diff options
-rw-r--r-- | drivers/crypto/hifn_795x.c | 205 |
1 files changed, 104 insertions, 101 deletions
diff --git a/drivers/crypto/hifn_795x.c b/drivers/crypto/hifn_795x.c index d6f042370d45..c9fe18d5348e 100644 --- a/drivers/crypto/hifn_795x.c +++ b/drivers/crypto/hifn_795x.c | |||
@@ -1168,109 +1168,15 @@ static int hifn_setup_crypto_command(struct hifn_device *dev, | |||
1168 | return cmd_len; | 1168 | return cmd_len; |
1169 | } | 1169 | } |
1170 | 1170 | ||
1171 | static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page, | 1171 | static int hifn_setup_cmd_desc(struct hifn_device *dev, |
1172 | unsigned int offset, unsigned int size) | 1172 | struct hifn_context *ctx, void *priv, unsigned int nbytes) |
1173 | { | ||
1174 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | ||
1175 | int idx; | ||
1176 | dma_addr_t addr; | ||
1177 | |||
1178 | addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_TODEVICE); | ||
1179 | |||
1180 | idx = dma->srci; | ||
1181 | |||
1182 | dma->srcr[idx].p = __cpu_to_le32(addr); | ||
1183 | dma->srcr[idx].l = __cpu_to_le32(size | HIFN_D_VALID | | ||
1184 | HIFN_D_MASKDONEIRQ | HIFN_D_NOINVALID | HIFN_D_LAST); | ||
1185 | |||
1186 | if (++idx == HIFN_D_SRC_RSIZE) { | ||
1187 | dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID | | ||
1188 | HIFN_D_JUMP | | ||
1189 | HIFN_D_MASKDONEIRQ | HIFN_D_LAST); | ||
1190 | idx = 0; | ||
1191 | } | ||
1192 | |||
1193 | dma->srci = idx; | ||
1194 | dma->srcu++; | ||
1195 | |||
1196 | if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) { | ||
1197 | hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); | ||
1198 | dev->flags |= HIFN_FLAG_SRC_BUSY; | ||
1199 | } | ||
1200 | |||
1201 | return size; | ||
1202 | } | ||
1203 | |||
1204 | static void hifn_setup_res_desc(struct hifn_device *dev) | ||
1205 | { | ||
1206 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | ||
1207 | |||
1208 | dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT | | ||
1209 | HIFN_D_VALID | HIFN_D_LAST); | ||
1210 | /* | ||
1211 | * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID | | ||
1212 | * HIFN_D_LAST | HIFN_D_NOINVALID); | ||
1213 | */ | ||
1214 | |||
1215 | if (++dma->resi == HIFN_D_RES_RSIZE) { | ||
1216 | dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID | | ||
1217 | HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST); | ||
1218 | dma->resi = 0; | ||
1219 | } | ||
1220 | |||
1221 | dma->resu++; | ||
1222 | |||
1223 | if (!(dev->flags & HIFN_FLAG_RES_BUSY)) { | ||
1224 | hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); | ||
1225 | dev->flags |= HIFN_FLAG_RES_BUSY; | ||
1226 | } | ||
1227 | } | ||
1228 | |||
1229 | static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page, | ||
1230 | unsigned offset, unsigned size) | ||
1231 | { | ||
1232 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | ||
1233 | int idx; | ||
1234 | dma_addr_t addr; | ||
1235 | |||
1236 | addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_FROMDEVICE); | ||
1237 | |||
1238 | idx = dma->dsti; | ||
1239 | dma->dstr[idx].p = __cpu_to_le32(addr); | ||
1240 | dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID | | ||
1241 | HIFN_D_MASKDONEIRQ | HIFN_D_NOINVALID | HIFN_D_LAST); | ||
1242 | |||
1243 | if (++idx == HIFN_D_DST_RSIZE) { | ||
1244 | dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID | | ||
1245 | HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | | ||
1246 | HIFN_D_LAST | HIFN_D_NOINVALID); | ||
1247 | idx = 0; | ||
1248 | } | ||
1249 | dma->dsti = idx; | ||
1250 | dma->dstu++; | ||
1251 | |||
1252 | if (!(dev->flags & HIFN_FLAG_DST_BUSY)) { | ||
1253 | hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); | ||
1254 | dev->flags |= HIFN_FLAG_DST_BUSY; | ||
1255 | } | ||
1256 | } | ||
1257 | |||
1258 | static int hifn_setup_dma(struct hifn_device *dev, struct page *spage, unsigned int soff, | ||
1259 | struct page *dpage, unsigned int doff, unsigned int nbytes, void *priv, | ||
1260 | struct hifn_context *ctx) | ||
1261 | { | 1173 | { |
1262 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | 1174 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; |
1263 | int cmd_len, sa_idx; | 1175 | int cmd_len, sa_idx; |
1264 | u8 *buf, *buf_pos; | 1176 | u8 *buf, *buf_pos; |
1265 | u16 mask; | 1177 | u16 mask; |
1266 | 1178 | ||
1267 | dprintk("%s: spage: %p, soffset: %u, dpage: %p, doffset: %u, nbytes: %u, priv: %p, ctx: %p.\n", | 1179 | sa_idx = dma->cmdi; |
1268 | dev->name, spage, soff, dpage, doff, nbytes, priv, ctx); | ||
1269 | |||
1270 | sa_idx = dma->resi; | ||
1271 | |||
1272 | hifn_setup_src_desc(dev, spage, soff, nbytes); | ||
1273 | |||
1274 | buf_pos = buf = dma->command_bufs[dma->cmdi]; | 1180 | buf_pos = buf = dma->command_bufs[dma->cmdi]; |
1275 | 1181 | ||
1276 | mask = 0; | 1182 | mask = 0; |
@@ -1372,16 +1278,113 @@ static int hifn_setup_dma(struct hifn_device *dev, struct page *spage, unsigned | |||
1372 | hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); | 1278 | hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA); |
1373 | dev->flags |= HIFN_FLAG_CMD_BUSY; | 1279 | dev->flags |= HIFN_FLAG_CMD_BUSY; |
1374 | } | 1280 | } |
1375 | |||
1376 | hifn_setup_dst_desc(dev, dpage, doff, nbytes); | ||
1377 | hifn_setup_res_desc(dev); | ||
1378 | |||
1379 | return 0; | 1281 | return 0; |
1380 | 1282 | ||
1381 | err_out: | 1283 | err_out: |
1382 | return -EINVAL; | 1284 | return -EINVAL; |
1383 | } | 1285 | } |
1384 | 1286 | ||
1287 | static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page, | ||
1288 | unsigned int offset, unsigned int size) | ||
1289 | { | ||
1290 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | ||
1291 | int idx; | ||
1292 | dma_addr_t addr; | ||
1293 | |||
1294 | addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_TODEVICE); | ||
1295 | |||
1296 | idx = dma->srci; | ||
1297 | |||
1298 | dma->srcr[idx].p = __cpu_to_le32(addr); | ||
1299 | dma->srcr[idx].l = __cpu_to_le32(size | HIFN_D_VALID | | ||
1300 | HIFN_D_MASKDONEIRQ | HIFN_D_NOINVALID | HIFN_D_LAST); | ||
1301 | |||
1302 | if (++idx == HIFN_D_SRC_RSIZE) { | ||
1303 | dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID | | ||
1304 | HIFN_D_JUMP | | ||
1305 | HIFN_D_MASKDONEIRQ | HIFN_D_LAST); | ||
1306 | idx = 0; | ||
1307 | } | ||
1308 | |||
1309 | dma->srci = idx; | ||
1310 | dma->srcu++; | ||
1311 | |||
1312 | if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) { | ||
1313 | hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA); | ||
1314 | dev->flags |= HIFN_FLAG_SRC_BUSY; | ||
1315 | } | ||
1316 | |||
1317 | return size; | ||
1318 | } | ||
1319 | |||
1320 | static void hifn_setup_res_desc(struct hifn_device *dev) | ||
1321 | { | ||
1322 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | ||
1323 | |||
1324 | dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT | | ||
1325 | HIFN_D_VALID | HIFN_D_LAST); | ||
1326 | /* | ||
1327 | * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID | | ||
1328 | * HIFN_D_LAST | HIFN_D_NOINVALID); | ||
1329 | */ | ||
1330 | |||
1331 | if (++dma->resi == HIFN_D_RES_RSIZE) { | ||
1332 | dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID | | ||
1333 | HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST); | ||
1334 | dma->resi = 0; | ||
1335 | } | ||
1336 | |||
1337 | dma->resu++; | ||
1338 | |||
1339 | if (!(dev->flags & HIFN_FLAG_RES_BUSY)) { | ||
1340 | hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA); | ||
1341 | dev->flags |= HIFN_FLAG_RES_BUSY; | ||
1342 | } | ||
1343 | } | ||
1344 | |||
1345 | static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page, | ||
1346 | unsigned offset, unsigned size) | ||
1347 | { | ||
1348 | struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt; | ||
1349 | int idx; | ||
1350 | dma_addr_t addr; | ||
1351 | |||
1352 | addr = pci_map_page(dev->pdev, page, offset, size, PCI_DMA_FROMDEVICE); | ||
1353 | |||
1354 | idx = dma->dsti; | ||
1355 | dma->dstr[idx].p = __cpu_to_le32(addr); | ||
1356 | dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID | | ||
1357 | HIFN_D_MASKDONEIRQ | HIFN_D_NOINVALID | HIFN_D_LAST); | ||
1358 | |||
1359 | if (++idx == HIFN_D_DST_RSIZE) { | ||
1360 | dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID | | ||
1361 | HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | | ||
1362 | HIFN_D_LAST | HIFN_D_NOINVALID); | ||
1363 | idx = 0; | ||
1364 | } | ||
1365 | dma->dsti = idx; | ||
1366 | dma->dstu++; | ||
1367 | |||
1368 | if (!(dev->flags & HIFN_FLAG_DST_BUSY)) { | ||
1369 | hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA); | ||
1370 | dev->flags |= HIFN_FLAG_DST_BUSY; | ||
1371 | } | ||
1372 | } | ||
1373 | |||
1374 | static int hifn_setup_dma(struct hifn_device *dev, struct page *spage, unsigned int soff, | ||
1375 | struct page *dpage, unsigned int doff, unsigned int nbytes, void *priv, | ||
1376 | struct hifn_context *ctx) | ||
1377 | { | ||
1378 | dprintk("%s: spage: %p, soffset: %u, dpage: %p, doffset: %u, nbytes: %u, priv: %p, ctx: %p.\n", | ||
1379 | dev->name, spage, soff, dpage, doff, nbytes, priv, ctx); | ||
1380 | |||
1381 | hifn_setup_src_desc(dev, spage, soff, nbytes); | ||
1382 | hifn_setup_cmd_desc(dev, ctx, priv, nbytes); | ||
1383 | hifn_setup_dst_desc(dev, dpage, doff, nbytes); | ||
1384 | hifn_setup_res_desc(dev); | ||
1385 | return 0; | ||
1386 | } | ||
1387 | |||
1385 | static int ablkcipher_walk_init(struct ablkcipher_walk *w, | 1388 | static int ablkcipher_walk_init(struct ablkcipher_walk *w, |
1386 | int num, gfp_t gfp_flags) | 1389 | int num, gfp_t gfp_flags) |
1387 | { | 1390 | { |