diff options
-rw-r--r-- | drivers/net/bnx2.c | 146 | ||||
-rw-r--r-- | drivers/net/bnx2.h | 20 |
2 files changed, 84 insertions, 82 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 5605d419128e..255197be35c1 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c | |||
@@ -296,7 +296,7 @@ bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) | |||
296 | u32 val1; | 296 | u32 val1; |
297 | int i, ret; | 297 | int i, ret; |
298 | 298 | ||
299 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | 299 | if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { |
300 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); | 300 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); |
301 | val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; | 301 | val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; |
302 | 302 | ||
@@ -334,7 +334,7 @@ bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val) | |||
334 | ret = 0; | 334 | ret = 0; |
335 | } | 335 | } |
336 | 336 | ||
337 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | 337 | if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { |
338 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); | 338 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); |
339 | val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; | 339 | val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; |
340 | 340 | ||
@@ -353,7 +353,7 @@ bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) | |||
353 | u32 val1; | 353 | u32 val1; |
354 | int i, ret; | 354 | int i, ret; |
355 | 355 | ||
356 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | 356 | if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { |
357 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); | 357 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); |
358 | val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; | 358 | val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL; |
359 | 359 | ||
@@ -383,7 +383,7 @@ bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val) | |||
383 | else | 383 | else |
384 | ret = 0; | 384 | ret = 0; |
385 | 385 | ||
386 | if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) { | 386 | if (bp->phy_flags & BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING) { |
387 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); | 387 | val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE); |
388 | val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; | 388 | val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL; |
389 | 389 | ||
@@ -634,7 +634,7 @@ bnx2_report_fw_link(struct bnx2 *bp) | |||
634 | { | 634 | { |
635 | u32 fw_link_status = 0; | 635 | u32 fw_link_status = 0; |
636 | 636 | ||
637 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) | 637 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
638 | return; | 638 | return; |
639 | 639 | ||
640 | if (bp->link_up) { | 640 | if (bp->link_up) { |
@@ -676,7 +676,7 @@ bnx2_report_fw_link(struct bnx2 *bp) | |||
676 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); | 676 | bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); |
677 | 677 | ||
678 | if (!(bmsr & BMSR_ANEGCOMPLETE) || | 678 | if (!(bmsr & BMSR_ANEGCOMPLETE) || |
679 | bp->phy_flags & PHY_PARALLEL_DETECT_FLAG) | 679 | bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) |
680 | fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET; | 680 | fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET; |
681 | else | 681 | else |
682 | fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE; | 682 | fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE; |
@@ -692,7 +692,7 @@ static char * | |||
692 | bnx2_xceiver_str(struct bnx2 *bp) | 692 | bnx2_xceiver_str(struct bnx2 *bp) |
693 | { | 693 | { |
694 | return ((bp->phy_port == PORT_FIBRE) ? "SerDes" : | 694 | return ((bp->phy_port == PORT_FIBRE) ? "SerDes" : |
695 | ((bp->phy_flags & PHY_SERDES_FLAG) ? "Remote Copper" : | 695 | ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) ? "Remote Copper" : |
696 | "Copper")); | 696 | "Copper")); |
697 | } | 697 | } |
698 | 698 | ||
@@ -752,7 +752,7 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp) | |||
752 | return; | 752 | return; |
753 | } | 753 | } |
754 | 754 | ||
755 | if ((bp->phy_flags & PHY_SERDES_FLAG) && | 755 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
756 | (CHIP_NUM(bp) == CHIP_NUM_5708)) { | 756 | (CHIP_NUM(bp) == CHIP_NUM_5708)) { |
757 | u32 val; | 757 | u32 val; |
758 | 758 | ||
@@ -767,7 +767,7 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp) | |||
767 | bnx2_read_phy(bp, bp->mii_adv, &local_adv); | 767 | bnx2_read_phy(bp, bp->mii_adv, &local_adv); |
768 | bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); | 768 | bnx2_read_phy(bp, bp->mii_lpa, &remote_adv); |
769 | 769 | ||
770 | if (bp->phy_flags & PHY_SERDES_FLAG) { | 770 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
771 | u32 new_local_adv = 0; | 771 | u32 new_local_adv = 0; |
772 | u32 new_remote_adv = 0; | 772 | u32 new_remote_adv = 0; |
773 | 773 | ||
@@ -1050,7 +1050,7 @@ bnx2_set_mac_link(struct bnx2 *bp) | |||
1050 | static void | 1050 | static void |
1051 | bnx2_enable_bmsr1(struct bnx2 *bp) | 1051 | bnx2_enable_bmsr1(struct bnx2 *bp) |
1052 | { | 1052 | { |
1053 | if ((bp->phy_flags & PHY_SERDES_FLAG) && | 1053 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
1054 | (CHIP_NUM(bp) == CHIP_NUM_5709)) | 1054 | (CHIP_NUM(bp) == CHIP_NUM_5709)) |
1055 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | 1055 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, |
1056 | MII_BNX2_BLK_ADDR_GP_STATUS); | 1056 | MII_BNX2_BLK_ADDR_GP_STATUS); |
@@ -1059,7 +1059,7 @@ bnx2_enable_bmsr1(struct bnx2 *bp) | |||
1059 | static void | 1059 | static void |
1060 | bnx2_disable_bmsr1(struct bnx2 *bp) | 1060 | bnx2_disable_bmsr1(struct bnx2 *bp) |
1061 | { | 1061 | { |
1062 | if ((bp->phy_flags & PHY_SERDES_FLAG) && | 1062 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
1063 | (CHIP_NUM(bp) == CHIP_NUM_5709)) | 1063 | (CHIP_NUM(bp) == CHIP_NUM_5709)) |
1064 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, | 1064 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, |
1065 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); | 1065 | MII_BNX2_BLK_ADDR_COMBO_IEEEB0); |
@@ -1071,7 +1071,7 @@ bnx2_test_and_enable_2g5(struct bnx2 *bp) | |||
1071 | u32 up1; | 1071 | u32 up1; |
1072 | int ret = 1; | 1072 | int ret = 1; |
1073 | 1073 | ||
1074 | if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) | 1074 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
1075 | return 0; | 1075 | return 0; |
1076 | 1076 | ||
1077 | if (bp->autoneg & AUTONEG_SPEED) | 1077 | if (bp->autoneg & AUTONEG_SPEED) |
@@ -1100,7 +1100,7 @@ bnx2_test_and_disable_2g5(struct bnx2 *bp) | |||
1100 | u32 up1; | 1100 | u32 up1; |
1101 | int ret = 0; | 1101 | int ret = 0; |
1102 | 1102 | ||
1103 | if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) | 1103 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
1104 | return 0; | 1104 | return 0; |
1105 | 1105 | ||
1106 | if (CHIP_NUM(bp) == CHIP_NUM_5709) | 1106 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
@@ -1125,7 +1125,7 @@ bnx2_enable_forced_2g5(struct bnx2 *bp) | |||
1125 | { | 1125 | { |
1126 | u32 bmcr; | 1126 | u32 bmcr; |
1127 | 1127 | ||
1128 | if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) | 1128 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
1129 | return; | 1129 | return; |
1130 | 1130 | ||
1131 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { | 1131 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
@@ -1160,7 +1160,7 @@ bnx2_disable_forced_2g5(struct bnx2 *bp) | |||
1160 | { | 1160 | { |
1161 | u32 bmcr; | 1161 | u32 bmcr; |
1162 | 1162 | ||
1163 | if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) | 1163 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
1164 | return; | 1164 | return; |
1165 | 1165 | ||
1166 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { | 1166 | if (CHIP_NUM(bp) == CHIP_NUM_5709) { |
@@ -1210,7 +1210,7 @@ bnx2_set_link(struct bnx2 *bp) | |||
1210 | return 0; | 1210 | return 0; |
1211 | } | 1211 | } |
1212 | 1212 | ||
1213 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) | 1213 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
1214 | return 0; | 1214 | return 0; |
1215 | 1215 | ||
1216 | link_up = bp->link_up; | 1216 | link_up = bp->link_up; |
@@ -1220,13 +1220,13 @@ bnx2_set_link(struct bnx2 *bp) | |||
1220 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); | 1220 | bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr); |
1221 | bnx2_disable_bmsr1(bp); | 1221 | bnx2_disable_bmsr1(bp); |
1222 | 1222 | ||
1223 | if ((bp->phy_flags & PHY_SERDES_FLAG) && | 1223 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
1224 | (CHIP_NUM(bp) == CHIP_NUM_5706)) { | 1224 | (CHIP_NUM(bp) == CHIP_NUM_5706)) { |
1225 | u32 val; | 1225 | u32 val; |
1226 | 1226 | ||
1227 | if (bp->phy_flags & PHY_FORCED_DOWN_FLAG) { | 1227 | if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) { |
1228 | bnx2_5706s_force_link_dn(bp, 0); | 1228 | bnx2_5706s_force_link_dn(bp, 0); |
1229 | bp->phy_flags &= ~PHY_FORCED_DOWN_FLAG; | 1229 | bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN; |
1230 | } | 1230 | } |
1231 | val = REG_RD(bp, BNX2_EMAC_STATUS); | 1231 | val = REG_RD(bp, BNX2_EMAC_STATUS); |
1232 | if (val & BNX2_EMAC_STATUS_LINK) | 1232 | if (val & BNX2_EMAC_STATUS_LINK) |
@@ -1238,7 +1238,7 @@ bnx2_set_link(struct bnx2 *bp) | |||
1238 | if (bmsr & BMSR_LSTATUS) { | 1238 | if (bmsr & BMSR_LSTATUS) { |
1239 | bp->link_up = 1; | 1239 | bp->link_up = 1; |
1240 | 1240 | ||
1241 | if (bp->phy_flags & PHY_SERDES_FLAG) { | 1241 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
1242 | if (CHIP_NUM(bp) == CHIP_NUM_5706) | 1242 | if (CHIP_NUM(bp) == CHIP_NUM_5706) |
1243 | bnx2_5706s_linkup(bp); | 1243 | bnx2_5706s_linkup(bp); |
1244 | else if (CHIP_NUM(bp) == CHIP_NUM_5708) | 1244 | else if (CHIP_NUM(bp) == CHIP_NUM_5708) |
@@ -1252,18 +1252,18 @@ bnx2_set_link(struct bnx2 *bp) | |||
1252 | bnx2_resolve_flow_ctrl(bp); | 1252 | bnx2_resolve_flow_ctrl(bp); |
1253 | } | 1253 | } |
1254 | else { | 1254 | else { |
1255 | if ((bp->phy_flags & PHY_SERDES_FLAG) && | 1255 | if ((bp->phy_flags & BNX2_PHY_FLAG_SERDES) && |
1256 | (bp->autoneg & AUTONEG_SPEED)) | 1256 | (bp->autoneg & AUTONEG_SPEED)) |
1257 | bnx2_disable_forced_2g5(bp); | 1257 | bnx2_disable_forced_2g5(bp); |
1258 | 1258 | ||
1259 | if (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG) { | 1259 | if (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT) { |
1260 | u32 bmcr; | 1260 | u32 bmcr; |
1261 | 1261 | ||
1262 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); | 1262 | bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); |
1263 | bmcr |= BMCR_ANENABLE; | 1263 | bmcr |= BMCR_ANENABLE; |
1264 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); | 1264 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); |
1265 | 1265 | ||
1266 | bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; | 1266 | bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; |
1267 | } | 1267 | } |
1268 | bp->link_up = 0; | 1268 | bp->link_up = 0; |
1269 | } | 1269 | } |
@@ -1309,7 +1309,7 @@ bnx2_phy_get_pause_adv(struct bnx2 *bp) | |||
1309 | if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) == | 1309 | if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) == |
1310 | (FLOW_CTRL_RX | FLOW_CTRL_TX)) { | 1310 | (FLOW_CTRL_RX | FLOW_CTRL_TX)) { |
1311 | 1311 | ||
1312 | if (bp->phy_flags & PHY_SERDES_FLAG) { | 1312 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
1313 | adv = ADVERTISE_1000XPAUSE; | 1313 | adv = ADVERTISE_1000XPAUSE; |
1314 | } | 1314 | } |
1315 | else { | 1315 | else { |
@@ -1317,7 +1317,7 @@ bnx2_phy_get_pause_adv(struct bnx2 *bp) | |||
1317 | } | 1317 | } |
1318 | } | 1318 | } |
1319 | else if (bp->req_flow_ctrl & FLOW_CTRL_TX) { | 1319 | else if (bp->req_flow_ctrl & FLOW_CTRL_TX) { |
1320 | if (bp->phy_flags & PHY_SERDES_FLAG) { | 1320 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
1321 | adv = ADVERTISE_1000XPSE_ASYM; | 1321 | adv = ADVERTISE_1000XPSE_ASYM; |
1322 | } | 1322 | } |
1323 | else { | 1323 | else { |
@@ -1325,7 +1325,7 @@ bnx2_phy_get_pause_adv(struct bnx2 *bp) | |||
1325 | } | 1325 | } |
1326 | } | 1326 | } |
1327 | else if (bp->req_flow_ctrl & FLOW_CTRL_RX) { | 1327 | else if (bp->req_flow_ctrl & FLOW_CTRL_RX) { |
1328 | if (bp->phy_flags & PHY_SERDES_FLAG) { | 1328 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
1329 | adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; | 1329 | adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM; |
1330 | } | 1330 | } |
1331 | else { | 1331 | else { |
@@ -1400,7 +1400,7 @@ bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port) | |||
1400 | u32 adv, bmcr; | 1400 | u32 adv, bmcr; |
1401 | u32 new_adv = 0; | 1401 | u32 new_adv = 0; |
1402 | 1402 | ||
1403 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) | 1403 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
1404 | return (bnx2_setup_remote_phy(bp, port)); | 1404 | return (bnx2_setup_remote_phy(bp, port)); |
1405 | 1405 | ||
1406 | if (!(bp->autoneg & AUTONEG_SPEED)) { | 1406 | if (!(bp->autoneg & AUTONEG_SPEED)) { |
@@ -1510,7 +1510,7 @@ bnx2_setup_serdes_phy(struct bnx2 *bp, u8 port) | |||
1510 | } | 1510 | } |
1511 | 1511 | ||
1512 | #define ETHTOOL_ALL_FIBRE_SPEED \ | 1512 | #define ETHTOOL_ALL_FIBRE_SPEED \ |
1513 | (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) ? \ | 1513 | (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) ? \ |
1514 | (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\ | 1514 | (ADVERTISED_2500baseX_Full | ADVERTISED_1000baseT_Full) :\ |
1515 | (ADVERTISED_1000baseT_Full) | 1515 | (ADVERTISED_1000baseT_Full) |
1516 | 1516 | ||
@@ -1574,12 +1574,12 @@ bnx2_set_default_remote_link(struct bnx2 *bp) | |||
1574 | static void | 1574 | static void |
1575 | bnx2_set_default_link(struct bnx2 *bp) | 1575 | bnx2_set_default_link(struct bnx2 *bp) |
1576 | { | 1576 | { |
1577 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) | 1577 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
1578 | return bnx2_set_default_remote_link(bp); | 1578 | return bnx2_set_default_remote_link(bp); |
1579 | 1579 | ||
1580 | bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; | 1580 | bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL; |
1581 | bp->req_line_speed = 0; | 1581 | bp->req_line_speed = 0; |
1582 | if (bp->phy_flags & PHY_SERDES_FLAG) { | 1582 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
1583 | u32 reg; | 1583 | u32 reg; |
1584 | 1584 | ||
1585 | bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; | 1585 | bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg; |
@@ -1809,7 +1809,7 @@ bnx2_setup_phy(struct bnx2 *bp, u8 port) | |||
1809 | if (bp->loopback == MAC_LOOPBACK) | 1809 | if (bp->loopback == MAC_LOOPBACK) |
1810 | return 0; | 1810 | return 0; |
1811 | 1811 | ||
1812 | if (bp->phy_flags & PHY_SERDES_FLAG) { | 1812 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
1813 | return (bnx2_setup_serdes_phy(bp, port)); | 1813 | return (bnx2_setup_serdes_phy(bp, port)); |
1814 | } | 1814 | } |
1815 | else { | 1815 | else { |
@@ -1844,7 +1844,7 @@ bnx2_init_5709s_phy(struct bnx2 *bp) | |||
1844 | 1844 | ||
1845 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); | 1845 | bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G); |
1846 | bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val); | 1846 | bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val); |
1847 | if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) | 1847 | if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) |
1848 | val |= BCM5708S_UP1_2G5; | 1848 | val |= BCM5708S_UP1_2G5; |
1849 | else | 1849 | else |
1850 | val &= ~BCM5708S_UP1_2G5; | 1850 | val &= ~BCM5708S_UP1_2G5; |
@@ -1887,7 +1887,7 @@ bnx2_init_5708s_phy(struct bnx2 *bp) | |||
1887 | val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN; | 1887 | val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN; |
1888 | bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val); | 1888 | bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val); |
1889 | 1889 | ||
1890 | if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) { | 1890 | if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) { |
1891 | bnx2_read_phy(bp, BCM5708S_UP1, &val); | 1891 | bnx2_read_phy(bp, BCM5708S_UP1, &val); |
1892 | val |= BCM5708S_UP1_2G5; | 1892 | val |= BCM5708S_UP1_2G5; |
1893 | bnx2_write_phy(bp, BCM5708S_UP1, val); | 1893 | bnx2_write_phy(bp, BCM5708S_UP1, val); |
@@ -1929,7 +1929,7 @@ bnx2_init_5706s_phy(struct bnx2 *bp) | |||
1929 | { | 1929 | { |
1930 | bnx2_reset_phy(bp); | 1930 | bnx2_reset_phy(bp); |
1931 | 1931 | ||
1932 | bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; | 1932 | bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; |
1933 | 1933 | ||
1934 | if (CHIP_NUM(bp) == CHIP_NUM_5706) | 1934 | if (CHIP_NUM(bp) == CHIP_NUM_5706) |
1935 | REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300); | 1935 | REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300); |
@@ -1968,7 +1968,7 @@ bnx2_init_copper_phy(struct bnx2 *bp) | |||
1968 | 1968 | ||
1969 | bnx2_reset_phy(bp); | 1969 | bnx2_reset_phy(bp); |
1970 | 1970 | ||
1971 | if (bp->phy_flags & PHY_CRC_FIX_FLAG) { | 1971 | if (bp->phy_flags & BNX2_PHY_FLAG_CRC_FIX) { |
1972 | bnx2_write_phy(bp, 0x18, 0x0c00); | 1972 | bnx2_write_phy(bp, 0x18, 0x0c00); |
1973 | bnx2_write_phy(bp, 0x17, 0x000a); | 1973 | bnx2_write_phy(bp, 0x17, 0x000a); |
1974 | bnx2_write_phy(bp, 0x15, 0x310b); | 1974 | bnx2_write_phy(bp, 0x15, 0x310b); |
@@ -1979,7 +1979,7 @@ bnx2_init_copper_phy(struct bnx2 *bp) | |||
1979 | bnx2_write_phy(bp, 0x18, 0x0400); | 1979 | bnx2_write_phy(bp, 0x18, 0x0400); |
1980 | } | 1980 | } |
1981 | 1981 | ||
1982 | if (bp->phy_flags & PHY_DIS_EARLY_DAC_FLAG) { | 1982 | if (bp->phy_flags & BNX2_PHY_FLAG_DIS_EARLY_DAC) { |
1983 | bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, | 1983 | bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS, |
1984 | MII_BNX2_DSP_EXPAND_REG | 0x8); | 1984 | MII_BNX2_DSP_EXPAND_REG | 0x8); |
1985 | bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); | 1985 | bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val); |
@@ -2019,8 +2019,8 @@ bnx2_init_phy(struct bnx2 *bp) | |||
2019 | u32 val; | 2019 | u32 val; |
2020 | int rc = 0; | 2020 | int rc = 0; |
2021 | 2021 | ||
2022 | bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG; | 2022 | bp->phy_flags &= ~BNX2_PHY_FLAG_INT_MODE_MASK; |
2023 | bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG; | 2023 | bp->phy_flags |= BNX2_PHY_FLAG_INT_MODE_LINK_READY; |
2024 | 2024 | ||
2025 | bp->mii_bmcr = MII_BMCR; | 2025 | bp->mii_bmcr = MII_BMCR; |
2026 | bp->mii_bmsr = MII_BMSR; | 2026 | bp->mii_bmsr = MII_BMSR; |
@@ -2030,7 +2030,7 @@ bnx2_init_phy(struct bnx2 *bp) | |||
2030 | 2030 | ||
2031 | REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); | 2031 | REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); |
2032 | 2032 | ||
2033 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) | 2033 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
2034 | goto setup_phy; | 2034 | goto setup_phy; |
2035 | 2035 | ||
2036 | bnx2_read_phy(bp, MII_PHYSID1, &val); | 2036 | bnx2_read_phy(bp, MII_PHYSID1, &val); |
@@ -2038,7 +2038,7 @@ bnx2_init_phy(struct bnx2 *bp) | |||
2038 | bnx2_read_phy(bp, MII_PHYSID2, &val); | 2038 | bnx2_read_phy(bp, MII_PHYSID2, &val); |
2039 | bp->phy_id |= val & 0xffff; | 2039 | bp->phy_id |= val & 0xffff; |
2040 | 2040 | ||
2041 | if (bp->phy_flags & PHY_SERDES_FLAG) { | 2041 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
2042 | if (CHIP_NUM(bp) == CHIP_NUM_5706) | 2042 | if (CHIP_NUM(bp) == CHIP_NUM_5706) |
2043 | rc = bnx2_init_5706s_phy(bp); | 2043 | rc = bnx2_init_5706s_phy(bp); |
2044 | else if (CHIP_NUM(bp) == CHIP_NUM_5708) | 2044 | else if (CHIP_NUM(bp) == CHIP_NUM_5708) |
@@ -4140,8 +4140,8 @@ bnx2_init_remote_phy(struct bnx2 *bp) | |||
4140 | { | 4140 | { |
4141 | u32 val; | 4141 | u32 val; |
4142 | 4142 | ||
4143 | bp->phy_flags &= ~REMOTE_PHY_CAP_FLAG; | 4143 | bp->phy_flags &= ~BNX2_PHY_FLAG_REMOTE_PHY_CAP; |
4144 | if (!(bp->phy_flags & PHY_SERDES_FLAG)) | 4144 | if (!(bp->phy_flags & BNX2_PHY_FLAG_SERDES)) |
4145 | return; | 4145 | return; |
4146 | 4146 | ||
4147 | val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_CAP_MB); | 4147 | val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_CAP_MB); |
@@ -4149,7 +4149,7 @@ bnx2_init_remote_phy(struct bnx2 *bp) | |||
4149 | return; | 4149 | return; |
4150 | 4150 | ||
4151 | if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) { | 4151 | if (val & BNX2_FW_CAP_REMOTE_PHY_CAPABLE) { |
4152 | bp->phy_flags |= REMOTE_PHY_CAP_FLAG; | 4152 | bp->phy_flags |= BNX2_PHY_FLAG_REMOTE_PHY_CAP; |
4153 | 4153 | ||
4154 | val = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS); | 4154 | val = REG_RD_IND(bp, bp->shmem_base + BNX2_LINK_STATUS); |
4155 | if (val & BNX2_LINK_STATUS_SERDES_LINK) | 4155 | if (val & BNX2_LINK_STATUS_SERDES_LINK) |
@@ -4270,7 +4270,8 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code) | |||
4270 | spin_lock_bh(&bp->phy_lock); | 4270 | spin_lock_bh(&bp->phy_lock); |
4271 | old_port = bp->phy_port; | 4271 | old_port = bp->phy_port; |
4272 | bnx2_init_remote_phy(bp); | 4272 | bnx2_init_remote_phy(bp); |
4273 | if ((bp->phy_flags & REMOTE_PHY_CAP_FLAG) && old_port != bp->phy_port) | 4273 | if ((bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) && |
4274 | old_port != bp->phy_port) | ||
4274 | bnx2_set_default_remote_link(bp); | 4275 | bnx2_set_default_remote_link(bp); |
4275 | spin_unlock_bh(&bp->phy_lock); | 4276 | spin_unlock_bh(&bp->phy_lock); |
4276 | 4277 | ||
@@ -5083,7 +5084,7 @@ bnx2_run_loopback(struct bnx2 *bp, int loopback_mode) | |||
5083 | bnx2_set_mac_loopback(bp); | 5084 | bnx2_set_mac_loopback(bp); |
5084 | } | 5085 | } |
5085 | else if (loopback_mode == BNX2_PHY_LOOPBACK) { | 5086 | else if (loopback_mode == BNX2_PHY_LOOPBACK) { |
5086 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) | 5087 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
5087 | return 0; | 5088 | return 0; |
5088 | 5089 | ||
5089 | bp->loopback = PHY_LOOPBACK; | 5090 | bp->loopback = PHY_LOOPBACK; |
@@ -5253,7 +5254,7 @@ bnx2_test_link(struct bnx2 *bp) | |||
5253 | { | 5254 | { |
5254 | u32 bmsr; | 5255 | u32 bmsr; |
5255 | 5256 | ||
5256 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) { | 5257 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { |
5257 | if (bp->link_up) | 5258 | if (bp->link_up) |
5258 | return 0; | 5259 | return 0; |
5259 | return -ENODEV; | 5260 | return -ENODEV; |
@@ -5335,9 +5336,9 @@ bnx2_5706_serdes_timer(struct bnx2 *bp) | |||
5335 | int check_link = 1; | 5336 | int check_link = 1; |
5336 | 5337 | ||
5337 | spin_lock(&bp->phy_lock); | 5338 | spin_lock(&bp->phy_lock); |
5338 | if (bp->phy_flags & PHY_FORCED_DOWN_FLAG) { | 5339 | if (bp->phy_flags & BNX2_PHY_FLAG_FORCED_DOWN) { |
5339 | bnx2_5706s_force_link_dn(bp, 0); | 5340 | bnx2_5706s_force_link_dn(bp, 0); |
5340 | bp->phy_flags &= ~PHY_FORCED_DOWN_FLAG; | 5341 | bp->phy_flags &= ~BNX2_PHY_FLAG_FORCED_DOWN; |
5341 | spin_unlock(&bp->phy_lock); | 5342 | spin_unlock(&bp->phy_lock); |
5342 | return; | 5343 | return; |
5343 | } | 5344 | } |
@@ -5357,12 +5358,12 @@ bnx2_5706_serdes_timer(struct bnx2 *bp) | |||
5357 | bmcr &= ~BMCR_ANENABLE; | 5358 | bmcr &= ~BMCR_ANENABLE; |
5358 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; | 5359 | bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX; |
5359 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); | 5360 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); |
5360 | bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG; | 5361 | bp->phy_flags |= BNX2_PHY_FLAG_PARALLEL_DETECT; |
5361 | } | 5362 | } |
5362 | } | 5363 | } |
5363 | } | 5364 | } |
5364 | else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && | 5365 | else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) && |
5365 | (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) { | 5366 | (bp->phy_flags & BNX2_PHY_FLAG_PARALLEL_DETECT)) { |
5366 | u32 phy2; | 5367 | u32 phy2; |
5367 | 5368 | ||
5368 | check_link = 0; | 5369 | check_link = 0; |
@@ -5375,7 +5376,7 @@ bnx2_5706_serdes_timer(struct bnx2 *bp) | |||
5375 | bmcr |= BMCR_ANENABLE; | 5376 | bmcr |= BMCR_ANENABLE; |
5376 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); | 5377 | bnx2_write_phy(bp, bp->mii_bmcr, bmcr); |
5377 | 5378 | ||
5378 | bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; | 5379 | bp->phy_flags &= ~BNX2_PHY_FLAG_PARALLEL_DETECT; |
5379 | } | 5380 | } |
5380 | } else | 5381 | } else |
5381 | bp->current_interval = bp->timer_interval; | 5382 | bp->current_interval = bp->timer_interval; |
@@ -5389,7 +5390,7 @@ bnx2_5706_serdes_timer(struct bnx2 *bp) | |||
5389 | 5390 | ||
5390 | if (val & MISC_SHDW_AN_DBG_NOSYNC) { | 5391 | if (val & MISC_SHDW_AN_DBG_NOSYNC) { |
5391 | bnx2_5706s_force_link_dn(bp, 1); | 5392 | bnx2_5706s_force_link_dn(bp, 1); |
5392 | bp->phy_flags |= PHY_FORCED_DOWN_FLAG; | 5393 | bp->phy_flags |= BNX2_PHY_FLAG_FORCED_DOWN; |
5393 | } | 5394 | } |
5394 | } | 5395 | } |
5395 | spin_unlock(&bp->phy_lock); | 5396 | spin_unlock(&bp->phy_lock); |
@@ -5398,10 +5399,10 @@ bnx2_5706_serdes_timer(struct bnx2 *bp) | |||
5398 | static void | 5399 | static void |
5399 | bnx2_5708_serdes_timer(struct bnx2 *bp) | 5400 | bnx2_5708_serdes_timer(struct bnx2 *bp) |
5400 | { | 5401 | { |
5401 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) | 5402 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
5402 | return; | 5403 | return; |
5403 | 5404 | ||
5404 | if ((bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) == 0) { | 5405 | if ((bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) == 0) { |
5405 | bp->serdes_an_pending = 0; | 5406 | bp->serdes_an_pending = 0; |
5406 | return; | 5407 | return; |
5407 | } | 5408 | } |
@@ -5448,7 +5449,7 @@ bnx2_timer(unsigned long data) | |||
5448 | REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | | 5449 | REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | |
5449 | BNX2_HC_COMMAND_STATS_NOW); | 5450 | BNX2_HC_COMMAND_STATS_NOW); |
5450 | 5451 | ||
5451 | if (bp->phy_flags & PHY_SERDES_FLAG) { | 5452 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
5452 | if (CHIP_NUM(bp) == CHIP_NUM_5706) | 5453 | if (CHIP_NUM(bp) == CHIP_NUM_5706) |
5453 | bnx2_5706_serdes_timer(bp); | 5454 | bnx2_5706_serdes_timer(bp); |
5454 | else | 5455 | else |
@@ -5962,7 +5963,7 @@ bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
5962 | int support_serdes = 0, support_copper = 0; | 5963 | int support_serdes = 0, support_copper = 0; |
5963 | 5964 | ||
5964 | cmd->supported = SUPPORTED_Autoneg; | 5965 | cmd->supported = SUPPORTED_Autoneg; |
5965 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) { | 5966 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { |
5966 | support_serdes = 1; | 5967 | support_serdes = 1; |
5967 | support_copper = 1; | 5968 | support_copper = 1; |
5968 | } else if (bp->phy_port == PORT_FIBRE) | 5969 | } else if (bp->phy_port == PORT_FIBRE) |
@@ -5973,7 +5974,7 @@ bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
5973 | if (support_serdes) { | 5974 | if (support_serdes) { |
5974 | cmd->supported |= SUPPORTED_1000baseT_Full | | 5975 | cmd->supported |= SUPPORTED_1000baseT_Full | |
5975 | SUPPORTED_FIBRE; | 5976 | SUPPORTED_FIBRE; |
5976 | if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) | 5977 | if (bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) |
5977 | cmd->supported |= SUPPORTED_2500baseX_Full; | 5978 | cmd->supported |= SUPPORTED_2500baseX_Full; |
5978 | 5979 | ||
5979 | } | 5980 | } |
@@ -6029,7 +6030,8 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
6029 | if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE) | 6030 | if (cmd->port != PORT_TP && cmd->port != PORT_FIBRE) |
6030 | goto err_out_unlock; | 6031 | goto err_out_unlock; |
6031 | 6032 | ||
6032 | if (cmd->port != bp->phy_port && !(bp->phy_flags & REMOTE_PHY_CAP_FLAG)) | 6033 | if (cmd->port != bp->phy_port && |
6034 | !(bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP)) | ||
6033 | goto err_out_unlock; | 6035 | goto err_out_unlock; |
6034 | 6036 | ||
6035 | if (cmd->autoneg == AUTONEG_ENABLE) { | 6037 | if (cmd->autoneg == AUTONEG_ENABLE) { |
@@ -6049,7 +6051,7 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
6049 | advertising = cmd->advertising; | 6051 | advertising = cmd->advertising; |
6050 | 6052 | ||
6051 | } else if (cmd->advertising == ADVERTISED_2500baseX_Full) { | 6053 | } else if (cmd->advertising == ADVERTISED_2500baseX_Full) { |
6052 | if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) || | 6054 | if (!(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE) || |
6053 | (cmd->port == PORT_TP)) | 6055 | (cmd->port == PORT_TP)) |
6054 | goto err_out_unlock; | 6056 | goto err_out_unlock; |
6055 | } else if (cmd->advertising == ADVERTISED_1000baseT_Full) | 6057 | } else if (cmd->advertising == ADVERTISED_1000baseT_Full) |
@@ -6072,7 +6074,7 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
6072 | goto err_out_unlock; | 6074 | goto err_out_unlock; |
6073 | 6075 | ||
6074 | if (cmd->speed == SPEED_2500 && | 6076 | if (cmd->speed == SPEED_2500 && |
6075 | !(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) | 6077 | !(bp->phy_flags & BNX2_PHY_FLAG_2_5G_CAPABLE)) |
6076 | goto err_out_unlock; | 6078 | goto err_out_unlock; |
6077 | } | 6079 | } |
6078 | else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500) | 6080 | else if (cmd->speed == SPEED_1000 || cmd->speed == SPEED_2500) |
@@ -6217,7 +6219,7 @@ bnx2_nway_reset(struct net_device *dev) | |||
6217 | 6219 | ||
6218 | spin_lock_bh(&bp->phy_lock); | 6220 | spin_lock_bh(&bp->phy_lock); |
6219 | 6221 | ||
6220 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) { | 6222 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) { |
6221 | int rc; | 6223 | int rc; |
6222 | 6224 | ||
6223 | rc = bnx2_setup_remote_phy(bp, bp->phy_port); | 6225 | rc = bnx2_setup_remote_phy(bp, bp->phy_port); |
@@ -6226,7 +6228,7 @@ bnx2_nway_reset(struct net_device *dev) | |||
6226 | } | 6228 | } |
6227 | 6229 | ||
6228 | /* Force a link down visible on the other side */ | 6230 | /* Force a link down visible on the other side */ |
6229 | if (bp->phy_flags & PHY_SERDES_FLAG) { | 6231 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
6230 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); | 6232 | bnx2_write_phy(bp, bp->mii_bmcr, BMCR_LOOPBACK); |
6231 | spin_unlock_bh(&bp->phy_lock); | 6233 | spin_unlock_bh(&bp->phy_lock); |
6232 | 6234 | ||
@@ -6838,7 +6840,7 @@ bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |||
6838 | case SIOCGMIIREG: { | 6840 | case SIOCGMIIREG: { |
6839 | u32 mii_regval; | 6841 | u32 mii_regval; |
6840 | 6842 | ||
6841 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) | 6843 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
6842 | return -EOPNOTSUPP; | 6844 | return -EOPNOTSUPP; |
6843 | 6845 | ||
6844 | if (!netif_running(dev)) | 6846 | if (!netif_running(dev)) |
@@ -6857,7 +6859,7 @@ bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |||
6857 | if (!capable(CAP_NET_ADMIN)) | 6859 | if (!capable(CAP_NET_ADMIN)) |
6858 | return -EPERM; | 6860 | return -EPERM; |
6859 | 6861 | ||
6860 | if (bp->phy_flags & REMOTE_PHY_CAP_FLAG) | 6862 | if (bp->phy_flags & BNX2_PHY_FLAG_REMOTE_PHY_CAP) |
6861 | return -EOPNOTSUPP; | 6863 | return -EOPNOTSUPP; |
6862 | 6864 | ||
6863 | if (!netif_running(dev)) | 6865 | if (!netif_running(dev)) |
@@ -6929,7 +6931,7 @@ bnx2_get_5709_media(struct bnx2 *bp) | |||
6929 | if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) | 6931 | if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) |
6930 | return; | 6932 | return; |
6931 | else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { | 6933 | else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) { |
6932 | bp->phy_flags |= PHY_SERDES_FLAG; | 6934 | bp->phy_flags |= BNX2_PHY_FLAG_SERDES; |
6933 | return; | 6935 | return; |
6934 | } | 6936 | } |
6935 | 6937 | ||
@@ -6943,7 +6945,7 @@ bnx2_get_5709_media(struct bnx2 *bp) | |||
6943 | case 0x4: | 6945 | case 0x4: |
6944 | case 0x5: | 6946 | case 0x5: |
6945 | case 0x6: | 6947 | case 0x6: |
6946 | bp->phy_flags |= PHY_SERDES_FLAG; | 6948 | bp->phy_flags |= BNX2_PHY_FLAG_SERDES; |
6947 | return; | 6949 | return; |
6948 | } | 6950 | } |
6949 | } else { | 6951 | } else { |
@@ -6951,7 +6953,7 @@ bnx2_get_5709_media(struct bnx2 *bp) | |||
6951 | case 0x1: | 6953 | case 0x1: |
6952 | case 0x2: | 6954 | case 0x2: |
6953 | case 0x4: | 6955 | case 0x4: |
6954 | bp->phy_flags |= PHY_SERDES_FLAG; | 6956 | bp->phy_flags |= BNX2_PHY_FLAG_SERDES; |
6955 | return; | 6957 | return; |
6956 | } | 6958 | } |
6957 | } | 6959 | } |
@@ -7260,10 +7262,10 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) | |||
7260 | if (CHIP_NUM(bp) == CHIP_NUM_5709) | 7262 | if (CHIP_NUM(bp) == CHIP_NUM_5709) |
7261 | bnx2_get_5709_media(bp); | 7263 | bnx2_get_5709_media(bp); |
7262 | else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) | 7264 | else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) |
7263 | bp->phy_flags |= PHY_SERDES_FLAG; | 7265 | bp->phy_flags |= BNX2_PHY_FLAG_SERDES; |
7264 | 7266 | ||
7265 | bp->phy_port = PORT_TP; | 7267 | bp->phy_port = PORT_TP; |
7266 | if (bp->phy_flags & PHY_SERDES_FLAG) { | 7268 | if (bp->phy_flags & BNX2_PHY_FLAG_SERDES) { |
7267 | bp->phy_port = PORT_FIBRE; | 7269 | bp->phy_port = PORT_FIBRE; |
7268 | reg = REG_RD_IND(bp, bp->shmem_base + | 7270 | reg = REG_RD_IND(bp, bp->shmem_base + |
7269 | BNX2_SHARED_HW_CFG_CONFIG); | 7271 | BNX2_SHARED_HW_CFG_CONFIG); |
@@ -7274,17 +7276,17 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev) | |||
7274 | if (CHIP_NUM(bp) != CHIP_NUM_5706) { | 7276 | if (CHIP_NUM(bp) != CHIP_NUM_5706) { |
7275 | bp->phy_addr = 2; | 7277 | bp->phy_addr = 2; |
7276 | if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) | 7278 | if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G) |
7277 | bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG; | 7279 | bp->phy_flags |= BNX2_PHY_FLAG_2_5G_CAPABLE; |
7278 | } | 7280 | } |
7279 | bnx2_init_remote_phy(bp); | 7281 | bnx2_init_remote_phy(bp); |
7280 | 7282 | ||
7281 | } else if (CHIP_NUM(bp) == CHIP_NUM_5706 || | 7283 | } else if (CHIP_NUM(bp) == CHIP_NUM_5706 || |
7282 | CHIP_NUM(bp) == CHIP_NUM_5708) | 7284 | CHIP_NUM(bp) == CHIP_NUM_5708) |
7283 | bp->phy_flags |= PHY_CRC_FIX_FLAG; | 7285 | bp->phy_flags |= BNX2_PHY_FLAG_CRC_FIX; |
7284 | else if (CHIP_NUM(bp) == CHIP_NUM_5709 && | 7286 | else if (CHIP_NUM(bp) == CHIP_NUM_5709 && |
7285 | (CHIP_REV(bp) == CHIP_REV_Ax || | 7287 | (CHIP_REV(bp) == CHIP_REV_Ax || |
7286 | CHIP_REV(bp) == CHIP_REV_Bx)) | 7288 | CHIP_REV(bp) == CHIP_REV_Bx)) |
7287 | bp->phy_flags |= PHY_DIS_EARLY_DAC_FLAG; | 7289 | bp->phy_flags |= BNX2_PHY_FLAG_DIS_EARLY_DAC; |
7288 | 7290 | ||
7289 | if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || | 7291 | if ((CHIP_ID(bp) == CHIP_ID_5708_A0) || |
7290 | (CHIP_ID(bp) == CHIP_ID_5708_B0) || | 7292 | (CHIP_ID(bp) == CHIP_ID_5708_B0) || |
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h index cd79b5cb01a8..54ce11afd9fe 100644 --- a/drivers/net/bnx2.h +++ b/drivers/net/bnx2.h | |||
@@ -6644,16 +6644,16 @@ struct bnx2 { | |||
6644 | spinlock_t indirect_lock; | 6644 | spinlock_t indirect_lock; |
6645 | 6645 | ||
6646 | u32 phy_flags; | 6646 | u32 phy_flags; |
6647 | #define PHY_SERDES_FLAG 1 | 6647 | #define BNX2_PHY_FLAG_SERDES 0x00000001 |
6648 | #define PHY_CRC_FIX_FLAG 2 | 6648 | #define BNX2_PHY_FLAG_CRC_FIX 0x00000002 |
6649 | #define PHY_PARALLEL_DETECT_FLAG 4 | 6649 | #define BNX2_PHY_FLAG_PARALLEL_DETECT 0x00000004 |
6650 | #define PHY_2_5G_CAPABLE_FLAG 8 | 6650 | #define BNX2_PHY_FLAG_2_5G_CAPABLE 0x00000008 |
6651 | #define PHY_INT_MODE_MASK_FLAG 0x300 | 6651 | #define BNX2_PHY_FLAG_INT_MODE_MASK 0x00000300 |
6652 | #define PHY_INT_MODE_AUTO_POLLING_FLAG 0x100 | 6652 | #define BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING 0x00000100 |
6653 | #define PHY_INT_MODE_LINK_READY_FLAG 0x200 | 6653 | #define BNX2_PHY_FLAG_INT_MODE_LINK_READY 0x00000200 |
6654 | #define PHY_DIS_EARLY_DAC_FLAG 0x400 | 6654 | #define BNX2_PHY_FLAG_DIS_EARLY_DAC 0x00000400 |
6655 | #define REMOTE_PHY_CAP_FLAG 0x800 | 6655 | #define BNX2_PHY_FLAG_REMOTE_PHY_CAP 0x00000800 |
6656 | #define PHY_FORCED_DOWN_FLAG 0x1000 | 6656 | #define BNX2_PHY_FLAG_FORCED_DOWN 0x00001000 |
6657 | 6657 | ||
6658 | u32 mii_bmcr; | 6658 | u32 mii_bmcr; |
6659 | u32 mii_bmsr; | 6659 | u32 mii_bmsr; |