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-rw-r--r--include/asm-blackfin/bfin5xx_spi.h2
-rw-r--r--include/asm-blackfin/mach-bf527/defBF52x_base.h2
-rw-r--r--include/asm-blackfin/mach-bf533/defBF532.h1
-rw-r--r--include/asm-blackfin/mach-bf537/defBF534.h2
-rw-r--r--include/asm-blackfin/mach-bf548/defBF544.h1
-rw-r--r--include/asm-blackfin/mach-bf548/defBF548.h2
-rw-r--r--include/asm-blackfin/mach-bf548/defBF549.h2
-rw-r--r--include/asm-blackfin/mach-bf548/defBF54x_base.h3
-rw-r--r--include/asm-blackfin/mach-bf561/defBF561.h1
9 files changed, 14 insertions, 2 deletions
diff --git a/include/asm-blackfin/bfin5xx_spi.h b/include/asm-blackfin/bfin5xx_spi.h
index 95c1c952e7c1..f617d8765451 100644
--- a/include/asm-blackfin/bfin5xx_spi.h
+++ b/include/asm-blackfin/bfin5xx_spi.h
@@ -21,8 +21,6 @@
21#ifndef _SPI_CHANNEL_H_ 21#ifndef _SPI_CHANNEL_H_
22#define _SPI_CHANNEL_H_ 22#define _SPI_CHANNEL_H_
23 23
24#define SPI0_REGBASE 0xffc00500
25
26#define SPI_READ 0 24#define SPI_READ 0
27#define SPI_WRITE 1 25#define SPI_WRITE 1
28 26
diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h
index 0b2fb5036ed0..b1ff67db01f8 100644
--- a/include/asm-blackfin/mach-bf527/defBF52x_base.h
+++ b/include/asm-blackfin/mach-bf527/defBF52x_base.h
@@ -102,6 +102,7 @@
102 102
103 103
104/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ 104/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
105#define SPI0_REGBASE 0xFFC00500
105#define SPI_CTL 0xFFC00500 /* SPI Control Register */ 106#define SPI_CTL 0xFFC00500 /* SPI Control Register */
106#define SPI_FLG 0xFFC00504 /* SPI Flag register */ 107#define SPI_FLG 0xFFC00504 /* SPI Flag register */
107#define SPI_STAT 0xFFC00508 /* SPI Status register */ 108#define SPI_STAT 0xFFC00508 /* SPI Status register */
@@ -480,6 +481,7 @@
480 481
481 482
482/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ 483/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
484#define TWI0_REGBASE 0xFFC01400
483#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ 485#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
484#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ 486#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
485#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ 487#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index 81b4af17c6a3..37134aaf9954 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -104,6 +104,7 @@
104#define UART_GCTL 0xFFC00424 /* Global Control Register */ 104#define UART_GCTL 0xFFC00424 /* Global Control Register */
105 105
106/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ 106/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
107#define SPI0_REGBASE 0xFFC00500
107#define SPI_CTL 0xFFC00500 /* SPI Control Register */ 108#define SPI_CTL 0xFFC00500 /* SPI Control Register */
108#define SPI_FLG 0xFFC00504 /* SPI Flag register */ 109#define SPI_FLG 0xFFC00504 /* SPI Flag register */
109#define SPI_STAT 0xFFC00508 /* SPI Status register */ 110#define SPI_STAT 0xFFC00508 /* SPI Status register */
diff --git a/include/asm-blackfin/mach-bf537/defBF534.h b/include/asm-blackfin/mach-bf537/defBF534.h
index dce4c543a339..d0d80d3152ba 100644
--- a/include/asm-blackfin/mach-bf537/defBF534.h
+++ b/include/asm-blackfin/mach-bf537/defBF534.h
@@ -86,6 +86,7 @@
86#define UART0_GCTL 0xFFC00424 /* Global Control Register */ 86#define UART0_GCTL 0xFFC00424 /* Global Control Register */
87 87
88/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ 88/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
89#define SPI0_REGBASE 0xFFC00500
89#define SPI_CTL 0xFFC00500 /* SPI Control Register */ 90#define SPI_CTL 0xFFC00500 /* SPI Control Register */
90#define SPI_FLG 0xFFC00504 /* SPI Flag register */ 91#define SPI_FLG 0xFFC00504 /* SPI Flag register */
91#define SPI_STAT 0xFFC00508 /* SPI Status register */ 92#define SPI_STAT 0xFFC00508 /* SPI Status register */
@@ -456,6 +457,7 @@
456#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ 457#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
457 458
458/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ 459/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
460#define TWI0_REGBASE 0xFFC01400
459#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ 461#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
460#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ 462#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
461#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ 463#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h
index dd955dcd39b8..760307e34b9e 100644
--- a/include/asm-blackfin/mach-bf548/defBF544.h
+++ b/include/asm-blackfin/mach-bf548/defBF544.h
@@ -81,6 +81,7 @@
81 81
82/* Two Wire Interface Registers (TWI1) */ 82/* Two Wire Interface Registers (TWI1) */
83 83
84#define TWI1_REGBASE 0xffc02200
84#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ 85#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
85#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ 86#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
86#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ 87#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
index 8d4214e0807c..70af33c963b0 100644
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ b/include/asm-blackfin/mach-bf548/defBF548.h
@@ -120,6 +120,7 @@
120 120
121/* Two Wire Interface Registers (TWI1) */ 121/* Two Wire Interface Registers (TWI1) */
122 122
123#define TWI1_REGBASE 0xffc02200
123#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ 124#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
124#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ 125#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
125#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ 126#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
@@ -139,6 +140,7 @@
139 140
140/* SPI2 Registers */ 141/* SPI2 Registers */
141 142
143#define SPI2_REGBASE 0xffc02400
142#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ 144#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
143#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ 145#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
144#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ 146#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h
index c2f4734da48d..50b3fe55ef0c 100644
--- a/include/asm-blackfin/mach-bf548/defBF549.h
+++ b/include/asm-blackfin/mach-bf548/defBF549.h
@@ -121,6 +121,7 @@
121 121
122/* Two Wire Interface Registers (TWI1) */ 122/* Two Wire Interface Registers (TWI1) */
123 123
124#define TWI1_REGBASE 0xffc02200
124#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */ 125#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
125#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */ 126#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
126#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */ 127#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
@@ -140,6 +141,7 @@
140 141
141/* SPI2 Registers */ 142/* SPI2 Registers */
142 143
144#define SPI2_REGBASE 0xffc02400
143#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */ 145#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
144#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */ 146#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
145#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */ 147#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index 895ddd40a838..e2632db74baa 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -109,6 +109,7 @@
109 109
110/* SPI0 Registers */ 110/* SPI0 Registers */
111 111
112#define SPI0_REGBASE 0xffc00500
112#define SPI0_CTL 0xffc00500 /* SPI0 Control Register */ 113#define SPI0_CTL 0xffc00500 /* SPI0 Control Register */
113#define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */ 114#define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */
114#define SPI0_STAT 0xffc00508 /* SPI0 Status Register */ 115#define SPI0_STAT 0xffc00508 /* SPI0 Status Register */
@@ -121,6 +122,7 @@
121 122
122/* Two Wire Interface Registers (TWI0) */ 123/* Two Wire Interface Registers (TWI0) */
123 124
125#define TWI0_REGBASE 0xffc00700
124#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */ 126#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
125#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */ 127#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
126#define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */ 128#define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */
@@ -978,6 +980,7 @@
978 980
979/* SPI1 Registers */ 981/* SPI1 Registers */
980 982
983#define SPI1_REGBASE 0xffc02300
981#define SPI1_CTL 0xffc02300 /* SPI1 Control Register */ 984#define SPI1_CTL 0xffc02300 /* SPI1 Control Register */
982#define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */ 985#define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */
983#define SPI1_STAT 0xffc02308 /* SPI1 Status Register */ 986#define SPI1_STAT 0xffc02308 /* SPI1 Status Register */
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index 0f2dc6e6335b..bf7dc4e00065 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -120,6 +120,7 @@
120#define UART_GCTL 0xFFC00424 /* Global Control Register */ 120#define UART_GCTL 0xFFC00424 /* Global Control Register */
121 121
122/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ 122/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
123#define SPI0_REGBASE 0xFFC00500
123#define SPI_CTL 0xFFC00500 /* SPI Control Register */ 124#define SPI_CTL 0xFFC00500 /* SPI Control Register */
124#define SPI_FLG 0xFFC00504 /* SPI Flag register */ 125#define SPI_FLG 0xFFC00504 /* SPI Flag register */
125#define SPI_STAT 0xFFC00508 /* SPI Status register */ 126#define SPI_STAT 0xFFC00508 /* SPI Status register */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-16 16:11:47 -0500