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-rw-r--r--arch/arm/Kconfig6
-rw-r--r--arch/arm/boot/compressed/head-xscale.S4
-rw-r--r--arch/arm/common/Makefile1
-rw-r--r--arch/arm/common/it8152.c387
-rw-r--r--arch/arm/configs/cm_x270_defconfig1410
-rw-r--r--arch/arm/kernel/bios32.c28
-rw-r--r--arch/arm/mach-pxa/Kconfig34
-rw-r--r--arch/arm/mach-pxa/Makefile47
-rw-r--r--arch/arm/mach-pxa/clock.c79
-rw-r--r--arch/arm/mach-pxa/clock.h43
-rw-r--r--arch/arm/mach-pxa/cm-x270-pci.c218
-rw-r--r--arch/arm/mach-pxa/cm-x270-pci.h13
-rw-r--r--arch/arm/mach-pxa/cm-x270.c645
-rw-r--r--arch/arm/mach-pxa/devices.h3
-rw-r--r--arch/arm/mach-pxa/generic.c184
-rw-r--r--arch/arm/mach-pxa/generic.h26
-rw-r--r--arch/arm/mach-pxa/irq.c80
-rw-r--r--arch/arm/mach-pxa/lubbock.c19
-rw-r--r--arch/arm/mach-pxa/mainstone.c19
-rw-r--r--arch/arm/mach-pxa/mfp.c235
-rw-r--r--arch/arm/mach-pxa/pxa25x.c90
-rw-r--r--arch/arm/mach-pxa/pxa27x.c127
-rw-r--r--arch/arm/mach-pxa/pxa300.c93
-rw-r--r--arch/arm/mach-pxa/pxa320.c88
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c216
-rw-r--r--arch/arm/mach-pxa/time.c53
-rw-r--r--arch/arm/mach-pxa/zylonite.c184
-rw-r--r--arch/arm/mach-pxa/zylonite_pxa300.c188
-rw-r--r--arch/arm/mach-pxa/zylonite_pxa320.c173
-rw-r--r--arch/arm/mm/Kconfig4
-rw-r--r--drivers/i2c/busses/i2c-pxa.c45
-rw-r--r--drivers/input/keyboard/pxa27x_keyboard.c25
-rw-r--r--drivers/leds/Kconfig6
-rw-r--r--drivers/leds/Makefile1
-rw-r--r--drivers/leds/leds-cm-x270.c122
-rw-r--r--drivers/mmc/host/pxamci.c43
-rw-r--r--drivers/mmc/host/pxamci.h14
-rw-r--r--drivers/net/irda/pxaficp_ir.c51
-rw-r--r--drivers/net/smc91x.c55
-rw-r--r--drivers/net/smc91x.h64
-rw-r--r--drivers/pcmcia/Makefile1
-rw-r--r--drivers/pcmcia/pxa2xx_cm_x270.c175
-rw-r--r--drivers/pcmcia/pxa2xx_lubbock.c31
-rw-r--r--drivers/pcmcia/pxa2xx_mainstone.c18
-rw-r--r--drivers/serial/pxa.c163
-rw-r--r--drivers/serial/serial_core.c18
-rw-r--r--drivers/usb/gadget/pxa2xx_udc.c68
-rw-r--r--drivers/usb/gadget/pxa2xx_udc.h1
-rw-r--r--drivers/video/pxafb.c36
-rw-r--r--drivers/video/pxafb.h1
-rw-r--r--include/asm-arm/arch-pxa/cm-x270.h50
-rw-r--r--include/asm-arm/arch-pxa/dma.h4
-rw-r--r--include/asm-arm/arch-pxa/gpio.h12
-rw-r--r--include/asm-arm/arch-pxa/hardware.h99
-rw-r--r--include/asm-arm/arch-pxa/irqs.h27
-rw-r--r--include/asm-arm/arch-pxa/memory.h10
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa300.h574
-rw-r--r--include/asm-arm/arch-pxa/mfp-pxa320.h446
-rw-r--r--include/asm-arm/arch-pxa/mfp.h576
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h2
-rw-r--r--include/asm-arm/arch-pxa/pxa3xx-regs.h75
-rw-r--r--include/asm-arm/arch-pxa/timex.h2
-rw-r--r--include/asm-arm/arch-pxa/zylonite.h35
-rw-r--r--include/asm-arm/hardware/it8152.h99
-rw-r--r--include/asm-arm/pci.h7
-rw-r--r--include/linux/pci_ids.h1
66 files changed, 7135 insertions, 519 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fcd1d8f95a21..0a0c88d0039c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -339,14 +339,14 @@ config ARCH_PNX4008
339 This enables support for Philips PNX4008 mobile platform. 339 This enables support for Philips PNX4008 mobile platform.
340 340
341config ARCH_PXA 341config ARCH_PXA
342 bool "PXA2xx-based" 342 bool "PXA2xx/PXA3xx-based"
343 depends on MMU 343 depends on MMU
344 select ARCH_MTD_XIP 344 select ARCH_MTD_XIP
345 select GENERIC_GPIO 345 select GENERIC_GPIO
346 select GENERIC_TIME 346 select GENERIC_TIME
347 select GENERIC_CLOCKEVENTS 347 select GENERIC_CLOCKEVENTS
348 help 348 help
349 Support for Intel's PXA2XX processor line. 349 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
350 350
351config ARCH_RPC 351config ARCH_RPC
352 bool "RiscPC" 352 bool "RiscPC"
@@ -489,7 +489,7 @@ source arch/arm/mm/Kconfig
489config IWMMXT 489config IWMMXT
490 bool "Enable iWMMXt support" 490 bool "Enable iWMMXt support"
491 depends on CPU_XSCALE || CPU_XSC3 491 depends on CPU_XSCALE || CPU_XSC3
492 default y if PXA27x 492 default y if PXA27x || PXA3xx
493 help 493 help
494 Enable support for iWMMXt context switching at run time if 494 Enable support for iWMMXt context switching at run time if
495 running on a CPU that supports it. 495 running on a CPU that supports it.
diff --git a/arch/arm/boot/compressed/head-xscale.S b/arch/arm/boot/compressed/head-xscale.S
index 236bbe578312..67ea99ef6521 100644
--- a/arch/arm/boot/compressed/head-xscale.S
+++ b/arch/arm/boot/compressed/head-xscale.S
@@ -33,10 +33,6 @@ __XScale_start:
33 bic r0, r0, #0x1000 @ clear Icache 33 bic r0, r0, #0x1000 @ clear Icache
34 mcr p15, 0, r0, c1, c0, 0 34 mcr p15, 0, r0, c1, c0, 0
35 35
36#ifdef CONFIG_ARCH_LUBBOCK
37 mov r7, #MACH_TYPE_LUBBOCK
38#endif
39
40#ifdef CONFIG_ARCH_COTULLA_IDP 36#ifdef CONFIG_ARCH_COTULLA_IDP
41 mov r7, #MACH_TYPE_COTULLA_IDP 37 mov r7, #MACH_TYPE_COTULLA_IDP
42#endif 38#endif
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index e1289a256ce5..3d0b9fa42f84 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_SHARPSL_PM) += sharpsl_pm.o
17obj-$(CONFIG_SHARP_SCOOP) += scoop.o 17obj-$(CONFIG_SHARP_SCOOP) += scoop.o
18obj-$(CONFIG_ARCH_IXP2000) += uengine.o 18obj-$(CONFIG_ARCH_IXP2000) += uengine.o
19obj-$(CONFIG_ARCH_IXP23XX) += uengine.o 19obj-$(CONFIG_ARCH_IXP23XX) += uengine.o
20obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
new file mode 100644
index 000000000000..c03de9bfd76b
--- /dev/null
+++ b/arch/arm/common/it8152.c
@@ -0,0 +1,387 @@
1/*
2 * linux/arch/arm/common/it8152.c
3 *
4 * Copyright Compulab Ltd, 2002-2007
5 * Mike Rapoport <mike@compulab.co.il>
6 *
7 * The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c
8 * (see this file for respective copyrights)
9 *
10 * Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation
11 * and demux code.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/sched.h>
19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/ptrace.h>
22#include <linux/interrupt.h>
23#include <linux/mm.h>
24#include <linux/slab.h>
25#include <linux/init.h>
26#include <linux/ioport.h>
27#include <linux/irq.h>
28#include <linux/io.h>
29
30#include <asm/mach/pci.h>
31#include <asm/hardware/it8152.h>
32
33#define MAX_SLOTS 21
34
35static void it8152_mask_irq(unsigned int irq)
36{
37 if (irq >= IT8152_LD_IRQ(0)) {
38 __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) |
39 (1 << (irq - IT8152_LD_IRQ(0)))),
40 IT8152_INTC_LDCNIMR);
41 } else if (irq >= IT8152_LP_IRQ(0)) {
42 __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) |
43 (1 << (irq - IT8152_LP_IRQ(0)))),
44 IT8152_INTC_LPCNIMR);
45 } else if (irq >= IT8152_PD_IRQ(0)) {
46 __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) |
47 (1 << (irq - IT8152_PD_IRQ(0)))),
48 IT8152_INTC_PDCNIMR);
49 }
50}
51
52static void it8152_unmask_irq(unsigned int irq)
53{
54 if (irq >= IT8152_LD_IRQ(0)) {
55 __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
56 ~(1 << (irq - IT8152_LD_IRQ(0)))),
57 IT8152_INTC_LDCNIMR);
58 } else if (irq >= IT8152_LP_IRQ(0)) {
59 __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) &
60 ~(1 << (irq - IT8152_LP_IRQ(0)))),
61 IT8152_INTC_LPCNIMR);
62 } else if (irq >= IT8152_PD_IRQ(0)) {
63 __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) &
64 ~(1 << (irq - IT8152_PD_IRQ(0)))),
65 IT8152_INTC_PDCNIMR);
66 }
67}
68
69static inline void it8152_irq(int irq)
70{
71 struct irq_desc *desc;
72
73 printk(KERN_DEBUG "===> %s: irq=%d\n", __FUNCTION__, irq);
74
75 desc = irq_desc + irq;
76 desc_handle_irq(irq, desc);
77}
78
79static struct irq_chip it8152_irq_chip = {
80 .name = "it8152",
81 .ack = it8152_mask_irq,
82 .mask = it8152_mask_irq,
83 .unmask = it8152_unmask_irq,
84};
85
86void it8152_init_irq(void)
87{
88 int irq;
89
90 __raw_writel((0xffff), IT8152_INTC_PDCNIMR);
91 __raw_writel((0), IT8152_INTC_PDCNIRR);
92 __raw_writel((0xffff), IT8152_INTC_LPCNIMR);
93 __raw_writel((0), IT8152_INTC_LPCNIRR);
94 __raw_writel((0xffff), IT8152_INTC_LDCNIMR);
95 __raw_writel((0), IT8152_INTC_LDCNIRR);
96
97 for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
98 set_irq_chip(irq, &it8152_irq_chip);
99 set_irq_handler(irq, handle_level_irq);
100 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
101 }
102}
103
104void it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
105{
106 int bits_pd, bits_lp, bits_ld;
107 int i;
108
109 printk(KERN_DEBUG "=> %s: irq = %d\n", __FUNCTION__, irq);
110
111 while (1) {
112 /* Read all */
113 bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
114 bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
115 bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
116
117 /* Ack */
118 __raw_writel((~bits_pd), IT8152_INTC_PDCNIRR);
119 __raw_writel((~bits_lp), IT8152_INTC_LPCNIRR);
120 __raw_writel((~bits_ld), IT8152_INTC_LDCNIRR);
121
122 if (!(bits_ld | bits_lp | bits_pd)) {
123 /* Re-read to guarantee, that there was a moment of
124 time, when they all three were 0. */
125 bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
126 bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
127 if (!(bits_ld | bits_lp | bits_pd))
128 return;
129 }
130
131 bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
132 while (bits_pd) {
133 i = __ffs(bits_pd);
134 it8152_irq(IT8152_PD_IRQ(i));
135 bits_pd &= ~(1 << i);
136 }
137
138 bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
139 while (bits_lp) {
140 i = __ffs(bits_pd);
141 it8152_irq(IT8152_LP_IRQ(i));
142 bits_lp &= ~(1 << i);
143 }
144
145 bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
146 while (bits_ld) {
147 i = __ffs(bits_pd);
148 it8152_irq(IT8152_LD_IRQ(i));
149 bits_ld &= ~(1 << i);
150 }
151 }
152}
153
154/* mapping for on-chip devices */
155int __init it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
156{
157 if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
158 (dev->device == PCI_DEVICE_ID_ITE_8152)) {
159 if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO)
160 return IT8152_AUDIO_INT;
161 if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)
162 return IT8152_USB_INT;
163 if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA)
164 return IT8152_CDMA_INT;
165 }
166
167 return 0;
168}
169
170static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus,
171 unsigned int devfn)
172{
173 unsigned long addr = 0;
174
175 if (bus->number == 0) {
176 if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
177 addr = (devfn << 8);
178 } else
179 addr = (bus->number << 16) | (devfn << 8);
180
181 return addr;
182}
183
184static int it8152_pci_read_config(struct pci_bus *bus,
185 unsigned int devfn, int where,
186 int size, u32 *value)
187{
188 unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
189 u32 v;
190 int shift;
191
192 shift = (where & 3);
193
194 __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
195 v = (__raw_readl(IT8152_PCI_CFG_DATA) >> (8 * (shift)));
196
197 *value = v;
198
199 return PCIBIOS_SUCCESSFUL;
200}
201
202static int it8152_pci_write_config(struct pci_bus *bus,
203 unsigned int devfn, int where,
204 int size, u32 value)
205{
206 unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
207 u32 v, vtemp, mask = 0;
208 int shift;
209
210 if (size == 1)
211 mask = 0xff;
212 if (size == 2)
213 mask = 0xffff;
214
215 shift = (where & 3);
216
217 __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
218 vtemp = __raw_readl(IT8152_PCI_CFG_DATA);
219
220 if (mask)
221 vtemp &= ~(mask << (8 * shift));
222 else
223 vtemp = 0;
224
225 v = (value << (8 * shift));
226 __raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
227 __raw_writel((v | vtemp), IT8152_PCI_CFG_DATA);
228
229 return PCIBIOS_SUCCESSFUL;
230}
231
232static struct pci_ops it8152_ops = {
233 .read = it8152_pci_read_config,
234 .write = it8152_pci_write_config,
235};
236
237static struct resource it8152_io = {
238 .name = "IT8152 PCI I/O region",
239 .flags = IORESOURCE_IO,
240};
241
242static struct resource it8152_mem = {
243 .name = "IT8152 PCI memory region",
244 .start = 0x10000000,
245 .end = 0x13e00000,
246 .flags = IORESOURCE_MEM,
247};
248
249/*
250 * The following functions are needed for DMA bouncing.
251 * ITE8152 chip can addrees up to 64MByte, so all the devices
252 * connected to ITE8152 (PCI and USB) should have limited DMA window
253 */
254
255/*
256 * Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
257 * other devices.
258 */
259static int it8152_pci_platform_notify(struct device *dev)
260{
261 if (dev->bus == &pci_bus_type) {
262 if (dev->dma_mask)
263 *dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
264 dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
265 dmabounce_register_dev(dev, 2048, 4096);
266 }
267 return 0;
268}
269
270static int it8152_pci_platform_notify_remove(struct device *dev)
271{
272 if (dev->bus == &pci_bus_type)
273 dmabounce_unregister_dev(dev);
274
275 return 0;
276}
277
278int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
279{
280 dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
281 __FUNCTION__, dma_addr, size);
282 return (dev->bus == &pci_bus_type) &&
283 ((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
284}
285
286/*
287 * We override these so we properly do dmabounce otherwise drivers
288 * are able to set the dma_mask to 0xffffffff and we can no longer
289 * trap bounces. :(
290 *
291 * We just return true on everyhing except for < 64MB in which case
292 * we will fail miseralby and die since we can't handle that case.
293 */
294int pci_set_dma_mask(struct pci_dev *dev, u64 mask)
295{
296 printk(KERN_DEBUG "%s: %s %llx\n",
297 __FUNCTION__, dev->dev.bus_id, mask);
298 if (mask >= PHYS_OFFSET + SZ_64M - 1)
299 return 0;
300
301 return -EIO;
302}
303
304int
305pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
306{
307 printk(KERN_DEBUG "%s: %s %llx\n",
308 __FUNCTION__, dev->dev.bus_id, mask);
309 if (mask >= PHYS_OFFSET + SZ_64M - 1)
310 return 0;
311
312 return -EIO;
313}
314
315int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
316{
317 it8152_io.start = IT8152_IO_BASE + 0x12000;
318 it8152_io.end = IT8152_IO_BASE + 0x12000 + 0x100000;
319
320 sys->mem_offset = 0x10000000;
321 sys->io_offset = IT8152_IO_BASE;
322
323 if (request_resource(&ioport_resource, &it8152_io)) {
324 printk(KERN_ERR "PCI: unable to allocate IO region\n");
325 goto err0;
326 }
327 if (request_resource(&iomem_resource, &it8152_mem)) {
328 printk(KERN_ERR "PCI: unable to allocate memory region\n");
329 goto err1;
330 }
331
332 sys->resource[0] = &it8152_io;
333 sys->resource[1] = &it8152_mem;
334
335 if (platform_notify || platform_notify_remove) {
336 printk(KERN_ERR "PCI: Can't use platform_notify\n");
337 goto err2;
338 }
339
340 platform_notify = it8152_pci_platform_notify;
341 platform_notify_remove = it8152_pci_platform_notify_remove;
342
343 return 1;
344
345err2:
346 release_resource(&it8152_io);
347err1:
348 release_resource(&it8152_mem);
349err0:
350 return -EBUSY;
351}
352
353/*
354 * If we set up a device for bus mastering, we need to check the latency
355 * timer as we don't have even crappy BIOSes to set it properly.
356 * The implementation is from arch/i386/pci/i386.c
357 */
358unsigned int pcibios_max_latency = 255;
359
360void pcibios_set_master(struct pci_dev *dev)
361{
362 u8 lat;
363
364 /* no need to update on-chip OHCI controller */
365 if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
366 (dev->device == PCI_DEVICE_ID_ITE_8152) &&
367 ((dev->class >> 8) == PCI_CLASS_SERIAL_USB))
368 return;
369
370 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
371 if (lat < 16)
372 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
373 else if (lat > pcibios_max_latency)
374 lat = pcibios_max_latency;
375 else
376 return;
377 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
378 pci_name(dev), lat);
379 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
380}
381
382
383struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
384{
385 return pci_scan_bus(nr, &it8152_ops, sys);
386}
387
diff --git a/arch/arm/configs/cm_x270_defconfig b/arch/arm/configs/cm_x270_defconfig
new file mode 100644
index 000000000000..5cab08397ae7
--- /dev/null
+++ b/arch/arm/configs/cm_x270_defconfig
@@ -0,0 +1,1410 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.22
4# Wed Jul 18 14:11:48 2007
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10# CONFIG_GENERIC_CLOCKEVENTS is not set
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_ARCH_MTD_XIP=y
26CONFIG_VECTORS_BASE=0xffff0000
27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
28
29#
30# Code maturity level options
31#
32CONFIG_EXPERIMENTAL=y
33CONFIG_BROKEN_ON_SMP=y
34CONFIG_INIT_ENV_ARG_LIMIT=32
35
36#
37# General setup
38#
39CONFIG_LOCALVERSION=""
40# CONFIG_LOCALVERSION_AUTO is not set
41CONFIG_SWAP=y
42CONFIG_SYSVIPC=y
43CONFIG_SYSVIPC_SYSCTL=y
44# CONFIG_POSIX_MQUEUE is not set
45# CONFIG_BSD_PROCESS_ACCT is not set
46# CONFIG_TASKSTATS is not set
47# CONFIG_USER_NS is not set
48# CONFIG_AUDIT is not set
49CONFIG_IKCONFIG=y
50CONFIG_IKCONFIG_PROC=y
51CONFIG_LOG_BUF_SHIFT=17
52CONFIG_SYSFS_DEPRECATED=y
53# CONFIG_RELAY is not set
54CONFIG_BLK_DEV_INITRD=y
55CONFIG_INITRAMFS_SOURCE=""
56CONFIG_CC_OPTIMIZE_FOR_SIZE=y
57CONFIG_SYSCTL=y
58CONFIG_EMBEDDED=y
59CONFIG_UID16=y
60CONFIG_SYSCTL_SYSCALL=y
61CONFIG_KALLSYMS=y
62# CONFIG_KALLSYMS_ALL is not set
63# CONFIG_KALLSYMS_EXTRA_PASS is not set
64CONFIG_HOTPLUG=y
65CONFIG_PRINTK=y
66CONFIG_BUG=y
67CONFIG_ELF_CORE=y
68CONFIG_BASE_FULL=y
69CONFIG_FUTEX=y
70CONFIG_ANON_INODES=y
71# CONFIG_EPOLL is not set
72# CONFIG_SIGNALFD is not set
73# CONFIG_TIMERFD is not set
74# CONFIG_EVENTFD is not set
75CONFIG_SHMEM=y
76CONFIG_VM_EVENT_COUNTERS=y
77CONFIG_SLAB=y
78# CONFIG_SLUB is not set
79# CONFIG_SLOB is not set
80CONFIG_RT_MUTEXES=y
81# CONFIG_TINY_SHMEM is not set
82CONFIG_BASE_SMALL=0
83CONFIG_MODULES=y
84CONFIG_MODULE_UNLOAD=y
85CONFIG_MODULE_FORCE_UNLOAD=y
86# CONFIG_MODVERSIONS is not set
87# CONFIG_MODULE_SRCVERSION_ALL is not set
88CONFIG_KMOD=y
89CONFIG_BLOCK=y
90# CONFIG_LBD is not set
91# CONFIG_BLK_DEV_IO_TRACE is not set
92# CONFIG_LSF is not set
93# CONFIG_BLK_DEV_BSG is not set
94
95#
96# IO Schedulers
97#
98CONFIG_IOSCHED_NOOP=y
99CONFIG_IOSCHED_AS=y
100CONFIG_IOSCHED_DEADLINE=y
101CONFIG_IOSCHED_CFQ=y
102CONFIG_DEFAULT_AS=y
103# CONFIG_DEFAULT_DEADLINE is not set
104# CONFIG_DEFAULT_CFQ is not set
105# CONFIG_DEFAULT_NOOP is not set
106CONFIG_DEFAULT_IOSCHED="anticipatory"
107
108#
109# System Type
110#
111# CONFIG_ARCH_AAEC2000 is not set
112# CONFIG_ARCH_INTEGRATOR is not set
113# CONFIG_ARCH_REALVIEW is not set
114# CONFIG_ARCH_VERSATILE is not set
115# CONFIG_ARCH_AT91 is not set
116# CONFIG_ARCH_CLPS7500 is not set
117# CONFIG_ARCH_CLPS711X is not set
118# CONFIG_ARCH_CO285 is not set
119# CONFIG_ARCH_EBSA110 is not set
120# CONFIG_ARCH_EP93XX is not set
121# CONFIG_ARCH_FOOTBRIDGE is not set
122# CONFIG_ARCH_NETX is not set
123# CONFIG_ARCH_H720X is not set
124# CONFIG_ARCH_IMX is not set
125# CONFIG_ARCH_IOP13XX is not set
126# CONFIG_ARCH_IOP32X is not set
127# CONFIG_ARCH_IOP33X is not set
128# CONFIG_ARCH_IXP23XX is not set
129# CONFIG_ARCH_IXP2000 is not set
130# CONFIG_ARCH_IXP4XX is not set
131# CONFIG_ARCH_L7200 is not set
132# CONFIG_ARCH_KS8695 is not set
133# CONFIG_ARCH_NS9XXX is not set
134# CONFIG_ARCH_PNX4008 is not set
135CONFIG_ARCH_PXA=y
136# CONFIG_ARCH_RPC is not set
137# CONFIG_ARCH_SA1100 is not set
138# CONFIG_ARCH_S3C2410 is not set
139# CONFIG_ARCH_SHARK is not set
140# CONFIG_ARCH_LH7A40X is not set
141# CONFIG_ARCH_DAVINCI is not set
142# CONFIG_ARCH_OMAP is not set
143CONFIG_DMABOUNCE=y
144
145#
146# Intel PXA2xx Implementations
147#
148# CONFIG_ARCH_LUBBOCK is not set
149# CONFIG_MACH_LOGICPD_PXA270 is not set
150# CONFIG_MACH_MAINSTONE is not set
151# CONFIG_ARCH_PXA_IDP is not set
152# CONFIG_PXA_SHARPSL is not set
153# CONFIG_MACH_TRIZEPS4 is not set
154CONFIG_MACH_ARMCORE=y
155CONFIG_PXA27x=y
156
157#
158# Processor Type
159#
160CONFIG_CPU_32=y
161CONFIG_CPU_XSCALE=y
162CONFIG_CPU_32v5=y
163CONFIG_CPU_ABRT_EV5T=y
164CONFIG_CPU_CACHE_VIVT=y
165CONFIG_CPU_TLB_V4WBI=y
166CONFIG_CPU_CP15=y
167CONFIG_CPU_CP15_MMU=y
168
169#
170# Processor Features
171#
172CONFIG_ARM_THUMB=y
173# CONFIG_CPU_DCACHE_DISABLE is not set
174# CONFIG_OUTER_CACHE is not set
175CONFIG_IWMMXT=y
176CONFIG_XSCALE_PMU=y
177
178#
179# Bus support
180#
181CONFIG_PCI=y
182CONFIG_PCI_SYSCALL=y
183CONFIG_PCI_HOST_ITE8152=y
184# CONFIG_ARCH_SUPPORTS_MSI is not set
185# CONFIG_PCI_DEBUG is not set
186
187#
188# PCCARD (PCMCIA/CardBus) support
189#
190# CONFIG_PCCARD is not set
191
192#
193# Kernel Features
194#
195# CONFIG_TICK_ONESHOT is not set
196# CONFIG_PREEMPT is not set
197# CONFIG_NO_IDLE_HZ is not set
198CONFIG_HZ=100
199# CONFIG_AEABI is not set
200# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
201CONFIG_SELECT_MEMORY_MODEL=y
202CONFIG_FLATMEM_MANUAL=y
203# CONFIG_DISCONTIGMEM_MANUAL is not set
204# CONFIG_SPARSEMEM_MANUAL is not set
205CONFIG_FLATMEM=y
206CONFIG_FLAT_NODE_MEM_MAP=y
207# CONFIG_SPARSEMEM_STATIC is not set
208CONFIG_SPLIT_PTLOCK_CPUS=4096
209# CONFIG_RESOURCES_64BIT is not set
210CONFIG_ZONE_DMA_FLAG=1
211CONFIG_BOUNCE=y
212CONFIG_VIRT_TO_BUS=y
213CONFIG_ALIGNMENT_TRAP=y
214
215#
216# Boot options
217#
218CONFIG_ZBOOT_ROM_TEXT=0x0
219CONFIG_ZBOOT_ROM_BSS=0x0
220CONFIG_CMDLINE=""
221# CONFIG_XIP_KERNEL is not set
222# CONFIG_KEXEC is not set
223
224#
225# Floating point emulation
226#
227
228#
229# At least one emulation must be selected
230#
231CONFIG_FPE_NWFPE=y
232# CONFIG_FPE_NWFPE_XP is not set
233# CONFIG_FPE_FASTFPE is not set
234
235#
236# Userspace binary formats
237#
238CONFIG_BINFMT_ELF=y
239# CONFIG_BINFMT_AOUT is not set
240# CONFIG_BINFMT_MISC is not set
241# CONFIG_ARTHUR is not set
242
243#
244# Power management options
245#
246CONFIG_PM=y
247# CONFIG_PM_LEGACY is not set
248# CONFIG_PM_DEBUG is not set
249# CONFIG_PM_SYSFS_DEPRECATED is not set
250# CONFIG_APM_EMULATION is not set
251
252#
253# Networking
254#
255CONFIG_NET=y
256
257#
258# Networking options
259#
260CONFIG_PACKET=y
261# CONFIG_PACKET_MMAP is not set
262CONFIG_UNIX=y
263CONFIG_XFRM=y
264# CONFIG_XFRM_USER is not set
265# CONFIG_XFRM_SUB_POLICY is not set
266# CONFIG_XFRM_MIGRATE is not set
267# CONFIG_NET_KEY is not set
268CONFIG_INET=y
269# CONFIG_IP_MULTICAST is not set
270# CONFIG_IP_ADVANCED_ROUTER is not set
271CONFIG_IP_FIB_HASH=y
272CONFIG_IP_PNP=y
273CONFIG_IP_PNP_DHCP=y
274CONFIG_IP_PNP_BOOTP=y
275# CONFIG_IP_PNP_RARP is not set
276# CONFIG_NET_IPIP is not set
277# CONFIG_NET_IPGRE is not set
278# CONFIG_ARPD is not set
279# CONFIG_SYN_COOKIES is not set
280# CONFIG_INET_AH is not set
281# CONFIG_INET_ESP is not set
282# CONFIG_INET_IPCOMP is not set
283# CONFIG_INET_XFRM_TUNNEL is not set
284# CONFIG_INET_TUNNEL is not set
285CONFIG_INET_XFRM_MODE_TRANSPORT=y
286CONFIG_INET_XFRM_MODE_TUNNEL=y
287CONFIG_INET_XFRM_MODE_BEET=y
288CONFIG_INET_DIAG=y
289CONFIG_INET_TCP_DIAG=y
290# CONFIG_TCP_CONG_ADVANCED is not set
291CONFIG_TCP_CONG_CUBIC=y
292CONFIG_DEFAULT_TCP_CONG="cubic"
293# CONFIG_TCP_MD5SIG is not set
294# CONFIG_IPV6 is not set
295# CONFIG_INET6_XFRM_TUNNEL is not set
296# CONFIG_INET6_TUNNEL is not set
297# CONFIG_NETWORK_SECMARK is not set
298# CONFIG_NETFILTER is not set
299# CONFIG_IP_DCCP is not set
300# CONFIG_IP_SCTP is not set
301# CONFIG_TIPC is not set
302# CONFIG_ATM is not set
303# CONFIG_BRIDGE is not set
304# CONFIG_VLAN_8021Q is not set
305# CONFIG_DECNET is not set
306# CONFIG_LLC2 is not set
307# CONFIG_IPX is not set
308# CONFIG_ATALK is not set
309# CONFIG_X25 is not set
310# CONFIG_LAPB is not set
311# CONFIG_ECONET is not set
312# CONFIG_WAN_ROUTER is not set
313
314#
315# QoS and/or fair queueing
316#
317# CONFIG_NET_SCHED is not set
318
319#
320# Network testing
321#
322# CONFIG_NET_PKTGEN is not set
323# CONFIG_HAMRADIO is not set
324# CONFIG_IRDA is not set
325# CONFIG_BT is not set
326# CONFIG_AF_RXRPC is not set
327
328#
329# Wireless
330#
331# CONFIG_CFG80211 is not set
332CONFIG_WIRELESS_EXT=y
333# CONFIG_MAC80211 is not set
334CONFIG_IEEE80211=m
335# CONFIG_IEEE80211_DEBUG is not set
336CONFIG_IEEE80211_CRYPT_WEP=m
337CONFIG_IEEE80211_CRYPT_CCMP=m
338# CONFIG_IEEE80211_CRYPT_TKIP is not set
339# CONFIG_IEEE80211_SOFTMAC is not set
340# CONFIG_RFKILL is not set
341# CONFIG_NET_9P is not set
342
343#
344# Device Drivers
345#
346
347#
348# Generic Driver Options
349#
350CONFIG_STANDALONE=y
351CONFIG_PREVENT_FIRMWARE_BUILD=y
352CONFIG_FW_LOADER=y
353# CONFIG_DEBUG_DRIVER is not set
354# CONFIG_DEBUG_DEVRES is not set
355# CONFIG_SYS_HYPERVISOR is not set
356# CONFIG_CONNECTOR is not set
357CONFIG_MTD=m
358# CONFIG_MTD_DEBUG is not set
359# CONFIG_MTD_CONCAT is not set
360CONFIG_MTD_PARTITIONS=y
361# CONFIG_MTD_REDBOOT_PARTS is not set
362# CONFIG_MTD_AFS_PARTS is not set
363
364#
365# User Modules And Translation Layers
366#
367CONFIG_MTD_CHAR=m
368CONFIG_MTD_BLKDEVS=m
369CONFIG_MTD_BLOCK=m
370# CONFIG_MTD_BLOCK_RO is not set
371# CONFIG_FTL is not set
372# CONFIG_NFTL is not set
373# CONFIG_INFTL is not set
374# CONFIG_RFD_FTL is not set
375# CONFIG_SSFDC is not set
376
377#
378# RAM/ROM/Flash chip drivers
379#
380# CONFIG_MTD_CFI is not set
381# CONFIG_MTD_JEDECPROBE is not set
382CONFIG_MTD_MAP_BANK_WIDTH_1=y
383CONFIG_MTD_MAP_BANK_WIDTH_2=y
384CONFIG_MTD_MAP_BANK_WIDTH_4=y
385# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
386# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
387# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
388CONFIG_MTD_CFI_I1=y
389CONFIG_MTD_CFI_I2=y
390# CONFIG_MTD_CFI_I4 is not set
391# CONFIG_MTD_CFI_I8 is not set
392# CONFIG_MTD_RAM is not set
393# CONFIG_MTD_ROM is not set
394# CONFIG_MTD_ABSENT is not set
395
396#
397# Mapping drivers for chip access
398#
399# CONFIG_MTD_COMPLEX_MAPPINGS is not set
400# CONFIG_MTD_SHARP_SL is not set
401# CONFIG_MTD_PLATRAM is not set
402
403#
404# Self-contained MTD device drivers
405#
406# CONFIG_MTD_PMC551 is not set
407# CONFIG_MTD_SLRAM is not set
408# CONFIG_MTD_PHRAM is not set
409# CONFIG_MTD_MTDRAM is not set
410# CONFIG_MTD_BLOCK2MTD is not set
411
412#
413# Disk-On-Chip Device Drivers
414#
415# CONFIG_MTD_DOC2000 is not set
416# CONFIG_MTD_DOC2001 is not set
417# CONFIG_MTD_DOC2001PLUS is not set
418CONFIG_MTD_NAND=m
419# CONFIG_MTD_NAND_VERIFY_WRITE is not set
420# CONFIG_MTD_NAND_ECC_SMC is not set
421# CONFIG_MTD_NAND_MUSEUM_IDS is not set
422# CONFIG_MTD_NAND_H1900 is not set
423CONFIG_MTD_NAND_IDS=m
424# CONFIG_MTD_NAND_DISKONCHIP is not set
425# CONFIG_MTD_NAND_SHARPSL is not set
426# CONFIG_MTD_NAND_CAFE is not set
427CONFIG_MTD_NAND_CM_X270=m
428# CONFIG_MTD_NAND_NANDSIM is not set
429# CONFIG_MTD_NAND_PLATFORM is not set
430# CONFIG_MTD_ONENAND is not set
431
432#
433# UBI - Unsorted block images
434#
435# CONFIG_MTD_UBI is not set
436# CONFIG_PARPORT is not set
437CONFIG_BLK_DEV=y
438# CONFIG_BLK_CPQ_DA is not set
439# CONFIG_BLK_CPQ_CISS_DA is not set
440# CONFIG_BLK_DEV_DAC960 is not set
441# CONFIG_BLK_DEV_UMEM is not set
442# CONFIG_BLK_DEV_COW_COMMON is not set
443CONFIG_BLK_DEV_LOOP=y
444# CONFIG_BLK_DEV_CRYPTOLOOP is not set
445# CONFIG_BLK_DEV_NBD is not set
446# CONFIG_BLK_DEV_SX8 is not set
447# CONFIG_BLK_DEV_UB is not set
448CONFIG_BLK_DEV_RAM=y
449CONFIG_BLK_DEV_RAM_COUNT=16
450CONFIG_BLK_DEV_RAM_SIZE=12000
451CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
452# CONFIG_CDROM_PKTCDVD is not set
453# CONFIG_ATA_OVER_ETH is not set
454CONFIG_IDE=m
455CONFIG_IDE_MAX_HWIFS=4
456CONFIG_BLK_DEV_IDE=m
457
458#
459# Please see Documentation/ide.txt for help/info on IDE drives
460#
461# CONFIG_BLK_DEV_IDE_SATA is not set
462CONFIG_BLK_DEV_IDEDISK=m
463# CONFIG_IDEDISK_MULTI_MODE is not set
464CONFIG_BLK_DEV_IDECD=m
465# CONFIG_BLK_DEV_IDETAPE is not set
466# CONFIG_BLK_DEV_IDEFLOPPY is not set
467# CONFIG_BLK_DEV_IDESCSI is not set
468# CONFIG_IDE_TASK_IOCTL is not set
469CONFIG_IDE_PROC_FS=y
470
471#
472# IDE chipset support/bugfixes
473#
474# CONFIG_IDE_GENERIC is not set
475# CONFIG_BLK_DEV_IDEPCI is not set
476# CONFIG_IDEPCI_PCIBUS_ORDER is not set
477# CONFIG_IDE_ARM is not set
478# CONFIG_BLK_DEV_IDEDMA is not set
479# CONFIG_BLK_DEV_HD is not set
480
481#
482# SCSI device support
483#
484# CONFIG_RAID_ATTRS is not set
485CONFIG_SCSI=y
486CONFIG_SCSI_DMA=y
487# CONFIG_SCSI_TGT is not set
488# CONFIG_SCSI_NETLINK is not set
489# CONFIG_SCSI_PROC_FS is not set
490
491#
492# SCSI support type (disk, tape, CD-ROM)
493#
494CONFIG_BLK_DEV_SD=y
495# CONFIG_CHR_DEV_ST is not set
496# CONFIG_CHR_DEV_OSST is not set
497# CONFIG_BLK_DEV_SR is not set
498# CONFIG_CHR_DEV_SG is not set
499# CONFIG_CHR_DEV_SCH is not set
500
501#
502# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
503#
504# CONFIG_SCSI_MULTI_LUN is not set
505# CONFIG_SCSI_CONSTANTS is not set
506# CONFIG_SCSI_LOGGING is not set
507# CONFIG_SCSI_SCAN_ASYNC is not set
508CONFIG_SCSI_WAIT_SCAN=m
509
510#
511# SCSI Transports
512#
513# CONFIG_SCSI_SPI_ATTRS is not set
514# CONFIG_SCSI_FC_ATTRS is not set
515# CONFIG_SCSI_ISCSI_ATTRS is not set
516# CONFIG_SCSI_SAS_ATTRS is not set
517# CONFIG_SCSI_SAS_LIBSAS is not set
518
519#
520# SCSI low-level drivers
521#
522# CONFIG_ISCSI_TCP is not set
523# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
524# CONFIG_SCSI_3W_9XXX is not set
525# CONFIG_SCSI_ACARD is not set
526# CONFIG_SCSI_AACRAID is not set
527# CONFIG_SCSI_AIC7XXX is not set
528# CONFIG_SCSI_AIC7XXX_OLD is not set
529# CONFIG_SCSI_AIC79XX is not set
530# CONFIG_SCSI_AIC94XX is not set
531# CONFIG_SCSI_DPT_I2O is not set
532# CONFIG_SCSI_ARCMSR is not set
533# CONFIG_MEGARAID_NEWGEN is not set
534# CONFIG_MEGARAID_LEGACY is not set
535# CONFIG_MEGARAID_SAS is not set
536# CONFIG_SCSI_HPTIOP is not set
537# CONFIG_SCSI_DMX3191D is not set
538# CONFIG_SCSI_FUTURE_DOMAIN is not set
539# CONFIG_SCSI_IPS is not set
540# CONFIG_SCSI_INITIO is not set
541# CONFIG_SCSI_INIA100 is not set
542# CONFIG_SCSI_STEX is not set
543# CONFIG_SCSI_SYM53C8XX_2 is not set
544# CONFIG_SCSI_QLOGIC_1280 is not set
545# CONFIG_SCSI_QLA_FC is not set
546# CONFIG_SCSI_QLA_ISCSI is not set
547# CONFIG_SCSI_LPFC is not set
548# CONFIG_SCSI_DC395x is not set
549# CONFIG_SCSI_DC390T is not set
550# CONFIG_SCSI_NSP32 is not set
551# CONFIG_SCSI_DEBUG is not set
552# CONFIG_SCSI_SRP is not set
553# CONFIG_ATA is not set
554# CONFIG_MD is not set
555
556#
557# Fusion MPT device support
558#
559# CONFIG_FUSION is not set
560# CONFIG_FUSION_SPI is not set
561# CONFIG_FUSION_FC is not set
562# CONFIG_FUSION_SAS is not set
563
564#
565# IEEE 1394 (FireWire) support
566#
567# CONFIG_FIREWIRE is not set
568# CONFIG_IEEE1394 is not set
569# CONFIG_I2O is not set
570CONFIG_NETDEVICES=y
571# CONFIG_NETDEVICES_MULTIQUEUE is not set
572# CONFIG_DUMMY is not set
573# CONFIG_BONDING is not set
574# CONFIG_MACVLAN is not set
575# CONFIG_EQUALIZER is not set
576# CONFIG_TUN is not set
577# CONFIG_ARCNET is not set
578# CONFIG_PHYLIB is not set
579CONFIG_NET_ETHERNET=y
580CONFIG_MII=y
581# CONFIG_AX88796 is not set
582# CONFIG_HAPPYMEAL is not set
583# CONFIG_SUNGEM is not set
584# CONFIG_CASSINI is not set
585# CONFIG_NET_VENDOR_3COM is not set
586# CONFIG_SMC91X is not set
587CONFIG_DM9000=y
588# CONFIG_SMC911X is not set
589# CONFIG_NET_TULIP is not set
590# CONFIG_HP100 is not set
591CONFIG_NET_PCI=y
592# CONFIG_PCNET32 is not set
593# CONFIG_AMD8111_ETH is not set
594# CONFIG_ADAPTEC_STARFIRE is not set
595# CONFIG_B44 is not set
596# CONFIG_FORCEDETH is not set
597# CONFIG_DGRS is not set
598# CONFIG_EEPRO100 is not set
599# CONFIG_E100 is not set
600# CONFIG_FEALNX is not set
601# CONFIG_NATSEMI is not set
602# CONFIG_NE2K_PCI is not set
603# CONFIG_8139CP is not set
604CONFIG_8139TOO=m
605# CONFIG_8139TOO_PIO is not set
606# CONFIG_8139TOO_TUNE_TWISTER is not set
607# CONFIG_8139TOO_8129 is not set
608# CONFIG_8139_OLD_RX_RESET is not set
609# CONFIG_SIS900 is not set
610# CONFIG_EPIC100 is not set
611# CONFIG_SUNDANCE is not set
612# CONFIG_TLAN is not set
613# CONFIG_VIA_RHINE is not set
614# CONFIG_SC92031 is not set
615CONFIG_NETDEV_1000=y
616# CONFIG_ACENIC is not set
617# CONFIG_DL2K is not set
618# CONFIG_E1000 is not set
619# CONFIG_NS83820 is not set
620# CONFIG_HAMACHI is not set
621# CONFIG_YELLOWFIN is not set
622# CONFIG_R8169 is not set
623# CONFIG_SIS190 is not set
624# CONFIG_SKGE is not set
625# CONFIG_SKY2 is not set
626# CONFIG_VIA_VELOCITY is not set
627# CONFIG_TIGON3 is not set
628# CONFIG_BNX2 is not set
629# CONFIG_QLA3XXX is not set
630# CONFIG_ATL1 is not set
631CONFIG_NETDEV_10000=y
632# CONFIG_CHELSIO_T1 is not set
633# CONFIG_CHELSIO_T3 is not set
634# CONFIG_IXGB is not set
635# CONFIG_S2IO is not set
636# CONFIG_MYRI10GE is not set
637# CONFIG_NETXEN_NIC is not set
638# CONFIG_MLX4_CORE is not set
639# CONFIG_TR is not set
640
641#
642# Wireless LAN
643#
644# CONFIG_WLAN_PRE80211 is not set
645# CONFIG_WLAN_80211 is not set
646
647#
648# USB Network Adapters
649#
650# CONFIG_USB_CATC is not set
651# CONFIG_USB_KAWETH is not set
652# CONFIG_USB_PEGASUS is not set
653# CONFIG_USB_RTL8150 is not set
654# CONFIG_USB_USBNET_MII is not set
655# CONFIG_USB_USBNET is not set
656# CONFIG_WAN is not set
657# CONFIG_FDDI is not set
658# CONFIG_HIPPI is not set
659# CONFIG_PPP is not set
660# CONFIG_SLIP is not set
661# CONFIG_NET_FC is not set
662# CONFIG_SHAPER is not set
663# CONFIG_NETCONSOLE is not set
664# CONFIG_NETPOLL is not set
665# CONFIG_NET_POLL_CONTROLLER is not set
666# CONFIG_ISDN is not set
667
668#
669# Input device support
670#
671CONFIG_INPUT=y
672# CONFIG_INPUT_FF_MEMLESS is not set
673# CONFIG_INPUT_POLLDEV is not set
674
675#
676# Userland interfaces
677#
678# CONFIG_INPUT_MOUSEDEV is not set
679# CONFIG_INPUT_JOYDEV is not set
680# CONFIG_INPUT_TSDEV is not set
681CONFIG_INPUT_EVDEV=y
682# CONFIG_INPUT_EVBUG is not set
683
684#
685# Input Device Drivers
686#
687# CONFIG_INPUT_KEYBOARD is not set
688# CONFIG_INPUT_MOUSE is not set
689# CONFIG_INPUT_JOYSTICK is not set
690# CONFIG_INPUT_TABLET is not set
691CONFIG_INPUT_TOUCHSCREEN=y
692# CONFIG_TOUCHSCREEN_GUNZE is not set
693# CONFIG_TOUCHSCREEN_ELO is not set
694# CONFIG_TOUCHSCREEN_MTOUCH is not set
695# CONFIG_TOUCHSCREEN_MK712 is not set
696# CONFIG_TOUCHSCREEN_PENMOUNT is not set
697# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
698# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
699CONFIG_TOUCHSCREEN_UCB1400=m
700# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
701# CONFIG_INPUT_MISC is not set
702
703#
704# Hardware I/O ports
705#
706# CONFIG_SERIO is not set
707# CONFIG_GAMEPORT is not set
708
709#
710# Character devices
711#
712CONFIG_VT=y
713CONFIG_VT_CONSOLE=y
714CONFIG_HW_CONSOLE=y
715# CONFIG_VT_HW_CONSOLE_BINDING is not set
716# CONFIG_SERIAL_NONSTANDARD is not set
717
718#
719# Serial drivers
720#
721# CONFIG_SERIAL_8250 is not set
722
723#
724# Non-8250 serial port support
725#
726CONFIG_SERIAL_PXA=y
727CONFIG_SERIAL_PXA_CONSOLE=y
728CONFIG_SERIAL_CORE=y
729CONFIG_SERIAL_CORE_CONSOLE=y
730# CONFIG_SERIAL_JSM is not set
731CONFIG_UNIX98_PTYS=y
732CONFIG_LEGACY_PTYS=y
733CONFIG_LEGACY_PTY_COUNT=256
734# CONFIG_IPMI_HANDLER is not set
735# CONFIG_WATCHDOG is not set
736CONFIG_HW_RANDOM=m
737# CONFIG_NVRAM is not set
738# CONFIG_R3964 is not set
739# CONFIG_APPLICOM is not set
740# CONFIG_DRM is not set
741# CONFIG_RAW_DRIVER is not set
742# CONFIG_TCG_TPM is not set
743CONFIG_DEVPORT=y
744# CONFIG_I2C is not set
745
746#
747# SPI support
748#
749# CONFIG_SPI is not set
750# CONFIG_SPI_MASTER is not set
751# CONFIG_W1 is not set
752# CONFIG_HWMON is not set
753CONFIG_MISC_DEVICES=y
754# CONFIG_PHANTOM is not set
755# CONFIG_EEPROM_93CX6 is not set
756# CONFIG_SGI_IOC4 is not set
757# CONFIG_TIFM_CORE is not set
758
759#
760# Multifunction device drivers
761#
762# CONFIG_MFD_SM501 is not set
763
764#
765# LED devices
766#
767CONFIG_NEW_LEDS=y
768CONFIG_LEDS_CLASS=y
769
770#
771# LED drivers
772#
773CONFIG_LEDS_CM_X270=y
774
775#
776# LED Triggers
777#
778CONFIG_LEDS_TRIGGERS=y
779# CONFIG_LEDS_TRIGGER_TIMER is not set
780# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
781CONFIG_LEDS_TRIGGER_HEARTBEAT=y
782
783#
784# Multimedia devices
785#
786# CONFIG_VIDEO_DEV is not set
787# CONFIG_DVB_CORE is not set
788CONFIG_DAB=y
789# CONFIG_USB_DABUSB is not set
790
791#
792# Graphics support
793#
794# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
795
796#
797# Display device support
798#
799# CONFIG_DISPLAY_SUPPORT is not set
800# CONFIG_VGASTATE is not set
801CONFIG_FB=y
802# CONFIG_FIRMWARE_EDID is not set
803# CONFIG_FB_DDC is not set
804CONFIG_FB_CFB_FILLRECT=y
805CONFIG_FB_CFB_COPYAREA=y
806CONFIG_FB_CFB_IMAGEBLIT=y
807# CONFIG_FB_SYS_FILLRECT is not set
808# CONFIG_FB_SYS_COPYAREA is not set
809# CONFIG_FB_SYS_IMAGEBLIT is not set
810# CONFIG_FB_SYS_FOPS is not set
811CONFIG_FB_DEFERRED_IO=y
812# CONFIG_FB_SVGALIB is not set
813# CONFIG_FB_MACMODES is not set
814# CONFIG_FB_BACKLIGHT is not set
815# CONFIG_FB_MODE_HELPERS is not set
816# CONFIG_FB_TILEBLITTING is not set
817
818#
819# Frame buffer hardware drivers
820#
821# CONFIG_FB_CIRRUS is not set
822# CONFIG_FB_PM2 is not set
823# CONFIG_FB_CYBER2000 is not set
824# CONFIG_FB_ASILIANT is not set
825# CONFIG_FB_IMSTT is not set
826# CONFIG_FB_S1D13XXX is not set
827# CONFIG_FB_NVIDIA is not set
828# CONFIG_FB_RIVA is not set
829# CONFIG_FB_MATROX is not set
830# CONFIG_FB_RADEON is not set
831# CONFIG_FB_ATY128 is not set
832# CONFIG_FB_ATY is not set
833# CONFIG_FB_S3 is not set
834# CONFIG_FB_SAVAGE is not set
835# CONFIG_FB_SIS is not set
836# CONFIG_FB_NEOMAGIC is not set
837# CONFIG_FB_KYRO is not set
838# CONFIG_FB_3DFX is not set
839# CONFIG_FB_VOODOO1 is not set
840# CONFIG_FB_VT8623 is not set
841# CONFIG_FB_TRIDENT is not set
842# CONFIG_FB_ARK is not set
843# CONFIG_FB_PM3 is not set
844CONFIG_FB_PXA=y
845# CONFIG_FB_PXA_PARAMETERS is not set
846CONFIG_FB_MBX=m
847# CONFIG_FB_VIRTUAL is not set
848
849#
850# Console display driver support
851#
852# CONFIG_VGA_CONSOLE is not set
853CONFIG_DUMMY_CONSOLE=y
854CONFIG_FRAMEBUFFER_CONSOLE=y
855# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
856# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
857# CONFIG_FONTS is not set
858CONFIG_FONT_8x8=y
859CONFIG_FONT_8x16=y
860CONFIG_LOGO=y
861CONFIG_LOGO_LINUX_MONO=y
862CONFIG_LOGO_LINUX_VGA16=y
863CONFIG_LOGO_LINUX_CLUT224=y
864
865#
866# Sound
867#
868CONFIG_SOUND=m
869
870#
871# Advanced Linux Sound Architecture
872#
873CONFIG_SND=m
874CONFIG_SND_TIMER=m
875CONFIG_SND_PCM=m
876# CONFIG_SND_SEQUENCER is not set
877CONFIG_SND_OSSEMUL=y
878CONFIG_SND_MIXER_OSS=m
879CONFIG_SND_PCM_OSS=m
880CONFIG_SND_PCM_OSS_PLUGINS=y
881# CONFIG_SND_DYNAMIC_MINORS is not set
882CONFIG_SND_SUPPORT_OLD_API=y
883CONFIG_SND_VERBOSE_PROCFS=y
884# CONFIG_SND_VERBOSE_PRINTK is not set
885# CONFIG_SND_DEBUG is not set
886
887#
888# Generic devices
889#
890CONFIG_SND_AC97_CODEC=m
891# CONFIG_SND_DUMMY is not set
892# CONFIG_SND_MTPAV is not set
893# CONFIG_SND_SERIAL_U16550 is not set
894# CONFIG_SND_MPU401 is not set
895
896#
897# PCI devices
898#
899# CONFIG_SND_AD1889 is not set
900# CONFIG_SND_ALS300 is not set
901# CONFIG_SND_ALI5451 is not set
902# CONFIG_SND_ATIIXP is not set
903# CONFIG_SND_ATIIXP_MODEM is not set
904# CONFIG_SND_AU8810 is not set
905# CONFIG_SND_AU8820 is not set
906# CONFIG_SND_AU8830 is not set
907# CONFIG_SND_AZT3328 is not set
908# CONFIG_SND_BT87X is not set
909# CONFIG_SND_CA0106 is not set
910# CONFIG_SND_CMIPCI is not set
911# CONFIG_SND_CS4281 is not set
912# CONFIG_SND_CS46XX is not set
913# CONFIG_SND_DARLA20 is not set
914# CONFIG_SND_GINA20 is not set
915# CONFIG_SND_LAYLA20 is not set
916# CONFIG_SND_DARLA24 is not set
917# CONFIG_SND_GINA24 is not set
918# CONFIG_SND_LAYLA24 is not set
919# CONFIG_SND_MONA is not set
920# CONFIG_SND_MIA is not set
921# CONFIG_SND_ECHO3G is not set
922# CONFIG_SND_INDIGO is not set
923# CONFIG_SND_INDIGOIO is not set
924# CONFIG_SND_INDIGODJ is not set
925# CONFIG_SND_EMU10K1 is not set
926# CONFIG_SND_EMU10K1X is not set
927# CONFIG_SND_ENS1370 is not set
928# CONFIG_SND_ENS1371 is not set
929# CONFIG_SND_ES1938 is not set
930# CONFIG_SND_ES1968 is not set
931# CONFIG_SND_FM801 is not set
932# CONFIG_SND_HDA_INTEL is not set
933# CONFIG_SND_HDSP is not set
934# CONFIG_SND_HDSPM is not set
935# CONFIG_SND_ICE1712 is not set
936# CONFIG_SND_ICE1724 is not set
937# CONFIG_SND_INTEL8X0 is not set
938# CONFIG_SND_INTEL8X0M is not set
939# CONFIG_SND_KORG1212 is not set
940# CONFIG_SND_MAESTRO3 is not set
941# CONFIG_SND_MIXART is not set
942# CONFIG_SND_NM256 is not set
943# CONFIG_SND_PCXHR is not set
944# CONFIG_SND_RIPTIDE is not set
945# CONFIG_SND_RME32 is not set
946# CONFIG_SND_RME96 is not set
947# CONFIG_SND_RME9652 is not set
948# CONFIG_SND_SONICVIBES is not set
949# CONFIG_SND_TRIDENT is not set
950# CONFIG_SND_VIA82XX is not set
951# CONFIG_SND_VIA82XX_MODEM is not set
952# CONFIG_SND_VX222 is not set
953# CONFIG_SND_YMFPCI is not set
954# CONFIG_SND_AC97_POWER_SAVE is not set
955
956#
957# ALSA ARM devices
958#
959CONFIG_SND_PXA2XX_PCM=m
960CONFIG_SND_PXA2XX_AC97=m
961
962#
963# USB devices
964#
965# CONFIG_SND_USB_AUDIO is not set
966# CONFIG_SND_USB_CAIAQ is not set
967
968#
969# System on Chip audio support
970#
971# CONFIG_SND_SOC is not set
972
973#
974# Open Sound System
975#
976# CONFIG_SOUND_PRIME is not set
977CONFIG_AC97_BUS=m
978CONFIG_HID_SUPPORT=y
979CONFIG_HID=y
980# CONFIG_HID_DEBUG is not set
981
982#
983# USB Input Devices
984#
985CONFIG_USB_HID=y
986# CONFIG_USB_HIDINPUT_POWERBOOK is not set
987# CONFIG_HID_FF is not set
988# CONFIG_USB_HIDDEV is not set
989CONFIG_USB_SUPPORT=y
990CONFIG_USB_ARCH_HAS_HCD=y
991CONFIG_USB_ARCH_HAS_OHCI=y
992CONFIG_USB_ARCH_HAS_EHCI=y
993CONFIG_USB=y
994# CONFIG_USB_DEBUG is not set
995
996#
997# Miscellaneous USB options
998#
999CONFIG_USB_DEVICEFS=y
1000# CONFIG_USB_DEVICE_CLASS is not set
1001# CONFIG_USB_DYNAMIC_MINORS is not set
1002# CONFIG_USB_SUSPEND is not set
1003# CONFIG_USB_PERSIST is not set
1004# CONFIG_USB_OTG is not set
1005
1006#
1007# USB Host Controller Drivers
1008#
1009# CONFIG_USB_EHCI_HCD is not set
1010# CONFIG_USB_ISP116X_HCD is not set
1011CONFIG_USB_OHCI_HCD=y
1012# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1013# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1014CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1015# CONFIG_USB_UHCI_HCD is not set
1016# CONFIG_USB_SL811_HCD is not set
1017# CONFIG_USB_R8A66597_HCD is not set
1018
1019#
1020# USB Device Class drivers
1021#
1022# CONFIG_USB_ACM is not set
1023# CONFIG_USB_PRINTER is not set
1024
1025#
1026# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1027#
1028
1029#
1030# may also be needed; see USB_STORAGE Help for more information
1031#
1032CONFIG_USB_STORAGE=y
1033# CONFIG_USB_STORAGE_DEBUG is not set
1034# CONFIG_USB_STORAGE_DATAFAB is not set
1035# CONFIG_USB_STORAGE_FREECOM is not set
1036# CONFIG_USB_STORAGE_DPCM is not set
1037# CONFIG_USB_STORAGE_USBAT is not set
1038# CONFIG_USB_STORAGE_SDDR09 is not set
1039# CONFIG_USB_STORAGE_SDDR55 is not set
1040# CONFIG_USB_STORAGE_JUMPSHOT is not set
1041# CONFIG_USB_STORAGE_ALAUDA is not set
1042# CONFIG_USB_STORAGE_KARMA is not set
1043# CONFIG_USB_LIBUSUAL is not set
1044
1045#
1046# USB Imaging devices
1047#
1048# CONFIG_USB_MDC800 is not set
1049# CONFIG_USB_MICROTEK is not set
1050CONFIG_USB_MON=y
1051
1052#
1053# USB port drivers
1054#
1055
1056#
1057# USB Serial Converter support
1058#
1059# CONFIG_USB_SERIAL is not set
1060
1061#
1062# USB Miscellaneous drivers
1063#
1064# CONFIG_USB_EMI62 is not set
1065# CONFIG_USB_EMI26 is not set
1066# CONFIG_USB_ADUTUX is not set
1067# CONFIG_USB_AUERSWALD is not set
1068# CONFIG_USB_RIO500 is not set
1069# CONFIG_USB_LEGOTOWER is not set
1070# CONFIG_USB_LCD is not set
1071# CONFIG_USB_BERRY_CHARGE is not set
1072# CONFIG_USB_LED is not set
1073# CONFIG_USB_CYPRESS_CY7C63 is not set
1074# CONFIG_USB_CYTHERM is not set
1075# CONFIG_USB_PHIDGET is not set
1076# CONFIG_USB_IDMOUSE is not set
1077# CONFIG_USB_FTDI_ELAN is not set
1078# CONFIG_USB_APPLEDISPLAY is not set
1079# CONFIG_USB_LD is not set
1080# CONFIG_USB_TRANCEVIBRATOR is not set
1081# CONFIG_USB_IOWARRIOR is not set
1082# CONFIG_USB_TEST is not set
1083
1084#
1085# USB DSL modem support
1086#
1087
1088#
1089# USB Gadget Support
1090#
1091# CONFIG_USB_GADGET is not set
1092CONFIG_MMC=m
1093# CONFIG_MMC_DEBUG is not set
1094# CONFIG_MMC_UNSAFE_RESUME is not set
1095
1096#
1097# MMC/SD Card Drivers
1098#
1099CONFIG_MMC_BLOCK=m
1100CONFIG_MMC_BLOCK_BOUNCE=y
1101
1102#
1103# MMC/SD Host Controller Drivers
1104#
1105CONFIG_MMC_PXA=m
1106# CONFIG_MMC_SDHCI is not set
1107# CONFIG_MMC_TIFM_SD is not set
1108
1109#
1110# Real Time Clock
1111#
1112CONFIG_RTC_LIB=y
1113CONFIG_RTC_CLASS=y
1114CONFIG_RTC_HCTOSYS=y
1115CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1116# CONFIG_RTC_DEBUG is not set
1117
1118#
1119# RTC interfaces
1120#
1121CONFIG_RTC_INTF_SYSFS=y
1122CONFIG_RTC_INTF_PROC=y
1123CONFIG_RTC_INTF_DEV=y
1124# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1125# CONFIG_RTC_DRV_TEST is not set
1126
1127#
1128# Platform RTC drivers
1129#
1130# CONFIG_RTC_DRV_CMOS is not set
1131# CONFIG_RTC_DRV_DS1553 is not set
1132# CONFIG_RTC_DRV_DS1742 is not set
1133# CONFIG_RTC_DRV_M48T86 is not set
1134# CONFIG_RTC_DRV_M48T59 is not set
1135CONFIG_RTC_DRV_V3020=y
1136
1137#
1138# on-CPU RTC drivers
1139#
1140CONFIG_RTC_DRV_SA1100=y
1141
1142#
1143# DMA Engine support
1144#
1145# CONFIG_DMA_ENGINE is not set
1146
1147#
1148# DMA Clients
1149#
1150
1151#
1152# DMA Devices
1153#
1154
1155#
1156# File systems
1157#
1158CONFIG_EXT2_FS=y
1159# CONFIG_EXT2_FS_XATTR is not set
1160# CONFIG_EXT2_FS_XIP is not set
1161CONFIG_EXT3_FS=y
1162CONFIG_EXT3_FS_XATTR=y
1163# CONFIG_EXT3_FS_POSIX_ACL is not set
1164# CONFIG_EXT3_FS_SECURITY is not set
1165# CONFIG_EXT4DEV_FS is not set
1166CONFIG_JBD=y
1167# CONFIG_JBD_DEBUG is not set
1168CONFIG_FS_MBCACHE=y
1169# CONFIG_REISERFS_FS is not set
1170# CONFIG_JFS_FS is not set
1171# CONFIG_FS_POSIX_ACL is not set
1172# CONFIG_XFS_FS is not set
1173# CONFIG_GFS2_FS is not set
1174# CONFIG_OCFS2_FS is not set
1175# CONFIG_MINIX_FS is not set
1176# CONFIG_ROMFS_FS is not set
1177CONFIG_INOTIFY=y
1178CONFIG_INOTIFY_USER=y
1179# CONFIG_QUOTA is not set
1180CONFIG_DNOTIFY=y
1181# CONFIG_AUTOFS_FS is not set
1182# CONFIG_AUTOFS4_FS is not set
1183# CONFIG_FUSE_FS is not set
1184
1185#
1186# CD-ROM/DVD Filesystems
1187#
1188# CONFIG_ISO9660_FS is not set
1189# CONFIG_UDF_FS is not set
1190
1191#
1192# DOS/FAT/NT Filesystems
1193#
1194CONFIG_FAT_FS=y
1195CONFIG_MSDOS_FS=y
1196CONFIG_VFAT_FS=y
1197CONFIG_FAT_DEFAULT_CODEPAGE=437
1198CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1199# CONFIG_NTFS_FS is not set
1200
1201#
1202# Pseudo filesystems
1203#
1204CONFIG_PROC_FS=y
1205CONFIG_PROC_SYSCTL=y
1206CONFIG_SYSFS=y
1207CONFIG_TMPFS=y
1208# CONFIG_TMPFS_POSIX_ACL is not set
1209# CONFIG_HUGETLB_PAGE is not set
1210CONFIG_RAMFS=y
1211# CONFIG_CONFIGFS_FS is not set
1212
1213#
1214# Miscellaneous filesystems
1215#
1216# CONFIG_ADFS_FS is not set
1217# CONFIG_AFFS_FS is not set
1218# CONFIG_HFS_FS is not set
1219# CONFIG_HFSPLUS_FS is not set
1220# CONFIG_BEFS_FS is not set
1221# CONFIG_BFS_FS is not set
1222# CONFIG_EFS_FS is not set
1223# CONFIG_JFFS2_FS is not set
1224# CONFIG_CRAMFS is not set
1225# CONFIG_VXFS_FS is not set
1226# CONFIG_HPFS_FS is not set
1227# CONFIG_QNX4FS_FS is not set
1228# CONFIG_SYSV_FS is not set
1229# CONFIG_UFS_FS is not set
1230
1231#
1232# Network File Systems
1233#
1234CONFIG_NFS_FS=y
1235CONFIG_NFS_V3=y
1236# CONFIG_NFS_V3_ACL is not set
1237# CONFIG_NFS_V4 is not set
1238# CONFIG_NFS_DIRECTIO is not set
1239# CONFIG_NFSD is not set
1240CONFIG_ROOT_NFS=y
1241CONFIG_LOCKD=y
1242CONFIG_LOCKD_V4=y
1243CONFIG_NFS_COMMON=y
1244CONFIG_SUNRPC=y
1245# CONFIG_SUNRPC_BIND34 is not set
1246# CONFIG_RPCSEC_GSS_KRB5 is not set
1247# CONFIG_RPCSEC_GSS_SPKM3 is not set
1248CONFIG_SMB_FS=y
1249# CONFIG_SMB_NLS_DEFAULT is not set
1250# CONFIG_CIFS is not set
1251# CONFIG_NCP_FS is not set
1252# CONFIG_CODA_FS is not set
1253# CONFIG_AFS_FS is not set
1254
1255#
1256# Partition Types
1257#
1258# CONFIG_PARTITION_ADVANCED is not set
1259CONFIG_MSDOS_PARTITION=y
1260
1261#
1262# Native Language Support
1263#
1264CONFIG_NLS=y
1265CONFIG_NLS_DEFAULT="iso8859-1"
1266CONFIG_NLS_CODEPAGE_437=y
1267# CONFIG_NLS_CODEPAGE_737 is not set
1268# CONFIG_NLS_CODEPAGE_775 is not set
1269# CONFIG_NLS_CODEPAGE_850 is not set
1270# CONFIG_NLS_CODEPAGE_852 is not set
1271# CONFIG_NLS_CODEPAGE_855 is not set
1272# CONFIG_NLS_CODEPAGE_857 is not set
1273# CONFIG_NLS_CODEPAGE_860 is not set
1274# CONFIG_NLS_CODEPAGE_861 is not set
1275# CONFIG_NLS_CODEPAGE_862 is not set
1276# CONFIG_NLS_CODEPAGE_863 is not set
1277# CONFIG_NLS_CODEPAGE_864 is not set
1278# CONFIG_NLS_CODEPAGE_865 is not set
1279# CONFIG_NLS_CODEPAGE_866 is not set
1280# CONFIG_NLS_CODEPAGE_869 is not set
1281# CONFIG_NLS_CODEPAGE_936 is not set
1282# CONFIG_NLS_CODEPAGE_950 is not set
1283# CONFIG_NLS_CODEPAGE_932 is not set
1284# CONFIG_NLS_CODEPAGE_949 is not set
1285# CONFIG_NLS_CODEPAGE_874 is not set
1286# CONFIG_NLS_ISO8859_8 is not set
1287# CONFIG_NLS_CODEPAGE_1250 is not set
1288# CONFIG_NLS_CODEPAGE_1251 is not set
1289# CONFIG_NLS_ASCII is not set
1290CONFIG_NLS_ISO8859_1=y
1291# CONFIG_NLS_ISO8859_2 is not set
1292# CONFIG_NLS_ISO8859_3 is not set
1293# CONFIG_NLS_ISO8859_4 is not set
1294# CONFIG_NLS_ISO8859_5 is not set
1295# CONFIG_NLS_ISO8859_6 is not set
1296# CONFIG_NLS_ISO8859_7 is not set
1297# CONFIG_NLS_ISO8859_9 is not set
1298# CONFIG_NLS_ISO8859_13 is not set
1299# CONFIG_NLS_ISO8859_14 is not set
1300# CONFIG_NLS_ISO8859_15 is not set
1301# CONFIG_NLS_KOI8_R is not set
1302# CONFIG_NLS_KOI8_U is not set
1303# CONFIG_NLS_UTF8 is not set
1304
1305#
1306# Distributed Lock Manager
1307#
1308# CONFIG_DLM is not set
1309
1310#
1311# Profiling support
1312#
1313# CONFIG_PROFILING is not set
1314
1315#
1316# Kernel hacking
1317#
1318# CONFIG_PRINTK_TIME is not set
1319CONFIG_ENABLE_MUST_CHECK=y
1320CONFIG_MAGIC_SYSRQ=y
1321# CONFIG_UNUSED_SYMBOLS is not set
1322# CONFIG_DEBUG_FS is not set
1323# CONFIG_HEADERS_CHECK is not set
1324CONFIG_DEBUG_KERNEL=y
1325# CONFIG_DEBUG_SHIRQ is not set
1326# CONFIG_DETECT_SOFTLOCKUP is not set
1327CONFIG_SCHED_DEBUG=y
1328# CONFIG_SCHEDSTATS is not set
1329# CONFIG_TIMER_STATS is not set
1330# CONFIG_DEBUG_SLAB is not set
1331# CONFIG_DEBUG_RT_MUTEXES is not set
1332# CONFIG_RT_MUTEX_TESTER is not set
1333# CONFIG_DEBUG_SPINLOCK is not set
1334# CONFIG_DEBUG_MUTEXES is not set
1335# CONFIG_DEBUG_LOCK_ALLOC is not set
1336# CONFIG_PROVE_LOCKING is not set
1337# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1338# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1339# CONFIG_DEBUG_KOBJECT is not set
1340# CONFIG_DEBUG_BUGVERBOSE is not set
1341CONFIG_DEBUG_INFO=y
1342# CONFIG_DEBUG_VM is not set
1343# CONFIG_DEBUG_LIST is not set
1344CONFIG_FRAME_POINTER=y
1345CONFIG_FORCED_INLINING=y
1346# CONFIG_RCU_TORTURE_TEST is not set
1347# CONFIG_FAULT_INJECTION is not set
1348CONFIG_DEBUG_USER=y
1349CONFIG_DEBUG_ERRORS=y
1350CONFIG_DEBUG_LL=y
1351# CONFIG_DEBUG_ICEDCC is not set
1352
1353#
1354# Security options
1355#
1356# CONFIG_KEYS is not set
1357# CONFIG_SECURITY is not set
1358CONFIG_CRYPTO=y
1359CONFIG_CRYPTO_ALGAPI=m
1360CONFIG_CRYPTO_BLKCIPHER=m
1361CONFIG_CRYPTO_MANAGER=m
1362# CONFIG_CRYPTO_HMAC is not set
1363# CONFIG_CRYPTO_XCBC is not set
1364# CONFIG_CRYPTO_NULL is not set
1365# CONFIG_CRYPTO_MD4 is not set
1366# CONFIG_CRYPTO_MD5 is not set
1367# CONFIG_CRYPTO_SHA1 is not set
1368# CONFIG_CRYPTO_SHA256 is not set
1369# CONFIG_CRYPTO_SHA512 is not set
1370# CONFIG_CRYPTO_WP512 is not set
1371# CONFIG_CRYPTO_TGR192 is not set
1372# CONFIG_CRYPTO_GF128MUL is not set
1373CONFIG_CRYPTO_ECB=m
1374CONFIG_CRYPTO_CBC=m
1375CONFIG_CRYPTO_PCBC=m
1376# CONFIG_CRYPTO_LRW is not set
1377# CONFIG_CRYPTO_CRYPTD is not set
1378# CONFIG_CRYPTO_DES is not set
1379# CONFIG_CRYPTO_FCRYPT is not set
1380# CONFIG_CRYPTO_BLOWFISH is not set
1381# CONFIG_CRYPTO_TWOFISH is not set
1382# CONFIG_CRYPTO_SERPENT is not set
1383CONFIG_CRYPTO_AES=m
1384# CONFIG_CRYPTO_CAST5 is not set
1385# CONFIG_CRYPTO_CAST6 is not set
1386# CONFIG_CRYPTO_TEA is not set
1387CONFIG_CRYPTO_ARC4=m
1388# CONFIG_CRYPTO_KHAZAD is not set
1389# CONFIG_CRYPTO_ANUBIS is not set
1390# CONFIG_CRYPTO_DEFLATE is not set
1391# CONFIG_CRYPTO_MICHAEL_MIC is not set
1392# CONFIG_CRYPTO_CRC32C is not set
1393# CONFIG_CRYPTO_CAMELLIA is not set
1394# CONFIG_CRYPTO_TEST is not set
1395CONFIG_CRYPTO_HW=y
1396
1397#
1398# Library routines
1399#
1400CONFIG_BITREVERSE=y
1401# CONFIG_CRC_CCITT is not set
1402# CONFIG_CRC16 is not set
1403# CONFIG_CRC_ITU_T is not set
1404CONFIG_CRC32=y
1405# CONFIG_CRC7 is not set
1406# CONFIG_LIBCRC32C is not set
1407CONFIG_PLIST=y
1408CONFIG_HAS_IOMEM=y
1409CONFIG_HAS_IOPORT=y
1410CONFIG_HAS_DMA=y
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index a2dd930d11ef..e5747547b44c 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -279,6 +279,25 @@ static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
279} 279}
280DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693); 280DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
281 281
282static void __init pci_fixup_it8152(struct pci_dev *dev)
283{
284 int i;
285 /* fixup for ITE 8152 devices */
286 /* FIXME: add defines for class 0x68000 and 0x80103 */
287 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
288 dev->class == 0x68000 ||
289 dev->class == 0x80103) {
290 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
291 dev->resource[i].start = 0;
292 dev->resource[i].end = 0;
293 dev->resource[i].flags = 0;
294 }
295 }
296}
297DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
298
299
300
282void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) 301void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
283{ 302{
284 if (debug_pci) 303 if (debug_pci)
@@ -292,9 +311,12 @@ void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
292 */ 311 */
293static inline int pdev_bad_for_parity(struct pci_dev *dev) 312static inline int pdev_bad_for_parity(struct pci_dev *dev)
294{ 313{
295 return (dev->vendor == PCI_VENDOR_ID_INTERG && 314 return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
296 (dev->device == PCI_DEVICE_ID_INTERG_2000 || 315 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
297 dev->device == PCI_DEVICE_ID_INTERG_2010)); 316 dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
317 (dev->vendor == PCI_VENDOR_ID_ITE &&
318 dev->device == PCI_DEVICE_ID_ITE_8152));
319
298} 320}
299 321
300/* 322/*
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 5ebec6d88b51..656d49661a29 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -1,6 +1,24 @@
1if ARCH_PXA 1if ARCH_PXA
2 2
3menu "Intel PXA2xx Implementations" 3menu "Intel PXA2xx/PXA3xx Implementations"
4
5if PXA3xx
6
7menu "Supported PXA3xx Processor Variants"
8
9config CPU_PXA300
10 bool "PXA300 (codename Monahans-L)"
11
12config CPU_PXA310
13 bool "PXA310 (codename Monahans-LV)"
14 select CPU_PXA300
15
16config CPU_PXA320
17 bool "PXA320 (codename Monahans-P)"
18
19endmenu
20
21endif
4 22
5choice 23choice
6 prompt "Select target board" 24 prompt "Select target board"
@@ -41,6 +59,15 @@ config MACH_EM_X270
41 bool "CompuLab EM-x270 platform" 59 bool "CompuLab EM-x270 platform"
42 select PXA27x 60 select PXA27x
43 61
62config MACH_ZYLONITE
63 bool "PXA3xx Development Platform"
64 select PXA3xx
65
66config MACH_ARMCORE
67 bool "CompuLab CM-X270 modules"
68 select PXA27x
69 select IWMMXT
70
44endchoice 71endchoice
45 72
46if PXA_SHARPSL 73if PXA_SHARPSL
@@ -130,6 +157,11 @@ config PXA27x
130 help 157 help
131 Select code specific to PXA27x variants 158 Select code specific to PXA27x variants
132 159
160config PXA3xx
161 bool
162 help
163 Select code specific to PXA3xx variants
164
133config PXA_SHARP_C7xx 165config PXA_SHARP_C7xx
134 bool 166 bool
135 select PXA_SSP 167 select PXA_SSP
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 7d6ab5c59ab9..4263527e5123 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -3,36 +3,51 @@
3# 3#
4 4
5# Common support (must be linked before board specific support) 5# Common support (must be linked before board specific support)
6obj-y += clock.o generic.o irq.o dma.o time.o 6obj-y += clock.o generic.o irq.o dma.o time.o
7obj-$(CONFIG_PXA25x) += pxa25x.o 7obj-$(CONFIG_PXA25x) += pxa25x.o
8obj-$(CONFIG_PXA27x) += pxa27x.o 8obj-$(CONFIG_PXA27x) += pxa27x.o
9obj-$(CONFIG_PXA3xx) += pxa3xx.o mfp.o
10obj-$(CONFIG_CPU_PXA300) += pxa300.o
11obj-$(CONFIG_CPU_PXA320) += pxa320.o
9 12
10# Specific board support 13# Specific board support
11obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o 14obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o
12obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o 15obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o
13obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o 16obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o
14obj-$(CONFIG_ARCH_PXA_IDP) += idp.o 17obj-$(CONFIG_ARCH_PXA_IDP) += idp.o
15obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o 18obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o
16obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o 19obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o corgi_pm.o
17obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o 20obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o corgi_ssp.o corgi_lcd.o sharpsl_pm.o spitz_pm.o
18obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o 21obj-$(CONFIG_MACH_AKITA) += akita-ioexp.o
19obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o 22obj-$(CONFIG_MACH_POODLE) += poodle.o corgi_ssp.o
20obj-$(CONFIG_MACH_TOSA) += tosa.o 23obj-$(CONFIG_MACH_TOSA) += tosa.o
21obj-$(CONFIG_MACH_EM_X270) += em-x270.o 24obj-$(CONFIG_MACH_EM_X270) += em-x270.o
25
26ifeq ($(CONFIG_MACH_ZYLONITE),y)
27 obj-y += zylonite.o
28 obj-$(CONFIG_CPU_PXA300) += zylonite_pxa300.o
29 obj-$(CONFIG_CPU_PXA320) += zylonite_pxa320.o
30endif
31
32obj-$(CONFIG_MACH_ARMCORE) += cm-x270.o
22 33
23# Support for blinky lights 34# Support for blinky lights
24led-y := leds.o 35led-y := leds.o
25led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o 36led-$(CONFIG_ARCH_LUBBOCK) += leds-lubbock.o
26led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o 37led-$(CONFIG_MACH_MAINSTONE) += leds-mainstone.o
27led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o 38led-$(CONFIG_ARCH_PXA_IDP) += leds-idp.o
28led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o 39led-$(CONFIG_MACH_TRIZEPS4) += leds-trizeps4.o
29 40
30obj-$(CONFIG_LEDS) += $(led-y) 41obj-$(CONFIG_LEDS) += $(led-y)
31 42
32# Misc features 43# Misc features
33obj-$(CONFIG_PM) += pm.o sleep.o 44obj-$(CONFIG_PM) += pm.o sleep.o
34obj-$(CONFIG_PXA_SSP) += ssp.o 45obj-$(CONFIG_PXA_SSP) += ssp.o
35 46
36ifeq ($(CONFIG_PXA27x),y) 47ifeq ($(CONFIG_PXA27x),y)
37obj-$(CONFIG_PM) += standby.o 48obj-$(CONFIG_PM) += standby.o
49endif
50
51ifeq ($(CONFIG_PCI),y)
52obj-$(CONFIG_MACH_ARMCORE) += cm-x270-pci.o
38endif 53endif
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index 34a31caa6f9d..83ef5ecaf432 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -9,19 +9,15 @@
9#include <linux/string.h> 9#include <linux/string.h>
10#include <linux/clk.h> 10#include <linux/clk.h>
11#include <linux/spinlock.h> 11#include <linux/spinlock.h>
12#include <linux/platform_device.h>
13#include <linux/delay.h>
12 14
13#include <asm/arch/pxa-regs.h> 15#include <asm/arch/pxa-regs.h>
14#include <asm/hardware.h> 16#include <asm/hardware.h>
15 17
16struct clk { 18#include "devices.h"
17 struct list_head node; 19#include "generic.h"
18 unsigned long rate; 20#include "clock.h"
19 struct module *owner;
20 const char *name;
21 unsigned int enabled;
22 void (*enable)(void);
23 void (*disable)(void);
24};
25 21
26static LIST_HEAD(clocks); 22static LIST_HEAD(clocks);
27static DEFINE_MUTEX(clocks_mutex); 23static DEFINE_MUTEX(clocks_mutex);
@@ -33,7 +29,8 @@ struct clk *clk_get(struct device *dev, const char *id)
33 29
34 mutex_lock(&clocks_mutex); 30 mutex_lock(&clocks_mutex);
35 list_for_each_entry(p, &clocks, node) { 31 list_for_each_entry(p, &clocks, node) {
36 if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { 32 if (strcmp(id, p->name) == 0 &&
33 (p->dev == NULL || p->dev == dev)) {
37 clk = p; 34 clk = p;
38 break; 35 break;
39 } 36 }
@@ -46,7 +43,6 @@ EXPORT_SYMBOL(clk_get);
46 43
47void clk_put(struct clk *clk) 44void clk_put(struct clk *clk)
48{ 45{
49 module_put(clk->owner);
50} 46}
51EXPORT_SYMBOL(clk_put); 47EXPORT_SYMBOL(clk_put);
52 48
@@ -56,8 +52,12 @@ int clk_enable(struct clk *clk)
56 52
57 spin_lock_irqsave(&clocks_lock, flags); 53 spin_lock_irqsave(&clocks_lock, flags);
58 if (clk->enabled++ == 0) 54 if (clk->enabled++ == 0)
59 clk->enable(); 55 clk->ops->enable(clk);
60 spin_unlock_irqrestore(&clocks_lock, flags); 56 spin_unlock_irqrestore(&clocks_lock, flags);
57
58 if (clk->delay)
59 udelay(clk->delay);
60
61 return 0; 61 return 0;
62} 62}
63EXPORT_SYMBOL(clk_enable); 63EXPORT_SYMBOL(clk_enable);
@@ -70,54 +70,75 @@ void clk_disable(struct clk *clk)
70 70
71 spin_lock_irqsave(&clocks_lock, flags); 71 spin_lock_irqsave(&clocks_lock, flags);
72 if (--clk->enabled == 0) 72 if (--clk->enabled == 0)
73 clk->disable(); 73 clk->ops->disable(clk);
74 spin_unlock_irqrestore(&clocks_lock, flags); 74 spin_unlock_irqrestore(&clocks_lock, flags);
75} 75}
76EXPORT_SYMBOL(clk_disable); 76EXPORT_SYMBOL(clk_disable);
77 77
78unsigned long clk_get_rate(struct clk *clk) 78unsigned long clk_get_rate(struct clk *clk)
79{ 79{
80 return clk->rate; 80 unsigned long rate;
81
82 rate = clk->rate;
83 if (clk->ops->getrate)
84 rate = clk->ops->getrate(clk);
85
86 return rate;
81} 87}
82EXPORT_SYMBOL(clk_get_rate); 88EXPORT_SYMBOL(clk_get_rate);
83 89
84 90
85static void clk_gpio27_enable(void) 91static void clk_gpio27_enable(struct clk *clk)
86{ 92{
87 pxa_gpio_mode(GPIO11_3_6MHz_MD); 93 pxa_gpio_mode(GPIO11_3_6MHz_MD);
88} 94}
89 95
90static void clk_gpio27_disable(void) 96static void clk_gpio27_disable(struct clk *clk)
91{ 97{
92} 98}
93 99
94static struct clk clk_gpio27 = { 100static const struct clkops clk_gpio27_ops = {
95 .name = "GPIO27_CLK",
96 .rate = 3686400,
97 .enable = clk_gpio27_enable, 101 .enable = clk_gpio27_enable,
98 .disable = clk_gpio27_disable, 102 .disable = clk_gpio27_disable,
99}; 103};
100 104
101int clk_register(struct clk *clk) 105
106void clk_cken_enable(struct clk *clk)
102{ 107{
103 mutex_lock(&clocks_mutex); 108 CKEN |= 1 << clk->cken;
104 list_add(&clk->node, &clocks);
105 mutex_unlock(&clocks_mutex);
106 return 0;
107} 109}
108EXPORT_SYMBOL(clk_register);
109 110
110void clk_unregister(struct clk *clk) 111void clk_cken_disable(struct clk *clk)
111{ 112{
113 CKEN &= ~(1 << clk->cken);
114}
115
116const struct clkops clk_cken_ops = {
117 .enable = clk_cken_enable,
118 .disable = clk_cken_disable,
119};
120
121static struct clk common_clks[] = {
122 {
123 .name = "GPIO27_CLK",
124 .ops = &clk_gpio27_ops,
125 .rate = 3686400,
126 },
127};
128
129void clks_register(struct clk *clks, size_t num)
130{
131 int i;
132
112 mutex_lock(&clocks_mutex); 133 mutex_lock(&clocks_mutex);
113 list_del(&clk->node); 134 for (i = 0; i < num; i++)
135 list_add(&clks[i].node, &clocks);
114 mutex_unlock(&clocks_mutex); 136 mutex_unlock(&clocks_mutex);
115} 137}
116EXPORT_SYMBOL(clk_unregister);
117 138
118static int __init clk_init(void) 139static int __init clk_init(void)
119{ 140{
120 clk_register(&clk_gpio27); 141 clks_register(common_clks, ARRAY_SIZE(common_clks));
121 return 0; 142 return 0;
122} 143}
123arch_initcall(clk_init); 144arch_initcall(clk_init);
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
new file mode 100644
index 000000000000..bc6b77e1592e
--- /dev/null
+++ b/arch/arm/mach-pxa/clock.h
@@ -0,0 +1,43 @@
1struct clk;
2
3struct clkops {
4 void (*enable)(struct clk *);
5 void (*disable)(struct clk *);
6 unsigned long (*getrate)(struct clk *);
7};
8
9struct clk {
10 struct list_head node;
11 const char *name;
12 struct device *dev;
13 const struct clkops *ops;
14 unsigned long rate;
15 unsigned int cken;
16 unsigned int delay;
17 unsigned int enabled;
18};
19
20#define INIT_CKEN(_name, _cken, _rate, _delay, _dev) \
21 { \
22 .name = _name, \
23 .dev = _dev, \
24 .ops = &clk_cken_ops, \
25 .rate = _rate, \
26 .cken = CKEN_##_cken, \
27 .delay = _delay, \
28 }
29
30#define INIT_CK(_name, _cken, _ops, _dev) \
31 { \
32 .name = _name, \
33 .dev = _dev, \
34 .ops = _ops, \
35 .cken = CKEN_##_cken, \
36 }
37
38extern const struct clkops clk_cken_ops;
39
40void clk_cken_enable(struct clk *clk);
41void clk_cken_disable(struct clk *clk);
42
43void clks_register(struct clk *clks, size_t num);
diff --git a/arch/arm/mach-pxa/cm-x270-pci.c b/arch/arm/mach-pxa/cm-x270-pci.c
new file mode 100644
index 000000000000..878d3b9b8633
--- /dev/null
+++ b/arch/arm/mach-pxa/cm-x270-pci.c
@@ -0,0 +1,218 @@
1/*
2 * linux/arch/arm/mach-pxa/cm-x270-pci.c
3 *
4 * PCI bios-type initialisation for PCI machines
5 *
6 * Bits taken from various places.
7 *
8 * Copyright (C) 2007 Compulab, Ltd.
9 * Mike Rapoport <mike@compulab.co.il>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/device.h>
20#include <linux/platform_device.h>
21#include <linux/irq.h>
22
23#include <asm/mach/pci.h>
24#include <asm/arch/cm-x270.h>
25#include <asm/arch/pxa-regs.h>
26#include <asm/mach-types.h>
27
28#include <asm/hardware/it8152.h>
29
30unsigned long it8152_base_address = CMX270_IT8152_VIRT;
31
32/*
33 * Only first 64MB of memory can be accessed via PCI.
34 * We use GFP_DMA to allocate safe buffers to do map/unmap.
35 * This is really ugly and we need a better way of specifying
36 * DMA-capable regions of memory.
37 */
38void __init cmx270_pci_adjust_zones(int node, unsigned long *zone_size,
39 unsigned long *zhole_size)
40{
41 unsigned int sz = SZ_64M >> PAGE_SHIFT;
42
43 printk(KERN_INFO "Adjusting zones for CM-x270\n");
44
45 /*
46 * Only adjust if > 64M on current system
47 */
48 if (node || (zone_size[0] <= sz))
49 return;
50
51 zone_size[1] = zone_size[0] - sz;
52 zone_size[0] = sz;
53 zhole_size[1] = zhole_size[0];
54 zhole_size[0] = 0;
55}
56
57static void cmx270_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
58{
59 /* clear our parent irq */
60 GEDR(GPIO_IT8152_IRQ) = GPIO_bit(GPIO_IT8152_IRQ);
61
62 it8152_irq_demux(irq, desc);
63}
64
65void __cmx270_pci_init_irq(void)
66{
67 it8152_init_irq();
68 pxa_gpio_mode(IRQ_TO_GPIO(GPIO_IT8152_IRQ));
69 set_irq_type(IRQ_GPIO(GPIO_IT8152_IRQ), IRQT_RISING);
70
71 set_irq_chained_handler(IRQ_GPIO(GPIO_IT8152_IRQ),
72 cmx270_it8152_irq_demux);
73}
74
75#ifdef CONFIG_PM
76static unsigned long sleep_save_ite[10];
77
78void __cmx270_pci_suspend(void)
79{
80 /* save ITE state */
81 sleep_save_ite[0] = __raw_readl(IT8152_INTC_PDCNIMR);
82 sleep_save_ite[1] = __raw_readl(IT8152_INTC_LPCNIMR);
83 sleep_save_ite[2] = __raw_readl(IT8152_INTC_LPNIAR);
84
85 /* Clear ITE IRQ's */
86 __raw_writel((0), IT8152_INTC_PDCNIRR);
87 __raw_writel((0), IT8152_INTC_LPCNIRR);
88}
89
90void __cmx270_pci_resume(void)
91{
92 /* restore IT8152 state */
93 __raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR);
94 __raw_writel((sleep_save_ite[1]), IT8152_INTC_LPCNIMR);
95 __raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR);
96}
97#else
98void cmx270_pci_suspend(void) {}
99void cmx270_pci_resume(void) {}
100#endif
101
102/* PCI IRQ mapping*/
103static int __init cmx270_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
104{
105 int irq;
106
107 printk(KERN_DEBUG "===> %s: %s slot=%x, pin=%x\n", __FUNCTION__,
108 pci_name(dev), slot, pin);
109
110 irq = it8152_pci_map_irq(dev, slot, pin);
111 if (irq)
112 return irq;
113
114 /*
115 Here comes the ugly part. The routing is baseboard specific,
116 but defining a platform for each possible base of CM-x270 is
117 unrealistic. Here we keep mapping for ATXBase and SB-x270.
118 */
119 /* ATXBASE PCI slot */
120 if (slot == 7)
121 return IT8152_PCI_INTA;
122
123 /* ATXBase/SB-x270 CardBus */
124 if (slot == 8 || slot == 0)
125 return IT8152_PCI_INTB;
126
127 /* ATXBase Ethernet */
128 if (slot == 9)
129 return IT8152_PCI_INTA;
130
131 /* SB-x270 Ethernet */
132 if (slot == 16)
133 return IT8152_PCI_INTA;
134
135 /* PC104+ interrupt routing */
136 if ((slot == 17) || (slot == 19))
137 return IT8152_PCI_INTA;
138 if ((slot == 18) || (slot == 20))
139 return IT8152_PCI_INTB;
140
141 return(0);
142}
143
144static struct pci_bus * __init
145cmx270_pci_scan_bus(int nr, struct pci_sys_data *sys)
146{
147 printk(KERN_INFO "Initializing CM-X270 PCI subsystem\n");
148
149 __raw_writel(0x800, IT8152_PCI_CFG_ADDR);
150 if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) {
151 printk(KERN_INFO "PCI Bridge found.\n");
152
153 /* set PCI I/O base at 0 */
154 writel(0x848, IT8152_PCI_CFG_ADDR);
155 writel(0, IT8152_PCI_CFG_DATA);
156
157 /* set PCI memory base at 0 */
158 writel(0x840, IT8152_PCI_CFG_ADDR);
159 writel(0, IT8152_PCI_CFG_DATA);
160
161 writel(0x20, IT8152_GPIO_GPDR);
162
163 /* CardBus Controller on ATXbase baseboard */
164 writel(0x4000, IT8152_PCI_CFG_ADDR);
165 if (readl(IT8152_PCI_CFG_DATA) == 0xAC51104C) {
166 printk(KERN_INFO "CardBus Bridge found.\n");
167
168 /* Configure socket 0 */
169 writel(0x408C, IT8152_PCI_CFG_ADDR);
170 writel(0x1022, IT8152_PCI_CFG_DATA);
171
172 writel(0x4080, IT8152_PCI_CFG_ADDR);
173 writel(0x3844d060, IT8152_PCI_CFG_DATA);
174
175 writel(0x4090, IT8152_PCI_CFG_ADDR);
176 writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
177 0x60440000),
178 IT8152_PCI_CFG_DATA);
179
180 writel(0x4018, IT8152_PCI_CFG_ADDR);
181 writel(0xb0000000, IT8152_PCI_CFG_DATA);
182
183 /* Configure socket 1 */
184 writel(0x418C, IT8152_PCI_CFG_ADDR);
185 writel(0x1022, IT8152_PCI_CFG_DATA);
186
187 writel(0x4180, IT8152_PCI_CFG_ADDR);
188 writel(0x3844d060, IT8152_PCI_CFG_DATA);
189
190 writel(0x4190, IT8152_PCI_CFG_ADDR);
191 writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) |
192 0x60440000),
193 IT8152_PCI_CFG_DATA);
194
195 writel(0x4118, IT8152_PCI_CFG_ADDR);
196 writel(0xb0000000, IT8152_PCI_CFG_DATA);
197 }
198 }
199 return it8152_pci_scan_bus(nr, sys);
200}
201
202static struct hw_pci cmx270_pci __initdata = {
203 .swizzle = pci_std_swizzle,
204 .map_irq = cmx270_pci_map_irq,
205 .nr_controllers = 1,
206 .setup = it8152_pci_setup,
207 .scan = cmx270_pci_scan_bus,
208};
209
210static int __init cmx270_init_pci(void)
211{
212 if (machine_is_armcore())
213 pci_common_init(&cmx270_pci);
214
215 return 0;
216}
217
218subsys_initcall(cmx270_init_pci);
diff --git a/arch/arm/mach-pxa/cm-x270-pci.h b/arch/arm/mach-pxa/cm-x270-pci.h
new file mode 100644
index 000000000000..ffe37b66f9a0
--- /dev/null
+++ b/arch/arm/mach-pxa/cm-x270-pci.h
@@ -0,0 +1,13 @@
1extern void __cmx270_pci_init_irq(void);
2extern void __cmx270_pci_suspend(void);
3extern void __cmx270_pci_resume(void);
4
5#ifdef CONFIG_PCI
6#define cmx270_pci_init_irq __cmx270_pci_init_irq
7#define cmx270_pci_suspend __cmx270_pci_suspend
8#define cmx270_pci_resume __cmx270_pci_resume
9#else
10#define cmx270_pci_init_irq() do {} while (0)
11#define cmx270_pci_suspend() do {} while (0)
12#define cmx270_pci_resume() do {} while (0)
13#endif
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c
new file mode 100644
index 000000000000..177664ccb2e2
--- /dev/null
+++ b/arch/arm/mach-pxa/cm-x270.c
@@ -0,0 +1,645 @@
1/*
2 * linux/arch/arm/mach-pxa/cm-x270.c
3 *
4 * Copyright (C) 2007 CompuLab, Ltd.
5 * Mike Rapoport <mike@compulab.co.il>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/types.h>
13#include <linux/pm.h>
14#include <linux/fb.h>
15#include <linux/platform_device.h>
16#include <linux/irq.h>
17#include <linux/sysdev.h>
18#include <linux/io.h>
19#include <linux/delay.h>
20
21#include <linux/dm9000.h>
22#include <linux/rtc-v3020.h>
23#include <linux/serial_8250.h>
24
25#include <video/mbxfb.h>
26
27#include <asm/mach/arch.h>
28#include <asm/mach-types.h>
29#include <asm/mach/map.h>
30
31#include <asm/arch/pxa-regs.h>
32#include <asm/arch/pxafb.h>
33#include <asm/arch/ohci.h>
34#include <asm/arch/mmc.h>
35#include <asm/arch/bitfield.h>
36#include <asm/arch/cm-x270.h>
37
38#include <asm/hardware/it8152.h>
39
40#include "generic.h"
41#include "cm-x270-pci.h"
42
43#define RTC_PHYS_BASE (PXA_CS1_PHYS + (5 << 22))
44#define DM9000_PHYS_BASE (PXA_CS1_PHYS + (6 << 22))
45
46static struct resource cmx270_dm9k_resource[] = {
47 [0] = {
48 .start = DM9000_PHYS_BASE,
49 .end = DM9000_PHYS_BASE + 4,
50 .flags = IORESOURCE_MEM,
51 },
52 [1] = {
53 .start = DM9000_PHYS_BASE + 8,
54 .end = DM9000_PHYS_BASE + 8 + 500,
55 .flags = IORESOURCE_MEM,
56 },
57 [2] = {
58 .start = CMX270_ETHIRQ,
59 .end = CMX270_ETHIRQ,
60 .flags = IORESOURCE_IRQ,
61 }
62};
63
64/* for the moment we limit ourselves to 32bit IO until some
65 * better IO routines can be written and tested
66 */
67static struct dm9000_plat_data cmx270_dm9k_platdata = {
68 .flags = DM9000_PLATF_32BITONLY,
69};
70
71/* Ethernet device */
72static struct platform_device cmx270_device_dm9k = {
73 .name = "dm9000",
74 .id = 0,
75 .num_resources = ARRAY_SIZE(cmx270_dm9k_resource),
76 .resource = cmx270_dm9k_resource,
77 .dev = {
78 .platform_data = &cmx270_dm9k_platdata,
79 }
80};
81
82/* audio device */
83static struct platform_device cmx270_audio_device = {
84 .name = "pxa2xx-ac97",
85 .id = -1,
86};
87
88/* touchscreen controller */
89static struct platform_device cmx270_ts_device = {
90 .name = "ucb1400_ts",
91 .id = -1,
92};
93
94/* RTC */
95static struct resource cmx270_v3020_resource[] = {
96 [0] = {
97 .start = RTC_PHYS_BASE,
98 .end = RTC_PHYS_BASE + 4,
99 .flags = IORESOURCE_MEM,
100 },
101};
102
103struct v3020_platform_data cmx270_v3020_pdata = {
104 .leftshift = 16,
105};
106
107static struct platform_device cmx270_rtc_device = {
108 .name = "v3020",
109 .num_resources = ARRAY_SIZE(cmx270_v3020_resource),
110 .resource = cmx270_v3020_resource,
111 .id = -1,
112 .dev = {
113 .platform_data = &cmx270_v3020_pdata,
114 }
115};
116
117/*
118 * CM-X270 LEDs
119 */
120static struct platform_device cmx270_led_device = {
121 .name = "cm-x270-led",
122 .id = -1,
123};
124
125/* 2700G graphics */
126static u64 fb_dma_mask = ~(u64)0;
127
128static struct resource cmx270_2700G_resource[] = {
129 /* frame buffer memory including ODFB and External SDRAM */
130 [0] = {
131 .start = MARATHON_PHYS,
132 .end = MARATHON_PHYS + 0x02000000,
133 .flags = IORESOURCE_MEM,
134 },
135 /* Marathon registers */
136 [1] = {
137 .start = MARATHON_PHYS + 0x03fe0000,
138 .end = MARATHON_PHYS + 0x03ffffff,
139 .flags = IORESOURCE_MEM,
140 },
141};
142
143static unsigned long save_lcd_regs[10];
144
145static int cmx270_marathon_probe(struct fb_info *fb)
146{
147 /* save PXA-270 pin settings before enabling 2700G */
148 save_lcd_regs[0] = GPDR1;
149 save_lcd_regs[1] = GPDR2;
150 save_lcd_regs[2] = GAFR1_U;
151 save_lcd_regs[3] = GAFR2_L;
152 save_lcd_regs[4] = GAFR2_U;
153
154 /* Disable PXA-270 on-chip controller driving pins */
155 GPDR1 &= ~(0xfc000000);
156 GPDR2 &= ~(0x00c03fff);
157 GAFR1_U &= ~(0xfff00000);
158 GAFR2_L &= ~(0x0fffffff);
159 GAFR2_U &= ~(0x0000f000);
160 return 0;
161}
162
163static int cmx270_marathon_remove(struct fb_info *fb)
164{
165 GPDR1 = save_lcd_regs[0];
166 GPDR2 = save_lcd_regs[1];
167 GAFR1_U = save_lcd_regs[2];
168 GAFR2_L = save_lcd_regs[3];
169 GAFR2_U = save_lcd_regs[4];
170 return 0;
171}
172
173static struct mbxfb_platform_data cmx270_2700G_data = {
174 .xres = {
175 .min = 240,
176 .max = 1200,
177 .defval = 640,
178 },
179 .yres = {
180 .min = 240,
181 .max = 1200,
182 .defval = 480,
183 },
184 .bpp = {
185 .min = 16,
186 .max = 32,
187 .defval = 16,
188 },
189 .memsize = 8*1024*1024,
190 .probe = cmx270_marathon_probe,
191 .remove = cmx270_marathon_remove,
192};
193
194static struct platform_device cmx270_2700G = {
195 .name = "mbx-fb",
196 .dev = {
197 .platform_data = &cmx270_2700G_data,
198 .dma_mask = &fb_dma_mask,
199 .coherent_dma_mask = 0xffffffff,
200 },
201 .num_resources = ARRAY_SIZE(cmx270_2700G_resource),
202 .resource = cmx270_2700G_resource,
203 .id = -1,
204};
205
206static u64 ata_dma_mask = ~(u64)0;
207
208static struct platform_device cmx270_ata = {
209 .name = "pata_cm_x270",
210 .id = -1,
211 .dev = {
212 .dma_mask = &ata_dma_mask,
213 .coherent_dma_mask = 0xffffffff,
214 },
215};
216
217/* platform devices */
218static struct platform_device *platform_devices[] __initdata = {
219 &cmx270_device_dm9k,
220 &cmx270_audio_device,
221 &cmx270_rtc_device,
222 &cmx270_2700G,
223 &cmx270_led_device,
224 &cmx270_ts_device,
225 &cmx270_ata,
226};
227
228/* Map PCI companion and IDE/General Purpose CS statically */
229static struct map_desc cmx270_io_desc[] __initdata = {
230 [0] = { /* IDE/general purpose space */
231 .virtual = CMX270_IDE104_VIRT,
232 .pfn = __phys_to_pfn(CMX270_IDE104_PHYS),
233 .length = SZ_64M - SZ_8M,
234 .type = MT_DEVICE
235 },
236 [1] = { /* PCI bridge */
237 .virtual = CMX270_IT8152_VIRT,
238 .pfn = __phys_to_pfn(CMX270_IT8152_PHYS),
239 .length = SZ_64M,
240 .type = MT_DEVICE
241 },
242};
243
244/*
245 Display definitions
246 keep these for backwards compatibility, although symbolic names (as
247 e.g. in lpd270.c) looks better
248*/
249#define MTYPE_STN320x240 0
250#define MTYPE_TFT640x480 1
251#define MTYPE_CRT640x480 2
252#define MTYPE_CRT800x600 3
253#define MTYPE_TFT320x240 6
254#define MTYPE_STN640x480 7
255
256static struct pxafb_mode_info generic_stn_320x240_mode = {
257 .pixclock = 76923,
258 .bpp = 8,
259 .xres = 320,
260 .yres = 240,
261 .hsync_len = 3,
262 .vsync_len = 2,
263 .left_margin = 3,
264 .upper_margin = 0,
265 .right_margin = 3,
266 .lower_margin = 0,
267 .sync = (FB_SYNC_HOR_HIGH_ACT |
268 FB_SYNC_VERT_HIGH_ACT),
269 .cmap_greyscale = 0,
270};
271
272static struct pxafb_mach_info generic_stn_320x240 = {
273 .modes = &generic_stn_320x240_mode,
274 .num_modes = 1,
275 .lccr0 = 0,
276 .lccr3 = (LCCR3_PixClkDiv(0x03) |
277 LCCR3_Acb(0xff) |
278 LCCR3_PCP),
279 .cmap_inverse = 0,
280 .cmap_static = 0,
281};
282
283static struct pxafb_mode_info generic_tft_640x480_mode = {
284 .pixclock = 38461,
285 .bpp = 8,
286 .xres = 640,
287 .yres = 480,
288 .hsync_len = 60,
289 .vsync_len = 2,
290 .left_margin = 70,
291 .upper_margin = 10,
292 .right_margin = 70,
293 .lower_margin = 5,
294 .sync = 0,
295 .cmap_greyscale = 0,
296};
297
298static struct pxafb_mach_info generic_tft_640x480 = {
299 .modes = &generic_tft_640x480_mode,
300 .num_modes = 1,
301 .lccr0 = (LCCR0_PAS),
302 .lccr3 = (LCCR3_PixClkDiv(0x01) |
303 LCCR3_Acb(0xff) |
304 LCCR3_PCP),
305 .cmap_inverse = 0,
306 .cmap_static = 0,
307};
308
309static struct pxafb_mode_info generic_crt_640x480_mode = {
310 .pixclock = 38461,
311 .bpp = 8,
312 .xres = 640,
313 .yres = 480,
314 .hsync_len = 63,
315 .vsync_len = 2,
316 .left_margin = 81,
317 .upper_margin = 33,
318 .right_margin = 16,
319 .lower_margin = 10,
320 .sync = (FB_SYNC_HOR_HIGH_ACT |
321 FB_SYNC_VERT_HIGH_ACT),
322 .cmap_greyscale = 0,
323};
324
325static struct pxafb_mach_info generic_crt_640x480 = {
326 .modes = &generic_crt_640x480_mode,
327 .num_modes = 1,
328 .lccr0 = (LCCR0_PAS),
329 .lccr3 = (LCCR3_PixClkDiv(0x01) |
330 LCCR3_Acb(0xff)),
331 .cmap_inverse = 0,
332 .cmap_static = 0,
333};
334
335static struct pxafb_mode_info generic_crt_800x600_mode = {
336 .pixclock = 28846,
337 .bpp = 8,
338 .xres = 800,
339 .yres = 600,
340 .hsync_len = 63,
341 .vsync_len = 2,
342 .left_margin = 26,
343 .upper_margin = 21,
344 .right_margin = 26,
345 .lower_margin = 11,
346 .sync = (FB_SYNC_HOR_HIGH_ACT |
347 FB_SYNC_VERT_HIGH_ACT),
348 .cmap_greyscale = 0,
349};
350
351static struct pxafb_mach_info generic_crt_800x600 = {
352 .modes = &generic_crt_800x600_mode,
353 .num_modes = 1,
354 .lccr0 = (LCCR0_PAS),
355 .lccr3 = (LCCR3_PixClkDiv(0x02) |
356 LCCR3_Acb(0xff)),
357 .cmap_inverse = 0,
358 .cmap_static = 0,
359};
360
361static struct pxafb_mode_info generic_tft_320x240_mode = {
362 .pixclock = 134615,
363 .bpp = 16,
364 .xres = 320,
365 .yres = 240,
366 .hsync_len = 63,
367 .vsync_len = 7,
368 .left_margin = 75,
369 .upper_margin = 0,
370 .right_margin = 15,
371 .lower_margin = 15,
372 .sync = 0,
373 .cmap_greyscale = 0,
374};
375
376static struct pxafb_mach_info generic_tft_320x240 = {
377 .modes = &generic_tft_320x240_mode,
378 .num_modes = 1,
379 .lccr0 = (LCCR0_PAS),
380 .lccr3 = (LCCR3_PixClkDiv(0x06) |
381 LCCR3_Acb(0xff) |
382 LCCR3_PCP),
383 .cmap_inverse = 0,
384 .cmap_static = 0,
385};
386
387static struct pxafb_mode_info generic_stn_640x480_mode = {
388 .pixclock = 57692,
389 .bpp = 8,
390 .xres = 640,
391 .yres = 480,
392 .hsync_len = 4,
393 .vsync_len = 2,
394 .left_margin = 10,
395 .upper_margin = 5,
396 .right_margin = 10,
397 .lower_margin = 5,
398 .sync = (FB_SYNC_HOR_HIGH_ACT |
399 FB_SYNC_VERT_HIGH_ACT),
400 .cmap_greyscale = 0,
401};
402
403static struct pxafb_mach_info generic_stn_640x480 = {
404 .modes = &generic_stn_640x480_mode,
405 .num_modes = 1,
406 .lccr0 = 0,
407 .lccr3 = (LCCR3_PixClkDiv(0x02) |
408 LCCR3_Acb(0xff)),
409 .cmap_inverse = 0,
410 .cmap_static = 0,
411};
412
413static struct pxafb_mach_info *cmx270_display = &generic_crt_640x480;
414
415static int __init cmx270_set_display(char *str)
416{
417 int disp_type = simple_strtol(str, NULL, 0);
418 switch (disp_type) {
419 case MTYPE_STN320x240:
420 cmx270_display = &generic_stn_320x240;
421 break;
422 case MTYPE_TFT640x480:
423 cmx270_display = &generic_tft_640x480;
424 break;
425 case MTYPE_CRT640x480:
426 cmx270_display = &generic_crt_640x480;
427 break;
428 case MTYPE_CRT800x600:
429 cmx270_display = &generic_crt_800x600;
430 break;
431 case MTYPE_TFT320x240:
432 cmx270_display = &generic_tft_320x240;
433 break;
434 case MTYPE_STN640x480:
435 cmx270_display = &generic_stn_640x480;
436 break;
437 default: /* fallback to CRT 640x480 */
438 cmx270_display = &generic_crt_640x480;
439 break;
440 }
441 return 1;
442}
443
444/*
445 This should be done really early to get proper configuration for
446 frame buffer.
447 Indeed, pxafb parameters can be used istead, but CM-X270 bootloader
448 has limitied line length for kernel command line, and also it will
449 break compatibitlty with proprietary releases already in field.
450*/
451__setup("monitor=", cmx270_set_display);
452
453/* PXA27x OHCI controller setup */
454static int cmx270_ohci_init(struct device *dev)
455{
456 /* Set the Power Control Polarity Low */
457 UHCHR = (UHCHR | UHCHR_PCPL) &
458 ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE);
459
460 return 0;
461}
462
463static struct pxaohci_platform_data cmx270_ohci_platform_data = {
464 .port_mode = PMM_PERPORT_MODE,
465 .init = cmx270_ohci_init,
466};
467
468
469static int cmx270_mci_init(struct device *dev,
470 irq_handler_t cmx270_detect_int,
471 void *data)
472{
473 int err;
474
475 /*
476 * setup GPIO for PXA27x MMC controller
477 */
478 pxa_gpio_mode(GPIO32_MMCCLK_MD);
479 pxa_gpio_mode(GPIO112_MMCCMD_MD);
480 pxa_gpio_mode(GPIO92_MMCDAT0_MD);
481 pxa_gpio_mode(GPIO109_MMCDAT1_MD);
482 pxa_gpio_mode(GPIO110_MMCDAT2_MD);
483 pxa_gpio_mode(GPIO111_MMCDAT3_MD);
484
485 /* SB-X270 uses GPIO105 as SD power enable */
486 pxa_gpio_mode(105 | GPIO_OUT);
487
488 /* card detect IRQ on GPIO 83 */
489 pxa_gpio_mode(IRQ_TO_GPIO(CMX270_MMC_IRQ));
490 set_irq_type(CMX270_MMC_IRQ, IRQT_FALLING);
491
492 err = request_irq(CMX270_MMC_IRQ, cmx270_detect_int,
493 IRQF_DISABLED | IRQF_TRIGGER_FALLING,
494 "MMC card detect", data);
495 if (err) {
496 printk(KERN_ERR "cmx270_mci_init: MMC/SD: can't"
497 " request MMC card detect IRQ\n");
498 return -1;
499 }
500
501 return 0;
502}
503
504static void cmx270_mci_setpower(struct device *dev, unsigned int vdd)
505{
506 struct pxamci_platform_data *p_d = dev->platform_data;
507
508 if ((1 << vdd) & p_d->ocr_mask) {
509 printk(KERN_DEBUG "%s: on\n", __FUNCTION__);
510 GPCR(105) = GPIO_bit(105);
511 } else {
512 GPSR(105) = GPIO_bit(105);
513 printk(KERN_DEBUG "%s: off\n", __FUNCTION__);
514 }
515}
516
517static void cmx270_mci_exit(struct device *dev, void *data)
518{
519 free_irq(CMX270_MMC_IRQ, data);
520}
521
522static struct pxamci_platform_data cmx270_mci_platform_data = {
523 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
524 .init = cmx270_mci_init,
525 .setpower = cmx270_mci_setpower,
526 .exit = cmx270_mci_exit,
527};
528
529#ifdef CONFIG_PM
530static unsigned long sleep_save_msc[10];
531
532static int cmx270_suspend(struct sys_device *dev, pm_message_t state)
533{
534 cmx270_pci_suspend();
535
536 /* save MSC registers */
537 sleep_save_msc[0] = MSC0;
538 sleep_save_msc[1] = MSC1;
539 sleep_save_msc[2] = MSC2;
540
541 /* setup power saving mode registers */
542 PCFR = 0x0;
543 PSLR = 0xff400000;
544 PMCR = 0x00000005;
545 PWER = 0x80000000;
546 PFER = 0x00000000;
547 PRER = 0x00000000;
548 PGSR0 = 0xC0018800;
549 PGSR1 = 0x004F0002;
550 PGSR2 = 0x6021C000;
551 PGSR3 = 0x00020000;
552
553 return 0;
554}
555
556static int cmx270_resume(struct sys_device *dev)
557{
558 cmx270_pci_resume();
559
560 /* restore MSC registers */
561 MSC0 = sleep_save_msc[0];
562 MSC1 = sleep_save_msc[1];
563 MSC2 = sleep_save_msc[2];
564
565 return 0;
566}
567
568static struct sysdev_class cmx270_pm_sysclass = {
569 set_kset_name("pm"),
570 .resume = cmx270_resume,
571 .suspend = cmx270_suspend,
572};
573
574static struct sys_device cmx270_pm_device = {
575 .cls = &cmx270_pm_sysclass,
576};
577
578static int __init cmx270_pm_init(void)
579{
580 int error;
581 error = sysdev_class_register(&cmx270_pm_sysclass);
582 if (error == 0)
583 error = sysdev_register(&cmx270_pm_device);
584 return error;
585}
586#else
587static int __init cmx270_pm_init(void) { return 0; }
588#endif
589
590static void __init cmx270_init(void)
591{
592 cmx270_pm_init();
593
594 set_pxa_fb_info(cmx270_display);
595
596 /* register CM-X270 platform devices */
597 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
598
599 /* set MCI and OHCI platform parameters */
600 pxa_set_mci_info(&cmx270_mci_platform_data);
601 pxa_set_ohci_info(&cmx270_ohci_platform_data);
602
603 /* This enables the STUART */
604 pxa_gpio_mode(GPIO46_STRXD_MD);
605 pxa_gpio_mode(GPIO47_STTXD_MD);
606
607 /* This enables the BTUART */
608 pxa_gpio_mode(GPIO42_BTRXD_MD);
609 pxa_gpio_mode(GPIO43_BTTXD_MD);
610 pxa_gpio_mode(GPIO44_BTCTS_MD);
611 pxa_gpio_mode(GPIO45_BTRTS_MD);
612}
613
614static void __init cmx270_init_irq(void)
615{
616 pxa27x_init_irq();
617
618
619 cmx270_pci_init_irq();
620
621 /* Setup interrupt for dm9000 */
622 pxa_gpio_mode(IRQ_TO_GPIO(CMX270_ETHIRQ));
623 set_irq_type(CMX270_ETHIRQ, IRQT_RISING);
624
625 /* Setup interrupt for 2700G */
626 pxa_gpio_mode(IRQ_TO_GPIO(CMX270_GFXIRQ));
627 set_irq_type(CMX270_GFXIRQ, IRQT_FALLING);
628}
629
630static void __init cmx270_map_io(void)
631{
632 pxa_map_io();
633 iotable_init(cmx270_io_desc, ARRAY_SIZE(cmx270_io_desc));
634}
635
636
637MACHINE_START(ARMCORE, "Compulab CM-x270")
638 .boot_params = 0xa0000100,
639 .phys_io = 0x40000000,
640 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
641 .map_io = cmx270_map_io,
642 .init_irq = cmx270_init_irq,
643 .timer = &pxa_timer,
644 .init_machine = cmx270_init,
645MACHINE_END
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 636fdb1c049c..94c8d5cdd60a 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -9,3 +9,6 @@ extern struct platform_device pxa_device_i2c;
9extern struct platform_device pxa_device_i2s; 9extern struct platform_device pxa_device_i2s;
10extern struct platform_device pxa_device_ficp; 10extern struct platform_device pxa_device_ficp;
11extern struct platform_device pxa_device_rtc; 11extern struct platform_device pxa_device_rtc;
12
13extern struct platform_device pxa27x_device_i2c_power;
14extern struct platform_device pxa27x_device_ohci;
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c
index 5510f6fdce55..1c34946ee16e 100644
--- a/arch/arm/mach-pxa/generic.c
+++ b/arch/arm/mach-pxa/generic.c
@@ -25,10 +25,6 @@
25#include <linux/pm.h> 25#include <linux/pm.h>
26#include <linux/string.h> 26#include <linux/string.h>
27 27
28#include <linux/sched.h>
29#include <asm/cnt32_to_63.h>
30#include <asm/div64.h>
31
32#include <asm/hardware.h> 28#include <asm/hardware.h>
33#include <asm/irq.h> 29#include <asm/irq.h>
34#include <asm/system.h> 30#include <asm/system.h>
@@ -47,66 +43,39 @@
47#include "generic.h" 43#include "generic.h"
48 44
49/* 45/*
50 * This is the PXA2xx sched_clock implementation. This has a resolution 46 * Get the clock frequency as reflected by CCCR and the turbo flag.
51 * of at least 308ns and a maximum value that depends on the value of 47 * We assume these values have been applied via a fcs.
52 * CLOCK_TICK_RATE. 48 * If info is not 0 we also display the current settings.
53 *
54 * The return value is guaranteed to be monotonic in that range as
55 * long as there is always less than 582 seconds between successive
56 * calls to this function.
57 */ 49 */
58unsigned long long sched_clock(void) 50unsigned int get_clk_frequency_khz(int info)
59{ 51{
60 unsigned long long v = cnt32_to_63(OSCR); 52 if (cpu_is_pxa21x() || cpu_is_pxa25x())
61 /* Note: top bit ov v needs cleared unless multiplier is even. */ 53 return pxa25x_get_clk_frequency_khz(info);
62 54 else if (cpu_is_pxa27x())
63#if CLOCK_TICK_RATE == 3686400 55 return pxa27x_get_clk_frequency_khz(info);
64 /* 1E9 / 3686400 => 78125 / 288, max value = 32025597s (370 days). */ 56 else
65 /* The <<1 is used to get rid of tick.hi top bit */ 57 return pxa3xx_get_clk_frequency_khz(info);
66 v *= 78125<<1; 58}
67 do_div(v, 288<<1); 59EXPORT_SYMBOL(get_clk_frequency_khz);
68#elif CLOCK_TICK_RATE == 3250000
69 /* 1E9 / 3250000 => 4000 / 13, max value = 709490156s (8211 days) */
70 v *= 4000;
71 do_div(v, 13);
72#elif CLOCK_TICK_RATE == 3249600
73 /* 1E9 / 3249600 => 625000 / 2031, max value = 4541295s (52 days) */
74 v *= 625000;
75 do_div(v, 2031);
76#else
77#warning "consider fixing sched_clock for your value of CLOCK_TICK_RATE"
78 /*
79 * 96-bit math to perform tick * NSEC_PER_SEC / CLOCK_TICK_RATE for
80 * any value of CLOCK_TICK_RATE. Max value is in the 80 thousand
81 * years range and truncation to unsigned long long limits it to
82 * sched_clock's max range of ~584 years. This is nice but with
83 * higher computation cost.
84 */
85 {
86 union {
87 unsigned long long val;
88 struct { unsigned long lo, hi; };
89 } x;
90 unsigned long long y;
91
92 x.val = v;
93 x.hi &= 0x7fffffff;
94 y = (unsigned long long)x.lo * NSEC_PER_SEC;
95 x.lo = y;
96 y = (y >> 32) + (unsigned long long)x.hi * NSEC_PER_SEC;
97 x.hi = do_div(y, CLOCK_TICK_RATE);
98 do_div(x.val, CLOCK_TICK_RATE);
99 x.hi += y;
100 v = x.val;
101 }
102#endif
103 60
104 return v; 61/*
62 * Return the current memory clock frequency in units of 10kHz
63 */
64unsigned int get_memclk_frequency_10khz(void)
65{
66 if (cpu_is_pxa21x() || cpu_is_pxa25x())
67 return pxa25x_get_memclk_frequency_10khz();
68 else if (cpu_is_pxa27x())
69 return pxa27x_get_memclk_frequency_10khz();
70 else
71 return pxa3xx_get_memclk_frequency_10khz();
105} 72}
73EXPORT_SYMBOL(get_memclk_frequency_10khz);
106 74
107/* 75/*
108 * Handy function to set GPIO alternate functions 76 * Handy function to set GPIO alternate functions
109 */ 77 */
78int pxa_last_gpio;
110 79
111int pxa_gpio_mode(int gpio_mode) 80int pxa_gpio_mode(int gpio_mode)
112{ 81{
@@ -115,7 +84,7 @@ int pxa_gpio_mode(int gpio_mode)
115 int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; 84 int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
116 int gafr; 85 int gafr;
117 86
118 if (gpio > PXA_LAST_GPIO) 87 if (gpio > pxa_last_gpio)
119 return -EINVAL; 88 return -EINVAL;
120 89
121 local_irq_save(flags); 90 local_irq_save(flags);
@@ -136,6 +105,44 @@ int pxa_gpio_mode(int gpio_mode)
136 105
137EXPORT_SYMBOL(pxa_gpio_mode); 106EXPORT_SYMBOL(pxa_gpio_mode);
138 107
108int gpio_direction_input(unsigned gpio)
109{
110 unsigned long flags;
111 u32 mask;
112
113 if (gpio > pxa_last_gpio)
114 return -EINVAL;
115
116 mask = GPIO_bit(gpio);
117 local_irq_save(flags);
118 GPDR(gpio) &= ~mask;
119 local_irq_restore(flags);
120
121 return 0;
122}
123EXPORT_SYMBOL(gpio_direction_input);
124
125int gpio_direction_output(unsigned gpio, int value)
126{
127 unsigned long flags;
128 u32 mask;
129
130 if (gpio > pxa_last_gpio)
131 return -EINVAL;
132
133 mask = GPIO_bit(gpio);
134 local_irq_save(flags);
135 if (value)
136 GPSR(gpio) = mask;
137 else
138 GPCR(gpio) = mask;
139 GPDR(gpio) |= mask;
140 local_irq_restore(flags);
141
142 return 0;
143}
144EXPORT_SYMBOL(gpio_direction_output);
145
139/* 146/*
140 * Return GPIO level 147 * Return GPIO level
141 */ 148 */
@@ -159,7 +166,7 @@ EXPORT_SYMBOL(pxa_gpio_set_value);
159/* 166/*
160 * Routine to safely enable or disable a clock in the CKEN 167 * Routine to safely enable or disable a clock in the CKEN
161 */ 168 */
162void pxa_set_cken(int clock, int enable) 169void __pxa_set_cken(int clock, int enable)
163{ 170{
164 unsigned long flags; 171 unsigned long flags;
165 local_irq_save(flags); 172 local_irq_save(flags);
@@ -172,7 +179,7 @@ void pxa_set_cken(int clock, int enable)
172 local_irq_restore(flags); 179 local_irq_restore(flags);
173} 180}
174 181
175EXPORT_SYMBOL(pxa_set_cken); 182EXPORT_SYMBOL(__pxa_set_cken);
176 183
177/* 184/*
178 * Intel PXA2xx internal register mapping. 185 * Intel PXA2xx internal register mapping.
@@ -329,21 +336,80 @@ void __init set_pxa_fb_parent(struct device *parent_dev)
329 pxa_device_fb.dev.parent = parent_dev; 336 pxa_device_fb.dev.parent = parent_dev;
330} 337}
331 338
339static struct resource pxa_resource_ffuart[] = {
340 {
341 .start = __PREG(FFUART),
342 .end = __PREG(FFUART) + 35,
343 .flags = IORESOURCE_MEM,
344 }, {
345 .start = IRQ_FFUART,
346 .end = IRQ_FFUART,
347 .flags = IORESOURCE_IRQ,
348 }
349};
350
332struct platform_device pxa_device_ffuart= { 351struct platform_device pxa_device_ffuart= {
333 .name = "pxa2xx-uart", 352 .name = "pxa2xx-uart",
334 .id = 0, 353 .id = 0,
354 .resource = pxa_resource_ffuart,
355 .num_resources = ARRAY_SIZE(pxa_resource_ffuart),
335}; 356};
357
358static struct resource pxa_resource_btuart[] = {
359 {
360 .start = __PREG(BTUART),
361 .end = __PREG(BTUART) + 35,
362 .flags = IORESOURCE_MEM,
363 }, {
364 .start = IRQ_BTUART,
365 .end = IRQ_BTUART,
366 .flags = IORESOURCE_IRQ,
367 }
368};
369
336struct platform_device pxa_device_btuart = { 370struct platform_device pxa_device_btuart = {
337 .name = "pxa2xx-uart", 371 .name = "pxa2xx-uart",
338 .id = 1, 372 .id = 1,
373 .resource = pxa_resource_btuart,
374 .num_resources = ARRAY_SIZE(pxa_resource_btuart),
339}; 375};
376
377static struct resource pxa_resource_stuart[] = {
378 {
379 .start = __PREG(STUART),
380 .end = __PREG(STUART) + 35,
381 .flags = IORESOURCE_MEM,
382 }, {
383 .start = IRQ_STUART,
384 .end = IRQ_STUART,
385 .flags = IORESOURCE_IRQ,
386 }
387};
388
340struct platform_device pxa_device_stuart = { 389struct platform_device pxa_device_stuart = {
341 .name = "pxa2xx-uart", 390 .name = "pxa2xx-uart",
342 .id = 2, 391 .id = 2,
392 .resource = pxa_resource_stuart,
393 .num_resources = ARRAY_SIZE(pxa_resource_stuart),
343}; 394};
395
396static struct resource pxa_resource_hwuart[] = {
397 {
398 .start = __PREG(HWUART),
399 .end = __PREG(HWUART) + 47,
400 .flags = IORESOURCE_MEM,
401 }, {
402 .start = IRQ_HWUART,
403 .end = IRQ_HWUART,
404 .flags = IORESOURCE_IRQ,
405 }
406};
407
344struct platform_device pxa_device_hwuart = { 408struct platform_device pxa_device_hwuart = {
345 .name = "pxa2xx-uart", 409 .name = "pxa2xx-uart",
346 .id = 3, 410 .id = 3,
411 .resource = pxa_resource_hwuart,
412 .num_resources = ARRAY_SIZE(pxa_resource_hwuart),
347}; 413};
348 414
349static struct resource pxai2c_resources[] = { 415static struct resource pxai2c_resources[] = {
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 91ab2ad8b34b..b30f240a16c7 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -15,14 +15,40 @@ extern struct sys_timer pxa_timer;
15extern void __init pxa_init_irq_low(void); 15extern void __init pxa_init_irq_low(void);
16extern void __init pxa_init_irq_high(void); 16extern void __init pxa_init_irq_high(void);
17extern void __init pxa_init_irq_gpio(int gpio_nr); 17extern void __init pxa_init_irq_gpio(int gpio_nr);
18extern void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int));
18extern void __init pxa25x_init_irq(void); 19extern void __init pxa25x_init_irq(void);
19extern void __init pxa27x_init_irq(void); 20extern void __init pxa27x_init_irq(void);
21extern void __init pxa3xx_init_irq(void);
20extern void __init pxa_map_io(void); 22extern void __init pxa_map_io(void);
21 23
22extern unsigned int get_clk_frequency_khz(int info); 24extern unsigned int get_clk_frequency_khz(int info);
25extern int pxa_last_gpio;
23 26
24#define SET_BANK(__nr,__start,__size) \ 27#define SET_BANK(__nr,__start,__size) \
25 mi->bank[__nr].start = (__start), \ 28 mi->bank[__nr].start = (__start), \
26 mi->bank[__nr].size = (__size), \ 29 mi->bank[__nr].size = (__size), \
27 mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27) 30 mi->bank[__nr].node = (((unsigned)(__start) - PHYS_OFFSET) >> 27)
28 31
32#ifdef CONFIG_PXA25x
33extern unsigned pxa25x_get_clk_frequency_khz(int);
34extern unsigned pxa25x_get_memclk_frequency_10khz(void);
35#else
36#define pxa25x_get_clk_frequency_khz(x) (0)
37#define pxa25x_get_memclk_frequency_10khz() (0)
38#endif
39
40#ifdef CONFIG_PXA27x
41extern unsigned pxa27x_get_clk_frequency_khz(int);
42extern unsigned pxa27x_get_memclk_frequency_10khz(void);
43#else
44#define pxa27x_get_clk_frequency_khz(x) (0)
45#define pxa27x_get_memclk_frequency_10khz() (0)
46#endif
47
48#ifdef CONFIG_PXA3xx
49extern unsigned pxa3xx_get_clk_frequency_khz(int);
50extern unsigned pxa3xx_get_memclk_frequency_10khz(void);
51#else
52#define pxa3xx_get_clk_frequency_khz(x) (0)
53#define pxa3xx_get_memclk_frequency_10khz() (0)
54#endif
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index ae2ae08032d7..07acb45b16ea 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -38,33 +38,11 @@ static void pxa_unmask_low_irq(unsigned int irq)
38 ICMR |= (1 << irq); 38 ICMR |= (1 << irq);
39} 39}
40 40
41static int pxa_set_wake(unsigned int irq, unsigned int on)
42{
43 u32 mask;
44
45 switch (irq) {
46 case IRQ_RTCAlrm:
47 mask = PWER_RTC;
48 break;
49#ifdef CONFIG_PXA27x
50 /* REVISIT can handle USBH1, USBH2, USB, MSL, USIM, ... */
51#endif
52 default:
53 return -EINVAL;
54 }
55 if (on)
56 PWER |= mask;
57 else
58 PWER &= ~mask;
59 return 0;
60}
61
62static struct irq_chip pxa_internal_chip_low = { 41static struct irq_chip pxa_internal_chip_low = {
63 .name = "SC", 42 .name = "SC",
64 .ack = pxa_mask_low_irq, 43 .ack = pxa_mask_low_irq,
65 .mask = pxa_mask_low_irq, 44 .mask = pxa_mask_low_irq,
66 .unmask = pxa_unmask_low_irq, 45 .unmask = pxa_unmask_low_irq,
67 .set_wake = pxa_set_wake,
68}; 46};
69 47
70void __init pxa_init_irq_low(void) 48void __init pxa_init_irq_low(void)
@@ -87,7 +65,7 @@ void __init pxa_init_irq_low(void)
87 } 65 }
88} 66}
89 67
90#ifdef CONFIG_PXA27x 68#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
91 69
92/* 70/*
93 * This is for the second set of internal IRQs as found on the PXA27x. 71 * This is for the second set of internal IRQs as found on the PXA27x.
@@ -125,26 +103,6 @@ void __init pxa_init_irq_high(void)
125} 103}
126#endif 104#endif
127 105
128/* Note that if an input/irq line ever gets changed to an output during
129 * suspend, the relevant PWER, PRER, and PFER bits should be cleared.
130 */
131#ifdef CONFIG_PXA27x
132
133/* PXA27x: Various gpios can issue wakeup events. This logic only
134 * handles the simple cases, not the WEMUX2 and WEMUX3 options
135 */
136#define PXA27x_GPIO_NOWAKE_MASK \
137 ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
138#define WAKEMASK(gpio) \
139 (((gpio) <= 15) \
140 ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
141 : ((gpio == 35) ? (1 << 24) : 0))
142#else
143
144/* pxa 210, 250, 255, 26x: gpios 0..15 can issue wakeups */
145#define WAKEMASK(gpio) (((gpio) <= 15) ? (1 << (gpio)) : 0)
146#endif
147
148/* 106/*
149 * PXA GPIO edge detection for IRQs: 107 * PXA GPIO edge detection for IRQs:
150 * IRQs are generated on Falling-Edge, Rising-Edge, or both. 108 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
@@ -158,11 +116,9 @@ static long GPIO_IRQ_mask[4];
158static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) 116static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
159{ 117{
160 int gpio, idx; 118 int gpio, idx;
161 u32 mask;
162 119
163 gpio = IRQ_TO_GPIO(irq); 120 gpio = IRQ_TO_GPIO(irq);
164 idx = gpio >> 5; 121 idx = gpio >> 5;
165 mask = WAKEMASK(gpio);
166 122
167 if (type == IRQT_PROBE) { 123 if (type == IRQT_PROBE) {
168 /* Don't mess with enabled GPIOs using preconfigured edges or 124 /* Don't mess with enabled GPIOs using preconfigured edges or
@@ -182,19 +138,15 @@ static int pxa_gpio_irq_type(unsigned int irq, unsigned int type)
182 if (type & __IRQT_RISEDGE) { 138 if (type & __IRQT_RISEDGE) {
183 /* printk("rising "); */ 139 /* printk("rising "); */
184 __set_bit (gpio, GPIO_IRQ_rising_edge); 140 __set_bit (gpio, GPIO_IRQ_rising_edge);
185 PRER |= mask;
186 } else { 141 } else {
187 __clear_bit (gpio, GPIO_IRQ_rising_edge); 142 __clear_bit (gpio, GPIO_IRQ_rising_edge);
188 PRER &= ~mask;
189 } 143 }
190 144
191 if (type & __IRQT_FALEDGE) { 145 if (type & __IRQT_FALEDGE) {
192 /* printk("falling "); */ 146 /* printk("falling "); */
193 __set_bit (gpio, GPIO_IRQ_falling_edge); 147 __set_bit (gpio, GPIO_IRQ_falling_edge);
194 PFER |= mask;
195 } else { 148 } else {
196 __clear_bit (gpio, GPIO_IRQ_falling_edge); 149 __clear_bit (gpio, GPIO_IRQ_falling_edge);
197 PFER &= ~mask;
198 } 150 }
199 151
200 /* printk("edges\n"); */ 152 /* printk("edges\n"); */
@@ -213,29 +165,12 @@ static void pxa_ack_low_gpio(unsigned int irq)
213 GEDR0 = (1 << (irq - IRQ_GPIO0)); 165 GEDR0 = (1 << (irq - IRQ_GPIO0));
214} 166}
215 167
216static int pxa_set_gpio_wake(unsigned int irq, unsigned int on)
217{
218 int gpio = IRQ_TO_GPIO(irq);
219 u32 mask = WAKEMASK(gpio);
220
221 if (!mask)
222 return -EINVAL;
223
224 if (on)
225 PWER |= mask;
226 else
227 PWER &= ~mask;
228 return 0;
229}
230
231
232static struct irq_chip pxa_low_gpio_chip = { 168static struct irq_chip pxa_low_gpio_chip = {
233 .name = "GPIO-l", 169 .name = "GPIO-l",
234 .ack = pxa_ack_low_gpio, 170 .ack = pxa_ack_low_gpio,
235 .mask = pxa_mask_low_irq, 171 .mask = pxa_mask_low_irq,
236 .unmask = pxa_unmask_low_irq, 172 .unmask = pxa_unmask_low_irq,
237 .set_type = pxa_gpio_irq_type, 173 .set_type = pxa_gpio_irq_type,
238 .set_wake = pxa_set_gpio_wake,
239}; 174};
240 175
241/* 176/*
@@ -342,13 +277,14 @@ static struct irq_chip pxa_muxed_gpio_chip = {
342 .mask = pxa_mask_muxed_gpio, 277 .mask = pxa_mask_muxed_gpio,
343 .unmask = pxa_unmask_muxed_gpio, 278 .unmask = pxa_unmask_muxed_gpio,
344 .set_type = pxa_gpio_irq_type, 279 .set_type = pxa_gpio_irq_type,
345 .set_wake = pxa_set_gpio_wake,
346}; 280};
347 281
348void __init pxa_init_irq_gpio(int gpio_nr) 282void __init pxa_init_irq_gpio(int gpio_nr)
349{ 283{
350 int irq, i; 284 int irq, i;
351 285
286 pxa_last_gpio = gpio_nr - 1;
287
352 /* clear all GPIO edge detects */ 288 /* clear all GPIO edge detects */
353 for (i = 0; i < gpio_nr; i += 32) { 289 for (i = 0; i < gpio_nr; i += 32) {
354 GFER(i) = 0; 290 GFER(i) = 0;
@@ -375,3 +311,13 @@ void __init pxa_init_irq_gpio(int gpio_nr)
375 set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low); 311 set_irq_chip(IRQ_GPIO_2_x, &pxa_internal_chip_low);
376 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); 312 set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler);
377} 313}
314
315void __init pxa_init_irq_set_wake(int (*set_wake)(unsigned int, unsigned int))
316{
317 pxa_internal_chip_low.set_wake = set_wake;
318#ifdef CONFIG_PXA27x
319 pxa_internal_chip_high.set_wake = set_wake;
320#endif
321 pxa_low_gpio_chip.set_wake = set_wake;
322 pxa_muxed_gpio_chip.set_wake = set_wake;
323}
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index e70048fd00a5..011a1a72b61c 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -512,6 +512,25 @@ static void __init lubbock_map_io(void)
512 pxa_gpio_mode(GPIO44_BTCTS_MD); 512 pxa_gpio_mode(GPIO44_BTCTS_MD);
513 pxa_gpio_mode(GPIO45_BTRTS_MD); 513 pxa_gpio_mode(GPIO45_BTRTS_MD);
514 514
515 GPSR(GPIO48_nPOE) =
516 GPIO_bit(GPIO48_nPOE) |
517 GPIO_bit(GPIO49_nPWE) |
518 GPIO_bit(GPIO50_nPIOR) |
519 GPIO_bit(GPIO51_nPIOW) |
520 GPIO_bit(GPIO52_nPCE_1) |
521 GPIO_bit(GPIO53_nPCE_2);
522
523 pxa_gpio_mode(GPIO48_nPOE_MD);
524 pxa_gpio_mode(GPIO49_nPWE_MD);
525 pxa_gpio_mode(GPIO50_nPIOR_MD);
526 pxa_gpio_mode(GPIO51_nPIOW_MD);
527 pxa_gpio_mode(GPIO52_nPCE_1_MD);
528 pxa_gpio_mode(GPIO53_nPCE_2_MD);
529 pxa_gpio_mode(GPIO54_pSKTSEL_MD);
530 pxa_gpio_mode(GPIO55_nPREG_MD);
531 pxa_gpio_mode(GPIO56_nPWAIT_MD);
532 pxa_gpio_mode(GPIO57_nIOIS16_MD);
533
515 /* This is for the SMC chip select */ 534 /* This is for the SMC chip select */
516 pxa_gpio_mode(GPIO79_nCS_3_MD); 535 pxa_gpio_mode(GPIO79_nCS_3_MD);
517 536
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index b02c79c7e6a3..a4bc3483cbb3 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -444,6 +444,25 @@ static void __init mainstone_init(void)
444 */ 444 */
445 pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD); 445 pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
446 446
447 GPSR(GPIO48_nPOE) =
448 GPIO_bit(GPIO48_nPOE) |
449 GPIO_bit(GPIO49_nPWE) |
450 GPIO_bit(GPIO50_nPIOR) |
451 GPIO_bit(GPIO51_nPIOW) |
452 GPIO_bit(GPIO85_nPCE_1) |
453 GPIO_bit(GPIO54_nPCE_2);
454
455 pxa_gpio_mode(GPIO48_nPOE_MD);
456 pxa_gpio_mode(GPIO49_nPWE_MD);
457 pxa_gpio_mode(GPIO50_nPIOR_MD);
458 pxa_gpio_mode(GPIO51_nPIOW_MD);
459 pxa_gpio_mode(GPIO85_nPCE_1_MD);
460 pxa_gpio_mode(GPIO54_nPCE_2_MD);
461 pxa_gpio_mode(GPIO79_pSKTSEL_MD);
462 pxa_gpio_mode(GPIO55_nPREG_MD);
463 pxa_gpio_mode(GPIO56_nPWAIT_MD);
464 pxa_gpio_mode(GPIO57_nIOIS16_MD);
465
447 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 466 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
448 467
449 /* reading Mainstone's "Virtual Configuration Register" 468 /* reading Mainstone's "Virtual Configuration Register"
diff --git a/arch/arm/mach-pxa/mfp.c b/arch/arm/mach-pxa/mfp.c
new file mode 100644
index 000000000000..5cd3cadbbd10
--- /dev/null
+++ b/arch/arm/mach-pxa/mfp.c
@@ -0,0 +1,235 @@
1/*
2 * linux/arch/arm/mach-pxa/mfp.c
3 *
4 * PXA3xx Multi-Function Pin Support
5 *
6 * Copyright (C) 2007 Marvell Internation Ltd.
7 *
8 * 2007-08-21: eric miao <eric.y.miao@gmail.com>
9 * initial version
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/io.h>
20
21#include <asm/hardware.h>
22#include <asm/arch/mfp.h>
23
24/* mfp_spin_lock is used to ensure that MFP register configuration
25 * (most likely a read-modify-write operation) is atomic, and that
26 * mfp_table[] is consistent
27 */
28static DEFINE_SPINLOCK(mfp_spin_lock);
29
30static void __iomem *mfpr_mmio_base = (void __iomem *)&__REG(MFPR_BASE);
31static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX];
32
33#define mfpr_readl(off) \
34 __raw_readl(mfpr_mmio_base + (off))
35
36#define mfpr_writel(off, val) \
37 __raw_writel(val, mfpr_mmio_base + (off))
38
39/*
40 * perform a read-back of any MFPR register to make sure the
41 * previous writings are finished
42 */
43#define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0)
44
45static inline void __mfp_config(int pin, unsigned long val)
46{
47 unsigned long off = mfp_table[pin].mfpr_off;
48
49 mfp_table[pin].mfpr_val = val;
50 mfpr_writel(off, val);
51}
52
53void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num)
54{
55 int i, pin;
56 unsigned long val, flags;
57 mfp_cfg_t *mfp_cfg = mfp_cfgs;
58
59 spin_lock_irqsave(&mfp_spin_lock, flags);
60
61 for (i = 0; i < num; i++, mfp_cfg++) {
62 pin = MFP_CFG_PIN(*mfp_cfg);
63 val = MFP_CFG_VAL(*mfp_cfg);
64
65 BUG_ON(pin >= MFP_PIN_MAX);
66
67 __mfp_config(pin, val);
68 }
69
70 mfpr_sync();
71 spin_unlock_irqrestore(&mfp_spin_lock, flags);
72}
73
74unsigned long pxa3xx_mfp_read(int mfp)
75{
76 unsigned long val, flags;
77
78 BUG_ON(mfp >= MFP_PIN_MAX);
79
80 spin_lock_irqsave(&mfp_spin_lock, flags);
81 val = mfpr_readl(mfp_table[mfp].mfpr_off);
82 spin_unlock_irqrestore(&mfp_spin_lock, flags);
83
84 return val;
85}
86
87void pxa3xx_mfp_write(int mfp, unsigned long val)
88{
89 unsigned long flags;
90
91 BUG_ON(mfp >= MFP_PIN_MAX);
92
93 spin_lock_irqsave(&mfp_spin_lock, flags);
94 mfpr_writel(mfp_table[mfp].mfpr_off, val);
95 mfpr_sync();
96 spin_unlock_irqrestore(&mfp_spin_lock, flags);
97}
98
99void pxa3xx_mfp_set_afds(int mfp, int af, int ds)
100{
101 uint32_t mfpr_off, mfpr_val;
102 unsigned long flags;
103
104 BUG_ON(mfp >= MFP_PIN_MAX);
105
106 spin_lock_irqsave(&mfp_spin_lock, flags);
107 mfpr_off = mfp_table[mfp].mfpr_off;
108
109 mfpr_val = mfpr_readl(mfpr_off);
110 mfpr_val &= ~(MFPR_AF_MASK | MFPR_DRV_MASK);
111 mfpr_val |= (((af & 0x7) << MFPR_ALT_OFFSET) |
112 ((ds & 0x7) << MFPR_DRV_OFFSET));
113
114 mfpr_writel(mfpr_off, mfpr_val);
115 mfpr_sync();
116
117 spin_unlock_irqrestore(&mfp_spin_lock, flags);
118}
119
120void pxa3xx_mfp_set_rdh(int mfp, int rdh)
121{
122 uint32_t mfpr_off, mfpr_val;
123 unsigned long flags;
124
125 BUG_ON(mfp >= MFP_PIN_MAX);
126
127 spin_lock_irqsave(&mfp_spin_lock, flags);
128
129 mfpr_off = mfp_table[mfp].mfpr_off;
130
131 mfpr_val = mfpr_readl(mfpr_off);
132 mfpr_val &= ~MFPR_RDH_MASK;
133
134 if (likely(rdh))
135 mfpr_val |= (1u << MFPR_SS_OFFSET);
136
137 mfpr_writel(mfpr_off, mfpr_val);
138 mfpr_sync();
139
140 spin_unlock_irqrestore(&mfp_spin_lock, flags);
141}
142
143void pxa3xx_mfp_set_lpm(int mfp, int lpm)
144{
145 uint32_t mfpr_off, mfpr_val;
146 unsigned long flags;
147
148 BUG_ON(mfp >= MFP_PIN_MAX);
149
150 spin_lock_irqsave(&mfp_spin_lock, flags);
151
152 mfpr_off = mfp_table[mfp].mfpr_off;
153 mfpr_val = mfpr_readl(mfpr_off);
154 mfpr_val &= ~MFPR_LPM_MASK;
155
156 if (lpm & 0x1) mfpr_val |= 1u << MFPR_SON_OFFSET;
157 if (lpm & 0x2) mfpr_val |= 1u << MFPR_SD_OFFSET;
158 if (lpm & 0x4) mfpr_val |= 1u << MFPR_PU_OFFSET;
159 if (lpm & 0x8) mfpr_val |= 1u << MFPR_PD_OFFSET;
160 if (lpm &0x10) mfpr_val |= 1u << MFPR_PS_OFFSET;
161
162 mfpr_writel(mfpr_off, mfpr_val);
163 mfpr_sync();
164
165 spin_unlock_irqrestore(&mfp_spin_lock, flags);
166}
167
168void pxa3xx_mfp_set_pull(int mfp, int pull)
169{
170 uint32_t mfpr_off, mfpr_val;
171 unsigned long flags;
172
173 BUG_ON(mfp >= MFP_PIN_MAX);
174
175 spin_lock_irqsave(&mfp_spin_lock, flags);
176
177 mfpr_off = mfp_table[mfp].mfpr_off;
178 mfpr_val = mfpr_readl(mfpr_off);
179 mfpr_val &= ~MFPR_PULL_MASK;
180 mfpr_val |= ((pull & 0x7u) << MFPR_PD_OFFSET);
181
182 mfpr_writel(mfpr_off, mfpr_val);
183 mfpr_sync();
184
185 spin_unlock_irqrestore(&mfp_spin_lock, flags);
186}
187
188void pxa3xx_mfp_set_edge(int mfp, int edge)
189{
190 uint32_t mfpr_off, mfpr_val;
191 unsigned long flags;
192
193 BUG_ON(mfp >= MFP_PIN_MAX);
194
195 spin_lock_irqsave(&mfp_spin_lock, flags);
196
197 mfpr_off = mfp_table[mfp].mfpr_off;
198 mfpr_val = mfpr_readl(mfpr_off);
199
200 mfpr_val &= ~MFPR_EDGE_MASK;
201 mfpr_val |= (edge & 0x3u) << MFPR_ERE_OFFSET;
202 mfpr_val |= (!edge & 0x1) << MFPR_EC_OFFSET;
203
204 mfpr_writel(mfpr_off, mfpr_val);
205 mfpr_sync();
206
207 spin_unlock_irqrestore(&mfp_spin_lock, flags);
208}
209
210void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map)
211{
212 struct pxa3xx_mfp_addr_map *p;
213 unsigned long offset, flags;
214 int i;
215
216 spin_lock_irqsave(&mfp_spin_lock, flags);
217
218 for (p = map; p->start != MFP_PIN_INVALID; p++) {
219 offset = p->offset;
220 i = p->start;
221
222 do {
223 mfp_table[i].mfpr_off = offset;
224 mfp_table[i].mfpr_val = 0;
225 offset += 4; i++;
226 } while ((i <= p->end) && (p->end != -1));
227 }
228
229 spin_unlock_irqrestore(&mfp_spin_lock, flags);
230}
231
232void __init pxa3xx_init_mfp(void)
233{
234 memset(mfp_table, 0, sizeof(mfp_table));
235}
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 6dfcca72e90f..0d6a72504caa 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -30,6 +30,7 @@
30 30
31#include "generic.h" 31#include "generic.h"
32#include "devices.h" 32#include "devices.h"
33#include "clock.h"
33 34
34/* 35/*
35 * Various clock factors driven by the CCCR register. 36 * Various clock factors driven by the CCCR register.
@@ -53,7 +54,7 @@ static unsigned char N2_clk_mult[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
53 * We assume these values have been applied via a fcs. 54 * We assume these values have been applied via a fcs.
54 * If info is not 0 we also display the current settings. 55 * If info is not 0 we also display the current settings.
55 */ 56 */
56unsigned int get_clk_frequency_khz(int info) 57unsigned int pxa25x_get_clk_frequency_khz(int info)
57{ 58{
58 unsigned long cccr, turbo; 59 unsigned long cccr, turbo;
59 unsigned int l, L, m, M, n2, N; 60 unsigned int l, L, m, M, n2, N;
@@ -86,27 +87,48 @@ unsigned int get_clk_frequency_khz(int info)
86 return (turbo & 1) ? (N/1000) : (M/1000); 87 return (turbo & 1) ? (N/1000) : (M/1000);
87} 88}
88 89
89EXPORT_SYMBOL(get_clk_frequency_khz);
90
91/* 90/*
92 * Return the current memory clock frequency in units of 10kHz 91 * Return the current memory clock frequency in units of 10kHz
93 */ 92 */
94unsigned int get_memclk_frequency_10khz(void) 93unsigned int pxa25x_get_memclk_frequency_10khz(void)
95{ 94{
96 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000; 95 return L_clk_mult[(CCCR >> 0) & 0x1f] * BASE_CLK / 10000;
97} 96}
98 97
99EXPORT_SYMBOL(get_memclk_frequency_10khz); 98static unsigned long clk_pxa25x_lcd_getrate(struct clk *clk)
100
101/*
102 * Return the current LCD clock frequency in units of 10kHz
103 */
104unsigned int get_lcdclk_frequency_10khz(void)
105{ 99{
106 return get_memclk_frequency_10khz(); 100 return pxa25x_get_memclk_frequency_10khz() * 10000;
107} 101}
108 102
109EXPORT_SYMBOL(get_lcdclk_frequency_10khz); 103static const struct clkops clk_pxa25x_lcd_ops = {
104 .enable = clk_cken_enable,
105 .disable = clk_cken_disable,
106 .getrate = clk_pxa25x_lcd_getrate,
107};
108
109/*
110 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
111 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
112 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
113 */
114static struct clk pxa25x_clks[] = {
115 INIT_CK("LCDCLK", LCD, &clk_pxa25x_lcd_ops, &pxa_device_fb.dev),
116 INIT_CKEN("UARTCLK", FFUART, 14745600, 1, &pxa_device_ffuart.dev),
117 INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
118 INIT_CKEN("UARTCLK", BTUART, 14745600, 1, &pxa_device_btuart.dev),
119 INIT_CKEN("UARTCLK", STUART, 14745600, 1, NULL),
120 INIT_CKEN("UDCCLK", USB, 47923000, 5, &pxa_device_udc.dev),
121 INIT_CKEN("MMCCLK", MMC, 19169000, 0, &pxa_device_mci.dev),
122 INIT_CKEN("I2CCLK", I2C, 31949000, 0, &pxa_device_i2c.dev),
123 /*
124 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
125 INIT_CKEN("PWMCLK", PWM0, 3686400, 0, NULL),
126 INIT_CKEN("SSPCLK", SSP, 3686400, 0, NULL),
127 INIT_CKEN("I2SCLK", I2S, 14745600, 0, NULL),
128 INIT_CKEN("NSSPCLK", NSSP, 3686400, 0, NULL),
129 */
130 INIT_CKEN("FICPCLK", FICP, 47923000, 0, NULL),
131};
110 132
111#ifdef CONFIG_PM 133#ifdef CONFIG_PM
112 134
@@ -205,10 +227,52 @@ static void __init pxa25x_init_pm(void)
205} 227}
206#endif 228#endif
207 229
230/* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
231 */
232
233static int pxa25x_set_wake(unsigned int irq, unsigned int on)
234{
235 int gpio = IRQ_TO_GPIO(irq);
236 uint32_t gpio_bit, mask = 0;
237
238 if (gpio >= 0 && gpio <= 15) {
239 gpio_bit = GPIO_bit(gpio);
240 mask = gpio_bit;
241 if (on) {
242 if (GRER(gpio) | gpio_bit)
243 PRER |= gpio_bit;
244 else
245 PRER &= ~gpio_bit;
246
247 if (GFER(gpio) | gpio_bit)
248 PFER |= gpio_bit;
249 else
250 PFER &= ~gpio_bit;
251 }
252 goto set_pwer;
253 }
254
255 if (irq == IRQ_RTCAlrm) {
256 mask = PWER_RTC;
257 goto set_pwer;
258 }
259
260 return -EINVAL;
261
262set_pwer:
263 if (on)
264 PWER |= mask;
265 else
266 PWER &=~mask;
267
268 return 0;
269}
270
208void __init pxa25x_init_irq(void) 271void __init pxa25x_init_irq(void)
209{ 272{
210 pxa_init_irq_low(); 273 pxa_init_irq_low();
211 pxa_init_irq_gpio(85); 274 pxa_init_irq_gpio(85);
275 pxa_init_irq_set_wake(pxa25x_set_wake);
212} 276}
213 277
214static struct platform_device *pxa25x_devices[] __initdata = { 278static struct platform_device *pxa25x_devices[] __initdata = {
@@ -229,6 +293,8 @@ static int __init pxa25x_init(void)
229 int ret = 0; 293 int ret = 0;
230 294
231 if (cpu_is_pxa21x() || cpu_is_pxa25x()) { 295 if (cpu_is_pxa21x() || cpu_is_pxa25x()) {
296 clks_register(pxa25x_clks, ARRAY_SIZE(pxa25x_clks));
297
232 if ((ret = pxa_init_dma(16))) 298 if ((ret = pxa_init_dma(16)))
233 return ret; 299 return ret;
234#ifdef CONFIG_PM 300#ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 203371ab19db..2d7fc39732e4 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -27,6 +27,7 @@
27 27
28#include "generic.h" 28#include "generic.h"
29#include "devices.h" 29#include "devices.h"
30#include "clock.h"
30 31
31/* Crystal clock: 13MHz */ 32/* Crystal clock: 13MHz */
32#define BASE_CLK 13000000 33#define BASE_CLK 13000000
@@ -36,7 +37,7 @@
36 * We assume these values have been applied via a fcs. 37 * We assume these values have been applied via a fcs.
37 * If info is not 0 we also display the current settings. 38 * If info is not 0 we also display the current settings.
38 */ 39 */
39unsigned int get_clk_frequency_khz( int info) 40unsigned int pxa27x_get_clk_frequency_khz(int info)
40{ 41{
41 unsigned long ccsr, clkcfg; 42 unsigned long ccsr, clkcfg;
42 unsigned int l, L, m, M, n2, N, S; 43 unsigned int l, L, m, M, n2, N, S;
@@ -79,7 +80,7 @@ unsigned int get_clk_frequency_khz( int info)
79 * Return the current mem clock frequency in units of 10kHz as 80 * Return the current mem clock frequency in units of 10kHz as
80 * reflected by CCCR[A], B, and L 81 * reflected by CCCR[A], B, and L
81 */ 82 */
82unsigned int get_memclk_frequency_10khz(void) 83unsigned int pxa27x_get_memclk_frequency_10khz(void)
83{ 84{
84 unsigned long ccsr, clkcfg; 85 unsigned long ccsr, clkcfg;
85 unsigned int l, L, m, M; 86 unsigned int l, L, m, M;
@@ -104,7 +105,7 @@ unsigned int get_memclk_frequency_10khz(void)
104/* 105/*
105 * Return the current LCD clock frequency in units of 10kHz as 106 * Return the current LCD clock frequency in units of 10kHz as
106 */ 107 */
107unsigned int get_lcdclk_frequency_10khz(void) 108static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
108{ 109{
109 unsigned long ccsr; 110 unsigned long ccsr;
110 unsigned int l, L, k, K; 111 unsigned int l, L, k, K;
@@ -120,9 +121,47 @@ unsigned int get_lcdclk_frequency_10khz(void)
120 return (K / 10000); 121 return (K / 10000);
121} 122}
122 123
123EXPORT_SYMBOL(get_clk_frequency_khz); 124static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
124EXPORT_SYMBOL(get_memclk_frequency_10khz); 125{
125EXPORT_SYMBOL(get_lcdclk_frequency_10khz); 126 return pxa27x_get_lcdclk_frequency_10khz() * 10000;
127}
128
129static const struct clkops clk_pxa27x_lcd_ops = {
130 .enable = clk_cken_enable,
131 .disable = clk_cken_disable,
132 .getrate = clk_pxa27x_lcd_getrate,
133};
134
135static struct clk pxa27x_clks[] = {
136 INIT_CK("LCDCLK", LCD, &clk_pxa27x_lcd_ops, &pxa_device_fb.dev),
137 INIT_CK("CAMCLK", CAMERA, &clk_pxa27x_lcd_ops, NULL),
138
139 INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
140 INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
141 INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
142
143 INIT_CKEN("I2SCLK", I2S, 14682000, 0, &pxa_device_i2s.dev),
144 INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
145 INIT_CKEN("UDCCLK", USB, 48000000, 5, &pxa_device_udc.dev),
146 INIT_CKEN("MMCCLK", MMC, 19500000, 0, &pxa_device_mci.dev),
147 INIT_CKEN("FICPCLK", FICP, 48000000, 0, &pxa_device_ficp.dev),
148
149 INIT_CKEN("USBCLK", USB, 48000000, 0, &pxa27x_device_ohci.dev),
150 INIT_CKEN("I2CCLK", PWRI2C, 13000000, 0, &pxa27x_device_i2c_power.dev),
151 INIT_CKEN("KBDCLK", KEYPAD, 32768, 0, NULL),
152
153 /*
154 INIT_CKEN("PWMCLK", PWM0, 13000000, 0, NULL),
155 INIT_CKEN("SSPCLK", SSP1, 13000000, 0, NULL),
156 INIT_CKEN("SSPCLK", SSP2, 13000000, 0, NULL),
157 INIT_CKEN("SSPCLK", SSP3, 13000000, 0, NULL),
158 INIT_CKEN("MSLCLK", MSL, 48000000, 0, NULL),
159 INIT_CKEN("USIMCLK", USIM, 48000000, 0, NULL),
160 INIT_CKEN("MSTKCLK", MEMSTK, 19500000, 0, NULL),
161 INIT_CKEN("IMCLK", IM, 0, 0, NULL),
162 INIT_CKEN("MEMCLK", MEMC, 0, 0, NULL),
163 */
164};
126 165
127#ifdef CONFIG_PM 166#ifdef CONFIG_PM
128 167
@@ -267,6 +306,69 @@ static void __init pxa27x_init_pm(void)
267} 306}
268#endif 307#endif
269 308
309/* PXA27x: Various gpios can issue wakeup events. This logic only
310 * handles the simple cases, not the WEMUX2 and WEMUX3 options
311 */
312#define PXA27x_GPIO_NOWAKE_MASK \
313 ((1 << 8) | (1 << 7) | (1 << 6) | (1 << 5) | (1 << 2))
314#define WAKEMASK(gpio) \
315 (((gpio) <= 15) \
316 ? ((1 << (gpio)) & ~PXA27x_GPIO_NOWAKE_MASK) \
317 : ((gpio == 35) ? (1 << 24) : 0))
318
319static int pxa27x_set_wake(unsigned int irq, unsigned int on)
320{
321 int gpio = IRQ_TO_GPIO(irq);
322 uint32_t mask;
323
324 if ((gpio >= 0 && gpio <= 15) || (gpio == 35)) {
325 if (WAKEMASK(gpio) == 0)
326 return -EINVAL;
327
328 mask = WAKEMASK(gpio);
329
330 if (on) {
331 if (GRER(gpio) | GPIO_bit(gpio))
332 PRER |= mask;
333 else
334 PRER &= ~mask;
335
336 if (GFER(gpio) | GPIO_bit(gpio))
337 PFER |= mask;
338 else
339 PFER &= ~mask;
340 }
341 goto set_pwer;
342 }
343
344 switch (irq) {
345 case IRQ_RTCAlrm:
346 mask = PWER_RTC;
347 break;
348 case IRQ_USB:
349 mask = 1u << 26;
350 break;
351 default:
352 return -EINVAL;
353 }
354
355set_pwer:
356 if (on)
357 PWER |= mask;
358 else
359 PWER &=~mask;
360
361 return 0;
362}
363
364void __init pxa27x_init_irq(void)
365{
366 pxa_init_irq_low();
367 pxa_init_irq_high();
368 pxa_init_irq_gpio(128);
369 pxa_init_irq_set_wake(pxa27x_set_wake);
370}
371
270/* 372/*
271 * device registration specific to PXA27x. 373 * device registration specific to PXA27x.
272 */ 374 */
@@ -286,7 +388,7 @@ static struct resource pxa27x_ohci_resources[] = {
286 }, 388 },
287}; 389};
288 390
289static struct platform_device pxa27x_device_ohci = { 391struct platform_device pxa27x_device_ohci = {
290 .name = "pxa27x-ohci", 392 .name = "pxa27x-ohci",
291 .id = -1, 393 .id = -1,
292 .dev = { 394 .dev = {
@@ -314,7 +416,7 @@ static struct resource i2c_power_resources[] = {
314 }, 416 },
315}; 417};
316 418
317static struct platform_device pxa27x_device_i2c_power = { 419struct platform_device pxa27x_device_i2c_power = {
318 .name = "pxa2xx-i2c", 420 .name = "pxa2xx-i2c",
319 .id = 1, 421 .id = 1,
320 .resource = i2c_power_resources, 422 .resource = i2c_power_resources,
@@ -336,17 +438,12 @@ static struct platform_device *devices[] __initdata = {
336 &pxa27x_device_ohci, 438 &pxa27x_device_ohci,
337}; 439};
338 440
339void __init pxa27x_init_irq(void)
340{
341 pxa_init_irq_low();
342 pxa_init_irq_high();
343 pxa_init_irq_gpio(128);
344}
345
346static int __init pxa27x_init(void) 441static int __init pxa27x_init(void)
347{ 442{
348 int ret = 0; 443 int ret = 0;
349 if (cpu_is_pxa27x()) { 444 if (cpu_is_pxa27x()) {
445 clks_register(pxa27x_clks, ARRAY_SIZE(pxa27x_clks));
446
350 if ((ret = pxa_init_dma(32))) 447 if ((ret = pxa_init_dma(32)))
351 return ret; 448 return ret;
352#ifdef CONFIG_PM 449#ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
new file mode 100644
index 000000000000..5363b1322652
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -0,0 +1,93 @@
1/*
2 * linux/arch/arm/mach-pxa/pxa300.c
3 *
4 * Code specific to PXA300/PXA310
5 *
6 * Copyright (C) 2007 Marvell Internation Ltd.
7 *
8 * 2007-08-21: eric miao <eric.y.miao@gmail.com>
9 * initial version
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18
19#include <asm/hardware.h>
20#include <asm/arch/mfp-pxa300.h>
21
22static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = {
23
24 MFP_ADDR_X(GPIO0, GPIO2, 0x00b4),
25 MFP_ADDR_X(GPIO3, GPIO26, 0x027c),
26 MFP_ADDR_X(GPIO27, GPIO127, 0x0400),
27 MFP_ADDR_X(GPIO0_2, GPIO6_2, 0x02ec),
28
29 MFP_ADDR(nBE0, 0x0204),
30 MFP_ADDR(nBE1, 0x0208),
31
32 MFP_ADDR(nLUA, 0x0244),
33 MFP_ADDR(nLLA, 0x0254),
34
35 MFP_ADDR(DF_CLE_nOE, 0x0240),
36 MFP_ADDR(DF_nRE_nOE, 0x0200),
37 MFP_ADDR(DF_ALE_nWE, 0x020C),
38 MFP_ADDR(DF_INT_RnB, 0x00C8),
39 MFP_ADDR(DF_nCS0, 0x0248),
40 MFP_ADDR(DF_nCS1, 0x0278),
41 MFP_ADDR(DF_nWE, 0x00CC),
42
43 MFP_ADDR(DF_ADDR0, 0x0210),
44 MFP_ADDR(DF_ADDR1, 0x0214),
45 MFP_ADDR(DF_ADDR2, 0x0218),
46 MFP_ADDR(DF_ADDR3, 0x021C),
47
48 MFP_ADDR(DF_IO0, 0x0220),
49 MFP_ADDR(DF_IO1, 0x0228),
50 MFP_ADDR(DF_IO2, 0x0230),
51 MFP_ADDR(DF_IO3, 0x0238),
52 MFP_ADDR(DF_IO4, 0x0258),
53 MFP_ADDR(DF_IO5, 0x0260),
54 MFP_ADDR(DF_IO6, 0x0268),
55 MFP_ADDR(DF_IO7, 0x0270),
56 MFP_ADDR(DF_IO8, 0x0224),
57 MFP_ADDR(DF_IO9, 0x022C),
58 MFP_ADDR(DF_IO10, 0x0234),
59 MFP_ADDR(DF_IO11, 0x023C),
60 MFP_ADDR(DF_IO12, 0x025C),
61 MFP_ADDR(DF_IO13, 0x0264),
62 MFP_ADDR(DF_IO14, 0x026C),
63 MFP_ADDR(DF_IO15, 0x0274),
64
65 MFP_ADDR_END,
66};
67
68/* override pxa300 MFP register addresses */
69static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = {
70 MFP_ADDR_X(GPIO30, GPIO98, 0x0418),
71 MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C),
72
73 MFP_ADDR(ULPI_STP, 0x040C),
74 MFP_ADDR(ULPI_NXT, 0x0410),
75 MFP_ADDR(ULPI_DIR, 0x0414),
76
77 MFP_ADDR_END,
78};
79
80static int __init pxa300_init(void)
81{
82 if (cpu_is_pxa300() || cpu_is_pxa310()) {
83 pxa3xx_init_mfp();
84 pxa3xx_mfp_init_addr(pxa300_mfp_addr_map);
85 }
86
87 if (cpu_is_pxa310())
88 pxa3xx_mfp_init_addr(pxa310_mfp_addr_map);
89
90 return 0;
91}
92
93core_initcall(pxa300_init);
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
new file mode 100644
index 000000000000..cd9eba5b3df9
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -0,0 +1,88 @@
1/*
2 * linux/arch/arm/mach-pxa/pxa320.c
3 *
4 * Code specific to PXA320
5 *
6 * Copyright (C) 2007 Marvell Internation Ltd.
7 *
8 * 2007-08-21: eric miao <eric.y.miao@gmail.com>
9 * initial version
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18
19#include <asm/hardware.h>
20#include <asm/arch/mfp.h>
21#include <asm/arch/mfp-pxa320.h>
22
23static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
24
25 MFP_ADDR_X(GPIO0, GPIO4, 0x0124),
26 MFP_ADDR_X(GPIO5, GPIO26, 0x028C),
27 MFP_ADDR_X(GPIO27, GPIO62, 0x0400),
28 MFP_ADDR_X(GPIO63, GPIO73, 0x04B4),
29 MFP_ADDR_X(GPIO74, GPIO98, 0x04F0),
30 MFP_ADDR_X(GPIO99, GPIO127, 0x0600),
31 MFP_ADDR_X(GPIO0_2, GPIO5_2, 0x0674),
32 MFP_ADDR_X(GPIO6_2, GPIO13_2, 0x0494),
33 MFP_ADDR_X(GPIO14_2, GPIO17_2, 0x04E0),
34
35 MFP_ADDR(nXCVREN, 0x0138),
36 MFP_ADDR(DF_CLE_nOE, 0x0204),
37 MFP_ADDR(DF_nADV1_ALE, 0x0208),
38 MFP_ADDR(DF_SCLK_S, 0x020C),
39 MFP_ADDR(DF_SCLK_E, 0x0210),
40 MFP_ADDR(nBE0, 0x0214),
41 MFP_ADDR(nBE1, 0x0218),
42 MFP_ADDR(DF_nADV2_ALE, 0x021C),
43 MFP_ADDR(DF_INT_RnB, 0x0220),
44 MFP_ADDR(DF_nCS0, 0x0224),
45 MFP_ADDR(DF_nCS1, 0x0228),
46 MFP_ADDR(DF_nWE, 0x022C),
47 MFP_ADDR(DF_nRE_nOE, 0x0230),
48 MFP_ADDR(nLUA, 0x0234),
49 MFP_ADDR(nLLA, 0x0238),
50 MFP_ADDR(DF_ADDR0, 0x023C),
51 MFP_ADDR(DF_ADDR1, 0x0240),
52 MFP_ADDR(DF_ADDR2, 0x0244),
53 MFP_ADDR(DF_ADDR3, 0x0248),
54 MFP_ADDR(DF_IO0, 0x024C),
55 MFP_ADDR(DF_IO8, 0x0250),
56 MFP_ADDR(DF_IO1, 0x0254),
57 MFP_ADDR(DF_IO9, 0x0258),
58 MFP_ADDR(DF_IO2, 0x025C),
59 MFP_ADDR(DF_IO10, 0x0260),
60 MFP_ADDR(DF_IO3, 0x0264),
61 MFP_ADDR(DF_IO11, 0x0268),
62 MFP_ADDR(DF_IO4, 0x026C),
63 MFP_ADDR(DF_IO12, 0x0270),
64 MFP_ADDR(DF_IO5, 0x0274),
65 MFP_ADDR(DF_IO13, 0x0278),
66 MFP_ADDR(DF_IO6, 0x027C),
67 MFP_ADDR(DF_IO14, 0x0280),
68 MFP_ADDR(DF_IO7, 0x0284),
69 MFP_ADDR(DF_IO15, 0x0288),
70
71 MFP_ADDR_END,
72};
73
74static void __init pxa320_init_mfp(void)
75{
76 pxa3xx_init_mfp();
77 pxa3xx_mfp_init_addr(pxa320_mfp_addr_map);
78}
79
80static int __init pxa320_init(void)
81{
82 if (cpu_is_pxa320())
83 pxa320_init_mfp();
84
85 return 0;
86}
87
88core_initcall(pxa320_init);
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
new file mode 100644
index 000000000000..39f0de8c189e
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -0,0 +1,216 @@
1/*
2 * linux/arch/arm/mach-pxa/pxa3xx.c
3 *
4 * code specific to pxa3xx aka Monahans
5 *
6 * Copyright (C) 2006 Marvell International Ltd.
7 *
8 * 2007-09-02: eric miao <eric.y.miao@gmail.com>
9 * initial version
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/pm.h>
20#include <linux/platform_device.h>
21#include <linux/irq.h>
22
23#include <asm/hardware.h>
24#include <asm/arch/pxa3xx-regs.h>
25#include <asm/arch/ohci.h>
26#include <asm/arch/pm.h>
27#include <asm/arch/dma.h>
28#include <asm/arch/ssp.h>
29
30#include "generic.h"
31#include "devices.h"
32#include "clock.h"
33
34/* Crystal clock: 13MHz */
35#define BASE_CLK 13000000
36
37/* Ring Oscillator Clock: 60MHz */
38#define RO_CLK 60000000
39
40#define ACCR_D0CS (1 << 26)
41
42/* crystal frequency to static memory controller multiplier (SMCFS) */
43static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
44
45/* crystal frequency to HSIO bus frequency multiplier (HSS) */
46static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
47
48/*
49 * Get the clock frequency as reflected by CCSR and the turbo flag.
50 * We assume these values have been applied via a fcs.
51 * If info is not 0 we also display the current settings.
52 */
53unsigned int pxa3xx_get_clk_frequency_khz(int info)
54{
55 unsigned long acsr, xclkcfg;
56 unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
57
58 /* Read XCLKCFG register turbo bit */
59 __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
60 t = xclkcfg & 0x1;
61
62 acsr = ACSR;
63
64 xl = acsr & 0x1f;
65 xn = (acsr >> 8) & 0x7;
66 hss = (acsr >> 14) & 0x3;
67
68 XL = xl * BASE_CLK;
69 XN = xn * XL;
70
71 ro = acsr & ACCR_D0CS;
72
73 CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
74 HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
75
76 if (info) {
77 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
78 RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
79 (ro) ? "" : "in");
80 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
81 XL / 1000000, (XL % 1000000) / 10000, xl);
82 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
83 XN / 1000000, (XN % 1000000) / 10000, xn,
84 (t) ? "" : "in");
85 pr_info("HSIO bus clock: %d.%02dMHz\n",
86 HSS / 1000000, (HSS % 1000000) / 10000);
87 }
88
89 return CLK;
90}
91
92/*
93 * Return the current static memory controller clock frequency
94 * in units of 10kHz
95 */
96unsigned int pxa3xx_get_memclk_frequency_10khz(void)
97{
98 unsigned long acsr;
99 unsigned int smcfs, clk = 0;
100
101 acsr = ACSR;
102
103 smcfs = (acsr >> 23) & 0x7;
104 clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
105
106 return (clk / 10000);
107}
108
109/*
110 * Return the current HSIO bus clock frequency
111 */
112static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
113{
114 unsigned long acsr;
115 unsigned int hss, hsio_clk;
116
117 acsr = ACSR;
118
119 hss = (acsr >> 14) & 0x3;
120 hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
121
122 return hsio_clk;
123}
124
125static void clk_pxa3xx_cken_enable(struct clk *clk)
126{
127 unsigned long mask = 1ul << (clk->cken & 0x1f);
128
129 local_irq_disable();
130
131 if (clk->cken < 32)
132 CKENA |= mask;
133 else
134 CKENB |= mask;
135
136 local_irq_enable();
137}
138
139static void clk_pxa3xx_cken_disable(struct clk *clk)
140{
141 unsigned long mask = 1ul << (clk->cken & 0x1f);
142
143 local_irq_disable();
144
145 if (clk->cken < 32)
146 CKENA &= ~mask;
147 else
148 CKENB &= ~mask;
149
150 local_irq_enable();
151}
152
153static const struct clkops clk_pxa3xx_hsio_ops = {
154 .enable = clk_pxa3xx_cken_enable,
155 .disable = clk_pxa3xx_cken_disable,
156 .getrate = clk_pxa3xx_hsio_getrate,
157};
158
159static struct clk pxa3xx_clks[] = {
160 INIT_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
161 INIT_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
162
163 INIT_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
164 INIT_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
165 INIT_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
166
167 INIT_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
168 INIT_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev),
169};
170
171void __init pxa3xx_init_irq(void)
172{
173 /* enable CP6 access */
174 u32 value;
175 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
176 value |= (1 << 6);
177 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
178
179 pxa_init_irq_low();
180 pxa_init_irq_high();
181 pxa_init_irq_gpio(128);
182}
183
184/*
185 * device registration specific to PXA3xx.
186 */
187
188static struct platform_device *devices[] __initdata = {
189 &pxa_device_mci,
190 &pxa_device_udc,
191 &pxa_device_fb,
192 &pxa_device_ffuart,
193 &pxa_device_btuart,
194 &pxa_device_stuart,
195 &pxa_device_i2c,
196 &pxa_device_i2s,
197 &pxa_device_ficp,
198 &pxa_device_rtc,
199};
200
201static int __init pxa3xx_init(void)
202{
203 int ret = 0;
204
205 if (cpu_is_pxa3xx()) {
206 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
207
208 if ((ret = pxa_init_dma(32)))
209 return ret;
210
211 return platform_add_devices(devices, ARRAY_SIZE(devices));
212 }
213 return 0;
214}
215
216subsys_initcall(pxa3xx_init);
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 98d27e646b09..ec4286c7931c 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -16,10 +16,48 @@
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/clockchips.h> 18#include <linux/clockchips.h>
19#include <linux/sched.h>
19 20
21#include <asm/div64.h>
22#include <asm/cnt32_to_63.h>
20#include <asm/mach/irq.h> 23#include <asm/mach/irq.h>
21#include <asm/mach/time.h> 24#include <asm/mach/time.h>
22#include <asm/arch/pxa-regs.h> 25#include <asm/arch/pxa-regs.h>
26#include <asm/mach-types.h>
27
28/*
29 * This is PXA's sched_clock implementation. This has a resolution
30 * of at least 308 ns and a maximum value of 208 days.
31 *
32 * The return value is guaranteed to be monotonic in that range as
33 * long as there is always less than 582 seconds between successive
34 * calls to sched_clock() which should always be the case in practice.
35 */
36
37#define OSCR2NS_SCALE_FACTOR 10
38
39static unsigned long oscr2ns_scale;
40
41static void __init set_oscr2ns_scale(unsigned long oscr_rate)
42{
43 unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR;
44 do_div(v, oscr_rate);
45 oscr2ns_scale = v;
46 /*
47 * We want an even value to automatically clear the top bit
48 * returned by cnt32_to_63() without an additional run time
49 * instruction. So if the LSB is 1 then round it up.
50 */
51 if (oscr2ns_scale & 1)
52 oscr2ns_scale++;
53}
54
55unsigned long long sched_clock(void)
56{
57 unsigned long long v = cnt32_to_63(OSCR);
58 return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR;
59}
60
23 61
24static irqreturn_t 62static irqreturn_t
25pxa_ost0_interrupt(int irq, void *dev_id) 63pxa_ost0_interrupt(int irq, void *dev_id)
@@ -149,18 +187,29 @@ static struct irqaction pxa_ost0_irq = {
149 187
150static void __init pxa_timer_init(void) 188static void __init pxa_timer_init(void)
151{ 189{
190 unsigned long clock_tick_rate;
191
152 OIER = 0; 192 OIER = 0;
153 OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3; 193 OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
154 194
195 if (cpu_is_pxa21x() || cpu_is_pxa25x())
196 clock_tick_rate = 3686400;
197 else if (machine_is_mainstone())
198 clock_tick_rate = 3249600;
199 else
200 clock_tick_rate = 3250000;
201
202 set_oscr2ns_scale(clock_tick_rate);
203
155 ckevt_pxa_osmr0.mult = 204 ckevt_pxa_osmr0.mult =
156 div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt_pxa_osmr0.shift); 205 div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
157 ckevt_pxa_osmr0.max_delta_ns = 206 ckevt_pxa_osmr0.max_delta_ns =
158 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0); 207 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
159 ckevt_pxa_osmr0.min_delta_ns = 208 ckevt_pxa_osmr0.min_delta_ns =
160 clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1; 209 clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1;
161 210
162 cksrc_pxa_oscr0.mult = 211 cksrc_pxa_oscr0.mult =
163 clocksource_hz2mult(CLOCK_TICK_RATE, cksrc_pxa_oscr0.shift); 212 clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);
164 213
165 setup_irq(IRQ_OST0, &pxa_ost0_irq); 214 setup_irq(IRQ_OST0, &pxa_ost0_irq);
166 215
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
new file mode 100644
index 000000000000..3f18d760dd1b
--- /dev/null
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -0,0 +1,184 @@
1/*
2 * linux/arch/arm/mach-pxa/zylonite.c
3 *
4 * Support for the PXA3xx Development Platform (aka Zylonite)
5 *
6 * Copyright (C) 2006 Marvell International Ltd.
7 *
8 * 2007-09-04: eric miao <eric.y.miao@gmail.com>
9 * rewrite to align with latest kernel
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/interrupt.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21
22#include <asm/mach-types.h>
23#include <asm/mach/arch.h>
24#include <asm/hardware.h>
25#include <asm/arch/gpio.h>
26#include <asm/arch/pxafb.h>
27#include <asm/arch/zylonite.h>
28
29#include "generic.h"
30
31int gpio_backlight;
32int gpio_eth_irq;
33
34int lcd_id;
35int lcd_orientation;
36
37static struct resource smc91x_resources[] = {
38 [0] = {
39 .start = ZYLONITE_ETH_PHYS + 0x300,
40 .end = ZYLONITE_ETH_PHYS + 0xfffff,
41 .flags = IORESOURCE_MEM,
42 },
43 [1] = {
44 .start = -1, /* for run-time assignment */
45 .end = -1,
46 .flags = IORESOURCE_IRQ,
47 }
48};
49
50static struct platform_device smc91x_device = {
51 .name = "smc91x",
52 .id = 0,
53 .num_resources = ARRAY_SIZE(smc91x_resources),
54 .resource = smc91x_resources,
55};
56
57#if defined(CONFIG_FB_PXA) || (CONFIG_FB_PXA_MODULES)
58static void zylonite_backlight_power(int on)
59{
60 gpio_set_value(gpio_backlight, on);
61}
62
63static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
64 .pixclock = 110000,
65 .xres = 240,
66 .yres = 320,
67 .bpp = 16,
68 .hsync_len = 4,
69 .left_margin = 6,
70 .right_margin = 4,
71 .vsync_len = 2,
72 .upper_margin = 2,
73 .lower_margin = 3,
74 .sync = FB_SYNC_VERT_HIGH_ACT,
75};
76
77static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
78 .pixclock = 50000,
79 .xres = 640,
80 .yres = 480,
81 .bpp = 16,
82 .hsync_len = 1,
83 .left_margin = 0x9f,
84 .right_margin = 1,
85 .vsync_len = 44,
86 .upper_margin = 0,
87 .lower_margin = 0,
88 .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
89};
90
91static struct pxafb_mach_info zylonite_toshiba_lcd_info = {
92 .num_modes = 1,
93 .lccr0 = LCCR0_Act,
94 .lccr3 = LCCR3_PCP,
95 .pxafb_backlight_power = zylonite_backlight_power,
96};
97
98static struct pxafb_mode_info sharp_ls037_modes[] = {
99 [0] = {
100 .pixclock = 158000,
101 .xres = 240,
102 .yres = 320,
103 .bpp = 16,
104 .hsync_len = 4,
105 .left_margin = 39,
106 .right_margin = 39,
107 .vsync_len = 1,
108 .upper_margin = 2,
109 .lower_margin = 3,
110 .sync = 0,
111 },
112 [1] = {
113 .pixclock = 39700,
114 .xres = 480,
115 .yres = 640,
116 .bpp = 16,
117 .hsync_len = 8,
118 .left_margin = 81,
119 .right_margin = 81,
120 .vsync_len = 1,
121 .upper_margin = 2,
122 .lower_margin = 7,
123 .sync = 0,
124 },
125};
126
127static struct pxafb_mach_info zylonite_sharp_lcd_info = {
128 .modes = sharp_ls037_modes,
129 .num_modes = 2,
130 .lccr0 = LCCR0_Act,
131 .lccr3 = LCCR3_PCP | LCCR3_HSP | LCCR3_VSP,
132 .pxafb_backlight_power = zylonite_backlight_power,
133};
134
135static void __init zylonite_init_lcd(void)
136{
137 /* backlight GPIO: output, default on */
138 gpio_direction_output(gpio_backlight, 1);
139
140 if (lcd_id & 0x20) {
141 set_pxa_fb_info(&zylonite_sharp_lcd_info);
142 return;
143 }
144
145 /* legacy LCD panels, it would be handy here if LCD panel type can
146 * be decided at run-time
147 */
148 if (1)
149 zylonite_toshiba_lcd_info.modes = &toshiba_ltm035a776c_mode;
150 else
151 zylonite_toshiba_lcd_info.modes = &toshiba_ltm04c380k_mode;
152
153 set_pxa_fb_info(&zylonite_toshiba_lcd_info);
154}
155#else
156static inline void zylonite_init_lcd(void) {}
157#endif
158
159static void __init zylonite_init(void)
160{
161 /* board-processor specific initialization */
162 zylonite_pxa300_init();
163 zylonite_pxa320_init();
164
165 /*
166 * Note: We depend that the bootloader set
167 * the correct value to MSC register for SMC91x.
168 */
169 smc91x_resources[1].start = gpio_to_irq(gpio_eth_irq);
170 smc91x_resources[1].end = gpio_to_irq(gpio_eth_irq);
171 platform_device_register(&smc91x_device);
172
173 zylonite_init_lcd();
174}
175
176MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
177 .phys_io = 0x40000000,
178 .boot_params = 0xa0000100,
179 .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
180 .map_io = pxa_map_io,
181 .init_irq = pxa3xx_init_irq,
182 .timer = &pxa_timer,
183 .init_machine = zylonite_init,
184MACHINE_END
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
new file mode 100644
index 000000000000..b5fbd2f4c693
--- /dev/null
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -0,0 +1,188 @@
1/*
2 * linux/arch/arm/mach-pxa/zylonite_pxa300.c
3 *
4 * PXA300/PXA310 specific support code for the
5 * PXA3xx Development Platform (aka Zylonite)
6 *
7 * Copyright (C) 2007 Marvell Internation Ltd.
8 * 2007-08-21: eric miao <eric.y.miao@gmail.com>
9 * initial version
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19
20#include <asm/gpio.h>
21#include <asm/arch/mfp-pxa300.h>
22#include <asm/arch/zylonite.h>
23
24#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
25
26/* PXA300/PXA310 common configurations */
27static mfp_cfg_t common_mfp_cfg[] __initdata = {
28 /* LCD */
29 GPIO54_LCD_LDD_0,
30 GPIO55_LCD_LDD_1,
31 GPIO56_LCD_LDD_2,
32 GPIO57_LCD_LDD_3,
33 GPIO58_LCD_LDD_4,
34 GPIO59_LCD_LDD_5,
35 GPIO60_LCD_LDD_6,
36 GPIO61_LCD_LDD_7,
37 GPIO62_LCD_LDD_8,
38 GPIO63_LCD_LDD_9,
39 GPIO64_LCD_LDD_10,
40 GPIO65_LCD_LDD_11,
41 GPIO66_LCD_LDD_12,
42 GPIO67_LCD_LDD_13,
43 GPIO68_LCD_LDD_14,
44 GPIO69_LCD_LDD_15,
45 GPIO70_LCD_LDD_16,
46 GPIO71_LCD_LDD_17,
47 GPIO72_LCD_FCLK,
48 GPIO73_LCD_LCLK,
49 GPIO74_LCD_PCLK,
50 GPIO75_LCD_BIAS,
51 GPIO76_LCD_VSYNC,
52 GPIO127_LCD_CS_N,
53
54 /* BTUART */
55 GPIO111_UART2_RTS,
56 GPIO112_UART2_RXD,
57 GPIO113_UART2_TXD,
58 GPIO114_UART2_CTS,
59
60 /* STUART */
61 GPIO109_UART3_TXD,
62 GPIO110_UART3_RXD,
63
64 /* AC97 */
65 GPIO23_AC97_nACRESET,
66 GPIO24_AC97_SYSCLK,
67 GPIO29_AC97_BITCLK,
68 GPIO25_AC97_SDATA_IN_0,
69 GPIO27_AC97_SDATA_OUT,
70 GPIO28_AC97_SYNC,
71
72 /* Keypad */
73 GPIO107_KP_DKIN_0,
74 GPIO108_KP_DKIN_1,
75 GPIO115_KP_MKIN_0,
76 GPIO116_KP_MKIN_1,
77 GPIO117_KP_MKIN_2,
78 GPIO118_KP_MKIN_3,
79 GPIO119_KP_MKIN_4,
80 GPIO120_KP_MKIN_5,
81 GPIO2_2_KP_MKIN_6,
82 GPIO3_2_KP_MKIN_7,
83 GPIO121_KP_MKOUT_0,
84 GPIO122_KP_MKOUT_1,
85 GPIO123_KP_MKOUT_2,
86 GPIO124_KP_MKOUT_3,
87 GPIO125_KP_MKOUT_4,
88 GPIO4_2_KP_MKOUT_5,
89 GPIO5_2_KP_MKOUT_6,
90 GPIO6_2_KP_MKOUT_7,
91};
92
93static mfp_cfg_t pxa300_mfp_cfg[] __initdata = {
94 /* FFUART */
95 GPIO30_UART1_RXD,
96 GPIO31_UART1_TXD,
97 GPIO32_UART1_CTS,
98 GPIO37_UART1_RTS,
99 GPIO33_UART1_DCD,
100 GPIO34_UART1_DSR,
101 GPIO35_UART1_RI,
102 GPIO36_UART1_DTR,
103
104 /* Ethernet */
105 GPIO2_nCS3,
106 GPIO99_GPIO,
107};
108
109static mfp_cfg_t pxa310_mfp_cfg[] __initdata = {
110 /* FFUART */
111 GPIO99_UART1_RXD,
112 GPIO100_UART1_TXD,
113 GPIO101_UART1_CTS,
114 GPIO106_UART1_RTS,
115
116 /* Ethernet */
117 GPIO2_nCS3,
118 GPIO102_GPIO,
119};
120
121#define NUM_LCD_DETECT_PINS 7
122
123static int lcd_detect_pins[] __initdata = {
124 MFP_PIN_GPIO71, /* LCD_LDD_17 - ORIENT */
125 MFP_PIN_GPIO70, /* LCD_LDD_16 - LCDID[5] */
126 MFP_PIN_GPIO75, /* LCD_BIAS - LCDID[4] */
127 MFP_PIN_GPIO73, /* LCD_LCLK - LCDID[3] */
128 MFP_PIN_GPIO72, /* LCD_FCLK - LCDID[2] */
129 MFP_PIN_GPIO127,/* LCD_CS_N - LCDID[1] */
130 MFP_PIN_GPIO76, /* LCD_VSYNC - LCDID[0] */
131};
132
133static void __init zylonite_detect_lcd_panel(void)
134{
135 unsigned long mfpr_save[NUM_LCD_DETECT_PINS];
136 int i, gpio, id = 0;
137
138 /* save the original MFP settings of these pins and configure
139 * them as GPIO Input, DS01X, Pull Neither, Edge Clear
140 */
141 for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
142 mfpr_save[i] = pxa3xx_mfp_read(lcd_detect_pins[i]);
143 pxa3xx_mfp_write(lcd_detect_pins[i], 0x8440);
144 }
145
146 for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
147 id = id << 1;
148 gpio = mfp_to_gpio(lcd_detect_pins[i]);
149 gpio_direction_input(gpio);
150
151 if (gpio_get_value(gpio))
152 id = id | 0x1;
153 }
154
155 /* lcd id, flush out bit 1 */
156 lcd_id = id & 0x3d;
157
158 /* lcd orientation, portrait or landscape */
159 lcd_orientation = (id >> 6) & 0x1;
160
161 /* restore the original MFP settings */
162 for (i = 0; i < NUM_LCD_DETECT_PINS; i++)
163 pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]);
164}
165
166void __init zylonite_pxa300_init(void)
167{
168 if (cpu_is_pxa300() || cpu_is_pxa310()) {
169 /* initialize MFP */
170 pxa3xx_mfp_config(ARRAY_AND_SIZE(common_mfp_cfg));
171
172 /* detect LCD panel */
173 zylonite_detect_lcd_panel();
174
175 /* GPIO pin assignment */
176 gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO20);
177 }
178
179 if (cpu_is_pxa300()) {
180 pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa300_mfp_cfg));
181 gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO99);
182 }
183
184 if (cpu_is_pxa310()) {
185 pxa3xx_mfp_config(ARRAY_AND_SIZE(pxa310_mfp_cfg));
186 gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO102);
187 }
188}
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c
new file mode 100644
index 000000000000..63cb36be086b
--- /dev/null
+++ b/arch/arm/mach-pxa/zylonite_pxa320.c
@@ -0,0 +1,173 @@
1/*
2 * linux/arch/arm/mach-pxa/zylonite_pxa320.c
3 *
4 * PXA320 specific support code for the
5 * PXA3xx Development Platform (aka Zylonite)
6 *
7 * Copyright (C) 2007 Marvell Internation Ltd.
8 * 2007-08-21: eric miao <eric.y.miao@gmail.com>
9 * initial version
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19
20#include <asm/arch/gpio.h>
21#include <asm/arch/mfp-pxa320.h>
22#include <asm/arch/zylonite.h>
23
24#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
25
26static mfp_cfg_t mfp_cfg[] __initdata = {
27 /* LCD */
28 GPIO6_2_LCD_LDD_0,
29 GPIO7_2_LCD_LDD_1,
30 GPIO8_2_LCD_LDD_2,
31 GPIO9_2_LCD_LDD_3,
32 GPIO10_2_LCD_LDD_4,
33 GPIO11_2_LCD_LDD_5,
34 GPIO12_2_LCD_LDD_6,
35 GPIO13_2_LCD_LDD_7,
36 GPIO63_LCD_LDD_8,
37 GPIO64_LCD_LDD_9,
38 GPIO65_LCD_LDD_10,
39 GPIO66_LCD_LDD_11,
40 GPIO67_LCD_LDD_12,
41 GPIO68_LCD_LDD_13,
42 GPIO69_LCD_LDD_14,
43 GPIO70_LCD_LDD_15,
44 GPIO71_LCD_LDD_16,
45 GPIO72_LCD_LDD_17,
46 GPIO73_LCD_CS_N,
47 GPIO74_LCD_VSYNC,
48 GPIO14_2_LCD_FCLK,
49 GPIO15_2_LCD_LCLK,
50 GPIO16_2_LCD_PCLK,
51 GPIO17_2_LCD_BIAS,
52
53 /* FFUART */
54 GPIO41_UART1_RXD,
55 GPIO42_UART1_TXD,
56 GPIO43_UART1_CTS,
57 GPIO44_UART1_DCD,
58 GPIO45_UART1_DSR,
59 GPIO46_UART1_RI,
60 GPIO47_UART1_DTR,
61 GPIO48_UART1_RTS,
62
63 /* AC97 */
64 GPIO34_AC97_SYSCLK,
65 GPIO35_AC97_SDATA_IN_0,
66 GPIO37_AC97_SDATA_OUT,
67 GPIO38_AC97_SYNC,
68 GPIO39_AC97_BITCLK,
69 GPIO40_AC97_nACRESET,
70
71 /* I2C */
72 GPIO32_I2C_SCL,
73 GPIO33_I2C_SDA,
74
75 /* Keypad */
76 GPIO105_KP_DKIN_0,
77 GPIO106_KP_DKIN_1,
78 GPIO113_KP_MKIN_0,
79 GPIO114_KP_MKIN_1,
80 GPIO115_KP_MKIN_2,
81 GPIO116_KP_MKIN_3,
82 GPIO117_KP_MKIN_4,
83 GPIO118_KP_MKIN_5,
84 GPIO119_KP_MKIN_6,
85 GPIO120_KP_MKIN_7,
86 GPIO121_KP_MKOUT_0,
87 GPIO122_KP_MKOUT_1,
88 GPIO123_KP_MKOUT_2,
89 GPIO124_KP_MKOUT_3,
90 GPIO125_KP_MKOUT_4,
91 GPIO126_KP_MKOUT_5,
92 GPIO127_KP_MKOUT_6,
93 GPIO5_2_KP_MKOUT_7,
94
95 /* Ethernet */
96 GPIO4_nCS3,
97 GPIO90_GPIO,
98};
99
100#define NUM_LCD_DETECT_PINS 7
101
102static int lcd_detect_pins[] __initdata = {
103 MFP_PIN_GPIO72, /* LCD_LDD_17 - ORIENT */
104 MFP_PIN_GPIO71, /* LCD_LDD_16 - LCDID[5] */
105 MFP_PIN_GPIO17_2, /* LCD_BIAS - LCDID[4] */
106 MFP_PIN_GPIO15_2, /* LCD_LCLK - LCDID[3] */
107 MFP_PIN_GPIO14_2, /* LCD_FCLK - LCDID[2] */
108 MFP_PIN_GPIO73, /* LCD_CS_N - LCDID[1] */
109 MFP_PIN_GPIO74, /* LCD_VSYNC - LCDID[0] */
110 /*
111 * set the MFP_PIN_GPIO 14/15/17 to alternate function other than
112 * GPIO to avoid input level confliction with 14_2, 15_2, 17_2
113 */
114 MFP_PIN_GPIO14,
115 MFP_PIN_GPIO15,
116 MFP_PIN_GPIO17,
117};
118
119static int lcd_detect_mfpr[] __initdata = {
120 /* AF0, DS 1X, Pull Neither, Edge Clear */
121 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, 0x8440, 0x8440,
122 0xc442, /* Backlight, Pull-Up, AF2 */
123 0x8445, /* AF5 */
124 0x8445, /* AF5 */
125};
126
127static void __init zylonite_detect_lcd_panel(void)
128{
129 unsigned long mfpr_save[ARRAY_SIZE(lcd_detect_pins)];
130 int i, gpio, id = 0;
131
132 /* save the original MFP settings of these pins and configure them
133 * as GPIO Input, DS01X, Pull Neither, Edge Clear
134 */
135 for (i = 0; i < ARRAY_SIZE(lcd_detect_pins); i++) {
136 mfpr_save[i] = pxa3xx_mfp_read(lcd_detect_pins[i]);
137 pxa3xx_mfp_write(lcd_detect_pins[i], lcd_detect_mfpr[i]);
138 }
139
140 for (i = 0; i < NUM_LCD_DETECT_PINS; i++) {
141 id = id << 1;
142 gpio = mfp_to_gpio(lcd_detect_pins[i]);
143 gpio_direction_input(gpio);
144
145 if (gpio_get_value(gpio))
146 id = id | 0x1;
147 }
148
149 /* lcd id, flush out bit 1 */
150 lcd_id = id & 0x3d;
151
152 /* lcd orientation, portrait or landscape */
153 lcd_orientation = (id >> 6) & 0x1;
154
155 /* restore the original MFP settings */
156 for (i = 0; i < ARRAY_SIZE(lcd_detect_pins); i++)
157 pxa3xx_mfp_write(lcd_detect_pins[i], mfpr_save[i]);
158}
159
160void __init zylonite_pxa320_init(void)
161{
162 if (cpu_is_pxa320()) {
163 /* initialize MFP */
164 pxa3xx_mfp_config(ARRAY_AND_SIZE(mfp_cfg));
165
166 /* detect LCD panel */
167 zylonite_detect_lcd_panel();
168
169 /* GPIO pin assignment */
170 gpio_backlight = mfp_to_gpio(MFP_PIN_GPIO14);
171 gpio_eth_irq = mfp_to_gpio(MFP_PIN_GPIO9);
172 }
173}
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 12161ae445da..7868f4dc1d00 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -322,7 +322,7 @@ config CPU_SA1100
322# XScale 322# XScale
323config CPU_XSCALE 323config CPU_XSCALE
324 bool 324 bool
325 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000 325 depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000
326 default y 326 default y
327 select CPU_32v5 327 select CPU_32v5
328 select CPU_ABRT_EV5T 328 select CPU_ABRT_EV5T
@@ -333,7 +333,7 @@ config CPU_XSCALE
333# XScale Core Version 3 333# XScale Core Version 3
334config CPU_XSC3 334config CPU_XSC3
335 bool 335 bool
336 depends on ARCH_IXP23XX || ARCH_IOP13XX 336 depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx
337 default y 337 default y
338 select CPU_32v5 338 select CPU_32v5
339 select CPU_ABRT_EV5T 339 select CPU_ABRT_EV5T
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index bb5466b27b59..00fad11733ad 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -31,6 +31,8 @@
31#include <linux/interrupt.h> 31#include <linux/interrupt.h>
32#include <linux/i2c-pxa.h> 32#include <linux/i2c-pxa.h>
33#include <linux/platform_device.h> 33#include <linux/platform_device.h>
34#include <linux/err.h>
35#include <linux/clk.h>
34 36
35#include <asm/hardware.h> 37#include <asm/hardware.h>
36#include <asm/irq.h> 38#include <asm/irq.h>
@@ -48,6 +50,7 @@ struct pxa_i2c {
48 unsigned int slave_addr; 50 unsigned int slave_addr;
49 51
50 struct i2c_adapter adap; 52 struct i2c_adapter adap;
53 struct clk *clk;
51#ifdef CONFIG_I2C_PXA_SLAVE 54#ifdef CONFIG_I2C_PXA_SLAVE
52 struct i2c_slave_client *slave; 55 struct i2c_slave_client *slave;
53#endif 56#endif
@@ -869,6 +872,12 @@ static int i2c_pxa_probe(struct platform_device *dev)
869 872
870 sprintf(i2c->adap.name, "pxa_i2c-i2c.%u", dev->id); 873 sprintf(i2c->adap.name, "pxa_i2c-i2c.%u", dev->id);
871 874
875 i2c->clk = clk_get(&dev->dev, "I2CCLK");
876 if (IS_ERR(i2c->clk)) {
877 ret = PTR_ERR(i2c->clk);
878 goto eclk;
879 }
880
872 i2c->reg_base = ioremap(res->start, res_len(res)); 881 i2c->reg_base = ioremap(res->start, res_len(res));
873 if (!i2c->reg_base) { 882 if (!i2c->reg_base) {
874 ret = -EIO; 883 ret = -EIO;
@@ -889,22 +898,19 @@ static int i2c_pxa_probe(struct platform_device *dev)
889 } 898 }
890#endif 899#endif
891 900
901 clk_enable(i2c->clk);
902#ifdef CONFIG_PXA27x
892 switch (dev->id) { 903 switch (dev->id) {
893 case 0: 904 case 0:
894#ifdef CONFIG_PXA27x
895 pxa_gpio_mode(GPIO117_I2CSCL_MD); 905 pxa_gpio_mode(GPIO117_I2CSCL_MD);
896 pxa_gpio_mode(GPIO118_I2CSDA_MD); 906 pxa_gpio_mode(GPIO118_I2CSDA_MD);
897#endif
898 pxa_set_cken(CKEN_I2C, 1);
899 break; 907 break;
900#ifdef CONFIG_PXA27x
901 case 1: 908 case 1:
902 local_irq_disable(); 909 local_irq_disable();
903 PCFR |= PCFR_PI2CEN; 910 PCFR |= PCFR_PI2CEN;
904 local_irq_enable(); 911 local_irq_enable();
905 pxa_set_cken(CKEN_PWRI2C, 1);
906#endif
907 } 912 }
913#endif
908 914
909 ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED, 915 ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
910 i2c->adap.name, i2c); 916 i2c->adap.name, i2c);
@@ -948,19 +954,18 @@ static int i2c_pxa_probe(struct platform_device *dev)
948eadapt: 954eadapt:
949 free_irq(irq, i2c); 955 free_irq(irq, i2c);
950ereqirq: 956ereqirq:
951 switch (dev->id) { 957 clk_disable(i2c->clk);
952 case 0: 958
953 pxa_set_cken(CKEN_I2C, 0);
954 break;
955#ifdef CONFIG_PXA27x 959#ifdef CONFIG_PXA27x
956 case 1: 960 if (dev->id == 1) {
957 pxa_set_cken(CKEN_PWRI2C, 0);
958 local_irq_disable(); 961 local_irq_disable();
959 PCFR &= ~PCFR_PI2CEN; 962 PCFR &= ~PCFR_PI2CEN;
960 local_irq_enable(); 963 local_irq_enable();
961#endif
962 } 964 }
965#endif
963eremap: 966eremap:
967 clk_put(i2c->clk);
968eclk:
964 kfree(i2c); 969 kfree(i2c);
965emalloc: 970emalloc:
966 release_mem_region(res->start, res_len(res)); 971 release_mem_region(res->start, res_len(res));
@@ -975,18 +980,18 @@ static int i2c_pxa_remove(struct platform_device *dev)
975 980
976 i2c_del_adapter(&i2c->adap); 981 i2c_del_adapter(&i2c->adap);
977 free_irq(i2c->irq, i2c); 982 free_irq(i2c->irq, i2c);
978 switch (dev->id) { 983
979 case 0: 984 clk_disable(i2c->clk);
980 pxa_set_cken(CKEN_I2C, 0); 985 clk_put(i2c->clk);
981 break; 986
982#ifdef CONFIG_PXA27x 987#ifdef CONFIG_PXA27x
983 case 1: 988 if (dev->id == 1) {
984 pxa_set_cken(CKEN_PWRI2C, 0);
985 local_irq_disable(); 989 local_irq_disable();
986 PCFR &= ~PCFR_PI2CEN; 990 PCFR &= ~PCFR_PI2CEN;
987 local_irq_enable(); 991 local_irq_enable();
988#endif
989 } 992 }
993#endif
994
990 release_mem_region(i2c->iobase, i2c->iosize); 995 release_mem_region(i2c->iobase, i2c->iosize);
991 kfree(i2c); 996 kfree(i2c);
992 997
diff --git a/drivers/input/keyboard/pxa27x_keyboard.c b/drivers/input/keyboard/pxa27x_keyboard.c
index ebe5eacf2990..b7061aa38816 100644
--- a/drivers/input/keyboard/pxa27x_keyboard.c
+++ b/drivers/input/keyboard/pxa27x_keyboard.c
@@ -23,6 +23,8 @@
23#include <linux/input.h> 23#include <linux/input.h>
24#include <linux/device.h> 24#include <linux/device.h>
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/clk.h>
27#include <linux/err.h>
26 28
27#include <asm/mach-types.h> 29#include <asm/mach-types.h>
28#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
@@ -40,6 +42,8 @@
40 col/2 == 2 ? KPASMKP2 : KPASMKP3) 42 col/2 == 2 ? KPASMKP2 : KPASMKP3)
41#define KPASMKPx_MKC(row, col) (1 << (row + 16 * (col % 2))) 43#define KPASMKPx_MKC(row, col) (1 << (row + 16 * (col % 2)))
42 44
45static struct clk *pxakbd_clk;
46
43static irqreturn_t pxakbd_irq_handler(int irq, void *dev_id) 47static irqreturn_t pxakbd_irq_handler(int irq, void *dev_id)
44{ 48{
45 struct platform_device *pdev = dev_id; 49 struct platform_device *pdev = dev_id;
@@ -104,7 +108,7 @@ static int pxakbd_open(struct input_dev *dev)
104 KPREC = 0x7F; 108 KPREC = 0x7F;
105 109
106 /* Enable unit clock */ 110 /* Enable unit clock */
107 pxa_set_cken(CKEN_KEYPAD, 1); 111 clk_enable(pxakbd_clk);
108 112
109 return 0; 113 return 0;
110} 114}
@@ -112,7 +116,7 @@ static int pxakbd_open(struct input_dev *dev)
112static void pxakbd_close(struct input_dev *dev) 116static void pxakbd_close(struct input_dev *dev)
113{ 117{
114 /* Disable clock unit */ 118 /* Disable clock unit */
115 pxa_set_cken(CKEN_KEYPAD, 0); 119 clk_disable(pxakbd_clk);
116} 120}
117 121
118#ifdef CONFIG_PM 122#ifdef CONFIG_PM
@@ -140,7 +144,8 @@ static int pxakbd_resume(struct platform_device *pdev)
140 KPREC = pdata->reg_kprec; 144 KPREC = pdata->reg_kprec;
141 145
142 /* Enable unit clock */ 146 /* Enable unit clock */
143 pxa_set_cken(CKEN_KEYPAD, 1); 147 clk_disable(pxakbd_clk);
148 clk_enable(pxakbd_clk);
144 } 149 }
145 150
146 mutex_unlock(&input_dev->mutex); 151 mutex_unlock(&input_dev->mutex);
@@ -158,11 +163,18 @@ static int __devinit pxakbd_probe(struct platform_device *pdev)
158 struct input_dev *input_dev; 163 struct input_dev *input_dev;
159 int i, row, col, error; 164 int i, row, col, error;
160 165
166 pxakbd_clk = clk_get(&pdev->dev, "KBDCLK");
167 if (IS_ERR(pxakbd_clk)) {
168 error = PTR_ERR(pxakbd_clk);
169 goto err_clk;
170 }
171
161 /* Create and register the input driver. */ 172 /* Create and register the input driver. */
162 input_dev = input_allocate_device(); 173 input_dev = input_allocate_device();
163 if (!input_dev) { 174 if (!input_dev) {
164 printk(KERN_ERR "Cannot request keypad device\n"); 175 printk(KERN_ERR "Cannot request keypad device\n");
165 return -ENOMEM; 176 error = -ENOMEM;
177 goto err_alloc;
166 } 178 }
167 179
168 input_dev->name = DRIVER_NAME; 180 input_dev->name = DRIVER_NAME;
@@ -185,7 +197,6 @@ static int __devinit pxakbd_probe(struct platform_device *pdev)
185 DRIVER_NAME, pdev); 197 DRIVER_NAME, pdev);
186 if (error) { 198 if (error) {
187 printk(KERN_ERR "Cannot request keypad IRQ\n"); 199 printk(KERN_ERR "Cannot request keypad IRQ\n");
188 pxa_set_cken(CKEN_KEYPAD, 0);
189 goto err_free_dev; 200 goto err_free_dev;
190 } 201 }
191 202
@@ -217,6 +228,9 @@ static int __devinit pxakbd_probe(struct platform_device *pdev)
217 free_irq(IRQ_KEYPAD, pdev); 228 free_irq(IRQ_KEYPAD, pdev);
218 err_free_dev: 229 err_free_dev:
219 input_free_device(input_dev); 230 input_free_device(input_dev);
231 err_alloc:
232 clk_put(pxakbd_clk);
233 err_clk:
220 return error; 234 return error;
221} 235}
222 236
@@ -226,6 +240,7 @@ static int __devexit pxakbd_remove(struct platform_device *pdev)
226 240
227 input_unregister_device(input_dev); 241 input_unregister_device(input_dev);
228 free_irq(IRQ_KEYPAD, pdev); 242 free_irq(IRQ_KEYPAD, pdev);
243 clk_put(pxakbd_clk);
229 platform_set_drvdata(pdev, NULL); 244 platform_set_drvdata(pdev, NULL);
230 245
231 return 0; 246 return 0;
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 3cb23210b912..257b44094e4c 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -108,6 +108,12 @@ config LEDS_GPIO
108 outputs. To be useful the particular board must have LEDs 108 outputs. To be useful the particular board must have LEDs
109 and they must be connected to the GPIO lines. 109 and they must be connected to the GPIO lines.
110 110
111config LEDS_CM_X270
112 tristate "LED Support for the CM-X270 LEDs"
113 depends on LEDS_CLASS && MACH_ARMCORE
114 help
115 This option enables support for the CM-X270 LEDs.
116
111comment "LED Triggers" 117comment "LED Triggers"
112 118
113config LEDS_TRIGGERS 119config LEDS_TRIGGERS
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index d2ca1abbc3d2..a60de1b46c2c 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_LEDS_H1940) += leds-h1940.o
18obj-$(CONFIG_LEDS_COBALT_QUBE) += leds-cobalt-qube.o 18obj-$(CONFIG_LEDS_COBALT_QUBE) += leds-cobalt-qube.o
19obj-$(CONFIG_LEDS_COBALT_RAQ) += leds-cobalt-raq.o 19obj-$(CONFIG_LEDS_COBALT_RAQ) += leds-cobalt-raq.o
20obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o 20obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o
21obj-$(CONFIG_LEDS_CM_X270) += leds-cm-x270.o
21 22
22# LED Triggers 23# LED Triggers
23obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o 24obj-$(CONFIG_LEDS_TRIGGER_TIMER) += ledtrig-timer.o
diff --git a/drivers/leds/leds-cm-x270.c b/drivers/leds/leds-cm-x270.c
new file mode 100644
index 000000000000..9aebef02a974
--- /dev/null
+++ b/drivers/leds/leds-cm-x270.c
@@ -0,0 +1,122 @@
1/*
2 * drivers/leds/leds-cm-x270.c
3 *
4 * Copyright 2007 CompuLab Ltd.
5 * Author: Mike Rapoport <mike@compulab.co.il>
6 *
7 * Based on leds-corgi.c
8 * Author: Richard Purdie <rpurdie@openedhand.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/leds.h>
20
21#include <asm/arch/hardware.h>
22#include <asm/arch/pxa-regs.h>
23
24#define GPIO_RED_LED (93)
25#define GPIO_GREEN_LED (94)
26
27static void cmx270_red_set(struct led_classdev *led_cdev,
28 enum led_brightness value)
29{
30 if (value)
31 GPCR(GPIO_RED_LED) = GPIO_bit(GPIO_RED_LED);
32 else
33 GPSR(GPIO_RED_LED) = GPIO_bit(GPIO_RED_LED);
34}
35
36static void cmx270_green_set(struct led_classdev *led_cdev,
37 enum led_brightness value)
38{
39 if (value)
40 GPCR(GPIO_GREEN_LED) = GPIO_bit(GPIO_GREEN_LED);
41 else
42 GPSR(GPIO_GREEN_LED) = GPIO_bit(GPIO_GREEN_LED);
43}
44
45static struct led_classdev cmx270_red_led = {
46 .name = "cm-x270:red",
47 .default_trigger = "nand-disk",
48 .brightness_set = cmx270_red_set,
49};
50
51static struct led_classdev cmx270_green_led = {
52 .name = "cm-x270:green",
53 .default_trigger = "heartbeat",
54 .brightness_set = cmx270_green_set,
55};
56
57#ifdef CONFIG_PM
58static int cmx270led_suspend(struct platform_device *dev, pm_message_t state)
59{
60 led_classdev_suspend(&cmx270_red_led);
61 led_classdev_suspend(&cmx270_green_led);
62 return 0;
63}
64
65static int cmx270led_resume(struct platform_device *dev)
66{
67 led_classdev_resume(&cmx270_red_led);
68 led_classdev_resume(&cmx270_green_led);
69 return 0;
70}
71#endif
72
73static int cmx270led_probe(struct platform_device *pdev)
74{
75 int ret;
76
77 ret = led_classdev_register(&pdev->dev, &cmx270_red_led);
78 if (ret < 0)
79 return ret;
80
81 ret = led_classdev_register(&pdev->dev, &cmx270_green_led);
82 if (ret < 0)
83 led_classdev_unregister(&cmx270_red_led);
84
85 return ret;
86}
87
88static int cmx270led_remove(struct platform_device *pdev)
89{
90 led_classdev_unregister(&cmx270_red_led);
91 led_classdev_unregister(&cmx270_green_led);
92 return 0;
93}
94
95static struct platform_driver cmx270led_driver = {
96 .probe = cmx270led_probe,
97 .remove = cmx270led_remove,
98#ifdef CONFIG_PM
99 .suspend = cmx270led_suspend,
100 .resume = cmx270led_resume,
101#endif
102 .driver = {
103 .name = "cm-x270-led",
104 },
105};
106
107static int __init cmx270led_init(void)
108{
109 return platform_driver_register(&cmx270led_driver);
110}
111
112static void __exit cmx270led_exit(void)
113{
114 platform_driver_unregister(&cmx270led_driver);
115}
116
117module_init(cmx270led_init);
118module_exit(cmx270led_exit);
119
120MODULE_AUTHOR("Mike Rapoport <mike@compulab.co.il>");
121MODULE_DESCRIPTION("CM-x270 LED driver");
122MODULE_LICENSE("GPL");
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index 657901eecfce..0601e01aa2c2 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -23,6 +23,8 @@
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/dma-mapping.h> 25#include <linux/dma-mapping.h>
26#include <linux/clk.h>
27#include <linux/err.h>
26#include <linux/mmc/host.h> 28#include <linux/mmc/host.h>
27 29
28#include <asm/dma.h> 30#include <asm/dma.h>
@@ -44,6 +46,8 @@ struct pxamci_host {
44 spinlock_t lock; 46 spinlock_t lock;
45 struct resource *res; 47 struct resource *res;
46 void __iomem *base; 48 void __iomem *base;
49 struct clk *clk;
50 unsigned long clkrate;
47 int irq; 51 int irq;
48 int dma; 52 int dma;
49 unsigned int clkrt; 53 unsigned int clkrt;
@@ -119,7 +123,7 @@ static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
119 writel(nob, host->base + MMC_NOB); 123 writel(nob, host->base + MMC_NOB);
120 writel(data->blksz, host->base + MMC_BLKLEN); 124 writel(data->blksz, host->base + MMC_BLKLEN);
121 125
122 clks = (unsigned long long)data->timeout_ns * CLOCKRATE; 126 clks = (unsigned long long)data->timeout_ns * host->clkrate;
123 do_div(clks, 1000000000UL); 127 do_div(clks, 1000000000UL);
124 timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt); 128 timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt);
125 writel((timeout + 255) / 256, host->base + MMC_RDTO); 129 writel((timeout + 255) / 256, host->base + MMC_RDTO);
@@ -365,18 +369,25 @@ static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
365 struct pxamci_host *host = mmc_priv(mmc); 369 struct pxamci_host *host = mmc_priv(mmc);
366 370
367 if (ios->clock) { 371 if (ios->clock) {
368 unsigned int clk = CLOCKRATE / ios->clock; 372 unsigned long rate = host->clkrate;
369 if (CLOCKRATE / clk > ios->clock) 373 unsigned int clk = rate / ios->clock;
374
375 /*
376 * clk might result in a lower divisor than we
377 * desire. check for that condition and adjust
378 * as appropriate.
379 */
380 if (rate / clk > ios->clock)
370 clk <<= 1; 381 clk <<= 1;
371 host->clkrt = fls(clk) - 1; 382 host->clkrt = fls(clk) - 1;
372 pxa_set_cken(CKEN_MMC, 1); 383 clk_enable(host->clk);
373 384
374 /* 385 /*
375 * we write clkrt on the next command 386 * we write clkrt on the next command
376 */ 387 */
377 } else { 388 } else {
378 pxamci_stop_clock(host); 389 pxamci_stop_clock(host);
379 pxa_set_cken(CKEN_MMC, 0); 390 clk_disable(host->clk);
380 } 391 }
381 392
382 if (host->power_mode != ios->power_mode) { 393 if (host->power_mode != ios->power_mode) {
@@ -462,8 +473,6 @@ static int pxamci_probe(struct platform_device *pdev)
462 } 473 }
463 474
464 mmc->ops = &pxamci_ops; 475 mmc->ops = &pxamci_ops;
465 mmc->f_min = CLOCKRATE_MIN;
466 mmc->f_max = CLOCKRATE_MAX;
467 476
468 /* 477 /*
469 * We can do SG-DMA, but we don't because we never know how much 478 * We can do SG-DMA, but we don't because we never know how much
@@ -490,6 +499,22 @@ static int pxamci_probe(struct platform_device *pdev)
490 host->mmc = mmc; 499 host->mmc = mmc;
491 host->dma = -1; 500 host->dma = -1;
492 host->pdata = pdev->dev.platform_data; 501 host->pdata = pdev->dev.platform_data;
502
503 host->clk = clk_get(&pdev->dev, "MMCCLK");
504 if (IS_ERR(host->clk)) {
505 ret = PTR_ERR(host->clk);
506 host->clk = NULL;
507 goto out;
508 }
509
510 host->clkrate = clk_get_rate(host->clk);
511
512 /*
513 * Calculate minimum clock rate, rounding up.
514 */
515 mmc->f_min = (host->clkrate + 63) / 64;
516 mmc->f_max = host->clkrate;
517
493 mmc->ocr_avail = host->pdata ? 518 mmc->ocr_avail = host->pdata ?
494 host->pdata->ocr_mask : 519 host->pdata->ocr_mask :
495 MMC_VDD_32_33|MMC_VDD_33_34; 520 MMC_VDD_32_33|MMC_VDD_33_34;
@@ -554,6 +579,8 @@ static int pxamci_probe(struct platform_device *pdev)
554 iounmap(host->base); 579 iounmap(host->base);
555 if (host->sg_cpu) 580 if (host->sg_cpu)
556 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 581 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
582 if (host->clk)
583 clk_put(host->clk);
557 } 584 }
558 if (mmc) 585 if (mmc)
559 mmc_free_host(mmc); 586 mmc_free_host(mmc);
@@ -588,6 +615,8 @@ static int pxamci_remove(struct platform_device *pdev)
588 iounmap(host->base); 615 iounmap(host->base);
589 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 616 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
590 617
618 clk_put(host->clk);
619
591 release_resource(host->res); 620 release_resource(host->res);
592 621
593 mmc_free_host(mmc); 622 mmc_free_host(mmc);
diff --git a/drivers/mmc/host/pxamci.h b/drivers/mmc/host/pxamci.h
index 3153e779d46a..748c7706f237 100644
--- a/drivers/mmc/host/pxamci.h
+++ b/drivers/mmc/host/pxamci.h
@@ -88,17 +88,3 @@
88#define MMC_RXFIFO 0x0040 /* 8 bit */ 88#define MMC_RXFIFO 0x0040 /* 8 bit */
89 89
90#define MMC_TXFIFO 0x0044 /* 8 bit */ 90#define MMC_TXFIFO 0x0044 /* 8 bit */
91
92/*
93 * The base MMC clock rate
94 */
95#ifdef CONFIG_PXA27x
96#define CLOCKRATE_MIN 304688
97#define CLOCKRATE_MAX 19500000
98#else
99#define CLOCKRATE_MIN 312500
100#define CLOCKRATE_MAX 20000000
101#endif
102
103#define CLOCKRATE CLOCKRATE_MAX
104
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c
index 55ff0fbe525a..8c09344f58dc 100644
--- a/drivers/net/irda/pxaficp_ir.c
+++ b/drivers/net/irda/pxaficp_ir.c
@@ -23,6 +23,7 @@
23#include <linux/dma-mapping.h> 23#include <linux/dma-mapping.h>
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25#include <linux/pm.h> 25#include <linux/pm.h>
26#include <linux/clk.h>
26 27
27#include <net/irda/irda.h> 28#include <net/irda/irda.h>
28#include <net/irda/irmod.h> 29#include <net/irda/irmod.h>
@@ -87,8 +88,30 @@ struct pxa_irda {
87 88
88 struct device *dev; 89 struct device *dev;
89 struct pxaficp_platform_data *pdata; 90 struct pxaficp_platform_data *pdata;
91 struct clk *fir_clk;
92 struct clk *sir_clk;
93 struct clk *cur_clk;
90}; 94};
91 95
96static inline void pxa_irda_disable_clk(struct pxa_irda *si)
97{
98 if (si->cur_clk)
99 clk_disable(si->cur_clk);
100 si->cur_clk = NULL;
101}
102
103static inline void pxa_irda_enable_firclk(struct pxa_irda *si)
104{
105 si->cur_clk = si->fir_clk;
106 clk_enable(si->fir_clk);
107}
108
109static inline void pxa_irda_enable_sirclk(struct pxa_irda *si)
110{
111 si->cur_clk = si->sir_clk;
112 clk_enable(si->sir_clk);
113}
114
92 115
93#define IS_FIR(si) ((si)->speed >= 4000000) 116#define IS_FIR(si) ((si)->speed >= 4000000)
94#define IRDA_FRAME_SIZE_LIMIT 2047 117#define IRDA_FRAME_SIZE_LIMIT 2047
@@ -134,7 +157,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
134 DCSR(si->rxdma) &= ~DCSR_RUN; 157 DCSR(si->rxdma) &= ~DCSR_RUN;
135 /* disable FICP */ 158 /* disable FICP */
136 ICCR0 = 0; 159 ICCR0 = 0;
137 pxa_set_cken(CKEN_FICP, 0); 160 pxa_irda_disable_clk(si);
138 161
139 /* set board transceiver to SIR mode */ 162 /* set board transceiver to SIR mode */
140 si->pdata->transceiver_mode(si->dev, IR_SIRMODE); 163 si->pdata->transceiver_mode(si->dev, IR_SIRMODE);
@@ -144,7 +167,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
144 pxa_gpio_mode(GPIO47_STTXD_MD); 167 pxa_gpio_mode(GPIO47_STTXD_MD);
145 168
146 /* enable the STUART clock */ 169 /* enable the STUART clock */
147 pxa_set_cken(CKEN_STUART, 1); 170 pxa_irda_enable_sirclk(si);
148 } 171 }
149 172
150 /* disable STUART first */ 173 /* disable STUART first */
@@ -169,7 +192,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
169 /* disable STUART */ 192 /* disable STUART */
170 STIER = 0; 193 STIER = 0;
171 STISR = 0; 194 STISR = 0;
172 pxa_set_cken(CKEN_STUART, 0); 195 pxa_irda_disable_clk(si);
173 196
174 /* disable FICP first */ 197 /* disable FICP first */
175 ICCR0 = 0; 198 ICCR0 = 0;
@@ -182,7 +205,7 @@ static int pxa_irda_set_speed(struct pxa_irda *si, int speed)
182 pxa_gpio_mode(GPIO47_ICPTXD_MD); 205 pxa_gpio_mode(GPIO47_ICPTXD_MD);
183 206
184 /* enable the FICP clock */ 207 /* enable the FICP clock */
185 pxa_set_cken(CKEN_FICP, 1); 208 pxa_irda_enable_firclk(si);
186 209
187 si->speed = speed; 210 si->speed = speed;
188 pxa_irda_fir_dma_rx_start(si); 211 pxa_irda_fir_dma_rx_start(si);
@@ -592,16 +615,15 @@ static void pxa_irda_shutdown(struct pxa_irda *si)
592 STIER = 0; 615 STIER = 0;
593 /* disable STUART SIR mode */ 616 /* disable STUART SIR mode */
594 STISR = 0; 617 STISR = 0;
595 /* disable the STUART clock */
596 pxa_set_cken(CKEN_STUART, 0);
597 618
598 /* disable DMA */ 619 /* disable DMA */
599 DCSR(si->txdma) &= ~DCSR_RUN; 620 DCSR(si->txdma) &= ~DCSR_RUN;
600 DCSR(si->rxdma) &= ~DCSR_RUN; 621 DCSR(si->rxdma) &= ~DCSR_RUN;
601 /* disable FICP */ 622 /* disable FICP */
602 ICCR0 = 0; 623 ICCR0 = 0;
603 /* disable the FICP clock */ 624
604 pxa_set_cken(CKEN_FICP, 0); 625 /* disable the STUART or FICP clocks */
626 pxa_irda_disable_clk(si);
605 627
606 DRCMR17 = 0; 628 DRCMR17 = 0;
607 DRCMR18 = 0; 629 DRCMR18 = 0;
@@ -792,6 +814,13 @@ static int pxa_irda_probe(struct platform_device *pdev)
792 si->dev = &pdev->dev; 814 si->dev = &pdev->dev;
793 si->pdata = pdev->dev.platform_data; 815 si->pdata = pdev->dev.platform_data;
794 816
817 si->sir_clk = clk_get(&pdev->dev, "UARTCLK");
818 si->fir_clk = clk_get(&pdev->dev, "FICPCLK");
819 if (IS_ERR(si->sir_clk) || IS_ERR(si->fir_clk)) {
820 err = PTR_ERR(IS_ERR(si->sir_clk) ? si->sir_clk : si->fir_clk);
821 goto err_mem_4;
822 }
823
795 /* 824 /*
796 * Initialise the SIR buffers 825 * Initialise the SIR buffers
797 */ 826 */
@@ -831,6 +860,10 @@ static int pxa_irda_probe(struct platform_device *pdev)
831err_mem_5: 860err_mem_5:
832 kfree(si->rx_buff.head); 861 kfree(si->rx_buff.head);
833err_mem_4: 862err_mem_4:
863 if (si->sir_clk && !IS_ERR(si->sir_clk))
864 clk_put(si->sir_clk);
865 if (si->fir_clk && !IS_ERR(si->fir_clk))
866 clk_put(si->fir_clk);
834 free_netdev(dev); 867 free_netdev(dev);
835err_mem_3: 868err_mem_3:
836 release_mem_region(__PREG(FICP), 0x1c); 869 release_mem_region(__PREG(FICP), 0x1c);
@@ -850,6 +883,8 @@ static int pxa_irda_remove(struct platform_device *_dev)
850 unregister_netdev(dev); 883 unregister_netdev(dev);
851 kfree(si->tx_buff.head); 884 kfree(si->tx_buff.head);
852 kfree(si->rx_buff.head); 885 kfree(si->rx_buff.head);
886 clk_put(si->fir_clk);
887 clk_put(si->sir_clk);
853 free_netdev(dev); 888 free_netdev(dev);
854 } 889 }
855 890
diff --git a/drivers/net/smc91x.c b/drivers/net/smc91x.c
index 24e610e711e8..7da7589d45dd 100644
--- a/drivers/net/smc91x.c
+++ b/drivers/net/smc91x.c
@@ -173,49 +173,6 @@ MODULE_LICENSE("GPL");
173 */ 173 */
174#define MII_DELAY 1 174#define MII_DELAY 1
175 175
176/* store this information for the driver.. */
177struct smc_local {
178 /*
179 * If I have to wait until memory is available to send a
180 * packet, I will store the skbuff here, until I get the
181 * desired memory. Then, I'll send it out and free it.
182 */
183 struct sk_buff *pending_tx_skb;
184 struct tasklet_struct tx_task;
185
186 /* version/revision of the SMC91x chip */
187 int version;
188
189 /* Contains the current active transmission mode */
190 int tcr_cur_mode;
191
192 /* Contains the current active receive mode */
193 int rcr_cur_mode;
194
195 /* Contains the current active receive/phy mode */
196 int rpc_cur_mode;
197 int ctl_rfduplx;
198 int ctl_rspeed;
199
200 u32 msg_enable;
201 u32 phy_type;
202 struct mii_if_info mii;
203
204 /* work queue */
205 struct work_struct phy_configure;
206 struct net_device *dev;
207 int work_pending;
208
209 spinlock_t lock;
210
211#ifdef SMC_USE_PXA_DMA
212 /* DMA needs the physical address of the chip */
213 u_long physaddr;
214#endif
215 void __iomem *base;
216 void __iomem *datacs;
217};
218
219#if SMC_DEBUG > 0 176#if SMC_DEBUG > 0
220#define DBG(n, args...) \ 177#define DBG(n, args...) \
221 do { \ 178 do { \
@@ -2215,17 +2172,19 @@ static int smc_drv_probe(struct platform_device *pdev)
2215 goto out_release_attrib; 2172 goto out_release_attrib;
2216 } 2173 }
2217 2174
2218 platform_set_drvdata(pdev, ndev);
2219 ret = smc_probe(ndev, addr);
2220 if (ret != 0)
2221 goto out_iounmap;
2222#ifdef SMC_USE_PXA_DMA 2175#ifdef SMC_USE_PXA_DMA
2223 else { 2176 {
2224 struct smc_local *lp = netdev_priv(ndev); 2177 struct smc_local *lp = netdev_priv(ndev);
2178 lp->device = &pdev->dev;
2225 lp->physaddr = res->start; 2179 lp->physaddr = res->start;
2226 } 2180 }
2227#endif 2181#endif
2228 2182
2183 platform_set_drvdata(pdev, ndev);
2184 ret = smc_probe(ndev, addr);
2185 if (ret != 0)
2186 goto out_iounmap;
2187
2229 smc_request_datacs(pdev, ndev); 2188 smc_request_datacs(pdev, ndev);
2230 2189
2231 return 0; 2190 return 0;
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index af9e6bf59552..729fd28c08b5 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -462,6 +462,52 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
462 462
463#endif 463#endif
464 464
465
466/* store this information for the driver.. */
467struct smc_local {
468 /*
469 * If I have to wait until memory is available to send a
470 * packet, I will store the skbuff here, until I get the
471 * desired memory. Then, I'll send it out and free it.
472 */
473 struct sk_buff *pending_tx_skb;
474 struct tasklet_struct tx_task;
475
476 /* version/revision of the SMC91x chip */
477 int version;
478
479 /* Contains the current active transmission mode */
480 int tcr_cur_mode;
481
482 /* Contains the current active receive mode */
483 int rcr_cur_mode;
484
485 /* Contains the current active receive/phy mode */
486 int rpc_cur_mode;
487 int ctl_rfduplx;
488 int ctl_rspeed;
489
490 u32 msg_enable;
491 u32 phy_type;
492 struct mii_if_info mii;
493
494 /* work queue */
495 struct work_struct phy_configure;
496 struct net_device *dev;
497 int work_pending;
498
499 spinlock_t lock;
500
501#ifdef SMC_USE_PXA_DMA
502 /* DMA needs the physical address of the chip */
503 u_long physaddr;
504 struct device *device;
505#endif
506 void __iomem *base;
507 void __iomem *datacs;
508};
509
510
465#ifdef SMC_USE_PXA_DMA 511#ifdef SMC_USE_PXA_DMA
466/* 512/*
467 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is 513 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
@@ -476,11 +522,12 @@ static inline void LPD7_SMC_outsw (unsigned char* a, int r,
476#ifdef SMC_insl 522#ifdef SMC_insl
477#undef SMC_insl 523#undef SMC_insl
478#define SMC_insl(a, r, p, l) \ 524#define SMC_insl(a, r, p, l) \
479 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l) 525 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
480static inline void 526static inline void
481smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma, 527smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
482 u_char *buf, int len) 528 u_char *buf, int len)
483{ 529{
530 u_long physaddr = lp->physaddr;
484 dma_addr_t dmabuf; 531 dma_addr_t dmabuf;
485 532
486 /* fallback if no DMA available */ 533 /* fallback if no DMA available */
@@ -497,7 +544,7 @@ smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
497 } 544 }
498 545
499 len *= 4; 546 len *= 4;
500 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); 547 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
501 DCSR(dma) = DCSR_NODESC; 548 DCSR(dma) = DCSR_NODESC;
502 DTADR(dma) = dmabuf; 549 DTADR(dma) = dmabuf;
503 DSADR(dma) = physaddr + reg; 550 DSADR(dma) = physaddr + reg;
@@ -507,18 +554,19 @@ smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
507 while (!(DCSR(dma) & DCSR_STOPSTATE)) 554 while (!(DCSR(dma) & DCSR_STOPSTATE))
508 cpu_relax(); 555 cpu_relax();
509 DCSR(dma) = 0; 556 DCSR(dma) = 0;
510 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); 557 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
511} 558}
512#endif 559#endif
513 560
514#ifdef SMC_insw 561#ifdef SMC_insw
515#undef SMC_insw 562#undef SMC_insw
516#define SMC_insw(a, r, p, l) \ 563#define SMC_insw(a, r, p, l) \
517 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l) 564 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
518static inline void 565static inline void
519smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma, 566smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
520 u_char *buf, int len) 567 u_char *buf, int len)
521{ 568{
569 u_long physaddr = lp->physaddr;
522 dma_addr_t dmabuf; 570 dma_addr_t dmabuf;
523 571
524 /* fallback if no DMA available */ 572 /* fallback if no DMA available */
@@ -535,7 +583,7 @@ smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
535 } 583 }
536 584
537 len *= 2; 585 len *= 2;
538 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE); 586 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
539 DCSR(dma) = DCSR_NODESC; 587 DCSR(dma) = DCSR_NODESC;
540 DTADR(dma) = dmabuf; 588 DTADR(dma) = dmabuf;
541 DSADR(dma) = physaddr + reg; 589 DSADR(dma) = physaddr + reg;
@@ -545,7 +593,7 @@ smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
545 while (!(DCSR(dma) & DCSR_STOPSTATE)) 593 while (!(DCSR(dma) & DCSR_STOPSTATE))
546 cpu_relax(); 594 cpu_relax();
547 DCSR(dma) = 0; 595 DCSR(dma) = 0;
548 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE); 596 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
549} 597}
550#endif 598#endif
551 599
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index 4276965517f2..dc7a4cb5d270 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -69,4 +69,5 @@ sa1100_cs-$(CONFIG_SA1100_SIMPAD) += sa1100_simpad.o
69pxa2xx_cs-$(CONFIG_ARCH_LUBBOCK) += pxa2xx_lubbock.o sa1111_generic.o 69pxa2xx_cs-$(CONFIG_ARCH_LUBBOCK) += pxa2xx_lubbock.o sa1111_generic.o
70pxa2xx_cs-$(CONFIG_MACH_MAINSTONE) += pxa2xx_mainstone.o 70pxa2xx_cs-$(CONFIG_MACH_MAINSTONE) += pxa2xx_mainstone.o
71pxa2xx_cs-$(CONFIG_PXA_SHARPSL) += pxa2xx_sharpsl.o 71pxa2xx_cs-$(CONFIG_PXA_SHARPSL) += pxa2xx_sharpsl.o
72pxa2xx_cs-$(CONFIG_MACH_ARMCORE) += pxa2xx_cm_x270.o
72 73
diff --git a/drivers/pcmcia/pxa2xx_cm_x270.c b/drivers/pcmcia/pxa2xx_cm_x270.c
new file mode 100644
index 000000000000..fbf2f3a6984c
--- /dev/null
+++ b/drivers/pcmcia/pxa2xx_cm_x270.c
@@ -0,0 +1,175 @@
1/*
2 * linux/drivers/pcmcia/pxa/pxa_cm_x270.c
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Compulab Ltd., 2003, 2007
9 * Mike Rapoport <mike@compulab.co.il>
10 *
11 */
12
13#include <linux/kernel.h>
14#include <linux/sched.h>
15#include <linux/platform_device.h>
16#include <linux/irq.h>
17#include <linux/delay.h>
18
19#include <pcmcia/ss.h>
20#include <asm/hardware.h>
21
22#include <asm/arch/pxa-regs.h>
23#include <asm/arch/cm-x270.h>
24
25#include "soc_common.h"
26
27static struct pcmcia_irqs irqs[] = {
28 { 0, PCMCIA_S0_CD_VALID, "PCMCIA0 CD" },
29 { 1, PCMCIA_S1_CD_VALID, "PCMCIA1 CD" },
30};
31
32static int cmx270_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
33{
34 GPSR(GPIO48_nPOE) = GPIO_bit(GPIO48_nPOE) |
35 GPIO_bit(GPIO49_nPWE) |
36 GPIO_bit(GPIO50_nPIOR) |
37 GPIO_bit(GPIO51_nPIOW) |
38 GPIO_bit(GPIO85_nPCE_1) |
39 GPIO_bit(GPIO54_nPCE_2);
40
41 pxa_gpio_mode(GPIO48_nPOE_MD);
42 pxa_gpio_mode(GPIO49_nPWE_MD);
43 pxa_gpio_mode(GPIO50_nPIOR_MD);
44 pxa_gpio_mode(GPIO51_nPIOW_MD);
45 pxa_gpio_mode(GPIO85_nPCE_1_MD);
46 pxa_gpio_mode(GPIO54_nPCE_2_MD);
47 pxa_gpio_mode(GPIO55_nPREG_MD);
48 pxa_gpio_mode(GPIO56_nPWAIT_MD);
49 pxa_gpio_mode(GPIO57_nIOIS16_MD);
50
51 /* Reset signal */
52 pxa_gpio_mode(GPIO53_nPCE_2 | GPIO_OUT);
53 GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
54
55 set_irq_type(PCMCIA_S0_CD_VALID, IRQ_TYPE_EDGE_BOTH);
56 set_irq_type(PCMCIA_S1_CD_VALID, IRQ_TYPE_EDGE_BOTH);
57
58 /* irq's for slots: */
59 set_irq_type(PCMCIA_S0_RDYINT, IRQ_TYPE_EDGE_FALLING);
60 set_irq_type(PCMCIA_S1_RDYINT, IRQ_TYPE_EDGE_FALLING);
61
62 skt->irq = (skt->nr == 0) ? PCMCIA_S0_RDYINT : PCMCIA_S1_RDYINT;
63 return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
64}
65
66static void cmx270_pcmcia_shutdown(struct soc_pcmcia_socket *skt)
67{
68 soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs));
69
70 set_irq_type(IRQ_TO_GPIO(PCMCIA_S0_CD_VALID), IRQ_TYPE_NONE);
71 set_irq_type(IRQ_TO_GPIO(PCMCIA_S1_CD_VALID), IRQ_TYPE_NONE);
72
73 set_irq_type(IRQ_TO_GPIO(PCMCIA_S0_RDYINT), IRQ_TYPE_NONE);
74 set_irq_type(IRQ_TO_GPIO(PCMCIA_S1_RDYINT), IRQ_TYPE_NONE);
75}
76
77
78static void cmx270_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
79 struct pcmcia_state *state)
80{
81 state->detect = (PCC_DETECT(skt->nr) == 0) ? 1 : 0;
82 state->ready = (PCC_READY(skt->nr) == 0) ? 0 : 1;
83 state->bvd1 = 1;
84 state->bvd2 = 1;
85 state->vs_3v = 0;
86 state->vs_Xv = 0;
87 state->wrprot = 0; /* not available */
88}
89
90
91static int cmx270_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
92 const socket_state_t *state)
93{
94 GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
95 pxa_gpio_mode(GPIO49_nPWE | GPIO_OUT);
96
97 switch (skt->nr) {
98 case 0:
99 if (state->flags & SS_RESET) {
100 GPCR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
101 GPSR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
102 udelay(10);
103 GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
104 GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
105 }
106 break;
107 case 1:
108 if (state->flags & SS_RESET) {
109 GPCR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
110 GPSR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
111 udelay(10);
112 GPCR(GPIO53_nPCE_2) = GPIO_bit(GPIO53_nPCE_2);
113 GPSR(GPIO49_nPWE) = GPIO_bit(GPIO49_nPWE);
114 }
115 break;
116 }
117
118 pxa_gpio_mode(GPIO49_nPWE_MD);
119
120 return 0;
121}
122
123static void cmx270_pcmcia_socket_init(struct soc_pcmcia_socket *skt)
124{
125}
126
127static void cmx270_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
128{
129}
130
131
132static struct pcmcia_low_level cmx270_pcmcia_ops = {
133 .owner = THIS_MODULE,
134 .hw_init = cmx270_pcmcia_hw_init,
135 .hw_shutdown = cmx270_pcmcia_shutdown,
136 .socket_state = cmx270_pcmcia_socket_state,
137 .configure_socket = cmx270_pcmcia_configure_socket,
138 .socket_init = cmx270_pcmcia_socket_init,
139 .socket_suspend = cmx270_pcmcia_socket_suspend,
140 .nr = 2,
141};
142
143static struct platform_device *cmx270_pcmcia_device;
144
145static int __init cmx270_pcmcia_init(void)
146{
147 int ret;
148
149 cmx270_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
150
151 if (!cmx270_pcmcia_device)
152 return -ENOMEM;
153
154 cmx270_pcmcia_device->dev.platform_data = &cmx270_pcmcia_ops;
155
156 printk(KERN_INFO "Registering cm-x270 PCMCIA interface.\n");
157 ret = platform_device_add(cmx270_pcmcia_device);
158
159 if (ret)
160 platform_device_put(cmx270_pcmcia_device);
161
162 return ret;
163}
164
165static void __exit cmx270_pcmcia_exit(void)
166{
167 platform_device_unregister(cmx270_pcmcia_device);
168}
169
170module_init(cmx270_pcmcia_init);
171module_exit(cmx270_pcmcia_exit);
172
173MODULE_LICENSE("GPL");
174MODULE_AUTHOR("Mike Rapoport <mike@compulab.co.il>");
175MODULE_DESCRIPTION("CM-x270 PCMCIA driver");
diff --git a/drivers/pcmcia/pxa2xx_lubbock.c b/drivers/pcmcia/pxa2xx_lubbock.c
index 5e9b9a3fd027..1510d6cde3e2 100644
--- a/drivers/pcmcia/pxa2xx_lubbock.c
+++ b/drivers/pcmcia/pxa2xx_lubbock.c
@@ -30,35 +30,6 @@
30#include "sa1111_generic.h" 30#include "sa1111_generic.h"
31 31
32static int 32static int
33lubbock_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
34{
35 /*
36 * Setup default state of GPIO outputs
37 * before we enable them as outputs.
38 */
39 GPSR(GPIO48_nPOE) =
40 GPIO_bit(GPIO48_nPOE) |
41 GPIO_bit(GPIO49_nPWE) |
42 GPIO_bit(GPIO50_nPIOR) |
43 GPIO_bit(GPIO51_nPIOW) |
44 GPIO_bit(GPIO52_nPCE_1) |
45 GPIO_bit(GPIO53_nPCE_2);
46
47 pxa_gpio_mode(GPIO48_nPOE_MD);
48 pxa_gpio_mode(GPIO49_nPWE_MD);
49 pxa_gpio_mode(GPIO50_nPIOR_MD);
50 pxa_gpio_mode(GPIO51_nPIOW_MD);
51 pxa_gpio_mode(GPIO52_nPCE_1_MD);
52 pxa_gpio_mode(GPIO53_nPCE_2_MD);
53 pxa_gpio_mode(GPIO54_pSKTSEL_MD);
54 pxa_gpio_mode(GPIO55_nPREG_MD);
55 pxa_gpio_mode(GPIO56_nPWAIT_MD);
56 pxa_gpio_mode(GPIO57_nIOIS16_MD);
57
58 return sa1111_pcmcia_hw_init(skt);
59}
60
61static int
62lubbock_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, 33lubbock_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
63 const socket_state_t *state) 34 const socket_state_t *state)
64{ 35{
@@ -230,7 +201,7 @@ lubbock_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
230 201
231static struct pcmcia_low_level lubbock_pcmcia_ops = { 202static struct pcmcia_low_level lubbock_pcmcia_ops = {
232 .owner = THIS_MODULE, 203 .owner = THIS_MODULE,
233 .hw_init = lubbock_pcmcia_hw_init, 204 .hw_init = sa1111_pcmcia_hw_init,
234 .hw_shutdown = sa1111_pcmcia_hw_shutdown, 205 .hw_shutdown = sa1111_pcmcia_hw_shutdown,
235 .socket_state = sa1111_pcmcia_socket_state, 206 .socket_state = sa1111_pcmcia_socket_state,
236 .configure_socket = lubbock_pcmcia_configure_socket, 207 .configure_socket = lubbock_pcmcia_configure_socket,
diff --git a/drivers/pcmcia/pxa2xx_mainstone.c b/drivers/pcmcia/pxa2xx_mainstone.c
index 383107ba4bd3..36c671c5fb65 100644
--- a/drivers/pcmcia/pxa2xx_mainstone.c
+++ b/drivers/pcmcia/pxa2xx_mainstone.c
@@ -43,24 +43,6 @@ static int mst_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
43 * Setup default state of GPIO outputs 43 * Setup default state of GPIO outputs
44 * before we enable them as outputs. 44 * before we enable them as outputs.
45 */ 45 */
46 GPSR(GPIO48_nPOE) =
47 GPIO_bit(GPIO48_nPOE) |
48 GPIO_bit(GPIO49_nPWE) |
49 GPIO_bit(GPIO50_nPIOR) |
50 GPIO_bit(GPIO51_nPIOW) |
51 GPIO_bit(GPIO85_nPCE_1) |
52 GPIO_bit(GPIO54_nPCE_2);
53
54 pxa_gpio_mode(GPIO48_nPOE_MD);
55 pxa_gpio_mode(GPIO49_nPWE_MD);
56 pxa_gpio_mode(GPIO50_nPIOR_MD);
57 pxa_gpio_mode(GPIO51_nPIOW_MD);
58 pxa_gpio_mode(GPIO85_nPCE_1_MD);
59 pxa_gpio_mode(GPIO54_nPCE_2_MD);
60 pxa_gpio_mode(GPIO79_pSKTSEL_MD);
61 pxa_gpio_mode(GPIO55_nPREG_MD);
62 pxa_gpio_mode(GPIO56_nPWAIT_MD);
63 pxa_gpio_mode(GPIO57_nIOIS16_MD);
64 46
65 skt->irq = (skt->nr == 0) ? MAINSTONE_S0_IRQ : MAINSTONE_S1_IRQ; 47 skt->irq = (skt->nr == 0) ? MAINSTONE_S0_IRQ : MAINSTONE_S1_IRQ;
66 return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs)); 48 return soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c
index e9c6cb391a23..af3a011b2b24 100644
--- a/drivers/serial/pxa.c
+++ b/drivers/serial/pxa.c
@@ -42,6 +42,7 @@
42#include <linux/tty.h> 42#include <linux/tty.h>
43#include <linux/tty_flip.h> 43#include <linux/tty_flip.h>
44#include <linux/serial_core.h> 44#include <linux/serial_core.h>
45#include <linux/clk.h>
45 46
46#include <asm/io.h> 47#include <asm/io.h>
47#include <asm/hardware.h> 48#include <asm/hardware.h>
@@ -55,7 +56,7 @@ struct uart_pxa_port {
55 unsigned char lcr; 56 unsigned char lcr;
56 unsigned char mcr; 57 unsigned char mcr;
57 unsigned int lsr_break_flag; 58 unsigned int lsr_break_flag;
58 unsigned int cken; 59 struct clk *clk;
59 char *name; 60 char *name;
60}; 61};
61 62
@@ -351,6 +352,8 @@ static int serial_pxa_startup(struct uart_port *port)
351 else 352 else
352 up->mcr = 0; 353 up->mcr = 0;
353 354
355 up->port.uartclk = clk_get_rate(up->clk);
356
354 /* 357 /*
355 * Allocate the IRQ 358 * Allocate the IRQ
356 */ 359 */
@@ -546,9 +549,11 @@ serial_pxa_pm(struct uart_port *port, unsigned int state,
546 unsigned int oldstate) 549 unsigned int oldstate)
547{ 550{
548 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 551 struct uart_pxa_port *up = (struct uart_pxa_port *)port;
549 pxa_set_cken(up->cken, !state); 552
550 if (!state) 553 if (!state)
551 udelay(1); 554 clk_enable(up->clk);
555 else
556 clk_disable(up->clk);
552} 557}
553 558
554static void serial_pxa_release_port(struct uart_port *port) 559static void serial_pxa_release_port(struct uart_port *port)
@@ -582,7 +587,7 @@ serial_pxa_type(struct uart_port *port)
582 587
583#ifdef CONFIG_SERIAL_PXA_CONSOLE 588#ifdef CONFIG_SERIAL_PXA_CONSOLE
584 589
585static struct uart_pxa_port serial_pxa_ports[]; 590static struct uart_pxa_port *serial_pxa_ports[4];
586static struct uart_driver serial_pxa_reg; 591static struct uart_driver serial_pxa_reg;
587 592
588#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 593#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
@@ -632,9 +637,11 @@ static void serial_pxa_console_putchar(struct uart_port *port, int ch)
632static void 637static void
633serial_pxa_console_write(struct console *co, const char *s, unsigned int count) 638serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
634{ 639{
635 struct uart_pxa_port *up = &serial_pxa_ports[co->index]; 640 struct uart_pxa_port *up = serial_pxa_ports[co->index];
636 unsigned int ier; 641 unsigned int ier;
637 642
643 clk_enable(up->clk);
644
638 /* 645 /*
639 * First save the IER then disable the interrupts 646 * First save the IER then disable the interrupts
640 */ 647 */
@@ -649,6 +656,8 @@ serial_pxa_console_write(struct console *co, const char *s, unsigned int count)
649 */ 656 */
650 wait_for_xmitr(up); 657 wait_for_xmitr(up);
651 serial_out(up, UART_IER, ier); 658 serial_out(up, UART_IER, ier);
659
660 clk_disable(up->clk);
652} 661}
653 662
654static int __init 663static int __init
@@ -662,7 +671,9 @@ serial_pxa_console_setup(struct console *co, char *options)
662 671
663 if (co->index == -1 || co->index >= serial_pxa_reg.nr) 672 if (co->index == -1 || co->index >= serial_pxa_reg.nr)
664 co->index = 0; 673 co->index = 0;
665 up = &serial_pxa_ports[co->index]; 674 up = serial_pxa_ports[co->index];
675 if (!up)
676 return -ENODEV;
666 677
667 if (options) 678 if (options)
668 uart_parse_options(options, &baud, &parity, &bits, &flow); 679 uart_parse_options(options, &baud, &parity, &bits, &flow);
@@ -680,15 +691,6 @@ static struct console serial_pxa_console = {
680 .data = &serial_pxa_reg, 691 .data = &serial_pxa_reg,
681}; 692};
682 693
683static int __init
684serial_pxa_console_init(void)
685{
686 register_console(&serial_pxa_console);
687 return 0;
688}
689
690console_initcall(serial_pxa_console_init);
691
692#define PXA_CONSOLE &serial_pxa_console 694#define PXA_CONSOLE &serial_pxa_console
693#else 695#else
694#define PXA_CONSOLE NULL 696#define PXA_CONSOLE NULL
@@ -714,73 +716,13 @@ struct uart_ops serial_pxa_pops = {
714 .verify_port = serial_pxa_verify_port, 716 .verify_port = serial_pxa_verify_port,
715}; 717};
716 718
717static struct uart_pxa_port serial_pxa_ports[] = {
718 { /* FFUART */
719 .name = "FFUART",
720 .cken = CKEN_FFUART,
721 .port = {
722 .type = PORT_PXA,
723 .iotype = UPIO_MEM,
724 .membase = (void *)&FFUART,
725 .mapbase = __PREG(FFUART),
726 .irq = IRQ_FFUART,
727 .uartclk = 921600 * 16,
728 .fifosize = 64,
729 .ops = &serial_pxa_pops,
730 .line = 0,
731 },
732 }, { /* BTUART */
733 .name = "BTUART",
734 .cken = CKEN_BTUART,
735 .port = {
736 .type = PORT_PXA,
737 .iotype = UPIO_MEM,
738 .membase = (void *)&BTUART,
739 .mapbase = __PREG(BTUART),
740 .irq = IRQ_BTUART,
741 .uartclk = 921600 * 16,
742 .fifosize = 64,
743 .ops = &serial_pxa_pops,
744 .line = 1,
745 },
746 }, { /* STUART */
747 .name = "STUART",
748 .cken = CKEN_STUART,
749 .port = {
750 .type = PORT_PXA,
751 .iotype = UPIO_MEM,
752 .membase = (void *)&STUART,
753 .mapbase = __PREG(STUART),
754 .irq = IRQ_STUART,
755 .uartclk = 921600 * 16,
756 .fifosize = 64,
757 .ops = &serial_pxa_pops,
758 .line = 2,
759 },
760 }, { /* HWUART */
761 .name = "HWUART",
762 .cken = CKEN_HWUART,
763 .port = {
764 .type = PORT_PXA,
765 .iotype = UPIO_MEM,
766 .membase = (void *)&HWUART,
767 .mapbase = __PREG(HWUART),
768 .irq = IRQ_HWUART,
769 .uartclk = 921600 * 16,
770 .fifosize = 64,
771 .ops = &serial_pxa_pops,
772 .line = 3,
773 },
774 }
775};
776
777static struct uart_driver serial_pxa_reg = { 719static struct uart_driver serial_pxa_reg = {
778 .owner = THIS_MODULE, 720 .owner = THIS_MODULE,
779 .driver_name = "PXA serial", 721 .driver_name = "PXA serial",
780 .dev_name = "ttyS", 722 .dev_name = "ttyS",
781 .major = TTY_MAJOR, 723 .major = TTY_MAJOR,
782 .minor = 64, 724 .minor = 64,
783 .nr = ARRAY_SIZE(serial_pxa_ports), 725 .nr = 4,
784 .cons = PXA_CONSOLE, 726 .cons = PXA_CONSOLE,
785}; 727};
786 728
@@ -806,10 +748,68 @@ static int serial_pxa_resume(struct platform_device *dev)
806 748
807static int serial_pxa_probe(struct platform_device *dev) 749static int serial_pxa_probe(struct platform_device *dev)
808{ 750{
809 serial_pxa_ports[dev->id].port.dev = &dev->dev; 751 struct uart_pxa_port *sport;
810 uart_add_one_port(&serial_pxa_reg, &serial_pxa_ports[dev->id].port); 752 struct resource *mmres, *irqres;
811 platform_set_drvdata(dev, &serial_pxa_ports[dev->id]); 753 int ret;
754
755 mmres = platform_get_resource(dev, IORESOURCE_MEM, 0);
756 irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0);
757 if (!mmres || !irqres)
758 return -ENODEV;
759
760 sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL);
761 if (!sport)
762 return -ENOMEM;
763
764 sport->clk = clk_get(&dev->dev, "UARTCLK");
765 if (IS_ERR(sport->clk)) {
766 ret = PTR_ERR(sport->clk);
767 goto err_free;
768 }
769
770 sport->port.type = PORT_PXA;
771 sport->port.iotype = UPIO_MEM;
772 sport->port.mapbase = mmres->start;
773 sport->port.irq = irqres->start;
774 sport->port.fifosize = 64;
775 sport->port.ops = &serial_pxa_pops;
776 sport->port.line = dev->id;
777 sport->port.dev = &dev->dev;
778 sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
779 sport->port.uartclk = clk_get_rate(sport->clk);
780
781 /*
782 * Is it worth keeping this?
783 */
784 if (mmres->start == __PREG(FFUART))
785 sport->name = "FFUART";
786 else if (mmres->start == __PREG(BTUART))
787 sport->name = "BTUART";
788 else if (mmres->start == __PREG(STUART))
789 sport->name = "STUART";
790 else if (mmres->start == __PREG(HWUART))
791 sport->name = "HWUART";
792 else
793 sport->name = "???";
794
795 sport->port.membase = ioremap(mmres->start, mmres->end - mmres->start + 1);
796 if (!sport->port.membase) {
797 ret = -ENOMEM;
798 goto err_clk;
799 }
800
801 serial_pxa_ports[dev->id] = sport;
802
803 uart_add_one_port(&serial_pxa_reg, &sport->port);
804 platform_set_drvdata(dev, sport);
805
812 return 0; 806 return 0;
807
808 err_clk:
809 clk_put(sport->clk);
810 err_free:
811 kfree(sport);
812 return ret;
813} 813}
814 814
815static int serial_pxa_remove(struct platform_device *dev) 815static int serial_pxa_remove(struct platform_device *dev)
@@ -818,8 +818,9 @@ static int serial_pxa_remove(struct platform_device *dev)
818 818
819 platform_set_drvdata(dev, NULL); 819 platform_set_drvdata(dev, NULL);
820 820
821 if (sport) 821 uart_remove_one_port(&serial_pxa_reg, &sport->port);
822 uart_remove_one_port(&serial_pxa_reg, &sport->port); 822 clk_put(sport->clk);
823 kfree(sport);
823 824
824 return 0; 825 return 0;
825} 826}
diff --git a/drivers/serial/serial_core.c b/drivers/serial/serial_core.c
index a055f58f342f..a3bd3a3f41f3 100644
--- a/drivers/serial/serial_core.c
+++ b/drivers/serial/serial_core.c
@@ -2127,6 +2127,14 @@ uart_configure_port(struct uart_driver *drv, struct uart_state *state,
2127 spin_unlock_irqrestore(&port->lock, flags); 2127 spin_unlock_irqrestore(&port->lock, flags);
2128 2128
2129 /* 2129 /*
2130 * If this driver supports console, and it hasn't been
2131 * successfully registered yet, try to re-register it.
2132 * It may be that the port was not available.
2133 */
2134 if (port->cons && !(port->cons->flags & CON_ENABLED))
2135 register_console(port->cons);
2136
2137 /*
2130 * Power down all ports by default, except the 2138 * Power down all ports by default, except the
2131 * console if we have one. 2139 * console if we have one.
2132 */ 2140 */
@@ -2286,6 +2294,7 @@ int uart_add_one_port(struct uart_driver *drv, struct uart_port *port)
2286 } 2294 }
2287 2295
2288 state->port = port; 2296 state->port = port;
2297 state->pm_state = -1;
2289 2298
2290 port->cons = drv->cons; 2299 port->cons = drv->cons;
2291 port->info = state->info; 2300 port->info = state->info;
@@ -2308,15 +2317,6 @@ int uart_add_one_port(struct uart_driver *drv, struct uart_port *port)
2308 tty_register_device(drv->tty_driver, port->line, port->dev); 2317 tty_register_device(drv->tty_driver, port->line, port->dev);
2309 2318
2310 /* 2319 /*
2311 * If this driver supports console, and it hasn't been
2312 * successfully registered yet, try to re-register it.
2313 * It may be that the port was not available.
2314 */
2315 if (port->type != PORT_UNKNOWN &&
2316 port->cons && !(port->cons->flags & CON_ENABLED))
2317 register_console(port->cons);
2318
2319 /*
2320 * Ensure UPF_DEAD is not set. 2320 * Ensure UPF_DEAD is not set.
2321 */ 2321 */
2322 port->flags &= ~UPF_DEAD; 2322 port->flags &= ~UPF_DEAD;
diff --git a/drivers/usb/gadget/pxa2xx_udc.c b/drivers/usb/gadget/pxa2xx_udc.c
index 1407ad1c8128..90d0d086b9b8 100644
--- a/drivers/usb/gadget/pxa2xx_udc.c
+++ b/drivers/usb/gadget/pxa2xx_udc.c
@@ -43,6 +43,8 @@
43#include <linux/platform_device.h> 43#include <linux/platform_device.h>
44#include <linux/dma-mapping.h> 44#include <linux/dma-mapping.h>
45#include <linux/irq.h> 45#include <linux/irq.h>
46#include <linux/clk.h>
47#include <linux/err.h>
46 48
47#include <asm/byteorder.h> 49#include <asm/byteorder.h>
48#include <asm/dma.h> 50#include <asm/dma.h>
@@ -1157,7 +1159,7 @@ static void udc_disable(struct pxa2xx_udc *dev)
1157 1159
1158#ifdef CONFIG_ARCH_PXA 1160#ifdef CONFIG_ARCH_PXA
1159 /* Disable clock for USB device */ 1161 /* Disable clock for USB device */
1160 pxa_set_cken(CKEN_USB, 0); 1162 clk_disable(dev->clk);
1161#endif 1163#endif
1162 1164
1163 ep0_idle (dev); 1165 ep0_idle (dev);
@@ -1202,8 +1204,7 @@ static void udc_enable (struct pxa2xx_udc *dev)
1202 1204
1203#ifdef CONFIG_ARCH_PXA 1205#ifdef CONFIG_ARCH_PXA
1204 /* Enable clock for USB device */ 1206 /* Enable clock for USB device */
1205 pxa_set_cken(CKEN_USB, 1); 1207 clk_enable(dev->clk);
1206 udelay(5);
1207#endif 1208#endif
1208 1209
1209 /* try to clear these bits before we enable the udc */ 1210 /* try to clear these bits before we enable the udc */
@@ -2137,6 +2138,14 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev)
2137 if (irq < 0) 2138 if (irq < 0)
2138 return -ENODEV; 2139 return -ENODEV;
2139 2140
2141#ifdef CONFIG_ARCH_PXA
2142 dev->clk = clk_get(&pdev->dev, "UDCCLK");
2143 if (IS_ERR(dev->clk)) {
2144 retval = PTR_ERR(dev->clk);
2145 goto err_clk;
2146 }
2147#endif
2148
2140 pr_debug("%s: IRQ %d%s%s\n", driver_name, irq, 2149 pr_debug("%s: IRQ %d%s%s\n", driver_name, irq,
2141 dev->has_cfr ? "" : " (!cfr)", 2150 dev->has_cfr ? "" : " (!cfr)",
2142 SIZE_STR "(pio)" 2151 SIZE_STR "(pio)"
@@ -2152,11 +2161,10 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev)
2152 dev_dbg(&pdev->dev, 2161 dev_dbg(&pdev->dev,
2153 "can't get vbus gpio %d, err: %d\n", 2162 "can't get vbus gpio %d, err: %d\n",
2154 dev->mach->gpio_vbus, retval); 2163 dev->mach->gpio_vbus, retval);
2155 return -EBUSY; 2164 goto err_gpio_vbus;
2156 } 2165 }
2157 gpio_direction_input(dev->mach->gpio_vbus); 2166 gpio_direction_input(dev->mach->gpio_vbus);
2158 vbus_irq = gpio_to_irq(dev->mach->gpio_vbus); 2167 vbus_irq = gpio_to_irq(dev->mach->gpio_vbus);
2159 set_irq_type(vbus_irq, IRQT_BOTHEDGE);
2160 } else 2168 } else
2161 vbus_irq = 0; 2169 vbus_irq = 0;
2162 2170
@@ -2166,9 +2174,7 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev)
2166 dev_dbg(&pdev->dev, 2174 dev_dbg(&pdev->dev,
2167 "can't get pullup gpio %d, err: %d\n", 2175 "can't get pullup gpio %d, err: %d\n",
2168 dev->mach->gpio_pullup, retval); 2176 dev->mach->gpio_pullup, retval);
2169 if (dev->mach->gpio_vbus) 2177 goto err_gpio_pullup;
2170 gpio_free(dev->mach->gpio_vbus);
2171 return -EBUSY;
2172 } 2178 }
2173 gpio_direction_output(dev->mach->gpio_pullup, 0); 2179 gpio_direction_output(dev->mach->gpio_pullup, 0);
2174 } 2180 }
@@ -2195,11 +2201,7 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev)
2195 if (retval != 0) { 2201 if (retval != 0) {
2196 printk(KERN_ERR "%s: can't get irq %d, err %d\n", 2202 printk(KERN_ERR "%s: can't get irq %d, err %d\n",
2197 driver_name, irq, retval); 2203 driver_name, irq, retval);
2198 if (dev->mach->gpio_pullup) 2204 goto err_irq1;
2199 gpio_free(dev->mach->gpio_pullup);
2200 if (dev->mach->gpio_vbus)
2201 gpio_free(dev->mach->gpio_vbus);
2202 return -EBUSY;
2203 } 2205 }
2204 dev->got_irq = 1; 2206 dev->got_irq = 1;
2205 2207
@@ -2213,12 +2215,7 @@ static int __init pxa2xx_udc_probe(struct platform_device *pdev)
2213 printk(KERN_ERR "%s: can't get irq %i, err %d\n", 2215 printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2214 driver_name, LUBBOCK_USB_DISC_IRQ, retval); 2216 driver_name, LUBBOCK_USB_DISC_IRQ, retval);
2215lubbock_fail0: 2217lubbock_fail0:
2216 free_irq(irq, dev); 2218 goto err_irq_lub;
2217 if (dev->mach->gpio_pullup)
2218 gpio_free(dev->mach->gpio_pullup);
2219 if (dev->mach->gpio_vbus)
2220 gpio_free(dev->mach->gpio_vbus);
2221 return -EBUSY;
2222 } 2219 }
2223 retval = request_irq(LUBBOCK_USB_IRQ, 2220 retval = request_irq(LUBBOCK_USB_IRQ,
2224 lubbock_vbus_irq, 2221 lubbock_vbus_irq,
@@ -2234,22 +2231,37 @@ lubbock_fail0:
2234#endif 2231#endif
2235 if (vbus_irq) { 2232 if (vbus_irq) {
2236 retval = request_irq(vbus_irq, udc_vbus_irq, 2233 retval = request_irq(vbus_irq, udc_vbus_irq,
2237 IRQF_DISABLED | IRQF_SAMPLE_RANDOM, 2234 IRQF_DISABLED | IRQF_SAMPLE_RANDOM |
2235 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
2238 driver_name, dev); 2236 driver_name, dev);
2239 if (retval != 0) { 2237 if (retval != 0) {
2240 printk(KERN_ERR "%s: can't get irq %i, err %d\n", 2238 printk(KERN_ERR "%s: can't get irq %i, err %d\n",
2241 driver_name, vbus_irq, retval); 2239 driver_name, vbus_irq, retval);
2242 free_irq(irq, dev); 2240 goto err_vbus_irq;
2243 if (dev->mach->gpio_pullup)
2244 gpio_free(dev->mach->gpio_pullup);
2245 if (dev->mach->gpio_vbus)
2246 gpio_free(dev->mach->gpio_vbus);
2247 return -EBUSY;
2248 } 2241 }
2249 } 2242 }
2250 create_proc_files(); 2243 create_proc_files();
2251 2244
2252 return 0; 2245 return 0;
2246
2247 err_vbus_irq:
2248#ifdef CONFIG_ARCH_LUBBOCK
2249 free_irq(LUBBOCK_USB_DISC_IRQ, dev);
2250 err_irq_lub:
2251#endif
2252 free_irq(irq, dev);
2253 err_irq1:
2254 if (dev->mach->gpio_pullup)
2255 gpio_free(dev->mach->gpio_pullup);
2256 err_gpio_pullup:
2257 if (dev->mach->gpio_vbus)
2258 gpio_free(dev->mach->gpio_vbus);
2259 err_gpio_vbus:
2260#ifdef CONFIG_ARCH_PXA
2261 clk_put(dev->clk);
2262 err_clk:
2263#endif
2264 return retval;
2253} 2265}
2254 2266
2255static void pxa2xx_udc_shutdown(struct platform_device *_dev) 2267static void pxa2xx_udc_shutdown(struct platform_device *_dev)
@@ -2284,6 +2296,10 @@ static int __exit pxa2xx_udc_remove(struct platform_device *pdev)
2284 if (dev->mach->gpio_pullup) 2296 if (dev->mach->gpio_pullup)
2285 gpio_free(dev->mach->gpio_pullup); 2297 gpio_free(dev->mach->gpio_pullup);
2286 2298
2299#ifdef CONFIG_ARCH_PXA
2300 clk_put(dev->clk);
2301#endif
2302
2287 platform_set_drvdata(pdev, NULL); 2303 platform_set_drvdata(pdev, NULL);
2288 the_controller = NULL; 2304 the_controller = NULL;
2289 return 0; 2305 return 0;
diff --git a/drivers/usb/gadget/pxa2xx_udc.h b/drivers/usb/gadget/pxa2xx_udc.h
index 0e5d0e6fb0e2..1db46d705777 100644
--- a/drivers/usb/gadget/pxa2xx_udc.h
+++ b/drivers/usb/gadget/pxa2xx_udc.h
@@ -125,6 +125,7 @@ struct pxa2xx_udc {
125 struct timer_list timer; 125 struct timer_list timer;
126 126
127 struct device *dev; 127 struct device *dev;
128 struct clk *clk;
128 struct pxa2xx_udc_mach_info *mach; 129 struct pxa2xx_udc_mach_info *mach;
129 u64 dma_mask; 130 u64 dma_mask;
130 struct pxa2xx_ep ep [PXA_UDC_NUM_ENDPOINTS]; 131 struct pxa2xx_ep ep [PXA_UDC_NUM_ENDPOINTS];
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c
index a280a52f8efe..f9b12ab59642 100644
--- a/drivers/video/pxafb.c
+++ b/drivers/video/pxafb.c
@@ -37,6 +37,8 @@
37#include <linux/cpufreq.h> 37#include <linux/cpufreq.h>
38#include <linux/platform_device.h> 38#include <linux/platform_device.h>
39#include <linux/dma-mapping.h> 39#include <linux/dma-mapping.h>
40#include <linux/clk.h>
41#include <linux/err.h>
40 42
41#include <asm/hardware.h> 43#include <asm/hardware.h>
42#include <asm/io.h> 44#include <asm/io.h>
@@ -506,15 +508,15 @@ static struct fb_ops pxafb_ops = {
506 * 508 *
507 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below. 509 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
508 */ 510 */
509static inline unsigned int get_pcd(unsigned int pixclock) 511static inline unsigned int get_pcd(struct pxafb_info *fbi, unsigned int pixclock)
510{ 512{
511 unsigned long long pcd; 513 unsigned long long pcd;
512 514
513 /* FIXME: Need to take into account Double Pixel Clock mode 515 /* FIXME: Need to take into account Double Pixel Clock mode
514 * (DPC) bit? or perhaps set it based on the various clock 516 * (DPC) bit? or perhaps set it based on the various clock
515 * speeds */ 517 * speeds */
516 518 pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
517 pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock; 519 pcd *= pixclock;
518 do_div(pcd, 100000000 * 2); 520 do_div(pcd, 100000000 * 2);
519 /* no need for this, since we should subtract 1 anyway. they cancel */ 521 /* no need for this, since we should subtract 1 anyway. they cancel */
520 /* pcd += 1; */ /* make up for integer math truncations */ 522 /* pcd += 1; */ /* make up for integer math truncations */
@@ -523,19 +525,21 @@ static inline unsigned int get_pcd(unsigned int pixclock)
523 525
524/* 526/*
525 * Some touchscreens need hsync information from the video driver to 527 * Some touchscreens need hsync information from the video driver to
526 * function correctly. We export it here. 528 * function correctly. We export it here. Note that 'hsync_time' and
529 * the value returned from pxafb_get_hsync_time() is the *reciprocal*
530 * of the hsync period in seconds.
527 */ 531 */
528static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd) 532static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
529{ 533{
530 unsigned long long htime; 534 unsigned long htime;
531 535
532 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) { 536 if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
533 fbi->hsync_time=0; 537 fbi->hsync_time=0;
534 return; 538 return;
535 } 539 }
536 540
537 htime = (unsigned long long)get_lcdclk_frequency_10khz() * 10000; 541 htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
538 do_div(htime, pcd * fbi->fb.var.hsync_len); 542
539 fbi->hsync_time = htime; 543 fbi->hsync_time = htime;
540} 544}
541 545
@@ -560,7 +564,7 @@ static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *
560{ 564{
561 struct pxafb_lcd_reg new_regs; 565 struct pxafb_lcd_reg new_regs;
562 u_long flags; 566 u_long flags;
563 u_int lines_per_panel, pcd = get_pcd(var->pixclock); 567 u_int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
564 568
565 pr_debug("pxafb: Configuring PXA LCD\n"); 569 pr_debug("pxafb: Configuring PXA LCD\n");
566 570
@@ -803,7 +807,7 @@ static void pxafb_enable_controller(struct pxafb_info *fbi)
803 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3); 807 pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
804 808
805 /* enable LCD controller clock */ 809 /* enable LCD controller clock */
806 pxa_set_cken(CKEN_LCD, 1); 810 clk_enable(fbi->clk);
807 811
808 /* Sequence from 11.7.10 */ 812 /* Sequence from 11.7.10 */
809 LCCR3 = fbi->reg_lccr3; 813 LCCR3 = fbi->reg_lccr3;
@@ -840,7 +844,7 @@ static void pxafb_disable_controller(struct pxafb_info *fbi)
840 remove_wait_queue(&fbi->ctrlr_wait, &wait); 844 remove_wait_queue(&fbi->ctrlr_wait, &wait);
841 845
842 /* disable LCD controller clock */ 846 /* disable LCD controller clock */
843 pxa_set_cken(CKEN_LCD, 0); 847 clk_disable(fbi->clk);
844} 848}
845 849
846/* 850/*
@@ -994,7 +998,7 @@ pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
994 break; 998 break;
995 999
996 case CPUFREQ_POSTCHANGE: 1000 case CPUFREQ_POSTCHANGE:
997 pcd = get_pcd(fbi->fb.var.pixclock); 1001 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
998 set_hsync_time(fbi, pcd); 1002 set_hsync_time(fbi, pcd);
999 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd); 1003 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
1000 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE); 1004 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
@@ -1119,6 +1123,12 @@ static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1119 memset(fbi, 0, sizeof(struct pxafb_info)); 1123 memset(fbi, 0, sizeof(struct pxafb_info));
1120 fbi->dev = dev; 1124 fbi->dev = dev;
1121 1125
1126 fbi->clk = clk_get(dev, "LCDCLK");
1127 if (IS_ERR(fbi->clk)) {
1128 kfree(fbi);
1129 return NULL;
1130 }
1131
1122 strcpy(fbi->fb.fix.id, PXA_NAME); 1132 strcpy(fbi->fb.fix.id, PXA_NAME);
1123 1133
1124 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS; 1134 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
diff --git a/drivers/video/pxafb.h b/drivers/video/pxafb.h
index 7499a1c4bf79..f8605b807b0a 100644
--- a/drivers/video/pxafb.h
+++ b/drivers/video/pxafb.h
@@ -40,6 +40,7 @@ struct pxafb_dma_descriptor {
40struct pxafb_info { 40struct pxafb_info {
41 struct fb_info fb; 41 struct fb_info fb;
42 struct device *dev; 42 struct device *dev;
43 struct clk *clk;
43 44
44 /* 45 /*
45 * These are the addresses we mapped 46 * These are the addresses we mapped
diff --git a/include/asm-arm/arch-pxa/cm-x270.h b/include/asm-arm/arch-pxa/cm-x270.h
new file mode 100644
index 000000000000..f8fac9e18009
--- /dev/null
+++ b/include/asm-arm/arch-pxa/cm-x270.h
@@ -0,0 +1,50 @@
1/*
2 * linux/include/asm/arch-pxa/cm-x270.h
3 *
4 * Copyright Compulab Ltd., 2003, 2007
5 * Mike Rapoport <mike@compulab.co.il>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12
13/* CM-x270 device physical addresses */
14#define CMX270_CS1_PHYS (PXA_CS1_PHYS)
15#define MARATHON_PHYS (PXA_CS2_PHYS)
16#define CMX270_IDE104_PHYS (PXA_CS3_PHYS)
17#define CMX270_IT8152_PHYS (PXA_CS4_PHYS)
18
19/* Statically mapped regions */
20#define CMX270_VIRT_BASE (0xe8000000)
21#define CMX270_IT8152_VIRT (CMX270_VIRT_BASE)
22#define CMX270_IDE104_VIRT (CMX270_IT8152_VIRT + SZ_64M)
23
24/* GPIO related definitions */
25#define GPIO_IT8152_IRQ (22)
26
27#define IRQ_GPIO_IT8152_IRQ IRQ_GPIO(GPIO_IT8152_IRQ)
28#define PME_IRQ IRQ_GPIO(0)
29#define CMX270_IDE_IRQ IRQ_GPIO(100)
30#define CMX270_GPIRQ1 IRQ_GPIO(101)
31#define CMX270_TOUCHIRQ IRQ_GPIO(96)
32#define CMX270_ETHIRQ IRQ_GPIO(10)
33#define CMX270_GFXIRQ IRQ_GPIO(95)
34#define CMX270_NANDIRQ IRQ_GPIO(89)
35#define CMX270_MMC_IRQ IRQ_GPIO(83)
36
37/* PCMCIA related definitions */
38#define PCC_DETECT(x) (GPLR(84 - (x)) & GPIO_bit(84 - (x)))
39#define PCC_READY(x) (GPLR(82 - (x)) & GPIO_bit(82 - (x)))
40
41#define PCMCIA_S0_CD_VALID IRQ_GPIO(84)
42#define PCMCIA_S0_CD_VALID_EDGE GPIO_BOTH_EDGES
43
44#define PCMCIA_S1_CD_VALID IRQ_GPIO(83)
45#define PCMCIA_S1_CD_VALID_EDGE GPIO_BOTH_EDGES
46
47#define PCMCIA_S0_RDYINT IRQ_GPIO(82)
48#define PCMCIA_S1_RDYINT IRQ_GPIO(81)
49
50#define PCMCIA_RESET_GPIO 53
diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h
index 3280ee2ddfa5..dbe110ee2666 100644
--- a/include/asm-arm/arch-pxa/dma.h
+++ b/include/asm-arm/arch-pxa/dma.h
@@ -30,6 +30,10 @@ typedef enum {
30 DMA_PRIO_LOW = 2 30 DMA_PRIO_LOW = 2
31} pxa_dma_prio; 31} pxa_dma_prio;
32 32
33#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
34#define HAVE_ARCH_PCI_SET_DMA_MASK 1
35#endif
36
33/* 37/*
34 * DMA registration 38 * DMA registration
35 */ 39 */
diff --git a/include/asm-arm/arch-pxa/gpio.h b/include/asm-arm/arch-pxa/gpio.h
index 9e99241f3edf..9dbc2dc794f7 100644
--- a/include/asm-arm/arch-pxa/gpio.h
+++ b/include/asm-arm/arch-pxa/gpio.h
@@ -38,16 +38,8 @@ static inline void gpio_free(unsigned gpio)
38 return; 38 return;
39} 39}
40 40
41static inline int gpio_direction_input(unsigned gpio) 41extern int gpio_direction_input(unsigned gpio);
42{ 42extern int gpio_direction_output(unsigned gpio, int value);
43 return pxa_gpio_mode(gpio | GPIO_IN);
44}
45
46static inline int gpio_direction_output(unsigned gpio, int value)
47{
48 return pxa_gpio_mode(gpio | GPIO_OUT |
49 (value ? GPIO_DFLT_HIGH : GPIO_DFLT_LOW));
50}
51 43
52static inline int __gpio_get_value(unsigned gpio) 44static inline int __gpio_get_value(unsigned gpio)
53{ 45{
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index 386121746417..ab2d963e742a 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -62,6 +62,7 @@
62 62
63#ifndef __ASSEMBLY__ 63#ifndef __ASSEMBLY__
64 64
65#ifdef CONFIG_PXA25x
65#define __cpu_is_pxa21x(id) \ 66#define __cpu_is_pxa21x(id) \
66 ({ \ 67 ({ \
67 unsigned int _id = (id) >> 4 & 0xf3f; \ 68 unsigned int _id = (id) >> 4 & 0xf3f; \
@@ -73,12 +74,50 @@
73 unsigned int _id = (id) >> 4 & 0xfff; \ 74 unsigned int _id = (id) >> 4 & 0xfff; \
74 _id == 0x2d0 || _id == 0x290; \ 75 _id == 0x2d0 || _id == 0x290; \
75 }) 76 })
77#else
78#define __cpu_is_pxa21x(id) (0)
79#define __cpu_is_pxa25x(id) (0)
80#endif
76 81
82#ifdef CONFIG_PXA27x
77#define __cpu_is_pxa27x(id) \ 83#define __cpu_is_pxa27x(id) \
78 ({ \ 84 ({ \
79 unsigned int _id = (id) >> 4 & 0xfff; \ 85 unsigned int _id = (id) >> 4 & 0xfff; \
80 _id == 0x411; \ 86 _id == 0x411; \
81 }) 87 })
88#else
89#define __cpu_is_pxa27x(id) (0)
90#endif
91
92#ifdef CONFIG_CPU_PXA300
93#define __cpu_is_pxa300(id) \
94 ({ \
95 unsigned int _id = (id) >> 4 & 0xfff; \
96 _id == 0x688; \
97 })
98#else
99#define __cpu_is_pxa300(id) (0)
100#endif
101
102#ifdef CONFIG_CPU_PXA310
103#define __cpu_is_pxa310(id) \
104 ({ \
105 unsigned int _id = (id) >> 4 & 0xfff; \
106 _id == 0x689; \
107 })
108#else
109#define __cpu_is_pxa310(id) (0)
110#endif
111
112#ifdef CONFIG_CPU_PXA320
113#define __cpu_is_pxa320(id) \
114 ({ \
115 unsigned int _id = (id) >> 4 & 0xfff; \
116 _id == 0x603 || _id == 0x682; \
117 })
118#else
119#define __cpu_is_pxa320(id) (0)
120#endif
82 121
83#define cpu_is_pxa21x() \ 122#define cpu_is_pxa21x() \
84 ({ \ 123 ({ \
@@ -98,6 +137,53 @@
98 __cpu_is_pxa27x(id); \ 137 __cpu_is_pxa27x(id); \
99 }) 138 })
100 139
140#define cpu_is_pxa300() \
141 ({ \
142 unsigned int id = read_cpuid(CPUID_ID); \
143 __cpu_is_pxa300(id); \
144 })
145
146#define cpu_is_pxa310() \
147 ({ \
148 unsigned int id = read_cpuid(CPUID_ID); \
149 __cpu_is_pxa310(id); \
150 })
151
152#define cpu_is_pxa320() \
153 ({ \
154 unsigned int id = read_cpuid(CPUID_ID); \
155 __cpu_is_pxa320(id); \
156 })
157
158/*
159 * CPUID Core Generation Bit
160 * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
161 * == 0x3 for pxa300/pxa310/pxa320
162 */
163#define __cpu_is_pxa2xx(id) \
164 ({ \
165 unsigned int _id = (id) >> 13 & 0x7; \
166 _id <= 0x2; \
167 })
168
169#define __cpu_is_pxa3xx(id) \
170 ({ \
171 unsigned int _id = (id) >> 13 & 0x7; \
172 _id == 0x3; \
173 })
174
175#define cpu_is_pxa2xx() \
176 ({ \
177 unsigned int id = read_cpuid(CPUID_ID); \
178 __cpu_is_pxa2xx(id); \
179 })
180
181#define cpu_is_pxa3xx() \
182 ({ \
183 unsigned int id = read_cpuid(CPUID_ID); \
184 __cpu_is_pxa3xx(id); \
185 })
186
101/* 187/*
102 * Handy routine to set GPIO alternate functions 188 * Handy routine to set GPIO alternate functions
103 */ 189 */
@@ -116,14 +202,23 @@ extern void pxa_gpio_set_value(unsigned gpio, int value);
116/* 202/*
117 * Routine to enable or disable CKEN 203 * Routine to enable or disable CKEN
118 */ 204 */
119extern void pxa_set_cken(int clock, int enable); 205static inline void __deprecated pxa_set_cken(int clock, int enable)
206{
207 extern void __pxa_set_cken(int clock, int enable);
208 __pxa_set_cken(clock, enable);
209}
120 210
121/* 211/*
122 * return current memory and LCD clock frequency in units of 10kHz 212 * return current memory and LCD clock frequency in units of 10kHz
123 */ 213 */
124extern unsigned int get_memclk_frequency_10khz(void); 214extern unsigned int get_memclk_frequency_10khz(void);
125extern unsigned int get_lcdclk_frequency_10khz(void);
126 215
127#endif 216#endif
128 217
218#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
219#define PCIBIOS_MIN_IO 0
220#define PCIBIOS_MIN_MEM 0
221#define pcibios_assign_all_busses() 1
222#endif
223
129#endif /* _ASM_ARCH_HARDWARE_H */ 224#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index a07fe0f928cd..6238dbf7a236 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -66,12 +66,6 @@
66#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE) 66#define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE)
67#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) 67#define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
68 68
69#if defined(CONFIG_PXA25x)
70#define PXA_LAST_GPIO 84
71#elif defined(CONFIG_PXA27x)
72#define PXA_LAST_GPIO 127
73#endif
74
75/* 69/*
76 * The next 16 interrupts are for board specific purposes. Since 70 * The next 16 interrupts are for board specific purposes. Since
77 * the kernel can only run on one machine at a time, we can re-use 71 * the kernel can only run on one machine at a time, we can re-use
@@ -216,3 +210,24 @@
216#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1) 210#define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1)
217#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) 211#define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2)
218#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) 212#define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3)
213
214/* ITE8152 irqs */
215/* add IT8152 IRQs beyond BOARD_END */
216#ifdef CONFIG_PCI_HOST_ITE8152
217#define IT8152_IRQ(x) (IRQ_GPIO(IRQ_BOARD_END) + 1 + (x))
218
219/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */
220#define IT8152_LD_IRQ_COUNT 9
221#define IT8152_LP_IRQ_COUNT 16
222#define IT8152_PD_IRQ_COUNT 15
223
224/* Priorities: */
225#define IT8152_PD_IRQ(i) IT8152_IRQ(i)
226#define IT8152_LP_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT)
227#define IT8152_LD_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT)
228
229#define IT8152_LAST_IRQ IT8152_LD_IRQ(IT8152_LD_IRQ_COUNT - 1)
230
231#undef NR_IRQS
232#define NR_IRQS (IT8152_LAST_IRQ+1)
233#endif
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
index e17f9881faf0..bee81d66c184 100644
--- a/include/asm-arm/arch-pxa/memory.h
+++ b/include/asm-arm/arch-pxa/memory.h
@@ -39,4 +39,14 @@
39 */ 39 */
40#define NODE_MEM_SIZE_BITS 26 40#define NODE_MEM_SIZE_BITS 26
41 41
42#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
43void cmx270_pci_adjust_zones(int node, unsigned long *size,
44 unsigned long *holes);
45
46#define arch_adjust_zones(node, size, holes) \
47 cmx270_pci_adjust_zones(node, size, holes)
48
49#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1)
50#endif
51
42#endif 52#endif
diff --git a/include/asm-arm/arch-pxa/mfp-pxa300.h b/include/asm-arm/arch-pxa/mfp-pxa300.h
new file mode 100644
index 000000000000..7513c7a3402d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa300.h
@@ -0,0 +1,574 @@
1/*
2 * linux/include/asm-arm/arch-pxa/mfp-pxa300.h
3 *
4 * PXA300/PXA310 specific MFP configuration definitions
5 *
6 * Copyright (C) 2007 Marvell International Ltd.
7 * 2007-08-21: eric miao <eric.y.miao@gmail.com>
8 * initial version
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARCH_MFP_PXA300_H
16#define __ASM_ARCH_MFP_PXA300_H
17
18#include <asm/arch/mfp.h>
19
20/* GPIO */
21#define GPIO46_GPIO MFP_CFG(GPIO46, AF1)
22#define GPIO49_GPIO MFP_CFG(GPIO49, AF3)
23#define GPIO50_GPIO MFP_CFG(GPIO50, AF2)
24#define GPIO51_GPIO MFP_CFG(GPIO51, AF3)
25#define GPIO52_GPIO MFP_CFG(GPIO52, AF3)
26#define GPIO56_GPIO MFP_CFG(GPIO56, AF0)
27#define GPIO58_GPIO MFP_CFG(GPIO58, AF0)
28#define GPIO59_GPIO MFP_CFG(GPIO59, AF0)
29#define GPIO60_GPIO MFP_CFG(GPIO60, AF0)
30#define GPIO61_GPIO MFP_CFG(GPIO61, AF0)
31#define GPIO62_GPIO MFP_CFG(GPIO62, AF0)
32
33#ifdef CONFIG_CPU_PXA310
34#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0)
35#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0)
36#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0)
37#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0)
38#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0)
39#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0)
40#endif
41
42/* Chip Select */
43#define GPIO2_nCS3 MFP_CFG(GPIO2, AF1)
44
45/* AC97 */
46#define GPIO23_AC97_nACRESET MFP_CFG(GPIO23, AF1)
47#define GPIO24_AC97_SYSCLK MFP_CFG(GPIO24, AF1)
48#define GPIO29_AC97_BITCLK MFP_CFG(GPIO29, AF1)
49#define GPIO25_AC97_SDATA_IN_0 MFP_CFG(GPIO25, AF1)
50#define GPIO26_AC97_SDATA_IN_1 MFP_CFG(GPIO26, AF1)
51#define GPIO17_AC97_SDATA_IN_2 MFP_CFG(GPIO17, AF3)
52#define GPIO21_AC97_SDATA_IN_2 MFP_CFG(GPIO21, AF2)
53#define GPIO18_AC97_SDATA_IN_3 MFP_CFG(GPIO18, AF3)
54#define GPIO22_AC97_SDATA_IN_3 MFP_CFG(GPIO22, AF2)
55#define GPIO27_AC97_SDATA_OUT MFP_CFG(GPIO27, AF1)
56#define GPIO28_AC97_SYNC MFP_CFG(GPIO28, AF1)
57
58/* I2C */
59#define GPIO21_I2C_SCL MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH)
60#define GPIO22_I2C_SDA MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH)
61
62/* QCI */
63#define GPIO39_CI_DD_0 MFP_CFG_DRV(GPIO39, AF1, DS04X)
64#define GPIO40_CI_DD_1 MFP_CFG_DRV(GPIO40, AF1, DS04X)
65#define GPIO41_CI_DD_2 MFP_CFG_DRV(GPIO41, AF1, DS04X)
66#define GPIO42_CI_DD_3 MFP_CFG_DRV(GPIO42, AF1, DS04X)
67#define GPIO43_CI_DD_4 MFP_CFG_DRV(GPIO43, AF1, DS04X)
68#define GPIO44_CI_DD_5 MFP_CFG_DRV(GPIO44, AF1, DS04X)
69#define GPIO45_CI_DD_6 MFP_CFG_DRV(GPIO45, AF1, DS04X)
70#define GPIO46_CI_DD_7 MFP_CFG_DRV(GPIO46, AF0, DS04X)
71#define GPIO47_CI_DD_8 MFP_CFG_DRV(GPIO47, AF1, DS04X)
72#define GPIO48_CI_DD_9 MFP_CFG_DRV(GPIO48, AF1, DS04X)
73#define GPIO52_CI_HSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X)
74#define GPIO51_CI_VSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X)
75#define GPIO49_CI_MCLK MFP_CFG_DRV(GPIO49, AF0, DS04X)
76#define GPIO50_CI_PCLK MFP_CFG_DRV(GPIO50, AF0, DS04X)
77
78/* KEYPAD */
79#define GPIO3_KP_DKIN_6 MFP_CFG_LPM(GPIO3, AF2, FLOAT)
80#define GPIO4_KP_DKIN_7 MFP_CFG_LPM(GPIO4, AF2, FLOAT)
81#define GPIO16_KP_DKIN_6 MFP_CFG_LPM(GPIO16, AF6, FLOAT)
82#define GPIO83_KP_DKIN_2 MFP_CFG_LPM(GPIO83, AF5, FLOAT)
83#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF5, FLOAT)
84#define GPIO85_KP_DKIN_0 MFP_CFG_LPM(GPIO85, AF3, FLOAT)
85#define GPIO86_KP_DKIN_1 MFP_CFG_LPM(GPIO86, AF3, FLOAT)
86#define GPIO87_KP_DKIN_2 MFP_CFG_LPM(GPIO87, AF3, FLOAT)
87#define GPIO88_KP_DKIN_3 MFP_CFG_LPM(GPIO88, AF3, FLOAT)
88#define GPIO89_KP_DKIN_3 MFP_CFG_LPM(GPIO89, AF3, FLOAT)
89#define GPIO107_KP_DKIN_0 MFP_CFG_LPM(GPIO107, AF2, FLOAT)
90#define GPIO108_KP_DKIN_1 MFP_CFG_LPM(GPIO108, AF2, FLOAT)
91#define GPIO109_KP_DKIN_2 MFP_CFG_LPM(GPIO109, AF2, FLOAT)
92#define GPIO110_KP_DKIN_3 MFP_CFG_LPM(GPIO110, AF2, FLOAT)
93#define GPIO111_KP_DKIN_4 MFP_CFG_LPM(GPIO111, AF2, FLOAT)
94#define GPIO112_KP_DKIN_5 MFP_CFG_LPM(GPIO112, AF2, FLOAT)
95#define GPIO113_KP_DKIN_6 MFP_CFG_LPM(GPIO113, AF2, FLOAT)
96#define GPIO114_KP_DKIN_7 MFP_CFG_LPM(GPIO114, AF2, FLOAT)
97#define GPIO115_KP_DKIN_0 MFP_CFG_LPM(GPIO115, AF2, FLOAT)
98#define GPIO116_KP_DKIN_1 MFP_CFG_LPM(GPIO116, AF2, FLOAT)
99#define GPIO117_KP_DKIN_2 MFP_CFG_LPM(GPIO117, AF2, FLOAT)
100#define GPIO118_KP_DKIN_3 MFP_CFG_LPM(GPIO118, AF2, FLOAT)
101#define GPIO119_KP_DKIN_4 MFP_CFG_LPM(GPIO119, AF2, FLOAT)
102#define GPIO120_KP_DKIN_5 MFP_CFG_LPM(GPIO120, AF2, FLOAT)
103#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT)
104#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT)
105#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT)
106#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT)
107#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF5, FLOAT)
108#define GPIO0_2_KP_DKIN_0 MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
109#define GPIO1_2_KP_DKIN_1 MFP_CFG_LPM(GPIO1_2, AF2, FLOAT)
110#define GPIO2_2_KP_DKIN_6 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
111#define GPIO3_2_KP_DKIN_7 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
112#define GPIO4_2_KP_DKIN_1 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
113#define GPIO5_2_KP_DKIN_0 MFP_CFG_LPM(GPIO5_2, AF2, FLOAT)
114
115#define GPIO5_KP_MKIN_0 MFP_CFG_LPM(GPIO5, AF2, FLOAT)
116#define GPIO6_KP_MKIN_1 MFP_CFG_LPM(GPIO6, AF2, FLOAT)
117#define GPIO9_KP_MKIN_6 MFP_CFG_LPM(GPIO9, AF3, FLOAT)
118#define GPIO10_KP_MKIN_7 MFP_CFG_LPM(GPIO10, AF3, FLOAT)
119#define GPIO70_KP_MKIN_6 MFP_CFG_LPM(GPIO70, AF3, FLOAT)
120#define GPIO71_KP_MKIN_7 MFP_CFG_LPM(GPIO71, AF3, FLOAT)
121#define GPIO100_KP_MKIN_6 MFP_CFG_LPM(GPIO100, AF7, FLOAT)
122#define GPIO101_KP_MKIN_7 MFP_CFG_LPM(GPIO101, AF7, FLOAT)
123#define GPIO112_KP_MKIN_6 MFP_CFG_LPM(GPIO112, AF4, FLOAT)
124#define GPIO113_KP_MKIN_7 MFP_CFG_LPM(GPIO113, AF4, FLOAT)
125#define GPIO115_KP_MKIN_0 MFP_CFG_LPM(GPIO115, AF1, FLOAT)
126#define GPIO116_KP_MKIN_1 MFP_CFG_LPM(GPIO116, AF1, FLOAT)
127#define GPIO117_KP_MKIN_2 MFP_CFG_LPM(GPIO117, AF1, FLOAT)
128#define GPIO118_KP_MKIN_3 MFP_CFG_LPM(GPIO118, AF1, FLOAT)
129#define GPIO119_KP_MKIN_4 MFP_CFG_LPM(GPIO119, AF1, FLOAT)
130#define GPIO120_KP_MKIN_5 MFP_CFG_LPM(GPIO120, AF1, FLOAT)
131#define GPIO125_KP_MKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT)
132#define GPIO2_2_KP_MKIN_6 MFP_CFG_LPM(GPIO2_2, AF1, FLOAT)
133#define GPIO3_2_KP_MKIN_7 MFP_CFG_LPM(GPIO3_2, AF1, FLOAT)
134
135#define GPIO7_KP_MKOUT_5 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH)
136#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF3, DRIVE_HIGH)
137#define GPIO12_KP_MKOUT_6 MFP_CFG_LPM(GPIO12, AF3, DRIVE_HIGH)
138#define GPIO13_KP_MKOUT_7 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH)
139#define GPIO19_KP_MKOUT_4 MFP_CFG_LPM(GPIO19, AF3, DRIVE_HIGH)
140#define GPIO20_KP_MKOUT_5 MFP_CFG_LPM(GPIO20, AF3, DRIVE_HIGH)
141#define GPIO38_KP_MKOUT_5 MFP_CFG_LPM(GPIO38, AF5, DRIVE_HIGH)
142#define GPIO53_KP_MKOUT_6 MFP_CFG_LPM(GPIO53, AF5, DRIVE_HIGH)
143#define GPIO78_KP_MKOUT_7 MFP_CFG_LPM(GPIO78, AF5, DRIVE_HIGH)
144#define GPIO85_KP_MKOUT_0 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH)
145#define GPIO86_KP_MKOUT_1 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH)
146#define GPIO87_KP_MKOUT_2 MFP_CFG_LPM(GPIO87, AF2, DRIVE_HIGH)
147#define GPIO88_KP_MKOUT_3 MFP_CFG_LPM(GPIO88, AF2, DRIVE_HIGH)
148#define GPIO104_KP_MKOUT_6 MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH)
149#define GPIO105_KP_MKOUT_7 MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH)
150#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
151#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
152#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
153#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
154#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
155#define GPIO126_KP_MKOUT_7 MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH)
156#define GPIO5_2_KP_MKOUT_6 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
157#define GPIO4_2_KP_MKOUT_5 MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH)
158#define GPIO6_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH)
159
160/* LCD */
161#define GPIO54_LCD_LDD_0 MFP_CFG_DRV(GPIO54, AF1, DS01X)
162#define GPIO55_LCD_LDD_1 MFP_CFG_DRV(GPIO55, AF1, DS01X)
163#define GPIO56_LCD_LDD_2 MFP_CFG_DRV(GPIO56, AF1, DS01X)
164#define GPIO57_LCD_LDD_3 MFP_CFG_DRV(GPIO57, AF1, DS01X)
165#define GPIO58_LCD_LDD_4 MFP_CFG_DRV(GPIO58, AF1, DS01X)
166#define GPIO59_LCD_LDD_5 MFP_CFG_DRV(GPIO59, AF1, DS01X)
167#define GPIO60_LCD_LDD_6 MFP_CFG_DRV(GPIO60, AF1, DS01X)
168#define GPIO61_LCD_LDD_7 MFP_CFG_DRV(GPIO61, AF1, DS01X)
169#define GPIO62_LCD_LDD_8 MFP_CFG_DRV(GPIO62, AF1, DS01X)
170#define GPIO63_LCD_LDD_9 MFP_CFG_DRV(GPIO63, AF1, DS01X)
171#define GPIO64_LCD_LDD_10 MFP_CFG_DRV(GPIO64, AF1, DS01X)
172#define GPIO65_LCD_LDD_11 MFP_CFG_DRV(GPIO65, AF1, DS01X)
173#define GPIO66_LCD_LDD_12 MFP_CFG_DRV(GPIO66, AF1, DS01X)
174#define GPIO67_LCD_LDD_13 MFP_CFG_DRV(GPIO67, AF1, DS01X)
175#define GPIO68_LCD_LDD_14 MFP_CFG_DRV(GPIO68, AF1, DS01X)
176#define GPIO69_LCD_LDD_15 MFP_CFG_DRV(GPIO69, AF1, DS01X)
177#define GPIO70_LCD_LDD_16 MFP_CFG_DRV(GPIO70, AF1, DS01X)
178#define GPIO71_LCD_LDD_17 MFP_CFG_DRV(GPIO71, AF1, DS01X)
179#define GPIO62_LCD_CS_N MFP_CFG_DRV(GPIO62, AF2, DS01X)
180#define GPIO72_LCD_FCLK MFP_CFG_DRV(GPIO72, AF1, DS01X)
181#define GPIO73_LCD_LCLK MFP_CFG_DRV(GPIO73, AF1, DS01X)
182#define GPIO74_LCD_PCLK MFP_CFG_DRV(GPIO74, AF1, DS01X)
183#define GPIO75_LCD_BIAS MFP_CFG_DRV(GPIO75, AF1, DS01X)
184#define GPIO76_LCD_VSYNC MFP_CFG_DRV(GPIO76, AF2, DS01X)
185
186#define GPIO15_LCD_CS_N MFP_CFG_DRV(GPIO15, AF2, DS01X)
187#define GPIO127_LCD_CS_N MFP_CFG_DRV(GPIO127, AF1, DS01X)
188#define GPIO63_LCD_VSYNC MFP_CFG_DRV(GPIO63, AF2, DS01X)
189
190/* Mini-LCD */
191#define GPIO72_MLCD_FCLK MFP_CFG_DRV(GPIO72, AF7, DS08X)
192#define GPIO73_MLCD_LCLK MFP_CFG_DRV(GPIO73, AF7, DS08X)
193#define GPIO54_MLCD_LDD_0 MFP_CFG_DRV(GPIO54, AF7, DS08X)
194#define GPIO55_MLCD_LDD_1 MFP_CFG_DRV(GPIO55, AF7, DS08X)
195#define GPIO56_MLCD_LDD_2 MFP_CFG_DRV(GPIO56, AF7, DS08X)
196#define GPIO57_MLCD_LDD_3 MFP_CFG_DRV(GPIO57, AF7, DS08X)
197#define GPIO58_MLCD_LDD_4 MFP_CFG_DRV(GPIO58, AF7, DS08X)
198#define GPIO59_MLCD_LDD_5 MFP_CFG_DRV(GPIO59, AF7, DS08X)
199#define GPIO60_MLCD_LDD_6 MFP_CFG_DRV(GPIO60, AF7, DS08X)
200#define GPIO61_MLCD_LDD_7 MFP_CFG_DRV(GPIO61, AF7, DS08X)
201#define GPIO62_MLCD_LDD_8 MFP_CFG_DRV(GPIO62, AF7, DS08X)
202#define GPIO63_MLCD_LDD_9 MFP_CFG_DRV(GPIO63, AF7, DS08X)
203#define GPIO64_MLCD_LDD_10 MFP_CFG_DRV(GPIO64, AF7, DS08X)
204#define GPIO65_MLCD_LDD_11 MFP_CFG_DRV(GPIO65, AF7, DS08X)
205#define GPIO66_MLCD_LDD_12 MFP_CFG_DRV(GPIO66, AF7, DS08X)
206#define GPIO67_MLCD_LDD_13 MFP_CFG_DRV(GPIO67, AF7, DS08X)
207#define GPIO68_MLCD_LDD_14 MFP_CFG_DRV(GPIO68, AF7, DS08X)
208#define GPIO69_MLCD_LDD_15 MFP_CFG_DRV(GPIO69, AF7, DS08X)
209#define GPIO74_MLCD_PCLK MFP_CFG_DRV(GPIO74, AF7, DS08X)
210#define GPIO75_MLCD_BIAS MFP_CFG_DRV(GPIO75, AF2, DS08X)
211
212/* MMC1 */
213#define GPIO7_MMC1_CLK MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH)
214#define GPIO8_MMC1_CMD MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH)
215#define GPIO14_MMC1_CMD MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH)
216#define GPIO15_MMC1_CMD MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH)
217#define GPIO3_MMC1_DAT0 MFP_CFG_LPM(GPIO3, AF4, DRIVE_HIGH)
218#define GPIO4_MMC1_DAT1 MFP_CFG_LPM(GPIO4, AF4, DRIVE_HIGH)
219#define GPIO5_MMC1_DAT2 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH)
220#define GPIO6_MMC1_DAT3 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH)
221
222/* MMC2 */
223#define GPIO9_MMC2_DAT0 MFP_CFG_LPM(GPIO9, AF4, PULL_HIGH)
224#define GPIO10_MMC2_DAT1 MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH)
225#define GPIO11_MMC2_DAT2 MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH)
226#define GPIO12_MMC2_DAT3 MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH)
227#define GPIO13_MMC2_CLK MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH)
228#define GPIO14_MMC2_CMD MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH)
229#define GPIO77_MMC2_DAT0 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
230#define GPIO78_MMC2_DAT1 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
231#define GPIO79_MMC2_DAT2 MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
232#define GPIO80_MMC2_DAT3 MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
233#define GPIO81_MMC2_CLK MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH)
234#define GPIO82_MMC2_CMD MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH)
235
236/* SSP1 */
237#define GPIO89_SSP1_EXTCLK MFP_CFG(GPIO89, AF1)
238#define GPIO90_SSP1_SYSCLK MFP_CFG(GPIO90, AF1)
239#define GPIO15_SSP1_SCLK MFP_CFG(GPIO15, AF6)
240#define GPIO16_SSP1_FRM MFP_CFG(GPIO16, AF2)
241#define GPIO33_SSP1_SCLK MFP_CFG(GPIO33, AF5)
242#define GPIO34_SSP1_FRM MFP_CFG(GPIO34, AF5)
243#define GPIO85_SSP1_SCLK MFP_CFG(GPIO85, AF1)
244#define GPIO86_SSP1_FRM MFP_CFG(GPIO86, AF1)
245#define GPIO18_SSP1_TXD MFP_CFG(GPIO18, AF7)
246#define GPIO18_SSP1_RXD MFP_CFG(GPIO18, AF2)
247#define GPIO20_SSP1_TXD MFP_CFG(GPIO20, AF2)
248#define GPIO20_SSP1_RXD MFP_CFG(GPIO20, AF7)
249#define GPIO35_SSP1_TXD MFP_CFG(GPIO35, AF5)
250#define GPIO35_SSP1_RXD MFP_CFG(GPIO35, AF4)
251#define GPIO36_SSP1_TXD MFP_CFG(GPIO36, AF5)
252#define GPIO36_SSP1_RXD MFP_CFG(GPIO36, AF6)
253#define GPIO87_SSP1_TXD MFP_CFG(GPIO87, AF1)
254#define GPIO87_SSP1_RXD MFP_CFG(GPIO87, AF6)
255#define GPIO88_SSP1_TXD MFP_CFG(GPIO88, AF6)
256#define GPIO88_SSP1_RXD MFP_CFG(GPIO88, AF1)
257
258/* SSP2 */
259#define GPIO29_SSP2_EXTCLK MFP_CFG(GPIO29, AF2)
260#define GPIO23_SSP2_SCLK MFP_CFG(GPIO23, AF2)
261#define GPIO17_SSP2_FRM MFP_CFG(GPIO17, AF2)
262#define GPIO25_SSP2_SCLK MFP_CFG(GPIO25, AF2)
263#define GPIO26_SSP2_FRM MFP_CFG(GPIO26, AF2)
264#define GPIO33_SSP2_SCLK MFP_CFG(GPIO33, AF6)
265#define GPIO34_SSP2_FRM MFP_CFG(GPIO34, AF6)
266#define GPIO64_SSP2_SCLK MFP_CFG(GPIO64, AF2)
267#define GPIO65_SSP2_FRM MFP_CFG(GPIO65, AF2)
268#define GPIO19_SSP2_TXD MFP_CFG(GPIO19, AF2)
269#define GPIO19_SSP2_RXD MFP_CFG(GPIO19, AF7)
270#define GPIO24_SSP2_TXD MFP_CFG(GPIO24, AF5)
271#define GPIO24_SSP2_RXD MFP_CFG(GPIO24, AF4)
272#define GPIO27_SSP2_TXD MFP_CFG(GPIO27, AF2)
273#define GPIO27_SSP2_RXD MFP_CFG(GPIO27, AF5)
274#define GPIO28_SSP2_TXD MFP_CFG(GPIO28, AF5)
275#define GPIO28_SSP2_RXD MFP_CFG(GPIO28, AF2)
276#define GPIO35_SSP2_TXD MFP_CFG(GPIO35, AF7)
277#define GPIO35_SSP2_RXD MFP_CFG(GPIO35, AF6)
278#define GPIO66_SSP2_TXD MFP_CFG(GPIO66, AF4)
279#define GPIO66_SSP2_RXD MFP_CFG(GPIO66, AF2)
280#define GPIO67_SSP2_TXD MFP_CFG(GPIO67, AF2)
281#define GPIO67_SSP2_RXD MFP_CFG(GPIO67, AF4)
282#define GPIO36_SSP2_TXD MFP_CFG(GPIO36, AF7)
283
284/* SSP3 */
285#define GPIO69_SSP3_FRM MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW)
286#define GPIO68_SSP3_SCLK MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT)
287#define GPIO92_SSP3_FRM MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW)
288#define GPIO91_SSP3_SCLK MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT)
289#define GPIO70_SSP3_TXD MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW)
290#define GPIO70_SSP3_RXD MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT)
291#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW)
292#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT)
293#define GPIO93_SSP3_TXD MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW)
294#define GPIO93_SSP3_RXD MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT)
295#define GPIO94_SSP3_TXD MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW)
296#define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT)
297
298/* SSP4 */
299#define GPIO95_SSP4_SCLK MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
300#define GPIO96_SSP4_FRM MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
301#define GPIO97_SSP4_TXD MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH)
302#define GPIO97_SSP4_RXD MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH)
303#define GPIO98_SSP4_TXD MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH)
304#define GPIO98_SSP4_RXD MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH)
305
306/* UART1 */
307#define GPIO32_UART1_CTS MFP_CFG_LPM(GPIO32, AF2, FLOAT)
308#define GPIO37_UART1_CTS MFP_CFG_LPM(GPIO37, AF4, FLOAT)
309#define GPIO79_UART1_CTS MFP_CFG_LPM(GPIO79, AF1, FLOAT)
310#define GPIO84_UART1_CTS MFP_CFG_LPM(GPIO84, AF3, FLOAT)
311#define GPIO101_UART1_CTS MFP_CFG_LPM(GPIO101, AF1, FLOAT)
312#define GPIO106_UART1_CTS MFP_CFG_LPM(GPIO106, AF6, FLOAT)
313
314#define GPIO32_UART1_RTS MFP_CFG_LPM(GPIO32, AF4, FLOAT)
315#define GPIO37_UART1_RTS MFP_CFG_LPM(GPIO37, AF2, FLOAT)
316#define GPIO79_UART1_RTS MFP_CFG_LPM(GPIO79, AF3, FLOAT)
317#define GPIO84_UART1_RTS MFP_CFG_LPM(GPIO84, AF1, FLOAT)
318#define GPIO101_UART1_RTS MFP_CFG_LPM(GPIO101, AF6, FLOAT)
319#define GPIO106_UART1_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT)
320
321#define GPIO34_UART1_DSR MFP_CFG_LPM(GPIO34, AF2, FLOAT)
322#define GPIO36_UART1_DSR MFP_CFG_LPM(GPIO36, AF4, FLOAT)
323#define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF1, FLOAT)
324#define GPIO83_UART1_DSR MFP_CFG_LPM(GPIO83, AF3, FLOAT)
325#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF1, FLOAT)
326#define GPIO105_UART1_DSR MFP_CFG_LPM(GPIO105, AF6, FLOAT)
327
328#define GPIO34_UART1_DTR MFP_CFG_LPM(GPIO34, AF4, FLOAT)
329#define GPIO36_UART1_DTR MFP_CFG_LPM(GPIO36, AF2, FLOAT)
330#define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF3, FLOAT)
331#define GPIO83_UART1_DTR MFP_CFG_LPM(GPIO83, AF1, FLOAT)
332#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF6, FLOAT)
333#define GPIO105_UART1_DTR MFP_CFG_LPM(GPIO105, AF1, FLOAT)
334
335#define GPIO35_UART1_RI MFP_CFG_LPM(GPIO35, AF2, FLOAT)
336#define GPIO82_UART1_RI MFP_CFG_LPM(GPIO82, AF1, FLOAT)
337#define GPIO104_UART1_RI MFP_CFG_LPM(GPIO104, AF1, FLOAT)
338
339#define GPIO33_UART1_DCD MFP_CFG_LPM(GPIO33, AF2, FLOAT)
340#define GPIO80_UART1_DCD MFP_CFG_LPM(GPIO80, AF1, FLOAT)
341#define GPIO102_UART1_DCD MFP_CFG_LPM(GPIO102, AF1, FLOAT)
342
343#define GPIO30_UART1_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT)
344#define GPIO31_UART1_RXD MFP_CFG_LPM(GPIO31, AF4, FLOAT)
345#define GPIO77_UART1_RXD MFP_CFG_LPM(GPIO77, AF1, FLOAT)
346#define GPIO78_UART1_RXD MFP_CFG_LPM(GPIO78, AF3, FLOAT)
347#define GPIO99_UART1_RXD MFP_CFG_LPM(GPIO99, AF1, FLOAT)
348#define GPIO100_UART1_RXD MFP_CFG_LPM(GPIO100, AF6, FLOAT)
349#define GPIO102_UART1_RXD MFP_CFG_LPM(GPIO102, AF6, FLOAT)
350#define GPIO104_UART1_RXD MFP_CFG_LPM(GPIO104, AF4, FLOAT)
351
352#define GPIO30_UART1_TXD MFP_CFG_LPM(GPIO30, AF4, FLOAT)
353#define GPIO31_UART1_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT)
354#define GPIO77_UART1_TXD MFP_CFG_LPM(GPIO77, AF3, FLOAT)
355#define GPIO78_UART1_TXD MFP_CFG_LPM(GPIO78, AF1, FLOAT)
356#define GPIO99_UART1_TXD MFP_CFG_LPM(GPIO99, AF6, FLOAT)
357#define GPIO100_UART1_TXD MFP_CFG_LPM(GPIO100, AF1, FLOAT)
358#define GPIO102_UART1_TXD MFP_CFG_LPM(GPIO102, AF4, FLOAT)
359
360/* UART2 */
361#define GPIO15_UART2_CTS MFP_CFG_LPM(GPIO15, AF3, FLOAT)
362#define GPIO16_UART2_CTS MFP_CFG_LPM(GPIO16, AF5, FLOAT)
363#define GPIO111_UART2_CTS MFP_CFG_LPM(GPIO111, AF3, FLOAT)
364#define GPIO114_UART2_CTS MFP_CFG_LPM(GPIO114, AF1, FLOAT)
365
366#define GPIO15_UART2_RTS MFP_CFG_LPM(GPIO15, AF4, FLOAT)
367#define GPIO16_UART2_RTS MFP_CFG_LPM(GPIO16, AF4, FLOAT)
368#define GPIO114_UART2_RTS MFP_CFG_LPM(GPIO114, AF3, FLOAT)
369#define GPIO111_UART2_RTS MFP_CFG_LPM(GPIO111, AF1, FLOAT)
370
371#define GPIO18_UART2_RXD MFP_CFG_LPM(GPIO18, AF5, FLOAT)
372#define GPIO19_UART2_RXD MFP_CFG_LPM(GPIO19, AF4, FLOAT)
373#define GPIO112_UART2_RXD MFP_CFG_LPM(GPIO112, AF1, FLOAT)
374#define GPIO113_UART2_RXD MFP_CFG_LPM(GPIO113, AF3, FLOAT)
375
376#define GPIO18_UART2_TXD MFP_CFG_LPM(GPIO18, AF4, FLOAT)
377#define GPIO19_UART2_TXD MFP_CFG_LPM(GPIO19, AF5, FLOAT)
378#define GPIO112_UART2_TXD MFP_CFG_LPM(GPIO112, AF3, FLOAT)
379#define GPIO113_UART2_TXD MFP_CFG_LPM(GPIO113, AF1, FLOAT)
380
381/* UART3 */
382#define GPIO91_UART3_CTS MFP_CFG_LPM(GPIO91, AF2, FLOAT)
383#define GPIO92_UART3_CTS MFP_CFG_LPM(GPIO92, AF4, FLOAT)
384#define GPIO107_UART3_CTS MFP_CFG_LPM(GPIO107, AF1, FLOAT)
385#define GPIO108_UART3_CTS MFP_CFG_LPM(GPIO108, AF3, FLOAT)
386
387#define GPIO91_UART3_RTS MFP_CFG_LPM(GPIO91, AF4, FLOAT)
388#define GPIO92_UART3_RTS MFP_CFG_LPM(GPIO92, AF2, FLOAT)
389#define GPIO107_UART3_RTS MFP_CFG_LPM(GPIO107, AF3, FLOAT)
390#define GPIO108_UART3_RTS MFP_CFG_LPM(GPIO108, AF1, FLOAT)
391
392#define GPIO7_UART3_RXD MFP_CFG_LPM(GPIO7, AF2, FLOAT)
393#define GPIO8_UART3_RXD MFP_CFG_LPM(GPIO8, AF6, FLOAT)
394#define GPIO93_UART3_RXD MFP_CFG_LPM(GPIO93, AF4, FLOAT)
395#define GPIO94_UART3_RXD MFP_CFG_LPM(GPIO94, AF2, FLOAT)
396#define GPIO109_UART3_RXD MFP_CFG_LPM(GPIO109, AF3, FLOAT)
397#define GPIO110_UART3_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT)
398
399#define GPIO7_UART3_TXD MFP_CFG_LPM(GPIO7, AF6, FLOAT)
400#define GPIO8_UART3_TXD MFP_CFG_LPM(GPIO8, AF2, FLOAT)
401#define GPIO93_UART3_TXD MFP_CFG_LPM(GPIO93, AF2, FLOAT)
402#define GPIO94_UART3_TXD MFP_CFG_LPM(GPIO94, AF4, FLOAT)
403#define GPIO109_UART3_TXD MFP_CFG_LPM(GPIO109, AF1, FLOAT)
404#define GPIO110_UART3_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT)
405
406/* USB Host */
407#define GPIO0_2_USBH_PEN MFP_CFG(GPIO0_2, AF1)
408#define GPIO1_2_USBH_PWR MFP_CFG(GPIO1_2, AF1)
409
410/* USB P3 */
411#define GPIO77_USB_P3_1 MFP_CFG(GPIO77, AF2)
412#define GPIO78_USB_P3_2 MFP_CFG(GPIO78, AF2)
413#define GPIO79_USB_P3_3 MFP_CFG(GPIO79, AF2)
414#define GPIO80_USB_P3_4 MFP_CFG(GPIO80, AF2)
415#define GPIO81_USB_P3_5 MFP_CFG(GPIO81, AF2)
416#define GPIO82_USB_P3_6 MFP_CFG(GPIO82, AF2)
417
418/* PWM */
419#define GPIO17_PWM0_OUT MFP_CFG(GPIO17, AF1)
420#define GPIO18_PWM1_OUT MFP_CFG(GPIO18, AF1)
421#define GPIO19_PWM2_OUT MFP_CFG(GPIO19, AF1)
422#define GPIO20_PWM3_OUT MFP_CFG(GPIO20, AF1)
423
424/* CIR */
425#define GPIO8_CIR_OUT MFP_CFG(GPIO8, AF5)
426#define GPIO16_CIR_OUT MFP_CFG(GPIO16, AF3)
427
428#define GPIO20_OW_DQ_IN MFP_CFG(GPIO20, AF5)
429#define GPIO126_OW_DQ MFP_CFG(GPIO126, AF2)
430
431#define GPIO0_DF_RDY MFP_CFG(GPIO0, AF1)
432#define GPIO7_CLK_BYPASS_XSC MFP_CFG(GPIO7, AF7)
433#define GPIO17_EXT_SYNC_MVT_0 MFP_CFG(GPIO17, AF6)
434#define GPIO18_EXT_SYNC_MVT_1 MFP_CFG(GPIO18, AF6)
435#define GPIO19_OST_CHOUT_MVT_0 MFP_CFG(GPIO19, AF6)
436#define GPIO20_OST_CHOUT_MVT_1 MFP_CFG(GPIO20, AF6)
437#define GPIO49_48M_CLK MFP_CFG(GPIO49, AF2)
438#define GPIO126_EXT_CLK MFP_CFG(GPIO126, AF3)
439#define GPIO127_CLK_BYPASS_GB MFP_CFG(GPIO127, AF7)
440#define GPIO71_EXT_MATCH_MVT MFP_CFG(GPIO71, AF6)
441
442#define GPIO3_uIO_IN MFP_CFG(GPIO3, AF1)
443
444#define GPIO4_uSIM_CARD_STATE MFP_CFG(GPIO4, AF1)
445#define GPIO5_uSIM_uCLK MFP_CFG(GPIO5, AF1)
446#define GPIO6_uSIM_uRST MFP_CFG(GPIO6, AF1)
447#define GPIO16_uSIM_UVS_0 MFP_CFG(GPIO16, AF1)
448
449#define GPIO9_SCIO MFP_CFG(GPIO9, AF1)
450#define GPIO20_RTC_MVT MFP_CFG(GPIO20, AF4)
451#define GPIO126_RTC_MVT MFP_CFG(GPIO126, AF1)
452
453/*
454 * PXA300 specific MFP configurations
455 */
456#ifdef CONFIG_CPU_PXA300
457#define GPIO99_USB_P2_2 MFP_CFG(GPIO99, AF2)
458#define GPIO99_USB_P2_5 MFP_CFG(GPIO99, AF3)
459#define GPIO99_USB_P2_6 MFP_CFG(GPIO99, AF4)
460#define GPIO100_USB_P2_2 MFP_CFG(GPIO100, AF4)
461#define GPIO100_USB_P2_5 MFP_CFG(GPIO100, AF5)
462#define GPIO101_USB_P2_1 MFP_CFG(GPIO101, AF2)
463#define GPIO102_USB_P2_4 MFP_CFG(GPIO102, AF2)
464#define GPIO104_USB_P2_3 MFP_CFG(GPIO104, AF2)
465#define GPIO105_USB_P2_5 MFP_CFG(GPIO105, AF2)
466#define GPIO100_USB_P2_6 MFP_CFG(GPIO100, AF2)
467#define GPIO106_USB_P2_7 MFP_CFG(GPIO106, AF2)
468#define GPIO103_USB_P2_8 MFP_CFG(GPIO103, AF2)
469
470/* U2D UTMI */
471#define GPIO38_UTM_CLK MFP_CFG(GPIO38, AF1)
472#define GPIO26_U2D_RXERROR MFP_CFG(GPIO26, AF3)
473#define GPIO50_U2D_RXERROR MFP_CFG(GPIO50, AF1)
474#define GPIO89_U2D_RXERROR MFP_CFG(GPIO89, AF5)
475#define GPIO24_UTM_RXVALID MFP_CFG(GPIO24, AF3)
476#define GPIO48_UTM_RXVALID MFP_CFG(GPIO48, AF2)
477#define GPIO87_UTM_RXVALID MFP_CFG(GPIO87, AF5)
478#define GPIO25_UTM_RXACTIVE MFP_CFG(GPIO25, AF3)
479#define GPIO47_UTM_RXACTIVE MFP_CFG(GPIO47, AF2)
480#define GPIO49_UTM_RXACTIVE MFP_CFG(GPIO49, AF1)
481#define GPIO88_UTM_RXACTIVE MFP_CFG(GPIO88, AF5)
482#define GPIO53_UTM_TXREADY MFP_CFG(GPIO53, AF1)
483#define GPIO67_UTM_LINESTATE_0 MFP_CFG(GPIO67, AF3)
484#define GPIO92_UTM_LINESTATE_0 MFP_CFG(GPIO92, AF3)
485#define GPIO104_UTM_LINESTATE_0 MFP_CFG(GPIO104, AF3)
486#define GPIO109_UTM_LINESTATE_0 MFP_CFG(GPIO109, AF4)
487#define GPIO68_UTM_LINESTATE_1 MFP_CFG(GPIO68, AF3)
488#define GPIO93_UTM_LINESTATE_1 MFP_CFG(GPIO93, AF3)
489#define GPIO105_UTM_LINESTATE_1 MFP_CFG(GPIO105, AF3)
490#define GPIO27_U2D_OPMODE_0 MFP_CFG(GPIO27, AF4)
491#define GPIO51_U2D_OPMODE_0 MFP_CFG(GPIO51, AF2)
492#define GPIO90_U2D_OPMODE_0 MFP_CFG(GPIO90, AF7)
493#define GPIO28_U2D_OPMODE_1 MFP_CFG(GPIO28, AF4)
494#define GPIO52_U2D_OPMODE_1 MFP_CFG(GPIO52, AF2)
495#define GPIO106_U2D_OPMODE_1 MFP_CFG(GPIO106, AF3)
496#define GPIO110_U2D_OPMODE_1 MFP_CFG(GPIO110, AF5)
497#define GPIO76_U2D_RESET MFP_CFG(GPIO76, AF1)
498#define GPIO95_U2D_RESET MFP_CFG(GPIO95, AF2)
499#define GPIO100_U2D_RESET MFP_CFG(GPIO100, AF3)
500#define GPIO66_U2D_SUSPEND MFP_CFG(GPIO66, AF3)
501#define GPIO98_U2D_SUSPEND MFP_CFG(GPIO98, AF2)
502#define GPIO103_U2D_SUSPEND MFP_CFG(GPIO103, AF3)
503#define GPIO65_U2D_TERM_SEL MFP_CFG(GPIO65, AF5)
504#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF3)
505#define GPIO102_U2D_TERM_SEL MFP_CFG(GPIO102, AF5)
506#define GPIO29_U2D_TXVALID MFP_CFG(GPIO29, AF3)
507#define GPIO52_U2D_TXVALID MFP_CFG(GPIO52, AF4)
508#define GPIO69_U2D_TXVALID MFP_CFG(GPIO69, AF3)
509#define GPIO85_U2D_TXVALID MFP_CFG(GPIO85, AF7)
510#define GPIO64_U2D_XCVR_SEL MFP_CFG(GPIO64, AF5)
511#define GPIO96_U2D_XCVR_SEL MFP_CFG(GPIO96, AF3)
512#define GPIO101_U2D_XCVR_SEL MFP_CFG(GPIO101, AF5)
513#define GPIO30_UTM_PHYDATA_0 MFP_CFG(GPIO30, AF3)
514#define GPIO31_UTM_PHYDATA_1 MFP_CFG(GPIO31, AF3)
515#define GPIO32_UTM_PHYDATA_2 MFP_CFG(GPIO32, AF3)
516#define GPIO33_UTM_PHYDATA_3 MFP_CFG(GPIO33, AF3)
517#define GPIO34_UTM_PHYDATA_4 MFP_CFG(GPIO34, AF3)
518#define GPIO35_UTM_PHYDATA_5 MFP_CFG(GPIO35, AF3)
519#define GPIO36_UTM_PHYDATA_6 MFP_CFG(GPIO36, AF3)
520#define GPIO37_UTM_PHYDATA_7 MFP_CFG(GPIO37, AF3)
521#define GPIO39_UTM_PHYDATA_0 MFP_CFG(GPIO39, AF3)
522#define GPIO40_UTM_PHYDATA_1 MFP_CFG(GPIO40, AF3)
523#define GPIO41_UTM_PHYDATA_2 MFP_CFG(GPIO41, AF3)
524#define GPIO42_UTM_PHYDATA_3 MFP_CFG(GPIO42, AF3)
525#define GPIO43_UTM_PHYDATA_4 MFP_CFG(GPIO43, AF3)
526#define GPIO44_UTM_PHYDATA_5 MFP_CFG(GPIO44, AF3)
527#define GPIO45_UTM_PHYDATA_6 MFP_CFG(GPIO45, AF3)
528#define GPIO46_UTM_PHYDATA_7 MFP_CFG(GPIO46, AF3)
529#endif /* CONFIG_CPU_PXA300 */
530
531/*
532 * PXA310 specific MFP configurations
533 */
534#ifdef CONFIG_CPU_PXA310
535/* USB P2 */
536#define GPIO36_USB_P2_1 MFP_CFG(GPIO36, AF1)
537#define GPIO30_USB_P2_2 MFP_CFG(GPIO30, AF1)
538#define GPIO35_USB_P2_3 MFP_CFG(GPIO35, AF1)
539#define GPIO32_USB_P2_4 MFP_CFG(GPIO32, AF1)
540#define GPIO34_USB_P2_5 MFP_CFG(GPIO34, AF1)
541#define GPIO31_USB_P2_6 MFP_CFG(GPIO31, AF1)
542
543/* MMC1 */
544#define GPIO24_MMC1_CMD MFP_CFG(GPIO24, AF3)
545#define GPIO29_MMC1_DAT0 MFP_CFG(GPIO29, AF3)
546
547/* MMC3 */
548#define GPIO103_MMC3_CLK MFP_CFG(GPIO103, AF2)
549#define GPIO105_MMC3_CMD MFP_CFG(GPIO105, AF2)
550#define GPIO11_2_MMC3_CLK MFP_CFG(GPIO11_2, AF1)
551#define GPIO12_2_MMC3_CMD MFP_CFG(GPIO12_2, AF1)
552#define GPIO7_2_MMC3_DAT0 MFP_CFG(GPIO7_2, AF1)
553#define GPIO8_2_MMC3_DAT1 MFP_CFG(GPIO8_2, AF1)
554#define GPIO9_2_MMC3_DAT2 MFP_CFG(GPIO9_2, AF1)
555#define GPIO10_2_MMC3_DAT3 MFP_CFG(GPIO10_2, AF1)
556
557/* ULPI */
558#define GPIO38_ULPI_CLK MFP_CFG(GPIO38, AF1)
559#define GPIO30_ULPI_DATA_OUT_0 MFP_CFG(GPIO30, AF3)
560#define GPIO31_ULPI_DATA_OUT_1 MFP_CFG(GPIO31, AF3)
561#define GPIO32_ULPI_DATA_OUT_2 MFP_CFG(GPIO32, AF3)
562#define GPIO33_ULPI_DATA_OUT_3 MFP_CFG(GPIO33, AF3)
563#define GPIO34_ULPI_DATA_OUT_4 MFP_CFG(GPIO34, AF3)
564#define GPIO35_ULPI_DATA_OUT_5 MFP_CFG(GPIO35, AF3)
565#define GPIO36_ULPI_DATA_OUT_6 MFP_CFG(GPIO36, AF3)
566#define GPIO37_ULPI_DATA_OUT_7 MFP_CFG(GPIO37, AF3)
567#define GPIO33_ULPI_OTG_INTR MFP_CFG(GPIO33, AF1)
568
569#define ULPI_DIR MFP_CFG_DRV(ULPI_DIR, MFP_AF0, MFP_DS01X)
570#define ULPI_NXT MFP_CFG_DRV(ULPI_NXT, MFP_AF0, MFP_DS01X)
571#define ULPI_STP MFP_CFG_DRV(ULPI_STP, MFP_AF0, MFP_DS01X)
572#endif /* CONFIG_CPU_PXA310 */
573
574#endif /* __ASM_ARCH_MFP_PXA300_H */
diff --git a/include/asm-arm/arch-pxa/mfp-pxa320.h b/include/asm-arm/arch-pxa/mfp-pxa320.h
new file mode 100644
index 000000000000..ae8ba34194cf
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp-pxa320.h
@@ -0,0 +1,446 @@
1/*
2 * linux/include/asm-arm/arch-pxa/mfp-pxa320.h
3 *
4 * PXA320 specific MFP configuration definitions
5 *
6 * Copyright (C) 2007 Marvell International Ltd.
7 * 2007-08-21: eric miao <eric.y.miao@gmail.com>
8 * initial version
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef __ASM_ARCH_MFP_PXA320_H
16#define __ASM_ARCH_MFP_PXA320_H
17
18#include <asm/arch/mfp.h>
19
20/* GPIO */
21#define GPIO46_GPIO MFP_CFG(GPIO6, AF0)
22#define GPIO49_GPIO MFP_CFG(GPIO49, AF0)
23#define GPIO50_GPIO MFP_CFG(GPIO50, AF0)
24#define GPIO51_GPIO MFP_CFG(GPIO51, AF0)
25#define GPIO52_GPIO MFP_CFG(GPIO52, AF0)
26
27#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0)
28#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0)
29#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0)
30#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0)
31#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0)
32#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0)
33#define GPIO13_2_GPIO MFP_CFG(GPIO13_2, AF0)
34#define GPIO14_2_GPIO MFP_CFG(GPIO14_2, AF0)
35#define GPIO15_2_GPIO MFP_CFG(GPIO15_2, AF0)
36#define GPIO16_2_GPIO MFP_CFG(GPIO16_2, AF0)
37#define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0)
38
39/* Chip Select */
40#define GPIO4_nCS3 MFP_CFG(GPIO4, AF1)
41
42/* AC97 */
43#define GPIO34_AC97_SYSCLK MFP_CFG(GPIO34, AF1)
44#define GPIO39_AC97_BITCLK MFP_CFG(GPIO39, AF1)
45#define GPIO40_AC97_nACRESET MFP_CFG(GPIO40, AF1)
46#define GPIO35_AC97_SDATA_IN_0 MFP_CFG(GPIO35, AF1)
47#define GPIO36_AC97_SDATA_IN_1 MFP_CFG(GPIO36, AF1)
48#define GPIO32_AC97_SDATA_IN_2 MFP_CFG(GPIO32, AF2)
49#define GPIO33_AC97_SDATA_IN_3 MFP_CFG(GPIO33, AF2)
50#define GPIO11_AC97_SDATA_IN_2 MFP_CFG(GPIO11, AF3)
51#define GPIO12_AC97_SDATA_IN_3 MFP_CFG(GPIO12, AF3)
52#define GPIO37_AC97_SDATA_OUT MFP_CFG(GPIO37, AF1)
53#define GPIO38_AC97_SYNC MFP_CFG(GPIO38, AF1)
54
55/* I2C */
56#define GPIO32_I2C_SCL MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH)
57#define GPIO33_I2C_SDA MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH)
58
59/* QCI */
60#define GPIO49_CI_DD_0 MFP_CFG_DRV(GPIO49, AF1, DS04X)
61#define GPIO50_CI_DD_1 MFP_CFG_DRV(GPIO50, AF1, DS04X)
62#define GPIO51_CI_DD_2 MFP_CFG_DRV(GPIO51, AF1, DS04X)
63#define GPIO52_CI_DD_3 MFP_CFG_DRV(GPIO52, AF1, DS04X)
64#define GPIO53_CI_DD_4 MFP_CFG_DRV(GPIO53, AF1, DS04X)
65#define GPIO54_CI_DD_5 MFP_CFG_DRV(GPIO54, AF1, DS04X)
66#define GPIO55_CI_DD_6 MFP_CFG_DRV(GPIO55, AF1, DS04X)
67#define GPIO56_CI_DD_7 MFP_CFG_DRV(GPIO56, AF0, DS04X)
68#define GPIO57_CI_DD_8 MFP_CFG_DRV(GPIO57, AF1, DS04X)
69#define GPIO58_CI_DD_9 MFP_CFG_DRV(GPIO58, AF1, DS04X)
70#define GPIO59_CI_MCLK MFP_CFG_DRV(GPIO59, AF0, DS04X)
71#define GPIO60_CI_PCLK MFP_CFG_DRV(GPIO60, AF0, DS04X)
72#define GPIO61_CI_HSYNC MFP_CFG_DRV(GPIO61, AF0, DS04X)
73#define GPIO62_CI_VSYNC MFP_CFG_DRV(GPIO62, AF0, DS04X)
74
75#define GPIO31_CIR_OUT MFP_CFG(GPIO31, AF5)
76
77#define GPIO0_2_CLK_EXT MFP_CFG(GPIO0_2, AF3)
78#define GPIO0_DRQ MFP_CFG(GPIO0, AF2)
79#define GPIO11_EXT_SYNC0 MFP_CFG(GPIO11, AF5)
80#define GPIO12_EXT_SYNC1 MFP_CFG(GPIO12, AF6)
81#define GPIO0_2_HZ_CLK MFP_CFG(GPIO0_2, AF1)
82#define GPIO14_HZ_CLK MFP_CFG(GPIO14, AF4)
83#define GPIO30_ICP_RXD MFP_CFG(GPIO30, AF1)
84#define GPIO31_ICP_TXD MFP_CFG(GPIO31, AF1)
85
86#define GPIO83_KP_DKIN_0 MFP_CFG_LPM(GPIO83, AF3, FLOAT)
87#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF3, FLOAT)
88#define GPIO85_KP_DKIN_2 MFP_CFG_LPM(GPIO85, AF3, FLOAT)
89#define GPIO86_KP_DKIN_3 MFP_CFG_LPM(GPIO86, AF3, FLOAT)
90
91#define GPIO105_KP_DKIN_0 MFP_CFG_LPM(GPIO105, AF2, FLOAT)
92#define GPIO106_KP_DKIN_1 MFP_CFG_LPM(GPIO106, AF2, FLOAT)
93#define GPIO107_KP_DKIN_2 MFP_CFG_LPM(GPIO107, AF2, FLOAT)
94#define GPIO108_KP_DKIN_3 MFP_CFG_LPM(GPIO108, AF2, FLOAT)
95#define GPIO109_KP_DKIN_4 MFP_CFG_LPM(GPIO109, AF2, FLOAT)
96#define GPIO110_KP_DKIN_5 MFP_CFG_LPM(GPIO110, AF2, FLOAT)
97#define GPIO111_KP_DKIN_6 MFP_CFG_LPM(GPIO111, AF2, FLOAT)
98#define GPIO112_KP_DKIN_7 MFP_CFG_LPM(GPIO112, AF2, FLOAT)
99
100#define GPIO113_KP_DKIN_0 MFP_CFG_LPM(GPIO113, AF2, FLOAT)
101#define GPIO114_KP_DKIN_1 MFP_CFG_LPM(GPIO114, AF2, FLOAT)
102#define GPIO115_KP_DKIN_2 MFP_CFG_LPM(GPIO115, AF2, FLOAT)
103#define GPIO116_KP_DKIN_3 MFP_CFG_LPM(GPIO116, AF2, FLOAT)
104#define GPIO117_KP_DKIN_4 MFP_CFG_LPM(GPIO117, AF2, FLOAT)
105#define GPIO118_KP_DKIN_5 MFP_CFG_LPM(GPIO118, AF2, FLOAT)
106#define GPIO119_KP_DKIN_6 MFP_CFG_LPM(GPIO119, AF2, FLOAT)
107#define GPIO120_KP_DKIN_7 MFP_CFG_LPM(GPIO120, AF2, FLOAT)
108
109#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF2, FLOAT)
110#define GPIO126_KP_DKIN_1 MFP_CFG_LPM(GPIO126, AF2, FLOAT)
111
112#define GPIO2_2_KP_DKIN_0 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT)
113#define GPIO3_2_KP_DKIN_1 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT)
114#define GPIO125_KP_DKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT)
115#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT)
116#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT)
117#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT)
118#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT)
119#define GPIO4_2_KP_DKIN_7 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT)
120
121#define GPIO113_KP_MKIN_0 MFP_CFG_LPM(GPIO113, AF1, FLOAT)
122#define GPIO114_KP_MKIN_1 MFP_CFG_LPM(GPIO114, AF1, FLOAT)
123#define GPIO115_KP_MKIN_2 MFP_CFG_LPM(GPIO115, AF1, FLOAT)
124#define GPIO116_KP_MKIN_3 MFP_CFG_LPM(GPIO116, AF1, FLOAT)
125#define GPIO117_KP_MKIN_4 MFP_CFG_LPM(GPIO117, AF1, FLOAT)
126#define GPIO118_KP_MKIN_5 MFP_CFG_LPM(GPIO118, AF1, FLOAT)
127#define GPIO119_KP_MKIN_6 MFP_CFG_LPM(GPIO119, AF1, FLOAT)
128#define GPIO120_KP_MKIN_7 MFP_CFG_LPM(GPIO120, AF1, FLOAT)
129
130#define GPIO83_KP_MKOUT_0 MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH)
131#define GPIO84_KP_MKOUT_1 MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH)
132#define GPIO85_KP_MKOUT_2 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH)
133#define GPIO86_KP_MKOUT_3 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH)
134#define GPIO13_KP_MKOUT_4 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH)
135#define GPIO14_KP_MKOUT_5 MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH)
136
137#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH)
138#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH)
139#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH)
140#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH)
141#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH)
142#define GPIO126_KP_MKOUT_5 MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH)
143#define GPIO127_KP_MKOUT_6 MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH)
144#define GPIO5_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH)
145
146/* LCD */
147#define GPIO6_2_LCD_LDD_0 MFP_CFG_DRV(GPIO6_2, AF1, DS01X)
148#define GPIO7_2_LCD_LDD_1 MFP_CFG_DRV(GPIO7_2, AF1, DS01X)
149#define GPIO8_2_LCD_LDD_2 MFP_CFG_DRV(GPIO8_2, AF1, DS01X)
150#define GPIO9_2_LCD_LDD_3 MFP_CFG_DRV(GPIO9_2, AF1, DS01X)
151#define GPIO10_2_LCD_LDD_4 MFP_CFG_DRV(GPIO10_2, AF1, DS01X)
152#define GPIO11_2_LCD_LDD_5 MFP_CFG_DRV(GPIO11_2, AF1, DS01X)
153#define GPIO12_2_LCD_LDD_6 MFP_CFG_DRV(GPIO12_2, AF1, DS01X)
154#define GPIO13_2_LCD_LDD_7 MFP_CFG_DRV(GPIO13_2, AF1, DS01X)
155#define GPIO63_LCD_LDD_8 MFP_CFG_DRV(GPIO63, AF1, DS01X)
156#define GPIO64_LCD_LDD_9 MFP_CFG_DRV(GPIO64, AF1, DS01X)
157#define GPIO65_LCD_LDD_10 MFP_CFG_DRV(GPIO65, AF1, DS01X)
158#define GPIO66_LCD_LDD_11 MFP_CFG_DRV(GPIO66, AF1, DS01X)
159#define GPIO67_LCD_LDD_12 MFP_CFG_DRV(GPIO67, AF1, DS01X)
160#define GPIO68_LCD_LDD_13 MFP_CFG_DRV(GPIO68, AF1, DS01X)
161#define GPIO69_LCD_LDD_14 MFP_CFG_DRV(GPIO69, AF1, DS01X)
162#define GPIO70_LCD_LDD_15 MFP_CFG_DRV(GPIO70, AF1, DS01X)
163#define GPIO71_LCD_LDD_16 MFP_CFG_DRV(GPIO71, AF1, DS01X)
164#define GPIO72_LCD_LDD_17 MFP_CFG_DRV(GPIO72, AF1, DS01X)
165#define GPIO73_LCD_CS_N MFP_CFG_DRV(GPIO73, AF2, DS01X)
166#define GPIO74_LCD_VSYNC MFP_CFG_DRV(GPIO74, AF2, DS01X)
167#define GPIO14_2_LCD_FCLK MFP_CFG_DRV(GPIO14_2, AF1, DS01X)
168#define GPIO15_2_LCD_LCLK MFP_CFG_DRV(GPIO15_2, AF1, DS01X)
169#define GPIO16_2_LCD_PCLK MFP_CFG_DRV(GPIO16_2, AF1, DS01X)
170#define GPIO17_2_LCD_BIAS MFP_CFG_DRV(GPIO17_2, AF1, DS01X)
171#define GPIO64_LCD_VSYNC MFP_CFG_DRV(GPIO64, AF2, DS01X)
172#define GPIO63_LCD_CS_N MFP_CFG_DRV(GPIO63, AF2, DS01X)
173
174#define GPIO6_2_MLCD_DD_0 MFP_CFG_DRV(GPIO6_2, AF7, DS08X)
175#define GPIO7_2_MLCD_DD_1 MFP_CFG_DRV(GPIO7_2, AF7, DS08X)
176#define GPIO8_2_MLCD_DD_2 MFP_CFG_DRV(GPIO8_2, AF7, DS08X)
177#define GPIO9_2_MLCD_DD_3 MFP_CFG_DRV(GPIO9_2, AF7, DS08X)
178#define GPIO10_2_MLCD_DD_4 MFP_CFG_DRV(GPIO10_2, AF7, DS08X)
179#define GPIO11_2_MLCD_DD_5 MFP_CFG_DRV(GPIO11_2, AF7, DS08X)
180#define GPIO12_2_MLCD_DD_6 MFP_CFG_DRV(GPIO12_2, AF7, DS08X)
181#define GPIO13_2_MLCD_DD_7 MFP_CFG_DRV(GPIO13_2, AF7, DS08X)
182#define GPIO63_MLCD_DD_8 MFP_CFG_DRV(GPIO63, AF7, DS08X)
183#define GPIO64_MLCD_DD_9 MFP_CFG_DRV(GPIO64, AF7, DS08X)
184#define GPIO65_MLCD_DD_10 MFP_CFG_DRV(GPIO65, AF7, DS08X)
185#define GPIO66_MLCD_DD_11 MFP_CFG_DRV(GPIO66, AF7, DS08X)
186#define GPIO67_MLCD_DD_12 MFP_CFG_DRV(GPIO67, AF7, DS08X)
187#define GPIO68_MLCD_DD_13 MFP_CFG_DRV(GPIO68, AF7, DS08X)
188#define GPIO69_MLCD_DD_14 MFP_CFG_DRV(GPIO69, AF7, DS08X)
189#define GPIO70_MLCD_DD_15 MFP_CFG_DRV(GPIO70, AF7, DS08X)
190#define GPIO71_MLCD_DD_16 MFP_CFG_DRV(GPIO71, AF7, DS08X)
191#define GPIO72_MLCD_DD_17 MFP_CFG_DRV(GPIO72, AF7, DS08X)
192#define GPIO73_MLCD_CS MFP_CFG_DRV(GPIO73, AF7, DS08X)
193#define GPIO74_MLCD_VSYNC MFP_CFG_DRV(GPIO74, AF7, DS08X)
194#define GPIO14_2_MLCD_FCLK MFP_CFG_DRV(GPIO14_2, AF7, DS08X)
195#define GPIO15_2_MLCD_LCLK MFP_CFG_DRV(GPIO15_2, AF7, DS08X)
196#define GPIO16_2_MLCD_PCLK MFP_CFG_DRV(GPIO16_2, AF7, DS08X)
197#define GPIO17_2_MLCD_BIAS MFP_CFG_DRV(GPIO17_2, AF7, DS08X)
198
199/* MMC1 */
200#define GPIO9_MMC1_CMD MFP_CFG_LPM(GPIO9, AF4, DRIVE_HIGH)
201#define GPIO22_MMC1_CLK MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH)
202#define GPIO23_MMC1_CMD MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH)
203#define GPIO30_MMC1_CLK MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH)
204#define GPIO31_MMC1_CMD MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH)
205#define GPIO5_MMC1_DAT0 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH)
206#define GPIO6_MMC1_DAT1 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH)
207#define GPIO7_MMC1_DAT2 MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH)
208#define GPIO8_MMC1_DAT3 MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH)
209#define GPIO18_MMC1_DAT0 MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH)
210#define GPIO19_MMC1_DAT1 MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH)
211#define GPIO20_MMC1_DAT2 MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH)
212#define GPIO21_MMC1_DAT3 MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH)
213
214#define GPIO28_MMC2_CLK MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH)
215#define GPIO29_MMC2_CMD MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH)
216#define GPIO30_MMC2_CLK MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH)
217#define GPIO31_MMC2_CMD MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH)
218#define GPIO79_MMC2_CLK MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH)
219#define GPIO80_MMC2_CMD MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH)
220
221#define GPIO5_MMC2_DAT0 MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH)
222#define GPIO6_MMC2_DAT1 MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH)
223#define GPIO7_MMC2_DAT2 MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH)
224#define GPIO8_MMC2_DAT3 MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH)
225#define GPIO24_MMC2_DAT0 MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH)
226#define GPIO75_MMC2_DAT0 MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH)
227#define GPIO25_MMC2_DAT1 MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH)
228#define GPIO76_MMC2_DAT1 MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH)
229#define GPIO26_MMC2_DAT2 MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH)
230#define GPIO77_MMC2_DAT2 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH)
231#define GPIO27_MMC2_DAT3 MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH)
232#define GPIO78_MMC2_DAT3 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH)
233
234/* 1-Wire */
235#define GPIO14_ONE_WIRE MFP_CFG_LPM(GPIO14, AF5, FLOAT)
236#define GPIO0_2_ONE_WIRE MFP_CFG_LPM(GPIO0_2, AF2, FLOAT)
237
238/* SSP1 */
239#define GPIO87_SSP1_EXTCLK MFP_CFG(GPIO87, AF1)
240#define GPIO88_SSP1_SYSCLK MFP_CFG(GPIO88, AF1)
241#define GPIO83_SSP1_SCLK MFP_CFG(GPIO83, AF1)
242#define GPIO84_SSP1_SFRM MFP_CFG(GPIO84, AF1)
243#define GPIO85_SSP1_RXD MFP_CFG(GPIO85, AF6)
244#define GPIO85_SSP1_TXD MFP_CFG(GPIO85, AF1)
245#define GPIO86_SSP1_RXD MFP_CFG(GPIO86, AF1)
246#define GPIO86_SSP1_TXD MFP_CFG(GPIO86, AF6)
247
248/* SSP2 */
249#define GPIO39_SSP2_EXTCLK MFP_CFG(GPIO39, AF2)
250#define GPIO40_SSP2_SYSCLK MFP_CFG(GPIO40, AF2)
251#define GPIO12_SSP2_SCLK MFP_CFG(GPIO12, AF2)
252#define GPIO35_SSP2_SCLK MFP_CFG(GPIO35, AF2)
253#define GPIO36_SSP2_SFRM MFP_CFG(GPIO36, AF2)
254#define GPIO37_SSP2_RXD MFP_CFG(GPIO37, AF5)
255#define GPIO37_SSP2_TXD MFP_CFG(GPIO37, AF2)
256#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2)
257#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5)
258
259#define GPIO69_SSP3_SCLK MFP_CFG(GPIO69, AF2, DS08X, FLOAT)
260#define GPIO70_SSP3_FRM MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW)
261#define GPIO89_SSP3_SCLK MFP_CFG(GPIO89, AF1, DS08X, FLOAT)
262#define GPIO90_SSP3_FRM MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW)
263#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT)
264#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW)
265#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT)
266#define GPIO72_SSP3_TXD MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW)
267#define GPIO91_SSP3_RXD MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT)
268#define GPIO91_SSP3_TXD MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW)
269#define GPIO92_SSP3_RXD MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT)
270#define GPIO92_SSP3_TXD MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW)
271
272#define GPIO93_SSP4_SCLK MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH)
273#define GPIO94_SSP4_FRM MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH)
274#define GPIO94_SSP4_RXD MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH)
275#define GPIO95_SSP4_RXD MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH)
276#define GPIO95_SSP4_TXD MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH)
277#define GPIO96_SSP4_RXD MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH)
278#define GPIO96_SSP4_TXD MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH)
279
280/* UART1 */
281#define GPIO41_UART1_RXD MFP_CFG_LPM(GPIO41, AF2, FLOAT)
282#define GPIO41_UART1_TXD MFP_CFG_LPM(GPIO41, AF4, FLOAT)
283#define GPIO42_UART1_RXD MFP_CFG_LPM(GPIO42, AF4, FLOAT)
284#define GPIO42_UART1_TXD MFP_CFG_LPM(GPIO42, AF2, FLOAT)
285#define GPIO97_UART1_RXD MFP_CFG_LPM(GPIO97, AF1, FLOAT)
286#define GPIO97_UART1_TXD MFP_CFG_LPM(GPIO97, AF6, FLOAT)
287#define GPIO98_UART1_RXD MFP_CFG_LPM(GPIO98, AF6, FLOAT)
288#define GPIO98_UART1_TXD MFP_CFG_LPM(GPIO98, AF1, FLOAT)
289#define GPIO43_UART1_CTS MFP_CFG_LPM(GPIO43, AF2, FLOAT)
290#define GPIO43_UART1_RTS MFP_CFG_LPM(GPIO43, AF4, FLOAT)
291#define GPIO48_UART1_CTS MFP_CFG_LPM(GPIO48, AF4, FLOAT)
292#define GPIO48_UART1_RTS MFP_CFG_LPM(GPIO48, AF2, FLOAT)
293#define GPIO99_UART1_CTS MFP_CFG_LPM(GPIO99, AF1, FLOAT)
294#define GPIO99_UART1_RTS MFP_CFG_LPM(GPIO99, AF6, FLOAT)
295#define GPIO104_UART1_CTS MFP_CFG_LPM(GPIO104, AF6, FLOAT)
296#define GPIO104_UART1_RTS MFP_CFG_LPM(GPIO104, AF1, FLOAT)
297#define GPIO45_UART1_DTR MFP_CFG_LPM(GPIO45, AF4, FLOAT)
298#define GPIO45_UART1_DSR MFP_CFG_LPM(GPIO45, AF2, FLOAT)
299#define GPIO47_UART1_DTR MFP_CFG_LPM(GPIO47, AF2, FLOAT)
300#define GPIO47_UART1_DSR MFP_CFG_LPM(GPIO47, AF4, FLOAT)
301#define GPIO101_UART1_DTR MFP_CFG_LPM(GPIO101, AF6, FLOAT)
302#define GPIO101_UART1_DSR MFP_CFG_LPM(GPIO101, AF1, FLOAT)
303#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF1, FLOAT)
304#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF6, FLOAT)
305#define GPIO44_UART1_DCD MFP_CFG_LPM(GPIO44, AF2, FLOAT)
306#define GPIO100_UART1_DCD MFP_CFG_LPM(GPIO100, AF1, FLOAT)
307#define GPIO46_UART1_RI MFP_CFG_LPM(GPIO46, AF2, FLOAT)
308#define GPIO102_UART1_RI MFP_CFG_LPM(GPIO102, AF1, FLOAT)
309
310/* UART2 */
311#define GPIO109_UART2_CTS MFP_CFG_LPM(GPIO109, AF3, FLOAT)
312#define GPIO109_UART2_RTS MFP_CFG_LPM(GPIO109, AF1, FLOAT)
313#define GPIO112_UART2_CTS MFP_CFG_LPM(GPIO112, AF1, FLOAT)
314#define GPIO112_UART2_RTS MFP_CFG_LPM(GPIO112, AF3, FLOAT)
315#define GPIO110_UART2_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT)
316#define GPIO110_UART2_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT)
317#define GPIO111_UART2_RXD MFP_CFG_LPM(GPIO111, AF3, FLOAT)
318#define GPIO111_UART2_TXD MFP_CFG_LPM(GPIO111, AF1, FLOAT)
319
320/* UART3 */
321#define GPIO89_UART3_CTS MFP_CFG_LPM(GPIO89, AF2, FLOAT)
322#define GPIO89_UART3_RTS MFP_CFG_LPM(GPIO89, AF4, FLOAT)
323#define GPIO90_UART3_CTS MFP_CFG_LPM(GPIO90, AF4, FLOAT)
324#define GPIO90_UART3_RTS MFP_CFG_LPM(GPIO90, AF2, FLOAT)
325#define GPIO105_UART3_CTS MFP_CFG_LPM(GPIO105, AF1, FLOAT)
326#define GPIO105_UART3_RTS MFP_CFG_LPM(GPIO105, AF3, FLOAT)
327#define GPIO106_UART3_CTS MFP_CFG_LPM(GPIO106, AF3, FLOAT)
328#define GPIO106_UART3_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT)
329#define GPIO30_UART3_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT)
330#define GPIO30_UART3_TXD MFP_CFG_LPM(GPIO30, AF6, FLOAT)
331#define GPIO31_UART3_RXD MFP_CFG_LPM(GPIO31, AF6, FLOAT)
332#define GPIO31_UART3_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT)
333#define GPIO91_UART3_RXD MFP_CFG_LPM(GPIO91, AF4, FLOAT)
334#define GPIO91_UART3_TXD MFP_CFG_LPM(GPIO91, AF2, FLOAT)
335#define GPIO92_UART3_RXD MFP_CFG_LPM(GPIO92, AF2, FLOAT)
336#define GPIO92_UART3_TXD MFP_CFG_LPM(GPIO92, AF4, FLOAT)
337#define GPIO107_UART3_RXD MFP_CFG_LPM(GPIO107, AF3, FLOAT)
338#define GPIO107_UART3_TXD MFP_CFG_LPM(GPIO107, AF1, FLOAT)
339#define GPIO108_UART3_RXD MFP_CFG_LPM(GPIO108, AF1, FLOAT)
340#define GPIO108_UART3_TXD MFP_CFG_LPM(GPIO108, AF3, FLOAT)
341
342
343/* USB 2.0 UTMI */
344#define GPIO10_UTM_CLK MFP_CFG(GPIO10, AF1)
345#define GPIO36_U2D_RXERROR MFP_CFG(GPIO36, AF3)
346#define GPIO60_U2D_RXERROR MFP_CFG(GPIO60, AF1)
347#define GPIO87_U2D_RXERROR MFP_CFG(GPIO87, AF5)
348#define GPIO34_UTM_RXVALID MFP_CFG(GPIO34, AF3)
349#define GPIO58_UTM_RXVALID MFP_CFG(GPIO58, AF2)
350#define GPIO85_UTM_RXVALID MFP_CFG(GPIO85, AF5)
351#define GPIO35_UTM_RXACTIVE MFP_CFG(GPIO35, AF3)
352#define GPIO59_UTM_RXACTIVE MFP_CFG(GPIO59, AF1)
353#define GPIO86_UTM_RXACTIVE MFP_CFG(GPIO86, AF5)
354#define GPIO73_UTM_TXREADY MFP_CFG(GPIO73, AF1)
355#define GPIO68_UTM_LINESTATE_0 MFP_CFG(GPIO68, AF3)
356#define GPIO90_UTM_LINESTATE_0 MFP_CFG(GPIO90, AF3)
357#define GPIO102_UTM_LINESTATE_0 MFP_CFG(GPIO102, AF3)
358#define GPIO107_UTM_LINESTATE_0 MFP_CFG(GPIO107, AF4)
359#define GPIO69_UTM_LINESTATE_1 MFP_CFG(GPIO69, AF3)
360#define GPIO91_UTM_LINESTATE_1 MFP_CFG(GPIO91, AF3)
361#define GPIO103_UTM_LINESTATE_1 MFP_CFG(GPIO103, AF3)
362
363#define GPIO41_U2D_PHYDATA_0 MFP_CFG(GPIO41, AF3)
364#define GPIO42_U2D_PHYDATA_1 MFP_CFG(GPIO42, AF3)
365#define GPIO43_U2D_PHYDATA_2 MFP_CFG(GPIO43, AF3)
366#define GPIO44_U2D_PHYDATA_3 MFP_CFG(GPIO44, AF3)
367#define GPIO45_U2D_PHYDATA_4 MFP_CFG(GPIO45, AF3)
368#define GPIO46_U2D_PHYDATA_5 MFP_CFG(GPIO46, AF3)
369#define GPIO47_U2D_PHYDATA_6 MFP_CFG(GPIO47, AF3)
370#define GPIO48_U2D_PHYDATA_7 MFP_CFG(GPIO48, AF3)
371
372#define GPIO49_U2D_PHYDATA_0 MFP_CFG(GPIO49, AF3)
373#define GPIO50_U2D_PHYDATA_1 MFP_CFG(GPIO50, AF3)
374#define GPIO51_U2D_PHYDATA_2 MFP_CFG(GPIO51, AF3)
375#define GPIO52_U2D_PHYDATA_3 MFP_CFG(GPIO52, AF3)
376#define GPIO53_U2D_PHYDATA_4 MFP_CFG(GPIO53, AF3)
377#define GPIO54_U2D_PHYDATA_5 MFP_CFG(GPIO54, AF3)
378#define GPIO55_U2D_PHYDATA_6 MFP_CFG(GPIO55, AF3)
379#define GPIO56_U2D_PHYDATA_7 MFP_CFG(GPIO56, AF3)
380
381#define GPIO37_U2D_OPMODE0 MFP_CFG(GPIO37, AF4)
382#define GPIO61_U2D_OPMODE0 MFP_CFG(GPIO61, AF2)
383#define GPIO88_U2D_OPMODE0 MFP_CFG(GPIO88, AF7)
384
385#define GPIO38_U2D_OPMODE1 MFP_CFG(GPIO38, AF4)
386#define GPIO62_U2D_OPMODE1 MFP_CFG(GPIO62, AF2)
387#define GPIO104_U2D_OPMODE1 MFP_CFG(GPIO104, AF4)
388#define GPIO108_U2D_OPMODE1 MFP_CFG(GPIO108, AF5)
389
390#define GPIO74_U2D_RESET MFP_CFG(GPIO74, AF1)
391#define GPIO93_U2D_RESET MFP_CFG(GPIO93, AF2)
392#define GPIO98_U2D_RESET MFP_CFG(GPIO98, AF3)
393
394#define GPIO67_U2D_SUSPEND MFP_CFG(GPIO67, AF3)
395#define GPIO96_U2D_SUSPEND MFP_CFG(GPIO96, AF2)
396#define GPIO101_U2D_SUSPEND MFP_CFG(GPIO101, AF3)
397
398#define GPIO66_U2D_TERM_SEL MFP_CFG(GPIO66, AF5)
399#define GPIO95_U2D_TERM_SEL MFP_CFG(GPIO95, AF3)
400#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF7)
401#define GPIO100_U2D_TERM_SEL MFP_CFG(GPIO100, AF5)
402
403#define GPIO39_U2D_TXVALID MFP_CFG(GPIO39, AF4)
404#define GPIO70_U2D_TXVALID MFP_CFG(GPIO70, AF5)
405#define GPIO83_U2D_TXVALID MFP_CFG(GPIO83, AF7)
406
407#define GPIO65_U2D_XCVR_SEL MFP_CFG(GPIO65, AF5)
408#define GPIO94_U2D_XCVR_SEL MFP_CFG(GPIO94, AF3)
409#define GPIO99_U2D_XCVR_SEL MFP_CFG(GPIO99, AF5)
410
411/* USB Host 1.1 */
412#define GPIO2_2_USBH_PEN MFP_CFG(GPIO2_2, AF1)
413#define GPIO3_2_USBH_PWR MFP_CFG(GPIO3_2, AF1)
414
415/* USB P2 */
416#define GPIO97_USB_P2_2 MFP_CFG(GPIO97, AF2)
417#define GPIO97_USB_P2_6 MFP_CFG(GPIO97, AF4)
418#define GPIO98_USB_P2_2 MFP_CFG(GPIO98, AF4)
419#define GPIO98_USB_P2_6 MFP_CFG(GPIO98, AF2)
420#define GPIO99_USB_P2_1 MFP_CFG(GPIO99, AF2)
421#define GPIO100_USB_P2_4 MFP_CFG(GPIO100, AF2)
422#define GPIO101_USB_P2_8 MFP_CFG(GPIO101, AF2)
423#define GPIO102_USB_P2_3 MFP_CFG(GPIO102, AF2)
424#define GPIO103_USB_P2_5 MFP_CFG(GPIO103, AF2)
425#define GPIO104_USB_P2_7 MFP_CFG(GPIO104, AF2)
426
427/* USB P3 */
428#define GPIO75_USB_P3_1 MFP_CFG(GPIO75, AF2)
429#define GPIO76_USB_P3_2 MFP_CFG(GPIO76, AF2)
430#define GPIO77_USB_P3_3 MFP_CFG(GPIO77, AF2)
431#define GPIO78_USB_P3_4 MFP_CFG(GPIO78, AF2)
432#define GPIO79_USB_P3_5 MFP_CFG(GPIO79, AF2)
433#define GPIO80_USB_P3_6 MFP_CFG(GPIO80, AF2)
434
435#define GPIO13_CHOUT0 MFP_CFG(GPIO13, AF6)
436#define GPIO14_CHOUT1 MFP_CFG(GPIO14, AF6)
437
438#define GPIO2_RDY MFP_CFG(GPIO2, AF1)
439#define GPIO5_NPIOR MFP_CFG(GPIO5, AF3)
440
441#define GPIO11_PWM0_OUT MFP_CFG(GPIO11, AF1)
442#define GPIO12_PWM1_OUT MFP_CFG(GPIO12, AF1)
443#define GPIO13_PWM2_OUT MFP_CFG(GPIO13, AF1)
444#define GPIO14_PWM3_OUT MFP_CFG(GPIO14, AF1)
445
446#endif /* __ASM_ARCH_MFP_PXA320_H */
diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h
new file mode 100644
index 000000000000..60291742ffdd
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mfp.h
@@ -0,0 +1,576 @@
1/*
2 * linux/include/asm-arm/arch-pxa/mfp.h
3 *
4 * Multi-Function Pin Definitions
5 *
6 * Copyright (C) 2007 Marvell International Ltd.
7 *
8 * 2007-8-21: eric miao <eric.y.miao@gmail.com>
9 * initial version
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#ifndef __ASM_ARCH_MFP_H
17#define __ASM_ARCH_MFP_H
18
19#define MFPR_BASE (0x40e10000)
20#define MFPR_SIZE (PAGE_SIZE)
21
22#define mfp_to_gpio(m) ((m) % 128)
23
24/* list of all the configurable MFP pins */
25enum {
26 MFP_PIN_INVALID = -1,
27
28 MFP_PIN_GPIO0 = 0,
29 MFP_PIN_GPIO1,
30 MFP_PIN_GPIO2,
31 MFP_PIN_GPIO3,
32 MFP_PIN_GPIO4,
33 MFP_PIN_GPIO5,
34 MFP_PIN_GPIO6,
35 MFP_PIN_GPIO7,
36 MFP_PIN_GPIO8,
37 MFP_PIN_GPIO9,
38 MFP_PIN_GPIO10,
39 MFP_PIN_GPIO11,
40 MFP_PIN_GPIO12,
41 MFP_PIN_GPIO13,
42 MFP_PIN_GPIO14,
43 MFP_PIN_GPIO15,
44 MFP_PIN_GPIO16,
45 MFP_PIN_GPIO17,
46 MFP_PIN_GPIO18,
47 MFP_PIN_GPIO19,
48 MFP_PIN_GPIO20,
49 MFP_PIN_GPIO21,
50 MFP_PIN_GPIO22,
51 MFP_PIN_GPIO23,
52 MFP_PIN_GPIO24,
53 MFP_PIN_GPIO25,
54 MFP_PIN_GPIO26,
55 MFP_PIN_GPIO27,
56 MFP_PIN_GPIO28,
57 MFP_PIN_GPIO29,
58 MFP_PIN_GPIO30,
59 MFP_PIN_GPIO31,
60 MFP_PIN_GPIO32,
61 MFP_PIN_GPIO33,
62 MFP_PIN_GPIO34,
63 MFP_PIN_GPIO35,
64 MFP_PIN_GPIO36,
65 MFP_PIN_GPIO37,
66 MFP_PIN_GPIO38,
67 MFP_PIN_GPIO39,
68 MFP_PIN_GPIO40,
69 MFP_PIN_GPIO41,
70 MFP_PIN_GPIO42,
71 MFP_PIN_GPIO43,
72 MFP_PIN_GPIO44,
73 MFP_PIN_GPIO45,
74 MFP_PIN_GPIO46,
75 MFP_PIN_GPIO47,
76 MFP_PIN_GPIO48,
77 MFP_PIN_GPIO49,
78 MFP_PIN_GPIO50,
79 MFP_PIN_GPIO51,
80 MFP_PIN_GPIO52,
81 MFP_PIN_GPIO53,
82 MFP_PIN_GPIO54,
83 MFP_PIN_GPIO55,
84 MFP_PIN_GPIO56,
85 MFP_PIN_GPIO57,
86 MFP_PIN_GPIO58,
87 MFP_PIN_GPIO59,
88 MFP_PIN_GPIO60,
89 MFP_PIN_GPIO61,
90 MFP_PIN_GPIO62,
91 MFP_PIN_GPIO63,
92 MFP_PIN_GPIO64,
93 MFP_PIN_GPIO65,
94 MFP_PIN_GPIO66,
95 MFP_PIN_GPIO67,
96 MFP_PIN_GPIO68,
97 MFP_PIN_GPIO69,
98 MFP_PIN_GPIO70,
99 MFP_PIN_GPIO71,
100 MFP_PIN_GPIO72,
101 MFP_PIN_GPIO73,
102 MFP_PIN_GPIO74,
103 MFP_PIN_GPIO75,
104 MFP_PIN_GPIO76,
105 MFP_PIN_GPIO77,
106 MFP_PIN_GPIO78,
107 MFP_PIN_GPIO79,
108 MFP_PIN_GPIO80,
109 MFP_PIN_GPIO81,
110 MFP_PIN_GPIO82,
111 MFP_PIN_GPIO83,
112 MFP_PIN_GPIO84,
113 MFP_PIN_GPIO85,
114 MFP_PIN_GPIO86,
115 MFP_PIN_GPIO87,
116 MFP_PIN_GPIO88,
117 MFP_PIN_GPIO89,
118 MFP_PIN_GPIO90,
119 MFP_PIN_GPIO91,
120 MFP_PIN_GPIO92,
121 MFP_PIN_GPIO93,
122 MFP_PIN_GPIO94,
123 MFP_PIN_GPIO95,
124 MFP_PIN_GPIO96,
125 MFP_PIN_GPIO97,
126 MFP_PIN_GPIO98,
127 MFP_PIN_GPIO99,
128 MFP_PIN_GPIO100,
129 MFP_PIN_GPIO101,
130 MFP_PIN_GPIO102,
131 MFP_PIN_GPIO103,
132 MFP_PIN_GPIO104,
133 MFP_PIN_GPIO105,
134 MFP_PIN_GPIO106,
135 MFP_PIN_GPIO107,
136 MFP_PIN_GPIO108,
137 MFP_PIN_GPIO109,
138 MFP_PIN_GPIO110,
139 MFP_PIN_GPIO111,
140 MFP_PIN_GPIO112,
141 MFP_PIN_GPIO113,
142 MFP_PIN_GPIO114,
143 MFP_PIN_GPIO115,
144 MFP_PIN_GPIO116,
145 MFP_PIN_GPIO117,
146 MFP_PIN_GPIO118,
147 MFP_PIN_GPIO119,
148 MFP_PIN_GPIO120,
149 MFP_PIN_GPIO121,
150 MFP_PIN_GPIO122,
151 MFP_PIN_GPIO123,
152 MFP_PIN_GPIO124,
153 MFP_PIN_GPIO125,
154 MFP_PIN_GPIO126,
155 MFP_PIN_GPIO127,
156 MFP_PIN_GPIO0_2,
157 MFP_PIN_GPIO1_2,
158 MFP_PIN_GPIO2_2,
159 MFP_PIN_GPIO3_2,
160 MFP_PIN_GPIO4_2,
161 MFP_PIN_GPIO5_2,
162 MFP_PIN_GPIO6_2,
163 MFP_PIN_GPIO7_2,
164 MFP_PIN_GPIO8_2,
165 MFP_PIN_GPIO9_2,
166 MFP_PIN_GPIO10_2,
167 MFP_PIN_GPIO11_2,
168 MFP_PIN_GPIO12_2,
169 MFP_PIN_GPIO13_2,
170 MFP_PIN_GPIO14_2,
171 MFP_PIN_GPIO15_2,
172 MFP_PIN_GPIO16_2,
173 MFP_PIN_GPIO17_2,
174
175 MFP_PIN_ULPI_STP,
176 MFP_PIN_ULPI_NXT,
177 MFP_PIN_ULPI_DIR,
178
179 MFP_PIN_nXCVREN,
180 MFP_PIN_DF_CLE_nOE,
181 MFP_PIN_DF_nADV1_ALE,
182 MFP_PIN_DF_SCLK_E,
183 MFP_PIN_DF_SCLK_S,
184 MFP_PIN_nBE0,
185 MFP_PIN_nBE1,
186 MFP_PIN_DF_nADV2_ALE,
187 MFP_PIN_DF_INT_RnB,
188 MFP_PIN_DF_nCS0,
189 MFP_PIN_DF_nCS1,
190 MFP_PIN_nLUA,
191 MFP_PIN_nLLA,
192 MFP_PIN_DF_nWE,
193 MFP_PIN_DF_ALE_nWE,
194 MFP_PIN_DF_nRE_nOE,
195 MFP_PIN_DF_ADDR0,
196 MFP_PIN_DF_ADDR1,
197 MFP_PIN_DF_ADDR2,
198 MFP_PIN_DF_ADDR3,
199 MFP_PIN_DF_IO0,
200 MFP_PIN_DF_IO1,
201 MFP_PIN_DF_IO2,
202 MFP_PIN_DF_IO3,
203 MFP_PIN_DF_IO4,
204 MFP_PIN_DF_IO5,
205 MFP_PIN_DF_IO6,
206 MFP_PIN_DF_IO7,
207 MFP_PIN_DF_IO8,
208 MFP_PIN_DF_IO9,
209 MFP_PIN_DF_IO10,
210 MFP_PIN_DF_IO11,
211 MFP_PIN_DF_IO12,
212 MFP_PIN_DF_IO13,
213 MFP_PIN_DF_IO14,
214 MFP_PIN_DF_IO15,
215
216 MFP_PIN_MAX,
217};
218
219/*
220 * Table that determines the low power modes outputs, with actual settings
221 * used in parentheses for don't-care values. Except for the float output,
222 * the configured driven and pulled levels match, so if there is a need for
223 * non-LPM pulled output, the same configuration could probably be used.
224 *
225 * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel
226 * (bit 7) (bit 8) (bit 14d) (bit 13d)
227 *
228 * Drive 0 0 0 0 X (1) 0
229 * Drive 1 0 1 X (1) 0 0
230 * Pull hi (1) 1 X(1) 1 0 0
231 * Pull lo (0) 1 X(0) 0 1 0
232 * Z (float) 1 X(0) 0 0 0
233 */
234#define MFP_LPM_DRIVE_LOW 0x8
235#define MFP_LPM_DRIVE_HIGH 0x6
236#define MFP_LPM_PULL_HIGH 0x7
237#define MFP_LPM_PULL_LOW 0x9
238#define MFP_LPM_FLOAT 0x1
239#define MFP_LPM_PULL_NEITHER 0x0
240
241/*
242 * The pullup and pulldown state of the MFP pin is by default determined by
243 * selected alternate function. In case some buggy devices need to override
244 * this default behavior, pxa3xx_mfp_set_pull() can be invoked with one of
245 * the following definition as the parameter.
246 *
247 * Definition pull_sel pullup_en pulldown_en
248 * MFP_PULL_HIGH 1 1 0
249 * MFP_PULL_LOW 1 0 1
250 * MFP_PULL_BOTH 1 1 1
251 * MFP_PULL_NONE 1 0 0
252 * MFP_PULL_DEFAULT 0 X X
253 *
254 * NOTE: pxa3xx_mfp_set_pull() will modify the PULLUP_EN and PULLDOWN_EN
255 * bits, which will cause potential conflicts with the low power mode
256 * setting, device drivers should take care of this
257 */
258#define MFP_PULL_BOTH (0x7u)
259#define MFP_PULL_HIGH (0x6u)
260#define MFP_PULL_LOW (0x5u)
261#define MFP_PULL_NONE (0x4u)
262#define MFP_PULL_DEFAULT (0x0u)
263
264#define MFP_AF0 (0)
265#define MFP_AF1 (1)
266#define MFP_AF2 (2)
267#define MFP_AF3 (3)
268#define MFP_AF4 (4)
269#define MFP_AF5 (5)
270#define MFP_AF6 (6)
271#define MFP_AF7 (7)
272
273#define MFP_DS01X (0)
274#define MFP_DS02X (1)
275#define MFP_DS03X (2)
276#define MFP_DS04X (3)
277#define MFP_DS06X (4)
278#define MFP_DS08X (5)
279#define MFP_DS10X (6)
280#define MFP_DS12X (7)
281
282#define MFP_EDGE_BOTH 0x3
283#define MFP_EDGE_RISE 0x2
284#define MFP_EDGE_FALL 0x1
285#define MFP_EDGE_NONE 0x0
286
287#define MFPR_AF_MASK 0x0007
288#define MFPR_DRV_MASK 0x1c00
289#define MFPR_RDH_MASK 0x0200
290#define MFPR_LPM_MASK 0xe180
291#define MFPR_PULL_MASK 0xe000
292#define MFPR_EDGE_MASK 0x0070
293
294#define MFPR_ALT_OFFSET 0
295#define MFPR_ERE_OFFSET 4
296#define MFPR_EFE_OFFSET 5
297#define MFPR_EC_OFFSET 6
298#define MFPR_SON_OFFSET 7
299#define MFPR_SD_OFFSET 8
300#define MFPR_SS_OFFSET 9
301#define MFPR_DRV_OFFSET 10
302#define MFPR_PD_OFFSET 13
303#define MFPR_PU_OFFSET 14
304#define MFPR_PS_OFFSET 15
305
306#define MFPR(af, drv, rdh, lpm, edge) \
307 (((af) & 0x7) | (((drv) & 0x7) << 10) |\
308 (((rdh) & 0x1) << 9) |\
309 (((lpm) & 0x3) << 7) |\
310 (((lpm) & 0x4) << 12)|\
311 (((lpm) & 0x8) << 10)|\
312 ((!(edge)) << 6) |\
313 (((edge) & 0x1) << 5) |\
314 (((edge) & 0x2) << 3))
315
316/*
317 * a possible MFP configuration is represented by a 32-bit integer
318 * bit 0..15 - MFPR value (16-bit)
319 * bit 16..31 - mfp pin index (used to obtain the MFPR offset)
320 *
321 * to facilitate the definition, the following macros are provided
322 *
323 * MFPR_DEFAULT - default MFPR value, with
324 * alternate function = 0,
325 * drive strength = fast 1mA (MFP_DS01X)
326 * low power mode = default
327 * release dalay hold = false (RDH bit)
328 * edge detection = none
329 *
330 * MFP_CFG - default MFPR value with alternate function
331 * MFP_CFG_DRV - default MFPR value with alternate function and
332 * pin drive strength
333 * MFP_CFG_LPM - default MFPR value with alternate function and
334 * low power mode
335 * MFP_CFG_X - default MFPR value with alternate function,
336 * pin drive strength and low power mode
337 *
338 * use
339 *
340 * MFP_CFG_PIN - to get the MFP pin index
341 * MFP_CFG_VAL - to get the corresponding MFPR value
342 */
343
344typedef uint32_t mfp_cfg_t;
345
346#define MFP_CFG_PIN(mfp_cfg) (((mfp_cfg) >> 16) & 0xffff)
347#define MFP_CFG_VAL(mfp_cfg) ((mfp_cfg) & 0xffff)
348
349#define MFPR_DEFAULT (0x0000)
350
351#define MFP_CFG(pin, af) \
352 ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af))
353
354#define MFP_CFG_DRV(pin, af, drv) \
355 ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\
356 ((MFP_##drv) << 10) | (MFP_##af))
357
358#define MFP_CFG_LPM(pin, af, lpm) \
359 ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af) |\
360 (((MFP_LPM_##lpm) & 0x3) << 7) |\
361 (((MFP_LPM_##lpm) & 0x4) << 12) |\
362 (((MFP_LPM_##lpm) & 0x8) << 10))
363
364#define MFP_CFG_X(pin, af, drv, lpm) \
365 ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\
366 ((MFP_##drv) << 10) | (MFP_##af) |\
367 (((MFP_LPM_##lpm) & 0x3) << 7) |\
368 (((MFP_LPM_##lpm) & 0x4) << 12) |\
369 (((MFP_LPM_##lpm) & 0x8) << 10))
370
371/* common MFP configurations - processor specific ones defined
372 * in mfp-pxa3xx.h
373 */
374#define GPIO0_GPIO MFP_CFG(GPIO0, AF0)
375#define GPIO1_GPIO MFP_CFG(GPIO1, AF0)
376#define GPIO2_GPIO MFP_CFG(GPIO2, AF0)
377#define GPIO3_GPIO MFP_CFG(GPIO3, AF0)
378#define GPIO4_GPIO MFP_CFG(GPIO4, AF0)
379#define GPIO5_GPIO MFP_CFG(GPIO5, AF0)
380#define GPIO6_GPIO MFP_CFG(GPIO6, AF0)
381#define GPIO7_GPIO MFP_CFG(GPIO7, AF0)
382#define GPIO8_GPIO MFP_CFG(GPIO8, AF0)
383#define GPIO9_GPIO MFP_CFG(GPIO9, AF0)
384#define GPIO10_GPIO MFP_CFG(GPIO10, AF0)
385#define GPIO11_GPIO MFP_CFG(GPIO11, AF0)
386#define GPIO12_GPIO MFP_CFG(GPIO12, AF0)
387#define GPIO13_GPIO MFP_CFG(GPIO13, AF0)
388#define GPIO14_GPIO MFP_CFG(GPIO14, AF0)
389#define GPIO15_GPIO MFP_CFG(GPIO15, AF0)
390#define GPIO16_GPIO MFP_CFG(GPIO16, AF0)
391#define GPIO17_GPIO MFP_CFG(GPIO17, AF0)
392#define GPIO18_GPIO MFP_CFG(GPIO18, AF0)
393#define GPIO19_GPIO MFP_CFG(GPIO19, AF0)
394#define GPIO20_GPIO MFP_CFG(GPIO20, AF0)
395#define GPIO21_GPIO MFP_CFG(GPIO21, AF0)
396#define GPIO22_GPIO MFP_CFG(GPIO22, AF0)
397#define GPIO23_GPIO MFP_CFG(GPIO23, AF0)
398#define GPIO24_GPIO MFP_CFG(GPIO24, AF0)
399#define GPIO25_GPIO MFP_CFG(GPIO25, AF0)
400#define GPIO26_GPIO MFP_CFG(GPIO26, AF0)
401#define GPIO27_GPIO MFP_CFG(GPIO27, AF0)
402#define GPIO28_GPIO MFP_CFG(GPIO28, AF0)
403#define GPIO29_GPIO MFP_CFG(GPIO29, AF0)
404#define GPIO30_GPIO MFP_CFG(GPIO30, AF0)
405#define GPIO31_GPIO MFP_CFG(GPIO31, AF0)
406#define GPIO32_GPIO MFP_CFG(GPIO32, AF0)
407#define GPIO33_GPIO MFP_CFG(GPIO33, AF0)
408#define GPIO34_GPIO MFP_CFG(GPIO34, AF0)
409#define GPIO35_GPIO MFP_CFG(GPIO35, AF0)
410#define GPIO36_GPIO MFP_CFG(GPIO36, AF0)
411#define GPIO37_GPIO MFP_CFG(GPIO37, AF0)
412#define GPIO38_GPIO MFP_CFG(GPIO38, AF0)
413#define GPIO39_GPIO MFP_CFG(GPIO39, AF0)
414#define GPIO40_GPIO MFP_CFG(GPIO40, AF0)
415#define GPIO41_GPIO MFP_CFG(GPIO41, AF0)
416#define GPIO42_GPIO MFP_CFG(GPIO42, AF0)
417#define GPIO43_GPIO MFP_CFG(GPIO43, AF0)
418#define GPIO44_GPIO MFP_CFG(GPIO44, AF0)
419#define GPIO45_GPIO MFP_CFG(GPIO45, AF0)
420
421#define GPIO47_GPIO MFP_CFG(GPIO47, AF0)
422#define GPIO48_GPIO MFP_CFG(GPIO48, AF0)
423
424#define GPIO53_GPIO MFP_CFG(GPIO53, AF0)
425#define GPIO54_GPIO MFP_CFG(GPIO54, AF0)
426#define GPIO55_GPIO MFP_CFG(GPIO55, AF0)
427
428#define GPIO57_GPIO MFP_CFG(GPIO57, AF0)
429
430#define GPIO63_GPIO MFP_CFG(GPIO63, AF0)
431#define GPIO64_GPIO MFP_CFG(GPIO64, AF0)
432#define GPIO65_GPIO MFP_CFG(GPIO65, AF0)
433#define GPIO66_GPIO MFP_CFG(GPIO66, AF0)
434#define GPIO67_GPIO MFP_CFG(GPIO67, AF0)
435#define GPIO68_GPIO MFP_CFG(GPIO68, AF0)
436#define GPIO69_GPIO MFP_CFG(GPIO69, AF0)
437#define GPIO70_GPIO MFP_CFG(GPIO70, AF0)
438#define GPIO71_GPIO MFP_CFG(GPIO71, AF0)
439#define GPIO72_GPIO MFP_CFG(GPIO72, AF0)
440#define GPIO73_GPIO MFP_CFG(GPIO73, AF0)
441#define GPIO74_GPIO MFP_CFG(GPIO74, AF0)
442#define GPIO75_GPIO MFP_CFG(GPIO75, AF0)
443#define GPIO76_GPIO MFP_CFG(GPIO76, AF0)
444#define GPIO77_GPIO MFP_CFG(GPIO77, AF0)
445#define GPIO78_GPIO MFP_CFG(GPIO78, AF0)
446#define GPIO79_GPIO MFP_CFG(GPIO79, AF0)
447#define GPIO80_GPIO MFP_CFG(GPIO80, AF0)
448#define GPIO81_GPIO MFP_CFG(GPIO81, AF0)
449#define GPIO82_GPIO MFP_CFG(GPIO82, AF0)
450#define GPIO83_GPIO MFP_CFG(GPIO83, AF0)
451#define GPIO84_GPIO MFP_CFG(GPIO84, AF0)
452#define GPIO85_GPIO MFP_CFG(GPIO85, AF0)
453#define GPIO86_GPIO MFP_CFG(GPIO86, AF0)
454#define GPIO87_GPIO MFP_CFG(GPIO87, AF0)
455#define GPIO88_GPIO MFP_CFG(GPIO88, AF0)
456#define GPIO89_GPIO MFP_CFG(GPIO89, AF0)
457#define GPIO90_GPIO MFP_CFG(GPIO90, AF0)
458#define GPIO91_GPIO MFP_CFG(GPIO91, AF0)
459#define GPIO92_GPIO MFP_CFG(GPIO92, AF0)
460#define GPIO93_GPIO MFP_CFG(GPIO93, AF0)
461#define GPIO94_GPIO MFP_CFG(GPIO94, AF0)
462#define GPIO95_GPIO MFP_CFG(GPIO95, AF0)
463#define GPIO96_GPIO MFP_CFG(GPIO96, AF0)
464#define GPIO97_GPIO MFP_CFG(GPIO97, AF0)
465#define GPIO98_GPIO MFP_CFG(GPIO98, AF0)
466#define GPIO99_GPIO MFP_CFG(GPIO99, AF0)
467#define GPIO100_GPIO MFP_CFG(GPIO100, AF0)
468#define GPIO101_GPIO MFP_CFG(GPIO101, AF0)
469#define GPIO102_GPIO MFP_CFG(GPIO102, AF0)
470#define GPIO103_GPIO MFP_CFG(GPIO103, AF0)
471#define GPIO104_GPIO MFP_CFG(GPIO104, AF0)
472#define GPIO105_GPIO MFP_CFG(GPIO105, AF0)
473#define GPIO106_GPIO MFP_CFG(GPIO106, AF0)
474#define GPIO107_GPIO MFP_CFG(GPIO107, AF0)
475#define GPIO108_GPIO MFP_CFG(GPIO108, AF0)
476#define GPIO109_GPIO MFP_CFG(GPIO109, AF0)
477#define GPIO110_GPIO MFP_CFG(GPIO110, AF0)
478#define GPIO111_GPIO MFP_CFG(GPIO111, AF0)
479#define GPIO112_GPIO MFP_CFG(GPIO112, AF0)
480#define GPIO113_GPIO MFP_CFG(GPIO113, AF0)
481#define GPIO114_GPIO MFP_CFG(GPIO114, AF0)
482#define GPIO115_GPIO MFP_CFG(GPIO115, AF0)
483#define GPIO116_GPIO MFP_CFG(GPIO116, AF0)
484#define GPIO117_GPIO MFP_CFG(GPIO117, AF0)
485#define GPIO118_GPIO MFP_CFG(GPIO118, AF0)
486#define GPIO119_GPIO MFP_CFG(GPIO119, AF0)
487#define GPIO120_GPIO MFP_CFG(GPIO120, AF0)
488#define GPIO121_GPIO MFP_CFG(GPIO121, AF0)
489#define GPIO122_GPIO MFP_CFG(GPIO122, AF0)
490#define GPIO123_GPIO MFP_CFG(GPIO123, AF0)
491#define GPIO124_GPIO MFP_CFG(GPIO124, AF0)
492#define GPIO125_GPIO MFP_CFG(GPIO125, AF0)
493#define GPIO126_GPIO MFP_CFG(GPIO126, AF0)
494#define GPIO127_GPIO MFP_CFG(GPIO127, AF0)
495
496#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0)
497#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0)
498#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0)
499#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0)
500#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0)
501#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0)
502#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0)
503
504/*
505 * each MFP pin will have a MFPR register, since the offset of the
506 * register varies between processors, the processor specific code
507 * should initialize the pin offsets by pxa3xx_mfp_init_addr()
508 *
509 * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map"
510 * structure, which represents a range of MFP pins from "start" to
511 * "end", with the offset begining at "offset", to define a single
512 * pin, let "end" = -1
513 *
514 * use
515 *
516 * MFP_ADDR_X() to define a range of pins
517 * MFP_ADDR() to define a single pin
518 * MFP_ADDR_END to signal the end of pin offset definitions
519 */
520struct pxa3xx_mfp_addr_map {
521 unsigned int start;
522 unsigned int end;
523 unsigned long offset;
524};
525
526#define MFP_ADDR_X(start, end, offset) \
527 { MFP_PIN_##start, MFP_PIN_##end, offset }
528
529#define MFP_ADDR(pin, offset) \
530 { MFP_PIN_##pin, -1, offset }
531
532#define MFP_ADDR_END { MFP_PIN_INVALID, 0 }
533
534struct pxa3xx_mfp_pin {
535 unsigned long mfpr_off; /* MFPRxx register offset */
536 unsigned long mfpr_val; /* MFPRxx register value */
537};
538
539/*
540 * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access
541 * to the MFPR register
542 */
543unsigned long pxa3xx_mfp_read(int mfp);
544void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val);
545
546/*
547 * pxa3xx_mfp_set_afds - set MFP alternate function and drive strength
548 * pxa3xx_mfp_set_rdh - set MFP release delay hold on/off
549 * pxa3xx_mfp_set_lpm - set MFP low power mode state
550 * pxa3xx_mfp_set_edge - set MFP edge detection in low power mode
551 *
552 * use these functions to override/change the default configuration
553 * done by pxa3xx_mfp_set_config(s)
554 */
555void pxa3xx_mfp_set_afds(int mfp, int af, int ds);
556void pxa3xx_mfp_set_rdh(int mfp, int rdh);
557void pxa3xx_mfp_set_lpm(int mfp, int lpm);
558void pxa3xx_mfp_set_edge(int mfp, int edge);
559
560/*
561 * pxa3xx_mfp_config - configure the MFPR registers
562 *
563 * used by board specific initialization code
564 */
565void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num);
566
567/*
568 * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin
569 * index and MFPR register offset
570 *
571 * used by processor specific code
572 */
573void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *);
574void __init pxa3xx_init_mfp(void);
575
576#endif /* __ASM_ARCH_MFP_H */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index e68b593d69da..67f53e07db86 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1177,7 +1177,7 @@
1177 1177
1178#define GPIO_bit(x) (1 << ((x) & 0x1f)) 1178#define GPIO_bit(x) (1 << ((x) & 0x1f))
1179 1179
1180#ifdef CONFIG_PXA27x 1180#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
1181 1181
1182/* Interrupt Controller */ 1182/* Interrupt Controller */
1183 1183
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h
new file mode 100644
index 000000000000..3900a0ca0bc0
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h
@@ -0,0 +1,75 @@
1/*
2 * linux/include/asm-arm/arch-pxa/pxa3xx-regs.h
3 *
4 * PXA3xx specific register definitions
5 *
6 * Copyright (C) 2007 Marvell International Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARCH_PXA3XX_REGS_H
14#define __ASM_ARCH_PXA3XX_REGS_H
15
16/*
17 * Application Subsystem Clock
18 */
19#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
20#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */
21#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */
22#define CKENA __REG(0x4134000C) /* A Clock Enable Register */
23#define CKENB __REG(0x41340010) /* B Clock Enable Register */
24#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
25
26/*
27 * Clock Enable Bit
28 */
29#define CKEN_LCD 1 /* < LCD Clock Enable */
30#define CKEN_USBH 2 /* < USB host clock enable */
31#define CKEN_CAMERA 3 /* < Camera interface clock enable */
32#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */
33#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */
34#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */
35#define CKEN_SMC 9 /* < Static Memory Controller clock enable */
36#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */
37#define CKEN_BOOT 11 /* < Boot rom clock enable */
38#define CKEN_MMC1 12 /* < MMC1 Clock enable */
39#define CKEN_MMC2 13 /* < MMC2 clock enable */
40#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */
41#define CKEN_CIR 15 /* < Consumer IR Clock Enable */
42#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */
43#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */
44#define CKEN_TPM 19 /* < TPM clock enable */
45#define CKEN_UDC 20 /* < UDC clock enable */
46#define CKEN_BTUART 21 /* < BTUART clock enable */
47#define CKEN_FFUART 22 /* < FFUART clock enable */
48#define CKEN_STUART 23 /* < STUART clock enable */
49#define CKEN_AC97 24 /* < AC97 clock enable */
50#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */
51#define CKEN_SSP1 26 /* < SSP1 clock enable */
52#define CKEN_SSP2 27 /* < SSP2 clock enable */
53#define CKEN_SSP3 28 /* < SSP3 clock enable */
54#define CKEN_SSP4 29 /* < SSP4 clock enable */
55#define CKEN_MSL0 30 /* < MSL0 clock enable */
56#define CKEN_PWM0 32 /* < PWM[0] clock enable */
57#define CKEN_PWM1 33 /* < PWM[1] clock enable */
58#define CKEN_I2C 36 /* < I2C clock enable */
59#define CKEN_INTC 38 /* < Interrupt controller clock enable */
60#define CKEN_GPIO 39 /* < GPIO clock enable */
61#define CKEN_1WIRE 40 /* < 1-wire clock enable */
62#define CKEN_HSIO2 41 /* < HSIO2 clock enable */
63#define CKEN_MINI_IM 48 /* < Mini-IM */
64#define CKEN_MINI_LCD 49 /* < Mini LCD */
65
66#if defined(CONFIG_CPU_PXA310)
67#define CKEN_MMC3 5 /* < MMC3 Clock Enable */
68#define CKEN_MVED 43 /* < MVED clock enable */
69#endif
70
71/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */
72#define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */
73#define PXA320_CKEN_GRAPHICS 7 /* Graphics controller clock enable */
74
75#endif /* __ASM_ARCH_PXA3XX_REGS_H */
diff --git a/include/asm-arm/arch-pxa/timex.h b/include/asm-arm/arch-pxa/timex.h
index 2473bb51d0a6..8d882f0b6a16 100644
--- a/include/asm-arm/arch-pxa/timex.h
+++ b/include/asm-arm/arch-pxa/timex.h
@@ -21,4 +21,6 @@
21#else 21#else
22#define CLOCK_TICK_RATE 3250000 22#define CLOCK_TICK_RATE 3250000
23#endif 23#endif
24#else
25#define CLOCK_TICK_RATE 3250000
24#endif 26#endif
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
new file mode 100644
index 000000000000..f58b59162b82
--- /dev/null
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -0,0 +1,35 @@
1#ifndef __ASM_ARCH_ZYLONITE_H
2#define __ASM_ARCH_ZYLONITE_H
3
4#define ZYLONITE_ETH_PHYS 0x14000000
5
6/* the following variables are processor specific and initialized
7 * by the corresponding zylonite_pxa3xx_init()
8 */
9extern int gpio_backlight;
10extern int gpio_eth_irq;
11
12extern int lcd_id;
13extern int lcd_orientation;
14
15#ifdef CONFIG_CPU_PXA300
16extern void zylonite_pxa300_init(void);
17#else
18static inline void zylonite_pxa300_init(void)
19{
20 if (cpu_is_pxa300() || cpu_is_pxa310())
21 panic("%s: PXA300/PXA310 not supported\n", __FUNCTION__);
22}
23#endif
24
25#ifdef CONFIG_CPU_PXA320
26extern void zylonite_pxa320_init(void);
27#else
28static inline void zylonite_pxa320_init(void)
29{
30 if (cpu_is_pxa320())
31 panic("%s: PXA320 not supported\n", __FUNCTION__);
32}
33#endif
34
35#endif /* __ASM_ARCH_ZYLONITE_H */
diff --git a/include/asm-arm/hardware/it8152.h b/include/asm-arm/hardware/it8152.h
new file mode 100644
index 000000000000..aaebb61aca48
--- /dev/null
+++ b/include/asm-arm/hardware/it8152.h
@@ -0,0 +1,99 @@
1/*
2 * linux/include/arm/hardware/it8152.h
3 *
4 * Copyright Compulab Ltd., 2006,2007
5 * Mike Rapoport <mike@compulab.co.il>
6 *
7 * ITE 8152 companion chip register definitions
8 */
9
10#ifndef __ASM_HARDWARE_IT8152_H
11#define __ASM_HARDWARE_IT8152_H
12extern unsigned long it8152_base_address;
13
14#define IT8152_IO_BASE (it8152_base_address + 0x03e00000)
15#define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000)
16
17#define __REG_IT8152(x) (it8152_base_address + (x))
18
19#define IT8152_PCI_CFG_ADDR __REG_IT8152(0x3f00800)
20#define IT8152_PCI_CFG_DATA __REG_IT8152(0x3f00804)
21
22#define IT8152_INTC_LDCNIRR __REG_IT8152(0x3f00300)
23#define IT8152_INTC_LDPNIRR __REG_IT8152(0x3f00304)
24#define IT8152_INTC_LDCNIMR __REG_IT8152(0x3f00308)
25#define IT8152_INTC_LDPNIMR __REG_IT8152(0x3f0030C)
26#define IT8152_INTC_LDNITR __REG_IT8152(0x3f00310)
27#define IT8152_INTC_LDNIAR __REG_IT8152(0x3f00314)
28#define IT8152_INTC_LPCNIRR __REG_IT8152(0x3f00320)
29#define IT8152_INTC_LPPNIRR __REG_IT8152(0x3f00324)
30#define IT8152_INTC_LPCNIMR __REG_IT8152(0x3f00328)
31#define IT8152_INTC_LPPNIMR __REG_IT8152(0x3f0032C)
32#define IT8152_INTC_LPNITR __REG_IT8152(0x3f00330)
33#define IT8152_INTC_LPNIAR __REG_IT8152(0x3f00334)
34#define IT8152_INTC_PDCNIRR __REG_IT8152(0x3f00340)
35#define IT8152_INTC_PDPNIRR __REG_IT8152(0x3f00344)
36#define IT8152_INTC_PDCNIMR __REG_IT8152(0x3f00348)
37#define IT8152_INTC_PDPNIMR __REG_IT8152(0x3f0034C)
38#define IT8152_INTC_PDNITR __REG_IT8152(0x3f00350)
39#define IT8152_INTC_PDNIAR __REG_IT8152(0x3f00354)
40#define IT8152_INTC_INTC_TYPER __REG_IT8152(0x3f003FC)
41
42#define IT8152_GPIO_GPDR __REG_IT8152(0x3f00500)
43
44/*
45 Interrup contoler per register summary:
46 ---------------------------------------
47 LCDNIRR:
48 IT8152_LD_IRQ(8) PCICLK stop
49 IT8152_LD_IRQ(7) MCLK ready
50 IT8152_LD_IRQ(6) s/w
51 IT8152_LD_IRQ(5) UART
52 IT8152_LD_IRQ(4) GPIO
53 IT8152_LD_IRQ(3) TIMER 4
54 IT8152_LD_IRQ(2) TIMER 3
55 IT8152_LD_IRQ(1) TIMER 2
56 IT8152_LD_IRQ(0) TIMER 1
57
58 LPCNIRR:
59 IT8152_LP_IRQ(x) serial IRQ x
60
61 PCIDNIRR:
62 IT8152_PD_IRQ(14) PCISERR
63 IT8152_PD_IRQ(13) CPU/PCI bridge target abort (h2pTADR)
64 IT8152_PD_IRQ(12) CPU/PCI bridge master abort (h2pMADR)
65 IT8152_PD_IRQ(11) PCI INTD
66 IT8152_PD_IRQ(10) PCI INTC
67 IT8152_PD_IRQ(9) PCI INTB
68 IT8152_PD_IRQ(8) PCI INTA
69 IT8152_PD_IRQ(7) serial INTD
70 IT8152_PD_IRQ(6) serial INTC
71 IT8152_PD_IRQ(5) serial INTB
72 IT8152_PD_IRQ(4) serial INTA
73 IT8152_PD_IRQ(3) serial IRQ IOCHK (IOCHKR)
74 IT8152_PD_IRQ(2) chaining DMA (CDMAR)
75 IT8152_PD_IRQ(1) USB (USBR)
76 IT8152_PD_IRQ(0) Audio controller (ACR)
77 */
78/* frequently used interrupts */
79#define IT8152_PCISERR IT8152_PD_IRQ(14)
80#define IT8152_H2PTADR IT8152_PD_IRQ(13)
81#define IT8152_H2PMAR IT8152_PD_IRQ(12)
82#define IT8152_PCI_INTD IT8152_PD_IRQ(11)
83#define IT8152_PCI_INTC IT8152_PD_IRQ(10)
84#define IT8152_PCI_INTB IT8152_PD_IRQ(9)
85#define IT8152_PCI_INTA IT8152_PD_IRQ(8)
86#define IT8152_CDMA_INT IT8152_PD_IRQ(2)
87#define IT8152_USB_INT IT8152_PD_IRQ(1)
88#define IT8152_AUDIO_INT IT8152_PD_IRQ(0)
89
90struct pci_dev;
91struct pci_sys_data;
92
93extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc);
94extern void it8152_init_irq(void);
95extern int it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
96extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
97extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys);
98
99#endif /* __ASM_HARDWARE_IT8152_H */
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
index ed3f898191f4..75feb1574a69 100644
--- a/include/asm-arm/pci.h
+++ b/include/asm-arm/pci.h
@@ -8,10 +8,17 @@
8 8
9#define pcibios_scan_all_fns(a, b) 0 9#define pcibios_scan_all_fns(a, b) 0
10 10
11#ifdef CONFIG_PCI_HOST_ITE8152
12/* ITE bridge requires setting latency timer to avoid early bus access
13 termination by PIC bus mater devices
14*/
15extern void pcibios_set_master(struct pci_dev *dev);
16#else
11static inline void pcibios_set_master(struct pci_dev *dev) 17static inline void pcibios_set_master(struct pci_dev *dev)
12{ 18{
13 /* No special bus mastering setup handling */ 19 /* No special bus mastering setup handling */
14} 20}
21#endif
15 22
16static inline void pcibios_penalize_isa_irq(int irq, int active) 23static inline void pcibios_penalize_isa_irq(int irq, int active)
17{ 24{
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 3948708c42ca..2bcb02d555e8 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1631,6 +1631,7 @@
1631#define PCI_DEVICE_ID_ITE_8211 0x8211 1631#define PCI_DEVICE_ID_ITE_8211 0x8211
1632#define PCI_DEVICE_ID_ITE_8212 0x8212 1632#define PCI_DEVICE_ID_ITE_8212 0x8212
1633#define PCI_DEVICE_ID_ITE_8213 0x8213 1633#define PCI_DEVICE_ID_ITE_8213 0x8213
1634#define PCI_DEVICE_ID_ITE_8152 0x8152
1634#define PCI_DEVICE_ID_ITE_8872 0x8872 1635#define PCI_DEVICE_ID_ITE_8872 0x8872
1635#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886 1636#define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886
1636 1637
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 05:26:17 -0500