diff options
1280 files changed, 64187 insertions, 37340 deletions
| @@ -3738,7 +3738,7 @@ S: 93149 Nittenau | |||
| 3738 | S: Germany | 3738 | S: Germany |
| 3739 | 3739 | ||
| 3740 | N: Gertjan van Wingerde | 3740 | N: Gertjan van Wingerde |
| 3741 | E: gwingerde@home.nl | 3741 | E: gwingerde@gmail.com |
| 3742 | D: Ralink rt2x00 WLAN driver | 3742 | D: Ralink rt2x00 WLAN driver |
| 3743 | D: Minix V2 file-system | 3743 | D: Minix V2 file-system |
| 3744 | D: Misc fixes | 3744 | D: Misc fixes |
diff --git a/Documentation/RCU/checklist.txt b/Documentation/RCU/checklist.txt index 6e253407b3dc..accfe2f5247d 100644 --- a/Documentation/RCU/checklist.txt +++ b/Documentation/RCU/checklist.txt | |||
| @@ -298,3 +298,15 @@ over a rather long period of time, but improvements are always welcome! | |||
| 298 | 298 | ||
| 299 | Note that, rcu_assign_pointer() and rcu_dereference() relate to | 299 | Note that, rcu_assign_pointer() and rcu_dereference() relate to |
| 300 | SRCU just as they do to other forms of RCU. | 300 | SRCU just as they do to other forms of RCU. |
| 301 | |||
| 302 | 15. The whole point of call_rcu(), synchronize_rcu(), and friends | ||
| 303 | is to wait until all pre-existing readers have finished before | ||
| 304 | carrying out some otherwise-destructive operation. It is | ||
| 305 | therefore critically important to -first- remove any path | ||
| 306 | that readers can follow that could be affected by the | ||
| 307 | destructive operation, and -only- -then- invoke call_rcu(), | ||
| 308 | synchronize_rcu(), or friends. | ||
| 309 | |||
| 310 | Because these primitives only wait for pre-existing readers, | ||
| 311 | it is the caller's responsibility to guarantee safety to | ||
| 312 | any subsequent readers. | ||
diff --git a/Documentation/arm/Samsung-S3C24XX/Suspend.txt b/Documentation/arm/Samsung-S3C24XX/Suspend.txt index 0dab6e32c130..a30fe510572b 100644 --- a/Documentation/arm/Samsung-S3C24XX/Suspend.txt +++ b/Documentation/arm/Samsung-S3C24XX/Suspend.txt | |||
| @@ -40,13 +40,13 @@ Resuming | |||
| 40 | Machine Support | 40 | Machine Support |
| 41 | --------------- | 41 | --------------- |
| 42 | 42 | ||
| 43 | The machine specific functions must call the s3c2410_pm_init() function | 43 | The machine specific functions must call the s3c_pm_init() function |
| 44 | to say that its bootloader is capable of resuming. This can be as | 44 | to say that its bootloader is capable of resuming. This can be as |
| 45 | simple as adding the following to the machine's definition: | 45 | simple as adding the following to the machine's definition: |
| 46 | 46 | ||
| 47 | INITMACHINE(s3c2410_pm_init) | 47 | INITMACHINE(s3c_pm_init) |
| 48 | 48 | ||
| 49 | A board can do its own setup before calling s3c2410_pm_init, if it | 49 | A board can do its own setup before calling s3c_pm_init, if it |
| 50 | needs to setup anything else for power management support. | 50 | needs to setup anything else for power management support. |
| 51 | 51 | ||
| 52 | There is currently no support for over-riding the default method of | 52 | There is currently no support for over-riding the default method of |
| @@ -74,7 +74,7 @@ statuc void __init machine_init(void) | |||
| 74 | 74 | ||
| 75 | enable_irq_wake(IRQ_EINT0); | 75 | enable_irq_wake(IRQ_EINT0); |
| 76 | 76 | ||
| 77 | s3c2410_pm_init(); | 77 | s3c_pm_init(); |
| 78 | } | 78 | } |
| 79 | 79 | ||
| 80 | 80 | ||
diff --git a/Documentation/arm/memory.txt b/Documentation/arm/memory.txt index dc6045577a8b..43cb1004d35f 100644 --- a/Documentation/arm/memory.txt +++ b/Documentation/arm/memory.txt | |||
| @@ -29,7 +29,14 @@ ffff0000 ffff0fff CPU vector page. | |||
| 29 | CPU supports vector relocation (control | 29 | CPU supports vector relocation (control |
| 30 | register V bit.) | 30 | register V bit.) |
| 31 | 31 | ||
| 32 | ffc00000 fffeffff DMA memory mapping region. Memory returned | 32 | fffe0000 fffeffff XScale cache flush area. This is used |
| 33 | in proc-xscale.S to flush the whole data | ||
| 34 | cache. Free for other usage on non-XScale. | ||
| 35 | |||
| 36 | fff00000 fffdffff Fixmap mapping region. Addresses provided | ||
| 37 | by fix_to_virt() will be located here. | ||
| 38 | |||
| 39 | ffc00000 ffefffff DMA memory mapping region. Memory returned | ||
| 33 | by the dma_alloc_xxx functions will be | 40 | by the dma_alloc_xxx functions will be |
| 34 | dynamically mapped here. | 41 | dynamically mapped here. |
| 35 | 42 | ||
diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt index 5ddbe350487a..20d3b94703a4 100644 --- a/Documentation/feature-removal-schedule.txt +++ b/Documentation/feature-removal-schedule.txt | |||
| @@ -335,3 +335,12 @@ Why: In 2.6.18 the Secmark concept was introduced to replace the "compat_net" | |||
| 335 | Secmark, it is time to deprecate the older mechanism and start the | 335 | Secmark, it is time to deprecate the older mechanism and start the |
| 336 | process of removing the old code. | 336 | process of removing the old code. |
| 337 | Who: Paul Moore <paul.moore@hp.com> | 337 | Who: Paul Moore <paul.moore@hp.com> |
| 338 | --------------------------- | ||
| 339 | |||
| 340 | What: sysfs ui for changing p4-clockmod parameters | ||
| 341 | When: September 2009 | ||
| 342 | Why: See commits 129f8ae9b1b5be94517da76009ea956e89104ce8 and | ||
| 343 | e088e4c9cdb618675874becb91b2fd581ee707e6. | ||
| 344 | Removal is subject to fixing any remaining bugs in ACPI which may | ||
| 345 | cause the thermal throttling not to happen at the right time. | ||
| 346 | Who: Dave Jones <davej@redhat.com>, Matthew Garrett <mjg@redhat.com> | ||
diff --git a/Documentation/filesystems/ext2.txt b/Documentation/filesystems/ext2.txt index 4333e836c495..e055acb6b2d4 100644 --- a/Documentation/filesystems/ext2.txt +++ b/Documentation/filesystems/ext2.txt | |||
| @@ -373,10 +373,11 @@ Filesystem Resizing http://ext2resize.sourceforge.net/ | |||
| 373 | Compression (*) http://e2compr.sourceforge.net/ | 373 | Compression (*) http://e2compr.sourceforge.net/ |
| 374 | 374 | ||
| 375 | Implementations for: | 375 | Implementations for: |
| 376 | Windows 95/98/NT/2000 http://uranus.it.swin.edu.au/~jn/linux/Explore2fs.htm | 376 | Windows 95/98/NT/2000 http://www.chrysocome.net/explore2fs |
| 377 | Windows 95 (*) http://www.yipton.demon.co.uk/content.html#FSDEXT2 | 377 | Windows 95 (*) http://www.yipton.net/content.html#FSDEXT2 |
| 378 | DOS client (*) ftp://metalab.unc.edu/pub/Linux/system/filesystems/ext2/ | 378 | DOS client (*) ftp://metalab.unc.edu/pub/Linux/system/filesystems/ext2/ |
| 379 | OS/2 http://perso.wanadoo.fr/matthieu.willm/ext2-os2/ | 379 | OS/2 (+) ftp://metalab.unc.edu/pub/Linux/system/filesystems/ext2/ |
| 380 | RISC OS client ftp://ftp.barnet.ac.uk/pub/acorn/armlinux/iscafs/ | 380 | RISC OS client http://www.esw-heim.tu-clausthal.de/~marco/smorbrod/IscaFS/ |
| 381 | 381 | ||
| 382 | (*) no longer actively developed/supported (as of Apr 2001) | 382 | (*) no longer actively developed/supported (as of Apr 2001) |
| 383 | (+) no longer actively developed/supported (as of Mar 2009) | ||
diff --git a/Documentation/filesystems/ext3.txt b/Documentation/filesystems/ext3.txt index 9dd2a3bb2acc..e5f3833a6ef8 100644 --- a/Documentation/filesystems/ext3.txt +++ b/Documentation/filesystems/ext3.txt | |||
| @@ -198,5 +198,5 @@ kernel source: <file:fs/ext3/> | |||
| 198 | programs: http://e2fsprogs.sourceforge.net/ | 198 | programs: http://e2fsprogs.sourceforge.net/ |
| 199 | http://ext2resize.sourceforge.net | 199 | http://ext2resize.sourceforge.net |
| 200 | 200 | ||
| 201 | useful links: http://www-106.ibm.com/developerworks/linux/library/l-fs7/ | 201 | useful links: http://www.ibm.com/developerworks/library/l-fs7.html |
| 202 | http://www-106.ibm.com/developerworks/linux/library/l-fs8/ | 202 | http://www.ibm.com/developerworks/library/l-fs8.html |
diff --git a/Documentation/filesystems/proc.txt b/Documentation/filesystems/proc.txt index a87be42f8211..830bad7cce0f 100644 --- a/Documentation/filesystems/proc.txt +++ b/Documentation/filesystems/proc.txt | |||
| @@ -1478,6 +1478,13 @@ of problems on the network like duplicate address or bad checksums. Normally, | |||
| 1478 | this should be enabled, but if the problem persists the messages can be | 1478 | this should be enabled, but if the problem persists the messages can be |
| 1479 | disabled. | 1479 | disabled. |
| 1480 | 1480 | ||
| 1481 | netdev_budget | ||
| 1482 | ------------- | ||
| 1483 | |||
| 1484 | Maximum number of packets taken from all interfaces in one polling cycle (NAPI | ||
| 1485 | poll). In one polling cycle interfaces which are registered to polling are | ||
| 1486 | probed in a round-robin manner. The limit of packets in one such probe can be | ||
| 1487 | set per-device via sysfs class/net/<device>/weight . | ||
| 1481 | 1488 | ||
| 1482 | netdev_max_backlog | 1489 | netdev_max_backlog |
| 1483 | ------------------ | 1490 | ------------------ |
diff --git a/Documentation/filesystems/squashfs.txt b/Documentation/filesystems/squashfs.txt index 3e79e4a7a392..b324c033035a 100644 --- a/Documentation/filesystems/squashfs.txt +++ b/Documentation/filesystems/squashfs.txt | |||
| @@ -22,7 +22,7 @@ Squashfs filesystem features versus Cramfs: | |||
| 22 | 22 | ||
| 23 | Squashfs Cramfs | 23 | Squashfs Cramfs |
| 24 | 24 | ||
| 25 | Max filesystem size: 2^64 16 MiB | 25 | Max filesystem size: 2^64 256 MiB |
| 26 | Max file size: ~ 2 TiB 16 MiB | 26 | Max file size: ~ 2 TiB 16 MiB |
| 27 | Max files: unlimited unlimited | 27 | Max files: unlimited unlimited |
| 28 | Max directories: unlimited unlimited | 28 | Max directories: unlimited unlimited |
diff --git a/Documentation/hwmon/lm90 b/Documentation/hwmon/lm90 index 0e8411710238..93d8e3d55150 100644 --- a/Documentation/hwmon/lm90 +++ b/Documentation/hwmon/lm90 | |||
| @@ -42,6 +42,11 @@ Supported chips: | |||
| 42 | Addresses scanned: I2C 0x4e | 42 | Addresses scanned: I2C 0x4e |
| 43 | Datasheet: Publicly available at the Maxim website | 43 | Datasheet: Publicly available at the Maxim website |
| 44 | http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3497 | 44 | http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3497 |
| 45 | * Maxim MAX6648 | ||
| 46 | Prefix: 'max6646' | ||
| 47 | Addresses scanned: I2C 0x4c | ||
| 48 | Datasheet: Publicly available at the Maxim website | ||
| 49 | http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3500 | ||
| 45 | * Maxim MAX6649 | 50 | * Maxim MAX6649 |
| 46 | Prefix: 'max6646' | 51 | Prefix: 'max6646' |
| 47 | Addresses scanned: I2C 0x4c | 52 | Addresses scanned: I2C 0x4c |
| @@ -74,6 +79,11 @@ Supported chips: | |||
| 74 | 0x4c, 0x4d and 0x4e | 79 | 0x4c, 0x4d and 0x4e |
| 75 | Datasheet: Publicly available at the Maxim website | 80 | Datasheet: Publicly available at the Maxim website |
| 76 | http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3370 | 81 | http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3370 |
| 82 | * Maxim MAX6692 | ||
| 83 | Prefix: 'max6646' | ||
| 84 | Addresses scanned: I2C 0x4c | ||
| 85 | Datasheet: Publicly available at the Maxim website | ||
| 86 | http://www.maxim-ic.com/quick_view2.cfm/qv_pk/3500 | ||
| 77 | 87 | ||
| 78 | 88 | ||
| 79 | Author: Jean Delvare <khali@linux-fr.org> | 89 | Author: Jean Delvare <khali@linux-fr.org> |
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index 54f21a5c262b..ef9827f7c84e 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt | |||
| @@ -830,6 +830,12 @@ and is between 256 and 4096 characters. It is defined in the file | |||
| 830 | hvc_iucv= [S390] Number of z/VM IUCV hypervisor console (HVC) | 830 | hvc_iucv= [S390] Number of z/VM IUCV hypervisor console (HVC) |
| 831 | terminal devices. Valid values: 0..8 | 831 | terminal devices. Valid values: 0..8 |
| 832 | 832 | ||
| 833 | i2c_bus= [HW] Override the default board specific I2C bus speed | ||
| 834 | or register an additional I2C bus that is not | ||
| 835 | registered from board initialization code. | ||
| 836 | Format: | ||
| 837 | <bus_id>,<clkrate> | ||
| 838 | |||
| 833 | i8042.debug [HW] Toggle i8042 debug mode | 839 | i8042.debug [HW] Toggle i8042 debug mode |
| 834 | i8042.direct [HW] Put keyboard port into non-translated mode | 840 | i8042.direct [HW] Put keyboard port into non-translated mode |
| 835 | i8042.dumbkbd [HW] Pretend that controller can only read data from | 841 | i8042.dumbkbd [HW] Pretend that controller can only read data from |
diff --git a/Documentation/logo.gif b/Documentation/logo.gif deleted file mode 100644 index 2eae75fecfb9..000000000000 --- a/Documentation/logo.gif +++ /dev/null | |||
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diff --git a/Documentation/logo.txt b/Documentation/logo.txt index 296f0f7f67eb..a2e62445e28e 100644 --- a/Documentation/logo.txt +++ b/Documentation/logo.txt | |||
| @@ -1,13 +1,4 @@ | |||
| 1 | This is the full-colour version of the currently unofficial Linux logo | 1 | Tux is taking a three month sabbatical to work as a barber, so Tuz is |
| 2 | ("currently unofficial" just means that there has been no paperwork and | 2 | standing in. He's taken pains to ensure you'll hardly notice. |
| 3 | that I have not really announced it yet). It was created by Larry Ewing, | ||
| 4 | and is freely usable as long as you acknowledge Larry as the original | ||
| 5 | artist. | ||
| 6 | |||
| 7 | Note that there are black-and-white versions of this available that | ||
| 8 | scale down to smaller sizes and are better for letterheads or whatever | ||
| 9 | you want to use it for: for the full range of logos take a look at | ||
| 10 | Larry's web-page: | ||
| 11 | |||
| 12 | http://www.isc.tamu.edu/~lewing/linux/ | ||
| 13 | 3 | ||
| 4 | Image by Andrew McGown and Josh Bush. Image is licensed CC BY-SA. | ||
diff --git a/Documentation/networking/ipv6.txt b/Documentation/networking/ipv6.txt new file mode 100644 index 000000000000..268e5c103dd8 --- /dev/null +++ b/Documentation/networking/ipv6.txt | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | |||
| 2 | Options for the ipv6 module are supplied as parameters at load time. | ||
| 3 | |||
| 4 | Module options may be given as command line arguments to the insmod | ||
| 5 | or modprobe command, but are usually specified in either the | ||
| 6 | /etc/modules.conf or /etc/modprobe.conf configuration file, or in a | ||
| 7 | distro-specific configuration file. | ||
| 8 | |||
| 9 | The available ipv6 module parameters are listed below. If a parameter | ||
| 10 | is not specified the default value is used. | ||
| 11 | |||
| 12 | The parameters are as follows: | ||
| 13 | |||
| 14 | disable | ||
| 15 | |||
| 16 | Specifies whether to load the IPv6 module, but disable all | ||
| 17 | its functionality. This might be used when another module | ||
| 18 | has a dependency on the IPv6 module being loaded, but no | ||
| 19 | IPv6 addresses or operations are desired. | ||
| 20 | |||
| 21 | The possible values and their effects are: | ||
| 22 | |||
| 23 | 0 | ||
| 24 | IPv6 is enabled. | ||
| 25 | |||
| 26 | This is the default value. | ||
| 27 | |||
| 28 | 1 | ||
| 29 | IPv6 is disabled. | ||
| 30 | |||
| 31 | No IPv6 addresses will be added to interfaces, and | ||
| 32 | it will not be possible to open an IPv6 socket. | ||
| 33 | |||
| 34 | A reboot is required to enable IPv6. | ||
| 35 | |||
diff --git a/MAINTAINERS b/MAINTAINERS index 1c2ca1dc66f2..50725d026da0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS | |||
| @@ -622,7 +622,7 @@ P: Dirk Opfer | |||
| 622 | M: dirk@opfer-online.de | 622 | M: dirk@opfer-online.de |
| 623 | S: Maintained | 623 | S: Maintained |
| 624 | 624 | ||
| 625 | ARM/PALMTX SUPPORT | 625 | ARM/PALMTX,PALMT5,PALMLD SUPPORT |
| 626 | P: Marek Vasut | 626 | P: Marek Vasut |
| 627 | M: marek.vasut@gmail.com | 627 | M: marek.vasut@gmail.com |
| 628 | W: http://hackndev.com | 628 | W: http://hackndev.com |
| @@ -1469,8 +1469,6 @@ L: linux-acpi@vger.kernel.org | |||
| 1469 | S: Supported | 1469 | S: Supported |
| 1470 | 1470 | ||
| 1471 | DOCUMENTATION (/Documentation directory) | 1471 | DOCUMENTATION (/Documentation directory) |
| 1472 | P: Michael Kerrisk | ||
| 1473 | M: mtk.manpages@gmail.com | ||
| 1474 | P: Randy Dunlap | 1472 | P: Randy Dunlap |
| 1475 | M: rdunlap@xenotime.net | 1473 | M: rdunlap@xenotime.net |
| 1476 | L: linux-doc@vger.kernel.org | 1474 | L: linux-doc@vger.kernel.org |
| @@ -2879,7 +2877,7 @@ P: Michael Kerrisk | |||
| 2879 | M: mtk.manpages@gmail.com | 2877 | M: mtk.manpages@gmail.com |
| 2880 | W: http://www.kernel.org/doc/man-pages | 2878 | W: http://www.kernel.org/doc/man-pages |
| 2881 | L: linux-man@vger.kernel.org | 2879 | L: linux-man@vger.kernel.org |
| 2882 | S: Supported | 2880 | S: Maintained |
| 2883 | 2881 | ||
| 2884 | MARVELL LIBERTAS WIRELESS DRIVER | 2882 | MARVELL LIBERTAS WIRELESS DRIVER |
| 2885 | P: Dan Williams | 2883 | P: Dan Williams |
| @@ -3352,10 +3350,8 @@ S: Maintained | |||
| 3352 | PARISC ARCHITECTURE | 3350 | PARISC ARCHITECTURE |
| 3353 | P: Kyle McMartin | 3351 | P: Kyle McMartin |
| 3354 | M: kyle@mcmartin.ca | 3352 | M: kyle@mcmartin.ca |
| 3355 | P: Matthew Wilcox | 3353 | P: Helge Deller |
| 3356 | M: matthew@wil.cx | 3354 | M: deller@gmx.de |
| 3357 | P: Grant Grundler | ||
| 3358 | M: grundler@parisc-linux.org | ||
| 3359 | L: linux-parisc@vger.kernel.org | 3355 | L: linux-parisc@vger.kernel.org |
| 3360 | W: http://www.parisc-linux.org/ | 3356 | W: http://www.parisc-linux.org/ |
| 3361 | T: git kernel.org:/pub/scm/linux/kernel/git/kyle/parisc-2.6.git | 3357 | T: git kernel.org:/pub/scm/linux/kernel/git/kyle/parisc-2.6.git |
| @@ -3543,6 +3539,22 @@ M: linux@arm.linux.org.uk | |||
| 3543 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | 3539 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) |
| 3544 | S: Maintained | 3540 | S: Maintained |
| 3545 | 3541 | ||
| 3542 | PXA168 SUPPORT | ||
| 3543 | P: Eric Miao | ||
| 3544 | M: eric.miao@marvell.com | ||
| 3545 | P: Jason Chagas | ||
| 3546 | M: jason.chagas@marvell.com | ||
| 3547 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | ||
| 3548 | T: git kernel.org:/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git | ||
| 3549 | S: Supported | ||
| 3550 | |||
| 3551 | PXA910 SUPPORT | ||
| 3552 | P: Eric Miao | ||
| 3553 | M: eric.miao@marvell.com | ||
| 3554 | L: linux-arm-kernel@lists.arm.linux.org.uk (subscribers-only) | ||
| 3555 | T: git kernel.org:/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git | ||
| 3556 | S: Supported | ||
| 3557 | |||
| 3546 | PXA MMCI DRIVER | 3558 | PXA MMCI DRIVER |
| 3547 | S: Orphan | 3559 | S: Orphan |
| 3548 | 3560 | ||
| @@ -3880,6 +3892,15 @@ L: linux-ide@vger.kernel.org | |||
| 3880 | T: git kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev.git | 3892 | T: git kernel.org:/pub/scm/linux/kernel/git/jgarzik/libata-dev.git |
| 3881 | S: Supported | 3893 | S: Supported |
| 3882 | 3894 | ||
| 3895 | SERVER ENGINES 10Gbps NIC - BladeEngine 2 DRIVER | ||
| 3896 | P: Sathya Perla | ||
| 3897 | M: sathyap@serverengines.com | ||
| 3898 | P: Subbu Seetharaman | ||
| 3899 | M: subbus@serverengines.com | ||
| 3900 | L: netdev@vger.kernel.org | ||
| 3901 | W: http://www.serverengines.com | ||
| 3902 | S: Supported | ||
| 3903 | |||
| 3883 | SFC NETWORK DRIVER | 3904 | SFC NETWORK DRIVER |
| 3884 | P: Steve Hodgson | 3905 | P: Steve Hodgson |
| 3885 | P: Ben Hutchings | 3906 | P: Ben Hutchings |
| @@ -1,8 +1,8 @@ | |||
| 1 | VERSION = 2 | 1 | VERSION = 2 |
| 2 | PATCHLEVEL = 6 | 2 | PATCHLEVEL = 6 |
| 3 | SUBLEVEL = 29 | 3 | SUBLEVEL = 29 |
| 4 | EXTRAVERSION = -rc7 | 4 | EXTRAVERSION = |
| 5 | NAME = Erotic Pickled Herring | 5 | NAME = Temporary Tasmanian Devil |
| 6 | 6 | ||
| 7 | # *DOCUMENTATION* | 7 | # *DOCUMENTATION* |
| 8 | # To see a list of typical targets execute "make help" | 8 | # To see a list of typical targets execute "make help" |
| @@ -566,6 +566,12 @@ KBUILD_CFLAGS += $(call cc-option,-Wdeclaration-after-statement,) | |||
| 566 | # disable pointer signed / unsigned warnings in gcc 4.0 | 566 | # disable pointer signed / unsigned warnings in gcc 4.0 |
| 567 | KBUILD_CFLAGS += $(call cc-option,-Wno-pointer-sign,) | 567 | KBUILD_CFLAGS += $(call cc-option,-Wno-pointer-sign,) |
| 568 | 568 | ||
| 569 | # disable invalid "can't wrap" optimzations for signed / pointers | ||
| 570 | KBUILD_CFLAGS += $(call cc-option,-fwrapv) | ||
| 571 | |||
| 572 | # revert to pre-gcc-4.4 behaviour of .eh_frame | ||
| 573 | KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm) | ||
| 574 | |||
| 569 | # Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments | 575 | # Add user supplied CPPFLAGS, AFLAGS and CFLAGS as the last assignments |
| 570 | # But warn user when we do so | 576 | # But warn user when we do so |
| 571 | warn-assign = \ | 577 | warn-assign = \ |
| @@ -904,12 +910,18 @@ localver = $(subst $(space),, $(string) \ | |||
| 904 | # and if the SCM is know a tag from the SCM is appended. | 910 | # and if the SCM is know a tag from the SCM is appended. |
| 905 | # The appended tag is determined by the SCM used. | 911 | # The appended tag is determined by the SCM used. |
| 906 | # | 912 | # |
| 907 | # Currently, only git is supported. | 913 | # .scmversion is used when generating rpm packages so we do not loose |
| 908 | # Other SCMs can edit scripts/setlocalversion and add the appropriate | 914 | # the version information from the SCM when we do the build of the kernel |
| 909 | # checks as needed. | 915 | # from the copied source |
| 910 | ifdef CONFIG_LOCALVERSION_AUTO | 916 | ifdef CONFIG_LOCALVERSION_AUTO |
| 911 | _localver-auto = $(shell $(CONFIG_SHELL) \ | 917 | |
| 912 | $(srctree)/scripts/setlocalversion $(srctree)) | 918 | ifeq ($(wildcard .scmversion),) |
| 919 | _localver-auto = $(shell $(CONFIG_SHELL) \ | ||
| 920 | $(srctree)/scripts/setlocalversion $(srctree)) | ||
| 921 | else | ||
| 922 | _localver-auto = $(shell cat .scmversion 2> /dev/null) | ||
| 923 | endif | ||
| 924 | |||
| 913 | localver-auto = $(LOCALVERSION)$(_localver-auto) | 925 | localver-auto = $(LOCALVERSION)$(_localver-auto) |
| 914 | endif | 926 | endif |
| 915 | 927 | ||
| @@ -1537,7 +1549,7 @@ quiet_cmd_depmod = DEPMOD $(KERNELRELEASE) | |||
| 1537 | cmd_depmod = \ | 1549 | cmd_depmod = \ |
| 1538 | if [ -r System.map -a -x $(DEPMOD) ]; then \ | 1550 | if [ -r System.map -a -x $(DEPMOD) ]; then \ |
| 1539 | $(DEPMOD) -ae -F System.map \ | 1551 | $(DEPMOD) -ae -F System.map \ |
| 1540 | $(if $(strip $(INSTALL_MOD_PATH)), -b $(INSTALL_MOD_PATH) -r) \ | 1552 | $(if $(strip $(INSTALL_MOD_PATH)), -b $(INSTALL_MOD_PATH) ) \ |
| 1541 | $(KERNELRELEASE); \ | 1553 | $(KERNELRELEASE); \ |
| 1542 | fi | 1554 | fi |
| 1543 | 1555 | ||
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index dbfdf87f993f..e62b37a15a1d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
| @@ -241,6 +241,7 @@ config ARCH_VERSATILE | |||
| 241 | config ARCH_AT91 | 241 | config ARCH_AT91 |
| 242 | bool "Atmel AT91" | 242 | bool "Atmel AT91" |
| 243 | select GENERIC_GPIO | 243 | select GENERIC_GPIO |
| 244 | select ARCH_REQUIRE_GPIOLIB | ||
| 244 | select HAVE_CLK | 245 | select HAVE_CLK |
| 245 | help | 246 | help |
| 246 | This enables support for systems based on the Atmel AT91RM9200, | 247 | This enables support for systems based on the Atmel AT91RM9200, |
| @@ -477,12 +478,29 @@ config ARCH_PXA | |||
| 477 | select HAVE_CLK | 478 | select HAVE_CLK |
| 478 | select COMMON_CLKDEV | 479 | select COMMON_CLKDEV |
| 479 | select ARCH_REQUIRE_GPIOLIB | 480 | select ARCH_REQUIRE_GPIOLIB |
| 481 | select HAVE_CLK | ||
| 482 | select COMMON_CLKDEV | ||
| 480 | select GENERIC_TIME | 483 | select GENERIC_TIME |
| 481 | select GENERIC_CLOCKEVENTS | 484 | select GENERIC_CLOCKEVENTS |
| 482 | select TICK_ONESHOT | 485 | select TICK_ONESHOT |
| 486 | select PLAT_PXA | ||
| 483 | help | 487 | help |
| 484 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. | 488 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
| 485 | 489 | ||
| 490 | config ARCH_MMP | ||
| 491 | bool "Marvell PXA168/910" | ||
| 492 | depends on MMU | ||
| 493 | select GENERIC_GPIO | ||
| 494 | select ARCH_REQUIRE_GPIOLIB | ||
| 495 | select HAVE_CLK | ||
| 496 | select COMMON_CLKDEV | ||
| 497 | select GENERIC_TIME | ||
| 498 | select GENERIC_CLOCKEVENTS | ||
| 499 | select TICK_ONESHOT | ||
| 500 | select PLAT_PXA | ||
| 501 | help | ||
| 502 | Support for Marvell's PXA168/910 processor line. | ||
| 503 | |||
| 486 | config ARCH_RPC | 504 | config ARCH_RPC |
| 487 | bool "RiscPC" | 505 | bool "RiscPC" |
| 488 | select ARCH_ACORN | 506 | select ARCH_ACORN |
| @@ -617,6 +635,9 @@ source "arch/arm/mach-loki/Kconfig" | |||
| 617 | source "arch/arm/mach-mv78xx0/Kconfig" | 635 | source "arch/arm/mach-mv78xx0/Kconfig" |
| 618 | 636 | ||
| 619 | source "arch/arm/mach-pxa/Kconfig" | 637 | source "arch/arm/mach-pxa/Kconfig" |
| 638 | source "arch/arm/plat-pxa/Kconfig" | ||
| 639 | |||
| 640 | source "arch/arm/mach-mmp/Kconfig" | ||
| 620 | 641 | ||
| 621 | source "arch/arm/mach-sa1100/Kconfig" | 642 | source "arch/arm/mach-sa1100/Kconfig" |
| 622 | 643 | ||
| @@ -686,12 +707,15 @@ config PLAT_IOP | |||
| 686 | config PLAT_ORION | 707 | config PLAT_ORION |
| 687 | bool | 708 | bool |
| 688 | 709 | ||
| 710 | config PLAT_PXA | ||
| 711 | bool | ||
| 712 | |||
| 689 | source arch/arm/mm/Kconfig | 713 | source arch/arm/mm/Kconfig |
| 690 | 714 | ||
| 691 | config IWMMXT | 715 | config IWMMXT |
| 692 | bool "Enable iWMMXt support" | 716 | bool "Enable iWMMXt support" |
| 693 | depends on CPU_XSCALE || CPU_XSC3 | 717 | depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK |
| 694 | default y if PXA27x || PXA3xx | 718 | default y if PXA27x || PXA3xx || ARCH_MMP |
| 695 | help | 719 | help |
| 696 | Enable support for iWMMXt context switching at run time if | 720 | Enable support for iWMMXt context switching at run time if |
| 697 | running on a CPU that supports it. | 721 | running on a CPU that supports it. |
| @@ -915,6 +939,23 @@ config NODES_SHIFT | |||
| 915 | default "2" | 939 | default "2" |
| 916 | depends on NEED_MULTIPLE_NODES | 940 | depends on NEED_MULTIPLE_NODES |
| 917 | 941 | ||
| 942 | config HIGHMEM | ||
| 943 | bool "High Memory Support (EXPERIMENTAL)" | ||
| 944 | depends on MMU && EXPERIMENTAL | ||
| 945 | help | ||
| 946 | The address space of ARM processors is only 4 Gigabytes large | ||
| 947 | and it has to accommodate user address space, kernel address | ||
| 948 | space as well as some memory mapped IO. That means that, if you | ||
| 949 | have a large amount of physical memory and/or IO, not all of the | ||
| 950 | memory can be "permanently mapped" by the kernel. The physical | ||
| 951 | memory that is not permanently mapped is called "high memory". | ||
| 952 | |||
| 953 | Depending on the selected kernel/user memory split, minimum | ||
| 954 | vmalloc space and actual amount of RAM, you may not need this | ||
| 955 | option which should result in a slightly faster kernel. | ||
| 956 | |||
| 957 | If unsure, say n. | ||
| 958 | |||
| 918 | source "mm/Kconfig" | 959 | source "mm/Kconfig" |
| 919 | 960 | ||
| 920 | config LEDS | 961 | config LEDS |
| @@ -1092,7 +1133,7 @@ source "drivers/cpufreq/Kconfig" | |||
| 1092 | 1133 | ||
| 1093 | config CPU_FREQ_SA1100 | 1134 | config CPU_FREQ_SA1100 |
| 1094 | bool | 1135 | bool |
| 1095 | depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_H3800 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT) | 1136 | depends on CPU_FREQ && (SA1100_H3100 || SA1100_H3600 || SA1100_LART || SA1100_PLEB || SA1100_BADGE4 || SA1100_HACKKIT) |
| 1096 | default y | 1137 | default y |
| 1097 | 1138 | ||
| 1098 | config CPU_FREQ_SA1110 | 1139 | config CPU_FREQ_SA1110 |
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 192ee01a9ba2..a71fd941ade7 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug | |||
| @@ -2,18 +2,29 @@ menu "Kernel hacking" | |||
| 2 | 2 | ||
| 3 | source "lib/Kconfig.debug" | 3 | source "lib/Kconfig.debug" |
| 4 | 4 | ||
| 5 | # RMK wants arm kernels compiled with frame pointers so hardwire this to y. | 5 | # RMK wants arm kernels compiled with frame pointers or stack unwinding. |
| 6 | # If you know what you are doing and are willing to live without stack | 6 | # If you know what you are doing and are willing to live without stack |
| 7 | # traces, you can get a slightly smaller kernel by setting this option to | 7 | # traces, you can get a slightly smaller kernel by setting this option to |
| 8 | # n, but then RMK will have to kill you ;). | 8 | # n, but then RMK will have to kill you ;). |
| 9 | config FRAME_POINTER | 9 | config FRAME_POINTER |
| 10 | bool | 10 | bool |
| 11 | default y | 11 | default y if !ARM_UNWIND |
| 12 | help | 12 | help |
| 13 | If you say N here, the resulting kernel will be slightly smaller and | 13 | If you say N here, the resulting kernel will be slightly smaller and |
| 14 | faster. However, when a problem occurs with the kernel, the | 14 | faster. However, if neither FRAME_POINTER nor ARM_UNWIND are enabled, |
| 15 | information that is reported is severely limited. Most people | 15 | when a problem occurs with the kernel, the information that is |
| 16 | should say Y here. | 16 | reported is severely limited. |
| 17 | |||
| 18 | config ARM_UNWIND | ||
| 19 | bool "Enable stack unwinding support" | ||
| 20 | depends on AEABI && EXPERIMENTAL | ||
| 21 | default y | ||
| 22 | help | ||
| 23 | This option enables stack unwinding support in the kernel | ||
| 24 | using the information automatically generated by the | ||
| 25 | compiler. The resulting kernel image is slightly bigger but | ||
| 26 | the performance is not affected. Currently, this feature | ||
| 27 | only works with EABI compilers. If unsure say Y. | ||
| 17 | 28 | ||
| 18 | config DEBUG_USER | 29 | config DEBUG_USER |
| 19 | bool "Verbose user fault messages" | 30 | bool "Verbose user fault messages" |
| @@ -66,7 +77,7 @@ config DEBUG_ICEDCC | |||
| 66 | Say Y here if you want the debug print routines to direct their | 77 | Say Y here if you want the debug print routines to direct their |
| 67 | output to the EmbeddedICE macrocell's DCC channel using | 78 | output to the EmbeddedICE macrocell's DCC channel using |
| 68 | co-processor 14. This is known to work on the ARM9 style ICE | 79 | co-processor 14. This is known to work on the ARM9 style ICE |
| 69 | channel. | 80 | channel and on the XScale with the PEEDI. |
| 70 | 81 | ||
| 71 | It does include a timeout to ensure that the system does not | 82 | It does include a timeout to ensure that the system does not |
| 72 | totally freeze when there is nothing connected to read. | 83 | totally freeze when there is nothing connected to read. |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 24e0f0187697..95186ef17e17 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
| @@ -85,6 +85,10 @@ else | |||
| 85 | CFLAGS_ABI :=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) $(call cc-option,-mno-thumb-interwork,) | 85 | CFLAGS_ABI :=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) $(call cc-option,-mno-thumb-interwork,) |
| 86 | endif | 86 | endif |
| 87 | 87 | ||
| 88 | ifeq ($(CONFIG_ARM_UNWIND),y) | ||
| 89 | CFLAGS_ABI +=-funwind-tables | ||
| 90 | endif | ||
| 91 | |||
| 88 | # Need -Uarm for gcc < 3.x | 92 | # Need -Uarm for gcc < 3.x |
| 89 | KBUILD_CFLAGS +=$(CFLAGS_ABI) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm | 93 | KBUILD_CFLAGS +=$(CFLAGS_ABI) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm |
| 90 | KBUILD_AFLAGS +=$(CFLAGS_ABI) $(arch-y) $(tune-y) -msoft-float | 94 | KBUILD_AFLAGS +=$(CFLAGS_ABI) $(arch-y) $(tune-y) -msoft-float |
| @@ -105,6 +109,8 @@ ifeq ($(CONFIG_ARCH_SA1100),y) | |||
| 105 | textofs-$(CONFIG_SA1111) := 0x00208000 | 109 | textofs-$(CONFIG_SA1111) := 0x00208000 |
| 106 | endif | 110 | endif |
| 107 | machine-$(CONFIG_ARCH_PXA) := pxa | 111 | machine-$(CONFIG_ARCH_PXA) := pxa |
| 112 | machine-$(CONFIG_ARCH_MMP) := mmp | ||
| 113 | plat-$(CONFIG_PLAT_PXA) := pxa | ||
| 108 | machine-$(CONFIG_ARCH_L7200) := l7200 | 114 | machine-$(CONFIG_ARCH_L7200) := l7200 |
| 109 | machine-$(CONFIG_ARCH_INTEGRATOR) := integrator | 115 | machine-$(CONFIG_ARCH_INTEGRATOR) := integrator |
| 110 | textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 | 116 | textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 |
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 77d614232d81..d14b827adcd6 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S | |||
| @@ -27,6 +27,12 @@ | |||
| 27 | .macro writeb, ch, rb | 27 | .macro writeb, ch, rb |
| 28 | mcr p14, 0, \ch, c0, c5, 0 | 28 | mcr p14, 0, \ch, c0, c5, 0 |
| 29 | .endm | 29 | .endm |
| 30 | #elif defined(CONFIG_CPU_XSCALE) | ||
| 31 | .macro loadsp, rb | ||
| 32 | .endm | ||
| 33 | .macro writeb, ch, rb | ||
| 34 | mcr p14, 0, \ch, c8, c0, 0 | ||
| 35 | .endm | ||
| 30 | #else | 36 | #else |
| 31 | .macro loadsp, rb | 37 | .macro loadsp, rb |
| 32 | .endm | 38 | .endm |
| @@ -630,6 +636,18 @@ proc_types: | |||
| 630 | b __armv4_mmu_cache_off | 636 | b __armv4_mmu_cache_off |
| 631 | b __armv4_mmu_cache_flush | 637 | b __armv4_mmu_cache_flush |
| 632 | 638 | ||
| 639 | .word 0x56158000 @ PXA168 | ||
| 640 | .word 0xfffff000 | ||
| 641 | b __armv4_mmu_cache_on | ||
| 642 | b __armv4_mmu_cache_off | ||
| 643 | b __armv5tej_mmu_cache_flush | ||
| 644 | |||
| 645 | .word 0x56056930 | ||
| 646 | .word 0xff0ffff0 @ PXA935 | ||
| 647 | b __armv4_mmu_cache_on | ||
| 648 | b __armv4_mmu_cache_off | ||
| 649 | b __armv4_mmu_cache_flush | ||
| 650 | |||
| 633 | .word 0x56050000 @ Feroceon | 651 | .word 0x56050000 @ Feroceon |
| 634 | .word 0xff0f0000 | 652 | .word 0xff0f0000 |
| 635 | b __armv4_mmu_cache_on | 653 | b __armv4_mmu_cache_on |
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c index 3fc08413fff0..393c81641314 100644 --- a/arch/arm/boot/compressed/misc.c +++ b/arch/arm/boot/compressed/misc.c | |||
| @@ -46,6 +46,21 @@ static void icedcc_putc(int ch) | |||
| 46 | 46 | ||
| 47 | asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); | 47 | asm("mcr p14, 0, %0, c0, c5, 0" : : "r" (ch)); |
| 48 | } | 48 | } |
| 49 | #elif defined(CONFIG_CPU_XSCALE) | ||
| 50 | |||
| 51 | static void icedcc_putc(int ch) | ||
| 52 | { | ||
| 53 | int status, i = 0x4000000; | ||
| 54 | |||
| 55 | do { | ||
| 56 | if (--i < 0) | ||
| 57 | return; | ||
| 58 | |||
| 59 | asm volatile ("mrc p14, 0, %0, c14, c0, 0" : "=r" (status)); | ||
| 60 | } while (status & (1 << 28)); | ||
| 61 | |||
| 62 | asm("mcr p14, 0, %0, c8, c0, 0" : : "r" (ch)); | ||
| 63 | } | ||
| 49 | 64 | ||
| 50 | #else | 65 | #else |
| 51 | 66 | ||
diff --git a/arch/arm/boot/compressed/vmlinux.lds.in b/arch/arm/boot/compressed/vmlinux.lds.in index 153a07e7222b..a5924b9b88bd 100644 --- a/arch/arm/boot/compressed/vmlinux.lds.in +++ b/arch/arm/boot/compressed/vmlinux.lds.in | |||
| @@ -11,6 +11,11 @@ OUTPUT_ARCH(arm) | |||
| 11 | ENTRY(_start) | 11 | ENTRY(_start) |
| 12 | SECTIONS | 12 | SECTIONS |
| 13 | { | 13 | { |
| 14 | /DISCARD/ : { | ||
| 15 | *(.ARM.exidx*) | ||
| 16 | *(.ARM.extab*) | ||
| 17 | } | ||
| 18 | |||
| 14 | . = TEXT_START; | 19 | . = TEXT_START; |
| 15 | _text = .; | 20 | _text = .; |
| 16 | 21 | ||
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c index f030f0775be7..734ac9135998 100644 --- a/arch/arm/common/dmabounce.c +++ b/arch/arm/common/dmabounce.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <linux/module.h> | 25 | #include <linux/module.h> |
| 26 | #include <linux/init.h> | 26 | #include <linux/init.h> |
| 27 | #include <linux/slab.h> | 27 | #include <linux/slab.h> |
| 28 | #include <linux/page-flags.h> | ||
| 28 | #include <linux/device.h> | 29 | #include <linux/device.h> |
| 29 | #include <linux/dma-mapping.h> | 30 | #include <linux/dma-mapping.h> |
| 30 | #include <linux/dmapool.h> | 31 | #include <linux/dmapool.h> |
| @@ -349,6 +350,12 @@ dma_addr_t dma_map_page(struct device *dev, struct page *page, | |||
| 349 | 350 | ||
| 350 | BUG_ON(!valid_dma_direction(dir)); | 351 | BUG_ON(!valid_dma_direction(dir)); |
| 351 | 352 | ||
| 353 | if (PageHighMem(page)) { | ||
| 354 | dev_err(dev, "DMA buffer bouncing of HIGHMEM pages " | ||
| 355 | "is not supported\n"); | ||
| 356 | return ~0; | ||
| 357 | } | ||
| 358 | |||
| 352 | return map_single(dev, page_address(page) + offset, size, dir); | 359 | return map_single(dev, page_address(page) + offset, size, dir); |
| 353 | } | 360 | } |
| 354 | EXPORT_SYMBOL(dma_map_page); | 361 | EXPORT_SYMBOL(dma_map_page); |
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c index 697c64913990..7713a08bb10c 100644 --- a/arch/arm/common/scoop.c +++ b/arch/arm/common/scoop.c | |||
| @@ -124,37 +124,6 @@ static int scoop_gpio_direction_output(struct gpio_chip *chip, | |||
| 124 | return 0; | 124 | return 0; |
| 125 | } | 125 | } |
| 126 | 126 | ||
| 127 | unsigned short set_scoop_gpio(struct device *dev, unsigned short bit) | ||
| 128 | { | ||
| 129 | unsigned short gpio_bit; | ||
| 130 | unsigned long flag; | ||
| 131 | struct scoop_dev *sdev = dev_get_drvdata(dev); | ||
| 132 | |||
| 133 | spin_lock_irqsave(&sdev->scoop_lock, flag); | ||
| 134 | gpio_bit = ioread16(sdev->base + SCOOP_GPWR) | bit; | ||
| 135 | iowrite16(gpio_bit, sdev->base + SCOOP_GPWR); | ||
| 136 | spin_unlock_irqrestore(&sdev->scoop_lock, flag); | ||
| 137 | |||
| 138 | return gpio_bit; | ||
| 139 | } | ||
| 140 | |||
| 141 | unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit) | ||
| 142 | { | ||
| 143 | unsigned short gpio_bit; | ||
| 144 | unsigned long flag; | ||
| 145 | struct scoop_dev *sdev = dev_get_drvdata(dev); | ||
| 146 | |||
| 147 | spin_lock_irqsave(&sdev->scoop_lock, flag); | ||
| 148 | gpio_bit = ioread16(sdev->base + SCOOP_GPWR) & ~bit; | ||
| 149 | iowrite16(gpio_bit, sdev->base + SCOOP_GPWR); | ||
| 150 | spin_unlock_irqrestore(&sdev->scoop_lock, flag); | ||
| 151 | |||
| 152 | return gpio_bit; | ||
| 153 | } | ||
| 154 | |||
| 155 | EXPORT_SYMBOL(set_scoop_gpio); | ||
| 156 | EXPORT_SYMBOL(reset_scoop_gpio); | ||
| 157 | |||
| 158 | unsigned short read_scoop_reg(struct device *dev, unsigned short reg) | 127 | unsigned short read_scoop_reg(struct device *dev, unsigned short reg) |
| 159 | { | 128 | { |
| 160 | struct scoop_dev *sdev = dev_get_drvdata(dev); | 129 | struct scoop_dev *sdev = dev_get_drvdata(dev); |
diff --git a/arch/arm/common/sharpsl_pm.c b/arch/arm/common/sharpsl_pm.c index 780bbf7cb26f..140f1d721d50 100644 --- a/arch/arm/common/sharpsl_pm.c +++ b/arch/arm/common/sharpsl_pm.c | |||
| @@ -29,8 +29,8 @@ | |||
| 29 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
| 30 | #include <asm/irq.h> | 30 | #include <asm/irq.h> |
| 31 | #include <mach/pm.h> | 31 | #include <mach/pm.h> |
| 32 | #include <mach/pxa-regs.h> | ||
| 33 | #include <mach/pxa2xx-regs.h> | 32 | #include <mach/pxa2xx-regs.h> |
| 33 | #include <mach/regs-rtc.h> | ||
| 34 | #include <mach/sharpsl.h> | 34 | #include <mach/sharpsl.h> |
| 35 | #include <asm/hardware/sharpsl_pm.h> | 35 | #include <asm/hardware/sharpsl_pm.h> |
| 36 | 36 | ||
diff --git a/arch/arm/configs/acs5k_defconfig b/arch/arm/configs/acs5k_defconfig new file mode 100644 index 000000000000..1cab4e79d368 --- /dev/null +++ b/arch/arm/configs/acs5k_defconfig | |||
| @@ -0,0 +1,1233 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.27-simtec-micrel1 | ||
| 4 | # Tue Dec 16 13:31:34 2008 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | # CONFIG_GENERIC_TIME is not set | ||
| 10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_ARCH_SUPPORTS_AOUT=y | ||
| 26 | CONFIG_ZONE_DMA=y | ||
| 27 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 28 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 29 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 30 | |||
| 31 | # | ||
| 32 | # General setup | ||
| 33 | # | ||
| 34 | CONFIG_EXPERIMENTAL=y | ||
| 35 | CONFIG_BROKEN_ON_SMP=y | ||
| 36 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 37 | CONFIG_LOCALVERSION="" | ||
| 38 | CONFIG_LOCALVERSION_AUTO=y | ||
| 39 | # CONFIG_SWAP is not set | ||
| 40 | CONFIG_SYSVIPC=y | ||
| 41 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 42 | CONFIG_POSIX_MQUEUE=y | ||
| 43 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 44 | # CONFIG_TASKSTATS is not set | ||
| 45 | # CONFIG_AUDIT is not set | ||
| 46 | # CONFIG_IKCONFIG is not set | ||
| 47 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 48 | # CONFIG_CGROUPS is not set | ||
| 49 | # CONFIG_GROUP_SCHED is not set | ||
| 50 | CONFIG_SYSFS_DEPRECATED=y | ||
| 51 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 52 | # CONFIG_RELAY is not set | ||
| 53 | CONFIG_NAMESPACES=y | ||
| 54 | # CONFIG_UTS_NS is not set | ||
| 55 | # CONFIG_IPC_NS is not set | ||
| 56 | # CONFIG_USER_NS is not set | ||
| 57 | # CONFIG_PID_NS is not set | ||
| 58 | CONFIG_BLK_DEV_INITRD=y | ||
| 59 | CONFIG_INITRAMFS_SOURCE="" | ||
| 60 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 61 | CONFIG_SYSCTL=y | ||
| 62 | # CONFIG_EMBEDDED is not set | ||
| 63 | CONFIG_UID16=y | ||
| 64 | CONFIG_SYSCTL_SYSCALL=y | ||
| 65 | CONFIG_KALLSYMS=y | ||
| 66 | # CONFIG_KALLSYMS_ALL is not set | ||
| 67 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 68 | CONFIG_HOTPLUG=y | ||
| 69 | CONFIG_PRINTK=y | ||
| 70 | CONFIG_BUG=y | ||
| 71 | CONFIG_ELF_CORE=y | ||
| 72 | CONFIG_COMPAT_BRK=y | ||
| 73 | CONFIG_BASE_FULL=y | ||
| 74 | CONFIG_FUTEX=y | ||
| 75 | CONFIG_ANON_INODES=y | ||
| 76 | CONFIG_EPOLL=y | ||
| 77 | CONFIG_SIGNALFD=y | ||
| 78 | CONFIG_TIMERFD=y | ||
| 79 | CONFIG_EVENTFD=y | ||
| 80 | CONFIG_SHMEM=y | ||
| 81 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 82 | CONFIG_SLAB=y | ||
| 83 | # CONFIG_SLUB is not set | ||
| 84 | # CONFIG_SLOB is not set | ||
| 85 | # CONFIG_PROFILING is not set | ||
| 86 | # CONFIG_MARKERS is not set | ||
| 87 | CONFIG_HAVE_OPROFILE=y | ||
| 88 | # CONFIG_KPROBES is not set | ||
| 89 | # CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set | ||
| 90 | # CONFIG_HAVE_IOREMAP_PROT is not set | ||
| 91 | CONFIG_HAVE_KPROBES=y | ||
| 92 | CONFIG_HAVE_KRETPROBES=y | ||
| 93 | # CONFIG_HAVE_ARCH_TRACEHOOK is not set | ||
| 94 | # CONFIG_HAVE_DMA_ATTRS is not set | ||
| 95 | # CONFIG_USE_GENERIC_SMP_HELPERS is not set | ||
| 96 | # CONFIG_HAVE_CLK is not set | ||
| 97 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 98 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 99 | CONFIG_SLABINFO=y | ||
| 100 | CONFIG_RT_MUTEXES=y | ||
| 101 | # CONFIG_TINY_SHMEM is not set | ||
| 102 | CONFIG_BASE_SMALL=0 | ||
| 103 | CONFIG_MODULES=y | ||
| 104 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 105 | CONFIG_MODULE_UNLOAD=y | ||
| 106 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 107 | # CONFIG_MODVERSIONS is not set | ||
| 108 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 109 | CONFIG_KMOD=y | ||
| 110 | CONFIG_BLOCK=y | ||
| 111 | # CONFIG_LBD is not set | ||
| 112 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 113 | # CONFIG_LSF is not set | ||
| 114 | # CONFIG_BLK_DEV_BSG is not set | ||
| 115 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 116 | |||
| 117 | # | ||
| 118 | # IO Schedulers | ||
| 119 | # | ||
| 120 | CONFIG_IOSCHED_NOOP=y | ||
| 121 | CONFIG_IOSCHED_AS=y | ||
| 122 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 123 | # CONFIG_IOSCHED_CFQ is not set | ||
| 124 | CONFIG_DEFAULT_AS=y | ||
| 125 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 126 | # CONFIG_DEFAULT_CFQ is not set | ||
| 127 | # CONFIG_DEFAULT_NOOP is not set | ||
| 128 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
| 129 | CONFIG_CLASSIC_RCU=y | ||
| 130 | |||
| 131 | # | ||
| 132 | # System Type | ||
| 133 | # | ||
| 134 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 135 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 136 | # CONFIG_ARCH_REALVIEW is not set | ||
| 137 | # CONFIG_ARCH_VERSATILE is not set | ||
| 138 | # CONFIG_ARCH_AT91 is not set | ||
| 139 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 140 | # CONFIG_ARCH_CLPS711X is not set | ||
| 141 | # CONFIG_ARCH_EBSA110 is not set | ||
| 142 | # CONFIG_ARCH_EP93XX is not set | ||
| 143 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 144 | # CONFIG_ARCH_NETX is not set | ||
| 145 | # CONFIG_ARCH_H720X is not set | ||
| 146 | # CONFIG_ARCH_IMX is not set | ||
| 147 | # CONFIG_ARCH_IOP13XX is not set | ||
| 148 | # CONFIG_ARCH_IOP32X is not set | ||
| 149 | # CONFIG_ARCH_IOP33X is not set | ||
| 150 | # CONFIG_ARCH_IXP23XX is not set | ||
| 151 | # CONFIG_ARCH_IXP2000 is not set | ||
| 152 | # CONFIG_ARCH_IXP4XX is not set | ||
| 153 | # CONFIG_ARCH_L7200 is not set | ||
| 154 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 155 | CONFIG_ARCH_KS8695=y | ||
| 156 | # CONFIG_ARCH_NS9XXX is not set | ||
| 157 | # CONFIG_ARCH_LOKI is not set | ||
| 158 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 159 | # CONFIG_ARCH_MXC is not set | ||
| 160 | # CONFIG_ARCH_ORION5X is not set | ||
| 161 | # CONFIG_ARCH_PNX4008 is not set | ||
| 162 | # CONFIG_ARCH_PXA is not set | ||
| 163 | # CONFIG_ARCH_RPC is not set | ||
| 164 | # CONFIG_ARCH_SA1100 is not set | ||
| 165 | # CONFIG_ARCH_S3C2410 is not set | ||
| 166 | # CONFIG_ARCH_SHARK is not set | ||
| 167 | # CONFIG_ARCH_LH7A40X is not set | ||
| 168 | # CONFIG_ARCH_DAVINCI is not set | ||
| 169 | # CONFIG_ARCH_OMAP is not set | ||
| 170 | # CONFIG_ARCH_MSM7X00A is not set | ||
| 171 | |||
| 172 | # | ||
| 173 | # Boot options | ||
| 174 | # | ||
| 175 | |||
| 176 | # | ||
| 177 | # Power management | ||
| 178 | # | ||
| 179 | |||
| 180 | # | ||
| 181 | # Kendin/Micrel KS8695 Implementations | ||
| 182 | # | ||
| 183 | CONFIG_MACH_KS8695=y | ||
| 184 | CONFIG_MACH_DSM320=y | ||
| 185 | CONFIG_MACH_ACS5K=y | ||
| 186 | |||
| 187 | # | ||
| 188 | # Processor Type | ||
| 189 | # | ||
| 190 | CONFIG_CPU_32=y | ||
| 191 | CONFIG_CPU_ARM922T=y | ||
| 192 | CONFIG_CPU_32v4T=y | ||
| 193 | CONFIG_CPU_ABRT_EV4T=y | ||
| 194 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 195 | CONFIG_CPU_CACHE_V4WT=y | ||
| 196 | CONFIG_CPU_CACHE_VIVT=y | ||
| 197 | CONFIG_CPU_COPY_V4WB=y | ||
| 198 | CONFIG_CPU_TLB_V4WBI=y | ||
| 199 | CONFIG_CPU_CP15=y | ||
| 200 | CONFIG_CPU_CP15_MMU=y | ||
| 201 | |||
| 202 | # | ||
| 203 | # Processor Features | ||
| 204 | # | ||
| 205 | # CONFIG_ARM_THUMB is not set | ||
| 206 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 207 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 208 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 209 | # CONFIG_OUTER_CACHE is not set | ||
| 210 | |||
| 211 | # | ||
| 212 | # Bus support | ||
| 213 | # | ||
| 214 | CONFIG_PCI=y | ||
| 215 | CONFIG_PCI_SYSCALL=y | ||
| 216 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 217 | CONFIG_PCI_LEGACY=y | ||
| 218 | CONFIG_PCI_DEBUG=y | ||
| 219 | CONFIG_PCCARD=y | ||
| 220 | # CONFIG_PCMCIA_DEBUG is not set | ||
| 221 | CONFIG_PCMCIA=y | ||
| 222 | CONFIG_PCMCIA_LOAD_CIS=y | ||
| 223 | CONFIG_PCMCIA_IOCTL=y | ||
| 224 | CONFIG_CARDBUS=y | ||
| 225 | |||
| 226 | # | ||
| 227 | # PC-card bridges | ||
| 228 | # | ||
| 229 | CONFIG_YENTA=y | ||
| 230 | CONFIG_YENTA_O2=y | ||
| 231 | CONFIG_YENTA_RICOH=y | ||
| 232 | CONFIG_YENTA_TI=y | ||
| 233 | CONFIG_YENTA_ENE_TUNE=y | ||
| 234 | CONFIG_YENTA_TOSHIBA=y | ||
| 235 | # CONFIG_PD6729 is not set | ||
| 236 | # CONFIG_I82092 is not set | ||
| 237 | CONFIG_PCCARD_NONSTATIC=y | ||
| 238 | |||
| 239 | # | ||
| 240 | # Kernel Features | ||
| 241 | # | ||
| 242 | # CONFIG_TICK_ONESHOT is not set | ||
| 243 | # CONFIG_PREEMPT is not set | ||
| 244 | CONFIG_HZ=100 | ||
| 245 | CONFIG_AEABI=y | ||
| 246 | CONFIG_OABI_COMPAT=y | ||
| 247 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 248 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | ||
| 249 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 250 | CONFIG_FLATMEM_MANUAL=y | ||
| 251 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 252 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 253 | CONFIG_FLATMEM=y | ||
| 254 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 255 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 256 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 257 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 258 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 259 | # CONFIG_RESOURCES_64BIT is not set | ||
| 260 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 261 | CONFIG_BOUNCE=y | ||
| 262 | CONFIG_VIRT_TO_BUS=y | ||
| 263 | # CONFIG_LEDS is not set | ||
| 264 | CONFIG_ALIGNMENT_TRAP=y | ||
| 265 | |||
| 266 | # | ||
| 267 | # Boot options | ||
| 268 | # | ||
| 269 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 270 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 271 | CONFIG_CMDLINE="mem=32M console=ttyS0,115200 initrd=0x20410000,3145728 root=/dev/ram0 rw" | ||
| 272 | # CONFIG_XIP_KERNEL is not set | ||
| 273 | # CONFIG_KEXEC is not set | ||
| 274 | |||
| 275 | # | ||
| 276 | # Floating point emulation | ||
| 277 | # | ||
| 278 | |||
| 279 | # | ||
| 280 | # At least one emulation must be selected | ||
| 281 | # | ||
| 282 | # CONFIG_FPE_NWFPE is not set | ||
| 283 | # CONFIG_FPE_FASTFPE is not set | ||
| 284 | |||
| 285 | # | ||
| 286 | # Userspace binary formats | ||
| 287 | # | ||
| 288 | CONFIG_BINFMT_ELF=y | ||
| 289 | # CONFIG_BINFMT_AOUT is not set | ||
| 290 | # CONFIG_BINFMT_MISC is not set | ||
| 291 | |||
| 292 | # | ||
| 293 | # Power management options | ||
| 294 | # | ||
| 295 | # CONFIG_PM is not set | ||
| 296 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 297 | CONFIG_NET=y | ||
| 298 | |||
| 299 | # | ||
| 300 | # Networking options | ||
| 301 | # | ||
| 302 | CONFIG_PACKET=y | ||
| 303 | # CONFIG_PACKET_MMAP is not set | ||
| 304 | CONFIG_UNIX=y | ||
| 305 | CONFIG_XFRM=y | ||
| 306 | # CONFIG_XFRM_USER is not set | ||
| 307 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 308 | # CONFIG_XFRM_MIGRATE is not set | ||
| 309 | # CONFIG_XFRM_STATISTICS is not set | ||
| 310 | # CONFIG_NET_KEY is not set | ||
| 311 | CONFIG_INET=y | ||
| 312 | # CONFIG_IP_MULTICAST is not set | ||
| 313 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 314 | CONFIG_IP_FIB_HASH=y | ||
| 315 | CONFIG_IP_PNP=y | ||
| 316 | CONFIG_IP_PNP_DHCP=y | ||
| 317 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 318 | # CONFIG_IP_PNP_RARP is not set | ||
| 319 | # CONFIG_NET_IPIP is not set | ||
| 320 | # CONFIG_NET_IPGRE is not set | ||
| 321 | # CONFIG_ARPD is not set | ||
| 322 | # CONFIG_SYN_COOKIES is not set | ||
| 323 | # CONFIG_INET_AH is not set | ||
| 324 | # CONFIG_INET_ESP is not set | ||
| 325 | # CONFIG_INET_IPCOMP is not set | ||
| 326 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 327 | # CONFIG_INET_TUNNEL is not set | ||
| 328 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 329 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 330 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 331 | # CONFIG_INET_LRO is not set | ||
| 332 | CONFIG_INET_DIAG=y | ||
| 333 | CONFIG_INET_TCP_DIAG=y | ||
| 334 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 335 | CONFIG_TCP_CONG_CUBIC=y | ||
| 336 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 337 | # CONFIG_TCP_MD5SIG is not set | ||
| 338 | # CONFIG_IPV6 is not set | ||
| 339 | # CONFIG_NETWORK_SECMARK is not set | ||
| 340 | # CONFIG_NETFILTER is not set | ||
| 341 | # CONFIG_IP_DCCP is not set | ||
| 342 | # CONFIG_IP_SCTP is not set | ||
| 343 | # CONFIG_TIPC is not set | ||
| 344 | # CONFIG_ATM is not set | ||
| 345 | # CONFIG_BRIDGE is not set | ||
| 346 | # CONFIG_VLAN_8021Q is not set | ||
| 347 | # CONFIG_DECNET is not set | ||
| 348 | # CONFIG_LLC2 is not set | ||
| 349 | # CONFIG_IPX is not set | ||
| 350 | # CONFIG_ATALK is not set | ||
| 351 | # CONFIG_X25 is not set | ||
| 352 | # CONFIG_LAPB is not set | ||
| 353 | # CONFIG_ECONET is not set | ||
| 354 | # CONFIG_WAN_ROUTER is not set | ||
| 355 | # CONFIG_NET_SCHED is not set | ||
| 356 | |||
| 357 | # | ||
| 358 | # Network testing | ||
| 359 | # | ||
| 360 | # CONFIG_NET_PKTGEN is not set | ||
| 361 | # CONFIG_HAMRADIO is not set | ||
| 362 | # CONFIG_CAN is not set | ||
| 363 | # CONFIG_IRDA is not set | ||
| 364 | # CONFIG_BT is not set | ||
| 365 | # CONFIG_AF_RXRPC is not set | ||
| 366 | |||
| 367 | # | ||
| 368 | # Wireless | ||
| 369 | # | ||
| 370 | # CONFIG_CFG80211 is not set | ||
| 371 | CONFIG_WIRELESS_EXT=y | ||
| 372 | CONFIG_WIRELESS_EXT_SYSFS=y | ||
| 373 | # CONFIG_MAC80211 is not set | ||
| 374 | # CONFIG_IEEE80211 is not set | ||
| 375 | # CONFIG_RFKILL is not set | ||
| 376 | # CONFIG_NET_9P is not set | ||
| 377 | |||
| 378 | # | ||
| 379 | # Device Drivers | ||
| 380 | # | ||
| 381 | |||
| 382 | # | ||
| 383 | # Generic Driver Options | ||
| 384 | # | ||
| 385 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 386 | CONFIG_STANDALONE=y | ||
| 387 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 388 | CONFIG_FW_LOADER=y | ||
| 389 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 390 | CONFIG_EXTRA_FIRMWARE="" | ||
| 391 | # CONFIG_DEBUG_DRIVER is not set | ||
| 392 | # CONFIG_DEBUG_DEVRES is not set | ||
| 393 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 394 | # CONFIG_CONNECTOR is not set | ||
| 395 | CONFIG_MTD=y | ||
| 396 | # CONFIG_MTD_DEBUG is not set | ||
| 397 | CONFIG_MTD_CONCAT=y | ||
| 398 | CONFIG_MTD_PARTITIONS=y | ||
| 399 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 400 | # CONFIG_MTD_CMDLINE_PARTS is not set | ||
| 401 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 402 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 403 | |||
| 404 | # | ||
| 405 | # User Modules And Translation Layers | ||
| 406 | # | ||
| 407 | CONFIG_MTD_CHAR=y | ||
| 408 | CONFIG_MTD_BLKDEVS=y | ||
| 409 | CONFIG_MTD_BLOCK=y | ||
| 410 | # CONFIG_FTL is not set | ||
| 411 | # CONFIG_NFTL is not set | ||
| 412 | # CONFIG_INFTL is not set | ||
| 413 | # CONFIG_RFD_FTL is not set | ||
| 414 | # CONFIG_SSFDC is not set | ||
| 415 | # CONFIG_MTD_OOPS is not set | ||
| 416 | |||
| 417 | # | ||
| 418 | # RAM/ROM/Flash chip drivers | ||
| 419 | # | ||
| 420 | CONFIG_MTD_CFI=y | ||
| 421 | CONFIG_MTD_JEDECPROBE=y | ||
| 422 | CONFIG_MTD_GEN_PROBE=y | ||
| 423 | CONFIG_MTD_CFI_ADV_OPTIONS=y | ||
| 424 | CONFIG_MTD_CFI_NOSWAP=y | ||
| 425 | # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set | ||
| 426 | # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set | ||
| 427 | # CONFIG_MTD_CFI_GEOMETRY is not set | ||
| 428 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 429 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 430 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 431 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 432 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 433 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 434 | CONFIG_MTD_CFI_I1=y | ||
| 435 | CONFIG_MTD_CFI_I2=y | ||
| 436 | # CONFIG_MTD_CFI_I4 is not set | ||
| 437 | # CONFIG_MTD_CFI_I8 is not set | ||
| 438 | # CONFIG_MTD_OTP is not set | ||
| 439 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 440 | CONFIG_MTD_CFI_AMDSTD=y | ||
| 441 | # CONFIG_MTD_CFI_STAA is not set | ||
| 442 | CONFIG_MTD_CFI_UTIL=y | ||
| 443 | # CONFIG_MTD_RAM is not set | ||
| 444 | # CONFIG_MTD_ROM is not set | ||
| 445 | # CONFIG_MTD_ABSENT is not set | ||
| 446 | |||
| 447 | # | ||
| 448 | # Mapping drivers for chip access | ||
| 449 | # | ||
| 450 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 451 | CONFIG_MTD_PHYSMAP=y | ||
| 452 | CONFIG_MTD_PHYSMAP_START=0x8000000 | ||
| 453 | CONFIG_MTD_PHYSMAP_LEN=0 | ||
| 454 | CONFIG_MTD_PHYSMAP_BANKWIDTH=4 | ||
| 455 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 456 | # CONFIG_MTD_IMPA7 is not set | ||
| 457 | # CONFIG_MTD_INTEL_VR_NOR is not set | ||
| 458 | # CONFIG_MTD_PLATRAM is not set | ||
| 459 | |||
| 460 | # | ||
| 461 | # Self-contained MTD device drivers | ||
| 462 | # | ||
| 463 | # CONFIG_MTD_PMC551 is not set | ||
| 464 | # CONFIG_MTD_SLRAM is not set | ||
| 465 | # CONFIG_MTD_PHRAM is not set | ||
| 466 | # CONFIG_MTD_MTDRAM is not set | ||
| 467 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 468 | |||
| 469 | # | ||
| 470 | # Disk-On-Chip Device Drivers | ||
| 471 | # | ||
| 472 | # CONFIG_MTD_DOC2000 is not set | ||
| 473 | # CONFIG_MTD_DOC2001 is not set | ||
| 474 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 475 | # CONFIG_MTD_NAND is not set | ||
| 476 | # CONFIG_MTD_ONENAND is not set | ||
| 477 | |||
| 478 | # | ||
| 479 | # UBI - Unsorted block images | ||
| 480 | # | ||
| 481 | # CONFIG_MTD_UBI is not set | ||
| 482 | # CONFIG_PARPORT is not set | ||
| 483 | CONFIG_BLK_DEV=y | ||
| 484 | # CONFIG_BLK_CPQ_DA is not set | ||
| 485 | # CONFIG_BLK_CPQ_CISS_DA is not set | ||
| 486 | # CONFIG_BLK_DEV_DAC960 is not set | ||
| 487 | # CONFIG_BLK_DEV_UMEM is not set | ||
| 488 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 489 | # CONFIG_BLK_DEV_LOOP is not set | ||
| 490 | # CONFIG_BLK_DEV_NBD is not set | ||
| 491 | # CONFIG_BLK_DEV_SX8 is not set | ||
| 492 | CONFIG_BLK_DEV_RAM=y | ||
| 493 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 494 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
| 495 | # CONFIG_BLK_DEV_XIP is not set | ||
| 496 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 497 | # CONFIG_ATA_OVER_ETH is not set | ||
| 498 | CONFIG_MISC_DEVICES=y | ||
| 499 | # CONFIG_PHANTOM is not set | ||
| 500 | # CONFIG_EEPROM_93CX6 is not set | ||
| 501 | # CONFIG_SGI_IOC4 is not set | ||
| 502 | # CONFIG_TIFM_CORE is not set | ||
| 503 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 504 | # CONFIG_HP_ILO is not set | ||
| 505 | CONFIG_HAVE_IDE=y | ||
| 506 | # CONFIG_IDE is not set | ||
| 507 | |||
| 508 | # | ||
| 509 | # SCSI device support | ||
| 510 | # | ||
| 511 | # CONFIG_RAID_ATTRS is not set | ||
| 512 | # CONFIG_SCSI is not set | ||
| 513 | # CONFIG_SCSI_DMA is not set | ||
| 514 | # CONFIG_SCSI_NETLINK is not set | ||
| 515 | # CONFIG_ATA is not set | ||
| 516 | # CONFIG_MD is not set | ||
| 517 | # CONFIG_FUSION is not set | ||
| 518 | |||
| 519 | # | ||
| 520 | # IEEE 1394 (FireWire) support | ||
| 521 | # | ||
| 522 | |||
| 523 | # | ||
| 524 | # Enable only one of the two stacks, unless you know what you are doing | ||
| 525 | # | ||
| 526 | # CONFIG_FIREWIRE is not set | ||
| 527 | # CONFIG_IEEE1394 is not set | ||
| 528 | # CONFIG_I2O is not set | ||
| 529 | CONFIG_NETDEVICES=y | ||
| 530 | # CONFIG_DUMMY is not set | ||
| 531 | # CONFIG_BONDING is not set | ||
| 532 | # CONFIG_MACVLAN is not set | ||
| 533 | # CONFIG_EQUALIZER is not set | ||
| 534 | # CONFIG_TUN is not set | ||
| 535 | # CONFIG_VETH is not set | ||
| 536 | # CONFIG_ARCNET is not set | ||
| 537 | # CONFIG_PHYLIB is not set | ||
| 538 | CONFIG_NET_ETHERNET=y | ||
| 539 | CONFIG_MII=y | ||
| 540 | CONFIG_ARM_KS8695_ETHER=y | ||
| 541 | # CONFIG_AX88796 is not set | ||
| 542 | # CONFIG_HAPPYMEAL is not set | ||
| 543 | # CONFIG_SUNGEM is not set | ||
| 544 | # CONFIG_CASSINI is not set | ||
| 545 | # CONFIG_NET_VENDOR_3COM is not set | ||
| 546 | # CONFIG_SMC91X is not set | ||
| 547 | # CONFIG_DM9000 is not set | ||
| 548 | # CONFIG_NET_TULIP is not set | ||
| 549 | # CONFIG_HP100 is not set | ||
| 550 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 551 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 552 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 553 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 554 | # CONFIG_NET_PCI is not set | ||
| 555 | # CONFIG_B44 is not set | ||
| 556 | # CONFIG_NETDEV_1000 is not set | ||
| 557 | # CONFIG_NETDEV_10000 is not set | ||
| 558 | # CONFIG_TR is not set | ||
| 559 | |||
| 560 | # | ||
| 561 | # Wireless LAN | ||
| 562 | # | ||
| 563 | # CONFIG_WLAN_PRE80211 is not set | ||
| 564 | CONFIG_WLAN_80211=y | ||
| 565 | # CONFIG_PCMCIA_RAYCS is not set | ||
| 566 | # CONFIG_IPW2100 is not set | ||
| 567 | # CONFIG_IPW2200 is not set | ||
| 568 | # CONFIG_LIBERTAS is not set | ||
| 569 | # CONFIG_HERMES is not set | ||
| 570 | # CONFIG_ATMEL is not set | ||
| 571 | # CONFIG_AIRO_CS is not set | ||
| 572 | # CONFIG_PCMCIA_WL3501 is not set | ||
| 573 | CONFIG_PRISM54=m | ||
| 574 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 575 | # CONFIG_HOSTAP is not set | ||
| 576 | # CONFIG_NET_PCMCIA is not set | ||
| 577 | # CONFIG_WAN is not set | ||
| 578 | # CONFIG_FDDI is not set | ||
| 579 | # CONFIG_HIPPI is not set | ||
| 580 | # CONFIG_PPP is not set | ||
| 581 | # CONFIG_SLIP is not set | ||
| 582 | # CONFIG_NETCONSOLE is not set | ||
| 583 | # CONFIG_NETPOLL is not set | ||
| 584 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 585 | # CONFIG_ISDN is not set | ||
| 586 | |||
| 587 | # | ||
| 588 | # Input device support | ||
| 589 | # | ||
| 590 | CONFIG_INPUT=y | ||
| 591 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 592 | # CONFIG_INPUT_POLLDEV is not set | ||
| 593 | |||
| 594 | # | ||
| 595 | # Userland interfaces | ||
| 596 | # | ||
| 597 | CONFIG_INPUT_MOUSEDEV=y | ||
| 598 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 599 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 600 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 601 | # CONFIG_INPUT_JOYDEV is not set | ||
| 602 | # CONFIG_INPUT_EVDEV is not set | ||
| 603 | # CONFIG_INPUT_EVBUG is not set | ||
| 604 | |||
| 605 | # | ||
| 606 | # Input Device Drivers | ||
| 607 | # | ||
| 608 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 609 | # CONFIG_INPUT_MOUSE is not set | ||
| 610 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 611 | # CONFIG_INPUT_TABLET is not set | ||
| 612 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 613 | # CONFIG_INPUT_MISC is not set | ||
| 614 | |||
| 615 | # | ||
| 616 | # Hardware I/O ports | ||
| 617 | # | ||
| 618 | # CONFIG_SERIO is not set | ||
| 619 | # CONFIG_GAMEPORT is not set | ||
| 620 | |||
| 621 | # | ||
| 622 | # Character devices | ||
| 623 | # | ||
| 624 | CONFIG_VT=y | ||
| 625 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 626 | CONFIG_VT_CONSOLE=y | ||
| 627 | CONFIG_HW_CONSOLE=y | ||
| 628 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 629 | CONFIG_DEVKMEM=y | ||
| 630 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 631 | # CONFIG_NOZOMI is not set | ||
| 632 | |||
| 633 | # | ||
| 634 | # Serial drivers | ||
| 635 | # | ||
| 636 | # CONFIG_SERIAL_8250 is not set | ||
| 637 | |||
| 638 | # | ||
| 639 | # Non-8250 serial port support | ||
| 640 | # | ||
| 641 | CONFIG_SERIAL_KS8695=y | ||
| 642 | CONFIG_SERIAL_KS8695_CONSOLE=y | ||
| 643 | CONFIG_SERIAL_CORE=y | ||
| 644 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 645 | # CONFIG_SERIAL_JSM is not set | ||
| 646 | CONFIG_UNIX98_PTYS=y | ||
| 647 | CONFIG_LEGACY_PTYS=y | ||
| 648 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 649 | # CONFIG_IPMI_HANDLER is not set | ||
| 650 | CONFIG_HW_RANDOM=m | ||
| 651 | # CONFIG_NVRAM is not set | ||
| 652 | # CONFIG_R3964 is not set | ||
| 653 | # CONFIG_APPLICOM is not set | ||
| 654 | |||
| 655 | # | ||
| 656 | # PCMCIA character devices | ||
| 657 | # | ||
| 658 | # CONFIG_SYNCLINK_CS is not set | ||
| 659 | # CONFIG_CARDMAN_4000 is not set | ||
| 660 | # CONFIG_CARDMAN_4040 is not set | ||
| 661 | # CONFIG_IPWIRELESS is not set | ||
| 662 | # CONFIG_RAW_DRIVER is not set | ||
| 663 | # CONFIG_TCG_TPM is not set | ||
| 664 | CONFIG_DEVPORT=y | ||
| 665 | CONFIG_ACS5KCAN=y | ||
| 666 | CONFIG_I2C=y | ||
| 667 | CONFIG_I2C_BOARDINFO=y | ||
| 668 | CONFIG_I2C_CHARDEV=y | ||
| 669 | CONFIG_I2C_HELPER_AUTO=y | ||
| 670 | CONFIG_I2C_ALGOBIT=y | ||
| 671 | |||
| 672 | # | ||
| 673 | # I2C Hardware Bus support | ||
| 674 | # | ||
| 675 | |||
| 676 | # | ||
| 677 | # PC SMBus host controller drivers | ||
| 678 | # | ||
| 679 | # CONFIG_I2C_ALI1535 is not set | ||
| 680 | # CONFIG_I2C_ALI1563 is not set | ||
| 681 | # CONFIG_I2C_ALI15X3 is not set | ||
| 682 | # CONFIG_I2C_AMD756 is not set | ||
| 683 | # CONFIG_I2C_AMD8111 is not set | ||
| 684 | # CONFIG_I2C_I801 is not set | ||
| 685 | # CONFIG_I2C_ISCH is not set | ||
| 686 | # CONFIG_I2C_PIIX4 is not set | ||
| 687 | # CONFIG_I2C_NFORCE2 is not set | ||
| 688 | # CONFIG_I2C_SIS5595 is not set | ||
| 689 | # CONFIG_I2C_SIS630 is not set | ||
| 690 | # CONFIG_I2C_SIS96X is not set | ||
| 691 | # CONFIG_I2C_VIA is not set | ||
| 692 | # CONFIG_I2C_VIAPRO is not set | ||
| 693 | |||
| 694 | # | ||
| 695 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 696 | # | ||
| 697 | CONFIG_I2C_GPIO=y | ||
| 698 | # CONFIG_I2C_OCORES is not set | ||
| 699 | # CONFIG_I2C_SIMTEC is not set | ||
| 700 | |||
| 701 | # | ||
| 702 | # External I2C/SMBus adapter drivers | ||
| 703 | # | ||
| 704 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 705 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 706 | |||
| 707 | # | ||
| 708 | # Graphics adapter I2C/DDC channel drivers | ||
| 709 | # | ||
| 710 | # CONFIG_I2C_VOODOO3 is not set | ||
| 711 | |||
| 712 | # | ||
| 713 | # Other I2C/SMBus bus drivers | ||
| 714 | # | ||
| 715 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 716 | # CONFIG_I2C_STUB is not set | ||
| 717 | |||
| 718 | # | ||
| 719 | # Miscellaneous I2C Chip support | ||
| 720 | # | ||
| 721 | # CONFIG_DS1682 is not set | ||
| 722 | # CONFIG_AT24 is not set | ||
| 723 | # CONFIG_SENSORS_EEPROM is not set | ||
| 724 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 725 | # CONFIG_PCF8575 is not set | ||
| 726 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 727 | # CONFIG_TPS65010 is not set | ||
| 728 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 729 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 730 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 731 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 732 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 733 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 734 | # CONFIG_SPI is not set | ||
| 735 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 736 | CONFIG_GPIOLIB=y | ||
| 737 | # CONFIG_DEBUG_GPIO is not set | ||
| 738 | CONFIG_GPIO_SYSFS=y | ||
| 739 | |||
| 740 | # | ||
| 741 | # I2C GPIO expanders: | ||
| 742 | # | ||
| 743 | # CONFIG_GPIO_MAX732X is not set | ||
| 744 | CONFIG_GPIO_PCA953X=y | ||
| 745 | # CONFIG_GPIO_PCF857X is not set | ||
| 746 | |||
| 747 | # | ||
| 748 | # PCI GPIO expanders: | ||
| 749 | # | ||
| 750 | # CONFIG_GPIO_BT8XX is not set | ||
| 751 | |||
| 752 | # | ||
| 753 | # SPI GPIO expanders: | ||
| 754 | # | ||
| 755 | # CONFIG_W1 is not set | ||
| 756 | # CONFIG_POWER_SUPPLY is not set | ||
| 757 | CONFIG_HWMON=y | ||
| 758 | # CONFIG_HWMON_VID is not set | ||
| 759 | # CONFIG_SENSORS_AD7414 is not set | ||
| 760 | # CONFIG_SENSORS_AD7418 is not set | ||
| 761 | # CONFIG_SENSORS_ADM1021 is not set | ||
| 762 | # CONFIG_SENSORS_ADM1025 is not set | ||
| 763 | # CONFIG_SENSORS_ADM1026 is not set | ||
| 764 | # CONFIG_SENSORS_ADM1029 is not set | ||
| 765 | # CONFIG_SENSORS_ADM1031 is not set | ||
| 766 | # CONFIG_SENSORS_ADM9240 is not set | ||
| 767 | # CONFIG_SENSORS_ADT7470 is not set | ||
| 768 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 769 | # CONFIG_SENSORS_ATXP1 is not set | ||
| 770 | # CONFIG_SENSORS_DS1621 is not set | ||
| 771 | # CONFIG_SENSORS_I5K_AMB is not set | ||
| 772 | # CONFIG_SENSORS_F71805F is not set | ||
| 773 | # CONFIG_SENSORS_F71882FG is not set | ||
| 774 | # CONFIG_SENSORS_F75375S is not set | ||
| 775 | # CONFIG_SENSORS_GL518SM is not set | ||
| 776 | # CONFIG_SENSORS_GL520SM is not set | ||
| 777 | # CONFIG_SENSORS_IT87 is not set | ||
| 778 | # CONFIG_SENSORS_LM63 is not set | ||
| 779 | # CONFIG_SENSORS_LM75 is not set | ||
| 780 | # CONFIG_SENSORS_LM77 is not set | ||
| 781 | # CONFIG_SENSORS_LM78 is not set | ||
| 782 | # CONFIG_SENSORS_LM80 is not set | ||
| 783 | # CONFIG_SENSORS_LM83 is not set | ||
| 784 | # CONFIG_SENSORS_LM85 is not set | ||
| 785 | # CONFIG_SENSORS_LM87 is not set | ||
| 786 | # CONFIG_SENSORS_LM90 is not set | ||
| 787 | # CONFIG_SENSORS_LM92 is not set | ||
| 788 | # CONFIG_SENSORS_LM93 is not set | ||
| 789 | # CONFIG_SENSORS_MAX1619 is not set | ||
| 790 | # CONFIG_SENSORS_MAX6650 is not set | ||
| 791 | # CONFIG_SENSORS_PC87360 is not set | ||
| 792 | # CONFIG_SENSORS_PC87427 is not set | ||
| 793 | # CONFIG_SENSORS_SIS5595 is not set | ||
| 794 | # CONFIG_SENSORS_DME1737 is not set | ||
| 795 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
| 796 | # CONFIG_SENSORS_SMSC47M192 is not set | ||
| 797 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
| 798 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 799 | # CONFIG_SENSORS_THMC50 is not set | ||
| 800 | # CONFIG_SENSORS_VIA686A is not set | ||
| 801 | # CONFIG_SENSORS_VT1211 is not set | ||
| 802 | # CONFIG_SENSORS_VT8231 is not set | ||
| 803 | # CONFIG_SENSORS_W83781D is not set | ||
| 804 | # CONFIG_SENSORS_W83791D is not set | ||
| 805 | # CONFIG_SENSORS_W83792D is not set | ||
| 806 | # CONFIG_SENSORS_W83793 is not set | ||
| 807 | # CONFIG_SENSORS_W83L785TS is not set | ||
| 808 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 809 | # CONFIG_SENSORS_W83627HF is not set | ||
| 810 | # CONFIG_SENSORS_W83627EHF is not set | ||
| 811 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
| 812 | CONFIG_WATCHDOG=y | ||
| 813 | # CONFIG_WATCHDOG_NOWAYOUT is not set | ||
| 814 | |||
| 815 | # | ||
| 816 | # Watchdog Device Drivers | ||
| 817 | # | ||
| 818 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 819 | CONFIG_KS8695_WATCHDOG=y | ||
| 820 | # CONFIG_ALIM7101_WDT is not set | ||
| 821 | |||
| 822 | # | ||
| 823 | # PCI-based Watchdog Cards | ||
| 824 | # | ||
| 825 | # CONFIG_PCIPCWATCHDOG is not set | ||
| 826 | # CONFIG_WDTPCI is not set | ||
| 827 | |||
| 828 | # | ||
| 829 | # Sonics Silicon Backplane | ||
| 830 | # | ||
| 831 | CONFIG_SSB_POSSIBLE=y | ||
| 832 | # CONFIG_SSB is not set | ||
| 833 | |||
| 834 | # | ||
| 835 | # Multifunction device drivers | ||
| 836 | # | ||
| 837 | # CONFIG_MFD_CORE is not set | ||
| 838 | # CONFIG_MFD_SM501 is not set | ||
| 839 | # CONFIG_MFD_ASIC3 is not set | ||
| 840 | # CONFIG_HTC_EGPIO is not set | ||
| 841 | # CONFIG_HTC_PASIC3 is not set | ||
| 842 | # CONFIG_MFD_TMIO is not set | ||
| 843 | # CONFIG_MFD_T7L66XB is not set | ||
| 844 | # CONFIG_MFD_TC6387XB is not set | ||
| 845 | # CONFIG_MFD_TC6393XB is not set | ||
| 846 | |||
| 847 | # | ||
| 848 | # Multimedia devices | ||
| 849 | # | ||
| 850 | |||
| 851 | # | ||
| 852 | # Multimedia core support | ||
| 853 | # | ||
| 854 | # CONFIG_VIDEO_DEV is not set | ||
| 855 | # CONFIG_DVB_CORE is not set | ||
| 856 | # CONFIG_VIDEO_MEDIA is not set | ||
| 857 | |||
| 858 | # | ||
| 859 | # Multimedia drivers | ||
| 860 | # | ||
| 861 | # CONFIG_DAB is not set | ||
| 862 | |||
| 863 | # | ||
| 864 | # Graphics support | ||
| 865 | # | ||
| 866 | # CONFIG_DRM is not set | ||
| 867 | # CONFIG_VGASTATE is not set | ||
| 868 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 869 | # CONFIG_FB is not set | ||
| 870 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 871 | |||
| 872 | # | ||
| 873 | # Display device support | ||
| 874 | # | ||
| 875 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 876 | |||
| 877 | # | ||
| 878 | # Console display driver support | ||
| 879 | # | ||
| 880 | # CONFIG_VGA_CONSOLE is not set | ||
| 881 | CONFIG_DUMMY_CONSOLE=y | ||
| 882 | # CONFIG_SOUND is not set | ||
| 883 | CONFIG_HID_SUPPORT=y | ||
| 884 | CONFIG_HID=y | ||
| 885 | CONFIG_HID_DEBUG=y | ||
| 886 | # CONFIG_HIDRAW is not set | ||
| 887 | CONFIG_USB_SUPPORT=y | ||
| 888 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 889 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 890 | CONFIG_USB_ARCH_HAS_EHCI=y | ||
| 891 | # CONFIG_USB is not set | ||
| 892 | |||
| 893 | # | ||
| 894 | # Enable Host or Gadget support to see Inventra options | ||
| 895 | # | ||
| 896 | |||
| 897 | # | ||
| 898 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | ||
| 899 | # | ||
| 900 | # CONFIG_USB_GADGET is not set | ||
| 901 | # CONFIG_MMC is not set | ||
| 902 | # CONFIG_NEW_LEDS is not set | ||
| 903 | CONFIG_RTC_LIB=y | ||
| 904 | CONFIG_RTC_CLASS=y | ||
| 905 | CONFIG_RTC_HCTOSYS=y | ||
| 906 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 907 | # CONFIG_RTC_DEBUG is not set | ||
| 908 | |||
| 909 | # | ||
| 910 | # RTC interfaces | ||
| 911 | # | ||
| 912 | CONFIG_RTC_INTF_SYSFS=y | ||
| 913 | CONFIG_RTC_INTF_PROC=y | ||
| 914 | CONFIG_RTC_INTF_DEV=y | ||
| 915 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 916 | # CONFIG_RTC_DRV_TEST is not set | ||
| 917 | |||
| 918 | # | ||
| 919 | # I2C RTC drivers | ||
| 920 | # | ||
| 921 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 922 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 923 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 924 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 925 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 926 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 927 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 928 | CONFIG_RTC_DRV_PCF8563=y | ||
| 929 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 930 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 931 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 932 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 933 | |||
| 934 | # | ||
| 935 | # SPI RTC drivers | ||
| 936 | # | ||
| 937 | |||
| 938 | # | ||
| 939 | # Platform RTC drivers | ||
| 940 | # | ||
| 941 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 942 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 943 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 944 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 945 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 946 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 947 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 948 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 949 | |||
| 950 | # | ||
| 951 | # on-CPU RTC drivers | ||
| 952 | # | ||
| 953 | # CONFIG_DMADEVICES is not set | ||
| 954 | |||
| 955 | # | ||
| 956 | # Voltage and Current regulators | ||
| 957 | # | ||
| 958 | # CONFIG_REGULATOR is not set | ||
| 959 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set | ||
| 960 | # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set | ||
| 961 | # CONFIG_REGULATOR_BQ24022 is not set | ||
| 962 | # CONFIG_UIO is not set | ||
| 963 | |||
| 964 | # | ||
| 965 | # File systems | ||
| 966 | # | ||
| 967 | CONFIG_EXT2_FS=y | ||
| 968 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 969 | # CONFIG_EXT2_FS_XIP is not set | ||
| 970 | # CONFIG_EXT3_FS is not set | ||
| 971 | # CONFIG_EXT4DEV_FS is not set | ||
| 972 | # CONFIG_REISERFS_FS is not set | ||
| 973 | # CONFIG_JFS_FS is not set | ||
| 974 | # CONFIG_FS_POSIX_ACL is not set | ||
| 975 | # CONFIG_XFS_FS is not set | ||
| 976 | # CONFIG_OCFS2_FS is not set | ||
| 977 | CONFIG_DNOTIFY=y | ||
| 978 | CONFIG_INOTIFY=y | ||
| 979 | CONFIG_INOTIFY_USER=y | ||
| 980 | # CONFIG_QUOTA is not set | ||
| 981 | # CONFIG_AUTOFS_FS is not set | ||
| 982 | # CONFIG_AUTOFS4_FS is not set | ||
| 983 | # CONFIG_FUSE_FS is not set | ||
| 984 | |||
| 985 | # | ||
| 986 | # CD-ROM/DVD Filesystems | ||
| 987 | # | ||
| 988 | # CONFIG_ISO9660_FS is not set | ||
| 989 | # CONFIG_UDF_FS is not set | ||
| 990 | |||
| 991 | # | ||
| 992 | # DOS/FAT/NT Filesystems | ||
| 993 | # | ||
| 994 | # CONFIG_MSDOS_FS is not set | ||
| 995 | # CONFIG_VFAT_FS is not set | ||
| 996 | # CONFIG_NTFS_FS is not set | ||
| 997 | |||
| 998 | # | ||
| 999 | # Pseudo filesystems | ||
| 1000 | # | ||
| 1001 | CONFIG_PROC_FS=y | ||
| 1002 | CONFIG_PROC_SYSCTL=y | ||
| 1003 | CONFIG_SYSFS=y | ||
| 1004 | CONFIG_TMPFS=y | ||
| 1005 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1006 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1007 | # CONFIG_CONFIGFS_FS is not set | ||
| 1008 | |||
| 1009 | # | ||
| 1010 | # Miscellaneous filesystems | ||
| 1011 | # | ||
| 1012 | # CONFIG_ADFS_FS is not set | ||
| 1013 | # CONFIG_AFFS_FS is not set | ||
| 1014 | # CONFIG_HFS_FS is not set | ||
| 1015 | # CONFIG_HFSPLUS_FS is not set | ||
| 1016 | # CONFIG_BEFS_FS is not set | ||
| 1017 | # CONFIG_BFS_FS is not set | ||
| 1018 | # CONFIG_EFS_FS is not set | ||
| 1019 | CONFIG_JFFS2_FS=y | ||
| 1020 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 1021 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 1022 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1023 | CONFIG_JFFS2_SUMMARY=y | ||
| 1024 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 1025 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 1026 | CONFIG_JFFS2_ZLIB=y | ||
| 1027 | # CONFIG_JFFS2_LZO is not set | ||
| 1028 | CONFIG_JFFS2_RTIME=y | ||
| 1029 | CONFIG_JFFS2_RUBIN=y | ||
| 1030 | # CONFIG_JFFS2_CMODE_NONE is not set | ||
| 1031 | CONFIG_JFFS2_CMODE_PRIORITY=y | ||
| 1032 | # CONFIG_JFFS2_CMODE_SIZE is not set | ||
| 1033 | # CONFIG_JFFS2_CMODE_FAVOURLZO is not set | ||
| 1034 | CONFIG_CRAMFS=y | ||
| 1035 | # CONFIG_VXFS_FS is not set | ||
| 1036 | # CONFIG_MINIX_FS is not set | ||
| 1037 | # CONFIG_OMFS_FS is not set | ||
| 1038 | # CONFIG_HPFS_FS is not set | ||
| 1039 | # CONFIG_QNX4FS_FS is not set | ||
| 1040 | # CONFIG_ROMFS_FS is not set | ||
| 1041 | # CONFIG_SYSV_FS is not set | ||
| 1042 | # CONFIG_UFS_FS is not set | ||
| 1043 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1044 | CONFIG_NFS_FS=y | ||
| 1045 | CONFIG_NFS_V3=y | ||
| 1046 | # CONFIG_NFS_V3_ACL is not set | ||
| 1047 | # CONFIG_NFS_V4 is not set | ||
| 1048 | CONFIG_ROOT_NFS=y | ||
| 1049 | # CONFIG_NFSD is not set | ||
| 1050 | CONFIG_LOCKD=y | ||
| 1051 | CONFIG_LOCKD_V4=y | ||
| 1052 | CONFIG_NFS_COMMON=y | ||
| 1053 | CONFIG_SUNRPC=y | ||
| 1054 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 1055 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1056 | # CONFIG_SMB_FS is not set | ||
| 1057 | # CONFIG_CIFS is not set | ||
| 1058 | # CONFIG_NCP_FS is not set | ||
| 1059 | # CONFIG_CODA_FS is not set | ||
| 1060 | # CONFIG_AFS_FS is not set | ||
| 1061 | |||
| 1062 | # | ||
| 1063 | # Partition Types | ||
| 1064 | # | ||
| 1065 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 1066 | CONFIG_MSDOS_PARTITION=y | ||
| 1067 | # CONFIG_NLS is not set | ||
| 1068 | # CONFIG_DLM is not set | ||
| 1069 | |||
| 1070 | # | ||
| 1071 | # Kernel hacking | ||
| 1072 | # | ||
| 1073 | # CONFIG_PRINTK_TIME is not set | ||
| 1074 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1075 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1076 | CONFIG_FRAME_WARN=1024 | ||
| 1077 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1078 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1079 | # CONFIG_DEBUG_FS is not set | ||
| 1080 | # CONFIG_HEADERS_CHECK is not set | ||
| 1081 | CONFIG_DEBUG_KERNEL=y | ||
| 1082 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1083 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1084 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1085 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1086 | CONFIG_SCHED_DEBUG=y | ||
| 1087 | # CONFIG_SCHEDSTATS is not set | ||
| 1088 | # CONFIG_TIMER_STATS is not set | ||
| 1089 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1090 | # CONFIG_DEBUG_SLAB is not set | ||
| 1091 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1092 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1093 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1094 | CONFIG_DEBUG_MUTEXES=y | ||
| 1095 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1096 | # CONFIG_PROVE_LOCKING is not set | ||
| 1097 | # CONFIG_LOCK_STAT is not set | ||
| 1098 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1099 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1100 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1101 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1102 | # CONFIG_DEBUG_INFO is not set | ||
| 1103 | # CONFIG_DEBUG_VM is not set | ||
| 1104 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1105 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 1106 | # CONFIG_DEBUG_LIST is not set | ||
| 1107 | # CONFIG_DEBUG_SG is not set | ||
| 1108 | CONFIG_FRAME_POINTER=y | ||
| 1109 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1110 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1111 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1112 | # CONFIG_FAULT_INJECTION is not set | ||
| 1113 | # CONFIG_LATENCYTOP is not set | ||
| 1114 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1115 | CONFIG_HAVE_FTRACE=y | ||
| 1116 | CONFIG_HAVE_DYNAMIC_FTRACE=y | ||
| 1117 | # CONFIG_FTRACE is not set | ||
| 1118 | # CONFIG_SCHED_TRACER is not set | ||
| 1119 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1120 | # CONFIG_SAMPLES is not set | ||
| 1121 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1122 | # CONFIG_KGDB is not set | ||
| 1123 | CONFIG_DEBUG_USER=y | ||
| 1124 | # CONFIG_DEBUG_ERRORS is not set | ||
| 1125 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1126 | CONFIG_DEBUG_LL=y | ||
| 1127 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 1128 | |||
| 1129 | # | ||
| 1130 | # Security options | ||
| 1131 | # | ||
| 1132 | # CONFIG_KEYS is not set | ||
| 1133 | # CONFIG_SECURITY is not set | ||
| 1134 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1135 | CONFIG_CRYPTO=y | ||
| 1136 | |||
| 1137 | # | ||
| 1138 | # Crypto core or helper | ||
| 1139 | # | ||
| 1140 | # CONFIG_CRYPTO_MANAGER is not set | ||
| 1141 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1142 | # CONFIG_CRYPTO_NULL is not set | ||
| 1143 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1144 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1145 | # CONFIG_CRYPTO_TEST is not set | ||
| 1146 | |||
| 1147 | # | ||
| 1148 | # Authenticated Encryption with Associated Data | ||
| 1149 | # | ||
| 1150 | # CONFIG_CRYPTO_CCM is not set | ||
| 1151 | # CONFIG_CRYPTO_GCM is not set | ||
| 1152 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1153 | |||
| 1154 | # | ||
| 1155 | # Block modes | ||
| 1156 | # | ||
| 1157 | # CONFIG_CRYPTO_CBC is not set | ||
| 1158 | # CONFIG_CRYPTO_CTR is not set | ||
| 1159 | # CONFIG_CRYPTO_CTS is not set | ||
| 1160 | # CONFIG_CRYPTO_ECB is not set | ||
| 1161 | # CONFIG_CRYPTO_LRW is not set | ||
| 1162 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1163 | # CONFIG_CRYPTO_XTS is not set | ||
| 1164 | |||
| 1165 | # | ||
| 1166 | # Hash modes | ||
| 1167 | # | ||
| 1168 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1169 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1170 | |||
| 1171 | # | ||
| 1172 | # Digest | ||
| 1173 | # | ||
| 1174 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1175 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1176 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1177 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1178 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1179 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1180 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1181 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1182 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1183 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1184 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1185 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1186 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1187 | |||
| 1188 | # | ||
| 1189 | # Ciphers | ||
| 1190 | # | ||
| 1191 | # CONFIG_CRYPTO_AES is not set | ||
| 1192 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1193 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1194 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1195 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1196 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1197 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1198 | # CONFIG_CRYPTO_DES is not set | ||
| 1199 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1200 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1201 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1202 | # CONFIG_CRYPTO_SEED is not set | ||
| 1203 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1204 | # CONFIG_CRYPTO_TEA is not set | ||
| 1205 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1206 | |||
| 1207 | # | ||
| 1208 | # Compression | ||
| 1209 | # | ||
| 1210 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1211 | # CONFIG_CRYPTO_LZO is not set | ||
| 1212 | CONFIG_CRYPTO_HW=y | ||
| 1213 | # CONFIG_CRYPTO_DEV_HIFN_795X is not set | ||
| 1214 | |||
| 1215 | # | ||
| 1216 | # Library routines | ||
| 1217 | # | ||
| 1218 | CONFIG_BITREVERSE=y | ||
| 1219 | # CONFIG_GENERIC_FIND_FIRST_BIT is not set | ||
| 1220 | # CONFIG_GENERIC_FIND_NEXT_BIT is not set | ||
| 1221 | # CONFIG_CRC_CCITT is not set | ||
| 1222 | # CONFIG_CRC16 is not set | ||
| 1223 | # CONFIG_CRC_T10DIF is not set | ||
| 1224 | # CONFIG_CRC_ITU_T is not set | ||
| 1225 | CONFIG_CRC32=y | ||
| 1226 | # CONFIG_CRC7 is not set | ||
| 1227 | # CONFIG_LIBCRC32C is not set | ||
| 1228 | CONFIG_ZLIB_INFLATE=y | ||
| 1229 | CONFIG_ZLIB_DEFLATE=y | ||
| 1230 | CONFIG_PLIST=y | ||
| 1231 | CONFIG_HAS_IOMEM=y | ||
| 1232 | CONFIG_HAS_IOPORT=y | ||
| 1233 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/acs5k_tiny_defconfig b/arch/arm/configs/acs5k_tiny_defconfig new file mode 100644 index 000000000000..8e3d084afd78 --- /dev/null +++ b/arch/arm/configs/acs5k_tiny_defconfig | |||
| @@ -0,0 +1,941 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.27-simtec-micrel1 | ||
| 4 | # Tue Jan 6 13:23:07 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | # CONFIG_GENERIC_TIME is not set | ||
| 10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_ARCH_SUPPORTS_AOUT=y | ||
| 26 | CONFIG_ZONE_DMA=y | ||
| 27 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 28 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 29 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 30 | |||
| 31 | # | ||
| 32 | # General setup | ||
| 33 | # | ||
| 34 | CONFIG_EXPERIMENTAL=y | ||
| 35 | CONFIG_BROKEN_ON_SMP=y | ||
| 36 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 37 | CONFIG_LOCALVERSION="" | ||
| 38 | CONFIG_LOCALVERSION_AUTO=y | ||
| 39 | # CONFIG_SWAP is not set | ||
| 40 | CONFIG_SYSVIPC=y | ||
| 41 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 42 | CONFIG_POSIX_MQUEUE=y | ||
| 43 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 44 | # CONFIG_TASKSTATS is not set | ||
| 45 | # CONFIG_AUDIT is not set | ||
| 46 | # CONFIG_IKCONFIG is not set | ||
| 47 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 48 | # CONFIG_CGROUPS is not set | ||
| 49 | # CONFIG_GROUP_SCHED is not set | ||
| 50 | CONFIG_SYSFS_DEPRECATED=y | ||
| 51 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 52 | # CONFIG_RELAY is not set | ||
| 53 | CONFIG_NAMESPACES=y | ||
| 54 | # CONFIG_UTS_NS is not set | ||
| 55 | # CONFIG_IPC_NS is not set | ||
| 56 | # CONFIG_USER_NS is not set | ||
| 57 | # CONFIG_PID_NS is not set | ||
| 58 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 59 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 60 | CONFIG_SYSCTL=y | ||
| 61 | # CONFIG_EMBEDDED is not set | ||
| 62 | CONFIG_UID16=y | ||
| 63 | CONFIG_SYSCTL_SYSCALL=y | ||
| 64 | CONFIG_KALLSYMS=y | ||
| 65 | # CONFIG_KALLSYMS_ALL is not set | ||
| 66 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 67 | CONFIG_HOTPLUG=y | ||
| 68 | CONFIG_PRINTK=y | ||
| 69 | CONFIG_BUG=y | ||
| 70 | CONFIG_ELF_CORE=y | ||
| 71 | CONFIG_COMPAT_BRK=y | ||
| 72 | CONFIG_BASE_FULL=y | ||
| 73 | CONFIG_FUTEX=y | ||
| 74 | CONFIG_ANON_INODES=y | ||
| 75 | CONFIG_EPOLL=y | ||
| 76 | CONFIG_SIGNALFD=y | ||
| 77 | CONFIG_TIMERFD=y | ||
| 78 | CONFIG_EVENTFD=y | ||
| 79 | CONFIG_SHMEM=y | ||
| 80 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 81 | CONFIG_SLAB=y | ||
| 82 | # CONFIG_SLUB is not set | ||
| 83 | # CONFIG_SLOB is not set | ||
| 84 | # CONFIG_PROFILING is not set | ||
| 85 | # CONFIG_MARKERS is not set | ||
| 86 | CONFIG_HAVE_OPROFILE=y | ||
| 87 | # CONFIG_KPROBES is not set | ||
| 88 | # CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set | ||
| 89 | # CONFIG_HAVE_IOREMAP_PROT is not set | ||
| 90 | CONFIG_HAVE_KPROBES=y | ||
| 91 | CONFIG_HAVE_KRETPROBES=y | ||
| 92 | # CONFIG_HAVE_ARCH_TRACEHOOK is not set | ||
| 93 | # CONFIG_HAVE_DMA_ATTRS is not set | ||
| 94 | # CONFIG_USE_GENERIC_SMP_HELPERS is not set | ||
| 95 | # CONFIG_HAVE_CLK is not set | ||
| 96 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 97 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 98 | CONFIG_SLABINFO=y | ||
| 99 | CONFIG_RT_MUTEXES=y | ||
| 100 | # CONFIG_TINY_SHMEM is not set | ||
| 101 | CONFIG_BASE_SMALL=0 | ||
| 102 | CONFIG_MODULES=y | ||
| 103 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 104 | CONFIG_MODULE_UNLOAD=y | ||
| 105 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 106 | # CONFIG_MODVERSIONS is not set | ||
| 107 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 108 | CONFIG_KMOD=y | ||
| 109 | CONFIG_BLOCK=y | ||
| 110 | # CONFIG_LBD is not set | ||
| 111 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 112 | # CONFIG_LSF is not set | ||
| 113 | # CONFIG_BLK_DEV_BSG is not set | ||
| 114 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 115 | |||
| 116 | # | ||
| 117 | # IO Schedulers | ||
| 118 | # | ||
| 119 | CONFIG_IOSCHED_NOOP=y | ||
| 120 | CONFIG_IOSCHED_AS=y | ||
| 121 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 122 | # CONFIG_IOSCHED_CFQ is not set | ||
| 123 | CONFIG_DEFAULT_AS=y | ||
| 124 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 125 | # CONFIG_DEFAULT_CFQ is not set | ||
| 126 | # CONFIG_DEFAULT_NOOP is not set | ||
| 127 | CONFIG_DEFAULT_IOSCHED="anticipatory" | ||
| 128 | CONFIG_CLASSIC_RCU=y | ||
| 129 | |||
| 130 | # | ||
| 131 | # System Type | ||
| 132 | # | ||
| 133 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 134 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 135 | # CONFIG_ARCH_REALVIEW is not set | ||
| 136 | # CONFIG_ARCH_VERSATILE is not set | ||
| 137 | # CONFIG_ARCH_AT91 is not set | ||
| 138 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 139 | # CONFIG_ARCH_CLPS711X is not set | ||
| 140 | # CONFIG_ARCH_EBSA110 is not set | ||
| 141 | # CONFIG_ARCH_EP93XX is not set | ||
| 142 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 143 | # CONFIG_ARCH_NETX is not set | ||
| 144 | # CONFIG_ARCH_H720X is not set | ||
| 145 | # CONFIG_ARCH_IMX is not set | ||
| 146 | # CONFIG_ARCH_IOP13XX is not set | ||
| 147 | # CONFIG_ARCH_IOP32X is not set | ||
| 148 | # CONFIG_ARCH_IOP33X is not set | ||
| 149 | # CONFIG_ARCH_IXP23XX is not set | ||
| 150 | # CONFIG_ARCH_IXP2000 is not set | ||
| 151 | # CONFIG_ARCH_IXP4XX is not set | ||
| 152 | # CONFIG_ARCH_L7200 is not set | ||
| 153 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 154 | CONFIG_ARCH_KS8695=y | ||
| 155 | # CONFIG_ARCH_NS9XXX is not set | ||
| 156 | # CONFIG_ARCH_LOKI is not set | ||
| 157 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 158 | # CONFIG_ARCH_MXC is not set | ||
| 159 | # CONFIG_ARCH_ORION5X is not set | ||
| 160 | # CONFIG_ARCH_PNX4008 is not set | ||
| 161 | # CONFIG_ARCH_PXA is not set | ||
| 162 | # CONFIG_ARCH_RPC is not set | ||
| 163 | # CONFIG_ARCH_SA1100 is not set | ||
| 164 | # CONFIG_ARCH_S3C2410 is not set | ||
| 165 | # CONFIG_ARCH_SHARK is not set | ||
| 166 | # CONFIG_ARCH_LH7A40X is not set | ||
| 167 | # CONFIG_ARCH_DAVINCI is not set | ||
| 168 | # CONFIG_ARCH_OMAP is not set | ||
| 169 | # CONFIG_ARCH_MSM7X00A is not set | ||
| 170 | |||
| 171 | # | ||
| 172 | # Boot options | ||
| 173 | # | ||
| 174 | |||
| 175 | # | ||
| 176 | # Power management | ||
| 177 | # | ||
| 178 | |||
| 179 | # | ||
| 180 | # Kendin/Micrel KS8695 Implementations | ||
| 181 | # | ||
| 182 | # CONFIG_MACH_KS8695 is not set | ||
| 183 | # CONFIG_MACH_DSM320 is not set | ||
| 184 | CONFIG_MACH_ACS5K=y | ||
| 185 | |||
| 186 | # | ||
| 187 | # Processor Type | ||
| 188 | # | ||
| 189 | CONFIG_CPU_32=y | ||
| 190 | CONFIG_CPU_ARM922T=y | ||
| 191 | CONFIG_CPU_32v4T=y | ||
| 192 | CONFIG_CPU_ABRT_EV4T=y | ||
| 193 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 194 | CONFIG_CPU_CACHE_V4WT=y | ||
| 195 | CONFIG_CPU_CACHE_VIVT=y | ||
| 196 | CONFIG_CPU_COPY_V4WB=y | ||
| 197 | CONFIG_CPU_TLB_V4WBI=y | ||
| 198 | CONFIG_CPU_CP15=y | ||
| 199 | CONFIG_CPU_CP15_MMU=y | ||
| 200 | |||
| 201 | # | ||
| 202 | # Processor Features | ||
| 203 | # | ||
| 204 | # CONFIG_ARM_THUMB is not set | ||
| 205 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 206 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 207 | # CONFIG_CPU_DCACHE_WRITETHROUGH is not set | ||
| 208 | # CONFIG_OUTER_CACHE is not set | ||
| 209 | |||
| 210 | # | ||
| 211 | # Bus support | ||
| 212 | # | ||
| 213 | # CONFIG_PCI is not set | ||
| 214 | # CONFIG_PCI_SYSCALL is not set | ||
| 215 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 216 | # CONFIG_PCCARD is not set | ||
| 217 | |||
| 218 | # | ||
| 219 | # Kernel Features | ||
| 220 | # | ||
| 221 | # CONFIG_TICK_ONESHOT is not set | ||
| 222 | # CONFIG_PREEMPT is not set | ||
| 223 | CONFIG_HZ=100 | ||
| 224 | CONFIG_AEABI=y | ||
| 225 | CONFIG_OABI_COMPAT=y | ||
| 226 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 227 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | ||
| 228 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 229 | CONFIG_FLATMEM_MANUAL=y | ||
| 230 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 231 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 232 | CONFIG_FLATMEM=y | ||
| 233 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 234 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 235 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 236 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 237 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 238 | # CONFIG_RESOURCES_64BIT is not set | ||
| 239 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 240 | CONFIG_BOUNCE=y | ||
| 241 | CONFIG_VIRT_TO_BUS=y | ||
| 242 | # CONFIG_LEDS is not set | ||
| 243 | CONFIG_ALIGNMENT_TRAP=y | ||
| 244 | |||
| 245 | # | ||
| 246 | # Boot options | ||
| 247 | # | ||
| 248 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 249 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 250 | CONFIG_CMDLINE="console=ttyAM0,115200 init=/bin/sh" | ||
| 251 | # CONFIG_XIP_KERNEL is not set | ||
| 252 | # CONFIG_KEXEC is not set | ||
| 253 | |||
| 254 | # | ||
| 255 | # Floating point emulation | ||
| 256 | # | ||
| 257 | |||
| 258 | # | ||
| 259 | # At least one emulation must be selected | ||
| 260 | # | ||
| 261 | CONFIG_FPE_NWFPE=y | ||
| 262 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 263 | # CONFIG_FPE_FASTFPE is not set | ||
| 264 | |||
| 265 | # | ||
| 266 | # Userspace binary formats | ||
| 267 | # | ||
| 268 | CONFIG_BINFMT_ELF=y | ||
| 269 | # CONFIG_BINFMT_AOUT is not set | ||
| 270 | # CONFIG_BINFMT_MISC is not set | ||
| 271 | |||
| 272 | # | ||
| 273 | # Power management options | ||
| 274 | # | ||
| 275 | # CONFIG_PM is not set | ||
| 276 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 277 | CONFIG_NET=y | ||
| 278 | |||
| 279 | # | ||
| 280 | # Networking options | ||
| 281 | # | ||
| 282 | CONFIG_PACKET=y | ||
| 283 | # CONFIG_PACKET_MMAP is not set | ||
| 284 | CONFIG_UNIX=y | ||
| 285 | # CONFIG_NET_KEY is not set | ||
| 286 | CONFIG_INET=y | ||
| 287 | # CONFIG_IP_MULTICAST is not set | ||
| 288 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 289 | CONFIG_IP_FIB_HASH=y | ||
| 290 | # CONFIG_IP_PNP is not set | ||
| 291 | # CONFIG_NET_IPIP is not set | ||
| 292 | # CONFIG_NET_IPGRE is not set | ||
| 293 | # CONFIG_ARPD is not set | ||
| 294 | # CONFIG_SYN_COOKIES is not set | ||
| 295 | # CONFIG_INET_AH is not set | ||
| 296 | # CONFIG_INET_ESP is not set | ||
| 297 | # CONFIG_INET_IPCOMP is not set | ||
| 298 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 299 | # CONFIG_INET_TUNNEL is not set | ||
| 300 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 301 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 302 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 303 | # CONFIG_INET_LRO is not set | ||
| 304 | CONFIG_INET_DIAG=y | ||
| 305 | CONFIG_INET_TCP_DIAG=y | ||
| 306 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 307 | CONFIG_TCP_CONG_CUBIC=y | ||
| 308 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 309 | # CONFIG_TCP_MD5SIG is not set | ||
| 310 | # CONFIG_IPV6 is not set | ||
| 311 | # CONFIG_NETWORK_SECMARK is not set | ||
| 312 | # CONFIG_NETFILTER is not set | ||
| 313 | # CONFIG_IP_DCCP is not set | ||
| 314 | # CONFIG_IP_SCTP is not set | ||
| 315 | # CONFIG_TIPC is not set | ||
| 316 | # CONFIG_ATM is not set | ||
| 317 | # CONFIG_BRIDGE is not set | ||
| 318 | # CONFIG_VLAN_8021Q is not set | ||
| 319 | # CONFIG_DECNET is not set | ||
| 320 | # CONFIG_LLC2 is not set | ||
| 321 | # CONFIG_IPX is not set | ||
| 322 | # CONFIG_ATALK is not set | ||
| 323 | # CONFIG_X25 is not set | ||
| 324 | # CONFIG_LAPB is not set | ||
| 325 | # CONFIG_ECONET is not set | ||
| 326 | # CONFIG_WAN_ROUTER is not set | ||
| 327 | # CONFIG_NET_SCHED is not set | ||
| 328 | |||
| 329 | # | ||
| 330 | # Network testing | ||
| 331 | # | ||
| 332 | # CONFIG_NET_PKTGEN is not set | ||
| 333 | # CONFIG_HAMRADIO is not set | ||
| 334 | # CONFIG_CAN is not set | ||
| 335 | # CONFIG_IRDA is not set | ||
| 336 | # CONFIG_BT is not set | ||
| 337 | # CONFIG_AF_RXRPC is not set | ||
| 338 | |||
| 339 | # | ||
| 340 | # Wireless | ||
| 341 | # | ||
| 342 | # CONFIG_CFG80211 is not set | ||
| 343 | # CONFIG_WIRELESS_EXT is not set | ||
| 344 | # CONFIG_MAC80211 is not set | ||
| 345 | # CONFIG_IEEE80211 is not set | ||
| 346 | # CONFIG_RFKILL is not set | ||
| 347 | # CONFIG_NET_9P is not set | ||
| 348 | |||
| 349 | # | ||
| 350 | # Device Drivers | ||
| 351 | # | ||
| 352 | |||
| 353 | # | ||
| 354 | # Generic Driver Options | ||
| 355 | # | ||
| 356 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 357 | CONFIG_STANDALONE=y | ||
| 358 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 359 | CONFIG_FW_LOADER=y | ||
| 360 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 361 | CONFIG_EXTRA_FIRMWARE="" | ||
| 362 | # CONFIG_DEBUG_DRIVER is not set | ||
| 363 | # CONFIG_DEBUG_DEVRES is not set | ||
| 364 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 365 | # CONFIG_CONNECTOR is not set | ||
| 366 | CONFIG_MTD=y | ||
| 367 | # CONFIG_MTD_DEBUG is not set | ||
| 368 | CONFIG_MTD_CONCAT=y | ||
| 369 | CONFIG_MTD_PARTITIONS=y | ||
| 370 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 371 | # CONFIG_MTD_CMDLINE_PARTS is not set | ||
| 372 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 373 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 374 | |||
| 375 | # | ||
| 376 | # User Modules And Translation Layers | ||
| 377 | # | ||
| 378 | CONFIG_MTD_CHAR=y | ||
| 379 | CONFIG_MTD_BLKDEVS=y | ||
| 380 | CONFIG_MTD_BLOCK=y | ||
| 381 | # CONFIG_FTL is not set | ||
| 382 | # CONFIG_NFTL is not set | ||
| 383 | # CONFIG_INFTL is not set | ||
| 384 | # CONFIG_RFD_FTL is not set | ||
| 385 | # CONFIG_SSFDC is not set | ||
| 386 | # CONFIG_MTD_OOPS is not set | ||
| 387 | |||
| 388 | # | ||
| 389 | # RAM/ROM/Flash chip drivers | ||
| 390 | # | ||
| 391 | CONFIG_MTD_CFI=y | ||
| 392 | CONFIG_MTD_JEDECPROBE=y | ||
| 393 | CONFIG_MTD_GEN_PROBE=y | ||
| 394 | CONFIG_MTD_CFI_ADV_OPTIONS=y | ||
| 395 | CONFIG_MTD_CFI_NOSWAP=y | ||
| 396 | # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set | ||
| 397 | # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set | ||
| 398 | # CONFIG_MTD_CFI_GEOMETRY is not set | ||
| 399 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 400 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 401 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 402 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 403 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 404 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 405 | CONFIG_MTD_CFI_I1=y | ||
| 406 | CONFIG_MTD_CFI_I2=y | ||
| 407 | # CONFIG_MTD_CFI_I4 is not set | ||
| 408 | # CONFIG_MTD_CFI_I8 is not set | ||
| 409 | # CONFIG_MTD_OTP is not set | ||
| 410 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 411 | CONFIG_MTD_CFI_AMDSTD=y | ||
| 412 | # CONFIG_MTD_CFI_STAA is not set | ||
| 413 | CONFIG_MTD_CFI_UTIL=y | ||
| 414 | # CONFIG_MTD_RAM is not set | ||
| 415 | # CONFIG_MTD_ROM is not set | ||
| 416 | # CONFIG_MTD_ABSENT is not set | ||
| 417 | |||
| 418 | # | ||
| 419 | # Mapping drivers for chip access | ||
| 420 | # | ||
| 421 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 422 | CONFIG_MTD_PHYSMAP=y | ||
| 423 | CONFIG_MTD_PHYSMAP_START=0x8000000 | ||
| 424 | CONFIG_MTD_PHYSMAP_LEN=0 | ||
| 425 | CONFIG_MTD_PHYSMAP_BANKWIDTH=4 | ||
| 426 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 427 | # CONFIG_MTD_IMPA7 is not set | ||
| 428 | # CONFIG_MTD_PLATRAM is not set | ||
| 429 | |||
| 430 | # | ||
| 431 | # Self-contained MTD device drivers | ||
| 432 | # | ||
| 433 | # CONFIG_MTD_SLRAM is not set | ||
| 434 | # CONFIG_MTD_PHRAM is not set | ||
| 435 | # CONFIG_MTD_MTDRAM is not set | ||
| 436 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 437 | |||
| 438 | # | ||
| 439 | # Disk-On-Chip Device Drivers | ||
| 440 | # | ||
| 441 | # CONFIG_MTD_DOC2000 is not set | ||
| 442 | # CONFIG_MTD_DOC2001 is not set | ||
| 443 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 444 | # CONFIG_MTD_NAND is not set | ||
| 445 | # CONFIG_MTD_ONENAND is not set | ||
| 446 | |||
| 447 | # | ||
| 448 | # UBI - Unsorted block images | ||
| 449 | # | ||
| 450 | # CONFIG_MTD_UBI is not set | ||
| 451 | # CONFIG_PARPORT is not set | ||
| 452 | # CONFIG_BLK_DEV is not set | ||
| 453 | # CONFIG_MISC_DEVICES is not set | ||
| 454 | CONFIG_HAVE_IDE=y | ||
| 455 | # CONFIG_IDE is not set | ||
| 456 | |||
| 457 | # | ||
| 458 | # SCSI device support | ||
| 459 | # | ||
| 460 | # CONFIG_RAID_ATTRS is not set | ||
| 461 | # CONFIG_SCSI is not set | ||
| 462 | # CONFIG_SCSI_DMA is not set | ||
| 463 | # CONFIG_SCSI_NETLINK is not set | ||
| 464 | # CONFIG_ATA is not set | ||
| 465 | # CONFIG_MD is not set | ||
| 466 | CONFIG_NETDEVICES=y | ||
| 467 | # CONFIG_DUMMY is not set | ||
| 468 | # CONFIG_BONDING is not set | ||
| 469 | # CONFIG_MACVLAN is not set | ||
| 470 | # CONFIG_EQUALIZER is not set | ||
| 471 | # CONFIG_TUN is not set | ||
| 472 | # CONFIG_VETH is not set | ||
| 473 | # CONFIG_PHYLIB is not set | ||
| 474 | CONFIG_NET_ETHERNET=y | ||
| 475 | CONFIG_MII=y | ||
| 476 | CONFIG_ARM_KS8695_ETHER=y | ||
| 477 | # CONFIG_AX88796 is not set | ||
| 478 | # CONFIG_SMC91X is not set | ||
| 479 | # CONFIG_DM9000 is not set | ||
| 480 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 481 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 482 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 483 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 484 | # CONFIG_B44 is not set | ||
| 485 | # CONFIG_NETDEV_1000 is not set | ||
| 486 | # CONFIG_NETDEV_10000 is not set | ||
| 487 | |||
| 488 | # | ||
| 489 | # Wireless LAN | ||
| 490 | # | ||
| 491 | # CONFIG_WLAN_PRE80211 is not set | ||
| 492 | CONFIG_WLAN_80211=y | ||
| 493 | # CONFIG_LIBERTAS is not set | ||
| 494 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 495 | # CONFIG_HOSTAP is not set | ||
| 496 | # CONFIG_WAN is not set | ||
| 497 | # CONFIG_PPP is not set | ||
| 498 | # CONFIG_SLIP is not set | ||
| 499 | # CONFIG_NETCONSOLE is not set | ||
| 500 | # CONFIG_NETPOLL is not set | ||
| 501 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 502 | # CONFIG_ISDN is not set | ||
| 503 | |||
| 504 | # | ||
| 505 | # Input device support | ||
| 506 | # | ||
| 507 | CONFIG_INPUT=y | ||
| 508 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 509 | # CONFIG_INPUT_POLLDEV is not set | ||
| 510 | |||
| 511 | # | ||
| 512 | # Userland interfaces | ||
| 513 | # | ||
| 514 | CONFIG_INPUT_MOUSEDEV=y | ||
| 515 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 516 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 517 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 518 | # CONFIG_INPUT_JOYDEV is not set | ||
| 519 | # CONFIG_INPUT_EVDEV is not set | ||
| 520 | # CONFIG_INPUT_EVBUG is not set | ||
| 521 | |||
| 522 | # | ||
| 523 | # Input Device Drivers | ||
| 524 | # | ||
| 525 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 526 | # CONFIG_INPUT_MOUSE is not set | ||
| 527 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 528 | # CONFIG_INPUT_TABLET is not set | ||
| 529 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 530 | # CONFIG_INPUT_MISC is not set | ||
| 531 | |||
| 532 | # | ||
| 533 | # Hardware I/O ports | ||
| 534 | # | ||
| 535 | # CONFIG_SERIO is not set | ||
| 536 | # CONFIG_GAMEPORT is not set | ||
| 537 | |||
| 538 | # | ||
| 539 | # Character devices | ||
| 540 | # | ||
| 541 | CONFIG_VT=y | ||
| 542 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 543 | CONFIG_VT_CONSOLE=y | ||
| 544 | CONFIG_HW_CONSOLE=y | ||
| 545 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 546 | CONFIG_DEVKMEM=y | ||
| 547 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 548 | |||
| 549 | # | ||
| 550 | # Serial drivers | ||
| 551 | # | ||
| 552 | # CONFIG_SERIAL_8250 is not set | ||
| 553 | |||
| 554 | # | ||
| 555 | # Non-8250 serial port support | ||
| 556 | # | ||
| 557 | CONFIG_SERIAL_KS8695=y | ||
| 558 | CONFIG_SERIAL_KS8695_CONSOLE=y | ||
| 559 | CONFIG_SERIAL_CORE=y | ||
| 560 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 561 | CONFIG_UNIX98_PTYS=y | ||
| 562 | CONFIG_LEGACY_PTYS=y | ||
| 563 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 564 | # CONFIG_IPMI_HANDLER is not set | ||
| 565 | # CONFIG_HW_RANDOM is not set | ||
| 566 | # CONFIG_NVRAM is not set | ||
| 567 | # CONFIG_R3964 is not set | ||
| 568 | # CONFIG_RAW_DRIVER is not set | ||
| 569 | # CONFIG_TCG_TPM is not set | ||
| 570 | CONFIG_ACS5KCAN=y | ||
| 571 | CONFIG_I2C=y | ||
| 572 | CONFIG_I2C_BOARDINFO=y | ||
| 573 | CONFIG_I2C_CHARDEV=y | ||
| 574 | CONFIG_I2C_HELPER_AUTO=y | ||
| 575 | CONFIG_I2C_ALGOBIT=y | ||
| 576 | |||
| 577 | # | ||
| 578 | # I2C Hardware Bus support | ||
| 579 | # | ||
| 580 | |||
| 581 | # | ||
| 582 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 583 | # | ||
| 584 | CONFIG_I2C_GPIO=y | ||
| 585 | # CONFIG_I2C_OCORES is not set | ||
| 586 | # CONFIG_I2C_SIMTEC is not set | ||
| 587 | |||
| 588 | # | ||
| 589 | # External I2C/SMBus adapter drivers | ||
| 590 | # | ||
| 591 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 592 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 593 | |||
| 594 | # | ||
| 595 | # Other I2C/SMBus bus drivers | ||
| 596 | # | ||
| 597 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 598 | # CONFIG_I2C_STUB is not set | ||
| 599 | |||
| 600 | # | ||
| 601 | # Miscellaneous I2C Chip support | ||
| 602 | # | ||
| 603 | # CONFIG_DS1682 is not set | ||
| 604 | # CONFIG_AT24 is not set | ||
| 605 | # CONFIG_SENSORS_EEPROM is not set | ||
| 606 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 607 | # CONFIG_PCF8575 is not set | ||
| 608 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 609 | # CONFIG_TPS65010 is not set | ||
| 610 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 611 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 612 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 613 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 614 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 615 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 616 | # CONFIG_SPI is not set | ||
| 617 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 618 | CONFIG_GPIOLIB=y | ||
| 619 | # CONFIG_DEBUG_GPIO is not set | ||
| 620 | CONFIG_GPIO_SYSFS=y | ||
| 621 | |||
| 622 | # | ||
| 623 | # I2C GPIO expanders: | ||
| 624 | # | ||
| 625 | # CONFIG_GPIO_MAX732X is not set | ||
| 626 | CONFIG_GPIO_PCA953X=y | ||
| 627 | # CONFIG_GPIO_PCF857X is not set | ||
| 628 | |||
| 629 | # | ||
| 630 | # PCI GPIO expanders: | ||
| 631 | # | ||
| 632 | |||
| 633 | # | ||
| 634 | # SPI GPIO expanders: | ||
| 635 | # | ||
| 636 | # CONFIG_W1 is not set | ||
| 637 | # CONFIG_POWER_SUPPLY is not set | ||
| 638 | # CONFIG_HWMON is not set | ||
| 639 | CONFIG_WATCHDOG=y | ||
| 640 | # CONFIG_WATCHDOG_NOWAYOUT is not set | ||
| 641 | |||
| 642 | # | ||
| 643 | # Watchdog Device Drivers | ||
| 644 | # | ||
| 645 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 646 | CONFIG_KS8695_WATCHDOG=y | ||
| 647 | |||
| 648 | # | ||
| 649 | # Sonics Silicon Backplane | ||
| 650 | # | ||
| 651 | CONFIG_SSB_POSSIBLE=y | ||
| 652 | # CONFIG_SSB is not set | ||
| 653 | |||
| 654 | # | ||
| 655 | # Multifunction device drivers | ||
| 656 | # | ||
| 657 | # CONFIG_MFD_CORE is not set | ||
| 658 | # CONFIG_MFD_SM501 is not set | ||
| 659 | # CONFIG_MFD_ASIC3 is not set | ||
| 660 | # CONFIG_HTC_EGPIO is not set | ||
| 661 | # CONFIG_HTC_PASIC3 is not set | ||
| 662 | # CONFIG_MFD_TMIO is not set | ||
| 663 | # CONFIG_MFD_T7L66XB is not set | ||
| 664 | # CONFIG_MFD_TC6387XB is not set | ||
| 665 | # CONFIG_MFD_TC6393XB is not set | ||
| 666 | |||
| 667 | # | ||
| 668 | # Multimedia devices | ||
| 669 | # | ||
| 670 | |||
| 671 | # | ||
| 672 | # Multimedia core support | ||
| 673 | # | ||
| 674 | # CONFIG_VIDEO_DEV is not set | ||
| 675 | # CONFIG_DVB_CORE is not set | ||
| 676 | # CONFIG_VIDEO_MEDIA is not set | ||
| 677 | |||
| 678 | # | ||
| 679 | # Multimedia drivers | ||
| 680 | # | ||
| 681 | # CONFIG_DAB is not set | ||
| 682 | |||
| 683 | # | ||
| 684 | # Graphics support | ||
| 685 | # | ||
| 686 | # CONFIG_VGASTATE is not set | ||
| 687 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 688 | # CONFIG_FB is not set | ||
| 689 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 690 | |||
| 691 | # | ||
| 692 | # Display device support | ||
| 693 | # | ||
| 694 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 695 | |||
| 696 | # | ||
| 697 | # Console display driver support | ||
| 698 | # | ||
| 699 | # CONFIG_VGA_CONSOLE is not set | ||
| 700 | CONFIG_DUMMY_CONSOLE=y | ||
| 701 | # CONFIG_SOUND is not set | ||
| 702 | # CONFIG_HID_SUPPORT is not set | ||
| 703 | # CONFIG_USB_SUPPORT is not set | ||
| 704 | # CONFIG_MMC is not set | ||
| 705 | # CONFIG_NEW_LEDS is not set | ||
| 706 | CONFIG_RTC_LIB=y | ||
| 707 | CONFIG_RTC_CLASS=y | ||
| 708 | CONFIG_RTC_HCTOSYS=y | ||
| 709 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 710 | # CONFIG_RTC_DEBUG is not set | ||
| 711 | |||
| 712 | # | ||
| 713 | # RTC interfaces | ||
| 714 | # | ||
| 715 | CONFIG_RTC_INTF_SYSFS=y | ||
| 716 | CONFIG_RTC_INTF_PROC=y | ||
| 717 | CONFIG_RTC_INTF_DEV=y | ||
| 718 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 719 | # CONFIG_RTC_DRV_TEST is not set | ||
| 720 | |||
| 721 | # | ||
| 722 | # I2C RTC drivers | ||
| 723 | # | ||
| 724 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 725 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 726 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 727 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 728 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 729 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 730 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 731 | CONFIG_RTC_DRV_PCF8563=y | ||
| 732 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 733 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 734 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 735 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 736 | |||
| 737 | # | ||
| 738 | # SPI RTC drivers | ||
| 739 | # | ||
| 740 | |||
| 741 | # | ||
| 742 | # Platform RTC drivers | ||
| 743 | # | ||
| 744 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 745 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 746 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 747 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 748 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 749 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 750 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 751 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 752 | |||
| 753 | # | ||
| 754 | # on-CPU RTC drivers | ||
| 755 | # | ||
| 756 | # CONFIG_DMADEVICES is not set | ||
| 757 | |||
| 758 | # | ||
| 759 | # Voltage and Current regulators | ||
| 760 | # | ||
| 761 | # CONFIG_REGULATOR is not set | ||
| 762 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set | ||
| 763 | # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set | ||
| 764 | # CONFIG_REGULATOR_BQ24022 is not set | ||
| 765 | # CONFIG_UIO is not set | ||
| 766 | |||
| 767 | # | ||
| 768 | # File systems | ||
| 769 | # | ||
| 770 | # CONFIG_EXT2_FS is not set | ||
| 771 | # CONFIG_EXT3_FS is not set | ||
| 772 | # CONFIG_EXT4DEV_FS is not set | ||
| 773 | # CONFIG_REISERFS_FS is not set | ||
| 774 | # CONFIG_JFS_FS is not set | ||
| 775 | # CONFIG_FS_POSIX_ACL is not set | ||
| 776 | # CONFIG_XFS_FS is not set | ||
| 777 | # CONFIG_OCFS2_FS is not set | ||
| 778 | CONFIG_DNOTIFY=y | ||
| 779 | CONFIG_INOTIFY=y | ||
| 780 | CONFIG_INOTIFY_USER=y | ||
| 781 | # CONFIG_QUOTA is not set | ||
| 782 | # CONFIG_AUTOFS_FS is not set | ||
| 783 | # CONFIG_AUTOFS4_FS is not set | ||
| 784 | # CONFIG_FUSE_FS is not set | ||
| 785 | |||
| 786 | # | ||
| 787 | # CD-ROM/DVD Filesystems | ||
| 788 | # | ||
| 789 | # CONFIG_ISO9660_FS is not set | ||
| 790 | # CONFIG_UDF_FS is not set | ||
| 791 | |||
| 792 | # | ||
| 793 | # DOS/FAT/NT Filesystems | ||
| 794 | # | ||
| 795 | # CONFIG_MSDOS_FS is not set | ||
| 796 | # CONFIG_VFAT_FS is not set | ||
| 797 | # CONFIG_NTFS_FS is not set | ||
| 798 | |||
| 799 | # | ||
| 800 | # Pseudo filesystems | ||
| 801 | # | ||
| 802 | CONFIG_PROC_FS=y | ||
| 803 | CONFIG_PROC_SYSCTL=y | ||
| 804 | CONFIG_SYSFS=y | ||
| 805 | CONFIG_TMPFS=y | ||
| 806 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 807 | # CONFIG_HUGETLB_PAGE is not set | ||
| 808 | # CONFIG_CONFIGFS_FS is not set | ||
| 809 | |||
| 810 | # | ||
| 811 | # Miscellaneous filesystems | ||
| 812 | # | ||
| 813 | # CONFIG_ADFS_FS is not set | ||
| 814 | # CONFIG_AFFS_FS is not set | ||
| 815 | # CONFIG_HFS_FS is not set | ||
| 816 | # CONFIG_HFSPLUS_FS is not set | ||
| 817 | # CONFIG_BEFS_FS is not set | ||
| 818 | # CONFIG_BFS_FS is not set | ||
| 819 | # CONFIG_EFS_FS is not set | ||
| 820 | CONFIG_JFFS2_FS=y | ||
| 821 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 822 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 823 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 824 | CONFIG_JFFS2_SUMMARY=y | ||
| 825 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 826 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 827 | CONFIG_JFFS2_ZLIB=y | ||
| 828 | # CONFIG_JFFS2_LZO is not set | ||
| 829 | CONFIG_JFFS2_RTIME=y | ||
| 830 | CONFIG_JFFS2_RUBIN=y | ||
| 831 | # CONFIG_JFFS2_CMODE_NONE is not set | ||
| 832 | CONFIG_JFFS2_CMODE_PRIORITY=y | ||
| 833 | # CONFIG_JFFS2_CMODE_SIZE is not set | ||
| 834 | # CONFIG_JFFS2_CMODE_FAVOURLZO is not set | ||
| 835 | # CONFIG_CRAMFS is not set | ||
| 836 | CONFIG_SQUASHFS=y | ||
| 837 | # CONFIG_SQUASHFS_EMBEDDED is not set | ||
| 838 | CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 | ||
| 839 | # CONFIG_VXFS_FS is not set | ||
| 840 | # CONFIG_MINIX_FS is not set | ||
| 841 | # CONFIG_OMFS_FS is not set | ||
| 842 | # CONFIG_HPFS_FS is not set | ||
| 843 | # CONFIG_QNX4FS_FS is not set | ||
| 844 | # CONFIG_ROMFS_FS is not set | ||
| 845 | # CONFIG_SYSV_FS is not set | ||
| 846 | # CONFIG_UFS_FS is not set | ||
| 847 | # CONFIG_NETWORK_FILESYSTEMS is not set | ||
| 848 | |||
| 849 | # | ||
| 850 | # Partition Types | ||
| 851 | # | ||
| 852 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 853 | CONFIG_MSDOS_PARTITION=y | ||
| 854 | # CONFIG_NLS is not set | ||
| 855 | # CONFIG_DLM is not set | ||
| 856 | |||
| 857 | # | ||
| 858 | # Kernel hacking | ||
| 859 | # | ||
| 860 | # CONFIG_PRINTK_TIME is not set | ||
| 861 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 862 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 863 | CONFIG_FRAME_WARN=1024 | ||
| 864 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 865 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 866 | # CONFIG_DEBUG_FS is not set | ||
| 867 | # CONFIG_HEADERS_CHECK is not set | ||
| 868 | CONFIG_DEBUG_KERNEL=y | ||
| 869 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 870 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 871 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 872 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 873 | CONFIG_SCHED_DEBUG=y | ||
| 874 | # CONFIG_SCHEDSTATS is not set | ||
| 875 | # CONFIG_TIMER_STATS is not set | ||
| 876 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 877 | # CONFIG_DEBUG_SLAB is not set | ||
| 878 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 879 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 880 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 881 | CONFIG_DEBUG_MUTEXES=y | ||
| 882 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 883 | # CONFIG_PROVE_LOCKING is not set | ||
| 884 | # CONFIG_LOCK_STAT is not set | ||
| 885 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 886 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 887 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 888 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 889 | # CONFIG_DEBUG_INFO is not set | ||
| 890 | # CONFIG_DEBUG_VM is not set | ||
| 891 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 892 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 893 | # CONFIG_DEBUG_LIST is not set | ||
| 894 | # CONFIG_DEBUG_SG is not set | ||
| 895 | CONFIG_FRAME_POINTER=y | ||
| 896 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 897 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 898 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 899 | # CONFIG_FAULT_INJECTION is not set | ||
| 900 | # CONFIG_LATENCYTOP is not set | ||
| 901 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 902 | CONFIG_HAVE_FTRACE=y | ||
| 903 | CONFIG_HAVE_DYNAMIC_FTRACE=y | ||
| 904 | # CONFIG_FTRACE is not set | ||
| 905 | # CONFIG_SCHED_TRACER is not set | ||
| 906 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 907 | # CONFIG_SAMPLES is not set | ||
| 908 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 909 | # CONFIG_KGDB is not set | ||
| 910 | CONFIG_DEBUG_USER=y | ||
| 911 | # CONFIG_DEBUG_ERRORS is not set | ||
| 912 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 913 | # CONFIG_DEBUG_LL is not set | ||
| 914 | |||
| 915 | # | ||
| 916 | # Security options | ||
| 917 | # | ||
| 918 | # CONFIG_KEYS is not set | ||
| 919 | # CONFIG_SECURITY is not set | ||
| 920 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 921 | # CONFIG_CRYPTO is not set | ||
| 922 | |||
| 923 | # | ||
| 924 | # Library routines | ||
| 925 | # | ||
| 926 | CONFIG_BITREVERSE=y | ||
| 927 | # CONFIG_GENERIC_FIND_FIRST_BIT is not set | ||
| 928 | # CONFIG_GENERIC_FIND_NEXT_BIT is not set | ||
| 929 | # CONFIG_CRC_CCITT is not set | ||
| 930 | # CONFIG_CRC16 is not set | ||
| 931 | # CONFIG_CRC_T10DIF is not set | ||
| 932 | # CONFIG_CRC_ITU_T is not set | ||
| 933 | CONFIG_CRC32=y | ||
| 934 | # CONFIG_CRC7 is not set | ||
| 935 | # CONFIG_LIBCRC32C is not set | ||
| 936 | CONFIG_ZLIB_INFLATE=y | ||
| 937 | CONFIG_ZLIB_DEFLATE=y | ||
| 938 | CONFIG_PLIST=y | ||
| 939 | CONFIG_HAS_IOMEM=y | ||
| 940 | CONFIG_HAS_IOPORT=y | ||
| 941 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/assabet_defconfig b/arch/arm/configs/assabet_defconfig index b1cd331aaecf..c66dd399e426 100644 --- a/arch/arm/configs/assabet_defconfig +++ b/arch/arm/configs/assabet_defconfig | |||
| @@ -89,7 +89,6 @@ CONFIG_SA1100_ASSABET=y | |||
| 89 | # CONFIG_SA1100_COLLIE is not set | 89 | # CONFIG_SA1100_COLLIE is not set |
| 90 | # CONFIG_SA1100_H3100 is not set | 90 | # CONFIG_SA1100_H3100 is not set |
| 91 | # CONFIG_SA1100_H3600 is not set | 91 | # CONFIG_SA1100_H3600 is not set |
| 92 | # CONFIG_SA1100_H3800 is not set | ||
| 93 | # CONFIG_SA1100_BADGE4 is not set | 92 | # CONFIG_SA1100_BADGE4 is not set |
| 94 | # CONFIG_SA1100_JORNADA720 is not set | 93 | # CONFIG_SA1100_JORNADA720 is not set |
| 95 | # CONFIG_SA1100_HACKKIT is not set | 94 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig index 80222feb7dad..f264846218a2 100644 --- a/arch/arm/configs/badge4_defconfig +++ b/arch/arm/configs/badge4_defconfig | |||
| @@ -91,7 +91,6 @@ CONFIG_ARCH_SA1100=y | |||
| 91 | # CONFIG_SA1100_COLLIE is not set | 91 | # CONFIG_SA1100_COLLIE is not set |
| 92 | # CONFIG_SA1100_H3100 is not set | 92 | # CONFIG_SA1100_H3100 is not set |
| 93 | # CONFIG_SA1100_H3600 is not set | 93 | # CONFIG_SA1100_H3600 is not set |
| 94 | # CONFIG_SA1100_H3800 is not set | ||
| 95 | CONFIG_SA1100_BADGE4=y | 94 | CONFIG_SA1100_BADGE4=y |
| 96 | # CONFIG_SA1100_JORNADA720 is not set | 95 | # CONFIG_SA1100_JORNADA720 is not set |
| 97 | # CONFIG_SA1100_HACKKIT is not set | 96 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/configs/cerfcube_defconfig b/arch/arm/configs/cerfcube_defconfig index ee130b528bd4..2b4c0668b1b4 100644 --- a/arch/arm/configs/cerfcube_defconfig +++ b/arch/arm/configs/cerfcube_defconfig | |||
| @@ -93,7 +93,6 @@ CONFIG_SA1100_CERF_FLASH_16MB=y | |||
| 93 | # CONFIG_SA1100_COLLIE is not set | 93 | # CONFIG_SA1100_COLLIE is not set |
| 94 | # CONFIG_SA1100_H3100 is not set | 94 | # CONFIG_SA1100_H3100 is not set |
| 95 | # CONFIG_SA1100_H3600 is not set | 95 | # CONFIG_SA1100_H3600 is not set |
| 96 | # CONFIG_SA1100_H3800 is not set | ||
| 97 | # CONFIG_SA1100_BADGE4 is not set | 96 | # CONFIG_SA1100_BADGE4 is not set |
| 98 | # CONFIG_SA1100_JORNADA720 is not set | 97 | # CONFIG_SA1100_JORNADA720 is not set |
| 99 | # CONFIG_SA1100_HACKKIT is not set | 98 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/configs/xm_x2xx_defconfig b/arch/arm/configs/cm_x2xx_defconfig index 1039f366bf8d..797b790cba78 100644 --- a/arch/arm/configs/xm_x2xx_defconfig +++ b/arch/arm/configs/cm_x2xx_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.27-rc8 | 3 | # Linux kernel version: 2.6.29-rc2 |
| 4 | # Sun Oct 5 11:05:36 2008 | 4 | # Sun Feb 1 16:31:36 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| @@ -22,7 +22,6 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set |
| 23 | CONFIG_GENERIC_HWEIGHT=y | 23 | CONFIG_GENERIC_HWEIGHT=y |
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 25 | CONFIG_ARCH_SUPPORTS_AOUT=y | ||
| 26 | CONFIG_ZONE_DMA=y | 25 | CONFIG_ZONE_DMA=y |
| 27 | CONFIG_ARCH_MTD_XIP=y | 26 | CONFIG_ARCH_MTD_XIP=y |
| 28 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | 27 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| @@ -47,12 +46,12 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 47 | CONFIG_IKCONFIG=y | 46 | CONFIG_IKCONFIG=y |
| 48 | CONFIG_IKCONFIG_PROC=y | 47 | CONFIG_IKCONFIG_PROC=y |
| 49 | CONFIG_LOG_BUF_SHIFT=14 | 48 | CONFIG_LOG_BUF_SHIFT=14 |
| 50 | # CONFIG_CGROUPS is not set | ||
| 51 | CONFIG_GROUP_SCHED=y | 49 | CONFIG_GROUP_SCHED=y |
| 52 | CONFIG_FAIR_GROUP_SCHED=y | 50 | CONFIG_FAIR_GROUP_SCHED=y |
| 53 | # CONFIG_RT_GROUP_SCHED is not set | 51 | # CONFIG_RT_GROUP_SCHED is not set |
| 54 | CONFIG_USER_SCHED=y | 52 | CONFIG_USER_SCHED=y |
| 55 | # CONFIG_CGROUP_SCHED is not set | 53 | # CONFIG_CGROUP_SCHED is not set |
| 54 | # CONFIG_CGROUPS is not set | ||
| 56 | CONFIG_SYSFS_DEPRECATED=y | 55 | CONFIG_SYSFS_DEPRECATED=y |
| 57 | CONFIG_SYSFS_DEPRECATED_V2=y | 56 | CONFIG_SYSFS_DEPRECATED_V2=y |
| 58 | # CONFIG_RELAY is not set | 57 | # CONFIG_RELAY is not set |
| @@ -80,27 +79,21 @@ CONFIG_SIGNALFD=y | |||
| 80 | CONFIG_TIMERFD=y | 79 | CONFIG_TIMERFD=y |
| 81 | CONFIG_EVENTFD=y | 80 | CONFIG_EVENTFD=y |
| 82 | CONFIG_SHMEM=y | 81 | CONFIG_SHMEM=y |
| 82 | CONFIG_AIO=y | ||
| 83 | # CONFIG_VM_EVENT_COUNTERS is not set | 83 | # CONFIG_VM_EVENT_COUNTERS is not set |
| 84 | CONFIG_PCI_QUIRKS=y | ||
| 84 | # CONFIG_SLUB_DEBUG is not set | 85 | # CONFIG_SLUB_DEBUG is not set |
| 85 | # CONFIG_SLAB is not set | 86 | # CONFIG_SLAB is not set |
| 86 | CONFIG_SLUB=y | 87 | CONFIG_SLUB=y |
| 87 | # CONFIG_SLOB is not set | 88 | # CONFIG_SLOB is not set |
| 88 | # CONFIG_PROFILING is not set | 89 | # CONFIG_PROFILING is not set |
| 89 | # CONFIG_MARKERS is not set | ||
| 90 | CONFIG_HAVE_OPROFILE=y | 90 | CONFIG_HAVE_OPROFILE=y |
| 91 | # CONFIG_KPROBES is not set | 91 | # CONFIG_KPROBES is not set |
| 92 | # CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set | ||
| 93 | # CONFIG_HAVE_IOREMAP_PROT is not set | ||
| 94 | CONFIG_HAVE_KPROBES=y | 92 | CONFIG_HAVE_KPROBES=y |
| 95 | CONFIG_HAVE_KRETPROBES=y | 93 | CONFIG_HAVE_KRETPROBES=y |
| 96 | # CONFIG_HAVE_ARCH_TRACEHOOK is not set | ||
| 97 | # CONFIG_HAVE_DMA_ATTRS is not set | ||
| 98 | # CONFIG_USE_GENERIC_SMP_HELPERS is not set | ||
| 99 | CONFIG_HAVE_CLK=y | 94 | CONFIG_HAVE_CLK=y |
| 100 | # CONFIG_PROC_PAGE_MONITOR is not set | ||
| 101 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | 95 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y |
| 102 | CONFIG_RT_MUTEXES=y | 96 | CONFIG_RT_MUTEXES=y |
| 103 | # CONFIG_TINY_SHMEM is not set | ||
| 104 | CONFIG_BASE_SMALL=0 | 97 | CONFIG_BASE_SMALL=0 |
| 105 | CONFIG_MODULES=y | 98 | CONFIG_MODULES=y |
| 106 | # CONFIG_MODULE_FORCE_LOAD is not set | 99 | # CONFIG_MODULE_FORCE_LOAD is not set |
| @@ -108,11 +101,9 @@ CONFIG_MODULE_UNLOAD=y | |||
| 108 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 101 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 109 | # CONFIG_MODVERSIONS is not set | 102 | # CONFIG_MODVERSIONS is not set |
| 110 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 103 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 111 | CONFIG_KMOD=y | ||
| 112 | CONFIG_BLOCK=y | 104 | CONFIG_BLOCK=y |
| 113 | # CONFIG_LBD is not set | 105 | # CONFIG_LBD is not set |
| 114 | # CONFIG_BLK_DEV_IO_TRACE is not set | 106 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 115 | # CONFIG_LSF is not set | ||
| 116 | # CONFIG_BLK_DEV_BSG is not set | 107 | # CONFIG_BLK_DEV_BSG is not set |
| 117 | # CONFIG_BLK_DEV_INTEGRITY is not set | 108 | # CONFIG_BLK_DEV_INTEGRITY is not set |
| 118 | 109 | ||
| @@ -129,6 +120,11 @@ CONFIG_DEFAULT_CFQ=y | |||
| 129 | # CONFIG_DEFAULT_NOOP is not set | 120 | # CONFIG_DEFAULT_NOOP is not set |
| 130 | CONFIG_DEFAULT_IOSCHED="cfq" | 121 | CONFIG_DEFAULT_IOSCHED="cfq" |
| 131 | CONFIG_CLASSIC_RCU=y | 122 | CONFIG_CLASSIC_RCU=y |
| 123 | # CONFIG_TREE_RCU is not set | ||
| 124 | # CONFIG_PREEMPT_RCU is not set | ||
| 125 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 126 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 127 | CONFIG_FREEZER=y | ||
| 132 | 128 | ||
| 133 | # | 129 | # |
| 134 | # System Type | 130 | # System Type |
| @@ -138,7 +134,6 @@ CONFIG_CLASSIC_RCU=y | |||
| 138 | # CONFIG_ARCH_REALVIEW is not set | 134 | # CONFIG_ARCH_REALVIEW is not set |
| 139 | # CONFIG_ARCH_VERSATILE is not set | 135 | # CONFIG_ARCH_VERSATILE is not set |
| 140 | # CONFIG_ARCH_AT91 is not set | 136 | # CONFIG_ARCH_AT91 is not set |
| 141 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 142 | # CONFIG_ARCH_CLPS711X is not set | 137 | # CONFIG_ARCH_CLPS711X is not set |
| 143 | # CONFIG_ARCH_EBSA110 is not set | 138 | # CONFIG_ARCH_EBSA110 is not set |
| 144 | # CONFIG_ARCH_EP93XX is not set | 139 | # CONFIG_ARCH_EP93XX is not set |
| @@ -165,17 +160,19 @@ CONFIG_ARCH_PXA=y | |||
| 165 | # CONFIG_ARCH_RPC is not set | 160 | # CONFIG_ARCH_RPC is not set |
| 166 | # CONFIG_ARCH_SA1100 is not set | 161 | # CONFIG_ARCH_SA1100 is not set |
| 167 | # CONFIG_ARCH_S3C2410 is not set | 162 | # CONFIG_ARCH_S3C2410 is not set |
| 163 | # CONFIG_ARCH_S3C64XX is not set | ||
| 168 | # CONFIG_ARCH_SHARK is not set | 164 | # CONFIG_ARCH_SHARK is not set |
| 169 | # CONFIG_ARCH_LH7A40X is not set | 165 | # CONFIG_ARCH_LH7A40X is not set |
| 170 | # CONFIG_ARCH_DAVINCI is not set | 166 | # CONFIG_ARCH_DAVINCI is not set |
| 171 | # CONFIG_ARCH_OMAP is not set | 167 | # CONFIG_ARCH_OMAP is not set |
| 172 | # CONFIG_ARCH_MSM7X00A is not set | 168 | # CONFIG_ARCH_MSM is not set |
| 173 | CONFIG_DMABOUNCE=y | 169 | # CONFIG_ARCH_W90X900 is not set |
| 174 | 170 | ||
| 175 | # | 171 | # |
| 176 | # Intel PXA2xx/PXA3xx Implementations | 172 | # Intel PXA2xx/PXA3xx Implementations |
| 177 | # | 173 | # |
| 178 | # CONFIG_ARCH_GUMSTIX is not set | 174 | # CONFIG_ARCH_GUMSTIX is not set |
| 175 | # CONFIG_MACH_INTELMOTE2 is not set | ||
| 179 | # CONFIG_ARCH_LUBBOCK is not set | 176 | # CONFIG_ARCH_LUBBOCK is not set |
| 180 | # CONFIG_MACH_LOGICPD_PXA270 is not set | 177 | # CONFIG_MACH_LOGICPD_PXA270 is not set |
| 181 | # CONFIG_MACH_MAINSTONE is not set | 178 | # CONFIG_MACH_MAINSTONE is not set |
| @@ -185,7 +182,9 @@ CONFIG_DMABOUNCE=y | |||
| 185 | # CONFIG_ARCH_VIPER is not set | 182 | # CONFIG_ARCH_VIPER is not set |
| 186 | # CONFIG_ARCH_PXA_ESERIES is not set | 183 | # CONFIG_ARCH_PXA_ESERIES is not set |
| 187 | # CONFIG_TRIZEPS_PXA is not set | 184 | # CONFIG_TRIZEPS_PXA is not set |
| 188 | CONFIG_MACH_EM_X270=y | 185 | # CONFIG_MACH_H5000 is not set |
| 186 | # CONFIG_MACH_EM_X270 is not set | ||
| 187 | # CONFIG_MACH_EXEDA is not set | ||
| 189 | # CONFIG_MACH_COLIBRI is not set | 188 | # CONFIG_MACH_COLIBRI is not set |
| 190 | # CONFIG_MACH_ZYLONITE is not set | 189 | # CONFIG_MACH_ZYLONITE is not set |
| 191 | # CONFIG_MACH_LITTLETON is not set | 190 | # CONFIG_MACH_LITTLETON is not set |
| @@ -204,14 +203,6 @@ CONFIG_PXA_SSP=y | |||
| 204 | # CONFIG_PXA_PWM is not set | 203 | # CONFIG_PXA_PWM is not set |
| 205 | 204 | ||
| 206 | # | 205 | # |
| 207 | # Boot options | ||
| 208 | # | ||
| 209 | |||
| 210 | # | ||
| 211 | # Power management | ||
| 212 | # | ||
| 213 | |||
| 214 | # | ||
| 215 | # Processor Type | 206 | # Processor Type |
| 216 | # | 207 | # |
| 217 | CONFIG_CPU_32=y | 208 | CONFIG_CPU_32=y |
| @@ -232,6 +223,8 @@ CONFIG_ARM_THUMB=y | |||
| 232 | # CONFIG_OUTER_CACHE is not set | 223 | # CONFIG_OUTER_CACHE is not set |
| 233 | CONFIG_IWMMXT=y | 224 | CONFIG_IWMMXT=y |
| 234 | CONFIG_XSCALE_PMU=y | 225 | CONFIG_XSCALE_PMU=y |
| 226 | CONFIG_DMABOUNCE=y | ||
| 227 | CONFIG_COMMON_CLKDEV=y | ||
| 235 | 228 | ||
| 236 | # | 229 | # |
| 237 | # Bus support | 230 | # Bus support |
| @@ -242,6 +235,7 @@ CONFIG_PCI_HOST_ITE8152=y | |||
| 242 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 235 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 243 | CONFIG_PCI_LEGACY=y | 236 | CONFIG_PCI_LEGACY=y |
| 244 | # CONFIG_PCI_DEBUG is not set | 237 | # CONFIG_PCI_DEBUG is not set |
| 238 | # CONFIG_PCI_STUB is not set | ||
| 245 | CONFIG_PCCARD=m | 239 | CONFIG_PCCARD=m |
| 246 | # CONFIG_PCMCIA_DEBUG is not set | 240 | # CONFIG_PCMCIA_DEBUG is not set |
| 247 | CONFIG_PCMCIA=m | 241 | CONFIG_PCMCIA=m |
| @@ -287,14 +281,13 @@ CONFIG_FLATMEM_MANUAL=y | |||
| 287 | # CONFIG_SPARSEMEM_MANUAL is not set | 281 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 288 | CONFIG_FLATMEM=y | 282 | CONFIG_FLATMEM=y |
| 289 | CONFIG_FLAT_NODE_MEM_MAP=y | 283 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 290 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 291 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 292 | CONFIG_PAGEFLAGS_EXTENDED=y | 284 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 293 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 285 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 294 | # CONFIG_RESOURCES_64BIT is not set | 286 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 295 | CONFIG_ZONE_DMA_FLAG=1 | 287 | CONFIG_ZONE_DMA_FLAG=1 |
| 296 | CONFIG_BOUNCE=y | 288 | CONFIG_BOUNCE=y |
| 297 | CONFIG_VIRT_TO_BUS=y | 289 | CONFIG_VIRT_TO_BUS=y |
| 290 | CONFIG_UNEVICTABLE_LRU=y | ||
| 298 | CONFIG_ALIGNMENT_TRAP=y | 291 | CONFIG_ALIGNMENT_TRAP=y |
| 299 | 292 | ||
| 300 | # | 293 | # |
| @@ -327,6 +320,8 @@ CONFIG_FPE_NWFPE=y | |||
| 327 | # Userspace binary formats | 320 | # Userspace binary formats |
| 328 | # | 321 | # |
| 329 | CONFIG_BINFMT_ELF=y | 322 | CONFIG_BINFMT_ELF=y |
| 323 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 324 | CONFIG_HAVE_AOUT=y | ||
| 330 | # CONFIG_BINFMT_AOUT is not set | 325 | # CONFIG_BINFMT_AOUT is not set |
| 331 | # CONFIG_BINFMT_MISC is not set | 326 | # CONFIG_BINFMT_MISC is not set |
| 332 | 327 | ||
| @@ -345,6 +340,7 @@ CONFIG_NET=y | |||
| 345 | # | 340 | # |
| 346 | # Networking options | 341 | # Networking options |
| 347 | # | 342 | # |
| 343 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 348 | CONFIG_PACKET=y | 344 | CONFIG_PACKET=y |
| 349 | CONFIG_PACKET_MMAP=y | 345 | CONFIG_PACKET_MMAP=y |
| 350 | CONFIG_UNIX=y | 346 | CONFIG_UNIX=y |
| @@ -389,6 +385,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 389 | # CONFIG_TIPC is not set | 385 | # CONFIG_TIPC is not set |
| 390 | # CONFIG_ATM is not set | 386 | # CONFIG_ATM is not set |
| 391 | # CONFIG_BRIDGE is not set | 387 | # CONFIG_BRIDGE is not set |
| 388 | # CONFIG_NET_DSA is not set | ||
| 392 | # CONFIG_VLAN_8021Q is not set | 389 | # CONFIG_VLAN_8021Q is not set |
| 393 | # CONFIG_DECNET is not set | 390 | # CONFIG_DECNET is not set |
| 394 | # CONFIG_LLC2 is not set | 391 | # CONFIG_LLC2 is not set |
| @@ -399,6 +396,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 399 | # CONFIG_ECONET is not set | 396 | # CONFIG_ECONET is not set |
| 400 | # CONFIG_WAN_ROUTER is not set | 397 | # CONFIG_WAN_ROUTER is not set |
| 401 | # CONFIG_NET_SCHED is not set | 398 | # CONFIG_NET_SCHED is not set |
| 399 | # CONFIG_DCB is not set | ||
| 402 | 400 | ||
| 403 | # | 401 | # |
| 404 | # Network testing | 402 | # Network testing |
| @@ -420,8 +418,6 @@ CONFIG_BT_HIDP=m | |||
| 420 | # | 418 | # |
| 421 | # Bluetooth device drivers | 419 | # Bluetooth device drivers |
| 422 | # | 420 | # |
| 423 | CONFIG_BT_HCIUSB=m | ||
| 424 | CONFIG_BT_HCIUSB_SCO=y | ||
| 425 | # CONFIG_BT_HCIBTUSB is not set | 421 | # CONFIG_BT_HCIBTUSB is not set |
| 426 | # CONFIG_BT_HCIBTSDIO is not set | 422 | # CONFIG_BT_HCIBTSDIO is not set |
| 427 | # CONFIG_BT_HCIUART is not set | 423 | # CONFIG_BT_HCIUART is not set |
| @@ -434,15 +430,15 @@ CONFIG_BT_HCIUSB_SCO=y | |||
| 434 | # CONFIG_BT_HCIBTUART is not set | 430 | # CONFIG_BT_HCIBTUART is not set |
| 435 | # CONFIG_BT_HCIVHCI is not set | 431 | # CONFIG_BT_HCIVHCI is not set |
| 436 | # CONFIG_AF_RXRPC is not set | 432 | # CONFIG_AF_RXRPC is not set |
| 437 | 433 | # CONFIG_PHONET is not set | |
| 438 | # | 434 | CONFIG_WIRELESS=y |
| 439 | # Wireless | ||
| 440 | # | ||
| 441 | # CONFIG_CFG80211 is not set | 435 | # CONFIG_CFG80211 is not set |
| 436 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 442 | CONFIG_WIRELESS_EXT=y | 437 | CONFIG_WIRELESS_EXT=y |
| 443 | CONFIG_WIRELESS_EXT_SYSFS=y | 438 | CONFIG_WIRELESS_EXT_SYSFS=y |
| 439 | CONFIG_LIB80211=m | ||
| 444 | # CONFIG_MAC80211 is not set | 440 | # CONFIG_MAC80211 is not set |
| 445 | # CONFIG_IEEE80211 is not set | 441 | # CONFIG_WIMAX is not set |
| 446 | # CONFIG_RFKILL is not set | 442 | # CONFIG_RFKILL is not set |
| 447 | # CONFIG_NET_9P is not set | 443 | # CONFIG_NET_9P is not set |
| 448 | 444 | ||
| @@ -467,6 +463,7 @@ CONFIG_MTD=y | |||
| 467 | # CONFIG_MTD_DEBUG is not set | 463 | # CONFIG_MTD_DEBUG is not set |
| 468 | # CONFIG_MTD_CONCAT is not set | 464 | # CONFIG_MTD_CONCAT is not set |
| 469 | CONFIG_MTD_PARTITIONS=y | 465 | CONFIG_MTD_PARTITIONS=y |
| 466 | # CONFIG_MTD_TESTS is not set | ||
| 470 | # CONFIG_MTD_REDBOOT_PARTS is not set | 467 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 471 | CONFIG_MTD_CMDLINE_PARTS=y | 468 | CONFIG_MTD_CMDLINE_PARTS=y |
| 472 | # CONFIG_MTD_AFS_PARTS is not set | 469 | # CONFIG_MTD_AFS_PARTS is not set |
| @@ -521,9 +518,7 @@ CONFIG_MTD_CFI_UTIL=y | |||
| 521 | # | 518 | # |
| 522 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | 519 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set |
| 523 | CONFIG_MTD_PHYSMAP=y | 520 | CONFIG_MTD_PHYSMAP=y |
| 524 | CONFIG_MTD_PHYSMAP_START=0x0 | 521 | # CONFIG_MTD_PHYSMAP_COMPAT is not set |
| 525 | CONFIG_MTD_PHYSMAP_LEN=0x400000 | ||
| 526 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | ||
| 527 | CONFIG_MTD_PXA2XX=y | 522 | CONFIG_MTD_PXA2XX=y |
| 528 | # CONFIG_MTD_ARM_INTEGRATOR is not set | 523 | # CONFIG_MTD_ARM_INTEGRATOR is not set |
| 529 | # CONFIG_MTD_IMPA7 is not set | 524 | # CONFIG_MTD_IMPA7 is not set |
| @@ -535,6 +530,8 @@ CONFIG_MTD_PXA2XX=y | |||
| 535 | # Self-contained MTD device drivers | 530 | # Self-contained MTD device drivers |
| 536 | # | 531 | # |
| 537 | # CONFIG_MTD_PMC551 is not set | 532 | # CONFIG_MTD_PMC551 is not set |
| 533 | # CONFIG_MTD_DATAFLASH is not set | ||
| 534 | # CONFIG_MTD_M25P80 is not set | ||
| 538 | # CONFIG_MTD_SLRAM is not set | 535 | # CONFIG_MTD_SLRAM is not set |
| 539 | # CONFIG_MTD_PHRAM is not set | 536 | # CONFIG_MTD_PHRAM is not set |
| 540 | # CONFIG_MTD_MTDRAM is not set | 537 | # CONFIG_MTD_MTDRAM is not set |
| @@ -563,6 +560,12 @@ CONFIG_MTD_NAND_PLATFORM=y | |||
| 563 | # CONFIG_MTD_ONENAND is not set | 560 | # CONFIG_MTD_ONENAND is not set |
| 564 | 561 | ||
| 565 | # | 562 | # |
| 563 | # LPDDR flash memory drivers | ||
| 564 | # | ||
| 565 | # CONFIG_MTD_LPDDR is not set | ||
| 566 | # CONFIG_MTD_QINFO_PROBE is not set | ||
| 567 | |||
| 568 | # | ||
| 566 | # UBI - Unsorted block images | 569 | # UBI - Unsorted block images |
| 567 | # | 570 | # |
| 568 | # CONFIG_MTD_UBI is not set | 571 | # CONFIG_MTD_UBI is not set |
| @@ -642,6 +645,8 @@ CONFIG_SCSI_LOWLEVEL=y | |||
| 642 | # CONFIG_MEGARAID_LEGACY is not set | 645 | # CONFIG_MEGARAID_LEGACY is not set |
| 643 | # CONFIG_MEGARAID_SAS is not set | 646 | # CONFIG_MEGARAID_SAS is not set |
| 644 | # CONFIG_SCSI_HPTIOP is not set | 647 | # CONFIG_SCSI_HPTIOP is not set |
| 648 | # CONFIG_LIBFC is not set | ||
| 649 | # CONFIG_FCOE is not set | ||
| 645 | # CONFIG_SCSI_DMX3191D is not set | 650 | # CONFIG_SCSI_DMX3191D is not set |
| 646 | # CONFIG_SCSI_FUTURE_DOMAIN is not set | 651 | # CONFIG_SCSI_FUTURE_DOMAIN is not set |
| 647 | # CONFIG_SCSI_IPS is not set | 652 | # CONFIG_SCSI_IPS is not set |
| @@ -756,26 +761,30 @@ CONFIG_MII=y | |||
| 756 | CONFIG_DM9000=y | 761 | CONFIG_DM9000=y |
| 757 | CONFIG_DM9000_DEBUGLEVEL=1 | 762 | CONFIG_DM9000_DEBUGLEVEL=1 |
| 758 | # CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set | 763 | # CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set |
| 764 | # CONFIG_ENC28J60 is not set | ||
| 759 | # CONFIG_SMC911X is not set | 765 | # CONFIG_SMC911X is not set |
| 766 | # CONFIG_SMSC911X is not set | ||
| 760 | # CONFIG_NET_TULIP is not set | 767 | # CONFIG_NET_TULIP is not set |
| 761 | # CONFIG_HP100 is not set | 768 | # CONFIG_HP100 is not set |
| 762 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | 769 | # CONFIG_IBM_NEW_EMAC_ZMII is not set |
| 763 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 770 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 764 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 771 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 765 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 772 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 773 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 774 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 775 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 766 | CONFIG_NET_PCI=y | 776 | CONFIG_NET_PCI=y |
| 767 | # CONFIG_PCNET32 is not set | 777 | # CONFIG_PCNET32 is not set |
| 768 | # CONFIG_AMD8111_ETH is not set | 778 | # CONFIG_AMD8111_ETH is not set |
| 769 | # CONFIG_ADAPTEC_STARFIRE is not set | 779 | # CONFIG_ADAPTEC_STARFIRE is not set |
| 770 | # CONFIG_B44 is not set | 780 | # CONFIG_B44 is not set |
| 771 | # CONFIG_FORCEDETH is not set | 781 | # CONFIG_FORCEDETH is not set |
| 772 | # CONFIG_EEPRO100 is not set | ||
| 773 | # CONFIG_E100 is not set | 782 | # CONFIG_E100 is not set |
| 774 | # CONFIG_FEALNX is not set | 783 | # CONFIG_FEALNX is not set |
| 775 | # CONFIG_NATSEMI is not set | 784 | # CONFIG_NATSEMI is not set |
| 776 | # CONFIG_NE2K_PCI is not set | 785 | # CONFIG_NE2K_PCI is not set |
| 777 | # CONFIG_8139CP is not set | 786 | # CONFIG_8139CP is not set |
| 778 | CONFIG_8139TOO=y | 787 | CONFIG_8139TOO=m |
| 779 | # CONFIG_8139TOO_PIO is not set | 788 | # CONFIG_8139TOO_PIO is not set |
| 780 | # CONFIG_8139TOO_TUNE_TWISTER is not set | 789 | # CONFIG_8139TOO_TUNE_TWISTER is not set |
| 781 | # CONFIG_8139TOO_8129 is not set | 790 | # CONFIG_8139TOO_8129 is not set |
| @@ -783,10 +792,12 @@ CONFIG_8139TOO=y | |||
| 783 | # CONFIG_R6040 is not set | 792 | # CONFIG_R6040 is not set |
| 784 | # CONFIG_SIS900 is not set | 793 | # CONFIG_SIS900 is not set |
| 785 | # CONFIG_EPIC100 is not set | 794 | # CONFIG_EPIC100 is not set |
| 795 | # CONFIG_SMSC9420 is not set | ||
| 786 | # CONFIG_SUNDANCE is not set | 796 | # CONFIG_SUNDANCE is not set |
| 787 | # CONFIG_TLAN is not set | 797 | # CONFIG_TLAN is not set |
| 788 | # CONFIG_VIA_RHINE is not set | 798 | # CONFIG_VIA_RHINE is not set |
| 789 | # CONFIG_SC92031 is not set | 799 | # CONFIG_SC92031 is not set |
| 800 | # CONFIG_ATL2 is not set | ||
| 790 | # CONFIG_NETDEV_1000 is not set | 801 | # CONFIG_NETDEV_1000 is not set |
| 791 | # CONFIG_NETDEV_10000 is not set | 802 | # CONFIG_NETDEV_10000 is not set |
| 792 | # CONFIG_TR is not set | 803 | # CONFIG_TR is not set |
| @@ -797,8 +808,6 @@ CONFIG_8139TOO=y | |||
| 797 | # CONFIG_WLAN_PRE80211 is not set | 808 | # CONFIG_WLAN_PRE80211 is not set |
| 798 | CONFIG_WLAN_80211=y | 809 | CONFIG_WLAN_80211=y |
| 799 | # CONFIG_PCMCIA_RAYCS is not set | 810 | # CONFIG_PCMCIA_RAYCS is not set |
| 800 | # CONFIG_IPW2100 is not set | ||
| 801 | # CONFIG_IPW2200 is not set | ||
| 802 | CONFIG_LIBERTAS=m | 811 | CONFIG_LIBERTAS=m |
| 803 | # CONFIG_LIBERTAS_USB is not set | 812 | # CONFIG_LIBERTAS_USB is not set |
| 804 | # CONFIG_LIBERTAS_CS is not set | 813 | # CONFIG_LIBERTAS_CS is not set |
| @@ -811,10 +820,16 @@ CONFIG_LIBERTAS_SDIO=m | |||
| 811 | # CONFIG_PRISM54 is not set | 820 | # CONFIG_PRISM54 is not set |
| 812 | # CONFIG_USB_ZD1201 is not set | 821 | # CONFIG_USB_ZD1201 is not set |
| 813 | # CONFIG_USB_NET_RNDIS_WLAN is not set | 822 | # CONFIG_USB_NET_RNDIS_WLAN is not set |
| 823 | # CONFIG_IPW2100 is not set | ||
| 824 | # CONFIG_IPW2200 is not set | ||
| 814 | # CONFIG_IWLWIFI_LEDS is not set | 825 | # CONFIG_IWLWIFI_LEDS is not set |
| 815 | # CONFIG_HOSTAP is not set | 826 | # CONFIG_HOSTAP is not set |
| 816 | 827 | ||
| 817 | # | 828 | # |
| 829 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 830 | # | ||
| 831 | |||
| 832 | # | ||
| 818 | # USB Network Adapters | 833 | # USB Network Adapters |
| 819 | # | 834 | # |
| 820 | # CONFIG_USB_CATC is not set | 835 | # CONFIG_USB_CATC is not set |
| @@ -879,22 +894,22 @@ CONFIG_KEYBOARD_PXA27x=m | |||
| 879 | # CONFIG_INPUT_JOYSTICK is not set | 894 | # CONFIG_INPUT_JOYSTICK is not set |
| 880 | # CONFIG_INPUT_TABLET is not set | 895 | # CONFIG_INPUT_TABLET is not set |
| 881 | CONFIG_INPUT_TOUCHSCREEN=y | 896 | CONFIG_INPUT_TOUCHSCREEN=y |
| 897 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
| 882 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | 898 | # CONFIG_TOUCHSCREEN_FUJITSU is not set |
| 883 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 899 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| 884 | # CONFIG_TOUCHSCREEN_ELO is not set | 900 | # CONFIG_TOUCHSCREEN_ELO is not set |
| 901 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 885 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | 902 | # CONFIG_TOUCHSCREEN_MTOUCH is not set |
| 886 | # CONFIG_TOUCHSCREEN_INEXIO is not set | 903 | # CONFIG_TOUCHSCREEN_INEXIO is not set |
| 887 | # CONFIG_TOUCHSCREEN_MK712 is not set | 904 | # CONFIG_TOUCHSCREEN_MK712 is not set |
| 888 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | 905 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set |
| 889 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | 906 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set |
| 890 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | 907 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set |
| 891 | CONFIG_TOUCHSCREEN_WM97XX=m | 908 | CONFIG_TOUCHSCREEN_UCB1400=m |
| 892 | # CONFIG_TOUCHSCREEN_WM9705 is not set | 909 | # CONFIG_TOUCHSCREEN_WM97XX is not set |
| 893 | CONFIG_TOUCHSCREEN_WM9712=y | ||
| 894 | # CONFIG_TOUCHSCREEN_WM9713 is not set | ||
| 895 | # CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set | ||
| 896 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | 910 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set |
| 897 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | 911 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set |
| 912 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 898 | # CONFIG_INPUT_MISC is not set | 913 | # CONFIG_INPUT_MISC is not set |
| 899 | 914 | ||
| 900 | # | 915 | # |
| @@ -933,6 +948,7 @@ CONFIG_SERIAL_CORE=y | |||
| 933 | CONFIG_SERIAL_CORE_CONSOLE=y | 948 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 934 | # CONFIG_SERIAL_JSM is not set | 949 | # CONFIG_SERIAL_JSM is not set |
| 935 | CONFIG_UNIX98_PTYS=y | 950 | CONFIG_UNIX98_PTYS=y |
| 951 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 936 | CONFIG_LEGACY_PTYS=y | 952 | CONFIG_LEGACY_PTYS=y |
| 937 | CONFIG_LEGACY_PTY_COUNT=16 | 953 | CONFIG_LEGACY_PTY_COUNT=16 |
| 938 | # CONFIG_IPMI_HANDLER is not set | 954 | # CONFIG_IPMI_HANDLER is not set |
| @@ -1009,26 +1025,45 @@ CONFIG_I2C_PXA=y | |||
| 1009 | # Miscellaneous I2C Chip support | 1025 | # Miscellaneous I2C Chip support |
| 1010 | # | 1026 | # |
| 1011 | # CONFIG_DS1682 is not set | 1027 | # CONFIG_DS1682 is not set |
| 1012 | # CONFIG_EEPROM_AT24 is not set | 1028 | # CONFIG_AT24 is not set |
| 1013 | # CONFIG_EEPROM_LEGACY is not set | 1029 | # CONFIG_SENSORS_EEPROM is not set |
| 1014 | # CONFIG_SENSORS_PCF8574 is not set | 1030 | # CONFIG_SENSORS_PCF8574 is not set |
| 1015 | # CONFIG_PCF8575 is not set | 1031 | # CONFIG_PCF8575 is not set |
| 1016 | # CONFIG_SENSORS_PCA9539 is not set | 1032 | # CONFIG_SENSORS_PCA9539 is not set |
| 1017 | # CONFIG_SENSORS_PCF8591 is not set | 1033 | # CONFIG_SENSORS_PCF8591 is not set |
| 1018 | # CONFIG_TPS65010 is not set | ||
| 1019 | # CONFIG_SENSORS_MAX6875 is not set | 1034 | # CONFIG_SENSORS_MAX6875 is not set |
| 1020 | # CONFIG_SENSORS_TSL2550 is not set | 1035 | # CONFIG_SENSORS_TSL2550 is not set |
| 1021 | # CONFIG_I2C_DEBUG_CORE is not set | 1036 | # CONFIG_I2C_DEBUG_CORE is not set |
| 1022 | # CONFIG_I2C_DEBUG_ALGO is not set | 1037 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 1023 | # CONFIG_I2C_DEBUG_BUS is not set | 1038 | # CONFIG_I2C_DEBUG_BUS is not set |
| 1024 | # CONFIG_I2C_DEBUG_CHIP is not set | 1039 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 1025 | # CONFIG_SPI is not set | 1040 | CONFIG_SPI=y |
| 1041 | # CONFIG_SPI_DEBUG is not set | ||
| 1042 | CONFIG_SPI_MASTER=y | ||
| 1043 | |||
| 1044 | # | ||
| 1045 | # SPI Master Controller Drivers | ||
| 1046 | # | ||
| 1047 | # CONFIG_SPI_BITBANG is not set | ||
| 1048 | # CONFIG_SPI_GPIO is not set | ||
| 1049 | CONFIG_SPI_PXA2XX=m | ||
| 1050 | |||
| 1051 | # | ||
| 1052 | # SPI Protocol Masters | ||
| 1053 | # | ||
| 1054 | # CONFIG_SPI_AT25 is not set | ||
| 1055 | # CONFIG_SPI_SPIDEV is not set | ||
| 1056 | # CONFIG_SPI_TLE62X0 is not set | ||
| 1026 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | 1057 | CONFIG_ARCH_REQUIRE_GPIOLIB=y |
| 1027 | CONFIG_GPIOLIB=y | 1058 | CONFIG_GPIOLIB=y |
| 1028 | # CONFIG_DEBUG_GPIO is not set | 1059 | # CONFIG_DEBUG_GPIO is not set |
| 1029 | # CONFIG_GPIO_SYSFS is not set | 1060 | # CONFIG_GPIO_SYSFS is not set |
| 1030 | 1061 | ||
| 1031 | # | 1062 | # |
| 1063 | # Memory mapped GPIO expanders: | ||
| 1064 | # | ||
| 1065 | |||
| 1066 | # | ||
| 1032 | # I2C GPIO expanders: | 1067 | # I2C GPIO expanders: |
| 1033 | # | 1068 | # |
| 1034 | # CONFIG_GPIO_MAX732X is not set | 1069 | # CONFIG_GPIO_MAX732X is not set |
| @@ -1043,17 +1078,19 @@ CONFIG_GPIOLIB=y | |||
| 1043 | # | 1078 | # |
| 1044 | # SPI GPIO expanders: | 1079 | # SPI GPIO expanders: |
| 1045 | # | 1080 | # |
| 1081 | # CONFIG_GPIO_MAX7301 is not set | ||
| 1082 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 1046 | # CONFIG_W1 is not set | 1083 | # CONFIG_W1 is not set |
| 1047 | # CONFIG_POWER_SUPPLY is not set | 1084 | # CONFIG_POWER_SUPPLY is not set |
| 1048 | # CONFIG_HWMON is not set | 1085 | # CONFIG_HWMON is not set |
| 1049 | # CONFIG_THERMAL is not set | 1086 | # CONFIG_THERMAL is not set |
| 1050 | # CONFIG_THERMAL_HWMON is not set | 1087 | # CONFIG_THERMAL_HWMON is not set |
| 1051 | # CONFIG_WATCHDOG is not set | 1088 | # CONFIG_WATCHDOG is not set |
| 1089 | CONFIG_SSB_POSSIBLE=y | ||
| 1052 | 1090 | ||
| 1053 | # | 1091 | # |
| 1054 | # Sonics Silicon Backplane | 1092 | # Sonics Silicon Backplane |
| 1055 | # | 1093 | # |
| 1056 | CONFIG_SSB_POSSIBLE=y | ||
| 1057 | # CONFIG_SSB is not set | 1094 | # CONFIG_SSB is not set |
| 1058 | 1095 | ||
| 1059 | # | 1096 | # |
| @@ -1064,11 +1101,17 @@ CONFIG_SSB_POSSIBLE=y | |||
| 1064 | # CONFIG_MFD_ASIC3 is not set | 1101 | # CONFIG_MFD_ASIC3 is not set |
| 1065 | # CONFIG_HTC_EGPIO is not set | 1102 | # CONFIG_HTC_EGPIO is not set |
| 1066 | # CONFIG_HTC_PASIC3 is not set | 1103 | # CONFIG_HTC_PASIC3 is not set |
| 1067 | # CONFIG_UCB1400_CORE is not set | 1104 | CONFIG_UCB1400_CORE=m |
| 1105 | # CONFIG_TPS65010 is not set | ||
| 1106 | # CONFIG_TWL4030_CORE is not set | ||
| 1068 | # CONFIG_MFD_TMIO is not set | 1107 | # CONFIG_MFD_TMIO is not set |
| 1069 | # CONFIG_MFD_T7L66XB is not set | 1108 | # CONFIG_MFD_T7L66XB is not set |
| 1070 | # CONFIG_MFD_TC6387XB is not set | 1109 | # CONFIG_MFD_TC6387XB is not set |
| 1071 | # CONFIG_MFD_TC6393XB is not set | 1110 | # CONFIG_MFD_TC6393XB is not set |
| 1111 | # CONFIG_PMIC_DA903X is not set | ||
| 1112 | # CONFIG_MFD_WM8400 is not set | ||
| 1113 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 1114 | # CONFIG_MFD_PCF50633 is not set | ||
| 1072 | 1115 | ||
| 1073 | # | 1116 | # |
| 1074 | # Multimedia devices | 1117 | # Multimedia devices |
| @@ -1077,13 +1120,117 @@ CONFIG_SSB_POSSIBLE=y | |||
| 1077 | # | 1120 | # |
| 1078 | # Multimedia core support | 1121 | # Multimedia core support |
| 1079 | # | 1122 | # |
| 1080 | # CONFIG_VIDEO_DEV is not set | 1123 | CONFIG_VIDEO_DEV=m |
| 1124 | CONFIG_VIDEO_V4L2_COMMON=m | ||
| 1125 | # CONFIG_VIDEO_ALLOW_V4L1 is not set | ||
| 1126 | CONFIG_VIDEO_V4L1_COMPAT=y | ||
| 1081 | # CONFIG_DVB_CORE is not set | 1127 | # CONFIG_DVB_CORE is not set |
| 1082 | # CONFIG_VIDEO_MEDIA is not set | 1128 | CONFIG_VIDEO_MEDIA=m |
| 1083 | 1129 | ||
| 1084 | # | 1130 | # |
| 1085 | # Multimedia drivers | 1131 | # Multimedia drivers |
| 1086 | # | 1132 | # |
| 1133 | # CONFIG_MEDIA_ATTACH is not set | ||
| 1134 | CONFIG_MEDIA_TUNER=m | ||
| 1135 | CONFIG_MEDIA_TUNER_CUSTOMIZE=y | ||
| 1136 | # CONFIG_MEDIA_TUNER_SIMPLE is not set | ||
| 1137 | # CONFIG_MEDIA_TUNER_TDA8290 is not set | ||
| 1138 | # CONFIG_MEDIA_TUNER_TDA827X is not set | ||
| 1139 | # CONFIG_MEDIA_TUNER_TDA18271 is not set | ||
| 1140 | # CONFIG_MEDIA_TUNER_TDA9887 is not set | ||
| 1141 | # CONFIG_MEDIA_TUNER_TEA5761 is not set | ||
| 1142 | # CONFIG_MEDIA_TUNER_TEA5767 is not set | ||
| 1143 | # CONFIG_MEDIA_TUNER_MT20XX is not set | ||
| 1144 | # CONFIG_MEDIA_TUNER_MT2060 is not set | ||
| 1145 | # CONFIG_MEDIA_TUNER_MT2266 is not set | ||
| 1146 | # CONFIG_MEDIA_TUNER_MT2131 is not set | ||
| 1147 | # CONFIG_MEDIA_TUNER_QT1010 is not set | ||
| 1148 | # CONFIG_MEDIA_TUNER_XC2028 is not set | ||
| 1149 | # CONFIG_MEDIA_TUNER_XC5000 is not set | ||
| 1150 | # CONFIG_MEDIA_TUNER_MXL5005S is not set | ||
| 1151 | # CONFIG_MEDIA_TUNER_MXL5007T is not set | ||
| 1152 | CONFIG_VIDEO_V4L2=m | ||
| 1153 | CONFIG_VIDEOBUF_GEN=m | ||
| 1154 | CONFIG_VIDEOBUF_DMA_SG=m | ||
| 1155 | CONFIG_VIDEO_CAPTURE_DRIVERS=y | ||
| 1156 | # CONFIG_VIDEO_ADV_DEBUG is not set | ||
| 1157 | # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set | ||
| 1158 | # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set | ||
| 1159 | |||
| 1160 | # | ||
| 1161 | # Encoders/decoders and other helper chips | ||
| 1162 | # | ||
| 1163 | |||
| 1164 | # | ||
| 1165 | # Audio decoders | ||
| 1166 | # | ||
| 1167 | # CONFIG_VIDEO_TVAUDIO is not set | ||
| 1168 | # CONFIG_VIDEO_TDA7432 is not set | ||
| 1169 | # CONFIG_VIDEO_TDA9840 is not set | ||
| 1170 | # CONFIG_VIDEO_TDA9875 is not set | ||
| 1171 | # CONFIG_VIDEO_TEA6415C is not set | ||
| 1172 | # CONFIG_VIDEO_TEA6420 is not set | ||
| 1173 | # CONFIG_VIDEO_MSP3400 is not set | ||
| 1174 | # CONFIG_VIDEO_CS5345 is not set | ||
| 1175 | # CONFIG_VIDEO_CS53L32A is not set | ||
| 1176 | # CONFIG_VIDEO_M52790 is not set | ||
| 1177 | # CONFIG_VIDEO_TLV320AIC23B is not set | ||
| 1178 | # CONFIG_VIDEO_WM8775 is not set | ||
| 1179 | # CONFIG_VIDEO_WM8739 is not set | ||
| 1180 | # CONFIG_VIDEO_VP27SMPX is not set | ||
| 1181 | |||
| 1182 | # | ||
| 1183 | # Video decoders | ||
| 1184 | # | ||
| 1185 | # CONFIG_VIDEO_OV7670 is not set | ||
| 1186 | # CONFIG_VIDEO_TCM825X is not set | ||
| 1187 | # CONFIG_VIDEO_SAA711X is not set | ||
| 1188 | # CONFIG_VIDEO_SAA717X is not set | ||
| 1189 | # CONFIG_VIDEO_TVP514X is not set | ||
| 1190 | # CONFIG_VIDEO_TVP5150 is not set | ||
| 1191 | |||
| 1192 | # | ||
| 1193 | # Video and audio decoders | ||
| 1194 | # | ||
| 1195 | # CONFIG_VIDEO_CX25840 is not set | ||
| 1196 | |||
| 1197 | # | ||
| 1198 | # MPEG video encoders | ||
| 1199 | # | ||
| 1200 | # CONFIG_VIDEO_CX2341X is not set | ||
| 1201 | |||
| 1202 | # | ||
| 1203 | # Video encoders | ||
| 1204 | # | ||
| 1205 | # CONFIG_VIDEO_SAA7127 is not set | ||
| 1206 | |||
| 1207 | # | ||
| 1208 | # Video improvement chips | ||
| 1209 | # | ||
| 1210 | # CONFIG_VIDEO_UPD64031A is not set | ||
| 1211 | # CONFIG_VIDEO_UPD64083 is not set | ||
| 1212 | # CONFIG_VIDEO_VIVI is not set | ||
| 1213 | # CONFIG_VIDEO_BT848 is not set | ||
| 1214 | # CONFIG_VIDEO_SAA5246A is not set | ||
| 1215 | # CONFIG_VIDEO_SAA5249 is not set | ||
| 1216 | # CONFIG_VIDEO_SAA7134 is not set | ||
| 1217 | # CONFIG_VIDEO_HEXIUM_ORION is not set | ||
| 1218 | # CONFIG_VIDEO_HEXIUM_GEMINI is not set | ||
| 1219 | # CONFIG_VIDEO_CX88 is not set | ||
| 1220 | # CONFIG_VIDEO_IVTV is not set | ||
| 1221 | # CONFIG_VIDEO_CAFE_CCIC is not set | ||
| 1222 | CONFIG_SOC_CAMERA=m | ||
| 1223 | # CONFIG_SOC_CAMERA_MT9M001 is not set | ||
| 1224 | CONFIG_SOC_CAMERA_MT9M111=m | ||
| 1225 | # CONFIG_SOC_CAMERA_MT9T031 is not set | ||
| 1226 | # CONFIG_SOC_CAMERA_MT9V022 is not set | ||
| 1227 | # CONFIG_SOC_CAMERA_TW9910 is not set | ||
| 1228 | # CONFIG_SOC_CAMERA_PLATFORM is not set | ||
| 1229 | # CONFIG_SOC_CAMERA_OV772X is not set | ||
| 1230 | CONFIG_VIDEO_PXA27x=m | ||
| 1231 | # CONFIG_VIDEO_SH_MOBILE_CEU is not set | ||
| 1232 | # CONFIG_V4L_USB_DRIVERS is not set | ||
| 1233 | # CONFIG_RADIO_ADAPTERS is not set | ||
| 1087 | # CONFIG_DAB is not set | 1234 | # CONFIG_DAB is not set |
| 1088 | 1235 | ||
| 1089 | # | 1236 | # |
| @@ -1095,6 +1242,7 @@ CONFIG_SSB_POSSIBLE=y | |||
| 1095 | CONFIG_FB=y | 1242 | CONFIG_FB=y |
| 1096 | # CONFIG_FIRMWARE_EDID is not set | 1243 | # CONFIG_FIRMWARE_EDID is not set |
| 1097 | # CONFIG_FB_DDC is not set | 1244 | # CONFIG_FB_DDC is not set |
| 1245 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 1098 | CONFIG_FB_CFB_FILLRECT=y | 1246 | CONFIG_FB_CFB_FILLRECT=y |
| 1099 | CONFIG_FB_CFB_COPYAREA=y | 1247 | CONFIG_FB_CFB_COPYAREA=y |
| 1100 | CONFIG_FB_CFB_IMAGEBLIT=y | 1248 | CONFIG_FB_CFB_IMAGEBLIT=y |
| @@ -1128,6 +1276,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y | |||
| 1128 | # CONFIG_FB_S3 is not set | 1276 | # CONFIG_FB_S3 is not set |
| 1129 | # CONFIG_FB_SAVAGE is not set | 1277 | # CONFIG_FB_SAVAGE is not set |
| 1130 | # CONFIG_FB_SIS is not set | 1278 | # CONFIG_FB_SIS is not set |
| 1279 | # CONFIG_FB_VIA is not set | ||
| 1131 | # CONFIG_FB_NEOMAGIC is not set | 1280 | # CONFIG_FB_NEOMAGIC is not set |
| 1132 | # CONFIG_FB_KYRO is not set | 1281 | # CONFIG_FB_KYRO is not set |
| 1133 | # CONFIG_FB_3DFX is not set | 1282 | # CONFIG_FB_3DFX is not set |
| @@ -1138,13 +1287,17 @@ CONFIG_FB_CFB_IMAGEBLIT=y | |||
| 1138 | # CONFIG_FB_PM3 is not set | 1287 | # CONFIG_FB_PM3 is not set |
| 1139 | # CONFIG_FB_CARMINE is not set | 1288 | # CONFIG_FB_CARMINE is not set |
| 1140 | CONFIG_FB_PXA=y | 1289 | CONFIG_FB_PXA=y |
| 1290 | # CONFIG_FB_PXA_OVERLAY is not set | ||
| 1141 | # CONFIG_FB_PXA_SMARTPANEL is not set | 1291 | # CONFIG_FB_PXA_SMARTPANEL is not set |
| 1142 | CONFIG_FB_PXA_PARAMETERS=y | 1292 | CONFIG_FB_PXA_PARAMETERS=y |
| 1143 | CONFIG_FB_MBX=m | 1293 | CONFIG_FB_MBX=m |
| 1144 | # CONFIG_FB_W100 is not set | 1294 | # CONFIG_FB_W100 is not set |
| 1145 | # CONFIG_FB_VIRTUAL is not set | 1295 | # CONFIG_FB_VIRTUAL is not set |
| 1146 | # CONFIG_FB_METRONOME is not set | 1296 | # CONFIG_FB_METRONOME is not set |
| 1147 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 1297 | # CONFIG_FB_MB862XX is not set |
| 1298 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 1299 | # CONFIG_LCD_CLASS_DEVICE is not set | ||
| 1300 | # CONFIG_BACKLIGHT_CLASS_DEVICE is not set | ||
| 1148 | 1301 | ||
| 1149 | # | 1302 | # |
| 1150 | # Display device support | 1303 | # Display device support |
| @@ -1167,6 +1320,7 @@ CONFIG_LOGO_LINUX_MONO=y | |||
| 1167 | CONFIG_LOGO_LINUX_VGA16=y | 1320 | CONFIG_LOGO_LINUX_VGA16=y |
| 1168 | CONFIG_LOGO_LINUX_CLUT224=y | 1321 | CONFIG_LOGO_LINUX_CLUT224=y |
| 1169 | CONFIG_SOUND=m | 1322 | CONFIG_SOUND=m |
| 1323 | CONFIG_SOUND_OSS_CORE=y | ||
| 1170 | CONFIG_SND=m | 1324 | CONFIG_SND=m |
| 1171 | CONFIG_SND_TIMER=m | 1325 | CONFIG_SND_TIMER=m |
| 1172 | CONFIG_SND_PCM=m | 1326 | CONFIG_SND_PCM=m |
| @@ -1182,81 +1336,16 @@ CONFIG_SND_VERBOSE_PROCFS=y | |||
| 1182 | # CONFIG_SND_DEBUG is not set | 1336 | # CONFIG_SND_DEBUG is not set |
| 1183 | CONFIG_SND_VMASTER=y | 1337 | CONFIG_SND_VMASTER=y |
| 1184 | CONFIG_SND_AC97_CODEC=m | 1338 | CONFIG_SND_AC97_CODEC=m |
| 1185 | CONFIG_SND_DRIVERS=y | 1339 | # CONFIG_SND_DRIVERS is not set |
| 1186 | # CONFIG_SND_DUMMY is not set | 1340 | # CONFIG_SND_PCI is not set |
| 1187 | # CONFIG_SND_MTPAV is not set | ||
| 1188 | # CONFIG_SND_SERIAL_U16550 is not set | ||
| 1189 | # CONFIG_SND_MPU401 is not set | ||
| 1190 | # CONFIG_SND_AC97_POWER_SAVE is not set | ||
| 1191 | CONFIG_SND_PCI=y | ||
| 1192 | # CONFIG_SND_AD1889 is not set | ||
| 1193 | # CONFIG_SND_ALS300 is not set | ||
| 1194 | # CONFIG_SND_ALI5451 is not set | ||
| 1195 | # CONFIG_SND_ATIIXP is not set | ||
| 1196 | # CONFIG_SND_ATIIXP_MODEM is not set | ||
| 1197 | # CONFIG_SND_AU8810 is not set | ||
| 1198 | # CONFIG_SND_AU8820 is not set | ||
| 1199 | # CONFIG_SND_AU8830 is not set | ||
| 1200 | # CONFIG_SND_AW2 is not set | ||
| 1201 | # CONFIG_SND_AZT3328 is not set | ||
| 1202 | # CONFIG_SND_BT87X is not set | ||
| 1203 | # CONFIG_SND_CA0106 is not set | ||
| 1204 | # CONFIG_SND_CMIPCI is not set | ||
| 1205 | # CONFIG_SND_OXYGEN is not set | ||
| 1206 | # CONFIG_SND_CS4281 is not set | ||
| 1207 | # CONFIG_SND_CS46XX is not set | ||
| 1208 | # CONFIG_SND_DARLA20 is not set | ||
| 1209 | # CONFIG_SND_GINA20 is not set | ||
| 1210 | # CONFIG_SND_LAYLA20 is not set | ||
| 1211 | # CONFIG_SND_DARLA24 is not set | ||
| 1212 | # CONFIG_SND_GINA24 is not set | ||
| 1213 | # CONFIG_SND_LAYLA24 is not set | ||
| 1214 | # CONFIG_SND_MONA is not set | ||
| 1215 | # CONFIG_SND_MIA is not set | ||
| 1216 | # CONFIG_SND_ECHO3G is not set | ||
| 1217 | # CONFIG_SND_INDIGO is not set | ||
| 1218 | # CONFIG_SND_INDIGOIO is not set | ||
| 1219 | # CONFIG_SND_INDIGODJ is not set | ||
| 1220 | # CONFIG_SND_EMU10K1 is not set | ||
| 1221 | # CONFIG_SND_EMU10K1X is not set | ||
| 1222 | # CONFIG_SND_ENS1370 is not set | ||
| 1223 | # CONFIG_SND_ENS1371 is not set | ||
| 1224 | # CONFIG_SND_ES1938 is not set | ||
| 1225 | # CONFIG_SND_ES1968 is not set | ||
| 1226 | # CONFIG_SND_FM801 is not set | ||
| 1227 | # CONFIG_SND_HDA_INTEL is not set | ||
| 1228 | # CONFIG_SND_HDSP is not set | ||
| 1229 | # CONFIG_SND_HDSPM is not set | ||
| 1230 | # CONFIG_SND_HIFIER is not set | ||
| 1231 | # CONFIG_SND_ICE1712 is not set | ||
| 1232 | # CONFIG_SND_ICE1724 is not set | ||
| 1233 | # CONFIG_SND_INTEL8X0 is not set | ||
| 1234 | # CONFIG_SND_INTEL8X0M is not set | ||
| 1235 | # CONFIG_SND_KORG1212 is not set | ||
| 1236 | # CONFIG_SND_MAESTRO3 is not set | ||
| 1237 | # CONFIG_SND_MIXART is not set | ||
| 1238 | # CONFIG_SND_NM256 is not set | ||
| 1239 | # CONFIG_SND_PCXHR is not set | ||
| 1240 | # CONFIG_SND_RIPTIDE is not set | ||
| 1241 | # CONFIG_SND_RME32 is not set | ||
| 1242 | # CONFIG_SND_RME96 is not set | ||
| 1243 | # CONFIG_SND_RME9652 is not set | ||
| 1244 | # CONFIG_SND_SONICVIBES is not set | ||
| 1245 | # CONFIG_SND_TRIDENT is not set | ||
| 1246 | # CONFIG_SND_VIA82XX is not set | ||
| 1247 | # CONFIG_SND_VIA82XX_MODEM is not set | ||
| 1248 | # CONFIG_SND_VIRTUOSO is not set | ||
| 1249 | # CONFIG_SND_VX222 is not set | ||
| 1250 | # CONFIG_SND_YMFPCI is not set | ||
| 1251 | CONFIG_SND_ARM=y | 1341 | CONFIG_SND_ARM=y |
| 1252 | CONFIG_SND_PXA2XX_PCM=m | 1342 | CONFIG_SND_PXA2XX_PCM=m |
| 1343 | CONFIG_SND_PXA2XX_LIB=m | ||
| 1344 | CONFIG_SND_PXA2XX_LIB_AC97=y | ||
| 1253 | CONFIG_SND_PXA2XX_AC97=m | 1345 | CONFIG_SND_PXA2XX_AC97=m |
| 1254 | CONFIG_SND_USB=y | 1346 | # CONFIG_SND_SPI is not set |
| 1255 | # CONFIG_SND_USB_AUDIO is not set | 1347 | # CONFIG_SND_USB is not set |
| 1256 | # CONFIG_SND_USB_CAIAQ is not set | 1348 | # CONFIG_SND_PCMCIA is not set |
| 1257 | CONFIG_SND_PCMCIA=y | ||
| 1258 | # CONFIG_SND_VXPOCKET is not set | ||
| 1259 | # CONFIG_SND_PDAUDIOCF is not set | ||
| 1260 | # CONFIG_SND_SOC is not set | 1349 | # CONFIG_SND_SOC is not set |
| 1261 | # CONFIG_SOUND_PRIME is not set | 1350 | # CONFIG_SOUND_PRIME is not set |
| 1262 | CONFIG_AC97_BUS=m | 1351 | CONFIG_AC97_BUS=m |
| @@ -1269,9 +1358,37 @@ CONFIG_HID_DEBUG=y | |||
| 1269 | # USB Input Devices | 1358 | # USB Input Devices |
| 1270 | # | 1359 | # |
| 1271 | CONFIG_USB_HID=y | 1360 | CONFIG_USB_HID=y |
| 1272 | # CONFIG_USB_HIDINPUT_POWERBOOK is not set | 1361 | # CONFIG_HID_PID is not set |
| 1273 | # CONFIG_HID_FF is not set | ||
| 1274 | # CONFIG_USB_HIDDEV is not set | 1362 | # CONFIG_USB_HIDDEV is not set |
| 1363 | |||
| 1364 | # | ||
| 1365 | # Special HID drivers | ||
| 1366 | # | ||
| 1367 | CONFIG_HID_COMPAT=y | ||
| 1368 | CONFIG_HID_A4TECH=y | ||
| 1369 | CONFIG_HID_APPLE=y | ||
| 1370 | CONFIG_HID_BELKIN=y | ||
| 1371 | CONFIG_HID_CHERRY=y | ||
| 1372 | CONFIG_HID_CHICONY=y | ||
| 1373 | CONFIG_HID_CYPRESS=y | ||
| 1374 | CONFIG_HID_EZKEY=y | ||
| 1375 | CONFIG_HID_GYRATION=y | ||
| 1376 | CONFIG_HID_LOGITECH=y | ||
| 1377 | # CONFIG_LOGITECH_FF is not set | ||
| 1378 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | ||
| 1379 | CONFIG_HID_MICROSOFT=y | ||
| 1380 | CONFIG_HID_MONTEREY=y | ||
| 1381 | # CONFIG_HID_NTRIG is not set | ||
| 1382 | CONFIG_HID_PANTHERLORD=y | ||
| 1383 | # CONFIG_PANTHERLORD_FF is not set | ||
| 1384 | CONFIG_HID_PETALYNX=y | ||
| 1385 | CONFIG_HID_SAMSUNG=y | ||
| 1386 | CONFIG_HID_SONY=y | ||
| 1387 | CONFIG_HID_SUNPLUS=y | ||
| 1388 | # CONFIG_GREENASIA_FF is not set | ||
| 1389 | # CONFIG_HID_TOPSEED is not set | ||
| 1390 | # CONFIG_THRUSTMASTER_FF is not set | ||
| 1391 | # CONFIG_ZEROPLUS_FF is not set | ||
| 1275 | CONFIG_USB_SUPPORT=y | 1392 | CONFIG_USB_SUPPORT=y |
| 1276 | CONFIG_USB_ARCH_HAS_HCD=y | 1393 | CONFIG_USB_ARCH_HAS_HCD=y |
| 1277 | CONFIG_USB_ARCH_HAS_OHCI=y | 1394 | CONFIG_USB_ARCH_HAS_OHCI=y |
| @@ -1291,12 +1408,15 @@ CONFIG_USB_DEVICEFS=y | |||
| 1291 | # CONFIG_USB_OTG_WHITELIST is not set | 1408 | # CONFIG_USB_OTG_WHITELIST is not set |
| 1292 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | 1409 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set |
| 1293 | CONFIG_USB_MON=y | 1410 | CONFIG_USB_MON=y |
| 1411 | # CONFIG_USB_WUSB is not set | ||
| 1412 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1294 | 1413 | ||
| 1295 | # | 1414 | # |
| 1296 | # USB Host Controller Drivers | 1415 | # USB Host Controller Drivers |
| 1297 | # | 1416 | # |
| 1298 | # CONFIG_USB_C67X00_HCD is not set | 1417 | # CONFIG_USB_C67X00_HCD is not set |
| 1299 | # CONFIG_USB_EHCI_HCD is not set | 1418 | # CONFIG_USB_EHCI_HCD is not set |
| 1419 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1300 | # CONFIG_USB_ISP116X_HCD is not set | 1420 | # CONFIG_USB_ISP116X_HCD is not set |
| 1301 | # CONFIG_USB_ISP1760_HCD is not set | 1421 | # CONFIG_USB_ISP1760_HCD is not set |
| 1302 | CONFIG_USB_OHCI_HCD=y | 1422 | CONFIG_USB_OHCI_HCD=y |
| @@ -1306,6 +1426,8 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y | |||
| 1306 | # CONFIG_USB_UHCI_HCD is not set | 1426 | # CONFIG_USB_UHCI_HCD is not set |
| 1307 | # CONFIG_USB_SL811_HCD is not set | 1427 | # CONFIG_USB_SL811_HCD is not set |
| 1308 | # CONFIG_USB_R8A66597_HCD is not set | 1428 | # CONFIG_USB_R8A66597_HCD is not set |
| 1429 | # CONFIG_USB_WHCI_HCD is not set | ||
| 1430 | # CONFIG_USB_HWA_HCD is not set | ||
| 1309 | # CONFIG_USB_MUSB_HDRC is not set | 1431 | # CONFIG_USB_MUSB_HDRC is not set |
| 1310 | 1432 | ||
| 1311 | # | 1433 | # |
| @@ -1314,20 +1436,20 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y | |||
| 1314 | # CONFIG_USB_ACM is not set | 1436 | # CONFIG_USB_ACM is not set |
| 1315 | # CONFIG_USB_PRINTER is not set | 1437 | # CONFIG_USB_PRINTER is not set |
| 1316 | # CONFIG_USB_WDM is not set | 1438 | # CONFIG_USB_WDM is not set |
| 1439 | # CONFIG_USB_TMC is not set | ||
| 1317 | 1440 | ||
| 1318 | # | 1441 | # |
| 1319 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 1442 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; |
| 1320 | # | 1443 | # |
| 1321 | 1444 | ||
| 1322 | # | 1445 | # |
| 1323 | # may also be needed; see USB_STORAGE Help for more information | 1446 | # see USB_STORAGE Help for more information |
| 1324 | # | 1447 | # |
| 1325 | CONFIG_USB_STORAGE=y | 1448 | CONFIG_USB_STORAGE=y |
| 1326 | # CONFIG_USB_STORAGE_DEBUG is not set | 1449 | # CONFIG_USB_STORAGE_DEBUG is not set |
| 1327 | # CONFIG_USB_STORAGE_DATAFAB is not set | 1450 | # CONFIG_USB_STORAGE_DATAFAB is not set |
| 1328 | # CONFIG_USB_STORAGE_FREECOM is not set | 1451 | # CONFIG_USB_STORAGE_FREECOM is not set |
| 1329 | # CONFIG_USB_STORAGE_ISD200 is not set | 1452 | # CONFIG_USB_STORAGE_ISD200 is not set |
| 1330 | # CONFIG_USB_STORAGE_DPCM is not set | ||
| 1331 | # CONFIG_USB_STORAGE_USBAT is not set | 1453 | # CONFIG_USB_STORAGE_USBAT is not set |
| 1332 | # CONFIG_USB_STORAGE_SDDR09 is not set | 1454 | # CONFIG_USB_STORAGE_SDDR09 is not set |
| 1333 | # CONFIG_USB_STORAGE_SDDR55 is not set | 1455 | # CONFIG_USB_STORAGE_SDDR55 is not set |
| @@ -1355,6 +1477,7 @@ CONFIG_USB_STORAGE=y | |||
| 1355 | # CONFIG_USB_EMI62 is not set | 1477 | # CONFIG_USB_EMI62 is not set |
| 1356 | # CONFIG_USB_EMI26 is not set | 1478 | # CONFIG_USB_EMI26 is not set |
| 1357 | # CONFIG_USB_ADUTUX is not set | 1479 | # CONFIG_USB_ADUTUX is not set |
| 1480 | # CONFIG_USB_SEVSEG is not set | ||
| 1358 | # CONFIG_USB_RIO500 is not set | 1481 | # CONFIG_USB_RIO500 is not set |
| 1359 | # CONFIG_USB_LEGOTOWER is not set | 1482 | # CONFIG_USB_LEGOTOWER is not set |
| 1360 | # CONFIG_USB_LCD is not set | 1483 | # CONFIG_USB_LCD is not set |
| @@ -1371,13 +1494,20 @@ CONFIG_USB_STORAGE=y | |||
| 1371 | # CONFIG_USB_IOWARRIOR is not set | 1494 | # CONFIG_USB_IOWARRIOR is not set |
| 1372 | # CONFIG_USB_TEST is not set | 1495 | # CONFIG_USB_TEST is not set |
| 1373 | # CONFIG_USB_ISIGHTFW is not set | 1496 | # CONFIG_USB_ISIGHTFW is not set |
| 1497 | # CONFIG_USB_VST is not set | ||
| 1374 | # CONFIG_USB_GADGET is not set | 1498 | # CONFIG_USB_GADGET is not set |
| 1499 | |||
| 1500 | # | ||
| 1501 | # OTG and related infrastructure | ||
| 1502 | # | ||
| 1503 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1504 | # CONFIG_UWB is not set | ||
| 1375 | CONFIG_MMC=m | 1505 | CONFIG_MMC=m |
| 1376 | # CONFIG_MMC_DEBUG is not set | 1506 | # CONFIG_MMC_DEBUG is not set |
| 1377 | # CONFIG_MMC_UNSAFE_RESUME is not set | 1507 | # CONFIG_MMC_UNSAFE_RESUME is not set |
| 1378 | 1508 | ||
| 1379 | # | 1509 | # |
| 1380 | # MMC/SD Card Drivers | 1510 | # MMC/SD/SDIO Card Drivers |
| 1381 | # | 1511 | # |
| 1382 | CONFIG_MMC_BLOCK=m | 1512 | CONFIG_MMC_BLOCK=m |
| 1383 | CONFIG_MMC_BLOCK_BOUNCE=y | 1513 | CONFIG_MMC_BLOCK_BOUNCE=y |
| @@ -1385,11 +1515,12 @@ CONFIG_MMC_BLOCK_BOUNCE=y | |||
| 1385 | # CONFIG_MMC_TEST is not set | 1515 | # CONFIG_MMC_TEST is not set |
| 1386 | 1516 | ||
| 1387 | # | 1517 | # |
| 1388 | # MMC/SD Host Controller Drivers | 1518 | # MMC/SD/SDIO Host Controller Drivers |
| 1389 | # | 1519 | # |
| 1390 | CONFIG_MMC_PXA=m | 1520 | CONFIG_MMC_PXA=m |
| 1391 | # CONFIG_MMC_SDHCI is not set | 1521 | # CONFIG_MMC_SDHCI is not set |
| 1392 | # CONFIG_MMC_TIFM_SD is not set | 1522 | # CONFIG_MMC_TIFM_SD is not set |
| 1523 | # CONFIG_MMC_SPI is not set | ||
| 1393 | # CONFIG_MMC_SDRICOH_CS is not set | 1524 | # CONFIG_MMC_SDRICOH_CS is not set |
| 1394 | # CONFIG_MEMSTICK is not set | 1525 | # CONFIG_MEMSTICK is not set |
| 1395 | # CONFIG_ACCESSIBILITY is not set | 1526 | # CONFIG_ACCESSIBILITY is not set |
| @@ -1400,8 +1531,7 @@ CONFIG_LEDS_CLASS=y | |||
| 1400 | # LED drivers | 1531 | # LED drivers |
| 1401 | # | 1532 | # |
| 1402 | # CONFIG_LEDS_PCA9532 is not set | 1533 | # CONFIG_LEDS_PCA9532 is not set |
| 1403 | # CONFIG_LEDS_GPIO is not set | 1534 | CONFIG_LEDS_GPIO=m |
| 1404 | CONFIG_LEDS_CM_X270=y | ||
| 1405 | # CONFIG_LEDS_PCA955X is not set | 1535 | # CONFIG_LEDS_PCA955X is not set |
| 1406 | 1536 | ||
| 1407 | # | 1537 | # |
| @@ -1410,6 +1540,7 @@ CONFIG_LEDS_CM_X270=y | |||
| 1410 | CONFIG_LEDS_TRIGGERS=y | 1540 | CONFIG_LEDS_TRIGGERS=y |
| 1411 | # CONFIG_LEDS_TRIGGER_TIMER is not set | 1541 | # CONFIG_LEDS_TRIGGER_TIMER is not set |
| 1412 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 1542 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 1543 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 1413 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | 1544 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set |
| 1414 | CONFIG_RTC_LIB=y | 1545 | CONFIG_RTC_LIB=y |
| 1415 | CONFIG_RTC_CLASS=y | 1546 | CONFIG_RTC_CLASS=y |
| @@ -1441,37 +1572,43 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1441 | # CONFIG_RTC_DRV_M41T80 is not set | 1572 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1442 | # CONFIG_RTC_DRV_S35390A is not set | 1573 | # CONFIG_RTC_DRV_S35390A is not set |
| 1443 | # CONFIG_RTC_DRV_FM3130 is not set | 1574 | # CONFIG_RTC_DRV_FM3130 is not set |
| 1575 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1444 | 1576 | ||
| 1445 | # | 1577 | # |
| 1446 | # SPI RTC drivers | 1578 | # SPI RTC drivers |
| 1447 | # | 1579 | # |
| 1580 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 1581 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1582 | # CONFIG_RTC_DRV_DS1390 is not set | ||
| 1583 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 1584 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1585 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1586 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1448 | 1587 | ||
| 1449 | # | 1588 | # |
| 1450 | # Platform RTC drivers | 1589 | # Platform RTC drivers |
| 1451 | # | 1590 | # |
| 1452 | # CONFIG_RTC_DRV_CMOS is not set | 1591 | # CONFIG_RTC_DRV_CMOS is not set |
| 1592 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1453 | # CONFIG_RTC_DRV_DS1511 is not set | 1593 | # CONFIG_RTC_DRV_DS1511 is not set |
| 1454 | # CONFIG_RTC_DRV_DS1553 is not set | 1594 | # CONFIG_RTC_DRV_DS1553 is not set |
| 1455 | # CONFIG_RTC_DRV_DS1742 is not set | 1595 | # CONFIG_RTC_DRV_DS1742 is not set |
| 1456 | # CONFIG_RTC_DRV_STK17TA8 is not set | 1596 | # CONFIG_RTC_DRV_STK17TA8 is not set |
| 1457 | # CONFIG_RTC_DRV_M48T86 is not set | 1597 | # CONFIG_RTC_DRV_M48T86 is not set |
| 1598 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1458 | # CONFIG_RTC_DRV_M48T59 is not set | 1599 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1600 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1459 | CONFIG_RTC_DRV_V3020=y | 1601 | CONFIG_RTC_DRV_V3020=y |
| 1460 | 1602 | ||
| 1461 | # | 1603 | # |
| 1462 | # on-CPU RTC drivers | 1604 | # on-CPU RTC drivers |
| 1463 | # | 1605 | # |
| 1464 | CONFIG_RTC_DRV_SA1100=y | 1606 | CONFIG_RTC_DRV_SA1100=y |
| 1607 | # CONFIG_RTC_DRV_PXA is not set | ||
| 1465 | # CONFIG_DMADEVICES is not set | 1608 | # CONFIG_DMADEVICES is not set |
| 1466 | |||
| 1467 | # | ||
| 1468 | # Voltage and Current regulators | ||
| 1469 | # | ||
| 1470 | # CONFIG_REGULATOR is not set | 1609 | # CONFIG_REGULATOR is not set |
| 1471 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set | ||
| 1472 | # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set | ||
| 1473 | # CONFIG_REGULATOR_BQ24022 is not set | ||
| 1474 | # CONFIG_UIO is not set | 1610 | # CONFIG_UIO is not set |
| 1611 | # CONFIG_STAGING is not set | ||
| 1475 | 1612 | ||
| 1476 | # | 1613 | # |
| 1477 | # File systems | 1614 | # File systems |
| @@ -1483,14 +1620,16 @@ CONFIG_EXT3_FS=y | |||
| 1483 | CONFIG_EXT3_FS_XATTR=y | 1620 | CONFIG_EXT3_FS_XATTR=y |
| 1484 | # CONFIG_EXT3_FS_POSIX_ACL is not set | 1621 | # CONFIG_EXT3_FS_POSIX_ACL is not set |
| 1485 | # CONFIG_EXT3_FS_SECURITY is not set | 1622 | # CONFIG_EXT3_FS_SECURITY is not set |
| 1486 | # CONFIG_EXT4DEV_FS is not set | 1623 | # CONFIG_EXT4_FS is not set |
| 1487 | CONFIG_JBD=y | 1624 | CONFIG_JBD=y |
| 1488 | CONFIG_FS_MBCACHE=y | 1625 | CONFIG_FS_MBCACHE=y |
| 1489 | # CONFIG_REISERFS_FS is not set | 1626 | # CONFIG_REISERFS_FS is not set |
| 1490 | # CONFIG_JFS_FS is not set | 1627 | # CONFIG_JFS_FS is not set |
| 1491 | # CONFIG_FS_POSIX_ACL is not set | 1628 | # CONFIG_FS_POSIX_ACL is not set |
| 1629 | CONFIG_FILE_LOCKING=y | ||
| 1492 | # CONFIG_XFS_FS is not set | 1630 | # CONFIG_XFS_FS is not set |
| 1493 | # CONFIG_OCFS2_FS is not set | 1631 | # CONFIG_OCFS2_FS is not set |
| 1632 | # CONFIG_BTRFS_FS is not set | ||
| 1494 | CONFIG_DNOTIFY=y | 1633 | CONFIG_DNOTIFY=y |
| 1495 | CONFIG_INOTIFY=y | 1634 | CONFIG_INOTIFY=y |
| 1496 | CONFIG_INOTIFY_USER=y | 1635 | CONFIG_INOTIFY_USER=y |
| @@ -1520,15 +1659,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | |||
| 1520 | # | 1659 | # |
| 1521 | CONFIG_PROC_FS=y | 1660 | CONFIG_PROC_FS=y |
| 1522 | CONFIG_PROC_SYSCTL=y | 1661 | CONFIG_PROC_SYSCTL=y |
| 1662 | # CONFIG_PROC_PAGE_MONITOR is not set | ||
| 1523 | CONFIG_SYSFS=y | 1663 | CONFIG_SYSFS=y |
| 1524 | CONFIG_TMPFS=y | 1664 | CONFIG_TMPFS=y |
| 1525 | # CONFIG_TMPFS_POSIX_ACL is not set | 1665 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 1526 | # CONFIG_HUGETLB_PAGE is not set | 1666 | # CONFIG_HUGETLB_PAGE is not set |
| 1527 | # CONFIG_CONFIGFS_FS is not set | 1667 | # CONFIG_CONFIGFS_FS is not set |
| 1528 | 1668 | CONFIG_MISC_FILESYSTEMS=y | |
| 1529 | # | ||
| 1530 | # Miscellaneous filesystems | ||
| 1531 | # | ||
| 1532 | # CONFIG_ADFS_FS is not set | 1669 | # CONFIG_ADFS_FS is not set |
| 1533 | # CONFIG_AFFS_FS is not set | 1670 | # CONFIG_AFFS_FS is not set |
| 1534 | # CONFIG_HFS_FS is not set | 1671 | # CONFIG_HFS_FS is not set |
| @@ -1548,6 +1685,7 @@ CONFIG_JFFS2_ZLIB=y | |||
| 1548 | CONFIG_JFFS2_RTIME=y | 1685 | CONFIG_JFFS2_RTIME=y |
| 1549 | # CONFIG_JFFS2_RUBIN is not set | 1686 | # CONFIG_JFFS2_RUBIN is not set |
| 1550 | # CONFIG_CRAMFS is not set | 1687 | # CONFIG_CRAMFS is not set |
| 1688 | # CONFIG_SQUASHFS is not set | ||
| 1551 | # CONFIG_VXFS_FS is not set | 1689 | # CONFIG_VXFS_FS is not set |
| 1552 | # CONFIG_MINIX_FS is not set | 1690 | # CONFIG_MINIX_FS is not set |
| 1553 | # CONFIG_OMFS_FS is not set | 1691 | # CONFIG_OMFS_FS is not set |
| @@ -1567,6 +1705,7 @@ CONFIG_LOCKD=y | |||
| 1567 | CONFIG_LOCKD_V4=y | 1705 | CONFIG_LOCKD_V4=y |
| 1568 | CONFIG_NFS_COMMON=y | 1706 | CONFIG_NFS_COMMON=y |
| 1569 | CONFIG_SUNRPC=y | 1707 | CONFIG_SUNRPC=y |
| 1708 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 1570 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 1709 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 1571 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1710 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1572 | # CONFIG_SMB_FS is not set | 1711 | # CONFIG_SMB_FS is not set |
| @@ -1678,19 +1817,29 @@ CONFIG_DEBUG_KERNEL=y | |||
| 1678 | # CONFIG_DEBUG_MEMORY_INIT is not set | 1817 | # CONFIG_DEBUG_MEMORY_INIT is not set |
| 1679 | # CONFIG_DEBUG_LIST is not set | 1818 | # CONFIG_DEBUG_LIST is not set |
| 1680 | # CONFIG_DEBUG_SG is not set | 1819 | # CONFIG_DEBUG_SG is not set |
| 1820 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1681 | CONFIG_FRAME_POINTER=y | 1821 | CONFIG_FRAME_POINTER=y |
| 1682 | # CONFIG_BOOT_PRINTK_DELAY is not set | 1822 | # CONFIG_BOOT_PRINTK_DELAY is not set |
| 1683 | # CONFIG_RCU_TORTURE_TEST is not set | 1823 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1824 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1684 | # CONFIG_BACKTRACE_SELF_TEST is not set | 1825 | # CONFIG_BACKTRACE_SELF_TEST is not set |
| 1826 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1685 | # CONFIG_FAULT_INJECTION is not set | 1827 | # CONFIG_FAULT_INJECTION is not set |
| 1686 | # CONFIG_LATENCYTOP is not set | 1828 | # CONFIG_LATENCYTOP is not set |
| 1687 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 1829 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 1688 | CONFIG_HAVE_FTRACE=y | 1830 | CONFIG_HAVE_FUNCTION_TRACER=y |
| 1689 | CONFIG_HAVE_DYNAMIC_FTRACE=y | 1831 | |
| 1690 | # CONFIG_FTRACE is not set | 1832 | # |
| 1833 | # Tracers | ||
| 1834 | # | ||
| 1835 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1691 | # CONFIG_IRQSOFF_TRACER is not set | 1836 | # CONFIG_IRQSOFF_TRACER is not set |
| 1692 | # CONFIG_SCHED_TRACER is not set | 1837 | # CONFIG_SCHED_TRACER is not set |
| 1693 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | 1838 | # CONFIG_CONTEXT_SWITCH_TRACER is not set |
| 1839 | # CONFIG_BOOT_TRACER is not set | ||
| 1840 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1841 | # CONFIG_STACK_TRACER is not set | ||
| 1842 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1694 | # CONFIG_SAMPLES is not set | 1843 | # CONFIG_SAMPLES is not set |
| 1695 | CONFIG_HAVE_ARCH_KGDB=y | 1844 | CONFIG_HAVE_ARCH_KGDB=y |
| 1696 | # CONFIG_KGDB is not set | 1845 | # CONFIG_KGDB is not set |
| @@ -1705,13 +1854,16 @@ CONFIG_DEBUG_LL=y | |||
| 1705 | # | 1854 | # |
| 1706 | # CONFIG_KEYS is not set | 1855 | # CONFIG_KEYS is not set |
| 1707 | # CONFIG_SECURITY is not set | 1856 | # CONFIG_SECURITY is not set |
| 1857 | # CONFIG_SECURITYFS is not set | ||
| 1708 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | 1858 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1709 | CONFIG_CRYPTO=y | 1859 | CONFIG_CRYPTO=y |
| 1710 | 1860 | ||
| 1711 | # | 1861 | # |
| 1712 | # Crypto core or helper | 1862 | # Crypto core or helper |
| 1713 | # | 1863 | # |
| 1864 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1714 | # CONFIG_CRYPTO_MANAGER is not set | 1865 | # CONFIG_CRYPTO_MANAGER is not set |
| 1866 | # CONFIG_CRYPTO_MANAGER2 is not set | ||
| 1715 | # CONFIG_CRYPTO_GF128MUL is not set | 1867 | # CONFIG_CRYPTO_GF128MUL is not set |
| 1716 | # CONFIG_CRYPTO_NULL is not set | 1868 | # CONFIG_CRYPTO_NULL is not set |
| 1717 | # CONFIG_CRYPTO_CRYPTD is not set | 1869 | # CONFIG_CRYPTO_CRYPTD is not set |
| @@ -1783,14 +1935,18 @@ CONFIG_CRYPTO=y | |||
| 1783 | # | 1935 | # |
| 1784 | # CONFIG_CRYPTO_DEFLATE is not set | 1936 | # CONFIG_CRYPTO_DEFLATE is not set |
| 1785 | # CONFIG_CRYPTO_LZO is not set | 1937 | # CONFIG_CRYPTO_LZO is not set |
| 1938 | |||
| 1939 | # | ||
| 1940 | # Random Number Generation | ||
| 1941 | # | ||
| 1942 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1786 | # CONFIG_CRYPTO_HW is not set | 1943 | # CONFIG_CRYPTO_HW is not set |
| 1787 | 1944 | ||
| 1788 | # | 1945 | # |
| 1789 | # Library routines | 1946 | # Library routines |
| 1790 | # | 1947 | # |
| 1791 | CONFIG_BITREVERSE=y | 1948 | CONFIG_BITREVERSE=y |
| 1792 | # CONFIG_GENERIC_FIND_FIRST_BIT is not set | 1949 | CONFIG_GENERIC_FIND_LAST_BIT=y |
| 1793 | # CONFIG_GENERIC_FIND_NEXT_BIT is not set | ||
| 1794 | CONFIG_CRC_CCITT=m | 1950 | CONFIG_CRC_CCITT=m |
| 1795 | # CONFIG_CRC16 is not set | 1951 | # CONFIG_CRC16 is not set |
| 1796 | # CONFIG_CRC_T10DIF is not set | 1952 | # CONFIG_CRC_T10DIF is not set |
diff --git a/arch/arm/configs/colibri_defconfig b/arch/arm/configs/colibri_pxa270_defconfig index 744086fff414..4cf3bde1c522 100644 --- a/arch/arm/configs/colibri_defconfig +++ b/arch/arm/configs/colibri_pxa270_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.24-rc3 | 3 | # Linux kernel version: 2.6.29-rc8 |
| 4 | # Mon Dec 3 13:36:09 2007 | 4 | # Fri Mar 13 16:18:17 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| @@ -12,6 +12,7 @@ CONFIG_MMU=y | |||
| 12 | # CONFIG_NO_IOPORT is not set | 12 | # CONFIG_NO_IOPORT is not set |
| 13 | CONFIG_GENERIC_HARDIRQS=y | 13 | CONFIG_GENERIC_HARDIRQS=y |
| 14 | CONFIG_STACKTRACE_SUPPORT=y | 14 | CONFIG_STACKTRACE_SUPPORT=y |
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | 16 | CONFIG_LOCKDEP_SUPPORT=y |
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y |
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | 18 | CONFIG_HARDIRQS_SW_RESEND=y |
| @@ -21,8 +22,8 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set |
| 22 | CONFIG_GENERIC_HWEIGHT=y | 23 | CONFIG_GENERIC_HWEIGHT=y |
| 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 24 | CONFIG_ZONE_DMA=y | ||
| 25 | CONFIG_ARCH_MTD_XIP=y | 25 | CONFIG_ARCH_MTD_XIP=y |
| 26 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 26 | CONFIG_VECTORS_BASE=0xffff0000 | 27 | CONFIG_VECTORS_BASE=0xffff0000 |
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 28 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 28 | 29 | ||
| @@ -42,22 +43,30 @@ CONFIG_POSIX_MQUEUE=y | |||
| 42 | CONFIG_BSD_PROCESS_ACCT=y | 43 | CONFIG_BSD_PROCESS_ACCT=y |
| 43 | CONFIG_BSD_PROCESS_ACCT_V3=y | 44 | CONFIG_BSD_PROCESS_ACCT_V3=y |
| 44 | # CONFIG_TASKSTATS is not set | 45 | # CONFIG_TASKSTATS is not set |
| 45 | # CONFIG_USER_NS is not set | ||
| 46 | # CONFIG_PID_NS is not set | ||
| 47 | # CONFIG_AUDIT is not set | 46 | # CONFIG_AUDIT is not set |
| 47 | |||
| 48 | # | ||
| 49 | # RCU Subsystem | ||
| 50 | # | ||
| 51 | CONFIG_CLASSIC_RCU=y | ||
| 52 | # CONFIG_TREE_RCU is not set | ||
| 53 | # CONFIG_PREEMPT_RCU is not set | ||
| 54 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 55 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 48 | CONFIG_IKCONFIG=y | 56 | CONFIG_IKCONFIG=y |
| 49 | CONFIG_IKCONFIG_PROC=y | 57 | CONFIG_IKCONFIG_PROC=y |
| 50 | CONFIG_LOG_BUF_SHIFT=14 | 58 | CONFIG_LOG_BUF_SHIFT=14 |
| 59 | # CONFIG_GROUP_SCHED is not set | ||
| 51 | # CONFIG_CGROUPS is not set | 60 | # CONFIG_CGROUPS is not set |
| 52 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 53 | CONFIG_FAIR_USER_SCHED=y | ||
| 54 | # CONFIG_FAIR_CGROUP_SCHED is not set | ||
| 55 | CONFIG_SYSFS_DEPRECATED=y | 61 | CONFIG_SYSFS_DEPRECATED=y |
| 62 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 56 | # CONFIG_RELAY is not set | 63 | # CONFIG_RELAY is not set |
| 64 | # CONFIG_NAMESPACES is not set | ||
| 57 | CONFIG_BLK_DEV_INITRD=y | 65 | CONFIG_BLK_DEV_INITRD=y |
| 58 | CONFIG_INITRAMFS_SOURCE="" | 66 | CONFIG_INITRAMFS_SOURCE="" |
| 59 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 67 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 60 | CONFIG_SYSCTL=y | 68 | CONFIG_SYSCTL=y |
| 69 | CONFIG_ANON_INODES=y | ||
| 61 | CONFIG_EMBEDDED=y | 70 | CONFIG_EMBEDDED=y |
| 62 | CONFIG_UID16=y | 71 | CONFIG_UID16=y |
| 63 | CONFIG_SYSCTL_SYSCALL=y | 72 | CONFIG_SYSCTL_SYSCALL=y |
| @@ -70,29 +79,38 @@ CONFIG_BUG=y | |||
| 70 | CONFIG_ELF_CORE=y | 79 | CONFIG_ELF_CORE=y |
| 71 | CONFIG_BASE_FULL=y | 80 | CONFIG_BASE_FULL=y |
| 72 | CONFIG_FUTEX=y | 81 | CONFIG_FUTEX=y |
| 73 | CONFIG_ANON_INODES=y | ||
| 74 | CONFIG_EPOLL=y | 82 | CONFIG_EPOLL=y |
| 75 | CONFIG_SIGNALFD=y | 83 | CONFIG_SIGNALFD=y |
| 84 | CONFIG_TIMERFD=y | ||
| 76 | CONFIG_EVENTFD=y | 85 | CONFIG_EVENTFD=y |
| 77 | CONFIG_SHMEM=y | 86 | CONFIG_SHMEM=y |
| 87 | CONFIG_AIO=y | ||
| 78 | CONFIG_VM_EVENT_COUNTERS=y | 88 | CONFIG_VM_EVENT_COUNTERS=y |
| 89 | CONFIG_COMPAT_BRK=y | ||
| 79 | CONFIG_SLAB=y | 90 | CONFIG_SLAB=y |
| 80 | # CONFIG_SLUB is not set | 91 | # CONFIG_SLUB is not set |
| 81 | # CONFIG_SLOB is not set | 92 | # CONFIG_SLOB is not set |
| 93 | # CONFIG_PROFILING is not set | ||
| 94 | CONFIG_HAVE_OPROFILE=y | ||
| 95 | # CONFIG_KPROBES is not set | ||
| 96 | CONFIG_HAVE_KPROBES=y | ||
| 97 | CONFIG_HAVE_KRETPROBES=y | ||
| 98 | CONFIG_HAVE_CLK=y | ||
| 99 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 100 | CONFIG_SLABINFO=y | ||
| 82 | CONFIG_RT_MUTEXES=y | 101 | CONFIG_RT_MUTEXES=y |
| 83 | # CONFIG_TINY_SHMEM is not set | ||
| 84 | CONFIG_BASE_SMALL=0 | 102 | CONFIG_BASE_SMALL=0 |
| 85 | CONFIG_MODULES=y | 103 | CONFIG_MODULES=y |
| 104 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 86 | CONFIG_MODULE_UNLOAD=y | 105 | CONFIG_MODULE_UNLOAD=y |
| 87 | CONFIG_MODULE_FORCE_UNLOAD=y | 106 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 88 | CONFIG_MODVERSIONS=y | 107 | CONFIG_MODVERSIONS=y |
| 89 | CONFIG_MODULE_SRCVERSION_ALL=y | 108 | CONFIG_MODULE_SRCVERSION_ALL=y |
| 90 | CONFIG_KMOD=y | ||
| 91 | CONFIG_BLOCK=y | 109 | CONFIG_BLOCK=y |
| 92 | CONFIG_LBD=y | 110 | CONFIG_LBD=y |
| 93 | # CONFIG_BLK_DEV_IO_TRACE is not set | 111 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 94 | CONFIG_LSF=y | ||
| 95 | # CONFIG_BLK_DEV_BSG is not set | 112 | # CONFIG_BLK_DEV_BSG is not set |
| 113 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 96 | 114 | ||
| 97 | # | 115 | # |
| 98 | # IO Schedulers | 116 | # IO Schedulers |
| @@ -106,6 +124,7 @@ CONFIG_DEFAULT_AS=y | |||
| 106 | # CONFIG_DEFAULT_CFQ is not set | 124 | # CONFIG_DEFAULT_CFQ is not set |
| 107 | # CONFIG_DEFAULT_NOOP is not set | 125 | # CONFIG_DEFAULT_NOOP is not set |
| 108 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 126 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 127 | CONFIG_FREEZER=y | ||
| 109 | 128 | ||
| 110 | # | 129 | # |
| 111 | # System Type | 130 | # System Type |
| @@ -115,9 +134,7 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" | |||
| 115 | # CONFIG_ARCH_REALVIEW is not set | 134 | # CONFIG_ARCH_REALVIEW is not set |
| 116 | # CONFIG_ARCH_VERSATILE is not set | 135 | # CONFIG_ARCH_VERSATILE is not set |
| 117 | # CONFIG_ARCH_AT91 is not set | 136 | # CONFIG_ARCH_AT91 is not set |
| 118 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 119 | # CONFIG_ARCH_CLPS711X is not set | 137 | # CONFIG_ARCH_CLPS711X is not set |
| 120 | # CONFIG_ARCH_CO285 is not set | ||
| 121 | # CONFIG_ARCH_EBSA110 is not set | 138 | # CONFIG_ARCH_EBSA110 is not set |
| 122 | # CONFIG_ARCH_EP93XX is not set | 139 | # CONFIG_ARCH_EP93XX is not set |
| 123 | # CONFIG_ARCH_FOOTBRIDGE is not set | 140 | # CONFIG_ARCH_FOOTBRIDGE is not set |
| @@ -131,41 +148,58 @@ CONFIG_DEFAULT_IOSCHED="anticipatory" | |||
| 131 | # CONFIG_ARCH_IXP2000 is not set | 148 | # CONFIG_ARCH_IXP2000 is not set |
| 132 | # CONFIG_ARCH_IXP4XX is not set | 149 | # CONFIG_ARCH_IXP4XX is not set |
| 133 | # CONFIG_ARCH_L7200 is not set | 150 | # CONFIG_ARCH_L7200 is not set |
| 151 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 134 | # CONFIG_ARCH_KS8695 is not set | 152 | # CONFIG_ARCH_KS8695 is not set |
| 135 | # CONFIG_ARCH_NS9XXX is not set | 153 | # CONFIG_ARCH_NS9XXX is not set |
| 154 | # CONFIG_ARCH_LOKI is not set | ||
| 155 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 136 | # CONFIG_ARCH_MXC is not set | 156 | # CONFIG_ARCH_MXC is not set |
| 157 | # CONFIG_ARCH_ORION5X is not set | ||
| 137 | # CONFIG_ARCH_PNX4008 is not set | 158 | # CONFIG_ARCH_PNX4008 is not set |
| 138 | CONFIG_ARCH_PXA=y | 159 | CONFIG_ARCH_PXA=y |
| 139 | # CONFIG_ARCH_RPC is not set | 160 | # CONFIG_ARCH_RPC is not set |
| 140 | # CONFIG_ARCH_SA1100 is not set | 161 | # CONFIG_ARCH_SA1100 is not set |
| 141 | # CONFIG_ARCH_S3C2410 is not set | 162 | # CONFIG_ARCH_S3C2410 is not set |
| 163 | # CONFIG_ARCH_S3C64XX is not set | ||
| 142 | # CONFIG_ARCH_SHARK is not set | 164 | # CONFIG_ARCH_SHARK is not set |
| 143 | # CONFIG_ARCH_LH7A40X is not set | 165 | # CONFIG_ARCH_LH7A40X is not set |
| 144 | # CONFIG_ARCH_DAVINCI is not set | 166 | # CONFIG_ARCH_DAVINCI is not set |
| 145 | # CONFIG_ARCH_OMAP is not set | 167 | # CONFIG_ARCH_OMAP is not set |
| 168 | # CONFIG_ARCH_MSM is not set | ||
| 169 | # CONFIG_ARCH_W90X900 is not set | ||
| 146 | 170 | ||
| 147 | # | 171 | # |
| 148 | # Intel PXA2xx/PXA3xx Implementations | 172 | # Intel PXA2xx/PXA3xx Implementations |
| 149 | # | 173 | # |
| 174 | # CONFIG_ARCH_GUMSTIX is not set | ||
| 175 | # CONFIG_MACH_INTELMOTE2 is not set | ||
| 150 | # CONFIG_ARCH_LUBBOCK is not set | 176 | # CONFIG_ARCH_LUBBOCK is not set |
| 151 | # CONFIG_MACH_LOGICPD_PXA270 is not set | 177 | # CONFIG_MACH_LOGICPD_PXA270 is not set |
| 152 | # CONFIG_MACH_MAINSTONE is not set | 178 | # CONFIG_MACH_MAINSTONE is not set |
| 179 | # CONFIG_MACH_MP900C is not set | ||
| 153 | # CONFIG_ARCH_PXA_IDP is not set | 180 | # CONFIG_ARCH_PXA_IDP is not set |
| 154 | # CONFIG_PXA_SHARPSL is not set | 181 | # CONFIG_PXA_SHARPSL is not set |
| 155 | # CONFIG_MACH_TRIZEPS4 is not set | 182 | # CONFIG_ARCH_VIPER is not set |
| 183 | # CONFIG_ARCH_PXA_ESERIES is not set | ||
| 184 | # CONFIG_TRIZEPS_PXA is not set | ||
| 185 | # CONFIG_MACH_H5000 is not set | ||
| 156 | # CONFIG_MACH_EM_X270 is not set | 186 | # CONFIG_MACH_EM_X270 is not set |
| 157 | CONFIG_MACH_COLIBRI=y | 187 | CONFIG_MACH_COLIBRI=y |
| 188 | # CONFIG_MACH_COLIBRI300 is not set | ||
| 158 | # CONFIG_MACH_ZYLONITE is not set | 189 | # CONFIG_MACH_ZYLONITE is not set |
| 190 | # CONFIG_MACH_LITTLETON is not set | ||
| 191 | # CONFIG_MACH_RAUMFELD_PROTO is not set | ||
| 192 | # CONFIG_MACH_TAVOREVB is not set | ||
| 193 | # CONFIG_MACH_SAAR is not set | ||
| 159 | # CONFIG_MACH_ARMCORE is not set | 194 | # CONFIG_MACH_ARMCORE is not set |
| 195 | # CONFIG_MACH_CM_X300 is not set | ||
| 196 | # CONFIG_MACH_MAGICIAN is not set | ||
| 197 | # CONFIG_MACH_MIOA701 is not set | ||
| 198 | # CONFIG_MACH_PCM027 is not set | ||
| 199 | # CONFIG_ARCH_PXA_PALM is not set | ||
| 200 | # CONFIG_PXA_EZX is not set | ||
| 160 | CONFIG_PXA27x=y | 201 | CONFIG_PXA27x=y |
| 161 | 202 | # CONFIG_PXA_PWM is not set | |
| 162 | # | ||
| 163 | # Boot options | ||
| 164 | # | ||
| 165 | |||
| 166 | # | ||
| 167 | # Power management | ||
| 168 | # | ||
| 169 | 203 | ||
| 170 | # | 204 | # |
| 171 | # Processor Type | 205 | # Processor Type |
| @@ -174,6 +208,7 @@ CONFIG_CPU_32=y | |||
| 174 | CONFIG_CPU_XSCALE=y | 208 | CONFIG_CPU_XSCALE=y |
| 175 | CONFIG_CPU_32v5=y | 209 | CONFIG_CPU_32v5=y |
| 176 | CONFIG_CPU_ABRT_EV5T=y | 210 | CONFIG_CPU_ABRT_EV5T=y |
| 211 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 177 | CONFIG_CPU_CACHE_VIVT=y | 212 | CONFIG_CPU_CACHE_VIVT=y |
| 178 | CONFIG_CPU_TLB_V4WBI=y | 213 | CONFIG_CPU_TLB_V4WBI=y |
| 179 | CONFIG_CPU_CP15=y | 214 | CONFIG_CPU_CP15=y |
| @@ -187,6 +222,7 @@ CONFIG_ARM_THUMB=y | |||
| 187 | # CONFIG_OUTER_CACHE is not set | 222 | # CONFIG_OUTER_CACHE is not set |
| 188 | CONFIG_IWMMXT=y | 223 | CONFIG_IWMMXT=y |
| 189 | CONFIG_XSCALE_PMU=y | 224 | CONFIG_XSCALE_PMU=y |
| 225 | CONFIG_COMMON_CLKDEV=y | ||
| 190 | 226 | ||
| 191 | # | 227 | # |
| 192 | # Bus support | 228 | # Bus support |
| @@ -198,28 +234,33 @@ CONFIG_XSCALE_PMU=y | |||
| 198 | # | 234 | # |
| 199 | # Kernel Features | 235 | # Kernel Features |
| 200 | # | 236 | # |
| 201 | # CONFIG_TICK_ONESHOT is not set | 237 | CONFIG_TICK_ONESHOT=y |
| 202 | # CONFIG_NO_HZ is not set | 238 | # CONFIG_NO_HZ is not set |
| 203 | # CONFIG_HIGH_RES_TIMERS is not set | 239 | # CONFIG_HIGH_RES_TIMERS is not set |
| 204 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 240 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| 241 | CONFIG_VMSPLIT_3G=y | ||
| 242 | # CONFIG_VMSPLIT_2G is not set | ||
| 243 | # CONFIG_VMSPLIT_1G is not set | ||
| 244 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 205 | CONFIG_PREEMPT=y | 245 | CONFIG_PREEMPT=y |
| 206 | CONFIG_HZ=100 | 246 | CONFIG_HZ=100 |
| 207 | CONFIG_AEABI=y | 247 | CONFIG_AEABI=y |
| 208 | CONFIG_OABI_COMPAT=y | 248 | CONFIG_OABI_COMPAT=y |
| 209 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | 249 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y |
| 250 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 251 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 210 | CONFIG_SELECT_MEMORY_MODEL=y | 252 | CONFIG_SELECT_MEMORY_MODEL=y |
| 211 | CONFIG_FLATMEM_MANUAL=y | 253 | CONFIG_FLATMEM_MANUAL=y |
| 212 | # CONFIG_DISCONTIGMEM_MANUAL is not set | 254 | # CONFIG_DISCONTIGMEM_MANUAL is not set |
| 213 | # CONFIG_SPARSEMEM_MANUAL is not set | 255 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 214 | CONFIG_FLATMEM=y | 256 | CONFIG_FLATMEM=y |
| 215 | CONFIG_FLAT_NODE_MEM_MAP=y | 257 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 216 | # CONFIG_SPARSEMEM_STATIC is not set | 258 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 217 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 218 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 259 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 219 | # CONFIG_RESOURCES_64BIT is not set | 260 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 220 | CONFIG_ZONE_DMA_FLAG=1 | 261 | CONFIG_ZONE_DMA_FLAG=0 |
| 221 | CONFIG_BOUNCE=y | ||
| 222 | CONFIG_VIRT_TO_BUS=y | 262 | CONFIG_VIRT_TO_BUS=y |
| 263 | CONFIG_UNEVICTABLE_LRU=y | ||
| 223 | CONFIG_ALIGNMENT_TRAP=y | 264 | CONFIG_ALIGNMENT_TRAP=y |
| 224 | 265 | ||
| 225 | # | 266 | # |
| @@ -232,6 +273,12 @@ CONFIG_CMDLINE="" | |||
| 232 | # CONFIG_KEXEC is not set | 273 | # CONFIG_KEXEC is not set |
| 233 | 274 | ||
| 234 | # | 275 | # |
| 276 | # CPU Power Management | ||
| 277 | # | ||
| 278 | # CONFIG_CPU_FREQ is not set | ||
| 279 | # CONFIG_CPU_IDLE is not set | ||
| 280 | |||
| 281 | # | ||
| 235 | # Floating point emulation | 282 | # Floating point emulation |
| 236 | # | 283 | # |
| 237 | 284 | ||
| @@ -246,6 +293,8 @@ CONFIG_FPE_NWFPE=y | |||
| 246 | # Userspace binary formats | 293 | # Userspace binary formats |
| 247 | # | 294 | # |
| 248 | CONFIG_BINFMT_ELF=y | 295 | CONFIG_BINFMT_ELF=y |
| 296 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 297 | CONFIG_HAVE_AOUT=y | ||
| 249 | # CONFIG_BINFMT_AOUT is not set | 298 | # CONFIG_BINFMT_AOUT is not set |
| 250 | # CONFIG_BINFMT_MISC is not set | 299 | # CONFIG_BINFMT_MISC is not set |
| 251 | 300 | ||
| @@ -253,21 +302,18 @@ CONFIG_BINFMT_ELF=y | |||
| 253 | # Power management options | 302 | # Power management options |
| 254 | # | 303 | # |
| 255 | CONFIG_PM=y | 304 | CONFIG_PM=y |
| 256 | # CONFIG_PM_LEGACY is not set | ||
| 257 | # CONFIG_PM_DEBUG is not set | 305 | # CONFIG_PM_DEBUG is not set |
| 258 | CONFIG_PM_SLEEP=y | 306 | CONFIG_PM_SLEEP=y |
| 259 | CONFIG_SUSPEND_UP_POSSIBLE=y | ||
| 260 | CONFIG_SUSPEND=y | 307 | CONFIG_SUSPEND=y |
| 308 | CONFIG_SUSPEND_FREEZER=y | ||
| 261 | # CONFIG_APM_EMULATION is not set | 309 | # CONFIG_APM_EMULATION is not set |
| 262 | 310 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | |
| 263 | # | ||
| 264 | # Networking | ||
| 265 | # | ||
| 266 | CONFIG_NET=y | 311 | CONFIG_NET=y |
| 267 | 312 | ||
| 268 | # | 313 | # |
| 269 | # Networking options | 314 | # Networking options |
| 270 | # | 315 | # |
| 316 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 271 | CONFIG_PACKET=y | 317 | CONFIG_PACKET=y |
| 272 | CONFIG_PACKET_MMAP=y | 318 | CONFIG_PACKET_MMAP=y |
| 273 | CONFIG_UNIX=y | 319 | CONFIG_UNIX=y |
| @@ -275,6 +321,7 @@ CONFIG_XFRM=y | |||
| 275 | CONFIG_XFRM_USER=m | 321 | CONFIG_XFRM_USER=m |
| 276 | # CONFIG_XFRM_SUB_POLICY is not set | 322 | # CONFIG_XFRM_SUB_POLICY is not set |
| 277 | # CONFIG_XFRM_MIGRATE is not set | 323 | # CONFIG_XFRM_MIGRATE is not set |
| 324 | # CONFIG_XFRM_STATISTICS is not set | ||
| 278 | CONFIG_NET_KEY=y | 325 | CONFIG_NET_KEY=y |
| 279 | # CONFIG_NET_KEY_MIGRATE is not set | 326 | # CONFIG_NET_KEY_MIGRATE is not set |
| 280 | CONFIG_INET=y | 327 | CONFIG_INET=y |
| @@ -304,26 +351,26 @@ CONFIG_INET_TCP_DIAG=y | |||
| 304 | CONFIG_TCP_CONG_CUBIC=y | 351 | CONFIG_TCP_CONG_CUBIC=y |
| 305 | CONFIG_DEFAULT_TCP_CONG="cubic" | 352 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 306 | # CONFIG_TCP_MD5SIG is not set | 353 | # CONFIG_TCP_MD5SIG is not set |
| 307 | # CONFIG_IP_VS is not set | ||
| 308 | # CONFIG_IPV6 is not set | 354 | # CONFIG_IPV6 is not set |
| 309 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 310 | # CONFIG_INET6_TUNNEL is not set | ||
| 311 | # CONFIG_NETLABEL is not set | 355 | # CONFIG_NETLABEL is not set |
| 312 | # CONFIG_NETWORK_SECMARK is not set | 356 | # CONFIG_NETWORK_SECMARK is not set |
| 313 | CONFIG_NETFILTER=y | 357 | CONFIG_NETFILTER=y |
| 314 | # CONFIG_NETFILTER_DEBUG is not set | 358 | # CONFIG_NETFILTER_DEBUG is not set |
| 359 | CONFIG_NETFILTER_ADVANCED=y | ||
| 315 | 360 | ||
| 316 | # | 361 | # |
| 317 | # Core Netfilter Configuration | 362 | # Core Netfilter Configuration |
| 318 | # | 363 | # |
| 319 | # CONFIG_NETFILTER_NETLINK is not set | 364 | # CONFIG_NETFILTER_NETLINK_QUEUE is not set |
| 320 | # CONFIG_NF_CONNTRACK_ENABLED is not set | 365 | # CONFIG_NETFILTER_NETLINK_LOG is not set |
| 321 | # CONFIG_NF_CONNTRACK is not set | 366 | # CONFIG_NF_CONNTRACK is not set |
| 322 | # CONFIG_NETFILTER_XTABLES is not set | 367 | # CONFIG_NETFILTER_XTABLES is not set |
| 368 | # CONFIG_IP_VS is not set | ||
| 323 | 369 | ||
| 324 | # | 370 | # |
| 325 | # IP: Netfilter Configuration | 371 | # IP: Netfilter Configuration |
| 326 | # | 372 | # |
| 373 | # CONFIG_NF_DEFRAG_IPV4 is not set | ||
| 327 | CONFIG_IP_NF_QUEUE=m | 374 | CONFIG_IP_NF_QUEUE=m |
| 328 | # CONFIG_IP_NF_IPTABLES is not set | 375 | # CONFIG_IP_NF_IPTABLES is not set |
| 329 | # CONFIG_IP_NF_ARPTABLES is not set | 376 | # CONFIG_IP_NF_ARPTABLES is not set |
| @@ -332,7 +379,9 @@ CONFIG_IP_NF_QUEUE=m | |||
| 332 | # CONFIG_TIPC is not set | 379 | # CONFIG_TIPC is not set |
| 333 | # CONFIG_ATM is not set | 380 | # CONFIG_ATM is not set |
| 334 | # CONFIG_BRIDGE is not set | 381 | # CONFIG_BRIDGE is not set |
| 382 | # CONFIG_NET_DSA is not set | ||
| 335 | CONFIG_VLAN_8021Q=m | 383 | CONFIG_VLAN_8021Q=m |
| 384 | # CONFIG_VLAN_8021Q_GVRP is not set | ||
| 336 | # CONFIG_DECNET is not set | 385 | # CONFIG_DECNET is not set |
| 337 | # CONFIG_LLC2 is not set | 386 | # CONFIG_LLC2 is not set |
| 338 | # CONFIG_IPX is not set | 387 | # CONFIG_IPX is not set |
| @@ -342,12 +391,14 @@ CONFIG_VLAN_8021Q=m | |||
| 342 | # CONFIG_ECONET is not set | 391 | # CONFIG_ECONET is not set |
| 343 | # CONFIG_WAN_ROUTER is not set | 392 | # CONFIG_WAN_ROUTER is not set |
| 344 | # CONFIG_NET_SCHED is not set | 393 | # CONFIG_NET_SCHED is not set |
| 394 | # CONFIG_DCB is not set | ||
| 345 | 395 | ||
| 346 | # | 396 | # |
| 347 | # Network testing | 397 | # Network testing |
| 348 | # | 398 | # |
| 349 | # CONFIG_NET_PKTGEN is not set | 399 | # CONFIG_NET_PKTGEN is not set |
| 350 | # CONFIG_HAMRADIO is not set | 400 | # CONFIG_HAMRADIO is not set |
| 401 | # CONFIG_CAN is not set | ||
| 351 | CONFIG_IRDA=m | 402 | CONFIG_IRDA=m |
| 352 | 403 | ||
| 353 | # | 404 | # |
| @@ -382,15 +433,6 @@ CONFIG_IRTTY_SIR=m | |||
| 382 | # CONFIG_KS959_DONGLE is not set | 433 | # CONFIG_KS959_DONGLE is not set |
| 383 | 434 | ||
| 384 | # | 435 | # |
| 385 | # Old SIR device drivers | ||
| 386 | # | ||
| 387 | # CONFIG_IRPORT_SIR is not set | ||
| 388 | |||
| 389 | # | ||
| 390 | # Old Serial dongle support | ||
| 391 | # | ||
| 392 | |||
| 393 | # | ||
| 394 | # FIR device drivers | 436 | # FIR device drivers |
| 395 | # | 437 | # |
| 396 | # CONFIG_USB_IRDA is not set | 438 | # CONFIG_USB_IRDA is not set |
| @@ -410,7 +452,6 @@ CONFIG_BT_HIDP=m | |||
| 410 | # | 452 | # |
| 411 | # Bluetooth device drivers | 453 | # Bluetooth device drivers |
| 412 | # | 454 | # |
| 413 | # CONFIG_BT_HCIUSB is not set | ||
| 414 | # CONFIG_BT_HCIBTUSB is not set | 455 | # CONFIG_BT_HCIBTUSB is not set |
| 415 | # CONFIG_BT_HCIBTSDIO is not set | 456 | # CONFIG_BT_HCIBTSDIO is not set |
| 416 | # CONFIG_BT_HCIUART is not set | 457 | # CONFIG_BT_HCIUART is not set |
| @@ -419,21 +460,20 @@ CONFIG_BT_HIDP=m | |||
| 419 | # CONFIG_BT_HCIBFUSB is not set | 460 | # CONFIG_BT_HCIBFUSB is not set |
| 420 | # CONFIG_BT_HCIVHCI is not set | 461 | # CONFIG_BT_HCIVHCI is not set |
| 421 | # CONFIG_AF_RXRPC is not set | 462 | # CONFIG_AF_RXRPC is not set |
| 422 | 463 | # CONFIG_PHONET is not set | |
| 423 | # | 464 | CONFIG_WIRELESS=y |
| 424 | # Wireless | ||
| 425 | # | ||
| 426 | CONFIG_CFG80211=y | 465 | CONFIG_CFG80211=y |
| 466 | # CONFIG_CFG80211_REG_DEBUG is not set | ||
| 427 | CONFIG_NL80211=y | 467 | CONFIG_NL80211=y |
| 468 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 428 | CONFIG_WIRELESS_EXT=y | 469 | CONFIG_WIRELESS_EXT=y |
| 470 | CONFIG_WIRELESS_EXT_SYSFS=y | ||
| 471 | CONFIG_LIB80211=y | ||
| 472 | CONFIG_LIB80211_CRYPT_WEP=y | ||
| 473 | CONFIG_LIB80211_CRYPT_CCMP=y | ||
| 474 | CONFIG_LIB80211_CRYPT_TKIP=y | ||
| 429 | # CONFIG_MAC80211 is not set | 475 | # CONFIG_MAC80211 is not set |
| 430 | CONFIG_IEEE80211=y | 476 | # CONFIG_WIMAX is not set |
| 431 | # CONFIG_IEEE80211_DEBUG is not set | ||
| 432 | CONFIG_IEEE80211_CRYPT_WEP=y | ||
| 433 | CONFIG_IEEE80211_CRYPT_CCMP=m | ||
| 434 | CONFIG_IEEE80211_CRYPT_TKIP=m | ||
| 435 | CONFIG_IEEE80211_SOFTMAC=m | ||
| 436 | # CONFIG_IEEE80211_SOFTMAC_DEBUG is not set | ||
| 437 | # CONFIG_RFKILL is not set | 477 | # CONFIG_RFKILL is not set |
| 438 | # CONFIG_NET_9P is not set | 478 | # CONFIG_NET_9P is not set |
| 439 | 479 | ||
| @@ -448,6 +488,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |||
| 448 | CONFIG_STANDALONE=y | 488 | CONFIG_STANDALONE=y |
| 449 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 489 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 450 | CONFIG_FW_LOADER=y | 490 | CONFIG_FW_LOADER=y |
| 491 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 492 | CONFIG_EXTRA_FIRMWARE="" | ||
| 451 | # CONFIG_DEBUG_DRIVER is not set | 493 | # CONFIG_DEBUG_DRIVER is not set |
| 452 | # CONFIG_DEBUG_DEVRES is not set | 494 | # CONFIG_DEBUG_DEVRES is not set |
| 453 | # CONFIG_SYS_HYPERVISOR is not set | 495 | # CONFIG_SYS_HYPERVISOR is not set |
| @@ -457,9 +499,11 @@ CONFIG_MTD=y | |||
| 457 | # CONFIG_MTD_DEBUG is not set | 499 | # CONFIG_MTD_DEBUG is not set |
| 458 | CONFIG_MTD_CONCAT=y | 500 | CONFIG_MTD_CONCAT=y |
| 459 | CONFIG_MTD_PARTITIONS=y | 501 | CONFIG_MTD_PARTITIONS=y |
| 502 | # CONFIG_MTD_TESTS is not set | ||
| 460 | # CONFIG_MTD_REDBOOT_PARTS is not set | 503 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 461 | # CONFIG_MTD_CMDLINE_PARTS is not set | 504 | # CONFIG_MTD_CMDLINE_PARTS is not set |
| 462 | # CONFIG_MTD_AFS_PARTS is not set | 505 | # CONFIG_MTD_AFS_PARTS is not set |
| 506 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 463 | 507 | ||
| 464 | # | 508 | # |
| 465 | # User Modules And Translation Layers | 509 | # User Modules And Translation Layers |
| @@ -510,9 +554,7 @@ CONFIG_MTD_CFI_UTIL=y | |||
| 510 | # | 554 | # |
| 511 | CONFIG_MTD_COMPLEX_MAPPINGS=y | 555 | CONFIG_MTD_COMPLEX_MAPPINGS=y |
| 512 | CONFIG_MTD_PHYSMAP=y | 556 | CONFIG_MTD_PHYSMAP=y |
| 513 | CONFIG_MTD_PHYSMAP_START=0x0 | 557 | # CONFIG_MTD_PHYSMAP_COMPAT is not set |
| 514 | CONFIG_MTD_PHYSMAP_LEN=0x0 | ||
| 515 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | ||
| 516 | CONFIG_MTD_PXA2XX=y | 558 | CONFIG_MTD_PXA2XX=y |
| 517 | # CONFIG_MTD_ARM_INTEGRATOR is not set | 559 | # CONFIG_MTD_ARM_INTEGRATOR is not set |
| 518 | # CONFIG_MTD_IMPA7 is not set | 560 | # CONFIG_MTD_IMPA7 is not set |
| @@ -538,6 +580,7 @@ CONFIG_MTD_NAND=y | |||
| 538 | # CONFIG_MTD_NAND_ECC_SMC is not set | 580 | # CONFIG_MTD_NAND_ECC_SMC is not set |
| 539 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | 581 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set |
| 540 | # CONFIG_MTD_NAND_H1900 is not set | 582 | # CONFIG_MTD_NAND_H1900 is not set |
| 583 | # CONFIG_MTD_NAND_GPIO is not set | ||
| 541 | CONFIG_MTD_NAND_IDS=y | 584 | CONFIG_MTD_NAND_IDS=y |
| 542 | CONFIG_MTD_NAND_DISKONCHIP=y | 585 | CONFIG_MTD_NAND_DISKONCHIP=y |
| 543 | CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y | 586 | CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y |
| @@ -556,6 +599,11 @@ CONFIG_MTD_ONENAND=y | |||
| 556 | # CONFIG_MTD_ONENAND_SIM is not set | 599 | # CONFIG_MTD_ONENAND_SIM is not set |
| 557 | 600 | ||
| 558 | # | 601 | # |
| 602 | # LPDDR flash memory drivers | ||
| 603 | # | ||
| 604 | # CONFIG_MTD_LPDDR is not set | ||
| 605 | |||
| 606 | # | ||
| 559 | # UBI - Unsorted block images | 607 | # UBI - Unsorted block images |
| 560 | # | 608 | # |
| 561 | # CONFIG_MTD_UBI is not set | 609 | # CONFIG_MTD_UBI is not set |
| @@ -569,36 +617,41 @@ CONFIG_BLK_DEV_NBD=y | |||
| 569 | CONFIG_BLK_DEV_RAM=y | 617 | CONFIG_BLK_DEV_RAM=y |
| 570 | CONFIG_BLK_DEV_RAM_COUNT=8 | 618 | CONFIG_BLK_DEV_RAM_COUNT=8 |
| 571 | CONFIG_BLK_DEV_RAM_SIZE=4096 | 619 | CONFIG_BLK_DEV_RAM_SIZE=4096 |
| 572 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 620 | # CONFIG_BLK_DEV_XIP is not set |
| 573 | # CONFIG_CDROM_PKTCDVD is not set | 621 | # CONFIG_CDROM_PKTCDVD is not set |
| 574 | # CONFIG_ATA_OVER_ETH is not set | 622 | # CONFIG_ATA_OVER_ETH is not set |
| 575 | CONFIG_MISC_DEVICES=y | 623 | CONFIG_MISC_DEVICES=y |
| 624 | # CONFIG_ICS932S401 is not set | ||
| 625 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 626 | # CONFIG_ISL29003 is not set | ||
| 627 | # CONFIG_C2PORT is not set | ||
| 628 | |||
| 629 | # | ||
| 630 | # EEPROM support | ||
| 631 | # | ||
| 632 | # CONFIG_EEPROM_AT24 is not set | ||
| 633 | # CONFIG_EEPROM_LEGACY is not set | ||
| 576 | # CONFIG_EEPROM_93CX6 is not set | 634 | # CONFIG_EEPROM_93CX6 is not set |
| 635 | CONFIG_HAVE_IDE=y | ||
| 577 | CONFIG_IDE=y | 636 | CONFIG_IDE=y |
| 578 | CONFIG_IDE_MAX_HWIFS=4 | ||
| 579 | CONFIG_BLK_DEV_IDE=y | ||
| 580 | 637 | ||
| 581 | # | 638 | # |
| 582 | # Please see Documentation/ide.txt for help/info on IDE drives | 639 | # Please see Documentation/ide/ide.txt for help/info on IDE drives |
| 583 | # | 640 | # |
| 584 | # CONFIG_BLK_DEV_IDE_SATA is not set | 641 | # CONFIG_BLK_DEV_IDE_SATA is not set |
| 585 | CONFIG_BLK_DEV_IDEDISK=y | 642 | CONFIG_IDE_GD=y |
| 586 | CONFIG_IDEDISK_MULTI_MODE=y | 643 | CONFIG_IDE_GD_ATA=y |
| 644 | # CONFIG_IDE_GD_ATAPI is not set | ||
| 587 | # CONFIG_BLK_DEV_IDECD is not set | 645 | # CONFIG_BLK_DEV_IDECD is not set |
| 588 | # CONFIG_BLK_DEV_IDETAPE is not set | 646 | # CONFIG_BLK_DEV_IDETAPE is not set |
| 589 | # CONFIG_BLK_DEV_IDEFLOPPY is not set | ||
| 590 | # CONFIG_IDE_TASK_IOCTL is not set | 647 | # CONFIG_IDE_TASK_IOCTL is not set |
| 591 | CONFIG_IDE_PROC_FS=y | 648 | CONFIG_IDE_PROC_FS=y |
| 592 | 649 | ||
| 593 | # | 650 | # |
| 594 | # IDE chipset support/bugfixes | 651 | # IDE chipset support/bugfixes |
| 595 | # | 652 | # |
| 596 | CONFIG_IDE_GENERIC=y | ||
| 597 | # CONFIG_BLK_DEV_PLATFORM is not set | 653 | # CONFIG_BLK_DEV_PLATFORM is not set |
| 598 | # CONFIG_IDE_ARM is not set | ||
| 599 | # CONFIG_BLK_DEV_IDEDMA is not set | 654 | # CONFIG_BLK_DEV_IDEDMA is not set |
| 600 | CONFIG_IDE_ARCH_OBSOLETE_INIT=y | ||
| 601 | # CONFIG_BLK_DEV_HD is not set | ||
| 602 | 655 | ||
| 603 | # | 656 | # |
| 604 | # SCSI device support | 657 | # SCSI device support |
| @@ -610,7 +663,6 @@ CONFIG_IDE_ARCH_OBSOLETE_INIT=y | |||
| 610 | # CONFIG_ATA is not set | 663 | # CONFIG_ATA is not set |
| 611 | # CONFIG_MD is not set | 664 | # CONFIG_MD is not set |
| 612 | CONFIG_NETDEVICES=y | 665 | CONFIG_NETDEVICES=y |
| 613 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 614 | # CONFIG_DUMMY is not set | 666 | # CONFIG_DUMMY is not set |
| 615 | # CONFIG_BONDING is not set | 667 | # CONFIG_BONDING is not set |
| 616 | # CONFIG_MACVLAN is not set | 668 | # CONFIG_MACVLAN is not set |
| @@ -631,6 +683,10 @@ CONFIG_PHYLIB=y | |||
| 631 | # CONFIG_SMSC_PHY is not set | 683 | # CONFIG_SMSC_PHY is not set |
| 632 | # CONFIG_BROADCOM_PHY is not set | 684 | # CONFIG_BROADCOM_PHY is not set |
| 633 | # CONFIG_ICPLUS_PHY is not set | 685 | # CONFIG_ICPLUS_PHY is not set |
| 686 | # CONFIG_REALTEK_PHY is not set | ||
| 687 | # CONFIG_NATIONAL_PHY is not set | ||
| 688 | # CONFIG_STE10XP is not set | ||
| 689 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 634 | # CONFIG_FIXED_PHY is not set | 690 | # CONFIG_FIXED_PHY is not set |
| 635 | # CONFIG_MDIO_BITBANG is not set | 691 | # CONFIG_MDIO_BITBANG is not set |
| 636 | CONFIG_NET_ETHERNET=y | 692 | CONFIG_NET_ETHERNET=y |
| @@ -638,11 +694,17 @@ CONFIG_MII=y | |||
| 638 | # CONFIG_AX88796 is not set | 694 | # CONFIG_AX88796 is not set |
| 639 | # CONFIG_SMC91X is not set | 695 | # CONFIG_SMC91X is not set |
| 640 | CONFIG_DM9000=y | 696 | CONFIG_DM9000=y |
| 697 | CONFIG_DM9000_DEBUGLEVEL=4 | ||
| 698 | # CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set | ||
| 641 | # CONFIG_SMC911X is not set | 699 | # CONFIG_SMC911X is not set |
| 700 | # CONFIG_SMSC911X is not set | ||
| 642 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | 701 | # CONFIG_IBM_NEW_EMAC_ZMII is not set |
| 643 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 702 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 644 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 703 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 645 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 704 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 705 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 706 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 707 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 646 | # CONFIG_B44 is not set | 708 | # CONFIG_B44 is not set |
| 647 | # CONFIG_NETDEV_1000 is not set | 709 | # CONFIG_NETDEV_1000 is not set |
| 648 | # CONFIG_NETDEV_10000 is not set | 710 | # CONFIG_NETDEV_10000 is not set |
| @@ -654,10 +716,15 @@ CONFIG_DM9000=y | |||
| 654 | CONFIG_WLAN_80211=y | 716 | CONFIG_WLAN_80211=y |
| 655 | # CONFIG_LIBERTAS is not set | 717 | # CONFIG_LIBERTAS is not set |
| 656 | # CONFIG_USB_ZD1201 is not set | 718 | # CONFIG_USB_ZD1201 is not set |
| 719 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
| 720 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 657 | CONFIG_HOSTAP=y | 721 | CONFIG_HOSTAP=y |
| 658 | CONFIG_HOSTAP_FIRMWARE=y | 722 | CONFIG_HOSTAP_FIRMWARE=y |
| 659 | CONFIG_HOSTAP_FIRMWARE_NVRAM=y | 723 | CONFIG_HOSTAP_FIRMWARE_NVRAM=y |
| 660 | # CONFIG_ZD1211RW is not set | 724 | |
| 725 | # | ||
| 726 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 727 | # | ||
| 661 | 728 | ||
| 662 | # | 729 | # |
| 663 | # USB Network Adapters | 730 | # USB Network Adapters |
| @@ -670,7 +737,6 @@ CONFIG_HOSTAP_FIRMWARE_NVRAM=y | |||
| 670 | # CONFIG_WAN is not set | 737 | # CONFIG_WAN is not set |
| 671 | # CONFIG_PPP is not set | 738 | # CONFIG_PPP is not set |
| 672 | # CONFIG_SLIP is not set | 739 | # CONFIG_SLIP is not set |
| 673 | # CONFIG_SHAPER is not set | ||
| 674 | # CONFIG_NETCONSOLE is not set | 740 | # CONFIG_NETCONSOLE is not set |
| 675 | # CONFIG_NETPOLL is not set | 741 | # CONFIG_NETPOLL is not set |
| 676 | # CONFIG_NET_POLL_CONTROLLER is not set | 742 | # CONFIG_NET_POLL_CONTROLLER is not set |
| @@ -710,6 +776,7 @@ CONFIG_INPUT_MOUSE=y | |||
| 710 | # CONFIG_MOUSE_PS2 is not set | 776 | # CONFIG_MOUSE_PS2 is not set |
| 711 | CONFIG_MOUSE_SERIAL=m | 777 | CONFIG_MOUSE_SERIAL=m |
| 712 | # CONFIG_MOUSE_APPLETOUCH is not set | 778 | # CONFIG_MOUSE_APPLETOUCH is not set |
| 779 | # CONFIG_MOUSE_BCM5974 is not set | ||
| 713 | # CONFIG_MOUSE_VSXXXAA is not set | 780 | # CONFIG_MOUSE_VSXXXAA is not set |
| 714 | # CONFIG_MOUSE_GPIO is not set | 781 | # CONFIG_MOUSE_GPIO is not set |
| 715 | # CONFIG_INPUT_JOYSTICK is not set | 782 | # CONFIG_INPUT_JOYSTICK is not set |
| @@ -718,20 +785,25 @@ CONFIG_INPUT_TOUCHSCREEN=y | |||
| 718 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | 785 | # CONFIG_TOUCHSCREEN_FUJITSU is not set |
| 719 | # CONFIG_TOUCHSCREEN_GUNZE is not set | 786 | # CONFIG_TOUCHSCREEN_GUNZE is not set |
| 720 | # CONFIG_TOUCHSCREEN_ELO is not set | 787 | # CONFIG_TOUCHSCREEN_ELO is not set |
| 788 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 721 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | 789 | # CONFIG_TOUCHSCREEN_MTOUCH is not set |
| 790 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 722 | # CONFIG_TOUCHSCREEN_MK712 is not set | 791 | # CONFIG_TOUCHSCREEN_MK712 is not set |
| 723 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | 792 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set |
| 724 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | 793 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set |
| 725 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | 794 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set |
| 726 | CONFIG_TOUCHSCREEN_UCB1400=y | ||
| 727 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | 795 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set |
| 796 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 797 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 728 | CONFIG_INPUT_MISC=y | 798 | CONFIG_INPUT_MISC=y |
| 729 | # CONFIG_INPUT_ATI_REMOTE is not set | 799 | # CONFIG_INPUT_ATI_REMOTE is not set |
| 730 | # CONFIG_INPUT_ATI_REMOTE2 is not set | 800 | # CONFIG_INPUT_ATI_REMOTE2 is not set |
| 731 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | 801 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set |
| 732 | # CONFIG_INPUT_POWERMATE is not set | 802 | # CONFIG_INPUT_POWERMATE is not set |
| 733 | # CONFIG_INPUT_YEALINK is not set | 803 | # CONFIG_INPUT_YEALINK is not set |
| 804 | # CONFIG_INPUT_CM109 is not set | ||
| 734 | CONFIG_INPUT_UINPUT=m | 805 | CONFIG_INPUT_UINPUT=m |
| 806 | # CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set | ||
| 735 | 807 | ||
| 736 | # | 808 | # |
| 737 | # Hardware I/O ports | 809 | # Hardware I/O ports |
| @@ -746,9 +818,11 @@ CONFIG_SERIO_LIBPS2=y | |||
| 746 | # Character devices | 818 | # Character devices |
| 747 | # | 819 | # |
| 748 | CONFIG_VT=y | 820 | CONFIG_VT=y |
| 821 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 749 | CONFIG_VT_CONSOLE=y | 822 | CONFIG_VT_CONSOLE=y |
| 750 | CONFIG_HW_CONSOLE=y | 823 | CONFIG_HW_CONSOLE=y |
| 751 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | 824 | # CONFIG_VT_HW_CONSOLE_BINDING is not set |
| 825 | CONFIG_DEVKMEM=y | ||
| 752 | # CONFIG_SERIAL_NONSTANDARD is not set | 826 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 753 | 827 | ||
| 754 | # | 828 | # |
| @@ -764,45 +838,50 @@ CONFIG_SERIAL_PXA_CONSOLE=y | |||
| 764 | CONFIG_SERIAL_CORE=y | 838 | CONFIG_SERIAL_CORE=y |
| 765 | CONFIG_SERIAL_CORE_CONSOLE=y | 839 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 766 | CONFIG_UNIX98_PTYS=y | 840 | CONFIG_UNIX98_PTYS=y |
| 841 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 767 | CONFIG_LEGACY_PTYS=y | 842 | CONFIG_LEGACY_PTYS=y |
| 768 | CONFIG_LEGACY_PTY_COUNT=256 | 843 | CONFIG_LEGACY_PTY_COUNT=256 |
| 769 | # CONFIG_IPMI_HANDLER is not set | 844 | # CONFIG_IPMI_HANDLER is not set |
| 770 | CONFIG_HW_RANDOM=y | 845 | CONFIG_HW_RANDOM=y |
| 771 | # CONFIG_NVRAM is not set | ||
| 772 | # CONFIG_R3964 is not set | 846 | # CONFIG_R3964 is not set |
| 773 | # CONFIG_RAW_DRIVER is not set | 847 | # CONFIG_RAW_DRIVER is not set |
| 774 | # CONFIG_TCG_TPM is not set | 848 | # CONFIG_TCG_TPM is not set |
| 775 | CONFIG_I2C=y | 849 | CONFIG_I2C=y |
| 776 | CONFIG_I2C_BOARDINFO=y | 850 | CONFIG_I2C_BOARDINFO=y |
| 777 | CONFIG_I2C_CHARDEV=y | 851 | CONFIG_I2C_CHARDEV=y |
| 852 | CONFIG_I2C_HELPER_AUTO=y | ||
| 778 | 853 | ||
| 779 | # | 854 | # |
| 780 | # I2C Algorithms | 855 | # I2C Hardware Bus support |
| 781 | # | 856 | # |
| 782 | # CONFIG_I2C_ALGOBIT is not set | ||
| 783 | # CONFIG_I2C_ALGOPCF is not set | ||
| 784 | # CONFIG_I2C_ALGOPCA is not set | ||
| 785 | 857 | ||
| 786 | # | 858 | # |
| 787 | # I2C Hardware Bus support | 859 | # I2C system bus drivers (mostly embedded / system-on-chip) |
| 788 | # | 860 | # |
| 789 | # CONFIG_I2C_GPIO is not set | 861 | # CONFIG_I2C_GPIO is not set |
| 790 | # CONFIG_I2C_PXA is not set | ||
| 791 | # CONFIG_I2C_OCORES is not set | 862 | # CONFIG_I2C_OCORES is not set |
| 792 | # CONFIG_I2C_PARPORT_LIGHT is not set | 863 | # CONFIG_I2C_PXA is not set |
| 793 | # CONFIG_I2C_SIMTEC is not set | 864 | # CONFIG_I2C_SIMTEC is not set |
| 865 | |||
| 866 | # | ||
| 867 | # External I2C/SMBus adapter drivers | ||
| 868 | # | ||
| 869 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 794 | # CONFIG_I2C_TAOS_EVM is not set | 870 | # CONFIG_I2C_TAOS_EVM is not set |
| 795 | # CONFIG_I2C_STUB is not set | ||
| 796 | # CONFIG_I2C_TINY_USB is not set | 871 | # CONFIG_I2C_TINY_USB is not set |
| 797 | 872 | ||
| 798 | # | 873 | # |
| 874 | # Other I2C/SMBus bus drivers | ||
| 875 | # | ||
| 876 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 877 | # CONFIG_I2C_STUB is not set | ||
| 878 | |||
| 879 | # | ||
| 799 | # Miscellaneous I2C Chip support | 880 | # Miscellaneous I2C Chip support |
| 800 | # | 881 | # |
| 801 | # CONFIG_SENSORS_DS1337 is not set | ||
| 802 | # CONFIG_SENSORS_DS1374 is not set | ||
| 803 | # CONFIG_DS1682 is not set | 882 | # CONFIG_DS1682 is not set |
| 804 | # CONFIG_EEPROM_LEGACY is not set | ||
| 805 | # CONFIG_SENSORS_PCF8574 is not set | 883 | # CONFIG_SENSORS_PCF8574 is not set |
| 884 | # CONFIG_PCF8575 is not set | ||
| 806 | # CONFIG_SENSORS_PCA9539 is not set | 885 | # CONFIG_SENSORS_PCA9539 is not set |
| 807 | # CONFIG_SENSORS_PCF8591 is not set | 886 | # CONFIG_SENSORS_PCF8591 is not set |
| 808 | # CONFIG_SENSORS_MAX6875 is not set | 887 | # CONFIG_SENSORS_MAX6875 is not set |
| @@ -811,16 +890,35 @@ CONFIG_I2C_CHARDEV=y | |||
| 811 | # CONFIG_I2C_DEBUG_ALGO is not set | 890 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 812 | # CONFIG_I2C_DEBUG_BUS is not set | 891 | # CONFIG_I2C_DEBUG_BUS is not set |
| 813 | # CONFIG_I2C_DEBUG_CHIP is not set | 892 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 893 | # CONFIG_SPI is not set | ||
| 894 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 895 | CONFIG_GPIOLIB=y | ||
| 896 | # CONFIG_DEBUG_GPIO is not set | ||
| 897 | # CONFIG_GPIO_SYSFS is not set | ||
| 814 | 898 | ||
| 815 | # | 899 | # |
| 816 | # SPI support | 900 | # Memory mapped GPIO expanders: |
| 901 | # | ||
| 902 | |||
| 903 | # | ||
| 904 | # I2C GPIO expanders: | ||
| 905 | # | ||
| 906 | # CONFIG_GPIO_MAX732X is not set | ||
| 907 | # CONFIG_GPIO_PCA953X is not set | ||
| 908 | # CONFIG_GPIO_PCF857X is not set | ||
| 909 | |||
| 910 | # | ||
| 911 | # PCI GPIO expanders: | ||
| 912 | # | ||
| 913 | |||
| 914 | # | ||
| 915 | # SPI GPIO expanders: | ||
| 817 | # | 916 | # |
| 818 | # CONFIG_SPI is not set | ||
| 819 | # CONFIG_SPI_MASTER is not set | ||
| 820 | # CONFIG_W1 is not set | 917 | # CONFIG_W1 is not set |
| 821 | # CONFIG_POWER_SUPPLY is not set | 918 | # CONFIG_POWER_SUPPLY is not set |
| 822 | CONFIG_HWMON=y | 919 | CONFIG_HWMON=y |
| 823 | # CONFIG_HWMON_VID is not set | 920 | # CONFIG_HWMON_VID is not set |
| 921 | # CONFIG_SENSORS_AD7414 is not set | ||
| 824 | # CONFIG_SENSORS_AD7418 is not set | 922 | # CONFIG_SENSORS_AD7418 is not set |
| 825 | # CONFIG_SENSORS_ADM1021 is not set | 923 | # CONFIG_SENSORS_ADM1021 is not set |
| 826 | # CONFIG_SENSORS_ADM1025 is not set | 924 | # CONFIG_SENSORS_ADM1025 is not set |
| @@ -828,7 +926,10 @@ CONFIG_HWMON=y | |||
| 828 | # CONFIG_SENSORS_ADM1029 is not set | 926 | # CONFIG_SENSORS_ADM1029 is not set |
| 829 | # CONFIG_SENSORS_ADM1031 is not set | 927 | # CONFIG_SENSORS_ADM1031 is not set |
| 830 | # CONFIG_SENSORS_ADM9240 is not set | 928 | # CONFIG_SENSORS_ADM9240 is not set |
| 929 | # CONFIG_SENSORS_ADT7462 is not set | ||
| 831 | # CONFIG_SENSORS_ADT7470 is not set | 930 | # CONFIG_SENSORS_ADT7470 is not set |
| 931 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 932 | # CONFIG_SENSORS_ADT7475 is not set | ||
| 832 | # CONFIG_SENSORS_ATXP1 is not set | 933 | # CONFIG_SENSORS_ATXP1 is not set |
| 833 | # CONFIG_SENSORS_DS1621 is not set | 934 | # CONFIG_SENSORS_DS1621 is not set |
| 834 | # CONFIG_SENSORS_F71805F is not set | 935 | # CONFIG_SENSORS_F71805F is not set |
| @@ -848,6 +949,7 @@ CONFIG_HWMON=y | |||
| 848 | # CONFIG_SENSORS_LM90 is not set | 949 | # CONFIG_SENSORS_LM90 is not set |
| 849 | # CONFIG_SENSORS_LM92 is not set | 950 | # CONFIG_SENSORS_LM92 is not set |
| 850 | # CONFIG_SENSORS_LM93 is not set | 951 | # CONFIG_SENSORS_LM93 is not set |
| 952 | # CONFIG_SENSORS_LTC4245 is not set | ||
| 851 | # CONFIG_SENSORS_MAX1619 is not set | 953 | # CONFIG_SENSORS_MAX1619 is not set |
| 852 | # CONFIG_SENSORS_MAX6650 is not set | 954 | # CONFIG_SENSORS_MAX6650 is not set |
| 853 | # CONFIG_SENSORS_PC87360 is not set | 955 | # CONFIG_SENSORS_PC87360 is not set |
| @@ -856,6 +958,7 @@ CONFIG_HWMON=y | |||
| 856 | # CONFIG_SENSORS_SMSC47M1 is not set | 958 | # CONFIG_SENSORS_SMSC47M1 is not set |
| 857 | # CONFIG_SENSORS_SMSC47M192 is not set | 959 | # CONFIG_SENSORS_SMSC47M192 is not set |
| 858 | # CONFIG_SENSORS_SMSC47B397 is not set | 960 | # CONFIG_SENSORS_SMSC47B397 is not set |
| 961 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 859 | # CONFIG_SENSORS_THMC50 is not set | 962 | # CONFIG_SENSORS_THMC50 is not set |
| 860 | # CONFIG_SENSORS_VT1211 is not set | 963 | # CONFIG_SENSORS_VT1211 is not set |
| 861 | # CONFIG_SENSORS_W83781D is not set | 964 | # CONFIG_SENSORS_W83781D is not set |
| @@ -863,9 +966,12 @@ CONFIG_HWMON=y | |||
| 863 | # CONFIG_SENSORS_W83792D is not set | 966 | # CONFIG_SENSORS_W83792D is not set |
| 864 | # CONFIG_SENSORS_W83793 is not set | 967 | # CONFIG_SENSORS_W83793 is not set |
| 865 | # CONFIG_SENSORS_W83L785TS is not set | 968 | # CONFIG_SENSORS_W83L785TS is not set |
| 969 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 866 | # CONFIG_SENSORS_W83627HF is not set | 970 | # CONFIG_SENSORS_W83627HF is not set |
| 867 | # CONFIG_SENSORS_W83627EHF is not set | 971 | # CONFIG_SENSORS_W83627EHF is not set |
| 868 | # CONFIG_HWMON_DEBUG_CHIP is not set | 972 | # CONFIG_HWMON_DEBUG_CHIP is not set |
| 973 | # CONFIG_THERMAL is not set | ||
| 974 | # CONFIG_THERMAL_HWMON is not set | ||
| 869 | CONFIG_WATCHDOG=y | 975 | CONFIG_WATCHDOG=y |
| 870 | # CONFIG_WATCHDOG_NOWAYOUT is not set | 976 | # CONFIG_WATCHDOG_NOWAYOUT is not set |
| 871 | 977 | ||
| @@ -879,23 +985,46 @@ CONFIG_WATCHDOG=y | |||
| 879 | # USB-based Watchdog Cards | 985 | # USB-based Watchdog Cards |
| 880 | # | 986 | # |
| 881 | # CONFIG_USBPCWATCHDOG is not set | 987 | # CONFIG_USBPCWATCHDOG is not set |
| 988 | CONFIG_SSB_POSSIBLE=y | ||
| 882 | 989 | ||
| 883 | # | 990 | # |
| 884 | # Sonics Silicon Backplane | 991 | # Sonics Silicon Backplane |
| 885 | # | 992 | # |
| 886 | CONFIG_SSB_POSSIBLE=y | ||
| 887 | # CONFIG_SSB is not set | 993 | # CONFIG_SSB is not set |
| 888 | 994 | ||
| 889 | # | 995 | # |
| 890 | # Multifunction device drivers | 996 | # Multifunction device drivers |
| 891 | # | 997 | # |
| 998 | # CONFIG_MFD_CORE is not set | ||
| 892 | # CONFIG_MFD_SM501 is not set | 999 | # CONFIG_MFD_SM501 is not set |
| 1000 | # CONFIG_MFD_ASIC3 is not set | ||
| 1001 | # CONFIG_HTC_EGPIO is not set | ||
| 1002 | # CONFIG_HTC_PASIC3 is not set | ||
| 1003 | # CONFIG_TPS65010 is not set | ||
| 1004 | # CONFIG_TWL4030_CORE is not set | ||
| 1005 | # CONFIG_MFD_TMIO is not set | ||
| 1006 | # CONFIG_MFD_T7L66XB is not set | ||
| 1007 | # CONFIG_MFD_TC6387XB is not set | ||
| 1008 | # CONFIG_MFD_TC6393XB is not set | ||
| 1009 | # CONFIG_PMIC_DA903X is not set | ||
| 1010 | # CONFIG_MFD_WM8400 is not set | ||
| 1011 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 1012 | # CONFIG_MFD_PCF50633 is not set | ||
| 893 | 1013 | ||
| 894 | # | 1014 | # |
| 895 | # Multimedia devices | 1015 | # Multimedia devices |
| 896 | # | 1016 | # |
| 1017 | |||
| 1018 | # | ||
| 1019 | # Multimedia core support | ||
| 1020 | # | ||
| 897 | # CONFIG_VIDEO_DEV is not set | 1021 | # CONFIG_VIDEO_DEV is not set |
| 898 | # CONFIG_DVB_CORE is not set | 1022 | # CONFIG_DVB_CORE is not set |
| 1023 | # CONFIG_VIDEO_MEDIA is not set | ||
| 1024 | |||
| 1025 | # | ||
| 1026 | # Multimedia drivers | ||
| 1027 | # | ||
| 899 | CONFIG_DAB=y | 1028 | CONFIG_DAB=y |
| 900 | # CONFIG_USB_DABUSB is not set | 1029 | # CONFIG_USB_DABUSB is not set |
| 901 | 1030 | ||
| @@ -907,6 +1036,7 @@ CONFIG_DAB=y | |||
| 907 | CONFIG_FB=y | 1036 | CONFIG_FB=y |
| 908 | CONFIG_FIRMWARE_EDID=y | 1037 | CONFIG_FIRMWARE_EDID=y |
| 909 | # CONFIG_FB_DDC is not set | 1038 | # CONFIG_FB_DDC is not set |
| 1039 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 910 | CONFIG_FB_CFB_FILLRECT=y | 1040 | CONFIG_FB_CFB_FILLRECT=y |
| 911 | CONFIG_FB_CFB_COPYAREA=y | 1041 | CONFIG_FB_CFB_COPYAREA=y |
| 912 | CONFIG_FB_CFB_IMAGEBLIT=y | 1042 | CONFIG_FB_CFB_IMAGEBLIT=y |
| @@ -914,8 +1044,8 @@ CONFIG_FB_CFB_IMAGEBLIT=y | |||
| 914 | # CONFIG_FB_SYS_FILLRECT is not set | 1044 | # CONFIG_FB_SYS_FILLRECT is not set |
| 915 | # CONFIG_FB_SYS_COPYAREA is not set | 1045 | # CONFIG_FB_SYS_COPYAREA is not set |
| 916 | # CONFIG_FB_SYS_IMAGEBLIT is not set | 1046 | # CONFIG_FB_SYS_IMAGEBLIT is not set |
| 1047 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 917 | # CONFIG_FB_SYS_FOPS is not set | 1048 | # CONFIG_FB_SYS_FOPS is not set |
| 918 | CONFIG_FB_DEFERRED_IO=y | ||
| 919 | # CONFIG_FB_SVGALIB is not set | 1049 | # CONFIG_FB_SVGALIB is not set |
| 920 | # CONFIG_FB_MACMODES is not set | 1050 | # CONFIG_FB_MACMODES is not set |
| 921 | # CONFIG_FB_BACKLIGHT is not set | 1051 | # CONFIG_FB_BACKLIGHT is not set |
| @@ -928,13 +1058,20 @@ CONFIG_FB_DEFERRED_IO=y | |||
| 928 | # CONFIG_FB_UVESA is not set | 1058 | # CONFIG_FB_UVESA is not set |
| 929 | # CONFIG_FB_S1D13XXX is not set | 1059 | # CONFIG_FB_S1D13XXX is not set |
| 930 | CONFIG_FB_PXA=y | 1060 | CONFIG_FB_PXA=y |
| 1061 | # CONFIG_FB_PXA_OVERLAY is not set | ||
| 1062 | # CONFIG_FB_PXA_SMARTPANEL is not set | ||
| 931 | # CONFIG_FB_PXA_PARAMETERS is not set | 1063 | # CONFIG_FB_PXA_PARAMETERS is not set |
| 932 | # CONFIG_FB_MBX is not set | 1064 | # CONFIG_FB_MBX is not set |
| 1065 | # CONFIG_FB_W100 is not set | ||
| 933 | # CONFIG_FB_VIRTUAL is not set | 1066 | # CONFIG_FB_VIRTUAL is not set |
| 1067 | # CONFIG_FB_METRONOME is not set | ||
| 1068 | # CONFIG_FB_MB862XX is not set | ||
| 934 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 1069 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 935 | CONFIG_LCD_CLASS_DEVICE=y | 1070 | CONFIG_LCD_CLASS_DEVICE=y |
| 1071 | # CONFIG_LCD_ILI9320 is not set | ||
| 1072 | # CONFIG_LCD_PLATFORM is not set | ||
| 936 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 1073 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 937 | # CONFIG_BACKLIGHT_CORGI is not set | 1074 | CONFIG_BACKLIGHT_GENERIC=y |
| 938 | 1075 | ||
| 939 | # | 1076 | # |
| 940 | # Display device support | 1077 | # Display device support |
| @@ -964,12 +1101,7 @@ CONFIG_LOGO=y | |||
| 964 | CONFIG_LOGO_LINUX_MONO=y | 1101 | CONFIG_LOGO_LINUX_MONO=y |
| 965 | CONFIG_LOGO_LINUX_VGA16=y | 1102 | CONFIG_LOGO_LINUX_VGA16=y |
| 966 | CONFIG_LOGO_LINUX_CLUT224=y | 1103 | CONFIG_LOGO_LINUX_CLUT224=y |
| 967 | |||
| 968 | # | ||
| 969 | # Sound | ||
| 970 | # | ||
| 971 | # CONFIG_SOUND is not set | 1104 | # CONFIG_SOUND is not set |
| 972 | CONFIG_AC97_BUS=y | ||
| 973 | CONFIG_HID_SUPPORT=y | 1105 | CONFIG_HID_SUPPORT=y |
| 974 | CONFIG_HID=y | 1106 | CONFIG_HID=y |
| 975 | # CONFIG_HID_DEBUG is not set | 1107 | # CONFIG_HID_DEBUG is not set |
| @@ -979,18 +1111,26 @@ CONFIG_HID=y | |||
| 979 | # USB Input Devices | 1111 | # USB Input Devices |
| 980 | # | 1112 | # |
| 981 | # CONFIG_USB_HID is not set | 1113 | # CONFIG_USB_HID is not set |
| 1114 | # CONFIG_HID_PID is not set | ||
| 982 | 1115 | ||
| 983 | # | 1116 | # |
| 984 | # USB HID Boot Protocol drivers | 1117 | # USB HID Boot Protocol drivers |
| 985 | # | 1118 | # |
| 986 | # CONFIG_USB_KBD is not set | 1119 | # CONFIG_USB_KBD is not set |
| 987 | # CONFIG_USB_MOUSE is not set | 1120 | # CONFIG_USB_MOUSE is not set |
| 1121 | |||
| 1122 | # | ||
| 1123 | # Special HID drivers | ||
| 1124 | # | ||
| 1125 | CONFIG_HID_COMPAT=y | ||
| 1126 | # CONFIG_HID_APPLE is not set | ||
| 988 | CONFIG_USB_SUPPORT=y | 1127 | CONFIG_USB_SUPPORT=y |
| 989 | CONFIG_USB_ARCH_HAS_HCD=y | 1128 | CONFIG_USB_ARCH_HAS_HCD=y |
| 990 | CONFIG_USB_ARCH_HAS_OHCI=y | 1129 | CONFIG_USB_ARCH_HAS_OHCI=y |
| 991 | # CONFIG_USB_ARCH_HAS_EHCI is not set | 1130 | # CONFIG_USB_ARCH_HAS_EHCI is not set |
| 992 | CONFIG_USB=y | 1131 | CONFIG_USB=y |
| 993 | # CONFIG_USB_DEBUG is not set | 1132 | # CONFIG_USB_DEBUG is not set |
| 1133 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 994 | 1134 | ||
| 995 | # | 1135 | # |
| 996 | # Miscellaneous USB options | 1136 | # Miscellaneous USB options |
| @@ -999,29 +1139,40 @@ CONFIG_USB_DEVICEFS=y | |||
| 999 | # CONFIG_USB_DEVICE_CLASS is not set | 1139 | # CONFIG_USB_DEVICE_CLASS is not set |
| 1000 | # CONFIG_USB_DYNAMIC_MINORS is not set | 1140 | # CONFIG_USB_DYNAMIC_MINORS is not set |
| 1001 | # CONFIG_USB_SUSPEND is not set | 1141 | # CONFIG_USB_SUSPEND is not set |
| 1002 | # CONFIG_USB_PERSIST is not set | ||
| 1003 | # CONFIG_USB_OTG is not set | 1142 | # CONFIG_USB_OTG is not set |
| 1143 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 1144 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
| 1145 | # CONFIG_USB_MON is not set | ||
| 1146 | # CONFIG_USB_WUSB is not set | ||
| 1147 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1004 | 1148 | ||
| 1005 | # | 1149 | # |
| 1006 | # USB Host Controller Drivers | 1150 | # USB Host Controller Drivers |
| 1007 | # | 1151 | # |
| 1152 | # CONFIG_USB_C67X00_HCD is not set | ||
| 1153 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1008 | # CONFIG_USB_ISP116X_HCD is not set | 1154 | # CONFIG_USB_ISP116X_HCD is not set |
| 1009 | # CONFIG_USB_OHCI_HCD is not set | 1155 | # CONFIG_USB_OHCI_HCD is not set |
| 1010 | # CONFIG_USB_SL811_HCD is not set | 1156 | # CONFIG_USB_SL811_HCD is not set |
| 1011 | # CONFIG_USB_R8A66597_HCD is not set | 1157 | # CONFIG_USB_R8A66597_HCD is not set |
| 1158 | # CONFIG_USB_HWA_HCD is not set | ||
| 1159 | # CONFIG_USB_MUSB_HDRC is not set | ||
| 1160 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
| 1012 | 1161 | ||
| 1013 | # | 1162 | # |
| 1014 | # USB Device Class drivers | 1163 | # USB Device Class drivers |
| 1015 | # | 1164 | # |
| 1016 | # CONFIG_USB_ACM is not set | 1165 | # CONFIG_USB_ACM is not set |
| 1017 | # CONFIG_USB_PRINTER is not set | 1166 | # CONFIG_USB_PRINTER is not set |
| 1167 | # CONFIG_USB_WDM is not set | ||
| 1168 | # CONFIG_USB_TMC is not set | ||
| 1018 | 1169 | ||
| 1019 | # | 1170 | # |
| 1020 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 1171 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; |
| 1021 | # | 1172 | # |
| 1022 | 1173 | ||
| 1023 | # | 1174 | # |
| 1024 | # may also be needed; see USB_STORAGE Help for more information | 1175 | # see USB_STORAGE Help for more information |
| 1025 | # | 1176 | # |
| 1026 | # CONFIG_USB_LIBUSUAL is not set | 1177 | # CONFIG_USB_LIBUSUAL is not set |
| 1027 | 1178 | ||
| @@ -1029,19 +1180,14 @@ CONFIG_USB_DEVICEFS=y | |||
| 1029 | # USB Imaging devices | 1180 | # USB Imaging devices |
| 1030 | # | 1181 | # |
| 1031 | # CONFIG_USB_MDC800 is not set | 1182 | # CONFIG_USB_MDC800 is not set |
| 1032 | # CONFIG_USB_MON is not set | ||
| 1033 | 1183 | ||
| 1034 | # | 1184 | # |
| 1035 | # USB port drivers | 1185 | # USB port drivers |
| 1036 | # | 1186 | # |
| 1037 | |||
| 1038 | # | ||
| 1039 | # USB Serial Converter support | ||
| 1040 | # | ||
| 1041 | CONFIG_USB_SERIAL=m | 1187 | CONFIG_USB_SERIAL=m |
| 1188 | # CONFIG_USB_EZUSB is not set | ||
| 1042 | # CONFIG_USB_SERIAL_GENERIC is not set | 1189 | # CONFIG_USB_SERIAL_GENERIC is not set |
| 1043 | # CONFIG_USB_SERIAL_AIRCABLE is not set | 1190 | # CONFIG_USB_SERIAL_AIRCABLE is not set |
| 1044 | # CONFIG_USB_SERIAL_AIRPRIME is not set | ||
| 1045 | # CONFIG_USB_SERIAL_ARK3116 is not set | 1191 | # CONFIG_USB_SERIAL_ARK3116 is not set |
| 1046 | # CONFIG_USB_SERIAL_BELKIN is not set | 1192 | # CONFIG_USB_SERIAL_BELKIN is not set |
| 1047 | # CONFIG_USB_SERIAL_CH341 is not set | 1193 | # CONFIG_USB_SERIAL_CH341 is not set |
| @@ -1059,6 +1205,7 @@ CONFIG_USB_SERIAL=m | |||
| 1059 | # CONFIG_USB_SERIAL_EDGEPORT_TI is not set | 1205 | # CONFIG_USB_SERIAL_EDGEPORT_TI is not set |
| 1060 | # CONFIG_USB_SERIAL_GARMIN is not set | 1206 | # CONFIG_USB_SERIAL_GARMIN is not set |
| 1061 | # CONFIG_USB_SERIAL_IPW is not set | 1207 | # CONFIG_USB_SERIAL_IPW is not set |
| 1208 | # CONFIG_USB_SERIAL_IUU is not set | ||
| 1062 | # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set | 1209 | # CONFIG_USB_SERIAL_KEYSPAN_PDA is not set |
| 1063 | # CONFIG_USB_SERIAL_KEYSPAN is not set | 1210 | # CONFIG_USB_SERIAL_KEYSPAN is not set |
| 1064 | # CONFIG_USB_SERIAL_KLSI is not set | 1211 | # CONFIG_USB_SERIAL_KLSI is not set |
| @@ -1066,17 +1213,21 @@ CONFIG_USB_SERIAL=m | |||
| 1066 | # CONFIG_USB_SERIAL_MCT_U232 is not set | 1213 | # CONFIG_USB_SERIAL_MCT_U232 is not set |
| 1067 | # CONFIG_USB_SERIAL_MOS7720 is not set | 1214 | # CONFIG_USB_SERIAL_MOS7720 is not set |
| 1068 | # CONFIG_USB_SERIAL_MOS7840 is not set | 1215 | # CONFIG_USB_SERIAL_MOS7840 is not set |
| 1216 | # CONFIG_USB_SERIAL_MOTOROLA is not set | ||
| 1069 | # CONFIG_USB_SERIAL_NAVMAN is not set | 1217 | # CONFIG_USB_SERIAL_NAVMAN is not set |
| 1070 | # CONFIG_USB_SERIAL_PL2303 is not set | 1218 | # CONFIG_USB_SERIAL_PL2303 is not set |
| 1071 | # CONFIG_USB_SERIAL_OTI6858 is not set | 1219 | # CONFIG_USB_SERIAL_OTI6858 is not set |
| 1220 | # CONFIG_USB_SERIAL_SPCP8X5 is not set | ||
| 1072 | # CONFIG_USB_SERIAL_HP4X is not set | 1221 | # CONFIG_USB_SERIAL_HP4X is not set |
| 1073 | # CONFIG_USB_SERIAL_SAFE is not set | 1222 | # CONFIG_USB_SERIAL_SAFE is not set |
| 1223 | # CONFIG_USB_SERIAL_SIEMENS_MPI is not set | ||
| 1074 | # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set | 1224 | # CONFIG_USB_SERIAL_SIERRAWIRELESS is not set |
| 1075 | # CONFIG_USB_SERIAL_TI is not set | 1225 | # CONFIG_USB_SERIAL_TI is not set |
| 1076 | # CONFIG_USB_SERIAL_CYBERJACK is not set | 1226 | # CONFIG_USB_SERIAL_CYBERJACK is not set |
| 1077 | # CONFIG_USB_SERIAL_XIRCOM is not set | 1227 | # CONFIG_USB_SERIAL_XIRCOM is not set |
| 1078 | # CONFIG_USB_SERIAL_OPTION is not set | 1228 | # CONFIG_USB_SERIAL_OPTION is not set |
| 1079 | # CONFIG_USB_SERIAL_OMNINET is not set | 1229 | # CONFIG_USB_SERIAL_OMNINET is not set |
| 1230 | # CONFIG_USB_SERIAL_OPTICON is not set | ||
| 1080 | # CONFIG_USB_SERIAL_DEBUG is not set | 1231 | # CONFIG_USB_SERIAL_DEBUG is not set |
| 1081 | 1232 | ||
| 1082 | # | 1233 | # |
| @@ -1085,7 +1236,7 @@ CONFIG_USB_SERIAL=m | |||
| 1085 | # CONFIG_USB_EMI62 is not set | 1236 | # CONFIG_USB_EMI62 is not set |
| 1086 | # CONFIG_USB_EMI26 is not set | 1237 | # CONFIG_USB_EMI26 is not set |
| 1087 | # CONFIG_USB_ADUTUX is not set | 1238 | # CONFIG_USB_ADUTUX is not set |
| 1088 | # CONFIG_USB_AUERSWALD is not set | 1239 | # CONFIG_USB_SEVSEG is not set |
| 1089 | # CONFIG_USB_RIO500 is not set | 1240 | # CONFIG_USB_RIO500 is not set |
| 1090 | # CONFIG_USB_LEGOTOWER is not set | 1241 | # CONFIG_USB_LEGOTOWER is not set |
| 1091 | # CONFIG_USB_LCD is not set | 1242 | # CONFIG_USB_LCD is not set |
| @@ -1101,30 +1252,29 @@ CONFIG_USB_SERIAL=m | |||
| 1101 | # CONFIG_USB_TRANCEVIBRATOR is not set | 1252 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 1102 | # CONFIG_USB_IOWARRIOR is not set | 1253 | # CONFIG_USB_IOWARRIOR is not set |
| 1103 | # CONFIG_USB_TEST is not set | 1254 | # CONFIG_USB_TEST is not set |
| 1104 | 1255 | # CONFIG_USB_ISIGHTFW is not set | |
| 1105 | # | 1256 | # CONFIG_USB_VST is not set |
| 1106 | # USB DSL modem support | ||
| 1107 | # | ||
| 1108 | |||
| 1109 | # | ||
| 1110 | # USB Gadget Support | ||
| 1111 | # | ||
| 1112 | CONFIG_USB_GADGET=m | 1257 | CONFIG_USB_GADGET=m |
| 1113 | # CONFIG_USB_GADGET_DEBUG is not set | 1258 | # CONFIG_USB_GADGET_DEBUG is not set |
| 1114 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | 1259 | # CONFIG_USB_GADGET_DEBUG_FILES is not set |
| 1115 | # CONFIG_USB_GADGET_DEBUG_FS is not set | 1260 | # CONFIG_USB_GADGET_DEBUG_FS is not set |
| 1261 | CONFIG_USB_GADGET_VBUS_DRAW=2 | ||
| 1116 | CONFIG_USB_GADGET_SELECTED=y | 1262 | CONFIG_USB_GADGET_SELECTED=y |
| 1117 | # CONFIG_USB_GADGET_AMD5536UDC is not set | 1263 | # CONFIG_USB_GADGET_AT91 is not set |
| 1118 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | 1264 | # CONFIG_USB_GADGET_ATMEL_USBA is not set |
| 1119 | # CONFIG_USB_GADGET_FSL_USB2 is not set | 1265 | # CONFIG_USB_GADGET_FSL_USB2 is not set |
| 1120 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1121 | # CONFIG_USB_GADGET_PXA2XX is not set | ||
| 1122 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 1123 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1124 | # CONFIG_USB_GADGET_LH7A40X is not set | 1266 | # CONFIG_USB_GADGET_LH7A40X is not set |
| 1125 | # CONFIG_USB_GADGET_OMAP is not set | 1267 | # CONFIG_USB_GADGET_OMAP is not set |
| 1268 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 1269 | # CONFIG_USB_GADGET_PXA27X is not set | ||
| 1126 | # CONFIG_USB_GADGET_S3C2410 is not set | 1270 | # CONFIG_USB_GADGET_S3C2410 is not set |
| 1127 | # CONFIG_USB_GADGET_AT91 is not set | 1271 | # CONFIG_USB_GADGET_IMX is not set |
| 1272 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 1273 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 1274 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 1275 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 1276 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1277 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1128 | CONFIG_USB_GADGET_DUMMY_HCD=y | 1278 | CONFIG_USB_GADGET_DUMMY_HCD=y |
| 1129 | CONFIG_USB_DUMMY_HCD=m | 1279 | CONFIG_USB_DUMMY_HCD=m |
| 1130 | CONFIG_USB_GADGET_DUALSPEED=y | 1280 | CONFIG_USB_GADGET_DUALSPEED=y |
| @@ -1134,21 +1284,32 @@ CONFIG_USB_GADGET_DUALSPEED=y | |||
| 1134 | # CONFIG_USB_FILE_STORAGE is not set | 1284 | # CONFIG_USB_FILE_STORAGE is not set |
| 1135 | # CONFIG_USB_G_SERIAL is not set | 1285 | # CONFIG_USB_G_SERIAL is not set |
| 1136 | # CONFIG_USB_MIDI_GADGET is not set | 1286 | # CONFIG_USB_MIDI_GADGET is not set |
| 1287 | # CONFIG_USB_G_PRINTER is not set | ||
| 1288 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
| 1289 | |||
| 1290 | # | ||
| 1291 | # OTG and related infrastructure | ||
| 1292 | # | ||
| 1293 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1137 | CONFIG_MMC=y | 1294 | CONFIG_MMC=y |
| 1138 | # CONFIG_MMC_DEBUG is not set | 1295 | # CONFIG_MMC_DEBUG is not set |
| 1139 | # CONFIG_MMC_UNSAFE_RESUME is not set | 1296 | # CONFIG_MMC_UNSAFE_RESUME is not set |
| 1140 | 1297 | ||
| 1141 | # | 1298 | # |
| 1142 | # MMC/SD Card Drivers | 1299 | # MMC/SD/SDIO Card Drivers |
| 1143 | # | 1300 | # |
| 1144 | CONFIG_MMC_BLOCK=y | 1301 | CONFIG_MMC_BLOCK=y |
| 1145 | CONFIG_MMC_BLOCK_BOUNCE=y | 1302 | CONFIG_MMC_BLOCK_BOUNCE=y |
| 1146 | # CONFIG_SDIO_UART is not set | 1303 | # CONFIG_SDIO_UART is not set |
| 1304 | # CONFIG_MMC_TEST is not set | ||
| 1147 | 1305 | ||
| 1148 | # | 1306 | # |
| 1149 | # MMC/SD Host Controller Drivers | 1307 | # MMC/SD/SDIO Host Controller Drivers |
| 1150 | # | 1308 | # |
| 1151 | # CONFIG_MMC_PXA is not set | 1309 | # CONFIG_MMC_PXA is not set |
| 1310 | # CONFIG_MMC_SDHCI is not set | ||
| 1311 | # CONFIG_MEMSTICK is not set | ||
| 1312 | # CONFIG_ACCESSIBILITY is not set | ||
| 1152 | CONFIG_NEW_LEDS=y | 1313 | CONFIG_NEW_LEDS=y |
| 1153 | # CONFIG_LEDS_CLASS is not set | 1314 | # CONFIG_LEDS_CLASS is not set |
| 1154 | 1315 | ||
| @@ -1163,6 +1324,8 @@ CONFIG_LEDS_TRIGGERS=y | |||
| 1163 | CONFIG_LEDS_TRIGGER_TIMER=y | 1324 | CONFIG_LEDS_TRIGGER_TIMER=y |
| 1164 | # CONFIG_LEDS_TRIGGER_IDE_DISK is not set | 1325 | # CONFIG_LEDS_TRIGGER_IDE_DISK is not set |
| 1165 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | 1326 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y |
| 1327 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 1328 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | ||
| 1166 | CONFIG_RTC_LIB=y | 1329 | CONFIG_RTC_LIB=y |
| 1167 | CONFIG_RTC_CLASS=y | 1330 | CONFIG_RTC_CLASS=y |
| 1168 | # CONFIG_RTC_HCTOSYS is not set | 1331 | # CONFIG_RTC_HCTOSYS is not set |
| @@ -1190,6 +1353,9 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1190 | # CONFIG_RTC_DRV_PCF8563 is not set | 1353 | # CONFIG_RTC_DRV_PCF8563 is not set |
| 1191 | CONFIG_RTC_DRV_PCF8583=m | 1354 | CONFIG_RTC_DRV_PCF8583=m |
| 1192 | # CONFIG_RTC_DRV_M41T80 is not set | 1355 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1356 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1357 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1358 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1193 | 1359 | ||
| 1194 | # | 1360 | # |
| 1195 | # SPI RTC drivers | 1361 | # SPI RTC drivers |
| @@ -1199,36 +1365,45 @@ CONFIG_RTC_DRV_PCF8583=m | |||
| 1199 | # Platform RTC drivers | 1365 | # Platform RTC drivers |
| 1200 | # | 1366 | # |
| 1201 | # CONFIG_RTC_DRV_CMOS is not set | 1367 | # CONFIG_RTC_DRV_CMOS is not set |
| 1368 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1369 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1202 | # CONFIG_RTC_DRV_DS1553 is not set | 1370 | # CONFIG_RTC_DRV_DS1553 is not set |
| 1203 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1204 | # CONFIG_RTC_DRV_DS1742 is not set | 1371 | # CONFIG_RTC_DRV_DS1742 is not set |
| 1372 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1205 | # CONFIG_RTC_DRV_M48T86 is not set | 1373 | # CONFIG_RTC_DRV_M48T86 is not set |
| 1374 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1206 | # CONFIG_RTC_DRV_M48T59 is not set | 1375 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1376 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1207 | # CONFIG_RTC_DRV_V3020 is not set | 1377 | # CONFIG_RTC_DRV_V3020 is not set |
| 1208 | 1378 | ||
| 1209 | # | 1379 | # |
| 1210 | # on-CPU RTC drivers | 1380 | # on-CPU RTC drivers |
| 1211 | # | 1381 | # |
| 1212 | # CONFIG_RTC_DRV_SA1100 is not set | 1382 | # CONFIG_RTC_DRV_SA1100 is not set |
| 1383 | # CONFIG_RTC_DRV_PXA is not set | ||
| 1384 | # CONFIG_DMADEVICES is not set | ||
| 1385 | # CONFIG_REGULATOR is not set | ||
| 1386 | # CONFIG_UIO is not set | ||
| 1387 | # CONFIG_STAGING is not set | ||
| 1213 | 1388 | ||
| 1214 | # | 1389 | # |
| 1215 | # File systems | 1390 | # File systems |
| 1216 | # | 1391 | # |
| 1217 | # CONFIG_EXT2_FS is not set | 1392 | # CONFIG_EXT2_FS is not set |
| 1218 | # CONFIG_EXT3_FS is not set | 1393 | # CONFIG_EXT3_FS is not set |
| 1219 | # CONFIG_EXT4DEV_FS is not set | 1394 | # CONFIG_EXT4_FS is not set |
| 1220 | # CONFIG_REISERFS_FS is not set | 1395 | # CONFIG_REISERFS_FS is not set |
| 1221 | # CONFIG_JFS_FS is not set | 1396 | # CONFIG_JFS_FS is not set |
| 1222 | CONFIG_FS_POSIX_ACL=y | 1397 | CONFIG_FS_POSIX_ACL=y |
| 1398 | CONFIG_FILE_LOCKING=y | ||
| 1223 | # CONFIG_XFS_FS is not set | 1399 | # CONFIG_XFS_FS is not set |
| 1224 | # CONFIG_GFS2_FS is not set | 1400 | # CONFIG_GFS2_FS is not set |
| 1225 | # CONFIG_OCFS2_FS is not set | 1401 | # CONFIG_OCFS2_FS is not set |
| 1226 | # CONFIG_MINIX_FS is not set | 1402 | # CONFIG_BTRFS_FS is not set |
| 1227 | # CONFIG_ROMFS_FS is not set | 1403 | CONFIG_DNOTIFY=y |
| 1228 | CONFIG_INOTIFY=y | 1404 | CONFIG_INOTIFY=y |
| 1229 | CONFIG_INOTIFY_USER=y | 1405 | CONFIG_INOTIFY_USER=y |
| 1230 | # CONFIG_QUOTA is not set | 1406 | # CONFIG_QUOTA is not set |
| 1231 | CONFIG_DNOTIFY=y | ||
| 1232 | # CONFIG_AUTOFS_FS is not set | 1407 | # CONFIG_AUTOFS_FS is not set |
| 1233 | CONFIG_AUTOFS4_FS=y | 1408 | CONFIG_AUTOFS4_FS=y |
| 1234 | # CONFIG_FUSE_FS is not set | 1409 | # CONFIG_FUSE_FS is not set |
| @@ -1254,15 +1429,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15" | |||
| 1254 | # | 1429 | # |
| 1255 | CONFIG_PROC_FS=y | 1430 | CONFIG_PROC_FS=y |
| 1256 | CONFIG_PROC_SYSCTL=y | 1431 | CONFIG_PROC_SYSCTL=y |
| 1432 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1257 | CONFIG_SYSFS=y | 1433 | CONFIG_SYSFS=y |
| 1258 | CONFIG_TMPFS=y | 1434 | CONFIG_TMPFS=y |
| 1259 | # CONFIG_TMPFS_POSIX_ACL is not set | 1435 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 1260 | # CONFIG_HUGETLB_PAGE is not set | 1436 | # CONFIG_HUGETLB_PAGE is not set |
| 1261 | CONFIG_CONFIGFS_FS=y | 1437 | CONFIG_CONFIGFS_FS=y |
| 1262 | 1438 | CONFIG_MISC_FILESYSTEMS=y | |
| 1263 | # | ||
| 1264 | # Miscellaneous filesystems | ||
| 1265 | # | ||
| 1266 | # CONFIG_ADFS_FS is not set | 1439 | # CONFIG_ADFS_FS is not set |
| 1267 | # CONFIG_AFFS_FS is not set | 1440 | # CONFIG_AFFS_FS is not set |
| 1268 | # CONFIG_ECRYPT_FS is not set | 1441 | # CONFIG_ECRYPT_FS is not set |
| @@ -1283,9 +1456,13 @@ CONFIG_JFFS2_ZLIB=y | |||
| 1283 | CONFIG_JFFS2_RTIME=y | 1456 | CONFIG_JFFS2_RTIME=y |
| 1284 | # CONFIG_JFFS2_RUBIN is not set | 1457 | # CONFIG_JFFS2_RUBIN is not set |
| 1285 | # CONFIG_CRAMFS is not set | 1458 | # CONFIG_CRAMFS is not set |
| 1459 | # CONFIG_SQUASHFS is not set | ||
| 1286 | # CONFIG_VXFS_FS is not set | 1460 | # CONFIG_VXFS_FS is not set |
| 1461 | # CONFIG_MINIX_FS is not set | ||
| 1462 | # CONFIG_OMFS_FS is not set | ||
| 1287 | # CONFIG_HPFS_FS is not set | 1463 | # CONFIG_HPFS_FS is not set |
| 1288 | # CONFIG_QNX4FS_FS is not set | 1464 | # CONFIG_QNX4FS_FS is not set |
| 1465 | # CONFIG_ROMFS_FS is not set | ||
| 1289 | # CONFIG_SYSV_FS is not set | 1466 | # CONFIG_SYSV_FS is not set |
| 1290 | # CONFIG_UFS_FS is not set | 1467 | # CONFIG_UFS_FS is not set |
| 1291 | CONFIG_NETWORK_FILESYSTEMS=y | 1468 | CONFIG_NETWORK_FILESYSTEMS=y |
| @@ -1293,20 +1470,18 @@ CONFIG_NFS_FS=y | |||
| 1293 | CONFIG_NFS_V3=y | 1470 | CONFIG_NFS_V3=y |
| 1294 | # CONFIG_NFS_V3_ACL is not set | 1471 | # CONFIG_NFS_V3_ACL is not set |
| 1295 | CONFIG_NFS_V4=y | 1472 | CONFIG_NFS_V4=y |
| 1296 | # CONFIG_NFS_DIRECTIO is not set | 1473 | CONFIG_ROOT_NFS=y |
| 1297 | CONFIG_NFSD=y | 1474 | CONFIG_NFSD=y |
| 1298 | CONFIG_NFSD_V3=y | 1475 | CONFIG_NFSD_V3=y |
| 1299 | # CONFIG_NFSD_V3_ACL is not set | 1476 | # CONFIG_NFSD_V3_ACL is not set |
| 1300 | CONFIG_NFSD_V4=y | 1477 | CONFIG_NFSD_V4=y |
| 1301 | CONFIG_NFSD_TCP=y | ||
| 1302 | CONFIG_ROOT_NFS=y | ||
| 1303 | CONFIG_LOCKD=y | 1478 | CONFIG_LOCKD=y |
| 1304 | CONFIG_LOCKD_V4=y | 1479 | CONFIG_LOCKD_V4=y |
| 1305 | CONFIG_EXPORTFS=y | 1480 | CONFIG_EXPORTFS=y |
| 1306 | CONFIG_NFS_COMMON=y | 1481 | CONFIG_NFS_COMMON=y |
| 1307 | CONFIG_SUNRPC=y | 1482 | CONFIG_SUNRPC=y |
| 1308 | CONFIG_SUNRPC_GSS=y | 1483 | CONFIG_SUNRPC_GSS=y |
| 1309 | # CONFIG_SUNRPC_BIND34 is not set | 1484 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 1310 | CONFIG_RPCSEC_GSS_KRB5=y | 1485 | CONFIG_RPCSEC_GSS_KRB5=y |
| 1311 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1486 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1312 | # CONFIG_SMB_FS is not set | 1487 | # CONFIG_SMB_FS is not set |
| @@ -1361,9 +1536,6 @@ CONFIG_NLS_ISO8859_15=m | |||
| 1361 | # CONFIG_NLS_KOI8_U is not set | 1536 | # CONFIG_NLS_KOI8_U is not set |
| 1362 | CONFIG_NLS_UTF8=m | 1537 | CONFIG_NLS_UTF8=m |
| 1363 | # CONFIG_DLM is not set | 1538 | # CONFIG_DLM is not set |
| 1364 | CONFIG_INSTRUMENTATION=y | ||
| 1365 | # CONFIG_PROFILING is not set | ||
| 1366 | # CONFIG_MARKERS is not set | ||
| 1367 | 1539 | ||
| 1368 | # | 1540 | # |
| 1369 | # Kernel hacking | 1541 | # Kernel hacking |
| @@ -1371,6 +1543,7 @@ CONFIG_INSTRUMENTATION=y | |||
| 1371 | CONFIG_PRINTK_TIME=y | 1543 | CONFIG_PRINTK_TIME=y |
| 1372 | CONFIG_ENABLE_WARN_DEPRECATED=y | 1544 | CONFIG_ENABLE_WARN_DEPRECATED=y |
| 1373 | CONFIG_ENABLE_MUST_CHECK=y | 1545 | CONFIG_ENABLE_MUST_CHECK=y |
| 1546 | CONFIG_FRAME_WARN=1024 | ||
| 1374 | CONFIG_MAGIC_SYSRQ=y | 1547 | CONFIG_MAGIC_SYSRQ=y |
| 1375 | # CONFIG_UNUSED_SYMBOLS is not set | 1548 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1376 | CONFIG_DEBUG_FS=y | 1549 | CONFIG_DEBUG_FS=y |
| @@ -1378,9 +1551,12 @@ CONFIG_DEBUG_FS=y | |||
| 1378 | CONFIG_DEBUG_KERNEL=y | 1551 | CONFIG_DEBUG_KERNEL=y |
| 1379 | # CONFIG_DEBUG_SHIRQ is not set | 1552 | # CONFIG_DEBUG_SHIRQ is not set |
| 1380 | CONFIG_DETECT_SOFTLOCKUP=y | 1553 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1554 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1555 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1381 | CONFIG_SCHED_DEBUG=y | 1556 | CONFIG_SCHED_DEBUG=y |
| 1382 | # CONFIG_SCHEDSTATS is not set | 1557 | # CONFIG_SCHEDSTATS is not set |
| 1383 | # CONFIG_TIMER_STATS is not set | 1558 | # CONFIG_TIMER_STATS is not set |
| 1559 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1384 | # CONFIG_DEBUG_SLAB is not set | 1560 | # CONFIG_DEBUG_SLAB is not set |
| 1385 | CONFIG_DEBUG_PREEMPT=y | 1561 | CONFIG_DEBUG_PREEMPT=y |
| 1386 | # CONFIG_DEBUG_RT_MUTEXES is not set | 1562 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| @@ -1396,16 +1572,40 @@ CONFIG_DEBUG_PREEMPT=y | |||
| 1396 | CONFIG_DEBUG_BUGVERBOSE=y | 1572 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1397 | CONFIG_DEBUG_INFO=y | 1573 | CONFIG_DEBUG_INFO=y |
| 1398 | # CONFIG_DEBUG_VM is not set | 1574 | # CONFIG_DEBUG_VM is not set |
| 1575 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1576 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1399 | # CONFIG_DEBUG_LIST is not set | 1577 | # CONFIG_DEBUG_LIST is not set |
| 1400 | # CONFIG_DEBUG_SG is not set | 1578 | # CONFIG_DEBUG_SG is not set |
| 1579 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1401 | CONFIG_FRAME_POINTER=y | 1580 | CONFIG_FRAME_POINTER=y |
| 1402 | CONFIG_FORCED_INLINING=y | ||
| 1403 | # CONFIG_BOOT_PRINTK_DELAY is not set | 1581 | # CONFIG_BOOT_PRINTK_DELAY is not set |
| 1404 | # CONFIG_RCU_TORTURE_TEST is not set | 1582 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1583 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1584 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1585 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1405 | # CONFIG_FAULT_INJECTION is not set | 1586 | # CONFIG_FAULT_INJECTION is not set |
| 1587 | # CONFIG_LATENCYTOP is not set | ||
| 1588 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1589 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1590 | |||
| 1591 | # | ||
| 1592 | # Tracers | ||
| 1593 | # | ||
| 1594 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1595 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1596 | # CONFIG_PREEMPT_TRACER is not set | ||
| 1597 | # CONFIG_SCHED_TRACER is not set | ||
| 1598 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1599 | # CONFIG_BOOT_TRACER is not set | ||
| 1600 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1601 | # CONFIG_STACK_TRACER is not set | ||
| 1602 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1406 | # CONFIG_SAMPLES is not set | 1603 | # CONFIG_SAMPLES is not set |
| 1604 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1605 | # CONFIG_KGDB is not set | ||
| 1407 | CONFIG_DEBUG_USER=y | 1606 | CONFIG_DEBUG_USER=y |
| 1408 | CONFIG_DEBUG_ERRORS=y | 1607 | CONFIG_DEBUG_ERRORS=y |
| 1608 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1409 | CONFIG_DEBUG_LL=y | 1609 | CONFIG_DEBUG_LL=y |
| 1410 | # CONFIG_DEBUG_ICEDCC is not set | 1610 | # CONFIG_DEBUG_ICEDCC is not set |
| 1411 | 1611 | ||
| @@ -1415,58 +1615,114 @@ CONFIG_DEBUG_LL=y | |||
| 1415 | CONFIG_KEYS=y | 1615 | CONFIG_KEYS=y |
| 1416 | CONFIG_KEYS_DEBUG_PROC_KEYS=y | 1616 | CONFIG_KEYS_DEBUG_PROC_KEYS=y |
| 1417 | CONFIG_SECURITY=y | 1617 | CONFIG_SECURITY=y |
| 1618 | # CONFIG_SECURITYFS is not set | ||
| 1418 | # CONFIG_SECURITY_NETWORK is not set | 1619 | # CONFIG_SECURITY_NETWORK is not set |
| 1419 | CONFIG_SECURITY_CAPABILITIES=y | 1620 | # CONFIG_SECURITY_PATH is not set |
| 1420 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | 1621 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1421 | # CONFIG_SECURITY_ROOTPLUG is not set | 1622 | # CONFIG_SECURITY_ROOTPLUG is not set |
| 1623 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 | ||
| 1422 | CONFIG_CRYPTO=y | 1624 | CONFIG_CRYPTO=y |
| 1625 | |||
| 1626 | # | ||
| 1627 | # Crypto core or helper | ||
| 1628 | # | ||
| 1629 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1423 | CONFIG_CRYPTO_ALGAPI=y | 1630 | CONFIG_CRYPTO_ALGAPI=y |
| 1631 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1632 | CONFIG_CRYPTO_AEAD2=y | ||
| 1424 | CONFIG_CRYPTO_BLKCIPHER=y | 1633 | CONFIG_CRYPTO_BLKCIPHER=y |
| 1634 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1635 | CONFIG_CRYPTO_HASH=y | ||
| 1636 | CONFIG_CRYPTO_HASH2=y | ||
| 1637 | CONFIG_CRYPTO_RNG2=y | ||
| 1425 | CONFIG_CRYPTO_MANAGER=y | 1638 | CONFIG_CRYPTO_MANAGER=y |
| 1639 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1640 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1641 | # CONFIG_CRYPTO_NULL is not set | ||
| 1642 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1643 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1644 | # CONFIG_CRYPTO_TEST is not set | ||
| 1645 | |||
| 1646 | # | ||
| 1647 | # Authenticated Encryption with Associated Data | ||
| 1648 | # | ||
| 1649 | # CONFIG_CRYPTO_CCM is not set | ||
| 1650 | # CONFIG_CRYPTO_GCM is not set | ||
| 1651 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1652 | |||
| 1653 | # | ||
| 1654 | # Block modes | ||
| 1655 | # | ||
| 1656 | CONFIG_CRYPTO_CBC=y | ||
| 1657 | # CONFIG_CRYPTO_CTR is not set | ||
| 1658 | # CONFIG_CRYPTO_CTS is not set | ||
| 1659 | CONFIG_CRYPTO_ECB=y | ||
| 1660 | # CONFIG_CRYPTO_LRW is not set | ||
| 1661 | CONFIG_CRYPTO_PCBC=m | ||
| 1662 | # CONFIG_CRYPTO_XTS is not set | ||
| 1663 | |||
| 1664 | # | ||
| 1665 | # Hash modes | ||
| 1666 | # | ||
| 1426 | # CONFIG_CRYPTO_HMAC is not set | 1667 | # CONFIG_CRYPTO_HMAC is not set |
| 1427 | # CONFIG_CRYPTO_XCBC is not set | 1668 | # CONFIG_CRYPTO_XCBC is not set |
| 1428 | # CONFIG_CRYPTO_NULL is not set | 1669 | |
| 1670 | # | ||
| 1671 | # Digest | ||
| 1672 | # | ||
| 1673 | CONFIG_CRYPTO_CRC32C=y | ||
| 1429 | # CONFIG_CRYPTO_MD4 is not set | 1674 | # CONFIG_CRYPTO_MD4 is not set |
| 1430 | CONFIG_CRYPTO_MD5=y | 1675 | CONFIG_CRYPTO_MD5=y |
| 1676 | CONFIG_CRYPTO_MICHAEL_MIC=y | ||
| 1677 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1678 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1679 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1680 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1431 | CONFIG_CRYPTO_SHA1=m | 1681 | CONFIG_CRYPTO_SHA1=m |
| 1432 | CONFIG_CRYPTO_SHA256=m | 1682 | CONFIG_CRYPTO_SHA256=m |
| 1433 | CONFIG_CRYPTO_SHA512=m | 1683 | CONFIG_CRYPTO_SHA512=m |
| 1434 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1435 | # CONFIG_CRYPTO_TGR192 is not set | 1684 | # CONFIG_CRYPTO_TGR192 is not set |
| 1436 | # CONFIG_CRYPTO_GF128MUL is not set | 1685 | # CONFIG_CRYPTO_WP512 is not set |
| 1437 | CONFIG_CRYPTO_ECB=y | 1686 | |
| 1438 | CONFIG_CRYPTO_CBC=y | 1687 | # |
| 1439 | CONFIG_CRYPTO_PCBC=m | 1688 | # Ciphers |
| 1440 | # CONFIG_CRYPTO_LRW is not set | 1689 | # |
| 1441 | # CONFIG_CRYPTO_XTS is not set | 1690 | CONFIG_CRYPTO_AES=y |
| 1442 | # CONFIG_CRYPTO_CRYPTD is not set | 1691 | # CONFIG_CRYPTO_ANUBIS is not set |
| 1443 | CONFIG_CRYPTO_DES=y | 1692 | CONFIG_CRYPTO_ARC4=y |
| 1444 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1445 | # CONFIG_CRYPTO_BLOWFISH is not set | 1693 | # CONFIG_CRYPTO_BLOWFISH is not set |
| 1446 | # CONFIG_CRYPTO_TWOFISH is not set | 1694 | # CONFIG_CRYPTO_CAMELLIA is not set |
| 1447 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1448 | CONFIG_CRYPTO_AES=m | ||
| 1449 | # CONFIG_CRYPTO_CAST5 is not set | 1695 | # CONFIG_CRYPTO_CAST5 is not set |
| 1450 | # CONFIG_CRYPTO_CAST6 is not set | 1696 | # CONFIG_CRYPTO_CAST6 is not set |
| 1451 | # CONFIG_CRYPTO_TEA is not set | 1697 | CONFIG_CRYPTO_DES=y |
| 1452 | CONFIG_CRYPTO_ARC4=y | 1698 | # CONFIG_CRYPTO_FCRYPT is not set |
| 1453 | # CONFIG_CRYPTO_KHAZAD is not set | 1699 | # CONFIG_CRYPTO_KHAZAD is not set |
| 1454 | # CONFIG_CRYPTO_ANUBIS is not set | 1700 | # CONFIG_CRYPTO_SALSA20 is not set |
| 1455 | # CONFIG_CRYPTO_SEED is not set | 1701 | # CONFIG_CRYPTO_SEED is not set |
| 1702 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1703 | # CONFIG_CRYPTO_TEA is not set | ||
| 1704 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1705 | |||
| 1706 | # | ||
| 1707 | # Compression | ||
| 1708 | # | ||
| 1456 | CONFIG_CRYPTO_DEFLATE=m | 1709 | CONFIG_CRYPTO_DEFLATE=m |
| 1457 | CONFIG_CRYPTO_MICHAEL_MIC=m | 1710 | # CONFIG_CRYPTO_LZO is not set |
| 1458 | CONFIG_CRYPTO_CRC32C=y | 1711 | |
| 1459 | # CONFIG_CRYPTO_CAMELLIA is not set | 1712 | # |
| 1460 | # CONFIG_CRYPTO_TEST is not set | 1713 | # Random Number Generation |
| 1461 | # CONFIG_CRYPTO_AUTHENC is not set | 1714 | # |
| 1715 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1462 | CONFIG_CRYPTO_HW=y | 1716 | CONFIG_CRYPTO_HW=y |
| 1463 | 1717 | ||
| 1464 | # | 1718 | # |
| 1465 | # Library routines | 1719 | # Library routines |
| 1466 | # | 1720 | # |
| 1467 | CONFIG_BITREVERSE=y | 1721 | CONFIG_BITREVERSE=y |
| 1722 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1468 | CONFIG_CRC_CCITT=y | 1723 | CONFIG_CRC_CCITT=y |
| 1469 | CONFIG_CRC16=y | 1724 | CONFIG_CRC16=y |
| 1725 | # CONFIG_CRC_T10DIF is not set | ||
| 1470 | # CONFIG_CRC_ITU_T is not set | 1726 | # CONFIG_CRC_ITU_T is not set |
| 1471 | CONFIG_CRC32=y | 1727 | CONFIG_CRC32=y |
| 1472 | # CONFIG_CRC7 is not set | 1728 | # CONFIG_CRC7 is not set |
diff --git a/arch/arm/configs/colibri_pxa300_defconfig b/arch/arm/configs/colibri_pxa300_defconfig new file mode 100644 index 000000000000..4774a36fa740 --- /dev/null +++ b/arch/arm/configs/colibri_pxa300_defconfig | |||
| @@ -0,0 +1,1156 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.29-rc8 | ||
| 4 | # Fri Mar 13 16:13:20 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_ARCH_MTD_XIP=y | ||
| 26 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 27 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 28 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 29 | |||
| 30 | # | ||
| 31 | # General setup | ||
| 32 | # | ||
| 33 | CONFIG_EXPERIMENTAL=y | ||
| 34 | CONFIG_BROKEN_ON_SMP=y | ||
| 35 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 36 | CONFIG_LOCALVERSION="" | ||
| 37 | CONFIG_LOCALVERSION_AUTO=y | ||
| 38 | CONFIG_SWAP=y | ||
| 39 | # CONFIG_SYSVIPC is not set | ||
| 40 | # CONFIG_POSIX_MQUEUE is not set | ||
| 41 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 42 | # CONFIG_TASKSTATS is not set | ||
| 43 | # CONFIG_AUDIT is not set | ||
| 44 | |||
| 45 | # | ||
| 46 | # RCU Subsystem | ||
| 47 | # | ||
| 48 | CONFIG_CLASSIC_RCU=y | ||
| 49 | # CONFIG_TREE_RCU is not set | ||
| 50 | # CONFIG_PREEMPT_RCU is not set | ||
| 51 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 52 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 53 | # CONFIG_IKCONFIG is not set | ||
| 54 | CONFIG_LOG_BUF_SHIFT=17 | ||
| 55 | # CONFIG_GROUP_SCHED is not set | ||
| 56 | # CONFIG_CGROUPS is not set | ||
| 57 | # CONFIG_SYSFS_DEPRECATED_V2 is not set | ||
| 58 | # CONFIG_RELAY is not set | ||
| 59 | CONFIG_NAMESPACES=y | ||
| 60 | # CONFIG_UTS_NS is not set | ||
| 61 | # CONFIG_USER_NS is not set | ||
| 62 | # CONFIG_PID_NS is not set | ||
| 63 | # CONFIG_NET_NS is not set | ||
| 64 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 65 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 66 | CONFIG_SYSCTL=y | ||
| 67 | CONFIG_ANON_INODES=y | ||
| 68 | # CONFIG_EMBEDDED is not set | ||
| 69 | CONFIG_UID16=y | ||
| 70 | CONFIG_SYSCTL_SYSCALL=y | ||
| 71 | CONFIG_KALLSYMS=y | ||
| 72 | # CONFIG_KALLSYMS_ALL is not set | ||
| 73 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 74 | CONFIG_HOTPLUG=y | ||
| 75 | CONFIG_PRINTK=y | ||
| 76 | CONFIG_BUG=y | ||
| 77 | CONFIG_ELF_CORE=y | ||
| 78 | CONFIG_BASE_FULL=y | ||
| 79 | CONFIG_FUTEX=y | ||
| 80 | CONFIG_EPOLL=y | ||
| 81 | CONFIG_SIGNALFD=y | ||
| 82 | CONFIG_TIMERFD=y | ||
| 83 | CONFIG_EVENTFD=y | ||
| 84 | CONFIG_SHMEM=y | ||
| 85 | CONFIG_AIO=y | ||
| 86 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 87 | CONFIG_SLUB_DEBUG=y | ||
| 88 | CONFIG_COMPAT_BRK=y | ||
| 89 | # CONFIG_SLAB is not set | ||
| 90 | CONFIG_SLUB=y | ||
| 91 | # CONFIG_SLOB is not set | ||
| 92 | # CONFIG_PROFILING is not set | ||
| 93 | CONFIG_HAVE_OPROFILE=y | ||
| 94 | # CONFIG_KPROBES is not set | ||
| 95 | CONFIG_HAVE_KPROBES=y | ||
| 96 | CONFIG_HAVE_KRETPROBES=y | ||
| 97 | CONFIG_HAVE_CLK=y | ||
| 98 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 99 | CONFIG_SLABINFO=y | ||
| 100 | CONFIG_RT_MUTEXES=y | ||
| 101 | CONFIG_BASE_SMALL=0 | ||
| 102 | CONFIG_MODULES=y | ||
| 103 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 104 | CONFIG_MODULE_UNLOAD=y | ||
| 105 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 106 | # CONFIG_MODVERSIONS is not set | ||
| 107 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 108 | CONFIG_BLOCK=y | ||
| 109 | # CONFIG_LBD is not set | ||
| 110 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 111 | # CONFIG_BLK_DEV_BSG is not set | ||
| 112 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 113 | |||
| 114 | # | ||
| 115 | # IO Schedulers | ||
| 116 | # | ||
| 117 | CONFIG_IOSCHED_NOOP=y | ||
| 118 | CONFIG_IOSCHED_AS=y | ||
| 119 | CONFIG_IOSCHED_DEADLINE=y | ||
| 120 | CONFIG_IOSCHED_CFQ=y | ||
| 121 | # CONFIG_DEFAULT_AS is not set | ||
| 122 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 123 | CONFIG_DEFAULT_CFQ=y | ||
| 124 | # CONFIG_DEFAULT_NOOP is not set | ||
| 125 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 126 | # CONFIG_FREEZER is not set | ||
| 127 | |||
| 128 | # | ||
| 129 | # System Type | ||
| 130 | # | ||
| 131 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 132 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 133 | # CONFIG_ARCH_REALVIEW is not set | ||
| 134 | # CONFIG_ARCH_VERSATILE is not set | ||
| 135 | # CONFIG_ARCH_AT91 is not set | ||
| 136 | # CONFIG_ARCH_CLPS711X is not set | ||
| 137 | # CONFIG_ARCH_EBSA110 is not set | ||
| 138 | # CONFIG_ARCH_EP93XX is not set | ||
| 139 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 140 | # CONFIG_ARCH_NETX is not set | ||
| 141 | # CONFIG_ARCH_H720X is not set | ||
| 142 | # CONFIG_ARCH_IMX is not set | ||
| 143 | # CONFIG_ARCH_IOP13XX is not set | ||
| 144 | # CONFIG_ARCH_IOP32X is not set | ||
| 145 | # CONFIG_ARCH_IOP33X is not set | ||
| 146 | # CONFIG_ARCH_IXP23XX is not set | ||
| 147 | # CONFIG_ARCH_IXP2000 is not set | ||
| 148 | # CONFIG_ARCH_IXP4XX is not set | ||
| 149 | # CONFIG_ARCH_L7200 is not set | ||
| 150 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 151 | # CONFIG_ARCH_KS8695 is not set | ||
| 152 | # CONFIG_ARCH_NS9XXX is not set | ||
| 153 | # CONFIG_ARCH_LOKI is not set | ||
| 154 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 155 | # CONFIG_ARCH_MXC is not set | ||
| 156 | # CONFIG_ARCH_ORION5X is not set | ||
| 157 | # CONFIG_ARCH_PNX4008 is not set | ||
| 158 | CONFIG_ARCH_PXA=y | ||
| 159 | # CONFIG_ARCH_RPC is not set | ||
| 160 | # CONFIG_ARCH_SA1100 is not set | ||
| 161 | # CONFIG_ARCH_S3C2410 is not set | ||
| 162 | # CONFIG_ARCH_S3C64XX is not set | ||
| 163 | # CONFIG_ARCH_SHARK is not set | ||
| 164 | # CONFIG_ARCH_LH7A40X is not set | ||
| 165 | # CONFIG_ARCH_DAVINCI is not set | ||
| 166 | # CONFIG_ARCH_OMAP is not set | ||
| 167 | # CONFIG_ARCH_MSM is not set | ||
| 168 | # CONFIG_ARCH_W90X900 is not set | ||
| 169 | |||
| 170 | # | ||
| 171 | # Intel PXA2xx/PXA3xx Implementations | ||
| 172 | # | ||
| 173 | |||
| 174 | # | ||
| 175 | # Supported PXA3xx Processor Variants | ||
| 176 | # | ||
| 177 | CONFIG_CPU_PXA300=y | ||
| 178 | # CONFIG_CPU_PXA310 is not set | ||
| 179 | # CONFIG_CPU_PXA320 is not set | ||
| 180 | # CONFIG_CPU_PXA930 is not set | ||
| 181 | # CONFIG_CPU_PXA935 is not set | ||
| 182 | # CONFIG_ARCH_GUMSTIX is not set | ||
| 183 | # CONFIG_MACH_INTELMOTE2 is not set | ||
| 184 | # CONFIG_ARCH_LUBBOCK is not set | ||
| 185 | # CONFIG_MACH_LOGICPD_PXA270 is not set | ||
| 186 | # CONFIG_MACH_MAINSTONE is not set | ||
| 187 | # CONFIG_MACH_MP900C is not set | ||
| 188 | # CONFIG_ARCH_PXA_IDP is not set | ||
| 189 | # CONFIG_PXA_SHARPSL is not set | ||
| 190 | # CONFIG_ARCH_VIPER is not set | ||
| 191 | # CONFIG_ARCH_PXA_ESERIES is not set | ||
| 192 | # CONFIG_TRIZEPS_PXA is not set | ||
| 193 | # CONFIG_MACH_H5000 is not set | ||
| 194 | # CONFIG_MACH_EM_X270 is not set | ||
| 195 | # CONFIG_MACH_COLIBRI is not set | ||
| 196 | CONFIG_MACH_COLIBRI300=y | ||
| 197 | # CONFIG_MACH_ZYLONITE is not set | ||
| 198 | # CONFIG_MACH_LITTLETON is not set | ||
| 199 | # CONFIG_MACH_RAUMFELD_PROTO is not set | ||
| 200 | # CONFIG_MACH_TAVOREVB is not set | ||
| 201 | # CONFIG_MACH_SAAR is not set | ||
| 202 | # CONFIG_MACH_ARMCORE is not set | ||
| 203 | # CONFIG_MACH_CM_X300 is not set | ||
| 204 | # CONFIG_MACH_MAGICIAN is not set | ||
| 205 | # CONFIG_MACH_MIOA701 is not set | ||
| 206 | # CONFIG_MACH_PCM027 is not set | ||
| 207 | # CONFIG_ARCH_PXA_PALM is not set | ||
| 208 | # CONFIG_PXA_EZX is not set | ||
| 209 | CONFIG_PXA3xx=y | ||
| 210 | # CONFIG_PXA_PWM is not set | ||
| 211 | |||
| 212 | # | ||
| 213 | # Processor Type | ||
| 214 | # | ||
| 215 | CONFIG_CPU_32=y | ||
| 216 | CONFIG_CPU_XSC3=y | ||
| 217 | CONFIG_CPU_32v5=y | ||
| 218 | CONFIG_CPU_ABRT_EV5T=y | ||
| 219 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 220 | CONFIG_CPU_CACHE_VIVT=y | ||
| 221 | CONFIG_CPU_TLB_V4WBI=y | ||
| 222 | CONFIG_CPU_CP15=y | ||
| 223 | CONFIG_CPU_CP15_MMU=y | ||
| 224 | CONFIG_IO_36=y | ||
| 225 | |||
| 226 | # | ||
| 227 | # Processor Features | ||
| 228 | # | ||
| 229 | CONFIG_ARM_THUMB=y | ||
| 230 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 231 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
| 232 | CONFIG_OUTER_CACHE=y | ||
| 233 | CONFIG_CACHE_XSC3L2=y | ||
| 234 | CONFIG_IWMMXT=y | ||
| 235 | CONFIG_COMMON_CLKDEV=y | ||
| 236 | |||
| 237 | # | ||
| 238 | # Bus support | ||
| 239 | # | ||
| 240 | # CONFIG_PCI_SYSCALL is not set | ||
| 241 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 242 | # CONFIG_PCCARD is not set | ||
| 243 | |||
| 244 | # | ||
| 245 | # Kernel Features | ||
| 246 | # | ||
| 247 | CONFIG_TICK_ONESHOT=y | ||
| 248 | # CONFIG_NO_HZ is not set | ||
| 249 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 250 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 251 | CONFIG_VMSPLIT_3G=y | ||
| 252 | # CONFIG_VMSPLIT_2G is not set | ||
| 253 | # CONFIG_VMSPLIT_1G is not set | ||
| 254 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 255 | # CONFIG_PREEMPT is not set | ||
| 256 | CONFIG_HZ=100 | ||
| 257 | CONFIG_AEABI=y | ||
| 258 | CONFIG_OABI_COMPAT=y | ||
| 259 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 260 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 261 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 262 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 263 | CONFIG_FLATMEM_MANUAL=y | ||
| 264 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 265 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 266 | CONFIG_FLATMEM=y | ||
| 267 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 268 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 269 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 270 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 271 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 272 | CONFIG_VIRT_TO_BUS=y | ||
| 273 | CONFIG_UNEVICTABLE_LRU=y | ||
| 274 | CONFIG_ALIGNMENT_TRAP=y | ||
| 275 | |||
| 276 | # | ||
| 277 | # Boot options | ||
| 278 | # | ||
| 279 | CONFIG_ZBOOT_ROM_TEXT=0 | ||
| 280 | CONFIG_ZBOOT_ROM_BSS=0 | ||
| 281 | CONFIG_CMDLINE="console=ttyS0,115200 rw" | ||
| 282 | # CONFIG_XIP_KERNEL is not set | ||
| 283 | # CONFIG_KEXEC is not set | ||
| 284 | |||
| 285 | # | ||
| 286 | # CPU Power Management | ||
| 287 | # | ||
| 288 | # CONFIG_CPU_FREQ is not set | ||
| 289 | CONFIG_CPU_IDLE=y | ||
| 290 | CONFIG_CPU_IDLE_GOV_LADDER=y | ||
| 291 | |||
| 292 | # | ||
| 293 | # Floating point emulation | ||
| 294 | # | ||
| 295 | |||
| 296 | # | ||
| 297 | # At least one emulation must be selected | ||
| 298 | # | ||
| 299 | CONFIG_FPE_NWFPE=y | ||
| 300 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 301 | # CONFIG_FPE_FASTFPE is not set | ||
| 302 | |||
| 303 | # | ||
| 304 | # Userspace binary formats | ||
| 305 | # | ||
| 306 | CONFIG_BINFMT_ELF=y | ||
| 307 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 308 | CONFIG_HAVE_AOUT=y | ||
| 309 | # CONFIG_BINFMT_AOUT is not set | ||
| 310 | # CONFIG_BINFMT_MISC is not set | ||
| 311 | |||
| 312 | # | ||
| 313 | # Power management options | ||
| 314 | # | ||
| 315 | # CONFIG_PM is not set | ||
| 316 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 317 | CONFIG_NET=y | ||
| 318 | |||
| 319 | # | ||
| 320 | # Networking options | ||
| 321 | # | ||
| 322 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 323 | # CONFIG_PACKET is not set | ||
| 324 | CONFIG_UNIX=y | ||
| 325 | CONFIG_XFRM=y | ||
| 326 | # CONFIG_XFRM_USER is not set | ||
| 327 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 328 | # CONFIG_XFRM_MIGRATE is not set | ||
| 329 | # CONFIG_XFRM_STATISTICS is not set | ||
| 330 | # CONFIG_NET_KEY is not set | ||
| 331 | CONFIG_INET=y | ||
| 332 | CONFIG_IP_MULTICAST=y | ||
| 333 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 334 | CONFIG_IP_FIB_HASH=y | ||
| 335 | CONFIG_IP_PNP=y | ||
| 336 | # CONFIG_IP_PNP_DHCP is not set | ||
| 337 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 338 | # CONFIG_IP_PNP_RARP is not set | ||
| 339 | # CONFIG_NET_IPIP is not set | ||
| 340 | # CONFIG_NET_IPGRE is not set | ||
| 341 | # CONFIG_IP_MROUTE is not set | ||
| 342 | # CONFIG_ARPD is not set | ||
| 343 | CONFIG_SYN_COOKIES=y | ||
| 344 | # CONFIG_INET_AH is not set | ||
| 345 | # CONFIG_INET_ESP is not set | ||
| 346 | # CONFIG_INET_IPCOMP is not set | ||
| 347 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 348 | CONFIG_INET_TUNNEL=y | ||
| 349 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 350 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 351 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 352 | # CONFIG_INET_LRO is not set | ||
| 353 | CONFIG_INET_DIAG=y | ||
| 354 | CONFIG_INET_TCP_DIAG=y | ||
| 355 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 356 | CONFIG_TCP_CONG_CUBIC=y | ||
| 357 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 358 | # CONFIG_TCP_MD5SIG is not set | ||
| 359 | CONFIG_IPV6=y | ||
| 360 | # CONFIG_IPV6_PRIVACY is not set | ||
| 361 | # CONFIG_IPV6_ROUTER_PREF is not set | ||
| 362 | # CONFIG_IPV6_OPTIMISTIC_DAD is not set | ||
| 363 | # CONFIG_INET6_AH is not set | ||
| 364 | # CONFIG_INET6_ESP is not set | ||
| 365 | # CONFIG_INET6_IPCOMP is not set | ||
| 366 | # CONFIG_IPV6_MIP6 is not set | ||
| 367 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 368 | # CONFIG_INET6_TUNNEL is not set | ||
| 369 | CONFIG_INET6_XFRM_MODE_TRANSPORT=y | ||
| 370 | CONFIG_INET6_XFRM_MODE_TUNNEL=y | ||
| 371 | CONFIG_INET6_XFRM_MODE_BEET=y | ||
| 372 | # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set | ||
| 373 | CONFIG_IPV6_SIT=y | ||
| 374 | CONFIG_IPV6_NDISC_NODETYPE=y | ||
| 375 | # CONFIG_IPV6_TUNNEL is not set | ||
| 376 | # CONFIG_IPV6_MULTIPLE_TABLES is not set | ||
| 377 | # CONFIG_IPV6_MROUTE is not set | ||
| 378 | # CONFIG_NETWORK_SECMARK is not set | ||
| 379 | # CONFIG_NETFILTER is not set | ||
| 380 | # CONFIG_IP_DCCP is not set | ||
| 381 | # CONFIG_IP_SCTP is not set | ||
| 382 | # CONFIG_TIPC is not set | ||
| 383 | # CONFIG_ATM is not set | ||
| 384 | # CONFIG_BRIDGE is not set | ||
| 385 | # CONFIG_NET_DSA is not set | ||
| 386 | # CONFIG_VLAN_8021Q is not set | ||
| 387 | # CONFIG_DECNET is not set | ||
| 388 | # CONFIG_LLC2 is not set | ||
| 389 | # CONFIG_IPX is not set | ||
| 390 | # CONFIG_ATALK is not set | ||
| 391 | # CONFIG_X25 is not set | ||
| 392 | # CONFIG_LAPB is not set | ||
| 393 | # CONFIG_ECONET is not set | ||
| 394 | # CONFIG_WAN_ROUTER is not set | ||
| 395 | # CONFIG_NET_SCHED is not set | ||
| 396 | # CONFIG_DCB is not set | ||
| 397 | |||
| 398 | # | ||
| 399 | # Network testing | ||
| 400 | # | ||
| 401 | # CONFIG_NET_PKTGEN is not set | ||
| 402 | # CONFIG_HAMRADIO is not set | ||
| 403 | # CONFIG_CAN is not set | ||
| 404 | # CONFIG_IRDA is not set | ||
| 405 | # CONFIG_BT is not set | ||
| 406 | # CONFIG_AF_RXRPC is not set | ||
| 407 | # CONFIG_PHONET is not set | ||
| 408 | # CONFIG_WIRELESS is not set | ||
| 409 | # CONFIG_WIMAX is not set | ||
| 410 | # CONFIG_RFKILL is not set | ||
| 411 | # CONFIG_NET_9P is not set | ||
| 412 | |||
| 413 | # | ||
| 414 | # Device Drivers | ||
| 415 | # | ||
| 416 | |||
| 417 | # | ||
| 418 | # Generic Driver Options | ||
| 419 | # | ||
| 420 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 421 | CONFIG_STANDALONE=y | ||
| 422 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 423 | CONFIG_FW_LOADER=y | ||
| 424 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 425 | CONFIG_EXTRA_FIRMWARE="" | ||
| 426 | # CONFIG_DEBUG_DRIVER is not set | ||
| 427 | # CONFIG_DEBUG_DEVRES is not set | ||
| 428 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 429 | # CONFIG_CONNECTOR is not set | ||
| 430 | # CONFIG_MTD is not set | ||
| 431 | # CONFIG_PARPORT is not set | ||
| 432 | CONFIG_BLK_DEV=y | ||
| 433 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 434 | # CONFIG_BLK_DEV_LOOP is not set | ||
| 435 | # CONFIG_BLK_DEV_NBD is not set | ||
| 436 | # CONFIG_BLK_DEV_UB is not set | ||
| 437 | # CONFIG_BLK_DEV_RAM is not set | ||
| 438 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 439 | # CONFIG_ATA_OVER_ETH is not set | ||
| 440 | # CONFIG_MISC_DEVICES is not set | ||
| 441 | CONFIG_HAVE_IDE=y | ||
| 442 | # CONFIG_IDE is not set | ||
| 443 | |||
| 444 | # | ||
| 445 | # SCSI device support | ||
| 446 | # | ||
| 447 | # CONFIG_RAID_ATTRS is not set | ||
| 448 | CONFIG_SCSI=y | ||
| 449 | CONFIG_SCSI_DMA=y | ||
| 450 | # CONFIG_SCSI_TGT is not set | ||
| 451 | # CONFIG_SCSI_NETLINK is not set | ||
| 452 | CONFIG_SCSI_PROC_FS=y | ||
| 453 | |||
| 454 | # | ||
| 455 | # SCSI support type (disk, tape, CD-ROM) | ||
| 456 | # | ||
| 457 | CONFIG_BLK_DEV_SD=y | ||
| 458 | # CONFIG_CHR_DEV_ST is not set | ||
| 459 | # CONFIG_CHR_DEV_OSST is not set | ||
| 460 | # CONFIG_BLK_DEV_SR is not set | ||
| 461 | CONFIG_CHR_DEV_SG=y | ||
| 462 | # CONFIG_CHR_DEV_SCH is not set | ||
| 463 | |||
| 464 | # | ||
| 465 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 466 | # | ||
| 467 | # CONFIG_SCSI_MULTI_LUN is not set | ||
| 468 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 469 | # CONFIG_SCSI_LOGGING is not set | ||
| 470 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 471 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 472 | |||
| 473 | # | ||
| 474 | # SCSI Transports | ||
| 475 | # | ||
| 476 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 477 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 478 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 479 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 480 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 481 | CONFIG_SCSI_LOWLEVEL=y | ||
| 482 | # CONFIG_ISCSI_TCP is not set | ||
| 483 | # CONFIG_LIBFC is not set | ||
| 484 | # CONFIG_SCSI_DEBUG is not set | ||
| 485 | # CONFIG_SCSI_DH is not set | ||
| 486 | # CONFIG_ATA is not set | ||
| 487 | # CONFIG_MD is not set | ||
| 488 | CONFIG_NETDEVICES=y | ||
| 489 | # CONFIG_DUMMY is not set | ||
| 490 | # CONFIG_BONDING is not set | ||
| 491 | # CONFIG_MACVLAN is not set | ||
| 492 | # CONFIG_EQUALIZER is not set | ||
| 493 | # CONFIG_TUN is not set | ||
| 494 | # CONFIG_VETH is not set | ||
| 495 | # CONFIG_PHYLIB is not set | ||
| 496 | CONFIG_NET_ETHERNET=y | ||
| 497 | CONFIG_MII=y | ||
| 498 | CONFIG_AX88796=y | ||
| 499 | # CONFIG_AX88796_93CX6 is not set | ||
| 500 | # CONFIG_SMC91X is not set | ||
| 501 | # CONFIG_DM9000 is not set | ||
| 502 | # CONFIG_SMC911X is not set | ||
| 503 | # CONFIG_SMSC911X is not set | ||
| 504 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 505 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 506 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 507 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 508 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 509 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 510 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 511 | # CONFIG_B44 is not set | ||
| 512 | # CONFIG_NETDEV_1000 is not set | ||
| 513 | # CONFIG_NETDEV_10000 is not set | ||
| 514 | |||
| 515 | # | ||
| 516 | # Wireless LAN | ||
| 517 | # | ||
| 518 | # CONFIG_WLAN_PRE80211 is not set | ||
| 519 | # CONFIG_WLAN_80211 is not set | ||
| 520 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 521 | |||
| 522 | # | ||
| 523 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 524 | # | ||
| 525 | |||
| 526 | # | ||
| 527 | # USB Network Adapters | ||
| 528 | # | ||
| 529 | # CONFIG_USB_CATC is not set | ||
| 530 | # CONFIG_USB_KAWETH is not set | ||
| 531 | # CONFIG_USB_PEGASUS is not set | ||
| 532 | # CONFIG_USB_RTL8150 is not set | ||
| 533 | # CONFIG_USB_USBNET is not set | ||
| 534 | # CONFIG_WAN is not set | ||
| 535 | # CONFIG_PPP is not set | ||
| 536 | # CONFIG_SLIP is not set | ||
| 537 | # CONFIG_NETCONSOLE is not set | ||
| 538 | # CONFIG_NETPOLL is not set | ||
| 539 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 540 | # CONFIG_ISDN is not set | ||
| 541 | |||
| 542 | # | ||
| 543 | # Input device support | ||
| 544 | # | ||
| 545 | CONFIG_INPUT=y | ||
| 546 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 547 | # CONFIG_INPUT_POLLDEV is not set | ||
| 548 | |||
| 549 | # | ||
| 550 | # Userland interfaces | ||
| 551 | # | ||
| 552 | CONFIG_INPUT_MOUSEDEV=y | ||
| 553 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
| 554 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 555 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 556 | # CONFIG_INPUT_JOYDEV is not set | ||
| 557 | CONFIG_INPUT_EVDEV=y | ||
| 558 | # CONFIG_INPUT_EVBUG is not set | ||
| 559 | |||
| 560 | # | ||
| 561 | # Input Device Drivers | ||
| 562 | # | ||
| 563 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 564 | # CONFIG_INPUT_MOUSE is not set | ||
| 565 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 566 | # CONFIG_INPUT_TABLET is not set | ||
| 567 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 568 | CONFIG_INPUT_MISC=y | ||
| 569 | # CONFIG_INPUT_ATI_REMOTE is not set | ||
| 570 | # CONFIG_INPUT_ATI_REMOTE2 is not set | ||
| 571 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | ||
| 572 | # CONFIG_INPUT_POWERMATE is not set | ||
| 573 | # CONFIG_INPUT_YEALINK is not set | ||
| 574 | # CONFIG_INPUT_CM109 is not set | ||
| 575 | # CONFIG_INPUT_UINPUT is not set | ||
| 576 | CONFIG_INPUT_GPIO_ROTARY_ENCODER=y | ||
| 577 | |||
| 578 | # | ||
| 579 | # Hardware I/O ports | ||
| 580 | # | ||
| 581 | CONFIG_SERIO=y | ||
| 582 | CONFIG_SERIO_SERPORT=y | ||
| 583 | # CONFIG_SERIO_RAW is not set | ||
| 584 | # CONFIG_GAMEPORT is not set | ||
| 585 | |||
| 586 | # | ||
| 587 | # Character devices | ||
| 588 | # | ||
| 589 | CONFIG_VT=y | ||
| 590 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 591 | CONFIG_VT_CONSOLE=y | ||
| 592 | CONFIG_HW_CONSOLE=y | ||
| 593 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 594 | CONFIG_DEVKMEM=y | ||
| 595 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 596 | |||
| 597 | # | ||
| 598 | # Serial drivers | ||
| 599 | # | ||
| 600 | # CONFIG_SERIAL_8250 is not set | ||
| 601 | |||
| 602 | # | ||
| 603 | # Non-8250 serial port support | ||
| 604 | # | ||
| 605 | CONFIG_SERIAL_PXA=y | ||
| 606 | CONFIG_SERIAL_PXA_CONSOLE=y | ||
| 607 | CONFIG_SERIAL_CORE=y | ||
| 608 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 609 | CONFIG_UNIX98_PTYS=y | ||
| 610 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 611 | CONFIG_LEGACY_PTYS=y | ||
| 612 | CONFIG_LEGACY_PTY_COUNT=256 | ||
| 613 | # CONFIG_IPMI_HANDLER is not set | ||
| 614 | CONFIG_HW_RANDOM=y | ||
| 615 | # CONFIG_R3964 is not set | ||
| 616 | # CONFIG_RAW_DRIVER is not set | ||
| 617 | # CONFIG_TCG_TPM is not set | ||
| 618 | # CONFIG_I2C is not set | ||
| 619 | # CONFIG_SPI is not set | ||
| 620 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 621 | CONFIG_GPIOLIB=y | ||
| 622 | CONFIG_DEBUG_GPIO=y | ||
| 623 | # CONFIG_GPIO_SYSFS is not set | ||
| 624 | |||
| 625 | # | ||
| 626 | # Memory mapped GPIO expanders: | ||
| 627 | # | ||
| 628 | |||
| 629 | # | ||
| 630 | # I2C GPIO expanders: | ||
| 631 | # | ||
| 632 | |||
| 633 | # | ||
| 634 | # PCI GPIO expanders: | ||
| 635 | # | ||
| 636 | |||
| 637 | # | ||
| 638 | # SPI GPIO expanders: | ||
| 639 | # | ||
| 640 | # CONFIG_W1 is not set | ||
| 641 | # CONFIG_POWER_SUPPLY is not set | ||
| 642 | # CONFIG_HWMON is not set | ||
| 643 | # CONFIG_THERMAL is not set | ||
| 644 | # CONFIG_THERMAL_HWMON is not set | ||
| 645 | # CONFIG_WATCHDOG is not set | ||
| 646 | CONFIG_SSB_POSSIBLE=y | ||
| 647 | |||
| 648 | # | ||
| 649 | # Sonics Silicon Backplane | ||
| 650 | # | ||
| 651 | # CONFIG_SSB is not set | ||
| 652 | |||
| 653 | # | ||
| 654 | # Multifunction device drivers | ||
| 655 | # | ||
| 656 | # CONFIG_MFD_CORE is not set | ||
| 657 | # CONFIG_MFD_SM501 is not set | ||
| 658 | # CONFIG_MFD_ASIC3 is not set | ||
| 659 | # CONFIG_HTC_EGPIO is not set | ||
| 660 | # CONFIG_HTC_PASIC3 is not set | ||
| 661 | # CONFIG_MFD_TMIO is not set | ||
| 662 | # CONFIG_MFD_T7L66XB is not set | ||
| 663 | # CONFIG_MFD_TC6387XB is not set | ||
| 664 | # CONFIG_MFD_TC6393XB is not set | ||
| 665 | |||
| 666 | # | ||
| 667 | # Multimedia devices | ||
| 668 | # | ||
| 669 | |||
| 670 | # | ||
| 671 | # Multimedia core support | ||
| 672 | # | ||
| 673 | # CONFIG_VIDEO_DEV is not set | ||
| 674 | # CONFIG_DVB_CORE is not set | ||
| 675 | # CONFIG_VIDEO_MEDIA is not set | ||
| 676 | |||
| 677 | # | ||
| 678 | # Multimedia drivers | ||
| 679 | # | ||
| 680 | # CONFIG_DAB is not set | ||
| 681 | |||
| 682 | # | ||
| 683 | # Graphics support | ||
| 684 | # | ||
| 685 | # CONFIG_VGASTATE is not set | ||
| 686 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 687 | CONFIG_FB=y | ||
| 688 | # CONFIG_FIRMWARE_EDID is not set | ||
| 689 | # CONFIG_FB_DDC is not set | ||
| 690 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 691 | CONFIG_FB_CFB_FILLRECT=y | ||
| 692 | CONFIG_FB_CFB_COPYAREA=y | ||
| 693 | CONFIG_FB_CFB_IMAGEBLIT=y | ||
| 694 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 695 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 696 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 697 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 698 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 699 | # CONFIG_FB_SYS_FOPS is not set | ||
| 700 | # CONFIG_FB_SVGALIB is not set | ||
| 701 | # CONFIG_FB_MACMODES is not set | ||
| 702 | # CONFIG_FB_BACKLIGHT is not set | ||
| 703 | # CONFIG_FB_MODE_HELPERS is not set | ||
| 704 | # CONFIG_FB_TILEBLITTING is not set | ||
| 705 | |||
| 706 | # | ||
| 707 | # Frame buffer hardware drivers | ||
| 708 | # | ||
| 709 | # CONFIG_FB_S1D13XXX is not set | ||
| 710 | CONFIG_FB_PXA=y | ||
| 711 | # CONFIG_FB_PXA_OVERLAY is not set | ||
| 712 | # CONFIG_FB_PXA_SMARTPANEL is not set | ||
| 713 | # CONFIG_FB_PXA_PARAMETERS is not set | ||
| 714 | # CONFIG_FB_MBX is not set | ||
| 715 | # CONFIG_FB_W100 is not set | ||
| 716 | # CONFIG_FB_VIRTUAL is not set | ||
| 717 | # CONFIG_FB_METRONOME is not set | ||
| 718 | # CONFIG_FB_MB862XX is not set | ||
| 719 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 720 | # CONFIG_LCD_CLASS_DEVICE is not set | ||
| 721 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | ||
| 722 | # CONFIG_BACKLIGHT_GENERIC is not set | ||
| 723 | |||
| 724 | # | ||
| 725 | # Display device support | ||
| 726 | # | ||
| 727 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 728 | |||
| 729 | # | ||
| 730 | # Console display driver support | ||
| 731 | # | ||
| 732 | # CONFIG_VGA_CONSOLE is not set | ||
| 733 | CONFIG_DUMMY_CONSOLE=y | ||
| 734 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 735 | # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set | ||
| 736 | # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set | ||
| 737 | # CONFIG_FONTS is not set | ||
| 738 | CONFIG_FONT_8x8=y | ||
| 739 | CONFIG_FONT_8x16=y | ||
| 740 | CONFIG_LOGO=y | ||
| 741 | CONFIG_LOGO_LINUX_MONO=y | ||
| 742 | CONFIG_LOGO_LINUX_VGA16=y | ||
| 743 | CONFIG_LOGO_LINUX_CLUT224=y | ||
| 744 | # CONFIG_SOUND is not set | ||
| 745 | # CONFIG_HID_SUPPORT is not set | ||
| 746 | CONFIG_USB_SUPPORT=y | ||
| 747 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 748 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 749 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 750 | CONFIG_USB=y | ||
| 751 | CONFIG_USB_DEBUG=y | ||
| 752 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 753 | |||
| 754 | # | ||
| 755 | # Miscellaneous USB options | ||
| 756 | # | ||
| 757 | CONFIG_USB_DEVICEFS=y | ||
| 758 | CONFIG_USB_DEVICE_CLASS=y | ||
| 759 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 760 | # CONFIG_USB_OTG is not set | ||
| 761 | CONFIG_USB_MON=y | ||
| 762 | # CONFIG_USB_WUSB is not set | ||
| 763 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 764 | |||
| 765 | # | ||
| 766 | # USB Host Controller Drivers | ||
| 767 | # | ||
| 768 | # CONFIG_USB_C67X00_HCD is not set | ||
| 769 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 770 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 771 | # CONFIG_USB_OHCI_HCD is not set | ||
| 772 | # CONFIG_USB_SL811_HCD is not set | ||
| 773 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 774 | # CONFIG_USB_HWA_HCD is not set | ||
| 775 | # CONFIG_USB_MUSB_HDRC is not set | ||
| 776 | |||
| 777 | # | ||
| 778 | # USB Device Class drivers | ||
| 779 | # | ||
| 780 | # CONFIG_USB_ACM is not set | ||
| 781 | # CONFIG_USB_PRINTER is not set | ||
| 782 | # CONFIG_USB_WDM is not set | ||
| 783 | # CONFIG_USB_TMC is not set | ||
| 784 | |||
| 785 | # | ||
| 786 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; | ||
| 787 | # | ||
| 788 | |||
| 789 | # | ||
| 790 | # see USB_STORAGE Help for more information | ||
| 791 | # | ||
| 792 | CONFIG_USB_STORAGE=y | ||
| 793 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 794 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 795 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 796 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 797 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 798 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 799 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 800 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 801 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 802 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 803 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 804 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 805 | # CONFIG_USB_LIBUSUAL is not set | ||
| 806 | |||
| 807 | # | ||
| 808 | # USB Imaging devices | ||
| 809 | # | ||
| 810 | # CONFIG_USB_MDC800 is not set | ||
| 811 | # CONFIG_USB_MICROTEK is not set | ||
| 812 | |||
| 813 | # | ||
| 814 | # USB port drivers | ||
| 815 | # | ||
| 816 | # CONFIG_USB_SERIAL is not set | ||
| 817 | |||
| 818 | # | ||
| 819 | # USB Miscellaneous drivers | ||
| 820 | # | ||
| 821 | # CONFIG_USB_EMI62 is not set | ||
| 822 | # CONFIG_USB_EMI26 is not set | ||
| 823 | # CONFIG_USB_ADUTUX is not set | ||
| 824 | # CONFIG_USB_SEVSEG is not set | ||
| 825 | # CONFIG_USB_RIO500 is not set | ||
| 826 | # CONFIG_USB_LEGOTOWER is not set | ||
| 827 | # CONFIG_USB_LCD is not set | ||
| 828 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 829 | # CONFIG_USB_LED is not set | ||
| 830 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 831 | # CONFIG_USB_CYTHERM is not set | ||
| 832 | # CONFIG_USB_PHIDGET is not set | ||
| 833 | # CONFIG_USB_IDMOUSE is not set | ||
| 834 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 835 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 836 | # CONFIG_USB_LD is not set | ||
| 837 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 838 | # CONFIG_USB_IOWARRIOR is not set | ||
| 839 | # CONFIG_USB_TEST is not set | ||
| 840 | # CONFIG_USB_ISIGHTFW is not set | ||
| 841 | # CONFIG_USB_VST is not set | ||
| 842 | # CONFIG_USB_GADGET is not set | ||
| 843 | |||
| 844 | # | ||
| 845 | # OTG and related infrastructure | ||
| 846 | # | ||
| 847 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 848 | CONFIG_MMC=y | ||
| 849 | # CONFIG_MMC_DEBUG is not set | ||
| 850 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 851 | |||
| 852 | # | ||
| 853 | # MMC/SD/SDIO Card Drivers | ||
| 854 | # | ||
| 855 | CONFIG_MMC_BLOCK=y | ||
| 856 | # CONFIG_MMC_BLOCK_BOUNCE is not set | ||
| 857 | # CONFIG_SDIO_UART is not set | ||
| 858 | # CONFIG_MMC_TEST is not set | ||
| 859 | |||
| 860 | # | ||
| 861 | # MMC/SD/SDIO Host Controller Drivers | ||
| 862 | # | ||
| 863 | CONFIG_MMC_PXA=y | ||
| 864 | # CONFIG_MMC_SDHCI is not set | ||
| 865 | # CONFIG_MEMSTICK is not set | ||
| 866 | # CONFIG_ACCESSIBILITY is not set | ||
| 867 | # CONFIG_NEW_LEDS is not set | ||
| 868 | CONFIG_RTC_LIB=y | ||
| 869 | # CONFIG_RTC_CLASS is not set | ||
| 870 | # CONFIG_DMADEVICES is not set | ||
| 871 | # CONFIG_REGULATOR is not set | ||
| 872 | # CONFIG_UIO is not set | ||
| 873 | # CONFIG_STAGING is not set | ||
| 874 | |||
| 875 | # | ||
| 876 | # File systems | ||
| 877 | # | ||
| 878 | # CONFIG_EXT2_FS is not set | ||
| 879 | CONFIG_EXT3_FS=y | ||
| 880 | CONFIG_EXT3_FS_XATTR=y | ||
| 881 | # CONFIG_EXT3_FS_POSIX_ACL is not set | ||
| 882 | # CONFIG_EXT3_FS_SECURITY is not set | ||
| 883 | # CONFIG_EXT4_FS is not set | ||
| 884 | CONFIG_JBD=y | ||
| 885 | CONFIG_FS_MBCACHE=y | ||
| 886 | # CONFIG_REISERFS_FS is not set | ||
| 887 | # CONFIG_JFS_FS is not set | ||
| 888 | # CONFIG_FS_POSIX_ACL is not set | ||
| 889 | CONFIG_FILE_LOCKING=y | ||
| 890 | # CONFIG_XFS_FS is not set | ||
| 891 | # CONFIG_OCFS2_FS is not set | ||
| 892 | # CONFIG_BTRFS_FS is not set | ||
| 893 | CONFIG_DNOTIFY=y | ||
| 894 | CONFIG_INOTIFY=y | ||
| 895 | CONFIG_INOTIFY_USER=y | ||
| 896 | # CONFIG_QUOTA is not set | ||
| 897 | # CONFIG_AUTOFS_FS is not set | ||
| 898 | # CONFIG_AUTOFS4_FS is not set | ||
| 899 | # CONFIG_FUSE_FS is not set | ||
| 900 | |||
| 901 | # | ||
| 902 | # CD-ROM/DVD Filesystems | ||
| 903 | # | ||
| 904 | # CONFIG_ISO9660_FS is not set | ||
| 905 | # CONFIG_UDF_FS is not set | ||
| 906 | |||
| 907 | # | ||
| 908 | # DOS/FAT/NT Filesystems | ||
| 909 | # | ||
| 910 | # CONFIG_MSDOS_FS is not set | ||
| 911 | # CONFIG_VFAT_FS is not set | ||
| 912 | # CONFIG_NTFS_FS is not set | ||
| 913 | |||
| 914 | # | ||
| 915 | # Pseudo filesystems | ||
| 916 | # | ||
| 917 | CONFIG_PROC_FS=y | ||
| 918 | CONFIG_PROC_SYSCTL=y | ||
| 919 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 920 | CONFIG_SYSFS=y | ||
| 921 | # CONFIG_TMPFS is not set | ||
| 922 | # CONFIG_HUGETLB_PAGE is not set | ||
| 923 | # CONFIG_CONFIGFS_FS is not set | ||
| 924 | CONFIG_MISC_FILESYSTEMS=y | ||
| 925 | # CONFIG_ADFS_FS is not set | ||
| 926 | # CONFIG_AFFS_FS is not set | ||
| 927 | # CONFIG_HFS_FS is not set | ||
| 928 | # CONFIG_HFSPLUS_FS is not set | ||
| 929 | # CONFIG_BEFS_FS is not set | ||
| 930 | # CONFIG_BFS_FS is not set | ||
| 931 | # CONFIG_EFS_FS is not set | ||
| 932 | # CONFIG_CRAMFS is not set | ||
| 933 | # CONFIG_SQUASHFS is not set | ||
| 934 | # CONFIG_VXFS_FS is not set | ||
| 935 | # CONFIG_MINIX_FS is not set | ||
| 936 | # CONFIG_OMFS_FS is not set | ||
| 937 | # CONFIG_HPFS_FS is not set | ||
| 938 | # CONFIG_QNX4FS_FS is not set | ||
| 939 | # CONFIG_ROMFS_FS is not set | ||
| 940 | # CONFIG_SYSV_FS is not set | ||
| 941 | # CONFIG_UFS_FS is not set | ||
| 942 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 943 | CONFIG_NFS_FS=y | ||
| 944 | CONFIG_NFS_V3=y | ||
| 945 | # CONFIG_NFS_V3_ACL is not set | ||
| 946 | # CONFIG_NFS_V4 is not set | ||
| 947 | CONFIG_ROOT_NFS=y | ||
| 948 | # CONFIG_NFSD is not set | ||
| 949 | CONFIG_LOCKD=y | ||
| 950 | CONFIG_LOCKD_V4=y | ||
| 951 | CONFIG_NFS_COMMON=y | ||
| 952 | CONFIG_SUNRPC=y | ||
| 953 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 954 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 955 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 956 | # CONFIG_SMB_FS is not set | ||
| 957 | # CONFIG_CIFS is not set | ||
| 958 | # CONFIG_NCP_FS is not set | ||
| 959 | # CONFIG_CODA_FS is not set | ||
| 960 | # CONFIG_AFS_FS is not set | ||
| 961 | |||
| 962 | # | ||
| 963 | # Partition Types | ||
| 964 | # | ||
| 965 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 966 | CONFIG_MSDOS_PARTITION=y | ||
| 967 | # CONFIG_NLS is not set | ||
| 968 | # CONFIG_DLM is not set | ||
| 969 | |||
| 970 | # | ||
| 971 | # Kernel hacking | ||
| 972 | # | ||
| 973 | CONFIG_PRINTK_TIME=y | ||
| 974 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 975 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 976 | CONFIG_FRAME_WARN=1024 | ||
| 977 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 978 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 979 | # CONFIG_DEBUG_FS is not set | ||
| 980 | # CONFIG_HEADERS_CHECK is not set | ||
| 981 | CONFIG_DEBUG_KERNEL=y | ||
| 982 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 983 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 984 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 985 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 986 | CONFIG_SCHED_DEBUG=y | ||
| 987 | # CONFIG_SCHEDSTATS is not set | ||
| 988 | # CONFIG_TIMER_STATS is not set | ||
| 989 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 990 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 991 | # CONFIG_SLUB_STATS is not set | ||
| 992 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 993 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 994 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 995 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 996 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 997 | # CONFIG_PROVE_LOCKING is not set | ||
| 998 | # CONFIG_LOCK_STAT is not set | ||
| 999 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1000 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1001 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1002 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 1003 | CONFIG_DEBUG_INFO=y | ||
| 1004 | # CONFIG_DEBUG_VM is not set | ||
| 1005 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1006 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 1007 | # CONFIG_DEBUG_LIST is not set | ||
| 1008 | # CONFIG_DEBUG_SG is not set | ||
| 1009 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1010 | CONFIG_FRAME_POINTER=y | ||
| 1011 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1012 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1013 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1014 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1015 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1016 | # CONFIG_FAULT_INJECTION is not set | ||
| 1017 | # CONFIG_LATENCYTOP is not set | ||
| 1018 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1019 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1020 | |||
| 1021 | # | ||
| 1022 | # Tracers | ||
| 1023 | # | ||
| 1024 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1025 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1026 | # CONFIG_SCHED_TRACER is not set | ||
| 1027 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1028 | # CONFIG_BOOT_TRACER is not set | ||
| 1029 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1030 | # CONFIG_STACK_TRACER is not set | ||
| 1031 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1032 | # CONFIG_SAMPLES is not set | ||
| 1033 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1034 | # CONFIG_KGDB is not set | ||
| 1035 | CONFIG_DEBUG_USER=y | ||
| 1036 | CONFIG_DEBUG_ERRORS=y | ||
| 1037 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1038 | CONFIG_DEBUG_LL=y | ||
| 1039 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 1040 | |||
| 1041 | # | ||
| 1042 | # Security options | ||
| 1043 | # | ||
| 1044 | # CONFIG_KEYS is not set | ||
| 1045 | # CONFIG_SECURITY is not set | ||
| 1046 | # CONFIG_SECURITYFS is not set | ||
| 1047 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1048 | CONFIG_CRYPTO=y | ||
| 1049 | |||
| 1050 | # | ||
| 1051 | # Crypto core or helper | ||
| 1052 | # | ||
| 1053 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1054 | CONFIG_CRYPTO_ALGAPI=y | ||
| 1055 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1056 | CONFIG_CRYPTO_AEAD2=y | ||
| 1057 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 1058 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1059 | CONFIG_CRYPTO_HASH2=y | ||
| 1060 | CONFIG_CRYPTO_RNG2=y | ||
| 1061 | CONFIG_CRYPTO_MANAGER=y | ||
| 1062 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1063 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1064 | # CONFIG_CRYPTO_NULL is not set | ||
| 1065 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1066 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1067 | # CONFIG_CRYPTO_TEST is not set | ||
| 1068 | |||
| 1069 | # | ||
| 1070 | # Authenticated Encryption with Associated Data | ||
| 1071 | # | ||
| 1072 | # CONFIG_CRYPTO_CCM is not set | ||
| 1073 | # CONFIG_CRYPTO_GCM is not set | ||
| 1074 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1075 | |||
| 1076 | # | ||
| 1077 | # Block modes | ||
| 1078 | # | ||
| 1079 | # CONFIG_CRYPTO_CBC is not set | ||
| 1080 | # CONFIG_CRYPTO_CTR is not set | ||
| 1081 | # CONFIG_CRYPTO_CTS is not set | ||
| 1082 | CONFIG_CRYPTO_ECB=y | ||
| 1083 | # CONFIG_CRYPTO_LRW is not set | ||
| 1084 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1085 | # CONFIG_CRYPTO_XTS is not set | ||
| 1086 | |||
| 1087 | # | ||
| 1088 | # Hash modes | ||
| 1089 | # | ||
| 1090 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1091 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1092 | |||
| 1093 | # | ||
| 1094 | # Digest | ||
| 1095 | # | ||
| 1096 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1097 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1098 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1099 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1100 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1101 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1102 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1103 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1104 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1105 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1106 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1107 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1108 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1109 | |||
| 1110 | # | ||
| 1111 | # Ciphers | ||
| 1112 | # | ||
| 1113 | CONFIG_CRYPTO_AES=y | ||
| 1114 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1115 | CONFIG_CRYPTO_ARC4=y | ||
| 1116 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1117 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1118 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1119 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1120 | # CONFIG_CRYPTO_DES is not set | ||
| 1121 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1122 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1123 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1124 | # CONFIG_CRYPTO_SEED is not set | ||
| 1125 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1126 | # CONFIG_CRYPTO_TEA is not set | ||
| 1127 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1128 | |||
| 1129 | # | ||
| 1130 | # Compression | ||
| 1131 | # | ||
| 1132 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1133 | # CONFIG_CRYPTO_LZO is not set | ||
| 1134 | |||
| 1135 | # | ||
| 1136 | # Random Number Generation | ||
| 1137 | # | ||
| 1138 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1139 | CONFIG_CRYPTO_HW=y | ||
| 1140 | |||
| 1141 | # | ||
| 1142 | # Library routines | ||
| 1143 | # | ||
| 1144 | CONFIG_BITREVERSE=y | ||
| 1145 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1146 | # CONFIG_CRC_CCITT is not set | ||
| 1147 | # CONFIG_CRC16 is not set | ||
| 1148 | # CONFIG_CRC_T10DIF is not set | ||
| 1149 | # CONFIG_CRC_ITU_T is not set | ||
| 1150 | CONFIG_CRC32=y | ||
| 1151 | # CONFIG_CRC7 is not set | ||
| 1152 | # CONFIG_LIBCRC32C is not set | ||
| 1153 | CONFIG_PLIST=y | ||
| 1154 | CONFIG_HAS_IOMEM=y | ||
| 1155 | CONFIG_HAS_IOPORT=y | ||
| 1156 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig index f7622e658163..1aa62249031b 100644 --- a/arch/arm/configs/collie_defconfig +++ b/arch/arm/configs/collie_defconfig | |||
| @@ -113,7 +113,6 @@ CONFIG_ARCH_SA1100=y | |||
| 113 | CONFIG_SA1100_COLLIE=y | 113 | CONFIG_SA1100_COLLIE=y |
| 114 | # CONFIG_SA1100_H3100 is not set | 114 | # CONFIG_SA1100_H3100 is not set |
| 115 | # CONFIG_SA1100_H3600 is not set | 115 | # CONFIG_SA1100_H3600 is not set |
| 116 | # CONFIG_SA1100_H3800 is not set | ||
| 117 | # CONFIG_SA1100_BADGE4 is not set | 116 | # CONFIG_SA1100_BADGE4 is not set |
| 118 | # CONFIG_SA1100_JORNADA720 is not set | 117 | # CONFIG_SA1100_JORNADA720 is not set |
| 119 | # CONFIG_SA1100_HACKKIT is not set | 118 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig new file mode 100644 index 000000000000..e9955b786c80 --- /dev/null +++ b/arch/arm/configs/em_x270_defconfig | |||
| @@ -0,0 +1,1741 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.29-rc2 | ||
| 4 | # Sun Feb 1 16:43:31 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_ARCH_MTD_XIP=y | ||
| 26 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 27 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 28 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 29 | |||
| 30 | # | ||
| 31 | # General setup | ||
| 32 | # | ||
| 33 | CONFIG_EXPERIMENTAL=y | ||
| 34 | CONFIG_BROKEN_ON_SMP=y | ||
| 35 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 36 | CONFIG_LOCALVERSION="" | ||
| 37 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 38 | CONFIG_SWAP=y | ||
| 39 | CONFIG_SYSVIPC=y | ||
| 40 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 41 | # CONFIG_POSIX_MQUEUE is not set | ||
| 42 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 43 | # CONFIG_TASKSTATS is not set | ||
| 44 | # CONFIG_AUDIT is not set | ||
| 45 | CONFIG_IKCONFIG=y | ||
| 46 | CONFIG_IKCONFIG_PROC=y | ||
| 47 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 48 | CONFIG_GROUP_SCHED=y | ||
| 49 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 50 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 51 | CONFIG_USER_SCHED=y | ||
| 52 | # CONFIG_CGROUP_SCHED is not set | ||
| 53 | # CONFIG_CGROUPS is not set | ||
| 54 | CONFIG_SYSFS_DEPRECATED=y | ||
| 55 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 56 | # CONFIG_RELAY is not set | ||
| 57 | # CONFIG_NAMESPACES is not set | ||
| 58 | CONFIG_BLK_DEV_INITRD=y | ||
| 59 | CONFIG_INITRAMFS_SOURCE="" | ||
| 60 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 61 | CONFIG_SYSCTL=y | ||
| 62 | CONFIG_EMBEDDED=y | ||
| 63 | CONFIG_UID16=y | ||
| 64 | CONFIG_SYSCTL_SYSCALL=y | ||
| 65 | CONFIG_KALLSYMS=y | ||
| 66 | # CONFIG_KALLSYMS_ALL is not set | ||
| 67 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 68 | CONFIG_HOTPLUG=y | ||
| 69 | CONFIG_PRINTK=y | ||
| 70 | CONFIG_BUG=y | ||
| 71 | CONFIG_ELF_CORE=y | ||
| 72 | # CONFIG_COMPAT_BRK is not set | ||
| 73 | CONFIG_BASE_FULL=y | ||
| 74 | CONFIG_FUTEX=y | ||
| 75 | CONFIG_ANON_INODES=y | ||
| 76 | CONFIG_EPOLL=y | ||
| 77 | CONFIG_SIGNALFD=y | ||
| 78 | CONFIG_TIMERFD=y | ||
| 79 | CONFIG_EVENTFD=y | ||
| 80 | CONFIG_SHMEM=y | ||
| 81 | CONFIG_AIO=y | ||
| 82 | # CONFIG_VM_EVENT_COUNTERS is not set | ||
| 83 | # CONFIG_SLUB_DEBUG is not set | ||
| 84 | # CONFIG_SLAB is not set | ||
| 85 | CONFIG_SLUB=y | ||
| 86 | # CONFIG_SLOB is not set | ||
| 87 | # CONFIG_PROFILING is not set | ||
| 88 | CONFIG_HAVE_OPROFILE=y | ||
| 89 | # CONFIG_KPROBES is not set | ||
| 90 | CONFIG_HAVE_KPROBES=y | ||
| 91 | CONFIG_HAVE_KRETPROBES=y | ||
| 92 | CONFIG_HAVE_CLK=y | ||
| 93 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 94 | CONFIG_RT_MUTEXES=y | ||
| 95 | CONFIG_BASE_SMALL=0 | ||
| 96 | CONFIG_MODULES=y | ||
| 97 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 98 | CONFIG_MODULE_UNLOAD=y | ||
| 99 | # CONFIG_MODULE_FORCE_UNLOAD is not set | ||
| 100 | # CONFIG_MODVERSIONS is not set | ||
| 101 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 102 | CONFIG_BLOCK=y | ||
| 103 | # CONFIG_LBD is not set | ||
| 104 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 105 | # CONFIG_BLK_DEV_BSG is not set | ||
| 106 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 107 | |||
| 108 | # | ||
| 109 | # IO Schedulers | ||
| 110 | # | ||
| 111 | CONFIG_IOSCHED_NOOP=y | ||
| 112 | CONFIG_IOSCHED_AS=y | ||
| 113 | CONFIG_IOSCHED_DEADLINE=y | ||
| 114 | CONFIG_IOSCHED_CFQ=y | ||
| 115 | # CONFIG_DEFAULT_AS is not set | ||
| 116 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 117 | CONFIG_DEFAULT_CFQ=y | ||
| 118 | # CONFIG_DEFAULT_NOOP is not set | ||
| 119 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 120 | CONFIG_CLASSIC_RCU=y | ||
| 121 | # CONFIG_TREE_RCU is not set | ||
| 122 | # CONFIG_PREEMPT_RCU is not set | ||
| 123 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 124 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 125 | CONFIG_FREEZER=y | ||
| 126 | |||
| 127 | # | ||
| 128 | # System Type | ||
| 129 | # | ||
| 130 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 131 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 132 | # CONFIG_ARCH_REALVIEW is not set | ||
| 133 | # CONFIG_ARCH_VERSATILE is not set | ||
| 134 | # CONFIG_ARCH_AT91 is not set | ||
| 135 | # CONFIG_ARCH_CLPS711X is not set | ||
| 136 | # CONFIG_ARCH_EBSA110 is not set | ||
| 137 | # CONFIG_ARCH_EP93XX is not set | ||
| 138 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 139 | # CONFIG_ARCH_NETX is not set | ||
| 140 | # CONFIG_ARCH_H720X is not set | ||
| 141 | # CONFIG_ARCH_IMX is not set | ||
| 142 | # CONFIG_ARCH_IOP13XX is not set | ||
| 143 | # CONFIG_ARCH_IOP32X is not set | ||
| 144 | # CONFIG_ARCH_IOP33X is not set | ||
| 145 | # CONFIG_ARCH_IXP23XX is not set | ||
| 146 | # CONFIG_ARCH_IXP2000 is not set | ||
| 147 | # CONFIG_ARCH_IXP4XX is not set | ||
| 148 | # CONFIG_ARCH_L7200 is not set | ||
| 149 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 150 | # CONFIG_ARCH_KS8695 is not set | ||
| 151 | # CONFIG_ARCH_NS9XXX is not set | ||
| 152 | # CONFIG_ARCH_LOKI is not set | ||
| 153 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 154 | # CONFIG_ARCH_MXC is not set | ||
| 155 | # CONFIG_ARCH_ORION5X is not set | ||
| 156 | # CONFIG_ARCH_PNX4008 is not set | ||
| 157 | CONFIG_ARCH_PXA=y | ||
| 158 | # CONFIG_ARCH_RPC is not set | ||
| 159 | # CONFIG_ARCH_SA1100 is not set | ||
| 160 | # CONFIG_ARCH_S3C2410 is not set | ||
| 161 | # CONFIG_ARCH_S3C64XX is not set | ||
| 162 | # CONFIG_ARCH_SHARK is not set | ||
| 163 | # CONFIG_ARCH_LH7A40X is not set | ||
| 164 | # CONFIG_ARCH_DAVINCI is not set | ||
| 165 | # CONFIG_ARCH_OMAP is not set | ||
| 166 | # CONFIG_ARCH_MSM is not set | ||
| 167 | # CONFIG_ARCH_W90X900 is not set | ||
| 168 | |||
| 169 | # | ||
| 170 | # Intel PXA2xx/PXA3xx Implementations | ||
| 171 | # | ||
| 172 | # CONFIG_ARCH_GUMSTIX is not set | ||
| 173 | # CONFIG_MACH_INTELMOTE2 is not set | ||
| 174 | # CONFIG_ARCH_LUBBOCK is not set | ||
| 175 | # CONFIG_MACH_LOGICPD_PXA270 is not set | ||
| 176 | # CONFIG_MACH_MAINSTONE is not set | ||
| 177 | # CONFIG_MACH_MP900C is not set | ||
| 178 | # CONFIG_ARCH_PXA_IDP is not set | ||
| 179 | # CONFIG_PXA_SHARPSL is not set | ||
| 180 | # CONFIG_ARCH_VIPER is not set | ||
| 181 | # CONFIG_ARCH_PXA_ESERIES is not set | ||
| 182 | # CONFIG_TRIZEPS_PXA is not set | ||
| 183 | # CONFIG_MACH_H5000 is not set | ||
| 184 | CONFIG_MACH_EM_X270=y | ||
| 185 | CONFIG_MACH_EXEDA=y | ||
| 186 | # CONFIG_MACH_COLIBRI is not set | ||
| 187 | # CONFIG_MACH_ZYLONITE is not set | ||
| 188 | # CONFIG_MACH_LITTLETON is not set | ||
| 189 | # CONFIG_MACH_TAVOREVB is not set | ||
| 190 | # CONFIG_MACH_SAAR is not set | ||
| 191 | # CONFIG_MACH_ARMCORE is not set | ||
| 192 | # CONFIG_MACH_CM_X300 is not set | ||
| 193 | # CONFIG_MACH_MAGICIAN is not set | ||
| 194 | # CONFIG_MACH_MIOA701 is not set | ||
| 195 | # CONFIG_MACH_PCM027 is not set | ||
| 196 | # CONFIG_ARCH_PXA_PALM is not set | ||
| 197 | # CONFIG_PXA_EZX is not set | ||
| 198 | CONFIG_PXA27x=y | ||
| 199 | CONFIG_PXA_SSP=y | ||
| 200 | # CONFIG_PXA_PWM is not set | ||
| 201 | |||
| 202 | # | ||
| 203 | # Processor Type | ||
| 204 | # | ||
| 205 | CONFIG_CPU_32=y | ||
| 206 | CONFIG_CPU_XSCALE=y | ||
| 207 | CONFIG_CPU_32v5=y | ||
| 208 | CONFIG_CPU_ABRT_EV5T=y | ||
| 209 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 210 | CONFIG_CPU_CACHE_VIVT=y | ||
| 211 | CONFIG_CPU_TLB_V4WBI=y | ||
| 212 | CONFIG_CPU_CP15=y | ||
| 213 | CONFIG_CPU_CP15_MMU=y | ||
| 214 | |||
| 215 | # | ||
| 216 | # Processor Features | ||
| 217 | # | ||
| 218 | CONFIG_ARM_THUMB=y | ||
| 219 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 220 | # CONFIG_OUTER_CACHE is not set | ||
| 221 | CONFIG_IWMMXT=y | ||
| 222 | CONFIG_XSCALE_PMU=y | ||
| 223 | CONFIG_COMMON_CLKDEV=y | ||
| 224 | |||
| 225 | # | ||
| 226 | # Bus support | ||
| 227 | # | ||
| 228 | # CONFIG_PCI_SYSCALL is not set | ||
| 229 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 230 | # CONFIG_PCCARD is not set | ||
| 231 | |||
| 232 | # | ||
| 233 | # Kernel Features | ||
| 234 | # | ||
| 235 | CONFIG_TICK_ONESHOT=y | ||
| 236 | CONFIG_NO_HZ=y | ||
| 237 | # CONFIG_HIGH_RES_TIMERS is not set | ||
| 238 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 239 | CONFIG_VMSPLIT_3G=y | ||
| 240 | # CONFIG_VMSPLIT_2G is not set | ||
| 241 | # CONFIG_VMSPLIT_1G is not set | ||
| 242 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 243 | # CONFIG_PREEMPT is not set | ||
| 244 | CONFIG_HZ=100 | ||
| 245 | CONFIG_AEABI=y | ||
| 246 | CONFIG_OABI_COMPAT=y | ||
| 247 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 248 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 249 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 250 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 251 | CONFIG_FLATMEM_MANUAL=y | ||
| 252 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 253 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 254 | CONFIG_FLATMEM=y | ||
| 255 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 256 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 257 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 258 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 259 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 260 | CONFIG_VIRT_TO_BUS=y | ||
| 261 | CONFIG_UNEVICTABLE_LRU=y | ||
| 262 | CONFIG_ALIGNMENT_TRAP=y | ||
| 263 | |||
| 264 | # | ||
| 265 | # Boot options | ||
| 266 | # | ||
| 267 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 268 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 269 | CONFIG_CMDLINE="root=1f03 mem=32M" | ||
| 270 | # CONFIG_XIP_KERNEL is not set | ||
| 271 | # CONFIG_KEXEC is not set | ||
| 272 | |||
| 273 | # | ||
| 274 | # CPU Power Management | ||
| 275 | # | ||
| 276 | CONFIG_CPU_FREQ=y | ||
| 277 | CONFIG_CPU_FREQ_TABLE=y | ||
| 278 | # CONFIG_CPU_FREQ_DEBUG is not set | ||
| 279 | CONFIG_CPU_FREQ_STAT=y | ||
| 280 | # CONFIG_CPU_FREQ_STAT_DETAILS is not set | ||
| 281 | CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y | ||
| 282 | # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set | ||
| 283 | # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set | ||
| 284 | # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set | ||
| 285 | # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set | ||
| 286 | CONFIG_CPU_FREQ_GOV_PERFORMANCE=y | ||
| 287 | # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set | ||
| 288 | CONFIG_CPU_FREQ_GOV_USERSPACE=m | ||
| 289 | # CONFIG_CPU_FREQ_GOV_ONDEMAND is not set | ||
| 290 | # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set | ||
| 291 | # CONFIG_CPU_IDLE is not set | ||
| 292 | |||
| 293 | # | ||
| 294 | # Floating point emulation | ||
| 295 | # | ||
| 296 | |||
| 297 | # | ||
| 298 | # At least one emulation must be selected | ||
| 299 | # | ||
| 300 | CONFIG_FPE_NWFPE=y | ||
| 301 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 302 | # CONFIG_FPE_FASTFPE is not set | ||
| 303 | |||
| 304 | # | ||
| 305 | # Userspace binary formats | ||
| 306 | # | ||
| 307 | CONFIG_BINFMT_ELF=y | ||
| 308 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 309 | CONFIG_HAVE_AOUT=y | ||
| 310 | # CONFIG_BINFMT_AOUT is not set | ||
| 311 | # CONFIG_BINFMT_MISC is not set | ||
| 312 | |||
| 313 | # | ||
| 314 | # Power management options | ||
| 315 | # | ||
| 316 | CONFIG_PM=y | ||
| 317 | # CONFIG_PM_DEBUG is not set | ||
| 318 | CONFIG_PM_SLEEP=y | ||
| 319 | CONFIG_SUSPEND=y | ||
| 320 | CONFIG_SUSPEND_FREEZER=y | ||
| 321 | CONFIG_APM_EMULATION=y | ||
| 322 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 323 | CONFIG_NET=y | ||
| 324 | |||
| 325 | # | ||
| 326 | # Networking options | ||
| 327 | # | ||
| 328 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 329 | CONFIG_PACKET=y | ||
| 330 | CONFIG_PACKET_MMAP=y | ||
| 331 | CONFIG_UNIX=y | ||
| 332 | CONFIG_XFRM=y | ||
| 333 | # CONFIG_XFRM_USER is not set | ||
| 334 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 335 | # CONFIG_XFRM_MIGRATE is not set | ||
| 336 | # CONFIG_XFRM_STATISTICS is not set | ||
| 337 | # CONFIG_NET_KEY is not set | ||
| 338 | CONFIG_INET=y | ||
| 339 | CONFIG_IP_MULTICAST=y | ||
| 340 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 341 | CONFIG_IP_FIB_HASH=y | ||
| 342 | CONFIG_IP_PNP=y | ||
| 343 | CONFIG_IP_PNP_DHCP=y | ||
| 344 | CONFIG_IP_PNP_BOOTP=y | ||
| 345 | # CONFIG_IP_PNP_RARP is not set | ||
| 346 | # CONFIG_NET_IPIP is not set | ||
| 347 | # CONFIG_NET_IPGRE is not set | ||
| 348 | # CONFIG_IP_MROUTE is not set | ||
| 349 | # CONFIG_ARPD is not set | ||
| 350 | # CONFIG_SYN_COOKIES is not set | ||
| 351 | # CONFIG_INET_AH is not set | ||
| 352 | # CONFIG_INET_ESP is not set | ||
| 353 | # CONFIG_INET_IPCOMP is not set | ||
| 354 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 355 | # CONFIG_INET_TUNNEL is not set | ||
| 356 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 357 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 358 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 359 | # CONFIG_INET_LRO is not set | ||
| 360 | # CONFIG_INET_DIAG is not set | ||
| 361 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 362 | CONFIG_TCP_CONG_CUBIC=y | ||
| 363 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 364 | # CONFIG_TCP_MD5SIG is not set | ||
| 365 | # CONFIG_IPV6 is not set | ||
| 366 | # CONFIG_NETWORK_SECMARK is not set | ||
| 367 | # CONFIG_NETFILTER is not set | ||
| 368 | # CONFIG_IP_DCCP is not set | ||
| 369 | # CONFIG_IP_SCTP is not set | ||
| 370 | # CONFIG_TIPC is not set | ||
| 371 | # CONFIG_ATM is not set | ||
| 372 | # CONFIG_BRIDGE is not set | ||
| 373 | # CONFIG_NET_DSA is not set | ||
| 374 | # CONFIG_VLAN_8021Q is not set | ||
| 375 | # CONFIG_DECNET is not set | ||
| 376 | # CONFIG_LLC2 is not set | ||
| 377 | # CONFIG_IPX is not set | ||
| 378 | # CONFIG_ATALK is not set | ||
| 379 | # CONFIG_X25 is not set | ||
| 380 | # CONFIG_LAPB is not set | ||
| 381 | # CONFIG_ECONET is not set | ||
| 382 | # CONFIG_WAN_ROUTER is not set | ||
| 383 | # CONFIG_NET_SCHED is not set | ||
| 384 | # CONFIG_DCB is not set | ||
| 385 | |||
| 386 | # | ||
| 387 | # Network testing | ||
| 388 | # | ||
| 389 | # CONFIG_NET_PKTGEN is not set | ||
| 390 | # CONFIG_HAMRADIO is not set | ||
| 391 | # CONFIG_CAN is not set | ||
| 392 | # CONFIG_IRDA is not set | ||
| 393 | CONFIG_BT=m | ||
| 394 | CONFIG_BT_L2CAP=m | ||
| 395 | CONFIG_BT_SCO=m | ||
| 396 | CONFIG_BT_RFCOMM=m | ||
| 397 | # CONFIG_BT_RFCOMM_TTY is not set | ||
| 398 | CONFIG_BT_BNEP=m | ||
| 399 | # CONFIG_BT_BNEP_MC_FILTER is not set | ||
| 400 | # CONFIG_BT_BNEP_PROTO_FILTER is not set | ||
| 401 | CONFIG_BT_HIDP=m | ||
| 402 | |||
| 403 | # | ||
| 404 | # Bluetooth device drivers | ||
| 405 | # | ||
| 406 | CONFIG_BT_HCIBTUSB=m | ||
| 407 | # CONFIG_BT_HCIBTSDIO is not set | ||
| 408 | # CONFIG_BT_HCIUART is not set | ||
| 409 | # CONFIG_BT_HCIBCM203X is not set | ||
| 410 | # CONFIG_BT_HCIBPA10X is not set | ||
| 411 | # CONFIG_BT_HCIBFUSB is not set | ||
| 412 | # CONFIG_BT_HCIVHCI is not set | ||
| 413 | # CONFIG_AF_RXRPC is not set | ||
| 414 | # CONFIG_PHONET is not set | ||
| 415 | CONFIG_WIRELESS=y | ||
| 416 | # CONFIG_CFG80211 is not set | ||
| 417 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 418 | CONFIG_WIRELESS_EXT=y | ||
| 419 | CONFIG_WIRELESS_EXT_SYSFS=y | ||
| 420 | CONFIG_LIB80211=m | ||
| 421 | # CONFIG_MAC80211 is not set | ||
| 422 | # CONFIG_WIMAX is not set | ||
| 423 | # CONFIG_RFKILL is not set | ||
| 424 | # CONFIG_NET_9P is not set | ||
| 425 | |||
| 426 | # | ||
| 427 | # Device Drivers | ||
| 428 | # | ||
| 429 | |||
| 430 | # | ||
| 431 | # Generic Driver Options | ||
| 432 | # | ||
| 433 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 434 | CONFIG_STANDALONE=y | ||
| 435 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 436 | CONFIG_FW_LOADER=m | ||
| 437 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 438 | CONFIG_EXTRA_FIRMWARE="" | ||
| 439 | # CONFIG_DEBUG_DRIVER is not set | ||
| 440 | # CONFIG_DEBUG_DEVRES is not set | ||
| 441 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 442 | # CONFIG_CONNECTOR is not set | ||
| 443 | CONFIG_MTD=y | ||
| 444 | # CONFIG_MTD_DEBUG is not set | ||
| 445 | # CONFIG_MTD_CONCAT is not set | ||
| 446 | CONFIG_MTD_PARTITIONS=y | ||
| 447 | # CONFIG_MTD_TESTS is not set | ||
| 448 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 449 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 450 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 451 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 452 | |||
| 453 | # | ||
| 454 | # User Modules And Translation Layers | ||
| 455 | # | ||
| 456 | CONFIG_MTD_CHAR=y | ||
| 457 | CONFIG_MTD_BLKDEVS=y | ||
| 458 | CONFIG_MTD_BLOCK=y | ||
| 459 | # CONFIG_FTL is not set | ||
| 460 | # CONFIG_NFTL is not set | ||
| 461 | # CONFIG_INFTL is not set | ||
| 462 | # CONFIG_RFD_FTL is not set | ||
| 463 | # CONFIG_SSFDC is not set | ||
| 464 | # CONFIG_MTD_OOPS is not set | ||
| 465 | |||
| 466 | # | ||
| 467 | # RAM/ROM/Flash chip drivers | ||
| 468 | # | ||
| 469 | CONFIG_MTD_CFI=y | ||
| 470 | CONFIG_MTD_JEDECPROBE=y | ||
| 471 | CONFIG_MTD_GEN_PROBE=y | ||
| 472 | CONFIG_MTD_CFI_ADV_OPTIONS=y | ||
| 473 | CONFIG_MTD_CFI_NOSWAP=y | ||
| 474 | # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set | ||
| 475 | # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set | ||
| 476 | # CONFIG_MTD_CFI_GEOMETRY is not set | ||
| 477 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 478 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 479 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 480 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 481 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 482 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 483 | CONFIG_MTD_CFI_I1=y | ||
| 484 | CONFIG_MTD_CFI_I2=y | ||
| 485 | # CONFIG_MTD_CFI_I4 is not set | ||
| 486 | # CONFIG_MTD_CFI_I8 is not set | ||
| 487 | # CONFIG_MTD_OTP is not set | ||
| 488 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 489 | CONFIG_MTD_CFI_AMDSTD=y | ||
| 490 | CONFIG_MTD_CFI_STAA=y | ||
| 491 | CONFIG_MTD_CFI_UTIL=y | ||
| 492 | # CONFIG_MTD_RAM is not set | ||
| 493 | # CONFIG_MTD_ROM is not set | ||
| 494 | # CONFIG_MTD_ABSENT is not set | ||
| 495 | # CONFIG_MTD_XIP is not set | ||
| 496 | |||
| 497 | # | ||
| 498 | # Mapping drivers for chip access | ||
| 499 | # | ||
| 500 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 501 | CONFIG_MTD_PHYSMAP=y | ||
| 502 | # CONFIG_MTD_PHYSMAP_COMPAT is not set | ||
| 503 | CONFIG_MTD_PXA2XX=y | ||
| 504 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 505 | # CONFIG_MTD_IMPA7 is not set | ||
| 506 | # CONFIG_MTD_SHARP_SL is not set | ||
| 507 | # CONFIG_MTD_PLATRAM is not set | ||
| 508 | |||
| 509 | # | ||
| 510 | # Self-contained MTD device drivers | ||
| 511 | # | ||
| 512 | # CONFIG_MTD_DATAFLASH is not set | ||
| 513 | # CONFIG_MTD_M25P80 is not set | ||
| 514 | # CONFIG_MTD_SLRAM is not set | ||
| 515 | # CONFIG_MTD_PHRAM is not set | ||
| 516 | # CONFIG_MTD_MTDRAM is not set | ||
| 517 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 518 | |||
| 519 | # | ||
| 520 | # Disk-On-Chip Device Drivers | ||
| 521 | # | ||
| 522 | # CONFIG_MTD_DOC2000 is not set | ||
| 523 | # CONFIG_MTD_DOC2001 is not set | ||
| 524 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 525 | CONFIG_MTD_NAND=y | ||
| 526 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
| 527 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 528 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 529 | # CONFIG_MTD_NAND_H1900 is not set | ||
| 530 | # CONFIG_MTD_NAND_GPIO is not set | ||
| 531 | CONFIG_MTD_NAND_IDS=y | ||
| 532 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 533 | # CONFIG_MTD_NAND_SHARPSL is not set | ||
| 534 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 535 | CONFIG_MTD_NAND_PLATFORM=y | ||
| 536 | # CONFIG_MTD_ALAUDA is not set | ||
| 537 | # CONFIG_MTD_ONENAND is not set | ||
| 538 | |||
| 539 | # | ||
| 540 | # LPDDR flash memory drivers | ||
| 541 | # | ||
| 542 | # CONFIG_MTD_LPDDR is not set | ||
| 543 | # CONFIG_MTD_QINFO_PROBE is not set | ||
| 544 | |||
| 545 | # | ||
| 546 | # UBI - Unsorted block images | ||
| 547 | # | ||
| 548 | # CONFIG_MTD_UBI is not set | ||
| 549 | # CONFIG_PARPORT is not set | ||
| 550 | CONFIG_BLK_DEV=y | ||
| 551 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 552 | CONFIG_BLK_DEV_LOOP=y | ||
| 553 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 554 | # CONFIG_BLK_DEV_NBD is not set | ||
| 555 | # CONFIG_BLK_DEV_UB is not set | ||
| 556 | CONFIG_BLK_DEV_RAM=y | ||
| 557 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 558 | CONFIG_BLK_DEV_RAM_SIZE=4096 | ||
| 559 | # CONFIG_BLK_DEV_XIP is not set | ||
| 560 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 561 | # CONFIG_ATA_OVER_ETH is not set | ||
| 562 | # CONFIG_MISC_DEVICES is not set | ||
| 563 | CONFIG_HAVE_IDE=y | ||
| 564 | # CONFIG_IDE is not set | ||
| 565 | |||
| 566 | # | ||
| 567 | # SCSI device support | ||
| 568 | # | ||
| 569 | # CONFIG_RAID_ATTRS is not set | ||
| 570 | CONFIG_SCSI=y | ||
| 571 | CONFIG_SCSI_DMA=y | ||
| 572 | # CONFIG_SCSI_TGT is not set | ||
| 573 | # CONFIG_SCSI_NETLINK is not set | ||
| 574 | CONFIG_SCSI_PROC_FS=y | ||
| 575 | |||
| 576 | # | ||
| 577 | # SCSI support type (disk, tape, CD-ROM) | ||
| 578 | # | ||
| 579 | CONFIG_BLK_DEV_SD=y | ||
| 580 | # CONFIG_CHR_DEV_ST is not set | ||
| 581 | # CONFIG_CHR_DEV_OSST is not set | ||
| 582 | # CONFIG_BLK_DEV_SR is not set | ||
| 583 | # CONFIG_CHR_DEV_SG is not set | ||
| 584 | # CONFIG_CHR_DEV_SCH is not set | ||
| 585 | |||
| 586 | # | ||
| 587 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 588 | # | ||
| 589 | # CONFIG_SCSI_MULTI_LUN is not set | ||
| 590 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 591 | # CONFIG_SCSI_LOGGING is not set | ||
| 592 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 593 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 594 | |||
| 595 | # | ||
| 596 | # SCSI Transports | ||
| 597 | # | ||
| 598 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 599 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 600 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 601 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 602 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 603 | # CONFIG_SCSI_LOWLEVEL is not set | ||
| 604 | # CONFIG_SCSI_DH is not set | ||
| 605 | # CONFIG_ATA is not set | ||
| 606 | # CONFIG_MD is not set | ||
| 607 | CONFIG_NETDEVICES=y | ||
| 608 | # CONFIG_DUMMY is not set | ||
| 609 | # CONFIG_BONDING is not set | ||
| 610 | # CONFIG_MACVLAN is not set | ||
| 611 | # CONFIG_EQUALIZER is not set | ||
| 612 | # CONFIG_TUN is not set | ||
| 613 | # CONFIG_VETH is not set | ||
| 614 | # CONFIG_PHYLIB is not set | ||
| 615 | CONFIG_NET_ETHERNET=y | ||
| 616 | CONFIG_MII=y | ||
| 617 | # CONFIG_AX88796 is not set | ||
| 618 | # CONFIG_SMC91X is not set | ||
| 619 | CONFIG_DM9000=y | ||
| 620 | CONFIG_DM9000_DEBUGLEVEL=1 | ||
| 621 | # CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set | ||
| 622 | # CONFIG_ENC28J60 is not set | ||
| 623 | # CONFIG_SMC911X is not set | ||
| 624 | # CONFIG_SMSC911X is not set | ||
| 625 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 626 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 627 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 628 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 629 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 630 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 631 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 632 | # CONFIG_B44 is not set | ||
| 633 | # CONFIG_NETDEV_1000 is not set | ||
| 634 | # CONFIG_NETDEV_10000 is not set | ||
| 635 | |||
| 636 | # | ||
| 637 | # Wireless LAN | ||
| 638 | # | ||
| 639 | # CONFIG_WLAN_PRE80211 is not set | ||
| 640 | CONFIG_WLAN_80211=y | ||
| 641 | CONFIG_LIBERTAS=m | ||
| 642 | # CONFIG_LIBERTAS_USB is not set | ||
| 643 | CONFIG_LIBERTAS_SDIO=m | ||
| 644 | # CONFIG_LIBERTAS_DEBUG is not set | ||
| 645 | # CONFIG_USB_ZD1201 is not set | ||
| 646 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
| 647 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 648 | # CONFIG_HOSTAP is not set | ||
| 649 | |||
| 650 | # | ||
| 651 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 652 | # | ||
| 653 | |||
| 654 | # | ||
| 655 | # USB Network Adapters | ||
| 656 | # | ||
| 657 | # CONFIG_USB_CATC is not set | ||
| 658 | # CONFIG_USB_KAWETH is not set | ||
| 659 | # CONFIG_USB_PEGASUS is not set | ||
| 660 | # CONFIG_USB_RTL8150 is not set | ||
| 661 | # CONFIG_USB_USBNET is not set | ||
| 662 | # CONFIG_WAN is not set | ||
| 663 | CONFIG_PPP=m | ||
| 664 | CONFIG_PPP_MULTILINK=y | ||
| 665 | CONFIG_PPP_FILTER=y | ||
| 666 | CONFIG_PPP_ASYNC=m | ||
| 667 | # CONFIG_PPP_SYNC_TTY is not set | ||
| 668 | CONFIG_PPP_DEFLATE=m | ||
| 669 | CONFIG_PPP_BSDCOMP=m | ||
| 670 | # CONFIG_PPP_MPPE is not set | ||
| 671 | # CONFIG_PPPOE is not set | ||
| 672 | # CONFIG_PPPOL2TP is not set | ||
| 673 | # CONFIG_SLIP is not set | ||
| 674 | CONFIG_SLHC=m | ||
| 675 | # CONFIG_NETCONSOLE is not set | ||
| 676 | # CONFIG_NETPOLL is not set | ||
| 677 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 678 | # CONFIG_ISDN is not set | ||
| 679 | |||
| 680 | # | ||
| 681 | # Input device support | ||
| 682 | # | ||
| 683 | CONFIG_INPUT=y | ||
| 684 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 685 | # CONFIG_INPUT_POLLDEV is not set | ||
| 686 | |||
| 687 | # | ||
| 688 | # Userland interfaces | ||
| 689 | # | ||
| 690 | CONFIG_INPUT_MOUSEDEV=y | ||
| 691 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
| 692 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 693 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 694 | # CONFIG_INPUT_JOYDEV is not set | ||
| 695 | CONFIG_INPUT_EVDEV=y | ||
| 696 | # CONFIG_INPUT_EVBUG is not set | ||
| 697 | CONFIG_INPUT_APMPOWER=y | ||
| 698 | |||
| 699 | # | ||
| 700 | # Input Device Drivers | ||
| 701 | # | ||
| 702 | CONFIG_INPUT_KEYBOARD=y | ||
| 703 | CONFIG_KEYBOARD_ATKBD=y | ||
| 704 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 705 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 706 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 707 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 708 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 709 | CONFIG_KEYBOARD_PXA27x=y | ||
| 710 | CONFIG_KEYBOARD_GPIO=y | ||
| 711 | # CONFIG_INPUT_MOUSE is not set | ||
| 712 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 713 | # CONFIG_INPUT_TABLET is not set | ||
| 714 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 715 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
| 716 | # CONFIG_TOUCHSCREEN_DA9034 is not set | ||
| 717 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 718 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
| 719 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
| 720 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 721 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
| 722 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 723 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
| 724 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
| 725 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
| 726 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
| 727 | CONFIG_TOUCHSCREEN_WM97XX=m | ||
| 728 | # CONFIG_TOUCHSCREEN_WM9705 is not set | ||
| 729 | CONFIG_TOUCHSCREEN_WM9712=y | ||
| 730 | # CONFIG_TOUCHSCREEN_WM9713 is not set | ||
| 731 | # CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set | ||
| 732 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
| 733 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 734 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 735 | # CONFIG_INPUT_MISC is not set | ||
| 736 | |||
| 737 | # | ||
| 738 | # Hardware I/O ports | ||
| 739 | # | ||
| 740 | CONFIG_SERIO=y | ||
| 741 | # CONFIG_SERIO_SERPORT is not set | ||
| 742 | CONFIG_SERIO_LIBPS2=y | ||
| 743 | # CONFIG_SERIO_RAW is not set | ||
| 744 | # CONFIG_GAMEPORT is not set | ||
| 745 | |||
| 746 | # | ||
| 747 | # Character devices | ||
| 748 | # | ||
| 749 | CONFIG_VT=y | ||
| 750 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 751 | CONFIG_VT_CONSOLE=y | ||
| 752 | CONFIG_HW_CONSOLE=y | ||
| 753 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 754 | CONFIG_DEVKMEM=y | ||
| 755 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 756 | |||
| 757 | # | ||
| 758 | # Serial drivers | ||
| 759 | # | ||
| 760 | # CONFIG_SERIAL_8250 is not set | ||
| 761 | |||
| 762 | # | ||
| 763 | # Non-8250 serial port support | ||
| 764 | # | ||
| 765 | CONFIG_SERIAL_PXA=y | ||
| 766 | CONFIG_SERIAL_PXA_CONSOLE=y | ||
| 767 | CONFIG_SERIAL_CORE=y | ||
| 768 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 769 | CONFIG_UNIX98_PTYS=y | ||
| 770 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 771 | CONFIG_LEGACY_PTYS=y | ||
| 772 | CONFIG_LEGACY_PTY_COUNT=16 | ||
| 773 | # CONFIG_IPMI_HANDLER is not set | ||
| 774 | # CONFIG_HW_RANDOM is not set | ||
| 775 | # CONFIG_NVRAM is not set | ||
| 776 | # CONFIG_R3964 is not set | ||
| 777 | # CONFIG_RAW_DRIVER is not set | ||
| 778 | # CONFIG_TCG_TPM is not set | ||
| 779 | CONFIG_I2C=y | ||
| 780 | CONFIG_I2C_BOARDINFO=y | ||
| 781 | CONFIG_I2C_CHARDEV=m | ||
| 782 | CONFIG_I2C_HELPER_AUTO=y | ||
| 783 | |||
| 784 | # | ||
| 785 | # I2C Hardware Bus support | ||
| 786 | # | ||
| 787 | |||
| 788 | # | ||
| 789 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 790 | # | ||
| 791 | # CONFIG_I2C_GPIO is not set | ||
| 792 | # CONFIG_I2C_OCORES is not set | ||
| 793 | CONFIG_I2C_PXA=y | ||
| 794 | # CONFIG_I2C_PXA_SLAVE is not set | ||
| 795 | # CONFIG_I2C_SIMTEC is not set | ||
| 796 | |||
| 797 | # | ||
| 798 | # External I2C/SMBus adapter drivers | ||
| 799 | # | ||
| 800 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 801 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 802 | # CONFIG_I2C_TINY_USB is not set | ||
| 803 | |||
| 804 | # | ||
| 805 | # Other I2C/SMBus bus drivers | ||
| 806 | # | ||
| 807 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 808 | # CONFIG_I2C_STUB is not set | ||
| 809 | |||
| 810 | # | ||
| 811 | # Miscellaneous I2C Chip support | ||
| 812 | # | ||
| 813 | # CONFIG_DS1682 is not set | ||
| 814 | # CONFIG_EEPROM_AT24 is not set | ||
| 815 | # CONFIG_EEPROM_LEGACY is not set | ||
| 816 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 817 | # CONFIG_PCF8575 is not set | ||
| 818 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 819 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 820 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 821 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 822 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 823 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 824 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 825 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 826 | CONFIG_SPI=y | ||
| 827 | # CONFIG_SPI_DEBUG is not set | ||
| 828 | CONFIG_SPI_MASTER=y | ||
| 829 | |||
| 830 | # | ||
| 831 | # SPI Master Controller Drivers | ||
| 832 | # | ||
| 833 | # CONFIG_SPI_BITBANG is not set | ||
| 834 | # CONFIG_SPI_GPIO is not set | ||
| 835 | CONFIG_SPI_PXA2XX=y | ||
| 836 | |||
| 837 | # | ||
| 838 | # SPI Protocol Masters | ||
| 839 | # | ||
| 840 | # CONFIG_SPI_AT25 is not set | ||
| 841 | # CONFIG_SPI_SPIDEV is not set | ||
| 842 | # CONFIG_SPI_TLE62X0 is not set | ||
| 843 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 844 | CONFIG_GPIOLIB=y | ||
| 845 | # CONFIG_DEBUG_GPIO is not set | ||
| 846 | # CONFIG_GPIO_SYSFS is not set | ||
| 847 | |||
| 848 | # | ||
| 849 | # Memory mapped GPIO expanders: | ||
| 850 | # | ||
| 851 | |||
| 852 | # | ||
| 853 | # I2C GPIO expanders: | ||
| 854 | # | ||
| 855 | # CONFIG_GPIO_MAX732X is not set | ||
| 856 | # CONFIG_GPIO_PCA953X is not set | ||
| 857 | # CONFIG_GPIO_PCF857X is not set | ||
| 858 | |||
| 859 | # | ||
| 860 | # PCI GPIO expanders: | ||
| 861 | # | ||
| 862 | |||
| 863 | # | ||
| 864 | # SPI GPIO expanders: | ||
| 865 | # | ||
| 866 | # CONFIG_GPIO_MAX7301 is not set | ||
| 867 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 868 | # CONFIG_W1 is not set | ||
| 869 | CONFIG_POWER_SUPPLY=y | ||
| 870 | # CONFIG_POWER_SUPPLY_DEBUG is not set | ||
| 871 | # CONFIG_PDA_POWER is not set | ||
| 872 | # CONFIG_APM_POWER is not set | ||
| 873 | # CONFIG_BATTERY_DS2760 is not set | ||
| 874 | # CONFIG_BATTERY_BQ27x00 is not set | ||
| 875 | CONFIG_BATTERY_DA9030=y | ||
| 876 | # CONFIG_HWMON is not set | ||
| 877 | # CONFIG_THERMAL is not set | ||
| 878 | # CONFIG_THERMAL_HWMON is not set | ||
| 879 | # CONFIG_WATCHDOG is not set | ||
| 880 | CONFIG_SSB_POSSIBLE=y | ||
| 881 | |||
| 882 | # | ||
| 883 | # Sonics Silicon Backplane | ||
| 884 | # | ||
| 885 | # CONFIG_SSB is not set | ||
| 886 | |||
| 887 | # | ||
| 888 | # Multifunction device drivers | ||
| 889 | # | ||
| 890 | # CONFIG_MFD_CORE is not set | ||
| 891 | # CONFIG_MFD_SM501 is not set | ||
| 892 | # CONFIG_MFD_ASIC3 is not set | ||
| 893 | # CONFIG_HTC_EGPIO is not set | ||
| 894 | # CONFIG_HTC_PASIC3 is not set | ||
| 895 | # CONFIG_UCB1400_CORE is not set | ||
| 896 | # CONFIG_TPS65010 is not set | ||
| 897 | # CONFIG_TWL4030_CORE is not set | ||
| 898 | # CONFIG_MFD_TMIO is not set | ||
| 899 | # CONFIG_MFD_T7L66XB is not set | ||
| 900 | # CONFIG_MFD_TC6387XB is not set | ||
| 901 | # CONFIG_MFD_TC6393XB is not set | ||
| 902 | CONFIG_PMIC_DA903X=y | ||
| 903 | # CONFIG_MFD_WM8400 is not set | ||
| 904 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 905 | # CONFIG_MFD_PCF50633 is not set | ||
| 906 | |||
| 907 | # | ||
| 908 | # Multimedia devices | ||
| 909 | # | ||
| 910 | |||
| 911 | # | ||
| 912 | # Multimedia core support | ||
| 913 | # | ||
| 914 | CONFIG_VIDEO_DEV=m | ||
| 915 | CONFIG_VIDEO_V4L2_COMMON=m | ||
| 916 | # CONFIG_VIDEO_ALLOW_V4L1 is not set | ||
| 917 | CONFIG_VIDEO_V4L1_COMPAT=y | ||
| 918 | # CONFIG_DVB_CORE is not set | ||
| 919 | CONFIG_VIDEO_MEDIA=m | ||
| 920 | |||
| 921 | # | ||
| 922 | # Multimedia drivers | ||
| 923 | # | ||
| 924 | # CONFIG_MEDIA_ATTACH is not set | ||
| 925 | CONFIG_MEDIA_TUNER=m | ||
| 926 | CONFIG_MEDIA_TUNER_CUSTOMIZE=y | ||
| 927 | # CONFIG_MEDIA_TUNER_SIMPLE is not set | ||
| 928 | # CONFIG_MEDIA_TUNER_TDA8290 is not set | ||
| 929 | # CONFIG_MEDIA_TUNER_TDA827X is not set | ||
| 930 | # CONFIG_MEDIA_TUNER_TDA18271 is not set | ||
| 931 | # CONFIG_MEDIA_TUNER_TDA9887 is not set | ||
| 932 | # CONFIG_MEDIA_TUNER_TEA5761 is not set | ||
| 933 | # CONFIG_MEDIA_TUNER_TEA5767 is not set | ||
| 934 | # CONFIG_MEDIA_TUNER_MT20XX is not set | ||
| 935 | # CONFIG_MEDIA_TUNER_MT2060 is not set | ||
| 936 | # CONFIG_MEDIA_TUNER_MT2266 is not set | ||
| 937 | # CONFIG_MEDIA_TUNER_MT2131 is not set | ||
| 938 | # CONFIG_MEDIA_TUNER_QT1010 is not set | ||
| 939 | # CONFIG_MEDIA_TUNER_XC2028 is not set | ||
| 940 | # CONFIG_MEDIA_TUNER_XC5000 is not set | ||
| 941 | # CONFIG_MEDIA_TUNER_MXL5005S is not set | ||
| 942 | # CONFIG_MEDIA_TUNER_MXL5007T is not set | ||
| 943 | CONFIG_VIDEO_V4L2=m | ||
| 944 | CONFIG_VIDEOBUF_GEN=m | ||
| 945 | CONFIG_VIDEOBUF_DMA_SG=m | ||
| 946 | CONFIG_VIDEO_CAPTURE_DRIVERS=y | ||
| 947 | # CONFIG_VIDEO_ADV_DEBUG is not set | ||
| 948 | # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set | ||
| 949 | # CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set | ||
| 950 | |||
| 951 | # | ||
| 952 | # Encoders/decoders and other helper chips | ||
| 953 | # | ||
| 954 | |||
| 955 | # | ||
| 956 | # Audio decoders | ||
| 957 | # | ||
| 958 | # CONFIG_VIDEO_TVAUDIO is not set | ||
| 959 | # CONFIG_VIDEO_TDA7432 is not set | ||
| 960 | # CONFIG_VIDEO_TDA9840 is not set | ||
| 961 | # CONFIG_VIDEO_TDA9875 is not set | ||
| 962 | # CONFIG_VIDEO_TEA6415C is not set | ||
| 963 | # CONFIG_VIDEO_TEA6420 is not set | ||
| 964 | # CONFIG_VIDEO_MSP3400 is not set | ||
| 965 | # CONFIG_VIDEO_CS5345 is not set | ||
| 966 | # CONFIG_VIDEO_CS53L32A is not set | ||
| 967 | # CONFIG_VIDEO_M52790 is not set | ||
| 968 | # CONFIG_VIDEO_TLV320AIC23B is not set | ||
| 969 | # CONFIG_VIDEO_WM8775 is not set | ||
| 970 | # CONFIG_VIDEO_WM8739 is not set | ||
| 971 | # CONFIG_VIDEO_VP27SMPX is not set | ||
| 972 | |||
| 973 | # | ||
| 974 | # Video decoders | ||
| 975 | # | ||
| 976 | # CONFIG_VIDEO_OV7670 is not set | ||
| 977 | # CONFIG_VIDEO_TCM825X is not set | ||
| 978 | # CONFIG_VIDEO_SAA711X is not set | ||
| 979 | # CONFIG_VIDEO_SAA717X is not set | ||
| 980 | # CONFIG_VIDEO_TVP514X is not set | ||
| 981 | # CONFIG_VIDEO_TVP5150 is not set | ||
| 982 | |||
| 983 | # | ||
| 984 | # Video and audio decoders | ||
| 985 | # | ||
| 986 | # CONFIG_VIDEO_CX25840 is not set | ||
| 987 | |||
| 988 | # | ||
| 989 | # MPEG video encoders | ||
| 990 | # | ||
| 991 | # CONFIG_VIDEO_CX2341X is not set | ||
| 992 | |||
| 993 | # | ||
| 994 | # Video encoders | ||
| 995 | # | ||
| 996 | # CONFIG_VIDEO_SAA7127 is not set | ||
| 997 | |||
| 998 | # | ||
| 999 | # Video improvement chips | ||
| 1000 | # | ||
| 1001 | # CONFIG_VIDEO_UPD64031A is not set | ||
| 1002 | # CONFIG_VIDEO_UPD64083 is not set | ||
| 1003 | # CONFIG_VIDEO_VIVI is not set | ||
| 1004 | # CONFIG_VIDEO_SAA5246A is not set | ||
| 1005 | # CONFIG_VIDEO_SAA5249 is not set | ||
| 1006 | CONFIG_SOC_CAMERA=m | ||
| 1007 | # CONFIG_SOC_CAMERA_MT9M001 is not set | ||
| 1008 | CONFIG_SOC_CAMERA_MT9M111=m | ||
| 1009 | # CONFIG_SOC_CAMERA_MT9T031 is not set | ||
| 1010 | # CONFIG_SOC_CAMERA_MT9V022 is not set | ||
| 1011 | # CONFIG_SOC_CAMERA_TW9910 is not set | ||
| 1012 | # CONFIG_SOC_CAMERA_PLATFORM is not set | ||
| 1013 | # CONFIG_SOC_CAMERA_OV772X is not set | ||
| 1014 | CONFIG_VIDEO_PXA27x=m | ||
| 1015 | # CONFIG_VIDEO_SH_MOBILE_CEU is not set | ||
| 1016 | # CONFIG_V4L_USB_DRIVERS is not set | ||
| 1017 | # CONFIG_RADIO_ADAPTERS is not set | ||
| 1018 | # CONFIG_DAB is not set | ||
| 1019 | |||
| 1020 | # | ||
| 1021 | # Graphics support | ||
| 1022 | # | ||
| 1023 | # CONFIG_VGASTATE is not set | ||
| 1024 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 1025 | CONFIG_FB=y | ||
| 1026 | # CONFIG_FIRMWARE_EDID is not set | ||
| 1027 | # CONFIG_FB_DDC is not set | ||
| 1028 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 1029 | CONFIG_FB_CFB_FILLRECT=y | ||
| 1030 | CONFIG_FB_CFB_COPYAREA=y | ||
| 1031 | CONFIG_FB_CFB_IMAGEBLIT=y | ||
| 1032 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 1033 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 1034 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 1035 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 1036 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 1037 | # CONFIG_FB_SYS_FOPS is not set | ||
| 1038 | # CONFIG_FB_SVGALIB is not set | ||
| 1039 | # CONFIG_FB_MACMODES is not set | ||
| 1040 | # CONFIG_FB_BACKLIGHT is not set | ||
| 1041 | # CONFIG_FB_MODE_HELPERS is not set | ||
| 1042 | # CONFIG_FB_TILEBLITTING is not set | ||
| 1043 | |||
| 1044 | # | ||
| 1045 | # Frame buffer hardware drivers | ||
| 1046 | # | ||
| 1047 | # CONFIG_FB_S1D13XXX is not set | ||
| 1048 | CONFIG_FB_PXA=y | ||
| 1049 | # CONFIG_FB_PXA_OVERLAY is not set | ||
| 1050 | # CONFIG_FB_PXA_SMARTPANEL is not set | ||
| 1051 | CONFIG_FB_PXA_PARAMETERS=y | ||
| 1052 | CONFIG_FB_MBX=m | ||
| 1053 | # CONFIG_FB_MBX_DEBUG is not set | ||
| 1054 | # CONFIG_FB_W100 is not set | ||
| 1055 | # CONFIG_FB_VIRTUAL is not set | ||
| 1056 | # CONFIG_FB_METRONOME is not set | ||
| 1057 | # CONFIG_FB_MB862XX is not set | ||
| 1058 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | ||
| 1059 | CONFIG_LCD_CLASS_DEVICE=y | ||
| 1060 | # CONFIG_LCD_LTV350QV is not set | ||
| 1061 | # CONFIG_LCD_ILI9320 is not set | ||
| 1062 | CONFIG_LCD_TDO24M=y | ||
| 1063 | # CONFIG_LCD_VGG2432A4 is not set | ||
| 1064 | # CONFIG_LCD_PLATFORM is not set | ||
| 1065 | CONFIG_BACKLIGHT_CLASS_DEVICE=m | ||
| 1066 | # CONFIG_BACKLIGHT_GENERIC is not set | ||
| 1067 | CONFIG_BACKLIGHT_DA903X=m | ||
| 1068 | |||
| 1069 | # | ||
| 1070 | # Display device support | ||
| 1071 | # | ||
| 1072 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 1073 | |||
| 1074 | # | ||
| 1075 | # Console display driver support | ||
| 1076 | # | ||
| 1077 | # CONFIG_VGA_CONSOLE is not set | ||
| 1078 | CONFIG_DUMMY_CONSOLE=y | ||
| 1079 | CONFIG_FRAMEBUFFER_CONSOLE=y | ||
| 1080 | # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set | ||
| 1081 | # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set | ||
| 1082 | # CONFIG_FONTS is not set | ||
| 1083 | CONFIG_FONT_8x8=y | ||
| 1084 | CONFIG_FONT_8x16=y | ||
| 1085 | CONFIG_LOGO=y | ||
| 1086 | CONFIG_LOGO_LINUX_MONO=y | ||
| 1087 | CONFIG_LOGO_LINUX_VGA16=y | ||
| 1088 | CONFIG_LOGO_LINUX_CLUT224=y | ||
| 1089 | CONFIG_SOUND=m | ||
| 1090 | CONFIG_SOUND_OSS_CORE=y | ||
| 1091 | CONFIG_SND=m | ||
| 1092 | CONFIG_SND_TIMER=m | ||
| 1093 | CONFIG_SND_PCM=m | ||
| 1094 | # CONFIG_SND_SEQUENCER is not set | ||
| 1095 | CONFIG_SND_OSSEMUL=y | ||
| 1096 | CONFIG_SND_MIXER_OSS=m | ||
| 1097 | CONFIG_SND_PCM_OSS=m | ||
| 1098 | CONFIG_SND_PCM_OSS_PLUGINS=y | ||
| 1099 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
| 1100 | CONFIG_SND_SUPPORT_OLD_API=y | ||
| 1101 | CONFIG_SND_VERBOSE_PROCFS=y | ||
| 1102 | # CONFIG_SND_VERBOSE_PRINTK is not set | ||
| 1103 | # CONFIG_SND_DEBUG is not set | ||
| 1104 | CONFIG_SND_VMASTER=y | ||
| 1105 | CONFIG_SND_AC97_CODEC=m | ||
| 1106 | # CONFIG_SND_DRIVERS is not set | ||
| 1107 | CONFIG_SND_ARM=y | ||
| 1108 | CONFIG_SND_PXA2XX_LIB=m | ||
| 1109 | CONFIG_SND_PXA2XX_LIB_AC97=y | ||
| 1110 | # CONFIG_SND_PXA2XX_AC97 is not set | ||
| 1111 | # CONFIG_SND_SPI is not set | ||
| 1112 | # CONFIG_SND_USB is not set | ||
| 1113 | CONFIG_SND_SOC=m | ||
| 1114 | CONFIG_SND_SOC_AC97_BUS=y | ||
| 1115 | CONFIG_SND_PXA2XX_SOC=m | ||
| 1116 | CONFIG_SND_PXA2XX_SOC_AC97=m | ||
| 1117 | CONFIG_SND_PXA2XX_SOC_EM_X270=m | ||
| 1118 | CONFIG_SND_SOC_I2C_AND_SPI=m | ||
| 1119 | # CONFIG_SND_SOC_ALL_CODECS is not set | ||
| 1120 | CONFIG_SND_SOC_WM9712=m | ||
| 1121 | # CONFIG_SOUND_PRIME is not set | ||
| 1122 | CONFIG_AC97_BUS=m | ||
| 1123 | CONFIG_HID_SUPPORT=y | ||
| 1124 | CONFIG_HID=y | ||
| 1125 | CONFIG_HID_DEBUG=y | ||
| 1126 | # CONFIG_HIDRAW is not set | ||
| 1127 | |||
| 1128 | # | ||
| 1129 | # USB Input Devices | ||
| 1130 | # | ||
| 1131 | CONFIG_USB_HID=y | ||
| 1132 | # CONFIG_HID_PID is not set | ||
| 1133 | # CONFIG_USB_HIDDEV is not set | ||
| 1134 | |||
| 1135 | # | ||
| 1136 | # Special HID drivers | ||
| 1137 | # | ||
| 1138 | CONFIG_HID_COMPAT=y | ||
| 1139 | CONFIG_HID_A4TECH=y | ||
| 1140 | CONFIG_HID_APPLE=y | ||
| 1141 | CONFIG_HID_BELKIN=y | ||
| 1142 | CONFIG_HID_CHERRY=y | ||
| 1143 | CONFIG_HID_CHICONY=y | ||
| 1144 | CONFIG_HID_CYPRESS=y | ||
| 1145 | CONFIG_HID_EZKEY=y | ||
| 1146 | CONFIG_HID_GYRATION=y | ||
| 1147 | CONFIG_HID_LOGITECH=y | ||
| 1148 | # CONFIG_LOGITECH_FF is not set | ||
| 1149 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | ||
| 1150 | CONFIG_HID_MICROSOFT=y | ||
| 1151 | CONFIG_HID_MONTEREY=y | ||
| 1152 | # CONFIG_HID_NTRIG is not set | ||
| 1153 | CONFIG_HID_PANTHERLORD=y | ||
| 1154 | # CONFIG_PANTHERLORD_FF is not set | ||
| 1155 | CONFIG_HID_PETALYNX=y | ||
| 1156 | CONFIG_HID_SAMSUNG=y | ||
| 1157 | CONFIG_HID_SONY=y | ||
| 1158 | CONFIG_HID_SUNPLUS=y | ||
| 1159 | # CONFIG_GREENASIA_FF is not set | ||
| 1160 | # CONFIG_HID_TOPSEED is not set | ||
| 1161 | # CONFIG_THRUSTMASTER_FF is not set | ||
| 1162 | # CONFIG_ZEROPLUS_FF is not set | ||
| 1163 | CONFIG_USB_SUPPORT=y | ||
| 1164 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 1165 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 1166 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 1167 | CONFIG_USB=y | ||
| 1168 | # CONFIG_USB_DEBUG is not set | ||
| 1169 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 1170 | |||
| 1171 | # | ||
| 1172 | # Miscellaneous USB options | ||
| 1173 | # | ||
| 1174 | CONFIG_USB_DEVICEFS=y | ||
| 1175 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 1176 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 1177 | # CONFIG_USB_SUSPEND is not set | ||
| 1178 | # CONFIG_USB_OTG is not set | ||
| 1179 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 1180 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
| 1181 | CONFIG_USB_MON=y | ||
| 1182 | # CONFIG_USB_WUSB is not set | ||
| 1183 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1184 | |||
| 1185 | # | ||
| 1186 | # USB Host Controller Drivers | ||
| 1187 | # | ||
| 1188 | # CONFIG_USB_C67X00_HCD is not set | ||
| 1189 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1190 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 1191 | CONFIG_USB_OHCI_HCD=y | ||
| 1192 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
| 1193 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 1194 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
| 1195 | # CONFIG_USB_SL811_HCD is not set | ||
| 1196 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 1197 | # CONFIG_USB_HWA_HCD is not set | ||
| 1198 | # CONFIG_USB_MUSB_HDRC is not set | ||
| 1199 | |||
| 1200 | # | ||
| 1201 | # USB Device Class drivers | ||
| 1202 | # | ||
| 1203 | # CONFIG_USB_ACM is not set | ||
| 1204 | # CONFIG_USB_PRINTER is not set | ||
| 1205 | # CONFIG_USB_WDM is not set | ||
| 1206 | # CONFIG_USB_TMC is not set | ||
| 1207 | |||
| 1208 | # | ||
| 1209 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; | ||
| 1210 | # | ||
| 1211 | |||
| 1212 | # | ||
| 1213 | # see USB_STORAGE Help for more information | ||
| 1214 | # | ||
| 1215 | CONFIG_USB_STORAGE=y | ||
| 1216 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 1217 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 1218 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 1219 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 1220 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 1221 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 1222 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 1223 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 1224 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 1225 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 1226 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 1227 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 1228 | # CONFIG_USB_LIBUSUAL is not set | ||
| 1229 | |||
| 1230 | # | ||
| 1231 | # USB Imaging devices | ||
| 1232 | # | ||
| 1233 | # CONFIG_USB_MDC800 is not set | ||
| 1234 | # CONFIG_USB_MICROTEK is not set | ||
| 1235 | |||
| 1236 | # | ||
| 1237 | # USB port drivers | ||
| 1238 | # | ||
| 1239 | # CONFIG_USB_SERIAL is not set | ||
| 1240 | |||
| 1241 | # | ||
| 1242 | # USB Miscellaneous drivers | ||
| 1243 | # | ||
| 1244 | # CONFIG_USB_EMI62 is not set | ||
| 1245 | # CONFIG_USB_EMI26 is not set | ||
| 1246 | # CONFIG_USB_ADUTUX is not set | ||
| 1247 | # CONFIG_USB_SEVSEG is not set | ||
| 1248 | # CONFIG_USB_RIO500 is not set | ||
| 1249 | # CONFIG_USB_LEGOTOWER is not set | ||
| 1250 | # CONFIG_USB_LCD is not set | ||
| 1251 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 1252 | # CONFIG_USB_LED is not set | ||
| 1253 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 1254 | # CONFIG_USB_CYTHERM is not set | ||
| 1255 | # CONFIG_USB_PHIDGET is not set | ||
| 1256 | # CONFIG_USB_IDMOUSE is not set | ||
| 1257 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 1258 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 1259 | # CONFIG_USB_LD is not set | ||
| 1260 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 1261 | # CONFIG_USB_IOWARRIOR is not set | ||
| 1262 | # CONFIG_USB_TEST is not set | ||
| 1263 | # CONFIG_USB_ISIGHTFW is not set | ||
| 1264 | # CONFIG_USB_VST is not set | ||
| 1265 | # CONFIG_USB_GADGET is not set | ||
| 1266 | |||
| 1267 | # | ||
| 1268 | # OTG and related infrastructure | ||
| 1269 | # | ||
| 1270 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1271 | CONFIG_MMC=m | ||
| 1272 | # CONFIG_MMC_DEBUG is not set | ||
| 1273 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 1274 | |||
| 1275 | # | ||
| 1276 | # MMC/SD/SDIO Card Drivers | ||
| 1277 | # | ||
| 1278 | CONFIG_MMC_BLOCK=m | ||
| 1279 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 1280 | # CONFIG_SDIO_UART is not set | ||
| 1281 | # CONFIG_MMC_TEST is not set | ||
| 1282 | |||
| 1283 | # | ||
| 1284 | # MMC/SD/SDIO Host Controller Drivers | ||
| 1285 | # | ||
| 1286 | CONFIG_MMC_PXA=m | ||
| 1287 | # CONFIG_MMC_SDHCI is not set | ||
| 1288 | # CONFIG_MMC_SPI is not set | ||
| 1289 | # CONFIG_MEMSTICK is not set | ||
| 1290 | # CONFIG_ACCESSIBILITY is not set | ||
| 1291 | CONFIG_NEW_LEDS=y | ||
| 1292 | CONFIG_LEDS_CLASS=y | ||
| 1293 | |||
| 1294 | # | ||
| 1295 | # LED drivers | ||
| 1296 | # | ||
| 1297 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1298 | # CONFIG_LEDS_GPIO is not set | ||
| 1299 | # CONFIG_LEDS_PCA955X is not set | ||
| 1300 | CONFIG_LEDS_DA903X=y | ||
| 1301 | |||
| 1302 | # | ||
| 1303 | # LED Triggers | ||
| 1304 | # | ||
| 1305 | CONFIG_LEDS_TRIGGERS=y | ||
| 1306 | # CONFIG_LEDS_TRIGGER_TIMER is not set | ||
| 1307 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 1308 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 1309 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | ||
| 1310 | CONFIG_RTC_LIB=y | ||
| 1311 | CONFIG_RTC_CLASS=y | ||
| 1312 | CONFIG_RTC_HCTOSYS=y | ||
| 1313 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 1314 | # CONFIG_RTC_DEBUG is not set | ||
| 1315 | |||
| 1316 | # | ||
| 1317 | # RTC interfaces | ||
| 1318 | # | ||
| 1319 | CONFIG_RTC_INTF_SYSFS=y | ||
| 1320 | CONFIG_RTC_INTF_PROC=y | ||
| 1321 | CONFIG_RTC_INTF_DEV=y | ||
| 1322 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 1323 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1324 | |||
| 1325 | # | ||
| 1326 | # I2C RTC drivers | ||
| 1327 | # | ||
| 1328 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 1329 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 1330 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 1331 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 1332 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 1333 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 1334 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 1335 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 1336 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 1337 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 1338 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1339 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1340 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1341 | |||
| 1342 | # | ||
| 1343 | # SPI RTC drivers | ||
| 1344 | # | ||
| 1345 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 1346 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1347 | # CONFIG_RTC_DRV_DS1390 is not set | ||
| 1348 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 1349 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1350 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1351 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1352 | |||
| 1353 | # | ||
| 1354 | # Platform RTC drivers | ||
| 1355 | # | ||
| 1356 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 1357 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1358 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1359 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1360 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1361 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1362 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1363 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1364 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1365 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1366 | CONFIG_RTC_DRV_V3020=y | ||
| 1367 | |||
| 1368 | # | ||
| 1369 | # on-CPU RTC drivers | ||
| 1370 | # | ||
| 1371 | CONFIG_RTC_DRV_SA1100=y | ||
| 1372 | # CONFIG_RTC_DRV_PXA is not set | ||
| 1373 | # CONFIG_DMADEVICES is not set | ||
| 1374 | CONFIG_REGULATOR=y | ||
| 1375 | # CONFIG_REGULATOR_DEBUG is not set | ||
| 1376 | # CONFIG_REGULATOR_FIXED_VOLTAGE is not set | ||
| 1377 | # CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set | ||
| 1378 | # CONFIG_REGULATOR_BQ24022 is not set | ||
| 1379 | CONFIG_REGULATOR_DA903X=y | ||
| 1380 | # CONFIG_UIO is not set | ||
| 1381 | # CONFIG_STAGING is not set | ||
| 1382 | |||
| 1383 | # | ||
| 1384 | # File systems | ||
| 1385 | # | ||
| 1386 | CONFIG_EXT2_FS=y | ||
| 1387 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 1388 | # CONFIG_EXT2_FS_XIP is not set | ||
| 1389 | CONFIG_EXT3_FS=y | ||
| 1390 | CONFIG_EXT3_FS_XATTR=y | ||
| 1391 | # CONFIG_EXT3_FS_POSIX_ACL is not set | ||
| 1392 | # CONFIG_EXT3_FS_SECURITY is not set | ||
| 1393 | # CONFIG_EXT4_FS is not set | ||
| 1394 | CONFIG_JBD=y | ||
| 1395 | # CONFIG_JBD_DEBUG is not set | ||
| 1396 | CONFIG_FS_MBCACHE=y | ||
| 1397 | # CONFIG_REISERFS_FS is not set | ||
| 1398 | # CONFIG_JFS_FS is not set | ||
| 1399 | # CONFIG_FS_POSIX_ACL is not set | ||
| 1400 | CONFIG_FILE_LOCKING=y | ||
| 1401 | # CONFIG_XFS_FS is not set | ||
| 1402 | # CONFIG_OCFS2_FS is not set | ||
| 1403 | # CONFIG_BTRFS_FS is not set | ||
| 1404 | CONFIG_DNOTIFY=y | ||
| 1405 | CONFIG_INOTIFY=y | ||
| 1406 | CONFIG_INOTIFY_USER=y | ||
| 1407 | # CONFIG_QUOTA is not set | ||
| 1408 | # CONFIG_AUTOFS_FS is not set | ||
| 1409 | # CONFIG_AUTOFS4_FS is not set | ||
| 1410 | # CONFIG_FUSE_FS is not set | ||
| 1411 | |||
| 1412 | # | ||
| 1413 | # CD-ROM/DVD Filesystems | ||
| 1414 | # | ||
| 1415 | # CONFIG_ISO9660_FS is not set | ||
| 1416 | # CONFIG_UDF_FS is not set | ||
| 1417 | |||
| 1418 | # | ||
| 1419 | # DOS/FAT/NT Filesystems | ||
| 1420 | # | ||
| 1421 | CONFIG_FAT_FS=m | ||
| 1422 | # CONFIG_MSDOS_FS is not set | ||
| 1423 | CONFIG_VFAT_FS=m | ||
| 1424 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1425 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1426 | # CONFIG_NTFS_FS is not set | ||
| 1427 | |||
| 1428 | # | ||
| 1429 | # Pseudo filesystems | ||
| 1430 | # | ||
| 1431 | CONFIG_PROC_FS=y | ||
| 1432 | CONFIG_PROC_SYSCTL=y | ||
| 1433 | # CONFIG_PROC_PAGE_MONITOR is not set | ||
| 1434 | CONFIG_SYSFS=y | ||
| 1435 | CONFIG_TMPFS=y | ||
| 1436 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1437 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1438 | # CONFIG_CONFIGFS_FS is not set | ||
| 1439 | CONFIG_MISC_FILESYSTEMS=y | ||
| 1440 | # CONFIG_ADFS_FS is not set | ||
| 1441 | # CONFIG_AFFS_FS is not set | ||
| 1442 | # CONFIG_HFS_FS is not set | ||
| 1443 | # CONFIG_HFSPLUS_FS is not set | ||
| 1444 | # CONFIG_BEFS_FS is not set | ||
| 1445 | # CONFIG_BFS_FS is not set | ||
| 1446 | # CONFIG_EFS_FS is not set | ||
| 1447 | CONFIG_JFFS2_FS=y | ||
| 1448 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 1449 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 1450 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1451 | CONFIG_JFFS2_SUMMARY=y | ||
| 1452 | # CONFIG_JFFS2_FS_XATTR is not set | ||
| 1453 | # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set | ||
| 1454 | CONFIG_JFFS2_ZLIB=y | ||
| 1455 | # CONFIG_JFFS2_LZO is not set | ||
| 1456 | CONFIG_JFFS2_RTIME=y | ||
| 1457 | # CONFIG_JFFS2_RUBIN is not set | ||
| 1458 | # CONFIG_CRAMFS is not set | ||
| 1459 | # CONFIG_SQUASHFS is not set | ||
| 1460 | # CONFIG_VXFS_FS is not set | ||
| 1461 | # CONFIG_MINIX_FS is not set | ||
| 1462 | # CONFIG_OMFS_FS is not set | ||
| 1463 | # CONFIG_HPFS_FS is not set | ||
| 1464 | # CONFIG_QNX4FS_FS is not set | ||
| 1465 | # CONFIG_ROMFS_FS is not set | ||
| 1466 | # CONFIG_SYSV_FS is not set | ||
| 1467 | # CONFIG_UFS_FS is not set | ||
| 1468 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1469 | CONFIG_NFS_FS=y | ||
| 1470 | CONFIG_NFS_V3=y | ||
| 1471 | # CONFIG_NFS_V3_ACL is not set | ||
| 1472 | # CONFIG_NFS_V4 is not set | ||
| 1473 | CONFIG_ROOT_NFS=y | ||
| 1474 | # CONFIG_NFSD is not set | ||
| 1475 | CONFIG_LOCKD=y | ||
| 1476 | CONFIG_LOCKD_V4=y | ||
| 1477 | CONFIG_NFS_COMMON=y | ||
| 1478 | CONFIG_SUNRPC=y | ||
| 1479 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 1480 | # CONFIG_RPCSEC_GSS_KRB5 is not set | ||
| 1481 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1482 | # CONFIG_SMB_FS is not set | ||
| 1483 | CONFIG_CIFS=m | ||
| 1484 | # CONFIG_CIFS_STATS is not set | ||
| 1485 | # CONFIG_CIFS_WEAK_PW_HASH is not set | ||
| 1486 | # CONFIG_CIFS_XATTR is not set | ||
| 1487 | # CONFIG_CIFS_DEBUG2 is not set | ||
| 1488 | # CONFIG_CIFS_EXPERIMENTAL is not set | ||
| 1489 | # CONFIG_NCP_FS is not set | ||
| 1490 | # CONFIG_CODA_FS is not set | ||
| 1491 | # CONFIG_AFS_FS is not set | ||
| 1492 | |||
| 1493 | # | ||
| 1494 | # Partition Types | ||
| 1495 | # | ||
| 1496 | CONFIG_PARTITION_ADVANCED=y | ||
| 1497 | # CONFIG_ACORN_PARTITION is not set | ||
| 1498 | # CONFIG_OSF_PARTITION is not set | ||
| 1499 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1500 | # CONFIG_ATARI_PARTITION is not set | ||
| 1501 | # CONFIG_MAC_PARTITION is not set | ||
| 1502 | CONFIG_MSDOS_PARTITION=y | ||
| 1503 | # CONFIG_BSD_DISKLABEL is not set | ||
| 1504 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 1505 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 1506 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 1507 | # CONFIG_LDM_PARTITION is not set | ||
| 1508 | # CONFIG_SGI_PARTITION is not set | ||
| 1509 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1510 | # CONFIG_SUN_PARTITION is not set | ||
| 1511 | # CONFIG_KARMA_PARTITION is not set | ||
| 1512 | # CONFIG_EFI_PARTITION is not set | ||
| 1513 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1514 | CONFIG_NLS=m | ||
| 1515 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1516 | CONFIG_NLS_CODEPAGE_437=m | ||
| 1517 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1518 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1519 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1520 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1521 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1522 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1523 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1524 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1525 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1526 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1527 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1528 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1529 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1530 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1531 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1532 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1533 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1534 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1535 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1536 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1537 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1538 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1539 | # CONFIG_NLS_ASCII is not set | ||
| 1540 | CONFIG_NLS_ISO8859_1=m | ||
| 1541 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1542 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1543 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1544 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1545 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1546 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1547 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1548 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1549 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1550 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1551 | # CONFIG_NLS_KOI8_R is not set | ||
| 1552 | # CONFIG_NLS_KOI8_U is not set | ||
| 1553 | CONFIG_NLS_UTF8=m | ||
| 1554 | # CONFIG_DLM is not set | ||
| 1555 | |||
| 1556 | # | ||
| 1557 | # Kernel hacking | ||
| 1558 | # | ||
| 1559 | # CONFIG_PRINTK_TIME is not set | ||
| 1560 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1561 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1562 | CONFIG_FRAME_WARN=0 | ||
| 1563 | # CONFIG_MAGIC_SYSRQ is not set | ||
| 1564 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1565 | CONFIG_DEBUG_FS=y | ||
| 1566 | # CONFIG_HEADERS_CHECK is not set | ||
| 1567 | CONFIG_DEBUG_KERNEL=y | ||
| 1568 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1569 | # CONFIG_DETECT_SOFTLOCKUP is not set | ||
| 1570 | # CONFIG_SCHED_DEBUG is not set | ||
| 1571 | # CONFIG_SCHEDSTATS is not set | ||
| 1572 | # CONFIG_TIMER_STATS is not set | ||
| 1573 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1574 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1575 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1576 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1577 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1578 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1579 | # CONFIG_PROVE_LOCKING is not set | ||
| 1580 | # CONFIG_LOCK_STAT is not set | ||
| 1581 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1582 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1583 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1584 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 1585 | # CONFIG_DEBUG_INFO is not set | ||
| 1586 | # CONFIG_DEBUG_VM is not set | ||
| 1587 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1588 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1589 | # CONFIG_DEBUG_LIST is not set | ||
| 1590 | # CONFIG_DEBUG_SG is not set | ||
| 1591 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1592 | CONFIG_FRAME_POINTER=y | ||
| 1593 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1594 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1595 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1596 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1597 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1598 | # CONFIG_FAULT_INJECTION is not set | ||
| 1599 | # CONFIG_LATENCYTOP is not set | ||
| 1600 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 1601 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1602 | |||
| 1603 | # | ||
| 1604 | # Tracers | ||
| 1605 | # | ||
| 1606 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1607 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1608 | # CONFIG_SCHED_TRACER is not set | ||
| 1609 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1610 | # CONFIG_BOOT_TRACER is not set | ||
| 1611 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1612 | # CONFIG_STACK_TRACER is not set | ||
| 1613 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1614 | # CONFIG_SAMPLES is not set | ||
| 1615 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1616 | # CONFIG_KGDB is not set | ||
| 1617 | CONFIG_DEBUG_USER=y | ||
| 1618 | CONFIG_DEBUG_ERRORS=y | ||
| 1619 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1620 | CONFIG_DEBUG_LL=y | ||
| 1621 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 1622 | |||
| 1623 | # | ||
| 1624 | # Security options | ||
| 1625 | # | ||
| 1626 | # CONFIG_KEYS is not set | ||
| 1627 | # CONFIG_SECURITY is not set | ||
| 1628 | # CONFIG_SECURITYFS is not set | ||
| 1629 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1630 | CONFIG_CRYPTO=y | ||
| 1631 | |||
| 1632 | # | ||
| 1633 | # Crypto core or helper | ||
| 1634 | # | ||
| 1635 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1636 | CONFIG_CRYPTO_ALGAPI=m | ||
| 1637 | CONFIG_CRYPTO_ALGAPI2=m | ||
| 1638 | CONFIG_CRYPTO_AEAD2=m | ||
| 1639 | CONFIG_CRYPTO_BLKCIPHER=m | ||
| 1640 | CONFIG_CRYPTO_BLKCIPHER2=m | ||
| 1641 | CONFIG_CRYPTO_HASH=m | ||
| 1642 | CONFIG_CRYPTO_HASH2=m | ||
| 1643 | CONFIG_CRYPTO_RNG2=m | ||
| 1644 | CONFIG_CRYPTO_MANAGER=m | ||
| 1645 | CONFIG_CRYPTO_MANAGER2=m | ||
| 1646 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1647 | # CONFIG_CRYPTO_NULL is not set | ||
| 1648 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1649 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1650 | # CONFIG_CRYPTO_TEST is not set | ||
| 1651 | |||
| 1652 | # | ||
| 1653 | # Authenticated Encryption with Associated Data | ||
| 1654 | # | ||
| 1655 | # CONFIG_CRYPTO_CCM is not set | ||
| 1656 | # CONFIG_CRYPTO_GCM is not set | ||
| 1657 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1658 | |||
| 1659 | # | ||
| 1660 | # Block modes | ||
| 1661 | # | ||
| 1662 | # CONFIG_CRYPTO_CBC is not set | ||
| 1663 | # CONFIG_CRYPTO_CTR is not set | ||
| 1664 | # CONFIG_CRYPTO_CTS is not set | ||
| 1665 | CONFIG_CRYPTO_ECB=m | ||
| 1666 | # CONFIG_CRYPTO_LRW is not set | ||
| 1667 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1668 | # CONFIG_CRYPTO_XTS is not set | ||
| 1669 | |||
| 1670 | # | ||
| 1671 | # Hash modes | ||
| 1672 | # | ||
| 1673 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1674 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1675 | |||
| 1676 | # | ||
| 1677 | # Digest | ||
| 1678 | # | ||
| 1679 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1680 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1681 | # CONFIG_CRYPTO_MD5 is not set | ||
| 1682 | CONFIG_CRYPTO_MICHAEL_MIC=m | ||
| 1683 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1684 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1685 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1686 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1687 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1688 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1689 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1690 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1691 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1692 | |||
| 1693 | # | ||
| 1694 | # Ciphers | ||
| 1695 | # | ||
| 1696 | CONFIG_CRYPTO_AES=m | ||
| 1697 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1698 | CONFIG_CRYPTO_ARC4=m | ||
| 1699 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1700 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1701 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1702 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1703 | # CONFIG_CRYPTO_DES is not set | ||
| 1704 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1705 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1706 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1707 | # CONFIG_CRYPTO_SEED is not set | ||
| 1708 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1709 | # CONFIG_CRYPTO_TEA is not set | ||
| 1710 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1711 | |||
| 1712 | # | ||
| 1713 | # Compression | ||
| 1714 | # | ||
| 1715 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 1716 | # CONFIG_CRYPTO_LZO is not set | ||
| 1717 | |||
| 1718 | # | ||
| 1719 | # Random Number Generation | ||
| 1720 | # | ||
| 1721 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1722 | # CONFIG_CRYPTO_HW is not set | ||
| 1723 | |||
| 1724 | # | ||
| 1725 | # Library routines | ||
| 1726 | # | ||
| 1727 | CONFIG_BITREVERSE=y | ||
| 1728 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1729 | CONFIG_CRC_CCITT=m | ||
| 1730 | # CONFIG_CRC16 is not set | ||
| 1731 | # CONFIG_CRC_T10DIF is not set | ||
| 1732 | # CONFIG_CRC_ITU_T is not set | ||
| 1733 | CONFIG_CRC32=y | ||
| 1734 | # CONFIG_CRC7 is not set | ||
| 1735 | # CONFIG_LIBCRC32C is not set | ||
| 1736 | CONFIG_ZLIB_INFLATE=y | ||
| 1737 | CONFIG_ZLIB_DEFLATE=y | ||
| 1738 | CONFIG_PLIST=y | ||
| 1739 | CONFIG_HAS_IOMEM=y | ||
| 1740 | CONFIG_HAS_IOPORT=y | ||
| 1741 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig index 8f986e9f1c62..1502957db2c3 100644 --- a/arch/arm/configs/h3600_defconfig +++ b/arch/arm/configs/h3600_defconfig | |||
| @@ -90,7 +90,6 @@ CONFIG_ARCH_SA1100=y | |||
| 90 | # CONFIG_SA1100_COLLIE is not set | 90 | # CONFIG_SA1100_COLLIE is not set |
| 91 | # CONFIG_SA1100_H3100 is not set | 91 | # CONFIG_SA1100_H3100 is not set |
| 92 | CONFIG_SA1100_H3600=y | 92 | CONFIG_SA1100_H3600=y |
| 93 | # CONFIG_SA1100_H3800 is not set | ||
| 94 | CONFIG_SA1100_H3XXX=y | 93 | CONFIG_SA1100_H3XXX=y |
| 95 | # CONFIG_SA1100_BADGE4 is not set | 94 | # CONFIG_SA1100_BADGE4 is not set |
| 96 | # CONFIG_SA1100_JORNADA720 is not set | 95 | # CONFIG_SA1100_JORNADA720 is not set |
| @@ -100,7 +99,6 @@ CONFIG_SA1100_H3XXX=y | |||
| 100 | # CONFIG_SA1100_SHANNON is not set | 99 | # CONFIG_SA1100_SHANNON is not set |
| 101 | # CONFIG_SA1100_SIMPAD is not set | 100 | # CONFIG_SA1100_SIMPAD is not set |
| 102 | # CONFIG_SA1100_SSP is not set | 101 | # CONFIG_SA1100_SSP is not set |
| 103 | # CONFIG_H3600_SLEEVE is not set | ||
| 104 | 102 | ||
| 105 | # | 103 | # |
| 106 | # Processor Type | 104 | # Processor Type |
diff --git a/arch/arm/configs/hackkit_defconfig b/arch/arm/configs/hackkit_defconfig index 1c8fb89a6730..db0708d5cbea 100644 --- a/arch/arm/configs/hackkit_defconfig +++ b/arch/arm/configs/hackkit_defconfig | |||
| @@ -91,7 +91,6 @@ CONFIG_ARCH_SA1100=y | |||
| 91 | # CONFIG_SA1100_COLLIE is not set | 91 | # CONFIG_SA1100_COLLIE is not set |
| 92 | # CONFIG_SA1100_H3100 is not set | 92 | # CONFIG_SA1100_H3100 is not set |
| 93 | # CONFIG_SA1100_H3600 is not set | 93 | # CONFIG_SA1100_H3600 is not set |
| 94 | # CONFIG_SA1100_H3800 is not set | ||
| 95 | # CONFIG_SA1100_BADGE4 is not set | 94 | # CONFIG_SA1100_BADGE4 is not set |
| 96 | # CONFIG_SA1100_JORNADA720 is not set | 95 | # CONFIG_SA1100_JORNADA720 is not set |
| 97 | CONFIG_SA1100_HACKKIT=y | 96 | CONFIG_SA1100_HACKKIT=y |
diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig index 81fadafae02d..f3074e49f2fa 100644 --- a/arch/arm/configs/jornada720_defconfig +++ b/arch/arm/configs/jornada720_defconfig | |||
| @@ -178,7 +178,6 @@ CONFIG_DMABOUNCE=y | |||
| 178 | # CONFIG_SA1100_COLLIE is not set | 178 | # CONFIG_SA1100_COLLIE is not set |
| 179 | # CONFIG_SA1100_H3100 is not set | 179 | # CONFIG_SA1100_H3100 is not set |
| 180 | # CONFIG_SA1100_H3600 is not set | 180 | # CONFIG_SA1100_H3600 is not set |
| 181 | # CONFIG_SA1100_H3800 is not set | ||
| 182 | # CONFIG_SA1100_BADGE4 is not set | 181 | # CONFIG_SA1100_BADGE4 is not set |
| 183 | CONFIG_SA1100_JORNADA720=y | 182 | CONFIG_SA1100_JORNADA720=y |
| 184 | CONFIG_SA1100_JORNADA720_SSP=y | 183 | CONFIG_SA1100_JORNADA720_SSP=y |
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig index 4bc38078d580..c367ae44012e 100644 --- a/arch/arm/configs/kirkwood_defconfig +++ b/arch/arm/configs/kirkwood_defconfig | |||
| @@ -1,11 +1,11 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.28-rc7 | 3 | # Linux kernel version: 2.6.29-rc5 |
| 4 | # Thu Dec 4 15:27:39 2008 | 4 | # Tue Mar 3 21:45:57 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| 8 | # CONFIG_GENERIC_GPIO is not set | 8 | CONFIG_GENERIC_GPIO=y |
| 9 | CONFIG_GENERIC_TIME=y | 9 | CONFIG_GENERIC_TIME=y |
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | 10 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 11 | CONFIG_MMU=y | 11 | CONFIG_MMU=y |
| @@ -42,10 +42,19 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 42 | # CONFIG_BSD_PROCESS_ACCT is not set | 42 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 43 | # CONFIG_TASKSTATS is not set | 43 | # CONFIG_TASKSTATS is not set |
| 44 | # CONFIG_AUDIT is not set | 44 | # CONFIG_AUDIT is not set |
| 45 | |||
| 46 | # | ||
| 47 | # RCU Subsystem | ||
| 48 | # | ||
| 49 | CONFIG_CLASSIC_RCU=y | ||
| 50 | # CONFIG_TREE_RCU is not set | ||
| 51 | # CONFIG_PREEMPT_RCU is not set | ||
| 52 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 53 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 45 | # CONFIG_IKCONFIG is not set | 54 | # CONFIG_IKCONFIG is not set |
| 46 | CONFIG_LOG_BUF_SHIFT=14 | 55 | CONFIG_LOG_BUF_SHIFT=19 |
| 47 | # CONFIG_CGROUPS is not set | ||
| 48 | # CONFIG_GROUP_SCHED is not set | 56 | # CONFIG_GROUP_SCHED is not set |
| 57 | # CONFIG_CGROUPS is not set | ||
| 49 | # CONFIG_SYSFS_DEPRECATED_V2 is not set | 58 | # CONFIG_SYSFS_DEPRECATED_V2 is not set |
| 50 | # CONFIG_RELAY is not set | 59 | # CONFIG_RELAY is not set |
| 51 | CONFIG_NAMESPACES=y | 60 | CONFIG_NAMESPACES=y |
| @@ -53,6 +62,7 @@ CONFIG_NAMESPACES=y | |||
| 53 | # CONFIG_IPC_NS is not set | 62 | # CONFIG_IPC_NS is not set |
| 54 | # CONFIG_USER_NS is not set | 63 | # CONFIG_USER_NS is not set |
| 55 | # CONFIG_PID_NS is not set | 64 | # CONFIG_PID_NS is not set |
| 65 | # CONFIG_NET_NS is not set | ||
| 56 | # CONFIG_BLK_DEV_INITRD is not set | 66 | # CONFIG_BLK_DEV_INITRD is not set |
| 57 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 67 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 58 | CONFIG_SYSCTL=y | 68 | CONFIG_SYSCTL=y |
| @@ -83,6 +93,7 @@ CONFIG_SLUB_DEBUG=y | |||
| 83 | CONFIG_SLUB=y | 93 | CONFIG_SLUB=y |
| 84 | # CONFIG_SLOB is not set | 94 | # CONFIG_SLOB is not set |
| 85 | CONFIG_PROFILING=y | 95 | CONFIG_PROFILING=y |
| 96 | CONFIG_TRACEPOINTS=y | ||
| 86 | # CONFIG_MARKERS is not set | 97 | # CONFIG_MARKERS is not set |
| 87 | CONFIG_OPROFILE=y | 98 | CONFIG_OPROFILE=y |
| 88 | CONFIG_HAVE_OPROFILE=y | 99 | CONFIG_HAVE_OPROFILE=y |
| @@ -93,7 +104,6 @@ CONFIG_HAVE_KRETPROBES=y | |||
| 93 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | 104 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y |
| 94 | CONFIG_SLABINFO=y | 105 | CONFIG_SLABINFO=y |
| 95 | CONFIG_RT_MUTEXES=y | 106 | CONFIG_RT_MUTEXES=y |
| 96 | # CONFIG_TINY_SHMEM is not set | ||
| 97 | CONFIG_BASE_SMALL=0 | 107 | CONFIG_BASE_SMALL=0 |
| 98 | CONFIG_MODULES=y | 108 | CONFIG_MODULES=y |
| 99 | # CONFIG_MODULE_FORCE_LOAD is not set | 109 | # CONFIG_MODULE_FORCE_LOAD is not set |
| @@ -101,11 +111,9 @@ CONFIG_MODULE_UNLOAD=y | |||
| 101 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 111 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 102 | # CONFIG_MODVERSIONS is not set | 112 | # CONFIG_MODVERSIONS is not set |
| 103 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 113 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 104 | CONFIG_KMOD=y | ||
| 105 | CONFIG_BLOCK=y | 114 | CONFIG_BLOCK=y |
| 106 | # CONFIG_LBD is not set | 115 | # CONFIG_LBD is not set |
| 107 | # CONFIG_BLK_DEV_IO_TRACE is not set | 116 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 108 | # CONFIG_LSF is not set | ||
| 109 | # CONFIG_BLK_DEV_BSG is not set | 117 | # CONFIG_BLK_DEV_BSG is not set |
| 110 | # CONFIG_BLK_DEV_INTEGRITY is not set | 118 | # CONFIG_BLK_DEV_INTEGRITY is not set |
| 111 | 119 | ||
| @@ -121,7 +129,6 @@ CONFIG_IOSCHED_CFQ=y | |||
| 121 | CONFIG_DEFAULT_CFQ=y | 129 | CONFIG_DEFAULT_CFQ=y |
| 122 | # CONFIG_DEFAULT_NOOP is not set | 130 | # CONFIG_DEFAULT_NOOP is not set |
| 123 | CONFIG_DEFAULT_IOSCHED="cfq" | 131 | CONFIG_DEFAULT_IOSCHED="cfq" |
| 124 | CONFIG_CLASSIC_RCU=y | ||
| 125 | # CONFIG_FREEZER is not set | 132 | # CONFIG_FREEZER is not set |
| 126 | 133 | ||
| 127 | # | 134 | # |
| @@ -132,7 +139,6 @@ CONFIG_CLASSIC_RCU=y | |||
| 132 | # CONFIG_ARCH_REALVIEW is not set | 139 | # CONFIG_ARCH_REALVIEW is not set |
| 133 | # CONFIG_ARCH_VERSATILE is not set | 140 | # CONFIG_ARCH_VERSATILE is not set |
| 134 | # CONFIG_ARCH_AT91 is not set | 141 | # CONFIG_ARCH_AT91 is not set |
| 135 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 136 | # CONFIG_ARCH_CLPS711X is not set | 142 | # CONFIG_ARCH_CLPS711X is not set |
| 137 | # CONFIG_ARCH_EBSA110 is not set | 143 | # CONFIG_ARCH_EBSA110 is not set |
| 138 | # CONFIG_ARCH_EP93XX is not set | 144 | # CONFIG_ARCH_EP93XX is not set |
| @@ -159,11 +165,13 @@ CONFIG_ARCH_KIRKWOOD=y | |||
| 159 | # CONFIG_ARCH_RPC is not set | 165 | # CONFIG_ARCH_RPC is not set |
| 160 | # CONFIG_ARCH_SA1100 is not set | 166 | # CONFIG_ARCH_SA1100 is not set |
| 161 | # CONFIG_ARCH_S3C2410 is not set | 167 | # CONFIG_ARCH_S3C2410 is not set |
| 168 | # CONFIG_ARCH_S3C64XX is not set | ||
| 162 | # CONFIG_ARCH_SHARK is not set | 169 | # CONFIG_ARCH_SHARK is not set |
| 163 | # CONFIG_ARCH_LH7A40X is not set | 170 | # CONFIG_ARCH_LH7A40X is not set |
| 164 | # CONFIG_ARCH_DAVINCI is not set | 171 | # CONFIG_ARCH_DAVINCI is not set |
| 165 | # CONFIG_ARCH_OMAP is not set | 172 | # CONFIG_ARCH_OMAP is not set |
| 166 | # CONFIG_ARCH_MSM is not set | 173 | # CONFIG_ARCH_MSM is not set |
| 174 | # CONFIG_ARCH_W90X900 is not set | ||
| 167 | 175 | ||
| 168 | # | 176 | # |
| 169 | # Marvell Kirkwood Implementations | 177 | # Marvell Kirkwood Implementations |
| @@ -171,14 +179,8 @@ CONFIG_ARCH_KIRKWOOD=y | |||
| 171 | CONFIG_MACH_DB88F6281_BP=y | 179 | CONFIG_MACH_DB88F6281_BP=y |
| 172 | CONFIG_MACH_RD88F6192_NAS=y | 180 | CONFIG_MACH_RD88F6192_NAS=y |
| 173 | CONFIG_MACH_RD88F6281=y | 181 | CONFIG_MACH_RD88F6281=y |
| 174 | 182 | CONFIG_MACH_SHEEVAPLUG=y | |
| 175 | # | 183 | CONFIG_MACH_TS219=y |
| 176 | # Boot options | ||
| 177 | # | ||
| 178 | |||
| 179 | # | ||
| 180 | # Power management | ||
| 181 | # | ||
| 182 | CONFIG_PLAT_ORION=y | 184 | CONFIG_PLAT_ORION=y |
| 183 | 185 | ||
| 184 | # | 186 | # |
| @@ -214,6 +216,7 @@ CONFIG_PCI_SYSCALL=y | |||
| 214 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 216 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 215 | CONFIG_PCI_LEGACY=y | 217 | CONFIG_PCI_LEGACY=y |
| 216 | # CONFIG_PCI_DEBUG is not set | 218 | # CONFIG_PCI_DEBUG is not set |
| 219 | # CONFIG_PCI_STUB is not set | ||
| 217 | # CONFIG_PCCARD is not set | 220 | # CONFIG_PCCARD is not set |
| 218 | 221 | ||
| 219 | # | 222 | # |
| @@ -242,7 +245,6 @@ CONFIG_FLATMEM=y | |||
| 242 | CONFIG_FLAT_NODE_MEM_MAP=y | 245 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 243 | CONFIG_PAGEFLAGS_EXTENDED=y | 246 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 244 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 247 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 245 | # CONFIG_RESOURCES_64BIT is not set | ||
| 246 | # CONFIG_PHYS_ADDR_T_64BIT is not set | 248 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 247 | CONFIG_ZONE_DMA_FLAG=0 | 249 | CONFIG_ZONE_DMA_FLAG=0 |
| 248 | CONFIG_VIRT_TO_BUS=y | 250 | CONFIG_VIRT_TO_BUS=y |
| @@ -291,6 +293,7 @@ CONFIG_NET=y | |||
| 291 | # | 293 | # |
| 292 | # Networking options | 294 | # Networking options |
| 293 | # | 295 | # |
| 296 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 294 | CONFIG_PACKET=y | 297 | CONFIG_PACKET=y |
| 295 | CONFIG_PACKET_MMAP=y | 298 | CONFIG_PACKET_MMAP=y |
| 296 | CONFIG_UNIX=y | 299 | CONFIG_UNIX=y |
| @@ -355,6 +358,7 @@ CONFIG_NET_DSA_MV88E6123_61_65=y | |||
| 355 | # CONFIG_ECONET is not set | 358 | # CONFIG_ECONET is not set |
| 356 | # CONFIG_WAN_ROUTER is not set | 359 | # CONFIG_WAN_ROUTER is not set |
| 357 | # CONFIG_NET_SCHED is not set | 360 | # CONFIG_NET_SCHED is not set |
| 361 | # CONFIG_DCB is not set | ||
| 358 | 362 | ||
| 359 | # | 363 | # |
| 360 | # Network testing | 364 | # Network testing |
| @@ -368,12 +372,27 @@ CONFIG_NET_PKTGEN=m | |||
| 368 | # CONFIG_AF_RXRPC is not set | 372 | # CONFIG_AF_RXRPC is not set |
| 369 | # CONFIG_PHONET is not set | 373 | # CONFIG_PHONET is not set |
| 370 | CONFIG_WIRELESS=y | 374 | CONFIG_WIRELESS=y |
| 371 | # CONFIG_CFG80211 is not set | 375 | CONFIG_CFG80211=y |
| 376 | # CONFIG_CFG80211_REG_DEBUG is not set | ||
| 377 | # CONFIG_NL80211 is not set | ||
| 372 | CONFIG_WIRELESS_OLD_REGULATORY=y | 378 | CONFIG_WIRELESS_OLD_REGULATORY=y |
| 373 | CONFIG_WIRELESS_EXT=y | 379 | CONFIG_WIRELESS_EXT=y |
| 374 | CONFIG_WIRELESS_EXT_SYSFS=y | 380 | CONFIG_WIRELESS_EXT_SYSFS=y |
| 375 | # CONFIG_MAC80211 is not set | 381 | CONFIG_LIB80211=y |
| 376 | # CONFIG_IEEE80211 is not set | 382 | CONFIG_MAC80211=y |
| 383 | |||
| 384 | # | ||
| 385 | # Rate control algorithm selection | ||
| 386 | # | ||
| 387 | CONFIG_MAC80211_RC_MINSTREL=y | ||
| 388 | # CONFIG_MAC80211_RC_DEFAULT_PID is not set | ||
| 389 | CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y | ||
| 390 | CONFIG_MAC80211_RC_DEFAULT="minstrel" | ||
| 391 | # CONFIG_MAC80211_MESH is not set | ||
| 392 | # CONFIG_MAC80211_LEDS is not set | ||
| 393 | # CONFIG_MAC80211_DEBUGFS is not set | ||
| 394 | # CONFIG_MAC80211_DEBUG_MENU is not set | ||
| 395 | # CONFIG_WIMAX is not set | ||
| 377 | # CONFIG_RFKILL is not set | 396 | # CONFIG_RFKILL is not set |
| 378 | # CONFIG_NET_9P is not set | 397 | # CONFIG_NET_9P is not set |
| 379 | 398 | ||
| @@ -398,6 +417,7 @@ CONFIG_MTD=y | |||
| 398 | # CONFIG_MTD_DEBUG is not set | 417 | # CONFIG_MTD_DEBUG is not set |
| 399 | # CONFIG_MTD_CONCAT is not set | 418 | # CONFIG_MTD_CONCAT is not set |
| 400 | CONFIG_MTD_PARTITIONS=y | 419 | CONFIG_MTD_PARTITIONS=y |
| 420 | # CONFIG_MTD_TESTS is not set | ||
| 401 | # CONFIG_MTD_REDBOOT_PARTS is not set | 421 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 402 | CONFIG_MTD_CMDLINE_PARTS=y | 422 | CONFIG_MTD_CMDLINE_PARTS=y |
| 403 | # CONFIG_MTD_AFS_PARTS is not set | 423 | # CONFIG_MTD_AFS_PARTS is not set |
| @@ -451,9 +471,7 @@ CONFIG_MTD_CFI_UTIL=y | |||
| 451 | # | 471 | # |
| 452 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | 472 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set |
| 453 | CONFIG_MTD_PHYSMAP=y | 473 | CONFIG_MTD_PHYSMAP=y |
| 454 | CONFIG_MTD_PHYSMAP_START=0x0 | 474 | # CONFIG_MTD_PHYSMAP_COMPAT is not set |
| 455 | CONFIG_MTD_PHYSMAP_LEN=0x0 | ||
| 456 | CONFIG_MTD_PHYSMAP_BANKWIDTH=0 | ||
| 457 | # CONFIG_MTD_ARM_INTEGRATOR is not set | 475 | # CONFIG_MTD_ARM_INTEGRATOR is not set |
| 458 | # CONFIG_MTD_IMPA7 is not set | 476 | # CONFIG_MTD_IMPA7 is not set |
| 459 | # CONFIG_MTD_INTEL_VR_NOR is not set | 477 | # CONFIG_MTD_INTEL_VR_NOR is not set |
| @@ -481,6 +499,7 @@ CONFIG_MTD_NAND=y | |||
| 481 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | 499 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set |
| 482 | # CONFIG_MTD_NAND_ECC_SMC is not set | 500 | # CONFIG_MTD_NAND_ECC_SMC is not set |
| 483 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | 501 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set |
| 502 | # CONFIG_MTD_NAND_GPIO is not set | ||
| 484 | CONFIG_MTD_NAND_IDS=y | 503 | CONFIG_MTD_NAND_IDS=y |
| 485 | # CONFIG_MTD_NAND_DISKONCHIP is not set | 504 | # CONFIG_MTD_NAND_DISKONCHIP is not set |
| 486 | # CONFIG_MTD_NAND_CAFE is not set | 505 | # CONFIG_MTD_NAND_CAFE is not set |
| @@ -491,6 +510,12 @@ CONFIG_MTD_NAND_ORION=y | |||
| 491 | # CONFIG_MTD_ONENAND is not set | 510 | # CONFIG_MTD_ONENAND is not set |
| 492 | 511 | ||
| 493 | # | 512 | # |
| 513 | # LPDDR flash memory drivers | ||
| 514 | # | ||
| 515 | # CONFIG_MTD_LPDDR is not set | ||
| 516 | # CONFIG_MTD_QINFO_PROBE is not set | ||
| 517 | |||
| 518 | # | ||
| 494 | # UBI - Unsorted block images | 519 | # UBI - Unsorted block images |
| 495 | # | 520 | # |
| 496 | # CONFIG_MTD_UBI is not set | 521 | # CONFIG_MTD_UBI is not set |
| @@ -568,6 +593,8 @@ CONFIG_SCSI_LOWLEVEL=y | |||
| 568 | # CONFIG_MEGARAID_LEGACY is not set | 593 | # CONFIG_MEGARAID_LEGACY is not set |
| 569 | # CONFIG_MEGARAID_SAS is not set | 594 | # CONFIG_MEGARAID_SAS is not set |
| 570 | # CONFIG_SCSI_HPTIOP is not set | 595 | # CONFIG_SCSI_HPTIOP is not set |
| 596 | # CONFIG_LIBFC is not set | ||
| 597 | # CONFIG_FCOE is not set | ||
| 571 | # CONFIG_SCSI_DMX3191D is not set | 598 | # CONFIG_SCSI_DMX3191D is not set |
| 572 | # CONFIG_SCSI_FUTURE_DOMAIN is not set | 599 | # CONFIG_SCSI_FUTURE_DOMAIN is not set |
| 573 | # CONFIG_SCSI_IPS is not set | 600 | # CONFIG_SCSI_IPS is not set |
| @@ -682,6 +709,9 @@ CONFIG_MARVELL_PHY=y | |||
| 682 | # CONFIG_BROADCOM_PHY is not set | 709 | # CONFIG_BROADCOM_PHY is not set |
| 683 | # CONFIG_ICPLUS_PHY is not set | 710 | # CONFIG_ICPLUS_PHY is not set |
| 684 | # CONFIG_REALTEK_PHY is not set | 711 | # CONFIG_REALTEK_PHY is not set |
| 712 | # CONFIG_NATIONAL_PHY is not set | ||
| 713 | # CONFIG_STE10XP is not set | ||
| 714 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 685 | # CONFIG_FIXED_PHY is not set | 715 | # CONFIG_FIXED_PHY is not set |
| 686 | # CONFIG_MDIO_BITBANG is not set | 716 | # CONFIG_MDIO_BITBANG is not set |
| 687 | CONFIG_NET_ETHERNET=y | 717 | CONFIG_NET_ETHERNET=y |
| @@ -695,6 +725,7 @@ CONFIG_MII=y | |||
| 695 | # CONFIG_DM9000 is not set | 725 | # CONFIG_DM9000 is not set |
| 696 | # CONFIG_ENC28J60 is not set | 726 | # CONFIG_ENC28J60 is not set |
| 697 | # CONFIG_SMC911X is not set | 727 | # CONFIG_SMC911X is not set |
| 728 | # CONFIG_SMSC911X is not set | ||
| 698 | # CONFIG_NET_TULIP is not set | 729 | # CONFIG_NET_TULIP is not set |
| 699 | # CONFIG_HP100 is not set | 730 | # CONFIG_HP100 is not set |
| 700 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | 731 | # CONFIG_IBM_NEW_EMAC_ZMII is not set |
| @@ -710,7 +741,6 @@ CONFIG_NET_PCI=y | |||
| 710 | # CONFIG_ADAPTEC_STARFIRE is not set | 741 | # CONFIG_ADAPTEC_STARFIRE is not set |
| 711 | # CONFIG_B44 is not set | 742 | # CONFIG_B44 is not set |
| 712 | # CONFIG_FORCEDETH is not set | 743 | # CONFIG_FORCEDETH is not set |
| 713 | # CONFIG_EEPRO100 is not set | ||
| 714 | # CONFIG_E100 is not set | 744 | # CONFIG_E100 is not set |
| 715 | # CONFIG_FEALNX is not set | 745 | # CONFIG_FEALNX is not set |
| 716 | # CONFIG_NATSEMI is not set | 746 | # CONFIG_NATSEMI is not set |
| @@ -720,6 +750,7 @@ CONFIG_NET_PCI=y | |||
| 720 | # CONFIG_R6040 is not set | 750 | # CONFIG_R6040 is not set |
| 721 | # CONFIG_SIS900 is not set | 751 | # CONFIG_SIS900 is not set |
| 722 | # CONFIG_EPIC100 is not set | 752 | # CONFIG_EPIC100 is not set |
| 753 | # CONFIG_SMSC9420 is not set | ||
| 723 | # CONFIG_SUNDANCE is not set | 754 | # CONFIG_SUNDANCE is not set |
| 724 | # CONFIG_TLAN is not set | 755 | # CONFIG_TLAN is not set |
| 725 | # CONFIG_VIA_RHINE is not set | 756 | # CONFIG_VIA_RHINE is not set |
| @@ -754,8 +785,39 @@ CONFIG_MV643XX_ETH=y | |||
| 754 | # Wireless LAN | 785 | # Wireless LAN |
| 755 | # | 786 | # |
| 756 | # CONFIG_WLAN_PRE80211 is not set | 787 | # CONFIG_WLAN_PRE80211 is not set |
| 757 | # CONFIG_WLAN_80211 is not set | 788 | CONFIG_WLAN_80211=y |
| 789 | CONFIG_LIBERTAS=y | ||
| 790 | # CONFIG_LIBERTAS_USB is not set | ||
| 791 | CONFIG_LIBERTAS_SDIO=y | ||
| 792 | # CONFIG_LIBERTAS_DEBUG is not set | ||
| 793 | # CONFIG_LIBERTAS_THINFIRM is not set | ||
| 794 | # CONFIG_HERMES is not set | ||
| 795 | # CONFIG_ATMEL is not set | ||
| 796 | # CONFIG_PRISM54 is not set | ||
| 797 | # CONFIG_USB_ZD1201 is not set | ||
| 798 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
| 799 | # CONFIG_RTL8180 is not set | ||
| 800 | # CONFIG_RTL8187 is not set | ||
| 801 | # CONFIG_ADM8211 is not set | ||
| 802 | # CONFIG_MAC80211_HWSIM is not set | ||
| 803 | # CONFIG_P54_COMMON is not set | ||
| 804 | # CONFIG_ATH5K is not set | ||
| 805 | # CONFIG_ATH9K is not set | ||
| 806 | # CONFIG_IPW2100 is not set | ||
| 807 | # CONFIG_IPW2200 is not set | ||
| 808 | # CONFIG_IWLCORE is not set | ||
| 758 | # CONFIG_IWLWIFI_LEDS is not set | 809 | # CONFIG_IWLWIFI_LEDS is not set |
| 810 | # CONFIG_IWLAGN is not set | ||
| 811 | # CONFIG_IWL3945 is not set | ||
| 812 | # CONFIG_HOSTAP is not set | ||
| 813 | # CONFIG_B43 is not set | ||
| 814 | # CONFIG_B43LEGACY is not set | ||
| 815 | # CONFIG_ZD1211RW is not set | ||
| 816 | # CONFIG_RT2X00 is not set | ||
| 817 | |||
| 818 | # | ||
| 819 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 820 | # | ||
| 759 | 821 | ||
| 760 | # | 822 | # |
| 761 | # USB Network Adapters | 823 | # USB Network Adapters |
| @@ -791,13 +853,20 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y | |||
| 791 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | 853 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 |
| 792 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | 854 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 |
| 793 | # CONFIG_INPUT_JOYDEV is not set | 855 | # CONFIG_INPUT_JOYDEV is not set |
| 794 | # CONFIG_INPUT_EVDEV is not set | 856 | CONFIG_INPUT_EVDEV=y |
| 795 | # CONFIG_INPUT_EVBUG is not set | 857 | # CONFIG_INPUT_EVBUG is not set |
| 796 | 858 | ||
| 797 | # | 859 | # |
| 798 | # Input Device Drivers | 860 | # Input Device Drivers |
| 799 | # | 861 | # |
| 800 | # CONFIG_INPUT_KEYBOARD is not set | 862 | CONFIG_INPUT_KEYBOARD=y |
| 863 | CONFIG_KEYBOARD_ATKBD=y | ||
| 864 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 865 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 866 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 867 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 868 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 869 | CONFIG_KEYBOARD_GPIO=y | ||
| 801 | # CONFIG_INPUT_MOUSE is not set | 870 | # CONFIG_INPUT_MOUSE is not set |
| 802 | # CONFIG_INPUT_JOYSTICK is not set | 871 | # CONFIG_INPUT_JOYSTICK is not set |
| 803 | # CONFIG_INPUT_TABLET is not set | 872 | # CONFIG_INPUT_TABLET is not set |
| @@ -807,7 +876,11 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | |||
| 807 | # | 876 | # |
| 808 | # Hardware I/O ports | 877 | # Hardware I/O ports |
| 809 | # | 878 | # |
| 810 | # CONFIG_SERIO is not set | 879 | CONFIG_SERIO=y |
| 880 | CONFIG_SERIO_SERPORT=y | ||
| 881 | # CONFIG_SERIO_PCIPS2 is not set | ||
| 882 | CONFIG_SERIO_LIBPS2=y | ||
| 883 | # CONFIG_SERIO_RAW is not set | ||
| 811 | # CONFIG_GAMEPORT is not set | 884 | # CONFIG_GAMEPORT is not set |
| 812 | 885 | ||
| 813 | # | 886 | # |
| @@ -839,11 +912,11 @@ CONFIG_SERIAL_CORE=y | |||
| 839 | CONFIG_SERIAL_CORE_CONSOLE=y | 912 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 840 | # CONFIG_SERIAL_JSM is not set | 913 | # CONFIG_SERIAL_JSM is not set |
| 841 | CONFIG_UNIX98_PTYS=y | 914 | CONFIG_UNIX98_PTYS=y |
| 915 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 842 | CONFIG_LEGACY_PTYS=y | 916 | CONFIG_LEGACY_PTYS=y |
| 843 | CONFIG_LEGACY_PTY_COUNT=16 | 917 | CONFIG_LEGACY_PTY_COUNT=16 |
| 844 | # CONFIG_IPMI_HANDLER is not set | 918 | # CONFIG_IPMI_HANDLER is not set |
| 845 | # CONFIG_HW_RANDOM is not set | 919 | # CONFIG_HW_RANDOM is not set |
| 846 | # CONFIG_NVRAM is not set | ||
| 847 | # CONFIG_R3964 is not set | 920 | # CONFIG_R3964 is not set |
| 848 | # CONFIG_APPLICOM is not set | 921 | # CONFIG_APPLICOM is not set |
| 849 | # CONFIG_RAW_DRIVER is not set | 922 | # CONFIG_RAW_DRIVER is not set |
| @@ -879,6 +952,7 @@ CONFIG_I2C_HELPER_AUTO=y | |||
| 879 | # | 952 | # |
| 880 | # I2C system bus drivers (mostly embedded / system-on-chip) | 953 | # I2C system bus drivers (mostly embedded / system-on-chip) |
| 881 | # | 954 | # |
| 955 | # CONFIG_I2C_GPIO is not set | ||
| 882 | CONFIG_I2C_MV64XXX=y | 956 | CONFIG_I2C_MV64XXX=y |
| 883 | # CONFIG_I2C_OCORES is not set | 957 | # CONFIG_I2C_OCORES is not set |
| 884 | # CONFIG_I2C_SIMTEC is not set | 958 | # CONFIG_I2C_SIMTEC is not set |
| @@ -905,8 +979,6 @@ CONFIG_I2C_MV64XXX=y | |||
| 905 | # Miscellaneous I2C Chip support | 979 | # Miscellaneous I2C Chip support |
| 906 | # | 980 | # |
| 907 | # CONFIG_DS1682 is not set | 981 | # CONFIG_DS1682 is not set |
| 908 | # CONFIG_EEPROM_AT24 is not set | ||
| 909 | # CONFIG_EEPROM_LEGACY is not set | ||
| 910 | # CONFIG_SENSORS_PCF8574 is not set | 982 | # CONFIG_SENSORS_PCF8574 is not set |
| 911 | # CONFIG_PCF8575 is not set | 983 | # CONFIG_PCF8575 is not set |
| 912 | # CONFIG_SENSORS_PCA9539 is not set | 984 | # CONFIG_SENSORS_PCA9539 is not set |
| @@ -925,12 +997,12 @@ CONFIG_SPI_MASTER=y | |||
| 925 | # SPI Master Controller Drivers | 997 | # SPI Master Controller Drivers |
| 926 | # | 998 | # |
| 927 | # CONFIG_SPI_BITBANG is not set | 999 | # CONFIG_SPI_BITBANG is not set |
| 1000 | # CONFIG_SPI_GPIO is not set | ||
| 928 | CONFIG_SPI_ORION=y | 1001 | CONFIG_SPI_ORION=y |
| 929 | 1002 | ||
| 930 | # | 1003 | # |
| 931 | # SPI Protocol Masters | 1004 | # SPI Protocol Masters |
| 932 | # | 1005 | # |
| 933 | # CONFIG_EEPROM_AT25 is not set | ||
| 934 | # CONFIG_SPI_SPIDEV is not set | 1006 | # CONFIG_SPI_SPIDEV is not set |
| 935 | # CONFIG_SPI_TLE62X0 is not set | 1007 | # CONFIG_SPI_TLE62X0 is not set |
| 936 | # CONFIG_W1 is not set | 1008 | # CONFIG_W1 is not set |
| @@ -952,10 +1024,12 @@ CONFIG_SSB_POSSIBLE=y | |||
| 952 | # CONFIG_MFD_CORE is not set | 1024 | # CONFIG_MFD_CORE is not set |
| 953 | # CONFIG_MFD_SM501 is not set | 1025 | # CONFIG_MFD_SM501 is not set |
| 954 | # CONFIG_HTC_PASIC3 is not set | 1026 | # CONFIG_HTC_PASIC3 is not set |
| 1027 | # CONFIG_TWL4030_CORE is not set | ||
| 955 | # CONFIG_MFD_TMIO is not set | 1028 | # CONFIG_MFD_TMIO is not set |
| 956 | # CONFIG_PMIC_DA903X is not set | 1029 | # CONFIG_PMIC_DA903X is not set |
| 957 | # CONFIG_MFD_WM8400 is not set | 1030 | # CONFIG_MFD_WM8400 is not set |
| 958 | # CONFIG_MFD_WM8350_I2C is not set | 1031 | # CONFIG_MFD_WM8350_I2C is not set |
| 1032 | # CONFIG_MFD_PCF50633 is not set | ||
| 959 | 1033 | ||
| 960 | # | 1034 | # |
| 961 | # Multimedia devices | 1035 | # Multimedia devices |
| @@ -1012,11 +1086,9 @@ CONFIG_HID_COMPAT=y | |||
| 1012 | CONFIG_HID_A4TECH=y | 1086 | CONFIG_HID_A4TECH=y |
| 1013 | CONFIG_HID_APPLE=y | 1087 | CONFIG_HID_APPLE=y |
| 1014 | CONFIG_HID_BELKIN=y | 1088 | CONFIG_HID_BELKIN=y |
| 1015 | CONFIG_HID_BRIGHT=y | ||
| 1016 | CONFIG_HID_CHERRY=y | 1089 | CONFIG_HID_CHERRY=y |
| 1017 | CONFIG_HID_CHICONY=y | 1090 | CONFIG_HID_CHICONY=y |
| 1018 | CONFIG_HID_CYPRESS=y | 1091 | CONFIG_HID_CYPRESS=y |
| 1019 | CONFIG_HID_DELL=y | ||
| 1020 | CONFIG_HID_EZKEY=y | 1092 | CONFIG_HID_EZKEY=y |
| 1021 | CONFIG_HID_GYRATION=y | 1093 | CONFIG_HID_GYRATION=y |
| 1022 | CONFIG_HID_LOGITECH=y | 1094 | CONFIG_HID_LOGITECH=y |
| @@ -1024,12 +1096,15 @@ CONFIG_HID_LOGITECH=y | |||
| 1024 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | 1096 | # CONFIG_LOGIRUMBLEPAD2_FF is not set |
| 1025 | CONFIG_HID_MICROSOFT=y | 1097 | CONFIG_HID_MICROSOFT=y |
| 1026 | CONFIG_HID_MONTEREY=y | 1098 | CONFIG_HID_MONTEREY=y |
| 1099 | CONFIG_HID_NTRIG=y | ||
| 1027 | CONFIG_HID_PANTHERLORD=y | 1100 | CONFIG_HID_PANTHERLORD=y |
| 1028 | # CONFIG_PANTHERLORD_FF is not set | 1101 | # CONFIG_PANTHERLORD_FF is not set |
| 1029 | CONFIG_HID_PETALYNX=y | 1102 | CONFIG_HID_PETALYNX=y |
| 1030 | CONFIG_HID_SAMSUNG=y | 1103 | CONFIG_HID_SAMSUNG=y |
| 1031 | CONFIG_HID_SONY=y | 1104 | CONFIG_HID_SONY=y |
| 1032 | CONFIG_HID_SUNPLUS=y | 1105 | CONFIG_HID_SUNPLUS=y |
| 1106 | # CONFIG_GREENASIA_FF is not set | ||
| 1107 | CONFIG_HID_TOPSEED=y | ||
| 1033 | # CONFIG_THRUSTMASTER_FF is not set | 1108 | # CONFIG_THRUSTMASTER_FF is not set |
| 1034 | # CONFIG_ZEROPLUS_FF is not set | 1109 | # CONFIG_ZEROPLUS_FF is not set |
| 1035 | CONFIG_USB_SUPPORT=y | 1110 | CONFIG_USB_SUPPORT=y |
| @@ -1058,6 +1133,7 @@ CONFIG_USB_DEVICE_CLASS=y | |||
| 1058 | CONFIG_USB_EHCI_HCD=y | 1133 | CONFIG_USB_EHCI_HCD=y |
| 1059 | CONFIG_USB_EHCI_ROOT_HUB_TT=y | 1134 | CONFIG_USB_EHCI_ROOT_HUB_TT=y |
| 1060 | CONFIG_USB_EHCI_TT_NEWSCHED=y | 1135 | CONFIG_USB_EHCI_TT_NEWSCHED=y |
| 1136 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1061 | # CONFIG_USB_ISP116X_HCD is not set | 1137 | # CONFIG_USB_ISP116X_HCD is not set |
| 1062 | # CONFIG_USB_ISP1760_HCD is not set | 1138 | # CONFIG_USB_ISP1760_HCD is not set |
| 1063 | # CONFIG_USB_OHCI_HCD is not set | 1139 | # CONFIG_USB_OHCI_HCD is not set |
| @@ -1087,7 +1163,6 @@ CONFIG_USB_STORAGE=y | |||
| 1087 | CONFIG_USB_STORAGE_DATAFAB=y | 1163 | CONFIG_USB_STORAGE_DATAFAB=y |
| 1088 | CONFIG_USB_STORAGE_FREECOM=y | 1164 | CONFIG_USB_STORAGE_FREECOM=y |
| 1089 | # CONFIG_USB_STORAGE_ISD200 is not set | 1165 | # CONFIG_USB_STORAGE_ISD200 is not set |
| 1090 | CONFIG_USB_STORAGE_DPCM=y | ||
| 1091 | # CONFIG_USB_STORAGE_USBAT is not set | 1166 | # CONFIG_USB_STORAGE_USBAT is not set |
| 1092 | CONFIG_USB_STORAGE_SDDR09=y | 1167 | CONFIG_USB_STORAGE_SDDR09=y |
| 1093 | CONFIG_USB_STORAGE_SDDR55=y | 1168 | CONFIG_USB_STORAGE_SDDR55=y |
| @@ -1135,21 +1210,51 @@ CONFIG_USB_STORAGE_JUMPSHOT=y | |||
| 1135 | # CONFIG_USB_ISIGHTFW is not set | 1210 | # CONFIG_USB_ISIGHTFW is not set |
| 1136 | # CONFIG_USB_VST is not set | 1211 | # CONFIG_USB_VST is not set |
| 1137 | # CONFIG_USB_GADGET is not set | 1212 | # CONFIG_USB_GADGET is not set |
| 1213 | |||
| 1214 | # | ||
| 1215 | # OTG and related infrastructure | ||
| 1216 | # | ||
| 1217 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1138 | # CONFIG_UWB is not set | 1218 | # CONFIG_UWB is not set |
| 1139 | # CONFIG_MMC is not set | 1219 | CONFIG_MMC=y |
| 1220 | # CONFIG_MMC_DEBUG is not set | ||
| 1221 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 1222 | |||
| 1223 | # | ||
| 1224 | # MMC/SD/SDIO Card Drivers | ||
| 1225 | # | ||
| 1226 | CONFIG_MMC_BLOCK=y | ||
| 1227 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 1228 | CONFIG_SDIO_UART=y | ||
| 1229 | # CONFIG_MMC_TEST is not set | ||
| 1230 | |||
| 1231 | # | ||
| 1232 | # MMC/SD/SDIO Host Controller Drivers | ||
| 1233 | # | ||
| 1234 | # CONFIG_MMC_SDHCI is not set | ||
| 1235 | # CONFIG_MMC_TIFM_SD is not set | ||
| 1236 | CONFIG_MMC_MVSDIO=y | ||
| 1237 | # CONFIG_MMC_SPI is not set | ||
| 1140 | # CONFIG_MEMSTICK is not set | 1238 | # CONFIG_MEMSTICK is not set |
| 1141 | # CONFIG_ACCESSIBILITY is not set | 1239 | # CONFIG_ACCESSIBILITY is not set |
| 1142 | CONFIG_NEW_LEDS=y | 1240 | CONFIG_NEW_LEDS=y |
| 1143 | # CONFIG_LEDS_CLASS is not set | 1241 | CONFIG_LEDS_CLASS=y |
| 1144 | 1242 | ||
| 1145 | # | 1243 | # |
| 1146 | # LED drivers | 1244 | # LED drivers |
| 1147 | # | 1245 | # |
| 1246 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1247 | CONFIG_LEDS_GPIO=y | ||
| 1248 | # CONFIG_LEDS_PCA955X is not set | ||
| 1148 | 1249 | ||
| 1149 | # | 1250 | # |
| 1150 | # LED Triggers | 1251 | # LED Triggers |
| 1151 | # | 1252 | # |
| 1152 | # CONFIG_LEDS_TRIGGERS is not set | 1253 | CONFIG_LEDS_TRIGGERS=y |
| 1254 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 1255 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 1256 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 1257 | CONFIG_LEDS_TRIGGER_DEFAULT_ON=y | ||
| 1153 | CONFIG_RTC_LIB=y | 1258 | CONFIG_RTC_LIB=y |
| 1154 | CONFIG_RTC_CLASS=y | 1259 | CONFIG_RTC_CLASS=y |
| 1155 | CONFIG_RTC_HCTOSYS=y | 1260 | CONFIG_RTC_HCTOSYS=y |
| @@ -1178,7 +1283,7 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1178 | # CONFIG_RTC_DRV_PCF8563 is not set | 1283 | # CONFIG_RTC_DRV_PCF8563 is not set |
| 1179 | # CONFIG_RTC_DRV_PCF8583 is not set | 1284 | # CONFIG_RTC_DRV_PCF8583 is not set |
| 1180 | # CONFIG_RTC_DRV_M41T80 is not set | 1285 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1181 | # CONFIG_RTC_DRV_S35390A is not set | 1286 | CONFIG_RTC_DRV_S35390A=y |
| 1182 | # CONFIG_RTC_DRV_FM3130 is not set | 1287 | # CONFIG_RTC_DRV_FM3130 is not set |
| 1183 | # CONFIG_RTC_DRV_RX8581 is not set | 1288 | # CONFIG_RTC_DRV_RX8581 is not set |
| 1184 | 1289 | ||
| @@ -1227,6 +1332,7 @@ CONFIG_DMA_ENGINE=y | |||
| 1227 | # CONFIG_DMATEST is not set | 1332 | # CONFIG_DMATEST is not set |
| 1228 | # CONFIG_REGULATOR is not set | 1333 | # CONFIG_REGULATOR is not set |
| 1229 | # CONFIG_UIO is not set | 1334 | # CONFIG_UIO is not set |
| 1335 | # CONFIG_STAGING is not set | ||
| 1230 | 1336 | ||
| 1231 | # | 1337 | # |
| 1232 | # File systems | 1338 | # File systems |
| @@ -1238,16 +1344,14 @@ CONFIG_EXT3_FS=y | |||
| 1238 | # CONFIG_EXT3_FS_XATTR is not set | 1344 | # CONFIG_EXT3_FS_XATTR is not set |
| 1239 | # CONFIG_EXT4_FS is not set | 1345 | # CONFIG_EXT4_FS is not set |
| 1240 | CONFIG_JBD=y | 1346 | CONFIG_JBD=y |
| 1347 | # CONFIG_JBD_DEBUG is not set | ||
| 1241 | # CONFIG_REISERFS_FS is not set | 1348 | # CONFIG_REISERFS_FS is not set |
| 1242 | # CONFIG_JFS_FS is not set | 1349 | # CONFIG_JFS_FS is not set |
| 1243 | # CONFIG_FS_POSIX_ACL is not set | 1350 | # CONFIG_FS_POSIX_ACL is not set |
| 1244 | CONFIG_FILE_LOCKING=y | 1351 | CONFIG_FILE_LOCKING=y |
| 1245 | CONFIG_XFS_FS=y | 1352 | # CONFIG_XFS_FS is not set |
| 1246 | # CONFIG_XFS_QUOTA is not set | ||
| 1247 | # CONFIG_XFS_POSIX_ACL is not set | ||
| 1248 | # CONFIG_XFS_RT is not set | ||
| 1249 | # CONFIG_XFS_DEBUG is not set | ||
| 1250 | # CONFIG_OCFS2_FS is not set | 1353 | # CONFIG_OCFS2_FS is not set |
| 1354 | # CONFIG_BTRFS_FS is not set | ||
| 1251 | CONFIG_DNOTIFY=y | 1355 | CONFIG_DNOTIFY=y |
| 1252 | CONFIG_INOTIFY=y | 1356 | CONFIG_INOTIFY=y |
| 1253 | CONFIG_INOTIFY_USER=y | 1357 | CONFIG_INOTIFY_USER=y |
| @@ -1268,9 +1372,9 @@ CONFIG_UDF_NLS=y | |||
| 1268 | # | 1372 | # |
| 1269 | # DOS/FAT/NT Filesystems | 1373 | # DOS/FAT/NT Filesystems |
| 1270 | # | 1374 | # |
| 1271 | CONFIG_FAT_FS=m | 1375 | CONFIG_FAT_FS=y |
| 1272 | CONFIG_MSDOS_FS=m | 1376 | CONFIG_MSDOS_FS=y |
| 1273 | CONFIG_VFAT_FS=m | 1377 | CONFIG_VFAT_FS=y |
| 1274 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | 1378 | CONFIG_FAT_DEFAULT_CODEPAGE=437 |
| 1275 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | 1379 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" |
| 1276 | # CONFIG_NTFS_FS is not set | 1380 | # CONFIG_NTFS_FS is not set |
| @@ -1286,10 +1390,7 @@ CONFIG_TMPFS=y | |||
| 1286 | # CONFIG_TMPFS_POSIX_ACL is not set | 1390 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 1287 | # CONFIG_HUGETLB_PAGE is not set | 1391 | # CONFIG_HUGETLB_PAGE is not set |
| 1288 | # CONFIG_CONFIGFS_FS is not set | 1392 | # CONFIG_CONFIGFS_FS is not set |
| 1289 | 1393 | CONFIG_MISC_FILESYSTEMS=y | |
| 1290 | # | ||
| 1291 | # Miscellaneous filesystems | ||
| 1292 | # | ||
| 1293 | # CONFIG_ADFS_FS is not set | 1394 | # CONFIG_ADFS_FS is not set |
| 1294 | # CONFIG_AFFS_FS is not set | 1395 | # CONFIG_AFFS_FS is not set |
| 1295 | # CONFIG_HFS_FS is not set | 1396 | # CONFIG_HFS_FS is not set |
| @@ -1309,6 +1410,7 @@ CONFIG_JFFS2_ZLIB=y | |||
| 1309 | CONFIG_JFFS2_RTIME=y | 1410 | CONFIG_JFFS2_RTIME=y |
| 1310 | # CONFIG_JFFS2_RUBIN is not set | 1411 | # CONFIG_JFFS2_RUBIN is not set |
| 1311 | CONFIG_CRAMFS=y | 1412 | CONFIG_CRAMFS=y |
| 1413 | # CONFIG_SQUASHFS is not set | ||
| 1312 | # CONFIG_VXFS_FS is not set | 1414 | # CONFIG_VXFS_FS is not set |
| 1313 | # CONFIG_MINIX_FS is not set | 1415 | # CONFIG_MINIX_FS is not set |
| 1314 | # CONFIG_OMFS_FS is not set | 1416 | # CONFIG_OMFS_FS is not set |
| @@ -1393,7 +1495,7 @@ CONFIG_ENABLE_MUST_CHECK=y | |||
| 1393 | CONFIG_FRAME_WARN=1024 | 1495 | CONFIG_FRAME_WARN=1024 |
| 1394 | CONFIG_MAGIC_SYSRQ=y | 1496 | CONFIG_MAGIC_SYSRQ=y |
| 1395 | # CONFIG_UNUSED_SYMBOLS is not set | 1497 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1396 | # CONFIG_DEBUG_FS is not set | 1498 | CONFIG_DEBUG_FS=y |
| 1397 | # CONFIG_HEADERS_CHECK is not set | 1499 | # CONFIG_HEADERS_CHECK is not set |
| 1398 | CONFIG_DEBUG_KERNEL=y | 1500 | CONFIG_DEBUG_KERNEL=y |
| 1399 | # CONFIG_DEBUG_SHIRQ is not set | 1501 | # CONFIG_DEBUG_SHIRQ is not set |
| @@ -1416,6 +1518,7 @@ CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | |||
| 1416 | # CONFIG_LOCK_STAT is not set | 1518 | # CONFIG_LOCK_STAT is not set |
| 1417 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1519 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1418 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | 1520 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set |
| 1521 | CONFIG_STACKTRACE=y | ||
| 1419 | # CONFIG_DEBUG_KOBJECT is not set | 1522 | # CONFIG_DEBUG_KOBJECT is not set |
| 1420 | CONFIG_DEBUG_BUGVERBOSE=y | 1523 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1421 | CONFIG_DEBUG_INFO=y | 1524 | CONFIG_DEBUG_INFO=y |
| @@ -1424,7 +1527,7 @@ CONFIG_DEBUG_INFO=y | |||
| 1424 | CONFIG_DEBUG_MEMORY_INIT=y | 1527 | CONFIG_DEBUG_MEMORY_INIT=y |
| 1425 | # CONFIG_DEBUG_LIST is not set | 1528 | # CONFIG_DEBUG_LIST is not set |
| 1426 | # CONFIG_DEBUG_SG is not set | 1529 | # CONFIG_DEBUG_SG is not set |
| 1427 | CONFIG_FRAME_POINTER=y | 1530 | # CONFIG_DEBUG_NOTIFIERS is not set |
| 1428 | # CONFIG_BOOT_PRINTK_DELAY is not set | 1531 | # CONFIG_BOOT_PRINTK_DELAY is not set |
| 1429 | # CONFIG_RCU_TORTURE_TEST is not set | 1532 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1430 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | 1533 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set |
| @@ -1435,7 +1538,10 @@ CONFIG_FRAME_POINTER=y | |||
| 1435 | # CONFIG_FAULT_INJECTION is not set | 1538 | # CONFIG_FAULT_INJECTION is not set |
| 1436 | # CONFIG_LATENCYTOP is not set | 1539 | # CONFIG_LATENCYTOP is not set |
| 1437 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 1540 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 1541 | CONFIG_NOP_TRACER=y | ||
| 1438 | CONFIG_HAVE_FUNCTION_TRACER=y | 1542 | CONFIG_HAVE_FUNCTION_TRACER=y |
| 1543 | CONFIG_RING_BUFFER=y | ||
| 1544 | CONFIG_TRACING=y | ||
| 1439 | 1545 | ||
| 1440 | # | 1546 | # |
| 1441 | # Tracers | 1547 | # Tracers |
| @@ -1446,11 +1552,14 @@ CONFIG_HAVE_FUNCTION_TRACER=y | |||
| 1446 | # CONFIG_SCHED_TRACER is not set | 1552 | # CONFIG_SCHED_TRACER is not set |
| 1447 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | 1553 | # CONFIG_CONTEXT_SWITCH_TRACER is not set |
| 1448 | # CONFIG_BOOT_TRACER is not set | 1554 | # CONFIG_BOOT_TRACER is not set |
| 1555 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1449 | # CONFIG_STACK_TRACER is not set | 1556 | # CONFIG_STACK_TRACER is not set |
| 1557 | # CONFIG_FTRACE_STARTUP_TEST is not set | ||
| 1450 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | 1558 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set |
| 1451 | # CONFIG_SAMPLES is not set | 1559 | # CONFIG_SAMPLES is not set |
| 1452 | CONFIG_HAVE_ARCH_KGDB=y | 1560 | CONFIG_HAVE_ARCH_KGDB=y |
| 1453 | # CONFIG_KGDB is not set | 1561 | # CONFIG_KGDB is not set |
| 1562 | CONFIG_ARM_UNWIND=y | ||
| 1454 | CONFIG_DEBUG_USER=y | 1563 | CONFIG_DEBUG_USER=y |
| 1455 | CONFIG_DEBUG_ERRORS=y | 1564 | CONFIG_DEBUG_ERRORS=y |
| 1456 | # CONFIG_DEBUG_STACK_USAGE is not set | 1565 | # CONFIG_DEBUG_STACK_USAGE is not set |
| @@ -1464,19 +1573,22 @@ CONFIG_DEBUG_LL=y | |||
| 1464 | # CONFIG_SECURITY is not set | 1573 | # CONFIG_SECURITY is not set |
| 1465 | # CONFIG_SECURITYFS is not set | 1574 | # CONFIG_SECURITYFS is not set |
| 1466 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | 1575 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1467 | CONFIG_ASYNC_CORE=y | ||
| 1468 | CONFIG_CRYPTO=y | 1576 | CONFIG_CRYPTO=y |
| 1469 | 1577 | ||
| 1470 | # | 1578 | # |
| 1471 | # Crypto core or helper | 1579 | # Crypto core or helper |
| 1472 | # | 1580 | # |
| 1473 | # CONFIG_CRYPTO_FIPS is not set | 1581 | # CONFIG_CRYPTO_FIPS is not set |
| 1474 | CONFIG_CRYPTO_ALGAPI=m | 1582 | CONFIG_CRYPTO_ALGAPI=y |
| 1475 | CONFIG_CRYPTO_AEAD=m | 1583 | CONFIG_CRYPTO_ALGAPI2=y |
| 1476 | CONFIG_CRYPTO_BLKCIPHER=m | 1584 | CONFIG_CRYPTO_AEAD2=y |
| 1477 | CONFIG_CRYPTO_HASH=m | 1585 | CONFIG_CRYPTO_BLKCIPHER=y |
| 1478 | CONFIG_CRYPTO_RNG=m | 1586 | CONFIG_CRYPTO_BLKCIPHER2=y |
| 1479 | CONFIG_CRYPTO_MANAGER=m | 1587 | CONFIG_CRYPTO_HASH=y |
| 1588 | CONFIG_CRYPTO_HASH2=y | ||
| 1589 | CONFIG_CRYPTO_RNG2=y | ||
| 1590 | CONFIG_CRYPTO_MANAGER=y | ||
| 1591 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1480 | # CONFIG_CRYPTO_GF128MUL is not set | 1592 | # CONFIG_CRYPTO_GF128MUL is not set |
| 1481 | # CONFIG_CRYPTO_NULL is not set | 1593 | # CONFIG_CRYPTO_NULL is not set |
| 1482 | # CONFIG_CRYPTO_CRYPTD is not set | 1594 | # CONFIG_CRYPTO_CRYPTD is not set |
| @@ -1496,7 +1608,7 @@ CONFIG_CRYPTO_MANAGER=m | |||
| 1496 | CONFIG_CRYPTO_CBC=m | 1608 | CONFIG_CRYPTO_CBC=m |
| 1497 | # CONFIG_CRYPTO_CTR is not set | 1609 | # CONFIG_CRYPTO_CTR is not set |
| 1498 | # CONFIG_CRYPTO_CTS is not set | 1610 | # CONFIG_CRYPTO_CTS is not set |
| 1499 | CONFIG_CRYPTO_ECB=m | 1611 | CONFIG_CRYPTO_ECB=y |
| 1500 | # CONFIG_CRYPTO_LRW is not set | 1612 | # CONFIG_CRYPTO_LRW is not set |
| 1501 | CONFIG_CRYPTO_PCBC=m | 1613 | CONFIG_CRYPTO_PCBC=m |
| 1502 | # CONFIG_CRYPTO_XTS is not set | 1614 | # CONFIG_CRYPTO_XTS is not set |
| @@ -1510,7 +1622,7 @@ CONFIG_CRYPTO_PCBC=m | |||
| 1510 | # | 1622 | # |
| 1511 | # Digest | 1623 | # Digest |
| 1512 | # | 1624 | # |
| 1513 | # CONFIG_CRYPTO_CRC32C is not set | 1625 | CONFIG_CRYPTO_CRC32C=y |
| 1514 | # CONFIG_CRYPTO_MD4 is not set | 1626 | # CONFIG_CRYPTO_MD4 is not set |
| 1515 | # CONFIG_CRYPTO_MD5 is not set | 1627 | # CONFIG_CRYPTO_MD5 is not set |
| 1516 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | 1628 | # CONFIG_CRYPTO_MICHAEL_MIC is not set |
| @@ -1527,9 +1639,9 @@ CONFIG_CRYPTO_PCBC=m | |||
| 1527 | # | 1639 | # |
| 1528 | # Ciphers | 1640 | # Ciphers |
| 1529 | # | 1641 | # |
| 1530 | # CONFIG_CRYPTO_AES is not set | 1642 | CONFIG_CRYPTO_AES=y |
| 1531 | # CONFIG_CRYPTO_ANUBIS is not set | 1643 | # CONFIG_CRYPTO_ANUBIS is not set |
| 1532 | # CONFIG_CRYPTO_ARC4 is not set | 1644 | CONFIG_CRYPTO_ARC4=y |
| 1533 | # CONFIG_CRYPTO_BLOWFISH is not set | 1645 | # CONFIG_CRYPTO_BLOWFISH is not set |
| 1534 | # CONFIG_CRYPTO_CAMELLIA is not set | 1646 | # CONFIG_CRYPTO_CAMELLIA is not set |
| 1535 | # CONFIG_CRYPTO_CAST5 is not set | 1647 | # CONFIG_CRYPTO_CAST5 is not set |
| @@ -1560,6 +1672,7 @@ CONFIG_CRYPTO_HW=y | |||
| 1560 | # Library routines | 1672 | # Library routines |
| 1561 | # | 1673 | # |
| 1562 | CONFIG_BITREVERSE=y | 1674 | CONFIG_BITREVERSE=y |
| 1675 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1563 | CONFIG_CRC_CCITT=y | 1676 | CONFIG_CRC_CCITT=y |
| 1564 | CONFIG_CRC16=y | 1677 | CONFIG_CRC16=y |
| 1565 | # CONFIG_CRC_T10DIF is not set | 1678 | # CONFIG_CRC_T10DIF is not set |
diff --git a/arch/arm/configs/lart_defconfig b/arch/arm/configs/lart_defconfig index a1cc34f25602..56ae56899d2e 100644 --- a/arch/arm/configs/lart_defconfig +++ b/arch/arm/configs/lart_defconfig | |||
| @@ -87,7 +87,6 @@ CONFIG_ARCH_SA1100=y | |||
| 87 | # CONFIG_SA1100_COLLIE is not set | 87 | # CONFIG_SA1100_COLLIE is not set |
| 88 | # CONFIG_SA1100_H3100 is not set | 88 | # CONFIG_SA1100_H3100 is not set |
| 89 | # CONFIG_SA1100_H3600 is not set | 89 | # CONFIG_SA1100_H3600 is not set |
| 90 | # CONFIG_SA1100_H3800 is not set | ||
| 91 | # CONFIG_SA1100_BADGE4 is not set | 90 | # CONFIG_SA1100_BADGE4 is not set |
| 92 | # CONFIG_SA1100_JORNADA720 is not set | 91 | # CONFIG_SA1100_JORNADA720 is not set |
| 93 | # CONFIG_SA1100_HACKKIT is not set | 92 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig index 73ba62b71063..82428c2f234c 100644 --- a/arch/arm/configs/magician_defconfig +++ b/arch/arm/configs/magician_defconfig | |||
| @@ -1,9 +1,10 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.24-rc6 | 3 | # Linux kernel version: 2.6.29-rc3 |
| 4 | # Sun Dec 30 13:02:54 2007 | 4 | # Fri Jan 30 12:42:03 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_HAVE_PWM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | 8 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y |
| 8 | CONFIG_GENERIC_GPIO=y | 9 | CONFIG_GENERIC_GPIO=y |
| 9 | CONFIG_GENERIC_TIME=y | 10 | CONFIG_GENERIC_TIME=y |
| @@ -12,6 +13,7 @@ CONFIG_MMU=y | |||
| 12 | # CONFIG_NO_IOPORT is not set | 13 | # CONFIG_NO_IOPORT is not set |
| 13 | CONFIG_GENERIC_HARDIRQS=y | 14 | CONFIG_GENERIC_HARDIRQS=y |
| 14 | CONFIG_STACKTRACE_SUPPORT=y | 15 | CONFIG_STACKTRACE_SUPPORT=y |
| 16 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 15 | CONFIG_LOCKDEP_SUPPORT=y | 17 | CONFIG_LOCKDEP_SUPPORT=y |
| 16 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | 18 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y |
| 17 | CONFIG_HARDIRQS_SW_RESEND=y | 19 | CONFIG_HARDIRQS_SW_RESEND=y |
| @@ -21,8 +23,8 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y | |||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | 23 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set |
| 22 | CONFIG_GENERIC_HWEIGHT=y | 24 | CONFIG_GENERIC_HWEIGHT=y |
| 23 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 25 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 24 | CONFIG_ZONE_DMA=y | ||
| 25 | CONFIG_ARCH_MTD_XIP=y | 26 | CONFIG_ARCH_MTD_XIP=y |
| 27 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 26 | CONFIG_VECTORS_BASE=0xffff0000 | 28 | CONFIG_VECTORS_BASE=0xffff0000 |
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | 29 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" |
| 28 | 30 | ||
| @@ -41,16 +43,24 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 41 | # CONFIG_POSIX_MQUEUE is not set | 43 | # CONFIG_POSIX_MQUEUE is not set |
| 42 | # CONFIG_BSD_PROCESS_ACCT is not set | 44 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 43 | # CONFIG_TASKSTATS is not set | 45 | # CONFIG_TASKSTATS is not set |
| 44 | # CONFIG_USER_NS is not set | ||
| 45 | # CONFIG_PID_NS is not set | ||
| 46 | # CONFIG_AUDIT is not set | 46 | # CONFIG_AUDIT is not set |
| 47 | |||
| 48 | # | ||
| 49 | # RCU Subsystem | ||
| 50 | # | ||
| 51 | CONFIG_CLASSIC_RCU=y | ||
| 52 | # CONFIG_TREE_RCU is not set | ||
| 53 | # CONFIG_PREEMPT_RCU is not set | ||
| 54 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 55 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 47 | CONFIG_IKCONFIG=y | 56 | CONFIG_IKCONFIG=y |
| 48 | CONFIG_IKCONFIG_PROC=y | 57 | CONFIG_IKCONFIG_PROC=y |
| 49 | CONFIG_LOG_BUF_SHIFT=16 | 58 | CONFIG_LOG_BUF_SHIFT=16 |
| 59 | # CONFIG_GROUP_SCHED is not set | ||
| 50 | # CONFIG_CGROUPS is not set | 60 | # CONFIG_CGROUPS is not set |
| 51 | # CONFIG_FAIR_GROUP_SCHED is not set | 61 | # CONFIG_SYSFS_DEPRECATED_V2 is not set |
| 52 | # CONFIG_SYSFS_DEPRECATED is not set | ||
| 53 | # CONFIG_RELAY is not set | 62 | # CONFIG_RELAY is not set |
| 63 | # CONFIG_NAMESPACES is not set | ||
| 54 | CONFIG_BLK_DEV_INITRD=y | 64 | CONFIG_BLK_DEV_INITRD=y |
| 55 | CONFIG_INITRAMFS_SOURCE="" | 65 | CONFIG_INITRAMFS_SOURCE="" |
| 56 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 66 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| @@ -65,31 +75,41 @@ CONFIG_HOTPLUG=y | |||
| 65 | CONFIG_PRINTK=y | 75 | CONFIG_PRINTK=y |
| 66 | CONFIG_BUG=y | 76 | CONFIG_BUG=y |
| 67 | CONFIG_ELF_CORE=y | 77 | CONFIG_ELF_CORE=y |
| 78 | CONFIG_COMPAT_BRK=y | ||
| 68 | CONFIG_BASE_FULL=y | 79 | CONFIG_BASE_FULL=y |
| 69 | CONFIG_FUTEX=y | 80 | CONFIG_FUTEX=y |
| 70 | CONFIG_ANON_INODES=y | 81 | CONFIG_ANON_INODES=y |
| 71 | CONFIG_EPOLL=y | 82 | CONFIG_EPOLL=y |
| 72 | CONFIG_SIGNALFD=y | 83 | CONFIG_SIGNALFD=y |
| 84 | CONFIG_TIMERFD=y | ||
| 73 | CONFIG_EVENTFD=y | 85 | CONFIG_EVENTFD=y |
| 74 | CONFIG_SHMEM=y | 86 | CONFIG_SHMEM=y |
| 87 | CONFIG_AIO=y | ||
| 75 | CONFIG_VM_EVENT_COUNTERS=y | 88 | CONFIG_VM_EVENT_COUNTERS=y |
| 76 | CONFIG_SLAB=y | 89 | CONFIG_SLAB=y |
| 77 | # CONFIG_SLUB is not set | 90 | # CONFIG_SLUB is not set |
| 78 | # CONFIG_SLOB is not set | 91 | # CONFIG_SLOB is not set |
| 92 | # CONFIG_PROFILING is not set | ||
| 93 | CONFIG_HAVE_OPROFILE=y | ||
| 94 | # CONFIG_KPROBES is not set | ||
| 95 | CONFIG_HAVE_KPROBES=y | ||
| 96 | CONFIG_HAVE_KRETPROBES=y | ||
| 97 | CONFIG_HAVE_CLK=y | ||
| 98 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 99 | CONFIG_SLABINFO=y | ||
| 79 | CONFIG_RT_MUTEXES=y | 100 | CONFIG_RT_MUTEXES=y |
| 80 | # CONFIG_TINY_SHMEM is not set | ||
| 81 | CONFIG_BASE_SMALL=0 | 101 | CONFIG_BASE_SMALL=0 |
| 82 | CONFIG_MODULES=y | 102 | CONFIG_MODULES=y |
| 103 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 83 | CONFIG_MODULE_UNLOAD=y | 104 | CONFIG_MODULE_UNLOAD=y |
| 84 | CONFIG_MODULE_FORCE_UNLOAD=y | 105 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 85 | # CONFIG_MODVERSIONS is not set | 106 | # CONFIG_MODVERSIONS is not set |
| 86 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 107 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 87 | CONFIG_KMOD=y | ||
| 88 | CONFIG_BLOCK=y | 108 | CONFIG_BLOCK=y |
| 89 | # CONFIG_LBD is not set | 109 | # CONFIG_LBD is not set |
| 90 | # CONFIG_BLK_DEV_IO_TRACE is not set | 110 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 91 | # CONFIG_LSF is not set | ||
| 92 | # CONFIG_BLK_DEV_BSG is not set | 111 | # CONFIG_BLK_DEV_BSG is not set |
| 112 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 93 | 113 | ||
| 94 | # | 114 | # |
| 95 | # IO Schedulers | 115 | # IO Schedulers |
| @@ -103,8 +123,7 @@ CONFIG_IOSCHED_NOOP=y | |||
| 103 | # CONFIG_DEFAULT_CFQ is not set | 123 | # CONFIG_DEFAULT_CFQ is not set |
| 104 | CONFIG_DEFAULT_NOOP=y | 124 | CONFIG_DEFAULT_NOOP=y |
| 105 | CONFIG_DEFAULT_IOSCHED="noop" | 125 | CONFIG_DEFAULT_IOSCHED="noop" |
| 106 | CONFIG_CLASSIC_RCU=y | 126 | CONFIG_FREEZER=y |
| 107 | # CONFIG_PREEMPT_RCU is not set | ||
| 108 | 127 | ||
| 109 | # | 128 | # |
| 110 | # System Type | 129 | # System Type |
| @@ -114,9 +133,7 @@ CONFIG_CLASSIC_RCU=y | |||
| 114 | # CONFIG_ARCH_REALVIEW is not set | 133 | # CONFIG_ARCH_REALVIEW is not set |
| 115 | # CONFIG_ARCH_VERSATILE is not set | 134 | # CONFIG_ARCH_VERSATILE is not set |
| 116 | # CONFIG_ARCH_AT91 is not set | 135 | # CONFIG_ARCH_AT91 is not set |
| 117 | # CONFIG_ARCH_CLPS7500 is not set | ||
| 118 | # CONFIG_ARCH_CLPS711X is not set | 136 | # CONFIG_ARCH_CLPS711X is not set |
| 119 | # CONFIG_ARCH_CO285 is not set | ||
| 120 | # CONFIG_ARCH_EBSA110 is not set | 137 | # CONFIG_ARCH_EBSA110 is not set |
| 121 | # CONFIG_ARCH_EP93XX is not set | 138 | # CONFIG_ARCH_EP93XX is not set |
| 122 | # CONFIG_ARCH_FOOTBRIDGE is not set | 139 | # CONFIG_ARCH_FOOTBRIDGE is not set |
| @@ -130,41 +147,58 @@ CONFIG_CLASSIC_RCU=y | |||
| 130 | # CONFIG_ARCH_IXP2000 is not set | 147 | # CONFIG_ARCH_IXP2000 is not set |
| 131 | # CONFIG_ARCH_IXP4XX is not set | 148 | # CONFIG_ARCH_IXP4XX is not set |
| 132 | # CONFIG_ARCH_L7200 is not set | 149 | # CONFIG_ARCH_L7200 is not set |
| 150 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 133 | # CONFIG_ARCH_KS8695 is not set | 151 | # CONFIG_ARCH_KS8695 is not set |
| 134 | # CONFIG_ARCH_NS9XXX is not set | 152 | # CONFIG_ARCH_NS9XXX is not set |
| 153 | # CONFIG_ARCH_LOKI is not set | ||
| 154 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 135 | # CONFIG_ARCH_MXC is not set | 155 | # CONFIG_ARCH_MXC is not set |
| 156 | # CONFIG_ARCH_ORION5X is not set | ||
| 136 | # CONFIG_ARCH_PNX4008 is not set | 157 | # CONFIG_ARCH_PNX4008 is not set |
| 137 | CONFIG_ARCH_PXA=y | 158 | CONFIG_ARCH_PXA=y |
| 138 | # CONFIG_ARCH_RPC is not set | 159 | # CONFIG_ARCH_RPC is not set |
| 139 | # CONFIG_ARCH_SA1100 is not set | 160 | # CONFIG_ARCH_SA1100 is not set |
| 140 | # CONFIG_ARCH_S3C2410 is not set | 161 | # CONFIG_ARCH_S3C2410 is not set |
| 162 | # CONFIG_ARCH_S3C64XX is not set | ||
| 141 | # CONFIG_ARCH_SHARK is not set | 163 | # CONFIG_ARCH_SHARK is not set |
| 142 | # CONFIG_ARCH_LH7A40X is not set | 164 | # CONFIG_ARCH_LH7A40X is not set |
| 143 | # CONFIG_ARCH_DAVINCI is not set | 165 | # CONFIG_ARCH_DAVINCI is not set |
| 144 | # CONFIG_ARCH_OMAP is not set | 166 | # CONFIG_ARCH_OMAP is not set |
| 167 | # CONFIG_ARCH_MSM is not set | ||
| 168 | # CONFIG_ARCH_W90X900 is not set | ||
| 145 | 169 | ||
| 146 | # | 170 | # |
| 147 | # Intel PXA2xx/PXA3xx Implementations | 171 | # Intel PXA2xx/PXA3xx Implementations |
| 148 | # | 172 | # |
| 173 | # CONFIG_ARCH_GUMSTIX is not set | ||
| 174 | # CONFIG_MACH_INTELMOTE2 is not set | ||
| 149 | # CONFIG_ARCH_LUBBOCK is not set | 175 | # CONFIG_ARCH_LUBBOCK is not set |
| 150 | # CONFIG_MACH_LOGICPD_PXA270 is not set | 176 | # CONFIG_MACH_LOGICPD_PXA270 is not set |
| 151 | # CONFIG_MACH_MAINSTONE is not set | 177 | # CONFIG_MACH_MAINSTONE is not set |
| 178 | # CONFIG_MACH_MP900C is not set | ||
| 152 | # CONFIG_ARCH_PXA_IDP is not set | 179 | # CONFIG_ARCH_PXA_IDP is not set |
| 153 | # CONFIG_PXA_SHARPSL is not set | 180 | # CONFIG_PXA_SHARPSL is not set |
| 154 | # CONFIG_MACH_TRIZEPS4 is not set | 181 | # CONFIG_ARCH_VIPER is not set |
| 182 | # CONFIG_ARCH_PXA_ESERIES is not set | ||
| 183 | # CONFIG_TRIZEPS_PXA is not set | ||
| 184 | # CONFIG_MACH_H5000 is not set | ||
| 155 | # CONFIG_MACH_EM_X270 is not set | 185 | # CONFIG_MACH_EM_X270 is not set |
| 186 | # CONFIG_MACH_COLIBRI is not set | ||
| 156 | # CONFIG_MACH_ZYLONITE is not set | 187 | # CONFIG_MACH_ZYLONITE is not set |
| 188 | # CONFIG_MACH_LITTLETON is not set | ||
| 189 | # CONFIG_MACH_TAVOREVB is not set | ||
| 190 | # CONFIG_MACH_SAAR is not set | ||
| 157 | # CONFIG_MACH_ARMCORE is not set | 191 | # CONFIG_MACH_ARMCORE is not set |
| 192 | # CONFIG_MACH_CM_X300 is not set | ||
| 158 | CONFIG_MACH_MAGICIAN=y | 193 | CONFIG_MACH_MAGICIAN=y |
| 194 | # CONFIG_MACH_MIOA701 is not set | ||
| 195 | # CONFIG_MACH_PCM027 is not set | ||
| 196 | # CONFIG_ARCH_PXA_PALM is not set | ||
| 197 | # CONFIG_PXA_EZX is not set | ||
| 159 | CONFIG_PXA27x=y | 198 | CONFIG_PXA27x=y |
| 160 | 199 | CONFIG_PXA_SSP=y | |
| 161 | # | 200 | CONFIG_PXA_PWM=y |
| 162 | # Boot options | 201 | CONFIG_PXA_HAVE_BOARD_IRQS=y |
| 163 | # | ||
| 164 | |||
| 165 | # | ||
| 166 | # Power management | ||
| 167 | # | ||
| 168 | 202 | ||
| 169 | # | 203 | # |
| 170 | # Processor Type | 204 | # Processor Type |
| @@ -173,6 +207,7 @@ CONFIG_CPU_32=y | |||
| 173 | CONFIG_CPU_XSCALE=y | 207 | CONFIG_CPU_XSCALE=y |
| 174 | CONFIG_CPU_32v5=y | 208 | CONFIG_CPU_32v5=y |
| 175 | CONFIG_CPU_ABRT_EV5T=y | 209 | CONFIG_CPU_ABRT_EV5T=y |
| 210 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 176 | CONFIG_CPU_CACHE_VIVT=y | 211 | CONFIG_CPU_CACHE_VIVT=y |
| 177 | CONFIG_CPU_TLB_V4WBI=y | 212 | CONFIG_CPU_TLB_V4WBI=y |
| 178 | CONFIG_CPU_CP15=y | 213 | CONFIG_CPU_CP15=y |
| @@ -186,6 +221,7 @@ CONFIG_ARM_THUMB=y | |||
| 186 | # CONFIG_OUTER_CACHE is not set | 221 | # CONFIG_OUTER_CACHE is not set |
| 187 | CONFIG_IWMMXT=y | 222 | CONFIG_IWMMXT=y |
| 188 | CONFIG_XSCALE_PMU=y | 223 | CONFIG_XSCALE_PMU=y |
| 224 | CONFIG_COMMON_CLKDEV=y | ||
| 189 | 225 | ||
| 190 | # | 226 | # |
| 191 | # Bus support | 227 | # Bus support |
| @@ -197,28 +233,33 @@ CONFIG_XSCALE_PMU=y | |||
| 197 | # | 233 | # |
| 198 | # Kernel Features | 234 | # Kernel Features |
| 199 | # | 235 | # |
| 200 | # CONFIG_TICK_ONESHOT is not set | 236 | CONFIG_TICK_ONESHOT=y |
| 201 | # CONFIG_NO_HZ is not set | 237 | CONFIG_NO_HZ=y |
| 202 | # CONFIG_HIGH_RES_TIMERS is not set | 238 | # CONFIG_HIGH_RES_TIMERS is not set |
| 203 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 239 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| 240 | CONFIG_VMSPLIT_3G=y | ||
| 241 | # CONFIG_VMSPLIT_2G is not set | ||
| 242 | # CONFIG_VMSPLIT_1G is not set | ||
| 243 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 204 | CONFIG_PREEMPT=y | 244 | CONFIG_PREEMPT=y |
| 205 | CONFIG_HZ=100 | 245 | CONFIG_HZ=100 |
| 206 | CONFIG_AEABI=y | 246 | CONFIG_AEABI=y |
| 207 | CONFIG_OABI_COMPAT=y | 247 | CONFIG_OABI_COMPAT=y |
| 208 | # CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set | 248 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y |
| 249 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 250 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 209 | CONFIG_SELECT_MEMORY_MODEL=y | 251 | CONFIG_SELECT_MEMORY_MODEL=y |
| 210 | CONFIG_FLATMEM_MANUAL=y | 252 | CONFIG_FLATMEM_MANUAL=y |
| 211 | # CONFIG_DISCONTIGMEM_MANUAL is not set | 253 | # CONFIG_DISCONTIGMEM_MANUAL is not set |
| 212 | # CONFIG_SPARSEMEM_MANUAL is not set | 254 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 213 | CONFIG_FLATMEM=y | 255 | CONFIG_FLATMEM=y |
| 214 | CONFIG_FLAT_NODE_MEM_MAP=y | 256 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 215 | # CONFIG_SPARSEMEM_STATIC is not set | 257 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 216 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 217 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 258 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 218 | # CONFIG_RESOURCES_64BIT is not set | 259 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 219 | CONFIG_ZONE_DMA_FLAG=1 | 260 | CONFIG_ZONE_DMA_FLAG=0 |
| 220 | CONFIG_BOUNCE=y | ||
| 221 | CONFIG_VIRT_TO_BUS=y | 261 | CONFIG_VIRT_TO_BUS=y |
| 262 | CONFIG_UNEVICTABLE_LRU=y | ||
| 222 | CONFIG_ALIGNMENT_TRAP=y | 263 | CONFIG_ALIGNMENT_TRAP=y |
| 223 | 264 | ||
| 224 | # | 265 | # |
| @@ -229,9 +270,10 @@ CONFIG_ZBOOT_ROM_BSS=0x0 | |||
| 229 | CONFIG_CMDLINE="keepinitrd" | 270 | CONFIG_CMDLINE="keepinitrd" |
| 230 | # CONFIG_XIP_KERNEL is not set | 271 | # CONFIG_XIP_KERNEL is not set |
| 231 | CONFIG_KEXEC=y | 272 | CONFIG_KEXEC=y |
| 273 | CONFIG_ATAGS_PROC=y | ||
| 232 | 274 | ||
| 233 | # | 275 | # |
| 234 | # CPU Frequency scaling | 276 | # CPU Power Management |
| 235 | # | 277 | # |
| 236 | CONFIG_CPU_FREQ=y | 278 | CONFIG_CPU_FREQ=y |
| 237 | CONFIG_CPU_FREQ_TABLE=y | 279 | CONFIG_CPU_FREQ_TABLE=y |
| @@ -239,6 +281,7 @@ CONFIG_CPU_FREQ_TABLE=y | |||
| 239 | CONFIG_CPU_FREQ_STAT=y | 281 | CONFIG_CPU_FREQ_STAT=y |
| 240 | # CONFIG_CPU_FREQ_STAT_DETAILS is not set | 282 | # CONFIG_CPU_FREQ_STAT_DETAILS is not set |
| 241 | CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y | 283 | CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y |
| 284 | # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set | ||
| 242 | # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set | 285 | # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set |
| 243 | # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set | 286 | # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set |
| 244 | # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set | 287 | # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set |
| @@ -247,6 +290,7 @@ CONFIG_CPU_FREQ_GOV_PERFORMANCE=y | |||
| 247 | # CONFIG_CPU_FREQ_GOV_USERSPACE is not set | 290 | # CONFIG_CPU_FREQ_GOV_USERSPACE is not set |
| 248 | CONFIG_CPU_FREQ_GOV_ONDEMAND=y | 291 | CONFIG_CPU_FREQ_GOV_ONDEMAND=y |
| 249 | # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set | 292 | # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set |
| 293 | # CONFIG_CPU_IDLE is not set | ||
| 250 | 294 | ||
| 251 | # | 295 | # |
| 252 | # Floating point emulation | 296 | # Floating point emulation |
| @@ -263,6 +307,8 @@ CONFIG_FPE_NWFPE=y | |||
| 263 | # Userspace binary formats | 307 | # Userspace binary formats |
| 264 | # | 308 | # |
| 265 | CONFIG_BINFMT_ELF=y | 309 | CONFIG_BINFMT_ELF=y |
| 310 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 311 | CONFIG_HAVE_AOUT=y | ||
| 266 | # CONFIG_BINFMT_AOUT is not set | 312 | # CONFIG_BINFMT_AOUT is not set |
| 267 | # CONFIG_BINFMT_MISC is not set | 313 | # CONFIG_BINFMT_MISC is not set |
| 268 | 314 | ||
| @@ -270,21 +316,18 @@ CONFIG_BINFMT_ELF=y | |||
| 270 | # Power management options | 316 | # Power management options |
| 271 | # | 317 | # |
| 272 | CONFIG_PM=y | 318 | CONFIG_PM=y |
| 273 | # CONFIG_PM_LEGACY is not set | ||
| 274 | # CONFIG_PM_DEBUG is not set | 319 | # CONFIG_PM_DEBUG is not set |
| 275 | CONFIG_PM_SLEEP=y | 320 | CONFIG_PM_SLEEP=y |
| 276 | CONFIG_SUSPEND_UP_POSSIBLE=y | ||
| 277 | CONFIG_SUSPEND=y | 321 | CONFIG_SUSPEND=y |
| 278 | CONFIG_APM_EMULATION=y | 322 | CONFIG_SUSPEND_FREEZER=y |
| 279 | 323 | # CONFIG_APM_EMULATION is not set | |
| 280 | # | 324 | CONFIG_ARCH_SUSPEND_POSSIBLE=y |
| 281 | # Networking | ||
| 282 | # | ||
| 283 | CONFIG_NET=y | 325 | CONFIG_NET=y |
| 284 | 326 | ||
| 285 | # | 327 | # |
| 286 | # Networking options | 328 | # Networking options |
| 287 | # | 329 | # |
| 330 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 288 | CONFIG_PACKET=y | 331 | CONFIG_PACKET=y |
| 289 | CONFIG_PACKET_MMAP=y | 332 | CONFIG_PACKET_MMAP=y |
| 290 | CONFIG_UNIX=y | 333 | CONFIG_UNIX=y |
| @@ -316,33 +359,15 @@ CONFIG_IP_PNP=y | |||
| 316 | CONFIG_TCP_CONG_CUBIC=y | 359 | CONFIG_TCP_CONG_CUBIC=y |
| 317 | CONFIG_DEFAULT_TCP_CONG="cubic" | 360 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 318 | # CONFIG_TCP_MD5SIG is not set | 361 | # CONFIG_TCP_MD5SIG is not set |
| 319 | # CONFIG_IP_VS is not set | ||
| 320 | # CONFIG_IPV6 is not set | 362 | # CONFIG_IPV6 is not set |
| 321 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 322 | # CONFIG_INET6_TUNNEL is not set | ||
| 323 | # CONFIG_NETWORK_SECMARK is not set | 363 | # CONFIG_NETWORK_SECMARK is not set |
| 324 | CONFIG_NETFILTER=y | 364 | # CONFIG_NETFILTER is not set |
| 325 | # CONFIG_NETFILTER_DEBUG is not set | ||
| 326 | |||
| 327 | # | ||
| 328 | # Core Netfilter Configuration | ||
| 329 | # | ||
| 330 | # CONFIG_NETFILTER_NETLINK is not set | ||
| 331 | # CONFIG_NF_CONNTRACK_ENABLED is not set | ||
| 332 | # CONFIG_NF_CONNTRACK is not set | ||
| 333 | # CONFIG_NETFILTER_XTABLES is not set | ||
| 334 | |||
| 335 | # | ||
| 336 | # IP: Netfilter Configuration | ||
| 337 | # | ||
| 338 | # CONFIG_IP_NF_QUEUE is not set | ||
| 339 | # CONFIG_IP_NF_IPTABLES is not set | ||
| 340 | # CONFIG_IP_NF_ARPTABLES is not set | ||
| 341 | # CONFIG_IP_DCCP is not set | 365 | # CONFIG_IP_DCCP is not set |
| 342 | # CONFIG_IP_SCTP is not set | 366 | # CONFIG_IP_SCTP is not set |
| 343 | # CONFIG_TIPC is not set | 367 | # CONFIG_TIPC is not set |
| 344 | # CONFIG_ATM is not set | 368 | # CONFIG_ATM is not set |
| 345 | # CONFIG_BRIDGE is not set | 369 | # CONFIG_BRIDGE is not set |
| 370 | # CONFIG_NET_DSA is not set | ||
| 346 | # CONFIG_VLAN_8021Q is not set | 371 | # CONFIG_VLAN_8021Q is not set |
| 347 | # CONFIG_DECNET is not set | 372 | # CONFIG_DECNET is not set |
| 348 | # CONFIG_LLC2 is not set | 373 | # CONFIG_LLC2 is not set |
| @@ -353,6 +378,7 @@ CONFIG_NETFILTER=y | |||
| 353 | # CONFIG_ECONET is not set | 378 | # CONFIG_ECONET is not set |
| 354 | # CONFIG_WAN_ROUTER is not set | 379 | # CONFIG_WAN_ROUTER is not set |
| 355 | # CONFIG_NET_SCHED is not set | 380 | # CONFIG_NET_SCHED is not set |
| 381 | # CONFIG_DCB is not set | ||
| 356 | 382 | ||
| 357 | # | 383 | # |
| 358 | # Network testing | 384 | # Network testing |
| @@ -390,20 +416,17 @@ CONFIG_IRTTY_SIR=m | |||
| 390 | # Dongle support | 416 | # Dongle support |
| 391 | # | 417 | # |
| 392 | # CONFIG_DONGLE is not set | 418 | # CONFIG_DONGLE is not set |
| 393 | 419 | # CONFIG_KINGSUN_DONGLE is not set | |
| 394 | # | 420 | # CONFIG_KSDAZZLE_DONGLE is not set |
| 395 | # Old SIR device drivers | 421 | # CONFIG_KS959_DONGLE is not set |
| 396 | # | ||
| 397 | # CONFIG_IRPORT_SIR is not set | ||
| 398 | |||
| 399 | # | ||
| 400 | # Old Serial dongle support | ||
| 401 | # | ||
| 402 | 422 | ||
| 403 | # | 423 | # |
| 404 | # FIR device drivers | 424 | # FIR device drivers |
| 405 | # | 425 | # |
| 426 | # CONFIG_USB_IRDA is not set | ||
| 427 | # CONFIG_SIGMATEL_FIR is not set | ||
| 406 | CONFIG_PXA_FICP=m | 428 | CONFIG_PXA_FICP=m |
| 429 | # CONFIG_MCS_FIR is not set | ||
| 407 | CONFIG_BT=m | 430 | CONFIG_BT=m |
| 408 | CONFIG_BT_L2CAP=m | 431 | CONFIG_BT_L2CAP=m |
| 409 | CONFIG_BT_SCO=m | 432 | CONFIG_BT_SCO=m |
| @@ -417,17 +440,17 @@ CONFIG_BT_HIDP=m | |||
| 417 | # | 440 | # |
| 418 | # Bluetooth device drivers | 441 | # Bluetooth device drivers |
| 419 | # | 442 | # |
| 443 | CONFIG_BT_HCIBTUSB=m | ||
| 444 | # CONFIG_BT_HCIBTSDIO is not set | ||
| 420 | # CONFIG_BT_HCIUART is not set | 445 | # CONFIG_BT_HCIUART is not set |
| 446 | # CONFIG_BT_HCIBCM203X is not set | ||
| 447 | # CONFIG_BT_HCIBPA10X is not set | ||
| 448 | # CONFIG_BT_HCIBFUSB is not set | ||
| 421 | # CONFIG_BT_HCIVHCI is not set | 449 | # CONFIG_BT_HCIVHCI is not set |
| 422 | # CONFIG_AF_RXRPC is not set | 450 | # CONFIG_AF_RXRPC is not set |
| 423 | 451 | # CONFIG_PHONET is not set | |
| 424 | # | 452 | # CONFIG_WIRELESS is not set |
| 425 | # Wireless | 453 | # CONFIG_WIMAX is not set |
| 426 | # | ||
| 427 | # CONFIG_CFG80211 is not set | ||
| 428 | # CONFIG_WIRELESS_EXT is not set | ||
| 429 | # CONFIG_MAC80211 is not set | ||
| 430 | # CONFIG_IEEE80211 is not set | ||
| 431 | # CONFIG_RFKILL is not set | 454 | # CONFIG_RFKILL is not set |
| 432 | # CONFIG_NET_9P is not set | 455 | # CONFIG_NET_9P is not set |
| 433 | 456 | ||
| @@ -442,25 +465,28 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |||
| 442 | CONFIG_STANDALONE=y | 465 | CONFIG_STANDALONE=y |
| 443 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 466 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 444 | CONFIG_FW_LOADER=y | 467 | CONFIG_FW_LOADER=y |
| 468 | # CONFIG_FIRMWARE_IN_KERNEL is not set | ||
| 469 | CONFIG_EXTRA_FIRMWARE="" | ||
| 445 | # CONFIG_DEBUG_DRIVER is not set | 470 | # CONFIG_DEBUG_DRIVER is not set |
| 446 | # CONFIG_DEBUG_DEVRES is not set | 471 | # CONFIG_DEBUG_DEVRES is not set |
| 447 | # CONFIG_SYS_HYPERVISOR is not set | 472 | # CONFIG_SYS_HYPERVISOR is not set |
| 448 | # CONFIG_CONNECTOR is not set | 473 | # CONFIG_CONNECTOR is not set |
| 449 | CONFIG_MTD=y | 474 | CONFIG_MTD=y |
| 450 | CONFIG_MTD_DEBUG=y | 475 | # CONFIG_MTD_DEBUG is not set |
| 451 | CONFIG_MTD_DEBUG_VERBOSE=0 | ||
| 452 | # CONFIG_MTD_CONCAT is not set | 476 | # CONFIG_MTD_CONCAT is not set |
| 453 | CONFIG_MTD_PARTITIONS=y | 477 | CONFIG_MTD_PARTITIONS=y |
| 478 | # CONFIG_MTD_TESTS is not set | ||
| 454 | # CONFIG_MTD_REDBOOT_PARTS is not set | 479 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 455 | CONFIG_MTD_CMDLINE_PARTS=y | 480 | CONFIG_MTD_CMDLINE_PARTS=y |
| 456 | # CONFIG_MTD_AFS_PARTS is not set | 481 | # CONFIG_MTD_AFS_PARTS is not set |
| 482 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 457 | 483 | ||
| 458 | # | 484 | # |
| 459 | # User Modules And Translation Layers | 485 | # User Modules And Translation Layers |
| 460 | # | 486 | # |
| 461 | CONFIG_MTD_CHAR=m | 487 | CONFIG_MTD_CHAR=y |
| 462 | CONFIG_MTD_BLKDEVS=m | 488 | CONFIG_MTD_BLKDEVS=y |
| 463 | CONFIG_MTD_BLOCK=m | 489 | CONFIG_MTD_BLOCK=y |
| 464 | # CONFIG_FTL is not set | 490 | # CONFIG_FTL is not set |
| 465 | # CONFIG_NFTL is not set | 491 | # CONFIG_NFTL is not set |
| 466 | # CONFIG_INFTL is not set | 492 | # CONFIG_INFTL is not set |
| @@ -473,6 +499,7 @@ CONFIG_MTD_BLOCK=m | |||
| 473 | # | 499 | # |
| 474 | CONFIG_MTD_CFI=y | 500 | CONFIG_MTD_CFI=y |
| 475 | # CONFIG_MTD_JEDECPROBE is not set | 501 | # CONFIG_MTD_JEDECPROBE is not set |
| 502 | CONFIG_MTD_GEN_PROBE=y | ||
| 476 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | 503 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set |
| 477 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | 504 | CONFIG_MTD_MAP_BANK_WIDTH_1=y |
| 478 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | 505 | CONFIG_MTD_MAP_BANK_WIDTH_2=y |
| @@ -487,6 +514,7 @@ CONFIG_MTD_CFI_I2=y | |||
| 487 | CONFIG_MTD_CFI_INTELEXT=y | 514 | CONFIG_MTD_CFI_INTELEXT=y |
| 488 | # CONFIG_MTD_CFI_AMDSTD is not set | 515 | # CONFIG_MTD_CFI_AMDSTD is not set |
| 489 | # CONFIG_MTD_CFI_STAA is not set | 516 | # CONFIG_MTD_CFI_STAA is not set |
| 517 | CONFIG_MTD_CFI_UTIL=y | ||
| 490 | # CONFIG_MTD_RAM is not set | 518 | # CONFIG_MTD_RAM is not set |
| 491 | # CONFIG_MTD_ROM is not set | 519 | # CONFIG_MTD_ROM is not set |
| 492 | # CONFIG_MTD_ABSENT is not set | 520 | # CONFIG_MTD_ABSENT is not set |
| @@ -497,9 +525,7 @@ CONFIG_MTD_CFI_INTELEXT=y | |||
| 497 | # | 525 | # |
| 498 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | 526 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set |
| 499 | CONFIG_MTD_PHYSMAP=y | 527 | CONFIG_MTD_PHYSMAP=y |
| 500 | CONFIG_MTD_PHYSMAP_START=0x00000000 | 528 | # CONFIG_MTD_PHYSMAP_COMPAT is not set |
| 501 | CONFIG_MTD_PHYSMAP_LEN=0x04000000 | ||
| 502 | CONFIG_MTD_PHYSMAP_BANKWIDTH=4 | ||
| 503 | # CONFIG_MTD_PXA2XX is not set | 529 | # CONFIG_MTD_PXA2XX is not set |
| 504 | # CONFIG_MTD_ARM_INTEGRATOR is not set | 530 | # CONFIG_MTD_ARM_INTEGRATOR is not set |
| 505 | # CONFIG_MTD_SHARP_SL is not set | 531 | # CONFIG_MTD_SHARP_SL is not set |
| @@ -523,6 +549,12 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=4 | |||
| 523 | # CONFIG_MTD_ONENAND is not set | 549 | # CONFIG_MTD_ONENAND is not set |
| 524 | 550 | ||
| 525 | # | 551 | # |
| 552 | # LPDDR flash memory drivers | ||
| 553 | # | ||
| 554 | # CONFIG_MTD_LPDDR is not set | ||
| 555 | # CONFIG_MTD_QINFO_PROBE is not set | ||
| 556 | |||
| 557 | # | ||
| 526 | # UBI - Unsorted block images | 558 | # UBI - Unsorted block images |
| 527 | # | 559 | # |
| 528 | # CONFIG_MTD_UBI is not set | 560 | # CONFIG_MTD_UBI is not set |
| @@ -531,10 +563,12 @@ CONFIG_BLK_DEV=y | |||
| 531 | # CONFIG_BLK_DEV_COW_COMMON is not set | 563 | # CONFIG_BLK_DEV_COW_COMMON is not set |
| 532 | # CONFIG_BLK_DEV_LOOP is not set | 564 | # CONFIG_BLK_DEV_LOOP is not set |
| 533 | # CONFIG_BLK_DEV_NBD is not set | 565 | # CONFIG_BLK_DEV_NBD is not set |
| 566 | # CONFIG_BLK_DEV_UB is not set | ||
| 534 | # CONFIG_BLK_DEV_RAM is not set | 567 | # CONFIG_BLK_DEV_RAM is not set |
| 535 | # CONFIG_CDROM_PKTCDVD is not set | 568 | # CONFIG_CDROM_PKTCDVD is not set |
| 536 | # CONFIG_ATA_OVER_ETH is not set | 569 | # CONFIG_ATA_OVER_ETH is not set |
| 537 | # CONFIG_MISC_DEVICES is not set | 570 | # CONFIG_MISC_DEVICES is not set |
| 571 | CONFIG_HAVE_IDE=y | ||
| 538 | # CONFIG_IDE is not set | 572 | # CONFIG_IDE is not set |
| 539 | 573 | ||
| 540 | # | 574 | # |
| @@ -547,7 +581,6 @@ CONFIG_BLK_DEV=y | |||
| 547 | # CONFIG_ATA is not set | 581 | # CONFIG_ATA is not set |
| 548 | # CONFIG_MD is not set | 582 | # CONFIG_MD is not set |
| 549 | CONFIG_NETDEVICES=y | 583 | CONFIG_NETDEVICES=y |
| 550 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 551 | # CONFIG_DUMMY is not set | 584 | # CONFIG_DUMMY is not set |
| 552 | # CONFIG_BONDING is not set | 585 | # CONFIG_BONDING is not set |
| 553 | # CONFIG_MACVLAN is not set | 586 | # CONFIG_MACVLAN is not set |
| @@ -563,6 +596,20 @@ CONFIG_NETDEVICES=y | |||
| 563 | # | 596 | # |
| 564 | # CONFIG_WLAN_PRE80211 is not set | 597 | # CONFIG_WLAN_PRE80211 is not set |
| 565 | # CONFIG_WLAN_80211 is not set | 598 | # CONFIG_WLAN_80211 is not set |
| 599 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 600 | |||
| 601 | # | ||
| 602 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 603 | # | ||
| 604 | |||
| 605 | # | ||
| 606 | # USB Network Adapters | ||
| 607 | # | ||
| 608 | # CONFIG_USB_CATC is not set | ||
| 609 | # CONFIG_USB_KAWETH is not set | ||
| 610 | # CONFIG_USB_PEGASUS is not set | ||
| 611 | # CONFIG_USB_RTL8150 is not set | ||
| 612 | # CONFIG_USB_USBNET is not set | ||
| 566 | # CONFIG_WAN is not set | 613 | # CONFIG_WAN is not set |
| 567 | CONFIG_PPP=m | 614 | CONFIG_PPP=m |
| 568 | # CONFIG_PPP_MULTILINK is not set | 615 | # CONFIG_PPP_MULTILINK is not set |
| @@ -612,7 +659,26 @@ CONFIG_KEYBOARD_GPIO=y | |||
| 612 | # CONFIG_INPUT_JOYSTICK is not set | 659 | # CONFIG_INPUT_JOYSTICK is not set |
| 613 | # CONFIG_INPUT_TABLET is not set | 660 | # CONFIG_INPUT_TABLET is not set |
| 614 | CONFIG_INPUT_TOUCHSCREEN=y | 661 | CONFIG_INPUT_TOUCHSCREEN=y |
| 662 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 663 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
| 664 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
| 665 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 666 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
| 667 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 668 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
| 669 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
| 670 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
| 671 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
| 672 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
| 673 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 674 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 615 | CONFIG_INPUT_MISC=y | 675 | CONFIG_INPUT_MISC=y |
| 676 | # CONFIG_INPUT_ATI_REMOTE is not set | ||
| 677 | # CONFIG_INPUT_ATI_REMOTE2 is not set | ||
| 678 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | ||
| 679 | # CONFIG_INPUT_POWERMATE is not set | ||
| 680 | # CONFIG_INPUT_YEALINK is not set | ||
| 681 | # CONFIG_INPUT_CM109 is not set | ||
| 616 | CONFIG_INPUT_UINPUT=m | 682 | CONFIG_INPUT_UINPUT=m |
| 617 | 683 | ||
| 618 | # | 684 | # |
| @@ -625,9 +691,11 @@ CONFIG_INPUT_UINPUT=m | |||
| 625 | # Character devices | 691 | # Character devices |
| 626 | # | 692 | # |
| 627 | CONFIG_VT=y | 693 | CONFIG_VT=y |
| 694 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 628 | CONFIG_VT_CONSOLE=y | 695 | CONFIG_VT_CONSOLE=y |
| 629 | CONFIG_HW_CONSOLE=y | 696 | CONFIG_HW_CONSOLE=y |
| 630 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | 697 | # CONFIG_VT_HW_CONSOLE_BINDING is not set |
| 698 | # CONFIG_DEVKMEM is not set | ||
| 631 | # CONFIG_SERIAL_NONSTANDARD is not set | 699 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 632 | 700 | ||
| 633 | # | 701 | # |
| @@ -642,6 +710,7 @@ CONFIG_SERIAL_PXA=y | |||
| 642 | # CONFIG_SERIAL_PXA_CONSOLE is not set | 710 | # CONFIG_SERIAL_PXA_CONSOLE is not set |
| 643 | CONFIG_SERIAL_CORE=y | 711 | CONFIG_SERIAL_CORE=y |
| 644 | CONFIG_UNIX98_PTYS=y | 712 | CONFIG_UNIX98_PTYS=y |
| 713 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 645 | # CONFIG_LEGACY_PTYS is not set | 714 | # CONFIG_LEGACY_PTYS is not set |
| 646 | # CONFIG_IPMI_HANDLER is not set | 715 | # CONFIG_IPMI_HANDLER is not set |
| 647 | # CONFIG_HW_RANDOM is not set | 716 | # CONFIG_HW_RANDOM is not set |
| @@ -649,37 +718,45 @@ CONFIG_UNIX98_PTYS=y | |||
| 649 | # CONFIG_R3964 is not set | 718 | # CONFIG_R3964 is not set |
| 650 | # CONFIG_RAW_DRIVER is not set | 719 | # CONFIG_RAW_DRIVER is not set |
| 651 | # CONFIG_TCG_TPM is not set | 720 | # CONFIG_TCG_TPM is not set |
| 652 | CONFIG_I2C=m | 721 | CONFIG_I2C=y |
| 653 | CONFIG_I2C_BOARDINFO=y | 722 | CONFIG_I2C_BOARDINFO=y |
| 654 | CONFIG_I2C_CHARDEV=m | 723 | CONFIG_I2C_CHARDEV=m |
| 724 | CONFIG_I2C_HELPER_AUTO=y | ||
| 655 | 725 | ||
| 656 | # | 726 | # |
| 657 | # I2C Algorithms | 727 | # I2C Hardware Bus support |
| 658 | # | 728 | # |
| 659 | # CONFIG_I2C_ALGOBIT is not set | ||
| 660 | # CONFIG_I2C_ALGOPCF is not set | ||
| 661 | # CONFIG_I2C_ALGOPCA is not set | ||
| 662 | 729 | ||
| 663 | # | 730 | # |
| 664 | # I2C Hardware Bus support | 731 | # I2C system bus drivers (mostly embedded / system-on-chip) |
| 665 | # | 732 | # |
| 666 | # CONFIG_I2C_GPIO is not set | 733 | # CONFIG_I2C_GPIO is not set |
| 667 | CONFIG_I2C_PXA=m | ||
| 668 | # CONFIG_I2C_PXA_SLAVE is not set | ||
| 669 | # CONFIG_I2C_OCORES is not set | 734 | # CONFIG_I2C_OCORES is not set |
| 670 | # CONFIG_I2C_PARPORT_LIGHT is not set | 735 | CONFIG_I2C_PXA=y |
| 736 | # CONFIG_I2C_PXA_SLAVE is not set | ||
| 671 | # CONFIG_I2C_SIMTEC is not set | 737 | # CONFIG_I2C_SIMTEC is not set |
| 738 | |||
| 739 | # | ||
| 740 | # External I2C/SMBus adapter drivers | ||
| 741 | # | ||
| 742 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 672 | # CONFIG_I2C_TAOS_EVM is not set | 743 | # CONFIG_I2C_TAOS_EVM is not set |
| 744 | # CONFIG_I2C_TINY_USB is not set | ||
| 745 | |||
| 746 | # | ||
| 747 | # Other I2C/SMBus bus drivers | ||
| 748 | # | ||
| 749 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 673 | # CONFIG_I2C_STUB is not set | 750 | # CONFIG_I2C_STUB is not set |
| 674 | 751 | ||
| 675 | # | 752 | # |
| 676 | # Miscellaneous I2C Chip support | 753 | # Miscellaneous I2C Chip support |
| 677 | # | 754 | # |
| 678 | # CONFIG_SENSORS_DS1337 is not set | ||
| 679 | # CONFIG_SENSORS_DS1374 is not set | ||
| 680 | # CONFIG_DS1682 is not set | 755 | # CONFIG_DS1682 is not set |
| 756 | # CONFIG_AT24 is not set | ||
| 681 | # CONFIG_EEPROM_LEGACY is not set | 757 | # CONFIG_EEPROM_LEGACY is not set |
| 682 | # CONFIG_SENSORS_PCF8574 is not set | 758 | # CONFIG_SENSORS_PCF8574 is not set |
| 759 | # CONFIG_PCF8575 is not set | ||
| 683 | # CONFIG_SENSORS_PCA9539 is not set | 760 | # CONFIG_SENSORS_PCA9539 is not set |
| 684 | # CONFIG_SENSORS_PCF8591 is not set | 761 | # CONFIG_SENSORS_PCF8591 is not set |
| 685 | # CONFIG_SENSORS_MAX6875 is not set | 762 | # CONFIG_SENSORS_MAX6875 is not set |
| @@ -688,19 +765,39 @@ CONFIG_I2C_PXA=m | |||
| 688 | # CONFIG_I2C_DEBUG_ALGO is not set | 765 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 689 | # CONFIG_I2C_DEBUG_BUS is not set | 766 | # CONFIG_I2C_DEBUG_BUS is not set |
| 690 | # CONFIG_I2C_DEBUG_CHIP is not set | 767 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 768 | # CONFIG_SPI is not set | ||
| 769 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 770 | CONFIG_GPIOLIB=y | ||
| 771 | # CONFIG_DEBUG_GPIO is not set | ||
| 772 | # CONFIG_GPIO_SYSFS is not set | ||
| 691 | 773 | ||
| 692 | # | 774 | # |
| 693 | # SPI support | 775 | # Memory mapped GPIO expanders: |
| 776 | # | ||
| 777 | |||
| 778 | # | ||
| 779 | # I2C GPIO expanders: | ||
| 780 | # | ||
| 781 | # CONFIG_GPIO_MAX732X is not set | ||
| 782 | # CONFIG_GPIO_PCA953X is not set | ||
| 783 | # CONFIG_GPIO_PCF857X is not set | ||
| 784 | |||
| 785 | # | ||
| 786 | # PCI GPIO expanders: | ||
| 787 | # | ||
| 788 | |||
| 789 | # | ||
| 790 | # SPI GPIO expanders: | ||
| 694 | # | 791 | # |
| 695 | # CONFIG_SPI is not set | ||
| 696 | # CONFIG_SPI_MASTER is not set | ||
| 697 | CONFIG_W1=y | 792 | CONFIG_W1=y |
| 698 | 793 | ||
| 699 | # | 794 | # |
| 700 | # 1-wire Bus Masters | 795 | # 1-wire Bus Masters |
| 701 | # | 796 | # |
| 797 | # CONFIG_W1_MASTER_DS2490 is not set | ||
| 702 | # CONFIG_W1_MASTER_DS2482 is not set | 798 | # CONFIG_W1_MASTER_DS2482 is not set |
| 703 | CONFIG_W1_MASTER_DS1WM=y | 799 | CONFIG_W1_MASTER_DS1WM=y |
| 800 | # CONFIG_W1_MASTER_GPIO is not set | ||
| 704 | 801 | ||
| 705 | # | 802 | # |
| 706 | # 1-wire Slaves | 803 | # 1-wire Slaves |
| @@ -709,32 +806,56 @@ CONFIG_W1_MASTER_DS1WM=y | |||
| 709 | # CONFIG_W1_SLAVE_SMEM is not set | 806 | # CONFIG_W1_SLAVE_SMEM is not set |
| 710 | # CONFIG_W1_SLAVE_DS2433 is not set | 807 | # CONFIG_W1_SLAVE_DS2433 is not set |
| 711 | CONFIG_W1_SLAVE_DS2760=y | 808 | CONFIG_W1_SLAVE_DS2760=y |
| 809 | # CONFIG_W1_SLAVE_BQ27000 is not set | ||
| 712 | CONFIG_POWER_SUPPLY=y | 810 | CONFIG_POWER_SUPPLY=y |
| 713 | # CONFIG_POWER_SUPPLY_DEBUG is not set | 811 | # CONFIG_POWER_SUPPLY_DEBUG is not set |
| 714 | CONFIG_PDA_POWER=y | 812 | CONFIG_PDA_POWER=y |
| 715 | # CONFIG_APM_POWER is not set | ||
| 716 | CONFIG_BATTERY_DS2760=y | 813 | CONFIG_BATTERY_DS2760=y |
| 814 | # CONFIG_BATTERY_BQ27x00 is not set | ||
| 717 | # CONFIG_HWMON is not set | 815 | # CONFIG_HWMON is not set |
| 816 | # CONFIG_THERMAL is not set | ||
| 817 | # CONFIG_THERMAL_HWMON is not set | ||
| 718 | # CONFIG_WATCHDOG is not set | 818 | # CONFIG_WATCHDOG is not set |
| 819 | CONFIG_SSB_POSSIBLE=y | ||
| 719 | 820 | ||
| 720 | # | 821 | # |
| 721 | # Sonics Silicon Backplane | 822 | # Sonics Silicon Backplane |
| 722 | # | 823 | # |
| 723 | CONFIG_SSB_POSSIBLE=y | ||
| 724 | # CONFIG_SSB is not set | 824 | # CONFIG_SSB is not set |
| 725 | 825 | ||
| 726 | # | 826 | # |
| 727 | # Multifunction device drivers | 827 | # Multifunction device drivers |
| 728 | # | 828 | # |
| 829 | # CONFIG_MFD_CORE is not set | ||
| 729 | # CONFIG_MFD_SM501 is not set | 830 | # CONFIG_MFD_SM501 is not set |
| 831 | # CONFIG_MFD_ASIC3 is not set | ||
| 730 | CONFIG_HTC_EGPIO=y | 832 | CONFIG_HTC_EGPIO=y |
| 731 | CONFIG_HTC_PASIC3=y | 833 | CONFIG_HTC_PASIC3=y |
| 834 | # CONFIG_TPS65010 is not set | ||
| 835 | # CONFIG_TWL4030_CORE is not set | ||
| 836 | # CONFIG_MFD_TMIO is not set | ||
| 837 | # CONFIG_MFD_T7L66XB is not set | ||
| 838 | # CONFIG_MFD_TC6387XB is not set | ||
| 839 | # CONFIG_MFD_TC6393XB is not set | ||
| 840 | # CONFIG_PMIC_DA903X is not set | ||
| 841 | # CONFIG_MFD_WM8400 is not set | ||
| 842 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 843 | # CONFIG_MFD_PCF50633 is not set | ||
| 732 | 844 | ||
| 733 | # | 845 | # |
| 734 | # Multimedia devices | 846 | # Multimedia devices |
| 735 | # | 847 | # |
| 848 | |||
| 849 | # | ||
| 850 | # Multimedia core support | ||
| 851 | # | ||
| 736 | # CONFIG_VIDEO_DEV is not set | 852 | # CONFIG_VIDEO_DEV is not set |
| 737 | # CONFIG_DVB_CORE is not set | 853 | # CONFIG_DVB_CORE is not set |
| 854 | # CONFIG_VIDEO_MEDIA is not set | ||
| 855 | |||
| 856 | # | ||
| 857 | # Multimedia drivers | ||
| 858 | # | ||
| 738 | # CONFIG_DAB is not set | 859 | # CONFIG_DAB is not set |
| 739 | 860 | ||
| 740 | # | 861 | # |
| @@ -745,6 +866,7 @@ CONFIG_HTC_PASIC3=y | |||
| 745 | CONFIG_FB=y | 866 | CONFIG_FB=y |
| 746 | # CONFIG_FIRMWARE_EDID is not set | 867 | # CONFIG_FIRMWARE_EDID is not set |
| 747 | # CONFIG_FB_DDC is not set | 868 | # CONFIG_FB_DDC is not set |
| 869 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 748 | CONFIG_FB_CFB_FILLRECT=y | 870 | CONFIG_FB_CFB_FILLRECT=y |
| 749 | CONFIG_FB_CFB_COPYAREA=y | 871 | CONFIG_FB_CFB_COPYAREA=y |
| 750 | CONFIG_FB_CFB_IMAGEBLIT=y | 872 | CONFIG_FB_CFB_IMAGEBLIT=y |
| @@ -752,8 +874,8 @@ CONFIG_FB_CFB_IMAGEBLIT=y | |||
| 752 | # CONFIG_FB_SYS_FILLRECT is not set | 874 | # CONFIG_FB_SYS_FILLRECT is not set |
| 753 | # CONFIG_FB_SYS_COPYAREA is not set | 875 | # CONFIG_FB_SYS_COPYAREA is not set |
| 754 | # CONFIG_FB_SYS_IMAGEBLIT is not set | 876 | # CONFIG_FB_SYS_IMAGEBLIT is not set |
| 877 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 755 | # CONFIG_FB_SYS_FOPS is not set | 878 | # CONFIG_FB_SYS_FOPS is not set |
| 756 | CONFIG_FB_DEFERRED_IO=y | ||
| 757 | # CONFIG_FB_SVGALIB is not set | 879 | # CONFIG_FB_SVGALIB is not set |
| 758 | # CONFIG_FB_MACMODES is not set | 880 | # CONFIG_FB_MACMODES is not set |
| 759 | # CONFIG_FB_BACKLIGHT is not set | 881 | # CONFIG_FB_BACKLIGHT is not set |
| @@ -765,13 +887,21 @@ CONFIG_FB_DEFERRED_IO=y | |||
| 765 | # | 887 | # |
| 766 | # CONFIG_FB_S1D13XXX is not set | 888 | # CONFIG_FB_S1D13XXX is not set |
| 767 | CONFIG_FB_PXA=y | 889 | CONFIG_FB_PXA=y |
| 890 | CONFIG_FB_PXA_OVERLAY=y | ||
| 891 | # CONFIG_FB_PXA_SMARTPANEL is not set | ||
| 768 | # CONFIG_FB_PXA_PARAMETERS is not set | 892 | # CONFIG_FB_PXA_PARAMETERS is not set |
| 769 | # CONFIG_FB_MBX is not set | 893 | # CONFIG_FB_MBX is not set |
| 894 | # CONFIG_FB_W100 is not set | ||
| 770 | # CONFIG_FB_VIRTUAL is not set | 895 | # CONFIG_FB_VIRTUAL is not set |
| 896 | # CONFIG_FB_METRONOME is not set | ||
| 897 | # CONFIG_FB_MB862XX is not set | ||
| 771 | CONFIG_BACKLIGHT_LCD_SUPPORT=y | 898 | CONFIG_BACKLIGHT_LCD_SUPPORT=y |
| 772 | CONFIG_LCD_CLASS_DEVICE=y | 899 | CONFIG_LCD_CLASS_DEVICE=y |
| 900 | # CONFIG_LCD_ILI9320 is not set | ||
| 901 | # CONFIG_LCD_PLATFORM is not set | ||
| 773 | CONFIG_BACKLIGHT_CLASS_DEVICE=y | 902 | CONFIG_BACKLIGHT_CLASS_DEVICE=y |
| 774 | CONFIG_BACKLIGHT_CORGI=y | 903 | # CONFIG_BACKLIGHT_GENERIC is not set |
| 904 | CONFIG_BACKLIGHT_PWM=y | ||
| 775 | 905 | ||
| 776 | # | 906 | # |
| 777 | # Display device support | 907 | # Display device support |
| @@ -802,15 +932,8 @@ CONFIG_FONT_MINI_4x6=y | |||
| 802 | # CONFIG_FONT_SUN12x22 is not set | 932 | # CONFIG_FONT_SUN12x22 is not set |
| 803 | # CONFIG_FONT_10x18 is not set | 933 | # CONFIG_FONT_10x18 is not set |
| 804 | # CONFIG_LOGO is not set | 934 | # CONFIG_LOGO is not set |
| 805 | |||
| 806 | # | ||
| 807 | # Sound | ||
| 808 | # | ||
| 809 | CONFIG_SOUND=y | 935 | CONFIG_SOUND=y |
| 810 | 936 | CONFIG_SOUND_OSS_CORE=y | |
| 811 | # | ||
| 812 | # Advanced Linux Sound Architecture | ||
| 813 | # | ||
| 814 | CONFIG_SND=m | 937 | CONFIG_SND=m |
| 815 | CONFIG_SND_TIMER=m | 938 | CONFIG_SND_TIMER=m |
| 816 | CONFIG_SND_PCM=m | 939 | CONFIG_SND_PCM=m |
| @@ -824,53 +947,185 @@ CONFIG_SND_SUPPORT_OLD_API=y | |||
| 824 | CONFIG_SND_VERBOSE_PROCFS=y | 947 | CONFIG_SND_VERBOSE_PROCFS=y |
| 825 | # CONFIG_SND_VERBOSE_PRINTK is not set | 948 | # CONFIG_SND_VERBOSE_PRINTK is not set |
| 826 | # CONFIG_SND_DEBUG is not set | 949 | # CONFIG_SND_DEBUG is not set |
| 827 | 950 | CONFIG_SND_DRIVERS=y | |
| 828 | # | ||
| 829 | # Generic devices | ||
| 830 | # | ||
| 831 | # CONFIG_SND_DUMMY is not set | 951 | # CONFIG_SND_DUMMY is not set |
| 832 | # CONFIG_SND_MTPAV is not set | 952 | # CONFIG_SND_MTPAV is not set |
| 833 | # CONFIG_SND_SERIAL_U16550 is not set | 953 | # CONFIG_SND_SERIAL_U16550 is not set |
| 834 | # CONFIG_SND_MPU401 is not set | 954 | # CONFIG_SND_MPU401 is not set |
| 835 | 955 | # CONFIG_SND_ARM is not set | |
| 836 | # | 956 | CONFIG_SND_PXA2XX_LIB=m |
| 837 | # ALSA ARM devices | 957 | # CONFIG_SND_USB is not set |
| 838 | # | ||
| 839 | # CONFIG_SND_PXA2XX_AC97 is not set | ||
| 840 | |||
| 841 | # | ||
| 842 | # System on Chip audio support | ||
| 843 | # | ||
| 844 | CONFIG_SND_SOC=m | 958 | CONFIG_SND_SOC=m |
| 845 | CONFIG_SND_PXA2XX_SOC=m | 959 | CONFIG_SND_PXA2XX_SOC=m |
| 846 | 960 | CONFIG_SND_SOC_I2C_AND_SPI=m | |
| 847 | # | 961 | # CONFIG_SND_SOC_ALL_CODECS is not set |
| 848 | # SoC Audio support for SuperH | ||
| 849 | # | ||
| 850 | |||
| 851 | # | ||
| 852 | # Open Sound System | ||
| 853 | # | ||
| 854 | # CONFIG_SOUND_PRIME is not set | 962 | # CONFIG_SOUND_PRIME is not set |
| 855 | # CONFIG_HID_SUPPORT is not set | 963 | # CONFIG_HID_SUPPORT is not set |
| 856 | CONFIG_HID=m | 964 | CONFIG_HID=m |
| 857 | # CONFIG_USB_SUPPORT is not set | 965 | CONFIG_USB_SUPPORT=y |
| 966 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 967 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 968 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 969 | CONFIG_USB=y | ||
| 970 | # CONFIG_USB_DEBUG is not set | ||
| 971 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 972 | |||
| 973 | # | ||
| 974 | # Miscellaneous USB options | ||
| 975 | # | ||
| 976 | # CONFIG_USB_DEVICEFS is not set | ||
| 977 | # CONFIG_USB_DEVICE_CLASS is not set | ||
| 978 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 979 | # CONFIG_USB_SUSPEND is not set | ||
| 980 | # CONFIG_USB_OTG is not set | ||
| 981 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 982 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
| 983 | CONFIG_USB_MON=m | ||
| 984 | # CONFIG_USB_WUSB is not set | ||
| 985 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 986 | |||
| 987 | # | ||
| 988 | # USB Host Controller Drivers | ||
| 989 | # | ||
| 990 | # CONFIG_USB_C67X00_HCD is not set | ||
| 991 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 992 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 993 | CONFIG_USB_OHCI_HCD=y | ||
| 994 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | ||
| 995 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | ||
| 996 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | ||
| 997 | # CONFIG_USB_SL811_HCD is not set | ||
| 998 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 999 | # CONFIG_USB_HWA_HCD is not set | ||
| 1000 | # CONFIG_USB_MUSB_HDRC is not set | ||
| 1001 | # CONFIG_USB_GADGET_MUSB_HDRC is not set | ||
| 1002 | |||
| 1003 | # | ||
| 1004 | # USB Device Class drivers | ||
| 1005 | # | ||
| 1006 | # CONFIG_USB_ACM is not set | ||
| 1007 | # CONFIG_USB_PRINTER is not set | ||
| 1008 | # CONFIG_USB_WDM is not set | ||
| 1009 | # CONFIG_USB_TMC is not set | ||
| 1010 | |||
| 1011 | # | ||
| 1012 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; | ||
| 1013 | # | ||
| 1014 | |||
| 1015 | # | ||
| 1016 | # see USB_STORAGE Help for more information | ||
| 1017 | # | ||
| 1018 | # CONFIG_USB_LIBUSUAL is not set | ||
| 1019 | |||
| 1020 | # | ||
| 1021 | # USB Imaging devices | ||
| 1022 | # | ||
| 1023 | # CONFIG_USB_MDC800 is not set | ||
| 1024 | |||
| 1025 | # | ||
| 1026 | # USB port drivers | ||
| 1027 | # | ||
| 1028 | # CONFIG_USB_SERIAL is not set | ||
| 1029 | |||
| 1030 | # | ||
| 1031 | # USB Miscellaneous drivers | ||
| 1032 | # | ||
| 1033 | # CONFIG_USB_EMI62 is not set | ||
| 1034 | # CONFIG_USB_EMI26 is not set | ||
| 1035 | # CONFIG_USB_ADUTUX is not set | ||
| 1036 | # CONFIG_USB_SEVSEG is not set | ||
| 1037 | # CONFIG_USB_RIO500 is not set | ||
| 1038 | # CONFIG_USB_LEGOTOWER is not set | ||
| 1039 | # CONFIG_USB_LCD is not set | ||
| 1040 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 1041 | # CONFIG_USB_LED is not set | ||
| 1042 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 1043 | # CONFIG_USB_CYTHERM is not set | ||
| 1044 | # CONFIG_USB_PHIDGET is not set | ||
| 1045 | # CONFIG_USB_IDMOUSE is not set | ||
| 1046 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 1047 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 1048 | # CONFIG_USB_LD is not set | ||
| 1049 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 1050 | # CONFIG_USB_IOWARRIOR is not set | ||
| 1051 | # CONFIG_USB_ISIGHTFW is not set | ||
| 1052 | # CONFIG_USB_VST is not set | ||
| 1053 | CONFIG_USB_GADGET=y | ||
| 1054 | # CONFIG_USB_GADGET_DEBUG is not set | ||
| 1055 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
| 1056 | CONFIG_USB_GADGET_VBUS_DRAW=500 | ||
| 1057 | CONFIG_USB_GADGET_SELECTED=y | ||
| 1058 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 1059 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 1060 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 1061 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 1062 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 1063 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 1064 | CONFIG_USB_GADGET_PXA27X=y | ||
| 1065 | CONFIG_USB_PXA27X=y | ||
| 1066 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 1067 | # CONFIG_USB_GADGET_IMX is not set | ||
| 1068 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 1069 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 1070 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 1071 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 1072 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1073 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1074 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 1075 | # CONFIG_USB_GADGET_DUALSPEED is not set | ||
| 1076 | # CONFIG_USB_ZERO is not set | ||
| 1077 | CONFIG_USB_ETH=m | ||
| 1078 | # CONFIG_USB_ETH_RNDIS is not set | ||
| 1079 | CONFIG_USB_GADGETFS=m | ||
| 1080 | CONFIG_USB_FILE_STORAGE=m | ||
| 1081 | # CONFIG_USB_FILE_STORAGE_TEST is not set | ||
| 1082 | CONFIG_USB_G_SERIAL=m | ||
| 1083 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 1084 | # CONFIG_USB_G_PRINTER is not set | ||
| 1085 | CONFIG_USB_CDC_COMPOSITE=m | ||
| 1086 | |||
| 1087 | # | ||
| 1088 | # OTG and related infrastructure | ||
| 1089 | # | ||
| 1090 | CONFIG_USB_OTG_UTILS=y | ||
| 1091 | CONFIG_USB_GPIO_VBUS=y | ||
| 858 | CONFIG_MMC=y | 1092 | CONFIG_MMC=y |
| 859 | # CONFIG_MMC_DEBUG is not set | 1093 | # CONFIG_MMC_DEBUG is not set |
| 860 | # CONFIG_MMC_UNSAFE_RESUME is not set | 1094 | # CONFIG_MMC_UNSAFE_RESUME is not set |
| 861 | 1095 | ||
| 862 | # | 1096 | # |
| 863 | # MMC/SD Card Drivers | 1097 | # MMC/SD/SDIO Card Drivers |
| 864 | # | 1098 | # |
| 865 | CONFIG_MMC_BLOCK=y | 1099 | CONFIG_MMC_BLOCK=y |
| 866 | CONFIG_MMC_BLOCK_BOUNCE=y | 1100 | CONFIG_MMC_BLOCK_BOUNCE=y |
| 867 | CONFIG_SDIO_UART=m | 1101 | CONFIG_SDIO_UART=m |
| 1102 | # CONFIG_MMC_TEST is not set | ||
| 868 | 1103 | ||
| 869 | # | 1104 | # |
| 870 | # MMC/SD Host Controller Drivers | 1105 | # MMC/SD/SDIO Host Controller Drivers |
| 871 | # | 1106 | # |
| 872 | CONFIG_MMC_PXA=y | 1107 | CONFIG_MMC_PXA=y |
| 1108 | # CONFIG_MMC_SDHCI is not set | ||
| 1109 | # CONFIG_MEMSTICK is not set | ||
| 1110 | # CONFIG_ACCESSIBILITY is not set | ||
| 873 | CONFIG_NEW_LEDS=y | 1111 | CONFIG_NEW_LEDS=y |
| 1112 | CONFIG_LEDS_CLASS=y | ||
| 1113 | |||
| 1114 | # | ||
| 1115 | # LED drivers | ||
| 1116 | # | ||
| 1117 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1118 | CONFIG_LEDS_GPIO=y | ||
| 1119 | # CONFIG_LEDS_PCA955X is not set | ||
| 1120 | |||
| 1121 | # | ||
| 1122 | # LED Triggers | ||
| 1123 | # | ||
| 1124 | CONFIG_LEDS_TRIGGERS=y | ||
| 1125 | # CONFIG_LEDS_TRIGGER_TIMER is not set | ||
| 1126 | # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set | ||
| 1127 | CONFIG_LEDS_TRIGGER_BACKLIGHT=y | ||
| 1128 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | ||
| 874 | CONFIG_RTC_LIB=y | 1129 | CONFIG_RTC_LIB=y |
| 875 | CONFIG_RTC_CLASS=y | 1130 | CONFIG_RTC_CLASS=y |
| 876 | CONFIG_RTC_HCTOSYS=y | 1131 | CONFIG_RTC_HCTOSYS=y |
| @@ -899,6 +1154,9 @@ CONFIG_RTC_INTF_DEV=y | |||
| 899 | # CONFIG_RTC_DRV_PCF8563 is not set | 1154 | # CONFIG_RTC_DRV_PCF8563 is not set |
| 900 | # CONFIG_RTC_DRV_PCF8583 is not set | 1155 | # CONFIG_RTC_DRV_PCF8583 is not set |
| 901 | # CONFIG_RTC_DRV_M41T80 is not set | 1156 | # CONFIG_RTC_DRV_M41T80 is not set |
| 1157 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1158 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1159 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 902 | 1160 | ||
| 903 | # | 1161 | # |
| 904 | # SPI RTC drivers | 1162 | # SPI RTC drivers |
| @@ -908,17 +1166,26 @@ CONFIG_RTC_INTF_DEV=y | |||
| 908 | # Platform RTC drivers | 1166 | # Platform RTC drivers |
| 909 | # | 1167 | # |
| 910 | # CONFIG_RTC_DRV_CMOS is not set | 1168 | # CONFIG_RTC_DRV_CMOS is not set |
| 1169 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1170 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 911 | # CONFIG_RTC_DRV_DS1553 is not set | 1171 | # CONFIG_RTC_DRV_DS1553 is not set |
| 912 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 913 | # CONFIG_RTC_DRV_DS1742 is not set | 1172 | # CONFIG_RTC_DRV_DS1742 is not set |
| 1173 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 914 | # CONFIG_RTC_DRV_M48T86 is not set | 1174 | # CONFIG_RTC_DRV_M48T86 is not set |
| 1175 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 915 | # CONFIG_RTC_DRV_M48T59 is not set | 1176 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1177 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 916 | # CONFIG_RTC_DRV_V3020 is not set | 1178 | # CONFIG_RTC_DRV_V3020 is not set |
| 917 | 1179 | ||
| 918 | # | 1180 | # |
| 919 | # on-CPU RTC drivers | 1181 | # on-CPU RTC drivers |
| 920 | # | 1182 | # |
| 921 | CONFIG_RTC_DRV_SA1100=y | 1183 | CONFIG_RTC_DRV_SA1100=y |
| 1184 | # CONFIG_RTC_DRV_PXA is not set | ||
| 1185 | # CONFIG_DMADEVICES is not set | ||
| 1186 | # CONFIG_REGULATOR is not set | ||
| 1187 | # CONFIG_UIO is not set | ||
| 1188 | # CONFIG_STAGING is not set | ||
| 922 | 1189 | ||
| 923 | # | 1190 | # |
| 924 | # File systems | 1191 | # File systems |
| @@ -927,19 +1194,18 @@ CONFIG_EXT2_FS=y | |||
| 927 | # CONFIG_EXT2_FS_XATTR is not set | 1194 | # CONFIG_EXT2_FS_XATTR is not set |
| 928 | # CONFIG_EXT2_FS_XIP is not set | 1195 | # CONFIG_EXT2_FS_XIP is not set |
| 929 | # CONFIG_EXT3_FS is not set | 1196 | # CONFIG_EXT3_FS is not set |
| 930 | # CONFIG_EXT4DEV_FS is not set | 1197 | # CONFIG_EXT4_FS is not set |
| 931 | # CONFIG_REISERFS_FS is not set | 1198 | # CONFIG_REISERFS_FS is not set |
| 932 | # CONFIG_JFS_FS is not set | 1199 | # CONFIG_JFS_FS is not set |
| 933 | # CONFIG_FS_POSIX_ACL is not set | 1200 | # CONFIG_FS_POSIX_ACL is not set |
| 1201 | CONFIG_FILE_LOCKING=y | ||
| 934 | # CONFIG_XFS_FS is not set | 1202 | # CONFIG_XFS_FS is not set |
| 935 | # CONFIG_GFS2_FS is not set | ||
| 936 | # CONFIG_OCFS2_FS is not set | 1203 | # CONFIG_OCFS2_FS is not set |
| 937 | # CONFIG_MINIX_FS is not set | 1204 | # CONFIG_BTRFS_FS is not set |
| 938 | # CONFIG_ROMFS_FS is not set | 1205 | CONFIG_DNOTIFY=y |
| 939 | CONFIG_INOTIFY=y | 1206 | CONFIG_INOTIFY=y |
| 940 | CONFIG_INOTIFY_USER=y | 1207 | CONFIG_INOTIFY_USER=y |
| 941 | # CONFIG_QUOTA is not set | 1208 | # CONFIG_QUOTA is not set |
| 942 | CONFIG_DNOTIFY=y | ||
| 943 | # CONFIG_AUTOFS_FS is not set | 1209 | # CONFIG_AUTOFS_FS is not set |
| 944 | # CONFIG_AUTOFS4_FS is not set | 1210 | # CONFIG_AUTOFS4_FS is not set |
| 945 | # CONFIG_FUSE_FS is not set | 1211 | # CONFIG_FUSE_FS is not set |
| @@ -965,15 +1231,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | |||
| 965 | # | 1231 | # |
| 966 | CONFIG_PROC_FS=y | 1232 | CONFIG_PROC_FS=y |
| 967 | CONFIG_PROC_SYSCTL=y | 1233 | CONFIG_PROC_SYSCTL=y |
| 1234 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 968 | CONFIG_SYSFS=y | 1235 | CONFIG_SYSFS=y |
| 969 | CONFIG_TMPFS=y | 1236 | CONFIG_TMPFS=y |
| 970 | # CONFIG_TMPFS_POSIX_ACL is not set | 1237 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 971 | # CONFIG_HUGETLB_PAGE is not set | 1238 | # CONFIG_HUGETLB_PAGE is not set |
| 972 | # CONFIG_CONFIGFS_FS is not set | 1239 | # CONFIG_CONFIGFS_FS is not set |
| 973 | 1240 | CONFIG_MISC_FILESYSTEMS=y | |
| 974 | # | ||
| 975 | # Miscellaneous filesystems | ||
| 976 | # | ||
| 977 | # CONFIG_ADFS_FS is not set | 1241 | # CONFIG_ADFS_FS is not set |
| 978 | # CONFIG_AFFS_FS is not set | 1242 | # CONFIG_AFFS_FS is not set |
| 979 | # CONFIG_HFS_FS is not set | 1243 | # CONFIG_HFS_FS is not set |
| @@ -997,9 +1261,13 @@ CONFIG_JFFS2_CMODE_PRIORITY=y | |||
| 997 | # CONFIG_JFFS2_CMODE_SIZE is not set | 1261 | # CONFIG_JFFS2_CMODE_SIZE is not set |
| 998 | # CONFIG_JFFS2_CMODE_FAVOURLZO is not set | 1262 | # CONFIG_JFFS2_CMODE_FAVOURLZO is not set |
| 999 | # CONFIG_CRAMFS is not set | 1263 | # CONFIG_CRAMFS is not set |
| 1264 | # CONFIG_SQUASHFS is not set | ||
| 1000 | # CONFIG_VXFS_FS is not set | 1265 | # CONFIG_VXFS_FS is not set |
| 1266 | # CONFIG_MINIX_FS is not set | ||
| 1267 | # CONFIG_OMFS_FS is not set | ||
| 1001 | # CONFIG_HPFS_FS is not set | 1268 | # CONFIG_HPFS_FS is not set |
| 1002 | # CONFIG_QNX4FS_FS is not set | 1269 | # CONFIG_QNX4FS_FS is not set |
| 1270 | # CONFIG_ROMFS_FS is not set | ||
| 1003 | # CONFIG_SYSV_FS is not set | 1271 | # CONFIG_SYSV_FS is not set |
| 1004 | # CONFIG_UFS_FS is not set | 1272 | # CONFIG_UFS_FS is not set |
| 1005 | CONFIG_NETWORK_FILESYSTEMS=y | 1273 | CONFIG_NETWORK_FILESYSTEMS=y |
| @@ -1007,14 +1275,13 @@ CONFIG_NFS_FS=y | |||
| 1007 | CONFIG_NFS_V3=y | 1275 | CONFIG_NFS_V3=y |
| 1008 | # CONFIG_NFS_V3_ACL is not set | 1276 | # CONFIG_NFS_V3_ACL is not set |
| 1009 | # CONFIG_NFS_V4 is not set | 1277 | # CONFIG_NFS_V4 is not set |
| 1010 | # CONFIG_NFS_DIRECTIO is not set | ||
| 1011 | # CONFIG_NFSD is not set | ||
| 1012 | CONFIG_ROOT_NFS=y | 1278 | CONFIG_ROOT_NFS=y |
| 1279 | # CONFIG_NFSD is not set | ||
| 1013 | CONFIG_LOCKD=y | 1280 | CONFIG_LOCKD=y |
| 1014 | CONFIG_LOCKD_V4=y | 1281 | CONFIG_LOCKD_V4=y |
| 1015 | CONFIG_NFS_COMMON=y | 1282 | CONFIG_NFS_COMMON=y |
| 1016 | CONFIG_SUNRPC=y | 1283 | CONFIG_SUNRPC=y |
| 1017 | # CONFIG_SUNRPC_BIND34 is not set | 1284 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 1018 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 1285 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 1019 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1286 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1020 | # CONFIG_SMB_FS is not set | 1287 | # CONFIG_SMB_FS is not set |
| @@ -1076,6 +1343,7 @@ CONFIG_NLS_UTF8=y | |||
| 1076 | CONFIG_PRINTK_TIME=y | 1343 | CONFIG_PRINTK_TIME=y |
| 1077 | CONFIG_ENABLE_WARN_DEPRECATED=y | 1344 | CONFIG_ENABLE_WARN_DEPRECATED=y |
| 1078 | CONFIG_ENABLE_MUST_CHECK=y | 1345 | CONFIG_ENABLE_MUST_CHECK=y |
| 1346 | CONFIG_FRAME_WARN=1024 | ||
| 1079 | # CONFIG_MAGIC_SYSRQ is not set | 1347 | # CONFIG_MAGIC_SYSRQ is not set |
| 1080 | # CONFIG_UNUSED_SYMBOLS is not set | 1348 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1081 | # CONFIG_DEBUG_FS is not set | 1349 | # CONFIG_DEBUG_FS is not set |
| @@ -1083,15 +1351,18 @@ CONFIG_ENABLE_MUST_CHECK=y | |||
| 1083 | CONFIG_DEBUG_KERNEL=y | 1351 | CONFIG_DEBUG_KERNEL=y |
| 1084 | # CONFIG_DEBUG_SHIRQ is not set | 1352 | # CONFIG_DEBUG_SHIRQ is not set |
| 1085 | CONFIG_DETECT_SOFTLOCKUP=y | 1353 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1354 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1355 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1086 | # CONFIG_SCHED_DEBUG is not set | 1356 | # CONFIG_SCHED_DEBUG is not set |
| 1087 | # CONFIG_SCHEDSTATS is not set | 1357 | # CONFIG_SCHEDSTATS is not set |
| 1088 | CONFIG_TIMER_STATS=y | 1358 | CONFIG_TIMER_STATS=y |
| 1359 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1089 | # CONFIG_DEBUG_SLAB is not set | 1360 | # CONFIG_DEBUG_SLAB is not set |
| 1090 | CONFIG_DEBUG_PREEMPT=y | 1361 | # CONFIG_DEBUG_PREEMPT is not set |
| 1091 | # CONFIG_DEBUG_RT_MUTEXES is not set | 1362 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| 1092 | # CONFIG_RT_MUTEX_TESTER is not set | 1363 | # CONFIG_RT_MUTEX_TESTER is not set |
| 1093 | # CONFIG_DEBUG_SPINLOCK is not set | 1364 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1094 | CONFIG_DEBUG_MUTEXES=y | 1365 | # CONFIG_DEBUG_MUTEXES is not set |
| 1095 | # CONFIG_DEBUG_LOCK_ALLOC is not set | 1366 | # CONFIG_DEBUG_LOCK_ALLOC is not set |
| 1096 | # CONFIG_PROVE_LOCKING is not set | 1367 | # CONFIG_PROVE_LOCKING is not set |
| 1097 | # CONFIG_LOCK_STAT is not set | 1368 | # CONFIG_LOCK_STAT is not set |
| @@ -1100,17 +1371,41 @@ CONFIG_DEBUG_MUTEXES=y | |||
| 1100 | # CONFIG_DEBUG_KOBJECT is not set | 1371 | # CONFIG_DEBUG_KOBJECT is not set |
| 1101 | CONFIG_DEBUG_BUGVERBOSE=y | 1372 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1102 | # CONFIG_DEBUG_INFO is not set | 1373 | # CONFIG_DEBUG_INFO is not set |
| 1103 | CONFIG_DEBUG_VM=y | 1374 | # CONFIG_DEBUG_VM is not set |
| 1375 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1376 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1104 | # CONFIG_DEBUG_LIST is not set | 1377 | # CONFIG_DEBUG_LIST is not set |
| 1105 | # CONFIG_DEBUG_SG is not set | 1378 | # CONFIG_DEBUG_SG is not set |
| 1379 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1106 | CONFIG_FRAME_POINTER=y | 1380 | CONFIG_FRAME_POINTER=y |
| 1107 | CONFIG_FORCED_INLINING=y | ||
| 1108 | # CONFIG_BOOT_PRINTK_DELAY is not set | 1381 | # CONFIG_BOOT_PRINTK_DELAY is not set |
| 1109 | # CONFIG_RCU_TORTURE_TEST is not set | 1382 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1383 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1384 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1385 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1110 | # CONFIG_FAULT_INJECTION is not set | 1386 | # CONFIG_FAULT_INJECTION is not set |
| 1387 | # CONFIG_LATENCYTOP is not set | ||
| 1388 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1389 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1390 | |||
| 1391 | # | ||
| 1392 | # Tracers | ||
| 1393 | # | ||
| 1394 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1395 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1396 | # CONFIG_PREEMPT_TRACER is not set | ||
| 1397 | # CONFIG_SCHED_TRACER is not set | ||
| 1398 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1399 | # CONFIG_BOOT_TRACER is not set | ||
| 1400 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1401 | # CONFIG_STACK_TRACER is not set | ||
| 1402 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1111 | # CONFIG_SAMPLES is not set | 1403 | # CONFIG_SAMPLES is not set |
| 1404 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1405 | # CONFIG_KGDB is not set | ||
| 1112 | CONFIG_DEBUG_USER=y | 1406 | CONFIG_DEBUG_USER=y |
| 1113 | CONFIG_DEBUG_ERRORS=y | 1407 | CONFIG_DEBUG_ERRORS=y |
| 1408 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1114 | CONFIG_DEBUG_LL=y | 1409 | CONFIG_DEBUG_LL=y |
| 1115 | # CONFIG_DEBUG_ICEDCC is not set | 1410 | # CONFIG_DEBUG_ICEDCC is not set |
| 1116 | 1411 | ||
| @@ -1119,55 +1414,110 @@ CONFIG_DEBUG_LL=y | |||
| 1119 | # | 1414 | # |
| 1120 | # CONFIG_KEYS is not set | 1415 | # CONFIG_KEYS is not set |
| 1121 | # CONFIG_SECURITY is not set | 1416 | # CONFIG_SECURITY is not set |
| 1417 | # CONFIG_SECURITYFS is not set | ||
| 1122 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | 1418 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1123 | CONFIG_CRYPTO=y | 1419 | CONFIG_CRYPTO=y |
| 1420 | |||
| 1421 | # | ||
| 1422 | # Crypto core or helper | ||
| 1423 | # | ||
| 1424 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1124 | CONFIG_CRYPTO_ALGAPI=m | 1425 | CONFIG_CRYPTO_ALGAPI=m |
| 1426 | CONFIG_CRYPTO_ALGAPI2=m | ||
| 1427 | CONFIG_CRYPTO_AEAD2=m | ||
| 1125 | CONFIG_CRYPTO_BLKCIPHER=m | 1428 | CONFIG_CRYPTO_BLKCIPHER=m |
| 1429 | CONFIG_CRYPTO_BLKCIPHER2=m | ||
| 1430 | CONFIG_CRYPTO_HASH=m | ||
| 1431 | CONFIG_CRYPTO_HASH2=m | ||
| 1432 | CONFIG_CRYPTO_RNG2=m | ||
| 1126 | CONFIG_CRYPTO_MANAGER=m | 1433 | CONFIG_CRYPTO_MANAGER=m |
| 1434 | CONFIG_CRYPTO_MANAGER2=m | ||
| 1435 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1436 | # CONFIG_CRYPTO_NULL is not set | ||
| 1437 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1438 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1439 | # CONFIG_CRYPTO_TEST is not set | ||
| 1440 | |||
| 1441 | # | ||
| 1442 | # Authenticated Encryption with Associated Data | ||
| 1443 | # | ||
| 1444 | # CONFIG_CRYPTO_CCM is not set | ||
| 1445 | # CONFIG_CRYPTO_GCM is not set | ||
| 1446 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1447 | |||
| 1448 | # | ||
| 1449 | # Block modes | ||
| 1450 | # | ||
| 1451 | # CONFIG_CRYPTO_CBC is not set | ||
| 1452 | # CONFIG_CRYPTO_CTR is not set | ||
| 1453 | # CONFIG_CRYPTO_CTS is not set | ||
| 1454 | CONFIG_CRYPTO_ECB=m | ||
| 1455 | # CONFIG_CRYPTO_LRW is not set | ||
| 1456 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1457 | # CONFIG_CRYPTO_XTS is not set | ||
| 1458 | |||
| 1459 | # | ||
| 1460 | # Hash modes | ||
| 1461 | # | ||
| 1127 | # CONFIG_CRYPTO_HMAC is not set | 1462 | # CONFIG_CRYPTO_HMAC is not set |
| 1128 | # CONFIG_CRYPTO_XCBC is not set | 1463 | # CONFIG_CRYPTO_XCBC is not set |
| 1129 | # CONFIG_CRYPTO_NULL is not set | 1464 | |
| 1465 | # | ||
| 1466 | # Digest | ||
| 1467 | # | ||
| 1468 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1130 | # CONFIG_CRYPTO_MD4 is not set | 1469 | # CONFIG_CRYPTO_MD4 is not set |
| 1131 | # CONFIG_CRYPTO_MD5 is not set | 1470 | # CONFIG_CRYPTO_MD5 is not set |
| 1471 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1472 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1473 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1474 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1475 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1132 | CONFIG_CRYPTO_SHA1=m | 1476 | CONFIG_CRYPTO_SHA1=m |
| 1133 | # CONFIG_CRYPTO_SHA256 is not set | 1477 | # CONFIG_CRYPTO_SHA256 is not set |
| 1134 | # CONFIG_CRYPTO_SHA512 is not set | 1478 | # CONFIG_CRYPTO_SHA512 is not set |
| 1135 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1136 | # CONFIG_CRYPTO_TGR192 is not set | 1479 | # CONFIG_CRYPTO_TGR192 is not set |
| 1137 | # CONFIG_CRYPTO_GF128MUL is not set | 1480 | # CONFIG_CRYPTO_WP512 is not set |
| 1138 | CONFIG_CRYPTO_ECB=m | 1481 | |
| 1139 | # CONFIG_CRYPTO_CBC is not set | 1482 | # |
| 1140 | CONFIG_CRYPTO_PCBC=m | 1483 | # Ciphers |
| 1141 | # CONFIG_CRYPTO_LRW is not set | 1484 | # |
| 1142 | # CONFIG_CRYPTO_XTS is not set | ||
| 1143 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1144 | # CONFIG_CRYPTO_DES is not set | ||
| 1145 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1146 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1147 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1148 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1149 | # CONFIG_CRYPTO_AES is not set | 1485 | # CONFIG_CRYPTO_AES is not set |
| 1486 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1487 | CONFIG_CRYPTO_ARC4=m | ||
| 1488 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1489 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1150 | # CONFIG_CRYPTO_CAST5 is not set | 1490 | # CONFIG_CRYPTO_CAST5 is not set |
| 1151 | # CONFIG_CRYPTO_CAST6 is not set | 1491 | # CONFIG_CRYPTO_CAST6 is not set |
| 1152 | # CONFIG_CRYPTO_TEA is not set | 1492 | # CONFIG_CRYPTO_DES is not set |
| 1153 | CONFIG_CRYPTO_ARC4=m | 1493 | # CONFIG_CRYPTO_FCRYPT is not set |
| 1154 | # CONFIG_CRYPTO_KHAZAD is not set | 1494 | # CONFIG_CRYPTO_KHAZAD is not set |
| 1155 | # CONFIG_CRYPTO_ANUBIS is not set | 1495 | # CONFIG_CRYPTO_SALSA20 is not set |
| 1156 | # CONFIG_CRYPTO_SEED is not set | 1496 | # CONFIG_CRYPTO_SEED is not set |
| 1497 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1498 | # CONFIG_CRYPTO_TEA is not set | ||
| 1499 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1500 | |||
| 1501 | # | ||
| 1502 | # Compression | ||
| 1503 | # | ||
| 1157 | # CONFIG_CRYPTO_DEFLATE is not set | 1504 | # CONFIG_CRYPTO_DEFLATE is not set |
| 1158 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | 1505 | # CONFIG_CRYPTO_LZO is not set |
| 1159 | # CONFIG_CRYPTO_CRC32C is not set | 1506 | |
| 1160 | # CONFIG_CRYPTO_CAMELLIA is not set | 1507 | # |
| 1161 | # CONFIG_CRYPTO_TEST is not set | 1508 | # Random Number Generation |
| 1162 | # CONFIG_CRYPTO_AUTHENC is not set | 1509 | # |
| 1510 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1163 | # CONFIG_CRYPTO_HW is not set | 1511 | # CONFIG_CRYPTO_HW is not set |
| 1164 | 1512 | ||
| 1165 | # | 1513 | # |
| 1166 | # Library routines | 1514 | # Library routines |
| 1167 | # | 1515 | # |
| 1168 | CONFIG_BITREVERSE=y | 1516 | CONFIG_BITREVERSE=y |
| 1517 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1169 | CONFIG_CRC_CCITT=y | 1518 | CONFIG_CRC_CCITT=y |
| 1170 | # CONFIG_CRC16 is not set | 1519 | # CONFIG_CRC16 is not set |
| 1520 | # CONFIG_CRC_T10DIF is not set | ||
| 1171 | # CONFIG_CRC_ITU_T is not set | 1521 | # CONFIG_CRC_ITU_T is not set |
| 1172 | CONFIG_CRC32=y | 1522 | CONFIG_CRC32=y |
| 1173 | # CONFIG_CRC7 is not set | 1523 | # CONFIG_CRC7 is not set |
diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig index 83c817f31bcc..b0698722e0cb 100644 --- a/arch/arm/configs/mv78xx0_defconfig +++ b/arch/arm/configs/mv78xx0_defconfig | |||
| @@ -165,6 +165,7 @@ CONFIG_ARCH_MV78XX0=y | |||
| 165 | # Marvell MV78xx0 Implementations | 165 | # Marvell MV78xx0 Implementations |
| 166 | # | 166 | # |
| 167 | CONFIG_MACH_DB78X00_BP=y | 167 | CONFIG_MACH_DB78X00_BP=y |
| 168 | CONFIG_MACH_RD78X00_MASA=y | ||
| 168 | 169 | ||
| 169 | # | 170 | # |
| 170 | # Boot options | 171 | # Boot options |
diff --git a/arch/arm/configs/neponset_defconfig b/arch/arm/configs/neponset_defconfig index d81ea219c934..36cd62edd05c 100644 --- a/arch/arm/configs/neponset_defconfig +++ b/arch/arm/configs/neponset_defconfig | |||
| @@ -91,7 +91,6 @@ CONFIG_ASSABET_NEPONSET=y | |||
| 91 | # CONFIG_SA1100_COLLIE is not set | 91 | # CONFIG_SA1100_COLLIE is not set |
| 92 | # CONFIG_SA1100_H3100 is not set | 92 | # CONFIG_SA1100_H3100 is not set |
| 93 | # CONFIG_SA1100_H3600 is not set | 93 | # CONFIG_SA1100_H3600 is not set |
| 94 | # CONFIG_SA1100_H3800 is not set | ||
| 95 | # CONFIG_SA1100_BADGE4 is not set | 94 | # CONFIG_SA1100_BADGE4 is not set |
| 96 | # CONFIG_SA1100_JORNADA720 is not set | 95 | # CONFIG_SA1100_JORNADA720 is not set |
| 97 | # CONFIG_SA1100_HACKKIT is not set | 96 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/configs/omap_3430sdp_defconfig b/arch/arm/configs/omap_3430sdp_defconfig new file mode 100644 index 000000000000..8fb918d9ba65 --- /dev/null +++ b/arch/arm/configs/omap_3430sdp_defconfig | |||
| @@ -0,0 +1,2061 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.29-rc8 | ||
| 4 | # Fri Mar 13 14:17:01 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 26 | CONFIG_OPROFILE_ARMV7=y | ||
| 27 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 28 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 29 | |||
| 30 | # | ||
| 31 | # General setup | ||
| 32 | # | ||
| 33 | CONFIG_EXPERIMENTAL=y | ||
| 34 | CONFIG_BROKEN_ON_SMP=y | ||
| 35 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 36 | CONFIG_LOCALVERSION="" | ||
| 37 | CONFIG_LOCALVERSION_AUTO=y | ||
| 38 | CONFIG_SWAP=y | ||
| 39 | CONFIG_SYSVIPC=y | ||
| 40 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 41 | # CONFIG_POSIX_MQUEUE is not set | ||
| 42 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 43 | # CONFIG_BSD_PROCESS_ACCT_V3 is not set | ||
| 44 | # CONFIG_TASKSTATS is not set | ||
| 45 | # CONFIG_AUDIT is not set | ||
| 46 | |||
| 47 | # | ||
| 48 | # RCU Subsystem | ||
| 49 | # | ||
| 50 | CONFIG_CLASSIC_RCU=y | ||
| 51 | # CONFIG_TREE_RCU is not set | ||
| 52 | # CONFIG_PREEMPT_RCU is not set | ||
| 53 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 54 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 55 | CONFIG_IKCONFIG=y | ||
| 56 | CONFIG_IKCONFIG_PROC=y | ||
| 57 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 58 | CONFIG_GROUP_SCHED=y | ||
| 59 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 60 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 61 | CONFIG_USER_SCHED=y | ||
| 62 | # CONFIG_CGROUP_SCHED is not set | ||
| 63 | # CONFIG_CGROUPS is not set | ||
| 64 | CONFIG_SYSFS_DEPRECATED=y | ||
| 65 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 66 | # CONFIG_RELAY is not set | ||
| 67 | # CONFIG_NAMESPACES is not set | ||
| 68 | CONFIG_BLK_DEV_INITRD=y | ||
| 69 | CONFIG_INITRAMFS_SOURCE="" | ||
| 70 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 71 | CONFIG_SYSCTL=y | ||
| 72 | CONFIG_ANON_INODES=y | ||
| 73 | CONFIG_EMBEDDED=y | ||
| 74 | CONFIG_UID16=y | ||
| 75 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 76 | CONFIG_KALLSYMS=y | ||
| 77 | # CONFIG_KALLSYMS_ALL is not set | ||
| 78 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 79 | CONFIG_HOTPLUG=y | ||
| 80 | CONFIG_PRINTK=y | ||
| 81 | CONFIG_BUG=y | ||
| 82 | # CONFIG_ELF_CORE is not set | ||
| 83 | CONFIG_BASE_FULL=y | ||
| 84 | CONFIG_FUTEX=y | ||
| 85 | CONFIG_EPOLL=y | ||
| 86 | CONFIG_SIGNALFD=y | ||
| 87 | CONFIG_TIMERFD=y | ||
| 88 | CONFIG_EVENTFD=y | ||
| 89 | CONFIG_SHMEM=y | ||
| 90 | CONFIG_AIO=y | ||
| 91 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 92 | CONFIG_SLUB_DEBUG=y | ||
| 93 | # CONFIG_COMPAT_BRK is not set | ||
| 94 | # CONFIG_SLAB is not set | ||
| 95 | CONFIG_SLUB=y | ||
| 96 | # CONFIG_SLOB is not set | ||
| 97 | CONFIG_PROFILING=y | ||
| 98 | CONFIG_TRACEPOINTS=y | ||
| 99 | # CONFIG_MARKERS is not set | ||
| 100 | CONFIG_OPROFILE=y | ||
| 101 | CONFIG_HAVE_OPROFILE=y | ||
| 102 | # CONFIG_KPROBES is not set | ||
| 103 | CONFIG_HAVE_KPROBES=y | ||
| 104 | CONFIG_HAVE_KRETPROBES=y | ||
| 105 | CONFIG_HAVE_CLK=y | ||
| 106 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 107 | CONFIG_SLABINFO=y | ||
| 108 | CONFIG_RT_MUTEXES=y | ||
| 109 | CONFIG_BASE_SMALL=0 | ||
| 110 | CONFIG_MODULES=y | ||
| 111 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 112 | CONFIG_MODULE_UNLOAD=y | ||
| 113 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 114 | CONFIG_MODVERSIONS=y | ||
| 115 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 116 | CONFIG_BLOCK=y | ||
| 117 | CONFIG_LBD=y | ||
| 118 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 119 | # CONFIG_BLK_DEV_BSG is not set | ||
| 120 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 121 | |||
| 122 | # | ||
| 123 | # IO Schedulers | ||
| 124 | # | ||
| 125 | CONFIG_IOSCHED_NOOP=y | ||
| 126 | CONFIG_IOSCHED_AS=y | ||
| 127 | CONFIG_IOSCHED_DEADLINE=y | ||
| 128 | CONFIG_IOSCHED_CFQ=y | ||
| 129 | # CONFIG_DEFAULT_AS is not set | ||
| 130 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 131 | CONFIG_DEFAULT_CFQ=y | ||
| 132 | # CONFIG_DEFAULT_NOOP is not set | ||
| 133 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 134 | CONFIG_FREEZER=y | ||
| 135 | |||
| 136 | # | ||
| 137 | # System Type | ||
| 138 | # | ||
| 139 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 140 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 141 | # CONFIG_ARCH_REALVIEW is not set | ||
| 142 | # CONFIG_ARCH_VERSATILE is not set | ||
| 143 | # CONFIG_ARCH_AT91 is not set | ||
| 144 | # CONFIG_ARCH_CLPS711X is not set | ||
| 145 | # CONFIG_ARCH_EBSA110 is not set | ||
| 146 | # CONFIG_ARCH_EP93XX is not set | ||
| 147 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 148 | # CONFIG_ARCH_NETX is not set | ||
| 149 | # CONFIG_ARCH_H720X is not set | ||
| 150 | # CONFIG_ARCH_IMX is not set | ||
| 151 | # CONFIG_ARCH_IOP13XX is not set | ||
| 152 | # CONFIG_ARCH_IOP32X is not set | ||
| 153 | # CONFIG_ARCH_IOP33X is not set | ||
| 154 | # CONFIG_ARCH_IXP23XX is not set | ||
| 155 | # CONFIG_ARCH_IXP2000 is not set | ||
| 156 | # CONFIG_ARCH_IXP4XX is not set | ||
| 157 | # CONFIG_ARCH_L7200 is not set | ||
| 158 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 159 | # CONFIG_ARCH_KS8695 is not set | ||
| 160 | # CONFIG_ARCH_NS9XXX is not set | ||
| 161 | # CONFIG_ARCH_LOKI is not set | ||
| 162 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 163 | # CONFIG_ARCH_MXC is not set | ||
| 164 | # CONFIG_ARCH_ORION5X is not set | ||
| 165 | # CONFIG_ARCH_PNX4008 is not set | ||
| 166 | # CONFIG_ARCH_PXA is not set | ||
| 167 | # CONFIG_ARCH_RPC is not set | ||
| 168 | # CONFIG_ARCH_SA1100 is not set | ||
| 169 | # CONFIG_ARCH_S3C2410 is not set | ||
| 170 | # CONFIG_ARCH_S3C64XX is not set | ||
| 171 | # CONFIG_ARCH_SHARK is not set | ||
| 172 | # CONFIG_ARCH_LH7A40X is not set | ||
| 173 | # CONFIG_ARCH_DAVINCI is not set | ||
| 174 | CONFIG_ARCH_OMAP=y | ||
| 175 | # CONFIG_ARCH_MSM is not set | ||
| 176 | # CONFIG_ARCH_W90X900 is not set | ||
| 177 | |||
| 178 | # | ||
| 179 | # TI OMAP Implementations | ||
| 180 | # | ||
| 181 | CONFIG_ARCH_OMAP_OTG=y | ||
| 182 | # CONFIG_ARCH_OMAP1 is not set | ||
| 183 | # CONFIG_ARCH_OMAP2 is not set | ||
| 184 | CONFIG_ARCH_OMAP3=y | ||
| 185 | |||
| 186 | # | ||
| 187 | # OMAP Feature Selections | ||
| 188 | # | ||
| 189 | # CONFIG_OMAP_DEBUG_POWERDOMAIN is not set | ||
| 190 | # CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set | ||
| 191 | # CONFIG_OMAP_RESET_CLOCKS is not set | ||
| 192 | CONFIG_OMAP_MUX=y | ||
| 193 | CONFIG_OMAP_MUX_DEBUG=y | ||
| 194 | CONFIG_OMAP_MUX_WARNINGS=y | ||
| 195 | CONFIG_OMAP_MCBSP=y | ||
| 196 | # CONFIG_OMAP_MPU_TIMER is not set | ||
| 197 | CONFIG_OMAP_32K_TIMER=y | ||
| 198 | CONFIG_OMAP_32K_TIMER_HZ=128 | ||
| 199 | CONFIG_OMAP_DM_TIMER=y | ||
| 200 | # CONFIG_OMAP_LL_DEBUG_UART1 is not set | ||
| 201 | # CONFIG_OMAP_LL_DEBUG_UART2 is not set | ||
| 202 | CONFIG_OMAP_LL_DEBUG_UART3=y | ||
| 203 | CONFIG_OMAP_SERIAL_WAKE=y | ||
| 204 | CONFIG_ARCH_OMAP34XX=y | ||
| 205 | CONFIG_ARCH_OMAP3430=y | ||
| 206 | |||
| 207 | # | ||
| 208 | # OMAP Board Type | ||
| 209 | # | ||
| 210 | CONFIG_MACH_OMAP3_BEAGLE=y | ||
| 211 | CONFIG_MACH_OMAP_LDP=y | ||
| 212 | CONFIG_MACH_OVERO=y | ||
| 213 | CONFIG_MACH_OMAP3_PANDORA=y | ||
| 214 | CONFIG_MACH_OMAP_3430SDP=y | ||
| 215 | |||
| 216 | # | ||
| 217 | # Processor Type | ||
| 218 | # | ||
| 219 | CONFIG_CPU_32=y | ||
| 220 | CONFIG_CPU_32v6K=y | ||
| 221 | CONFIG_CPU_V7=y | ||
| 222 | CONFIG_CPU_32v7=y | ||
| 223 | CONFIG_CPU_ABRT_EV7=y | ||
| 224 | CONFIG_CPU_PABRT_IFAR=y | ||
| 225 | CONFIG_CPU_CACHE_V7=y | ||
| 226 | CONFIG_CPU_CACHE_VIPT=y | ||
| 227 | CONFIG_CPU_COPY_V6=y | ||
| 228 | CONFIG_CPU_TLB_V7=y | ||
| 229 | CONFIG_CPU_HAS_ASID=y | ||
| 230 | CONFIG_CPU_CP15=y | ||
| 231 | CONFIG_CPU_CP15_MMU=y | ||
| 232 | |||
| 233 | # | ||
| 234 | # Processor Features | ||
| 235 | # | ||
| 236 | CONFIG_ARM_THUMB=y | ||
| 237 | CONFIG_ARM_THUMBEE=y | ||
| 238 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 239 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 240 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
| 241 | CONFIG_HAS_TLS_REG=y | ||
| 242 | # CONFIG_OUTER_CACHE is not set | ||
| 243 | |||
| 244 | # | ||
| 245 | # Bus support | ||
| 246 | # | ||
| 247 | # CONFIG_PCI_SYSCALL is not set | ||
| 248 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 249 | # CONFIG_PCCARD is not set | ||
| 250 | |||
| 251 | # | ||
| 252 | # Kernel Features | ||
| 253 | # | ||
| 254 | CONFIG_TICK_ONESHOT=y | ||
| 255 | CONFIG_NO_HZ=y | ||
| 256 | CONFIG_HIGH_RES_TIMERS=y | ||
| 257 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 258 | CONFIG_VMSPLIT_3G=y | ||
| 259 | # CONFIG_VMSPLIT_2G is not set | ||
| 260 | # CONFIG_VMSPLIT_1G is not set | ||
| 261 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 262 | # CONFIG_PREEMPT is not set | ||
| 263 | CONFIG_HZ=128 | ||
| 264 | CONFIG_AEABI=y | ||
| 265 | # CONFIG_OABI_COMPAT is not set | ||
| 266 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 267 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 268 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 269 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 270 | CONFIG_FLATMEM_MANUAL=y | ||
| 271 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 272 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 273 | CONFIG_FLATMEM=y | ||
| 274 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 275 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 276 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
| 277 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 278 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 279 | CONFIG_VIRT_TO_BUS=y | ||
| 280 | CONFIG_UNEVICTABLE_LRU=y | ||
| 281 | CONFIG_LEDS=y | ||
| 282 | CONFIG_ALIGNMENT_TRAP=y | ||
| 283 | |||
| 284 | # | ||
| 285 | # Boot options | ||
| 286 | # | ||
| 287 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 288 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 289 | CONFIG_CMDLINE="console=ttyS2,115200 root=/dev/mmcblk0p3 rootwait debug" | ||
| 290 | # CONFIG_XIP_KERNEL is not set | ||
| 291 | CONFIG_KEXEC=y | ||
| 292 | CONFIG_ATAGS_PROC=y | ||
| 293 | |||
| 294 | # | ||
| 295 | # CPU Power Management | ||
| 296 | # | ||
| 297 | CONFIG_CPU_FREQ=y | ||
| 298 | CONFIG_CPU_FREQ_TABLE=y | ||
| 299 | # CONFIG_CPU_FREQ_DEBUG is not set | ||
| 300 | CONFIG_CPU_FREQ_STAT=y | ||
| 301 | CONFIG_CPU_FREQ_STAT_DETAILS=y | ||
| 302 | CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y | ||
| 303 | # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set | ||
| 304 | # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set | ||
| 305 | # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set | ||
| 306 | # CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set | ||
| 307 | CONFIG_CPU_FREQ_GOV_PERFORMANCE=y | ||
| 308 | # CONFIG_CPU_FREQ_GOV_POWERSAVE is not set | ||
| 309 | CONFIG_CPU_FREQ_GOV_USERSPACE=y | ||
| 310 | CONFIG_CPU_FREQ_GOV_ONDEMAND=y | ||
| 311 | # CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set | ||
| 312 | # CONFIG_CPU_IDLE is not set | ||
| 313 | |||
| 314 | # | ||
| 315 | # Floating point emulation | ||
| 316 | # | ||
| 317 | |||
| 318 | # | ||
| 319 | # At least one emulation must be selected | ||
| 320 | # | ||
| 321 | CONFIG_VFP=y | ||
| 322 | CONFIG_VFPv3=y | ||
| 323 | CONFIG_NEON=y | ||
| 324 | |||
| 325 | # | ||
| 326 | # Userspace binary formats | ||
| 327 | # | ||
| 328 | CONFIG_BINFMT_ELF=y | ||
| 329 | CONFIG_HAVE_AOUT=y | ||
| 330 | CONFIG_BINFMT_AOUT=m | ||
| 331 | CONFIG_BINFMT_MISC=y | ||
| 332 | |||
| 333 | # | ||
| 334 | # Power management options | ||
| 335 | # | ||
| 336 | CONFIG_PM=y | ||
| 337 | # CONFIG_PM_DEBUG is not set | ||
| 338 | CONFIG_PM_SLEEP=y | ||
| 339 | CONFIG_SUSPEND=y | ||
| 340 | CONFIG_SUSPEND_FREEZER=y | ||
| 341 | # CONFIG_APM_EMULATION is not set | ||
| 342 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 343 | CONFIG_NET=y | ||
| 344 | |||
| 345 | # | ||
| 346 | # Networking options | ||
| 347 | # | ||
| 348 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 349 | CONFIG_PACKET=y | ||
| 350 | CONFIG_PACKET_MMAP=y | ||
| 351 | CONFIG_UNIX=y | ||
| 352 | CONFIG_XFRM=y | ||
| 353 | # CONFIG_XFRM_USER is not set | ||
| 354 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 355 | # CONFIG_XFRM_MIGRATE is not set | ||
| 356 | # CONFIG_XFRM_STATISTICS is not set | ||
| 357 | CONFIG_NET_KEY=y | ||
| 358 | # CONFIG_NET_KEY_MIGRATE is not set | ||
| 359 | CONFIG_INET=y | ||
| 360 | # CONFIG_IP_MULTICAST is not set | ||
| 361 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 362 | CONFIG_IP_FIB_HASH=y | ||
| 363 | CONFIG_IP_PNP=y | ||
| 364 | CONFIG_IP_PNP_DHCP=y | ||
| 365 | CONFIG_IP_PNP_BOOTP=y | ||
| 366 | CONFIG_IP_PNP_RARP=y | ||
| 367 | # CONFIG_NET_IPIP is not set | ||
| 368 | # CONFIG_NET_IPGRE is not set | ||
| 369 | # CONFIG_ARPD is not set | ||
| 370 | # CONFIG_SYN_COOKIES is not set | ||
| 371 | # CONFIG_INET_AH is not set | ||
| 372 | # CONFIG_INET_ESP is not set | ||
| 373 | # CONFIG_INET_IPCOMP is not set | ||
| 374 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 375 | CONFIG_INET_TUNNEL=m | ||
| 376 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 377 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 378 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 379 | # CONFIG_INET_LRO is not set | ||
| 380 | CONFIG_INET_DIAG=y | ||
| 381 | CONFIG_INET_TCP_DIAG=y | ||
| 382 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 383 | CONFIG_TCP_CONG_CUBIC=y | ||
| 384 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 385 | # CONFIG_TCP_MD5SIG is not set | ||
| 386 | CONFIG_IPV6=m | ||
| 387 | # CONFIG_IPV6_PRIVACY is not set | ||
| 388 | # CONFIG_IPV6_ROUTER_PREF is not set | ||
| 389 | # CONFIG_IPV6_OPTIMISTIC_DAD is not set | ||
| 390 | # CONFIG_INET6_AH is not set | ||
| 391 | # CONFIG_INET6_ESP is not set | ||
| 392 | # CONFIG_INET6_IPCOMP is not set | ||
| 393 | # CONFIG_IPV6_MIP6 is not set | ||
| 394 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 395 | # CONFIG_INET6_TUNNEL is not set | ||
| 396 | CONFIG_INET6_XFRM_MODE_TRANSPORT=m | ||
| 397 | CONFIG_INET6_XFRM_MODE_TUNNEL=m | ||
| 398 | CONFIG_INET6_XFRM_MODE_BEET=m | ||
| 399 | # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set | ||
| 400 | CONFIG_IPV6_SIT=m | ||
| 401 | CONFIG_IPV6_NDISC_NODETYPE=y | ||
| 402 | # CONFIG_IPV6_TUNNEL is not set | ||
| 403 | # CONFIG_IPV6_MULTIPLE_TABLES is not set | ||
| 404 | # CONFIG_IPV6_MROUTE is not set | ||
| 405 | # CONFIG_NETWORK_SECMARK is not set | ||
| 406 | # CONFIG_NETFILTER is not set | ||
| 407 | # CONFIG_IP_DCCP is not set | ||
| 408 | # CONFIG_IP_SCTP is not set | ||
| 409 | # CONFIG_TIPC is not set | ||
| 410 | # CONFIG_ATM is not set | ||
| 411 | # CONFIG_BRIDGE is not set | ||
| 412 | # CONFIG_NET_DSA is not set | ||
| 413 | # CONFIG_VLAN_8021Q is not set | ||
| 414 | # CONFIG_DECNET is not set | ||
| 415 | # CONFIG_LLC2 is not set | ||
| 416 | # CONFIG_IPX is not set | ||
| 417 | # CONFIG_ATALK is not set | ||
| 418 | # CONFIG_X25 is not set | ||
| 419 | # CONFIG_LAPB is not set | ||
| 420 | # CONFIG_ECONET is not set | ||
| 421 | # CONFIG_WAN_ROUTER is not set | ||
| 422 | # CONFIG_NET_SCHED is not set | ||
| 423 | # CONFIG_DCB is not set | ||
| 424 | |||
| 425 | # | ||
| 426 | # Network testing | ||
| 427 | # | ||
| 428 | # CONFIG_NET_PKTGEN is not set | ||
| 429 | # CONFIG_HAMRADIO is not set | ||
| 430 | # CONFIG_CAN is not set | ||
| 431 | # CONFIG_IRDA is not set | ||
| 432 | CONFIG_BT=y | ||
| 433 | CONFIG_BT_L2CAP=y | ||
| 434 | CONFIG_BT_SCO=y | ||
| 435 | CONFIG_BT_RFCOMM=y | ||
| 436 | CONFIG_BT_RFCOMM_TTY=y | ||
| 437 | CONFIG_BT_BNEP=y | ||
| 438 | CONFIG_BT_BNEP_MC_FILTER=y | ||
| 439 | CONFIG_BT_BNEP_PROTO_FILTER=y | ||
| 440 | CONFIG_BT_HIDP=y | ||
| 441 | |||
| 442 | # | ||
| 443 | # Bluetooth device drivers | ||
| 444 | # | ||
| 445 | # CONFIG_BT_HCIBTUSB is not set | ||
| 446 | # CONFIG_BT_HCIBTSDIO is not set | ||
| 447 | CONFIG_BT_HCIUART=y | ||
| 448 | CONFIG_BT_HCIUART_H4=y | ||
| 449 | CONFIG_BT_HCIUART_BCSP=y | ||
| 450 | # CONFIG_BT_HCIUART_LL is not set | ||
| 451 | CONFIG_BT_HCIBCM203X=y | ||
| 452 | CONFIG_BT_HCIBPA10X=y | ||
| 453 | # CONFIG_BT_HCIBFUSB is not set | ||
| 454 | # CONFIG_BT_HCIVHCI is not set | ||
| 455 | # CONFIG_AF_RXRPC is not set | ||
| 456 | # CONFIG_PHONET is not set | ||
| 457 | CONFIG_WIRELESS=y | ||
| 458 | CONFIG_CFG80211=y | ||
| 459 | # CONFIG_CFG80211_REG_DEBUG is not set | ||
| 460 | CONFIG_NL80211=y | ||
| 461 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 462 | CONFIG_WIRELESS_EXT=y | ||
| 463 | CONFIG_WIRELESS_EXT_SYSFS=y | ||
| 464 | CONFIG_LIB80211=y | ||
| 465 | CONFIG_LIB80211_CRYPT_WEP=m | ||
| 466 | CONFIG_LIB80211_CRYPT_CCMP=m | ||
| 467 | CONFIG_LIB80211_CRYPT_TKIP=m | ||
| 468 | CONFIG_MAC80211=y | ||
| 469 | |||
| 470 | # | ||
| 471 | # Rate control algorithm selection | ||
| 472 | # | ||
| 473 | CONFIG_MAC80211_RC_PID=y | ||
| 474 | # CONFIG_MAC80211_RC_MINSTREL is not set | ||
| 475 | CONFIG_MAC80211_RC_DEFAULT_PID=y | ||
| 476 | # CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set | ||
| 477 | CONFIG_MAC80211_RC_DEFAULT="pid" | ||
| 478 | # CONFIG_MAC80211_MESH is not set | ||
| 479 | CONFIG_MAC80211_LEDS=y | ||
| 480 | # CONFIG_MAC80211_DEBUGFS is not set | ||
| 481 | # CONFIG_MAC80211_DEBUG_MENU is not set | ||
| 482 | # CONFIG_WIMAX is not set | ||
| 483 | # CONFIG_RFKILL is not set | ||
| 484 | # CONFIG_NET_9P is not set | ||
| 485 | |||
| 486 | # | ||
| 487 | # Device Drivers | ||
| 488 | # | ||
| 489 | |||
| 490 | # | ||
| 491 | # Generic Driver Options | ||
| 492 | # | ||
| 493 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 494 | CONFIG_STANDALONE=y | ||
| 495 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 496 | CONFIG_FW_LOADER=y | ||
| 497 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 498 | CONFIG_EXTRA_FIRMWARE="" | ||
| 499 | # CONFIG_DEBUG_DRIVER is not set | ||
| 500 | # CONFIG_DEBUG_DEVRES is not set | ||
| 501 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 502 | # CONFIG_CONNECTOR is not set | ||
| 503 | CONFIG_MTD=y | ||
| 504 | # CONFIG_MTD_DEBUG is not set | ||
| 505 | CONFIG_MTD_CONCAT=y | ||
| 506 | CONFIG_MTD_PARTITIONS=y | ||
| 507 | # CONFIG_MTD_TESTS is not set | ||
| 508 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 509 | # CONFIG_MTD_CMDLINE_PARTS is not set | ||
| 510 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 511 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 512 | |||
| 513 | # | ||
| 514 | # User Modules And Translation Layers | ||
| 515 | # | ||
| 516 | CONFIG_MTD_CHAR=y | ||
| 517 | CONFIG_MTD_BLKDEVS=y | ||
| 518 | CONFIG_MTD_BLOCK=y | ||
| 519 | # CONFIG_FTL is not set | ||
| 520 | # CONFIG_NFTL is not set | ||
| 521 | # CONFIG_INFTL is not set | ||
| 522 | # CONFIG_RFD_FTL is not set | ||
| 523 | # CONFIG_SSFDC is not set | ||
| 524 | # CONFIG_MTD_OOPS is not set | ||
| 525 | |||
| 526 | # | ||
| 527 | # RAM/ROM/Flash chip drivers | ||
| 528 | # | ||
| 529 | # CONFIG_MTD_CFI is not set | ||
| 530 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 531 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 532 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 533 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 534 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 535 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 536 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 537 | CONFIG_MTD_CFI_I1=y | ||
| 538 | CONFIG_MTD_CFI_I2=y | ||
| 539 | # CONFIG_MTD_CFI_I4 is not set | ||
| 540 | # CONFIG_MTD_CFI_I8 is not set | ||
| 541 | # CONFIG_MTD_RAM is not set | ||
| 542 | # CONFIG_MTD_ROM is not set | ||
| 543 | # CONFIG_MTD_ABSENT is not set | ||
| 544 | |||
| 545 | # | ||
| 546 | # Mapping drivers for chip access | ||
| 547 | # | ||
| 548 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 549 | # CONFIG_MTD_PLATRAM is not set | ||
| 550 | |||
| 551 | # | ||
| 552 | # Self-contained MTD device drivers | ||
| 553 | # | ||
| 554 | # CONFIG_MTD_DATAFLASH is not set | ||
| 555 | # CONFIG_MTD_M25P80 is not set | ||
| 556 | # CONFIG_MTD_SLRAM is not set | ||
| 557 | # CONFIG_MTD_PHRAM is not set | ||
| 558 | # CONFIG_MTD_MTDRAM is not set | ||
| 559 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 560 | |||
| 561 | # | ||
| 562 | # Disk-On-Chip Device Drivers | ||
| 563 | # | ||
| 564 | # CONFIG_MTD_DOC2000 is not set | ||
| 565 | # CONFIG_MTD_DOC2001 is not set | ||
| 566 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 567 | CONFIG_MTD_NAND=y | ||
| 568 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
| 569 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 570 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 571 | # CONFIG_MTD_NAND_GPIO is not set | ||
| 572 | CONFIG_MTD_NAND_IDS=y | ||
| 573 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 574 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 575 | # CONFIG_MTD_NAND_PLATFORM is not set | ||
| 576 | # CONFIG_MTD_ALAUDA is not set | ||
| 577 | # CONFIG_MTD_ONENAND is not set | ||
| 578 | |||
| 579 | # | ||
| 580 | # LPDDR flash memory drivers | ||
| 581 | # | ||
| 582 | # CONFIG_MTD_LPDDR is not set | ||
| 583 | |||
| 584 | # | ||
| 585 | # UBI - Unsorted block images | ||
| 586 | # | ||
| 587 | # CONFIG_MTD_UBI is not set | ||
| 588 | # CONFIG_PARPORT is not set | ||
| 589 | CONFIG_BLK_DEV=y | ||
| 590 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 591 | CONFIG_BLK_DEV_LOOP=y | ||
| 592 | CONFIG_BLK_DEV_CRYPTOLOOP=m | ||
| 593 | # CONFIG_BLK_DEV_NBD is not set | ||
| 594 | # CONFIG_BLK_DEV_UB is not set | ||
| 595 | CONFIG_BLK_DEV_RAM=y | ||
| 596 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 597 | CONFIG_BLK_DEV_RAM_SIZE=16384 | ||
| 598 | # CONFIG_BLK_DEV_XIP is not set | ||
| 599 | CONFIG_CDROM_PKTCDVD=m | ||
| 600 | CONFIG_CDROM_PKTCDVD_BUFFERS=8 | ||
| 601 | # CONFIG_CDROM_PKTCDVD_WCACHE is not set | ||
| 602 | # CONFIG_ATA_OVER_ETH is not set | ||
| 603 | CONFIG_MISC_DEVICES=y | ||
| 604 | # CONFIG_ICS932S401 is not set | ||
| 605 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 606 | # CONFIG_C2PORT is not set | ||
| 607 | |||
| 608 | # | ||
| 609 | # EEPROM support | ||
| 610 | # | ||
| 611 | # CONFIG_EEPROM_AT24 is not set | ||
| 612 | # CONFIG_EEPROM_AT25 is not set | ||
| 613 | # CONFIG_EEPROM_LEGACY is not set | ||
| 614 | CONFIG_EEPROM_93CX6=m | ||
| 615 | CONFIG_HAVE_IDE=y | ||
| 616 | # CONFIG_IDE is not set | ||
| 617 | |||
| 618 | # | ||
| 619 | # SCSI device support | ||
| 620 | # | ||
| 621 | CONFIG_RAID_ATTRS=m | ||
| 622 | CONFIG_SCSI=y | ||
| 623 | CONFIG_SCSI_DMA=y | ||
| 624 | # CONFIG_SCSI_TGT is not set | ||
| 625 | # CONFIG_SCSI_NETLINK is not set | ||
| 626 | CONFIG_SCSI_PROC_FS=y | ||
| 627 | |||
| 628 | # | ||
| 629 | # SCSI support type (disk, tape, CD-ROM) | ||
| 630 | # | ||
| 631 | CONFIG_BLK_DEV_SD=y | ||
| 632 | # CONFIG_CHR_DEV_ST is not set | ||
| 633 | # CONFIG_CHR_DEV_OSST is not set | ||
| 634 | # CONFIG_BLK_DEV_SR is not set | ||
| 635 | CONFIG_CHR_DEV_SG=m | ||
| 636 | # CONFIG_CHR_DEV_SCH is not set | ||
| 637 | |||
| 638 | # | ||
| 639 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 640 | # | ||
| 641 | CONFIG_SCSI_MULTI_LUN=y | ||
| 642 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 643 | # CONFIG_SCSI_LOGGING is not set | ||
| 644 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 645 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 646 | |||
| 647 | # | ||
| 648 | # SCSI Transports | ||
| 649 | # | ||
| 650 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 651 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 652 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 653 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 654 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 655 | CONFIG_SCSI_LOWLEVEL=y | ||
| 656 | # CONFIG_ISCSI_TCP is not set | ||
| 657 | # CONFIG_LIBFC is not set | ||
| 658 | # CONFIG_SCSI_DEBUG is not set | ||
| 659 | # CONFIG_SCSI_DH is not set | ||
| 660 | # CONFIG_ATA is not set | ||
| 661 | CONFIG_MD=y | ||
| 662 | CONFIG_BLK_DEV_MD=m | ||
| 663 | CONFIG_MD_LINEAR=m | ||
| 664 | CONFIG_MD_RAID0=m | ||
| 665 | CONFIG_MD_RAID1=m | ||
| 666 | CONFIG_MD_RAID10=m | ||
| 667 | CONFIG_MD_RAID456=m | ||
| 668 | CONFIG_MD_RAID5_RESHAPE=y | ||
| 669 | CONFIG_MD_MULTIPATH=m | ||
| 670 | CONFIG_MD_FAULTY=m | ||
| 671 | CONFIG_BLK_DEV_DM=m | ||
| 672 | # CONFIG_DM_DEBUG is not set | ||
| 673 | CONFIG_DM_CRYPT=m | ||
| 674 | CONFIG_DM_SNAPSHOT=m | ||
| 675 | CONFIG_DM_MIRROR=m | ||
| 676 | CONFIG_DM_ZERO=m | ||
| 677 | CONFIG_DM_MULTIPATH=m | ||
| 678 | CONFIG_DM_DELAY=m | ||
| 679 | # CONFIG_DM_UEVENT is not set | ||
| 680 | CONFIG_NETDEVICES=y | ||
| 681 | CONFIG_DUMMY=m | ||
| 682 | # CONFIG_BONDING is not set | ||
| 683 | # CONFIG_MACVLAN is not set | ||
| 684 | # CONFIG_EQUALIZER is not set | ||
| 685 | CONFIG_TUN=m | ||
| 686 | # CONFIG_VETH is not set | ||
| 687 | CONFIG_PHYLIB=y | ||
| 688 | |||
| 689 | # | ||
| 690 | # MII PHY device drivers | ||
| 691 | # | ||
| 692 | # CONFIG_MARVELL_PHY is not set | ||
| 693 | # CONFIG_DAVICOM_PHY is not set | ||
| 694 | # CONFIG_QSEMI_PHY is not set | ||
| 695 | # CONFIG_LXT_PHY is not set | ||
| 696 | # CONFIG_CICADA_PHY is not set | ||
| 697 | # CONFIG_VITESSE_PHY is not set | ||
| 698 | CONFIG_SMSC_PHY=y | ||
| 699 | # CONFIG_BROADCOM_PHY is not set | ||
| 700 | # CONFIG_ICPLUS_PHY is not set | ||
| 701 | # CONFIG_REALTEK_PHY is not set | ||
| 702 | # CONFIG_NATIONAL_PHY is not set | ||
| 703 | # CONFIG_STE10XP is not set | ||
| 704 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 705 | # CONFIG_FIXED_PHY is not set | ||
| 706 | # CONFIG_MDIO_BITBANG is not set | ||
| 707 | CONFIG_NET_ETHERNET=y | ||
| 708 | CONFIG_MII=y | ||
| 709 | # CONFIG_AX88796 is not set | ||
| 710 | CONFIG_SMC91X=y | ||
| 711 | # CONFIG_DM9000 is not set | ||
| 712 | # CONFIG_ENC28J60 is not set | ||
| 713 | CONFIG_SMC911X=m | ||
| 714 | CONFIG_SMSC911X=m | ||
| 715 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 716 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 717 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 718 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 719 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 720 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 721 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 722 | # CONFIG_B44 is not set | ||
| 723 | # CONFIG_NETDEV_1000 is not set | ||
| 724 | # CONFIG_NETDEV_10000 is not set | ||
| 725 | |||
| 726 | # | ||
| 727 | # Wireless LAN | ||
| 728 | # | ||
| 729 | # CONFIG_WLAN_PRE80211 is not set | ||
| 730 | CONFIG_WLAN_80211=y | ||
| 731 | CONFIG_LIBERTAS=y | ||
| 732 | CONFIG_LIBERTAS_USB=y | ||
| 733 | CONFIG_LIBERTAS_SDIO=y | ||
| 734 | CONFIG_LIBERTAS_DEBUG=y | ||
| 735 | # CONFIG_LIBERTAS_THINFIRM is not set | ||
| 736 | CONFIG_USB_ZD1201=m | ||
| 737 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
| 738 | CONFIG_RTL8187=m | ||
| 739 | # CONFIG_MAC80211_HWSIM is not set | ||
| 740 | CONFIG_P54_COMMON=m | ||
| 741 | CONFIG_P54_USB=m | ||
| 742 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 743 | CONFIG_HOSTAP=m | ||
| 744 | CONFIG_HOSTAP_FIRMWARE=y | ||
| 745 | CONFIG_HOSTAP_FIRMWARE_NVRAM=y | ||
| 746 | # CONFIG_B43 is not set | ||
| 747 | # CONFIG_B43LEGACY is not set | ||
| 748 | # CONFIG_ZD1211RW is not set | ||
| 749 | # CONFIG_RT2X00 is not set | ||
| 750 | |||
| 751 | # | ||
| 752 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 753 | # | ||
| 754 | |||
| 755 | # | ||
| 756 | # USB Network Adapters | ||
| 757 | # | ||
| 758 | CONFIG_USB_CATC=m | ||
| 759 | CONFIG_USB_KAWETH=m | ||
| 760 | CONFIG_USB_PEGASUS=m | ||
| 761 | CONFIG_USB_RTL8150=m | ||
| 762 | CONFIG_USB_USBNET=y | ||
| 763 | CONFIG_USB_NET_AX8817X=y | ||
| 764 | CONFIG_USB_NET_CDCETHER=y | ||
| 765 | CONFIG_USB_NET_DM9601=m | ||
| 766 | # CONFIG_USB_NET_SMSC95XX is not set | ||
| 767 | CONFIG_USB_NET_GL620A=m | ||
| 768 | CONFIG_USB_NET_NET1080=m | ||
| 769 | CONFIG_USB_NET_PLUSB=m | ||
| 770 | CONFIG_USB_NET_MCS7830=m | ||
| 771 | CONFIG_USB_NET_RNDIS_HOST=m | ||
| 772 | CONFIG_USB_NET_CDC_SUBSET=m | ||
| 773 | CONFIG_USB_ALI_M5632=y | ||
| 774 | CONFIG_USB_AN2720=y | ||
| 775 | CONFIG_USB_BELKIN=y | ||
| 776 | CONFIG_USB_ARMLINUX=y | ||
| 777 | CONFIG_USB_EPSON2888=y | ||
| 778 | CONFIG_USB_KC2190=y | ||
| 779 | CONFIG_USB_NET_ZAURUS=m | ||
| 780 | # CONFIG_WAN is not set | ||
| 781 | CONFIG_PPP=m | ||
| 782 | # CONFIG_PPP_MULTILINK is not set | ||
| 783 | # CONFIG_PPP_FILTER is not set | ||
| 784 | CONFIG_PPP_ASYNC=m | ||
| 785 | CONFIG_PPP_SYNC_TTY=m | ||
| 786 | CONFIG_PPP_DEFLATE=m | ||
| 787 | CONFIG_PPP_BSDCOMP=m | ||
| 788 | CONFIG_PPP_MPPE=m | ||
| 789 | CONFIG_PPPOE=m | ||
| 790 | # CONFIG_PPPOL2TP is not set | ||
| 791 | # CONFIG_SLIP is not set | ||
| 792 | CONFIG_SLHC=m | ||
| 793 | # CONFIG_NETCONSOLE is not set | ||
| 794 | # CONFIG_NETPOLL is not set | ||
| 795 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 796 | # CONFIG_ISDN is not set | ||
| 797 | |||
| 798 | # | ||
| 799 | # Input device support | ||
| 800 | # | ||
| 801 | CONFIG_INPUT=y | ||
| 802 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 803 | # CONFIG_INPUT_POLLDEV is not set | ||
| 804 | |||
| 805 | # | ||
| 806 | # Userland interfaces | ||
| 807 | # | ||
| 808 | CONFIG_INPUT_MOUSEDEV=y | ||
| 809 | CONFIG_INPUT_MOUSEDEV_PSAUX=y | ||
| 810 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 811 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 812 | # CONFIG_INPUT_JOYDEV is not set | ||
| 813 | CONFIG_INPUT_EVDEV=y | ||
| 814 | # CONFIG_INPUT_EVBUG is not set | ||
| 815 | |||
| 816 | # | ||
| 817 | # Input Device Drivers | ||
| 818 | # | ||
| 819 | CONFIG_INPUT_KEYBOARD=y | ||
| 820 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 821 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 822 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 823 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 824 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 825 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 826 | # CONFIG_KEYBOARD_GPIO is not set | ||
| 827 | CONFIG_INPUT_MOUSE=y | ||
| 828 | CONFIG_MOUSE_PS2=y | ||
| 829 | CONFIG_MOUSE_PS2_ALPS=y | ||
| 830 | CONFIG_MOUSE_PS2_LOGIPS2PP=y | ||
| 831 | CONFIG_MOUSE_PS2_SYNAPTICS=y | ||
| 832 | CONFIG_MOUSE_PS2_TRACKPOINT=y | ||
| 833 | # CONFIG_MOUSE_PS2_ELANTECH is not set | ||
| 834 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | ||
| 835 | # CONFIG_MOUSE_SERIAL is not set | ||
| 836 | # CONFIG_MOUSE_APPLETOUCH is not set | ||
| 837 | # CONFIG_MOUSE_BCM5974 is not set | ||
| 838 | # CONFIG_MOUSE_VSXXXAA is not set | ||
| 839 | # CONFIG_MOUSE_GPIO is not set | ||
| 840 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 841 | # CONFIG_INPUT_TABLET is not set | ||
| 842 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 843 | # CONFIG_INPUT_MISC is not set | ||
| 844 | |||
| 845 | # | ||
| 846 | # Hardware I/O ports | ||
| 847 | # | ||
| 848 | CONFIG_SERIO=y | ||
| 849 | CONFIG_SERIO_SERPORT=y | ||
| 850 | CONFIG_SERIO_LIBPS2=y | ||
| 851 | # CONFIG_SERIO_RAW is not set | ||
| 852 | # CONFIG_GAMEPORT is not set | ||
| 853 | |||
| 854 | # | ||
| 855 | # Character devices | ||
| 856 | # | ||
| 857 | CONFIG_VT=y | ||
| 858 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 859 | CONFIG_VT_CONSOLE=y | ||
| 860 | CONFIG_HW_CONSOLE=y | ||
| 861 | CONFIG_VT_HW_CONSOLE_BINDING=y | ||
| 862 | CONFIG_DEVKMEM=y | ||
| 863 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 864 | |||
| 865 | # | ||
| 866 | # Serial drivers | ||
| 867 | # | ||
| 868 | CONFIG_SERIAL_8250=y | ||
| 869 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 870 | CONFIG_SERIAL_8250_NR_UARTS=32 | ||
| 871 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | ||
| 872 | CONFIG_SERIAL_8250_EXTENDED=y | ||
| 873 | CONFIG_SERIAL_8250_MANY_PORTS=y | ||
| 874 | CONFIG_SERIAL_8250_SHARE_IRQ=y | ||
| 875 | CONFIG_SERIAL_8250_DETECT_IRQ=y | ||
| 876 | CONFIG_SERIAL_8250_RSA=y | ||
| 877 | |||
| 878 | # | ||
| 879 | # Non-8250 serial port support | ||
| 880 | # | ||
| 881 | CONFIG_SERIAL_CORE=y | ||
| 882 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 883 | CONFIG_UNIX98_PTYS=y | ||
| 884 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 885 | # CONFIG_LEGACY_PTYS is not set | ||
| 886 | # CONFIG_IPMI_HANDLER is not set | ||
| 887 | CONFIG_HW_RANDOM=y | ||
| 888 | # CONFIG_R3964 is not set | ||
| 889 | # CONFIG_RAW_DRIVER is not set | ||
| 890 | # CONFIG_TCG_TPM is not set | ||
| 891 | CONFIG_I2C=y | ||
| 892 | CONFIG_I2C_BOARDINFO=y | ||
| 893 | CONFIG_I2C_CHARDEV=y | ||
| 894 | CONFIG_I2C_HELPER_AUTO=y | ||
| 895 | |||
| 896 | # | ||
| 897 | # I2C Hardware Bus support | ||
| 898 | # | ||
| 899 | |||
| 900 | # | ||
| 901 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 902 | # | ||
| 903 | # CONFIG_I2C_GPIO is not set | ||
| 904 | # CONFIG_I2C_OCORES is not set | ||
| 905 | CONFIG_I2C_OMAP=y | ||
| 906 | # CONFIG_I2C_SIMTEC is not set | ||
| 907 | |||
| 908 | # | ||
| 909 | # External I2C/SMBus adapter drivers | ||
| 910 | # | ||
| 911 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 912 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 913 | # CONFIG_I2C_TINY_USB is not set | ||
| 914 | |||
| 915 | # | ||
| 916 | # Other I2C/SMBus bus drivers | ||
| 917 | # | ||
| 918 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 919 | # CONFIG_I2C_STUB is not set | ||
| 920 | |||
| 921 | # | ||
| 922 | # Miscellaneous I2C Chip support | ||
| 923 | # | ||
| 924 | # CONFIG_DS1682 is not set | ||
| 925 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 926 | # CONFIG_PCF8575 is not set | ||
| 927 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 928 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 929 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 930 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 931 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 932 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 933 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 934 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 935 | CONFIG_SPI=y | ||
| 936 | # CONFIG_SPI_DEBUG is not set | ||
| 937 | CONFIG_SPI_MASTER=y | ||
| 938 | |||
| 939 | # | ||
| 940 | # SPI Master Controller Drivers | ||
| 941 | # | ||
| 942 | # CONFIG_SPI_BITBANG is not set | ||
| 943 | # CONFIG_SPI_GPIO is not set | ||
| 944 | CONFIG_SPI_OMAP24XX=y | ||
| 945 | |||
| 946 | # | ||
| 947 | # SPI Protocol Masters | ||
| 948 | # | ||
| 949 | # CONFIG_SPI_SPIDEV is not set | ||
| 950 | # CONFIG_SPI_TLE62X0 is not set | ||
| 951 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 952 | CONFIG_GPIOLIB=y | ||
| 953 | CONFIG_DEBUG_GPIO=y | ||
| 954 | CONFIG_GPIO_SYSFS=y | ||
| 955 | |||
| 956 | # | ||
| 957 | # Memory mapped GPIO expanders: | ||
| 958 | # | ||
| 959 | |||
| 960 | # | ||
| 961 | # I2C GPIO expanders: | ||
| 962 | # | ||
| 963 | # CONFIG_GPIO_MAX732X is not set | ||
| 964 | # CONFIG_GPIO_PCA953X is not set | ||
| 965 | # CONFIG_GPIO_PCF857X is not set | ||
| 966 | CONFIG_GPIO_TWL4030=y | ||
| 967 | |||
| 968 | # | ||
| 969 | # PCI GPIO expanders: | ||
| 970 | # | ||
| 971 | |||
| 972 | # | ||
| 973 | # SPI GPIO expanders: | ||
| 974 | # | ||
| 975 | # CONFIG_GPIO_MAX7301 is not set | ||
| 976 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 977 | # CONFIG_W1 is not set | ||
| 978 | CONFIG_POWER_SUPPLY=m | ||
| 979 | # CONFIG_POWER_SUPPLY_DEBUG is not set | ||
| 980 | # CONFIG_PDA_POWER is not set | ||
| 981 | # CONFIG_BATTERY_DS2760 is not set | ||
| 982 | # CONFIG_BATTERY_BQ27x00 is not set | ||
| 983 | CONFIG_HWMON=y | ||
| 984 | # CONFIG_HWMON_VID is not set | ||
| 985 | # CONFIG_SENSORS_AD7414 is not set | ||
| 986 | # CONFIG_SENSORS_AD7418 is not set | ||
| 987 | # CONFIG_SENSORS_ADCXX is not set | ||
| 988 | # CONFIG_SENSORS_ADM1021 is not set | ||
| 989 | # CONFIG_SENSORS_ADM1025 is not set | ||
| 990 | # CONFIG_SENSORS_ADM1026 is not set | ||
| 991 | # CONFIG_SENSORS_ADM1029 is not set | ||
| 992 | # CONFIG_SENSORS_ADM1031 is not set | ||
| 993 | # CONFIG_SENSORS_ADM9240 is not set | ||
| 994 | # CONFIG_SENSORS_ADT7462 is not set | ||
| 995 | # CONFIG_SENSORS_ADT7470 is not set | ||
| 996 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 997 | # CONFIG_SENSORS_ADT7475 is not set | ||
| 998 | # CONFIG_SENSORS_ATXP1 is not set | ||
| 999 | # CONFIG_SENSORS_DS1621 is not set | ||
| 1000 | # CONFIG_SENSORS_F71805F is not set | ||
| 1001 | # CONFIG_SENSORS_F71882FG is not set | ||
| 1002 | # CONFIG_SENSORS_F75375S is not set | ||
| 1003 | # CONFIG_SENSORS_GL518SM is not set | ||
| 1004 | # CONFIG_SENSORS_GL520SM is not set | ||
| 1005 | # CONFIG_SENSORS_IT87 is not set | ||
| 1006 | # CONFIG_SENSORS_LM63 is not set | ||
| 1007 | # CONFIG_SENSORS_LM70 is not set | ||
| 1008 | # CONFIG_SENSORS_LM75 is not set | ||
| 1009 | # CONFIG_SENSORS_LM77 is not set | ||
| 1010 | # CONFIG_SENSORS_LM78 is not set | ||
| 1011 | # CONFIG_SENSORS_LM80 is not set | ||
| 1012 | # CONFIG_SENSORS_LM83 is not set | ||
| 1013 | # CONFIG_SENSORS_LM85 is not set | ||
| 1014 | # CONFIG_SENSORS_LM87 is not set | ||
| 1015 | # CONFIG_SENSORS_LM90 is not set | ||
| 1016 | # CONFIG_SENSORS_LM92 is not set | ||
| 1017 | # CONFIG_SENSORS_LM93 is not set | ||
| 1018 | # CONFIG_SENSORS_LTC4245 is not set | ||
| 1019 | # CONFIG_SENSORS_MAX1111 is not set | ||
| 1020 | # CONFIG_SENSORS_MAX1619 is not set | ||
| 1021 | # CONFIG_SENSORS_MAX6650 is not set | ||
| 1022 | # CONFIG_SENSORS_PC87360 is not set | ||
| 1023 | # CONFIG_SENSORS_PC87427 is not set | ||
| 1024 | # CONFIG_SENSORS_DME1737 is not set | ||
| 1025 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
| 1026 | # CONFIG_SENSORS_SMSC47M192 is not set | ||
| 1027 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
| 1028 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 1029 | # CONFIG_SENSORS_THMC50 is not set | ||
| 1030 | # CONFIG_SENSORS_VT1211 is not set | ||
| 1031 | # CONFIG_SENSORS_W83781D is not set | ||
| 1032 | # CONFIG_SENSORS_W83791D is not set | ||
| 1033 | # CONFIG_SENSORS_W83792D is not set | ||
| 1034 | # CONFIG_SENSORS_W83793 is not set | ||
| 1035 | # CONFIG_SENSORS_W83L785TS is not set | ||
| 1036 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 1037 | # CONFIG_SENSORS_W83627HF is not set | ||
| 1038 | # CONFIG_SENSORS_W83627EHF is not set | ||
| 1039 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
| 1040 | # CONFIG_THERMAL is not set | ||
| 1041 | # CONFIG_THERMAL_HWMON is not set | ||
| 1042 | CONFIG_WATCHDOG=y | ||
| 1043 | CONFIG_WATCHDOG_NOWAYOUT=y | ||
| 1044 | |||
| 1045 | # | ||
| 1046 | # Watchdog Device Drivers | ||
| 1047 | # | ||
| 1048 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 1049 | # CONFIG_OMAP_WATCHDOG is not set | ||
| 1050 | |||
| 1051 | # | ||
| 1052 | # USB-based Watchdog Cards | ||
| 1053 | # | ||
| 1054 | # CONFIG_USBPCWATCHDOG is not set | ||
| 1055 | CONFIG_SSB_POSSIBLE=y | ||
| 1056 | |||
| 1057 | # | ||
| 1058 | # Sonics Silicon Backplane | ||
| 1059 | # | ||
| 1060 | # CONFIG_SSB is not set | ||
| 1061 | |||
| 1062 | # | ||
| 1063 | # Multifunction device drivers | ||
| 1064 | # | ||
| 1065 | # CONFIG_MFD_CORE is not set | ||
| 1066 | # CONFIG_MFD_SM501 is not set | ||
| 1067 | # CONFIG_MFD_ASIC3 is not set | ||
| 1068 | # CONFIG_HTC_EGPIO is not set | ||
| 1069 | # CONFIG_HTC_PASIC3 is not set | ||
| 1070 | # CONFIG_TPS65010 is not set | ||
| 1071 | CONFIG_TWL4030_CORE=y | ||
| 1072 | # CONFIG_MFD_TMIO is not set | ||
| 1073 | # CONFIG_MFD_T7L66XB is not set | ||
| 1074 | # CONFIG_MFD_TC6387XB is not set | ||
| 1075 | # CONFIG_MFD_TC6393XB is not set | ||
| 1076 | # CONFIG_PMIC_DA903X is not set | ||
| 1077 | # CONFIG_MFD_WM8400 is not set | ||
| 1078 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 1079 | # CONFIG_MFD_PCF50633 is not set | ||
| 1080 | |||
| 1081 | # | ||
| 1082 | # Multimedia devices | ||
| 1083 | # | ||
| 1084 | |||
| 1085 | # | ||
| 1086 | # Multimedia core support | ||
| 1087 | # | ||
| 1088 | CONFIG_VIDEO_DEV=m | ||
| 1089 | CONFIG_VIDEO_V4L2_COMMON=m | ||
| 1090 | CONFIG_VIDEO_ALLOW_V4L1=y | ||
| 1091 | CONFIG_VIDEO_V4L1_COMPAT=y | ||
| 1092 | CONFIG_DVB_CORE=m | ||
| 1093 | CONFIG_VIDEO_MEDIA=m | ||
| 1094 | |||
| 1095 | # | ||
| 1096 | # Multimedia drivers | ||
| 1097 | # | ||
| 1098 | CONFIG_MEDIA_ATTACH=y | ||
| 1099 | CONFIG_MEDIA_TUNER=m | ||
| 1100 | # CONFIG_MEDIA_TUNER_CUSTOMIZE is not set | ||
| 1101 | CONFIG_MEDIA_TUNER_SIMPLE=m | ||
| 1102 | CONFIG_MEDIA_TUNER_TDA8290=m | ||
| 1103 | CONFIG_MEDIA_TUNER_TDA827X=m | ||
| 1104 | CONFIG_MEDIA_TUNER_TDA18271=m | ||
| 1105 | CONFIG_MEDIA_TUNER_TDA9887=m | ||
| 1106 | CONFIG_MEDIA_TUNER_TEA5761=m | ||
| 1107 | CONFIG_MEDIA_TUNER_TEA5767=m | ||
| 1108 | CONFIG_MEDIA_TUNER_MT20XX=m | ||
| 1109 | CONFIG_MEDIA_TUNER_MT2060=m | ||
| 1110 | CONFIG_MEDIA_TUNER_MT2266=m | ||
| 1111 | CONFIG_MEDIA_TUNER_QT1010=m | ||
| 1112 | CONFIG_MEDIA_TUNER_XC2028=m | ||
| 1113 | CONFIG_MEDIA_TUNER_XC5000=m | ||
| 1114 | CONFIG_MEDIA_TUNER_MXL5005S=m | ||
| 1115 | CONFIG_VIDEO_V4L2=m | ||
| 1116 | CONFIG_VIDEO_V4L1=m | ||
| 1117 | CONFIG_VIDEO_TVEEPROM=m | ||
| 1118 | CONFIG_VIDEO_TUNER=m | ||
| 1119 | CONFIG_VIDEO_CAPTURE_DRIVERS=y | ||
| 1120 | # CONFIG_VIDEO_ADV_DEBUG is not set | ||
| 1121 | # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set | ||
| 1122 | CONFIG_VIDEO_HELPER_CHIPS_AUTO=y | ||
| 1123 | CONFIG_VIDEO_MSP3400=m | ||
| 1124 | CONFIG_VIDEO_CS53L32A=m | ||
| 1125 | CONFIG_VIDEO_WM8775=m | ||
| 1126 | CONFIG_VIDEO_SAA711X=m | ||
| 1127 | CONFIG_VIDEO_CX25840=m | ||
| 1128 | CONFIG_VIDEO_CX2341X=m | ||
| 1129 | # CONFIG_VIDEO_VIVI is not set | ||
| 1130 | # CONFIG_VIDEO_CPIA is not set | ||
| 1131 | # CONFIG_VIDEO_CPIA2 is not set | ||
| 1132 | # CONFIG_VIDEO_SAA5246A is not set | ||
| 1133 | # CONFIG_VIDEO_SAA5249 is not set | ||
| 1134 | # CONFIG_VIDEO_AU0828 is not set | ||
| 1135 | # CONFIG_SOC_CAMERA is not set | ||
| 1136 | CONFIG_V4L_USB_DRIVERS=y | ||
| 1137 | CONFIG_USB_VIDEO_CLASS=m | ||
| 1138 | CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y | ||
| 1139 | # CONFIG_USB_GSPCA is not set | ||
| 1140 | CONFIG_VIDEO_PVRUSB2=m | ||
| 1141 | CONFIG_VIDEO_PVRUSB2_SYSFS=y | ||
| 1142 | CONFIG_VIDEO_PVRUSB2_DVB=y | ||
| 1143 | # CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set | ||
| 1144 | # CONFIG_VIDEO_EM28XX is not set | ||
| 1145 | CONFIG_VIDEO_USBVISION=m | ||
| 1146 | CONFIG_VIDEO_USBVIDEO=m | ||
| 1147 | CONFIG_USB_VICAM=m | ||
| 1148 | CONFIG_USB_IBMCAM=m | ||
| 1149 | CONFIG_USB_KONICAWC=m | ||
| 1150 | CONFIG_USB_QUICKCAM_MESSENGER=m | ||
| 1151 | # CONFIG_USB_ET61X251 is not set | ||
| 1152 | CONFIG_VIDEO_OVCAMCHIP=m | ||
| 1153 | CONFIG_USB_W9968CF=m | ||
| 1154 | CONFIG_USB_OV511=m | ||
| 1155 | CONFIG_USB_SE401=m | ||
| 1156 | CONFIG_USB_SN9C102=m | ||
| 1157 | CONFIG_USB_STV680=m | ||
| 1158 | # CONFIG_USB_ZC0301 is not set | ||
| 1159 | CONFIG_USB_PWC=m | ||
| 1160 | # CONFIG_USB_PWC_DEBUG is not set | ||
| 1161 | CONFIG_USB_ZR364XX=m | ||
| 1162 | # CONFIG_USB_STKWEBCAM is not set | ||
| 1163 | # CONFIG_USB_S2255 is not set | ||
| 1164 | CONFIG_RADIO_ADAPTERS=y | ||
| 1165 | # CONFIG_USB_DSBR is not set | ||
| 1166 | # CONFIG_USB_SI470X is not set | ||
| 1167 | # CONFIG_USB_MR800 is not set | ||
| 1168 | # CONFIG_RADIO_TEA5764 is not set | ||
| 1169 | # CONFIG_DVB_DYNAMIC_MINORS is not set | ||
| 1170 | CONFIG_DVB_CAPTURE_DRIVERS=y | ||
| 1171 | # CONFIG_TTPCI_EEPROM is not set | ||
| 1172 | |||
| 1173 | # | ||
| 1174 | # Supported USB Adapters | ||
| 1175 | # | ||
| 1176 | CONFIG_DVB_USB=m | ||
| 1177 | # CONFIG_DVB_USB_DEBUG is not set | ||
| 1178 | CONFIG_DVB_USB_A800=m | ||
| 1179 | CONFIG_DVB_USB_DIBUSB_MB=m | ||
| 1180 | # CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set | ||
| 1181 | CONFIG_DVB_USB_DIBUSB_MC=m | ||
| 1182 | CONFIG_DVB_USB_DIB0700=m | ||
| 1183 | CONFIG_DVB_USB_UMT_010=m | ||
| 1184 | CONFIG_DVB_USB_CXUSB=m | ||
| 1185 | CONFIG_DVB_USB_M920X=m | ||
| 1186 | CONFIG_DVB_USB_GL861=m | ||
| 1187 | CONFIG_DVB_USB_AU6610=m | ||
| 1188 | CONFIG_DVB_USB_DIGITV=m | ||
| 1189 | CONFIG_DVB_USB_VP7045=m | ||
| 1190 | CONFIG_DVB_USB_VP702X=m | ||
| 1191 | CONFIG_DVB_USB_GP8PSK=m | ||
| 1192 | CONFIG_DVB_USB_NOVA_T_USB2=m | ||
| 1193 | CONFIG_DVB_USB_TTUSB2=m | ||
| 1194 | CONFIG_DVB_USB_DTT200U=m | ||
| 1195 | CONFIG_DVB_USB_OPERA1=m | ||
| 1196 | CONFIG_DVB_USB_AF9005=m | ||
| 1197 | CONFIG_DVB_USB_AF9005_REMOTE=m | ||
| 1198 | # CONFIG_DVB_USB_DW2102 is not set | ||
| 1199 | # CONFIG_DVB_USB_CINERGY_T2 is not set | ||
| 1200 | # CONFIG_DVB_USB_ANYSEE is not set | ||
| 1201 | # CONFIG_DVB_USB_DTV5100 is not set | ||
| 1202 | # CONFIG_DVB_USB_AF9015 is not set | ||
| 1203 | # CONFIG_DVB_SIANO_SMS1XXX is not set | ||
| 1204 | |||
| 1205 | # | ||
| 1206 | # Supported FlexCopII (B2C2) Adapters | ||
| 1207 | # | ||
| 1208 | # CONFIG_DVB_B2C2_FLEXCOP is not set | ||
| 1209 | |||
| 1210 | # | ||
| 1211 | # Supported DVB Frontends | ||
| 1212 | # | ||
| 1213 | |||
| 1214 | # | ||
| 1215 | # Customise DVB Frontends | ||
| 1216 | # | ||
| 1217 | # CONFIG_DVB_FE_CUSTOMISE is not set | ||
| 1218 | |||
| 1219 | # | ||
| 1220 | # Multistandard (satellite) frontends | ||
| 1221 | # | ||
| 1222 | # CONFIG_DVB_STB0899 is not set | ||
| 1223 | # CONFIG_DVB_STB6100 is not set | ||
| 1224 | |||
| 1225 | # | ||
| 1226 | # DVB-S (satellite) frontends | ||
| 1227 | # | ||
| 1228 | CONFIG_DVB_CX24110=m | ||
| 1229 | CONFIG_DVB_CX24123=m | ||
| 1230 | CONFIG_DVB_MT312=m | ||
| 1231 | CONFIG_DVB_S5H1420=m | ||
| 1232 | # CONFIG_DVB_STV0288 is not set | ||
| 1233 | # CONFIG_DVB_STB6000 is not set | ||
| 1234 | CONFIG_DVB_STV0299=m | ||
| 1235 | CONFIG_DVB_TDA8083=m | ||
| 1236 | CONFIG_DVB_TDA10086=m | ||
| 1237 | # CONFIG_DVB_TDA8261 is not set | ||
| 1238 | CONFIG_DVB_VES1X93=m | ||
| 1239 | CONFIG_DVB_TUNER_ITD1000=m | ||
| 1240 | # CONFIG_DVB_TUNER_CX24113 is not set | ||
| 1241 | CONFIG_DVB_TDA826X=m | ||
| 1242 | CONFIG_DVB_TUA6100=m | ||
| 1243 | # CONFIG_DVB_CX24116 is not set | ||
| 1244 | # CONFIG_DVB_SI21XX is not set | ||
| 1245 | |||
| 1246 | # | ||
| 1247 | # DVB-T (terrestrial) frontends | ||
| 1248 | # | ||
| 1249 | CONFIG_DVB_SP8870=m | ||
| 1250 | CONFIG_DVB_SP887X=m | ||
| 1251 | CONFIG_DVB_CX22700=m | ||
| 1252 | CONFIG_DVB_CX22702=m | ||
| 1253 | # CONFIG_DVB_DRX397XD is not set | ||
| 1254 | CONFIG_DVB_L64781=m | ||
| 1255 | CONFIG_DVB_TDA1004X=m | ||
| 1256 | CONFIG_DVB_NXT6000=m | ||
| 1257 | CONFIG_DVB_MT352=m | ||
| 1258 | CONFIG_DVB_ZL10353=m | ||
| 1259 | CONFIG_DVB_DIB3000MB=m | ||
| 1260 | CONFIG_DVB_DIB3000MC=m | ||
| 1261 | CONFIG_DVB_DIB7000M=m | ||
| 1262 | CONFIG_DVB_DIB7000P=m | ||
| 1263 | CONFIG_DVB_TDA10048=m | ||
| 1264 | |||
| 1265 | # | ||
| 1266 | # DVB-C (cable) frontends | ||
| 1267 | # | ||
| 1268 | CONFIG_DVB_VES1820=m | ||
| 1269 | CONFIG_DVB_TDA10021=m | ||
| 1270 | CONFIG_DVB_TDA10023=m | ||
| 1271 | CONFIG_DVB_STV0297=m | ||
| 1272 | |||
| 1273 | # | ||
| 1274 | # ATSC (North American/Korean Terrestrial/Cable DTV) frontends | ||
| 1275 | # | ||
| 1276 | CONFIG_DVB_NXT200X=m | ||
| 1277 | # CONFIG_DVB_OR51211 is not set | ||
| 1278 | # CONFIG_DVB_OR51132 is not set | ||
| 1279 | CONFIG_DVB_BCM3510=m | ||
| 1280 | CONFIG_DVB_LGDT330X=m | ||
| 1281 | # CONFIG_DVB_LGDT3304 is not set | ||
| 1282 | CONFIG_DVB_S5H1409=m | ||
| 1283 | CONFIG_DVB_AU8522=m | ||
| 1284 | CONFIG_DVB_S5H1411=m | ||
| 1285 | |||
| 1286 | # | ||
| 1287 | # ISDB-T (terrestrial) frontends | ||
| 1288 | # | ||
| 1289 | # CONFIG_DVB_S921 is not set | ||
| 1290 | |||
| 1291 | # | ||
| 1292 | # Digital terrestrial only tuners/PLL | ||
| 1293 | # | ||
| 1294 | CONFIG_DVB_PLL=m | ||
| 1295 | CONFIG_DVB_TUNER_DIB0070=m | ||
| 1296 | |||
| 1297 | # | ||
| 1298 | # SEC control devices for DVB-S | ||
| 1299 | # | ||
| 1300 | CONFIG_DVB_LNBP21=m | ||
| 1301 | # CONFIG_DVB_ISL6405 is not set | ||
| 1302 | CONFIG_DVB_ISL6421=m | ||
| 1303 | # CONFIG_DVB_LGS8GL5 is not set | ||
| 1304 | |||
| 1305 | # | ||
| 1306 | # Tools to develop new frontends | ||
| 1307 | # | ||
| 1308 | # CONFIG_DVB_DUMMY_FE is not set | ||
| 1309 | # CONFIG_DVB_AF9013 is not set | ||
| 1310 | # CONFIG_DAB is not set | ||
| 1311 | |||
| 1312 | # | ||
| 1313 | # Graphics support | ||
| 1314 | # | ||
| 1315 | # CONFIG_VGASTATE is not set | ||
| 1316 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 1317 | # CONFIG_FB is not set | ||
| 1318 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 1319 | |||
| 1320 | # | ||
| 1321 | # Display device support | ||
| 1322 | # | ||
| 1323 | CONFIG_DISPLAY_SUPPORT=y | ||
| 1324 | |||
| 1325 | # | ||
| 1326 | # Display hardware drivers | ||
| 1327 | # | ||
| 1328 | |||
| 1329 | # | ||
| 1330 | # Console display driver support | ||
| 1331 | # | ||
| 1332 | # CONFIG_VGA_CONSOLE is not set | ||
| 1333 | CONFIG_DUMMY_CONSOLE=y | ||
| 1334 | CONFIG_SOUND=y | ||
| 1335 | CONFIG_SOUND_OSS_CORE=y | ||
| 1336 | CONFIG_SND=y | ||
| 1337 | CONFIG_SND_TIMER=y | ||
| 1338 | CONFIG_SND_PCM=y | ||
| 1339 | CONFIG_SND_HWDEP=y | ||
| 1340 | CONFIG_SND_RAWMIDI=y | ||
| 1341 | CONFIG_SND_SEQUENCER=m | ||
| 1342 | # CONFIG_SND_SEQ_DUMMY is not set | ||
| 1343 | CONFIG_SND_OSSEMUL=y | ||
| 1344 | CONFIG_SND_MIXER_OSS=y | ||
| 1345 | CONFIG_SND_PCM_OSS=y | ||
| 1346 | CONFIG_SND_PCM_OSS_PLUGINS=y | ||
| 1347 | CONFIG_SND_SEQUENCER_OSS=y | ||
| 1348 | # CONFIG_SND_HRTIMER is not set | ||
| 1349 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
| 1350 | CONFIG_SND_SUPPORT_OLD_API=y | ||
| 1351 | CONFIG_SND_VERBOSE_PROCFS=y | ||
| 1352 | CONFIG_SND_VERBOSE_PRINTK=y | ||
| 1353 | CONFIG_SND_DEBUG=y | ||
| 1354 | # CONFIG_SND_DEBUG_VERBOSE is not set | ||
| 1355 | # CONFIG_SND_PCM_XRUN_DEBUG is not set | ||
| 1356 | CONFIG_SND_DRIVERS=y | ||
| 1357 | # CONFIG_SND_DUMMY is not set | ||
| 1358 | # CONFIG_SND_VIRMIDI is not set | ||
| 1359 | # CONFIG_SND_MTPAV is not set | ||
| 1360 | # CONFIG_SND_SERIAL_U16550 is not set | ||
| 1361 | # CONFIG_SND_MPU401 is not set | ||
| 1362 | CONFIG_SND_ARM=y | ||
| 1363 | CONFIG_SND_SPI=y | ||
| 1364 | CONFIG_SND_USB=y | ||
| 1365 | CONFIG_SND_USB_AUDIO=y | ||
| 1366 | CONFIG_SND_USB_CAIAQ=m | ||
| 1367 | CONFIG_SND_USB_CAIAQ_INPUT=y | ||
| 1368 | CONFIG_SND_SOC=y | ||
| 1369 | CONFIG_SND_OMAP_SOC=y | ||
| 1370 | CONFIG_SND_OMAP_SOC_MCBSP=y | ||
| 1371 | # CONFIG_SND_OMAP_SOC_OVERO is not set | ||
| 1372 | CONFIG_SND_OMAP_SOC_SDP3430=y | ||
| 1373 | CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=y | ||
| 1374 | CONFIG_SND_SOC_I2C_AND_SPI=y | ||
| 1375 | # CONFIG_SND_SOC_ALL_CODECS is not set | ||
| 1376 | CONFIG_SND_SOC_TWL4030=y | ||
| 1377 | # CONFIG_SOUND_PRIME is not set | ||
| 1378 | CONFIG_HID_SUPPORT=y | ||
| 1379 | CONFIG_HID=y | ||
| 1380 | CONFIG_HID_DEBUG=y | ||
| 1381 | # CONFIG_HIDRAW is not set | ||
| 1382 | |||
| 1383 | # | ||
| 1384 | # USB Input Devices | ||
| 1385 | # | ||
| 1386 | CONFIG_USB_HID=y | ||
| 1387 | # CONFIG_HID_PID is not set | ||
| 1388 | # CONFIG_USB_HIDDEV is not set | ||
| 1389 | |||
| 1390 | # | ||
| 1391 | # Special HID drivers | ||
| 1392 | # | ||
| 1393 | CONFIG_HID_COMPAT=y | ||
| 1394 | CONFIG_HID_A4TECH=y | ||
| 1395 | CONFIG_HID_APPLE=y | ||
| 1396 | CONFIG_HID_BELKIN=y | ||
| 1397 | CONFIG_HID_CHERRY=y | ||
| 1398 | CONFIG_HID_CHICONY=y | ||
| 1399 | CONFIG_HID_CYPRESS=y | ||
| 1400 | CONFIG_HID_EZKEY=y | ||
| 1401 | CONFIG_HID_GYRATION=y | ||
| 1402 | CONFIG_HID_LOGITECH=y | ||
| 1403 | # CONFIG_LOGITECH_FF is not set | ||
| 1404 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | ||
| 1405 | CONFIG_HID_MICROSOFT=y | ||
| 1406 | CONFIG_HID_MONTEREY=y | ||
| 1407 | # CONFIG_HID_NTRIG is not set | ||
| 1408 | CONFIG_HID_PANTHERLORD=y | ||
| 1409 | # CONFIG_PANTHERLORD_FF is not set | ||
| 1410 | CONFIG_HID_PETALYNX=y | ||
| 1411 | CONFIG_HID_SAMSUNG=y | ||
| 1412 | CONFIG_HID_SONY=y | ||
| 1413 | CONFIG_HID_SUNPLUS=y | ||
| 1414 | # CONFIG_GREENASIA_FF is not set | ||
| 1415 | # CONFIG_HID_TOPSEED is not set | ||
| 1416 | # CONFIG_THRUSTMASTER_FF is not set | ||
| 1417 | # CONFIG_ZEROPLUS_FF is not set | ||
| 1418 | CONFIG_USB_SUPPORT=y | ||
| 1419 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 1420 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 1421 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 1422 | CONFIG_USB=y | ||
| 1423 | CONFIG_USB_DEBUG=y | ||
| 1424 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 1425 | |||
| 1426 | # | ||
| 1427 | # Miscellaneous USB options | ||
| 1428 | # | ||
| 1429 | CONFIG_USB_DEVICEFS=y | ||
| 1430 | CONFIG_USB_DEVICE_CLASS=y | ||
| 1431 | CONFIG_USB_DYNAMIC_MINORS=y | ||
| 1432 | CONFIG_USB_SUSPEND=y | ||
| 1433 | CONFIG_USB_OTG=y | ||
| 1434 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 1435 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
| 1436 | CONFIG_USB_MON=y | ||
| 1437 | # CONFIG_USB_WUSB is not set | ||
| 1438 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1439 | |||
| 1440 | # | ||
| 1441 | # USB Host Controller Drivers | ||
| 1442 | # | ||
| 1443 | # CONFIG_USB_C67X00_HCD is not set | ||
| 1444 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1445 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 1446 | # CONFIG_USB_OHCI_HCD is not set | ||
| 1447 | # CONFIG_USB_SL811_HCD is not set | ||
| 1448 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 1449 | # CONFIG_USB_HWA_HCD is not set | ||
| 1450 | CONFIG_USB_MUSB_HDRC=y | ||
| 1451 | CONFIG_USB_MUSB_SOC=y | ||
| 1452 | |||
| 1453 | # | ||
| 1454 | # OMAP 343x high speed USB support | ||
| 1455 | # | ||
| 1456 | # CONFIG_USB_MUSB_HOST is not set | ||
| 1457 | # CONFIG_USB_MUSB_PERIPHERAL is not set | ||
| 1458 | CONFIG_USB_MUSB_OTG=y | ||
| 1459 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 1460 | CONFIG_USB_MUSB_HDRC_HCD=y | ||
| 1461 | CONFIG_MUSB_PIO_ONLY=y | ||
| 1462 | # CONFIG_USB_MUSB_DEBUG is not set | ||
| 1463 | |||
| 1464 | # | ||
| 1465 | # USB Device Class drivers | ||
| 1466 | # | ||
| 1467 | # CONFIG_USB_ACM is not set | ||
| 1468 | CONFIG_USB_PRINTER=y | ||
| 1469 | CONFIG_USB_WDM=y | ||
| 1470 | # CONFIG_USB_TMC is not set | ||
| 1471 | |||
| 1472 | # | ||
| 1473 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; | ||
| 1474 | # | ||
| 1475 | |||
| 1476 | # | ||
| 1477 | # see USB_STORAGE Help for more information | ||
| 1478 | # | ||
| 1479 | CONFIG_USB_STORAGE=y | ||
| 1480 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 1481 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 1482 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 1483 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 1484 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 1485 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 1486 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 1487 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 1488 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 1489 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 1490 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 1491 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 1492 | # CONFIG_USB_LIBUSUAL is not set | ||
| 1493 | |||
| 1494 | # | ||
| 1495 | # USB Imaging devices | ||
| 1496 | # | ||
| 1497 | # CONFIG_USB_MDC800 is not set | ||
| 1498 | # CONFIG_USB_MICROTEK is not set | ||
| 1499 | |||
| 1500 | # | ||
| 1501 | # USB port drivers | ||
| 1502 | # | ||
| 1503 | # CONFIG_USB_SERIAL is not set | ||
| 1504 | |||
| 1505 | # | ||
| 1506 | # USB Miscellaneous drivers | ||
| 1507 | # | ||
| 1508 | # CONFIG_USB_EMI62 is not set | ||
| 1509 | # CONFIG_USB_EMI26 is not set | ||
| 1510 | # CONFIG_USB_ADUTUX is not set | ||
| 1511 | # CONFIG_USB_SEVSEG is not set | ||
| 1512 | # CONFIG_USB_RIO500 is not set | ||
| 1513 | # CONFIG_USB_LEGOTOWER is not set | ||
| 1514 | # CONFIG_USB_LCD is not set | ||
| 1515 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 1516 | # CONFIG_USB_LED is not set | ||
| 1517 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 1518 | # CONFIG_USB_CYTHERM is not set | ||
| 1519 | # CONFIG_USB_PHIDGET is not set | ||
| 1520 | # CONFIG_USB_IDMOUSE is not set | ||
| 1521 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 1522 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 1523 | # CONFIG_USB_LD is not set | ||
| 1524 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 1525 | # CONFIG_USB_IOWARRIOR is not set | ||
| 1526 | # CONFIG_USB_TEST is not set | ||
| 1527 | # CONFIG_USB_ISIGHTFW is not set | ||
| 1528 | # CONFIG_USB_VST is not set | ||
| 1529 | CONFIG_USB_GADGET=y | ||
| 1530 | # CONFIG_USB_GADGET_DEBUG is not set | ||
| 1531 | # CONFIG_USB_GADGET_DEBUG_FILES is not set | ||
| 1532 | # CONFIG_USB_GADGET_DEBUG_FS is not set | ||
| 1533 | CONFIG_USB_GADGET_VBUS_DRAW=2 | ||
| 1534 | CONFIG_USB_GADGET_SELECTED=y | ||
| 1535 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 1536 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 1537 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 1538 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 1539 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 1540 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 1541 | # CONFIG_USB_GADGET_PXA27X is not set | ||
| 1542 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 1543 | # CONFIG_USB_GADGET_IMX is not set | ||
| 1544 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 1545 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 1546 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 1547 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 1548 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1549 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1550 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 1551 | CONFIG_USB_GADGET_DUALSPEED=y | ||
| 1552 | # CONFIG_USB_ZERO is not set | ||
| 1553 | CONFIG_USB_ETH=y | ||
| 1554 | CONFIG_USB_ETH_RNDIS=y | ||
| 1555 | # CONFIG_USB_GADGETFS is not set | ||
| 1556 | # CONFIG_USB_FILE_STORAGE is not set | ||
| 1557 | # CONFIG_USB_G_SERIAL is not set | ||
| 1558 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 1559 | # CONFIG_USB_G_PRINTER is not set | ||
| 1560 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
| 1561 | |||
| 1562 | # | ||
| 1563 | # OTG and related infrastructure | ||
| 1564 | # | ||
| 1565 | CONFIG_USB_OTG_UTILS=y | ||
| 1566 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1567 | # CONFIG_ISP1301_OMAP is not set | ||
| 1568 | CONFIG_TWL4030_USB=y | ||
| 1569 | CONFIG_MMC=y | ||
| 1570 | # CONFIG_MMC_DEBUG is not set | ||
| 1571 | CONFIG_MMC_UNSAFE_RESUME=y | ||
| 1572 | |||
| 1573 | # | ||
| 1574 | # MMC/SD/SDIO Card Drivers | ||
| 1575 | # | ||
| 1576 | CONFIG_MMC_BLOCK=y | ||
| 1577 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 1578 | CONFIG_SDIO_UART=y | ||
| 1579 | # CONFIG_MMC_TEST is not set | ||
| 1580 | |||
| 1581 | # | ||
| 1582 | # MMC/SD/SDIO Host Controller Drivers | ||
| 1583 | # | ||
| 1584 | # CONFIG_MMC_SDHCI is not set | ||
| 1585 | # CONFIG_MMC_OMAP is not set | ||
| 1586 | CONFIG_MMC_OMAP_HS=y | ||
| 1587 | # CONFIG_MMC_SPI is not set | ||
| 1588 | # CONFIG_MEMSTICK is not set | ||
| 1589 | # CONFIG_ACCESSIBILITY is not set | ||
| 1590 | CONFIG_NEW_LEDS=y | ||
| 1591 | CONFIG_LEDS_CLASS=y | ||
| 1592 | |||
| 1593 | # | ||
| 1594 | # LED drivers | ||
| 1595 | # | ||
| 1596 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1597 | CONFIG_LEDS_GPIO=y | ||
| 1598 | # CONFIG_LEDS_PCA955X is not set | ||
| 1599 | |||
| 1600 | # | ||
| 1601 | # LED Triggers | ||
| 1602 | # | ||
| 1603 | CONFIG_LEDS_TRIGGERS=y | ||
| 1604 | CONFIG_LEDS_TRIGGER_TIMER=y | ||
| 1605 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 1606 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 1607 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | ||
| 1608 | CONFIG_RTC_LIB=y | ||
| 1609 | CONFIG_RTC_CLASS=y | ||
| 1610 | CONFIG_RTC_HCTOSYS=y | ||
| 1611 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 1612 | # CONFIG_RTC_DEBUG is not set | ||
| 1613 | |||
| 1614 | # | ||
| 1615 | # RTC interfaces | ||
| 1616 | # | ||
| 1617 | CONFIG_RTC_INTF_SYSFS=y | ||
| 1618 | CONFIG_RTC_INTF_PROC=y | ||
| 1619 | CONFIG_RTC_INTF_DEV=y | ||
| 1620 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 1621 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1622 | |||
| 1623 | # | ||
| 1624 | # I2C RTC drivers | ||
| 1625 | # | ||
| 1626 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 1627 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 1628 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 1629 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 1630 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 1631 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 1632 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 1633 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 1634 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 1635 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 1636 | CONFIG_RTC_DRV_TWL4030=y | ||
| 1637 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1638 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1639 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1640 | |||
| 1641 | # | ||
| 1642 | # SPI RTC drivers | ||
| 1643 | # | ||
| 1644 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 1645 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1646 | # CONFIG_RTC_DRV_DS1390 is not set | ||
| 1647 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 1648 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1649 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1650 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1651 | |||
| 1652 | # | ||
| 1653 | # Platform RTC drivers | ||
| 1654 | # | ||
| 1655 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 1656 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1657 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1658 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1659 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1660 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1661 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1662 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1663 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1664 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1665 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 1666 | |||
| 1667 | # | ||
| 1668 | # on-CPU RTC drivers | ||
| 1669 | # | ||
| 1670 | # CONFIG_DMADEVICES is not set | ||
| 1671 | # CONFIG_REGULATOR is not set | ||
| 1672 | # CONFIG_UIO is not set | ||
| 1673 | # CONFIG_STAGING is not set | ||
| 1674 | |||
| 1675 | # | ||
| 1676 | # File systems | ||
| 1677 | # | ||
| 1678 | CONFIG_EXT2_FS=y | ||
| 1679 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 1680 | # CONFIG_EXT2_FS_XIP is not set | ||
| 1681 | CONFIG_EXT3_FS=y | ||
| 1682 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 1683 | # CONFIG_EXT4_FS is not set | ||
| 1684 | CONFIG_JBD=y | ||
| 1685 | # CONFIG_JBD_DEBUG is not set | ||
| 1686 | # CONFIG_REISERFS_FS is not set | ||
| 1687 | # CONFIG_JFS_FS is not set | ||
| 1688 | CONFIG_FS_POSIX_ACL=y | ||
| 1689 | CONFIG_FILE_LOCKING=y | ||
| 1690 | CONFIG_XFS_FS=m | ||
| 1691 | # CONFIG_XFS_QUOTA is not set | ||
| 1692 | # CONFIG_XFS_POSIX_ACL is not set | ||
| 1693 | # CONFIG_XFS_RT is not set | ||
| 1694 | # CONFIG_XFS_DEBUG is not set | ||
| 1695 | # CONFIG_GFS2_FS is not set | ||
| 1696 | # CONFIG_OCFS2_FS is not set | ||
| 1697 | # CONFIG_BTRFS_FS is not set | ||
| 1698 | CONFIG_DNOTIFY=y | ||
| 1699 | CONFIG_INOTIFY=y | ||
| 1700 | CONFIG_INOTIFY_USER=y | ||
| 1701 | CONFIG_QUOTA=y | ||
| 1702 | # CONFIG_QUOTA_NETLINK_INTERFACE is not set | ||
| 1703 | CONFIG_PRINT_QUOTA_WARNING=y | ||
| 1704 | CONFIG_QUOTA_TREE=y | ||
| 1705 | # CONFIG_QFMT_V1 is not set | ||
| 1706 | CONFIG_QFMT_V2=y | ||
| 1707 | CONFIG_QUOTACTL=y | ||
| 1708 | # CONFIG_AUTOFS_FS is not set | ||
| 1709 | # CONFIG_AUTOFS4_FS is not set | ||
| 1710 | CONFIG_FUSE_FS=m | ||
| 1711 | |||
| 1712 | # | ||
| 1713 | # CD-ROM/DVD Filesystems | ||
| 1714 | # | ||
| 1715 | CONFIG_ISO9660_FS=m | ||
| 1716 | CONFIG_JOLIET=y | ||
| 1717 | CONFIG_ZISOFS=y | ||
| 1718 | CONFIG_UDF_FS=m | ||
| 1719 | CONFIG_UDF_NLS=y | ||
| 1720 | |||
| 1721 | # | ||
| 1722 | # DOS/FAT/NT Filesystems | ||
| 1723 | # | ||
| 1724 | CONFIG_FAT_FS=y | ||
| 1725 | CONFIG_MSDOS_FS=y | ||
| 1726 | CONFIG_VFAT_FS=y | ||
| 1727 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1728 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1729 | # CONFIG_NTFS_FS is not set | ||
| 1730 | |||
| 1731 | # | ||
| 1732 | # Pseudo filesystems | ||
| 1733 | # | ||
| 1734 | CONFIG_PROC_FS=y | ||
| 1735 | CONFIG_PROC_SYSCTL=y | ||
| 1736 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1737 | CONFIG_SYSFS=y | ||
| 1738 | CONFIG_TMPFS=y | ||
| 1739 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1740 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1741 | # CONFIG_CONFIGFS_FS is not set | ||
| 1742 | CONFIG_MISC_FILESYSTEMS=y | ||
| 1743 | # CONFIG_ADFS_FS is not set | ||
| 1744 | # CONFIG_AFFS_FS is not set | ||
| 1745 | # CONFIG_HFS_FS is not set | ||
| 1746 | # CONFIG_HFSPLUS_FS is not set | ||
| 1747 | # CONFIG_BEFS_FS is not set | ||
| 1748 | # CONFIG_BFS_FS is not set | ||
| 1749 | # CONFIG_EFS_FS is not set | ||
| 1750 | CONFIG_JFFS2_FS=y | ||
| 1751 | CONFIG_JFFS2_FS_DEBUG=0 | ||
| 1752 | CONFIG_JFFS2_FS_WRITEBUFFER=y | ||
| 1753 | # CONFIG_JFFS2_FS_WBUF_VERIFY is not set | ||
| 1754 | CONFIG_JFFS2_SUMMARY=y | ||
| 1755 | CONFIG_JFFS2_FS_XATTR=y | ||
| 1756 | CONFIG_JFFS2_FS_POSIX_ACL=y | ||
| 1757 | CONFIG_JFFS2_FS_SECURITY=y | ||
| 1758 | CONFIG_JFFS2_COMPRESSION_OPTIONS=y | ||
| 1759 | CONFIG_JFFS2_ZLIB=y | ||
| 1760 | CONFIG_JFFS2_LZO=y | ||
| 1761 | CONFIG_JFFS2_RTIME=y | ||
| 1762 | CONFIG_JFFS2_RUBIN=y | ||
| 1763 | # CONFIG_JFFS2_CMODE_NONE is not set | ||
| 1764 | CONFIG_JFFS2_CMODE_PRIORITY=y | ||
| 1765 | # CONFIG_JFFS2_CMODE_SIZE is not set | ||
| 1766 | # CONFIG_JFFS2_CMODE_FAVOURLZO is not set | ||
| 1767 | # CONFIG_CRAMFS is not set | ||
| 1768 | # CONFIG_SQUASHFS is not set | ||
| 1769 | # CONFIG_VXFS_FS is not set | ||
| 1770 | # CONFIG_MINIX_FS is not set | ||
| 1771 | # CONFIG_OMFS_FS is not set | ||
| 1772 | # CONFIG_HPFS_FS is not set | ||
| 1773 | # CONFIG_QNX4FS_FS is not set | ||
| 1774 | # CONFIG_ROMFS_FS is not set | ||
| 1775 | # CONFIG_SYSV_FS is not set | ||
| 1776 | # CONFIG_UFS_FS is not set | ||
| 1777 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1778 | CONFIG_NFS_FS=y | ||
| 1779 | CONFIG_NFS_V3=y | ||
| 1780 | # CONFIG_NFS_V3_ACL is not set | ||
| 1781 | CONFIG_NFS_V4=y | ||
| 1782 | CONFIG_ROOT_NFS=y | ||
| 1783 | # CONFIG_NFSD is not set | ||
| 1784 | CONFIG_LOCKD=y | ||
| 1785 | CONFIG_LOCKD_V4=y | ||
| 1786 | CONFIG_EXPORTFS=m | ||
| 1787 | CONFIG_NFS_COMMON=y | ||
| 1788 | CONFIG_SUNRPC=y | ||
| 1789 | CONFIG_SUNRPC_GSS=y | ||
| 1790 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 1791 | CONFIG_RPCSEC_GSS_KRB5=y | ||
| 1792 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1793 | # CONFIG_SMB_FS is not set | ||
| 1794 | # CONFIG_CIFS is not set | ||
| 1795 | # CONFIG_NCP_FS is not set | ||
| 1796 | # CONFIG_CODA_FS is not set | ||
| 1797 | # CONFIG_AFS_FS is not set | ||
| 1798 | |||
| 1799 | # | ||
| 1800 | # Partition Types | ||
| 1801 | # | ||
| 1802 | CONFIG_PARTITION_ADVANCED=y | ||
| 1803 | # CONFIG_ACORN_PARTITION is not set | ||
| 1804 | # CONFIG_OSF_PARTITION is not set | ||
| 1805 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1806 | # CONFIG_ATARI_PARTITION is not set | ||
| 1807 | # CONFIG_MAC_PARTITION is not set | ||
| 1808 | CONFIG_MSDOS_PARTITION=y | ||
| 1809 | # CONFIG_BSD_DISKLABEL is not set | ||
| 1810 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 1811 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 1812 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 1813 | # CONFIG_LDM_PARTITION is not set | ||
| 1814 | # CONFIG_SGI_PARTITION is not set | ||
| 1815 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1816 | # CONFIG_SUN_PARTITION is not set | ||
| 1817 | # CONFIG_KARMA_PARTITION is not set | ||
| 1818 | # CONFIG_EFI_PARTITION is not set | ||
| 1819 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1820 | CONFIG_NLS=y | ||
| 1821 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1822 | CONFIG_NLS_CODEPAGE_437=y | ||
| 1823 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1824 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1825 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1826 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1827 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1828 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1829 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1830 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1831 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1832 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1833 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1834 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1835 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1836 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1837 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1838 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1839 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1840 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1841 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1842 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1843 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1844 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1845 | # CONFIG_NLS_ASCII is not set | ||
| 1846 | CONFIG_NLS_ISO8859_1=y | ||
| 1847 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1848 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1849 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1850 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1851 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1852 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1853 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1854 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1855 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1856 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1857 | # CONFIG_NLS_KOI8_R is not set | ||
| 1858 | # CONFIG_NLS_KOI8_U is not set | ||
| 1859 | # CONFIG_NLS_UTF8 is not set | ||
| 1860 | # CONFIG_DLM is not set | ||
| 1861 | |||
| 1862 | # | ||
| 1863 | # Kernel hacking | ||
| 1864 | # | ||
| 1865 | # CONFIG_PRINTK_TIME is not set | ||
| 1866 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1867 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1868 | CONFIG_FRAME_WARN=1024 | ||
| 1869 | CONFIG_MAGIC_SYSRQ=y | ||
| 1870 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1871 | CONFIG_DEBUG_FS=y | ||
| 1872 | # CONFIG_HEADERS_CHECK is not set | ||
| 1873 | CONFIG_DEBUG_KERNEL=y | ||
| 1874 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1875 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1876 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1877 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1878 | CONFIG_SCHED_DEBUG=y | ||
| 1879 | CONFIG_SCHEDSTATS=y | ||
| 1880 | CONFIG_TIMER_STATS=y | ||
| 1881 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1882 | # CONFIG_SLUB_DEBUG_ON is not set | ||
| 1883 | # CONFIG_SLUB_STATS is not set | ||
| 1884 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1885 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1886 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 1887 | CONFIG_DEBUG_MUTEXES=y | ||
| 1888 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1889 | # CONFIG_PROVE_LOCKING is not set | ||
| 1890 | # CONFIG_LOCK_STAT is not set | ||
| 1891 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 1892 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1893 | CONFIG_STACKTRACE=y | ||
| 1894 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1895 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 1896 | # CONFIG_DEBUG_INFO is not set | ||
| 1897 | # CONFIG_DEBUG_VM is not set | ||
| 1898 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1899 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1900 | # CONFIG_DEBUG_LIST is not set | ||
| 1901 | # CONFIG_DEBUG_SG is not set | ||
| 1902 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1903 | CONFIG_FRAME_POINTER=y | ||
| 1904 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1905 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1906 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1907 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1908 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1909 | # CONFIG_FAULT_INJECTION is not set | ||
| 1910 | # CONFIG_LATENCYTOP is not set | ||
| 1911 | CONFIG_NOP_TRACER=y | ||
| 1912 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1913 | CONFIG_RING_BUFFER=y | ||
| 1914 | CONFIG_TRACING=y | ||
| 1915 | |||
| 1916 | # | ||
| 1917 | # Tracers | ||
| 1918 | # | ||
| 1919 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1920 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1921 | # CONFIG_SCHED_TRACER is not set | ||
| 1922 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1923 | # CONFIG_BOOT_TRACER is not set | ||
| 1924 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1925 | # CONFIG_STACK_TRACER is not set | ||
| 1926 | # CONFIG_FTRACE_STARTUP_TEST is not set | ||
| 1927 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1928 | # CONFIG_SAMPLES is not set | ||
| 1929 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1930 | # CONFIG_KGDB is not set | ||
| 1931 | # CONFIG_DEBUG_USER is not set | ||
| 1932 | # CONFIG_DEBUG_ERRORS is not set | ||
| 1933 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1934 | # CONFIG_DEBUG_LL is not set | ||
| 1935 | |||
| 1936 | # | ||
| 1937 | # Security options | ||
| 1938 | # | ||
| 1939 | # CONFIG_KEYS is not set | ||
| 1940 | # CONFIG_SECURITY is not set | ||
| 1941 | # CONFIG_SECURITYFS is not set | ||
| 1942 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1943 | CONFIG_XOR_BLOCKS=m | ||
| 1944 | CONFIG_ASYNC_CORE=m | ||
| 1945 | CONFIG_ASYNC_MEMCPY=m | ||
| 1946 | CONFIG_ASYNC_XOR=m | ||
| 1947 | CONFIG_CRYPTO=y | ||
| 1948 | |||
| 1949 | # | ||
| 1950 | # Crypto core or helper | ||
| 1951 | # | ||
| 1952 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1953 | CONFIG_CRYPTO_ALGAPI=y | ||
| 1954 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1955 | CONFIG_CRYPTO_AEAD2=y | ||
| 1956 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 1957 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1958 | CONFIG_CRYPTO_HASH=y | ||
| 1959 | CONFIG_CRYPTO_HASH2=y | ||
| 1960 | CONFIG_CRYPTO_RNG2=y | ||
| 1961 | CONFIG_CRYPTO_MANAGER=y | ||
| 1962 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1963 | CONFIG_CRYPTO_GF128MUL=m | ||
| 1964 | CONFIG_CRYPTO_NULL=m | ||
| 1965 | CONFIG_CRYPTO_CRYPTD=m | ||
| 1966 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1967 | CONFIG_CRYPTO_TEST=m | ||
| 1968 | |||
| 1969 | # | ||
| 1970 | # Authenticated Encryption with Associated Data | ||
| 1971 | # | ||
| 1972 | # CONFIG_CRYPTO_CCM is not set | ||
| 1973 | # CONFIG_CRYPTO_GCM is not set | ||
| 1974 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1975 | |||
| 1976 | # | ||
| 1977 | # Block modes | ||
| 1978 | # | ||
| 1979 | CONFIG_CRYPTO_CBC=y | ||
| 1980 | # CONFIG_CRYPTO_CTR is not set | ||
| 1981 | # CONFIG_CRYPTO_CTS is not set | ||
| 1982 | CONFIG_CRYPTO_ECB=y | ||
| 1983 | CONFIG_CRYPTO_LRW=m | ||
| 1984 | CONFIG_CRYPTO_PCBC=m | ||
| 1985 | # CONFIG_CRYPTO_XTS is not set | ||
| 1986 | |||
| 1987 | # | ||
| 1988 | # Hash modes | ||
| 1989 | # | ||
| 1990 | CONFIG_CRYPTO_HMAC=m | ||
| 1991 | CONFIG_CRYPTO_XCBC=m | ||
| 1992 | |||
| 1993 | # | ||
| 1994 | # Digest | ||
| 1995 | # | ||
| 1996 | CONFIG_CRYPTO_CRC32C=y | ||
| 1997 | CONFIG_CRYPTO_MD4=m | ||
| 1998 | CONFIG_CRYPTO_MD5=y | ||
| 1999 | CONFIG_CRYPTO_MICHAEL_MIC=y | ||
| 2000 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 2001 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 2002 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 2003 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 2004 | CONFIG_CRYPTO_SHA1=m | ||
| 2005 | CONFIG_CRYPTO_SHA256=m | ||
| 2006 | CONFIG_CRYPTO_SHA512=m | ||
| 2007 | CONFIG_CRYPTO_TGR192=m | ||
| 2008 | CONFIG_CRYPTO_WP512=m | ||
| 2009 | |||
| 2010 | # | ||
| 2011 | # Ciphers | ||
| 2012 | # | ||
| 2013 | CONFIG_CRYPTO_AES=y | ||
| 2014 | CONFIG_CRYPTO_ANUBIS=m | ||
| 2015 | CONFIG_CRYPTO_ARC4=y | ||
| 2016 | CONFIG_CRYPTO_BLOWFISH=m | ||
| 2017 | CONFIG_CRYPTO_CAMELLIA=m | ||
| 2018 | CONFIG_CRYPTO_CAST5=m | ||
| 2019 | CONFIG_CRYPTO_CAST6=m | ||
| 2020 | CONFIG_CRYPTO_DES=y | ||
| 2021 | CONFIG_CRYPTO_FCRYPT=m | ||
| 2022 | CONFIG_CRYPTO_KHAZAD=m | ||
| 2023 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 2024 | # CONFIG_CRYPTO_SEED is not set | ||
| 2025 | CONFIG_CRYPTO_SERPENT=m | ||
| 2026 | CONFIG_CRYPTO_TEA=m | ||
| 2027 | CONFIG_CRYPTO_TWOFISH=m | ||
| 2028 | CONFIG_CRYPTO_TWOFISH_COMMON=m | ||
| 2029 | |||
| 2030 | # | ||
| 2031 | # Compression | ||
| 2032 | # | ||
| 2033 | CONFIG_CRYPTO_DEFLATE=m | ||
| 2034 | # CONFIG_CRYPTO_LZO is not set | ||
| 2035 | |||
| 2036 | # | ||
| 2037 | # Random Number Generation | ||
| 2038 | # | ||
| 2039 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 2040 | CONFIG_CRYPTO_HW=y | ||
| 2041 | |||
| 2042 | # | ||
| 2043 | # Library routines | ||
| 2044 | # | ||
| 2045 | CONFIG_BITREVERSE=y | ||
| 2046 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 2047 | CONFIG_CRC_CCITT=y | ||
| 2048 | CONFIG_CRC16=m | ||
| 2049 | CONFIG_CRC_T10DIF=y | ||
| 2050 | CONFIG_CRC_ITU_T=y | ||
| 2051 | CONFIG_CRC32=y | ||
| 2052 | CONFIG_CRC7=y | ||
| 2053 | CONFIG_LIBCRC32C=y | ||
| 2054 | CONFIG_ZLIB_INFLATE=y | ||
| 2055 | CONFIG_ZLIB_DEFLATE=y | ||
| 2056 | CONFIG_LZO_COMPRESS=y | ||
| 2057 | CONFIG_LZO_DECOMPRESS=y | ||
| 2058 | CONFIG_PLIST=y | ||
| 2059 | CONFIG_HAS_IOMEM=y | ||
| 2060 | CONFIG_HAS_IOPORT=y | ||
| 2061 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig index a8ee6984a09e..020e6a8a9e5c 100644 --- a/arch/arm/configs/orion5x_defconfig +++ b/arch/arm/configs/orion5x_defconfig | |||
| @@ -481,7 +481,7 @@ CONFIG_MTD_NAND_IDS=y | |||
| 481 | # CONFIG_MTD_NAND_DISKONCHIP is not set | 481 | # CONFIG_MTD_NAND_DISKONCHIP is not set |
| 482 | # CONFIG_MTD_NAND_CAFE is not set | 482 | # CONFIG_MTD_NAND_CAFE is not set |
| 483 | # CONFIG_MTD_NAND_NANDSIM is not set | 483 | # CONFIG_MTD_NAND_NANDSIM is not set |
| 484 | # CONFIG_MTD_NAND_PLATFORM is not set | 484 | CONFIG_MTD_NAND_PLATFORM=y |
| 485 | # CONFIG_MTD_ALAUDA is not set | 485 | # CONFIG_MTD_ALAUDA is not set |
| 486 | CONFIG_MTD_NAND_ORION=y | 486 | CONFIG_MTD_NAND_ORION=y |
| 487 | # CONFIG_MTD_ONENAND is not set | 487 | # CONFIG_MTD_ONENAND is not set |
| @@ -1177,7 +1177,7 @@ CONFIG_RTC_DRV_S35390A=y | |||
| 1177 | # CONFIG_RTC_DRV_DS1553 is not set | 1177 | # CONFIG_RTC_DRV_DS1553 is not set |
| 1178 | # CONFIG_RTC_DRV_DS1742 is not set | 1178 | # CONFIG_RTC_DRV_DS1742 is not set |
| 1179 | # CONFIG_RTC_DRV_STK17TA8 is not set | 1179 | # CONFIG_RTC_DRV_STK17TA8 is not set |
| 1180 | # CONFIG_RTC_DRV_M48T86 is not set | 1180 | CONFIG_RTC_DRV_M48T86=y |
| 1181 | # CONFIG_RTC_DRV_M48T59 is not set | 1181 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1182 | # CONFIG_RTC_DRV_V3020 is not set | 1182 | # CONFIG_RTC_DRV_V3020 is not set |
| 1183 | 1183 | ||
diff --git a/arch/arm/configs/pleb_defconfig b/arch/arm/configs/pleb_defconfig index a6b47ea8e465..f2d2dda25949 100644 --- a/arch/arm/configs/pleb_defconfig +++ b/arch/arm/configs/pleb_defconfig | |||
| @@ -88,7 +88,6 @@ CONFIG_ARCH_SA1100=y | |||
| 88 | # CONFIG_SA1100_COLLIE is not set | 88 | # CONFIG_SA1100_COLLIE is not set |
| 89 | # CONFIG_SA1100_H3100 is not set | 89 | # CONFIG_SA1100_H3100 is not set |
| 90 | # CONFIG_SA1100_H3600 is not set | 90 | # CONFIG_SA1100_H3600 is not set |
| 91 | # CONFIG_SA1100_H3800 is not set | ||
| 92 | # CONFIG_SA1100_BADGE4 is not set | 91 | # CONFIG_SA1100_BADGE4 is not set |
| 93 | # CONFIG_SA1100_JORNADA720 is not set | 92 | # CONFIG_SA1100_JORNADA720 is not set |
| 94 | # CONFIG_SA1100_HACKKIT is not set | 93 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/configs/pxa168_defconfig b/arch/arm/configs/pxa168_defconfig new file mode 100644 index 000000000000..db5faeaec96c --- /dev/null +++ b/arch/arm/configs/pxa168_defconfig | |||
| @@ -0,0 +1,891 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.29-rc3 | ||
| 4 | # Fri Mar 20 13:43:13 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 26 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 28 | |||
| 29 | # | ||
| 30 | # General setup | ||
| 31 | # | ||
| 32 | CONFIG_EXPERIMENTAL=y | ||
| 33 | CONFIG_BROKEN_ON_SMP=y | ||
| 34 | CONFIG_LOCK_KERNEL=y | ||
| 35 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 36 | CONFIG_LOCALVERSION="" | ||
| 37 | CONFIG_LOCALVERSION_AUTO=y | ||
| 38 | CONFIG_SWAP=y | ||
| 39 | CONFIG_SYSVIPC=y | ||
| 40 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 41 | # CONFIG_POSIX_MQUEUE is not set | ||
| 42 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 43 | # CONFIG_TASKSTATS is not set | ||
| 44 | # CONFIG_AUDIT is not set | ||
| 45 | |||
| 46 | # | ||
| 47 | # RCU Subsystem | ||
| 48 | # | ||
| 49 | CONFIG_CLASSIC_RCU=y | ||
| 50 | # CONFIG_TREE_RCU is not set | ||
| 51 | # CONFIG_PREEMPT_RCU is not set | ||
| 52 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 53 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 54 | # CONFIG_IKCONFIG is not set | ||
| 55 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 56 | # CONFIG_GROUP_SCHED is not set | ||
| 57 | # CONFIG_CGROUPS is not set | ||
| 58 | CONFIG_SYSFS_DEPRECATED=y | ||
| 59 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 60 | # CONFIG_RELAY is not set | ||
| 61 | CONFIG_NAMESPACES=y | ||
| 62 | # CONFIG_UTS_NS is not set | ||
| 63 | # CONFIG_IPC_NS is not set | ||
| 64 | # CONFIG_USER_NS is not set | ||
| 65 | # CONFIG_PID_NS is not set | ||
| 66 | # CONFIG_NET_NS is not set | ||
| 67 | CONFIG_BLK_DEV_INITRD=y | ||
| 68 | CONFIG_INITRAMFS_SOURCE="" | ||
| 69 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 70 | CONFIG_SYSCTL=y | ||
| 71 | # CONFIG_EMBEDDED is not set | ||
| 72 | CONFIG_UID16=y | ||
| 73 | CONFIG_SYSCTL_SYSCALL=y | ||
| 74 | CONFIG_KALLSYMS=y | ||
| 75 | # CONFIG_KALLSYMS_ALL is not set | ||
| 76 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 77 | CONFIG_HOTPLUG=y | ||
| 78 | CONFIG_PRINTK=y | ||
| 79 | CONFIG_BUG=y | ||
| 80 | CONFIG_ELF_CORE=y | ||
| 81 | CONFIG_COMPAT_BRK=y | ||
| 82 | CONFIG_BASE_FULL=y | ||
| 83 | CONFIG_FUTEX=y | ||
| 84 | CONFIG_ANON_INODES=y | ||
| 85 | CONFIG_EPOLL=y | ||
| 86 | CONFIG_SIGNALFD=y | ||
| 87 | CONFIG_TIMERFD=y | ||
| 88 | CONFIG_EVENTFD=y | ||
| 89 | CONFIG_SHMEM=y | ||
| 90 | CONFIG_AIO=y | ||
| 91 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 92 | CONFIG_SLAB=y | ||
| 93 | # CONFIG_SLUB is not set | ||
| 94 | # CONFIG_SLOB is not set | ||
| 95 | # CONFIG_PROFILING is not set | ||
| 96 | CONFIG_HAVE_OPROFILE=y | ||
| 97 | # CONFIG_KPROBES is not set | ||
| 98 | CONFIG_HAVE_KPROBES=y | ||
| 99 | CONFIG_HAVE_KRETPROBES=y | ||
| 100 | CONFIG_HAVE_CLK=y | ||
| 101 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 102 | CONFIG_SLABINFO=y | ||
| 103 | CONFIG_RT_MUTEXES=y | ||
| 104 | CONFIG_BASE_SMALL=0 | ||
| 105 | CONFIG_MODULES=y | ||
| 106 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 107 | CONFIG_MODULE_UNLOAD=y | ||
| 108 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 109 | # CONFIG_MODVERSIONS is not set | ||
| 110 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 111 | CONFIG_BLOCK=y | ||
| 112 | # CONFIG_LBD is not set | ||
| 113 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 114 | # CONFIG_BLK_DEV_BSG is not set | ||
| 115 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 116 | |||
| 117 | # | ||
| 118 | # IO Schedulers | ||
| 119 | # | ||
| 120 | CONFIG_IOSCHED_NOOP=y | ||
| 121 | CONFIG_IOSCHED_AS=y | ||
| 122 | CONFIG_IOSCHED_DEADLINE=y | ||
| 123 | CONFIG_IOSCHED_CFQ=y | ||
| 124 | # CONFIG_DEFAULT_AS is not set | ||
| 125 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 126 | CONFIG_DEFAULT_CFQ=y | ||
| 127 | # CONFIG_DEFAULT_NOOP is not set | ||
| 128 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 129 | # CONFIG_FREEZER is not set | ||
| 130 | |||
| 131 | # | ||
| 132 | # System Type | ||
| 133 | # | ||
| 134 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 135 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 136 | # CONFIG_ARCH_REALVIEW is not set | ||
| 137 | # CONFIG_ARCH_VERSATILE is not set | ||
| 138 | # CONFIG_ARCH_AT91 is not set | ||
| 139 | # CONFIG_ARCH_CLPS711X is not set | ||
| 140 | # CONFIG_ARCH_EBSA110 is not set | ||
| 141 | # CONFIG_ARCH_EP93XX is not set | ||
| 142 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 143 | # CONFIG_ARCH_NETX is not set | ||
| 144 | # CONFIG_ARCH_H720X is not set | ||
| 145 | # CONFIG_ARCH_IMX is not set | ||
| 146 | # CONFIG_ARCH_IOP13XX is not set | ||
| 147 | # CONFIG_ARCH_IOP32X is not set | ||
| 148 | # CONFIG_ARCH_IOP33X is not set | ||
| 149 | # CONFIG_ARCH_IXP23XX is not set | ||
| 150 | # CONFIG_ARCH_IXP2000 is not set | ||
| 151 | # CONFIG_ARCH_IXP4XX is not set | ||
| 152 | # CONFIG_ARCH_L7200 is not set | ||
| 153 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 154 | # CONFIG_ARCH_KS8695 is not set | ||
| 155 | # CONFIG_ARCH_NS9XXX is not set | ||
| 156 | # CONFIG_ARCH_LOKI is not set | ||
| 157 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 158 | # CONFIG_ARCH_MXC is not set | ||
| 159 | # CONFIG_ARCH_ORION5X is not set | ||
| 160 | # CONFIG_ARCH_PNX4008 is not set | ||
| 161 | # CONFIG_ARCH_PXA is not set | ||
| 162 | CONFIG_ARCH_MMP=y | ||
| 163 | # CONFIG_ARCH_RPC is not set | ||
| 164 | # CONFIG_ARCH_SA1100 is not set | ||
| 165 | # CONFIG_ARCH_S3C2410 is not set | ||
| 166 | # CONFIG_ARCH_S3C64XX is not set | ||
| 167 | # CONFIG_ARCH_SHARK is not set | ||
| 168 | # CONFIG_ARCH_LH7A40X is not set | ||
| 169 | # CONFIG_ARCH_DAVINCI is not set | ||
| 170 | # CONFIG_ARCH_OMAP is not set | ||
| 171 | # CONFIG_ARCH_MSM is not set | ||
| 172 | # CONFIG_ARCH_W90X900 is not set | ||
| 173 | # CONFIG_MACH_TAVOREVB is not set | ||
| 174 | |||
| 175 | # | ||
| 176 | # Marvell PXA168/910 Implmentations | ||
| 177 | # | ||
| 178 | CONFIG_MACH_ASPENITE=y | ||
| 179 | CONFIG_MACH_ZYLONITE2=y | ||
| 180 | # CONFIG_MACH_TTC_DKB is not set | ||
| 181 | CONFIG_CPU_PXA168=y | ||
| 182 | CONFIG_PLAT_PXA=y | ||
| 183 | |||
| 184 | # | ||
| 185 | # Processor Type | ||
| 186 | # | ||
| 187 | CONFIG_CPU_32=y | ||
| 188 | CONFIG_CPU_MOHAWK=y | ||
| 189 | CONFIG_CPU_32v5=y | ||
| 190 | CONFIG_CPU_ABRT_EV5T=y | ||
| 191 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 192 | CONFIG_CPU_CACHE_VIVT=y | ||
| 193 | CONFIG_CPU_COPY_V4WB=y | ||
| 194 | CONFIG_CPU_TLB_V4WBI=y | ||
| 195 | CONFIG_CPU_CP15=y | ||
| 196 | CONFIG_CPU_CP15_MMU=y | ||
| 197 | |||
| 198 | # | ||
| 199 | # Processor Features | ||
| 200 | # | ||
| 201 | CONFIG_ARM_THUMB=y | ||
| 202 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 203 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 204 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
| 205 | # CONFIG_OUTER_CACHE is not set | ||
| 206 | CONFIG_IWMMXT=y | ||
| 207 | CONFIG_COMMON_CLKDEV=y | ||
| 208 | |||
| 209 | # | ||
| 210 | # Bus support | ||
| 211 | # | ||
| 212 | # CONFIG_PCI_SYSCALL is not set | ||
| 213 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 214 | # CONFIG_PCCARD is not set | ||
| 215 | |||
| 216 | # | ||
| 217 | # Kernel Features | ||
| 218 | # | ||
| 219 | CONFIG_TICK_ONESHOT=y | ||
| 220 | CONFIG_NO_HZ=y | ||
| 221 | CONFIG_HIGH_RES_TIMERS=y | ||
| 222 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 223 | CONFIG_VMSPLIT_3G=y | ||
| 224 | # CONFIG_VMSPLIT_2G is not set | ||
| 225 | # CONFIG_VMSPLIT_1G is not set | ||
| 226 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 227 | CONFIG_PREEMPT=y | ||
| 228 | CONFIG_HZ=100 | ||
| 229 | CONFIG_AEABI=y | ||
| 230 | CONFIG_OABI_COMPAT=y | ||
| 231 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 232 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 233 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 234 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 235 | CONFIG_FLATMEM_MANUAL=y | ||
| 236 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 237 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 238 | CONFIG_FLATMEM=y | ||
| 239 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 240 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 241 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 242 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 243 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 244 | CONFIG_VIRT_TO_BUS=y | ||
| 245 | CONFIG_UNEVICTABLE_LRU=y | ||
| 246 | CONFIG_ALIGNMENT_TRAP=y | ||
| 247 | |||
| 248 | # | ||
| 249 | # Boot options | ||
| 250 | # | ||
| 251 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 252 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 253 | CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M" | ||
| 254 | # CONFIG_XIP_KERNEL is not set | ||
| 255 | # CONFIG_KEXEC is not set | ||
| 256 | |||
| 257 | # | ||
| 258 | # CPU Power Management | ||
| 259 | # | ||
| 260 | # CONFIG_CPU_IDLE is not set | ||
| 261 | |||
| 262 | # | ||
| 263 | # Floating point emulation | ||
| 264 | # | ||
| 265 | |||
| 266 | # | ||
| 267 | # At least one emulation must be selected | ||
| 268 | # | ||
| 269 | CONFIG_FPE_NWFPE=y | ||
| 270 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 271 | # CONFIG_FPE_FASTFPE is not set | ||
| 272 | |||
| 273 | # | ||
| 274 | # Userspace binary formats | ||
| 275 | # | ||
| 276 | CONFIG_BINFMT_ELF=y | ||
| 277 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 278 | CONFIG_HAVE_AOUT=y | ||
| 279 | # CONFIG_BINFMT_AOUT is not set | ||
| 280 | # CONFIG_BINFMT_MISC is not set | ||
| 281 | |||
| 282 | # | ||
| 283 | # Power management options | ||
| 284 | # | ||
| 285 | # CONFIG_PM is not set | ||
| 286 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 287 | CONFIG_NET=y | ||
| 288 | |||
| 289 | # | ||
| 290 | # Networking options | ||
| 291 | # | ||
| 292 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 293 | CONFIG_PACKET=y | ||
| 294 | # CONFIG_PACKET_MMAP is not set | ||
| 295 | CONFIG_UNIX=y | ||
| 296 | CONFIG_XFRM=y | ||
| 297 | # CONFIG_XFRM_USER is not set | ||
| 298 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 299 | # CONFIG_XFRM_MIGRATE is not set | ||
| 300 | # CONFIG_XFRM_STATISTICS is not set | ||
| 301 | # CONFIG_NET_KEY is not set | ||
| 302 | CONFIG_INET=y | ||
| 303 | # CONFIG_IP_MULTICAST is not set | ||
| 304 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 305 | CONFIG_IP_FIB_HASH=y | ||
| 306 | CONFIG_IP_PNP=y | ||
| 307 | # CONFIG_IP_PNP_DHCP is not set | ||
| 308 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 309 | # CONFIG_IP_PNP_RARP is not set | ||
| 310 | # CONFIG_NET_IPIP is not set | ||
| 311 | # CONFIG_NET_IPGRE is not set | ||
| 312 | # CONFIG_ARPD is not set | ||
| 313 | # CONFIG_SYN_COOKIES is not set | ||
| 314 | # CONFIG_INET_AH is not set | ||
| 315 | # CONFIG_INET_ESP is not set | ||
| 316 | # CONFIG_INET_IPCOMP is not set | ||
| 317 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 318 | # CONFIG_INET_TUNNEL is not set | ||
| 319 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 320 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 321 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 322 | # CONFIG_INET_LRO is not set | ||
| 323 | CONFIG_INET_DIAG=y | ||
| 324 | CONFIG_INET_TCP_DIAG=y | ||
| 325 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 326 | CONFIG_TCP_CONG_CUBIC=y | ||
| 327 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 328 | # CONFIG_TCP_MD5SIG is not set | ||
| 329 | # CONFIG_IPV6 is not set | ||
| 330 | # CONFIG_NETWORK_SECMARK is not set | ||
| 331 | # CONFIG_NETFILTER is not set | ||
| 332 | # CONFIG_IP_DCCP is not set | ||
| 333 | # CONFIG_IP_SCTP is not set | ||
| 334 | # CONFIG_TIPC is not set | ||
| 335 | # CONFIG_ATM is not set | ||
| 336 | # CONFIG_BRIDGE is not set | ||
| 337 | # CONFIG_NET_DSA is not set | ||
| 338 | # CONFIG_VLAN_8021Q is not set | ||
| 339 | # CONFIG_DECNET is not set | ||
| 340 | # CONFIG_LLC2 is not set | ||
| 341 | # CONFIG_IPX is not set | ||
| 342 | # CONFIG_ATALK is not set | ||
| 343 | # CONFIG_X25 is not set | ||
| 344 | # CONFIG_LAPB is not set | ||
| 345 | # CONFIG_ECONET is not set | ||
| 346 | # CONFIG_WAN_ROUTER is not set | ||
| 347 | # CONFIG_NET_SCHED is not set | ||
| 348 | # CONFIG_DCB is not set | ||
| 349 | |||
| 350 | # | ||
| 351 | # Network testing | ||
| 352 | # | ||
| 353 | # CONFIG_NET_PKTGEN is not set | ||
| 354 | # CONFIG_HAMRADIO is not set | ||
| 355 | # CONFIG_CAN is not set | ||
| 356 | # CONFIG_IRDA is not set | ||
| 357 | # CONFIG_BT is not set | ||
| 358 | # CONFIG_AF_RXRPC is not set | ||
| 359 | # CONFIG_PHONET is not set | ||
| 360 | CONFIG_WIRELESS=y | ||
| 361 | # CONFIG_CFG80211 is not set | ||
| 362 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 363 | # CONFIG_WIRELESS_EXT is not set | ||
| 364 | # CONFIG_LIB80211 is not set | ||
| 365 | # CONFIG_MAC80211 is not set | ||
| 366 | # CONFIG_WIMAX is not set | ||
| 367 | # CONFIG_RFKILL is not set | ||
| 368 | # CONFIG_NET_9P is not set | ||
| 369 | |||
| 370 | # | ||
| 371 | # Device Drivers | ||
| 372 | # | ||
| 373 | |||
| 374 | # | ||
| 375 | # Generic Driver Options | ||
| 376 | # | ||
| 377 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 378 | # CONFIG_STANDALONE is not set | ||
| 379 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | ||
| 380 | CONFIG_FW_LOADER=y | ||
| 381 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 382 | CONFIG_EXTRA_FIRMWARE="" | ||
| 383 | # CONFIG_DEBUG_DRIVER is not set | ||
| 384 | # CONFIG_DEBUG_DEVRES is not set | ||
| 385 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 386 | # CONFIG_CONNECTOR is not set | ||
| 387 | # CONFIG_MTD is not set | ||
| 388 | # CONFIG_PARPORT is not set | ||
| 389 | # CONFIG_BLK_DEV is not set | ||
| 390 | # CONFIG_MISC_DEVICES is not set | ||
| 391 | CONFIG_HAVE_IDE=y | ||
| 392 | # CONFIG_IDE is not set | ||
| 393 | |||
| 394 | # | ||
| 395 | # SCSI device support | ||
| 396 | # | ||
| 397 | # CONFIG_RAID_ATTRS is not set | ||
| 398 | # CONFIG_SCSI is not set | ||
| 399 | # CONFIG_SCSI_DMA is not set | ||
| 400 | # CONFIG_SCSI_NETLINK is not set | ||
| 401 | # CONFIG_ATA is not set | ||
| 402 | # CONFIG_MD is not set | ||
| 403 | CONFIG_NETDEVICES=y | ||
| 404 | # CONFIG_DUMMY is not set | ||
| 405 | # CONFIG_BONDING is not set | ||
| 406 | # CONFIG_MACVLAN is not set | ||
| 407 | # CONFIG_EQUALIZER is not set | ||
| 408 | # CONFIG_TUN is not set | ||
| 409 | # CONFIG_VETH is not set | ||
| 410 | # CONFIG_PHYLIB is not set | ||
| 411 | CONFIG_NET_ETHERNET=y | ||
| 412 | CONFIG_MII=y | ||
| 413 | # CONFIG_AX88796 is not set | ||
| 414 | CONFIG_SMC91X=y | ||
| 415 | # CONFIG_DM9000 is not set | ||
| 416 | # CONFIG_SMC911X is not set | ||
| 417 | # CONFIG_SMSC911X is not set | ||
| 418 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 419 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 420 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 421 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 422 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 423 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 424 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 425 | # CONFIG_B44 is not set | ||
| 426 | # CONFIG_NETDEV_1000 is not set | ||
| 427 | # CONFIG_NETDEV_10000 is not set | ||
| 428 | |||
| 429 | # | ||
| 430 | # Wireless LAN | ||
| 431 | # | ||
| 432 | # CONFIG_WLAN_PRE80211 is not set | ||
| 433 | # CONFIG_WLAN_80211 is not set | ||
| 434 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 435 | |||
| 436 | # | ||
| 437 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 438 | # | ||
| 439 | # CONFIG_WAN is not set | ||
| 440 | # CONFIG_PPP is not set | ||
| 441 | # CONFIG_SLIP is not set | ||
| 442 | # CONFIG_NETCONSOLE is not set | ||
| 443 | # CONFIG_NETPOLL is not set | ||
| 444 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 445 | # CONFIG_ISDN is not set | ||
| 446 | |||
| 447 | # | ||
| 448 | # Input device support | ||
| 449 | # | ||
| 450 | CONFIG_INPUT=y | ||
| 451 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 452 | # CONFIG_INPUT_POLLDEV is not set | ||
| 453 | |||
| 454 | # | ||
| 455 | # Userland interfaces | ||
| 456 | # | ||
| 457 | CONFIG_INPUT_MOUSEDEV=y | ||
| 458 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 459 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 460 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 461 | # CONFIG_INPUT_JOYDEV is not set | ||
| 462 | # CONFIG_INPUT_EVDEV is not set | ||
| 463 | # CONFIG_INPUT_EVBUG is not set | ||
| 464 | |||
| 465 | # | ||
| 466 | # Input Device Drivers | ||
| 467 | # | ||
| 468 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 469 | # CONFIG_INPUT_MOUSE is not set | ||
| 470 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 471 | # CONFIG_INPUT_TABLET is not set | ||
| 472 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 473 | # CONFIG_INPUT_MISC is not set | ||
| 474 | |||
| 475 | # | ||
| 476 | # Hardware I/O ports | ||
| 477 | # | ||
| 478 | # CONFIG_SERIO is not set | ||
| 479 | # CONFIG_GAMEPORT is not set | ||
| 480 | |||
| 481 | # | ||
| 482 | # Character devices | ||
| 483 | # | ||
| 484 | CONFIG_VT=y | ||
| 485 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 486 | CONFIG_VT_CONSOLE=y | ||
| 487 | CONFIG_HW_CONSOLE=y | ||
| 488 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 489 | CONFIG_DEVKMEM=y | ||
| 490 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 491 | |||
| 492 | # | ||
| 493 | # Serial drivers | ||
| 494 | # | ||
| 495 | # CONFIG_SERIAL_8250 is not set | ||
| 496 | |||
| 497 | # | ||
| 498 | # Non-8250 serial port support | ||
| 499 | # | ||
| 500 | CONFIG_SERIAL_PXA=y | ||
| 501 | CONFIG_SERIAL_PXA_CONSOLE=y | ||
| 502 | CONFIG_SERIAL_CORE=y | ||
| 503 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 504 | CONFIG_UNIX98_PTYS=y | ||
| 505 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 506 | # CONFIG_LEGACY_PTYS is not set | ||
| 507 | # CONFIG_IPMI_HANDLER is not set | ||
| 508 | # CONFIG_HW_RANDOM is not set | ||
| 509 | # CONFIG_R3964 is not set | ||
| 510 | # CONFIG_RAW_DRIVER is not set | ||
| 511 | # CONFIG_TCG_TPM is not set | ||
| 512 | # CONFIG_I2C is not set | ||
| 513 | # CONFIG_SPI is not set | ||
| 514 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 515 | CONFIG_GPIOLIB=y | ||
| 516 | # CONFIG_DEBUG_GPIO is not set | ||
| 517 | # CONFIG_GPIO_SYSFS is not set | ||
| 518 | |||
| 519 | # | ||
| 520 | # Memory mapped GPIO expanders: | ||
| 521 | # | ||
| 522 | |||
| 523 | # | ||
| 524 | # I2C GPIO expanders: | ||
| 525 | # | ||
| 526 | |||
| 527 | # | ||
| 528 | # PCI GPIO expanders: | ||
| 529 | # | ||
| 530 | |||
| 531 | # | ||
| 532 | # SPI GPIO expanders: | ||
| 533 | # | ||
| 534 | # CONFIG_W1 is not set | ||
| 535 | # CONFIG_POWER_SUPPLY is not set | ||
| 536 | # CONFIG_HWMON is not set | ||
| 537 | # CONFIG_THERMAL is not set | ||
| 538 | # CONFIG_THERMAL_HWMON is not set | ||
| 539 | # CONFIG_WATCHDOG is not set | ||
| 540 | CONFIG_SSB_POSSIBLE=y | ||
| 541 | |||
| 542 | # | ||
| 543 | # Sonics Silicon Backplane | ||
| 544 | # | ||
| 545 | # CONFIG_SSB is not set | ||
| 546 | |||
| 547 | # | ||
| 548 | # Multifunction device drivers | ||
| 549 | # | ||
| 550 | # CONFIG_MFD_CORE is not set | ||
| 551 | # CONFIG_MFD_SM501 is not set | ||
| 552 | # CONFIG_MFD_ASIC3 is not set | ||
| 553 | # CONFIG_HTC_EGPIO is not set | ||
| 554 | # CONFIG_HTC_PASIC3 is not set | ||
| 555 | # CONFIG_MFD_TMIO is not set | ||
| 556 | # CONFIG_MFD_T7L66XB is not set | ||
| 557 | # CONFIG_MFD_TC6387XB is not set | ||
| 558 | # CONFIG_MFD_TC6393XB is not set | ||
| 559 | |||
| 560 | # | ||
| 561 | # Multimedia devices | ||
| 562 | # | ||
| 563 | |||
| 564 | # | ||
| 565 | # Multimedia core support | ||
| 566 | # | ||
| 567 | # CONFIG_VIDEO_DEV is not set | ||
| 568 | # CONFIG_DVB_CORE is not set | ||
| 569 | # CONFIG_VIDEO_MEDIA is not set | ||
| 570 | |||
| 571 | # | ||
| 572 | # Multimedia drivers | ||
| 573 | # | ||
| 574 | # CONFIG_DAB is not set | ||
| 575 | |||
| 576 | # | ||
| 577 | # Graphics support | ||
| 578 | # | ||
| 579 | # CONFIG_VGASTATE is not set | ||
| 580 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 581 | # CONFIG_FB is not set | ||
| 582 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 583 | |||
| 584 | # | ||
| 585 | # Display device support | ||
| 586 | # | ||
| 587 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 588 | |||
| 589 | # | ||
| 590 | # Console display driver support | ||
| 591 | # | ||
| 592 | # CONFIG_VGA_CONSOLE is not set | ||
| 593 | CONFIG_DUMMY_CONSOLE=y | ||
| 594 | # CONFIG_SOUND is not set | ||
| 595 | # CONFIG_HID_SUPPORT is not set | ||
| 596 | # CONFIG_USB_SUPPORT is not set | ||
| 597 | # CONFIG_MMC is not set | ||
| 598 | # CONFIG_MEMSTICK is not set | ||
| 599 | # CONFIG_ACCESSIBILITY is not set | ||
| 600 | # CONFIG_NEW_LEDS is not set | ||
| 601 | CONFIG_RTC_LIB=y | ||
| 602 | # CONFIG_RTC_CLASS is not set | ||
| 603 | # CONFIG_DMADEVICES is not set | ||
| 604 | # CONFIG_REGULATOR is not set | ||
| 605 | # CONFIG_UIO is not set | ||
| 606 | # CONFIG_STAGING is not set | ||
| 607 | |||
| 608 | # | ||
| 609 | # File systems | ||
| 610 | # | ||
| 611 | # CONFIG_EXT2_FS is not set | ||
| 612 | # CONFIG_EXT3_FS is not set | ||
| 613 | # CONFIG_EXT4_FS is not set | ||
| 614 | # CONFIG_REISERFS_FS is not set | ||
| 615 | # CONFIG_JFS_FS is not set | ||
| 616 | CONFIG_FS_POSIX_ACL=y | ||
| 617 | CONFIG_FILE_LOCKING=y | ||
| 618 | # CONFIG_XFS_FS is not set | ||
| 619 | # CONFIG_OCFS2_FS is not set | ||
| 620 | # CONFIG_BTRFS_FS is not set | ||
| 621 | CONFIG_DNOTIFY=y | ||
| 622 | CONFIG_INOTIFY=y | ||
| 623 | CONFIG_INOTIFY_USER=y | ||
| 624 | # CONFIG_QUOTA is not set | ||
| 625 | # CONFIG_AUTOFS_FS is not set | ||
| 626 | # CONFIG_AUTOFS4_FS is not set | ||
| 627 | # CONFIG_FUSE_FS is not set | ||
| 628 | CONFIG_GENERIC_ACL=y | ||
| 629 | |||
| 630 | # | ||
| 631 | # CD-ROM/DVD Filesystems | ||
| 632 | # | ||
| 633 | # CONFIG_ISO9660_FS is not set | ||
| 634 | # CONFIG_UDF_FS is not set | ||
| 635 | |||
| 636 | # | ||
| 637 | # DOS/FAT/NT Filesystems | ||
| 638 | # | ||
| 639 | # CONFIG_MSDOS_FS is not set | ||
| 640 | # CONFIG_VFAT_FS is not set | ||
| 641 | # CONFIG_NTFS_FS is not set | ||
| 642 | |||
| 643 | # | ||
| 644 | # Pseudo filesystems | ||
| 645 | # | ||
| 646 | CONFIG_PROC_FS=y | ||
| 647 | CONFIG_PROC_SYSCTL=y | ||
| 648 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 649 | CONFIG_SYSFS=y | ||
| 650 | CONFIG_TMPFS=y | ||
| 651 | CONFIG_TMPFS_POSIX_ACL=y | ||
| 652 | # CONFIG_HUGETLB_PAGE is not set | ||
| 653 | # CONFIG_CONFIGFS_FS is not set | ||
| 654 | CONFIG_MISC_FILESYSTEMS=y | ||
| 655 | # CONFIG_ADFS_FS is not set | ||
| 656 | # CONFIG_AFFS_FS is not set | ||
| 657 | # CONFIG_HFS_FS is not set | ||
| 658 | # CONFIG_HFSPLUS_FS is not set | ||
| 659 | # CONFIG_BEFS_FS is not set | ||
| 660 | # CONFIG_BFS_FS is not set | ||
| 661 | # CONFIG_EFS_FS is not set | ||
| 662 | CONFIG_CRAMFS=y | ||
| 663 | # CONFIG_SQUASHFS is not set | ||
| 664 | # CONFIG_VXFS_FS is not set | ||
| 665 | # CONFIG_MINIX_FS is not set | ||
| 666 | # CONFIG_OMFS_FS is not set | ||
| 667 | # CONFIG_HPFS_FS is not set | ||
| 668 | # CONFIG_QNX4FS_FS is not set | ||
| 669 | # CONFIG_ROMFS_FS is not set | ||
| 670 | # CONFIG_SYSV_FS is not set | ||
| 671 | # CONFIG_UFS_FS is not set | ||
| 672 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 673 | CONFIG_NFS_FS=y | ||
| 674 | CONFIG_NFS_V3=y | ||
| 675 | CONFIG_NFS_V3_ACL=y | ||
| 676 | CONFIG_NFS_V4=y | ||
| 677 | CONFIG_ROOT_NFS=y | ||
| 678 | # CONFIG_NFSD is not set | ||
| 679 | CONFIG_LOCKD=y | ||
| 680 | CONFIG_LOCKD_V4=y | ||
| 681 | CONFIG_NFS_ACL_SUPPORT=y | ||
| 682 | CONFIG_NFS_COMMON=y | ||
| 683 | CONFIG_SUNRPC=y | ||
| 684 | CONFIG_SUNRPC_GSS=y | ||
| 685 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 686 | CONFIG_RPCSEC_GSS_KRB5=y | ||
| 687 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 688 | # CONFIG_SMB_FS is not set | ||
| 689 | # CONFIG_CIFS is not set | ||
| 690 | # CONFIG_NCP_FS is not set | ||
| 691 | # CONFIG_CODA_FS is not set | ||
| 692 | # CONFIG_AFS_FS is not set | ||
| 693 | |||
| 694 | # | ||
| 695 | # Partition Types | ||
| 696 | # | ||
| 697 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 698 | CONFIG_MSDOS_PARTITION=y | ||
| 699 | # CONFIG_NLS is not set | ||
| 700 | # CONFIG_DLM is not set | ||
| 701 | |||
| 702 | # | ||
| 703 | # Kernel hacking | ||
| 704 | # | ||
| 705 | CONFIG_PRINTK_TIME=y | ||
| 706 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 707 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 708 | CONFIG_FRAME_WARN=1024 | ||
| 709 | CONFIG_MAGIC_SYSRQ=y | ||
| 710 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 711 | # CONFIG_DEBUG_FS is not set | ||
| 712 | # CONFIG_HEADERS_CHECK is not set | ||
| 713 | CONFIG_DEBUG_KERNEL=y | ||
| 714 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 715 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 716 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 717 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 718 | CONFIG_SCHED_DEBUG=y | ||
| 719 | # CONFIG_SCHEDSTATS is not set | ||
| 720 | # CONFIG_TIMER_STATS is not set | ||
| 721 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 722 | # CONFIG_DEBUG_SLAB is not set | ||
| 723 | # CONFIG_DEBUG_PREEMPT is not set | ||
| 724 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 725 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 726 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 727 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 728 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 729 | # CONFIG_PROVE_LOCKING is not set | ||
| 730 | # CONFIG_LOCK_STAT is not set | ||
| 731 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 732 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 733 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 734 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 735 | CONFIG_DEBUG_INFO=y | ||
| 736 | # CONFIG_DEBUG_VM is not set | ||
| 737 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 738 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 739 | # CONFIG_DEBUG_LIST is not set | ||
| 740 | # CONFIG_DEBUG_SG is not set | ||
| 741 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 742 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 743 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 744 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 745 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 746 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 747 | # CONFIG_FAULT_INJECTION is not set | ||
| 748 | # CONFIG_LATENCYTOP is not set | ||
| 749 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 750 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 751 | |||
| 752 | # | ||
| 753 | # Tracers | ||
| 754 | # | ||
| 755 | # CONFIG_FUNCTION_TRACER is not set | ||
| 756 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 757 | # CONFIG_PREEMPT_TRACER is not set | ||
| 758 | # CONFIG_SCHED_TRACER is not set | ||
| 759 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 760 | # CONFIG_BOOT_TRACER is not set | ||
| 761 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 762 | # CONFIG_STACK_TRACER is not set | ||
| 763 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 764 | # CONFIG_SAMPLES is not set | ||
| 765 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 766 | # CONFIG_KGDB is not set | ||
| 767 | CONFIG_ARM_UNWIND=y | ||
| 768 | CONFIG_DEBUG_USER=y | ||
| 769 | CONFIG_DEBUG_ERRORS=y | ||
| 770 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 771 | CONFIG_DEBUG_LL=y | ||
| 772 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 773 | |||
| 774 | # | ||
| 775 | # Security options | ||
| 776 | # | ||
| 777 | # CONFIG_KEYS is not set | ||
| 778 | # CONFIG_SECURITY is not set | ||
| 779 | # CONFIG_SECURITYFS is not set | ||
| 780 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 781 | CONFIG_CRYPTO=y | ||
| 782 | |||
| 783 | # | ||
| 784 | # Crypto core or helper | ||
| 785 | # | ||
| 786 | # CONFIG_CRYPTO_FIPS is not set | ||
| 787 | CONFIG_CRYPTO_ALGAPI=y | ||
| 788 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 789 | CONFIG_CRYPTO_AEAD2=y | ||
| 790 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 791 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 792 | CONFIG_CRYPTO_HASH=y | ||
| 793 | CONFIG_CRYPTO_HASH2=y | ||
| 794 | CONFIG_CRYPTO_RNG2=y | ||
| 795 | CONFIG_CRYPTO_MANAGER=y | ||
| 796 | CONFIG_CRYPTO_MANAGER2=y | ||
| 797 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 798 | # CONFIG_CRYPTO_NULL is not set | ||
| 799 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 800 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 801 | # CONFIG_CRYPTO_TEST is not set | ||
| 802 | |||
| 803 | # | ||
| 804 | # Authenticated Encryption with Associated Data | ||
| 805 | # | ||
| 806 | # CONFIG_CRYPTO_CCM is not set | ||
| 807 | # CONFIG_CRYPTO_GCM is not set | ||
| 808 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 809 | |||
| 810 | # | ||
| 811 | # Block modes | ||
| 812 | # | ||
| 813 | CONFIG_CRYPTO_CBC=y | ||
| 814 | # CONFIG_CRYPTO_CTR is not set | ||
| 815 | # CONFIG_CRYPTO_CTS is not set | ||
| 816 | # CONFIG_CRYPTO_ECB is not set | ||
| 817 | # CONFIG_CRYPTO_LRW is not set | ||
| 818 | # CONFIG_CRYPTO_PCBC is not set | ||
| 819 | # CONFIG_CRYPTO_XTS is not set | ||
| 820 | |||
| 821 | # | ||
| 822 | # Hash modes | ||
| 823 | # | ||
| 824 | # CONFIG_CRYPTO_HMAC is not set | ||
| 825 | # CONFIG_CRYPTO_XCBC is not set | ||
| 826 | |||
| 827 | # | ||
| 828 | # Digest | ||
| 829 | # | ||
| 830 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 831 | # CONFIG_CRYPTO_MD4 is not set | ||
| 832 | CONFIG_CRYPTO_MD5=y | ||
| 833 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 834 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 835 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 836 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 837 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 838 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 839 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 840 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 841 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 842 | # CONFIG_CRYPTO_WP512 is not set | ||
| 843 | |||
| 844 | # | ||
| 845 | # Ciphers | ||
| 846 | # | ||
| 847 | # CONFIG_CRYPTO_AES is not set | ||
| 848 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 849 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 850 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 851 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 852 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 853 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 854 | CONFIG_CRYPTO_DES=y | ||
| 855 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 856 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 857 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 858 | # CONFIG_CRYPTO_SEED is not set | ||
| 859 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 860 | # CONFIG_CRYPTO_TEA is not set | ||
| 861 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 862 | |||
| 863 | # | ||
| 864 | # Compression | ||
| 865 | # | ||
| 866 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 867 | # CONFIG_CRYPTO_LZO is not set | ||
| 868 | |||
| 869 | # | ||
| 870 | # Random Number Generation | ||
| 871 | # | ||
| 872 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 873 | CONFIG_CRYPTO_HW=y | ||
| 874 | |||
| 875 | # | ||
| 876 | # Library routines | ||
| 877 | # | ||
| 878 | CONFIG_BITREVERSE=y | ||
| 879 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 880 | CONFIG_CRC_CCITT=y | ||
| 881 | # CONFIG_CRC16 is not set | ||
| 882 | # CONFIG_CRC_T10DIF is not set | ||
| 883 | # CONFIG_CRC_ITU_T is not set | ||
| 884 | CONFIG_CRC32=y | ||
| 885 | # CONFIG_CRC7 is not set | ||
| 886 | # CONFIG_LIBCRC32C is not set | ||
| 887 | CONFIG_ZLIB_INFLATE=y | ||
| 888 | CONFIG_PLIST=y | ||
| 889 | CONFIG_HAS_IOMEM=y | ||
| 890 | CONFIG_HAS_IOPORT=y | ||
| 891 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/pxa910_defconfig b/arch/arm/configs/pxa910_defconfig new file mode 100644 index 000000000000..8c7e299f1d66 --- /dev/null +++ b/arch/arm/configs/pxa910_defconfig | |||
| @@ -0,0 +1,891 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.29-rc3 | ||
| 4 | # Fri Mar 20 13:45:12 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 26 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 28 | |||
| 29 | # | ||
| 30 | # General setup | ||
| 31 | # | ||
| 32 | CONFIG_EXPERIMENTAL=y | ||
| 33 | CONFIG_BROKEN_ON_SMP=y | ||
| 34 | CONFIG_LOCK_KERNEL=y | ||
| 35 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 36 | CONFIG_LOCALVERSION="" | ||
| 37 | CONFIG_LOCALVERSION_AUTO=y | ||
| 38 | CONFIG_SWAP=y | ||
| 39 | CONFIG_SYSVIPC=y | ||
| 40 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 41 | # CONFIG_POSIX_MQUEUE is not set | ||
| 42 | # CONFIG_BSD_PROCESS_ACCT is not set | ||
| 43 | # CONFIG_TASKSTATS is not set | ||
| 44 | # CONFIG_AUDIT is not set | ||
| 45 | |||
| 46 | # | ||
| 47 | # RCU Subsystem | ||
| 48 | # | ||
| 49 | CONFIG_CLASSIC_RCU=y | ||
| 50 | # CONFIG_TREE_RCU is not set | ||
| 51 | # CONFIG_PREEMPT_RCU is not set | ||
| 52 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 53 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 54 | # CONFIG_IKCONFIG is not set | ||
| 55 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 56 | # CONFIG_GROUP_SCHED is not set | ||
| 57 | # CONFIG_CGROUPS is not set | ||
| 58 | CONFIG_SYSFS_DEPRECATED=y | ||
| 59 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 60 | # CONFIG_RELAY is not set | ||
| 61 | CONFIG_NAMESPACES=y | ||
| 62 | # CONFIG_UTS_NS is not set | ||
| 63 | # CONFIG_IPC_NS is not set | ||
| 64 | # CONFIG_USER_NS is not set | ||
| 65 | # CONFIG_PID_NS is not set | ||
| 66 | # CONFIG_NET_NS is not set | ||
| 67 | CONFIG_BLK_DEV_INITRD=y | ||
| 68 | CONFIG_INITRAMFS_SOURCE="" | ||
| 69 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 70 | CONFIG_SYSCTL=y | ||
| 71 | # CONFIG_EMBEDDED is not set | ||
| 72 | CONFIG_UID16=y | ||
| 73 | CONFIG_SYSCTL_SYSCALL=y | ||
| 74 | CONFIG_KALLSYMS=y | ||
| 75 | # CONFIG_KALLSYMS_ALL is not set | ||
| 76 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | ||
| 77 | CONFIG_HOTPLUG=y | ||
| 78 | CONFIG_PRINTK=y | ||
| 79 | CONFIG_BUG=y | ||
| 80 | CONFIG_ELF_CORE=y | ||
| 81 | CONFIG_COMPAT_BRK=y | ||
| 82 | CONFIG_BASE_FULL=y | ||
| 83 | CONFIG_FUTEX=y | ||
| 84 | CONFIG_ANON_INODES=y | ||
| 85 | CONFIG_EPOLL=y | ||
| 86 | CONFIG_SIGNALFD=y | ||
| 87 | CONFIG_TIMERFD=y | ||
| 88 | CONFIG_EVENTFD=y | ||
| 89 | CONFIG_SHMEM=y | ||
| 90 | CONFIG_AIO=y | ||
| 91 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 92 | CONFIG_SLAB=y | ||
| 93 | # CONFIG_SLUB is not set | ||
| 94 | # CONFIG_SLOB is not set | ||
| 95 | # CONFIG_PROFILING is not set | ||
| 96 | CONFIG_HAVE_OPROFILE=y | ||
| 97 | # CONFIG_KPROBES is not set | ||
| 98 | CONFIG_HAVE_KPROBES=y | ||
| 99 | CONFIG_HAVE_KRETPROBES=y | ||
| 100 | CONFIG_HAVE_CLK=y | ||
| 101 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 102 | CONFIG_SLABINFO=y | ||
| 103 | CONFIG_RT_MUTEXES=y | ||
| 104 | CONFIG_BASE_SMALL=0 | ||
| 105 | CONFIG_MODULES=y | ||
| 106 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 107 | CONFIG_MODULE_UNLOAD=y | ||
| 108 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 109 | # CONFIG_MODVERSIONS is not set | ||
| 110 | # CONFIG_MODULE_SRCVERSION_ALL is not set | ||
| 111 | CONFIG_BLOCK=y | ||
| 112 | # CONFIG_LBD is not set | ||
| 113 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 114 | # CONFIG_BLK_DEV_BSG is not set | ||
| 115 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 116 | |||
| 117 | # | ||
| 118 | # IO Schedulers | ||
| 119 | # | ||
| 120 | CONFIG_IOSCHED_NOOP=y | ||
| 121 | CONFIG_IOSCHED_AS=y | ||
| 122 | CONFIG_IOSCHED_DEADLINE=y | ||
| 123 | CONFIG_IOSCHED_CFQ=y | ||
| 124 | # CONFIG_DEFAULT_AS is not set | ||
| 125 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 126 | CONFIG_DEFAULT_CFQ=y | ||
| 127 | # CONFIG_DEFAULT_NOOP is not set | ||
| 128 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 129 | # CONFIG_FREEZER is not set | ||
| 130 | |||
| 131 | # | ||
| 132 | # System Type | ||
| 133 | # | ||
| 134 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 135 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 136 | # CONFIG_ARCH_REALVIEW is not set | ||
| 137 | # CONFIG_ARCH_VERSATILE is not set | ||
| 138 | # CONFIG_ARCH_AT91 is not set | ||
| 139 | # CONFIG_ARCH_CLPS711X is not set | ||
| 140 | # CONFIG_ARCH_EBSA110 is not set | ||
| 141 | # CONFIG_ARCH_EP93XX is not set | ||
| 142 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 143 | # CONFIG_ARCH_NETX is not set | ||
| 144 | # CONFIG_ARCH_H720X is not set | ||
| 145 | # CONFIG_ARCH_IMX is not set | ||
| 146 | # CONFIG_ARCH_IOP13XX is not set | ||
| 147 | # CONFIG_ARCH_IOP32X is not set | ||
| 148 | # CONFIG_ARCH_IOP33X is not set | ||
| 149 | # CONFIG_ARCH_IXP23XX is not set | ||
| 150 | # CONFIG_ARCH_IXP2000 is not set | ||
| 151 | # CONFIG_ARCH_IXP4XX is not set | ||
| 152 | # CONFIG_ARCH_L7200 is not set | ||
| 153 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 154 | # CONFIG_ARCH_KS8695 is not set | ||
| 155 | # CONFIG_ARCH_NS9XXX is not set | ||
| 156 | # CONFIG_ARCH_LOKI is not set | ||
| 157 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 158 | # CONFIG_ARCH_MXC is not set | ||
| 159 | # CONFIG_ARCH_ORION5X is not set | ||
| 160 | # CONFIG_ARCH_PNX4008 is not set | ||
| 161 | # CONFIG_ARCH_PXA is not set | ||
| 162 | CONFIG_ARCH_MMP=y | ||
| 163 | # CONFIG_ARCH_RPC is not set | ||
| 164 | # CONFIG_ARCH_SA1100 is not set | ||
| 165 | # CONFIG_ARCH_S3C2410 is not set | ||
| 166 | # CONFIG_ARCH_S3C64XX is not set | ||
| 167 | # CONFIG_ARCH_SHARK is not set | ||
| 168 | # CONFIG_ARCH_LH7A40X is not set | ||
| 169 | # CONFIG_ARCH_DAVINCI is not set | ||
| 170 | # CONFIG_ARCH_OMAP is not set | ||
| 171 | # CONFIG_ARCH_MSM is not set | ||
| 172 | # CONFIG_ARCH_W90X900 is not set | ||
| 173 | CONFIG_MACH_TAVOREVB=y | ||
| 174 | |||
| 175 | # | ||
| 176 | # Marvell PXA168/910 Implmentations | ||
| 177 | # | ||
| 178 | # CONFIG_MACH_ASPENITE is not set | ||
| 179 | # CONFIG_MACH_ZYLONITE2 is not set | ||
| 180 | CONFIG_MACH_TTC_DKB=y | ||
| 181 | CONFIG_CPU_PXA910=y | ||
| 182 | CONFIG_PLAT_PXA=y | ||
| 183 | |||
| 184 | # | ||
| 185 | # Processor Type | ||
| 186 | # | ||
| 187 | CONFIG_CPU_32=y | ||
| 188 | CONFIG_CPU_MOHAWK=y | ||
| 189 | CONFIG_CPU_32v5=y | ||
| 190 | CONFIG_CPU_ABRT_EV5T=y | ||
| 191 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 192 | CONFIG_CPU_CACHE_VIVT=y | ||
| 193 | CONFIG_CPU_COPY_V4WB=y | ||
| 194 | CONFIG_CPU_TLB_V4WBI=y | ||
| 195 | CONFIG_CPU_CP15=y | ||
| 196 | CONFIG_CPU_CP15_MMU=y | ||
| 197 | |||
| 198 | # | ||
| 199 | # Processor Features | ||
| 200 | # | ||
| 201 | CONFIG_ARM_THUMB=y | ||
| 202 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 203 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 204 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
| 205 | # CONFIG_OUTER_CACHE is not set | ||
| 206 | CONFIG_IWMMXT=y | ||
| 207 | CONFIG_COMMON_CLKDEV=y | ||
| 208 | |||
| 209 | # | ||
| 210 | # Bus support | ||
| 211 | # | ||
| 212 | # CONFIG_PCI_SYSCALL is not set | ||
| 213 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 214 | # CONFIG_PCCARD is not set | ||
| 215 | |||
| 216 | # | ||
| 217 | # Kernel Features | ||
| 218 | # | ||
| 219 | CONFIG_TICK_ONESHOT=y | ||
| 220 | CONFIG_NO_HZ=y | ||
| 221 | CONFIG_HIGH_RES_TIMERS=y | ||
| 222 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 223 | CONFIG_VMSPLIT_3G=y | ||
| 224 | # CONFIG_VMSPLIT_2G is not set | ||
| 225 | # CONFIG_VMSPLIT_1G is not set | ||
| 226 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 227 | CONFIG_PREEMPT=y | ||
| 228 | CONFIG_HZ=100 | ||
| 229 | CONFIG_AEABI=y | ||
| 230 | CONFIG_OABI_COMPAT=y | ||
| 231 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 232 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 233 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 234 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 235 | CONFIG_FLATMEM_MANUAL=y | ||
| 236 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 237 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 238 | CONFIG_FLATMEM=y | ||
| 239 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 240 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 241 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 242 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 243 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 244 | CONFIG_VIRT_TO_BUS=y | ||
| 245 | CONFIG_UNEVICTABLE_LRU=y | ||
| 246 | CONFIG_ALIGNMENT_TRAP=y | ||
| 247 | |||
| 248 | # | ||
| 249 | # Boot options | ||
| 250 | # | ||
| 251 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 252 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 253 | CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M" | ||
| 254 | # CONFIG_XIP_KERNEL is not set | ||
| 255 | # CONFIG_KEXEC is not set | ||
| 256 | |||
| 257 | # | ||
| 258 | # CPU Power Management | ||
| 259 | # | ||
| 260 | # CONFIG_CPU_IDLE is not set | ||
| 261 | |||
| 262 | # | ||
| 263 | # Floating point emulation | ||
| 264 | # | ||
| 265 | |||
| 266 | # | ||
| 267 | # At least one emulation must be selected | ||
| 268 | # | ||
| 269 | CONFIG_FPE_NWFPE=y | ||
| 270 | # CONFIG_FPE_NWFPE_XP is not set | ||
| 271 | # CONFIG_FPE_FASTFPE is not set | ||
| 272 | |||
| 273 | # | ||
| 274 | # Userspace binary formats | ||
| 275 | # | ||
| 276 | CONFIG_BINFMT_ELF=y | ||
| 277 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 278 | CONFIG_HAVE_AOUT=y | ||
| 279 | # CONFIG_BINFMT_AOUT is not set | ||
| 280 | # CONFIG_BINFMT_MISC is not set | ||
| 281 | |||
| 282 | # | ||
| 283 | # Power management options | ||
| 284 | # | ||
| 285 | # CONFIG_PM is not set | ||
| 286 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 287 | CONFIG_NET=y | ||
| 288 | |||
| 289 | # | ||
| 290 | # Networking options | ||
| 291 | # | ||
| 292 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 293 | CONFIG_PACKET=y | ||
| 294 | # CONFIG_PACKET_MMAP is not set | ||
| 295 | CONFIG_UNIX=y | ||
| 296 | CONFIG_XFRM=y | ||
| 297 | # CONFIG_XFRM_USER is not set | ||
| 298 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 299 | # CONFIG_XFRM_MIGRATE is not set | ||
| 300 | # CONFIG_XFRM_STATISTICS is not set | ||
| 301 | # CONFIG_NET_KEY is not set | ||
| 302 | CONFIG_INET=y | ||
| 303 | # CONFIG_IP_MULTICAST is not set | ||
| 304 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 305 | CONFIG_IP_FIB_HASH=y | ||
| 306 | CONFIG_IP_PNP=y | ||
| 307 | # CONFIG_IP_PNP_DHCP is not set | ||
| 308 | # CONFIG_IP_PNP_BOOTP is not set | ||
| 309 | # CONFIG_IP_PNP_RARP is not set | ||
| 310 | # CONFIG_NET_IPIP is not set | ||
| 311 | # CONFIG_NET_IPGRE is not set | ||
| 312 | # CONFIG_ARPD is not set | ||
| 313 | # CONFIG_SYN_COOKIES is not set | ||
| 314 | # CONFIG_INET_AH is not set | ||
| 315 | # CONFIG_INET_ESP is not set | ||
| 316 | # CONFIG_INET_IPCOMP is not set | ||
| 317 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 318 | # CONFIG_INET_TUNNEL is not set | ||
| 319 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 320 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 321 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 322 | # CONFIG_INET_LRO is not set | ||
| 323 | CONFIG_INET_DIAG=y | ||
| 324 | CONFIG_INET_TCP_DIAG=y | ||
| 325 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 326 | CONFIG_TCP_CONG_CUBIC=y | ||
| 327 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 328 | # CONFIG_TCP_MD5SIG is not set | ||
| 329 | # CONFIG_IPV6 is not set | ||
| 330 | # CONFIG_NETWORK_SECMARK is not set | ||
| 331 | # CONFIG_NETFILTER is not set | ||
| 332 | # CONFIG_IP_DCCP is not set | ||
| 333 | # CONFIG_IP_SCTP is not set | ||
| 334 | # CONFIG_TIPC is not set | ||
| 335 | # CONFIG_ATM is not set | ||
| 336 | # CONFIG_BRIDGE is not set | ||
| 337 | # CONFIG_NET_DSA is not set | ||
| 338 | # CONFIG_VLAN_8021Q is not set | ||
| 339 | # CONFIG_DECNET is not set | ||
| 340 | # CONFIG_LLC2 is not set | ||
| 341 | # CONFIG_IPX is not set | ||
| 342 | # CONFIG_ATALK is not set | ||
| 343 | # CONFIG_X25 is not set | ||
| 344 | # CONFIG_LAPB is not set | ||
| 345 | # CONFIG_ECONET is not set | ||
| 346 | # CONFIG_WAN_ROUTER is not set | ||
| 347 | # CONFIG_NET_SCHED is not set | ||
| 348 | # CONFIG_DCB is not set | ||
| 349 | |||
| 350 | # | ||
| 351 | # Network testing | ||
| 352 | # | ||
| 353 | # CONFIG_NET_PKTGEN is not set | ||
| 354 | # CONFIG_HAMRADIO is not set | ||
| 355 | # CONFIG_CAN is not set | ||
| 356 | # CONFIG_IRDA is not set | ||
| 357 | # CONFIG_BT is not set | ||
| 358 | # CONFIG_AF_RXRPC is not set | ||
| 359 | # CONFIG_PHONET is not set | ||
| 360 | CONFIG_WIRELESS=y | ||
| 361 | # CONFIG_CFG80211 is not set | ||
| 362 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 363 | # CONFIG_WIRELESS_EXT is not set | ||
| 364 | # CONFIG_LIB80211 is not set | ||
| 365 | # CONFIG_MAC80211 is not set | ||
| 366 | # CONFIG_WIMAX is not set | ||
| 367 | # CONFIG_RFKILL is not set | ||
| 368 | # CONFIG_NET_9P is not set | ||
| 369 | |||
| 370 | # | ||
| 371 | # Device Drivers | ||
| 372 | # | ||
| 373 | |||
| 374 | # | ||
| 375 | # Generic Driver Options | ||
| 376 | # | ||
| 377 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 378 | # CONFIG_STANDALONE is not set | ||
| 379 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | ||
| 380 | CONFIG_FW_LOADER=y | ||
| 381 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 382 | CONFIG_EXTRA_FIRMWARE="" | ||
| 383 | # CONFIG_DEBUG_DRIVER is not set | ||
| 384 | # CONFIG_DEBUG_DEVRES is not set | ||
| 385 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 386 | # CONFIG_CONNECTOR is not set | ||
| 387 | # CONFIG_MTD is not set | ||
| 388 | # CONFIG_PARPORT is not set | ||
| 389 | # CONFIG_BLK_DEV is not set | ||
| 390 | # CONFIG_MISC_DEVICES is not set | ||
| 391 | CONFIG_HAVE_IDE=y | ||
| 392 | # CONFIG_IDE is not set | ||
| 393 | |||
| 394 | # | ||
| 395 | # SCSI device support | ||
| 396 | # | ||
| 397 | # CONFIG_RAID_ATTRS is not set | ||
| 398 | # CONFIG_SCSI is not set | ||
| 399 | # CONFIG_SCSI_DMA is not set | ||
| 400 | # CONFIG_SCSI_NETLINK is not set | ||
| 401 | # CONFIG_ATA is not set | ||
| 402 | # CONFIG_MD is not set | ||
| 403 | CONFIG_NETDEVICES=y | ||
| 404 | # CONFIG_DUMMY is not set | ||
| 405 | # CONFIG_BONDING is not set | ||
| 406 | # CONFIG_MACVLAN is not set | ||
| 407 | # CONFIG_EQUALIZER is not set | ||
| 408 | # CONFIG_TUN is not set | ||
| 409 | # CONFIG_VETH is not set | ||
| 410 | # CONFIG_PHYLIB is not set | ||
| 411 | CONFIG_NET_ETHERNET=y | ||
| 412 | CONFIG_MII=y | ||
| 413 | # CONFIG_AX88796 is not set | ||
| 414 | CONFIG_SMC91X=y | ||
| 415 | # CONFIG_DM9000 is not set | ||
| 416 | # CONFIG_SMC911X is not set | ||
| 417 | # CONFIG_SMSC911X is not set | ||
| 418 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 419 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 420 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 421 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 422 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 423 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 424 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 425 | # CONFIG_B44 is not set | ||
| 426 | # CONFIG_NETDEV_1000 is not set | ||
| 427 | # CONFIG_NETDEV_10000 is not set | ||
| 428 | |||
| 429 | # | ||
| 430 | # Wireless LAN | ||
| 431 | # | ||
| 432 | # CONFIG_WLAN_PRE80211 is not set | ||
| 433 | # CONFIG_WLAN_80211 is not set | ||
| 434 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 435 | |||
| 436 | # | ||
| 437 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 438 | # | ||
| 439 | # CONFIG_WAN is not set | ||
| 440 | # CONFIG_PPP is not set | ||
| 441 | # CONFIG_SLIP is not set | ||
| 442 | # CONFIG_NETCONSOLE is not set | ||
| 443 | # CONFIG_NETPOLL is not set | ||
| 444 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 445 | # CONFIG_ISDN is not set | ||
| 446 | |||
| 447 | # | ||
| 448 | # Input device support | ||
| 449 | # | ||
| 450 | CONFIG_INPUT=y | ||
| 451 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 452 | # CONFIG_INPUT_POLLDEV is not set | ||
| 453 | |||
| 454 | # | ||
| 455 | # Userland interfaces | ||
| 456 | # | ||
| 457 | CONFIG_INPUT_MOUSEDEV=y | ||
| 458 | # CONFIG_INPUT_MOUSEDEV_PSAUX is not set | ||
| 459 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | ||
| 460 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | ||
| 461 | # CONFIG_INPUT_JOYDEV is not set | ||
| 462 | # CONFIG_INPUT_EVDEV is not set | ||
| 463 | # CONFIG_INPUT_EVBUG is not set | ||
| 464 | |||
| 465 | # | ||
| 466 | # Input Device Drivers | ||
| 467 | # | ||
| 468 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 469 | # CONFIG_INPUT_MOUSE is not set | ||
| 470 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 471 | # CONFIG_INPUT_TABLET is not set | ||
| 472 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 473 | # CONFIG_INPUT_MISC is not set | ||
| 474 | |||
| 475 | # | ||
| 476 | # Hardware I/O ports | ||
| 477 | # | ||
| 478 | # CONFIG_SERIO is not set | ||
| 479 | # CONFIG_GAMEPORT is not set | ||
| 480 | |||
| 481 | # | ||
| 482 | # Character devices | ||
| 483 | # | ||
| 484 | CONFIG_VT=y | ||
| 485 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 486 | CONFIG_VT_CONSOLE=y | ||
| 487 | CONFIG_HW_CONSOLE=y | ||
| 488 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 489 | CONFIG_DEVKMEM=y | ||
| 490 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 491 | |||
| 492 | # | ||
| 493 | # Serial drivers | ||
| 494 | # | ||
| 495 | # CONFIG_SERIAL_8250 is not set | ||
| 496 | |||
| 497 | # | ||
| 498 | # Non-8250 serial port support | ||
| 499 | # | ||
| 500 | CONFIG_SERIAL_PXA=y | ||
| 501 | CONFIG_SERIAL_PXA_CONSOLE=y | ||
| 502 | CONFIG_SERIAL_CORE=y | ||
| 503 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 504 | CONFIG_UNIX98_PTYS=y | ||
| 505 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 506 | # CONFIG_LEGACY_PTYS is not set | ||
| 507 | # CONFIG_IPMI_HANDLER is not set | ||
| 508 | # CONFIG_HW_RANDOM is not set | ||
| 509 | # CONFIG_R3964 is not set | ||
| 510 | # CONFIG_RAW_DRIVER is not set | ||
| 511 | # CONFIG_TCG_TPM is not set | ||
| 512 | # CONFIG_I2C is not set | ||
| 513 | # CONFIG_SPI is not set | ||
| 514 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 515 | CONFIG_GPIOLIB=y | ||
| 516 | # CONFIG_DEBUG_GPIO is not set | ||
| 517 | # CONFIG_GPIO_SYSFS is not set | ||
| 518 | |||
| 519 | # | ||
| 520 | # Memory mapped GPIO expanders: | ||
| 521 | # | ||
| 522 | |||
| 523 | # | ||
| 524 | # I2C GPIO expanders: | ||
| 525 | # | ||
| 526 | |||
| 527 | # | ||
| 528 | # PCI GPIO expanders: | ||
| 529 | # | ||
| 530 | |||
| 531 | # | ||
| 532 | # SPI GPIO expanders: | ||
| 533 | # | ||
| 534 | # CONFIG_W1 is not set | ||
| 535 | # CONFIG_POWER_SUPPLY is not set | ||
| 536 | # CONFIG_HWMON is not set | ||
| 537 | # CONFIG_THERMAL is not set | ||
| 538 | # CONFIG_THERMAL_HWMON is not set | ||
| 539 | # CONFIG_WATCHDOG is not set | ||
| 540 | CONFIG_SSB_POSSIBLE=y | ||
| 541 | |||
| 542 | # | ||
| 543 | # Sonics Silicon Backplane | ||
| 544 | # | ||
| 545 | # CONFIG_SSB is not set | ||
| 546 | |||
| 547 | # | ||
| 548 | # Multifunction device drivers | ||
| 549 | # | ||
| 550 | # CONFIG_MFD_CORE is not set | ||
| 551 | # CONFIG_MFD_SM501 is not set | ||
| 552 | # CONFIG_MFD_ASIC3 is not set | ||
| 553 | # CONFIG_HTC_EGPIO is not set | ||
| 554 | # CONFIG_HTC_PASIC3 is not set | ||
| 555 | # CONFIG_MFD_TMIO is not set | ||
| 556 | # CONFIG_MFD_T7L66XB is not set | ||
| 557 | # CONFIG_MFD_TC6387XB is not set | ||
| 558 | # CONFIG_MFD_TC6393XB is not set | ||
| 559 | |||
| 560 | # | ||
| 561 | # Multimedia devices | ||
| 562 | # | ||
| 563 | |||
| 564 | # | ||
| 565 | # Multimedia core support | ||
| 566 | # | ||
| 567 | # CONFIG_VIDEO_DEV is not set | ||
| 568 | # CONFIG_DVB_CORE is not set | ||
| 569 | # CONFIG_VIDEO_MEDIA is not set | ||
| 570 | |||
| 571 | # | ||
| 572 | # Multimedia drivers | ||
| 573 | # | ||
| 574 | # CONFIG_DAB is not set | ||
| 575 | |||
| 576 | # | ||
| 577 | # Graphics support | ||
| 578 | # | ||
| 579 | # CONFIG_VGASTATE is not set | ||
| 580 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 581 | # CONFIG_FB is not set | ||
| 582 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 583 | |||
| 584 | # | ||
| 585 | # Display device support | ||
| 586 | # | ||
| 587 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 588 | |||
| 589 | # | ||
| 590 | # Console display driver support | ||
| 591 | # | ||
| 592 | # CONFIG_VGA_CONSOLE is not set | ||
| 593 | CONFIG_DUMMY_CONSOLE=y | ||
| 594 | # CONFIG_SOUND is not set | ||
| 595 | # CONFIG_HID_SUPPORT is not set | ||
| 596 | # CONFIG_USB_SUPPORT is not set | ||
| 597 | # CONFIG_MMC is not set | ||
| 598 | # CONFIG_MEMSTICK is not set | ||
| 599 | # CONFIG_ACCESSIBILITY is not set | ||
| 600 | # CONFIG_NEW_LEDS is not set | ||
| 601 | CONFIG_RTC_LIB=y | ||
| 602 | # CONFIG_RTC_CLASS is not set | ||
| 603 | # CONFIG_DMADEVICES is not set | ||
| 604 | # CONFIG_REGULATOR is not set | ||
| 605 | # CONFIG_UIO is not set | ||
| 606 | # CONFIG_STAGING is not set | ||
| 607 | |||
| 608 | # | ||
| 609 | # File systems | ||
| 610 | # | ||
| 611 | # CONFIG_EXT2_FS is not set | ||
| 612 | # CONFIG_EXT3_FS is not set | ||
| 613 | # CONFIG_EXT4_FS is not set | ||
| 614 | # CONFIG_REISERFS_FS is not set | ||
| 615 | # CONFIG_JFS_FS is not set | ||
| 616 | CONFIG_FS_POSIX_ACL=y | ||
| 617 | CONFIG_FILE_LOCKING=y | ||
| 618 | # CONFIG_XFS_FS is not set | ||
| 619 | # CONFIG_OCFS2_FS is not set | ||
| 620 | # CONFIG_BTRFS_FS is not set | ||
| 621 | CONFIG_DNOTIFY=y | ||
| 622 | CONFIG_INOTIFY=y | ||
| 623 | CONFIG_INOTIFY_USER=y | ||
| 624 | # CONFIG_QUOTA is not set | ||
| 625 | # CONFIG_AUTOFS_FS is not set | ||
| 626 | # CONFIG_AUTOFS4_FS is not set | ||
| 627 | # CONFIG_FUSE_FS is not set | ||
| 628 | CONFIG_GENERIC_ACL=y | ||
| 629 | |||
| 630 | # | ||
| 631 | # CD-ROM/DVD Filesystems | ||
| 632 | # | ||
| 633 | # CONFIG_ISO9660_FS is not set | ||
| 634 | # CONFIG_UDF_FS is not set | ||
| 635 | |||
| 636 | # | ||
| 637 | # DOS/FAT/NT Filesystems | ||
| 638 | # | ||
| 639 | # CONFIG_MSDOS_FS is not set | ||
| 640 | # CONFIG_VFAT_FS is not set | ||
| 641 | # CONFIG_NTFS_FS is not set | ||
| 642 | |||
| 643 | # | ||
| 644 | # Pseudo filesystems | ||
| 645 | # | ||
| 646 | CONFIG_PROC_FS=y | ||
| 647 | CONFIG_PROC_SYSCTL=y | ||
| 648 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 649 | CONFIG_SYSFS=y | ||
| 650 | CONFIG_TMPFS=y | ||
| 651 | CONFIG_TMPFS_POSIX_ACL=y | ||
| 652 | # CONFIG_HUGETLB_PAGE is not set | ||
| 653 | # CONFIG_CONFIGFS_FS is not set | ||
| 654 | CONFIG_MISC_FILESYSTEMS=y | ||
| 655 | # CONFIG_ADFS_FS is not set | ||
| 656 | # CONFIG_AFFS_FS is not set | ||
| 657 | # CONFIG_HFS_FS is not set | ||
| 658 | # CONFIG_HFSPLUS_FS is not set | ||
| 659 | # CONFIG_BEFS_FS is not set | ||
| 660 | # CONFIG_BFS_FS is not set | ||
| 661 | # CONFIG_EFS_FS is not set | ||
| 662 | CONFIG_CRAMFS=y | ||
| 663 | # CONFIG_SQUASHFS is not set | ||
| 664 | # CONFIG_VXFS_FS is not set | ||
| 665 | # CONFIG_MINIX_FS is not set | ||
| 666 | # CONFIG_OMFS_FS is not set | ||
| 667 | # CONFIG_HPFS_FS is not set | ||
| 668 | # CONFIG_QNX4FS_FS is not set | ||
| 669 | # CONFIG_ROMFS_FS is not set | ||
| 670 | # CONFIG_SYSV_FS is not set | ||
| 671 | # CONFIG_UFS_FS is not set | ||
| 672 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 673 | CONFIG_NFS_FS=y | ||
| 674 | CONFIG_NFS_V3=y | ||
| 675 | CONFIG_NFS_V3_ACL=y | ||
| 676 | CONFIG_NFS_V4=y | ||
| 677 | CONFIG_ROOT_NFS=y | ||
| 678 | # CONFIG_NFSD is not set | ||
| 679 | CONFIG_LOCKD=y | ||
| 680 | CONFIG_LOCKD_V4=y | ||
| 681 | CONFIG_NFS_ACL_SUPPORT=y | ||
| 682 | CONFIG_NFS_COMMON=y | ||
| 683 | CONFIG_SUNRPC=y | ||
| 684 | CONFIG_SUNRPC_GSS=y | ||
| 685 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 686 | CONFIG_RPCSEC_GSS_KRB5=y | ||
| 687 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 688 | # CONFIG_SMB_FS is not set | ||
| 689 | # CONFIG_CIFS is not set | ||
| 690 | # CONFIG_NCP_FS is not set | ||
| 691 | # CONFIG_CODA_FS is not set | ||
| 692 | # CONFIG_AFS_FS is not set | ||
| 693 | |||
| 694 | # | ||
| 695 | # Partition Types | ||
| 696 | # | ||
| 697 | # CONFIG_PARTITION_ADVANCED is not set | ||
| 698 | CONFIG_MSDOS_PARTITION=y | ||
| 699 | # CONFIG_NLS is not set | ||
| 700 | # CONFIG_DLM is not set | ||
| 701 | |||
| 702 | # | ||
| 703 | # Kernel hacking | ||
| 704 | # | ||
| 705 | CONFIG_PRINTK_TIME=y | ||
| 706 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 707 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 708 | CONFIG_FRAME_WARN=1024 | ||
| 709 | CONFIG_MAGIC_SYSRQ=y | ||
| 710 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 711 | # CONFIG_DEBUG_FS is not set | ||
| 712 | # CONFIG_HEADERS_CHECK is not set | ||
| 713 | CONFIG_DEBUG_KERNEL=y | ||
| 714 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 715 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 716 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 717 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 718 | CONFIG_SCHED_DEBUG=y | ||
| 719 | # CONFIG_SCHEDSTATS is not set | ||
| 720 | # CONFIG_TIMER_STATS is not set | ||
| 721 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 722 | # CONFIG_DEBUG_SLAB is not set | ||
| 723 | # CONFIG_DEBUG_PREEMPT is not set | ||
| 724 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 725 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 726 | # CONFIG_DEBUG_SPINLOCK is not set | ||
| 727 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 728 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 729 | # CONFIG_PROVE_LOCKING is not set | ||
| 730 | # CONFIG_LOCK_STAT is not set | ||
| 731 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | ||
| 732 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 733 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 734 | CONFIG_DEBUG_BUGVERBOSE=y | ||
| 735 | CONFIG_DEBUG_INFO=y | ||
| 736 | # CONFIG_DEBUG_VM is not set | ||
| 737 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 738 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 739 | # CONFIG_DEBUG_LIST is not set | ||
| 740 | # CONFIG_DEBUG_SG is not set | ||
| 741 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 742 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 743 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 744 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 745 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 746 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 747 | # CONFIG_FAULT_INJECTION is not set | ||
| 748 | # CONFIG_LATENCYTOP is not set | ||
| 749 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 750 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 751 | |||
| 752 | # | ||
| 753 | # Tracers | ||
| 754 | # | ||
| 755 | # CONFIG_FUNCTION_TRACER is not set | ||
| 756 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 757 | # CONFIG_PREEMPT_TRACER is not set | ||
| 758 | # CONFIG_SCHED_TRACER is not set | ||
| 759 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 760 | # CONFIG_BOOT_TRACER is not set | ||
| 761 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 762 | # CONFIG_STACK_TRACER is not set | ||
| 763 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 764 | # CONFIG_SAMPLES is not set | ||
| 765 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 766 | # CONFIG_KGDB is not set | ||
| 767 | CONFIG_ARM_UNWIND=y | ||
| 768 | CONFIG_DEBUG_USER=y | ||
| 769 | CONFIG_DEBUG_ERRORS=y | ||
| 770 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 771 | CONFIG_DEBUG_LL=y | ||
| 772 | # CONFIG_DEBUG_ICEDCC is not set | ||
| 773 | |||
| 774 | # | ||
| 775 | # Security options | ||
| 776 | # | ||
| 777 | # CONFIG_KEYS is not set | ||
| 778 | # CONFIG_SECURITY is not set | ||
| 779 | # CONFIG_SECURITYFS is not set | ||
| 780 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 781 | CONFIG_CRYPTO=y | ||
| 782 | |||
| 783 | # | ||
| 784 | # Crypto core or helper | ||
| 785 | # | ||
| 786 | # CONFIG_CRYPTO_FIPS is not set | ||
| 787 | CONFIG_CRYPTO_ALGAPI=y | ||
| 788 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 789 | CONFIG_CRYPTO_AEAD2=y | ||
| 790 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 791 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 792 | CONFIG_CRYPTO_HASH=y | ||
| 793 | CONFIG_CRYPTO_HASH2=y | ||
| 794 | CONFIG_CRYPTO_RNG2=y | ||
| 795 | CONFIG_CRYPTO_MANAGER=y | ||
| 796 | CONFIG_CRYPTO_MANAGER2=y | ||
| 797 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 798 | # CONFIG_CRYPTO_NULL is not set | ||
| 799 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 800 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 801 | # CONFIG_CRYPTO_TEST is not set | ||
| 802 | |||
| 803 | # | ||
| 804 | # Authenticated Encryption with Associated Data | ||
| 805 | # | ||
| 806 | # CONFIG_CRYPTO_CCM is not set | ||
| 807 | # CONFIG_CRYPTO_GCM is not set | ||
| 808 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 809 | |||
| 810 | # | ||
| 811 | # Block modes | ||
| 812 | # | ||
| 813 | CONFIG_CRYPTO_CBC=y | ||
| 814 | # CONFIG_CRYPTO_CTR is not set | ||
| 815 | # CONFIG_CRYPTO_CTS is not set | ||
| 816 | # CONFIG_CRYPTO_ECB is not set | ||
| 817 | # CONFIG_CRYPTO_LRW is not set | ||
| 818 | # CONFIG_CRYPTO_PCBC is not set | ||
| 819 | # CONFIG_CRYPTO_XTS is not set | ||
| 820 | |||
| 821 | # | ||
| 822 | # Hash modes | ||
| 823 | # | ||
| 824 | # CONFIG_CRYPTO_HMAC is not set | ||
| 825 | # CONFIG_CRYPTO_XCBC is not set | ||
| 826 | |||
| 827 | # | ||
| 828 | # Digest | ||
| 829 | # | ||
| 830 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 831 | # CONFIG_CRYPTO_MD4 is not set | ||
| 832 | CONFIG_CRYPTO_MD5=y | ||
| 833 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 834 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 835 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 836 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 837 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 838 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 839 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 840 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 841 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 842 | # CONFIG_CRYPTO_WP512 is not set | ||
| 843 | |||
| 844 | # | ||
| 845 | # Ciphers | ||
| 846 | # | ||
| 847 | # CONFIG_CRYPTO_AES is not set | ||
| 848 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 849 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 850 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 851 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 852 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 853 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 854 | CONFIG_CRYPTO_DES=y | ||
| 855 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 856 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 857 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 858 | # CONFIG_CRYPTO_SEED is not set | ||
| 859 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 860 | # CONFIG_CRYPTO_TEA is not set | ||
| 861 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 862 | |||
| 863 | # | ||
| 864 | # Compression | ||
| 865 | # | ||
| 866 | # CONFIG_CRYPTO_DEFLATE is not set | ||
| 867 | # CONFIG_CRYPTO_LZO is not set | ||
| 868 | |||
| 869 | # | ||
| 870 | # Random Number Generation | ||
| 871 | # | ||
| 872 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 873 | CONFIG_CRYPTO_HW=y | ||
| 874 | |||
| 875 | # | ||
| 876 | # Library routines | ||
| 877 | # | ||
| 878 | CONFIG_BITREVERSE=y | ||
| 879 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 880 | CONFIG_CRC_CCITT=y | ||
| 881 | # CONFIG_CRC16 is not set | ||
| 882 | # CONFIG_CRC_T10DIF is not set | ||
| 883 | # CONFIG_CRC_ITU_T is not set | ||
| 884 | CONFIG_CRC32=y | ||
| 885 | # CONFIG_CRC7 is not set | ||
| 886 | # CONFIG_LIBCRC32C is not set | ||
| 887 | CONFIG_ZLIB_INFLATE=y | ||
| 888 | CONFIG_PLIST=y | ||
| 889 | CONFIG_HAS_IOMEM=y | ||
| 890 | CONFIG_HAS_IOPORT=y | ||
| 891 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/rx51_defconfig b/arch/arm/configs/rx51_defconfig new file mode 100644 index 000000000000..593102da8cd7 --- /dev/null +++ b/arch/arm/configs/rx51_defconfig | |||
| @@ -0,0 +1,1821 @@ | |||
| 1 | # | ||
| 2 | # Automatically generated make config: don't edit | ||
| 3 | # Linux kernel version: 2.6.29-rc8 | ||
| 4 | # Fri Mar 13 15:28:56 2009 | ||
| 5 | # | ||
| 6 | CONFIG_ARM=y | ||
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | CONFIG_GENERIC_GPIO=y | ||
| 9 | CONFIG_GENERIC_TIME=y | ||
| 10 | CONFIG_GENERIC_CLOCKEVENTS=y | ||
| 11 | CONFIG_MMU=y | ||
| 12 | # CONFIG_NO_IOPORT is not set | ||
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | ||
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y | ||
| 25 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 26 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 27 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 28 | |||
| 29 | # | ||
| 30 | # General setup | ||
| 31 | # | ||
| 32 | CONFIG_EXPERIMENTAL=y | ||
| 33 | CONFIG_BROKEN_ON_SMP=y | ||
| 34 | CONFIG_INIT_ENV_ARG_LIMIT=32 | ||
| 35 | CONFIG_LOCALVERSION="" | ||
| 36 | CONFIG_LOCALVERSION_AUTO=y | ||
| 37 | CONFIG_SWAP=y | ||
| 38 | CONFIG_SYSVIPC=y | ||
| 39 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 40 | CONFIG_POSIX_MQUEUE=y | ||
| 41 | CONFIG_BSD_PROCESS_ACCT=y | ||
| 42 | # CONFIG_BSD_PROCESS_ACCT_V3 is not set | ||
| 43 | # CONFIG_TASKSTATS is not set | ||
| 44 | # CONFIG_AUDIT is not set | ||
| 45 | |||
| 46 | # | ||
| 47 | # RCU Subsystem | ||
| 48 | # | ||
| 49 | CONFIG_CLASSIC_RCU=y | ||
| 50 | # CONFIG_TREE_RCU is not set | ||
| 51 | # CONFIG_PREEMPT_RCU is not set | ||
| 52 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 53 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 54 | # CONFIG_IKCONFIG is not set | ||
| 55 | CONFIG_LOG_BUF_SHIFT=17 | ||
| 56 | CONFIG_GROUP_SCHED=y | ||
| 57 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 58 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 59 | CONFIG_USER_SCHED=y | ||
| 60 | # CONFIG_CGROUP_SCHED is not set | ||
| 61 | # CONFIG_CGROUPS is not set | ||
| 62 | CONFIG_SYSFS_DEPRECATED=y | ||
| 63 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 64 | # CONFIG_RELAY is not set | ||
| 65 | # CONFIG_NAMESPACES is not set | ||
| 66 | CONFIG_BLK_DEV_INITRD=y | ||
| 67 | CONFIG_INITRAMFS_SOURCE="" | ||
| 68 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 69 | CONFIG_SYSCTL=y | ||
| 70 | CONFIG_ANON_INODES=y | ||
| 71 | CONFIG_EMBEDDED=y | ||
| 72 | CONFIG_UID16=y | ||
| 73 | # CONFIG_SYSCTL_SYSCALL is not set | ||
| 74 | CONFIG_KALLSYMS=y | ||
| 75 | CONFIG_KALLSYMS_ALL=y | ||
| 76 | CONFIG_KALLSYMS_EXTRA_PASS=y | ||
| 77 | CONFIG_HOTPLUG=y | ||
| 78 | CONFIG_PRINTK=y | ||
| 79 | CONFIG_BUG=y | ||
| 80 | CONFIG_ELF_CORE=y | ||
| 81 | CONFIG_BASE_FULL=y | ||
| 82 | CONFIG_FUTEX=y | ||
| 83 | CONFIG_EPOLL=y | ||
| 84 | CONFIG_SIGNALFD=y | ||
| 85 | CONFIG_TIMERFD=y | ||
| 86 | CONFIG_EVENTFD=y | ||
| 87 | CONFIG_SHMEM=y | ||
| 88 | CONFIG_AIO=y | ||
| 89 | CONFIG_VM_EVENT_COUNTERS=y | ||
| 90 | CONFIG_COMPAT_BRK=y | ||
| 91 | CONFIG_SLAB=y | ||
| 92 | # CONFIG_SLUB is not set | ||
| 93 | # CONFIG_SLOB is not set | ||
| 94 | # CONFIG_PROFILING is not set | ||
| 95 | CONFIG_HAVE_OPROFILE=y | ||
| 96 | CONFIG_KPROBES=y | ||
| 97 | CONFIG_KRETPROBES=y | ||
| 98 | CONFIG_HAVE_KPROBES=y | ||
| 99 | CONFIG_HAVE_KRETPROBES=y | ||
| 100 | CONFIG_HAVE_CLK=y | ||
| 101 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 102 | CONFIG_SLABINFO=y | ||
| 103 | CONFIG_RT_MUTEXES=y | ||
| 104 | CONFIG_BASE_SMALL=0 | ||
| 105 | CONFIG_MODULES=y | ||
| 106 | CONFIG_MODULE_FORCE_LOAD=y | ||
| 107 | CONFIG_MODULE_UNLOAD=y | ||
| 108 | CONFIG_MODULE_FORCE_UNLOAD=y | ||
| 109 | CONFIG_MODVERSIONS=y | ||
| 110 | CONFIG_MODULE_SRCVERSION_ALL=y | ||
| 111 | CONFIG_BLOCK=y | ||
| 112 | # CONFIG_LBD is not set | ||
| 113 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 114 | # CONFIG_BLK_DEV_BSG is not set | ||
| 115 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 116 | |||
| 117 | # | ||
| 118 | # IO Schedulers | ||
| 119 | # | ||
| 120 | CONFIG_IOSCHED_NOOP=y | ||
| 121 | # CONFIG_IOSCHED_AS is not set | ||
| 122 | # CONFIG_IOSCHED_DEADLINE is not set | ||
| 123 | CONFIG_IOSCHED_CFQ=y | ||
| 124 | # CONFIG_DEFAULT_AS is not set | ||
| 125 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 126 | CONFIG_DEFAULT_CFQ=y | ||
| 127 | # CONFIG_DEFAULT_NOOP is not set | ||
| 128 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 129 | CONFIG_FREEZER=y | ||
| 130 | |||
| 131 | # | ||
| 132 | # System Type | ||
| 133 | # | ||
| 134 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 135 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 136 | # CONFIG_ARCH_REALVIEW is not set | ||
| 137 | # CONFIG_ARCH_VERSATILE is not set | ||
| 138 | # CONFIG_ARCH_AT91 is not set | ||
| 139 | # CONFIG_ARCH_CLPS711X is not set | ||
| 140 | # CONFIG_ARCH_EBSA110 is not set | ||
| 141 | # CONFIG_ARCH_EP93XX is not set | ||
| 142 | # CONFIG_ARCH_FOOTBRIDGE is not set | ||
| 143 | # CONFIG_ARCH_NETX is not set | ||
| 144 | # CONFIG_ARCH_H720X is not set | ||
| 145 | # CONFIG_ARCH_IMX is not set | ||
| 146 | # CONFIG_ARCH_IOP13XX is not set | ||
| 147 | # CONFIG_ARCH_IOP32X is not set | ||
| 148 | # CONFIG_ARCH_IOP33X is not set | ||
| 149 | # CONFIG_ARCH_IXP23XX is not set | ||
| 150 | # CONFIG_ARCH_IXP2000 is not set | ||
| 151 | # CONFIG_ARCH_IXP4XX is not set | ||
| 152 | # CONFIG_ARCH_L7200 is not set | ||
| 153 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 154 | # CONFIG_ARCH_KS8695 is not set | ||
| 155 | # CONFIG_ARCH_NS9XXX is not set | ||
| 156 | # CONFIG_ARCH_LOKI is not set | ||
| 157 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 158 | # CONFIG_ARCH_MXC is not set | ||
| 159 | # CONFIG_ARCH_ORION5X is not set | ||
| 160 | # CONFIG_ARCH_PNX4008 is not set | ||
| 161 | # CONFIG_ARCH_PXA is not set | ||
| 162 | # CONFIG_ARCH_RPC is not set | ||
| 163 | # CONFIG_ARCH_SA1100 is not set | ||
| 164 | # CONFIG_ARCH_S3C2410 is not set | ||
| 165 | # CONFIG_ARCH_S3C64XX is not set | ||
| 166 | # CONFIG_ARCH_SHARK is not set | ||
| 167 | # CONFIG_ARCH_LH7A40X is not set | ||
| 168 | # CONFIG_ARCH_DAVINCI is not set | ||
| 169 | CONFIG_ARCH_OMAP=y | ||
| 170 | # CONFIG_ARCH_MSM is not set | ||
| 171 | # CONFIG_ARCH_W90X900 is not set | ||
| 172 | |||
| 173 | # | ||
| 174 | # TI OMAP Implementations | ||
| 175 | # | ||
| 176 | CONFIG_ARCH_OMAP_OTG=y | ||
| 177 | # CONFIG_ARCH_OMAP1 is not set | ||
| 178 | # CONFIG_ARCH_OMAP2 is not set | ||
| 179 | CONFIG_ARCH_OMAP3=y | ||
| 180 | |||
| 181 | # | ||
| 182 | # OMAP Feature Selections | ||
| 183 | # | ||
| 184 | # CONFIG_OMAP_DEBUG_POWERDOMAIN is not set | ||
| 185 | # CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set | ||
| 186 | CONFIG_OMAP_RESET_CLOCKS=y | ||
| 187 | CONFIG_OMAP_MUX=y | ||
| 188 | CONFIG_OMAP_MUX_DEBUG=y | ||
| 189 | CONFIG_OMAP_MUX_WARNINGS=y | ||
| 190 | CONFIG_OMAP_MCBSP=y | ||
| 191 | # CONFIG_OMAP_MPU_TIMER is not set | ||
| 192 | CONFIG_OMAP_32K_TIMER=y | ||
| 193 | CONFIG_OMAP_32K_TIMER_HZ=128 | ||
| 194 | CONFIG_OMAP_DM_TIMER=y | ||
| 195 | # CONFIG_OMAP_LL_DEBUG_UART1 is not set | ||
| 196 | # CONFIG_OMAP_LL_DEBUG_UART2 is not set | ||
| 197 | CONFIG_OMAP_LL_DEBUG_UART3=y | ||
| 198 | CONFIG_OMAP_SERIAL_WAKE=y | ||
| 199 | CONFIG_ARCH_OMAP34XX=y | ||
| 200 | CONFIG_ARCH_OMAP3430=y | ||
| 201 | |||
| 202 | # | ||
| 203 | # OMAP Board Type | ||
| 204 | # | ||
| 205 | # CONFIG_MACH_OMAP3_BEAGLE is not set | ||
| 206 | # CONFIG_MACH_OMAP_LDP is not set | ||
| 207 | # CONFIG_MACH_OVERO is not set | ||
| 208 | # CONFIG_MACH_OMAP3_PANDORA is not set | ||
| 209 | # CONFIG_MACH_OMAP_3430SDP is not set | ||
| 210 | CONFIG_MACH_NOKIA_RX51=y | ||
| 211 | |||
| 212 | # | ||
| 213 | # Processor Type | ||
| 214 | # | ||
| 215 | CONFIG_CPU_32=y | ||
| 216 | CONFIG_CPU_32v6K=y | ||
| 217 | CONFIG_CPU_V7=y | ||
| 218 | CONFIG_CPU_32v7=y | ||
| 219 | CONFIG_CPU_ABRT_EV7=y | ||
| 220 | CONFIG_CPU_PABRT_IFAR=y | ||
| 221 | CONFIG_CPU_CACHE_V7=y | ||
| 222 | CONFIG_CPU_CACHE_VIPT=y | ||
| 223 | CONFIG_CPU_COPY_V6=y | ||
| 224 | CONFIG_CPU_TLB_V7=y | ||
| 225 | CONFIG_CPU_HAS_ASID=y | ||
| 226 | CONFIG_CPU_CP15=y | ||
| 227 | CONFIG_CPU_CP15_MMU=y | ||
| 228 | |||
| 229 | # | ||
| 230 | # Processor Features | ||
| 231 | # | ||
| 232 | CONFIG_ARM_THUMB=y | ||
| 233 | # CONFIG_ARM_THUMBEE is not set | ||
| 234 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 235 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 236 | # CONFIG_CPU_BPREDICT_DISABLE is not set | ||
| 237 | CONFIG_HAS_TLS_REG=y | ||
| 238 | # CONFIG_OUTER_CACHE is not set | ||
| 239 | |||
| 240 | # | ||
| 241 | # Bus support | ||
| 242 | # | ||
| 243 | # CONFIG_PCI_SYSCALL is not set | ||
| 244 | # CONFIG_ARCH_SUPPORTS_MSI is not set | ||
| 245 | # CONFIG_PCCARD is not set | ||
| 246 | |||
| 247 | # | ||
| 248 | # Kernel Features | ||
| 249 | # | ||
| 250 | CONFIG_TICK_ONESHOT=y | ||
| 251 | CONFIG_NO_HZ=y | ||
| 252 | CONFIG_HIGH_RES_TIMERS=y | ||
| 253 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | ||
| 254 | CONFIG_VMSPLIT_3G=y | ||
| 255 | # CONFIG_VMSPLIT_2G is not set | ||
| 256 | # CONFIG_VMSPLIT_1G is not set | ||
| 257 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 258 | # CONFIG_PREEMPT is not set | ||
| 259 | CONFIG_HZ=128 | ||
| 260 | CONFIG_AEABI=y | ||
| 261 | # CONFIG_OABI_COMPAT is not set | ||
| 262 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 263 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 264 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 265 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 266 | CONFIG_FLATMEM_MANUAL=y | ||
| 267 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 268 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 269 | CONFIG_FLATMEM=y | ||
| 270 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 271 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 272 | CONFIG_SPLIT_PTLOCK_CPUS=4 | ||
| 273 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 274 | CONFIG_ZONE_DMA_FLAG=0 | ||
| 275 | CONFIG_VIRT_TO_BUS=y | ||
| 276 | CONFIG_UNEVICTABLE_LRU=y | ||
| 277 | # CONFIG_LEDS is not set | ||
| 278 | CONFIG_ALIGNMENT_TRAP=y | ||
| 279 | |||
| 280 | # | ||
| 281 | # Boot options | ||
| 282 | # | ||
| 283 | CONFIG_ZBOOT_ROM_TEXT=0x0 | ||
| 284 | CONFIG_ZBOOT_ROM_BSS=0x0 | ||
| 285 | CONFIG_CMDLINE="init=/sbin/preinit ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs rw console=ttyMTD5" | ||
| 286 | # CONFIG_XIP_KERNEL is not set | ||
| 287 | # CONFIG_KEXEC is not set | ||
| 288 | |||
| 289 | # | ||
| 290 | # CPU Power Management | ||
| 291 | # | ||
| 292 | # CONFIG_CPU_FREQ is not set | ||
| 293 | # CONFIG_CPU_IDLE is not set | ||
| 294 | |||
| 295 | # | ||
| 296 | # Floating point emulation | ||
| 297 | # | ||
| 298 | |||
| 299 | # | ||
| 300 | # At least one emulation must be selected | ||
| 301 | # | ||
| 302 | CONFIG_VFP=y | ||
| 303 | CONFIG_VFPv3=y | ||
| 304 | CONFIG_NEON=y | ||
| 305 | |||
| 306 | # | ||
| 307 | # Userspace binary formats | ||
| 308 | # | ||
| 309 | CONFIG_BINFMT_ELF=y | ||
| 310 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 311 | CONFIG_HAVE_AOUT=y | ||
| 312 | # CONFIG_BINFMT_AOUT is not set | ||
| 313 | CONFIG_BINFMT_MISC=y | ||
| 314 | |||
| 315 | # | ||
| 316 | # Power management options | ||
| 317 | # | ||
| 318 | CONFIG_PM=y | ||
| 319 | CONFIG_PM_DEBUG=y | ||
| 320 | # CONFIG_PM_VERBOSE is not set | ||
| 321 | CONFIG_CAN_PM_TRACE=y | ||
| 322 | CONFIG_PM_SLEEP=y | ||
| 323 | CONFIG_SUSPEND=y | ||
| 324 | CONFIG_SUSPEND_FREEZER=y | ||
| 325 | # CONFIG_APM_EMULATION is not set | ||
| 326 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 327 | CONFIG_NET=y | ||
| 328 | |||
| 329 | # | ||
| 330 | # Networking options | ||
| 331 | # | ||
| 332 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 333 | CONFIG_PACKET=y | ||
| 334 | # CONFIG_PACKET_MMAP is not set | ||
| 335 | CONFIG_UNIX=y | ||
| 336 | CONFIG_XFRM=y | ||
| 337 | # CONFIG_XFRM_USER is not set | ||
| 338 | # CONFIG_XFRM_SUB_POLICY is not set | ||
| 339 | # CONFIG_XFRM_MIGRATE is not set | ||
| 340 | # CONFIG_XFRM_STATISTICS is not set | ||
| 341 | CONFIG_NET_KEY=y | ||
| 342 | # CONFIG_NET_KEY_MIGRATE is not set | ||
| 343 | CONFIG_INET=y | ||
| 344 | # CONFIG_IP_MULTICAST is not set | ||
| 345 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 346 | CONFIG_IP_FIB_HASH=y | ||
| 347 | CONFIG_IP_PNP=y | ||
| 348 | CONFIG_IP_PNP_DHCP=y | ||
| 349 | CONFIG_IP_PNP_BOOTP=y | ||
| 350 | CONFIG_IP_PNP_RARP=y | ||
| 351 | # CONFIG_NET_IPIP is not set | ||
| 352 | # CONFIG_NET_IPGRE is not set | ||
| 353 | # CONFIG_ARPD is not set | ||
| 354 | # CONFIG_SYN_COOKIES is not set | ||
| 355 | # CONFIG_INET_AH is not set | ||
| 356 | # CONFIG_INET_ESP is not set | ||
| 357 | # CONFIG_INET_IPCOMP is not set | ||
| 358 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 359 | # CONFIG_INET_TUNNEL is not set | ||
| 360 | CONFIG_INET_XFRM_MODE_TRANSPORT=y | ||
| 361 | CONFIG_INET_XFRM_MODE_TUNNEL=y | ||
| 362 | CONFIG_INET_XFRM_MODE_BEET=y | ||
| 363 | # CONFIG_INET_LRO is not set | ||
| 364 | CONFIG_INET_DIAG=y | ||
| 365 | CONFIG_INET_TCP_DIAG=y | ||
| 366 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 367 | CONFIG_TCP_CONG_CUBIC=y | ||
| 368 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 369 | # CONFIG_TCP_MD5SIG is not set | ||
| 370 | # CONFIG_IPV6 is not set | ||
| 371 | # CONFIG_NETLABEL is not set | ||
| 372 | # CONFIG_NETWORK_SECMARK is not set | ||
| 373 | CONFIG_NETFILTER=y | ||
| 374 | # CONFIG_NETFILTER_DEBUG is not set | ||
| 375 | CONFIG_NETFILTER_ADVANCED=y | ||
| 376 | |||
| 377 | # | ||
| 378 | # Core Netfilter Configuration | ||
| 379 | # | ||
| 380 | # CONFIG_NETFILTER_NETLINK_QUEUE is not set | ||
| 381 | # CONFIG_NETFILTER_NETLINK_LOG is not set | ||
| 382 | # CONFIG_NF_CONNTRACK is not set | ||
| 383 | CONFIG_NETFILTER_XTABLES=m | ||
| 384 | # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set | ||
| 385 | # CONFIG_NETFILTER_XT_TARGET_MARK is not set | ||
| 386 | # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set | ||
| 387 | # CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set | ||
| 388 | # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set | ||
| 389 | # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set | ||
| 390 | # CONFIG_NETFILTER_XT_MATCH_COMMENT is not set | ||
| 391 | # CONFIG_NETFILTER_XT_MATCH_DCCP is not set | ||
| 392 | # CONFIG_NETFILTER_XT_MATCH_DSCP is not set | ||
| 393 | # CONFIG_NETFILTER_XT_MATCH_ESP is not set | ||
| 394 | # CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set | ||
| 395 | # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set | ||
| 396 | # CONFIG_NETFILTER_XT_MATCH_LENGTH is not set | ||
| 397 | # CONFIG_NETFILTER_XT_MATCH_LIMIT is not set | ||
| 398 | # CONFIG_NETFILTER_XT_MATCH_MAC is not set | ||
| 399 | # CONFIG_NETFILTER_XT_MATCH_MARK is not set | ||
| 400 | # CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set | ||
| 401 | # CONFIG_NETFILTER_XT_MATCH_OWNER is not set | ||
| 402 | # CONFIG_NETFILTER_XT_MATCH_POLICY is not set | ||
| 403 | # CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set | ||
| 404 | # CONFIG_NETFILTER_XT_MATCH_QUOTA is not set | ||
| 405 | # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set | ||
| 406 | # CONFIG_NETFILTER_XT_MATCH_REALM is not set | ||
| 407 | # CONFIG_NETFILTER_XT_MATCH_RECENT is not set | ||
| 408 | # CONFIG_NETFILTER_XT_MATCH_SCTP is not set | ||
| 409 | # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set | ||
| 410 | # CONFIG_NETFILTER_XT_MATCH_STRING is not set | ||
| 411 | # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set | ||
| 412 | # CONFIG_NETFILTER_XT_MATCH_TIME is not set | ||
| 413 | # CONFIG_NETFILTER_XT_MATCH_U32 is not set | ||
| 414 | # CONFIG_IP_VS is not set | ||
| 415 | |||
| 416 | # | ||
| 417 | # IP: Netfilter Configuration | ||
| 418 | # | ||
| 419 | # CONFIG_NF_DEFRAG_IPV4 is not set | ||
| 420 | # CONFIG_IP_NF_QUEUE is not set | ||
| 421 | CONFIG_IP_NF_IPTABLES=m | ||
| 422 | # CONFIG_IP_NF_MATCH_ADDRTYPE is not set | ||
| 423 | # CONFIG_IP_NF_MATCH_AH is not set | ||
| 424 | # CONFIG_IP_NF_MATCH_ECN is not set | ||
| 425 | # CONFIG_IP_NF_MATCH_TTL is not set | ||
| 426 | CONFIG_IP_NF_FILTER=m | ||
| 427 | # CONFIG_IP_NF_TARGET_REJECT is not set | ||
| 428 | # CONFIG_IP_NF_TARGET_LOG is not set | ||
| 429 | # CONFIG_IP_NF_TARGET_ULOG is not set | ||
| 430 | # CONFIG_IP_NF_MANGLE is not set | ||
| 431 | # CONFIG_IP_NF_RAW is not set | ||
| 432 | # CONFIG_IP_NF_SECURITY is not set | ||
| 433 | # CONFIG_IP_NF_ARPTABLES is not set | ||
| 434 | # CONFIG_IP_DCCP is not set | ||
| 435 | # CONFIG_IP_SCTP is not set | ||
| 436 | # CONFIG_TIPC is not set | ||
| 437 | # CONFIG_ATM is not set | ||
| 438 | # CONFIG_BRIDGE is not set | ||
| 439 | # CONFIG_NET_DSA is not set | ||
| 440 | # CONFIG_VLAN_8021Q is not set | ||
| 441 | # CONFIG_DECNET is not set | ||
| 442 | # CONFIG_LLC2 is not set | ||
| 443 | # CONFIG_IPX is not set | ||
| 444 | # CONFIG_ATALK is not set | ||
| 445 | # CONFIG_X25 is not set | ||
| 446 | # CONFIG_LAPB is not set | ||
| 447 | # CONFIG_ECONET is not set | ||
| 448 | # CONFIG_WAN_ROUTER is not set | ||
| 449 | # CONFIG_NET_SCHED is not set | ||
| 450 | # CONFIG_DCB is not set | ||
| 451 | |||
| 452 | # | ||
| 453 | # Network testing | ||
| 454 | # | ||
| 455 | # CONFIG_NET_PKTGEN is not set | ||
| 456 | # CONFIG_NET_TCPPROBE is not set | ||
| 457 | # CONFIG_HAMRADIO is not set | ||
| 458 | # CONFIG_CAN is not set | ||
| 459 | # CONFIG_IRDA is not set | ||
| 460 | CONFIG_BT=m | ||
| 461 | CONFIG_BT_L2CAP=m | ||
| 462 | CONFIG_BT_SCO=m | ||
| 463 | CONFIG_BT_RFCOMM=m | ||
| 464 | CONFIG_BT_RFCOMM_TTY=y | ||
| 465 | CONFIG_BT_BNEP=m | ||
| 466 | CONFIG_BT_BNEP_MC_FILTER=y | ||
| 467 | CONFIG_BT_BNEP_PROTO_FILTER=y | ||
| 468 | CONFIG_BT_HIDP=m | ||
| 469 | |||
| 470 | # | ||
| 471 | # Bluetooth device drivers | ||
| 472 | # | ||
| 473 | # CONFIG_BT_HCIBTUSB is not set | ||
| 474 | # CONFIG_BT_HCIBTSDIO is not set | ||
| 475 | # CONFIG_BT_HCIUART is not set | ||
| 476 | # CONFIG_BT_HCIBCM203X is not set | ||
| 477 | # CONFIG_BT_HCIBPA10X is not set | ||
| 478 | # CONFIG_BT_HCIBFUSB is not set | ||
| 479 | # CONFIG_BT_HCIVHCI is not set | ||
| 480 | # CONFIG_AF_RXRPC is not set | ||
| 481 | # CONFIG_PHONET is not set | ||
| 482 | CONFIG_WIRELESS=y | ||
| 483 | CONFIG_CFG80211=y | ||
| 484 | # CONFIG_CFG80211_REG_DEBUG is not set | ||
| 485 | CONFIG_NL80211=y | ||
| 486 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 487 | CONFIG_WIRELESS_EXT=y | ||
| 488 | CONFIG_WIRELESS_EXT_SYSFS=y | ||
| 489 | # CONFIG_LIB80211 is not set | ||
| 490 | CONFIG_MAC80211=m | ||
| 491 | |||
| 492 | # | ||
| 493 | # Rate control algorithm selection | ||
| 494 | # | ||
| 495 | CONFIG_MAC80211_RC_PID=y | ||
| 496 | # CONFIG_MAC80211_RC_MINSTREL is not set | ||
| 497 | CONFIG_MAC80211_RC_DEFAULT_PID=y | ||
| 498 | # CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set | ||
| 499 | CONFIG_MAC80211_RC_DEFAULT="pid" | ||
| 500 | # CONFIG_MAC80211_MESH is not set | ||
| 501 | # CONFIG_MAC80211_LEDS is not set | ||
| 502 | # CONFIG_MAC80211_DEBUGFS is not set | ||
| 503 | # CONFIG_MAC80211_DEBUG_MENU is not set | ||
| 504 | # CONFIG_WIMAX is not set | ||
| 505 | # CONFIG_RFKILL is not set | ||
| 506 | # CONFIG_NET_9P is not set | ||
| 507 | |||
| 508 | # | ||
| 509 | # Device Drivers | ||
| 510 | # | ||
| 511 | |||
| 512 | # | ||
| 513 | # Generic Driver Options | ||
| 514 | # | ||
| 515 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 516 | CONFIG_STANDALONE=y | ||
| 517 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 518 | CONFIG_FW_LOADER=y | ||
| 519 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 520 | CONFIG_EXTRA_FIRMWARE="" | ||
| 521 | # CONFIG_DEBUG_DRIVER is not set | ||
| 522 | # CONFIG_DEBUG_DEVRES is not set | ||
| 523 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 524 | # CONFIG_CONNECTOR is not set | ||
| 525 | CONFIG_MTD=y | ||
| 526 | # CONFIG_MTD_DEBUG is not set | ||
| 527 | CONFIG_MTD_CONCAT=y | ||
| 528 | CONFIG_MTD_PARTITIONS=y | ||
| 529 | # CONFIG_MTD_TESTS is not set | ||
| 530 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 531 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 532 | # CONFIG_MTD_AFS_PARTS is not set | ||
| 533 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 534 | |||
| 535 | # | ||
| 536 | # User Modules And Translation Layers | ||
| 537 | # | ||
| 538 | CONFIG_MTD_CHAR=y | ||
| 539 | CONFIG_MTD_BLKDEVS=y | ||
| 540 | CONFIG_MTD_BLOCK=y | ||
| 541 | # CONFIG_FTL is not set | ||
| 542 | # CONFIG_NFTL is not set | ||
| 543 | # CONFIG_INFTL is not set | ||
| 544 | # CONFIG_RFD_FTL is not set | ||
| 545 | # CONFIG_SSFDC is not set | ||
| 546 | CONFIG_MTD_OOPS=y | ||
| 547 | |||
| 548 | # | ||
| 549 | # RAM/ROM/Flash chip drivers | ||
| 550 | # | ||
| 551 | CONFIG_MTD_CFI=y | ||
| 552 | # CONFIG_MTD_JEDECPROBE is not set | ||
| 553 | CONFIG_MTD_GEN_PROBE=y | ||
| 554 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 555 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 556 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 557 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 558 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 559 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 560 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 561 | CONFIG_MTD_CFI_I1=y | ||
| 562 | CONFIG_MTD_CFI_I2=y | ||
| 563 | # CONFIG_MTD_CFI_I4 is not set | ||
| 564 | # CONFIG_MTD_CFI_I8 is not set | ||
| 565 | CONFIG_MTD_CFI_INTELEXT=y | ||
| 566 | # CONFIG_MTD_CFI_AMDSTD is not set | ||
| 567 | # CONFIG_MTD_CFI_STAA is not set | ||
| 568 | CONFIG_MTD_CFI_UTIL=y | ||
| 569 | # CONFIG_MTD_RAM is not set | ||
| 570 | # CONFIG_MTD_ROM is not set | ||
| 571 | # CONFIG_MTD_ABSENT is not set | ||
| 572 | |||
| 573 | # | ||
| 574 | # Mapping drivers for chip access | ||
| 575 | # | ||
| 576 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 577 | # CONFIG_MTD_PHYSMAP is not set | ||
| 578 | # CONFIG_MTD_ARM_INTEGRATOR is not set | ||
| 579 | # CONFIG_MTD_OMAP_NOR is not set | ||
| 580 | # CONFIG_MTD_PLATRAM is not set | ||
| 581 | |||
| 582 | # | ||
| 583 | # Self-contained MTD device drivers | ||
| 584 | # | ||
| 585 | # CONFIG_MTD_DATAFLASH is not set | ||
| 586 | # CONFIG_MTD_M25P80 is not set | ||
| 587 | # CONFIG_MTD_SLRAM is not set | ||
| 588 | # CONFIG_MTD_PHRAM is not set | ||
| 589 | # CONFIG_MTD_MTDRAM is not set | ||
| 590 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 591 | |||
| 592 | # | ||
| 593 | # Disk-On-Chip Device Drivers | ||
| 594 | # | ||
| 595 | # CONFIG_MTD_DOC2000 is not set | ||
| 596 | # CONFIG_MTD_DOC2001 is not set | ||
| 597 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 598 | # CONFIG_MTD_NAND is not set | ||
| 599 | CONFIG_MTD_ONENAND=y | ||
| 600 | # CONFIG_MTD_ONENAND_VERIFY_WRITE is not set | ||
| 601 | # CONFIG_MTD_ONENAND_GENERIC is not set | ||
| 602 | CONFIG_MTD_ONENAND_OMAP2=y | ||
| 603 | # CONFIG_MTD_ONENAND_OTP is not set | ||
| 604 | # CONFIG_MTD_ONENAND_2X_PROGRAM is not set | ||
| 605 | # CONFIG_MTD_ONENAND_SIM is not set | ||
| 606 | |||
| 607 | # | ||
| 608 | # LPDDR flash memory drivers | ||
| 609 | # | ||
| 610 | # CONFIG_MTD_LPDDR is not set | ||
| 611 | |||
| 612 | # | ||
| 613 | # UBI - Unsorted block images | ||
| 614 | # | ||
| 615 | CONFIG_MTD_UBI=y | ||
| 616 | CONFIG_MTD_UBI_WL_THRESHOLD=4096 | ||
| 617 | CONFIG_MTD_UBI_BEB_RESERVE=1 | ||
| 618 | # CONFIG_MTD_UBI_GLUEBI is not set | ||
| 619 | |||
| 620 | # | ||
| 621 | # UBI debugging options | ||
| 622 | # | ||
| 623 | # CONFIG_MTD_UBI_DEBUG is not set | ||
| 624 | # CONFIG_PARPORT is not set | ||
| 625 | CONFIG_BLK_DEV=y | ||
| 626 | # CONFIG_BLK_DEV_COW_COMMON is not set | ||
| 627 | CONFIG_BLK_DEV_LOOP=y | ||
| 628 | # CONFIG_BLK_DEV_CRYPTOLOOP is not set | ||
| 629 | # CONFIG_BLK_DEV_NBD is not set | ||
| 630 | # CONFIG_BLK_DEV_UB is not set | ||
| 631 | CONFIG_BLK_DEV_RAM=y | ||
| 632 | CONFIG_BLK_DEV_RAM_COUNT=16 | ||
| 633 | CONFIG_BLK_DEV_RAM_SIZE=4096 | ||
| 634 | # CONFIG_BLK_DEV_XIP is not set | ||
| 635 | # CONFIG_CDROM_PKTCDVD is not set | ||
| 636 | # CONFIG_ATA_OVER_ETH is not set | ||
| 637 | CONFIG_MISC_DEVICES=y | ||
| 638 | # CONFIG_ICS932S401 is not set | ||
| 639 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 640 | # CONFIG_C2PORT is not set | ||
| 641 | |||
| 642 | # | ||
| 643 | # EEPROM support | ||
| 644 | # | ||
| 645 | # CONFIG_EEPROM_AT24 is not set | ||
| 646 | # CONFIG_EEPROM_AT25 is not set | ||
| 647 | # CONFIG_EEPROM_LEGACY is not set | ||
| 648 | # CONFIG_EEPROM_93CX6 is not set | ||
| 649 | CONFIG_HAVE_IDE=y | ||
| 650 | # CONFIG_IDE is not set | ||
| 651 | |||
| 652 | # | ||
| 653 | # SCSI device support | ||
| 654 | # | ||
| 655 | # CONFIG_RAID_ATTRS is not set | ||
| 656 | CONFIG_SCSI=m | ||
| 657 | CONFIG_SCSI_DMA=y | ||
| 658 | # CONFIG_SCSI_TGT is not set | ||
| 659 | # CONFIG_SCSI_NETLINK is not set | ||
| 660 | CONFIG_SCSI_PROC_FS=y | ||
| 661 | |||
| 662 | # | ||
| 663 | # SCSI support type (disk, tape, CD-ROM) | ||
| 664 | # | ||
| 665 | CONFIG_BLK_DEV_SD=m | ||
| 666 | # CONFIG_CHR_DEV_ST is not set | ||
| 667 | # CONFIG_CHR_DEV_OSST is not set | ||
| 668 | # CONFIG_BLK_DEV_SR is not set | ||
| 669 | # CONFIG_CHR_DEV_SG is not set | ||
| 670 | # CONFIG_CHR_DEV_SCH is not set | ||
| 671 | |||
| 672 | # | ||
| 673 | # Some SCSI devices (e.g. CD jukebox) support multiple LUNs | ||
| 674 | # | ||
| 675 | CONFIG_SCSI_MULTI_LUN=y | ||
| 676 | # CONFIG_SCSI_CONSTANTS is not set | ||
| 677 | # CONFIG_SCSI_LOGGING is not set | ||
| 678 | CONFIG_SCSI_SCAN_ASYNC=y | ||
| 679 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 680 | |||
| 681 | # | ||
| 682 | # SCSI Transports | ||
| 683 | # | ||
| 684 | # CONFIG_SCSI_SPI_ATTRS is not set | ||
| 685 | # CONFIG_SCSI_FC_ATTRS is not set | ||
| 686 | # CONFIG_SCSI_ISCSI_ATTRS is not set | ||
| 687 | # CONFIG_SCSI_SAS_LIBSAS is not set | ||
| 688 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 689 | CONFIG_SCSI_LOWLEVEL=y | ||
| 690 | # CONFIG_ISCSI_TCP is not set | ||
| 691 | # CONFIG_LIBFC is not set | ||
| 692 | # CONFIG_SCSI_DEBUG is not set | ||
| 693 | # CONFIG_SCSI_DH is not set | ||
| 694 | # CONFIG_ATA is not set | ||
| 695 | # CONFIG_MD is not set | ||
| 696 | CONFIG_NETDEVICES=y | ||
| 697 | # CONFIG_DUMMY is not set | ||
| 698 | # CONFIG_BONDING is not set | ||
| 699 | # CONFIG_MACVLAN is not set | ||
| 700 | # CONFIG_EQUALIZER is not set | ||
| 701 | CONFIG_TUN=m | ||
| 702 | # CONFIG_VETH is not set | ||
| 703 | # CONFIG_PHYLIB is not set | ||
| 704 | CONFIG_NET_ETHERNET=y | ||
| 705 | CONFIG_MII=m | ||
| 706 | # CONFIG_AX88796 is not set | ||
| 707 | CONFIG_SMC91X=m | ||
| 708 | # CONFIG_DM9000 is not set | ||
| 709 | # CONFIG_ENC28J60 is not set | ||
| 710 | # CONFIG_SMC911X is not set | ||
| 711 | # CONFIG_SMSC911X is not set | ||
| 712 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 713 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 714 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 715 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 716 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 717 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 718 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 719 | # CONFIG_B44 is not set | ||
| 720 | # CONFIG_NETDEV_1000 is not set | ||
| 721 | # CONFIG_NETDEV_10000 is not set | ||
| 722 | |||
| 723 | # | ||
| 724 | # Wireless LAN | ||
| 725 | # | ||
| 726 | # CONFIG_WLAN_PRE80211 is not set | ||
| 727 | CONFIG_WLAN_80211=y | ||
| 728 | # CONFIG_LIBERTAS is not set | ||
| 729 | # CONFIG_LIBERTAS_THINFIRM is not set | ||
| 730 | # CONFIG_USB_ZD1201 is not set | ||
| 731 | # CONFIG_USB_NET_RNDIS_WLAN is not set | ||
| 732 | # CONFIG_RTL8187 is not set | ||
| 733 | # CONFIG_MAC80211_HWSIM is not set | ||
| 734 | # CONFIG_P54_COMMON is not set | ||
| 735 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 736 | # CONFIG_HOSTAP is not set | ||
| 737 | # CONFIG_B43 is not set | ||
| 738 | # CONFIG_B43LEGACY is not set | ||
| 739 | # CONFIG_ZD1211RW is not set | ||
| 740 | # CONFIG_RT2X00 is not set | ||
| 741 | |||
| 742 | # | ||
| 743 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 744 | # | ||
| 745 | |||
| 746 | # | ||
| 747 | # USB Network Adapters | ||
| 748 | # | ||
| 749 | # CONFIG_USB_CATC is not set | ||
| 750 | # CONFIG_USB_KAWETH is not set | ||
| 751 | # CONFIG_USB_PEGASUS is not set | ||
| 752 | # CONFIG_USB_RTL8150 is not set | ||
| 753 | # CONFIG_USB_USBNET is not set | ||
| 754 | # CONFIG_WAN is not set | ||
| 755 | # CONFIG_PPP is not set | ||
| 756 | # CONFIG_SLIP is not set | ||
| 757 | # CONFIG_NETCONSOLE is not set | ||
| 758 | # CONFIG_NETPOLL is not set | ||
| 759 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 760 | # CONFIG_ISDN is not set | ||
| 761 | |||
| 762 | # | ||
| 763 | # Input device support | ||
| 764 | # | ||
| 765 | CONFIG_INPUT=y | ||
| 766 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 767 | # CONFIG_INPUT_POLLDEV is not set | ||
| 768 | |||
| 769 | # | ||
| 770 | # Userland interfaces | ||
| 771 | # | ||
| 772 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 773 | # CONFIG_INPUT_JOYDEV is not set | ||
| 774 | CONFIG_INPUT_EVDEV=y | ||
| 775 | # CONFIG_INPUT_EVBUG is not set | ||
| 776 | |||
| 777 | # | ||
| 778 | # Input Device Drivers | ||
| 779 | # | ||
| 780 | CONFIG_INPUT_KEYBOARD=y | ||
| 781 | # CONFIG_KEYBOARD_ATKBD is not set | ||
| 782 | # CONFIG_KEYBOARD_SUNKBD is not set | ||
| 783 | # CONFIG_KEYBOARD_LKKBD is not set | ||
| 784 | # CONFIG_KEYBOARD_XTKBD is not set | ||
| 785 | # CONFIG_KEYBOARD_NEWTON is not set | ||
| 786 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 787 | # CONFIG_KEYBOARD_GPIO is not set | ||
| 788 | # CONFIG_INPUT_MOUSE is not set | ||
| 789 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 790 | # CONFIG_INPUT_TABLET is not set | ||
| 791 | CONFIG_INPUT_TOUCHSCREEN=y | ||
| 792 | # CONFIG_TOUCHSCREEN_ADS7846 is not set | ||
| 793 | # CONFIG_TOUCHSCREEN_FUJITSU is not set | ||
| 794 | # CONFIG_TOUCHSCREEN_GUNZE is not set | ||
| 795 | # CONFIG_TOUCHSCREEN_ELO is not set | ||
| 796 | # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set | ||
| 797 | # CONFIG_TOUCHSCREEN_MTOUCH is not set | ||
| 798 | # CONFIG_TOUCHSCREEN_INEXIO is not set | ||
| 799 | # CONFIG_TOUCHSCREEN_MK712 is not set | ||
| 800 | # CONFIG_TOUCHSCREEN_PENMOUNT is not set | ||
| 801 | # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set | ||
| 802 | # CONFIG_TOUCHSCREEN_TOUCHWIN is not set | ||
| 803 | # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set | ||
| 804 | # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set | ||
| 805 | # CONFIG_TOUCHSCREEN_TSC2007 is not set | ||
| 806 | CONFIG_INPUT_MISC=y | ||
| 807 | # CONFIG_INPUT_ATI_REMOTE is not set | ||
| 808 | # CONFIG_INPUT_ATI_REMOTE2 is not set | ||
| 809 | # CONFIG_INPUT_KEYSPAN_REMOTE is not set | ||
| 810 | # CONFIG_INPUT_POWERMATE is not set | ||
| 811 | # CONFIG_INPUT_YEALINK is not set | ||
| 812 | # CONFIG_INPUT_CM109 is not set | ||
| 813 | CONFIG_INPUT_UINPUT=m | ||
| 814 | |||
| 815 | # | ||
| 816 | # Hardware I/O ports | ||
| 817 | # | ||
| 818 | # CONFIG_SERIO is not set | ||
| 819 | # CONFIG_GAMEPORT is not set | ||
| 820 | |||
| 821 | # | ||
| 822 | # Character devices | ||
| 823 | # | ||
| 824 | CONFIG_VT=y | ||
| 825 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 826 | CONFIG_VT_CONSOLE=y | ||
| 827 | CONFIG_HW_CONSOLE=y | ||
| 828 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 829 | CONFIG_DEVKMEM=y | ||
| 830 | # CONFIG_SERIAL_NONSTANDARD is not set | ||
| 831 | |||
| 832 | # | ||
| 833 | # Serial drivers | ||
| 834 | # | ||
| 835 | CONFIG_SERIAL_8250=y | ||
| 836 | CONFIG_SERIAL_8250_CONSOLE=y | ||
| 837 | CONFIG_SERIAL_8250_NR_UARTS=4 | ||
| 838 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | ||
| 839 | # CONFIG_SERIAL_8250_EXTENDED is not set | ||
| 840 | |||
| 841 | # | ||
| 842 | # Non-8250 serial port support | ||
| 843 | # | ||
| 844 | CONFIG_SERIAL_CORE=y | ||
| 845 | CONFIG_SERIAL_CORE_CONSOLE=y | ||
| 846 | CONFIG_UNIX98_PTYS=y | ||
| 847 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 848 | # CONFIG_LEGACY_PTYS is not set | ||
| 849 | # CONFIG_IPMI_HANDLER is not set | ||
| 850 | CONFIG_HW_RANDOM=m | ||
| 851 | # CONFIG_R3964 is not set | ||
| 852 | # CONFIG_RAW_DRIVER is not set | ||
| 853 | # CONFIG_TCG_TPM is not set | ||
| 854 | CONFIG_I2C=y | ||
| 855 | CONFIG_I2C_BOARDINFO=y | ||
| 856 | CONFIG_I2C_CHARDEV=y | ||
| 857 | CONFIG_I2C_HELPER_AUTO=y | ||
| 858 | |||
| 859 | # | ||
| 860 | # I2C Hardware Bus support | ||
| 861 | # | ||
| 862 | |||
| 863 | # | ||
| 864 | # I2C system bus drivers (mostly embedded / system-on-chip) | ||
| 865 | # | ||
| 866 | # CONFIG_I2C_GPIO is not set | ||
| 867 | # CONFIG_I2C_OCORES is not set | ||
| 868 | CONFIG_I2C_OMAP=y | ||
| 869 | # CONFIG_I2C_SIMTEC is not set | ||
| 870 | |||
| 871 | # | ||
| 872 | # External I2C/SMBus adapter drivers | ||
| 873 | # | ||
| 874 | # CONFIG_I2C_PARPORT_LIGHT is not set | ||
| 875 | # CONFIG_I2C_TAOS_EVM is not set | ||
| 876 | # CONFIG_I2C_TINY_USB is not set | ||
| 877 | |||
| 878 | # | ||
| 879 | # Other I2C/SMBus bus drivers | ||
| 880 | # | ||
| 881 | # CONFIG_I2C_PCA_PLATFORM is not set | ||
| 882 | # CONFIG_I2C_STUB is not set | ||
| 883 | |||
| 884 | # | ||
| 885 | # Miscellaneous I2C Chip support | ||
| 886 | # | ||
| 887 | # CONFIG_DS1682 is not set | ||
| 888 | # CONFIG_SENSORS_PCF8574 is not set | ||
| 889 | # CONFIG_PCF8575 is not set | ||
| 890 | # CONFIG_SENSORS_PCA9539 is not set | ||
| 891 | # CONFIG_SENSORS_PCF8591 is not set | ||
| 892 | # CONFIG_SENSORS_MAX6875 is not set | ||
| 893 | # CONFIG_SENSORS_TSL2550 is not set | ||
| 894 | # CONFIG_I2C_DEBUG_CORE is not set | ||
| 895 | # CONFIG_I2C_DEBUG_ALGO is not set | ||
| 896 | # CONFIG_I2C_DEBUG_BUS is not set | ||
| 897 | # CONFIG_I2C_DEBUG_CHIP is not set | ||
| 898 | CONFIG_SPI=y | ||
| 899 | # CONFIG_SPI_DEBUG is not set | ||
| 900 | CONFIG_SPI_MASTER=y | ||
| 901 | |||
| 902 | # | ||
| 903 | # SPI Master Controller Drivers | ||
| 904 | # | ||
| 905 | # CONFIG_SPI_BITBANG is not set | ||
| 906 | # CONFIG_SPI_GPIO is not set | ||
| 907 | CONFIG_SPI_OMAP24XX=y | ||
| 908 | |||
| 909 | # | ||
| 910 | # SPI Protocol Masters | ||
| 911 | # | ||
| 912 | # CONFIG_SPI_SPIDEV is not set | ||
| 913 | # CONFIG_SPI_TLE62X0 is not set | ||
| 914 | CONFIG_ARCH_REQUIRE_GPIOLIB=y | ||
| 915 | CONFIG_GPIOLIB=y | ||
| 916 | # CONFIG_DEBUG_GPIO is not set | ||
| 917 | CONFIG_GPIO_SYSFS=y | ||
| 918 | |||
| 919 | # | ||
| 920 | # Memory mapped GPIO expanders: | ||
| 921 | # | ||
| 922 | |||
| 923 | # | ||
| 924 | # I2C GPIO expanders: | ||
| 925 | # | ||
| 926 | # CONFIG_GPIO_MAX732X is not set | ||
| 927 | # CONFIG_GPIO_PCA953X is not set | ||
| 928 | # CONFIG_GPIO_PCF857X is not set | ||
| 929 | CONFIG_GPIO_TWL4030=y | ||
| 930 | |||
| 931 | # | ||
| 932 | # PCI GPIO expanders: | ||
| 933 | # | ||
| 934 | |||
| 935 | # | ||
| 936 | # SPI GPIO expanders: | ||
| 937 | # | ||
| 938 | # CONFIG_GPIO_MAX7301 is not set | ||
| 939 | # CONFIG_GPIO_MCP23S08 is not set | ||
| 940 | # CONFIG_W1 is not set | ||
| 941 | # CONFIG_POWER_SUPPLY is not set | ||
| 942 | CONFIG_HWMON=y | ||
| 943 | # CONFIG_HWMON_VID is not set | ||
| 944 | # CONFIG_SENSORS_AD7414 is not set | ||
| 945 | # CONFIG_SENSORS_AD7418 is not set | ||
| 946 | # CONFIG_SENSORS_ADCXX is not set | ||
| 947 | # CONFIG_SENSORS_ADM1021 is not set | ||
| 948 | # CONFIG_SENSORS_ADM1025 is not set | ||
| 949 | # CONFIG_SENSORS_ADM1026 is not set | ||
| 950 | # CONFIG_SENSORS_ADM1029 is not set | ||
| 951 | # CONFIG_SENSORS_ADM1031 is not set | ||
| 952 | # CONFIG_SENSORS_ADM9240 is not set | ||
| 953 | # CONFIG_SENSORS_ADT7462 is not set | ||
| 954 | # CONFIG_SENSORS_ADT7470 is not set | ||
| 955 | # CONFIG_SENSORS_ADT7473 is not set | ||
| 956 | # CONFIG_SENSORS_ADT7475 is not set | ||
| 957 | # CONFIG_SENSORS_ATXP1 is not set | ||
| 958 | # CONFIG_SENSORS_DS1621 is not set | ||
| 959 | # CONFIG_SENSORS_F71805F is not set | ||
| 960 | # CONFIG_SENSORS_F71882FG is not set | ||
| 961 | # CONFIG_SENSORS_F75375S is not set | ||
| 962 | # CONFIG_SENSORS_GL518SM is not set | ||
| 963 | # CONFIG_SENSORS_GL520SM is not set | ||
| 964 | # CONFIG_SENSORS_IT87 is not set | ||
| 965 | # CONFIG_SENSORS_LM63 is not set | ||
| 966 | # CONFIG_SENSORS_LM70 is not set | ||
| 967 | # CONFIG_SENSORS_LM75 is not set | ||
| 968 | # CONFIG_SENSORS_LM77 is not set | ||
| 969 | # CONFIG_SENSORS_LM78 is not set | ||
| 970 | # CONFIG_SENSORS_LM80 is not set | ||
| 971 | # CONFIG_SENSORS_LM83 is not set | ||
| 972 | # CONFIG_SENSORS_LM85 is not set | ||
| 973 | # CONFIG_SENSORS_LM87 is not set | ||
| 974 | # CONFIG_SENSORS_LM90 is not set | ||
| 975 | # CONFIG_SENSORS_LM92 is not set | ||
| 976 | # CONFIG_SENSORS_LM93 is not set | ||
| 977 | # CONFIG_SENSORS_LTC4245 is not set | ||
| 978 | # CONFIG_SENSORS_MAX1111 is not set | ||
| 979 | # CONFIG_SENSORS_MAX1619 is not set | ||
| 980 | # CONFIG_SENSORS_MAX6650 is not set | ||
| 981 | # CONFIG_SENSORS_PC87360 is not set | ||
| 982 | # CONFIG_SENSORS_PC87427 is not set | ||
| 983 | # CONFIG_SENSORS_DME1737 is not set | ||
| 984 | # CONFIG_SENSORS_SMSC47M1 is not set | ||
| 985 | # CONFIG_SENSORS_SMSC47M192 is not set | ||
| 986 | # CONFIG_SENSORS_SMSC47B397 is not set | ||
| 987 | # CONFIG_SENSORS_ADS7828 is not set | ||
| 988 | # CONFIG_SENSORS_THMC50 is not set | ||
| 989 | # CONFIG_SENSORS_VT1211 is not set | ||
| 990 | # CONFIG_SENSORS_W83781D is not set | ||
| 991 | # CONFIG_SENSORS_W83791D is not set | ||
| 992 | # CONFIG_SENSORS_W83792D is not set | ||
| 993 | # CONFIG_SENSORS_W83793 is not set | ||
| 994 | # CONFIG_SENSORS_W83L785TS is not set | ||
| 995 | # CONFIG_SENSORS_W83L786NG is not set | ||
| 996 | # CONFIG_SENSORS_W83627HF is not set | ||
| 997 | # CONFIG_SENSORS_W83627EHF is not set | ||
| 998 | # CONFIG_HWMON_DEBUG_CHIP is not set | ||
| 999 | # CONFIG_THERMAL is not set | ||
| 1000 | # CONFIG_THERMAL_HWMON is not set | ||
| 1001 | CONFIG_WATCHDOG=y | ||
| 1002 | # CONFIG_WATCHDOG_NOWAYOUT is not set | ||
| 1003 | |||
| 1004 | # | ||
| 1005 | # Watchdog Device Drivers | ||
| 1006 | # | ||
| 1007 | # CONFIG_SOFT_WATCHDOG is not set | ||
| 1008 | CONFIG_OMAP_WATCHDOG=m | ||
| 1009 | |||
| 1010 | # | ||
| 1011 | # USB-based Watchdog Cards | ||
| 1012 | # | ||
| 1013 | # CONFIG_USBPCWATCHDOG is not set | ||
| 1014 | CONFIG_SSB_POSSIBLE=y | ||
| 1015 | |||
| 1016 | # | ||
| 1017 | # Sonics Silicon Backplane | ||
| 1018 | # | ||
| 1019 | # CONFIG_SSB is not set | ||
| 1020 | |||
| 1021 | # | ||
| 1022 | # Multifunction device drivers | ||
| 1023 | # | ||
| 1024 | # CONFIG_MFD_CORE is not set | ||
| 1025 | # CONFIG_MFD_SM501 is not set | ||
| 1026 | # CONFIG_MFD_ASIC3 is not set | ||
| 1027 | # CONFIG_HTC_EGPIO is not set | ||
| 1028 | # CONFIG_HTC_PASIC3 is not set | ||
| 1029 | # CONFIG_TPS65010 is not set | ||
| 1030 | CONFIG_TWL4030_CORE=y | ||
| 1031 | # CONFIG_MFD_TMIO is not set | ||
| 1032 | # CONFIG_MFD_T7L66XB is not set | ||
| 1033 | # CONFIG_MFD_TC6387XB is not set | ||
| 1034 | # CONFIG_MFD_TC6393XB is not set | ||
| 1035 | # CONFIG_PMIC_DA903X is not set | ||
| 1036 | # CONFIG_MFD_WM8400 is not set | ||
| 1037 | # CONFIG_MFD_WM8350_I2C is not set | ||
| 1038 | # CONFIG_MFD_PCF50633 is not set | ||
| 1039 | |||
| 1040 | # | ||
| 1041 | # Multimedia devices | ||
| 1042 | # | ||
| 1043 | |||
| 1044 | # | ||
| 1045 | # Multimedia core support | ||
| 1046 | # | ||
| 1047 | CONFIG_VIDEO_DEV=m | ||
| 1048 | CONFIG_VIDEO_V4L2_COMMON=m | ||
| 1049 | CONFIG_VIDEO_ALLOW_V4L1=y | ||
| 1050 | CONFIG_VIDEO_V4L1_COMPAT=y | ||
| 1051 | # CONFIG_DVB_CORE is not set | ||
| 1052 | CONFIG_VIDEO_MEDIA=m | ||
| 1053 | |||
| 1054 | # | ||
| 1055 | # Multimedia drivers | ||
| 1056 | # | ||
| 1057 | # CONFIG_MEDIA_ATTACH is not set | ||
| 1058 | CONFIG_MEDIA_TUNER=m | ||
| 1059 | # CONFIG_MEDIA_TUNER_CUSTOMIZE is not set | ||
| 1060 | CONFIG_MEDIA_TUNER_SIMPLE=m | ||
| 1061 | CONFIG_MEDIA_TUNER_TDA8290=m | ||
| 1062 | CONFIG_MEDIA_TUNER_TDA9887=m | ||
| 1063 | CONFIG_MEDIA_TUNER_TEA5761=m | ||
| 1064 | CONFIG_MEDIA_TUNER_TEA5767=m | ||
| 1065 | CONFIG_MEDIA_TUNER_MT20XX=m | ||
| 1066 | CONFIG_MEDIA_TUNER_XC2028=m | ||
| 1067 | CONFIG_MEDIA_TUNER_XC5000=m | ||
| 1068 | CONFIG_VIDEO_V4L2=m | ||
| 1069 | CONFIG_VIDEO_V4L1=m | ||
| 1070 | CONFIG_VIDEO_CAPTURE_DRIVERS=y | ||
| 1071 | # CONFIG_VIDEO_ADV_DEBUG is not set | ||
| 1072 | # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set | ||
| 1073 | CONFIG_VIDEO_HELPER_CHIPS_AUTO=y | ||
| 1074 | # CONFIG_VIDEO_VIVI is not set | ||
| 1075 | # CONFIG_VIDEO_CPIA is not set | ||
| 1076 | # CONFIG_VIDEO_CPIA2 is not set | ||
| 1077 | # CONFIG_VIDEO_SAA5246A is not set | ||
| 1078 | # CONFIG_VIDEO_SAA5249 is not set | ||
| 1079 | # CONFIG_SOC_CAMERA is not set | ||
| 1080 | CONFIG_V4L_USB_DRIVERS=y | ||
| 1081 | # CONFIG_USB_VIDEO_CLASS is not set | ||
| 1082 | # CONFIG_USB_GSPCA is not set | ||
| 1083 | # CONFIG_VIDEO_PVRUSB2 is not set | ||
| 1084 | # CONFIG_VIDEO_EM28XX is not set | ||
| 1085 | # CONFIG_VIDEO_USBVISION is not set | ||
| 1086 | # CONFIG_USB_VICAM is not set | ||
| 1087 | # CONFIG_USB_IBMCAM is not set | ||
| 1088 | # CONFIG_USB_KONICAWC is not set | ||
| 1089 | # CONFIG_USB_QUICKCAM_MESSENGER is not set | ||
| 1090 | # CONFIG_USB_ET61X251 is not set | ||
| 1091 | # CONFIG_VIDEO_OVCAMCHIP is not set | ||
| 1092 | # CONFIG_USB_OV511 is not set | ||
| 1093 | # CONFIG_USB_SE401 is not set | ||
| 1094 | # CONFIG_USB_SN9C102 is not set | ||
| 1095 | # CONFIG_USB_STV680 is not set | ||
| 1096 | # CONFIG_USB_ZC0301 is not set | ||
| 1097 | # CONFIG_USB_PWC is not set | ||
| 1098 | # CONFIG_USB_ZR364XX is not set | ||
| 1099 | # CONFIG_USB_STKWEBCAM is not set | ||
| 1100 | # CONFIG_USB_S2255 is not set | ||
| 1101 | CONFIG_RADIO_ADAPTERS=y | ||
| 1102 | # CONFIG_USB_DSBR is not set | ||
| 1103 | # CONFIG_USB_SI470X is not set | ||
| 1104 | # CONFIG_USB_MR800 is not set | ||
| 1105 | # CONFIG_RADIO_TEA5764 is not set | ||
| 1106 | # CONFIG_DAB is not set | ||
| 1107 | |||
| 1108 | # | ||
| 1109 | # Graphics support | ||
| 1110 | # | ||
| 1111 | # CONFIG_VGASTATE is not set | ||
| 1112 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 1113 | # CONFIG_FB is not set | ||
| 1114 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 1115 | |||
| 1116 | # | ||
| 1117 | # Display device support | ||
| 1118 | # | ||
| 1119 | CONFIG_DISPLAY_SUPPORT=y | ||
| 1120 | |||
| 1121 | # | ||
| 1122 | # Display hardware drivers | ||
| 1123 | # | ||
| 1124 | |||
| 1125 | # | ||
| 1126 | # Console display driver support | ||
| 1127 | # | ||
| 1128 | # CONFIG_VGA_CONSOLE is not set | ||
| 1129 | CONFIG_DUMMY_CONSOLE=y | ||
| 1130 | CONFIG_SOUND=y | ||
| 1131 | # CONFIG_SOUND_OSS_CORE is not set | ||
| 1132 | CONFIG_SND=y | ||
| 1133 | CONFIG_SND_TIMER=y | ||
| 1134 | CONFIG_SND_PCM=y | ||
| 1135 | # CONFIG_SND_SEQUENCER is not set | ||
| 1136 | # CONFIG_SND_MIXER_OSS is not set | ||
| 1137 | # CONFIG_SND_PCM_OSS is not set | ||
| 1138 | # CONFIG_SND_HRTIMER is not set | ||
| 1139 | # CONFIG_SND_DYNAMIC_MINORS is not set | ||
| 1140 | CONFIG_SND_SUPPORT_OLD_API=y | ||
| 1141 | CONFIG_SND_VERBOSE_PROCFS=y | ||
| 1142 | # CONFIG_SND_VERBOSE_PRINTK is not set | ||
| 1143 | # CONFIG_SND_DEBUG is not set | ||
| 1144 | CONFIG_SND_DRIVERS=y | ||
| 1145 | # CONFIG_SND_DUMMY is not set | ||
| 1146 | # CONFIG_SND_MTPAV is not set | ||
| 1147 | # CONFIG_SND_SERIAL_U16550 is not set | ||
| 1148 | # CONFIG_SND_MPU401 is not set | ||
| 1149 | CONFIG_SND_ARM=y | ||
| 1150 | CONFIG_SND_SPI=y | ||
| 1151 | # CONFIG_SND_USB is not set | ||
| 1152 | CONFIG_SND_SOC=y | ||
| 1153 | CONFIG_SND_OMAP_SOC=y | ||
| 1154 | CONFIG_SND_SOC_I2C_AND_SPI=y | ||
| 1155 | # CONFIG_SND_SOC_ALL_CODECS is not set | ||
| 1156 | # CONFIG_SOUND_PRIME is not set | ||
| 1157 | CONFIG_HID_SUPPORT=y | ||
| 1158 | CONFIG_HID=m | ||
| 1159 | # CONFIG_HID_DEBUG is not set | ||
| 1160 | # CONFIG_HIDRAW is not set | ||
| 1161 | |||
| 1162 | # | ||
| 1163 | # USB Input Devices | ||
| 1164 | # | ||
| 1165 | CONFIG_USB_HID=m | ||
| 1166 | # CONFIG_HID_PID is not set | ||
| 1167 | # CONFIG_USB_HIDDEV is not set | ||
| 1168 | |||
| 1169 | # | ||
| 1170 | # USB HID Boot Protocol drivers | ||
| 1171 | # | ||
| 1172 | # CONFIG_USB_KBD is not set | ||
| 1173 | # CONFIG_USB_MOUSE is not set | ||
| 1174 | |||
| 1175 | # | ||
| 1176 | # Special HID drivers | ||
| 1177 | # | ||
| 1178 | CONFIG_HID_COMPAT=y | ||
| 1179 | CONFIG_HID_A4TECH=m | ||
| 1180 | CONFIG_HID_APPLE=m | ||
| 1181 | CONFIG_HID_BELKIN=m | ||
| 1182 | CONFIG_HID_CHERRY=m | ||
| 1183 | CONFIG_HID_CHICONY=m | ||
| 1184 | CONFIG_HID_CYPRESS=m | ||
| 1185 | CONFIG_HID_EZKEY=m | ||
| 1186 | CONFIG_HID_GYRATION=m | ||
| 1187 | CONFIG_HID_LOGITECH=m | ||
| 1188 | # CONFIG_LOGITECH_FF is not set | ||
| 1189 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | ||
| 1190 | CONFIG_HID_MICROSOFT=m | ||
| 1191 | CONFIG_HID_MONTEREY=m | ||
| 1192 | # CONFIG_HID_NTRIG is not set | ||
| 1193 | CONFIG_HID_PANTHERLORD=m | ||
| 1194 | # CONFIG_PANTHERLORD_FF is not set | ||
| 1195 | CONFIG_HID_PETALYNX=m | ||
| 1196 | CONFIG_HID_SAMSUNG=m | ||
| 1197 | CONFIG_HID_SONY=m | ||
| 1198 | CONFIG_HID_SUNPLUS=m | ||
| 1199 | # CONFIG_GREENASIA_FF is not set | ||
| 1200 | # CONFIG_HID_TOPSEED is not set | ||
| 1201 | # CONFIG_THRUSTMASTER_FF is not set | ||
| 1202 | # CONFIG_ZEROPLUS_FF is not set | ||
| 1203 | CONFIG_USB_SUPPORT=y | ||
| 1204 | CONFIG_USB_ARCH_HAS_HCD=y | ||
| 1205 | CONFIG_USB_ARCH_HAS_OHCI=y | ||
| 1206 | # CONFIG_USB_ARCH_HAS_EHCI is not set | ||
| 1207 | CONFIG_USB=y | ||
| 1208 | CONFIG_USB_DEBUG=y | ||
| 1209 | CONFIG_USB_ANNOUNCE_NEW_DEVICES=y | ||
| 1210 | |||
| 1211 | # | ||
| 1212 | # Miscellaneous USB options | ||
| 1213 | # | ||
| 1214 | CONFIG_USB_DEVICEFS=y | ||
| 1215 | CONFIG_USB_DEVICE_CLASS=y | ||
| 1216 | # CONFIG_USB_DYNAMIC_MINORS is not set | ||
| 1217 | CONFIG_USB_SUSPEND=y | ||
| 1218 | CONFIG_USB_OTG=y | ||
| 1219 | CONFIG_USB_OTG_WHITELIST=y | ||
| 1220 | CONFIG_USB_OTG_BLACKLIST_HUB=y | ||
| 1221 | CONFIG_USB_MON=y | ||
| 1222 | # CONFIG_USB_WUSB is not set | ||
| 1223 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1224 | |||
| 1225 | # | ||
| 1226 | # USB Host Controller Drivers | ||
| 1227 | # | ||
| 1228 | # CONFIG_USB_C67X00_HCD is not set | ||
| 1229 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1230 | # CONFIG_USB_ISP116X_HCD is not set | ||
| 1231 | # CONFIG_USB_OHCI_HCD is not set | ||
| 1232 | # CONFIG_USB_SL811_HCD is not set | ||
| 1233 | # CONFIG_USB_R8A66597_HCD is not set | ||
| 1234 | # CONFIG_USB_HWA_HCD is not set | ||
| 1235 | CONFIG_USB_MUSB_HDRC=y | ||
| 1236 | CONFIG_USB_MUSB_SOC=y | ||
| 1237 | |||
| 1238 | # | ||
| 1239 | # OMAP 343x high speed USB support | ||
| 1240 | # | ||
| 1241 | # CONFIG_USB_MUSB_HOST is not set | ||
| 1242 | # CONFIG_USB_MUSB_PERIPHERAL is not set | ||
| 1243 | CONFIG_USB_MUSB_OTG=y | ||
| 1244 | CONFIG_USB_GADGET_MUSB_HDRC=y | ||
| 1245 | CONFIG_USB_MUSB_HDRC_HCD=y | ||
| 1246 | # CONFIG_MUSB_PIO_ONLY is not set | ||
| 1247 | CONFIG_USB_INVENTRA_DMA=y | ||
| 1248 | # CONFIG_USB_TI_CPPI_DMA is not set | ||
| 1249 | # CONFIG_USB_MUSB_DEBUG is not set | ||
| 1250 | |||
| 1251 | # | ||
| 1252 | # USB Device Class drivers | ||
| 1253 | # | ||
| 1254 | # CONFIG_USB_ACM is not set | ||
| 1255 | # CONFIG_USB_PRINTER is not set | ||
| 1256 | # CONFIG_USB_WDM is not set | ||
| 1257 | # CONFIG_USB_TMC is not set | ||
| 1258 | |||
| 1259 | # | ||
| 1260 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; | ||
| 1261 | # | ||
| 1262 | |||
| 1263 | # | ||
| 1264 | # see USB_STORAGE Help for more information | ||
| 1265 | # | ||
| 1266 | CONFIG_USB_STORAGE=m | ||
| 1267 | # CONFIG_USB_STORAGE_DEBUG is not set | ||
| 1268 | # CONFIG_USB_STORAGE_DATAFAB is not set | ||
| 1269 | # CONFIG_USB_STORAGE_FREECOM is not set | ||
| 1270 | # CONFIG_USB_STORAGE_ISD200 is not set | ||
| 1271 | # CONFIG_USB_STORAGE_USBAT is not set | ||
| 1272 | # CONFIG_USB_STORAGE_SDDR09 is not set | ||
| 1273 | # CONFIG_USB_STORAGE_SDDR55 is not set | ||
| 1274 | # CONFIG_USB_STORAGE_JUMPSHOT is not set | ||
| 1275 | # CONFIG_USB_STORAGE_ALAUDA is not set | ||
| 1276 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 1277 | # CONFIG_USB_STORAGE_KARMA is not set | ||
| 1278 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 1279 | CONFIG_USB_LIBUSUAL=y | ||
| 1280 | |||
| 1281 | # | ||
| 1282 | # USB Imaging devices | ||
| 1283 | # | ||
| 1284 | # CONFIG_USB_MDC800 is not set | ||
| 1285 | # CONFIG_USB_MICROTEK is not set | ||
| 1286 | |||
| 1287 | # | ||
| 1288 | # USB port drivers | ||
| 1289 | # | ||
| 1290 | # CONFIG_USB_SERIAL is not set | ||
| 1291 | |||
| 1292 | # | ||
| 1293 | # USB Miscellaneous drivers | ||
| 1294 | # | ||
| 1295 | # CONFIG_USB_EMI62 is not set | ||
| 1296 | # CONFIG_USB_EMI26 is not set | ||
| 1297 | # CONFIG_USB_ADUTUX is not set | ||
| 1298 | # CONFIG_USB_SEVSEG is not set | ||
| 1299 | # CONFIG_USB_RIO500 is not set | ||
| 1300 | # CONFIG_USB_LEGOTOWER is not set | ||
| 1301 | # CONFIG_USB_LCD is not set | ||
| 1302 | # CONFIG_USB_BERRY_CHARGE is not set | ||
| 1303 | # CONFIG_USB_LED is not set | ||
| 1304 | # CONFIG_USB_CYPRESS_CY7C63 is not set | ||
| 1305 | # CONFIG_USB_CYTHERM is not set | ||
| 1306 | # CONFIG_USB_PHIDGET is not set | ||
| 1307 | # CONFIG_USB_IDMOUSE is not set | ||
| 1308 | # CONFIG_USB_FTDI_ELAN is not set | ||
| 1309 | # CONFIG_USB_APPLEDISPLAY is not set | ||
| 1310 | # CONFIG_USB_LD is not set | ||
| 1311 | # CONFIG_USB_TRANCEVIBRATOR is not set | ||
| 1312 | # CONFIG_USB_IOWARRIOR is not set | ||
| 1313 | CONFIG_USB_TEST=m | ||
| 1314 | # CONFIG_USB_ISIGHTFW is not set | ||
| 1315 | # CONFIG_USB_VST is not set | ||
| 1316 | CONFIG_USB_GADGET=m | ||
| 1317 | CONFIG_USB_GADGET_DEBUG=y | ||
| 1318 | CONFIG_USB_GADGET_DEBUG_FILES=y | ||
| 1319 | CONFIG_USB_GADGET_DEBUG_FS=y | ||
| 1320 | CONFIG_USB_GADGET_VBUS_DRAW=2 | ||
| 1321 | CONFIG_USB_GADGET_SELECTED=y | ||
| 1322 | # CONFIG_USB_GADGET_AT91 is not set | ||
| 1323 | # CONFIG_USB_GADGET_ATMEL_USBA is not set | ||
| 1324 | # CONFIG_USB_GADGET_FSL_USB2 is not set | ||
| 1325 | # CONFIG_USB_GADGET_LH7A40X is not set | ||
| 1326 | # CONFIG_USB_GADGET_OMAP is not set | ||
| 1327 | # CONFIG_USB_GADGET_PXA25X is not set | ||
| 1328 | # CONFIG_USB_GADGET_PXA27X is not set | ||
| 1329 | # CONFIG_USB_GADGET_S3C2410 is not set | ||
| 1330 | # CONFIG_USB_GADGET_IMX is not set | ||
| 1331 | # CONFIG_USB_GADGET_M66592 is not set | ||
| 1332 | # CONFIG_USB_GADGET_AMD5536UDC is not set | ||
| 1333 | # CONFIG_USB_GADGET_FSL_QE is not set | ||
| 1334 | # CONFIG_USB_GADGET_CI13XXX is not set | ||
| 1335 | # CONFIG_USB_GADGET_NET2280 is not set | ||
| 1336 | # CONFIG_USB_GADGET_GOKU is not set | ||
| 1337 | # CONFIG_USB_GADGET_DUMMY_HCD is not set | ||
| 1338 | CONFIG_USB_GADGET_DUALSPEED=y | ||
| 1339 | CONFIG_USB_ZERO=m | ||
| 1340 | # CONFIG_USB_ZERO_HNPTEST is not set | ||
| 1341 | # CONFIG_USB_ETH is not set | ||
| 1342 | # CONFIG_USB_GADGETFS is not set | ||
| 1343 | CONFIG_USB_FILE_STORAGE=m | ||
| 1344 | # CONFIG_USB_FILE_STORAGE_TEST is not set | ||
| 1345 | # CONFIG_USB_G_SERIAL is not set | ||
| 1346 | # CONFIG_USB_MIDI_GADGET is not set | ||
| 1347 | # CONFIG_USB_G_PRINTER is not set | ||
| 1348 | # CONFIG_USB_CDC_COMPOSITE is not set | ||
| 1349 | |||
| 1350 | # | ||
| 1351 | # OTG and related infrastructure | ||
| 1352 | # | ||
| 1353 | CONFIG_USB_OTG_UTILS=y | ||
| 1354 | # CONFIG_USB_GPIO_VBUS is not set | ||
| 1355 | # CONFIG_ISP1301_OMAP is not set | ||
| 1356 | CONFIG_TWL4030_USB=y | ||
| 1357 | CONFIG_MMC=m | ||
| 1358 | # CONFIG_MMC_DEBUG is not set | ||
| 1359 | # CONFIG_MMC_UNSAFE_RESUME is not set | ||
| 1360 | |||
| 1361 | # | ||
| 1362 | # MMC/SD/SDIO Card Drivers | ||
| 1363 | # | ||
| 1364 | CONFIG_MMC_BLOCK=m | ||
| 1365 | CONFIG_MMC_BLOCK_BOUNCE=y | ||
| 1366 | # CONFIG_SDIO_UART is not set | ||
| 1367 | # CONFIG_MMC_TEST is not set | ||
| 1368 | |||
| 1369 | # | ||
| 1370 | # MMC/SD/SDIO Host Controller Drivers | ||
| 1371 | # | ||
| 1372 | # CONFIG_MMC_SDHCI is not set | ||
| 1373 | # CONFIG_MMC_OMAP is not set | ||
| 1374 | CONFIG_MMC_OMAP_HS=m | ||
| 1375 | # CONFIG_MMC_SPI is not set | ||
| 1376 | # CONFIG_MEMSTICK is not set | ||
| 1377 | # CONFIG_ACCESSIBILITY is not set | ||
| 1378 | CONFIG_NEW_LEDS=y | ||
| 1379 | CONFIG_LEDS_CLASS=m | ||
| 1380 | |||
| 1381 | # | ||
| 1382 | # LED drivers | ||
| 1383 | # | ||
| 1384 | # CONFIG_LEDS_PCA9532 is not set | ||
| 1385 | # CONFIG_LEDS_GPIO is not set | ||
| 1386 | # CONFIG_LEDS_PCA955X is not set | ||
| 1387 | |||
| 1388 | # | ||
| 1389 | # LED Triggers | ||
| 1390 | # | ||
| 1391 | # CONFIG_LEDS_TRIGGERS is not set | ||
| 1392 | CONFIG_RTC_LIB=y | ||
| 1393 | CONFIG_RTC_CLASS=m | ||
| 1394 | |||
| 1395 | # | ||
| 1396 | # RTC interfaces | ||
| 1397 | # | ||
| 1398 | CONFIG_RTC_INTF_SYSFS=y | ||
| 1399 | CONFIG_RTC_INTF_PROC=y | ||
| 1400 | CONFIG_RTC_INTF_DEV=y | ||
| 1401 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 1402 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1403 | |||
| 1404 | # | ||
| 1405 | # I2C RTC drivers | ||
| 1406 | # | ||
| 1407 | # CONFIG_RTC_DRV_DS1307 is not set | ||
| 1408 | # CONFIG_RTC_DRV_DS1374 is not set | ||
| 1409 | # CONFIG_RTC_DRV_DS1672 is not set | ||
| 1410 | # CONFIG_RTC_DRV_MAX6900 is not set | ||
| 1411 | # CONFIG_RTC_DRV_RS5C372 is not set | ||
| 1412 | # CONFIG_RTC_DRV_ISL1208 is not set | ||
| 1413 | # CONFIG_RTC_DRV_X1205 is not set | ||
| 1414 | # CONFIG_RTC_DRV_PCF8563 is not set | ||
| 1415 | # CONFIG_RTC_DRV_PCF8583 is not set | ||
| 1416 | # CONFIG_RTC_DRV_M41T80 is not set | ||
| 1417 | CONFIG_RTC_DRV_TWL4030=m | ||
| 1418 | # CONFIG_RTC_DRV_S35390A is not set | ||
| 1419 | # CONFIG_RTC_DRV_FM3130 is not set | ||
| 1420 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 1421 | |||
| 1422 | # | ||
| 1423 | # SPI RTC drivers | ||
| 1424 | # | ||
| 1425 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 1426 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 1427 | # CONFIG_RTC_DRV_DS1390 is not set | ||
| 1428 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 1429 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 1430 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 1431 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 1432 | |||
| 1433 | # | ||
| 1434 | # Platform RTC drivers | ||
| 1435 | # | ||
| 1436 | # CONFIG_RTC_DRV_CMOS is not set | ||
| 1437 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1438 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1439 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1440 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1441 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1442 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1443 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1444 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1445 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1446 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 1447 | |||
| 1448 | # | ||
| 1449 | # on-CPU RTC drivers | ||
| 1450 | # | ||
| 1451 | # CONFIG_DMADEVICES is not set | ||
| 1452 | # CONFIG_REGULATOR is not set | ||
| 1453 | # CONFIG_UIO is not set | ||
| 1454 | # CONFIG_STAGING is not set | ||
| 1455 | |||
| 1456 | # | ||
| 1457 | # File systems | ||
| 1458 | # | ||
| 1459 | CONFIG_EXT2_FS=m | ||
| 1460 | # CONFIG_EXT2_FS_XATTR is not set | ||
| 1461 | # CONFIG_EXT2_FS_XIP is not set | ||
| 1462 | CONFIG_EXT3_FS=m | ||
| 1463 | # CONFIG_EXT3_FS_XATTR is not set | ||
| 1464 | # CONFIG_EXT4_FS is not set | ||
| 1465 | CONFIG_JBD=m | ||
| 1466 | # CONFIG_JBD_DEBUG is not set | ||
| 1467 | # CONFIG_REISERFS_FS is not set | ||
| 1468 | # CONFIG_JFS_FS is not set | ||
| 1469 | # CONFIG_FS_POSIX_ACL is not set | ||
| 1470 | CONFIG_FILE_LOCKING=y | ||
| 1471 | # CONFIG_XFS_FS is not set | ||
| 1472 | # CONFIG_OCFS2_FS is not set | ||
| 1473 | # CONFIG_BTRFS_FS is not set | ||
| 1474 | CONFIG_DNOTIFY=y | ||
| 1475 | CONFIG_INOTIFY=y | ||
| 1476 | CONFIG_INOTIFY_USER=y | ||
| 1477 | CONFIG_QUOTA=y | ||
| 1478 | # CONFIG_QUOTA_NETLINK_INTERFACE is not set | ||
| 1479 | CONFIG_PRINT_QUOTA_WARNING=y | ||
| 1480 | CONFIG_QUOTA_TREE=y | ||
| 1481 | # CONFIG_QFMT_V1 is not set | ||
| 1482 | CONFIG_QFMT_V2=y | ||
| 1483 | CONFIG_QUOTACTL=y | ||
| 1484 | # CONFIG_AUTOFS_FS is not set | ||
| 1485 | # CONFIG_AUTOFS4_FS is not set | ||
| 1486 | CONFIG_FUSE_FS=m | ||
| 1487 | |||
| 1488 | # | ||
| 1489 | # CD-ROM/DVD Filesystems | ||
| 1490 | # | ||
| 1491 | # CONFIG_ISO9660_FS is not set | ||
| 1492 | # CONFIG_UDF_FS is not set | ||
| 1493 | |||
| 1494 | # | ||
| 1495 | # DOS/FAT/NT Filesystems | ||
| 1496 | # | ||
| 1497 | CONFIG_FAT_FS=m | ||
| 1498 | CONFIG_MSDOS_FS=m | ||
| 1499 | CONFIG_VFAT_FS=m | ||
| 1500 | CONFIG_FAT_DEFAULT_CODEPAGE=437 | ||
| 1501 | CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | ||
| 1502 | # CONFIG_NTFS_FS is not set | ||
| 1503 | |||
| 1504 | # | ||
| 1505 | # Pseudo filesystems | ||
| 1506 | # | ||
| 1507 | CONFIG_PROC_FS=y | ||
| 1508 | CONFIG_PROC_SYSCTL=y | ||
| 1509 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1510 | CONFIG_SYSFS=y | ||
| 1511 | CONFIG_TMPFS=y | ||
| 1512 | # CONFIG_TMPFS_POSIX_ACL is not set | ||
| 1513 | # CONFIG_HUGETLB_PAGE is not set | ||
| 1514 | # CONFIG_CONFIGFS_FS is not set | ||
| 1515 | CONFIG_MISC_FILESYSTEMS=y | ||
| 1516 | # CONFIG_ADFS_FS is not set | ||
| 1517 | # CONFIG_AFFS_FS is not set | ||
| 1518 | # CONFIG_HFS_FS is not set | ||
| 1519 | # CONFIG_HFSPLUS_FS is not set | ||
| 1520 | # CONFIG_BEFS_FS is not set | ||
| 1521 | # CONFIG_BFS_FS is not set | ||
| 1522 | # CONFIG_EFS_FS is not set | ||
| 1523 | # CONFIG_JFFS2_FS is not set | ||
| 1524 | CONFIG_UBIFS_FS=y | ||
| 1525 | # CONFIG_UBIFS_FS_XATTR is not set | ||
| 1526 | # CONFIG_UBIFS_FS_ADVANCED_COMPR is not set | ||
| 1527 | CONFIG_UBIFS_FS_LZO=y | ||
| 1528 | CONFIG_UBIFS_FS_ZLIB=y | ||
| 1529 | # CONFIG_UBIFS_FS_DEBUG is not set | ||
| 1530 | CONFIG_CRAMFS=y | ||
| 1531 | # CONFIG_SQUASHFS is not set | ||
| 1532 | # CONFIG_VXFS_FS is not set | ||
| 1533 | # CONFIG_MINIX_FS is not set | ||
| 1534 | # CONFIG_OMFS_FS is not set | ||
| 1535 | # CONFIG_HPFS_FS is not set | ||
| 1536 | # CONFIG_QNX4FS_FS is not set | ||
| 1537 | # CONFIG_ROMFS_FS is not set | ||
| 1538 | # CONFIG_SYSV_FS is not set | ||
| 1539 | # CONFIG_UFS_FS is not set | ||
| 1540 | CONFIG_NETWORK_FILESYSTEMS=y | ||
| 1541 | CONFIG_NFS_FS=m | ||
| 1542 | CONFIG_NFS_V3=y | ||
| 1543 | # CONFIG_NFS_V3_ACL is not set | ||
| 1544 | CONFIG_NFS_V4=y | ||
| 1545 | # CONFIG_NFSD is not set | ||
| 1546 | CONFIG_LOCKD=m | ||
| 1547 | CONFIG_LOCKD_V4=y | ||
| 1548 | CONFIG_NFS_COMMON=y | ||
| 1549 | CONFIG_SUNRPC=m | ||
| 1550 | CONFIG_SUNRPC_GSS=m | ||
| 1551 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 1552 | CONFIG_RPCSEC_GSS_KRB5=m | ||
| 1553 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | ||
| 1554 | # CONFIG_SMB_FS is not set | ||
| 1555 | # CONFIG_CIFS is not set | ||
| 1556 | # CONFIG_NCP_FS is not set | ||
| 1557 | # CONFIG_CODA_FS is not set | ||
| 1558 | # CONFIG_AFS_FS is not set | ||
| 1559 | |||
| 1560 | # | ||
| 1561 | # Partition Types | ||
| 1562 | # | ||
| 1563 | CONFIG_PARTITION_ADVANCED=y | ||
| 1564 | # CONFIG_ACORN_PARTITION is not set | ||
| 1565 | # CONFIG_OSF_PARTITION is not set | ||
| 1566 | # CONFIG_AMIGA_PARTITION is not set | ||
| 1567 | # CONFIG_ATARI_PARTITION is not set | ||
| 1568 | # CONFIG_MAC_PARTITION is not set | ||
| 1569 | CONFIG_MSDOS_PARTITION=y | ||
| 1570 | # CONFIG_BSD_DISKLABEL is not set | ||
| 1571 | # CONFIG_MINIX_SUBPARTITION is not set | ||
| 1572 | # CONFIG_SOLARIS_X86_PARTITION is not set | ||
| 1573 | # CONFIG_UNIXWARE_DISKLABEL is not set | ||
| 1574 | # CONFIG_LDM_PARTITION is not set | ||
| 1575 | # CONFIG_SGI_PARTITION is not set | ||
| 1576 | # CONFIG_ULTRIX_PARTITION is not set | ||
| 1577 | # CONFIG_SUN_PARTITION is not set | ||
| 1578 | # CONFIG_KARMA_PARTITION is not set | ||
| 1579 | # CONFIG_EFI_PARTITION is not set | ||
| 1580 | # CONFIG_SYSV68_PARTITION is not set | ||
| 1581 | CONFIG_NLS=y | ||
| 1582 | CONFIG_NLS_DEFAULT="iso8859-1" | ||
| 1583 | CONFIG_NLS_CODEPAGE_437=y | ||
| 1584 | # CONFIG_NLS_CODEPAGE_737 is not set | ||
| 1585 | # CONFIG_NLS_CODEPAGE_775 is not set | ||
| 1586 | # CONFIG_NLS_CODEPAGE_850 is not set | ||
| 1587 | # CONFIG_NLS_CODEPAGE_852 is not set | ||
| 1588 | # CONFIG_NLS_CODEPAGE_855 is not set | ||
| 1589 | # CONFIG_NLS_CODEPAGE_857 is not set | ||
| 1590 | # CONFIG_NLS_CODEPAGE_860 is not set | ||
| 1591 | # CONFIG_NLS_CODEPAGE_861 is not set | ||
| 1592 | # CONFIG_NLS_CODEPAGE_862 is not set | ||
| 1593 | # CONFIG_NLS_CODEPAGE_863 is not set | ||
| 1594 | # CONFIG_NLS_CODEPAGE_864 is not set | ||
| 1595 | # CONFIG_NLS_CODEPAGE_865 is not set | ||
| 1596 | # CONFIG_NLS_CODEPAGE_866 is not set | ||
| 1597 | # CONFIG_NLS_CODEPAGE_869 is not set | ||
| 1598 | # CONFIG_NLS_CODEPAGE_936 is not set | ||
| 1599 | # CONFIG_NLS_CODEPAGE_950 is not set | ||
| 1600 | # CONFIG_NLS_CODEPAGE_932 is not set | ||
| 1601 | # CONFIG_NLS_CODEPAGE_949 is not set | ||
| 1602 | # CONFIG_NLS_CODEPAGE_874 is not set | ||
| 1603 | # CONFIG_NLS_ISO8859_8 is not set | ||
| 1604 | # CONFIG_NLS_CODEPAGE_1250 is not set | ||
| 1605 | # CONFIG_NLS_CODEPAGE_1251 is not set | ||
| 1606 | # CONFIG_NLS_ASCII is not set | ||
| 1607 | CONFIG_NLS_ISO8859_1=y | ||
| 1608 | # CONFIG_NLS_ISO8859_2 is not set | ||
| 1609 | # CONFIG_NLS_ISO8859_3 is not set | ||
| 1610 | # CONFIG_NLS_ISO8859_4 is not set | ||
| 1611 | # CONFIG_NLS_ISO8859_5 is not set | ||
| 1612 | # CONFIG_NLS_ISO8859_6 is not set | ||
| 1613 | # CONFIG_NLS_ISO8859_7 is not set | ||
| 1614 | # CONFIG_NLS_ISO8859_9 is not set | ||
| 1615 | # CONFIG_NLS_ISO8859_13 is not set | ||
| 1616 | # CONFIG_NLS_ISO8859_14 is not set | ||
| 1617 | # CONFIG_NLS_ISO8859_15 is not set | ||
| 1618 | # CONFIG_NLS_KOI8_R is not set | ||
| 1619 | # CONFIG_NLS_KOI8_U is not set | ||
| 1620 | # CONFIG_NLS_UTF8 is not set | ||
| 1621 | # CONFIG_DLM is not set | ||
| 1622 | |||
| 1623 | # | ||
| 1624 | # Kernel hacking | ||
| 1625 | # | ||
| 1626 | CONFIG_PRINTK_TIME=y | ||
| 1627 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1628 | CONFIG_ENABLE_MUST_CHECK=y | ||
| 1629 | CONFIG_FRAME_WARN=1024 | ||
| 1630 | CONFIG_MAGIC_SYSRQ=y | ||
| 1631 | # CONFIG_UNUSED_SYMBOLS is not set | ||
| 1632 | CONFIG_DEBUG_FS=y | ||
| 1633 | # CONFIG_HEADERS_CHECK is not set | ||
| 1634 | CONFIG_DEBUG_KERNEL=y | ||
| 1635 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1636 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1637 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1638 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1639 | CONFIG_SCHED_DEBUG=y | ||
| 1640 | # CONFIG_SCHEDSTATS is not set | ||
| 1641 | CONFIG_TIMER_STATS=y | ||
| 1642 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1643 | # CONFIG_DEBUG_SLAB is not set | ||
| 1644 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1645 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 1646 | CONFIG_DEBUG_SPINLOCK=y | ||
| 1647 | CONFIG_DEBUG_MUTEXES=y | ||
| 1648 | CONFIG_DEBUG_LOCK_ALLOC=y | ||
| 1649 | CONFIG_PROVE_LOCKING=y | ||
| 1650 | CONFIG_LOCKDEP=y | ||
| 1651 | CONFIG_LOCK_STAT=y | ||
| 1652 | # CONFIG_DEBUG_LOCKDEP is not set | ||
| 1653 | CONFIG_TRACE_IRQFLAGS=y | ||
| 1654 | CONFIG_DEBUG_SPINLOCK_SLEEP=y | ||
| 1655 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 1656 | CONFIG_STACKTRACE=y | ||
| 1657 | # CONFIG_DEBUG_KOBJECT is not set | ||
| 1658 | # CONFIG_DEBUG_BUGVERBOSE is not set | ||
| 1659 | CONFIG_DEBUG_INFO=y | ||
| 1660 | # CONFIG_DEBUG_VM is not set | ||
| 1661 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1662 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1663 | # CONFIG_DEBUG_LIST is not set | ||
| 1664 | # CONFIG_DEBUG_SG is not set | ||
| 1665 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1666 | CONFIG_FRAME_POINTER=y | ||
| 1667 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1668 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1669 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1670 | # CONFIG_KPROBES_SANITY_TEST is not set | ||
| 1671 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1672 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1673 | # CONFIG_LKDTM is not set | ||
| 1674 | # CONFIG_FAULT_INJECTION is not set | ||
| 1675 | # CONFIG_LATENCYTOP is not set | ||
| 1676 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1677 | |||
| 1678 | # | ||
| 1679 | # Tracers | ||
| 1680 | # | ||
| 1681 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1682 | # CONFIG_IRQSOFF_TRACER is not set | ||
| 1683 | # CONFIG_SCHED_TRACER is not set | ||
| 1684 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1685 | # CONFIG_BOOT_TRACER is not set | ||
| 1686 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1687 | # CONFIG_STACK_TRACER is not set | ||
| 1688 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1689 | # CONFIG_SAMPLES is not set | ||
| 1690 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1691 | # CONFIG_KGDB is not set | ||
| 1692 | # CONFIG_DEBUG_USER is not set | ||
| 1693 | # CONFIG_DEBUG_ERRORS is not set | ||
| 1694 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 1695 | # CONFIG_DEBUG_LL is not set | ||
| 1696 | |||
| 1697 | # | ||
| 1698 | # Security options | ||
| 1699 | # | ||
| 1700 | # CONFIG_KEYS is not set | ||
| 1701 | CONFIG_SECURITY=y | ||
| 1702 | # CONFIG_SECURITYFS is not set | ||
| 1703 | # CONFIG_SECURITY_NETWORK is not set | ||
| 1704 | # CONFIG_SECURITY_PATH is not set | ||
| 1705 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1706 | # CONFIG_SECURITY_ROOTPLUG is not set | ||
| 1707 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 | ||
| 1708 | CONFIG_CRYPTO=y | ||
| 1709 | |||
| 1710 | # | ||
| 1711 | # Crypto core or helper | ||
| 1712 | # | ||
| 1713 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1714 | CONFIG_CRYPTO_ALGAPI=y | ||
| 1715 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1716 | CONFIG_CRYPTO_AEAD2=y | ||
| 1717 | CONFIG_CRYPTO_BLKCIPHER=y | ||
| 1718 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1719 | CONFIG_CRYPTO_HASH=y | ||
| 1720 | CONFIG_CRYPTO_HASH2=y | ||
| 1721 | CONFIG_CRYPTO_RNG2=y | ||
| 1722 | CONFIG_CRYPTO_MANAGER=y | ||
| 1723 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1724 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1725 | # CONFIG_CRYPTO_NULL is not set | ||
| 1726 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1727 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1728 | # CONFIG_CRYPTO_TEST is not set | ||
| 1729 | |||
| 1730 | # | ||
| 1731 | # Authenticated Encryption with Associated Data | ||
| 1732 | # | ||
| 1733 | # CONFIG_CRYPTO_CCM is not set | ||
| 1734 | # CONFIG_CRYPTO_GCM is not set | ||
| 1735 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1736 | |||
| 1737 | # | ||
| 1738 | # Block modes | ||
| 1739 | # | ||
| 1740 | CONFIG_CRYPTO_CBC=y | ||
| 1741 | # CONFIG_CRYPTO_CTR is not set | ||
| 1742 | # CONFIG_CRYPTO_CTS is not set | ||
| 1743 | CONFIG_CRYPTO_ECB=y | ||
| 1744 | # CONFIG_CRYPTO_LRW is not set | ||
| 1745 | CONFIG_CRYPTO_PCBC=m | ||
| 1746 | # CONFIG_CRYPTO_XTS is not set | ||
| 1747 | |||
| 1748 | # | ||
| 1749 | # Hash modes | ||
| 1750 | # | ||
| 1751 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1752 | # CONFIG_CRYPTO_XCBC is not set | ||
| 1753 | |||
| 1754 | # | ||
| 1755 | # Digest | ||
| 1756 | # | ||
| 1757 | CONFIG_CRYPTO_CRC32C=y | ||
| 1758 | # CONFIG_CRYPTO_MD4 is not set | ||
| 1759 | CONFIG_CRYPTO_MD5=y | ||
| 1760 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1761 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1762 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1763 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1764 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1765 | # CONFIG_CRYPTO_SHA1 is not set | ||
| 1766 | # CONFIG_CRYPTO_SHA256 is not set | ||
| 1767 | # CONFIG_CRYPTO_SHA512 is not set | ||
| 1768 | # CONFIG_CRYPTO_TGR192 is not set | ||
| 1769 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1770 | |||
| 1771 | # | ||
| 1772 | # Ciphers | ||
| 1773 | # | ||
| 1774 | CONFIG_CRYPTO_AES=y | ||
| 1775 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1776 | CONFIG_CRYPTO_ARC4=y | ||
| 1777 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1778 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1779 | # CONFIG_CRYPTO_CAST5 is not set | ||
| 1780 | # CONFIG_CRYPTO_CAST6 is not set | ||
| 1781 | CONFIG_CRYPTO_DES=y | ||
| 1782 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1783 | # CONFIG_CRYPTO_KHAZAD is not set | ||
| 1784 | # CONFIG_CRYPTO_SALSA20 is not set | ||
| 1785 | # CONFIG_CRYPTO_SEED is not set | ||
| 1786 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1787 | # CONFIG_CRYPTO_TEA is not set | ||
| 1788 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1789 | |||
| 1790 | # | ||
| 1791 | # Compression | ||
| 1792 | # | ||
| 1793 | CONFIG_CRYPTO_DEFLATE=y | ||
| 1794 | CONFIG_CRYPTO_LZO=y | ||
| 1795 | |||
| 1796 | # | ||
| 1797 | # Random Number Generation | ||
| 1798 | # | ||
| 1799 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1800 | CONFIG_CRYPTO_HW=y | ||
| 1801 | |||
| 1802 | # | ||
| 1803 | # Library routines | ||
| 1804 | # | ||
| 1805 | CONFIG_BITREVERSE=y | ||
| 1806 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1807 | CONFIG_CRC_CCITT=y | ||
| 1808 | CONFIG_CRC16=y | ||
| 1809 | # CONFIG_CRC_T10DIF is not set | ||
| 1810 | # CONFIG_CRC_ITU_T is not set | ||
| 1811 | CONFIG_CRC32=y | ||
| 1812 | CONFIG_CRC7=m | ||
| 1813 | CONFIG_LIBCRC32C=y | ||
| 1814 | CONFIG_ZLIB_INFLATE=y | ||
| 1815 | CONFIG_ZLIB_DEFLATE=y | ||
| 1816 | CONFIG_LZO_COMPRESS=y | ||
| 1817 | CONFIG_LZO_DECOMPRESS=y | ||
| 1818 | CONFIG_PLIST=y | ||
| 1819 | CONFIG_HAS_IOMEM=y | ||
| 1820 | CONFIG_HAS_IOPORT=y | ||
| 1821 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/shannon_defconfig b/arch/arm/configs/shannon_defconfig index d052c8f80515..984f7096a533 100644 --- a/arch/arm/configs/shannon_defconfig +++ b/arch/arm/configs/shannon_defconfig | |||
| @@ -87,7 +87,6 @@ CONFIG_ARCH_SA1100=y | |||
| 87 | # CONFIG_SA1100_COLLIE is not set | 87 | # CONFIG_SA1100_COLLIE is not set |
| 88 | # CONFIG_SA1100_H3100 is not set | 88 | # CONFIG_SA1100_H3100 is not set |
| 89 | # CONFIG_SA1100_H3600 is not set | 89 | # CONFIG_SA1100_H3600 is not set |
| 90 | # CONFIG_SA1100_H3800 is not set | ||
| 91 | # CONFIG_SA1100_BADGE4 is not set | 90 | # CONFIG_SA1100_BADGE4 is not set |
| 92 | # CONFIG_SA1100_JORNADA720 is not set | 91 | # CONFIG_SA1100_JORNADA720 is not set |
| 93 | # CONFIG_SA1100_HACKKIT is not set | 92 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/configs/shark_defconfig b/arch/arm/configs/shark_defconfig index 9b6561d119af..90235bf7a1de 100644 --- a/arch/arm/configs/shark_defconfig +++ b/arch/arm/configs/shark_defconfig | |||
| @@ -1,88 +1,174 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.12-git3 | 3 | # Linux kernel version: 2.6.28-git6 |
| 4 | # Sat Jul 16 15:21:47 2005 | 4 | # Thu Jan 8 17:14:47 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_ARM=y | 6 | CONFIG_ARM=y |
| 7 | CONFIG_SYS_SUPPORTS_APM_EMULATION=y | ||
| 8 | # CONFIG_GENERIC_GPIO is not set | ||
| 9 | # CONFIG_GENERIC_TIME is not set | ||
| 10 | # CONFIG_GENERIC_CLOCKEVENTS is not set | ||
| 7 | CONFIG_MMU=y | 11 | CONFIG_MMU=y |
| 8 | CONFIG_UID16=y | 12 | # CONFIG_NO_IOPORT is not set |
| 13 | CONFIG_GENERIC_HARDIRQS=y | ||
| 14 | CONFIG_STACKTRACE_SUPPORT=y | ||
| 15 | CONFIG_HAVE_LATENCYTOP_SUPPORT=y | ||
| 16 | CONFIG_LOCKDEP_SUPPORT=y | ||
| 17 | CONFIG_TRACE_IRQFLAGS_SUPPORT=y | ||
| 18 | CONFIG_HARDIRQS_SW_RESEND=y | ||
| 19 | CONFIG_GENERIC_IRQ_PROBE=y | ||
| 9 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 20 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 21 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | ||
| 22 | # CONFIG_ARCH_HAS_ILOG2_U64 is not set | ||
| 23 | CONFIG_GENERIC_HWEIGHT=y | ||
| 10 | CONFIG_GENERIC_CALIBRATE_DELAY=y | 24 | CONFIG_GENERIC_CALIBRATE_DELAY=y |
| 25 | CONFIG_ZONE_DMA=y | ||
| 26 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | ||
| 27 | CONFIG_VECTORS_BASE=0xffff0000 | ||
| 28 | CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" | ||
| 11 | 29 | ||
| 12 | # | 30 | # |
| 13 | # Code maturity level options | 31 | # General setup |
| 14 | # | 32 | # |
| 15 | CONFIG_EXPERIMENTAL=y | 33 | CONFIG_EXPERIMENTAL=y |
| 16 | CONFIG_CLEAN_COMPILE=y | ||
| 17 | CONFIG_BROKEN_ON_SMP=y | 34 | CONFIG_BROKEN_ON_SMP=y |
| 18 | CONFIG_INIT_ENV_ARG_LIMIT=32 | 35 | CONFIG_INIT_ENV_ARG_LIMIT=32 |
| 19 | |||
| 20 | # | ||
| 21 | # General setup | ||
| 22 | # | ||
| 23 | CONFIG_LOCALVERSION="" | 36 | CONFIG_LOCALVERSION="" |
| 37 | # CONFIG_LOCALVERSION_AUTO is not set | ||
| 24 | CONFIG_SWAP=y | 38 | CONFIG_SWAP=y |
| 25 | CONFIG_SYSVIPC=y | 39 | CONFIG_SYSVIPC=y |
| 40 | CONFIG_SYSVIPC_SYSCTL=y | ||
| 26 | # CONFIG_POSIX_MQUEUE is not set | 41 | # CONFIG_POSIX_MQUEUE is not set |
| 27 | # CONFIG_BSD_PROCESS_ACCT is not set | 42 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 28 | CONFIG_SYSCTL=y | 43 | # CONFIG_TASKSTATS is not set |
| 29 | # CONFIG_AUDIT is not set | 44 | # CONFIG_AUDIT is not set |
| 30 | # CONFIG_HOTPLUG is not set | ||
| 31 | CONFIG_KOBJECT_UEVENT=y | ||
| 32 | # CONFIG_IKCONFIG is not set | 45 | # CONFIG_IKCONFIG is not set |
| 46 | CONFIG_LOG_BUF_SHIFT=14 | ||
| 47 | # CONFIG_CGROUPS is not set | ||
| 48 | CONFIG_GROUP_SCHED=y | ||
| 49 | CONFIG_FAIR_GROUP_SCHED=y | ||
| 50 | # CONFIG_RT_GROUP_SCHED is not set | ||
| 51 | CONFIG_USER_SCHED=y | ||
| 52 | # CONFIG_CGROUP_SCHED is not set | ||
| 53 | CONFIG_SYSFS_DEPRECATED=y | ||
| 54 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 55 | # CONFIG_RELAY is not set | ||
| 56 | CONFIG_NAMESPACES=y | ||
| 57 | # CONFIG_UTS_NS is not set | ||
| 58 | # CONFIG_IPC_NS is not set | ||
| 59 | # CONFIG_USER_NS is not set | ||
| 60 | # CONFIG_PID_NS is not set | ||
| 61 | # CONFIG_BLK_DEV_INITRD is not set | ||
| 62 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 63 | CONFIG_SYSCTL=y | ||
| 33 | # CONFIG_EMBEDDED is not set | 64 | # CONFIG_EMBEDDED is not set |
| 65 | CONFIG_UID16=y | ||
| 66 | CONFIG_SYSCTL_SYSCALL=y | ||
| 34 | CONFIG_KALLSYMS=y | 67 | CONFIG_KALLSYMS=y |
| 35 | # CONFIG_KALLSYMS_ALL is not set | 68 | # CONFIG_KALLSYMS_ALL is not set |
| 36 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 69 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 70 | CONFIG_HOTPLUG=y | ||
| 37 | CONFIG_PRINTK=y | 71 | CONFIG_PRINTK=y |
| 38 | CONFIG_BUG=y | 72 | CONFIG_BUG=y |
| 73 | CONFIG_ELF_CORE=y | ||
| 74 | CONFIG_COMPAT_BRK=y | ||
| 39 | CONFIG_BASE_FULL=y | 75 | CONFIG_BASE_FULL=y |
| 40 | CONFIG_FUTEX=y | 76 | CONFIG_FUTEX=y |
| 77 | CONFIG_ANON_INODES=y | ||
| 41 | CONFIG_EPOLL=y | 78 | CONFIG_EPOLL=y |
| 42 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 79 | CONFIG_SIGNALFD=y |
| 80 | CONFIG_TIMERFD=y | ||
| 81 | CONFIG_EVENTFD=y | ||
| 43 | CONFIG_SHMEM=y | 82 | CONFIG_SHMEM=y |
| 44 | CONFIG_CC_ALIGN_FUNCTIONS=0 | 83 | CONFIG_AIO=y |
| 45 | CONFIG_CC_ALIGN_LABELS=0 | 84 | CONFIG_VM_EVENT_COUNTERS=y |
| 46 | CONFIG_CC_ALIGN_LOOPS=0 | 85 | CONFIG_PCI_QUIRKS=y |
| 47 | CONFIG_CC_ALIGN_JUMPS=0 | 86 | CONFIG_SLAB=y |
| 87 | # CONFIG_SLUB is not set | ||
| 88 | # CONFIG_SLOB is not set | ||
| 89 | # CONFIG_PROFILING is not set | ||
| 90 | CONFIG_HAVE_OPROFILE=y | ||
| 91 | # CONFIG_KPROBES is not set | ||
| 92 | CONFIG_HAVE_KPROBES=y | ||
| 93 | CONFIG_HAVE_KRETPROBES=y | ||
| 94 | CONFIG_HAVE_GENERIC_DMA_COHERENT=y | ||
| 95 | CONFIG_SLABINFO=y | ||
| 96 | CONFIG_RT_MUTEXES=y | ||
| 48 | # CONFIG_TINY_SHMEM is not set | 97 | # CONFIG_TINY_SHMEM is not set |
| 49 | CONFIG_BASE_SMALL=0 | 98 | CONFIG_BASE_SMALL=0 |
| 50 | |||
| 51 | # | ||
| 52 | # Loadable module support | ||
| 53 | # | ||
| 54 | CONFIG_MODULES=y | 99 | CONFIG_MODULES=y |
| 100 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 55 | CONFIG_MODULE_UNLOAD=y | 101 | CONFIG_MODULE_UNLOAD=y |
| 56 | CONFIG_MODULE_FORCE_UNLOAD=y | 102 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 57 | CONFIG_OBSOLETE_MODPARM=y | ||
| 58 | # CONFIG_MODVERSIONS is not set | 103 | # CONFIG_MODVERSIONS is not set |
| 59 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 104 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 60 | CONFIG_KMOD=y | 105 | CONFIG_KMOD=y |
| 106 | CONFIG_BLOCK=y | ||
| 107 | # CONFIG_LBD is not set | ||
| 108 | # CONFIG_BLK_DEV_IO_TRACE is not set | ||
| 109 | # CONFIG_BLK_DEV_BSG is not set | ||
| 110 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 111 | |||
| 112 | # | ||
| 113 | # IO Schedulers | ||
| 114 | # | ||
| 115 | CONFIG_IOSCHED_NOOP=y | ||
| 116 | CONFIG_IOSCHED_AS=y | ||
| 117 | CONFIG_IOSCHED_DEADLINE=y | ||
| 118 | CONFIG_IOSCHED_CFQ=y | ||
| 119 | # CONFIG_DEFAULT_AS is not set | ||
| 120 | # CONFIG_DEFAULT_DEADLINE is not set | ||
| 121 | CONFIG_DEFAULT_CFQ=y | ||
| 122 | # CONFIG_DEFAULT_NOOP is not set | ||
| 123 | CONFIG_DEFAULT_IOSCHED="cfq" | ||
| 124 | CONFIG_CLASSIC_RCU=y | ||
| 125 | # CONFIG_TREE_RCU is not set | ||
| 126 | # CONFIG_PREEMPT_RCU is not set | ||
| 127 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 128 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 129 | # CONFIG_FREEZER is not set | ||
| 61 | 130 | ||
| 62 | # | 131 | # |
| 63 | # System Type | 132 | # System Type |
| 64 | # | 133 | # |
| 65 | # CONFIG_ARCH_CLPS7500 is not set | 134 | # CONFIG_ARCH_AAEC2000 is not set |
| 135 | # CONFIG_ARCH_INTEGRATOR is not set | ||
| 136 | # CONFIG_ARCH_REALVIEW is not set | ||
| 137 | # CONFIG_ARCH_VERSATILE is not set | ||
| 138 | # CONFIG_ARCH_AT91 is not set | ||
| 66 | # CONFIG_ARCH_CLPS711X is not set | 139 | # CONFIG_ARCH_CLPS711X is not set |
| 67 | # CONFIG_ARCH_CO285 is not set | ||
| 68 | # CONFIG_ARCH_EBSA110 is not set | 140 | # CONFIG_ARCH_EBSA110 is not set |
| 141 | # CONFIG_ARCH_EP93XX is not set | ||
| 69 | # CONFIG_ARCH_FOOTBRIDGE is not set | 142 | # CONFIG_ARCH_FOOTBRIDGE is not set |
| 70 | # CONFIG_ARCH_INTEGRATOR is not set | 143 | # CONFIG_ARCH_NETX is not set |
| 71 | # CONFIG_ARCH_IOP3XX is not set | 144 | # CONFIG_ARCH_H720X is not set |
| 72 | # CONFIG_ARCH_IXP4XX is not set | 145 | # CONFIG_ARCH_IMX is not set |
| 146 | # CONFIG_ARCH_IOP13XX is not set | ||
| 147 | # CONFIG_ARCH_IOP32X is not set | ||
| 148 | # CONFIG_ARCH_IOP33X is not set | ||
| 149 | # CONFIG_ARCH_IXP23XX is not set | ||
| 73 | # CONFIG_ARCH_IXP2000 is not set | 150 | # CONFIG_ARCH_IXP2000 is not set |
| 151 | # CONFIG_ARCH_IXP4XX is not set | ||
| 74 | # CONFIG_ARCH_L7200 is not set | 152 | # CONFIG_ARCH_L7200 is not set |
| 153 | # CONFIG_ARCH_KIRKWOOD is not set | ||
| 154 | # CONFIG_ARCH_KS8695 is not set | ||
| 155 | # CONFIG_ARCH_NS9XXX is not set | ||
| 156 | # CONFIG_ARCH_LOKI is not set | ||
| 157 | # CONFIG_ARCH_MV78XX0 is not set | ||
| 158 | # CONFIG_ARCH_MXC is not set | ||
| 159 | # CONFIG_ARCH_ORION5X is not set | ||
| 160 | # CONFIG_ARCH_PNX4008 is not set | ||
| 75 | # CONFIG_ARCH_PXA is not set | 161 | # CONFIG_ARCH_PXA is not set |
| 76 | # CONFIG_ARCH_RPC is not set | 162 | # CONFIG_ARCH_RPC is not set |
| 77 | # CONFIG_ARCH_SA1100 is not set | 163 | # CONFIG_ARCH_SA1100 is not set |
| 78 | # CONFIG_ARCH_S3C2410 is not set | 164 | # CONFIG_ARCH_S3C2410 is not set |
| 165 | # CONFIG_ARCH_S3C64XX is not set | ||
| 79 | CONFIG_ARCH_SHARK=y | 166 | CONFIG_ARCH_SHARK=y |
| 80 | # CONFIG_ARCH_LH7A40X is not set | 167 | # CONFIG_ARCH_LH7A40X is not set |
| 168 | # CONFIG_ARCH_DAVINCI is not set | ||
| 81 | # CONFIG_ARCH_OMAP is not set | 169 | # CONFIG_ARCH_OMAP is not set |
| 82 | # CONFIG_ARCH_VERSATILE is not set | 170 | # CONFIG_ARCH_MSM is not set |
| 83 | # CONFIG_ARCH_IMX is not set | 171 | # CONFIG_ARCH_W90X900 is not set |
| 84 | # CONFIG_ARCH_H720X is not set | ||
| 85 | # CONFIG_ARCH_AAEC2000 is not set | ||
| 86 | 172 | ||
| 87 | # | 173 | # |
| 88 | # Processor Type | 174 | # Processor Type |
| @@ -91,14 +177,20 @@ CONFIG_CPU_32=y | |||
| 91 | CONFIG_CPU_SA110=y | 177 | CONFIG_CPU_SA110=y |
| 92 | CONFIG_CPU_32v4=y | 178 | CONFIG_CPU_32v4=y |
| 93 | CONFIG_CPU_ABRT_EV4=y | 179 | CONFIG_CPU_ABRT_EV4=y |
| 180 | CONFIG_CPU_PABRT_NOIFAR=y | ||
| 94 | CONFIG_CPU_CACHE_V4WB=y | 181 | CONFIG_CPU_CACHE_V4WB=y |
| 95 | CONFIG_CPU_CACHE_VIVT=y | 182 | CONFIG_CPU_CACHE_VIVT=y |
| 96 | CONFIG_CPU_COPY_V4WB=y | 183 | CONFIG_CPU_COPY_V4WB=y |
| 97 | CONFIG_CPU_TLB_V4WB=y | 184 | CONFIG_CPU_TLB_V4WB=y |
| 185 | CONFIG_CPU_CP15=y | ||
| 186 | CONFIG_CPU_CP15_MMU=y | ||
| 98 | 187 | ||
| 99 | # | 188 | # |
| 100 | # Processor Features | 189 | # Processor Features |
| 101 | # | 190 | # |
| 191 | # CONFIG_CPU_ICACHE_DISABLE is not set | ||
| 192 | # CONFIG_CPU_DCACHE_DISABLE is not set | ||
| 193 | # CONFIG_OUTER_CACHE is not set | ||
| 102 | 194 | ||
| 103 | # | 195 | # |
| 104 | # Bus support | 196 | # Bus support |
| @@ -107,22 +199,40 @@ CONFIG_ISA=y | |||
| 107 | CONFIG_ISA_DMA=y | 199 | CONFIG_ISA_DMA=y |
| 108 | CONFIG_ISA_DMA_API=y | 200 | CONFIG_ISA_DMA_API=y |
| 109 | CONFIG_PCI=y | 201 | CONFIG_PCI=y |
| 202 | CONFIG_PCI_SYSCALL=y | ||
| 110 | CONFIG_PCI_HOST_VIA82C505=y | 203 | CONFIG_PCI_HOST_VIA82C505=y |
| 111 | CONFIG_PCI_LEGACY_PROC=y | 204 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 112 | # CONFIG_PCI_NAMES is not set | 205 | CONFIG_PCI_LEGACY=y |
| 113 | # CONFIG_PCI_DEBUG is not set | 206 | # CONFIG_PCI_DEBUG is not set |
| 114 | |||
| 115 | # | ||
| 116 | # PCCARD (PCMCIA/CardBus) support | ||
| 117 | # | ||
| 118 | # CONFIG_PCCARD is not set | 207 | # CONFIG_PCCARD is not set |
| 119 | 208 | ||
| 120 | # | 209 | # |
| 121 | # Kernel Features | 210 | # Kernel Features |
| 122 | # | 211 | # |
| 123 | # CONFIG_SMP is not set | 212 | CONFIG_VMSPLIT_3G=y |
| 213 | # CONFIG_VMSPLIT_2G is not set | ||
| 214 | # CONFIG_VMSPLIT_1G is not set | ||
| 215 | CONFIG_PAGE_OFFSET=0xC0000000 | ||
| 124 | # CONFIG_PREEMPT is not set | 216 | # CONFIG_PREEMPT is not set |
| 125 | # CONFIG_DISCONTIGMEM is not set | 217 | CONFIG_HZ=100 |
| 218 | # CONFIG_AEABI is not set | ||
| 219 | CONFIG_ARCH_FLATMEM_HAS_HOLES=y | ||
| 220 | # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set | ||
| 221 | # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set | ||
| 222 | CONFIG_SELECT_MEMORY_MODEL=y | ||
| 223 | CONFIG_FLATMEM_MANUAL=y | ||
| 224 | # CONFIG_DISCONTIGMEM_MANUAL is not set | ||
| 225 | # CONFIG_SPARSEMEM_MANUAL is not set | ||
| 226 | CONFIG_FLATMEM=y | ||
| 227 | CONFIG_FLAT_NODE_MEM_MAP=y | ||
| 228 | CONFIG_PAGEFLAGS_EXTENDED=y | ||
| 229 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | ||
| 230 | # CONFIG_RESOURCES_64BIT is not set | ||
| 231 | # CONFIG_PHYS_ADDR_T_64BIT is not set | ||
| 232 | CONFIG_ZONE_DMA_FLAG=1 | ||
| 233 | CONFIG_BOUNCE=y | ||
| 234 | CONFIG_VIRT_TO_BUS=y | ||
| 235 | CONFIG_UNEVICTABLE_LRU=y | ||
| 126 | CONFIG_LEDS=y | 236 | CONFIG_LEDS=y |
| 127 | CONFIG_LEDS_TIMER=y | 237 | CONFIG_LEDS_TIMER=y |
| 128 | # CONFIG_LEDS_CPU is not set | 238 | # CONFIG_LEDS_CPU is not set |
| @@ -135,6 +245,12 @@ CONFIG_ZBOOT_ROM_TEXT=0x0 | |||
| 135 | CONFIG_ZBOOT_ROM_BSS=0x0 | 245 | CONFIG_ZBOOT_ROM_BSS=0x0 |
| 136 | CONFIG_CMDLINE="" | 246 | CONFIG_CMDLINE="" |
| 137 | # CONFIG_XIP_KERNEL is not set | 247 | # CONFIG_XIP_KERNEL is not set |
| 248 | # CONFIG_KEXEC is not set | ||
| 249 | |||
| 250 | # | ||
| 251 | # CPU Power Management | ||
| 252 | # | ||
| 253 | # CONFIG_CPU_IDLE is not set | ||
| 138 | 254 | ||
| 139 | # | 255 | # |
| 140 | # Floating point emulation | 256 | # Floating point emulation |
| @@ -143,13 +259,16 @@ CONFIG_CMDLINE="" | |||
| 143 | # | 259 | # |
| 144 | # At least one emulation must be selected | 260 | # At least one emulation must be selected |
| 145 | # | 261 | # |
| 146 | # CONFIG_FPE_NWFPE is not set | 262 | CONFIG_FPE_NWFPE=y |
| 147 | CONFIG_FPE_FASTFPE=y | 263 | # CONFIG_FPE_NWFPE_XP is not set |
| 264 | # CONFIG_FPE_FASTFPE is not set | ||
| 148 | 265 | ||
| 149 | # | 266 | # |
| 150 | # Userspace binary formats | 267 | # Userspace binary formats |
| 151 | # | 268 | # |
| 152 | CONFIG_BINFMT_ELF=y | 269 | CONFIG_BINFMT_ELF=y |
| 270 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 271 | CONFIG_HAVE_AOUT=y | ||
| 153 | # CONFIG_BINFMT_AOUT is not set | 272 | # CONFIG_BINFMT_AOUT is not set |
| 154 | # CONFIG_BINFMT_MISC is not set | 273 | # CONFIG_BINFMT_MISC is not set |
| 155 | # CONFIG_ARTHUR is not set | 274 | # CONFIG_ARTHUR is not set |
| @@ -158,44 +277,104 @@ CONFIG_BINFMT_ELF=y | |||
| 158 | # Power management options | 277 | # Power management options |
| 159 | # | 278 | # |
| 160 | # CONFIG_PM is not set | 279 | # CONFIG_PM is not set |
| 280 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | ||
| 281 | CONFIG_NET=y | ||
| 161 | 282 | ||
| 162 | # | 283 | # |
| 163 | # Device Drivers | 284 | # Networking options |
| 164 | # | 285 | # |
| 286 | # CONFIG_NET_NS is not set | ||
| 287 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 288 | CONFIG_PACKET=y | ||
| 289 | # CONFIG_PACKET_MMAP is not set | ||
| 290 | CONFIG_UNIX=y | ||
| 291 | # CONFIG_NET_KEY is not set | ||
| 292 | CONFIG_INET=y | ||
| 293 | # CONFIG_IP_MULTICAST is not set | ||
| 294 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 295 | CONFIG_IP_FIB_HASH=y | ||
| 296 | # CONFIG_IP_PNP is not set | ||
| 297 | # CONFIG_NET_IPIP is not set | ||
| 298 | # CONFIG_NET_IPGRE is not set | ||
| 299 | # CONFIG_ARPD is not set | ||
| 300 | # CONFIG_SYN_COOKIES is not set | ||
| 301 | # CONFIG_INET_AH is not set | ||
| 302 | # CONFIG_INET_ESP is not set | ||
| 303 | # CONFIG_INET_IPCOMP is not set | ||
| 304 | # CONFIG_INET_XFRM_TUNNEL is not set | ||
| 305 | # CONFIG_INET_TUNNEL is not set | ||
| 306 | # CONFIG_INET_XFRM_MODE_TRANSPORT is not set | ||
| 307 | # CONFIG_INET_XFRM_MODE_TUNNEL is not set | ||
| 308 | # CONFIG_INET_XFRM_MODE_BEET is not set | ||
| 309 | # CONFIG_INET_LRO is not set | ||
| 310 | # CONFIG_INET_DIAG is not set | ||
| 311 | # CONFIG_TCP_CONG_ADVANCED is not set | ||
| 312 | CONFIG_TCP_CONG_CUBIC=y | ||
| 313 | CONFIG_DEFAULT_TCP_CONG="cubic" | ||
| 314 | # CONFIG_TCP_MD5SIG is not set | ||
| 315 | # CONFIG_IPV6 is not set | ||
| 316 | # CONFIG_NETWORK_SECMARK is not set | ||
| 317 | # CONFIG_NETFILTER is not set | ||
| 318 | # CONFIG_IP_DCCP is not set | ||
| 319 | # CONFIG_IP_SCTP is not set | ||
| 320 | # CONFIG_TIPC is not set | ||
| 321 | # CONFIG_ATM is not set | ||
| 322 | # CONFIG_BRIDGE is not set | ||
| 323 | # CONFIG_NET_DSA is not set | ||
| 324 | # CONFIG_VLAN_8021Q is not set | ||
| 325 | # CONFIG_DECNET is not set | ||
| 326 | # CONFIG_LLC2 is not set | ||
| 327 | # CONFIG_IPX is not set | ||
| 328 | # CONFIG_ATALK is not set | ||
| 329 | # CONFIG_X25 is not set | ||
| 330 | # CONFIG_LAPB is not set | ||
| 331 | # CONFIG_ECONET is not set | ||
| 332 | # CONFIG_WAN_ROUTER is not set | ||
| 333 | # CONFIG_NET_SCHED is not set | ||
| 334 | # CONFIG_DCB is not set | ||
| 165 | 335 | ||
| 166 | # | 336 | # |
| 167 | # Generic Driver Options | 337 | # Network testing |
| 168 | # | 338 | # |
| 169 | # CONFIG_STANDALONE is not set | 339 | # CONFIG_NET_PKTGEN is not set |
| 170 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 340 | # CONFIG_HAMRADIO is not set |
| 171 | # CONFIG_FW_LOADER is not set | 341 | # CONFIG_CAN is not set |
| 172 | # CONFIG_DEBUG_DRIVER is not set | 342 | # CONFIG_IRDA is not set |
| 343 | # CONFIG_BT is not set | ||
| 344 | # CONFIG_AF_RXRPC is not set | ||
| 345 | # CONFIG_PHONET is not set | ||
| 346 | # CONFIG_WIRELESS is not set | ||
| 347 | # CONFIG_RFKILL is not set | ||
| 348 | # CONFIG_NET_9P is not set | ||
| 173 | 349 | ||
| 174 | # | 350 | # |
| 175 | # Memory Technology Devices (MTD) | 351 | # Device Drivers |
| 176 | # | 352 | # |
| 177 | # CONFIG_MTD is not set | ||
| 178 | 353 | ||
| 179 | # | 354 | # |
| 180 | # Parallel port support | 355 | # Generic Driver Options |
| 181 | # | 356 | # |
| 357 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
| 358 | # CONFIG_STANDALONE is not set | ||
| 359 | CONFIG_PREVENT_FIRMWARE_BUILD=y | ||
| 360 | CONFIG_FW_LOADER=y | ||
| 361 | # CONFIG_FIRMWARE_IN_KERNEL is not set | ||
| 362 | CONFIG_EXTRA_FIRMWARE="" | ||
| 363 | # CONFIG_DEBUG_DRIVER is not set | ||
| 364 | # CONFIG_DEBUG_DEVRES is not set | ||
| 365 | # CONFIG_SYS_HYPERVISOR is not set | ||
| 366 | # CONFIG_CONNECTOR is not set | ||
| 367 | # CONFIG_MTD is not set | ||
| 182 | CONFIG_PARPORT=m | 368 | CONFIG_PARPORT=m |
| 183 | CONFIG_PARPORT_PC=m | 369 | CONFIG_PARPORT_PC=m |
| 184 | # CONFIG_PARPORT_SERIAL is not set | 370 | # CONFIG_PARPORT_SERIAL is not set |
| 185 | # CONFIG_PARPORT_PC_FIFO is not set | 371 | # CONFIG_PARPORT_PC_FIFO is not set |
| 186 | # CONFIG_PARPORT_PC_SUPERIO is not set | 372 | # CONFIG_PARPORT_PC_SUPERIO is not set |
| 187 | # CONFIG_PARPORT_ARC is not set | ||
| 188 | # CONFIG_PARPORT_GSC is not set | 373 | # CONFIG_PARPORT_GSC is not set |
| 374 | # CONFIG_PARPORT_AX88796 is not set | ||
| 189 | # CONFIG_PARPORT_1284 is not set | 375 | # CONFIG_PARPORT_1284 is not set |
| 190 | |||
| 191 | # | ||
| 192 | # Plug and Play support | ||
| 193 | # | ||
| 194 | # CONFIG_PNP is not set | 376 | # CONFIG_PNP is not set |
| 195 | 377 | CONFIG_BLK_DEV=y | |
| 196 | # | ||
| 197 | # Block devices | ||
| 198 | # | ||
| 199 | # CONFIG_BLK_DEV_XD is not set | 378 | # CONFIG_BLK_DEV_XD is not set |
| 200 | # CONFIG_PARIDE is not set | 379 | # CONFIG_PARIDE is not set |
| 201 | # CONFIG_BLK_CPQ_DA is not set | 380 | # CONFIG_BLK_CPQ_DA is not set |
| @@ -210,52 +389,78 @@ CONFIG_BLK_DEV_LOOP=y | |||
| 210 | CONFIG_BLK_DEV_RAM=y | 389 | CONFIG_BLK_DEV_RAM=y |
| 211 | CONFIG_BLK_DEV_RAM_COUNT=16 | 390 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 212 | CONFIG_BLK_DEV_RAM_SIZE=4096 | 391 | CONFIG_BLK_DEV_RAM_SIZE=4096 |
| 213 | # CONFIG_BLK_DEV_INITRD is not set | 392 | # CONFIG_BLK_DEV_XIP is not set |
| 214 | CONFIG_INITRAMFS_SOURCE="" | ||
| 215 | # CONFIG_CDROM_PKTCDVD is not set | 393 | # CONFIG_CDROM_PKTCDVD is not set |
| 216 | |||
| 217 | # | ||
| 218 | # IO Schedulers | ||
| 219 | # | ||
| 220 | CONFIG_IOSCHED_NOOP=y | ||
| 221 | CONFIG_IOSCHED_AS=y | ||
| 222 | CONFIG_IOSCHED_DEADLINE=y | ||
| 223 | CONFIG_IOSCHED_CFQ=y | ||
| 224 | # CONFIG_ATA_OVER_ETH is not set | 394 | # CONFIG_ATA_OVER_ETH is not set |
| 225 | 395 | # CONFIG_BLK_DEV_HD is not set | |
| 226 | # | 396 | CONFIG_MISC_DEVICES=y |
| 227 | # ATA/ATAPI/MFM/RLL support | 397 | # CONFIG_PHANTOM is not set |
| 228 | # | 398 | # CONFIG_EEPROM_93CX6 is not set |
| 399 | # CONFIG_SGI_IOC4 is not set | ||
| 400 | # CONFIG_TIFM_CORE is not set | ||
| 401 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 402 | # CONFIG_HP_ILO is not set | ||
| 403 | # CONFIG_C2PORT is not set | ||
| 404 | CONFIG_HAVE_IDE=y | ||
| 229 | CONFIG_IDE=y | 405 | CONFIG_IDE=y |
| 230 | CONFIG_BLK_DEV_IDE=y | ||
| 231 | 406 | ||
| 232 | # | 407 | # |
| 233 | # Please see Documentation/ide.txt for help/info on IDE drives | 408 | # Please see Documentation/ide/ide.txt for help/info on IDE drives |
| 234 | # | 409 | # |
| 410 | CONFIG_IDE_ATAPI=y | ||
| 235 | # CONFIG_BLK_DEV_IDE_SATA is not set | 411 | # CONFIG_BLK_DEV_IDE_SATA is not set |
| 236 | CONFIG_BLK_DEV_IDEDISK=y | 412 | CONFIG_IDE_GD=y |
| 237 | # CONFIG_IDEDISK_MULTI_MODE is not set | 413 | CONFIG_IDE_GD_ATA=y |
| 414 | # CONFIG_IDE_GD_ATAPI is not set | ||
| 238 | CONFIG_BLK_DEV_IDECD=m | 415 | CONFIG_BLK_DEV_IDECD=m |
| 416 | CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y | ||
| 239 | # CONFIG_BLK_DEV_IDETAPE is not set | 417 | # CONFIG_BLK_DEV_IDETAPE is not set |
| 240 | CONFIG_BLK_DEV_IDEFLOPPY=y | ||
| 241 | # CONFIG_BLK_DEV_IDESCSI is not set | ||
| 242 | # CONFIG_IDE_TASK_IOCTL is not set | 418 | # CONFIG_IDE_TASK_IOCTL is not set |
| 419 | CONFIG_IDE_PROC_FS=y | ||
| 243 | 420 | ||
| 244 | # | 421 | # |
| 245 | # IDE chipset support/bugfixes | 422 | # IDE chipset support/bugfixes |
| 246 | # | 423 | # |
| 247 | CONFIG_IDE_GENERIC=y | 424 | # CONFIG_BLK_DEV_PLATFORM is not set |
| 248 | # CONFIG_BLK_DEV_IDEPCI is not set | 425 | |
| 426 | # | ||
| 427 | # PCI IDE chipsets support | ||
| 428 | # | ||
| 429 | # CONFIG_BLK_DEV_GENERIC is not set | ||
| 430 | # CONFIG_BLK_DEV_OPTI621 is not set | ||
| 431 | # CONFIG_BLK_DEV_AEC62XX is not set | ||
| 432 | # CONFIG_BLK_DEV_ALI15X3 is not set | ||
| 433 | # CONFIG_BLK_DEV_CMD64X is not set | ||
| 434 | # CONFIG_BLK_DEV_TRIFLEX is not set | ||
| 435 | # CONFIG_BLK_DEV_CS5520 is not set | ||
| 436 | # CONFIG_BLK_DEV_CS5530 is not set | ||
| 437 | # CONFIG_BLK_DEV_HPT366 is not set | ||
| 438 | # CONFIG_BLK_DEV_JMICRON is not set | ||
| 439 | # CONFIG_BLK_DEV_SC1200 is not set | ||
| 440 | # CONFIG_BLK_DEV_PIIX is not set | ||
| 441 | # CONFIG_BLK_DEV_IT8213 is not set | ||
| 442 | # CONFIG_BLK_DEV_IT821X is not set | ||
| 443 | # CONFIG_BLK_DEV_NS87415 is not set | ||
| 444 | # CONFIG_BLK_DEV_PDC202XX_OLD is not set | ||
| 445 | # CONFIG_BLK_DEV_PDC202XX_NEW is not set | ||
| 446 | # CONFIG_BLK_DEV_SVWKS is not set | ||
| 447 | # CONFIG_BLK_DEV_SIIMAGE is not set | ||
| 448 | # CONFIG_BLK_DEV_SL82C105 is not set | ||
| 449 | # CONFIG_BLK_DEV_SLC90E66 is not set | ||
| 450 | # CONFIG_BLK_DEV_TRM290 is not set | ||
| 451 | # CONFIG_BLK_DEV_VIA82CXXX is not set | ||
| 452 | # CONFIG_BLK_DEV_TC86C001 is not set | ||
| 249 | CONFIG_IDE_ARM=y | 453 | CONFIG_IDE_ARM=y |
| 250 | # CONFIG_IDE_CHIPSETS is not set | ||
| 251 | # CONFIG_BLK_DEV_IDEDMA is not set | 454 | # CONFIG_BLK_DEV_IDEDMA is not set |
| 252 | # CONFIG_IDEDMA_AUTO is not set | ||
| 253 | # CONFIG_BLK_DEV_HD is not set | ||
| 254 | 455 | ||
| 255 | # | 456 | # |
| 256 | # SCSI device support | 457 | # SCSI device support |
| 257 | # | 458 | # |
| 459 | # CONFIG_RAID_ATTRS is not set | ||
| 258 | CONFIG_SCSI=m | 460 | CONFIG_SCSI=m |
| 461 | CONFIG_SCSI_DMA=y | ||
| 462 | # CONFIG_SCSI_TGT is not set | ||
| 463 | # CONFIG_SCSI_NETLINK is not set | ||
| 259 | CONFIG_SCSI_PROC_FS=y | 464 | CONFIG_SCSI_PROC_FS=y |
| 260 | 465 | ||
| 261 | # | 466 | # |
| @@ -275,17 +480,20 @@ CONFIG_CHR_DEV_SG=m | |||
| 275 | # CONFIG_SCSI_MULTI_LUN is not set | 480 | # CONFIG_SCSI_MULTI_LUN is not set |
| 276 | # CONFIG_SCSI_CONSTANTS is not set | 481 | # CONFIG_SCSI_CONSTANTS is not set |
| 277 | # CONFIG_SCSI_LOGGING is not set | 482 | # CONFIG_SCSI_LOGGING is not set |
| 483 | # CONFIG_SCSI_SCAN_ASYNC is not set | ||
| 484 | CONFIG_SCSI_WAIT_SCAN=m | ||
| 278 | 485 | ||
| 279 | # | 486 | # |
| 280 | # SCSI Transport Attributes | 487 | # SCSI Transports |
| 281 | # | 488 | # |
| 282 | # CONFIG_SCSI_SPI_ATTRS is not set | 489 | # CONFIG_SCSI_SPI_ATTRS is not set |
| 283 | # CONFIG_SCSI_FC_ATTRS is not set | 490 | # CONFIG_SCSI_FC_ATTRS is not set |
| 284 | # CONFIG_SCSI_ISCSI_ATTRS is not set | 491 | # CONFIG_SCSI_ISCSI_ATTRS is not set |
| 285 | 492 | # CONFIG_SCSI_SAS_LIBSAS is not set | |
| 286 | # | 493 | # CONFIG_SCSI_SRP_ATTRS is not set |
| 287 | # SCSI low-level drivers | 494 | CONFIG_SCSI_LOWLEVEL=y |
| 288 | # | 495 | # CONFIG_ISCSI_TCP is not set |
| 496 | # CONFIG_SCSI_CXGB3_ISCSI is not set | ||
| 289 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set | 497 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set |
| 290 | # CONFIG_SCSI_3W_9XXX is not set | 498 | # CONFIG_SCSI_3W_9XXX is not set |
| 291 | # CONFIG_SCSI_7000FASST is not set | 499 | # CONFIG_SCSI_7000FASST is not set |
| @@ -296,12 +504,18 @@ CONFIG_CHR_DEV_SG=m | |||
| 296 | # CONFIG_SCSI_AIC7XXX is not set | 504 | # CONFIG_SCSI_AIC7XXX is not set |
| 297 | # CONFIG_SCSI_AIC7XXX_OLD is not set | 505 | # CONFIG_SCSI_AIC7XXX_OLD is not set |
| 298 | # CONFIG_SCSI_AIC79XX is not set | 506 | # CONFIG_SCSI_AIC79XX is not set |
| 507 | # CONFIG_SCSI_AIC94XX is not set | ||
| 299 | # CONFIG_SCSI_DPT_I2O is not set | 508 | # CONFIG_SCSI_DPT_I2O is not set |
| 509 | # CONFIG_SCSI_ADVANSYS is not set | ||
| 300 | # CONFIG_SCSI_IN2000 is not set | 510 | # CONFIG_SCSI_IN2000 is not set |
| 511 | # CONFIG_SCSI_ARCMSR is not set | ||
| 301 | # CONFIG_MEGARAID_NEWGEN is not set | 512 | # CONFIG_MEGARAID_NEWGEN is not set |
| 302 | # CONFIG_MEGARAID_LEGACY is not set | 513 | # CONFIG_MEGARAID_LEGACY is not set |
| 303 | # CONFIG_SCSI_SATA is not set | 514 | # CONFIG_MEGARAID_SAS is not set |
| 515 | # CONFIG_SCSI_HPTIOP is not set | ||
| 304 | # CONFIG_SCSI_BUSLOGIC is not set | 516 | # CONFIG_SCSI_BUSLOGIC is not set |
| 517 | # CONFIG_LIBFC is not set | ||
| 518 | # CONFIG_FCOE is not set | ||
| 305 | # CONFIG_SCSI_DMX3191D is not set | 519 | # CONFIG_SCSI_DMX3191D is not set |
| 306 | # CONFIG_SCSI_DTC3280 is not set | 520 | # CONFIG_SCSI_DTC3280 is not set |
| 307 | # CONFIG_SCSI_EATA is not set | 521 | # CONFIG_SCSI_EATA is not set |
| @@ -314,20 +528,15 @@ CONFIG_CHR_DEV_SG=m | |||
| 314 | # CONFIG_SCSI_INIA100 is not set | 528 | # CONFIG_SCSI_INIA100 is not set |
| 315 | # CONFIG_SCSI_PPA is not set | 529 | # CONFIG_SCSI_PPA is not set |
| 316 | # CONFIG_SCSI_IMM is not set | 530 | # CONFIG_SCSI_IMM is not set |
| 531 | # CONFIG_SCSI_MVSAS is not set | ||
| 317 | # CONFIG_SCSI_NCR53C406A is not set | 532 | # CONFIG_SCSI_NCR53C406A is not set |
| 533 | # CONFIG_SCSI_STEX is not set | ||
| 318 | # CONFIG_SCSI_SYM53C8XX_2 is not set | 534 | # CONFIG_SCSI_SYM53C8XX_2 is not set |
| 319 | # CONFIG_SCSI_IPR is not set | ||
| 320 | # CONFIG_SCSI_PAS16 is not set | 535 | # CONFIG_SCSI_PAS16 is not set |
| 321 | # CONFIG_SCSI_PSI240I is not set | ||
| 322 | # CONFIG_SCSI_QLOGIC_FAS is not set | 536 | # CONFIG_SCSI_QLOGIC_FAS is not set |
| 323 | # CONFIG_SCSI_QLOGIC_FC is not set | ||
| 324 | # CONFIG_SCSI_QLOGIC_1280 is not set | 537 | # CONFIG_SCSI_QLOGIC_1280 is not set |
| 325 | CONFIG_SCSI_QLA2XXX=m | 538 | # CONFIG_SCSI_QLA_FC is not set |
| 326 | # CONFIG_SCSI_QLA21XX is not set | 539 | # CONFIG_SCSI_QLA_ISCSI is not set |
| 327 | # CONFIG_SCSI_QLA22XX is not set | ||
| 328 | # CONFIG_SCSI_QLA2300 is not set | ||
| 329 | # CONFIG_SCSI_QLA2322 is not set | ||
| 330 | # CONFIG_SCSI_QLA6312 is not set | ||
| 331 | # CONFIG_SCSI_LPFC is not set | 540 | # CONFIG_SCSI_LPFC is not set |
| 332 | # CONFIG_SCSI_SYM53C416 is not set | 541 | # CONFIG_SCSI_SYM53C416 is not set |
| 333 | # CONFIG_SCSI_DC395x is not set | 542 | # CONFIG_SCSI_DC395x is not set |
| @@ -336,123 +545,57 @@ CONFIG_SCSI_QLA2XXX=m | |||
| 336 | # CONFIG_SCSI_U14_34F is not set | 545 | # CONFIG_SCSI_U14_34F is not set |
| 337 | # CONFIG_SCSI_NSP32 is not set | 546 | # CONFIG_SCSI_NSP32 is not set |
| 338 | # CONFIG_SCSI_DEBUG is not set | 547 | # CONFIG_SCSI_DEBUG is not set |
| 339 | 548 | # CONFIG_SCSI_SRP is not set | |
| 340 | # | 549 | # CONFIG_SCSI_DH is not set |
| 341 | # Multi-device support (RAID and LVM) | 550 | # CONFIG_ATA is not set |
| 342 | # | ||
| 343 | # CONFIG_MD is not set | 551 | # CONFIG_MD is not set |
| 344 | |||
| 345 | # | ||
| 346 | # Fusion MPT device support | ||
| 347 | # | ||
| 348 | # CONFIG_FUSION is not set | 552 | # CONFIG_FUSION is not set |
| 349 | # CONFIG_FUSION_SPI is not set | ||
| 350 | # CONFIG_FUSION_FC is not set | ||
| 351 | 553 | ||
| 352 | # | 554 | # |
| 353 | # IEEE 1394 (FireWire) support | 555 | # IEEE 1394 (FireWire) support |
| 354 | # | 556 | # |
| 355 | # CONFIG_IEEE1394 is not set | ||
| 356 | 557 | ||
| 357 | # | 558 | # |
| 358 | # I2O device support | 559 | # Enable only one of the two stacks, unless you know what you are doing |
| 359 | # | 560 | # |
| 561 | # CONFIG_FIREWIRE is not set | ||
| 562 | # CONFIG_IEEE1394 is not set | ||
| 360 | # CONFIG_I2O is not set | 563 | # CONFIG_I2O is not set |
| 361 | |||
| 362 | # | ||
| 363 | # Networking support | ||
| 364 | # | ||
| 365 | CONFIG_NET=y | ||
| 366 | |||
| 367 | # | ||
| 368 | # Networking options | ||
| 369 | # | ||
| 370 | CONFIG_PACKET=y | ||
| 371 | # CONFIG_PACKET_MMAP is not set | ||
| 372 | CONFIG_UNIX=y | ||
| 373 | # CONFIG_NET_KEY is not set | ||
| 374 | CONFIG_INET=y | ||
| 375 | # CONFIG_IP_MULTICAST is not set | ||
| 376 | # CONFIG_IP_ADVANCED_ROUTER is not set | ||
| 377 | # CONFIG_IP_PNP is not set | ||
| 378 | # CONFIG_NET_IPIP is not set | ||
| 379 | # CONFIG_NET_IPGRE is not set | ||
| 380 | # CONFIG_ARPD is not set | ||
| 381 | # CONFIG_SYN_COOKIES is not set | ||
| 382 | # CONFIG_INET_AH is not set | ||
| 383 | # CONFIG_INET_ESP is not set | ||
| 384 | # CONFIG_INET_IPCOMP is not set | ||
| 385 | # CONFIG_INET_TUNNEL is not set | ||
| 386 | CONFIG_IP_TCPDIAG=y | ||
| 387 | # CONFIG_IP_TCPDIAG_IPV6 is not set | ||
| 388 | # CONFIG_IPV6 is not set | ||
| 389 | # CONFIG_NETFILTER is not set | ||
| 390 | |||
| 391 | # | ||
| 392 | # SCTP Configuration (EXPERIMENTAL) | ||
| 393 | # | ||
| 394 | # CONFIG_IP_SCTP is not set | ||
| 395 | # CONFIG_ATM is not set | ||
| 396 | # CONFIG_BRIDGE is not set | ||
| 397 | # CONFIG_VLAN_8021Q is not set | ||
| 398 | # CONFIG_DECNET is not set | ||
| 399 | # CONFIG_LLC2 is not set | ||
| 400 | # CONFIG_IPX is not set | ||
| 401 | # CONFIG_ATALK is not set | ||
| 402 | # CONFIG_X25 is not set | ||
| 403 | # CONFIG_LAPB is not set | ||
| 404 | # CONFIG_NET_DIVERT is not set | ||
| 405 | # CONFIG_ECONET is not set | ||
| 406 | # CONFIG_WAN_ROUTER is not set | ||
| 407 | |||
| 408 | # | ||
| 409 | # QoS and/or fair queueing | ||
| 410 | # | ||
| 411 | # CONFIG_NET_SCHED is not set | ||
| 412 | # CONFIG_NET_CLS_ROUTE is not set | ||
| 413 | |||
| 414 | # | ||
| 415 | # Network testing | ||
| 416 | # | ||
| 417 | # CONFIG_NET_PKTGEN is not set | ||
| 418 | # CONFIG_NETPOLL is not set | ||
| 419 | # CONFIG_NET_POLL_CONTROLLER is not set | ||
| 420 | # CONFIG_HAMRADIO is not set | ||
| 421 | # CONFIG_IRDA is not set | ||
| 422 | # CONFIG_BT is not set | ||
| 423 | CONFIG_NETDEVICES=y | 564 | CONFIG_NETDEVICES=y |
| 424 | # CONFIG_DUMMY is not set | 565 | # CONFIG_DUMMY is not set |
| 425 | # CONFIG_BONDING is not set | 566 | # CONFIG_BONDING is not set |
| 567 | # CONFIG_MACVLAN is not set | ||
| 426 | # CONFIG_EQUALIZER is not set | 568 | # CONFIG_EQUALIZER is not set |
| 427 | # CONFIG_TUN is not set | 569 | # CONFIG_TUN is not set |
| 428 | 570 | # CONFIG_VETH is not set | |
| 429 | # | ||
| 430 | # ARCnet devices | ||
| 431 | # | ||
| 432 | # CONFIG_ARCNET is not set | 571 | # CONFIG_ARCNET is not set |
| 433 | 572 | # CONFIG_PHYLIB is not set | |
| 434 | # | ||
| 435 | # Ethernet (10 or 100Mbit) | ||
| 436 | # | ||
| 437 | CONFIG_NET_ETHERNET=y | 573 | CONFIG_NET_ETHERNET=y |
| 438 | # CONFIG_MII is not set | 574 | # CONFIG_MII is not set |
| 575 | # CONFIG_AX88796 is not set | ||
| 439 | # CONFIG_HAPPYMEAL is not set | 576 | # CONFIG_HAPPYMEAL is not set |
| 440 | # CONFIG_SUNGEM is not set | 577 | # CONFIG_SUNGEM is not set |
| 578 | # CONFIG_CASSINI is not set | ||
| 441 | # CONFIG_NET_VENDOR_3COM is not set | 579 | # CONFIG_NET_VENDOR_3COM is not set |
| 442 | # CONFIG_LANCE is not set | 580 | # CONFIG_LANCE is not set |
| 443 | # CONFIG_NET_VENDOR_SMC is not set | 581 | # CONFIG_NET_VENDOR_SMC is not set |
| 444 | # CONFIG_SMC91X is not set | 582 | # CONFIG_SMC91X is not set |
| 445 | # CONFIG_DM9000 is not set | 583 | # CONFIG_DM9000 is not set |
| 584 | # CONFIG_SMC911X is not set | ||
| 585 | # CONFIG_SMSC911X is not set | ||
| 446 | # CONFIG_NET_VENDOR_RACAL is not set | 586 | # CONFIG_NET_VENDOR_RACAL is not set |
| 447 | |||
| 448 | # | ||
| 449 | # Tulip family network device support | ||
| 450 | # | ||
| 451 | # CONFIG_NET_TULIP is not set | 587 | # CONFIG_NET_TULIP is not set |
| 452 | # CONFIG_AT1700 is not set | 588 | # CONFIG_AT1700 is not set |
| 453 | # CONFIG_DEPCA is not set | 589 | # CONFIG_DEPCA is not set |
| 454 | # CONFIG_HP100 is not set | 590 | # CONFIG_HP100 is not set |
| 455 | # CONFIG_NET_ISA is not set | 591 | # CONFIG_NET_ISA is not set |
| 592 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | ||
| 593 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | ||
| 594 | # CONFIG_IBM_NEW_EMAC_TAH is not set | ||
| 595 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | ||
| 596 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 597 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 598 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 456 | CONFIG_NET_PCI=y | 599 | CONFIG_NET_PCI=y |
| 457 | # CONFIG_PCNET32 is not set | 600 | # CONFIG_PCNET32 is not set |
| 458 | # CONFIG_AMD8111_ETH is not set | 601 | # CONFIG_AMD8111_ETH is not set |
| @@ -462,56 +605,69 @@ CONFIG_NET_PCI=y | |||
| 462 | # CONFIG_B44 is not set | 605 | # CONFIG_B44 is not set |
| 463 | # CONFIG_FORCEDETH is not set | 606 | # CONFIG_FORCEDETH is not set |
| 464 | CONFIG_CS89x0=y | 607 | CONFIG_CS89x0=y |
| 465 | # CONFIG_DGRS is not set | 608 | CONFIG_CS89x0_NOEEPROM=y |
| 466 | # CONFIG_EEPRO100 is not set | ||
| 467 | # CONFIG_E100 is not set | 609 | # CONFIG_E100 is not set |
| 468 | # CONFIG_FEALNX is not set | 610 | # CONFIG_FEALNX is not set |
| 469 | # CONFIG_NATSEMI is not set | 611 | # CONFIG_NATSEMI is not set |
| 470 | # CONFIG_NE2K_PCI is not set | 612 | # CONFIG_NE2K_PCI is not set |
| 471 | # CONFIG_8139CP is not set | 613 | # CONFIG_8139CP is not set |
| 472 | # CONFIG_8139TOO is not set | 614 | # CONFIG_8139TOO is not set |
| 615 | # CONFIG_R6040 is not set | ||
| 473 | # CONFIG_SIS900 is not set | 616 | # CONFIG_SIS900 is not set |
| 474 | # CONFIG_EPIC100 is not set | 617 | # CONFIG_EPIC100 is not set |
| 618 | # CONFIG_SMSC9420 is not set | ||
| 475 | # CONFIG_SUNDANCE is not set | 619 | # CONFIG_SUNDANCE is not set |
| 476 | # CONFIG_TLAN is not set | 620 | # CONFIG_TLAN is not set |
| 477 | # CONFIG_VIA_RHINE is not set | 621 | # CONFIG_VIA_RHINE is not set |
| 622 | # CONFIG_SC92031 is not set | ||
| 478 | # CONFIG_NET_POCKET is not set | 623 | # CONFIG_NET_POCKET is not set |
| 479 | 624 | # CONFIG_ATL2 is not set | |
| 480 | # | 625 | CONFIG_NETDEV_1000=y |
| 481 | # Ethernet (1000 Mbit) | ||
| 482 | # | ||
| 483 | # CONFIG_ACENIC is not set | 626 | # CONFIG_ACENIC is not set |
| 484 | # CONFIG_DL2K is not set | 627 | # CONFIG_DL2K is not set |
| 485 | # CONFIG_E1000 is not set | 628 | # CONFIG_E1000 is not set |
| 629 | # CONFIG_E1000E is not set | ||
| 630 | # CONFIG_IP1000 is not set | ||
| 631 | # CONFIG_IGB is not set | ||
| 486 | # CONFIG_NS83820 is not set | 632 | # CONFIG_NS83820 is not set |
| 487 | # CONFIG_HAMACHI is not set | 633 | # CONFIG_HAMACHI is not set |
| 488 | # CONFIG_YELLOWFIN is not set | 634 | # CONFIG_YELLOWFIN is not set |
| 489 | # CONFIG_R8169 is not set | 635 | # CONFIG_R8169 is not set |
| 636 | # CONFIG_SIS190 is not set | ||
| 490 | # CONFIG_SKGE is not set | 637 | # CONFIG_SKGE is not set |
| 491 | # CONFIG_SK98LIN is not set | 638 | # CONFIG_SKY2 is not set |
| 492 | # CONFIG_VIA_VELOCITY is not set | 639 | # CONFIG_VIA_VELOCITY is not set |
| 493 | # CONFIG_TIGON3 is not set | 640 | # CONFIG_TIGON3 is not set |
| 494 | # CONFIG_BNX2 is not set | 641 | # CONFIG_BNX2 is not set |
| 495 | 642 | # CONFIG_QLA3XXX is not set | |
| 496 | # | 643 | # CONFIG_ATL1 is not set |
| 497 | # Ethernet (10000 Mbit) | 644 | # CONFIG_ATL1E is not set |
| 498 | # | 645 | # CONFIG_JME is not set |
| 646 | CONFIG_NETDEV_10000=y | ||
| 647 | # CONFIG_CHELSIO_T1 is not set | ||
| 648 | CONFIG_CHELSIO_T3_DEPENDS=y | ||
| 649 | # CONFIG_CHELSIO_T3 is not set | ||
| 650 | # CONFIG_ENIC is not set | ||
| 651 | # CONFIG_IXGBE is not set | ||
| 499 | # CONFIG_IXGB is not set | 652 | # CONFIG_IXGB is not set |
| 500 | # CONFIG_S2IO is not set | 653 | # CONFIG_S2IO is not set |
| 501 | 654 | # CONFIG_MYRI10GE is not set | |
| 502 | # | 655 | # CONFIG_NETXEN_NIC is not set |
| 503 | # Token Ring devices | 656 | # CONFIG_NIU is not set |
| 504 | # | 657 | # CONFIG_MLX4_EN is not set |
| 658 | # CONFIG_MLX4_CORE is not set | ||
| 659 | # CONFIG_TEHUTI is not set | ||
| 660 | # CONFIG_BNX2X is not set | ||
| 661 | # CONFIG_QLGE is not set | ||
| 662 | # CONFIG_SFC is not set | ||
| 505 | # CONFIG_TR is not set | 663 | # CONFIG_TR is not set |
| 506 | 664 | ||
| 507 | # | 665 | # |
| 508 | # Wireless LAN (non-hamradio) | 666 | # Wireless LAN |
| 509 | # | ||
| 510 | # CONFIG_NET_RADIO is not set | ||
| 511 | |||
| 512 | # | ||
| 513 | # Wan interfaces | ||
| 514 | # | 667 | # |
| 668 | # CONFIG_WLAN_PRE80211 is not set | ||
| 669 | # CONFIG_WLAN_80211 is not set | ||
| 670 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 515 | # CONFIG_WAN is not set | 671 | # CONFIG_WAN is not set |
| 516 | # CONFIG_FDDI is not set | 672 | # CONFIG_FDDI is not set |
| 517 | # CONFIG_HIPPI is not set | 673 | # CONFIG_HIPPI is not set |
| @@ -519,18 +675,17 @@ CONFIG_CS89x0=y | |||
| 519 | # CONFIG_PPP is not set | 675 | # CONFIG_PPP is not set |
| 520 | # CONFIG_SLIP is not set | 676 | # CONFIG_SLIP is not set |
| 521 | # CONFIG_NET_FC is not set | 677 | # CONFIG_NET_FC is not set |
| 522 | # CONFIG_SHAPER is not set | ||
| 523 | # CONFIG_NETCONSOLE is not set | 678 | # CONFIG_NETCONSOLE is not set |
| 524 | 679 | # CONFIG_NETPOLL is not set | |
| 525 | # | 680 | # CONFIG_NET_POLL_CONTROLLER is not set |
| 526 | # ISDN subsystem | ||
| 527 | # | ||
| 528 | # CONFIG_ISDN is not set | 681 | # CONFIG_ISDN is not set |
| 529 | 682 | ||
| 530 | # | 683 | # |
| 531 | # Input device support | 684 | # Input device support |
| 532 | # | 685 | # |
| 533 | CONFIG_INPUT=y | 686 | CONFIG_INPUT=y |
| 687 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 688 | # CONFIG_INPUT_POLLDEV is not set | ||
| 534 | 689 | ||
| 535 | # | 690 | # |
| 536 | # Userland interfaces | 691 | # Userland interfaces |
| @@ -540,7 +695,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y | |||
| 540 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | 695 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 |
| 541 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | 696 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 |
| 542 | # CONFIG_INPUT_JOYDEV is not set | 697 | # CONFIG_INPUT_JOYDEV is not set |
| 543 | # CONFIG_INPUT_TSDEV is not set | ||
| 544 | # CONFIG_INPUT_EVDEV is not set | 698 | # CONFIG_INPUT_EVDEV is not set |
| 545 | # CONFIG_INPUT_EVBUG is not set | 699 | # CONFIG_INPUT_EVBUG is not set |
| 546 | 700 | ||
| @@ -553,14 +707,25 @@ CONFIG_KEYBOARD_ATKBD=y | |||
| 553 | # CONFIG_KEYBOARD_LKKBD is not set | 707 | # CONFIG_KEYBOARD_LKKBD is not set |
| 554 | # CONFIG_KEYBOARD_XTKBD is not set | 708 | # CONFIG_KEYBOARD_XTKBD is not set |
| 555 | # CONFIG_KEYBOARD_NEWTON is not set | 709 | # CONFIG_KEYBOARD_NEWTON is not set |
| 710 | # CONFIG_KEYBOARD_STOWAWAY is not set | ||
| 556 | CONFIG_INPUT_MOUSE=y | 711 | CONFIG_INPUT_MOUSE=y |
| 557 | CONFIG_MOUSE_PS2=y | 712 | CONFIG_MOUSE_PS2=y |
| 713 | CONFIG_MOUSE_PS2_ALPS=y | ||
| 714 | CONFIG_MOUSE_PS2_LOGIPS2PP=y | ||
| 715 | CONFIG_MOUSE_PS2_SYNAPTICS=y | ||
| 716 | CONFIG_MOUSE_PS2_LIFEBOOK=y | ||
| 717 | CONFIG_MOUSE_PS2_TRACKPOINT=y | ||
| 718 | # CONFIG_MOUSE_PS2_ELANTECH is not set | ||
| 719 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | ||
| 558 | # CONFIG_MOUSE_SERIAL is not set | 720 | # CONFIG_MOUSE_SERIAL is not set |
| 721 | # CONFIG_MOUSE_APPLETOUCH is not set | ||
| 722 | # CONFIG_MOUSE_BCM5974 is not set | ||
| 559 | # CONFIG_MOUSE_INPORT is not set | 723 | # CONFIG_MOUSE_INPORT is not set |
| 560 | # CONFIG_MOUSE_LOGIBM is not set | 724 | # CONFIG_MOUSE_LOGIBM is not set |
| 561 | # CONFIG_MOUSE_PC110PAD is not set | 725 | # CONFIG_MOUSE_PC110PAD is not set |
| 562 | # CONFIG_MOUSE_VSXXXAA is not set | 726 | # CONFIG_MOUSE_VSXXXAA is not set |
| 563 | # CONFIG_INPUT_JOYSTICK is not set | 727 | # CONFIG_INPUT_JOYSTICK is not set |
| 728 | # CONFIG_INPUT_TABLET is not set | ||
| 564 | # CONFIG_INPUT_TOUCHSCREEN is not set | 729 | # CONFIG_INPUT_TOUCHSCREEN is not set |
| 565 | # CONFIG_INPUT_MISC is not set | 730 | # CONFIG_INPUT_MISC is not set |
| 566 | 731 | ||
| @@ -580,16 +745,22 @@ CONFIG_SERIO_LIBPS2=y | |||
| 580 | # Character devices | 745 | # Character devices |
| 581 | # | 746 | # |
| 582 | CONFIG_VT=y | 747 | CONFIG_VT=y |
| 748 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 583 | CONFIG_VT_CONSOLE=y | 749 | CONFIG_VT_CONSOLE=y |
| 584 | CONFIG_HW_CONSOLE=y | 750 | CONFIG_HW_CONSOLE=y |
| 751 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | ||
| 752 | CONFIG_DEVKMEM=y | ||
| 585 | # CONFIG_SERIAL_NONSTANDARD is not set | 753 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 754 | # CONFIG_NOZOMI is not set | ||
| 586 | 755 | ||
| 587 | # | 756 | # |
| 588 | # Serial drivers | 757 | # Serial drivers |
| 589 | # | 758 | # |
| 590 | CONFIG_SERIAL_8250=y | 759 | CONFIG_SERIAL_8250=y |
| 591 | CONFIG_SERIAL_8250_CONSOLE=y | 760 | CONFIG_SERIAL_8250_CONSOLE=y |
| 761 | CONFIG_SERIAL_8250_PCI=y | ||
| 592 | CONFIG_SERIAL_8250_NR_UARTS=4 | 762 | CONFIG_SERIAL_8250_NR_UARTS=4 |
| 763 | CONFIG_SERIAL_8250_RUNTIME_UARTS=4 | ||
| 593 | # CONFIG_SERIAL_8250_EXTENDED is not set | 764 | # CONFIG_SERIAL_8250_EXTENDED is not set |
| 594 | 765 | ||
| 595 | # | 766 | # |
| @@ -599,90 +770,122 @@ CONFIG_SERIAL_CORE=y | |||
| 599 | CONFIG_SERIAL_CORE_CONSOLE=y | 770 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 600 | # CONFIG_SERIAL_JSM is not set | 771 | # CONFIG_SERIAL_JSM is not set |
| 601 | CONFIG_UNIX98_PTYS=y | 772 | CONFIG_UNIX98_PTYS=y |
| 773 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 602 | CONFIG_LEGACY_PTYS=y | 774 | CONFIG_LEGACY_PTYS=y |
| 603 | CONFIG_LEGACY_PTY_COUNT=256 | 775 | CONFIG_LEGACY_PTY_COUNT=256 |
| 604 | CONFIG_PRINTER=m | 776 | CONFIG_PRINTER=m |
| 605 | # CONFIG_LP_CONSOLE is not set | 777 | # CONFIG_LP_CONSOLE is not set |
| 606 | # CONFIG_PPDEV is not set | 778 | # CONFIG_PPDEV is not set |
| 607 | # CONFIG_TIPAR is not set | ||
| 608 | |||
| 609 | # | ||
| 610 | # IPMI | ||
| 611 | # | ||
| 612 | # CONFIG_IPMI_HANDLER is not set | 779 | # CONFIG_IPMI_HANDLER is not set |
| 613 | 780 | CONFIG_HW_RANDOM=m | |
| 614 | # | ||
| 615 | # Watchdog Cards | ||
| 616 | # | ||
| 617 | # CONFIG_WATCHDOG is not set | ||
| 618 | # CONFIG_NVRAM is not set | 781 | # CONFIG_NVRAM is not set |
| 619 | CONFIG_RTC=y | ||
| 620 | # CONFIG_DTLK is not set | 782 | # CONFIG_DTLK is not set |
| 621 | # CONFIG_R3964 is not set | 783 | # CONFIG_R3964 is not set |
| 622 | # CONFIG_APPLICOM is not set | 784 | # CONFIG_APPLICOM is not set |
| 623 | |||
| 624 | # | ||
| 625 | # Ftape, the floppy tape device driver | ||
| 626 | # | ||
| 627 | # CONFIG_DRM is not set | ||
| 628 | # CONFIG_RAW_DRIVER is not set | 785 | # CONFIG_RAW_DRIVER is not set |
| 786 | # CONFIG_TCG_TPM is not set | ||
| 787 | CONFIG_DEVPORT=y | ||
| 788 | # CONFIG_I2C is not set | ||
| 789 | # CONFIG_SPI is not set | ||
| 790 | # CONFIG_W1 is not set | ||
| 791 | # CONFIG_POWER_SUPPLY is not set | ||
| 792 | # CONFIG_HWMON is not set | ||
| 793 | # CONFIG_THERMAL is not set | ||
| 794 | # CONFIG_THERMAL_HWMON is not set | ||
| 795 | # CONFIG_WATCHDOG is not set | ||
| 796 | CONFIG_SSB_POSSIBLE=y | ||
| 629 | 797 | ||
| 630 | # | 798 | # |
| 631 | # TPM devices | 799 | # Sonics Silicon Backplane |
| 632 | # | 800 | # |
| 633 | # CONFIG_TCG_TPM is not set | 801 | # CONFIG_SSB is not set |
| 634 | 802 | ||
| 635 | # | 803 | # |
| 636 | # I2C support | 804 | # Multifunction device drivers |
| 637 | # | 805 | # |
| 638 | # CONFIG_I2C is not set | 806 | # CONFIG_MFD_CORE is not set |
| 807 | # CONFIG_MFD_SM501 is not set | ||
| 808 | # CONFIG_HTC_PASIC3 is not set | ||
| 809 | # CONFIG_MFD_TMIO is not set | ||
| 639 | 810 | ||
| 640 | # | 811 | # |
| 641 | # Misc devices | 812 | # Multimedia devices |
| 642 | # | 813 | # |
| 643 | 814 | ||
| 644 | # | 815 | # |
| 645 | # Multimedia devices | 816 | # Multimedia core support |
| 646 | # | 817 | # |
| 647 | # CONFIG_VIDEO_DEV is not set | 818 | # CONFIG_VIDEO_DEV is not set |
| 819 | # CONFIG_DVB_CORE is not set | ||
| 820 | # CONFIG_VIDEO_MEDIA is not set | ||
| 648 | 821 | ||
| 649 | # | 822 | # |
| 650 | # Digital Video Broadcasting Devices | 823 | # Multimedia drivers |
| 651 | # | 824 | # |
| 652 | # CONFIG_DVB is not set | 825 | # CONFIG_DAB is not set |
| 653 | 826 | ||
| 654 | # | 827 | # |
| 655 | # Graphics support | 828 | # Graphics support |
| 656 | # | 829 | # |
| 830 | # CONFIG_DRM is not set | ||
| 831 | # CONFIG_VGASTATE is not set | ||
| 832 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 657 | CONFIG_FB=y | 833 | CONFIG_FB=y |
| 834 | # CONFIG_FIRMWARE_EDID is not set | ||
| 835 | # CONFIG_FB_DDC is not set | ||
| 836 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 658 | CONFIG_FB_CFB_FILLRECT=y | 837 | CONFIG_FB_CFB_FILLRECT=y |
| 659 | CONFIG_FB_CFB_COPYAREA=y | 838 | CONFIG_FB_CFB_COPYAREA=y |
| 660 | CONFIG_FB_CFB_IMAGEBLIT=y | 839 | CONFIG_FB_CFB_IMAGEBLIT=y |
| 661 | CONFIG_FB_SOFT_CURSOR=y | 840 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set |
| 841 | # CONFIG_FB_SYS_FILLRECT is not set | ||
| 842 | # CONFIG_FB_SYS_COPYAREA is not set | ||
| 843 | # CONFIG_FB_SYS_IMAGEBLIT is not set | ||
| 844 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 845 | # CONFIG_FB_SYS_FOPS is not set | ||
| 846 | # CONFIG_FB_SVGALIB is not set | ||
| 662 | # CONFIG_FB_MACMODES is not set | 847 | # CONFIG_FB_MACMODES is not set |
| 848 | # CONFIG_FB_BACKLIGHT is not set | ||
| 663 | # CONFIG_FB_MODE_HELPERS is not set | 849 | # CONFIG_FB_MODE_HELPERS is not set |
| 664 | # CONFIG_FB_TILEBLITTING is not set | 850 | # CONFIG_FB_TILEBLITTING is not set |
| 851 | |||
| 852 | # | ||
| 853 | # Frame buffer hardware drivers | ||
| 854 | # | ||
| 665 | # CONFIG_FB_CIRRUS is not set | 855 | # CONFIG_FB_CIRRUS is not set |
| 666 | # CONFIG_FB_PM2 is not set | 856 | # CONFIG_FB_PM2 is not set |
| 667 | CONFIG_FB_CYBER2000=y | 857 | CONFIG_FB_CYBER2000=y |
| 668 | # CONFIG_FB_ASILIANT is not set | 858 | # CONFIG_FB_ASILIANT is not set |
| 669 | # CONFIG_FB_IMSTT is not set | 859 | # CONFIG_FB_IMSTT is not set |
| 860 | # CONFIG_FB_S1D13XXX is not set | ||
| 670 | # CONFIG_FB_NVIDIA is not set | 861 | # CONFIG_FB_NVIDIA is not set |
| 671 | # CONFIG_FB_RIVA is not set | 862 | # CONFIG_FB_RIVA is not set |
| 672 | # CONFIG_FB_MATROX is not set | 863 | # CONFIG_FB_MATROX is not set |
| 673 | # CONFIG_FB_RADEON_OLD is not set | ||
| 674 | # CONFIG_FB_RADEON is not set | 864 | # CONFIG_FB_RADEON is not set |
| 675 | # CONFIG_FB_ATY128 is not set | 865 | # CONFIG_FB_ATY128 is not set |
| 676 | # CONFIG_FB_ATY is not set | 866 | # CONFIG_FB_ATY is not set |
| 867 | # CONFIG_FB_S3 is not set | ||
| 677 | # CONFIG_FB_SAVAGE is not set | 868 | # CONFIG_FB_SAVAGE is not set |
| 678 | # CONFIG_FB_SIS is not set | 869 | # CONFIG_FB_SIS is not set |
| 870 | # CONFIG_FB_VIA is not set | ||
| 679 | # CONFIG_FB_NEOMAGIC is not set | 871 | # CONFIG_FB_NEOMAGIC is not set |
| 680 | # CONFIG_FB_KYRO is not set | 872 | # CONFIG_FB_KYRO is not set |
| 681 | # CONFIG_FB_3DFX is not set | 873 | # CONFIG_FB_3DFX is not set |
| 682 | # CONFIG_FB_VOODOO1 is not set | 874 | # CONFIG_FB_VOODOO1 is not set |
| 875 | # CONFIG_FB_VT8623 is not set | ||
| 683 | # CONFIG_FB_TRIDENT is not set | 876 | # CONFIG_FB_TRIDENT is not set |
| 684 | # CONFIG_FB_S1D13XXX is not set | 877 | # CONFIG_FB_ARK is not set |
| 878 | # CONFIG_FB_PM3 is not set | ||
| 879 | # CONFIG_FB_CARMINE is not set | ||
| 685 | # CONFIG_FB_VIRTUAL is not set | 880 | # CONFIG_FB_VIRTUAL is not set |
| 881 | # CONFIG_FB_METRONOME is not set | ||
| 882 | # CONFIG_FB_MB862XX is not set | ||
| 883 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 884 | |||
| 885 | # | ||
| 886 | # Display device support | ||
| 887 | # | ||
| 888 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 686 | 889 | ||
| 687 | # | 890 | # |
| 688 | # Console display driver support | 891 | # Console display driver support |
| @@ -691,126 +894,132 @@ CONFIG_FB_CYBER2000=y | |||
| 691 | # CONFIG_MDA_CONSOLE is not set | 894 | # CONFIG_MDA_CONSOLE is not set |
| 692 | CONFIG_DUMMY_CONSOLE=y | 895 | CONFIG_DUMMY_CONSOLE=y |
| 693 | CONFIG_FRAMEBUFFER_CONSOLE=y | 896 | CONFIG_FRAMEBUFFER_CONSOLE=y |
| 897 | # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set | ||
| 898 | # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set | ||
| 694 | # CONFIG_FONTS is not set | 899 | # CONFIG_FONTS is not set |
| 695 | CONFIG_FONT_8x8=y | 900 | CONFIG_FONT_8x8=y |
| 696 | CONFIG_FONT_8x16=y | 901 | CONFIG_FONT_8x16=y |
| 697 | |||
| 698 | # | ||
| 699 | # Logo configuration | ||
| 700 | # | ||
| 701 | CONFIG_LOGO=y | 902 | CONFIG_LOGO=y |
| 702 | # CONFIG_LOGO_LINUX_MONO is not set | 903 | # CONFIG_LOGO_LINUX_MONO is not set |
| 703 | # CONFIG_LOGO_LINUX_VGA16 is not set | 904 | # CONFIG_LOGO_LINUX_VGA16 is not set |
| 704 | CONFIG_LOGO_LINUX_CLUT224=y | 905 | CONFIG_LOGO_LINUX_CLUT224=y |
| 705 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 706 | |||
| 707 | # | ||
| 708 | # Sound | ||
| 709 | # | ||
| 710 | CONFIG_SOUND=m | 906 | CONFIG_SOUND=m |
| 711 | 907 | CONFIG_SOUND_OSS_CORE=y | |
| 712 | # | ||
| 713 | # Advanced Linux Sound Architecture | ||
| 714 | # | ||
| 715 | # CONFIG_SND is not set | 908 | # CONFIG_SND is not set |
| 716 | |||
| 717 | # | ||
| 718 | # Open Sound System | ||
| 719 | # | ||
| 720 | CONFIG_SOUND_PRIME=m | 909 | CONFIG_SOUND_PRIME=m |
| 721 | # CONFIG_SOUND_BT878 is not set | ||
| 722 | # CONFIG_SOUND_CMPCI is not set | ||
| 723 | # CONFIG_SOUND_EMU10K1 is not set | ||
| 724 | # CONFIG_SOUND_FUSION is not set | ||
| 725 | # CONFIG_SOUND_CS4281 is not set | ||
| 726 | # CONFIG_SOUND_ES1370 is not set | ||
| 727 | # CONFIG_SOUND_ES1371 is not set | ||
| 728 | # CONFIG_SOUND_ESSSOLO1 is not set | ||
| 729 | # CONFIG_SOUND_MAESTRO is not set | ||
| 730 | # CONFIG_SOUND_MAESTRO3 is not set | ||
| 731 | # CONFIG_SOUND_ICH is not set | ||
| 732 | # CONFIG_SOUND_SONICVIBES is not set | ||
| 733 | # CONFIG_SOUND_TRIDENT is not set | ||
| 734 | # CONFIG_SOUND_MSNDCLAS is not set | 910 | # CONFIG_SOUND_MSNDCLAS is not set |
| 735 | # CONFIG_SOUND_MSNDPIN is not set | 911 | # CONFIG_SOUND_MSNDPIN is not set |
| 736 | # CONFIG_SOUND_VIA82CXXX is not set | ||
| 737 | CONFIG_SOUND_OSS=m | 912 | CONFIG_SOUND_OSS=m |
| 738 | # CONFIG_SOUND_TRACEINIT is not set | 913 | # CONFIG_SOUND_TRACEINIT is not set |
| 739 | # CONFIG_SOUND_DMAP is not set | 914 | # CONFIG_SOUND_DMAP is not set |
| 740 | # CONFIG_SOUND_AD1816 is not set | ||
| 741 | # CONFIG_SOUND_AD1889 is not set | ||
| 742 | # CONFIG_SOUND_SGALAXY is not set | ||
| 743 | CONFIG_SOUND_ADLIB=m | ||
| 744 | # CONFIG_SOUND_ACI_MIXER is not set | ||
| 745 | # CONFIG_SOUND_CS4232 is not set | ||
| 746 | # CONFIG_SOUND_SSCAPE is not set | 915 | # CONFIG_SOUND_SSCAPE is not set |
| 747 | # CONFIG_SOUND_GUS is not set | ||
| 748 | # CONFIG_SOUND_VMIDI is not set | 916 | # CONFIG_SOUND_VMIDI is not set |
| 749 | # CONFIG_SOUND_TRIX is not set | 917 | # CONFIG_SOUND_TRIX is not set |
| 750 | # CONFIG_SOUND_MSS is not set | 918 | # CONFIG_SOUND_MSS is not set |
| 751 | # CONFIG_SOUND_MPU401 is not set | 919 | # CONFIG_SOUND_MPU401 is not set |
| 752 | # CONFIG_SOUND_NM256 is not set | ||
| 753 | # CONFIG_SOUND_MAD16 is not set | ||
| 754 | # CONFIG_SOUND_PAS is not set | 920 | # CONFIG_SOUND_PAS is not set |
| 755 | # CONFIG_SOUND_PSS is not set | 921 | # CONFIG_SOUND_PSS is not set |
| 756 | CONFIG_SOUND_SB=m | 922 | CONFIG_SOUND_SB=m |
| 757 | # CONFIG_SOUND_AWE32_SYNTH is not set | ||
| 758 | # CONFIG_SOUND_WAVEFRONT is not set | ||
| 759 | # CONFIG_SOUND_MAUI is not set | ||
| 760 | # CONFIG_SOUND_YM3812 is not set | 923 | # CONFIG_SOUND_YM3812 is not set |
| 761 | # CONFIG_SOUND_OPL3SA1 is not set | ||
| 762 | # CONFIG_SOUND_OPL3SA2 is not set | ||
| 763 | # CONFIG_SOUND_YMFPCI is not set | ||
| 764 | # CONFIG_SOUND_UART6850 is not set | 924 | # CONFIG_SOUND_UART6850 is not set |
| 765 | # CONFIG_SOUND_AEDSP16 is not set | 925 | # CONFIG_SOUND_AEDSP16 is not set |
| 766 | # CONFIG_SOUND_KAHLUA is not set | 926 | # CONFIG_SOUND_KAHLUA is not set |
| 767 | # CONFIG_SOUND_ALI5455 is not set | 927 | CONFIG_HID_SUPPORT=y |
| 768 | # CONFIG_SOUND_FORTE is not set | 928 | CONFIG_HID=y |
| 769 | # CONFIG_SOUND_RME96XX is not set | 929 | # CONFIG_HID_DEBUG is not set |
| 770 | # CONFIG_SOUND_AD1980 is not set | 930 | # CONFIG_HIDRAW is not set |
| 931 | # CONFIG_HID_PID is not set | ||
| 771 | 932 | ||
| 772 | # | 933 | # |
| 773 | # USB support | 934 | # Special HID drivers |
| 774 | # | 935 | # |
| 936 | CONFIG_HID_COMPAT=y | ||
| 937 | CONFIG_USB_SUPPORT=y | ||
| 775 | CONFIG_USB_ARCH_HAS_HCD=y | 938 | CONFIG_USB_ARCH_HAS_HCD=y |
| 776 | CONFIG_USB_ARCH_HAS_OHCI=y | 939 | CONFIG_USB_ARCH_HAS_OHCI=y |
| 940 | CONFIG_USB_ARCH_HAS_EHCI=y | ||
| 777 | # CONFIG_USB is not set | 941 | # CONFIG_USB is not set |
| 778 | 942 | ||
| 779 | # | 943 | # |
| 780 | # USB Gadget Support | 944 | # Enable Host or Gadget support to see Inventra options |
| 781 | # | 945 | # |
| 782 | # CONFIG_USB_GADGET is not set | ||
| 783 | 946 | ||
| 784 | # | 947 | # |
| 785 | # MMC/SD Card support | 948 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; |
| 786 | # | 949 | # |
| 950 | # CONFIG_USB_GADGET is not set | ||
| 951 | # CONFIG_UWB is not set | ||
| 787 | # CONFIG_MMC is not set | 952 | # CONFIG_MMC is not set |
| 953 | # CONFIG_MEMSTICK is not set | ||
| 954 | # CONFIG_ACCESSIBILITY is not set | ||
| 955 | # CONFIG_NEW_LEDS is not set | ||
| 956 | CONFIG_RTC_LIB=y | ||
| 957 | CONFIG_RTC_CLASS=y | ||
| 958 | CONFIG_RTC_HCTOSYS=y | ||
| 959 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 960 | # CONFIG_RTC_DEBUG is not set | ||
| 961 | |||
| 962 | # | ||
| 963 | # RTC interfaces | ||
| 964 | # | ||
| 965 | CONFIG_RTC_INTF_SYSFS=y | ||
| 966 | CONFIG_RTC_INTF_PROC=y | ||
| 967 | CONFIG_RTC_INTF_DEV=y | ||
| 968 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 969 | # CONFIG_RTC_DRV_TEST is not set | ||
| 970 | |||
| 971 | # | ||
| 972 | # SPI RTC drivers | ||
| 973 | # | ||
| 974 | |||
| 975 | # | ||
| 976 | # Platform RTC drivers | ||
| 977 | # | ||
| 978 | CONFIG_RTC_DRV_CMOS=y | ||
| 979 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 980 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 981 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 982 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 983 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 984 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 985 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 986 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 987 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 988 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 989 | |||
| 990 | # | ||
| 991 | # on-CPU RTC drivers | ||
| 992 | # | ||
| 993 | # CONFIG_DMADEVICES is not set | ||
| 994 | # CONFIG_AUXDISPLAY is not set | ||
| 995 | # CONFIG_REGULATOR is not set | ||
| 996 | # CONFIG_UIO is not set | ||
| 788 | 997 | ||
| 789 | # | 998 | # |
| 790 | # File systems | 999 | # File systems |
| 791 | # | 1000 | # |
| 792 | CONFIG_EXT2_FS=y | 1001 | CONFIG_EXT2_FS=y |
| 793 | # CONFIG_EXT2_FS_XATTR is not set | 1002 | # CONFIG_EXT2_FS_XATTR is not set |
| 1003 | # CONFIG_EXT2_FS_XIP is not set | ||
| 794 | CONFIG_EXT3_FS=y | 1004 | CONFIG_EXT3_FS=y |
| 795 | CONFIG_EXT3_FS_XATTR=y | 1005 | CONFIG_EXT3_FS_XATTR=y |
| 796 | # CONFIG_EXT3_FS_POSIX_ACL is not set | 1006 | # CONFIG_EXT3_FS_POSIX_ACL is not set |
| 797 | # CONFIG_EXT3_FS_SECURITY is not set | 1007 | # CONFIG_EXT3_FS_SECURITY is not set |
| 1008 | # CONFIG_EXT4_FS is not set | ||
| 798 | CONFIG_JBD=y | 1009 | CONFIG_JBD=y |
| 799 | # CONFIG_JBD_DEBUG is not set | ||
| 800 | CONFIG_FS_MBCACHE=y | 1010 | CONFIG_FS_MBCACHE=y |
| 801 | # CONFIG_REISERFS_FS is not set | 1011 | # CONFIG_REISERFS_FS is not set |
| 802 | # CONFIG_JFS_FS is not set | 1012 | # CONFIG_JFS_FS is not set |
| 803 | 1013 | # CONFIG_FS_POSIX_ACL is not set | |
| 804 | # | 1014 | CONFIG_FILE_LOCKING=y |
| 805 | # XFS support | ||
| 806 | # | ||
| 807 | # CONFIG_XFS_FS is not set | 1015 | # CONFIG_XFS_FS is not set |
| 808 | # CONFIG_MINIX_FS is not set | 1016 | # CONFIG_OCFS2_FS is not set |
| 809 | # CONFIG_ROMFS_FS is not set | ||
| 810 | # CONFIG_QUOTA is not set | ||
| 811 | CONFIG_DNOTIFY=y | 1017 | CONFIG_DNOTIFY=y |
| 1018 | # CONFIG_INOTIFY is not set | ||
| 1019 | # CONFIG_QUOTA is not set | ||
| 812 | # CONFIG_AUTOFS_FS is not set | 1020 | # CONFIG_AUTOFS_FS is not set |
| 813 | # CONFIG_AUTOFS4_FS is not set | 1021 | # CONFIG_AUTOFS4_FS is not set |
| 1022 | # CONFIG_FUSE_FS is not set | ||
| 814 | 1023 | ||
| 815 | # | 1024 | # |
| 816 | # CD-ROM/DVD Filesystems | 1025 | # CD-ROM/DVD Filesystems |
| @@ -834,14 +1043,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | |||
| 834 | # Pseudo filesystems | 1043 | # Pseudo filesystems |
| 835 | # | 1044 | # |
| 836 | CONFIG_PROC_FS=y | 1045 | CONFIG_PROC_FS=y |
| 1046 | CONFIG_PROC_SYSCTL=y | ||
| 1047 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 837 | CONFIG_SYSFS=y | 1048 | CONFIG_SYSFS=y |
| 838 | CONFIG_DEVFS_FS=y | ||
| 839 | CONFIG_DEVFS_MOUNT=y | ||
| 840 | # CONFIG_DEVFS_DEBUG is not set | ||
| 841 | # CONFIG_DEVPTS_FS_XATTR is not set | ||
| 842 | # CONFIG_TMPFS is not set | 1049 | # CONFIG_TMPFS is not set |
| 843 | # CONFIG_HUGETLB_PAGE is not set | 1050 | # CONFIG_HUGETLB_PAGE is not set |
| 844 | CONFIG_RAMFS=y | 1051 | # CONFIG_CONFIGFS_FS is not set |
| 845 | 1052 | ||
| 846 | # | 1053 | # |
| 847 | # Miscellaneous filesystems | 1054 | # Miscellaneous filesystems |
| @@ -855,22 +1062,27 @@ CONFIG_RAMFS=y | |||
| 855 | # CONFIG_EFS_FS is not set | 1062 | # CONFIG_EFS_FS is not set |
| 856 | # CONFIG_CRAMFS is not set | 1063 | # CONFIG_CRAMFS is not set |
| 857 | # CONFIG_VXFS_FS is not set | 1064 | # CONFIG_VXFS_FS is not set |
| 1065 | # CONFIG_MINIX_FS is not set | ||
| 1066 | # CONFIG_OMFS_FS is not set | ||
| 858 | # CONFIG_HPFS_FS is not set | 1067 | # CONFIG_HPFS_FS is not set |
| 859 | # CONFIG_QNX4FS_FS is not set | 1068 | # CONFIG_QNX4FS_FS is not set |
| 1069 | # CONFIG_ROMFS_FS is not set | ||
| 860 | # CONFIG_SYSV_FS is not set | 1070 | # CONFIG_SYSV_FS is not set |
| 861 | # CONFIG_UFS_FS is not set | 1071 | # CONFIG_UFS_FS is not set |
| 862 | 1072 | CONFIG_NETWORK_FILESYSTEMS=y | |
| 863 | # | 1073 | CONFIG_NFS_FS=y |
| 864 | # Network File Systems | ||
| 865 | # | ||
| 866 | CONFIG_NFS_FS=m | ||
| 867 | CONFIG_NFS_V3=y | 1074 | CONFIG_NFS_V3=y |
| 1075 | # CONFIG_NFS_V3_ACL is not set | ||
| 868 | # CONFIG_NFS_V4 is not set | 1076 | # CONFIG_NFS_V4 is not set |
| 869 | # CONFIG_NFS_DIRECTIO is not set | 1077 | CONFIG_NFSD=m |
| 870 | # CONFIG_NFSD is not set | 1078 | # CONFIG_NFSD_V3 is not set |
| 871 | CONFIG_LOCKD=m | 1079 | # CONFIG_NFSD_V4 is not set |
| 1080 | CONFIG_LOCKD=y | ||
| 872 | CONFIG_LOCKD_V4=y | 1081 | CONFIG_LOCKD_V4=y |
| 873 | CONFIG_SUNRPC=m | 1082 | CONFIG_EXPORTFS=m |
| 1083 | CONFIG_NFS_COMMON=y | ||
| 1084 | CONFIG_SUNRPC=y | ||
| 1085 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 874 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 1086 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 875 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1087 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 876 | # CONFIG_SMB_FS is not set | 1088 | # CONFIG_SMB_FS is not set |
| @@ -897,11 +1109,9 @@ CONFIG_MSDOS_PARTITION=y | |||
| 897 | # CONFIG_SGI_PARTITION is not set | 1109 | # CONFIG_SGI_PARTITION is not set |
| 898 | # CONFIG_ULTRIX_PARTITION is not set | 1110 | # CONFIG_ULTRIX_PARTITION is not set |
| 899 | # CONFIG_SUN_PARTITION is not set | 1111 | # CONFIG_SUN_PARTITION is not set |
| 1112 | # CONFIG_KARMA_PARTITION is not set | ||
| 900 | # CONFIG_EFI_PARTITION is not set | 1113 | # CONFIG_EFI_PARTITION is not set |
| 901 | 1114 | # CONFIG_SYSV68_PARTITION is not set | |
| 902 | # | ||
| 903 | # Native Language Support | ||
| 904 | # | ||
| 905 | CONFIG_NLS=m | 1115 | CONFIG_NLS=m |
| 906 | CONFIG_NLS_DEFAULT="iso8859-1" | 1116 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 907 | CONFIG_NLS_CODEPAGE_437=m | 1117 | CONFIG_NLS_CODEPAGE_437=m |
| @@ -942,30 +1152,74 @@ CONFIG_NLS_ISO8859_1=m | |||
| 942 | # CONFIG_NLS_KOI8_R is not set | 1152 | # CONFIG_NLS_KOI8_R is not set |
| 943 | # CONFIG_NLS_KOI8_U is not set | 1153 | # CONFIG_NLS_KOI8_U is not set |
| 944 | # CONFIG_NLS_UTF8 is not set | 1154 | # CONFIG_NLS_UTF8 is not set |
| 945 | 1155 | # CONFIG_DLM is not set | |
| 946 | # | ||
| 947 | # Profiling support | ||
| 948 | # | ||
| 949 | # CONFIG_PROFILING is not set | ||
| 950 | 1156 | ||
| 951 | # | 1157 | # |
| 952 | # Kernel hacking | 1158 | # Kernel hacking |
| 953 | # | 1159 | # |
| 954 | # CONFIG_PRINTK_TIME is not set | 1160 | # CONFIG_PRINTK_TIME is not set |
| 955 | CONFIG_DEBUG_KERNEL=y | 1161 | # CONFIG_ENABLE_WARN_DEPRECATED is not set |
| 1162 | # CONFIG_ENABLE_MUST_CHECK is not set | ||
| 1163 | CONFIG_FRAME_WARN=1024 | ||
| 956 | # CONFIG_MAGIC_SYSRQ is not set | 1164 | # CONFIG_MAGIC_SYSRQ is not set |
| 957 | CONFIG_LOG_BUF_SHIFT=14 | 1165 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1166 | # CONFIG_DEBUG_FS is not set | ||
| 1167 | # CONFIG_HEADERS_CHECK is not set | ||
| 1168 | CONFIG_DEBUG_KERNEL=y | ||
| 1169 | # CONFIG_DEBUG_SHIRQ is not set | ||
| 1170 | CONFIG_DETECT_SOFTLOCKUP=y | ||
| 1171 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1172 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1173 | # CONFIG_SCHED_DEBUG is not set | ||
| 958 | # CONFIG_SCHEDSTATS is not set | 1174 | # CONFIG_SCHEDSTATS is not set |
| 1175 | # CONFIG_TIMER_STATS is not set | ||
| 1176 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 959 | # CONFIG_DEBUG_SLAB is not set | 1177 | # CONFIG_DEBUG_SLAB is not set |
| 1178 | # CONFIG_DEBUG_RT_MUTEXES is not set | ||
| 1179 | # CONFIG_RT_MUTEX_TESTER is not set | ||
| 960 | # CONFIG_DEBUG_SPINLOCK is not set | 1180 | # CONFIG_DEBUG_SPINLOCK is not set |
| 1181 | # CONFIG_DEBUG_MUTEXES is not set | ||
| 1182 | # CONFIG_DEBUG_LOCK_ALLOC is not set | ||
| 1183 | # CONFIG_PROVE_LOCKING is not set | ||
| 1184 | # CONFIG_LOCK_STAT is not set | ||
| 961 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set | 1185 | # CONFIG_DEBUG_SPINLOCK_SLEEP is not set |
| 1186 | # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set | ||
| 962 | # CONFIG_DEBUG_KOBJECT is not set | 1187 | # CONFIG_DEBUG_KOBJECT is not set |
| 963 | CONFIG_DEBUG_BUGVERBOSE=y | 1188 | CONFIG_DEBUG_BUGVERBOSE=y |
| 964 | # CONFIG_DEBUG_INFO is not set | 1189 | # CONFIG_DEBUG_INFO is not set |
| 965 | # CONFIG_DEBUG_FS is not set | 1190 | # CONFIG_DEBUG_VM is not set |
| 1191 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1192 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 1193 | # CONFIG_DEBUG_LIST is not set | ||
| 1194 | # CONFIG_DEBUG_SG is not set | ||
| 1195 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 966 | CONFIG_FRAME_POINTER=y | 1196 | CONFIG_FRAME_POINTER=y |
| 1197 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1198 | # CONFIG_RCU_TORTURE_TEST is not set | ||
| 1199 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1200 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1201 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1202 | # CONFIG_FAULT_INJECTION is not set | ||
| 1203 | # CONFIG_LATENCYTOP is not set | ||
| 1204 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1205 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1206 | |||
| 1207 | # | ||
| 1208 | # Tracers | ||
| 1209 | # | ||
| 1210 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1211 | # CONFIG_SCHED_TRACER is not set | ||
| 1212 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1213 | # CONFIG_BOOT_TRACER is not set | ||
| 1214 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1215 | # CONFIG_STACK_TRACER is not set | ||
| 1216 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1217 | # CONFIG_SAMPLES is not set | ||
| 1218 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 1219 | # CONFIG_KGDB is not set | ||
| 967 | CONFIG_DEBUG_USER=y | 1220 | CONFIG_DEBUG_USER=y |
| 968 | # CONFIG_DEBUG_ERRORS is not set | 1221 | # CONFIG_DEBUG_ERRORS is not set |
| 1222 | # CONFIG_DEBUG_STACK_USAGE is not set | ||
| 969 | # CONFIG_DEBUG_LL is not set | 1223 | # CONFIG_DEBUG_LL is not set |
| 970 | 1224 | ||
| 971 | # | 1225 | # |
| @@ -973,19 +1227,23 @@ CONFIG_DEBUG_USER=y | |||
| 973 | # | 1227 | # |
| 974 | # CONFIG_KEYS is not set | 1228 | # CONFIG_KEYS is not set |
| 975 | # CONFIG_SECURITY is not set | 1229 | # CONFIG_SECURITY is not set |
| 976 | 1230 | # CONFIG_SECURITYFS is not set | |
| 977 | # | 1231 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 978 | # Cryptographic options | ||
| 979 | # | ||
| 980 | # CONFIG_CRYPTO is not set | 1232 | # CONFIG_CRYPTO is not set |
| 981 | 1233 | ||
| 982 | # | 1234 | # |
| 983 | # Hardware crypto devices | ||
| 984 | # | ||
| 985 | |||
| 986 | # | ||
| 987 | # Library routines | 1235 | # Library routines |
| 988 | # | 1236 | # |
| 1237 | CONFIG_BITREVERSE=y | ||
| 1238 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 989 | # CONFIG_CRC_CCITT is not set | 1239 | # CONFIG_CRC_CCITT is not set |
| 1240 | # CONFIG_CRC16 is not set | ||
| 1241 | # CONFIG_CRC_T10DIF is not set | ||
| 1242 | # CONFIG_CRC_ITU_T is not set | ||
| 990 | CONFIG_CRC32=y | 1243 | CONFIG_CRC32=y |
| 1244 | # CONFIG_CRC7 is not set | ||
| 991 | # CONFIG_LIBCRC32C is not set | 1245 | # CONFIG_LIBCRC32C is not set |
| 1246 | CONFIG_PLIST=y | ||
| 1247 | CONFIG_HAS_IOMEM=y | ||
| 1248 | CONFIG_HAS_IOPORT=y | ||
| 1249 | CONFIG_HAS_DMA=y | ||
diff --git a/arch/arm/configs/simpad_defconfig b/arch/arm/configs/simpad_defconfig index 03f783e696b3..685d2b513206 100644 --- a/arch/arm/configs/simpad_defconfig +++ b/arch/arm/configs/simpad_defconfig | |||
| @@ -89,7 +89,6 @@ CONFIG_ARCH_SA1100=y | |||
| 89 | # CONFIG_SA1100_COLLIE is not set | 89 | # CONFIG_SA1100_COLLIE is not set |
| 90 | # CONFIG_SA1100_H3100 is not set | 90 | # CONFIG_SA1100_H3100 is not set |
| 91 | # CONFIG_SA1100_H3600 is not set | 91 | # CONFIG_SA1100_H3600 is not set |
| 92 | # CONFIG_SA1100_H3800 is not set | ||
| 93 | # CONFIG_SA1100_BADGE4 is not set | 92 | # CONFIG_SA1100_BADGE4 is not set |
| 94 | # CONFIG_SA1100_JORNADA720 is not set | 93 | # CONFIG_SA1100_JORNADA720 is not set |
| 95 | # CONFIG_SA1100_HACKKIT is not set | 94 | # CONFIG_SA1100_HACKKIT is not set |
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 6cbd8fdc9f1f..bfb0cb9aaa97 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h | |||
| @@ -94,6 +94,14 @@ | |||
| 94 | # endif | 94 | # endif |
| 95 | #endif | 95 | #endif |
| 96 | 96 | ||
| 97 | #if defined(CONFIG_CPU_MOHAWK) | ||
| 98 | # ifdef _CACHE | ||
| 99 | # define MULTI_CACHE 1 | ||
| 100 | # else | ||
| 101 | # define _CACHE mohawk | ||
| 102 | # endif | ||
| 103 | #endif | ||
| 104 | |||
| 97 | #if defined(CONFIG_CPU_FEROCEON) | 105 | #if defined(CONFIG_CPU_FEROCEON) |
| 98 | # define MULTI_CACHE 1 | 106 | # define MULTI_CACHE 1 |
| 99 | #endif | 107 | #endif |
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 22cb14ec3438..ff46dfa68a97 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h | |||
| @@ -15,10 +15,20 @@ | |||
| 15 | * must not be used by drivers. | 15 | * must not be used by drivers. |
| 16 | */ | 16 | */ |
| 17 | #ifndef __arch_page_to_dma | 17 | #ifndef __arch_page_to_dma |
| 18 | |||
| 19 | #if !defined(CONFIG_HIGHMEM) | ||
| 18 | static inline dma_addr_t page_to_dma(struct device *dev, struct page *page) | 20 | static inline dma_addr_t page_to_dma(struct device *dev, struct page *page) |
| 19 | { | 21 | { |
| 20 | return (dma_addr_t)__virt_to_bus((unsigned long)page_address(page)); | 22 | return (dma_addr_t)__virt_to_bus((unsigned long)page_address(page)); |
| 21 | } | 23 | } |
| 24 | #elif defined(__pfn_to_bus) | ||
| 25 | static inline dma_addr_t page_to_dma(struct device *dev, struct page *page) | ||
| 26 | { | ||
| 27 | return (dma_addr_t)__pfn_to_bus(page_to_pfn(page)); | ||
| 28 | } | ||
| 29 | #else | ||
| 30 | #error "this machine class needs to define __arch_page_to_dma to use HIGHMEM" | ||
| 31 | #endif | ||
| 22 | 32 | ||
| 23 | static inline void *dma_to_virt(struct device *dev, dma_addr_t addr) | 33 | static inline void *dma_to_virt(struct device *dev, dma_addr_t addr) |
| 24 | { | 34 | { |
| @@ -57,6 +67,8 @@ static inline dma_addr_t virt_to_dma(struct device *dev, void *addr) | |||
| 57 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | 67 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) |
| 58 | */ | 68 | */ |
| 59 | extern void dma_cache_maint(const void *kaddr, size_t size, int rw); | 69 | extern void dma_cache_maint(const void *kaddr, size_t size, int rw); |
| 70 | extern void dma_cache_maint_page(struct page *page, unsigned long offset, | ||
| 71 | size_t size, int rw); | ||
| 60 | 72 | ||
| 61 | /* | 73 | /* |
| 62 | * Return whether the given device DMA address mask can be supported | 74 | * Return whether the given device DMA address mask can be supported |
| @@ -316,7 +328,7 @@ static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, | |||
| 316 | BUG_ON(!valid_dma_direction(dir)); | 328 | BUG_ON(!valid_dma_direction(dir)); |
| 317 | 329 | ||
| 318 | if (!arch_is_coherent()) | 330 | if (!arch_is_coherent()) |
| 319 | dma_cache_maint(page_address(page) + offset, size, dir); | 331 | dma_cache_maint_page(page, offset, size, dir); |
| 320 | 332 | ||
| 321 | return page_to_dma(dev, page) + offset; | 333 | return page_to_dma(dev, page) + offset; |
| 322 | } | 334 | } |
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h index df5638f3643a..7edf3536df24 100644 --- a/arch/arm/include/asm/dma.h +++ b/arch/arm/include/asm/dma.h | |||
| @@ -19,21 +19,17 @@ | |||
| 19 | #include <asm/system.h> | 19 | #include <asm/system.h> |
| 20 | #include <asm/scatterlist.h> | 20 | #include <asm/scatterlist.h> |
| 21 | 21 | ||
| 22 | typedef unsigned int dmach_t; | ||
| 23 | |||
| 24 | #include <mach/isa-dma.h> | 22 | #include <mach/isa-dma.h> |
| 25 | 23 | ||
| 26 | /* | 24 | /* |
| 27 | * DMA modes | 25 | * The DMA modes reflect the settings for the ISA DMA controller |
| 28 | */ | 26 | */ |
| 29 | typedef unsigned int dmamode_t; | 27 | #define DMA_MODE_MASK 0xcc |
| 30 | |||
| 31 | #define DMA_MODE_MASK 3 | ||
| 32 | 28 | ||
| 33 | #define DMA_MODE_READ 0 | 29 | #define DMA_MODE_READ 0x44 |
| 34 | #define DMA_MODE_WRITE 1 | 30 | #define DMA_MODE_WRITE 0x48 |
| 35 | #define DMA_MODE_CASCADE 2 | 31 | #define DMA_MODE_CASCADE 0xc0 |
| 36 | #define DMA_AUTOINIT 4 | 32 | #define DMA_AUTOINIT 0x10 |
| 37 | 33 | ||
| 38 | extern spinlock_t dma_spin_lock; | 34 | extern spinlock_t dma_spin_lock; |
| 39 | 35 | ||
| @@ -52,44 +48,44 @@ static inline void release_dma_lock(unsigned long flags) | |||
| 52 | /* Clear the 'DMA Pointer Flip Flop'. | 48 | /* Clear the 'DMA Pointer Flip Flop'. |
| 53 | * Write 0 for LSB/MSB, 1 for MSB/LSB access. | 49 | * Write 0 for LSB/MSB, 1 for MSB/LSB access. |
| 54 | */ | 50 | */ |
| 55 | #define clear_dma_ff(channel) | 51 | #define clear_dma_ff(chan) |
| 56 | 52 | ||
| 57 | /* Set only the page register bits of the transfer address. | 53 | /* Set only the page register bits of the transfer address. |
| 58 | * | 54 | * |
| 59 | * NOTE: This is an architecture specific function, and should | 55 | * NOTE: This is an architecture specific function, and should |
| 60 | * be hidden from the drivers | 56 | * be hidden from the drivers |
| 61 | */ | 57 | */ |
| 62 | extern void set_dma_page(dmach_t channel, char pagenr); | 58 | extern void set_dma_page(unsigned int chan, char pagenr); |
| 63 | 59 | ||
| 64 | /* Request a DMA channel | 60 | /* Request a DMA channel |
| 65 | * | 61 | * |
| 66 | * Some architectures may need to do allocate an interrupt | 62 | * Some architectures may need to do allocate an interrupt |
| 67 | */ | 63 | */ |
| 68 | extern int request_dma(dmach_t channel, const char * device_id); | 64 | extern int request_dma(unsigned int chan, const char * device_id); |
| 69 | 65 | ||
| 70 | /* Free a DMA channel | 66 | /* Free a DMA channel |
| 71 | * | 67 | * |
| 72 | * Some architectures may need to do free an interrupt | 68 | * Some architectures may need to do free an interrupt |
| 73 | */ | 69 | */ |
| 74 | extern void free_dma(dmach_t channel); | 70 | extern void free_dma(unsigned int chan); |
| 75 | 71 | ||
| 76 | /* Enable DMA for this channel | 72 | /* Enable DMA for this channel |
| 77 | * | 73 | * |
| 78 | * On some architectures, this may have other side effects like | 74 | * On some architectures, this may have other side effects like |
| 79 | * enabling an interrupt and setting the DMA registers. | 75 | * enabling an interrupt and setting the DMA registers. |
| 80 | */ | 76 | */ |
| 81 | extern void enable_dma(dmach_t channel); | 77 | extern void enable_dma(unsigned int chan); |
| 82 | 78 | ||
| 83 | /* Disable DMA for this channel | 79 | /* Disable DMA for this channel |
| 84 | * | 80 | * |
| 85 | * On some architectures, this may have other side effects like | 81 | * On some architectures, this may have other side effects like |
| 86 | * disabling an interrupt or whatever. | 82 | * disabling an interrupt or whatever. |
| 87 | */ | 83 | */ |
| 88 | extern void disable_dma(dmach_t channel); | 84 | extern void disable_dma(unsigned int chan); |
| 89 | 85 | ||
| 90 | /* Test whether the specified channel has an active DMA transfer | 86 | /* Test whether the specified channel has an active DMA transfer |
| 91 | */ | 87 | */ |
| 92 | extern int dma_channel_active(dmach_t channel); | 88 | extern int dma_channel_active(unsigned int chan); |
| 93 | 89 | ||
| 94 | /* Set the DMA scatter gather list for this channel | 90 | /* Set the DMA scatter gather list for this channel |
| 95 | * | 91 | * |
| @@ -97,7 +93,7 @@ extern int dma_channel_active(dmach_t channel); | |||
| 97 | * especially since some DMA architectures don't update the | 93 | * especially since some DMA architectures don't update the |
| 98 | * DMA address immediately, but defer it to the enable_dma(). | 94 | * DMA address immediately, but defer it to the enable_dma(). |
| 99 | */ | 95 | */ |
| 100 | extern void set_dma_sg(dmach_t channel, struct scatterlist *sg, int nr_sg); | 96 | extern void set_dma_sg(unsigned int chan, struct scatterlist *sg, int nr_sg); |
| 101 | 97 | ||
| 102 | /* Set the DMA address for this channel | 98 | /* Set the DMA address for this channel |
| 103 | * | 99 | * |
| @@ -105,9 +101,9 @@ extern void set_dma_sg(dmach_t channel, struct scatterlist *sg, int nr_sg); | |||
| 105 | * especially since some DMA architectures don't update the | 101 | * especially since some DMA architectures don't update the |
| 106 | * DMA address immediately, but defer it to the enable_dma(). | 102 | * DMA address immediately, but defer it to the enable_dma(). |
| 107 | */ | 103 | */ |
| 108 | extern void __set_dma_addr(dmach_t channel, void *addr); | 104 | extern void __set_dma_addr(unsigned int chan, void *addr); |
| 109 | #define set_dma_addr(channel, addr) \ | 105 | #define set_dma_addr(chan, addr) \ |
| 110 | __set_dma_addr(channel, bus_to_virt(addr)) | 106 | __set_dma_addr(chan, bus_to_virt(addr)) |
| 111 | 107 | ||
| 112 | /* Set the DMA byte count for this channel | 108 | /* Set the DMA byte count for this channel |
| 113 | * | 109 | * |
| @@ -115,7 +111,7 @@ extern void __set_dma_addr(dmach_t channel, void *addr); | |||
| 115 | * especially since some DMA architectures don't update the | 111 | * especially since some DMA architectures don't update the |
| 116 | * DMA count immediately, but defer it to the enable_dma(). | 112 | * DMA count immediately, but defer it to the enable_dma(). |
| 117 | */ | 113 | */ |
| 118 | extern void set_dma_count(dmach_t channel, unsigned long count); | 114 | extern void set_dma_count(unsigned int chan, unsigned long count); |
| 119 | 115 | ||
| 120 | /* Set the transfer direction for this channel | 116 | /* Set the transfer direction for this channel |
| 121 | * | 117 | * |
| @@ -124,11 +120,11 @@ extern void set_dma_count(dmach_t channel, unsigned long count); | |||
| 124 | * DMA transfer direction immediately, but defer it to the | 120 | * DMA transfer direction immediately, but defer it to the |
| 125 | * enable_dma(). | 121 | * enable_dma(). |
| 126 | */ | 122 | */ |
| 127 | extern void set_dma_mode(dmach_t channel, dmamode_t mode); | 123 | extern void set_dma_mode(unsigned int chan, unsigned int mode); |
| 128 | 124 | ||
| 129 | /* Set the transfer speed for this channel | 125 | /* Set the transfer speed for this channel |
| 130 | */ | 126 | */ |
| 131 | extern void set_dma_speed(dmach_t channel, int cycle_ns); | 127 | extern void set_dma_speed(unsigned int chan, int cycle_ns); |
| 132 | 128 | ||
| 133 | /* Get DMA residue count. After a DMA transfer, this | 129 | /* Get DMA residue count. After a DMA transfer, this |
| 134 | * should return zero. Reading this while a DMA transfer is | 130 | * should return zero. Reading this while a DMA transfer is |
| @@ -136,7 +132,7 @@ extern void set_dma_speed(dmach_t channel, int cycle_ns); | |||
| 136 | * If called before the channel has been used, it may return 1. | 132 | * If called before the channel has been used, it may return 1. |
| 137 | * Otherwise, it returns the number of _bytes_ left to transfer. | 133 | * Otherwise, it returns the number of _bytes_ left to transfer. |
| 138 | */ | 134 | */ |
| 139 | extern int get_dma_residue(dmach_t channel); | 135 | extern int get_dma_residue(unsigned int chan); |
| 140 | 136 | ||
| 141 | #ifndef NO_DMA | 137 | #ifndef NO_DMA |
| 142 | #define NO_DMA 255 | 138 | #define NO_DMA 255 |
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h index a58378c343b9..def8eac6e89d 100644 --- a/arch/arm/include/asm/elf.h +++ b/arch/arm/include/asm/elf.h | |||
| @@ -50,6 +50,7 @@ typedef struct user_fp elf_fpregset_t; | |||
| 50 | #define R_ARM_ABS32 2 | 50 | #define R_ARM_ABS32 2 |
| 51 | #define R_ARM_CALL 28 | 51 | #define R_ARM_CALL 28 |
| 52 | #define R_ARM_JUMP24 29 | 52 | #define R_ARM_JUMP24 29 |
| 53 | #define R_ARM_PREL31 42 | ||
| 53 | 54 | ||
| 54 | /* | 55 | /* |
| 55 | * These are used to set parameters in the core dumps. | 56 | * These are used to set parameters in the core dumps. |
diff --git a/arch/arm/include/asm/fixmap.h b/arch/arm/include/asm/fixmap.h new file mode 100644 index 000000000000..bbae919bceb4 --- /dev/null +++ b/arch/arm/include/asm/fixmap.h | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | #ifndef _ASM_FIXMAP_H | ||
| 2 | #define _ASM_FIXMAP_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Nothing too fancy for now. | ||
| 6 | * | ||
| 7 | * On ARM we already have well known fixed virtual addresses imposed by | ||
| 8 | * the architecture such as the vector page which is located at 0xffff0000, | ||
| 9 | * therefore a second level page table is already allocated covering | ||
| 10 | * 0xfff00000 upwards. | ||
| 11 | * | ||
| 12 | * The cache flushing code in proc-xscale.S uses the virtual area between | ||
| 13 | * 0xfffe0000 and 0xfffeffff. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #define FIXADDR_START 0xfff00000UL | ||
| 17 | #define FIXADDR_TOP 0xfffe0000UL | ||
| 18 | #define FIXADDR_SIZE (FIXADDR_TOP - FIXADDR_START) | ||
| 19 | |||
| 20 | #define FIX_KMAP_BEGIN 0 | ||
| 21 | #define FIX_KMAP_END (FIXADDR_SIZE >> PAGE_SHIFT) | ||
| 22 | |||
| 23 | #define __fix_to_virt(x) (FIXADDR_START + ((x) << PAGE_SHIFT)) | ||
| 24 | #define __virt_to_fix(x) (((x) - FIXADDR_START) >> PAGE_SHIFT) | ||
| 25 | |||
| 26 | extern void __this_fixmap_does_not_exist(void); | ||
| 27 | |||
| 28 | static inline unsigned long fix_to_virt(const unsigned int idx) | ||
| 29 | { | ||
| 30 | if (idx >= FIX_KMAP_END) | ||
| 31 | __this_fixmap_does_not_exist(); | ||
| 32 | return __fix_to_virt(idx); | ||
| 33 | } | ||
| 34 | |||
| 35 | static inline unsigned int virt_to_fix(const unsigned long vaddr) | ||
| 36 | { | ||
| 37 | BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START); | ||
| 38 | return __virt_to_fix(vaddr); | ||
| 39 | } | ||
| 40 | |||
| 41 | #endif | ||
diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h index dfb8330599f9..46492a63a7c4 100644 --- a/arch/arm/include/asm/hardware/scoop.h +++ b/arch/arm/include/asm/hardware/scoop.h | |||
| @@ -63,7 +63,5 @@ struct scoop_pcmcia_config { | |||
| 63 | extern struct scoop_pcmcia_config *platform_scoop_config; | 63 | extern struct scoop_pcmcia_config *platform_scoop_config; |
| 64 | 64 | ||
| 65 | void reset_scoop(struct device *dev); | 65 | void reset_scoop(struct device *dev); |
| 66 | unsigned short __deprecated set_scoop_gpio(struct device *dev, unsigned short bit); | ||
| 67 | unsigned short __deprecated reset_scoop_gpio(struct device *dev, unsigned short bit); | ||
| 68 | unsigned short read_scoop_reg(struct device *dev, unsigned short reg); | 66 | unsigned short read_scoop_reg(struct device *dev, unsigned short reg); |
| 69 | void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data); | 67 | void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data); |
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h new file mode 100644 index 000000000000..7f36d00600b4 --- /dev/null +++ b/arch/arm/include/asm/highmem.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | #ifndef _ASM_HIGHMEM_H | ||
| 2 | #define _ASM_HIGHMEM_H | ||
| 3 | |||
| 4 | #include <asm/kmap_types.h> | ||
| 5 | |||
| 6 | #define PKMAP_BASE (PAGE_OFFSET - PMD_SIZE) | ||
| 7 | #define LAST_PKMAP PTRS_PER_PTE | ||
| 8 | #define LAST_PKMAP_MASK (LAST_PKMAP - 1) | ||
| 9 | #define PKMAP_NR(virt) (((virt) - PKMAP_BASE) >> PAGE_SHIFT) | ||
| 10 | #define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) | ||
| 11 | |||
| 12 | #define kmap_prot PAGE_KERNEL | ||
| 13 | |||
| 14 | #define flush_cache_kmaps() flush_cache_all() | ||
| 15 | |||
| 16 | extern pte_t *pkmap_page_table; | ||
| 17 | |||
| 18 | #define ARCH_NEEDS_KMAP_HIGH_GET | ||
| 19 | |||
| 20 | extern void *kmap_high(struct page *page); | ||
| 21 | extern void *kmap_high_get(struct page *page); | ||
| 22 | extern void kunmap_high(struct page *page); | ||
| 23 | |||
| 24 | extern void *kmap(struct page *page); | ||
| 25 | extern void kunmap(struct page *page); | ||
| 26 | extern void *kmap_atomic(struct page *page, enum km_type type); | ||
| 27 | extern void kunmap_atomic(void *kvaddr, enum km_type type); | ||
| 28 | extern void *kmap_atomic_pfn(unsigned long pfn, enum km_type type); | ||
| 29 | extern struct page *kmap_atomic_to_page(const void *ptr); | ||
| 30 | |||
| 31 | #endif | ||
diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h index bda489f9f017..f7bd52b1c365 100644 --- a/arch/arm/include/asm/hwcap.h +++ b/arch/arm/include/asm/hwcap.h | |||
| @@ -17,6 +17,8 @@ | |||
| 17 | #define HWCAP_CRUNCH 1024 | 17 | #define HWCAP_CRUNCH 1024 |
| 18 | #define HWCAP_THUMBEE 2048 | 18 | #define HWCAP_THUMBEE 2048 |
| 19 | #define HWCAP_NEON 4096 | 19 | #define HWCAP_NEON 4096 |
| 20 | #define HWCAP_VFPv3 8192 | ||
| 21 | #define HWCAP_VFPv3D16 16384 | ||
| 20 | 22 | ||
| 21 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) | 23 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
| 22 | /* | 24 | /* |
diff --git a/arch/arm/include/asm/kmap_types.h b/arch/arm/include/asm/kmap_types.h index 45def13ee17a..d16ec97ec9a9 100644 --- a/arch/arm/include/asm/kmap_types.h +++ b/arch/arm/include/asm/kmap_types.h | |||
| @@ -18,6 +18,7 @@ enum km_type { | |||
| 18 | KM_IRQ1, | 18 | KM_IRQ1, |
| 19 | KM_SOFTIRQ0, | 19 | KM_SOFTIRQ0, |
| 20 | KM_SOFTIRQ1, | 20 | KM_SOFTIRQ1, |
| 21 | KM_L2_CACHE, | ||
| 21 | KM_TYPE_NR | 22 | KM_TYPE_NR |
| 22 | }; | 23 | }; |
| 23 | 24 | ||
diff --git a/arch/arm/include/asm/mach/dma.h b/arch/arm/include/asm/mach/dma.h index fc7278ea7146..9e614a18e680 100644 --- a/arch/arm/include/asm/mach/dma.h +++ b/arch/arm/include/asm/mach/dma.h | |||
| @@ -15,13 +15,13 @@ struct dma_struct; | |||
| 15 | typedef struct dma_struct dma_t; | 15 | typedef struct dma_struct dma_t; |
| 16 | 16 | ||
| 17 | struct dma_ops { | 17 | struct dma_ops { |
| 18 | int (*request)(dmach_t, dma_t *); /* optional */ | 18 | int (*request)(unsigned int, dma_t *); /* optional */ |
| 19 | void (*free)(dmach_t, dma_t *); /* optional */ | 19 | void (*free)(unsigned int, dma_t *); /* optional */ |
| 20 | void (*enable)(dmach_t, dma_t *); /* mandatory */ | 20 | void (*enable)(unsigned int, dma_t *); /* mandatory */ |
| 21 | void (*disable)(dmach_t, dma_t *); /* mandatory */ | 21 | void (*disable)(unsigned int, dma_t *); /* mandatory */ |
| 22 | int (*residue)(dmach_t, dma_t *); /* optional */ | 22 | int (*residue)(unsigned int, dma_t *); /* optional */ |
| 23 | int (*setspeed)(dmach_t, dma_t *, int); /* optional */ | 23 | int (*setspeed)(unsigned int, dma_t *, int); /* optional */ |
| 24 | char *type; | 24 | const char *type; |
| 25 | }; | 25 | }; |
| 26 | 26 | ||
| 27 | struct dma_struct { | 27 | struct dma_struct { |
| @@ -34,24 +34,21 @@ struct dma_struct { | |||
| 34 | unsigned int active:1; /* Transfer active */ | 34 | unsigned int active:1; /* Transfer active */ |
| 35 | unsigned int invalid:1; /* Address/Count changed */ | 35 | unsigned int invalid:1; /* Address/Count changed */ |
| 36 | 36 | ||
| 37 | dmamode_t dma_mode; /* DMA mode */ | 37 | unsigned int dma_mode; /* DMA mode */ |
| 38 | int speed; /* DMA speed */ | 38 | int speed; /* DMA speed */ |
| 39 | 39 | ||
| 40 | unsigned int lock; /* Device is allocated */ | 40 | unsigned int lock; /* Device is allocated */ |
| 41 | const char *device_id; /* Device name */ | 41 | const char *device_id; /* Device name */ |
| 42 | 42 | ||
| 43 | unsigned int dma_base; /* Controller base address */ | 43 | const struct dma_ops *d_ops; |
| 44 | int dma_irq; /* Controller IRQ */ | ||
| 45 | struct scatterlist cur_sg; /* Current controller buffer */ | ||
| 46 | unsigned int state; | ||
| 47 | |||
| 48 | struct dma_ops *d_ops; | ||
| 49 | }; | 44 | }; |
| 50 | 45 | ||
| 51 | /* Prototype: void arch_dma_init(dma) | 46 | /* |
| 52 | * Purpose : Initialise architecture specific DMA | 47 | * isa_dma_add - add an ISA-style DMA channel |
| 53 | * Params : dma - pointer to array of DMA structures | ||
| 54 | */ | 48 | */ |
| 55 | extern void arch_dma_init(dma_t *dma); | 49 | extern int isa_dma_add(unsigned int, dma_t *dma); |
| 56 | 50 | ||
| 57 | extern void isa_init_dma(dma_t *dma); | 51 | /* |
| 52 | * Add the ISA DMA controller. Always takes channels 0-7. | ||
| 53 | */ | ||
| 54 | extern void isa_init_dma(void); | ||
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h index 39d949b63e80..58cf91f38e6f 100644 --- a/arch/arm/include/asm/mach/map.h +++ b/arch/arm/include/asm/mach/map.h | |||
| @@ -26,6 +26,7 @@ struct map_desc { | |||
| 26 | #define MT_HIGH_VECTORS 8 | 26 | #define MT_HIGH_VECTORS 8 |
| 27 | #define MT_MEMORY 9 | 27 | #define MT_MEMORY 9 |
| 28 | #define MT_ROM 10 | 28 | #define MT_ROM 10 |
| 29 | #define MT_MEMORY_NONCACHED 11 | ||
| 29 | 30 | ||
| 30 | #ifdef CONFIG_MMU | 31 | #ifdef CONFIG_MMU |
| 31 | extern void iotable_init(struct map_desc *, int); | 32 | extern void iotable_init(struct map_desc *, int); |
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index 0202a7c20e62..85763db87449 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h | |||
| @@ -44,14 +44,21 @@ | |||
| 44 | * The module space lives between the addresses given by TASK_SIZE | 44 | * The module space lives between the addresses given by TASK_SIZE |
| 45 | * and PAGE_OFFSET - it must be within 32MB of the kernel text. | 45 | * and PAGE_OFFSET - it must be within 32MB of the kernel text. |
| 46 | */ | 46 | */ |
| 47 | #define MODULES_END (PAGE_OFFSET) | 47 | #define MODULES_VADDR (PAGE_OFFSET - 16*1024*1024) |
| 48 | #define MODULES_VADDR (MODULES_END - 16*1048576) | ||
| 49 | |||
| 50 | #if TASK_SIZE > MODULES_VADDR | 48 | #if TASK_SIZE > MODULES_VADDR |
| 51 | #error Top of user space clashes with start of module space | 49 | #error Top of user space clashes with start of module space |
| 52 | #endif | 50 | #endif |
| 53 | 51 | ||
| 54 | /* | 52 | /* |
| 53 | * The highmem pkmap virtual space shares the end of the module area. | ||
| 54 | */ | ||
| 55 | #ifdef CONFIG_HIGHMEM | ||
| 56 | #define MODULES_END (PAGE_OFFSET - PMD_SIZE) | ||
| 57 | #else | ||
| 58 | #define MODULES_END (PAGE_OFFSET) | ||
| 59 | #endif | ||
| 60 | |||
| 61 | /* | ||
| 55 | * The XIP kernel gets mapped at the bottom of the module vm area. | 62 | * The XIP kernel gets mapped at the bottom of the module vm area. |
| 56 | * Since we use sections to map it, this macro replaces the physical address | 63 | * Since we use sections to map it, this macro replaces the physical address |
| 57 | * with its virtual address while keeping offset from the base section. | 64 | * with its virtual address while keeping offset from the base section. |
| @@ -181,6 +188,7 @@ static inline void *phys_to_virt(unsigned long x) | |||
| 181 | #ifndef __virt_to_bus | 188 | #ifndef __virt_to_bus |
| 182 | #define __virt_to_bus __virt_to_phys | 189 | #define __virt_to_bus __virt_to_phys |
| 183 | #define __bus_to_virt __phys_to_virt | 190 | #define __bus_to_virt __phys_to_virt |
| 191 | #define __pfn_to_bus(x) ((x) << PAGE_SHIFT) | ||
| 184 | #endif | 192 | #endif |
| 185 | 193 | ||
| 186 | static inline __deprecated unsigned long virt_to_bus(void *x) | 194 | static inline __deprecated unsigned long virt_to_bus(void *x) |
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h index 24b168dc31a3..e4dfa69abb68 100644 --- a/arch/arm/include/asm/module.h +++ b/arch/arm/include/asm/module.h | |||
| @@ -1,15 +1,27 @@ | |||
| 1 | #ifndef _ASM_ARM_MODULE_H | 1 | #ifndef _ASM_ARM_MODULE_H |
| 2 | #define _ASM_ARM_MODULE_H | 2 | #define _ASM_ARM_MODULE_H |
| 3 | 3 | ||
| 4 | struct mod_arch_specific | ||
| 5 | { | ||
| 6 | int foo; | ||
| 7 | }; | ||
| 8 | |||
| 9 | #define Elf_Shdr Elf32_Shdr | 4 | #define Elf_Shdr Elf32_Shdr |
| 10 | #define Elf_Sym Elf32_Sym | 5 | #define Elf_Sym Elf32_Sym |
| 11 | #define Elf_Ehdr Elf32_Ehdr | 6 | #define Elf_Ehdr Elf32_Ehdr |
| 12 | 7 | ||
| 8 | struct unwind_table; | ||
| 9 | |||
| 10 | struct mod_arch_specific | ||
| 11 | { | ||
| 12 | #ifdef CONFIG_ARM_UNWIND | ||
| 13 | Elf_Shdr *unw_sec_init; | ||
| 14 | Elf_Shdr *unw_sec_devinit; | ||
| 15 | Elf_Shdr *unw_sec_core; | ||
| 16 | Elf_Shdr *sec_init_text; | ||
| 17 | Elf_Shdr *sec_devinit_text; | ||
| 18 | Elf_Shdr *sec_core_text; | ||
| 19 | struct unwind_table *unwind_init; | ||
| 20 | struct unwind_table *unwind_devinit; | ||
| 21 | struct unwind_table *unwind_core; | ||
| 22 | #endif | ||
| 23 | }; | ||
| 24 | |||
| 13 | /* | 25 | /* |
| 14 | * Include the ARM architecture version. | 26 | * Include the ARM architecture version. |
| 15 | */ | 27 | */ |
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h index db80203b68e0..c6250311550b 100644 --- a/arch/arm/include/asm/proc-fns.h +++ b/arch/arm/include/asm/proc-fns.h | |||
| @@ -185,6 +185,14 @@ | |||
| 185 | # define CPU_NAME cpu_xsc3 | 185 | # define CPU_NAME cpu_xsc3 |
| 186 | # endif | 186 | # endif |
| 187 | # endif | 187 | # endif |
| 188 | # ifdef CONFIG_CPU_MOHAWK | ||
| 189 | # ifdef CPU_NAME | ||
| 190 | # undef MULTI_CPU | ||
| 191 | # define MULTI_CPU | ||
| 192 | # else | ||
| 193 | # define CPU_NAME cpu_mohawk | ||
| 194 | # endif | ||
| 195 | # endif | ||
| 188 | # ifdef CONFIG_CPU_FEROCEON | 196 | # ifdef CONFIG_CPU_FEROCEON |
| 189 | # ifdef CPU_NAME | 197 | # ifdef CPU_NAME |
| 190 | # undef MULTI_CPU | 198 | # undef MULTI_CPU |
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h index 73192618f1c2..236a06b9b7ce 100644 --- a/arch/arm/include/asm/ptrace.h +++ b/arch/arm/include/asm/ptrace.h | |||
| @@ -27,6 +27,8 @@ | |||
| 27 | /* PTRACE_SYSCALL is 24 */ | 27 | /* PTRACE_SYSCALL is 24 */ |
| 28 | #define PTRACE_GETCRUNCHREGS 25 | 28 | #define PTRACE_GETCRUNCHREGS 25 |
| 29 | #define PTRACE_SETCRUNCHREGS 26 | 29 | #define PTRACE_SETCRUNCHREGS 26 |
| 30 | #define PTRACE_GETVFPREGS 27 | ||
| 31 | #define PTRACE_SETVFPREGS 28 | ||
| 30 | 32 | ||
| 31 | /* | 33 | /* |
| 32 | * PSR bits | 34 | * PSR bits |
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h index 503843db1565..c10d1aa4b487 100644 --- a/arch/arm/include/asm/sizes.h +++ b/arch/arm/include/asm/sizes.h | |||
| @@ -43,6 +43,7 @@ | |||
| 43 | #define SZ_8M 0x00800000 | 43 | #define SZ_8M 0x00800000 |
| 44 | #define SZ_16M 0x01000000 | 44 | #define SZ_16M 0x01000000 |
| 45 | #define SZ_32M 0x02000000 | 45 | #define SZ_32M 0x02000000 |
| 46 | #define SZ_48M 0x03000000 | ||
| 46 | #define SZ_64M 0x04000000 | 47 | #define SZ_64M 0x04000000 |
| 47 | #define SZ_128M 0x08000000 | 48 | #define SZ_128M 0x08000000 |
| 48 | #define SZ_256M 0x10000000 | 49 | #define SZ_256M 0x10000000 |
diff --git a/arch/arm/include/asm/stacktrace.h b/arch/arm/include/asm/stacktrace.h new file mode 100644 index 000000000000..4d0a16441b29 --- /dev/null +++ b/arch/arm/include/asm/stacktrace.h | |||
| @@ -0,0 +1,15 @@ | |||
| 1 | #ifndef __ASM_STACKTRACE_H | ||
| 2 | #define __ASM_STACKTRACE_H | ||
| 3 | |||
| 4 | struct stackframe { | ||
| 5 | unsigned long fp; | ||
| 6 | unsigned long sp; | ||
| 7 | unsigned long lr; | ||
| 8 | unsigned long pc; | ||
| 9 | }; | ||
| 10 | |||
| 11 | extern int unwind_frame(struct stackframe *frame); | ||
| 12 | extern void walk_stackframe(struct stackframe *frame, | ||
| 13 | int (*fn)(struct stackframe *, void *), void *data); | ||
| 14 | |||
| 15 | #endif /* __ASM_STACKTRACE_H */ | ||
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 811be55f338e..0a0d49ae1e6d 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h | |||
| @@ -97,8 +97,8 @@ extern void __show_regs(struct pt_regs *); | |||
| 97 | extern int cpu_architecture(void); | 97 | extern int cpu_architecture(void); |
| 98 | extern void cpu_init(void); | 98 | extern void cpu_init(void); |
| 99 | 99 | ||
| 100 | void arm_machine_restart(char mode); | 100 | void arm_machine_restart(char mode, const char *cmd); |
| 101 | extern void (*arm_pm_restart)(char str); | 101 | extern void (*arm_pm_restart)(char str, const char *cmd); |
| 102 | 102 | ||
| 103 | #define UDBG_UNDEFINED (1 << 0) | 103 | #define UDBG_UNDEFINED (1 << 0) |
| 104 | #define UDBG_SYSCALL (1 << 1) | 104 | #define UDBG_SYSCALL (1 << 1) |
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index 68b9ec82a37f..4f8848260ee2 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h | |||
| @@ -99,6 +99,8 @@ static inline struct thread_info *current_thread_info(void) | |||
| 99 | 99 | ||
| 100 | #define thread_saved_pc(tsk) \ | 100 | #define thread_saved_pc(tsk) \ |
| 101 | ((unsigned long)(task_thread_info(tsk)->cpu_context.pc)) | 101 | ((unsigned long)(task_thread_info(tsk)->cpu_context.pc)) |
| 102 | #define thread_saved_sp(tsk) \ | ||
| 103 | ((unsigned long)(task_thread_info(tsk)->cpu_context.sp)) | ||
| 102 | #define thread_saved_fp(tsk) \ | 104 | #define thread_saved_fp(tsk) \ |
| 103 | ((unsigned long)(task_thread_info(tsk)->cpu_context.fp)) | 105 | ((unsigned long)(task_thread_info(tsk)->cpu_context.fp)) |
| 104 | 106 | ||
| @@ -113,6 +115,8 @@ extern void iwmmxt_task_restore(struct thread_info *, void *); | |||
| 113 | extern void iwmmxt_task_release(struct thread_info *); | 115 | extern void iwmmxt_task_release(struct thread_info *); |
| 114 | extern void iwmmxt_task_switch(struct thread_info *); | 116 | extern void iwmmxt_task_switch(struct thread_info *); |
| 115 | 117 | ||
| 118 | extern void vfp_sync_state(struct thread_info *thread); | ||
| 119 | |||
| 116 | #endif | 120 | #endif |
| 117 | 121 | ||
| 118 | /* | 122 | /* |
diff --git a/arch/arm/include/asm/traps.h b/arch/arm/include/asm/traps.h index aa399aec568e..491960bf4260 100644 --- a/arch/arm/include/asm/traps.h +++ b/arch/arm/include/asm/traps.h | |||
| @@ -25,5 +25,6 @@ static inline int in_exception_text(unsigned long ptr) | |||
| 25 | } | 25 | } |
| 26 | 26 | ||
| 27 | extern void __init early_trap_init(void); | 27 | extern void __init early_trap_init(void); |
| 28 | extern void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame); | ||
| 28 | 29 | ||
| 29 | #endif | 30 | #endif |
diff --git a/arch/arm/include/asm/unwind.h b/arch/arm/include/asm/unwind.h new file mode 100644 index 000000000000..a5edf421005c --- /dev/null +++ b/arch/arm/include/asm/unwind.h | |||
| @@ -0,0 +1,69 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/include/asm/unwind.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef __ASM_UNWIND_H | ||
| 21 | #define __ASM_UNWIND_H | ||
| 22 | |||
| 23 | #ifndef __ASSEMBLY__ | ||
| 24 | |||
| 25 | /* Unwind reason code according the the ARM EABI documents */ | ||
| 26 | enum unwind_reason_code { | ||
| 27 | URC_OK = 0, /* operation completed successfully */ | ||
| 28 | URC_CONTINUE_UNWIND = 8, | ||
| 29 | URC_FAILURE = 9 /* unspecified failure of some kind */ | ||
| 30 | }; | ||
| 31 | |||
| 32 | struct unwind_idx { | ||
| 33 | unsigned long addr; | ||
| 34 | unsigned long insn; | ||
| 35 | }; | ||
| 36 | |||
| 37 | struct unwind_table { | ||
| 38 | struct list_head list; | ||
| 39 | struct unwind_idx *start; | ||
| 40 | struct unwind_idx *stop; | ||
| 41 | unsigned long begin_addr; | ||
| 42 | unsigned long end_addr; | ||
| 43 | }; | ||
| 44 | |||
| 45 | extern struct unwind_table *unwind_table_add(unsigned long start, | ||
| 46 | unsigned long size, | ||
| 47 | unsigned long text_addr, | ||
| 48 | unsigned long text_size); | ||
| 49 | extern void unwind_table_del(struct unwind_table *tab); | ||
| 50 | extern void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk); | ||
| 51 | |||
| 52 | #ifdef CONFIG_ARM_UNWIND | ||
| 53 | extern int __init unwind_init(void); | ||
| 54 | #else | ||
| 55 | static inline int __init unwind_init(void) | ||
| 56 | { | ||
| 57 | return 0; | ||
| 58 | } | ||
| 59 | #endif | ||
| 60 | |||
| 61 | #endif /* !__ASSEMBLY__ */ | ||
| 62 | |||
| 63 | #ifdef CONFIG_ARM_UNWIND | ||
| 64 | #define UNWIND(code...) code | ||
| 65 | #else | ||
| 66 | #define UNWIND(code...) | ||
| 67 | #endif | ||
| 68 | |||
| 69 | #endif /* __ASM_UNWIND_H */ | ||
diff --git a/arch/arm/include/asm/user.h b/arch/arm/include/asm/user.h index 825c1e7c582d..df95e050f9dd 100644 --- a/arch/arm/include/asm/user.h +++ b/arch/arm/include/asm/user.h | |||
| @@ -81,4 +81,13 @@ struct user{ | |||
| 81 | #define HOST_TEXT_START_ADDR (u.start_code) | 81 | #define HOST_TEXT_START_ADDR (u.start_code) |
| 82 | #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) | 82 | #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) |
| 83 | 83 | ||
| 84 | /* | ||
| 85 | * User specific VFP registers. If only VFPv2 is present, registers 16 to 31 | ||
| 86 | * are ignored by the ptrace system call. | ||
| 87 | */ | ||
| 88 | struct user_vfp { | ||
| 89 | unsigned long long fpregs[32]; | ||
| 90 | unsigned long fpscr; | ||
| 91 | }; | ||
| 92 | |||
| 84 | #endif /* _ARM_USER_H */ | 93 | #endif /* _ARM_USER_H */ |
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 4305345987d3..11a5197a221f 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile | |||
| @@ -29,12 +29,14 @@ obj-$(CONFIG_ATAGS_PROC) += atags.o | |||
| 29 | obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o | 29 | obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o |
| 30 | obj-$(CONFIG_ARM_THUMBEE) += thumbee.o | 30 | obj-$(CONFIG_ARM_THUMBEE) += thumbee.o |
| 31 | obj-$(CONFIG_KGDB) += kgdb.o | 31 | obj-$(CONFIG_KGDB) += kgdb.o |
| 32 | obj-$(CONFIG_ARM_UNWIND) += unwind.o | ||
| 32 | 33 | ||
| 33 | obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o | 34 | obj-$(CONFIG_CRUNCH) += crunch.o crunch-bits.o |
| 34 | AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 | 35 | AFLAGS_crunch-bits.o := -Wa,-mcpu=ep9312 |
| 35 | 36 | ||
| 36 | obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o | 37 | obj-$(CONFIG_CPU_XSCALE) += xscale-cp0.o |
| 37 | obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o | 38 | obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o |
| 39 | obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o | ||
| 38 | obj-$(CONFIG_IWMMXT) += iwmmxt.o | 40 | obj-$(CONFIG_IWMMXT) += iwmmxt.o |
| 39 | AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt | 41 | AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt |
| 40 | 42 | ||
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S index f53c58290543..b121b6053cce 100644 --- a/arch/arm/kernel/debug.S +++ b/arch/arm/kernel/debug.S | |||
| @@ -49,6 +49,33 @@ | |||
| 49 | 1002: | 49 | 1002: |
| 50 | .endm | 50 | .endm |
| 51 | 51 | ||
| 52 | #elif defined(CONFIG_CPU_XSCALE) | ||
| 53 | |||
| 54 | .macro addruart, rx | ||
| 55 | .endm | ||
| 56 | |||
| 57 | .macro senduart, rd, rx | ||
| 58 | mcr p14, 0, \rd, c8, c0, 0 | ||
| 59 | .endm | ||
| 60 | |||
| 61 | .macro busyuart, rd, rx | ||
| 62 | 1001: | ||
| 63 | mrc p14, 0, \rx, c14, c0, 0 | ||
| 64 | tst \rx, #0x10000000 | ||
| 65 | beq 1001b | ||
| 66 | .endm | ||
| 67 | |||
| 68 | .macro waituart, rd, rx | ||
| 69 | mov \rd, #0x10000000 | ||
| 70 | 1001: | ||
| 71 | subs \rd, \rd, #1 | ||
| 72 | bmi 1002f | ||
| 73 | mrc p14, 0, \rx, c14, c0, 0 | ||
| 74 | tst \rx, #0x10000000 | ||
| 75 | bne 1001b | ||
| 76 | 1002: | ||
| 77 | .endm | ||
| 78 | |||
| 52 | #else | 79 | #else |
| 53 | 80 | ||
| 54 | .macro addruart, rx | 81 | .macro addruart, rx |
diff --git a/arch/arm/kernel/dma-isa.c b/arch/arm/kernel/dma-isa.c index 4a3a50495c60..0e88e46fc732 100644 --- a/arch/arm/kernel/dma-isa.c +++ b/arch/arm/kernel/dma-isa.c | |||
| @@ -24,11 +24,6 @@ | |||
| 24 | #include <asm/dma.h> | 24 | #include <asm/dma.h> |
| 25 | #include <asm/mach/dma.h> | 25 | #include <asm/mach/dma.h> |
| 26 | 26 | ||
| 27 | #define ISA_DMA_MODE_READ 0x44 | ||
| 28 | #define ISA_DMA_MODE_WRITE 0x48 | ||
| 29 | #define ISA_DMA_MODE_CASCADE 0xc0 | ||
| 30 | #define ISA_DMA_AUTOINIT 0x10 | ||
| 31 | |||
| 32 | #define ISA_DMA_MASK 0 | 27 | #define ISA_DMA_MASK 0 |
| 33 | #define ISA_DMA_MODE 1 | 28 | #define ISA_DMA_MODE 1 |
| 34 | #define ISA_DMA_CLRFF 2 | 29 | #define ISA_DMA_CLRFF 2 |
| @@ -49,38 +44,35 @@ static unsigned int isa_dma_port[8][7] = { | |||
| 49 | { 0xd4, 0xd6, 0xd8, 0x48a, 0x08a, 0xcc, 0xce } | 44 | { 0xd4, 0xd6, 0xd8, 0x48a, 0x08a, 0xcc, 0xce } |
| 50 | }; | 45 | }; |
| 51 | 46 | ||
| 52 | static int isa_get_dma_residue(dmach_t channel, dma_t *dma) | 47 | static int isa_get_dma_residue(unsigned int chan, dma_t *dma) |
| 53 | { | 48 | { |
| 54 | unsigned int io_port = isa_dma_port[channel][ISA_DMA_COUNT]; | 49 | unsigned int io_port = isa_dma_port[chan][ISA_DMA_COUNT]; |
| 55 | int count; | 50 | int count; |
| 56 | 51 | ||
| 57 | count = 1 + inb(io_port); | 52 | count = 1 + inb(io_port); |
| 58 | count |= inb(io_port) << 8; | 53 | count |= inb(io_port) << 8; |
| 59 | 54 | ||
| 60 | return channel < 4 ? count : (count << 1); | 55 | return chan < 4 ? count : (count << 1); |
| 61 | } | 56 | } |
| 62 | 57 | ||
| 63 | static void isa_enable_dma(dmach_t channel, dma_t *dma) | 58 | static void isa_enable_dma(unsigned int chan, dma_t *dma) |
| 64 | { | 59 | { |
| 65 | if (dma->invalid) { | 60 | if (dma->invalid) { |
| 66 | unsigned long address, length; | 61 | unsigned long address, length; |
| 67 | unsigned int mode; | 62 | unsigned int mode; |
| 68 | enum dma_data_direction direction; | 63 | enum dma_data_direction direction; |
| 69 | 64 | ||
| 70 | mode = channel & 3; | 65 | mode = (chan & 3) | dma->dma_mode; |
| 71 | switch (dma->dma_mode & DMA_MODE_MASK) { | 66 | switch (dma->dma_mode & DMA_MODE_MASK) { |
| 72 | case DMA_MODE_READ: | 67 | case DMA_MODE_READ: |
| 73 | mode |= ISA_DMA_MODE_READ; | ||
| 74 | direction = DMA_FROM_DEVICE; | 68 | direction = DMA_FROM_DEVICE; |
| 75 | break; | 69 | break; |
| 76 | 70 | ||
| 77 | case DMA_MODE_WRITE: | 71 | case DMA_MODE_WRITE: |
| 78 | mode |= ISA_DMA_MODE_WRITE; | ||
| 79 | direction = DMA_TO_DEVICE; | 72 | direction = DMA_TO_DEVICE; |
| 80 | break; | 73 | break; |
| 81 | 74 | ||
| 82 | case DMA_MODE_CASCADE: | 75 | case DMA_MODE_CASCADE: |
| 83 | mode |= ISA_DMA_MODE_CASCADE; | ||
| 84 | direction = DMA_BIDIRECTIONAL; | 76 | direction = DMA_BIDIRECTIONAL; |
| 85 | break; | 77 | break; |
| 86 | 78 | ||
| @@ -105,34 +97,31 @@ static void isa_enable_dma(dmach_t channel, dma_t *dma) | |||
| 105 | address = dma->buf.dma_address; | 97 | address = dma->buf.dma_address; |
| 106 | length = dma->buf.length - 1; | 98 | length = dma->buf.length - 1; |
| 107 | 99 | ||
| 108 | outb(address >> 16, isa_dma_port[channel][ISA_DMA_PGLO]); | 100 | outb(address >> 16, isa_dma_port[chan][ISA_DMA_PGLO]); |
| 109 | outb(address >> 24, isa_dma_port[channel][ISA_DMA_PGHI]); | 101 | outb(address >> 24, isa_dma_port[chan][ISA_DMA_PGHI]); |
| 110 | 102 | ||
| 111 | if (channel >= 4) { | 103 | if (chan >= 4) { |
| 112 | address >>= 1; | 104 | address >>= 1; |
| 113 | length >>= 1; | 105 | length >>= 1; |
| 114 | } | 106 | } |
| 115 | 107 | ||
| 116 | outb(0, isa_dma_port[channel][ISA_DMA_CLRFF]); | 108 | outb(0, isa_dma_port[chan][ISA_DMA_CLRFF]); |
| 117 | |||
| 118 | outb(address, isa_dma_port[channel][ISA_DMA_ADDR]); | ||
| 119 | outb(address >> 8, isa_dma_port[channel][ISA_DMA_ADDR]); | ||
| 120 | 109 | ||
| 121 | outb(length, isa_dma_port[channel][ISA_DMA_COUNT]); | 110 | outb(address, isa_dma_port[chan][ISA_DMA_ADDR]); |
| 122 | outb(length >> 8, isa_dma_port[channel][ISA_DMA_COUNT]); | 111 | outb(address >> 8, isa_dma_port[chan][ISA_DMA_ADDR]); |
| 123 | 112 | ||
| 124 | if (dma->dma_mode & DMA_AUTOINIT) | 113 | outb(length, isa_dma_port[chan][ISA_DMA_COUNT]); |
| 125 | mode |= ISA_DMA_AUTOINIT; | 114 | outb(length >> 8, isa_dma_port[chan][ISA_DMA_COUNT]); |
| 126 | 115 | ||
| 127 | outb(mode, isa_dma_port[channel][ISA_DMA_MODE]); | 116 | outb(mode, isa_dma_port[chan][ISA_DMA_MODE]); |
| 128 | dma->invalid = 0; | 117 | dma->invalid = 0; |
| 129 | } | 118 | } |
| 130 | outb(channel & 3, isa_dma_port[channel][ISA_DMA_MASK]); | 119 | outb(chan & 3, isa_dma_port[chan][ISA_DMA_MASK]); |
| 131 | } | 120 | } |
| 132 | 121 | ||
| 133 | static void isa_disable_dma(dmach_t channel, dma_t *dma) | 122 | static void isa_disable_dma(unsigned int chan, dma_t *dma) |
| 134 | { | 123 | { |
| 135 | outb(channel | 4, isa_dma_port[channel][ISA_DMA_MASK]); | 124 | outb(chan | 4, isa_dma_port[chan][ISA_DMA_MASK]); |
| 136 | } | 125 | } |
| 137 | 126 | ||
| 138 | static struct dma_ops isa_dma_ops = { | 127 | static struct dma_ops isa_dma_ops = { |
| @@ -160,7 +149,12 @@ static struct resource dma_resources[] = { { | |||
| 160 | .end = 0x048f | 149 | .end = 0x048f |
| 161 | } }; | 150 | } }; |
| 162 | 151 | ||
| 163 | void __init isa_init_dma(dma_t *dma) | 152 | static dma_t isa_dma[8]; |
| 153 | |||
| 154 | /* | ||
| 155 | * ISA DMA always starts at channel 0 | ||
| 156 | */ | ||
| 157 | void __init isa_init_dma(void) | ||
| 164 | { | 158 | { |
| 165 | /* | 159 | /* |
| 166 | * Try to autodetect presence of an ISA DMA controller. | 160 | * Try to autodetect presence of an ISA DMA controller. |
| @@ -178,11 +172,11 @@ void __init isa_init_dma(dma_t *dma) | |||
| 178 | outb(0xaa, 0x00); | 172 | outb(0xaa, 0x00); |
| 179 | 173 | ||
| 180 | if (inb(0) == 0x55 && inb(0) == 0xaa) { | 174 | if (inb(0) == 0x55 && inb(0) == 0xaa) { |
| 181 | int channel, i; | 175 | unsigned int chan, i; |
| 182 | 176 | ||
| 183 | for (channel = 0; channel < 8; channel++) { | 177 | for (chan = 0; chan < 8; chan++) { |
| 184 | dma[channel].d_ops = &isa_dma_ops; | 178 | isa_dma[chan].d_ops = &isa_dma_ops; |
| 185 | isa_disable_dma(channel, NULL); | 179 | isa_disable_dma(chan, NULL); |
| 186 | } | 180 | } |
| 187 | 181 | ||
| 188 | outb(0x40, 0x0b); | 182 | outb(0x40, 0x0b); |
| @@ -217,5 +211,12 @@ void __init isa_init_dma(dma_t *dma) | |||
| 217 | 211 | ||
| 218 | for (i = 0; i < ARRAY_SIZE(dma_resources); i++) | 212 | for (i = 0; i < ARRAY_SIZE(dma_resources); i++) |
| 219 | request_resource(&ioport_resource, dma_resources + i); | 213 | request_resource(&ioport_resource, dma_resources + i); |
| 214 | |||
| 215 | for (chan = 0; chan < 8; chan++) { | ||
| 216 | int ret = isa_dma_add(chan, &isa_dma[chan]); | ||
| 217 | if (ret) | ||
| 218 | printk(KERN_ERR "ISADMA%u: unable to register: %d\n", | ||
| 219 | chan, ret); | ||
| 220 | } | ||
| 220 | } | 221 | } |
| 221 | } | 222 | } |
diff --git a/arch/arm/kernel/dma.c b/arch/arm/kernel/dma.c index d006085ed7e7..7d5b9fb01e71 100644 --- a/arch/arm/kernel/dma.c +++ b/arch/arm/kernel/dma.c | |||
| @@ -15,6 +15,7 @@ | |||
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <linux/spinlock.h> | 16 | #include <linux/spinlock.h> |
| 17 | #include <linux/errno.h> | 17 | #include <linux/errno.h> |
| 18 | #include <linux/scatterlist.h> | ||
| 18 | 19 | ||
| 19 | #include <asm/dma.h> | 20 | #include <asm/dma.h> |
| 20 | 21 | ||
| @@ -23,19 +24,40 @@ | |||
| 23 | DEFINE_SPINLOCK(dma_spin_lock); | 24 | DEFINE_SPINLOCK(dma_spin_lock); |
| 24 | EXPORT_SYMBOL(dma_spin_lock); | 25 | EXPORT_SYMBOL(dma_spin_lock); |
| 25 | 26 | ||
| 26 | static dma_t dma_chan[MAX_DMA_CHANNELS]; | 27 | static dma_t *dma_chan[MAX_DMA_CHANNELS]; |
| 28 | |||
| 29 | static inline dma_t *dma_channel(unsigned int chan) | ||
| 30 | { | ||
| 31 | if (chan >= MAX_DMA_CHANNELS) | ||
| 32 | return NULL; | ||
| 33 | |||
| 34 | return dma_chan[chan]; | ||
| 35 | } | ||
| 36 | |||
| 37 | int __init isa_dma_add(unsigned int chan, dma_t *dma) | ||
| 38 | { | ||
| 39 | if (!dma->d_ops) | ||
| 40 | return -EINVAL; | ||
| 41 | |||
| 42 | sg_init_table(&dma->buf, 1); | ||
| 43 | |||
| 44 | if (dma_chan[chan]) | ||
| 45 | return -EBUSY; | ||
| 46 | dma_chan[chan] = dma; | ||
| 47 | return 0; | ||
| 48 | } | ||
| 27 | 49 | ||
| 28 | /* | 50 | /* |
| 29 | * Request DMA channel | 51 | * Request DMA channel |
| 30 | * | 52 | * |
| 31 | * On certain platforms, we have to allocate an interrupt as well... | 53 | * On certain platforms, we have to allocate an interrupt as well... |
| 32 | */ | 54 | */ |
| 33 | int request_dma(dmach_t channel, const char *device_id) | 55 | int request_dma(unsigned int chan, const char *device_id) |
| 34 | { | 56 | { |
| 35 | dma_t *dma = dma_chan + channel; | 57 | dma_t *dma = dma_channel(chan); |
| 36 | int ret; | 58 | int ret; |
| 37 | 59 | ||
| 38 | if (channel >= MAX_DMA_CHANNELS || !dma->d_ops) | 60 | if (!dma) |
| 39 | goto bad_dma; | 61 | goto bad_dma; |
| 40 | 62 | ||
| 41 | if (xchg(&dma->lock, 1) != 0) | 63 | if (xchg(&dma->lock, 1) != 0) |
| @@ -47,7 +69,7 @@ int request_dma(dmach_t channel, const char *device_id) | |||
| 47 | 69 | ||
| 48 | ret = 0; | 70 | ret = 0; |
| 49 | if (dma->d_ops->request) | 71 | if (dma->d_ops->request) |
| 50 | ret = dma->d_ops->request(channel, dma); | 72 | ret = dma->d_ops->request(chan, dma); |
| 51 | 73 | ||
| 52 | if (ret) | 74 | if (ret) |
| 53 | xchg(&dma->lock, 0); | 75 | xchg(&dma->lock, 0); |
| @@ -55,7 +77,7 @@ int request_dma(dmach_t channel, const char *device_id) | |||
| 55 | return ret; | 77 | return ret; |
| 56 | 78 | ||
| 57 | bad_dma: | 79 | bad_dma: |
| 58 | printk(KERN_ERR "dma: trying to allocate DMA%d\n", channel); | 80 | printk(KERN_ERR "dma: trying to allocate DMA%d\n", chan); |
| 59 | return -EINVAL; | 81 | return -EINVAL; |
| 60 | 82 | ||
| 61 | busy: | 83 | busy: |
| @@ -68,42 +90,42 @@ EXPORT_SYMBOL(request_dma); | |||
| 68 | * | 90 | * |
| 69 | * On certain platforms, we have to free interrupt as well... | 91 | * On certain platforms, we have to free interrupt as well... |
| 70 | */ | 92 | */ |
| 71 | void free_dma(dmach_t channel) | 93 | void free_dma(unsigned int chan) |
| 72 | { | 94 | { |
| 73 | dma_t *dma = dma_chan + channel; | 95 | dma_t *dma = dma_channel(chan); |
| 74 | 96 | ||
| 75 | if (channel >= MAX_DMA_CHANNELS || !dma->d_ops) | 97 | if (!dma) |
| 76 | goto bad_dma; | 98 | goto bad_dma; |
| 77 | 99 | ||
| 78 | if (dma->active) { | 100 | if (dma->active) { |
| 79 | printk(KERN_ERR "dma%d: freeing active DMA\n", channel); | 101 | printk(KERN_ERR "dma%d: freeing active DMA\n", chan); |
| 80 | dma->d_ops->disable(channel, dma); | 102 | dma->d_ops->disable(chan, dma); |
| 81 | dma->active = 0; | 103 | dma->active = 0; |
| 82 | } | 104 | } |
| 83 | 105 | ||
| 84 | if (xchg(&dma->lock, 0) != 0) { | 106 | if (xchg(&dma->lock, 0) != 0) { |
| 85 | if (dma->d_ops->free) | 107 | if (dma->d_ops->free) |
| 86 | dma->d_ops->free(channel, dma); | 108 | dma->d_ops->free(chan, dma); |
| 87 | return; | 109 | return; |
| 88 | } | 110 | } |
| 89 | 111 | ||
| 90 | printk(KERN_ERR "dma%d: trying to free free DMA\n", channel); | 112 | printk(KERN_ERR "dma%d: trying to free free DMA\n", chan); |
| 91 | return; | 113 | return; |
| 92 | 114 | ||
| 93 | bad_dma: | 115 | bad_dma: |
| 94 | printk(KERN_ERR "dma: trying to free DMA%d\n", channel); | 116 | printk(KERN_ERR "dma: trying to free DMA%d\n", chan); |
| 95 | } | 117 | } |
| 96 | EXPORT_SYMBOL(free_dma); | 118 | EXPORT_SYMBOL(free_dma); |
| 97 | 119 | ||
| 98 | /* Set DMA Scatter-Gather list | 120 | /* Set DMA Scatter-Gather list |
| 99 | */ | 121 | */ |
| 100 | void set_dma_sg (dmach_t channel, struct scatterlist *sg, int nr_sg) | 122 | void set_dma_sg (unsigned int chan, struct scatterlist *sg, int nr_sg) |
| 101 | { | 123 | { |
| 102 | dma_t *dma = dma_chan + channel; | 124 | dma_t *dma = dma_channel(chan); |
| 103 | 125 | ||
| 104 | if (dma->active) | 126 | if (dma->active) |
| 105 | printk(KERN_ERR "dma%d: altering DMA SG while " | 127 | printk(KERN_ERR "dma%d: altering DMA SG while " |
| 106 | "DMA active\n", channel); | 128 | "DMA active\n", chan); |
| 107 | 129 | ||
| 108 | dma->sg = sg; | 130 | dma->sg = sg; |
| 109 | dma->sgcount = nr_sg; | 131 | dma->sgcount = nr_sg; |
| @@ -115,13 +137,13 @@ EXPORT_SYMBOL(set_dma_sg); | |||
| 115 | * | 137 | * |
| 116 | * Copy address to the structure, and set the invalid bit | 138 | * Copy address to the structure, and set the invalid bit |
| 117 | */ | 139 | */ |
| 118 | void __set_dma_addr (dmach_t channel, void *addr) | 140 | void __set_dma_addr (unsigned int chan, void *addr) |
| 119 | { | 141 | { |
| 120 | dma_t *dma = dma_chan + channel; | 142 | dma_t *dma = dma_channel(chan); |
| 121 | 143 | ||
| 122 | if (dma->active) | 144 | if (dma->active) |
| 123 | printk(KERN_ERR "dma%d: altering DMA address while " | 145 | printk(KERN_ERR "dma%d: altering DMA address while " |
| 124 | "DMA active\n", channel); | 146 | "DMA active\n", chan); |
| 125 | 147 | ||
| 126 | dma->sg = NULL; | 148 | dma->sg = NULL; |
| 127 | dma->addr = addr; | 149 | dma->addr = addr; |
| @@ -133,13 +155,13 @@ EXPORT_SYMBOL(__set_dma_addr); | |||
| 133 | * | 155 | * |
| 134 | * Copy address to the structure, and set the invalid bit | 156 | * Copy address to the structure, and set the invalid bit |
| 135 | */ | 157 | */ |
| 136 | void set_dma_count (dmach_t channel, unsigned long count) | 158 | void set_dma_count (unsigned int chan, unsigned long count) |
| 137 | { | 159 | { |
| 138 | dma_t *dma = dma_chan + channel; | 160 | dma_t *dma = dma_channel(chan); |
| 139 | 161 | ||
| 140 | if (dma->active) | 162 | if (dma->active) |
| 141 | printk(KERN_ERR "dma%d: altering DMA count while " | 163 | printk(KERN_ERR "dma%d: altering DMA count while " |
| 142 | "DMA active\n", channel); | 164 | "DMA active\n", chan); |
| 143 | 165 | ||
| 144 | dma->sg = NULL; | 166 | dma->sg = NULL; |
| 145 | dma->count = count; | 167 | dma->count = count; |
| @@ -149,13 +171,13 @@ EXPORT_SYMBOL(set_dma_count); | |||
| 149 | 171 | ||
| 150 | /* Set DMA direction mode | 172 | /* Set DMA direction mode |
| 151 | */ | 173 | */ |
| 152 | void set_dma_mode (dmach_t channel, dmamode_t mode) | 174 | void set_dma_mode (unsigned int chan, unsigned int mode) |
| 153 | { | 175 | { |
| 154 | dma_t *dma = dma_chan + channel; | 176 | dma_t *dma = dma_channel(chan); |
| 155 | 177 | ||
| 156 | if (dma->active) | 178 | if (dma->active) |
| 157 | printk(KERN_ERR "dma%d: altering DMA mode while " | 179 | printk(KERN_ERR "dma%d: altering DMA mode while " |
| 158 | "DMA active\n", channel); | 180 | "DMA active\n", chan); |
| 159 | 181 | ||
| 160 | dma->dma_mode = mode; | 182 | dma->dma_mode = mode; |
| 161 | dma->invalid = 1; | 183 | dma->invalid = 1; |
| @@ -164,42 +186,42 @@ EXPORT_SYMBOL(set_dma_mode); | |||
| 164 | 186 | ||
| 165 | /* Enable DMA channel | 187 | /* Enable DMA channel |
| 166 | */ | 188 | */ |
| 167 | void enable_dma (dmach_t channel) | 189 | void enable_dma (unsigned int chan) |
| 168 | { | 190 | { |
| 169 | dma_t *dma = dma_chan + channel; | 191 | dma_t *dma = dma_channel(chan); |
| 170 | 192 | ||
| 171 | if (!dma->lock) | 193 | if (!dma->lock) |
| 172 | goto free_dma; | 194 | goto free_dma; |
| 173 | 195 | ||
| 174 | if (dma->active == 0) { | 196 | if (dma->active == 0) { |
| 175 | dma->active = 1; | 197 | dma->active = 1; |
| 176 | dma->d_ops->enable(channel, dma); | 198 | dma->d_ops->enable(chan, dma); |
| 177 | } | 199 | } |
| 178 | return; | 200 | return; |
| 179 | 201 | ||
| 180 | free_dma: | 202 | free_dma: |
| 181 | printk(KERN_ERR "dma%d: trying to enable free DMA\n", channel); | 203 | printk(KERN_ERR "dma%d: trying to enable free DMA\n", chan); |
| 182 | BUG(); | 204 | BUG(); |
| 183 | } | 205 | } |
| 184 | EXPORT_SYMBOL(enable_dma); | 206 | EXPORT_SYMBOL(enable_dma); |
| 185 | 207 | ||
| 186 | /* Disable DMA channel | 208 | /* Disable DMA channel |
| 187 | */ | 209 | */ |
| 188 | void disable_dma (dmach_t channel) | 210 | void disable_dma (unsigned int chan) |
| 189 | { | 211 | { |
| 190 | dma_t *dma = dma_chan + channel; | 212 | dma_t *dma = dma_channel(chan); |
| 191 | 213 | ||
| 192 | if (!dma->lock) | 214 | if (!dma->lock) |
| 193 | goto free_dma; | 215 | goto free_dma; |
| 194 | 216 | ||
| 195 | if (dma->active == 1) { | 217 | if (dma->active == 1) { |
| 196 | dma->active = 0; | 218 | dma->active = 0; |
| 197 | dma->d_ops->disable(channel, dma); | 219 | dma->d_ops->disable(chan, dma); |
| 198 | } | 220 | } |
| 199 | return; | 221 | return; |
| 200 | 222 | ||
| 201 | free_dma: | 223 | free_dma: |
| 202 | printk(KERN_ERR "dma%d: trying to disable free DMA\n", channel); | 224 | printk(KERN_ERR "dma%d: trying to disable free DMA\n", chan); |
| 203 | BUG(); | 225 | BUG(); |
| 204 | } | 226 | } |
| 205 | EXPORT_SYMBOL(disable_dma); | 227 | EXPORT_SYMBOL(disable_dma); |
| @@ -207,45 +229,38 @@ EXPORT_SYMBOL(disable_dma); | |||
| 207 | /* | 229 | /* |
| 208 | * Is the specified DMA channel active? | 230 | * Is the specified DMA channel active? |
| 209 | */ | 231 | */ |
| 210 | int dma_channel_active(dmach_t channel) | 232 | int dma_channel_active(unsigned int chan) |
| 211 | { | 233 | { |
| 212 | return dma_chan[channel].active; | 234 | dma_t *dma = dma_channel(chan); |
| 235 | return dma->active; | ||
| 213 | } | 236 | } |
| 214 | EXPORT_SYMBOL(dma_channel_active); | 237 | EXPORT_SYMBOL(dma_channel_active); |
| 215 | 238 | ||
| 216 | void set_dma_page(dmach_t channel, char pagenr) | 239 | void set_dma_page(unsigned int chan, char pagenr) |
| 217 | { | 240 | { |
| 218 | printk(KERN_ERR "dma%d: trying to set_dma_page\n", channel); | 241 | printk(KERN_ERR "dma%d: trying to set_dma_page\n", chan); |
| 219 | } | 242 | } |
| 220 | EXPORT_SYMBOL(set_dma_page); | 243 | EXPORT_SYMBOL(set_dma_page); |
| 221 | 244 | ||
| 222 | void set_dma_speed(dmach_t channel, int cycle_ns) | 245 | void set_dma_speed(unsigned int chan, int cycle_ns) |
| 223 | { | 246 | { |
| 224 | dma_t *dma = dma_chan + channel; | 247 | dma_t *dma = dma_channel(chan); |
| 225 | int ret = 0; | 248 | int ret = 0; |
| 226 | 249 | ||
| 227 | if (dma->d_ops->setspeed) | 250 | if (dma->d_ops->setspeed) |
| 228 | ret = dma->d_ops->setspeed(channel, dma, cycle_ns); | 251 | ret = dma->d_ops->setspeed(chan, dma, cycle_ns); |
| 229 | dma->speed = ret; | 252 | dma->speed = ret; |
| 230 | } | 253 | } |
| 231 | EXPORT_SYMBOL(set_dma_speed); | 254 | EXPORT_SYMBOL(set_dma_speed); |
| 232 | 255 | ||
| 233 | int get_dma_residue(dmach_t channel) | 256 | int get_dma_residue(unsigned int chan) |
| 234 | { | 257 | { |
| 235 | dma_t *dma = dma_chan + channel; | 258 | dma_t *dma = dma_channel(chan); |
| 236 | int ret = 0; | 259 | int ret = 0; |
| 237 | 260 | ||
| 238 | if (dma->d_ops->residue) | 261 | if (dma->d_ops->residue) |
| 239 | ret = dma->d_ops->residue(channel, dma); | 262 | ret = dma->d_ops->residue(chan, dma); |
| 240 | 263 | ||
| 241 | return ret; | 264 | return ret; |
| 242 | } | 265 | } |
| 243 | EXPORT_SYMBOL(get_dma_residue); | 266 | EXPORT_SYMBOL(get_dma_residue); |
| 244 | |||
| 245 | static int __init init_dma(void) | ||
| 246 | { | ||
| 247 | arch_dma_init(dma_chan); | ||
| 248 | return 0; | ||
| 249 | } | ||
| 250 | |||
| 251 | core_initcall(init_dma); | ||
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 85040cfeb5e5..d662a2f1fd85 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | #include <asm/vfpmacros.h> | 20 | #include <asm/vfpmacros.h> |
| 21 | #include <mach/entry-macro.S> | 21 | #include <mach/entry-macro.S> |
| 22 | #include <asm/thread_notify.h> | 22 | #include <asm/thread_notify.h> |
| 23 | #include <asm/unwind.h> | ||
| 23 | 24 | ||
| 24 | #include "entry-header.S" | 25 | #include "entry-header.S" |
| 25 | 26 | ||
| @@ -123,6 +124,8 @@ ENDPROC(__und_invalid) | |||
| 123 | #endif | 124 | #endif |
| 124 | 125 | ||
| 125 | .macro svc_entry, stack_hole=0 | 126 | .macro svc_entry, stack_hole=0 |
| 127 | UNWIND(.fnstart ) | ||
| 128 | UNWIND(.save {r0 - pc} ) | ||
| 126 | sub sp, sp, #(S_FRAME_SIZE + \stack_hole) | 129 | sub sp, sp, #(S_FRAME_SIZE + \stack_hole) |
| 127 | SPFIX( tst sp, #4 ) | 130 | SPFIX( tst sp, #4 ) |
| 128 | SPFIX( bicne sp, sp, #4 ) | 131 | SPFIX( bicne sp, sp, #4 ) |
| @@ -196,6 +199,7 @@ __dabt_svc: | |||
| 196 | ldr r0, [sp, #S_PSR] | 199 | ldr r0, [sp, #S_PSR] |
| 197 | msr spsr_cxsf, r0 | 200 | msr spsr_cxsf, r0 |
| 198 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | 201 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr |
| 202 | UNWIND(.fnend ) | ||
| 199 | ENDPROC(__dabt_svc) | 203 | ENDPROC(__dabt_svc) |
| 200 | 204 | ||
| 201 | .align 5 | 205 | .align 5 |
| @@ -228,6 +232,7 @@ __irq_svc: | |||
| 228 | bleq trace_hardirqs_on | 232 | bleq trace_hardirqs_on |
| 229 | #endif | 233 | #endif |
| 230 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | 234 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr |
| 235 | UNWIND(.fnend ) | ||
| 231 | ENDPROC(__irq_svc) | 236 | ENDPROC(__irq_svc) |
| 232 | 237 | ||
| 233 | .ltorg | 238 | .ltorg |
| @@ -278,6 +283,7 @@ __und_svc: | |||
| 278 | ldr lr, [sp, #S_PSR] @ Get SVC cpsr | 283 | ldr lr, [sp, #S_PSR] @ Get SVC cpsr |
| 279 | msr spsr_cxsf, lr | 284 | msr spsr_cxsf, lr |
| 280 | ldmia sp, {r0 - pc}^ @ Restore SVC registers | 285 | ldmia sp, {r0 - pc}^ @ Restore SVC registers |
| 286 | UNWIND(.fnend ) | ||
| 281 | ENDPROC(__und_svc) | 287 | ENDPROC(__und_svc) |
| 282 | 288 | ||
| 283 | .align 5 | 289 | .align 5 |
| @@ -320,6 +326,7 @@ __pabt_svc: | |||
| 320 | ldr r0, [sp, #S_PSR] | 326 | ldr r0, [sp, #S_PSR] |
| 321 | msr spsr_cxsf, r0 | 327 | msr spsr_cxsf, r0 |
| 322 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr | 328 | ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr |
| 329 | UNWIND(.fnend ) | ||
| 323 | ENDPROC(__pabt_svc) | 330 | ENDPROC(__pabt_svc) |
| 324 | 331 | ||
| 325 | .align 5 | 332 | .align 5 |
| @@ -343,6 +350,8 @@ ENDPROC(__pabt_svc) | |||
| 343 | #endif | 350 | #endif |
| 344 | 351 | ||
| 345 | .macro usr_entry | 352 | .macro usr_entry |
| 353 | UNWIND(.fnstart ) | ||
| 354 | UNWIND(.cantunwind ) @ don't unwind the user space | ||
| 346 | sub sp, sp, #S_FRAME_SIZE | 355 | sub sp, sp, #S_FRAME_SIZE |
| 347 | stmib sp, {r1 - r12} | 356 | stmib sp, {r1 - r12} |
| 348 | 357 | ||
| @@ -420,6 +429,7 @@ __dabt_usr: | |||
| 420 | mov r2, sp | 429 | mov r2, sp |
| 421 | adr lr, ret_from_exception | 430 | adr lr, ret_from_exception |
| 422 | b do_DataAbort | 431 | b do_DataAbort |
| 432 | UNWIND(.fnend ) | ||
| 423 | ENDPROC(__dabt_usr) | 433 | ENDPROC(__dabt_usr) |
| 424 | 434 | ||
| 425 | .align 5 | 435 | .align 5 |
| @@ -450,6 +460,7 @@ __irq_usr: | |||
| 450 | 460 | ||
| 451 | mov why, #0 | 461 | mov why, #0 |
| 452 | b ret_to_user | 462 | b ret_to_user |
| 463 | UNWIND(.fnend ) | ||
| 453 | ENDPROC(__irq_usr) | 464 | ENDPROC(__irq_usr) |
| 454 | 465 | ||
| 455 | .ltorg | 466 | .ltorg |
| @@ -484,6 +495,7 @@ __und_usr: | |||
| 484 | #else | 495 | #else |
| 485 | b __und_usr_unknown | 496 | b __und_usr_unknown |
| 486 | #endif | 497 | #endif |
| 498 | UNWIND(.fnend ) | ||
| 487 | ENDPROC(__und_usr) | 499 | ENDPROC(__und_usr) |
| 488 | 500 | ||
| 489 | @ | 501 | @ |
| @@ -671,14 +683,18 @@ __pabt_usr: | |||
| 671 | enable_irq @ Enable interrupts | 683 | enable_irq @ Enable interrupts |
| 672 | mov r1, sp @ regs | 684 | mov r1, sp @ regs |
| 673 | bl do_PrefetchAbort @ call abort handler | 685 | bl do_PrefetchAbort @ call abort handler |
| 686 | UNWIND(.fnend ) | ||
| 674 | /* fall through */ | 687 | /* fall through */ |
| 675 | /* | 688 | /* |
| 676 | * This is the return code to user mode for abort handlers | 689 | * This is the return code to user mode for abort handlers |
| 677 | */ | 690 | */ |
| 678 | ENTRY(ret_from_exception) | 691 | ENTRY(ret_from_exception) |
| 692 | UNWIND(.fnstart ) | ||
| 693 | UNWIND(.cantunwind ) | ||
| 679 | get_thread_info tsk | 694 | get_thread_info tsk |
| 680 | mov why, #0 | 695 | mov why, #0 |
| 681 | b ret_to_user | 696 | b ret_to_user |
| 697 | UNWIND(.fnend ) | ||
| 682 | ENDPROC(__pabt_usr) | 698 | ENDPROC(__pabt_usr) |
| 683 | ENDPROC(ret_from_exception) | 699 | ENDPROC(ret_from_exception) |
| 684 | 700 | ||
| @@ -688,6 +704,8 @@ ENDPROC(ret_from_exception) | |||
| 688 | * previous and next are guaranteed not to be the same. | 704 | * previous and next are guaranteed not to be the same. |
| 689 | */ | 705 | */ |
| 690 | ENTRY(__switch_to) | 706 | ENTRY(__switch_to) |
| 707 | UNWIND(.fnstart ) | ||
| 708 | UNWIND(.cantunwind ) | ||
| 691 | add ip, r1, #TI_CPU_SAVE | 709 | add ip, r1, #TI_CPU_SAVE |
| 692 | ldr r3, [r2, #TI_TP_VALUE] | 710 | ldr r3, [r2, #TI_TP_VALUE] |
| 693 | stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack | 711 | stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack |
| @@ -717,6 +735,7 @@ ENTRY(__switch_to) | |||
| 717 | bl atomic_notifier_call_chain | 735 | bl atomic_notifier_call_chain |
| 718 | mov r0, r5 | 736 | mov r0, r5 |
| 719 | ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously | 737 | ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously |
| 738 | UNWIND(.fnend ) | ||
| 720 | ENDPROC(__switch_to) | 739 | ENDPROC(__switch_to) |
| 721 | 740 | ||
| 722 | __INIT | 741 | __INIT |
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 49a6ba926c2b..b55cb0331809 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | #include <asm/unistd.h> | 11 | #include <asm/unistd.h> |
| 12 | #include <asm/ftrace.h> | 12 | #include <asm/ftrace.h> |
| 13 | #include <mach/entry-macro.S> | 13 | #include <mach/entry-macro.S> |
| 14 | #include <asm/unwind.h> | ||
| 14 | 15 | ||
| 15 | #include "entry-header.S" | 16 | #include "entry-header.S" |
| 16 | 17 | ||
| @@ -22,6 +23,8 @@ | |||
| 22 | * stack. | 23 | * stack. |
| 23 | */ | 24 | */ |
| 24 | ret_fast_syscall: | 25 | ret_fast_syscall: |
| 26 | UNWIND(.fnstart ) | ||
| 27 | UNWIND(.cantunwind ) | ||
| 25 | disable_irq @ disable interrupts | 28 | disable_irq @ disable interrupts |
| 26 | ldr r1, [tsk, #TI_FLAGS] | 29 | ldr r1, [tsk, #TI_FLAGS] |
| 27 | tst r1, #_TIF_WORK_MASK | 30 | tst r1, #_TIF_WORK_MASK |
| @@ -38,6 +41,7 @@ ret_fast_syscall: | |||
| 38 | mov r0, r0 | 41 | mov r0, r0 |
| 39 | add sp, sp, #S_FRAME_SIZE - S_PC | 42 | add sp, sp, #S_FRAME_SIZE - S_PC |
| 40 | movs pc, lr @ return & move spsr_svc into cpsr | 43 | movs pc, lr @ return & move spsr_svc into cpsr |
| 44 | UNWIND(.fnend ) | ||
| 41 | 45 | ||
| 42 | /* | 46 | /* |
| 43 | * Ok, we need to do extra processing, enter the slow path. | 47 | * Ok, we need to do extra processing, enter the slow path. |
| @@ -111,6 +115,7 @@ ENTRY(mcount) | |||
| 111 | .globl mcount_call | 115 | .globl mcount_call |
| 112 | mcount_call: | 116 | mcount_call: |
| 113 | bl ftrace_stub | 117 | bl ftrace_stub |
| 118 | ldr lr, [fp, #-4] @ restore lr | ||
| 114 | ldmia sp!, {r0-r3, pc} | 119 | ldmia sp!, {r0-r3, pc} |
| 115 | 120 | ||
| 116 | ENTRY(ftrace_caller) | 121 | ENTRY(ftrace_caller) |
| @@ -122,6 +127,7 @@ ENTRY(ftrace_caller) | |||
| 122 | .globl ftrace_call | 127 | .globl ftrace_call |
| 123 | ftrace_call: | 128 | ftrace_call: |
| 124 | bl ftrace_stub | 129 | bl ftrace_stub |
| 130 | ldr lr, [fp, #-4] @ restore lr | ||
| 125 | ldmia sp!, {r0-r3, pc} | 131 | ldmia sp!, {r0-r3, pc} |
| 126 | 132 | ||
| 127 | #else | 133 | #else |
| @@ -133,6 +139,7 @@ ENTRY(mcount) | |||
| 133 | adr r0, ftrace_stub | 139 | adr r0, ftrace_stub |
| 134 | cmp r0, r2 | 140 | cmp r0, r2 |
| 135 | bne trace | 141 | bne trace |
| 142 | ldr lr, [fp, #-4] @ restore lr | ||
| 136 | ldmia sp!, {r0-r3, pc} | 143 | ldmia sp!, {r0-r3, pc} |
| 137 | 144 | ||
| 138 | trace: | 145 | trace: |
| @@ -141,6 +148,7 @@ trace: | |||
| 141 | sub r0, r0, #MCOUNT_INSN_SIZE | 148 | sub r0, r0, #MCOUNT_INSN_SIZE |
| 142 | mov lr, pc | 149 | mov lr, pc |
| 143 | mov pc, r2 | 150 | mov pc, r2 |
| 151 | mov lr, r1 @ restore lr | ||
| 144 | ldmia sp!, {r0-r3, pc} | 152 | ldmia sp!, {r0-r3, pc} |
| 145 | 153 | ||
| 146 | #endif /* CONFIG_DYNAMIC_FTRACE */ | 154 | #endif /* CONFIG_DYNAMIC_FTRACE */ |
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c index 36f81d967979..6ff7919613d7 100644 --- a/arch/arm/kernel/fiq.c +++ b/arch/arm/kernel/fiq.c | |||
| @@ -88,7 +88,7 @@ void set_fiq_handler(void *start, unsigned int length) | |||
| 88 | * disable irqs for the duration. Note - these functions are almost | 88 | * disable irqs for the duration. Note - these functions are almost |
| 89 | * entirely coded in assembly. | 89 | * entirely coded in assembly. |
| 90 | */ | 90 | */ |
| 91 | void __attribute__((naked)) set_fiq_regs(struct pt_regs *regs) | 91 | void __naked set_fiq_regs(struct pt_regs *regs) |
| 92 | { | 92 | { |
| 93 | register unsigned long tmp; | 93 | register unsigned long tmp; |
| 94 | asm volatile ( | 94 | asm volatile ( |
| @@ -106,7 +106,7 @@ void __attribute__((naked)) set_fiq_regs(struct pt_regs *regs) | |||
| 106 | : "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | FIQ_MODE)); | 106 | : "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | FIQ_MODE)); |
| 107 | } | 107 | } |
| 108 | 108 | ||
| 109 | void __attribute__((naked)) get_fiq_regs(struct pt_regs *regs) | 109 | void __naked get_fiq_regs(struct pt_regs *regs) |
| 110 | { | 110 | { |
| 111 | register unsigned long tmp; | 111 | register unsigned long tmp; |
| 112 | asm volatile ( | 112 | asm volatile ( |
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index dab48f27263f..13dbd5bf5cc2 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | 22 | ||
| 23 | #include <asm/pgtable.h> | 23 | #include <asm/pgtable.h> |
| 24 | #include <asm/sections.h> | 24 | #include <asm/sections.h> |
| 25 | #include <asm/unwind.h> | ||
| 25 | 26 | ||
| 26 | #ifdef CONFIG_XIP_KERNEL | 27 | #ifdef CONFIG_XIP_KERNEL |
| 27 | /* | 28 | /* |
| @@ -66,6 +67,24 @@ int module_frob_arch_sections(Elf_Ehdr *hdr, | |||
| 66 | char *secstrings, | 67 | char *secstrings, |
| 67 | struct module *mod) | 68 | struct module *mod) |
| 68 | { | 69 | { |
| 70 | #ifdef CONFIG_ARM_UNWIND | ||
| 71 | Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum; | ||
| 72 | |||
| 73 | for (s = sechdrs; s < sechdrs_end; s++) { | ||
| 74 | if (strcmp(".ARM.exidx.init.text", secstrings + s->sh_name) == 0) | ||
| 75 | mod->arch.unw_sec_init = s; | ||
| 76 | else if (strcmp(".ARM.exidx.devinit.text", secstrings + s->sh_name) == 0) | ||
| 77 | mod->arch.unw_sec_devinit = s; | ||
| 78 | else if (strcmp(".ARM.exidx", secstrings + s->sh_name) == 0) | ||
| 79 | mod->arch.unw_sec_core = s; | ||
| 80 | else if (strcmp(".init.text", secstrings + s->sh_name) == 0) | ||
| 81 | mod->arch.sec_init_text = s; | ||
| 82 | else if (strcmp(".devinit.text", secstrings + s->sh_name) == 0) | ||
| 83 | mod->arch.sec_devinit_text = s; | ||
| 84 | else if (strcmp(".text", secstrings + s->sh_name) == 0) | ||
| 85 | mod->arch.sec_core_text = s; | ||
| 86 | } | ||
| 87 | #endif | ||
| 69 | return 0; | 88 | return 0; |
| 70 | } | 89 | } |
| 71 | 90 | ||
| @@ -104,6 +123,10 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, | |||
| 104 | loc = dstsec->sh_addr + rel->r_offset; | 123 | loc = dstsec->sh_addr + rel->r_offset; |
| 105 | 124 | ||
| 106 | switch (ELF32_R_TYPE(rel->r_info)) { | 125 | switch (ELF32_R_TYPE(rel->r_info)) { |
| 126 | case R_ARM_NONE: | ||
| 127 | /* ignore */ | ||
| 128 | break; | ||
| 129 | |||
| 107 | case R_ARM_ABS32: | 130 | case R_ARM_ABS32: |
| 108 | *(u32 *)loc += sym->st_value; | 131 | *(u32 *)loc += sym->st_value; |
| 109 | break; | 132 | break; |
| @@ -132,6 +155,11 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, | |||
| 132 | *(u32 *)loc |= offset & 0x00ffffff; | 155 | *(u32 *)loc |= offset & 0x00ffffff; |
| 133 | break; | 156 | break; |
| 134 | 157 | ||
| 158 | case R_ARM_PREL31: | ||
| 159 | offset = *(u32 *)loc + sym->st_value - loc; | ||
| 160 | *(u32 *)loc = offset & 0x7fffffff; | ||
| 161 | break; | ||
| 162 | |||
| 135 | default: | 163 | default: |
| 136 | printk(KERN_ERR "%s: unknown relocation: %u\n", | 164 | printk(KERN_ERR "%s: unknown relocation: %u\n", |
| 137 | module->name, ELF32_R_TYPE(rel->r_info)); | 165 | module->name, ELF32_R_TYPE(rel->r_info)); |
| @@ -150,14 +178,50 @@ apply_relocate_add(Elf32_Shdr *sechdrs, const char *strtab, | |||
| 150 | return -ENOEXEC; | 178 | return -ENOEXEC; |
| 151 | } | 179 | } |
| 152 | 180 | ||
| 181 | #ifdef CONFIG_ARM_UNWIND | ||
| 182 | static void register_unwind_tables(struct module *mod) | ||
| 183 | { | ||
| 184 | if (mod->arch.unw_sec_init && mod->arch.sec_init_text) | ||
| 185 | mod->arch.unwind_init = | ||
| 186 | unwind_table_add(mod->arch.unw_sec_init->sh_addr, | ||
| 187 | mod->arch.unw_sec_init->sh_size, | ||
| 188 | mod->arch.sec_init_text->sh_addr, | ||
| 189 | mod->arch.sec_init_text->sh_size); | ||
| 190 | if (mod->arch.unw_sec_devinit && mod->arch.sec_devinit_text) | ||
| 191 | mod->arch.unwind_devinit = | ||
| 192 | unwind_table_add(mod->arch.unw_sec_devinit->sh_addr, | ||
| 193 | mod->arch.unw_sec_devinit->sh_size, | ||
| 194 | mod->arch.sec_devinit_text->sh_addr, | ||
| 195 | mod->arch.sec_devinit_text->sh_size); | ||
| 196 | if (mod->arch.unw_sec_core && mod->arch.sec_core_text) | ||
| 197 | mod->arch.unwind_core = | ||
| 198 | unwind_table_add(mod->arch.unw_sec_core->sh_addr, | ||
| 199 | mod->arch.unw_sec_core->sh_size, | ||
| 200 | mod->arch.sec_core_text->sh_addr, | ||
| 201 | mod->arch.sec_core_text->sh_size); | ||
| 202 | } | ||
| 203 | |||
| 204 | static void unregister_unwind_tables(struct module *mod) | ||
| 205 | { | ||
| 206 | unwind_table_del(mod->arch.unwind_init); | ||
| 207 | unwind_table_del(mod->arch.unwind_devinit); | ||
| 208 | unwind_table_del(mod->arch.unwind_core); | ||
| 209 | } | ||
| 210 | #else | ||
| 211 | static inline void register_unwind_tables(struct module *mod) { } | ||
| 212 | static inline void unregister_unwind_tables(struct module *mod) { } | ||
| 213 | #endif | ||
| 214 | |||
| 153 | int | 215 | int |
| 154 | module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs, | 216 | module_finalize(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs, |
| 155 | struct module *module) | 217 | struct module *module) |
| 156 | { | 218 | { |
| 219 | register_unwind_tables(module); | ||
| 157 | return 0; | 220 | return 0; |
| 158 | } | 221 | } |
| 159 | 222 | ||
| 160 | void | 223 | void |
| 161 | module_arch_cleanup(struct module *mod) | 224 | module_arch_cleanup(struct module *mod) |
| 162 | { | 225 | { |
| 226 | unregister_unwind_tables(mod); | ||
| 163 | } | 227 | } |
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index d3ea6fa89521..2de14e2afdc5 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c | |||
| @@ -34,6 +34,7 @@ | |||
| 34 | #include <asm/processor.h> | 34 | #include <asm/processor.h> |
| 35 | #include <asm/system.h> | 35 | #include <asm/system.h> |
| 36 | #include <asm/thread_notify.h> | 36 | #include <asm/thread_notify.h> |
| 37 | #include <asm/stacktrace.h> | ||
| 37 | #include <asm/mach/time.h> | 38 | #include <asm/mach/time.h> |
| 38 | 39 | ||
| 39 | static const char *processor_modes[] = { | 40 | static const char *processor_modes[] = { |
| @@ -82,7 +83,7 @@ static int __init hlt_setup(char *__unused) | |||
| 82 | __setup("nohlt", nohlt_setup); | 83 | __setup("nohlt", nohlt_setup); |
| 83 | __setup("hlt", hlt_setup); | 84 | __setup("hlt", hlt_setup); |
| 84 | 85 | ||
| 85 | void arm_machine_restart(char mode) | 86 | void arm_machine_restart(char mode, const char *cmd) |
| 86 | { | 87 | { |
| 87 | /* | 88 | /* |
| 88 | * Clean and disable cache, and turn off interrupts | 89 | * Clean and disable cache, and turn off interrupts |
| @@ -99,7 +100,7 @@ void arm_machine_restart(char mode) | |||
| 99 | /* | 100 | /* |
| 100 | * Now call the architecture specific reboot code. | 101 | * Now call the architecture specific reboot code. |
| 101 | */ | 102 | */ |
| 102 | arch_reset(mode); | 103 | arch_reset(mode, cmd); |
| 103 | 104 | ||
| 104 | /* | 105 | /* |
| 105 | * Whoops - the architecture was unable to reboot. | 106 | * Whoops - the architecture was unable to reboot. |
| @@ -119,7 +120,7 @@ EXPORT_SYMBOL(pm_idle); | |||
| 119 | void (*pm_power_off)(void); | 120 | void (*pm_power_off)(void); |
| 120 | EXPORT_SYMBOL(pm_power_off); | 121 | EXPORT_SYMBOL(pm_power_off); |
| 121 | 122 | ||
| 122 | void (*arm_pm_restart)(char str) = arm_machine_restart; | 123 | void (*arm_pm_restart)(char str, const char *cmd) = arm_machine_restart; |
| 123 | EXPORT_SYMBOL_GPL(arm_pm_restart); | 124 | EXPORT_SYMBOL_GPL(arm_pm_restart); |
| 124 | 125 | ||
| 125 | 126 | ||
| @@ -194,9 +195,9 @@ void machine_power_off(void) | |||
| 194 | pm_power_off(); | 195 | pm_power_off(); |
| 195 | } | 196 | } |
| 196 | 197 | ||
| 197 | void machine_restart(char * __unused) | 198 | void machine_restart(char *cmd) |
| 198 | { | 199 | { |
| 199 | arm_pm_restart(reboot_mode); | 200 | arm_pm_restart(reboot_mode, cmd); |
| 200 | } | 201 | } |
| 201 | 202 | ||
| 202 | void __show_regs(struct pt_regs *regs) | 203 | void __show_regs(struct pt_regs *regs) |
| @@ -372,23 +373,21 @@ EXPORT_SYMBOL(kernel_thread); | |||
| 372 | 373 | ||
| 373 | unsigned long get_wchan(struct task_struct *p) | 374 | unsigned long get_wchan(struct task_struct *p) |
| 374 | { | 375 | { |
| 375 | unsigned long fp, lr; | 376 | struct stackframe frame; |
| 376 | unsigned long stack_start, stack_end; | ||
| 377 | int count = 0; | 377 | int count = 0; |
| 378 | if (!p || p == current || p->state == TASK_RUNNING) | 378 | if (!p || p == current || p->state == TASK_RUNNING) |
| 379 | return 0; | 379 | return 0; |
| 380 | 380 | ||
| 381 | stack_start = (unsigned long)end_of_stack(p); | 381 | frame.fp = thread_saved_fp(p); |
| 382 | stack_end = (unsigned long)task_stack_page(p) + THREAD_SIZE; | 382 | frame.sp = thread_saved_sp(p); |
| 383 | 383 | frame.lr = 0; /* recovered from the stack */ | |
| 384 | fp = thread_saved_fp(p); | 384 | frame.pc = thread_saved_pc(p); |
| 385 | do { | 385 | do { |
| 386 | if (fp < stack_start || fp > stack_end) | 386 | int ret = unwind_frame(&frame); |
| 387 | if (ret < 0) | ||
| 387 | return 0; | 388 | return 0; |
| 388 | lr = ((unsigned long *)fp)[-1]; | 389 | if (!in_sched_functions(frame.pc)) |
| 389 | if (!in_sched_functions(lr)) | 390 | return frame.pc; |
| 390 | return lr; | ||
| 391 | fp = *(unsigned long *) (fp - 12); | ||
| 392 | } while (count ++ < 16); | 391 | } while (count ++ < 16); |
| 393 | return 0; | 392 | return 0; |
| 394 | } | 393 | } |
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c index df653ea59250..89882a1d0187 100644 --- a/arch/arm/kernel/ptrace.c +++ b/arch/arm/kernel/ptrace.c | |||
| @@ -653,6 +653,54 @@ static int ptrace_setcrunchregs(struct task_struct *tsk, void __user *ufp) | |||
| 653 | } | 653 | } |
| 654 | #endif | 654 | #endif |
| 655 | 655 | ||
| 656 | #ifdef CONFIG_VFP | ||
| 657 | /* | ||
| 658 | * Get the child VFP state. | ||
| 659 | */ | ||
| 660 | static int ptrace_getvfpregs(struct task_struct *tsk, void __user *data) | ||
| 661 | { | ||
| 662 | struct thread_info *thread = task_thread_info(tsk); | ||
| 663 | union vfp_state *vfp = &thread->vfpstate; | ||
| 664 | struct user_vfp __user *ufp = data; | ||
| 665 | |||
| 666 | vfp_sync_state(thread); | ||
| 667 | |||
| 668 | /* copy the floating point registers */ | ||
| 669 | if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs, | ||
| 670 | sizeof(vfp->hard.fpregs))) | ||
| 671 | return -EFAULT; | ||
| 672 | |||
| 673 | /* copy the status and control register */ | ||
| 674 | if (put_user(vfp->hard.fpscr, &ufp->fpscr)) | ||
| 675 | return -EFAULT; | ||
| 676 | |||
| 677 | return 0; | ||
| 678 | } | ||
| 679 | |||
| 680 | /* | ||
| 681 | * Set the child VFP state. | ||
| 682 | */ | ||
| 683 | static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data) | ||
| 684 | { | ||
| 685 | struct thread_info *thread = task_thread_info(tsk); | ||
| 686 | union vfp_state *vfp = &thread->vfpstate; | ||
| 687 | struct user_vfp __user *ufp = data; | ||
| 688 | |||
| 689 | vfp_sync_state(thread); | ||
| 690 | |||
| 691 | /* copy the floating point registers */ | ||
| 692 | if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs, | ||
| 693 | sizeof(vfp->hard.fpregs))) | ||
| 694 | return -EFAULT; | ||
| 695 | |||
| 696 | /* copy the status and control register */ | ||
| 697 | if (get_user(vfp->hard.fpscr, &ufp->fpscr)) | ||
| 698 | return -EFAULT; | ||
| 699 | |||
| 700 | return 0; | ||
| 701 | } | ||
| 702 | #endif | ||
| 703 | |||
| 656 | long arch_ptrace(struct task_struct *child, long request, long addr, long data) | 704 | long arch_ptrace(struct task_struct *child, long request, long addr, long data) |
| 657 | { | 705 | { |
| 658 | int ret; | 706 | int ret; |
| @@ -775,6 +823,16 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) | |||
| 775 | break; | 823 | break; |
| 776 | #endif | 824 | #endif |
| 777 | 825 | ||
| 826 | #ifdef CONFIG_VFP | ||
| 827 | case PTRACE_GETVFPREGS: | ||
| 828 | ret = ptrace_getvfpregs(child, (void __user *)data); | ||
| 829 | break; | ||
| 830 | |||
| 831 | case PTRACE_SETVFPREGS: | ||
| 832 | ret = ptrace_setvfpregs(child, (void __user *)data); | ||
| 833 | break; | ||
| 834 | #endif | ||
| 835 | |||
| 778 | default: | 836 | default: |
| 779 | ret = ptrace_request(child, request, addr, data); | 837 | ret = ptrace_request(child, request, addr, data); |
| 780 | break; | 838 | break; |
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c index 68d6494c0389..bc5e4128f9f3 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c | |||
| @@ -40,6 +40,7 @@ | |||
| 40 | #include <asm/mach/irq.h> | 40 | #include <asm/mach/irq.h> |
| 41 | #include <asm/mach/time.h> | 41 | #include <asm/mach/time.h> |
| 42 | #include <asm/traps.h> | 42 | #include <asm/traps.h> |
| 43 | #include <asm/unwind.h> | ||
| 43 | 44 | ||
| 44 | #include "compat.h" | 45 | #include "compat.h" |
| 45 | #include "atags.h" | 46 | #include "atags.h" |
| @@ -685,6 +686,8 @@ void __init setup_arch(char **cmdline_p) | |||
| 685 | struct machine_desc *mdesc; | 686 | struct machine_desc *mdesc; |
| 686 | char *from = default_command_line; | 687 | char *from = default_command_line; |
| 687 | 688 | ||
| 689 | unwind_init(); | ||
| 690 | |||
| 688 | setup_processor(); | 691 | setup_processor(); |
| 689 | mdesc = setup_machine(machine_arch_type); | 692 | mdesc = setup_machine(machine_arch_type); |
| 690 | machine_name = mdesc->name; | 693 | machine_name = mdesc->name; |
| @@ -780,6 +783,8 @@ static const char *hwcap_str[] = { | |||
| 780 | "crunch", | 783 | "crunch", |
| 781 | "thumbee", | 784 | "thumbee", |
| 782 | "neon", | 785 | "neon", |
| 786 | "vfpv3", | ||
| 787 | "vfpv3d16", | ||
| 783 | NULL | 788 | NULL |
| 784 | }; | 789 | }; |
| 785 | 790 | ||
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 55fa7ff96a3e..7801aac3c043 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c | |||
| @@ -93,6 +93,7 @@ int __cpuinit __cpu_up(unsigned int cpu) | |||
| 93 | pmd = pmd_offset(pgd + pgd_index(PHYS_OFFSET), PHYS_OFFSET); | 93 | pmd = pmd_offset(pgd + pgd_index(PHYS_OFFSET), PHYS_OFFSET); |
| 94 | *pmd = __pmd((PHYS_OFFSET & PGDIR_MASK) | | 94 | *pmd = __pmd((PHYS_OFFSET & PGDIR_MASK) | |
| 95 | PMD_TYPE_SECT | PMD_SECT_AP_WRITE); | 95 | PMD_TYPE_SECT | PMD_SECT_AP_WRITE); |
| 96 | flush_pmd_entry(pmd); | ||
| 96 | 97 | ||
| 97 | /* | 98 | /* |
| 98 | * We need to tell the secondary core where to find | 99 | * We need to tell the secondary core where to find |
| @@ -130,6 +131,7 @@ int __cpuinit __cpu_up(unsigned int cpu) | |||
| 130 | secondary_data.pgdir = 0; | 131 | secondary_data.pgdir = 0; |
| 131 | 132 | ||
| 132 | *pmd = __pmd(0); | 133 | *pmd = __pmd(0); |
| 134 | clean_pmd_entry(pmd); | ||
| 133 | pgd_free(&init_mm, pgd); | 135 | pgd_free(&init_mm, pgd); |
| 134 | 136 | ||
| 135 | if (ret) { | 137 | if (ret) { |
diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c index fc650f64df43..9f444e5cc165 100644 --- a/arch/arm/kernel/stacktrace.c +++ b/arch/arm/kernel/stacktrace.c | |||
| @@ -2,35 +2,60 @@ | |||
| 2 | #include <linux/sched.h> | 2 | #include <linux/sched.h> |
| 3 | #include <linux/stacktrace.h> | 3 | #include <linux/stacktrace.h> |
| 4 | 4 | ||
| 5 | #include "stacktrace.h" | 5 | #include <asm/stacktrace.h> |
| 6 | 6 | ||
| 7 | int walk_stackframe(unsigned long fp, unsigned long low, unsigned long high, | 7 | #if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) |
| 8 | int (*fn)(struct stackframe *, void *), void *data) | 8 | /* |
| 9 | * Unwind the current stack frame and store the new register values in the | ||
| 10 | * structure passed as argument. Unwinding is equivalent to a function return, | ||
| 11 | * hence the new PC value rather than LR should be used for backtrace. | ||
| 12 | * | ||
| 13 | * With framepointer enabled, a simple function prologue looks like this: | ||
| 14 | * mov ip, sp | ||
| 15 | * stmdb sp!, {fp, ip, lr, pc} | ||
| 16 | * sub fp, ip, #4 | ||
| 17 | * | ||
| 18 | * A simple function epilogue looks like this: | ||
| 19 | * ldm sp, {fp, sp, pc} | ||
| 20 | * | ||
| 21 | * Note that with framepointer enabled, even the leaf functions have the same | ||
| 22 | * prologue and epilogue, therefore we can ignore the LR value in this case. | ||
| 23 | */ | ||
| 24 | int unwind_frame(struct stackframe *frame) | ||
| 9 | { | 25 | { |
| 10 | struct stackframe *frame; | 26 | unsigned long high, low; |
| 11 | 27 | unsigned long fp = frame->fp; | |
| 12 | do { | ||
| 13 | /* | ||
| 14 | * Check current frame pointer is within bounds | ||
| 15 | */ | ||
| 16 | if (fp < (low + 12) || fp + 4 >= high) | ||
| 17 | break; | ||
| 18 | 28 | ||
| 19 | frame = (struct stackframe *)(fp - 12); | 29 | /* only go to a higher address on the stack */ |
| 30 | low = frame->sp; | ||
| 31 | high = ALIGN(low, THREAD_SIZE) + THREAD_SIZE; | ||
| 20 | 32 | ||
| 21 | if (fn(frame, data)) | 33 | /* check current frame pointer is within bounds */ |
| 22 | break; | 34 | if (fp < (low + 12) || fp + 4 >= high) |
| 35 | return -EINVAL; | ||
| 23 | 36 | ||
| 24 | /* | 37 | /* restore the registers from the stack frame */ |
| 25 | * Update the low bound - the next frame must always | 38 | frame->fp = *(unsigned long *)(fp - 12); |
| 26 | * be at a higher address than the current frame. | 39 | frame->sp = *(unsigned long *)(fp - 8); |
| 27 | */ | 40 | frame->pc = *(unsigned long *)(fp - 4); |
| 28 | low = fp + 4; | ||
| 29 | fp = frame->fp; | ||
| 30 | } while (fp); | ||
| 31 | 41 | ||
| 32 | return 0; | 42 | return 0; |
| 33 | } | 43 | } |
| 44 | #endif | ||
| 45 | |||
| 46 | void walk_stackframe(struct stackframe *frame, | ||
| 47 | int (*fn)(struct stackframe *, void *), void *data) | ||
| 48 | { | ||
| 49 | while (1) { | ||
| 50 | int ret; | ||
| 51 | |||
| 52 | if (fn(frame, data)) | ||
| 53 | break; | ||
| 54 | ret = unwind_frame(frame); | ||
| 55 | if (ret < 0) | ||
| 56 | break; | ||
| 57 | } | ||
| 58 | } | ||
| 34 | EXPORT_SYMBOL(walk_stackframe); | 59 | EXPORT_SYMBOL(walk_stackframe); |
| 35 | 60 | ||
| 36 | #ifdef CONFIG_STACKTRACE | 61 | #ifdef CONFIG_STACKTRACE |
| @@ -44,7 +69,7 @@ static int save_trace(struct stackframe *frame, void *d) | |||
| 44 | { | 69 | { |
| 45 | struct stack_trace_data *data = d; | 70 | struct stack_trace_data *data = d; |
| 46 | struct stack_trace *trace = data->trace; | 71 | struct stack_trace *trace = data->trace; |
| 47 | unsigned long addr = frame->lr; | 72 | unsigned long addr = frame->pc; |
| 48 | 73 | ||
| 49 | if (data->no_sched_functions && in_sched_functions(addr)) | 74 | if (data->no_sched_functions && in_sched_functions(addr)) |
| 50 | return 0; | 75 | return 0; |
| @@ -61,11 +86,10 @@ static int save_trace(struct stackframe *frame, void *d) | |||
| 61 | void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) | 86 | void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) |
| 62 | { | 87 | { |
| 63 | struct stack_trace_data data; | 88 | struct stack_trace_data data; |
| 64 | unsigned long fp, base; | 89 | struct stackframe frame; |
| 65 | 90 | ||
| 66 | data.trace = trace; | 91 | data.trace = trace; |
| 67 | data.skip = trace->skip; | 92 | data.skip = trace->skip; |
| 68 | base = (unsigned long)task_stack_page(tsk); | ||
| 69 | 93 | ||
| 70 | if (tsk != current) { | 94 | if (tsk != current) { |
| 71 | #ifdef CONFIG_SMP | 95 | #ifdef CONFIG_SMP |
| @@ -76,14 +100,22 @@ void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace) | |||
| 76 | BUG(); | 100 | BUG(); |
| 77 | #else | 101 | #else |
| 78 | data.no_sched_functions = 1; | 102 | data.no_sched_functions = 1; |
| 79 | fp = thread_saved_fp(tsk); | 103 | frame.fp = thread_saved_fp(tsk); |
| 104 | frame.sp = thread_saved_sp(tsk); | ||
| 105 | frame.lr = 0; /* recovered from the stack */ | ||
| 106 | frame.pc = thread_saved_pc(tsk); | ||
| 80 | #endif | 107 | #endif |
| 81 | } else { | 108 | } else { |
| 109 | register unsigned long current_sp asm ("sp"); | ||
| 110 | |||
| 82 | data.no_sched_functions = 0; | 111 | data.no_sched_functions = 0; |
| 83 | asm("mov %0, fp" : "=r" (fp)); | 112 | frame.fp = (unsigned long)__builtin_frame_address(0); |
| 113 | frame.sp = current_sp; | ||
| 114 | frame.lr = (unsigned long)__builtin_return_address(0); | ||
| 115 | frame.pc = (unsigned long)save_stack_trace_tsk; | ||
| 84 | } | 116 | } |
| 85 | 117 | ||
| 86 | walk_stackframe(fp, base, base + THREAD_SIZE, save_trace, &data); | 118 | walk_stackframe(&frame, save_trace, &data); |
| 87 | if (trace->nr_entries < trace->max_entries) | 119 | if (trace->nr_entries < trace->max_entries) |
| 88 | trace->entries[trace->nr_entries++] = ULONG_MAX; | 120 | trace->entries[trace->nr_entries++] = ULONG_MAX; |
| 89 | } | 121 | } |
diff --git a/arch/arm/kernel/stacktrace.h b/arch/arm/kernel/stacktrace.h deleted file mode 100644 index e9fd20cb5662..000000000000 --- a/arch/arm/kernel/stacktrace.h +++ /dev/null | |||
| @@ -1,9 +0,0 @@ | |||
| 1 | struct stackframe { | ||
| 2 | unsigned long fp; | ||
| 3 | unsigned long sp; | ||
| 4 | unsigned long lr; | ||
| 5 | unsigned long pc; | ||
| 6 | }; | ||
| 7 | |||
| 8 | int walk_stackframe(unsigned long fp, unsigned long low, unsigned long high, | ||
| 9 | int (*fn)(struct stackframe *, void *), void *data); | ||
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index c68b44aa88d2..4cdc4a0bd02d 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | 33 | ||
| 34 | #include <asm/leds.h> | 34 | #include <asm/leds.h> |
| 35 | #include <asm/thread_info.h> | 35 | #include <asm/thread_info.h> |
| 36 | #include <asm/stacktrace.h> | ||
| 36 | #include <asm/mach/time.h> | 37 | #include <asm/mach/time.h> |
| 37 | 38 | ||
| 38 | /* | 39 | /* |
| @@ -55,14 +56,22 @@ EXPORT_SYMBOL(rtc_lock); | |||
| 55 | #ifdef CONFIG_SMP | 56 | #ifdef CONFIG_SMP |
| 56 | unsigned long profile_pc(struct pt_regs *regs) | 57 | unsigned long profile_pc(struct pt_regs *regs) |
| 57 | { | 58 | { |
| 58 | unsigned long fp, pc = instruction_pointer(regs); | 59 | struct stackframe frame; |
| 59 | 60 | ||
| 60 | if (in_lock_functions(pc)) { | 61 | if (!in_lock_functions(regs->ARM_pc)) |
| 61 | fp = regs->ARM_fp; | 62 | return regs->ARM_pc; |
| 62 | pc = ((unsigned long *)fp)[-1]; | 63 | |
| 63 | } | 64 | frame.fp = regs->ARM_fp; |
| 65 | frame.sp = regs->ARM_sp; | ||
| 66 | frame.lr = regs->ARM_lr; | ||
| 67 | frame.pc = regs->ARM_pc; | ||
| 68 | do { | ||
| 69 | int ret = unwind_frame(&frame); | ||
| 70 | if (ret < 0) | ||
| 71 | return 0; | ||
| 72 | } while (in_lock_functions(frame.pc)); | ||
| 64 | 73 | ||
| 65 | return pc; | 74 | return frame.pc; |
| 66 | } | 75 | } |
| 67 | EXPORT_SYMBOL(profile_pc); | 76 | EXPORT_SYMBOL(profile_pc); |
| 68 | #endif | 77 | #endif |
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index 79abc4ddc0cf..57eb0f6f6005 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c | |||
| @@ -27,6 +27,7 @@ | |||
| 27 | #include <asm/system.h> | 27 | #include <asm/system.h> |
| 28 | #include <asm/unistd.h> | 28 | #include <asm/unistd.h> |
| 29 | #include <asm/traps.h> | 29 | #include <asm/traps.h> |
| 30 | #include <asm/unwind.h> | ||
| 30 | 31 | ||
| 31 | #include "ptrace.h" | 32 | #include "ptrace.h" |
| 32 | #include "signal.h" | 33 | #include "signal.h" |
| @@ -61,6 +62,7 @@ void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long | |||
| 61 | dump_mem("Exception stack", frame + 4, frame + 4 + sizeof(struct pt_regs)); | 62 | dump_mem("Exception stack", frame + 4, frame + 4 + sizeof(struct pt_regs)); |
| 62 | } | 63 | } |
| 63 | 64 | ||
| 65 | #ifndef CONFIG_ARM_UNWIND | ||
| 64 | /* | 66 | /* |
| 65 | * Stack pointers should always be within the kernels view of | 67 | * Stack pointers should always be within the kernels view of |
| 66 | * physical memory. If it is not there, then we can't dump | 68 | * physical memory. If it is not there, then we can't dump |
| @@ -74,6 +76,7 @@ static int verify_stack(unsigned long sp) | |||
| 74 | 76 | ||
| 75 | return 0; | 77 | return 0; |
| 76 | } | 78 | } |
| 79 | #endif | ||
| 77 | 80 | ||
| 78 | /* | 81 | /* |
| 79 | * Dump out the contents of some memory nicely... | 82 | * Dump out the contents of some memory nicely... |
| @@ -150,13 +153,33 @@ static void dump_instr(struct pt_regs *regs) | |||
| 150 | set_fs(fs); | 153 | set_fs(fs); |
| 151 | } | 154 | } |
| 152 | 155 | ||
| 156 | #ifdef CONFIG_ARM_UNWIND | ||
| 157 | static inline void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) | ||
| 158 | { | ||
| 159 | unwind_backtrace(regs, tsk); | ||
| 160 | } | ||
| 161 | #else | ||
| 153 | static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) | 162 | static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) |
| 154 | { | 163 | { |
| 155 | unsigned int fp; | 164 | unsigned int fp, mode; |
| 156 | int ok = 1; | 165 | int ok = 1; |
| 157 | 166 | ||
| 158 | printk("Backtrace: "); | 167 | printk("Backtrace: "); |
| 159 | fp = regs->ARM_fp; | 168 | |
| 169 | if (!tsk) | ||
| 170 | tsk = current; | ||
| 171 | |||
| 172 | if (regs) { | ||
| 173 | fp = regs->ARM_fp; | ||
| 174 | mode = processor_mode(regs); | ||
| 175 | } else if (tsk != current) { | ||
| 176 | fp = thread_saved_fp(tsk); | ||
| 177 | mode = 0x10; | ||
| 178 | } else { | ||
| 179 | asm("mov %0, fp" : "=r" (fp) : : "cc"); | ||
| 180 | mode = 0x10; | ||
| 181 | } | ||
| 182 | |||
| 160 | if (!fp) { | 183 | if (!fp) { |
| 161 | printk("no frame pointer"); | 184 | printk("no frame pointer"); |
| 162 | ok = 0; | 185 | ok = 0; |
| @@ -168,29 +191,20 @@ static void dump_backtrace(struct pt_regs *regs, struct task_struct *tsk) | |||
| 168 | printk("\n"); | 191 | printk("\n"); |
| 169 | 192 | ||
| 170 | if (ok) | 193 | if (ok) |
| 171 | c_backtrace(fp, processor_mode(regs)); | 194 | c_backtrace(fp, mode); |
| 172 | } | 195 | } |
| 196 | #endif | ||
| 173 | 197 | ||
| 174 | void dump_stack(void) | 198 | void dump_stack(void) |
| 175 | { | 199 | { |
| 176 | __backtrace(); | 200 | dump_backtrace(NULL, NULL); |
| 177 | } | 201 | } |
| 178 | 202 | ||
| 179 | EXPORT_SYMBOL(dump_stack); | 203 | EXPORT_SYMBOL(dump_stack); |
| 180 | 204 | ||
| 181 | void show_stack(struct task_struct *tsk, unsigned long *sp) | 205 | void show_stack(struct task_struct *tsk, unsigned long *sp) |
| 182 | { | 206 | { |
| 183 | unsigned long fp; | 207 | dump_backtrace(NULL, tsk); |
| 184 | |||
| 185 | if (!tsk) | ||
| 186 | tsk = current; | ||
| 187 | |||
| 188 | if (tsk != current) | ||
| 189 | fp = thread_saved_fp(tsk); | ||
| 190 | else | ||
| 191 | asm("mov %0, fp" : "=r" (fp) : : "cc"); | ||
| 192 | |||
| 193 | c_backtrace(fp, 0x10); | ||
| 194 | barrier(); | 208 | barrier(); |
| 195 | } | 209 | } |
| 196 | 210 | ||
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c new file mode 100644 index 000000000000..1dedc2c7ff49 --- /dev/null +++ b/arch/arm/kernel/unwind.c | |||
| @@ -0,0 +1,434 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/kernel/unwind.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 18 | * | ||
| 19 | * | ||
| 20 | * Stack unwinding support for ARM | ||
| 21 | * | ||
| 22 | * An ARM EABI version of gcc is required to generate the unwind | ||
| 23 | * tables. For information about the structure of the unwind tables, | ||
| 24 | * see "Exception Handling ABI for the ARM Architecture" at: | ||
| 25 | * | ||
| 26 | * http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html | ||
| 27 | */ | ||
| 28 | |||
| 29 | #include <linux/kernel.h> | ||
| 30 | #include <linux/init.h> | ||
| 31 | #include <linux/module.h> | ||
| 32 | #include <linux/sched.h> | ||
| 33 | #include <linux/slab.h> | ||
| 34 | #include <linux/spinlock.h> | ||
| 35 | #include <linux/list.h> | ||
| 36 | |||
| 37 | #include <asm/stacktrace.h> | ||
| 38 | #include <asm/traps.h> | ||
| 39 | #include <asm/unwind.h> | ||
| 40 | |||
| 41 | /* Dummy functions to avoid linker complaints */ | ||
| 42 | void __aeabi_unwind_cpp_pr0(void) | ||
| 43 | { | ||
| 44 | }; | ||
| 45 | EXPORT_SYMBOL(__aeabi_unwind_cpp_pr0); | ||
| 46 | |||
| 47 | void __aeabi_unwind_cpp_pr1(void) | ||
| 48 | { | ||
| 49 | }; | ||
| 50 | EXPORT_SYMBOL(__aeabi_unwind_cpp_pr1); | ||
| 51 | |||
| 52 | void __aeabi_unwind_cpp_pr2(void) | ||
| 53 | { | ||
| 54 | }; | ||
| 55 | EXPORT_SYMBOL(__aeabi_unwind_cpp_pr2); | ||
| 56 | |||
| 57 | struct unwind_ctrl_block { | ||
| 58 | unsigned long vrs[16]; /* virtual register set */ | ||
| 59 | unsigned long *insn; /* pointer to the current instructions word */ | ||
| 60 | int entries; /* number of entries left to interpret */ | ||
| 61 | int byte; /* current byte number in the instructions word */ | ||
| 62 | }; | ||
| 63 | |||
| 64 | enum regs { | ||
| 65 | FP = 11, | ||
| 66 | SP = 13, | ||
| 67 | LR = 14, | ||
| 68 | PC = 15 | ||
| 69 | }; | ||
| 70 | |||
| 71 | extern struct unwind_idx __start_unwind_idx[]; | ||
| 72 | extern struct unwind_idx __stop_unwind_idx[]; | ||
| 73 | |||
| 74 | static DEFINE_SPINLOCK(unwind_lock); | ||
| 75 | static LIST_HEAD(unwind_tables); | ||
| 76 | |||
| 77 | /* Convert a prel31 symbol to an absolute address */ | ||
| 78 | #define prel31_to_addr(ptr) \ | ||
| 79 | ({ \ | ||
| 80 | /* sign-extend to 32 bits */ \ | ||
| 81 | long offset = (((long)*(ptr)) << 1) >> 1; \ | ||
| 82 | (unsigned long)(ptr) + offset; \ | ||
| 83 | }) | ||
| 84 | |||
| 85 | /* | ||
| 86 | * Binary search in the unwind index. The entries entries are | ||
| 87 | * guaranteed to be sorted in ascending order by the linker. | ||
| 88 | */ | ||
| 89 | static struct unwind_idx *search_index(unsigned long addr, | ||
| 90 | struct unwind_idx *first, | ||
| 91 | struct unwind_idx *last) | ||
| 92 | { | ||
| 93 | pr_debug("%s(%08lx, %p, %p)\n", __func__, addr, first, last); | ||
| 94 | |||
| 95 | if (addr < first->addr) { | ||
| 96 | pr_warning("unwind: Unknown symbol address %08lx\n", addr); | ||
| 97 | return NULL; | ||
| 98 | } else if (addr >= last->addr) | ||
| 99 | return last; | ||
| 100 | |||
| 101 | while (first < last - 1) { | ||
| 102 | struct unwind_idx *mid = first + ((last - first + 1) >> 1); | ||
| 103 | |||
| 104 | if (addr < mid->addr) | ||
| 105 | last = mid; | ||
| 106 | else | ||
| 107 | first = mid; | ||
| 108 | } | ||
| 109 | |||
| 110 | return first; | ||
| 111 | } | ||
| 112 | |||
| 113 | static struct unwind_idx *unwind_find_idx(unsigned long addr) | ||
| 114 | { | ||
| 115 | struct unwind_idx *idx = NULL; | ||
| 116 | unsigned long flags; | ||
| 117 | |||
| 118 | pr_debug("%s(%08lx)\n", __func__, addr); | ||
| 119 | |||
| 120 | if (core_kernel_text(addr)) | ||
| 121 | /* main unwind table */ | ||
| 122 | idx = search_index(addr, __start_unwind_idx, | ||
| 123 | __stop_unwind_idx - 1); | ||
| 124 | else { | ||
| 125 | /* module unwind tables */ | ||
| 126 | struct unwind_table *table; | ||
| 127 | |||
| 128 | spin_lock_irqsave(&unwind_lock, flags); | ||
| 129 | list_for_each_entry(table, &unwind_tables, list) { | ||
| 130 | if (addr >= table->begin_addr && | ||
| 131 | addr < table->end_addr) { | ||
| 132 | idx = search_index(addr, table->start, | ||
| 133 | table->stop - 1); | ||
| 134 | break; | ||
| 135 | } | ||
| 136 | } | ||
| 137 | spin_unlock_irqrestore(&unwind_lock, flags); | ||
| 138 | } | ||
| 139 | |||
| 140 | pr_debug("%s: idx = %p\n", __func__, idx); | ||
| 141 | return idx; | ||
| 142 | } | ||
| 143 | |||
| 144 | static unsigned long unwind_get_byte(struct unwind_ctrl_block *ctrl) | ||
| 145 | { | ||
| 146 | unsigned long ret; | ||
| 147 | |||
| 148 | if (ctrl->entries <= 0) { | ||
| 149 | pr_warning("unwind: Corrupt unwind table\n"); | ||
| 150 | return 0; | ||
| 151 | } | ||
| 152 | |||
| 153 | ret = (*ctrl->insn >> (ctrl->byte * 8)) & 0xff; | ||
| 154 | |||
| 155 | if (ctrl->byte == 0) { | ||
| 156 | ctrl->insn++; | ||
| 157 | ctrl->entries--; | ||
| 158 | ctrl->byte = 3; | ||
| 159 | } else | ||
| 160 | ctrl->byte--; | ||
| 161 | |||
| 162 | return ret; | ||
| 163 | } | ||
| 164 | |||
| 165 | /* | ||
| 166 | * Execute the current unwind instruction. | ||
| 167 | */ | ||
| 168 | static int unwind_exec_insn(struct unwind_ctrl_block *ctrl) | ||
| 169 | { | ||
| 170 | unsigned long insn = unwind_get_byte(ctrl); | ||
| 171 | |||
| 172 | pr_debug("%s: insn = %08lx\n", __func__, insn); | ||
| 173 | |||
| 174 | if ((insn & 0xc0) == 0x00) | ||
| 175 | ctrl->vrs[SP] += ((insn & 0x3f) << 2) + 4; | ||
| 176 | else if ((insn & 0xc0) == 0x40) | ||
| 177 | ctrl->vrs[SP] -= ((insn & 0x3f) << 2) + 4; | ||
| 178 | else if ((insn & 0xf0) == 0x80) { | ||
| 179 | unsigned long mask; | ||
| 180 | unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; | ||
| 181 | int load_sp, reg = 4; | ||
| 182 | |||
| 183 | insn = (insn << 8) | unwind_get_byte(ctrl); | ||
| 184 | mask = insn & 0x0fff; | ||
| 185 | if (mask == 0) { | ||
| 186 | pr_warning("unwind: 'Refuse to unwind' instruction %04lx\n", | ||
| 187 | insn); | ||
| 188 | return -URC_FAILURE; | ||
| 189 | } | ||
| 190 | |||
| 191 | /* pop R4-R15 according to mask */ | ||
| 192 | load_sp = mask & (1 << (13 - 4)); | ||
| 193 | while (mask) { | ||
| 194 | if (mask & 1) | ||
| 195 | ctrl->vrs[reg] = *vsp++; | ||
| 196 | mask >>= 1; | ||
| 197 | reg++; | ||
| 198 | } | ||
| 199 | if (!load_sp) | ||
| 200 | ctrl->vrs[SP] = (unsigned long)vsp; | ||
| 201 | } else if ((insn & 0xf0) == 0x90 && | ||
| 202 | (insn & 0x0d) != 0x0d) | ||
| 203 | ctrl->vrs[SP] = ctrl->vrs[insn & 0x0f]; | ||
| 204 | else if ((insn & 0xf0) == 0xa0) { | ||
| 205 | unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; | ||
| 206 | int reg; | ||
| 207 | |||
| 208 | /* pop R4-R[4+bbb] */ | ||
| 209 | for (reg = 4; reg <= 4 + (insn & 7); reg++) | ||
| 210 | ctrl->vrs[reg] = *vsp++; | ||
| 211 | if (insn & 0x80) | ||
| 212 | ctrl->vrs[14] = *vsp++; | ||
| 213 | ctrl->vrs[SP] = (unsigned long)vsp; | ||
| 214 | } else if (insn == 0xb0) { | ||
| 215 | ctrl->vrs[PC] = ctrl->vrs[LR]; | ||
| 216 | /* no further processing */ | ||
| 217 | ctrl->entries = 0; | ||
| 218 | } else if (insn == 0xb1) { | ||
| 219 | unsigned long mask = unwind_get_byte(ctrl); | ||
| 220 | unsigned long *vsp = (unsigned long *)ctrl->vrs[SP]; | ||
| 221 | int reg = 0; | ||
| 222 | |||
| 223 | if (mask == 0 || mask & 0xf0) { | ||
| 224 | pr_warning("unwind: Spare encoding %04lx\n", | ||
| 225 | (insn << 8) | mask); | ||
| 226 | return -URC_FAILURE; | ||
| 227 | } | ||
| 228 | |||
| 229 | /* pop R0-R3 according to mask */ | ||
| 230 | while (mask) { | ||
| 231 | if (mask & 1) | ||
| 232 | ctrl->vrs[reg] = *vsp++; | ||
| 233 | mask >>= 1; | ||
| 234 | reg++; | ||
| 235 | } | ||
| 236 | ctrl->vrs[SP] = (unsigned long)vsp; | ||
| 237 | } else if (insn == 0xb2) { | ||
| 238 | unsigned long uleb128 = unwind_get_byte(ctrl); | ||
| 239 | |||
| 240 | ctrl->vrs[SP] += 0x204 + (uleb128 << 2); | ||
| 241 | } else { | ||
| 242 | pr_warning("unwind: Unhandled instruction %02lx\n", insn); | ||
| 243 | return -URC_FAILURE; | ||
| 244 | } | ||
| 245 | |||
| 246 | pr_debug("%s: fp = %08lx sp = %08lx lr = %08lx pc = %08lx\n", __func__, | ||
| 247 | ctrl->vrs[FP], ctrl->vrs[SP], ctrl->vrs[LR], ctrl->vrs[PC]); | ||
| 248 | |||
| 249 | return URC_OK; | ||
| 250 | } | ||
| 251 | |||
| 252 | /* | ||
| 253 | * Unwind a single frame starting with *sp for the symbol at *pc. It | ||
| 254 | * updates the *pc and *sp with the new values. | ||
| 255 | */ | ||
| 256 | int unwind_frame(struct stackframe *frame) | ||
| 257 | { | ||
| 258 | unsigned long high, low; | ||
| 259 | struct unwind_idx *idx; | ||
| 260 | struct unwind_ctrl_block ctrl; | ||
| 261 | |||
| 262 | /* only go to a higher address on the stack */ | ||
| 263 | low = frame->sp; | ||
| 264 | high = ALIGN(low, THREAD_SIZE) + THREAD_SIZE; | ||
| 265 | |||
| 266 | pr_debug("%s(pc = %08lx lr = %08lx sp = %08lx)\n", __func__, | ||
| 267 | frame->pc, frame->lr, frame->sp); | ||
| 268 | |||
| 269 | if (!kernel_text_address(frame->pc)) | ||
| 270 | return -URC_FAILURE; | ||
| 271 | |||
| 272 | idx = unwind_find_idx(frame->pc); | ||
| 273 | if (!idx) { | ||
| 274 | pr_warning("unwind: Index not found %08lx\n", frame->pc); | ||
| 275 | return -URC_FAILURE; | ||
| 276 | } | ||
| 277 | |||
| 278 | ctrl.vrs[FP] = frame->fp; | ||
| 279 | ctrl.vrs[SP] = frame->sp; | ||
| 280 | ctrl.vrs[LR] = frame->lr; | ||
| 281 | ctrl.vrs[PC] = 0; | ||
| 282 | |||
| 283 | if (idx->insn == 1) | ||
| 284 | /* can't unwind */ | ||
| 285 | return -URC_FAILURE; | ||
| 286 | else if ((idx->insn & 0x80000000) == 0) | ||
| 287 | /* prel31 to the unwind table */ | ||
| 288 | ctrl.insn = (unsigned long *)prel31_to_addr(&idx->insn); | ||
| 289 | else if ((idx->insn & 0xff000000) == 0x80000000) | ||
| 290 | /* only personality routine 0 supported in the index */ | ||
| 291 | ctrl.insn = &idx->insn; | ||
| 292 | else { | ||
| 293 | pr_warning("unwind: Unsupported personality routine %08lx in the index at %p\n", | ||
| 294 | idx->insn, idx); | ||
| 295 | return -URC_FAILURE; | ||
| 296 | } | ||
| 297 | |||
| 298 | /* check the personality routine */ | ||
| 299 | if ((*ctrl.insn & 0xff000000) == 0x80000000) { | ||
| 300 | ctrl.byte = 2; | ||
| 301 | ctrl.entries = 1; | ||
| 302 | } else if ((*ctrl.insn & 0xff000000) == 0x81000000) { | ||
| 303 | ctrl.byte = 1; | ||
| 304 | ctrl.entries = 1 + ((*ctrl.insn & 0x00ff0000) >> 16); | ||
| 305 | } else { | ||
| 306 | pr_warning("unwind: Unsupported personality routine %08lx at %p\n", | ||
| 307 | *ctrl.insn, ctrl.insn); | ||
| 308 | return -URC_FAILURE; | ||
| 309 | } | ||
| 310 | |||
| 311 | while (ctrl.entries > 0) { | ||
| 312 | int urc; | ||
| 313 | |||
| 314 | if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high) | ||
| 315 | return -URC_FAILURE; | ||
| 316 | urc = unwind_exec_insn(&ctrl); | ||
| 317 | if (urc < 0) | ||
| 318 | return urc; | ||
| 319 | } | ||
| 320 | |||
| 321 | if (ctrl.vrs[PC] == 0) | ||
| 322 | ctrl.vrs[PC] = ctrl.vrs[LR]; | ||
| 323 | |||
| 324 | frame->fp = ctrl.vrs[FP]; | ||
| 325 | frame->sp = ctrl.vrs[SP]; | ||
| 326 | frame->lr = ctrl.vrs[LR]; | ||
| 327 | frame->pc = ctrl.vrs[PC]; | ||
| 328 | |||
| 329 | return URC_OK; | ||
| 330 | } | ||
| 331 | |||
| 332 | void unwind_backtrace(struct pt_regs *regs, struct task_struct *tsk) | ||
| 333 | { | ||
| 334 | struct stackframe frame; | ||
| 335 | unsigned long high, low; | ||
| 336 | register unsigned long current_sp asm ("sp"); | ||
| 337 | |||
| 338 | pr_debug("%s(regs = %p tsk = %p)\n", __func__, regs, tsk); | ||
| 339 | |||
| 340 | if (!tsk) | ||
| 341 | tsk = current; | ||
| 342 | |||
| 343 | if (regs) { | ||
| 344 | frame.fp = regs->ARM_fp; | ||
| 345 | frame.sp = regs->ARM_sp; | ||
| 346 | frame.lr = regs->ARM_lr; | ||
| 347 | frame.pc = regs->ARM_pc; | ||
| 348 | } else if (tsk == current) { | ||
| 349 | frame.fp = (unsigned long)__builtin_frame_address(0); | ||
| 350 | frame.sp = current_sp; | ||
| 351 | frame.lr = (unsigned long)__builtin_return_address(0); | ||
| 352 | frame.pc = (unsigned long)unwind_backtrace; | ||
| 353 | } else { | ||
| 354 | /* task blocked in __switch_to */ | ||
| 355 | frame.fp = thread_saved_fp(tsk); | ||
| 356 | frame.sp = thread_saved_sp(tsk); | ||
| 357 | /* | ||
| 358 | * The function calling __switch_to cannot be a leaf function | ||
| 359 | * so LR is recovered from the stack. | ||
| 360 | */ | ||
| 361 | frame.lr = 0; | ||
| 362 | frame.pc = thread_saved_pc(tsk); | ||
| 363 | } | ||
| 364 | |||
| 365 | low = frame.sp & ~(THREAD_SIZE - 1); | ||
| 366 | high = low + THREAD_SIZE; | ||
| 367 | |||
| 368 | while (1) { | ||
| 369 | int urc; | ||
| 370 | unsigned long where = frame.pc; | ||
| 371 | |||
| 372 | urc = unwind_frame(&frame); | ||
| 373 | if (urc < 0) | ||
| 374 | break; | ||
| 375 | dump_backtrace_entry(where, frame.pc, frame.sp - 4); | ||
| 376 | } | ||
| 377 | } | ||
| 378 | |||
| 379 | struct unwind_table *unwind_table_add(unsigned long start, unsigned long size, | ||
| 380 | unsigned long text_addr, | ||
| 381 | unsigned long text_size) | ||
| 382 | { | ||
| 383 | unsigned long flags; | ||
| 384 | struct unwind_idx *idx; | ||
| 385 | struct unwind_table *tab = kmalloc(sizeof(*tab), GFP_KERNEL); | ||
| 386 | |||
| 387 | pr_debug("%s(%08lx, %08lx, %08lx, %08lx)\n", __func__, start, size, | ||
| 388 | text_addr, text_size); | ||
| 389 | |||
| 390 | if (!tab) | ||
| 391 | return tab; | ||
| 392 | |||
| 393 | tab->start = (struct unwind_idx *)start; | ||
| 394 | tab->stop = (struct unwind_idx *)(start + size); | ||
| 395 | tab->begin_addr = text_addr; | ||
| 396 | tab->end_addr = text_addr + text_size; | ||
| 397 | |||
| 398 | /* Convert the symbol addresses to absolute values */ | ||
| 399 | for (idx = tab->start; idx < tab->stop; idx++) | ||
| 400 | idx->addr = prel31_to_addr(&idx->addr); | ||
| 401 | |||
| 402 | spin_lock_irqsave(&unwind_lock, flags); | ||
| 403 | list_add_tail(&tab->list, &unwind_tables); | ||
| 404 | spin_unlock_irqrestore(&unwind_lock, flags); | ||
| 405 | |||
| 406 | return tab; | ||
| 407 | } | ||
| 408 | |||
| 409 | void unwind_table_del(struct unwind_table *tab) | ||
| 410 | { | ||
| 411 | unsigned long flags; | ||
| 412 | |||
| 413 | if (!tab) | ||
| 414 | return; | ||
| 415 | |||
| 416 | spin_lock_irqsave(&unwind_lock, flags); | ||
| 417 | list_del(&tab->list); | ||
| 418 | spin_unlock_irqrestore(&unwind_lock, flags); | ||
| 419 | |||
| 420 | kfree(tab); | ||
| 421 | } | ||
| 422 | |||
| 423 | int __init unwind_init(void) | ||
| 424 | { | ||
| 425 | struct unwind_idx *idx; | ||
| 426 | |||
| 427 | /* Convert the symbol addresses to absolute values */ | ||
| 428 | for (idx = __start_unwind_idx; idx < __stop_unwind_idx; idx++) | ||
| 429 | idx->addr = prel31_to_addr(&idx->addr); | ||
| 430 | |||
| 431 | pr_debug("unwind: ARM stack unwinding initialised\n"); | ||
| 432 | |||
| 433 | return 0; | ||
| 434 | } | ||
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index 00216071eaf7..5f664599c945 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S | |||
| @@ -80,6 +80,8 @@ SECTIONS | |||
| 80 | EXIT_TEXT | 80 | EXIT_TEXT |
| 81 | EXIT_DATA | 81 | EXIT_DATA |
| 82 | *(.exitcall.exit) | 82 | *(.exitcall.exit) |
| 83 | *(.ARM.exidx.exit.text) | ||
| 84 | *(.ARM.extab.exit.text) | ||
| 83 | #ifndef CONFIG_MMU | 85 | #ifndef CONFIG_MMU |
| 84 | *(.fixup) | 86 | *(.fixup) |
| 85 | *(__ex_table) | 87 | *(__ex_table) |
| @@ -110,6 +112,23 @@ SECTIONS | |||
| 110 | 112 | ||
| 111 | _etext = .; /* End of text and rodata section */ | 113 | _etext = .; /* End of text and rodata section */ |
| 112 | 114 | ||
| 115 | #ifdef CONFIG_ARM_UNWIND | ||
| 116 | /* | ||
| 117 | * Stack unwinding tables | ||
| 118 | */ | ||
| 119 | . = ALIGN(8); | ||
| 120 | .ARM.unwind_idx : { | ||
| 121 | __start_unwind_idx = .; | ||
| 122 | *(.ARM.exidx*) | ||
| 123 | __stop_unwind_idx = .; | ||
| 124 | } | ||
| 125 | .ARM.unwind_tab : { | ||
| 126 | __start_unwind_tab = .; | ||
| 127 | *(.ARM.extab*) | ||
| 128 | __stop_unwind_tab = .; | ||
| 129 | } | ||
| 130 | #endif | ||
| 131 | |||
| 113 | #ifdef CONFIG_XIP_KERNEL | 132 | #ifdef CONFIG_XIP_KERNEL |
| 114 | __data_loc = ALIGN(4); /* location in binary */ | 133 | __data_loc = ALIGN(4); /* location in binary */ |
| 115 | . = PAGE_OFFSET + TEXT_OFFSET; | 134 | . = PAGE_OFFSET + TEXT_OFFSET; |
diff --git a/arch/arm/mach-aaec2000/include/mach/system.h b/arch/arm/mach-aaec2000/include/mach/system.h index 8f4115d734ce..fe08ca1add6f 100644 --- a/arch/arm/mach-aaec2000/include/mach/system.h +++ b/arch/arm/mach-aaec2000/include/mach/system.h | |||
| @@ -16,7 +16,7 @@ static inline void arch_idle(void) | |||
| 16 | cpu_do_idle(); | 16 | cpu_do_idle(); |
| 17 | } | 17 | } |
| 18 | 18 | ||
| 19 | static inline void arch_reset(char mode) | 19 | static inline void arch_reset(char mode, const char *cmd) |
| 20 | { | 20 | { |
| 21 | cpu_reset(0); | 21 | cpu_reset(0); |
| 22 | } | 22 | } |
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c index 134af97ff340..b7f233242315 100644 --- a/arch/arm/mach-at91/at91sam9263_devices.c +++ b/arch/arm/mach-at91/at91sam9263_devices.c | |||
| @@ -347,6 +347,111 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) | |||
| 347 | void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} | 347 | void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {} |
| 348 | #endif | 348 | #endif |
| 349 | 349 | ||
| 350 | /* -------------------------------------------------------------------- | ||
| 351 | * Compact Flash (PCMCIA or IDE) | ||
| 352 | * -------------------------------------------------------------------- */ | ||
| 353 | |||
| 354 | #if defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE) || \ | ||
| 355 | defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) | ||
| 356 | |||
| 357 | static struct at91_cf_data cf0_data; | ||
| 358 | |||
| 359 | static struct resource cf0_resources[] = { | ||
| 360 | [0] = { | ||
| 361 | .start = AT91_CHIPSELECT_4, | ||
| 362 | .end = AT91_CHIPSELECT_4 + SZ_256M - 1, | ||
| 363 | .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT, | ||
| 364 | } | ||
| 365 | }; | ||
| 366 | |||
| 367 | static struct platform_device cf0_device = { | ||
| 368 | .id = 0, | ||
| 369 | .dev = { | ||
| 370 | .platform_data = &cf0_data, | ||
| 371 | }, | ||
| 372 | .resource = cf0_resources, | ||
| 373 | .num_resources = ARRAY_SIZE(cf0_resources), | ||
| 374 | }; | ||
| 375 | |||
| 376 | static struct at91_cf_data cf1_data; | ||
| 377 | |||
| 378 | static struct resource cf1_resources[] = { | ||
| 379 | [0] = { | ||
| 380 | .start = AT91_CHIPSELECT_5, | ||
| 381 | .end = AT91_CHIPSELECT_5 + SZ_256M - 1, | ||
| 382 | .flags = IORESOURCE_MEM | IORESOURCE_MEM_8AND16BIT, | ||
| 383 | } | ||
| 384 | }; | ||
| 385 | |||
| 386 | static struct platform_device cf1_device = { | ||
| 387 | .id = 1, | ||
| 388 | .dev = { | ||
| 389 | .platform_data = &cf1_data, | ||
| 390 | }, | ||
| 391 | .resource = cf1_resources, | ||
| 392 | .num_resources = ARRAY_SIZE(cf1_resources), | ||
| 393 | }; | ||
| 394 | |||
| 395 | void __init at91_add_device_cf(struct at91_cf_data *data) | ||
| 396 | { | ||
| 397 | unsigned long ebi0_csa; | ||
| 398 | struct platform_device *pdev; | ||
| 399 | |||
| 400 | if (!data) | ||
| 401 | return; | ||
| 402 | |||
| 403 | /* | ||
| 404 | * assign CS4 or CS5 to SMC with Compact Flash logic support, | ||
| 405 | * we assume SMC timings are configured by board code, | ||
| 406 | * except True IDE where timings are controlled by driver | ||
| 407 | */ | ||
| 408 | ebi0_csa = at91_sys_read(AT91_MATRIX_EBI0CSA); | ||
| 409 | switch (data->chipselect) { | ||
| 410 | case 4: | ||
| 411 | at91_set_A_periph(AT91_PIN_PD6, 0); /* EBI0_NCS4/CFCS0 */ | ||
| 412 | ebi0_csa |= AT91_MATRIX_EBI0_CS4A_SMC_CF1; | ||
| 413 | cf0_data = *data; | ||
| 414 | pdev = &cf0_device; | ||
| 415 | break; | ||
| 416 | case 5: | ||
| 417 | at91_set_A_periph(AT91_PIN_PD7, 0); /* EBI0_NCS5/CFCS1 */ | ||
| 418 | ebi0_csa |= AT91_MATRIX_EBI0_CS5A_SMC_CF2; | ||
| 419 | cf1_data = *data; | ||
| 420 | pdev = &cf1_device; | ||
| 421 | break; | ||
| 422 | default: | ||
| 423 | printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n", | ||
| 424 | data->chipselect); | ||
| 425 | return; | ||
| 426 | } | ||
| 427 | at91_sys_write(AT91_MATRIX_EBI0CSA, ebi0_csa); | ||
| 428 | |||
| 429 | if (data->det_pin) { | ||
| 430 | at91_set_gpio_input(data->det_pin, 1); | ||
| 431 | at91_set_deglitch(data->det_pin, 1); | ||
| 432 | } | ||
| 433 | |||
| 434 | if (data->irq_pin) { | ||
| 435 | at91_set_gpio_input(data->irq_pin, 1); | ||
| 436 | at91_set_deglitch(data->irq_pin, 1); | ||
| 437 | } | ||
| 438 | |||
| 439 | if (data->vcc_pin) | ||
| 440 | /* initially off */ | ||
| 441 | at91_set_gpio_output(data->vcc_pin, 0); | ||
| 442 | |||
| 443 | /* enable EBI controlled pins */ | ||
| 444 | at91_set_A_periph(AT91_PIN_PD5, 1); /* NWAIT */ | ||
| 445 | at91_set_A_periph(AT91_PIN_PD8, 0); /* CFCE1 */ | ||
| 446 | at91_set_A_periph(AT91_PIN_PD9, 0); /* CFCE2 */ | ||
| 447 | at91_set_A_periph(AT91_PIN_PD14, 0); /* CFNRW */ | ||
| 448 | |||
| 449 | pdev->name = (data->flags & AT91_CF_TRUE_IDE) ? "at91_ide" : "at91_cf"; | ||
| 450 | platform_device_register(pdev); | ||
| 451 | } | ||
| 452 | #else | ||
| 453 | void __init at91_add_device_cf(struct at91_cf_data *data) {} | ||
| 454 | #endif | ||
| 350 | 455 | ||
| 351 | /* -------------------------------------------------------------------- | 456 | /* -------------------------------------------------------------------- |
| 352 | * NAND / SmartMedia | 457 | * NAND / SmartMedia |
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c index 81439fe6fb3d..438efbb17482 100644 --- a/arch/arm/mach-at91/board-sam9g20ek.c +++ b/arch/arm/mach-at91/board-sam9g20ek.c | |||
| @@ -238,6 +238,10 @@ static void __init ek_board_init(void) | |||
| 238 | at91_add_device_i2c(NULL, 0); | 238 | at91_add_device_i2c(NULL, 0); |
| 239 | /* LEDs */ | 239 | /* LEDs */ |
| 240 | at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); | 240 | at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); |
| 241 | /* PCK0 provides MCLK to the WM8731 */ | ||
| 242 | at91_set_B_periph(AT91_PIN_PC1, 0); | ||
| 243 | /* SSC (for WM8731) */ | ||
| 244 | at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX); | ||
| 241 | } | 245 | } |
| 242 | 246 | ||
| 243 | MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK") | 247 | MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK") |
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 7b9ce7a336b0..b5daf7f5e011 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h | |||
| @@ -47,9 +47,6 @@ extern void at91_irq_resume(void); | |||
| 47 | #define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ | 47 | #define AT91RM9200_BGA 4 /* AT91RM9200 BGA package has 4 banks */ |
| 48 | 48 | ||
| 49 | struct at91_gpio_bank { | 49 | struct at91_gpio_bank { |
| 50 | unsigned chipbase; /* bank's first GPIO number */ | ||
| 51 | void __iomem *regbase; /* base of register bank */ | ||
| 52 | struct at91_gpio_bank *next; /* bank sharing same IRQ/clock/... */ | ||
| 53 | unsigned short id; /* peripheral ID */ | 50 | unsigned short id; /* peripheral ID */ |
| 54 | unsigned long offset; /* offset from system peripheral base */ | 51 | unsigned long offset; /* offset from system peripheral base */ |
| 55 | struct clk *clock; /* associated clock */ | 52 | struct clk *clock; /* associated clock */ |
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c index 2f7d4977dce9..f2236f0e101f 100644 --- a/arch/arm/mach-at91/gpio.c +++ b/arch/arm/mach-at91/gpio.c | |||
| @@ -24,19 +24,59 @@ | |||
| 24 | #include <mach/at91_pio.h> | 24 | #include <mach/at91_pio.h> |
| 25 | #include <mach/gpio.h> | 25 | #include <mach/gpio.h> |
| 26 | 26 | ||
| 27 | #include <asm/gpio.h> | ||
| 28 | |||
| 27 | #include "generic.h" | 29 | #include "generic.h" |
| 28 | 30 | ||
| 31 | struct at91_gpio_chip { | ||
| 32 | struct gpio_chip chip; | ||
| 33 | struct at91_gpio_chip *next; /* Bank sharing same clock */ | ||
| 34 | struct at91_gpio_bank *bank; /* Bank definition */ | ||
| 35 | void __iomem *regbase; /* Base of register bank */ | ||
| 36 | }; | ||
| 29 | 37 | ||
| 30 | static struct at91_gpio_bank *gpio; | 38 | #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) |
| 31 | static int gpio_banks; | 39 | |
| 40 | static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip); | ||
| 41 | static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val); | ||
| 42 | static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset); | ||
| 43 | static int at91_gpiolib_direction_output(struct gpio_chip *chip, | ||
| 44 | unsigned offset, int val); | ||
| 45 | static int at91_gpiolib_direction_input(struct gpio_chip *chip, | ||
| 46 | unsigned offset); | ||
| 47 | static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset); | ||
| 48 | |||
| 49 | #define AT91_GPIO_CHIP(name, base_gpio, nr_gpio) \ | ||
| 50 | { \ | ||
| 51 | .chip = { \ | ||
| 52 | .label = name, \ | ||
| 53 | .request = at91_gpiolib_request, \ | ||
| 54 | .direction_input = at91_gpiolib_direction_input, \ | ||
| 55 | .direction_output = at91_gpiolib_direction_output, \ | ||
| 56 | .get = at91_gpiolib_get, \ | ||
| 57 | .set = at91_gpiolib_set, \ | ||
| 58 | .dbg_show = at91_gpiolib_dbg_show, \ | ||
| 59 | .base = base_gpio, \ | ||
| 60 | .ngpio = nr_gpio, \ | ||
| 61 | }, \ | ||
| 62 | } | ||
| 63 | |||
| 64 | static struct at91_gpio_chip gpio_chip[] = { | ||
| 65 | AT91_GPIO_CHIP("A", 0x00 + PIN_BASE, 32), | ||
| 66 | AT91_GPIO_CHIP("B", 0x20 + PIN_BASE, 32), | ||
| 67 | AT91_GPIO_CHIP("C", 0x40 + PIN_BASE, 32), | ||
| 68 | AT91_GPIO_CHIP("D", 0x60 + PIN_BASE, 32), | ||
| 69 | AT91_GPIO_CHIP("E", 0x80 + PIN_BASE, 32), | ||
| 70 | }; | ||
| 32 | 71 | ||
| 72 | static int gpio_banks; | ||
| 33 | 73 | ||
| 34 | static inline void __iomem *pin_to_controller(unsigned pin) | 74 | static inline void __iomem *pin_to_controller(unsigned pin) |
| 35 | { | 75 | { |
| 36 | pin -= PIN_BASE; | 76 | pin -= PIN_BASE; |
| 37 | pin /= 32; | 77 | pin /= 32; |
| 38 | if (likely(pin < gpio_banks)) | 78 | if (likely(pin < gpio_banks)) |
| 39 | return gpio[pin].regbase; | 79 | return gpio_chip[pin].regbase; |
| 40 | 80 | ||
| 41 | return NULL; | 81 | return NULL; |
| 42 | } | 82 | } |
| @@ -197,39 +237,6 @@ int __init_or_module at91_set_multi_drive(unsigned pin, int is_on) | |||
| 197 | } | 237 | } |
| 198 | EXPORT_SYMBOL(at91_set_multi_drive); | 238 | EXPORT_SYMBOL(at91_set_multi_drive); |
| 199 | 239 | ||
| 200 | /*--------------------------------------------------------------------------*/ | ||
| 201 | |||
| 202 | /* new-style GPIO calls; these expect at91_set_GPIO_periph to have been | ||
| 203 | * called, and maybe at91_set_multi_drive() for putout pins. | ||
| 204 | */ | ||
| 205 | |||
| 206 | int gpio_direction_input(unsigned pin) | ||
| 207 | { | ||
| 208 | void __iomem *pio = pin_to_controller(pin); | ||
| 209 | unsigned mask = pin_to_mask(pin); | ||
| 210 | |||
| 211 | if (!pio || !(__raw_readl(pio + PIO_PSR) & mask)) | ||
| 212 | return -EINVAL; | ||
| 213 | __raw_writel(mask, pio + PIO_ODR); | ||
| 214 | return 0; | ||
| 215 | } | ||
| 216 | EXPORT_SYMBOL(gpio_direction_input); | ||
| 217 | |||
| 218 | int gpio_direction_output(unsigned pin, int value) | ||
| 219 | { | ||
| 220 | void __iomem *pio = pin_to_controller(pin); | ||
| 221 | unsigned mask = pin_to_mask(pin); | ||
| 222 | |||
| 223 | if (!pio || !(__raw_readl(pio + PIO_PSR) & mask)) | ||
| 224 | return -EINVAL; | ||
| 225 | __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); | ||
| 226 | __raw_writel(mask, pio + PIO_OER); | ||
| 227 | return 0; | ||
| 228 | } | ||
| 229 | EXPORT_SYMBOL(gpio_direction_output); | ||
| 230 | |||
| 231 | /*--------------------------------------------------------------------------*/ | ||
| 232 | |||
| 233 | /* | 240 | /* |
| 234 | * assuming the pin is muxed as a gpio output, set its value. | 241 | * assuming the pin is muxed as a gpio output, set its value. |
| 235 | */ | 242 | */ |
| @@ -282,7 +289,7 @@ static int gpio_irq_set_wake(unsigned pin, unsigned state) | |||
| 282 | else | 289 | else |
| 283 | wakeups[bank] &= ~mask; | 290 | wakeups[bank] &= ~mask; |
| 284 | 291 | ||
| 285 | set_irq_wake(gpio[bank].id, state); | 292 | set_irq_wake(gpio_chip[bank].bank->id, state); |
| 286 | 293 | ||
| 287 | return 0; | 294 | return 0; |
| 288 | } | 295 | } |
| @@ -292,14 +299,14 @@ void at91_gpio_suspend(void) | |||
| 292 | int i; | 299 | int i; |
| 293 | 300 | ||
| 294 | for (i = 0; i < gpio_banks; i++) { | 301 | for (i = 0; i < gpio_banks; i++) { |
| 295 | void __iomem *pio = gpio[i].regbase; | 302 | void __iomem *pio = gpio_chip[i].regbase; |
| 296 | 303 | ||
| 297 | backups[i] = __raw_readl(pio + PIO_IMR); | 304 | backups[i] = __raw_readl(pio + PIO_IMR); |
| 298 | __raw_writel(backups[i], pio + PIO_IDR); | 305 | __raw_writel(backups[i], pio + PIO_IDR); |
| 299 | __raw_writel(wakeups[i], pio + PIO_IER); | 306 | __raw_writel(wakeups[i], pio + PIO_IER); |
| 300 | 307 | ||
| 301 | if (!wakeups[i]) | 308 | if (!wakeups[i]) |
| 302 | clk_disable(gpio[i].clock); | 309 | clk_disable(gpio_chip[i].bank->clock); |
| 303 | else { | 310 | else { |
| 304 | #ifdef CONFIG_PM_DEBUG | 311 | #ifdef CONFIG_PM_DEBUG |
| 305 | printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); | 312 | printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); |
| @@ -313,10 +320,10 @@ void at91_gpio_resume(void) | |||
| 313 | int i; | 320 | int i; |
| 314 | 321 | ||
| 315 | for (i = 0; i < gpio_banks; i++) { | 322 | for (i = 0; i < gpio_banks; i++) { |
| 316 | void __iomem *pio = gpio[i].regbase; | 323 | void __iomem *pio = gpio_chip[i].regbase; |
| 317 | 324 | ||
| 318 | if (!wakeups[i]) | 325 | if (!wakeups[i]) |
| 319 | clk_enable(gpio[i].clock); | 326 | clk_enable(gpio_chip[i].bank->clock); |
| 320 | 327 | ||
| 321 | __raw_writel(wakeups[i], pio + PIO_IDR); | 328 | __raw_writel(wakeups[i], pio + PIO_IDR); |
| 322 | __raw_writel(backups[i], pio + PIO_IER); | 329 | __raw_writel(backups[i], pio + PIO_IER); |
| @@ -380,12 +387,12 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |||
| 380 | { | 387 | { |
| 381 | unsigned pin; | 388 | unsigned pin; |
| 382 | struct irq_desc *gpio; | 389 | struct irq_desc *gpio; |
| 383 | struct at91_gpio_bank *bank; | 390 | struct at91_gpio_chip *at91_gpio; |
| 384 | void __iomem *pio; | 391 | void __iomem *pio; |
| 385 | u32 isr; | 392 | u32 isr; |
| 386 | 393 | ||
| 387 | bank = get_irq_chip_data(irq); | 394 | at91_gpio = get_irq_chip_data(irq); |
| 388 | pio = bank->regbase; | 395 | pio = at91_gpio->regbase; |
| 389 | 396 | ||
| 390 | /* temporarily mask (level sensitive) parent IRQ */ | 397 | /* temporarily mask (level sensitive) parent IRQ */ |
| 391 | desc->chip->ack(irq); | 398 | desc->chip->ack(irq); |
| @@ -396,14 +403,14 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) | |||
| 396 | */ | 403 | */ |
| 397 | isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); | 404 | isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); |
| 398 | if (!isr) { | 405 | if (!isr) { |
| 399 | if (!bank->next) | 406 | if (!at91_gpio->next) |
| 400 | break; | 407 | break; |
| 401 | bank = bank->next; | 408 | at91_gpio = at91_gpio->next; |
| 402 | pio = bank->regbase; | 409 | pio = at91_gpio->regbase; |
| 403 | continue; | 410 | continue; |
| 404 | } | 411 | } |
| 405 | 412 | ||
| 406 | pin = bank->chipbase; | 413 | pin = at91_gpio->chip.base; |
| 407 | gpio = &irq_desc[pin]; | 414 | gpio = &irq_desc[pin]; |
| 408 | 415 | ||
| 409 | while (isr) { | 416 | while (isr) { |
| @@ -502,17 +509,17 @@ static struct lock_class_key gpio_lock_class; | |||
| 502 | void __init at91_gpio_irq_setup(void) | 509 | void __init at91_gpio_irq_setup(void) |
| 503 | { | 510 | { |
| 504 | unsigned pioc, pin; | 511 | unsigned pioc, pin; |
| 505 | struct at91_gpio_bank *this, *prev; | 512 | struct at91_gpio_chip *this, *prev; |
| 506 | 513 | ||
| 507 | for (pioc = 0, pin = PIN_BASE, this = gpio, prev = NULL; | 514 | for (pioc = 0, pin = PIN_BASE, this = gpio_chip, prev = NULL; |
| 508 | pioc++ < gpio_banks; | 515 | pioc++ < gpio_banks; |
| 509 | prev = this, this++) { | 516 | prev = this, this++) { |
| 510 | unsigned id = this->id; | 517 | unsigned id = this->bank->id; |
| 511 | unsigned i; | 518 | unsigned i; |
| 512 | 519 | ||
| 513 | __raw_writel(~0, this->regbase + PIO_IDR); | 520 | __raw_writel(~0, this->regbase + PIO_IDR); |
| 514 | 521 | ||
| 515 | for (i = 0, pin = this->chipbase; i < 32; i++, pin++) { | 522 | for (i = 0, pin = this->chip.base; i < 32; i++, pin++) { |
| 516 | lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class); | 523 | lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class); |
| 517 | 524 | ||
| 518 | /* | 525 | /* |
| @@ -537,32 +544,117 @@ void __init at91_gpio_irq_setup(void) | |||
| 537 | pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); | 544 | pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); |
| 538 | } | 545 | } |
| 539 | 546 | ||
| 547 | /* gpiolib support */ | ||
| 548 | static int at91_gpiolib_direction_input(struct gpio_chip *chip, | ||
| 549 | unsigned offset) | ||
| 550 | { | ||
| 551 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | ||
| 552 | void __iomem *pio = at91_gpio->regbase; | ||
| 553 | unsigned mask = 1 << offset; | ||
| 554 | |||
| 555 | __raw_writel(mask, pio + PIO_ODR); | ||
| 556 | return 0; | ||
| 557 | } | ||
| 558 | |||
| 559 | static int at91_gpiolib_direction_output(struct gpio_chip *chip, | ||
| 560 | unsigned offset, int val) | ||
| 561 | { | ||
| 562 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | ||
| 563 | void __iomem *pio = at91_gpio->regbase; | ||
| 564 | unsigned mask = 1 << offset; | ||
| 565 | |||
| 566 | __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); | ||
| 567 | __raw_writel(mask, pio + PIO_OER); | ||
| 568 | return 0; | ||
| 569 | } | ||
| 570 | |||
| 571 | static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset) | ||
| 572 | { | ||
| 573 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | ||
| 574 | void __iomem *pio = at91_gpio->regbase; | ||
| 575 | unsigned mask = 1 << offset; | ||
| 576 | u32 pdsr; | ||
| 577 | |||
| 578 | pdsr = __raw_readl(pio + PIO_PDSR); | ||
| 579 | return (pdsr & mask) != 0; | ||
| 580 | } | ||
| 581 | |||
| 582 | static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val) | ||
| 583 | { | ||
| 584 | struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); | ||
| 585 | void __iomem *pio = at91_gpio->regbase; | ||
| 586 | unsigned mask = 1 << offset; | ||
| 587 | |||
| 588 | __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); | ||
| 589 | } | ||
| 590 | |||
| 591 | static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset) | ||
| 592 | { | ||
| 593 | unsigned pin = chip->base + offset; | ||
| 594 | void __iomem *pio = pin_to_controller(pin); | ||
| 595 | unsigned mask = pin_to_mask(pin); | ||
| 596 | |||
| 597 | /* Cannot request GPIOs that are in alternate function mode */ | ||
| 598 | if (!(__raw_readl(pio + PIO_PSR) & mask)) | ||
| 599 | return -EPERM; | ||
| 600 | |||
| 601 | return 0; | ||
| 602 | } | ||
| 603 | |||
| 604 | static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip) | ||
| 605 | { | ||
| 606 | int i; | ||
| 607 | |||
| 608 | for (i = 0; i < chip->ngpio; i++) { | ||
| 609 | unsigned pin = chip->base + i; | ||
| 610 | void __iomem *pio = pin_to_controller(pin); | ||
| 611 | unsigned mask = pin_to_mask(pin); | ||
| 612 | const char *gpio_label; | ||
| 613 | |||
| 614 | gpio_label = gpiochip_is_requested(chip, i); | ||
| 615 | if (gpio_label) { | ||
| 616 | seq_printf(s, "[%s] GPIO%s%d: ", | ||
| 617 | gpio_label, chip->label, i); | ||
| 618 | if (__raw_readl(pio + PIO_PSR) & mask) | ||
| 619 | seq_printf(s, "[gpio] %s\n", | ||
| 620 | at91_get_gpio_value(pin) ? | ||
| 621 | "set" : "clear"); | ||
| 622 | else | ||
| 623 | seq_printf(s, "[periph %s]\n", | ||
| 624 | __raw_readl(pio + PIO_ABSR) & | ||
| 625 | mask ? "B" : "A"); | ||
| 626 | } | ||
| 627 | } | ||
| 628 | } | ||
| 629 | |||
| 540 | /* | 630 | /* |
| 541 | * Called from the processor-specific init to enable GPIO pin support. | 631 | * Called from the processor-specific init to enable GPIO pin support. |
| 542 | */ | 632 | */ |
| 543 | void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) | 633 | void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) |
| 544 | { | 634 | { |
| 545 | unsigned i; | 635 | unsigned i; |
| 546 | struct at91_gpio_bank *last; | 636 | struct at91_gpio_chip *at91_gpio, *last = NULL; |
| 547 | 637 | ||
| 548 | BUG_ON(nr_banks > MAX_GPIO_BANKS); | 638 | BUG_ON(nr_banks > MAX_GPIO_BANKS); |
| 549 | 639 | ||
| 550 | gpio = data; | ||
| 551 | gpio_banks = nr_banks; | 640 | gpio_banks = nr_banks; |
| 552 | 641 | ||
| 553 | for (i = 0, last = NULL; i < nr_banks; i++, last = data, data++) { | 642 | for (i = 0; i < nr_banks; i++) { |
| 554 | data->chipbase = PIN_BASE + i * 32; | 643 | at91_gpio = &gpio_chip[i]; |
| 555 | data->regbase = data->offset + (void __iomem *)AT91_VA_BASE_SYS; | 644 | |
| 645 | at91_gpio->bank = &data[i]; | ||
| 646 | at91_gpio->chip.base = PIN_BASE + i * 32; | ||
| 647 | at91_gpio->regbase = at91_gpio->bank->offset + | ||
| 648 | (void __iomem *)AT91_VA_BASE_SYS; | ||
| 556 | 649 | ||
| 557 | /* enable PIO controller's clock */ | 650 | /* enable PIO controller's clock */ |
| 558 | clk_enable(data->clock); | 651 | clk_enable(at91_gpio->bank->clock); |
| 559 | 652 | ||
| 560 | /* | 653 | /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */ |
| 561 | * Some processors share peripheral ID between multiple GPIO banks. | 654 | if (last && last->bank->id == at91_gpio->bank->id) |
| 562 | * SAM9263 (PIOC, PIOD, PIOE) | 655 | last->next = at91_gpio; |
| 563 | * CAP9 (PIOA, PIOB, PIOC, PIOD) | 656 | last = at91_gpio; |
| 564 | */ | 657 | |
| 565 | if (last && last->id == data->id) | 658 | gpiochip_add(&at91_gpio->chip); |
| 566 | last->next = data; | ||
| 567 | } | 659 | } |
| 568 | } | 660 | } |
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h index 0b3ae21b4565..793fe7b25f36 100644 --- a/arch/arm/mach-at91/include/mach/board.h +++ b/arch/arm/mach-at91/include/mach/board.h | |||
| @@ -56,6 +56,9 @@ struct at91_cf_data { | |||
| 56 | u8 vcc_pin; /* power switching */ | 56 | u8 vcc_pin; /* power switching */ |
| 57 | u8 rst_pin; /* card reset */ | 57 | u8 rst_pin; /* card reset */ |
| 58 | u8 chipselect; /* EBI Chip Select number */ | 58 | u8 chipselect; /* EBI Chip Select number */ |
| 59 | u8 flags; | ||
| 60 | #define AT91_CF_TRUE_IDE 0x01 | ||
| 61 | #define AT91_IDE_SWAP_A0_A2 0x02 | ||
| 59 | }; | 62 | }; |
| 60 | extern void __init at91_add_device_cf(struct at91_cf_data *data); | 63 | extern void __init at91_add_device_cf(struct at91_cf_data *data); |
| 61 | 64 | ||
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h index bffa6741a751..04c91e31c9c5 100644 --- a/arch/arm/mach-at91/include/mach/gpio.h +++ b/arch/arm/mach-at91/include/mach/gpio.h | |||
| @@ -213,32 +213,12 @@ extern void at91_gpio_resume(void); | |||
| 213 | */ | 213 | */ |
| 214 | 214 | ||
| 215 | #include <asm/errno.h> | 215 | #include <asm/errno.h> |
| 216 | |||
| 217 | static inline int gpio_request(unsigned gpio, const char *label) | ||
| 218 | { | ||
| 219 | return 0; | ||
| 220 | } | ||
| 221 | |||
| 222 | static inline void gpio_free(unsigned gpio) | ||
| 223 | { | ||
| 224 | might_sleep(); | ||
| 225 | } | ||
| 226 | |||
| 227 | extern int gpio_direction_input(unsigned gpio); | ||
| 228 | extern int gpio_direction_output(unsigned gpio, int value); | ||
| 229 | |||
| 230 | static inline int gpio_get_value(unsigned gpio) | ||
| 231 | { | ||
| 232 | return at91_get_gpio_value(gpio); | ||
| 233 | } | ||
| 234 | |||
| 235 | static inline void gpio_set_value(unsigned gpio, int value) | ||
| 236 | { | ||
| 237 | at91_set_gpio_value(gpio, value); | ||
| 238 | } | ||
| 239 | |||
| 240 | #include <asm-generic/gpio.h> /* cansleep wrappers */ | 216 | #include <asm-generic/gpio.h> /* cansleep wrappers */ |
| 241 | 217 | ||
| 218 | #define gpio_get_value __gpio_get_value | ||
| 219 | #define gpio_set_value __gpio_set_value | ||
| 220 | #define gpio_cansleep __gpio_cansleep | ||
| 221 | |||
| 242 | static inline int gpio_to_irq(unsigned gpio) | 222 | static inline int gpio_to_irq(unsigned gpio) |
| 243 | { | 223 | { |
| 244 | return gpio; | 224 | return gpio; |
diff --git a/arch/arm/mach-at91/include/mach/system.h b/arch/arm/mach-at91/include/mach/system.h index e712658d966c..5268af3933c2 100644 --- a/arch/arm/mach-at91/include/mach/system.h +++ b/arch/arm/mach-at91/include/mach/system.h | |||
| @@ -43,7 +43,7 @@ static inline void arch_idle(void) | |||
| 43 | 43 | ||
| 44 | void (*at91_arch_reset)(void); | 44 | void (*at91_arch_reset)(void); |
| 45 | 45 | ||
| 46 | static inline void arch_reset(char mode) | 46 | static inline void arch_reset(char mode, const char *cmd) |
| 47 | { | 47 | { |
| 48 | /* call the CPU-specific reset function */ | 48 | /* call the CPU-specific reset function */ |
| 49 | if (at91_arch_reset) | 49 | if (at91_arch_reset) |
diff --git a/arch/arm/mach-clps711x/include/mach/system.h b/arch/arm/mach-clps711x/include/mach/system.h index 24e96159e3e7..f916cd7a477d 100644 --- a/arch/arm/mach-clps711x/include/mach/system.h +++ b/arch/arm/mach-clps711x/include/mach/system.h | |||
| @@ -32,7 +32,7 @@ static inline void arch_idle(void) | |||
| 32 | mov r0, r0"); | 32 | mov r0, r0"); |
| 33 | } | 33 | } |
| 34 | 34 | ||
| 35 | static inline void arch_reset(char mode) | 35 | static inline void arch_reset(char mode, const char *cmd) |
| 36 | { | 36 | { |
| 37 | cpu_reset(0); | 37 | cpu_reset(0); |
| 38 | } | 38 | } |
diff --git a/arch/arm/mach-davinci/include/mach/system.h b/arch/arm/mach-davinci/include/mach/system.h index 17ca41dc2c53..b7e7036674fa 100644 --- a/arch/arm/mach-davinci/include/mach/system.h +++ b/arch/arm/mach-davinci/include/mach/system.h | |||
| @@ -21,7 +21,7 @@ static void arch_idle(void) | |||
| 21 | cpu_do_idle(); | 21 | cpu_do_idle(); |
| 22 | } | 22 | } |
| 23 | 23 | ||
| 24 | static void arch_reset(char mode) | 24 | static void arch_reset(char mode, const char *cmd) |
| 25 | { | 25 | { |
| 26 | davinci_watchdog_reset(); | 26 | davinci_watchdog_reset(); |
| 27 | } | 27 | } |
diff --git a/arch/arm/mach-ebsa110/include/mach/system.h b/arch/arm/mach-ebsa110/include/mach/system.h index 350a028997ef..9a26245bf1fc 100644 --- a/arch/arm/mach-ebsa110/include/mach/system.h +++ b/arch/arm/mach-ebsa110/include/mach/system.h | |||
| @@ -34,6 +34,6 @@ static inline void arch_idle(void) | |||
| 34 | asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc"); | 34 | asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc"); |
| 35 | } | 35 | } |
| 36 | 36 | ||
| 37 | #define arch_reset(mode) cpu_reset(0x80000000) | 37 | #define arch_reset(mode, cmd) cpu_reset(0x80000000) |
| 38 | 38 | ||
| 39 | #endif | 39 | #endif |
diff --git a/arch/arm/mach-ep93xx/Makefile b/arch/arm/mach-ep93xx/Makefile index 944e42d51646..9522e205b73f 100644 --- a/arch/arm/mach-ep93xx/Makefile +++ b/arch/arm/mach-ep93xx/Makefile | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Makefile for the linux kernel. | 2 | # Makefile for the linux kernel. |
| 3 | # | 3 | # |
| 4 | obj-y := core.o clock.o gpio.o | 4 | obj-y := core.o clock.o dma-m2p.o gpio.o |
| 5 | obj-m := | 5 | obj-m := |
| 6 | obj-n := | 6 | obj-n := |
| 7 | obj- := | 7 | obj- := |
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c index 96049283a10a..e8ebeaea6c48 100644 --- a/arch/arm/mach-ep93xx/clock.c +++ b/arch/arm/mach-ep93xx/clock.c | |||
| @@ -41,6 +41,56 @@ static struct clk clk_usb_host = { | |||
| 41 | .enable_mask = EP93XX_SYSCON_CLOCK_USH_EN, | 41 | .enable_mask = EP93XX_SYSCON_CLOCK_USH_EN, |
| 42 | }; | 42 | }; |
| 43 | 43 | ||
| 44 | /* DMA Clocks */ | ||
| 45 | static struct clk clk_m2p0 = { | ||
| 46 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 47 | .enable_mask = 0x00020000, | ||
| 48 | }; | ||
| 49 | static struct clk clk_m2p1 = { | ||
| 50 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 51 | .enable_mask = 0x00010000, | ||
| 52 | }; | ||
| 53 | static struct clk clk_m2p2 = { | ||
| 54 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 55 | .enable_mask = 0x00080000, | ||
| 56 | }; | ||
| 57 | static struct clk clk_m2p3 = { | ||
| 58 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 59 | .enable_mask = 0x00040000, | ||
| 60 | }; | ||
| 61 | static struct clk clk_m2p4 = { | ||
| 62 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 63 | .enable_mask = 0x00200000, | ||
| 64 | }; | ||
| 65 | static struct clk clk_m2p5 = { | ||
| 66 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 67 | .enable_mask = 0x00100000, | ||
| 68 | }; | ||
| 69 | static struct clk clk_m2p6 = { | ||
| 70 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 71 | .enable_mask = 0x00800000, | ||
| 72 | }; | ||
| 73 | static struct clk clk_m2p7 = { | ||
| 74 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 75 | .enable_mask = 0x00400000, | ||
| 76 | }; | ||
| 77 | static struct clk clk_m2p8 = { | ||
| 78 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 79 | .enable_mask = 0x02000000, | ||
| 80 | }; | ||
| 81 | static struct clk clk_m2p9 = { | ||
| 82 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 83 | .enable_mask = 0x01000000, | ||
| 84 | }; | ||
| 85 | static struct clk clk_m2m0 = { | ||
| 86 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 87 | .enable_mask = 0x04000000, | ||
| 88 | }; | ||
| 89 | static struct clk clk_m2m1 = { | ||
| 90 | .enable_reg = EP93XX_SYSCON_CLOCK_CONTROL, | ||
| 91 | .enable_mask = 0x08000000, | ||
| 92 | }; | ||
| 93 | |||
| 44 | #define INIT_CK(dev,con,ck) \ | 94 | #define INIT_CK(dev,con,ck) \ |
| 45 | { .dev_id = dev, .con_id = con, .clk = ck } | 95 | { .dev_id = dev, .con_id = con, .clk = ck } |
| 46 | 96 | ||
| @@ -54,6 +104,18 @@ static struct clk_lookup clocks[] = { | |||
| 54 | INIT_CK(NULL, "pclk", &clk_p), | 104 | INIT_CK(NULL, "pclk", &clk_p), |
| 55 | INIT_CK(NULL, "pll2", &clk_pll2), | 105 | INIT_CK(NULL, "pll2", &clk_pll2), |
| 56 | INIT_CK(NULL, "usb_host", &clk_usb_host), | 106 | INIT_CK(NULL, "usb_host", &clk_usb_host), |
| 107 | INIT_CK(NULL, "m2p0", &clk_m2p0), | ||
| 108 | INIT_CK(NULL, "m2p1", &clk_m2p1), | ||
| 109 | INIT_CK(NULL, "m2p2", &clk_m2p2), | ||
| 110 | INIT_CK(NULL, "m2p3", &clk_m2p3), | ||
| 111 | INIT_CK(NULL, "m2p4", &clk_m2p4), | ||
| 112 | INIT_CK(NULL, "m2p5", &clk_m2p5), | ||
| 113 | INIT_CK(NULL, "m2p6", &clk_m2p6), | ||
| 114 | INIT_CK(NULL, "m2p7", &clk_m2p7), | ||
| 115 | INIT_CK(NULL, "m2p8", &clk_m2p8), | ||
| 116 | INIT_CK(NULL, "m2p9", &clk_m2p9), | ||
| 117 | INIT_CK(NULL, "m2m0", &clk_m2m0), | ||
| 118 | INIT_CK(NULL, "m2m1", &clk_m2m1), | ||
| 57 | }; | 119 | }; |
| 58 | 120 | ||
| 59 | 121 | ||
| @@ -110,6 +172,22 @@ static unsigned long calc_pll_rate(u32 config_word) | |||
| 110 | return (unsigned long)rate; | 172 | return (unsigned long)rate; |
| 111 | } | 173 | } |
| 112 | 174 | ||
| 175 | static void __init ep93xx_dma_clock_init(void) | ||
| 176 | { | ||
| 177 | clk_m2p0.rate = clk_h.rate; | ||
| 178 | clk_m2p1.rate = clk_h.rate; | ||
| 179 | clk_m2p2.rate = clk_h.rate; | ||
| 180 | clk_m2p3.rate = clk_h.rate; | ||
| 181 | clk_m2p4.rate = clk_h.rate; | ||
| 182 | clk_m2p5.rate = clk_h.rate; | ||
| 183 | clk_m2p6.rate = clk_h.rate; | ||
| 184 | clk_m2p7.rate = clk_h.rate; | ||
| 185 | clk_m2p8.rate = clk_h.rate; | ||
| 186 | clk_m2p9.rate = clk_h.rate; | ||
| 187 | clk_m2m0.rate = clk_h.rate; | ||
| 188 | clk_m2m1.rate = clk_h.rate; | ||
| 189 | } | ||
| 190 | |||
| 113 | static int __init ep93xx_clock_init(void) | 191 | static int __init ep93xx_clock_init(void) |
| 114 | { | 192 | { |
| 115 | u32 value; | 193 | u32 value; |
| @@ -124,6 +202,7 @@ static int __init ep93xx_clock_init(void) | |||
| 124 | clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; | 202 | clk_f.rate = clk_pll1.rate / fclk_divisors[(value >> 25) & 0x7]; |
| 125 | clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7]; | 203 | clk_h.rate = clk_pll1.rate / hclk_divisors[(value >> 20) & 0x7]; |
| 126 | clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3]; | 204 | clk_p.rate = clk_h.rate / pclk_divisors[(value >> 18) & 0x3]; |
| 205 | ep93xx_dma_clock_init(); | ||
| 127 | 206 | ||
| 128 | value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2); | 207 | value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2); |
| 129 | if (!(value & 0x00080000)) { /* PLL2 bypassed? */ | 208 | if (!(value & 0x00080000)) { /* PLL2 bypassed? */ |
diff --git a/arch/arm/mach-ep93xx/dma-m2p.c b/arch/arm/mach-ep93xx/dma-m2p.c new file mode 100644 index 000000000000..a2df5bb7dff0 --- /dev/null +++ b/arch/arm/mach-ep93xx/dma-m2p.c | |||
| @@ -0,0 +1,408 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ep93xx/dma-m2p.c | ||
| 3 | * M2P DMA handling for Cirrus EP93xx chips. | ||
| 4 | * | ||
| 5 | * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org> | ||
| 6 | * Copyright (C) 2006 Applied Data Systems | ||
| 7 | * | ||
| 8 | * Copyright (C) 2009 Ryan Mallon <ryan@bluewatersys.com> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or (at | ||
| 13 | * your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | /* | ||
| 17 | * On the EP93xx chip the following peripherals my be allocated to the 10 | ||
| 18 | * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive). | ||
| 19 | * | ||
| 20 | * I2S contains 3 Tx and 3 Rx DMA Channels | ||
| 21 | * AAC contains 3 Tx and 3 Rx DMA Channels | ||
| 22 | * UART1 contains 1 Tx and 1 Rx DMA Channels | ||
| 23 | * UART2 contains 1 Tx and 1 Rx DMA Channels | ||
| 24 | * UART3 contains 1 Tx and 1 Rx DMA Channels | ||
| 25 | * IrDA contains 1 Tx and 1 Rx DMA Channels | ||
| 26 | * | ||
| 27 | * SSP and IDE use the Memory to Memory (M2M) channels and are not covered | ||
| 28 | * with this implementation. | ||
| 29 | */ | ||
| 30 | |||
| 31 | #include <linux/kernel.h> | ||
| 32 | #include <linux/clk.h> | ||
| 33 | #include <linux/err.h> | ||
| 34 | #include <linux/interrupt.h> | ||
| 35 | #include <linux/module.h> | ||
| 36 | |||
| 37 | #include <mach/dma.h> | ||
| 38 | #include <mach/hardware.h> | ||
| 39 | |||
| 40 | #define M2P_CONTROL 0x00 | ||
| 41 | #define M2P_CONTROL_STALL_IRQ_EN (1 << 0) | ||
| 42 | #define M2P_CONTROL_NFB_IRQ_EN (1 << 1) | ||
| 43 | #define M2P_CONTROL_ERROR_IRQ_EN (1 << 3) | ||
| 44 | #define M2P_CONTROL_ENABLE (1 << 4) | ||
| 45 | #define M2P_INTERRUPT 0x04 | ||
| 46 | #define M2P_INTERRUPT_STALL (1 << 0) | ||
| 47 | #define M2P_INTERRUPT_NFB (1 << 1) | ||
| 48 | #define M2P_INTERRUPT_ERROR (1 << 3) | ||
| 49 | #define M2P_PPALLOC 0x08 | ||
| 50 | #define M2P_STATUS 0x0c | ||
| 51 | #define M2P_REMAIN 0x14 | ||
| 52 | #define M2P_MAXCNT0 0x20 | ||
| 53 | #define M2P_BASE0 0x24 | ||
| 54 | #define M2P_MAXCNT1 0x30 | ||
| 55 | #define M2P_BASE1 0x34 | ||
| 56 | |||
| 57 | #define STATE_IDLE 0 /* Channel is inactive. */ | ||
| 58 | #define STATE_STALL 1 /* Channel is active, no buffers pending. */ | ||
| 59 | #define STATE_ON 2 /* Channel is active, one buffer pending. */ | ||
| 60 | #define STATE_NEXT 3 /* Channel is active, two buffers pending. */ | ||
| 61 | |||
| 62 | struct m2p_channel { | ||
| 63 | char *name; | ||
| 64 | void __iomem *base; | ||
| 65 | int irq; | ||
| 66 | |||
| 67 | struct clk *clk; | ||
| 68 | spinlock_t lock; | ||
| 69 | |||
| 70 | void *client; | ||
| 71 | unsigned next_slot:1; | ||
| 72 | struct ep93xx_dma_buffer *buffer_xfer; | ||
| 73 | struct ep93xx_dma_buffer *buffer_next; | ||
| 74 | struct list_head buffers_pending; | ||
| 75 | }; | ||
| 76 | |||
| 77 | static struct m2p_channel m2p_rx[] = { | ||
| 78 | {"m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1}, | ||
| 79 | {"m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3}, | ||
| 80 | {"m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5}, | ||
| 81 | {"m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7}, | ||
| 82 | {"m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9}, | ||
| 83 | {NULL}, | ||
| 84 | }; | ||
| 85 | |||
| 86 | static struct m2p_channel m2p_tx[] = { | ||
| 87 | {"m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0}, | ||
| 88 | {"m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2}, | ||
| 89 | {"m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4}, | ||
| 90 | {"m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6}, | ||
| 91 | {"m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8}, | ||
| 92 | {NULL}, | ||
| 93 | }; | ||
| 94 | |||
| 95 | static void feed_buf(struct m2p_channel *ch, struct ep93xx_dma_buffer *buf) | ||
| 96 | { | ||
| 97 | if (ch->next_slot == 0) { | ||
| 98 | writel(buf->size, ch->base + M2P_MAXCNT0); | ||
| 99 | writel(buf->bus_addr, ch->base + M2P_BASE0); | ||
| 100 | } else { | ||
| 101 | writel(buf->size, ch->base + M2P_MAXCNT1); | ||
| 102 | writel(buf->bus_addr, ch->base + M2P_BASE1); | ||
| 103 | } | ||
| 104 | ch->next_slot ^= 1; | ||
| 105 | } | ||
| 106 | |||
| 107 | static void choose_buffer_xfer(struct m2p_channel *ch) | ||
| 108 | { | ||
| 109 | struct ep93xx_dma_buffer *buf; | ||
| 110 | |||
| 111 | ch->buffer_xfer = NULL; | ||
| 112 | if (!list_empty(&ch->buffers_pending)) { | ||
| 113 | buf = list_entry(ch->buffers_pending.next, | ||
| 114 | struct ep93xx_dma_buffer, list); | ||
| 115 | list_del(&buf->list); | ||
| 116 | feed_buf(ch, buf); | ||
| 117 | ch->buffer_xfer = buf; | ||
| 118 | } | ||
| 119 | } | ||
| 120 | |||
| 121 | static void choose_buffer_next(struct m2p_channel *ch) | ||
| 122 | { | ||
| 123 | struct ep93xx_dma_buffer *buf; | ||
| 124 | |||
| 125 | ch->buffer_next = NULL; | ||
| 126 | if (!list_empty(&ch->buffers_pending)) { | ||
| 127 | buf = list_entry(ch->buffers_pending.next, | ||
| 128 | struct ep93xx_dma_buffer, list); | ||
| 129 | list_del(&buf->list); | ||
| 130 | feed_buf(ch, buf); | ||
| 131 | ch->buffer_next = buf; | ||
| 132 | } | ||
| 133 | } | ||
| 134 | |||
| 135 | static inline void m2p_set_control(struct m2p_channel *ch, u32 v) | ||
| 136 | { | ||
| 137 | /* | ||
| 138 | * The control register must be read immediately after being written so | ||
| 139 | * that the internal state machine is correctly updated. See the ep93xx | ||
| 140 | * users' guide for details. | ||
| 141 | */ | ||
| 142 | writel(v, ch->base + M2P_CONTROL); | ||
| 143 | readl(ch->base + M2P_CONTROL); | ||
| 144 | } | ||
| 145 | |||
| 146 | static inline int m2p_channel_state(struct m2p_channel *ch) | ||
| 147 | { | ||
| 148 | return (readl(ch->base + M2P_STATUS) >> 4) & 0x3; | ||
| 149 | } | ||
| 150 | |||
| 151 | static irqreturn_t m2p_irq(int irq, void *dev_id) | ||
| 152 | { | ||
| 153 | struct m2p_channel *ch = dev_id; | ||
| 154 | struct ep93xx_dma_m2p_client *cl; | ||
| 155 | u32 irq_status, v; | ||
| 156 | int error = 0; | ||
| 157 | |||
| 158 | cl = ch->client; | ||
| 159 | |||
| 160 | spin_lock(&ch->lock); | ||
| 161 | irq_status = readl(ch->base + M2P_INTERRUPT); | ||
| 162 | |||
| 163 | if (irq_status & M2P_INTERRUPT_ERROR) { | ||
| 164 | writel(M2P_INTERRUPT_ERROR, ch->base + M2P_INTERRUPT); | ||
| 165 | error = 1; | ||
| 166 | } | ||
| 167 | |||
| 168 | if ((irq_status & (M2P_INTERRUPT_STALL | M2P_INTERRUPT_NFB)) == 0) { | ||
| 169 | spin_unlock(&ch->lock); | ||
| 170 | return IRQ_NONE; | ||
| 171 | } | ||
| 172 | |||
| 173 | switch (m2p_channel_state(ch)) { | ||
| 174 | case STATE_IDLE: | ||
| 175 | pr_crit("m2p_irq: dma interrupt without a dma buffer\n"); | ||
| 176 | BUG(); | ||
| 177 | break; | ||
| 178 | |||
| 179 | case STATE_STALL: | ||
| 180 | cl->buffer_finished(cl->cookie, ch->buffer_xfer, 0, error); | ||
| 181 | if (ch->buffer_next != NULL) { | ||
| 182 | cl->buffer_finished(cl->cookie, ch->buffer_next, | ||
| 183 | 0, error); | ||
| 184 | } | ||
| 185 | choose_buffer_xfer(ch); | ||
| 186 | choose_buffer_next(ch); | ||
| 187 | if (ch->buffer_xfer != NULL) | ||
| 188 | cl->buffer_started(cl->cookie, ch->buffer_xfer); | ||
| 189 | break; | ||
| 190 | |||
| 191 | case STATE_ON: | ||
| 192 | cl->buffer_finished(cl->cookie, ch->buffer_xfer, 0, error); | ||
| 193 | ch->buffer_xfer = ch->buffer_next; | ||
| 194 | choose_buffer_next(ch); | ||
| 195 | cl->buffer_started(cl->cookie, ch->buffer_xfer); | ||
| 196 | break; | ||
| 197 | |||
| 198 | case STATE_NEXT: | ||
| 199 | pr_crit("m2p_irq: dma interrupt while next\n"); | ||
| 200 | BUG(); | ||
| 201 | break; | ||
| 202 | } | ||
| 203 | |||
| 204 | v = readl(ch->base + M2P_CONTROL) & ~(M2P_CONTROL_STALL_IRQ_EN | | ||
| 205 | M2P_CONTROL_NFB_IRQ_EN); | ||
| 206 | if (ch->buffer_xfer != NULL) | ||
| 207 | v |= M2P_CONTROL_STALL_IRQ_EN; | ||
| 208 | if (ch->buffer_next != NULL) | ||
| 209 | v |= M2P_CONTROL_NFB_IRQ_EN; | ||
| 210 | m2p_set_control(ch, v); | ||
| 211 | |||
| 212 | spin_unlock(&ch->lock); | ||
| 213 | return IRQ_HANDLED; | ||
| 214 | } | ||
| 215 | |||
| 216 | static struct m2p_channel *find_free_channel(struct ep93xx_dma_m2p_client *cl) | ||
| 217 | { | ||
| 218 | struct m2p_channel *ch; | ||
| 219 | int i; | ||
| 220 | |||
| 221 | if (cl->flags & EP93XX_DMA_M2P_RX) | ||
| 222 | ch = m2p_rx; | ||
| 223 | else | ||
| 224 | ch = m2p_tx; | ||
| 225 | |||
| 226 | for (i = 0; ch[i].base; i++) { | ||
| 227 | struct ep93xx_dma_m2p_client *client; | ||
| 228 | |||
| 229 | client = ch[i].client; | ||
| 230 | if (client != NULL) { | ||
| 231 | int port; | ||
| 232 | |||
| 233 | port = cl->flags & EP93XX_DMA_M2P_PORT_MASK; | ||
| 234 | if (port == (client->flags & | ||
| 235 | EP93XX_DMA_M2P_PORT_MASK)) { | ||
| 236 | pr_warning("DMA channel already used by %s\n", | ||
| 237 | cl->name ? : "unknown client"); | ||
| 238 | return ERR_PTR(-EBUSY); | ||
| 239 | } | ||
| 240 | } | ||
| 241 | } | ||
| 242 | |||
| 243 | for (i = 0; ch[i].base; i++) { | ||
| 244 | if (ch[i].client == NULL) | ||
| 245 | return ch + i; | ||
| 246 | } | ||
| 247 | |||
| 248 | pr_warning("No free DMA channel for %s\n", | ||
| 249 | cl->name ? : "unknown client"); | ||
| 250 | return ERR_PTR(-ENODEV); | ||
| 251 | } | ||
| 252 | |||
| 253 | static void channel_enable(struct m2p_channel *ch) | ||
| 254 | { | ||
| 255 | struct ep93xx_dma_m2p_client *cl = ch->client; | ||
| 256 | u32 v; | ||
| 257 | |||
| 258 | clk_enable(ch->clk); | ||
| 259 | |||
| 260 | v = cl->flags & EP93XX_DMA_M2P_PORT_MASK; | ||
| 261 | writel(v, ch->base + M2P_PPALLOC); | ||
| 262 | |||
| 263 | v = cl->flags & EP93XX_DMA_M2P_ERROR_MASK; | ||
| 264 | v |= M2P_CONTROL_ENABLE | M2P_CONTROL_ERROR_IRQ_EN; | ||
| 265 | m2p_set_control(ch, v); | ||
| 266 | } | ||
| 267 | |||
| 268 | static void channel_disable(struct m2p_channel *ch) | ||
| 269 | { | ||
| 270 | u32 v; | ||
| 271 | |||
| 272 | v = readl(ch->base + M2P_CONTROL); | ||
| 273 | v &= ~(M2P_CONTROL_STALL_IRQ_EN | M2P_CONTROL_NFB_IRQ_EN); | ||
| 274 | m2p_set_control(ch, v); | ||
| 275 | |||
| 276 | while (m2p_channel_state(ch) == STATE_ON) | ||
| 277 | cpu_relax(); | ||
| 278 | |||
| 279 | m2p_set_control(ch, 0x0); | ||
| 280 | |||
| 281 | while (m2p_channel_state(ch) == STATE_STALL) | ||
| 282 | cpu_relax(); | ||
| 283 | |||
| 284 | clk_disable(ch->clk); | ||
| 285 | } | ||
| 286 | |||
| 287 | int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *cl) | ||
| 288 | { | ||
| 289 | struct m2p_channel *ch; | ||
| 290 | int err; | ||
| 291 | |||
| 292 | ch = find_free_channel(cl); | ||
| 293 | if (IS_ERR(ch)) | ||
| 294 | return PTR_ERR(ch); | ||
| 295 | |||
| 296 | err = request_irq(ch->irq, m2p_irq, 0, cl->name ? : "dma-m2p", ch); | ||
| 297 | if (err) | ||
| 298 | return err; | ||
| 299 | |||
| 300 | ch->client = cl; | ||
| 301 | ch->next_slot = 0; | ||
| 302 | ch->buffer_xfer = NULL; | ||
| 303 | ch->buffer_next = NULL; | ||
| 304 | INIT_LIST_HEAD(&ch->buffers_pending); | ||
| 305 | |||
| 306 | cl->channel = ch; | ||
| 307 | |||
| 308 | channel_enable(ch); | ||
| 309 | |||
| 310 | return 0; | ||
| 311 | } | ||
| 312 | EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_client_register); | ||
| 313 | |||
| 314 | void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *cl) | ||
| 315 | { | ||
| 316 | struct m2p_channel *ch = cl->channel; | ||
| 317 | |||
| 318 | channel_disable(ch); | ||
| 319 | free_irq(ch->irq, ch); | ||
| 320 | ch->client = NULL; | ||
| 321 | } | ||
| 322 | EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_client_unregister); | ||
| 323 | |||
| 324 | void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *cl, | ||
| 325 | struct ep93xx_dma_buffer *buf) | ||
| 326 | { | ||
| 327 | struct m2p_channel *ch = cl->channel; | ||
| 328 | unsigned long flags; | ||
| 329 | u32 v; | ||
| 330 | |||
| 331 | spin_lock_irqsave(&ch->lock, flags); | ||
| 332 | v = readl(ch->base + M2P_CONTROL); | ||
| 333 | if (ch->buffer_xfer == NULL) { | ||
| 334 | ch->buffer_xfer = buf; | ||
| 335 | feed_buf(ch, buf); | ||
| 336 | cl->buffer_started(cl->cookie, buf); | ||
| 337 | |||
| 338 | v |= M2P_CONTROL_STALL_IRQ_EN; | ||
| 339 | m2p_set_control(ch, v); | ||
| 340 | |||
| 341 | } else if (ch->buffer_next == NULL) { | ||
| 342 | ch->buffer_next = buf; | ||
| 343 | feed_buf(ch, buf); | ||
| 344 | |||
| 345 | v |= M2P_CONTROL_NFB_IRQ_EN; | ||
| 346 | m2p_set_control(ch, v); | ||
| 347 | } else { | ||
| 348 | list_add_tail(&buf->list, &ch->buffers_pending); | ||
| 349 | } | ||
| 350 | spin_unlock_irqrestore(&ch->lock, flags); | ||
| 351 | } | ||
| 352 | EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_submit); | ||
| 353 | |||
| 354 | void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *cl, | ||
| 355 | struct ep93xx_dma_buffer *buf) | ||
| 356 | { | ||
| 357 | struct m2p_channel *ch = cl->channel; | ||
| 358 | |||
| 359 | list_add_tail(&buf->list, &ch->buffers_pending); | ||
| 360 | } | ||
| 361 | EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_submit_recursive); | ||
| 362 | |||
| 363 | void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *cl) | ||
| 364 | { | ||
| 365 | struct m2p_channel *ch = cl->channel; | ||
| 366 | |||
| 367 | channel_disable(ch); | ||
| 368 | ch->next_slot = 0; | ||
| 369 | ch->buffer_xfer = NULL; | ||
| 370 | ch->buffer_next = NULL; | ||
| 371 | INIT_LIST_HEAD(&ch->buffers_pending); | ||
| 372 | channel_enable(ch); | ||
| 373 | } | ||
| 374 | EXPORT_SYMBOL_GPL(ep93xx_dma_m2p_flush); | ||
| 375 | |||
| 376 | static int init_channel(struct m2p_channel *ch) | ||
| 377 | { | ||
| 378 | ch->clk = clk_get(NULL, ch->name); | ||
| 379 | if (IS_ERR(ch->clk)) | ||
| 380 | return PTR_ERR(ch->clk); | ||
| 381 | |||
| 382 | spin_lock_init(&ch->lock); | ||
| 383 | ch->client = NULL; | ||
| 384 | |||
| 385 | return 0; | ||
| 386 | } | ||
| 387 | |||
| 388 | static int __init ep93xx_dma_m2p_init(void) | ||
| 389 | { | ||
| 390 | int i; | ||
| 391 | int ret; | ||
| 392 | |||
| 393 | for (i = 0; m2p_rx[i].base; i++) { | ||
| 394 | ret = init_channel(m2p_rx + i); | ||
| 395 | if (ret) | ||
| 396 | return ret; | ||
| 397 | } | ||
| 398 | |||
| 399 | for (i = 0; m2p_tx[i].base; i++) { | ||
| 400 | ret = init_channel(m2p_tx + i); | ||
| 401 | if (ret) | ||
| 402 | return ret; | ||
| 403 | } | ||
| 404 | |||
| 405 | pr_info("M2P DMA subsystem initialized\n"); | ||
| 406 | return 0; | ||
| 407 | } | ||
| 408 | arch_initcall(ep93xx_dma_m2p_init); | ||
diff --git a/arch/arm/mach-ep93xx/edb9307a.c b/arch/arm/mach-ep93xx/edb9307a.c index 5b5c22b681be..6171167d3315 100644 --- a/arch/arm/mach-ep93xx/edb9307a.c +++ b/arch/arm/mach-ep93xx/edb9307a.c | |||
| @@ -48,12 +48,24 @@ static struct ep93xx_eth_data edb9307a_eth_data = { | |||
| 48 | .phy_id = 1, | 48 | .phy_id = 1, |
| 49 | }; | 49 | }; |
| 50 | 50 | ||
| 51 | static struct i2c_board_info __initdata edb9307a_i2c_data[] = { | ||
| 52 | { | ||
| 53 | /* On-board battery backed RTC */ | ||
| 54 | I2C_BOARD_INFO("isl1208", 0x6f), | ||
| 55 | }, | ||
| 56 | /* | ||
| 57 | * The I2C signals are also routed to the Expansion Connector (J4) | ||
| 58 | */ | ||
| 59 | }; | ||
| 60 | |||
| 51 | static void __init edb9307a_init_machine(void) | 61 | static void __init edb9307a_init_machine(void) |
| 52 | { | 62 | { |
| 53 | ep93xx_init_devices(); | 63 | ep93xx_init_devices(); |
| 54 | platform_device_register(&edb9307a_flash); | 64 | platform_device_register(&edb9307a_flash); |
| 55 | 65 | ||
| 56 | ep93xx_register_eth(&edb9307a_eth_data, 1); | 66 | ep93xx_register_eth(&edb9307a_eth_data, 1); |
| 67 | |||
| 68 | ep93xx_init_i2c(edb9307a_i2c_data, ARRAY_SIZE(edb9307a_i2c_data)); | ||
| 57 | } | 69 | } |
| 58 | 70 | ||
| 59 | MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board") | 71 | MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board") |
diff --git a/arch/arm/mach-ep93xx/include/mach/dma.h b/arch/arm/mach-ep93xx/include/mach/dma.h new file mode 100644 index 000000000000..ef6bd9d13148 --- /dev/null +++ b/arch/arm/mach-ep93xx/include/mach/dma.h | |||
| @@ -0,0 +1,52 @@ | |||
| 1 | #ifndef __ASM_ARCH_DMA_H | ||
| 2 | #define __ASM_ARCH_DMA_H | ||
| 3 | |||
| 4 | #include <linux/list.h> | ||
| 5 | #include <linux/types.h> | ||
| 6 | |||
| 7 | struct ep93xx_dma_buffer { | ||
| 8 | struct list_head list; | ||
| 9 | u32 bus_addr; | ||
| 10 | u16 size; | ||
| 11 | }; | ||
| 12 | |||
| 13 | struct ep93xx_dma_m2p_client { | ||
| 14 | char *name; | ||
| 15 | u8 flags; | ||
| 16 | void *cookie; | ||
| 17 | void (*buffer_started)(void *cookie, | ||
| 18 | struct ep93xx_dma_buffer *buf); | ||
| 19 | void (*buffer_finished)(void *cookie, | ||
| 20 | struct ep93xx_dma_buffer *buf, | ||
| 21 | int bytes, int error); | ||
| 22 | |||
| 23 | /* Internal to the DMA code. */ | ||
| 24 | void *channel; | ||
| 25 | }; | ||
| 26 | |||
| 27 | #define EP93XX_DMA_M2P_PORT_I2S1 0x00 | ||
| 28 | #define EP93XX_DMA_M2P_PORT_I2S2 0x01 | ||
| 29 | #define EP93XX_DMA_M2P_PORT_AAC1 0x02 | ||
| 30 | #define EP93XX_DMA_M2P_PORT_AAC2 0x03 | ||
| 31 | #define EP93XX_DMA_M2P_PORT_AAC3 0x04 | ||
| 32 | #define EP93XX_DMA_M2P_PORT_I2S3 0x05 | ||
| 33 | #define EP93XX_DMA_M2P_PORT_UART1 0x06 | ||
| 34 | #define EP93XX_DMA_M2P_PORT_UART2 0x07 | ||
| 35 | #define EP93XX_DMA_M2P_PORT_UART3 0x08 | ||
| 36 | #define EP93XX_DMA_M2P_PORT_IRDA 0x09 | ||
| 37 | #define EP93XX_DMA_M2P_PORT_MASK 0x0f | ||
| 38 | #define EP93XX_DMA_M2P_TX 0x00 | ||
| 39 | #define EP93XX_DMA_M2P_RX 0x10 | ||
| 40 | #define EP93XX_DMA_M2P_ABORT_ON_ERROR 0x20 | ||
| 41 | #define EP93XX_DMA_M2P_IGNORE_ERROR 0x40 | ||
| 42 | #define EP93XX_DMA_M2P_ERROR_MASK 0x60 | ||
| 43 | |||
| 44 | int ep93xx_dma_m2p_client_register(struct ep93xx_dma_m2p_client *m2p); | ||
| 45 | void ep93xx_dma_m2p_client_unregister(struct ep93xx_dma_m2p_client *m2p); | ||
| 46 | void ep93xx_dma_m2p_submit(struct ep93xx_dma_m2p_client *m2p, | ||
| 47 | struct ep93xx_dma_buffer *buf); | ||
| 48 | void ep93xx_dma_m2p_submit_recursive(struct ep93xx_dma_m2p_client *m2p, | ||
| 49 | struct ep93xx_dma_buffer *buf); | ||
| 50 | void ep93xx_dma_m2p_flush(struct ep93xx_dma_m2p_client *m2p); | ||
| 51 | |||
| 52 | #endif /* __ASM_ARCH_DMA_H */ | ||
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h index 22d6c9a6e4ca..f66be12b856e 100644 --- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h +++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h | |||
| @@ -58,7 +58,8 @@ | |||
| 58 | 58 | ||
| 59 | 59 | ||
| 60 | /* AHB peripherals */ | 60 | /* AHB peripherals */ |
| 61 | #define EP93XX_DMA_BASE (EP93XX_AHB_VIRT_BASE + 0x00000000) | 61 | #define EP93XX_DMA_BASE ((void __iomem *) \ |
| 62 | (EP93XX_AHB_VIRT_BASE + 0x00000000)) | ||
| 62 | 63 | ||
| 63 | #define EP93XX_ETHERNET_BASE (EP93XX_AHB_VIRT_BASE + 0x00010000) | 64 | #define EP93XX_ETHERNET_BASE (EP93XX_AHB_VIRT_BASE + 0x00010000) |
| 64 | #define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000) | 65 | #define EP93XX_ETHERNET_PHYS_BASE (EP93XX_AHB_PHYS_BASE + 0x00010000) |
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h index 88f7e88f152f..05f0f4f2f3ce 100644 --- a/arch/arm/mach-ep93xx/include/mach/platform.h +++ b/arch/arm/mach-ep93xx/include/mach/platform.h | |||
| @@ -4,6 +4,8 @@ | |||
| 4 | 4 | ||
| 5 | #ifndef __ASSEMBLY__ | 5 | #ifndef __ASSEMBLY__ |
| 6 | 6 | ||
| 7 | struct i2c_board_info; | ||
| 8 | |||
| 7 | struct ep93xx_eth_data | 9 | struct ep93xx_eth_data |
| 8 | { | 10 | { |
| 9 | unsigned char dev_addr[6]; | 11 | unsigned char dev_addr[6]; |
diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h index 67789d0f329e..ed8f35e4f068 100644 --- a/arch/arm/mach-ep93xx/include/mach/system.h +++ b/arch/arm/mach-ep93xx/include/mach/system.h | |||
| @@ -9,7 +9,7 @@ static inline void arch_idle(void) | |||
| 9 | cpu_do_idle(); | 9 | cpu_do_idle(); |
| 10 | } | 10 | } |
| 11 | 11 | ||
| 12 | static inline void arch_reset(char mode) | 12 | static inline void arch_reset(char mode, const char *cmd) |
| 13 | { | 13 | { |
| 14 | u32 devicecfg; | 14 | u32 devicecfg; |
| 15 | 15 | ||
diff --git a/arch/arm/mach-footbridge/dma.c b/arch/arm/mach-footbridge/dma.c index 4f3506346969..e2e0df8bcee2 100644 --- a/arch/arm/mach-footbridge/dma.c +++ b/arch/arm/mach-footbridge/dma.c | |||
| @@ -21,16 +21,16 @@ | |||
| 21 | #include <asm/hardware/dec21285.h> | 21 | #include <asm/hardware/dec21285.h> |
| 22 | 22 | ||
| 23 | #if 0 | 23 | #if 0 |
| 24 | static int fb_dma_request(dmach_t channel, dma_t *dma) | 24 | static int fb_dma_request(unsigned int chan, dma_t *dma) |
| 25 | { | 25 | { |
| 26 | return -EINVAL; | 26 | return -EINVAL; |
| 27 | } | 27 | } |
| 28 | 28 | ||
| 29 | static void fb_dma_enable(dmach_t channel, dma_t *dma) | 29 | static void fb_dma_enable(unsigned int chan, dma_t *dma) |
| 30 | { | 30 | { |
| 31 | } | 31 | } |
| 32 | 32 | ||
| 33 | static void fb_dma_disable(dmach_t channel, dma_t *dma) | 33 | static void fb_dma_disable(unsigned int chan, dma_t *dma) |
| 34 | { | 34 | { |
| 35 | } | 35 | } |
| 36 | 36 | ||
| @@ -42,7 +42,7 @@ static struct dma_ops fb_dma_ops = { | |||
| 42 | }; | 42 | }; |
| 43 | #endif | 43 | #endif |
| 44 | 44 | ||
| 45 | void __init arch_dma_init(dma_t *dma) | 45 | static int __init fb_dma_init(void) |
| 46 | { | 46 | { |
| 47 | #if 0 | 47 | #if 0 |
| 48 | dma[_DC21285_DMA(0)].d_ops = &fb_dma_ops; | 48 | dma[_DC21285_DMA(0)].d_ops = &fb_dma_ops; |
| @@ -50,6 +50,8 @@ void __init arch_dma_init(dma_t *dma) | |||
| 50 | #endif | 50 | #endif |
| 51 | #ifdef CONFIG_ISA_DMA | 51 | #ifdef CONFIG_ISA_DMA |
| 52 | if (footbridge_cfn_mode()) | 52 | if (footbridge_cfn_mode()) |
| 53 | isa_init_dma(dma + _ISA_DMA(0)); | 53 | isa_init_dma(); |
| 54 | #endif | 54 | #endif |
| 55 | return 0; | ||
| 55 | } | 56 | } |
| 57 | core_initcall(fb_dma_init); | ||
diff --git a/arch/arm/mach-footbridge/include/mach/system.h b/arch/arm/mach-footbridge/include/mach/system.h index 2db7f36bd6ca..0b2931566209 100644 --- a/arch/arm/mach-footbridge/include/mach/system.h +++ b/arch/arm/mach-footbridge/include/mach/system.h | |||
| @@ -18,7 +18,7 @@ static inline void arch_idle(void) | |||
| 18 | cpu_do_idle(); | 18 | cpu_do_idle(); |
| 19 | } | 19 | } |
| 20 | 20 | ||
| 21 | static inline void arch_reset(char mode) | 21 | static inline void arch_reset(char mode, const char *cmd) |
| 22 | { | 22 | { |
| 23 | if (mode == 's') { | 23 | if (mode == 's') { |
| 24 | /* | 24 | /* |
diff --git a/arch/arm/mach-h720x/include/mach/system.h b/arch/arm/mach-h720x/include/mach/system.h index e4a7c760d52a..a708d24ee46d 100644 --- a/arch/arm/mach-h720x/include/mach/system.h +++ b/arch/arm/mach-h720x/include/mach/system.h | |||
| @@ -25,7 +25,7 @@ static void arch_idle(void) | |||
| 25 | } | 25 | } |
| 26 | 26 | ||
| 27 | 27 | ||
| 28 | static __inline__ void arch_reset(char mode) | 28 | static __inline__ void arch_reset(char mode, const char *cmd) |
| 29 | { | 29 | { |
| 30 | CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET; | 30 | CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET; |
| 31 | } | 31 | } |
diff --git a/arch/arm/mach-imx/include/mach/system.h b/arch/arm/mach-imx/include/mach/system.h index adee7e51bab2..46d4ca91af79 100644 --- a/arch/arm/mach-imx/include/mach/system.h +++ b/arch/arm/mach-imx/include/mach/system.h | |||
| @@ -32,7 +32,7 @@ arch_idle(void) | |||
| 32 | } | 32 | } |
| 33 | 33 | ||
| 34 | static inline void | 34 | static inline void |
| 35 | arch_reset(char mode) | 35 | arch_reset(char mode, const char *cmd) |
| 36 | { | 36 | { |
| 37 | cpu_reset(0); | 37 | cpu_reset(0); |
| 38 | } | 38 | } |
diff --git a/arch/arm/mach-integrator/include/mach/system.h b/arch/arm/mach-integrator/include/mach/system.h index c485345c8c77..e1551b8dab77 100644 --- a/arch/arm/mach-integrator/include/mach/system.h +++ b/arch/arm/mach-integrator/include/mach/system.h | |||
| @@ -32,7 +32,7 @@ static inline void arch_idle(void) | |||
| 32 | cpu_do_idle(); | 32 | cpu_do_idle(); |
| 33 | } | 33 | } |
| 34 | 34 | ||
| 35 | static inline void arch_reset(char mode) | 35 | static inline void arch_reset(char mode, const char *cmd) |
| 36 | { | 36 | { |
| 37 | /* | 37 | /* |
| 38 | * To reset, we hit the on-board reset register | 38 | * To reset, we hit the on-board reset register |
diff --git a/arch/arm/mach-iop13xx/include/mach/memory.h b/arch/arm/mach-iop13xx/include/mach/memory.h index e012bf13c955..42ae29b288a1 100644 --- a/arch/arm/mach-iop13xx/include/mach/memory.h +++ b/arch/arm/mach-iop13xx/include/mach/memory.h | |||
| @@ -59,7 +59,10 @@ static inline unsigned long __lbus_to_virt(dma_addr_t x) | |||
| 59 | }) | 59 | }) |
| 60 | 60 | ||
| 61 | #define __arch_page_to_dma(dev, page) \ | 61 | #define __arch_page_to_dma(dev, page) \ |
| 62 | __arch_virt_to_dma(dev, page_address(page)) | 62 | ({ \ |
| 63 | /* __is_lbus_virt() can never be true for RAM pages */ \ | ||
| 64 | (dma_addr_t)page_to_phys(page); \ | ||
| 65 | }) | ||
| 63 | 66 | ||
| 64 | #endif /* CONFIG_ARCH_IOP13XX */ | 67 | #endif /* CONFIG_ARCH_IOP13XX */ |
| 65 | #endif /* !ASSEMBLY */ | 68 | #endif /* !ASSEMBLY */ |
diff --git a/arch/arm/mach-iop13xx/include/mach/system.h b/arch/arm/mach-iop13xx/include/mach/system.h index c7127f416e1f..d0c66ef450a7 100644 --- a/arch/arm/mach-iop13xx/include/mach/system.h +++ b/arch/arm/mach-iop13xx/include/mach/system.h | |||
| @@ -13,7 +13,7 @@ static inline void arch_idle(void) | |||
| 13 | cpu_do_idle(); | 13 | cpu_do_idle(); |
| 14 | } | 14 | } |
| 15 | 15 | ||
| 16 | static inline void arch_reset(char mode) | 16 | static inline void arch_reset(char mode, const char *cmd) |
| 17 | { | 17 | { |
| 18 | /* | 18 | /* |
| 19 | * Reset the internal bus (warning both cores are reset) | 19 | * Reset the internal bus (warning both cores are reset) |
diff --git a/arch/arm/mach-iop32x/include/mach/system.h b/arch/arm/mach-iop32x/include/mach/system.h index 32d9e5b0a28d..a4b808fe0d81 100644 --- a/arch/arm/mach-iop32x/include/mach/system.h +++ b/arch/arm/mach-iop32x/include/mach/system.h | |||
| @@ -16,7 +16,7 @@ static inline void arch_idle(void) | |||
| 16 | cpu_do_idle(); | 16 | cpu_do_idle(); |
| 17 | } | 17 | } |
| 18 | 18 | ||
| 19 | static inline void arch_reset(char mode) | 19 | static inline void arch_reset(char mode, const char *cmd) |
| 20 | { | 20 | { |
| 21 | local_irq_disable(); | 21 | local_irq_disable(); |
| 22 | 22 | ||
diff --git a/arch/arm/mach-iop33x/include/mach/system.h b/arch/arm/mach-iop33x/include/mach/system.h index 0cb3ad862acd..f192a34be073 100644 --- a/arch/arm/mach-iop33x/include/mach/system.h +++ b/arch/arm/mach-iop33x/include/mach/system.h | |||
| @@ -14,7 +14,7 @@ static inline void arch_idle(void) | |||
| 14 | cpu_do_idle(); | 14 | cpu_do_idle(); |
| 15 | } | 15 | } |
| 16 | 16 | ||
| 17 | static inline void arch_reset(char mode) | 17 | static inline void arch_reset(char mode, const char *cmd) |
| 18 | { | 18 | { |
| 19 | *IOP3XX_PCSR = 0x30; | 19 | *IOP3XX_PCSR = 0x30; |
| 20 | 20 | ||
diff --git a/arch/arm/mach-ixp2000/include/mach/system.h b/arch/arm/mach-ixp2000/include/mach/system.h index 2e9c68f95a24..de370992c848 100644 --- a/arch/arm/mach-ixp2000/include/mach/system.h +++ b/arch/arm/mach-ixp2000/include/mach/system.h | |||
| @@ -17,7 +17,7 @@ static inline void arch_idle(void) | |||
| 17 | cpu_do_idle(); | 17 | cpu_do_idle(); |
| 18 | } | 18 | } |
| 19 | 19 | ||
| 20 | static inline void arch_reset(char mode) | 20 | static inline void arch_reset(char mode, const char *cmd) |
| 21 | { | 21 | { |
| 22 | local_irq_disable(); | 22 | local_irq_disable(); |
| 23 | 23 | ||
diff --git a/arch/arm/mach-ixp23xx/include/mach/system.h b/arch/arm/mach-ixp23xx/include/mach/system.h index d57c3fc10f1f..8920ff2dff1f 100644 --- a/arch/arm/mach-ixp23xx/include/mach/system.h +++ b/arch/arm/mach-ixp23xx/include/mach/system.h | |||
| @@ -19,7 +19,7 @@ static inline void arch_idle(void) | |||
| 19 | #endif | 19 | #endif |
| 20 | } | 20 | } |
| 21 | 21 | ||
| 22 | static inline void arch_reset(char mode) | 22 | static inline void arch_reset(char mode, const char *cmd) |
| 23 | { | 23 | { |
| 24 | /* First try machine specific support */ | 24 | /* First try machine specific support */ |
| 25 | if (machine_is_ixdp2351()) { | 25 | if (machine_is_ixdp2351()) { |
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c index d816c51320c7..70afcfe5b881 100644 --- a/arch/arm/mach-ixp4xx/common-pci.c +++ b/arch/arm/mach-ixp4xx/common-pci.c | |||
| @@ -366,7 +366,7 @@ void __init ixp4xx_adjust_zones(int node, unsigned long *zone_size, | |||
| 366 | } | 366 | } |
| 367 | 367 | ||
| 368 | void __init ixp4xx_pci_preinit(void) | 368 | void __init ixp4xx_pci_preinit(void) |
| 369 | { | 369 | { |
| 370 | unsigned long cpuid = read_cpuid_id(); | 370 | unsigned long cpuid = read_cpuid_id(); |
| 371 | 371 | ||
| 372 | /* | 372 | /* |
| @@ -386,17 +386,17 @@ void __init ixp4xx_pci_preinit(void) | |||
| 386 | 386 | ||
| 387 | pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); | 387 | pr_debug("setup PCI-AHB(inbound) and AHB-PCI(outbound) address mappings\n"); |
| 388 | 388 | ||
| 389 | /* | 389 | /* |
| 390 | * We use identity AHB->PCI address translation | 390 | * We use identity AHB->PCI address translation |
| 391 | * in the 0x48000000 to 0x4bffffff address space | 391 | * in the 0x48000000 to 0x4bffffff address space |
| 392 | */ | 392 | */ |
| 393 | *PCI_PCIMEMBASE = 0x48494A4B; | 393 | *PCI_PCIMEMBASE = 0x48494A4B; |
| 394 | 394 | ||
| 395 | /* | 395 | /* |
| 396 | * We also use identity PCI->AHB address translation | 396 | * We also use identity PCI->AHB address translation |
| 397 | * in 4 16MB BARs that begin at the physical memory start | 397 | * in 4 16MB BARs that begin at the physical memory start |
| 398 | */ | 398 | */ |
| 399 | *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) + | 399 | *PCI_AHBMEMBASE = (PHYS_OFFSET & 0xFF000000) + |
| 400 | ((PHYS_OFFSET & 0xFF000000) >> 8) + | 400 | ((PHYS_OFFSET & 0xFF000000) >> 8) + |
| 401 | ((PHYS_OFFSET & 0xFF000000) >> 16) + | 401 | ((PHYS_OFFSET & 0xFF000000) >> 16) + |
| 402 | ((PHYS_OFFSET & 0xFF000000) >> 24) + | 402 | ((PHYS_OFFSET & 0xFF000000) >> 24) + |
| @@ -408,18 +408,19 @@ void __init ixp4xx_pci_preinit(void) | |||
| 408 | pr_debug("setup BARs in controller\n"); | 408 | pr_debug("setup BARs in controller\n"); |
| 409 | 409 | ||
| 410 | /* | 410 | /* |
| 411 | * We configure the PCI inbound memory windows to be | 411 | * We configure the PCI inbound memory windows to be |
| 412 | * 1:1 mapped to SDRAM | 412 | * 1:1 mapped to SDRAM |
| 413 | */ | 413 | */ |
| 414 | local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET + 0x00000000); | 414 | local_write_config(PCI_BASE_ADDRESS_0, 4, PHYS_OFFSET); |
| 415 | local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + 0x01000000); | 415 | local_write_config(PCI_BASE_ADDRESS_1, 4, PHYS_OFFSET + SZ_16M); |
| 416 | local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + 0x02000000); | 416 | local_write_config(PCI_BASE_ADDRESS_2, 4, PHYS_OFFSET + SZ_32M); |
| 417 | local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + 0x03000000); | 417 | local_write_config(PCI_BASE_ADDRESS_3, 4, PHYS_OFFSET + SZ_48M); |
| 418 | 418 | ||
| 419 | /* | 419 | /* |
| 420 | * Enable CSR window at 0xff000000. | 420 | * Enable CSR window at 64 MiB to allow PCI masters |
| 421 | * to continue prefetching past 64 MiB boundary. | ||
| 421 | */ | 422 | */ |
| 422 | local_write_config(PCI_BASE_ADDRESS_4, 4, 0xff000008); | 423 | local_write_config(PCI_BASE_ADDRESS_4, 4, PHYS_OFFSET + SZ_64M); |
| 423 | 424 | ||
| 424 | /* | 425 | /* |
| 425 | * Enable the IO window to be way up high, at 0xfffffc00 | 426 | * Enable the IO window to be way up high, at 0xfffffc00 |
| @@ -500,7 +501,7 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys) | |||
| 500 | return 1; | 501 | return 1; |
| 501 | } | 502 | } |
| 502 | 503 | ||
| 503 | struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) | 504 | struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys) |
| 504 | { | 505 | { |
| 505 | return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys); | 506 | return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys); |
| 506 | } | 507 | } |
diff --git a/arch/arm/mach-ixp4xx/include/mach/cpu.h b/arch/arm/mach-ixp4xx/include/mach/cpu.h index 51bd69c46d94..def7773be67c 100644 --- a/arch/arm/mach-ixp4xx/include/mach/cpu.h +++ b/arch/arm/mach-ixp4xx/include/mach/cpu.h | |||
| @@ -17,26 +17,31 @@ | |||
| 17 | #include <asm/cputype.h> | 17 | #include <asm/cputype.h> |
| 18 | 18 | ||
| 19 | /* Processor id value in CP15 Register 0 */ | 19 | /* Processor id value in CP15 Register 0 */ |
| 20 | #define IXP425_PROCESSOR_ID_VALUE 0x690541c0 | 20 | #define IXP42X_PROCESSOR_ID_VALUE 0x690541c0 /* including unused 0x690541Ex */ |
| 21 | #define IXP435_PROCESSOR_ID_VALUE 0x69054040 | 21 | #define IXP42X_PROCESSOR_ID_MASK 0xffffffc0 |
| 22 | #define IXP465_PROCESSOR_ID_VALUE 0x69054200 | 22 | |
| 23 | #define IXP4XX_PROCESSOR_ID_MASK 0xfffffff0 | 23 | #define IXP43X_PROCESSOR_ID_VALUE 0x69054040 |
| 24 | 24 | #define IXP43X_PROCESSOR_ID_MASK 0xfffffff0 | |
| 25 | #define cpu_is_ixp42x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \ | 25 | |
| 26 | IXP425_PROCESSOR_ID_VALUE) | 26 | #define IXP46X_PROCESSOR_ID_VALUE 0x69054200 /* including IXP455 */ |
| 27 | #define cpu_is_ixp43x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \ | 27 | #define IXP46X_PROCESSOR_ID_MASK 0xfffffff0 |
| 28 | IXP435_PROCESSOR_ID_VALUE) | 28 | |
| 29 | #define cpu_is_ixp46x() ((read_cpuid_id() & IXP4XX_PROCESSOR_ID_MASK) == \ | 29 | #define cpu_is_ixp42x() ((read_cpuid_id() & IXP42X_PROCESSOR_ID_MASK) == \ |
| 30 | IXP465_PROCESSOR_ID_VALUE) | 30 | IXP42X_PROCESSOR_ID_VALUE) |
| 31 | #define cpu_is_ixp43x() ((read_cpuid_id() & IXP43X_PROCESSOR_ID_MASK) == \ | ||
| 32 | IXP43X_PROCESSOR_ID_VALUE) | ||
| 33 | #define cpu_is_ixp46x() ((read_cpuid_id() & IXP46X_PROCESSOR_ID_MASK) == \ | ||
| 34 | IXP46X_PROCESSOR_ID_VALUE) | ||
| 31 | 35 | ||
| 32 | static inline u32 ixp4xx_read_feature_bits(void) | 36 | static inline u32 ixp4xx_read_feature_bits(void) |
| 33 | { | 37 | { |
| 34 | unsigned int val = ~*IXP4XX_EXP_CFG2; | 38 | unsigned int val = ~*IXP4XX_EXP_CFG2; |
| 35 | val &= ~IXP4XX_FEATURE_RESERVED; | ||
| 36 | if (!cpu_is_ixp46x()) | ||
| 37 | val &= ~IXP4XX_FEATURE_IXP46X_ONLY; | ||
| 38 | 39 | ||
| 39 | return val; | 40 | if (cpu_is_ixp42x()) |
| 41 | return val & IXP42X_FEATURE_MASK; | ||
| 42 | if (cpu_is_ixp43x()) | ||
| 43 | return val & IXP43X_FEATURE_MASK; | ||
| 44 | return val & IXP46X_FEATURE_MASK; | ||
| 40 | } | 45 | } |
| 41 | 46 | ||
| 42 | static inline void ixp4xx_write_feature_bits(u32 value) | 47 | static inline void ixp4xx_write_feature_bits(u32 value) |
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h index ad9c888dd850..97c530f66e78 100644 --- a/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h +++ b/arch/arm/mach-ixp4xx/include/mach/ixp4xx-regs.h | |||
| @@ -604,6 +604,7 @@ | |||
| 604 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | 604 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ |
| 605 | 605 | ||
| 606 | /* "fuse" bits of IXP_EXP_CFG2 */ | 606 | /* "fuse" bits of IXP_EXP_CFG2 */ |
| 607 | /* All IXP4xx CPUs */ | ||
| 607 | #define IXP4XX_FEATURE_RCOMP (1 << 0) | 608 | #define IXP4XX_FEATURE_RCOMP (1 << 0) |
| 608 | #define IXP4XX_FEATURE_USB_DEVICE (1 << 1) | 609 | #define IXP4XX_FEATURE_USB_DEVICE (1 << 1) |
| 609 | #define IXP4XX_FEATURE_HASH (1 << 2) | 610 | #define IXP4XX_FEATURE_HASH (1 << 2) |
| @@ -619,20 +620,41 @@ | |||
| 619 | #define IXP4XX_FEATURE_RESET_NPEB (1 << 12) | 620 | #define IXP4XX_FEATURE_RESET_NPEB (1 << 12) |
| 620 | #define IXP4XX_FEATURE_RESET_NPEC (1 << 13) | 621 | #define IXP4XX_FEATURE_RESET_NPEC (1 << 13) |
| 621 | #define IXP4XX_FEATURE_PCI (1 << 14) | 622 | #define IXP4XX_FEATURE_PCI (1 << 14) |
| 622 | #define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) | ||
| 623 | #define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) | 623 | #define IXP4XX_FEATURE_UTOPIA_PHY_LIMIT (3 << 16) |
| 624 | #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) | ||
| 625 | #define IXP42X_FEATURE_MASK (IXP4XX_FEATURE_RCOMP | \ | ||
| 626 | IXP4XX_FEATURE_USB_DEVICE | \ | ||
| 627 | IXP4XX_FEATURE_HASH | \ | ||
| 628 | IXP4XX_FEATURE_AES | \ | ||
| 629 | IXP4XX_FEATURE_DES | \ | ||
| 630 | IXP4XX_FEATURE_HDLC | \ | ||
| 631 | IXP4XX_FEATURE_AAL | \ | ||
| 632 | IXP4XX_FEATURE_HSS | \ | ||
| 633 | IXP4XX_FEATURE_UTOPIA | \ | ||
| 634 | IXP4XX_FEATURE_NPEB_ETH0 | \ | ||
| 635 | IXP4XX_FEATURE_NPEC_ETH | \ | ||
| 636 | IXP4XX_FEATURE_RESET_NPEA | \ | ||
| 637 | IXP4XX_FEATURE_RESET_NPEB | \ | ||
| 638 | IXP4XX_FEATURE_RESET_NPEC | \ | ||
| 639 | IXP4XX_FEATURE_PCI | \ | ||
| 640 | IXP4XX_FEATURE_UTOPIA_PHY_LIMIT | \ | ||
| 641 | IXP4XX_FEATURE_XSCALE_MAX_FREQ) | ||
| 642 | |||
| 643 | |||
| 644 | /* IXP43x/46x CPUs */ | ||
| 645 | #define IXP4XX_FEATURE_ECC_TIMESYNC (1 << 15) | ||
| 624 | #define IXP4XX_FEATURE_USB_HOST (1 << 18) | 646 | #define IXP4XX_FEATURE_USB_HOST (1 << 18) |
| 625 | #define IXP4XX_FEATURE_NPEA_ETH (1 << 19) | 647 | #define IXP4XX_FEATURE_NPEA_ETH (1 << 19) |
| 648 | #define IXP43X_FEATURE_MASK (IXP42X_FEATURE_MASK | \ | ||
| 649 | IXP4XX_FEATURE_ECC_TIMESYNC | \ | ||
| 650 | IXP4XX_FEATURE_USB_HOST | \ | ||
| 651 | IXP4XX_FEATURE_NPEA_ETH) | ||
| 652 | |||
| 653 | /* IXP46x CPU (including IXP455) only */ | ||
| 626 | #define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) | 654 | #define IXP4XX_FEATURE_NPEB_ETH_1_TO_3 (1 << 20) |
| 627 | #define IXP4XX_FEATURE_RSA (1 << 21) | 655 | #define IXP4XX_FEATURE_RSA (1 << 21) |
| 628 | #define IXP4XX_FEATURE_XSCALE_MAX_FREQ (3 << 22) | 656 | #define IXP46X_FEATURE_MASK (IXP43X_FEATURE_MASK | \ |
| 629 | #define IXP4XX_FEATURE_RESERVED (0xFF << 24) | 657 | IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ |
| 630 | 658 | IXP4XX_FEATURE_RSA) | |
| 631 | #define IXP4XX_FEATURE_IXP46X_ONLY (IXP4XX_FEATURE_ECC_TIMESYNC | \ | ||
| 632 | IXP4XX_FEATURE_USB_HOST | \ | ||
| 633 | IXP4XX_FEATURE_NPEA_ETH | \ | ||
| 634 | IXP4XX_FEATURE_NPEB_ETH_1_TO_3 | \ | ||
| 635 | IXP4XX_FEATURE_RSA | \ | ||
| 636 | IXP4XX_FEATURE_XSCALE_MAX_FREQ) | ||
| 637 | 659 | ||
| 638 | #endif | 660 | #endif |
diff --git a/arch/arm/mach-ixp4xx/include/mach/system.h b/arch/arm/mach-ixp4xx/include/mach/system.h index 92a7e8ddf69a..d2aa26f5acd7 100644 --- a/arch/arm/mach-ixp4xx/include/mach/system.h +++ b/arch/arm/mach-ixp4xx/include/mach/system.h | |||
| @@ -20,7 +20,7 @@ static inline void arch_idle(void) | |||
| 20 | } | 20 | } |
| 21 | 21 | ||
| 22 | 22 | ||
| 23 | static inline void arch_reset(char mode) | 23 | static inline void arch_reset(char mode, const char *cmd) |
| 24 | { | 24 | { |
| 25 | if ( 1 && mode == 's') { | 25 | if ( 1 && mode == 's') { |
| 26 | /* Jump into ROM at address 0 */ | 26 | /* Jump into ROM at address 0 */ |
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c index c73a94d0ca2b..252310234903 100644 --- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c +++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c | |||
| @@ -575,8 +575,8 @@ int npe_load_firmware(struct npe *npe, const char *name, struct device *dev) | |||
| 575 | for (i = 0; i < image->size; i++) | 575 | for (i = 0; i < image->size; i++) |
| 576 | image->data[i] = swab32(image->data[i]); | 576 | image->data[i] = swab32(image->data[i]); |
| 577 | 577 | ||
| 578 | if (!cpu_is_ixp46x() && ((image->id >> 28) & 0xF /* device ID */)) { | 578 | if (cpu_is_ixp42x() && ((image->id >> 28) & 0xF /* device ID */)) { |
| 579 | print_npe(KERN_INFO, npe, "IXP46x firmware ignored on " | 579 | print_npe(KERN_INFO, npe, "IXP43x/IXP46x firmware ignored on " |
| 580 | "IXP42x\n"); | 580 | "IXP42x\n"); |
| 581 | goto err; | 581 | goto err; |
| 582 | } | 582 | } |
| @@ -596,7 +596,7 @@ int npe_load_firmware(struct npe *npe, const char *name, struct device *dev) | |||
| 596 | "revision 0x%X:%X\n", (image->id >> 16) & 0xFF, | 596 | "revision 0x%X:%X\n", (image->id >> 16) & 0xFF, |
| 597 | (image->id >> 8) & 0xFF, image->id & 0xFF); | 597 | (image->id >> 8) & 0xFF, image->id & 0xFF); |
| 598 | 598 | ||
| 599 | if (!cpu_is_ixp46x()) { | 599 | if (cpu_is_ixp42x()) { |
| 600 | if (!npe->id) | 600 | if (!npe->id) |
| 601 | instr_size = NPE_A_42X_INSTR_SIZE; | 601 | instr_size = NPE_A_42X_INSTR_SIZE; |
| 602 | else | 602 | else |
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 3600cd9f0519..b5421cccd7e1 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig | |||
| @@ -20,6 +20,18 @@ config MACH_RD88F6281 | |||
| 20 | Say 'Y' here if you want your kernel to support the | 20 | Say 'Y' here if you want your kernel to support the |
| 21 | Marvell RD-88F6281 Reference Board. | 21 | Marvell RD-88F6281 Reference Board. |
| 22 | 22 | ||
| 23 | config MACH_SHEEVAPLUG | ||
| 24 | bool "Marvell SheevaPlug Reference Board" | ||
| 25 | help | ||
| 26 | Say 'Y' here if you want your kernel to support the | ||
| 27 | Marvell SheevaPlug Reference Board. | ||
| 28 | |||
| 29 | config MACH_TS219 | ||
| 30 | bool "QNAP TS-119 and TS-219 Turbo NAS" | ||
| 31 | help | ||
| 32 | Say 'Y' here if you want your kernel to support the | ||
| 33 | QNAP TS-119 and TS-219 Turbo NAS devices. | ||
| 34 | |||
| 23 | endmenu | 35 | endmenu |
| 24 | 36 | ||
| 25 | endif | 37 | endif |
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile index b96c55dad343..8f03c9b9bdd9 100644 --- a/arch/arm/mach-kirkwood/Makefile +++ b/arch/arm/mach-kirkwood/Makefile | |||
| @@ -1,5 +1,7 @@ | |||
| 1 | obj-y += common.o addr-map.o irq.o pcie.o | 1 | obj-y += common.o addr-map.o irq.o pcie.o mpp.o |
| 2 | 2 | ||
| 3 | obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o | 3 | obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o |
| 4 | obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o | 4 | obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o |
| 5 | obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o | 5 | obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o |
| 6 | obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o | ||
| 7 | obj-$(CONFIG_MACH_TS219) += ts219-setup.o | ||
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c index b3404b7775b3..19b03f62c3f4 100644 --- a/arch/arm/mach-kirkwood/common.c +++ b/arch/arm/mach-kirkwood/common.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <linux/serial_8250.h> | 14 | #include <linux/serial_8250.h> |
| 15 | #include <linux/mbus.h> | 15 | #include <linux/mbus.h> |
| 16 | #include <linux/mv643xx_eth.h> | 16 | #include <linux/mv643xx_eth.h> |
| 17 | #include <linux/mv643xx_i2c.h> | ||
| 17 | #include <linux/ata_platform.h> | 18 | #include <linux/ata_platform.h> |
| 18 | #include <linux/spi/orion_spi.h> | 19 | #include <linux/spi/orion_spi.h> |
| 19 | #include <net/dsa.h> | 20 | #include <net/dsa.h> |
| @@ -24,6 +25,7 @@ | |||
| 24 | #include <mach/kirkwood.h> | 25 | #include <mach/kirkwood.h> |
| 25 | #include <plat/cache-feroceon-l2.h> | 26 | #include <plat/cache-feroceon-l2.h> |
| 26 | #include <plat/ehci-orion.h> | 27 | #include <plat/ehci-orion.h> |
| 28 | #include <plat/mvsdio.h> | ||
| 27 | #include <plat/mv_xor.h> | 29 | #include <plat/mv_xor.h> |
| 28 | #include <plat/orion_nand.h> | 30 | #include <plat/orion_nand.h> |
| 29 | #include <plat/time.h> | 31 | #include <plat/time.h> |
| @@ -254,7 +256,7 @@ static struct resource kirkwood_rtc_resource = { | |||
| 254 | .flags = IORESOURCE_MEM, | 256 | .flags = IORESOURCE_MEM, |
| 255 | }; | 257 | }; |
| 256 | 258 | ||
| 257 | void __init kirkwood_rtc_init(void) | 259 | static void __init kirkwood_rtc_init(void) |
| 258 | { | 260 | { |
| 259 | platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1); | 261 | platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1); |
| 260 | } | 262 | } |
| @@ -296,6 +298,50 @@ void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data) | |||
| 296 | 298 | ||
| 297 | 299 | ||
| 298 | /***************************************************************************** | 300 | /***************************************************************************** |
| 301 | * SD/SDIO/MMC | ||
| 302 | ****************************************************************************/ | ||
| 303 | static struct resource mvsdio_resources[] = { | ||
| 304 | [0] = { | ||
| 305 | .start = SDIO_PHYS_BASE, | ||
| 306 | .end = SDIO_PHYS_BASE + SZ_1K - 1, | ||
| 307 | .flags = IORESOURCE_MEM, | ||
| 308 | }, | ||
| 309 | [1] = { | ||
| 310 | .start = IRQ_KIRKWOOD_SDIO, | ||
| 311 | .end = IRQ_KIRKWOOD_SDIO, | ||
| 312 | .flags = IORESOURCE_IRQ, | ||
| 313 | }, | ||
| 314 | }; | ||
| 315 | |||
| 316 | static u64 mvsdio_dmamask = 0xffffffffUL; | ||
| 317 | |||
| 318 | static struct platform_device kirkwood_sdio = { | ||
| 319 | .name = "mvsdio", | ||
| 320 | .id = -1, | ||
| 321 | .dev = { | ||
| 322 | .dma_mask = &mvsdio_dmamask, | ||
| 323 | .coherent_dma_mask = 0xffffffff, | ||
| 324 | }, | ||
| 325 | .num_resources = ARRAY_SIZE(mvsdio_resources), | ||
| 326 | .resource = mvsdio_resources, | ||
| 327 | }; | ||
| 328 | |||
| 329 | void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data) | ||
| 330 | { | ||
| 331 | u32 dev, rev; | ||
| 332 | |||
| 333 | kirkwood_pcie_id(&dev, &rev); | ||
| 334 | if (rev == 0) /* catch all Kirkwood Z0's */ | ||
| 335 | mvsdio_data->clock = 100000000; | ||
| 336 | else | ||
| 337 | mvsdio_data->clock = 200000000; | ||
| 338 | mvsdio_data->dram = &kirkwood_mbus_dram_info; | ||
| 339 | kirkwood_sdio.dev.platform_data = mvsdio_data; | ||
| 340 | platform_device_register(&kirkwood_sdio); | ||
| 341 | } | ||
| 342 | |||
| 343 | |||
| 344 | /***************************************************************************** | ||
| 299 | * SPI | 345 | * SPI |
| 300 | ****************************************************************************/ | 346 | ****************************************************************************/ |
| 301 | static struct orion_spi_info kirkwood_spi_plat_data = { | 347 | static struct orion_spi_info kirkwood_spi_plat_data = { |
| @@ -326,6 +372,45 @@ void __init kirkwood_spi_init() | |||
| 326 | 372 | ||
| 327 | 373 | ||
| 328 | /***************************************************************************** | 374 | /***************************************************************************** |
| 375 | * I2C | ||
| 376 | ****************************************************************************/ | ||
| 377 | static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = { | ||
| 378 | .freq_m = 8, /* assumes 166 MHz TCLK */ | ||
| 379 | .freq_n = 3, | ||
| 380 | .timeout = 1000, /* Default timeout of 1 second */ | ||
| 381 | }; | ||
| 382 | |||
| 383 | static struct resource kirkwood_i2c_resources[] = { | ||
| 384 | { | ||
| 385 | .name = "i2c", | ||
| 386 | .start = I2C_PHYS_BASE, | ||
| 387 | .end = I2C_PHYS_BASE + 0x1f, | ||
| 388 | .flags = IORESOURCE_MEM, | ||
| 389 | }, { | ||
| 390 | .name = "i2c", | ||
| 391 | .start = IRQ_KIRKWOOD_TWSI, | ||
| 392 | .end = IRQ_KIRKWOOD_TWSI, | ||
| 393 | .flags = IORESOURCE_IRQ, | ||
| 394 | }, | ||
| 395 | }; | ||
| 396 | |||
| 397 | static struct platform_device kirkwood_i2c = { | ||
| 398 | .name = MV64XXX_I2C_CTLR_NAME, | ||
| 399 | .id = 0, | ||
| 400 | .num_resources = ARRAY_SIZE(kirkwood_i2c_resources), | ||
| 401 | .resource = kirkwood_i2c_resources, | ||
| 402 | .dev = { | ||
| 403 | .platform_data = &kirkwood_i2c_pdata, | ||
| 404 | }, | ||
| 405 | }; | ||
| 406 | |||
| 407 | void __init kirkwood_i2c_init(void) | ||
| 408 | { | ||
| 409 | platform_device_register(&kirkwood_i2c); | ||
| 410 | } | ||
| 411 | |||
| 412 | |||
| 413 | /***************************************************************************** | ||
| 329 | * UART0 | 414 | * UART0 |
| 330 | ****************************************************************************/ | 415 | ****************************************************************************/ |
| 331 | static struct plat_serial8250_port kirkwood_uart0_data[] = { | 416 | static struct plat_serial8250_port kirkwood_uart0_data[] = { |
| @@ -502,7 +587,7 @@ static struct platform_device kirkwood_xor01_channel = { | |||
| 502 | }, | 587 | }, |
| 503 | }; | 588 | }; |
| 504 | 589 | ||
| 505 | void __init kirkwood_xor0_init(void) | 590 | static void __init kirkwood_xor0_init(void) |
| 506 | { | 591 | { |
| 507 | platform_device_register(&kirkwood_xor0_shared); | 592 | platform_device_register(&kirkwood_xor0_shared); |
| 508 | 593 | ||
| @@ -600,7 +685,7 @@ static struct platform_device kirkwood_xor11_channel = { | |||
| 600 | }, | 685 | }, |
| 601 | }; | 686 | }; |
| 602 | 687 | ||
| 603 | void __init kirkwood_xor1_init(void) | 688 | static void __init kirkwood_xor1_init(void) |
| 604 | { | 689 | { |
| 605 | platform_device_register(&kirkwood_xor1_shared); | 690 | platform_device_register(&kirkwood_xor1_shared); |
| 606 | 691 | ||
| @@ -708,4 +793,9 @@ void __init kirkwood_init(void) | |||
| 708 | #ifdef CONFIG_CACHE_FEROCEON_L2 | 793 | #ifdef CONFIG_CACHE_FEROCEON_L2 |
| 709 | kirkwood_l2_init(); | 794 | kirkwood_l2_init(); |
| 710 | #endif | 795 | #endif |
| 796 | |||
| 797 | /* internal devices that every board has */ | ||
| 798 | kirkwood_rtc_init(); | ||
| 799 | kirkwood_xor0_init(); | ||
| 800 | kirkwood_xor1_init(); | ||
| 711 | } | 801 | } |
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h index fe367c18e722..6ee88406f381 100644 --- a/arch/arm/mach-kirkwood/common.h +++ b/arch/arm/mach-kirkwood/common.h | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | struct dsa_platform_data; | 14 | struct dsa_platform_data; |
| 15 | struct mv643xx_eth_platform_data; | 15 | struct mv643xx_eth_platform_data; |
| 16 | struct mv_sata_platform_data; | 16 | struct mv_sata_platform_data; |
| 17 | struct mvsdio_platform_data; | ||
| 17 | 18 | ||
| 18 | /* | 19 | /* |
| 19 | * Basic Kirkwood init functions used early by machine-setup. | 20 | * Basic Kirkwood init functions used early by machine-setup. |
| @@ -33,14 +34,14 @@ void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data); | |||
| 33 | void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data); | 34 | void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data); |
| 34 | void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq); | 35 | void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq); |
| 35 | void kirkwood_pcie_init(void); | 36 | void kirkwood_pcie_init(void); |
| 36 | void kirkwood_rtc_init(void); | ||
| 37 | void kirkwood_sata_init(struct mv_sata_platform_data *sata_data); | 37 | void kirkwood_sata_init(struct mv_sata_platform_data *sata_data); |
| 38 | void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data); | ||
| 38 | void kirkwood_spi_init(void); | 39 | void kirkwood_spi_init(void); |
| 40 | void kirkwood_i2c_init(void); | ||
| 39 | void kirkwood_uart0_init(void); | 41 | void kirkwood_uart0_init(void); |
| 40 | void kirkwood_uart1_init(void); | 42 | void kirkwood_uart1_init(void); |
| 41 | void kirkwood_xor0_init(void); | ||
| 42 | void kirkwood_xor1_init(void); | ||
| 43 | 43 | ||
| 44 | extern int kirkwood_tclk; | ||
| 44 | extern struct sys_timer kirkwood_timer; | 45 | extern struct sys_timer kirkwood_timer; |
| 45 | 46 | ||
| 46 | 47 | ||
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c index a14c2948c62a..5505d5837752 100644 --- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c +++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c | |||
| @@ -11,18 +11,59 @@ | |||
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
| 13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/pci.h> | ||
| 15 | #include <linux/irq.h> | ||
| 16 | #include <linux/mtd/physmap.h> | ||
| 17 | #include <linux/mtd/nand.h> | 14 | #include <linux/mtd/nand.h> |
| 18 | #include <linux/timer.h> | 15 | #include <linux/mtd/partitions.h> |
| 19 | #include <linux/ata_platform.h> | 16 | #include <linux/ata_platform.h> |
| 20 | #include <linux/mv643xx_eth.h> | 17 | #include <linux/mv643xx_eth.h> |
| 21 | #include <asm/mach-types.h> | 18 | #include <asm/mach-types.h> |
| 22 | #include <asm/mach/arch.h> | 19 | #include <asm/mach/arch.h> |
| 23 | #include <asm/mach/pci.h> | ||
| 24 | #include <mach/kirkwood.h> | 20 | #include <mach/kirkwood.h> |
| 21 | #include <plat/orion_nand.h> | ||
| 22 | #include <plat/mvsdio.h> | ||
| 25 | #include "common.h" | 23 | #include "common.h" |
| 24 | #include "mpp.h" | ||
| 25 | |||
| 26 | static struct mtd_partition db88f6281_nand_parts[] = { | ||
| 27 | { | ||
| 28 | .name = "u-boot", | ||
| 29 | .offset = 0, | ||
| 30 | .size = SZ_1M | ||
| 31 | }, { | ||
| 32 | .name = "uImage", | ||
| 33 | .offset = MTDPART_OFS_NXTBLK, | ||
| 34 | .size = SZ_4M | ||
| 35 | }, { | ||
| 36 | .name = "root", | ||
| 37 | .offset = MTDPART_OFS_NXTBLK, | ||
| 38 | .size = MTDPART_SIZ_FULL | ||
| 39 | }, | ||
| 40 | }; | ||
| 41 | |||
| 42 | static struct resource db88f6281_nand_resource = { | ||
| 43 | .flags = IORESOURCE_MEM, | ||
| 44 | .start = KIRKWOOD_NAND_MEM_PHYS_BASE, | ||
| 45 | .end = KIRKWOOD_NAND_MEM_PHYS_BASE + | ||
| 46 | KIRKWOOD_NAND_MEM_SIZE - 1, | ||
| 47 | }; | ||
| 48 | |||
| 49 | static struct orion_nand_data db88f6281_nand_data = { | ||
| 50 | .parts = db88f6281_nand_parts, | ||
| 51 | .nr_parts = ARRAY_SIZE(db88f6281_nand_parts), | ||
| 52 | .cle = 0, | ||
| 53 | .ale = 1, | ||
| 54 | .width = 8, | ||
| 55 | .chip_delay = 25, | ||
| 56 | }; | ||
| 57 | |||
| 58 | static struct platform_device db88f6281_nand_flash = { | ||
| 59 | .name = "orion_nand", | ||
| 60 | .id = -1, | ||
| 61 | .dev = { | ||
| 62 | .platform_data = &db88f6281_nand_data, | ||
| 63 | }, | ||
| 64 | .resource = &db88f6281_nand_resource, | ||
| 65 | .num_resources = 1, | ||
| 66 | }; | ||
| 26 | 67 | ||
| 27 | static struct mv643xx_eth_platform_data db88f6281_ge00_data = { | 68 | static struct mv643xx_eth_platform_data db88f6281_ge00_data = { |
| 28 | .phy_addr = MV643XX_ETH_PHY_ADDR(8), | 69 | .phy_addr = MV643XX_ETH_PHY_ADDR(8), |
| @@ -32,18 +73,32 @@ static struct mv_sata_platform_data db88f6281_sata_data = { | |||
| 32 | .n_ports = 2, | 73 | .n_ports = 2, |
| 33 | }; | 74 | }; |
| 34 | 75 | ||
| 76 | static struct mvsdio_platform_data db88f6281_mvsdio_data = { | ||
| 77 | .gpio_write_protect = 37, | ||
| 78 | .gpio_card_detect = 38, | ||
| 79 | }; | ||
| 80 | |||
| 81 | static unsigned int db88f6281_mpp_config[] __initdata = { | ||
| 82 | MPP37_GPIO, | ||
| 83 | MPP38_GPIO, | ||
| 84 | 0 | ||
| 85 | }; | ||
| 86 | |||
| 35 | static void __init db88f6281_init(void) | 87 | static void __init db88f6281_init(void) |
| 36 | { | 88 | { |
| 37 | /* | 89 | /* |
| 38 | * Basic setup. Needs to be called early. | 90 | * Basic setup. Needs to be called early. |
| 39 | */ | 91 | */ |
| 40 | kirkwood_init(); | 92 | kirkwood_init(); |
| 93 | kirkwood_mpp_conf(db88f6281_mpp_config); | ||
| 41 | 94 | ||
| 42 | kirkwood_ehci_init(); | 95 | kirkwood_ehci_init(); |
| 43 | kirkwood_ge00_init(&db88f6281_ge00_data); | 96 | kirkwood_ge00_init(&db88f6281_ge00_data); |
| 44 | kirkwood_rtc_init(); | ||
| 45 | kirkwood_sata_init(&db88f6281_sata_data); | 97 | kirkwood_sata_init(&db88f6281_sata_data); |
| 46 | kirkwood_uart0_init(); | 98 | kirkwood_uart0_init(); |
| 99 | kirkwood_sdio_init(&db88f6281_mvsdio_data); | ||
| 100 | |||
| 101 | platform_device_register(&db88f6281_nand_flash); | ||
| 47 | } | 102 | } |
| 48 | 103 | ||
| 49 | static int __init db88f6281_pci_init(void) | 104 | static int __init db88f6281_pci_init(void) |
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h index ada480c0e197..38c986853590 100644 --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h | |||
| @@ -93,6 +93,7 @@ | |||
| 93 | #define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034) | 93 | #define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034) |
| 94 | #define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300) | 94 | #define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300) |
| 95 | #define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) | 95 | #define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600) |
| 96 | #define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) | ||
| 96 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) | 97 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) |
| 97 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) | 98 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) |
| 98 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) | 99 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) |
| @@ -116,5 +117,7 @@ | |||
| 116 | 117 | ||
| 117 | #define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) | 118 | #define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000) |
| 118 | 119 | ||
| 120 | #define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000) | ||
| 121 | |||
| 119 | 122 | ||
| 120 | #endif | 123 | #endif |
diff --git a/arch/arm/mach-kirkwood/include/mach/system.h b/arch/arm/mach-kirkwood/include/mach/system.h index 8510f6cfdabf..23a1914c1da8 100644 --- a/arch/arm/mach-kirkwood/include/mach/system.h +++ b/arch/arm/mach-kirkwood/include/mach/system.h | |||
| @@ -17,7 +17,7 @@ static inline void arch_idle(void) | |||
| 17 | cpu_do_idle(); | 17 | cpu_do_idle(); |
| 18 | } | 18 | } |
| 19 | 19 | ||
| 20 | static inline void arch_reset(char mode) | 20 | static inline void arch_reset(char mode, const char *cmd) |
| 21 | { | 21 | { |
| 22 | /* | 22 | /* |
| 23 | * Enable soft reset to assert RSTOUTn. | 23 | * Enable soft reset to assert RSTOUTn. |
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c new file mode 100644 index 000000000000..63c44934391a --- /dev/null +++ b/arch/arm/mach-kirkwood/mpp.c | |||
| @@ -0,0 +1,97 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-kirkwood/mpp.c | ||
| 3 | * | ||
| 4 | * MPP functions for Marvell Kirkwood SoCs | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/mbus.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | #include <asm/gpio.h> | ||
| 16 | #include <mach/hardware.h> | ||
| 17 | #include "common.h" | ||
| 18 | #include "mpp.h" | ||
| 19 | |||
| 20 | static unsigned int __init kirkwood_variant(void) | ||
| 21 | { | ||
| 22 | u32 dev, rev; | ||
| 23 | |||
| 24 | kirkwood_pcie_id(&dev, &rev); | ||
| 25 | |||
| 26 | if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) | ||
| 27 | return MPP_F6281_MASK; | ||
| 28 | if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0) | ||
| 29 | return MPP_F6192_MASK; | ||
| 30 | if (dev == MV88F6180_DEV_ID) | ||
| 31 | return MPP_F6180_MASK; | ||
| 32 | |||
| 33 | printk(KERN_ERR "MPP setup: unknown kirkwood variant " | ||
| 34 | "(dev %#x rev %#x)\n", dev, rev); | ||
| 35 | return 0; | ||
| 36 | } | ||
| 37 | |||
| 38 | #define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4) | ||
| 39 | #define MPP_NR_REGS (1 + MPP_MAX/8) | ||
| 40 | |||
| 41 | void __init kirkwood_mpp_conf(unsigned int *mpp_list) | ||
| 42 | { | ||
| 43 | u32 mpp_ctrl[MPP_NR_REGS]; | ||
| 44 | unsigned int variant_mask; | ||
| 45 | int i; | ||
| 46 | |||
| 47 | variant_mask = kirkwood_variant(); | ||
| 48 | if (!variant_mask) | ||
| 49 | return; | ||
| 50 | |||
| 51 | printk(KERN_DEBUG "initial MPP regs:"); | ||
| 52 | for (i = 0; i < MPP_NR_REGS; i++) { | ||
| 53 | mpp_ctrl[i] = readl(MPP_CTRL(i)); | ||
| 54 | printk(" %08x", mpp_ctrl[i]); | ||
| 55 | } | ||
| 56 | printk("\n"); | ||
| 57 | |||
| 58 | while (*mpp_list) { | ||
| 59 | unsigned int num = MPP_NUM(*mpp_list); | ||
| 60 | unsigned int sel = MPP_SEL(*mpp_list); | ||
| 61 | int shift, gpio_mode; | ||
| 62 | |||
| 63 | if (num > MPP_MAX) { | ||
| 64 | printk(KERN_ERR "kirkwood_mpp_conf: invalid MPP " | ||
| 65 | "number (%u)\n", num); | ||
| 66 | continue; | ||
| 67 | } | ||
| 68 | if (!(*mpp_list & variant_mask)) { | ||
| 69 | printk(KERN_WARNING | ||
| 70 | "kirkwood_mpp_conf: requested MPP%u config " | ||
| 71 | "unavailable on this hardware\n", num); | ||
| 72 | continue; | ||
| 73 | } | ||
| 74 | |||
| 75 | shift = (num & 7) << 2; | ||
| 76 | mpp_ctrl[num / 8] &= ~(0xf << shift); | ||
| 77 | mpp_ctrl[num / 8] |= sel << shift; | ||
| 78 | |||
| 79 | gpio_mode = 0; | ||
| 80 | if (*mpp_list & MPP_INPUT_MASK) | ||
| 81 | gpio_mode |= GPIO_INPUT_OK; | ||
| 82 | if (*mpp_list & MPP_OUTPUT_MASK) | ||
| 83 | gpio_mode |= GPIO_OUTPUT_OK; | ||
| 84 | if (sel != 0) | ||
| 85 | gpio_mode = 0; | ||
| 86 | orion_gpio_set_valid(num, gpio_mode); | ||
| 87 | |||
| 88 | mpp_list++; | ||
| 89 | } | ||
| 90 | |||
| 91 | printk(KERN_DEBUG " final MPP regs:"); | ||
| 92 | for (i = 0; i < MPP_NR_REGS; i++) { | ||
| 93 | writel(mpp_ctrl[i], MPP_CTRL(i)); | ||
| 94 | printk(" %08x", mpp_ctrl[i]); | ||
| 95 | } | ||
| 96 | printk("\n"); | ||
| 97 | } | ||
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h new file mode 100644 index 000000000000..e021a80c2caf --- /dev/null +++ b/arch/arm/mach-kirkwood/mpp.h | |||
| @@ -0,0 +1,303 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins | ||
| 3 | * | ||
| 4 | * Copyright 2009: Marvell Technology Group Ltd. | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __KIRKWOOD_MPP_H | ||
| 12 | #define __KIRKWOOD_MPP_H | ||
| 13 | |||
| 14 | #define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ | ||
| 15 | /* MPP number */ ((_num) & 0xff) | \ | ||
| 16 | /* MPP select value */ (((_sel) & 0xf) << 8) | \ | ||
| 17 | /* may be input signal */ ((!!(_in)) << 12) | \ | ||
| 18 | /* may be output signal */ ((!!(_out)) << 13) | \ | ||
| 19 | /* available on F6180 */ ((!!(_F6180)) << 14) | \ | ||
| 20 | /* available on F6190 */ ((!!(_F6190)) << 15) | \ | ||
| 21 | /* available on F6192 */ ((!!(_F6192)) << 16) | \ | ||
| 22 | /* available on F6281 */ ((!!(_F6281)) << 17)) | ||
| 23 | |||
| 24 | #define MPP_NUM(x) ((x) & 0xff) | ||
| 25 | #define MPP_SEL(x) (((x) >> 8) & 0xf) | ||
| 26 | |||
| 27 | /* num sel i o 6180 6190 6192 6281 */ | ||
| 28 | |||
| 29 | #define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 ) | ||
| 30 | #define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 ) | ||
| 31 | |||
| 32 | #define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 ) | ||
| 33 | #define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 ) | ||
| 34 | #define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 ) | ||
| 35 | #define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 ) | ||
| 36 | |||
| 37 | #define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 38 | #define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 39 | #define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 40 | |||
| 41 | #define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 42 | #define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 43 | #define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 44 | |||
| 45 | #define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 46 | #define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 47 | #define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 48 | |||
| 49 | #define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 50 | #define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 51 | #define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 ) | ||
| 52 | |||
| 53 | #define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 54 | #define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 55 | #define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 ) | ||
| 56 | #define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 ) | ||
| 57 | #define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 ) | ||
| 58 | |||
| 59 | #define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 60 | #define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 61 | #define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 62 | #define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 ) | ||
| 63 | #define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 ) | ||
| 64 | |||
| 65 | #define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 ) | ||
| 66 | #define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 67 | #define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 ) | ||
| 68 | |||
| 69 | #define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 70 | #define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 ) | ||
| 71 | #define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 72 | #define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) | ||
| 73 | |||
| 74 | #define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 75 | #define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 76 | #define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 77 | #define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) | ||
| 78 | #define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 ) | ||
| 79 | #define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 ) | ||
| 80 | #define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 ) | ||
| 81 | #define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 ) | ||
| 82 | |||
| 83 | #define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 84 | #define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 85 | #define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 ) | ||
| 86 | #define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 ) | ||
| 87 | #define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 ) | ||
| 88 | #define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 ) | ||
| 89 | #define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 ) | ||
| 90 | |||
| 91 | #define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 92 | #define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 93 | #define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) | ||
| 94 | #define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) | ||
| 95 | #define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) | ||
| 96 | |||
| 97 | #define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 98 | #define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 ) | ||
| 99 | #define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 ) | ||
| 100 | #define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 ) | ||
| 101 | #define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 ) | ||
| 102 | #define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 ) | ||
| 103 | #define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 ) | ||
| 104 | |||
| 105 | #define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 106 | #define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 ) | ||
| 107 | |||
| 108 | #define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 109 | #define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 110 | #define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 ) | ||
| 111 | |||
| 112 | #define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 113 | #define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 114 | #define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 ) | ||
| 115 | #define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 ) | ||
| 116 | #define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 ) | ||
| 117 | |||
| 118 | #define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 119 | #define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 120 | #define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 ) | ||
| 121 | #define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 ) | ||
| 122 | #define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 ) | ||
| 123 | |||
| 124 | #define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 125 | #define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 126 | #define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 ) | ||
| 127 | #define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 ) | ||
| 128 | #define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 ) | ||
| 129 | #define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 ) | ||
| 130 | |||
| 131 | #define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 132 | #define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 133 | #define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 ) | ||
| 134 | |||
| 135 | #define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 136 | #define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 137 | |||
| 138 | #define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 ) | ||
| 139 | #define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 ) | ||
| 140 | |||
| 141 | #define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 142 | #define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 143 | #define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 144 | #define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 145 | #define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 ) | ||
| 146 | #define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 ) | ||
| 147 | |||
| 148 | #define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 149 | #define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 150 | #define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 151 | #define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 152 | #define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 ) | ||
| 153 | #define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 ) | ||
| 154 | |||
| 155 | #define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 156 | #define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 157 | #define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 158 | #define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 159 | #define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 ) | ||
| 160 | #define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 ) | ||
| 161 | |||
| 162 | #define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 163 | #define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 164 | #define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 ) | ||
| 165 | #define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 166 | #define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 ) | ||
| 167 | #define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 ) | ||
| 168 | |||
| 169 | #define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 170 | #define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 171 | #define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 172 | #define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 173 | #define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 ) | ||
| 174 | |||
| 175 | #define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 176 | #define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 177 | #define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 178 | #define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 179 | #define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 ) | ||
| 180 | |||
| 181 | #define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 182 | #define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 183 | #define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 ) | ||
| 184 | #define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 185 | #define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 ) | ||
| 186 | |||
| 187 | #define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 188 | #define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 189 | #define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 190 | #define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 191 | #define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 ) | ||
| 192 | |||
| 193 | #define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 194 | #define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 195 | #define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 ) | ||
| 196 | #define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 197 | #define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 ) | ||
| 198 | |||
| 199 | #define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 200 | #define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 201 | #define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 ) | ||
| 202 | #define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 203 | |||
| 204 | #define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 205 | #define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 206 | #define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 ) | ||
| 207 | #define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 208 | |||
| 209 | #define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 210 | #define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 211 | #define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 ) | ||
| 212 | #define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 213 | |||
| 214 | #define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 215 | #define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 ) | ||
| 216 | #define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 ) | ||
| 217 | #define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 218 | |||
| 219 | #define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 220 | #define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 221 | #define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 222 | |||
| 223 | #define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) | ||
| 224 | #define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 225 | #define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 226 | |||
| 227 | #define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) | ||
| 228 | #define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) | ||
| 229 | #define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 ) | ||
| 230 | #define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 ) | ||
| 231 | #define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 ) | ||
| 232 | |||
| 233 | #define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 234 | #define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 235 | #define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 ) | ||
| 236 | #define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 ) | ||
| 237 | |||
| 238 | #define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 239 | #define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 240 | #define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 ) | ||
| 241 | #define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 ) | ||
| 242 | |||
| 243 | #define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 244 | #define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 245 | #define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 ) | ||
| 246 | #define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 ) | ||
| 247 | |||
| 248 | #define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 249 | #define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 250 | #define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 ) | ||
| 251 | #define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 ) | ||
| 252 | |||
| 253 | #define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 254 | #define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 255 | #define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 ) | ||
| 256 | #define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 ) | ||
| 257 | |||
| 258 | #define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 259 | #define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 260 | #define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 ) | ||
| 261 | #define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 ) | ||
| 262 | |||
| 263 | #define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 264 | #define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 265 | #define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 ) | ||
| 266 | #define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 ) | ||
| 267 | |||
| 268 | #define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 269 | #define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 270 | #define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 ) | ||
| 271 | #define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 ) | ||
| 272 | |||
| 273 | #define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 ) | ||
| 274 | #define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 275 | #define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 ) | ||
| 276 | #define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 ) | ||
| 277 | |||
| 278 | #define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 ) | ||
| 279 | #define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 280 | #define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 ) | ||
| 281 | |||
| 282 | #define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 ) | ||
| 283 | #define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 284 | #define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 ) | ||
| 285 | |||
| 286 | #define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 ) | ||
| 287 | #define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 288 | #define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 ) | ||
| 289 | |||
| 290 | #define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) | ||
| 291 | #define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 292 | #define MPP48_TDM_DTX MPP( 48. 0x2, 0, 1, 0, 0, 0, 1 ) | ||
| 293 | |||
| 294 | #define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) | ||
| 295 | #define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) | ||
| 296 | #define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 ) | ||
| 297 | #define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 ) | ||
| 298 | |||
| 299 | #define MPP_MAX 49 | ||
| 300 | |||
| 301 | void kirkwood_mpp_conf(unsigned int *mpp_list); | ||
| 302 | |||
| 303 | #endif | ||
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c index b1d1a87a6821..2f0e4ef3db0f 100644 --- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c +++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c | |||
| @@ -11,11 +11,8 @@ | |||
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
| 13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/pci.h> | ||
| 15 | #include <linux/irq.h> | ||
| 16 | #include <linux/mtd/physmap.h> | ||
| 17 | #include <linux/mtd/nand.h> | 14 | #include <linux/mtd/nand.h> |
| 18 | #include <linux/timer.h> | 15 | #include <linux/mtd/partitions.h> |
| 19 | #include <linux/ata_platform.h> | 16 | #include <linux/ata_platform.h> |
| 20 | #include <linux/mv643xx_eth.h> | 17 | #include <linux/mv643xx_eth.h> |
| 21 | #include <linux/spi/flash.h> | 18 | #include <linux/spi/flash.h> |
| @@ -23,7 +20,6 @@ | |||
| 23 | #include <linux/spi/orion_spi.h> | 20 | #include <linux/spi/orion_spi.h> |
| 24 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
| 25 | #include <asm/mach/arch.h> | 22 | #include <asm/mach/arch.h> |
| 26 | #include <asm/mach/pci.h> | ||
| 27 | #include <mach/kirkwood.h> | 23 | #include <mach/kirkwood.h> |
| 28 | #include "common.h" | 24 | #include "common.h" |
| 29 | 25 | ||
| @@ -61,14 +57,11 @@ static void __init rd88f6192_init(void) | |||
| 61 | 57 | ||
| 62 | kirkwood_ehci_init(); | 58 | kirkwood_ehci_init(); |
| 63 | kirkwood_ge00_init(&rd88f6192_ge00_data); | 59 | kirkwood_ge00_init(&rd88f6192_ge00_data); |
| 64 | kirkwood_rtc_init(); | ||
| 65 | kirkwood_sata_init(&rd88f6192_sata_data); | 60 | kirkwood_sata_init(&rd88f6192_sata_data); |
| 66 | spi_register_board_info(rd88F6192_spi_slave_info, | 61 | spi_register_board_info(rd88F6192_spi_slave_info, |
| 67 | ARRAY_SIZE(rd88F6192_spi_slave_info)); | 62 | ARRAY_SIZE(rd88F6192_spi_slave_info)); |
| 68 | kirkwood_spi_init(); | 63 | kirkwood_spi_init(); |
| 69 | kirkwood_uart0_init(); | 64 | kirkwood_uart0_init(); |
| 70 | kirkwood_xor0_init(); | ||
| 71 | kirkwood_xor1_init(); | ||
| 72 | } | 65 | } |
| 73 | 66 | ||
| 74 | static int __init rd88f6192_pci_init(void) | 67 | static int __init rd88f6192_pci_init(void) |
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c index 9a0e905d10cd..c3deea5e3cad 100644 --- a/arch/arm/mach-kirkwood/rd88f6281-setup.c +++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c | |||
| @@ -11,21 +11,20 @@ | |||
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
| 13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/pci.h> | ||
| 15 | #include <linux/irq.h> | 14 | #include <linux/irq.h> |
| 16 | #include <linux/mtd/physmap.h> | ||
| 17 | #include <linux/mtd/nand.h> | 15 | #include <linux/mtd/nand.h> |
| 18 | #include <linux/timer.h> | 16 | #include <linux/mtd/partitions.h> |
| 19 | #include <linux/ata_platform.h> | 17 | #include <linux/ata_platform.h> |
| 20 | #include <linux/mv643xx_eth.h> | 18 | #include <linux/mv643xx_eth.h> |
| 21 | #include <linux/ethtool.h> | 19 | #include <linux/ethtool.h> |
| 22 | #include <net/dsa.h> | 20 | #include <net/dsa.h> |
| 23 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
| 24 | #include <asm/mach/arch.h> | 22 | #include <asm/mach/arch.h> |
| 25 | #include <asm/mach/pci.h> | ||
| 26 | #include <mach/kirkwood.h> | 23 | #include <mach/kirkwood.h> |
| 24 | #include <plat/mvsdio.h> | ||
| 27 | #include <plat/orion_nand.h> | 25 | #include <plat/orion_nand.h> |
| 28 | #include "common.h" | 26 | #include "common.h" |
| 27 | #include "mpp.h" | ||
| 29 | 28 | ||
| 30 | static struct mtd_partition rd88f6281_nand_parts[] = { | 29 | static struct mtd_partition rd88f6281_nand_parts[] = { |
| 31 | { | 30 | { |
| @@ -91,6 +90,15 @@ static struct mv_sata_platform_data rd88f6281_sata_data = { | |||
| 91 | .n_ports = 2, | 90 | .n_ports = 2, |
| 92 | }; | 91 | }; |
| 93 | 92 | ||
| 93 | static struct mvsdio_platform_data rd88f6281_mvsdio_data = { | ||
| 94 | .gpio_card_detect = 28, | ||
| 95 | }; | ||
| 96 | |||
| 97 | static unsigned int rd88f6281_mpp_config[] __initdata = { | ||
| 98 | MPP28_GPIO, | ||
| 99 | 0 | ||
| 100 | }; | ||
| 101 | |||
| 94 | static void __init rd88f6281_init(void) | 102 | static void __init rd88f6281_init(void) |
| 95 | { | 103 | { |
| 96 | u32 dev, rev; | 104 | u32 dev, rev; |
| @@ -99,6 +107,7 @@ static void __init rd88f6281_init(void) | |||
| 99 | * Basic setup. Needs to be called early. | 107 | * Basic setup. Needs to be called early. |
| 100 | */ | 108 | */ |
| 101 | kirkwood_init(); | 109 | kirkwood_init(); |
| 110 | kirkwood_mpp_conf(rd88f6281_mpp_config); | ||
| 102 | 111 | ||
| 103 | kirkwood_ehci_init(); | 112 | kirkwood_ehci_init(); |
| 104 | 113 | ||
| @@ -112,8 +121,8 @@ static void __init rd88f6281_init(void) | |||
| 112 | } | 121 | } |
| 113 | kirkwood_ge00_switch_init(&rd88f6281_switch_data, NO_IRQ); | 122 | kirkwood_ge00_switch_init(&rd88f6281_switch_data, NO_IRQ); |
| 114 | 123 | ||
| 115 | kirkwood_rtc_init(); | ||
| 116 | kirkwood_sata_init(&rd88f6281_sata_data); | 124 | kirkwood_sata_init(&rd88f6281_sata_data); |
| 125 | kirkwood_sdio_init(&rd88f6281_mvsdio_data); | ||
| 117 | kirkwood_uart0_init(); | 126 | kirkwood_uart0_init(); |
| 118 | 127 | ||
| 119 | platform_device_register(&rd88f6281_nand_flash); | 128 | platform_device_register(&rd88f6281_nand_flash); |
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c new file mode 100644 index 000000000000..831e4a56cae1 --- /dev/null +++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c | |||
| @@ -0,0 +1,136 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-kirkwood/sheevaplug-setup.c | ||
| 3 | * | ||
| 4 | * Marvell SheevaPlug Reference Board Setup | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/mtd/nand.h> | ||
| 15 | #include <linux/mtd/partitions.h> | ||
| 16 | #include <linux/mv643xx_eth.h> | ||
| 17 | #include <linux/gpio.h> | ||
| 18 | #include <linux/leds.h> | ||
| 19 | #include <asm/mach-types.h> | ||
| 20 | #include <asm/mach/arch.h> | ||
| 21 | #include <mach/kirkwood.h> | ||
| 22 | #include <plat/mvsdio.h> | ||
| 23 | #include <plat/orion_nand.h> | ||
| 24 | #include "common.h" | ||
| 25 | #include "mpp.h" | ||
| 26 | |||
| 27 | static struct mtd_partition sheevaplug_nand_parts[] = { | ||
| 28 | { | ||
| 29 | .name = "u-boot", | ||
| 30 | .offset = 0, | ||
| 31 | .size = SZ_1M | ||
| 32 | }, { | ||
| 33 | .name = "uImage", | ||
| 34 | .offset = MTDPART_OFS_NXTBLK, | ||
| 35 | .size = SZ_4M | ||
| 36 | }, { | ||
| 37 | .name = "root", | ||
| 38 | .offset = MTDPART_OFS_NXTBLK, | ||
| 39 | .size = MTDPART_SIZ_FULL | ||
| 40 | }, | ||
| 41 | }; | ||
| 42 | |||
| 43 | static struct resource sheevaplug_nand_resource = { | ||
| 44 | .flags = IORESOURCE_MEM, | ||
| 45 | .start = KIRKWOOD_NAND_MEM_PHYS_BASE, | ||
| 46 | .end = KIRKWOOD_NAND_MEM_PHYS_BASE + | ||
| 47 | KIRKWOOD_NAND_MEM_SIZE - 1, | ||
| 48 | }; | ||
| 49 | |||
| 50 | static struct orion_nand_data sheevaplug_nand_data = { | ||
| 51 | .parts = sheevaplug_nand_parts, | ||
| 52 | .nr_parts = ARRAY_SIZE(sheevaplug_nand_parts), | ||
| 53 | .cle = 0, | ||
| 54 | .ale = 1, | ||
| 55 | .width = 8, | ||
| 56 | .chip_delay = 25, | ||
| 57 | }; | ||
| 58 | |||
| 59 | static struct platform_device sheevaplug_nand_flash = { | ||
| 60 | .name = "orion_nand", | ||
| 61 | .id = -1, | ||
| 62 | .dev = { | ||
| 63 | .platform_data = &sheevaplug_nand_data, | ||
| 64 | }, | ||
| 65 | .resource = &sheevaplug_nand_resource, | ||
| 66 | .num_resources = 1, | ||
| 67 | }; | ||
| 68 | |||
| 69 | static struct mv643xx_eth_platform_data sheevaplug_ge00_data = { | ||
| 70 | .phy_addr = MV643XX_ETH_PHY_ADDR(0), | ||
| 71 | }; | ||
| 72 | |||
| 73 | static struct mvsdio_platform_data sheevaplug_mvsdio_data = { | ||
| 74 | // unfortunately the CD signal has not been connected */ | ||
| 75 | }; | ||
| 76 | |||
| 77 | static struct gpio_led sheevaplug_led_pins[] = { | ||
| 78 | { | ||
| 79 | .name = "plug:green:health", | ||
| 80 | .default_trigger = "default-on", | ||
| 81 | .gpio = 49, | ||
| 82 | .active_low = 1, | ||
| 83 | }, | ||
| 84 | }; | ||
| 85 | |||
| 86 | static struct gpio_led_platform_data sheevaplug_led_data = { | ||
| 87 | .leds = sheevaplug_led_pins, | ||
| 88 | .num_leds = ARRAY_SIZE(sheevaplug_led_pins), | ||
| 89 | }; | ||
| 90 | |||
| 91 | static struct platform_device sheevaplug_leds = { | ||
| 92 | .name = "leds-gpio", | ||
| 93 | .id = -1, | ||
| 94 | .dev = { | ||
| 95 | .platform_data = &sheevaplug_led_data, | ||
| 96 | } | ||
| 97 | }; | ||
| 98 | |||
| 99 | static unsigned int sheevaplug_mpp_config[] __initdata = { | ||
| 100 | MPP29_GPIO, /* USB Power Enable */ | ||
| 101 | MPP49_GPIO, /* LED */ | ||
| 102 | 0 | ||
| 103 | }; | ||
| 104 | |||
| 105 | static void __init sheevaplug_init(void) | ||
| 106 | { | ||
| 107 | /* | ||
| 108 | * Basic setup. Needs to be called early. | ||
| 109 | */ | ||
| 110 | kirkwood_init(); | ||
| 111 | kirkwood_mpp_conf(sheevaplug_mpp_config); | ||
| 112 | |||
| 113 | kirkwood_uart0_init(); | ||
| 114 | |||
| 115 | if (gpio_request(29, "USB Power Enable") != 0 || | ||
| 116 | gpio_direction_output(29, 1) != 0) | ||
| 117 | printk(KERN_ERR "can't set up GPIO 29 (USB Power Enable)\n"); | ||
| 118 | kirkwood_ehci_init(); | ||
| 119 | |||
| 120 | kirkwood_ge00_init(&sheevaplug_ge00_data); | ||
| 121 | kirkwood_sdio_init(&sheevaplug_mvsdio_data); | ||
| 122 | |||
| 123 | platform_device_register(&sheevaplug_nand_flash); | ||
| 124 | platform_device_register(&sheevaplug_leds); | ||
| 125 | } | ||
| 126 | |||
| 127 | MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board") | ||
| 128 | /* Maintainer: shadi Ammouri <shadi@marvell.com> */ | ||
| 129 | .phys_io = KIRKWOOD_REGS_PHYS_BASE, | ||
| 130 | .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, | ||
| 131 | .boot_params = 0x00000100, | ||
| 132 | .init_machine = sheevaplug_init, | ||
| 133 | .map_io = kirkwood_map_io, | ||
| 134 | .init_irq = kirkwood_init_irq, | ||
| 135 | .timer = &kirkwood_timer, | ||
| 136 | MACHINE_END | ||
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c new file mode 100644 index 000000000000..dda5743cf3e0 --- /dev/null +++ b/arch/arm/mach-kirkwood/ts219-setup.c | |||
| @@ -0,0 +1,220 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * QNAP TS-119/TS-219 Turbo NAS Board Setup | ||
| 4 | * | ||
| 5 | * Copyright (C) 2009 Martin Michlmayr <tbm@cyrius.com> | ||
| 6 | * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or | ||
| 9 | * modify it under the terms of the GNU General Public License | ||
| 10 | * as published by the Free Software Foundation; either version | ||
| 11 | * 2 of the License, or (at your option) any later version. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/mtd/physmap.h> | ||
| 18 | #include <linux/spi/flash.h> | ||
| 19 | #include <linux/spi/spi.h> | ||
| 20 | #include <linux/spi/orion_spi.h> | ||
| 21 | #include <linux/i2c.h> | ||
| 22 | #include <linux/mv643xx_eth.h> | ||
| 23 | #include <linux/ata_platform.h> | ||
| 24 | #include <linux/gpio_keys.h> | ||
| 25 | #include <linux/input.h> | ||
| 26 | #include <linux/timex.h> | ||
| 27 | #include <linux/serial_reg.h> | ||
| 28 | #include <linux/pci.h> | ||
| 29 | #include <asm/mach-types.h> | ||
| 30 | #include <asm/mach/arch.h> | ||
| 31 | #include <mach/kirkwood.h> | ||
| 32 | #include "common.h" | ||
| 33 | #include "mpp.h" | ||
| 34 | |||
| 35 | /**************************************************************************** | ||
| 36 | * 16 MiB NOR flash. The struct mtd_partition is not in the same order as the | ||
| 37 | * partitions on the device because we want to keep compatability with | ||
| 38 | * the QNAP firmware. | ||
| 39 | * Layout as used by QNAP: | ||
| 40 | * 0x00000000-0x00080000 : "U-Boot" | ||
| 41 | * 0x00200000-0x00400000 : "Kernel" | ||
| 42 | * 0x00400000-0x00d00000 : "RootFS" | ||
| 43 | * 0x00d00000-0x01000000 : "RootFS2" | ||
| 44 | * 0x00080000-0x000c0000 : "U-Boot Config" | ||
| 45 | * 0x000c0000-0x00200000 : "NAS Config" | ||
| 46 | * | ||
| 47 | * We'll use "RootFS1" instead of "RootFS" to stay compatible with the layout | ||
| 48 | * used by the QNAP TS-109/TS-209. | ||
| 49 | * | ||
| 50 | ***************************************************************************/ | ||
| 51 | |||
| 52 | static struct mtd_partition qnap_ts219_partitions[] = { | ||
| 53 | { | ||
| 54 | .name = "U-Boot", | ||
| 55 | .size = 0x00080000, | ||
| 56 | .offset = 0, | ||
| 57 | .mask_flags = MTD_WRITEABLE, | ||
| 58 | }, { | ||
| 59 | .name = "Kernel", | ||
| 60 | .size = 0x00200000, | ||
| 61 | .offset = 0x00200000, | ||
| 62 | }, { | ||
| 63 | .name = "RootFS1", | ||
| 64 | .size = 0x00900000, | ||
| 65 | .offset = 0x00400000, | ||
| 66 | }, { | ||
| 67 | .name = "RootFS2", | ||
| 68 | .size = 0x00300000, | ||
| 69 | .offset = 0x00d00000, | ||
| 70 | }, { | ||
| 71 | .name = "U-Boot Config", | ||
| 72 | .size = 0x00040000, | ||
| 73 | .offset = 0x00080000, | ||
| 74 | }, { | ||
| 75 | .name = "NAS Config", | ||
| 76 | .size = 0x00140000, | ||
| 77 | .offset = 0x000c0000, | ||
| 78 | }, | ||
| 79 | }; | ||
| 80 | |||
| 81 | static const struct flash_platform_data qnap_ts219_flash = { | ||
| 82 | .type = "m25p128", | ||
| 83 | .name = "spi_flash", | ||
| 84 | .parts = qnap_ts219_partitions, | ||
| 85 | .nr_parts = ARRAY_SIZE(qnap_ts219_partitions), | ||
| 86 | }; | ||
| 87 | |||
| 88 | static struct spi_board_info __initdata qnap_ts219_spi_slave_info[] = { | ||
| 89 | { | ||
| 90 | .modalias = "m25p80", | ||
| 91 | .platform_data = &qnap_ts219_flash, | ||
| 92 | .irq = -1, | ||
| 93 | .max_speed_hz = 20000000, | ||
| 94 | .bus_num = 0, | ||
| 95 | .chip_select = 0, | ||
| 96 | }, | ||
| 97 | }; | ||
| 98 | |||
| 99 | static struct i2c_board_info __initdata qnap_ts219_i2c_rtc = { | ||
| 100 | I2C_BOARD_INFO("s35390a", 0x30), | ||
| 101 | }; | ||
| 102 | |||
| 103 | static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = { | ||
| 104 | .phy_addr = MV643XX_ETH_PHY_ADDR(8), | ||
| 105 | }; | ||
| 106 | |||
| 107 | static struct mv_sata_platform_data qnap_ts219_sata_data = { | ||
| 108 | .n_ports = 2, | ||
| 109 | }; | ||
| 110 | |||
| 111 | static struct gpio_keys_button qnap_ts219_buttons[] = { | ||
| 112 | { | ||
| 113 | .code = KEY_COPY, | ||
| 114 | .gpio = 15, | ||
| 115 | .desc = "USB Copy", | ||
| 116 | .active_low = 1, | ||
| 117 | }, | ||
| 118 | { | ||
| 119 | .code = KEY_RESTART, | ||
| 120 | .gpio = 16, | ||
| 121 | .desc = "Reset", | ||
| 122 | .active_low = 1, | ||
| 123 | }, | ||
| 124 | }; | ||
| 125 | |||
| 126 | static struct gpio_keys_platform_data qnap_ts219_button_data = { | ||
| 127 | .buttons = qnap_ts219_buttons, | ||
| 128 | .nbuttons = ARRAY_SIZE(qnap_ts219_buttons), | ||
| 129 | }; | ||
| 130 | |||
| 131 | static struct platform_device qnap_ts219_button_device = { | ||
| 132 | .name = "gpio-keys", | ||
| 133 | .id = -1, | ||
| 134 | .num_resources = 0, | ||
| 135 | .dev = { | ||
| 136 | .platform_data = &qnap_ts219_button_data, | ||
| 137 | } | ||
| 138 | }; | ||
| 139 | |||
| 140 | static unsigned int qnap_ts219_mpp_config[] __initdata = { | ||
| 141 | MPP0_SPI_SCn, | ||
| 142 | MPP1_SPI_MOSI, | ||
| 143 | MPP2_SPI_SCK, | ||
| 144 | MPP3_SPI_MISO, | ||
| 145 | MPP8_TW_SDA, | ||
| 146 | MPP9_TW_SCK, | ||
| 147 | MPP10_UART0_TXD, | ||
| 148 | MPP11_UART0_RXD, | ||
| 149 | MPP13_UART1_TXD, /* PIC controller */ | ||
| 150 | MPP14_UART1_RXD, /* PIC controller */ | ||
| 151 | MPP15_GPIO, /* USB Copy button */ | ||
| 152 | MPP16_GPIO, /* Reset button */ | ||
| 153 | MPP20_SATA1_ACTn, | ||
| 154 | MPP21_SATA0_ACTn, | ||
| 155 | MPP22_SATA1_PRESENTn, | ||
| 156 | MPP23_SATA0_PRESENTn, | ||
| 157 | 0 | ||
| 158 | }; | ||
| 159 | |||
| 160 | |||
| 161 | /***************************************************************************** | ||
| 162 | * QNAP TS-x19 specific power off method via UART1-attached PIC | ||
| 163 | ****************************************************************************/ | ||
| 164 | |||
| 165 | #define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2)) | ||
| 166 | |||
| 167 | void qnap_ts219_power_off(void) | ||
| 168 | { | ||
| 169 | /* 19200 baud divisor */ | ||
| 170 | const unsigned divisor = ((kirkwood_tclk + (8 * 19200)) / (16 * 19200)); | ||
| 171 | |||
| 172 | pr_info("%s: triggering power-off...\n", __func__); | ||
| 173 | |||
| 174 | /* hijack UART1 and reset into sane state (19200,8n1) */ | ||
| 175 | writel(0x83, UART1_REG(LCR)); | ||
| 176 | writel(divisor & 0xff, UART1_REG(DLL)); | ||
| 177 | writel((divisor >> 8) & 0xff, UART1_REG(DLM)); | ||
| 178 | writel(0x03, UART1_REG(LCR)); | ||
| 179 | writel(0x00, UART1_REG(IER)); | ||
| 180 | writel(0x00, UART1_REG(FCR)); | ||
| 181 | writel(0x00, UART1_REG(MCR)); | ||
| 182 | |||
| 183 | /* send the power-off command 'A' to PIC */ | ||
| 184 | writel('A', UART1_REG(TX)); | ||
| 185 | } | ||
| 186 | |||
| 187 | static void __init qnap_ts219_init(void) | ||
| 188 | { | ||
| 189 | /* | ||
| 190 | * Basic setup. Needs to be called early. | ||
| 191 | */ | ||
| 192 | kirkwood_init(); | ||
| 193 | kirkwood_mpp_conf(qnap_ts219_mpp_config); | ||
| 194 | |||
| 195 | kirkwood_uart0_init(); | ||
| 196 | kirkwood_uart1_init(); /* A PIC controller is connected here. */ | ||
| 197 | spi_register_board_info(qnap_ts219_spi_slave_info, | ||
| 198 | ARRAY_SIZE(qnap_ts219_spi_slave_info)); | ||
| 199 | kirkwood_spi_init(); | ||
| 200 | kirkwood_i2c_init(); | ||
| 201 | i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1); | ||
| 202 | kirkwood_ge00_init(&qnap_ts219_ge00_data); | ||
| 203 | kirkwood_sata_init(&qnap_ts219_sata_data); | ||
| 204 | kirkwood_ehci_init(); | ||
| 205 | platform_device_register(&qnap_ts219_button_device); | ||
| 206 | |||
| 207 | pm_power_off = qnap_ts219_power_off; | ||
| 208 | |||
| 209 | } | ||
| 210 | |||
| 211 | MACHINE_START(TS219, "QNAP TS-119/TS-219") | ||
| 212 | /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */ | ||
| 213 | .phys_io = KIRKWOOD_REGS_PHYS_BASE, | ||
| 214 | .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc, | ||
| 215 | .boot_params = 0x00000100, | ||
| 216 | .init_machine = qnap_ts219_init, | ||
| 217 | .map_io = kirkwood_map_io, | ||
| 218 | .init_irq = kirkwood_init_irq, | ||
| 219 | .timer = &kirkwood_timer, | ||
| 220 | MACHINE_END | ||
diff --git a/arch/arm/mach-ks8695/Kconfig b/arch/arm/mach-ks8695/Kconfig index 2754daabda55..fe0c82e30b2d 100644 --- a/arch/arm/mach-ks8695/Kconfig +++ b/arch/arm/mach-ks8695/Kconfig | |||
| @@ -14,6 +14,12 @@ config MACH_DSM320 | |||
| 14 | Say 'Y' here if you want your kernel to run on the D-Link | 14 | Say 'Y' here if you want your kernel to run on the D-Link |
| 15 | DSM-320 Wireless Media Player. | 15 | DSM-320 Wireless Media Player. |
| 16 | 16 | ||
| 17 | config MACH_ACS5K | ||
| 18 | bool "Brivo Systems LLC, ACS-5000 Master board" | ||
| 19 | help | ||
| 20 | say 'Y' here if you want your kernel to run on the Brivo | ||
| 21 | Systems LLC, ACS-5000 Master board. | ||
| 22 | |||
| 17 | endmenu | 23 | endmenu |
| 18 | 24 | ||
| 19 | endif | 25 | endif |
diff --git a/arch/arm/mach-ks8695/Makefile b/arch/arm/mach-ks8695/Makefile index f735d2cc0294..7e3e8160ed30 100644 --- a/arch/arm/mach-ks8695/Makefile +++ b/arch/arm/mach-ks8695/Makefile | |||
| @@ -17,3 +17,4 @@ obj-$(CONFIG_LEDS) += leds.o | |||
| 17 | # Board-specific support | 17 | # Board-specific support |
| 18 | obj-$(CONFIG_MACH_KS8695) += board-micrel.o | 18 | obj-$(CONFIG_MACH_KS8695) += board-micrel.o |
| 19 | obj-$(CONFIG_MACH_DSM320) += board-dsm320.o | 19 | obj-$(CONFIG_MACH_DSM320) += board-dsm320.o |
| 20 | obj-$(CONFIG_MACH_ACS5K) += board-acs5k.o | ||
diff --git a/arch/arm/mach-ks8695/board-acs5k.c b/arch/arm/mach-ks8695/board-acs5k.c new file mode 100644 index 000000000000..9e3e5a640ad2 --- /dev/null +++ b/arch/arm/mach-ks8695/board-acs5k.c | |||
| @@ -0,0 +1,233 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-ks8695/board-acs5k.c | ||
| 3 | * | ||
| 4 | * Brivo Systems LLC, ACS-5000 Master Board | ||
| 5 | * | ||
| 6 | * Copyright 2008 Simtec Electronics | ||
| 7 | * Daniel Silverstone <dsilvers@simtec.co.uk> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/types.h> | ||
| 16 | #include <linux/interrupt.h> | ||
| 17 | #include <linux/init.h> | ||
| 18 | #include <linux/platform_device.h> | ||
| 19 | |||
| 20 | #include <linux/i2c.h> | ||
| 21 | #include <linux/i2c-algo-bit.h> | ||
| 22 | #include <linux/i2c-gpio.h> | ||
| 23 | #include <linux/i2c/pca953x.h> | ||
| 24 | |||
| 25 | #include <linux/mtd/mtd.h> | ||
| 26 | #include <linux/mtd/map.h> | ||
| 27 | #include <linux/mtd/physmap.h> | ||
| 28 | #include <linux/mtd/partitions.h> | ||
| 29 | |||
| 30 | #include <asm/mach-types.h> | ||
| 31 | |||
| 32 | #include <asm/mach/arch.h> | ||
| 33 | #include <asm/mach/map.h> | ||
| 34 | #include <asm/mach/irq.h> | ||
| 35 | |||
| 36 | #include <mach/devices.h> | ||
| 37 | #include <mach/gpio.h> | ||
| 38 | |||
| 39 | #include "generic.h" | ||
| 40 | |||
| 41 | static struct i2c_gpio_platform_data acs5k_i2c_device_platdata = { | ||
| 42 | .sda_pin = 4, | ||
| 43 | .scl_pin = 5, | ||
| 44 | .udelay = 10, | ||
| 45 | }; | ||
| 46 | |||
| 47 | static struct platform_device acs5k_i2c_device = { | ||
| 48 | .name = "i2c-gpio", | ||
| 49 | .id = -1, | ||
| 50 | .num_resources = 0, | ||
| 51 | .resource = NULL, | ||
| 52 | .dev = { | ||
| 53 | .platform_data = &acs5k_i2c_device_platdata, | ||
| 54 | }, | ||
| 55 | }; | ||
| 56 | |||
| 57 | static int acs5k_pca9555_setup(struct i2c_client *client, | ||
| 58 | unsigned gpio_base, unsigned ngpio, | ||
| 59 | void *context) | ||
| 60 | { | ||
| 61 | static int acs5k_gpio_value[] = { | ||
| 62 | -1, -1, -1, -1, -1, -1, -1, 0, 1, 1, -1, 0, 1, 0, -1, -1 | ||
| 63 | }; | ||
| 64 | int n; | ||
| 65 | |||
| 66 | for (n = 0; n < ARRAY_SIZE(acs5k_gpio_value); ++n) { | ||
| 67 | gpio_request(gpio_base + n, "ACS-5000 GPIO Expander"); | ||
| 68 | if (acs5k_gpio_value[n] < 0) | ||
| 69 | gpio_direction_input(gpio_base + n); | ||
| 70 | else | ||
| 71 | gpio_direction_output(gpio_base + n, | ||
| 72 | acs5k_gpio_value[n]); | ||
| 73 | gpio_export(gpio_base + n, 0); /* Export, direction locked down */ | ||
| 74 | } | ||
| 75 | |||
| 76 | return 0; | ||
| 77 | } | ||
| 78 | |||
| 79 | static struct pca953x_platform_data acs5k_i2c_pca9555_platdata = { | ||
| 80 | .gpio_base = 16, /* Start directly after the CPU's GPIO */ | ||
| 81 | .invert = 0, /* Do not invert */ | ||
| 82 | .setup = acs5k_pca9555_setup, | ||
| 83 | }; | ||
| 84 | |||
| 85 | static struct i2c_board_info acs5k_i2c_devs[] __initdata = { | ||
| 86 | { | ||
| 87 | I2C_BOARD_INFO("pcf8563", 0x51), | ||
| 88 | }, | ||
| 89 | { | ||
| 90 | I2C_BOARD_INFO("pca9555", 0x20), | ||
| 91 | .platform_data = &acs5k_i2c_pca9555_platdata, | ||
| 92 | }, | ||
| 93 | }; | ||
| 94 | |||
| 95 | static void __devinit acs5k_i2c_init(void) | ||
| 96 | { | ||
| 97 | /* The gpio interface */ | ||
| 98 | platform_device_register(&acs5k_i2c_device); | ||
| 99 | /* I2C devices */ | ||
| 100 | i2c_register_board_info(0, acs5k_i2c_devs, | ||
| 101 | ARRAY_SIZE(acs5k_i2c_devs)); | ||
| 102 | } | ||
| 103 | |||
| 104 | static struct mtd_partition acs5k_nor_partitions[] = { | ||
| 105 | [0] = { | ||
| 106 | .name = "Boot Agent and config", | ||
| 107 | .size = SZ_256K, | ||
| 108 | .offset = 0, | ||
| 109 | .mask_flags = MTD_WRITEABLE, | ||
| 110 | }, | ||
| 111 | [1] = { | ||
| 112 | .name = "Kernel", | ||
| 113 | .size = SZ_1M, | ||
| 114 | .offset = SZ_256K, | ||
| 115 | }, | ||
| 116 | [2] = { | ||
| 117 | .name = "SquashFS1", | ||
| 118 | .size = SZ_2M, | ||
| 119 | .offset = SZ_256K + SZ_1M, | ||
| 120 | }, | ||
| 121 | [3] = { | ||
| 122 | .name = "SquashFS2", | ||
| 123 | .size = SZ_4M + SZ_2M, | ||
| 124 | .offset = SZ_256K + SZ_1M + SZ_2M, | ||
| 125 | }, | ||
| 126 | [4] = { | ||
| 127 | .name = "Data", | ||
| 128 | .size = SZ_16M + SZ_4M + SZ_2M + SZ_512K, /* 22.5 MB */ | ||
| 129 | .offset = SZ_256K + SZ_8M + SZ_1M, | ||
| 130 | } | ||
| 131 | }; | ||
| 132 | |||
| 133 | static struct physmap_flash_data acs5k_nor_pdata = { | ||
| 134 | .width = 4, | ||
| 135 | .nr_parts = ARRAY_SIZE(acs5k_nor_partitions), | ||
| 136 | .parts = acs5k_nor_partitions, | ||
| 137 | }; | ||
| 138 | |||
| 139 | static struct resource acs5k_nor_resource[] = { | ||
| 140 | [0] = { | ||
| 141 | .start = SZ_32M, /* We expect the bootloader to map | ||
| 142 | * the flash here. | ||
| 143 | */ | ||
| 144 | .end = SZ_32M + SZ_16M - 1, | ||
| 145 | .flags = IORESOURCE_MEM, | ||
| 146 | }, | ||
| 147 | [1] = { | ||
| 148 | .start = SZ_32M + SZ_16M, | ||
| 149 | .end = SZ_32M + SZ_32M - SZ_256K - 1, | ||
| 150 | .flags = IORESOURCE_MEM, | ||
| 151 | } | ||
| 152 | }; | ||
| 153 | |||
| 154 | static struct platform_device acs5k_device_nor = { | ||
| 155 | .name = "physmap-flash", | ||
| 156 | .id = -1, | ||
| 157 | .num_resources = ARRAY_SIZE(acs5k_nor_resource), | ||
| 158 | .resource = acs5k_nor_resource, | ||
| 159 | .dev = { | ||
| 160 | .platform_data = &acs5k_nor_pdata, | ||
| 161 | }, | ||
| 162 | }; | ||
| 163 | |||
| 164 | static void __init acs5k_register_nor(void) | ||
| 165 | { | ||
| 166 | int ret; | ||
| 167 | |||
| 168 | if (acs5k_nor_partitions[0].mask_flags == 0) | ||
| 169 | printk(KERN_WARNING "Warning: Unprotecting bootloader and configuration partition\n"); | ||
| 170 | |||
| 171 | ret = platform_device_register(&acs5k_device_nor); | ||
| 172 | if (ret < 0) | ||
| 173 | printk(KERN_ERR "failed to register physmap-flash device\n"); | ||
| 174 | } | ||
| 175 | |||
| 176 | static int __init acs5k_protection_setup(char *s) | ||
| 177 | { | ||
| 178 | /* We can't allocate anything here but we should be able | ||
| 179 | * to trivially parse s and decide if we can protect the | ||
| 180 | * bootloader partition or not | ||
| 181 | */ | ||
| 182 | if (strcmp(s, "no") == 0) | ||
| 183 | acs5k_nor_partitions[0].mask_flags = 0; | ||
| 184 | |||
| 185 | return 1; | ||
| 186 | } | ||
| 187 | |||
| 188 | __setup("protect_bootloader=", acs5k_protection_setup); | ||
| 189 | |||
| 190 | static void __init acs5k_init_gpio(void) | ||
| 191 | { | ||
| 192 | int i; | ||
| 193 | |||
| 194 | ks8695_register_gpios(); | ||
| 195 | for (i = 0; i < 4; ++i) | ||
| 196 | gpio_request(i, "ACS5K IRQ"); | ||
| 197 | gpio_request(7, "ACS5K KS_FRDY"); | ||
| 198 | for (i = 8; i < 16; ++i) | ||
| 199 | gpio_request(i, "ACS5K Unused"); | ||
| 200 | |||
| 201 | gpio_request(3, "ACS5K CAN Control"); | ||
| 202 | gpio_request(6, "ACS5K Heartbeat"); | ||
| 203 | gpio_direction_output(3, 1); /* Default CAN_RESET high */ | ||
| 204 | gpio_direction_output(6, 0); /* Default KS8695_ACTIVE low */ | ||
| 205 | gpio_export(3, 0); /* export CAN_RESET as output only */ | ||
| 206 | gpio_export(6, 0); /* export KS8695_ACTIVE as output only */ | ||
| 207 | } | ||
| 208 | |||
| 209 | static void __init acs5k_init(void) | ||
| 210 | { | ||
| 211 | acs5k_init_gpio(); | ||
| 212 | |||
| 213 | /* Network device */ | ||
| 214 | ks8695_add_device_lan(); /* eth0 = LAN */ | ||
| 215 | ks8695_add_device_wan(); /* ethX = WAN */ | ||
| 216 | |||
| 217 | /* NOR devices */ | ||
| 218 | acs5k_register_nor(); | ||
| 219 | |||
| 220 | /* I2C bus */ | ||
| 221 | acs5k_i2c_init(); | ||
| 222 | } | ||
| 223 | |||
| 224 | MACHINE_START(ACS5K, "Brivo Systems LLC ACS-5000 Master board") | ||
| 225 | /* Maintainer: Simtec Electronics. */ | ||
| 226 | .phys_io = KS8695_IO_PA, | ||
| 227 | .io_pg_offst = (KS8695_IO_VA >> 18) & 0xfffc, | ||
| 228 | .boot_params = KS8695_SDRAM_PA + 0x100, | ||
| 229 | .map_io = ks8695_map_io, | ||
| 230 | .init_irq = ks8695_init_irq, | ||
| 231 | .init_machine = acs5k_init, | ||
| 232 | .timer = &ks8695_timer, | ||
| 233 | MACHINE_END | ||
diff --git a/arch/arm/mach-ks8695/include/mach/memory.h b/arch/arm/mach-ks8695/include/mach/memory.h index 6d5887cf5742..76e5308685a4 100644 --- a/arch/arm/mach-ks8695/include/mach/memory.h +++ b/arch/arm/mach-ks8695/include/mach/memory.h | |||
| @@ -35,7 +35,11 @@ extern struct bus_type platform_bus_type; | |||
| 35 | __phys_to_virt(x) : __bus_to_virt(x)); }) | 35 | __phys_to_virt(x) : __bus_to_virt(x)); }) |
| 36 | #define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \ | 36 | #define __arch_virt_to_dma(dev, x) ({ is_lbus_device(dev) ? \ |
| 37 | (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); }) | 37 | (dma_addr_t)__virt_to_phys(x) : (dma_addr_t)__virt_to_bus(x); }) |
| 38 | #define __arch_page_to_dma(dev, x) __arch_virt_to_dma(dev, page_address(x)) | 38 | #define __arch_page_to_dma(dev, x) \ |
| 39 | ({ dma_addr_t __dma = page_to_phys(page); \ | ||
| 40 | if (!is_lbus_device(dev)) \ | ||
| 41 | __dma = __dma - PHYS_OFFSET + KS8695_PCIMEM_PA; \ | ||
| 42 | __dma; }) | ||
| 39 | 43 | ||
| 40 | #endif | 44 | #endif |
| 41 | 45 | ||
diff --git a/arch/arm/mach-ks8695/include/mach/system.h b/arch/arm/mach-ks8695/include/mach/system.h index 5a9b032bdbeb..fb1dda9be2d0 100644 --- a/arch/arm/mach-ks8695/include/mach/system.h +++ b/arch/arm/mach-ks8695/include/mach/system.h | |||
| @@ -27,7 +27,7 @@ static void arch_idle(void) | |||
| 27 | 27 | ||
| 28 | } | 28 | } |
| 29 | 29 | ||
| 30 | static void arch_reset(char mode) | 30 | static void arch_reset(char mode, const char *cmd) |
| 31 | { | 31 | { |
| 32 | unsigned int reg; | 32 | unsigned int reg; |
| 33 | 33 | ||
diff --git a/arch/arm/mach-l7200/include/mach/system.h b/arch/arm/mach-l7200/include/mach/system.h index 5272abee0d0e..e0dd3b6ae4aa 100644 --- a/arch/arm/mach-l7200/include/mach/system.h +++ b/arch/arm/mach-l7200/include/mach/system.h | |||
| @@ -19,7 +19,7 @@ static inline void arch_idle(void) | |||
| 19 | *(unsigned long *)(IO_BASE + 0x50004) = 1; /* idle mode */ | 19 | *(unsigned long *)(IO_BASE + 0x50004) = 1; /* idle mode */ |
| 20 | } | 20 | } |
| 21 | 21 | ||
| 22 | static inline void arch_reset(char mode) | 22 | static inline void arch_reset(char mode, const char *cmd) |
| 23 | { | 23 | { |
| 24 | if (mode == 's') { | 24 | if (mode == 's') { |
| 25 | cpu_reset(0); | 25 | cpu_reset(0); |
diff --git a/arch/arm/mach-lh7a40x/include/mach/system.h b/arch/arm/mach-lh7a40x/include/mach/system.h index fa46bb1ef07b..45a56d3b93d7 100644 --- a/arch/arm/mach-lh7a40x/include/mach/system.h +++ b/arch/arm/mach-lh7a40x/include/mach/system.h | |||
| @@ -13,7 +13,7 @@ static inline void arch_idle(void) | |||
| 13 | cpu_do_idle (); | 13 | cpu_do_idle (); |
| 14 | } | 14 | } |
| 15 | 15 | ||
| 16 | static inline void arch_reset(char mode) | 16 | static inline void arch_reset(char mode, const char *cmd) |
| 17 | { | 17 | { |
| 18 | cpu_reset (0); | 18 | cpu_reset (0); |
| 19 | } | 19 | } |
diff --git a/arch/arm/mach-loki/include/mach/system.h b/arch/arm/mach-loki/include/mach/system.h index 8db1147d4ec5..c1de36fe9b37 100644 --- a/arch/arm/mach-loki/include/mach/system.h +++ b/arch/arm/mach-loki/include/mach/system.h | |||
| @@ -17,7 +17,7 @@ static inline void arch_idle(void) | |||
| 17 | cpu_do_idle(); | 17 | cpu_do_idle(); |
| 18 | } | 18 | } |
| 19 | 19 | ||
| 20 | static inline void arch_reset(char mode) | 20 | static inline void arch_reset(char mode, const char *cmd) |
| 21 | { | 21 | { |
| 22 | /* | 22 | /* |
| 23 | * Enable soft reset to assert RSTOUTn. | 23 | * Enable soft reset to assert RSTOUTn. |
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig new file mode 100644 index 000000000000..c6a564fc4a7c --- /dev/null +++ b/arch/arm/mach-mmp/Kconfig | |||
| @@ -0,0 +1,47 @@ | |||
| 1 | if ARCH_MMP | ||
| 2 | |||
| 3 | menu "Marvell PXA168/910 Implmentations" | ||
| 4 | |||
| 5 | config MACH_ASPENITE | ||
| 6 | bool "Marvell's PXA168 Aspenite Development Board" | ||
| 7 | select CPU_PXA168 | ||
| 8 | help | ||
| 9 | Say 'Y' here if you want to support the Marvell PXA168-based | ||
| 10 | Aspenite Development Board. | ||
| 11 | |||
| 12 | config MACH_ZYLONITE2 | ||
| 13 | bool "Marvell's PXA168 Zylonite2 Development Board" | ||
| 14 | select CPU_PXA168 | ||
| 15 | help | ||
| 16 | Say 'Y' here if you want to support the Marvell PXA168-based | ||
| 17 | Zylonite2 Development Board. | ||
| 18 | |||
| 19 | config MACH_TAVOREVB | ||
| 20 | bool "Marvell's PXA910 TavorEVB Development Board" | ||
| 21 | select CPU_PXA910 | ||
| 22 | help | ||
| 23 | Say 'Y' here if you want to support the Marvell PXA910-based | ||
| 24 | TavorEVB Development Board. | ||
| 25 | |||
| 26 | config MACH_TTC_DKB | ||
| 27 | bool "Marvell's PXA910 TavorEVB Development Board" | ||
| 28 | select CPU_PXA910 | ||
| 29 | help | ||
| 30 | Say 'Y' here if you want to support the Marvell PXA910-based | ||
| 31 | TTC_DKB Development Board. | ||
| 32 | |||
| 33 | endmenu | ||
| 34 | |||
| 35 | config CPU_PXA168 | ||
| 36 | bool | ||
| 37 | select CPU_MOHAWK | ||
| 38 | help | ||
| 39 | Select code specific to PXA168 | ||
| 40 | |||
| 41 | config CPU_PXA910 | ||
| 42 | bool | ||
| 43 | select CPU_MOHAWK | ||
| 44 | help | ||
| 45 | Select code specific to PXA910 | ||
| 46 | |||
| 47 | endif | ||
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile new file mode 100644 index 000000000000..6883e6584883 --- /dev/null +++ b/arch/arm/mach-mmp/Makefile | |||
| @@ -0,0 +1,15 @@ | |||
| 1 | # | ||
| 2 | # Makefile for Marvell's PXA168 processors line | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-y += common.o clock.o devices.o irq.o time.o | ||
| 6 | |||
| 7 | # SoC support | ||
| 8 | obj-$(CONFIG_CPU_PXA168) += pxa168.o | ||
| 9 | obj-$(CONFIG_CPU_PXA910) += pxa910.o | ||
| 10 | |||
| 11 | # board support | ||
| 12 | obj-$(CONFIG_MACH_ASPENITE) += aspenite.o | ||
| 13 | obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o | ||
| 14 | obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o | ||
| 15 | obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o | ||
diff --git a/arch/arm/mach-mmp/Makefile.boot b/arch/arm/mach-mmp/Makefile.boot new file mode 100644 index 000000000000..574a4aa8321a --- /dev/null +++ b/arch/arm/mach-mmp/Makefile.boot | |||
| @@ -0,0 +1 @@ | |||
| zreladdr-y := 0x00008000 | |||
diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c new file mode 100644 index 000000000000..4562452d4074 --- /dev/null +++ b/arch/arm/mach-mmp/aspenite.c | |||
| @@ -0,0 +1,117 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/aspenite.c | ||
| 3 | * | ||
| 4 | * Support for the Marvell PXA168-based Aspenite and Zylonite2 | ||
| 5 | * Development Platform. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * publishhed by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/kernel.h> | ||
| 14 | #include <linux/platform_device.h> | ||
| 15 | #include <linux/smc91x.h> | ||
| 16 | |||
| 17 | #include <asm/mach-types.h> | ||
| 18 | #include <asm/mach/arch.h> | ||
| 19 | #include <mach/addr-map.h> | ||
| 20 | #include <mach/mfp-pxa168.h> | ||
| 21 | #include <mach/pxa168.h> | ||
| 22 | #include <mach/gpio.h> | ||
| 23 | |||
| 24 | #include "common.h" | ||
| 25 | |||
| 26 | static unsigned long common_pin_config[] __initdata = { | ||
| 27 | /* Data Flash Interface */ | ||
| 28 | GPIO0_DFI_D15, | ||
| 29 | GPIO1_DFI_D14, | ||
| 30 | GPIO2_DFI_D13, | ||
| 31 | GPIO3_DFI_D12, | ||
| 32 | GPIO4_DFI_D11, | ||
| 33 | GPIO5_DFI_D10, | ||
| 34 | GPIO6_DFI_D9, | ||
| 35 | GPIO7_DFI_D8, | ||
| 36 | GPIO8_DFI_D7, | ||
| 37 | GPIO9_DFI_D6, | ||
| 38 | GPIO10_DFI_D5, | ||
| 39 | GPIO11_DFI_D4, | ||
| 40 | GPIO12_DFI_D3, | ||
| 41 | GPIO13_DFI_D2, | ||
| 42 | GPIO14_DFI_D1, | ||
| 43 | GPIO15_DFI_D0, | ||
| 44 | |||
| 45 | /* Static Memory Controller */ | ||
| 46 | GPIO18_SMC_nCS0, | ||
| 47 | GPIO34_SMC_nCS1, | ||
| 48 | GPIO23_SMC_nLUA, | ||
| 49 | GPIO25_SMC_nLLA, | ||
| 50 | GPIO28_SMC_RDY, | ||
| 51 | GPIO29_SMC_SCLK, | ||
| 52 | GPIO35_SMC_BE1, | ||
| 53 | GPIO36_SMC_BE2, | ||
| 54 | GPIO27_GPIO, /* Ethernet IRQ */ | ||
| 55 | |||
| 56 | /* UART1 */ | ||
| 57 | GPIO107_UART1_RXD, | ||
| 58 | GPIO108_UART1_TXD, | ||
| 59 | }; | ||
| 60 | |||
| 61 | static struct smc91x_platdata smc91x_info = { | ||
| 62 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
| 63 | }; | ||
| 64 | |||
| 65 | static struct resource smc91x_resources[] = { | ||
| 66 | [0] = { | ||
| 67 | .start = SMC_CS1_PHYS_BASE + 0x300, | ||
| 68 | .end = SMC_CS1_PHYS_BASE + 0xfffff, | ||
| 69 | .flags = IORESOURCE_MEM, | ||
| 70 | }, | ||
| 71 | [1] = { | ||
| 72 | .start = gpio_to_irq(27), | ||
| 73 | .end = gpio_to_irq(27), | ||
| 74 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, | ||
| 75 | } | ||
| 76 | }; | ||
| 77 | |||
| 78 | static struct platform_device smc91x_device = { | ||
| 79 | .name = "smc91x", | ||
| 80 | .id = 0, | ||
| 81 | .dev = { | ||
| 82 | .platform_data = &smc91x_info, | ||
| 83 | }, | ||
| 84 | .num_resources = ARRAY_SIZE(smc91x_resources), | ||
| 85 | .resource = smc91x_resources, | ||
| 86 | }; | ||
| 87 | |||
| 88 | static void __init common_init(void) | ||
| 89 | { | ||
| 90 | mfp_config(ARRAY_AND_SIZE(common_pin_config)); | ||
| 91 | |||
| 92 | /* on-chip devices */ | ||
| 93 | pxa168_add_uart(1); | ||
| 94 | |||
| 95 | /* off-chip devices */ | ||
| 96 | platform_device_register(&smc91x_device); | ||
| 97 | } | ||
| 98 | |||
| 99 | MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform") | ||
| 100 | .phys_io = APB_PHYS_BASE, | ||
| 101 | .boot_params = 0x00000100, | ||
| 102 | .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, | ||
| 103 | .map_io = pxa_map_io, | ||
| 104 | .init_irq = pxa168_init_irq, | ||
| 105 | .timer = &pxa168_timer, | ||
| 106 | .init_machine = common_init, | ||
| 107 | MACHINE_END | ||
| 108 | |||
| 109 | MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform") | ||
| 110 | .phys_io = APB_PHYS_BASE, | ||
| 111 | .boot_params = 0x00000100, | ||
| 112 | .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, | ||
| 113 | .map_io = pxa_map_io, | ||
| 114 | .init_irq = pxa168_init_irq, | ||
| 115 | .timer = &pxa168_timer, | ||
| 116 | .init_machine = common_init, | ||
| 117 | MACHINE_END | ||
diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c new file mode 100644 index 000000000000..2d9cc5a7122f --- /dev/null +++ b/arch/arm/mach-mmp/clock.c | |||
| @@ -0,0 +1,83 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/clock.c | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/module.h> | ||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <linux/list.h> | ||
| 12 | #include <linux/spinlock.h> | ||
| 13 | #include <linux/clk.h> | ||
| 14 | #include <linux/io.h> | ||
| 15 | |||
| 16 | #include <mach/regs-apbc.h> | ||
| 17 | #include "clock.h" | ||
| 18 | |||
| 19 | static void apbc_clk_enable(struct clk *clk) | ||
| 20 | { | ||
| 21 | uint32_t clk_rst; | ||
| 22 | |||
| 23 | clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(clk->fnclksel); | ||
| 24 | __raw_writel(clk_rst, clk->clk_rst); | ||
| 25 | } | ||
| 26 | |||
| 27 | static void apbc_clk_disable(struct clk *clk) | ||
| 28 | { | ||
| 29 | __raw_writel(0, clk->clk_rst); | ||
| 30 | } | ||
| 31 | |||
| 32 | struct clkops apbc_clk_ops = { | ||
| 33 | .enable = apbc_clk_enable, | ||
| 34 | .disable = apbc_clk_disable, | ||
| 35 | }; | ||
| 36 | |||
| 37 | static DEFINE_SPINLOCK(clocks_lock); | ||
| 38 | |||
| 39 | int clk_enable(struct clk *clk) | ||
| 40 | { | ||
| 41 | unsigned long flags; | ||
| 42 | |||
| 43 | spin_lock_irqsave(&clocks_lock, flags); | ||
| 44 | if (clk->enabled++ == 0) | ||
| 45 | clk->ops->enable(clk); | ||
| 46 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
| 47 | return 0; | ||
| 48 | } | ||
| 49 | EXPORT_SYMBOL(clk_enable); | ||
| 50 | |||
| 51 | void clk_disable(struct clk *clk) | ||
| 52 | { | ||
| 53 | unsigned long flags; | ||
| 54 | |||
| 55 | WARN_ON(clk->enabled == 0); | ||
| 56 | |||
| 57 | spin_lock_irqsave(&clocks_lock, flags); | ||
| 58 | if (--clk->enabled == 0) | ||
| 59 | clk->ops->disable(clk); | ||
| 60 | spin_unlock_irqrestore(&clocks_lock, flags); | ||
| 61 | } | ||
| 62 | EXPORT_SYMBOL(clk_disable); | ||
| 63 | |||
| 64 | unsigned long clk_get_rate(struct clk *clk) | ||
| 65 | { | ||
| 66 | unsigned long rate; | ||
| 67 | |||
| 68 | if (clk->ops->getrate) | ||
| 69 | rate = clk->ops->getrate(clk); | ||
| 70 | else | ||
| 71 | rate = clk->rate; | ||
| 72 | |||
| 73 | return rate; | ||
| 74 | } | ||
| 75 | EXPORT_SYMBOL(clk_get_rate); | ||
| 76 | |||
| 77 | void clks_register(struct clk_lookup *clks, size_t num) | ||
| 78 | { | ||
| 79 | int i; | ||
| 80 | |||
| 81 | for (i = 0; i < num; i++) | ||
| 82 | clkdev_add(&clks[i]); | ||
| 83 | } | ||
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h new file mode 100644 index 000000000000..ed967e78e6a8 --- /dev/null +++ b/arch/arm/mach-mmp/clock.h | |||
| @@ -0,0 +1,71 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/clock.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <asm/clkdev.h> | ||
| 10 | |||
| 11 | struct clkops { | ||
| 12 | void (*enable)(struct clk *); | ||
| 13 | void (*disable)(struct clk *); | ||
| 14 | unsigned long (*getrate)(struct clk *); | ||
| 15 | }; | ||
| 16 | |||
| 17 | struct clk { | ||
| 18 | const struct clkops *ops; | ||
| 19 | |||
| 20 | void __iomem *clk_rst; /* clock reset control register */ | ||
| 21 | int fnclksel; /* functional clock select (APBC) */ | ||
| 22 | uint32_t enable_val; /* value for clock enable (APMU) */ | ||
| 23 | unsigned long rate; | ||
| 24 | int enabled; | ||
| 25 | }; | ||
| 26 | |||
| 27 | extern struct clkops apbc_clk_ops; | ||
| 28 | |||
| 29 | #define APBC_CLK(_name, _reg, _fnclksel, _rate) \ | ||
| 30 | struct clk clk_##_name = { \ | ||
| 31 | .clk_rst = (void __iomem *)APBC_##_reg, \ | ||
| 32 | .fnclksel = _fnclksel, \ | ||
| 33 | .rate = _rate, \ | ||
| 34 | .ops = &apbc_clk_ops, \ | ||
| 35 | } | ||
| 36 | |||
| 37 | #define APBC_CLK_OPS(_name, _reg, _fnclksel, _rate, _ops) \ | ||
| 38 | struct clk clk_##_name = { \ | ||
| 39 | .clk_rst = (void __iomem *)APBC_##_reg, \ | ||
| 40 | .fnclksel = _fnclksel, \ | ||
| 41 | .rate = _rate, \ | ||
| 42 | .ops = _ops, \ | ||
| 43 | } | ||
| 44 | |||
| 45 | #define APMU_CLK(_name, _reg, _eval, _rate) \ | ||
| 46 | struct clk clk_##_name = { \ | ||
| 47 | .clk_rst = (void __iomem *)APMU_##_reg, \ | ||
| 48 | .enable_val = _eval, \ | ||
| 49 | .rate = _rate, \ | ||
| 50 | .ops = &apmu_clk_ops, \ | ||
| 51 | } | ||
| 52 | |||
| 53 | #define APMU_CLK_OPS(_name, _reg, _eval, _rate, _ops) \ | ||
| 54 | struct clk clk_##_name = { \ | ||
| 55 | .clk_rst = (void __iomem *)APMU_##_reg, \ | ||
| 56 | .enable_val = _eval, \ | ||
| 57 | .rate = _rate, \ | ||
| 58 | .ops = _ops, \ | ||
| 59 | } | ||
| 60 | |||
| 61 | #define INIT_CLKREG(_clk, _devname, _conname) \ | ||
| 62 | { \ | ||
| 63 | .clk = _clk, \ | ||
| 64 | .dev_id = _devname, \ | ||
| 65 | .con_id = _conname, \ | ||
| 66 | } | ||
| 67 | |||
| 68 | extern struct clk clk_pxa168_gpio; | ||
| 69 | extern struct clk clk_pxa168_timers; | ||
| 70 | |||
| 71 | extern void clks_register(struct clk_lookup *, size_t); | ||
diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c new file mode 100644 index 000000000000..e1e66c18b446 --- /dev/null +++ b/arch/arm/mach-mmp/common.c | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/common.c | ||
| 3 | * | ||
| 4 | * Code common to PXA168 processor lines | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | |||
| 14 | #include <asm/page.h> | ||
| 15 | #include <asm/mach/map.h> | ||
| 16 | #include <mach/addr-map.h> | ||
| 17 | |||
| 18 | #include "common.h" | ||
| 19 | |||
| 20 | static struct map_desc standard_io_desc[] __initdata = { | ||
| 21 | { | ||
| 22 | .pfn = __phys_to_pfn(APB_PHYS_BASE), | ||
| 23 | .virtual = APB_VIRT_BASE, | ||
| 24 | .length = APB_PHYS_SIZE, | ||
| 25 | .type = MT_DEVICE, | ||
| 26 | }, { | ||
| 27 | .pfn = __phys_to_pfn(AXI_PHYS_BASE), | ||
| 28 | .virtual = AXI_VIRT_BASE, | ||
| 29 | .length = AXI_PHYS_SIZE, | ||
| 30 | .type = MT_DEVICE, | ||
| 31 | }, | ||
| 32 | }; | ||
| 33 | |||
| 34 | void __init pxa_map_io(void) | ||
| 35 | { | ||
| 36 | iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); | ||
| 37 | } | ||
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h new file mode 100644 index 000000000000..c33fbbc49417 --- /dev/null +++ b/arch/arm/mach-mmp/common.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) | ||
| 2 | |||
| 3 | struct sys_timer; | ||
| 4 | |||
| 5 | extern void timer_init(int irq); | ||
| 6 | |||
| 7 | extern struct sys_timer pxa168_timer; | ||
| 8 | extern struct sys_timer pxa910_timer; | ||
| 9 | extern void __init pxa168_init_irq(void); | ||
| 10 | extern void __init pxa910_init_irq(void); | ||
| 11 | |||
| 12 | extern void __init icu_init_irq(void); | ||
| 13 | extern void __init pxa_map_io(void); | ||
diff --git a/arch/arm/mach-mmp/devices.c b/arch/arm/mach-mmp/devices.c new file mode 100644 index 000000000000..191d9dea8731 --- /dev/null +++ b/arch/arm/mach-mmp/devices.c | |||
| @@ -0,0 +1,69 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/devices.c | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/init.h> | ||
| 10 | #include <linux/platform_device.h> | ||
| 11 | #include <linux/dma-mapping.h> | ||
| 12 | |||
| 13 | #include <asm/irq.h> | ||
| 14 | #include <mach/devices.h> | ||
| 15 | |||
| 16 | int __init pxa_register_device(struct pxa_device_desc *desc, | ||
| 17 | void *data, size_t size) | ||
| 18 | { | ||
| 19 | struct platform_device *pdev; | ||
| 20 | struct resource res[2 + MAX_RESOURCE_DMA]; | ||
| 21 | int i, ret = 0, nres = 0; | ||
| 22 | |||
| 23 | pdev = platform_device_alloc(desc->drv_name, desc->id); | ||
| 24 | if (pdev == NULL) | ||
| 25 | return -ENOMEM; | ||
| 26 | |||
| 27 | pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); | ||
| 28 | |||
| 29 | memset(res, 0, sizeof(res)); | ||
| 30 | |||
| 31 | if (desc->start != -1ul && desc->size > 0) { | ||
| 32 | res[nres].start = desc->start; | ||
| 33 | res[nres].end = desc->start + desc->size - 1; | ||
| 34 | res[nres].flags = IORESOURCE_MEM; | ||
| 35 | nres++; | ||
| 36 | } | ||
| 37 | |||
| 38 | if (desc->irq != NO_IRQ) { | ||
| 39 | res[nres].start = desc->irq; | ||
| 40 | res[nres].end = desc->irq; | ||
| 41 | res[nres].flags = IORESOURCE_IRQ; | ||
| 42 | nres++; | ||
| 43 | } | ||
| 44 | |||
| 45 | for (i = 0; i < MAX_RESOURCE_DMA; i++, nres++) { | ||
| 46 | if (desc->dma[i] == 0) | ||
| 47 | break; | ||
| 48 | |||
| 49 | res[nres].start = desc->dma[i]; | ||
| 50 | res[nres].end = desc->dma[i]; | ||
| 51 | res[nres].flags = IORESOURCE_DMA; | ||
| 52 | } | ||
| 53 | |||
| 54 | ret = platform_device_add_resources(pdev, res, nres); | ||
| 55 | if (ret) { | ||
| 56 | platform_device_put(pdev); | ||
| 57 | return ret; | ||
| 58 | } | ||
| 59 | |||
| 60 | if (data && size) { | ||
| 61 | ret = platform_device_add_data(pdev, data, size); | ||
| 62 | if (ret) { | ||
| 63 | platform_device_put(pdev); | ||
| 64 | return ret; | ||
| 65 | } | ||
| 66 | } | ||
| 67 | |||
| 68 | return platform_device_add(pdev); | ||
| 69 | } | ||
diff --git a/arch/arm/mach-mmp/include/mach/addr-map.h b/arch/arm/mach-mmp/include/mach/addr-map.h new file mode 100644 index 000000000000..3254089a644d --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/addr-map.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/addr-map.h | ||
| 3 | * | ||
| 4 | * Common address map definitions | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_MACH_ADDR_MAP_H | ||
| 12 | #define __ASM_MACH_ADDR_MAP_H | ||
| 13 | |||
| 14 | /* APB - Application Subsystem Peripheral Bus | ||
| 15 | * | ||
| 16 | * NOTE: the DMA controller registers are actually on the AXI fabric #1 | ||
| 17 | * slave port to AHB/APB bridge, due to its close relationship to those | ||
| 18 | * peripherals on APB, let's count it into the ABP mapping area. | ||
| 19 | */ | ||
| 20 | #define APB_PHYS_BASE 0xd4000000 | ||
| 21 | #define APB_VIRT_BASE 0xfe000000 | ||
| 22 | #define APB_PHYS_SIZE 0x00200000 | ||
| 23 | |||
| 24 | #define AXI_PHYS_BASE 0xd4200000 | ||
| 25 | #define AXI_VIRT_BASE 0xfe200000 | ||
| 26 | #define AXI_PHYS_SIZE 0x00200000 | ||
| 27 | |||
| 28 | /* Static Memory Controller - Chip Select 0 and 1 */ | ||
| 29 | #define SMC_CS0_PHYS_BASE 0x80000000 | ||
| 30 | #define SMC_CS0_PHYS_SIZE 0x10000000 | ||
| 31 | #define SMC_CS1_PHYS_BASE 0x90000000 | ||
| 32 | #define SMC_CS1_PHYS_SIZE 0x10000000 | ||
| 33 | |||
| 34 | #endif /* __ASM_MACH_ADDR_MAP_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/clkdev.h b/arch/arm/mach-mmp/include/mach/clkdev.h new file mode 100644 index 000000000000..2fb354e54e0d --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/clkdev.h | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | #ifndef __ASM_MACH_CLKDEV_H | ||
| 2 | #define __ASM_MACH_CLKDEV_H | ||
| 3 | |||
| 4 | #define __clk_get(clk) ({ 1; }) | ||
| 5 | #define __clk_put(clk) do { } while (0) | ||
| 6 | |||
| 7 | #endif /* __ASM_MACH_CLKDEV_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/cputype.h b/arch/arm/mach-mmp/include/mach/cputype.h new file mode 100644 index 000000000000..25e797b09083 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/cputype.h | |||
| @@ -0,0 +1,30 @@ | |||
| 1 | #ifndef __ASM_MACH_CPUTYPE_H | ||
| 2 | #define __ASM_MACH_CPUTYPE_H | ||
| 3 | |||
| 4 | #include <asm/cputype.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * CPU Stepping OLD_ID CPU_ID CHIP_ID | ||
| 8 | * | ||
| 9 | * PXA168 A0 0x41159263 0x56158400 0x00A0A333 | ||
| 10 | * PXA910 Y0 0x41159262 0x56158000 0x00F0C910 | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifdef CONFIG_CPU_PXA168 | ||
| 14 | # define __cpu_is_pxa168(id) \ | ||
| 15 | ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x84; }) | ||
| 16 | #else | ||
| 17 | # define __cpu_is_pxa168(id) (0) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #ifdef CONFIG_CPU_PXA910 | ||
| 21 | # define __cpu_is_pxa910(id) \ | ||
| 22 | ({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x80; }) | ||
| 23 | #else | ||
| 24 | # define __cpu_is_pxa910(id) (0) | ||
| 25 | #endif | ||
| 26 | |||
| 27 | #define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); }) | ||
| 28 | #define cpu_is_pxa910() ({ __cpu_is_pxa910(read_cpuid_id()); }) | ||
| 29 | |||
| 30 | #endif /* __ASM_MACH_CPUTYPE_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S new file mode 100644 index 000000000000..a850f87de51d --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/debug-macro.S | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | /* arch/arm/mach-mmp/include/mach/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copied from arch/arm/mach-pxa/include/mach/debug.S | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #include <mach/addr-map.h> | ||
| 13 | |||
| 14 | .macro addruart,rx | ||
| 15 | mrc p15, 0, \rx, c1, c0 | ||
| 16 | tst \rx, #1 @ MMU enabled? | ||
| 17 | ldreq \rx, =APB_PHYS_BASE @ physical | ||
| 18 | ldrne \rx, =APB_VIRT_BASE @ virtual | ||
| 19 | orr \rx, \rx, #0x00017000 | ||
| 20 | .endm | ||
| 21 | |||
| 22 | #define UART_SHIFT 2 | ||
| 23 | #include <asm/hardware/debug-8250.S> | ||
diff --git a/arch/arm/mach-mmp/include/mach/devices.h b/arch/arm/mach-mmp/include/mach/devices.h new file mode 100644 index 000000000000..24585397217e --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/devices.h | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | #include <linux/types.h> | ||
| 2 | |||
| 3 | #define MAX_RESOURCE_DMA 2 | ||
| 4 | |||
| 5 | /* structure for describing the on-chip devices */ | ||
| 6 | struct pxa_device_desc { | ||
| 7 | const char *dev_name; | ||
| 8 | const char *drv_name; | ||
| 9 | int id; | ||
| 10 | int irq; | ||
| 11 | unsigned long start; | ||
| 12 | unsigned long size; | ||
| 13 | int dma[MAX_RESOURCE_DMA]; | ||
| 14 | }; | ||
| 15 | |||
| 16 | #define PXA168_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \ | ||
| 17 | struct pxa_device_desc pxa168_device_##_name __initdata = { \ | ||
| 18 | .dev_name = "pxa168-" #_name, \ | ||
| 19 | .drv_name = _drv, \ | ||
| 20 | .id = _id, \ | ||
| 21 | .irq = IRQ_PXA168_##_irq, \ | ||
| 22 | .start = _start, \ | ||
| 23 | .size = _size, \ | ||
| 24 | .dma = { _dma }, \ | ||
| 25 | }; | ||
| 26 | |||
| 27 | #define PXA910_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \ | ||
| 28 | struct pxa_device_desc pxa910_device_##_name __initdata = { \ | ||
| 29 | .dev_name = "pxa910-" #_name, \ | ||
| 30 | .drv_name = _drv, \ | ||
| 31 | .id = _id, \ | ||
| 32 | .irq = IRQ_PXA910_##_irq, \ | ||
| 33 | .start = _start, \ | ||
| 34 | .size = _size, \ | ||
| 35 | .dma = { _dma }, \ | ||
| 36 | }; | ||
| 37 | extern int pxa_register_device(struct pxa_device_desc *, void *, size_t); | ||
diff --git a/arch/arm/mach-mmp/include/mach/dma.h b/arch/arm/mach-mmp/include/mach/dma.h new file mode 100644 index 000000000000..1d6914544da4 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/dma.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/dma.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #ifndef __ASM_MACH_DMA_H | ||
| 6 | #define __ASM_MACH_DMA_H | ||
| 7 | |||
| 8 | #include <mach/addr-map.h> | ||
| 9 | |||
| 10 | #define DMAC_REGS_VIRT (APB_VIRT_BASE + 0x00000) | ||
| 11 | |||
| 12 | #include <plat/dma.h> | ||
| 13 | #endif /* __ASM_MACH_DMA_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S new file mode 100644 index 000000000000..6d3cd35478b5 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/entry-macro.S | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/entry-macro.S | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <mach/regs-icu.h> | ||
| 10 | |||
| 11 | .macro disable_fiq | ||
| 12 | .endm | ||
| 13 | |||
| 14 | .macro arch_ret_to_user, tmp1, tmp2 | ||
| 15 | .endm | ||
| 16 | |||
| 17 | .macro get_irqnr_preamble, base, tmp | ||
| 18 | ldr \base, =ICU_AP_IRQ_SEL_INT_NUM | ||
| 19 | .endm | ||
| 20 | |||
| 21 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 22 | ldr \tmp, [\base, #0] | ||
| 23 | and \irqnr, \tmp, #0x3f | ||
| 24 | tst \tmp, #(1 << 6) | ||
| 25 | .endm | ||
diff --git a/arch/arm/mach-mmp/include/mach/gpio.h b/arch/arm/mach-mmp/include/mach/gpio.h new file mode 100644 index 000000000000..ab26d13295c4 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/gpio.h | |||
| @@ -0,0 +1,36 @@ | |||
| 1 | #ifndef __ASM_MACH_GPIO_H | ||
| 2 | #define __ASM_MACH_GPIO_H | ||
| 3 | |||
| 4 | #include <mach/addr-map.h> | ||
| 5 | #include <mach/irqs.h> | ||
| 6 | #include <asm-generic/gpio.h> | ||
| 7 | |||
| 8 | #define GPIO_REGS_VIRT (APB_VIRT_BASE + 0x19000) | ||
| 9 | |||
| 10 | #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) | ||
| 11 | #define GPIO_REG(x) (*((volatile u32 *)(GPIO_REGS_VIRT + (x)))) | ||
| 12 | |||
| 13 | #define NR_BUILTIN_GPIO (128) | ||
| 14 | |||
| 15 | #define gpio_to_bank(gpio) ((gpio) >> 5) | ||
| 16 | #define gpio_to_irq(gpio) (IRQ_GPIO_START + (gpio)) | ||
| 17 | #define irq_to_gpio(irq) ((irq) - IRQ_GPIO_START) | ||
| 18 | |||
| 19 | |||
| 20 | #define __gpio_is_inverted(gpio) (0) | ||
| 21 | #define __gpio_is_occupied(gpio) (0) | ||
| 22 | |||
| 23 | /* NOTE: these macros are defined here to make optimization of | ||
| 24 | * gpio_{get,set}_value() to work when 'gpio' is a constant. | ||
| 25 | * Usage of these macros otherwise is no longer recommended, | ||
| 26 | * use generic GPIO API whenever possible. | ||
| 27 | */ | ||
| 28 | #define GPIO_bit(gpio) (1 << ((gpio) & 0x1f)) | ||
| 29 | |||
| 30 | #define GPLR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x00) | ||
| 31 | #define GPDR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x0c) | ||
| 32 | #define GPSR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x18) | ||
| 33 | #define GPCR(x) GPIO_REG(BANK_OFF(gpio_to_bank(x)) + 0x24) | ||
| 34 | |||
| 35 | #include <plat/gpio.h> | ||
| 36 | #endif /* __ASM_MACH_GPIO_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/hardware.h b/arch/arm/mach-mmp/include/mach/hardware.h new file mode 100644 index 000000000000..99264a5ce5e4 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/hardware.h | |||
| @@ -0,0 +1,4 @@ | |||
| 1 | #ifndef __ASM_MACH_HARDWARE_H | ||
| 2 | #define __ASM_MACH_HARDWARE_H | ||
| 3 | |||
| 4 | #endif /* __ASM_MACH_HARDWARE_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/io.h b/arch/arm/mach-mmp/include/mach/io.h new file mode 100644 index 000000000000..e7adf3d012c1 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/io.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/io.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_MACH_IO_H | ||
| 10 | #define __ASM_MACH_IO_H | ||
| 11 | |||
| 12 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 13 | |||
| 14 | /* | ||
| 15 | * We don't actually have real ISA nor PCI buses, but there is so many | ||
| 16 | * drivers out there that might just work if we fake them... | ||
| 17 | */ | ||
| 18 | #define __io(a) __typesafe_io(a) | ||
| 19 | #define __mem_pci(a) (a) | ||
| 20 | |||
| 21 | #endif /* __ASM_MACH_IO_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/irqs.h b/arch/arm/mach-mmp/include/mach/irqs.h new file mode 100644 index 000000000000..e83e45ebf7a4 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/irqs.h | |||
| @@ -0,0 +1,119 @@ | |||
| 1 | #ifndef __ASM_MACH_IRQS_H | ||
| 2 | #define __ASM_MACH_IRQS_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Interrupt numbers for PXA168 | ||
| 6 | */ | ||
| 7 | #define IRQ_PXA168_NONE (-1) | ||
| 8 | #define IRQ_PXA168_SSP3 0 | ||
| 9 | #define IRQ_PXA168_SSP2 1 | ||
| 10 | #define IRQ_PXA168_SSP1 2 | ||
| 11 | #define IRQ_PXA168_SSP0 3 | ||
| 12 | #define IRQ_PXA168_PMIC_INT 4 | ||
| 13 | #define IRQ_PXA168_RTC_INT 5 | ||
| 14 | #define IRQ_PXA168_RTC_ALARM 6 | ||
| 15 | #define IRQ_PXA168_TWSI0 7 | ||
| 16 | #define IRQ_PXA168_GPU 8 | ||
| 17 | #define IRQ_PXA168_KEYPAD 9 | ||
| 18 | #define IRQ_PXA168_ONEWIRE 12 | ||
| 19 | #define IRQ_PXA168_TIMER1 13 | ||
| 20 | #define IRQ_PXA168_TIMER2 14 | ||
| 21 | #define IRQ_PXA168_TIMER3 15 | ||
| 22 | #define IRQ_PXA168_CMU 16 | ||
| 23 | #define IRQ_PXA168_SSP4 17 | ||
| 24 | #define IRQ_PXA168_MSP_WAKEUP 19 | ||
| 25 | #define IRQ_PXA168_CF_WAKEUP 20 | ||
| 26 | #define IRQ_PXA168_XD_WAKEUP 21 | ||
| 27 | #define IRQ_PXA168_MFU 22 | ||
| 28 | #define IRQ_PXA168_MSP 23 | ||
| 29 | #define IRQ_PXA168_CF 24 | ||
| 30 | #define IRQ_PXA168_XD 25 | ||
| 31 | #define IRQ_PXA168_DDR_INT 26 | ||
| 32 | #define IRQ_PXA168_UART1 27 | ||
| 33 | #define IRQ_PXA168_UART2 28 | ||
| 34 | #define IRQ_PXA168_WDT 35 | ||
| 35 | #define IRQ_PXA168_FRQ_CHANGE 38 | ||
| 36 | #define IRQ_PXA168_SDH1 39 | ||
| 37 | #define IRQ_PXA168_SDH2 40 | ||
| 38 | #define IRQ_PXA168_LCD 41 | ||
| 39 | #define IRQ_PXA168_CI 42 | ||
| 40 | #define IRQ_PXA168_USB1 44 | ||
| 41 | #define IRQ_PXA168_NAND 45 | ||
| 42 | #define IRQ_PXA168_HIFI_DMA 46 | ||
| 43 | #define IRQ_PXA168_DMA_INT0 47 | ||
| 44 | #define IRQ_PXA168_DMA_INT1 48 | ||
| 45 | #define IRQ_PXA168_GPIOX 49 | ||
| 46 | #define IRQ_PXA168_USB2 51 | ||
| 47 | #define IRQ_PXA168_AC97 57 | ||
| 48 | #define IRQ_PXA168_TWSI1 58 | ||
| 49 | #define IRQ_PXA168_PMU 60 | ||
| 50 | #define IRQ_PXA168_SM_INT 63 | ||
| 51 | |||
| 52 | /* | ||
| 53 | * Interrupt numbers for PXA910 | ||
| 54 | */ | ||
| 55 | #define IRQ_PXA910_AIRQ 0 | ||
| 56 | #define IRQ_PXA910_SSP3 1 | ||
| 57 | #define IRQ_PXA910_SSP2 2 | ||
| 58 | #define IRQ_PXA910_SSP1 3 | ||
| 59 | #define IRQ_PXA910_PMIC_INT 4 | ||
| 60 | #define IRQ_PXA910_RTC_INT 5 | ||
| 61 | #define IRQ_PXA910_RTC_ALARM 6 | ||
| 62 | #define IRQ_PXA910_TWSI0 7 | ||
| 63 | #define IRQ_PXA910_GPU 8 | ||
| 64 | #define IRQ_PXA910_KEYPAD 9 | ||
| 65 | #define IRQ_PXA910_ROTARY 10 | ||
| 66 | #define IRQ_PXA910_TRACKBALL 11 | ||
| 67 | #define IRQ_PXA910_ONEWIRE 12 | ||
| 68 | #define IRQ_PXA910_AP1_TIMER1 13 | ||
| 69 | #define IRQ_PXA910_AP1_TIMER2 14 | ||
| 70 | #define IRQ_PXA910_AP1_TIMER3 15 | ||
| 71 | #define IRQ_PXA910_IPC_AP0 16 | ||
| 72 | #define IRQ_PXA910_IPC_AP1 17 | ||
| 73 | #define IRQ_PXA910_IPC_AP2 18 | ||
| 74 | #define IRQ_PXA910_IPC_AP3 19 | ||
| 75 | #define IRQ_PXA910_IPC_AP4 20 | ||
| 76 | #define IRQ_PXA910_IPC_CP0 21 | ||
| 77 | #define IRQ_PXA910_IPC_CP1 22 | ||
| 78 | #define IRQ_PXA910_IPC_CP2 23 | ||
| 79 | #define IRQ_PXA910_IPC_CP3 24 | ||
| 80 | #define IRQ_PXA910_IPC_CP4 25 | ||
| 81 | #define IRQ_PXA910_L2_DDR 26 | ||
| 82 | #define IRQ_PXA910_UART2 27 | ||
| 83 | #define IRQ_PXA910_UART3 28 | ||
| 84 | #define IRQ_PXA910_AP2_TIMER1 29 | ||
| 85 | #define IRQ_PXA910_AP2_TIMER2 30 | ||
| 86 | #define IRQ_PXA910_CP2_TIMER1 31 | ||
| 87 | #define IRQ_PXA910_CP2_TIMER2 32 | ||
| 88 | #define IRQ_PXA910_CP2_TIMER3 33 | ||
| 89 | #define IRQ_PXA910_GSSP 34 | ||
| 90 | #define IRQ_PXA910_CP2_WDT 35 | ||
| 91 | #define IRQ_PXA910_MAIN_PMU 36 | ||
| 92 | #define IRQ_PXA910_CP_FREQ_CHG 37 | ||
| 93 | #define IRQ_PXA910_AP_FREQ_CHG 38 | ||
| 94 | #define IRQ_PXA910_MMC 39 | ||
| 95 | #define IRQ_PXA910_AEU 40 | ||
| 96 | #define IRQ_PXA910_LCD 41 | ||
| 97 | #define IRQ_PXA910_CCIC 42 | ||
| 98 | #define IRQ_PXA910_IRE 43 | ||
| 99 | #define IRQ_PXA910_USB1 44 | ||
| 100 | #define IRQ_PXA910_NAND 45 | ||
| 101 | #define IRQ_PXA910_HIFI_DMA 46 | ||
| 102 | #define IRQ_PXA910_DMA_INT0 47 | ||
| 103 | #define IRQ_PXA910_DMA_INT1 48 | ||
| 104 | #define IRQ_PXA910_AP_GPIO 49 | ||
| 105 | #define IRQ_PXA910_AP2_TIMER3 50 | ||
| 106 | #define IRQ_PXA910_USB2 51 | ||
| 107 | #define IRQ_PXA910_TWSI1 54 | ||
| 108 | #define IRQ_PXA910_CP_GPIO 55 | ||
| 109 | #define IRQ_PXA910_UART1 59 /* Slow UART */ | ||
| 110 | #define IRQ_PXA910_AP_PMU 60 | ||
| 111 | #define IRQ_PXA910_SM_INT 63 /* from PinMux */ | ||
| 112 | |||
| 113 | #define IRQ_GPIO_START 64 | ||
| 114 | #define IRQ_GPIO_NUM 128 | ||
| 115 | #define IRQ_GPIO(x) (IRQ_GPIO_START + (x)) | ||
| 116 | |||
| 117 | #define NR_IRQS (IRQ_GPIO_START + IRQ_GPIO_NUM) | ||
| 118 | |||
| 119 | #endif /* __ASM_MACH_IRQS_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/memory.h b/arch/arm/mach-mmp/include/mach/memory.h new file mode 100644 index 000000000000..bdb21d70714c --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/memory.h | |||
| @@ -0,0 +1,14 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/memory.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_MACH_MEMORY_H | ||
| 10 | #define __ASM_MACH_MEMORY_H | ||
| 11 | |||
| 12 | #define PHYS_OFFSET UL(0x00000000) | ||
| 13 | |||
| 14 | #endif /* __ASM_MACH_MEMORY_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h new file mode 100644 index 000000000000..d0bdb6e3682b --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h | |||
| @@ -0,0 +1,258 @@ | |||
| 1 | #ifndef __ASM_MACH_MFP_PXA168_H | ||
| 2 | #define __ASM_MACH_MFP_PXA168_H | ||
| 3 | |||
| 4 | #include <mach/mfp.h> | ||
| 5 | |||
| 6 | /* GPIO */ | ||
| 7 | #define GPIO0_GPIO MFP_CFG(GPIO0, AF5) | ||
| 8 | #define GPIO1_GPIO MFP_CFG(GPIO1, AF5) | ||
| 9 | #define GPIO2_GPIO MFP_CFG(GPIO2, AF5) | ||
| 10 | #define GPIO3_GPIO MFP_CFG(GPIO3, AF5) | ||
| 11 | #define GPIO4_GPIO MFP_CFG(GPIO4, AF5) | ||
| 12 | #define GPIO5_GPIO MFP_CFG(GPIO5, AF5) | ||
| 13 | #define GPIO6_GPIO MFP_CFG(GPIO6, AF5) | ||
| 14 | #define GPIO7_GPIO MFP_CFG(GPIO7, AF5) | ||
| 15 | #define GPIO8_GPIO MFP_CFG(GPIO8, AF5) | ||
| 16 | #define GPIO9_GPIO MFP_CFG(GPIO9, AF5) | ||
| 17 | #define GPIO10_GPIO MFP_CFG(GPIO10, AF5) | ||
| 18 | #define GPIO11_GPIO MFP_CFG(GPIO11, AF5) | ||
| 19 | #define GPIO12_GPIO MFP_CFG(GPIO12, AF5) | ||
| 20 | #define GPIO13_GPIO MFP_CFG(GPIO13, AF5) | ||
| 21 | #define GPIO14_GPIO MFP_CFG(GPIO14, AF5) | ||
| 22 | #define GPIO15_GPIO MFP_CFG(GPIO15, AF5) | ||
| 23 | #define GPIO16_GPIO MFP_CFG(GPIO16, AF0) | ||
| 24 | #define GPIO17_GPIO MFP_CFG(GPIO17, AF5) | ||
| 25 | #define GPIO18_GPIO MFP_CFG(GPIO18, AF0) | ||
| 26 | #define GPIO19_GPIO MFP_CFG(GPIO19, AF5) | ||
| 27 | #define GPIO20_GPIO MFP_CFG(GPIO20, AF0) | ||
| 28 | #define GPIO21_GPIO MFP_CFG(GPIO21, AF5) | ||
| 29 | #define GPIO22_GPIO MFP_CFG(GPIO22, AF5) | ||
| 30 | #define GPIO23_GPIO MFP_CFG(GPIO23, AF5) | ||
| 31 | #define GPIO24_GPIO MFP_CFG(GPIO24, AF5) | ||
| 32 | #define GPIO25_GPIO MFP_CFG(GPIO25, AF5) | ||
| 33 | #define GPIO26_GPIO MFP_CFG(GPIO26, AF0) | ||
| 34 | #define GPIO27_GPIO MFP_CFG(GPIO27, AF5) | ||
| 35 | #define GPIO28_GPIO MFP_CFG(GPIO28, AF5) | ||
| 36 | #define GPIO29_GPIO MFP_CFG(GPIO29, AF5) | ||
| 37 | #define GPIO30_GPIO MFP_CFG(GPIO30, AF5) | ||
| 38 | #define GPIO31_GPIO MFP_CFG(GPIO31, AF5) | ||
| 39 | #define GPIO32_GPIO MFP_CFG(GPIO32, AF5) | ||
| 40 | #define GPIO33_GPIO MFP_CFG(GPIO33, AF5) | ||
| 41 | #define GPIO34_GPIO MFP_CFG(GPIO34, AF0) | ||
| 42 | #define GPIO35_GPIO MFP_CFG(GPIO35, AF0) | ||
| 43 | #define GPIO36_GPIO MFP_CFG(GPIO36, AF0) | ||
| 44 | #define GPIO37_GPIO MFP_CFG(GPIO37, AF0) | ||
| 45 | #define GPIO38_GPIO MFP_CFG(GPIO38, AF0) | ||
| 46 | #define GPIO39_GPIO MFP_CFG(GPIO39, AF0) | ||
| 47 | #define GPIO40_GPIO MFP_CFG(GPIO40, AF0) | ||
| 48 | #define GPIO41_GPIO MFP_CFG(GPIO41, AF0) | ||
| 49 | #define GPIO42_GPIO MFP_CFG(GPIO42, AF0) | ||
| 50 | #define GPIO43_GPIO MFP_CFG(GPIO43, AF0) | ||
| 51 | #define GPIO44_GPIO MFP_CFG(GPIO44, AF0) | ||
| 52 | #define GPIO45_GPIO MFP_CFG(GPIO45, AF0) | ||
| 53 | #define GPIO46_GPIO MFP_CFG(GPIO46, AF0) | ||
| 54 | #define GPIO47_GPIO MFP_CFG(GPIO47, AF0) | ||
| 55 | #define GPIO48_GPIO MFP_CFG(GPIO48, AF0) | ||
| 56 | #define GPIO49_GPIO MFP_CFG(GPIO49, AF0) | ||
| 57 | #define GPIO50_GPIO MFP_CFG(GPIO50, AF0) | ||
| 58 | #define GPIO51_GPIO MFP_CFG(GPIO51, AF0) | ||
| 59 | #define GPIO52_GPIO MFP_CFG(GPIO52, AF0) | ||
| 60 | #define GPIO53_GPIO MFP_CFG(GPIO53, AF0) | ||
| 61 | #define GPIO54_GPIO MFP_CFG(GPIO54, AF0) | ||
| 62 | #define GPIO55_GPIO MFP_CFG(GPIO55, AF0) | ||
| 63 | #define GPIO56_GPIO MFP_CFG(GPIO56, AF0) | ||
| 64 | #define GPIO57_GPIO MFP_CFG(GPIO57, AF0) | ||
| 65 | #define GPIO58_GPIO MFP_CFG(GPIO58, AF0) | ||
| 66 | #define GPIO59_GPIO MFP_CFG(GPIO59, AF0) | ||
| 67 | #define GPIO60_GPIO MFP_CFG(GPIO60, AF0) | ||
| 68 | #define GPIO61_GPIO MFP_CFG(GPIO61, AF0) | ||
| 69 | #define GPIO62_GPIO MFP_CFG(GPIO62, AF0) | ||
| 70 | #define GPIO63_GPIO MFP_CFG(GPIO63, AF0) | ||
| 71 | #define GPIO64_GPIO MFP_CFG(GPIO64, AF0) | ||
| 72 | #define GPIO65_GPIO MFP_CFG(GPIO65, AF0) | ||
| 73 | #define GPIO66_GPIO MFP_CFG(GPIO66, AF0) | ||
| 74 | #define GPIO67_GPIO MFP_CFG(GPIO67, AF0) | ||
| 75 | #define GPIO68_GPIO MFP_CFG(GPIO68, AF0) | ||
| 76 | #define GPIO69_GPIO MFP_CFG(GPIO69, AF0) | ||
| 77 | #define GPIO70_GPIO MFP_CFG(GPIO70, AF0) | ||
| 78 | #define GPIO71_GPIO MFP_CFG(GPIO71, AF0) | ||
| 79 | #define GPIO72_GPIO MFP_CFG(GPIO72, AF0) | ||
| 80 | #define GPIO73_GPIO MFP_CFG(GPIO73, AF0) | ||
| 81 | #define GPIO74_GPIO MFP_CFG(GPIO74, AF0) | ||
| 82 | #define GPIO75_GPIO MFP_CFG(GPIO75, AF0) | ||
| 83 | #define GPIO76_GPIO MFP_CFG(GPIO76, AF0) | ||
| 84 | #define GPIO77_GPIO MFP_CFG(GPIO77, AF0) | ||
| 85 | #define GPIO78_GPIO MFP_CFG(GPIO78, AF0) | ||
| 86 | #define GPIO79_GPIO MFP_CFG(GPIO79, AF0) | ||
| 87 | #define GPIO80_GPIO MFP_CFG(GPIO80, AF0) | ||
| 88 | #define GPIO81_GPIO MFP_CFG(GPIO81, AF0) | ||
| 89 | #define GPIO82_GPIO MFP_CFG(GPIO82, AF0) | ||
| 90 | #define GPIO83_GPIO MFP_CFG(GPIO83, AF0) | ||
| 91 | #define GPIO84_GPIO MFP_CFG(GPIO84, AF0) | ||
| 92 | #define GPIO85_GPIO MFP_CFG(GPIO85, AF0) | ||
| 93 | #define GPIO86_GPIO MFP_CFG(GPIO86, AF0) | ||
| 94 | #define GPIO87_GPIO MFP_CFG(GPIO87, AF0) | ||
| 95 | #define GPIO88_GPIO MFP_CFG(GPIO88, AF0) | ||
| 96 | #define GPIO89_GPIO MFP_CFG(GPIO89, AF0) | ||
| 97 | #define GPIO90_GPIO MFP_CFG(GPIO90, AF0) | ||
| 98 | #define GPIO91_GPIO MFP_CFG(GPIO91, AF0) | ||
| 99 | #define GPIO92_GPIO MFP_CFG(GPIO92, AF0) | ||
| 100 | #define GPIO93_GPIO MFP_CFG(GPIO93, AF0) | ||
| 101 | #define GPIO94_GPIO MFP_CFG(GPIO94, AF0) | ||
| 102 | #define GPIO95_GPIO MFP_CFG(GPIO95, AF0) | ||
| 103 | #define GPIO96_GPIO MFP_CFG(GPIO96, AF0) | ||
| 104 | #define GPIO97_GPIO MFP_CFG(GPIO97, AF0) | ||
| 105 | #define GPIO98_GPIO MFP_CFG(GPIO98, AF0) | ||
| 106 | #define GPIO99_GPIO MFP_CFG(GPIO99, AF0) | ||
| 107 | #define GPIO100_GPIO MFP_CFG(GPIO100, AF0) | ||
| 108 | #define GPIO101_GPIO MFP_CFG(GPIO101, AF0) | ||
| 109 | #define GPIO102_GPIO MFP_CFG(GPIO102, AF0) | ||
| 110 | #define GPIO103_GPIO MFP_CFG(GPIO103, AF0) | ||
| 111 | #define GPIO104_GPIO MFP_CFG(GPIO104, AF0) | ||
| 112 | #define GPIO105_GPIO MFP_CFG(GPIO105, AF0) | ||
| 113 | #define GPIO106_GPIO MFP_CFG(GPIO106, AF0) | ||
| 114 | #define GPIO107_GPIO MFP_CFG(GPIO107, AF0) | ||
| 115 | #define GPIO108_GPIO MFP_CFG(GPIO108, AF0) | ||
| 116 | #define GPIO109_GPIO MFP_CFG(GPIO109, AF0) | ||
| 117 | #define GPIO110_GPIO MFP_CFG(GPIO110, AF0) | ||
| 118 | #define GPIO111_GPIO MFP_CFG(GPIO111, AF0) | ||
| 119 | #define GPIO112_GPIO MFP_CFG(GPIO112, AF0) | ||
| 120 | #define GPIO113_GPIO MFP_CFG(GPIO113, AF0) | ||
| 121 | #define GPIO114_GPIO MFP_CFG(GPIO114, AF0) | ||
| 122 | #define GPIO115_GPIO MFP_CFG(GPIO115, AF0) | ||
| 123 | #define GPIO116_GPIO MFP_CFG(GPIO116, AF0) | ||
| 124 | #define GPIO117_GPIO MFP_CFG(GPIO117, AF0) | ||
| 125 | #define GPIO118_GPIO MFP_CFG(GPIO118, AF0) | ||
| 126 | #define GPIO119_GPIO MFP_CFG(GPIO119, AF0) | ||
| 127 | #define GPIO120_GPIO MFP_CFG(GPIO120, AF0) | ||
| 128 | #define GPIO121_GPIO MFP_CFG(GPIO121, AF0) | ||
| 129 | #define GPIO122_GPIO MFP_CFG(GPIO122, AF0) | ||
| 130 | |||
| 131 | /* DFI */ | ||
| 132 | #define GPIO0_DFI_D15 MFP_CFG(GPIO0, AF0) | ||
| 133 | #define GPIO1_DFI_D14 MFP_CFG(GPIO1, AF0) | ||
| 134 | #define GPIO2_DFI_D13 MFP_CFG(GPIO2, AF0) | ||
| 135 | #define GPIO3_DFI_D12 MFP_CFG(GPIO3, AF0) | ||
| 136 | #define GPIO4_DFI_D11 MFP_CFG(GPIO4, AF0) | ||
| 137 | #define GPIO5_DFI_D10 MFP_CFG(GPIO5, AF0) | ||
| 138 | #define GPIO6_DFI_D9 MFP_CFG(GPIO6, AF0) | ||
| 139 | #define GPIO7_DFI_D8 MFP_CFG(GPIO7, AF0) | ||
| 140 | #define GPIO8_DFI_D7 MFP_CFG(GPIO8, AF0) | ||
| 141 | #define GPIO9_DFI_D6 MFP_CFG(GPIO9, AF0) | ||
| 142 | #define GPIO10_DFI_D5 MFP_CFG(GPIO10, AF0) | ||
| 143 | #define GPIO11_DFI_D4 MFP_CFG(GPIO11, AF0) | ||
| 144 | #define GPIO12_DFI_D3 MFP_CFG(GPIO12, AF0) | ||
| 145 | #define GPIO13_DFI_D2 MFP_CFG(GPIO13, AF0) | ||
| 146 | #define GPIO14_DFI_D1 MFP_CFG(GPIO14, AF0) | ||
| 147 | #define GPIO15_DFI_D0 MFP_CFG(GPIO15, AF0) | ||
| 148 | |||
| 149 | #define GPIO30_DFI_ADDR0 MFP_CFG(GPIO30, AF0) | ||
| 150 | #define GPIO31_DFI_ADDR1 MFP_CFG(GPIO31, AF0) | ||
| 151 | #define GPIO32_DFI_ADDR2 MFP_CFG(GPIO32, AF0) | ||
| 152 | #define GPIO33_DFI_ADDR3 MFP_CFG(GPIO33, AF0) | ||
| 153 | |||
| 154 | /* NAND */ | ||
| 155 | #define GPIO16_ND_nCS0 MFP_CFG(GPIO16, AF1) | ||
| 156 | #define GPIO17_ND_nWE MFP_CFG(GPIO17, AF0) | ||
| 157 | #define GPIO21_ND_ALE MFP_CFG(GPIO21, AF0) | ||
| 158 | #define GPIO22_ND_CLE MFP_CFG(GPIO22, AF0) | ||
| 159 | #define GPIO24_ND_nRE MFP_CFG(GPIO24, AF0) | ||
| 160 | #define GPIO26_ND_RnB1 MFP_CFG(GPIO26, AF1) | ||
| 161 | #define GPIO27_ND_RnB2 MFP_CFG(GPIO27, AF1) | ||
| 162 | |||
| 163 | /* Static Memory Controller */ | ||
| 164 | #define GPIO18_SMC_nCS0 MFP_CFG(GPIO18, AF3) | ||
| 165 | #define GPIO18_SMC_nCS1 MFP_CFG(GPIO18, AF2) | ||
| 166 | #define GPIO16_SMC_nCS0 MFP_CFG(GPIO16, AF2) | ||
| 167 | #define GPIO16_SMC_nCS1 MFP_CFG(GPIO16, AF3) | ||
| 168 | #define GPIO19_SMC_nCS0 MFP_CFG(GPIO19, AF0) | ||
| 169 | #define GPIO20_SMC_nCS1 MFP_CFG(GPIO20, AF2) | ||
| 170 | #define GPIO23_SMC_nLUA MFP_CFG(GPIO23, AF0) | ||
| 171 | #define GPIO25_SMC_nLLA MFP_CFG(GPIO25, AF0) | ||
| 172 | #define GPIO27_SMC_IRQ MFP_CFG(GPIO27, AF0) | ||
| 173 | #define GPIO28_SMC_RDY MFP_CFG(GPIO28, AF0) | ||
| 174 | #define GPIO29_SMC_SCLK MFP_CFG(GPIO29, AF0) | ||
| 175 | #define GPIO34_SMC_nCS1 MFP_CFG(GPIO34, AF2) | ||
| 176 | #define GPIO35_SMC_BE1 MFP_CFG(GPIO35, AF2) | ||
| 177 | #define GPIO36_SMC_BE2 MFP_CFG(GPIO36, AF2) | ||
| 178 | |||
| 179 | /* Compact Flash */ | ||
| 180 | #define GPIO19_CF_nCE1 MFP_CFG(GPIO19, AF3) | ||
| 181 | #define GPIO20_CF_nCE2 MFP_CFG(GPIO20, AF3) | ||
| 182 | #define GPIO23_CF_nALE MFP_CFG(GPIO23, AF3) | ||
| 183 | #define GPIO25_CF_nRESET MFP_CFG(GPIO25, AF3) | ||
| 184 | #define GPIO28_CF_RDY MFP_CFG(GPIO28, AF3) | ||
| 185 | #define GPIO29_CF_STSCH MFP_CFG(GPIO29, AF3) | ||
| 186 | #define GPIO30_CF_nREG MFP_CFG(GPIO30, AF3) | ||
| 187 | #define GPIO31_CF_nIOIS16 MFP_CFG(GPIO31, AF3) | ||
| 188 | #define GPIO32_CF_nCD1 MFP_CFG(GPIO32, AF3) | ||
| 189 | #define GPIO33_CF_nCD2 MFP_CFG(GPIO33, AF3) | ||
| 190 | |||
| 191 | /* UART1 */ | ||
| 192 | #define GPIO107_UART1_TXD MFP_CFG_DRV(GPIO107, AF1, FAST) | ||
| 193 | #define GPIO107_UART1_RXD MFP_CFG_DRV(GPIO107, AF2, FAST) | ||
| 194 | #define GPIO108_UART1_RXD MFP_CFG_DRV(GPIO108, AF1, FAST) | ||
| 195 | #define GPIO108_UART1_TXD MFP_CFG_DRV(GPIO108, AF2, FAST) | ||
| 196 | #define GPIO109_UART1_CTS MFP_CFG(GPIO109, AF1) | ||
| 197 | #define GPIO109_UART1_RTS MFP_CFG(GPIO109, AF2) | ||
| 198 | #define GPIO110_UART1_RTS MFP_CFG(GPIO110, AF1) | ||
| 199 | #define GPIO110_UART1_CTS MFP_CFG(GPIO110, AF2) | ||
| 200 | #define GPIO111_UART1_RI MFP_CFG(GPIO111, AF1) | ||
| 201 | #define GPIO111_UART1_DSR MFP_CFG(GPIO111, AF2) | ||
| 202 | #define GPIO112_UART1_DTR MFP_CFG(GPIO111, AF1) | ||
| 203 | #define GPIO112_UART1_DCD MFP_CFG(GPIO112, AF2) | ||
| 204 | |||
| 205 | /* MMC1 */ | ||
| 206 | #define GPIO37_MMC1_DAT7 MFP_CFG(GPIO37, AF1) | ||
| 207 | #define GPIO38_MMC1_DAT6 MFP_CFG(GPIO38, AF1) | ||
| 208 | #define GPIO54_MMC1_DAT5 MFP_CFG(GPIO54, AF1) | ||
| 209 | #define GPIO48_MMC1_DAT4 MFP_CFG(GPIO48, AF1) | ||
| 210 | #define GPIO51_MMC1_DAT3 MFP_CFG(GPIO51, AF1) | ||
| 211 | #define GPIO52_MMC1_DAT2 MFP_CFG(GPIO52, AF1) | ||
| 212 | #define GPIO40_MMC1_DAT1 MFP_CFG(GPIO40, AF1) | ||
| 213 | #define GPIO41_MMC1_DAT0 MFP_CFG(GPIO41, AF1) | ||
| 214 | #define GPIO49_MMC1_CMD MFP_CFG(GPIO49, AF1) | ||
| 215 | #define GPIO43_MMC1_CLK MFP_CFG(GPIO43, AF1) | ||
| 216 | #define GPIO53_MMC1_CD MFP_CFG(GPIO53, AF1) | ||
| 217 | #define GPIO46_MMC1_WP MFP_CFG(GPIO46, AF1) | ||
| 218 | |||
| 219 | /* LCD */ | ||
| 220 | #define GPIO84_LCD_CS MFP_CFG(GPIO84, AF1) | ||
| 221 | #define GPIO60_LCD_DD0 MFP_CFG(GPIO60, AF1) | ||
| 222 | #define GPIO61_LCD_DD1 MFP_CFG(GPIO61, AF1) | ||
| 223 | #define GPIO70_LCD_DD10 MFP_CFG(GPIO70, AF1) | ||
| 224 | #define GPIO71_LCD_DD11 MFP_CFG(GPIO71, AF1) | ||
| 225 | #define GPIO72_LCD_DD12 MFP_CFG(GPIO72, AF1) | ||
| 226 | #define GPIO73_LCD_DD13 MFP_CFG(GPIO73, AF1) | ||
| 227 | #define GPIO74_LCD_DD14 MFP_CFG(GPIO74, AF1) | ||
| 228 | #define GPIO75_LCD_DD15 MFP_CFG(GPIO75, AF1) | ||
| 229 | #define GPIO76_LCD_DD16 MFP_CFG(GPIO76, AF1) | ||
| 230 | #define GPIO77_LCD_DD17 MFP_CFG(GPIO77, AF1) | ||
| 231 | #define GPIO78_LCD_DD18 MFP_CFG(GPIO78, AF1) | ||
| 232 | #define GPIO79_LCD_DD19 MFP_CFG(GPIO79, AF1) | ||
| 233 | #define GPIO62_LCD_DD2 MFP_CFG(GPIO62, AF1) | ||
| 234 | #define GPIO80_LCD_DD20 MFP_CFG(GPIO80, AF1) | ||
| 235 | #define GPIO81_LCD_DD21 MFP_CFG(GPIO81, AF1) | ||
| 236 | #define GPIO82_LCD_DD22 MFP_CFG(GPIO82, AF1) | ||
| 237 | #define GPIO83_LCD_DD23 MFP_CFG(GPIO83, AF1) | ||
| 238 | #define GPIO63_LCD_DD3 MFP_CFG(GPIO63, AF1) | ||
| 239 | #define GPIO64_LCD_DD4 MFP_CFG(GPIO64, AF1) | ||
| 240 | #define GPIO65_LCD_DD5 MFP_CFG(GPIO65, AF1) | ||
| 241 | #define GPIO66_LCD_DD6 MFP_CFG(GPIO66, AF1) | ||
| 242 | #define GPIO67_LCD_DD7 MFP_CFG(GPIO67, AF1) | ||
| 243 | #define GPIO68_LCD_DD8 MFP_CFG(GPIO68, AF1) | ||
| 244 | #define GPIO69_LCD_DD9 MFP_CFG(GPIO69, AF1) | ||
| 245 | #define GPIO59_LCD_DENA_BIAS MFP_CFG(GPIO59, AF1) | ||
| 246 | #define GPIO56_LCD_FCLK_RD MFP_CFG(GPIO56, AF1) | ||
| 247 | #define GPIO57_LCD_LCLK_A0 MFP_CFG(GPIO57, AF1) | ||
| 248 | #define GPIO58_LCD_PCLK_WR MFP_CFG(GPIO58, AF1) | ||
| 249 | #define GPIO85_LCD_VSYNC MFP_CFG(GPIO85, AF1) | ||
| 250 | |||
| 251 | /* I2S */ | ||
| 252 | #define GPIO113_I2S_MCLK MFP_CFG(GPIO113,AF6) | ||
| 253 | #define GPIO114_I2S_FRM MFP_CFG(GPIO114,AF1) | ||
| 254 | #define GPIO115_I2S_BCLK MFP_CFG(GPIO115,AF1) | ||
| 255 | #define GPIO116_I2S_RXD MFP_CFG(GPIO116,AF2) | ||
| 256 | #define GPIO117_I2S_TXD MFP_CFG(GPIO117,AF2) | ||
| 257 | |||
| 258 | #endif /* __ASM_MACH_MFP_PXA168_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h new file mode 100644 index 000000000000..48a1cbc7c56b --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h | |||
| @@ -0,0 +1,157 @@ | |||
| 1 | #ifndef __ASM_MACH_MFP_PXA910_H | ||
| 2 | #define __ASM_MACH_MFP_PXA910_H | ||
| 3 | |||
| 4 | #include <mach/mfp.h> | ||
| 5 | |||
| 6 | /* UART2 */ | ||
| 7 | #define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6) | ||
| 8 | #define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF6) | ||
| 9 | |||
| 10 | /* UART3 */ | ||
| 11 | #define GPIO31_UART3_RXD MFP_CFG(GPIO31, AF4) | ||
| 12 | #define GPIO32_UART3_TXD MFP_CFG(GPIO32, AF4) | ||
| 13 | |||
| 14 | /*IRDA*/ | ||
| 15 | #define GPIO51_IRDA_SHDN MFP_CFG(GPIO51, AF0) | ||
| 16 | |||
| 17 | /* SMC */ | ||
| 18 | #define SM_nCS0_nCS0 MFP_CFG(SM_nCS0, AF0) | ||
| 19 | #define SM_ADV_SM_ADV MFP_CFG(SM_ADV, AF0) | ||
| 20 | #define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0) | ||
| 21 | #define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0) | ||
| 22 | #define SM_BE0_SM_BE0 MFP_CFG(SM_BE0, AF1) | ||
| 23 | #define SM_BE1_SM_BE1 MFP_CFG(SM_BE1, AF1) | ||
| 24 | |||
| 25 | /* I2C */ | ||
| 26 | #define GPIO53_CI2C_SCL MFP_CFG(GPIO53, AF2) | ||
| 27 | #define GPIO54_CI2C_SDA MFP_CFG(GPIO54, AF2) | ||
| 28 | |||
| 29 | /* SSP1 (I2S) */ | ||
| 30 | #define GPIO24_SSP1_SDATA_IN MFP_CFG_DRV(GPIO24, AF1, MEDIUM) | ||
| 31 | #define GPIO21_SSP1_BITCLK MFP_CFG_DRV(GPIO21, AF1, MEDIUM) | ||
| 32 | #define GPIO20_SSP1_SYSCLK MFP_CFG_DRV(GPIO20, AF1, MEDIUM) | ||
| 33 | #define GPIO22_SSP1_SYNC MFP_CFG_DRV(GPIO22, AF1, MEDIUM) | ||
| 34 | #define GPIO23_SSP1_DATA_OUT MFP_CFG_DRV(GPIO23, AF1, MEDIUM) | ||
| 35 | #define GPIO124_MN_CLK_OUT MFP_CFG_DRV(GPIO124, AF1, MEDIUM) | ||
| 36 | #define GPIO123_CLK_REQ MFP_CFG_DRV(GPIO123, AF0, MEDIUM) | ||
| 37 | |||
| 38 | /* DFI */ | ||
| 39 | #define DF_IO0_ND_IO0 MFP_CFG(DF_IO0, AF0) | ||
| 40 | #define DF_IO1_ND_IO1 MFP_CFG(DF_IO1, AF0) | ||
| 41 | #define DF_IO2_ND_IO2 MFP_CFG(DF_IO2, AF0) | ||
| 42 | #define DF_IO3_ND_IO3 MFP_CFG(DF_IO3, AF0) | ||
| 43 | #define DF_IO4_ND_IO4 MFP_CFG(DF_IO4, AF0) | ||
| 44 | #define DF_IO5_ND_IO5 MFP_CFG(DF_IO5, AF0) | ||
| 45 | #define DF_IO6_ND_IO6 MFP_CFG(DF_IO6, AF0) | ||
| 46 | #define DF_IO7_ND_IO7 MFP_CFG(DF_IO7, AF0) | ||
| 47 | #define DF_IO8_ND_IO8 MFP_CFG(DF_IO8, AF0) | ||
| 48 | #define DF_IO9_ND_IO9 MFP_CFG(DF_IO9, AF0) | ||
| 49 | #define DF_IO10_ND_IO10 MFP_CFG(DF_IO10, AF0) | ||
| 50 | #define DF_IO11_ND_IO11 MFP_CFG(DF_IO11, AF0) | ||
| 51 | #define DF_IO12_ND_IO12 MFP_CFG(DF_IO12, AF0) | ||
| 52 | #define DF_IO13_ND_IO13 MFP_CFG(DF_IO13, AF0) | ||
| 53 | #define DF_IO14_ND_IO14 MFP_CFG(DF_IO14, AF0) | ||
| 54 | #define DF_IO15_ND_IO15 MFP_CFG(DF_IO15, AF0) | ||
| 55 | #define DF_nCS0_SM_nCS2_nCS0 MFP_CFG(DF_nCS0_SM_nCS2, AF0) | ||
| 56 | #define DF_ALE_SM_WEn_ND_ALE MFP_CFG(DF_ALE_SM_WEn, AF1) | ||
| 57 | #define DF_CLE_SM_OEn_ND_CLE MFP_CFG(DF_CLE_SM_OEn, AF0) | ||
| 58 | #define DF_WEn_DF_WEn MFP_CFG(DF_WEn, AF1) | ||
| 59 | #define DF_REn_DF_REn MFP_CFG(DF_REn, AF1) | ||
| 60 | #define DF_RDY0_DF_RDY0 MFP_CFG(DF_RDY0, AF0) | ||
| 61 | |||
| 62 | /*keypad*/ | ||
| 63 | #define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1) | ||
| 64 | #define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1) | ||
| 65 | #define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1) | ||
| 66 | #define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1) | ||
| 67 | #define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1) | ||
| 68 | #define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1) | ||
| 69 | #define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1) | ||
| 70 | #define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1) | ||
| 71 | #define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1) | ||
| 72 | #define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1) | ||
| 73 | #define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1) | ||
| 74 | #define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1) | ||
| 75 | #define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1) | ||
| 76 | #define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1) | ||
| 77 | #define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1) | ||
| 78 | #define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1) | ||
| 79 | #define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1) | ||
| 80 | #define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1) | ||
| 81 | #define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1) | ||
| 82 | #define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1) | ||
| 83 | |||
| 84 | /* LCD */ | ||
| 85 | #define GPIO81_LCD_FCLK MFP_CFG(GPIO81, AF1) | ||
| 86 | #define GPIO82_LCD_LCLK MFP_CFG(GPIO82, AF1) | ||
| 87 | #define GPIO83_LCD_PCLK MFP_CFG(GPIO83, AF1) | ||
| 88 | #define GPIO84_LCD_DENA MFP_CFG(GPIO84, AF1) | ||
| 89 | #define GPIO85_LCD_DD0 MFP_CFG(GPIO85, AF1) | ||
| 90 | #define GPIO86_LCD_DD1 MFP_CFG(GPIO86, AF1) | ||
| 91 | #define GPIO87_LCD_DD2 MFP_CFG(GPIO87, AF1) | ||
| 92 | #define GPIO88_LCD_DD3 MFP_CFG(GPIO88, AF1) | ||
| 93 | #define GPIO89_LCD_DD4 MFP_CFG(GPIO89, AF1) | ||
| 94 | #define GPIO90_LCD_DD5 MFP_CFG(GPIO90, AF1) | ||
| 95 | #define GPIO91_LCD_DD6 MFP_CFG(GPIO91, AF1) | ||
| 96 | #define GPIO92_LCD_DD7 MFP_CFG(GPIO92, AF1) | ||
| 97 | #define GPIO93_LCD_DD8 MFP_CFG(GPIO93, AF1) | ||
| 98 | #define GPIO94_LCD_DD9 MFP_CFG(GPIO94, AF1) | ||
| 99 | #define GPIO95_LCD_DD10 MFP_CFG(GPIO95, AF1) | ||
| 100 | #define GPIO96_LCD_DD11 MFP_CFG(GPIO96, AF1) | ||
| 101 | #define GPIO97_LCD_DD12 MFP_CFG(GPIO97, AF1) | ||
| 102 | #define GPIO98_LCD_DD13 MFP_CFG(GPIO98, AF1) | ||
| 103 | #define GPIO100_LCD_DD14 MFP_CFG(GPIO100, AF1) | ||
| 104 | #define GPIO101_LCD_DD15 MFP_CFG(GPIO101, AF1) | ||
| 105 | #define GPIO102_LCD_DD16 MFP_CFG(GPIO102, AF1) | ||
| 106 | #define GPIO103_LCD_DD17 MFP_CFG(GPIO103, AF1) | ||
| 107 | #define GPIO104_LCD_DD18 MFP_CFG(GPIO104, AF1) | ||
| 108 | #define GPIO105_LCD_DD19 MFP_CFG(GPIO105, AF1) | ||
| 109 | #define GPIO106_LCD_DD20 MFP_CFG(GPIO106, AF1) | ||
| 110 | #define GPIO107_LCD_DD21 MFP_CFG(GPIO107, AF1) | ||
| 111 | #define GPIO108_LCD_DD22 MFP_CFG(GPIO108, AF1) | ||
| 112 | #define GPIO109_LCD_DD23 MFP_CFG(GPIO109, AF1) | ||
| 113 | |||
| 114 | #define GPIO104_LCD_SPIDOUT MFP_CFG(GPIO104, AF3) | ||
| 115 | #define GPIO105_LCD_SPIDIN MFP_CFG(GPIO105, AF3) | ||
| 116 | #define GPIO107_LCD_CS1 MFP_CFG(GPIO107, AF3) | ||
| 117 | #define GPIO108_LCD_DCLK MFP_CFG(GPIO108, AF3) | ||
| 118 | |||
| 119 | #define GPIO106_LCD_RESET MFP_CFG(GPIO106, AF0) | ||
| 120 | |||
| 121 | /*smart panel*/ | ||
| 122 | #define GPIO82_LCD_A0 MFP_CFG(GPIO82, AF0) | ||
| 123 | #define GPIO83_LCD_WR MFP_CFG(GPIO83, AF0) | ||
| 124 | #define GPIO103_LCD_CS MFP_CFG(GPIO103, AF0) | ||
| 125 | |||
| 126 | /*1wire*/ | ||
| 127 | #define GPIO106_1WIRE MFP_CFG(GPIO106, AF3) | ||
| 128 | |||
| 129 | /*CCIC*/ | ||
| 130 | #define GPIO67_CCIC_IN7 MFP_CFG_DRV(GPIO67, AF1, MEDIUM) | ||
| 131 | #define GPIO68_CCIC_IN6 MFP_CFG_DRV(GPIO68, AF1, MEDIUM) | ||
| 132 | #define GPIO69_CCIC_IN5 MFP_CFG_DRV(GPIO69, AF1, MEDIUM) | ||
| 133 | #define GPIO70_CCIC_IN4 MFP_CFG_DRV(GPIO70, AF1, MEDIUM) | ||
| 134 | #define GPIO71_CCIC_IN3 MFP_CFG_DRV(GPIO71, AF1, MEDIUM) | ||
| 135 | #define GPIO72_CCIC_IN2 MFP_CFG_DRV(GPIO72, AF1, MEDIUM) | ||
| 136 | #define GPIO73_CCIC_IN1 MFP_CFG_DRV(GPIO73, AF1, MEDIUM) | ||
| 137 | #define GPIO74_CCIC_IN0 MFP_CFG_DRV(GPIO74, AF1, MEDIUM) | ||
| 138 | #define GPIO75_CAM_HSYNC MFP_CFG_DRV(GPIO75, AF1, MEDIUM) | ||
| 139 | #define GPIO76_CAM_VSYNC MFP_CFG_DRV(GPIO76, AF1, MEDIUM) | ||
| 140 | #define GPIO77_CAM_MCLK MFP_CFG_DRV(GPIO77, AF1, MEDIUM) | ||
| 141 | #define GPIO78_CAM_PCLK MFP_CFG_DRV(GPIO78, AF1, MEDIUM) | ||
| 142 | |||
| 143 | /* MMC1 */ | ||
| 144 | #define MMC1_DAT7_MMC1_DAT7 MFP_CFG_DRV(MMC1_DAT7, AF0, MEDIUM) | ||
| 145 | #define MMC1_DAT6_MMC1_DAT6 MFP_CFG_DRV(MMC1_DAT6, AF0, MEDIUM) | ||
| 146 | #define MMC1_DAT5_MMC1_DAT5 MFP_CFG_DRV(MMC1_DAT5, AF0, MEDIUM) | ||
| 147 | #define MMC1_DAT4_MMC1_DAT4 MFP_CFG_DRV(MMC1_DAT4, AF0, MEDIUM) | ||
| 148 | #define MMC1_DAT3_MMC1_DAT3 MFP_CFG_DRV(MMC1_DAT3, AF0, MEDIUM) | ||
| 149 | #define MMC1_DAT2_MMC1_DAT2 MFP_CFG_DRV(MMC1_DAT2, AF0, MEDIUM) | ||
| 150 | #define MMC1_DAT1_MMC1_DAT1 MFP_CFG_DRV(MMC1_DAT1, AF0, MEDIUM) | ||
| 151 | #define MMC1_DAT0_MMC1_DAT0 MFP_CFG_DRV(MMC1_DAT0, AF0, MEDIUM) | ||
| 152 | #define MMC1_CMD_MMC1_CMD MFP_CFG_DRV(MMC1_CMD, AF0, MEDIUM) | ||
| 153 | #define MMC1_CLK_MMC1_CLK MFP_CFG_DRV(MMC1_CLK, AF0, MEDIUM) | ||
| 154 | #define MMC1_CD_MMC1_CD MFP_CFG_DRV(MMC1_CD, AF0, MEDIUM) | ||
| 155 | #define MMC1_WP_MMC1_WP MFP_CFG_DRV(MMC1_WP, AF0, MEDIUM) | ||
| 156 | |||
| 157 | #endif /* __ASM_MACH MFP_PXA910_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/mfp.h b/arch/arm/mach-mmp/include/mach/mfp.h new file mode 100644 index 000000000000..277ea4cd0f9f --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/mfp.h | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | #ifndef __ASM_MACH_MFP_H | ||
| 2 | #define __ASM_MACH_MFP_H | ||
| 3 | |||
| 4 | #include <plat/mfp.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * NOTE: the MFPR register bit definitions on PXA168 processor lines are a | ||
| 8 | * bit different from those on PXA3xx. Bit [7:10] are now reserved, which | ||
| 9 | * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits. | ||
| 10 | * | ||
| 11 | * To cope with this difference and re-use the pxa3xx mfp code as much as | ||
| 12 | * possible, we make the following compromise: | ||
| 13 | * | ||
| 14 | * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT) | ||
| 15 | * 2. DRIVE strength definitions redefined to include the reserved bit10 | ||
| 16 | * 3. Override MFP_CFG() and MFP_CFG_DRV() | ||
| 17 | * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X() | ||
| 18 | */ | ||
| 19 | |||
| 20 | #define MFP_DRIVE_VERY_SLOW (0x0 << 13) | ||
| 21 | #define MFP_DRIVE_SLOW (0x2 << 13) | ||
| 22 | #define MFP_DRIVE_MEDIUM (0x4 << 13) | ||
| 23 | #define MFP_DRIVE_FAST (0x8 << 13) | ||
| 24 | |||
| 25 | #undef MFP_CFG | ||
| 26 | #undef MFP_CFG_DRV | ||
| 27 | #undef MFP_CFG_LPM | ||
| 28 | #undef MFP_CFG_X | ||
| 29 | #undef MFP_CFG_DEFAULT | ||
| 30 | |||
| 31 | #define MFP_CFG(pin, af) \ | ||
| 32 | (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM) | ||
| 33 | |||
| 34 | #define MFP_CFG_DRV(pin, af, drv) \ | ||
| 35 | (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv) | ||
| 36 | |||
| 37 | #endif /* __ASM_MACH_MFP_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h new file mode 100644 index 000000000000..ef0a8a2076e9 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/pxa168.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | #ifndef __ASM_MACH_PXA168_H | ||
| 2 | #define __ASM_MACH_PXA168_H | ||
| 3 | |||
| 4 | #include <mach/devices.h> | ||
| 5 | |||
| 6 | extern struct pxa_device_desc pxa168_device_uart1; | ||
| 7 | extern struct pxa_device_desc pxa168_device_uart2; | ||
| 8 | |||
| 9 | static inline int pxa168_add_uart(int id) | ||
| 10 | { | ||
| 11 | struct pxa_device_desc *d = NULL; | ||
| 12 | |||
| 13 | switch (id) { | ||
| 14 | case 1: d = &pxa168_device_uart1; break; | ||
| 15 | case 2: d = &pxa168_device_uart2; break; | ||
| 16 | } | ||
| 17 | |||
| 18 | if (d == NULL) | ||
| 19 | return -EINVAL; | ||
| 20 | |||
| 21 | return pxa_register_device(d, NULL, 0); | ||
| 22 | } | ||
| 23 | #endif /* __ASM_MACH_PXA168_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h new file mode 100644 index 000000000000..b7aeaf574c36 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/pxa910.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | #ifndef __ASM_MACH_PXA910_H | ||
| 2 | #define __ASM_MACH_PXA910_H | ||
| 3 | |||
| 4 | #include <mach/devices.h> | ||
| 5 | |||
| 6 | extern struct pxa_device_desc pxa910_device_uart1; | ||
| 7 | extern struct pxa_device_desc pxa910_device_uart2; | ||
| 8 | |||
| 9 | static inline int pxa910_add_uart(int id) | ||
| 10 | { | ||
| 11 | struct pxa_device_desc *d = NULL; | ||
| 12 | |||
| 13 | switch (id) { | ||
| 14 | case 1: d = &pxa910_device_uart1; break; | ||
| 15 | case 2: d = &pxa910_device_uart2; break; | ||
| 16 | } | ||
| 17 | |||
| 18 | if (d == NULL) | ||
| 19 | return -EINVAL; | ||
| 20 | |||
| 21 | return pxa_register_device(d, NULL, 0); | ||
| 22 | } | ||
| 23 | #endif /* __ASM_MACH_PXA910_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h new file mode 100644 index 000000000000..c6b8c9dc2026 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h | |||
| @@ -0,0 +1,78 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/regs-apbc.h | ||
| 3 | * | ||
| 4 | * Application Peripheral Bus Clock Unit | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_MACH_REGS_APBC_H | ||
| 12 | #define __ASM_MACH_REGS_APBC_H | ||
| 13 | |||
| 14 | #include <mach/addr-map.h> | ||
| 15 | |||
| 16 | #define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000) | ||
| 17 | #define APBC_REG(x) (APBC_VIRT_BASE + (x)) | ||
| 18 | |||
| 19 | /* | ||
| 20 | * APB clock register offsets for PXA168 | ||
| 21 | */ | ||
| 22 | #define APBC_PXA168_UART1 APBC_REG(0x000) | ||
| 23 | #define APBC_PXA168_UART2 APBC_REG(0x004) | ||
| 24 | #define APBC_PXA168_GPIO APBC_REG(0x008) | ||
| 25 | #define APBC_PXA168_PWM0 APBC_REG(0x00c) | ||
| 26 | #define APBC_PXA168_PWM1 APBC_REG(0x010) | ||
| 27 | #define APBC_PXA168_SSP1 APBC_REG(0x01c) | ||
| 28 | #define APBC_PXA168_SSP2 APBC_REG(0x020) | ||
| 29 | #define APBC_PXA168_RTC APBC_REG(0x028) | ||
| 30 | #define APBC_PXA168_TWSI0 APBC_REG(0x02c) | ||
| 31 | #define APBC_PXA168_KPC APBC_REG(0x030) | ||
| 32 | #define APBC_PXA168_TIMERS APBC_REG(0x034) | ||
| 33 | #define APBC_PXA168_AIB APBC_REG(0x03c) | ||
| 34 | #define APBC_PXA168_SW_JTAG APBC_REG(0x040) | ||
| 35 | #define APBC_PXA168_ONEWIRE APBC_REG(0x048) | ||
| 36 | #define APBC_PXA168_SSP3 APBC_REG(0x04c) | ||
| 37 | #define APBC_PXA168_ASFAR APBC_REG(0x050) | ||
| 38 | #define APBC_PXA168_ASSAR APBC_REG(0x054) | ||
| 39 | #define APBC_PXA168_SSP4 APBC_REG(0x058) | ||
| 40 | #define APBC_PXA168_SSP5 APBC_REG(0x05c) | ||
| 41 | #define APBC_PXA168_TWSI1 APBC_REG(0x06c) | ||
| 42 | #define APBC_PXA168_UART3 APBC_REG(0x070) | ||
| 43 | #define APBC_PXA168_AC97 APBC_REG(0x084) | ||
| 44 | |||
| 45 | /* | ||
| 46 | * APB Clock register offsets for PXA910 | ||
| 47 | */ | ||
| 48 | #define APBC_PXA910_UART0 APBC_REG(0x000) | ||
| 49 | #define APBC_PXA910_UART1 APBC_REG(0x004) | ||
| 50 | #define APBC_PXA910_GPIO APBC_REG(0x008) | ||
| 51 | #define APBC_PXA910_PWM0 APBC_REG(0x00c) | ||
| 52 | #define APBC_PXA910_PWM1 APBC_REG(0x010) | ||
| 53 | #define APBC_PXA910_PWM2 APBC_REG(0x014) | ||
| 54 | #define APBC_PXA910_PWM3 APBC_REG(0x018) | ||
| 55 | #define APBC_PXA910_SSP1 APBC_REG(0x01c) | ||
| 56 | #define APBC_PXA910_SSP2 APBC_REG(0x020) | ||
| 57 | #define APBC_PXA910_IPC APBC_REG(0x024) | ||
| 58 | #define APBC_PXA910_TWSI0 APBC_REG(0x02c) | ||
| 59 | #define APBC_PXA910_KPC APBC_REG(0x030) | ||
| 60 | #define APBC_PXA910_TIMERS APBC_REG(0x034) | ||
| 61 | #define APBC_PXA910_TBROT APBC_REG(0x038) | ||
| 62 | #define APBC_PXA910_AIB APBC_REG(0x03c) | ||
| 63 | #define APBC_PXA910_SW_JTAG APBC_REG(0x040) | ||
| 64 | #define APBC_PXA910_TIMERS1 APBC_REG(0x044) | ||
| 65 | #define APBC_PXA910_ONEWIRE APBC_REG(0x048) | ||
| 66 | #define APBC_PXA910_SSP3 APBC_REG(0x04c) | ||
| 67 | #define APBC_PXA910_ASFAR APBC_REG(0x050) | ||
| 68 | #define APBC_PXA910_ASSAR APBC_REG(0x054) | ||
| 69 | |||
| 70 | /* Common APB clock register bit definitions */ | ||
| 71 | #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ | ||
| 72 | #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ | ||
| 73 | #define APBC_RST (1 << 2) /* Reset Generation */ | ||
| 74 | |||
| 75 | /* Functional Clock Selection Mask */ | ||
| 76 | #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) | ||
| 77 | |||
| 78 | #endif /* __ASM_MACH_REGS_APBC_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h new file mode 100644 index 000000000000..919030514120 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h | |||
| @@ -0,0 +1,36 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/regs-apmu.h | ||
| 3 | * | ||
| 4 | * Application Subsystem Power Management Unit | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_MACH_REGS_APMU_H | ||
| 12 | #define __ASM_MACH_REGS_APMU_H | ||
| 13 | |||
| 14 | #include <mach/addr-map.h> | ||
| 15 | |||
| 16 | #define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800) | ||
| 17 | #define APMU_REG(x) (APMU_VIRT_BASE + (x)) | ||
| 18 | |||
| 19 | /* Clock Reset Control */ | ||
| 20 | #define APMU_IRE APMU_REG(0x048) | ||
| 21 | #define APMU_LCD APMU_REG(0x04c) | ||
| 22 | #define APMU_CCIC APMU_REG(0x050) | ||
| 23 | #define APMU_SDH0 APMU_REG(0x054) | ||
| 24 | #define APMU_SDH1 APMU_REG(0x058) | ||
| 25 | #define APMU_USB APMU_REG(0x05c) | ||
| 26 | #define APMU_NAND APMU_REG(0x060) | ||
| 27 | #define APMU_DMA APMU_REG(0x064) | ||
| 28 | #define APMU_GEU APMU_REG(0x068) | ||
| 29 | #define APMU_BUS APMU_REG(0x06c) | ||
| 30 | |||
| 31 | #define APMU_FNCLK_EN (1 << 4) | ||
| 32 | #define APMU_AXICLK_EN (1 << 3) | ||
| 33 | #define APMU_FNRST_DIS (1 << 1) | ||
| 34 | #define APMU_AXIRST_DIS (1 << 0) | ||
| 35 | |||
| 36 | #endif /* __ASM_MACH_REGS_APMU_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/regs-icu.h b/arch/arm/mach-mmp/include/mach/regs-icu.h new file mode 100644 index 000000000000..e5f08723e0cc --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/regs-icu.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/regs-icu.h | ||
| 3 | * | ||
| 4 | * Interrupt Control Unit | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_MACH_ICU_H | ||
| 12 | #define __ASM_MACH_ICU_H | ||
| 13 | |||
| 14 | #include <mach/addr-map.h> | ||
| 15 | |||
| 16 | #define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000) | ||
| 17 | #define ICU_REG(x) (ICU_VIRT_BASE + (x)) | ||
| 18 | |||
| 19 | #define ICU_INT_CONF(n) ICU_REG((n) << 2) | ||
| 20 | #define ICU_INT_CONF_AP_INT (1 << 6) | ||
| 21 | #define ICU_INT_CONF_CP_INT (1 << 5) | ||
| 22 | #define ICU_INT_CONF_IRQ (1 << 4) | ||
| 23 | #define ICU_INT_CONF_MASK (0xf) | ||
| 24 | |||
| 25 | #define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */ | ||
| 26 | #define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */ | ||
| 27 | #define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */ | ||
| 28 | #define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */ | ||
| 29 | #define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */ | ||
| 30 | |||
| 31 | #endif /* __ASM_MACH_ICU_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/regs-timers.h b/arch/arm/mach-mmp/include/mach/regs-timers.h new file mode 100644 index 000000000000..45589fec9fc7 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/regs-timers.h | |||
| @@ -0,0 +1,44 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/regs-timers.h | ||
| 3 | * | ||
| 4 | * Timers Module | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_MACH_REGS_TIMERS_H | ||
| 12 | #define __ASM_MACH_REGS_TIMERS_H | ||
| 13 | |||
| 14 | #include <mach/addr-map.h> | ||
| 15 | |||
| 16 | #define TIMERS1_VIRT_BASE (APB_VIRT_BASE + 0x14000) | ||
| 17 | #define TIMERS2_VIRT_BASE (APB_VIRT_BASE + 0x16000) | ||
| 18 | |||
| 19 | #define TMR_CCR (0x0000) | ||
| 20 | #define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2)) | ||
| 21 | #define TMR_CR(n) (0x0028 + ((n) << 2)) | ||
| 22 | #define TMR_SR(n) (0x0034 + ((n) << 2)) | ||
| 23 | #define TMR_IER(n) (0x0040 + ((n) << 2)) | ||
| 24 | #define TMR_PLVR(n) (0x004c + ((n) << 2)) | ||
| 25 | #define TMR_PLCR(n) (0x0058 + ((n) << 2)) | ||
| 26 | #define TMR_WMER (0x0064) | ||
| 27 | #define TMR_WMR (0x0068) | ||
| 28 | #define TMR_WVR (0x006c) | ||
| 29 | #define TMR_WSR (0x0070) | ||
| 30 | #define TMR_ICR(n) (0x0074 + ((n) << 2)) | ||
| 31 | #define TMR_WICR (0x0080) | ||
| 32 | #define TMR_CER (0x0084) | ||
| 33 | #define TMR_CMR (0x0088) | ||
| 34 | #define TMR_ILR(n) (0x008c + ((n) << 2)) | ||
| 35 | #define TMR_WCR (0x0098) | ||
| 36 | #define TMR_WFAR (0x009c) | ||
| 37 | #define TMR_WSAR (0x00A0) | ||
| 38 | #define TMR_CVWR(n) (0x00A4 + ((n) << 2)) | ||
| 39 | |||
| 40 | #define TMR_CCR_CS_0(x) (((x) & 0x3) << 0) | ||
| 41 | #define TMR_CCR_CS_1(x) (((x) & 0x7) << 2) | ||
| 42 | #define TMR_CCR_CS_2(x) (((x) & 0x3) << 5) | ||
| 43 | |||
| 44 | #endif /* __ASM_MACH_REGS_TIMERS_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/system.h b/arch/arm/mach-mmp/include/mach/system.h new file mode 100644 index 000000000000..001edfefec19 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/system.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/system.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __ASM_MACH_SYSTEM_H | ||
| 10 | #define __ASM_MACH_SYSTEM_H | ||
| 11 | |||
| 12 | static inline void arch_idle(void) | ||
| 13 | { | ||
| 14 | cpu_do_idle(); | ||
| 15 | } | ||
| 16 | |||
| 17 | static inline void arch_reset(char mode) | ||
| 18 | { | ||
| 19 | cpu_reset(0); | ||
| 20 | } | ||
| 21 | #endif /* __ASM_MACH_SYSTEM_H */ | ||
diff --git a/arch/arm/mach-mmp/include/mach/timex.h b/arch/arm/mach-mmp/include/mach/timex.h new file mode 100644 index 000000000000..6cebbd0ca8f4 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/timex.h | |||
| @@ -0,0 +1,9 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/timex.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #define CLOCK_TICK_RATE 3250000 | ||
diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h new file mode 100644 index 000000000000..c93d5fa5865c --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/uncompress.h | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-mmp/include/mach/uncompress.h | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #include <linux/serial_reg.h> | ||
| 10 | #include <mach/addr-map.h> | ||
| 11 | |||
| 12 | #define UART1_BASE (APB_PHYS_BASE + 0x36000) | ||
| 13 | #define UART2_BASE (APB_PHYS_BASE + 0x17000) | ||
| 14 | #define UART3_BASE (APB_PHYS_BASE + 0x18000) | ||
| 15 | |||
| 16 | static inline void putc(char c) | ||
| 17 | { | ||
| 18 | volatile unsigned long *UART = (unsigned long *)UART2_BASE; | ||
| 19 | |||
| 20 | /* UART enabled? */ | ||
| 21 | if (!(UART[UART_IER] & UART_IER_UUE)) | ||
| 22 | return; | ||
| 23 | |||
| 24 | while (!(UART[UART_LSR] & UART_LSR_THRE)) | ||
| 25 | barrier(); | ||
| 26 | |||
| 27 | UART[UART_TX] = c; | ||
| 28 | } | ||
| 29 | |||
| 30 | /* | ||
| 31 | * This does not append a newline | ||
| 32 | */ | ||
| 33 | static inline void flush(void) | ||
| 34 | { | ||
| 35 | } | ||
| 36 | |||
| 37 | /* | ||
| 38 | * nothing to do | ||
| 39 | */ | ||
| 40 | #define arch_decomp_setup() | ||
| 41 | #define arch_decomp_wdog() | ||
diff --git a/arch/arm/mach-mmp/include/mach/vmalloc.h b/arch/arm/mach-mmp/include/mach/vmalloc.h new file mode 100644 index 000000000000..b60ccaf9fee7 --- /dev/null +++ b/arch/arm/mach-mmp/include/mach/vmalloc.h | |||
| @@ -0,0 +1,5 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/include/mach/vmalloc.h | ||
| 3 | */ | ||
| 4 | |||
| 5 | #define VMALLOC_END 0xfe000000 | ||
diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c new file mode 100644 index 000000000000..52ff2f065eba --- /dev/null +++ b/arch/arm/mach-mmp/irq.c | |||
| @@ -0,0 +1,55 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/irq.c | ||
| 3 | * | ||
| 4 | * Generic IRQ handling, GPIO IRQ demultiplexing, etc. | ||
| 5 | * | ||
| 6 | * Author: Bin Yang <bin.yang@marvell.com> | ||
| 7 | * Created: Sep 30, 2008 | ||
| 8 | * Copyright: Marvell International Ltd. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/irq.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | |||
| 19 | #include <mach/regs-icu.h> | ||
| 20 | |||
| 21 | #include "common.h" | ||
| 22 | |||
| 23 | #define IRQ_ROUTE_TO_AP (ICU_INT_CONF_AP_INT | ICU_INT_CONF_IRQ) | ||
| 24 | |||
| 25 | #define PRIORITY_DEFAULT 0x1 | ||
| 26 | #define PRIORITY_NONE 0x0 /* means IRQ disabled */ | ||
| 27 | |||
| 28 | static void icu_mask_irq(unsigned int irq) | ||
| 29 | { | ||
| 30 | __raw_writel(PRIORITY_NONE, ICU_INT_CONF(irq)); | ||
| 31 | } | ||
| 32 | |||
| 33 | static void icu_unmask_irq(unsigned int irq) | ||
| 34 | { | ||
| 35 | __raw_writel(IRQ_ROUTE_TO_AP | PRIORITY_DEFAULT, ICU_INT_CONF(irq)); | ||
| 36 | } | ||
| 37 | |||
| 38 | static struct irq_chip icu_irq_chip = { | ||
| 39 | .name = "icu_irq", | ||
| 40 | .ack = icu_mask_irq, | ||
| 41 | .mask = icu_mask_irq, | ||
| 42 | .unmask = icu_unmask_irq, | ||
| 43 | }; | ||
| 44 | |||
| 45 | void __init icu_init_irq(void) | ||
| 46 | { | ||
| 47 | int irq; | ||
| 48 | |||
| 49 | for (irq = 0; irq < 64; irq++) { | ||
| 50 | icu_mask_irq(irq); | ||
| 51 | set_irq_chip(irq, &icu_irq_chip); | ||
| 52 | set_irq_handler(irq, handle_level_irq); | ||
| 53 | set_irq_flags(irq, IRQF_VALID); | ||
| 54 | } | ||
| 55 | } | ||
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c new file mode 100644 index 000000000000..ae924468658c --- /dev/null +++ b/arch/arm/mach-mmp/pxa168.c | |||
| @@ -0,0 +1,111 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/pxa168.c | ||
| 3 | * | ||
| 4 | * Code specific to PXA168 | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/module.h> | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/list.h> | ||
| 15 | #include <linux/io.h> | ||
| 16 | #include <linux/clk.h> | ||
| 17 | |||
| 18 | #include <asm/mach/time.h> | ||
| 19 | #include <mach/addr-map.h> | ||
| 20 | #include <mach/cputype.h> | ||
| 21 | #include <mach/regs-apbc.h> | ||
| 22 | #include <mach/irqs.h> | ||
| 23 | #include <mach/gpio.h> | ||
| 24 | #include <mach/dma.h> | ||
| 25 | #include <mach/devices.h> | ||
| 26 | #include <mach/mfp.h> | ||
| 27 | |||
| 28 | #include "common.h" | ||
| 29 | #include "clock.h" | ||
| 30 | |||
| 31 | #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) | ||
| 32 | |||
| 33 | static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata = | ||
| 34 | { | ||
| 35 | MFP_ADDR_X(GPIO0, GPIO36, 0x04c), | ||
| 36 | MFP_ADDR_X(GPIO37, GPIO55, 0x000), | ||
| 37 | MFP_ADDR_X(GPIO56, GPIO123, 0x0e0), | ||
| 38 | MFP_ADDR_X(GPIO124, GPIO127, 0x0f4), | ||
| 39 | |||
| 40 | MFP_ADDR_END, | ||
| 41 | }; | ||
| 42 | |||
| 43 | #define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) | ||
| 44 | |||
| 45 | static void __init pxa168_init_gpio(void) | ||
| 46 | { | ||
| 47 | int i; | ||
| 48 | |||
| 49 | /* enable GPIO clock */ | ||
| 50 | __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA168_GPIO); | ||
| 51 | |||
| 52 | /* unmask GPIO edge detection for all 4 banks - APMASKx */ | ||
| 53 | for (i = 0; i < 4; i++) | ||
| 54 | __raw_writel(0xffffffff, APMASK(i)); | ||
| 55 | |||
| 56 | pxa_init_gpio(IRQ_PXA168_GPIOX, 0, 127, NULL); | ||
| 57 | } | ||
| 58 | |||
| 59 | void __init pxa168_init_irq(void) | ||
| 60 | { | ||
| 61 | icu_init_irq(); | ||
| 62 | pxa168_init_gpio(); | ||
| 63 | } | ||
| 64 | |||
| 65 | /* APB peripheral clocks */ | ||
| 66 | static APBC_CLK(uart1, PXA168_UART1, 1, 14745600); | ||
| 67 | static APBC_CLK(uart2, PXA168_UART2, 1, 14745600); | ||
| 68 | |||
| 69 | /* device and clock bindings */ | ||
| 70 | static struct clk_lookup pxa168_clkregs[] = { | ||
| 71 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | ||
| 72 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), | ||
| 73 | }; | ||
| 74 | |||
| 75 | static int __init pxa168_init(void) | ||
| 76 | { | ||
| 77 | if (cpu_is_pxa168()) { | ||
| 78 | mfp_init_base(MFPR_VIRT_BASE); | ||
| 79 | mfp_init_addr(pxa168_mfp_addr_map); | ||
| 80 | pxa_init_dma(IRQ_PXA168_DMA_INT0, 32); | ||
| 81 | clks_register(ARRAY_AND_SIZE(pxa168_clkregs)); | ||
| 82 | } | ||
| 83 | |||
| 84 | return 0; | ||
| 85 | } | ||
| 86 | postcore_initcall(pxa168_init); | ||
| 87 | |||
| 88 | /* system timer - clock enabled, 3.25MHz */ | ||
| 89 | #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) | ||
| 90 | |||
| 91 | static void __init pxa168_timer_init(void) | ||
| 92 | { | ||
| 93 | /* this is early, we have to initialize the CCU registers by | ||
| 94 | * ourselves instead of using clk_* API. Clock rate is defined | ||
| 95 | * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running | ||
| 96 | */ | ||
| 97 | __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS); | ||
| 98 | |||
| 99 | /* 3.25MHz, bus/functional clock enabled, release reset */ | ||
| 100 | __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS); | ||
| 101 | |||
| 102 | timer_init(IRQ_PXA168_TIMER1); | ||
| 103 | } | ||
| 104 | |||
| 105 | struct sys_timer pxa168_timer = { | ||
| 106 | .init = pxa168_timer_init, | ||
| 107 | }; | ||
| 108 | |||
| 109 | /* on-chip devices */ | ||
| 110 | PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22); | ||
| 111 | PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24); | ||
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c new file mode 100644 index 000000000000..453f8f7758bf --- /dev/null +++ b/arch/arm/mach-mmp/pxa910.c | |||
| @@ -0,0 +1,158 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/pxa910.c | ||
| 3 | * | ||
| 4 | * Code specific to PXA910 | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/module.h> | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/list.h> | ||
| 15 | #include <linux/io.h> | ||
| 16 | |||
| 17 | #include <asm/mach/time.h> | ||
| 18 | #include <mach/addr-map.h> | ||
| 19 | #include <mach/regs-apbc.h> | ||
| 20 | #include <mach/regs-apmu.h> | ||
| 21 | #include <mach/cputype.h> | ||
| 22 | #include <mach/irqs.h> | ||
| 23 | #include <mach/gpio.h> | ||
| 24 | #include <mach/dma.h> | ||
| 25 | #include <mach/mfp.h> | ||
| 26 | #include <mach/devices.h> | ||
| 27 | |||
| 28 | #include "common.h" | ||
| 29 | #include "clock.h" | ||
| 30 | |||
| 31 | #define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) | ||
| 32 | |||
| 33 | static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata = | ||
| 34 | { | ||
| 35 | MFP_ADDR_X(GPIO0, GPIO54, 0xdc), | ||
| 36 | MFP_ADDR_X(GPIO67, GPIO98, 0x1b8), | ||
| 37 | MFP_ADDR_X(GPIO100, GPIO109, 0x238), | ||
| 38 | |||
| 39 | MFP_ADDR(GPIO123, 0xcc), | ||
| 40 | MFP_ADDR(GPIO124, 0xd0), | ||
| 41 | |||
| 42 | MFP_ADDR(DF_IO0, 0x40), | ||
| 43 | MFP_ADDR(DF_IO1, 0x3c), | ||
| 44 | MFP_ADDR(DF_IO2, 0x38), | ||
| 45 | MFP_ADDR(DF_IO3, 0x34), | ||
| 46 | MFP_ADDR(DF_IO4, 0x30), | ||
| 47 | MFP_ADDR(DF_IO5, 0x2c), | ||
| 48 | MFP_ADDR(DF_IO6, 0x28), | ||
| 49 | MFP_ADDR(DF_IO7, 0x24), | ||
| 50 | MFP_ADDR(DF_IO8, 0x20), | ||
| 51 | MFP_ADDR(DF_IO9, 0x1c), | ||
| 52 | MFP_ADDR(DF_IO10, 0x18), | ||
| 53 | MFP_ADDR(DF_IO11, 0x14), | ||
| 54 | MFP_ADDR(DF_IO12, 0x10), | ||
| 55 | MFP_ADDR(DF_IO13, 0xc), | ||
| 56 | MFP_ADDR(DF_IO14, 0x8), | ||
| 57 | MFP_ADDR(DF_IO15, 0x4), | ||
| 58 | |||
| 59 | MFP_ADDR(DF_nCS0_SM_nCS2, 0x44), | ||
| 60 | MFP_ADDR(DF_nCS1_SM_nCS3, 0x48), | ||
| 61 | MFP_ADDR(SM_nCS0, 0x4c), | ||
| 62 | MFP_ADDR(SM_nCS1, 0x50), | ||
| 63 | MFP_ADDR(DF_WEn, 0x54), | ||
| 64 | MFP_ADDR(DF_REn, 0x58), | ||
| 65 | MFP_ADDR(DF_CLE_SM_OEn, 0x5c), | ||
| 66 | MFP_ADDR(DF_ALE_SM_WEn, 0x60), | ||
| 67 | MFP_ADDR(SM_SCLK, 0x64), | ||
| 68 | MFP_ADDR(DF_RDY0, 0x68), | ||
| 69 | MFP_ADDR(SM_BE0, 0x6c), | ||
| 70 | MFP_ADDR(SM_BE1, 0x70), | ||
| 71 | MFP_ADDR(SM_ADV, 0x74), | ||
| 72 | MFP_ADDR(DF_RDY1, 0x78), | ||
| 73 | MFP_ADDR(SM_ADVMUX, 0x7c), | ||
| 74 | MFP_ADDR(SM_RDY, 0x80), | ||
| 75 | |||
| 76 | MFP_ADDR_X(MMC1_DAT7, MMC1_WP, 0x84), | ||
| 77 | |||
| 78 | MFP_ADDR_END, | ||
| 79 | }; | ||
| 80 | |||
| 81 | #define APMASK(i) (GPIO_REGS_VIRT + BANK_OFF(i) + 0x09c) | ||
| 82 | |||
| 83 | static void __init pxa910_init_gpio(void) | ||
| 84 | { | ||
| 85 | int i; | ||
| 86 | |||
| 87 | /* enable GPIO clock */ | ||
| 88 | __raw_writel(APBC_APBCLK | APBC_FNCLK, APBC_PXA910_GPIO); | ||
| 89 | |||
| 90 | /* unmask GPIO edge detection for all 4 banks - APMASKx */ | ||
| 91 | for (i = 0; i < 4; i++) | ||
| 92 | __raw_writel(0xffffffff, APMASK(i)); | ||
| 93 | |||
| 94 | pxa_init_gpio(IRQ_PXA910_AP_GPIO, 0, 127, NULL); | ||
| 95 | } | ||
| 96 | |||
| 97 | void __init pxa910_init_irq(void) | ||
| 98 | { | ||
| 99 | icu_init_irq(); | ||
| 100 | pxa910_init_gpio(); | ||
| 101 | } | ||
| 102 | |||
| 103 | /* APB peripheral clocks */ | ||
| 104 | static APBC_CLK(uart1, PXA910_UART0, 1, 14745600); | ||
| 105 | static APBC_CLK(uart2, PXA910_UART1, 1, 14745600); | ||
| 106 | |||
| 107 | /* device and clock bindings */ | ||
| 108 | static struct clk_lookup pxa910_clkregs[] = { | ||
| 109 | INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL), | ||
| 110 | INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL), | ||
| 111 | }; | ||
| 112 | |||
| 113 | static int __init pxa910_init(void) | ||
| 114 | { | ||
| 115 | if (cpu_is_pxa910()) { | ||
| 116 | mfp_init_base(MFPR_VIRT_BASE); | ||
| 117 | mfp_init_addr(pxa910_mfp_addr_map); | ||
| 118 | pxa_init_dma(IRQ_PXA910_DMA_INT0, 32); | ||
| 119 | clks_register(ARRAY_AND_SIZE(pxa910_clkregs)); | ||
| 120 | } | ||
| 121 | |||
| 122 | return 0; | ||
| 123 | } | ||
| 124 | postcore_initcall(pxa910_init); | ||
| 125 | |||
| 126 | /* system timer - clock enabled, 3.25MHz */ | ||
| 127 | #define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) | ||
| 128 | |||
| 129 | static void __init pxa910_timer_init(void) | ||
| 130 | { | ||
| 131 | /* reset and configure */ | ||
| 132 | __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS); | ||
| 133 | __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS); | ||
| 134 | |||
| 135 | timer_init(IRQ_PXA910_AP1_TIMER1); | ||
| 136 | } | ||
| 137 | |||
| 138 | struct sys_timer pxa910_timer = { | ||
| 139 | .init = pxa910_timer_init, | ||
| 140 | }; | ||
| 141 | |||
| 142 | /* on-chip devices */ | ||
| 143 | |||
| 144 | /* NOTE: there are totally 3 UARTs on PXA910: | ||
| 145 | * | ||
| 146 | * UART1 - Slow UART (can be used both by AP and CP) | ||
| 147 | * UART2/3 - Fast UART | ||
| 148 | * | ||
| 149 | * To be backward compatible with the legacy FFUART/BTUART/STUART sequence, | ||
| 150 | * they are re-ordered as: | ||
| 151 | * | ||
| 152 | * pxa910_device_uart1 - UART2 as FFUART | ||
| 153 | * pxa910_device_uart2 - UART3 as BTUART | ||
| 154 | * | ||
| 155 | * UART1 is not used by AP for the moment. | ||
| 156 | */ | ||
| 157 | PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22); | ||
| 158 | PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24); | ||
diff --git a/arch/arm/mach-mmp/tavorevb.c b/arch/arm/mach-mmp/tavorevb.c new file mode 100644 index 000000000000..0e0c9220eaba --- /dev/null +++ b/arch/arm/mach-mmp/tavorevb.c | |||
| @@ -0,0 +1,109 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/tavorevb.c | ||
| 3 | * | ||
| 4 | * Support for the Marvell PXA910-based TavorEVB Development Platform. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * publishhed by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/smc91x.h> | ||
| 15 | |||
| 16 | #include <asm/mach-types.h> | ||
| 17 | #include <asm/mach/arch.h> | ||
| 18 | #include <mach/addr-map.h> | ||
| 19 | #include <mach/mfp-pxa910.h> | ||
| 20 | #include <mach/pxa910.h> | ||
| 21 | #include <mach/gpio.h> | ||
| 22 | |||
| 23 | #include "common.h" | ||
| 24 | |||
| 25 | static unsigned long tavorevb_pin_config[] __initdata = { | ||
| 26 | /* UART2 */ | ||
| 27 | GPIO47_UART2_RXD, | ||
| 28 | GPIO48_UART2_TXD, | ||
| 29 | |||
| 30 | /* SMC */ | ||
| 31 | SM_nCS0_nCS0, | ||
| 32 | SM_ADV_SM_ADV, | ||
| 33 | SM_SCLK_SM_SCLK, | ||
| 34 | SM_SCLK_SM_SCLK, | ||
| 35 | SM_BE0_SM_BE0, | ||
| 36 | SM_BE1_SM_BE1, | ||
| 37 | |||
| 38 | /* DFI */ | ||
| 39 | DF_IO0_ND_IO0, | ||
| 40 | DF_IO1_ND_IO1, | ||
| 41 | DF_IO2_ND_IO2, | ||
| 42 | DF_IO3_ND_IO3, | ||
| 43 | DF_IO4_ND_IO4, | ||
| 44 | DF_IO5_ND_IO5, | ||
| 45 | DF_IO6_ND_IO6, | ||
| 46 | DF_IO7_ND_IO7, | ||
| 47 | DF_IO8_ND_IO8, | ||
| 48 | DF_IO9_ND_IO9, | ||
| 49 | DF_IO10_ND_IO10, | ||
| 50 | DF_IO11_ND_IO11, | ||
| 51 | DF_IO12_ND_IO12, | ||
| 52 | DF_IO13_ND_IO13, | ||
| 53 | DF_IO14_ND_IO14, | ||
| 54 | DF_IO15_ND_IO15, | ||
| 55 | DF_nCS0_SM_nCS2_nCS0, | ||
| 56 | DF_ALE_SM_WEn_ND_ALE, | ||
| 57 | DF_CLE_SM_OEn_ND_CLE, | ||
| 58 | DF_WEn_DF_WEn, | ||
| 59 | DF_REn_DF_REn, | ||
| 60 | DF_RDY0_DF_RDY0, | ||
| 61 | }; | ||
| 62 | |||
| 63 | static struct smc91x_platdata tavorevb_smc91x_info = { | ||
| 64 | .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, | ||
| 65 | }; | ||
| 66 | |||
| 67 | static struct resource smc91x_resources[] = { | ||
| 68 | [0] = { | ||
| 69 | .start = SMC_CS1_PHYS_BASE + 0x300, | ||
| 70 | .end = SMC_CS1_PHYS_BASE + 0xfffff, | ||
| 71 | .flags = IORESOURCE_MEM, | ||
| 72 | }, | ||
| 73 | [1] = { | ||
| 74 | .start = gpio_to_irq(80), | ||
| 75 | .end = gpio_to_irq(80), | ||
| 76 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, | ||
| 77 | } | ||
| 78 | }; | ||
| 79 | |||
| 80 | static struct platform_device smc91x_device = { | ||
| 81 | .name = "smc91x", | ||
| 82 | .id = 0, | ||
| 83 | .dev = { | ||
| 84 | .platform_data = &tavorevb_smc91x_info, | ||
| 85 | }, | ||
| 86 | .num_resources = ARRAY_SIZE(smc91x_resources), | ||
| 87 | .resource = smc91x_resources, | ||
| 88 | }; | ||
| 89 | |||
| 90 | static void __init tavorevb_init(void) | ||
| 91 | { | ||
| 92 | mfp_config(ARRAY_AND_SIZE(tavorevb_pin_config)); | ||
| 93 | |||
| 94 | /* on-chip devices */ | ||
| 95 | pxa910_add_uart(1); | ||
| 96 | |||
| 97 | /* off-chip devices */ | ||
| 98 | platform_device_register(&smc91x_device); | ||
| 99 | } | ||
| 100 | |||
| 101 | MACHINE_START(TAVOREVB, "PXA910 Evaluation Board (aka TavorEVB)") | ||
| 102 | .phys_io = APB_PHYS_BASE, | ||
| 103 | .boot_params = 0x00000100, | ||
| 104 | .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, | ||
| 105 | .map_io = pxa_map_io, | ||
| 106 | .init_irq = pxa910_init_irq, | ||
| 107 | .timer = &pxa910_timer, | ||
| 108 | .init_machine = tavorevb_init, | ||
| 109 | MACHINE_END | ||
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c new file mode 100644 index 000000000000..b03a6eda7419 --- /dev/null +++ b/arch/arm/mach-mmp/time.c | |||
| @@ -0,0 +1,199 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/time.c | ||
| 3 | * | ||
| 4 | * Support for clocksource and clockevents | ||
| 5 | * | ||
| 6 | * Copyright (C) 2008 Marvell International Ltd. | ||
| 7 | * All rights reserved. | ||
| 8 | * | ||
| 9 | * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com> | ||
| 10 | * 2008-10-08: Bin Yang <bin.yang@marvell.com> | ||
| 11 | * | ||
| 12 | * The timers module actually includes three timers, each timer with upto | ||
| 13 | * three match comparators. Timer #0 is used here in free-running mode as | ||
| 14 | * the clock source, and match comparator #1 used as clock event device. | ||
| 15 | * | ||
| 16 | * This program is free software; you can redistribute it and/or modify | ||
| 17 | * it under the terms of the GNU General Public License version 2 as | ||
| 18 | * published by the Free Software Foundation. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/init.h> | ||
| 22 | #include <linux/kernel.h> | ||
| 23 | #include <linux/interrupt.h> | ||
| 24 | #include <linux/clockchips.h> | ||
| 25 | |||
| 26 | #include <linux/io.h> | ||
| 27 | #include <linux/irq.h> | ||
| 28 | #include <linux/sched.h> | ||
| 29 | #include <linux/cnt32_to_63.h> | ||
| 30 | |||
| 31 | #include <mach/addr-map.h> | ||
| 32 | #include <mach/regs-timers.h> | ||
| 33 | #include <mach/irqs.h> | ||
| 34 | |||
| 35 | #include "clock.h" | ||
| 36 | |||
| 37 | #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE | ||
| 38 | |||
| 39 | #define MAX_DELTA (0xfffffffe) | ||
| 40 | #define MIN_DELTA (16) | ||
| 41 | |||
| 42 | #define TCR2NS_SCALE_FACTOR 10 | ||
| 43 | |||
| 44 | static unsigned long tcr2ns_scale; | ||
| 45 | |||
| 46 | static void __init set_tcr2ns_scale(unsigned long tcr_rate) | ||
| 47 | { | ||
| 48 | unsigned long long v = 1000000000ULL << TCR2NS_SCALE_FACTOR; | ||
| 49 | do_div(v, tcr_rate); | ||
| 50 | tcr2ns_scale = v; | ||
| 51 | /* | ||
| 52 | * We want an even value to automatically clear the top bit | ||
| 53 | * returned by cnt32_to_63() without an additional run time | ||
| 54 | * instruction. So if the LSB is 1 then round it up. | ||
| 55 | */ | ||
| 56 | if (tcr2ns_scale & 1) | ||
| 57 | tcr2ns_scale++; | ||
| 58 | } | ||
| 59 | |||
| 60 | /* | ||
| 61 | * FIXME: the timer needs some delay to stablize the counter capture | ||
| 62 | */ | ||
| 63 | static inline uint32_t timer_read(void) | ||
| 64 | { | ||
| 65 | int delay = 100; | ||
| 66 | |||
| 67 | __raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(0)); | ||
| 68 | |||
| 69 | while (delay--) | ||
| 70 | cpu_relax(); | ||
| 71 | |||
| 72 | return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(0)); | ||
| 73 | } | ||
| 74 | |||
| 75 | unsigned long long sched_clock(void) | ||
| 76 | { | ||
| 77 | unsigned long long v = cnt32_to_63(timer_read()); | ||
| 78 | return (v * tcr2ns_scale) >> TCR2NS_SCALE_FACTOR; | ||
| 79 | } | ||
| 80 | |||
| 81 | static irqreturn_t timer_interrupt(int irq, void *dev_id) | ||
| 82 | { | ||
| 83 | struct clock_event_device *c = dev_id; | ||
| 84 | |||
| 85 | /* disable and clear pending interrupt status */ | ||
| 86 | __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0)); | ||
| 87 | __raw_writel(0x1, TIMERS_VIRT_BASE + TMR_ICR(0)); | ||
| 88 | c->event_handler(c); | ||
| 89 | return IRQ_HANDLED; | ||
| 90 | } | ||
| 91 | |||
| 92 | static int timer_set_next_event(unsigned long delta, | ||
| 93 | struct clock_event_device *dev) | ||
| 94 | { | ||
| 95 | unsigned long flags, next; | ||
| 96 | |||
| 97 | local_irq_save(flags); | ||
| 98 | |||
| 99 | /* clear pending interrupt status and enable */ | ||
| 100 | __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0)); | ||
| 101 | __raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0)); | ||
| 102 | |||
| 103 | next = timer_read() + delta; | ||
| 104 | __raw_writel(next, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0)); | ||
| 105 | |||
| 106 | local_irq_restore(flags); | ||
| 107 | return 0; | ||
| 108 | } | ||
| 109 | |||
| 110 | static void timer_set_mode(enum clock_event_mode mode, | ||
| 111 | struct clock_event_device *dev) | ||
| 112 | { | ||
| 113 | unsigned long flags; | ||
| 114 | |||
| 115 | local_irq_save(flags); | ||
| 116 | switch (mode) { | ||
| 117 | case CLOCK_EVT_MODE_ONESHOT: | ||
| 118 | case CLOCK_EVT_MODE_UNUSED: | ||
| 119 | case CLOCK_EVT_MODE_SHUTDOWN: | ||
| 120 | /* disable the matching interrupt */ | ||
| 121 | __raw_writel(0x00, TIMERS_VIRT_BASE + TMR_IER(0)); | ||
| 122 | break; | ||
| 123 | case CLOCK_EVT_MODE_RESUME: | ||
| 124 | case CLOCK_EVT_MODE_PERIODIC: | ||
| 125 | break; | ||
| 126 | } | ||
| 127 | local_irq_restore(flags); | ||
| 128 | } | ||
| 129 | |||
| 130 | static struct clock_event_device ckevt = { | ||
| 131 | .name = "clockevent", | ||
| 132 | .features = CLOCK_EVT_FEAT_ONESHOT, | ||
| 133 | .shift = 32, | ||
| 134 | .rating = 200, | ||
| 135 | .set_next_event = timer_set_next_event, | ||
| 136 | .set_mode = timer_set_mode, | ||
| 137 | }; | ||
| 138 | |||
| 139 | static cycle_t clksrc_read(void) | ||
| 140 | { | ||
| 141 | return timer_read(); | ||
| 142 | } | ||
| 143 | |||
| 144 | static struct clocksource cksrc = { | ||
| 145 | .name = "clocksource", | ||
| 146 | .shift = 20, | ||
| 147 | .rating = 200, | ||
| 148 | .read = clksrc_read, | ||
| 149 | .mask = CLOCKSOURCE_MASK(32), | ||
| 150 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | ||
| 151 | }; | ||
| 152 | |||
| 153 | static void __init timer_config(void) | ||
| 154 | { | ||
| 155 | uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR); | ||
| 156 | uint32_t cer = __raw_readl(TIMERS_VIRT_BASE + TMR_CER); | ||
| 157 | uint32_t cmr = __raw_readl(TIMERS_VIRT_BASE + TMR_CMR); | ||
| 158 | |||
| 159 | __raw_writel(cer & ~0x1, TIMERS_VIRT_BASE + TMR_CER); /* disable */ | ||
| 160 | |||
| 161 | ccr &= TMR_CCR_CS_0(0x3); | ||
| 162 | __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR); | ||
| 163 | |||
| 164 | /* free-running mode */ | ||
| 165 | __raw_writel(cmr | 0x01, TIMERS_VIRT_BASE + TMR_CMR); | ||
| 166 | |||
| 167 | __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* free-running */ | ||
| 168 | __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0)); /* clear status */ | ||
| 169 | __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0)); | ||
| 170 | |||
| 171 | /* enable timer counter */ | ||
| 172 | __raw_writel(cer | 0x01, TIMERS_VIRT_BASE + TMR_CER); | ||
| 173 | } | ||
| 174 | |||
| 175 | static struct irqaction timer_irq = { | ||
| 176 | .name = "timer", | ||
| 177 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
| 178 | .handler = timer_interrupt, | ||
| 179 | .dev_id = &ckevt, | ||
| 180 | }; | ||
| 181 | |||
| 182 | void __init timer_init(int irq) | ||
| 183 | { | ||
| 184 | timer_config(); | ||
| 185 | |||
| 186 | set_tcr2ns_scale(CLOCK_TICK_RATE); | ||
| 187 | |||
| 188 | ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift); | ||
| 189 | ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt); | ||
| 190 | ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt); | ||
| 191 | ckevt.cpumask = cpumask_of(0); | ||
| 192 | |||
| 193 | cksrc.mult = clocksource_hz2mult(CLOCK_TICK_RATE, cksrc.shift); | ||
| 194 | |||
| 195 | setup_irq(irq, &timer_irq); | ||
| 196 | |||
| 197 | clocksource_register(&cksrc); | ||
| 198 | clockevents_register_device(&ckevt); | ||
| 199 | } | ||
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c new file mode 100644 index 000000000000..08cfef6c92a2 --- /dev/null +++ b/arch/arm/mach-mmp/ttc_dkb.c | |||
| @@ -0,0 +1,47 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mmp/ttc_dkb.c | ||
| 3 | * | ||
| 4 | * Support for the Marvell PXA910-based TTC_DKB Development Platform. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * publishhed by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/init.h> | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | |||
| 15 | #include <asm/mach-types.h> | ||
| 16 | #include <asm/mach/arch.h> | ||
| 17 | #include <mach/addr-map.h> | ||
| 18 | #include <mach/mfp-pxa910.h> | ||
| 19 | #include <mach/pxa910.h> | ||
| 20 | |||
| 21 | #include "common.h" | ||
| 22 | |||
| 23 | #define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) | ||
| 24 | |||
| 25 | static unsigned long ttc_dkb_pin_config[] __initdata = { | ||
| 26 | /* UART2 */ | ||
| 27 | GPIO47_UART2_RXD, | ||
| 28 | GPIO48_UART2_TXD, | ||
| 29 | }; | ||
| 30 | |||
| 31 | static void __init ttc_dkb_init(void) | ||
| 32 | { | ||
| 33 | mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config)); | ||
| 34 | |||
| 35 | /* on-chip devices */ | ||
| 36 | pxa910_add_uart(1); | ||
| 37 | } | ||
| 38 | |||
| 39 | MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform") | ||
| 40 | .phys_io = APB_PHYS_BASE, | ||
| 41 | .boot_params = 0x00000100, | ||
| 42 | .io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc, | ||
| 43 | .map_io = pxa_map_io, | ||
| 44 | .init_irq = pxa910_init_irq, | ||
| 45 | .timer = &pxa910_timer, | ||
| 46 | .init_machine = ttc_dkb_init, | ||
| 47 | MACHINE_END | ||
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h index f05ad2e0f235..574ccc493daf 100644 --- a/arch/arm/mach-msm/include/mach/system.h +++ b/arch/arm/mach-msm/include/mach/system.h | |||
| @@ -17,7 +17,7 @@ | |||
| 17 | 17 | ||
| 18 | void arch_idle(void); | 18 | void arch_idle(void); |
| 19 | 19 | ||
| 20 | static inline void arch_reset(char mode) | 20 | static inline void arch_reset(char mode, const char *cmd) |
| 21 | { | 21 | { |
| 22 | for (;;) ; /* depends on IPC w/ other core */ | 22 | for (;;) ; /* depends on IPC w/ other core */ |
| 23 | } | 23 | } |
diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig index d83cb86837db..6fbe68fe4412 100644 --- a/arch/arm/mach-mv78xx0/Kconfig +++ b/arch/arm/mach-mv78xx0/Kconfig | |||
| @@ -8,6 +8,12 @@ config MACH_DB78X00_BP | |||
| 8 | Say 'Y' here if you want your kernel to support the | 8 | Say 'Y' here if you want your kernel to support the |
| 9 | Marvell DB-78x00-BP Development Board. | 9 | Marvell DB-78x00-BP Development Board. |
| 10 | 10 | ||
| 11 | config MACH_RD78X00_MASA | ||
| 12 | bool "Marvell RD-78x00-mASA Reference Design" | ||
| 13 | help | ||
| 14 | Say 'Y' here if you want your kernel to support the | ||
| 15 | Marvell RD-78x00-mASA Reference Design. | ||
| 16 | |||
| 11 | endmenu | 17 | endmenu |
| 12 | 18 | ||
| 13 | endif | 19 | endif |
diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile index ec16c05c3b1b..da628b7f3bb6 100644 --- a/arch/arm/mach-mv78xx0/Makefile +++ b/arch/arm/mach-mv78xx0/Makefile | |||
| @@ -1,2 +1,3 @@ | |||
| 1 | obj-y += common.o addr-map.o irq.o pcie.o | 1 | obj-y += common.o addr-map.o irq.o pcie.o |
| 2 | obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o | 2 | obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o |
| 3 | obj-$(CONFIG_MACH_RD78X00_MASA) += rd78x00-masa-setup.o | ||
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c index b0e4e0d8f506..a575daaa62d1 100644 --- a/arch/arm/mach-mv78xx0/common.c +++ b/arch/arm/mach-mv78xx0/common.c | |||
| @@ -14,7 +14,9 @@ | |||
| 14 | #include <linux/serial_8250.h> | 14 | #include <linux/serial_8250.h> |
| 15 | #include <linux/mbus.h> | 15 | #include <linux/mbus.h> |
| 16 | #include <linux/mv643xx_eth.h> | 16 | #include <linux/mv643xx_eth.h> |
| 17 | #include <linux/mv643xx_i2c.h> | ||
| 17 | #include <linux/ata_platform.h> | 18 | #include <linux/ata_platform.h> |
| 19 | #include <linux/ethtool.h> | ||
| 18 | #include <asm/mach/map.h> | 20 | #include <asm/mach/map.h> |
| 19 | #include <asm/mach/time.h> | 21 | #include <asm/mach/time.h> |
| 20 | #include <mach/mv78xx0.h> | 22 | #include <mach/mv78xx0.h> |
| @@ -430,9 +432,22 @@ static struct platform_device mv78xx0_ge10 = { | |||
| 430 | 432 | ||
| 431 | void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) | 433 | void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data) |
| 432 | { | 434 | { |
| 435 | u32 dev, rev; | ||
| 436 | |||
| 433 | eth_data->shared = &mv78xx0_ge10_shared; | 437 | eth_data->shared = &mv78xx0_ge10_shared; |
| 434 | mv78xx0_ge10.dev.platform_data = eth_data; | 438 | mv78xx0_ge10.dev.platform_data = eth_data; |
| 435 | 439 | ||
| 440 | /* | ||
| 441 | * On the Z0, ge10 and ge11 are internally connected back | ||
| 442 | * to back, and not brought out. | ||
| 443 | */ | ||
| 444 | mv78xx0_pcie_id(&dev, &rev); | ||
| 445 | if (dev == MV78X00_Z0_DEV_ID) { | ||
| 446 | eth_data->phy_addr = MV643XX_ETH_PHY_NONE; | ||
| 447 | eth_data->speed = SPEED_1000; | ||
| 448 | eth_data->duplex = DUPLEX_FULL; | ||
| 449 | } | ||
| 450 | |||
| 436 | platform_device_register(&mv78xx0_ge10_shared); | 451 | platform_device_register(&mv78xx0_ge10_shared); |
| 437 | platform_device_register(&mv78xx0_ge10); | 452 | platform_device_register(&mv78xx0_ge10); |
| 438 | } | 453 | } |
| @@ -484,13 +499,101 @@ static struct platform_device mv78xx0_ge11 = { | |||
| 484 | 499 | ||
| 485 | void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) | 500 | void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data) |
| 486 | { | 501 | { |
| 502 | u32 dev, rev; | ||
| 503 | |||
| 487 | eth_data->shared = &mv78xx0_ge11_shared; | 504 | eth_data->shared = &mv78xx0_ge11_shared; |
| 488 | mv78xx0_ge11.dev.platform_data = eth_data; | 505 | mv78xx0_ge11.dev.platform_data = eth_data; |
| 489 | 506 | ||
| 507 | /* | ||
| 508 | * On the Z0, ge10 and ge11 are internally connected back | ||
| 509 | * to back, and not brought out. | ||
| 510 | */ | ||
| 511 | mv78xx0_pcie_id(&dev, &rev); | ||
| 512 | if (dev == MV78X00_Z0_DEV_ID) { | ||
| 513 | eth_data->phy_addr = MV643XX_ETH_PHY_NONE; | ||
| 514 | eth_data->speed = SPEED_1000; | ||
| 515 | eth_data->duplex = DUPLEX_FULL; | ||
| 516 | } | ||
| 517 | |||
| 490 | platform_device_register(&mv78xx0_ge11_shared); | 518 | platform_device_register(&mv78xx0_ge11_shared); |
| 491 | platform_device_register(&mv78xx0_ge11); | 519 | platform_device_register(&mv78xx0_ge11); |
| 492 | } | 520 | } |
| 493 | 521 | ||
| 522 | /***************************************************************************** | ||
| 523 | * I2C bus 0 | ||
| 524 | ****************************************************************************/ | ||
| 525 | |||
| 526 | static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = { | ||
| 527 | .freq_m = 8, /* assumes 166 MHz TCLK */ | ||
| 528 | .freq_n = 3, | ||
| 529 | .timeout = 1000, /* Default timeout of 1 second */ | ||
| 530 | }; | ||
| 531 | |||
| 532 | static struct resource mv78xx0_i2c_0_resources[] = { | ||
| 533 | { | ||
| 534 | .name = "i2c 0 base", | ||
| 535 | .start = I2C_0_PHYS_BASE, | ||
| 536 | .end = I2C_0_PHYS_BASE + 0x1f, | ||
| 537 | .flags = IORESOURCE_MEM, | ||
| 538 | }, { | ||
| 539 | .name = "i2c 0 irq", | ||
| 540 | .start = IRQ_MV78XX0_I2C_0, | ||
| 541 | .end = IRQ_MV78XX0_I2C_0, | ||
| 542 | .flags = IORESOURCE_IRQ, | ||
| 543 | }, | ||
| 544 | }; | ||
| 545 | |||
| 546 | |||
| 547 | static struct platform_device mv78xx0_i2c_0 = { | ||
| 548 | .name = MV64XXX_I2C_CTLR_NAME, | ||
| 549 | .id = 0, | ||
| 550 | .num_resources = ARRAY_SIZE(mv78xx0_i2c_0_resources), | ||
| 551 | .resource = mv78xx0_i2c_0_resources, | ||
| 552 | .dev = { | ||
| 553 | .platform_data = &mv78xx0_i2c_0_pdata, | ||
| 554 | }, | ||
| 555 | }; | ||
| 556 | |||
| 557 | /***************************************************************************** | ||
| 558 | * I2C bus 1 | ||
| 559 | ****************************************************************************/ | ||
| 560 | |||
| 561 | static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = { | ||
| 562 | .freq_m = 8, /* assumes 166 MHz TCLK */ | ||
| 563 | .freq_n = 3, | ||
| 564 | .timeout = 1000, /* Default timeout of 1 second */ | ||
| 565 | }; | ||
| 566 | |||
| 567 | static struct resource mv78xx0_i2c_1_resources[] = { | ||
| 568 | { | ||
| 569 | .name = "i2c 1 base", | ||
| 570 | .start = I2C_1_PHYS_BASE, | ||
| 571 | .end = I2C_1_PHYS_BASE + 0x1f, | ||
| 572 | .flags = IORESOURCE_MEM, | ||
| 573 | }, { | ||
| 574 | .name = "i2c 1 irq", | ||
| 575 | .start = IRQ_MV78XX0_I2C_1, | ||
| 576 | .end = IRQ_MV78XX0_I2C_1, | ||
| 577 | .flags = IORESOURCE_IRQ, | ||
| 578 | }, | ||
| 579 | }; | ||
| 580 | |||
| 581 | |||
| 582 | static struct platform_device mv78xx0_i2c_1 = { | ||
| 583 | .name = MV64XXX_I2C_CTLR_NAME, | ||
| 584 | .id = 1, | ||
| 585 | .num_resources = ARRAY_SIZE(mv78xx0_i2c_1_resources), | ||
| 586 | .resource = mv78xx0_i2c_1_resources, | ||
| 587 | .dev = { | ||
| 588 | .platform_data = &mv78xx0_i2c_1_pdata, | ||
| 589 | }, | ||
| 590 | }; | ||
| 591 | |||
| 592 | void __init mv78xx0_i2c_init(void) | ||
| 593 | { | ||
| 594 | platform_device_register(&mv78xx0_i2c_0); | ||
| 595 | platform_device_register(&mv78xx0_i2c_1); | ||
| 596 | } | ||
| 494 | 597 | ||
| 495 | /***************************************************************************** | 598 | /***************************************************************************** |
| 496 | * SATA | 599 | * SATA |
| @@ -719,6 +822,32 @@ struct sys_timer mv78xx0_timer = { | |||
| 719 | /***************************************************************************** | 822 | /***************************************************************************** |
| 720 | * General | 823 | * General |
| 721 | ****************************************************************************/ | 824 | ****************************************************************************/ |
| 825 | static char * __init mv78xx0_id(void) | ||
| 826 | { | ||
| 827 | u32 dev, rev; | ||
| 828 | |||
| 829 | mv78xx0_pcie_id(&dev, &rev); | ||
| 830 | |||
| 831 | if (dev == MV78X00_Z0_DEV_ID) { | ||
| 832 | if (rev == MV78X00_REV_Z0) | ||
| 833 | return "MV78X00-Z0"; | ||
| 834 | else | ||
| 835 | return "MV78X00-Rev-Unsupported"; | ||
| 836 | } else if (dev == MV78100_DEV_ID) { | ||
| 837 | if (rev == MV78100_REV_A0) | ||
| 838 | return "MV78100-A0"; | ||
| 839 | else | ||
| 840 | return "MV78100-Rev-Unsupported"; | ||
| 841 | } else if (dev == MV78200_DEV_ID) { | ||
| 842 | if (rev == MV78100_REV_A0) | ||
| 843 | return "MV78200-A0"; | ||
| 844 | else | ||
| 845 | return "MV78200-Rev-Unsupported"; | ||
| 846 | } else { | ||
| 847 | return "Device-Unknown"; | ||
| 848 | } | ||
| 849 | } | ||
| 850 | |||
| 722 | static int __init is_l2_writethrough(void) | 851 | static int __init is_l2_writethrough(void) |
| 723 | { | 852 | { |
| 724 | return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); | 853 | return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH); |
| @@ -737,7 +866,8 @@ void __init mv78xx0_init(void) | |||
| 737 | get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); | 866 | get_pclk_l2clk(hclk, core_index, &pclk, &l2clk); |
| 738 | tclk = get_tclk(); | 867 | tclk = get_tclk(); |
| 739 | 868 | ||
| 740 | printk(KERN_INFO "MV78xx0 core #%d, ", core_index); | 869 | printk(KERN_INFO "%s ", mv78xx0_id()); |
| 870 | printk("core #%d, ", core_index); | ||
| 741 | printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); | 871 | printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000); |
| 742 | printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000); | 872 | printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000); |
| 743 | printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); | 873 | printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000); |
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h index 78af5de319dd..befc22475469 100644 --- a/arch/arm/mach-mv78xx0/common.h +++ b/arch/arm/mach-mv78xx0/common.h | |||
| @@ -29,6 +29,8 @@ void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size, | |||
| 29 | void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, | 29 | void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size, |
| 30 | int maj, int min); | 30 | int maj, int min); |
| 31 | 31 | ||
| 32 | void mv78xx0_pcie_id(u32 *dev, u32 *rev); | ||
| 33 | |||
| 32 | void mv78xx0_ehci0_init(void); | 34 | void mv78xx0_ehci0_init(void); |
| 33 | void mv78xx0_ehci1_init(void); | 35 | void mv78xx0_ehci1_init(void); |
| 34 | void mv78xx0_ehci2_init(void); | 36 | void mv78xx0_ehci2_init(void); |
| @@ -42,6 +44,7 @@ void mv78xx0_uart0_init(void); | |||
| 42 | void mv78xx0_uart1_init(void); | 44 | void mv78xx0_uart1_init(void); |
| 43 | void mv78xx0_uart2_init(void); | 45 | void mv78xx0_uart2_init(void); |
| 44 | void mv78xx0_uart3_init(void); | 46 | void mv78xx0_uart3_init(void); |
| 47 | void mv78xx0_i2c_init(void); | ||
| 45 | 48 | ||
| 46 | extern struct sys_timer mv78xx0_timer; | 49 | extern struct sys_timer mv78xx0_timer; |
| 47 | 50 | ||
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c index 2e285bbb7bbd..efdabe04c69e 100644 --- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c +++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | #include <linux/ata_platform.h> | 14 | #include <linux/ata_platform.h> |
| 15 | #include <linux/mv643xx_eth.h> | 15 | #include <linux/mv643xx_eth.h> |
| 16 | #include <linux/ethtool.h> | 16 | #include <linux/ethtool.h> |
| 17 | #include <linux/i2c.h> | ||
| 17 | #include <mach/mv78xx0.h> | 18 | #include <mach/mv78xx0.h> |
| 18 | #include <asm/mach-types.h> | 19 | #include <asm/mach-types.h> |
| 19 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
| @@ -28,21 +29,22 @@ static struct mv643xx_eth_platform_data db78x00_ge01_data = { | |||
| 28 | }; | 29 | }; |
| 29 | 30 | ||
| 30 | static struct mv643xx_eth_platform_data db78x00_ge10_data = { | 31 | static struct mv643xx_eth_platform_data db78x00_ge10_data = { |
| 31 | .phy_addr = MV643XX_ETH_PHY_NONE, | 32 | .phy_addr = MV643XX_ETH_PHY_ADDR(10), |
| 32 | .speed = SPEED_1000, | ||
| 33 | .duplex = DUPLEX_FULL, | ||
| 34 | }; | 33 | }; |
| 35 | 34 | ||
| 36 | static struct mv643xx_eth_platform_data db78x00_ge11_data = { | 35 | static struct mv643xx_eth_platform_data db78x00_ge11_data = { |
| 37 | .phy_addr = MV643XX_ETH_PHY_NONE, | 36 | .phy_addr = MV643XX_ETH_PHY_ADDR(11), |
| 38 | .speed = SPEED_1000, | ||
| 39 | .duplex = DUPLEX_FULL, | ||
| 40 | }; | 37 | }; |
| 41 | 38 | ||
| 42 | static struct mv_sata_platform_data db78x00_sata_data = { | 39 | static struct mv_sata_platform_data db78x00_sata_data = { |
| 43 | .n_ports = 2, | 40 | .n_ports = 2, |
| 44 | }; | 41 | }; |
| 45 | 42 | ||
| 43 | static struct i2c_board_info __initdata db78x00_i2c_rtc = { | ||
| 44 | I2C_BOARD_INFO("ds1338", 0x68), | ||
| 45 | }; | ||
| 46 | |||
| 47 | |||
| 46 | static void __init db78x00_init(void) | 48 | static void __init db78x00_init(void) |
| 47 | { | 49 | { |
| 48 | /* | 50 | /* |
| @@ -64,6 +66,8 @@ static void __init db78x00_init(void) | |||
| 64 | mv78xx0_sata_init(&db78x00_sata_data); | 66 | mv78xx0_sata_init(&db78x00_sata_data); |
| 65 | mv78xx0_uart0_init(); | 67 | mv78xx0_uart0_init(); |
| 66 | mv78xx0_uart2_init(); | 68 | mv78xx0_uart2_init(); |
| 69 | mv78xx0_i2c_init(); | ||
| 70 | i2c_register_board_info(0, &db78x00_i2c_rtc, 1); | ||
| 67 | } else { | 71 | } else { |
| 68 | mv78xx0_uart1_init(); | 72 | mv78xx0_uart1_init(); |
| 69 | mv78xx0_uart3_init(); | 73 | mv78xx0_uart3_init(); |
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h index e930ea5330a2..582cffc733ad 100644 --- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h +++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h | |||
| @@ -80,6 +80,18 @@ | |||
| 80 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) | 80 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300) |
| 81 | 81 | ||
| 82 | /* | 82 | /* |
| 83 | * Supported devices and revisions. | ||
| 84 | */ | ||
| 85 | #define MV78X00_Z0_DEV_ID 0x6381 | ||
| 86 | #define MV78X00_REV_Z0 1 | ||
| 87 | |||
| 88 | #define MV78100_DEV_ID 0x7810 | ||
| 89 | #define MV78100_REV_A0 1 | ||
| 90 | |||
| 91 | #define MV78200_DEV_ID 0x7820 | ||
| 92 | #define MV78200_REV_A0 1 | ||
| 93 | |||
| 94 | /* | ||
| 83 | * Register Map | 95 | * Register Map |
| 84 | */ | 96 | */ |
| 85 | #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) | 97 | #define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000) |
| @@ -90,6 +102,8 @@ | |||
| 90 | #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) | 102 | #define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000) |
| 91 | #define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) | 103 | #define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030) |
| 92 | #define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) | 104 | #define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034) |
| 105 | #define I2C_0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000) | ||
| 106 | #define I2C_1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1100) | ||
| 93 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) | 107 | #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000) |
| 94 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) | 108 | #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000) |
| 95 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) | 109 | #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100) |
diff --git a/arch/arm/mach-mv78xx0/include/mach/system.h b/arch/arm/mach-mv78xx0/include/mach/system.h index 7d5179408832..1d6350b22d0b 100644 --- a/arch/arm/mach-mv78xx0/include/mach/system.h +++ b/arch/arm/mach-mv78xx0/include/mach/system.h | |||
| @@ -17,7 +17,7 @@ static inline void arch_idle(void) | |||
| 17 | cpu_do_idle(); | 17 | cpu_do_idle(); |
| 18 | } | 18 | } |
| 19 | 19 | ||
| 20 | static inline void arch_reset(char mode) | 20 | static inline void arch_reset(char mode, const char *cmd) |
| 21 | { | 21 | { |
| 22 | /* | 22 | /* |
| 23 | * Enable soft reset to assert RSTOUTn. | 23 | * Enable soft reset to assert RSTOUTn. |
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c index aad3a7a2f830..a560439dcc3c 100644 --- a/arch/arm/mach-mv78xx0/pcie.c +++ b/arch/arm/mach-mv78xx0/pcie.c | |||
| @@ -33,6 +33,12 @@ static struct resource pcie_io_space; | |||
| 33 | static struct resource pcie_mem_space; | 33 | static struct resource pcie_mem_space; |
| 34 | 34 | ||
| 35 | 35 | ||
| 36 | void __init mv78xx0_pcie_id(u32 *dev, u32 *rev) | ||
| 37 | { | ||
| 38 | *dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE); | ||
| 39 | *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE); | ||
| 40 | } | ||
| 41 | |||
| 36 | static void __init mv78xx0_pcie_preinit(void) | 42 | static void __init mv78xx0_pcie_preinit(void) |
| 37 | { | 43 | { |
| 38 | int i; | 44 | int i; |
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c new file mode 100644 index 000000000000..e136b7a03355 --- /dev/null +++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c | |||
| @@ -0,0 +1,88 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-mv78x00/rd78x00-masa-setup.c | ||
| 3 | * | ||
| 4 | * Marvell RD-78x00-mASA Development Board Setup | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/ata_platform.h> | ||
| 15 | #include <linux/mv643xx_eth.h> | ||
| 16 | #include <linux/ethtool.h> | ||
| 17 | #include <mach/mv78xx0.h> | ||
| 18 | #include <asm/mach-types.h> | ||
| 19 | #include <asm/mach/arch.h> | ||
| 20 | #include "common.h" | ||
| 21 | |||
| 22 | static struct mv643xx_eth_platform_data rd78x00_masa_ge00_data = { | ||
| 23 | .phy_addr = MV643XX_ETH_PHY_ADDR(8), | ||
| 24 | }; | ||
| 25 | |||
| 26 | static struct mv643xx_eth_platform_data rd78x00_masa_ge01_data = { | ||
| 27 | .phy_addr = MV643XX_ETH_PHY_ADDR(9), | ||
| 28 | }; | ||
| 29 | |||
| 30 | static struct mv643xx_eth_platform_data rd78x00_masa_ge10_data = { | ||
| 31 | }; | ||
| 32 | |||
| 33 | static struct mv643xx_eth_platform_data rd78x00_masa_ge11_data = { | ||
| 34 | }; | ||
| 35 | |||
| 36 | static struct mv_sata_platform_data rd78x00_masa_sata_data = { | ||
| 37 | .n_ports = 2, | ||
| 38 | }; | ||
| 39 | |||
| 40 | static void __init rd78x00_masa_init(void) | ||
| 41 | { | ||
| 42 | /* | ||
| 43 | * Basic MV78x00 setup. Needs to be called early. | ||
| 44 | */ | ||
| 45 | mv78xx0_init(); | ||
| 46 | |||
| 47 | /* | ||
| 48 | * Partition on-chip peripherals between the two CPU cores. | ||
| 49 | */ | ||
| 50 | if (mv78xx0_core_index() == 0) { | ||
| 51 | mv78xx0_ehci0_init(); | ||
| 52 | mv78xx0_ehci1_init(); | ||
| 53 | mv78xx0_ge00_init(&rd78x00_masa_ge00_data); | ||
| 54 | mv78xx0_ge10_init(&rd78x00_masa_ge10_data); | ||
| 55 | mv78xx0_sata_init(&rd78x00_masa_sata_data); | ||
| 56 | mv78xx0_uart0_init(); | ||
| 57 | mv78xx0_uart2_init(); | ||
| 58 | } else { | ||
| 59 | mv78xx0_ehci2_init(); | ||
| 60 | mv78xx0_ge01_init(&rd78x00_masa_ge01_data); | ||
| 61 | mv78xx0_ge11_init(&rd78x00_masa_ge11_data); | ||
| 62 | mv78xx0_uart1_init(); | ||
| 63 | mv78xx0_uart3_init(); | ||
| 64 | } | ||
| 65 | } | ||
| 66 | |||
| 67 | static int __init rd78x00_pci_init(void) | ||
| 68 | { | ||
| 69 | /* | ||
| 70 | * Assign all PCIe devices to CPU core #0. | ||
| 71 | */ | ||
| 72 | if (machine_is_rd78x00_masa() && mv78xx0_core_index() == 0) | ||
| 73 | mv78xx0_pcie_init(1, 1); | ||
| 74 | |||
| 75 | return 0; | ||
| 76 | } | ||
| 77 | subsys_initcall(rd78x00_pci_init); | ||
| 78 | |||
| 79 | MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board") | ||
| 80 | /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ | ||
| 81 | .phys_io = MV78XX0_REGS_PHYS_BASE, | ||
| 82 | .io_pg_offst = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc, | ||
| 83 | .boot_params = 0x00000100, | ||
| 84 | .init_machine = rd78x00_masa_init, | ||
| 85 | .map_io = mv78xx0_map_io, | ||
| 86 | .init_irq = mv78xx0_init_irq, | ||
| 87 | .timer = &mv78xx0_timer, | ||
| 88 | MACHINE_END | ||
diff --git a/arch/arm/mach-mx1/Kconfig b/arch/arm/mach-mx1/Kconfig index 2b59fc74784f..eb7660f5d4b7 100644 --- a/arch/arm/mach-mx1/Kconfig +++ b/arch/arm/mach-mx1/Kconfig | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | if ARCH_MX1 | 1 | if ARCH_MX1 |
| 2 | 2 | ||
| 3 | comment "MX1 Platforms" | 3 | comment "MX1 platforms:" |
| 4 | 4 | ||
| 5 | config MACH_MXLADS | 5 | config MACH_MXLADS |
| 6 | bool | 6 | bool |
| @@ -11,4 +11,9 @@ config ARCH_MX1ADS | |||
| 11 | help | 11 | help |
| 12 | Say Y here if you are using Motorola MX1ADS/MXLADS boards | 12 | Say Y here if you are using Motorola MX1ADS/MXLADS boards |
| 13 | 13 | ||
| 14 | config MACH_SCB9328 | ||
| 15 | bool "Synertronixx scb9328" | ||
| 16 | help | ||
| 17 | Say Y here if you are using a Synertronixx scb9328 board | ||
| 18 | |||
| 14 | endif | 19 | endif |
diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile index b969719011fa..82f1309568ef 100644 --- a/arch/arm/mach-mx1/Makefile +++ b/arch/arm/mach-mx1/Makefile | |||
| @@ -8,3 +8,4 @@ obj-y += generic.o clock.o devices.o | |||
| 8 | 8 | ||
| 9 | # Specific board support | 9 | # Specific board support |
| 10 | obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o | 10 | obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o |
| 11 | obj-$(CONFIG_MACH_SCB9328) += scb9328.o \ No newline at end of file | ||
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c index 4bcd1ece55f5..0d0f306851d0 100644 --- a/arch/arm/mach-mx1/clock.c +++ b/arch/arm/mach-mx1/clock.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | 25 | ||
| 26 | #include <mach/clock.h> | 26 | #include <mach/clock.h> |
| 27 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 28 | #include <mach/common.h> | ||
| 28 | #include "crm_regs.h" | 29 | #include "crm_regs.h" |
| 29 | 30 | ||
| 30 | static int _clk_enable(struct clk *clk) | 31 | static int _clk_enable(struct clk *clk) |
| @@ -87,33 +88,6 @@ static int _clk_parent_set_rate(struct clk *clk, unsigned long rate) | |||
| 87 | return clk->parent->set_rate(clk->parent, rate); | 88 | return clk->parent->set_rate(clk->parent, rate); |
| 88 | } | 89 | } |
| 89 | 90 | ||
| 90 | /* | ||
| 91 | * get the system pll clock in Hz | ||
| 92 | * | ||
| 93 | * mfi + mfn / (mfd +1) | ||
| 94 | * f = 2 * f_ref * -------------------- | ||
| 95 | * pd + 1 | ||
| 96 | */ | ||
| 97 | static unsigned long mx1_decode_pll(unsigned int pll, u32 f_ref) | ||
| 98 | { | ||
| 99 | unsigned long long ll; | ||
| 100 | unsigned long quot; | ||
| 101 | |||
| 102 | u32 mfi = (pll >> 10) & 0xf; | ||
| 103 | u32 mfn = pll & 0x3ff; | ||
| 104 | u32 mfd = (pll >> 16) & 0x3ff; | ||
| 105 | u32 pd = (pll >> 26) & 0xf; | ||
| 106 | |||
| 107 | mfi = mfi <= 5 ? 5 : mfi; | ||
| 108 | |||
| 109 | ll = 2 * (unsigned long long)f_ref * | ||
| 110 | ((mfi << 16) + (mfn << 16) / (mfd + 1)); | ||
| 111 | quot = (pd + 1) * (1 << 16); | ||
| 112 | ll += quot / 2; | ||
| 113 | do_div(ll, quot); | ||
| 114 | return (unsigned long)ll; | ||
| 115 | } | ||
| 116 | |||
| 117 | static unsigned long clk16m_get_rate(struct clk *clk) | 91 | static unsigned long clk16m_get_rate(struct clk *clk) |
| 118 | { | 92 | { |
| 119 | return 16000000; | 93 | return 16000000; |
| @@ -188,7 +162,7 @@ static struct clk prem_clk = { | |||
| 188 | 162 | ||
| 189 | static unsigned long system_clk_get_rate(struct clk *clk) | 163 | static unsigned long system_clk_get_rate(struct clk *clk) |
| 190 | { | 164 | { |
| 191 | return mx1_decode_pll(__raw_readl(CCM_SPCTL0), | 165 | return mxc_decode_pll(__raw_readl(CCM_SPCTL0), |
| 192 | clk_get_rate(clk->parent)); | 166 | clk_get_rate(clk->parent)); |
| 193 | } | 167 | } |
| 194 | 168 | ||
| @@ -200,7 +174,7 @@ static struct clk system_clk = { | |||
| 200 | 174 | ||
| 201 | static unsigned long mcu_clk_get_rate(struct clk *clk) | 175 | static unsigned long mcu_clk_get_rate(struct clk *clk) |
| 202 | { | 176 | { |
| 203 | return mx1_decode_pll(__raw_readl(CCM_MPCTL0), | 177 | return mxc_decode_pll(__raw_readl(CCM_MPCTL0), |
| 204 | clk_get_rate(clk->parent)); | 178 | clk_get_rate(clk->parent)); |
| 205 | } | 179 | } |
| 206 | 180 | ||
| @@ -488,7 +462,7 @@ static struct clk clko_clk = { | |||
| 488 | }; | 462 | }; |
| 489 | 463 | ||
| 490 | static struct clk dma_clk = { | 464 | static struct clk dma_clk = { |
| 491 | .name = "dma_clk", | 465 | .name = "dma", |
| 492 | .parent = &hclk, | 466 | .parent = &hclk, |
| 493 | .round_rate = _clk_parent_round_rate, | 467 | .round_rate = _clk_parent_round_rate, |
| 494 | .set_rate = _clk_parent_set_rate, | 468 | .set_rate = _clk_parent_set_rate, |
| @@ -539,7 +513,7 @@ static struct clk gpt_clk = { | |||
| 539 | }; | 513 | }; |
| 540 | 514 | ||
| 541 | static struct clk uart_clk = { | 515 | static struct clk uart_clk = { |
| 542 | .name = "uart_clk", | 516 | .name = "uart", |
| 543 | .parent = &perclk[0], | 517 | .parent = &perclk[0], |
| 544 | .round_rate = _clk_parent_round_rate, | 518 | .round_rate = _clk_parent_round_rate, |
| 545 | .set_rate = _clk_parent_set_rate, | 519 | .set_rate = _clk_parent_set_rate, |
| @@ -621,7 +595,7 @@ static struct clk *mxc_clks[] = { | |||
| 621 | &rtc_clk, | 595 | &rtc_clk, |
| 622 | }; | 596 | }; |
| 623 | 597 | ||
| 624 | int __init mxc_clocks_init(unsigned long fref) | 598 | int __init mx1_clocks_init(unsigned long fref) |
| 625 | { | 599 | { |
| 626 | struct clk **clkp; | 600 | struct clk **clkp; |
| 627 | unsigned int reg; | 601 | unsigned int reg; |
| @@ -652,5 +626,7 @@ int __init mxc_clocks_init(unsigned long fref) | |||
| 652 | clk_enable(&hclk); | 626 | clk_enable(&hclk); |
| 653 | clk_enable(&fclk); | 627 | clk_enable(&fclk); |
| 654 | 628 | ||
| 629 | mxc_timer_init(&gpt_clk); | ||
| 630 | |||
| 655 | return 0; | 631 | return 0; |
| 656 | } | 632 | } |
diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c index 686d8d2dbb24..97f42d96d7a1 100644 --- a/arch/arm/mach-mx1/devices.c +++ b/arch/arm/mach-mx1/devices.c | |||
| @@ -23,8 +23,11 @@ | |||
| 23 | #include <linux/init.h> | 23 | #include <linux/init.h> |
| 24 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/gpio.h> | 25 | #include <linux/gpio.h> |
| 26 | #include <mach/irqs.h> | ||
| 26 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 27 | 28 | ||
| 29 | #include "devices.h" | ||
| 30 | |||
| 28 | static struct resource imx_csi_resources[] = { | 31 | static struct resource imx_csi_resources[] = { |
| 29 | [0] = { | 32 | [0] = { |
| 30 | .start = 0x00224000, | 33 | .start = 0x00224000, |
diff --git a/arch/arm/mach-mx1/mx1ads.c b/arch/arm/mach-mx1/mx1ads.c index 2e4b185fe4a9..7ae229bc1b79 100644 --- a/arch/arm/mach-mx1/mx1ads.c +++ b/arch/arm/mach-mx1/mx1ads.c | |||
| @@ -16,15 +16,22 @@ | |||
| 16 | #include <linux/init.h> | 16 | #include <linux/init.h> |
| 17 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
| 18 | #include <linux/mtd/physmap.h> | 18 | #include <linux/mtd/physmap.h> |
| 19 | #include <linux/i2c.h> | ||
| 20 | #include <linux/i2c/pcf857x.h> | ||
| 19 | 21 | ||
| 20 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
| 21 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 22 | #include <asm/mach/time.h> | 24 | #include <asm/mach/time.h> |
| 23 | 25 | ||
| 26 | #include <mach/irqs.h> | ||
| 24 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 25 | #include <mach/common.h> | 28 | #include <mach/common.h> |
| 26 | #include <mach/imx-uart.h> | 29 | #include <mach/imx-uart.h> |
| 27 | #include <mach/iomux-mx1-mx2.h> | 30 | #include <mach/irqs.h> |
| 31 | #ifdef CONFIG_I2C_IMX | ||
| 32 | #include <mach/i2c.h> | ||
| 33 | #endif | ||
| 34 | #include <mach/iomux.h> | ||
| 28 | #include "devices.h" | 35 | #include "devices.h" |
| 29 | 36 | ||
| 30 | /* | 37 | /* |
| @@ -104,6 +111,55 @@ static struct platform_device flash_device = { | |||
| 104 | }; | 111 | }; |
| 105 | 112 | ||
| 106 | /* | 113 | /* |
| 114 | * I2C | ||
| 115 | */ | ||
| 116 | |||
| 117 | #ifdef CONFIG_I2C_IMX | ||
| 118 | static int i2c_pins[] = { | ||
| 119 | PA15_PF_I2C_SDA, | ||
| 120 | PA16_PF_I2C_SCL, | ||
| 121 | }; | ||
| 122 | |||
| 123 | static int i2c_init(struct device *dev) | ||
| 124 | { | ||
| 125 | return mxc_gpio_setup_multiple_pins(i2c_pins, | ||
| 126 | ARRAY_SIZE(i2c_pins), "I2C"); | ||
| 127 | } | ||
| 128 | |||
| 129 | static void i2c_exit(struct device *dev) | ||
| 130 | { | ||
| 131 | mxc_gpio_release_multiple_pins(i2c_pins, | ||
| 132 | ARRAY_SIZE(i2c_pins)); | ||
| 133 | } | ||
| 134 | |||
| 135 | static struct pcf857x_platform_data pcf857x_data[] = { | ||
| 136 | { | ||
| 137 | .gpio_base = 4 * 32, | ||
| 138 | }, { | ||
| 139 | .gpio_base = 4 * 32 + 16, | ||
| 140 | } | ||
| 141 | }; | ||
| 142 | |||
| 143 | static struct imxi2c_platform_data mx1ads_i2c_data = { | ||
| 144 | .bitrate = 100000, | ||
| 145 | .init = i2c_init, | ||
| 146 | .exit = i2c_exit, | ||
| 147 | }; | ||
| 148 | |||
| 149 | static struct i2c_board_info mx1ads_i2c_devices[] = { | ||
| 150 | { | ||
| 151 | I2C_BOARD_INFO("pcf857x", 0x22), | ||
| 152 | .type = "pcf8575", | ||
| 153 | .platform_data = &pcf857x_data[0], | ||
| 154 | }, { | ||
| 155 | I2C_BOARD_INFO("pcf857x", 0x24), | ||
| 156 | .type = "pcf8575", | ||
| 157 | .platform_data = &pcf857x_data[1], | ||
| 158 | }, | ||
| 159 | }; | ||
| 160 | #endif | ||
| 161 | |||
| 162 | /* | ||
| 107 | * Board init | 163 | * Board init |
| 108 | */ | 164 | */ |
| 109 | static void __init mx1ads_init(void) | 165 | static void __init mx1ads_init(void) |
| @@ -114,12 +170,19 @@ static void __init mx1ads_init(void) | |||
| 114 | 170 | ||
| 115 | /* Physmap flash */ | 171 | /* Physmap flash */ |
| 116 | mxc_register_device(&flash_device, &mx1ads_flash_data); | 172 | mxc_register_device(&flash_device, &mx1ads_flash_data); |
| 173 | |||
| 174 | /* I2C */ | ||
| 175 | #ifdef CONFIG_I2C_IMX | ||
| 176 | i2c_register_board_info(0, mx1ads_i2c_devices, | ||
| 177 | ARRAY_SIZE(mx1ads_i2c_devices)); | ||
| 178 | |||
| 179 | mxc_register_device(&imx_i2c_device, &mx1ads_i2c_data); | ||
| 180 | #endif | ||
| 117 | } | 181 | } |
| 118 | 182 | ||
| 119 | static void __init mx1ads_timer_init(void) | 183 | static void __init mx1ads_timer_init(void) |
| 120 | { | 184 | { |
| 121 | mxc_clocks_init(32000); | 185 | mx1_clocks_init(32000); |
| 122 | mxc_timer_init("gpt_clk"); | ||
| 123 | } | 186 | } |
| 124 | 187 | ||
| 125 | struct sys_timer mx1ads_timer = { | 188 | struct sys_timer mx1ads_timer = { |
diff --git a/arch/arm/mach-mx1/scb9328.c b/arch/arm/mach-mx1/scb9328.c new file mode 100644 index 000000000000..0e71f3fa28bf --- /dev/null +++ b/arch/arm/mach-mx1/scb9328.c | |||
| @@ -0,0 +1,160 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-mx1/scb9328.c | ||
| 3 | * | ||
| 4 | * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de> | ||
| 5 | * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/mtd/physmap.h> | ||
| 15 | #include <linux/interrupt.h> | ||
| 16 | #include <linux/dm9000.h> | ||
| 17 | |||
| 18 | #include <asm/mach-types.h> | ||
| 19 | #include <asm/mach/arch.h> | ||
| 20 | #include <asm/mach/time.h> | ||
| 21 | |||
| 22 | #include <mach/common.h> | ||
| 23 | #include <mach/hardware.h> | ||
| 24 | #include <mach/irqs.h> | ||
| 25 | #include <mach/imx-uart.h> | ||
| 26 | #include <mach/iomux.h> | ||
| 27 | |||
| 28 | #include "devices.h" | ||
| 29 | |||
| 30 | /* | ||
| 31 | * This scb9328 has a 32MiB flash | ||
| 32 | */ | ||
| 33 | static struct resource flash_resource = { | ||
| 34 | .start = IMX_CS0_PHYS, | ||
| 35 | .end = IMX_CS0_PHYS + (32 * 1024 * 1024) - 1, | ||
| 36 | .flags = IORESOURCE_MEM, | ||
| 37 | }; | ||
| 38 | |||
| 39 | static struct physmap_flash_data scb_flash_data = { | ||
| 40 | .width = 2, | ||
| 41 | }; | ||
| 42 | |||
| 43 | static struct platform_device scb_flash_device = { | ||
| 44 | .name = "physmap-flash", | ||
| 45 | .id = 0, | ||
| 46 | .dev = { | ||
| 47 | .platform_data = &scb_flash_data, | ||
| 48 | }, | ||
| 49 | .resource = &flash_resource, | ||
| 50 | .num_resources = 1, | ||
| 51 | }; | ||
| 52 | |||
| 53 | /* | ||
| 54 | * scb9328 has a DM9000 network controller | ||
| 55 | * connected to CS5, with 16 bit data path | ||
| 56 | * and interrupt connected to GPIO 3 | ||
| 57 | */ | ||
| 58 | |||
| 59 | /* | ||
| 60 | * internal datapath is fixed 16 bit | ||
| 61 | */ | ||
| 62 | static struct dm9000_plat_data dm9000_platdata = { | ||
| 63 | .flags = DM9000_PLATF_16BITONLY, | ||
| 64 | }; | ||
| 65 | |||
| 66 | /* | ||
| 67 | * the DM9000 drivers wants two defined address spaces | ||
| 68 | * to gain access to address latch registers and the data path. | ||
| 69 | */ | ||
| 70 | static struct resource dm9000x_resources[] = { | ||
| 71 | [0] = { | ||
| 72 | .name = "address area", | ||
| 73 | .start = IMX_CS5_PHYS, | ||
| 74 | .end = IMX_CS5_PHYS + 1, | ||
| 75 | .flags = IORESOURCE_MEM /* address access */ | ||
| 76 | }, | ||
| 77 | [1] = { | ||
| 78 | .name = "data area", | ||
| 79 | .start = IMX_CS5_PHYS + 4, | ||
| 80 | .end = IMX_CS5_PHYS + 5, | ||
| 81 | .flags = IORESOURCE_MEM /* data access */ | ||
| 82 | }, | ||
| 83 | [2] = { | ||
| 84 | .start = IRQ_GPIOC(3), | ||
| 85 | .end = IRQ_GPIOC(3), | ||
| 86 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL | ||
| 87 | }, | ||
| 88 | }; | ||
| 89 | |||
| 90 | static struct platform_device dm9000x_device = { | ||
| 91 | .name = "dm9000", | ||
| 92 | .id = 0, | ||
| 93 | .num_resources = ARRAY_SIZE(dm9000x_resources), | ||
| 94 | .resource = dm9000x_resources, | ||
| 95 | .dev = { | ||
| 96 | .platform_data = &dm9000_platdata, | ||
| 97 | } | ||
| 98 | }; | ||
| 99 | |||
| 100 | static int mxc_uart1_pins[] = { | ||
| 101 | PC9_PF_UART1_CTS, | ||
| 102 | PC10_PF_UART1_RTS, | ||
| 103 | PC11_PF_UART1_TXD, | ||
| 104 | PC12_PF_UART1_RXD, | ||
| 105 | }; | ||
| 106 | |||
| 107 | static int uart1_mxc_init(struct platform_device *pdev) | ||
| 108 | { | ||
| 109 | return mxc_gpio_setup_multiple_pins(mxc_uart1_pins, | ||
| 110 | ARRAY_SIZE(mxc_uart1_pins), "UART1"); | ||
| 111 | } | ||
| 112 | |||
| 113 | static int uart1_mxc_exit(struct platform_device *pdev) | ||
| 114 | { | ||
| 115 | mxc_gpio_release_multiple_pins(mxc_uart1_pins, | ||
| 116 | ARRAY_SIZE(mxc_uart1_pins)); | ||
| 117 | return 0; | ||
| 118 | } | ||
| 119 | |||
| 120 | static struct imxuart_platform_data uart_pdata = { | ||
| 121 | .init = uart1_mxc_init, | ||
| 122 | .exit = uart1_mxc_exit, | ||
| 123 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 124 | }; | ||
| 125 | |||
| 126 | static struct platform_device *devices[] __initdata = { | ||
| 127 | &scb_flash_device, | ||
| 128 | &dm9000x_device, | ||
| 129 | }; | ||
| 130 | |||
| 131 | /* | ||
| 132 | * scb9328_init - Init the CPU card itself | ||
| 133 | */ | ||
| 134 | static void __init scb9328_init(void) | ||
| 135 | { | ||
| 136 | mxc_register_device(&imx_uart1_device, &uart_pdata); | ||
| 137 | |||
| 138 | printk(KERN_INFO"Scb9328: Adding devices\n"); | ||
| 139 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 140 | } | ||
| 141 | |||
| 142 | static void __init scb9328_timer_init(void) | ||
| 143 | { | ||
| 144 | mx1_clocks_init(32000); | ||
| 145 | } | ||
| 146 | |||
| 147 | static struct sys_timer scb9328_timer = { | ||
| 148 | .init = scb9328_timer_init, | ||
| 149 | }; | ||
| 150 | |||
| 151 | MACHINE_START(SCB9328, "Synertronixx scb9328") | ||
| 152 | /* Sascha Hauer */ | ||
| 153 | .phys_io = 0x00200000, | ||
| 154 | .io_pg_offst = ((0xe0200000) >> 18) & 0xfffc, | ||
| 155 | .boot_params = 0x08000100, | ||
| 156 | .map_io = mxc_map_io, | ||
| 157 | .init_irq = mxc_init_irq, | ||
| 158 | .timer = &scb9328_timer, | ||
| 159 | .init_machine = scb9328_init, | ||
| 160 | MACHINE_END | ||
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig index 1eaa97cb716d..42a788842f49 100644 --- a/arch/arm/mach-mx2/Kconfig +++ b/arch/arm/mach-mx2/Kconfig | |||
| @@ -1,14 +1,22 @@ | |||
| 1 | comment "MX2 family CPU support" | 1 | if ARCH_MX2 |
| 2 | depends on ARCH_MX2 | 2 | |
| 3 | choice | ||
| 4 | prompt "CPUs:" | ||
| 5 | default MACH_MX21 | ||
| 6 | |||
| 7 | config MACH_MX21 | ||
| 8 | bool "i.MX21 support" | ||
| 9 | help | ||
| 10 | This enables support for Freescale's MX2 based i.MX21 processor. | ||
| 3 | 11 | ||
| 4 | config MACH_MX27 | 12 | config MACH_MX27 |
| 5 | bool "i.MX27 support" | 13 | bool "i.MX27 support" |
| 6 | depends on ARCH_MX2 | ||
| 7 | help | 14 | help |
| 8 | This enables support for Freescale's MX2 based i.MX27 processor. | 15 | This enables support for Freescale's MX2 based i.MX27 processor. |
| 9 | 16 | ||
| 10 | comment "MX2 Platforms" | 17 | endchoice |
| 11 | depends on ARCH_MX2 | 18 | |
| 19 | comment "MX2 platforms:" | ||
| 12 | 20 | ||
| 13 | config MACH_MX27ADS | 21 | config MACH_MX27ADS |
| 14 | bool "MX27ADS platform" | 22 | bool "MX27ADS platform" |
| @@ -37,3 +45,5 @@ config MACH_PCM970_BASEBOARD | |||
| 37 | PCM970 evaluation board. | 45 | PCM970 evaluation board. |
| 38 | 46 | ||
| 39 | endchoice | 47 | endchoice |
| 48 | |||
| 49 | endif | ||
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile index 382d86080e86..6e1a2bffc812 100644 --- a/arch/arm/mach-mx2/Makefile +++ b/arch/arm/mach-mx2/Makefile | |||
| @@ -6,6 +6,8 @@ | |||
| 6 | 6 | ||
| 7 | obj-y := system.o generic.o devices.o serial.o | 7 | obj-y := system.o generic.o devices.o serial.o |
| 8 | 8 | ||
| 9 | obj-$(CONFIG_MACH_MX21) += clock_imx21.o | ||
| 10 | |||
| 9 | obj-$(CONFIG_MACH_MX27) += cpu_imx27.o | 11 | obj-$(CONFIG_MACH_MX27) += cpu_imx27.o |
| 10 | obj-$(CONFIG_MACH_MX27) += clock_imx27.o | 12 | obj-$(CONFIG_MACH_MX27) += clock_imx27.o |
| 11 | 13 | ||
diff --git a/arch/arm/mach-mx2/Makefile.boot b/arch/arm/mach-mx2/Makefile.boot index 696831dcd485..e867398a8fdb 100644 --- a/arch/arm/mach-mx2/Makefile.boot +++ b/arch/arm/mach-mx2/Makefile.boot | |||
| @@ -1,3 +1,7 @@ | |||
| 1 | zreladdr-y := 0xA0008000 | 1 | zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000 |
| 2 | params_phys-y := 0xA0000100 | 2 | params_phys-$(CONFIG_MACH_MX21) := 0xC0000100 |
| 3 | initrd_phys-y := 0xA0800000 | 3 | initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000 |
| 4 | |||
| 5 | zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000 | ||
| 6 | params_phys-$(CONFIG_MACH_MX27) := 0xA0000100 | ||
| 7 | initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000 | ||
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c new file mode 100644 index 000000000000..2dee5c87614c --- /dev/null +++ b/arch/arm/mach-mx2/clock_imx21.c | |||
| @@ -0,0 +1,984 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or | ||
| 7 | * modify it under the terms of the GNU General Public License | ||
| 8 | * as published by the Free Software Foundation; either version 2 | ||
| 9 | * of the License, or (at your option) any later version. | ||
| 10 | * This program is distributed in the hope that it will be useful, | ||
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 13 | * GNU General Public License for more details. | ||
| 14 | * | ||
| 15 | * You should have received a copy of the GNU General Public License | ||
| 16 | * along with this program; if not, write to the Free Software | ||
| 17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 18 | * MA 02110-1301, USA. | ||
| 19 | */ | ||
| 20 | |||
| 21 | #include <linux/clk.h> | ||
| 22 | #include <linux/io.h> | ||
| 23 | #include <linux/module.h> | ||
| 24 | |||
| 25 | #include <mach/clock.h> | ||
| 26 | #include <mach/common.h> | ||
| 27 | #include <asm/clkdev.h> | ||
| 28 | #include <asm/div64.h> | ||
| 29 | |||
| 30 | #include "crm_regs.h" | ||
| 31 | |||
| 32 | static int _clk_enable(struct clk *clk) | ||
| 33 | { | ||
| 34 | u32 reg; | ||
| 35 | |||
| 36 | reg = __raw_readl(clk->enable_reg); | ||
| 37 | reg |= 1 << clk->enable_shift; | ||
| 38 | __raw_writel(reg, clk->enable_reg); | ||
| 39 | return 0; | ||
| 40 | } | ||
| 41 | |||
| 42 | static void _clk_disable(struct clk *clk) | ||
| 43 | { | ||
| 44 | u32 reg; | ||
| 45 | |||
| 46 | reg = __raw_readl(clk->enable_reg); | ||
| 47 | reg &= ~(1 << clk->enable_shift); | ||
| 48 | __raw_writel(reg, clk->enable_reg); | ||
| 49 | } | ||
| 50 | |||
| 51 | static int _clk_spll_enable(struct clk *clk) | ||
| 52 | { | ||
| 53 | u32 reg; | ||
| 54 | |||
| 55 | reg = __raw_readl(CCM_CSCR); | ||
| 56 | reg |= CCM_CSCR_SPEN; | ||
| 57 | __raw_writel(reg, CCM_CSCR); | ||
| 58 | |||
| 59 | while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0) | ||
| 60 | ; | ||
| 61 | return 0; | ||
| 62 | } | ||
| 63 | |||
| 64 | static void _clk_spll_disable(struct clk *clk) | ||
| 65 | { | ||
| 66 | u32 reg; | ||
| 67 | |||
| 68 | reg = __raw_readl(CCM_CSCR); | ||
| 69 | reg &= ~CCM_CSCR_SPEN; | ||
| 70 | __raw_writel(reg, CCM_CSCR); | ||
| 71 | } | ||
| 72 | |||
| 73 | |||
| 74 | #define CSCR() (__raw_readl(CCM_CSCR)) | ||
| 75 | #define PCDR0() (__raw_readl(CCM_PCDR0)) | ||
| 76 | #define PCDR1() (__raw_readl(CCM_PCDR1)) | ||
| 77 | |||
| 78 | static unsigned long _clk_perclkx_round_rate(struct clk *clk, | ||
| 79 | unsigned long rate) | ||
| 80 | { | ||
| 81 | u32 div; | ||
| 82 | unsigned long parent_rate; | ||
| 83 | |||
| 84 | parent_rate = clk_get_rate(clk->parent); | ||
| 85 | |||
| 86 | div = parent_rate / rate; | ||
| 87 | if (parent_rate % rate) | ||
| 88 | div++; | ||
| 89 | |||
| 90 | if (div > 64) | ||
| 91 | div = 64; | ||
| 92 | |||
| 93 | return parent_rate / div; | ||
| 94 | } | ||
| 95 | |||
| 96 | static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate) | ||
| 97 | { | ||
| 98 | u32 reg; | ||
| 99 | u32 div; | ||
| 100 | unsigned long parent_rate; | ||
| 101 | |||
| 102 | parent_rate = clk_get_rate(clk->parent); | ||
| 103 | |||
| 104 | if (clk->id < 0 || clk->id > 3) | ||
| 105 | return -EINVAL; | ||
| 106 | |||
| 107 | div = parent_rate / rate; | ||
| 108 | if (div > 64 || div < 1 || ((parent_rate / div) != rate)) | ||
| 109 | return -EINVAL; | ||
| 110 | div--; | ||
| 111 | |||
| 112 | reg = | ||
| 113 | __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK << | ||
| 114 | (clk->id << 3)); | ||
| 115 | reg |= div << (clk->id << 3); | ||
| 116 | __raw_writel(reg, CCM_PCDR1); | ||
| 117 | |||
| 118 | return 0; | ||
| 119 | } | ||
| 120 | |||
| 121 | static unsigned long _clk_usb_recalc(struct clk *clk) | ||
| 122 | { | ||
| 123 | unsigned long usb_pdf; | ||
| 124 | unsigned long parent_rate; | ||
| 125 | |||
| 126 | parent_rate = clk_get_rate(clk->parent); | ||
| 127 | |||
| 128 | usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET; | ||
| 129 | |||
| 130 | return parent_rate / (usb_pdf + 1U); | ||
| 131 | } | ||
| 132 | |||
| 133 | static unsigned long _clk_ssix_recalc(struct clk *clk, unsigned long pdf) | ||
| 134 | { | ||
| 135 | unsigned long parent_rate; | ||
| 136 | |||
| 137 | parent_rate = clk_get_rate(clk->parent); | ||
| 138 | |||
| 139 | pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */ | ||
| 140 | |||
| 141 | return 2UL * parent_rate / pdf; | ||
| 142 | } | ||
| 143 | |||
| 144 | static unsigned long _clk_ssi1_recalc(struct clk *clk) | ||
| 145 | { | ||
| 146 | return _clk_ssix_recalc(clk, | ||
| 147 | (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK) | ||
| 148 | >> CCM_PCDR0_SSI1BAUDDIV_OFFSET); | ||
| 149 | } | ||
| 150 | |||
| 151 | static unsigned long _clk_ssi2_recalc(struct clk *clk) | ||
| 152 | { | ||
| 153 | return _clk_ssix_recalc(clk, | ||
| 154 | (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >> | ||
| 155 | CCM_PCDR0_SSI2BAUDDIV_OFFSET); | ||
| 156 | } | ||
| 157 | |||
| 158 | static unsigned long _clk_nfc_recalc(struct clk *clk) | ||
| 159 | { | ||
| 160 | unsigned long nfc_pdf; | ||
| 161 | unsigned long parent_rate; | ||
| 162 | |||
| 163 | parent_rate = clk_get_rate(clk->parent); | ||
| 164 | |||
| 165 | nfc_pdf = (PCDR0() & CCM_PCDR0_NFCDIV_MASK) | ||
| 166 | >> CCM_PCDR0_NFCDIV_OFFSET; | ||
| 167 | |||
| 168 | return parent_rate / (nfc_pdf + 1); | ||
| 169 | } | ||
| 170 | |||
| 171 | static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate) | ||
| 172 | { | ||
| 173 | return clk->parent->round_rate(clk->parent, rate); | ||
| 174 | } | ||
| 175 | |||
| 176 | static int _clk_parent_set_rate(struct clk *clk, unsigned long rate) | ||
| 177 | { | ||
| 178 | return clk->parent->set_rate(clk->parent, rate); | ||
| 179 | } | ||
| 180 | |||
| 181 | static unsigned long external_high_reference; /* in Hz */ | ||
| 182 | |||
| 183 | static unsigned long get_high_reference_clock_rate(struct clk *clk) | ||
| 184 | { | ||
| 185 | return external_high_reference; | ||
| 186 | } | ||
| 187 | |||
| 188 | /* | ||
| 189 | * the high frequency external clock reference | ||
| 190 | * Default case is 26MHz. | ||
| 191 | */ | ||
| 192 | static struct clk ckih_clk = { | ||
| 193 | .get_rate = get_high_reference_clock_rate, | ||
| 194 | }; | ||
| 195 | |||
| 196 | static unsigned long external_low_reference; /* in Hz */ | ||
| 197 | |||
| 198 | static unsigned long get_low_reference_clock_rate(struct clk *clk) | ||
| 199 | { | ||
| 200 | return external_low_reference; | ||
| 201 | } | ||
| 202 | |||
| 203 | /* | ||
| 204 | * the low frequency external clock reference | ||
| 205 | * Default case is 32.768kHz. | ||
| 206 | */ | ||
| 207 | static struct clk ckil_clk = { | ||
| 208 | .get_rate = get_low_reference_clock_rate, | ||
| 209 | }; | ||
| 210 | |||
| 211 | |||
| 212 | static unsigned long _clk_fpm_recalc(struct clk *clk) | ||
| 213 | { | ||
| 214 | return clk_get_rate(clk->parent) * 512; | ||
| 215 | } | ||
| 216 | |||
| 217 | /* Output of frequency pre multiplier */ | ||
| 218 | static struct clk fpm_clk = { | ||
| 219 | .parent = &ckil_clk, | ||
| 220 | .get_rate = _clk_fpm_recalc, | ||
| 221 | }; | ||
| 222 | |||
| 223 | static unsigned long get_mpll_clk(struct clk *clk) | ||
| 224 | { | ||
| 225 | uint32_t reg; | ||
| 226 | unsigned long ref_clk; | ||
| 227 | unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0; | ||
| 228 | unsigned long long temp; | ||
| 229 | |||
| 230 | ref_clk = clk_get_rate(clk->parent); | ||
| 231 | |||
| 232 | reg = __raw_readl(CCM_MPCTL0); | ||
| 233 | pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET; | ||
| 234 | mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET; | ||
| 235 | mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET; | ||
| 236 | mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET; | ||
| 237 | |||
| 238 | mfi = (mfi <= 5) ? 5 : mfi; | ||
| 239 | temp = 2LL * ref_clk * mfn; | ||
| 240 | do_div(temp, mfd + 1); | ||
| 241 | temp = 2LL * ref_clk * mfi + temp; | ||
| 242 | do_div(temp, pdf + 1); | ||
| 243 | |||
| 244 | return (unsigned long)temp; | ||
| 245 | } | ||
| 246 | |||
| 247 | static struct clk mpll_clk = { | ||
| 248 | .parent = &ckih_clk, | ||
| 249 | .get_rate = get_mpll_clk, | ||
| 250 | }; | ||
| 251 | |||
| 252 | static unsigned long _clk_fclk_get_rate(struct clk *clk) | ||
| 253 | { | ||
| 254 | unsigned long parent_rate; | ||
| 255 | u32 div; | ||
| 256 | |||
| 257 | div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET; | ||
| 258 | parent_rate = clk_get_rate(clk->parent); | ||
| 259 | |||
| 260 | return parent_rate / (div+1); | ||
| 261 | } | ||
| 262 | |||
| 263 | static struct clk fclk_clk = { | ||
| 264 | .parent = &mpll_clk, | ||
| 265 | .get_rate = _clk_fclk_get_rate | ||
| 266 | }; | ||
| 267 | |||
| 268 | static unsigned long get_spll_clk(struct clk *clk) | ||
| 269 | { | ||
| 270 | uint32_t reg; | ||
| 271 | unsigned long ref_clk; | ||
| 272 | unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0; | ||
| 273 | unsigned long long temp; | ||
| 274 | |||
| 275 | ref_clk = clk_get_rate(clk->parent); | ||
| 276 | |||
| 277 | reg = __raw_readl(CCM_SPCTL0); | ||
| 278 | pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET; | ||
| 279 | mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET; | ||
| 280 | mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET; | ||
| 281 | mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET; | ||
| 282 | |||
| 283 | mfi = (mfi <= 5) ? 5 : mfi; | ||
| 284 | temp = 2LL * ref_clk * mfn; | ||
| 285 | do_div(temp, mfd + 1); | ||
| 286 | temp = 2LL * ref_clk * mfi + temp; | ||
| 287 | do_div(temp, pdf + 1); | ||
| 288 | |||
| 289 | return (unsigned long)temp; | ||
| 290 | } | ||
| 291 | |||
| 292 | static struct clk spll_clk = { | ||
| 293 | .parent = &ckih_clk, | ||
| 294 | .get_rate = get_spll_clk, | ||
| 295 | .enable = _clk_spll_enable, | ||
| 296 | .disable = _clk_spll_disable, | ||
| 297 | }; | ||
| 298 | |||
| 299 | static unsigned long get_hclk_clk(struct clk *clk) | ||
| 300 | { | ||
| 301 | unsigned long rate; | ||
| 302 | unsigned long bclk_pdf; | ||
| 303 | |||
| 304 | bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK) | ||
| 305 | >> CCM_CSCR_BCLK_OFFSET; | ||
| 306 | |||
| 307 | rate = clk_get_rate(clk->parent); | ||
| 308 | return rate / (bclk_pdf + 1); | ||
| 309 | } | ||
| 310 | |||
| 311 | static struct clk hclk_clk = { | ||
| 312 | .parent = &fclk_clk, | ||
| 313 | .get_rate = get_hclk_clk, | ||
| 314 | }; | ||
| 315 | |||
| 316 | static unsigned long get_ipg_clk(struct clk *clk) | ||
| 317 | { | ||
| 318 | unsigned long rate; | ||
| 319 | unsigned long ipg_pdf; | ||
| 320 | |||
| 321 | ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET; | ||
| 322 | |||
| 323 | rate = clk_get_rate(clk->parent); | ||
| 324 | return rate / (ipg_pdf + 1); | ||
| 325 | } | ||
| 326 | |||
| 327 | static struct clk ipg_clk = { | ||
| 328 | .parent = &hclk_clk, | ||
| 329 | .get_rate = get_ipg_clk, | ||
| 330 | }; | ||
| 331 | |||
| 332 | static unsigned long _clk_perclkx_recalc(struct clk *clk) | ||
| 333 | { | ||
| 334 | unsigned long perclk_pdf; | ||
| 335 | unsigned long parent_rate; | ||
| 336 | |||
| 337 | parent_rate = clk_get_rate(clk->parent); | ||
| 338 | |||
| 339 | if (clk->id < 0 || clk->id > 3) | ||
| 340 | return 0; | ||
| 341 | |||
| 342 | perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK; | ||
| 343 | |||
| 344 | return parent_rate / (perclk_pdf + 1); | ||
| 345 | } | ||
| 346 | |||
| 347 | static struct clk per_clk[] = { | ||
| 348 | { | ||
| 349 | .id = 0, | ||
| 350 | .parent = &mpll_clk, | ||
| 351 | .get_rate = _clk_perclkx_recalc, | ||
| 352 | }, { | ||
| 353 | .id = 1, | ||
| 354 | .parent = &mpll_clk, | ||
| 355 | .get_rate = _clk_perclkx_recalc, | ||
| 356 | }, { | ||
| 357 | .id = 2, | ||
| 358 | .parent = &mpll_clk, | ||
| 359 | .round_rate = _clk_perclkx_round_rate, | ||
| 360 | .set_rate = _clk_perclkx_set_rate, | ||
| 361 | .get_rate = _clk_perclkx_recalc, | ||
| 362 | /* Enable/Disable done via lcd_clkc[1] */ | ||
| 363 | }, { | ||
| 364 | .id = 3, | ||
| 365 | .parent = &mpll_clk, | ||
| 366 | .round_rate = _clk_perclkx_round_rate, | ||
| 367 | .set_rate = _clk_perclkx_set_rate, | ||
| 368 | .get_rate = _clk_perclkx_recalc, | ||
| 369 | /* Enable/Disable done via csi_clk[1] */ | ||
| 370 | }, | ||
| 371 | }; | ||
| 372 | |||
| 373 | static struct clk uart_ipg_clk[]; | ||
| 374 | |||
| 375 | static struct clk uart_clk[] = { | ||
| 376 | { | ||
| 377 | .id = 0, | ||
| 378 | .parent = &per_clk[0], | ||
| 379 | .secondary = &uart_ipg_clk[0], | ||
| 380 | }, { | ||
| 381 | .id = 1, | ||
| 382 | .parent = &per_clk[0], | ||
| 383 | .secondary = &uart_ipg_clk[1], | ||
| 384 | }, { | ||
| 385 | .id = 2, | ||
| 386 | .parent = &per_clk[0], | ||
| 387 | .secondary = &uart_ipg_clk[2], | ||
| 388 | }, { | ||
| 389 | .id = 3, | ||
| 390 | .parent = &per_clk[0], | ||
| 391 | .secondary = &uart_ipg_clk[3], | ||
| 392 | }, | ||
| 393 | }; | ||
| 394 | |||
| 395 | static struct clk uart_ipg_clk[] = { | ||
| 396 | { | ||
| 397 | .id = 0, | ||
| 398 | .parent = &ipg_clk, | ||
| 399 | .enable = _clk_enable, | ||
| 400 | .enable_reg = CCM_PCCR_UART1_REG, | ||
| 401 | .enable_shift = CCM_PCCR_UART1_OFFSET, | ||
| 402 | .disable = _clk_disable, | ||
| 403 | }, { | ||
| 404 | .id = 1, | ||
| 405 | .parent = &ipg_clk, | ||
| 406 | .enable = _clk_enable, | ||
| 407 | .enable_reg = CCM_PCCR_UART2_REG, | ||
| 408 | .enable_shift = CCM_PCCR_UART2_OFFSET, | ||
| 409 | .disable = _clk_disable, | ||
| 410 | }, { | ||
| 411 | .id = 2, | ||
| 412 | .parent = &ipg_clk, | ||
| 413 | .enable = _clk_enable, | ||
| 414 | .enable_reg = CCM_PCCR_UART3_REG, | ||
| 415 | .enable_shift = CCM_PCCR_UART3_OFFSET, | ||
| 416 | .disable = _clk_disable, | ||
| 417 | }, { | ||
| 418 | .id = 3, | ||
| 419 | .parent = &ipg_clk, | ||
| 420 | .enable = _clk_enable, | ||
| 421 | .enable_reg = CCM_PCCR_UART4_REG, | ||
| 422 | .enable_shift = CCM_PCCR_UART4_OFFSET, | ||
| 423 | .disable = _clk_disable, | ||
| 424 | }, | ||
| 425 | }; | ||
| 426 | |||
| 427 | static struct clk gpt_ipg_clk[]; | ||
| 428 | |||
| 429 | static struct clk gpt_clk[] = { | ||
| 430 | { | ||
| 431 | .id = 0, | ||
| 432 | .parent = &per_clk[0], | ||
| 433 | .secondary = &gpt_ipg_clk[0], | ||
| 434 | }, { | ||
| 435 | .id = 1, | ||
| 436 | .parent = &per_clk[0], | ||
| 437 | .secondary = &gpt_ipg_clk[1], | ||
| 438 | }, { | ||
| 439 | .id = 2, | ||
| 440 | .parent = &per_clk[0], | ||
| 441 | .secondary = &gpt_ipg_clk[2], | ||
| 442 | }, | ||
| 443 | }; | ||
| 444 | |||
| 445 | static struct clk gpt_ipg_clk[] = { | ||
| 446 | { | ||
| 447 | .id = 0, | ||
| 448 | .parent = &ipg_clk, | ||
| 449 | .enable = _clk_enable, | ||
| 450 | .enable_reg = CCM_PCCR_GPT1_REG, | ||
| 451 | .enable_shift = CCM_PCCR_GPT1_OFFSET, | ||
| 452 | .disable = _clk_disable, | ||
| 453 | }, { | ||
| 454 | .id = 1, | ||
| 455 | .parent = &ipg_clk, | ||
| 456 | .enable = _clk_enable, | ||
| 457 | .enable_reg = CCM_PCCR_GPT2_REG, | ||
| 458 | .enable_shift = CCM_PCCR_GPT2_OFFSET, | ||
| 459 | .disable = _clk_disable, | ||
| 460 | }, { | ||
| 461 | .id = 2, | ||
| 462 | .parent = &ipg_clk, | ||
| 463 | .enable = _clk_enable, | ||
| 464 | .enable_reg = CCM_PCCR_GPT3_REG, | ||
| 465 | .enable_shift = CCM_PCCR_GPT3_OFFSET, | ||
| 466 | .disable = _clk_disable, | ||
| 467 | }, | ||
| 468 | }; | ||
| 469 | |||
| 470 | static struct clk pwm_clk[] = { | ||
| 471 | { | ||
| 472 | .parent = &per_clk[0], | ||
| 473 | .secondary = &pwm_clk[1], | ||
| 474 | }, { | ||
| 475 | .parent = &ipg_clk, | ||
| 476 | .enable = _clk_enable, | ||
| 477 | .enable_reg = CCM_PCCR_PWM_REG, | ||
| 478 | .enable_shift = CCM_PCCR_PWM_OFFSET, | ||
| 479 | .disable = _clk_disable, | ||
| 480 | }, | ||
| 481 | }; | ||
| 482 | |||
| 483 | static struct clk sdhc_ipg_clk[]; | ||
| 484 | |||
| 485 | static struct clk sdhc_clk[] = { | ||
| 486 | { | ||
| 487 | .id = 0, | ||
| 488 | .parent = &per_clk[1], | ||
| 489 | .secondary = &sdhc_ipg_clk[0], | ||
| 490 | }, { | ||
| 491 | .id = 1, | ||
| 492 | .parent = &per_clk[1], | ||
| 493 | .secondary = &sdhc_ipg_clk[1], | ||
| 494 | }, | ||
| 495 | }; | ||
| 496 | |||
| 497 | static struct clk sdhc_ipg_clk[] = { | ||
| 498 | { | ||
| 499 | .id = 0, | ||
| 500 | .parent = &ipg_clk, | ||
| 501 | .enable = _clk_enable, | ||
| 502 | .enable_reg = CCM_PCCR_SDHC1_REG, | ||
| 503 | .enable_shift = CCM_PCCR_SDHC1_OFFSET, | ||
| 504 | .disable = _clk_disable, | ||
| 505 | }, { | ||
| 506 | .id = 1, | ||
| 507 | .parent = &ipg_clk, | ||
| 508 | .enable = _clk_enable, | ||
| 509 | .enable_reg = CCM_PCCR_SDHC2_REG, | ||
| 510 | .enable_shift = CCM_PCCR_SDHC2_OFFSET, | ||
| 511 | .disable = _clk_disable, | ||
| 512 | }, | ||
| 513 | }; | ||
| 514 | |||
| 515 | static struct clk cspi_ipg_clk[]; | ||
| 516 | |||
| 517 | static struct clk cspi_clk[] = { | ||
| 518 | { | ||
| 519 | .id = 0, | ||
| 520 | .parent = &per_clk[1], | ||
| 521 | .secondary = &cspi_ipg_clk[0], | ||
| 522 | }, { | ||
| 523 | .id = 1, | ||
| 524 | .parent = &per_clk[1], | ||
| 525 | .secondary = &cspi_ipg_clk[1], | ||
| 526 | }, { | ||
| 527 | .id = 2, | ||
| 528 | .parent = &per_clk[1], | ||
| 529 | .secondary = &cspi_ipg_clk[2], | ||
| 530 | }, | ||
| 531 | }; | ||
| 532 | |||
| 533 | static struct clk cspi_ipg_clk[] = { | ||
| 534 | { | ||
| 535 | .id = 0, | ||
| 536 | .parent = &ipg_clk, | ||
| 537 | .enable = _clk_enable, | ||
| 538 | .enable_reg = CCM_PCCR_CSPI1_REG, | ||
| 539 | .enable_shift = CCM_PCCR_CSPI1_OFFSET, | ||
| 540 | .disable = _clk_disable, | ||
| 541 | }, { | ||
| 542 | .id = 1, | ||
| 543 | .parent = &ipg_clk, | ||
| 544 | .enable = _clk_enable, | ||
| 545 | .enable_reg = CCM_PCCR_CSPI2_REG, | ||
| 546 | .enable_shift = CCM_PCCR_CSPI2_OFFSET, | ||
| 547 | .disable = _clk_disable, | ||
| 548 | }, { | ||
| 549 | .id = 3, | ||
| 550 | .parent = &ipg_clk, | ||
| 551 | .enable = _clk_enable, | ||
| 552 | .enable_reg = CCM_PCCR_CSPI3_REG, | ||
| 553 | .enable_shift = CCM_PCCR_CSPI3_OFFSET, | ||
| 554 | .disable = _clk_disable, | ||
| 555 | }, | ||
| 556 | }; | ||
| 557 | |||
| 558 | static struct clk lcdc_clk[] = { | ||
| 559 | { | ||
| 560 | .parent = &per_clk[2], | ||
| 561 | .secondary = &lcdc_clk[1], | ||
| 562 | .round_rate = _clk_parent_round_rate, | ||
| 563 | .set_rate = _clk_parent_set_rate, | ||
| 564 | }, { | ||
| 565 | .parent = &ipg_clk, | ||
| 566 | .secondary = &lcdc_clk[2], | ||
| 567 | .enable = _clk_enable, | ||
| 568 | .enable_reg = CCM_PCCR_LCDC_REG, | ||
| 569 | .enable_shift = CCM_PCCR_LCDC_OFFSET, | ||
| 570 | .disable = _clk_disable, | ||
| 571 | }, { | ||
| 572 | .parent = &hclk_clk, | ||
| 573 | .enable = _clk_enable, | ||
| 574 | .enable_reg = CCM_PCCR_HCLK_LCDC_REG, | ||
| 575 | .enable_shift = CCM_PCCR_HCLK_LCDC_OFFSET, | ||
| 576 | .disable = _clk_disable, | ||
| 577 | }, | ||
| 578 | }; | ||
| 579 | |||
| 580 | static struct clk csi_clk[] = { | ||
| 581 | { | ||
| 582 | .parent = &per_clk[3], | ||
| 583 | .secondary = &csi_clk[1], | ||
| 584 | .round_rate = _clk_parent_round_rate, | ||
| 585 | .set_rate = _clk_parent_set_rate, | ||
| 586 | }, { | ||
| 587 | .parent = &hclk_clk, | ||
| 588 | .enable = _clk_enable, | ||
| 589 | .enable_reg = CCM_PCCR_HCLK_CSI_REG, | ||
| 590 | .enable_shift = CCM_PCCR_HCLK_CSI_OFFSET, | ||
| 591 | .disable = _clk_disable, | ||
| 592 | }, | ||
| 593 | }; | ||
| 594 | |||
| 595 | static struct clk usb_clk[] = { | ||
| 596 | { | ||
| 597 | .parent = &spll_clk, | ||
| 598 | .get_rate = _clk_usb_recalc, | ||
| 599 | .enable = _clk_enable, | ||
| 600 | .enable_reg = CCM_PCCR_USBOTG_REG, | ||
| 601 | .enable_shift = CCM_PCCR_USBOTG_OFFSET, | ||
| 602 | .disable = _clk_disable, | ||
| 603 | }, { | ||
| 604 | .parent = &hclk_clk, | ||
| 605 | .enable = _clk_enable, | ||
| 606 | .enable_reg = CCM_PCCR_HCLK_USBOTG_REG, | ||
| 607 | .enable_shift = CCM_PCCR_HCLK_USBOTG_OFFSET, | ||
| 608 | .disable = _clk_disable, | ||
| 609 | } | ||
| 610 | }; | ||
| 611 | |||
| 612 | static struct clk ssi_ipg_clk[]; | ||
| 613 | |||
| 614 | static struct clk ssi_clk[] = { | ||
| 615 | { | ||
| 616 | .id = 0, | ||
| 617 | .parent = &mpll_clk, | ||
| 618 | .secondary = &ssi_ipg_clk[0], | ||
| 619 | .get_rate = _clk_ssi1_recalc, | ||
| 620 | .enable = _clk_enable, | ||
| 621 | .enable_reg = CCM_PCCR_SSI1_BAUD_REG, | ||
| 622 | .enable_shift = CCM_PCCR_SSI1_BAUD_OFFSET, | ||
| 623 | .disable = _clk_disable, | ||
| 624 | }, { | ||
| 625 | .id = 1, | ||
| 626 | .parent = &mpll_clk, | ||
| 627 | .secondary = &ssi_ipg_clk[1], | ||
| 628 | .get_rate = _clk_ssi2_recalc, | ||
| 629 | .enable = _clk_enable, | ||
| 630 | .enable_reg = CCM_PCCR_SSI2_BAUD_REG, | ||
| 631 | .enable_shift = CCM_PCCR_SSI2_BAUD_OFFSET, | ||
| 632 | .disable = _clk_disable, | ||
| 633 | }, | ||
| 634 | }; | ||
| 635 | |||
| 636 | static struct clk ssi_ipg_clk[] = { | ||
| 637 | { | ||
| 638 | .id = 0, | ||
| 639 | .parent = &ipg_clk, | ||
| 640 | .enable = _clk_enable, | ||
| 641 | .enable_reg = CCM_PCCR_SSI1_REG, | ||
| 642 | .enable_shift = CCM_PCCR_SSI1_IPG_OFFSET, | ||
| 643 | .disable = _clk_disable, | ||
| 644 | }, { | ||
| 645 | .id = 1, | ||
| 646 | .parent = &ipg_clk, | ||
| 647 | .enable = _clk_enable, | ||
| 648 | .enable_reg = CCM_PCCR_SSI2_REG, | ||
| 649 | .enable_shift = CCM_PCCR_SSI2_IPG_OFFSET, | ||
| 650 | .disable = _clk_disable, | ||
| 651 | }, | ||
| 652 | }; | ||
| 653 | |||
| 654 | |||
| 655 | static struct clk nfc_clk = { | ||
| 656 | .parent = &fclk_clk, | ||
| 657 | .get_rate = _clk_nfc_recalc, | ||
| 658 | .enable = _clk_enable, | ||
| 659 | .enable_reg = CCM_PCCR_NFC_REG, | ||
| 660 | .enable_shift = CCM_PCCR_NFC_OFFSET, | ||
| 661 | .disable = _clk_disable, | ||
| 662 | }; | ||
| 663 | |||
| 664 | static struct clk dma_clk[] = { | ||
| 665 | { | ||
| 666 | .parent = &hclk_clk, | ||
| 667 | .enable = _clk_enable, | ||
| 668 | .enable_reg = CCM_PCCR_DMA_REG, | ||
| 669 | .enable_shift = CCM_PCCR_DMA_OFFSET, | ||
| 670 | .disable = _clk_disable, | ||
| 671 | .secondary = &dma_clk[1], | ||
| 672 | }, { | ||
| 673 | .enable = _clk_enable, | ||
| 674 | .enable_reg = CCM_PCCR_HCLK_DMA_REG, | ||
| 675 | .enable_shift = CCM_PCCR_HCLK_DMA_OFFSET, | ||
| 676 | .disable = _clk_disable, | ||
| 677 | }, | ||
| 678 | }; | ||
| 679 | |||
| 680 | static struct clk brom_clk = { | ||
| 681 | .parent = &hclk_clk, | ||
| 682 | .enable = _clk_enable, | ||
| 683 | .enable_reg = CCM_PCCR_HCLK_BROM_REG, | ||
| 684 | .enable_shift = CCM_PCCR_HCLK_BROM_OFFSET, | ||
| 685 | .disable = _clk_disable, | ||
| 686 | }; | ||
| 687 | |||
| 688 | static struct clk emma_clk[] = { | ||
| 689 | { | ||
| 690 | .parent = &hclk_clk, | ||
| 691 | .enable = _clk_enable, | ||
| 692 | .enable_reg = CCM_PCCR_EMMA_REG, | ||
| 693 | .enable_shift = CCM_PCCR_EMMA_OFFSET, | ||
| 694 | .disable = _clk_disable, | ||
| 695 | .secondary = &emma_clk[1], | ||
| 696 | }, { | ||
| 697 | .enable = _clk_enable, | ||
| 698 | .enable_reg = CCM_PCCR_HCLK_EMMA_REG, | ||
| 699 | .enable_shift = CCM_PCCR_HCLK_EMMA_OFFSET, | ||
| 700 | .disable = _clk_disable, | ||
| 701 | } | ||
| 702 | }; | ||
| 703 | |||
| 704 | static struct clk slcdc_clk[] = { | ||
| 705 | { | ||
| 706 | .parent = &hclk_clk, | ||
| 707 | .enable = _clk_enable, | ||
| 708 | .enable_reg = CCM_PCCR_SLCDC_REG, | ||
| 709 | .enable_shift = CCM_PCCR_SLCDC_OFFSET, | ||
| 710 | .disable = _clk_disable, | ||
| 711 | .secondary = &slcdc_clk[1], | ||
| 712 | }, { | ||
| 713 | .enable = _clk_enable, | ||
| 714 | .enable_reg = CCM_PCCR_HCLK_SLCDC_REG, | ||
| 715 | .enable_shift = CCM_PCCR_HCLK_SLCDC_OFFSET, | ||
| 716 | .disable = _clk_disable, | ||
| 717 | } | ||
| 718 | }; | ||
| 719 | |||
| 720 | static struct clk wdog_clk = { | ||
| 721 | .parent = &ipg_clk, | ||
| 722 | .enable = _clk_enable, | ||
| 723 | .enable_reg = CCM_PCCR_WDT_REG, | ||
| 724 | .enable_shift = CCM_PCCR_WDT_OFFSET, | ||
| 725 | .disable = _clk_disable, | ||
| 726 | }; | ||
| 727 | |||
| 728 | static struct clk gpio_clk = { | ||
| 729 | .parent = &ipg_clk, | ||
| 730 | .enable = _clk_enable, | ||
| 731 | .enable_reg = CCM_PCCR_GPIO_REG, | ||
| 732 | .enable_shift = CCM_PCCR_GPIO_OFFSET, | ||
| 733 | .disable = _clk_disable, | ||
| 734 | }; | ||
| 735 | |||
| 736 | static struct clk i2c_clk = { | ||
| 737 | .id = 0, | ||
| 738 | .parent = &ipg_clk, | ||
| 739 | .enable = _clk_enable, | ||
| 740 | .enable_reg = CCM_PCCR_I2C1_REG, | ||
| 741 | .enable_shift = CCM_PCCR_I2C1_OFFSET, | ||
| 742 | .disable = _clk_disable, | ||
| 743 | }; | ||
| 744 | |||
| 745 | static struct clk kpp_clk = { | ||
| 746 | .parent = &ipg_clk, | ||
| 747 | .enable = _clk_enable, | ||
| 748 | .enable_reg = CCM_PCCR_KPP_REG, | ||
| 749 | .enable_shift = CCM_PCCR_KPP_OFFSET, | ||
| 750 | .disable = _clk_disable, | ||
| 751 | }; | ||
| 752 | |||
| 753 | static struct clk owire_clk = { | ||
| 754 | .parent = &ipg_clk, | ||
| 755 | .enable = _clk_enable, | ||
| 756 | .enable_reg = CCM_PCCR_OWIRE_REG, | ||
| 757 | .enable_shift = CCM_PCCR_OWIRE_OFFSET, | ||
| 758 | .disable = _clk_disable, | ||
| 759 | }; | ||
| 760 | |||
| 761 | static struct clk rtc_clk = { | ||
| 762 | .parent = &ipg_clk, | ||
| 763 | .enable = _clk_enable, | ||
| 764 | .enable_reg = CCM_PCCR_RTC_REG, | ||
| 765 | .enable_shift = CCM_PCCR_RTC_OFFSET, | ||
| 766 | .disable = _clk_disable, | ||
| 767 | }; | ||
| 768 | |||
| 769 | static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate) | ||
| 770 | { | ||
| 771 | u32 div; | ||
| 772 | unsigned long parent_rate; | ||
| 773 | |||
| 774 | parent_rate = clk_get_rate(clk->parent); | ||
| 775 | div = parent_rate / rate; | ||
| 776 | if (parent_rate % rate) | ||
| 777 | div++; | ||
| 778 | |||
| 779 | if (div > 8) | ||
| 780 | div = 8; | ||
| 781 | |||
| 782 | return parent_rate / div; | ||
| 783 | } | ||
| 784 | |||
| 785 | static int _clk_clko_set_rate(struct clk *clk, unsigned long rate) | ||
| 786 | { | ||
| 787 | u32 reg; | ||
| 788 | u32 div; | ||
| 789 | unsigned long parent_rate; | ||
| 790 | |||
| 791 | parent_rate = clk_get_rate(clk->parent); | ||
| 792 | |||
| 793 | div = parent_rate / rate; | ||
| 794 | |||
| 795 | if (div > 8 || div < 1 || ((parent_rate / div) != rate)) | ||
| 796 | return -EINVAL; | ||
| 797 | div--; | ||
| 798 | |||
| 799 | reg = __raw_readl(CCM_PCDR0); | ||
| 800 | |||
| 801 | if (clk->parent == &usb_clk[0]) { | ||
| 802 | reg &= ~CCM_PCDR0_48MDIV_MASK; | ||
| 803 | reg |= div << CCM_PCDR0_48MDIV_OFFSET; | ||
| 804 | } | ||
| 805 | __raw_writel(reg, CCM_PCDR0); | ||
| 806 | |||
| 807 | return 0; | ||
| 808 | } | ||
| 809 | |||
| 810 | static unsigned long _clk_clko_recalc(struct clk *clk) | ||
| 811 | { | ||
| 812 | u32 div = 0; | ||
| 813 | unsigned long parent_rate; | ||
| 814 | |||
| 815 | parent_rate = clk_get_rate(clk->parent); | ||
| 816 | |||
| 817 | if (clk->parent == &usb_clk[0]) /* 48M */ | ||
| 818 | div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_48MDIV_MASK | ||
| 819 | >> CCM_PCDR0_48MDIV_OFFSET; | ||
| 820 | div++; | ||
| 821 | |||
| 822 | return parent_rate / div; | ||
| 823 | } | ||
| 824 | |||
| 825 | static struct clk clko_clk; | ||
| 826 | |||
| 827 | static int _clk_clko_set_parent(struct clk *clk, struct clk *parent) | ||
| 828 | { | ||
| 829 | u32 reg; | ||
| 830 | |||
| 831 | reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK; | ||
| 832 | |||
| 833 | if (parent == &ckil_clk) | ||
| 834 | reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 835 | else if (parent == &fpm_clk) | ||
| 836 | reg |= 1 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 837 | else if (parent == &ckih_clk) | ||
| 838 | reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 839 | else if (parent == mpll_clk.parent) | ||
| 840 | reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 841 | else if (parent == spll_clk.parent) | ||
| 842 | reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 843 | else if (parent == &mpll_clk) | ||
| 844 | reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 845 | else if (parent == &spll_clk) | ||
| 846 | reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 847 | else if (parent == &fclk_clk) | ||
| 848 | reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 849 | else if (parent == &hclk_clk) | ||
| 850 | reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 851 | else if (parent == &ipg_clk) | ||
| 852 | reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 853 | else if (parent == &per_clk[0]) | ||
| 854 | reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 855 | else if (parent == &per_clk[1]) | ||
| 856 | reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 857 | else if (parent == &per_clk[2]) | ||
| 858 | reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 859 | else if (parent == &per_clk[3]) | ||
| 860 | reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 861 | else if (parent == &ssi_clk[0]) | ||
| 862 | reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 863 | else if (parent == &ssi_clk[1]) | ||
| 864 | reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 865 | else if (parent == &nfc_clk) | ||
| 866 | reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 867 | else if (parent == &usb_clk[0]) | ||
| 868 | reg |= 0x14 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 869 | else if (parent == &clko_clk) | ||
| 870 | reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 871 | else | ||
| 872 | return -EINVAL; | ||
| 873 | |||
| 874 | __raw_writel(reg, CCM_CCSR); | ||
| 875 | |||
| 876 | return 0; | ||
| 877 | } | ||
| 878 | |||
| 879 | static struct clk clko_clk = { | ||
| 880 | .get_rate = _clk_clko_recalc, | ||
| 881 | .set_rate = _clk_clko_set_rate, | ||
| 882 | .round_rate = _clk_clko_round_rate, | ||
| 883 | .set_parent = _clk_clko_set_parent, | ||
| 884 | }; | ||
| 885 | |||
| 886 | |||
| 887 | #define _REGISTER_CLOCK(d, n, c) \ | ||
| 888 | { \ | ||
| 889 | .dev_id = d, \ | ||
| 890 | .con_id = n, \ | ||
| 891 | .clk = &c, \ | ||
| 892 | }, | ||
| 893 | static struct clk_lookup lookups[] __initdata = { | ||
| 894 | /* It's unlikely that any driver wants one of them directly: | ||
| 895 | _REGISTER_CLOCK(NULL, "ckih", ckih_clk) | ||
| 896 | _REGISTER_CLOCK(NULL, "ckil", ckil_clk) | ||
| 897 | _REGISTER_CLOCK(NULL, "fpm", fpm_clk) | ||
| 898 | _REGISTER_CLOCK(NULL, "mpll", mpll_clk) | ||
| 899 | _REGISTER_CLOCK(NULL, "spll", spll_clk) | ||
| 900 | _REGISTER_CLOCK(NULL, "fclk", fclk_clk) | ||
| 901 | _REGISTER_CLOCK(NULL, "hclk", hclk_clk) | ||
| 902 | _REGISTER_CLOCK(NULL, "ipg", ipg_clk) | ||
| 903 | */ | ||
| 904 | _REGISTER_CLOCK(NULL, "perclk1", per_clk[0]) | ||
| 905 | _REGISTER_CLOCK(NULL, "perclk2", per_clk[1]) | ||
| 906 | _REGISTER_CLOCK(NULL, "perclk3", per_clk[2]) | ||
| 907 | _REGISTER_CLOCK(NULL, "perclk4", per_clk[3]) | ||
| 908 | _REGISTER_CLOCK(NULL, "clko", clko_clk) | ||
| 909 | _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0]) | ||
| 910 | _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1]) | ||
| 911 | _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2]) | ||
| 912 | _REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[3]) | ||
| 913 | _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[0]) | ||
| 914 | _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[1]) | ||
| 915 | _REGISTER_CLOCK(NULL, "gpt1", gpt_clk[2]) | ||
| 916 | _REGISTER_CLOCK(NULL, "pwm", pwm_clk[0]) | ||
| 917 | _REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0]) | ||
| 918 | _REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1]) | ||
| 919 | _REGISTER_CLOCK(NULL, "cspi1", cspi_clk[0]) | ||
| 920 | _REGISTER_CLOCK(NULL, "cspi2", cspi_clk[1]) | ||
| 921 | _REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2]) | ||
| 922 | _REGISTER_CLOCK(NULL, "lcdc", lcdc_clk[0]) | ||
| 923 | _REGISTER_CLOCK(NULL, "csi", csi_clk[0]) | ||
| 924 | _REGISTER_CLOCK(NULL, "usb", usb_clk[0]) | ||
| 925 | _REGISTER_CLOCK(NULL, "ssi1", ssi_clk[0]) | ||
| 926 | _REGISTER_CLOCK(NULL, "ssi2", ssi_clk[1]) | ||
| 927 | _REGISTER_CLOCK(NULL, "nfc", nfc_clk) | ||
| 928 | _REGISTER_CLOCK(NULL, "dma", dma_clk[0]) | ||
| 929 | _REGISTER_CLOCK(NULL, "brom", brom_clk) | ||
| 930 | _REGISTER_CLOCK(NULL, "emma", emma_clk[0]) | ||
| 931 | _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0]) | ||
| 932 | _REGISTER_CLOCK(NULL, "wdog", wdog_clk) | ||
| 933 | _REGISTER_CLOCK(NULL, "gpio", gpio_clk) | ||
| 934 | _REGISTER_CLOCK(NULL, "i2c", i2c_clk) | ||
| 935 | _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk) | ||
| 936 | _REGISTER_CLOCK(NULL, "owire", owire_clk) | ||
| 937 | _REGISTER_CLOCK(NULL, "rtc", rtc_clk) | ||
| 938 | }; | ||
| 939 | |||
| 940 | /* | ||
| 941 | * must be called very early to get information about the | ||
| 942 | * available clock rate when the timer framework starts | ||
| 943 | */ | ||
| 944 | int __init mx21_clocks_init(unsigned long lref, unsigned long href) | ||
| 945 | { | ||
| 946 | int i; | ||
| 947 | u32 cscr; | ||
| 948 | |||
| 949 | external_low_reference = lref; | ||
| 950 | external_high_reference = href; | ||
| 951 | |||
| 952 | /* detect clock reference for both system PLL */ | ||
| 953 | cscr = CSCR(); | ||
| 954 | if (cscr & CCM_CSCR_MCU) | ||
| 955 | mpll_clk.parent = &ckih_clk; | ||
| 956 | else | ||
| 957 | mpll_clk.parent = &fpm_clk; | ||
| 958 | |||
| 959 | if (cscr & CCM_CSCR_SP) | ||
| 960 | spll_clk.parent = &ckih_clk; | ||
| 961 | else | ||
| 962 | spll_clk.parent = &fpm_clk; | ||
| 963 | |||
| 964 | for (i = 0; i < ARRAY_SIZE(lookups); i++) | ||
| 965 | clkdev_add(&lookups[i]); | ||
| 966 | |||
| 967 | /* Turn off all clock gates */ | ||
| 968 | __raw_writel(0, CCM_PCCR0); | ||
| 969 | __raw_writel(CCM_PCCR_GPT1_MASK, CCM_PCCR1); | ||
| 970 | |||
| 971 | /* This turns of the serial PLL as well */ | ||
| 972 | spll_clk.disable(&spll_clk); | ||
| 973 | |||
| 974 | /* This will propagate to all children and init all the clock rates. */ | ||
| 975 | clk_enable(&per_clk[0]); | ||
| 976 | clk_enable(&gpio_clk); | ||
| 977 | |||
| 978 | #ifdef CONFIG_DEBUG_LL_CONSOLE | ||
| 979 | clk_enable(&uart_clk[0]); | ||
| 980 | #endif | ||
| 981 | |||
| 982 | mxc_timer_init(&gpt_clk[0]); | ||
| 983 | return 0; | ||
| 984 | } | ||
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c index c69896d011a1..3f7280c490f0 100644 --- a/arch/arm/mach-mx2/clock_imx27.c +++ b/arch/arm/mach-mx2/clock_imx27.c | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de |
| 4 | * Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com | ||
| 4 | * | 5 | * |
| 5 | * This program is free software; you can redistribute it and/or | 6 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License | 7 | * modify it under the terms of the GNU General Public License |
| @@ -20,23 +21,60 @@ | |||
| 20 | #include <linux/clk.h> | 21 | #include <linux/clk.h> |
| 21 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 22 | #include <linux/module.h> | 23 | #include <linux/module.h> |
| 23 | #include <linux/spinlock.h> | ||
| 24 | 24 | ||
| 25 | #include <mach/clock.h> | 25 | #include <asm/clkdev.h> |
| 26 | #include <mach/common.h> | ||
| 27 | #include <asm/div64.h> | 26 | #include <asm/div64.h> |
| 28 | 27 | ||
| 29 | #include "crm_regs.h" | 28 | #include <mach/clock.h> |
| 30 | 29 | #include <mach/common.h> | |
| 31 | static struct clk ckil_clk; | 30 | #include <mach/hardware.h> |
| 32 | static struct clk mpll_clk; | 31 | |
| 33 | static struct clk mpll_main_clk[]; | 32 | /* Register offsets */ |
| 34 | static struct clk spll_clk; | 33 | #define CCM_CSCR (IO_ADDRESS(CCM_BASE_ADDR) + 0x0) |
| 35 | 34 | #define CCM_MPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x4) | |
| 36 | static int _clk_enable(struct clk *clk) | 35 | #define CCM_MPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x8) |
| 36 | #define CCM_SPCTL0 (IO_ADDRESS(CCM_BASE_ADDR) + 0xC) | ||
| 37 | #define CCM_SPCTL1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x10) | ||
| 38 | #define CCM_OSC26MCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x14) | ||
| 39 | #define CCM_PCDR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x18) | ||
| 40 | #define CCM_PCDR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x1c) | ||
| 41 | #define CCM_PCCR0 (IO_ADDRESS(CCM_BASE_ADDR) + 0x20) | ||
| 42 | #define CCM_PCCR1 (IO_ADDRESS(CCM_BASE_ADDR) + 0x24) | ||
| 43 | #define CCM_CCSR (IO_ADDRESS(CCM_BASE_ADDR) + 0x28) | ||
| 44 | #define CCM_PMCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x2c) | ||
| 45 | #define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) | ||
| 46 | #define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) | ||
| 47 | |||
| 48 | #define CCM_CSCR_UPDATE_DIS (1 << 31) | ||
| 49 | #define CCM_CSCR_SSI2 (1 << 23) | ||
| 50 | #define CCM_CSCR_SSI1 (1 << 22) | ||
| 51 | #define CCM_CSCR_VPU (1 << 21) | ||
| 52 | #define CCM_CSCR_MSHC (1 << 20) | ||
| 53 | #define CCM_CSCR_SPLLRES (1 << 19) | ||
| 54 | #define CCM_CSCR_MPLLRES (1 << 18) | ||
| 55 | #define CCM_CSCR_SP (1 << 17) | ||
| 56 | #define CCM_CSCR_MCU (1 << 16) | ||
| 57 | #define CCM_CSCR_OSC26MDIV (1 << 4) | ||
| 58 | #define CCM_CSCR_OSC26M (1 << 3) | ||
| 59 | #define CCM_CSCR_FPM (1 << 2) | ||
| 60 | #define CCM_CSCR_SPEN (1 << 1) | ||
| 61 | #define CCM_CSCR_MPEN (1 << 0) | ||
| 62 | |||
| 63 | /* i.MX27 TO 2+ */ | ||
| 64 | #define CCM_CSCR_ARM_SRC (1 << 15) | ||
| 65 | |||
| 66 | #define CCM_SPCTL1_LF (1 << 15) | ||
| 67 | #define CCM_SPCTL1_BRMO (1 << 6) | ||
| 68 | |||
| 69 | static struct clk mpll_main1_clk, mpll_main2_clk; | ||
| 70 | |||
| 71 | static int clk_pccr_enable(struct clk *clk) | ||
| 37 | { | 72 | { |
| 38 | unsigned long reg; | 73 | unsigned long reg; |
| 39 | 74 | ||
| 75 | if (!clk->enable_reg) | ||
| 76 | return 0; | ||
| 77 | |||
| 40 | reg = __raw_readl(clk->enable_reg); | 78 | reg = __raw_readl(clk->enable_reg); |
| 41 | reg |= 1 << clk->enable_shift; | 79 | reg |= 1 << clk->enable_shift; |
| 42 | __raw_writel(reg, clk->enable_reg); | 80 | __raw_writel(reg, clk->enable_reg); |
| @@ -44,16 +82,19 @@ static int _clk_enable(struct clk *clk) | |||
| 44 | return 0; | 82 | return 0; |
| 45 | } | 83 | } |
| 46 | 84 | ||
| 47 | static void _clk_disable(struct clk *clk) | 85 | static void clk_pccr_disable(struct clk *clk) |
| 48 | { | 86 | { |
| 49 | unsigned long reg; | 87 | unsigned long reg; |
| 50 | 88 | ||
| 89 | if (!clk->enable_reg) | ||
| 90 | return; | ||
| 91 | |||
| 51 | reg = __raw_readl(clk->enable_reg); | 92 | reg = __raw_readl(clk->enable_reg); |
| 52 | reg &= ~(1 << clk->enable_shift); | 93 | reg &= ~(1 << clk->enable_shift); |
| 53 | __raw_writel(reg, clk->enable_reg); | 94 | __raw_writel(reg, clk->enable_reg); |
| 54 | } | 95 | } |
| 55 | 96 | ||
| 56 | static int _clk_spll_enable(struct clk *clk) | 97 | static int clk_spll_enable(struct clk *clk) |
| 57 | { | 98 | { |
| 58 | unsigned long reg; | 99 | unsigned long reg; |
| 59 | 100 | ||
| @@ -61,13 +102,12 @@ static int _clk_spll_enable(struct clk *clk) | |||
| 61 | reg |= CCM_CSCR_SPEN; | 102 | reg |= CCM_CSCR_SPEN; |
| 62 | __raw_writel(reg, CCM_CSCR); | 103 | __raw_writel(reg, CCM_CSCR); |
| 63 | 104 | ||
| 64 | while ((__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF) == 0) | 105 | while (!(__raw_readl(CCM_SPCTL1) & CCM_SPCTL1_LF)); |
| 65 | ; | ||
| 66 | 106 | ||
| 67 | return 0; | 107 | return 0; |
| 68 | } | 108 | } |
| 69 | 109 | ||
| 70 | static void _clk_spll_disable(struct clk *clk) | 110 | static void clk_spll_disable(struct clk *clk) |
| 71 | { | 111 | { |
| 72 | unsigned long reg; | 112 | unsigned long reg; |
| 73 | 113 | ||
| @@ -76,192 +116,30 @@ static void _clk_spll_disable(struct clk *clk) | |||
| 76 | __raw_writel(reg, CCM_CSCR); | 116 | __raw_writel(reg, CCM_CSCR); |
| 77 | } | 117 | } |
| 78 | 118 | ||
| 79 | static void _clk_pccr01_enable(unsigned long mask0, unsigned long mask1) | 119 | static int clk_cpu_set_parent(struct clk *clk, struct clk *parent) |
| 80 | { | ||
| 81 | unsigned long reg; | ||
| 82 | |||
| 83 | reg = __raw_readl(CCM_PCCR0); | ||
| 84 | reg |= mask0; | ||
| 85 | __raw_writel(reg, CCM_PCCR0); | ||
| 86 | |||
| 87 | reg = __raw_readl(CCM_PCCR1); | ||
| 88 | reg |= mask1; | ||
| 89 | __raw_writel(reg, CCM_PCCR1); | ||
| 90 | |||
| 91 | } | ||
| 92 | |||
| 93 | static void _clk_pccr01_disable(unsigned long mask0, unsigned long mask1) | ||
| 94 | { | ||
| 95 | unsigned long reg; | ||
| 96 | |||
| 97 | reg = __raw_readl(CCM_PCCR0); | ||
| 98 | reg &= ~mask0; | ||
| 99 | __raw_writel(reg, CCM_PCCR0); | ||
| 100 | |||
| 101 | reg = __raw_readl(CCM_PCCR1); | ||
| 102 | reg &= ~mask1; | ||
| 103 | __raw_writel(reg, CCM_PCCR1); | ||
| 104 | } | ||
| 105 | |||
| 106 | static void _clk_pccr10_enable(unsigned long mask1, unsigned long mask0) | ||
| 107 | { | ||
| 108 | unsigned long reg; | ||
| 109 | |||
| 110 | reg = __raw_readl(CCM_PCCR1); | ||
| 111 | reg |= mask1; | ||
| 112 | __raw_writel(reg, CCM_PCCR1); | ||
| 113 | |||
| 114 | reg = __raw_readl(CCM_PCCR0); | ||
| 115 | reg |= mask0; | ||
| 116 | __raw_writel(reg, CCM_PCCR0); | ||
| 117 | } | ||
| 118 | |||
| 119 | static void _clk_pccr10_disable(unsigned long mask1, unsigned long mask0) | ||
| 120 | { | ||
| 121 | unsigned long reg; | ||
| 122 | |||
| 123 | reg = __raw_readl(CCM_PCCR1); | ||
| 124 | reg &= ~mask1; | ||
| 125 | __raw_writel(reg, CCM_PCCR1); | ||
| 126 | |||
| 127 | reg = __raw_readl(CCM_PCCR0); | ||
| 128 | reg &= ~mask0; | ||
| 129 | __raw_writel(reg, CCM_PCCR0); | ||
| 130 | } | ||
| 131 | |||
| 132 | static int _clk_dma_enable(struct clk *clk) | ||
| 133 | { | ||
| 134 | _clk_pccr01_enable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK); | ||
| 135 | |||
| 136 | return 0; | ||
| 137 | } | ||
| 138 | |||
| 139 | static void _clk_dma_disable(struct clk *clk) | ||
| 140 | { | ||
| 141 | _clk_pccr01_disable(CCM_PCCR0_DMA_MASK, CCM_PCCR1_HCLK_DMA_MASK); | ||
| 142 | } | ||
| 143 | |||
| 144 | static int _clk_rtic_enable(struct clk *clk) | ||
| 145 | { | ||
| 146 | _clk_pccr01_enable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK); | ||
| 147 | |||
| 148 | return 0; | ||
| 149 | } | ||
| 150 | |||
| 151 | static void _clk_rtic_disable(struct clk *clk) | ||
| 152 | { | ||
| 153 | _clk_pccr01_disable(CCM_PCCR0_RTIC_MASK, CCM_PCCR1_HCLK_RTIC_MASK); | ||
| 154 | } | ||
| 155 | |||
| 156 | static int _clk_emma_enable(struct clk *clk) | ||
| 157 | { | ||
| 158 | _clk_pccr01_enable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK); | ||
| 159 | |||
| 160 | return 0; | ||
| 161 | } | ||
| 162 | |||
| 163 | static void _clk_emma_disable(struct clk *clk) | ||
| 164 | { | ||
| 165 | _clk_pccr01_disable(CCM_PCCR0_EMMA_MASK, CCM_PCCR1_HCLK_EMMA_MASK); | ||
| 166 | } | ||
| 167 | |||
| 168 | static int _clk_slcdc_enable(struct clk *clk) | ||
| 169 | { | ||
| 170 | _clk_pccr01_enable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK); | ||
| 171 | |||
| 172 | return 0; | ||
| 173 | } | ||
| 174 | |||
| 175 | static void _clk_slcdc_disable(struct clk *clk) | ||
| 176 | { | ||
| 177 | _clk_pccr01_disable(CCM_PCCR0_SLCDC_MASK, CCM_PCCR1_HCLK_SLCDC_MASK); | ||
| 178 | } | ||
| 179 | |||
| 180 | static int _clk_fec_enable(struct clk *clk) | ||
| 181 | { | ||
| 182 | _clk_pccr01_enable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK); | ||
| 183 | |||
| 184 | return 0; | ||
| 185 | } | ||
| 186 | |||
| 187 | static void _clk_fec_disable(struct clk *clk) | ||
| 188 | { | ||
| 189 | _clk_pccr01_disable(CCM_PCCR0_FEC_MASK, CCM_PCCR1_HCLK_FEC_MASK); | ||
| 190 | } | ||
| 191 | |||
| 192 | static int _clk_vpu_enable(struct clk *clk) | ||
| 193 | { | ||
| 194 | unsigned long reg; | ||
| 195 | |||
| 196 | reg = __raw_readl(CCM_PCCR1); | ||
| 197 | reg |= CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK; | ||
| 198 | __raw_writel(reg, CCM_PCCR1); | ||
| 199 | |||
| 200 | return 0; | ||
| 201 | } | ||
| 202 | |||
| 203 | static void _clk_vpu_disable(struct clk *clk) | ||
| 204 | { | 120 | { |
| 205 | unsigned long reg; | 121 | int cscr = __raw_readl(CCM_CSCR); |
| 206 | |||
| 207 | reg = __raw_readl(CCM_PCCR1); | ||
| 208 | reg &= ~(CCM_PCCR1_VPU_BAUD_MASK | CCM_PCCR1_HCLK_VPU_MASK); | ||
| 209 | __raw_writel(reg, CCM_PCCR1); | ||
| 210 | } | ||
| 211 | |||
| 212 | static int _clk_sahara2_enable(struct clk *clk) | ||
| 213 | { | ||
| 214 | _clk_pccr01_enable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK); | ||
| 215 | |||
| 216 | return 0; | ||
| 217 | } | ||
| 218 | |||
| 219 | static void _clk_sahara2_disable(struct clk *clk) | ||
| 220 | { | ||
| 221 | _clk_pccr01_disable(CCM_PCCR0_SAHARA_MASK, CCM_PCCR1_HCLK_SAHARA_MASK); | ||
| 222 | } | ||
| 223 | |||
| 224 | static int _clk_mstick1_enable(struct clk *clk) | ||
| 225 | { | ||
| 226 | _clk_pccr10_enable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK); | ||
| 227 | |||
| 228 | return 0; | ||
| 229 | } | ||
| 230 | |||
| 231 | static void _clk_mstick1_disable(struct clk *clk) | ||
| 232 | { | ||
| 233 | _clk_pccr10_disable(CCM_PCCR1_MSHC_BAUD_MASK, CCM_PCCR0_MSHC_MASK); | ||
| 234 | } | ||
| 235 | |||
| 236 | #define CSCR() (__raw_readl(CCM_CSCR)) | ||
| 237 | #define PCDR0() (__raw_readl(CCM_PCDR0)) | ||
| 238 | #define PCDR1() (__raw_readl(CCM_PCDR1)) | ||
| 239 | |||
| 240 | static int _clk_cpu_set_parent(struct clk *clk, struct clk *parent) | ||
| 241 | { | ||
| 242 | int cscr = CSCR(); | ||
| 243 | 122 | ||
| 244 | if (clk->parent == parent) | 123 | if (clk->parent == parent) |
| 245 | return 0; | 124 | return 0; |
| 246 | 125 | ||
| 247 | if (mx27_revision() >= CHIP_REV_2_0) { | 126 | if (mx27_revision() >= CHIP_REV_2_0) { |
| 248 | if (parent == &mpll_main_clk[0]) { | 127 | if (parent == &mpll_main1_clk) { |
| 249 | cscr |= CCM_CSCR_ARM_SRC; | 128 | cscr |= CCM_CSCR_ARM_SRC; |
| 250 | } else { | 129 | } else { |
| 251 | if (parent == &mpll_main_clk[1]) | 130 | if (parent == &mpll_main2_clk) |
| 252 | cscr &= ~CCM_CSCR_ARM_SRC; | 131 | cscr &= ~CCM_CSCR_ARM_SRC; |
| 253 | else | 132 | else |
| 254 | return -EINVAL; | 133 | return -EINVAL; |
| 255 | } | 134 | } |
| 256 | __raw_writel(cscr, CCM_CSCR); | 135 | __raw_writel(cscr, CCM_CSCR); |
| 257 | } else | 136 | clk->parent = parent; |
| 258 | return -ENODEV; | 137 | return 0; |
| 259 | 138 | } | |
| 260 | clk->parent = parent; | 139 | return -ENODEV; |
| 261 | return 0; | ||
| 262 | } | 140 | } |
| 263 | 141 | ||
| 264 | static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate) | 142 | static unsigned long round_rate_cpu(struct clk *clk, unsigned long rate) |
| 265 | { | 143 | { |
| 266 | int div; | 144 | int div; |
| 267 | unsigned long parent_rate; | 145 | unsigned long parent_rate; |
| @@ -278,7 +156,7 @@ static unsigned long _clk_cpu_round_rate(struct clk *clk, unsigned long rate) | |||
| 278 | return parent_rate / div; | 156 | return parent_rate / div; |
| 279 | } | 157 | } |
| 280 | 158 | ||
| 281 | static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) | 159 | static int set_rate_cpu(struct clk *clk, unsigned long rate) |
| 282 | { | 160 | { |
| 283 | unsigned int div; | 161 | unsigned int div; |
| 284 | uint32_t reg; | 162 | uint32_t reg; |
| @@ -295,19 +173,18 @@ static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) | |||
| 295 | 173 | ||
| 296 | reg = __raw_readl(CCM_CSCR); | 174 | reg = __raw_readl(CCM_CSCR); |
| 297 | if (mx27_revision() >= CHIP_REV_2_0) { | 175 | if (mx27_revision() >= CHIP_REV_2_0) { |
| 298 | reg &= ~CCM_CSCR_ARM_MASK; | 176 | reg &= ~(3 << 12); |
| 299 | reg |= div << CCM_CSCR_ARM_OFFSET; | 177 | reg |= div << 12; |
| 300 | reg &= ~0x06; | 178 | reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN); |
| 301 | __raw_writel(reg | 0x80000000, CCM_CSCR); | 179 | __raw_writel(reg | CCM_CSCR_UPDATE_DIS, CCM_CSCR); |
| 302 | } else { | 180 | } else { |
| 303 | printk(KERN_ERR "Cant set CPU frequency!\n"); | 181 | printk(KERN_ERR "Can't set CPU frequency!\n"); |
| 304 | } | 182 | } |
| 305 | 183 | ||
| 306 | return 0; | 184 | return 0; |
| 307 | } | 185 | } |
| 308 | 186 | ||
| 309 | static unsigned long _clk_perclkx_round_rate(struct clk *clk, | 187 | static unsigned long round_rate_per(struct clk *clk, unsigned long rate) |
| 310 | unsigned long rate) | ||
| 311 | { | 188 | { |
| 312 | u32 div; | 189 | u32 div; |
| 313 | unsigned long parent_rate; | 190 | unsigned long parent_rate; |
| @@ -324,7 +201,7 @@ static unsigned long _clk_perclkx_round_rate(struct clk *clk, | |||
| 324 | return parent_rate / div; | 201 | return parent_rate / div; |
| 325 | } | 202 | } |
| 326 | 203 | ||
| 327 | static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate) | 204 | static int set_rate_per(struct clk *clk, unsigned long rate) |
| 328 | { | 205 | { |
| 329 | u32 reg; | 206 | u32 reg; |
| 330 | u32 div; | 207 | u32 div; |
| @@ -340,84 +217,65 @@ static int _clk_perclkx_set_rate(struct clk *clk, unsigned long rate) | |||
| 340 | return -EINVAL; | 217 | return -EINVAL; |
| 341 | div--; | 218 | div--; |
| 342 | 219 | ||
| 343 | reg = | 220 | reg = __raw_readl(CCM_PCDR1) & ~(0x3f << (clk->id << 3)); |
| 344 | __raw_readl(CCM_PCDR1) & ~(CCM_PCDR1_PERDIV1_MASK << | ||
| 345 | (clk->id << 3)); | ||
| 346 | reg |= div << (clk->id << 3); | 221 | reg |= div << (clk->id << 3); |
| 347 | __raw_writel(reg, CCM_PCDR1); | 222 | __raw_writel(reg, CCM_PCDR1); |
| 348 | 223 | ||
| 349 | return 0; | 224 | return 0; |
| 350 | } | 225 | } |
| 351 | 226 | ||
| 352 | static unsigned long _clk_usb_recalc(struct clk *clk) | 227 | static unsigned long get_rate_usb(struct clk *clk) |
| 353 | { | 228 | { |
| 354 | unsigned long usb_pdf; | 229 | unsigned long usb_pdf; |
| 355 | unsigned long parent_rate; | 230 | unsigned long parent_rate; |
| 356 | 231 | ||
| 357 | parent_rate = clk_get_rate(clk->parent); | 232 | parent_rate = clk_get_rate(clk->parent); |
| 358 | 233 | ||
| 359 | usb_pdf = (CSCR() & CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET; | 234 | usb_pdf = (__raw_readl(CCM_CSCR) >> 28) & 0x7; |
| 360 | 235 | ||
| 361 | return parent_rate / (usb_pdf + 1U); | 236 | return parent_rate / (usb_pdf + 1U); |
| 362 | } | 237 | } |
| 363 | 238 | ||
| 364 | static unsigned long _clk_ssi1_recalc(struct clk *clk) | 239 | static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf) |
| 365 | { | 240 | { |
| 366 | unsigned long ssi1_pdf; | ||
| 367 | unsigned long parent_rate; | 241 | unsigned long parent_rate; |
| 368 | 242 | ||
| 369 | parent_rate = clk_get_rate(clk->parent); | 243 | parent_rate = clk_get_rate(clk->parent); |
| 370 | 244 | ||
| 371 | ssi1_pdf = (PCDR0() & CCM_PCDR0_SSI1BAUDDIV_MASK) >> | ||
| 372 | CCM_PCDR0_SSI1BAUDDIV_OFFSET; | ||
| 373 | |||
| 374 | if (mx27_revision() >= CHIP_REV_2_0) | 245 | if (mx27_revision() >= CHIP_REV_2_0) |
| 375 | ssi1_pdf += 4; | 246 | pdf += 4; /* MX27 TO2+ */ |
| 376 | else | 247 | else |
| 377 | ssi1_pdf = (ssi1_pdf < 2) ? 124UL : ssi1_pdf; | 248 | pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */ |
| 378 | 249 | ||
| 379 | return 2UL * parent_rate / ssi1_pdf; | 250 | return 2UL * parent_rate / pdf; |
| 380 | } | 251 | } |
| 381 | 252 | ||
| 382 | static unsigned long _clk_ssi2_recalc(struct clk *clk) | 253 | static unsigned long get_rate_ssi1(struct clk *clk) |
| 383 | { | 254 | { |
| 384 | unsigned long ssi2_pdf; | 255 | return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 16) & 0x3f); |
| 385 | unsigned long parent_rate; | 256 | } |
| 386 | |||
| 387 | parent_rate = clk_get_rate(clk->parent); | ||
| 388 | |||
| 389 | ssi2_pdf = (PCDR0() & CCM_PCDR0_SSI2BAUDDIV_MASK) >> | ||
| 390 | CCM_PCDR0_SSI2BAUDDIV_OFFSET; | ||
| 391 | |||
| 392 | if (mx27_revision() >= CHIP_REV_2_0) | ||
| 393 | ssi2_pdf += 4; | ||
| 394 | else | ||
| 395 | ssi2_pdf = (ssi2_pdf < 2) ? 124UL : ssi2_pdf; | ||
| 396 | 257 | ||
| 397 | return 2UL * parent_rate / ssi2_pdf; | 258 | static unsigned long get_rate_ssi2(struct clk *clk) |
| 259 | { | ||
| 260 | return get_rate_ssix(clk, (__raw_readl(CCM_PCDR0) >> 26) & 0x3f); | ||
| 398 | } | 261 | } |
| 399 | 262 | ||
| 400 | static unsigned long _clk_nfc_recalc(struct clk *clk) | 263 | static unsigned long get_rate_nfc(struct clk *clk) |
| 401 | { | 264 | { |
| 402 | unsigned long nfc_pdf; | 265 | unsigned long nfc_pdf; |
| 403 | unsigned long parent_rate; | 266 | unsigned long parent_rate; |
| 404 | 267 | ||
| 405 | parent_rate = clk_get_rate(clk->parent); | 268 | parent_rate = clk_get_rate(clk->parent); |
| 406 | 269 | ||
| 407 | if (mx27_revision() >= CHIP_REV_2_0) { | 270 | if (mx27_revision() >= CHIP_REV_2_0) |
| 408 | nfc_pdf = | 271 | nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf; |
| 409 | (PCDR0() & CCM_PCDR0_NFCDIV2_MASK) >> | 272 | else |
| 410 | CCM_PCDR0_NFCDIV2_OFFSET; | 273 | nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf; |
| 411 | } else { | ||
| 412 | nfc_pdf = | ||
| 413 | (PCDR0() & CCM_PCDR0_NFCDIV_MASK) >> | ||
| 414 | CCM_PCDR0_NFCDIV_OFFSET; | ||
| 415 | } | ||
| 416 | 274 | ||
| 417 | return parent_rate / (nfc_pdf + 1); | 275 | return parent_rate / (nfc_pdf + 1); |
| 418 | } | 276 | } |
| 419 | 277 | ||
| 420 | static unsigned long _clk_vpu_recalc(struct clk *clk) | 278 | static unsigned long get_rate_vpu(struct clk *clk) |
| 421 | { | 279 | { |
| 422 | unsigned long vpu_pdf; | 280 | unsigned long vpu_pdf; |
| 423 | unsigned long parent_rate; | 281 | unsigned long parent_rate; |
| @@ -425,25 +283,27 @@ static unsigned long _clk_vpu_recalc(struct clk *clk) | |||
| 425 | parent_rate = clk_get_rate(clk->parent); | 283 | parent_rate = clk_get_rate(clk->parent); |
| 426 | 284 | ||
| 427 | if (mx27_revision() >= CHIP_REV_2_0) { | 285 | if (mx27_revision() >= CHIP_REV_2_0) { |
| 428 | vpu_pdf = | 286 | vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f; |
| 429 | (PCDR0() & CCM_PCDR0_VPUDIV2_MASK) >> | ||
| 430 | CCM_PCDR0_VPUDIV2_OFFSET; | ||
| 431 | vpu_pdf += 4; | 287 | vpu_pdf += 4; |
| 432 | } else { | 288 | } else { |
| 433 | vpu_pdf = | 289 | vpu_pdf = (__raw_readl(CCM_PCDR0) >> 8) & 0xf; |
| 434 | (PCDR0() & CCM_PCDR0_VPUDIV_MASK) >> | ||
| 435 | CCM_PCDR0_VPUDIV_OFFSET; | ||
| 436 | vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf; | 290 | vpu_pdf = (vpu_pdf < 2) ? 124 : vpu_pdf; |
| 437 | } | 291 | } |
| 292 | |||
| 438 | return 2UL * parent_rate / vpu_pdf; | 293 | return 2UL * parent_rate / vpu_pdf; |
| 439 | } | 294 | } |
| 440 | 295 | ||
| 441 | static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate) | 296 | static unsigned long round_rate_parent(struct clk *clk, unsigned long rate) |
| 442 | { | 297 | { |
| 443 | return clk->parent->round_rate(clk->parent, rate); | 298 | return clk->parent->round_rate(clk->parent, rate); |
| 444 | } | 299 | } |
| 445 | 300 | ||
| 446 | static int _clk_parent_set_rate(struct clk *clk, unsigned long rate) | 301 | static unsigned long get_rate_parent(struct clk *clk) |
| 302 | { | ||
| 303 | return clk_get_rate(clk->parent); | ||
| 304 | } | ||
| 305 | |||
| 306 | static int set_rate_parent(struct clk *clk, unsigned long rate) | ||
| 447 | { | 307 | { |
| 448 | return clk->parent->set_rate(clk->parent, rate); | 308 | return clk->parent->set_rate(clk->parent, rate); |
| 449 | } | 309 | } |
| @@ -451,1112 +311,380 @@ static int _clk_parent_set_rate(struct clk *clk, unsigned long rate) | |||
| 451 | /* in Hz */ | 311 | /* in Hz */ |
| 452 | static unsigned long external_high_reference = 26000000; | 312 | static unsigned long external_high_reference = 26000000; |
| 453 | 313 | ||
| 454 | static unsigned long get_high_reference_clock_rate(struct clk *clk) | 314 | static unsigned long get_rate_high_reference(struct clk *clk) |
| 455 | { | 315 | { |
| 456 | return external_high_reference; | 316 | return external_high_reference; |
| 457 | } | 317 | } |
| 458 | 318 | ||
| 459 | /* | ||
| 460 | * the high frequency external clock reference | ||
| 461 | * Default case is 26MHz. Could be changed at runtime | ||
| 462 | * with a call to change_external_high_reference() | ||
| 463 | */ | ||
| 464 | static struct clk ckih_clk = { | ||
| 465 | .name = "ckih", | ||
| 466 | .get_rate = get_high_reference_clock_rate, | ||
| 467 | }; | ||
| 468 | |||
| 469 | /* in Hz */ | 319 | /* in Hz */ |
| 470 | static unsigned long external_low_reference = 32768; | 320 | static unsigned long external_low_reference = 32768; |
| 471 | 321 | ||
| 472 | static unsigned long get_low_reference_clock_rate(struct clk *clk) | 322 | static unsigned long get_rate_low_reference(struct clk *clk) |
| 473 | { | 323 | { |
| 474 | return external_low_reference; | 324 | return external_low_reference; |
| 475 | } | 325 | } |
| 476 | 326 | ||
| 477 | /* | 327 | static unsigned long get_rate_fpm(struct clk *clk) |
| 478 | * the low frequency external clock reference | ||
| 479 | * Default case is 32.768kHz Could be changed at runtime | ||
| 480 | * with a call to change_external_low_reference() | ||
| 481 | */ | ||
| 482 | static struct clk ckil_clk = { | ||
| 483 | .name = "ckil", | ||
| 484 | .get_rate = get_low_reference_clock_rate, | ||
| 485 | }; | ||
| 486 | |||
| 487 | static unsigned long get_mpll_clk(struct clk *clk) | ||
| 488 | { | 328 | { |
| 489 | uint32_t reg; | 329 | return clk_get_rate(clk->parent) * 1024; |
| 490 | unsigned long ref_clk; | ||
| 491 | unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0; | ||
| 492 | unsigned long long temp; | ||
| 493 | |||
| 494 | ref_clk = clk_get_rate(clk->parent); | ||
| 495 | |||
| 496 | reg = __raw_readl(CCM_MPCTL0); | ||
| 497 | pdf = (reg & CCM_MPCTL0_PD_MASK) >> CCM_MPCTL0_PD_OFFSET; | ||
| 498 | mfd = (reg & CCM_MPCTL0_MFD_MASK) >> CCM_MPCTL0_MFD_OFFSET; | ||
| 499 | mfi = (reg & CCM_MPCTL0_MFI_MASK) >> CCM_MPCTL0_MFI_OFFSET; | ||
| 500 | mfn = (reg & CCM_MPCTL0_MFN_MASK) >> CCM_MPCTL0_MFN_OFFSET; | ||
| 501 | |||
| 502 | mfi = (mfi <= 5) ? 5 : mfi; | ||
| 503 | temp = 2LL * ref_clk * mfn; | ||
| 504 | do_div(temp, mfd + 1); | ||
| 505 | temp = 2LL * ref_clk * mfi + temp; | ||
| 506 | do_div(temp, pdf + 1); | ||
| 507 | |||
| 508 | return (unsigned long)temp; | ||
| 509 | } | 330 | } |
| 510 | 331 | ||
| 511 | static struct clk mpll_clk = { | 332 | static unsigned long get_rate_mpll(struct clk *clk) |
| 512 | .name = "mpll", | 333 | { |
| 513 | .parent = &ckih_clk, | 334 | return mxc_decode_pll(__raw_readl(CCM_MPCTL0), |
| 514 | .get_rate = get_mpll_clk, | 335 | clk_get_rate(clk->parent)); |
| 515 | }; | 336 | } |
| 516 | 337 | ||
| 517 | static unsigned long _clk_mpll_main_get_rate(struct clk *clk) | 338 | static unsigned long get_rate_mpll_main(struct clk *clk) |
| 518 | { | 339 | { |
| 519 | unsigned long parent_rate; | 340 | unsigned long parent_rate; |
| 520 | 341 | ||
| 521 | parent_rate = clk_get_rate(clk->parent); | 342 | parent_rate = clk_get_rate(clk->parent); |
| 522 | 343 | ||
| 523 | /* i.MX27 TO2: | 344 | /* i.MX27 TO2: |
| 524 | * clk->id == 0: arm clock source path 1 which is from 2*MPLL/DIV_2 | 345 | * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2 |
| 525 | * clk->id == 1: arm clock source path 2 which is from 2*MPLL/DIV_3 | 346 | * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3 |
| 526 | */ | 347 | */ |
| 527 | |||
| 528 | if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1) | 348 | if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1) |
| 529 | return 2UL * parent_rate / 3UL; | 349 | return 2UL * parent_rate / 3UL; |
| 530 | 350 | ||
| 531 | return parent_rate; | 351 | return parent_rate; |
| 532 | } | 352 | } |
| 533 | 353 | ||
| 534 | static struct clk mpll_main_clk[] = { | 354 | static unsigned long get_rate_spll(struct clk *clk) |
| 535 | { | ||
| 536 | /* For i.MX27 TO2, it is the MPLL path 1 of ARM core | ||
| 537 | * It provide the clock source whose rate is same as MPLL | ||
| 538 | */ | ||
| 539 | .name = "mpll_main", | ||
| 540 | .id = 0, | ||
| 541 | .parent = &mpll_clk, | ||
| 542 | .get_rate = _clk_mpll_main_get_rate | ||
| 543 | }, { | ||
| 544 | /* For i.MX27 TO2, it is the MPLL path 2 of ARM core | ||
| 545 | * It provide the clock source whose rate is same MPLL * 2/3 | ||
| 546 | */ | ||
| 547 | .name = "mpll_main", | ||
| 548 | .id = 1, | ||
| 549 | .parent = &mpll_clk, | ||
| 550 | .get_rate = _clk_mpll_main_get_rate | ||
| 551 | } | ||
| 552 | }; | ||
| 553 | |||
| 554 | static unsigned long get_spll_clk(struct clk *clk) | ||
| 555 | { | 355 | { |
| 556 | uint32_t reg; | 356 | uint32_t reg; |
| 557 | unsigned long ref_clk; | 357 | unsigned long rate; |
| 558 | unsigned long mfi = 0, mfn = 0, mfd = 0, pdf = 0; | ||
| 559 | unsigned long long temp; | ||
| 560 | 358 | ||
| 561 | ref_clk = clk_get_rate(clk->parent); | 359 | rate = clk_get_rate(clk->parent); |
| 562 | 360 | ||
| 563 | reg = __raw_readl(CCM_SPCTL0); | 361 | reg = __raw_readl(CCM_SPCTL0); |
| 564 | /*TODO: This is TO2 Bug */ | 362 | |
| 363 | /* On TO2 we have to write the value back. Otherwise we | ||
| 364 | * read 0 from this register the next time. | ||
| 365 | */ | ||
| 565 | if (mx27_revision() >= CHIP_REV_2_0) | 366 | if (mx27_revision() >= CHIP_REV_2_0) |
| 566 | __raw_writel(reg, CCM_SPCTL0); | 367 | __raw_writel(reg, CCM_SPCTL0); |
| 567 | 368 | ||
| 568 | pdf = (reg & CCM_SPCTL0_PD_MASK) >> CCM_SPCTL0_PD_OFFSET; | 369 | return mxc_decode_pll(reg, rate); |
| 569 | mfd = (reg & CCM_SPCTL0_MFD_MASK) >> CCM_SPCTL0_MFD_OFFSET; | ||
| 570 | mfi = (reg & CCM_SPCTL0_MFI_MASK) >> CCM_SPCTL0_MFI_OFFSET; | ||
| 571 | mfn = (reg & CCM_SPCTL0_MFN_MASK) >> CCM_SPCTL0_MFN_OFFSET; | ||
| 572 | |||
| 573 | mfi = (mfi <= 5) ? 5 : mfi; | ||
| 574 | temp = 2LL * ref_clk * mfn; | ||
| 575 | do_div(temp, mfd + 1); | ||
| 576 | temp = 2LL * ref_clk * mfi + temp; | ||
| 577 | do_div(temp, pdf + 1); | ||
| 578 | |||
| 579 | return (unsigned long)temp; | ||
| 580 | } | 370 | } |
| 581 | 371 | ||
| 582 | static struct clk spll_clk = { | 372 | static unsigned long get_rate_cpu(struct clk *clk) |
| 583 | .name = "spll", | ||
| 584 | .parent = &ckih_clk, | ||
| 585 | .get_rate = get_spll_clk, | ||
| 586 | .enable = _clk_spll_enable, | ||
| 587 | .disable = _clk_spll_disable, | ||
| 588 | }; | ||
| 589 | |||
| 590 | static unsigned long get_cpu_clk(struct clk *clk) | ||
| 591 | { | 373 | { |
| 592 | u32 div; | 374 | u32 div; |
| 593 | unsigned long rate; | 375 | unsigned long rate; |
| 594 | 376 | ||
| 595 | if (mx27_revision() >= CHIP_REV_2_0) | 377 | if (mx27_revision() >= CHIP_REV_2_0) |
| 596 | div = (CSCR() & CCM_CSCR_ARM_MASK) >> CCM_CSCR_ARM_OFFSET; | 378 | div = (__raw_readl(CCM_CSCR) >> 12) & 0x3; |
| 597 | else | 379 | else |
| 598 | div = (CSCR() & CCM_CSCR_PRESC_MASK) >> CCM_CSCR_PRESC_OFFSET; | 380 | div = (__raw_readl(CCM_CSCR) >> 13) & 0x7; |
| 599 | 381 | ||
| 600 | rate = clk_get_rate(clk->parent); | 382 | rate = clk_get_rate(clk->parent); |
| 601 | return rate / (div + 1); | 383 | return rate / (div + 1); |
| 602 | } | 384 | } |
| 603 | 385 | ||
| 604 | static struct clk cpu_clk = { | 386 | static unsigned long get_rate_ahb(struct clk *clk) |
| 605 | .name = "cpu_clk", | ||
| 606 | .parent = &mpll_main_clk[1], | ||
| 607 | .set_parent = _clk_cpu_set_parent, | ||
| 608 | .round_rate = _clk_cpu_round_rate, | ||
| 609 | .get_rate = get_cpu_clk, | ||
| 610 | .set_rate = _clk_cpu_set_rate, | ||
| 611 | }; | ||
| 612 | |||
| 613 | static unsigned long get_ahb_clk(struct clk *clk) | ||
| 614 | { | 387 | { |
| 615 | unsigned long rate; | 388 | unsigned long rate, bclk_pdf; |
| 616 | unsigned long bclk_pdf; | ||
| 617 | 389 | ||
| 618 | if (mx27_revision() >= CHIP_REV_2_0) | 390 | if (mx27_revision() >= CHIP_REV_2_0) |
| 619 | bclk_pdf = (CSCR() & CCM_CSCR_AHB_MASK) | 391 | bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3; |
| 620 | >> CCM_CSCR_AHB_OFFSET; | ||
| 621 | else | 392 | else |
| 622 | bclk_pdf = (CSCR() & CCM_CSCR_BCLK_MASK) | 393 | bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf; |
| 623 | >> CCM_CSCR_BCLK_OFFSET; | ||
| 624 | 394 | ||
| 625 | rate = clk_get_rate(clk->parent); | 395 | rate = clk_get_rate(clk->parent); |
| 626 | return rate / (bclk_pdf + 1); | 396 | return rate / (bclk_pdf + 1); |
| 627 | } | 397 | } |
| 628 | 398 | ||
| 629 | static struct clk ahb_clk = { | 399 | static unsigned long get_rate_ipg(struct clk *clk) |
| 630 | .name = "ahb_clk", | ||
| 631 | .parent = &mpll_main_clk[1], | ||
| 632 | .get_rate = get_ahb_clk, | ||
| 633 | }; | ||
| 634 | |||
| 635 | static unsigned long get_ipg_clk(struct clk *clk) | ||
| 636 | { | 400 | { |
| 637 | unsigned long rate; | 401 | unsigned long rate, ipg_pdf; |
| 638 | unsigned long ipg_pdf; | ||
| 639 | 402 | ||
| 640 | if (mx27_revision() >= CHIP_REV_2_0) | 403 | if (mx27_revision() >= CHIP_REV_2_0) |
| 641 | return clk_get_rate(clk->parent); | 404 | return clk_get_rate(clk->parent); |
| 642 | else | 405 | else |
| 643 | ipg_pdf = (CSCR() & CCM_CSCR_IPDIV) >> CCM_CSCR_IPDIV_OFFSET; | 406 | ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1; |
| 644 | 407 | ||
| 645 | rate = clk_get_rate(clk->parent); | 408 | rate = clk_get_rate(clk->parent); |
| 646 | return rate / (ipg_pdf + 1); | 409 | return rate / (ipg_pdf + 1); |
| 647 | } | 410 | } |
| 648 | 411 | ||
| 649 | static struct clk ipg_clk = { | 412 | static unsigned long get_rate_per(struct clk *clk) |
| 650 | .name = "ipg_clk", | ||
| 651 | .parent = &ahb_clk, | ||
| 652 | .get_rate = get_ipg_clk, | ||
| 653 | }; | ||
| 654 | |||
| 655 | static unsigned long _clk_perclkx_recalc(struct clk *clk) | ||
| 656 | { | 413 | { |
| 657 | unsigned long perclk_pdf; | 414 | unsigned long perclk_pdf, parent_rate; |
| 658 | unsigned long parent_rate; | ||
| 659 | 415 | ||
| 660 | parent_rate = clk_get_rate(clk->parent); | 416 | parent_rate = clk_get_rate(clk->parent); |
| 661 | 417 | ||
| 662 | if (clk->id < 0 || clk->id > 3) | 418 | if (clk->id < 0 || clk->id > 3) |
| 663 | return 0; | 419 | return 0; |
| 664 | 420 | ||
| 665 | perclk_pdf = (PCDR1() >> (clk->id << 3)) & CCM_PCDR1_PERDIV1_MASK; | 421 | perclk_pdf = (__raw_readl(CCM_PCDR1) >> (clk->id << 3)) & 0x3f; |
| 666 | 422 | ||
| 667 | return parent_rate / (perclk_pdf + 1); | 423 | return parent_rate / (perclk_pdf + 1); |
| 668 | } | 424 | } |
| 669 | 425 | ||
| 670 | static struct clk per_clk[] = { | 426 | /* |
| 671 | { | 427 | * the high frequency external clock reference |
| 672 | .name = "per_clk", | 428 | * Default case is 26MHz. Could be changed at runtime |
| 673 | .id = 0, | 429 | * with a call to change_external_high_reference() |
| 674 | .parent = &mpll_main_clk[1], | 430 | */ |
| 675 | .get_rate = _clk_perclkx_recalc, | 431 | static struct clk ckih_clk = { |
| 676 | .enable = _clk_enable, | 432 | .get_rate = get_rate_high_reference, |
| 677 | .enable_reg = CCM_PCCR1, | ||
| 678 | .enable_shift = CCM_PCCR1_PERCLK1_OFFSET, | ||
| 679 | .disable = _clk_disable, | ||
| 680 | }, { | ||
| 681 | .name = "per_clk", | ||
| 682 | .id = 1, | ||
| 683 | .parent = &mpll_main_clk[1], | ||
| 684 | .get_rate = _clk_perclkx_recalc, | ||
| 685 | .enable = _clk_enable, | ||
| 686 | .enable_reg = CCM_PCCR1, | ||
| 687 | .enable_shift = CCM_PCCR1_PERCLK2_OFFSET, | ||
| 688 | .disable = _clk_disable, | ||
| 689 | }, { | ||
| 690 | .name = "per_clk", | ||
| 691 | .id = 2, | ||
| 692 | .parent = &mpll_main_clk[1], | ||
| 693 | .round_rate = _clk_perclkx_round_rate, | ||
| 694 | .set_rate = _clk_perclkx_set_rate, | ||
| 695 | .get_rate = _clk_perclkx_recalc, | ||
| 696 | .enable = _clk_enable, | ||
| 697 | .enable_reg = CCM_PCCR1, | ||
| 698 | .enable_shift = CCM_PCCR1_PERCLK3_OFFSET, | ||
| 699 | .disable = _clk_disable, | ||
| 700 | }, { | ||
| 701 | .name = "per_clk", | ||
| 702 | .id = 3, | ||
| 703 | .parent = &mpll_main_clk[1], | ||
| 704 | .round_rate = _clk_perclkx_round_rate, | ||
| 705 | .set_rate = _clk_perclkx_set_rate, | ||
| 706 | .get_rate = _clk_perclkx_recalc, | ||
| 707 | .enable = _clk_enable, | ||
| 708 | .enable_reg = CCM_PCCR1, | ||
| 709 | .enable_shift = CCM_PCCR1_PERCLK4_OFFSET, | ||
| 710 | .disable = _clk_disable, | ||
| 711 | }, | ||
| 712 | }; | ||
| 713 | |||
| 714 | struct clk uart1_clk[] = { | ||
| 715 | { | ||
| 716 | .name = "uart_clk", | ||
| 717 | .id = 0, | ||
| 718 | .parent = &per_clk[0], | ||
| 719 | .secondary = &uart1_clk[1], | ||
| 720 | }, { | ||
| 721 | .name = "uart_ipg_clk", | ||
| 722 | .id = 0, | ||
| 723 | .parent = &ipg_clk, | ||
| 724 | .enable = _clk_enable, | ||
| 725 | .enable_reg = CCM_PCCR1, | ||
| 726 | .enable_shift = CCM_PCCR1_UART1_OFFSET, | ||
| 727 | .disable = _clk_disable, | ||
| 728 | }, | ||
| 729 | }; | ||
| 730 | |||
| 731 | struct clk uart2_clk[] = { | ||
| 732 | { | ||
| 733 | .name = "uart_clk", | ||
| 734 | .id = 1, | ||
| 735 | .parent = &per_clk[0], | ||
| 736 | .secondary = &uart2_clk[1], | ||
| 737 | }, { | ||
| 738 | .name = "uart_ipg_clk", | ||
| 739 | .id = 1, | ||
| 740 | .parent = &ipg_clk, | ||
| 741 | .enable = _clk_enable, | ||
| 742 | .enable_reg = CCM_PCCR1, | ||
| 743 | .enable_shift = CCM_PCCR1_UART2_OFFSET, | ||
| 744 | .disable = _clk_disable, | ||
| 745 | }, | ||
| 746 | }; | ||
| 747 | |||
| 748 | struct clk uart3_clk[] = { | ||
| 749 | { | ||
| 750 | .name = "uart_clk", | ||
| 751 | .id = 2, | ||
| 752 | .parent = &per_clk[0], | ||
| 753 | .secondary = &uart3_clk[1], | ||
| 754 | }, { | ||
| 755 | .name = "uart_ipg_clk", | ||
| 756 | .id = 2, | ||
| 757 | .parent = &ipg_clk, | ||
| 758 | .enable = _clk_enable, | ||
| 759 | .enable_reg = CCM_PCCR1, | ||
| 760 | .enable_shift = CCM_PCCR1_UART3_OFFSET, | ||
| 761 | .disable = _clk_disable, | ||
| 762 | }, | ||
| 763 | }; | ||
| 764 | |||
| 765 | struct clk uart4_clk[] = { | ||
| 766 | { | ||
| 767 | .name = "uart_clk", | ||
| 768 | .id = 3, | ||
| 769 | .parent = &per_clk[0], | ||
| 770 | .secondary = &uart4_clk[1], | ||
| 771 | }, { | ||
| 772 | .name = "uart_ipg_clk", | ||
| 773 | .id = 3, | ||
| 774 | .parent = &ipg_clk, | ||
| 775 | .enable = _clk_enable, | ||
| 776 | .enable_reg = CCM_PCCR1, | ||
| 777 | .enable_shift = CCM_PCCR1_UART4_OFFSET, | ||
| 778 | .disable = _clk_disable, | ||
| 779 | }, | ||
| 780 | }; | ||
| 781 | |||
| 782 | struct clk uart5_clk[] = { | ||
| 783 | { | ||
| 784 | .name = "uart_clk", | ||
| 785 | .id = 4, | ||
| 786 | .parent = &per_clk[0], | ||
| 787 | .secondary = &uart5_clk[1], | ||
| 788 | }, { | ||
| 789 | .name = "uart_ipg_clk", | ||
| 790 | .id = 4, | ||
| 791 | .parent = &ipg_clk, | ||
| 792 | .enable = _clk_enable, | ||
| 793 | .enable_reg = CCM_PCCR1, | ||
| 794 | .enable_shift = CCM_PCCR1_UART5_OFFSET, | ||
| 795 | .disable = _clk_disable, | ||
| 796 | }, | ||
| 797 | }; | ||
| 798 | |||
| 799 | struct clk uart6_clk[] = { | ||
| 800 | { | ||
| 801 | .name = "uart_clk", | ||
| 802 | .id = 5, | ||
| 803 | .parent = &per_clk[0], | ||
| 804 | .secondary = &uart6_clk[1], | ||
| 805 | }, { | ||
| 806 | .name = "uart_ipg_clk", | ||
| 807 | .id = 5, | ||
| 808 | .parent = &ipg_clk, | ||
| 809 | .enable = _clk_enable, | ||
| 810 | .enable_reg = CCM_PCCR1, | ||
| 811 | .enable_shift = CCM_PCCR1_UART6_OFFSET, | ||
| 812 | .disable = _clk_disable, | ||
| 813 | }, | ||
| 814 | }; | ||
| 815 | |||
| 816 | static struct clk gpt1_clk[] = { | ||
| 817 | { | ||
| 818 | .name = "gpt_clk", | ||
| 819 | .id = 0, | ||
| 820 | .parent = &per_clk[0], | ||
| 821 | .secondary = &gpt1_clk[1], | ||
| 822 | }, { | ||
| 823 | .name = "gpt_ipg_clk", | ||
| 824 | .id = 0, | ||
| 825 | .parent = &ipg_clk, | ||
| 826 | .enable = _clk_enable, | ||
| 827 | .enable_reg = CCM_PCCR0, | ||
| 828 | .enable_shift = CCM_PCCR0_GPT1_OFFSET, | ||
| 829 | .disable = _clk_disable, | ||
| 830 | }, | ||
| 831 | }; | ||
| 832 | |||
| 833 | static struct clk gpt2_clk[] = { | ||
| 834 | { | ||
| 835 | .name = "gpt_clk", | ||
| 836 | .id = 1, | ||
| 837 | .parent = &per_clk[0], | ||
| 838 | .secondary = &gpt2_clk[1], | ||
| 839 | }, { | ||
| 840 | .name = "gpt_ipg_clk", | ||
| 841 | .id = 1, | ||
| 842 | .parent = &ipg_clk, | ||
| 843 | .enable = _clk_enable, | ||
| 844 | .enable_reg = CCM_PCCR0, | ||
| 845 | .enable_shift = CCM_PCCR0_GPT2_OFFSET, | ||
| 846 | .disable = _clk_disable, | ||
| 847 | }, | ||
| 848 | }; | ||
| 849 | |||
| 850 | static struct clk gpt3_clk[] = { | ||
| 851 | { | ||
| 852 | .name = "gpt_clk", | ||
| 853 | .id = 2, | ||
| 854 | .parent = &per_clk[0], | ||
| 855 | .secondary = &gpt3_clk[1], | ||
| 856 | }, { | ||
| 857 | .name = "gpt_ipg_clk", | ||
| 858 | .id = 2, | ||
| 859 | .parent = &ipg_clk, | ||
| 860 | .enable = _clk_enable, | ||
| 861 | .enable_reg = CCM_PCCR0, | ||
| 862 | .enable_shift = CCM_PCCR0_GPT3_OFFSET, | ||
| 863 | .disable = _clk_disable, | ||
| 864 | }, | ||
| 865 | }; | ||
| 866 | |||
| 867 | static struct clk gpt4_clk[] = { | ||
| 868 | { | ||
| 869 | .name = "gpt_clk", | ||
| 870 | .id = 3, | ||
| 871 | .parent = &per_clk[0], | ||
| 872 | .secondary = &gpt4_clk[1], | ||
| 873 | }, { | ||
| 874 | .name = "gpt_ipg_clk", | ||
| 875 | .id = 3, | ||
| 876 | .parent = &ipg_clk, | ||
| 877 | .enable = _clk_enable, | ||
| 878 | .enable_reg = CCM_PCCR0, | ||
| 879 | .enable_shift = CCM_PCCR0_GPT4_OFFSET, | ||
| 880 | .disable = _clk_disable, | ||
| 881 | }, | ||
| 882 | }; | ||
| 883 | |||
| 884 | static struct clk gpt5_clk[] = { | ||
| 885 | { | ||
| 886 | .name = "gpt_clk", | ||
| 887 | .id = 4, | ||
| 888 | .parent = &per_clk[0], | ||
| 889 | .secondary = &gpt5_clk[1], | ||
| 890 | }, { | ||
| 891 | .name = "gpt_ipg_clk", | ||
| 892 | .id = 4, | ||
| 893 | .parent = &ipg_clk, | ||
| 894 | .enable = _clk_enable, | ||
| 895 | .enable_reg = CCM_PCCR0, | ||
| 896 | .enable_shift = CCM_PCCR0_GPT5_OFFSET, | ||
| 897 | .disable = _clk_disable, | ||
| 898 | }, | ||
| 899 | }; | 433 | }; |
| 900 | 434 | ||
| 901 | static struct clk gpt6_clk[] = { | 435 | static struct clk mpll_clk = { |
| 902 | { | 436 | .parent = &ckih_clk, |
| 903 | .name = "gpt_clk", | 437 | .get_rate = get_rate_mpll, |
| 904 | .id = 5, | ||
| 905 | .parent = &per_clk[0], | ||
| 906 | .secondary = &gpt6_clk[1], | ||
| 907 | }, { | ||
| 908 | .name = "gpt_ipg_clk", | ||
| 909 | .id = 5, | ||
| 910 | .parent = &ipg_clk, | ||
| 911 | .enable = _clk_enable, | ||
| 912 | .enable_reg = CCM_PCCR0, | ||
| 913 | .enable_shift = CCM_PCCR0_GPT6_OFFSET, | ||
| 914 | .disable = _clk_disable, | ||
| 915 | }, | ||
| 916 | }; | 438 | }; |
| 917 | 439 | ||
| 918 | static struct clk pwm_clk[] = { | 440 | /* For i.MX27 TO2, it is the MPLL path 1 of ARM core |
| 919 | { | 441 | * It provides the clock source whose rate is same as MPLL |
| 920 | .name = "pwm_clk", | 442 | */ |
| 921 | .parent = &per_clk[0], | 443 | static struct clk mpll_main1_clk = { |
| 922 | .secondary = &pwm_clk[1], | 444 | .id = 0, |
| 923 | }, { | 445 | .parent = &mpll_clk, |
| 924 | .name = "pwm_clk", | 446 | .get_rate = get_rate_mpll_main, |
| 925 | .parent = &ipg_clk, | ||
| 926 | .enable = _clk_enable, | ||
| 927 | .enable_reg = CCM_PCCR0, | ||
| 928 | .enable_shift = CCM_PCCR0_PWM_OFFSET, | ||
| 929 | .disable = _clk_disable, | ||
| 930 | }, | ||
| 931 | }; | 447 | }; |
| 932 | 448 | ||
| 933 | static struct clk sdhc1_clk[] = { | 449 | /* For i.MX27 TO2, it is the MPLL path 2 of ARM core |
| 934 | { | 450 | * It provides the clock source whose rate is same MPLL * 2 / 3 |
| 935 | .name = "sdhc_clk", | 451 | */ |
| 936 | .id = 0, | 452 | static struct clk mpll_main2_clk = { |
| 937 | .parent = &per_clk[1], | 453 | .id = 1, |
| 938 | .secondary = &sdhc1_clk[1], | 454 | .parent = &mpll_clk, |
| 939 | }, { | 455 | .get_rate = get_rate_mpll_main, |
| 940 | .name = "sdhc_ipg_clk", | ||
| 941 | .id = 0, | ||
| 942 | .parent = &ipg_clk, | ||
| 943 | .enable = _clk_enable, | ||
| 944 | .enable_reg = CCM_PCCR0, | ||
| 945 | .enable_shift = CCM_PCCR0_SDHC1_OFFSET, | ||
| 946 | .disable = _clk_disable, | ||
| 947 | }, | ||
| 948 | }; | 456 | }; |
| 949 | 457 | ||
| 950 | static struct clk sdhc2_clk[] = { | 458 | static struct clk ahb_clk = { |
| 951 | { | 459 | .parent = &mpll_main2_clk, |
| 952 | .name = "sdhc_clk", | 460 | .get_rate = get_rate_ahb, |
| 953 | .id = 1, | ||
| 954 | .parent = &per_clk[1], | ||
| 955 | .secondary = &sdhc2_clk[1], | ||
| 956 | }, { | ||
| 957 | .name = "sdhc_ipg_clk", | ||
| 958 | .id = 1, | ||
| 959 | .parent = &ipg_clk, | ||
| 960 | .enable = _clk_enable, | ||
| 961 | .enable_reg = CCM_PCCR0, | ||
| 962 | .enable_shift = CCM_PCCR0_SDHC2_OFFSET, | ||
| 963 | .disable = _clk_disable, | ||
| 964 | }, | ||
| 965 | }; | 461 | }; |
| 966 | 462 | ||
| 967 | static struct clk sdhc3_clk[] = { | 463 | static struct clk ipg_clk = { |
| 968 | { | 464 | .parent = &ahb_clk, |
| 969 | .name = "sdhc_clk", | 465 | .get_rate = get_rate_ipg, |
| 970 | .id = 2, | ||
| 971 | .parent = &per_clk[1], | ||
| 972 | .secondary = &sdhc3_clk[1], | ||
| 973 | }, { | ||
| 974 | .name = "sdhc_ipg_clk", | ||
| 975 | .id = 2, | ||
| 976 | .parent = &ipg_clk, | ||
| 977 | .enable = _clk_enable, | ||
| 978 | .enable_reg = CCM_PCCR0, | ||
| 979 | .enable_shift = CCM_PCCR0_SDHC3_OFFSET, | ||
| 980 | .disable = _clk_disable, | ||
| 981 | }, | ||
| 982 | }; | 466 | }; |
| 983 | 467 | ||
| 984 | static struct clk cspi1_clk[] = { | 468 | static struct clk cpu_clk = { |
| 985 | { | 469 | .parent = &mpll_main2_clk, |
| 986 | .name = "cspi_clk", | 470 | .set_parent = clk_cpu_set_parent, |
| 987 | .id = 0, | 471 | .round_rate = round_rate_cpu, |
| 988 | .parent = &per_clk[1], | 472 | .get_rate = get_rate_cpu, |
| 989 | .secondary = &cspi1_clk[1], | 473 | .set_rate = set_rate_cpu, |
| 990 | }, { | ||
| 991 | .name = "cspi_ipg_clk", | ||
| 992 | .id = 0, | ||
| 993 | .parent = &ipg_clk, | ||
| 994 | .enable = _clk_enable, | ||
| 995 | .enable_reg = CCM_PCCR0, | ||
| 996 | .enable_shift = CCM_PCCR0_CSPI1_OFFSET, | ||
| 997 | .disable = _clk_disable, | ||
| 998 | }, | ||
| 999 | }; | 474 | }; |
| 1000 | 475 | ||
| 1001 | static struct clk cspi2_clk[] = { | 476 | static struct clk spll_clk = { |
| 1002 | { | 477 | .parent = &ckih_clk, |
| 1003 | .name = "cspi_clk", | 478 | .get_rate = get_rate_spll, |
| 1004 | .id = 1, | 479 | .enable = clk_spll_enable, |
| 1005 | .parent = &per_clk[1], | 480 | .disable = clk_spll_disable, |
| 1006 | .secondary = &cspi2_clk[1], | ||
| 1007 | }, { | ||
| 1008 | .name = "cspi_ipg_clk", | ||
| 1009 | .id = 1, | ||
| 1010 | .parent = &ipg_clk, | ||
| 1011 | .enable = _clk_enable, | ||
| 1012 | .enable_reg = CCM_PCCR0, | ||
| 1013 | .enable_shift = CCM_PCCR0_CSPI2_OFFSET, | ||
| 1014 | .disable = _clk_disable, | ||
| 1015 | }, | ||
| 1016 | }; | 481 | }; |
| 1017 | 482 | ||
| 1018 | static struct clk cspi3_clk[] = { | 483 | /* |
| 1019 | { | 484 | * the low frequency external clock reference |
| 1020 | .name = "cspi_clk", | 485 | * Default case is 32.768kHz. |
| 1021 | .id = 2, | 486 | */ |
| 1022 | .parent = &per_clk[1], | 487 | static struct clk ckil_clk = { |
| 1023 | .secondary = &cspi3_clk[1], | 488 | .get_rate = get_rate_low_reference, |
| 1024 | }, { | ||
| 1025 | .name = "cspi_ipg_clk", | ||
| 1026 | .id = 2, | ||
| 1027 | .parent = &ipg_clk, | ||
| 1028 | .enable = _clk_enable, | ||
| 1029 | .enable_reg = CCM_PCCR0, | ||
| 1030 | .enable_shift = CCM_PCCR0_CSPI3_OFFSET, | ||
| 1031 | .disable = _clk_disable, | ||
| 1032 | }, | ||
| 1033 | }; | 489 | }; |
| 1034 | 490 | ||
| 1035 | static struct clk lcdc_clk[] = { | 491 | /* Output of frequency pre multiplier */ |
| 1036 | { | 492 | static struct clk fpm_clk = { |
| 1037 | .name = "lcdc_clk", | 493 | .parent = &ckil_clk, |
| 1038 | .parent = &per_clk[2], | 494 | .get_rate = get_rate_fpm, |
| 1039 | .secondary = &lcdc_clk[1], | ||
| 1040 | .round_rate = _clk_parent_round_rate, | ||
| 1041 | .set_rate = _clk_parent_set_rate, | ||
| 1042 | }, { | ||
| 1043 | .name = "lcdc_ipg_clk", | ||
| 1044 | .parent = &ipg_clk, | ||
| 1045 | .secondary = &lcdc_clk[2], | ||
| 1046 | .enable = _clk_enable, | ||
| 1047 | .enable_reg = CCM_PCCR0, | ||
| 1048 | .enable_shift = CCM_PCCR0_LCDC_OFFSET, | ||
| 1049 | .disable = _clk_disable, | ||
| 1050 | }, { | ||
| 1051 | .name = "lcdc_ahb_clk", | ||
| 1052 | .parent = &ahb_clk, | ||
| 1053 | .enable = _clk_enable, | ||
| 1054 | .enable_reg = CCM_PCCR1, | ||
| 1055 | .enable_shift = CCM_PCCR1_HCLK_LCDC_OFFSET, | ||
| 1056 | .disable = _clk_disable, | ||
| 1057 | }, | ||
| 1058 | }; | 495 | }; |
| 1059 | 496 | ||
| 1060 | static struct clk csi_clk[] = { | 497 | #define PCCR0 CCM_PCCR0 |
| 1061 | { | 498 | #define PCCR1 CCM_PCCR1 |
| 1062 | .name = "csi_perclk", | ||
| 1063 | .parent = &per_clk[3], | ||
| 1064 | .secondary = &csi_clk[1], | ||
| 1065 | .round_rate = _clk_parent_round_rate, | ||
| 1066 | .set_rate = _clk_parent_set_rate, | ||
| 1067 | }, { | ||
| 1068 | .name = "csi_ahb_clk", | ||
| 1069 | .parent = &ahb_clk, | ||
| 1070 | .enable = _clk_enable, | ||
| 1071 | .enable_reg = CCM_PCCR1, | ||
| 1072 | .enable_shift = CCM_PCCR1_HCLK_CSI_OFFSET, | ||
| 1073 | .disable = _clk_disable, | ||
| 1074 | }, | ||
| 1075 | }; | ||
| 1076 | 499 | ||
| 1077 | static struct clk usb_clk[] = { | 500 | #define DEFINE_CLOCK(name, i, er, es, gr, s, p) \ |
| 1078 | { | 501 | static struct clk name = { \ |
| 1079 | .name = "usb_clk", | 502 | .id = i, \ |
| 1080 | .parent = &spll_clk, | 503 | .enable_reg = er, \ |
| 1081 | .get_rate = _clk_usb_recalc, | 504 | .enable_shift = es, \ |
| 1082 | .enable = _clk_enable, | 505 | .get_rate = gr, \ |
| 1083 | .enable_reg = CCM_PCCR1, | 506 | .enable = clk_pccr_enable, \ |
| 1084 | .enable_shift = CCM_PCCR1_USBOTG_OFFSET, | 507 | .disable = clk_pccr_disable, \ |
| 1085 | .disable = _clk_disable, | 508 | .secondary = s, \ |
| 1086 | }, { | 509 | .parent = p, \ |
| 1087 | .name = "usb_ahb_clk", | ||
| 1088 | .parent = &ahb_clk, | ||
| 1089 | .enable = _clk_enable, | ||
| 1090 | .enable_reg = CCM_PCCR1, | ||
| 1091 | .enable_shift = CCM_PCCR1_HCLK_USBOTG_OFFSET, | ||
| 1092 | .disable = _clk_disable, | ||
| 1093 | } | 510 | } |
| 1094 | }; | ||
| 1095 | 511 | ||
| 1096 | static struct clk ssi1_clk[] = { | 512 | #define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \ |
| 1097 | { | 513 | static struct clk name = { \ |
| 1098 | .name = "ssi_clk", | 514 | .id = i, \ |
| 1099 | .id = 0, | 515 | .enable_reg = er, \ |
| 1100 | .parent = &mpll_main_clk[1], | 516 | .enable_shift = es, \ |
| 1101 | .secondary = &ssi1_clk[1], | 517 | .get_rate = get_rate_##getsetround, \ |
| 1102 | .get_rate = _clk_ssi1_recalc, | 518 | .set_rate = set_rate_##getsetround, \ |
| 1103 | .enable = _clk_enable, | 519 | .round_rate = round_rate_##getsetround, \ |
| 1104 | .enable_reg = CCM_PCCR1, | 520 | .enable = clk_pccr_enable, \ |
| 1105 | .enable_shift = CCM_PCCR1_SSI1_BAUD_OFFSET, | 521 | .disable = clk_pccr_disable, \ |
| 1106 | .disable = _clk_disable, | 522 | .secondary = s, \ |
| 1107 | }, { | 523 | .parent = p, \ |
| 1108 | .name = "ssi_ipg_clk", | 524 | } |
| 1109 | .id = 0, | ||
| 1110 | .parent = &ipg_clk, | ||
| 1111 | .enable = _clk_enable, | ||
| 1112 | .enable_reg = CCM_PCCR0, | ||
| 1113 | .enable_shift = CCM_PCCR0_SSI1_IPG_OFFSET, | ||
| 1114 | .disable = _clk_disable, | ||
| 1115 | }, | ||
| 1116 | }; | ||
| 1117 | 525 | ||
| 1118 | static struct clk ssi2_clk[] = { | 526 | /* Forward declaration to keep the following list in order */ |
| 1119 | { | 527 | static struct clk slcdc_clk1, sahara2_clk1, rtic_clk1, fec_clk1, emma_clk1, |
| 1120 | .name = "ssi_clk", | 528 | dma_clk1, lcdc_clk2, vpu_clk1; |
| 1121 | .id = 1, | 529 | |
| 1122 | .parent = &mpll_main_clk[1], | 530 | /* All clocks we can gate through PCCRx in the order of PCCRx bits */ |
| 1123 | .secondary = &ssi2_clk[1], | 531 | DEFINE_CLOCK(ssi2_clk1, 1, PCCR0, 0, NULL, NULL, &ipg_clk); |
| 1124 | .get_rate = _clk_ssi2_recalc, | 532 | DEFINE_CLOCK(ssi1_clk1, 0, PCCR0, 1, NULL, NULL, &ipg_clk); |
| 1125 | .enable = _clk_enable, | 533 | DEFINE_CLOCK(slcdc_clk, 0, PCCR0, 2, NULL, &slcdc_clk1, &ahb_clk); |
| 1126 | .enable_reg = CCM_PCCR1, | 534 | DEFINE_CLOCK(sdhc3_clk1, 0, PCCR0, 3, NULL, NULL, &ipg_clk); |
| 1127 | .enable_shift = CCM_PCCR1_SSI2_BAUD_OFFSET, | 535 | DEFINE_CLOCK(sdhc2_clk1, 0, PCCR0, 4, NULL, NULL, &ipg_clk); |
| 1128 | .disable = _clk_disable, | 536 | DEFINE_CLOCK(sdhc1_clk1, 0, PCCR0, 5, NULL, NULL, &ipg_clk); |
| 1129 | }, { | 537 | DEFINE_CLOCK(scc_clk, 0, PCCR0, 6, NULL, NULL, &ipg_clk); |
| 1130 | .name = "ssi_ipg_clk", | 538 | DEFINE_CLOCK(sahara2_clk, 0, PCCR0, 7, NULL, &sahara2_clk1, &ahb_clk); |
| 1131 | .id = 1, | 539 | DEFINE_CLOCK(rtic_clk, 0, PCCR0, 8, NULL, &rtic_clk1, &ahb_clk); |
| 1132 | .parent = &ipg_clk, | 540 | DEFINE_CLOCK(rtc_clk, 0, PCCR0, 9, NULL, NULL, &ipg_clk); |
| 1133 | .enable = _clk_enable, | 541 | DEFINE_CLOCK(pwm_clk1, 0, PCCR0, 11, NULL, NULL, &ipg_clk); |
| 1134 | .enable_reg = CCM_PCCR0, | 542 | DEFINE_CLOCK(owire_clk, 0, PCCR0, 12, NULL, NULL, &ipg_clk); |
| 1135 | .enable_shift = CCM_PCCR0_SSI2_IPG_OFFSET, | 543 | DEFINE_CLOCK(mstick_clk1, 0, PCCR0, 13, NULL, NULL, &ipg_clk); |
| 1136 | .disable = _clk_disable, | 544 | DEFINE_CLOCK(lcdc_clk1, 0, PCCR0, 14, NULL, &lcdc_clk2, &ipg_clk); |
| 545 | DEFINE_CLOCK(kpp_clk, 0, PCCR0, 15, NULL, NULL, &ipg_clk); | ||
| 546 | DEFINE_CLOCK(iim_clk, 0, PCCR0, 16, NULL, NULL, &ipg_clk); | ||
| 547 | DEFINE_CLOCK(i2c2_clk, 1, PCCR0, 17, NULL, NULL, &ipg_clk); | ||
| 548 | DEFINE_CLOCK(i2c1_clk, 0, PCCR0, 18, NULL, NULL, &ipg_clk); | ||
| 549 | DEFINE_CLOCK(gpt6_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk); | ||
| 550 | DEFINE_CLOCK(gpt5_clk1, 0, PCCR0, 20, NULL, NULL, &ipg_clk); | ||
| 551 | DEFINE_CLOCK(gpt4_clk1, 0, PCCR0, 21, NULL, NULL, &ipg_clk); | ||
| 552 | DEFINE_CLOCK(gpt3_clk1, 0, PCCR0, 22, NULL, NULL, &ipg_clk); | ||
| 553 | DEFINE_CLOCK(gpt2_clk1, 0, PCCR0, 23, NULL, NULL, &ipg_clk); | ||
| 554 | DEFINE_CLOCK(gpt1_clk1, 0, PCCR0, 24, NULL, NULL, &ipg_clk); | ||
| 555 | DEFINE_CLOCK(gpio_clk, 0, PCCR0, 25, NULL, NULL, &ipg_clk); | ||
| 556 | DEFINE_CLOCK(fec_clk, 0, PCCR0, 26, NULL, &fec_clk1, &ahb_clk); | ||
| 557 | DEFINE_CLOCK(emma_clk, 0, PCCR0, 27, NULL, &emma_clk1, &ahb_clk); | ||
| 558 | DEFINE_CLOCK(dma_clk, 0, PCCR0, 28, NULL, &dma_clk1, &ahb_clk); | ||
| 559 | DEFINE_CLOCK(cspi13_clk1, 0, PCCR0, 29, NULL, NULL, &ipg_clk); | ||
| 560 | DEFINE_CLOCK(cspi2_clk1, 0, PCCR0, 30, NULL, NULL, &ipg_clk); | ||
| 561 | DEFINE_CLOCK(cspi1_clk1, 0, PCCR0, 31, NULL, NULL, &ipg_clk); | ||
| 562 | |||
| 563 | DEFINE_CLOCK(mstick_clk, 0, PCCR1, 2, NULL, &mstick_clk1, &ipg_clk); | ||
| 564 | DEFINE_CLOCK(nfc_clk, 0, PCCR1, 3, get_rate_nfc, NULL, &cpu_clk); | ||
| 565 | DEFINE_CLOCK(ssi2_clk, 1, PCCR1, 4, get_rate_ssi2, &ssi2_clk1, &mpll_main2_clk); | ||
| 566 | DEFINE_CLOCK(ssi1_clk, 0, PCCR1, 5, get_rate_ssi1, &ssi1_clk1, &mpll_main2_clk); | ||
| 567 | DEFINE_CLOCK(vpu_clk, 0, PCCR1, 6, get_rate_vpu, &vpu_clk1, &mpll_main2_clk); | ||
| 568 | DEFINE_CLOCK1(per4_clk, 3, PCCR1, 7, per, NULL, &mpll_main2_clk); | ||
| 569 | DEFINE_CLOCK1(per3_clk, 2, PCCR1, 8, per, NULL, &mpll_main2_clk); | ||
| 570 | DEFINE_CLOCK1(per2_clk, 1, PCCR1, 9, per, NULL, &mpll_main2_clk); | ||
| 571 | DEFINE_CLOCK1(per1_clk, 0, PCCR1, 10, per, NULL, &mpll_main2_clk); | ||
| 572 | DEFINE_CLOCK(usb_clk1, 0, PCCR1, 11, NULL, NULL, &ahb_clk); | ||
| 573 | DEFINE_CLOCK(slcdc_clk1, 0, PCCR1, 12, NULL, NULL, &ahb_clk); | ||
| 574 | DEFINE_CLOCK(sahara2_clk1, 0, PCCR1, 13, NULL, NULL, &ahb_clk); | ||
| 575 | DEFINE_CLOCK(rtic_clk1, 0, PCCR1, 14, NULL, NULL, &ahb_clk); | ||
| 576 | DEFINE_CLOCK(lcdc_clk2, 0, PCCR1, 15, NULL, NULL, &ahb_clk); | ||
| 577 | DEFINE_CLOCK(vpu_clk1, 0, PCCR1, 16, NULL, NULL, &ahb_clk); | ||
| 578 | DEFINE_CLOCK(fec_clk1, 0, PCCR1, 17, NULL, NULL, &ahb_clk); | ||
| 579 | DEFINE_CLOCK(emma_clk1, 0, PCCR1, 18, NULL, NULL, &ahb_clk); | ||
| 580 | DEFINE_CLOCK(emi_clk, 0, PCCR1, 19, NULL, NULL, &ahb_clk); | ||
| 581 | DEFINE_CLOCK(dma_clk1, 0, PCCR1, 20, NULL, NULL, &ahb_clk); | ||
| 582 | DEFINE_CLOCK(csi_clk1, 0, PCCR1, 21, NULL, NULL, &ahb_clk); | ||
| 583 | DEFINE_CLOCK(brom_clk, 0, PCCR1, 22, NULL, NULL, &ahb_clk); | ||
| 584 | DEFINE_CLOCK(ata_clk, 0, PCCR1, 23, NULL, NULL, &ahb_clk); | ||
| 585 | DEFINE_CLOCK(wdog_clk, 0, PCCR1, 24, NULL, NULL, &ipg_clk); | ||
| 586 | DEFINE_CLOCK(usb_clk, 0, PCCR1, 25, get_rate_usb, &usb_clk1, &spll_clk); | ||
| 587 | DEFINE_CLOCK(uart6_clk1, 0, PCCR1, 26, NULL, NULL, &ipg_clk); | ||
| 588 | DEFINE_CLOCK(uart5_clk1, 0, PCCR1, 27, NULL, NULL, &ipg_clk); | ||
| 589 | DEFINE_CLOCK(uart4_clk1, 0, PCCR1, 28, NULL, NULL, &ipg_clk); | ||
| 590 | DEFINE_CLOCK(uart3_clk1, 0, PCCR1, 29, NULL, NULL, &ipg_clk); | ||
| 591 | DEFINE_CLOCK(uart2_clk1, 0, PCCR1, 30, NULL, NULL, &ipg_clk); | ||
| 592 | DEFINE_CLOCK(uart1_clk1, 0, PCCR1, 31, NULL, NULL, &ipg_clk); | ||
| 593 | |||
| 594 | /* Clocks we cannot directly gate, but drivers need their rates */ | ||
| 595 | DEFINE_CLOCK(cspi1_clk, 0, 0, 0, NULL, &cspi1_clk1, &per2_clk); | ||
| 596 | DEFINE_CLOCK(cspi2_clk, 1, 0, 0, NULL, &cspi2_clk1, &per2_clk); | ||
| 597 | DEFINE_CLOCK(cspi3_clk, 2, 0, 0, NULL, &cspi13_clk1, &per2_clk); | ||
| 598 | DEFINE_CLOCK(sdhc1_clk, 0, 0, 0, NULL, &sdhc1_clk1, &per2_clk); | ||
| 599 | DEFINE_CLOCK(sdhc2_clk, 1, 0, 0, NULL, &sdhc2_clk1, &per2_clk); | ||
| 600 | DEFINE_CLOCK(sdhc3_clk, 2, 0, 0, NULL, &sdhc3_clk1, &per2_clk); | ||
| 601 | DEFINE_CLOCK(pwm_clk, 0, 0, 0, NULL, &pwm_clk1, &per1_clk); | ||
| 602 | DEFINE_CLOCK(gpt1_clk, 0, 0, 0, NULL, &gpt1_clk1, &per1_clk); | ||
| 603 | DEFINE_CLOCK(gpt2_clk, 1, 0, 0, NULL, &gpt2_clk1, &per1_clk); | ||
| 604 | DEFINE_CLOCK(gpt3_clk, 2, 0, 0, NULL, &gpt3_clk1, &per1_clk); | ||
| 605 | DEFINE_CLOCK(gpt4_clk, 3, 0, 0, NULL, &gpt4_clk1, &per1_clk); | ||
| 606 | DEFINE_CLOCK(gpt5_clk, 4, 0, 0, NULL, &gpt5_clk1, &per1_clk); | ||
| 607 | DEFINE_CLOCK(gpt6_clk, 5, 0, 0, NULL, &gpt6_clk1, &per1_clk); | ||
| 608 | DEFINE_CLOCK(uart1_clk, 0, 0, 0, NULL, &uart1_clk1, &per1_clk); | ||
| 609 | DEFINE_CLOCK(uart2_clk, 1, 0, 0, NULL, &uart2_clk1, &per1_clk); | ||
| 610 | DEFINE_CLOCK(uart3_clk, 2, 0, 0, NULL, &uart3_clk1, &per1_clk); | ||
| 611 | DEFINE_CLOCK(uart4_clk, 3, 0, 0, NULL, &uart4_clk1, &per1_clk); | ||
| 612 | DEFINE_CLOCK(uart5_clk, 4, 0, 0, NULL, &uart5_clk1, &per1_clk); | ||
| 613 | DEFINE_CLOCK(uart6_clk, 5, 0, 0, NULL, &uart6_clk1, &per1_clk); | ||
| 614 | DEFINE_CLOCK1(lcdc_clk, 0, 0, 0, parent, &lcdc_clk1, &per3_clk); | ||
| 615 | DEFINE_CLOCK1(csi_clk, 0, 0, 0, parent, &csi_clk1, &per4_clk); | ||
| 616 | |||
| 617 | #define _REGISTER_CLOCK(d, n, c) \ | ||
| 618 | { \ | ||
| 619 | .dev_id = d, \ | ||
| 620 | .con_id = n, \ | ||
| 621 | .clk = &c, \ | ||
| 1137 | }, | 622 | }, |
| 1138 | }; | ||
| 1139 | |||
| 1140 | static struct clk nfc_clk = { | ||
| 1141 | .name = "nfc_clk", | ||
| 1142 | .parent = &cpu_clk, | ||
| 1143 | .get_rate = _clk_nfc_recalc, | ||
| 1144 | .enable = _clk_enable, | ||
| 1145 | .enable_reg = CCM_PCCR1, | ||
| 1146 | .enable_shift = CCM_PCCR1_NFC_BAUD_OFFSET, | ||
| 1147 | .disable = _clk_disable, | ||
| 1148 | }; | ||
| 1149 | |||
| 1150 | static struct clk vpu_clk = { | ||
| 1151 | .name = "vpu_clk", | ||
| 1152 | .parent = &mpll_main_clk[1], | ||
| 1153 | .get_rate = _clk_vpu_recalc, | ||
| 1154 | .enable = _clk_vpu_enable, | ||
| 1155 | .disable = _clk_vpu_disable, | ||
| 1156 | }; | ||
| 1157 | |||
| 1158 | static struct clk dma_clk = { | ||
| 1159 | .name = "dma_clk", | ||
| 1160 | .parent = &ahb_clk, | ||
| 1161 | .enable = _clk_dma_enable, | ||
| 1162 | .disable = _clk_dma_disable, | ||
| 1163 | }; | ||
| 1164 | |||
| 1165 | static struct clk rtic_clk = { | ||
| 1166 | .name = "rtic_clk", | ||
| 1167 | .parent = &ahb_clk, | ||
| 1168 | .enable = _clk_rtic_enable, | ||
| 1169 | .disable = _clk_rtic_disable, | ||
| 1170 | }; | ||
| 1171 | 623 | ||
| 1172 | static struct clk brom_clk = { | 624 | static struct clk_lookup lookups[] __initdata = { |
| 1173 | .name = "brom_clk", | 625 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) |
| 1174 | .parent = &ahb_clk, | 626 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) |
| 1175 | .enable = _clk_enable, | 627 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) |
| 1176 | .enable_reg = CCM_PCCR1, | 628 | _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk) |
| 1177 | .enable_shift = CCM_PCCR1_HCLK_BROM_OFFSET, | 629 | _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk) |
| 1178 | .disable = _clk_disable, | 630 | _REGISTER_CLOCK("imx-uart.5", NULL, uart6_clk) |
| 1179 | }; | 631 | _REGISTER_CLOCK(NULL, "gpt1", gpt1_clk) |
| 1180 | 632 | _REGISTER_CLOCK(NULL, "gpt2", gpt2_clk) | |
| 1181 | static struct clk emma_clk = { | 633 | _REGISTER_CLOCK(NULL, "gpt3", gpt3_clk) |
| 1182 | .name = "emma_clk", | 634 | _REGISTER_CLOCK(NULL, "gpt4", gpt4_clk) |
| 1183 | .parent = &ahb_clk, | 635 | _REGISTER_CLOCK(NULL, "gpt5", gpt5_clk) |
| 1184 | .enable = _clk_emma_enable, | 636 | _REGISTER_CLOCK(NULL, "gpt6", gpt6_clk) |
| 1185 | .disable = _clk_emma_disable, | 637 | _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk) |
| 1186 | }; | 638 | _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk) |
| 1187 | 639 | _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk) | |
| 1188 | static struct clk slcdc_clk = { | 640 | _REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk) |
| 1189 | .name = "slcdc_clk", | 641 | _REGISTER_CLOCK(NULL, "cspi1", cspi1_clk) |
| 1190 | .parent = &ahb_clk, | 642 | _REGISTER_CLOCK(NULL, "cspi2", cspi2_clk) |
| 1191 | .enable = _clk_slcdc_enable, | 643 | _REGISTER_CLOCK(NULL, "cspi3", cspi3_clk) |
| 1192 | .disable = _clk_slcdc_disable, | 644 | _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) |
| 1193 | }; | 645 | _REGISTER_CLOCK(NULL, "csi", csi_clk) |
| 1194 | 646 | _REGISTER_CLOCK(NULL, "usb", usb_clk) | |
| 1195 | static struct clk fec_clk = { | 647 | _REGISTER_CLOCK(NULL, "ssi1", ssi1_clk) |
| 1196 | .name = "fec_clk", | 648 | _REGISTER_CLOCK(NULL, "ssi2", ssi2_clk) |
| 1197 | .parent = &ahb_clk, | 649 | _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) |
| 1198 | .enable = _clk_fec_enable, | 650 | _REGISTER_CLOCK(NULL, "vpu", vpu_clk) |
| 1199 | .disable = _clk_fec_disable, | 651 | _REGISTER_CLOCK(NULL, "dma", dma_clk) |
| 1200 | }; | 652 | _REGISTER_CLOCK(NULL, "rtic", rtic_clk) |
| 1201 | 653 | _REGISTER_CLOCK(NULL, "brom", brom_clk) | |
| 1202 | static struct clk emi_clk = { | 654 | _REGISTER_CLOCK(NULL, "emma", emma_clk) |
| 1203 | .name = "emi_clk", | 655 | _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk) |
| 1204 | .parent = &ahb_clk, | 656 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) |
| 1205 | .enable = _clk_enable, | 657 | _REGISTER_CLOCK(NULL, "emi", emi_clk) |
| 1206 | .enable_reg = CCM_PCCR1, | 658 | _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk) |
| 1207 | .enable_shift = CCM_PCCR1_HCLK_EMI_OFFSET, | 659 | _REGISTER_CLOCK(NULL, "ata", ata_clk) |
| 1208 | .disable = _clk_disable, | 660 | _REGISTER_CLOCK(NULL, "mstick", mstick_clk) |
| 1209 | }; | 661 | _REGISTER_CLOCK(NULL, "wdog", wdog_clk) |
| 1210 | 662 | _REGISTER_CLOCK(NULL, "gpio", gpio_clk) | |
| 1211 | static struct clk sahara2_clk = { | 663 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) |
| 1212 | .name = "sahara_clk", | 664 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) |
| 1213 | .parent = &ahb_clk, | 665 | _REGISTER_CLOCK(NULL, "iim", iim_clk) |
| 1214 | .enable = _clk_sahara2_enable, | 666 | _REGISTER_CLOCK(NULL, "kpp", kpp_clk) |
| 1215 | .disable = _clk_sahara2_disable, | 667 | _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk) |
| 1216 | }; | 668 | _REGISTER_CLOCK(NULL, "rtc", rtc_clk) |
| 1217 | 669 | _REGISTER_CLOCK(NULL, "scc", scc_clk) | |
| 1218 | static struct clk ata_clk = { | 670 | }; |
| 1219 | .name = "ata_clk", | 671 | |
| 1220 | .parent = &ahb_clk, | 672 | /* Adjust the clock path for TO2 and later */ |
| 1221 | .enable = _clk_enable, | 673 | static void __init to2_adjust_clocks(void) |
| 1222 | .enable_reg = CCM_PCCR1, | 674 | { |
| 1223 | .enable_shift = CCM_PCCR1_HCLK_ATA_OFFSET, | 675 | unsigned long cscr = __raw_readl(CCM_CSCR); |
| 1224 | .disable = _clk_disable, | ||
| 1225 | }; | ||
| 1226 | |||
| 1227 | static struct clk mstick1_clk = { | ||
| 1228 | .name = "mstick1_clk", | ||
| 1229 | .parent = &ipg_clk, | ||
| 1230 | .enable = _clk_mstick1_enable, | ||
| 1231 | .disable = _clk_mstick1_disable, | ||
| 1232 | }; | ||
| 1233 | |||
| 1234 | static struct clk wdog_clk = { | ||
| 1235 | .name = "wdog_clk", | ||
| 1236 | .parent = &ipg_clk, | ||
| 1237 | .enable = _clk_enable, | ||
| 1238 | .enable_reg = CCM_PCCR1, | ||
| 1239 | .enable_shift = CCM_PCCR1_WDT_OFFSET, | ||
| 1240 | .disable = _clk_disable, | ||
| 1241 | }; | ||
| 1242 | |||
| 1243 | static struct clk gpio_clk = { | ||
| 1244 | .name = "gpio_clk", | ||
| 1245 | .parent = &ipg_clk, | ||
| 1246 | .enable = _clk_enable, | ||
| 1247 | .enable_reg = CCM_PCCR1, | ||
| 1248 | .enable_shift = CCM_PCCR0_GPIO_OFFSET, | ||
| 1249 | .disable = _clk_disable, | ||
| 1250 | }; | ||
| 1251 | |||
| 1252 | static struct clk i2c_clk[] = { | ||
| 1253 | { | ||
| 1254 | .name = "i2c_clk", | ||
| 1255 | .id = 0, | ||
| 1256 | .parent = &ipg_clk, | ||
| 1257 | .enable = _clk_enable, | ||
| 1258 | .enable_reg = CCM_PCCR0, | ||
| 1259 | .enable_shift = CCM_PCCR0_I2C1_OFFSET, | ||
| 1260 | .disable = _clk_disable, | ||
| 1261 | }, { | ||
| 1262 | .name = "i2c_clk", | ||
| 1263 | .id = 1, | ||
| 1264 | .parent = &ipg_clk, | ||
| 1265 | .enable = _clk_enable, | ||
| 1266 | .enable_reg = CCM_PCCR0, | ||
| 1267 | .enable_shift = CCM_PCCR0_I2C2_OFFSET, | ||
| 1268 | .disable = _clk_disable, | ||
| 1269 | }, | ||
| 1270 | }; | ||
| 1271 | |||
| 1272 | static struct clk iim_clk = { | ||
| 1273 | .name = "iim_clk", | ||
| 1274 | .parent = &ipg_clk, | ||
| 1275 | .enable = _clk_enable, | ||
| 1276 | .enable_reg = CCM_PCCR0, | ||
| 1277 | .enable_shift = CCM_PCCR0_IIM_OFFSET, | ||
| 1278 | .disable = _clk_disable, | ||
| 1279 | }; | ||
| 1280 | |||
| 1281 | static struct clk kpp_clk = { | ||
| 1282 | .name = "kpp_clk", | ||
| 1283 | .parent = &ipg_clk, | ||
| 1284 | .enable = _clk_enable, | ||
| 1285 | .enable_reg = CCM_PCCR0, | ||
| 1286 | .enable_shift = CCM_PCCR0_KPP_OFFSET, | ||
| 1287 | .disable = _clk_disable, | ||
| 1288 | }; | ||
| 1289 | |||
| 1290 | static struct clk owire_clk = { | ||
| 1291 | .name = "owire_clk", | ||
| 1292 | .parent = &ipg_clk, | ||
| 1293 | .enable = _clk_enable, | ||
| 1294 | .enable_reg = CCM_PCCR0, | ||
| 1295 | .enable_shift = CCM_PCCR0_OWIRE_OFFSET, | ||
| 1296 | .disable = _clk_disable, | ||
| 1297 | }; | ||
| 1298 | |||
| 1299 | static struct clk rtc_clk = { | ||
| 1300 | .name = "rtc_clk", | ||
| 1301 | .parent = &ipg_clk, | ||
| 1302 | .enable = _clk_enable, | ||
| 1303 | .enable_reg = CCM_PCCR0, | ||
| 1304 | .enable_shift = CCM_PCCR0_RTC_OFFSET, | ||
| 1305 | .disable = _clk_disable, | ||
| 1306 | }; | ||
| 1307 | |||
| 1308 | static struct clk scc_clk = { | ||
| 1309 | .name = "scc_clk", | ||
| 1310 | .parent = &ipg_clk, | ||
| 1311 | .enable = _clk_enable, | ||
| 1312 | .enable_reg = CCM_PCCR0, | ||
| 1313 | .enable_shift = CCM_PCCR0_SCC_OFFSET, | ||
| 1314 | .disable = _clk_disable, | ||
| 1315 | }; | ||
| 1316 | |||
| 1317 | static unsigned long _clk_clko_round_rate(struct clk *clk, unsigned long rate) | ||
| 1318 | { | ||
| 1319 | u32 div; | ||
| 1320 | unsigned long parent_rate; | ||
| 1321 | |||
| 1322 | parent_rate = clk_get_rate(clk->parent); | ||
| 1323 | div = parent_rate / rate; | ||
| 1324 | if (parent_rate % rate) | ||
| 1325 | div++; | ||
| 1326 | |||
| 1327 | if (div > 8) | ||
| 1328 | div = 8; | ||
| 1329 | |||
| 1330 | return parent_rate / div; | ||
| 1331 | } | ||
| 1332 | |||
| 1333 | static int _clk_clko_set_rate(struct clk *clk, unsigned long rate) | ||
| 1334 | { | ||
| 1335 | u32 reg; | ||
| 1336 | u32 div; | ||
| 1337 | unsigned long parent_rate; | ||
| 1338 | |||
| 1339 | parent_rate = clk_get_rate(clk->parent); | ||
| 1340 | |||
| 1341 | div = parent_rate / rate; | ||
| 1342 | |||
| 1343 | if (div > 8 || div < 1 || ((parent_rate / div) != rate)) | ||
| 1344 | return -EINVAL; | ||
| 1345 | div--; | ||
| 1346 | |||
| 1347 | reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKODIV_MASK; | ||
| 1348 | reg |= div << CCM_PCDR0_CLKODIV_OFFSET; | ||
| 1349 | __raw_writel(reg, CCM_PCDR0); | ||
| 1350 | |||
| 1351 | return 0; | ||
| 1352 | } | ||
| 1353 | |||
| 1354 | static unsigned long _clk_clko_recalc(struct clk *clk) | ||
| 1355 | { | ||
| 1356 | u32 div; | ||
| 1357 | unsigned long parent_rate; | ||
| 1358 | |||
| 1359 | parent_rate = clk_get_rate(clk->parent); | ||
| 1360 | |||
| 1361 | div = __raw_readl(CCM_PCDR0) & CCM_PCDR0_CLKODIV_MASK >> | ||
| 1362 | CCM_PCDR0_CLKODIV_OFFSET; | ||
| 1363 | div++; | ||
| 1364 | |||
| 1365 | return parent_rate / div; | ||
| 1366 | } | ||
| 1367 | |||
| 1368 | static int _clk_clko_set_parent(struct clk *clk, struct clk *parent) | ||
| 1369 | { | ||
| 1370 | u32 reg; | ||
| 1371 | |||
| 1372 | reg = __raw_readl(CCM_CCSR) & ~CCM_CCSR_CLKOSEL_MASK; | ||
| 1373 | |||
| 1374 | if (parent == &ckil_clk) | ||
| 1375 | reg |= 0 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1376 | else if (parent == &ckih_clk) | ||
| 1377 | reg |= 2 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1378 | else if (parent == mpll_clk.parent) | ||
| 1379 | reg |= 3 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1380 | else if (parent == spll_clk.parent) | ||
| 1381 | reg |= 4 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1382 | else if (parent == &mpll_clk) | ||
| 1383 | reg |= 5 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1384 | else if (parent == &spll_clk) | ||
| 1385 | reg |= 6 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1386 | else if (parent == &cpu_clk) | ||
| 1387 | reg |= 7 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1388 | else if (parent == &ahb_clk) | ||
| 1389 | reg |= 8 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1390 | else if (parent == &ipg_clk) | ||
| 1391 | reg |= 9 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1392 | else if (parent == &per_clk[0]) | ||
| 1393 | reg |= 0xA << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1394 | else if (parent == &per_clk[1]) | ||
| 1395 | reg |= 0xB << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1396 | else if (parent == &per_clk[2]) | ||
| 1397 | reg |= 0xC << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1398 | else if (parent == &per_clk[3]) | ||
| 1399 | reg |= 0xD << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1400 | else if (parent == &ssi1_clk[0]) | ||
| 1401 | reg |= 0xE << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1402 | else if (parent == &ssi2_clk[0]) | ||
| 1403 | reg |= 0xF << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1404 | else if (parent == &nfc_clk) | ||
| 1405 | reg |= 0x10 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1406 | else if (parent == &mstick1_clk) | ||
| 1407 | reg |= 0x11 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1408 | else if (parent == &vpu_clk) | ||
| 1409 | reg |= 0x12 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1410 | else if (parent == &usb_clk[0]) | ||
| 1411 | reg |= 0x15 << CCM_CCSR_CLKOSEL_OFFSET; | ||
| 1412 | else | ||
| 1413 | return -EINVAL; | ||
| 1414 | |||
| 1415 | __raw_writel(reg, CCM_CCSR); | ||
| 1416 | |||
| 1417 | return 0; | ||
| 1418 | } | ||
| 1419 | |||
| 1420 | static int _clk_clko_enable(struct clk *clk) | ||
| 1421 | { | ||
| 1422 | u32 reg; | ||
| 1423 | |||
| 1424 | reg = __raw_readl(CCM_PCDR0) | CCM_PCDR0_CLKO_EN; | ||
| 1425 | __raw_writel(reg, CCM_PCDR0); | ||
| 1426 | |||
| 1427 | return 0; | ||
| 1428 | } | ||
| 1429 | |||
| 1430 | static void _clk_clko_disable(struct clk *clk) | ||
| 1431 | { | ||
| 1432 | u32 reg; | ||
| 1433 | |||
| 1434 | reg = __raw_readl(CCM_PCDR0) & ~CCM_PCDR0_CLKO_EN; | ||
| 1435 | __raw_writel(reg, CCM_PCDR0); | ||
| 1436 | } | ||
| 1437 | |||
| 1438 | static struct clk clko_clk = { | ||
| 1439 | .name = "clko_clk", | ||
| 1440 | .get_rate = _clk_clko_recalc, | ||
| 1441 | .set_rate = _clk_clko_set_rate, | ||
| 1442 | .round_rate = _clk_clko_round_rate, | ||
| 1443 | .set_parent = _clk_clko_set_parent, | ||
| 1444 | .enable = _clk_clko_enable, | ||
| 1445 | .disable = _clk_clko_disable, | ||
| 1446 | }; | ||
| 1447 | |||
| 1448 | static struct clk *mxc_clks[] = { | ||
| 1449 | &ckih_clk, | ||
| 1450 | &ckil_clk, | ||
| 1451 | &mpll_clk, | ||
| 1452 | &mpll_main_clk[0], | ||
| 1453 | &mpll_main_clk[1], | ||
| 1454 | &spll_clk, | ||
| 1455 | &cpu_clk, | ||
| 1456 | &ahb_clk, | ||
| 1457 | &ipg_clk, | ||
| 1458 | &per_clk[0], | ||
| 1459 | &per_clk[1], | ||
| 1460 | &per_clk[2], | ||
| 1461 | &per_clk[3], | ||
| 1462 | &clko_clk, | ||
| 1463 | &uart1_clk[0], | ||
| 1464 | &uart1_clk[1], | ||
| 1465 | &uart2_clk[0], | ||
| 1466 | &uart2_clk[1], | ||
| 1467 | &uart3_clk[0], | ||
| 1468 | &uart3_clk[1], | ||
| 1469 | &uart4_clk[0], | ||
| 1470 | &uart4_clk[1], | ||
| 1471 | &uart5_clk[0], | ||
| 1472 | &uart5_clk[1], | ||
| 1473 | &uart6_clk[0], | ||
| 1474 | &uart6_clk[1], | ||
| 1475 | &gpt1_clk[0], | ||
| 1476 | &gpt1_clk[1], | ||
| 1477 | &gpt2_clk[0], | ||
| 1478 | &gpt2_clk[1], | ||
| 1479 | &gpt3_clk[0], | ||
| 1480 | &gpt3_clk[1], | ||
| 1481 | &gpt4_clk[0], | ||
| 1482 | &gpt4_clk[1], | ||
| 1483 | &gpt5_clk[0], | ||
| 1484 | &gpt5_clk[1], | ||
| 1485 | &gpt6_clk[0], | ||
| 1486 | &gpt6_clk[1], | ||
| 1487 | &pwm_clk[0], | ||
| 1488 | &pwm_clk[1], | ||
| 1489 | &sdhc1_clk[0], | ||
| 1490 | &sdhc1_clk[1], | ||
| 1491 | &sdhc2_clk[0], | ||
| 1492 | &sdhc2_clk[1], | ||
| 1493 | &sdhc3_clk[0], | ||
| 1494 | &sdhc3_clk[1], | ||
| 1495 | &cspi1_clk[0], | ||
| 1496 | &cspi1_clk[1], | ||
| 1497 | &cspi2_clk[0], | ||
| 1498 | &cspi2_clk[1], | ||
| 1499 | &cspi3_clk[0], | ||
| 1500 | &cspi3_clk[1], | ||
| 1501 | &lcdc_clk[0], | ||
| 1502 | &lcdc_clk[1], | ||
| 1503 | &lcdc_clk[2], | ||
| 1504 | &csi_clk[0], | ||
| 1505 | &csi_clk[1], | ||
| 1506 | &usb_clk[0], | ||
| 1507 | &usb_clk[1], | ||
| 1508 | &ssi1_clk[0], | ||
| 1509 | &ssi1_clk[1], | ||
| 1510 | &ssi2_clk[0], | ||
| 1511 | &ssi2_clk[1], | ||
| 1512 | &nfc_clk, | ||
| 1513 | &vpu_clk, | ||
| 1514 | &dma_clk, | ||
| 1515 | &rtic_clk, | ||
| 1516 | &brom_clk, | ||
| 1517 | &emma_clk, | ||
| 1518 | &slcdc_clk, | ||
| 1519 | &fec_clk, | ||
| 1520 | &emi_clk, | ||
| 1521 | &sahara2_clk, | ||
| 1522 | &ata_clk, | ||
| 1523 | &mstick1_clk, | ||
| 1524 | &wdog_clk, | ||
| 1525 | &gpio_clk, | ||
| 1526 | &i2c_clk[0], | ||
| 1527 | &i2c_clk[1], | ||
| 1528 | &iim_clk, | ||
| 1529 | &kpp_clk, | ||
| 1530 | &owire_clk, | ||
| 1531 | &rtc_clk, | ||
| 1532 | &scc_clk, | ||
| 1533 | }; | ||
| 1534 | |||
| 1535 | void __init change_external_low_reference(unsigned long new_ref) | ||
| 1536 | { | ||
| 1537 | external_low_reference = new_ref; | ||
| 1538 | } | ||
| 1539 | |||
| 1540 | unsigned long __init clk_early_get_timer_rate(void) | ||
| 1541 | { | ||
| 1542 | return clk_get_rate(&per_clk[0]); | ||
| 1543 | } | ||
| 1544 | |||
| 1545 | static void __init probe_mxc_clocks(void) | ||
| 1546 | { | ||
| 1547 | int i; | ||
| 1548 | 676 | ||
| 1549 | if (mx27_revision() >= CHIP_REV_2_0) { | 677 | if (mx27_revision() >= CHIP_REV_2_0) { |
| 1550 | if (CSCR() & 0x8000) | 678 | if (cscr & CCM_CSCR_ARM_SRC) |
| 1551 | cpu_clk.parent = &mpll_main_clk[0]; | 679 | cpu_clk.parent = &mpll_main1_clk; |
| 1552 | 680 | ||
| 1553 | if (!(CSCR() & 0x00800000)) | 681 | if (!(cscr & CCM_CSCR_SSI2)) |
| 1554 | ssi2_clk[0].parent = &spll_clk; | 682 | ssi1_clk.parent = &spll_clk; |
| 1555 | 683 | ||
| 1556 | if (!(CSCR() & 0x00400000)) | 684 | if (!(cscr & CCM_CSCR_SSI1)) |
| 1557 | ssi1_clk[0].parent = &spll_clk; | 685 | ssi1_clk.parent = &spll_clk; |
| 1558 | 686 | ||
| 1559 | if (!(CSCR() & 0x00200000)) | 687 | if (!(cscr & CCM_CSCR_VPU)) |
| 1560 | vpu_clk.parent = &spll_clk; | 688 | vpu_clk.parent = &spll_clk; |
| 1561 | } else { | 689 | } else { |
| 1562 | cpu_clk.parent = &mpll_clk; | 690 | cpu_clk.parent = &mpll_clk; |
| @@ -1565,11 +693,13 @@ static void __init probe_mxc_clocks(void) | |||
| 1565 | cpu_clk.set_rate = NULL; | 693 | cpu_clk.set_rate = NULL; |
| 1566 | ahb_clk.parent = &mpll_clk; | 694 | ahb_clk.parent = &mpll_clk; |
| 1567 | 695 | ||
| 1568 | for (i = 0; i < sizeof(per_clk) / sizeof(per_clk[0]); i++) | 696 | per1_clk.parent = &mpll_clk; |
| 1569 | per_clk[i].parent = &mpll_clk; | 697 | per2_clk.parent = &mpll_clk; |
| 698 | per3_clk.parent = &mpll_clk; | ||
| 699 | per4_clk.parent = &mpll_clk; | ||
| 1570 | 700 | ||
| 1571 | ssi1_clk[0].parent = &mpll_clk; | 701 | ssi1_clk.parent = &mpll_clk; |
| 1572 | ssi2_clk[0].parent = &mpll_clk; | 702 | ssi2_clk.parent = &mpll_clk; |
| 1573 | 703 | ||
| 1574 | vpu_clk.parent = &mpll_clk; | 704 | vpu_clk.parent = &mpll_clk; |
| 1575 | } | 705 | } |
| @@ -1579,47 +709,47 @@ static void __init probe_mxc_clocks(void) | |||
| 1579 | * must be called very early to get information about the | 709 | * must be called very early to get information about the |
| 1580 | * available clock rate when the timer framework starts | 710 | * available clock rate when the timer framework starts |
| 1581 | */ | 711 | */ |
| 1582 | int __init mxc_clocks_init(unsigned long fref) | 712 | int __init mx27_clocks_init(unsigned long fref) |
| 1583 | { | 713 | { |
| 1584 | u32 cscr; | 714 | u32 cscr = __raw_readl(CCM_CSCR); |
| 1585 | struct clk **clkp; | 715 | int i; |
| 1586 | 716 | ||
| 1587 | external_high_reference = fref; | 717 | external_high_reference = fref; |
| 1588 | 718 | ||
| 1589 | /* detect clock reference for both system PLL */ | 719 | /* detect clock reference for both system PLLs */ |
| 1590 | cscr = CSCR(); | ||
| 1591 | if (cscr & CCM_CSCR_MCU) | 720 | if (cscr & CCM_CSCR_MCU) |
| 1592 | mpll_clk.parent = &ckih_clk; | 721 | mpll_clk.parent = &ckih_clk; |
| 1593 | else | 722 | else |
| 1594 | mpll_clk.parent = &ckil_clk; | 723 | mpll_clk.parent = &fpm_clk; |
| 1595 | 724 | ||
| 1596 | if (cscr & CCM_CSCR_SP) | 725 | if (cscr & CCM_CSCR_SP) |
| 1597 | spll_clk.parent = &ckih_clk; | 726 | spll_clk.parent = &ckih_clk; |
| 1598 | else | 727 | else |
| 1599 | spll_clk.parent = &ckil_clk; | 728 | spll_clk.parent = &fpm_clk; |
| 1600 | 729 | ||
| 1601 | probe_mxc_clocks(); | 730 | to2_adjust_clocks(); |
| 1602 | 731 | ||
| 1603 | per_clk[0].enable(&per_clk[0]); | 732 | for (i = 0; i < ARRAY_SIZE(lookups); i++) |
| 1604 | gpt1_clk[1].enable(&gpt1_clk[1]); | 733 | clkdev_add(&lookups[i]); |
| 1605 | 734 | ||
| 1606 | for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) | 735 | /* Turn off all clocks we do not need */ |
| 1607 | clk_register(*clkp); | 736 | __raw_writel(0, CCM_PCCR0); |
| 737 | __raw_writel((1 << 10) | (1 << 19), CCM_PCCR1); | ||
| 1608 | 738 | ||
| 1609 | /* Turn off all possible clocks */ | ||
| 1610 | __raw_writel(CCM_PCCR0_GPT1_MASK, CCM_PCCR0); | ||
| 1611 | __raw_writel(CCM_PCCR1_PERCLK1_MASK | CCM_PCCR1_HCLK_EMI_MASK, | ||
| 1612 | CCM_PCCR1); | ||
| 1613 | spll_clk.disable(&spll_clk); | 739 | spll_clk.disable(&spll_clk); |
| 1614 | 740 | ||
| 1615 | /* This will propagate to all children and init all the clock rates */ | 741 | /* enable basic clocks */ |
| 1616 | 742 | clk_enable(&per1_clk); | |
| 1617 | clk_enable(&emi_clk); | ||
| 1618 | clk_enable(&gpio_clk); | 743 | clk_enable(&gpio_clk); |
| 744 | clk_enable(&emi_clk); | ||
| 1619 | clk_enable(&iim_clk); | 745 | clk_enable(&iim_clk); |
| 1620 | clk_enable(&gpt1_clk[0]); | 746 | |
| 1621 | #ifdef CONFIG_DEBUG_LL_CONSOLE | 747 | #ifdef CONFIG_DEBUG_LL_CONSOLE |
| 1622 | clk_enable(&uart1_clk[0]); | 748 | clk_enable(&uart1_clk); |
| 1623 | #endif | 749 | #endif |
| 750 | |||
| 751 | mxc_timer_init(&gpt1_clk); | ||
| 752 | |||
| 1624 | return 0; | 753 | return 0; |
| 1625 | } | 754 | } |
| 755 | |||
diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-mx2/cpu_imx27.c index 239308fe6652..d9e3bf9644c9 100644 --- a/arch/arm/mach-mx2/cpu_imx27.c +++ b/arch/arm/mach-mx2/cpu_imx27.c | |||
| @@ -26,11 +26,11 @@ | |||
| 26 | 26 | ||
| 27 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 28 | 28 | ||
| 29 | #include "crm_regs.h" | ||
| 30 | |||
| 31 | static int cpu_silicon_rev = -1; | 29 | static int cpu_silicon_rev = -1; |
| 32 | static int cpu_partnumber; | 30 | static int cpu_partnumber; |
| 33 | 31 | ||
| 32 | #define SYS_CHIP_ID 0x00 /* The offset of CHIP ID register */ | ||
| 33 | |||
| 34 | static void query_silicon_parameter(void) | 34 | static void query_silicon_parameter(void) |
| 35 | { | 35 | { |
| 36 | u32 val; | 36 | u32 val; |
diff --git a/arch/arm/mach-mx2/crm_regs.h b/arch/arm/mach-mx2/crm_regs.h index 94644cd0a0fc..749de76b3f95 100644 --- a/arch/arm/mach-mx2/crm_regs.h +++ b/arch/arm/mach-mx2/crm_regs.h | |||
| @@ -38,42 +38,36 @@ | |||
| 38 | #define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) | 38 | #define CCM_PMCOUNT (IO_ADDRESS(CCM_BASE_ADDR) + 0x30) |
| 39 | #define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) | 39 | #define CCM_WKGDCTL (IO_ADDRESS(CCM_BASE_ADDR) + 0x34) |
| 40 | 40 | ||
| 41 | #define CCM_CSCR_USB_OFFSET 28 | 41 | #define CCM_CSCR_PRESC_OFFSET 29 |
| 42 | #define CCM_CSCR_USB_MASK (0x7 << 28) | 42 | #define CCM_CSCR_PRESC_MASK (0x7 << CCM_CSCR_PRESC_OFFSET) |
| 43 | |||
| 44 | #define CCM_CSCR_USB_OFFSET 26 | ||
| 45 | #define CCM_CSCR_USB_MASK (0x7 << CCM_CSCR_USB_OFFSET) | ||
| 43 | #define CCM_CSCR_SD_OFFSET 24 | 46 | #define CCM_CSCR_SD_OFFSET 24 |
| 44 | #define CCM_CSCR_SD_MASK (0x3 << 24) | 47 | #define CCM_CSCR_SD_MASK (0x3 << CCM_CSCR_SD_OFFSET) |
| 45 | #define CCM_CSCR_SSI2 (1 << 23) | 48 | #define CCM_CSCR_SPLLRES (1 << 22) |
| 46 | #define CCM_CSCR_SSI2_OFFSET 23 | 49 | #define CCM_CSCR_MPLLRES (1 << 21) |
| 47 | #define CCM_CSCR_SSI1 (1 << 22) | 50 | #define CCM_CSCR_SSI2_OFFSET 20 |
| 48 | #define CCM_CSCR_SSI1_OFFSET 22 | 51 | #define CCM_CSCR_SSI2 (1 << CCM_CSCR_SSI2_OFFSET) |
| 49 | #define CCM_CSCR_VPU (1 << 21) | 52 | #define CCM_CSCR_SSI1_OFFSET 19 |
| 50 | #define CCM_CSCR_VPU_OFFSET 21 | 53 | #define CCM_CSCR_SSI1 (1 << CCM_CSCR_SSI1_OFFSET) |
| 51 | #define CCM_CSCR_MSHC (1 << 20) | 54 | #define CCM_CSCR_FIR_OFFSET 18 |
| 52 | #define CCM_CSCR_SPLLRES (1 << 19) | 55 | #define CCM_CSCR_FIR (1 << CCM_CSCR_FIR_OFFSET) |
| 53 | #define CCM_CSCR_MPLLRES (1 << 18) | ||
| 54 | #define CCM_CSCR_SP (1 << 17) | 56 | #define CCM_CSCR_SP (1 << 17) |
| 55 | #define CCM_CSCR_MCU (1 << 16) | 57 | #define CCM_CSCR_MCU (1 << 16) |
| 56 | /* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/ | 58 | #define CCM_CSCR_BCLK_OFFSET 10 |
| 57 | #define CCM_CSCR_ARM_SRC (1 << 15) | 59 | #define CCM_CSCR_BCLK_MASK (0xf << CCM_CSCR_BCLK_OFFSET) |
| 58 | #define CCM_CSCR_ARM_OFFSET 12 | 60 | #define CCM_CSCR_IPDIV_OFFSET 9 |
| 59 | #define CCM_CSCR_ARM_MASK (0x3 << 12) | 61 | #define CCM_CSCR_IPDIV (1 << CCM_CSCR_IPDIV_OFFSET) |
| 60 | /* CCM_CSCR_ARM_xxx just be avaliable on i.MX27 TO2*/ | 62 | |
| 61 | #define CCM_CSCR_PRESC_OFFSET 13 | ||
| 62 | #define CCM_CSCR_PRESC_MASK (0x7 << 13) | ||
| 63 | #define CCM_CSCR_BCLK_OFFSET 9 | ||
| 64 | #define CCM_CSCR_BCLK_MASK (0xf << 9) | ||
| 65 | #define CCM_CSCR_IPDIV_OFFSET 8 | ||
| 66 | #define CCM_CSCR_IPDIV (1 << 8) | ||
| 67 | /* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/ | ||
| 68 | #define CCM_CSCR_AHB_OFFSET 8 | ||
| 69 | #define CCM_CSCR_AHB_MASK (0x3 << 8) | ||
| 70 | /* CCM_CSCR_AHB_xxx just be avaliable on i.MX27 TO2*/ | ||
| 71 | #define CCM_CSCR_OSC26MDIV (1 << 4) | 63 | #define CCM_CSCR_OSC26MDIV (1 << 4) |
| 72 | #define CCM_CSCR_OSC26M (1 << 3) | 64 | #define CCM_CSCR_OSC26M (1 << 3) |
| 73 | #define CCM_CSCR_FPM (1 << 2) | 65 | #define CCM_CSCR_FPM (1 << 2) |
| 74 | #define CCM_CSCR_SPEN (1 << 1) | 66 | #define CCM_CSCR_SPEN (1 << 1) |
| 75 | #define CCM_CSCR_MPEN 1 | 67 | #define CCM_CSCR_MPEN 1 |
| 76 | 68 | ||
| 69 | |||
| 70 | |||
| 77 | #define CCM_MPCTL0_CPLM (1 << 31) | 71 | #define CCM_MPCTL0_CPLM (1 << 31) |
| 78 | #define CCM_MPCTL0_PD_OFFSET 26 | 72 | #define CCM_MPCTL0_PD_OFFSET 26 |
| 79 | #define CCM_MPCTL0_PD_MASK (0xf << 26) | 73 | #define CCM_MPCTL0_PD_MASK (0xf << 26) |
| @@ -109,25 +103,14 @@ | |||
| 109 | 103 | ||
| 110 | #define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26 | 104 | #define CCM_PCDR0_SSI2BAUDDIV_OFFSET 26 |
| 111 | #define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26) | 105 | #define CCM_PCDR0_SSI2BAUDDIV_MASK (0x3f << 26) |
| 112 | #define CCM_PCDR0_CLKO_EN 25 | ||
| 113 | #define CCM_PCDR0_CLKODIV_OFFSET 22 | ||
| 114 | #define CCM_PCDR0_CLKODIV_MASK (0x7 << 22) | ||
| 115 | #define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16 | 106 | #define CCM_PCDR0_SSI1BAUDDIV_OFFSET 16 |
| 116 | #define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16) | 107 | #define CCM_PCDR0_SSI1BAUDDIV_MASK (0x3f << 16) |
| 117 | /*The difinition for i.MX27 TO2*/ | ||
| 118 | #define CCM_PCDR0_VPUDIV2_OFFSET 10 | ||
| 119 | #define CCM_PCDR0_VPUDIV2_MASK (0x3f << 10) | ||
| 120 | #define CCM_PCDR0_NFCDIV2_OFFSET 6 | ||
| 121 | #define CCM_PCDR0_NFCDIV2_MASK (0xf << 6) | ||
| 122 | #define CCM_PCDR0_MSHCDIV2_MASK 0x3f | ||
| 123 | /*The difinition for i.MX27 TO2*/ | ||
| 124 | #define CCM_PCDR0_NFCDIV_OFFSET 12 | 108 | #define CCM_PCDR0_NFCDIV_OFFSET 12 |
| 125 | #define CCM_PCDR0_NFCDIV_MASK (0xf << 12) | 109 | #define CCM_PCDR0_NFCDIV_MASK (0xf << 12) |
| 126 | #define CCM_PCDR0_VPUDIV_OFFSET 8 | 110 | #define CCM_PCDR0_48MDIV_OFFSET 5 |
| 127 | #define CCM_PCDR0_VPUDIV_MASK (0xf << 8) | 111 | #define CCM_PCDR0_48MDIV_MASK (0x7 << CCM_PCDR0_48MDIV_OFFSET) |
| 128 | #define CCM_PCDR0_MSHCDIV_OFFSET 0 | 112 | #define CCM_PCDR0_FIRIDIV_OFFSET 0 |
| 129 | #define CCM_PCDR0_MSHCDIV_MASK 0x1f | 113 | #define CCM_PCDR0_FIRIDIV_MASK 0x1f |
| 130 | |||
| 131 | #define CCM_PCDR1_PERDIV4_OFFSET 24 | 114 | #define CCM_PCDR1_PERDIV4_OFFSET 24 |
| 132 | #define CCM_PCDR1_PERDIV4_MASK (0x3f << 24) | 115 | #define CCM_PCDR1_PERDIV4_MASK (0x3f << 24) |
| 133 | #define CCM_PCDR1_PERDIV3_OFFSET 16 | 116 | #define CCM_PCDR1_PERDIV3_OFFSET 16 |
| @@ -137,133 +120,135 @@ | |||
| 137 | #define CCM_PCDR1_PERDIV1_OFFSET 0 | 120 | #define CCM_PCDR1_PERDIV1_OFFSET 0 |
| 138 | #define CCM_PCDR1_PERDIV1_MASK 0x3f | 121 | #define CCM_PCDR1_PERDIV1_MASK 0x3f |
| 139 | 122 | ||
| 140 | #define CCM_PCCR0_CSPI1_OFFSET 31 | 123 | #define CCM_PCCR_HCLK_CSI_OFFSET 31 |
| 141 | #define CCM_PCCR0_CSPI1_MASK (1 << 31) | 124 | #define CCM_PCCR_HCLK_CSI_REG CCM_PCCR0 |
| 142 | #define CCM_PCCR0_CSPI2_OFFSET 30 | 125 | #define CCM_PCCR_HCLK_DMA_OFFSET 30 |
| 143 | #define CCM_PCCR0_CSPI2_MASK (1 << 30) | 126 | #define CCM_PCCR_HCLK_DMA_REG CCM_PCCR0 |
| 144 | #define CCM_PCCR0_CSPI3_OFFSET 29 | 127 | #define CCM_PCCR_HCLK_BROM_OFFSET 28 |
| 145 | #define CCM_PCCR0_CSPI3_MASK (1 << 29) | 128 | #define CCM_PCCR_HCLK_BROM_REG CCM_PCCR0 |
| 146 | #define CCM_PCCR0_DMA_OFFSET 28 | 129 | #define CCM_PCCR_HCLK_EMMA_OFFSET 27 |
| 147 | #define CCM_PCCR0_DMA_MASK (1 << 28) | 130 | #define CCM_PCCR_HCLK_EMMA_REG CCM_PCCR0 |
| 148 | #define CCM_PCCR0_EMMA_OFFSET 27 | 131 | #define CCM_PCCR_HCLK_LCDC_OFFSET 26 |
| 149 | #define CCM_PCCR0_EMMA_MASK (1 << 27) | 132 | #define CCM_PCCR_HCLK_LCDC_REG CCM_PCCR0 |
| 150 | #define CCM_PCCR0_FEC_OFFSET 26 | 133 | #define CCM_PCCR_HCLK_SLCDC_OFFSET 25 |
| 151 | #define CCM_PCCR0_FEC_MASK (1 << 26) | 134 | #define CCM_PCCR_HCLK_SLCDC_REG CCM_PCCR0 |
| 152 | #define CCM_PCCR0_GPIO_OFFSET 25 | 135 | #define CCM_PCCR_HCLK_USBOTG_OFFSET 24 |
| 153 | #define CCM_PCCR0_GPIO_MASK (1 << 25) | 136 | #define CCM_PCCR_HCLK_USBOTG_REG CCM_PCCR0 |
| 154 | #define CCM_PCCR0_GPT1_OFFSET 24 | 137 | #define CCM_PCCR_HCLK_BMI_OFFSET 23 |
| 155 | #define CCM_PCCR0_GPT1_MASK (1 << 24) | 138 | #define CCM_PCCR_BMI_MASK (1 << CCM_PCCR_BMI_MASK) |
| 156 | #define CCM_PCCR0_GPT2_OFFSET 23 | 139 | #define CCM_PCCR_HCLK_BMI_REG CCM_PCCR0 |
| 157 | #define CCM_PCCR0_GPT2_MASK (1 << 23) | 140 | #define CCM_PCCR_PERCLK4_OFFSET 22 |
| 158 | #define CCM_PCCR0_GPT3_OFFSET 22 | 141 | #define CCM_PCCR_PERCLK4_REG CCM_PCCR0 |
| 159 | #define CCM_PCCR0_GPT3_MASK (1 << 22) | 142 | #define CCM_PCCR_SLCDC_OFFSET 21 |
| 160 | #define CCM_PCCR0_GPT4_OFFSET 21 | 143 | #define CCM_PCCR_SLCDC_REG CCM_PCCR0 |
| 161 | #define CCM_PCCR0_GPT4_MASK (1 << 21) | 144 | #define CCM_PCCR_FIRI_BAUD_OFFSET 20 |
| 162 | #define CCM_PCCR0_GPT5_OFFSET 20 | 145 | #define CCM_PCCR_FIRI_BAUD_MASK (1 << CCM_PCCR_FIRI_BAUD_MASK) |
| 163 | #define CCM_PCCR0_GPT5_MASK (1 << 20) | 146 | #define CCM_PCCR_FIRI_BAUD_REG CCM_PCCR0 |
| 164 | #define CCM_PCCR0_GPT6_OFFSET 19 | 147 | #define CCM_PCCR_NFC_OFFSET 19 |
| 165 | #define CCM_PCCR0_GPT6_MASK (1 << 19) | 148 | #define CCM_PCCR_NFC_REG CCM_PCCR0 |
| 166 | #define CCM_PCCR0_I2C1_OFFSET 18 | 149 | #define CCM_PCCR_LCDC_OFFSET 18 |
| 167 | #define CCM_PCCR0_I2C1_MASK (1 << 18) | 150 | #define CCM_PCCR_LCDC_REG CCM_PCCR0 |
| 168 | #define CCM_PCCR0_I2C2_OFFSET 17 | 151 | #define CCM_PCCR_SSI1_BAUD_OFFSET 17 |
| 169 | #define CCM_PCCR0_I2C2_MASK (1 << 17) | 152 | #define CCM_PCCR_SSI1_BAUD_REG CCM_PCCR0 |
| 170 | #define CCM_PCCR0_IIM_OFFSET 16 | 153 | #define CCM_PCCR_SSI2_BAUD_OFFSET 16 |
| 171 | #define CCM_PCCR0_IIM_MASK (1 << 16) | 154 | #define CCM_PCCR_SSI2_BAUD_REG CCM_PCCR0 |
| 172 | #define CCM_PCCR0_KPP_OFFSET 15 | 155 | #define CCM_PCCR_EMMA_OFFSET 15 |
| 173 | #define CCM_PCCR0_KPP_MASK (1 << 15) | 156 | #define CCM_PCCR_EMMA_REG CCM_PCCR0 |
| 174 | #define CCM_PCCR0_LCDC_OFFSET 14 | 157 | #define CCM_PCCR_USBOTG_OFFSET 14 |
| 175 | #define CCM_PCCR0_LCDC_MASK (1 << 14) | 158 | #define CCM_PCCR_USBOTG_REG CCM_PCCR0 |
| 176 | #define CCM_PCCR0_MSHC_OFFSET 13 | 159 | #define CCM_PCCR_DMA_OFFSET 13 |
| 177 | #define CCM_PCCR0_MSHC_MASK (1 << 13) | 160 | #define CCM_PCCR_DMA_REG CCM_PCCR0 |
| 178 | #define CCM_PCCR0_OWIRE_OFFSET 12 | 161 | #define CCM_PCCR_I2C1_OFFSET 12 |
| 179 | #define CCM_PCCR0_OWIRE_MASK (1 << 12) | 162 | #define CCM_PCCR_I2C1_REG CCM_PCCR0 |
| 180 | #define CCM_PCCR0_PWM_OFFSET 11 | 163 | #define CCM_PCCR_GPIO_OFFSET 11 |
| 181 | #define CCM_PCCR0_PWM_MASK (1 << 11) | 164 | #define CCM_PCCR_GPIO_REG CCM_PCCR0 |
| 182 | #define CCM_PCCR0_RTC_OFFSET 9 | 165 | #define CCM_PCCR_SDHC2_OFFSET 10 |
| 183 | #define CCM_PCCR0_RTC_MASK (1 << 9) | 166 | #define CCM_PCCR_SDHC2_REG CCM_PCCR0 |
| 184 | #define CCM_PCCR0_RTIC_OFFSET 8 | 167 | #define CCM_PCCR_SDHC1_OFFSET 9 |
| 185 | #define CCM_PCCR0_RTIC_MASK (1 << 8) | 168 | #define CCM_PCCR_SDHC1_REG CCM_PCCR0 |
| 186 | #define CCM_PCCR0_SAHARA_OFFSET 7 | 169 | #define CCM_PCCR_FIRI_OFFSET 8 |
| 187 | #define CCM_PCCR0_SAHARA_MASK (1 << 7) | 170 | #define CCM_PCCR_FIRI_MASK (1 << CCM_PCCR_BAUD_MASK) |
| 188 | #define CCM_PCCR0_SCC_OFFSET 6 | 171 | #define CCM_PCCR_FIRI_REG CCM_PCCR0 |
| 189 | #define CCM_PCCR0_SCC_MASK (1 << 6) | 172 | #define CCM_PCCR_SSI2_IPG_OFFSET 7 |
| 190 | #define CCM_PCCR0_SDHC1_OFFSET 5 | 173 | #define CCM_PCCR_SSI2_REG CCM_PCCR0 |
| 191 | #define CCM_PCCR0_SDHC1_MASK (1 << 5) | 174 | #define CCM_PCCR_SSI1_IPG_OFFSET 6 |
| 192 | #define CCM_PCCR0_SDHC2_OFFSET 4 | 175 | #define CCM_PCCR_SSI1_REG CCM_PCCR0 |
| 193 | #define CCM_PCCR0_SDHC2_MASK (1 << 4) | 176 | #define CCM_PCCR_CSPI2_OFFSET 5 |
| 194 | #define CCM_PCCR0_SDHC3_OFFSET 3 | 177 | #define CCM_PCCR_CSPI2_REG CCM_PCCR0 |
| 195 | #define CCM_PCCR0_SDHC3_MASK (1 << 3) | 178 | #define CCM_PCCR_CSPI1_OFFSET 4 |
| 196 | #define CCM_PCCR0_SLCDC_OFFSET 2 | 179 | #define CCM_PCCR_CSPI1_REG CCM_PCCR0 |
| 197 | #define CCM_PCCR0_SLCDC_MASK (1 << 2) | 180 | #define CCM_PCCR_UART4_OFFSET 3 |
| 198 | #define CCM_PCCR0_SSI1_IPG_OFFSET 1 | 181 | #define CCM_PCCR_UART4_REG CCM_PCCR0 |
| 199 | #define CCM_PCCR0_SSI1_IPG_MASK (1 << 1) | 182 | #define CCM_PCCR_UART3_OFFSET 2 |
| 200 | #define CCM_PCCR0_SSI2_IPG_OFFSET 0 | 183 | #define CCM_PCCR_UART3_REG CCM_PCCR0 |
| 201 | #define CCM_PCCR0_SSI2_IPG_MASK (1 << 0) | 184 | #define CCM_PCCR_UART2_OFFSET 1 |
| 185 | #define CCM_PCCR_UART2_REG CCM_PCCR0 | ||
| 186 | #define CCM_PCCR_UART1_OFFSET 0 | ||
| 187 | #define CCM_PCCR_UART1_REG CCM_PCCR0 | ||
| 188 | |||
| 189 | #define CCM_PCCR_OWIRE_OFFSET 31 | ||
| 190 | #define CCM_PCCR_OWIRE_REG CCM_PCCR1 | ||
| 191 | #define CCM_PCCR_KPP_OFFSET 30 | ||
| 192 | #define CCM_PCCR_KPP_REG CCM_PCCR1 | ||
| 193 | #define CCM_PCCR_RTC_OFFSET 29 | ||
| 194 | #define CCM_PCCR_RTC_REG CCM_PCCR1 | ||
| 195 | #define CCM_PCCR_PWM_OFFSET 28 | ||
| 196 | #define CCM_PCCR_PWM_REG CCM_PCCR1 | ||
| 197 | #define CCM_PCCR_GPT3_OFFSET 27 | ||
| 198 | #define CCM_PCCR_GPT3_REG CCM_PCCR1 | ||
| 199 | #define CCM_PCCR_GPT2_OFFSET 26 | ||
| 200 | #define CCM_PCCR_GPT2_REG CCM_PCCR1 | ||
| 201 | #define CCM_PCCR_GPT1_OFFSET 25 | ||
| 202 | #define CCM_PCCR_GPT1_REG CCM_PCCR1 | ||
| 203 | #define CCM_PCCR_WDT_OFFSET 24 | ||
| 204 | #define CCM_PCCR_WDT_REG CCM_PCCR1 | ||
| 205 | #define CCM_PCCR_CSPI3_OFFSET 23 | ||
| 206 | #define CCM_PCCR_CSPI3_REG CCM_PCCR1 | ||
| 207 | |||
| 208 | #define CCM_PCCR_CSPI1_MASK (1 << CCM_PCCR_CSPI1_OFFSET) | ||
| 209 | #define CCM_PCCR_CSPI2_MASK (1 << CCM_PCCR_CSPI2_OFFSET) | ||
| 210 | #define CCM_PCCR_CSPI3_MASK (1 << CCM_PCCR_CSPI3_OFFSET) | ||
| 211 | #define CCM_PCCR_DMA_MASK (1 << CCM_PCCR_DMA_OFFSET) | ||
| 212 | #define CCM_PCCR_EMMA_MASK (1 << CCM_PCCR_EMMA_OFFSET) | ||
| 213 | #define CCM_PCCR_GPIO_MASK (1 << CCM_PCCR_GPIO_OFFSET) | ||
| 214 | #define CCM_PCCR_GPT1_MASK (1 << CCM_PCCR_GPT1_OFFSET) | ||
| 215 | #define CCM_PCCR_GPT2_MASK (1 << CCM_PCCR_GPT2_OFFSET) | ||
| 216 | #define CCM_PCCR_GPT3_MASK (1 << CCM_PCCR_GPT3_OFFSET) | ||
| 217 | #define CCM_PCCR_HCLK_BROM_MASK (1 << CCM_PCCR_HCLK_BROM_OFFSET) | ||
| 218 | #define CCM_PCCR_HCLK_CSI_MASK (1 << CCM_PCCR_HCLK_CSI_OFFSET) | ||
| 219 | #define CCM_PCCR_HCLK_DMA_MASK (1 << CCM_PCCR_HCLK_DMA_OFFSET) | ||
| 220 | #define CCM_PCCR_HCLK_EMMA_MASK (1 << CCM_PCCR_HCLK_EMMA_OFFSET) | ||
| 221 | #define CCM_PCCR_HCLK_LCDC_MASK (1 << CCM_PCCR_HCLK_LCDC_OFFSET) | ||
| 222 | #define CCM_PCCR_HCLK_SLCDC_MASK (1 << CCM_PCCR_HCLK_SLCDC_OFFSET) | ||
| 223 | #define CCM_PCCR_HCLK_USBOTG_MASK (1 << CCM_PCCR_HCLK_USBOTG_OFFSET) | ||
| 224 | #define CCM_PCCR_I2C1_MASK (1 << CCM_PCCR_I2C1_OFFSET) | ||
| 225 | #define CCM_PCCR_KPP_MASK (1 << CCM_PCCR_KPP_OFFSET) | ||
| 226 | #define CCM_PCCR_LCDC_MASK (1 << CCM_PCCR_LCDC_OFFSET) | ||
| 227 | #define CCM_PCCR_NFC_MASK (1 << CCM_PCCR_NFC_OFFSET) | ||
| 228 | #define CCM_PCCR_OWIRE_MASK (1 << CCM_PCCR_OWIRE_OFFSET) | ||
| 229 | #define CCM_PCCR_PERCLK4_MASK (1 << CCM_PCCR_PERCLK4_OFFSET) | ||
| 230 | #define CCM_PCCR_PWM_MASK (1 << CCM_PCCR_PWM_OFFSET) | ||
| 231 | #define CCM_PCCR_RTC_MASK (1 << CCM_PCCR_RTC_OFFSET) | ||
| 232 | #define CCM_PCCR_SDHC1_MASK (1 << CCM_PCCR_SDHC1_OFFSET) | ||
| 233 | #define CCM_PCCR_SDHC2_MASK (1 << CCM_PCCR_SDHC2_OFFSET) | ||
| 234 | #define CCM_PCCR_SLCDC_MASK (1 << CCM_PCCR_SLCDC_OFFSET) | ||
| 235 | #define CCM_PCCR_SSI1_BAUD_MASK (1 << CCM_PCCR_SSI1_BAUD_OFFSET) | ||
| 236 | #define CCM_PCCR_SSI1_IPG_MASK (1 << CCM_PCCR_SSI1_IPG_OFFSET) | ||
| 237 | #define CCM_PCCR_SSI2_BAUD_MASK (1 << CCM_PCCR_SSI2_BAUD_OFFSET) | ||
| 238 | #define CCM_PCCR_SSI2_IPG_MASK (1 << CCM_PCCR_SSI2_IPG_OFFSET) | ||
| 239 | #define CCM_PCCR_UART1_MASK (1 << CCM_PCCR_UART1_OFFSET) | ||
| 240 | #define CCM_PCCR_UART2_MASK (1 << CCM_PCCR_UART2_OFFSET) | ||
| 241 | #define CCM_PCCR_UART3_MASK (1 << CCM_PCCR_UART3_OFFSET) | ||
| 242 | #define CCM_PCCR_UART4_MASK (1 << CCM_PCCR_UART4_OFFSET) | ||
| 243 | #define CCM_PCCR_USBOTG_MASK (1 << CCM_PCCR_USBOTG_OFFSET) | ||
| 244 | #define CCM_PCCR_WDT_MASK (1 << CCM_PCCR_WDT_OFFSET) | ||
| 202 | 245 | ||
| 203 | #define CCM_PCCR1_UART1_OFFSET 31 | ||
| 204 | #define CCM_PCCR1_UART1_MASK (1 << 31) | ||
| 205 | #define CCM_PCCR1_UART2_OFFSET 30 | ||
| 206 | #define CCM_PCCR1_UART2_MASK (1 << 30) | ||
| 207 | #define CCM_PCCR1_UART3_OFFSET 29 | ||
| 208 | #define CCM_PCCR1_UART3_MASK (1 << 29) | ||
| 209 | #define CCM_PCCR1_UART4_OFFSET 28 | ||
| 210 | #define CCM_PCCR1_UART4_MASK (1 << 28) | ||
| 211 | #define CCM_PCCR1_UART5_OFFSET 27 | ||
| 212 | #define CCM_PCCR1_UART5_MASK (1 << 27) | ||
| 213 | #define CCM_PCCR1_UART6_OFFSET 26 | ||
| 214 | #define CCM_PCCR1_UART6_MASK (1 << 26) | ||
| 215 | #define CCM_PCCR1_USBOTG_OFFSET 25 | ||
| 216 | #define CCM_PCCR1_USBOTG_MASK (1 << 25) | ||
| 217 | #define CCM_PCCR1_WDT_OFFSET 24 | ||
| 218 | #define CCM_PCCR1_WDT_MASK (1 << 24) | ||
| 219 | #define CCM_PCCR1_HCLK_ATA_OFFSET 23 | ||
| 220 | #define CCM_PCCR1_HCLK_ATA_MASK (1 << 23) | ||
| 221 | #define CCM_PCCR1_HCLK_BROM_OFFSET 22 | ||
| 222 | #define CCM_PCCR1_HCLK_BROM_MASK (1 << 22) | ||
| 223 | #define CCM_PCCR1_HCLK_CSI_OFFSET 21 | ||
| 224 | #define CCM_PCCR1_HCLK_CSI_MASK (1 << 21) | ||
| 225 | #define CCM_PCCR1_HCLK_DMA_OFFSET 20 | ||
| 226 | #define CCM_PCCR1_HCLK_DMA_MASK (1 << 20) | ||
| 227 | #define CCM_PCCR1_HCLK_EMI_OFFSET 19 | ||
| 228 | #define CCM_PCCR1_HCLK_EMI_MASK (1 << 19) | ||
| 229 | #define CCM_PCCR1_HCLK_EMMA_OFFSET 18 | ||
| 230 | #define CCM_PCCR1_HCLK_EMMA_MASK (1 << 18) | ||
| 231 | #define CCM_PCCR1_HCLK_FEC_OFFSET 17 | ||
| 232 | #define CCM_PCCR1_HCLK_FEC_MASK (1 << 17) | ||
| 233 | #define CCM_PCCR1_HCLK_VPU_OFFSET 16 | ||
| 234 | #define CCM_PCCR1_HCLK_VPU_MASK (1 << 16) | ||
| 235 | #define CCM_PCCR1_HCLK_LCDC_OFFSET 15 | ||
| 236 | #define CCM_PCCR1_HCLK_LCDC_MASK (1 << 15) | ||
| 237 | #define CCM_PCCR1_HCLK_RTIC_OFFSET 14 | ||
| 238 | #define CCM_PCCR1_HCLK_RTIC_MASK (1 << 14) | ||
| 239 | #define CCM_PCCR1_HCLK_SAHARA_OFFSET 13 | ||
| 240 | #define CCM_PCCR1_HCLK_SAHARA_MASK (1 << 13) | ||
| 241 | #define CCM_PCCR1_HCLK_SLCDC_OFFSET 12 | ||
| 242 | #define CCM_PCCR1_HCLK_SLCDC_MASK (1 << 12) | ||
| 243 | #define CCM_PCCR1_HCLK_USBOTG_OFFSET 11 | ||
| 244 | #define CCM_PCCR1_HCLK_USBOTG_MASK (1 << 11) | ||
| 245 | #define CCM_PCCR1_PERCLK1_OFFSET 10 | ||
| 246 | #define CCM_PCCR1_PERCLK1_MASK (1 << 10) | ||
| 247 | #define CCM_PCCR1_PERCLK2_OFFSET 9 | ||
| 248 | #define CCM_PCCR1_PERCLK2_MASK (1 << 9) | ||
| 249 | #define CCM_PCCR1_PERCLK3_OFFSET 8 | ||
| 250 | #define CCM_PCCR1_PERCLK3_MASK (1 << 8) | ||
| 251 | #define CCM_PCCR1_PERCLK4_OFFSET 7 | ||
| 252 | #define CCM_PCCR1_PERCLK4_MASK (1 << 7) | ||
| 253 | #define CCM_PCCR1_VPU_BAUD_OFFSET 6 | ||
| 254 | #define CCM_PCCR1_VPU_BAUD_MASK (1 << 6) | ||
| 255 | #define CCM_PCCR1_SSI1_BAUD_OFFSET 5 | ||
| 256 | #define CCM_PCCR1_SSI1_BAUD_MASK (1 << 5) | ||
| 257 | #define CCM_PCCR1_SSI2_BAUD_OFFSET 4 | ||
| 258 | #define CCM_PCCR1_SSI2_BAUD_MASK (1 << 4) | ||
| 259 | #define CCM_PCCR1_NFC_BAUD_OFFSET 3 | ||
| 260 | #define CCM_PCCR1_NFC_BAUD_MASK (1 << 3) | ||
| 261 | #define CCM_PCCR1_MSHC_BAUD_OFFSET 2 | ||
| 262 | #define CCM_PCCR1_MSHC_BAUD_MASK (1 << 2) | ||
| 263 | 246 | ||
| 264 | #define CCM_CCSR_32KSR (1 << 15) | 247 | #define CCM_CCSR_32KSR (1 << 15) |
| 248 | |||
| 265 | #define CCM_CCSR_CLKMODE1 (1 << 9) | 249 | #define CCM_CCSR_CLKMODE1 (1 << 9) |
| 266 | #define CCM_CCSR_CLKMODE0 (1 << 8) | 250 | #define CCM_CCSR_CLKMODE0 (1 << 8) |
| 251 | |||
| 267 | #define CCM_CCSR_CLKOSEL_OFFSET 0 | 252 | #define CCM_CCSR_CLKOSEL_OFFSET 0 |
| 268 | #define CCM_CCSR_CLKOSEL_MASK 0x1f | 253 | #define CCM_CCSR_CLKOSEL_MASK 0x1f |
| 269 | 254 | ||
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c index 2f9240be1c76..f81aa8a8fbb4 100644 --- a/arch/arm/mach-mx2/devices.c +++ b/arch/arm/mach-mx2/devices.c | |||
| @@ -34,6 +34,10 @@ | |||
| 34 | 34 | ||
| 35 | #include <mach/irqs.h> | 35 | #include <mach/irqs.h> |
| 36 | #include <mach/hardware.h> | 36 | #include <mach/hardware.h> |
| 37 | #include <mach/common.h> | ||
| 38 | #include <mach/mmc.h> | ||
| 39 | |||
| 40 | #include "devices.h" | ||
| 37 | 41 | ||
| 38 | /* | 42 | /* |
| 39 | * Resource definition for the MXC IrDA | 43 | * Resource definition for the MXC IrDA |
| @@ -225,37 +229,217 @@ struct platform_device mxc_nand_device = { | |||
| 225 | .resource = mxc_nand_resources, | 229 | .resource = mxc_nand_resources, |
| 226 | }; | 230 | }; |
| 227 | 231 | ||
| 232 | #ifdef CONFIG_FB_IMX | ||
| 233 | /* | ||
| 234 | * lcdc: | ||
| 235 | * - i.MX1: the basic controller | ||
| 236 | * - i.MX21: to be checked | ||
| 237 | * - i.MX27: like i.MX1, with slightly variations | ||
| 238 | */ | ||
| 239 | static struct resource mxc_fb[] = { | ||
| 240 | { | ||
| 241 | .start = LCDC_BASE_ADDR, | ||
| 242 | .end = LCDC_BASE_ADDR + 0xFFF, | ||
| 243 | .flags = IORESOURCE_MEM, | ||
| 244 | }, | ||
| 245 | { | ||
| 246 | .start = MXC_INT_LCDC, | ||
| 247 | .end = MXC_INT_LCDC, | ||
| 248 | .flags = IORESOURCE_IRQ, | ||
| 249 | } | ||
| 250 | }; | ||
| 251 | |||
| 252 | /* mxc lcd driver */ | ||
| 253 | struct platform_device mxc_fb_device = { | ||
| 254 | .name = "imx-fb", | ||
| 255 | .id = 0, | ||
| 256 | .num_resources = ARRAY_SIZE(mxc_fb), | ||
| 257 | .resource = mxc_fb, | ||
| 258 | .dev = { | ||
| 259 | .coherent_dma_mask = 0xFFFFFFFF, | ||
| 260 | }, | ||
| 261 | }; | ||
| 262 | #endif | ||
| 263 | |||
| 264 | #ifdef CONFIG_MACH_MX27 | ||
| 265 | static struct resource mxc_fec_resources[] = { | ||
| 266 | { | ||
| 267 | .start = FEC_BASE_ADDR, | ||
| 268 | .end = FEC_BASE_ADDR + 0xfff, | ||
| 269 | .flags = IORESOURCE_MEM | ||
| 270 | }, { | ||
| 271 | .start = MXC_INT_FEC, | ||
| 272 | .end = MXC_INT_FEC, | ||
| 273 | .flags = IORESOURCE_IRQ | ||
| 274 | }, | ||
| 275 | }; | ||
| 276 | |||
| 277 | struct platform_device mxc_fec_device = { | ||
| 278 | .name = "fec", | ||
| 279 | .id = 0, | ||
| 280 | .num_resources = ARRAY_SIZE(mxc_fec_resources), | ||
| 281 | .resource = mxc_fec_resources, | ||
| 282 | }; | ||
| 283 | #endif | ||
| 284 | |||
| 285 | static struct resource mxc_i2c_1_resources[] = { | ||
| 286 | [0] = { | ||
| 287 | .start = I2C_BASE_ADDR, | ||
| 288 | .end = I2C_BASE_ADDR + 0x0fff, | ||
| 289 | .flags = IORESOURCE_MEM | ||
| 290 | }, | ||
| 291 | [1] = { | ||
| 292 | .start = MXC_INT_I2C, | ||
| 293 | .end = MXC_INT_I2C, | ||
| 294 | .flags = IORESOURCE_IRQ | ||
| 295 | } | ||
| 296 | }; | ||
| 297 | |||
| 298 | struct platform_device mxc_i2c_device0 = { | ||
| 299 | .name = "imx-i2c", | ||
| 300 | .id = 0, | ||
| 301 | .num_resources = ARRAY_SIZE(mxc_i2c_1_resources), | ||
| 302 | .resource = mxc_i2c_1_resources | ||
| 303 | }; | ||
| 304 | |||
| 305 | #ifdef CONFIG_MACH_MX27 | ||
| 306 | static struct resource mxc_i2c_2_resources[] = { | ||
| 307 | [0] = { | ||
| 308 | .start = I2C2_BASE_ADDR, | ||
| 309 | .end = I2C2_BASE_ADDR + 0x0fff, | ||
| 310 | .flags = IORESOURCE_MEM | ||
| 311 | }, | ||
| 312 | [1] = { | ||
| 313 | .start = MXC_INT_I2C2, | ||
| 314 | .end = MXC_INT_I2C2, | ||
| 315 | .flags = IORESOURCE_IRQ | ||
| 316 | } | ||
| 317 | }; | ||
| 318 | |||
| 319 | struct platform_device mxc_i2c_device1 = { | ||
| 320 | .name = "imx-i2c", | ||
| 321 | .id = 1, | ||
| 322 | .num_resources = ARRAY_SIZE(mxc_i2c_2_resources), | ||
| 323 | .resource = mxc_i2c_2_resources | ||
| 324 | }; | ||
| 325 | #endif | ||
| 326 | |||
| 327 | static struct resource mxc_pwm_resources[] = { | ||
| 328 | [0] = { | ||
| 329 | .start = PWM_BASE_ADDR, | ||
| 330 | .end = PWM_BASE_ADDR + 0x0fff, | ||
| 331 | .flags = IORESOURCE_MEM | ||
| 332 | }, | ||
| 333 | [1] = { | ||
| 334 | .start = MXC_INT_PWM, | ||
| 335 | .end = MXC_INT_PWM, | ||
| 336 | .flags = IORESOURCE_IRQ, | ||
| 337 | } | ||
| 338 | }; | ||
| 339 | |||
| 340 | struct platform_device mxc_pwm_device = { | ||
| 341 | .name = "mxc_pwm", | ||
| 342 | .id = 0, | ||
| 343 | .num_resources = ARRAY_SIZE(mxc_pwm_resources), | ||
| 344 | .resource = mxc_pwm_resources | ||
| 345 | }; | ||
| 346 | |||
| 347 | /* | ||
| 348 | * Resource definition for the MXC SDHC | ||
| 349 | */ | ||
| 350 | static struct resource mxc_sdhc1_resources[] = { | ||
| 351 | [0] = { | ||
| 352 | .start = SDHC1_BASE_ADDR, | ||
| 353 | .end = SDHC1_BASE_ADDR + SZ_4K - 1, | ||
| 354 | .flags = IORESOURCE_MEM, | ||
| 355 | }, | ||
| 356 | [1] = { | ||
| 357 | .start = MXC_INT_SDHC1, | ||
| 358 | .end = MXC_INT_SDHC1, | ||
| 359 | .flags = IORESOURCE_IRQ, | ||
| 360 | }, | ||
| 361 | [2] = { | ||
| 362 | .start = DMA_REQ_SDHC1, | ||
| 363 | .end = DMA_REQ_SDHC1, | ||
| 364 | .flags = IORESOURCE_DMA | ||
| 365 | }, | ||
| 366 | }; | ||
| 367 | |||
| 368 | static u64 mxc_sdhc1_dmamask = 0xffffffffUL; | ||
| 369 | |||
| 370 | struct platform_device mxc_sdhc_device0 = { | ||
| 371 | .name = "mxc-mmc", | ||
| 372 | .id = 0, | ||
| 373 | .dev = { | ||
| 374 | .dma_mask = &mxc_sdhc1_dmamask, | ||
| 375 | .coherent_dma_mask = 0xffffffff, | ||
| 376 | }, | ||
| 377 | .num_resources = ARRAY_SIZE(mxc_sdhc1_resources), | ||
| 378 | .resource = mxc_sdhc1_resources, | ||
| 379 | }; | ||
| 380 | |||
| 381 | static struct resource mxc_sdhc2_resources[] = { | ||
| 382 | [0] = { | ||
| 383 | .start = SDHC2_BASE_ADDR, | ||
| 384 | .end = SDHC2_BASE_ADDR + SZ_4K - 1, | ||
| 385 | .flags = IORESOURCE_MEM, | ||
| 386 | }, | ||
| 387 | [1] = { | ||
| 388 | .start = MXC_INT_SDHC2, | ||
| 389 | .end = MXC_INT_SDHC2, | ||
| 390 | .flags = IORESOURCE_IRQ, | ||
| 391 | }, | ||
| 392 | [2] = { | ||
| 393 | .start = DMA_REQ_SDHC2, | ||
| 394 | .end = DMA_REQ_SDHC2, | ||
| 395 | .flags = IORESOURCE_DMA | ||
| 396 | }, | ||
| 397 | }; | ||
| 398 | |||
| 399 | static u64 mxc_sdhc2_dmamask = 0xffffffffUL; | ||
| 400 | |||
| 401 | struct platform_device mxc_sdhc_device1 = { | ||
| 402 | .name = "mxc-mmc", | ||
| 403 | .id = 1, | ||
| 404 | .dev = { | ||
| 405 | .dma_mask = &mxc_sdhc2_dmamask, | ||
| 406 | .coherent_dma_mask = 0xffffffff, | ||
| 407 | }, | ||
| 408 | .num_resources = ARRAY_SIZE(mxc_sdhc2_resources), | ||
| 409 | .resource = mxc_sdhc2_resources, | ||
| 410 | }; | ||
| 411 | |||
| 228 | /* GPIO port description */ | 412 | /* GPIO port description */ |
| 229 | static struct mxc_gpio_port imx_gpio_ports[] = { | 413 | static struct mxc_gpio_port imx_gpio_ports[] = { |
| 230 | [0] = { | 414 | [0] = { |
| 231 | .chip.label = "gpio-0", | 415 | .chip.label = "gpio-0", |
| 232 | .irq = MXC_INT_GPIO, | 416 | .irq = MXC_INT_GPIO, |
| 233 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 0), | 417 | .base = IO_ADDRESS(GPIO_BASE_ADDR), |
| 234 | .virtual_irq_start = MXC_GPIO_IRQ_START, | 418 | .virtual_irq_start = MXC_GPIO_IRQ_START, |
| 235 | }, | 419 | }, |
| 236 | [1] = { | 420 | [1] = { |
| 237 | .chip.label = "gpio-1", | 421 | .chip.label = "gpio-1", |
| 238 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 1), | 422 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100), |
| 239 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, | 423 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, |
| 240 | }, | 424 | }, |
| 241 | [2] = { | 425 | [2] = { |
| 242 | .chip.label = "gpio-2", | 426 | .chip.label = "gpio-2", |
| 243 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 2), | 427 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200), |
| 244 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, | 428 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, |
| 245 | }, | 429 | }, |
| 246 | [3] = { | 430 | [3] = { |
| 247 | .chip.label = "gpio-3", | 431 | .chip.label = "gpio-3", |
| 248 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 3), | 432 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300), |
| 249 | .virtual_irq_start = MXC_GPIO_IRQ_START + 96, | 433 | .virtual_irq_start = MXC_GPIO_IRQ_START + 96, |
| 250 | }, | 434 | }, |
| 251 | [4] = { | 435 | [4] = { |
| 252 | .chip.label = "gpio-4", | 436 | .chip.label = "gpio-4", |
| 253 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 4), | 437 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400), |
| 254 | .virtual_irq_start = MXC_GPIO_IRQ_START + 128, | 438 | .virtual_irq_start = MXC_GPIO_IRQ_START + 128, |
| 255 | }, | 439 | }, |
| 256 | [5] = { | 440 | [5] = { |
| 257 | .chip.label = "gpio-5", | 441 | .chip.label = "gpio-5", |
| 258 | .base = (void*)(AIPI_BASE_ADDR_VIRT + 0x15000 + 0x100 * 5), | 442 | .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500), |
| 259 | .virtual_irq_start = MXC_GPIO_IRQ_START + 160, | 443 | .virtual_irq_start = MXC_GPIO_IRQ_START + 160, |
| 260 | } | 444 | } |
| 261 | }; | 445 | }; |
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h index 1e8cb577a642..049005bb6aa9 100644 --- a/arch/arm/mach-mx2/devices.h +++ b/arch/arm/mach-mx2/devices.h | |||
| @@ -1,4 +1,3 @@ | |||
| 1 | |||
| 2 | extern struct platform_device mxc_gpt1; | 1 | extern struct platform_device mxc_gpt1; |
| 3 | extern struct platform_device mxc_gpt2; | 2 | extern struct platform_device mxc_gpt2; |
| 4 | extern struct platform_device mxc_gpt3; | 3 | extern struct platform_device mxc_gpt3; |
| @@ -14,3 +13,10 @@ extern struct platform_device mxc_uart_device4; | |||
| 14 | extern struct platform_device mxc_uart_device5; | 13 | extern struct platform_device mxc_uart_device5; |
| 15 | extern struct platform_device mxc_w1_master_device; | 14 | extern struct platform_device mxc_w1_master_device; |
| 16 | extern struct platform_device mxc_nand_device; | 15 | extern struct platform_device mxc_nand_device; |
| 16 | extern struct platform_device mxc_fb_device; | ||
| 17 | extern struct platform_device mxc_fec_device; | ||
| 18 | extern struct platform_device mxc_pwm_device; | ||
| 19 | extern struct platform_device mxc_i2c_device0; | ||
| 20 | extern struct platform_device mxc_i2c_device1; | ||
| 21 | extern struct platform_device mxc_sdhc_device0; | ||
| 22 | extern struct platform_device mxc_sdhc_device1; | ||
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/generic.c index dea6521d4d5c..bd51dd04948e 100644 --- a/arch/arm/mach-mx2/generic.c +++ b/arch/arm/mach-mx2/generic.c | |||
| @@ -21,6 +21,7 @@ | |||
| 21 | #include <linux/mm.h> | 21 | #include <linux/mm.h> |
| 22 | #include <linux/init.h> | 22 | #include <linux/init.h> |
| 23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
| 24 | #include <mach/common.h> | ||
| 24 | #include <asm/pgtable.h> | 25 | #include <asm/pgtable.h> |
| 25 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| 26 | 27 | ||
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c index 2b5c67f54571..4a3b097adc12 100644 --- a/arch/arm/mach-mx2/mx27ads.c +++ b/arch/arm/mach-mx2/mx27ads.c | |||
| @@ -31,7 +31,7 @@ | |||
| 31 | #include <asm/mach/map.h> | 31 | #include <asm/mach/map.h> |
| 32 | #include <mach/gpio.h> | 32 | #include <mach/gpio.h> |
| 33 | #include <mach/imx-uart.h> | 33 | #include <mach/imx-uart.h> |
| 34 | #include <mach/iomux-mx1-mx2.h> | 34 | #include <mach/iomux.h> |
| 35 | #include <mach/board-mx27ads.h> | 35 | #include <mach/board-mx27ads.h> |
| 36 | 36 | ||
| 37 | #include "devices.h" | 37 | #include "devices.h" |
| @@ -135,6 +135,7 @@ static int uart_mxc_port3_exit(struct platform_device *pdev) | |||
| 135 | { | 135 | { |
| 136 | mxc_gpio_release_multiple_pins(mxc_uart3_pins, | 136 | mxc_gpio_release_multiple_pins(mxc_uart3_pins, |
| 137 | ARRAY_SIZE(mxc_uart3_pins)); | 137 | ARRAY_SIZE(mxc_uart3_pins)); |
| 138 | return 0; | ||
| 138 | } | 139 | } |
| 139 | 140 | ||
| 140 | static int mxc_uart4_pins[] = { | 141 | static int mxc_uart4_pins[] = { |
| @@ -179,6 +180,7 @@ static int uart_mxc_port5_exit(struct platform_device *pdev) | |||
| 179 | 180 | ||
| 180 | static struct platform_device *platform_devices[] __initdata = { | 181 | static struct platform_device *platform_devices[] __initdata = { |
| 181 | &mx27ads_nor_mtd_device, | 182 | &mx27ads_nor_mtd_device, |
| 183 | &mxc_fec_device, | ||
| 182 | }; | 184 | }; |
| 183 | 185 | ||
| 184 | static int mxc_fec_pins[] = { | 186 | static int mxc_fec_pins[] = { |
| @@ -196,7 +198,7 @@ static int mxc_fec_pins[] = { | |||
| 196 | PD11_AOUT_FEC_TX_CLK, | 198 | PD11_AOUT_FEC_TX_CLK, |
| 197 | PD12_AOUT_FEC_RXD0, | 199 | PD12_AOUT_FEC_RXD0, |
| 198 | PD13_AOUT_FEC_RX_DV, | 200 | PD13_AOUT_FEC_RX_DV, |
| 199 | PD14_AOUT_FEC_CLR, | 201 | PD14_AOUT_FEC_RX_CLK, |
| 200 | PD15_AOUT_FEC_COL, | 202 | PD15_AOUT_FEC_COL, |
| 201 | PD16_AIN_FEC_TX_ER, | 203 | PD16_AIN_FEC_TX_ER, |
| 202 | PF23_AIN_FEC_TX_EN | 204 | PF23_AIN_FEC_TX_EN |
| @@ -208,12 +210,6 @@ static void gpio_fec_active(void) | |||
| 208 | ARRAY_SIZE(mxc_fec_pins), "FEC"); | 210 | ARRAY_SIZE(mxc_fec_pins), "FEC"); |
| 209 | } | 211 | } |
| 210 | 212 | ||
| 211 | static void gpio_fec_inactive(void) | ||
| 212 | { | ||
| 213 | mxc_gpio_release_multiple_pins(mxc_fec_pins, | ||
| 214 | ARRAY_SIZE(mxc_fec_pins)); | ||
| 215 | } | ||
| 216 | |||
| 217 | static struct imxuart_platform_data uart_pdata[] = { | 213 | static struct imxuart_platform_data uart_pdata[] = { |
| 218 | { | 214 | { |
| 219 | .init = uart_mxc_port0_init, | 215 | .init = uart_mxc_port0_init, |
| @@ -263,11 +259,10 @@ static void __init mx27ads_timer_init(void) | |||
| 263 | if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0) | 259 | if ((__raw_readw(PBC_VERSION_REG) & CKIH_27MHZ_BIT_SET) == 0) |
| 264 | fref = 27000000; | 260 | fref = 27000000; |
| 265 | 261 | ||
| 266 | mxc_clocks_init(fref); | 262 | mx27_clocks_init(fref); |
| 267 | mxc_timer_init("gpt_clk.0"); | ||
| 268 | } | 263 | } |
| 269 | 264 | ||
| 270 | struct sys_timer mx27ads_timer = { | 265 | static struct sys_timer mx27ads_timer = { |
| 271 | .init = mx27ads_timer_init, | 266 | .init = mx27ads_timer_init, |
| 272 | }; | 267 | }; |
| 273 | 268 | ||
| @@ -280,7 +275,7 @@ static struct map_desc mx27ads_io_desc[] __initdata = { | |||
| 280 | }, | 275 | }, |
| 281 | }; | 276 | }; |
| 282 | 277 | ||
| 283 | void __init mx27ads_map_io(void) | 278 | static void __init mx27ads_map_io(void) |
| 284 | { | 279 | { |
| 285 | mxc_map_io(); | 280 | mxc_map_io(); |
| 286 | iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc)); | 281 | iotable_init(mx27ads_io_desc, ARRAY_SIZE(mx27ads_io_desc)); |
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c index dfd4156da7d5..aa4eaa61d1b5 100644 --- a/arch/arm/mach-mx2/pcm038.c +++ b/arch/arm/mach-mx2/pcm038.c | |||
| @@ -20,11 +20,18 @@ | |||
| 20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
| 21 | #include <linux/mtd/physmap.h> | 21 | #include <linux/mtd/physmap.h> |
| 22 | #include <linux/mtd/plat-ram.h> | 22 | #include <linux/mtd/plat-ram.h> |
| 23 | #include <linux/io.h> | ||
| 24 | #include <linux/i2c.h> | ||
| 25 | #include <linux/i2c/at24.h> | ||
| 26 | |||
| 23 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| 24 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 25 | #include <mach/common.h> | 29 | #include <mach/common.h> |
| 26 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
| 27 | #include <mach/iomux-mx1-mx2.h> | 31 | #include <mach/iomux.h> |
| 32 | #ifdef CONFIG_I2C_IMX | ||
| 33 | #include <mach/i2c.h> | ||
| 34 | #endif | ||
| 28 | #include <asm/mach/time.h> | 35 | #include <asm/mach/time.h> |
| 29 | #include <mach/imx-uart.h> | 36 | #include <mach/imx-uart.h> |
| 30 | #include <mach/board-pcm038.h> | 37 | #include <mach/board-pcm038.h> |
| @@ -121,10 +128,10 @@ static int uart_mxc_port1_exit(struct platform_device *pdev) | |||
| 121 | return 0; | 128 | return 0; |
| 122 | } | 129 | } |
| 123 | 130 | ||
| 124 | static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS, | 131 | static int mxc_uart2_pins[] = { PE8_PF_UART3_TXD, |
| 125 | PE9_PF_UART3_RXD, | 132 | PE9_PF_UART3_RXD, |
| 126 | PE10_PF_UART3_CTS, | 133 | PE10_PF_UART3_CTS, |
| 127 | PE9_PF_UART3_RXD }; | 134 | PE11_PF_UART3_RTS }; |
| 128 | 135 | ||
| 129 | static int uart_mxc_port2_init(struct platform_device *pdev) | 136 | static int uart_mxc_port2_init(struct platform_device *pdev) |
| 130 | { | 137 | { |
| @@ -170,7 +177,7 @@ static int mxc_fec_pins[] = { | |||
| 170 | PD11_AOUT_FEC_TX_CLK, | 177 | PD11_AOUT_FEC_TX_CLK, |
| 171 | PD12_AOUT_FEC_RXD0, | 178 | PD12_AOUT_FEC_RXD0, |
| 172 | PD13_AOUT_FEC_RX_DV, | 179 | PD13_AOUT_FEC_RX_DV, |
| 173 | PD14_AOUT_FEC_CLR, | 180 | PD14_AOUT_FEC_RX_CLK, |
| 174 | PD15_AOUT_FEC_COL, | 181 | PD15_AOUT_FEC_COL, |
| 175 | PD16_AIN_FEC_TX_ER, | 182 | PD16_AIN_FEC_TX_ER, |
| 176 | PF23_AIN_FEC_TX_EN | 183 | PF23_AIN_FEC_TX_EN |
| @@ -182,12 +189,6 @@ static void gpio_fec_active(void) | |||
| 182 | ARRAY_SIZE(mxc_fec_pins), "FEC"); | 189 | ARRAY_SIZE(mxc_fec_pins), "FEC"); |
| 183 | } | 190 | } |
| 184 | 191 | ||
| 185 | static void gpio_fec_inactive(void) | ||
| 186 | { | ||
| 187 | mxc_gpio_release_multiple_pins(mxc_fec_pins, | ||
| 188 | ARRAY_SIZE(mxc_fec_pins)); | ||
| 189 | } | ||
| 190 | |||
| 191 | static struct mxc_nand_platform_data pcm038_nand_board_info = { | 192 | static struct mxc_nand_platform_data pcm038_nand_board_info = { |
| 192 | .width = 1, | 193 | .width = 1, |
| 193 | .hw_ecc = 1, | 194 | .hw_ecc = 1, |
| @@ -196,6 +197,7 @@ static struct mxc_nand_platform_data pcm038_nand_board_info = { | |||
| 196 | static struct platform_device *platform_devices[] __initdata = { | 197 | static struct platform_device *platform_devices[] __initdata = { |
| 197 | &pcm038_nor_mtd_device, | 198 | &pcm038_nor_mtd_device, |
| 198 | &mxc_w1_master_device, | 199 | &mxc_w1_master_device, |
| 200 | &mxc_fec_device, | ||
| 199 | &pcm038_sram_mtd_device, | 201 | &pcm038_sram_mtd_device, |
| 200 | }; | 202 | }; |
| 201 | 203 | ||
| @@ -208,6 +210,51 @@ static void __init pcm038_init_sram(void) | |||
| 208 | __raw_writel(0x22220a00, CSCR_A(1)); | 210 | __raw_writel(0x22220a00, CSCR_A(1)); |
| 209 | } | 211 | } |
| 210 | 212 | ||
| 213 | #ifdef CONFIG_I2C_IMX | ||
| 214 | static int mxc_i2c1_pins[] = { | ||
| 215 | PC5_PF_I2C2_SDA, | ||
| 216 | PC6_PF_I2C2_SCL | ||
| 217 | }; | ||
| 218 | |||
| 219 | static int pcm038_i2c_1_init(struct device *dev) | ||
| 220 | { | ||
| 221 | return mxc_gpio_setup_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins), | ||
| 222 | "I2C1"); | ||
| 223 | } | ||
| 224 | |||
| 225 | static void pcm038_i2c_1_exit(struct device *dev) | ||
| 226 | { | ||
| 227 | mxc_gpio_release_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins)); | ||
| 228 | } | ||
| 229 | |||
| 230 | static struct imxi2c_platform_data pcm038_i2c_1_data = { | ||
| 231 | .bitrate = 100000, | ||
| 232 | .init = pcm038_i2c_1_init, | ||
| 233 | .exit = pcm038_i2c_1_exit, | ||
| 234 | }; | ||
| 235 | |||
| 236 | static struct at24_platform_data board_eeprom = { | ||
| 237 | .byte_len = 4096, | ||
| 238 | .page_size = 32, | ||
| 239 | .flags = AT24_FLAG_ADDR16, | ||
| 240 | }; | ||
| 241 | |||
| 242 | static struct i2c_board_info pcm038_i2c_devices[] = { | ||
| 243 | [0] = { | ||
| 244 | I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ | ||
| 245 | .platform_data = &board_eeprom, | ||
| 246 | }, | ||
| 247 | [1] = { | ||
| 248 | I2C_BOARD_INFO("rtc-pcf8563", 0x51), | ||
| 249 | .type = "pcf8563" | ||
| 250 | }, | ||
| 251 | [2] = { | ||
| 252 | I2C_BOARD_INFO("lm75", 0x4a), | ||
| 253 | .type = "lm75" | ||
| 254 | } | ||
| 255 | }; | ||
| 256 | #endif | ||
| 257 | |||
| 211 | static void __init pcm038_init(void) | 258 | static void __init pcm038_init(void) |
| 212 | { | 259 | { |
| 213 | gpio_fec_active(); | 260 | gpio_fec_active(); |
| @@ -217,9 +264,17 @@ static void __init pcm038_init(void) | |||
| 217 | mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); | 264 | mxc_register_device(&mxc_uart_device1, &uart_pdata[1]); |
| 218 | mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); | 265 | mxc_register_device(&mxc_uart_device2, &uart_pdata[2]); |
| 219 | 266 | ||
| 220 | mxc_gpio_mode(PE16_AF_RTCK); /* OWIRE */ | 267 | mxc_gpio_mode(PE16_AF_OWIRE); |
| 221 | mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info); | 268 | mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info); |
| 222 | 269 | ||
| 270 | #ifdef CONFIG_I2C_IMX | ||
| 271 | /* only the i2c master 1 is used on this CPU card */ | ||
| 272 | i2c_register_board_info(1, pcm038_i2c_devices, | ||
| 273 | ARRAY_SIZE(pcm038_i2c_devices)); | ||
| 274 | |||
| 275 | mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data); | ||
| 276 | #endif | ||
| 277 | |||
| 223 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); | 278 | platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); |
| 224 | 279 | ||
| 225 | #ifdef CONFIG_MACH_PCM970_BASEBOARD | 280 | #ifdef CONFIG_MACH_PCM970_BASEBOARD |
| @@ -229,11 +284,10 @@ static void __init pcm038_init(void) | |||
| 229 | 284 | ||
| 230 | static void __init pcm038_timer_init(void) | 285 | static void __init pcm038_timer_init(void) |
| 231 | { | 286 | { |
| 232 | mxc_clocks_init(26000000); | 287 | mx27_clocks_init(26000000); |
| 233 | mxc_timer_init("gpt_clk.0"); | ||
| 234 | } | 288 | } |
| 235 | 289 | ||
| 236 | struct sys_timer pcm038_timer = { | 290 | static struct sys_timer pcm038_timer = { |
| 237 | .init = pcm038_timer_init, | 291 | .init = pcm038_timer_init, |
| 238 | }; | 292 | }; |
| 239 | 293 | ||
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c index a560cd6ad23d..bf4e520bc1bc 100644 --- a/arch/arm/mach-mx2/pcm970-baseboard.c +++ b/arch/arm/mach-mx2/pcm970-baseboard.c | |||
| @@ -17,9 +17,138 @@ | |||
| 17 | */ | 17 | */ |
| 18 | 18 | ||
| 19 | #include <linux/platform_device.h> | 19 | #include <linux/platform_device.h> |
| 20 | #include <mach/hardware.h> | 20 | #include <linux/gpio.h> |
| 21 | #include <linux/irq.h> | ||
| 22 | |||
| 21 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 22 | 24 | ||
| 25 | #include <mach/hardware.h> | ||
| 26 | #include <mach/common.h> | ||
| 27 | #include <mach/mmc.h> | ||
| 28 | #include <mach/imxfb.h> | ||
| 29 | #include <mach/iomux.h> | ||
| 30 | |||
| 31 | #include "devices.h" | ||
| 32 | |||
| 33 | static int pcm970_sdhc2_get_ro(struct device *dev) | ||
| 34 | { | ||
| 35 | return gpio_get_value(GPIO_PORTC + 28); | ||
| 36 | } | ||
| 37 | |||
| 38 | static int pcm970_sdhc2_pins[] = { | ||
| 39 | PB4_PF_SD2_D0, | ||
| 40 | PB5_PF_SD2_D1, | ||
| 41 | PB6_PF_SD2_D2, | ||
| 42 | PB7_PF_SD2_D3, | ||
| 43 | PB8_PF_SD2_CMD, | ||
| 44 | PB9_PF_SD2_CLK, | ||
| 45 | }; | ||
| 46 | |||
| 47 | static int pcm970_sdhc2_init(struct device *dev, irq_handler_t detect_irq, void *data) | ||
| 48 | { | ||
| 49 | int ret; | ||
| 50 | |||
| 51 | ret = mxc_gpio_setup_multiple_pins(pcm970_sdhc2_pins, | ||
| 52 | ARRAY_SIZE(pcm970_sdhc2_pins), "sdhc2"); | ||
| 53 | if(ret) | ||
| 54 | return ret; | ||
| 55 | |||
| 56 | ret = request_irq(IRQ_GPIOC(29), detect_irq, 0, | ||
| 57 | "imx-mmc-detect", data); | ||
| 58 | if (ret) | ||
| 59 | goto out_release_gpio; | ||
| 60 | |||
| 61 | set_irq_type(IRQ_GPIOC(29), IRQF_TRIGGER_FALLING); | ||
| 62 | |||
| 63 | ret = gpio_request(GPIO_PORTC + 28, "imx-mmc-ro"); | ||
| 64 | if (ret) | ||
| 65 | goto out_release_gpio; | ||
| 66 | |||
| 67 | mxc_gpio_mode((GPIO_PORTC | 28) | GPIO_GPIO | GPIO_IN); | ||
| 68 | gpio_direction_input(GPIO_PORTC + 28); | ||
| 69 | |||
| 70 | return 0; | ||
| 71 | |||
| 72 | out_release_gpio: | ||
| 73 | mxc_gpio_release_multiple_pins(pcm970_sdhc2_pins, | ||
| 74 | ARRAY_SIZE(pcm970_sdhc2_pins)); | ||
| 75 | return ret; | ||
| 76 | } | ||
| 77 | |||
| 78 | static void pcm970_sdhc2_exit(struct device *dev, void *data) | ||
| 79 | { | ||
| 80 | free_irq(IRQ_GPIOC(29), data); | ||
| 81 | gpio_free(GPIO_PORTC + 28); | ||
| 82 | mxc_gpio_release_multiple_pins(pcm970_sdhc2_pins, | ||
| 83 | ARRAY_SIZE(pcm970_sdhc2_pins)); | ||
| 84 | } | ||
| 85 | |||
| 86 | static struct imxmmc_platform_data sdhc_pdata = { | ||
| 87 | .get_ro = pcm970_sdhc2_get_ro, | ||
| 88 | .init = pcm970_sdhc2_init, | ||
| 89 | .exit = pcm970_sdhc2_exit, | ||
| 90 | }; | ||
| 91 | |||
| 92 | static int mxc_fb_pins[] = { | ||
| 93 | PA5_PF_LSCLK, PA6_PF_LD0, PA7_PF_LD1, PA8_PF_LD2, | ||
| 94 | PA9_PF_LD3, PA10_PF_LD4, PA11_PF_LD5, PA12_PF_LD6, | ||
| 95 | PA13_PF_LD7, PA14_PF_LD8, PA15_PF_LD9, PA16_PF_LD10, | ||
| 96 | PA17_PF_LD11, PA18_PF_LD12, PA19_PF_LD13, PA20_PF_LD14, | ||
| 97 | PA21_PF_LD15, PA22_PF_LD16, PA23_PF_LD17, PA24_PF_REV, | ||
| 98 | PA25_PF_CLS, PA26_PF_PS, PA27_PF_SPL_SPR, PA28_PF_HSYNC, | ||
| 99 | PA29_PF_VSYNC, PA30_PF_CONTRAST, PA31_PF_OE_ACD | ||
| 100 | }; | ||
| 101 | |||
| 102 | static int pcm038_fb_init(struct platform_device *pdev) | ||
| 103 | { | ||
| 104 | return mxc_gpio_setup_multiple_pins(mxc_fb_pins, | ||
| 105 | ARRAY_SIZE(mxc_fb_pins), "FB"); | ||
| 106 | } | ||
| 107 | |||
| 108 | static int pcm038_fb_exit(struct platform_device *pdev) | ||
| 109 | { | ||
| 110 | mxc_gpio_release_multiple_pins(mxc_fb_pins, ARRAY_SIZE(mxc_fb_pins)); | ||
| 111 | |||
| 112 | return 0; | ||
| 113 | } | ||
| 114 | |||
| 115 | /* | ||
| 116 | * Connected is a portrait Sharp-QVGA display | ||
| 117 | * of type: LQ035Q7DH06 | ||
| 118 | */ | ||
| 119 | static struct imx_fb_platform_data pcm038_fb_data = { | ||
| 120 | .pixclock = 188679, /* in ps (5.3MHz) */ | ||
| 121 | .xres = 240, | ||
| 122 | .yres = 320, | ||
| 123 | |||
| 124 | .bpp = 16, | ||
| 125 | .hsync_len = 7, | ||
| 126 | .left_margin = 5, | ||
| 127 | .right_margin = 16, | ||
| 128 | |||
| 129 | .vsync_len = 1, | ||
| 130 | .upper_margin = 7, | ||
| 131 | .lower_margin = 9, | ||
| 132 | .fixed_screen_cpu = 0, | ||
| 133 | |||
| 134 | /* | ||
| 135 | * - HSYNC active high | ||
| 136 | * - VSYNC active high | ||
| 137 | * - clk notenabled while idle | ||
| 138 | * - clock not inverted | ||
| 139 | * - data not inverted | ||
| 140 | * - data enable low active | ||
| 141 | * - enable sharp mode | ||
| 142 | */ | ||
| 143 | .pcr = 0xFA0080C0, | ||
| 144 | .pwmr = 0x00A903FF, | ||
| 145 | .lscr1 = 0x00120300, | ||
| 146 | .dmacr = 0x00020010, | ||
| 147 | |||
| 148 | .init = pcm038_fb_init, | ||
| 149 | .exit = pcm038_fb_exit, | ||
| 150 | }; | ||
| 151 | |||
| 23 | /* | 152 | /* |
| 24 | * system init for baseboard usage. Will be called by pcm038 init. | 153 | * system init for baseboard usage. Will be called by pcm038 init. |
| 25 | * | 154 | * |
| @@ -28,4 +157,6 @@ | |||
| 28 | */ | 157 | */ |
| 29 | void __init pcm970_baseboard_init(void) | 158 | void __init pcm970_baseboard_init(void) |
| 30 | { | 159 | { |
| 160 | mxc_register_device(&mxc_fb_device, &pcm038_fb_data); | ||
| 161 | mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); | ||
| 31 | } | 162 | } |
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-mx2/serial.c index 16debc296dad..40a485cdc10e 100644 --- a/arch/arm/mach-mx2/serial.c +++ b/arch/arm/mach-mx2/serial.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/serial.h> | 22 | #include <linux/serial.h> |
| 23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
| 24 | #include <mach/imx-uart.h> | 24 | #include <mach/imx-uart.h> |
| 25 | #include "devices.h" | ||
| 25 | 26 | ||
| 26 | static struct resource uart0[] = { | 27 | static struct resource uart0[] = { |
| 27 | { | 28 | { |
| @@ -99,6 +100,7 @@ struct platform_device mxc_uart_device3 = { | |||
| 99 | .num_resources = ARRAY_SIZE(uart3), | 100 | .num_resources = ARRAY_SIZE(uart3), |
| 100 | }; | 101 | }; |
| 101 | 102 | ||
| 103 | #ifdef CONFIG_MACH_MX27 | ||
| 102 | static struct resource uart4[] = { | 104 | static struct resource uart4[] = { |
| 103 | { | 105 | { |
| 104 | .start = UART5_BASE_ADDR, | 106 | .start = UART5_BASE_ADDR, |
| @@ -136,3 +138,4 @@ struct platform_device mxc_uart_device5 = { | |||
| 136 | .resource = uart5, | 138 | .resource = uart5, |
| 137 | .num_resources = ARRAY_SIZE(uart5), | 139 | .num_resources = ARRAY_SIZE(uart5), |
| 138 | }; | 140 | }; |
| 141 | #endif | ||
diff --git a/arch/arm/mach-mx2/system.c b/arch/arm/mach-mx2/system.c index 7b8269719d11..92c79d4bd162 100644 --- a/arch/arm/mach-mx2/system.c +++ b/arch/arm/mach-mx2/system.c | |||
| @@ -46,7 +46,7 @@ void arch_idle(void) | |||
| 46 | /* | 46 | /* |
| 47 | * Reset the system. It is called by machine_restart(). | 47 | * Reset the system. It is called by machine_restart(). |
| 48 | */ | 48 | */ |
| 49 | void arch_reset(char mode) | 49 | void arch_reset(char mode, const char *cmd) |
| 50 | { | 50 | { |
| 51 | struct clk *clk; | 51 | struct clk *clk; |
| 52 | 52 | ||
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig index e79659e8176e..d6235583e979 100644 --- a/arch/arm/mach-mx3/Kconfig +++ b/arch/arm/mach-mx3/Kconfig | |||
| @@ -1,21 +1,40 @@ | |||
| 1 | menu "MX3 Options" | 1 | if ARCH_MX3 |
| 2 | depends on ARCH_MX3 | 2 | |
| 3 | config ARCH_MX31 | ||
| 4 | bool | ||
| 5 | |||
| 6 | config ARCH_MX35 | ||
| 7 | bool | ||
| 8 | |||
| 9 | comment "MX3 platforms:" | ||
| 3 | 10 | ||
| 4 | config MACH_MX31ADS | 11 | config MACH_MX31ADS |
| 5 | bool "Support MX31ADS platforms" | 12 | bool "Support MX31ADS platforms" |
| 13 | select ARCH_MX31 | ||
| 6 | default y | 14 | default y |
| 7 | help | 15 | help |
| 8 | Include support for MX31ADS platform. This includes specific | 16 | Include support for MX31ADS platform. This includes specific |
| 9 | configurations for the board and its peripherals. | 17 | configurations for the board and its peripherals. |
| 10 | 18 | ||
| 19 | config MACH_MX31ADS_WM1133_EV1 | ||
| 20 | bool "Support Wolfson Microelectronics 1133-EV1 module" | ||
| 21 | depends on MACH_MX31ADS | ||
| 22 | select MFD_WM8350_CONFIG_MODE_0 | ||
| 23 | select MFD_WM8352_CONFIG_MODE_0 | ||
| 24 | help | ||
| 25 | Include support for the Wolfson Microelectronics 1133-EV1 PMU | ||
| 26 | and audio module for the MX31ADS platform. | ||
| 27 | |||
| 11 | config MACH_PCM037 | 28 | config MACH_PCM037 |
| 12 | bool "Support Phytec pcm037 platforms" | 29 | bool "Support Phytec pcm037 (i.MX31) platforms" |
| 30 | select ARCH_MX31 | ||
| 13 | help | 31 | help |
| 14 | Include support for Phytec pcm037 platform. This includes | 32 | Include support for Phytec pcm037 platform. This includes |
| 15 | specific configurations for the board and its peripherals. | 33 | specific configurations for the board and its peripherals. |
| 16 | 34 | ||
| 17 | config MACH_MX31LITE | 35 | config MACH_MX31LITE |
| 18 | bool "Support MX31 LITEKIT (LogicPD)" | 36 | bool "Support MX31 LITEKIT (LogicPD)" |
| 37 | select ARCH_MX31 | ||
| 19 | default n | 38 | default n |
| 20 | help | 39 | help |
| 21 | Include support for MX31 LITEKIT platform. This includes specific | 40 | Include support for MX31 LITEKIT platform. This includes specific |
| @@ -23,6 +42,7 @@ config MACH_MX31LITE | |||
| 23 | 42 | ||
| 24 | config MACH_MX31_3DS | 43 | config MACH_MX31_3DS |
| 25 | bool "Support MX31PDK (3DS)" | 44 | bool "Support MX31PDK (3DS)" |
| 45 | select ARCH_MX31 | ||
| 26 | default n | 46 | default n |
| 27 | help | 47 | help |
| 28 | Include support for MX31PDK (3DS) platform. This includes specific | 48 | Include support for MX31PDK (3DS) platform. This includes specific |
| @@ -30,10 +50,18 @@ config MACH_MX31_3DS | |||
| 30 | 50 | ||
| 31 | config MACH_MX31MOBOARD | 51 | config MACH_MX31MOBOARD |
| 32 | bool "Support mx31moboard platforms (EPFL Mobots group)" | 52 | bool "Support mx31moboard platforms (EPFL Mobots group)" |
| 53 | select ARCH_MX31 | ||
| 33 | default n | 54 | default n |
| 34 | help | 55 | help |
| 35 | Include support for mx31moboard platform. This includes specific | 56 | Include support for mx31moboard platform. This includes specific |
| 36 | configurations for the board and its peripherals. | 57 | configurations for the board and its peripherals. |
| 37 | 58 | ||
| 38 | endmenu | 59 | config MACH_QONG |
| 60 | bool "Support Dave/DENX QongEVB-LITE platform" | ||
| 61 | select ARCH_MX31 | ||
| 62 | default n | ||
| 63 | help | ||
| 64 | Include support for Dave/DENX QongEVB-LITE platform. This includes | ||
| 65 | specific configurations for the board and its peripherals. | ||
| 39 | 66 | ||
| 67 | endif | ||
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile index 5a151540fe83..272c8a953b30 100644 --- a/arch/arm/mach-mx3/Makefile +++ b/arch/arm/mach-mx3/Makefile | |||
| @@ -4,9 +4,13 @@ | |||
| 4 | 4 | ||
| 5 | # Object file lists. | 5 | # Object file lists. |
| 6 | 6 | ||
| 7 | obj-y := mm.o clock.o devices.o iomux.o | 7 | obj-y := mm.o devices.o |
| 8 | obj-$(CONFIG_ARCH_MX31) += clock.o iomux.o | ||
| 9 | obj-$(CONFIG_ARCH_MX35) += clock-imx35.o | ||
| 8 | obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o | 10 | obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o |
| 9 | obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o | 11 | obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o |
| 10 | obj-$(CONFIG_MACH_PCM037) += pcm037.o | 12 | obj-$(CONFIG_MACH_PCM037) += pcm037.o |
| 11 | obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o | 13 | obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o |
| 12 | obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o | 14 | obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o mx31moboard-devboard.o \ |
| 15 | mx31moboard-marxbot.o | ||
| 16 | obj-$(CONFIG_MACH_QONG) += qong.o | ||
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c new file mode 100644 index 000000000000..53a112d4e04a --- /dev/null +++ b/arch/arm/mach-mx3/clock-imx35.c | |||
| @@ -0,0 +1,487 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 by Sascha Hauer, Pengutronix | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/kernel.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | #include <linux/list.h> | ||
| 22 | #include <linux/clk.h> | ||
| 23 | #include <linux/io.h> | ||
| 24 | |||
| 25 | #include <asm/clkdev.h> | ||
| 26 | |||
| 27 | #include <mach/clock.h> | ||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <mach/common.h> | ||
| 30 | |||
| 31 | #define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR) | ||
| 32 | |||
| 33 | #define CCM_CCMR 0x00 | ||
| 34 | #define CCM_PDR0 0x04 | ||
| 35 | #define CCM_PDR1 0x08 | ||
| 36 | #define CCM_PDR2 0x0C | ||
| 37 | #define CCM_PDR3 0x10 | ||
| 38 | #define CCM_PDR4 0x14 | ||
| 39 | #define CCM_RCSR 0x18 | ||
| 40 | #define CCM_MPCTL 0x1C | ||
| 41 | #define CCM_PPCTL 0x20 | ||
| 42 | #define CCM_ACMR 0x24 | ||
| 43 | #define CCM_COSR 0x28 | ||
| 44 | #define CCM_CGR0 0x2C | ||
| 45 | #define CCM_CGR1 0x30 | ||
| 46 | #define CCM_CGR2 0x34 | ||
| 47 | #define CCM_CGR3 0x38 | ||
| 48 | |||
| 49 | #ifdef HAVE_SET_RATE_SUPPORT | ||
| 50 | static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost) | ||
| 51 | { | ||
| 52 | u32 min_pre, temp_pre, old_err, err; | ||
| 53 | |||
| 54 | min_pre = (div - 1) / maxpost + 1; | ||
| 55 | old_err = 8; | ||
| 56 | |||
| 57 | for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) { | ||
| 58 | if (div > (temp_pre * maxpost)) | ||
| 59 | break; | ||
| 60 | |||
| 61 | if (div < (temp_pre * temp_pre)) | ||
| 62 | continue; | ||
| 63 | |||
| 64 | err = div % temp_pre; | ||
| 65 | |||
| 66 | if (err == 0) { | ||
| 67 | *pre = temp_pre; | ||
| 68 | break; | ||
| 69 | } | ||
| 70 | |||
| 71 | err = temp_pre - err; | ||
| 72 | |||
| 73 | if (err < old_err) { | ||
| 74 | old_err = err; | ||
| 75 | *pre = temp_pre; | ||
| 76 | } | ||
| 77 | } | ||
| 78 | |||
| 79 | *post = (div + *pre - 1) / *pre; | ||
| 80 | } | ||
| 81 | |||
| 82 | /* get the best values for a 3-bit divider combined with a 6-bit divider */ | ||
| 83 | static void calc_dividers_3_6(u32 div, u32 *pre, u32 *post) | ||
| 84 | { | ||
| 85 | if (div >= 512) { | ||
| 86 | *pre = 8; | ||
| 87 | *post = 64; | ||
| 88 | } else if (div >= 64) { | ||
| 89 | calc_dividers(div, pre, post, 64); | ||
| 90 | } else if (div <= 8) { | ||
| 91 | *pre = div; | ||
| 92 | *post = 1; | ||
| 93 | } else { | ||
| 94 | *pre = 1; | ||
| 95 | *post = div; | ||
| 96 | } | ||
| 97 | } | ||
| 98 | |||
| 99 | /* get the best values for two cascaded 3-bit dividers */ | ||
| 100 | static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post) | ||
| 101 | { | ||
| 102 | if (div >= 64) { | ||
| 103 | *pre = *post = 8; | ||
| 104 | } else if (div > 8) { | ||
| 105 | calc_dividers(div, pre, post, 8); | ||
| 106 | } else { | ||
| 107 | *pre = 1; | ||
| 108 | *post = div; | ||
| 109 | } | ||
| 110 | } | ||
| 111 | #endif | ||
| 112 | |||
| 113 | static unsigned long get_rate_mpll(void) | ||
| 114 | { | ||
| 115 | ulong mpctl = __raw_readl(CCM_BASE + CCM_MPCTL); | ||
| 116 | |||
| 117 | return mxc_decode_pll(mpctl, 24000000); | ||
| 118 | } | ||
| 119 | |||
| 120 | static unsigned long get_rate_ppll(void) | ||
| 121 | { | ||
| 122 | ulong ppctl = __raw_readl(CCM_BASE + CCM_PPCTL); | ||
| 123 | |||
| 124 | return mxc_decode_pll(ppctl, 24000000); | ||
| 125 | } | ||
| 126 | |||
| 127 | struct arm_ahb_div { | ||
| 128 | unsigned char arm, ahb, sel; | ||
| 129 | }; | ||
| 130 | |||
| 131 | static struct arm_ahb_div clk_consumer[] = { | ||
| 132 | { .arm = 1, .ahb = 4, .sel = 0}, | ||
| 133 | { .arm = 1, .ahb = 3, .sel = 1}, | ||
| 134 | { .arm = 2, .ahb = 2, .sel = 0}, | ||
| 135 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 136 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 137 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 138 | { .arm = 4, .ahb = 1, .sel = 0}, | ||
| 139 | { .arm = 1, .ahb = 5, .sel = 0}, | ||
| 140 | { .arm = 1, .ahb = 8, .sel = 0}, | ||
| 141 | { .arm = 1, .ahb = 6, .sel = 1}, | ||
| 142 | { .arm = 2, .ahb = 4, .sel = 0}, | ||
| 143 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 144 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 145 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 146 | { .arm = 4, .ahb = 2, .sel = 0}, | ||
| 147 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 148 | }; | ||
| 149 | |||
| 150 | static struct arm_ahb_div clk_automotive[] = { | ||
| 151 | { .arm = 1, .ahb = 3, .sel = 0}, | ||
| 152 | { .arm = 1, .ahb = 2, .sel = 1}, | ||
| 153 | { .arm = 2, .ahb = 1, .sel = 1}, | ||
| 154 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 155 | { .arm = 1, .ahb = 6, .sel = 0}, | ||
| 156 | { .arm = 1, .ahb = 4, .sel = 1}, | ||
| 157 | { .arm = 2, .ahb = 2, .sel = 1}, | ||
| 158 | { .arm = 0, .ahb = 0, .sel = 0}, | ||
| 159 | }; | ||
| 160 | |||
| 161 | static unsigned long get_rate_arm(void) | ||
| 162 | { | ||
| 163 | unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0); | ||
| 164 | struct arm_ahb_div *aad; | ||
| 165 | unsigned long fref = get_rate_mpll(); | ||
| 166 | |||
| 167 | if (pdr0 & 1) { | ||
| 168 | /* consumer path */ | ||
| 169 | aad = &clk_consumer[(pdr0 >> 16) & 0xf]; | ||
| 170 | if (aad->sel) | ||
| 171 | fref = fref * 2 / 3; | ||
| 172 | } else { | ||
| 173 | /* auto path */ | ||
| 174 | aad = &clk_automotive[(pdr0 >> 9) & 0x7]; | ||
| 175 | if (aad->sel) | ||
| 176 | fref = fref * 3 / 4; | ||
| 177 | } | ||
| 178 | return fref / aad->arm; | ||
| 179 | } | ||
| 180 | |||
| 181 | static unsigned long get_rate_ahb(struct clk *clk) | ||
| 182 | { | ||
| 183 | unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0); | ||
| 184 | struct arm_ahb_div *aad; | ||
| 185 | unsigned long fref = get_rate_mpll(); | ||
| 186 | |||
| 187 | if (pdr0 & 1) | ||
| 188 | /* consumer path */ | ||
| 189 | aad = &clk_consumer[(pdr0 >> 16) & 0xf]; | ||
| 190 | else | ||
| 191 | /* auto path */ | ||
| 192 | aad = &clk_automotive[(pdr0 >> 9) & 0x7]; | ||
| 193 | |||
| 194 | return fref / aad->ahb; | ||
| 195 | } | ||
| 196 | |||
| 197 | static unsigned long get_rate_ipg(struct clk *clk) | ||
| 198 | { | ||
| 199 | return get_rate_ahb(NULL) >> 1; | ||
| 200 | } | ||
| 201 | |||
| 202 | static unsigned long get_3_3_div(unsigned long in) | ||
| 203 | { | ||
| 204 | return (((in >> 3) & 0x7) + 1) * ((in & 0x7) + 1); | ||
| 205 | } | ||
| 206 | |||
| 207 | static unsigned long get_rate_uart(struct clk *clk) | ||
| 208 | { | ||
| 209 | unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3); | ||
| 210 | unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4); | ||
| 211 | unsigned long div = get_3_3_div(pdr4 >> 10); | ||
| 212 | |||
| 213 | if (pdr3 & (1 << 14)) | ||
| 214 | return get_rate_arm() / div; | ||
| 215 | else | ||
| 216 | return get_rate_ppll() / div; | ||
| 217 | } | ||
| 218 | |||
| 219 | static unsigned long get_rate_sdhc(struct clk *clk) | ||
| 220 | { | ||
| 221 | unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3); | ||
| 222 | unsigned long div, rate; | ||
| 223 | |||
| 224 | if (pdr3 & (1 << 6)) | ||
| 225 | rate = get_rate_arm(); | ||
| 226 | else | ||
| 227 | rate = get_rate_ppll(); | ||
| 228 | |||
| 229 | switch (clk->id) { | ||
| 230 | default: | ||
| 231 | case 0: | ||
| 232 | div = pdr3 & 0x3f; | ||
| 233 | break; | ||
| 234 | case 1: | ||
| 235 | div = (pdr3 >> 8) & 0x3f; | ||
| 236 | break; | ||
| 237 | case 2: | ||
| 238 | div = (pdr3 >> 16) & 0x3f; | ||
| 239 | break; | ||
| 240 | } | ||
| 241 | |||
| 242 | return rate / get_3_3_div(div); | ||
| 243 | } | ||
| 244 | |||
| 245 | static unsigned long get_rate_mshc(struct clk *clk) | ||
| 246 | { | ||
| 247 | unsigned long pdr1 = __raw_readl(CCM_BASE + CCM_PDR1); | ||
| 248 | unsigned long div1, div2, rate; | ||
| 249 | |||
| 250 | if (pdr1 & (1 << 7)) | ||
| 251 | rate = get_rate_arm(); | ||
| 252 | else | ||
| 253 | rate = get_rate_ppll(); | ||
| 254 | |||
| 255 | div1 = (pdr1 >> 29) & 0x7; | ||
| 256 | div2 = (pdr1 >> 22) & 0x3f; | ||
| 257 | |||
| 258 | return rate / ((div1 + 1) * (div2 + 1)); | ||
| 259 | } | ||
| 260 | |||
| 261 | static unsigned long get_rate_ssi(struct clk *clk) | ||
| 262 | { | ||
| 263 | unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2); | ||
| 264 | unsigned long div1, div2, rate; | ||
| 265 | |||
| 266 | if (pdr2 & (1 << 6)) | ||
| 267 | rate = get_rate_arm(); | ||
| 268 | else | ||
| 269 | rate = get_rate_ppll(); | ||
| 270 | |||
| 271 | switch (clk->id) { | ||
| 272 | default: | ||
| 273 | case 0: | ||
| 274 | div1 = pdr2 & 0x3f; | ||
| 275 | div2 = (pdr2 >> 24) & 0x7; | ||
| 276 | break; | ||
| 277 | case 1: | ||
| 278 | div1 = (pdr2 >> 8) & 0x3f; | ||
| 279 | div2 = (pdr2 >> 27) & 0x7; | ||
| 280 | break; | ||
| 281 | } | ||
| 282 | |||
| 283 | return rate / ((div1 + 1) * (div2 + 1)); | ||
| 284 | } | ||
| 285 | |||
| 286 | static unsigned long get_rate_csi(struct clk *clk) | ||
| 287 | { | ||
| 288 | unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2); | ||
| 289 | unsigned long rate; | ||
| 290 | |||
| 291 | if (pdr2 & (1 << 7)) | ||
| 292 | rate = get_rate_arm(); | ||
| 293 | else | ||
| 294 | rate = get_rate_ppll(); | ||
| 295 | |||
| 296 | return rate / get_3_3_div((pdr2 >> 16) & 0x3f); | ||
| 297 | } | ||
| 298 | |||
| 299 | static unsigned long get_rate_ipg_per(struct clk *clk) | ||
| 300 | { | ||
| 301 | unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0); | ||
| 302 | unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4); | ||
| 303 | unsigned long div1, div2; | ||
| 304 | |||
| 305 | if (pdr0 & (1 << 26)) { | ||
| 306 | div1 = (pdr4 >> 19) & 0x7; | ||
| 307 | div2 = (pdr4 >> 16) & 0x7; | ||
| 308 | return get_rate_arm() / ((div1 + 1) * (div2 + 1)); | ||
| 309 | } else { | ||
| 310 | div1 = (pdr0 >> 12) & 0x7; | ||
| 311 | return get_rate_ahb(NULL) / div1; | ||
| 312 | } | ||
| 313 | } | ||
| 314 | |||
| 315 | static int clk_cgr_enable(struct clk *clk) | ||
| 316 | { | ||
| 317 | u32 reg; | ||
| 318 | |||
| 319 | reg = __raw_readl(clk->enable_reg); | ||
| 320 | reg |= 3 << clk->enable_shift; | ||
| 321 | __raw_writel(reg, clk->enable_reg); | ||
| 322 | |||
| 323 | return 0; | ||
| 324 | } | ||
| 325 | |||
| 326 | static void clk_cgr_disable(struct clk *clk) | ||
| 327 | { | ||
| 328 | u32 reg; | ||
| 329 | |||
| 330 | reg = __raw_readl(clk->enable_reg); | ||
| 331 | reg &= ~(3 << clk->enable_shift); | ||
| 332 | __raw_writel(reg, clk->enable_reg); | ||
| 333 | } | ||
| 334 | |||
| 335 | #define DEFINE_CLOCK(name, i, er, es, gr, sr) \ | ||
| 336 | static struct clk name = { \ | ||
| 337 | .id = i, \ | ||
| 338 | .enable_reg = CCM_BASE + er, \ | ||
| 339 | .enable_shift = es, \ | ||
| 340 | .get_rate = gr, \ | ||
| 341 | .set_rate = sr, \ | ||
| 342 | .enable = clk_cgr_enable, \ | ||
| 343 | .disable = clk_cgr_disable, \ | ||
| 344 | } | ||
| 345 | |||
| 346 | DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL); | ||
| 347 | DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL); | ||
| 348 | DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); | ||
| 349 | DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL); | ||
| 350 | DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL); | ||
| 351 | DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL); | ||
| 352 | DEFINE_CLOCK(cspi2_clk, 1, CCM_CGR0, 12, get_rate_ipg, NULL); | ||
| 353 | DEFINE_CLOCK(ect_clk, 0, CCM_CGR0, 14, get_rate_ipg, NULL); | ||
| 354 | DEFINE_CLOCK(edio_clk, 0, CCM_CGR0, 16, NULL, NULL); | ||
| 355 | DEFINE_CLOCK(emi_clk, 0, CCM_CGR0, 18, get_rate_ipg, NULL); | ||
| 356 | DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg_per, NULL); | ||
| 357 | DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg_per, NULL); | ||
| 358 | DEFINE_CLOCK(esai_clk, 0, CCM_CGR0, 24, NULL, NULL); | ||
| 359 | DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL); | ||
| 360 | DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL); | ||
| 361 | DEFINE_CLOCK(esdhc3_clk, 2, CCM_CGR0, 30, get_rate_sdhc, NULL); | ||
| 362 | |||
| 363 | DEFINE_CLOCK(fec_clk, 0, CCM_CGR1, 0, get_rate_ipg, NULL); | ||
| 364 | DEFINE_CLOCK(gpio1_clk, 0, CCM_CGR1, 2, NULL, NULL); | ||
| 365 | DEFINE_CLOCK(gpio2_clk, 1, CCM_CGR1, 4, NULL, NULL); | ||
| 366 | DEFINE_CLOCK(gpio3_clk, 2, CCM_CGR1, 6, NULL, NULL); | ||
| 367 | DEFINE_CLOCK(gpt_clk, 0, CCM_CGR1, 8, get_rate_ipg, NULL); | ||
| 368 | DEFINE_CLOCK(i2c1_clk, 0, CCM_CGR1, 10, get_rate_ipg_per, NULL); | ||
| 369 | DEFINE_CLOCK(i2c2_clk, 1, CCM_CGR1, 12, get_rate_ipg_per, NULL); | ||
| 370 | DEFINE_CLOCK(i2c3_clk, 2, CCM_CGR1, 14, get_rate_ipg_per, NULL); | ||
| 371 | DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL); | ||
| 372 | DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, NULL, NULL); | ||
| 373 | DEFINE_CLOCK(kpp_clk, 0, CCM_CGR1, 20, get_rate_ipg, NULL); | ||
| 374 | DEFINE_CLOCK(mlb_clk, 0, CCM_CGR1, 22, get_rate_ahb, NULL); | ||
| 375 | DEFINE_CLOCK(mshc_clk, 0, CCM_CGR1, 24, get_rate_mshc, NULL); | ||
| 376 | DEFINE_CLOCK(owire_clk, 0, CCM_CGR1, 26, get_rate_ipg_per, NULL); | ||
| 377 | DEFINE_CLOCK(pwm_clk, 0, CCM_CGR1, 28, get_rate_ipg_per, NULL); | ||
| 378 | DEFINE_CLOCK(rngc_clk, 0, CCM_CGR1, 30, get_rate_ipg, NULL); | ||
| 379 | |||
| 380 | DEFINE_CLOCK(rtc_clk, 0, CCM_CGR2, 0, get_rate_ipg, NULL); | ||
| 381 | DEFINE_CLOCK(rtic_clk, 0, CCM_CGR2, 2, get_rate_ahb, NULL); | ||
| 382 | DEFINE_CLOCK(scc_clk, 0, CCM_CGR2, 4, get_rate_ipg, NULL); | ||
| 383 | DEFINE_CLOCK(sdma_clk, 0, CCM_CGR2, 6, NULL, NULL); | ||
| 384 | DEFINE_CLOCK(spba_clk, 0, CCM_CGR2, 8, get_rate_ipg, NULL); | ||
| 385 | DEFINE_CLOCK(spdif_clk, 0, CCM_CGR2, 10, NULL, NULL); | ||
| 386 | DEFINE_CLOCK(ssi1_clk, 0, CCM_CGR2, 12, get_rate_ssi, NULL); | ||
| 387 | DEFINE_CLOCK(ssi2_clk, 1, CCM_CGR2, 14, get_rate_ssi, NULL); | ||
| 388 | DEFINE_CLOCK(uart1_clk, 0, CCM_CGR2, 16, get_rate_uart, NULL); | ||
| 389 | DEFINE_CLOCK(uart2_clk, 1, CCM_CGR2, 18, get_rate_uart, NULL); | ||
| 390 | DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL); | ||
| 391 | DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, NULL, NULL); | ||
| 392 | DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL); | ||
| 393 | DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL); | ||
| 394 | DEFINE_CLOCK(admux_clk, 0, CCM_CGR2, 30, NULL, NULL); | ||
| 395 | |||
| 396 | DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL); | ||
| 397 | DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL); | ||
| 398 | DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL); | ||
| 399 | |||
| 400 | #define _REGISTER_CLOCK(d, n, c) \ | ||
| 401 | { \ | ||
| 402 | .dev_id = d, \ | ||
| 403 | .con_id = n, \ | ||
| 404 | .clk = &c, \ | ||
| 405 | }, | ||
| 406 | |||
| 407 | static struct clk_lookup lookups[] __initdata = { | ||
| 408 | _REGISTER_CLOCK(NULL, "asrc", asrc_clk) | ||
| 409 | _REGISTER_CLOCK(NULL, "ata", ata_clk) | ||
| 410 | _REGISTER_CLOCK(NULL, "audmux", audmux_clk) | ||
| 411 | _REGISTER_CLOCK(NULL, "can", can1_clk) | ||
| 412 | _REGISTER_CLOCK(NULL, "can", can2_clk) | ||
| 413 | _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk) | ||
| 414 | _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk) | ||
| 415 | _REGISTER_CLOCK(NULL, "ect", ect_clk) | ||
| 416 | _REGISTER_CLOCK(NULL, "edio", edio_clk) | ||
| 417 | _REGISTER_CLOCK(NULL, "emi", emi_clk) | ||
| 418 | _REGISTER_CLOCK(NULL, "epit", epit1_clk) | ||
| 419 | _REGISTER_CLOCK(NULL, "epit", epit2_clk) | ||
| 420 | _REGISTER_CLOCK(NULL, "esai", esai_clk) | ||
| 421 | _REGISTER_CLOCK(NULL, "sdhc", esdhc1_clk) | ||
| 422 | _REGISTER_CLOCK(NULL, "sdhc", esdhc2_clk) | ||
| 423 | _REGISTER_CLOCK(NULL, "sdhc", esdhc3_clk) | ||
| 424 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) | ||
| 425 | _REGISTER_CLOCK(NULL, "gpio", gpio1_clk) | ||
| 426 | _REGISTER_CLOCK(NULL, "gpio", gpio2_clk) | ||
| 427 | _REGISTER_CLOCK(NULL, "gpio", gpio3_clk) | ||
| 428 | _REGISTER_CLOCK("gpt.0", NULL, gpt_clk) | ||
| 429 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) | ||
| 430 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) | ||
| 431 | _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk) | ||
| 432 | _REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk) | ||
| 433 | _REGISTER_CLOCK(NULL, "ipu", ipu_clk) | ||
| 434 | _REGISTER_CLOCK(NULL, "kpp", kpp_clk) | ||
| 435 | _REGISTER_CLOCK(NULL, "mlb", mlb_clk) | ||
| 436 | _REGISTER_CLOCK(NULL, "mshc", mshc_clk) | ||
| 437 | _REGISTER_CLOCK("mxc_w1", NULL, owire_clk) | ||
| 438 | _REGISTER_CLOCK(NULL, "pwm", pwm_clk) | ||
| 439 | _REGISTER_CLOCK(NULL, "rngc", rngc_clk) | ||
| 440 | _REGISTER_CLOCK(NULL, "rtc", rtc_clk) | ||
| 441 | _REGISTER_CLOCK(NULL, "rtic", rtic_clk) | ||
| 442 | _REGISTER_CLOCK(NULL, "scc", scc_clk) | ||
| 443 | _REGISTER_CLOCK(NULL, "sdma", sdma_clk) | ||
| 444 | _REGISTER_CLOCK(NULL, "spba", spba_clk) | ||
| 445 | _REGISTER_CLOCK(NULL, "spdif", spdif_clk) | ||
| 446 | _REGISTER_CLOCK(NULL, "ssi", ssi1_clk) | ||
| 447 | _REGISTER_CLOCK(NULL, "ssi", ssi2_clk) | ||
| 448 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) | ||
| 449 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) | ||
| 450 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) | ||
| 451 | _REGISTER_CLOCK(NULL, "usbotg", usbotg_clk) | ||
| 452 | _REGISTER_CLOCK("mxc_wdt.0", NULL, wdog_clk) | ||
| 453 | _REGISTER_CLOCK(NULL, "max", max_clk) | ||
| 454 | _REGISTER_CLOCK(NULL, "admux", admux_clk) | ||
| 455 | _REGISTER_CLOCK(NULL, "csi", csi_clk) | ||
| 456 | _REGISTER_CLOCK(NULL, "iim", iim_clk) | ||
| 457 | _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk) | ||
| 458 | }; | ||
| 459 | |||
| 460 | int __init mx35_clocks_init() | ||
| 461 | { | ||
| 462 | int i; | ||
| 463 | unsigned int ll = 0; | ||
| 464 | |||
| 465 | mxc_set_cpu_type(MXC_CPU_MX35); | ||
| 466 | |||
| 467 | #ifdef CONFIG_DEBUG_LL_CONSOLE | ||
| 468 | ll = (3 << 16); | ||
| 469 | #endif | ||
| 470 | |||
| 471 | for (i = 0; i < ARRAY_SIZE(lookups); i++) | ||
| 472 | clkdev_add(&lookups[i]); | ||
| 473 | |||
| 474 | /* Turn off all clocks except the ones we need to survive, namely: | ||
| 475 | * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart | ||
| 476 | */ | ||
| 477 | __raw_writel((3 << 18), CCM_BASE + CCM_CGR0); | ||
| 478 | __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16), | ||
| 479 | CCM_BASE + CCM_CGR1); | ||
| 480 | __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2); | ||
| 481 | __raw_writel(0, CCM_BASE + CCM_CGR3); | ||
| 482 | |||
| 483 | mxc_timer_init(&gpt_clk); | ||
| 484 | |||
| 485 | return 0; | ||
| 486 | } | ||
| 487 | |||
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c index b1746aae1f89..ca46f4801c3d 100644 --- a/arch/arm/mach-mx3/clock.c +++ b/arch/arm/mach-mx3/clock.c | |||
| @@ -23,9 +23,13 @@ | |||
| 23 | #include <linux/clk.h> | 23 | #include <linux/clk.h> |
| 24 | #include <linux/err.h> | 24 | #include <linux/err.h> |
| 25 | #include <linux/io.h> | 25 | #include <linux/io.h> |
| 26 | |||
| 27 | #include <asm/clkdev.h> | ||
| 28 | #include <asm/div64.h> | ||
| 29 | |||
| 26 | #include <mach/clock.h> | 30 | #include <mach/clock.h> |
| 27 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
| 28 | #include <asm/div64.h> | 32 | #include <mach/common.h> |
| 29 | 33 | ||
| 30 | #include "crm_regs.h" | 34 | #include "crm_regs.h" |
| 31 | 35 | ||
| @@ -64,17 +68,17 @@ static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post) | |||
| 64 | } | 68 | } |
| 65 | 69 | ||
| 66 | static struct clk mcu_pll_clk; | 70 | static struct clk mcu_pll_clk; |
| 67 | static struct clk mcu_main_clk; | ||
| 68 | static struct clk usb_pll_clk; | ||
| 69 | static struct clk serial_pll_clk; | 71 | static struct clk serial_pll_clk; |
| 70 | static struct clk ipg_clk; | 72 | static struct clk ipg_clk; |
| 71 | static struct clk ckih_clk; | 73 | static struct clk ckih_clk; |
| 72 | static struct clk ahb_clk; | ||
| 73 | 74 | ||
| 74 | static int _clk_enable(struct clk *clk) | 75 | static int cgr_enable(struct clk *clk) |
| 75 | { | 76 | { |
| 76 | u32 reg; | 77 | u32 reg; |
| 77 | 78 | ||
| 79 | if (!clk->enable_reg) | ||
| 80 | return 0; | ||
| 81 | |||
| 78 | reg = __raw_readl(clk->enable_reg); | 82 | reg = __raw_readl(clk->enable_reg); |
| 79 | reg |= 3 << clk->enable_shift; | 83 | reg |= 3 << clk->enable_shift; |
| 80 | __raw_writel(reg, clk->enable_reg); | 84 | __raw_writel(reg, clk->enable_reg); |
| @@ -82,133 +86,69 @@ static int _clk_enable(struct clk *clk) | |||
| 82 | return 0; | 86 | return 0; |
| 83 | } | 87 | } |
| 84 | 88 | ||
| 85 | static void _clk_disable(struct clk *clk) | 89 | static void cgr_disable(struct clk *clk) |
| 86 | { | 90 | { |
| 87 | u32 reg; | 91 | u32 reg; |
| 88 | 92 | ||
| 93 | if (!clk->enable_reg) | ||
| 94 | return; | ||
| 95 | |||
| 89 | reg = __raw_readl(clk->enable_reg); | 96 | reg = __raw_readl(clk->enable_reg); |
| 90 | reg &= ~(3 << clk->enable_shift); | 97 | reg &= ~(3 << clk->enable_shift); |
| 98 | |||
| 99 | /* special case for EMI clock */ | ||
| 100 | if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8) | ||
| 101 | reg |= (1 << clk->enable_shift); | ||
| 102 | |||
| 91 | __raw_writel(reg, clk->enable_reg); | 103 | __raw_writel(reg, clk->enable_reg); |
| 92 | } | 104 | } |
| 93 | 105 | ||
| 94 | static void _clk_emi_disable(struct clk *clk) | 106 | static unsigned long pll_ref_get_rate(void) |
| 95 | { | 107 | { |
| 96 | u32 reg; | 108 | unsigned long ccmr; |
| 109 | unsigned int prcs; | ||
| 97 | 110 | ||
| 98 | reg = __raw_readl(clk->enable_reg); | 111 | ccmr = __raw_readl(MXC_CCM_CCMR); |
| 99 | reg &= ~(3 << clk->enable_shift); | 112 | prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET; |
| 100 | reg |= (1 << clk->enable_shift); | 113 | if (prcs == 0x1) |
| 101 | __raw_writel(reg, clk->enable_reg); | 114 | return CKIL_CLK_FREQ * 1024; |
| 115 | else | ||
| 116 | return clk_get_rate(&ckih_clk); | ||
| 102 | } | 117 | } |
| 103 | 118 | ||
| 104 | static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) | 119 | static unsigned long usb_pll_get_rate(struct clk *clk) |
| 105 | { | 120 | { |
| 106 | u32 reg; | 121 | unsigned long reg; |
| 107 | signed long pd = 1; /* Pre-divider */ | ||
| 108 | signed long mfi; /* Multiplication Factor (Integer part) */ | ||
| 109 | signed long mfn; /* Multiplication Factor (Integer part) */ | ||
| 110 | signed long mfd; /* Multiplication Factor (Denominator Part) */ | ||
| 111 | signed long tmp; | ||
| 112 | u32 ref_freq = clk_get_rate(clk->parent); | ||
| 113 | 122 | ||
| 114 | while (((ref_freq / pd) * 10) > rate) | 123 | reg = __raw_readl(MXC_CCM_UPCTL); |
| 115 | pd++; | ||
| 116 | 124 | ||
| 117 | if ((ref_freq / pd) < PRE_DIV_MIN_FREQ) | 125 | return mxc_decode_pll(reg, pll_ref_get_rate()); |
| 118 | return -EINVAL; | 126 | } |
| 119 | 127 | ||
| 120 | /* the ref_freq/2 in the following is to round up */ | 128 | static unsigned long serial_pll_get_rate(struct clk *clk) |
| 121 | mfi = (((rate / 2) * pd) + (ref_freq / 2)) / ref_freq; | 129 | { |
| 122 | if (mfi < 5 || mfi > 15) | 130 | unsigned long reg; |
| 123 | return -EINVAL; | ||
| 124 | 131 | ||
| 125 | /* pick a mfd value that will work | 132 | reg = __raw_readl(MXC_CCM_SRPCTL); |
| 126 | * then solve for mfn */ | ||
| 127 | mfd = ref_freq / 50000; | ||
| 128 | |||
| 129 | /* | ||
| 130 | * pll_freq * pd * mfd | ||
| 131 | * mfn = -------------------- - (mfi * mfd) | ||
| 132 | * 2 * ref_freq | ||
| 133 | */ | ||
| 134 | /* the tmp/2 is for rounding */ | ||
| 135 | tmp = ref_freq / 10000; | ||
| 136 | mfn = | ||
| 137 | ((((((rate / 2) + (tmp / 2)) / tmp) * pd) * mfd) / 10000) - | ||
| 138 | (mfi * mfd); | ||
| 139 | |||
| 140 | mfn = mfn & 0x3ff; | ||
| 141 | pd--; | ||
| 142 | mfd--; | ||
| 143 | |||
| 144 | /* Change the Pll value */ | ||
| 145 | reg = (mfi << MXC_CCM_PCTL_MFI_OFFSET) | | ||
| 146 | (mfn << MXC_CCM_PCTL_MFN_OFFSET) | | ||
| 147 | (mfd << MXC_CCM_PCTL_MFD_OFFSET) | (pd << MXC_CCM_PCTL_PD_OFFSET); | ||
| 148 | |||
| 149 | if (clk == &mcu_pll_clk) | ||
| 150 | __raw_writel(reg, MXC_CCM_MPCTL); | ||
| 151 | else if (clk == &usb_pll_clk) | ||
| 152 | __raw_writel(reg, MXC_CCM_UPCTL); | ||
| 153 | else if (clk == &serial_pll_clk) | ||
| 154 | __raw_writel(reg, MXC_CCM_SRPCTL); | ||
| 155 | 133 | ||
| 156 | return 0; | 134 | return mxc_decode_pll(reg, pll_ref_get_rate()); |
| 157 | } | 135 | } |
| 158 | 136 | ||
| 159 | static unsigned long _clk_pll_get_rate(struct clk *clk) | 137 | static unsigned long mcu_pll_get_rate(struct clk *clk) |
| 160 | { | 138 | { |
| 161 | long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; | ||
| 162 | unsigned long reg, ccmr; | 139 | unsigned long reg, ccmr; |
| 163 | s64 temp; | ||
| 164 | unsigned int prcs; | ||
| 165 | 140 | ||
| 166 | ccmr = __raw_readl(MXC_CCM_CCMR); | 141 | ccmr = __raw_readl(MXC_CCM_CCMR); |
| 167 | prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET; | ||
| 168 | if (prcs == 0x1) | ||
| 169 | ref_clk = CKIL_CLK_FREQ * 1024; | ||
| 170 | else | ||
| 171 | ref_clk = clk_get_rate(&ckih_clk); | ||
| 172 | |||
| 173 | if (clk == &mcu_pll_clk) { | ||
| 174 | if ((ccmr & MXC_CCM_CCMR_MPE) == 0) | ||
| 175 | return ref_clk; | ||
| 176 | if ((ccmr & MXC_CCM_CCMR_MDS) != 0) | ||
| 177 | return ref_clk; | ||
| 178 | reg = __raw_readl(MXC_CCM_MPCTL); | ||
| 179 | } else if (clk == &usb_pll_clk) | ||
| 180 | reg = __raw_readl(MXC_CCM_UPCTL); | ||
| 181 | else if (clk == &serial_pll_clk) | ||
| 182 | reg = __raw_readl(MXC_CCM_SRPCTL); | ||
| 183 | else { | ||
| 184 | BUG(); | ||
| 185 | return 0; | ||
| 186 | } | ||
| 187 | |||
| 188 | pdf = (reg & MXC_CCM_PCTL_PD_MASK) >> MXC_CCM_PCTL_PD_OFFSET; | ||
| 189 | mfd = (reg & MXC_CCM_PCTL_MFD_MASK) >> MXC_CCM_PCTL_MFD_OFFSET; | ||
| 190 | mfi = (reg & MXC_CCM_PCTL_MFI_MASK) >> MXC_CCM_PCTL_MFI_OFFSET; | ||
| 191 | mfi = (mfi <= 5) ? 5 : mfi; | ||
| 192 | mfn = mfn_abs = reg & MXC_CCM_PCTL_MFN_MASK; | ||
| 193 | 142 | ||
| 194 | if (mfn >= 0x200) { | 143 | if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS)) |
| 195 | mfn |= 0xFFFFFE00; | 144 | return clk_get_rate(&ckih_clk); |
| 196 | mfn_abs = -mfn; | ||
| 197 | } | ||
| 198 | |||
| 199 | ref_clk *= 2; | ||
| 200 | ref_clk /= pdf + 1; | ||
| 201 | 145 | ||
| 202 | temp = (u64) ref_clk * mfn_abs; | 146 | reg = __raw_readl(MXC_CCM_MPCTL); |
| 203 | do_div(temp, mfd + 1); | ||
| 204 | if (mfn < 0) | ||
| 205 | temp = -temp; | ||
| 206 | temp = (ref_clk * mfi) + temp; | ||
| 207 | 147 | ||
| 208 | return temp; | 148 | return mxc_decode_pll(reg, pll_ref_get_rate()); |
| 209 | } | 149 | } |
| 210 | 150 | ||
| 211 | static int _clk_usb_pll_enable(struct clk *clk) | 151 | static int usb_pll_enable(struct clk *clk) |
| 212 | { | 152 | { |
| 213 | u32 reg; | 153 | u32 reg; |
| 214 | 154 | ||
| @@ -222,7 +162,7 @@ static int _clk_usb_pll_enable(struct clk *clk) | |||
| 222 | return 0; | 162 | return 0; |
| 223 | } | 163 | } |
| 224 | 164 | ||
| 225 | static void _clk_usb_pll_disable(struct clk *clk) | 165 | static void usb_pll_disable(struct clk *clk) |
| 226 | { | 166 | { |
| 227 | u32 reg; | 167 | u32 reg; |
| 228 | 168 | ||
| @@ -231,7 +171,7 @@ static void _clk_usb_pll_disable(struct clk *clk) | |||
| 231 | __raw_writel(reg, MXC_CCM_CCMR); | 171 | __raw_writel(reg, MXC_CCM_CCMR); |
| 232 | } | 172 | } |
| 233 | 173 | ||
| 234 | static int _clk_serial_pll_enable(struct clk *clk) | 174 | static int serial_pll_enable(struct clk *clk) |
| 235 | { | 175 | { |
| 236 | u32 reg; | 176 | u32 reg; |
| 237 | 177 | ||
| @@ -245,7 +185,7 @@ static int _clk_serial_pll_enable(struct clk *clk) | |||
| 245 | return 0; | 185 | return 0; |
| 246 | } | 186 | } |
| 247 | 187 | ||
| 248 | static void _clk_serial_pll_disable(struct clk *clk) | 188 | static void serial_pll_disable(struct clk *clk) |
| 249 | { | 189 | { |
| 250 | u32 reg; | 190 | u32 reg; |
| 251 | 191 | ||
| @@ -258,7 +198,7 @@ static void _clk_serial_pll_disable(struct clk *clk) | |||
| 258 | #define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off) | 198 | #define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off) |
| 259 | #define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off) | 199 | #define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off) |
| 260 | 200 | ||
| 261 | static unsigned long _clk_mcu_main_get_rate(struct clk *clk) | 201 | static unsigned long mcu_main_get_rate(struct clk *clk) |
| 262 | { | 202 | { |
| 263 | u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0); | 203 | u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0); |
| 264 | 204 | ||
| @@ -268,7 +208,7 @@ static unsigned long _clk_mcu_main_get_rate(struct clk *clk) | |||
| 268 | return clk_get_rate(&mcu_pll_clk); | 208 | return clk_get_rate(&mcu_pll_clk); |
| 269 | } | 209 | } |
| 270 | 210 | ||
| 271 | static unsigned long _clk_hclk_get_rate(struct clk *clk) | 211 | static unsigned long ahb_get_rate(struct clk *clk) |
| 272 | { | 212 | { |
| 273 | unsigned long max_pdf; | 213 | unsigned long max_pdf; |
| 274 | 214 | ||
| @@ -277,7 +217,7 @@ static unsigned long _clk_hclk_get_rate(struct clk *clk) | |||
| 277 | return clk_get_rate(clk->parent) / (max_pdf + 1); | 217 | return clk_get_rate(clk->parent) / (max_pdf + 1); |
| 278 | } | 218 | } |
| 279 | 219 | ||
| 280 | static unsigned long _clk_ipg_get_rate(struct clk *clk) | 220 | static unsigned long ipg_get_rate(struct clk *clk) |
| 281 | { | 221 | { |
| 282 | unsigned long ipg_pdf; | 222 | unsigned long ipg_pdf; |
| 283 | 223 | ||
| @@ -286,7 +226,7 @@ static unsigned long _clk_ipg_get_rate(struct clk *clk) | |||
| 286 | return clk_get_rate(clk->parent) / (ipg_pdf + 1); | 226 | return clk_get_rate(clk->parent) / (ipg_pdf + 1); |
| 287 | } | 227 | } |
| 288 | 228 | ||
| 289 | static unsigned long _clk_nfc_get_rate(struct clk *clk) | 229 | static unsigned long nfc_get_rate(struct clk *clk) |
| 290 | { | 230 | { |
| 291 | unsigned long nfc_pdf; | 231 | unsigned long nfc_pdf; |
| 292 | 232 | ||
| @@ -295,7 +235,7 @@ static unsigned long _clk_nfc_get_rate(struct clk *clk) | |||
| 295 | return clk_get_rate(clk->parent) / (nfc_pdf + 1); | 235 | return clk_get_rate(clk->parent) / (nfc_pdf + 1); |
| 296 | } | 236 | } |
| 297 | 237 | ||
| 298 | static unsigned long _clk_hsp_get_rate(struct clk *clk) | 238 | static unsigned long hsp_get_rate(struct clk *clk) |
| 299 | { | 239 | { |
| 300 | unsigned long hsp_pdf; | 240 | unsigned long hsp_pdf; |
| 301 | 241 | ||
| @@ -304,7 +244,7 @@ static unsigned long _clk_hsp_get_rate(struct clk *clk) | |||
| 304 | return clk_get_rate(clk->parent) / (hsp_pdf + 1); | 244 | return clk_get_rate(clk->parent) / (hsp_pdf + 1); |
| 305 | } | 245 | } |
| 306 | 246 | ||
| 307 | static unsigned long _clk_usb_get_rate(struct clk *clk) | 247 | static unsigned long usb_get_rate(struct clk *clk) |
| 308 | { | 248 | { |
| 309 | unsigned long usb_pdf, usb_prepdf; | 249 | unsigned long usb_pdf, usb_prepdf; |
| 310 | 250 | ||
| @@ -315,7 +255,7 @@ static unsigned long _clk_usb_get_rate(struct clk *clk) | |||
| 315 | return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1); | 255 | return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1); |
| 316 | } | 256 | } |
| 317 | 257 | ||
| 318 | static unsigned long _clk_csi_get_rate(struct clk *clk) | 258 | static unsigned long csi_get_rate(struct clk *clk) |
| 319 | { | 259 | { |
| 320 | u32 reg, pre, post; | 260 | u32 reg, pre, post; |
| 321 | 261 | ||
| @@ -329,7 +269,7 @@ static unsigned long _clk_csi_get_rate(struct clk *clk) | |||
| 329 | return clk_get_rate(clk->parent) / (pre * post); | 269 | return clk_get_rate(clk->parent) / (pre * post); |
| 330 | } | 270 | } |
| 331 | 271 | ||
| 332 | static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate) | 272 | static unsigned long csi_round_rate(struct clk *clk, unsigned long rate) |
| 333 | { | 273 | { |
| 334 | u32 pre, post, parent = clk_get_rate(clk->parent); | 274 | u32 pre, post, parent = clk_get_rate(clk->parent); |
| 335 | u32 div = parent / rate; | 275 | u32 div = parent / rate; |
| @@ -342,7 +282,7 @@ static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate) | |||
| 342 | return parent / (pre * post); | 282 | return parent / (pre * post); |
| 343 | } | 283 | } |
| 344 | 284 | ||
| 345 | static int _clk_csi_set_rate(struct clk *clk, unsigned long rate) | 285 | static int csi_set_rate(struct clk *clk, unsigned long rate) |
| 346 | { | 286 | { |
| 347 | u32 reg, div, pre, post, parent = clk_get_rate(clk->parent); | 287 | u32 reg, div, pre, post, parent = clk_get_rate(clk->parent); |
| 348 | 288 | ||
| @@ -363,16 +303,7 @@ static int _clk_csi_set_rate(struct clk *clk, unsigned long rate) | |||
| 363 | return 0; | 303 | return 0; |
| 364 | } | 304 | } |
| 365 | 305 | ||
| 366 | static unsigned long _clk_per_get_rate(struct clk *clk) | 306 | static unsigned long ssi1_get_rate(struct clk *clk) |
| 367 | { | ||
| 368 | unsigned long per_pdf; | ||
| 369 | |||
| 370 | per_pdf = PDR0(MXC_CCM_PDR0_PER_PODF_MASK, | ||
| 371 | MXC_CCM_PDR0_PER_PODF_OFFSET); | ||
| 372 | return clk_get_rate(clk->parent) / (per_pdf + 1); | ||
| 373 | } | ||
| 374 | |||
| 375 | static unsigned long _clk_ssi1_get_rate(struct clk *clk) | ||
| 376 | { | 307 | { |
| 377 | unsigned long ssi1_pdf, ssi1_prepdf; | 308 | unsigned long ssi1_pdf, ssi1_prepdf; |
| 378 | 309 | ||
| @@ -383,7 +314,7 @@ static unsigned long _clk_ssi1_get_rate(struct clk *clk) | |||
| 383 | return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1); | 314 | return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1); |
| 384 | } | 315 | } |
| 385 | 316 | ||
| 386 | static unsigned long _clk_ssi2_get_rate(struct clk *clk) | 317 | static unsigned long ssi2_get_rate(struct clk *clk) |
| 387 | { | 318 | { |
| 388 | unsigned long ssi2_pdf, ssi2_prepdf; | 319 | unsigned long ssi2_pdf, ssi2_prepdf; |
| 389 | 320 | ||
| @@ -394,7 +325,7 @@ static unsigned long _clk_ssi2_get_rate(struct clk *clk) | |||
| 394 | return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1); | 325 | return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1); |
| 395 | } | 326 | } |
| 396 | 327 | ||
| 397 | static unsigned long _clk_firi_get_rate(struct clk *clk) | 328 | static unsigned long firi_get_rate(struct clk *clk) |
| 398 | { | 329 | { |
| 399 | unsigned long firi_pdf, firi_prepdf; | 330 | unsigned long firi_pdf, firi_prepdf; |
| 400 | 331 | ||
| @@ -405,7 +336,7 @@ static unsigned long _clk_firi_get_rate(struct clk *clk) | |||
| 405 | return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1); | 336 | return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1); |
| 406 | } | 337 | } |
| 407 | 338 | ||
| 408 | static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate) | 339 | static unsigned long firi_round_rate(struct clk *clk, unsigned long rate) |
| 409 | { | 340 | { |
| 410 | u32 pre, post; | 341 | u32 pre, post; |
| 411 | u32 parent = clk_get_rate(clk->parent); | 342 | u32 parent = clk_get_rate(clk->parent); |
| @@ -420,7 +351,7 @@ static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate) | |||
| 420 | 351 | ||
| 421 | } | 352 | } |
| 422 | 353 | ||
| 423 | static int _clk_firi_set_rate(struct clk *clk, unsigned long rate) | 354 | static int firi_set_rate(struct clk *clk, unsigned long rate) |
| 424 | { | 355 | { |
| 425 | u32 reg, div, pre, post, parent = clk_get_rate(clk->parent); | 356 | u32 reg, div, pre, post, parent = clk_get_rate(clk->parent); |
| 426 | 357 | ||
| @@ -441,12 +372,12 @@ static int _clk_firi_set_rate(struct clk *clk, unsigned long rate) | |||
| 441 | return 0; | 372 | return 0; |
| 442 | } | 373 | } |
| 443 | 374 | ||
| 444 | static unsigned long _clk_mbx_get_rate(struct clk *clk) | 375 | static unsigned long mbx_get_rate(struct clk *clk) |
| 445 | { | 376 | { |
| 446 | return clk_get_rate(clk->parent) / 2; | 377 | return clk_get_rate(clk->parent) / 2; |
| 447 | } | 378 | } |
| 448 | 379 | ||
| 449 | static unsigned long _clk_mstick1_get_rate(struct clk *clk) | 380 | static unsigned long mstick1_get_rate(struct clk *clk) |
| 450 | { | 381 | { |
| 451 | unsigned long msti_pdf; | 382 | unsigned long msti_pdf; |
| 452 | 383 | ||
| @@ -455,7 +386,7 @@ static unsigned long _clk_mstick1_get_rate(struct clk *clk) | |||
| 455 | return clk_get_rate(clk->parent) / (msti_pdf + 1); | 386 | return clk_get_rate(clk->parent) / (msti_pdf + 1); |
| 456 | } | 387 | } |
| 457 | 388 | ||
| 458 | static unsigned long _clk_mstick2_get_rate(struct clk *clk) | 389 | static unsigned long mstick2_get_rate(struct clk *clk) |
| 459 | { | 390 | { |
| 460 | unsigned long msti_pdf; | 391 | unsigned long msti_pdf; |
| 461 | 392 | ||
| @@ -472,661 +403,185 @@ static unsigned long clk_ckih_get_rate(struct clk *clk) | |||
| 472 | } | 403 | } |
| 473 | 404 | ||
| 474 | static struct clk ckih_clk = { | 405 | static struct clk ckih_clk = { |
| 475 | .name = "ckih", | ||
| 476 | .get_rate = clk_ckih_get_rate, | 406 | .get_rate = clk_ckih_get_rate, |
| 477 | }; | 407 | }; |
| 478 | 408 | ||
| 479 | static unsigned long clk_ckil_get_rate(struct clk *clk) | ||
| 480 | { | ||
| 481 | return CKIL_CLK_FREQ; | ||
| 482 | } | ||
| 483 | |||
| 484 | static struct clk ckil_clk = { | ||
| 485 | .name = "ckil", | ||
| 486 | .get_rate = clk_ckil_get_rate, | ||
| 487 | }; | ||
| 488 | |||
| 489 | static struct clk mcu_pll_clk = { | 409 | static struct clk mcu_pll_clk = { |
| 490 | .name = "mcu_pll", | ||
| 491 | .parent = &ckih_clk, | 410 | .parent = &ckih_clk, |
| 492 | .set_rate = _clk_pll_set_rate, | 411 | .get_rate = mcu_pll_get_rate, |
| 493 | .get_rate = _clk_pll_get_rate, | ||
| 494 | }; | 412 | }; |
| 495 | 413 | ||
| 496 | static struct clk mcu_main_clk = { | 414 | static struct clk mcu_main_clk = { |
| 497 | .name = "mcu_main_clk", | ||
| 498 | .parent = &mcu_pll_clk, | 415 | .parent = &mcu_pll_clk, |
| 499 | .get_rate = _clk_mcu_main_get_rate, | 416 | .get_rate = mcu_main_get_rate, |
| 500 | }; | 417 | }; |
| 501 | 418 | ||
| 502 | static struct clk serial_pll_clk = { | 419 | static struct clk serial_pll_clk = { |
| 503 | .name = "serial_pll", | ||
| 504 | .parent = &ckih_clk, | 420 | .parent = &ckih_clk, |
| 505 | .set_rate = _clk_pll_set_rate, | 421 | .get_rate = serial_pll_get_rate, |
| 506 | .get_rate = _clk_pll_get_rate, | 422 | .enable = serial_pll_enable, |
| 507 | .enable = _clk_serial_pll_enable, | 423 | .disable = serial_pll_disable, |
| 508 | .disable = _clk_serial_pll_disable, | ||
| 509 | }; | 424 | }; |
| 510 | 425 | ||
| 511 | static struct clk usb_pll_clk = { | 426 | static struct clk usb_pll_clk = { |
| 512 | .name = "usb_pll", | ||
| 513 | .parent = &ckih_clk, | 427 | .parent = &ckih_clk, |
| 514 | .set_rate = _clk_pll_set_rate, | 428 | .get_rate = usb_pll_get_rate, |
| 515 | .get_rate = _clk_pll_get_rate, | 429 | .enable = usb_pll_enable, |
| 516 | .enable = _clk_usb_pll_enable, | 430 | .disable = usb_pll_disable, |
| 517 | .disable = _clk_usb_pll_disable, | ||
| 518 | }; | 431 | }; |
| 519 | 432 | ||
| 520 | static struct clk ahb_clk = { | 433 | static struct clk ahb_clk = { |
| 521 | .name = "ahb_clk", | ||
| 522 | .parent = &mcu_main_clk, | 434 | .parent = &mcu_main_clk, |
| 523 | .get_rate = _clk_hclk_get_rate, | 435 | .get_rate = ahb_get_rate, |
| 524 | }; | 436 | }; |
| 525 | 437 | ||
| 526 | static struct clk per_clk = { | 438 | #define DEFINE_CLOCK(name, i, er, es, gr, s, p) \ |
| 527 | .name = "per_clk", | 439 | static struct clk name = { \ |
| 528 | .parent = &usb_pll_clk, | 440 | .id = i, \ |
| 529 | .get_rate = _clk_per_get_rate, | 441 | .enable_reg = er, \ |
| 530 | }; | 442 | .enable_shift = es, \ |
| 531 | 443 | .get_rate = gr, \ | |
| 532 | static struct clk perclk_clk = { | 444 | .enable = cgr_enable, \ |
| 533 | .name = "perclk_clk", | 445 | .disable = cgr_disable, \ |
| 534 | .parent = &ipg_clk, | 446 | .secondary = s, \ |
| 535 | }; | 447 | .parent = p, \ |
| 536 | 448 | } | |
| 537 | static struct clk cspi_clk[] = { | ||
| 538 | { | ||
| 539 | .name = "cspi_clk", | ||
| 540 | .id = 0, | ||
| 541 | .parent = &ipg_clk, | ||
| 542 | .enable = _clk_enable, | ||
| 543 | .enable_reg = MXC_CCM_CGR2, | ||
| 544 | .enable_shift = MXC_CCM_CGR2_CSPI1_OFFSET, | ||
| 545 | .disable = _clk_disable,}, | ||
| 546 | { | ||
| 547 | .name = "cspi_clk", | ||
| 548 | .id = 1, | ||
| 549 | .parent = &ipg_clk, | ||
| 550 | .enable = _clk_enable, | ||
| 551 | .enable_reg = MXC_CCM_CGR2, | ||
| 552 | .enable_shift = MXC_CCM_CGR2_CSPI2_OFFSET, | ||
| 553 | .disable = _clk_disable,}, | ||
| 554 | { | ||
| 555 | .name = "cspi_clk", | ||
| 556 | .id = 2, | ||
| 557 | .parent = &ipg_clk, | ||
| 558 | .enable = _clk_enable, | ||
| 559 | .enable_reg = MXC_CCM_CGR0, | ||
| 560 | .enable_shift = MXC_CCM_CGR0_CSPI3_OFFSET, | ||
| 561 | .disable = _clk_disable,}, | ||
| 562 | }; | ||
| 563 | |||
| 564 | static struct clk ipg_clk = { | ||
| 565 | .name = "ipg_clk", | ||
| 566 | .parent = &ahb_clk, | ||
| 567 | .get_rate = _clk_ipg_get_rate, | ||
| 568 | }; | ||
| 569 | |||
| 570 | static struct clk emi_clk = { | ||
| 571 | .name = "emi_clk", | ||
| 572 | .parent = &ahb_clk, | ||
| 573 | .enable = _clk_enable, | ||
| 574 | .enable_reg = MXC_CCM_CGR2, | ||
| 575 | .enable_shift = MXC_CCM_CGR2_EMI_OFFSET, | ||
| 576 | .disable = _clk_emi_disable, | ||
| 577 | }; | ||
| 578 | |||
| 579 | static struct clk gpt_clk = { | ||
| 580 | .name = "gpt_clk", | ||
| 581 | .parent = &perclk_clk, | ||
| 582 | .enable = _clk_enable, | ||
| 583 | .enable_reg = MXC_CCM_CGR0, | ||
| 584 | .enable_shift = MXC_CCM_CGR0_GPT_OFFSET, | ||
| 585 | .disable = _clk_disable, | ||
| 586 | }; | ||
| 587 | |||
| 588 | static struct clk pwm_clk = { | ||
| 589 | .name = "pwm_clk", | ||
| 590 | .parent = &perclk_clk, | ||
| 591 | .enable = _clk_enable, | ||
| 592 | .enable_reg = MXC_CCM_CGR0, | ||
| 593 | .enable_shift = MXC_CCM_CGR1_PWM_OFFSET, | ||
| 594 | .disable = _clk_disable, | ||
| 595 | }; | ||
| 596 | |||
| 597 | static struct clk epit_clk[] = { | ||
| 598 | { | ||
| 599 | .name = "epit_clk", | ||
| 600 | .id = 0, | ||
| 601 | .parent = &perclk_clk, | ||
| 602 | .enable = _clk_enable, | ||
| 603 | .enable_reg = MXC_CCM_CGR0, | ||
| 604 | .enable_shift = MXC_CCM_CGR0_EPIT1_OFFSET, | ||
| 605 | .disable = _clk_disable,}, | ||
| 606 | { | ||
| 607 | .name = "epit_clk", | ||
| 608 | .id = 1, | ||
| 609 | .parent = &perclk_clk, | ||
| 610 | .enable = _clk_enable, | ||
| 611 | .enable_reg = MXC_CCM_CGR0, | ||
| 612 | .enable_shift = MXC_CCM_CGR0_EPIT2_OFFSET, | ||
| 613 | .disable = _clk_disable,}, | ||
| 614 | }; | ||
| 615 | |||
| 616 | static struct clk nfc_clk = { | ||
| 617 | .name = "nfc_clk", | ||
| 618 | .parent = &ahb_clk, | ||
| 619 | .get_rate = _clk_nfc_get_rate, | ||
| 620 | }; | ||
| 621 | |||
| 622 | static struct clk scc_clk = { | ||
| 623 | .name = "scc_clk", | ||
| 624 | .parent = &ipg_clk, | ||
| 625 | }; | ||
| 626 | |||
| 627 | static struct clk ipu_clk = { | ||
| 628 | .name = "ipu_clk", | ||
| 629 | .parent = &mcu_main_clk, | ||
| 630 | .get_rate = _clk_hsp_get_rate, | ||
| 631 | .enable = _clk_enable, | ||
| 632 | .enable_reg = MXC_CCM_CGR1, | ||
| 633 | .enable_shift = MXC_CCM_CGR1_IPU_OFFSET, | ||
| 634 | .disable = _clk_disable, | ||
| 635 | }; | ||
| 636 | |||
| 637 | static struct clk kpp_clk = { | ||
| 638 | .name = "kpp_clk", | ||
| 639 | .parent = &ipg_clk, | ||
| 640 | .enable = _clk_enable, | ||
| 641 | .enable_reg = MXC_CCM_CGR1, | ||
| 642 | .enable_shift = MXC_CCM_CGR1_KPP_OFFSET, | ||
| 643 | .disable = _clk_disable, | ||
| 644 | }; | ||
| 645 | |||
| 646 | static struct clk wdog_clk = { | ||
| 647 | .name = "wdog_clk", | ||
| 648 | .parent = &ipg_clk, | ||
| 649 | .enable = _clk_enable, | ||
| 650 | .enable_reg = MXC_CCM_CGR1, | ||
| 651 | .enable_shift = MXC_CCM_CGR1_WDOG_OFFSET, | ||
| 652 | .disable = _clk_disable, | ||
| 653 | }; | ||
| 654 | static struct clk rtc_clk = { | ||
| 655 | .name = "rtc_clk", | ||
| 656 | .parent = &ipg_clk, | ||
| 657 | .enable = _clk_enable, | ||
| 658 | .enable_reg = MXC_CCM_CGR1, | ||
| 659 | .enable_shift = MXC_CCM_CGR1_RTC_OFFSET, | ||
| 660 | .disable = _clk_disable, | ||
| 661 | }; | ||
| 662 | |||
| 663 | static struct clk usb_clk[] = { | ||
| 664 | { | ||
| 665 | .name = "usb_clk", | ||
| 666 | .parent = &usb_pll_clk, | ||
| 667 | .get_rate = _clk_usb_get_rate,}, | ||
| 668 | { | ||
| 669 | .name = "usb_ahb_clk", | ||
| 670 | .parent = &ahb_clk, | ||
| 671 | .enable = _clk_enable, | ||
| 672 | .enable_reg = MXC_CCM_CGR1, | ||
| 673 | .enable_shift = MXC_CCM_CGR1_USBOTG_OFFSET, | ||
| 674 | .disable = _clk_disable,}, | ||
| 675 | }; | ||
| 676 | |||
| 677 | static struct clk csi_clk = { | ||
| 678 | .name = "csi_clk", | ||
| 679 | .parent = &serial_pll_clk, | ||
| 680 | .get_rate = _clk_csi_get_rate, | ||
| 681 | .round_rate = _clk_csi_round_rate, | ||
| 682 | .set_rate = _clk_csi_set_rate, | ||
| 683 | .enable = _clk_enable, | ||
| 684 | .enable_reg = MXC_CCM_CGR1, | ||
| 685 | .enable_shift = MXC_CCM_CGR1_CSI_OFFSET, | ||
| 686 | .disable = _clk_disable, | ||
| 687 | }; | ||
| 688 | |||
| 689 | static struct clk uart_clk[] = { | ||
| 690 | { | ||
| 691 | .name = "uart_clk", | ||
| 692 | .id = 0, | ||
| 693 | .parent = &perclk_clk, | ||
| 694 | .enable = _clk_enable, | ||
| 695 | .enable_reg = MXC_CCM_CGR0, | ||
| 696 | .enable_shift = MXC_CCM_CGR0_UART1_OFFSET, | ||
| 697 | .disable = _clk_disable,}, | ||
| 698 | { | ||
| 699 | .name = "uart_clk", | ||
| 700 | .id = 1, | ||
| 701 | .parent = &perclk_clk, | ||
| 702 | .enable = _clk_enable, | ||
| 703 | .enable_reg = MXC_CCM_CGR0, | ||
| 704 | .enable_shift = MXC_CCM_CGR0_UART2_OFFSET, | ||
| 705 | .disable = _clk_disable,}, | ||
| 706 | { | ||
| 707 | .name = "uart_clk", | ||
| 708 | .id = 2, | ||
| 709 | .parent = &perclk_clk, | ||
| 710 | .enable = _clk_enable, | ||
| 711 | .enable_reg = MXC_CCM_CGR1, | ||
| 712 | .enable_shift = MXC_CCM_CGR1_UART3_OFFSET, | ||
| 713 | .disable = _clk_disable,}, | ||
| 714 | { | ||
| 715 | .name = "uart_clk", | ||
| 716 | .id = 3, | ||
| 717 | .parent = &perclk_clk, | ||
| 718 | .enable = _clk_enable, | ||
| 719 | .enable_reg = MXC_CCM_CGR1, | ||
| 720 | .enable_shift = MXC_CCM_CGR1_UART4_OFFSET, | ||
| 721 | .disable = _clk_disable,}, | ||
| 722 | { | ||
| 723 | .name = "uart_clk", | ||
| 724 | .id = 4, | ||
| 725 | .parent = &perclk_clk, | ||
| 726 | .enable = _clk_enable, | ||
| 727 | .enable_reg = MXC_CCM_CGR1, | ||
| 728 | .enable_shift = MXC_CCM_CGR1_UART5_OFFSET, | ||
| 729 | .disable = _clk_disable,}, | ||
| 730 | }; | ||
| 731 | |||
| 732 | static struct clk i2c_clk[] = { | ||
| 733 | { | ||
| 734 | .name = "i2c_clk", | ||
| 735 | .id = 0, | ||
| 736 | .parent = &perclk_clk, | ||
| 737 | .enable = _clk_enable, | ||
| 738 | .enable_reg = MXC_CCM_CGR0, | ||
| 739 | .enable_shift = MXC_CCM_CGR0_I2C1_OFFSET, | ||
| 740 | .disable = _clk_disable,}, | ||
| 741 | { | ||
| 742 | .name = "i2c_clk", | ||
| 743 | .id = 1, | ||
| 744 | .parent = &perclk_clk, | ||
| 745 | .enable = _clk_enable, | ||
| 746 | .enable_reg = MXC_CCM_CGR0, | ||
| 747 | .enable_shift = MXC_CCM_CGR0_I2C2_OFFSET, | ||
| 748 | .disable = _clk_disable,}, | ||
| 749 | { | ||
| 750 | .name = "i2c_clk", | ||
| 751 | .id = 2, | ||
| 752 | .parent = &perclk_clk, | ||
| 753 | .enable = _clk_enable, | ||
| 754 | .enable_reg = MXC_CCM_CGR0, | ||
| 755 | .enable_shift = MXC_CCM_CGR0_I2C3_OFFSET, | ||
| 756 | .disable = _clk_disable,}, | ||
| 757 | }; | ||
| 758 | |||
| 759 | static struct clk owire_clk = { | ||
| 760 | .name = "owire_clk", | ||
| 761 | .parent = &perclk_clk, | ||
| 762 | .enable_reg = MXC_CCM_CGR1, | ||
| 763 | .enable_shift = MXC_CCM_CGR1_OWIRE_OFFSET, | ||
| 764 | .enable = _clk_enable, | ||
| 765 | .disable = _clk_disable, | ||
| 766 | }; | ||
| 767 | |||
| 768 | static struct clk sdhc_clk[] = { | ||
| 769 | { | ||
| 770 | .name = "sdhc_clk", | ||
| 771 | .id = 0, | ||
| 772 | .parent = &perclk_clk, | ||
| 773 | .enable = _clk_enable, | ||
| 774 | .enable_reg = MXC_CCM_CGR0, | ||
| 775 | .enable_shift = MXC_CCM_CGR0_SD_MMC1_OFFSET, | ||
| 776 | .disable = _clk_disable,}, | ||
| 777 | { | ||
| 778 | .name = "sdhc_clk", | ||
| 779 | .id = 1, | ||
| 780 | .parent = &perclk_clk, | ||
| 781 | .enable = _clk_enable, | ||
| 782 | .enable_reg = MXC_CCM_CGR0, | ||
| 783 | .enable_shift = MXC_CCM_CGR0_SD_MMC2_OFFSET, | ||
| 784 | .disable = _clk_disable,}, | ||
| 785 | }; | ||
| 786 | |||
| 787 | static struct clk ssi_clk[] = { | ||
| 788 | { | ||
| 789 | .name = "ssi_clk", | ||
| 790 | .parent = &serial_pll_clk, | ||
| 791 | .get_rate = _clk_ssi1_get_rate, | ||
| 792 | .enable = _clk_enable, | ||
| 793 | .enable_reg = MXC_CCM_CGR0, | ||
| 794 | .enable_shift = MXC_CCM_CGR0_SSI1_OFFSET, | ||
| 795 | .disable = _clk_disable,}, | ||
| 796 | { | ||
| 797 | .name = "ssi_clk", | ||
| 798 | .id = 1, | ||
| 799 | .parent = &serial_pll_clk, | ||
| 800 | .get_rate = _clk_ssi2_get_rate, | ||
| 801 | .enable = _clk_enable, | ||
| 802 | .enable_reg = MXC_CCM_CGR2, | ||
| 803 | .enable_shift = MXC_CCM_CGR2_SSI2_OFFSET, | ||
| 804 | .disable = _clk_disable,}, | ||
| 805 | }; | ||
| 806 | |||
| 807 | static struct clk firi_clk = { | ||
| 808 | .name = "firi_clk", | ||
| 809 | .parent = &usb_pll_clk, | ||
| 810 | .round_rate = _clk_firi_round_rate, | ||
| 811 | .set_rate = _clk_firi_set_rate, | ||
| 812 | .get_rate = _clk_firi_get_rate, | ||
| 813 | .enable = _clk_enable, | ||
| 814 | .enable_reg = MXC_CCM_CGR2, | ||
| 815 | .enable_shift = MXC_CCM_CGR2_FIRI_OFFSET, | ||
| 816 | .disable = _clk_disable, | ||
| 817 | }; | ||
| 818 | |||
| 819 | static struct clk ata_clk = { | ||
| 820 | .name = "ata_clk", | ||
| 821 | .parent = &ipg_clk, | ||
| 822 | .enable = _clk_enable, | ||
| 823 | .enable_reg = MXC_CCM_CGR0, | ||
| 824 | .enable_shift = MXC_CCM_CGR0_ATA_OFFSET, | ||
| 825 | .disable = _clk_disable, | ||
| 826 | }; | ||
| 827 | |||
| 828 | static struct clk mbx_clk = { | ||
| 829 | .name = "mbx_clk", | ||
| 830 | .parent = &ahb_clk, | ||
| 831 | .enable = _clk_enable, | ||
| 832 | .enable_reg = MXC_CCM_CGR2, | ||
| 833 | .enable_shift = MXC_CCM_CGR2_GACC_OFFSET, | ||
| 834 | .get_rate = _clk_mbx_get_rate, | ||
| 835 | }; | ||
| 836 | |||
| 837 | static struct clk vpu_clk = { | ||
| 838 | .name = "vpu_clk", | ||
| 839 | .parent = &ahb_clk, | ||
| 840 | .enable = _clk_enable, | ||
| 841 | .enable_reg = MXC_CCM_CGR2, | ||
| 842 | .enable_shift = MXC_CCM_CGR2_GACC_OFFSET, | ||
| 843 | .get_rate = _clk_mbx_get_rate, | ||
| 844 | }; | ||
| 845 | |||
| 846 | static struct clk rtic_clk = { | ||
| 847 | .name = "rtic_clk", | ||
| 848 | .parent = &ahb_clk, | ||
| 849 | .enable = _clk_enable, | ||
| 850 | .enable_reg = MXC_CCM_CGR2, | ||
| 851 | .enable_shift = MXC_CCM_CGR2_RTIC_OFFSET, | ||
| 852 | .disable = _clk_disable, | ||
| 853 | }; | ||
| 854 | |||
| 855 | static struct clk rng_clk = { | ||
| 856 | .name = "rng_clk", | ||
| 857 | .parent = &ipg_clk, | ||
| 858 | .enable = _clk_enable, | ||
| 859 | .enable_reg = MXC_CCM_CGR0, | ||
| 860 | .enable_shift = MXC_CCM_CGR0_RNG_OFFSET, | ||
| 861 | .disable = _clk_disable, | ||
| 862 | }; | ||
| 863 | |||
| 864 | static struct clk sdma_clk[] = { | ||
| 865 | { | ||
| 866 | .name = "sdma_ahb_clk", | ||
| 867 | .parent = &ahb_clk, | ||
| 868 | .enable = _clk_enable, | ||
| 869 | .enable_reg = MXC_CCM_CGR0, | ||
| 870 | .enable_shift = MXC_CCM_CGR0_SDMA_OFFSET, | ||
| 871 | .disable = _clk_disable,}, | ||
| 872 | { | ||
| 873 | .name = "sdma_ipg_clk", | ||
| 874 | .parent = &ipg_clk,} | ||
| 875 | }; | ||
| 876 | |||
| 877 | static struct clk mpeg4_clk = { | ||
| 878 | .name = "mpeg4_clk", | ||
| 879 | .parent = &ahb_clk, | ||
| 880 | .enable = _clk_enable, | ||
| 881 | .enable_reg = MXC_CCM_CGR1, | ||
| 882 | .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET, | ||
| 883 | .disable = _clk_disable, | ||
| 884 | }; | ||
| 885 | |||
| 886 | static struct clk vl2cc_clk = { | ||
| 887 | .name = "vl2cc_clk", | ||
| 888 | .parent = &ahb_clk, | ||
| 889 | .enable = _clk_enable, | ||
| 890 | .enable_reg = MXC_CCM_CGR1, | ||
| 891 | .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET, | ||
| 892 | .disable = _clk_disable, | ||
| 893 | }; | ||
| 894 | |||
| 895 | static struct clk mstick_clk[] = { | ||
| 896 | { | ||
| 897 | .name = "mstick_clk", | ||
| 898 | .id = 0, | ||
| 899 | .parent = &usb_pll_clk, | ||
| 900 | .get_rate = _clk_mstick1_get_rate, | ||
| 901 | .enable = _clk_enable, | ||
| 902 | .enable_reg = MXC_CCM_CGR1, | ||
| 903 | .enable_shift = MXC_CCM_CGR1_MEMSTICK1_OFFSET, | ||
| 904 | .disable = _clk_disable,}, | ||
| 905 | { | ||
| 906 | .name = "mstick_clk", | ||
| 907 | .id = 1, | ||
| 908 | .parent = &usb_pll_clk, | ||
| 909 | .get_rate = _clk_mstick2_get_rate, | ||
| 910 | .enable = _clk_enable, | ||
| 911 | .enable_reg = MXC_CCM_CGR1, | ||
| 912 | .enable_shift = MXC_CCM_CGR1_MEMSTICK2_OFFSET, | ||
| 913 | .disable = _clk_disable,}, | ||
| 914 | }; | ||
| 915 | |||
| 916 | static struct clk iim_clk = { | ||
| 917 | .name = "iim_clk", | ||
| 918 | .parent = &ipg_clk, | ||
| 919 | .enable = _clk_enable, | ||
| 920 | .enable_reg = MXC_CCM_CGR0, | ||
| 921 | .enable_shift = MXC_CCM_CGR0_IIM_OFFSET, | ||
| 922 | .disable = _clk_disable, | ||
| 923 | }; | ||
| 924 | |||
| 925 | static unsigned long _clk_cko1_round_rate(struct clk *clk, unsigned long rate) | ||
| 926 | { | ||
| 927 | u32 div, parent = clk_get_rate(clk->parent); | ||
| 928 | |||
| 929 | div = parent / rate; | ||
| 930 | if (parent % rate) | ||
| 931 | div++; | ||
| 932 | |||
| 933 | if (div > 8) | ||
| 934 | div = 16; | ||
| 935 | else if (div > 4) | ||
| 936 | div = 8; | ||
| 937 | else if (div > 2) | ||
| 938 | div = 4; | ||
| 939 | |||
| 940 | return parent / div; | ||
| 941 | } | ||
| 942 | |||
| 943 | static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate) | ||
| 944 | { | ||
| 945 | u32 reg, div, parent = clk_get_rate(clk->parent); | ||
| 946 | |||
| 947 | div = parent / rate; | ||
| 948 | |||
| 949 | if (div == 16) | ||
| 950 | div = 4; | ||
| 951 | else if (div == 8) | ||
| 952 | div = 3; | ||
| 953 | else if (div == 4) | ||
| 954 | div = 2; | ||
| 955 | else if (div == 2) | ||
| 956 | div = 1; | ||
| 957 | else if (div == 1) | ||
| 958 | div = 0; | ||
| 959 | else | ||
| 960 | return -EINVAL; | ||
| 961 | |||
| 962 | reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOUTDIV_MASK; | ||
| 963 | reg |= div << MXC_CCM_COSR_CLKOUTDIV_OFFSET; | ||
| 964 | __raw_writel(reg, MXC_CCM_COSR); | ||
| 965 | |||
| 966 | return 0; | ||
| 967 | } | ||
| 968 | |||
| 969 | static unsigned long _clk_cko1_get_rate(struct clk *clk) | ||
| 970 | { | ||
| 971 | u32 div; | ||
| 972 | |||
| 973 | div = __raw_readl(MXC_CCM_COSR) & MXC_CCM_COSR_CLKOUTDIV_MASK >> | ||
| 974 | MXC_CCM_COSR_CLKOUTDIV_OFFSET; | ||
| 975 | |||
| 976 | return clk_get_rate(clk->parent) / (1 << div); | ||
| 977 | } | ||
| 978 | |||
| 979 | static int _clk_cko1_set_parent(struct clk *clk, struct clk *parent) | ||
| 980 | { | ||
| 981 | u32 reg; | ||
| 982 | |||
| 983 | reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOSEL_MASK; | ||
| 984 | |||
| 985 | if (parent == &mcu_main_clk) | ||
| 986 | reg |= 0 << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 987 | else if (parent == &ipg_clk) | ||
| 988 | reg |= 1 << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 989 | else if (parent == &usb_pll_clk) | ||
| 990 | reg |= 2 << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 991 | else if (parent == mcu_main_clk.parent) | ||
| 992 | reg |= 3 << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 993 | else if (parent == &ahb_clk) | ||
| 994 | reg |= 5 << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 995 | else if (parent == &serial_pll_clk) | ||
| 996 | reg |= 7 << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 997 | else if (parent == &ckih_clk) | ||
| 998 | reg |= 8 << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 999 | else if (parent == &emi_clk) | ||
| 1000 | reg |= 9 << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 1001 | else if (parent == &ipu_clk) | ||
| 1002 | reg |= 0xA << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 1003 | else if (parent == &nfc_clk) | ||
| 1004 | reg |= 0xB << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 1005 | else if (parent == &uart_clk[0]) | ||
| 1006 | reg |= 0xC << MXC_CCM_COSR_CLKOSEL_OFFSET; | ||
| 1007 | else | ||
| 1008 | return -EINVAL; | ||
| 1009 | |||
| 1010 | __raw_writel(reg, MXC_CCM_COSR); | ||
| 1011 | |||
| 1012 | return 0; | ||
| 1013 | } | ||
| 1014 | |||
| 1015 | static int _clk_cko1_enable(struct clk *clk) | ||
| 1016 | { | ||
| 1017 | u32 reg; | ||
| 1018 | |||
| 1019 | reg = __raw_readl(MXC_CCM_COSR) | MXC_CCM_COSR_CLKOEN; | ||
| 1020 | __raw_writel(reg, MXC_CCM_COSR); | ||
| 1021 | 449 | ||
| 1022 | return 0; | 450 | #define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \ |
| 1023 | } | 451 | static struct clk name = { \ |
| 452 | .id = i, \ | ||
| 453 | .enable_reg = er, \ | ||
| 454 | .enable_shift = es, \ | ||
| 455 | .get_rate = getsetround##_get_rate, \ | ||
| 456 | .set_rate = getsetround##_set_rate, \ | ||
| 457 | .round_rate = getsetround##_round_rate, \ | ||
| 458 | .enable = cgr_enable, \ | ||
| 459 | .disable = cgr_disable, \ | ||
| 460 | .secondary = s, \ | ||
| 461 | .parent = p, \ | ||
| 462 | } | ||
| 1024 | 463 | ||
| 1025 | static void _clk_cko1_disable(struct clk *clk) | 464 | DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk); |
| 465 | |||
| 466 | DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk); | ||
| 467 | DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk); | ||
| 468 | DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CGR0, 4, NULL, NULL, &perclk_clk); | ||
| 469 | DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk); | ||
| 470 | DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk); | ||
| 471 | DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk); | ||
| 472 | DEFINE_CLOCK(ata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk); | ||
| 473 | DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, &sdma_clk1, &ahb_clk); | ||
| 474 | DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk); | ||
| 475 | DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk); | ||
| 476 | DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk); | ||
| 477 | DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk); | ||
| 478 | DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk); | ||
| 479 | DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk); | ||
| 480 | DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk); | ||
| 481 | DEFINE_CLOCK(i2c3_clk, 2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk); | ||
| 482 | |||
| 483 | DEFINE_CLOCK(mpeg4_clk, 0, MXC_CCM_CGR1, 0, NULL, NULL, &ahb_clk); | ||
| 484 | DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk); | ||
| 485 | DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk); | ||
| 486 | DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &ahb_clk); | ||
| 487 | DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ipg_clk); | ||
| 488 | DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk); | ||
| 489 | DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk); | ||
| 490 | DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk); | ||
| 491 | DEFINE_CLOCK(kpp_clk, 0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk); | ||
| 492 | DEFINE_CLOCK(ipu_clk, 0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk); | ||
| 493 | DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk); | ||
| 494 | DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk); | ||
| 495 | DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk); | ||
| 496 | DEFINE_CLOCK(owire_clk, 0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk); | ||
| 497 | |||
| 498 | DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CGR2, 0, ssi2_get_rate, NULL, &serial_pll_clk); | ||
| 499 | DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CGR2, 2, NULL, NULL, &ipg_clk); | ||
| 500 | DEFINE_CLOCK(cspi2_clk, 1, MXC_CCM_CGR2, 4, NULL, NULL, &ipg_clk); | ||
| 501 | DEFINE_CLOCK(mbx_clk, 0, MXC_CCM_CGR2, 6, mbx_get_rate, NULL, &ahb_clk); | ||
| 502 | DEFINE_CLOCK(emi_clk, 0, MXC_CCM_CGR2, 8, NULL, NULL, &ahb_clk); | ||
| 503 | DEFINE_CLOCK(rtic_clk, 0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk); | ||
| 504 | DEFINE_CLOCK1(firi_clk, 0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk); | ||
| 505 | |||
| 506 | DEFINE_CLOCK(sdma_clk2, 0, NULL, 0, NULL, NULL, &ipg_clk); | ||
| 507 | DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk); | ||
| 508 | DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk); | ||
| 509 | DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk); | ||
| 510 | DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk); | ||
| 511 | |||
| 512 | #define _REGISTER_CLOCK(d, n, c) \ | ||
| 513 | { \ | ||
| 514 | .dev_id = d, \ | ||
| 515 | .con_id = n, \ | ||
| 516 | .clk = &c, \ | ||
| 517 | }, | ||
| 518 | |||
| 519 | static struct clk_lookup lookups[] __initdata = { | ||
| 520 | _REGISTER_CLOCK(NULL, "emi", emi_clk) | ||
| 521 | _REGISTER_CLOCK(NULL, "cspi", cspi1_clk) | ||
| 522 | _REGISTER_CLOCK(NULL, "cspi", cspi2_clk) | ||
| 523 | _REGISTER_CLOCK(NULL, "cspi", cspi3_clk) | ||
| 524 | _REGISTER_CLOCK(NULL, "gpt", gpt_clk) | ||
| 525 | _REGISTER_CLOCK(NULL, "pwm", pwm_clk) | ||
| 526 | _REGISTER_CLOCK(NULL, "wdog", wdog_clk) | ||
| 527 | _REGISTER_CLOCK(NULL, "rtc", rtc_clk) | ||
| 528 | _REGISTER_CLOCK(NULL, "epit", epit1_clk) | ||
| 529 | _REGISTER_CLOCK(NULL, "epit", epit2_clk) | ||
| 530 | _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk) | ||
| 531 | _REGISTER_CLOCK("ipu-core", NULL, ipu_clk) | ||
| 532 | _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk) | ||
| 533 | _REGISTER_CLOCK(NULL, "kpp", kpp_clk) | ||
| 534 | _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1) | ||
| 535 | _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2) | ||
| 536 | _REGISTER_CLOCK("mx3-camera.0", "csi", csi_clk) | ||
| 537 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) | ||
| 538 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) | ||
| 539 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) | ||
| 540 | _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk) | ||
| 541 | _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk) | ||
| 542 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) | ||
| 543 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) | ||
| 544 | _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk) | ||
| 545 | _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk) | ||
| 546 | _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk) | ||
| 547 | _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk) | ||
| 548 | _REGISTER_CLOCK(NULL, "ssi", ssi1_clk) | ||
| 549 | _REGISTER_CLOCK(NULL, "ssi", ssi2_clk) | ||
| 550 | _REGISTER_CLOCK(NULL, "firi", firi_clk) | ||
| 551 | _REGISTER_CLOCK(NULL, "ata", ata_clk) | ||
| 552 | _REGISTER_CLOCK(NULL, "rtic", rtic_clk) | ||
| 553 | _REGISTER_CLOCK(NULL, "rng", rng_clk) | ||
| 554 | _REGISTER_CLOCK(NULL, "sdma_ahb", sdma_clk1) | ||
| 555 | _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2) | ||
| 556 | _REGISTER_CLOCK(NULL, "mstick", mstick1_clk) | ||
| 557 | _REGISTER_CLOCK(NULL, "mstick", mstick2_clk) | ||
| 558 | _REGISTER_CLOCK(NULL, "scc", scc_clk) | ||
| 559 | _REGISTER_CLOCK(NULL, "iim", iim_clk) | ||
| 560 | _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk) | ||
| 561 | _REGISTER_CLOCK(NULL, "mbx", mbx_clk) | ||
| 562 | }; | ||
| 563 | |||
| 564 | int __init mx31_clocks_init(unsigned long fref) | ||
| 1026 | { | 565 | { |
| 1027 | u32 reg; | 566 | u32 reg; |
| 567 | int i; | ||
| 1028 | 568 | ||
| 1029 | reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOEN; | 569 | mxc_set_cpu_type(MXC_CPU_MX31); |
| 1030 | __raw_writel(reg, MXC_CCM_COSR); | ||
| 1031 | } | ||
| 1032 | |||
| 1033 | static struct clk cko1_clk = { | ||
| 1034 | .name = "cko1_clk", | ||
| 1035 | .get_rate = _clk_cko1_get_rate, | ||
| 1036 | .set_rate = _clk_cko1_set_rate, | ||
| 1037 | .round_rate = _clk_cko1_round_rate, | ||
| 1038 | .set_parent = _clk_cko1_set_parent, | ||
| 1039 | .enable = _clk_cko1_enable, | ||
| 1040 | .disable = _clk_cko1_disable, | ||
| 1041 | }; | ||
| 1042 | |||
| 1043 | static struct clk *mxc_clks[] = { | ||
| 1044 | &ckih_clk, | ||
| 1045 | &ckil_clk, | ||
| 1046 | &mcu_pll_clk, | ||
| 1047 | &usb_pll_clk, | ||
| 1048 | &serial_pll_clk, | ||
| 1049 | &mcu_main_clk, | ||
| 1050 | &ahb_clk, | ||
| 1051 | &per_clk, | ||
| 1052 | &perclk_clk, | ||
| 1053 | &cko1_clk, | ||
| 1054 | &emi_clk, | ||
| 1055 | &cspi_clk[0], | ||
| 1056 | &cspi_clk[1], | ||
| 1057 | &cspi_clk[2], | ||
| 1058 | &ipg_clk, | ||
| 1059 | &gpt_clk, | ||
| 1060 | &pwm_clk, | ||
| 1061 | &wdog_clk, | ||
| 1062 | &rtc_clk, | ||
| 1063 | &epit_clk[0], | ||
| 1064 | &epit_clk[1], | ||
| 1065 | &nfc_clk, | ||
| 1066 | &ipu_clk, | ||
| 1067 | &kpp_clk, | ||
| 1068 | &usb_clk[0], | ||
| 1069 | &usb_clk[1], | ||
| 1070 | &csi_clk, | ||
| 1071 | &uart_clk[0], | ||
| 1072 | &uart_clk[1], | ||
| 1073 | &uart_clk[2], | ||
| 1074 | &uart_clk[3], | ||
| 1075 | &uart_clk[4], | ||
| 1076 | &i2c_clk[0], | ||
| 1077 | &i2c_clk[1], | ||
| 1078 | &i2c_clk[2], | ||
| 1079 | &owire_clk, | ||
| 1080 | &sdhc_clk[0], | ||
| 1081 | &sdhc_clk[1], | ||
| 1082 | &ssi_clk[0], | ||
| 1083 | &ssi_clk[1], | ||
| 1084 | &firi_clk, | ||
| 1085 | &ata_clk, | ||
| 1086 | &rtic_clk, | ||
| 1087 | &rng_clk, | ||
| 1088 | &sdma_clk[0], | ||
| 1089 | &sdma_clk[1], | ||
| 1090 | &mstick_clk[0], | ||
| 1091 | &mstick_clk[1], | ||
| 1092 | &scc_clk, | ||
| 1093 | &iim_clk, | ||
| 1094 | }; | ||
| 1095 | |||
| 1096 | int __init mxc_clocks_init(unsigned long fref) | ||
| 1097 | { | ||
| 1098 | u32 reg; | ||
| 1099 | struct clk **clkp; | ||
| 1100 | 570 | ||
| 1101 | ckih_rate = fref; | 571 | ckih_rate = fref; |
| 1102 | 572 | ||
| 1103 | for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) | 573 | for (i = 0; i < ARRAY_SIZE(lookups); i++) |
| 1104 | clk_register(*clkp); | 574 | clkdev_add(&lookups[i]); |
| 1105 | |||
| 1106 | if (cpu_is_mx31()) { | ||
| 1107 | clk_register(&mpeg4_clk); | ||
| 1108 | clk_register(&mbx_clk); | ||
| 1109 | } else { | ||
| 1110 | clk_register(&vpu_clk); | ||
| 1111 | clk_register(&vl2cc_clk); | ||
| 1112 | } | ||
| 1113 | 575 | ||
| 1114 | /* Turn off all possible clocks */ | 576 | /* Turn off all possible clocks */ |
| 1115 | __raw_writel(MXC_CCM_CGR0_GPT_MASK, MXC_CCM_CGR0); | 577 | __raw_writel((3 << 4), MXC_CCM_CGR0); |
| 1116 | __raw_writel(0, MXC_CCM_CGR1); | 578 | __raw_writel(0, MXC_CCM_CGR1); |
| 1117 | 579 | __raw_writel((3 << 8) | (3 << 14) | (3 << 16)| | |
| 1118 | __raw_writel(MXC_CCM_CGR2_EMI_MASK | | ||
| 1119 | MXC_CCM_CGR2_IPMUX1_MASK | | ||
| 1120 | MXC_CCM_CGR2_IPMUX2_MASK | | ||
| 1121 | MXC_CCM_CGR2_MXCCLKENSEL_MASK | /* for MX32 */ | ||
| 1122 | MXC_CCM_CGR2_CHIKCAMPEN_MASK | /* for MX32 */ | ||
| 1123 | MXC_CCM_CGR2_OVRVPUBUSY_MASK | /* for MX32 */ | ||
| 1124 | 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for | 580 | 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for |
| 1125 | MX32, but still required to be set */ | 581 | MX32, but still required to be set */ |
| 1126 | MXC_CCM_CGR2); | 582 | MXC_CCM_CGR2); |
| 1127 | 583 | ||
| 1128 | clk_disable(&cko1_clk); | 584 | usb_pll_disable(&usb_pll_clk); |
| 1129 | clk_disable(&usb_pll_clk); | ||
| 1130 | 585 | ||
| 1131 | pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk)); | 586 | pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk)); |
| 1132 | 587 | ||
| @@ -1143,6 +598,8 @@ int __init mxc_clocks_init(unsigned long fref) | |||
| 1143 | __raw_writel(reg, MXC_CCM_PMCR1); | 598 | __raw_writel(reg, MXC_CCM_PMCR1); |
| 1144 | } | 599 | } |
| 1145 | 600 | ||
| 601 | mxc_timer_init(&ipg_clk); | ||
| 602 | |||
| 1146 | return 0; | 603 | return 0; |
| 1147 | } | 604 | } |
| 1148 | 605 | ||
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h index 4a0e0ede23bb..adfa3627ad84 100644 --- a/arch/arm/mach-mx3/crm_regs.h +++ b/arch/arm/mach-mx3/crm_regs.h | |||
| @@ -91,47 +91,6 @@ | |||
| 91 | #define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 | 91 | #define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 |
| 92 | #define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 | 92 | #define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 |
| 93 | 93 | ||
| 94 | #define MXC_CCM_PDR0_HSP_DIV_1 (0x0 << 11) | ||
| 95 | #define MXC_CCM_PDR0_HSP_DIV_2 (0x1 << 11) | ||
| 96 | #define MXC_CCM_PDR0_HSP_DIV_3 (0x2 << 11) | ||
| 97 | #define MXC_CCM_PDR0_HSP_DIV_4 (0x3 << 11) | ||
| 98 | #define MXC_CCM_PDR0_HSP_DIV_5 (0x4 << 11) | ||
| 99 | #define MXC_CCM_PDR0_HSP_DIV_6 (0x5 << 11) | ||
| 100 | #define MXC_CCM_PDR0_HSP_DIV_7 (0x6 << 11) | ||
| 101 | #define MXC_CCM_PDR0_HSP_DIV_8 (0x7 << 11) | ||
| 102 | |||
| 103 | #define MXC_CCM_PDR0_IPG_DIV_1 (0x0 << 6) | ||
| 104 | #define MXC_CCM_PDR0_IPG_DIV_2 (0x1 << 6) | ||
| 105 | #define MXC_CCM_PDR0_IPG_DIV_3 (0x2 << 6) | ||
| 106 | #define MXC_CCM_PDR0_IPG_DIV_4 (0x3 << 6) | ||
| 107 | |||
| 108 | #define MXC_CCM_PDR0_MAX_DIV_1 (0x0 << 3) | ||
| 109 | #define MXC_CCM_PDR0_MAX_DIV_2 (0x1 << 3) | ||
| 110 | #define MXC_CCM_PDR0_MAX_DIV_3 (0x2 << 3) | ||
| 111 | #define MXC_CCM_PDR0_MAX_DIV_4 (0x3 << 3) | ||
| 112 | #define MXC_CCM_PDR0_MAX_DIV_5 (0x4 << 3) | ||
| 113 | #define MXC_CCM_PDR0_MAX_DIV_6 (0x5 << 3) | ||
| 114 | #define MXC_CCM_PDR0_MAX_DIV_7 (0x6 << 3) | ||
| 115 | #define MXC_CCM_PDR0_MAX_DIV_8 (0x7 << 3) | ||
| 116 | |||
| 117 | #define MXC_CCM_PDR0_NFC_DIV_1 (0x0 << 8) | ||
| 118 | #define MXC_CCM_PDR0_NFC_DIV_2 (0x1 << 8) | ||
| 119 | #define MXC_CCM_PDR0_NFC_DIV_3 (0x2 << 8) | ||
| 120 | #define MXC_CCM_PDR0_NFC_DIV_4 (0x3 << 8) | ||
| 121 | #define MXC_CCM_PDR0_NFC_DIV_5 (0x4 << 8) | ||
| 122 | #define MXC_CCM_PDR0_NFC_DIV_6 (0x5 << 8) | ||
| 123 | #define MXC_CCM_PDR0_NFC_DIV_7 (0x6 << 8) | ||
| 124 | #define MXC_CCM_PDR0_NFC_DIV_8 (0x7 << 8) | ||
| 125 | |||
| 126 | #define MXC_CCM_PDR0_MCU_DIV_1 0x0 | ||
| 127 | #define MXC_CCM_PDR0_MCU_DIV_2 0x1 | ||
| 128 | #define MXC_CCM_PDR0_MCU_DIV_3 0x2 | ||
| 129 | #define MXC_CCM_PDR0_MCU_DIV_4 0x3 | ||
| 130 | #define MXC_CCM_PDR0_MCU_DIV_5 0x4 | ||
| 131 | #define MXC_CCM_PDR0_MCU_DIV_6 0x5 | ||
| 132 | #define MXC_CCM_PDR0_MCU_DIV_7 0x6 | ||
| 133 | #define MXC_CCM_PDR0_MCU_DIV_8 0x7 | ||
| 134 | |||
| 135 | #define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 | 94 | #define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 |
| 136 | #define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) | 95 | #define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) |
| 137 | #define MXC_CCM_PDR1_USB_PODF_OFFSET 27 | 96 | #define MXC_CCM_PDR1_USB_PODF_OFFSET 27 |
| @@ -152,118 +111,6 @@ | |||
| 152 | /* Bit definitions for RCSR */ | 111 | /* Bit definitions for RCSR */ |
| 153 | #define MXC_CCM_RCSR_NF16B 0x80000000 | 112 | #define MXC_CCM_RCSR_NF16B 0x80000000 |
| 154 | 113 | ||
| 155 | /* Bit definitions for both MCU, USB and SR PLL control registers */ | ||
| 156 | #define MXC_CCM_PCTL_BRM 0x80000000 | ||
| 157 | #define MXC_CCM_PCTL_PD_OFFSET 26 | ||
| 158 | #define MXC_CCM_PCTL_PD_MASK (0xF << 26) | ||
| 159 | #define MXC_CCM_PCTL_MFD_OFFSET 16 | ||
| 160 | #define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16) | ||
| 161 | #define MXC_CCM_PCTL_MFI_OFFSET 10 | ||
| 162 | #define MXC_CCM_PCTL_MFI_MASK (0xF << 10) | ||
| 163 | #define MXC_CCM_PCTL_MFN_OFFSET 0 | ||
| 164 | #define MXC_CCM_PCTL_MFN_MASK 0x3FF | ||
| 165 | |||
| 166 | #define MXC_CCM_CGR0_SD_MMC1_OFFSET 0 | ||
| 167 | #define MXC_CCM_CGR0_SD_MMC1_MASK (0x3 << 0) | ||
| 168 | #define MXC_CCM_CGR0_SD_MMC2_OFFSET 2 | ||
| 169 | #define MXC_CCM_CGR0_SD_MMC2_MASK (0x3 << 2) | ||
| 170 | #define MXC_CCM_CGR0_GPT_OFFSET 4 | ||
| 171 | #define MXC_CCM_CGR0_GPT_MASK (0x3 << 4) | ||
| 172 | #define MXC_CCM_CGR0_EPIT1_OFFSET 6 | ||
| 173 | #define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 6) | ||
| 174 | #define MXC_CCM_CGR0_EPIT2_OFFSET 8 | ||
| 175 | #define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 8) | ||
| 176 | #define MXC_CCM_CGR0_IIM_OFFSET 10 | ||
| 177 | #define MXC_CCM_CGR0_IIM_MASK (0x3 << 10) | ||
| 178 | #define MXC_CCM_CGR0_ATA_OFFSET 12 | ||
| 179 | #define MXC_CCM_CGR0_ATA_MASK (0x3 << 12) | ||
| 180 | #define MXC_CCM_CGR0_SDMA_OFFSET 14 | ||
| 181 | #define MXC_CCM_CGR0_SDMA_MASK (0x3 << 14) | ||
| 182 | #define MXC_CCM_CGR0_CSPI3_OFFSET 16 | ||
| 183 | #define MXC_CCM_CGR0_CSPI3_MASK (0x3 << 16) | ||
| 184 | #define MXC_CCM_CGR0_RNG_OFFSET 18 | ||
| 185 | #define MXC_CCM_CGR0_RNG_MASK (0x3 << 18) | ||
| 186 | #define MXC_CCM_CGR0_UART1_OFFSET 20 | ||
| 187 | #define MXC_CCM_CGR0_UART1_MASK (0x3 << 20) | ||
| 188 | #define MXC_CCM_CGR0_UART2_OFFSET 22 | ||
| 189 | #define MXC_CCM_CGR0_UART2_MASK (0x3 << 22) | ||
| 190 | #define MXC_CCM_CGR0_SSI1_OFFSET 24 | ||
| 191 | #define MXC_CCM_CGR0_SSI1_MASK (0x3 << 24) | ||
| 192 | #define MXC_CCM_CGR0_I2C1_OFFSET 26 | ||
| 193 | #define MXC_CCM_CGR0_I2C1_MASK (0x3 << 26) | ||
| 194 | #define MXC_CCM_CGR0_I2C2_OFFSET 28 | ||
| 195 | #define MXC_CCM_CGR0_I2C2_MASK (0x3 << 28) | ||
| 196 | #define MXC_CCM_CGR0_I2C3_OFFSET 30 | ||
| 197 | #define MXC_CCM_CGR0_I2C3_MASK (0x3 << 30) | ||
| 198 | |||
| 199 | #define MXC_CCM_CGR1_HANTRO_OFFSET 0 | ||
| 200 | #define MXC_CCM_CGR1_HANTRO_MASK (0x3 << 0) | ||
| 201 | #define MXC_CCM_CGR1_MEMSTICK1_OFFSET 2 | ||
| 202 | #define MXC_CCM_CGR1_MEMSTICK1_MASK (0x3 << 2) | ||
| 203 | #define MXC_CCM_CGR1_MEMSTICK2_OFFSET 4 | ||
| 204 | #define MXC_CCM_CGR1_MEMSTICK2_MASK (0x3 << 4) | ||
| 205 | #define MXC_CCM_CGR1_CSI_OFFSET 6 | ||
| 206 | #define MXC_CCM_CGR1_CSI_MASK (0x3 << 6) | ||
| 207 | #define MXC_CCM_CGR1_RTC_OFFSET 8 | ||
| 208 | #define MXC_CCM_CGR1_RTC_MASK (0x3 << 8) | ||
| 209 | #define MXC_CCM_CGR1_WDOG_OFFSET 10 | ||
| 210 | #define MXC_CCM_CGR1_WDOG_MASK (0x3 << 10) | ||
| 211 | #define MXC_CCM_CGR1_PWM_OFFSET 12 | ||
| 212 | #define MXC_CCM_CGR1_PWM_MASK (0x3 << 12) | ||
| 213 | #define MXC_CCM_CGR1_SIM_OFFSET 14 | ||
| 214 | #define MXC_CCM_CGR1_SIM_MASK (0x3 << 14) | ||
| 215 | #define MXC_CCM_CGR1_ECT_OFFSET 16 | ||
| 216 | #define MXC_CCM_CGR1_ECT_MASK (0x3 << 16) | ||
| 217 | #define MXC_CCM_CGR1_USBOTG_OFFSET 18 | ||
| 218 | #define MXC_CCM_CGR1_USBOTG_MASK (0x3 << 18) | ||
| 219 | #define MXC_CCM_CGR1_KPP_OFFSET 20 | ||
| 220 | #define MXC_CCM_CGR1_KPP_MASK (0x3 << 20) | ||
| 221 | #define MXC_CCM_CGR1_IPU_OFFSET 22 | ||
| 222 | #define MXC_CCM_CGR1_IPU_MASK (0x3 << 22) | ||
| 223 | #define MXC_CCM_CGR1_UART3_OFFSET 24 | ||
| 224 | #define MXC_CCM_CGR1_UART3_MASK (0x3 << 24) | ||
| 225 | #define MXC_CCM_CGR1_UART4_OFFSET 26 | ||
| 226 | #define MXC_CCM_CGR1_UART4_MASK (0x3 << 26) | ||
| 227 | #define MXC_CCM_CGR1_UART5_OFFSET 28 | ||
| 228 | #define MXC_CCM_CGR1_UART5_MASK (0x3 << 28) | ||
| 229 | #define MXC_CCM_CGR1_OWIRE_OFFSET 30 | ||
| 230 | #define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 30) | ||
| 231 | |||
| 232 | #define MXC_CCM_CGR2_SSI2_OFFSET 0 | ||
| 233 | #define MXC_CCM_CGR2_SSI2_MASK (0x3 << 0) | ||
| 234 | #define MXC_CCM_CGR2_CSPI1_OFFSET 2 | ||
| 235 | #define MXC_CCM_CGR2_CSPI1_MASK (0x3 << 2) | ||
| 236 | #define MXC_CCM_CGR2_CSPI2_OFFSET 4 | ||
| 237 | #define MXC_CCM_CGR2_CSPI2_MASK (0x3 << 4) | ||
| 238 | #define MXC_CCM_CGR2_GACC_OFFSET 6 | ||
| 239 | #define MXC_CCM_CGR2_GACC_MASK (0x3 << 6) | ||
| 240 | #define MXC_CCM_CGR2_EMI_OFFSET 8 | ||
| 241 | #define MXC_CCM_CGR2_EMI_MASK (0x3 << 8) | ||
| 242 | #define MXC_CCM_CGR2_RTIC_OFFSET 10 | ||
| 243 | #define MXC_CCM_CGR2_RTIC_MASK (0x3 << 10) | ||
| 244 | #define MXC_CCM_CGR2_FIRI_OFFSET 12 | ||
| 245 | #define MXC_CCM_CGR2_FIRI_MASK (0x3 << 12) | ||
| 246 | #define MXC_CCM_CGR2_IPMUX1_OFFSET 14 | ||
| 247 | #define MXC_CCM_CGR2_IPMUX1_MASK (0x3 << 14) | ||
| 248 | #define MXC_CCM_CGR2_IPMUX2_OFFSET 16 | ||
| 249 | #define MXC_CCM_CGR2_IPMUX2_MASK (0x3 << 16) | ||
| 250 | |||
| 251 | /* These new CGR2 bits are added in MX32 */ | ||
| 252 | #define MXC_CCM_CGR2_APMSYSCLKSEL_OFFSET 18 | ||
| 253 | #define MXC_CCM_CGR2_APMSYSCLKSEL_MASK (0x3 << 18) | ||
| 254 | #define MXC_CCM_CGR2_APMSSICLKSEL_OFFSET 20 | ||
| 255 | #define MXC_CCM_CGR2_APMSSICLKSEL_MASK (0x3 << 20) | ||
| 256 | #define MXC_CCM_CGR2_APMPERCLKSEL_OFFSET 22 | ||
| 257 | #define MXC_CCM_CGR2_APMPERCLKSEL_MASK (0x3 << 22) | ||
| 258 | #define MXC_CCM_CGR2_MXCCLKENSEL_OFFSET 24 | ||
| 259 | #define MXC_CCM_CGR2_MXCCLKENSEL_MASK (0x1 << 24) | ||
| 260 | #define MXC_CCM_CGR2_CHIKCAMPEN_OFFSET 25 | ||
| 261 | #define MXC_CCM_CGR2_CHIKCAMPEN_MASK (0x1 << 25) | ||
| 262 | #define MXC_CCM_CGR2_OVRVPUBUSY_OFFSET 26 | ||
| 263 | #define MXC_CCM_CGR2_OVRVPUBUSY_MASK (0x1 << 26) | ||
| 264 | #define MXC_CCM_CGR2_APMENA_OFFSET 30 | ||
| 265 | #define MXC_CCM_CGR2_AOMENA_MASK (0x1 << 30) | ||
| 266 | |||
| 267 | /* | 114 | /* |
| 268 | * LTR0 register offsets | 115 | * LTR0 register offsets |
| 269 | */ | 116 | */ |
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index f8428800f286..380be0c9b213 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c | |||
| @@ -25,6 +25,8 @@ | |||
| 25 | #include <mach/irqs.h> | 25 | #include <mach/irqs.h> |
| 26 | #include <mach/imx-uart.h> | 26 | #include <mach/imx-uart.h> |
| 27 | 27 | ||
| 28 | #include "devices.h" | ||
| 29 | |||
| 28 | static struct resource uart0[] = { | 30 | static struct resource uart0[] = { |
| 29 | { | 31 | { |
| 30 | .start = UART1_BASE_ADDR, | 32 | .start = UART1_BASE_ADDR, |
| @@ -82,6 +84,7 @@ struct platform_device mxc_uart_device2 = { | |||
| 82 | .num_resources = ARRAY_SIZE(uart2), | 84 | .num_resources = ARRAY_SIZE(uart2), |
| 83 | }; | 85 | }; |
| 84 | 86 | ||
| 87 | #ifdef CONFIG_ARCH_MX31 | ||
| 85 | static struct resource uart3[] = { | 88 | static struct resource uart3[] = { |
| 86 | { | 89 | { |
| 87 | .start = UART4_BASE_ADDR, | 90 | .start = UART4_BASE_ADDR, |
| @@ -119,6 +122,7 @@ struct platform_device mxc_uart_device4 = { | |||
| 119 | .resource = uart4, | 122 | .resource = uart4, |
| 120 | .num_resources = ARRAY_SIZE(uart4), | 123 | .num_resources = ARRAY_SIZE(uart4), |
| 121 | }; | 124 | }; |
| 125 | #endif /* CONFIG_ARCH_MX31 */ | ||
| 122 | 126 | ||
| 123 | /* GPIO port description */ | 127 | /* GPIO port description */ |
| 124 | static struct mxc_gpio_port imx_gpio_ports[] = { | 128 | static struct mxc_gpio_port imx_gpio_ports[] = { |
| @@ -164,8 +168,8 @@ struct platform_device mxc_w1_master_device = { | |||
| 164 | 168 | ||
| 165 | static struct resource mxc_nand_resources[] = { | 169 | static struct resource mxc_nand_resources[] = { |
| 166 | { | 170 | { |
| 167 | .start = NFC_BASE_ADDR, | 171 | .start = 0, /* runtime dependent */ |
| 168 | .end = NFC_BASE_ADDR + 0xfff, | 172 | .end = 0, |
| 169 | .flags = IORESOURCE_MEM | 173 | .flags = IORESOURCE_MEM |
| 170 | }, { | 174 | }, { |
| 171 | .start = MXC_INT_NANDFC, | 175 | .start = MXC_INT_NANDFC, |
| @@ -180,3 +184,188 @@ struct platform_device mxc_nand_device = { | |||
| 180 | .num_resources = ARRAY_SIZE(mxc_nand_resources), | 184 | .num_resources = ARRAY_SIZE(mxc_nand_resources), |
| 181 | .resource = mxc_nand_resources, | 185 | .resource = mxc_nand_resources, |
| 182 | }; | 186 | }; |
| 187 | |||
| 188 | static struct resource mxc_i2c0_resources[] = { | ||
| 189 | { | ||
| 190 | .start = I2C_BASE_ADDR, | ||
| 191 | .end = I2C_BASE_ADDR + SZ_4K - 1, | ||
| 192 | .flags = IORESOURCE_MEM, | ||
| 193 | }, | ||
| 194 | { | ||
| 195 | .start = MXC_INT_I2C, | ||
| 196 | .end = MXC_INT_I2C, | ||
| 197 | .flags = IORESOURCE_IRQ, | ||
| 198 | }, | ||
| 199 | }; | ||
| 200 | |||
| 201 | struct platform_device mxc_i2c_device0 = { | ||
| 202 | .name = "imx-i2c", | ||
| 203 | .id = 0, | ||
| 204 | .num_resources = ARRAY_SIZE(mxc_i2c0_resources), | ||
| 205 | .resource = mxc_i2c0_resources, | ||
| 206 | }; | ||
| 207 | |||
| 208 | static struct resource mxc_i2c1_resources[] = { | ||
| 209 | { | ||
| 210 | .start = I2C2_BASE_ADDR, | ||
| 211 | .end = I2C2_BASE_ADDR + SZ_4K - 1, | ||
| 212 | .flags = IORESOURCE_MEM, | ||
| 213 | }, | ||
| 214 | { | ||
| 215 | .start = MXC_INT_I2C2, | ||
| 216 | .end = MXC_INT_I2C2, | ||
| 217 | .flags = IORESOURCE_IRQ, | ||
| 218 | }, | ||
| 219 | }; | ||
| 220 | |||
| 221 | struct platform_device mxc_i2c_device1 = { | ||
| 222 | .name = "imx-i2c", | ||
| 223 | .id = 1, | ||
| 224 | .num_resources = ARRAY_SIZE(mxc_i2c1_resources), | ||
| 225 | .resource = mxc_i2c1_resources, | ||
| 226 | }; | ||
| 227 | |||
| 228 | static struct resource mxc_i2c2_resources[] = { | ||
| 229 | { | ||
| 230 | .start = I2C3_BASE_ADDR, | ||
| 231 | .end = I2C3_BASE_ADDR + SZ_4K - 1, | ||
| 232 | .flags = IORESOURCE_MEM, | ||
| 233 | }, | ||
| 234 | { | ||
| 235 | .start = MXC_INT_I2C3, | ||
| 236 | .end = MXC_INT_I2C3, | ||
| 237 | .flags = IORESOURCE_IRQ, | ||
| 238 | }, | ||
| 239 | }; | ||
| 240 | |||
| 241 | struct platform_device mxc_i2c_device2 = { | ||
| 242 | .name = "imx-i2c", | ||
| 243 | .id = 2, | ||
| 244 | .num_resources = ARRAY_SIZE(mxc_i2c2_resources), | ||
| 245 | .resource = mxc_i2c2_resources, | ||
| 246 | }; | ||
| 247 | |||
| 248 | #ifdef CONFIG_ARCH_MX31 | ||
| 249 | static struct resource mxcsdhc0_resources[] = { | ||
| 250 | { | ||
| 251 | .start = MMC_SDHC1_BASE_ADDR, | ||
| 252 | .end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1, | ||
| 253 | .flags = IORESOURCE_MEM, | ||
| 254 | }, { | ||
| 255 | .start = MXC_INT_MMC_SDHC1, | ||
| 256 | .end = MXC_INT_MMC_SDHC1, | ||
| 257 | .flags = IORESOURCE_IRQ, | ||
| 258 | }, | ||
| 259 | }; | ||
| 260 | |||
| 261 | static struct resource mxcsdhc1_resources[] = { | ||
| 262 | { | ||
| 263 | .start = MMC_SDHC2_BASE_ADDR, | ||
| 264 | .end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1, | ||
| 265 | .flags = IORESOURCE_MEM, | ||
| 266 | }, { | ||
| 267 | .start = MXC_INT_MMC_SDHC2, | ||
| 268 | .end = MXC_INT_MMC_SDHC2, | ||
| 269 | .flags = IORESOURCE_IRQ, | ||
| 270 | }, | ||
| 271 | }; | ||
| 272 | |||
| 273 | struct platform_device mxcsdhc_device0 = { | ||
| 274 | .name = "mxc-mmc", | ||
| 275 | .id = 0, | ||
| 276 | .num_resources = ARRAY_SIZE(mxcsdhc0_resources), | ||
| 277 | .resource = mxcsdhc0_resources, | ||
| 278 | }; | ||
| 279 | |||
| 280 | struct platform_device mxcsdhc_device1 = { | ||
| 281 | .name = "mxc-mmc", | ||
| 282 | .id = 1, | ||
| 283 | .num_resources = ARRAY_SIZE(mxcsdhc1_resources), | ||
| 284 | .resource = mxcsdhc1_resources, | ||
| 285 | }; | ||
| 286 | #endif /* CONFIG_ARCH_MX31 */ | ||
| 287 | |||
| 288 | /* i.MX31 Image Processing Unit */ | ||
| 289 | |||
| 290 | /* The resource order is important! */ | ||
| 291 | static struct resource mx3_ipu_rsrc[] = { | ||
| 292 | { | ||
| 293 | .start = IPU_CTRL_BASE_ADDR, | ||
| 294 | .end = IPU_CTRL_BASE_ADDR + 0x5F, | ||
| 295 | .flags = IORESOURCE_MEM, | ||
| 296 | }, { | ||
| 297 | .start = IPU_CTRL_BASE_ADDR + 0x88, | ||
| 298 | .end = IPU_CTRL_BASE_ADDR + 0xB3, | ||
| 299 | .flags = IORESOURCE_MEM, | ||
| 300 | }, { | ||
| 301 | .start = MXC_INT_IPU_SYN, | ||
| 302 | .end = MXC_INT_IPU_SYN, | ||
| 303 | .flags = IORESOURCE_IRQ, | ||
| 304 | }, { | ||
| 305 | .start = MXC_INT_IPU_ERR, | ||
| 306 | .end = MXC_INT_IPU_ERR, | ||
| 307 | .flags = IORESOURCE_IRQ, | ||
| 308 | }, | ||
| 309 | }; | ||
| 310 | |||
| 311 | struct platform_device mx3_ipu = { | ||
| 312 | .name = "ipu-core", | ||
| 313 | .id = -1, | ||
| 314 | .num_resources = ARRAY_SIZE(mx3_ipu_rsrc), | ||
| 315 | .resource = mx3_ipu_rsrc, | ||
| 316 | }; | ||
| 317 | |||
| 318 | static struct resource fb_resources[] = { | ||
| 319 | { | ||
| 320 | .start = IPU_CTRL_BASE_ADDR + 0xB4, | ||
| 321 | .end = IPU_CTRL_BASE_ADDR + 0x1BF, | ||
| 322 | .flags = IORESOURCE_MEM, | ||
| 323 | }, | ||
| 324 | }; | ||
| 325 | |||
| 326 | struct platform_device mx3_fb = { | ||
| 327 | .name = "mx3_sdc_fb", | ||
| 328 | .id = -1, | ||
| 329 | .num_resources = ARRAY_SIZE(fb_resources), | ||
| 330 | .resource = fb_resources, | ||
| 331 | .dev = { | ||
| 332 | .coherent_dma_mask = 0xffffffff, | ||
| 333 | }, | ||
| 334 | }; | ||
| 335 | |||
| 336 | #ifdef CONFIG_ARCH_MX35 | ||
| 337 | static struct resource mxc_fec_resources[] = { | ||
| 338 | { | ||
| 339 | .start = MXC_FEC_BASE_ADDR, | ||
| 340 | .end = MXC_FEC_BASE_ADDR + 0xfff, | ||
| 341 | .flags = IORESOURCE_MEM | ||
| 342 | }, { | ||
| 343 | .start = MXC_INT_FEC, | ||
| 344 | .end = MXC_INT_FEC, | ||
| 345 | .flags = IORESOURCE_IRQ | ||
| 346 | }, | ||
| 347 | }; | ||
| 348 | |||
| 349 | struct platform_device mxc_fec_device = { | ||
| 350 | .name = "fec", | ||
| 351 | .id = 0, | ||
| 352 | .num_resources = ARRAY_SIZE(mxc_fec_resources), | ||
| 353 | .resource = mxc_fec_resources, | ||
| 354 | }; | ||
| 355 | #endif | ||
| 356 | |||
| 357 | static int mx3_devices_init(void) | ||
| 358 | { | ||
| 359 | if (cpu_is_mx31()) { | ||
| 360 | mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR; | ||
| 361 | mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff; | ||
| 362 | } | ||
| 363 | if (cpu_is_mx35()) { | ||
| 364 | mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR; | ||
| 365 | mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff; | ||
| 366 | } | ||
| 367 | |||
| 368 | return 0; | ||
| 369 | } | ||
| 370 | |||
| 371 | subsys_initcall(mx3_devices_init); | ||
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h index 9949ef4e0694..88c04b296fab 100644 --- a/arch/arm/mach-mx3/devices.h +++ b/arch/arm/mach-mx3/devices.h | |||
| @@ -6,3 +6,11 @@ extern struct platform_device mxc_uart_device3; | |||
| 6 | extern struct platform_device mxc_uart_device4; | 6 | extern struct platform_device mxc_uart_device4; |
| 7 | extern struct platform_device mxc_w1_master_device; | 7 | extern struct platform_device mxc_w1_master_device; |
| 8 | extern struct platform_device mxc_nand_device; | 8 | extern struct platform_device mxc_nand_device; |
| 9 | extern struct platform_device mxc_i2c_device0; | ||
| 10 | extern struct platform_device mxc_i2c_device1; | ||
| 11 | extern struct platform_device mxc_i2c_device2; | ||
| 12 | extern struct platform_device mx3_ipu; | ||
| 13 | extern struct platform_device mx3_fb; | ||
| 14 | extern struct platform_device mxc_fec_device; | ||
| 15 | extern struct platform_device mxcsdhc_device0; | ||
| 16 | extern struct platform_device mxcsdhc_device1; | ||
diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c index 7a5088b519a8..40ffc5a664d9 100644 --- a/arch/arm/mach-mx3/iomux.c +++ b/arch/arm/mach-mx3/iomux.c | |||
| @@ -1,6 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. | 2 | * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | 3 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> |
| 4 | * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch> | ||
| 4 | * | 5 | * |
| 5 | * This program is free software; you can redistribute it and/or | 6 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License | 7 | * modify it under the terms of the GNU General Public License |
| @@ -21,6 +22,7 @@ | |||
| 21 | #include <linux/spinlock.h> | 22 | #include <linux/spinlock.h> |
| 22 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 23 | #include <linux/gpio.h> | 24 | #include <linux/gpio.h> |
| 25 | #include <linux/kernel.h> | ||
| 24 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
| 25 | #include <mach/gpio.h> | 27 | #include <mach/gpio.h> |
| 26 | #include <mach/iomux-mx3.h> | 28 | #include <mach/iomux-mx3.h> |
| @@ -38,6 +40,8 @@ | |||
| 38 | static DEFINE_SPINLOCK(gpio_mux_lock); | 40 | static DEFINE_SPINLOCK(gpio_mux_lock); |
| 39 | 41 | ||
| 40 | #define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3) | 42 | #define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3) |
| 43 | |||
| 44 | unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG]; | ||
| 41 | /* | 45 | /* |
| 42 | * set the mode for a IOMUX pin. | 46 | * set the mode for a IOMUX pin. |
| 43 | */ | 47 | */ |
| @@ -50,9 +54,6 @@ int mxc_iomux_mode(unsigned int pin_mode) | |||
| 50 | field = pin_mode & 0x3; | 54 | field = pin_mode & 0x3; |
| 51 | mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT; | 55 | mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT; |
| 52 | 56 | ||
| 53 | pr_debug("%s: reg offset = 0x%x field = %d mode = 0x%02x\n", | ||
| 54 | __func__, (pin_mode & IOMUX_REG_MASK), field, mode); | ||
| 55 | |||
| 56 | spin_lock(&gpio_mux_lock); | 57 | spin_lock(&gpio_mux_lock); |
| 57 | 58 | ||
| 58 | l = __raw_readl(reg); | 59 | l = __raw_readl(reg); |
| @@ -93,6 +94,86 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config) | |||
| 93 | EXPORT_SYMBOL(mxc_iomux_set_pad); | 94 | EXPORT_SYMBOL(mxc_iomux_set_pad); |
| 94 | 95 | ||
| 95 | /* | 96 | /* |
| 97 | * setups a single pin: | ||
| 98 | * - reserves the pin so that it is not claimed by another driver | ||
| 99 | * - setups the iomux according to the configuration | ||
| 100 | * - if the pin is configured as a GPIO, we claim it through kernel gpiolib | ||
| 101 | */ | ||
| 102 | int mxc_iomux_setup_pin(const unsigned int pin, const char *label) | ||
| 103 | { | ||
| 104 | unsigned pad = pin & IOMUX_PADNUM_MASK; | ||
| 105 | unsigned gpio; | ||
| 106 | |||
| 107 | if (pad >= (PIN_MAX + 1)) { | ||
| 108 | printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n", | ||
| 109 | pad, label ? label : "?"); | ||
| 110 | return -EINVAL; | ||
| 111 | } | ||
| 112 | |||
| 113 | if (test_and_set_bit(pad, mxc_pin_alloc_map)) { | ||
| 114 | printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n", | ||
| 115 | pad, label ? label : "?"); | ||
| 116 | return -EINVAL; | ||
| 117 | } | ||
| 118 | mxc_iomux_mode(pin); | ||
| 119 | |||
| 120 | /* if we have a gpio, we can allocate it */ | ||
| 121 | gpio = (pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT; | ||
| 122 | if (gpio < (GPIO_PORT_MAX + 1) * 32) | ||
| 123 | if (gpio_request(gpio, label)) | ||
| 124 | return -EINVAL; | ||
| 125 | |||
| 126 | return 0; | ||
| 127 | } | ||
| 128 | EXPORT_SYMBOL(mxc_iomux_setup_pin); | ||
| 129 | |||
| 130 | int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, | ||
| 131 | const char *label) | ||
| 132 | { | ||
| 133 | unsigned int *p = pin_list; | ||
| 134 | int i; | ||
| 135 | int ret = -EINVAL; | ||
| 136 | |||
| 137 | for (i = 0; i < count; i++) { | ||
| 138 | if (mxc_iomux_setup_pin(*p, label)) | ||
| 139 | goto setup_error; | ||
| 140 | p++; | ||
| 141 | } | ||
| 142 | return 0; | ||
| 143 | |||
| 144 | setup_error: | ||
| 145 | mxc_iomux_release_multiple_pins(pin_list, i); | ||
| 146 | return ret; | ||
| 147 | } | ||
| 148 | EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins); | ||
| 149 | |||
| 150 | void mxc_iomux_release_pin(const unsigned int pin) | ||
| 151 | { | ||
| 152 | unsigned pad = pin & IOMUX_PADNUM_MASK; | ||
| 153 | unsigned gpio; | ||
| 154 | |||
| 155 | if (pad < (PIN_MAX + 1)) | ||
| 156 | clear_bit(pad, mxc_pin_alloc_map); | ||
| 157 | |||
| 158 | gpio = (pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT; | ||
| 159 | if (gpio < (GPIO_PORT_MAX + 1) * 32) | ||
| 160 | gpio_free(gpio); | ||
| 161 | } | ||
| 162 | EXPORT_SYMBOL(mxc_iomux_release_pin); | ||
| 163 | |||
| 164 | void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count) | ||
| 165 | { | ||
| 166 | unsigned int *p = pin_list; | ||
| 167 | int i; | ||
| 168 | |||
| 169 | for (i = 0; i < count; i++) { | ||
| 170 | mxc_iomux_release_pin(*p); | ||
| 171 | p++; | ||
| 172 | } | ||
| 173 | } | ||
| 174 | EXPORT_SYMBOL(mxc_iomux_release_multiple_pins); | ||
| 175 | |||
| 176 | /* | ||
| 96 | * This function enables/disables the general purpose function for a particular | 177 | * This function enables/disables the general purpose function for a particular |
| 97 | * signal. | 178 | * signal. |
| 98 | */ | 179 | */ |
| @@ -111,4 +192,3 @@ void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en) | |||
| 111 | spin_unlock(&gpio_mux_lock); | 192 | spin_unlock(&gpio_mux_lock); |
| 112 | } | 193 | } |
| 113 | EXPORT_SYMBOL(mxc_iomux_set_gpr); | 194 | EXPORT_SYMBOL(mxc_iomux_set_gpr); |
| 114 | |||
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c index 0589b5cd33c7..9e1459cb4b74 100644 --- a/arch/arm/mach-mx3/mm.c +++ b/arch/arm/mach-mx3/mm.c | |||
| @@ -22,10 +22,14 @@ | |||
| 22 | 22 | ||
| 23 | #include <linux/mm.h> | 23 | #include <linux/mm.h> |
| 24 | #include <linux/init.h> | 24 | #include <linux/init.h> |
| 25 | #include <mach/hardware.h> | 25 | #include <linux/err.h> |
| 26 | |||
| 26 | #include <asm/pgtable.h> | 27 | #include <asm/pgtable.h> |
| 27 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
| 29 | #include <asm/hardware/cache-l2x0.h> | ||
| 30 | |||
| 28 | #include <mach/common.h> | 31 | #include <mach/common.h> |
| 32 | #include <mach/hardware.h> | ||
| 29 | 33 | ||
| 30 | /*! | 34 | /*! |
| 31 | * @file mm.c | 35 | * @file mm.c |
| @@ -50,6 +54,16 @@ static struct map_desc mxc_io_desc[] __initdata = { | |||
| 50 | .pfn = __phys_to_pfn(AVIC_BASE_ADDR), | 54 | .pfn = __phys_to_pfn(AVIC_BASE_ADDR), |
| 51 | .length = AVIC_SIZE, | 55 | .length = AVIC_SIZE, |
| 52 | .type = MT_DEVICE_NONSHARED | 56 | .type = MT_DEVICE_NONSHARED |
| 57 | }, { | ||
| 58 | .virtual = AIPS1_BASE_ADDR_VIRT, | ||
| 59 | .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), | ||
| 60 | .length = AIPS1_SIZE, | ||
| 61 | .type = MT_DEVICE_NONSHARED | ||
| 62 | }, { | ||
| 63 | .virtual = AIPS2_BASE_ADDR_VIRT, | ||
| 64 | .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), | ||
| 65 | .length = AIPS2_SIZE, | ||
| 66 | .type = MT_DEVICE_NONSHARED | ||
| 53 | }, | 67 | }, |
| 54 | }; | 68 | }; |
| 55 | 69 | ||
| @@ -62,3 +76,24 @@ void __init mxc_map_io(void) | |||
| 62 | { | 76 | { |
| 63 | iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); | 77 | iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); |
| 64 | } | 78 | } |
| 79 | |||
| 80 | #ifdef CONFIG_CACHE_L2X0 | ||
| 81 | static int mxc_init_l2x0(void) | ||
| 82 | { | ||
| 83 | void __iomem *l2x0_base; | ||
| 84 | |||
| 85 | l2x0_base = ioremap(L2CC_BASE_ADDR, 4096); | ||
| 86 | if (IS_ERR(l2x0_base)) { | ||
| 87 | printk(KERN_ERR "remapping L2 cache area failed with %ld\n", | ||
| 88 | PTR_ERR(l2x0_base)); | ||
| 89 | return 0; | ||
| 90 | } | ||
| 91 | |||
| 92 | l2x0_init(l2x0_base, 0x00030024, 0x00000000); | ||
| 93 | |||
| 94 | return 0; | ||
| 95 | } | ||
| 96 | |||
| 97 | arch_initcall(mxc_init_l2x0); | ||
| 98 | #endif | ||
| 99 | |||
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c index f902a7c37c31..83e5e8e1276f 100644 --- a/arch/arm/mach-mx3/mx31ads.c +++ b/arch/arm/mach-mx3/mx31ads.c | |||
| @@ -22,6 +22,8 @@ | |||
| 22 | #include <linux/init.h> | 22 | #include <linux/init.h> |
| 23 | #include <linux/clk.h> | 23 | #include <linux/clk.h> |
| 24 | #include <linux/serial_8250.h> | 24 | #include <linux/serial_8250.h> |
| 25 | #include <linux/gpio.h> | ||
| 26 | #include <linux/i2c.h> | ||
| 25 | #include <linux/irq.h> | 27 | #include <linux/irq.h> |
| 26 | 28 | ||
| 27 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
| @@ -35,6 +37,12 @@ | |||
| 35 | #include <mach/imx-uart.h> | 37 | #include <mach/imx-uart.h> |
| 36 | #include <mach/iomux-mx3.h> | 38 | #include <mach/iomux-mx3.h> |
| 37 | 39 | ||
| 40 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 | ||
| 41 | #include <linux/mfd/wm8350/audio.h> | ||
| 42 | #include <linux/mfd/wm8350/core.h> | ||
| 43 | #include <linux/mfd/wm8350/pmic.h> | ||
| 44 | #endif | ||
| 45 | |||
| 38 | #include "devices.h" | 46 | #include "devices.h" |
| 39 | 47 | ||
| 40 | /*! | 48 | /*! |
| @@ -94,13 +102,16 @@ static struct imxuart_platform_data uart_pdata = { | |||
| 94 | .flags = IMXUART_HAVE_RTSCTS, | 102 | .flags = IMXUART_HAVE_RTSCTS, |
| 95 | }; | 103 | }; |
| 96 | 104 | ||
| 105 | static int uart_pins[] = { | ||
| 106 | MX31_PIN_CTS1__CTS1, | ||
| 107 | MX31_PIN_RTS1__RTS1, | ||
| 108 | MX31_PIN_TXD1__TXD1, | ||
| 109 | MX31_PIN_RXD1__RXD1 | ||
| 110 | }; | ||
| 111 | |||
| 97 | static inline void mxc_init_imx_uart(void) | 112 | static inline void mxc_init_imx_uart(void) |
| 98 | { | 113 | { |
| 99 | mxc_iomux_mode(MX31_PIN_CTS1__CTS1); | 114 | mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); |
| 100 | mxc_iomux_mode(MX31_PIN_RTS1__RTS1); | ||
| 101 | mxc_iomux_mode(MX31_PIN_TXD1__TXD1); | ||
| 102 | mxc_iomux_mode(MX31_PIN_RXD1__RXD1); | ||
| 103 | |||
| 104 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | 115 | mxc_register_device(&mxc_uart_device0, &uart_pdata); |
| 105 | } | 116 | } |
| 106 | #else /* !SERIAL_IMX */ | 117 | #else /* !SERIAL_IMX */ |
| @@ -176,7 +187,7 @@ static void __init mx31ads_init_expio(void) | |||
| 176 | /* | 187 | /* |
| 177 | * Configure INT line as GPIO input | 188 | * Configure INT line as GPIO input |
| 178 | */ | 189 | */ |
| 179 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO)); | 190 | mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio"); |
| 180 | 191 | ||
| 181 | /* disable the interrupt and clear the status */ | 192 | /* disable the interrupt and clear the status */ |
| 182 | __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); | 193 | __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); |
| @@ -191,26 +202,301 @@ static void __init mx31ads_init_expio(void) | |||
| 191 | set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); | 202 | set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); |
| 192 | } | 203 | } |
| 193 | 204 | ||
| 205 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 | ||
| 206 | /* This section defines setup for the Wolfson Microelectronics | ||
| 207 | * 1133-EV1 PMU/audio board. When other PMU boards are supported the | ||
| 208 | * regulator definitions may be shared with them, but for now they can | ||
| 209 | * only be used with this board so would generate warnings about | ||
| 210 | * unused statics and some of the configuration is specific to this | ||
| 211 | * module. | ||
| 212 | */ | ||
| 213 | |||
| 214 | /* CPU */ | ||
| 215 | static struct regulator_consumer_supply sw1a_consumers[] = { | ||
| 216 | { | ||
| 217 | .supply = "cpu_vcc", | ||
| 218 | } | ||
| 219 | }; | ||
| 220 | |||
| 221 | static struct regulator_init_data sw1a_data = { | ||
| 222 | .constraints = { | ||
| 223 | .name = "SW1A", | ||
| 224 | .min_uV = 1275000, | ||
| 225 | .max_uV = 1600000, | ||
| 226 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | | ||
| 227 | REGULATOR_CHANGE_MODE, | ||
| 228 | .valid_modes_mask = REGULATOR_MODE_NORMAL | | ||
| 229 | REGULATOR_MODE_FAST, | ||
| 230 | .state_mem = { | ||
| 231 | .uV = 1400000, | ||
| 232 | .mode = REGULATOR_MODE_NORMAL, | ||
| 233 | .enabled = 1, | ||
| 234 | }, | ||
| 235 | .initial_state = PM_SUSPEND_MEM, | ||
| 236 | .always_on = 1, | ||
| 237 | .boot_on = 1, | ||
| 238 | }, | ||
| 239 | .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers), | ||
| 240 | .consumer_supplies = sw1a_consumers, | ||
| 241 | }; | ||
| 242 | |||
| 243 | /* System IO - High */ | ||
| 244 | static struct regulator_init_data viohi_data = { | ||
| 245 | .constraints = { | ||
| 246 | .name = "VIOHO", | ||
| 247 | .min_uV = 2800000, | ||
| 248 | .max_uV = 2800000, | ||
| 249 | .state_mem = { | ||
| 250 | .uV = 2800000, | ||
| 251 | .mode = REGULATOR_MODE_NORMAL, | ||
| 252 | .enabled = 1, | ||
| 253 | }, | ||
| 254 | .initial_state = PM_SUSPEND_MEM, | ||
| 255 | .always_on = 1, | ||
| 256 | .boot_on = 1, | ||
| 257 | }, | ||
| 258 | }; | ||
| 259 | |||
| 260 | /* System IO - Low */ | ||
| 261 | static struct regulator_init_data violo_data = { | ||
| 262 | .constraints = { | ||
| 263 | .name = "VIOLO", | ||
| 264 | .min_uV = 1800000, | ||
| 265 | .max_uV = 1800000, | ||
| 266 | .state_mem = { | ||
| 267 | .uV = 1800000, | ||
| 268 | .mode = REGULATOR_MODE_NORMAL, | ||
| 269 | .enabled = 1, | ||
| 270 | }, | ||
| 271 | .initial_state = PM_SUSPEND_MEM, | ||
| 272 | .always_on = 1, | ||
| 273 | .boot_on = 1, | ||
| 274 | }, | ||
| 275 | }; | ||
| 276 | |||
| 277 | /* DDR RAM */ | ||
| 278 | static struct regulator_init_data sw2a_data = { | ||
| 279 | .constraints = { | ||
| 280 | .name = "SW2A", | ||
| 281 | .min_uV = 1800000, | ||
| 282 | .max_uV = 1800000, | ||
| 283 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 284 | .state_mem = { | ||
| 285 | .uV = 1800000, | ||
| 286 | .mode = REGULATOR_MODE_NORMAL, | ||
| 287 | .enabled = 1, | ||
| 288 | }, | ||
| 289 | .state_disk = { | ||
| 290 | .mode = REGULATOR_MODE_NORMAL, | ||
| 291 | .enabled = 0, | ||
| 292 | }, | ||
| 293 | .always_on = 1, | ||
| 294 | .boot_on = 1, | ||
| 295 | .initial_state = PM_SUSPEND_MEM, | ||
| 296 | }, | ||
| 297 | }; | ||
| 298 | |||
| 299 | static struct regulator_init_data ldo1_data = { | ||
| 300 | .constraints = { | ||
| 301 | .name = "VCAM/VMMC1/VMMC2", | ||
| 302 | .min_uV = 2800000, | ||
| 303 | .max_uV = 2800000, | ||
| 304 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 305 | .apply_uV = 1, | ||
| 306 | }, | ||
| 307 | }; | ||
| 308 | |||
| 309 | static struct regulator_consumer_supply ldo2_consumers[] = { | ||
| 310 | { | ||
| 311 | .supply = "AVDD", | ||
| 312 | }, | ||
| 313 | { | ||
| 314 | .supply = "HPVDD", | ||
| 315 | }, | ||
| 316 | }; | ||
| 317 | |||
| 318 | /* CODEC and SIM */ | ||
| 319 | static struct regulator_init_data ldo2_data = { | ||
| 320 | .constraints = { | ||
| 321 | .name = "VESIM/VSIM/AVDD", | ||
| 322 | .min_uV = 3300000, | ||
| 323 | .max_uV = 3300000, | ||
| 324 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 325 | .apply_uV = 1, | ||
| 326 | }, | ||
| 327 | .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers), | ||
| 328 | .consumer_supplies = ldo2_consumers, | ||
| 329 | }; | ||
| 330 | |||
| 331 | /* General */ | ||
| 332 | static struct regulator_init_data vdig_data = { | ||
| 333 | .constraints = { | ||
| 334 | .name = "VDIG", | ||
| 335 | .min_uV = 1500000, | ||
| 336 | .max_uV = 1500000, | ||
| 337 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 338 | .apply_uV = 1, | ||
| 339 | .always_on = 1, | ||
| 340 | .boot_on = 1, | ||
| 341 | }, | ||
| 342 | }; | ||
| 343 | |||
| 344 | /* Tranceivers */ | ||
| 345 | static struct regulator_init_data ldo4_data = { | ||
| 346 | .constraints = { | ||
| 347 | .name = "VRF1/CVDD_2.775", | ||
| 348 | .min_uV = 2500000, | ||
| 349 | .max_uV = 2500000, | ||
| 350 | .valid_modes_mask = REGULATOR_MODE_NORMAL, | ||
| 351 | .apply_uV = 1, | ||
| 352 | .always_on = 1, | ||
| 353 | .boot_on = 1, | ||
| 354 | }, | ||
| 355 | }; | ||
| 356 | |||
| 357 | static struct wm8350_led_platform_data wm8350_led_data = { | ||
| 358 | .name = "wm8350:white", | ||
| 359 | .default_trigger = "heartbeat", | ||
| 360 | .max_uA = 27899, | ||
| 361 | }; | ||
| 362 | |||
| 363 | static struct wm8350_audio_platform_data imx32ads_wm8350_setup = { | ||
| 364 | .vmid_discharge_msecs = 1000, | ||
| 365 | .drain_msecs = 30, | ||
| 366 | .cap_discharge_msecs = 700, | ||
| 367 | .vmid_charge_msecs = 700, | ||
| 368 | .vmid_s_curve = WM8350_S_CURVE_SLOW, | ||
| 369 | .dis_out4 = WM8350_DISCHARGE_SLOW, | ||
| 370 | .dis_out3 = WM8350_DISCHARGE_SLOW, | ||
| 371 | .dis_out2 = WM8350_DISCHARGE_SLOW, | ||
| 372 | .dis_out1 = WM8350_DISCHARGE_SLOW, | ||
| 373 | .vroi_out4 = WM8350_TIE_OFF_500R, | ||
| 374 | .vroi_out3 = WM8350_TIE_OFF_500R, | ||
| 375 | .vroi_out2 = WM8350_TIE_OFF_500R, | ||
| 376 | .vroi_out1 = WM8350_TIE_OFF_500R, | ||
| 377 | .vroi_enable = 0, | ||
| 378 | .codec_current_on = WM8350_CODEC_ISEL_1_0, | ||
| 379 | .codec_current_standby = WM8350_CODEC_ISEL_0_5, | ||
| 380 | .codec_current_charge = WM8350_CODEC_ISEL_1_5, | ||
| 381 | }; | ||
| 382 | |||
| 383 | static int mx31_wm8350_init(struct wm8350 *wm8350) | ||
| 384 | { | ||
| 385 | int i; | ||
| 386 | |||
| 387 | wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN, | ||
| 388 | WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW, | ||
| 389 | WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF, | ||
| 390 | WM8350_GPIO_DEBOUNCE_ON); | ||
| 391 | |||
| 392 | wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN, | ||
| 393 | WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH, | ||
| 394 | WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, | ||
| 395 | WM8350_GPIO_DEBOUNCE_ON); | ||
| 396 | |||
| 397 | wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN, | ||
| 398 | WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH, | ||
| 399 | WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, | ||
| 400 | WM8350_GPIO_DEBOUNCE_OFF); | ||
| 401 | |||
| 402 | wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN, | ||
| 403 | WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH, | ||
| 404 | WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF, | ||
| 405 | WM8350_GPIO_DEBOUNCE_OFF); | ||
| 406 | |||
| 407 | wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT, | ||
| 408 | WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH, | ||
| 409 | WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, | ||
| 410 | WM8350_GPIO_DEBOUNCE_OFF); | ||
| 411 | |||
| 412 | wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT, | ||
| 413 | WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW, | ||
| 414 | WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, | ||
| 415 | WM8350_GPIO_DEBOUNCE_OFF); | ||
| 416 | |||
| 417 | wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT, | ||
| 418 | WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW, | ||
| 419 | WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF, | ||
| 420 | WM8350_GPIO_DEBOUNCE_OFF); | ||
| 421 | |||
| 422 | /* Fix up for our own supplies. */ | ||
| 423 | for (i = 0; i < ARRAY_SIZE(ldo2_consumers); i++) | ||
| 424 | ldo2_consumers[i].dev = wm8350->dev; | ||
| 425 | |||
| 426 | wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data); | ||
| 427 | wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data); | ||
| 428 | wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data); | ||
| 429 | wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data); | ||
| 430 | wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data); | ||
| 431 | wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data); | ||
| 432 | wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data); | ||
| 433 | wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data); | ||
| 434 | |||
| 435 | /* LEDs */ | ||
| 436 | wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1, | ||
| 437 | WM8350_DC5_ERRACT_SHUTDOWN_CONV); | ||
| 438 | wm8350_isink_set_flash(wm8350, WM8350_ISINK_A, | ||
| 439 | WM8350_ISINK_FLASH_DISABLE, | ||
| 440 | WM8350_ISINK_FLASH_TRIG_BIT, | ||
| 441 | WM8350_ISINK_FLASH_DUR_32MS, | ||
| 442 | WM8350_ISINK_FLASH_ON_INSTANT, | ||
| 443 | WM8350_ISINK_FLASH_OFF_INSTANT, | ||
| 444 | WM8350_ISINK_FLASH_MODE_EN); | ||
| 445 | wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5, | ||
| 446 | WM8350_ISINK_MODE_BOOST, | ||
| 447 | WM8350_ISINK_ILIM_NORMAL, | ||
| 448 | WM8350_DC5_RMP_20V, | ||
| 449 | WM8350_DC5_FBSRC_ISINKA); | ||
| 450 | wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A, | ||
| 451 | &wm8350_led_data); | ||
| 452 | |||
| 453 | wm8350->codec.platform_data = &imx32ads_wm8350_setup; | ||
| 454 | |||
| 455 | return 0; | ||
| 456 | } | ||
| 457 | |||
| 458 | static struct wm8350_platform_data __initdata mx31_wm8350_pdata = { | ||
| 459 | .init = mx31_wm8350_init, | ||
| 460 | }; | ||
| 461 | #endif | ||
| 462 | |||
| 463 | #if defined(CONFIG_I2C_IMX) || defined(CONFIG_I2C_IMX_MODULE) | ||
| 464 | static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = { | ||
| 465 | #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 | ||
| 466 | { | ||
| 467 | I2C_BOARD_INFO("wm8350", 0x1a), | ||
| 468 | .platform_data = &mx31_wm8350_pdata, | ||
| 469 | .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), | ||
| 470 | }, | ||
| 471 | #endif | ||
| 472 | }; | ||
| 473 | |||
| 474 | static void mxc_init_i2c(void) | ||
| 475 | { | ||
| 476 | i2c_register_board_info(1, mx31ads_i2c1_devices, | ||
| 477 | ARRAY_SIZE(mx31ads_i2c1_devices)); | ||
| 478 | |||
| 479 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1)); | ||
| 480 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1)); | ||
| 481 | |||
| 482 | mxc_register_device(&mxc_i2c_device1, NULL); | ||
| 483 | } | ||
| 484 | #else | ||
| 485 | static void mxc_init_i2c(void) | ||
| 486 | { | ||
| 487 | } | ||
| 488 | #endif | ||
| 489 | |||
| 194 | /*! | 490 | /*! |
| 195 | * This structure defines static mappings for the i.MX31ADS board. | 491 | * This structure defines static mappings for the i.MX31ADS board. |
| 196 | */ | 492 | */ |
| 197 | static struct map_desc mx31ads_io_desc[] __initdata = { | 493 | static struct map_desc mx31ads_io_desc[] __initdata = { |
| 198 | { | 494 | { |
| 199 | .virtual = AIPS1_BASE_ADDR_VIRT, | ||
| 200 | .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), | ||
| 201 | .length = AIPS1_SIZE, | ||
| 202 | .type = MT_DEVICE_NONSHARED | ||
| 203 | }, { | ||
| 204 | .virtual = SPBA0_BASE_ADDR_VIRT, | 495 | .virtual = SPBA0_BASE_ADDR_VIRT, |
| 205 | .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), | 496 | .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), |
| 206 | .length = SPBA0_SIZE, | 497 | .length = SPBA0_SIZE, |
| 207 | .type = MT_DEVICE_NONSHARED | 498 | .type = MT_DEVICE_NONSHARED |
| 208 | }, { | 499 | }, { |
| 209 | .virtual = AIPS2_BASE_ADDR_VIRT, | ||
| 210 | .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), | ||
| 211 | .length = AIPS2_SIZE, | ||
| 212 | .type = MT_DEVICE_NONSHARED | ||
| 213 | }, { | ||
| 214 | .virtual = CS4_BASE_ADDR_VIRT, | 500 | .virtual = CS4_BASE_ADDR_VIRT, |
| 215 | .pfn = __phys_to_pfn(CS4_BASE_ADDR), | 501 | .pfn = __phys_to_pfn(CS4_BASE_ADDR), |
| 216 | .length = CS4_SIZE / 2, | 502 | .length = CS4_SIZE / 2, |
| @@ -221,13 +507,13 @@ static struct map_desc mx31ads_io_desc[] __initdata = { | |||
| 221 | /*! | 507 | /*! |
| 222 | * Set up static virtual mappings. | 508 | * Set up static virtual mappings. |
| 223 | */ | 509 | */ |
| 224 | void __init mx31ads_map_io(void) | 510 | static void __init mx31ads_map_io(void) |
| 225 | { | 511 | { |
| 226 | mxc_map_io(); | 512 | mxc_map_io(); |
| 227 | iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc)); | 513 | iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc)); |
| 228 | } | 514 | } |
| 229 | 515 | ||
| 230 | void __init mx31ads_init_irq(void) | 516 | static void __init mx31ads_init_irq(void) |
| 231 | { | 517 | { |
| 232 | mxc_init_irq(); | 518 | mxc_init_irq(); |
| 233 | mx31ads_init_expio(); | 519 | mx31ads_init_expio(); |
| @@ -240,15 +526,15 @@ static void __init mxc_board_init(void) | |||
| 240 | { | 526 | { |
| 241 | mxc_init_extuart(); | 527 | mxc_init_extuart(); |
| 242 | mxc_init_imx_uart(); | 528 | mxc_init_imx_uart(); |
| 529 | mxc_init_i2c(); | ||
| 243 | } | 530 | } |
| 244 | 531 | ||
| 245 | static void __init mx31ads_timer_init(void) | 532 | static void __init mx31ads_timer_init(void) |
| 246 | { | 533 | { |
| 247 | mxc_clocks_init(26000000); | 534 | mx31_clocks_init(26000000); |
| 248 | mxc_timer_init("ipg_clk.0"); | ||
| 249 | } | 535 | } |
| 250 | 536 | ||
| 251 | struct sys_timer mx31ads_timer = { | 537 | static struct sys_timer mx31ads_timer = { |
| 252 | .init = mx31ads_timer_init, | 538 | .init = mx31ads_timer_init, |
| 253 | }; | 539 | }; |
| 254 | 540 | ||
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c index c43440070143..894d98cd9941 100644 --- a/arch/arm/mach-mx3/mx31lite.c +++ b/arch/arm/mach-mx3/mx31lite.c | |||
| @@ -42,21 +42,11 @@ | |||
| 42 | */ | 42 | */ |
| 43 | static struct map_desc mx31lite_io_desc[] __initdata = { | 43 | static struct map_desc mx31lite_io_desc[] __initdata = { |
| 44 | { | 44 | { |
| 45 | .virtual = AIPS1_BASE_ADDR_VIRT, | ||
| 46 | .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), | ||
| 47 | .length = AIPS1_SIZE, | ||
| 48 | .type = MT_DEVICE_NONSHARED | ||
| 49 | }, { | ||
| 50 | .virtual = SPBA0_BASE_ADDR_VIRT, | 45 | .virtual = SPBA0_BASE_ADDR_VIRT, |
| 51 | .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), | 46 | .pfn = __phys_to_pfn(SPBA0_BASE_ADDR), |
| 52 | .length = SPBA0_SIZE, | 47 | .length = SPBA0_SIZE, |
| 53 | .type = MT_DEVICE_NONSHARED | 48 | .type = MT_DEVICE_NONSHARED |
| 54 | }, { | 49 | }, { |
| 55 | .virtual = AIPS2_BASE_ADDR_VIRT, | ||
| 56 | .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), | ||
| 57 | .length = AIPS2_SIZE, | ||
| 58 | .type = MT_DEVICE_NONSHARED | ||
| 59 | }, { | ||
| 60 | .virtual = CS4_BASE_ADDR_VIRT, | 50 | .virtual = CS4_BASE_ADDR_VIRT, |
| 61 | .pfn = __phys_to_pfn(CS4_BASE_ADDR), | 51 | .pfn = __phys_to_pfn(CS4_BASE_ADDR), |
| 62 | .length = CS4_SIZE, | 52 | .length = CS4_SIZE, |
| @@ -82,8 +72,7 @@ static void __init mxc_board_init(void) | |||
| 82 | 72 | ||
| 83 | static void __init mx31lite_timer_init(void) | 73 | static void __init mx31lite_timer_init(void) |
| 84 | { | 74 | { |
| 85 | mxc_clocks_init(26000000); | 75 | mx31_clocks_init(26000000); |
| 86 | mxc_timer_init("ipg_clk.0"); | ||
| 87 | } | 76 | } |
| 88 | 77 | ||
| 89 | struct sys_timer mx31lite_timer = { | 78 | struct sys_timer mx31lite_timer = { |
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c new file mode 100644 index 000000000000..d080b4add79c --- /dev/null +++ b/arch/arm/mach-mx3/mx31moboard-devboard.c | |||
| @@ -0,0 +1,48 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/types.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | |||
| 22 | #include <linux/platform_device.h> | ||
| 23 | |||
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/common.h> | ||
| 26 | #include <mach/imx-uart.h> | ||
| 27 | #include <mach/iomux-mx3.h> | ||
| 28 | |||
| 29 | #include "devices.h" | ||
| 30 | |||
| 31 | static struct imxuart_platform_data uart_pdata = { | ||
| 32 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 33 | }; | ||
| 34 | |||
| 35 | static int mxc_uart1_pins[] = { | ||
| 36 | MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2, | ||
| 37 | MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2, | ||
| 38 | }; | ||
| 39 | |||
| 40 | /* | ||
| 41 | * system init for baseboard usage. Will be called by mx31moboard init. | ||
| 42 | */ | ||
| 43 | void __init mx31moboard_devboard_init(void) | ||
| 44 | { | ||
| 45 | printk(KERN_INFO "Initializing mx31devboard peripherals\n"); | ||
| 46 | mxc_iomux_setup_multiple_pins(mxc_uart1_pins, ARRAY_SIZE(mxc_uart1_pins), "uart1"); | ||
| 47 | mxc_register_device(&mxc_uart_device1, &uart_pdata); | ||
| 48 | } | ||
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c new file mode 100644 index 000000000000..9ef9566823fb --- /dev/null +++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c | |||
| @@ -0,0 +1,37 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/types.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | |||
| 22 | #include <linux/platform_device.h> | ||
| 23 | |||
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/common.h> | ||
| 26 | #include <mach/imx-uart.h> | ||
| 27 | #include <mach/iomux-mx3.h> | ||
| 28 | |||
| 29 | #include "devices.h" | ||
| 30 | |||
| 31 | /* | ||
| 32 | * system init for baseboard usage. Will be called by mx31moboard init. | ||
| 33 | */ | ||
| 34 | void __init mx31moboard_marxbot_init(void) | ||
| 35 | { | ||
| 36 | printk(KERN_INFO "Initializing mx31marxbot peripherals\n"); | ||
| 37 | } | ||
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c index c29098af7394..34c2a1b99d4f 100644 --- a/arch/arm/mach-mx3/mx31moboard.c +++ b/arch/arm/mach-mx3/mx31moboard.c | |||
| @@ -32,6 +32,7 @@ | |||
| 32 | #include <mach/common.h> | 32 | #include <mach/common.h> |
| 33 | #include <mach/imx-uart.h> | 33 | #include <mach/imx-uart.h> |
| 34 | #include <mach/iomux-mx3.h> | 34 | #include <mach/iomux-mx3.h> |
| 35 | #include <mach/board-mx31moboard.h> | ||
| 35 | 36 | ||
| 36 | #include "devices.h" | 37 | #include "devices.h" |
| 37 | 38 | ||
| @@ -63,6 +64,18 @@ static struct platform_device *devices[] __initdata = { | |||
| 63 | &mx31moboard_flash, | 64 | &mx31moboard_flash, |
| 64 | }; | 65 | }; |
| 65 | 66 | ||
| 67 | static int mxc_uart0_pins[] = { | ||
| 68 | MX31_PIN_CTS1__CTS1, MX31_PIN_RTS1__RTS1, | ||
| 69 | MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1, | ||
| 70 | }; | ||
| 71 | static int mxc_uart4_pins[] = { | ||
| 72 | MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5, | ||
| 73 | MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5, | ||
| 74 | }; | ||
| 75 | |||
| 76 | static int mx31moboard_baseboard; | ||
| 77 | core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444); | ||
| 78 | |||
| 66 | /* | 79 | /* |
| 67 | * Board specific initialization. | 80 | * Board specific initialization. |
| 68 | */ | 81 | */ |
| @@ -70,58 +83,29 @@ static void __init mxc_board_init(void) | |||
| 70 | { | 83 | { |
| 71 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 84 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 72 | 85 | ||
| 73 | mxc_iomux_mode(MX31_PIN_CTS1__CTS1); | 86 | mxc_iomux_setup_multiple_pins(mxc_uart0_pins, ARRAY_SIZE(mxc_uart0_pins), "uart0"); |
| 74 | mxc_iomux_mode(MX31_PIN_RTS1__RTS1); | ||
| 75 | mxc_iomux_mode(MX31_PIN_TXD1__TXD1); | ||
| 76 | mxc_iomux_mode(MX31_PIN_RXD1__RXD1); | ||
| 77 | |||
| 78 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | 87 | mxc_register_device(&mxc_uart_device0, &uart_pdata); |
| 79 | 88 | ||
| 80 | mxc_iomux_mode(MX31_PIN_CTS2__CTS2); | 89 | mxc_iomux_setup_multiple_pins(mxc_uart4_pins, ARRAY_SIZE(mxc_uart4_pins), "uart4"); |
| 81 | mxc_iomux_mode(MX31_PIN_RTS2__RTS2); | ||
| 82 | mxc_iomux_mode(MX31_PIN_TXD2__TXD2); | ||
| 83 | mxc_iomux_mode(MX31_PIN_RXD2__RXD2); | ||
| 84 | |||
| 85 | mxc_register_device(&mxc_uart_device1, &uart_pdata); | ||
| 86 | |||
| 87 | mxc_iomux_mode(MX31_PIN_PC_RST__CTS5); | ||
| 88 | mxc_iomux_mode(MX31_PIN_PC_VS2__RTS5); | ||
| 89 | mxc_iomux_mode(MX31_PIN_PC_BVD2__TXD5); | ||
| 90 | mxc_iomux_mode(MX31_PIN_PC_BVD1__RXD5); | ||
| 91 | |||
| 92 | mxc_register_device(&mxc_uart_device4, &uart_pdata); | 90 | mxc_register_device(&mxc_uart_device4, &uart_pdata); |
| 93 | } | ||
| 94 | 91 | ||
| 95 | /* | 92 | switch (mx31moboard_baseboard) { |
| 96 | * This structure defines static mappings for the mx31moboard. | 93 | case MX31NOBOARD: |
| 97 | */ | 94 | break; |
| 98 | static struct map_desc mx31moboard_io_desc[] __initdata = { | 95 | case MX31DEVBOARD: |
| 99 | { | 96 | mx31moboard_devboard_init(); |
| 100 | .virtual = AIPS1_BASE_ADDR_VIRT, | 97 | break; |
| 101 | .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), | 98 | case MX31MARXBOT: |
| 102 | .length = AIPS1_SIZE, | 99 | mx31moboard_marxbot_init(); |
| 103 | .type = MT_DEVICE_NONSHARED | 100 | break; |
| 104 | }, { | 101 | default: |
| 105 | .virtual = AIPS2_BASE_ADDR_VIRT, | 102 | printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n", mx31moboard_baseboard); |
| 106 | .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), | 103 | } |
| 107 | .length = AIPS2_SIZE, | ||
| 108 | .type = MT_DEVICE_NONSHARED | ||
| 109 | }, | ||
| 110 | }; | ||
| 111 | |||
| 112 | /* | ||
| 113 | * Set up static virtual mappings. | ||
| 114 | */ | ||
| 115 | void __init mx31moboard_map_io(void) | ||
| 116 | { | ||
| 117 | mxc_map_io(); | ||
| 118 | iotable_init(mx31moboard_io_desc, ARRAY_SIZE(mx31moboard_io_desc)); | ||
| 119 | } | 104 | } |
| 120 | 105 | ||
| 121 | static void __init mx31moboard_timer_init(void) | 106 | static void __init mx31moboard_timer_init(void) |
| 122 | { | 107 | { |
| 123 | mxc_clocks_init(26000000); | 108 | mx31_clocks_init(26000000); |
| 124 | mxc_timer_init("ipg_clk.0"); | ||
| 125 | } | 109 | } |
| 126 | 110 | ||
| 127 | struct sys_timer mx31moboard_timer = { | 111 | struct sys_timer mx31moboard_timer = { |
| @@ -133,7 +117,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") | |||
| 133 | .phys_io = AIPS1_BASE_ADDR, | 117 | .phys_io = AIPS1_BASE_ADDR, |
| 134 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, | 118 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, |
| 135 | .boot_params = PHYS_OFFSET + 0x100, | 119 | .boot_params = PHYS_OFFSET + 0x100, |
| 136 | .map_io = mx31moboard_map_io, | 120 | .map_io = mxc_map_io, |
| 137 | .init_irq = mxc_init_irq, | 121 | .init_irq = mxc_init_irq, |
| 138 | .init_machine = mxc_board_init, | 122 | .init_machine = mxc_board_init, |
| 139 | .timer = &mx31moboard_timer, | 123 | .timer = &mx31moboard_timer, |
diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mx31pdk.c index d464d068a4a6..bc63f1785691 100644 --- a/arch/arm/mach-mx3/mx31pdk.c +++ b/arch/arm/mach-mx3/mx31pdk.c | |||
| @@ -45,40 +45,17 @@ static struct imxuart_platform_data uart_pdata = { | |||
| 45 | .flags = IMXUART_HAVE_RTSCTS, | 45 | .flags = IMXUART_HAVE_RTSCTS, |
| 46 | }; | 46 | }; |
| 47 | 47 | ||
| 48 | static inline void mxc_init_imx_uart(void) | 48 | static int uart_pins[] = { |
| 49 | { | 49 | MX31_PIN_CTS1__CTS1, |
| 50 | mxc_iomux_mode(MX31_PIN_CTS1__CTS1); | 50 | MX31_PIN_RTS1__RTS1, |
| 51 | mxc_iomux_mode(MX31_PIN_RTS1__RTS1); | 51 | MX31_PIN_TXD1__TXD1, |
| 52 | mxc_iomux_mode(MX31_PIN_TXD1__TXD1); | 52 | MX31_PIN_RXD1__RXD1 |
| 53 | mxc_iomux_mode(MX31_PIN_RXD1__RXD1); | ||
| 54 | |||
| 55 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | ||
| 56 | } | ||
| 57 | |||
| 58 | /*! | ||
| 59 | * This structure defines static mappings for the i.MX31PDK board. | ||
| 60 | */ | ||
| 61 | static struct map_desc mx31pdk_io_desc[] __initdata = { | ||
| 62 | { | ||
| 63 | .virtual = AIPS1_BASE_ADDR_VIRT, | ||
| 64 | .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), | ||
| 65 | .length = AIPS1_SIZE, | ||
| 66 | .type = MT_DEVICE_NONSHARED | ||
| 67 | }, { | ||
| 68 | .virtual = AIPS2_BASE_ADDR_VIRT, | ||
| 69 | .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), | ||
| 70 | .length = AIPS2_SIZE, | ||
| 71 | .type = MT_DEVICE_NONSHARED | ||
| 72 | }, | ||
| 73 | }; | 53 | }; |
| 74 | 54 | ||
| 75 | /*! | 55 | static inline void mxc_init_imx_uart(void) |
| 76 | * Set up static virtual mappings. | ||
| 77 | */ | ||
| 78 | static void __init mx31pdk_map_io(void) | ||
| 79 | { | 56 | { |
| 80 | mxc_map_io(); | 57 | mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0"); |
| 81 | iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc)); | 58 | mxc_register_device(&mxc_uart_device0, &uart_pdata); |
| 82 | } | 59 | } |
| 83 | 60 | ||
| 84 | /*! | 61 | /*! |
| @@ -91,8 +68,7 @@ static void __init mxc_board_init(void) | |||
| 91 | 68 | ||
| 92 | static void __init mx31pdk_timer_init(void) | 69 | static void __init mx31pdk_timer_init(void) |
| 93 | { | 70 | { |
| 94 | mxc_clocks_init(26000000); | 71 | mx31_clocks_init(26000000); |
| 95 | mxc_timer_init("ipg_clk.0"); | ||
| 96 | } | 72 | } |
| 97 | 73 | ||
| 98 | static struct sys_timer mx31pdk_timer = { | 74 | static struct sys_timer mx31pdk_timer = { |
| @@ -108,7 +84,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") | |||
| 108 | .phys_io = AIPS1_BASE_ADDR, | 84 | .phys_io = AIPS1_BASE_ADDR, |
| 109 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, | 85 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, |
| 110 | .boot_params = PHYS_OFFSET + 0x100, | 86 | .boot_params = PHYS_OFFSET + 0x100, |
| 111 | .map_io = mx31pdk_map_io, | 87 | .map_io = mxc_map_io, |
| 112 | .init_irq = mxc_init_irq, | 88 | .init_irq = mxc_init_irq, |
| 113 | .init_machine = mxc_board_init, | 89 | .init_machine = mxc_board_init, |
| 114 | .timer = &mx31pdk_timer, | 90 | .timer = &mx31pdk_timer, |
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c index 8cea82587222..5fce022114de 100644 --- a/arch/arm/mach-mx3/pcm037.c +++ b/arch/arm/mach-mx3/pcm037.c | |||
| @@ -26,6 +26,8 @@ | |||
| 26 | #include <linux/gpio.h> | 26 | #include <linux/gpio.h> |
| 27 | #include <linux/smc911x.h> | 27 | #include <linux/smc911x.h> |
| 28 | #include <linux/interrupt.h> | 28 | #include <linux/interrupt.h> |
| 29 | #include <linux/i2c.h> | ||
| 30 | #include <linux/i2c/at24.h> | ||
| 29 | 31 | ||
| 30 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
| 31 | #include <asm/mach-types.h> | 33 | #include <asm/mach-types.h> |
| @@ -37,6 +39,10 @@ | |||
| 37 | #include <mach/iomux-mx3.h> | 39 | #include <mach/iomux-mx3.h> |
| 38 | #include <mach/board-pcm037.h> | 40 | #include <mach/board-pcm037.h> |
| 39 | #include <mach/mxc_nand.h> | 41 | #include <mach/mxc_nand.h> |
| 42 | #include <mach/mmc.h> | ||
| 43 | #ifdef CONFIG_I2C_IMX | ||
| 44 | #include <mach/i2c.h> | ||
| 45 | #endif | ||
| 40 | 46 | ||
| 41 | #include "devices.h" | 47 | #include "devices.h" |
| 42 | 48 | ||
| @@ -117,12 +123,90 @@ static struct mxc_nand_platform_data pcm037_nand_board_info = { | |||
| 117 | .hw_ecc = 1, | 123 | .hw_ecc = 1, |
| 118 | }; | 124 | }; |
| 119 | 125 | ||
| 126 | #ifdef CONFIG_I2C_IMX | ||
| 127 | static int i2c_1_pins[] = { | ||
| 128 | MX31_PIN_CSPI2_MOSI__SCL, | ||
| 129 | MX31_PIN_CSPI2_MISO__SDA, | ||
| 130 | }; | ||
| 131 | |||
| 132 | static int pcm037_i2c_1_init(struct device *dev) | ||
| 133 | { | ||
| 134 | return mxc_iomux_setup_multiple_pins(i2c_1_pins, ARRAY_SIZE(i2c_1_pins), | ||
| 135 | "i2c-1"); | ||
| 136 | } | ||
| 137 | |||
| 138 | static void pcm037_i2c_1_exit(struct device *dev) | ||
| 139 | { | ||
| 140 | mxc_iomux_release_multiple_pins(i2c_1_pins, ARRAY_SIZE(i2c_1_pins)); | ||
| 141 | } | ||
| 142 | |||
| 143 | static struct imxi2c_platform_data pcm037_i2c_1_data = { | ||
| 144 | .bitrate = 100000, | ||
| 145 | .init = pcm037_i2c_1_init, | ||
| 146 | .exit = pcm037_i2c_1_exit, | ||
| 147 | }; | ||
| 148 | |||
| 149 | static struct at24_platform_data board_eeprom = { | ||
| 150 | .byte_len = 4096, | ||
| 151 | .page_size = 32, | ||
| 152 | .flags = AT24_FLAG_ADDR16, | ||
| 153 | }; | ||
| 154 | |||
| 155 | static struct i2c_board_info pcm037_i2c_devices[] = { | ||
| 156 | { | ||
| 157 | I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ | ||
| 158 | .platform_data = &board_eeprom, | ||
| 159 | }, { | ||
| 160 | I2C_BOARD_INFO("rtc-pcf8563", 0x51), | ||
| 161 | .type = "pcf8563", | ||
| 162 | } | ||
| 163 | }; | ||
| 164 | #endif | ||
| 165 | |||
| 166 | static int sdhc1_pins[] = { | ||
| 167 | MX31_PIN_SD1_DATA3__SD1_DATA3, | ||
| 168 | MX31_PIN_SD1_DATA2__SD1_DATA2, | ||
| 169 | MX31_PIN_SD1_DATA1__SD1_DATA1, | ||
| 170 | MX31_PIN_SD1_DATA0__SD1_DATA0, | ||
| 171 | MX31_PIN_SD1_CLK__SD1_CLK, | ||
| 172 | MX31_PIN_SD1_CMD__SD1_CMD, | ||
| 173 | }; | ||
| 174 | |||
| 175 | static int pcm970_sdhc1_init(struct device *dev, irq_handler_t h, void *data) | ||
| 176 | { | ||
| 177 | return mxc_iomux_setup_multiple_pins(sdhc1_pins, ARRAY_SIZE(sdhc1_pins), | ||
| 178 | "sdhc-1"); | ||
| 179 | } | ||
| 180 | |||
| 181 | static void pcm970_sdhc1_exit(struct device *dev, void *data) | ||
| 182 | { | ||
| 183 | mxc_iomux_release_multiple_pins(sdhc1_pins, ARRAY_SIZE(sdhc1_pins)); | ||
| 184 | } | ||
| 185 | |||
| 186 | /* No card and rw detection at the moment */ | ||
| 187 | static struct imxmmc_platform_data sdhc_pdata = { | ||
| 188 | .init = pcm970_sdhc1_init, | ||
| 189 | .exit = pcm970_sdhc1_exit, | ||
| 190 | }; | ||
| 191 | |||
| 120 | static struct platform_device *devices[] __initdata = { | 192 | static struct platform_device *devices[] __initdata = { |
| 121 | &pcm037_flash, | 193 | &pcm037_flash, |
| 122 | &pcm037_eth, | 194 | &pcm037_eth, |
| 123 | &pcm037_sram_device, | 195 | &pcm037_sram_device, |
| 124 | }; | 196 | }; |
| 125 | 197 | ||
| 198 | static int uart0_pins[] = { | ||
| 199 | MX31_PIN_CTS1__CTS1, | ||
| 200 | MX31_PIN_RTS1__RTS1, | ||
| 201 | MX31_PIN_TXD1__TXD1, | ||
| 202 | MX31_PIN_RXD1__RXD1 | ||
| 203 | }; | ||
| 204 | |||
| 205 | static int uart2_pins[] = { | ||
| 206 | MX31_PIN_CSPI3_MOSI__RXD3, | ||
| 207 | MX31_PIN_CSPI3_MISO__TXD3 | ||
| 208 | }; | ||
| 209 | |||
| 126 | /* | 210 | /* |
| 127 | * Board specific initialization. | 211 | * Board specific initialization. |
| 128 | */ | 212 | */ |
| @@ -130,59 +214,33 @@ static void __init mxc_board_init(void) | |||
| 130 | { | 214 | { |
| 131 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 215 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 132 | 216 | ||
| 133 | mxc_iomux_mode(MX31_PIN_CTS1__CTS1); | 217 | mxc_iomux_setup_multiple_pins(uart0_pins, ARRAY_SIZE(uart0_pins), "uart-0"); |
| 134 | mxc_iomux_mode(MX31_PIN_RTS1__RTS1); | ||
| 135 | mxc_iomux_mode(MX31_PIN_TXD1__TXD1); | ||
| 136 | mxc_iomux_mode(MX31_PIN_RXD1__RXD1); | ||
| 137 | |||
| 138 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | 218 | mxc_register_device(&mxc_uart_device0, &uart_pdata); |
| 139 | 219 | ||
| 140 | mxc_iomux_mode(MX31_PIN_CSPI3_MOSI__RXD3); | 220 | mxc_iomux_setup_multiple_pins(uart2_pins, ARRAY_SIZE(uart2_pins), "uart-2"); |
| 141 | mxc_iomux_mode(MX31_PIN_CSPI3_MISO__TXD3); | ||
| 142 | |||
| 143 | mxc_register_device(&mxc_uart_device2, &uart_pdata); | 221 | mxc_register_device(&mxc_uart_device2, &uart_pdata); |
| 144 | 222 | ||
| 145 | mxc_iomux_mode(MX31_PIN_BATT_LINE__OWIRE); | 223 | mxc_iomux_setup_pin(MX31_PIN_BATT_LINE__OWIRE, "batt-0wire"); |
| 146 | mxc_register_device(&mxc_w1_master_device, NULL); | 224 | mxc_register_device(&mxc_w1_master_device, NULL); |
| 147 | 225 | ||
| 148 | /* SMSC9215 IRQ pin */ | 226 | /* SMSC9215 IRQ pin */ |
| 149 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)); | 227 | if (!mxc_iomux_setup_pin(IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO), |
| 150 | if (!gpio_request(MX31_PIN_GPIO3_1, "pcm037-eth")) | 228 | "pcm037-eth")) |
| 151 | gpio_direction_input(MX31_PIN_GPIO3_1); | 229 | gpio_direction_input(MX31_PIN_GPIO3_1); |
| 152 | 230 | ||
| 153 | mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); | 231 | #ifdef CONFIG_I2C_IMX |
| 154 | } | 232 | i2c_register_board_info(1, pcm037_i2c_devices, |
| 233 | ARRAY_SIZE(pcm037_i2c_devices)); | ||
| 155 | 234 | ||
| 156 | /* | 235 | mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data); |
| 157 | * This structure defines static mappings for the pcm037 board. | 236 | #endif |
| 158 | */ | 237 | mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info); |
| 159 | static struct map_desc pcm037_io_desc[] __initdata = { | 238 | mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); |
| 160 | { | ||
| 161 | .virtual = AIPS1_BASE_ADDR_VIRT, | ||
| 162 | .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), | ||
| 163 | .length = AIPS1_SIZE, | ||
| 164 | .type = MT_DEVICE_NONSHARED | ||
| 165 | }, { | ||
| 166 | .virtual = AIPS2_BASE_ADDR_VIRT, | ||
| 167 | .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), | ||
| 168 | .length = AIPS2_SIZE, | ||
| 169 | .type = MT_DEVICE_NONSHARED | ||
| 170 | }, | ||
| 171 | }; | ||
| 172 | |||
| 173 | /* | ||
| 174 | * Set up static virtual mappings. | ||
| 175 | */ | ||
| 176 | void __init pcm037_map_io(void) | ||
| 177 | { | ||
| 178 | mxc_map_io(); | ||
| 179 | iotable_init(pcm037_io_desc, ARRAY_SIZE(pcm037_io_desc)); | ||
| 180 | } | 239 | } |
| 181 | 240 | ||
| 182 | static void __init pcm037_timer_init(void) | 241 | static void __init pcm037_timer_init(void) |
| 183 | { | 242 | { |
| 184 | mxc_clocks_init(26000000); | 243 | mx31_clocks_init(26000000); |
| 185 | mxc_timer_init("ipg_clk.0"); | ||
| 186 | } | 244 | } |
| 187 | 245 | ||
| 188 | struct sys_timer pcm037_timer = { | 246 | struct sys_timer pcm037_timer = { |
| @@ -194,7 +252,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037") | |||
| 194 | .phys_io = AIPS1_BASE_ADDR, | 252 | .phys_io = AIPS1_BASE_ADDR, |
| 195 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, | 253 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, |
| 196 | .boot_params = PHYS_OFFSET + 0x100, | 254 | .boot_params = PHYS_OFFSET + 0x100, |
| 197 | .map_io = pcm037_map_io, | 255 | .map_io = mxc_map_io, |
| 198 | .init_irq = mxc_init_irq, | 256 | .init_irq = mxc_init_irq, |
| 199 | .init_machine = mxc_board_init, | 257 | .init_machine = mxc_board_init, |
| 200 | .timer = &pcm037_timer, | 258 | .timer = &pcm037_timer, |
diff --git a/arch/arm/mach-mx3/qong.c b/arch/arm/mach-mx3/qong.c new file mode 100644 index 000000000000..6c4283cec6f4 --- /dev/null +++ b/arch/arm/mach-mx3/qong.c | |||
| @@ -0,0 +1,312 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/types.h> | ||
| 20 | #include <linux/init.h> | ||
| 21 | #include <linux/kernel.h> | ||
| 22 | #include <linux/memory.h> | ||
| 23 | #include <linux/platform_device.h> | ||
| 24 | #include <linux/mtd/physmap.h> | ||
| 25 | #include <linux/mtd/nand.h> | ||
| 26 | #include <linux/gpio.h> | ||
| 27 | |||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <mach/irqs.h> | ||
| 30 | #include <asm/mach-types.h> | ||
| 31 | #include <asm/mach/arch.h> | ||
| 32 | #include <asm/mach/time.h> | ||
| 33 | #include <asm/mach/map.h> | ||
| 34 | #include <mach/common.h> | ||
| 35 | #include <asm/page.h> | ||
| 36 | #include <asm/setup.h> | ||
| 37 | #include <mach/board-qong.h> | ||
| 38 | #include <mach/imx-uart.h> | ||
| 39 | #include <mach/iomux-mx3.h> | ||
| 40 | #include "devices.h" | ||
| 41 | |||
| 42 | /* FPGA defines */ | ||
| 43 | #define QONG_FPGA_VERSION(major, minor, rev) \ | ||
| 44 | (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF)) | ||
| 45 | |||
| 46 | #define QONG_FPGA_BASEADDR CS1_BASE_ADDR | ||
| 47 | #define QONG_FPGA_PERIPH_SIZE (1 << 24) | ||
| 48 | |||
| 49 | #define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR | ||
| 50 | #define QONG_FPGA_CTRL_SIZE 0x10 | ||
| 51 | /* FPGA control registers */ | ||
| 52 | #define QONG_FPGA_CTRL_VERSION 0x00 | ||
| 53 | |||
| 54 | #define QONG_DNET_ID 1 | ||
| 55 | #define QONG_DNET_BASEADDR \ | ||
| 56 | (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE) | ||
| 57 | #define QONG_DNET_SIZE 0x00001000 | ||
| 58 | |||
| 59 | #define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1) | ||
| 60 | |||
| 61 | /* | ||
| 62 | * This file contains the board-specific initialization routines. | ||
| 63 | */ | ||
| 64 | |||
| 65 | static struct imxuart_platform_data uart_pdata = { | ||
| 66 | .flags = IMXUART_HAVE_RTSCTS, | ||
| 67 | }; | ||
| 68 | |||
| 69 | static int uart_pins[] = { | ||
| 70 | MX31_PIN_CTS1__CTS1, | ||
| 71 | MX31_PIN_RTS1__RTS1, | ||
| 72 | MX31_PIN_TXD1__TXD1, | ||
| 73 | MX31_PIN_RXD1__RXD1 | ||
| 74 | }; | ||
| 75 | |||
| 76 | static inline void mxc_init_imx_uart(void) | ||
| 77 | { | ||
| 78 | mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), | ||
| 79 | "uart-0"); | ||
| 80 | mxc_register_device(&mxc_uart_device0, &uart_pdata); | ||
| 81 | } | ||
| 82 | |||
| 83 | static struct resource dnet_resources[] = { | ||
| 84 | [0] = { | ||
| 85 | .name = "dnet-memory", | ||
| 86 | .start = QONG_DNET_BASEADDR, | ||
| 87 | .end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1, | ||
| 88 | .flags = IORESOURCE_MEM, | ||
| 89 | }, | ||
| 90 | [1] = { | ||
| 91 | .start = QONG_FPGA_IRQ, | ||
| 92 | .end = QONG_FPGA_IRQ, | ||
| 93 | .flags = IORESOURCE_IRQ, | ||
| 94 | }, | ||
| 95 | }; | ||
| 96 | |||
| 97 | static struct platform_device dnet_device = { | ||
| 98 | .name = "dnet", | ||
| 99 | .id = -1, | ||
| 100 | .num_resources = ARRAY_SIZE(dnet_resources), | ||
| 101 | .resource = dnet_resources, | ||
| 102 | }; | ||
| 103 | |||
| 104 | static int __init qong_init_dnet(void) | ||
| 105 | { | ||
| 106 | int ret; | ||
| 107 | |||
| 108 | ret = platform_device_register(&dnet_device); | ||
| 109 | return ret; | ||
| 110 | } | ||
| 111 | |||
| 112 | /* MTD NOR flash */ | ||
| 113 | |||
| 114 | static struct physmap_flash_data qong_flash_data = { | ||
| 115 | .width = 2, | ||
| 116 | }; | ||
| 117 | |||
| 118 | static struct resource qong_flash_resource = { | ||
| 119 | .start = CS0_BASE_ADDR, | ||
| 120 | .end = CS0_BASE_ADDR + QONG_NOR_SIZE - 1, | ||
| 121 | .flags = IORESOURCE_MEM, | ||
| 122 | }; | ||
| 123 | |||
| 124 | static struct platform_device qong_nor_mtd_device = { | ||
| 125 | .name = "physmap-flash", | ||
| 126 | .id = 0, | ||
| 127 | .dev = { | ||
| 128 | .platform_data = &qong_flash_data, | ||
| 129 | }, | ||
| 130 | .resource = &qong_flash_resource, | ||
| 131 | .num_resources = 1, | ||
| 132 | }; | ||
| 133 | |||
| 134 | static void qong_init_nor_mtd(void) | ||
| 135 | { | ||
| 136 | (void)platform_device_register(&qong_nor_mtd_device); | ||
| 137 | } | ||
| 138 | |||
| 139 | /* | ||
| 140 | * Hardware specific access to control-lines | ||
| 141 | */ | ||
| 142 | static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) | ||
| 143 | { | ||
| 144 | struct nand_chip *nand_chip = mtd->priv; | ||
| 145 | |||
| 146 | if (cmd == NAND_CMD_NONE) | ||
| 147 | return; | ||
| 148 | |||
| 149 | if (ctrl & NAND_CLE) | ||
| 150 | writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24)); | ||
| 151 | else | ||
| 152 | writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23)); | ||
| 153 | } | ||
| 154 | |||
| 155 | /* | ||
| 156 | * Read the Device Ready pin. | ||
| 157 | */ | ||
| 158 | static int qong_nand_device_ready(struct mtd_info *mtd) | ||
| 159 | { | ||
| 160 | return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB)); | ||
| 161 | } | ||
| 162 | |||
| 163 | static void qong_nand_select_chip(struct mtd_info *mtd, int chip) | ||
| 164 | { | ||
| 165 | if (chip >= 0) | ||
| 166 | gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0); | ||
| 167 | else | ||
| 168 | gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1); | ||
| 169 | } | ||
| 170 | |||
| 171 | static struct platform_nand_data qong_nand_data = { | ||
| 172 | .chip = { | ||
| 173 | .chip_delay = 20, | ||
| 174 | .options = 0, | ||
| 175 | }, | ||
| 176 | .ctrl = { | ||
| 177 | .cmd_ctrl = qong_nand_cmd_ctrl, | ||
| 178 | .dev_ready = qong_nand_device_ready, | ||
| 179 | .select_chip = qong_nand_select_chip, | ||
| 180 | } | ||
| 181 | }; | ||
| 182 | |||
| 183 | static struct resource qong_nand_resource = { | ||
| 184 | .start = CS3_BASE_ADDR, | ||
| 185 | .end = CS3_BASE_ADDR + SZ_32M - 1, | ||
| 186 | .flags = IORESOURCE_MEM, | ||
| 187 | }; | ||
| 188 | |||
| 189 | static struct platform_device qong_nand_device = { | ||
| 190 | .name = "gen_nand", | ||
| 191 | .id = -1, | ||
| 192 | .dev = { | ||
| 193 | .platform_data = &qong_nand_data, | ||
| 194 | }, | ||
| 195 | .num_resources = 1, | ||
| 196 | .resource = &qong_nand_resource, | ||
| 197 | }; | ||
| 198 | |||
| 199 | static void __init qong_init_nand_mtd(void) | ||
| 200 | { | ||
| 201 | /* init CS */ | ||
| 202 | __raw_writel(0x00004f00, CSCR_U(3)); | ||
| 203 | __raw_writel(0x20013b31, CSCR_L(3)); | ||
| 204 | __raw_writel(0x00020800, CSCR_A(3)); | ||
| 205 | mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true); | ||
| 206 | |||
| 207 | /* enable pin */ | ||
| 208 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO)); | ||
| 209 | if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable")) | ||
| 210 | gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0); | ||
| 211 | |||
| 212 | /* ready/busy pin */ | ||
| 213 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO)); | ||
| 214 | if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy")) | ||
| 215 | gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB)); | ||
| 216 | |||
| 217 | /* write protect pin */ | ||
| 218 | mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO)); | ||
| 219 | if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp")) | ||
| 220 | gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B)); | ||
| 221 | |||
| 222 | platform_device_register(&qong_nand_device); | ||
| 223 | } | ||
| 224 | |||
| 225 | static void __init qong_init_fpga(void) | ||
| 226 | { | ||
| 227 | void __iomem *regs; | ||
| 228 | u32 fpga_ver; | ||
| 229 | |||
| 230 | regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE); | ||
| 231 | if (!regs) { | ||
| 232 | printk(KERN_ERR "%s: failed to map registers, aborting.\n", | ||
| 233 | __func__); | ||
| 234 | return; | ||
| 235 | } | ||
| 236 | |||
| 237 | fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION); | ||
| 238 | iounmap(regs); | ||
| 239 | printk(KERN_INFO "Qong FPGA version %d.%d.%d\n", | ||
| 240 | (fpga_ver & 0xF000) >> 12, | ||
| 241 | (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF); | ||
| 242 | if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) { | ||
| 243 | printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based " | ||
| 244 | "devices won't be registered!\n"); | ||
| 245 | return; | ||
| 246 | } | ||
| 247 | |||
| 248 | /* register FPGA-based devices */ | ||
| 249 | qong_init_nand_mtd(); | ||
| 250 | qong_init_dnet(); | ||
| 251 | } | ||
| 252 | |||
| 253 | /* | ||
| 254 | * This structure defines the MX31 memory map. | ||
| 255 | */ | ||
| 256 | static struct map_desc qong_io_desc[] __initdata = { | ||
| 257 | { | ||
| 258 | .virtual = AIPS1_BASE_ADDR_VIRT, | ||
| 259 | .pfn = __phys_to_pfn(AIPS1_BASE_ADDR), | ||
| 260 | .length = AIPS1_SIZE, | ||
| 261 | .type = MT_DEVICE_NONSHARED | ||
| 262 | }, { | ||
| 263 | .virtual = AIPS2_BASE_ADDR_VIRT, | ||
| 264 | .pfn = __phys_to_pfn(AIPS2_BASE_ADDR), | ||
| 265 | .length = AIPS2_SIZE, | ||
| 266 | .type = MT_DEVICE_NONSHARED | ||
| 267 | } | ||
| 268 | }; | ||
| 269 | |||
| 270 | /* | ||
| 271 | * Set up static virtual mappings. | ||
| 272 | */ | ||
| 273 | static void __init qong_map_io(void) | ||
| 274 | { | ||
| 275 | mxc_map_io(); | ||
| 276 | iotable_init(qong_io_desc, ARRAY_SIZE(qong_io_desc)); | ||
| 277 | } | ||
| 278 | |||
| 279 | /* | ||
| 280 | * Board specific initialization. | ||
| 281 | */ | ||
| 282 | static void __init mxc_board_init(void) | ||
| 283 | { | ||
| 284 | mxc_init_imx_uart(); | ||
| 285 | qong_init_nor_mtd(); | ||
| 286 | qong_init_fpga(); | ||
| 287 | } | ||
| 288 | |||
| 289 | static void __init qong_timer_init(void) | ||
| 290 | { | ||
| 291 | mx31_clocks_init(26000000); | ||
| 292 | } | ||
| 293 | |||
| 294 | static struct sys_timer qong_timer = { | ||
| 295 | .init = qong_timer_init, | ||
| 296 | }; | ||
| 297 | |||
| 298 | /* | ||
| 299 | * The following uses standard kernel macros defined in arch.h in order to | ||
| 300 | * initialize __mach_desc_QONG data structure. | ||
| 301 | */ | ||
| 302 | |||
| 303 | MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") | ||
| 304 | /* Maintainer: DENX Software Engineering GmbH */ | ||
| 305 | .phys_io = AIPS1_BASE_ADDR, | ||
| 306 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, | ||
| 307 | .boot_params = PHYS_OFFSET + 0x100, | ||
| 308 | .map_io = qong_map_io, | ||
| 309 | .init_irq = mxc_init_irq, | ||
| 310 | .init_machine = mxc_board_init, | ||
| 311 | .timer = &qong_timer, | ||
| 312 | MACHINE_END | ||
diff --git a/arch/arm/mach-netx/include/mach/system.h b/arch/arm/mach-netx/include/mach/system.h index 6c1023b8a9ab..dc7b4bc003c5 100644 --- a/arch/arm/mach-netx/include/mach/system.h +++ b/arch/arm/mach-netx/include/mach/system.h | |||
| @@ -28,7 +28,7 @@ static inline void arch_idle(void) | |||
| 28 | cpu_do_idle(); | 28 | cpu_do_idle(); |
| 29 | } | 29 | } |
| 30 | 30 | ||
| 31 | static inline void arch_reset(char mode) | 31 | static inline void arch_reset(char mode, const char *cmd) |
| 32 | { | 32 | { |
| 33 | writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES, | 33 | writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES, |
| 34 | NETX_SYSTEM_RES_CR); | 34 | NETX_SYSTEM_RES_CR); |
diff --git a/arch/arm/mach-ns9xxx/include/mach/system.h b/arch/arm/mach-ns9xxx/include/mach/system.h index e2068c57415f..1561588ca364 100644 --- a/arch/arm/mach-ns9xxx/include/mach/system.h +++ b/arch/arm/mach-ns9xxx/include/mach/system.h | |||
| @@ -20,7 +20,7 @@ static inline void arch_idle(void) | |||
| 20 | cpu_do_idle(); | 20 | cpu_do_idle(); |
| 21 | } | 21 | } |
| 22 | 22 | ||
| 23 | static inline void arch_reset(char mode) | 23 | static inline void arch_reset(char mode, const char *cmd) |
| 24 | { | 24 | { |
| 25 | #ifdef CONFIG_PROCESSOR_NS9360 | 25 | #ifdef CONFIG_PROCESSOR_NS9360 |
| 26 | if (processor_is_ns9360()) | 26 | if (processor_is_ns9360()) |
diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 10a301e32434..3f325d3718a9 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig | |||
| @@ -7,6 +7,11 @@ config ARCH_OMAP730 | |||
| 7 | select CPU_ARM926T | 7 | select CPU_ARM926T |
| 8 | select ARCH_OMAP_OTG | 8 | select ARCH_OMAP_OTG |
| 9 | 9 | ||
| 10 | config ARCH_OMAP850 | ||
| 11 | depends on ARCH_OMAP1 | ||
| 12 | bool "OMAP850 Based System" | ||
| 13 | select CPU_ARM926T | ||
| 14 | |||
| 10 | config ARCH_OMAP15XX | 15 | config ARCH_OMAP15XX |
| 11 | depends on ARCH_OMAP1 | 16 | depends on ARCH_OMAP1 |
| 12 | default y | 17 | default y |
| @@ -46,6 +51,12 @@ config MACH_OMAP_H3 | |||
| 46 | TI OMAP 1710 H3 board support. Say Y here if you have such | 51 | TI OMAP 1710 H3 board support. Say Y here if you have such |
| 47 | a board. | 52 | a board. |
| 48 | 53 | ||
| 54 | config MACH_OMAP_HTCWIZARD | ||
| 55 | bool "HTC Wizard" | ||
| 56 | depends on ARCH_OMAP850 | ||
| 57 | help | ||
| 58 | HTC Wizard smartphone support (AKA QTEK 9100, ...) | ||
| 59 | |||
| 49 | config MACH_OMAP_OSK | 60 | config MACH_OMAP_OSK |
| 50 | bool "TI OSK Support" | 61 | bool "TI OSK Support" |
| 51 | depends on ARCH_OMAP1 && ARCH_OMAP16XX | 62 | depends on ARCH_OMAP1 && ARCH_OMAP16XX |
| @@ -163,7 +174,7 @@ config OMAP_ARM_216MHZ | |||
| 163 | 174 | ||
| 164 | config OMAP_ARM_195MHZ | 175 | config OMAP_ARM_195MHZ |
| 165 | bool "OMAP ARM 195 MHz CPU" | 176 | bool "OMAP ARM 195 MHz CPU" |
| 166 | depends on ARCH_OMAP1 && ARCH_OMAP730 | 177 | depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850) |
| 167 | help | 178 | help |
| 168 | Enable 195MHz clock for OMAP CPU. If unsure, say N. | 179 | Enable 195MHz clock for OMAP CPU. If unsure, say N. |
| 169 | 180 | ||
| @@ -175,13 +186,13 @@ config OMAP_ARM_192MHZ | |||
| 175 | 186 | ||
| 176 | config OMAP_ARM_182MHZ | 187 | config OMAP_ARM_182MHZ |
| 177 | bool "OMAP ARM 182 MHz CPU" | 188 | bool "OMAP ARM 182 MHz CPU" |
| 178 | depends on ARCH_OMAP1 && ARCH_OMAP730 | 189 | depends on ARCH_OMAP1 && (ARCH_OMAP730 || ARCH_OMAP850) |
| 179 | help | 190 | help |
| 180 | Enable 182MHz clock for OMAP CPU. If unsure, say N. | 191 | Enable 182MHz clock for OMAP CPU. If unsure, say N. |
| 181 | 192 | ||
| 182 | config OMAP_ARM_168MHZ | 193 | config OMAP_ARM_168MHZ |
| 183 | bool "OMAP ARM 168 MHz CPU" | 194 | bool "OMAP ARM 168 MHz CPU" |
| 184 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730) | 195 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) |
| 185 | help | 196 | help |
| 186 | Enable 168MHz clock for OMAP CPU. If unsure, say N. | 197 | Enable 168MHz clock for OMAP CPU. If unsure, say N. |
| 187 | 198 | ||
| @@ -193,20 +204,20 @@ config OMAP_ARM_150MHZ | |||
| 193 | 204 | ||
| 194 | config OMAP_ARM_120MHZ | 205 | config OMAP_ARM_120MHZ |
| 195 | bool "OMAP ARM 120 MHz CPU" | 206 | bool "OMAP ARM 120 MHz CPU" |
| 196 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730) | 207 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) |
| 197 | help | 208 | help |
| 198 | Enable 120MHz clock for OMAP CPU. If unsure, say N. | 209 | Enable 120MHz clock for OMAP CPU. If unsure, say N. |
| 199 | 210 | ||
| 200 | config OMAP_ARM_60MHZ | 211 | config OMAP_ARM_60MHZ |
| 201 | bool "OMAP ARM 60 MHz CPU" | 212 | bool "OMAP ARM 60 MHz CPU" |
| 202 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730) | 213 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) |
| 203 | default y | 214 | default y |
| 204 | help | 215 | help |
| 205 | Enable 60MHz clock for OMAP CPU. If unsure, say Y. | 216 | Enable 60MHz clock for OMAP CPU. If unsure, say Y. |
| 206 | 217 | ||
| 207 | config OMAP_ARM_30MHZ | 218 | config OMAP_ARM_30MHZ |
| 208 | bool "OMAP ARM 30 MHz CPU" | 219 | bool "OMAP ARM 30 MHz CPU" |
| 209 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730) | 220 | depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX || ARCH_OMAP730 || ARCH_OMAP850) |
| 210 | help | 221 | help |
| 211 | Enable 30MHz clock for OMAP CPU. If unsure, say N. | 222 | Enable 30MHz clock for OMAP CPU. If unsure, say N. |
| 212 | 223 | ||
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 2e618391cc51..8b40aace9db4 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c | |||
| @@ -175,7 +175,6 @@ static struct omap_usb_config ams_delta_usb_config __initdata = { | |||
| 175 | static struct omap_board_config_kernel ams_delta_config[] = { | 175 | static struct omap_board_config_kernel ams_delta_config[] = { |
| 176 | { OMAP_TAG_LCD, &ams_delta_lcd_config }, | 176 | { OMAP_TAG_LCD, &ams_delta_lcd_config }, |
| 177 | { OMAP_TAG_UART, &ams_delta_uart_config }, | 177 | { OMAP_TAG_UART, &ams_delta_uart_config }, |
| 178 | { OMAP_TAG_USB, &ams_delta_usb_config }, | ||
| 179 | }; | 178 | }; |
| 180 | 179 | ||
| 181 | static struct resource ams_delta_kp_resources[] = { | 180 | static struct resource ams_delta_kp_resources[] = { |
| @@ -232,6 +231,7 @@ static void __init ams_delta_init(void) | |||
| 232 | /* Clear latch2 (NAND, LCD, modem enable) */ | 231 | /* Clear latch2 (NAND, LCD, modem enable) */ |
| 233 | ams_delta_latch2_write(~0, 0); | 232 | ams_delta_latch2_write(~0, 0); |
| 234 | 233 | ||
| 234 | omap_usb_init(&ams_delta_usb_config); | ||
| 235 | platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); | 235 | platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); |
| 236 | } | 236 | } |
| 237 | 237 | ||
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c index 30308294e7c1..19e0e9232336 100644 --- a/arch/arm/mach-omap1/board-fsample.c +++ b/arch/arm/mach-omap1/board-fsample.c | |||
| @@ -34,7 +34,39 @@ | |||
| 34 | #include <mach/keypad.h> | 34 | #include <mach/keypad.h> |
| 35 | #include <mach/common.h> | 35 | #include <mach/common.h> |
| 36 | #include <mach/board.h> | 36 | #include <mach/board.h> |
| 37 | #include <mach/board-fsample.h> | 37 | |
| 38 | /* fsample is pretty close to p2-sample */ | ||
| 39 | |||
| 40 | #define fsample_cpld_read(reg) __raw_readb(reg) | ||
| 41 | #define fsample_cpld_write(val, reg) __raw_writeb(val, reg) | ||
| 42 | |||
| 43 | #define FSAMPLE_CPLD_BASE 0xE8100000 | ||
| 44 | #define FSAMPLE_CPLD_SIZE SZ_4K | ||
| 45 | #define FSAMPLE_CPLD_START 0x05080000 | ||
| 46 | |||
| 47 | #define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00) | ||
| 48 | #define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02) | ||
| 49 | #define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02) | ||
| 50 | #define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04) | ||
| 51 | #define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06) | ||
| 52 | #define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06) | ||
| 53 | |||
| 54 | #define FSAMPLE_CPLD_BIT_BT_RESET 0 | ||
| 55 | #define FSAMPLE_CPLD_BIT_LCD_RESET 1 | ||
| 56 | #define FSAMPLE_CPLD_BIT_CAM_PWDN 2 | ||
| 57 | #define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3 | ||
| 58 | #define FSAMPLE_CPLD_BIT_SD_MMC_EN 4 | ||
| 59 | #define FSAMPLE_CPLD_BIT_aGPS_PWREN 5 | ||
| 60 | #define FSAMPLE_CPLD_BIT_BACKLIGHT 6 | ||
| 61 | #define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7 | ||
| 62 | #define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8 | ||
| 63 | #define FSAMPLE_CPLD_BIT_OTG_RESET 9 | ||
| 64 | |||
| 65 | #define fsample_cpld_set(bit) \ | ||
| 66 | fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR) | ||
| 67 | |||
| 68 | #define fsample_cpld_clear(bit) \ | ||
| 69 | fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR) | ||
| 38 | 70 | ||
| 39 | static int fsample_keymap[] = { | 71 | static int fsample_keymap[] = { |
| 40 | KEY(0,0,KEY_UP), | 72 | KEY(0,0,KEY_UP), |
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c index 7d2670205373..e724940e86f2 100644 --- a/arch/arm/mach-omap1/board-generic.c +++ b/arch/arm/mach-omap1/board-generic.c | |||
| @@ -62,7 +62,6 @@ static struct omap_uart_config generic_uart_config __initdata = { | |||
| 62 | }; | 62 | }; |
| 63 | 63 | ||
| 64 | static struct omap_board_config_kernel generic_config[] __initdata = { | 64 | static struct omap_board_config_kernel generic_config[] __initdata = { |
| 65 | { OMAP_TAG_USB, NULL }, | ||
| 66 | { OMAP_TAG_UART, &generic_uart_config }, | 65 | { OMAP_TAG_UART, &generic_uart_config }, |
| 67 | }; | 66 | }; |
| 68 | 67 | ||
| @@ -70,12 +69,12 @@ static void __init omap_generic_init(void) | |||
| 70 | { | 69 | { |
| 71 | #ifdef CONFIG_ARCH_OMAP15XX | 70 | #ifdef CONFIG_ARCH_OMAP15XX |
| 72 | if (cpu_is_omap15xx()) { | 71 | if (cpu_is_omap15xx()) { |
| 73 | generic_config[0].data = &generic1510_usb_config; | 72 | omap_usb_init(&generic1510_usb_config); |
| 74 | } | 73 | } |
| 75 | #endif | 74 | #endif |
| 76 | #if defined(CONFIG_ARCH_OMAP16XX) | 75 | #if defined(CONFIG_ARCH_OMAP16XX) |
| 77 | if (!cpu_is_omap1510()) { | 76 | if (!cpu_is_omap1510()) { |
| 78 | generic_config[0].data = &generic1610_usb_config; | 77 | omap_usb_init(&generic1610_usb_config); |
| 79 | } | 78 | } |
| 80 | #endif | 79 | #endif |
| 81 | 80 | ||
diff --git a/arch/arm/mach-omap1/board-h2-mmc.c b/arch/arm/mach-omap1/board-h2-mmc.c index 409fa56d0a87..44d4a966bed9 100644 --- a/arch/arm/mach-omap1/board-h2-mmc.c +++ b/arch/arm/mach-omap1/board-h2-mmc.c | |||
| @@ -19,6 +19,8 @@ | |||
| 19 | #include <mach/mmc.h> | 19 | #include <mach/mmc.h> |
| 20 | #include <mach/gpio.h> | 20 | #include <mach/gpio.h> |
| 21 | 21 | ||
| 22 | #include "board-h2.h" | ||
| 23 | |||
| 22 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) | 24 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) |
| 23 | 25 | ||
| 24 | static int mmc_set_power(struct device *dev, int slot, int power_on, | 26 | static int mmc_set_power(struct device *dev, int slot, int power_on, |
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c index 0d784a795092..f695aa053ac8 100644 --- a/arch/arm/mach-omap1/board-h2.c +++ b/arch/arm/mach-omap1/board-h2.c | |||
| @@ -46,6 +46,11 @@ | |||
| 46 | #include <mach/keypad.h> | 46 | #include <mach/keypad.h> |
| 47 | #include <mach/common.h> | 47 | #include <mach/common.h> |
| 48 | 48 | ||
| 49 | #include "board-h2.h" | ||
| 50 | |||
| 51 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ | ||
| 52 | #define OMAP1610_ETHR_START 0x04000300 | ||
| 53 | |||
| 49 | static int h2_keymap[] = { | 54 | static int h2_keymap[] = { |
| 50 | KEY(0, 0, KEY_LEFT), | 55 | KEY(0, 0, KEY_LEFT), |
| 51 | KEY(0, 1, KEY_RIGHT), | 56 | KEY(0, 1, KEY_RIGHT), |
| @@ -364,7 +369,6 @@ static struct omap_lcd_config h2_lcd_config __initdata = { | |||
| 364 | }; | 369 | }; |
| 365 | 370 | ||
| 366 | static struct omap_board_config_kernel h2_config[] __initdata = { | 371 | static struct omap_board_config_kernel h2_config[] __initdata = { |
| 367 | { OMAP_TAG_USB, &h2_usb_config }, | ||
| 368 | { OMAP_TAG_UART, &h2_uart_config }, | 372 | { OMAP_TAG_UART, &h2_uart_config }, |
| 369 | { OMAP_TAG_LCD, &h2_lcd_config }, | 373 | { OMAP_TAG_LCD, &h2_lcd_config }, |
| 370 | }; | 374 | }; |
| @@ -413,6 +417,7 @@ static void __init h2_init(void) | |||
| 413 | omap_serial_init(); | 417 | omap_serial_init(); |
| 414 | omap_register_i2c_bus(1, 100, h2_i2c_board_info, | 418 | omap_register_i2c_bus(1, 100, h2_i2c_board_info, |
| 415 | ARRAY_SIZE(h2_i2c_board_info)); | 419 | ARRAY_SIZE(h2_i2c_board_info)); |
| 420 | omap_usb_init(&h2_usb_config); | ||
| 416 | h2_mmc_init(); | 421 | h2_mmc_init(); |
| 417 | } | 422 | } |
| 418 | 423 | ||
diff --git a/arch/arm/plat-omap/include/mach/board-h2.h b/arch/arm/mach-omap1/board-h2.h index 15531c8dc0e6..315e2662547e 100644 --- a/arch/arm/plat-omap/include/mach/board-h2.h +++ b/arch/arm/mach-omap1/board-h2.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/plat-omap/include/mach/board-h2.h | 2 | * arch/arm/mach-omap1/board-h2.h |
| 3 | * | 3 | * |
| 4 | * Hardware definitions for TI OMAP1610 H2 board. | 4 | * Hardware definitions for TI OMAP1610 H2 board. |
| 5 | * | 5 | * |
| @@ -29,9 +29,6 @@ | |||
| 29 | #ifndef __ASM_ARCH_OMAP_H2_H | 29 | #ifndef __ASM_ARCH_OMAP_H2_H |
| 30 | #define __ASM_ARCH_OMAP_H2_H | 30 | #define __ASM_ARCH_OMAP_H2_H |
| 31 | 31 | ||
| 32 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ | ||
| 33 | #define OMAP1610_ETHR_START 0x04000300 | ||
| 34 | |||
| 35 | #define H2_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) | 32 | #define H2_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) |
| 36 | # define H2_TPS_GPIO_MMC_PWR_EN (H2_TPS_GPIO_BASE + 3) | 33 | # define H2_TPS_GPIO_MMC_PWR_EN (H2_TPS_GPIO_BASE + 3) |
| 37 | 34 | ||
diff --git a/arch/arm/mach-omap1/board-h3-mmc.c b/arch/arm/mach-omap1/board-h3-mmc.c index fdfe793d56f2..0d8a3c195e2e 100644 --- a/arch/arm/mach-omap1/board-h3-mmc.c +++ b/arch/arm/mach-omap1/board-h3-mmc.c | |||
| @@ -19,6 +19,8 @@ | |||
| 19 | #include <mach/mmc.h> | 19 | #include <mach/mmc.h> |
| 20 | #include <mach/gpio.h> | 20 | #include <mach/gpio.h> |
| 21 | 21 | ||
| 22 | #include "board-h3.h" | ||
| 23 | |||
| 22 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) | 24 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) |
| 23 | 25 | ||
| 24 | static int mmc_set_power(struct device *dev, int slot, int power_on, | 26 | static int mmc_set_power(struct device *dev, int slot, int power_on, |
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c index bf08b6ad22ee..4695965114c4 100644 --- a/arch/arm/mach-omap1/board-h3.c +++ b/arch/arm/mach-omap1/board-h3.c | |||
| @@ -50,6 +50,11 @@ | |||
| 50 | #include <mach/dma.h> | 50 | #include <mach/dma.h> |
| 51 | #include <mach/common.h> | 51 | #include <mach/common.h> |
| 52 | 52 | ||
| 53 | #include "board-h3.h" | ||
| 54 | |||
| 55 | /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ | ||
| 56 | #define OMAP1710_ETHR_START 0x04000300 | ||
| 57 | |||
| 53 | #define H3_TS_GPIO 48 | 58 | #define H3_TS_GPIO 48 |
| 54 | 59 | ||
| 55 | static int h3_keymap[] = { | 60 | static int h3_keymap[] = { |
| @@ -418,7 +423,6 @@ static struct omap_lcd_config h3_lcd_config __initdata = { | |||
| 418 | }; | 423 | }; |
| 419 | 424 | ||
| 420 | static struct omap_board_config_kernel h3_config[] __initdata = { | 425 | static struct omap_board_config_kernel h3_config[] __initdata = { |
| 421 | { OMAP_TAG_USB, &h3_usb_config }, | ||
| 422 | { OMAP_TAG_UART, &h3_uart_config }, | 426 | { OMAP_TAG_UART, &h3_uart_config }, |
| 423 | { OMAP_TAG_LCD, &h3_lcd_config }, | 427 | { OMAP_TAG_LCD, &h3_lcd_config }, |
| 424 | }; | 428 | }; |
| @@ -472,6 +476,7 @@ static void __init h3_init(void) | |||
| 472 | omap_serial_init(); | 476 | omap_serial_init(); |
| 473 | omap_register_i2c_bus(1, 100, h3_i2c_board_info, | 477 | omap_register_i2c_bus(1, 100, h3_i2c_board_info, |
| 474 | ARRAY_SIZE(h3_i2c_board_info)); | 478 | ARRAY_SIZE(h3_i2c_board_info)); |
| 479 | omap_usb_init(&h3_usb_config); | ||
| 475 | h3_mmc_init(); | 480 | h3_mmc_init(); |
| 476 | } | 481 | } |
| 477 | 482 | ||
diff --git a/arch/arm/plat-omap/include/mach/board-h3.h b/arch/arm/mach-omap1/board-h3.h index 1888326da7ea..78de535be3c5 100644 --- a/arch/arm/plat-omap/include/mach/board-h3.h +++ b/arch/arm/mach-omap1/board-h3.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * arch/arm/plat-omap/include/mach/board-h3.h | 2 | * arch/arm/mach-omap1/board-h3.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2001 RidgeRun, Inc. | 4 | * Copyright (C) 2001 RidgeRun, Inc. |
| 5 | * Copyright (C) 2004 Texas Instruments, Inc. | 5 | * Copyright (C) 2004 Texas Instruments, Inc. |
| @@ -27,9 +27,6 @@ | |||
| 27 | #ifndef __ASM_ARCH_OMAP_H3_H | 27 | #ifndef __ASM_ARCH_OMAP_H3_H |
| 28 | #define __ASM_ARCH_OMAP_H3_H | 28 | #define __ASM_ARCH_OMAP_H3_H |
| 29 | 29 | ||
| 30 | /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ | ||
| 31 | #define OMAP1710_ETHR_START 0x04000300 | ||
| 32 | |||
| 33 | #define H3_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) | 30 | #define H3_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) |
| 34 | # define H3_TPS_GPIO_MMC_PWR_EN (H3_TPS_GPIO_BASE + 4) | 31 | # define H3_TPS_GPIO_MMC_PWR_EN (H3_TPS_GPIO_BASE + 4) |
| 35 | 32 | ||
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c index 071cd02a734e..2fd98260ea49 100644 --- a/arch/arm/mach-omap1/board-innovator.c +++ b/arch/arm/mach-omap1/board-innovator.c | |||
| @@ -39,6 +39,9 @@ | |||
| 39 | #include <mach/common.h> | 39 | #include <mach/common.h> |
| 40 | #include <mach/mmc.h> | 40 | #include <mach/mmc.h> |
| 41 | 41 | ||
| 42 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ | ||
| 43 | #define INNOVATOR1610_ETHR_START 0x04000300 | ||
| 44 | |||
| 42 | static int innovator_keymap[] = { | 45 | static int innovator_keymap[] = { |
| 43 | KEY(0, 0, KEY_F1), | 46 | KEY(0, 0, KEY_F1), |
| 44 | KEY(0, 3, KEY_DOWN), | 47 | KEY(0, 3, KEY_DOWN), |
| @@ -370,7 +373,6 @@ static struct omap_uart_config innovator_uart_config __initdata = { | |||
| 370 | }; | 373 | }; |
| 371 | 374 | ||
| 372 | static struct omap_board_config_kernel innovator_config[] = { | 375 | static struct omap_board_config_kernel innovator_config[] = { |
| 373 | { OMAP_TAG_USB, NULL }, | ||
| 374 | { OMAP_TAG_LCD, NULL }, | 376 | { OMAP_TAG_LCD, NULL }, |
| 375 | { OMAP_TAG_UART, &innovator_uart_config }, | 377 | { OMAP_TAG_UART, &innovator_uart_config }, |
| 376 | }; | 378 | }; |
| @@ -392,13 +394,13 @@ static void __init innovator_init(void) | |||
| 392 | 394 | ||
| 393 | #ifdef CONFIG_ARCH_OMAP15XX | 395 | #ifdef CONFIG_ARCH_OMAP15XX |
| 394 | if (cpu_is_omap1510()) { | 396 | if (cpu_is_omap1510()) { |
| 395 | innovator_config[0].data = &innovator1510_usb_config; | 397 | omap_usb_init(&innovator1510_usb_config); |
| 396 | innovator_config[1].data = &innovator1510_lcd_config; | 398 | innovator_config[1].data = &innovator1510_lcd_config; |
| 397 | } | 399 | } |
| 398 | #endif | 400 | #endif |
| 399 | #ifdef CONFIG_ARCH_OMAP16XX | 401 | #ifdef CONFIG_ARCH_OMAP16XX |
| 400 | if (cpu_is_omap1610()) { | 402 | if (cpu_is_omap1610()) { |
| 401 | innovator_config[0].data = &h2_usb_config; | 403 | omap_usb_init(&h2_usb_config); |
| 402 | innovator_config[1].data = &innovator1610_lcd_config; | 404 | innovator_config[1].data = &innovator1610_lcd_config; |
| 403 | } | 405 | } |
| 404 | #endif | 406 | #endif |
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c index af51e0b180f2..7bc7a3cb9c51 100644 --- a/arch/arm/mach-omap1/board-nokia770.c +++ b/arch/arm/mach-omap1/board-nokia770.c | |||
| @@ -233,10 +233,6 @@ static inline void nokia770_mmc_init(void) | |||
| 233 | } | 233 | } |
| 234 | #endif | 234 | #endif |
| 235 | 235 | ||
| 236 | static struct omap_board_config_kernel nokia770_config[] __initdata = { | ||
| 237 | { OMAP_TAG_USB, NULL }, | ||
| 238 | }; | ||
| 239 | |||
| 240 | #if defined(CONFIG_OMAP_DSP) | 236 | #if defined(CONFIG_OMAP_DSP) |
| 241 | /* | 237 | /* |
| 242 | * audio power control | 238 | * audio power control |
| @@ -371,19 +367,16 @@ static __init int omap_dsp_init(void) | |||
| 371 | 367 | ||
| 372 | static void __init omap_nokia770_init(void) | 368 | static void __init omap_nokia770_init(void) |
| 373 | { | 369 | { |
| 374 | nokia770_config[0].data = &nokia770_usb_config; | ||
| 375 | |||
| 376 | platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices)); | 370 | platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices)); |
| 377 | spi_register_board_info(nokia770_spi_board_info, | 371 | spi_register_board_info(nokia770_spi_board_info, |
| 378 | ARRAY_SIZE(nokia770_spi_board_info)); | 372 | ARRAY_SIZE(nokia770_spi_board_info)); |
| 379 | omap_board_config = nokia770_config; | ||
| 380 | omap_board_config_size = ARRAY_SIZE(nokia770_config); | ||
| 381 | omap_gpio_init(); | 373 | omap_gpio_init(); |
| 382 | omap_serial_init(); | 374 | omap_serial_init(); |
| 383 | omap_register_i2c_bus(1, 100, NULL, 0); | 375 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 384 | omap_dsp_init(); | 376 | omap_dsp_init(); |
| 385 | ads7846_dev_init(); | 377 | ads7846_dev_init(); |
| 386 | mipid_dev_init(); | 378 | mipid_dev_init(); |
| 379 | omap_usb_init(&nokia770_usb_config); | ||
| 387 | nokia770_mmc_init(); | 380 | nokia770_mmc_init(); |
| 388 | } | 381 | } |
| 389 | 382 | ||
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c index 1a16ecb2ccc8..cf3247b15f87 100644 --- a/arch/arm/mach-omap1/board-osk.c +++ b/arch/arm/mach-omap1/board-osk.c | |||
| @@ -52,6 +52,20 @@ | |||
| 52 | #include <mach/tc.h> | 52 | #include <mach/tc.h> |
| 53 | #include <mach/common.h> | 53 | #include <mach/common.h> |
| 54 | 54 | ||
| 55 | /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */ | ||
| 56 | #define OMAP_OSK_ETHR_START 0x04800300 | ||
| 57 | |||
| 58 | /* TPS65010 has four GPIOs. nPG and LED2 can be treated like GPIOs with | ||
| 59 | * alternate pin configurations for hardware-controlled blinking. | ||
| 60 | */ | ||
| 61 | #define OSK_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) | ||
| 62 | # define OSK_TPS_GPIO_USB_PWR_EN (OSK_TPS_GPIO_BASE + 0) | ||
| 63 | # define OSK_TPS_GPIO_LED_D3 (OSK_TPS_GPIO_BASE + 1) | ||
| 64 | # define OSK_TPS_GPIO_LAN_RESET (OSK_TPS_GPIO_BASE + 2) | ||
| 65 | # define OSK_TPS_GPIO_DSP_PWR_EN (OSK_TPS_GPIO_BASE + 3) | ||
| 66 | # define OSK_TPS_GPIO_LED_D9 (OSK_TPS_GPIO_BASE + 4) | ||
| 67 | # define OSK_TPS_GPIO_LED_D2 (OSK_TPS_GPIO_BASE + 5) | ||
| 68 | |||
| 55 | static struct mtd_partition osk_partitions[] = { | 69 | static struct mtd_partition osk_partitions[] = { |
| 56 | /* bootloader (U-Boot, etc) in first sector */ | 70 | /* bootloader (U-Boot, etc) in first sector */ |
| 57 | { | 71 | { |
| @@ -290,7 +304,6 @@ static struct omap_lcd_config osk_lcd_config __initdata = { | |||
| 290 | #endif | 304 | #endif |
| 291 | 305 | ||
| 292 | static struct omap_board_config_kernel osk_config[] __initdata = { | 306 | static struct omap_board_config_kernel osk_config[] __initdata = { |
| 293 | { OMAP_TAG_USB, &osk_usb_config }, | ||
| 294 | { OMAP_TAG_UART, &osk_uart_config }, | 307 | { OMAP_TAG_UART, &osk_uart_config }, |
| 295 | #ifdef CONFIG_OMAP_OSK_MISTRAL | 308 | #ifdef CONFIG_OMAP_OSK_MISTRAL |
| 296 | { OMAP_TAG_LCD, &osk_lcd_config }, | 309 | { OMAP_TAG_LCD, &osk_lcd_config }, |
| @@ -541,6 +554,8 @@ static void __init osk_init(void) | |||
| 541 | l |= (3 << 1); | 554 | l |= (3 << 1); |
| 542 | omap_writel(l, USB_TRANSCEIVER_CTRL); | 555 | omap_writel(l, USB_TRANSCEIVER_CTRL); |
| 543 | 556 | ||
| 557 | omap_usb_init(&osk_usb_config); | ||
| 558 | |||
| 544 | /* irq for tps65010 chip */ | 559 | /* irq for tps65010 chip */ |
| 545 | /* bootloader effectively does: omap_cfg_reg(U19_1610_MPUIO1); */ | 560 | /* bootloader effectively does: omap_cfg_reg(U19_1610_MPUIO1); */ |
| 546 | if (gpio_request(OMAP_MPUIO(1), "tps65010") == 0) | 561 | if (gpio_request(OMAP_MPUIO(1), "tps65010") == 0) |
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c index 99f2b43f2541..886b4c0569bd 100644 --- a/arch/arm/mach-omap1/board-palmte.c +++ b/arch/arm/mach-omap1/board-palmte.c | |||
| @@ -43,6 +43,21 @@ | |||
| 43 | #include <mach/keypad.h> | 43 | #include <mach/keypad.h> |
| 44 | #include <mach/common.h> | 44 | #include <mach/common.h> |
| 45 | 45 | ||
| 46 | #define PALMTE_USBDETECT_GPIO 0 | ||
| 47 | #define PALMTE_USB_OR_DC_GPIO 1 | ||
| 48 | #define PALMTE_TSC_GPIO 4 | ||
| 49 | #define PALMTE_PINTDAV_GPIO 6 | ||
| 50 | #define PALMTE_MMC_WP_GPIO 8 | ||
| 51 | #define PALMTE_MMC_POWER_GPIO 9 | ||
| 52 | #define PALMTE_HDQ_GPIO 11 | ||
| 53 | #define PALMTE_HEADPHONES_GPIO 14 | ||
| 54 | #define PALMTE_SPEAKER_GPIO 15 | ||
| 55 | #define PALMTE_DC_GPIO OMAP_MPUIO(2) | ||
| 56 | #define PALMTE_MMC_SWITCH_GPIO OMAP_MPUIO(4) | ||
| 57 | #define PALMTE_MMC1_GPIO OMAP_MPUIO(6) | ||
| 58 | #define PALMTE_MMC2_GPIO OMAP_MPUIO(7) | ||
| 59 | #define PALMTE_MMC3_GPIO OMAP_MPUIO(11) | ||
| 60 | |||
| 46 | static void __init omap_palmte_init_irq(void) | 61 | static void __init omap_palmte_init_irq(void) |
| 47 | { | 62 | { |
| 48 | omap1_init_common_hw(); | 63 | omap1_init_common_hw(); |
| @@ -286,7 +301,6 @@ static void palmte_get_power_status(struct apm_power_info *info, int *battery) | |||
| 286 | #endif | 301 | #endif |
| 287 | 302 | ||
| 288 | static struct omap_board_config_kernel palmte_config[] __initdata = { | 303 | static struct omap_board_config_kernel palmte_config[] __initdata = { |
| 289 | { OMAP_TAG_USB, &palmte_usb_config }, | ||
| 290 | { OMAP_TAG_LCD, &palmte_lcd_config }, | 304 | { OMAP_TAG_LCD, &palmte_lcd_config }, |
| 291 | { OMAP_TAG_UART, &palmte_uart_config }, | 305 | { OMAP_TAG_UART, &palmte_uart_config }, |
| 292 | }; | 306 | }; |
| @@ -341,6 +355,7 @@ static void __init omap_palmte_init(void) | |||
| 341 | spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info)); | 355 | spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info)); |
| 342 | palmte_misc_gpio_setup(); | 356 | palmte_misc_gpio_setup(); |
| 343 | omap_serial_init(); | 357 | omap_serial_init(); |
| 358 | omap_usb_init(&palmte_usb_config); | ||
| 344 | omap_register_i2c_bus(1, 100, NULL, 0); | 359 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 345 | } | 360 | } |
| 346 | 361 | ||
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c index 1cbc1275c95f..4f1b44831d37 100644 --- a/arch/arm/mach-omap1/board-palmtt.c +++ b/arch/arm/mach-omap1/board-palmtt.c | |||
| @@ -43,6 +43,13 @@ | |||
| 43 | #include <linux/spi/spi.h> | 43 | #include <linux/spi/spi.h> |
| 44 | #include <linux/spi/ads7846.h> | 44 | #include <linux/spi/ads7846.h> |
| 45 | 45 | ||
| 46 | #define PALMTT_USBDETECT_GPIO 0 | ||
| 47 | #define PALMTT_CABLE_GPIO 1 | ||
| 48 | #define PALMTT_LED_GPIO 3 | ||
| 49 | #define PALMTT_PENIRQ_GPIO 6 | ||
| 50 | #define PALMTT_MMC_WP_GPIO 8 | ||
| 51 | #define PALMTT_HDQ_GPIO 11 | ||
| 52 | |||
| 46 | static int palmtt_keymap[] = { | 53 | static int palmtt_keymap[] = { |
| 47 | KEY(0, 0, KEY_ESC), | 54 | KEY(0, 0, KEY_ESC), |
| 48 | KEY(0, 1, KEY_SPACE), | 55 | KEY(0, 1, KEY_SPACE), |
| @@ -272,7 +279,6 @@ static struct omap_uart_config palmtt_uart_config __initdata = { | |||
| 272 | }; | 279 | }; |
| 273 | 280 | ||
| 274 | static struct omap_board_config_kernel palmtt_config[] __initdata = { | 281 | static struct omap_board_config_kernel palmtt_config[] __initdata = { |
| 275 | { OMAP_TAG_USB, &palmtt_usb_config }, | ||
| 276 | { OMAP_TAG_LCD, &palmtt_lcd_config }, | 282 | { OMAP_TAG_LCD, &palmtt_lcd_config }, |
| 277 | { OMAP_TAG_UART, &palmtt_uart_config }, | 283 | { OMAP_TAG_UART, &palmtt_uart_config }, |
| 278 | }; | 284 | }; |
| @@ -297,6 +303,7 @@ static void __init omap_palmtt_init(void) | |||
| 297 | 303 | ||
| 298 | spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo)); | 304 | spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo)); |
| 299 | omap_serial_init(); | 305 | omap_serial_init(); |
| 306 | omap_usb_init(&palmtt_usb_config); | ||
| 300 | omap_register_i2c_bus(1, 100, NULL, 0); | 307 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 301 | } | 308 | } |
| 302 | 309 | ||
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c index baf5efbfe3e8..9a55c3c58218 100644 --- a/arch/arm/mach-omap1/board-palmz71.c +++ b/arch/arm/mach-omap1/board-palmz71.c | |||
| @@ -46,6 +46,16 @@ | |||
| 46 | #include <linux/spi/spi.h> | 46 | #include <linux/spi/spi.h> |
| 47 | #include <linux/spi/ads7846.h> | 47 | #include <linux/spi/ads7846.h> |
| 48 | 48 | ||
| 49 | #define PALMZ71_USBDETECT_GPIO 0 | ||
| 50 | #define PALMZ71_PENIRQ_GPIO 6 | ||
| 51 | #define PALMZ71_MMC_WP_GPIO 8 | ||
| 52 | #define PALMZ71_HDQ_GPIO 11 | ||
| 53 | |||
| 54 | #define PALMZ71_HOTSYNC_GPIO OMAP_MPUIO(1) | ||
| 55 | #define PALMZ71_CABLE_GPIO OMAP_MPUIO(2) | ||
| 56 | #define PALMZ71_SLIDER_GPIO OMAP_MPUIO(3) | ||
| 57 | #define PALMZ71_MMC_IN_GPIO OMAP_MPUIO(4) | ||
| 58 | |||
| 49 | static void __init | 59 | static void __init |
| 50 | omap_palmz71_init_irq(void) | 60 | omap_palmz71_init_irq(void) |
| 51 | { | 61 | { |
| @@ -239,7 +249,6 @@ static struct omap_uart_config palmz71_uart_config __initdata = { | |||
| 239 | }; | 249 | }; |
| 240 | 250 | ||
| 241 | static struct omap_board_config_kernel palmz71_config[] __initdata = { | 251 | static struct omap_board_config_kernel palmz71_config[] __initdata = { |
| 242 | {OMAP_TAG_USB, &palmz71_usb_config}, | ||
| 243 | {OMAP_TAG_LCD, &palmz71_lcd_config}, | 252 | {OMAP_TAG_LCD, &palmz71_lcd_config}, |
| 244 | {OMAP_TAG_UART, &palmz71_uart_config}, | 253 | {OMAP_TAG_UART, &palmz71_uart_config}, |
| 245 | }; | 254 | }; |
| @@ -313,6 +322,7 @@ omap_palmz71_init(void) | |||
| 313 | 322 | ||
| 314 | spi_register_board_info(palmz71_boardinfo, | 323 | spi_register_board_info(palmz71_boardinfo, |
| 315 | ARRAY_SIZE(palmz71_boardinfo)); | 324 | ARRAY_SIZE(palmz71_boardinfo)); |
| 325 | omap_usb_init(&palmz71_usb_config); | ||
| 316 | omap_serial_init(); | 326 | omap_serial_init(); |
| 317 | omap_register_i2c_bus(1, 100, NULL, 0); | 327 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 318 | palmz71_gpio_setup(0); | 328 | palmz71_gpio_setup(0); |
diff --git a/arch/arm/mach-omap1/board-sx1-mmc.c b/arch/arm/mach-omap1/board-sx1-mmc.c index 66a4d7d5255d..58a46e4e45c3 100644 --- a/arch/arm/mach-omap1/board-sx1-mmc.c +++ b/arch/arm/mach-omap1/board-sx1-mmc.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
| 18 | #include <mach/mmc.h> | 18 | #include <mach/mmc.h> |
| 19 | #include <mach/gpio.h> | 19 | #include <mach/gpio.h> |
| 20 | #include <mach/board-sx1.h> | ||
| 20 | 21 | ||
| 21 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) | 22 | #if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) |
| 22 | 23 | ||
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c index 28c76a1e71c0..c096577695fe 100644 --- a/arch/arm/mach-omap1/board-sx1.c +++ b/arch/arm/mach-omap1/board-sx1.c | |||
| @@ -41,6 +41,7 @@ | |||
| 41 | #include <mach/board.h> | 41 | #include <mach/board.h> |
| 42 | #include <mach/common.h> | 42 | #include <mach/common.h> |
| 43 | #include <mach/keypad.h> | 43 | #include <mach/keypad.h> |
| 44 | #include <mach/board-sx1.h> | ||
| 44 | 45 | ||
| 45 | /* Write to I2C device */ | 46 | /* Write to I2C device */ |
| 46 | int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) | 47 | int sx1_i2c_write_byte(u8 devaddr, u8 regoffset, u8 value) |
| @@ -373,7 +374,6 @@ static struct omap_uart_config sx1_uart_config __initdata = { | |||
| 373 | }; | 374 | }; |
| 374 | 375 | ||
| 375 | static struct omap_board_config_kernel sx1_config[] __initdata = { | 376 | static struct omap_board_config_kernel sx1_config[] __initdata = { |
| 376 | { OMAP_TAG_USB, &sx1_usb_config }, | ||
| 377 | { OMAP_TAG_LCD, &sx1_lcd_config }, | 377 | { OMAP_TAG_LCD, &sx1_lcd_config }, |
| 378 | { OMAP_TAG_UART, &sx1_uart_config }, | 378 | { OMAP_TAG_UART, &sx1_uart_config }, |
| 379 | }; | 379 | }; |
| @@ -388,6 +388,7 @@ static void __init omap_sx1_init(void) | |||
| 388 | omap_board_config_size = ARRAY_SIZE(sx1_config); | 388 | omap_board_config_size = ARRAY_SIZE(sx1_config); |
| 389 | omap_serial_init(); | 389 | omap_serial_init(); |
| 390 | omap_register_i2c_bus(1, 100, NULL, 0); | 390 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 391 | omap_usb_init(&sx1_usb_config); | ||
| 391 | sx1_mmc_init(); | 392 | sx1_mmc_init(); |
| 392 | 393 | ||
| 393 | /* turn on USB power */ | 394 | /* turn on USB power */ |
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c index a7653542a2b0..98275e03dad1 100644 --- a/arch/arm/mach-omap1/board-voiceblue.c +++ b/arch/arm/mach-omap1/board-voiceblue.c | |||
| @@ -145,7 +145,6 @@ static struct omap_uart_config voiceblue_uart_config __initdata = { | |||
| 145 | }; | 145 | }; |
| 146 | 146 | ||
| 147 | static struct omap_board_config_kernel voiceblue_config[] = { | 147 | static struct omap_board_config_kernel voiceblue_config[] = { |
| 148 | { OMAP_TAG_USB, &voiceblue_usb_config }, | ||
| 149 | { OMAP_TAG_UART, &voiceblue_uart_config }, | 148 | { OMAP_TAG_UART, &voiceblue_uart_config }, |
| 150 | }; | 149 | }; |
| 151 | 150 | ||
| @@ -185,6 +184,7 @@ static void __init voiceblue_init(void) | |||
| 185 | omap_board_config = voiceblue_config; | 184 | omap_board_config = voiceblue_config; |
| 186 | omap_board_config_size = ARRAY_SIZE(voiceblue_config); | 185 | omap_board_config_size = ARRAY_SIZE(voiceblue_config); |
| 187 | omap_serial_init(); | 186 | omap_serial_init(); |
| 187 | omap_usb_init(&voiceblue_usb_config); | ||
| 188 | omap_register_i2c_bus(1, 100, NULL, 0); | 188 | omap_register_i2c_bus(1, 100, NULL, 0); |
| 189 | 189 | ||
| 190 | /* There is a good chance board is going up, so enable power LED | 190 | /* There is a good chance board is going up, so enable power LED |
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 5fba20731710..dafe4f71d15f 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c | |||
| @@ -20,41 +20,161 @@ | |||
| 20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
| 21 | 21 | ||
| 22 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
| 23 | #include <asm/clkdev.h> | ||
| 23 | 24 | ||
| 24 | #include <mach/cpu.h> | 25 | #include <mach/cpu.h> |
| 25 | #include <mach/usb.h> | 26 | #include <mach/usb.h> |
| 26 | #include <mach/clock.h> | 27 | #include <mach/clock.h> |
| 27 | #include <mach/sram.h> | 28 | #include <mach/sram.h> |
| 28 | 29 | ||
| 30 | static const struct clkops clkops_generic; | ||
| 31 | static const struct clkops clkops_uart; | ||
| 32 | static const struct clkops clkops_dspck; | ||
| 33 | |||
| 29 | #include "clock.h" | 34 | #include "clock.h" |
| 30 | 35 | ||
| 36 | static int clk_omap1_dummy_enable(struct clk *clk) | ||
| 37 | { | ||
| 38 | return 0; | ||
| 39 | } | ||
| 40 | |||
| 41 | static void clk_omap1_dummy_disable(struct clk *clk) | ||
| 42 | { | ||
| 43 | } | ||
| 44 | |||
| 45 | static const struct clkops clkops_dummy = { | ||
| 46 | .enable = clk_omap1_dummy_enable, | ||
| 47 | .disable = clk_omap1_dummy_disable, | ||
| 48 | }; | ||
| 49 | |||
| 50 | static struct clk dummy_ck = { | ||
| 51 | .name = "dummy", | ||
| 52 | .ops = &clkops_dummy, | ||
| 53 | .flags = RATE_FIXED, | ||
| 54 | }; | ||
| 55 | |||
| 56 | struct omap_clk { | ||
| 57 | u32 cpu; | ||
| 58 | struct clk_lookup lk; | ||
| 59 | }; | ||
| 60 | |||
| 61 | #define CLK(dev, con, ck, cp) \ | ||
| 62 | { \ | ||
| 63 | .cpu = cp, \ | ||
| 64 | .lk = { \ | ||
| 65 | .dev_id = dev, \ | ||
| 66 | .con_id = con, \ | ||
| 67 | .clk = ck, \ | ||
| 68 | }, \ | ||
| 69 | } | ||
| 70 | |||
| 71 | #define CK_310 (1 << 0) | ||
| 72 | #define CK_730 (1 << 1) | ||
| 73 | #define CK_1510 (1 << 2) | ||
| 74 | #define CK_16XX (1 << 3) | ||
| 75 | |||
| 76 | static struct omap_clk omap_clks[] = { | ||
| 77 | /* non-ULPD clocks */ | ||
| 78 | CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310), | ||
| 79 | CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310), | ||
| 80 | /* CK_GEN1 clocks */ | ||
| 81 | CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), | ||
| 82 | CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), | ||
| 83 | CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), | ||
| 84 | CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
| 85 | CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), | ||
| 86 | CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
| 87 | CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
| 88 | CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
| 89 | CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), | ||
| 90 | CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), | ||
| 91 | CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), | ||
| 92 | CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), | ||
| 93 | /* CK_GEN2 clocks */ | ||
| 94 | CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), | ||
| 95 | CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), | ||
| 96 | CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), | ||
| 97 | CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
| 98 | CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), | ||
| 99 | /* CK_GEN3 clocks */ | ||
| 100 | CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_730), | ||
| 101 | CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), | ||
| 102 | CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX), | ||
| 103 | CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), | ||
| 104 | CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), | ||
| 105 | CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), | ||
| 106 | CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), | ||
| 107 | CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
| 108 | CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), | ||
| 109 | CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), | ||
| 110 | CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), | ||
| 111 | CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_730), | ||
| 112 | CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), | ||
| 113 | /* ULPD clocks */ | ||
| 114 | CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), | ||
| 115 | CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), | ||
| 116 | CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), | ||
| 117 | CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), | ||
| 118 | CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), | ||
| 119 | CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), | ||
| 120 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), | ||
| 121 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), | ||
| 122 | CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), | ||
| 123 | CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), | ||
| 124 | CLK(NULL, "mclk", &mclk_16xx, CK_16XX), | ||
| 125 | CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), | ||
| 126 | CLK(NULL, "bclk", &bclk_16xx, CK_16XX), | ||
| 127 | CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), | ||
| 128 | CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
| 129 | CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), | ||
| 130 | CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), | ||
| 131 | /* Virtual clocks */ | ||
| 132 | CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), | ||
| 133 | CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310), | ||
| 134 | CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX), | ||
| 135 | CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310), | ||
| 136 | CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
| 137 | CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), | ||
| 138 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), | ||
| 139 | CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), | ||
| 140 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), | ||
| 141 | CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), | ||
| 142 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), | ||
| 143 | CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
| 144 | CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
| 145 | CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
| 146 | }; | ||
| 147 | |||
| 148 | static int omap1_clk_enable_generic(struct clk * clk); | ||
| 149 | static int omap1_clk_enable(struct clk *clk); | ||
| 150 | static void omap1_clk_disable_generic(struct clk * clk); | ||
| 151 | static void omap1_clk_disable(struct clk *clk); | ||
| 152 | |||
| 31 | __u32 arm_idlect1_mask; | 153 | __u32 arm_idlect1_mask; |
| 32 | 154 | ||
| 33 | /*------------------------------------------------------------------------- | 155 | /*------------------------------------------------------------------------- |
| 34 | * Omap1 specific clock functions | 156 | * Omap1 specific clock functions |
| 35 | *-------------------------------------------------------------------------*/ | 157 | *-------------------------------------------------------------------------*/ |
| 36 | 158 | ||
| 37 | static void omap1_watchdog_recalc(struct clk * clk) | 159 | static unsigned long omap1_watchdog_recalc(struct clk *clk) |
| 38 | { | 160 | { |
| 39 | clk->rate = clk->parent->rate / 14; | 161 | return clk->parent->rate / 14; |
| 40 | } | 162 | } |
| 41 | 163 | ||
| 42 | static void omap1_uart_recalc(struct clk * clk) | 164 | static unsigned long omap1_uart_recalc(struct clk *clk) |
| 43 | { | 165 | { |
| 44 | unsigned int val = omap_readl(clk->enable_reg); | 166 | unsigned int val = __raw_readl(clk->enable_reg); |
| 45 | if (val & clk->enable_bit) | 167 | return val & clk->enable_bit ? 48000000 : 12000000; |
| 46 | clk->rate = 48000000; | ||
| 47 | else | ||
| 48 | clk->rate = 12000000; | ||
| 49 | } | 168 | } |
| 50 | 169 | ||
| 51 | static void omap1_sossi_recalc(struct clk *clk) | 170 | static unsigned long omap1_sossi_recalc(struct clk *clk) |
| 52 | { | 171 | { |
| 53 | u32 div = omap_readl(MOD_CONF_CTRL_1); | 172 | u32 div = omap_readl(MOD_CONF_CTRL_1); |
| 54 | 173 | ||
| 55 | div = (div >> 17) & 0x7; | 174 | div = (div >> 17) & 0x7; |
| 56 | div++; | 175 | div++; |
| 57 | clk->rate = clk->parent->rate / div; | 176 | |
| 177 | return clk->parent->rate / div; | ||
| 58 | } | 178 | } |
| 59 | 179 | ||
| 60 | static int omap1_clk_enable_dsp_domain(struct clk *clk) | 180 | static int omap1_clk_enable_dsp_domain(struct clk *clk) |
| @@ -78,6 +198,11 @@ static void omap1_clk_disable_dsp_domain(struct clk *clk) | |||
| 78 | } | 198 | } |
| 79 | } | 199 | } |
| 80 | 200 | ||
| 201 | static const struct clkops clkops_dspck = { | ||
| 202 | .enable = &omap1_clk_enable_dsp_domain, | ||
| 203 | .disable = &omap1_clk_disable_dsp_domain, | ||
| 204 | }; | ||
| 205 | |||
| 81 | static int omap1_clk_enable_uart_functional(struct clk *clk) | 206 | static int omap1_clk_enable_uart_functional(struct clk *clk) |
| 82 | { | 207 | { |
| 83 | int ret; | 208 | int ret; |
| @@ -105,6 +230,11 @@ static void omap1_clk_disable_uart_functional(struct clk *clk) | |||
| 105 | omap1_clk_disable_generic(clk); | 230 | omap1_clk_disable_generic(clk); |
| 106 | } | 231 | } |
| 107 | 232 | ||
| 233 | static const struct clkops clkops_uart = { | ||
| 234 | .enable = &omap1_clk_enable_uart_functional, | ||
| 235 | .disable = &omap1_clk_disable_uart_functional, | ||
| 236 | }; | ||
| 237 | |||
| 108 | static void omap1_clk_allow_idle(struct clk *clk) | 238 | static void omap1_clk_allow_idle(struct clk *clk) |
| 109 | { | 239 | { |
| 110 | struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; | 240 | struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; |
| @@ -197,9 +327,6 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate) | |||
| 197 | struct clk * parent; | 327 | struct clk * parent; |
| 198 | unsigned dsor_exp; | 328 | unsigned dsor_exp; |
| 199 | 329 | ||
| 200 | if (unlikely(!(clk->flags & RATE_CKCTL))) | ||
| 201 | return -EINVAL; | ||
| 202 | |||
| 203 | parent = clk->parent; | 330 | parent = clk->parent; |
| 204 | if (unlikely(parent == NULL)) | 331 | if (unlikely(parent == NULL)) |
| 205 | return -EIO; | 332 | return -EIO; |
| @@ -215,22 +342,15 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate) | |||
| 215 | return dsor_exp; | 342 | return dsor_exp; |
| 216 | } | 343 | } |
| 217 | 344 | ||
| 218 | static void omap1_ckctl_recalc(struct clk * clk) | 345 | static unsigned long omap1_ckctl_recalc(struct clk *clk) |
| 219 | { | 346 | { |
| 220 | int dsor; | ||
| 221 | |||
| 222 | /* Calculate divisor encoded as 2-bit exponent */ | 347 | /* Calculate divisor encoded as 2-bit exponent */ |
| 223 | dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); | 348 | int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); |
| 224 | 349 | ||
| 225 | if (unlikely(clk->rate == clk->parent->rate / dsor)) | 350 | return clk->parent->rate / dsor; |
| 226 | return; /* No change, quick exit */ | ||
| 227 | clk->rate = clk->parent->rate / dsor; | ||
| 228 | |||
| 229 | if (unlikely(clk->flags & RATE_PROPAGATES)) | ||
| 230 | propagate_rate(clk); | ||
| 231 | } | 351 | } |
| 232 | 352 | ||
| 233 | static void omap1_ckctl_recalc_dsp_domain(struct clk * clk) | 353 | static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) |
| 234 | { | 354 | { |
| 235 | int dsor; | 355 | int dsor; |
| 236 | 356 | ||
| @@ -245,12 +365,7 @@ static void omap1_ckctl_recalc_dsp_domain(struct clk * clk) | |||
| 245 | dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); | 365 | dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); |
| 246 | omap1_clk_disable(&api_ck.clk); | 366 | omap1_clk_disable(&api_ck.clk); |
| 247 | 367 | ||
| 248 | if (unlikely(clk->rate == clk->parent->rate / dsor)) | 368 | return clk->parent->rate / dsor; |
| 249 | return; /* No change, quick exit */ | ||
| 250 | clk->rate = clk->parent->rate / dsor; | ||
| 251 | |||
| 252 | if (unlikely(clk->flags & RATE_PROPAGATES)) | ||
| 253 | propagate_rate(clk); | ||
| 254 | } | 369 | } |
| 255 | 370 | ||
| 256 | /* MPU virtual clock functions */ | 371 | /* MPU virtual clock functions */ |
| @@ -289,35 +404,57 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate) | |||
| 289 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); | 404 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); |
| 290 | 405 | ||
| 291 | ck_dpll1.rate = ptr->pll_rate; | 406 | ck_dpll1.rate = ptr->pll_rate; |
| 292 | propagate_rate(&ck_dpll1); | ||
| 293 | return 0; | 407 | return 0; |
| 294 | } | 408 | } |
| 295 | 409 | ||
| 296 | static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) | 410 | static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) |
| 297 | { | 411 | { |
| 298 | int ret = -EINVAL; | 412 | int dsor_exp; |
| 299 | int dsor_exp; | 413 | u16 regval; |
| 300 | __u16 regval; | ||
| 301 | |||
| 302 | if (clk->flags & RATE_CKCTL) { | ||
| 303 | dsor_exp = calc_dsor_exp(clk, rate); | ||
| 304 | if (dsor_exp > 3) | ||
| 305 | dsor_exp = -EINVAL; | ||
| 306 | if (dsor_exp < 0) | ||
| 307 | return dsor_exp; | ||
| 308 | |||
| 309 | regval = __raw_readw(DSP_CKCTL); | ||
| 310 | regval &= ~(3 << clk->rate_offset); | ||
| 311 | regval |= dsor_exp << clk->rate_offset; | ||
| 312 | __raw_writew(regval, DSP_CKCTL); | ||
| 313 | clk->rate = clk->parent->rate / (1 << dsor_exp); | ||
| 314 | ret = 0; | ||
| 315 | } | ||
| 316 | 414 | ||
| 317 | if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) | 415 | dsor_exp = calc_dsor_exp(clk, rate); |
| 318 | propagate_rate(clk); | 416 | if (dsor_exp > 3) |
| 417 | dsor_exp = -EINVAL; | ||
| 418 | if (dsor_exp < 0) | ||
| 419 | return dsor_exp; | ||
| 319 | 420 | ||
| 320 | return ret; | 421 | regval = __raw_readw(DSP_CKCTL); |
| 422 | regval &= ~(3 << clk->rate_offset); | ||
| 423 | regval |= dsor_exp << clk->rate_offset; | ||
| 424 | __raw_writew(regval, DSP_CKCTL); | ||
| 425 | clk->rate = clk->parent->rate / (1 << dsor_exp); | ||
| 426 | |||
| 427 | return 0; | ||
| 428 | } | ||
| 429 | |||
| 430 | static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) | ||
| 431 | { | ||
| 432 | int dsor_exp = calc_dsor_exp(clk, rate); | ||
| 433 | if (dsor_exp < 0) | ||
| 434 | return dsor_exp; | ||
| 435 | if (dsor_exp > 3) | ||
| 436 | dsor_exp = 3; | ||
| 437 | return clk->parent->rate / (1 << dsor_exp); | ||
| 438 | } | ||
| 439 | |||
| 440 | static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) | ||
| 441 | { | ||
| 442 | int dsor_exp; | ||
| 443 | u16 regval; | ||
| 444 | |||
| 445 | dsor_exp = calc_dsor_exp(clk, rate); | ||
| 446 | if (dsor_exp > 3) | ||
| 447 | dsor_exp = -EINVAL; | ||
| 448 | if (dsor_exp < 0) | ||
| 449 | return dsor_exp; | ||
| 450 | |||
| 451 | regval = omap_readw(ARM_CKCTL); | ||
| 452 | regval &= ~(3 << clk->rate_offset); | ||
| 453 | regval |= dsor_exp << clk->rate_offset; | ||
| 454 | regval = verify_ckctl_value(regval); | ||
| 455 | omap_writew(regval, ARM_CKCTL); | ||
| 456 | clk->rate = clk->parent->rate / (1 << dsor_exp); | ||
| 457 | return 0; | ||
| 321 | } | 458 | } |
| 322 | 459 | ||
| 323 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate) | 460 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate) |
| @@ -372,14 +509,14 @@ static int omap1_set_uart_rate(struct clk * clk, unsigned long rate) | |||
| 372 | { | 509 | { |
| 373 | unsigned int val; | 510 | unsigned int val; |
| 374 | 511 | ||
| 375 | val = omap_readl(clk->enable_reg); | 512 | val = __raw_readl(clk->enable_reg); |
| 376 | if (rate == 12000000) | 513 | if (rate == 12000000) |
| 377 | val &= ~(1 << clk->enable_bit); | 514 | val &= ~(1 << clk->enable_bit); |
| 378 | else if (rate == 48000000) | 515 | else if (rate == 48000000) |
| 379 | val |= (1 << clk->enable_bit); | 516 | val |= (1 << clk->enable_bit); |
| 380 | else | 517 | else |
| 381 | return -EINVAL; | 518 | return -EINVAL; |
| 382 | omap_writel(val, clk->enable_reg); | 519 | __raw_writel(val, clk->enable_reg); |
| 383 | clk->rate = rate; | 520 | clk->rate = rate; |
| 384 | 521 | ||
| 385 | return 0; | 522 | return 0; |
| @@ -398,8 +535,8 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) | |||
| 398 | else | 535 | else |
| 399 | ratio_bits = (dsor - 2) << 2; | 536 | ratio_bits = (dsor - 2) << 2; |
| 400 | 537 | ||
| 401 | ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd; | 538 | ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd; |
| 402 | omap_writew(ratio_bits, clk->enable_reg); | 539 | __raw_writew(ratio_bits, clk->enable_reg); |
| 403 | 540 | ||
| 404 | return 0; | 541 | return 0; |
| 405 | } | 542 | } |
| @@ -423,8 +560,6 @@ static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) | |||
| 423 | omap_writel(l, MOD_CONF_CTRL_1); | 560 | omap_writel(l, MOD_CONF_CTRL_1); |
| 424 | 561 | ||
| 425 | clk->rate = p_rate / (div + 1); | 562 | clk->rate = p_rate / (div + 1); |
| 426 | if (unlikely(clk->flags & RATE_PROPAGATES)) | ||
| 427 | propagate_rate(clk); | ||
| 428 | 563 | ||
| 429 | return 0; | 564 | return 0; |
| 430 | } | 565 | } |
| @@ -440,8 +575,8 @@ static void omap1_init_ext_clk(struct clk * clk) | |||
| 440 | __u16 ratio_bits; | 575 | __u16 ratio_bits; |
| 441 | 576 | ||
| 442 | /* Determine current rate and ensure clock is based on 96MHz APLL */ | 577 | /* Determine current rate and ensure clock is based on 96MHz APLL */ |
| 443 | ratio_bits = omap_readw(clk->enable_reg) & ~1; | 578 | ratio_bits = __raw_readw(clk->enable_reg) & ~1; |
| 444 | omap_writew(ratio_bits, clk->enable_reg); | 579 | __raw_writew(ratio_bits, clk->enable_reg); |
| 445 | 580 | ||
| 446 | ratio_bits = (ratio_bits & 0xfc) >> 2; | 581 | ratio_bits = (ratio_bits & 0xfc) >> 2; |
| 447 | if (ratio_bits > 6) | 582 | if (ratio_bits > 6) |
| @@ -468,7 +603,7 @@ static int omap1_clk_enable(struct clk *clk) | |||
| 468 | omap1_clk_deny_idle(clk->parent); | 603 | omap1_clk_deny_idle(clk->parent); |
| 469 | } | 604 | } |
| 470 | 605 | ||
| 471 | ret = clk->enable(clk); | 606 | ret = clk->ops->enable(clk); |
| 472 | 607 | ||
| 473 | if (unlikely(ret != 0) && clk->parent) { | 608 | if (unlikely(ret != 0) && clk->parent) { |
| 474 | omap1_clk_disable(clk->parent); | 609 | omap1_clk_disable(clk->parent); |
| @@ -482,7 +617,7 @@ static int omap1_clk_enable(struct clk *clk) | |||
| 482 | static void omap1_clk_disable(struct clk *clk) | 617 | static void omap1_clk_disable(struct clk *clk) |
| 483 | { | 618 | { |
| 484 | if (clk->usecount > 0 && !(--clk->usecount)) { | 619 | if (clk->usecount > 0 && !(--clk->usecount)) { |
| 485 | clk->disable(clk); | 620 | clk->ops->disable(clk); |
| 486 | if (likely(clk->parent)) { | 621 | if (likely(clk->parent)) { |
| 487 | omap1_clk_disable(clk->parent); | 622 | omap1_clk_disable(clk->parent); |
| 488 | if (clk->flags & CLOCK_NO_IDLE_PARENT) | 623 | if (clk->flags & CLOCK_NO_IDLE_PARENT) |
| @@ -496,9 +631,6 @@ static int omap1_clk_enable_generic(struct clk *clk) | |||
| 496 | __u16 regval16; | 631 | __u16 regval16; |
| 497 | __u32 regval32; | 632 | __u32 regval32; |
| 498 | 633 | ||
| 499 | if (clk->flags & ALWAYS_ENABLED) | ||
| 500 | return 0; | ||
| 501 | |||
| 502 | if (unlikely(clk->enable_reg == NULL)) { | 634 | if (unlikely(clk->enable_reg == NULL)) { |
| 503 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", | 635 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", |
| 504 | clk->name); | 636 | clk->name); |
| @@ -506,25 +638,13 @@ static int omap1_clk_enable_generic(struct clk *clk) | |||
| 506 | } | 638 | } |
| 507 | 639 | ||
| 508 | if (clk->flags & ENABLE_REG_32BIT) { | 640 | if (clk->flags & ENABLE_REG_32BIT) { |
| 509 | if (clk->flags & VIRTUAL_IO_ADDRESS) { | 641 | regval32 = __raw_readl(clk->enable_reg); |
| 510 | regval32 = __raw_readl(clk->enable_reg); | 642 | regval32 |= (1 << clk->enable_bit); |
| 511 | regval32 |= (1 << clk->enable_bit); | 643 | __raw_writel(regval32, clk->enable_reg); |
| 512 | __raw_writel(regval32, clk->enable_reg); | ||
| 513 | } else { | ||
| 514 | regval32 = omap_readl(clk->enable_reg); | ||
| 515 | regval32 |= (1 << clk->enable_bit); | ||
| 516 | omap_writel(regval32, clk->enable_reg); | ||
| 517 | } | ||
| 518 | } else { | 644 | } else { |
| 519 | if (clk->flags & VIRTUAL_IO_ADDRESS) { | 645 | regval16 = __raw_readw(clk->enable_reg); |
| 520 | regval16 = __raw_readw(clk->enable_reg); | 646 | regval16 |= (1 << clk->enable_bit); |
| 521 | regval16 |= (1 << clk->enable_bit); | 647 | __raw_writew(regval16, clk->enable_reg); |
| 522 | __raw_writew(regval16, clk->enable_reg); | ||
| 523 | } else { | ||
| 524 | regval16 = omap_readw(clk->enable_reg); | ||
| 525 | regval16 |= (1 << clk->enable_bit); | ||
| 526 | omap_writew(regval16, clk->enable_reg); | ||
| 527 | } | ||
| 528 | } | 648 | } |
| 529 | 649 | ||
| 530 | return 0; | 650 | return 0; |
| @@ -539,44 +659,26 @@ static void omap1_clk_disable_generic(struct clk *clk) | |||
| 539 | return; | 659 | return; |
| 540 | 660 | ||
| 541 | if (clk->flags & ENABLE_REG_32BIT) { | 661 | if (clk->flags & ENABLE_REG_32BIT) { |
| 542 | if (clk->flags & VIRTUAL_IO_ADDRESS) { | 662 | regval32 = __raw_readl(clk->enable_reg); |
| 543 | regval32 = __raw_readl(clk->enable_reg); | 663 | regval32 &= ~(1 << clk->enable_bit); |
| 544 | regval32 &= ~(1 << clk->enable_bit); | 664 | __raw_writel(regval32, clk->enable_reg); |
| 545 | __raw_writel(regval32, clk->enable_reg); | ||
| 546 | } else { | ||
| 547 | regval32 = omap_readl(clk->enable_reg); | ||
| 548 | regval32 &= ~(1 << clk->enable_bit); | ||
| 549 | omap_writel(regval32, clk->enable_reg); | ||
| 550 | } | ||
| 551 | } else { | 665 | } else { |
| 552 | if (clk->flags & VIRTUAL_IO_ADDRESS) { | 666 | regval16 = __raw_readw(clk->enable_reg); |
| 553 | regval16 = __raw_readw(clk->enable_reg); | 667 | regval16 &= ~(1 << clk->enable_bit); |
| 554 | regval16 &= ~(1 << clk->enable_bit); | 668 | __raw_writew(regval16, clk->enable_reg); |
| 555 | __raw_writew(regval16, clk->enable_reg); | ||
| 556 | } else { | ||
| 557 | regval16 = omap_readw(clk->enable_reg); | ||
| 558 | regval16 &= ~(1 << clk->enable_bit); | ||
| 559 | omap_writew(regval16, clk->enable_reg); | ||
| 560 | } | ||
| 561 | } | 669 | } |
| 562 | } | 670 | } |
| 563 | 671 | ||
| 672 | static const struct clkops clkops_generic = { | ||
| 673 | .enable = &omap1_clk_enable_generic, | ||
| 674 | .disable = &omap1_clk_disable_generic, | ||
| 675 | }; | ||
| 676 | |||
| 564 | static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) | 677 | static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) |
| 565 | { | 678 | { |
| 566 | int dsor_exp; | ||
| 567 | |||
| 568 | if (clk->flags & RATE_FIXED) | 679 | if (clk->flags & RATE_FIXED) |
| 569 | return clk->rate; | 680 | return clk->rate; |
| 570 | 681 | ||
| 571 | if (clk->flags & RATE_CKCTL) { | ||
| 572 | dsor_exp = calc_dsor_exp(clk, rate); | ||
| 573 | if (dsor_exp < 0) | ||
| 574 | return dsor_exp; | ||
| 575 | if (dsor_exp > 3) | ||
| 576 | dsor_exp = 3; | ||
| 577 | return clk->parent->rate / (1 << dsor_exp); | ||
| 578 | } | ||
| 579 | |||
| 580 | if (clk->round_rate != NULL) | 682 | if (clk->round_rate != NULL) |
| 581 | return clk->round_rate(clk, rate); | 683 | return clk->round_rate(clk, rate); |
| 582 | 684 | ||
| @@ -586,30 +688,9 @@ static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) | |||
| 586 | static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) | 688 | static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) |
| 587 | { | 689 | { |
| 588 | int ret = -EINVAL; | 690 | int ret = -EINVAL; |
| 589 | int dsor_exp; | ||
| 590 | __u16 regval; | ||
| 591 | 691 | ||
| 592 | if (clk->set_rate) | 692 | if (clk->set_rate) |
| 593 | ret = clk->set_rate(clk, rate); | 693 | ret = clk->set_rate(clk, rate); |
| 594 | else if (clk->flags & RATE_CKCTL) { | ||
| 595 | dsor_exp = calc_dsor_exp(clk, rate); | ||
| 596 | if (dsor_exp > 3) | ||
| 597 | dsor_exp = -EINVAL; | ||
| 598 | if (dsor_exp < 0) | ||
| 599 | return dsor_exp; | ||
| 600 | |||
| 601 | regval = omap_readw(ARM_CKCTL); | ||
| 602 | regval &= ~(3 << clk->rate_offset); | ||
| 603 | regval |= dsor_exp << clk->rate_offset; | ||
| 604 | regval = verify_ckctl_value(regval); | ||
| 605 | omap_writew(regval, ARM_CKCTL); | ||
| 606 | clk->rate = clk->parent->rate / (1 << dsor_exp); | ||
| 607 | ret = 0; | ||
| 608 | } | ||
| 609 | |||
| 610 | if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) | ||
| 611 | propagate_rate(clk); | ||
| 612 | |||
| 613 | return ret; | 694 | return ret; |
| 614 | } | 695 | } |
| 615 | 696 | ||
| @@ -632,17 +713,10 @@ static void __init omap1_clk_disable_unused(struct clk *clk) | |||
| 632 | } | 713 | } |
| 633 | 714 | ||
| 634 | /* Is the clock already disabled? */ | 715 | /* Is the clock already disabled? */ |
| 635 | if (clk->flags & ENABLE_REG_32BIT) { | 716 | if (clk->flags & ENABLE_REG_32BIT) |
| 636 | if (clk->flags & VIRTUAL_IO_ADDRESS) | 717 | regval32 = __raw_readl(clk->enable_reg); |
| 637 | regval32 = __raw_readl(clk->enable_reg); | 718 | else |
| 638 | else | 719 | regval32 = __raw_readw(clk->enable_reg); |
| 639 | regval32 = omap_readl(clk->enable_reg); | ||
| 640 | } else { | ||
| 641 | if (clk->flags & VIRTUAL_IO_ADDRESS) | ||
| 642 | regval32 = __raw_readw(clk->enable_reg); | ||
| 643 | else | ||
| 644 | regval32 = omap_readw(clk->enable_reg); | ||
| 645 | } | ||
| 646 | 720 | ||
| 647 | if ((regval32 & (1 << clk->enable_bit)) == 0) | 721 | if ((regval32 & (1 << clk->enable_bit)) == 0) |
| 648 | return; | 722 | return; |
| @@ -659,7 +733,7 @@ static void __init omap1_clk_disable_unused(struct clk *clk) | |||
| 659 | } | 733 | } |
| 660 | 734 | ||
| 661 | printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); | 735 | printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); |
| 662 | clk->disable(clk); | 736 | clk->ops->disable(clk); |
| 663 | printk(" done\n"); | 737 | printk(" done\n"); |
| 664 | } | 738 | } |
| 665 | 739 | ||
| @@ -677,10 +751,10 @@ static struct clk_functions omap1_clk_functions = { | |||
| 677 | 751 | ||
| 678 | int __init omap1_clk_init(void) | 752 | int __init omap1_clk_init(void) |
| 679 | { | 753 | { |
| 680 | struct clk ** clkp; | 754 | struct omap_clk *c; |
| 681 | const struct omap_clock_config *info; | 755 | const struct omap_clock_config *info; |
| 682 | int crystal_type = 0; /* Default 12 MHz */ | 756 | int crystal_type = 0; /* Default 12 MHz */ |
| 683 | u32 reg; | 757 | u32 reg, cpu_mask; |
| 684 | 758 | ||
| 685 | #ifdef CONFIG_DEBUG_LL | 759 | #ifdef CONFIG_DEBUG_LL |
| 686 | /* Resets some clocks that may be left on from bootloader, | 760 | /* Resets some clocks that may be left on from bootloader, |
| @@ -700,27 +774,24 @@ int __init omap1_clk_init(void) | |||
| 700 | /* By default all idlect1 clocks are allowed to idle */ | 774 | /* By default all idlect1 clocks are allowed to idle */ |
| 701 | arm_idlect1_mask = ~0; | 775 | arm_idlect1_mask = ~0; |
| 702 | 776 | ||
| 703 | for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) { | 777 | for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) |
| 704 | if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) { | 778 | clk_init_one(c->lk.clk); |
| 705 | clk_register(*clkp); | ||
| 706 | continue; | ||
| 707 | } | ||
| 708 | |||
| 709 | if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) { | ||
| 710 | clk_register(*clkp); | ||
| 711 | continue; | ||
| 712 | } | ||
| 713 | |||
| 714 | if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) { | ||
| 715 | clk_register(*clkp); | ||
| 716 | continue; | ||
| 717 | } | ||
| 718 | 779 | ||
| 719 | if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) { | 780 | cpu_mask = 0; |
| 720 | clk_register(*clkp); | 781 | if (cpu_is_omap16xx()) |
| 721 | continue; | 782 | cpu_mask |= CK_16XX; |
| 783 | if (cpu_is_omap1510()) | ||
| 784 | cpu_mask |= CK_1510; | ||
| 785 | if (cpu_is_omap730()) | ||
| 786 | cpu_mask |= CK_730; | ||
| 787 | if (cpu_is_omap310()) | ||
| 788 | cpu_mask |= CK_310; | ||
| 789 | |||
| 790 | for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) | ||
| 791 | if (c->cpu & cpu_mask) { | ||
| 792 | clkdev_add(&c->lk); | ||
| 793 | clk_register(c->lk.clk); | ||
| 722 | } | 794 | } |
| 723 | } | ||
| 724 | 795 | ||
| 725 | info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); | 796 | info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); |
| 726 | if (info != NULL) { | 797 | if (info != NULL) { |
| @@ -769,7 +840,6 @@ int __init omap1_clk_init(void) | |||
| 769 | } | 840 | } |
| 770 | } | 841 | } |
| 771 | } | 842 | } |
| 772 | propagate_rate(&ck_dpll1); | ||
| 773 | #else | 843 | #else |
| 774 | /* Find the highest supported frequency and enable it */ | 844 | /* Find the highest supported frequency and enable it */ |
| 775 | if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { | 845 | if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { |
| @@ -778,9 +848,9 @@ int __init omap1_clk_init(void) | |||
| 778 | omap_writew(0x2290, DPLL_CTL); | 848 | omap_writew(0x2290, DPLL_CTL); |
| 779 | omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); | 849 | omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); |
| 780 | ck_dpll1.rate = 60000000; | 850 | ck_dpll1.rate = 60000000; |
| 781 | propagate_rate(&ck_dpll1); | ||
| 782 | } | 851 | } |
| 783 | #endif | 852 | #endif |
| 853 | propagate_rate(&ck_dpll1); | ||
| 784 | /* Cache rates for clocks connected to ck_ref (not dpll1) */ | 854 | /* Cache rates for clocks connected to ck_ref (not dpll1) */ |
| 785 | propagate_rate(&ck_ref); | 855 | propagate_rate(&ck_ref); |
| 786 | printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " | 856 | printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " |
| @@ -832,4 +902,3 @@ int __init omap1_clk_init(void) | |||
| 832 | 902 | ||
| 833 | return 0; | 903 | return 0; |
| 834 | } | 904 | } |
| 835 | |||
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index c1dcdf18d8dd..17f874271255 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h | |||
| @@ -13,27 +13,22 @@ | |||
| 13 | #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H | 13 | #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H |
| 14 | #define __ARCH_ARM_MACH_OMAP1_CLOCK_H | 14 | #define __ARCH_ARM_MACH_OMAP1_CLOCK_H |
| 15 | 15 | ||
| 16 | static int omap1_clk_enable_generic(struct clk * clk); | 16 | static unsigned long omap1_ckctl_recalc(struct clk *clk); |
| 17 | static void omap1_clk_disable_generic(struct clk * clk); | 17 | static unsigned long omap1_watchdog_recalc(struct clk *clk); |
| 18 | static void omap1_ckctl_recalc(struct clk * clk); | ||
| 19 | static void omap1_watchdog_recalc(struct clk * clk); | ||
| 20 | static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); | 18 | static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); |
| 21 | static void omap1_sossi_recalc(struct clk *clk); | 19 | static unsigned long omap1_sossi_recalc(struct clk *clk); |
| 22 | static void omap1_ckctl_recalc_dsp_domain(struct clk * clk); | 20 | static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); |
| 23 | static int omap1_clk_enable_dsp_domain(struct clk * clk); | ||
| 24 | static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); | 21 | static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); |
| 25 | static void omap1_clk_disable_dsp_domain(struct clk * clk); | ||
| 26 | static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); | 22 | static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); |
| 27 | static void omap1_uart_recalc(struct clk * clk); | 23 | static unsigned long omap1_uart_recalc(struct clk *clk); |
| 28 | static int omap1_clk_enable_uart_functional(struct clk * clk); | ||
| 29 | static void omap1_clk_disable_uart_functional(struct clk * clk); | ||
| 30 | static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); | 24 | static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); |
| 31 | static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); | 25 | static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); |
| 32 | static void omap1_init_ext_clk(struct clk * clk); | 26 | static void omap1_init_ext_clk(struct clk * clk); |
| 33 | static int omap1_select_table_rate(struct clk * clk, unsigned long rate); | 27 | static int omap1_select_table_rate(struct clk * clk, unsigned long rate); |
| 34 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); | 28 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); |
| 35 | static int omap1_clk_enable(struct clk *clk); | 29 | |
| 36 | static void omap1_clk_disable(struct clk *clk); | 30 | static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); |
| 31 | static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); | ||
| 37 | 32 | ||
| 38 | struct mpu_rate { | 33 | struct mpu_rate { |
| 39 | unsigned long rate; | 34 | unsigned long rate; |
| @@ -152,101 +147,84 @@ static struct mpu_rate rate_table[] = { | |||
| 152 | 147 | ||
| 153 | static struct clk ck_ref = { | 148 | static struct clk ck_ref = { |
| 154 | .name = "ck_ref", | 149 | .name = "ck_ref", |
| 150 | .ops = &clkops_null, | ||
| 155 | .rate = 12000000, | 151 | .rate = 12000000, |
| 156 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | ||
| 157 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, | ||
| 158 | .enable = &omap1_clk_enable_generic, | ||
| 159 | .disable = &omap1_clk_disable_generic, | ||
| 160 | }; | 152 | }; |
| 161 | 153 | ||
| 162 | static struct clk ck_dpll1 = { | 154 | static struct clk ck_dpll1 = { |
| 163 | .name = "ck_dpll1", | 155 | .name = "ck_dpll1", |
| 156 | .ops = &clkops_null, | ||
| 164 | .parent = &ck_ref, | 157 | .parent = &ck_ref, |
| 165 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | ||
| 166 | CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 167 | .enable = &omap1_clk_enable_generic, | ||
| 168 | .disable = &omap1_clk_disable_generic, | ||
| 169 | }; | 158 | }; |
| 170 | 159 | ||
| 171 | static struct arm_idlect1_clk ck_dpll1out = { | 160 | static struct arm_idlect1_clk ck_dpll1out = { |
| 172 | .clk = { | 161 | .clk = { |
| 173 | .name = "ck_dpll1out", | 162 | .name = "ck_dpll1out", |
| 163 | .ops = &clkops_generic, | ||
| 174 | .parent = &ck_dpll1, | 164 | .parent = &ck_dpll1, |
| 175 | .flags = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL | | 165 | .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT, |
| 176 | ENABLE_REG_32BIT | RATE_PROPAGATES, | 166 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 177 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 178 | .enable_bit = EN_CKOUT_ARM, | 167 | .enable_bit = EN_CKOUT_ARM, |
| 179 | .recalc = &followparent_recalc, | 168 | .recalc = &followparent_recalc, |
| 180 | .enable = &omap1_clk_enable_generic, | ||
| 181 | .disable = &omap1_clk_disable_generic, | ||
| 182 | }, | 169 | }, |
| 183 | .idlect_shift = 12, | 170 | .idlect_shift = 12, |
| 184 | }; | 171 | }; |
| 185 | 172 | ||
| 186 | static struct clk sossi_ck = { | 173 | static struct clk sossi_ck = { |
| 187 | .name = "ck_sossi", | 174 | .name = "ck_sossi", |
| 175 | .ops = &clkops_generic, | ||
| 188 | .parent = &ck_dpll1out.clk, | 176 | .parent = &ck_dpll1out.clk, |
| 189 | .flags = CLOCK_IN_OMAP16XX | CLOCK_NO_IDLE_PARENT | | 177 | .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, |
| 190 | ENABLE_REG_32BIT, | 178 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), |
| 191 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_1, | ||
| 192 | .enable_bit = 16, | 179 | .enable_bit = 16, |
| 193 | .recalc = &omap1_sossi_recalc, | 180 | .recalc = &omap1_sossi_recalc, |
| 194 | .set_rate = &omap1_set_sossi_rate, | 181 | .set_rate = &omap1_set_sossi_rate, |
| 195 | .enable = &omap1_clk_enable_generic, | ||
| 196 | .disable = &omap1_clk_disable_generic, | ||
| 197 | }; | 182 | }; |
| 198 | 183 | ||
| 199 | static struct clk arm_ck = { | 184 | static struct clk arm_ck = { |
| 200 | .name = "arm_ck", | 185 | .name = "arm_ck", |
| 186 | .ops = &clkops_null, | ||
| 201 | .parent = &ck_dpll1, | 187 | .parent = &ck_dpll1, |
| 202 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | ||
| 203 | CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES | | ||
| 204 | ALWAYS_ENABLED, | ||
| 205 | .rate_offset = CKCTL_ARMDIV_OFFSET, | 188 | .rate_offset = CKCTL_ARMDIV_OFFSET, |
| 206 | .recalc = &omap1_ckctl_recalc, | 189 | .recalc = &omap1_ckctl_recalc, |
| 207 | .enable = &omap1_clk_enable_generic, | 190 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 208 | .disable = &omap1_clk_disable_generic, | 191 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 209 | }; | 192 | }; |
| 210 | 193 | ||
| 211 | static struct arm_idlect1_clk armper_ck = { | 194 | static struct arm_idlect1_clk armper_ck = { |
| 212 | .clk = { | 195 | .clk = { |
| 213 | .name = "armper_ck", | 196 | .name = "armper_ck", |
| 197 | .ops = &clkops_generic, | ||
| 214 | .parent = &ck_dpll1, | 198 | .parent = &ck_dpll1, |
| 215 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 199 | .flags = CLOCK_IDLE_CONTROL, |
| 216 | CLOCK_IN_OMAP310 | RATE_CKCTL | | 200 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 217 | CLOCK_IDLE_CONTROL, | ||
| 218 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 219 | .enable_bit = EN_PERCK, | 201 | .enable_bit = EN_PERCK, |
| 220 | .rate_offset = CKCTL_PERDIV_OFFSET, | 202 | .rate_offset = CKCTL_PERDIV_OFFSET, |
| 221 | .recalc = &omap1_ckctl_recalc, | 203 | .recalc = &omap1_ckctl_recalc, |
| 222 | .enable = &omap1_clk_enable_generic, | 204 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 223 | .disable = &omap1_clk_disable_generic, | 205 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 224 | }, | 206 | }, |
| 225 | .idlect_shift = 2, | 207 | .idlect_shift = 2, |
| 226 | }; | 208 | }; |
| 227 | 209 | ||
| 228 | static struct clk arm_gpio_ck = { | 210 | static struct clk arm_gpio_ck = { |
| 229 | .name = "arm_gpio_ck", | 211 | .name = "arm_gpio_ck", |
| 212 | .ops = &clkops_generic, | ||
| 230 | .parent = &ck_dpll1, | 213 | .parent = &ck_dpll1, |
| 231 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310, | 214 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 232 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 233 | .enable_bit = EN_GPIOCK, | 215 | .enable_bit = EN_GPIOCK, |
| 234 | .recalc = &followparent_recalc, | 216 | .recalc = &followparent_recalc, |
| 235 | .enable = &omap1_clk_enable_generic, | ||
| 236 | .disable = &omap1_clk_disable_generic, | ||
| 237 | }; | 217 | }; |
| 238 | 218 | ||
| 239 | static struct arm_idlect1_clk armxor_ck = { | 219 | static struct arm_idlect1_clk armxor_ck = { |
| 240 | .clk = { | 220 | .clk = { |
| 241 | .name = "armxor_ck", | 221 | .name = "armxor_ck", |
| 222 | .ops = &clkops_generic, | ||
| 242 | .parent = &ck_ref, | 223 | .parent = &ck_ref, |
| 243 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 224 | .flags = CLOCK_IDLE_CONTROL, |
| 244 | CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, | 225 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 245 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 246 | .enable_bit = EN_XORPCK, | 226 | .enable_bit = EN_XORPCK, |
| 247 | .recalc = &followparent_recalc, | 227 | .recalc = &followparent_recalc, |
| 248 | .enable = &omap1_clk_enable_generic, | ||
| 249 | .disable = &omap1_clk_disable_generic, | ||
| 250 | }, | 228 | }, |
| 251 | .idlect_shift = 1, | 229 | .idlect_shift = 1, |
| 252 | }; | 230 | }; |
| @@ -254,14 +232,12 @@ static struct arm_idlect1_clk armxor_ck = { | |||
| 254 | static struct arm_idlect1_clk armtim_ck = { | 232 | static struct arm_idlect1_clk armtim_ck = { |
| 255 | .clk = { | 233 | .clk = { |
| 256 | .name = "armtim_ck", | 234 | .name = "armtim_ck", |
| 235 | .ops = &clkops_generic, | ||
| 257 | .parent = &ck_ref, | 236 | .parent = &ck_ref, |
| 258 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 237 | .flags = CLOCK_IDLE_CONTROL, |
| 259 | CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, | 238 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 260 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 261 | .enable_bit = EN_TIMCK, | 239 | .enable_bit = EN_TIMCK, |
| 262 | .recalc = &followparent_recalc, | 240 | .recalc = &followparent_recalc, |
| 263 | .enable = &omap1_clk_enable_generic, | ||
| 264 | .disable = &omap1_clk_disable_generic, | ||
| 265 | }, | 241 | }, |
| 266 | .idlect_shift = 9, | 242 | .idlect_shift = 9, |
| 267 | }; | 243 | }; |
| @@ -269,201 +245,166 @@ static struct arm_idlect1_clk armtim_ck = { | |||
| 269 | static struct arm_idlect1_clk armwdt_ck = { | 245 | static struct arm_idlect1_clk armwdt_ck = { |
| 270 | .clk = { | 246 | .clk = { |
| 271 | .name = "armwdt_ck", | 247 | .name = "armwdt_ck", |
| 248 | .ops = &clkops_generic, | ||
| 272 | .parent = &ck_ref, | 249 | .parent = &ck_ref, |
| 273 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 250 | .flags = CLOCK_IDLE_CONTROL, |
| 274 | CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, | 251 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 275 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 276 | .enable_bit = EN_WDTCK, | 252 | .enable_bit = EN_WDTCK, |
| 277 | .recalc = &omap1_watchdog_recalc, | 253 | .recalc = &omap1_watchdog_recalc, |
| 278 | .enable = &omap1_clk_enable_generic, | ||
| 279 | .disable = &omap1_clk_disable_generic, | ||
| 280 | }, | 254 | }, |
| 281 | .idlect_shift = 0, | 255 | .idlect_shift = 0, |
| 282 | }; | 256 | }; |
| 283 | 257 | ||
| 284 | static struct clk arminth_ck16xx = { | 258 | static struct clk arminth_ck16xx = { |
| 285 | .name = "arminth_ck", | 259 | .name = "arminth_ck", |
| 260 | .ops = &clkops_null, | ||
| 286 | .parent = &arm_ck, | 261 | .parent = &arm_ck, |
| 287 | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, | ||
| 288 | .recalc = &followparent_recalc, | 262 | .recalc = &followparent_recalc, |
| 289 | /* Note: On 16xx the frequency can be divided by 2 by programming | 263 | /* Note: On 16xx the frequency can be divided by 2 by programming |
| 290 | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 | 264 | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 |
| 291 | * | 265 | * |
| 292 | * 1510 version is in TC clocks. | 266 | * 1510 version is in TC clocks. |
| 293 | */ | 267 | */ |
| 294 | .enable = &omap1_clk_enable_generic, | ||
| 295 | .disable = &omap1_clk_disable_generic, | ||
| 296 | }; | 268 | }; |
| 297 | 269 | ||
| 298 | static struct clk dsp_ck = { | 270 | static struct clk dsp_ck = { |
| 299 | .name = "dsp_ck", | 271 | .name = "dsp_ck", |
| 272 | .ops = &clkops_generic, | ||
| 300 | .parent = &ck_dpll1, | 273 | .parent = &ck_dpll1, |
| 301 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 274 | .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), |
| 302 | RATE_CKCTL, | ||
| 303 | .enable_reg = (void __iomem *)ARM_CKCTL, | ||
| 304 | .enable_bit = EN_DSPCK, | 275 | .enable_bit = EN_DSPCK, |
| 305 | .rate_offset = CKCTL_DSPDIV_OFFSET, | 276 | .rate_offset = CKCTL_DSPDIV_OFFSET, |
| 306 | .recalc = &omap1_ckctl_recalc, | 277 | .recalc = &omap1_ckctl_recalc, |
| 307 | .enable = &omap1_clk_enable_generic, | 278 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 308 | .disable = &omap1_clk_disable_generic, | 279 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 309 | }; | 280 | }; |
| 310 | 281 | ||
| 311 | static struct clk dspmmu_ck = { | 282 | static struct clk dspmmu_ck = { |
| 312 | .name = "dspmmu_ck", | 283 | .name = "dspmmu_ck", |
| 284 | .ops = &clkops_null, | ||
| 313 | .parent = &ck_dpll1, | 285 | .parent = &ck_dpll1, |
| 314 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | ||
| 315 | RATE_CKCTL | ALWAYS_ENABLED, | ||
| 316 | .rate_offset = CKCTL_DSPMMUDIV_OFFSET, | 286 | .rate_offset = CKCTL_DSPMMUDIV_OFFSET, |
| 317 | .recalc = &omap1_ckctl_recalc, | 287 | .recalc = &omap1_ckctl_recalc, |
| 318 | .enable = &omap1_clk_enable_generic, | 288 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 319 | .disable = &omap1_clk_disable_generic, | 289 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 320 | }; | 290 | }; |
| 321 | 291 | ||
| 322 | static struct clk dspper_ck = { | 292 | static struct clk dspper_ck = { |
| 323 | .name = "dspper_ck", | 293 | .name = "dspper_ck", |
| 294 | .ops = &clkops_dspck, | ||
| 324 | .parent = &ck_dpll1, | 295 | .parent = &ck_dpll1, |
| 325 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | ||
| 326 | RATE_CKCTL | VIRTUAL_IO_ADDRESS, | ||
| 327 | .enable_reg = DSP_IDLECT2, | 296 | .enable_reg = DSP_IDLECT2, |
| 328 | .enable_bit = EN_PERCK, | 297 | .enable_bit = EN_PERCK, |
| 329 | .rate_offset = CKCTL_PERDIV_OFFSET, | 298 | .rate_offset = CKCTL_PERDIV_OFFSET, |
| 330 | .recalc = &omap1_ckctl_recalc_dsp_domain, | 299 | .recalc = &omap1_ckctl_recalc_dsp_domain, |
| 300 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
| 331 | .set_rate = &omap1_clk_set_rate_dsp_domain, | 301 | .set_rate = &omap1_clk_set_rate_dsp_domain, |
| 332 | .enable = &omap1_clk_enable_dsp_domain, | ||
| 333 | .disable = &omap1_clk_disable_dsp_domain, | ||
| 334 | }; | 302 | }; |
| 335 | 303 | ||
| 336 | static struct clk dspxor_ck = { | 304 | static struct clk dspxor_ck = { |
| 337 | .name = "dspxor_ck", | 305 | .name = "dspxor_ck", |
| 306 | .ops = &clkops_dspck, | ||
| 338 | .parent = &ck_ref, | 307 | .parent = &ck_ref, |
| 339 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | ||
| 340 | VIRTUAL_IO_ADDRESS, | ||
| 341 | .enable_reg = DSP_IDLECT2, | 308 | .enable_reg = DSP_IDLECT2, |
| 342 | .enable_bit = EN_XORPCK, | 309 | .enable_bit = EN_XORPCK, |
| 343 | .recalc = &followparent_recalc, | 310 | .recalc = &followparent_recalc, |
| 344 | .enable = &omap1_clk_enable_dsp_domain, | ||
| 345 | .disable = &omap1_clk_disable_dsp_domain, | ||
| 346 | }; | 311 | }; |
| 347 | 312 | ||
| 348 | static struct clk dsptim_ck = { | 313 | static struct clk dsptim_ck = { |
| 349 | .name = "dsptim_ck", | 314 | .name = "dsptim_ck", |
| 315 | .ops = &clkops_dspck, | ||
| 350 | .parent = &ck_ref, | 316 | .parent = &ck_ref, |
| 351 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | ||
| 352 | VIRTUAL_IO_ADDRESS, | ||
| 353 | .enable_reg = DSP_IDLECT2, | 317 | .enable_reg = DSP_IDLECT2, |
| 354 | .enable_bit = EN_DSPTIMCK, | 318 | .enable_bit = EN_DSPTIMCK, |
| 355 | .recalc = &followparent_recalc, | 319 | .recalc = &followparent_recalc, |
| 356 | .enable = &omap1_clk_enable_dsp_domain, | ||
| 357 | .disable = &omap1_clk_disable_dsp_domain, | ||
| 358 | }; | 320 | }; |
| 359 | 321 | ||
| 360 | /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ | 322 | /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ |
| 361 | static struct arm_idlect1_clk tc_ck = { | 323 | static struct arm_idlect1_clk tc_ck = { |
| 362 | .clk = { | 324 | .clk = { |
| 363 | .name = "tc_ck", | 325 | .name = "tc_ck", |
| 326 | .ops = &clkops_null, | ||
| 364 | .parent = &ck_dpll1, | 327 | .parent = &ck_dpll1, |
| 365 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 328 | .flags = CLOCK_IDLE_CONTROL, |
| 366 | CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 | | ||
| 367 | RATE_CKCTL | RATE_PROPAGATES | | ||
| 368 | ALWAYS_ENABLED | CLOCK_IDLE_CONTROL, | ||
| 369 | .rate_offset = CKCTL_TCDIV_OFFSET, | 329 | .rate_offset = CKCTL_TCDIV_OFFSET, |
| 370 | .recalc = &omap1_ckctl_recalc, | 330 | .recalc = &omap1_ckctl_recalc, |
| 371 | .enable = &omap1_clk_enable_generic, | 331 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 372 | .disable = &omap1_clk_disable_generic, | 332 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 373 | }, | 333 | }, |
| 374 | .idlect_shift = 6, | 334 | .idlect_shift = 6, |
| 375 | }; | 335 | }; |
| 376 | 336 | ||
| 377 | static struct clk arminth_ck1510 = { | 337 | static struct clk arminth_ck1510 = { |
| 378 | .name = "arminth_ck", | 338 | .name = "arminth_ck", |
| 339 | .ops = &clkops_null, | ||
| 379 | .parent = &tc_ck.clk, | 340 | .parent = &tc_ck.clk, |
| 380 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | | ||
| 381 | ALWAYS_ENABLED, | ||
| 382 | .recalc = &followparent_recalc, | 341 | .recalc = &followparent_recalc, |
| 383 | /* Note: On 1510 the frequency follows TC_CK | 342 | /* Note: On 1510 the frequency follows TC_CK |
| 384 | * | 343 | * |
| 385 | * 16xx version is in MPU clocks. | 344 | * 16xx version is in MPU clocks. |
| 386 | */ | 345 | */ |
| 387 | .enable = &omap1_clk_enable_generic, | ||
| 388 | .disable = &omap1_clk_disable_generic, | ||
| 389 | }; | 346 | }; |
| 390 | 347 | ||
| 391 | static struct clk tipb_ck = { | 348 | static struct clk tipb_ck = { |
| 392 | /* No-idle controlled by "tc_ck" */ | 349 | /* No-idle controlled by "tc_ck" */ |
| 393 | .name = "tipb_ck", | 350 | .name = "tipb_ck", |
| 351 | .ops = &clkops_null, | ||
| 394 | .parent = &tc_ck.clk, | 352 | .parent = &tc_ck.clk, |
| 395 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | | ||
| 396 | ALWAYS_ENABLED, | ||
| 397 | .recalc = &followparent_recalc, | 353 | .recalc = &followparent_recalc, |
| 398 | .enable = &omap1_clk_enable_generic, | ||
| 399 | .disable = &omap1_clk_disable_generic, | ||
| 400 | }; | 354 | }; |
| 401 | 355 | ||
| 402 | static struct clk l3_ocpi_ck = { | 356 | static struct clk l3_ocpi_ck = { |
| 403 | /* No-idle controlled by "tc_ck" */ | 357 | /* No-idle controlled by "tc_ck" */ |
| 404 | .name = "l3_ocpi_ck", | 358 | .name = "l3_ocpi_ck", |
| 359 | .ops = &clkops_generic, | ||
| 405 | .parent = &tc_ck.clk, | 360 | .parent = &tc_ck.clk, |
| 406 | .flags = CLOCK_IN_OMAP16XX, | 361 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), |
| 407 | .enable_reg = (void __iomem *)ARM_IDLECT3, | ||
| 408 | .enable_bit = EN_OCPI_CK, | 362 | .enable_bit = EN_OCPI_CK, |
| 409 | .recalc = &followparent_recalc, | 363 | .recalc = &followparent_recalc, |
| 410 | .enable = &omap1_clk_enable_generic, | ||
| 411 | .disable = &omap1_clk_disable_generic, | ||
| 412 | }; | 364 | }; |
| 413 | 365 | ||
| 414 | static struct clk tc1_ck = { | 366 | static struct clk tc1_ck = { |
| 415 | .name = "tc1_ck", | 367 | .name = "tc1_ck", |
| 368 | .ops = &clkops_generic, | ||
| 416 | .parent = &tc_ck.clk, | 369 | .parent = &tc_ck.clk, |
| 417 | .flags = CLOCK_IN_OMAP16XX, | 370 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), |
| 418 | .enable_reg = (void __iomem *)ARM_IDLECT3, | ||
| 419 | .enable_bit = EN_TC1_CK, | 371 | .enable_bit = EN_TC1_CK, |
| 420 | .recalc = &followparent_recalc, | 372 | .recalc = &followparent_recalc, |
| 421 | .enable = &omap1_clk_enable_generic, | ||
| 422 | .disable = &omap1_clk_disable_generic, | ||
| 423 | }; | 373 | }; |
| 424 | 374 | ||
| 425 | static struct clk tc2_ck = { | 375 | static struct clk tc2_ck = { |
| 426 | .name = "tc2_ck", | 376 | .name = "tc2_ck", |
| 377 | .ops = &clkops_generic, | ||
| 427 | .parent = &tc_ck.clk, | 378 | .parent = &tc_ck.clk, |
| 428 | .flags = CLOCK_IN_OMAP16XX, | 379 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), |
| 429 | .enable_reg = (void __iomem *)ARM_IDLECT3, | ||
| 430 | .enable_bit = EN_TC2_CK, | 380 | .enable_bit = EN_TC2_CK, |
| 431 | .recalc = &followparent_recalc, | 381 | .recalc = &followparent_recalc, |
| 432 | .enable = &omap1_clk_enable_generic, | ||
| 433 | .disable = &omap1_clk_disable_generic, | ||
| 434 | }; | 382 | }; |
| 435 | 383 | ||
| 436 | static struct clk dma_ck = { | 384 | static struct clk dma_ck = { |
| 437 | /* No-idle controlled by "tc_ck" */ | 385 | /* No-idle controlled by "tc_ck" */ |
| 438 | .name = "dma_ck", | 386 | .name = "dma_ck", |
| 387 | .ops = &clkops_null, | ||
| 439 | .parent = &tc_ck.clk, | 388 | .parent = &tc_ck.clk, |
| 440 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | ||
| 441 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED, | ||
| 442 | .recalc = &followparent_recalc, | 389 | .recalc = &followparent_recalc, |
| 443 | .enable = &omap1_clk_enable_generic, | ||
| 444 | .disable = &omap1_clk_disable_generic, | ||
| 445 | }; | 390 | }; |
| 446 | 391 | ||
| 447 | static struct clk dma_lcdfree_ck = { | 392 | static struct clk dma_lcdfree_ck = { |
| 448 | .name = "dma_lcdfree_ck", | 393 | .name = "dma_lcdfree_ck", |
| 394 | .ops = &clkops_null, | ||
| 449 | .parent = &tc_ck.clk, | 395 | .parent = &tc_ck.clk, |
| 450 | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, | ||
| 451 | .recalc = &followparent_recalc, | 396 | .recalc = &followparent_recalc, |
| 452 | .enable = &omap1_clk_enable_generic, | ||
| 453 | .disable = &omap1_clk_disable_generic, | ||
| 454 | }; | 397 | }; |
| 455 | 398 | ||
| 456 | static struct arm_idlect1_clk api_ck = { | 399 | static struct arm_idlect1_clk api_ck = { |
| 457 | .clk = { | 400 | .clk = { |
| 458 | .name = "api_ck", | 401 | .name = "api_ck", |
| 402 | .ops = &clkops_generic, | ||
| 459 | .parent = &tc_ck.clk, | 403 | .parent = &tc_ck.clk, |
| 460 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 404 | .flags = CLOCK_IDLE_CONTROL, |
| 461 | CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL, | 405 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 462 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 463 | .enable_bit = EN_APICK, | 406 | .enable_bit = EN_APICK, |
| 464 | .recalc = &followparent_recalc, | 407 | .recalc = &followparent_recalc, |
| 465 | .enable = &omap1_clk_enable_generic, | ||
| 466 | .disable = &omap1_clk_disable_generic, | ||
| 467 | }, | 408 | }, |
| 468 | .idlect_shift = 8, | 409 | .idlect_shift = 8, |
| 469 | }; | 410 | }; |
| @@ -471,276 +412,238 @@ static struct arm_idlect1_clk api_ck = { | |||
| 471 | static struct arm_idlect1_clk lb_ck = { | 412 | static struct arm_idlect1_clk lb_ck = { |
| 472 | .clk = { | 413 | .clk = { |
| 473 | .name = "lb_ck", | 414 | .name = "lb_ck", |
| 415 | .ops = &clkops_generic, | ||
| 474 | .parent = &tc_ck.clk, | 416 | .parent = &tc_ck.clk, |
| 475 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | | 417 | .flags = CLOCK_IDLE_CONTROL, |
| 476 | CLOCK_IDLE_CONTROL, | 418 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 477 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 478 | .enable_bit = EN_LBCK, | 419 | .enable_bit = EN_LBCK, |
| 479 | .recalc = &followparent_recalc, | 420 | .recalc = &followparent_recalc, |
| 480 | .enable = &omap1_clk_enable_generic, | ||
| 481 | .disable = &omap1_clk_disable_generic, | ||
| 482 | }, | 421 | }, |
| 483 | .idlect_shift = 4, | 422 | .idlect_shift = 4, |
| 484 | }; | 423 | }; |
| 485 | 424 | ||
| 486 | static struct clk rhea1_ck = { | 425 | static struct clk rhea1_ck = { |
| 487 | .name = "rhea1_ck", | 426 | .name = "rhea1_ck", |
| 427 | .ops = &clkops_null, | ||
| 488 | .parent = &tc_ck.clk, | 428 | .parent = &tc_ck.clk, |
| 489 | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, | ||
| 490 | .recalc = &followparent_recalc, | 429 | .recalc = &followparent_recalc, |
| 491 | .enable = &omap1_clk_enable_generic, | ||
| 492 | .disable = &omap1_clk_disable_generic, | ||
| 493 | }; | 430 | }; |
| 494 | 431 | ||
| 495 | static struct clk rhea2_ck = { | 432 | static struct clk rhea2_ck = { |
| 496 | .name = "rhea2_ck", | 433 | .name = "rhea2_ck", |
| 434 | .ops = &clkops_null, | ||
| 497 | .parent = &tc_ck.clk, | 435 | .parent = &tc_ck.clk, |
| 498 | .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED, | ||
| 499 | .recalc = &followparent_recalc, | 436 | .recalc = &followparent_recalc, |
| 500 | .enable = &omap1_clk_enable_generic, | ||
| 501 | .disable = &omap1_clk_disable_generic, | ||
| 502 | }; | 437 | }; |
| 503 | 438 | ||
| 504 | static struct clk lcd_ck_16xx = { | 439 | static struct clk lcd_ck_16xx = { |
| 505 | .name = "lcd_ck", | 440 | .name = "lcd_ck", |
| 441 | .ops = &clkops_generic, | ||
| 506 | .parent = &ck_dpll1, | 442 | .parent = &ck_dpll1, |
| 507 | .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL, | 443 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 508 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 509 | .enable_bit = EN_LCDCK, | 444 | .enable_bit = EN_LCDCK, |
| 510 | .rate_offset = CKCTL_LCDDIV_OFFSET, | 445 | .rate_offset = CKCTL_LCDDIV_OFFSET, |
| 511 | .recalc = &omap1_ckctl_recalc, | 446 | .recalc = &omap1_ckctl_recalc, |
| 512 | .enable = &omap1_clk_enable_generic, | 447 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 513 | .disable = &omap1_clk_disable_generic, | 448 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 514 | }; | 449 | }; |
| 515 | 450 | ||
| 516 | static struct arm_idlect1_clk lcd_ck_1510 = { | 451 | static struct arm_idlect1_clk lcd_ck_1510 = { |
| 517 | .clk = { | 452 | .clk = { |
| 518 | .name = "lcd_ck", | 453 | .name = "lcd_ck", |
| 454 | .ops = &clkops_generic, | ||
| 519 | .parent = &ck_dpll1, | 455 | .parent = &ck_dpll1, |
| 520 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | | 456 | .flags = CLOCK_IDLE_CONTROL, |
| 521 | RATE_CKCTL | CLOCK_IDLE_CONTROL, | 457 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
| 522 | .enable_reg = (void __iomem *)ARM_IDLECT2, | ||
| 523 | .enable_bit = EN_LCDCK, | 458 | .enable_bit = EN_LCDCK, |
| 524 | .rate_offset = CKCTL_LCDDIV_OFFSET, | 459 | .rate_offset = CKCTL_LCDDIV_OFFSET, |
| 525 | .recalc = &omap1_ckctl_recalc, | 460 | .recalc = &omap1_ckctl_recalc, |
| 526 | .enable = &omap1_clk_enable_generic, | 461 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
| 527 | .disable = &omap1_clk_disable_generic, | 462 | .set_rate = omap1_clk_set_rate_ckctl_arm, |
| 528 | }, | 463 | }, |
| 529 | .idlect_shift = 3, | 464 | .idlect_shift = 3, |
| 530 | }; | 465 | }; |
| 531 | 466 | ||
| 532 | static struct clk uart1_1510 = { | 467 | static struct clk uart1_1510 = { |
| 533 | .name = "uart1_ck", | 468 | .name = "uart1_ck", |
| 469 | .ops = &clkops_null, | ||
| 534 | /* Direct from ULPD, no real parent */ | 470 | /* Direct from ULPD, no real parent */ |
| 535 | .parent = &armper_ck.clk, | 471 | .parent = &armper_ck.clk, |
| 536 | .rate = 12000000, | 472 | .rate = 12000000, |
| 537 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | | 473 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 538 | ENABLE_REG_32BIT | ALWAYS_ENABLED | | 474 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 539 | CLOCK_NO_IDLE_PARENT, | ||
| 540 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, | ||
| 541 | .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ | 475 | .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ |
| 542 | .set_rate = &omap1_set_uart_rate, | 476 | .set_rate = &omap1_set_uart_rate, |
| 543 | .recalc = &omap1_uart_recalc, | 477 | .recalc = &omap1_uart_recalc, |
| 544 | .enable = &omap1_clk_enable_generic, | ||
| 545 | .disable = &omap1_clk_disable_generic, | ||
| 546 | }; | 478 | }; |
| 547 | 479 | ||
| 548 | static struct uart_clk uart1_16xx = { | 480 | static struct uart_clk uart1_16xx = { |
| 549 | .clk = { | 481 | .clk = { |
| 550 | .name = "uart1_ck", | 482 | .name = "uart1_ck", |
| 483 | .ops = &clkops_uart, | ||
| 551 | /* Direct from ULPD, no real parent */ | 484 | /* Direct from ULPD, no real parent */ |
| 552 | .parent = &armper_ck.clk, | 485 | .parent = &armper_ck.clk, |
| 553 | .rate = 48000000, | 486 | .rate = 48000000, |
| 554 | .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | | 487 | .flags = RATE_FIXED | ENABLE_REG_32BIT | |
| 555 | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 488 | CLOCK_NO_IDLE_PARENT, |
| 556 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, | 489 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 557 | .enable_bit = 29, | 490 | .enable_bit = 29, |
| 558 | .enable = &omap1_clk_enable_uart_functional, | ||
| 559 | .disable = &omap1_clk_disable_uart_functional, | ||
| 560 | }, | 491 | }, |
| 561 | .sysc_addr = 0xfffb0054, | 492 | .sysc_addr = 0xfffb0054, |
| 562 | }; | 493 | }; |
| 563 | 494 | ||
| 564 | static struct clk uart2_ck = { | 495 | static struct clk uart2_ck = { |
| 565 | .name = "uart2_ck", | 496 | .name = "uart2_ck", |
| 497 | .ops = &clkops_null, | ||
| 566 | /* Direct from ULPD, no real parent */ | 498 | /* Direct from ULPD, no real parent */ |
| 567 | .parent = &armper_ck.clk, | 499 | .parent = &armper_ck.clk, |
| 568 | .rate = 12000000, | 500 | .rate = 12000000, |
| 569 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 501 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 570 | CLOCK_IN_OMAP310 | ENABLE_REG_32BIT | | 502 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 571 | ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT, | ||
| 572 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, | ||
| 573 | .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ | 503 | .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ |
| 574 | .set_rate = &omap1_set_uart_rate, | 504 | .set_rate = &omap1_set_uart_rate, |
| 575 | .recalc = &omap1_uart_recalc, | 505 | .recalc = &omap1_uart_recalc, |
| 576 | .enable = &omap1_clk_enable_generic, | ||
| 577 | .disable = &omap1_clk_disable_generic, | ||
| 578 | }; | 506 | }; |
| 579 | 507 | ||
| 580 | static struct clk uart3_1510 = { | 508 | static struct clk uart3_1510 = { |
| 581 | .name = "uart3_ck", | 509 | .name = "uart3_ck", |
| 510 | .ops = &clkops_null, | ||
| 582 | /* Direct from ULPD, no real parent */ | 511 | /* Direct from ULPD, no real parent */ |
| 583 | .parent = &armper_ck.clk, | 512 | .parent = &armper_ck.clk, |
| 584 | .rate = 12000000, | 513 | .rate = 12000000, |
| 585 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | | 514 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 586 | ENABLE_REG_32BIT | ALWAYS_ENABLED | | 515 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 587 | CLOCK_NO_IDLE_PARENT, | ||
| 588 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, | ||
| 589 | .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ | 516 | .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ |
| 590 | .set_rate = &omap1_set_uart_rate, | 517 | .set_rate = &omap1_set_uart_rate, |
| 591 | .recalc = &omap1_uart_recalc, | 518 | .recalc = &omap1_uart_recalc, |
| 592 | .enable = &omap1_clk_enable_generic, | ||
| 593 | .disable = &omap1_clk_disable_generic, | ||
| 594 | }; | 519 | }; |
| 595 | 520 | ||
| 596 | static struct uart_clk uart3_16xx = { | 521 | static struct uart_clk uart3_16xx = { |
| 597 | .clk = { | 522 | .clk = { |
| 598 | .name = "uart3_ck", | 523 | .name = "uart3_ck", |
| 524 | .ops = &clkops_uart, | ||
| 599 | /* Direct from ULPD, no real parent */ | 525 | /* Direct from ULPD, no real parent */ |
| 600 | .parent = &armper_ck.clk, | 526 | .parent = &armper_ck.clk, |
| 601 | .rate = 48000000, | 527 | .rate = 48000000, |
| 602 | .flags = CLOCK_IN_OMAP16XX | RATE_FIXED | | 528 | .flags = RATE_FIXED | ENABLE_REG_32BIT | |
| 603 | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 529 | CLOCK_NO_IDLE_PARENT, |
| 604 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, | 530 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 605 | .enable_bit = 31, | 531 | .enable_bit = 31, |
| 606 | .enable = &omap1_clk_enable_uart_functional, | ||
| 607 | .disable = &omap1_clk_disable_uart_functional, | ||
| 608 | }, | 532 | }, |
| 609 | .sysc_addr = 0xfffb9854, | 533 | .sysc_addr = 0xfffb9854, |
| 610 | }; | 534 | }; |
| 611 | 535 | ||
| 612 | static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ | 536 | static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ |
| 613 | .name = "usb_clko", | 537 | .name = "usb_clko", |
| 538 | .ops = &clkops_generic, | ||
| 614 | /* Direct from ULPD, no parent */ | 539 | /* Direct from ULPD, no parent */ |
| 615 | .rate = 6000000, | 540 | .rate = 6000000, |
| 616 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 541 | .flags = RATE_FIXED | ENABLE_REG_32BIT, |
| 617 | CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT, | 542 | .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), |
| 618 | .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL, | ||
| 619 | .enable_bit = USB_MCLK_EN_BIT, | 543 | .enable_bit = USB_MCLK_EN_BIT, |
| 620 | .enable = &omap1_clk_enable_generic, | ||
| 621 | .disable = &omap1_clk_disable_generic, | ||
| 622 | }; | 544 | }; |
| 623 | 545 | ||
| 624 | static struct clk usb_hhc_ck1510 = { | 546 | static struct clk usb_hhc_ck1510 = { |
| 625 | .name = "usb_hhc_ck", | 547 | .name = "usb_hhc_ck", |
| 548 | .ops = &clkops_generic, | ||
| 626 | /* Direct from ULPD, no parent */ | 549 | /* Direct from ULPD, no parent */ |
| 627 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ | 550 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ |
| 628 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | | 551 | .flags = RATE_FIXED | ENABLE_REG_32BIT, |
| 629 | RATE_FIXED | ENABLE_REG_32BIT, | 552 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 630 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, | ||
| 631 | .enable_bit = USB_HOST_HHC_UHOST_EN, | 553 | .enable_bit = USB_HOST_HHC_UHOST_EN, |
| 632 | .enable = &omap1_clk_enable_generic, | ||
| 633 | .disable = &omap1_clk_disable_generic, | ||
| 634 | }; | 554 | }; |
| 635 | 555 | ||
| 636 | static struct clk usb_hhc_ck16xx = { | 556 | static struct clk usb_hhc_ck16xx = { |
| 637 | .name = "usb_hhc_ck", | 557 | .name = "usb_hhc_ck", |
| 558 | .ops = &clkops_generic, | ||
| 638 | /* Direct from ULPD, no parent */ | 559 | /* Direct from ULPD, no parent */ |
| 639 | .rate = 48000000, | 560 | .rate = 48000000, |
| 640 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ | 561 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ |
| 641 | .flags = CLOCK_IN_OMAP16XX | | 562 | .flags = RATE_FIXED | ENABLE_REG_32BIT, |
| 642 | RATE_FIXED | ENABLE_REG_32BIT, | 563 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ |
| 643 | .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */, | ||
| 644 | .enable_bit = 8 /* UHOST_EN */, | 564 | .enable_bit = 8 /* UHOST_EN */, |
| 645 | .enable = &omap1_clk_enable_generic, | ||
| 646 | .disable = &omap1_clk_disable_generic, | ||
| 647 | }; | 565 | }; |
| 648 | 566 | ||
| 649 | static struct clk usb_dc_ck = { | 567 | static struct clk usb_dc_ck = { |
| 650 | .name = "usb_dc_ck", | 568 | .name = "usb_dc_ck", |
| 569 | .ops = &clkops_generic, | ||
| 651 | /* Direct from ULPD, no parent */ | 570 | /* Direct from ULPD, no parent */ |
| 652 | .rate = 48000000, | 571 | .rate = 48000000, |
| 653 | .flags = CLOCK_IN_OMAP16XX | RATE_FIXED, | 572 | .flags = RATE_FIXED, |
| 654 | .enable_reg = (void __iomem *)SOFT_REQ_REG, | 573 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
| 655 | .enable_bit = 4, | 574 | .enable_bit = 4, |
| 656 | .enable = &omap1_clk_enable_generic, | ||
| 657 | .disable = &omap1_clk_disable_generic, | ||
| 658 | }; | 575 | }; |
| 659 | 576 | ||
| 660 | static struct clk mclk_1510 = { | 577 | static struct clk mclk_1510 = { |
| 661 | .name = "mclk", | 578 | .name = "mclk", |
| 579 | .ops = &clkops_generic, | ||
| 662 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | 580 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 663 | .rate = 12000000, | 581 | .rate = 12000000, |
| 664 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED, | 582 | .flags = RATE_FIXED, |
| 665 | .enable_reg = (void __iomem *)SOFT_REQ_REG, | 583 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
| 666 | .enable_bit = 6, | 584 | .enable_bit = 6, |
| 667 | .enable = &omap1_clk_enable_generic, | ||
| 668 | .disable = &omap1_clk_disable_generic, | ||
| 669 | }; | 585 | }; |
| 670 | 586 | ||
| 671 | static struct clk mclk_16xx = { | 587 | static struct clk mclk_16xx = { |
| 672 | .name = "mclk", | 588 | .name = "mclk", |
| 589 | .ops = &clkops_generic, | ||
| 673 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | 590 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 674 | .flags = CLOCK_IN_OMAP16XX, | 591 | .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), |
| 675 | .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL, | ||
| 676 | .enable_bit = COM_ULPD_PLL_CLK_REQ, | 592 | .enable_bit = COM_ULPD_PLL_CLK_REQ, |
| 677 | .set_rate = &omap1_set_ext_clk_rate, | 593 | .set_rate = &omap1_set_ext_clk_rate, |
| 678 | .round_rate = &omap1_round_ext_clk_rate, | 594 | .round_rate = &omap1_round_ext_clk_rate, |
| 679 | .init = &omap1_init_ext_clk, | 595 | .init = &omap1_init_ext_clk, |
| 680 | .enable = &omap1_clk_enable_generic, | ||
| 681 | .disable = &omap1_clk_disable_generic, | ||
| 682 | }; | 596 | }; |
| 683 | 597 | ||
| 684 | static struct clk bclk_1510 = { | 598 | static struct clk bclk_1510 = { |
| 685 | .name = "bclk", | 599 | .name = "bclk", |
| 600 | .ops = &clkops_generic, | ||
| 686 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | 601 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 687 | .rate = 12000000, | 602 | .rate = 12000000, |
| 688 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED, | 603 | .flags = RATE_FIXED, |
| 689 | .enable = &omap1_clk_enable_generic, | ||
| 690 | .disable = &omap1_clk_disable_generic, | ||
| 691 | }; | 604 | }; |
| 692 | 605 | ||
| 693 | static struct clk bclk_16xx = { | 606 | static struct clk bclk_16xx = { |
| 694 | .name = "bclk", | 607 | .name = "bclk", |
| 608 | .ops = &clkops_generic, | ||
| 695 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | 609 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
| 696 | .flags = CLOCK_IN_OMAP16XX, | 610 | .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), |
| 697 | .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL, | ||
| 698 | .enable_bit = SWD_ULPD_PLL_CLK_REQ, | 611 | .enable_bit = SWD_ULPD_PLL_CLK_REQ, |
| 699 | .set_rate = &omap1_set_ext_clk_rate, | 612 | .set_rate = &omap1_set_ext_clk_rate, |
| 700 | .round_rate = &omap1_round_ext_clk_rate, | 613 | .round_rate = &omap1_round_ext_clk_rate, |
| 701 | .init = &omap1_init_ext_clk, | 614 | .init = &omap1_init_ext_clk, |
| 702 | .enable = &omap1_clk_enable_generic, | ||
| 703 | .disable = &omap1_clk_disable_generic, | ||
| 704 | }; | 615 | }; |
| 705 | 616 | ||
| 706 | static struct clk mmc1_ck = { | 617 | static struct clk mmc1_ck = { |
| 707 | .name = "mmc_ck", | 618 | .name = "mmc_ck", |
| 619 | .ops = &clkops_generic, | ||
| 708 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | 620 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
| 709 | .parent = &armper_ck.clk, | 621 | .parent = &armper_ck.clk, |
| 710 | .rate = 48000000, | 622 | .rate = 48000000, |
| 711 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 623 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 712 | CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT | | 624 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 713 | CLOCK_NO_IDLE_PARENT, | ||
| 714 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, | ||
| 715 | .enable_bit = 23, | 625 | .enable_bit = 23, |
| 716 | .enable = &omap1_clk_enable_generic, | ||
| 717 | .disable = &omap1_clk_disable_generic, | ||
| 718 | }; | 626 | }; |
| 719 | 627 | ||
| 720 | static struct clk mmc2_ck = { | 628 | static struct clk mmc2_ck = { |
| 721 | .name = "mmc_ck", | 629 | .name = "mmc_ck", |
| 722 | .id = 1, | 630 | .id = 1, |
| 631 | .ops = &clkops_generic, | ||
| 723 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | 632 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
| 724 | .parent = &armper_ck.clk, | 633 | .parent = &armper_ck.clk, |
| 725 | .rate = 48000000, | 634 | .rate = 48000000, |
| 726 | .flags = CLOCK_IN_OMAP16XX | | 635 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
| 727 | RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | 636 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
| 728 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, | ||
| 729 | .enable_bit = 20, | 637 | .enable_bit = 20, |
| 730 | .enable = &omap1_clk_enable_generic, | ||
| 731 | .disable = &omap1_clk_disable_generic, | ||
| 732 | }; | 638 | }; |
| 733 | 639 | ||
| 734 | static struct clk virtual_ck_mpu = { | 640 | static struct clk virtual_ck_mpu = { |
| 735 | .name = "mpu", | 641 | .name = "mpu", |
| 736 | .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 642 | .ops = &clkops_null, |
| 737 | CLOCK_IN_OMAP310 | VIRTUAL_CLOCK | ALWAYS_ENABLED, | ||
| 738 | .parent = &arm_ck, /* Is smarter alias for */ | 643 | .parent = &arm_ck, /* Is smarter alias for */ |
| 739 | .recalc = &followparent_recalc, | 644 | .recalc = &followparent_recalc, |
| 740 | .set_rate = &omap1_select_table_rate, | 645 | .set_rate = &omap1_select_table_rate, |
| 741 | .round_rate = &omap1_round_to_table_rate, | 646 | .round_rate = &omap1_round_to_table_rate, |
| 742 | .enable = &omap1_clk_enable_generic, | ||
| 743 | .disable = &omap1_clk_disable_generic, | ||
| 744 | }; | 647 | }; |
| 745 | 648 | ||
| 746 | /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK | 649 | /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK |
| @@ -748,78 +651,19 @@ remains active during MPU idle whenever this is enabled */ | |||
| 748 | static struct clk i2c_fck = { | 651 | static struct clk i2c_fck = { |
| 749 | .name = "i2c_fck", | 652 | .name = "i2c_fck", |
| 750 | .id = 1, | 653 | .id = 1, |
| 751 | .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | | 654 | .ops = &clkops_null, |
| 752 | VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT | | 655 | .flags = CLOCK_NO_IDLE_PARENT, |
| 753 | ALWAYS_ENABLED, | ||
| 754 | .parent = &armxor_ck.clk, | 656 | .parent = &armxor_ck.clk, |
| 755 | .recalc = &followparent_recalc, | 657 | .recalc = &followparent_recalc, |
| 756 | .enable = &omap1_clk_enable_generic, | ||
| 757 | .disable = &omap1_clk_disable_generic, | ||
| 758 | }; | 658 | }; |
| 759 | 659 | ||
| 760 | static struct clk i2c_ick = { | 660 | static struct clk i2c_ick = { |
| 761 | .name = "i2c_ick", | 661 | .name = "i2c_ick", |
| 762 | .id = 1, | 662 | .id = 1, |
| 763 | .flags = CLOCK_IN_OMAP16XX | | 663 | .ops = &clkops_null, |
| 764 | VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT | | 664 | .flags = CLOCK_NO_IDLE_PARENT, |
| 765 | ALWAYS_ENABLED, | ||
| 766 | .parent = &armper_ck.clk, | 665 | .parent = &armper_ck.clk, |
| 767 | .recalc = &followparent_recalc, | 666 | .recalc = &followparent_recalc, |
| 768 | .enable = &omap1_clk_enable_generic, | ||
| 769 | .disable = &omap1_clk_disable_generic, | ||
| 770 | }; | ||
| 771 | |||
| 772 | static struct clk * onchip_clks[] = { | ||
| 773 | /* non-ULPD clocks */ | ||
| 774 | &ck_ref, | ||
| 775 | &ck_dpll1, | ||
| 776 | /* CK_GEN1 clocks */ | ||
| 777 | &ck_dpll1out.clk, | ||
| 778 | &sossi_ck, | ||
| 779 | &arm_ck, | ||
| 780 | &armper_ck.clk, | ||
| 781 | &arm_gpio_ck, | ||
| 782 | &armxor_ck.clk, | ||
| 783 | &armtim_ck.clk, | ||
| 784 | &armwdt_ck.clk, | ||
| 785 | &arminth_ck1510, &arminth_ck16xx, | ||
| 786 | /* CK_GEN2 clocks */ | ||
| 787 | &dsp_ck, | ||
| 788 | &dspmmu_ck, | ||
| 789 | &dspper_ck, | ||
| 790 | &dspxor_ck, | ||
| 791 | &dsptim_ck, | ||
| 792 | /* CK_GEN3 clocks */ | ||
| 793 | &tc_ck.clk, | ||
| 794 | &tipb_ck, | ||
| 795 | &l3_ocpi_ck, | ||
| 796 | &tc1_ck, | ||
| 797 | &tc2_ck, | ||
| 798 | &dma_ck, | ||
| 799 | &dma_lcdfree_ck, | ||
| 800 | &api_ck.clk, | ||
| 801 | &lb_ck.clk, | ||
| 802 | &rhea1_ck, | ||
| 803 | &rhea2_ck, | ||
| 804 | &lcd_ck_16xx, | ||
| 805 | &lcd_ck_1510.clk, | ||
| 806 | /* ULPD clocks */ | ||
| 807 | &uart1_1510, | ||
| 808 | &uart1_16xx.clk, | ||
| 809 | &uart2_ck, | ||
| 810 | &uart3_1510, | ||
| 811 | &uart3_16xx.clk, | ||
| 812 | &usb_clko, | ||
| 813 | &usb_hhc_ck1510, &usb_hhc_ck16xx, | ||
| 814 | &usb_dc_ck, | ||
| 815 | &mclk_1510, &mclk_16xx, | ||
| 816 | &bclk_1510, &bclk_16xx, | ||
| 817 | &mmc1_ck, | ||
| 818 | &mmc2_ck, | ||
| 819 | /* Virtual clocks */ | ||
| 820 | &virtual_ck_mpu, | ||
| 821 | &i2c_fck, | ||
| 822 | &i2c_ick, | ||
| 823 | }; | 667 | }; |
| 824 | 668 | ||
| 825 | #endif | 669 | #endif |
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index ba5d7c08dc17..bbbaeb0abcd3 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c | |||
| @@ -86,7 +86,7 @@ static struct resource mbox_resources[] = { | |||
| 86 | }; | 86 | }; |
| 87 | 87 | ||
| 88 | static struct platform_device mbox_device = { | 88 | static struct platform_device mbox_device = { |
| 89 | .name = "mailbox", | 89 | .name = "omap1-mailbox", |
| 90 | .id = -1, | 90 | .id = -1, |
| 91 | .num_resources = ARRAY_SIZE(mbox_resources), | 91 | .num_resources = ARRAY_SIZE(mbox_resources), |
| 92 | .resource = mbox_resources, | 92 | .resource = mbox_resources, |
diff --git a/arch/arm/mach-omap1/id.c b/arch/arm/mach-omap1/id.c index 89bb8756f450..4ef26faf083e 100644 --- a/arch/arm/mach-omap1/id.c +++ b/arch/arm/mach-omap1/id.c | |||
| @@ -38,6 +38,7 @@ static struct omap_id omap_ids[] __initdata = { | |||
| 38 | { .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000}, | 38 | { .jtag_id = 0xb574, .die_rev = 0x2, .omap_id = 0x03310315, .type = 0x03100000}, |
| 39 | { .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100}, | 39 | { .jtag_id = 0x355f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300100}, |
| 40 | { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300}, | 40 | { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x07300300}, |
| 41 | { .jtag_id = 0xb55f, .die_rev = 0x0, .omap_id = 0x03320500, .type = 0x08500000}, | ||
| 41 | { .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000}, | 42 | { .jtag_id = 0xb470, .die_rev = 0x0, .omap_id = 0x03310100, .type = 0x15100000}, |
| 42 | { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000}, | 43 | { .jtag_id = 0xb576, .die_rev = 0x0, .omap_id = 0x03320000, .type = 0x16100000}, |
| 43 | { .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000}, | 44 | { .jtag_id = 0xb576, .die_rev = 0x2, .omap_id = 0x03320100, .type = 0x16110000}, |
| @@ -77,7 +78,7 @@ static u16 __init omap_get_jtag_id(void) | |||
| 77 | prod_id = omap_readl(OMAP_PRODUCTION_ID_1); | 78 | prod_id = omap_readl(OMAP_PRODUCTION_ID_1); |
| 78 | omap_id = omap_readl(OMAP32_ID_1); | 79 | omap_id = omap_readl(OMAP32_ID_1); |
| 79 | 80 | ||
| 80 | /* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730 */ | 81 | /* Check for unusable OMAP_PRODUCTION_ID_1 on 1611B/5912 and 730/850 */ |
| 81 | if (((prod_id >> 20) == 0) || (prod_id == omap_id)) | 82 | if (((prod_id >> 20) == 0) || (prod_id == omap_id)) |
| 82 | prod_id = 0; | 83 | prod_id = 0; |
| 83 | else | 84 | else |
| @@ -178,6 +179,7 @@ void __init omap_check_revision(void) | |||
| 178 | 179 | ||
| 179 | switch (cpu_type) { | 180 | switch (cpu_type) { |
| 180 | case 0x07: | 181 | case 0x07: |
| 182 | case 0x08: | ||
| 181 | omap_revision |= 0x07; | 183 | omap_revision |= 0x07; |
| 182 | break; | 184 | break; |
| 183 | case 0x03: | 185 | case 0x03: |
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index 4c3e582f3d3c..3afe540149f7 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c | |||
| @@ -52,6 +52,22 @@ static struct map_desc omap730_io_desc[] __initdata = { | |||
| 52 | }; | 52 | }; |
| 53 | #endif | 53 | #endif |
| 54 | 54 | ||
| 55 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 56 | static struct map_desc omap850_io_desc[] __initdata = { | ||
| 57 | { | ||
| 58 | .virtual = OMAP850_DSP_BASE, | ||
| 59 | .pfn = __phys_to_pfn(OMAP850_DSP_START), | ||
| 60 | .length = OMAP850_DSP_SIZE, | ||
| 61 | .type = MT_DEVICE | ||
| 62 | }, { | ||
| 63 | .virtual = OMAP850_DSPREG_BASE, | ||
| 64 | .pfn = __phys_to_pfn(OMAP850_DSPREG_START), | ||
| 65 | .length = OMAP850_DSPREG_SIZE, | ||
| 66 | .type = MT_DEVICE | ||
| 67 | } | ||
| 68 | }; | ||
| 69 | #endif | ||
| 70 | |||
| 55 | #ifdef CONFIG_ARCH_OMAP15XX | 71 | #ifdef CONFIG_ARCH_OMAP15XX |
| 56 | static struct map_desc omap1510_io_desc[] __initdata = { | 72 | static struct map_desc omap1510_io_desc[] __initdata = { |
| 57 | { | 73 | { |
| @@ -109,6 +125,13 @@ void __init omap1_map_common_io(void) | |||
| 109 | iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc)); | 125 | iotable_init(omap730_io_desc, ARRAY_SIZE(omap730_io_desc)); |
| 110 | } | 126 | } |
| 111 | #endif | 127 | #endif |
| 128 | |||
| 129 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 130 | if (cpu_is_omap850()) { | ||
| 131 | iotable_init(omap850_io_desc, ARRAY_SIZE(omap850_io_desc)); | ||
| 132 | } | ||
| 133 | #endif | ||
| 134 | |||
| 112 | #ifdef CONFIG_ARCH_OMAP15XX | 135 | #ifdef CONFIG_ARCH_OMAP15XX |
| 113 | if (cpu_is_omap15xx()) { | 136 | if (cpu_is_omap15xx()) { |
| 114 | iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc)); | 137 | iotable_init(omap1510_io_desc, ARRAY_SIZE(omap1510_io_desc)); |
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c index 9ad5197075ff..de03c8448994 100644 --- a/arch/arm/mach-omap1/irq.c +++ b/arch/arm/mach-omap1/irq.c | |||
| @@ -145,6 +145,14 @@ static struct omap_irq_bank omap730_irq_banks[] = { | |||
| 145 | }; | 145 | }; |
| 146 | #endif | 146 | #endif |
| 147 | 147 | ||
| 148 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 149 | static struct omap_irq_bank omap850_irq_banks[] = { | ||
| 150 | { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, | ||
| 151 | { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, | ||
| 152 | { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, | ||
| 153 | }; | ||
| 154 | #endif | ||
| 155 | |||
| 148 | #ifdef CONFIG_ARCH_OMAP15XX | 156 | #ifdef CONFIG_ARCH_OMAP15XX |
| 149 | static struct omap_irq_bank omap1510_irq_banks[] = { | 157 | static struct omap_irq_bank omap1510_irq_banks[] = { |
| 150 | { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, | 158 | { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, |
| @@ -184,6 +192,12 @@ void __init omap_init_irq(void) | |||
| 184 | irq_bank_count = ARRAY_SIZE(omap730_irq_banks); | 192 | irq_bank_count = ARRAY_SIZE(omap730_irq_banks); |
| 185 | } | 193 | } |
| 186 | #endif | 194 | #endif |
| 195 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 196 | if (cpu_is_omap850()) { | ||
| 197 | irq_banks = omap850_irq_banks; | ||
| 198 | irq_bank_count = ARRAY_SIZE(omap850_irq_banks); | ||
| 199 | } | ||
| 200 | #endif | ||
| 187 | #ifdef CONFIG_ARCH_OMAP15XX | 201 | #ifdef CONFIG_ARCH_OMAP15XX |
| 188 | if (cpu_is_omap1510()) { | 202 | if (cpu_is_omap1510()) { |
| 189 | irq_banks = omap1510_irq_banks; | 203 | irq_banks = omap1510_irq_banks; |
| @@ -214,9 +228,8 @@ void __init omap_init_irq(void) | |||
| 214 | irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET); | 228 | irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET); |
| 215 | 229 | ||
| 216 | /* Enable interrupts in global mask */ | 230 | /* Enable interrupts in global mask */ |
| 217 | if (cpu_is_omap730()) { | 231 | if (cpu_is_omap7xx()) |
| 218 | irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET); | 232 | irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET); |
| 219 | } | ||
| 220 | 233 | ||
| 221 | /* Install the interrupt handlers for each bank */ | 234 | /* Install the interrupt handlers for each bank */ |
| 222 | for (i = 0; i < irq_bank_count; i++) { | 235 | for (i = 0; i < irq_bank_count; i++) { |
| @@ -236,6 +249,8 @@ void __init omap_init_irq(void) | |||
| 236 | 249 | ||
| 237 | if (cpu_is_omap730()) | 250 | if (cpu_is_omap730()) |
| 238 | omap_unmask_irq(INT_730_IH2_IRQ); | 251 | omap_unmask_irq(INT_730_IH2_IRQ); |
| 252 | else if (cpu_is_omap850()) | ||
| 253 | omap_unmask_irq(INT_850_IH2_IRQ); | ||
| 239 | else if (cpu_is_omap15xx()) | 254 | else if (cpu_is_omap15xx()) |
| 240 | omap_unmask_irq(INT_1510_IH2_IRQ); | 255 | omap_unmask_irq(INT_1510_IH2_IRQ); |
| 241 | else if (cpu_is_omap16xx()) | 256 | else if (cpu_is_omap16xx()) |
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c index 59abbf331a96..0af4d6c85b47 100644 --- a/arch/arm/mach-omap1/mailbox.c +++ b/arch/arm/mach-omap1/mailbox.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Mailbox reservation modules for DSP | 2 | * Mailbox reservation modules for DSP |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 Nokia Corporation | 4 | * Copyright (C) 2006-2009 Nokia Corporation |
| 5 | * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | 5 | * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> |
| 6 | * | 6 | * |
| 7 | * This file is subject to the terms and conditions of the GNU General Public | 7 | * This file is subject to the terms and conditions of the GNU General Public |
| @@ -27,7 +27,7 @@ | |||
| 27 | #define MAILBOX_DSP2ARM1_Flag 0x1c | 27 | #define MAILBOX_DSP2ARM1_Flag 0x1c |
| 28 | #define MAILBOX_DSP2ARM2_Flag 0x20 | 28 | #define MAILBOX_DSP2ARM2_Flag 0x20 |
| 29 | 29 | ||
| 30 | unsigned long mbox_base; | 30 | static void __iomem *mbox_base; |
| 31 | 31 | ||
| 32 | struct omap_mbox1_fifo { | 32 | struct omap_mbox1_fifo { |
| 33 | unsigned long cmd; | 33 | unsigned long cmd; |
| @@ -40,14 +40,14 @@ struct omap_mbox1_priv { | |||
| 40 | struct omap_mbox1_fifo rx_fifo; | 40 | struct omap_mbox1_fifo rx_fifo; |
| 41 | }; | 41 | }; |
| 42 | 42 | ||
| 43 | static inline int mbox_read_reg(unsigned int reg) | 43 | static inline int mbox_read_reg(size_t ofs) |
| 44 | { | 44 | { |
| 45 | return __raw_readw(mbox_base + reg); | 45 | return __raw_readw(mbox_base + ofs); |
| 46 | } | 46 | } |
| 47 | 47 | ||
| 48 | static inline void mbox_write_reg(unsigned int val, unsigned int reg) | 48 | static inline void mbox_write_reg(u32 val, size_t ofs) |
| 49 | { | 49 | { |
| 50 | __raw_writew(val, mbox_base + reg); | 50 | __raw_writew(val, mbox_base + ofs); |
| 51 | } | 51 | } |
| 52 | 52 | ||
| 53 | /* msg */ | 53 | /* msg */ |
| @@ -143,7 +143,7 @@ struct omap_mbox mbox_dsp_info = { | |||
| 143 | }; | 143 | }; |
| 144 | EXPORT_SYMBOL(mbox_dsp_info); | 144 | EXPORT_SYMBOL(mbox_dsp_info); |
| 145 | 145 | ||
| 146 | static int __init omap1_mbox_probe(struct platform_device *pdev) | 146 | static int __devinit omap1_mbox_probe(struct platform_device *pdev) |
| 147 | { | 147 | { |
| 148 | struct resource *res; | 148 | struct resource *res; |
| 149 | int ret = 0; | 149 | int ret = 0; |
| @@ -170,12 +170,10 @@ static int __init omap1_mbox_probe(struct platform_device *pdev) | |||
| 170 | } | 170 | } |
| 171 | mbox_dsp_info.irq = res->start; | 171 | mbox_dsp_info.irq = res->start; |
| 172 | 172 | ||
| 173 | ret = omap_mbox_register(&mbox_dsp_info); | 173 | return omap_mbox_register(&pdev->dev, &mbox_dsp_info); |
| 174 | |||
| 175 | return ret; | ||
| 176 | } | 174 | } |
| 177 | 175 | ||
| 178 | static int omap1_mbox_remove(struct platform_device *pdev) | 176 | static int __devexit omap1_mbox_remove(struct platform_device *pdev) |
| 179 | { | 177 | { |
| 180 | omap_mbox_unregister(&mbox_dsp_info); | 178 | omap_mbox_unregister(&mbox_dsp_info); |
| 181 | 179 | ||
| @@ -184,9 +182,9 @@ static int omap1_mbox_remove(struct platform_device *pdev) | |||
| 184 | 182 | ||
| 185 | static struct platform_driver omap1_mbox_driver = { | 183 | static struct platform_driver omap1_mbox_driver = { |
| 186 | .probe = omap1_mbox_probe, | 184 | .probe = omap1_mbox_probe, |
| 187 | .remove = omap1_mbox_remove, | 185 | .remove = __devexit_p(omap1_mbox_remove), |
| 188 | .driver = { | 186 | .driver = { |
| 189 | .name = "mailbox", | 187 | .name = "omap1-mailbox", |
| 190 | }, | 188 | }, |
| 191 | }; | 189 | }; |
| 192 | 190 | ||
| @@ -203,4 +201,7 @@ static void __exit omap1_mbox_exit(void) | |||
| 203 | module_init(omap1_mbox_init); | 201 | module_init(omap1_mbox_init); |
| 204 | module_exit(omap1_mbox_exit); | 202 | module_exit(omap1_mbox_exit); |
| 205 | 203 | ||
| 206 | MODULE_LICENSE("GPL"); | 204 | MODULE_LICENSE("GPL v2"); |
| 205 | MODULE_DESCRIPTION("omap mailbox: omap1 architecture specific functions"); | ||
| 206 | MODULE_AUTHOR("Hiroshi DOYU" <Hiroshi.DOYU@nokia.com>); | ||
| 207 | MODULE_ALIAS("platform:omap1-mailbox"); | ||
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index 575ba31295cf..d040c3f1027f 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c | |||
| @@ -28,9 +28,9 @@ | |||
| 28 | #define DPS_RSTCT2_PER_EN (1 << 0) | 28 | #define DPS_RSTCT2_PER_EN (1 << 0) |
| 29 | #define DSP_RSTCT2_WD_PER_EN (1 << 1) | 29 | #define DSP_RSTCT2_WD_PER_EN (1 << 1) |
| 30 | 30 | ||
| 31 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) | 31 | static int dsp_use; |
| 32 | const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" }; | 32 | static struct clk *api_clk; |
| 33 | #endif | 33 | static struct clk *dsp_clk; |
| 34 | 34 | ||
| 35 | static void omap1_mcbsp_request(unsigned int id) | 35 | static void omap1_mcbsp_request(unsigned int id) |
| 36 | { | 36 | { |
| @@ -39,20 +39,40 @@ static void omap1_mcbsp_request(unsigned int id) | |||
| 39 | * are DSP public peripherals. | 39 | * are DSP public peripherals. |
| 40 | */ | 40 | */ |
| 41 | if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) { | 41 | if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) { |
| 42 | omap_dsp_request_mem(); | 42 | if (dsp_use++ == 0) { |
| 43 | /* | 43 | api_clk = clk_get(NULL, "api_clk"); |
| 44 | * DSP external peripheral reset | 44 | dsp_clk = clk_get(NULL, "dsp_clk"); |
| 45 | * FIXME: This should be moved to dsp code | 45 | if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) { |
| 46 | */ | 46 | clk_enable(api_clk); |
| 47 | __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN | | 47 | clk_enable(dsp_clk); |
| 48 | DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2); | 48 | |
| 49 | omap_dsp_request_mem(); | ||
| 50 | /* | ||
| 51 | * DSP external peripheral reset | ||
| 52 | * FIXME: This should be moved to dsp code | ||
| 53 | */ | ||
| 54 | __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN | | ||
| 55 | DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2); | ||
| 56 | } | ||
| 57 | } | ||
| 49 | } | 58 | } |
| 50 | } | 59 | } |
| 51 | 60 | ||
| 52 | static void omap1_mcbsp_free(unsigned int id) | 61 | static void omap1_mcbsp_free(unsigned int id) |
| 53 | { | 62 | { |
| 54 | if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) | 63 | if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) { |
| 55 | omap_dsp_release_mem(); | 64 | if (--dsp_use == 0) { |
| 65 | omap_dsp_release_mem(); | ||
| 66 | if (!IS_ERR(api_clk)) { | ||
| 67 | clk_disable(api_clk); | ||
| 68 | clk_put(api_clk); | ||
| 69 | } | ||
| 70 | if (!IS_ERR(dsp_clk)) { | ||
| 71 | clk_disable(dsp_clk); | ||
| 72 | clk_put(dsp_clk); | ||
| 73 | } | ||
| 74 | } | ||
| 75 | } | ||
| 56 | } | 76 | } |
| 57 | 77 | ||
| 58 | static struct omap_mcbsp_ops omap1_mcbsp_ops = { | 78 | static struct omap_mcbsp_ops omap1_mcbsp_ops = { |
| @@ -94,8 +114,6 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { | |||
| 94 | .rx_irq = INT_McBSP1RX, | 114 | .rx_irq = INT_McBSP1RX, |
| 95 | .tx_irq = INT_McBSP1TX, | 115 | .tx_irq = INT_McBSP1TX, |
| 96 | .ops = &omap1_mcbsp_ops, | 116 | .ops = &omap1_mcbsp_ops, |
| 97 | .clk_names = clk_names, | ||
| 98 | .num_clks = 3, | ||
| 99 | }, | 117 | }, |
| 100 | { | 118 | { |
| 101 | .phys_base = OMAP1510_MCBSP2_BASE, | 119 | .phys_base = OMAP1510_MCBSP2_BASE, |
| @@ -112,8 +130,6 @@ static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = { | |||
| 112 | .rx_irq = INT_McBSP3RX, | 130 | .rx_irq = INT_McBSP3RX, |
| 113 | .tx_irq = INT_McBSP3TX, | 131 | .tx_irq = INT_McBSP3TX, |
| 114 | .ops = &omap1_mcbsp_ops, | 132 | .ops = &omap1_mcbsp_ops, |
| 115 | .clk_names = clk_names, | ||
| 116 | .num_clks = 3, | ||
| 117 | }, | 133 | }, |
| 118 | }; | 134 | }; |
| 119 | #define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata) | 135 | #define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata) |
| @@ -131,8 +147,6 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { | |||
| 131 | .rx_irq = INT_McBSP1RX, | 147 | .rx_irq = INT_McBSP1RX, |
| 132 | .tx_irq = INT_McBSP1TX, | 148 | .tx_irq = INT_McBSP1TX, |
| 133 | .ops = &omap1_mcbsp_ops, | 149 | .ops = &omap1_mcbsp_ops, |
| 134 | .clk_names = clk_names, | ||
| 135 | .num_clks = 3, | ||
| 136 | }, | 150 | }, |
| 137 | { | 151 | { |
| 138 | .phys_base = OMAP1610_MCBSP2_BASE, | 152 | .phys_base = OMAP1610_MCBSP2_BASE, |
| @@ -149,8 +163,6 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { | |||
| 149 | .rx_irq = INT_McBSP3RX, | 163 | .rx_irq = INT_McBSP3RX, |
| 150 | .tx_irq = INT_McBSP3TX, | 164 | .tx_irq = INT_McBSP3TX, |
| 151 | .ops = &omap1_mcbsp_ops, | 165 | .ops = &omap1_mcbsp_ops, |
| 152 | .clk_names = clk_names, | ||
| 153 | .num_clks = 3, | ||
| 154 | }, | 166 | }, |
| 155 | }; | 167 | }; |
| 156 | #define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata) | 168 | #define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata) |
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 062c905c2ba6..721e0d9d8b1d 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c | |||
| @@ -58,6 +58,25 @@ MUX_CFG_730("W17_730_USB_VBUSI", 2, 29, 0, 28, 0, 0) | |||
| 58 | #define OMAP730_PINS_SZ 0 | 58 | #define OMAP730_PINS_SZ 0 |
| 59 | #endif /* CONFIG_ARCH_OMAP730 */ | 59 | #endif /* CONFIG_ARCH_OMAP730 */ |
| 60 | 60 | ||
| 61 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 62 | struct pin_config __initdata_or_module omap850_pins[] = { | ||
| 63 | MUX_CFG_850("E2_850_KBR0", 12, 21, 0, 20, 1, 0) | ||
| 64 | MUX_CFG_850("J7_850_KBR1", 12, 25, 0, 24, 1, 0) | ||
| 65 | MUX_CFG_850("E1_850_KBR2", 12, 29, 0, 28, 1, 0) | ||
| 66 | MUX_CFG_850("F3_850_KBR3", 13, 1, 0, 0, 1, 0) | ||
| 67 | MUX_CFG_850("D2_850_KBR4", 13, 5, 0, 4, 1, 0) | ||
| 68 | MUX_CFG_850("C2_850_KBC0", 13, 9, 0, 8, 1, 0) | ||
| 69 | MUX_CFG_850("D3_850_KBC1", 13, 13, 0, 12, 1, 0) | ||
| 70 | MUX_CFG_850("E4_850_KBC2", 13, 17, 0, 16, 1, 0) | ||
| 71 | MUX_CFG_850("F4_850_KBC3", 13, 21, 0, 20, 1, 0) | ||
| 72 | MUX_CFG_850("E3_850_KBC4", 13, 25, 0, 24, 1, 0) | ||
| 73 | |||
| 74 | MUX_CFG_850("AA17_850_USB_DM", 2, 21, 0, 20, 0, 0) | ||
| 75 | MUX_CFG_850("W16_850_USB_PU_EN", 2, 25, 0, 24, 0, 0) | ||
| 76 | MUX_CFG_850("W17_850_USB_VBUSI", 2, 29, 0, 28, 0, 0) | ||
| 77 | }; | ||
| 78 | #endif | ||
| 79 | |||
| 61 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) | 80 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) |
| 62 | static struct pin_config __initdata_or_module omap1xxx_pins[] = { | 81 | static struct pin_config __initdata_or_module omap1xxx_pins[] = { |
| 63 | /* | 82 | /* |
| @@ -419,6 +438,11 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) | |||
| 419 | printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", | 438 | printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n", |
| 420 | cfg->pull_name, cfg->pull_reg, pull_orig, pull); | 439 | cfg->pull_name, cfg->pull_reg, pull_orig, pull); |
| 421 | } | 440 | } |
| 441 | |||
| 442 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 443 | omap_mux_register(omap850_pins, ARRAY_SIZE(omap850_pins)); | ||
| 444 | #endif | ||
| 445 | |||
| 422 | #endif | 446 | #endif |
| 423 | 447 | ||
| 424 | #ifdef CONFIG_OMAP_MUX_ERRORS | 448 | #ifdef CONFIG_OMAP_MUX_ERRORS |
diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index 0002084e0655..842090b148f1 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c | |||
| @@ -121,6 +121,13 @@ void __init omap_serial_init(void) | |||
| 121 | serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2; | 121 | serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2; |
| 122 | } | 122 | } |
| 123 | 123 | ||
| 124 | if (cpu_is_omap850()) { | ||
| 125 | serial_platform_data[0].regshift = 0; | ||
| 126 | serial_platform_data[1].regshift = 0; | ||
| 127 | serial_platform_data[0].irq = INT_850_UART_MODEM_1; | ||
| 128 | serial_platform_data[1].irq = INT_850_UART_MODEM_IRDA_2; | ||
| 129 | } | ||
| 130 | |||
| 124 | if (cpu_is_omap15xx()) { | 131 | if (cpu_is_omap15xx()) { |
| 125 | serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16; | 132 | serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16; |
| 126 | serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16; | 133 | serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16; |
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 3754b79092ab..64ab386a65c7 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
| @@ -58,4 +58,12 @@ config MACH_OVERO | |||
| 58 | 58 | ||
| 59 | config MACH_OMAP3_PANDORA | 59 | config MACH_OMAP3_PANDORA |
| 60 | bool "OMAP3 Pandora" | 60 | bool "OMAP3 Pandora" |
| 61 | depends on ARCH_OMAP3 && ARCH_OMAP34XX \ No newline at end of file | 61 | depends on ARCH_OMAP3 && ARCH_OMAP34XX |
| 62 | |||
| 63 | config MACH_OMAP_3430SDP | ||
| 64 | bool "OMAP 3430 SDP board" | ||
| 65 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | ||
| 66 | |||
| 67 | config MACH_NOKIA_RX51 | ||
| 68 | bool "Nokia RX-51 board" | ||
| 69 | depends on ARCH_OMAP3 && ARCH_OMAP34XX | ||
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index bbd12bc10fdc..a2c3fcc27a22 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \ | 6 | obj-y := irq.o id.o io.o sdrc.o control.o prcm.o clock.o mux.o \ |
| 7 | devices.o serial.o gpmc.o timer-gp.o powerdomain.o \ | 7 | devices.o serial.o gpmc.o timer-gp.o powerdomain.o \ |
| 8 | clockdomain.o | 8 | clockdomain.o |
| 9 | 9 | ||
| @@ -14,6 +14,10 @@ obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o | |||
| 14 | obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o | 14 | obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o |
| 15 | obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o | 15 | obj-$(CONFIG_ARCH_OMAP3) += sram34xx.o |
| 16 | 16 | ||
| 17 | # SMS/SDRC | ||
| 18 | obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o | ||
| 19 | # obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o | ||
| 20 | |||
| 17 | # Power Management | 21 | # Power Management |
| 18 | ifeq ($(CONFIG_PM),y) | 22 | ifeq ($(CONFIG_PM),y) |
| 19 | obj-y += pm.o | 23 | obj-y += pm.o |
| @@ -38,4 +42,12 @@ obj-$(CONFIG_MACH_OVERO) += board-overo.o \ | |||
| 38 | mmc-twl4030.o | 42 | mmc-twl4030.o |
| 39 | obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \ | 43 | obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o \ |
| 40 | mmc-twl4030.o | 44 | mmc-twl4030.o |
| 45 | obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o \ | ||
| 46 | mmc-twl4030.o | ||
| 41 | 47 | ||
| 48 | obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ | ||
| 49 | board-rx51-peripherals.o \ | ||
| 50 | # Platform specific device init code | ||
| 51 | ifeq ($(CONFIG_USB_MUSB_SOC),y) | ||
| 52 | obj-y += usb-musb.o | ||
| 53 | endif | ||
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 83fa37211d77..22143651037e 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c | |||
| @@ -35,12 +35,16 @@ | |||
| 35 | #include <mach/board.h> | 35 | #include <mach/board.h> |
| 36 | #include <mach/common.h> | 36 | #include <mach/common.h> |
| 37 | #include <mach/gpmc.h> | 37 | #include <mach/gpmc.h> |
| 38 | #include <mach/usb.h> | ||
| 38 | 39 | ||
| 39 | #include "mmc-twl4030.h" | 40 | #include "mmc-twl4030.h" |
| 40 | 41 | ||
| 42 | #define SDP2430_CS0_BASE 0x04000000 | ||
| 41 | #define SDP2430_FLASH_CS 0 | 43 | #define SDP2430_FLASH_CS 0 |
| 42 | #define SDP2430_SMC91X_CS 5 | 44 | #define SDP2430_SMC91X_CS 5 |
| 43 | 45 | ||
| 46 | #define SDP2430_ETHR_GPIO_IRQ 149 | ||
| 47 | |||
| 44 | static struct mtd_partition sdp2430_partitions[] = { | 48 | static struct mtd_partition sdp2430_partitions[] = { |
| 45 | /* bootloader (U-Boot, etc) in first sector */ | 49 | /* bootloader (U-Boot, etc) in first sector */ |
| 46 | { | 50 | { |
| @@ -102,8 +106,8 @@ static struct resource sdp2430_smc91x_resources[] = { | |||
| 102 | .flags = IORESOURCE_MEM, | 106 | .flags = IORESOURCE_MEM, |
| 103 | }, | 107 | }, |
| 104 | [1] = { | 108 | [1] = { |
| 105 | .start = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), | 109 | .start = OMAP_GPIO_IRQ(SDP2430_ETHR_GPIO_IRQ), |
| 106 | .end = OMAP_GPIO_IRQ(OMAP24XX_ETHR_GPIO_IRQ), | 110 | .end = OMAP_GPIO_IRQ(SDP2430_ETHR_GPIO_IRQ), |
| 107 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | 111 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, |
| 108 | }, | 112 | }, |
| 109 | }; | 113 | }; |
| @@ -170,13 +174,13 @@ static inline void __init sdp2430_init_smc91x(void) | |||
| 170 | sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f; | 174 | sdp2430_smc91x_resources[0].end = cs_mem_base + 0x30f; |
| 171 | udelay(100); | 175 | udelay(100); |
| 172 | 176 | ||
| 173 | if (gpio_request(OMAP24XX_ETHR_GPIO_IRQ, "SMC91x irq") < 0) { | 177 | if (gpio_request(SDP2430_ETHR_GPIO_IRQ, "SMC91x irq") < 0) { |
| 174 | printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", | 178 | printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", |
| 175 | OMAP24XX_ETHR_GPIO_IRQ); | 179 | SDP2430_ETHR_GPIO_IRQ); |
| 176 | gpmc_cs_free(eth_cs); | 180 | gpmc_cs_free(eth_cs); |
| 177 | goto out; | 181 | goto out; |
| 178 | } | 182 | } |
| 179 | gpio_direction_input(OMAP24XX_ETHR_GPIO_IRQ); | 183 | gpio_direction_input(SDP2430_ETHR_GPIO_IRQ); |
| 180 | 184 | ||
| 181 | out: | 185 | out: |
| 182 | clk_disable(gpmc_fck); | 186 | clk_disable(gpmc_fck); |
| @@ -185,7 +189,7 @@ out: | |||
| 185 | 189 | ||
| 186 | static void __init omap_2430sdp_init_irq(void) | 190 | static void __init omap_2430sdp_init_irq(void) |
| 187 | { | 191 | { |
| 188 | omap2_init_common_hw(); | 192 | omap2_init_common_hw(NULL); |
| 189 | omap_init_irq(); | 193 | omap_init_irq(); |
| 190 | omap_gpio_init(); | 194 | omap_gpio_init(); |
| 191 | sdp2430_init_smc91x(); | 195 | sdp2430_init_smc91x(); |
| @@ -251,6 +255,7 @@ static void __init omap_2430sdp_init(void) | |||
| 251 | omap_board_config_size = ARRAY_SIZE(sdp2430_config); | 255 | omap_board_config_size = ARRAY_SIZE(sdp2430_config); |
| 252 | omap_serial_init(); | 256 | omap_serial_init(); |
| 253 | twl4030_mmc_init(mmc); | 257 | twl4030_mmc_init(mmc); |
| 258 | usb_musb_init(); | ||
| 254 | } | 259 | } |
| 255 | 260 | ||
| 256 | static void __init omap_2430sdp_map_io(void) | 261 | static void __init omap_2430sdp_map_io(void) |
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c new file mode 100644 index 000000000000..ed9274972122 --- /dev/null +++ b/arch/arm/mach-omap2/board-3430sdp.c | |||
| @@ -0,0 +1,542 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/board-3430sdp.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007 Texas Instruments | ||
| 5 | * | ||
| 6 | * Modified from mach-omap2/board-generic.c | ||
| 7 | * | ||
| 8 | * Initial code: Syed Mohammed Khasim | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/platform_device.h> | ||
| 18 | #include <linux/delay.h> | ||
| 19 | #include <linux/input.h> | ||
| 20 | #include <linux/spi/spi.h> | ||
| 21 | #include <linux/spi/ads7846.h> | ||
| 22 | #include <linux/i2c/twl4030.h> | ||
| 23 | #include <linux/regulator/machine.h> | ||
| 24 | #include <linux/io.h> | ||
| 25 | #include <linux/gpio.h> | ||
| 26 | |||
| 27 | #include <mach/hardware.h> | ||
| 28 | #include <asm/mach-types.h> | ||
| 29 | #include <asm/mach/arch.h> | ||
| 30 | #include <asm/mach/map.h> | ||
| 31 | |||
| 32 | #include <mach/mcspi.h> | ||
| 33 | #include <mach/mux.h> | ||
| 34 | #include <mach/board.h> | ||
| 35 | #include <mach/usb.h> | ||
| 36 | #include <mach/common.h> | ||
| 37 | #include <mach/dma.h> | ||
| 38 | #include <mach/gpmc.h> | ||
| 39 | |||
| 40 | #include <mach/control.h> | ||
| 41 | #include <mach/keypad.h> | ||
| 42 | |||
| 43 | #include "mmc-twl4030.h" | ||
| 44 | |||
| 45 | #define CONFIG_DISABLE_HFCLK 1 | ||
| 46 | |||
| 47 | #define SDP3430_ETHR_GPIO_IRQ_SDPV1 29 | ||
| 48 | #define SDP3430_ETHR_GPIO_IRQ_SDPV2 6 | ||
| 49 | #define SDP3430_SMC91X_CS 3 | ||
| 50 | |||
| 51 | #define SDP3430_TS_GPIO_IRQ_SDPV1 3 | ||
| 52 | #define SDP3430_TS_GPIO_IRQ_SDPV2 2 | ||
| 53 | |||
| 54 | #define ENABLE_VAUX3_DEDICATED 0x03 | ||
| 55 | #define ENABLE_VAUX3_DEV_GRP 0x20 | ||
| 56 | |||
| 57 | #define TWL4030_MSECURE_GPIO 22 | ||
| 58 | |||
| 59 | static struct resource sdp3430_smc91x_resources[] = { | ||
| 60 | [0] = { | ||
| 61 | .flags = IORESOURCE_MEM, | ||
| 62 | }, | ||
| 63 | [1] = { | ||
| 64 | .start = 0, | ||
| 65 | .end = 0, | ||
| 66 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | ||
| 67 | }, | ||
| 68 | }; | ||
| 69 | |||
| 70 | static struct platform_device sdp3430_smc91x_device = { | ||
| 71 | .name = "smc91x", | ||
| 72 | .id = -1, | ||
| 73 | .num_resources = ARRAY_SIZE(sdp3430_smc91x_resources), | ||
| 74 | .resource = sdp3430_smc91x_resources, | ||
| 75 | }; | ||
| 76 | |||
| 77 | static int sdp3430_keymap[] = { | ||
| 78 | KEY(0, 0, KEY_LEFT), | ||
| 79 | KEY(0, 1, KEY_RIGHT), | ||
| 80 | KEY(0, 2, KEY_A), | ||
| 81 | KEY(0, 3, KEY_B), | ||
| 82 | KEY(0, 4, KEY_C), | ||
| 83 | KEY(1, 0, KEY_DOWN), | ||
| 84 | KEY(1, 1, KEY_UP), | ||
| 85 | KEY(1, 2, KEY_E), | ||
| 86 | KEY(1, 3, KEY_F), | ||
| 87 | KEY(1, 4, KEY_G), | ||
| 88 | KEY(2, 0, KEY_ENTER), | ||
| 89 | KEY(2, 1, KEY_I), | ||
| 90 | KEY(2, 2, KEY_J), | ||
| 91 | KEY(2, 3, KEY_K), | ||
| 92 | KEY(2, 4, KEY_3), | ||
| 93 | KEY(3, 0, KEY_M), | ||
| 94 | KEY(3, 1, KEY_N), | ||
| 95 | KEY(3, 2, KEY_O), | ||
| 96 | KEY(3, 3, KEY_P), | ||
| 97 | KEY(3, 4, KEY_Q), | ||
| 98 | KEY(4, 0, KEY_R), | ||
| 99 | KEY(4, 1, KEY_4), | ||
| 100 | KEY(4, 2, KEY_T), | ||
| 101 | KEY(4, 3, KEY_U), | ||
| 102 | KEY(4, 4, KEY_D), | ||
| 103 | KEY(5, 0, KEY_V), | ||
| 104 | KEY(5, 1, KEY_W), | ||
| 105 | KEY(5, 2, KEY_L), | ||
| 106 | KEY(5, 3, KEY_S), | ||
| 107 | KEY(5, 4, KEY_H), | ||
| 108 | 0 | ||
| 109 | }; | ||
| 110 | |||
| 111 | static struct twl4030_keypad_data sdp3430_kp_data = { | ||
| 112 | .rows = 5, | ||
| 113 | .cols = 6, | ||
| 114 | .keymap = sdp3430_keymap, | ||
| 115 | .keymapsize = ARRAY_SIZE(sdp3430_keymap), | ||
| 116 | .rep = 1, | ||
| 117 | }; | ||
| 118 | |||
| 119 | static int ts_gpio; /* Needed for ads7846_get_pendown_state */ | ||
| 120 | |||
| 121 | /** | ||
| 122 | * @brief ads7846_dev_init : Requests & sets GPIO line for pen-irq | ||
| 123 | * | ||
| 124 | * @return - void. If request gpio fails then Flag KERN_ERR. | ||
| 125 | */ | ||
| 126 | static void ads7846_dev_init(void) | ||
| 127 | { | ||
| 128 | if (gpio_request(ts_gpio, "ADS7846 pendown") < 0) { | ||
| 129 | printk(KERN_ERR "can't get ads746 pen down GPIO\n"); | ||
| 130 | return; | ||
| 131 | } | ||
| 132 | |||
| 133 | gpio_direction_input(ts_gpio); | ||
| 134 | |||
| 135 | omap_set_gpio_debounce(ts_gpio, 1); | ||
| 136 | omap_set_gpio_debounce_time(ts_gpio, 0xa); | ||
| 137 | } | ||
| 138 | |||
| 139 | static int ads7846_get_pendown_state(void) | ||
| 140 | { | ||
| 141 | return !gpio_get_value(ts_gpio); | ||
| 142 | } | ||
| 143 | |||
| 144 | static struct ads7846_platform_data tsc2046_config __initdata = { | ||
| 145 | .get_pendown_state = ads7846_get_pendown_state, | ||
| 146 | .keep_vref_on = 1, | ||
| 147 | }; | ||
| 148 | |||
| 149 | |||
| 150 | static struct omap2_mcspi_device_config tsc2046_mcspi_config = { | ||
| 151 | .turbo_mode = 0, | ||
| 152 | .single_channel = 1, /* 0: slave, 1: master */ | ||
| 153 | }; | ||
| 154 | |||
| 155 | static struct spi_board_info sdp3430_spi_board_info[] __initdata = { | ||
| 156 | [0] = { | ||
| 157 | /* | ||
| 158 | * TSC2046 operates at a max freqency of 2MHz, so | ||
| 159 | * operate slightly below at 1.5MHz | ||
| 160 | */ | ||
| 161 | .modalias = "ads7846", | ||
| 162 | .bus_num = 1, | ||
| 163 | .chip_select = 0, | ||
| 164 | .max_speed_hz = 1500000, | ||
| 165 | .controller_data = &tsc2046_mcspi_config, | ||
| 166 | .irq = 0, | ||
| 167 | .platform_data = &tsc2046_config, | ||
| 168 | }, | ||
| 169 | }; | ||
| 170 | |||
| 171 | static struct platform_device sdp3430_lcd_device = { | ||
| 172 | .name = "sdp2430_lcd", | ||
| 173 | .id = -1, | ||
| 174 | }; | ||
| 175 | |||
| 176 | static struct regulator_consumer_supply sdp3430_vdac_supply = { | ||
| 177 | .supply = "vdac", | ||
| 178 | .dev = &sdp3430_lcd_device.dev, | ||
| 179 | }; | ||
| 180 | |||
| 181 | static struct regulator_consumer_supply sdp3430_vdvi_supply = { | ||
| 182 | .supply = "vdvi", | ||
| 183 | .dev = &sdp3430_lcd_device.dev, | ||
| 184 | }; | ||
| 185 | |||
| 186 | static struct platform_device *sdp3430_devices[] __initdata = { | ||
| 187 | &sdp3430_smc91x_device, | ||
| 188 | &sdp3430_lcd_device, | ||
| 189 | }; | ||
| 190 | |||
| 191 | static inline void __init sdp3430_init_smc91x(void) | ||
| 192 | { | ||
| 193 | int eth_cs; | ||
| 194 | unsigned long cs_mem_base; | ||
| 195 | int eth_gpio = 0; | ||
| 196 | |||
| 197 | eth_cs = SDP3430_SMC91X_CS; | ||
| 198 | |||
| 199 | if (gpmc_cs_request(eth_cs, SZ_16M, &cs_mem_base) < 0) { | ||
| 200 | printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); | ||
| 201 | return; | ||
| 202 | } | ||
| 203 | |||
| 204 | sdp3430_smc91x_resources[0].start = cs_mem_base + 0x300; | ||
| 205 | sdp3430_smc91x_resources[0].end = cs_mem_base + 0x30f; | ||
| 206 | udelay(100); | ||
| 207 | |||
| 208 | if (omap_rev() > OMAP3430_REV_ES1_0) | ||
| 209 | eth_gpio = SDP3430_ETHR_GPIO_IRQ_SDPV2; | ||
| 210 | else | ||
| 211 | eth_gpio = SDP3430_ETHR_GPIO_IRQ_SDPV1; | ||
| 212 | |||
| 213 | sdp3430_smc91x_resources[1].start = gpio_to_irq(eth_gpio); | ||
| 214 | |||
| 215 | if (gpio_request(eth_gpio, "SMC91x irq") < 0) { | ||
| 216 | printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", | ||
| 217 | eth_gpio); | ||
| 218 | return; | ||
| 219 | } | ||
| 220 | gpio_direction_input(eth_gpio); | ||
| 221 | } | ||
| 222 | |||
| 223 | static void __init omap_3430sdp_init_irq(void) | ||
| 224 | { | ||
| 225 | omap2_init_common_hw(NULL); | ||
| 226 | omap_init_irq(); | ||
| 227 | omap_gpio_init(); | ||
| 228 | sdp3430_init_smc91x(); | ||
| 229 | } | ||
| 230 | |||
| 231 | static struct omap_uart_config sdp3430_uart_config __initdata = { | ||
| 232 | .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), | ||
| 233 | }; | ||
| 234 | |||
| 235 | static struct omap_lcd_config sdp3430_lcd_config __initdata = { | ||
| 236 | .ctrl_name = "internal", | ||
| 237 | }; | ||
| 238 | |||
| 239 | static struct omap_board_config_kernel sdp3430_config[] __initdata = { | ||
| 240 | { OMAP_TAG_UART, &sdp3430_uart_config }, | ||
| 241 | { OMAP_TAG_LCD, &sdp3430_lcd_config }, | ||
| 242 | }; | ||
| 243 | |||
| 244 | static int sdp3430_batt_table[] = { | ||
| 245 | /* 0 C*/ | ||
| 246 | 30800, 29500, 28300, 27100, | ||
| 247 | 26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900, | ||
| 248 | 17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100, | ||
| 249 | 11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310, | ||
| 250 | 8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830, | ||
| 251 | 5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170, | ||
| 252 | 4040, 3910, 3790, 3670, 3550 | ||
| 253 | }; | ||
| 254 | |||
| 255 | static struct twl4030_bci_platform_data sdp3430_bci_data = { | ||
| 256 | .battery_tmp_tbl = sdp3430_batt_table, | ||
| 257 | .tblsize = ARRAY_SIZE(sdp3430_batt_table), | ||
| 258 | }; | ||
| 259 | |||
| 260 | static struct twl4030_hsmmc_info mmc[] = { | ||
| 261 | { | ||
| 262 | .mmc = 1, | ||
| 263 | /* 8 bits (default) requires S6.3 == ON, | ||
| 264 | * so the SIM card isn't used; else 4 bits. | ||
| 265 | */ | ||
| 266 | .wires = 8, | ||
| 267 | .gpio_wp = 4, | ||
| 268 | }, | ||
| 269 | { | ||
| 270 | .mmc = 2, | ||
| 271 | .wires = 8, | ||
| 272 | .gpio_wp = 7, | ||
| 273 | }, | ||
| 274 | {} /* Terminator */ | ||
| 275 | }; | ||
| 276 | |||
| 277 | static struct regulator_consumer_supply sdp3430_vmmc1_supply = { | ||
| 278 | .supply = "vmmc", | ||
| 279 | }; | ||
| 280 | |||
| 281 | static struct regulator_consumer_supply sdp3430_vsim_supply = { | ||
| 282 | .supply = "vmmc_aux", | ||
| 283 | }; | ||
| 284 | |||
| 285 | static struct regulator_consumer_supply sdp3430_vmmc2_supply = { | ||
| 286 | .supply = "vmmc", | ||
| 287 | }; | ||
| 288 | |||
| 289 | static int sdp3430_twl_gpio_setup(struct device *dev, | ||
| 290 | unsigned gpio, unsigned ngpio) | ||
| 291 | { | ||
| 292 | /* gpio + 0 is "mmc0_cd" (input/IRQ), | ||
| 293 | * gpio + 1 is "mmc1_cd" (input/IRQ) | ||
| 294 | */ | ||
| 295 | mmc[0].gpio_cd = gpio + 0; | ||
| 296 | mmc[1].gpio_cd = gpio + 1; | ||
| 297 | twl4030_mmc_init(mmc); | ||
| 298 | |||
| 299 | /* link regulators to MMC adapters ... we "know" the | ||
| 300 | * regulators will be set up only *after* we return. | ||
| 301 | */ | ||
| 302 | sdp3430_vmmc1_supply.dev = mmc[0].dev; | ||
| 303 | sdp3430_vsim_supply.dev = mmc[0].dev; | ||
| 304 | sdp3430_vmmc2_supply.dev = mmc[1].dev; | ||
| 305 | |||
| 306 | /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */ | ||
| 307 | gpio_request(gpio + 7, "sub_lcd_en_bkl"); | ||
| 308 | gpio_direction_output(gpio + 7, 0); | ||
| 309 | |||
| 310 | /* gpio + 15 is "sub_lcd_nRST" (output) */ | ||
| 311 | gpio_request(gpio + 15, "sub_lcd_nRST"); | ||
| 312 | gpio_direction_output(gpio + 15, 0); | ||
| 313 | |||
| 314 | return 0; | ||
| 315 | } | ||
| 316 | |||
| 317 | static struct twl4030_gpio_platform_data sdp3430_gpio_data = { | ||
| 318 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 319 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 320 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 321 | .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13) | ||
| 322 | | BIT(16) | BIT(17), | ||
| 323 | .setup = sdp3430_twl_gpio_setup, | ||
| 324 | }; | ||
| 325 | |||
| 326 | static struct twl4030_usb_data sdp3430_usb_data = { | ||
| 327 | .usb_mode = T2_USB_MODE_ULPI, | ||
| 328 | }; | ||
| 329 | |||
| 330 | static struct twl4030_madc_platform_data sdp3430_madc_data = { | ||
| 331 | .irq_line = 1, | ||
| 332 | }; | ||
| 333 | |||
| 334 | /* | ||
| 335 | * Apply all the fixed voltages since most versions of U-Boot | ||
| 336 | * don't bother with that initialization. | ||
| 337 | */ | ||
| 338 | |||
| 339 | /* VAUX1 for mainboard (irda and sub-lcd) */ | ||
| 340 | static struct regulator_init_data sdp3430_vaux1 = { | ||
| 341 | .constraints = { | ||
| 342 | .min_uV = 2800000, | ||
| 343 | .max_uV = 2800000, | ||
| 344 | .apply_uV = true, | ||
| 345 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 346 | | REGULATOR_MODE_STANDBY, | ||
| 347 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 348 | | REGULATOR_CHANGE_STATUS, | ||
| 349 | }, | ||
| 350 | }; | ||
| 351 | |||
| 352 | /* VAUX2 for camera module */ | ||
| 353 | static struct regulator_init_data sdp3430_vaux2 = { | ||
| 354 | .constraints = { | ||
| 355 | .min_uV = 2800000, | ||
| 356 | .max_uV = 2800000, | ||
| 357 | .apply_uV = true, | ||
| 358 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 359 | | REGULATOR_MODE_STANDBY, | ||
| 360 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 361 | | REGULATOR_CHANGE_STATUS, | ||
| 362 | }, | ||
| 363 | }; | ||
| 364 | |||
| 365 | /* VAUX3 for LCD board */ | ||
| 366 | static struct regulator_init_data sdp3430_vaux3 = { | ||
| 367 | .constraints = { | ||
| 368 | .min_uV = 2800000, | ||
| 369 | .max_uV = 2800000, | ||
| 370 | .apply_uV = true, | ||
| 371 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 372 | | REGULATOR_MODE_STANDBY, | ||
| 373 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 374 | | REGULATOR_CHANGE_STATUS, | ||
| 375 | }, | ||
| 376 | }; | ||
| 377 | |||
| 378 | /* VAUX4 for OMAP VDD_CSI2 (camera) */ | ||
| 379 | static struct regulator_init_data sdp3430_vaux4 = { | ||
| 380 | .constraints = { | ||
| 381 | .min_uV = 1800000, | ||
| 382 | .max_uV = 1800000, | ||
| 383 | .apply_uV = true, | ||
| 384 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 385 | | REGULATOR_MODE_STANDBY, | ||
| 386 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 387 | | REGULATOR_CHANGE_STATUS, | ||
| 388 | }, | ||
| 389 | }; | ||
| 390 | |||
| 391 | /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */ | ||
| 392 | static struct regulator_init_data sdp3430_vmmc1 = { | ||
| 393 | .constraints = { | ||
| 394 | .min_uV = 1850000, | ||
| 395 | .max_uV = 3150000, | ||
| 396 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 397 | | REGULATOR_MODE_STANDBY, | ||
| 398 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 399 | | REGULATOR_CHANGE_MODE | ||
| 400 | | REGULATOR_CHANGE_STATUS, | ||
| 401 | }, | ||
| 402 | .num_consumer_supplies = 1, | ||
| 403 | .consumer_supplies = &sdp3430_vmmc1_supply, | ||
| 404 | }; | ||
| 405 | |||
| 406 | /* VMMC2 for MMC2 card */ | ||
| 407 | static struct regulator_init_data sdp3430_vmmc2 = { | ||
| 408 | .constraints = { | ||
| 409 | .min_uV = 1850000, | ||
| 410 | .max_uV = 1850000, | ||
| 411 | .apply_uV = true, | ||
| 412 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 413 | | REGULATOR_MODE_STANDBY, | ||
| 414 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 415 | | REGULATOR_CHANGE_STATUS, | ||
| 416 | }, | ||
| 417 | .num_consumer_supplies = 1, | ||
| 418 | .consumer_supplies = &sdp3430_vmmc2_supply, | ||
| 419 | }; | ||
| 420 | |||
| 421 | /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */ | ||
| 422 | static struct regulator_init_data sdp3430_vsim = { | ||
| 423 | .constraints = { | ||
| 424 | .min_uV = 1800000, | ||
| 425 | .max_uV = 3000000, | ||
| 426 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 427 | | REGULATOR_MODE_STANDBY, | ||
| 428 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 429 | | REGULATOR_CHANGE_MODE | ||
| 430 | | REGULATOR_CHANGE_STATUS, | ||
| 431 | }, | ||
| 432 | .num_consumer_supplies = 1, | ||
| 433 | .consumer_supplies = &sdp3430_vsim_supply, | ||
| 434 | }; | ||
| 435 | |||
| 436 | /* VDAC for DSS driving S-Video */ | ||
| 437 | static struct regulator_init_data sdp3430_vdac = { | ||
| 438 | .constraints = { | ||
| 439 | .min_uV = 1800000, | ||
| 440 | .max_uV = 1800000, | ||
| 441 | .apply_uV = true, | ||
| 442 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 443 | | REGULATOR_MODE_STANDBY, | ||
| 444 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 445 | | REGULATOR_CHANGE_STATUS, | ||
| 446 | }, | ||
| 447 | .num_consumer_supplies = 1, | ||
| 448 | .consumer_supplies = &sdp3430_vdac_supply, | ||
| 449 | }; | ||
| 450 | |||
| 451 | /* VPLL2 for digital video outputs */ | ||
| 452 | static struct regulator_init_data sdp3430_vpll2 = { | ||
| 453 | .constraints = { | ||
| 454 | .name = "VDVI", | ||
| 455 | .min_uV = 1800000, | ||
| 456 | .max_uV = 1800000, | ||
| 457 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 458 | | REGULATOR_MODE_STANDBY, | ||
| 459 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 460 | | REGULATOR_CHANGE_STATUS, | ||
| 461 | }, | ||
| 462 | .num_consumer_supplies = 1, | ||
| 463 | .consumer_supplies = &sdp3430_vdvi_supply, | ||
| 464 | }; | ||
| 465 | |||
| 466 | static struct twl4030_platform_data sdp3430_twldata = { | ||
| 467 | .irq_base = TWL4030_IRQ_BASE, | ||
| 468 | .irq_end = TWL4030_IRQ_END, | ||
| 469 | |||
| 470 | /* platform_data for children goes here */ | ||
| 471 | .bci = &sdp3430_bci_data, | ||
| 472 | .gpio = &sdp3430_gpio_data, | ||
| 473 | .madc = &sdp3430_madc_data, | ||
| 474 | .keypad = &sdp3430_kp_data, | ||
| 475 | .usb = &sdp3430_usb_data, | ||
| 476 | |||
| 477 | .vaux1 = &sdp3430_vaux1, | ||
| 478 | .vaux2 = &sdp3430_vaux2, | ||
| 479 | .vaux3 = &sdp3430_vaux3, | ||
| 480 | .vaux4 = &sdp3430_vaux4, | ||
| 481 | .vmmc1 = &sdp3430_vmmc1, | ||
| 482 | .vmmc2 = &sdp3430_vmmc2, | ||
| 483 | .vsim = &sdp3430_vsim, | ||
| 484 | .vdac = &sdp3430_vdac, | ||
| 485 | .vpll2 = &sdp3430_vpll2, | ||
| 486 | }; | ||
| 487 | |||
| 488 | static struct i2c_board_info __initdata sdp3430_i2c_boardinfo[] = { | ||
| 489 | { | ||
| 490 | I2C_BOARD_INFO("twl4030", 0x48), | ||
| 491 | .flags = I2C_CLIENT_WAKE, | ||
| 492 | .irq = INT_34XX_SYS_NIRQ, | ||
| 493 | .platform_data = &sdp3430_twldata, | ||
| 494 | }, | ||
| 495 | }; | ||
| 496 | |||
| 497 | static int __init omap3430_i2c_init(void) | ||
| 498 | { | ||
| 499 | /* i2c1 for PMIC only */ | ||
| 500 | omap_register_i2c_bus(1, 2600, sdp3430_i2c_boardinfo, | ||
| 501 | ARRAY_SIZE(sdp3430_i2c_boardinfo)); | ||
| 502 | /* i2c2 on camera connector (for sensor control) and optional isp1301 */ | ||
| 503 | omap_register_i2c_bus(2, 400, NULL, 0); | ||
| 504 | /* i2c3 on display connector (for DVI, tfp410) */ | ||
| 505 | omap_register_i2c_bus(3, 400, NULL, 0); | ||
| 506 | return 0; | ||
| 507 | } | ||
| 508 | |||
| 509 | static void __init omap_3430sdp_init(void) | ||
| 510 | { | ||
| 511 | omap3430_i2c_init(); | ||
| 512 | platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices)); | ||
| 513 | omap_board_config = sdp3430_config; | ||
| 514 | omap_board_config_size = ARRAY_SIZE(sdp3430_config); | ||
| 515 | if (omap_rev() > OMAP3430_REV_ES1_0) | ||
| 516 | ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2; | ||
| 517 | else | ||
| 518 | ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV1; | ||
| 519 | sdp3430_spi_board_info[0].irq = gpio_to_irq(ts_gpio); | ||
| 520 | spi_register_board_info(sdp3430_spi_board_info, | ||
| 521 | ARRAY_SIZE(sdp3430_spi_board_info)); | ||
| 522 | ads7846_dev_init(); | ||
| 523 | omap_serial_init(); | ||
| 524 | usb_musb_init(); | ||
| 525 | } | ||
| 526 | |||
| 527 | static void __init omap_3430sdp_map_io(void) | ||
| 528 | { | ||
| 529 | omap2_set_globals_343x(); | ||
| 530 | omap2_map_common_io(); | ||
| 531 | } | ||
| 532 | |||
| 533 | MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") | ||
| 534 | /* Maintainer: Syed Khasim - Texas Instruments Inc */ | ||
| 535 | .phys_io = 0x48000000, | ||
| 536 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | ||
| 537 | .boot_params = 0x80000100, | ||
| 538 | .map_io = omap_3430sdp_map_io, | ||
| 539 | .init_irq = omap_3430sdp_init_irq, | ||
| 540 | .init_machine = omap_3430sdp_init, | ||
| 541 | .timer = &omap_timer, | ||
| 542 | MACHINE_END | ||
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c index 0a7b24ba1652..06dfba888b0c 100644 --- a/arch/arm/mach-omap2/board-apollon.c +++ b/arch/arm/mach-omap2/board-apollon.c | |||
| @@ -51,6 +51,7 @@ | |||
| 51 | 51 | ||
| 52 | #define APOLLON_FLASH_CS 0 | 52 | #define APOLLON_FLASH_CS 0 |
| 53 | #define APOLLON_ETH_CS 1 | 53 | #define APOLLON_ETH_CS 1 |
| 54 | #define APOLLON_ETHR_GPIO_IRQ 74 | ||
| 54 | 55 | ||
| 55 | static struct mtd_partition apollon_partitions[] = { | 56 | static struct mtd_partition apollon_partitions[] = { |
| 56 | { | 57 | { |
| @@ -249,7 +250,7 @@ out: | |||
| 249 | 250 | ||
| 250 | static void __init omap_apollon_init_irq(void) | 251 | static void __init omap_apollon_init_irq(void) |
| 251 | { | 252 | { |
| 252 | omap2_init_common_hw(); | 253 | omap2_init_common_hw(NULL); |
| 253 | omap_init_irq(); | 254 | omap_init_irq(); |
| 254 | omap_gpio_init(); | 255 | omap_gpio_init(); |
| 255 | apollon_init_smc91x(); | 256 | apollon_init_smc91x(); |
| @@ -272,7 +273,6 @@ static struct omap_lcd_config apollon_lcd_config __initdata = { | |||
| 272 | 273 | ||
| 273 | static struct omap_board_config_kernel apollon_config[] = { | 274 | static struct omap_board_config_kernel apollon_config[] = { |
| 274 | { OMAP_TAG_UART, &apollon_uart_config }, | 275 | { OMAP_TAG_UART, &apollon_uart_config }, |
| 275 | { OMAP_TAG_USB, &apollon_usb_config }, | ||
| 276 | { OMAP_TAG_LCD, &apollon_lcd_config }, | 276 | { OMAP_TAG_LCD, &apollon_lcd_config }, |
| 277 | }; | 277 | }; |
| 278 | 278 | ||
| @@ -299,6 +299,7 @@ static void __init apollon_usb_init(void) | |||
| 299 | omap_cfg_reg(P21_242X_GPIO12); | 299 | omap_cfg_reg(P21_242X_GPIO12); |
| 300 | gpio_request(12, "USB suspend"); | 300 | gpio_request(12, "USB suspend"); |
| 301 | gpio_direction_output(12, 0); | 301 | gpio_direction_output(12, 0); |
| 302 | omap_usb_init(&apollon_usb_config); | ||
| 302 | } | 303 | } |
| 303 | 304 | ||
| 304 | static void __init omap_apollon_init(void) | 305 | static void __init omap_apollon_init(void) |
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index 3b34c20d1df4..3492162a65c3 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c | |||
| @@ -33,7 +33,7 @@ | |||
| 33 | 33 | ||
| 34 | static void __init omap_generic_init_irq(void) | 34 | static void __init omap_generic_init_irq(void) |
| 35 | { | 35 | { |
| 36 | omap2_init_common_hw(); | 36 | omap2_init_common_hw(NULL); |
| 37 | omap_init_irq(); | 37 | omap_init_irq(); |
| 38 | } | 38 | } |
| 39 | 39 | ||
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 5e9b14675b1e..a0267a9ab466 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c | |||
| @@ -47,6 +47,8 @@ | |||
| 47 | #define H4_FLASH_CS 0 | 47 | #define H4_FLASH_CS 0 |
| 48 | #define H4_SMC91X_CS 1 | 48 | #define H4_SMC91X_CS 1 |
| 49 | 49 | ||
| 50 | #define H4_ETHR_GPIO_IRQ 92 | ||
| 51 | |||
| 50 | static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 }; | 52 | static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 }; |
| 51 | static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 }; | 53 | static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 }; |
| 52 | 54 | ||
| @@ -341,7 +343,7 @@ static inline void __init h4_init_debug(void) | |||
| 341 | udelay(100); | 343 | udelay(100); |
| 342 | 344 | ||
| 343 | omap_cfg_reg(M15_24XX_GPIO92); | 345 | omap_cfg_reg(M15_24XX_GPIO92); |
| 344 | if (debug_card_init(cs_mem_base, OMAP24XX_ETHR_GPIO_IRQ) < 0) | 346 | if (debug_card_init(cs_mem_base, H4_ETHR_GPIO_IRQ) < 0) |
| 345 | gpmc_cs_free(eth_cs); | 347 | gpmc_cs_free(eth_cs); |
| 346 | 348 | ||
| 347 | out: | 349 | out: |
| @@ -363,7 +365,7 @@ static void __init h4_init_flash(void) | |||
| 363 | 365 | ||
| 364 | static void __init omap_h4_init_irq(void) | 366 | static void __init omap_h4_init_irq(void) |
| 365 | { | 367 | { |
| 366 | omap2_init_common_hw(); | 368 | omap2_init_common_hw(NULL); |
| 367 | omap_init_irq(); | 369 | omap_init_irq(); |
| 368 | omap_gpio_init(); | 370 | omap_gpio_init(); |
| 369 | h4_init_flash(); | 371 | h4_init_flash(); |
| @@ -377,6 +379,39 @@ static struct omap_lcd_config h4_lcd_config __initdata = { | |||
| 377 | .ctrl_name = "internal", | 379 | .ctrl_name = "internal", |
| 378 | }; | 380 | }; |
| 379 | 381 | ||
| 382 | static struct omap_usb_config h4_usb_config __initdata = { | ||
| 383 | #ifdef CONFIG_MACH_OMAP2_H4_USB1 | ||
| 384 | /* NOTE: usb1 could also be used with 3 wire signaling */ | ||
| 385 | .pins[1] = 4, | ||
| 386 | #endif | ||
| 387 | |||
| 388 | #ifdef CONFIG_MACH_OMAP_H4_OTG | ||
| 389 | /* S1.10 ON -- USB OTG port | ||
| 390 | * usb0 switched to Mini-AB port and isp1301 transceiver; | ||
| 391 | * S2.POS3 = OFF, S2.POS4 = ON ... to allow battery charging | ||
| 392 | */ | ||
| 393 | .otg = 1, | ||
| 394 | .pins[0] = 4, | ||
| 395 | #ifdef CONFIG_USB_GADGET_OMAP | ||
| 396 | /* use OTG cable, or standard A-to-MiniB */ | ||
| 397 | .hmc_mode = 0x14, /* 0:dev/otg 1:host 2:disable */ | ||
| 398 | #elif defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 399 | /* use OTG cable, or NONSTANDARD (B-to-MiniB) */ | ||
| 400 | .hmc_mode = 0x11, /* 0:host 1:host 2:disable */ | ||
| 401 | #endif /* XX */ | ||
| 402 | |||
| 403 | #else | ||
| 404 | /* S1.10 OFF -- usb "download port" | ||
| 405 | * usb0 switched to Mini-B port and isp1105 transceiver; | ||
| 406 | * S2.POS3 = ON, S2.POS4 = OFF ... to enable battery charging | ||
| 407 | */ | ||
| 408 | .register_dev = 1, | ||
| 409 | .pins[0] = 3, | ||
| 410 | /* .hmc_mode = 0x14,*/ /* 0:dev 1:host 2:disable */ | ||
| 411 | .hmc_mode = 0x00, /* 0:dev|otg 1:disable 2:disable */ | ||
| 412 | #endif | ||
| 413 | }; | ||
| 414 | |||
| 380 | static struct omap_board_config_kernel h4_config[] = { | 415 | static struct omap_board_config_kernel h4_config[] = { |
| 381 | { OMAP_TAG_UART, &h4_uart_config }, | 416 | { OMAP_TAG_UART, &h4_uart_config }, |
| 382 | { OMAP_TAG_LCD, &h4_lcd_config }, | 417 | { OMAP_TAG_LCD, &h4_lcd_config }, |
| @@ -428,6 +463,7 @@ static void __init omap_h4_init(void) | |||
| 428 | platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); | 463 | platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices)); |
| 429 | omap_board_config = h4_config; | 464 | omap_board_config = h4_config; |
| 430 | omap_board_config_size = ARRAY_SIZE(h4_config); | 465 | omap_board_config_size = ARRAY_SIZE(h4_config); |
| 466 | omap_usb_init(&h4_usb_config); | ||
| 431 | omap_serial_init(); | 467 | omap_serial_init(); |
| 432 | } | 468 | } |
| 433 | 469 | ||
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index f6a13451d1fd..e096f776f996 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c | |||
| @@ -22,31 +22,34 @@ | |||
| 22 | #include <linux/spi/spi.h> | 22 | #include <linux/spi/spi.h> |
| 23 | #include <linux/spi/ads7846.h> | 23 | #include <linux/spi/ads7846.h> |
| 24 | #include <linux/i2c/twl4030.h> | 24 | #include <linux/i2c/twl4030.h> |
| 25 | #include <linux/io.h> | ||
| 25 | 26 | ||
| 26 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 27 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 28 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
| 29 | #include <asm/mach/map.h> | 30 | #include <asm/mach/map.h> |
| 30 | 31 | ||
| 31 | #include <mach/board-ldp.h> | ||
| 32 | #include <mach/mcspi.h> | 32 | #include <mach/mcspi.h> |
| 33 | #include <mach/gpio.h> | 33 | #include <mach/gpio.h> |
| 34 | #include <mach/board.h> | 34 | #include <mach/board.h> |
| 35 | #include <mach/common.h> | 35 | #include <mach/common.h> |
| 36 | #include <mach/gpmc.h> | 36 | #include <mach/gpmc.h> |
| 37 | 37 | ||
| 38 | #include <asm/io.h> | ||
| 39 | #include <asm/delay.h> | 38 | #include <asm/delay.h> |
| 40 | #include <mach/control.h> | 39 | #include <mach/control.h> |
| 40 | #include <mach/usb.h> | ||
| 41 | 41 | ||
| 42 | #include "mmc-twl4030.h" | 42 | #include "mmc-twl4030.h" |
| 43 | 43 | ||
| 44 | #define SDP3430_SMC91X_CS 3 | 44 | #define LDP_SMC911X_CS 1 |
| 45 | #define LDP_SMC911X_GPIO 152 | ||
| 46 | #define DEBUG_BASE 0x08000000 | ||
| 47 | #define LDP_ETHR_START DEBUG_BASE | ||
| 45 | 48 | ||
| 46 | static struct resource ldp_smc911x_resources[] = { | 49 | static struct resource ldp_smc911x_resources[] = { |
| 47 | [0] = { | 50 | [0] = { |
| 48 | .start = OMAP34XX_ETHR_START, | 51 | .start = LDP_ETHR_START, |
| 49 | .end = OMAP34XX_ETHR_START + SZ_4K, | 52 | .end = LDP_ETHR_START + SZ_4K, |
| 50 | .flags = IORESOURCE_MEM, | 53 | .flags = IORESOURCE_MEM, |
| 51 | }, | 54 | }, |
| 52 | [1] = { | 55 | [1] = { |
| @@ -81,7 +84,7 @@ static inline void __init ldp_init_smc911x(void) | |||
| 81 | } | 84 | } |
| 82 | 85 | ||
| 83 | ldp_smc911x_resources[0].start = cs_mem_base + 0x0; | 86 | ldp_smc911x_resources[0].start = cs_mem_base + 0x0; |
| 84 | ldp_smc911x_resources[0].end = cs_mem_base + 0xf; | 87 | ldp_smc911x_resources[0].end = cs_mem_base + 0xff; |
| 85 | udelay(100); | 88 | udelay(100); |
| 86 | 89 | ||
| 87 | eth_gpio = LDP_SMC911X_GPIO; | 90 | eth_gpio = LDP_SMC911X_GPIO; |
| @@ -98,7 +101,7 @@ static inline void __init ldp_init_smc911x(void) | |||
| 98 | 101 | ||
| 99 | static void __init omap_ldp_init_irq(void) | 102 | static void __init omap_ldp_init_irq(void) |
| 100 | { | 103 | { |
| 101 | omap2_init_common_hw(); | 104 | omap2_init_common_hw(NULL); |
| 102 | omap_init_irq(); | 105 | omap_init_irq(); |
| 103 | omap_gpio_init(); | 106 | omap_gpio_init(); |
| 104 | ldp_init_smc911x(); | 107 | ldp_init_smc911x(); |
| @@ -162,6 +165,7 @@ static void __init omap_ldp_init(void) | |||
| 162 | omap_board_config_size = ARRAY_SIZE(ldp_config); | 165 | omap_board_config_size = ARRAY_SIZE(ldp_config); |
| 163 | omap_serial_init(); | 166 | omap_serial_init(); |
| 164 | twl4030_mmc_init(mmc); | 167 | twl4030_mmc_init(mmc); |
| 168 | usb_musb_init(); | ||
| 165 | } | 169 | } |
| 166 | 170 | ||
| 167 | static void __init omap_ldp_map_io(void) | 171 | static void __init omap_ldp_map_io(void) |
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 38c88fbe658d..744740ae1b9c 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c | |||
| @@ -41,6 +41,7 @@ | |||
| 41 | #include <mach/gpmc.h> | 41 | #include <mach/gpmc.h> |
| 42 | #include <mach/nand.h> | 42 | #include <mach/nand.h> |
| 43 | #include <mach/mux.h> | 43 | #include <mach/mux.h> |
| 44 | #include <mach/usb.h> | ||
| 44 | 45 | ||
| 45 | #include "mmc-twl4030.h" | 46 | #include "mmc-twl4030.h" |
| 46 | 47 | ||
| @@ -175,16 +176,15 @@ static int __init omap3_beagle_i2c_init(void) | |||
| 175 | { | 176 | { |
| 176 | omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo, | 177 | omap_register_i2c_bus(1, 2600, beagle_i2c_boardinfo, |
| 177 | ARRAY_SIZE(beagle_i2c_boardinfo)); | 178 | ARRAY_SIZE(beagle_i2c_boardinfo)); |
| 178 | #ifdef CONFIG_I2C2_OMAP_BEAGLE | 179 | /* Bus 3 is attached to the DVI port where devices like the pico DLP |
| 179 | omap_register_i2c_bus(2, 400, NULL, 0); | 180 | * projector don't work reliably with 400kHz */ |
| 180 | #endif | 181 | omap_register_i2c_bus(3, 100, NULL, 0); |
| 181 | omap_register_i2c_bus(3, 400, NULL, 0); | ||
| 182 | return 0; | 182 | return 0; |
| 183 | } | 183 | } |
| 184 | 184 | ||
| 185 | static void __init omap3_beagle_init_irq(void) | 185 | static void __init omap3_beagle_init_irq(void) |
| 186 | { | 186 | { |
| 187 | omap2_init_common_hw(); | 187 | omap2_init_common_hw(NULL); |
| 188 | omap_init_irq(); | 188 | omap_init_irq(); |
| 189 | omap_gpio_init(); | 189 | omap_gpio_init(); |
| 190 | } | 190 | } |
| @@ -314,6 +314,7 @@ static void __init omap3_beagle_init(void) | |||
| 314 | /* REVISIT leave DVI powered down until it's needed ... */ | 314 | /* REVISIT leave DVI powered down until it's needed ... */ |
| 315 | gpio_direction_output(170, true); | 315 | gpio_direction_output(170, true); |
| 316 | 316 | ||
| 317 | usb_musb_init(); | ||
| 317 | omap3beagle_flash_init(); | 318 | omap3beagle_flash_init(); |
| 318 | } | 319 | } |
| 319 | 320 | ||
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index b3196107afdb..402f09c6cf10 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c | |||
| @@ -34,6 +34,7 @@ | |||
| 34 | #include <mach/gpio.h> | 34 | #include <mach/gpio.h> |
| 35 | #include <mach/hardware.h> | 35 | #include <mach/hardware.h> |
| 36 | #include <mach/mcspi.h> | 36 | #include <mach/mcspi.h> |
| 37 | #include <mach/usb.h> | ||
| 37 | 38 | ||
| 38 | #include "mmc-twl4030.h" | 39 | #include "mmc-twl4030.h" |
| 39 | 40 | ||
| @@ -53,6 +54,13 @@ static struct twl4030_hsmmc_info omap3pandora_mmc[] = { | |||
| 53 | .gpio_cd = -EINVAL, | 54 | .gpio_cd = -EINVAL, |
| 54 | .gpio_wp = 127, | 55 | .gpio_wp = 127, |
| 55 | .ext_clock = 1, | 56 | .ext_clock = 1, |
| 57 | .transceiver = true, | ||
| 58 | }, | ||
| 59 | { | ||
| 60 | .mmc = 3, | ||
| 61 | .wires = 4, | ||
| 62 | .gpio_cd = -EINVAL, | ||
| 63 | .gpio_wp = -EINVAL, | ||
| 56 | }, | 64 | }, |
| 57 | {} /* Terminator */ | 65 | {} /* Terminator */ |
| 58 | }; | 66 | }; |
| @@ -110,7 +118,7 @@ static int __init omap3pandora_i2c_init(void) | |||
| 110 | 118 | ||
| 111 | static void __init omap3pandora_init_irq(void) | 119 | static void __init omap3pandora_init_irq(void) |
| 112 | { | 120 | { |
| 113 | omap2_init_common_hw(); | 121 | omap2_init_common_hw(NULL); |
| 114 | omap_init_irq(); | 122 | omap_init_irq(); |
| 115 | omap_gpio_init(); | 123 | omap_gpio_init(); |
| 116 | } | 124 | } |
| @@ -193,6 +201,7 @@ static void __init omap3pandora_init(void) | |||
| 193 | spi_register_board_info(omap3pandora_spi_board_info, | 201 | spi_register_board_info(omap3pandora_spi_board_info, |
| 194 | ARRAY_SIZE(omap3pandora_spi_board_info)); | 202 | ARRAY_SIZE(omap3pandora_spi_board_info)); |
| 195 | omap3pandora_ads7846_init(); | 203 | omap3pandora_ads7846_init(); |
| 204 | usb_musb_init(); | ||
| 196 | } | 205 | } |
| 197 | 206 | ||
| 198 | static void __init omap3pandora_map_io(void) | 207 | static void __init omap3pandora_map_io(void) |
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 82b3dc557c96..b3f6e9d81807 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c | |||
| @@ -37,20 +37,85 @@ | |||
| 37 | #include <asm/mach/flash.h> | 37 | #include <asm/mach/flash.h> |
| 38 | #include <asm/mach/map.h> | 38 | #include <asm/mach/map.h> |
| 39 | 39 | ||
| 40 | #include <mach/board-overo.h> | ||
| 41 | #include <mach/board.h> | 40 | #include <mach/board.h> |
| 42 | #include <mach/common.h> | 41 | #include <mach/common.h> |
| 43 | #include <mach/gpio.h> | 42 | #include <mach/gpio.h> |
| 44 | #include <mach/gpmc.h> | 43 | #include <mach/gpmc.h> |
| 45 | #include <mach/hardware.h> | 44 | #include <mach/hardware.h> |
| 46 | #include <mach/nand.h> | 45 | #include <mach/nand.h> |
| 46 | #include <mach/usb.h> | ||
| 47 | 47 | ||
| 48 | #include "mmc-twl4030.h" | 48 | #include "mmc-twl4030.h" |
| 49 | 49 | ||
| 50 | #define OVERO_GPIO_BT_XGATE 15 | ||
| 51 | #define OVERO_GPIO_W2W_NRESET 16 | ||
| 52 | #define OVERO_GPIO_BT_NRESET 164 | ||
| 53 | #define OVERO_GPIO_USBH_CPEN 168 | ||
| 54 | #define OVERO_GPIO_USBH_NRESET 183 | ||
| 55 | |||
| 50 | #define NAND_BLOCK_SIZE SZ_128K | 56 | #define NAND_BLOCK_SIZE SZ_128K |
| 51 | #define GPMC_CS0_BASE 0x60 | 57 | #define GPMC_CS0_BASE 0x60 |
| 52 | #define GPMC_CS_SIZE 0x30 | 58 | #define GPMC_CS_SIZE 0x30 |
| 53 | 59 | ||
| 60 | #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ | ||
| 61 | defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) | ||
| 62 | |||
| 63 | #include <mach/mcspi.h> | ||
| 64 | #include <linux/spi/spi.h> | ||
| 65 | #include <linux/spi/ads7846.h> | ||
| 66 | |||
| 67 | static struct omap2_mcspi_device_config ads7846_mcspi_config = { | ||
| 68 | .turbo_mode = 0, | ||
| 69 | .single_channel = 1, /* 0: slave, 1: master */ | ||
| 70 | }; | ||
| 71 | |||
| 72 | static int ads7846_get_pendown_state(void) | ||
| 73 | { | ||
| 74 | return !gpio_get_value(OVERO_GPIO_PENDOWN); | ||
| 75 | } | ||
| 76 | |||
| 77 | static struct ads7846_platform_data ads7846_config = { | ||
| 78 | .x_max = 0x0fff, | ||
| 79 | .y_max = 0x0fff, | ||
| 80 | .x_plate_ohms = 180, | ||
| 81 | .pressure_max = 255, | ||
| 82 | .debounce_max = 10, | ||
| 83 | .debounce_tol = 3, | ||
| 84 | .debounce_rep = 1, | ||
| 85 | .get_pendown_state = ads7846_get_pendown_state, | ||
| 86 | .keep_vref_on = 1, | ||
| 87 | }; | ||
| 88 | |||
| 89 | static struct spi_board_info overo_spi_board_info[] __initdata = { | ||
| 90 | { | ||
| 91 | .modalias = "ads7846", | ||
| 92 | .bus_num = 1, | ||
| 93 | .chip_select = 0, | ||
| 94 | .max_speed_hz = 1500000, | ||
| 95 | .controller_data = &ads7846_mcspi_config, | ||
| 96 | .irq = OMAP_GPIO_IRQ(OVERO_GPIO_PENDOWN), | ||
| 97 | .platform_data = &ads7846_config, | ||
| 98 | } | ||
| 99 | }; | ||
| 100 | |||
| 101 | static void __init overo_ads7846_init(void) | ||
| 102 | { | ||
| 103 | if ((gpio_request(OVERO_GPIO_PENDOWN, "ADS7846_PENDOWN") == 0) && | ||
| 104 | (gpio_direction_input(OVERO_GPIO_PENDOWN) == 0)) { | ||
| 105 | gpio_export(OVERO_GPIO_PENDOWN, 0); | ||
| 106 | } else { | ||
| 107 | printk(KERN_ERR "could not obtain gpio for ADS7846_PENDOWN\n"); | ||
| 108 | return; | ||
| 109 | } | ||
| 110 | |||
| 111 | spi_register_board_info(overo_spi_board_info, | ||
| 112 | ARRAY_SIZE(overo_spi_board_info)); | ||
| 113 | } | ||
| 114 | |||
| 115 | #else | ||
| 116 | static inline void __init overo_ads7846_init(void) { return; } | ||
| 117 | #endif | ||
| 118 | |||
| 54 | static struct mtd_partition overo_nand_partitions[] = { | 119 | static struct mtd_partition overo_nand_partitions[] = { |
| 55 | { | 120 | { |
| 56 | .name = "xloader", | 121 | .name = "xloader", |
| @@ -174,7 +239,7 @@ static int __init overo_i2c_init(void) | |||
| 174 | 239 | ||
| 175 | static void __init overo_init_irq(void) | 240 | static void __init overo_init_irq(void) |
| 176 | { | 241 | { |
| 177 | omap2_init_common_hw(); | 242 | omap2_init_common_hw(NULL); |
| 178 | omap_init_irq(); | 243 | omap_init_irq(); |
| 179 | omap_gpio_init(); | 244 | omap_gpio_init(); |
| 180 | } | 245 | } |
| @@ -209,6 +274,7 @@ static struct twl4030_hsmmc_info mmc[] __initdata = { | |||
| 209 | .wires = 4, | 274 | .wires = 4, |
| 210 | .gpio_cd = -EINVAL, | 275 | .gpio_cd = -EINVAL, |
| 211 | .gpio_wp = -EINVAL, | 276 | .gpio_wp = -EINVAL, |
| 277 | .transceiver = true, | ||
| 212 | }, | 278 | }, |
| 213 | {} /* Terminator */ | 279 | {} /* Terminator */ |
| 214 | }; | 280 | }; |
| @@ -222,6 +288,8 @@ static void __init overo_init(void) | |||
| 222 | omap_serial_init(); | 288 | omap_serial_init(); |
| 223 | twl4030_mmc_init(mmc); | 289 | twl4030_mmc_init(mmc); |
| 224 | overo_flash_init(); | 290 | overo_flash_init(); |
| 291 | usb_musb_init(); | ||
| 292 | overo_ads7846_init(); | ||
| 225 | 293 | ||
| 226 | if ((gpio_request(OVERO_GPIO_W2W_NRESET, | 294 | if ((gpio_request(OVERO_GPIO_W2W_NRESET, |
| 227 | "OVERO_GPIO_W2W_NRESET") == 0) && | 295 | "OVERO_GPIO_W2W_NRESET") == 0) && |
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c new file mode 100644 index 000000000000..a7381729645c --- /dev/null +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c | |||
| @@ -0,0 +1,419 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/board-rx51-flash.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008-2009 Nokia | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/input.h> | ||
| 15 | #include <linux/spi/spi.h> | ||
| 16 | #include <linux/i2c.h> | ||
| 17 | #include <linux/i2c/twl4030.h> | ||
| 18 | #include <linux/clk.h> | ||
| 19 | #include <linux/delay.h> | ||
| 20 | #include <linux/regulator/machine.h> | ||
| 21 | #include <linux/gpio.h> | ||
| 22 | |||
| 23 | #include <mach/mcspi.h> | ||
| 24 | #include <mach/mux.h> | ||
| 25 | #include <mach/board.h> | ||
| 26 | #include <mach/common.h> | ||
| 27 | #include <mach/dma.h> | ||
| 28 | #include <mach/gpmc.h> | ||
| 29 | #include <mach/keypad.h> | ||
| 30 | |||
| 31 | #include "mmc-twl4030.h" | ||
| 32 | |||
| 33 | |||
| 34 | #define SMC91X_CS 1 | ||
| 35 | #define SMC91X_GPIO_IRQ 54 | ||
| 36 | #define SMC91X_GPIO_RESET 164 | ||
| 37 | #define SMC91X_GPIO_PWRDWN 86 | ||
| 38 | |||
| 39 | static struct resource rx51_smc91x_resources[] = { | ||
| 40 | [0] = { | ||
| 41 | .flags = IORESOURCE_MEM, | ||
| 42 | }, | ||
| 43 | [1] = { | ||
| 44 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, | ||
| 45 | }, | ||
| 46 | }; | ||
| 47 | |||
| 48 | static struct platform_device rx51_smc91x_device = { | ||
| 49 | .name = "smc91x", | ||
| 50 | .id = -1, | ||
| 51 | .num_resources = ARRAY_SIZE(rx51_smc91x_resources), | ||
| 52 | .resource = rx51_smc91x_resources, | ||
| 53 | }; | ||
| 54 | |||
| 55 | static int rx51_keymap[] = { | ||
| 56 | KEY(0, 0, KEY_Q), | ||
| 57 | KEY(0, 1, KEY_W), | ||
| 58 | KEY(0, 2, KEY_E), | ||
| 59 | KEY(0, 3, KEY_R), | ||
| 60 | KEY(0, 4, KEY_T), | ||
| 61 | KEY(0, 5, KEY_Y), | ||
| 62 | KEY(0, 6, KEY_U), | ||
| 63 | KEY(0, 7, KEY_I), | ||
| 64 | KEY(1, 0, KEY_O), | ||
| 65 | KEY(1, 1, KEY_D), | ||
| 66 | KEY(1, 2, KEY_DOT), | ||
| 67 | KEY(1, 3, KEY_V), | ||
| 68 | KEY(1, 4, KEY_DOWN), | ||
| 69 | KEY(2, 0, KEY_P), | ||
| 70 | KEY(2, 1, KEY_F), | ||
| 71 | KEY(2, 2, KEY_UP), | ||
| 72 | KEY(2, 3, KEY_B), | ||
| 73 | KEY(2, 4, KEY_RIGHT), | ||
| 74 | KEY(3, 0, KEY_COMMA), | ||
| 75 | KEY(3, 1, KEY_G), | ||
| 76 | KEY(3, 2, KEY_ENTER), | ||
| 77 | KEY(3, 3, KEY_N), | ||
| 78 | KEY(4, 0, KEY_BACKSPACE), | ||
| 79 | KEY(4, 1, KEY_H), | ||
| 80 | KEY(4, 3, KEY_M), | ||
| 81 | KEY(4, 4, KEY_LEFTCTRL), | ||
| 82 | KEY(5, 1, KEY_J), | ||
| 83 | KEY(5, 2, KEY_Z), | ||
| 84 | KEY(5, 3, KEY_SPACE), | ||
| 85 | KEY(5, 4, KEY_LEFTSHIFT), | ||
| 86 | KEY(6, 0, KEY_A), | ||
| 87 | KEY(6, 1, KEY_K), | ||
| 88 | KEY(6, 2, KEY_X), | ||
| 89 | KEY(6, 3, KEY_SPACE), | ||
| 90 | KEY(6, 4, KEY_FN), | ||
| 91 | KEY(7, 0, KEY_S), | ||
| 92 | KEY(7, 1, KEY_L), | ||
| 93 | KEY(7, 2, KEY_C), | ||
| 94 | KEY(7, 3, KEY_LEFT), | ||
| 95 | KEY(0xff, 0, KEY_F6), | ||
| 96 | KEY(0xff, 1, KEY_F7), | ||
| 97 | KEY(0xff, 2, KEY_F8), | ||
| 98 | KEY(0xff, 4, KEY_F9), | ||
| 99 | KEY(0xff, 5, KEY_F10), | ||
| 100 | }; | ||
| 101 | |||
| 102 | static struct twl4030_keypad_data rx51_kp_data = { | ||
| 103 | .rows = 8, | ||
| 104 | .cols = 8, | ||
| 105 | .keymap = rx51_keymap, | ||
| 106 | .keymapsize = ARRAY_SIZE(rx51_keymap), | ||
| 107 | .rep = 1, | ||
| 108 | }; | ||
| 109 | |||
| 110 | static struct platform_device *rx51_peripherals_devices[] = { | ||
| 111 | &rx51_smc91x_device, | ||
| 112 | }; | ||
| 113 | |||
| 114 | /* | ||
| 115 | * Timings are taken from smsc-lan91c96-ms.pdf | ||
| 116 | */ | ||
| 117 | static int smc91x_init_gpmc(int cs) | ||
| 118 | { | ||
| 119 | struct gpmc_timings t; | ||
| 120 | const int t2_r = 45; /* t2 in Figure 12.10 */ | ||
| 121 | const int t2_w = 30; /* t2 in Figure 12.11 */ | ||
| 122 | const int t3 = 15; /* t3 in Figure 12.10 */ | ||
| 123 | const int t5_r = 0; /* t5 in Figure 12.10 */ | ||
| 124 | const int t6_r = 45; /* t6 in Figure 12.10 */ | ||
| 125 | const int t6_w = 0; /* t6 in Figure 12.11 */ | ||
| 126 | const int t7_w = 15; /* t7 in Figure 12.11 */ | ||
| 127 | const int t15 = 12; /* t15 in Figure 12.2 */ | ||
| 128 | const int t20 = 185; /* t20 in Figure 12.2 */ | ||
| 129 | |||
| 130 | memset(&t, 0, sizeof(t)); | ||
| 131 | |||
| 132 | t.cs_on = t15; | ||
| 133 | t.cs_rd_off = t3 + t2_r + t5_r; /* Figure 12.10 */ | ||
| 134 | t.cs_wr_off = t3 + t2_w + t6_w; /* Figure 12.11 */ | ||
| 135 | t.adv_on = t3; /* Figure 12.10 */ | ||
| 136 | t.adv_rd_off = t3 + t2_r; /* Figure 12.10 */ | ||
| 137 | t.adv_wr_off = t3 + t2_w; /* Figure 12.11 */ | ||
| 138 | t.oe_off = t3 + t2_r + t5_r; /* Figure 12.10 */ | ||
| 139 | t.oe_on = t.oe_off - t6_r; /* Figure 12.10 */ | ||
| 140 | t.we_off = t3 + t2_w + t6_w; /* Figure 12.11 */ | ||
| 141 | t.we_on = t.we_off - t7_w; /* Figure 12.11 */ | ||
| 142 | t.rd_cycle = t20; /* Figure 12.2 */ | ||
| 143 | t.wr_cycle = t20; /* Figure 12.4 */ | ||
| 144 | t.access = t3 + t2_r + t5_r; /* Figure 12.10 */ | ||
| 145 | t.wr_access = t3 + t2_w + t6_w; /* Figure 12.11 */ | ||
| 146 | |||
| 147 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, GPMC_CONFIG1_DEVICESIZE_16); | ||
| 148 | |||
| 149 | return gpmc_cs_set_timings(cs, &t); | ||
| 150 | } | ||
| 151 | |||
| 152 | static void __init rx51_init_smc91x(void) | ||
| 153 | { | ||
| 154 | unsigned long cs_mem_base; | ||
| 155 | int ret; | ||
| 156 | |||
| 157 | omap_cfg_reg(U8_34XX_GPIO54_DOWN); | ||
| 158 | omap_cfg_reg(G25_34XX_GPIO86_OUT); | ||
| 159 | omap_cfg_reg(H19_34XX_GPIO164_OUT); | ||
| 160 | |||
| 161 | if (gpmc_cs_request(SMC91X_CS, SZ_16M, &cs_mem_base) < 0) { | ||
| 162 | printk(KERN_ERR "Failed to request GPMC mem for smc91x\n"); | ||
| 163 | return; | ||
| 164 | } | ||
| 165 | |||
| 166 | rx51_smc91x_resources[0].start = cs_mem_base + 0x300; | ||
| 167 | rx51_smc91x_resources[0].end = cs_mem_base + 0x30f; | ||
| 168 | |||
| 169 | smc91x_init_gpmc(SMC91X_CS); | ||
| 170 | |||
| 171 | if (gpio_request(SMC91X_GPIO_IRQ, "SMC91X irq") < 0) | ||
| 172 | goto free1; | ||
| 173 | |||
| 174 | gpio_direction_input(SMC91X_GPIO_IRQ); | ||
| 175 | rx51_smc91x_resources[1].start = gpio_to_irq(SMC91X_GPIO_IRQ); | ||
| 176 | |||
| 177 | ret = gpio_request(SMC91X_GPIO_PWRDWN, "SMC91X powerdown"); | ||
| 178 | if (ret) | ||
| 179 | goto free2; | ||
| 180 | gpio_direction_output(SMC91X_GPIO_PWRDWN, 0); | ||
| 181 | |||
| 182 | ret = gpio_request(SMC91X_GPIO_RESET, "SMC91X reset"); | ||
| 183 | if (ret) | ||
| 184 | goto free3; | ||
| 185 | gpio_direction_output(SMC91X_GPIO_RESET, 0); | ||
| 186 | gpio_set_value(SMC91X_GPIO_RESET, 1); | ||
| 187 | msleep(100); | ||
| 188 | gpio_set_value(SMC91X_GPIO_RESET, 0); | ||
| 189 | |||
| 190 | return; | ||
| 191 | |||
| 192 | free3: | ||
| 193 | gpio_free(SMC91X_GPIO_PWRDWN); | ||
| 194 | free2: | ||
| 195 | gpio_free(SMC91X_GPIO_IRQ); | ||
| 196 | free1: | ||
| 197 | gpmc_cs_free(SMC91X_CS); | ||
| 198 | |||
| 199 | printk(KERN_ERR "Could not initialize smc91x\n"); | ||
| 200 | } | ||
| 201 | |||
| 202 | static struct twl4030_madc_platform_data rx51_madc_data = { | ||
| 203 | .irq_line = 1, | ||
| 204 | }; | ||
| 205 | |||
| 206 | static struct twl4030_hsmmc_info mmc[] = { | ||
| 207 | { | ||
| 208 | .name = "external", | ||
| 209 | .mmc = 1, | ||
| 210 | .wires = 4, | ||
| 211 | .cover_only = true, | ||
| 212 | .gpio_cd = 160, | ||
| 213 | .gpio_wp = -EINVAL, | ||
| 214 | }, | ||
| 215 | { | ||
| 216 | .name = "internal", | ||
| 217 | .mmc = 2, | ||
| 218 | .wires = 8, | ||
| 219 | .gpio_cd = -EINVAL, | ||
| 220 | .gpio_wp = -EINVAL, | ||
| 221 | }, | ||
| 222 | {} /* Terminator */ | ||
| 223 | }; | ||
| 224 | |||
| 225 | static struct regulator_consumer_supply rx51_vmmc1_supply = { | ||
| 226 | .supply = "vmmc", | ||
| 227 | }; | ||
| 228 | |||
| 229 | static struct regulator_consumer_supply rx51_vmmc2_supply = { | ||
| 230 | .supply = "vmmc", | ||
| 231 | }; | ||
| 232 | |||
| 233 | static struct regulator_consumer_supply rx51_vsim_supply = { | ||
| 234 | .supply = "vmmc_aux", | ||
| 235 | }; | ||
| 236 | |||
| 237 | static struct regulator_init_data rx51_vaux1 = { | ||
| 238 | .constraints = { | ||
| 239 | .name = "V28", | ||
| 240 | .min_uV = 2800000, | ||
| 241 | .max_uV = 2800000, | ||
| 242 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 243 | | REGULATOR_MODE_STANDBY, | ||
| 244 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 245 | | REGULATOR_CHANGE_STATUS, | ||
| 246 | }, | ||
| 247 | }; | ||
| 248 | |||
| 249 | static struct regulator_init_data rx51_vaux2 = { | ||
| 250 | .constraints = { | ||
| 251 | .name = "VCSI", | ||
| 252 | .min_uV = 1800000, | ||
| 253 | .max_uV = 1800000, | ||
| 254 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 255 | | REGULATOR_MODE_STANDBY, | ||
| 256 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 257 | | REGULATOR_CHANGE_STATUS, | ||
| 258 | }, | ||
| 259 | }; | ||
| 260 | |||
| 261 | /* VAUX3 - adds more power to VIO_18 rail */ | ||
| 262 | static struct regulator_init_data rx51_vaux3 = { | ||
| 263 | .constraints = { | ||
| 264 | .name = "VCAM_DIG_18", | ||
| 265 | .min_uV = 1800000, | ||
| 266 | .max_uV = 1800000, | ||
| 267 | .apply_uV = true, | ||
| 268 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 269 | | REGULATOR_MODE_STANDBY, | ||
| 270 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 271 | | REGULATOR_CHANGE_STATUS, | ||
| 272 | }, | ||
| 273 | }; | ||
| 274 | |||
| 275 | static struct regulator_init_data rx51_vaux4 = { | ||
| 276 | .constraints = { | ||
| 277 | .name = "VCAM_ANA_28", | ||
| 278 | .min_uV = 2800000, | ||
| 279 | .max_uV = 2800000, | ||
| 280 | .apply_uV = true, | ||
| 281 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 282 | | REGULATOR_MODE_STANDBY, | ||
| 283 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 284 | | REGULATOR_CHANGE_STATUS, | ||
| 285 | }, | ||
| 286 | }; | ||
| 287 | |||
| 288 | static struct regulator_init_data rx51_vmmc1 = { | ||
| 289 | .constraints = { | ||
| 290 | .min_uV = 1850000, | ||
| 291 | .max_uV = 3150000, | ||
| 292 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 293 | | REGULATOR_MODE_STANDBY, | ||
| 294 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 295 | | REGULATOR_CHANGE_MODE | ||
| 296 | | REGULATOR_CHANGE_STATUS, | ||
| 297 | }, | ||
| 298 | .num_consumer_supplies = 1, | ||
| 299 | .consumer_supplies = &rx51_vmmc1_supply, | ||
| 300 | }; | ||
| 301 | |||
| 302 | static struct regulator_init_data rx51_vmmc2 = { | ||
| 303 | .constraints = { | ||
| 304 | .name = "VMMC2_30", | ||
| 305 | .min_uV = 1850000, | ||
| 306 | .max_uV = 3150000, | ||
| 307 | .apply_uV = true, | ||
| 308 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 309 | | REGULATOR_MODE_STANDBY, | ||
| 310 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 311 | | REGULATOR_CHANGE_MODE | ||
| 312 | | REGULATOR_CHANGE_STATUS, | ||
| 313 | }, | ||
| 314 | .num_consumer_supplies = 1, | ||
| 315 | .consumer_supplies = &rx51_vmmc2_supply, | ||
| 316 | }; | ||
| 317 | |||
| 318 | static struct regulator_init_data rx51_vsim = { | ||
| 319 | .constraints = { | ||
| 320 | .name = "VMMC2_IO_18", | ||
| 321 | .min_uV = 1800000, | ||
| 322 | .max_uV = 1800000, | ||
| 323 | .apply_uV = true, | ||
| 324 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 325 | | REGULATOR_MODE_STANDBY, | ||
| 326 | .valid_ops_mask = REGULATOR_CHANGE_MODE | ||
| 327 | | REGULATOR_CHANGE_STATUS, | ||
| 328 | }, | ||
| 329 | .num_consumer_supplies = 1, | ||
| 330 | .consumer_supplies = &rx51_vsim_supply, | ||
| 331 | }; | ||
| 332 | |||
| 333 | static struct regulator_init_data rx51_vdac = { | ||
| 334 | .constraints = { | ||
| 335 | .min_uV = 1800000, | ||
| 336 | .max_uV = 1800000, | ||
| 337 | .valid_modes_mask = REGULATOR_MODE_NORMAL | ||
| 338 | | REGULATOR_MODE_STANDBY, | ||
| 339 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | ||
| 340 | | REGULATOR_CHANGE_MODE | ||
| 341 | | REGULATOR_CHANGE_STATUS, | ||
| 342 | }, | ||
| 343 | }; | ||
| 344 | |||
| 345 | static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n) | ||
| 346 | { | ||
| 347 | /* FIXME this gpio setup is just a placeholder for now */ | ||
| 348 | gpio_request(gpio + 6, "backlight_pwm"); | ||
| 349 | gpio_direction_output(gpio + 6, 0); | ||
| 350 | gpio_request(gpio + 7, "speaker_en"); | ||
| 351 | gpio_direction_output(gpio + 7, 1); | ||
| 352 | |||
| 353 | /* set up MMC adapters, linking their regulators to them */ | ||
| 354 | twl4030_mmc_init(mmc); | ||
| 355 | rx51_vmmc1_supply.dev = mmc[0].dev; | ||
| 356 | rx51_vmmc2_supply.dev = mmc[1].dev; | ||
| 357 | rx51_vsim_supply.dev = mmc[1].dev; | ||
| 358 | |||
| 359 | return 0; | ||
| 360 | } | ||
| 361 | |||
| 362 | static struct twl4030_gpio_platform_data rx51_gpio_data = { | ||
| 363 | .gpio_base = OMAP_MAX_GPIO_LINES, | ||
| 364 | .irq_base = TWL4030_GPIO_IRQ_BASE, | ||
| 365 | .irq_end = TWL4030_GPIO_IRQ_END, | ||
| 366 | .pulldowns = BIT(0) | BIT(1) | BIT(2) | BIT(3) | ||
| 367 | | BIT(4) | BIT(5) | ||
| 368 | | BIT(8) | BIT(9) | BIT(10) | BIT(11) | ||
| 369 | | BIT(12) | BIT(13) | BIT(14) | BIT(15) | ||
| 370 | | BIT(16) | BIT(17) , | ||
| 371 | .setup = rx51_twlgpio_setup, | ||
| 372 | }; | ||
| 373 | |||
| 374 | static struct twl4030_platform_data rx51_twldata = { | ||
| 375 | .irq_base = TWL4030_IRQ_BASE, | ||
| 376 | .irq_end = TWL4030_IRQ_END, | ||
| 377 | |||
| 378 | /* platform_data for children goes here */ | ||
| 379 | .gpio = &rx51_gpio_data, | ||
| 380 | .keypad = &rx51_kp_data, | ||
| 381 | .madc = &rx51_madc_data, | ||
| 382 | |||
| 383 | .vaux1 = &rx51_vaux1, | ||
| 384 | .vaux2 = &rx51_vaux2, | ||
| 385 | .vaux3 = &rx51_vaux3, | ||
| 386 | .vaux4 = &rx51_vaux4, | ||
| 387 | .vmmc1 = &rx51_vmmc1, | ||
| 388 | .vmmc2 = &rx51_vmmc2, | ||
| 389 | .vsim = &rx51_vsim, | ||
| 390 | .vdac = &rx51_vdac, | ||
| 391 | }; | ||
| 392 | |||
| 393 | static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_1[] = { | ||
| 394 | { | ||
| 395 | I2C_BOARD_INFO("twl5030", 0x48), | ||
| 396 | .flags = I2C_CLIENT_WAKE, | ||
| 397 | .irq = INT_34XX_SYS_NIRQ, | ||
| 398 | .platform_data = &rx51_twldata, | ||
| 399 | }, | ||
| 400 | }; | ||
| 401 | |||
| 402 | static int __init rx51_i2c_init(void) | ||
| 403 | { | ||
| 404 | omap_register_i2c_bus(1, 2600, rx51_peripherals_i2c_board_info_1, | ||
| 405 | ARRAY_SIZE(rx51_peripherals_i2c_board_info_1)); | ||
| 406 | omap_register_i2c_bus(2, 100, NULL, 0); | ||
| 407 | omap_register_i2c_bus(3, 400, NULL, 0); | ||
| 408 | return 0; | ||
| 409 | } | ||
| 410 | |||
| 411 | |||
| 412 | void __init rx51_peripherals_init(void) | ||
| 413 | { | ||
| 414 | platform_add_devices(rx51_peripherals_devices, | ||
| 415 | ARRAY_SIZE(rx51_peripherals_devices)); | ||
| 416 | rx51_i2c_init(); | ||
| 417 | rx51_init_smc91x(); | ||
| 418 | } | ||
| 419 | |||
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c new file mode 100644 index 000000000000..3a0daac6c839 --- /dev/null +++ b/arch/arm/mach-omap2/board-rx51.c | |||
| @@ -0,0 +1,96 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/board-rx51.c | ||
| 3 | * | ||
| 4 | * Copyright (C) 2007, 2008 Nokia | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/delay.h> | ||
| 15 | #include <linux/err.h> | ||
| 16 | #include <linux/clk.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | #include <linux/delay.h> | ||
| 19 | #include <linux/gpio.h> | ||
| 20 | |||
| 21 | #include <mach/hardware.h> | ||
| 22 | #include <asm/mach-types.h> | ||
| 23 | #include <asm/mach/arch.h> | ||
| 24 | #include <asm/mach/map.h> | ||
| 25 | |||
| 26 | #include <mach/mcspi.h> | ||
| 27 | #include <mach/mux.h> | ||
| 28 | #include <mach/board.h> | ||
| 29 | #include <mach/common.h> | ||
| 30 | #include <mach/keypad.h> | ||
| 31 | #include <mach/dma.h> | ||
| 32 | #include <mach/gpmc.h> | ||
| 33 | #include <mach/usb.h> | ||
| 34 | |||
| 35 | static struct omap_uart_config rx51_uart_config = { | ||
| 36 | .enabled_uarts = ((1 << 0) | (1 << 1) | (1 << 2)), | ||
| 37 | }; | ||
| 38 | |||
| 39 | static struct omap_lcd_config rx51_lcd_config = { | ||
| 40 | .ctrl_name = "internal", | ||
| 41 | }; | ||
| 42 | |||
| 43 | static struct omap_fbmem_config rx51_fbmem0_config = { | ||
| 44 | .size = 752 * 1024, | ||
| 45 | }; | ||
| 46 | |||
| 47 | static struct omap_fbmem_config rx51_fbmem1_config = { | ||
| 48 | .size = 752 * 1024, | ||
| 49 | }; | ||
| 50 | |||
| 51 | static struct omap_fbmem_config rx51_fbmem2_config = { | ||
| 52 | .size = 752 * 1024, | ||
| 53 | }; | ||
| 54 | |||
| 55 | static struct omap_board_config_kernel rx51_config[] = { | ||
| 56 | { OMAP_TAG_UART, &rx51_uart_config }, | ||
| 57 | { OMAP_TAG_FBMEM, &rx51_fbmem0_config }, | ||
| 58 | { OMAP_TAG_FBMEM, &rx51_fbmem1_config }, | ||
| 59 | { OMAP_TAG_FBMEM, &rx51_fbmem2_config }, | ||
| 60 | { OMAP_TAG_LCD, &rx51_lcd_config }, | ||
| 61 | }; | ||
| 62 | |||
| 63 | static void __init rx51_init_irq(void) | ||
| 64 | { | ||
| 65 | omap2_init_common_hw(NULL); | ||
| 66 | omap_init_irq(); | ||
| 67 | omap_gpio_init(); | ||
| 68 | } | ||
| 69 | |||
| 70 | extern void __init rx51_peripherals_init(void); | ||
| 71 | |||
| 72 | static void __init rx51_init(void) | ||
| 73 | { | ||
| 74 | omap_board_config = rx51_config; | ||
| 75 | omap_board_config_size = ARRAY_SIZE(rx51_config); | ||
| 76 | omap_serial_init(); | ||
| 77 | usb_musb_init(); | ||
| 78 | rx51_peripherals_init(); | ||
| 79 | } | ||
| 80 | |||
| 81 | static void __init rx51_map_io(void) | ||
| 82 | { | ||
| 83 | omap2_set_globals_343x(); | ||
| 84 | omap2_map_common_io(); | ||
| 85 | } | ||
| 86 | |||
| 87 | MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") | ||
| 88 | /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */ | ||
| 89 | .phys_io = 0x48000000, | ||
| 90 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | ||
| 91 | .boot_params = 0x80000100, | ||
| 92 | .map_io = rx51_map_io, | ||
| 93 | .init_irq = rx51_init_irq, | ||
| 94 | .init_machine = rx51_init, | ||
| 95 | .timer = &omap_timer, | ||
| 96 | MACHINE_END | ||
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index ce4d46a4a838..4247a1534411 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
| @@ -26,11 +26,10 @@ | |||
| 26 | 26 | ||
| 27 | #include <mach/clock.h> | 27 | #include <mach/clock.h> |
| 28 | #include <mach/clockdomain.h> | 28 | #include <mach/clockdomain.h> |
| 29 | #include <mach/sram.h> | ||
| 30 | #include <mach/cpu.h> | 29 | #include <mach/cpu.h> |
| 31 | #include <asm/div64.h> | 30 | #include <asm/div64.h> |
| 32 | 31 | ||
| 33 | #include "memory.h" | 32 | #include <mach/sdrc.h> |
| 34 | #include "sdrc.h" | 33 | #include "sdrc.h" |
| 35 | #include "clock.h" | 34 | #include "clock.h" |
| 36 | #include "prm.h" | 35 | #include "prm.h" |
| @@ -46,7 +45,7 @@ | |||
| 46 | #define DPLL_MIN_DIVIDER 1 | 45 | #define DPLL_MIN_DIVIDER 1 |
| 47 | 46 | ||
| 48 | /* Possible error results from _dpll_test_mult */ | 47 | /* Possible error results from _dpll_test_mult */ |
| 49 | #define DPLL_MULT_UNDERFLOW (1 << 0) | 48 | #define DPLL_MULT_UNDERFLOW -1 |
| 50 | 49 | ||
| 51 | /* | 50 | /* |
| 52 | * Scale factor to mitigate roundoff errors in DPLL rate rounding. | 51 | * Scale factor to mitigate roundoff errors in DPLL rate rounding. |
| @@ -59,6 +58,16 @@ | |||
| 59 | #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ | 58 | #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ |
| 60 | (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) | 59 | (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) |
| 61 | 60 | ||
| 61 | /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ | ||
| 62 | #define DPLL_FINT_BAND1_MIN 750000 | ||
| 63 | #define DPLL_FINT_BAND1_MAX 2100000 | ||
| 64 | #define DPLL_FINT_BAND2_MIN 7500000 | ||
| 65 | #define DPLL_FINT_BAND2_MAX 21000000 | ||
| 66 | |||
| 67 | /* _dpll_test_fint() return codes */ | ||
| 68 | #define DPLL_FINT_UNDERFLOW -1 | ||
| 69 | #define DPLL_FINT_INVALID -2 | ||
| 70 | |||
| 62 | u8 cpu_mask; | 71 | u8 cpu_mask; |
| 63 | 72 | ||
| 64 | /*------------------------------------------------------------------------- | 73 | /*------------------------------------------------------------------------- |
| @@ -66,6 +75,74 @@ u8 cpu_mask; | |||
| 66 | *-------------------------------------------------------------------------*/ | 75 | *-------------------------------------------------------------------------*/ |
| 67 | 76 | ||
| 68 | /** | 77 | /** |
| 78 | * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware | ||
| 79 | * @clk: struct clk * | ||
| 80 | * | ||
| 81 | * If @clk has the DELAYED_APP flag set, meaning that parent/rate changes | ||
| 82 | * don't take effect until the VALID_CONFIG bit is written, write the | ||
| 83 | * VALID_CONFIG bit and wait for the write to complete. No return value. | ||
| 84 | */ | ||
| 85 | static void _omap2xxx_clk_commit(struct clk *clk) | ||
| 86 | { | ||
| 87 | if (!cpu_is_omap24xx()) | ||
| 88 | return; | ||
| 89 | |||
| 90 | if (!(clk->flags & DELAYED_APP)) | ||
| 91 | return; | ||
| 92 | |||
| 93 | prm_write_mod_reg(OMAP24XX_VALID_CONFIG, OMAP24XX_GR_MOD, | ||
| 94 | OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); | ||
| 95 | /* OCP barrier */ | ||
| 96 | prm_read_mod_reg(OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); | ||
| 97 | } | ||
| 98 | |||
| 99 | /* | ||
| 100 | * _dpll_test_fint - test whether an Fint value is valid for the DPLL | ||
| 101 | * @clk: DPLL struct clk to test | ||
| 102 | * @n: divider value (N) to test | ||
| 103 | * | ||
| 104 | * Tests whether a particular divider @n will result in a valid DPLL | ||
| 105 | * internal clock frequency Fint. See the 34xx TRM 4.7.6.2 "DPLL Jitter | ||
| 106 | * Correction". Returns 0 if OK, -1 if the enclosing loop can terminate | ||
| 107 | * (assuming that it is counting N upwards), or -2 if the enclosing loop | ||
| 108 | * should skip to the next iteration (again assuming N is increasing). | ||
| 109 | */ | ||
| 110 | static int _dpll_test_fint(struct clk *clk, u8 n) | ||
| 111 | { | ||
| 112 | struct dpll_data *dd; | ||
| 113 | long fint; | ||
| 114 | int ret = 0; | ||
| 115 | |||
| 116 | dd = clk->dpll_data; | ||
| 117 | |||
| 118 | /* DPLL divider must result in a valid jitter correction val */ | ||
| 119 | fint = clk->parent->rate / (n + 1); | ||
| 120 | if (fint < DPLL_FINT_BAND1_MIN) { | ||
| 121 | |||
| 122 | pr_debug("rejecting n=%d due to Fint failure, " | ||
| 123 | "lowering max_divider\n", n); | ||
| 124 | dd->max_divider = n; | ||
| 125 | ret = DPLL_FINT_UNDERFLOW; | ||
| 126 | |||
| 127 | } else if (fint > DPLL_FINT_BAND1_MAX && | ||
| 128 | fint < DPLL_FINT_BAND2_MIN) { | ||
| 129 | |||
| 130 | pr_debug("rejecting n=%d due to Fint failure\n", n); | ||
| 131 | ret = DPLL_FINT_INVALID; | ||
| 132 | |||
| 133 | } else if (fint > DPLL_FINT_BAND2_MAX) { | ||
| 134 | |||
| 135 | pr_debug("rejecting n=%d due to Fint failure, " | ||
| 136 | "boosting min_divider\n", n); | ||
| 137 | dd->min_divider = n; | ||
| 138 | ret = DPLL_FINT_INVALID; | ||
| 139 | |||
| 140 | } | ||
| 141 | |||
| 142 | return ret; | ||
| 143 | } | ||
| 144 | |||
| 145 | /** | ||
| 69 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk | 146 | * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk |
| 70 | * @clk: OMAP clock struct ptr to use | 147 | * @clk: OMAP clock struct ptr to use |
| 71 | * | 148 | * |
| @@ -120,7 +197,7 @@ void omap2_init_clksel_parent(struct clk *clk) | |||
| 120 | clk->name, clks->parent->name, | 197 | clk->name, clks->parent->name, |
| 121 | ((clk->parent) ? | 198 | ((clk->parent) ? |
| 122 | clk->parent->name : "NULL")); | 199 | clk->parent->name : "NULL")); |
| 123 | clk->parent = clks->parent; | 200 | clk_reparent(clk, clks->parent); |
| 124 | }; | 201 | }; |
| 125 | found = 1; | 202 | found = 1; |
| 126 | } | 203 | } |
| @@ -134,25 +211,52 @@ void omap2_init_clksel_parent(struct clk *clk) | |||
| 134 | return; | 211 | return; |
| 135 | } | 212 | } |
| 136 | 213 | ||
| 137 | /* Returns the DPLL rate */ | 214 | /** |
| 215 | * omap2_get_dpll_rate - returns the current DPLL CLKOUT rate | ||
| 216 | * @clk: struct clk * of a DPLL | ||
| 217 | * | ||
| 218 | * DPLLs can be locked or bypassed - basically, enabled or disabled. | ||
| 219 | * When locked, the DPLL output depends on the M and N values. When | ||
| 220 | * bypassed, on OMAP2xxx, the output rate is either the 32KiHz clock | ||
| 221 | * or sys_clk. Bypass rates on OMAP3 depend on the DPLL: DPLLs 1 and | ||
| 222 | * 2 are bypassed with dpll1_fclk and dpll2_fclk respectively | ||
| 223 | * (generated by DPLL3), while DPLL 3, 4, and 5 bypass rates are sys_clk. | ||
| 224 | * Returns the current DPLL CLKOUT rate (*not* CLKOUTX2) if the DPLL is | ||
| 225 | * locked, or the appropriate bypass rate if the DPLL is bypassed, or 0 | ||
| 226 | * if the clock @clk is not a DPLL. | ||
| 227 | */ | ||
| 138 | u32 omap2_get_dpll_rate(struct clk *clk) | 228 | u32 omap2_get_dpll_rate(struct clk *clk) |
| 139 | { | 229 | { |
| 140 | long long dpll_clk; | 230 | long long dpll_clk; |
| 141 | u32 dpll_mult, dpll_div, dpll; | 231 | u32 dpll_mult, dpll_div, v; |
| 142 | struct dpll_data *dd; | 232 | struct dpll_data *dd; |
| 143 | 233 | ||
| 144 | dd = clk->dpll_data; | 234 | dd = clk->dpll_data; |
| 145 | /* REVISIT: What do we return on error? */ | ||
| 146 | if (!dd) | 235 | if (!dd) |
| 147 | return 0; | 236 | return 0; |
| 148 | 237 | ||
| 149 | dpll = __raw_readl(dd->mult_div1_reg); | 238 | /* Return bypass rate if DPLL is bypassed */ |
| 150 | dpll_mult = dpll & dd->mult_mask; | 239 | v = __raw_readl(dd->control_reg); |
| 240 | v &= dd->enable_mask; | ||
| 241 | v >>= __ffs(dd->enable_mask); | ||
| 242 | |||
| 243 | if (cpu_is_omap24xx()) { | ||
| 244 | if (v == OMAP2XXX_EN_DPLL_LPBYPASS || | ||
| 245 | v == OMAP2XXX_EN_DPLL_FRBYPASS) | ||
| 246 | return dd->clk_bypass->rate; | ||
| 247 | } else if (cpu_is_omap34xx()) { | ||
| 248 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || | ||
| 249 | v == OMAP3XXX_EN_DPLL_FRBYPASS) | ||
| 250 | return dd->clk_bypass->rate; | ||
| 251 | } | ||
| 252 | |||
| 253 | v = __raw_readl(dd->mult_div1_reg); | ||
| 254 | dpll_mult = v & dd->mult_mask; | ||
| 151 | dpll_mult >>= __ffs(dd->mult_mask); | 255 | dpll_mult >>= __ffs(dd->mult_mask); |
| 152 | dpll_div = dpll & dd->div1_mask; | 256 | dpll_div = v & dd->div1_mask; |
| 153 | dpll_div >>= __ffs(dd->div1_mask); | 257 | dpll_div >>= __ffs(dd->div1_mask); |
| 154 | 258 | ||
| 155 | dpll_clk = (long long)clk->parent->rate * dpll_mult; | 259 | dpll_clk = (long long)dd->clk_ref->rate * dpll_mult; |
| 156 | do_div(dpll_clk, dpll_div + 1); | 260 | do_div(dpll_clk, dpll_div + 1); |
| 157 | 261 | ||
| 158 | return dpll_clk; | 262 | return dpll_clk; |
| @@ -162,14 +266,11 @@ u32 omap2_get_dpll_rate(struct clk *clk) | |||
| 162 | * Used for clocks that have the same value as the parent clock, | 266 | * Used for clocks that have the same value as the parent clock, |
| 163 | * divided by some factor | 267 | * divided by some factor |
| 164 | */ | 268 | */ |
| 165 | void omap2_fixed_divisor_recalc(struct clk *clk) | 269 | unsigned long omap2_fixed_divisor_recalc(struct clk *clk) |
| 166 | { | 270 | { |
| 167 | WARN_ON(!clk->fixed_div); | 271 | WARN_ON(!clk->fixed_div); |
| 168 | 272 | ||
| 169 | clk->rate = clk->parent->rate / clk->fixed_div; | 273 | return clk->parent->rate / clk->fixed_div; |
| 170 | |||
| 171 | if (clk->flags & RATE_PROPAGATES) | ||
| 172 | propagate_rate(clk); | ||
| 173 | } | 274 | } |
| 174 | 275 | ||
| 175 | /** | 276 | /** |
| @@ -190,11 +291,10 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name) | |||
| 190 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | 291 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. |
| 191 | * 34xx reverses this, just to keep us on our toes | 292 | * 34xx reverses this, just to keep us on our toes |
| 192 | */ | 293 | */ |
| 193 | if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) { | 294 | if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) |
| 194 | ena = mask; | 295 | ena = mask; |
| 195 | } else if (cpu_mask & RATE_IN_343X) { | 296 | else if (cpu_mask & RATE_IN_343X) |
| 196 | ena = 0; | 297 | ena = 0; |
| 197 | } | ||
| 198 | 298 | ||
| 199 | /* Wait for lock */ | 299 | /* Wait for lock */ |
| 200 | while (((__raw_readl(reg) & mask) != ena) && | 300 | while (((__raw_readl(reg) & mask) != ena) && |
| @@ -228,31 +328,12 @@ static void omap2_clk_wait_ready(struct clk *clk) | |||
| 228 | * it and pull it into struct clk itself somehow. | 328 | * it and pull it into struct clk itself somehow. |
| 229 | */ | 329 | */ |
| 230 | reg = clk->enable_reg; | 330 | reg = clk->enable_reg; |
| 231 | if ((((u32)reg & 0xff) >= CM_FCLKEN1) && | ||
| 232 | (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2)) | ||
| 233 | other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */ | ||
| 234 | else if ((((u32)reg & 0xff) >= CM_ICLKEN1) && | ||
| 235 | (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4)) | ||
| 236 | other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */ | ||
| 237 | else | ||
| 238 | return; | ||
| 239 | 331 | ||
| 240 | /* REVISIT: What are the appropriate exclusions for 34XX? */ | 332 | /* |
| 241 | /* No check for DSS or cam clocks */ | 333 | * Convert CM_ICLKEN* <-> CM_FCLKEN*. This conversion assumes |
| 242 | if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */ | 334 | * it's just a matter of XORing the bits. |
| 243 | if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT || | 335 | */ |
| 244 | clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT || | 336 | other_reg = (void __iomem *)((u32)reg ^ (CM_FCLKEN ^ CM_ICLKEN)); |
| 245 | clk->enable_bit == OMAP24XX_EN_CAM_SHIFT) | ||
| 246 | return; | ||
| 247 | } | ||
| 248 | |||
| 249 | /* REVISIT: What are the appropriate exclusions for 34XX? */ | ||
| 250 | /* OMAP3: ignore DSS-mod clocks */ | ||
| 251 | if (cpu_is_omap34xx() && | ||
| 252 | (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0) || | ||
| 253 | ((((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(CORE_MOD, 0)) && | ||
| 254 | clk->enable_bit == OMAP3430_EN_SSI_SHIFT))) | ||
| 255 | return; | ||
| 256 | 337 | ||
| 257 | /* Check if both functional and interface clocks | 338 | /* Check if both functional and interface clocks |
| 258 | * are running. */ | 339 | * are running. */ |
| @@ -264,18 +345,9 @@ static void omap2_clk_wait_ready(struct clk *clk) | |||
| 264 | omap2_wait_clock_ready(st_reg, bit, clk->name); | 345 | omap2_wait_clock_ready(st_reg, bit, clk->name); |
| 265 | } | 346 | } |
| 266 | 347 | ||
| 267 | /* Enables clock without considering parent dependencies or use count | 348 | static int omap2_dflt_clk_enable(struct clk *clk) |
| 268 | * REVISIT: Maybe change this to use clk->enable like on omap1? | ||
| 269 | */ | ||
| 270 | int _omap2_clk_enable(struct clk *clk) | ||
| 271 | { | 349 | { |
| 272 | u32 regval32; | 350 | u32 v; |
| 273 | |||
| 274 | if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) | ||
| 275 | return 0; | ||
| 276 | |||
| 277 | if (clk->enable) | ||
| 278 | return clk->enable(clk); | ||
| 279 | 351 | ||
| 280 | if (unlikely(clk->enable_reg == NULL)) { | 352 | if (unlikely(clk->enable_reg == NULL)) { |
| 281 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", | 353 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", |
| @@ -283,33 +355,38 @@ int _omap2_clk_enable(struct clk *clk) | |||
| 283 | return 0; /* REVISIT: -EINVAL */ | 355 | return 0; /* REVISIT: -EINVAL */ |
| 284 | } | 356 | } |
| 285 | 357 | ||
| 286 | regval32 = __raw_readl(clk->enable_reg); | 358 | v = __raw_readl(clk->enable_reg); |
| 287 | if (clk->flags & INVERT_ENABLE) | 359 | if (clk->flags & INVERT_ENABLE) |
| 288 | regval32 &= ~(1 << clk->enable_bit); | 360 | v &= ~(1 << clk->enable_bit); |
| 289 | else | 361 | else |
| 290 | regval32 |= (1 << clk->enable_bit); | 362 | v |= (1 << clk->enable_bit); |
| 291 | __raw_writel(regval32, clk->enable_reg); | 363 | __raw_writel(v, clk->enable_reg); |
| 292 | wmb(); | 364 | v = __raw_readl(clk->enable_reg); /* OCP barrier */ |
| 293 | |||
| 294 | omap2_clk_wait_ready(clk); | ||
| 295 | 365 | ||
| 296 | return 0; | 366 | return 0; |
| 297 | } | 367 | } |
| 298 | 368 | ||
| 299 | /* Disables clock without considering parent dependencies or use count */ | 369 | static int omap2_dflt_clk_enable_wait(struct clk *clk) |
| 300 | void _omap2_clk_disable(struct clk *clk) | ||
| 301 | { | 370 | { |
| 302 | u32 regval32; | 371 | int ret; |
| 303 | |||
| 304 | if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK)) | ||
| 305 | return; | ||
| 306 | 372 | ||
| 307 | if (clk->disable) { | 373 | if (!clk->enable_reg) { |
| 308 | clk->disable(clk); | 374 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", |
| 309 | return; | 375 | clk->name); |
| 376 | return 0; /* REVISIT: -EINVAL */ | ||
| 310 | } | 377 | } |
| 311 | 378 | ||
| 312 | if (clk->enable_reg == NULL) { | 379 | ret = omap2_dflt_clk_enable(clk); |
| 380 | if (ret == 0) | ||
| 381 | omap2_clk_wait_ready(clk); | ||
| 382 | return ret; | ||
| 383 | } | ||
| 384 | |||
| 385 | static void omap2_dflt_clk_disable(struct clk *clk) | ||
| 386 | { | ||
| 387 | u32 v; | ||
| 388 | |||
| 389 | if (!clk->enable_reg) { | ||
| 313 | /* | 390 | /* |
| 314 | * 'Independent' here refers to a clock which is not | 391 | * 'Independent' here refers to a clock which is not |
| 315 | * controlled by its parent. | 392 | * controlled by its parent. |
| @@ -319,20 +396,44 @@ void _omap2_clk_disable(struct clk *clk) | |||
| 319 | return; | 396 | return; |
| 320 | } | 397 | } |
| 321 | 398 | ||
| 322 | regval32 = __raw_readl(clk->enable_reg); | 399 | v = __raw_readl(clk->enable_reg); |
| 323 | if (clk->flags & INVERT_ENABLE) | 400 | if (clk->flags & INVERT_ENABLE) |
| 324 | regval32 |= (1 << clk->enable_bit); | 401 | v |= (1 << clk->enable_bit); |
| 325 | else | 402 | else |
| 326 | regval32 &= ~(1 << clk->enable_bit); | 403 | v &= ~(1 << clk->enable_bit); |
| 327 | __raw_writel(regval32, clk->enable_reg); | 404 | __raw_writel(v, clk->enable_reg); |
| 328 | wmb(); | 405 | /* No OCP barrier needed here since it is a disable operation */ |
| 406 | } | ||
| 407 | |||
| 408 | const struct clkops clkops_omap2_dflt_wait = { | ||
| 409 | .enable = omap2_dflt_clk_enable_wait, | ||
| 410 | .disable = omap2_dflt_clk_disable, | ||
| 411 | }; | ||
| 412 | |||
| 413 | const struct clkops clkops_omap2_dflt = { | ||
| 414 | .enable = omap2_dflt_clk_enable, | ||
| 415 | .disable = omap2_dflt_clk_disable, | ||
| 416 | }; | ||
| 417 | |||
| 418 | /* Enables clock without considering parent dependencies or use count | ||
| 419 | * REVISIT: Maybe change this to use clk->enable like on omap1? | ||
| 420 | */ | ||
| 421 | static int _omap2_clk_enable(struct clk *clk) | ||
| 422 | { | ||
| 423 | return clk->ops->enable(clk); | ||
| 424 | } | ||
| 425 | |||
| 426 | /* Disables clock without considering parent dependencies or use count */ | ||
| 427 | static void _omap2_clk_disable(struct clk *clk) | ||
| 428 | { | ||
| 429 | clk->ops->disable(clk); | ||
| 329 | } | 430 | } |
| 330 | 431 | ||
| 331 | void omap2_clk_disable(struct clk *clk) | 432 | void omap2_clk_disable(struct clk *clk) |
| 332 | { | 433 | { |
| 333 | if (clk->usecount > 0 && !(--clk->usecount)) { | 434 | if (clk->usecount > 0 && !(--clk->usecount)) { |
| 334 | _omap2_clk_disable(clk); | 435 | _omap2_clk_disable(clk); |
| 335 | if (likely((u32)clk->parent)) | 436 | if (clk->parent) |
| 336 | omap2_clk_disable(clk->parent); | 437 | omap2_clk_disable(clk->parent); |
| 337 | if (clk->clkdm) | 438 | if (clk->clkdm) |
| 338 | omap2_clkdm_clk_disable(clk->clkdm, clk); | 439 | omap2_clkdm_clk_disable(clk->clkdm, clk); |
| @@ -345,30 +446,29 @@ int omap2_clk_enable(struct clk *clk) | |||
| 345 | int ret = 0; | 446 | int ret = 0; |
| 346 | 447 | ||
| 347 | if (clk->usecount++ == 0) { | 448 | if (clk->usecount++ == 0) { |
| 348 | if (likely((u32)clk->parent)) | ||
| 349 | ret = omap2_clk_enable(clk->parent); | ||
| 350 | |||
| 351 | if (unlikely(ret != 0)) { | ||
| 352 | clk->usecount--; | ||
| 353 | return ret; | ||
| 354 | } | ||
| 355 | |||
| 356 | if (clk->clkdm) | 449 | if (clk->clkdm) |
| 357 | omap2_clkdm_clk_enable(clk->clkdm, clk); | 450 | omap2_clkdm_clk_enable(clk->clkdm, clk); |
| 358 | 451 | ||
| 359 | ret = _omap2_clk_enable(clk); | 452 | if (clk->parent) { |
| 360 | 453 | ret = omap2_clk_enable(clk->parent); | |
| 361 | if (unlikely(ret != 0)) { | 454 | if (ret) |
| 362 | if (clk->clkdm) | 455 | goto err; |
| 363 | omap2_clkdm_clk_disable(clk->clkdm, clk); | 456 | } |
| 364 | 457 | ||
| 365 | if (clk->parent) { | 458 | ret = _omap2_clk_enable(clk); |
| 459 | if (ret) { | ||
| 460 | if (clk->parent) | ||
| 366 | omap2_clk_disable(clk->parent); | 461 | omap2_clk_disable(clk->parent); |
| 367 | clk->usecount--; | 462 | |
| 368 | } | 463 | goto err; |
| 369 | } | 464 | } |
| 370 | } | 465 | } |
| 466 | return ret; | ||
| 371 | 467 | ||
| 468 | err: | ||
| 469 | if (clk->clkdm) | ||
| 470 | omap2_clkdm_clk_disable(clk->clkdm, clk); | ||
| 471 | clk->usecount--; | ||
| 372 | return ret; | 472 | return ret; |
| 373 | } | 473 | } |
| 374 | 474 | ||
| @@ -376,24 +476,22 @@ int omap2_clk_enable(struct clk *clk) | |||
| 376 | * Used for clocks that are part of CLKSEL_xyz governed clocks. | 476 | * Used for clocks that are part of CLKSEL_xyz governed clocks. |
| 377 | * REVISIT: Maybe change to use clk->enable() functions like on omap1? | 477 | * REVISIT: Maybe change to use clk->enable() functions like on omap1? |
| 378 | */ | 478 | */ |
| 379 | void omap2_clksel_recalc(struct clk *clk) | 479 | unsigned long omap2_clksel_recalc(struct clk *clk) |
| 380 | { | 480 | { |
| 481 | unsigned long rate; | ||
| 381 | u32 div = 0; | 482 | u32 div = 0; |
| 382 | 483 | ||
| 383 | pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); | 484 | pr_debug("clock: recalc'ing clksel clk %s\n", clk->name); |
| 384 | 485 | ||
| 385 | div = omap2_clksel_get_divisor(clk); | 486 | div = omap2_clksel_get_divisor(clk); |
| 386 | if (div == 0) | 487 | if (div == 0) |
| 387 | return; | 488 | return clk->rate; |
| 388 | 489 | ||
| 389 | if (unlikely(clk->rate == clk->parent->rate / div)) | 490 | rate = clk->parent->rate / div; |
| 390 | return; | ||
| 391 | clk->rate = clk->parent->rate / div; | ||
| 392 | 491 | ||
| 393 | pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div); | 492 | pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div); |
| 394 | 493 | ||
| 395 | if (unlikely(clk->flags & RATE_PROPAGATES)) | 494 | return rate; |
| 396 | propagate_rate(clk); | ||
| 397 | } | 495 | } |
| 398 | 496 | ||
| 399 | /** | 497 | /** |
| @@ -405,8 +503,8 @@ void omap2_clksel_recalc(struct clk *clk) | |||
| 405 | * the element associated with the supplied parent clock address. | 503 | * the element associated with the supplied parent clock address. |
| 406 | * Returns a pointer to the struct clksel on success or NULL on error. | 504 | * Returns a pointer to the struct clksel on success or NULL on error. |
| 407 | */ | 505 | */ |
| 408 | const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, | 506 | static const struct clksel *omap2_get_clksel_by_parent(struct clk *clk, |
| 409 | struct clk *src_clk) | 507 | struct clk *src_clk) |
| 410 | { | 508 | { |
| 411 | const struct clksel *clks; | 509 | const struct clksel *clks; |
| 412 | 510 | ||
| @@ -455,7 +553,7 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |||
| 455 | *new_div = 1; | 553 | *new_div = 1; |
| 456 | 554 | ||
| 457 | clks = omap2_get_clksel_by_parent(clk, clk->parent); | 555 | clks = omap2_get_clksel_by_parent(clk, clk->parent); |
| 458 | if (clks == NULL) | 556 | if (!clks) |
| 459 | return ~0; | 557 | return ~0; |
| 460 | 558 | ||
| 461 | for (clkr = clks->rates; clkr->div; clkr++) { | 559 | for (clkr = clks->rates; clkr->div; clkr++) { |
| @@ -514,7 +612,7 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) | |||
| 514 | /* Given a clock and a rate apply a clock specific rounding function */ | 612 | /* Given a clock and a rate apply a clock specific rounding function */ |
| 515 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate) | 613 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate) |
| 516 | { | 614 | { |
| 517 | if (clk->round_rate != NULL) | 615 | if (clk->round_rate) |
| 518 | return clk->round_rate(clk, rate); | 616 | return clk->round_rate(clk, rate); |
| 519 | 617 | ||
| 520 | if (clk->flags & RATE_FIXED) | 618 | if (clk->flags & RATE_FIXED) |
| @@ -540,7 +638,7 @@ u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val) | |||
| 540 | const struct clksel_rate *clkr; | 638 | const struct clksel_rate *clkr; |
| 541 | 639 | ||
| 542 | clks = omap2_get_clksel_by_parent(clk, clk->parent); | 640 | clks = omap2_get_clksel_by_parent(clk, clk->parent); |
| 543 | if (clks == NULL) | 641 | if (!clks) |
| 544 | return 0; | 642 | return 0; |
| 545 | 643 | ||
| 546 | for (clkr = clks->rates; clkr->div; clkr++) { | 644 | for (clkr = clks->rates; clkr->div; clkr++) { |
| @@ -576,7 +674,7 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) | |||
| 576 | WARN_ON(div == 0); | 674 | WARN_ON(div == 0); |
| 577 | 675 | ||
| 578 | clks = omap2_get_clksel_by_parent(clk, clk->parent); | 676 | clks = omap2_get_clksel_by_parent(clk, clk->parent); |
| 579 | if (clks == NULL) | 677 | if (!clks) |
| 580 | return ~0; | 678 | return ~0; |
| 581 | 679 | ||
| 582 | for (clkr = clks->rates; clkr->div; clkr++) { | 680 | for (clkr = clks->rates; clkr->div; clkr++) { |
| @@ -595,23 +693,6 @@ u32 omap2_divisor_to_clksel(struct clk *clk, u32 div) | |||
| 595 | } | 693 | } |
| 596 | 694 | ||
| 597 | /** | 695 | /** |
| 598 | * omap2_get_clksel - find clksel register addr & field mask for a clk | ||
| 599 | * @clk: struct clk to use | ||
| 600 | * @field_mask: ptr to u32 to store the register field mask | ||
| 601 | * | ||
| 602 | * Returns the address of the clksel register upon success or NULL on error. | ||
| 603 | */ | ||
| 604 | void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) | ||
| 605 | { | ||
| 606 | if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL))) | ||
| 607 | return NULL; | ||
| 608 | |||
| 609 | *field_mask = clk->clksel_mask; | ||
| 610 | |||
| 611 | return clk->clksel_reg; | ||
| 612 | } | ||
| 613 | |||
| 614 | /** | ||
| 615 | * omap2_clksel_get_divisor - get current divider applied to parent clock. | 696 | * omap2_clksel_get_divisor - get current divider applied to parent clock. |
| 616 | * @clk: OMAP struct clk to use. | 697 | * @clk: OMAP struct clk to use. |
| 617 | * | 698 | * |
| @@ -619,49 +700,41 @@ void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask) | |||
| 619 | */ | 700 | */ |
| 620 | u32 omap2_clksel_get_divisor(struct clk *clk) | 701 | u32 omap2_clksel_get_divisor(struct clk *clk) |
| 621 | { | 702 | { |
| 622 | u32 field_mask, field_val; | 703 | u32 v; |
| 623 | void __iomem *div_addr; | ||
| 624 | 704 | ||
| 625 | div_addr = omap2_get_clksel(clk, &field_mask); | 705 | if (!clk->clksel_mask) |
| 626 | if (div_addr == NULL) | ||
| 627 | return 0; | 706 | return 0; |
| 628 | 707 | ||
| 629 | field_val = __raw_readl(div_addr) & field_mask; | 708 | v = __raw_readl(clk->clksel_reg) & clk->clksel_mask; |
| 630 | field_val >>= __ffs(field_mask); | 709 | v >>= __ffs(clk->clksel_mask); |
| 631 | 710 | ||
| 632 | return omap2_clksel_to_divisor(clk, field_val); | 711 | return omap2_clksel_to_divisor(clk, v); |
| 633 | } | 712 | } |
| 634 | 713 | ||
| 635 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) | 714 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) |
| 636 | { | 715 | { |
| 637 | u32 field_mask, field_val, reg_val, validrate, new_div = 0; | 716 | u32 v, field_val, validrate, new_div = 0; |
| 638 | void __iomem *div_addr; | ||
| 639 | 717 | ||
| 640 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); | 718 | if (!clk->clksel_mask) |
| 641 | if (validrate != rate) | ||
| 642 | return -EINVAL; | 719 | return -EINVAL; |
| 643 | 720 | ||
| 644 | div_addr = omap2_get_clksel(clk, &field_mask); | 721 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); |
| 645 | if (div_addr == NULL) | 722 | if (validrate != rate) |
| 646 | return -EINVAL; | 723 | return -EINVAL; |
| 647 | 724 | ||
| 648 | field_val = omap2_divisor_to_clksel(clk, new_div); | 725 | field_val = omap2_divisor_to_clksel(clk, new_div); |
| 649 | if (field_val == ~0) | 726 | if (field_val == ~0) |
| 650 | return -EINVAL; | 727 | return -EINVAL; |
| 651 | 728 | ||
| 652 | reg_val = __raw_readl(div_addr); | 729 | v = __raw_readl(clk->clksel_reg); |
| 653 | reg_val &= ~field_mask; | 730 | v &= ~clk->clksel_mask; |
| 654 | reg_val |= (field_val << __ffs(field_mask)); | 731 | v |= field_val << __ffs(clk->clksel_mask); |
| 655 | __raw_writel(reg_val, div_addr); | 732 | __raw_writel(v, clk->clksel_reg); |
| 656 | wmb(); | 733 | v = __raw_readl(clk->clksel_reg); /* OCP barrier */ |
| 657 | 734 | ||
| 658 | clk->rate = clk->parent->rate / new_div; | 735 | clk->rate = clk->parent->rate / new_div; |
| 659 | 736 | ||
| 660 | if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { | 737 | _omap2xxx_clk_commit(clk); |
| 661 | prm_write_mod_reg(OMAP24XX_VALID_CONFIG, | ||
| 662 | OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET); | ||
| 663 | wmb(); | ||
| 664 | } | ||
| 665 | 738 | ||
| 666 | return 0; | 739 | return 0; |
| 667 | } | 740 | } |
| @@ -680,31 +753,24 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate) | |||
| 680 | return -EINVAL; | 753 | return -EINVAL; |
| 681 | 754 | ||
| 682 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ | 755 | /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */ |
| 683 | if (clk->set_rate != NULL) | 756 | if (clk->set_rate) |
| 684 | ret = clk->set_rate(clk, rate); | 757 | ret = clk->set_rate(clk, rate); |
| 685 | 758 | ||
| 686 | if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) | ||
| 687 | propagate_rate(clk); | ||
| 688 | |||
| 689 | return ret; | 759 | return ret; |
| 690 | } | 760 | } |
| 691 | 761 | ||
| 692 | /* | 762 | /* |
| 693 | * Converts encoded control register address into a full address | 763 | * Converts encoded control register address into a full address |
| 694 | * On error, *src_addr will be returned as 0. | 764 | * On error, the return value (parent_div) will be 0. |
| 695 | */ | 765 | */ |
| 696 | static u32 omap2_clksel_get_src_field(void __iomem **src_addr, | 766 | static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk, |
| 697 | struct clk *src_clk, u32 *field_mask, | 767 | u32 *field_val) |
| 698 | struct clk *clk, u32 *parent_div) | ||
| 699 | { | 768 | { |
| 700 | const struct clksel *clks; | 769 | const struct clksel *clks; |
| 701 | const struct clksel_rate *clkr; | 770 | const struct clksel_rate *clkr; |
| 702 | 771 | ||
| 703 | *parent_div = 0; | ||
| 704 | *src_addr = NULL; | ||
| 705 | |||
| 706 | clks = omap2_get_clksel_by_parent(clk, src_clk); | 772 | clks = omap2_get_clksel_by_parent(clk, src_clk); |
| 707 | if (clks == NULL) | 773 | if (!clks) |
| 708 | return 0; | 774 | return 0; |
| 709 | 775 | ||
| 710 | for (clkr = clks->rates; clkr->div; clkr++) { | 776 | for (clkr = clks->rates; clkr->div; clkr++) { |
| @@ -722,47 +788,35 @@ static u32 omap2_clksel_get_src_field(void __iomem **src_addr, | |||
| 722 | /* Should never happen. Add a clksel mask to the struct clk. */ | 788 | /* Should never happen. Add a clksel mask to the struct clk. */ |
| 723 | WARN_ON(clk->clksel_mask == 0); | 789 | WARN_ON(clk->clksel_mask == 0); |
| 724 | 790 | ||
| 725 | *field_mask = clk->clksel_mask; | 791 | *field_val = clkr->val; |
| 726 | *src_addr = clk->clksel_reg; | ||
| 727 | *parent_div = clkr->div; | ||
| 728 | 792 | ||
| 729 | return clkr->val; | 793 | return clkr->div; |
| 730 | } | 794 | } |
| 731 | 795 | ||
| 732 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) | 796 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) |
| 733 | { | 797 | { |
| 734 | void __iomem *src_addr; | 798 | u32 field_val, v, parent_div; |
| 735 | u32 field_val, field_mask, reg_val, parent_div; | ||
| 736 | 799 | ||
| 737 | if (unlikely(clk->flags & CONFIG_PARTICIPANT)) | 800 | if (clk->flags & CONFIG_PARTICIPANT) |
| 738 | return -EINVAL; | 801 | return -EINVAL; |
| 739 | 802 | ||
| 740 | if (!clk->clksel) | 803 | if (!clk->clksel) |
| 741 | return -EINVAL; | 804 | return -EINVAL; |
| 742 | 805 | ||
| 743 | field_val = omap2_clksel_get_src_field(&src_addr, new_parent, | 806 | parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val); |
| 744 | &field_mask, clk, &parent_div); | 807 | if (!parent_div) |
| 745 | if (src_addr == NULL) | ||
| 746 | return -EINVAL; | 808 | return -EINVAL; |
| 747 | 809 | ||
| 748 | if (clk->usecount > 0) | ||
| 749 | omap2_clk_disable(clk); | ||
| 750 | |||
| 751 | /* Set new source value (previous dividers if any in effect) */ | 810 | /* Set new source value (previous dividers if any in effect) */ |
| 752 | reg_val = __raw_readl(src_addr) & ~field_mask; | 811 | v = __raw_readl(clk->clksel_reg); |
| 753 | reg_val |= (field_val << __ffs(field_mask)); | 812 | v &= ~clk->clksel_mask; |
| 754 | __raw_writel(reg_val, src_addr); | 813 | v |= field_val << __ffs(clk->clksel_mask); |
| 755 | wmb(); | 814 | __raw_writel(v, clk->clksel_reg); |
| 756 | 815 | v = __raw_readl(clk->clksel_reg); /* OCP barrier */ | |
| 757 | if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { | ||
| 758 | __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); | ||
| 759 | wmb(); | ||
| 760 | } | ||
| 761 | 816 | ||
| 762 | clk->parent = new_parent; | 817 | _omap2xxx_clk_commit(clk); |
| 763 | 818 | ||
| 764 | if (clk->usecount > 0) | 819 | clk_reparent(clk, new_parent); |
| 765 | omap2_clk_enable(clk); | ||
| 766 | 820 | ||
| 767 | /* CLKSEL clocks follow their parents' rates, divided by a divisor */ | 821 | /* CLKSEL clocks follow their parents' rates, divided by a divisor */ |
| 768 | clk->rate = new_parent->rate; | 822 | clk->rate = new_parent->rate; |
| @@ -773,9 +827,6 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent) | |||
| 773 | pr_debug("clock: set parent of %s to %s (new rate %ld)\n", | 827 | pr_debug("clock: set parent of %s to %s (new rate %ld)\n", |
| 774 | clk->name, clk->parent->name, clk->rate); | 828 | clk->name, clk->parent->name, clk->rate); |
| 775 | 829 | ||
| 776 | if (unlikely(clk->flags & RATE_PROPAGATES)) | ||
| 777 | propagate_rate(clk); | ||
| 778 | |||
| 779 | return 0; | 830 | return 0; |
| 780 | } | 831 | } |
| 781 | 832 | ||
| @@ -805,7 +856,8 @@ int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance) | |||
| 805 | return 0; | 856 | return 0; |
| 806 | } | 857 | } |
| 807 | 858 | ||
| 808 | static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n) | 859 | static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, |
| 860 | unsigned int m, unsigned int n) | ||
| 809 | { | 861 | { |
| 810 | unsigned long long num; | 862 | unsigned long long num; |
| 811 | 863 | ||
| @@ -838,7 +890,7 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, | |||
| 838 | unsigned long target_rate, | 890 | unsigned long target_rate, |
| 839 | unsigned long parent_rate) | 891 | unsigned long parent_rate) |
| 840 | { | 892 | { |
| 841 | int flags = 0, carry = 0; | 893 | int r = 0, carry = 0; |
| 842 | 894 | ||
| 843 | /* Unscale m and round if necessary */ | 895 | /* Unscale m and round if necessary */ |
| 844 | if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) | 896 | if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL) |
| @@ -859,13 +911,13 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, | |||
| 859 | if (*m < DPLL_MIN_MULTIPLIER) { | 911 | if (*m < DPLL_MIN_MULTIPLIER) { |
| 860 | *m = DPLL_MIN_MULTIPLIER; | 912 | *m = DPLL_MIN_MULTIPLIER; |
| 861 | *new_rate = 0; | 913 | *new_rate = 0; |
| 862 | flags = DPLL_MULT_UNDERFLOW; | 914 | r = DPLL_MULT_UNDERFLOW; |
| 863 | } | 915 | } |
| 864 | 916 | ||
| 865 | if (*new_rate == 0) | 917 | if (*new_rate == 0) |
| 866 | *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); | 918 | *new_rate = _dpll_compute_new_rate(parent_rate, *m, n); |
| 867 | 919 | ||
| 868 | return flags; | 920 | return r; |
| 869 | } | 921 | } |
| 870 | 922 | ||
| 871 | /** | 923 | /** |
| @@ -889,54 +941,65 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) | |||
| 889 | int m, n, r, e, scaled_max_m; | 941 | int m, n, r, e, scaled_max_m; |
| 890 | unsigned long scaled_rt_rp, new_rate; | 942 | unsigned long scaled_rt_rp, new_rate; |
| 891 | int min_e = -1, min_e_m = -1, min_e_n = -1; | 943 | int min_e = -1, min_e_m = -1, min_e_n = -1; |
| 944 | struct dpll_data *dd; | ||
| 892 | 945 | ||
| 893 | if (!clk || !clk->dpll_data) | 946 | if (!clk || !clk->dpll_data) |
| 894 | return ~0; | 947 | return ~0; |
| 895 | 948 | ||
| 949 | dd = clk->dpll_data; | ||
| 950 | |||
| 896 | pr_debug("clock: starting DPLL round_rate for clock %s, target rate " | 951 | pr_debug("clock: starting DPLL round_rate for clock %s, target rate " |
| 897 | "%ld\n", clk->name, target_rate); | 952 | "%ld\n", clk->name, target_rate); |
| 898 | 953 | ||
| 899 | scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR); | 954 | scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR); |
| 900 | scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR; | 955 | scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR; |
| 901 | 956 | ||
| 902 | clk->dpll_data->last_rounded_rate = 0; | 957 | dd->last_rounded_rate = 0; |
| 903 | 958 | ||
| 904 | for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) { | 959 | for (n = dd->min_divider; n <= dd->max_divider; n++) { |
| 960 | |||
| 961 | /* Is the (input clk, divider) pair valid for the DPLL? */ | ||
| 962 | r = _dpll_test_fint(clk, n); | ||
| 963 | if (r == DPLL_FINT_UNDERFLOW) | ||
| 964 | break; | ||
| 965 | else if (r == DPLL_FINT_INVALID) | ||
| 966 | continue; | ||
| 905 | 967 | ||
| 906 | /* Compute the scaled DPLL multiplier, based on the divider */ | 968 | /* Compute the scaled DPLL multiplier, based on the divider */ |
| 907 | m = scaled_rt_rp * n; | 969 | m = scaled_rt_rp * n; |
| 908 | 970 | ||
| 909 | /* | 971 | /* |
| 910 | * Since we're counting n down, a m overflow means we can | 972 | * Since we're counting n up, a m overflow means we |
| 911 | * can immediately skip to the next n | 973 | * can bail out completely (since as n increases in |
| 974 | * the next iteration, there's no way that m can | ||
| 975 | * increase beyond the current m) | ||
| 912 | */ | 976 | */ |
| 913 | if (m > scaled_max_m) | 977 | if (m > scaled_max_m) |
| 914 | continue; | 978 | break; |
| 915 | 979 | ||
| 916 | r = _dpll_test_mult(&m, n, &new_rate, target_rate, | 980 | r = _dpll_test_mult(&m, n, &new_rate, target_rate, |
| 917 | clk->parent->rate); | 981 | dd->clk_ref->rate); |
| 982 | |||
| 983 | /* m can't be set low enough for this n - try with a larger n */ | ||
| 984 | if (r == DPLL_MULT_UNDERFLOW) | ||
| 985 | continue; | ||
| 918 | 986 | ||
| 919 | e = target_rate - new_rate; | 987 | e = target_rate - new_rate; |
| 920 | pr_debug("clock: n = %d: m = %d: rate error is %d " | 988 | pr_debug("clock: n = %d: m = %d: rate error is %d " |
| 921 | "(new_rate = %ld)\n", n, m, e, new_rate); | 989 | "(new_rate = %ld)\n", n, m, e, new_rate); |
| 922 | 990 | ||
| 923 | if (min_e == -1 || | 991 | if (min_e == -1 || |
| 924 | min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) { | 992 | min_e >= (int)(abs(e) - dd->rate_tolerance)) { |
| 925 | min_e = e; | 993 | min_e = e; |
| 926 | min_e_m = m; | 994 | min_e_m = m; |
| 927 | min_e_n = n; | 995 | min_e_n = n; |
| 928 | 996 | ||
| 929 | pr_debug("clock: found new least error %d\n", min_e); | 997 | pr_debug("clock: found new least error %d\n", min_e); |
| 930 | } | ||
| 931 | 998 | ||
| 932 | /* | 999 | /* We found good settings -- bail out now */ |
| 933 | * Since we're counting n down, a m underflow means we | 1000 | if (min_e <= dd->rate_tolerance) |
| 934 | * can bail out completely (since as n decreases in | 1001 | break; |
| 935 | * the next iteration, there's no way that m can | 1002 | } |
| 936 | * increase beyond the current m) | ||
| 937 | */ | ||
| 938 | if (r & DPLL_MULT_UNDERFLOW) | ||
| 939 | break; | ||
| 940 | } | 1003 | } |
| 941 | 1004 | ||
| 942 | if (min_e < 0) { | 1005 | if (min_e < 0) { |
| @@ -944,17 +1007,17 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) | |||
| 944 | return ~0; | 1007 | return ~0; |
| 945 | } | 1008 | } |
| 946 | 1009 | ||
| 947 | clk->dpll_data->last_rounded_m = min_e_m; | 1010 | dd->last_rounded_m = min_e_m; |
| 948 | clk->dpll_data->last_rounded_n = min_e_n; | 1011 | dd->last_rounded_n = min_e_n; |
| 949 | clk->dpll_data->last_rounded_rate = | 1012 | dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate, |
| 950 | _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n); | 1013 | min_e_m, min_e_n); |
| 951 | 1014 | ||
| 952 | pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", | 1015 | pr_debug("clock: final least error: e = %d, m = %d, n = %d\n", |
| 953 | min_e, min_e_m, min_e_n); | 1016 | min_e, min_e_m, min_e_n); |
| 954 | pr_debug("clock: final rate: %ld (target rate: %ld)\n", | 1017 | pr_debug("clock: final rate: %ld (target rate: %ld)\n", |
| 955 | clk->dpll_data->last_rounded_rate, target_rate); | 1018 | dd->last_rounded_rate, target_rate); |
| 956 | 1019 | ||
| 957 | return clk->dpll_data->last_rounded_rate; | 1020 | return dd->last_rounded_rate; |
| 958 | } | 1021 | } |
| 959 | 1022 | ||
| 960 | /*------------------------------------------------------------------------- | 1023 | /*------------------------------------------------------------------------- |
| @@ -973,6 +1036,10 @@ void omap2_clk_disable_unused(struct clk *clk) | |||
| 973 | return; | 1036 | return; |
| 974 | 1037 | ||
| 975 | printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); | 1038 | printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name); |
| 976 | _omap2_clk_disable(clk); | 1039 | if (cpu_is_omap34xx()) { |
| 1040 | omap2_clk_enable(clk); | ||
| 1041 | omap2_clk_disable(clk); | ||
| 1042 | } else | ||
| 1043 | _omap2_clk_disable(clk); | ||
| 977 | } | 1044 | } |
| 978 | #endif | 1045 | #endif |
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 1fb330e0847d..2679ddfa6424 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h | |||
| @@ -21,13 +21,28 @@ | |||
| 21 | /* The maximum error between a target DPLL rate and the rounded rate in Hz */ | 21 | /* The maximum error between a target DPLL rate and the rounded rate in Hz */ |
| 22 | #define DEFAULT_DPLL_RATE_TOLERANCE 50000 | 22 | #define DEFAULT_DPLL_RATE_TOLERANCE 50000 |
| 23 | 23 | ||
| 24 | /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ | ||
| 25 | #define CORE_CLK_SRC_32K 0x0 | ||
| 26 | #define CORE_CLK_SRC_DPLL 0x1 | ||
| 27 | #define CORE_CLK_SRC_DPLL_X2 0x2 | ||
| 28 | |||
| 29 | /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */ | ||
| 30 | #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1 | ||
| 31 | #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2 | ||
| 32 | #define OMAP2XXX_EN_DPLL_LOCKED 0x3 | ||
| 33 | |||
| 34 | /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ | ||
| 35 | #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5 | ||
| 36 | #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 | ||
| 37 | #define OMAP3XXX_EN_DPLL_LOCKED 0x7 | ||
| 38 | |||
| 24 | int omap2_clk_init(void); | 39 | int omap2_clk_init(void); |
| 25 | int omap2_clk_enable(struct clk *clk); | 40 | int omap2_clk_enable(struct clk *clk); |
| 26 | void omap2_clk_disable(struct clk *clk); | 41 | void omap2_clk_disable(struct clk *clk); |
| 27 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); | 42 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); |
| 28 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate); | 43 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate); |
| 29 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); | 44 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); |
| 30 | int omap2_dpll_rate_tolerance_set(struct clk *clk, unsigned int tolerance); | 45 | int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); |
| 31 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); | 46 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); |
| 32 | 47 | ||
| 33 | #ifdef CONFIG_OMAP_RESET_CLOCKS | 48 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
| @@ -36,7 +51,7 @@ void omap2_clk_disable_unused(struct clk *clk); | |||
| 36 | #define omap2_clk_disable_unused NULL | 51 | #define omap2_clk_disable_unused NULL |
| 37 | #endif | 52 | #endif |
| 38 | 53 | ||
| 39 | void omap2_clksel_recalc(struct clk *clk); | 54 | unsigned long omap2_clksel_recalc(struct clk *clk); |
| 40 | void omap2_init_clk_clkdm(struct clk *clk); | 55 | void omap2_init_clk_clkdm(struct clk *clk); |
| 41 | void omap2_init_clksel_parent(struct clk *clk); | 56 | void omap2_init_clksel_parent(struct clk *clk); |
| 42 | u32 omap2_clksel_get_divisor(struct clk *clk); | 57 | u32 omap2_clksel_get_divisor(struct clk *clk); |
| @@ -44,13 +59,16 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |||
| 44 | u32 *new_div); | 59 | u32 *new_div); |
| 45 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); | 60 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); |
| 46 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); | 61 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); |
| 47 | void omap2_fixed_divisor_recalc(struct clk *clk); | 62 | unsigned long omap2_fixed_divisor_recalc(struct clk *clk); |
| 48 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); | 63 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); |
| 49 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); | 64 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); |
| 50 | u32 omap2_get_dpll_rate(struct clk *clk); | 65 | u32 omap2_get_dpll_rate(struct clk *clk); |
| 51 | int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); | 66 | int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); |
| 52 | void omap2_clk_prepare_for_reboot(void); | 67 | void omap2_clk_prepare_for_reboot(void); |
| 53 | 68 | ||
| 69 | extern const struct clkops clkops_omap2_dflt_wait; | ||
| 70 | extern const struct clkops clkops_omap2_dflt; | ||
| 71 | |||
| 54 | extern u8 cpu_mask; | 72 | extern u8 cpu_mask; |
| 55 | 73 | ||
| 56 | /* clksel_rate data common to 24xx/343x */ | 74 | /* clksel_rate data common to 24xx/343x */ |
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c index d382eb0184ac..1e839c5a28c5 100644 --- a/arch/arm/mach-omap2/clock24xx.c +++ b/arch/arm/mach-omap2/clock24xx.c | |||
| @@ -31,15 +31,192 @@ | |||
| 31 | #include <mach/clock.h> | 31 | #include <mach/clock.h> |
| 32 | #include <mach/sram.h> | 32 | #include <mach/sram.h> |
| 33 | #include <asm/div64.h> | 33 | #include <asm/div64.h> |
| 34 | #include <asm/clkdev.h> | ||
| 34 | 35 | ||
| 35 | #include "memory.h" | 36 | #include <mach/sdrc.h> |
| 36 | #include "clock.h" | 37 | #include "clock.h" |
| 37 | #include "clock24xx.h" | ||
| 38 | #include "prm.h" | 38 | #include "prm.h" |
| 39 | #include "prm-regbits-24xx.h" | 39 | #include "prm-regbits-24xx.h" |
| 40 | #include "cm.h" | 40 | #include "cm.h" |
| 41 | #include "cm-regbits-24xx.h" | 41 | #include "cm-regbits-24xx.h" |
| 42 | 42 | ||
| 43 | static const struct clkops clkops_oscck; | ||
| 44 | static const struct clkops clkops_fixed; | ||
| 45 | |||
| 46 | #include "clock24xx.h" | ||
| 47 | |||
| 48 | struct omap_clk { | ||
| 49 | u32 cpu; | ||
| 50 | struct clk_lookup lk; | ||
| 51 | }; | ||
| 52 | |||
| 53 | #define CLK(dev, con, ck, cp) \ | ||
| 54 | { \ | ||
| 55 | .cpu = cp, \ | ||
| 56 | .lk = { \ | ||
| 57 | .dev_id = dev, \ | ||
| 58 | .con_id = con, \ | ||
| 59 | .clk = ck, \ | ||
| 60 | }, \ | ||
| 61 | } | ||
| 62 | |||
| 63 | #define CK_243X (1 << 0) | ||
| 64 | #define CK_242X (1 << 1) | ||
| 65 | |||
| 66 | static struct omap_clk omap24xx_clks[] = { | ||
| 67 | /* external root sources */ | ||
| 68 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X), | ||
| 69 | CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X), | ||
| 70 | CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X), | ||
| 71 | CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X), | ||
| 72 | /* internal analog sources */ | ||
| 73 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X), | ||
| 74 | CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X), | ||
| 75 | CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X), | ||
| 76 | /* internal prcm root sources */ | ||
| 77 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X), | ||
| 78 | CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X), | ||
| 79 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X), | ||
| 80 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X), | ||
| 81 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X), | ||
| 82 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X), | ||
| 83 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X), | ||
| 84 | CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X), | ||
| 85 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), | ||
| 86 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), | ||
| 87 | CLK(NULL, "emul_ck", &emul_ck, CK_242X), | ||
| 88 | /* mpu domain clocks */ | ||
| 89 | CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X), | ||
| 90 | /* dsp domain clocks */ | ||
| 91 | CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X), | ||
| 92 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X), | ||
| 93 | CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), | ||
| 94 | CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), | ||
| 95 | CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), | ||
| 96 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), | ||
| 97 | /* GFX domain clocks */ | ||
| 98 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X), | ||
| 99 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X), | ||
| 100 | CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X), | ||
| 101 | /* Modem domain clocks */ | ||
| 102 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), | ||
| 103 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), | ||
| 104 | /* DSS domain clocks */ | ||
| 105 | CLK(NULL, "dss_ick", &dss_ick, CK_243X | CK_242X), | ||
| 106 | CLK(NULL, "dss1_fck", &dss1_fck, CK_243X | CK_242X), | ||
| 107 | CLK(NULL, "dss2_fck", &dss2_fck, CK_243X | CK_242X), | ||
| 108 | CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X | CK_242X), | ||
| 109 | /* L3 domain clocks */ | ||
| 110 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), | ||
| 111 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), | ||
| 112 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X), | ||
| 113 | /* L4 domain clocks */ | ||
| 114 | CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X), | ||
| 115 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X), | ||
| 116 | /* virtual meta-group clock */ | ||
| 117 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X), | ||
| 118 | /* general l4 interface ck, multi-parent functional clk */ | ||
| 119 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X), | ||
| 120 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X), | ||
| 121 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X), | ||
| 122 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X), | ||
| 123 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X), | ||
| 124 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X), | ||
| 125 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X), | ||
| 126 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X), | ||
| 127 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X), | ||
| 128 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X), | ||
| 129 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X), | ||
| 130 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X), | ||
| 131 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X), | ||
| 132 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X), | ||
| 133 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X), | ||
| 134 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X), | ||
| 135 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X), | ||
| 136 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X), | ||
| 137 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X), | ||
| 138 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X), | ||
| 139 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X), | ||
| 140 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X), | ||
| 141 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X), | ||
| 142 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X), | ||
| 143 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X), | ||
| 144 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X), | ||
| 145 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X), | ||
| 146 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X), | ||
| 147 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), | ||
| 148 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), | ||
| 149 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), | ||
| 150 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), | ||
| 151 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), | ||
| 152 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), | ||
| 153 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X), | ||
| 154 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X), | ||
| 155 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X), | ||
| 156 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X), | ||
| 157 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), | ||
| 158 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), | ||
| 159 | CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X), | ||
| 160 | CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X), | ||
| 161 | CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X), | ||
| 162 | CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X), | ||
| 163 | CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X), | ||
| 164 | CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X), | ||
| 165 | CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X), | ||
| 166 | CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X), | ||
| 167 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X), | ||
| 168 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X), | ||
| 169 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X), | ||
| 170 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X), | ||
| 171 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X), | ||
| 172 | CLK(NULL, "icr_ick", &icr_ick, CK_243X), | ||
| 173 | CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X), | ||
| 174 | CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X), | ||
| 175 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X), | ||
| 176 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X), | ||
| 177 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X), | ||
| 178 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), | ||
| 179 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), | ||
| 180 | CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X), | ||
| 181 | CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X), | ||
| 182 | CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), | ||
| 183 | CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), | ||
| 184 | CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X), | ||
| 185 | CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X), | ||
| 186 | CLK(NULL, "eac_ick", &eac_ick, CK_242X), | ||
| 187 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), | ||
| 188 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X), | ||
| 189 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X), | ||
| 190 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X), | ||
| 191 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), | ||
| 192 | CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), | ||
| 193 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X), | ||
| 194 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), | ||
| 195 | CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), | ||
| 196 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X), | ||
| 197 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X), | ||
| 198 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X), | ||
| 199 | CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), | ||
| 200 | CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), | ||
| 201 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), | ||
| 202 | CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X), | ||
| 203 | CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X), | ||
| 204 | CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X), | ||
| 205 | CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), | ||
| 206 | CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), | ||
| 207 | CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), | ||
| 208 | CLK(NULL, "usbhs_ick", &usbhs_ick, CK_243X), | ||
| 209 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), | ||
| 210 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), | ||
| 211 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), | ||
| 212 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), | ||
| 213 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), | ||
| 214 | CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), | ||
| 215 | CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), | ||
| 216 | CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), | ||
| 217 | CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), | ||
| 218 | }; | ||
| 219 | |||
| 43 | /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ | 220 | /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ |
| 44 | #define EN_APLL_STOPPED 0 | 221 | #define EN_APLL_STOPPED 0 |
| 45 | #define EN_APLL_LOCKED 3 | 222 | #define EN_APLL_LOCKED 3 |
| @@ -59,19 +236,32 @@ static struct clk *sclk; | |||
| 59 | * Omap24xx specific clock functions | 236 | * Omap24xx specific clock functions |
| 60 | *-------------------------------------------------------------------------*/ | 237 | *-------------------------------------------------------------------------*/ |
| 61 | 238 | ||
| 62 | /* This actually returns the rate of core_ck, not dpll_ck. */ | 239 | /** |
| 63 | static u32 omap2_get_dpll_rate_24xx(struct clk *tclk) | 240 | * omap2xxx_clk_get_core_rate - return the CORE_CLK rate |
| 241 | * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") | ||
| 242 | * | ||
| 243 | * Returns the CORE_CLK rate. CORE_CLK can have one of three rate | ||
| 244 | * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz | ||
| 245 | * (the latter is unusual). This currently should be called with | ||
| 246 | * struct clk *dpll_ck, which is a composite clock of dpll_ck and | ||
| 247 | * core_ck. | ||
| 248 | */ | ||
| 249 | static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) | ||
| 64 | { | 250 | { |
| 65 | long long dpll_clk; | 251 | long long core_clk; |
| 66 | u8 amult; | 252 | u32 v; |
| 253 | |||
| 254 | core_clk = omap2_get_dpll_rate(clk); | ||
| 67 | 255 | ||
| 68 | dpll_clk = omap2_get_dpll_rate(tclk); | 256 | v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
| 257 | v &= OMAP24XX_CORE_CLK_SRC_MASK; | ||
| 69 | 258 | ||
| 70 | amult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 259 | if (v == CORE_CLK_SRC_32K) |
| 71 | amult &= OMAP24XX_CORE_CLK_SRC_MASK; | 260 | core_clk = 32768; |
| 72 | dpll_clk *= amult; | 261 | else |
| 262 | core_clk *= v; | ||
| 73 | 263 | ||
| 74 | return dpll_clk; | 264 | return core_clk; |
| 75 | } | 265 | } |
| 76 | 266 | ||
| 77 | static int omap2_enable_osc_ck(struct clk *clk) | 267 | static int omap2_enable_osc_ck(struct clk *clk) |
| @@ -96,6 +286,11 @@ static void omap2_disable_osc_ck(struct clk *clk) | |||
| 96 | OMAP24XX_PRCM_CLKSRC_CTRL); | 286 | OMAP24XX_PRCM_CLKSRC_CTRL); |
| 97 | } | 287 | } |
| 98 | 288 | ||
| 289 | static const struct clkops clkops_oscck = { | ||
| 290 | .enable = &omap2_enable_osc_ck, | ||
| 291 | .disable = &omap2_disable_osc_ck, | ||
| 292 | }; | ||
| 293 | |||
| 99 | #ifdef OLD_CK | 294 | #ifdef OLD_CK |
| 100 | /* Recalculate SYST_CLK */ | 295 | /* Recalculate SYST_CLK */ |
| 101 | static void omap2_sys_clk_recalc(struct clk * clk) | 296 | static void omap2_sys_clk_recalc(struct clk * clk) |
| @@ -149,11 +344,16 @@ static void omap2_clk_fixed_disable(struct clk *clk) | |||
| 149 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | 344 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); |
| 150 | } | 345 | } |
| 151 | 346 | ||
| 347 | static const struct clkops clkops_fixed = { | ||
| 348 | .enable = &omap2_clk_fixed_enable, | ||
| 349 | .disable = &omap2_clk_fixed_disable, | ||
| 350 | }; | ||
| 351 | |||
| 152 | /* | 352 | /* |
| 153 | * Uses the current prcm set to tell if a rate is valid. | 353 | * Uses the current prcm set to tell if a rate is valid. |
| 154 | * You can go slower, but not faster within a given rate set. | 354 | * You can go slower, but not faster within a given rate set. |
| 155 | */ | 355 | */ |
| 156 | long omap2_dpllcore_round_rate(unsigned long target_rate) | 356 | static long omap2_dpllcore_round_rate(unsigned long target_rate) |
| 157 | { | 357 | { |
| 158 | u32 high, low, core_clk_src; | 358 | u32 high, low, core_clk_src; |
| 159 | 359 | ||
| @@ -182,11 +382,9 @@ long omap2_dpllcore_round_rate(unsigned long target_rate) | |||
| 182 | 382 | ||
| 183 | } | 383 | } |
| 184 | 384 | ||
| 185 | static void omap2_dpllcore_recalc(struct clk *clk) | 385 | static unsigned long omap2_dpllcore_recalc(struct clk *clk) |
| 186 | { | 386 | { |
| 187 | clk->rate = omap2_get_dpll_rate_24xx(clk); | 387 | return omap2xxx_clk_get_core_rate(clk); |
| 188 | |||
| 189 | propagate_rate(clk); | ||
| 190 | } | 388 | } |
| 191 | 389 | ||
| 192 | static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | 390 | static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) |
| @@ -195,22 +393,19 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | |||
| 195 | u32 bypass = 0; | 393 | u32 bypass = 0; |
| 196 | struct prcm_config tmpset; | 394 | struct prcm_config tmpset; |
| 197 | const struct dpll_data *dd; | 395 | const struct dpll_data *dd; |
| 198 | unsigned long flags; | ||
| 199 | int ret = -EINVAL; | ||
| 200 | 396 | ||
| 201 | local_irq_save(flags); | 397 | cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck); |
| 202 | cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); | ||
| 203 | mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); | 398 | mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
| 204 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; | 399 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; |
| 205 | 400 | ||
| 206 | if ((rate == (cur_rate / 2)) && (mult == 2)) { | 401 | if ((rate == (cur_rate / 2)) && (mult == 2)) { |
| 207 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); | 402 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); |
| 208 | } else if ((rate == (cur_rate * 2)) && (mult == 1)) { | 403 | } else if ((rate == (cur_rate * 2)) && (mult == 1)) { |
| 209 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); | 404 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); |
| 210 | } else if (rate != cur_rate) { | 405 | } else if (rate != cur_rate) { |
| 211 | valid_rate = omap2_dpllcore_round_rate(rate); | 406 | valid_rate = omap2_dpllcore_round_rate(rate); |
| 212 | if (valid_rate != rate) | 407 | if (valid_rate != rate) |
| 213 | goto dpll_exit; | 408 | return -EINVAL; |
| 214 | 409 | ||
| 215 | if (mult == 1) | 410 | if (mult == 1) |
| 216 | low = curr_prcm_set->dpll_speed; | 411 | low = curr_prcm_set->dpll_speed; |
| @@ -219,7 +414,7 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | |||
| 219 | 414 | ||
| 220 | dd = clk->dpll_data; | 415 | dd = clk->dpll_data; |
| 221 | if (!dd) | 416 | if (!dd) |
| 222 | goto dpll_exit; | 417 | return -EINVAL; |
| 223 | 418 | ||
| 224 | tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); | 419 | tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); |
| 225 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | | 420 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | |
| @@ -245,22 +440,19 @@ static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) | |||
| 245 | if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ | 440 | if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ |
| 246 | bypass = 1; | 441 | bypass = 1; |
| 247 | 442 | ||
| 248 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); /* For init_mem */ | 443 | /* For omap2xxx_sdrc_init_params() */ |
| 444 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | ||
| 249 | 445 | ||
| 250 | /* Force dll lock mode */ | 446 | /* Force dll lock mode */ |
| 251 | omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, | 447 | omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, |
| 252 | bypass); | 448 | bypass); |
| 253 | 449 | ||
| 254 | /* Errata: ret dll entry state */ | 450 | /* Errata: ret dll entry state */ |
| 255 | omap2_init_memory_params(omap2_dll_force_needed()); | 451 | omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); |
| 256 | omap2_reprogram_sdrc(done_rate, 0); | 452 | omap2xxx_sdrc_reprogram(done_rate, 0); |
| 257 | } | 453 | } |
| 258 | omap2_dpllcore_recalc(&dpll_ck); | ||
| 259 | ret = 0; | ||
| 260 | 454 | ||
| 261 | dpll_exit: | 455 | return 0; |
| 262 | local_irq_restore(flags); | ||
| 263 | return(ret); | ||
| 264 | } | 456 | } |
| 265 | 457 | ||
| 266 | /** | 458 | /** |
| @@ -269,9 +461,9 @@ dpll_exit: | |||
| 269 | * | 461 | * |
| 270 | * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. | 462 | * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. |
| 271 | */ | 463 | */ |
| 272 | static void omap2_table_mpu_recalc(struct clk *clk) | 464 | static unsigned long omap2_table_mpu_recalc(struct clk *clk) |
| 273 | { | 465 | { |
| 274 | clk->rate = curr_prcm_set->mpu_speed; | 466 | return curr_prcm_set->mpu_speed; |
| 275 | } | 467 | } |
| 276 | 468 | ||
| 277 | /* | 469 | /* |
| @@ -337,12 +529,12 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate) | |||
| 337 | } | 529 | } |
| 338 | 530 | ||
| 339 | curr_prcm_set = prcm; | 531 | curr_prcm_set = prcm; |
| 340 | cur_rate = omap2_get_dpll_rate_24xx(&dpll_ck); | 532 | cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck); |
| 341 | 533 | ||
| 342 | if (prcm->dpll_speed == cur_rate / 2) { | 534 | if (prcm->dpll_speed == cur_rate / 2) { |
| 343 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL, 1); | 535 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); |
| 344 | } else if (prcm->dpll_speed == cur_rate * 2) { | 536 | } else if (prcm->dpll_speed == cur_rate * 2) { |
| 345 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); | 537 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); |
| 346 | } else if (prcm->dpll_speed != cur_rate) { | 538 | } else if (prcm->dpll_speed != cur_rate) { |
| 347 | local_irq_save(flags); | 539 | local_irq_save(flags); |
| 348 | 540 | ||
| @@ -366,27 +558,67 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate) | |||
| 366 | 558 | ||
| 367 | /* Major subsystem dividers */ | 559 | /* Major subsystem dividers */ |
| 368 | tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; | 560 | tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; |
| 369 | cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1); | 561 | cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, |
| 562 | CM_CLKSEL1); | ||
| 563 | |||
| 370 | if (cpu_is_omap2430()) | 564 | if (cpu_is_omap2430()) |
| 371 | cm_write_mod_reg(prcm->cm_clksel_mdm, | 565 | cm_write_mod_reg(prcm->cm_clksel_mdm, |
| 372 | OMAP2430_MDM_MOD, CM_CLKSEL); | 566 | OMAP2430_MDM_MOD, CM_CLKSEL); |
| 373 | 567 | ||
| 374 | /* x2 to enter init_mem */ | 568 | /* x2 to enter omap2xxx_sdrc_init_params() */ |
| 375 | omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); | 569 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); |
| 376 | 570 | ||
| 377 | omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, | 571 | omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, |
| 378 | bypass); | 572 | bypass); |
| 379 | 573 | ||
| 380 | omap2_init_memory_params(omap2_dll_force_needed()); | 574 | omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); |
| 381 | omap2_reprogram_sdrc(done_rate, 0); | 575 | omap2xxx_sdrc_reprogram(done_rate, 0); |
| 382 | 576 | ||
| 383 | local_irq_restore(flags); | 577 | local_irq_restore(flags); |
| 384 | } | 578 | } |
| 385 | omap2_dpllcore_recalc(&dpll_ck); | ||
| 386 | 579 | ||
| 387 | return 0; | 580 | return 0; |
| 388 | } | 581 | } |
| 389 | 582 | ||
| 583 | #ifdef CONFIG_CPU_FREQ | ||
| 584 | /* | ||
| 585 | * Walk PRCM rate table and fillout cpufreq freq_table | ||
| 586 | */ | ||
| 587 | static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)]; | ||
| 588 | |||
| 589 | void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) | ||
| 590 | { | ||
| 591 | struct prcm_config *prcm; | ||
| 592 | int i = 0; | ||
| 593 | |||
| 594 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | ||
| 595 | if (!(prcm->flags & cpu_mask)) | ||
| 596 | continue; | ||
| 597 | if (prcm->xtal_speed != sys_ck.rate) | ||
| 598 | continue; | ||
| 599 | |||
| 600 | /* don't put bypass rates in table */ | ||
| 601 | if (prcm->dpll_speed == prcm->xtal_speed) | ||
| 602 | continue; | ||
| 603 | |||
| 604 | freq_table[i].index = i; | ||
| 605 | freq_table[i].frequency = prcm->mpu_speed / 1000; | ||
| 606 | i++; | ||
| 607 | } | ||
| 608 | |||
| 609 | if (i == 0) { | ||
| 610 | printk(KERN_WARNING "%s: failed to initialize frequency " | ||
| 611 | "table\n", __func__); | ||
| 612 | return; | ||
| 613 | } | ||
| 614 | |||
| 615 | freq_table[i].index = i; | ||
| 616 | freq_table[i].frequency = CPUFREQ_TABLE_END; | ||
| 617 | |||
| 618 | *table = &freq_table[0]; | ||
| 619 | } | ||
| 620 | #endif | ||
| 621 | |||
| 390 | static struct clk_functions omap2_clk_functions = { | 622 | static struct clk_functions omap2_clk_functions = { |
| 391 | .clk_enable = omap2_clk_enable, | 623 | .clk_enable = omap2_clk_enable, |
| 392 | .clk_disable = omap2_clk_disable, | 624 | .clk_disable = omap2_clk_disable, |
| @@ -394,24 +626,27 @@ static struct clk_functions omap2_clk_functions = { | |||
| 394 | .clk_set_rate = omap2_clk_set_rate, | 626 | .clk_set_rate = omap2_clk_set_rate, |
| 395 | .clk_set_parent = omap2_clk_set_parent, | 627 | .clk_set_parent = omap2_clk_set_parent, |
| 396 | .clk_disable_unused = omap2_clk_disable_unused, | 628 | .clk_disable_unused = omap2_clk_disable_unused, |
| 629 | #ifdef CONFIG_CPU_FREQ | ||
| 630 | .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, | ||
| 631 | #endif | ||
| 397 | }; | 632 | }; |
| 398 | 633 | ||
| 399 | static u32 omap2_get_apll_clkin(void) | 634 | static u32 omap2_get_apll_clkin(void) |
| 400 | { | 635 | { |
| 401 | u32 aplls, sclk = 0; | 636 | u32 aplls, srate = 0; |
| 402 | 637 | ||
| 403 | aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); | 638 | aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); |
| 404 | aplls &= OMAP24XX_APLLS_CLKIN_MASK; | 639 | aplls &= OMAP24XX_APLLS_CLKIN_MASK; |
| 405 | aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; | 640 | aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; |
| 406 | 641 | ||
| 407 | if (aplls == APLLS_CLKIN_19_2MHZ) | 642 | if (aplls == APLLS_CLKIN_19_2MHZ) |
| 408 | sclk = 19200000; | 643 | srate = 19200000; |
| 409 | else if (aplls == APLLS_CLKIN_13MHZ) | 644 | else if (aplls == APLLS_CLKIN_13MHZ) |
| 410 | sclk = 13000000; | 645 | srate = 13000000; |
| 411 | else if (aplls == APLLS_CLKIN_12MHZ) | 646 | else if (aplls == APLLS_CLKIN_12MHZ) |
| 412 | sclk = 12000000; | 647 | srate = 12000000; |
| 413 | 648 | ||
| 414 | return sclk; | 649 | return srate; |
| 415 | } | 650 | } |
| 416 | 651 | ||
| 417 | static u32 omap2_get_sysclkdiv(void) | 652 | static u32 omap2_get_sysclkdiv(void) |
| @@ -425,16 +660,14 @@ static u32 omap2_get_sysclkdiv(void) | |||
| 425 | return div; | 660 | return div; |
| 426 | } | 661 | } |
| 427 | 662 | ||
| 428 | static void omap2_osc_clk_recalc(struct clk *clk) | 663 | static unsigned long omap2_osc_clk_recalc(struct clk *clk) |
| 429 | { | 664 | { |
| 430 | clk->rate = omap2_get_apll_clkin() * omap2_get_sysclkdiv(); | 665 | return omap2_get_apll_clkin() * omap2_get_sysclkdiv(); |
| 431 | propagate_rate(clk); | ||
| 432 | } | 666 | } |
| 433 | 667 | ||
| 434 | static void omap2_sys_clk_recalc(struct clk *clk) | 668 | static unsigned long omap2_sys_clk_recalc(struct clk *clk) |
| 435 | { | 669 | { |
| 436 | clk->rate = clk->parent->rate / omap2_get_sysclkdiv(); | 670 | return clk->parent->rate / omap2_get_sysclkdiv(); |
| 437 | propagate_rate(clk); | ||
| 438 | } | 671 | } |
| 439 | 672 | ||
| 440 | /* | 673 | /* |
| @@ -460,7 +693,7 @@ static int __init omap2_clk_arch_init(void) | |||
| 460 | if (!mpurate) | 693 | if (!mpurate) |
| 461 | return -EINVAL; | 694 | return -EINVAL; |
| 462 | 695 | ||
| 463 | if (omap2_select_table_rate(&virt_prcm_set, mpurate)) | 696 | if (clk_set_rate(&virt_prcm_set, mpurate)) |
| 464 | printk(KERN_ERR "Could not find matching MPU rate\n"); | 697 | printk(KERN_ERR "Could not find matching MPU rate\n"); |
| 465 | 698 | ||
| 466 | recalculate_root_clocks(); | 699 | recalculate_root_clocks(); |
| @@ -477,8 +710,8 @@ arch_initcall(omap2_clk_arch_init); | |||
| 477 | int __init omap2_clk_init(void) | 710 | int __init omap2_clk_init(void) |
| 478 | { | 711 | { |
| 479 | struct prcm_config *prcm; | 712 | struct prcm_config *prcm; |
| 480 | struct clk **clkp; | 713 | struct omap_clk *c; |
| 481 | u32 clkrate; | 714 | u32 clkrate, cpu_mask; |
| 482 | 715 | ||
| 483 | if (cpu_is_omap242x()) | 716 | if (cpu_is_omap242x()) |
| 484 | cpu_mask = RATE_IN_242X; | 717 | cpu_mask = RATE_IN_242X; |
| @@ -487,26 +720,28 @@ int __init omap2_clk_init(void) | |||
| 487 | 720 | ||
| 488 | clk_init(&omap2_clk_functions); | 721 | clk_init(&omap2_clk_functions); |
| 489 | 722 | ||
| 490 | omap2_osc_clk_recalc(&osc_ck); | 723 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); |
| 491 | omap2_sys_clk_recalc(&sys_ck); | 724 | propagate_rate(&osc_ck); |
| 725 | sys_ck.rate = omap2_sys_clk_recalc(&sys_ck); | ||
| 726 | propagate_rate(&sys_ck); | ||
| 492 | 727 | ||
| 493 | for (clkp = onchip_24xx_clks; | 728 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) |
| 494 | clkp < onchip_24xx_clks + ARRAY_SIZE(onchip_24xx_clks); | 729 | clk_init_one(c->lk.clk); |
| 495 | clkp++) { | ||
| 496 | 730 | ||
| 497 | if ((*clkp)->flags & CLOCK_IN_OMAP242X && cpu_is_omap2420()) { | 731 | cpu_mask = 0; |
| 498 | clk_register(*clkp); | 732 | if (cpu_is_omap2420()) |
| 499 | continue; | 733 | cpu_mask |= CK_242X; |
| 500 | } | 734 | if (cpu_is_omap2430()) |
| 735 | cpu_mask |= CK_243X; | ||
| 501 | 736 | ||
| 502 | if ((*clkp)->flags & CLOCK_IN_OMAP243X && cpu_is_omap2430()) { | 737 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) |
| 503 | clk_register(*clkp); | 738 | if (c->cpu & cpu_mask) { |
| 504 | continue; | 739 | clkdev_add(&c->lk); |
| 740 | clk_register(c->lk.clk); | ||
| 505 | } | 741 | } |
| 506 | } | ||
| 507 | 742 | ||
| 508 | /* Check the MPU rate set by bootloader */ | 743 | /* Check the MPU rate set by bootloader */ |
| 509 | clkrate = omap2_get_dpll_rate_24xx(&dpll_ck); | 744 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); |
| 510 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | 745 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
| 511 | if (!(prcm->flags & cpu_mask)) | 746 | if (!(prcm->flags & cpu_mask)) |
| 512 | continue; | 747 | continue; |
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index ad6d98d177c5..33c3e5b14323 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h | |||
| @@ -24,17 +24,13 @@ | |||
| 24 | #include "cm-regbits-24xx.h" | 24 | #include "cm-regbits-24xx.h" |
| 25 | #include "sdrc.h" | 25 | #include "sdrc.h" |
| 26 | 26 | ||
| 27 | static void omap2_table_mpu_recalc(struct clk *clk); | 27 | static unsigned long omap2_table_mpu_recalc(struct clk *clk); |
| 28 | static int omap2_select_table_rate(struct clk *clk, unsigned long rate); | 28 | static int omap2_select_table_rate(struct clk *clk, unsigned long rate); |
| 29 | static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); | 29 | static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate); |
| 30 | static void omap2_sys_clk_recalc(struct clk *clk); | 30 | static unsigned long omap2_sys_clk_recalc(struct clk *clk); |
| 31 | static void omap2_osc_clk_recalc(struct clk *clk); | 31 | static unsigned long omap2_osc_clk_recalc(struct clk *clk); |
| 32 | static void omap2_sys_clk_recalc(struct clk *clk); | 32 | static unsigned long omap2_sys_clk_recalc(struct clk *clk); |
| 33 | static void omap2_dpllcore_recalc(struct clk *clk); | 33 | static unsigned long omap2_dpllcore_recalc(struct clk *clk); |
| 34 | static int omap2_clk_fixed_enable(struct clk *clk); | ||
| 35 | static void omap2_clk_fixed_disable(struct clk *clk); | ||
| 36 | static int omap2_enable_osc_ck(struct clk *clk); | ||
| 37 | static void omap2_disable_osc_ck(struct clk *clk); | ||
| 38 | static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); | 34 | static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate); |
| 39 | 35 | ||
| 40 | /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. | 36 | /* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. |
| @@ -623,41 +619,35 @@ static struct prcm_config rate_table[] = { | |||
| 623 | /* Base external input clocks */ | 619 | /* Base external input clocks */ |
| 624 | static struct clk func_32k_ck = { | 620 | static struct clk func_32k_ck = { |
| 625 | .name = "func_32k_ck", | 621 | .name = "func_32k_ck", |
| 622 | .ops = &clkops_null, | ||
| 626 | .rate = 32000, | 623 | .rate = 32000, |
| 627 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 624 | .flags = RATE_FIXED, |
| 628 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, | ||
| 629 | .clkdm_name = "wkup_clkdm", | 625 | .clkdm_name = "wkup_clkdm", |
| 630 | .recalc = &propagate_rate, | ||
| 631 | }; | 626 | }; |
| 632 | 627 | ||
| 633 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ | 628 | /* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */ |
| 634 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ | 629 | static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ |
| 635 | .name = "osc_ck", | 630 | .name = "osc_ck", |
| 636 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 631 | .ops = &clkops_oscck, |
| 637 | RATE_PROPAGATES, | ||
| 638 | .clkdm_name = "wkup_clkdm", | 632 | .clkdm_name = "wkup_clkdm", |
| 639 | .enable = &omap2_enable_osc_ck, | ||
| 640 | .disable = &omap2_disable_osc_ck, | ||
| 641 | .recalc = &omap2_osc_clk_recalc, | 633 | .recalc = &omap2_osc_clk_recalc, |
| 642 | }; | 634 | }; |
| 643 | 635 | ||
| 644 | /* Without modem likely 12MHz, with modem likely 13MHz */ | 636 | /* Without modem likely 12MHz, with modem likely 13MHz */ |
| 645 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ | 637 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ |
| 646 | .name = "sys_ck", /* ~ ref_clk also */ | 638 | .name = "sys_ck", /* ~ ref_clk also */ |
| 639 | .ops = &clkops_null, | ||
| 647 | .parent = &osc_ck, | 640 | .parent = &osc_ck, |
| 648 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 649 | ALWAYS_ENABLED | RATE_PROPAGATES, | ||
| 650 | .clkdm_name = "wkup_clkdm", | 641 | .clkdm_name = "wkup_clkdm", |
| 651 | .recalc = &omap2_sys_clk_recalc, | 642 | .recalc = &omap2_sys_clk_recalc, |
| 652 | }; | 643 | }; |
| 653 | 644 | ||
| 654 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ | 645 | static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ |
| 655 | .name = "alt_ck", | 646 | .name = "alt_ck", |
| 647 | .ops = &clkops_null, | ||
| 656 | .rate = 54000000, | 648 | .rate = 54000000, |
| 657 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 649 | .flags = RATE_FIXED, |
| 658 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, | ||
| 659 | .clkdm_name = "wkup_clkdm", | 650 | .clkdm_name = "wkup_clkdm", |
| 660 | .recalc = &propagate_rate, | ||
| 661 | }; | 651 | }; |
| 662 | 652 | ||
| 663 | /* | 653 | /* |
| @@ -673,7 +663,12 @@ static struct dpll_data dpll_dd = { | |||
| 673 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 663 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 674 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, | 664 | .mult_mask = OMAP24XX_DPLL_MULT_MASK, |
| 675 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, | 665 | .div1_mask = OMAP24XX_DPLL_DIV_MASK, |
| 666 | .clk_bypass = &sys_ck, | ||
| 667 | .clk_ref = &sys_ck, | ||
| 668 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | ||
| 669 | .enable_mask = OMAP24XX_EN_DPLL_MASK, | ||
| 676 | .max_multiplier = 1024, | 670 | .max_multiplier = 1024, |
| 671 | .min_divider = 1, | ||
| 677 | .max_divider = 16, | 672 | .max_divider = 16, |
| 678 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | 673 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
| 679 | }; | 674 | }; |
| @@ -684,10 +679,9 @@ static struct dpll_data dpll_dd = { | |||
| 684 | */ | 679 | */ |
| 685 | static struct clk dpll_ck = { | 680 | static struct clk dpll_ck = { |
| 686 | .name = "dpll_ck", | 681 | .name = "dpll_ck", |
| 682 | .ops = &clkops_null, | ||
| 687 | .parent = &sys_ck, /* Can be func_32k also */ | 683 | .parent = &sys_ck, /* Can be func_32k also */ |
| 688 | .dpll_data = &dpll_dd, | 684 | .dpll_data = &dpll_dd, |
| 689 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 690 | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 691 | .clkdm_name = "wkup_clkdm", | 685 | .clkdm_name = "wkup_clkdm", |
| 692 | .recalc = &omap2_dpllcore_recalc, | 686 | .recalc = &omap2_dpllcore_recalc, |
| 693 | .set_rate = &omap2_reprogram_dpllcore, | 687 | .set_rate = &omap2_reprogram_dpllcore, |
| @@ -695,30 +689,24 @@ static struct clk dpll_ck = { | |||
| 695 | 689 | ||
| 696 | static struct clk apll96_ck = { | 690 | static struct clk apll96_ck = { |
| 697 | .name = "apll96_ck", | 691 | .name = "apll96_ck", |
| 692 | .ops = &clkops_fixed, | ||
| 698 | .parent = &sys_ck, | 693 | .parent = &sys_ck, |
| 699 | .rate = 96000000, | 694 | .rate = 96000000, |
| 700 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 695 | .flags = RATE_FIXED | ENABLE_ON_INIT, |
| 701 | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, | ||
| 702 | .clkdm_name = "wkup_clkdm", | 696 | .clkdm_name = "wkup_clkdm", |
| 703 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 697 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 704 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, | 698 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, |
| 705 | .enable = &omap2_clk_fixed_enable, | ||
| 706 | .disable = &omap2_clk_fixed_disable, | ||
| 707 | .recalc = &propagate_rate, | ||
| 708 | }; | 699 | }; |
| 709 | 700 | ||
| 710 | static struct clk apll54_ck = { | 701 | static struct clk apll54_ck = { |
| 711 | .name = "apll54_ck", | 702 | .name = "apll54_ck", |
| 703 | .ops = &clkops_fixed, | ||
| 712 | .parent = &sys_ck, | 704 | .parent = &sys_ck, |
| 713 | .rate = 54000000, | 705 | .rate = 54000000, |
| 714 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 706 | .flags = RATE_FIXED | ENABLE_ON_INIT, |
| 715 | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, | ||
| 716 | .clkdm_name = "wkup_clkdm", | 707 | .clkdm_name = "wkup_clkdm", |
| 717 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 708 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 718 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, | 709 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, |
| 719 | .enable = &omap2_clk_fixed_enable, | ||
| 720 | .disable = &omap2_clk_fixed_disable, | ||
| 721 | .recalc = &propagate_rate, | ||
| 722 | }; | 710 | }; |
| 723 | 711 | ||
| 724 | /* | 712 | /* |
| @@ -745,9 +733,8 @@ static const struct clksel func_54m_clksel[] = { | |||
| 745 | 733 | ||
| 746 | static struct clk func_54m_ck = { | 734 | static struct clk func_54m_ck = { |
| 747 | .name = "func_54m_ck", | 735 | .name = "func_54m_ck", |
| 736 | .ops = &clkops_null, | ||
| 748 | .parent = &apll54_ck, /* can also be alt_clk */ | 737 | .parent = &apll54_ck, /* can also be alt_clk */ |
| 749 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 750 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, | ||
| 751 | .clkdm_name = "wkup_clkdm", | 738 | .clkdm_name = "wkup_clkdm", |
| 752 | .init = &omap2_init_clksel_parent, | 739 | .init = &omap2_init_clksel_parent, |
| 753 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 740 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| @@ -758,9 +745,8 @@ static struct clk func_54m_ck = { | |||
| 758 | 745 | ||
| 759 | static struct clk core_ck = { | 746 | static struct clk core_ck = { |
| 760 | .name = "core_ck", | 747 | .name = "core_ck", |
| 748 | .ops = &clkops_null, | ||
| 761 | .parent = &dpll_ck, /* can also be 32k */ | 749 | .parent = &dpll_ck, /* can also be 32k */ |
| 762 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 763 | ALWAYS_ENABLED | RATE_PROPAGATES, | ||
| 764 | .clkdm_name = "wkup_clkdm", | 750 | .clkdm_name = "wkup_clkdm", |
| 765 | .recalc = &followparent_recalc, | 751 | .recalc = &followparent_recalc, |
| 766 | }; | 752 | }; |
| @@ -785,9 +771,8 @@ static const struct clksel func_96m_clksel[] = { | |||
| 785 | /* The parent of this clock is not selectable on 2420. */ | 771 | /* The parent of this clock is not selectable on 2420. */ |
| 786 | static struct clk func_96m_ck = { | 772 | static struct clk func_96m_ck = { |
| 787 | .name = "func_96m_ck", | 773 | .name = "func_96m_ck", |
| 774 | .ops = &clkops_null, | ||
| 788 | .parent = &apll96_ck, | 775 | .parent = &apll96_ck, |
| 789 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 790 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, | ||
| 791 | .clkdm_name = "wkup_clkdm", | 776 | .clkdm_name = "wkup_clkdm", |
| 792 | .init = &omap2_init_clksel_parent, | 777 | .init = &omap2_init_clksel_parent, |
| 793 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 778 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| @@ -818,9 +803,8 @@ static const struct clksel func_48m_clksel[] = { | |||
| 818 | 803 | ||
| 819 | static struct clk func_48m_ck = { | 804 | static struct clk func_48m_ck = { |
| 820 | .name = "func_48m_ck", | 805 | .name = "func_48m_ck", |
| 806 | .ops = &clkops_null, | ||
| 821 | .parent = &apll96_ck, /* 96M or Alt */ | 807 | .parent = &apll96_ck, /* 96M or Alt */ |
| 822 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 823 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, | ||
| 824 | .clkdm_name = "wkup_clkdm", | 808 | .clkdm_name = "wkup_clkdm", |
| 825 | .init = &omap2_init_clksel_parent, | 809 | .init = &omap2_init_clksel_parent, |
| 826 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 810 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| @@ -833,10 +817,9 @@ static struct clk func_48m_ck = { | |||
| 833 | 817 | ||
| 834 | static struct clk func_12m_ck = { | 818 | static struct clk func_12m_ck = { |
| 835 | .name = "func_12m_ck", | 819 | .name = "func_12m_ck", |
| 820 | .ops = &clkops_null, | ||
| 836 | .parent = &func_48m_ck, | 821 | .parent = &func_48m_ck, |
| 837 | .fixed_div = 4, | 822 | .fixed_div = 4, |
| 838 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 839 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, | ||
| 840 | .clkdm_name = "wkup_clkdm", | 823 | .clkdm_name = "wkup_clkdm", |
| 841 | .recalc = &omap2_fixed_divisor_recalc, | 824 | .recalc = &omap2_fixed_divisor_recalc, |
| 842 | }; | 825 | }; |
| @@ -844,8 +827,8 @@ static struct clk func_12m_ck = { | |||
| 844 | /* Secure timer, only available in secure mode */ | 827 | /* Secure timer, only available in secure mode */ |
| 845 | static struct clk wdt1_osc_ck = { | 828 | static struct clk wdt1_osc_ck = { |
| 846 | .name = "ck_wdt1_osc", | 829 | .name = "ck_wdt1_osc", |
| 830 | .ops = &clkops_null, /* RMK: missing? */ | ||
| 847 | .parent = &osc_ck, | 831 | .parent = &osc_ck, |
| 848 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 849 | .recalc = &followparent_recalc, | 832 | .recalc = &followparent_recalc, |
| 850 | }; | 833 | }; |
| 851 | 834 | ||
| @@ -887,9 +870,8 @@ static const struct clksel common_clkout_src_clksel[] = { | |||
| 887 | 870 | ||
| 888 | static struct clk sys_clkout_src = { | 871 | static struct clk sys_clkout_src = { |
| 889 | .name = "sys_clkout_src", | 872 | .name = "sys_clkout_src", |
| 873 | .ops = &clkops_omap2_dflt, | ||
| 890 | .parent = &func_54m_ck, | 874 | .parent = &func_54m_ck, |
| 891 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 892 | RATE_PROPAGATES, | ||
| 893 | .clkdm_name = "wkup_clkdm", | 875 | .clkdm_name = "wkup_clkdm", |
| 894 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 876 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
| 895 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, | 877 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, |
| @@ -918,9 +900,8 @@ static const struct clksel sys_clkout_clksel[] = { | |||
| 918 | 900 | ||
| 919 | static struct clk sys_clkout = { | 901 | static struct clk sys_clkout = { |
| 920 | .name = "sys_clkout", | 902 | .name = "sys_clkout", |
| 903 | .ops = &clkops_null, | ||
| 921 | .parent = &sys_clkout_src, | 904 | .parent = &sys_clkout_src, |
| 922 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
| 923 | PARENT_CONTROLS_CLOCK, | ||
| 924 | .clkdm_name = "wkup_clkdm", | 905 | .clkdm_name = "wkup_clkdm", |
| 925 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 906 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
| 926 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, | 907 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, |
| @@ -933,8 +914,8 @@ static struct clk sys_clkout = { | |||
| 933 | /* In 2430, new in 2420 ES2 */ | 914 | /* In 2430, new in 2420 ES2 */ |
| 934 | static struct clk sys_clkout2_src = { | 915 | static struct clk sys_clkout2_src = { |
| 935 | .name = "sys_clkout2_src", | 916 | .name = "sys_clkout2_src", |
| 917 | .ops = &clkops_omap2_dflt, | ||
| 936 | .parent = &func_54m_ck, | 918 | .parent = &func_54m_ck, |
| 937 | .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES, | ||
| 938 | .clkdm_name = "wkup_clkdm", | 919 | .clkdm_name = "wkup_clkdm", |
| 939 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 920 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
| 940 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, | 921 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, |
| @@ -955,8 +936,8 @@ static const struct clksel sys_clkout2_clksel[] = { | |||
| 955 | /* In 2430, new in 2420 ES2 */ | 936 | /* In 2430, new in 2420 ES2 */ |
| 956 | static struct clk sys_clkout2 = { | 937 | static struct clk sys_clkout2 = { |
| 957 | .name = "sys_clkout2", | 938 | .name = "sys_clkout2", |
| 939 | .ops = &clkops_null, | ||
| 958 | .parent = &sys_clkout2_src, | 940 | .parent = &sys_clkout2_src, |
| 959 | .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK, | ||
| 960 | .clkdm_name = "wkup_clkdm", | 941 | .clkdm_name = "wkup_clkdm", |
| 961 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 942 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
| 962 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, | 943 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, |
| @@ -968,8 +949,8 @@ static struct clk sys_clkout2 = { | |||
| 968 | 949 | ||
| 969 | static struct clk emul_ck = { | 950 | static struct clk emul_ck = { |
| 970 | .name = "emul_ck", | 951 | .name = "emul_ck", |
| 952 | .ops = &clkops_omap2_dflt, | ||
| 971 | .parent = &func_54m_ck, | 953 | .parent = &func_54m_ck, |
| 972 | .flags = CLOCK_IN_OMAP242X, | ||
| 973 | .clkdm_name = "wkup_clkdm", | 954 | .clkdm_name = "wkup_clkdm", |
| 974 | .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, | 955 | .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, |
| 975 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, | 956 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, |
| @@ -1003,10 +984,9 @@ static const struct clksel mpu_clksel[] = { | |||
| 1003 | 984 | ||
| 1004 | static struct clk mpu_ck = { /* Control cpu */ | 985 | static struct clk mpu_ck = { /* Control cpu */ |
| 1005 | .name = "mpu_ck", | 986 | .name = "mpu_ck", |
| 987 | .ops = &clkops_null, | ||
| 1006 | .parent = &core_ck, | 988 | .parent = &core_ck, |
| 1007 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 989 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
| 1008 | ALWAYS_ENABLED | DELAYED_APP | | ||
| 1009 | CONFIG_PARTICIPANT | RATE_PROPAGATES, | ||
| 1010 | .clkdm_name = "mpu_clkdm", | 990 | .clkdm_name = "mpu_clkdm", |
| 1011 | .init = &omap2_init_clksel_parent, | 991 | .init = &omap2_init_clksel_parent, |
| 1012 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | 992 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), |
| @@ -1046,9 +1026,9 @@ static const struct clksel dsp_fck_clksel[] = { | |||
| 1046 | 1026 | ||
| 1047 | static struct clk dsp_fck = { | 1027 | static struct clk dsp_fck = { |
| 1048 | .name = "dsp_fck", | 1028 | .name = "dsp_fck", |
| 1029 | .ops = &clkops_omap2_dflt_wait, | ||
| 1049 | .parent = &core_ck, | 1030 | .parent = &core_ck, |
| 1050 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | | 1031 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
| 1051 | CONFIG_PARTICIPANT | RATE_PROPAGATES, | ||
| 1052 | .clkdm_name = "dsp_clkdm", | 1032 | .clkdm_name = "dsp_clkdm", |
| 1053 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 1033 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 1054 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | 1034 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
| @@ -1076,9 +1056,9 @@ static const struct clksel dsp_irate_ick_clksel[] = { | |||
| 1076 | /* This clock does not exist as such in the TRM. */ | 1056 | /* This clock does not exist as such in the TRM. */ |
| 1077 | static struct clk dsp_irate_ick = { | 1057 | static struct clk dsp_irate_ick = { |
| 1078 | .name = "dsp_irate_ick", | 1058 | .name = "dsp_irate_ick", |
| 1059 | .ops = &clkops_null, | ||
| 1079 | .parent = &dsp_fck, | 1060 | .parent = &dsp_fck, |
| 1080 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | | 1061 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
| 1081 | CONFIG_PARTICIPANT | PARENT_CONTROLS_CLOCK, | ||
| 1082 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | 1062 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
| 1083 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, | 1063 | .clksel_mask = OMAP24XX_CLKSEL_DSP_IF_MASK, |
| 1084 | .clksel = dsp_irate_ick_clksel, | 1064 | .clksel = dsp_irate_ick_clksel, |
| @@ -1090,8 +1070,9 @@ static struct clk dsp_irate_ick = { | |||
| 1090 | /* 2420 only */ | 1070 | /* 2420 only */ |
| 1091 | static struct clk dsp_ick = { | 1071 | static struct clk dsp_ick = { |
| 1092 | .name = "dsp_ick", /* apparently ipi and isp */ | 1072 | .name = "dsp_ick", /* apparently ipi and isp */ |
| 1073 | .ops = &clkops_omap2_dflt_wait, | ||
| 1093 | .parent = &dsp_irate_ick, | 1074 | .parent = &dsp_irate_ick, |
| 1094 | .flags = CLOCK_IN_OMAP242X | DELAYED_APP | CONFIG_PARTICIPANT, | 1075 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
| 1095 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), | 1076 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN), |
| 1096 | .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ | 1077 | .enable_bit = OMAP2420_EN_DSP_IPI_SHIFT, /* for ipi */ |
| 1097 | }; | 1078 | }; |
| @@ -1099,8 +1080,9 @@ static struct clk dsp_ick = { | |||
| 1099 | /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ | 1080 | /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */ |
| 1100 | static struct clk iva2_1_ick = { | 1081 | static struct clk iva2_1_ick = { |
| 1101 | .name = "iva2_1_ick", | 1082 | .name = "iva2_1_ick", |
| 1083 | .ops = &clkops_omap2_dflt_wait, | ||
| 1102 | .parent = &dsp_irate_ick, | 1084 | .parent = &dsp_irate_ick, |
| 1103 | .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, | 1085 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
| 1104 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 1086 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 1105 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | 1087 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
| 1106 | }; | 1088 | }; |
| @@ -1112,9 +1094,9 @@ static struct clk iva2_1_ick = { | |||
| 1112 | */ | 1094 | */ |
| 1113 | static struct clk iva1_ifck = { | 1095 | static struct clk iva1_ifck = { |
| 1114 | .name = "iva1_ifck", | 1096 | .name = "iva1_ifck", |
| 1097 | .ops = &clkops_omap2_dflt_wait, | ||
| 1115 | .parent = &core_ck, | 1098 | .parent = &core_ck, |
| 1116 | .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | | 1099 | .flags = CONFIG_PARTICIPANT | DELAYED_APP, |
| 1117 | RATE_PROPAGATES | DELAYED_APP, | ||
| 1118 | .clkdm_name = "iva1_clkdm", | 1100 | .clkdm_name = "iva1_clkdm", |
| 1119 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 1101 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 1120 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, | 1102 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, |
| @@ -1129,8 +1111,8 @@ static struct clk iva1_ifck = { | |||
| 1129 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ | 1111 | /* IVA1 mpu/int/i/f clocks are /2 of parent */ |
| 1130 | static struct clk iva1_mpu_int_ifck = { | 1112 | static struct clk iva1_mpu_int_ifck = { |
| 1131 | .name = "iva1_mpu_int_ifck", | 1113 | .name = "iva1_mpu_int_ifck", |
| 1114 | .ops = &clkops_omap2_dflt_wait, | ||
| 1132 | .parent = &iva1_ifck, | 1115 | .parent = &iva1_ifck, |
| 1133 | .flags = CLOCK_IN_OMAP242X, | ||
| 1134 | .clkdm_name = "iva1_clkdm", | 1116 | .clkdm_name = "iva1_clkdm", |
| 1135 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 1117 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
| 1136 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, | 1118 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, |
| @@ -1175,10 +1157,9 @@ static const struct clksel core_l3_clksel[] = { | |||
| 1175 | 1157 | ||
| 1176 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ | 1158 | static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ |
| 1177 | .name = "core_l3_ck", | 1159 | .name = "core_l3_ck", |
| 1160 | .ops = &clkops_null, | ||
| 1178 | .parent = &core_ck, | 1161 | .parent = &core_ck, |
| 1179 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1162 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
| 1180 | ALWAYS_ENABLED | DELAYED_APP | | ||
| 1181 | CONFIG_PARTICIPANT | RATE_PROPAGATES, | ||
| 1182 | .clkdm_name = "core_l3_clkdm", | 1163 | .clkdm_name = "core_l3_clkdm", |
| 1183 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 1164 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 1184 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, | 1165 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, |
| @@ -1204,9 +1185,9 @@ static const struct clksel usb_l4_ick_clksel[] = { | |||
| 1204 | /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ | 1185 | /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ |
| 1205 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ | 1186 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ |
| 1206 | .name = "usb_l4_ick", | 1187 | .name = "usb_l4_ick", |
| 1188 | .ops = &clkops_omap2_dflt_wait, | ||
| 1207 | .parent = &core_l3_ck, | 1189 | .parent = &core_l3_ck, |
| 1208 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1190 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
| 1209 | DELAYED_APP | CONFIG_PARTICIPANT, | ||
| 1210 | .clkdm_name = "core_l4_clkdm", | 1191 | .clkdm_name = "core_l4_clkdm", |
| 1211 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1192 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1212 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | 1193 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
| @@ -1238,9 +1219,9 @@ static const struct clksel l4_clksel[] = { | |||
| 1238 | 1219 | ||
| 1239 | static struct clk l4_ck = { /* used both as an ick and fck */ | 1220 | static struct clk l4_ck = { /* used both as an ick and fck */ |
| 1240 | .name = "l4_ck", | 1221 | .name = "l4_ck", |
| 1222 | .ops = &clkops_null, | ||
| 1241 | .parent = &core_l3_ck, | 1223 | .parent = &core_l3_ck, |
| 1242 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1224 | .flags = DELAYED_APP, |
| 1243 | ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES, | ||
| 1244 | .clkdm_name = "core_l4_clkdm", | 1225 | .clkdm_name = "core_l4_clkdm", |
| 1245 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 1226 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
| 1246 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, | 1227 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, |
| @@ -1276,9 +1257,9 @@ static const struct clksel ssi_ssr_sst_fck_clksel[] = { | |||
| 1276 | 1257 | ||
| 1277 | static struct clk ssi_ssr_sst_fck = { | 1258 | static struct clk ssi_ssr_sst_fck = { |
| 1278 | .name = "ssi_fck", | 1259 | .name = "ssi_fck", |
| 1260 | .ops = &clkops_omap2_dflt_wait, | ||
| 1279 | .parent = &core_ck, | 1261 | .parent = &core_ck, |
| 1280 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1262 | .flags = DELAYED_APP, |
| 1281 | DELAYED_APP, | ||
| 1282 | .clkdm_name = "core_l3_clkdm", | 1263 | .clkdm_name = "core_l3_clkdm", |
| 1283 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1264 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1284 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | 1265 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, |
| @@ -1290,6 +1271,20 @@ static struct clk ssi_ssr_sst_fck = { | |||
| 1290 | .set_rate = &omap2_clksel_set_rate | 1271 | .set_rate = &omap2_clksel_set_rate |
| 1291 | }; | 1272 | }; |
| 1292 | 1273 | ||
| 1274 | /* | ||
| 1275 | * Presumably this is the same as SSI_ICLK. | ||
| 1276 | * TRM contradicts itself on what clockdomain SSI_ICLK is in | ||
| 1277 | */ | ||
| 1278 | static struct clk ssi_l4_ick = { | ||
| 1279 | .name = "ssi_l4_ick", | ||
| 1280 | .ops = &clkops_omap2_dflt_wait, | ||
| 1281 | .parent = &l4_ck, | ||
| 1282 | .clkdm_name = "core_l4_clkdm", | ||
| 1283 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
| 1284 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | ||
| 1285 | .recalc = &followparent_recalc, | ||
| 1286 | }; | ||
| 1287 | |||
| 1293 | 1288 | ||
| 1294 | /* | 1289 | /* |
| 1295 | * GFX clock domain | 1290 | * GFX clock domain |
| @@ -1312,8 +1307,8 @@ static const struct clksel gfx_fck_clksel[] = { | |||
| 1312 | 1307 | ||
| 1313 | static struct clk gfx_3d_fck = { | 1308 | static struct clk gfx_3d_fck = { |
| 1314 | .name = "gfx_3d_fck", | 1309 | .name = "gfx_3d_fck", |
| 1310 | .ops = &clkops_omap2_dflt_wait, | ||
| 1315 | .parent = &core_l3_ck, | 1311 | .parent = &core_l3_ck, |
| 1316 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1317 | .clkdm_name = "gfx_clkdm", | 1312 | .clkdm_name = "gfx_clkdm", |
| 1318 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 1313 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1319 | .enable_bit = OMAP24XX_EN_3D_SHIFT, | 1314 | .enable_bit = OMAP24XX_EN_3D_SHIFT, |
| @@ -1327,8 +1322,8 @@ static struct clk gfx_3d_fck = { | |||
| 1327 | 1322 | ||
| 1328 | static struct clk gfx_2d_fck = { | 1323 | static struct clk gfx_2d_fck = { |
| 1329 | .name = "gfx_2d_fck", | 1324 | .name = "gfx_2d_fck", |
| 1325 | .ops = &clkops_omap2_dflt_wait, | ||
| 1330 | .parent = &core_l3_ck, | 1326 | .parent = &core_l3_ck, |
| 1331 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1332 | .clkdm_name = "gfx_clkdm", | 1327 | .clkdm_name = "gfx_clkdm", |
| 1333 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 1328 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1334 | .enable_bit = OMAP24XX_EN_2D_SHIFT, | 1329 | .enable_bit = OMAP24XX_EN_2D_SHIFT, |
| @@ -1342,8 +1337,8 @@ static struct clk gfx_2d_fck = { | |||
| 1342 | 1337 | ||
| 1343 | static struct clk gfx_ick = { | 1338 | static struct clk gfx_ick = { |
| 1344 | .name = "gfx_ick", /* From l3 */ | 1339 | .name = "gfx_ick", /* From l3 */ |
| 1340 | .ops = &clkops_omap2_dflt_wait, | ||
| 1345 | .parent = &core_l3_ck, | 1341 | .parent = &core_l3_ck, |
| 1346 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1347 | .clkdm_name = "gfx_clkdm", | 1342 | .clkdm_name = "gfx_clkdm", |
| 1348 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | 1343 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
| 1349 | .enable_bit = OMAP_EN_GFX_SHIFT, | 1344 | .enable_bit = OMAP_EN_GFX_SHIFT, |
| @@ -1372,8 +1367,9 @@ static const struct clksel mdm_ick_clksel[] = { | |||
| 1372 | 1367 | ||
| 1373 | static struct clk mdm_ick = { /* used both as a ick and fck */ | 1368 | static struct clk mdm_ick = { /* used both as a ick and fck */ |
| 1374 | .name = "mdm_ick", | 1369 | .name = "mdm_ick", |
| 1370 | .ops = &clkops_omap2_dflt_wait, | ||
| 1375 | .parent = &core_ck, | 1371 | .parent = &core_ck, |
| 1376 | .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, | 1372 | .flags = DELAYED_APP | CONFIG_PARTICIPANT, |
| 1377 | .clkdm_name = "mdm_clkdm", | 1373 | .clkdm_name = "mdm_clkdm", |
| 1378 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), | 1374 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), |
| 1379 | .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, | 1375 | .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, |
| @@ -1387,8 +1383,8 @@ static struct clk mdm_ick = { /* used both as a ick and fck */ | |||
| 1387 | 1383 | ||
| 1388 | static struct clk mdm_osc_ck = { | 1384 | static struct clk mdm_osc_ck = { |
| 1389 | .name = "mdm_osc_ck", | 1385 | .name = "mdm_osc_ck", |
| 1386 | .ops = &clkops_omap2_dflt_wait, | ||
| 1390 | .parent = &osc_ck, | 1387 | .parent = &osc_ck, |
| 1391 | .flags = CLOCK_IN_OMAP243X, | ||
| 1392 | .clkdm_name = "mdm_clkdm", | 1388 | .clkdm_name = "mdm_clkdm", |
| 1393 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), | 1389 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), |
| 1394 | .enable_bit = OMAP2430_EN_OSC_SHIFT, | 1390 | .enable_bit = OMAP2430_EN_OSC_SHIFT, |
| @@ -1432,8 +1428,8 @@ static const struct clksel dss1_fck_clksel[] = { | |||
| 1432 | 1428 | ||
| 1433 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ | 1429 | static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ |
| 1434 | .name = "dss_ick", | 1430 | .name = "dss_ick", |
| 1431 | .ops = &clkops_omap2_dflt, | ||
| 1435 | .parent = &l4_ck, /* really both l3 and l4 */ | 1432 | .parent = &l4_ck, /* really both l3 and l4 */ |
| 1436 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1437 | .clkdm_name = "dss_clkdm", | 1433 | .clkdm_name = "dss_clkdm", |
| 1438 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1434 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1439 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | 1435 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
| @@ -1442,9 +1438,9 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ | |||
| 1442 | 1438 | ||
| 1443 | static struct clk dss1_fck = { | 1439 | static struct clk dss1_fck = { |
| 1444 | .name = "dss1_fck", | 1440 | .name = "dss1_fck", |
| 1441 | .ops = &clkops_omap2_dflt, | ||
| 1445 | .parent = &core_ck, /* Core or sys */ | 1442 | .parent = &core_ck, /* Core or sys */ |
| 1446 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1443 | .flags = DELAYED_APP, |
| 1447 | DELAYED_APP, | ||
| 1448 | .clkdm_name = "dss_clkdm", | 1444 | .clkdm_name = "dss_clkdm", |
| 1449 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1445 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1450 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | 1446 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
| @@ -1475,9 +1471,9 @@ static const struct clksel dss2_fck_clksel[] = { | |||
| 1475 | 1471 | ||
| 1476 | static struct clk dss2_fck = { /* Alt clk used in power management */ | 1472 | static struct clk dss2_fck = { /* Alt clk used in power management */ |
| 1477 | .name = "dss2_fck", | 1473 | .name = "dss2_fck", |
| 1474 | .ops = &clkops_omap2_dflt, | ||
| 1478 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ | 1475 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ |
| 1479 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1476 | .flags = DELAYED_APP, |
| 1480 | DELAYED_APP, | ||
| 1481 | .clkdm_name = "dss_clkdm", | 1477 | .clkdm_name = "dss_clkdm", |
| 1482 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1478 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1483 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, | 1479 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, |
| @@ -1490,8 +1486,8 @@ static struct clk dss2_fck = { /* Alt clk used in power management */ | |||
| 1490 | 1486 | ||
| 1491 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ | 1487 | static struct clk dss_54m_fck = { /* Alt clk used in power management */ |
| 1492 | .name = "dss_54m_fck", /* 54m tv clk */ | 1488 | .name = "dss_54m_fck", /* 54m tv clk */ |
| 1489 | .ops = &clkops_omap2_dflt_wait, | ||
| 1493 | .parent = &func_54m_ck, | 1490 | .parent = &func_54m_ck, |
| 1494 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1495 | .clkdm_name = "dss_clkdm", | 1491 | .clkdm_name = "dss_clkdm", |
| 1496 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1492 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1497 | .enable_bit = OMAP24XX_EN_TV_SHIFT, | 1493 | .enable_bit = OMAP24XX_EN_TV_SHIFT, |
| @@ -1518,8 +1514,8 @@ static const struct clksel omap24xx_gpt_clksel[] = { | |||
| 1518 | 1514 | ||
| 1519 | static struct clk gpt1_ick = { | 1515 | static struct clk gpt1_ick = { |
| 1520 | .name = "gpt1_ick", | 1516 | .name = "gpt1_ick", |
| 1517 | .ops = &clkops_omap2_dflt_wait, | ||
| 1521 | .parent = &l4_ck, | 1518 | .parent = &l4_ck, |
| 1522 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1523 | .clkdm_name = "core_l4_clkdm", | 1519 | .clkdm_name = "core_l4_clkdm", |
| 1524 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 1520 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 1525 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | 1521 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, |
| @@ -1528,8 +1524,8 @@ static struct clk gpt1_ick = { | |||
| 1528 | 1524 | ||
| 1529 | static struct clk gpt1_fck = { | 1525 | static struct clk gpt1_fck = { |
| 1530 | .name = "gpt1_fck", | 1526 | .name = "gpt1_fck", |
| 1527 | .ops = &clkops_omap2_dflt_wait, | ||
| 1531 | .parent = &func_32k_ck, | 1528 | .parent = &func_32k_ck, |
| 1532 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1533 | .clkdm_name = "core_l4_clkdm", | 1529 | .clkdm_name = "core_l4_clkdm", |
| 1534 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 1530 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 1535 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | 1531 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, |
| @@ -1544,8 +1540,8 @@ static struct clk gpt1_fck = { | |||
| 1544 | 1540 | ||
| 1545 | static struct clk gpt2_ick = { | 1541 | static struct clk gpt2_ick = { |
| 1546 | .name = "gpt2_ick", | 1542 | .name = "gpt2_ick", |
| 1543 | .ops = &clkops_omap2_dflt_wait, | ||
| 1547 | .parent = &l4_ck, | 1544 | .parent = &l4_ck, |
| 1548 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1549 | .clkdm_name = "core_l4_clkdm", | 1545 | .clkdm_name = "core_l4_clkdm", |
| 1550 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1546 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1551 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | 1547 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, |
| @@ -1554,8 +1550,8 @@ static struct clk gpt2_ick = { | |||
| 1554 | 1550 | ||
| 1555 | static struct clk gpt2_fck = { | 1551 | static struct clk gpt2_fck = { |
| 1556 | .name = "gpt2_fck", | 1552 | .name = "gpt2_fck", |
| 1553 | .ops = &clkops_omap2_dflt_wait, | ||
| 1557 | .parent = &func_32k_ck, | 1554 | .parent = &func_32k_ck, |
| 1558 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1559 | .clkdm_name = "core_l4_clkdm", | 1555 | .clkdm_name = "core_l4_clkdm", |
| 1560 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1556 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1561 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | 1557 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, |
| @@ -1568,8 +1564,8 @@ static struct clk gpt2_fck = { | |||
| 1568 | 1564 | ||
| 1569 | static struct clk gpt3_ick = { | 1565 | static struct clk gpt3_ick = { |
| 1570 | .name = "gpt3_ick", | 1566 | .name = "gpt3_ick", |
| 1567 | .ops = &clkops_omap2_dflt_wait, | ||
| 1571 | .parent = &l4_ck, | 1568 | .parent = &l4_ck, |
| 1572 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1573 | .clkdm_name = "core_l4_clkdm", | 1569 | .clkdm_name = "core_l4_clkdm", |
| 1574 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1570 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1575 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | 1571 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, |
| @@ -1578,8 +1574,8 @@ static struct clk gpt3_ick = { | |||
| 1578 | 1574 | ||
| 1579 | static struct clk gpt3_fck = { | 1575 | static struct clk gpt3_fck = { |
| 1580 | .name = "gpt3_fck", | 1576 | .name = "gpt3_fck", |
| 1577 | .ops = &clkops_omap2_dflt_wait, | ||
| 1581 | .parent = &func_32k_ck, | 1578 | .parent = &func_32k_ck, |
| 1582 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1583 | .clkdm_name = "core_l4_clkdm", | 1579 | .clkdm_name = "core_l4_clkdm", |
| 1584 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1580 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1585 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | 1581 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, |
| @@ -1592,8 +1588,8 @@ static struct clk gpt3_fck = { | |||
| 1592 | 1588 | ||
| 1593 | static struct clk gpt4_ick = { | 1589 | static struct clk gpt4_ick = { |
| 1594 | .name = "gpt4_ick", | 1590 | .name = "gpt4_ick", |
| 1591 | .ops = &clkops_omap2_dflt_wait, | ||
| 1595 | .parent = &l4_ck, | 1592 | .parent = &l4_ck, |
| 1596 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1597 | .clkdm_name = "core_l4_clkdm", | 1593 | .clkdm_name = "core_l4_clkdm", |
| 1598 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1594 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1599 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | 1595 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, |
| @@ -1602,8 +1598,8 @@ static struct clk gpt4_ick = { | |||
| 1602 | 1598 | ||
| 1603 | static struct clk gpt4_fck = { | 1599 | static struct clk gpt4_fck = { |
| 1604 | .name = "gpt4_fck", | 1600 | .name = "gpt4_fck", |
| 1601 | .ops = &clkops_omap2_dflt_wait, | ||
| 1605 | .parent = &func_32k_ck, | 1602 | .parent = &func_32k_ck, |
| 1606 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1607 | .clkdm_name = "core_l4_clkdm", | 1603 | .clkdm_name = "core_l4_clkdm", |
| 1608 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1604 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1609 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | 1605 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, |
| @@ -1616,8 +1612,8 @@ static struct clk gpt4_fck = { | |||
| 1616 | 1612 | ||
| 1617 | static struct clk gpt5_ick = { | 1613 | static struct clk gpt5_ick = { |
| 1618 | .name = "gpt5_ick", | 1614 | .name = "gpt5_ick", |
| 1615 | .ops = &clkops_omap2_dflt_wait, | ||
| 1619 | .parent = &l4_ck, | 1616 | .parent = &l4_ck, |
| 1620 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1621 | .clkdm_name = "core_l4_clkdm", | 1617 | .clkdm_name = "core_l4_clkdm", |
| 1622 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1618 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1623 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | 1619 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, |
| @@ -1626,8 +1622,8 @@ static struct clk gpt5_ick = { | |||
| 1626 | 1622 | ||
| 1627 | static struct clk gpt5_fck = { | 1623 | static struct clk gpt5_fck = { |
| 1628 | .name = "gpt5_fck", | 1624 | .name = "gpt5_fck", |
| 1625 | .ops = &clkops_omap2_dflt_wait, | ||
| 1629 | .parent = &func_32k_ck, | 1626 | .parent = &func_32k_ck, |
| 1630 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1631 | .clkdm_name = "core_l4_clkdm", | 1627 | .clkdm_name = "core_l4_clkdm", |
| 1632 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1628 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1633 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | 1629 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, |
| @@ -1640,8 +1636,8 @@ static struct clk gpt5_fck = { | |||
| 1640 | 1636 | ||
| 1641 | static struct clk gpt6_ick = { | 1637 | static struct clk gpt6_ick = { |
| 1642 | .name = "gpt6_ick", | 1638 | .name = "gpt6_ick", |
| 1639 | .ops = &clkops_omap2_dflt_wait, | ||
| 1643 | .parent = &l4_ck, | 1640 | .parent = &l4_ck, |
| 1644 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1645 | .clkdm_name = "core_l4_clkdm", | 1641 | .clkdm_name = "core_l4_clkdm", |
| 1646 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1642 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1647 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | 1643 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, |
| @@ -1650,8 +1646,8 @@ static struct clk gpt6_ick = { | |||
| 1650 | 1646 | ||
| 1651 | static struct clk gpt6_fck = { | 1647 | static struct clk gpt6_fck = { |
| 1652 | .name = "gpt6_fck", | 1648 | .name = "gpt6_fck", |
| 1649 | .ops = &clkops_omap2_dflt_wait, | ||
| 1653 | .parent = &func_32k_ck, | 1650 | .parent = &func_32k_ck, |
| 1654 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1655 | .clkdm_name = "core_l4_clkdm", | 1651 | .clkdm_name = "core_l4_clkdm", |
| 1656 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1652 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1657 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | 1653 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, |
| @@ -1664,8 +1660,8 @@ static struct clk gpt6_fck = { | |||
| 1664 | 1660 | ||
| 1665 | static struct clk gpt7_ick = { | 1661 | static struct clk gpt7_ick = { |
| 1666 | .name = "gpt7_ick", | 1662 | .name = "gpt7_ick", |
| 1663 | .ops = &clkops_omap2_dflt_wait, | ||
| 1667 | .parent = &l4_ck, | 1664 | .parent = &l4_ck, |
| 1668 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1669 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1665 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1670 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | 1666 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, |
| 1671 | .recalc = &followparent_recalc, | 1667 | .recalc = &followparent_recalc, |
| @@ -1673,8 +1669,8 @@ static struct clk gpt7_ick = { | |||
| 1673 | 1669 | ||
| 1674 | static struct clk gpt7_fck = { | 1670 | static struct clk gpt7_fck = { |
| 1675 | .name = "gpt7_fck", | 1671 | .name = "gpt7_fck", |
| 1672 | .ops = &clkops_omap2_dflt_wait, | ||
| 1676 | .parent = &func_32k_ck, | 1673 | .parent = &func_32k_ck, |
| 1677 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1678 | .clkdm_name = "core_l4_clkdm", | 1674 | .clkdm_name = "core_l4_clkdm", |
| 1679 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1675 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1680 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | 1676 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, |
| @@ -1687,8 +1683,8 @@ static struct clk gpt7_fck = { | |||
| 1687 | 1683 | ||
| 1688 | static struct clk gpt8_ick = { | 1684 | static struct clk gpt8_ick = { |
| 1689 | .name = "gpt8_ick", | 1685 | .name = "gpt8_ick", |
| 1686 | .ops = &clkops_omap2_dflt_wait, | ||
| 1690 | .parent = &l4_ck, | 1687 | .parent = &l4_ck, |
| 1691 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1692 | .clkdm_name = "core_l4_clkdm", | 1688 | .clkdm_name = "core_l4_clkdm", |
| 1693 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1689 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1694 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | 1690 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, |
| @@ -1697,8 +1693,8 @@ static struct clk gpt8_ick = { | |||
| 1697 | 1693 | ||
| 1698 | static struct clk gpt8_fck = { | 1694 | static struct clk gpt8_fck = { |
| 1699 | .name = "gpt8_fck", | 1695 | .name = "gpt8_fck", |
| 1696 | .ops = &clkops_omap2_dflt_wait, | ||
| 1700 | .parent = &func_32k_ck, | 1697 | .parent = &func_32k_ck, |
| 1701 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1702 | .clkdm_name = "core_l4_clkdm", | 1698 | .clkdm_name = "core_l4_clkdm", |
| 1703 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1699 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1704 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | 1700 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, |
| @@ -1711,8 +1707,8 @@ static struct clk gpt8_fck = { | |||
| 1711 | 1707 | ||
| 1712 | static struct clk gpt9_ick = { | 1708 | static struct clk gpt9_ick = { |
| 1713 | .name = "gpt9_ick", | 1709 | .name = "gpt9_ick", |
| 1710 | .ops = &clkops_omap2_dflt_wait, | ||
| 1714 | .parent = &l4_ck, | 1711 | .parent = &l4_ck, |
| 1715 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1716 | .clkdm_name = "core_l4_clkdm", | 1712 | .clkdm_name = "core_l4_clkdm", |
| 1717 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1713 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1718 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | 1714 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, |
| @@ -1721,8 +1717,8 @@ static struct clk gpt9_ick = { | |||
| 1721 | 1717 | ||
| 1722 | static struct clk gpt9_fck = { | 1718 | static struct clk gpt9_fck = { |
| 1723 | .name = "gpt9_fck", | 1719 | .name = "gpt9_fck", |
| 1720 | .ops = &clkops_omap2_dflt_wait, | ||
| 1724 | .parent = &func_32k_ck, | 1721 | .parent = &func_32k_ck, |
| 1725 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1726 | .clkdm_name = "core_l4_clkdm", | 1722 | .clkdm_name = "core_l4_clkdm", |
| 1727 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1723 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1728 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | 1724 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, |
| @@ -1735,8 +1731,8 @@ static struct clk gpt9_fck = { | |||
| 1735 | 1731 | ||
| 1736 | static struct clk gpt10_ick = { | 1732 | static struct clk gpt10_ick = { |
| 1737 | .name = "gpt10_ick", | 1733 | .name = "gpt10_ick", |
| 1734 | .ops = &clkops_omap2_dflt_wait, | ||
| 1738 | .parent = &l4_ck, | 1735 | .parent = &l4_ck, |
| 1739 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1740 | .clkdm_name = "core_l4_clkdm", | 1736 | .clkdm_name = "core_l4_clkdm", |
| 1741 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1737 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1742 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | 1738 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, |
| @@ -1745,8 +1741,8 @@ static struct clk gpt10_ick = { | |||
| 1745 | 1741 | ||
| 1746 | static struct clk gpt10_fck = { | 1742 | static struct clk gpt10_fck = { |
| 1747 | .name = "gpt10_fck", | 1743 | .name = "gpt10_fck", |
| 1744 | .ops = &clkops_omap2_dflt_wait, | ||
| 1748 | .parent = &func_32k_ck, | 1745 | .parent = &func_32k_ck, |
| 1749 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1750 | .clkdm_name = "core_l4_clkdm", | 1746 | .clkdm_name = "core_l4_clkdm", |
| 1751 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1747 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1752 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | 1748 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, |
| @@ -1759,8 +1755,8 @@ static struct clk gpt10_fck = { | |||
| 1759 | 1755 | ||
| 1760 | static struct clk gpt11_ick = { | 1756 | static struct clk gpt11_ick = { |
| 1761 | .name = "gpt11_ick", | 1757 | .name = "gpt11_ick", |
| 1758 | .ops = &clkops_omap2_dflt_wait, | ||
| 1762 | .parent = &l4_ck, | 1759 | .parent = &l4_ck, |
| 1763 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1764 | .clkdm_name = "core_l4_clkdm", | 1760 | .clkdm_name = "core_l4_clkdm", |
| 1765 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1761 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1766 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | 1762 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, |
| @@ -1769,8 +1765,8 @@ static struct clk gpt11_ick = { | |||
| 1769 | 1765 | ||
| 1770 | static struct clk gpt11_fck = { | 1766 | static struct clk gpt11_fck = { |
| 1771 | .name = "gpt11_fck", | 1767 | .name = "gpt11_fck", |
| 1768 | .ops = &clkops_omap2_dflt_wait, | ||
| 1772 | .parent = &func_32k_ck, | 1769 | .parent = &func_32k_ck, |
| 1773 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1774 | .clkdm_name = "core_l4_clkdm", | 1770 | .clkdm_name = "core_l4_clkdm", |
| 1775 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1771 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1776 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | 1772 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, |
| @@ -1783,8 +1779,8 @@ static struct clk gpt11_fck = { | |||
| 1783 | 1779 | ||
| 1784 | static struct clk gpt12_ick = { | 1780 | static struct clk gpt12_ick = { |
| 1785 | .name = "gpt12_ick", | 1781 | .name = "gpt12_ick", |
| 1782 | .ops = &clkops_omap2_dflt_wait, | ||
| 1786 | .parent = &l4_ck, | 1783 | .parent = &l4_ck, |
| 1787 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1788 | .clkdm_name = "core_l4_clkdm", | 1784 | .clkdm_name = "core_l4_clkdm", |
| 1789 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1785 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1790 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | 1786 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, |
| @@ -1793,8 +1789,8 @@ static struct clk gpt12_ick = { | |||
| 1793 | 1789 | ||
| 1794 | static struct clk gpt12_fck = { | 1790 | static struct clk gpt12_fck = { |
| 1795 | .name = "gpt12_fck", | 1791 | .name = "gpt12_fck", |
| 1792 | .ops = &clkops_omap2_dflt_wait, | ||
| 1796 | .parent = &func_32k_ck, | 1793 | .parent = &func_32k_ck, |
| 1797 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1798 | .clkdm_name = "core_l4_clkdm", | 1794 | .clkdm_name = "core_l4_clkdm", |
| 1799 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1795 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1800 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | 1796 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, |
| @@ -1807,9 +1803,9 @@ static struct clk gpt12_fck = { | |||
| 1807 | 1803 | ||
| 1808 | static struct clk mcbsp1_ick = { | 1804 | static struct clk mcbsp1_ick = { |
| 1809 | .name = "mcbsp_ick", | 1805 | .name = "mcbsp_ick", |
| 1806 | .ops = &clkops_omap2_dflt_wait, | ||
| 1810 | .id = 1, | 1807 | .id = 1, |
| 1811 | .parent = &l4_ck, | 1808 | .parent = &l4_ck, |
| 1812 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1813 | .clkdm_name = "core_l4_clkdm", | 1809 | .clkdm_name = "core_l4_clkdm", |
| 1814 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1810 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1815 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | 1811 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
| @@ -1818,9 +1814,9 @@ static struct clk mcbsp1_ick = { | |||
| 1818 | 1814 | ||
| 1819 | static struct clk mcbsp1_fck = { | 1815 | static struct clk mcbsp1_fck = { |
| 1820 | .name = "mcbsp_fck", | 1816 | .name = "mcbsp_fck", |
| 1817 | .ops = &clkops_omap2_dflt_wait, | ||
| 1821 | .id = 1, | 1818 | .id = 1, |
| 1822 | .parent = &func_96m_ck, | 1819 | .parent = &func_96m_ck, |
| 1823 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1824 | .clkdm_name = "core_l4_clkdm", | 1820 | .clkdm_name = "core_l4_clkdm", |
| 1825 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1821 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1826 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | 1822 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
| @@ -1829,9 +1825,9 @@ static struct clk mcbsp1_fck = { | |||
| 1829 | 1825 | ||
| 1830 | static struct clk mcbsp2_ick = { | 1826 | static struct clk mcbsp2_ick = { |
| 1831 | .name = "mcbsp_ick", | 1827 | .name = "mcbsp_ick", |
| 1828 | .ops = &clkops_omap2_dflt_wait, | ||
| 1832 | .id = 2, | 1829 | .id = 2, |
| 1833 | .parent = &l4_ck, | 1830 | .parent = &l4_ck, |
| 1834 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1835 | .clkdm_name = "core_l4_clkdm", | 1831 | .clkdm_name = "core_l4_clkdm", |
| 1836 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1832 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1837 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | 1833 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
| @@ -1840,9 +1836,9 @@ static struct clk mcbsp2_ick = { | |||
| 1840 | 1836 | ||
| 1841 | static struct clk mcbsp2_fck = { | 1837 | static struct clk mcbsp2_fck = { |
| 1842 | .name = "mcbsp_fck", | 1838 | .name = "mcbsp_fck", |
| 1839 | .ops = &clkops_omap2_dflt_wait, | ||
| 1843 | .id = 2, | 1840 | .id = 2, |
| 1844 | .parent = &func_96m_ck, | 1841 | .parent = &func_96m_ck, |
| 1845 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1846 | .clkdm_name = "core_l4_clkdm", | 1842 | .clkdm_name = "core_l4_clkdm", |
| 1847 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1843 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1848 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | 1844 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
| @@ -1851,9 +1847,9 @@ static struct clk mcbsp2_fck = { | |||
| 1851 | 1847 | ||
| 1852 | static struct clk mcbsp3_ick = { | 1848 | static struct clk mcbsp3_ick = { |
| 1853 | .name = "mcbsp_ick", | 1849 | .name = "mcbsp_ick", |
| 1850 | .ops = &clkops_omap2_dflt_wait, | ||
| 1854 | .id = 3, | 1851 | .id = 3, |
| 1855 | .parent = &l4_ck, | 1852 | .parent = &l4_ck, |
| 1856 | .flags = CLOCK_IN_OMAP243X, | ||
| 1857 | .clkdm_name = "core_l4_clkdm", | 1853 | .clkdm_name = "core_l4_clkdm", |
| 1858 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1854 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1859 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, | 1855 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, |
| @@ -1862,9 +1858,9 @@ static struct clk mcbsp3_ick = { | |||
| 1862 | 1858 | ||
| 1863 | static struct clk mcbsp3_fck = { | 1859 | static struct clk mcbsp3_fck = { |
| 1864 | .name = "mcbsp_fck", | 1860 | .name = "mcbsp_fck", |
| 1861 | .ops = &clkops_omap2_dflt_wait, | ||
| 1865 | .id = 3, | 1862 | .id = 3, |
| 1866 | .parent = &func_96m_ck, | 1863 | .parent = &func_96m_ck, |
| 1867 | .flags = CLOCK_IN_OMAP243X, | ||
| 1868 | .clkdm_name = "core_l4_clkdm", | 1864 | .clkdm_name = "core_l4_clkdm", |
| 1869 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1865 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1870 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, | 1866 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, |
| @@ -1873,9 +1869,9 @@ static struct clk mcbsp3_fck = { | |||
| 1873 | 1869 | ||
| 1874 | static struct clk mcbsp4_ick = { | 1870 | static struct clk mcbsp4_ick = { |
| 1875 | .name = "mcbsp_ick", | 1871 | .name = "mcbsp_ick", |
| 1872 | .ops = &clkops_omap2_dflt_wait, | ||
| 1876 | .id = 4, | 1873 | .id = 4, |
| 1877 | .parent = &l4_ck, | 1874 | .parent = &l4_ck, |
| 1878 | .flags = CLOCK_IN_OMAP243X, | ||
| 1879 | .clkdm_name = "core_l4_clkdm", | 1875 | .clkdm_name = "core_l4_clkdm", |
| 1880 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1876 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1881 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, | 1877 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, |
| @@ -1884,9 +1880,9 @@ static struct clk mcbsp4_ick = { | |||
| 1884 | 1880 | ||
| 1885 | static struct clk mcbsp4_fck = { | 1881 | static struct clk mcbsp4_fck = { |
| 1886 | .name = "mcbsp_fck", | 1882 | .name = "mcbsp_fck", |
| 1883 | .ops = &clkops_omap2_dflt_wait, | ||
| 1887 | .id = 4, | 1884 | .id = 4, |
| 1888 | .parent = &func_96m_ck, | 1885 | .parent = &func_96m_ck, |
| 1889 | .flags = CLOCK_IN_OMAP243X, | ||
| 1890 | .clkdm_name = "core_l4_clkdm", | 1886 | .clkdm_name = "core_l4_clkdm", |
| 1891 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1887 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1892 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, | 1888 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, |
| @@ -1895,9 +1891,9 @@ static struct clk mcbsp4_fck = { | |||
| 1895 | 1891 | ||
| 1896 | static struct clk mcbsp5_ick = { | 1892 | static struct clk mcbsp5_ick = { |
| 1897 | .name = "mcbsp_ick", | 1893 | .name = "mcbsp_ick", |
| 1894 | .ops = &clkops_omap2_dflt_wait, | ||
| 1898 | .id = 5, | 1895 | .id = 5, |
| 1899 | .parent = &l4_ck, | 1896 | .parent = &l4_ck, |
| 1900 | .flags = CLOCK_IN_OMAP243X, | ||
| 1901 | .clkdm_name = "core_l4_clkdm", | 1897 | .clkdm_name = "core_l4_clkdm", |
| 1902 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1898 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1903 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, | 1899 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, |
| @@ -1906,9 +1902,9 @@ static struct clk mcbsp5_ick = { | |||
| 1906 | 1902 | ||
| 1907 | static struct clk mcbsp5_fck = { | 1903 | static struct clk mcbsp5_fck = { |
| 1908 | .name = "mcbsp_fck", | 1904 | .name = "mcbsp_fck", |
| 1905 | .ops = &clkops_omap2_dflt_wait, | ||
| 1909 | .id = 5, | 1906 | .id = 5, |
| 1910 | .parent = &func_96m_ck, | 1907 | .parent = &func_96m_ck, |
| 1911 | .flags = CLOCK_IN_OMAP243X, | ||
| 1912 | .clkdm_name = "core_l4_clkdm", | 1908 | .clkdm_name = "core_l4_clkdm", |
| 1913 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1909 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1914 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, | 1910 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, |
| @@ -1917,10 +1913,10 @@ static struct clk mcbsp5_fck = { | |||
| 1917 | 1913 | ||
| 1918 | static struct clk mcspi1_ick = { | 1914 | static struct clk mcspi1_ick = { |
| 1919 | .name = "mcspi_ick", | 1915 | .name = "mcspi_ick", |
| 1916 | .ops = &clkops_omap2_dflt_wait, | ||
| 1920 | .id = 1, | 1917 | .id = 1, |
| 1921 | .parent = &l4_ck, | 1918 | .parent = &l4_ck, |
| 1922 | .clkdm_name = "core_l4_clkdm", | 1919 | .clkdm_name = "core_l4_clkdm", |
| 1923 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1924 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1920 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1925 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | 1921 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| 1926 | .recalc = &followparent_recalc, | 1922 | .recalc = &followparent_recalc, |
| @@ -1928,9 +1924,9 @@ static struct clk mcspi1_ick = { | |||
| 1928 | 1924 | ||
| 1929 | static struct clk mcspi1_fck = { | 1925 | static struct clk mcspi1_fck = { |
| 1930 | .name = "mcspi_fck", | 1926 | .name = "mcspi_fck", |
| 1927 | .ops = &clkops_omap2_dflt_wait, | ||
| 1931 | .id = 1, | 1928 | .id = 1, |
| 1932 | .parent = &func_48m_ck, | 1929 | .parent = &func_48m_ck, |
| 1933 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1934 | .clkdm_name = "core_l4_clkdm", | 1930 | .clkdm_name = "core_l4_clkdm", |
| 1935 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1931 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1936 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | 1932 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
| @@ -1939,9 +1935,9 @@ static struct clk mcspi1_fck = { | |||
| 1939 | 1935 | ||
| 1940 | static struct clk mcspi2_ick = { | 1936 | static struct clk mcspi2_ick = { |
| 1941 | .name = "mcspi_ick", | 1937 | .name = "mcspi_ick", |
| 1938 | .ops = &clkops_omap2_dflt_wait, | ||
| 1942 | .id = 2, | 1939 | .id = 2, |
| 1943 | .parent = &l4_ck, | 1940 | .parent = &l4_ck, |
| 1944 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1945 | .clkdm_name = "core_l4_clkdm", | 1941 | .clkdm_name = "core_l4_clkdm", |
| 1946 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1942 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1947 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | 1943 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| @@ -1950,9 +1946,9 @@ static struct clk mcspi2_ick = { | |||
| 1950 | 1946 | ||
| 1951 | static struct clk mcspi2_fck = { | 1947 | static struct clk mcspi2_fck = { |
| 1952 | .name = "mcspi_fck", | 1948 | .name = "mcspi_fck", |
| 1949 | .ops = &clkops_omap2_dflt_wait, | ||
| 1953 | .id = 2, | 1950 | .id = 2, |
| 1954 | .parent = &func_48m_ck, | 1951 | .parent = &func_48m_ck, |
| 1955 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1956 | .clkdm_name = "core_l4_clkdm", | 1952 | .clkdm_name = "core_l4_clkdm", |
| 1957 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1953 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1958 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | 1954 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
| @@ -1961,9 +1957,9 @@ static struct clk mcspi2_fck = { | |||
| 1961 | 1957 | ||
| 1962 | static struct clk mcspi3_ick = { | 1958 | static struct clk mcspi3_ick = { |
| 1963 | .name = "mcspi_ick", | 1959 | .name = "mcspi_ick", |
| 1960 | .ops = &clkops_omap2_dflt_wait, | ||
| 1964 | .id = 3, | 1961 | .id = 3, |
| 1965 | .parent = &l4_ck, | 1962 | .parent = &l4_ck, |
| 1966 | .flags = CLOCK_IN_OMAP243X, | ||
| 1967 | .clkdm_name = "core_l4_clkdm", | 1963 | .clkdm_name = "core_l4_clkdm", |
| 1968 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1964 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1969 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, | 1965 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, |
| @@ -1972,9 +1968,9 @@ static struct clk mcspi3_ick = { | |||
| 1972 | 1968 | ||
| 1973 | static struct clk mcspi3_fck = { | 1969 | static struct clk mcspi3_fck = { |
| 1974 | .name = "mcspi_fck", | 1970 | .name = "mcspi_fck", |
| 1971 | .ops = &clkops_omap2_dflt_wait, | ||
| 1975 | .id = 3, | 1972 | .id = 3, |
| 1976 | .parent = &func_48m_ck, | 1973 | .parent = &func_48m_ck, |
| 1977 | .flags = CLOCK_IN_OMAP243X, | ||
| 1978 | .clkdm_name = "core_l4_clkdm", | 1974 | .clkdm_name = "core_l4_clkdm", |
| 1979 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1975 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 1980 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, | 1976 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, |
| @@ -1983,8 +1979,8 @@ static struct clk mcspi3_fck = { | |||
| 1983 | 1979 | ||
| 1984 | static struct clk uart1_ick = { | 1980 | static struct clk uart1_ick = { |
| 1985 | .name = "uart1_ick", | 1981 | .name = "uart1_ick", |
| 1982 | .ops = &clkops_omap2_dflt_wait, | ||
| 1986 | .parent = &l4_ck, | 1983 | .parent = &l4_ck, |
| 1987 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1988 | .clkdm_name = "core_l4_clkdm", | 1984 | .clkdm_name = "core_l4_clkdm", |
| 1989 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1985 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1990 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | 1986 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, |
| @@ -1993,8 +1989,8 @@ static struct clk uart1_ick = { | |||
| 1993 | 1989 | ||
| 1994 | static struct clk uart1_fck = { | 1990 | static struct clk uart1_fck = { |
| 1995 | .name = "uart1_fck", | 1991 | .name = "uart1_fck", |
| 1992 | .ops = &clkops_omap2_dflt_wait, | ||
| 1996 | .parent = &func_48m_ck, | 1993 | .parent = &func_48m_ck, |
| 1997 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 1998 | .clkdm_name = "core_l4_clkdm", | 1994 | .clkdm_name = "core_l4_clkdm", |
| 1999 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1995 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2000 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | 1996 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, |
| @@ -2003,8 +1999,8 @@ static struct clk uart1_fck = { | |||
| 2003 | 1999 | ||
| 2004 | static struct clk uart2_ick = { | 2000 | static struct clk uart2_ick = { |
| 2005 | .name = "uart2_ick", | 2001 | .name = "uart2_ick", |
| 2002 | .ops = &clkops_omap2_dflt_wait, | ||
| 2006 | .parent = &l4_ck, | 2003 | .parent = &l4_ck, |
| 2007 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2008 | .clkdm_name = "core_l4_clkdm", | 2004 | .clkdm_name = "core_l4_clkdm", |
| 2009 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2005 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2010 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | 2006 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, |
| @@ -2013,8 +2009,8 @@ static struct clk uart2_ick = { | |||
| 2013 | 2009 | ||
| 2014 | static struct clk uart2_fck = { | 2010 | static struct clk uart2_fck = { |
| 2015 | .name = "uart2_fck", | 2011 | .name = "uart2_fck", |
| 2012 | .ops = &clkops_omap2_dflt_wait, | ||
| 2016 | .parent = &func_48m_ck, | 2013 | .parent = &func_48m_ck, |
| 2017 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2018 | .clkdm_name = "core_l4_clkdm", | 2014 | .clkdm_name = "core_l4_clkdm", |
| 2019 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2015 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2020 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | 2016 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, |
| @@ -2023,8 +2019,8 @@ static struct clk uart2_fck = { | |||
| 2023 | 2019 | ||
| 2024 | static struct clk uart3_ick = { | 2020 | static struct clk uart3_ick = { |
| 2025 | .name = "uart3_ick", | 2021 | .name = "uart3_ick", |
| 2022 | .ops = &clkops_omap2_dflt_wait, | ||
| 2026 | .parent = &l4_ck, | 2023 | .parent = &l4_ck, |
| 2027 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2028 | .clkdm_name = "core_l4_clkdm", | 2024 | .clkdm_name = "core_l4_clkdm", |
| 2029 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2025 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2030 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | 2026 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, |
| @@ -2033,8 +2029,8 @@ static struct clk uart3_ick = { | |||
| 2033 | 2029 | ||
| 2034 | static struct clk uart3_fck = { | 2030 | static struct clk uart3_fck = { |
| 2035 | .name = "uart3_fck", | 2031 | .name = "uart3_fck", |
| 2032 | .ops = &clkops_omap2_dflt_wait, | ||
| 2036 | .parent = &func_48m_ck, | 2033 | .parent = &func_48m_ck, |
| 2037 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2038 | .clkdm_name = "core_l4_clkdm", | 2034 | .clkdm_name = "core_l4_clkdm", |
| 2039 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2035 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2040 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | 2036 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, |
| @@ -2043,8 +2039,8 @@ static struct clk uart3_fck = { | |||
| 2043 | 2039 | ||
| 2044 | static struct clk gpios_ick = { | 2040 | static struct clk gpios_ick = { |
| 2045 | .name = "gpios_ick", | 2041 | .name = "gpios_ick", |
| 2042 | .ops = &clkops_omap2_dflt_wait, | ||
| 2046 | .parent = &l4_ck, | 2043 | .parent = &l4_ck, |
| 2047 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2048 | .clkdm_name = "core_l4_clkdm", | 2044 | .clkdm_name = "core_l4_clkdm", |
| 2049 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2045 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2050 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | 2046 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| @@ -2053,8 +2049,8 @@ static struct clk gpios_ick = { | |||
| 2053 | 2049 | ||
| 2054 | static struct clk gpios_fck = { | 2050 | static struct clk gpios_fck = { |
| 2055 | .name = "gpios_fck", | 2051 | .name = "gpios_fck", |
| 2052 | .ops = &clkops_omap2_dflt_wait, | ||
| 2056 | .parent = &func_32k_ck, | 2053 | .parent = &func_32k_ck, |
| 2057 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2058 | .clkdm_name = "wkup_clkdm", | 2054 | .clkdm_name = "wkup_clkdm", |
| 2059 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2055 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2060 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | 2056 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, |
| @@ -2063,8 +2059,8 @@ static struct clk gpios_fck = { | |||
| 2063 | 2059 | ||
| 2064 | static struct clk mpu_wdt_ick = { | 2060 | static struct clk mpu_wdt_ick = { |
| 2065 | .name = "mpu_wdt_ick", | 2061 | .name = "mpu_wdt_ick", |
| 2062 | .ops = &clkops_omap2_dflt_wait, | ||
| 2066 | .parent = &l4_ck, | 2063 | .parent = &l4_ck, |
| 2067 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2068 | .clkdm_name = "core_l4_clkdm", | 2064 | .clkdm_name = "core_l4_clkdm", |
| 2069 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2065 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2070 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | 2066 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| @@ -2073,8 +2069,8 @@ static struct clk mpu_wdt_ick = { | |||
| 2073 | 2069 | ||
| 2074 | static struct clk mpu_wdt_fck = { | 2070 | static struct clk mpu_wdt_fck = { |
| 2075 | .name = "mpu_wdt_fck", | 2071 | .name = "mpu_wdt_fck", |
| 2072 | .ops = &clkops_omap2_dflt_wait, | ||
| 2076 | .parent = &func_32k_ck, | 2073 | .parent = &func_32k_ck, |
| 2077 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2078 | .clkdm_name = "wkup_clkdm", | 2074 | .clkdm_name = "wkup_clkdm", |
| 2079 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2075 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2080 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | 2076 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
| @@ -2083,9 +2079,9 @@ static struct clk mpu_wdt_fck = { | |||
| 2083 | 2079 | ||
| 2084 | static struct clk sync_32k_ick = { | 2080 | static struct clk sync_32k_ick = { |
| 2085 | .name = "sync_32k_ick", | 2081 | .name = "sync_32k_ick", |
| 2082 | .ops = &clkops_omap2_dflt_wait, | ||
| 2086 | .parent = &l4_ck, | 2083 | .parent = &l4_ck, |
| 2087 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 2084 | .flags = ENABLE_ON_INIT, |
| 2088 | ENABLE_ON_INIT, | ||
| 2089 | .clkdm_name = "core_l4_clkdm", | 2085 | .clkdm_name = "core_l4_clkdm", |
| 2090 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2086 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2091 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, | 2087 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, |
| @@ -2094,8 +2090,8 @@ static struct clk sync_32k_ick = { | |||
| 2094 | 2090 | ||
| 2095 | static struct clk wdt1_ick = { | 2091 | static struct clk wdt1_ick = { |
| 2096 | .name = "wdt1_ick", | 2092 | .name = "wdt1_ick", |
| 2093 | .ops = &clkops_omap2_dflt_wait, | ||
| 2097 | .parent = &l4_ck, | 2094 | .parent = &l4_ck, |
| 2098 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2099 | .clkdm_name = "core_l4_clkdm", | 2095 | .clkdm_name = "core_l4_clkdm", |
| 2100 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2096 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2101 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, | 2097 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, |
| @@ -2104,9 +2100,9 @@ static struct clk wdt1_ick = { | |||
| 2104 | 2100 | ||
| 2105 | static struct clk omapctrl_ick = { | 2101 | static struct clk omapctrl_ick = { |
| 2106 | .name = "omapctrl_ick", | 2102 | .name = "omapctrl_ick", |
| 2103 | .ops = &clkops_omap2_dflt_wait, | ||
| 2107 | .parent = &l4_ck, | 2104 | .parent = &l4_ck, |
| 2108 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 2105 | .flags = ENABLE_ON_INIT, |
| 2109 | ENABLE_ON_INIT, | ||
| 2110 | .clkdm_name = "core_l4_clkdm", | 2106 | .clkdm_name = "core_l4_clkdm", |
| 2111 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2107 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2112 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, | 2108 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, |
| @@ -2115,8 +2111,8 @@ static struct clk omapctrl_ick = { | |||
| 2115 | 2111 | ||
| 2116 | static struct clk icr_ick = { | 2112 | static struct clk icr_ick = { |
| 2117 | .name = "icr_ick", | 2113 | .name = "icr_ick", |
| 2114 | .ops = &clkops_omap2_dflt_wait, | ||
| 2118 | .parent = &l4_ck, | 2115 | .parent = &l4_ck, |
| 2119 | .flags = CLOCK_IN_OMAP243X, | ||
| 2120 | .clkdm_name = "core_l4_clkdm", | 2116 | .clkdm_name = "core_l4_clkdm", |
| 2121 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2117 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2122 | .enable_bit = OMAP2430_EN_ICR_SHIFT, | 2118 | .enable_bit = OMAP2430_EN_ICR_SHIFT, |
| @@ -2125,8 +2121,8 @@ static struct clk icr_ick = { | |||
| 2125 | 2121 | ||
| 2126 | static struct clk cam_ick = { | 2122 | static struct clk cam_ick = { |
| 2127 | .name = "cam_ick", | 2123 | .name = "cam_ick", |
| 2124 | .ops = &clkops_omap2_dflt, | ||
| 2128 | .parent = &l4_ck, | 2125 | .parent = &l4_ck, |
| 2129 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2130 | .clkdm_name = "core_l4_clkdm", | 2126 | .clkdm_name = "core_l4_clkdm", |
| 2131 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2127 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2132 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | 2128 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, |
| @@ -2140,8 +2136,8 @@ static struct clk cam_ick = { | |||
| 2140 | */ | 2136 | */ |
| 2141 | static struct clk cam_fck = { | 2137 | static struct clk cam_fck = { |
| 2142 | .name = "cam_fck", | 2138 | .name = "cam_fck", |
| 2139 | .ops = &clkops_omap2_dflt, | ||
| 2143 | .parent = &func_96m_ck, | 2140 | .parent = &func_96m_ck, |
| 2144 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2145 | .clkdm_name = "core_l3_clkdm", | 2141 | .clkdm_name = "core_l3_clkdm", |
| 2146 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2142 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2147 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | 2143 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, |
| @@ -2150,8 +2146,8 @@ static struct clk cam_fck = { | |||
| 2150 | 2146 | ||
| 2151 | static struct clk mailboxes_ick = { | 2147 | static struct clk mailboxes_ick = { |
| 2152 | .name = "mailboxes_ick", | 2148 | .name = "mailboxes_ick", |
| 2149 | .ops = &clkops_omap2_dflt_wait, | ||
| 2153 | .parent = &l4_ck, | 2150 | .parent = &l4_ck, |
| 2154 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2155 | .clkdm_name = "core_l4_clkdm", | 2151 | .clkdm_name = "core_l4_clkdm", |
| 2156 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2152 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2157 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | 2153 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, |
| @@ -2160,8 +2156,8 @@ static struct clk mailboxes_ick = { | |||
| 2160 | 2156 | ||
| 2161 | static struct clk wdt4_ick = { | 2157 | static struct clk wdt4_ick = { |
| 2162 | .name = "wdt4_ick", | 2158 | .name = "wdt4_ick", |
| 2159 | .ops = &clkops_omap2_dflt_wait, | ||
| 2163 | .parent = &l4_ck, | 2160 | .parent = &l4_ck, |
| 2164 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2165 | .clkdm_name = "core_l4_clkdm", | 2161 | .clkdm_name = "core_l4_clkdm", |
| 2166 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2162 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2167 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | 2163 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, |
| @@ -2170,8 +2166,8 @@ static struct clk wdt4_ick = { | |||
| 2170 | 2166 | ||
| 2171 | static struct clk wdt4_fck = { | 2167 | static struct clk wdt4_fck = { |
| 2172 | .name = "wdt4_fck", | 2168 | .name = "wdt4_fck", |
| 2169 | .ops = &clkops_omap2_dflt_wait, | ||
| 2173 | .parent = &func_32k_ck, | 2170 | .parent = &func_32k_ck, |
| 2174 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2175 | .clkdm_name = "core_l4_clkdm", | 2171 | .clkdm_name = "core_l4_clkdm", |
| 2176 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2172 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2177 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | 2173 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, |
| @@ -2180,8 +2176,8 @@ static struct clk wdt4_fck = { | |||
| 2180 | 2176 | ||
| 2181 | static struct clk wdt3_ick = { | 2177 | static struct clk wdt3_ick = { |
| 2182 | .name = "wdt3_ick", | 2178 | .name = "wdt3_ick", |
| 2179 | .ops = &clkops_omap2_dflt_wait, | ||
| 2183 | .parent = &l4_ck, | 2180 | .parent = &l4_ck, |
| 2184 | .flags = CLOCK_IN_OMAP242X, | ||
| 2185 | .clkdm_name = "core_l4_clkdm", | 2181 | .clkdm_name = "core_l4_clkdm", |
| 2186 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2182 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2187 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | 2183 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, |
| @@ -2190,8 +2186,8 @@ static struct clk wdt3_ick = { | |||
| 2190 | 2186 | ||
| 2191 | static struct clk wdt3_fck = { | 2187 | static struct clk wdt3_fck = { |
| 2192 | .name = "wdt3_fck", | 2188 | .name = "wdt3_fck", |
| 2189 | .ops = &clkops_omap2_dflt_wait, | ||
| 2193 | .parent = &func_32k_ck, | 2190 | .parent = &func_32k_ck, |
| 2194 | .flags = CLOCK_IN_OMAP242X, | ||
| 2195 | .clkdm_name = "core_l4_clkdm", | 2191 | .clkdm_name = "core_l4_clkdm", |
| 2196 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2192 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2197 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | 2193 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, |
| @@ -2200,8 +2196,8 @@ static struct clk wdt3_fck = { | |||
| 2200 | 2196 | ||
| 2201 | static struct clk mspro_ick = { | 2197 | static struct clk mspro_ick = { |
| 2202 | .name = "mspro_ick", | 2198 | .name = "mspro_ick", |
| 2199 | .ops = &clkops_omap2_dflt_wait, | ||
| 2203 | .parent = &l4_ck, | 2200 | .parent = &l4_ck, |
| 2204 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2205 | .clkdm_name = "core_l4_clkdm", | 2201 | .clkdm_name = "core_l4_clkdm", |
| 2206 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2202 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2207 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | 2203 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, |
| @@ -2210,8 +2206,8 @@ static struct clk mspro_ick = { | |||
| 2210 | 2206 | ||
| 2211 | static struct clk mspro_fck = { | 2207 | static struct clk mspro_fck = { |
| 2212 | .name = "mspro_fck", | 2208 | .name = "mspro_fck", |
| 2209 | .ops = &clkops_omap2_dflt_wait, | ||
| 2213 | .parent = &func_96m_ck, | 2210 | .parent = &func_96m_ck, |
| 2214 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2215 | .clkdm_name = "core_l4_clkdm", | 2211 | .clkdm_name = "core_l4_clkdm", |
| 2216 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2212 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2217 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | 2213 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, |
| @@ -2220,8 +2216,8 @@ static struct clk mspro_fck = { | |||
| 2220 | 2216 | ||
| 2221 | static struct clk mmc_ick = { | 2217 | static struct clk mmc_ick = { |
| 2222 | .name = "mmc_ick", | 2218 | .name = "mmc_ick", |
| 2219 | .ops = &clkops_omap2_dflt_wait, | ||
| 2223 | .parent = &l4_ck, | 2220 | .parent = &l4_ck, |
| 2224 | .flags = CLOCK_IN_OMAP242X, | ||
| 2225 | .clkdm_name = "core_l4_clkdm", | 2221 | .clkdm_name = "core_l4_clkdm", |
| 2226 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2222 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2227 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | 2223 | .enable_bit = OMAP2420_EN_MMC_SHIFT, |
| @@ -2230,8 +2226,8 @@ static struct clk mmc_ick = { | |||
| 2230 | 2226 | ||
| 2231 | static struct clk mmc_fck = { | 2227 | static struct clk mmc_fck = { |
| 2232 | .name = "mmc_fck", | 2228 | .name = "mmc_fck", |
| 2229 | .ops = &clkops_omap2_dflt_wait, | ||
| 2233 | .parent = &func_96m_ck, | 2230 | .parent = &func_96m_ck, |
| 2234 | .flags = CLOCK_IN_OMAP242X, | ||
| 2235 | .clkdm_name = "core_l4_clkdm", | 2231 | .clkdm_name = "core_l4_clkdm", |
| 2236 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2232 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2237 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | 2233 | .enable_bit = OMAP2420_EN_MMC_SHIFT, |
| @@ -2240,8 +2236,8 @@ static struct clk mmc_fck = { | |||
| 2240 | 2236 | ||
| 2241 | static struct clk fac_ick = { | 2237 | static struct clk fac_ick = { |
| 2242 | .name = "fac_ick", | 2238 | .name = "fac_ick", |
| 2239 | .ops = &clkops_omap2_dflt_wait, | ||
| 2243 | .parent = &l4_ck, | 2240 | .parent = &l4_ck, |
| 2244 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2245 | .clkdm_name = "core_l4_clkdm", | 2241 | .clkdm_name = "core_l4_clkdm", |
| 2246 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2242 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2247 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | 2243 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, |
| @@ -2250,8 +2246,8 @@ static struct clk fac_ick = { | |||
| 2250 | 2246 | ||
| 2251 | static struct clk fac_fck = { | 2247 | static struct clk fac_fck = { |
| 2252 | .name = "fac_fck", | 2248 | .name = "fac_fck", |
| 2249 | .ops = &clkops_omap2_dflt_wait, | ||
| 2253 | .parent = &func_12m_ck, | 2250 | .parent = &func_12m_ck, |
| 2254 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2255 | .clkdm_name = "core_l4_clkdm", | 2251 | .clkdm_name = "core_l4_clkdm", |
| 2256 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2252 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2257 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | 2253 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, |
| @@ -2260,8 +2256,8 @@ static struct clk fac_fck = { | |||
| 2260 | 2256 | ||
| 2261 | static struct clk eac_ick = { | 2257 | static struct clk eac_ick = { |
| 2262 | .name = "eac_ick", | 2258 | .name = "eac_ick", |
| 2259 | .ops = &clkops_omap2_dflt_wait, | ||
| 2263 | .parent = &l4_ck, | 2260 | .parent = &l4_ck, |
| 2264 | .flags = CLOCK_IN_OMAP242X, | ||
| 2265 | .clkdm_name = "core_l4_clkdm", | 2261 | .clkdm_name = "core_l4_clkdm", |
| 2266 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2262 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2267 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | 2263 | .enable_bit = OMAP2420_EN_EAC_SHIFT, |
| @@ -2270,8 +2266,8 @@ static struct clk eac_ick = { | |||
| 2270 | 2266 | ||
| 2271 | static struct clk eac_fck = { | 2267 | static struct clk eac_fck = { |
| 2272 | .name = "eac_fck", | 2268 | .name = "eac_fck", |
| 2269 | .ops = &clkops_omap2_dflt_wait, | ||
| 2273 | .parent = &func_96m_ck, | 2270 | .parent = &func_96m_ck, |
| 2274 | .flags = CLOCK_IN_OMAP242X, | ||
| 2275 | .clkdm_name = "core_l4_clkdm", | 2271 | .clkdm_name = "core_l4_clkdm", |
| 2276 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2272 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2277 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | 2273 | .enable_bit = OMAP2420_EN_EAC_SHIFT, |
| @@ -2280,8 +2276,8 @@ static struct clk eac_fck = { | |||
| 2280 | 2276 | ||
| 2281 | static struct clk hdq_ick = { | 2277 | static struct clk hdq_ick = { |
| 2282 | .name = "hdq_ick", | 2278 | .name = "hdq_ick", |
| 2279 | .ops = &clkops_omap2_dflt_wait, | ||
| 2283 | .parent = &l4_ck, | 2280 | .parent = &l4_ck, |
| 2284 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2285 | .clkdm_name = "core_l4_clkdm", | 2281 | .clkdm_name = "core_l4_clkdm", |
| 2286 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2282 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2287 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | 2283 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, |
| @@ -2290,8 +2286,8 @@ static struct clk hdq_ick = { | |||
| 2290 | 2286 | ||
| 2291 | static struct clk hdq_fck = { | 2287 | static struct clk hdq_fck = { |
| 2292 | .name = "hdq_fck", | 2288 | .name = "hdq_fck", |
| 2289 | .ops = &clkops_omap2_dflt_wait, | ||
| 2293 | .parent = &func_12m_ck, | 2290 | .parent = &func_12m_ck, |
| 2294 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2295 | .clkdm_name = "core_l4_clkdm", | 2291 | .clkdm_name = "core_l4_clkdm", |
| 2296 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2292 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2297 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | 2293 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, |
| @@ -2300,9 +2296,9 @@ static struct clk hdq_fck = { | |||
| 2300 | 2296 | ||
| 2301 | static struct clk i2c2_ick = { | 2297 | static struct clk i2c2_ick = { |
| 2302 | .name = "i2c_ick", | 2298 | .name = "i2c_ick", |
| 2299 | .ops = &clkops_omap2_dflt_wait, | ||
| 2303 | .id = 2, | 2300 | .id = 2, |
| 2304 | .parent = &l4_ck, | 2301 | .parent = &l4_ck, |
| 2305 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2306 | .clkdm_name = "core_l4_clkdm", | 2302 | .clkdm_name = "core_l4_clkdm", |
| 2307 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2303 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2308 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | 2304 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, |
| @@ -2311,9 +2307,9 @@ static struct clk i2c2_ick = { | |||
| 2311 | 2307 | ||
| 2312 | static struct clk i2c2_fck = { | 2308 | static struct clk i2c2_fck = { |
| 2313 | .name = "i2c_fck", | 2309 | .name = "i2c_fck", |
| 2310 | .ops = &clkops_omap2_dflt_wait, | ||
| 2314 | .id = 2, | 2311 | .id = 2, |
| 2315 | .parent = &func_12m_ck, | 2312 | .parent = &func_12m_ck, |
| 2316 | .flags = CLOCK_IN_OMAP242X, | ||
| 2317 | .clkdm_name = "core_l4_clkdm", | 2313 | .clkdm_name = "core_l4_clkdm", |
| 2318 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2314 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2319 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | 2315 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, |
| @@ -2322,9 +2318,9 @@ static struct clk i2c2_fck = { | |||
| 2322 | 2318 | ||
| 2323 | static struct clk i2chs2_fck = { | 2319 | static struct clk i2chs2_fck = { |
| 2324 | .name = "i2c_fck", | 2320 | .name = "i2c_fck", |
| 2321 | .ops = &clkops_omap2_dflt_wait, | ||
| 2325 | .id = 2, | 2322 | .id = 2, |
| 2326 | .parent = &func_96m_ck, | 2323 | .parent = &func_96m_ck, |
| 2327 | .flags = CLOCK_IN_OMAP243X, | ||
| 2328 | .clkdm_name = "core_l4_clkdm", | 2324 | .clkdm_name = "core_l4_clkdm", |
| 2329 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2325 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2330 | .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, | 2326 | .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, |
| @@ -2333,9 +2329,9 @@ static struct clk i2chs2_fck = { | |||
| 2333 | 2329 | ||
| 2334 | static struct clk i2c1_ick = { | 2330 | static struct clk i2c1_ick = { |
| 2335 | .name = "i2c_ick", | 2331 | .name = "i2c_ick", |
| 2332 | .ops = &clkops_omap2_dflt_wait, | ||
| 2336 | .id = 1, | 2333 | .id = 1, |
| 2337 | .parent = &l4_ck, | 2334 | .parent = &l4_ck, |
| 2338 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2339 | .clkdm_name = "core_l4_clkdm", | 2335 | .clkdm_name = "core_l4_clkdm", |
| 2340 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2336 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2341 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | 2337 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, |
| @@ -2344,9 +2340,9 @@ static struct clk i2c1_ick = { | |||
| 2344 | 2340 | ||
| 2345 | static struct clk i2c1_fck = { | 2341 | static struct clk i2c1_fck = { |
| 2346 | .name = "i2c_fck", | 2342 | .name = "i2c_fck", |
| 2343 | .ops = &clkops_omap2_dflt_wait, | ||
| 2347 | .id = 1, | 2344 | .id = 1, |
| 2348 | .parent = &func_12m_ck, | 2345 | .parent = &func_12m_ck, |
| 2349 | .flags = CLOCK_IN_OMAP242X, | ||
| 2350 | .clkdm_name = "core_l4_clkdm", | 2346 | .clkdm_name = "core_l4_clkdm", |
| 2351 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2347 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2352 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | 2348 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, |
| @@ -2355,9 +2351,9 @@ static struct clk i2c1_fck = { | |||
| 2355 | 2351 | ||
| 2356 | static struct clk i2chs1_fck = { | 2352 | static struct clk i2chs1_fck = { |
| 2357 | .name = "i2c_fck", | 2353 | .name = "i2c_fck", |
| 2354 | .ops = &clkops_omap2_dflt_wait, | ||
| 2358 | .id = 1, | 2355 | .id = 1, |
| 2359 | .parent = &func_96m_ck, | 2356 | .parent = &func_96m_ck, |
| 2360 | .flags = CLOCK_IN_OMAP243X, | ||
| 2361 | .clkdm_name = "core_l4_clkdm", | 2357 | .clkdm_name = "core_l4_clkdm", |
| 2362 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2358 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2363 | .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, | 2359 | .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, |
| @@ -2366,33 +2362,33 @@ static struct clk i2chs1_fck = { | |||
| 2366 | 2362 | ||
| 2367 | static struct clk gpmc_fck = { | 2363 | static struct clk gpmc_fck = { |
| 2368 | .name = "gpmc_fck", | 2364 | .name = "gpmc_fck", |
| 2365 | .ops = &clkops_null, /* RMK: missing? */ | ||
| 2369 | .parent = &core_l3_ck, | 2366 | .parent = &core_l3_ck, |
| 2370 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 2367 | .flags = ENABLE_ON_INIT, |
| 2371 | ENABLE_ON_INIT, | ||
| 2372 | .clkdm_name = "core_l3_clkdm", | 2368 | .clkdm_name = "core_l3_clkdm", |
| 2373 | .recalc = &followparent_recalc, | 2369 | .recalc = &followparent_recalc, |
| 2374 | }; | 2370 | }; |
| 2375 | 2371 | ||
| 2376 | static struct clk sdma_fck = { | 2372 | static struct clk sdma_fck = { |
| 2377 | .name = "sdma_fck", | 2373 | .name = "sdma_fck", |
| 2374 | .ops = &clkops_null, /* RMK: missing? */ | ||
| 2378 | .parent = &core_l3_ck, | 2375 | .parent = &core_l3_ck, |
| 2379 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2380 | .clkdm_name = "core_l3_clkdm", | 2376 | .clkdm_name = "core_l3_clkdm", |
| 2381 | .recalc = &followparent_recalc, | 2377 | .recalc = &followparent_recalc, |
| 2382 | }; | 2378 | }; |
| 2383 | 2379 | ||
| 2384 | static struct clk sdma_ick = { | 2380 | static struct clk sdma_ick = { |
| 2385 | .name = "sdma_ick", | 2381 | .name = "sdma_ick", |
| 2382 | .ops = &clkops_null, /* RMK: missing? */ | ||
| 2386 | .parent = &l4_ck, | 2383 | .parent = &l4_ck, |
| 2387 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
| 2388 | .clkdm_name = "core_l3_clkdm", | 2384 | .clkdm_name = "core_l3_clkdm", |
| 2389 | .recalc = &followparent_recalc, | 2385 | .recalc = &followparent_recalc, |
| 2390 | }; | 2386 | }; |
| 2391 | 2387 | ||
| 2392 | static struct clk vlynq_ick = { | 2388 | static struct clk vlynq_ick = { |
| 2393 | .name = "vlynq_ick", | 2389 | .name = "vlynq_ick", |
| 2390 | .ops = &clkops_omap2_dflt_wait, | ||
| 2394 | .parent = &core_l3_ck, | 2391 | .parent = &core_l3_ck, |
| 2395 | .flags = CLOCK_IN_OMAP242X, | ||
| 2396 | .clkdm_name = "core_l3_clkdm", | 2392 | .clkdm_name = "core_l3_clkdm", |
| 2397 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2393 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 2398 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | 2394 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, |
| @@ -2426,8 +2422,9 @@ static const struct clksel vlynq_fck_clksel[] = { | |||
| 2426 | 2422 | ||
| 2427 | static struct clk vlynq_fck = { | 2423 | static struct clk vlynq_fck = { |
| 2428 | .name = "vlynq_fck", | 2424 | .name = "vlynq_fck", |
| 2425 | .ops = &clkops_omap2_dflt_wait, | ||
| 2429 | .parent = &func_96m_ck, | 2426 | .parent = &func_96m_ck, |
| 2430 | .flags = CLOCK_IN_OMAP242X | DELAYED_APP, | 2427 | .flags = DELAYED_APP, |
| 2431 | .clkdm_name = "core_l3_clkdm", | 2428 | .clkdm_name = "core_l3_clkdm", |
| 2432 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2429 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 2433 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | 2430 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, |
| @@ -2442,8 +2439,9 @@ static struct clk vlynq_fck = { | |||
| 2442 | 2439 | ||
| 2443 | static struct clk sdrc_ick = { | 2440 | static struct clk sdrc_ick = { |
| 2444 | .name = "sdrc_ick", | 2441 | .name = "sdrc_ick", |
| 2442 | .ops = &clkops_omap2_dflt_wait, | ||
| 2445 | .parent = &l4_ck, | 2443 | .parent = &l4_ck, |
| 2446 | .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, | 2444 | .flags = ENABLE_ON_INIT, |
| 2447 | .clkdm_name = "core_l4_clkdm", | 2445 | .clkdm_name = "core_l4_clkdm", |
| 2448 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | 2446 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
| 2449 | .enable_bit = OMAP2430_EN_SDRC_SHIFT, | 2447 | .enable_bit = OMAP2430_EN_SDRC_SHIFT, |
| @@ -2452,8 +2450,8 @@ static struct clk sdrc_ick = { | |||
| 2452 | 2450 | ||
| 2453 | static struct clk des_ick = { | 2451 | static struct clk des_ick = { |
| 2454 | .name = "des_ick", | 2452 | .name = "des_ick", |
| 2453 | .ops = &clkops_omap2_dflt_wait, | ||
| 2455 | .parent = &l4_ck, | 2454 | .parent = &l4_ck, |
| 2456 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2457 | .clkdm_name = "core_l4_clkdm", | 2455 | .clkdm_name = "core_l4_clkdm", |
| 2458 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | 2456 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 2459 | .enable_bit = OMAP24XX_EN_DES_SHIFT, | 2457 | .enable_bit = OMAP24XX_EN_DES_SHIFT, |
| @@ -2462,8 +2460,8 @@ static struct clk des_ick = { | |||
| 2462 | 2460 | ||
| 2463 | static struct clk sha_ick = { | 2461 | static struct clk sha_ick = { |
| 2464 | .name = "sha_ick", | 2462 | .name = "sha_ick", |
| 2463 | .ops = &clkops_omap2_dflt_wait, | ||
| 2465 | .parent = &l4_ck, | 2464 | .parent = &l4_ck, |
| 2466 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2467 | .clkdm_name = "core_l4_clkdm", | 2465 | .clkdm_name = "core_l4_clkdm", |
| 2468 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | 2466 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 2469 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, | 2467 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, |
| @@ -2472,8 +2470,8 @@ static struct clk sha_ick = { | |||
| 2472 | 2470 | ||
| 2473 | static struct clk rng_ick = { | 2471 | static struct clk rng_ick = { |
| 2474 | .name = "rng_ick", | 2472 | .name = "rng_ick", |
| 2473 | .ops = &clkops_omap2_dflt_wait, | ||
| 2475 | .parent = &l4_ck, | 2474 | .parent = &l4_ck, |
| 2476 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2477 | .clkdm_name = "core_l4_clkdm", | 2475 | .clkdm_name = "core_l4_clkdm", |
| 2478 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | 2476 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 2479 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, | 2477 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, |
| @@ -2482,8 +2480,8 @@ static struct clk rng_ick = { | |||
| 2482 | 2480 | ||
| 2483 | static struct clk aes_ick = { | 2481 | static struct clk aes_ick = { |
| 2484 | .name = "aes_ick", | 2482 | .name = "aes_ick", |
| 2483 | .ops = &clkops_omap2_dflt_wait, | ||
| 2485 | .parent = &l4_ck, | 2484 | .parent = &l4_ck, |
| 2486 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2487 | .clkdm_name = "core_l4_clkdm", | 2485 | .clkdm_name = "core_l4_clkdm", |
| 2488 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | 2486 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 2489 | .enable_bit = OMAP24XX_EN_AES_SHIFT, | 2487 | .enable_bit = OMAP24XX_EN_AES_SHIFT, |
| @@ -2492,8 +2490,8 @@ static struct clk aes_ick = { | |||
| 2492 | 2490 | ||
| 2493 | static struct clk pka_ick = { | 2491 | static struct clk pka_ick = { |
| 2494 | .name = "pka_ick", | 2492 | .name = "pka_ick", |
| 2493 | .ops = &clkops_omap2_dflt_wait, | ||
| 2495 | .parent = &l4_ck, | 2494 | .parent = &l4_ck, |
| 2496 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2497 | .clkdm_name = "core_l4_clkdm", | 2495 | .clkdm_name = "core_l4_clkdm", |
| 2498 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | 2496 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
| 2499 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, | 2497 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, |
| @@ -2502,8 +2500,8 @@ static struct clk pka_ick = { | |||
| 2502 | 2500 | ||
| 2503 | static struct clk usb_fck = { | 2501 | static struct clk usb_fck = { |
| 2504 | .name = "usb_fck", | 2502 | .name = "usb_fck", |
| 2503 | .ops = &clkops_omap2_dflt_wait, | ||
| 2505 | .parent = &func_48m_ck, | 2504 | .parent = &func_48m_ck, |
| 2506 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | ||
| 2507 | .clkdm_name = "core_l3_clkdm", | 2505 | .clkdm_name = "core_l3_clkdm", |
| 2508 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2506 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2509 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | 2507 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
| @@ -2512,8 +2510,8 @@ static struct clk usb_fck = { | |||
| 2512 | 2510 | ||
| 2513 | static struct clk usbhs_ick = { | 2511 | static struct clk usbhs_ick = { |
| 2514 | .name = "usbhs_ick", | 2512 | .name = "usbhs_ick", |
| 2513 | .ops = &clkops_omap2_dflt_wait, | ||
| 2515 | .parent = &core_l3_ck, | 2514 | .parent = &core_l3_ck, |
| 2516 | .flags = CLOCK_IN_OMAP243X, | ||
| 2517 | .clkdm_name = "core_l3_clkdm", | 2515 | .clkdm_name = "core_l3_clkdm", |
| 2518 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2516 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2519 | .enable_bit = OMAP2430_EN_USBHS_SHIFT, | 2517 | .enable_bit = OMAP2430_EN_USBHS_SHIFT, |
| @@ -2522,8 +2520,8 @@ static struct clk usbhs_ick = { | |||
| 2522 | 2520 | ||
| 2523 | static struct clk mmchs1_ick = { | 2521 | static struct clk mmchs1_ick = { |
| 2524 | .name = "mmchs_ick", | 2522 | .name = "mmchs_ick", |
| 2523 | .ops = &clkops_omap2_dflt_wait, | ||
| 2525 | .parent = &l4_ck, | 2524 | .parent = &l4_ck, |
| 2526 | .flags = CLOCK_IN_OMAP243X, | ||
| 2527 | .clkdm_name = "core_l4_clkdm", | 2525 | .clkdm_name = "core_l4_clkdm", |
| 2528 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2526 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2529 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | 2527 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, |
| @@ -2532,8 +2530,8 @@ static struct clk mmchs1_ick = { | |||
| 2532 | 2530 | ||
| 2533 | static struct clk mmchs1_fck = { | 2531 | static struct clk mmchs1_fck = { |
| 2534 | .name = "mmchs_fck", | 2532 | .name = "mmchs_fck", |
| 2533 | .ops = &clkops_omap2_dflt_wait, | ||
| 2535 | .parent = &func_96m_ck, | 2534 | .parent = &func_96m_ck, |
| 2536 | .flags = CLOCK_IN_OMAP243X, | ||
| 2537 | .clkdm_name = "core_l3_clkdm", | 2535 | .clkdm_name = "core_l3_clkdm", |
| 2538 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2536 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2539 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | 2537 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, |
| @@ -2542,9 +2540,9 @@ static struct clk mmchs1_fck = { | |||
| 2542 | 2540 | ||
| 2543 | static struct clk mmchs2_ick = { | 2541 | static struct clk mmchs2_ick = { |
| 2544 | .name = "mmchs_ick", | 2542 | .name = "mmchs_ick", |
| 2543 | .ops = &clkops_omap2_dflt_wait, | ||
| 2545 | .id = 1, | 2544 | .id = 1, |
| 2546 | .parent = &l4_ck, | 2545 | .parent = &l4_ck, |
| 2547 | .flags = CLOCK_IN_OMAP243X, | ||
| 2548 | .clkdm_name = "core_l4_clkdm", | 2546 | .clkdm_name = "core_l4_clkdm", |
| 2549 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2547 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2550 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | 2548 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, |
| @@ -2553,9 +2551,9 @@ static struct clk mmchs2_ick = { | |||
| 2553 | 2551 | ||
| 2554 | static struct clk mmchs2_fck = { | 2552 | static struct clk mmchs2_fck = { |
| 2555 | .name = "mmchs_fck", | 2553 | .name = "mmchs_fck", |
| 2554 | .ops = &clkops_omap2_dflt_wait, | ||
| 2556 | .id = 1, | 2555 | .id = 1, |
| 2557 | .parent = &func_96m_ck, | 2556 | .parent = &func_96m_ck, |
| 2558 | .flags = CLOCK_IN_OMAP243X, | ||
| 2559 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2557 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2560 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | 2558 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, |
| 2561 | .recalc = &followparent_recalc, | 2559 | .recalc = &followparent_recalc, |
| @@ -2563,8 +2561,8 @@ static struct clk mmchs2_fck = { | |||
| 2563 | 2561 | ||
| 2564 | static struct clk gpio5_ick = { | 2562 | static struct clk gpio5_ick = { |
| 2565 | .name = "gpio5_ick", | 2563 | .name = "gpio5_ick", |
| 2564 | .ops = &clkops_omap2_dflt_wait, | ||
| 2566 | .parent = &l4_ck, | 2565 | .parent = &l4_ck, |
| 2567 | .flags = CLOCK_IN_OMAP243X, | ||
| 2568 | .clkdm_name = "core_l4_clkdm", | 2566 | .clkdm_name = "core_l4_clkdm", |
| 2569 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2567 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2570 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, | 2568 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, |
| @@ -2573,8 +2571,8 @@ static struct clk gpio5_ick = { | |||
| 2573 | 2571 | ||
| 2574 | static struct clk gpio5_fck = { | 2572 | static struct clk gpio5_fck = { |
| 2575 | .name = "gpio5_fck", | 2573 | .name = "gpio5_fck", |
| 2574 | .ops = &clkops_omap2_dflt_wait, | ||
| 2576 | .parent = &func_32k_ck, | 2575 | .parent = &func_32k_ck, |
| 2577 | .flags = CLOCK_IN_OMAP243X, | ||
| 2578 | .clkdm_name = "core_l4_clkdm", | 2576 | .clkdm_name = "core_l4_clkdm", |
| 2579 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2577 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2580 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, | 2578 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, |
| @@ -2583,8 +2581,8 @@ static struct clk gpio5_fck = { | |||
| 2583 | 2581 | ||
| 2584 | static struct clk mdm_intc_ick = { | 2582 | static struct clk mdm_intc_ick = { |
| 2585 | .name = "mdm_intc_ick", | 2583 | .name = "mdm_intc_ick", |
| 2584 | .ops = &clkops_omap2_dflt_wait, | ||
| 2586 | .parent = &l4_ck, | 2585 | .parent = &l4_ck, |
| 2587 | .flags = CLOCK_IN_OMAP243X, | ||
| 2588 | .clkdm_name = "core_l4_clkdm", | 2586 | .clkdm_name = "core_l4_clkdm", |
| 2589 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2587 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2590 | .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, | 2588 | .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, |
| @@ -2593,8 +2591,8 @@ static struct clk mdm_intc_ick = { | |||
| 2593 | 2591 | ||
| 2594 | static struct clk mmchsdb1_fck = { | 2592 | static struct clk mmchsdb1_fck = { |
| 2595 | .name = "mmchsdb_fck", | 2593 | .name = "mmchsdb_fck", |
| 2594 | .ops = &clkops_omap2_dflt_wait, | ||
| 2596 | .parent = &func_32k_ck, | 2595 | .parent = &func_32k_ck, |
| 2597 | .flags = CLOCK_IN_OMAP243X, | ||
| 2598 | .clkdm_name = "core_l4_clkdm", | 2596 | .clkdm_name = "core_l4_clkdm", |
| 2599 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2597 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2600 | .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, | 2598 | .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, |
| @@ -2603,9 +2601,9 @@ static struct clk mmchsdb1_fck = { | |||
| 2603 | 2601 | ||
| 2604 | static struct clk mmchsdb2_fck = { | 2602 | static struct clk mmchsdb2_fck = { |
| 2605 | .name = "mmchsdb_fck", | 2603 | .name = "mmchsdb_fck", |
| 2604 | .ops = &clkops_omap2_dflt_wait, | ||
| 2606 | .id = 1, | 2605 | .id = 1, |
| 2607 | .parent = &func_32k_ck, | 2606 | .parent = &func_32k_ck, |
| 2608 | .flags = CLOCK_IN_OMAP243X, | ||
| 2609 | .clkdm_name = "core_l4_clkdm", | 2607 | .clkdm_name = "core_l4_clkdm", |
| 2610 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2608 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
| 2611 | .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, | 2609 | .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, |
| @@ -2628,166 +2626,13 @@ static struct clk mmchsdb2_fck = { | |||
| 2628 | */ | 2626 | */ |
| 2629 | static struct clk virt_prcm_set = { | 2627 | static struct clk virt_prcm_set = { |
| 2630 | .name = "virt_prcm_set", | 2628 | .name = "virt_prcm_set", |
| 2631 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 2629 | .ops = &clkops_null, |
| 2632 | VIRTUAL_CLOCK | ALWAYS_ENABLED | DELAYED_APP, | 2630 | .flags = DELAYED_APP, |
| 2633 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ | 2631 | .parent = &mpu_ck, /* Indexed by mpu speed, no parent */ |
| 2634 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ | 2632 | .recalc = &omap2_table_mpu_recalc, /* sets are keyed on mpu rate */ |
| 2635 | .set_rate = &omap2_select_table_rate, | 2633 | .set_rate = &omap2_select_table_rate, |
| 2636 | .round_rate = &omap2_round_to_table_rate, | 2634 | .round_rate = &omap2_round_to_table_rate, |
| 2637 | }; | 2635 | }; |
| 2638 | 2636 | ||
| 2639 | static struct clk *onchip_24xx_clks[] __initdata = { | ||
| 2640 | /* external root sources */ | ||
| 2641 | &func_32k_ck, | ||
| 2642 | &osc_ck, | ||
| 2643 | &sys_ck, | ||
| 2644 | &alt_ck, | ||
| 2645 | /* internal analog sources */ | ||
| 2646 | &dpll_ck, | ||
| 2647 | &apll96_ck, | ||
| 2648 | &apll54_ck, | ||
| 2649 | /* internal prcm root sources */ | ||
| 2650 | &func_54m_ck, | ||
| 2651 | &core_ck, | ||
| 2652 | &func_96m_ck, | ||
| 2653 | &func_48m_ck, | ||
| 2654 | &func_12m_ck, | ||
| 2655 | &wdt1_osc_ck, | ||
| 2656 | &sys_clkout_src, | ||
| 2657 | &sys_clkout, | ||
| 2658 | &sys_clkout2_src, | ||
| 2659 | &sys_clkout2, | ||
| 2660 | &emul_ck, | ||
| 2661 | /* mpu domain clocks */ | ||
| 2662 | &mpu_ck, | ||
| 2663 | /* dsp domain clocks */ | ||
| 2664 | &dsp_fck, | ||
| 2665 | &dsp_irate_ick, | ||
| 2666 | &dsp_ick, /* 242x */ | ||
| 2667 | &iva2_1_ick, /* 243x */ | ||
| 2668 | &iva1_ifck, /* 242x */ | ||
| 2669 | &iva1_mpu_int_ifck, /* 242x */ | ||
| 2670 | /* GFX domain clocks */ | ||
| 2671 | &gfx_3d_fck, | ||
| 2672 | &gfx_2d_fck, | ||
| 2673 | &gfx_ick, | ||
| 2674 | /* Modem domain clocks */ | ||
| 2675 | &mdm_ick, | ||
| 2676 | &mdm_osc_ck, | ||
| 2677 | /* DSS domain clocks */ | ||
| 2678 | &dss_ick, | ||
| 2679 | &dss1_fck, | ||
| 2680 | &dss2_fck, | ||
| 2681 | &dss_54m_fck, | ||
| 2682 | /* L3 domain clocks */ | ||
| 2683 | &core_l3_ck, | ||
| 2684 | &ssi_ssr_sst_fck, | ||
| 2685 | &usb_l4_ick, | ||
| 2686 | /* L4 domain clocks */ | ||
| 2687 | &l4_ck, /* used as both core_l4 and wu_l4 */ | ||
| 2688 | /* virtual meta-group clock */ | ||
| 2689 | &virt_prcm_set, | ||
| 2690 | /* general l4 interface ck, multi-parent functional clk */ | ||
| 2691 | &gpt1_ick, | ||
| 2692 | &gpt1_fck, | ||
| 2693 | &gpt2_ick, | ||
| 2694 | &gpt2_fck, | ||
| 2695 | &gpt3_ick, | ||
| 2696 | &gpt3_fck, | ||
| 2697 | &gpt4_ick, | ||
| 2698 | &gpt4_fck, | ||
| 2699 | &gpt5_ick, | ||
| 2700 | &gpt5_fck, | ||
| 2701 | &gpt6_ick, | ||
| 2702 | &gpt6_fck, | ||
| 2703 | &gpt7_ick, | ||
| 2704 | &gpt7_fck, | ||
| 2705 | &gpt8_ick, | ||
| 2706 | &gpt8_fck, | ||
| 2707 | &gpt9_ick, | ||
| 2708 | &gpt9_fck, | ||
| 2709 | &gpt10_ick, | ||
| 2710 | &gpt10_fck, | ||
| 2711 | &gpt11_ick, | ||
| 2712 | &gpt11_fck, | ||
| 2713 | &gpt12_ick, | ||
| 2714 | &gpt12_fck, | ||
| 2715 | &mcbsp1_ick, | ||
| 2716 | &mcbsp1_fck, | ||
| 2717 | &mcbsp2_ick, | ||
| 2718 | &mcbsp2_fck, | ||
| 2719 | &mcbsp3_ick, | ||
| 2720 | &mcbsp3_fck, | ||
| 2721 | &mcbsp4_ick, | ||
| 2722 | &mcbsp4_fck, | ||
| 2723 | &mcbsp5_ick, | ||
| 2724 | &mcbsp5_fck, | ||
| 2725 | &mcspi1_ick, | ||
| 2726 | &mcspi1_fck, | ||
| 2727 | &mcspi2_ick, | ||
| 2728 | &mcspi2_fck, | ||
| 2729 | &mcspi3_ick, | ||
| 2730 | &mcspi3_fck, | ||
| 2731 | &uart1_ick, | ||
| 2732 | &uart1_fck, | ||
| 2733 | &uart2_ick, | ||
| 2734 | &uart2_fck, | ||
| 2735 | &uart3_ick, | ||
| 2736 | &uart3_fck, | ||
| 2737 | &gpios_ick, | ||
| 2738 | &gpios_fck, | ||
| 2739 | &mpu_wdt_ick, | ||
| 2740 | &mpu_wdt_fck, | ||
| 2741 | &sync_32k_ick, | ||
| 2742 | &wdt1_ick, | ||
| 2743 | &omapctrl_ick, | ||
| 2744 | &icr_ick, | ||
| 2745 | &cam_fck, | ||
| 2746 | &cam_ick, | ||
| 2747 | &mailboxes_ick, | ||
| 2748 | &wdt4_ick, | ||
| 2749 | &wdt4_fck, | ||
| 2750 | &wdt3_ick, | ||
| 2751 | &wdt3_fck, | ||
| 2752 | &mspro_ick, | ||
| 2753 | &mspro_fck, | ||
| 2754 | &mmc_ick, | ||
| 2755 | &mmc_fck, | ||
| 2756 | &fac_ick, | ||
| 2757 | &fac_fck, | ||
| 2758 | &eac_ick, | ||
| 2759 | &eac_fck, | ||
| 2760 | &hdq_ick, | ||
| 2761 | &hdq_fck, | ||
| 2762 | &i2c1_ick, | ||
| 2763 | &i2c1_fck, | ||
| 2764 | &i2chs1_fck, | ||
| 2765 | &i2c2_ick, | ||
| 2766 | &i2c2_fck, | ||
| 2767 | &i2chs2_fck, | ||
| 2768 | &gpmc_fck, | ||
| 2769 | &sdma_fck, | ||
| 2770 | &sdma_ick, | ||
| 2771 | &vlynq_ick, | ||
| 2772 | &vlynq_fck, | ||
| 2773 | &sdrc_ick, | ||
| 2774 | &des_ick, | ||
| 2775 | &sha_ick, | ||
| 2776 | &rng_ick, | ||
| 2777 | &aes_ick, | ||
| 2778 | &pka_ick, | ||
| 2779 | &usb_fck, | ||
| 2780 | &usbhs_ick, | ||
| 2781 | &mmchs1_ick, | ||
| 2782 | &mmchs1_fck, | ||
| 2783 | &mmchs2_ick, | ||
| 2784 | &mmchs2_fck, | ||
| 2785 | &gpio5_ick, | ||
| 2786 | &gpio5_fck, | ||
| 2787 | &mdm_intc_ick, | ||
| 2788 | &mmchsdb1_fck, | ||
| 2789 | &mmchsdb2_fck, | ||
| 2790 | }; | ||
| 2791 | |||
| 2792 | #endif | 2637 | #endif |
| 2793 | 2638 | ||
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 31bb7010bd48..0a14dca31e30 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c | |||
| @@ -30,15 +30,251 @@ | |||
| 30 | #include <mach/clock.h> | 30 | #include <mach/clock.h> |
| 31 | #include <mach/sram.h> | 31 | #include <mach/sram.h> |
| 32 | #include <asm/div64.h> | 32 | #include <asm/div64.h> |
| 33 | #include <asm/clkdev.h> | ||
| 33 | 34 | ||
| 34 | #include "memory.h" | 35 | #include <mach/sdrc.h> |
| 35 | #include "clock.h" | 36 | #include "clock.h" |
| 36 | #include "clock34xx.h" | ||
| 37 | #include "prm.h" | 37 | #include "prm.h" |
| 38 | #include "prm-regbits-34xx.h" | 38 | #include "prm-regbits-34xx.h" |
| 39 | #include "cm.h" | 39 | #include "cm.h" |
| 40 | #include "cm-regbits-34xx.h" | 40 | #include "cm-regbits-34xx.h" |
| 41 | 41 | ||
| 42 | static const struct clkops clkops_noncore_dpll_ops; | ||
| 43 | |||
| 44 | #include "clock34xx.h" | ||
| 45 | |||
| 46 | struct omap_clk { | ||
| 47 | u32 cpu; | ||
| 48 | struct clk_lookup lk; | ||
| 49 | }; | ||
| 50 | |||
| 51 | #define CLK(dev, con, ck, cp) \ | ||
| 52 | { \ | ||
| 53 | .cpu = cp, \ | ||
| 54 | .lk = { \ | ||
| 55 | .dev_id = dev, \ | ||
| 56 | .con_id = con, \ | ||
| 57 | .clk = ck, \ | ||
| 58 | }, \ | ||
| 59 | } | ||
| 60 | |||
| 61 | #define CK_343X (1 << 0) | ||
| 62 | #define CK_3430ES1 (1 << 1) | ||
| 63 | #define CK_3430ES2 (1 << 2) | ||
| 64 | |||
| 65 | static struct omap_clk omap34xx_clks[] = { | ||
| 66 | CLK(NULL, "omap_32k_fck", &omap_32k_fck, CK_343X), | ||
| 67 | CLK(NULL, "virt_12m_ck", &virt_12m_ck, CK_343X), | ||
| 68 | CLK(NULL, "virt_13m_ck", &virt_13m_ck, CK_343X), | ||
| 69 | CLK(NULL, "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2), | ||
| 70 | CLK(NULL, "virt_19_2m_ck", &virt_19_2m_ck, CK_343X), | ||
| 71 | CLK(NULL, "virt_26m_ck", &virt_26m_ck, CK_343X), | ||
| 72 | CLK(NULL, "virt_38_4m_ck", &virt_38_4m_ck, CK_343X), | ||
| 73 | CLK(NULL, "osc_sys_ck", &osc_sys_ck, CK_343X), | ||
| 74 | CLK(NULL, "sys_ck", &sys_ck, CK_343X), | ||
| 75 | CLK(NULL, "sys_altclk", &sys_altclk, CK_343X), | ||
| 76 | CLK(NULL, "mcbsp_clks", &mcbsp_clks, CK_343X), | ||
| 77 | CLK(NULL, "sys_clkout1", &sys_clkout1, CK_343X), | ||
| 78 | CLK(NULL, "dpll1_ck", &dpll1_ck, CK_343X), | ||
| 79 | CLK(NULL, "dpll1_x2_ck", &dpll1_x2_ck, CK_343X), | ||
| 80 | CLK(NULL, "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_343X), | ||
| 81 | CLK(NULL, "dpll2_ck", &dpll2_ck, CK_343X), | ||
| 82 | CLK(NULL, "dpll2_m2_ck", &dpll2_m2_ck, CK_343X), | ||
| 83 | CLK(NULL, "dpll3_ck", &dpll3_ck, CK_343X), | ||
| 84 | CLK(NULL, "core_ck", &core_ck, CK_343X), | ||
| 85 | CLK(NULL, "dpll3_x2_ck", &dpll3_x2_ck, CK_343X), | ||
| 86 | CLK(NULL, "dpll3_m2_ck", &dpll3_m2_ck, CK_343X), | ||
| 87 | CLK(NULL, "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_343X), | ||
| 88 | CLK(NULL, "dpll3_m3_ck", &dpll3_m3_ck, CK_343X), | ||
| 89 | CLK(NULL, "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_343X), | ||
| 90 | CLK(NULL, "emu_core_alwon_ck", &emu_core_alwon_ck, CK_343X), | ||
| 91 | CLK(NULL, "dpll4_ck", &dpll4_ck, CK_343X), | ||
| 92 | CLK(NULL, "dpll4_x2_ck", &dpll4_x2_ck, CK_343X), | ||
| 93 | CLK(NULL, "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_343X), | ||
| 94 | CLK(NULL, "omap_96m_fck", &omap_96m_fck, CK_343X), | ||
| 95 | CLK(NULL, "cm_96m_fck", &cm_96m_fck, CK_343X), | ||
| 96 | CLK(NULL, "omap_54m_fck", &omap_54m_fck, CK_343X), | ||
| 97 | CLK(NULL, "omap_48m_fck", &omap_48m_fck, CK_343X), | ||
| 98 | CLK(NULL, "omap_12m_fck", &omap_12m_fck, CK_343X), | ||
| 99 | CLK(NULL, "dpll4_m2_ck", &dpll4_m2_ck, CK_343X), | ||
| 100 | CLK(NULL, "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_343X), | ||
| 101 | CLK(NULL, "dpll4_m3_ck", &dpll4_m3_ck, CK_343X), | ||
| 102 | CLK(NULL, "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_343X), | ||
| 103 | CLK(NULL, "dpll4_m4_ck", &dpll4_m4_ck, CK_343X), | ||
| 104 | CLK(NULL, "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_343X), | ||
| 105 | CLK(NULL, "dpll4_m5_ck", &dpll4_m5_ck, CK_343X), | ||
| 106 | CLK(NULL, "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_343X), | ||
| 107 | CLK(NULL, "dpll4_m6_ck", &dpll4_m6_ck, CK_343X), | ||
| 108 | CLK(NULL, "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_343X), | ||
| 109 | CLK(NULL, "emu_per_alwon_ck", &emu_per_alwon_ck, CK_343X), | ||
| 110 | CLK(NULL, "dpll5_ck", &dpll5_ck, CK_3430ES2), | ||
| 111 | CLK(NULL, "dpll5_m2_ck", &dpll5_m2_ck, CK_3430ES2), | ||
| 112 | CLK(NULL, "clkout2_src_ck", &clkout2_src_ck, CK_343X), | ||
| 113 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_343X), | ||
| 114 | CLK(NULL, "corex2_fck", &corex2_fck, CK_343X), | ||
| 115 | CLK(NULL, "dpll1_fck", &dpll1_fck, CK_343X), | ||
| 116 | CLK(NULL, "mpu_ck", &mpu_ck, CK_343X), | ||
| 117 | CLK(NULL, "arm_fck", &arm_fck, CK_343X), | ||
| 118 | CLK(NULL, "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_343X), | ||
| 119 | CLK(NULL, "dpll2_fck", &dpll2_fck, CK_343X), | ||
| 120 | CLK(NULL, "iva2_ck", &iva2_ck, CK_343X), | ||
| 121 | CLK(NULL, "l3_ick", &l3_ick, CK_343X), | ||
| 122 | CLK(NULL, "l4_ick", &l4_ick, CK_343X), | ||
| 123 | CLK(NULL, "rm_ick", &rm_ick, CK_343X), | ||
| 124 | CLK(NULL, "gfx_l3_ck", &gfx_l3_ck, CK_3430ES1), | ||
| 125 | CLK(NULL, "gfx_l3_fck", &gfx_l3_fck, CK_3430ES1), | ||
| 126 | CLK(NULL, "gfx_l3_ick", &gfx_l3_ick, CK_3430ES1), | ||
| 127 | CLK(NULL, "gfx_cg1_ck", &gfx_cg1_ck, CK_3430ES1), | ||
| 128 | CLK(NULL, "gfx_cg2_ck", &gfx_cg2_ck, CK_3430ES1), | ||
| 129 | CLK(NULL, "sgx_fck", &sgx_fck, CK_3430ES2), | ||
| 130 | CLK(NULL, "sgx_ick", &sgx_ick, CK_3430ES2), | ||
| 131 | CLK(NULL, "d2d_26m_fck", &d2d_26m_fck, CK_3430ES1), | ||
| 132 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_343X), | ||
| 133 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_343X), | ||
| 134 | CLK(NULL, "cpefuse_fck", &cpefuse_fck, CK_3430ES2), | ||
| 135 | CLK(NULL, "ts_fck", &ts_fck, CK_3430ES2), | ||
| 136 | CLK(NULL, "usbtll_fck", &usbtll_fck, CK_3430ES2), | ||
| 137 | CLK(NULL, "core_96m_fck", &core_96m_fck, CK_343X), | ||
| 138 | CLK("mmci-omap-hs.2", "fck", &mmchs3_fck, CK_3430ES2), | ||
| 139 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_343X), | ||
| 140 | CLK(NULL, "mspro_fck", &mspro_fck, CK_343X), | ||
| 141 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_343X), | ||
| 142 | CLK("i2c_omap.3", "fck", &i2c3_fck, CK_343X), | ||
| 143 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_343X), | ||
| 144 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_343X), | ||
| 145 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_343X), | ||
| 146 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_343X), | ||
| 147 | CLK(NULL, "core_48m_fck", &core_48m_fck, CK_343X), | ||
| 148 | CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_343X), | ||
| 149 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_343X), | ||
| 150 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_343X), | ||
| 151 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_343X), | ||
| 152 | CLK(NULL, "uart2_fck", &uart2_fck, CK_343X), | ||
| 153 | CLK(NULL, "uart1_fck", &uart1_fck, CK_343X), | ||
| 154 | CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1), | ||
| 155 | CLK(NULL, "core_12m_fck", &core_12m_fck, CK_343X), | ||
| 156 | CLK("omap_hdq.0", "fck", &hdq_fck, CK_343X), | ||
| 157 | CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck, CK_343X), | ||
| 158 | CLK(NULL, "ssi_sst_fck", &ssi_sst_fck, CK_343X), | ||
| 159 | CLK(NULL, "core_l3_ick", &core_l3_ick, CK_343X), | ||
| 160 | CLK(NULL, "hsotgusb_ick", &hsotgusb_ick, CK_343X), | ||
| 161 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_343X), | ||
| 162 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_343X), | ||
| 163 | CLK(NULL, "security_l3_ick", &security_l3_ick, CK_343X), | ||
| 164 | CLK(NULL, "pka_ick", &pka_ick, CK_343X), | ||
| 165 | CLK(NULL, "core_l4_ick", &core_l4_ick, CK_343X), | ||
| 166 | CLK(NULL, "usbtll_ick", &usbtll_ick, CK_3430ES2), | ||
| 167 | CLK("mmci-omap-hs.2", "ick", &mmchs3_ick, CK_3430ES2), | ||
| 168 | CLK(NULL, "icr_ick", &icr_ick, CK_343X), | ||
| 169 | CLK(NULL, "aes2_ick", &aes2_ick, CK_343X), | ||
| 170 | CLK(NULL, "sha12_ick", &sha12_ick, CK_343X), | ||
| 171 | CLK(NULL, "des2_ick", &des2_ick, CK_343X), | ||
| 172 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_343X), | ||
| 173 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_343X), | ||
| 174 | CLK(NULL, "mspro_ick", &mspro_ick, CK_343X), | ||
| 175 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_343X), | ||
| 176 | CLK("omap2_mcspi.4", "ick", &mcspi4_ick, CK_343X), | ||
| 177 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_343X), | ||
| 178 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_343X), | ||
| 179 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_343X), | ||
| 180 | CLK("i2c_omap.3", "ick", &i2c3_ick, CK_343X), | ||
| 181 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_343X), | ||
| 182 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_343X), | ||
| 183 | CLK(NULL, "uart2_ick", &uart2_ick, CK_343X), | ||
| 184 | CLK(NULL, "uart1_ick", &uart1_ick, CK_343X), | ||
| 185 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_343X), | ||
| 186 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_343X), | ||
| 187 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_343X), | ||
| 188 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_343X), | ||
| 189 | CLK(NULL, "fac_ick", &fac_ick, CK_3430ES1), | ||
| 190 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_343X), | ||
| 191 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_343X), | ||
| 192 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_343X), | ||
| 193 | CLK(NULL, "ssi_ick", &ssi_ick, CK_343X), | ||
| 194 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_3430ES1), | ||
| 195 | CLK(NULL, "security_l4_ick2", &security_l4_ick2, CK_343X), | ||
| 196 | CLK(NULL, "aes1_ick", &aes1_ick, CK_343X), | ||
| 197 | CLK("omap_rng", "ick", &rng_ick, CK_343X), | ||
| 198 | CLK(NULL, "sha11_ick", &sha11_ick, CK_343X), | ||
| 199 | CLK(NULL, "des1_ick", &des1_ick, CK_343X), | ||
| 200 | CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck, CK_343X), | ||
| 201 | CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_343X), | ||
| 202 | CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_343X), | ||
| 203 | CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_343X), | ||
| 204 | CLK(NULL, "dss_ick", &dss_ick, CK_343X), | ||
| 205 | CLK(NULL, "cam_mclk", &cam_mclk, CK_343X), | ||
| 206 | CLK(NULL, "cam_ick", &cam_ick, CK_343X), | ||
| 207 | CLK(NULL, "csi2_96m_fck", &csi2_96m_fck, CK_343X), | ||
| 208 | CLK(NULL, "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2), | ||
| 209 | CLK(NULL, "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2), | ||
| 210 | CLK(NULL, "usbhost_ick", &usbhost_ick, CK_3430ES2), | ||
| 211 | CLK(NULL, "usim_fck", &usim_fck, CK_3430ES2), | ||
| 212 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_343X), | ||
| 213 | CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_343X), | ||
| 214 | CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_343X), | ||
| 215 | CLK("omap_wdt", "fck", &wdt2_fck, CK_343X), | ||
| 216 | CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_343X), | ||
| 217 | CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2), | ||
| 218 | CLK("omap_wdt", "ick", &wdt2_ick, CK_343X), | ||
| 219 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_343X), | ||
| 220 | CLK(NULL, "gpio1_ick", &gpio1_ick, CK_343X), | ||
| 221 | CLK(NULL, "omap_32ksync_ick", &omap_32ksync_ick, CK_343X), | ||
| 222 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_343X), | ||
| 223 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_343X), | ||
| 224 | CLK(NULL, "per_96m_fck", &per_96m_fck, CK_343X), | ||
| 225 | CLK(NULL, "per_48m_fck", &per_48m_fck, CK_343X), | ||
| 226 | CLK(NULL, "uart3_fck", &uart3_fck, CK_343X), | ||
| 227 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_343X), | ||
| 228 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_343X), | ||
| 229 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_343X), | ||
| 230 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_343X), | ||
| 231 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_343X), | ||
| 232 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_343X), | ||
| 233 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_343X), | ||
| 234 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_343X), | ||
| 235 | CLK(NULL, "per_32k_alwon_fck", &per_32k_alwon_fck, CK_343X), | ||
| 236 | CLK(NULL, "gpio6_dbck", &gpio6_dbck, CK_343X), | ||
| 237 | CLK(NULL, "gpio5_dbck", &gpio5_dbck, CK_343X), | ||
| 238 | CLK(NULL, "gpio4_dbck", &gpio4_dbck, CK_343X), | ||
| 239 | CLK(NULL, "gpio3_dbck", &gpio3_dbck, CK_343X), | ||
| 240 | CLK(NULL, "gpio2_dbck", &gpio2_dbck, CK_343X), | ||
| 241 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_343X), | ||
| 242 | CLK(NULL, "per_l4_ick", &per_l4_ick, CK_343X), | ||
| 243 | CLK(NULL, "gpio6_ick", &gpio6_ick, CK_343X), | ||
| 244 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_343X), | ||
| 245 | CLK(NULL, "gpio4_ick", &gpio4_ick, CK_343X), | ||
| 246 | CLK(NULL, "gpio3_ick", &gpio3_ick, CK_343X), | ||
| 247 | CLK(NULL, "gpio2_ick", &gpio2_ick, CK_343X), | ||
| 248 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_343X), | ||
| 249 | CLK(NULL, "uart3_ick", &uart3_ick, CK_343X), | ||
| 250 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_343X), | ||
| 251 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_343X), | ||
| 252 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_343X), | ||
| 253 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_343X), | ||
| 254 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_343X), | ||
| 255 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_343X), | ||
| 256 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_343X), | ||
| 257 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_343X), | ||
| 258 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_343X), | ||
| 259 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_343X), | ||
| 260 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_343X), | ||
| 261 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_343X), | ||
| 262 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_343X), | ||
| 263 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_343X), | ||
| 264 | CLK(NULL, "emu_src_ck", &emu_src_ck, CK_343X), | ||
| 265 | CLK(NULL, "pclk_fck", &pclk_fck, CK_343X), | ||
| 266 | CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_343X), | ||
| 267 | CLK(NULL, "atclk_fck", &atclk_fck, CK_343X), | ||
| 268 | CLK(NULL, "traceclk_src_fck", &traceclk_src_fck, CK_343X), | ||
| 269 | CLK(NULL, "traceclk_fck", &traceclk_fck, CK_343X), | ||
| 270 | CLK(NULL, "sr1_fck", &sr1_fck, CK_343X), | ||
| 271 | CLK(NULL, "sr2_fck", &sr2_fck, CK_343X), | ||
| 272 | CLK(NULL, "sr_l4_ick", &sr_l4_ick, CK_343X), | ||
| 273 | CLK(NULL, "secure_32k_fck", &secure_32k_fck, CK_343X), | ||
| 274 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_343X), | ||
| 275 | CLK(NULL, "wdt1_fck", &wdt1_fck, CK_343X), | ||
| 276 | }; | ||
| 277 | |||
| 42 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ | 278 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ |
| 43 | #define DPLL_AUTOIDLE_DISABLE 0x0 | 279 | #define DPLL_AUTOIDLE_DISABLE 0x0 |
| 44 | #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 | 280 | #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 |
| @@ -51,11 +287,9 @@ | |||
| 51 | * | 287 | * |
| 52 | * Recalculate and propagate the DPLL rate. | 288 | * Recalculate and propagate the DPLL rate. |
| 53 | */ | 289 | */ |
| 54 | static void omap3_dpll_recalc(struct clk *clk) | 290 | static unsigned long omap3_dpll_recalc(struct clk *clk) |
| 55 | { | 291 | { |
| 56 | clk->rate = omap2_get_dpll_rate(clk); | 292 | return omap2_get_dpll_rate(clk); |
| 57 | |||
| 58 | propagate_rate(clk); | ||
| 59 | } | 293 | } |
| 60 | 294 | ||
| 61 | /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ | 295 | /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ |
| @@ -78,14 +312,12 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) | |||
| 78 | const struct dpll_data *dd; | 312 | const struct dpll_data *dd; |
| 79 | int i = 0; | 313 | int i = 0; |
| 80 | int ret = -EINVAL; | 314 | int ret = -EINVAL; |
| 81 | u32 idlest_mask; | ||
| 82 | 315 | ||
| 83 | dd = clk->dpll_data; | 316 | dd = clk->dpll_data; |
| 84 | 317 | ||
| 85 | state <<= dd->idlest_bit; | 318 | state <<= __ffs(dd->idlest_mask); |
| 86 | idlest_mask = 1 << dd->idlest_bit; | ||
| 87 | 319 | ||
| 88 | while (((__raw_readl(dd->idlest_reg) & idlest_mask) != state) && | 320 | while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && |
| 89 | i < MAX_DPLL_WAIT_TRIES) { | 321 | i < MAX_DPLL_WAIT_TRIES) { |
| 90 | i++; | 322 | i++; |
| 91 | udelay(1); | 323 | udelay(1); |
| @@ -104,6 +336,42 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state) | |||
| 104 | return ret; | 336 | return ret; |
| 105 | } | 337 | } |
| 106 | 338 | ||
| 339 | /* From 3430 TRM ES2 4.7.6.2 */ | ||
| 340 | static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) | ||
| 341 | { | ||
| 342 | unsigned long fint; | ||
| 343 | u16 f = 0; | ||
| 344 | |||
| 345 | fint = clk->dpll_data->clk_ref->rate / (n + 1); | ||
| 346 | |||
| 347 | pr_debug("clock: fint is %lu\n", fint); | ||
| 348 | |||
| 349 | if (fint >= 750000 && fint <= 1000000) | ||
| 350 | f = 0x3; | ||
| 351 | else if (fint > 1000000 && fint <= 1250000) | ||
| 352 | f = 0x4; | ||
| 353 | else if (fint > 1250000 && fint <= 1500000) | ||
| 354 | f = 0x5; | ||
| 355 | else if (fint > 1500000 && fint <= 1750000) | ||
| 356 | f = 0x6; | ||
| 357 | else if (fint > 1750000 && fint <= 2100000) | ||
| 358 | f = 0x7; | ||
| 359 | else if (fint > 7500000 && fint <= 10000000) | ||
| 360 | f = 0xB; | ||
| 361 | else if (fint > 10000000 && fint <= 12500000) | ||
| 362 | f = 0xC; | ||
| 363 | else if (fint > 12500000 && fint <= 15000000) | ||
| 364 | f = 0xD; | ||
| 365 | else if (fint > 15000000 && fint <= 17500000) | ||
| 366 | f = 0xE; | ||
| 367 | else if (fint > 17500000 && fint <= 21000000) | ||
| 368 | f = 0xF; | ||
| 369 | else | ||
| 370 | pr_debug("clock: unknown freqsel setting for %d\n", n); | ||
| 371 | |||
| 372 | return f; | ||
| 373 | } | ||
| 374 | |||
| 107 | /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ | 375 | /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ |
| 108 | 376 | ||
| 109 | /* | 377 | /* |
| @@ -128,25 +396,20 @@ static int _omap3_noncore_dpll_lock(struct clk *clk) | |||
| 128 | 396 | ||
| 129 | ai = omap3_dpll_autoidle_read(clk); | 397 | ai = omap3_dpll_autoidle_read(clk); |
| 130 | 398 | ||
| 399 | omap3_dpll_deny_idle(clk); | ||
| 400 | |||
| 131 | _omap3_dpll_write_clken(clk, DPLL_LOCKED); | 401 | _omap3_dpll_write_clken(clk, DPLL_LOCKED); |
| 132 | 402 | ||
| 133 | if (ai) { | 403 | r = _omap3_wait_dpll_status(clk, 1); |
| 134 | /* | 404 | |
| 135 | * If no downstream clocks are enabled, CM_IDLEST bit | 405 | if (ai) |
| 136 | * may never become active, so don't wait for DPLL to lock. | ||
| 137 | */ | ||
| 138 | r = 0; | ||
| 139 | omap3_dpll_allow_idle(clk); | 406 | omap3_dpll_allow_idle(clk); |
| 140 | } else { | ||
| 141 | r = _omap3_wait_dpll_status(clk, 1); | ||
| 142 | omap3_dpll_deny_idle(clk); | ||
| 143 | }; | ||
| 144 | 407 | ||
| 145 | return r; | 408 | return r; |
| 146 | } | 409 | } |
| 147 | 410 | ||
| 148 | /* | 411 | /* |
| 149 | * omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness | 412 | * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness |
| 150 | * @clk: pointer to a DPLL struct clk | 413 | * @clk: pointer to a DPLL struct clk |
| 151 | * | 414 | * |
| 152 | * Instructs a non-CORE DPLL to enter low-power bypass mode. In | 415 | * Instructs a non-CORE DPLL to enter low-power bypass mode. In |
| @@ -236,14 +499,25 @@ static int _omap3_noncore_dpll_stop(struct clk *clk) | |||
| 236 | static int omap3_noncore_dpll_enable(struct clk *clk) | 499 | static int omap3_noncore_dpll_enable(struct clk *clk) |
| 237 | { | 500 | { |
| 238 | int r; | 501 | int r; |
| 502 | struct dpll_data *dd; | ||
| 239 | 503 | ||
| 240 | if (clk == &dpll3_ck) | 504 | if (clk == &dpll3_ck) |
| 241 | return -EINVAL; | 505 | return -EINVAL; |
| 242 | 506 | ||
| 243 | if (clk->parent->rate == clk_get_rate(clk)) | 507 | dd = clk->dpll_data; |
| 508 | if (!dd) | ||
| 509 | return -EINVAL; | ||
| 510 | |||
| 511 | if (clk->rate == dd->clk_bypass->rate) { | ||
| 512 | WARN_ON(clk->parent != dd->clk_bypass); | ||
| 244 | r = _omap3_noncore_dpll_bypass(clk); | 513 | r = _omap3_noncore_dpll_bypass(clk); |
| 245 | else | 514 | } else { |
| 515 | WARN_ON(clk->parent != dd->clk_ref); | ||
| 246 | r = _omap3_noncore_dpll_lock(clk); | 516 | r = _omap3_noncore_dpll_lock(clk); |
| 517 | } | ||
| 518 | /* FIXME: this is dubious - if clk->rate has changed, what about propagating? */ | ||
| 519 | if (!r) | ||
| 520 | clk->rate = omap2_get_dpll_rate(clk); | ||
| 247 | 521 | ||
| 248 | return r; | 522 | return r; |
| 249 | } | 523 | } |
| @@ -270,6 +544,215 @@ static void omap3_noncore_dpll_disable(struct clk *clk) | |||
| 270 | _omap3_noncore_dpll_stop(clk); | 544 | _omap3_noncore_dpll_stop(clk); |
| 271 | } | 545 | } |
| 272 | 546 | ||
| 547 | |||
| 548 | /* Non-CORE DPLL rate set code */ | ||
| 549 | |||
| 550 | /* | ||
| 551 | * omap3_noncore_dpll_program - set non-core DPLL M,N values directly | ||
| 552 | * @clk: struct clk * of DPLL to set | ||
| 553 | * @m: DPLL multiplier to set | ||
| 554 | * @n: DPLL divider to set | ||
| 555 | * @freqsel: FREQSEL value to set | ||
| 556 | * | ||
| 557 | * Program the DPLL with the supplied M, N values, and wait for the DPLL to | ||
| 558 | * lock.. Returns -EINVAL upon error, or 0 upon success. | ||
| 559 | */ | ||
| 560 | static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | ||
| 561 | { | ||
| 562 | struct dpll_data *dd = clk->dpll_data; | ||
| 563 | u32 v; | ||
| 564 | |||
| 565 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ | ||
| 566 | _omap3_noncore_dpll_bypass(clk); | ||
| 567 | |||
| 568 | /* Set jitter correction */ | ||
| 569 | v = __raw_readl(dd->control_reg); | ||
| 570 | v &= ~dd->freqsel_mask; | ||
| 571 | v |= freqsel << __ffs(dd->freqsel_mask); | ||
| 572 | __raw_writel(v, dd->control_reg); | ||
| 573 | |||
| 574 | /* Set DPLL multiplier, divider */ | ||
| 575 | v = __raw_readl(dd->mult_div1_reg); | ||
| 576 | v &= ~(dd->mult_mask | dd->div1_mask); | ||
| 577 | v |= m << __ffs(dd->mult_mask); | ||
| 578 | v |= (n - 1) << __ffs(dd->div1_mask); | ||
| 579 | __raw_writel(v, dd->mult_div1_reg); | ||
| 580 | |||
| 581 | /* We let the clock framework set the other output dividers later */ | ||
| 582 | |||
| 583 | /* REVISIT: Set ramp-up delay? */ | ||
| 584 | |||
| 585 | _omap3_noncore_dpll_lock(clk); | ||
| 586 | |||
| 587 | return 0; | ||
| 588 | } | ||
| 589 | |||
| 590 | /** | ||
| 591 | * omap3_noncore_dpll_set_rate - set non-core DPLL rate | ||
| 592 | * @clk: struct clk * of DPLL to set | ||
| 593 | * @rate: rounded target rate | ||
| 594 | * | ||
| 595 | * Set the DPLL CLKOUT to the target rate. If the DPLL can enter | ||
| 596 | * low-power bypass, and the target rate is the bypass source clock | ||
| 597 | * rate, then configure the DPLL for bypass. Otherwise, round the | ||
| 598 | * target rate if it hasn't been done already, then program and lock | ||
| 599 | * the DPLL. Returns -EINVAL upon error, or 0 upon success. | ||
| 600 | */ | ||
| 601 | static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | ||
| 602 | { | ||
| 603 | struct clk *new_parent = NULL; | ||
| 604 | u16 freqsel; | ||
| 605 | struct dpll_data *dd; | ||
| 606 | int ret; | ||
| 607 | |||
| 608 | if (!clk || !rate) | ||
| 609 | return -EINVAL; | ||
| 610 | |||
| 611 | dd = clk->dpll_data; | ||
| 612 | if (!dd) | ||
| 613 | return -EINVAL; | ||
| 614 | |||
| 615 | if (rate == omap2_get_dpll_rate(clk)) | ||
| 616 | return 0; | ||
| 617 | |||
| 618 | /* | ||
| 619 | * Ensure both the bypass and ref clocks are enabled prior to | ||
| 620 | * doing anything; we need the bypass clock running to reprogram | ||
| 621 | * the DPLL. | ||
| 622 | */ | ||
| 623 | omap2_clk_enable(dd->clk_bypass); | ||
| 624 | omap2_clk_enable(dd->clk_ref); | ||
| 625 | |||
| 626 | if (dd->clk_bypass->rate == rate && | ||
| 627 | (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { | ||
| 628 | pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); | ||
| 629 | |||
| 630 | ret = _omap3_noncore_dpll_bypass(clk); | ||
| 631 | if (!ret) | ||
| 632 | new_parent = dd->clk_bypass; | ||
| 633 | } else { | ||
| 634 | if (dd->last_rounded_rate != rate) | ||
| 635 | omap2_dpll_round_rate(clk, rate); | ||
| 636 | |||
| 637 | if (dd->last_rounded_rate == 0) | ||
| 638 | return -EINVAL; | ||
| 639 | |||
| 640 | freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); | ||
| 641 | if (!freqsel) | ||
| 642 | WARN_ON(1); | ||
| 643 | |||
| 644 | pr_debug("clock: %s: set rate: locking rate to %lu.\n", | ||
| 645 | clk->name, rate); | ||
| 646 | |||
| 647 | ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, | ||
| 648 | dd->last_rounded_n, freqsel); | ||
| 649 | if (!ret) | ||
| 650 | new_parent = dd->clk_ref; | ||
| 651 | } | ||
| 652 | if (!ret) { | ||
| 653 | /* | ||
| 654 | * Switch the parent clock in the heirarchy, and make sure | ||
| 655 | * that the new parent's usecount is correct. Note: we | ||
| 656 | * enable the new parent before disabling the old to avoid | ||
| 657 | * any unnecessary hardware disable->enable transitions. | ||
| 658 | */ | ||
| 659 | if (clk->usecount) { | ||
| 660 | omap2_clk_enable(new_parent); | ||
| 661 | omap2_clk_disable(clk->parent); | ||
| 662 | } | ||
| 663 | clk_reparent(clk, new_parent); | ||
| 664 | clk->rate = rate; | ||
| 665 | } | ||
| 666 | omap2_clk_disable(dd->clk_ref); | ||
| 667 | omap2_clk_disable(dd->clk_bypass); | ||
| 668 | |||
| 669 | return 0; | ||
| 670 | } | ||
| 671 | |||
| 672 | static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate) | ||
| 673 | { | ||
| 674 | /* | ||
| 675 | * According to the 12-5 CDP code from TI, "Limitation 2.5" | ||
| 676 | * on 3430ES1 prevents us from changing DPLL multipliers or dividers | ||
| 677 | * on DPLL4. | ||
| 678 | */ | ||
| 679 | if (omap_rev() == OMAP3430_REV_ES1_0) { | ||
| 680 | printk(KERN_ERR "clock: DPLL4 cannot change rate due to " | ||
| 681 | "silicon 'Limitation 2.5' on 3430ES1.\n"); | ||
| 682 | return -EINVAL; | ||
| 683 | } | ||
| 684 | return omap3_noncore_dpll_set_rate(clk, rate); | ||
| 685 | } | ||
| 686 | |||
| 687 | |||
| 688 | /* | ||
| 689 | * CORE DPLL (DPLL3) rate programming functions | ||
| 690 | * | ||
| 691 | * These call into SRAM code to do the actual CM writes, since the SDRAM | ||
| 692 | * is clocked from DPLL3. | ||
| 693 | */ | ||
| 694 | |||
| 695 | /** | ||
| 696 | * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider | ||
| 697 | * @clk: struct clk * of DPLL to set | ||
| 698 | * @rate: rounded target rate | ||
| 699 | * | ||
| 700 | * Program the DPLL M2 divider with the rounded target rate. Returns | ||
| 701 | * -EINVAL upon error, or 0 upon success. | ||
| 702 | */ | ||
| 703 | static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) | ||
| 704 | { | ||
| 705 | u32 new_div = 0; | ||
| 706 | unsigned long validrate, sdrcrate; | ||
| 707 | struct omap_sdrc_params *sp; | ||
| 708 | |||
| 709 | if (!clk || !rate) | ||
| 710 | return -EINVAL; | ||
| 711 | |||
| 712 | if (clk != &dpll3_m2_ck) | ||
| 713 | return -EINVAL; | ||
| 714 | |||
| 715 | if (rate == clk->rate) | ||
| 716 | return 0; | ||
| 717 | |||
| 718 | validrate = omap2_clksel_round_rate_div(clk, rate, &new_div); | ||
| 719 | if (validrate != rate) | ||
| 720 | return -EINVAL; | ||
| 721 | |||
| 722 | sdrcrate = sdrc_ick.rate; | ||
| 723 | if (rate > clk->rate) | ||
| 724 | sdrcrate <<= ((rate / clk->rate) - 1); | ||
| 725 | else | ||
| 726 | sdrcrate >>= ((clk->rate / rate) - 1); | ||
| 727 | |||
| 728 | sp = omap2_sdrc_get_params(sdrcrate); | ||
| 729 | if (!sp) | ||
| 730 | return -EINVAL; | ||
| 731 | |||
| 732 | pr_info("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate, | ||
| 733 | validrate); | ||
| 734 | pr_info("clock: SDRC timing params used: %08x %08x %08x\n", | ||
| 735 | sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb); | ||
| 736 | |||
| 737 | /* REVISIT: SRAM code doesn't support other M2 divisors yet */ | ||
| 738 | WARN_ON(new_div != 1 && new_div != 2); | ||
| 739 | |||
| 740 | /* REVISIT: Add SDRC_MR changing to this code also */ | ||
| 741 | omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla, | ||
| 742 | sp->actim_ctrlb, new_div); | ||
| 743 | |||
| 744 | return 0; | ||
| 745 | } | ||
| 746 | |||
| 747 | |||
| 748 | static const struct clkops clkops_noncore_dpll_ops = { | ||
| 749 | .enable = &omap3_noncore_dpll_enable, | ||
| 750 | .disable = &omap3_noncore_dpll_disable, | ||
| 751 | }; | ||
| 752 | |||
| 753 | /* DPLL autoidle read/set code */ | ||
| 754 | |||
| 755 | |||
| 273 | /** | 756 | /** |
| 274 | * omap3_dpll_autoidle_read - read a DPLL's autoidle bits | 757 | * omap3_dpll_autoidle_read - read a DPLL's autoidle bits |
| 275 | * @clk: struct clk * of the DPLL to read | 758 | * @clk: struct clk * of the DPLL to read |
| @@ -356,9 +839,10 @@ static void omap3_dpll_deny_idle(struct clk *clk) | |||
| 356 | * Using parent clock DPLL data, look up DPLL state. If locked, set our | 839 | * Using parent clock DPLL data, look up DPLL state. If locked, set our |
| 357 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. | 840 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. |
| 358 | */ | 841 | */ |
| 359 | static void omap3_clkoutx2_recalc(struct clk *clk) | 842 | static unsigned long omap3_clkoutx2_recalc(struct clk *clk) |
| 360 | { | 843 | { |
| 361 | const struct dpll_data *dd; | 844 | const struct dpll_data *dd; |
| 845 | unsigned long rate; | ||
| 362 | u32 v; | 846 | u32 v; |
| 363 | struct clk *pclk; | 847 | struct clk *pclk; |
| 364 | 848 | ||
| @@ -372,17 +856,15 @@ static void omap3_clkoutx2_recalc(struct clk *clk) | |||
| 372 | 856 | ||
| 373 | dd = pclk->dpll_data; | 857 | dd = pclk->dpll_data; |
| 374 | 858 | ||
| 375 | WARN_ON(!dd->control_reg || !dd->enable_mask); | 859 | WARN_ON(!dd->enable_mask); |
| 376 | 860 | ||
| 377 | v = __raw_readl(dd->control_reg) & dd->enable_mask; | 861 | v = __raw_readl(dd->control_reg) & dd->enable_mask; |
| 378 | v >>= __ffs(dd->enable_mask); | 862 | v >>= __ffs(dd->enable_mask); |
| 379 | if (v != DPLL_LOCKED) | 863 | if (v != OMAP3XXX_EN_DPLL_LOCKED) |
| 380 | clk->rate = clk->parent->rate; | 864 | rate = clk->parent->rate; |
| 381 | else | 865 | else |
| 382 | clk->rate = clk->parent->rate * 2; | 866 | rate = clk->parent->rate * 2; |
| 383 | 867 | return rate; | |
| 384 | if (clk->flags & RATE_PROPAGATES) | ||
| 385 | propagate_rate(clk); | ||
| 386 | } | 868 | } |
| 387 | 869 | ||
| 388 | /* Common clock code */ | 870 | /* Common clock code */ |
| @@ -432,7 +914,7 @@ static int __init omap2_clk_arch_init(void) | |||
| 432 | 914 | ||
| 433 | /* REVISIT: not yet ready for 343x */ | 915 | /* REVISIT: not yet ready for 343x */ |
| 434 | #if 0 | 916 | #if 0 |
| 435 | if (omap2_select_table_rate(&virt_prcm_set, mpurate)) | 917 | if (clk_set_rate(&virt_prcm_set, mpurate)) |
| 436 | printk(KERN_ERR "Could not find matching MPU rate\n"); | 918 | printk(KERN_ERR "Could not find matching MPU rate\n"); |
| 437 | #endif | 919 | #endif |
| 438 | 920 | ||
| @@ -450,26 +932,13 @@ arch_initcall(omap2_clk_arch_init); | |||
| 450 | int __init omap2_clk_init(void) | 932 | int __init omap2_clk_init(void) |
| 451 | { | 933 | { |
| 452 | /* struct prcm_config *prcm; */ | 934 | /* struct prcm_config *prcm; */ |
| 453 | struct clk **clkp; | 935 | struct omap_clk *c; |
| 454 | /* u32 clkrate; */ | 936 | /* u32 clkrate; */ |
| 455 | u32 cpu_clkflg; | 937 | u32 cpu_clkflg; |
| 456 | 938 | ||
| 457 | /* REVISIT: Ultimately this will be used for multiboot */ | ||
| 458 | #if 0 | ||
| 459 | if (cpu_is_omap242x()) { | ||
| 460 | cpu_mask = RATE_IN_242X; | ||
| 461 | cpu_clkflg = CLOCK_IN_OMAP242X; | ||
| 462 | clkp = onchip_24xx_clks; | ||
| 463 | } else if (cpu_is_omap2430()) { | ||
| 464 | cpu_mask = RATE_IN_243X; | ||
| 465 | cpu_clkflg = CLOCK_IN_OMAP243X; | ||
| 466 | clkp = onchip_24xx_clks; | ||
| 467 | } | ||
| 468 | #endif | ||
| 469 | if (cpu_is_omap34xx()) { | 939 | if (cpu_is_omap34xx()) { |
| 470 | cpu_mask = RATE_IN_343X; | 940 | cpu_mask = RATE_IN_343X; |
| 471 | cpu_clkflg = CLOCK_IN_OMAP343X; | 941 | cpu_clkflg = CK_343X; |
| 472 | clkp = onchip_34xx_clks; | ||
| 473 | 942 | ||
| 474 | /* | 943 | /* |
| 475 | * Update this if there are further clock changes between ES2 | 944 | * Update this if there are further clock changes between ES2 |
| @@ -477,23 +946,24 @@ int __init omap2_clk_init(void) | |||
| 477 | */ | 946 | */ |
| 478 | if (omap_rev() == OMAP3430_REV_ES1_0) { | 947 | if (omap_rev() == OMAP3430_REV_ES1_0) { |
| 479 | /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ | 948 | /* No 3430ES1-only rates exist, so no RATE_IN_3430ES1 */ |
| 480 | cpu_clkflg |= CLOCK_IN_OMAP3430ES1; | 949 | cpu_clkflg |= CK_3430ES1; |
| 481 | } else { | 950 | } else { |
| 482 | cpu_mask |= RATE_IN_3430ES2; | 951 | cpu_mask |= RATE_IN_3430ES2; |
| 483 | cpu_clkflg |= CLOCK_IN_OMAP3430ES2; | 952 | cpu_clkflg |= CK_3430ES2; |
| 484 | } | 953 | } |
| 485 | } | 954 | } |
| 486 | 955 | ||
| 487 | clk_init(&omap2_clk_functions); | 956 | clk_init(&omap2_clk_functions); |
| 488 | 957 | ||
| 489 | for (clkp = onchip_34xx_clks; | 958 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) |
| 490 | clkp < onchip_34xx_clks + ARRAY_SIZE(onchip_34xx_clks); | 959 | clk_init_one(c->lk.clk); |
| 491 | clkp++) { | 960 | |
| 492 | if ((*clkp)->flags & cpu_clkflg) { | 961 | for (c = omap34xx_clks; c < omap34xx_clks + ARRAY_SIZE(omap34xx_clks); c++) |
| 493 | clk_register(*clkp); | 962 | if (c->cpu & cpu_clkflg) { |
| 494 | omap2_init_clk_clkdm(*clkp); | 963 | clkdev_add(&c->lk); |
| 964 | clk_register(c->lk.clk); | ||
| 965 | omap2_init_clk_clkdm(c->lk.clk); | ||
| 495 | } | 966 | } |
| 496 | } | ||
| 497 | 967 | ||
| 498 | /* REVISIT: Not yet ready for OMAP3 */ | 968 | /* REVISIT: Not yet ready for OMAP3 */ |
| 499 | #if 0 | 969 | #if 0 |
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h index a826094d89b5..70ec10deb654 100644 --- a/arch/arm/mach-omap2/clock34xx.h +++ b/arch/arm/mach-omap2/clock34xx.h | |||
| @@ -27,13 +27,14 @@ | |||
| 27 | #include "prm.h" | 27 | #include "prm.h" |
| 28 | #include "prm-regbits-34xx.h" | 28 | #include "prm-regbits-34xx.h" |
| 29 | 29 | ||
| 30 | static void omap3_dpll_recalc(struct clk *clk); | 30 | static unsigned long omap3_dpll_recalc(struct clk *clk); |
| 31 | static void omap3_clkoutx2_recalc(struct clk *clk); | 31 | static unsigned long omap3_clkoutx2_recalc(struct clk *clk); |
| 32 | static void omap3_dpll_allow_idle(struct clk *clk); | 32 | static void omap3_dpll_allow_idle(struct clk *clk); |
| 33 | static void omap3_dpll_deny_idle(struct clk *clk); | 33 | static void omap3_dpll_deny_idle(struct clk *clk); |
| 34 | static u32 omap3_dpll_autoidle_read(struct clk *clk); | 34 | static u32 omap3_dpll_autoidle_read(struct clk *clk); |
| 35 | static int omap3_noncore_dpll_enable(struct clk *clk); | 35 | static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); |
| 36 | static void omap3_noncore_dpll_disable(struct clk *clk); | 36 | static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); |
| 37 | static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); | ||
| 37 | 38 | ||
| 38 | /* Maximum DPLL multiplier, divider values for OMAP3 */ | 39 | /* Maximum DPLL multiplier, divider values for OMAP3 */ |
| 39 | #define OMAP3_MAX_DPLL_MULT 2048 | 40 | #define OMAP3_MAX_DPLL_MULT 2048 |
| @@ -47,6 +48,10 @@ static void omap3_noncore_dpll_disable(struct clk *clk); | |||
| 47 | * DPLL5 supplies other peripheral clocks (USBHOST, USIM). | 48 | * DPLL5 supplies other peripheral clocks (USBHOST, USIM). |
| 48 | */ | 49 | */ |
| 49 | 50 | ||
| 51 | /* Forward declarations for DPLL bypass clocks */ | ||
| 52 | static struct clk dpll1_fck; | ||
| 53 | static struct clk dpll2_fck; | ||
| 54 | |||
| 50 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ | 55 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
| 51 | #define DPLL_LOW_POWER_STOP 0x1 | 56 | #define DPLL_LOW_POWER_STOP 0x1 |
| 52 | #define DPLL_LOW_POWER_BYPASS 0x5 | 57 | #define DPLL_LOW_POWER_BYPASS 0x5 |
| @@ -57,67 +62,59 @@ static void omap3_noncore_dpll_disable(struct clk *clk); | |||
| 57 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ | 62 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ |
| 58 | static struct clk omap_32k_fck = { | 63 | static struct clk omap_32k_fck = { |
| 59 | .name = "omap_32k_fck", | 64 | .name = "omap_32k_fck", |
| 65 | .ops = &clkops_null, | ||
| 60 | .rate = 32768, | 66 | .rate = 32768, |
| 61 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 67 | .flags = RATE_FIXED, |
| 62 | ALWAYS_ENABLED, | ||
| 63 | .recalc = &propagate_rate, | ||
| 64 | }; | 68 | }; |
| 65 | 69 | ||
| 66 | static struct clk secure_32k_fck = { | 70 | static struct clk secure_32k_fck = { |
| 67 | .name = "secure_32k_fck", | 71 | .name = "secure_32k_fck", |
| 72 | .ops = &clkops_null, | ||
| 68 | .rate = 32768, | 73 | .rate = 32768, |
| 69 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 74 | .flags = RATE_FIXED, |
| 70 | ALWAYS_ENABLED, | ||
| 71 | .recalc = &propagate_rate, | ||
| 72 | }; | 75 | }; |
| 73 | 76 | ||
| 74 | /* Virtual source clocks for osc_sys_ck */ | 77 | /* Virtual source clocks for osc_sys_ck */ |
| 75 | static struct clk virt_12m_ck = { | 78 | static struct clk virt_12m_ck = { |
| 76 | .name = "virt_12m_ck", | 79 | .name = "virt_12m_ck", |
| 80 | .ops = &clkops_null, | ||
| 77 | .rate = 12000000, | 81 | .rate = 12000000, |
| 78 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 82 | .flags = RATE_FIXED, |
| 79 | ALWAYS_ENABLED, | ||
| 80 | .recalc = &propagate_rate, | ||
| 81 | }; | 83 | }; |
| 82 | 84 | ||
| 83 | static struct clk virt_13m_ck = { | 85 | static struct clk virt_13m_ck = { |
| 84 | .name = "virt_13m_ck", | 86 | .name = "virt_13m_ck", |
| 87 | .ops = &clkops_null, | ||
| 85 | .rate = 13000000, | 88 | .rate = 13000000, |
| 86 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 89 | .flags = RATE_FIXED, |
| 87 | ALWAYS_ENABLED, | ||
| 88 | .recalc = &propagate_rate, | ||
| 89 | }; | 90 | }; |
| 90 | 91 | ||
| 91 | static struct clk virt_16_8m_ck = { | 92 | static struct clk virt_16_8m_ck = { |
| 92 | .name = "virt_16_8m_ck", | 93 | .name = "virt_16_8m_ck", |
| 94 | .ops = &clkops_null, | ||
| 93 | .rate = 16800000, | 95 | .rate = 16800000, |
| 94 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES | | 96 | .flags = RATE_FIXED, |
| 95 | ALWAYS_ENABLED, | ||
| 96 | .recalc = &propagate_rate, | ||
| 97 | }; | 97 | }; |
| 98 | 98 | ||
| 99 | static struct clk virt_19_2m_ck = { | 99 | static struct clk virt_19_2m_ck = { |
| 100 | .name = "virt_19_2m_ck", | 100 | .name = "virt_19_2m_ck", |
| 101 | .ops = &clkops_null, | ||
| 101 | .rate = 19200000, | 102 | .rate = 19200000, |
| 102 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 103 | .flags = RATE_FIXED, |
| 103 | ALWAYS_ENABLED, | ||
| 104 | .recalc = &propagate_rate, | ||
| 105 | }; | 104 | }; |
| 106 | 105 | ||
| 107 | static struct clk virt_26m_ck = { | 106 | static struct clk virt_26m_ck = { |
| 108 | .name = "virt_26m_ck", | 107 | .name = "virt_26m_ck", |
| 108 | .ops = &clkops_null, | ||
| 109 | .rate = 26000000, | 109 | .rate = 26000000, |
| 110 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 110 | .flags = RATE_FIXED, |
| 111 | ALWAYS_ENABLED, | ||
| 112 | .recalc = &propagate_rate, | ||
| 113 | }; | 111 | }; |
| 114 | 112 | ||
| 115 | static struct clk virt_38_4m_ck = { | 113 | static struct clk virt_38_4m_ck = { |
| 116 | .name = "virt_38_4m_ck", | 114 | .name = "virt_38_4m_ck", |
| 115 | .ops = &clkops_null, | ||
| 117 | .rate = 38400000, | 116 | .rate = 38400000, |
| 118 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 117 | .flags = RATE_FIXED, |
| 119 | ALWAYS_ENABLED, | ||
| 120 | .recalc = &propagate_rate, | ||
| 121 | }; | 118 | }; |
| 122 | 119 | ||
| 123 | static const struct clksel_rate osc_sys_12m_rates[] = { | 120 | static const struct clksel_rate osc_sys_12m_rates[] = { |
| @@ -164,13 +161,13 @@ static const struct clksel osc_sys_clksel[] = { | |||
| 164 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ | 161 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ |
| 165 | static struct clk osc_sys_ck = { | 162 | static struct clk osc_sys_ck = { |
| 166 | .name = "osc_sys_ck", | 163 | .name = "osc_sys_ck", |
| 164 | .ops = &clkops_null, | ||
| 167 | .init = &omap2_init_clksel_parent, | 165 | .init = &omap2_init_clksel_parent, |
| 168 | .clksel_reg = OMAP3430_PRM_CLKSEL, | 166 | .clksel_reg = OMAP3430_PRM_CLKSEL, |
| 169 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, | 167 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, |
| 170 | .clksel = osc_sys_clksel, | 168 | .clksel = osc_sys_clksel, |
| 171 | /* REVISIT: deal with autoextclkmode? */ | 169 | /* REVISIT: deal with autoextclkmode? */ |
| 172 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | 170 | .flags = RATE_FIXED, |
| 173 | ALWAYS_ENABLED, | ||
| 174 | .recalc = &omap2_clksel_recalc, | 171 | .recalc = &omap2_clksel_recalc, |
| 175 | }; | 172 | }; |
| 176 | 173 | ||
| @@ -189,36 +186,34 @@ static const struct clksel sys_clksel[] = { | |||
| 189 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ | 186 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ |
| 190 | static struct clk sys_ck = { | 187 | static struct clk sys_ck = { |
| 191 | .name = "sys_ck", | 188 | .name = "sys_ck", |
| 189 | .ops = &clkops_null, | ||
| 192 | .parent = &osc_sys_ck, | 190 | .parent = &osc_sys_ck, |
| 193 | .init = &omap2_init_clksel_parent, | 191 | .init = &omap2_init_clksel_parent, |
| 194 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, | 192 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, |
| 195 | .clksel_mask = OMAP_SYSCLKDIV_MASK, | 193 | .clksel_mask = OMAP_SYSCLKDIV_MASK, |
| 196 | .clksel = sys_clksel, | 194 | .clksel = sys_clksel, |
| 197 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 198 | .recalc = &omap2_clksel_recalc, | 195 | .recalc = &omap2_clksel_recalc, |
| 199 | }; | 196 | }; |
| 200 | 197 | ||
| 201 | static struct clk sys_altclk = { | 198 | static struct clk sys_altclk = { |
| 202 | .name = "sys_altclk", | 199 | .name = "sys_altclk", |
| 203 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 200 | .ops = &clkops_null, |
| 204 | .recalc = &propagate_rate, | ||
| 205 | }; | 201 | }; |
| 206 | 202 | ||
| 207 | /* Optional external clock input for some McBSPs */ | 203 | /* Optional external clock input for some McBSPs */ |
| 208 | static struct clk mcbsp_clks = { | 204 | static struct clk mcbsp_clks = { |
| 209 | .name = "mcbsp_clks", | 205 | .name = "mcbsp_clks", |
| 210 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | 206 | .ops = &clkops_null, |
| 211 | .recalc = &propagate_rate, | ||
| 212 | }; | 207 | }; |
| 213 | 208 | ||
| 214 | /* PRM EXTERNAL CLOCK OUTPUT */ | 209 | /* PRM EXTERNAL CLOCK OUTPUT */ |
| 215 | 210 | ||
| 216 | static struct clk sys_clkout1 = { | 211 | static struct clk sys_clkout1 = { |
| 217 | .name = "sys_clkout1", | 212 | .name = "sys_clkout1", |
| 213 | .ops = &clkops_omap2_dflt, | ||
| 218 | .parent = &osc_sys_ck, | 214 | .parent = &osc_sys_ck, |
| 219 | .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, | 215 | .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, |
| 220 | .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, | 216 | .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, |
| 221 | .flags = CLOCK_IN_OMAP343X, | ||
| 222 | .recalc = &followparent_recalc, | 217 | .recalc = &followparent_recalc, |
| 223 | }; | 218 | }; |
| 224 | 219 | ||
| @@ -226,16 +221,6 @@ static struct clk sys_clkout1 = { | |||
| 226 | 221 | ||
| 227 | /* CM CLOCKS */ | 222 | /* CM CLOCKS */ |
| 228 | 223 | ||
| 229 | static const struct clksel_rate dpll_bypass_rates[] = { | ||
| 230 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 231 | { .div = 0 } | ||
| 232 | }; | ||
| 233 | |||
| 234 | static const struct clksel_rate dpll_locked_rates[] = { | ||
| 235 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 236 | { .div = 0 } | ||
| 237 | }; | ||
| 238 | |||
| 239 | static const struct clksel_rate div16_dpll_rates[] = { | 224 | static const struct clksel_rate div16_dpll_rates[] = { |
| 240 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | 225 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 241 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | 226 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, |
| @@ -263,6 +248,9 @@ static struct dpll_data dpll1_dd = { | |||
| 263 | .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | 248 | .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 264 | .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, | 249 | .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, |
| 265 | .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, | 250 | .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, |
| 251 | .clk_bypass = &dpll1_fck, | ||
| 252 | .clk_ref = &sys_ck, | ||
| 253 | .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, | ||
| 266 | .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), | 254 | .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), |
| 267 | .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, | 255 | .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, |
| 268 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), | 256 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
| @@ -272,18 +260,21 @@ static struct dpll_data dpll1_dd = { | |||
| 272 | .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), | 260 | .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
| 273 | .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, | 261 | .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, |
| 274 | .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | 262 | .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), |
| 275 | .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT, | 263 | .idlest_mask = OMAP3430_ST_MPU_CLK_MASK, |
| 276 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | 264 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 265 | .min_divider = 1, | ||
| 277 | .max_divider = OMAP3_MAX_DPLL_DIV, | 266 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 278 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | 267 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
| 279 | }; | 268 | }; |
| 280 | 269 | ||
| 281 | static struct clk dpll1_ck = { | 270 | static struct clk dpll1_ck = { |
| 282 | .name = "dpll1_ck", | 271 | .name = "dpll1_ck", |
| 272 | .ops = &clkops_null, | ||
| 283 | .parent = &sys_ck, | 273 | .parent = &sys_ck, |
| 284 | .dpll_data = &dpll1_dd, | 274 | .dpll_data = &dpll1_dd, |
| 285 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 286 | .round_rate = &omap2_dpll_round_rate, | 275 | .round_rate = &omap2_dpll_round_rate, |
| 276 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
| 277 | .clkdm_name = "dpll1_clkdm", | ||
| 287 | .recalc = &omap3_dpll_recalc, | 278 | .recalc = &omap3_dpll_recalc, |
| 288 | }; | 279 | }; |
| 289 | 280 | ||
| @@ -293,9 +284,9 @@ static struct clk dpll1_ck = { | |||
| 293 | */ | 284 | */ |
| 294 | static struct clk dpll1_x2_ck = { | 285 | static struct clk dpll1_x2_ck = { |
| 295 | .name = "dpll1_x2_ck", | 286 | .name = "dpll1_x2_ck", |
| 287 | .ops = &clkops_null, | ||
| 296 | .parent = &dpll1_ck, | 288 | .parent = &dpll1_ck, |
| 297 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 289 | .clkdm_name = "dpll1_clkdm", |
| 298 | PARENT_CONTROLS_CLOCK, | ||
| 299 | .recalc = &omap3_clkoutx2_recalc, | 290 | .recalc = &omap3_clkoutx2_recalc, |
| 300 | }; | 291 | }; |
| 301 | 292 | ||
| @@ -311,13 +302,13 @@ static const struct clksel div16_dpll1_x2m2_clksel[] = { | |||
| 311 | */ | 302 | */ |
| 312 | static struct clk dpll1_x2m2_ck = { | 303 | static struct clk dpll1_x2m2_ck = { |
| 313 | .name = "dpll1_x2m2_ck", | 304 | .name = "dpll1_x2m2_ck", |
| 305 | .ops = &clkops_null, | ||
| 314 | .parent = &dpll1_x2_ck, | 306 | .parent = &dpll1_x2_ck, |
| 315 | .init = &omap2_init_clksel_parent, | 307 | .init = &omap2_init_clksel_parent, |
| 316 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), | 308 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), |
| 317 | .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, | 309 | .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, |
| 318 | .clksel = div16_dpll1_x2m2_clksel, | 310 | .clksel = div16_dpll1_x2m2_clksel, |
| 319 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 311 | .clkdm_name = "dpll1_clkdm", |
| 320 | PARENT_CONTROLS_CLOCK, | ||
| 321 | .recalc = &omap2_clksel_recalc, | 312 | .recalc = &omap2_clksel_recalc, |
| 322 | }; | 313 | }; |
| 323 | 314 | ||
| @@ -329,6 +320,9 @@ static struct dpll_data dpll2_dd = { | |||
| 329 | .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | 320 | .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 330 | .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, | 321 | .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, |
| 331 | .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, | 322 | .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, |
| 323 | .clk_bypass = &dpll2_fck, | ||
| 324 | .clk_ref = &sys_ck, | ||
| 325 | .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, | ||
| 332 | .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), | 326 | .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), |
| 333 | .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, | 327 | .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, |
| 334 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | | 328 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | |
| @@ -339,20 +333,21 @@ static struct dpll_data dpll2_dd = { | |||
| 339 | .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), | 333 | .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
| 340 | .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, | 334 | .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, |
| 341 | .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), | 335 | .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), |
| 342 | .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT, | 336 | .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK, |
| 343 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | 337 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 338 | .min_divider = 1, | ||
| 344 | .max_divider = OMAP3_MAX_DPLL_DIV, | 339 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 345 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | 340 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
| 346 | }; | 341 | }; |
| 347 | 342 | ||
| 348 | static struct clk dpll2_ck = { | 343 | static struct clk dpll2_ck = { |
| 349 | .name = "dpll2_ck", | 344 | .name = "dpll2_ck", |
| 345 | .ops = &clkops_noncore_dpll_ops, | ||
| 350 | .parent = &sys_ck, | 346 | .parent = &sys_ck, |
| 351 | .dpll_data = &dpll2_dd, | 347 | .dpll_data = &dpll2_dd, |
| 352 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 353 | .enable = &omap3_noncore_dpll_enable, | ||
| 354 | .disable = &omap3_noncore_dpll_disable, | ||
| 355 | .round_rate = &omap2_dpll_round_rate, | 348 | .round_rate = &omap2_dpll_round_rate, |
| 349 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
| 350 | .clkdm_name = "dpll2_clkdm", | ||
| 356 | .recalc = &omap3_dpll_recalc, | 351 | .recalc = &omap3_dpll_recalc, |
| 357 | }; | 352 | }; |
| 358 | 353 | ||
| @@ -367,14 +362,14 @@ static const struct clksel div16_dpll2_m2x2_clksel[] = { | |||
| 367 | */ | 362 | */ |
| 368 | static struct clk dpll2_m2_ck = { | 363 | static struct clk dpll2_m2_ck = { |
| 369 | .name = "dpll2_m2_ck", | 364 | .name = "dpll2_m2_ck", |
| 365 | .ops = &clkops_null, | ||
| 370 | .parent = &dpll2_ck, | 366 | .parent = &dpll2_ck, |
| 371 | .init = &omap2_init_clksel_parent, | 367 | .init = &omap2_init_clksel_parent, |
| 372 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, | 368 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, |
| 373 | OMAP3430_CM_CLKSEL2_PLL), | 369 | OMAP3430_CM_CLKSEL2_PLL), |
| 374 | .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, | 370 | .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, |
| 375 | .clksel = div16_dpll2_m2x2_clksel, | 371 | .clksel = div16_dpll2_m2x2_clksel, |
| 376 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 372 | .clkdm_name = "dpll2_clkdm", |
| 377 | PARENT_CONTROLS_CLOCK, | ||
| 378 | .recalc = &omap2_clksel_recalc, | 373 | .recalc = &omap2_clksel_recalc, |
| 379 | }; | 374 | }; |
| 380 | 375 | ||
| @@ -387,6 +382,9 @@ static struct dpll_data dpll3_dd = { | |||
| 387 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 382 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 388 | .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, | 383 | .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, |
| 389 | .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, | 384 | .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, |
| 385 | .clk_bypass = &sys_ck, | ||
| 386 | .clk_ref = &sys_ck, | ||
| 387 | .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, | ||
| 390 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 388 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 391 | .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, | 389 | .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, |
| 392 | .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, | 390 | .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, |
| @@ -394,17 +392,21 @@ static struct dpll_data dpll3_dd = { | |||
| 394 | .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, | 392 | .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, |
| 395 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), | 393 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
| 396 | .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, | 394 | .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, |
| 395 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 396 | .idlest_mask = OMAP3430_ST_CORE_CLK_MASK, | ||
| 397 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | 397 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 398 | .min_divider = 1, | ||
| 398 | .max_divider = OMAP3_MAX_DPLL_DIV, | 399 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 399 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | 400 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
| 400 | }; | 401 | }; |
| 401 | 402 | ||
| 402 | static struct clk dpll3_ck = { | 403 | static struct clk dpll3_ck = { |
| 403 | .name = "dpll3_ck", | 404 | .name = "dpll3_ck", |
| 405 | .ops = &clkops_null, | ||
| 404 | .parent = &sys_ck, | 406 | .parent = &sys_ck, |
| 405 | .dpll_data = &dpll3_dd, | 407 | .dpll_data = &dpll3_dd, |
| 406 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 407 | .round_rate = &omap2_dpll_round_rate, | 408 | .round_rate = &omap2_dpll_round_rate, |
| 409 | .clkdm_name = "dpll3_clkdm", | ||
| 408 | .recalc = &omap3_dpll_recalc, | 410 | .recalc = &omap3_dpll_recalc, |
| 409 | }; | 411 | }; |
| 410 | 412 | ||
| @@ -414,9 +416,9 @@ static struct clk dpll3_ck = { | |||
| 414 | */ | 416 | */ |
| 415 | static struct clk dpll3_x2_ck = { | 417 | static struct clk dpll3_x2_ck = { |
| 416 | .name = "dpll3_x2_ck", | 418 | .name = "dpll3_x2_ck", |
| 419 | .ops = &clkops_null, | ||
| 417 | .parent = &dpll3_ck, | 420 | .parent = &dpll3_ck, |
| 418 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 421 | .clkdm_name = "dpll3_clkdm", |
| 419 | PARENT_CONTROLS_CLOCK, | ||
| 420 | .recalc = &omap3_clkoutx2_recalc, | 422 | .recalc = &omap3_clkoutx2_recalc, |
| 421 | }; | 423 | }; |
| 422 | 424 | ||
| @@ -460,55 +462,34 @@ static const struct clksel div31_dpll3m2_clksel[] = { | |||
| 460 | { .parent = NULL } | 462 | { .parent = NULL } |
| 461 | }; | 463 | }; |
| 462 | 464 | ||
| 463 | /* | 465 | /* DPLL3 output M2 - primary control point for CORE speed */ |
| 464 | * DPLL3 output M2 | ||
| 465 | * REVISIT: This DPLL output divider must be changed in SRAM, so until | ||
| 466 | * that code is ready, this should remain a 'read-only' clksel clock. | ||
| 467 | */ | ||
| 468 | static struct clk dpll3_m2_ck = { | 466 | static struct clk dpll3_m2_ck = { |
| 469 | .name = "dpll3_m2_ck", | 467 | .name = "dpll3_m2_ck", |
| 468 | .ops = &clkops_null, | ||
| 470 | .parent = &dpll3_ck, | 469 | .parent = &dpll3_ck, |
| 471 | .init = &omap2_init_clksel_parent, | 470 | .init = &omap2_init_clksel_parent, |
| 472 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 471 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 473 | .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, | 472 | .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, |
| 474 | .clksel = div31_dpll3m2_clksel, | 473 | .clksel = div31_dpll3m2_clksel, |
| 475 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 474 | .clkdm_name = "dpll3_clkdm", |
| 476 | PARENT_CONTROLS_CLOCK, | 475 | .round_rate = &omap2_clksel_round_rate, |
| 476 | .set_rate = &omap3_core_dpll_m2_set_rate, | ||
| 477 | .recalc = &omap2_clksel_recalc, | 477 | .recalc = &omap2_clksel_recalc, |
| 478 | }; | 478 | }; |
| 479 | 479 | ||
| 480 | static const struct clksel core_ck_clksel[] = { | ||
| 481 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 482 | { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, | ||
| 483 | { .parent = NULL } | ||
| 484 | }; | ||
| 485 | |||
| 486 | static struct clk core_ck = { | 480 | static struct clk core_ck = { |
| 487 | .name = "core_ck", | 481 | .name = "core_ck", |
| 488 | .init = &omap2_init_clksel_parent, | 482 | .ops = &clkops_null, |
| 489 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | 483 | .parent = &dpll3_m2_ck, |
| 490 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, | 484 | .recalc = &followparent_recalc, |
| 491 | .clksel = core_ck_clksel, | ||
| 492 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 493 | PARENT_CONTROLS_CLOCK, | ||
| 494 | .recalc = &omap2_clksel_recalc, | ||
| 495 | }; | ||
| 496 | |||
| 497 | static const struct clksel dpll3_m2x2_ck_clksel[] = { | ||
| 498 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 499 | { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, | ||
| 500 | { .parent = NULL } | ||
| 501 | }; | 485 | }; |
| 502 | 486 | ||
| 503 | static struct clk dpll3_m2x2_ck = { | 487 | static struct clk dpll3_m2x2_ck = { |
| 504 | .name = "dpll3_m2x2_ck", | 488 | .name = "dpll3_m2x2_ck", |
| 505 | .init = &omap2_init_clksel_parent, | 489 | .ops = &clkops_null, |
| 506 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | 490 | .parent = &dpll3_x2_ck, |
| 507 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, | 491 | .clkdm_name = "dpll3_clkdm", |
| 508 | .clksel = dpll3_m2x2_ck_clksel, | 492 | .recalc = &followparent_recalc, |
| 509 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 510 | PARENT_CONTROLS_CLOCK, | ||
| 511 | .recalc = &omap2_clksel_recalc, | ||
| 512 | }; | 493 | }; |
| 513 | 494 | ||
| 514 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 495 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| @@ -520,42 +501,34 @@ static const struct clksel div16_dpll3_clksel[] = { | |||
| 520 | /* This virtual clock is the source for dpll3_m3x2_ck */ | 501 | /* This virtual clock is the source for dpll3_m3x2_ck */ |
| 521 | static struct clk dpll3_m3_ck = { | 502 | static struct clk dpll3_m3_ck = { |
| 522 | .name = "dpll3_m3_ck", | 503 | .name = "dpll3_m3_ck", |
| 504 | .ops = &clkops_null, | ||
| 523 | .parent = &dpll3_ck, | 505 | .parent = &dpll3_ck, |
| 524 | .init = &omap2_init_clksel_parent, | 506 | .init = &omap2_init_clksel_parent, |
| 525 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 507 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 526 | .clksel_mask = OMAP3430_DIV_DPLL3_MASK, | 508 | .clksel_mask = OMAP3430_DIV_DPLL3_MASK, |
| 527 | .clksel = div16_dpll3_clksel, | 509 | .clksel = div16_dpll3_clksel, |
| 528 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 510 | .clkdm_name = "dpll3_clkdm", |
| 529 | PARENT_CONTROLS_CLOCK, | ||
| 530 | .recalc = &omap2_clksel_recalc, | 511 | .recalc = &omap2_clksel_recalc, |
| 531 | }; | 512 | }; |
| 532 | 513 | ||
| 533 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 514 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 534 | static struct clk dpll3_m3x2_ck = { | 515 | static struct clk dpll3_m3x2_ck = { |
| 535 | .name = "dpll3_m3x2_ck", | 516 | .name = "dpll3_m3x2_ck", |
| 517 | .ops = &clkops_omap2_dflt_wait, | ||
| 536 | .parent = &dpll3_m3_ck, | 518 | .parent = &dpll3_m3_ck, |
| 537 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 519 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 538 | .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, | 520 | .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, |
| 539 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | 521 | .flags = INVERT_ENABLE, |
| 522 | .clkdm_name = "dpll3_clkdm", | ||
| 540 | .recalc = &omap3_clkoutx2_recalc, | 523 | .recalc = &omap3_clkoutx2_recalc, |
| 541 | }; | 524 | }; |
| 542 | 525 | ||
| 543 | static const struct clksel emu_core_alwon_ck_clksel[] = { | ||
| 544 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 545 | { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, | ||
| 546 | { .parent = NULL } | ||
| 547 | }; | ||
| 548 | |||
| 549 | static struct clk emu_core_alwon_ck = { | 526 | static struct clk emu_core_alwon_ck = { |
| 550 | .name = "emu_core_alwon_ck", | 527 | .name = "emu_core_alwon_ck", |
| 528 | .ops = &clkops_null, | ||
| 551 | .parent = &dpll3_m3x2_ck, | 529 | .parent = &dpll3_m3x2_ck, |
| 552 | .init = &omap2_init_clksel_parent, | 530 | .clkdm_name = "dpll3_clkdm", |
| 553 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | 531 | .recalc = &followparent_recalc, |
| 554 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, | ||
| 555 | .clksel = emu_core_alwon_ck_clksel, | ||
| 556 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 557 | PARENT_CONTROLS_CLOCK, | ||
| 558 | .recalc = &omap2_clksel_recalc, | ||
| 559 | }; | 532 | }; |
| 560 | 533 | ||
| 561 | /* DPLL4 */ | 534 | /* DPLL4 */ |
| @@ -565,6 +538,9 @@ static struct dpll_data dpll4_dd = { | |||
| 565 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), | 538 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), |
| 566 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, | 539 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, |
| 567 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, | 540 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, |
| 541 | .clk_bypass = &sys_ck, | ||
| 542 | .clk_ref = &sys_ck, | ||
| 543 | .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, | ||
| 568 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 544 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 569 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, | 545 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, |
| 570 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), | 546 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
| @@ -574,20 +550,21 @@ static struct dpll_data dpll4_dd = { | |||
| 574 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), | 550 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
| 575 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, | 551 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, |
| 576 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | 552 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
| 577 | .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT, | 553 | .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
| 578 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | 554 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 555 | .min_divider = 1, | ||
| 579 | .max_divider = OMAP3_MAX_DPLL_DIV, | 556 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 580 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | 557 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
| 581 | }; | 558 | }; |
| 582 | 559 | ||
| 583 | static struct clk dpll4_ck = { | 560 | static struct clk dpll4_ck = { |
| 584 | .name = "dpll4_ck", | 561 | .name = "dpll4_ck", |
| 562 | .ops = &clkops_noncore_dpll_ops, | ||
| 585 | .parent = &sys_ck, | 563 | .parent = &sys_ck, |
| 586 | .dpll_data = &dpll4_dd, | 564 | .dpll_data = &dpll4_dd, |
| 587 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 588 | .enable = &omap3_noncore_dpll_enable, | ||
| 589 | .disable = &omap3_noncore_dpll_disable, | ||
| 590 | .round_rate = &omap2_dpll_round_rate, | 565 | .round_rate = &omap2_dpll_round_rate, |
| 566 | .set_rate = &omap3_dpll4_set_rate, | ||
| 567 | .clkdm_name = "dpll4_clkdm", | ||
| 591 | .recalc = &omap3_dpll_recalc, | 568 | .recalc = &omap3_dpll_recalc, |
| 592 | }; | 569 | }; |
| 593 | 570 | ||
| @@ -598,9 +575,9 @@ static struct clk dpll4_ck = { | |||
| 598 | */ | 575 | */ |
| 599 | static struct clk dpll4_x2_ck = { | 576 | static struct clk dpll4_x2_ck = { |
| 600 | .name = "dpll4_x2_ck", | 577 | .name = "dpll4_x2_ck", |
| 578 | .ops = &clkops_null, | ||
| 601 | .parent = &dpll4_ck, | 579 | .parent = &dpll4_ck, |
| 602 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 580 | .clkdm_name = "dpll4_clkdm", |
| 603 | PARENT_CONTROLS_CLOCK, | ||
| 604 | .recalc = &omap3_clkoutx2_recalc, | 581 | .recalc = &omap3_clkoutx2_recalc, |
| 605 | }; | 582 | }; |
| 606 | 583 | ||
| @@ -612,112 +589,101 @@ static const struct clksel div16_dpll4_clksel[] = { | |||
| 612 | /* This virtual clock is the source for dpll4_m2x2_ck */ | 589 | /* This virtual clock is the source for dpll4_m2x2_ck */ |
| 613 | static struct clk dpll4_m2_ck = { | 590 | static struct clk dpll4_m2_ck = { |
| 614 | .name = "dpll4_m2_ck", | 591 | .name = "dpll4_m2_ck", |
| 592 | .ops = &clkops_null, | ||
| 615 | .parent = &dpll4_ck, | 593 | .parent = &dpll4_ck, |
| 616 | .init = &omap2_init_clksel_parent, | 594 | .init = &omap2_init_clksel_parent, |
| 617 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), | 595 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), |
| 618 | .clksel_mask = OMAP3430_DIV_96M_MASK, | 596 | .clksel_mask = OMAP3430_DIV_96M_MASK, |
| 619 | .clksel = div16_dpll4_clksel, | 597 | .clksel = div16_dpll4_clksel, |
| 620 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 598 | .clkdm_name = "dpll4_clkdm", |
| 621 | PARENT_CONTROLS_CLOCK, | ||
| 622 | .recalc = &omap2_clksel_recalc, | 599 | .recalc = &omap2_clksel_recalc, |
| 623 | }; | 600 | }; |
| 624 | 601 | ||
| 625 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 602 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 626 | static struct clk dpll4_m2x2_ck = { | 603 | static struct clk dpll4_m2x2_ck = { |
| 627 | .name = "dpll4_m2x2_ck", | 604 | .name = "dpll4_m2x2_ck", |
| 605 | .ops = &clkops_omap2_dflt_wait, | ||
| 628 | .parent = &dpll4_m2_ck, | 606 | .parent = &dpll4_m2_ck, |
| 629 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 607 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 630 | .enable_bit = OMAP3430_PWRDN_96M_SHIFT, | 608 | .enable_bit = OMAP3430_PWRDN_96M_SHIFT, |
| 631 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | 609 | .flags = INVERT_ENABLE, |
| 610 | .clkdm_name = "dpll4_clkdm", | ||
| 632 | .recalc = &omap3_clkoutx2_recalc, | 611 | .recalc = &omap3_clkoutx2_recalc, |
| 633 | }; | 612 | }; |
| 634 | 613 | ||
| 635 | static const struct clksel omap_96m_alwon_fck_clksel[] = { | 614 | /* |
| 636 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | 615 | * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as |
| 637 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, | 616 | * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM: |
| 638 | { .parent = NULL } | 617 | * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and |
| 639 | }; | 618 | * CM_96K_(F)CLK. |
| 640 | 619 | */ | |
| 641 | static struct clk omap_96m_alwon_fck = { | 620 | static struct clk omap_96m_alwon_fck = { |
| 642 | .name = "omap_96m_alwon_fck", | 621 | .name = "omap_96m_alwon_fck", |
| 622 | .ops = &clkops_null, | ||
| 643 | .parent = &dpll4_m2x2_ck, | 623 | .parent = &dpll4_m2x2_ck, |
| 644 | .init = &omap2_init_clksel_parent, | 624 | .recalc = &followparent_recalc, |
| 645 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 646 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, | ||
| 647 | .clksel = omap_96m_alwon_fck_clksel, | ||
| 648 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 649 | PARENT_CONTROLS_CLOCK, | ||
| 650 | .recalc = &omap2_clksel_recalc, | ||
| 651 | }; | 625 | }; |
| 652 | 626 | ||
| 653 | static struct clk omap_96m_fck = { | 627 | static struct clk cm_96m_fck = { |
| 654 | .name = "omap_96m_fck", | 628 | .name = "cm_96m_fck", |
| 629 | .ops = &clkops_null, | ||
| 655 | .parent = &omap_96m_alwon_fck, | 630 | .parent = &omap_96m_alwon_fck, |
| 656 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 657 | PARENT_CONTROLS_CLOCK, | ||
| 658 | .recalc = &followparent_recalc, | 631 | .recalc = &followparent_recalc, |
| 659 | }; | 632 | }; |
| 660 | 633 | ||
| 661 | static const struct clksel cm_96m_fck_clksel[] = { | 634 | static const struct clksel_rate omap_96m_dpll_rates[] = { |
| 662 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | 635 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 663 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, | 636 | { .div = 0 } |
| 637 | }; | ||
| 638 | |||
| 639 | static const struct clksel_rate omap_96m_sys_rates[] = { | ||
| 640 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | ||
| 641 | { .div = 0 } | ||
| 642 | }; | ||
| 643 | |||
| 644 | static const struct clksel omap_96m_fck_clksel[] = { | ||
| 645 | { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, | ||
| 646 | { .parent = &sys_ck, .rates = omap_96m_sys_rates }, | ||
| 664 | { .parent = NULL } | 647 | { .parent = NULL } |
| 665 | }; | 648 | }; |
| 666 | 649 | ||
| 667 | static struct clk cm_96m_fck = { | 650 | static struct clk omap_96m_fck = { |
| 668 | .name = "cm_96m_fck", | 651 | .name = "omap_96m_fck", |
| 669 | .parent = &dpll4_m2x2_ck, | 652 | .ops = &clkops_null, |
| 653 | .parent = &sys_ck, | ||
| 670 | .init = &omap2_init_clksel_parent, | 654 | .init = &omap2_init_clksel_parent, |
| 671 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | 655 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 672 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, | 656 | .clksel_mask = OMAP3430_SOURCE_96M_MASK, |
| 673 | .clksel = cm_96m_fck_clksel, | 657 | .clksel = omap_96m_fck_clksel, |
| 674 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 675 | PARENT_CONTROLS_CLOCK, | ||
| 676 | .recalc = &omap2_clksel_recalc, | 658 | .recalc = &omap2_clksel_recalc, |
| 677 | }; | 659 | }; |
| 678 | 660 | ||
| 679 | /* This virtual clock is the source for dpll4_m3x2_ck */ | 661 | /* This virtual clock is the source for dpll4_m3x2_ck */ |
| 680 | static struct clk dpll4_m3_ck = { | 662 | static struct clk dpll4_m3_ck = { |
| 681 | .name = "dpll4_m3_ck", | 663 | .name = "dpll4_m3_ck", |
| 664 | .ops = &clkops_null, | ||
| 682 | .parent = &dpll4_ck, | 665 | .parent = &dpll4_ck, |
| 683 | .init = &omap2_init_clksel_parent, | 666 | .init = &omap2_init_clksel_parent, |
| 684 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | 667 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), |
| 685 | .clksel_mask = OMAP3430_CLKSEL_TV_MASK, | 668 | .clksel_mask = OMAP3430_CLKSEL_TV_MASK, |
| 686 | .clksel = div16_dpll4_clksel, | 669 | .clksel = div16_dpll4_clksel, |
| 687 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 670 | .clkdm_name = "dpll4_clkdm", |
| 688 | PARENT_CONTROLS_CLOCK, | ||
| 689 | .recalc = &omap2_clksel_recalc, | 671 | .recalc = &omap2_clksel_recalc, |
| 690 | }; | 672 | }; |
| 691 | 673 | ||
| 692 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 674 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 693 | static struct clk dpll4_m3x2_ck = { | 675 | static struct clk dpll4_m3x2_ck = { |
| 694 | .name = "dpll4_m3x2_ck", | 676 | .name = "dpll4_m3x2_ck", |
| 677 | .ops = &clkops_omap2_dflt_wait, | ||
| 695 | .parent = &dpll4_m3_ck, | 678 | .parent = &dpll4_m3_ck, |
| 696 | .init = &omap2_init_clksel_parent, | 679 | .init = &omap2_init_clksel_parent, |
| 697 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 680 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 698 | .enable_bit = OMAP3430_PWRDN_TV_SHIFT, | 681 | .enable_bit = OMAP3430_PWRDN_TV_SHIFT, |
| 699 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | 682 | .flags = INVERT_ENABLE, |
| 683 | .clkdm_name = "dpll4_clkdm", | ||
| 700 | .recalc = &omap3_clkoutx2_recalc, | 684 | .recalc = &omap3_clkoutx2_recalc, |
| 701 | }; | 685 | }; |
| 702 | 686 | ||
| 703 | static const struct clksel virt_omap_54m_fck_clksel[] = { | ||
| 704 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 705 | { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, | ||
| 706 | { .parent = NULL } | ||
| 707 | }; | ||
| 708 | |||
| 709 | static struct clk virt_omap_54m_fck = { | ||
| 710 | .name = "virt_omap_54m_fck", | ||
| 711 | .parent = &dpll4_m3x2_ck, | ||
| 712 | .init = &omap2_init_clksel_parent, | ||
| 713 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 714 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, | ||
| 715 | .clksel = virt_omap_54m_fck_clksel, | ||
| 716 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 717 | PARENT_CONTROLS_CLOCK, | ||
| 718 | .recalc = &omap2_clksel_recalc, | ||
| 719 | }; | ||
| 720 | |||
| 721 | static const struct clksel_rate omap_54m_d4m3x2_rates[] = { | 687 | static const struct clksel_rate omap_54m_d4m3x2_rates[] = { |
| 722 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | 688 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 723 | { .div = 0 } | 689 | { .div = 0 } |
| @@ -729,23 +695,22 @@ static const struct clksel_rate omap_54m_alt_rates[] = { | |||
| 729 | }; | 695 | }; |
| 730 | 696 | ||
| 731 | static const struct clksel omap_54m_clksel[] = { | 697 | static const struct clksel omap_54m_clksel[] = { |
| 732 | { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates }, | 698 | { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, |
| 733 | { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, | 699 | { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, |
| 734 | { .parent = NULL } | 700 | { .parent = NULL } |
| 735 | }; | 701 | }; |
| 736 | 702 | ||
| 737 | static struct clk omap_54m_fck = { | 703 | static struct clk omap_54m_fck = { |
| 738 | .name = "omap_54m_fck", | 704 | .name = "omap_54m_fck", |
| 705 | .ops = &clkops_null, | ||
| 739 | .init = &omap2_init_clksel_parent, | 706 | .init = &omap2_init_clksel_parent, |
| 740 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 707 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 741 | .clksel_mask = OMAP3430_SOURCE_54M, | 708 | .clksel_mask = OMAP3430_SOURCE_54M_MASK, |
| 742 | .clksel = omap_54m_clksel, | 709 | .clksel = omap_54m_clksel, |
| 743 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 744 | PARENT_CONTROLS_CLOCK, | ||
| 745 | .recalc = &omap2_clksel_recalc, | 710 | .recalc = &omap2_clksel_recalc, |
| 746 | }; | 711 | }; |
| 747 | 712 | ||
| 748 | static const struct clksel_rate omap_48m_96md2_rates[] = { | 713 | static const struct clksel_rate omap_48m_cm96m_rates[] = { |
| 749 | { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | 714 | { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 750 | { .div = 0 } | 715 | { .div = 0 } |
| 751 | }; | 716 | }; |
| @@ -756,106 +721,112 @@ static const struct clksel_rate omap_48m_alt_rates[] = { | |||
| 756 | }; | 721 | }; |
| 757 | 722 | ||
| 758 | static const struct clksel omap_48m_clksel[] = { | 723 | static const struct clksel omap_48m_clksel[] = { |
| 759 | { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates }, | 724 | { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates }, |
| 760 | { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, | 725 | { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, |
| 761 | { .parent = NULL } | 726 | { .parent = NULL } |
| 762 | }; | 727 | }; |
| 763 | 728 | ||
| 764 | static struct clk omap_48m_fck = { | 729 | static struct clk omap_48m_fck = { |
| 765 | .name = "omap_48m_fck", | 730 | .name = "omap_48m_fck", |
| 731 | .ops = &clkops_null, | ||
| 766 | .init = &omap2_init_clksel_parent, | 732 | .init = &omap2_init_clksel_parent, |
| 767 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 733 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
| 768 | .clksel_mask = OMAP3430_SOURCE_48M, | 734 | .clksel_mask = OMAP3430_SOURCE_48M_MASK, |
| 769 | .clksel = omap_48m_clksel, | 735 | .clksel = omap_48m_clksel, |
| 770 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 771 | PARENT_CONTROLS_CLOCK, | ||
| 772 | .recalc = &omap2_clksel_recalc, | 736 | .recalc = &omap2_clksel_recalc, |
| 773 | }; | 737 | }; |
| 774 | 738 | ||
| 775 | static struct clk omap_12m_fck = { | 739 | static struct clk omap_12m_fck = { |
| 776 | .name = "omap_12m_fck", | 740 | .name = "omap_12m_fck", |
| 741 | .ops = &clkops_null, | ||
| 777 | .parent = &omap_48m_fck, | 742 | .parent = &omap_48m_fck, |
| 778 | .fixed_div = 4, | 743 | .fixed_div = 4, |
| 779 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 780 | PARENT_CONTROLS_CLOCK, | ||
| 781 | .recalc = &omap2_fixed_divisor_recalc, | 744 | .recalc = &omap2_fixed_divisor_recalc, |
| 782 | }; | 745 | }; |
| 783 | 746 | ||
| 784 | /* This virstual clock is the source for dpll4_m4x2_ck */ | 747 | /* This virstual clock is the source for dpll4_m4x2_ck */ |
| 785 | static struct clk dpll4_m4_ck = { | 748 | static struct clk dpll4_m4_ck = { |
| 786 | .name = "dpll4_m4_ck", | 749 | .name = "dpll4_m4_ck", |
| 750 | .ops = &clkops_null, | ||
| 787 | .parent = &dpll4_ck, | 751 | .parent = &dpll4_ck, |
| 788 | .init = &omap2_init_clksel_parent, | 752 | .init = &omap2_init_clksel_parent, |
| 789 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | 753 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), |
| 790 | .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, | 754 | .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, |
| 791 | .clksel = div16_dpll4_clksel, | 755 | .clksel = div16_dpll4_clksel, |
| 792 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 756 | .clkdm_name = "dpll4_clkdm", |
| 793 | PARENT_CONTROLS_CLOCK, | ||
| 794 | .recalc = &omap2_clksel_recalc, | 757 | .recalc = &omap2_clksel_recalc, |
| 758 | .set_rate = &omap2_clksel_set_rate, | ||
| 759 | .round_rate = &omap2_clksel_round_rate, | ||
| 795 | }; | 760 | }; |
| 796 | 761 | ||
| 797 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 762 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 798 | static struct clk dpll4_m4x2_ck = { | 763 | static struct clk dpll4_m4x2_ck = { |
| 799 | .name = "dpll4_m4x2_ck", | 764 | .name = "dpll4_m4x2_ck", |
| 765 | .ops = &clkops_omap2_dflt_wait, | ||
| 800 | .parent = &dpll4_m4_ck, | 766 | .parent = &dpll4_m4_ck, |
| 801 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 767 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 802 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | 768 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, |
| 803 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | 769 | .flags = INVERT_ENABLE, |
| 770 | .clkdm_name = "dpll4_clkdm", | ||
| 804 | .recalc = &omap3_clkoutx2_recalc, | 771 | .recalc = &omap3_clkoutx2_recalc, |
| 805 | }; | 772 | }; |
| 806 | 773 | ||
| 807 | /* This virtual clock is the source for dpll4_m5x2_ck */ | 774 | /* This virtual clock is the source for dpll4_m5x2_ck */ |
| 808 | static struct clk dpll4_m5_ck = { | 775 | static struct clk dpll4_m5_ck = { |
| 809 | .name = "dpll4_m5_ck", | 776 | .name = "dpll4_m5_ck", |
| 777 | .ops = &clkops_null, | ||
| 810 | .parent = &dpll4_ck, | 778 | .parent = &dpll4_ck, |
| 811 | .init = &omap2_init_clksel_parent, | 779 | .init = &omap2_init_clksel_parent, |
| 812 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), | 780 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), |
| 813 | .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, | 781 | .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, |
| 814 | .clksel = div16_dpll4_clksel, | 782 | .clksel = div16_dpll4_clksel, |
| 815 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 783 | .clkdm_name = "dpll4_clkdm", |
| 816 | PARENT_CONTROLS_CLOCK, | ||
| 817 | .recalc = &omap2_clksel_recalc, | 784 | .recalc = &omap2_clksel_recalc, |
| 818 | }; | 785 | }; |
| 819 | 786 | ||
| 820 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 787 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 821 | static struct clk dpll4_m5x2_ck = { | 788 | static struct clk dpll4_m5x2_ck = { |
| 822 | .name = "dpll4_m5x2_ck", | 789 | .name = "dpll4_m5x2_ck", |
| 790 | .ops = &clkops_omap2_dflt_wait, | ||
| 823 | .parent = &dpll4_m5_ck, | 791 | .parent = &dpll4_m5_ck, |
| 824 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 792 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 825 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | 793 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, |
| 826 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | 794 | .flags = INVERT_ENABLE, |
| 795 | .clkdm_name = "dpll4_clkdm", | ||
| 827 | .recalc = &omap3_clkoutx2_recalc, | 796 | .recalc = &omap3_clkoutx2_recalc, |
| 828 | }; | 797 | }; |
| 829 | 798 | ||
| 830 | /* This virtual clock is the source for dpll4_m6x2_ck */ | 799 | /* This virtual clock is the source for dpll4_m6x2_ck */ |
| 831 | static struct clk dpll4_m6_ck = { | 800 | static struct clk dpll4_m6_ck = { |
| 832 | .name = "dpll4_m6_ck", | 801 | .name = "dpll4_m6_ck", |
| 802 | .ops = &clkops_null, | ||
| 833 | .parent = &dpll4_ck, | 803 | .parent = &dpll4_ck, |
| 834 | .init = &omap2_init_clksel_parent, | 804 | .init = &omap2_init_clksel_parent, |
| 835 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 805 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 836 | .clksel_mask = OMAP3430_DIV_DPLL4_MASK, | 806 | .clksel_mask = OMAP3430_DIV_DPLL4_MASK, |
| 837 | .clksel = div16_dpll4_clksel, | 807 | .clksel = div16_dpll4_clksel, |
| 838 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 808 | .clkdm_name = "dpll4_clkdm", |
| 839 | PARENT_CONTROLS_CLOCK, | ||
| 840 | .recalc = &omap2_clksel_recalc, | 809 | .recalc = &omap2_clksel_recalc, |
| 841 | }; | 810 | }; |
| 842 | 811 | ||
| 843 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | 812 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
| 844 | static struct clk dpll4_m6x2_ck = { | 813 | static struct clk dpll4_m6x2_ck = { |
| 845 | .name = "dpll4_m6x2_ck", | 814 | .name = "dpll4_m6x2_ck", |
| 815 | .ops = &clkops_omap2_dflt_wait, | ||
| 846 | .parent = &dpll4_m6_ck, | 816 | .parent = &dpll4_m6_ck, |
| 847 | .init = &omap2_init_clksel_parent, | 817 | .init = &omap2_init_clksel_parent, |
| 848 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 818 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
| 849 | .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, | 819 | .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, |
| 850 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | 820 | .flags = INVERT_ENABLE, |
| 821 | .clkdm_name = "dpll4_clkdm", | ||
| 851 | .recalc = &omap3_clkoutx2_recalc, | 822 | .recalc = &omap3_clkoutx2_recalc, |
| 852 | }; | 823 | }; |
| 853 | 824 | ||
| 854 | static struct clk emu_per_alwon_ck = { | 825 | static struct clk emu_per_alwon_ck = { |
| 855 | .name = "emu_per_alwon_ck", | 826 | .name = "emu_per_alwon_ck", |
| 827 | .ops = &clkops_null, | ||
| 856 | .parent = &dpll4_m6x2_ck, | 828 | .parent = &dpll4_m6x2_ck, |
| 857 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | 829 | .clkdm_name = "dpll4_clkdm", |
| 858 | PARENT_CONTROLS_CLOCK, | ||
| 859 | .recalc = &followparent_recalc, | 830 | .recalc = &followparent_recalc, |
| 860 | }; | 831 | }; |
| 861 | 832 | ||
| @@ -867,6 +838,9 @@ static struct dpll_data dpll5_dd = { | |||
| 867 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), | 838 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), |
| 868 | .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, | 839 | .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, |
| 869 | .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, | 840 | .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, |
| 841 | .clk_bypass = &sys_ck, | ||
| 842 | .clk_ref = &sys_ck, | ||
| 843 | .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, | ||
| 870 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), | 844 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), |
| 871 | .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, | 845 | .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, |
| 872 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), | 846 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
| @@ -876,20 +850,21 @@ static struct dpll_data dpll5_dd = { | |||
| 876 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), | 850 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), |
| 877 | .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, | 851 | .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, |
| 878 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), | 852 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), |
| 879 | .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT, | 853 | .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, |
| 880 | .max_multiplier = OMAP3_MAX_DPLL_MULT, | 854 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
| 855 | .min_divider = 1, | ||
| 881 | .max_divider = OMAP3_MAX_DPLL_DIV, | 856 | .max_divider = OMAP3_MAX_DPLL_DIV, |
| 882 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | 857 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE |
| 883 | }; | 858 | }; |
| 884 | 859 | ||
| 885 | static struct clk dpll5_ck = { | 860 | static struct clk dpll5_ck = { |
| 886 | .name = "dpll5_ck", | 861 | .name = "dpll5_ck", |
| 862 | .ops = &clkops_noncore_dpll_ops, | ||
| 887 | .parent = &sys_ck, | 863 | .parent = &sys_ck, |
| 888 | .dpll_data = &dpll5_dd, | 864 | .dpll_data = &dpll5_dd, |
| 889 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, | ||
| 890 | .enable = &omap3_noncore_dpll_enable, | ||
| 891 | .disable = &omap3_noncore_dpll_disable, | ||
| 892 | .round_rate = &omap2_dpll_round_rate, | 865 | .round_rate = &omap2_dpll_round_rate, |
| 866 | .set_rate = &omap3_noncore_dpll_set_rate, | ||
| 867 | .clkdm_name = "dpll5_clkdm", | ||
| 893 | .recalc = &omap3_dpll_recalc, | 868 | .recalc = &omap3_dpll_recalc, |
| 894 | }; | 869 | }; |
| 895 | 870 | ||
| @@ -900,31 +875,13 @@ static const struct clksel div16_dpll5_clksel[] = { | |||
| 900 | 875 | ||
| 901 | static struct clk dpll5_m2_ck = { | 876 | static struct clk dpll5_m2_ck = { |
| 902 | .name = "dpll5_m2_ck", | 877 | .name = "dpll5_m2_ck", |
| 878 | .ops = &clkops_null, | ||
| 903 | .parent = &dpll5_ck, | 879 | .parent = &dpll5_ck, |
| 904 | .init = &omap2_init_clksel_parent, | 880 | .init = &omap2_init_clksel_parent, |
| 905 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), | 881 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), |
| 906 | .clksel_mask = OMAP3430ES2_DIV_120M_MASK, | 882 | .clksel_mask = OMAP3430ES2_DIV_120M_MASK, |
| 907 | .clksel = div16_dpll5_clksel, | 883 | .clksel = div16_dpll5_clksel, |
| 908 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | | 884 | .clkdm_name = "dpll5_clkdm", |
| 909 | PARENT_CONTROLS_CLOCK, | ||
| 910 | .recalc = &omap2_clksel_recalc, | ||
| 911 | }; | ||
| 912 | |||
| 913 | static const struct clksel omap_120m_fck_clksel[] = { | ||
| 914 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 915 | { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, | ||
| 916 | { .parent = NULL } | ||
| 917 | }; | ||
| 918 | |||
| 919 | static struct clk omap_120m_fck = { | ||
| 920 | .name = "omap_120m_fck", | ||
| 921 | .parent = &dpll5_m2_ck, | ||
| 922 | .init = &omap2_init_clksel_parent, | ||
| 923 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), | ||
| 924 | .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, | ||
| 925 | .clksel = omap_120m_fck_clksel, | ||
| 926 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | | ||
| 927 | PARENT_CONTROLS_CLOCK, | ||
| 928 | .recalc = &omap2_clksel_recalc, | 885 | .recalc = &omap2_clksel_recalc, |
| 929 | }; | 886 | }; |
| 930 | 887 | ||
| @@ -951,22 +908,23 @@ static const struct clksel_rate clkout2_src_54m_rates[] = { | |||
| 951 | }; | 908 | }; |
| 952 | 909 | ||
| 953 | static const struct clksel clkout2_src_clksel[] = { | 910 | static const struct clksel clkout2_src_clksel[] = { |
| 954 | { .parent = &core_ck, .rates = clkout2_src_core_rates }, | 911 | { .parent = &core_ck, .rates = clkout2_src_core_rates }, |
| 955 | { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, | 912 | { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, |
| 956 | { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates }, | 913 | { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates }, |
| 957 | { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, | 914 | { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, |
| 958 | { .parent = NULL } | 915 | { .parent = NULL } |
| 959 | }; | 916 | }; |
| 960 | 917 | ||
| 961 | static struct clk clkout2_src_ck = { | 918 | static struct clk clkout2_src_ck = { |
| 962 | .name = "clkout2_src_ck", | 919 | .name = "clkout2_src_ck", |
| 920 | .ops = &clkops_omap2_dflt, | ||
| 963 | .init = &omap2_init_clksel_parent, | 921 | .init = &omap2_init_clksel_parent, |
| 964 | .enable_reg = OMAP3430_CM_CLKOUT_CTRL, | 922 | .enable_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 965 | .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, | 923 | .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, |
| 966 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | 924 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 967 | .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, | 925 | .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, |
| 968 | .clksel = clkout2_src_clksel, | 926 | .clksel = clkout2_src_clksel, |
| 969 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | 927 | .clkdm_name = "core_clkdm", |
| 970 | .recalc = &omap2_clksel_recalc, | 928 | .recalc = &omap2_clksel_recalc, |
| 971 | }; | 929 | }; |
| 972 | 930 | ||
| @@ -986,11 +944,11 @@ static const struct clksel sys_clkout2_clksel[] = { | |||
| 986 | 944 | ||
| 987 | static struct clk sys_clkout2 = { | 945 | static struct clk sys_clkout2 = { |
| 988 | .name = "sys_clkout2", | 946 | .name = "sys_clkout2", |
| 947 | .ops = &clkops_null, | ||
| 989 | .init = &omap2_init_clksel_parent, | 948 | .init = &omap2_init_clksel_parent, |
| 990 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | 949 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, |
| 991 | .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, | 950 | .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, |
| 992 | .clksel = sys_clkout2_clksel, | 951 | .clksel = sys_clkout2_clksel, |
| 993 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | ||
| 994 | .recalc = &omap2_clksel_recalc, | 952 | .recalc = &omap2_clksel_recalc, |
| 995 | }; | 953 | }; |
| 996 | 954 | ||
| @@ -998,16 +956,22 @@ static struct clk sys_clkout2 = { | |||
| 998 | 956 | ||
| 999 | static struct clk corex2_fck = { | 957 | static struct clk corex2_fck = { |
| 1000 | .name = "corex2_fck", | 958 | .name = "corex2_fck", |
| 959 | .ops = &clkops_null, | ||
| 1001 | .parent = &dpll3_m2x2_ck, | 960 | .parent = &dpll3_m2x2_ck, |
| 1002 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1003 | PARENT_CONTROLS_CLOCK, | ||
| 1004 | .recalc = &followparent_recalc, | 961 | .recalc = &followparent_recalc, |
| 1005 | }; | 962 | }; |
| 1006 | 963 | ||
| 1007 | /* DPLL power domain clock controls */ | 964 | /* DPLL power domain clock controls */ |
| 1008 | 965 | ||
| 1009 | static const struct clksel div2_core_clksel[] = { | 966 | static const struct clksel_rate div4_rates[] = { |
| 1010 | { .parent = &core_ck, .rates = div2_rates }, | 967 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, |
| 968 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | ||
| 969 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | ||
| 970 | { .div = 0 } | ||
| 971 | }; | ||
| 972 | |||
| 973 | static const struct clksel div4_core_clksel[] = { | ||
| 974 | { .parent = &core_ck, .rates = div4_rates }, | ||
| 1011 | { .parent = NULL } | 975 | { .parent = NULL } |
| 1012 | }; | 976 | }; |
| 1013 | 977 | ||
| @@ -1017,39 +981,21 @@ static const struct clksel div2_core_clksel[] = { | |||
| 1017 | */ | 981 | */ |
| 1018 | static struct clk dpll1_fck = { | 982 | static struct clk dpll1_fck = { |
| 1019 | .name = "dpll1_fck", | 983 | .name = "dpll1_fck", |
| 984 | .ops = &clkops_null, | ||
| 1020 | .parent = &core_ck, | 985 | .parent = &core_ck, |
| 1021 | .init = &omap2_init_clksel_parent, | 986 | .init = &omap2_init_clksel_parent, |
| 1022 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | 987 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 1023 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, | 988 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, |
| 1024 | .clksel = div2_core_clksel, | 989 | .clksel = div4_core_clksel, |
| 1025 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1026 | PARENT_CONTROLS_CLOCK, | ||
| 1027 | .recalc = &omap2_clksel_recalc, | 990 | .recalc = &omap2_clksel_recalc, |
| 1028 | }; | 991 | }; |
| 1029 | 992 | ||
| 1030 | /* | ||
| 1031 | * MPU clksel: | ||
| 1032 | * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck | ||
| 1033 | * derives from the high-frequency bypass clock originating from DPLL3, | ||
| 1034 | * called 'dpll1_fck' | ||
| 1035 | */ | ||
| 1036 | static const struct clksel mpu_clksel[] = { | ||
| 1037 | { .parent = &dpll1_fck, .rates = dpll_bypass_rates }, | ||
| 1038 | { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, | ||
| 1039 | { .parent = NULL } | ||
| 1040 | }; | ||
| 1041 | |||
| 1042 | static struct clk mpu_ck = { | 993 | static struct clk mpu_ck = { |
| 1043 | .name = "mpu_ck", | 994 | .name = "mpu_ck", |
| 995 | .ops = &clkops_null, | ||
| 1044 | .parent = &dpll1_x2m2_ck, | 996 | .parent = &dpll1_x2m2_ck, |
| 1045 | .init = &omap2_init_clksel_parent, | ||
| 1046 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | ||
| 1047 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, | ||
| 1048 | .clksel = mpu_clksel, | ||
| 1049 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1050 | PARENT_CONTROLS_CLOCK, | ||
| 1051 | .clkdm_name = "mpu_clkdm", | 997 | .clkdm_name = "mpu_clkdm", |
| 1052 | .recalc = &omap2_clksel_recalc, | 998 | .recalc = &followparent_recalc, |
| 1053 | }; | 999 | }; |
| 1054 | 1000 | ||
| 1055 | /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ | 1001 | /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ |
| @@ -1066,13 +1012,12 @@ static const struct clksel arm_fck_clksel[] = { | |||
| 1066 | 1012 | ||
| 1067 | static struct clk arm_fck = { | 1013 | static struct clk arm_fck = { |
| 1068 | .name = "arm_fck", | 1014 | .name = "arm_fck", |
| 1015 | .ops = &clkops_null, | ||
| 1069 | .parent = &mpu_ck, | 1016 | .parent = &mpu_ck, |
| 1070 | .init = &omap2_init_clksel_parent, | 1017 | .init = &omap2_init_clksel_parent, |
| 1071 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | 1018 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), |
| 1072 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, | 1019 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, |
| 1073 | .clksel = arm_fck_clksel, | 1020 | .clksel = arm_fck_clksel, |
| 1074 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1075 | PARENT_CONTROLS_CLOCK, | ||
| 1076 | .recalc = &omap2_clksel_recalc, | 1021 | .recalc = &omap2_clksel_recalc, |
| 1077 | }; | 1022 | }; |
| 1078 | 1023 | ||
| @@ -1084,63 +1029,48 @@ static struct clk arm_fck = { | |||
| 1084 | */ | 1029 | */ |
| 1085 | static struct clk emu_mpu_alwon_ck = { | 1030 | static struct clk emu_mpu_alwon_ck = { |
| 1086 | .name = "emu_mpu_alwon_ck", | 1031 | .name = "emu_mpu_alwon_ck", |
| 1032 | .ops = &clkops_null, | ||
| 1087 | .parent = &mpu_ck, | 1033 | .parent = &mpu_ck, |
| 1088 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1089 | PARENT_CONTROLS_CLOCK, | ||
| 1090 | .recalc = &followparent_recalc, | 1034 | .recalc = &followparent_recalc, |
| 1091 | }; | 1035 | }; |
| 1092 | 1036 | ||
| 1093 | static struct clk dpll2_fck = { | 1037 | static struct clk dpll2_fck = { |
| 1094 | .name = "dpll2_fck", | 1038 | .name = "dpll2_fck", |
| 1039 | .ops = &clkops_null, | ||
| 1095 | .parent = &core_ck, | 1040 | .parent = &core_ck, |
| 1096 | .init = &omap2_init_clksel_parent, | 1041 | .init = &omap2_init_clksel_parent, |
| 1097 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | 1042 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), |
| 1098 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, | 1043 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, |
| 1099 | .clksel = div2_core_clksel, | 1044 | .clksel = div4_core_clksel, |
| 1100 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1101 | PARENT_CONTROLS_CLOCK, | ||
| 1102 | .recalc = &omap2_clksel_recalc, | 1045 | .recalc = &omap2_clksel_recalc, |
| 1103 | }; | 1046 | }; |
| 1104 | 1047 | ||
| 1105 | /* | ||
| 1106 | * IVA2 clksel: | ||
| 1107 | * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck | ||
| 1108 | * derives from the high-frequency bypass clock originating from DPLL3, | ||
| 1109 | * called 'dpll2_fck' | ||
| 1110 | */ | ||
| 1111 | |||
| 1112 | static const struct clksel iva2_clksel[] = { | ||
| 1113 | { .parent = &dpll2_fck, .rates = dpll_bypass_rates }, | ||
| 1114 | { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, | ||
| 1115 | { .parent = NULL } | ||
| 1116 | }; | ||
| 1117 | |||
| 1118 | static struct clk iva2_ck = { | 1048 | static struct clk iva2_ck = { |
| 1119 | .name = "iva2_ck", | 1049 | .name = "iva2_ck", |
| 1050 | .ops = &clkops_omap2_dflt_wait, | ||
| 1120 | .parent = &dpll2_m2_ck, | 1051 | .parent = &dpll2_m2_ck, |
| 1121 | .init = &omap2_init_clksel_parent, | 1052 | .init = &omap2_init_clksel_parent, |
| 1122 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), | 1053 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), |
| 1123 | .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, | 1054 | .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, |
| 1124 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, | ||
| 1125 | OMAP3430_CM_IDLEST_PLL), | ||
| 1126 | .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, | ||
| 1127 | .clksel = iva2_clksel, | ||
| 1128 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 1129 | .clkdm_name = "iva2_clkdm", | 1055 | .clkdm_name = "iva2_clkdm", |
| 1130 | .recalc = &omap2_clksel_recalc, | 1056 | .recalc = &followparent_recalc, |
| 1131 | }; | 1057 | }; |
| 1132 | 1058 | ||
| 1133 | /* Common interface clocks */ | 1059 | /* Common interface clocks */ |
| 1134 | 1060 | ||
| 1061 | static const struct clksel div2_core_clksel[] = { | ||
| 1062 | { .parent = &core_ck, .rates = div2_rates }, | ||
| 1063 | { .parent = NULL } | ||
| 1064 | }; | ||
| 1065 | |||
| 1135 | static struct clk l3_ick = { | 1066 | static struct clk l3_ick = { |
| 1136 | .name = "l3_ick", | 1067 | .name = "l3_ick", |
| 1068 | .ops = &clkops_null, | ||
| 1137 | .parent = &core_ck, | 1069 | .parent = &core_ck, |
| 1138 | .init = &omap2_init_clksel_parent, | 1070 | .init = &omap2_init_clksel_parent, |
| 1139 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | 1071 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1140 | .clksel_mask = OMAP3430_CLKSEL_L3_MASK, | 1072 | .clksel_mask = OMAP3430_CLKSEL_L3_MASK, |
| 1141 | .clksel = div2_core_clksel, | 1073 | .clksel = div2_core_clksel, |
| 1142 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1143 | PARENT_CONTROLS_CLOCK, | ||
| 1144 | .clkdm_name = "core_l3_clkdm", | 1074 | .clkdm_name = "core_l3_clkdm", |
| 1145 | .recalc = &omap2_clksel_recalc, | 1075 | .recalc = &omap2_clksel_recalc, |
| 1146 | }; | 1076 | }; |
| @@ -1152,13 +1082,12 @@ static const struct clksel div2_l3_clksel[] = { | |||
| 1152 | 1082 | ||
| 1153 | static struct clk l4_ick = { | 1083 | static struct clk l4_ick = { |
| 1154 | .name = "l4_ick", | 1084 | .name = "l4_ick", |
| 1085 | .ops = &clkops_null, | ||
| 1155 | .parent = &l3_ick, | 1086 | .parent = &l3_ick, |
| 1156 | .init = &omap2_init_clksel_parent, | 1087 | .init = &omap2_init_clksel_parent, |
| 1157 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | 1088 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1158 | .clksel_mask = OMAP3430_CLKSEL_L4_MASK, | 1089 | .clksel_mask = OMAP3430_CLKSEL_L4_MASK, |
| 1159 | .clksel = div2_l3_clksel, | 1090 | .clksel = div2_l3_clksel, |
| 1160 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1161 | PARENT_CONTROLS_CLOCK, | ||
| 1162 | .clkdm_name = "core_l4_clkdm", | 1091 | .clkdm_name = "core_l4_clkdm", |
| 1163 | .recalc = &omap2_clksel_recalc, | 1092 | .recalc = &omap2_clksel_recalc, |
| 1164 | 1093 | ||
| @@ -1171,12 +1100,12 @@ static const struct clksel div2_l4_clksel[] = { | |||
| 1171 | 1100 | ||
| 1172 | static struct clk rm_ick = { | 1101 | static struct clk rm_ick = { |
| 1173 | .name = "rm_ick", | 1102 | .name = "rm_ick", |
| 1103 | .ops = &clkops_null, | ||
| 1174 | .parent = &l4_ick, | 1104 | .parent = &l4_ick, |
| 1175 | .init = &omap2_init_clksel_parent, | 1105 | .init = &omap2_init_clksel_parent, |
| 1176 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | 1106 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 1177 | .clksel_mask = OMAP3430_CLKSEL_RM_MASK, | 1107 | .clksel_mask = OMAP3430_CLKSEL_RM_MASK, |
| 1178 | .clksel = div2_l4_clksel, | 1108 | .clksel = div2_l4_clksel, |
| 1179 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | ||
| 1180 | .recalc = &omap2_clksel_recalc, | 1109 | .recalc = &omap2_clksel_recalc, |
| 1181 | }; | 1110 | }; |
| 1182 | 1111 | ||
| @@ -1192,53 +1121,52 @@ static const struct clksel gfx_l3_clksel[] = { | |||
| 1192 | /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ | 1121 | /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ |
| 1193 | static struct clk gfx_l3_ck = { | 1122 | static struct clk gfx_l3_ck = { |
| 1194 | .name = "gfx_l3_ck", | 1123 | .name = "gfx_l3_ck", |
| 1124 | .ops = &clkops_omap2_dflt_wait, | ||
| 1195 | .parent = &l3_ick, | 1125 | .parent = &l3_ick, |
| 1196 | .init = &omap2_init_clksel_parent, | 1126 | .init = &omap2_init_clksel_parent, |
| 1197 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | 1127 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
| 1198 | .enable_bit = OMAP_EN_GFX_SHIFT, | 1128 | .enable_bit = OMAP_EN_GFX_SHIFT, |
| 1199 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1200 | .recalc = &followparent_recalc, | 1129 | .recalc = &followparent_recalc, |
| 1201 | }; | 1130 | }; |
| 1202 | 1131 | ||
| 1203 | static struct clk gfx_l3_fck = { | 1132 | static struct clk gfx_l3_fck = { |
| 1204 | .name = "gfx_l3_fck", | 1133 | .name = "gfx_l3_fck", |
| 1134 | .ops = &clkops_null, | ||
| 1205 | .parent = &gfx_l3_ck, | 1135 | .parent = &gfx_l3_ck, |
| 1206 | .init = &omap2_init_clksel_parent, | 1136 | .init = &omap2_init_clksel_parent, |
| 1207 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | 1137 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
| 1208 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | 1138 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, |
| 1209 | .clksel = gfx_l3_clksel, | 1139 | .clksel = gfx_l3_clksel, |
| 1210 | .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES | | ||
| 1211 | PARENT_CONTROLS_CLOCK, | ||
| 1212 | .clkdm_name = "gfx_3430es1_clkdm", | 1140 | .clkdm_name = "gfx_3430es1_clkdm", |
| 1213 | .recalc = &omap2_clksel_recalc, | 1141 | .recalc = &omap2_clksel_recalc, |
| 1214 | }; | 1142 | }; |
| 1215 | 1143 | ||
| 1216 | static struct clk gfx_l3_ick = { | 1144 | static struct clk gfx_l3_ick = { |
| 1217 | .name = "gfx_l3_ick", | 1145 | .name = "gfx_l3_ick", |
| 1146 | .ops = &clkops_null, | ||
| 1218 | .parent = &gfx_l3_ck, | 1147 | .parent = &gfx_l3_ck, |
| 1219 | .flags = CLOCK_IN_OMAP3430ES1 | PARENT_CONTROLS_CLOCK, | ||
| 1220 | .clkdm_name = "gfx_3430es1_clkdm", | 1148 | .clkdm_name = "gfx_3430es1_clkdm", |
| 1221 | .recalc = &followparent_recalc, | 1149 | .recalc = &followparent_recalc, |
| 1222 | }; | 1150 | }; |
| 1223 | 1151 | ||
| 1224 | static struct clk gfx_cg1_ck = { | 1152 | static struct clk gfx_cg1_ck = { |
| 1225 | .name = "gfx_cg1_ck", | 1153 | .name = "gfx_cg1_ck", |
| 1154 | .ops = &clkops_omap2_dflt_wait, | ||
| 1226 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | 1155 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
| 1227 | .init = &omap2_init_clk_clkdm, | 1156 | .init = &omap2_init_clk_clkdm, |
| 1228 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 1157 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1229 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, | 1158 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, |
| 1230 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1231 | .clkdm_name = "gfx_3430es1_clkdm", | 1159 | .clkdm_name = "gfx_3430es1_clkdm", |
| 1232 | .recalc = &followparent_recalc, | 1160 | .recalc = &followparent_recalc, |
| 1233 | }; | 1161 | }; |
| 1234 | 1162 | ||
| 1235 | static struct clk gfx_cg2_ck = { | 1163 | static struct clk gfx_cg2_ck = { |
| 1236 | .name = "gfx_cg2_ck", | 1164 | .name = "gfx_cg2_ck", |
| 1165 | .ops = &clkops_omap2_dflt_wait, | ||
| 1237 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | 1166 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
| 1238 | .init = &omap2_init_clk_clkdm, | 1167 | .init = &omap2_init_clk_clkdm, |
| 1239 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 1168 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
| 1240 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, | 1169 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, |
| 1241 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1242 | .clkdm_name = "gfx_3430es1_clkdm", | 1170 | .clkdm_name = "gfx_3430es1_clkdm", |
| 1243 | .recalc = &followparent_recalc, | 1171 | .recalc = &followparent_recalc, |
| 1244 | }; | 1172 | }; |
| @@ -1265,24 +1193,24 @@ static const struct clksel sgx_clksel[] = { | |||
| 1265 | 1193 | ||
| 1266 | static struct clk sgx_fck = { | 1194 | static struct clk sgx_fck = { |
| 1267 | .name = "sgx_fck", | 1195 | .name = "sgx_fck", |
| 1196 | .ops = &clkops_omap2_dflt_wait, | ||
| 1268 | .init = &omap2_init_clksel_parent, | 1197 | .init = &omap2_init_clksel_parent, |
| 1269 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), | 1198 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), |
| 1270 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, | 1199 | .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, |
| 1271 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), | 1200 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), |
| 1272 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, | 1201 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, |
| 1273 | .clksel = sgx_clksel, | 1202 | .clksel = sgx_clksel, |
| 1274 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1275 | .clkdm_name = "sgx_clkdm", | 1203 | .clkdm_name = "sgx_clkdm", |
| 1276 | .recalc = &omap2_clksel_recalc, | 1204 | .recalc = &omap2_clksel_recalc, |
| 1277 | }; | 1205 | }; |
| 1278 | 1206 | ||
| 1279 | static struct clk sgx_ick = { | 1207 | static struct clk sgx_ick = { |
| 1280 | .name = "sgx_ick", | 1208 | .name = "sgx_ick", |
| 1209 | .ops = &clkops_omap2_dflt_wait, | ||
| 1281 | .parent = &l3_ick, | 1210 | .parent = &l3_ick, |
| 1282 | .init = &omap2_init_clk_clkdm, | 1211 | .init = &omap2_init_clk_clkdm, |
| 1283 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), | 1212 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), |
| 1284 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, | 1213 | .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, |
| 1285 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1286 | .clkdm_name = "sgx_clkdm", | 1214 | .clkdm_name = "sgx_clkdm", |
| 1287 | .recalc = &followparent_recalc, | 1215 | .recalc = &followparent_recalc, |
| 1288 | }; | 1216 | }; |
| @@ -1291,11 +1219,11 @@ static struct clk sgx_ick = { | |||
| 1291 | 1219 | ||
| 1292 | static struct clk d2d_26m_fck = { | 1220 | static struct clk d2d_26m_fck = { |
| 1293 | .name = "d2d_26m_fck", | 1221 | .name = "d2d_26m_fck", |
| 1222 | .ops = &clkops_omap2_dflt_wait, | ||
| 1294 | .parent = &sys_ck, | 1223 | .parent = &sys_ck, |
| 1295 | .init = &omap2_init_clk_clkdm, | 1224 | .init = &omap2_init_clk_clkdm, |
| 1296 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1225 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1297 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, | 1226 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, |
| 1298 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1299 | .clkdm_name = "d2d_clkdm", | 1227 | .clkdm_name = "d2d_clkdm", |
| 1300 | .recalc = &followparent_recalc, | 1228 | .recalc = &followparent_recalc, |
| 1301 | }; | 1229 | }; |
| @@ -1308,6 +1236,7 @@ static const struct clksel omap343x_gpt_clksel[] = { | |||
| 1308 | 1236 | ||
| 1309 | static struct clk gpt10_fck = { | 1237 | static struct clk gpt10_fck = { |
| 1310 | .name = "gpt10_fck", | 1238 | .name = "gpt10_fck", |
| 1239 | .ops = &clkops_omap2_dflt_wait, | ||
| 1311 | .parent = &sys_ck, | 1240 | .parent = &sys_ck, |
| 1312 | .init = &omap2_init_clksel_parent, | 1241 | .init = &omap2_init_clksel_parent, |
| 1313 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1242 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| @@ -1315,13 +1244,13 @@ static struct clk gpt10_fck = { | |||
| 1315 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | 1244 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1316 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, | 1245 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, |
| 1317 | .clksel = omap343x_gpt_clksel, | 1246 | .clksel = omap343x_gpt_clksel, |
| 1318 | .flags = CLOCK_IN_OMAP343X, | ||
| 1319 | .clkdm_name = "core_l4_clkdm", | 1247 | .clkdm_name = "core_l4_clkdm", |
| 1320 | .recalc = &omap2_clksel_recalc, | 1248 | .recalc = &omap2_clksel_recalc, |
| 1321 | }; | 1249 | }; |
| 1322 | 1250 | ||
| 1323 | static struct clk gpt11_fck = { | 1251 | static struct clk gpt11_fck = { |
| 1324 | .name = "gpt11_fck", | 1252 | .name = "gpt11_fck", |
| 1253 | .ops = &clkops_omap2_dflt_wait, | ||
| 1325 | .parent = &sys_ck, | 1254 | .parent = &sys_ck, |
| 1326 | .init = &omap2_init_clksel_parent, | 1255 | .init = &omap2_init_clksel_parent, |
| 1327 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1256 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| @@ -1329,35 +1258,34 @@ static struct clk gpt11_fck = { | |||
| 1329 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | 1258 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1330 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, | 1259 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, |
| 1331 | .clksel = omap343x_gpt_clksel, | 1260 | .clksel = omap343x_gpt_clksel, |
| 1332 | .flags = CLOCK_IN_OMAP343X, | ||
| 1333 | .clkdm_name = "core_l4_clkdm", | 1261 | .clkdm_name = "core_l4_clkdm", |
| 1334 | .recalc = &omap2_clksel_recalc, | 1262 | .recalc = &omap2_clksel_recalc, |
| 1335 | }; | 1263 | }; |
| 1336 | 1264 | ||
| 1337 | static struct clk cpefuse_fck = { | 1265 | static struct clk cpefuse_fck = { |
| 1338 | .name = "cpefuse_fck", | 1266 | .name = "cpefuse_fck", |
| 1267 | .ops = &clkops_omap2_dflt, | ||
| 1339 | .parent = &sys_ck, | 1268 | .parent = &sys_ck, |
| 1340 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | 1269 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1341 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, | 1270 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, |
| 1342 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1343 | .recalc = &followparent_recalc, | 1271 | .recalc = &followparent_recalc, |
| 1344 | }; | 1272 | }; |
| 1345 | 1273 | ||
| 1346 | static struct clk ts_fck = { | 1274 | static struct clk ts_fck = { |
| 1347 | .name = "ts_fck", | 1275 | .name = "ts_fck", |
| 1276 | .ops = &clkops_omap2_dflt, | ||
| 1348 | .parent = &omap_32k_fck, | 1277 | .parent = &omap_32k_fck, |
| 1349 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | 1278 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1350 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, | 1279 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, |
| 1351 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1352 | .recalc = &followparent_recalc, | 1280 | .recalc = &followparent_recalc, |
| 1353 | }; | 1281 | }; |
| 1354 | 1282 | ||
| 1355 | static struct clk usbtll_fck = { | 1283 | static struct clk usbtll_fck = { |
| 1356 | .name = "usbtll_fck", | 1284 | .name = "usbtll_fck", |
| 1357 | .parent = &omap_120m_fck, | 1285 | .ops = &clkops_omap2_dflt, |
| 1286 | .parent = &dpll5_m2_ck, | ||
| 1358 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | 1287 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
| 1359 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | 1288 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
| 1360 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1361 | .recalc = &followparent_recalc, | 1289 | .recalc = &followparent_recalc, |
| 1362 | }; | 1290 | }; |
| 1363 | 1291 | ||
| @@ -1365,84 +1293,83 @@ static struct clk usbtll_fck = { | |||
| 1365 | 1293 | ||
| 1366 | static struct clk core_96m_fck = { | 1294 | static struct clk core_96m_fck = { |
| 1367 | .name = "core_96m_fck", | 1295 | .name = "core_96m_fck", |
| 1296 | .ops = &clkops_null, | ||
| 1368 | .parent = &omap_96m_fck, | 1297 | .parent = &omap_96m_fck, |
| 1369 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1370 | PARENT_CONTROLS_CLOCK, | ||
| 1371 | .clkdm_name = "core_l4_clkdm", | 1298 | .clkdm_name = "core_l4_clkdm", |
| 1372 | .recalc = &followparent_recalc, | 1299 | .recalc = &followparent_recalc, |
| 1373 | }; | 1300 | }; |
| 1374 | 1301 | ||
| 1375 | static struct clk mmchs3_fck = { | 1302 | static struct clk mmchs3_fck = { |
| 1376 | .name = "mmchs_fck", | 1303 | .name = "mmchs_fck", |
| 1304 | .ops = &clkops_omap2_dflt_wait, | ||
| 1377 | .id = 2, | 1305 | .id = 2, |
| 1378 | .parent = &core_96m_fck, | 1306 | .parent = &core_96m_fck, |
| 1379 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1307 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1380 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | 1308 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
| 1381 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1382 | .clkdm_name = "core_l4_clkdm", | 1309 | .clkdm_name = "core_l4_clkdm", |
| 1383 | .recalc = &followparent_recalc, | 1310 | .recalc = &followparent_recalc, |
| 1384 | }; | 1311 | }; |
| 1385 | 1312 | ||
| 1386 | static struct clk mmchs2_fck = { | 1313 | static struct clk mmchs2_fck = { |
| 1387 | .name = "mmchs_fck", | 1314 | .name = "mmchs_fck", |
| 1315 | .ops = &clkops_omap2_dflt_wait, | ||
| 1388 | .id = 1, | 1316 | .id = 1, |
| 1389 | .parent = &core_96m_fck, | 1317 | .parent = &core_96m_fck, |
| 1390 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1318 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1391 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | 1319 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
| 1392 | .flags = CLOCK_IN_OMAP343X, | ||
| 1393 | .clkdm_name = "core_l4_clkdm", | 1320 | .clkdm_name = "core_l4_clkdm", |
| 1394 | .recalc = &followparent_recalc, | 1321 | .recalc = &followparent_recalc, |
| 1395 | }; | 1322 | }; |
| 1396 | 1323 | ||
| 1397 | static struct clk mspro_fck = { | 1324 | static struct clk mspro_fck = { |
| 1398 | .name = "mspro_fck", | 1325 | .name = "mspro_fck", |
| 1326 | .ops = &clkops_omap2_dflt_wait, | ||
| 1399 | .parent = &core_96m_fck, | 1327 | .parent = &core_96m_fck, |
| 1400 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1328 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1401 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | 1329 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, |
| 1402 | .flags = CLOCK_IN_OMAP343X, | ||
| 1403 | .clkdm_name = "core_l4_clkdm", | 1330 | .clkdm_name = "core_l4_clkdm", |
| 1404 | .recalc = &followparent_recalc, | 1331 | .recalc = &followparent_recalc, |
| 1405 | }; | 1332 | }; |
| 1406 | 1333 | ||
| 1407 | static struct clk mmchs1_fck = { | 1334 | static struct clk mmchs1_fck = { |
| 1408 | .name = "mmchs_fck", | 1335 | .name = "mmchs_fck", |
| 1336 | .ops = &clkops_omap2_dflt_wait, | ||
| 1409 | .parent = &core_96m_fck, | 1337 | .parent = &core_96m_fck, |
| 1410 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1338 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1411 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | 1339 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, |
| 1412 | .flags = CLOCK_IN_OMAP343X, | ||
| 1413 | .clkdm_name = "core_l4_clkdm", | 1340 | .clkdm_name = "core_l4_clkdm", |
| 1414 | .recalc = &followparent_recalc, | 1341 | .recalc = &followparent_recalc, |
| 1415 | }; | 1342 | }; |
| 1416 | 1343 | ||
| 1417 | static struct clk i2c3_fck = { | 1344 | static struct clk i2c3_fck = { |
| 1418 | .name = "i2c_fck", | 1345 | .name = "i2c_fck", |
| 1346 | .ops = &clkops_omap2_dflt_wait, | ||
| 1419 | .id = 3, | 1347 | .id = 3, |
| 1420 | .parent = &core_96m_fck, | 1348 | .parent = &core_96m_fck, |
| 1421 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1349 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1422 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | 1350 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
| 1423 | .flags = CLOCK_IN_OMAP343X, | ||
| 1424 | .clkdm_name = "core_l4_clkdm", | 1351 | .clkdm_name = "core_l4_clkdm", |
| 1425 | .recalc = &followparent_recalc, | 1352 | .recalc = &followparent_recalc, |
| 1426 | }; | 1353 | }; |
| 1427 | 1354 | ||
| 1428 | static struct clk i2c2_fck = { | 1355 | static struct clk i2c2_fck = { |
| 1429 | .name = "i2c_fck", | 1356 | .name = "i2c_fck", |
| 1357 | .ops = &clkops_omap2_dflt_wait, | ||
| 1430 | .id = 2, | 1358 | .id = 2, |
| 1431 | .parent = &core_96m_fck, | 1359 | .parent = &core_96m_fck, |
| 1432 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1360 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1433 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | 1361 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
| 1434 | .flags = CLOCK_IN_OMAP343X, | ||
| 1435 | .clkdm_name = "core_l4_clkdm", | 1362 | .clkdm_name = "core_l4_clkdm", |
| 1436 | .recalc = &followparent_recalc, | 1363 | .recalc = &followparent_recalc, |
| 1437 | }; | 1364 | }; |
| 1438 | 1365 | ||
| 1439 | static struct clk i2c1_fck = { | 1366 | static struct clk i2c1_fck = { |
| 1440 | .name = "i2c_fck", | 1367 | .name = "i2c_fck", |
| 1368 | .ops = &clkops_omap2_dflt_wait, | ||
| 1441 | .id = 1, | 1369 | .id = 1, |
| 1442 | .parent = &core_96m_fck, | 1370 | .parent = &core_96m_fck, |
| 1443 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1371 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1444 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | 1372 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
| 1445 | .flags = CLOCK_IN_OMAP343X, | ||
| 1446 | .clkdm_name = "core_l4_clkdm", | 1373 | .clkdm_name = "core_l4_clkdm", |
| 1447 | .recalc = &followparent_recalc, | 1374 | .recalc = &followparent_recalc, |
| 1448 | }; | 1375 | }; |
| @@ -1469,6 +1396,7 @@ static const struct clksel mcbsp_15_clksel[] = { | |||
| 1469 | 1396 | ||
| 1470 | static struct clk mcbsp5_fck = { | 1397 | static struct clk mcbsp5_fck = { |
| 1471 | .name = "mcbsp_fck", | 1398 | .name = "mcbsp_fck", |
| 1399 | .ops = &clkops_omap2_dflt_wait, | ||
| 1472 | .id = 5, | 1400 | .id = 5, |
| 1473 | .init = &omap2_init_clksel_parent, | 1401 | .init = &omap2_init_clksel_parent, |
| 1474 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1402 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| @@ -1476,13 +1404,13 @@ static struct clk mcbsp5_fck = { | |||
| 1476 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | 1404 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 1477 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, | 1405 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, |
| 1478 | .clksel = mcbsp_15_clksel, | 1406 | .clksel = mcbsp_15_clksel, |
| 1479 | .flags = CLOCK_IN_OMAP343X, | ||
| 1480 | .clkdm_name = "core_l4_clkdm", | 1407 | .clkdm_name = "core_l4_clkdm", |
| 1481 | .recalc = &omap2_clksel_recalc, | 1408 | .recalc = &omap2_clksel_recalc, |
| 1482 | }; | 1409 | }; |
| 1483 | 1410 | ||
| 1484 | static struct clk mcbsp1_fck = { | 1411 | static struct clk mcbsp1_fck = { |
| 1485 | .name = "mcbsp_fck", | 1412 | .name = "mcbsp_fck", |
| 1413 | .ops = &clkops_omap2_dflt_wait, | ||
| 1486 | .id = 1, | 1414 | .id = 1, |
| 1487 | .init = &omap2_init_clksel_parent, | 1415 | .init = &omap2_init_clksel_parent, |
| 1488 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1416 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| @@ -1490,7 +1418,6 @@ static struct clk mcbsp1_fck = { | |||
| 1490 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | 1418 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
| 1491 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, | 1419 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, |
| 1492 | .clksel = mcbsp_15_clksel, | 1420 | .clksel = mcbsp_15_clksel, |
| 1493 | .flags = CLOCK_IN_OMAP343X, | ||
| 1494 | .clkdm_name = "core_l4_clkdm", | 1421 | .clkdm_name = "core_l4_clkdm", |
| 1495 | .recalc = &omap2_clksel_recalc, | 1422 | .recalc = &omap2_clksel_recalc, |
| 1496 | }; | 1423 | }; |
| @@ -1499,77 +1426,76 @@ static struct clk mcbsp1_fck = { | |||
| 1499 | 1426 | ||
| 1500 | static struct clk core_48m_fck = { | 1427 | static struct clk core_48m_fck = { |
| 1501 | .name = "core_48m_fck", | 1428 | .name = "core_48m_fck", |
| 1429 | .ops = &clkops_null, | ||
| 1502 | .parent = &omap_48m_fck, | 1430 | .parent = &omap_48m_fck, |
| 1503 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1504 | PARENT_CONTROLS_CLOCK, | ||
| 1505 | .clkdm_name = "core_l4_clkdm", | 1431 | .clkdm_name = "core_l4_clkdm", |
| 1506 | .recalc = &followparent_recalc, | 1432 | .recalc = &followparent_recalc, |
| 1507 | }; | 1433 | }; |
| 1508 | 1434 | ||
| 1509 | static struct clk mcspi4_fck = { | 1435 | static struct clk mcspi4_fck = { |
| 1510 | .name = "mcspi_fck", | 1436 | .name = "mcspi_fck", |
| 1437 | .ops = &clkops_omap2_dflt_wait, | ||
| 1511 | .id = 4, | 1438 | .id = 4, |
| 1512 | .parent = &core_48m_fck, | 1439 | .parent = &core_48m_fck, |
| 1513 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1440 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1514 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | 1441 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
| 1515 | .flags = CLOCK_IN_OMAP343X, | ||
| 1516 | .recalc = &followparent_recalc, | 1442 | .recalc = &followparent_recalc, |
| 1517 | }; | 1443 | }; |
| 1518 | 1444 | ||
| 1519 | static struct clk mcspi3_fck = { | 1445 | static struct clk mcspi3_fck = { |
| 1520 | .name = "mcspi_fck", | 1446 | .name = "mcspi_fck", |
| 1447 | .ops = &clkops_omap2_dflt_wait, | ||
| 1521 | .id = 3, | 1448 | .id = 3, |
| 1522 | .parent = &core_48m_fck, | 1449 | .parent = &core_48m_fck, |
| 1523 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1450 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1524 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | 1451 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
| 1525 | .flags = CLOCK_IN_OMAP343X, | ||
| 1526 | .recalc = &followparent_recalc, | 1452 | .recalc = &followparent_recalc, |
| 1527 | }; | 1453 | }; |
| 1528 | 1454 | ||
| 1529 | static struct clk mcspi2_fck = { | 1455 | static struct clk mcspi2_fck = { |
| 1530 | .name = "mcspi_fck", | 1456 | .name = "mcspi_fck", |
| 1457 | .ops = &clkops_omap2_dflt_wait, | ||
| 1531 | .id = 2, | 1458 | .id = 2, |
| 1532 | .parent = &core_48m_fck, | 1459 | .parent = &core_48m_fck, |
| 1533 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1460 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1534 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | 1461 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
| 1535 | .flags = CLOCK_IN_OMAP343X, | ||
| 1536 | .recalc = &followparent_recalc, | 1462 | .recalc = &followparent_recalc, |
| 1537 | }; | 1463 | }; |
| 1538 | 1464 | ||
| 1539 | static struct clk mcspi1_fck = { | 1465 | static struct clk mcspi1_fck = { |
| 1540 | .name = "mcspi_fck", | 1466 | .name = "mcspi_fck", |
| 1467 | .ops = &clkops_omap2_dflt_wait, | ||
| 1541 | .id = 1, | 1468 | .id = 1, |
| 1542 | .parent = &core_48m_fck, | 1469 | .parent = &core_48m_fck, |
| 1543 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1470 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1544 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | 1471 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
| 1545 | .flags = CLOCK_IN_OMAP343X, | ||
| 1546 | .recalc = &followparent_recalc, | 1472 | .recalc = &followparent_recalc, |
| 1547 | }; | 1473 | }; |
| 1548 | 1474 | ||
| 1549 | static struct clk uart2_fck = { | 1475 | static struct clk uart2_fck = { |
| 1550 | .name = "uart2_fck", | 1476 | .name = "uart2_fck", |
| 1477 | .ops = &clkops_omap2_dflt_wait, | ||
| 1551 | .parent = &core_48m_fck, | 1478 | .parent = &core_48m_fck, |
| 1552 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1479 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1553 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | 1480 | .enable_bit = OMAP3430_EN_UART2_SHIFT, |
| 1554 | .flags = CLOCK_IN_OMAP343X, | ||
| 1555 | .recalc = &followparent_recalc, | 1481 | .recalc = &followparent_recalc, |
| 1556 | }; | 1482 | }; |
| 1557 | 1483 | ||
| 1558 | static struct clk uart1_fck = { | 1484 | static struct clk uart1_fck = { |
| 1559 | .name = "uart1_fck", | 1485 | .name = "uart1_fck", |
| 1486 | .ops = &clkops_omap2_dflt_wait, | ||
| 1560 | .parent = &core_48m_fck, | 1487 | .parent = &core_48m_fck, |
| 1561 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1488 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1562 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | 1489 | .enable_bit = OMAP3430_EN_UART1_SHIFT, |
| 1563 | .flags = CLOCK_IN_OMAP343X, | ||
| 1564 | .recalc = &followparent_recalc, | 1490 | .recalc = &followparent_recalc, |
| 1565 | }; | 1491 | }; |
| 1566 | 1492 | ||
| 1567 | static struct clk fshostusb_fck = { | 1493 | static struct clk fshostusb_fck = { |
| 1568 | .name = "fshostusb_fck", | 1494 | .name = "fshostusb_fck", |
| 1495 | .ops = &clkops_omap2_dflt_wait, | ||
| 1569 | .parent = &core_48m_fck, | 1496 | .parent = &core_48m_fck, |
| 1570 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1497 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1571 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | 1498 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, |
| 1572 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1573 | .recalc = &followparent_recalc, | 1499 | .recalc = &followparent_recalc, |
| 1574 | }; | 1500 | }; |
| 1575 | 1501 | ||
| @@ -1577,19 +1503,18 @@ static struct clk fshostusb_fck = { | |||
| 1577 | 1503 | ||
| 1578 | static struct clk core_12m_fck = { | 1504 | static struct clk core_12m_fck = { |
| 1579 | .name = "core_12m_fck", | 1505 | .name = "core_12m_fck", |
| 1506 | .ops = &clkops_null, | ||
| 1580 | .parent = &omap_12m_fck, | 1507 | .parent = &omap_12m_fck, |
| 1581 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1582 | PARENT_CONTROLS_CLOCK, | ||
| 1583 | .clkdm_name = "core_l4_clkdm", | 1508 | .clkdm_name = "core_l4_clkdm", |
| 1584 | .recalc = &followparent_recalc, | 1509 | .recalc = &followparent_recalc, |
| 1585 | }; | 1510 | }; |
| 1586 | 1511 | ||
| 1587 | static struct clk hdq_fck = { | 1512 | static struct clk hdq_fck = { |
| 1588 | .name = "hdq_fck", | 1513 | .name = "hdq_fck", |
| 1514 | .ops = &clkops_omap2_dflt_wait, | ||
| 1589 | .parent = &core_12m_fck, | 1515 | .parent = &core_12m_fck, |
| 1590 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1516 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1591 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | 1517 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, |
| 1592 | .flags = CLOCK_IN_OMAP343X, | ||
| 1593 | .recalc = &followparent_recalc, | 1518 | .recalc = &followparent_recalc, |
| 1594 | }; | 1519 | }; |
| 1595 | 1520 | ||
| @@ -1612,22 +1537,22 @@ static const struct clksel ssi_ssr_clksel[] = { | |||
| 1612 | 1537 | ||
| 1613 | static struct clk ssi_ssr_fck = { | 1538 | static struct clk ssi_ssr_fck = { |
| 1614 | .name = "ssi_ssr_fck", | 1539 | .name = "ssi_ssr_fck", |
| 1540 | .ops = &clkops_omap2_dflt, | ||
| 1615 | .init = &omap2_init_clksel_parent, | 1541 | .init = &omap2_init_clksel_parent, |
| 1616 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1542 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
| 1617 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | 1543 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
| 1618 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | 1544 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 1619 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, | 1545 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, |
| 1620 | .clksel = ssi_ssr_clksel, | 1546 | .clksel = ssi_ssr_clksel, |
| 1621 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 1622 | .clkdm_name = "core_l4_clkdm", | 1547 | .clkdm_name = "core_l4_clkdm", |
| 1623 | .recalc = &omap2_clksel_recalc, | 1548 | .recalc = &omap2_clksel_recalc, |
| 1624 | }; | 1549 | }; |
| 1625 | 1550 | ||
| 1626 | static struct clk ssi_sst_fck = { | 1551 | static struct clk ssi_sst_fck = { |
| 1627 | .name = "ssi_sst_fck", | 1552 | .name = "ssi_sst_fck", |
| 1553 | .ops = &clkops_null, | ||
| 1628 | .parent = &ssi_ssr_fck, | 1554 | .parent = &ssi_ssr_fck, |
| 1629 | .fixed_div = 2, | 1555 | .fixed_div = 2, |
| 1630 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | ||
| 1631 | .recalc = &omap2_fixed_divisor_recalc, | 1556 | .recalc = &omap2_fixed_divisor_recalc, |
| 1632 | }; | 1557 | }; |
| 1633 | 1558 | ||
| @@ -1641,39 +1566,39 @@ static struct clk ssi_sst_fck = { | |||
| 1641 | */ | 1566 | */ |
| 1642 | static struct clk core_l3_ick = { | 1567 | static struct clk core_l3_ick = { |
| 1643 | .name = "core_l3_ick", | 1568 | .name = "core_l3_ick", |
| 1569 | .ops = &clkops_null, | ||
| 1644 | .parent = &l3_ick, | 1570 | .parent = &l3_ick, |
| 1645 | .init = &omap2_init_clk_clkdm, | 1571 | .init = &omap2_init_clk_clkdm, |
| 1646 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1647 | PARENT_CONTROLS_CLOCK, | ||
| 1648 | .clkdm_name = "core_l3_clkdm", | 1572 | .clkdm_name = "core_l3_clkdm", |
| 1649 | .recalc = &followparent_recalc, | 1573 | .recalc = &followparent_recalc, |
| 1650 | }; | 1574 | }; |
| 1651 | 1575 | ||
| 1652 | static struct clk hsotgusb_ick = { | 1576 | static struct clk hsotgusb_ick = { |
| 1653 | .name = "hsotgusb_ick", | 1577 | .name = "hsotgusb_ick", |
| 1578 | .ops = &clkops_omap2_dflt_wait, | ||
| 1654 | .parent = &core_l3_ick, | 1579 | .parent = &core_l3_ick, |
| 1655 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1580 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1656 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | 1581 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, |
| 1657 | .flags = CLOCK_IN_OMAP343X, | ||
| 1658 | .clkdm_name = "core_l3_clkdm", | 1582 | .clkdm_name = "core_l3_clkdm", |
| 1659 | .recalc = &followparent_recalc, | 1583 | .recalc = &followparent_recalc, |
| 1660 | }; | 1584 | }; |
| 1661 | 1585 | ||
| 1662 | static struct clk sdrc_ick = { | 1586 | static struct clk sdrc_ick = { |
| 1663 | .name = "sdrc_ick", | 1587 | .name = "sdrc_ick", |
| 1588 | .ops = &clkops_omap2_dflt_wait, | ||
| 1664 | .parent = &core_l3_ick, | 1589 | .parent = &core_l3_ick, |
| 1665 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1590 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1666 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, | 1591 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, |
| 1667 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, | 1592 | .flags = ENABLE_ON_INIT, |
| 1668 | .clkdm_name = "core_l3_clkdm", | 1593 | .clkdm_name = "core_l3_clkdm", |
| 1669 | .recalc = &followparent_recalc, | 1594 | .recalc = &followparent_recalc, |
| 1670 | }; | 1595 | }; |
| 1671 | 1596 | ||
| 1672 | static struct clk gpmc_fck = { | 1597 | static struct clk gpmc_fck = { |
| 1673 | .name = "gpmc_fck", | 1598 | .name = "gpmc_fck", |
| 1599 | .ops = &clkops_null, | ||
| 1674 | .parent = &core_l3_ick, | 1600 | .parent = &core_l3_ick, |
| 1675 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | | 1601 | .flags = ENABLE_ON_INIT, /* huh? */ |
| 1676 | ENABLE_ON_INIT, | ||
| 1677 | .clkdm_name = "core_l3_clkdm", | 1602 | .clkdm_name = "core_l3_clkdm", |
| 1678 | .recalc = &followparent_recalc, | 1603 | .recalc = &followparent_recalc, |
| 1679 | }; | 1604 | }; |
| @@ -1682,18 +1607,17 @@ static struct clk gpmc_fck = { | |||
| 1682 | 1607 | ||
| 1683 | static struct clk security_l3_ick = { | 1608 | static struct clk security_l3_ick = { |
| 1684 | .name = "security_l3_ick", | 1609 | .name = "security_l3_ick", |
| 1610 | .ops = &clkops_null, | ||
| 1685 | .parent = &l3_ick, | 1611 | .parent = &l3_ick, |
| 1686 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1687 | PARENT_CONTROLS_CLOCK, | ||
| 1688 | .recalc = &followparent_recalc, | 1612 | .recalc = &followparent_recalc, |
| 1689 | }; | 1613 | }; |
| 1690 | 1614 | ||
| 1691 | static struct clk pka_ick = { | 1615 | static struct clk pka_ick = { |
| 1692 | .name = "pka_ick", | 1616 | .name = "pka_ick", |
| 1617 | .ops = &clkops_omap2_dflt_wait, | ||
| 1693 | .parent = &security_l3_ick, | 1618 | .parent = &security_l3_ick, |
| 1694 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1619 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 1695 | .enable_bit = OMAP3430_EN_PKA_SHIFT, | 1620 | .enable_bit = OMAP3430_EN_PKA_SHIFT, |
| 1696 | .flags = CLOCK_IN_OMAP343X, | ||
| 1697 | .recalc = &followparent_recalc, | 1621 | .recalc = &followparent_recalc, |
| 1698 | }; | 1622 | }; |
| 1699 | 1623 | ||
| @@ -1701,31 +1625,30 @@ static struct clk pka_ick = { | |||
| 1701 | 1625 | ||
| 1702 | static struct clk core_l4_ick = { | 1626 | static struct clk core_l4_ick = { |
| 1703 | .name = "core_l4_ick", | 1627 | .name = "core_l4_ick", |
| 1628 | .ops = &clkops_null, | ||
| 1704 | .parent = &l4_ick, | 1629 | .parent = &l4_ick, |
| 1705 | .init = &omap2_init_clk_clkdm, | 1630 | .init = &omap2_init_clk_clkdm, |
| 1706 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1707 | PARENT_CONTROLS_CLOCK, | ||
| 1708 | .clkdm_name = "core_l4_clkdm", | 1631 | .clkdm_name = "core_l4_clkdm", |
| 1709 | .recalc = &followparent_recalc, | 1632 | .recalc = &followparent_recalc, |
| 1710 | }; | 1633 | }; |
| 1711 | 1634 | ||
| 1712 | static struct clk usbtll_ick = { | 1635 | static struct clk usbtll_ick = { |
| 1713 | .name = "usbtll_ick", | 1636 | .name = "usbtll_ick", |
| 1637 | .ops = &clkops_omap2_dflt_wait, | ||
| 1714 | .parent = &core_l4_ick, | 1638 | .parent = &core_l4_ick, |
| 1715 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | 1639 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
| 1716 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | 1640 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, |
| 1717 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1718 | .clkdm_name = "core_l4_clkdm", | 1641 | .clkdm_name = "core_l4_clkdm", |
| 1719 | .recalc = &followparent_recalc, | 1642 | .recalc = &followparent_recalc, |
| 1720 | }; | 1643 | }; |
| 1721 | 1644 | ||
| 1722 | static struct clk mmchs3_ick = { | 1645 | static struct clk mmchs3_ick = { |
| 1723 | .name = "mmchs_ick", | 1646 | .name = "mmchs_ick", |
| 1647 | .ops = &clkops_omap2_dflt_wait, | ||
| 1724 | .id = 2, | 1648 | .id = 2, |
| 1725 | .parent = &core_l4_ick, | 1649 | .parent = &core_l4_ick, |
| 1726 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1650 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1727 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | 1651 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, |
| 1728 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 1729 | .clkdm_name = "core_l4_clkdm", | 1652 | .clkdm_name = "core_l4_clkdm", |
| 1730 | .recalc = &followparent_recalc, | 1653 | .recalc = &followparent_recalc, |
| 1731 | }; | 1654 | }; |
| @@ -1733,250 +1656,251 @@ static struct clk mmchs3_ick = { | |||
| 1733 | /* Intersystem Communication Registers - chassis mode only */ | 1656 | /* Intersystem Communication Registers - chassis mode only */ |
| 1734 | static struct clk icr_ick = { | 1657 | static struct clk icr_ick = { |
| 1735 | .name = "icr_ick", | 1658 | .name = "icr_ick", |
| 1659 | .ops = &clkops_omap2_dflt_wait, | ||
| 1736 | .parent = &core_l4_ick, | 1660 | .parent = &core_l4_ick, |
| 1737 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1661 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1738 | .enable_bit = OMAP3430_EN_ICR_SHIFT, | 1662 | .enable_bit = OMAP3430_EN_ICR_SHIFT, |
| 1739 | .flags = CLOCK_IN_OMAP343X, | ||
| 1740 | .clkdm_name = "core_l4_clkdm", | 1663 | .clkdm_name = "core_l4_clkdm", |
| 1741 | .recalc = &followparent_recalc, | 1664 | .recalc = &followparent_recalc, |
| 1742 | }; | 1665 | }; |
| 1743 | 1666 | ||
| 1744 | static struct clk aes2_ick = { | 1667 | static struct clk aes2_ick = { |
| 1745 | .name = "aes2_ick", | 1668 | .name = "aes2_ick", |
| 1669 | .ops = &clkops_omap2_dflt_wait, | ||
| 1746 | .parent = &core_l4_ick, | 1670 | .parent = &core_l4_ick, |
| 1747 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1671 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1748 | .enable_bit = OMAP3430_EN_AES2_SHIFT, | 1672 | .enable_bit = OMAP3430_EN_AES2_SHIFT, |
| 1749 | .flags = CLOCK_IN_OMAP343X, | ||
| 1750 | .clkdm_name = "core_l4_clkdm", | 1673 | .clkdm_name = "core_l4_clkdm", |
| 1751 | .recalc = &followparent_recalc, | 1674 | .recalc = &followparent_recalc, |
| 1752 | }; | 1675 | }; |
| 1753 | 1676 | ||
| 1754 | static struct clk sha12_ick = { | 1677 | static struct clk sha12_ick = { |
| 1755 | .name = "sha12_ick", | 1678 | .name = "sha12_ick", |
| 1679 | .ops = &clkops_omap2_dflt_wait, | ||
| 1756 | .parent = &core_l4_ick, | 1680 | .parent = &core_l4_ick, |
| 1757 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1681 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1758 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, | 1682 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, |
| 1759 | .flags = CLOCK_IN_OMAP343X, | ||
| 1760 | .clkdm_name = "core_l4_clkdm", | 1683 | .clkdm_name = "core_l4_clkdm", |
| 1761 | .recalc = &followparent_recalc, | 1684 | .recalc = &followparent_recalc, |
| 1762 | }; | 1685 | }; |
| 1763 | 1686 | ||
| 1764 | static struct clk des2_ick = { | 1687 | static struct clk des2_ick = { |
| 1765 | .name = "des2_ick", | 1688 | .name = "des2_ick", |
| 1689 | .ops = &clkops_omap2_dflt_wait, | ||
| 1766 | .parent = &core_l4_ick, | 1690 | .parent = &core_l4_ick, |
| 1767 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1691 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1768 | .enable_bit = OMAP3430_EN_DES2_SHIFT, | 1692 | .enable_bit = OMAP3430_EN_DES2_SHIFT, |
| 1769 | .flags = CLOCK_IN_OMAP343X, | ||
| 1770 | .clkdm_name = "core_l4_clkdm", | 1693 | .clkdm_name = "core_l4_clkdm", |
| 1771 | .recalc = &followparent_recalc, | 1694 | .recalc = &followparent_recalc, |
| 1772 | }; | 1695 | }; |
| 1773 | 1696 | ||
| 1774 | static struct clk mmchs2_ick = { | 1697 | static struct clk mmchs2_ick = { |
| 1775 | .name = "mmchs_ick", | 1698 | .name = "mmchs_ick", |
| 1699 | .ops = &clkops_omap2_dflt_wait, | ||
| 1776 | .id = 1, | 1700 | .id = 1, |
| 1777 | .parent = &core_l4_ick, | 1701 | .parent = &core_l4_ick, |
| 1778 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1702 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1779 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | 1703 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, |
| 1780 | .flags = CLOCK_IN_OMAP343X, | ||
| 1781 | .clkdm_name = "core_l4_clkdm", | 1704 | .clkdm_name = "core_l4_clkdm", |
| 1782 | .recalc = &followparent_recalc, | 1705 | .recalc = &followparent_recalc, |
| 1783 | }; | 1706 | }; |
| 1784 | 1707 | ||
| 1785 | static struct clk mmchs1_ick = { | 1708 | static struct clk mmchs1_ick = { |
| 1786 | .name = "mmchs_ick", | 1709 | .name = "mmchs_ick", |
| 1710 | .ops = &clkops_omap2_dflt_wait, | ||
| 1787 | .parent = &core_l4_ick, | 1711 | .parent = &core_l4_ick, |
| 1788 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1712 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1789 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | 1713 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, |
| 1790 | .flags = CLOCK_IN_OMAP343X, | ||
| 1791 | .clkdm_name = "core_l4_clkdm", | 1714 | .clkdm_name = "core_l4_clkdm", |
| 1792 | .recalc = &followparent_recalc, | 1715 | .recalc = &followparent_recalc, |
| 1793 | }; | 1716 | }; |
| 1794 | 1717 | ||
| 1795 | static struct clk mspro_ick = { | 1718 | static struct clk mspro_ick = { |
| 1796 | .name = "mspro_ick", | 1719 | .name = "mspro_ick", |
| 1720 | .ops = &clkops_omap2_dflt_wait, | ||
| 1797 | .parent = &core_l4_ick, | 1721 | .parent = &core_l4_ick, |
| 1798 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1722 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1799 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | 1723 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, |
| 1800 | .flags = CLOCK_IN_OMAP343X, | ||
| 1801 | .clkdm_name = "core_l4_clkdm", | 1724 | .clkdm_name = "core_l4_clkdm", |
| 1802 | .recalc = &followparent_recalc, | 1725 | .recalc = &followparent_recalc, |
| 1803 | }; | 1726 | }; |
| 1804 | 1727 | ||
| 1805 | static struct clk hdq_ick = { | 1728 | static struct clk hdq_ick = { |
| 1806 | .name = "hdq_ick", | 1729 | .name = "hdq_ick", |
| 1730 | .ops = &clkops_omap2_dflt_wait, | ||
| 1807 | .parent = &core_l4_ick, | 1731 | .parent = &core_l4_ick, |
| 1808 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1732 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1809 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | 1733 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, |
| 1810 | .flags = CLOCK_IN_OMAP343X, | ||
| 1811 | .clkdm_name = "core_l4_clkdm", | 1734 | .clkdm_name = "core_l4_clkdm", |
| 1812 | .recalc = &followparent_recalc, | 1735 | .recalc = &followparent_recalc, |
| 1813 | }; | 1736 | }; |
| 1814 | 1737 | ||
| 1815 | static struct clk mcspi4_ick = { | 1738 | static struct clk mcspi4_ick = { |
| 1816 | .name = "mcspi_ick", | 1739 | .name = "mcspi_ick", |
| 1740 | .ops = &clkops_omap2_dflt_wait, | ||
| 1817 | .id = 4, | 1741 | .id = 4, |
| 1818 | .parent = &core_l4_ick, | 1742 | .parent = &core_l4_ick, |
| 1819 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1743 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1820 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | 1744 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, |
| 1821 | .flags = CLOCK_IN_OMAP343X, | ||
| 1822 | .clkdm_name = "core_l4_clkdm", | 1745 | .clkdm_name = "core_l4_clkdm", |
| 1823 | .recalc = &followparent_recalc, | 1746 | .recalc = &followparent_recalc, |
| 1824 | }; | 1747 | }; |
| 1825 | 1748 | ||
| 1826 | static struct clk mcspi3_ick = { | 1749 | static struct clk mcspi3_ick = { |
| 1827 | .name = "mcspi_ick", | 1750 | .name = "mcspi_ick", |
| 1751 | .ops = &clkops_omap2_dflt_wait, | ||
| 1828 | .id = 3, | 1752 | .id = 3, |
| 1829 | .parent = &core_l4_ick, | 1753 | .parent = &core_l4_ick, |
| 1830 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1754 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1831 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | 1755 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, |
| 1832 | .flags = CLOCK_IN_OMAP343X, | ||
| 1833 | .clkdm_name = "core_l4_clkdm", | 1756 | .clkdm_name = "core_l4_clkdm", |
| 1834 | .recalc = &followparent_recalc, | 1757 | .recalc = &followparent_recalc, |
| 1835 | }; | 1758 | }; |
| 1836 | 1759 | ||
| 1837 | static struct clk mcspi2_ick = { | 1760 | static struct clk mcspi2_ick = { |
| 1838 | .name = "mcspi_ick", | 1761 | .name = "mcspi_ick", |
| 1762 | .ops = &clkops_omap2_dflt_wait, | ||
| 1839 | .id = 2, | 1763 | .id = 2, |
| 1840 | .parent = &core_l4_ick, | 1764 | .parent = &core_l4_ick, |
| 1841 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1765 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1842 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | 1766 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, |
| 1843 | .flags = CLOCK_IN_OMAP343X, | ||
| 1844 | .clkdm_name = "core_l4_clkdm", | 1767 | .clkdm_name = "core_l4_clkdm", |
| 1845 | .recalc = &followparent_recalc, | 1768 | .recalc = &followparent_recalc, |
| 1846 | }; | 1769 | }; |
| 1847 | 1770 | ||
| 1848 | static struct clk mcspi1_ick = { | 1771 | static struct clk mcspi1_ick = { |
| 1849 | .name = "mcspi_ick", | 1772 | .name = "mcspi_ick", |
| 1773 | .ops = &clkops_omap2_dflt_wait, | ||
| 1850 | .id = 1, | 1774 | .id = 1, |
| 1851 | .parent = &core_l4_ick, | 1775 | .parent = &core_l4_ick, |
| 1852 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1776 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1853 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | 1777 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, |
| 1854 | .flags = CLOCK_IN_OMAP343X, | ||
| 1855 | .clkdm_name = "core_l4_clkdm", | 1778 | .clkdm_name = "core_l4_clkdm", |
| 1856 | .recalc = &followparent_recalc, | 1779 | .recalc = &followparent_recalc, |
| 1857 | }; | 1780 | }; |
| 1858 | 1781 | ||
| 1859 | static struct clk i2c3_ick = { | 1782 | static struct clk i2c3_ick = { |
| 1860 | .name = "i2c_ick", | 1783 | .name = "i2c_ick", |
| 1784 | .ops = &clkops_omap2_dflt_wait, | ||
| 1861 | .id = 3, | 1785 | .id = 3, |
| 1862 | .parent = &core_l4_ick, | 1786 | .parent = &core_l4_ick, |
| 1863 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1787 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1864 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | 1788 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, |
| 1865 | .flags = CLOCK_IN_OMAP343X, | ||
| 1866 | .clkdm_name = "core_l4_clkdm", | 1789 | .clkdm_name = "core_l4_clkdm", |
| 1867 | .recalc = &followparent_recalc, | 1790 | .recalc = &followparent_recalc, |
| 1868 | }; | 1791 | }; |
| 1869 | 1792 | ||
| 1870 | static struct clk i2c2_ick = { | 1793 | static struct clk i2c2_ick = { |
| 1871 | .name = "i2c_ick", | 1794 | .name = "i2c_ick", |
| 1795 | .ops = &clkops_omap2_dflt_wait, | ||
| 1872 | .id = 2, | 1796 | .id = 2, |
| 1873 | .parent = &core_l4_ick, | 1797 | .parent = &core_l4_ick, |
| 1874 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1798 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1875 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | 1799 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, |
| 1876 | .flags = CLOCK_IN_OMAP343X, | ||
| 1877 | .clkdm_name = "core_l4_clkdm", | 1800 | .clkdm_name = "core_l4_clkdm", |
| 1878 | .recalc = &followparent_recalc, | 1801 | .recalc = &followparent_recalc, |
| 1879 | }; | 1802 | }; |
| 1880 | 1803 | ||
| 1881 | static struct clk i2c1_ick = { | 1804 | static struct clk i2c1_ick = { |
| 1882 | .name = "i2c_ick", | 1805 | .name = "i2c_ick", |
| 1806 | .ops = &clkops_omap2_dflt_wait, | ||
| 1883 | .id = 1, | 1807 | .id = 1, |
| 1884 | .parent = &core_l4_ick, | 1808 | .parent = &core_l4_ick, |
| 1885 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1809 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1886 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | 1810 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, |
| 1887 | .flags = CLOCK_IN_OMAP343X, | ||
| 1888 | .clkdm_name = "core_l4_clkdm", | 1811 | .clkdm_name = "core_l4_clkdm", |
| 1889 | .recalc = &followparent_recalc, | 1812 | .recalc = &followparent_recalc, |
| 1890 | }; | 1813 | }; |
| 1891 | 1814 | ||
| 1892 | static struct clk uart2_ick = { | 1815 | static struct clk uart2_ick = { |
| 1893 | .name = "uart2_ick", | 1816 | .name = "uart2_ick", |
| 1817 | .ops = &clkops_omap2_dflt_wait, | ||
| 1894 | .parent = &core_l4_ick, | 1818 | .parent = &core_l4_ick, |
| 1895 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1819 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1896 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | 1820 | .enable_bit = OMAP3430_EN_UART2_SHIFT, |
| 1897 | .flags = CLOCK_IN_OMAP343X, | ||
| 1898 | .clkdm_name = "core_l4_clkdm", | 1821 | .clkdm_name = "core_l4_clkdm", |
| 1899 | .recalc = &followparent_recalc, | 1822 | .recalc = &followparent_recalc, |
| 1900 | }; | 1823 | }; |
| 1901 | 1824 | ||
| 1902 | static struct clk uart1_ick = { | 1825 | static struct clk uart1_ick = { |
| 1903 | .name = "uart1_ick", | 1826 | .name = "uart1_ick", |
| 1827 | .ops = &clkops_omap2_dflt_wait, | ||
| 1904 | .parent = &core_l4_ick, | 1828 | .parent = &core_l4_ick, |
| 1905 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1829 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1906 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | 1830 | .enable_bit = OMAP3430_EN_UART1_SHIFT, |
| 1907 | .flags = CLOCK_IN_OMAP343X, | ||
| 1908 | .clkdm_name = "core_l4_clkdm", | 1831 | .clkdm_name = "core_l4_clkdm", |
| 1909 | .recalc = &followparent_recalc, | 1832 | .recalc = &followparent_recalc, |
| 1910 | }; | 1833 | }; |
| 1911 | 1834 | ||
| 1912 | static struct clk gpt11_ick = { | 1835 | static struct clk gpt11_ick = { |
| 1913 | .name = "gpt11_ick", | 1836 | .name = "gpt11_ick", |
| 1837 | .ops = &clkops_omap2_dflt_wait, | ||
| 1914 | .parent = &core_l4_ick, | 1838 | .parent = &core_l4_ick, |
| 1915 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1839 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1916 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | 1840 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, |
| 1917 | .flags = CLOCK_IN_OMAP343X, | ||
| 1918 | .clkdm_name = "core_l4_clkdm", | 1841 | .clkdm_name = "core_l4_clkdm", |
| 1919 | .recalc = &followparent_recalc, | 1842 | .recalc = &followparent_recalc, |
| 1920 | }; | 1843 | }; |
| 1921 | 1844 | ||
| 1922 | static struct clk gpt10_ick = { | 1845 | static struct clk gpt10_ick = { |
| 1923 | .name = "gpt10_ick", | 1846 | .name = "gpt10_ick", |
| 1847 | .ops = &clkops_omap2_dflt_wait, | ||
| 1924 | .parent = &core_l4_ick, | 1848 | .parent = &core_l4_ick, |
| 1925 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1849 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1926 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | 1850 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, |
| 1927 | .flags = CLOCK_IN_OMAP343X, | ||
| 1928 | .clkdm_name = "core_l4_clkdm", | 1851 | .clkdm_name = "core_l4_clkdm", |
| 1929 | .recalc = &followparent_recalc, | 1852 | .recalc = &followparent_recalc, |
| 1930 | }; | 1853 | }; |
| 1931 | 1854 | ||
| 1932 | static struct clk mcbsp5_ick = { | 1855 | static struct clk mcbsp5_ick = { |
| 1933 | .name = "mcbsp_ick", | 1856 | .name = "mcbsp_ick", |
| 1857 | .ops = &clkops_omap2_dflt_wait, | ||
| 1934 | .id = 5, | 1858 | .id = 5, |
| 1935 | .parent = &core_l4_ick, | 1859 | .parent = &core_l4_ick, |
| 1936 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1860 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1937 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | 1861 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, |
| 1938 | .flags = CLOCK_IN_OMAP343X, | ||
| 1939 | .clkdm_name = "core_l4_clkdm", | 1862 | .clkdm_name = "core_l4_clkdm", |
| 1940 | .recalc = &followparent_recalc, | 1863 | .recalc = &followparent_recalc, |
| 1941 | }; | 1864 | }; |
| 1942 | 1865 | ||
| 1943 | static struct clk mcbsp1_ick = { | 1866 | static struct clk mcbsp1_ick = { |
| 1944 | .name = "mcbsp_ick", | 1867 | .name = "mcbsp_ick", |
| 1868 | .ops = &clkops_omap2_dflt_wait, | ||
| 1945 | .id = 1, | 1869 | .id = 1, |
| 1946 | .parent = &core_l4_ick, | 1870 | .parent = &core_l4_ick, |
| 1947 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1871 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1948 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | 1872 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, |
| 1949 | .flags = CLOCK_IN_OMAP343X, | ||
| 1950 | .clkdm_name = "core_l4_clkdm", | 1873 | .clkdm_name = "core_l4_clkdm", |
| 1951 | .recalc = &followparent_recalc, | 1874 | .recalc = &followparent_recalc, |
| 1952 | }; | 1875 | }; |
| 1953 | 1876 | ||
| 1954 | static struct clk fac_ick = { | 1877 | static struct clk fac_ick = { |
| 1955 | .name = "fac_ick", | 1878 | .name = "fac_ick", |
| 1879 | .ops = &clkops_omap2_dflt_wait, | ||
| 1956 | .parent = &core_l4_ick, | 1880 | .parent = &core_l4_ick, |
| 1957 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1881 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1958 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, | 1882 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, |
| 1959 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 1960 | .clkdm_name = "core_l4_clkdm", | 1883 | .clkdm_name = "core_l4_clkdm", |
| 1961 | .recalc = &followparent_recalc, | 1884 | .recalc = &followparent_recalc, |
| 1962 | }; | 1885 | }; |
| 1963 | 1886 | ||
| 1964 | static struct clk mailboxes_ick = { | 1887 | static struct clk mailboxes_ick = { |
| 1965 | .name = "mailboxes_ick", | 1888 | .name = "mailboxes_ick", |
| 1889 | .ops = &clkops_omap2_dflt_wait, | ||
| 1966 | .parent = &core_l4_ick, | 1890 | .parent = &core_l4_ick, |
| 1967 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1891 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1968 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, | 1892 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, |
| 1969 | .flags = CLOCK_IN_OMAP343X, | ||
| 1970 | .clkdm_name = "core_l4_clkdm", | 1893 | .clkdm_name = "core_l4_clkdm", |
| 1971 | .recalc = &followparent_recalc, | 1894 | .recalc = &followparent_recalc, |
| 1972 | }; | 1895 | }; |
| 1973 | 1896 | ||
| 1974 | static struct clk omapctrl_ick = { | 1897 | static struct clk omapctrl_ick = { |
| 1975 | .name = "omapctrl_ick", | 1898 | .name = "omapctrl_ick", |
| 1899 | .ops = &clkops_omap2_dflt_wait, | ||
| 1976 | .parent = &core_l4_ick, | 1900 | .parent = &core_l4_ick, |
| 1977 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1901 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1978 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, | 1902 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, |
| 1979 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, | 1903 | .flags = ENABLE_ON_INIT, |
| 1980 | .recalc = &followparent_recalc, | 1904 | .recalc = &followparent_recalc, |
| 1981 | }; | 1905 | }; |
| 1982 | 1906 | ||
| @@ -1984,19 +1908,18 @@ static struct clk omapctrl_ick = { | |||
| 1984 | 1908 | ||
| 1985 | static struct clk ssi_l4_ick = { | 1909 | static struct clk ssi_l4_ick = { |
| 1986 | .name = "ssi_l4_ick", | 1910 | .name = "ssi_l4_ick", |
| 1911 | .ops = &clkops_null, | ||
| 1987 | .parent = &l4_ick, | 1912 | .parent = &l4_ick, |
| 1988 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 1989 | PARENT_CONTROLS_CLOCK, | ||
| 1990 | .clkdm_name = "core_l4_clkdm", | 1913 | .clkdm_name = "core_l4_clkdm", |
| 1991 | .recalc = &followparent_recalc, | 1914 | .recalc = &followparent_recalc, |
| 1992 | }; | 1915 | }; |
| 1993 | 1916 | ||
| 1994 | static struct clk ssi_ick = { | 1917 | static struct clk ssi_ick = { |
| 1995 | .name = "ssi_ick", | 1918 | .name = "ssi_ick", |
| 1919 | .ops = &clkops_omap2_dflt, | ||
| 1996 | .parent = &ssi_l4_ick, | 1920 | .parent = &ssi_l4_ick, |
| 1997 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1921 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| 1998 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | 1922 | .enable_bit = OMAP3430_EN_SSI_SHIFT, |
| 1999 | .flags = CLOCK_IN_OMAP343X, | ||
| 2000 | .clkdm_name = "core_l4_clkdm", | 1923 | .clkdm_name = "core_l4_clkdm", |
| 2001 | .recalc = &followparent_recalc, | 1924 | .recalc = &followparent_recalc, |
| 2002 | }; | 1925 | }; |
| @@ -2011,6 +1934,7 @@ static const struct clksel usb_l4_clksel[] = { | |||
| 2011 | 1934 | ||
| 2012 | static struct clk usb_l4_ick = { | 1935 | static struct clk usb_l4_ick = { |
| 2013 | .name = "usb_l4_ick", | 1936 | .name = "usb_l4_ick", |
| 1937 | .ops = &clkops_omap2_dflt_wait, | ||
| 2014 | .parent = &l4_ick, | 1938 | .parent = &l4_ick, |
| 2015 | .init = &omap2_init_clksel_parent, | 1939 | .init = &omap2_init_clksel_parent, |
| 2016 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1940 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
| @@ -2018,7 +1942,6 @@ static struct clk usb_l4_ick = { | |||
| 2018 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | 1942 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), |
| 2019 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, | 1943 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, |
| 2020 | .clksel = usb_l4_clksel, | 1944 | .clksel = usb_l4_clksel, |
| 2021 | .flags = CLOCK_IN_OMAP3430ES1, | ||
| 2022 | .recalc = &omap2_clksel_recalc, | 1945 | .recalc = &omap2_clksel_recalc, |
| 2023 | }; | 1946 | }; |
| 2024 | 1947 | ||
| @@ -2028,98 +1951,87 @@ static struct clk usb_l4_ick = { | |||
| 2028 | 1951 | ||
| 2029 | static struct clk security_l4_ick2 = { | 1952 | static struct clk security_l4_ick2 = { |
| 2030 | .name = "security_l4_ick2", | 1953 | .name = "security_l4_ick2", |
| 1954 | .ops = &clkops_null, | ||
| 2031 | .parent = &l4_ick, | 1955 | .parent = &l4_ick, |
| 2032 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 2033 | PARENT_CONTROLS_CLOCK, | ||
| 2034 | .recalc = &followparent_recalc, | 1956 | .recalc = &followparent_recalc, |
| 2035 | }; | 1957 | }; |
| 2036 | 1958 | ||
| 2037 | static struct clk aes1_ick = { | 1959 | static struct clk aes1_ick = { |
| 2038 | .name = "aes1_ick", | 1960 | .name = "aes1_ick", |
| 1961 | .ops = &clkops_omap2_dflt_wait, | ||
| 2039 | .parent = &security_l4_ick2, | 1962 | .parent = &security_l4_ick2, |
| 2040 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1963 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2041 | .enable_bit = OMAP3430_EN_AES1_SHIFT, | 1964 | .enable_bit = OMAP3430_EN_AES1_SHIFT, |
| 2042 | .flags = CLOCK_IN_OMAP343X, | ||
| 2043 | .recalc = &followparent_recalc, | 1965 | .recalc = &followparent_recalc, |
| 2044 | }; | 1966 | }; |
| 2045 | 1967 | ||
| 2046 | static struct clk rng_ick = { | 1968 | static struct clk rng_ick = { |
| 2047 | .name = "rng_ick", | 1969 | .name = "rng_ick", |
| 1970 | .ops = &clkops_omap2_dflt_wait, | ||
| 2048 | .parent = &security_l4_ick2, | 1971 | .parent = &security_l4_ick2, |
| 2049 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1972 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2050 | .enable_bit = OMAP3430_EN_RNG_SHIFT, | 1973 | .enable_bit = OMAP3430_EN_RNG_SHIFT, |
| 2051 | .flags = CLOCK_IN_OMAP343X, | ||
| 2052 | .recalc = &followparent_recalc, | 1974 | .recalc = &followparent_recalc, |
| 2053 | }; | 1975 | }; |
| 2054 | 1976 | ||
| 2055 | static struct clk sha11_ick = { | 1977 | static struct clk sha11_ick = { |
| 2056 | .name = "sha11_ick", | 1978 | .name = "sha11_ick", |
| 1979 | .ops = &clkops_omap2_dflt_wait, | ||
| 2057 | .parent = &security_l4_ick2, | 1980 | .parent = &security_l4_ick2, |
| 2058 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1981 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2059 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, | 1982 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, |
| 2060 | .flags = CLOCK_IN_OMAP343X, | ||
| 2061 | .recalc = &followparent_recalc, | 1983 | .recalc = &followparent_recalc, |
| 2062 | }; | 1984 | }; |
| 2063 | 1985 | ||
| 2064 | static struct clk des1_ick = { | 1986 | static struct clk des1_ick = { |
| 2065 | .name = "des1_ick", | 1987 | .name = "des1_ick", |
| 1988 | .ops = &clkops_omap2_dflt_wait, | ||
| 2066 | .parent = &security_l4_ick2, | 1989 | .parent = &security_l4_ick2, |
| 2067 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1990 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
| 2068 | .enable_bit = OMAP3430_EN_DES1_SHIFT, | 1991 | .enable_bit = OMAP3430_EN_DES1_SHIFT, |
| 2069 | .flags = CLOCK_IN_OMAP343X, | ||
| 2070 | .recalc = &followparent_recalc, | 1992 | .recalc = &followparent_recalc, |
| 2071 | }; | 1993 | }; |
| 2072 | 1994 | ||
| 2073 | /* DSS */ | 1995 | /* DSS */ |
| 2074 | static const struct clksel dss1_alwon_fck_clksel[] = { | ||
| 2075 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 2076 | { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, | ||
| 2077 | { .parent = NULL } | ||
| 2078 | }; | ||
| 2079 | |||
| 2080 | static struct clk dss1_alwon_fck = { | 1996 | static struct clk dss1_alwon_fck = { |
| 2081 | .name = "dss1_alwon_fck", | 1997 | .name = "dss1_alwon_fck", |
| 1998 | .ops = &clkops_omap2_dflt, | ||
| 2082 | .parent = &dpll4_m4x2_ck, | 1999 | .parent = &dpll4_m4x2_ck, |
| 2083 | .init = &omap2_init_clksel_parent, | ||
| 2084 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2000 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2085 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, | 2001 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, |
| 2086 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 2087 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, | ||
| 2088 | .clksel = dss1_alwon_fck_clksel, | ||
| 2089 | .flags = CLOCK_IN_OMAP343X, | ||
| 2090 | .clkdm_name = "dss_clkdm", | 2002 | .clkdm_name = "dss_clkdm", |
| 2091 | .recalc = &omap2_clksel_recalc, | 2003 | .recalc = &followparent_recalc, |
| 2092 | }; | 2004 | }; |
| 2093 | 2005 | ||
| 2094 | static struct clk dss_tv_fck = { | 2006 | static struct clk dss_tv_fck = { |
| 2095 | .name = "dss_tv_fck", | 2007 | .name = "dss_tv_fck", |
| 2008 | .ops = &clkops_omap2_dflt, | ||
| 2096 | .parent = &omap_54m_fck, | 2009 | .parent = &omap_54m_fck, |
| 2097 | .init = &omap2_init_clk_clkdm, | 2010 | .init = &omap2_init_clk_clkdm, |
| 2098 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2011 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2099 | .enable_bit = OMAP3430_EN_TV_SHIFT, | 2012 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
| 2100 | .flags = CLOCK_IN_OMAP343X, | ||
| 2101 | .clkdm_name = "dss_clkdm", | 2013 | .clkdm_name = "dss_clkdm", |
| 2102 | .recalc = &followparent_recalc, | 2014 | .recalc = &followparent_recalc, |
| 2103 | }; | 2015 | }; |
| 2104 | 2016 | ||
| 2105 | static struct clk dss_96m_fck = { | 2017 | static struct clk dss_96m_fck = { |
| 2106 | .name = "dss_96m_fck", | 2018 | .name = "dss_96m_fck", |
| 2019 | .ops = &clkops_omap2_dflt, | ||
| 2107 | .parent = &omap_96m_fck, | 2020 | .parent = &omap_96m_fck, |
| 2108 | .init = &omap2_init_clk_clkdm, | 2021 | .init = &omap2_init_clk_clkdm, |
| 2109 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2022 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2110 | .enable_bit = OMAP3430_EN_TV_SHIFT, | 2023 | .enable_bit = OMAP3430_EN_TV_SHIFT, |
| 2111 | .flags = CLOCK_IN_OMAP343X, | ||
| 2112 | .clkdm_name = "dss_clkdm", | 2024 | .clkdm_name = "dss_clkdm", |
| 2113 | .recalc = &followparent_recalc, | 2025 | .recalc = &followparent_recalc, |
| 2114 | }; | 2026 | }; |
| 2115 | 2027 | ||
| 2116 | static struct clk dss2_alwon_fck = { | 2028 | static struct clk dss2_alwon_fck = { |
| 2117 | .name = "dss2_alwon_fck", | 2029 | .name = "dss2_alwon_fck", |
| 2030 | .ops = &clkops_omap2_dflt, | ||
| 2118 | .parent = &sys_ck, | 2031 | .parent = &sys_ck, |
| 2119 | .init = &omap2_init_clk_clkdm, | 2032 | .init = &omap2_init_clk_clkdm, |
| 2120 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | 2033 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
| 2121 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, | 2034 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, |
| 2122 | .flags = CLOCK_IN_OMAP343X, | ||
| 2123 | .clkdm_name = "dss_clkdm", | 2035 | .clkdm_name = "dss_clkdm", |
| 2124 | .recalc = &followparent_recalc, | 2036 | .recalc = &followparent_recalc, |
| 2125 | }; | 2037 | }; |
| @@ -2127,45 +2039,46 @@ static struct clk dss2_alwon_fck = { | |||
| 2127 | static struct clk dss_ick = { | 2039 | static struct clk dss_ick = { |
| 2128 | /* Handles both L3 and L4 clocks */ | 2040 | /* Handles both L3 and L4 clocks */ |
| 2129 | .name = "dss_ick", | 2041 | .name = "dss_ick", |
| 2042 | .ops = &clkops_omap2_dflt, | ||
| 2130 | .parent = &l4_ick, | 2043 | .parent = &l4_ick, |
| 2131 | .init = &omap2_init_clk_clkdm, | 2044 | .init = &omap2_init_clk_clkdm, |
| 2132 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | 2045 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), |
| 2133 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | 2046 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, |
| 2134 | .flags = CLOCK_IN_OMAP343X, | ||
| 2135 | .clkdm_name = "dss_clkdm", | 2047 | .clkdm_name = "dss_clkdm", |
| 2136 | .recalc = &followparent_recalc, | 2048 | .recalc = &followparent_recalc, |
| 2137 | }; | 2049 | }; |
| 2138 | 2050 | ||
| 2139 | /* CAM */ | 2051 | /* CAM */ |
| 2140 | 2052 | ||
| 2141 | static const struct clksel cam_mclk_clksel[] = { | ||
| 2142 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | ||
| 2143 | { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, | ||
| 2144 | { .parent = NULL } | ||
| 2145 | }; | ||
| 2146 | |||
| 2147 | static struct clk cam_mclk = { | 2053 | static struct clk cam_mclk = { |
| 2148 | .name = "cam_mclk", | 2054 | .name = "cam_mclk", |
| 2055 | .ops = &clkops_omap2_dflt_wait, | ||
| 2149 | .parent = &dpll4_m5x2_ck, | 2056 | .parent = &dpll4_m5x2_ck, |
| 2150 | .init = &omap2_init_clksel_parent, | ||
| 2151 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | ||
| 2152 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, | ||
| 2153 | .clksel = cam_mclk_clksel, | ||
| 2154 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | 2057 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), |
| 2155 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | 2058 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
| 2156 | .flags = CLOCK_IN_OMAP343X, | ||
| 2157 | .clkdm_name = "cam_clkdm", | 2059 | .clkdm_name = "cam_clkdm", |
| 2158 | .recalc = &omap2_clksel_recalc, | 2060 | .recalc = &followparent_recalc, |
| 2159 | }; | 2061 | }; |
| 2160 | 2062 | ||
| 2161 | static struct clk cam_ick = { | 2063 | static struct clk cam_ick = { |
| 2162 | /* Handles both L3 and L4 clocks */ | 2064 | /* Handles both L3 and L4 clocks */ |
| 2163 | .name = "cam_ick", | 2065 | .name = "cam_ick", |
| 2066 | .ops = &clkops_omap2_dflt_wait, | ||
| 2164 | .parent = &l4_ick, | 2067 | .parent = &l4_ick, |
| 2165 | .init = &omap2_init_clk_clkdm, | 2068 | .init = &omap2_init_clk_clkdm, |
| 2166 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), | 2069 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), |
| 2167 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | 2070 | .enable_bit = OMAP3430_EN_CAM_SHIFT, |
| 2168 | .flags = CLOCK_IN_OMAP343X, | 2071 | .clkdm_name = "cam_clkdm", |
| 2072 | .recalc = &followparent_recalc, | ||
| 2073 | }; | ||
| 2074 | |||
| 2075 | static struct clk csi2_96m_fck = { | ||
| 2076 | .name = "csi2_96m_fck", | ||
| 2077 | .ops = &clkops_omap2_dflt_wait, | ||
| 2078 | .parent = &core_96m_fck, | ||
| 2079 | .init = &omap2_init_clk_clkdm, | ||
| 2080 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | ||
| 2081 | .enable_bit = OMAP3430_EN_CSI2_SHIFT, | ||
| 2169 | .clkdm_name = "cam_clkdm", | 2082 | .clkdm_name = "cam_clkdm", |
| 2170 | .recalc = &followparent_recalc, | 2083 | .recalc = &followparent_recalc, |
| 2171 | }; | 2084 | }; |
| @@ -2174,22 +2087,22 @@ static struct clk cam_ick = { | |||
| 2174 | 2087 | ||
| 2175 | static struct clk usbhost_120m_fck = { | 2088 | static struct clk usbhost_120m_fck = { |
| 2176 | .name = "usbhost_120m_fck", | 2089 | .name = "usbhost_120m_fck", |
| 2177 | .parent = &omap_120m_fck, | 2090 | .ops = &clkops_omap2_dflt_wait, |
| 2091 | .parent = &dpll5_m2_ck, | ||
| 2178 | .init = &omap2_init_clk_clkdm, | 2092 | .init = &omap2_init_clk_clkdm, |
| 2179 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | 2093 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
| 2180 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, | 2094 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, |
| 2181 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2182 | .clkdm_name = "usbhost_clkdm", | 2095 | .clkdm_name = "usbhost_clkdm", |
| 2183 | .recalc = &followparent_recalc, | 2096 | .recalc = &followparent_recalc, |
| 2184 | }; | 2097 | }; |
| 2185 | 2098 | ||
| 2186 | static struct clk usbhost_48m_fck = { | 2099 | static struct clk usbhost_48m_fck = { |
| 2187 | .name = "usbhost_48m_fck", | 2100 | .name = "usbhost_48m_fck", |
| 2101 | .ops = &clkops_omap2_dflt_wait, | ||
| 2188 | .parent = &omap_48m_fck, | 2102 | .parent = &omap_48m_fck, |
| 2189 | .init = &omap2_init_clk_clkdm, | 2103 | .init = &omap2_init_clk_clkdm, |
| 2190 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | 2104 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
| 2191 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, | 2105 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, |
| 2192 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2193 | .clkdm_name = "usbhost_clkdm", | 2106 | .clkdm_name = "usbhost_clkdm", |
| 2194 | .recalc = &followparent_recalc, | 2107 | .recalc = &followparent_recalc, |
| 2195 | }; | 2108 | }; |
| @@ -2197,22 +2110,11 @@ static struct clk usbhost_48m_fck = { | |||
| 2197 | static struct clk usbhost_ick = { | 2110 | static struct clk usbhost_ick = { |
| 2198 | /* Handles both L3 and L4 clocks */ | 2111 | /* Handles both L3 and L4 clocks */ |
| 2199 | .name = "usbhost_ick", | 2112 | .name = "usbhost_ick", |
| 2113 | .ops = &clkops_omap2_dflt_wait, | ||
| 2200 | .parent = &l4_ick, | 2114 | .parent = &l4_ick, |
| 2201 | .init = &omap2_init_clk_clkdm, | 2115 | .init = &omap2_init_clk_clkdm, |
| 2202 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), | 2116 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), |
| 2203 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | 2117 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, |
| 2204 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2205 | .clkdm_name = "usbhost_clkdm", | ||
| 2206 | .recalc = &followparent_recalc, | ||
| 2207 | }; | ||
| 2208 | |||
| 2209 | static struct clk usbhost_sar_fck = { | ||
| 2210 | .name = "usbhost_sar_fck", | ||
| 2211 | .parent = &osc_sys_ck, | ||
| 2212 | .init = &omap2_init_clk_clkdm, | ||
| 2213 | .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), | ||
| 2214 | .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, | ||
| 2215 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2216 | .clkdm_name = "usbhost_clkdm", | 2118 | .clkdm_name = "usbhost_clkdm", |
| 2217 | .recalc = &followparent_recalc, | 2119 | .recalc = &followparent_recalc, |
| 2218 | }; | 2120 | }; |
| @@ -2237,7 +2139,7 @@ static const struct clksel_rate usim_120m_rates[] = { | |||
| 2237 | 2139 | ||
| 2238 | static const struct clksel usim_clksel[] = { | 2140 | static const struct clksel usim_clksel[] = { |
| 2239 | { .parent = &omap_96m_fck, .rates = usim_96m_rates }, | 2141 | { .parent = &omap_96m_fck, .rates = usim_96m_rates }, |
| 2240 | { .parent = &omap_120m_fck, .rates = usim_120m_rates }, | 2142 | { .parent = &dpll5_m2_ck, .rates = usim_120m_rates }, |
| 2241 | { .parent = &sys_ck, .rates = div2_rates }, | 2143 | { .parent = &sys_ck, .rates = div2_rates }, |
| 2242 | { .parent = NULL }, | 2144 | { .parent = NULL }, |
| 2243 | }; | 2145 | }; |
| @@ -2245,63 +2147,63 @@ static const struct clksel usim_clksel[] = { | |||
| 2245 | /* 3430ES2 only */ | 2147 | /* 3430ES2 only */ |
| 2246 | static struct clk usim_fck = { | 2148 | static struct clk usim_fck = { |
| 2247 | .name = "usim_fck", | 2149 | .name = "usim_fck", |
| 2150 | .ops = &clkops_omap2_dflt_wait, | ||
| 2248 | .init = &omap2_init_clksel_parent, | 2151 | .init = &omap2_init_clksel_parent, |
| 2249 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2152 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2250 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | 2153 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, |
| 2251 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | 2154 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 2252 | .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, | 2155 | .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, |
| 2253 | .clksel = usim_clksel, | 2156 | .clksel = usim_clksel, |
| 2254 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2255 | .recalc = &omap2_clksel_recalc, | 2157 | .recalc = &omap2_clksel_recalc, |
| 2256 | }; | 2158 | }; |
| 2257 | 2159 | ||
| 2258 | /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ | 2160 | /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ |
| 2259 | static struct clk gpt1_fck = { | 2161 | static struct clk gpt1_fck = { |
| 2260 | .name = "gpt1_fck", | 2162 | .name = "gpt1_fck", |
| 2163 | .ops = &clkops_omap2_dflt_wait, | ||
| 2261 | .init = &omap2_init_clksel_parent, | 2164 | .init = &omap2_init_clksel_parent, |
| 2262 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2165 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2263 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | 2166 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, |
| 2264 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | 2167 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), |
| 2265 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, | 2168 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, |
| 2266 | .clksel = omap343x_gpt_clksel, | 2169 | .clksel = omap343x_gpt_clksel, |
| 2267 | .flags = CLOCK_IN_OMAP343X, | ||
| 2268 | .clkdm_name = "wkup_clkdm", | 2170 | .clkdm_name = "wkup_clkdm", |
| 2269 | .recalc = &omap2_clksel_recalc, | 2171 | .recalc = &omap2_clksel_recalc, |
| 2270 | }; | 2172 | }; |
| 2271 | 2173 | ||
| 2272 | static struct clk wkup_32k_fck = { | 2174 | static struct clk wkup_32k_fck = { |
| 2273 | .name = "wkup_32k_fck", | 2175 | .name = "wkup_32k_fck", |
| 2176 | .ops = &clkops_null, | ||
| 2274 | .init = &omap2_init_clk_clkdm, | 2177 | .init = &omap2_init_clk_clkdm, |
| 2275 | .parent = &omap_32k_fck, | 2178 | .parent = &omap_32k_fck, |
| 2276 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2277 | .clkdm_name = "wkup_clkdm", | 2179 | .clkdm_name = "wkup_clkdm", |
| 2278 | .recalc = &followparent_recalc, | 2180 | .recalc = &followparent_recalc, |
| 2279 | }; | 2181 | }; |
| 2280 | 2182 | ||
| 2281 | static struct clk gpio1_dbck = { | 2183 | static struct clk gpio1_dbck = { |
| 2282 | .name = "gpio1_dbck", | 2184 | .name = "gpio1_dbck", |
| 2185 | .ops = &clkops_omap2_dflt_wait, | ||
| 2283 | .parent = &wkup_32k_fck, | 2186 | .parent = &wkup_32k_fck, |
| 2284 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2187 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2285 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | 2188 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, |
| 2286 | .flags = CLOCK_IN_OMAP343X, | ||
| 2287 | .clkdm_name = "wkup_clkdm", | 2189 | .clkdm_name = "wkup_clkdm", |
| 2288 | .recalc = &followparent_recalc, | 2190 | .recalc = &followparent_recalc, |
| 2289 | }; | 2191 | }; |
| 2290 | 2192 | ||
| 2291 | static struct clk wdt2_fck = { | 2193 | static struct clk wdt2_fck = { |
| 2292 | .name = "wdt2_fck", | 2194 | .name = "wdt2_fck", |
| 2195 | .ops = &clkops_omap2_dflt_wait, | ||
| 2293 | .parent = &wkup_32k_fck, | 2196 | .parent = &wkup_32k_fck, |
| 2294 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2197 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2295 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | 2198 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, |
| 2296 | .flags = CLOCK_IN_OMAP343X, | ||
| 2297 | .clkdm_name = "wkup_clkdm", | 2199 | .clkdm_name = "wkup_clkdm", |
| 2298 | .recalc = &followparent_recalc, | 2200 | .recalc = &followparent_recalc, |
| 2299 | }; | 2201 | }; |
| 2300 | 2202 | ||
| 2301 | static struct clk wkup_l4_ick = { | 2203 | static struct clk wkup_l4_ick = { |
| 2302 | .name = "wkup_l4_ick", | 2204 | .name = "wkup_l4_ick", |
| 2205 | .ops = &clkops_null, | ||
| 2303 | .parent = &sys_ck, | 2206 | .parent = &sys_ck, |
| 2304 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2305 | .clkdm_name = "wkup_clkdm", | 2207 | .clkdm_name = "wkup_clkdm", |
| 2306 | .recalc = &followparent_recalc, | 2208 | .recalc = &followparent_recalc, |
| 2307 | }; | 2209 | }; |
| @@ -2310,50 +2212,50 @@ static struct clk wkup_l4_ick = { | |||
| 2310 | /* Never specifically named in the TRM, so we have to infer a likely name */ | 2212 | /* Never specifically named in the TRM, so we have to infer a likely name */ |
| 2311 | static struct clk usim_ick = { | 2213 | static struct clk usim_ick = { |
| 2312 | .name = "usim_ick", | 2214 | .name = "usim_ick", |
| 2215 | .ops = &clkops_omap2_dflt_wait, | ||
| 2313 | .parent = &wkup_l4_ick, | 2216 | .parent = &wkup_l4_ick, |
| 2314 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2217 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2315 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | 2218 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, |
| 2316 | .flags = CLOCK_IN_OMAP3430ES2, | ||
| 2317 | .clkdm_name = "wkup_clkdm", | 2219 | .clkdm_name = "wkup_clkdm", |
| 2318 | .recalc = &followparent_recalc, | 2220 | .recalc = &followparent_recalc, |
| 2319 | }; | 2221 | }; |
| 2320 | 2222 | ||
| 2321 | static struct clk wdt2_ick = { | 2223 | static struct clk wdt2_ick = { |
| 2322 | .name = "wdt2_ick", | 2224 | .name = "wdt2_ick", |
| 2225 | .ops = &clkops_omap2_dflt_wait, | ||
| 2323 | .parent = &wkup_l4_ick, | 2226 | .parent = &wkup_l4_ick, |
| 2324 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2227 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2325 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | 2228 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, |
| 2326 | .flags = CLOCK_IN_OMAP343X, | ||
| 2327 | .clkdm_name = "wkup_clkdm", | 2229 | .clkdm_name = "wkup_clkdm", |
| 2328 | .recalc = &followparent_recalc, | 2230 | .recalc = &followparent_recalc, |
| 2329 | }; | 2231 | }; |
| 2330 | 2232 | ||
| 2331 | static struct clk wdt1_ick = { | 2233 | static struct clk wdt1_ick = { |
| 2332 | .name = "wdt1_ick", | 2234 | .name = "wdt1_ick", |
| 2235 | .ops = &clkops_omap2_dflt_wait, | ||
| 2333 | .parent = &wkup_l4_ick, | 2236 | .parent = &wkup_l4_ick, |
| 2334 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2237 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2335 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, | 2238 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, |
| 2336 | .flags = CLOCK_IN_OMAP343X, | ||
| 2337 | .clkdm_name = "wkup_clkdm", | 2239 | .clkdm_name = "wkup_clkdm", |
| 2338 | .recalc = &followparent_recalc, | 2240 | .recalc = &followparent_recalc, |
| 2339 | }; | 2241 | }; |
| 2340 | 2242 | ||
| 2341 | static struct clk gpio1_ick = { | 2243 | static struct clk gpio1_ick = { |
| 2342 | .name = "gpio1_ick", | 2244 | .name = "gpio1_ick", |
| 2245 | .ops = &clkops_omap2_dflt_wait, | ||
| 2343 | .parent = &wkup_l4_ick, | 2246 | .parent = &wkup_l4_ick, |
| 2344 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2247 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2345 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | 2248 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, |
| 2346 | .flags = CLOCK_IN_OMAP343X, | ||
| 2347 | .clkdm_name = "wkup_clkdm", | 2249 | .clkdm_name = "wkup_clkdm", |
| 2348 | .recalc = &followparent_recalc, | 2250 | .recalc = &followparent_recalc, |
| 2349 | }; | 2251 | }; |
| 2350 | 2252 | ||
| 2351 | static struct clk omap_32ksync_ick = { | 2253 | static struct clk omap_32ksync_ick = { |
| 2352 | .name = "omap_32ksync_ick", | 2254 | .name = "omap_32ksync_ick", |
| 2255 | .ops = &clkops_omap2_dflt_wait, | ||
| 2353 | .parent = &wkup_l4_ick, | 2256 | .parent = &wkup_l4_ick, |
| 2354 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2257 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2355 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, | 2258 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, |
| 2356 | .flags = CLOCK_IN_OMAP343X, | ||
| 2357 | .clkdm_name = "wkup_clkdm", | 2259 | .clkdm_name = "wkup_clkdm", |
| 2358 | .recalc = &followparent_recalc, | 2260 | .recalc = &followparent_recalc, |
| 2359 | }; | 2261 | }; |
| @@ -2361,20 +2263,20 @@ static struct clk omap_32ksync_ick = { | |||
| 2361 | /* XXX This clock no longer exists in 3430 TRM rev F */ | 2263 | /* XXX This clock no longer exists in 3430 TRM rev F */ |
| 2362 | static struct clk gpt12_ick = { | 2264 | static struct clk gpt12_ick = { |
| 2363 | .name = "gpt12_ick", | 2265 | .name = "gpt12_ick", |
| 2266 | .ops = &clkops_omap2_dflt_wait, | ||
| 2364 | .parent = &wkup_l4_ick, | 2267 | .parent = &wkup_l4_ick, |
| 2365 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2268 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2366 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, | 2269 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, |
| 2367 | .flags = CLOCK_IN_OMAP343X, | ||
| 2368 | .clkdm_name = "wkup_clkdm", | 2270 | .clkdm_name = "wkup_clkdm", |
| 2369 | .recalc = &followparent_recalc, | 2271 | .recalc = &followparent_recalc, |
| 2370 | }; | 2272 | }; |
| 2371 | 2273 | ||
| 2372 | static struct clk gpt1_ick = { | 2274 | static struct clk gpt1_ick = { |
| 2373 | .name = "gpt1_ick", | 2275 | .name = "gpt1_ick", |
| 2276 | .ops = &clkops_omap2_dflt_wait, | ||
| 2374 | .parent = &wkup_l4_ick, | 2277 | .parent = &wkup_l4_ick, |
| 2375 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2278 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
| 2376 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | 2279 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, |
| 2377 | .flags = CLOCK_IN_OMAP343X, | ||
| 2378 | .clkdm_name = "wkup_clkdm", | 2280 | .clkdm_name = "wkup_clkdm", |
| 2379 | .recalc = &followparent_recalc, | 2281 | .recalc = &followparent_recalc, |
| 2380 | }; | 2282 | }; |
| @@ -2385,406 +2287,404 @@ static struct clk gpt1_ick = { | |||
| 2385 | 2287 | ||
| 2386 | static struct clk per_96m_fck = { | 2288 | static struct clk per_96m_fck = { |
| 2387 | .name = "per_96m_fck", | 2289 | .name = "per_96m_fck", |
| 2290 | .ops = &clkops_null, | ||
| 2388 | .parent = &omap_96m_alwon_fck, | 2291 | .parent = &omap_96m_alwon_fck, |
| 2389 | .init = &omap2_init_clk_clkdm, | 2292 | .init = &omap2_init_clk_clkdm, |
| 2390 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 2391 | PARENT_CONTROLS_CLOCK, | ||
| 2392 | .clkdm_name = "per_clkdm", | 2293 | .clkdm_name = "per_clkdm", |
| 2393 | .recalc = &followparent_recalc, | 2294 | .recalc = &followparent_recalc, |
| 2394 | }; | 2295 | }; |
| 2395 | 2296 | ||
| 2396 | static struct clk per_48m_fck = { | 2297 | static struct clk per_48m_fck = { |
| 2397 | .name = "per_48m_fck", | 2298 | .name = "per_48m_fck", |
| 2299 | .ops = &clkops_null, | ||
| 2398 | .parent = &omap_48m_fck, | 2300 | .parent = &omap_48m_fck, |
| 2399 | .init = &omap2_init_clk_clkdm, | 2301 | .init = &omap2_init_clk_clkdm, |
| 2400 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 2401 | PARENT_CONTROLS_CLOCK, | ||
| 2402 | .clkdm_name = "per_clkdm", | 2302 | .clkdm_name = "per_clkdm", |
| 2403 | .recalc = &followparent_recalc, | 2303 | .recalc = &followparent_recalc, |
| 2404 | }; | 2304 | }; |
| 2405 | 2305 | ||
| 2406 | static struct clk uart3_fck = { | 2306 | static struct clk uart3_fck = { |
| 2407 | .name = "uart3_fck", | 2307 | .name = "uart3_fck", |
| 2308 | .ops = &clkops_omap2_dflt_wait, | ||
| 2408 | .parent = &per_48m_fck, | 2309 | .parent = &per_48m_fck, |
| 2409 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2310 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2410 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | 2311 | .enable_bit = OMAP3430_EN_UART3_SHIFT, |
| 2411 | .flags = CLOCK_IN_OMAP343X, | ||
| 2412 | .clkdm_name = "per_clkdm", | 2312 | .clkdm_name = "per_clkdm", |
| 2413 | .recalc = &followparent_recalc, | 2313 | .recalc = &followparent_recalc, |
| 2414 | }; | 2314 | }; |
| 2415 | 2315 | ||
| 2416 | static struct clk gpt2_fck = { | 2316 | static struct clk gpt2_fck = { |
| 2417 | .name = "gpt2_fck", | 2317 | .name = "gpt2_fck", |
| 2318 | .ops = &clkops_omap2_dflt_wait, | ||
| 2418 | .init = &omap2_init_clksel_parent, | 2319 | .init = &omap2_init_clksel_parent, |
| 2419 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2320 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2420 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | 2321 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, |
| 2421 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | 2322 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2422 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, | 2323 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, |
| 2423 | .clksel = omap343x_gpt_clksel, | 2324 | .clksel = omap343x_gpt_clksel, |
| 2424 | .flags = CLOCK_IN_OMAP343X, | ||
| 2425 | .clkdm_name = "per_clkdm", | 2325 | .clkdm_name = "per_clkdm", |
| 2426 | .recalc = &omap2_clksel_recalc, | 2326 | .recalc = &omap2_clksel_recalc, |
| 2427 | }; | 2327 | }; |
| 2428 | 2328 | ||
| 2429 | static struct clk gpt3_fck = { | 2329 | static struct clk gpt3_fck = { |
| 2430 | .name = "gpt3_fck", | 2330 | .name = "gpt3_fck", |
| 2331 | .ops = &clkops_omap2_dflt_wait, | ||
| 2431 | .init = &omap2_init_clksel_parent, | 2332 | .init = &omap2_init_clksel_parent, |
| 2432 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2333 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2433 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | 2334 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, |
| 2434 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | 2335 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2435 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, | 2336 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, |
| 2436 | .clksel = omap343x_gpt_clksel, | 2337 | .clksel = omap343x_gpt_clksel, |
| 2437 | .flags = CLOCK_IN_OMAP343X, | ||
| 2438 | .clkdm_name = "per_clkdm", | 2338 | .clkdm_name = "per_clkdm", |
| 2439 | .recalc = &omap2_clksel_recalc, | 2339 | .recalc = &omap2_clksel_recalc, |
| 2440 | }; | 2340 | }; |
| 2441 | 2341 | ||
| 2442 | static struct clk gpt4_fck = { | 2342 | static struct clk gpt4_fck = { |
| 2443 | .name = "gpt4_fck", | 2343 | .name = "gpt4_fck", |
| 2344 | .ops = &clkops_omap2_dflt_wait, | ||
| 2444 | .init = &omap2_init_clksel_parent, | 2345 | .init = &omap2_init_clksel_parent, |
| 2445 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2346 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2446 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | 2347 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, |
| 2447 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | 2348 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2448 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, | 2349 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, |
| 2449 | .clksel = omap343x_gpt_clksel, | 2350 | .clksel = omap343x_gpt_clksel, |
| 2450 | .flags = CLOCK_IN_OMAP343X, | ||
| 2451 | .clkdm_name = "per_clkdm", | 2351 | .clkdm_name = "per_clkdm", |
| 2452 | .recalc = &omap2_clksel_recalc, | 2352 | .recalc = &omap2_clksel_recalc, |
| 2453 | }; | 2353 | }; |
| 2454 | 2354 | ||
| 2455 | static struct clk gpt5_fck = { | 2355 | static struct clk gpt5_fck = { |
| 2456 | .name = "gpt5_fck", | 2356 | .name = "gpt5_fck", |
| 2357 | .ops = &clkops_omap2_dflt_wait, | ||
| 2457 | .init = &omap2_init_clksel_parent, | 2358 | .init = &omap2_init_clksel_parent, |
| 2458 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2359 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2459 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | 2360 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, |
| 2460 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | 2361 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2461 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, | 2362 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, |
| 2462 | .clksel = omap343x_gpt_clksel, | 2363 | .clksel = omap343x_gpt_clksel, |
| 2463 | .flags = CLOCK_IN_OMAP343X, | ||
| 2464 | .clkdm_name = "per_clkdm", | 2364 | .clkdm_name = "per_clkdm", |
| 2465 | .recalc = &omap2_clksel_recalc, | 2365 | .recalc = &omap2_clksel_recalc, |
| 2466 | }; | 2366 | }; |
| 2467 | 2367 | ||
| 2468 | static struct clk gpt6_fck = { | 2368 | static struct clk gpt6_fck = { |
| 2469 | .name = "gpt6_fck", | 2369 | .name = "gpt6_fck", |
| 2370 | .ops = &clkops_omap2_dflt_wait, | ||
| 2470 | .init = &omap2_init_clksel_parent, | 2371 | .init = &omap2_init_clksel_parent, |
| 2471 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2372 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2472 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | 2373 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, |
| 2473 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | 2374 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2474 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, | 2375 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, |
| 2475 | .clksel = omap343x_gpt_clksel, | 2376 | .clksel = omap343x_gpt_clksel, |
| 2476 | .flags = CLOCK_IN_OMAP343X, | ||
| 2477 | .clkdm_name = "per_clkdm", | 2377 | .clkdm_name = "per_clkdm", |
| 2478 | .recalc = &omap2_clksel_recalc, | 2378 | .recalc = &omap2_clksel_recalc, |
| 2479 | }; | 2379 | }; |
| 2480 | 2380 | ||
| 2481 | static struct clk gpt7_fck = { | 2381 | static struct clk gpt7_fck = { |
| 2482 | .name = "gpt7_fck", | 2382 | .name = "gpt7_fck", |
| 2383 | .ops = &clkops_omap2_dflt_wait, | ||
| 2483 | .init = &omap2_init_clksel_parent, | 2384 | .init = &omap2_init_clksel_parent, |
| 2484 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2385 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2485 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | 2386 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, |
| 2486 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | 2387 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2487 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, | 2388 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, |
| 2488 | .clksel = omap343x_gpt_clksel, | 2389 | .clksel = omap343x_gpt_clksel, |
| 2489 | .flags = CLOCK_IN_OMAP343X, | ||
| 2490 | .clkdm_name = "per_clkdm", | 2390 | .clkdm_name = "per_clkdm", |
| 2491 | .recalc = &omap2_clksel_recalc, | 2391 | .recalc = &omap2_clksel_recalc, |
| 2492 | }; | 2392 | }; |
| 2493 | 2393 | ||
| 2494 | static struct clk gpt8_fck = { | 2394 | static struct clk gpt8_fck = { |
| 2495 | .name = "gpt8_fck", | 2395 | .name = "gpt8_fck", |
| 2396 | .ops = &clkops_omap2_dflt_wait, | ||
| 2496 | .init = &omap2_init_clksel_parent, | 2397 | .init = &omap2_init_clksel_parent, |
| 2497 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2398 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2498 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | 2399 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, |
| 2499 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | 2400 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2500 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, | 2401 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, |
| 2501 | .clksel = omap343x_gpt_clksel, | 2402 | .clksel = omap343x_gpt_clksel, |
| 2502 | .flags = CLOCK_IN_OMAP343X, | ||
| 2503 | .clkdm_name = "per_clkdm", | 2403 | .clkdm_name = "per_clkdm", |
| 2504 | .recalc = &omap2_clksel_recalc, | 2404 | .recalc = &omap2_clksel_recalc, |
| 2505 | }; | 2405 | }; |
| 2506 | 2406 | ||
| 2507 | static struct clk gpt9_fck = { | 2407 | static struct clk gpt9_fck = { |
| 2508 | .name = "gpt9_fck", | 2408 | .name = "gpt9_fck", |
| 2409 | .ops = &clkops_omap2_dflt_wait, | ||
| 2509 | .init = &omap2_init_clksel_parent, | 2410 | .init = &omap2_init_clksel_parent, |
| 2510 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2411 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2511 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | 2412 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, |
| 2512 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | 2413 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), |
| 2513 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, | 2414 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, |
| 2514 | .clksel = omap343x_gpt_clksel, | 2415 | .clksel = omap343x_gpt_clksel, |
| 2515 | .flags = CLOCK_IN_OMAP343X, | ||
| 2516 | .clkdm_name = "per_clkdm", | 2416 | .clkdm_name = "per_clkdm", |
| 2517 | .recalc = &omap2_clksel_recalc, | 2417 | .recalc = &omap2_clksel_recalc, |
| 2518 | }; | 2418 | }; |
| 2519 | 2419 | ||
| 2520 | static struct clk per_32k_alwon_fck = { | 2420 | static struct clk per_32k_alwon_fck = { |
| 2521 | .name = "per_32k_alwon_fck", | 2421 | .name = "per_32k_alwon_fck", |
| 2422 | .ops = &clkops_null, | ||
| 2522 | .parent = &omap_32k_fck, | 2423 | .parent = &omap_32k_fck, |
| 2523 | .clkdm_name = "per_clkdm", | 2424 | .clkdm_name = "per_clkdm", |
| 2524 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2525 | .recalc = &followparent_recalc, | 2425 | .recalc = &followparent_recalc, |
| 2526 | }; | 2426 | }; |
| 2527 | 2427 | ||
| 2528 | static struct clk gpio6_dbck = { | 2428 | static struct clk gpio6_dbck = { |
| 2529 | .name = "gpio6_dbck", | 2429 | .name = "gpio6_dbck", |
| 2430 | .ops = &clkops_omap2_dflt_wait, | ||
| 2530 | .parent = &per_32k_alwon_fck, | 2431 | .parent = &per_32k_alwon_fck, |
| 2531 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2432 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2532 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | 2433 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
| 2533 | .flags = CLOCK_IN_OMAP343X, | ||
| 2534 | .clkdm_name = "per_clkdm", | 2434 | .clkdm_name = "per_clkdm", |
| 2535 | .recalc = &followparent_recalc, | 2435 | .recalc = &followparent_recalc, |
| 2536 | }; | 2436 | }; |
| 2537 | 2437 | ||
| 2538 | static struct clk gpio5_dbck = { | 2438 | static struct clk gpio5_dbck = { |
| 2539 | .name = "gpio5_dbck", | 2439 | .name = "gpio5_dbck", |
| 2440 | .ops = &clkops_omap2_dflt_wait, | ||
| 2540 | .parent = &per_32k_alwon_fck, | 2441 | .parent = &per_32k_alwon_fck, |
| 2541 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2442 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2542 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | 2443 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
| 2543 | .flags = CLOCK_IN_OMAP343X, | ||
| 2544 | .clkdm_name = "per_clkdm", | 2444 | .clkdm_name = "per_clkdm", |
| 2545 | .recalc = &followparent_recalc, | 2445 | .recalc = &followparent_recalc, |
| 2546 | }; | 2446 | }; |
| 2547 | 2447 | ||
| 2548 | static struct clk gpio4_dbck = { | 2448 | static struct clk gpio4_dbck = { |
| 2549 | .name = "gpio4_dbck", | 2449 | .name = "gpio4_dbck", |
| 2450 | .ops = &clkops_omap2_dflt_wait, | ||
| 2550 | .parent = &per_32k_alwon_fck, | 2451 | .parent = &per_32k_alwon_fck, |
| 2551 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2452 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2552 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | 2453 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
| 2553 | .flags = CLOCK_IN_OMAP343X, | ||
| 2554 | .clkdm_name = "per_clkdm", | 2454 | .clkdm_name = "per_clkdm", |
| 2555 | .recalc = &followparent_recalc, | 2455 | .recalc = &followparent_recalc, |
| 2556 | }; | 2456 | }; |
| 2557 | 2457 | ||
| 2558 | static struct clk gpio3_dbck = { | 2458 | static struct clk gpio3_dbck = { |
| 2559 | .name = "gpio3_dbck", | 2459 | .name = "gpio3_dbck", |
| 2460 | .ops = &clkops_omap2_dflt_wait, | ||
| 2560 | .parent = &per_32k_alwon_fck, | 2461 | .parent = &per_32k_alwon_fck, |
| 2561 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2462 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2562 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | 2463 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
| 2563 | .flags = CLOCK_IN_OMAP343X, | ||
| 2564 | .clkdm_name = "per_clkdm", | 2464 | .clkdm_name = "per_clkdm", |
| 2565 | .recalc = &followparent_recalc, | 2465 | .recalc = &followparent_recalc, |
| 2566 | }; | 2466 | }; |
| 2567 | 2467 | ||
| 2568 | static struct clk gpio2_dbck = { | 2468 | static struct clk gpio2_dbck = { |
| 2569 | .name = "gpio2_dbck", | 2469 | .name = "gpio2_dbck", |
| 2470 | .ops = &clkops_omap2_dflt_wait, | ||
| 2570 | .parent = &per_32k_alwon_fck, | 2471 | .parent = &per_32k_alwon_fck, |
| 2571 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2472 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2572 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | 2473 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
| 2573 | .flags = CLOCK_IN_OMAP343X, | ||
| 2574 | .clkdm_name = "per_clkdm", | 2474 | .clkdm_name = "per_clkdm", |
| 2575 | .recalc = &followparent_recalc, | 2475 | .recalc = &followparent_recalc, |
| 2576 | }; | 2476 | }; |
| 2577 | 2477 | ||
| 2578 | static struct clk wdt3_fck = { | 2478 | static struct clk wdt3_fck = { |
| 2579 | .name = "wdt3_fck", | 2479 | .name = "wdt3_fck", |
| 2480 | .ops = &clkops_omap2_dflt_wait, | ||
| 2580 | .parent = &per_32k_alwon_fck, | 2481 | .parent = &per_32k_alwon_fck, |
| 2581 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2482 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| 2582 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | 2483 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, |
| 2583 | .flags = CLOCK_IN_OMAP343X, | ||
| 2584 | .clkdm_name = "per_clkdm", | 2484 | .clkdm_name = "per_clkdm", |
| 2585 | .recalc = &followparent_recalc, | 2485 | .recalc = &followparent_recalc, |
| 2586 | }; | 2486 | }; |
| 2587 | 2487 | ||
| 2588 | static struct clk per_l4_ick = { | 2488 | static struct clk per_l4_ick = { |
| 2589 | .name = "per_l4_ick", | 2489 | .name = "per_l4_ick", |
| 2490 | .ops = &clkops_null, | ||
| 2590 | .parent = &l4_ick, | 2491 | .parent = &l4_ick, |
| 2591 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | ||
| 2592 | PARENT_CONTROLS_CLOCK, | ||
| 2593 | .clkdm_name = "per_clkdm", | 2492 | .clkdm_name = "per_clkdm", |
| 2594 | .recalc = &followparent_recalc, | 2493 | .recalc = &followparent_recalc, |
| 2595 | }; | 2494 | }; |
| 2596 | 2495 | ||
| 2597 | static struct clk gpio6_ick = { | 2496 | static struct clk gpio6_ick = { |
| 2598 | .name = "gpio6_ick", | 2497 | .name = "gpio6_ick", |
| 2498 | .ops = &clkops_omap2_dflt_wait, | ||
| 2599 | .parent = &per_l4_ick, | 2499 | .parent = &per_l4_ick, |
| 2600 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2500 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2601 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | 2501 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
| 2602 | .flags = CLOCK_IN_OMAP343X, | ||
| 2603 | .clkdm_name = "per_clkdm", | 2502 | .clkdm_name = "per_clkdm", |
| 2604 | .recalc = &followparent_recalc, | 2503 | .recalc = &followparent_recalc, |
| 2605 | }; | 2504 | }; |
| 2606 | 2505 | ||
| 2607 | static struct clk gpio5_ick = { | 2506 | static struct clk gpio5_ick = { |
| 2608 | .name = "gpio5_ick", | 2507 | .name = "gpio5_ick", |
| 2508 | .ops = &clkops_omap2_dflt_wait, | ||
| 2609 | .parent = &per_l4_ick, | 2509 | .parent = &per_l4_ick, |
| 2610 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2510 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2611 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | 2511 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
| 2612 | .flags = CLOCK_IN_OMAP343X, | ||
| 2613 | .clkdm_name = "per_clkdm", | 2512 | .clkdm_name = "per_clkdm", |
| 2614 | .recalc = &followparent_recalc, | 2513 | .recalc = &followparent_recalc, |
| 2615 | }; | 2514 | }; |
| 2616 | 2515 | ||
| 2617 | static struct clk gpio4_ick = { | 2516 | static struct clk gpio4_ick = { |
| 2618 | .name = "gpio4_ick", | 2517 | .name = "gpio4_ick", |
| 2518 | .ops = &clkops_omap2_dflt_wait, | ||
| 2619 | .parent = &per_l4_ick, | 2519 | .parent = &per_l4_ick, |
| 2620 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2520 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2621 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | 2521 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
| 2622 | .flags = CLOCK_IN_OMAP343X, | ||
| 2623 | .clkdm_name = "per_clkdm", | 2522 | .clkdm_name = "per_clkdm", |
| 2624 | .recalc = &followparent_recalc, | 2523 | .recalc = &followparent_recalc, |
| 2625 | }; | 2524 | }; |
| 2626 | 2525 | ||
| 2627 | static struct clk gpio3_ick = { | 2526 | static struct clk gpio3_ick = { |
| 2628 | .name = "gpio3_ick", | 2527 | .name = "gpio3_ick", |
| 2528 | .ops = &clkops_omap2_dflt_wait, | ||
| 2629 | .parent = &per_l4_ick, | 2529 | .parent = &per_l4_ick, |
| 2630 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2530 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2631 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | 2531 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
| 2632 | .flags = CLOCK_IN_OMAP343X, | ||
| 2633 | .clkdm_name = "per_clkdm", | 2532 | .clkdm_name = "per_clkdm", |
| 2634 | .recalc = &followparent_recalc, | 2533 | .recalc = &followparent_recalc, |
| 2635 | }; | 2534 | }; |
| 2636 | 2535 | ||
| 2637 | static struct clk gpio2_ick = { | 2536 | static struct clk gpio2_ick = { |
| 2638 | .name = "gpio2_ick", | 2537 | .name = "gpio2_ick", |
| 2538 | .ops = &clkops_omap2_dflt_wait, | ||
| 2639 | .parent = &per_l4_ick, | 2539 | .parent = &per_l4_ick, |
| 2640 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2540 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2641 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | 2541 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
| 2642 | .flags = CLOCK_IN_OMAP343X, | ||
| 2643 | .clkdm_name = "per_clkdm", | 2542 | .clkdm_name = "per_clkdm", |
| 2644 | .recalc = &followparent_recalc, | 2543 | .recalc = &followparent_recalc, |
| 2645 | }; | 2544 | }; |
| 2646 | 2545 | ||
| 2647 | static struct clk wdt3_ick = { | 2546 | static struct clk wdt3_ick = { |
| 2648 | .name = "wdt3_ick", | 2547 | .name = "wdt3_ick", |
| 2548 | .ops = &clkops_omap2_dflt_wait, | ||
| 2649 | .parent = &per_l4_ick, | 2549 | .parent = &per_l4_ick, |
| 2650 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2550 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2651 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | 2551 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, |
| 2652 | .flags = CLOCK_IN_OMAP343X, | ||
| 2653 | .clkdm_name = "per_clkdm", | 2552 | .clkdm_name = "per_clkdm", |
| 2654 | .recalc = &followparent_recalc, | 2553 | .recalc = &followparent_recalc, |
| 2655 | }; | 2554 | }; |
| 2656 | 2555 | ||
| 2657 | static struct clk uart3_ick = { | 2556 | static struct clk uart3_ick = { |
| 2658 | .name = "uart3_ick", | 2557 | .name = "uart3_ick", |
| 2558 | .ops = &clkops_omap2_dflt_wait, | ||
| 2659 | .parent = &per_l4_ick, | 2559 | .parent = &per_l4_ick, |
| 2660 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2560 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2661 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | 2561 | .enable_bit = OMAP3430_EN_UART3_SHIFT, |
| 2662 | .flags = CLOCK_IN_OMAP343X, | ||
| 2663 | .clkdm_name = "per_clkdm", | 2562 | .clkdm_name = "per_clkdm", |
| 2664 | .recalc = &followparent_recalc, | 2563 | .recalc = &followparent_recalc, |
| 2665 | }; | 2564 | }; |
| 2666 | 2565 | ||
| 2667 | static struct clk gpt9_ick = { | 2566 | static struct clk gpt9_ick = { |
| 2668 | .name = "gpt9_ick", | 2567 | .name = "gpt9_ick", |
| 2568 | .ops = &clkops_omap2_dflt_wait, | ||
| 2669 | .parent = &per_l4_ick, | 2569 | .parent = &per_l4_ick, |
| 2670 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2570 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2671 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | 2571 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, |
| 2672 | .flags = CLOCK_IN_OMAP343X, | ||
| 2673 | .clkdm_name = "per_clkdm", | 2572 | .clkdm_name = "per_clkdm", |
| 2674 | .recalc = &followparent_recalc, | 2573 | .recalc = &followparent_recalc, |
| 2675 | }; | 2574 | }; |
| 2676 | 2575 | ||
| 2677 | static struct clk gpt8_ick = { | 2576 | static struct clk gpt8_ick = { |
| 2678 | .name = "gpt8_ick", | 2577 | .name = "gpt8_ick", |
| 2578 | .ops = &clkops_omap2_dflt_wait, | ||
| 2679 | .parent = &per_l4_ick, | 2579 | .parent = &per_l4_ick, |
| 2680 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2580 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2681 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | 2581 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, |
| 2682 | .flags = CLOCK_IN_OMAP343X, | ||
| 2683 | .clkdm_name = "per_clkdm", | 2582 | .clkdm_name = "per_clkdm", |
| 2684 | .recalc = &followparent_recalc, | 2583 | .recalc = &followparent_recalc, |
| 2685 | }; | 2584 | }; |
| 2686 | 2585 | ||
| 2687 | static struct clk gpt7_ick = { | 2586 | static struct clk gpt7_ick = { |
| 2688 | .name = "gpt7_ick", | 2587 | .name = "gpt7_ick", |
| 2588 | .ops = &clkops_omap2_dflt_wait, | ||
| 2689 | .parent = &per_l4_ick, | 2589 | .parent = &per_l4_ick, |
| 2690 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2590 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2691 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | 2591 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, |
| 2692 | .flags = CLOCK_IN_OMAP343X, | ||
| 2693 | .clkdm_name = "per_clkdm", | 2592 | .clkdm_name = "per_clkdm", |
| 2694 | .recalc = &followparent_recalc, | 2593 | .recalc = &followparent_recalc, |
| 2695 | }; | 2594 | }; |
| 2696 | 2595 | ||
| 2697 | static struct clk gpt6_ick = { | 2596 | static struct clk gpt6_ick = { |
| 2698 | .name = "gpt6_ick", | 2597 | .name = "gpt6_ick", |
| 2598 | .ops = &clkops_omap2_dflt_wait, | ||
| 2699 | .parent = &per_l4_ick, | 2599 | .parent = &per_l4_ick, |
| 2700 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2600 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2701 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | 2601 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, |
| 2702 | .flags = CLOCK_IN_OMAP343X, | ||
| 2703 | .clkdm_name = "per_clkdm", | 2602 | .clkdm_name = "per_clkdm", |
| 2704 | .recalc = &followparent_recalc, | 2603 | .recalc = &followparent_recalc, |
| 2705 | }; | 2604 | }; |
| 2706 | 2605 | ||
| 2707 | static struct clk gpt5_ick = { | 2606 | static struct clk gpt5_ick = { |
| 2708 | .name = "gpt5_ick", | 2607 | .name = "gpt5_ick", |
| 2608 | .ops = &clkops_omap2_dflt_wait, | ||
| 2709 | .parent = &per_l4_ick, | 2609 | .parent = &per_l4_ick, |
| 2710 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2610 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2711 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | 2611 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, |
| 2712 | .flags = CLOCK_IN_OMAP343X, | ||
| 2713 | .clkdm_name = "per_clkdm", | 2612 | .clkdm_name = "per_clkdm", |
| 2714 | .recalc = &followparent_recalc, | 2613 | .recalc = &followparent_recalc, |
| 2715 | }; | 2614 | }; |
| 2716 | 2615 | ||
| 2717 | static struct clk gpt4_ick = { | 2616 | static struct clk gpt4_ick = { |
| 2718 | .name = "gpt4_ick", | 2617 | .name = "gpt4_ick", |
| 2618 | .ops = &clkops_omap2_dflt_wait, | ||
| 2719 | .parent = &per_l4_ick, | 2619 | .parent = &per_l4_ick, |
| 2720 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2620 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2721 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | 2621 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, |
| 2722 | .flags = CLOCK_IN_OMAP343X, | ||
| 2723 | .clkdm_name = "per_clkdm", | 2622 | .clkdm_name = "per_clkdm", |
| 2724 | .recalc = &followparent_recalc, | 2623 | .recalc = &followparent_recalc, |
| 2725 | }; | 2624 | }; |
| 2726 | 2625 | ||
| 2727 | static struct clk gpt3_ick = { | 2626 | static struct clk gpt3_ick = { |
| 2728 | .name = "gpt3_ick", | 2627 | .name = "gpt3_ick", |
| 2628 | .ops = &clkops_omap2_dflt_wait, | ||
| 2729 | .parent = &per_l4_ick, | 2629 | .parent = &per_l4_ick, |
| 2730 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2630 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2731 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | 2631 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, |
| 2732 | .flags = CLOCK_IN_OMAP343X, | ||
| 2733 | .clkdm_name = "per_clkdm", | 2632 | .clkdm_name = "per_clkdm", |
| 2734 | .recalc = &followparent_recalc, | 2633 | .recalc = &followparent_recalc, |
| 2735 | }; | 2634 | }; |
| 2736 | 2635 | ||
| 2737 | static struct clk gpt2_ick = { | 2636 | static struct clk gpt2_ick = { |
| 2738 | .name = "gpt2_ick", | 2637 | .name = "gpt2_ick", |
| 2638 | .ops = &clkops_omap2_dflt_wait, | ||
| 2739 | .parent = &per_l4_ick, | 2639 | .parent = &per_l4_ick, |
| 2740 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2640 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2741 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | 2641 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, |
| 2742 | .flags = CLOCK_IN_OMAP343X, | ||
| 2743 | .clkdm_name = "per_clkdm", | 2642 | .clkdm_name = "per_clkdm", |
| 2744 | .recalc = &followparent_recalc, | 2643 | .recalc = &followparent_recalc, |
| 2745 | }; | 2644 | }; |
| 2746 | 2645 | ||
| 2747 | static struct clk mcbsp2_ick = { | 2646 | static struct clk mcbsp2_ick = { |
| 2748 | .name = "mcbsp_ick", | 2647 | .name = "mcbsp_ick", |
| 2648 | .ops = &clkops_omap2_dflt_wait, | ||
| 2749 | .id = 2, | 2649 | .id = 2, |
| 2750 | .parent = &per_l4_ick, | 2650 | .parent = &per_l4_ick, |
| 2751 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2651 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2752 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | 2652 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, |
| 2753 | .flags = CLOCK_IN_OMAP343X, | ||
| 2754 | .clkdm_name = "per_clkdm", | 2653 | .clkdm_name = "per_clkdm", |
| 2755 | .recalc = &followparent_recalc, | 2654 | .recalc = &followparent_recalc, |
| 2756 | }; | 2655 | }; |
| 2757 | 2656 | ||
| 2758 | static struct clk mcbsp3_ick = { | 2657 | static struct clk mcbsp3_ick = { |
| 2759 | .name = "mcbsp_ick", | 2658 | .name = "mcbsp_ick", |
| 2659 | .ops = &clkops_omap2_dflt_wait, | ||
| 2760 | .id = 3, | 2660 | .id = 3, |
| 2761 | .parent = &per_l4_ick, | 2661 | .parent = &per_l4_ick, |
| 2762 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2662 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2763 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | 2663 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, |
| 2764 | .flags = CLOCK_IN_OMAP343X, | ||
| 2765 | .clkdm_name = "per_clkdm", | 2664 | .clkdm_name = "per_clkdm", |
| 2766 | .recalc = &followparent_recalc, | 2665 | .recalc = &followparent_recalc, |
| 2767 | }; | 2666 | }; |
| 2768 | 2667 | ||
| 2769 | static struct clk mcbsp4_ick = { | 2668 | static struct clk mcbsp4_ick = { |
| 2770 | .name = "mcbsp_ick", | 2669 | .name = "mcbsp_ick", |
| 2670 | .ops = &clkops_omap2_dflt_wait, | ||
| 2771 | .id = 4, | 2671 | .id = 4, |
| 2772 | .parent = &per_l4_ick, | 2672 | .parent = &per_l4_ick, |
| 2773 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | 2673 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), |
| 2774 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | 2674 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, |
| 2775 | .flags = CLOCK_IN_OMAP343X, | ||
| 2776 | .clkdm_name = "per_clkdm", | 2675 | .clkdm_name = "per_clkdm", |
| 2777 | .recalc = &followparent_recalc, | 2676 | .recalc = &followparent_recalc, |
| 2778 | }; | 2677 | }; |
| 2779 | 2678 | ||
| 2780 | static const struct clksel mcbsp_234_clksel[] = { | 2679 | static const struct clksel mcbsp_234_clksel[] = { |
| 2781 | { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, | 2680 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, |
| 2782 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | 2681 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, |
| 2783 | { .parent = NULL } | 2682 | { .parent = NULL } |
| 2784 | }; | 2683 | }; |
| 2785 | 2684 | ||
| 2786 | static struct clk mcbsp2_fck = { | 2685 | static struct clk mcbsp2_fck = { |
| 2787 | .name = "mcbsp_fck", | 2686 | .name = "mcbsp_fck", |
| 2687 | .ops = &clkops_omap2_dflt_wait, | ||
| 2788 | .id = 2, | 2688 | .id = 2, |
| 2789 | .init = &omap2_init_clksel_parent, | 2689 | .init = &omap2_init_clksel_parent, |
| 2790 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2690 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| @@ -2792,13 +2692,13 @@ static struct clk mcbsp2_fck = { | |||
| 2792 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | 2692 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), |
| 2793 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, | 2693 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, |
| 2794 | .clksel = mcbsp_234_clksel, | 2694 | .clksel = mcbsp_234_clksel, |
| 2795 | .flags = CLOCK_IN_OMAP343X, | ||
| 2796 | .clkdm_name = "per_clkdm", | 2695 | .clkdm_name = "per_clkdm", |
| 2797 | .recalc = &omap2_clksel_recalc, | 2696 | .recalc = &omap2_clksel_recalc, |
| 2798 | }; | 2697 | }; |
| 2799 | 2698 | ||
| 2800 | static struct clk mcbsp3_fck = { | 2699 | static struct clk mcbsp3_fck = { |
| 2801 | .name = "mcbsp_fck", | 2700 | .name = "mcbsp_fck", |
| 2701 | .ops = &clkops_omap2_dflt_wait, | ||
| 2802 | .id = 3, | 2702 | .id = 3, |
| 2803 | .init = &omap2_init_clksel_parent, | 2703 | .init = &omap2_init_clksel_parent, |
| 2804 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2704 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| @@ -2806,13 +2706,13 @@ static struct clk mcbsp3_fck = { | |||
| 2806 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | 2706 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 2807 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, | 2707 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, |
| 2808 | .clksel = mcbsp_234_clksel, | 2708 | .clksel = mcbsp_234_clksel, |
| 2809 | .flags = CLOCK_IN_OMAP343X, | ||
| 2810 | .clkdm_name = "per_clkdm", | 2709 | .clkdm_name = "per_clkdm", |
| 2811 | .recalc = &omap2_clksel_recalc, | 2710 | .recalc = &omap2_clksel_recalc, |
| 2812 | }; | 2711 | }; |
| 2813 | 2712 | ||
| 2814 | static struct clk mcbsp4_fck = { | 2713 | static struct clk mcbsp4_fck = { |
| 2815 | .name = "mcbsp_fck", | 2714 | .name = "mcbsp_fck", |
| 2715 | .ops = &clkops_omap2_dflt_wait, | ||
| 2816 | .id = 4, | 2716 | .id = 4, |
| 2817 | .init = &omap2_init_clksel_parent, | 2717 | .init = &omap2_init_clksel_parent, |
| 2818 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | 2718 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), |
| @@ -2820,7 +2720,6 @@ static struct clk mcbsp4_fck = { | |||
| 2820 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | 2720 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), |
| 2821 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, | 2721 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, |
| 2822 | .clksel = mcbsp_234_clksel, | 2722 | .clksel = mcbsp_234_clksel, |
| 2823 | .flags = CLOCK_IN_OMAP343X, | ||
| 2824 | .clkdm_name = "per_clkdm", | 2723 | .clkdm_name = "per_clkdm", |
| 2825 | .recalc = &omap2_clksel_recalc, | 2724 | .recalc = &omap2_clksel_recalc, |
| 2826 | }; | 2725 | }; |
| @@ -2864,11 +2763,11 @@ static const struct clksel emu_src_clksel[] = { | |||
| 2864 | */ | 2763 | */ |
| 2865 | static struct clk emu_src_ck = { | 2764 | static struct clk emu_src_ck = { |
| 2866 | .name = "emu_src_ck", | 2765 | .name = "emu_src_ck", |
| 2766 | .ops = &clkops_null, | ||
| 2867 | .init = &omap2_init_clksel_parent, | 2767 | .init = &omap2_init_clksel_parent, |
| 2868 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2768 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2869 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, | 2769 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, |
| 2870 | .clksel = emu_src_clksel, | 2770 | .clksel = emu_src_clksel, |
| 2871 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2872 | .clkdm_name = "emu_clkdm", | 2771 | .clkdm_name = "emu_clkdm", |
| 2873 | .recalc = &omap2_clksel_recalc, | 2772 | .recalc = &omap2_clksel_recalc, |
| 2874 | }; | 2773 | }; |
| @@ -2888,11 +2787,11 @@ static const struct clksel pclk_emu_clksel[] = { | |||
| 2888 | 2787 | ||
| 2889 | static struct clk pclk_fck = { | 2788 | static struct clk pclk_fck = { |
| 2890 | .name = "pclk_fck", | 2789 | .name = "pclk_fck", |
| 2790 | .ops = &clkops_null, | ||
| 2891 | .init = &omap2_init_clksel_parent, | 2791 | .init = &omap2_init_clksel_parent, |
| 2892 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2792 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2893 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, | 2793 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, |
| 2894 | .clksel = pclk_emu_clksel, | 2794 | .clksel = pclk_emu_clksel, |
| 2895 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2896 | .clkdm_name = "emu_clkdm", | 2795 | .clkdm_name = "emu_clkdm", |
| 2897 | .recalc = &omap2_clksel_recalc, | 2796 | .recalc = &omap2_clksel_recalc, |
| 2898 | }; | 2797 | }; |
| @@ -2911,11 +2810,11 @@ static const struct clksel pclkx2_emu_clksel[] = { | |||
| 2911 | 2810 | ||
| 2912 | static struct clk pclkx2_fck = { | 2811 | static struct clk pclkx2_fck = { |
| 2913 | .name = "pclkx2_fck", | 2812 | .name = "pclkx2_fck", |
| 2813 | .ops = &clkops_null, | ||
| 2914 | .init = &omap2_init_clksel_parent, | 2814 | .init = &omap2_init_clksel_parent, |
| 2915 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2815 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2916 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, | 2816 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, |
| 2917 | .clksel = pclkx2_emu_clksel, | 2817 | .clksel = pclkx2_emu_clksel, |
| 2918 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2919 | .clkdm_name = "emu_clkdm", | 2818 | .clkdm_name = "emu_clkdm", |
| 2920 | .recalc = &omap2_clksel_recalc, | 2819 | .recalc = &omap2_clksel_recalc, |
| 2921 | }; | 2820 | }; |
| @@ -2927,22 +2826,22 @@ static const struct clksel atclk_emu_clksel[] = { | |||
| 2927 | 2826 | ||
| 2928 | static struct clk atclk_fck = { | 2827 | static struct clk atclk_fck = { |
| 2929 | .name = "atclk_fck", | 2828 | .name = "atclk_fck", |
| 2829 | .ops = &clkops_null, | ||
| 2930 | .init = &omap2_init_clksel_parent, | 2830 | .init = &omap2_init_clksel_parent, |
| 2931 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2831 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2932 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, | 2832 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, |
| 2933 | .clksel = atclk_emu_clksel, | 2833 | .clksel = atclk_emu_clksel, |
| 2934 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2935 | .clkdm_name = "emu_clkdm", | 2834 | .clkdm_name = "emu_clkdm", |
| 2936 | .recalc = &omap2_clksel_recalc, | 2835 | .recalc = &omap2_clksel_recalc, |
| 2937 | }; | 2836 | }; |
| 2938 | 2837 | ||
| 2939 | static struct clk traceclk_src_fck = { | 2838 | static struct clk traceclk_src_fck = { |
| 2940 | .name = "traceclk_src_fck", | 2839 | .name = "traceclk_src_fck", |
| 2840 | .ops = &clkops_null, | ||
| 2941 | .init = &omap2_init_clksel_parent, | 2841 | .init = &omap2_init_clksel_parent, |
| 2942 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2842 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2943 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, | 2843 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, |
| 2944 | .clksel = emu_src_clksel, | 2844 | .clksel = emu_src_clksel, |
| 2945 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | ||
| 2946 | .clkdm_name = "emu_clkdm", | 2845 | .clkdm_name = "emu_clkdm", |
| 2947 | .recalc = &omap2_clksel_recalc, | 2846 | .recalc = &omap2_clksel_recalc, |
| 2948 | }; | 2847 | }; |
| @@ -2961,11 +2860,11 @@ static const struct clksel traceclk_clksel[] = { | |||
| 2961 | 2860 | ||
| 2962 | static struct clk traceclk_fck = { | 2861 | static struct clk traceclk_fck = { |
| 2963 | .name = "traceclk_fck", | 2862 | .name = "traceclk_fck", |
| 2863 | .ops = &clkops_null, | ||
| 2964 | .init = &omap2_init_clksel_parent, | 2864 | .init = &omap2_init_clksel_parent, |
| 2965 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | 2865 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), |
| 2966 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, | 2866 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, |
| 2967 | .clksel = traceclk_clksel, | 2867 | .clksel = traceclk_clksel, |
| 2968 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | ||
| 2969 | .clkdm_name = "emu_clkdm", | 2868 | .clkdm_name = "emu_clkdm", |
| 2970 | .recalc = &omap2_clksel_recalc, | 2869 | .recalc = &omap2_clksel_recalc, |
| 2971 | }; | 2870 | }; |
| @@ -2975,27 +2874,27 @@ static struct clk traceclk_fck = { | |||
| 2975 | /* SmartReflex fclk (VDD1) */ | 2874 | /* SmartReflex fclk (VDD1) */ |
| 2976 | static struct clk sr1_fck = { | 2875 | static struct clk sr1_fck = { |
| 2977 | .name = "sr1_fck", | 2876 | .name = "sr1_fck", |
| 2877 | .ops = &clkops_omap2_dflt_wait, | ||
| 2978 | .parent = &sys_ck, | 2878 | .parent = &sys_ck, |
| 2979 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2879 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2980 | .enable_bit = OMAP3430_EN_SR1_SHIFT, | 2880 | .enable_bit = OMAP3430_EN_SR1_SHIFT, |
| 2981 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 2982 | .recalc = &followparent_recalc, | 2881 | .recalc = &followparent_recalc, |
| 2983 | }; | 2882 | }; |
| 2984 | 2883 | ||
| 2985 | /* SmartReflex fclk (VDD2) */ | 2884 | /* SmartReflex fclk (VDD2) */ |
| 2986 | static struct clk sr2_fck = { | 2885 | static struct clk sr2_fck = { |
| 2987 | .name = "sr2_fck", | 2886 | .name = "sr2_fck", |
| 2887 | .ops = &clkops_omap2_dflt_wait, | ||
| 2988 | .parent = &sys_ck, | 2888 | .parent = &sys_ck, |
| 2989 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2889 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
| 2990 | .enable_bit = OMAP3430_EN_SR2_SHIFT, | 2890 | .enable_bit = OMAP3430_EN_SR2_SHIFT, |
| 2991 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | ||
| 2992 | .recalc = &followparent_recalc, | 2891 | .recalc = &followparent_recalc, |
| 2993 | }; | 2892 | }; |
| 2994 | 2893 | ||
| 2995 | static struct clk sr_l4_ick = { | 2894 | static struct clk sr_l4_ick = { |
| 2996 | .name = "sr_l4_ick", | 2895 | .name = "sr_l4_ick", |
| 2896 | .ops = &clkops_null, /* RMK: missing? */ | ||
| 2997 | .parent = &l4_ick, | 2897 | .parent = &l4_ick, |
| 2998 | .flags = CLOCK_IN_OMAP343X, | ||
| 2999 | .clkdm_name = "core_l4_clkdm", | 2898 | .clkdm_name = "core_l4_clkdm", |
| 3000 | .recalc = &followparent_recalc, | 2899 | .recalc = &followparent_recalc, |
| 3001 | }; | 2900 | }; |
| @@ -3005,231 +2904,16 @@ static struct clk sr_l4_ick = { | |||
| 3005 | /* XXX This clock no longer exists in 3430 TRM rev F */ | 2904 | /* XXX This clock no longer exists in 3430 TRM rev F */ |
| 3006 | static struct clk gpt12_fck = { | 2905 | static struct clk gpt12_fck = { |
| 3007 | .name = "gpt12_fck", | 2906 | .name = "gpt12_fck", |
| 2907 | .ops = &clkops_null, | ||
| 3008 | .parent = &secure_32k_fck, | 2908 | .parent = &secure_32k_fck, |
| 3009 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | ||
| 3010 | .recalc = &followparent_recalc, | 2909 | .recalc = &followparent_recalc, |
| 3011 | }; | 2910 | }; |
| 3012 | 2911 | ||
| 3013 | static struct clk wdt1_fck = { | 2912 | static struct clk wdt1_fck = { |
| 3014 | .name = "wdt1_fck", | 2913 | .name = "wdt1_fck", |
| 2914 | .ops = &clkops_null, | ||
| 3015 | .parent = &secure_32k_fck, | 2915 | .parent = &secure_32k_fck, |
| 3016 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | 2916 | .recalc = &followparent_recalc, |
| 3017 | .recalc = &followparent_recalc, | ||
| 3018 | }; | ||
| 3019 | |||
| 3020 | static struct clk *onchip_34xx_clks[] __initdata = { | ||
| 3021 | &omap_32k_fck, | ||
| 3022 | &virt_12m_ck, | ||
| 3023 | &virt_13m_ck, | ||
| 3024 | &virt_16_8m_ck, | ||
| 3025 | &virt_19_2m_ck, | ||
| 3026 | &virt_26m_ck, | ||
| 3027 | &virt_38_4m_ck, | ||
| 3028 | &osc_sys_ck, | ||
| 3029 | &sys_ck, | ||
| 3030 | &sys_altclk, | ||
| 3031 | &mcbsp_clks, | ||
| 3032 | &sys_clkout1, | ||
| 3033 | &dpll1_ck, | ||
| 3034 | &dpll1_x2_ck, | ||
| 3035 | &dpll1_x2m2_ck, | ||
| 3036 | &dpll2_ck, | ||
| 3037 | &dpll2_m2_ck, | ||
| 3038 | &dpll3_ck, | ||
| 3039 | &core_ck, | ||
| 3040 | &dpll3_x2_ck, | ||
| 3041 | &dpll3_m2_ck, | ||
| 3042 | &dpll3_m2x2_ck, | ||
| 3043 | &dpll3_m3_ck, | ||
| 3044 | &dpll3_m3x2_ck, | ||
| 3045 | &emu_core_alwon_ck, | ||
| 3046 | &dpll4_ck, | ||
| 3047 | &dpll4_x2_ck, | ||
| 3048 | &omap_96m_alwon_fck, | ||
| 3049 | &omap_96m_fck, | ||
| 3050 | &cm_96m_fck, | ||
| 3051 | &virt_omap_54m_fck, | ||
| 3052 | &omap_54m_fck, | ||
| 3053 | &omap_48m_fck, | ||
| 3054 | &omap_12m_fck, | ||
| 3055 | &dpll4_m2_ck, | ||
| 3056 | &dpll4_m2x2_ck, | ||
| 3057 | &dpll4_m3_ck, | ||
| 3058 | &dpll4_m3x2_ck, | ||
| 3059 | &dpll4_m4_ck, | ||
| 3060 | &dpll4_m4x2_ck, | ||
| 3061 | &dpll4_m5_ck, | ||
| 3062 | &dpll4_m5x2_ck, | ||
| 3063 | &dpll4_m6_ck, | ||
| 3064 | &dpll4_m6x2_ck, | ||
| 3065 | &emu_per_alwon_ck, | ||
| 3066 | &dpll5_ck, | ||
| 3067 | &dpll5_m2_ck, | ||
| 3068 | &omap_120m_fck, | ||
| 3069 | &clkout2_src_ck, | ||
| 3070 | &sys_clkout2, | ||
| 3071 | &corex2_fck, | ||
| 3072 | &dpll1_fck, | ||
| 3073 | &mpu_ck, | ||
| 3074 | &arm_fck, | ||
| 3075 | &emu_mpu_alwon_ck, | ||
| 3076 | &dpll2_fck, | ||
| 3077 | &iva2_ck, | ||
| 3078 | &l3_ick, | ||
| 3079 | &l4_ick, | ||
| 3080 | &rm_ick, | ||
| 3081 | &gfx_l3_ck, | ||
| 3082 | &gfx_l3_fck, | ||
| 3083 | &gfx_l3_ick, | ||
| 3084 | &gfx_cg1_ck, | ||
| 3085 | &gfx_cg2_ck, | ||
| 3086 | &sgx_fck, | ||
| 3087 | &sgx_ick, | ||
| 3088 | &d2d_26m_fck, | ||
| 3089 | &gpt10_fck, | ||
| 3090 | &gpt11_fck, | ||
| 3091 | &cpefuse_fck, | ||
| 3092 | &ts_fck, | ||
| 3093 | &usbtll_fck, | ||
| 3094 | &core_96m_fck, | ||
| 3095 | &mmchs3_fck, | ||
| 3096 | &mmchs2_fck, | ||
| 3097 | &mspro_fck, | ||
| 3098 | &mmchs1_fck, | ||
| 3099 | &i2c3_fck, | ||
| 3100 | &i2c2_fck, | ||
| 3101 | &i2c1_fck, | ||
| 3102 | &mcbsp5_fck, | ||
| 3103 | &mcbsp1_fck, | ||
| 3104 | &core_48m_fck, | ||
| 3105 | &mcspi4_fck, | ||
| 3106 | &mcspi3_fck, | ||
| 3107 | &mcspi2_fck, | ||
| 3108 | &mcspi1_fck, | ||
| 3109 | &uart2_fck, | ||
| 3110 | &uart1_fck, | ||
| 3111 | &fshostusb_fck, | ||
| 3112 | &core_12m_fck, | ||
| 3113 | &hdq_fck, | ||
| 3114 | &ssi_ssr_fck, | ||
| 3115 | &ssi_sst_fck, | ||
| 3116 | &core_l3_ick, | ||
| 3117 | &hsotgusb_ick, | ||
| 3118 | &sdrc_ick, | ||
| 3119 | &gpmc_fck, | ||
| 3120 | &security_l3_ick, | ||
| 3121 | &pka_ick, | ||
| 3122 | &core_l4_ick, | ||
| 3123 | &usbtll_ick, | ||
| 3124 | &mmchs3_ick, | ||
| 3125 | &icr_ick, | ||
| 3126 | &aes2_ick, | ||
| 3127 | &sha12_ick, | ||
| 3128 | &des2_ick, | ||
| 3129 | &mmchs2_ick, | ||
| 3130 | &mmchs1_ick, | ||
| 3131 | &mspro_ick, | ||
| 3132 | &hdq_ick, | ||
| 3133 | &mcspi4_ick, | ||
| 3134 | &mcspi3_ick, | ||
| 3135 | &mcspi2_ick, | ||
| 3136 | &mcspi1_ick, | ||
| 3137 | &i2c3_ick, | ||
| 3138 | &i2c2_ick, | ||
| 3139 | &i2c1_ick, | ||
| 3140 | &uart2_ick, | ||
| 3141 | &uart1_ick, | ||
| 3142 | &gpt11_ick, | ||
| 3143 | &gpt10_ick, | ||
| 3144 | &mcbsp5_ick, | ||
| 3145 | &mcbsp1_ick, | ||
| 3146 | &fac_ick, | ||
| 3147 | &mailboxes_ick, | ||
| 3148 | &omapctrl_ick, | ||
| 3149 | &ssi_l4_ick, | ||
| 3150 | &ssi_ick, | ||
| 3151 | &usb_l4_ick, | ||
| 3152 | &security_l4_ick2, | ||
| 3153 | &aes1_ick, | ||
| 3154 | &rng_ick, | ||
| 3155 | &sha11_ick, | ||
| 3156 | &des1_ick, | ||
| 3157 | &dss1_alwon_fck, | ||
| 3158 | &dss_tv_fck, | ||
| 3159 | &dss_96m_fck, | ||
| 3160 | &dss2_alwon_fck, | ||
| 3161 | &dss_ick, | ||
| 3162 | &cam_mclk, | ||
| 3163 | &cam_ick, | ||
| 3164 | &usbhost_120m_fck, | ||
| 3165 | &usbhost_48m_fck, | ||
| 3166 | &usbhost_ick, | ||
| 3167 | &usbhost_sar_fck, | ||
| 3168 | &usim_fck, | ||
| 3169 | &gpt1_fck, | ||
| 3170 | &wkup_32k_fck, | ||
| 3171 | &gpio1_dbck, | ||
| 3172 | &wdt2_fck, | ||
| 3173 | &wkup_l4_ick, | ||
| 3174 | &usim_ick, | ||
| 3175 | &wdt2_ick, | ||
| 3176 | &wdt1_ick, | ||
| 3177 | &gpio1_ick, | ||
| 3178 | &omap_32ksync_ick, | ||
| 3179 | &gpt12_ick, | ||
| 3180 | &gpt1_ick, | ||
| 3181 | &per_96m_fck, | ||
| 3182 | &per_48m_fck, | ||
| 3183 | &uart3_fck, | ||
| 3184 | &gpt2_fck, | ||
| 3185 | &gpt3_fck, | ||
| 3186 | &gpt4_fck, | ||
| 3187 | &gpt5_fck, | ||
| 3188 | &gpt6_fck, | ||
| 3189 | &gpt7_fck, | ||
| 3190 | &gpt8_fck, | ||
| 3191 | &gpt9_fck, | ||
| 3192 | &per_32k_alwon_fck, | ||
| 3193 | &gpio6_dbck, | ||
| 3194 | &gpio5_dbck, | ||
| 3195 | &gpio4_dbck, | ||
| 3196 | &gpio3_dbck, | ||
| 3197 | &gpio2_dbck, | ||
| 3198 | &wdt3_fck, | ||
| 3199 | &per_l4_ick, | ||
| 3200 | &gpio6_ick, | ||
| 3201 | &gpio5_ick, | ||
| 3202 | &gpio4_ick, | ||
| 3203 | &gpio3_ick, | ||
| 3204 | &gpio2_ick, | ||
| 3205 | &wdt3_ick, | ||
| 3206 | &uart3_ick, | ||
| 3207 | &gpt9_ick, | ||
| 3208 | &gpt8_ick, | ||
| 3209 | &gpt7_ick, | ||
| 3210 | &gpt6_ick, | ||
| 3211 | &gpt5_ick, | ||
| 3212 | &gpt4_ick, | ||
| 3213 | &gpt3_ick, | ||
| 3214 | &gpt2_ick, | ||
| 3215 | &mcbsp2_ick, | ||
| 3216 | &mcbsp3_ick, | ||
| 3217 | &mcbsp4_ick, | ||
| 3218 | &mcbsp2_fck, | ||
| 3219 | &mcbsp3_fck, | ||
| 3220 | &mcbsp4_fck, | ||
| 3221 | &emu_src_ck, | ||
| 3222 | &pclk_fck, | ||
| 3223 | &pclkx2_fck, | ||
| 3224 | &atclk_fck, | ||
| 3225 | &traceclk_src_fck, | ||
| 3226 | &traceclk_fck, | ||
| 3227 | &sr1_fck, | ||
| 3228 | &sr2_fck, | ||
| 3229 | &sr_l4_ick, | ||
| 3230 | &secure_32k_fck, | ||
| 3231 | &gpt12_fck, | ||
| 3232 | &wdt1_fck, | ||
| 3233 | }; | 2917 | }; |
| 3234 | 2918 | ||
| 3235 | #endif | 2919 | #endif |
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 4c3ce9cfd948..0e7d501865b6 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/delay.h> | 22 | #include <linux/delay.h> |
| 23 | #include <linux/clk.h> | 23 | #include <linux/clk.h> |
| 24 | #include <linux/limits.h> | 24 | #include <linux/limits.h> |
| 25 | #include <linux/err.h> | ||
| 25 | 26 | ||
| 26 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 27 | 28 | ||
| @@ -71,16 +72,13 @@ static void _autodep_lookup(struct clkdm_pwrdm_autodep *autodep) | |||
| 71 | if (!omap_chip_is(autodep->omap_chip)) | 72 | if (!omap_chip_is(autodep->omap_chip)) |
| 72 | return; | 73 | return; |
| 73 | 74 | ||
| 74 | pwrdm = pwrdm_lookup(autodep->pwrdm_name); | 75 | pwrdm = pwrdm_lookup(autodep->pwrdm.name); |
| 75 | if (!pwrdm) { | 76 | if (!pwrdm) { |
| 76 | pr_debug("clockdomain: _autodep_lookup: powerdomain %s " | 77 | pr_err("clockdomain: autodeps: powerdomain %s does not exist\n", |
| 77 | "does not exist\n", autodep->pwrdm_name); | 78 | autodep->pwrdm.name); |
| 78 | WARN_ON(1); | 79 | pwrdm = ERR_PTR(-ENOENT); |
| 79 | return; | ||
| 80 | } | 80 | } |
| 81 | autodep->pwrdm = pwrdm; | 81 | autodep->pwrdm.ptr = pwrdm; |
| 82 | |||
| 83 | return; | ||
| 84 | } | 82 | } |
| 85 | 83 | ||
| 86 | /* | 84 | /* |
| @@ -95,16 +93,19 @@ static void _clkdm_add_autodeps(struct clockdomain *clkdm) | |||
| 95 | { | 93 | { |
| 96 | struct clkdm_pwrdm_autodep *autodep; | 94 | struct clkdm_pwrdm_autodep *autodep; |
| 97 | 95 | ||
| 98 | for (autodep = autodeps; autodep->pwrdm_name; autodep++) { | 96 | for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) { |
| 99 | if (!autodep->pwrdm) | 97 | if (IS_ERR(autodep->pwrdm.ptr)) |
| 98 | continue; | ||
| 99 | |||
| 100 | if (!omap_chip_is(autodep->omap_chip)) | ||
| 100 | continue; | 101 | continue; |
| 101 | 102 | ||
| 102 | pr_debug("clockdomain: adding %s sleepdep/wkdep for " | 103 | pr_debug("clockdomain: adding %s sleepdep/wkdep for " |
| 103 | "pwrdm %s\n", autodep->pwrdm_name, | 104 | "pwrdm %s\n", autodep->pwrdm.ptr->name, |
| 104 | clkdm->pwrdm->name); | 105 | clkdm->pwrdm.ptr->name); |
| 105 | 106 | ||
| 106 | pwrdm_add_sleepdep(clkdm->pwrdm, autodep->pwrdm); | 107 | pwrdm_add_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr); |
| 107 | pwrdm_add_wkdep(clkdm->pwrdm, autodep->pwrdm); | 108 | pwrdm_add_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr); |
| 108 | } | 109 | } |
| 109 | } | 110 | } |
| 110 | 111 | ||
| @@ -120,16 +121,19 @@ static void _clkdm_del_autodeps(struct clockdomain *clkdm) | |||
| 120 | { | 121 | { |
| 121 | struct clkdm_pwrdm_autodep *autodep; | 122 | struct clkdm_pwrdm_autodep *autodep; |
| 122 | 123 | ||
| 123 | for (autodep = autodeps; autodep->pwrdm_name; autodep++) { | 124 | for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) { |
| 124 | if (!autodep->pwrdm) | 125 | if (IS_ERR(autodep->pwrdm.ptr)) |
| 126 | continue; | ||
| 127 | |||
| 128 | if (!omap_chip_is(autodep->omap_chip)) | ||
| 125 | continue; | 129 | continue; |
| 126 | 130 | ||
| 127 | pr_debug("clockdomain: removing %s sleepdep/wkdep for " | 131 | pr_debug("clockdomain: removing %s sleepdep/wkdep for " |
| 128 | "pwrdm %s\n", autodep->pwrdm_name, | 132 | "pwrdm %s\n", autodep->pwrdm.ptr->name, |
| 129 | clkdm->pwrdm->name); | 133 | clkdm->pwrdm.ptr->name); |
| 130 | 134 | ||
| 131 | pwrdm_del_sleepdep(clkdm->pwrdm, autodep->pwrdm); | 135 | pwrdm_del_sleepdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr); |
| 132 | pwrdm_del_wkdep(clkdm->pwrdm, autodep->pwrdm); | 136 | pwrdm_del_wkdep(clkdm->pwrdm.ptr, autodep->pwrdm.ptr); |
| 133 | } | 137 | } |
| 134 | } | 138 | } |
| 135 | 139 | ||
| @@ -179,7 +183,7 @@ void clkdm_init(struct clockdomain **clkdms, | |||
| 179 | 183 | ||
| 180 | autodeps = init_autodeps; | 184 | autodeps = init_autodeps; |
| 181 | if (autodeps) | 185 | if (autodeps) |
| 182 | for (autodep = autodeps; autodep->pwrdm_name; autodep++) | 186 | for (autodep = autodeps; autodep->pwrdm.ptr; autodep++) |
| 183 | _autodep_lookup(autodep); | 187 | _autodep_lookup(autodep); |
| 184 | } | 188 | } |
| 185 | 189 | ||
| @@ -202,20 +206,20 @@ int clkdm_register(struct clockdomain *clkdm) | |||
| 202 | if (!omap_chip_is(clkdm->omap_chip)) | 206 | if (!omap_chip_is(clkdm->omap_chip)) |
| 203 | return -EINVAL; | 207 | return -EINVAL; |
| 204 | 208 | ||
| 205 | pwrdm = pwrdm_lookup(clkdm->pwrdm_name); | 209 | pwrdm = pwrdm_lookup(clkdm->pwrdm.name); |
| 206 | if (!pwrdm) { | 210 | if (!pwrdm) { |
| 207 | pr_debug("clockdomain: clkdm_register %s: powerdomain %s " | 211 | pr_err("clockdomain: %s: powerdomain %s does not exist\n", |
| 208 | "does not exist\n", clkdm->name, clkdm->pwrdm_name); | 212 | clkdm->name, clkdm->pwrdm.name); |
| 209 | return -EINVAL; | 213 | return -EINVAL; |
| 210 | } | 214 | } |
| 211 | clkdm->pwrdm = pwrdm; | 215 | clkdm->pwrdm.ptr = pwrdm; |
| 212 | 216 | ||
| 213 | mutex_lock(&clkdm_mutex); | 217 | mutex_lock(&clkdm_mutex); |
| 214 | /* Verify that the clockdomain is not already registered */ | 218 | /* Verify that the clockdomain is not already registered */ |
| 215 | if (_clkdm_lookup(clkdm->name)) { | 219 | if (_clkdm_lookup(clkdm->name)) { |
| 216 | ret = -EEXIST; | 220 | ret = -EEXIST; |
| 217 | goto cr_unlock; | 221 | goto cr_unlock; |
| 218 | }; | 222 | } |
| 219 | 223 | ||
| 220 | list_add(&clkdm->node, &clkdm_list); | 224 | list_add(&clkdm->node, &clkdm_list); |
| 221 | 225 | ||
| @@ -242,7 +246,7 @@ int clkdm_unregister(struct clockdomain *clkdm) | |||
| 242 | if (!clkdm) | 246 | if (!clkdm) |
| 243 | return -EINVAL; | 247 | return -EINVAL; |
| 244 | 248 | ||
| 245 | pwrdm_del_clkdm(clkdm->pwrdm, clkdm); | 249 | pwrdm_del_clkdm(clkdm->pwrdm.ptr, clkdm); |
| 246 | 250 | ||
| 247 | mutex_lock(&clkdm_mutex); | 251 | mutex_lock(&clkdm_mutex); |
| 248 | list_del(&clkdm->node); | 252 | list_del(&clkdm->node); |
| @@ -327,7 +331,7 @@ struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm) | |||
| 327 | if (!clkdm) | 331 | if (!clkdm) |
| 328 | return NULL; | 332 | return NULL; |
| 329 | 333 | ||
| 330 | return clkdm->pwrdm; | 334 | return clkdm->pwrdm.ptr; |
| 331 | } | 335 | } |
| 332 | 336 | ||
| 333 | 337 | ||
| @@ -348,7 +352,7 @@ static int omap2_clkdm_clktrctrl_read(struct clockdomain *clkdm) | |||
| 348 | if (!clkdm) | 352 | if (!clkdm) |
| 349 | return -EINVAL; | 353 | return -EINVAL; |
| 350 | 354 | ||
| 351 | v = cm_read_mod_reg(clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL); | 355 | v = cm_read_mod_reg(clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); |
| 352 | v &= clkdm->clktrctrl_mask; | 356 | v &= clkdm->clktrctrl_mask; |
| 353 | v >>= __ffs(clkdm->clktrctrl_mask); | 357 | v >>= __ffs(clkdm->clktrctrl_mask); |
| 354 | 358 | ||
| @@ -380,7 +384,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) | |||
| 380 | if (cpu_is_omap24xx()) { | 384 | if (cpu_is_omap24xx()) { |
| 381 | 385 | ||
| 382 | cm_set_mod_reg_bits(OMAP24XX_FORCESTATE, | 386 | cm_set_mod_reg_bits(OMAP24XX_FORCESTATE, |
| 383 | clkdm->pwrdm->prcm_offs, PM_PWSTCTRL); | 387 | clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL); |
| 384 | 388 | ||
| 385 | } else if (cpu_is_omap34xx()) { | 389 | } else if (cpu_is_omap34xx()) { |
| 386 | 390 | ||
| @@ -388,7 +392,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) | |||
| 388 | __ffs(clkdm->clktrctrl_mask)); | 392 | __ffs(clkdm->clktrctrl_mask)); |
| 389 | 393 | ||
| 390 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, | 394 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, |
| 391 | clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL); | 395 | clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); |
| 392 | 396 | ||
| 393 | } else { | 397 | } else { |
| 394 | BUG(); | 398 | BUG(); |
| @@ -422,7 +426,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) | |||
| 422 | if (cpu_is_omap24xx()) { | 426 | if (cpu_is_omap24xx()) { |
| 423 | 427 | ||
| 424 | cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE, | 428 | cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE, |
| 425 | clkdm->pwrdm->prcm_offs, PM_PWSTCTRL); | 429 | clkdm->pwrdm.ptr->prcm_offs, PM_PWSTCTRL); |
| 426 | 430 | ||
| 427 | } else if (cpu_is_omap34xx()) { | 431 | } else if (cpu_is_omap34xx()) { |
| 428 | 432 | ||
| @@ -430,7 +434,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) | |||
| 430 | __ffs(clkdm->clktrctrl_mask)); | 434 | __ffs(clkdm->clktrctrl_mask)); |
| 431 | 435 | ||
| 432 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, | 436 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, v, |
| 433 | clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL); | 437 | clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); |
| 434 | 438 | ||
| 435 | } else { | 439 | } else { |
| 436 | BUG(); | 440 | BUG(); |
| @@ -478,7 +482,7 @@ void omap2_clkdm_allow_idle(struct clockdomain *clkdm) | |||
| 478 | 482 | ||
| 479 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, | 483 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, |
| 480 | v << __ffs(clkdm->clktrctrl_mask), | 484 | v << __ffs(clkdm->clktrctrl_mask), |
| 481 | clkdm->pwrdm->prcm_offs, | 485 | clkdm->pwrdm.ptr->prcm_offs, |
| 482 | CM_CLKSTCTRL); | 486 | CM_CLKSTCTRL); |
| 483 | } | 487 | } |
| 484 | 488 | ||
| @@ -516,7 +520,7 @@ void omap2_clkdm_deny_idle(struct clockdomain *clkdm) | |||
| 516 | 520 | ||
| 517 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, | 521 | cm_rmw_mod_reg_bits(clkdm->clktrctrl_mask, |
| 518 | v << __ffs(clkdm->clktrctrl_mask), | 522 | v << __ffs(clkdm->clktrctrl_mask), |
| 519 | clkdm->pwrdm->prcm_offs, CM_CLKSTCTRL); | 523 | clkdm->pwrdm.ptr->prcm_offs, CM_CLKSTCTRL); |
| 520 | 524 | ||
| 521 | if (atomic_read(&clkdm->usecount) > 0) | 525 | if (atomic_read(&clkdm->usecount) > 0) |
| 522 | _clkdm_del_autodeps(clkdm); | 526 | _clkdm_del_autodeps(clkdm); |
| @@ -567,6 +571,8 @@ int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk) | |||
| 567 | else | 571 | else |
| 568 | omap2_clkdm_wakeup(clkdm); | 572 | omap2_clkdm_wakeup(clkdm); |
| 569 | 573 | ||
| 574 | pwrdm_wait_transition(clkdm->pwrdm.ptr); | ||
| 575 | |||
| 570 | return 0; | 576 | return 0; |
| 571 | } | 577 | } |
| 572 | 578 | ||
diff --git a/arch/arm/mach-omap2/clockdomains.h b/arch/arm/mach-omap2/clockdomains.h index cd86dcc7b424..281d5da19188 100644 --- a/arch/arm/mach-omap2/clockdomains.h +++ b/arch/arm/mach-omap2/clockdomains.h | |||
| @@ -14,12 +14,29 @@ | |||
| 14 | 14 | ||
| 15 | /* | 15 | /* |
| 16 | * OMAP2/3-common clockdomains | 16 | * OMAP2/3-common clockdomains |
| 17 | * | ||
| 18 | * Even though the 2420 has a single PRCM module from the | ||
| 19 | * interconnect's perspective, internally it does appear to have | ||
| 20 | * separate PRM and CM clockdomains. The usual test case is | ||
| 21 | * sys_clkout/sys_clkout2. | ||
| 17 | */ | 22 | */ |
| 18 | 23 | ||
| 19 | /* This is an implicit clockdomain - it is never defined as such in TRM */ | 24 | /* This is an implicit clockdomain - it is never defined as such in TRM */ |
| 20 | static struct clockdomain wkup_clkdm = { | 25 | static struct clockdomain wkup_clkdm = { |
| 21 | .name = "wkup_clkdm", | 26 | .name = "wkup_clkdm", |
| 22 | .pwrdm_name = "wkup_pwrdm", | 27 | .pwrdm = { .name = "wkup_pwrdm" }, |
| 28 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | ||
| 29 | }; | ||
| 30 | |||
| 31 | static struct clockdomain prm_clkdm = { | ||
| 32 | .name = "prm_clkdm", | ||
| 33 | .pwrdm = { .name = "wkup_pwrdm" }, | ||
| 34 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | ||
| 35 | }; | ||
| 36 | |||
| 37 | static struct clockdomain cm_clkdm = { | ||
| 38 | .name = "cm_clkdm", | ||
| 39 | .pwrdm = { .name = "core_pwrdm" }, | ||
| 23 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | 40 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), |
| 24 | }; | 41 | }; |
| 25 | 42 | ||
| @@ -31,7 +48,7 @@ static struct clockdomain wkup_clkdm = { | |||
| 31 | 48 | ||
| 32 | static struct clockdomain mpu_2420_clkdm = { | 49 | static struct clockdomain mpu_2420_clkdm = { |
| 33 | .name = "mpu_clkdm", | 50 | .name = "mpu_clkdm", |
| 34 | .pwrdm_name = "mpu_pwrdm", | 51 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 35 | .flags = CLKDM_CAN_HWSUP, | 52 | .flags = CLKDM_CAN_HWSUP, |
| 36 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, | 53 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, |
| 37 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 54 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| @@ -39,7 +56,7 @@ static struct clockdomain mpu_2420_clkdm = { | |||
| 39 | 56 | ||
| 40 | static struct clockdomain iva1_2420_clkdm = { | 57 | static struct clockdomain iva1_2420_clkdm = { |
| 41 | .name = "iva1_clkdm", | 58 | .name = "iva1_clkdm", |
| 42 | .pwrdm_name = "dsp_pwrdm", | 59 | .pwrdm = { .name = "dsp_pwrdm" }, |
| 43 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 60 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 44 | .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, | 61 | .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK, |
| 45 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), | 62 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), |
| @@ -56,7 +73,7 @@ static struct clockdomain iva1_2420_clkdm = { | |||
| 56 | 73 | ||
| 57 | static struct clockdomain mpu_2430_clkdm = { | 74 | static struct clockdomain mpu_2430_clkdm = { |
| 58 | .name = "mpu_clkdm", | 75 | .name = "mpu_clkdm", |
| 59 | .pwrdm_name = "mpu_pwrdm", | 76 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 60 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 77 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 61 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, | 78 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK, |
| 62 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | 79 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| @@ -64,7 +81,7 @@ static struct clockdomain mpu_2430_clkdm = { | |||
| 64 | 81 | ||
| 65 | static struct clockdomain mdm_clkdm = { | 82 | static struct clockdomain mdm_clkdm = { |
| 66 | .name = "mdm_clkdm", | 83 | .name = "mdm_clkdm", |
| 67 | .pwrdm_name = "mdm_pwrdm", | 84 | .pwrdm = { .name = "mdm_pwrdm" }, |
| 68 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 85 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 69 | .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, | 86 | .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK, |
| 70 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), | 87 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), |
| @@ -81,7 +98,7 @@ static struct clockdomain mdm_clkdm = { | |||
| 81 | 98 | ||
| 82 | static struct clockdomain dsp_clkdm = { | 99 | static struct clockdomain dsp_clkdm = { |
| 83 | .name = "dsp_clkdm", | 100 | .name = "dsp_clkdm", |
| 84 | .pwrdm_name = "dsp_pwrdm", | 101 | .pwrdm = { .name = "dsp_pwrdm" }, |
| 85 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 102 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 86 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, | 103 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK, |
| 87 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 104 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
| @@ -89,7 +106,7 @@ static struct clockdomain dsp_clkdm = { | |||
| 89 | 106 | ||
| 90 | static struct clockdomain gfx_24xx_clkdm = { | 107 | static struct clockdomain gfx_24xx_clkdm = { |
| 91 | .name = "gfx_clkdm", | 108 | .name = "gfx_clkdm", |
| 92 | .pwrdm_name = "gfx_pwrdm", | 109 | .pwrdm = { .name = "gfx_pwrdm" }, |
| 93 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 110 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 94 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, | 111 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK, |
| 95 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 112 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
| @@ -97,7 +114,7 @@ static struct clockdomain gfx_24xx_clkdm = { | |||
| 97 | 114 | ||
| 98 | static struct clockdomain core_l3_24xx_clkdm = { | 115 | static struct clockdomain core_l3_24xx_clkdm = { |
| 99 | .name = "core_l3_clkdm", | 116 | .name = "core_l3_clkdm", |
| 100 | .pwrdm_name = "core_pwrdm", | 117 | .pwrdm = { .name = "core_pwrdm" }, |
| 101 | .flags = CLKDM_CAN_HWSUP, | 118 | .flags = CLKDM_CAN_HWSUP, |
| 102 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, | 119 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK, |
| 103 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 120 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
| @@ -105,7 +122,7 @@ static struct clockdomain core_l3_24xx_clkdm = { | |||
| 105 | 122 | ||
| 106 | static struct clockdomain core_l4_24xx_clkdm = { | 123 | static struct clockdomain core_l4_24xx_clkdm = { |
| 107 | .name = "core_l4_clkdm", | 124 | .name = "core_l4_clkdm", |
| 108 | .pwrdm_name = "core_pwrdm", | 125 | .pwrdm = { .name = "core_pwrdm" }, |
| 109 | .flags = CLKDM_CAN_HWSUP, | 126 | .flags = CLKDM_CAN_HWSUP, |
| 110 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, | 127 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK, |
| 111 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 128 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
| @@ -113,7 +130,7 @@ static struct clockdomain core_l4_24xx_clkdm = { | |||
| 113 | 130 | ||
| 114 | static struct clockdomain dss_24xx_clkdm = { | 131 | static struct clockdomain dss_24xx_clkdm = { |
| 115 | .name = "dss_clkdm", | 132 | .name = "dss_clkdm", |
| 116 | .pwrdm_name = "core_pwrdm", | 133 | .pwrdm = { .name = "core_pwrdm" }, |
| 117 | .flags = CLKDM_CAN_HWSUP, | 134 | .flags = CLKDM_CAN_HWSUP, |
| 118 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, | 135 | .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK, |
| 119 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), | 136 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX), |
| @@ -130,7 +147,7 @@ static struct clockdomain dss_24xx_clkdm = { | |||
| 130 | 147 | ||
| 131 | static struct clockdomain mpu_34xx_clkdm = { | 148 | static struct clockdomain mpu_34xx_clkdm = { |
| 132 | .name = "mpu_clkdm", | 149 | .name = "mpu_clkdm", |
| 133 | .pwrdm_name = "mpu_pwrdm", | 150 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 134 | .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, | 151 | .flags = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP, |
| 135 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, | 152 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK, |
| 136 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 153 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -138,7 +155,7 @@ static struct clockdomain mpu_34xx_clkdm = { | |||
| 138 | 155 | ||
| 139 | static struct clockdomain neon_clkdm = { | 156 | static struct clockdomain neon_clkdm = { |
| 140 | .name = "neon_clkdm", | 157 | .name = "neon_clkdm", |
| 141 | .pwrdm_name = "neon_pwrdm", | 158 | .pwrdm = { .name = "neon_pwrdm" }, |
| 142 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 159 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 143 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, | 160 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK, |
| 144 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 161 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -146,7 +163,7 @@ static struct clockdomain neon_clkdm = { | |||
| 146 | 163 | ||
| 147 | static struct clockdomain iva2_clkdm = { | 164 | static struct clockdomain iva2_clkdm = { |
| 148 | .name = "iva2_clkdm", | 165 | .name = "iva2_clkdm", |
| 149 | .pwrdm_name = "iva2_pwrdm", | 166 | .pwrdm = { .name = "iva2_pwrdm" }, |
| 150 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 167 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 151 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, | 168 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK, |
| 152 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 169 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -154,7 +171,7 @@ static struct clockdomain iva2_clkdm = { | |||
| 154 | 171 | ||
| 155 | static struct clockdomain gfx_3430es1_clkdm = { | 172 | static struct clockdomain gfx_3430es1_clkdm = { |
| 156 | .name = "gfx_clkdm", | 173 | .name = "gfx_clkdm", |
| 157 | .pwrdm_name = "gfx_pwrdm", | 174 | .pwrdm = { .name = "gfx_pwrdm" }, |
| 158 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 175 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 159 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, | 176 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK, |
| 160 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), | 177 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1), |
| @@ -162,10 +179,10 @@ static struct clockdomain gfx_3430es1_clkdm = { | |||
| 162 | 179 | ||
| 163 | static struct clockdomain sgx_clkdm = { | 180 | static struct clockdomain sgx_clkdm = { |
| 164 | .name = "sgx_clkdm", | 181 | .name = "sgx_clkdm", |
| 165 | .pwrdm_name = "sgx_pwrdm", | 182 | .pwrdm = { .name = "sgx_pwrdm" }, |
| 166 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 183 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 167 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, | 184 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK, |
| 168 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), | 185 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
| 169 | }; | 186 | }; |
| 170 | 187 | ||
| 171 | /* | 188 | /* |
| @@ -177,7 +194,7 @@ static struct clockdomain sgx_clkdm = { | |||
| 177 | */ | 194 | */ |
| 178 | static struct clockdomain d2d_clkdm = { | 195 | static struct clockdomain d2d_clkdm = { |
| 179 | .name = "d2d_clkdm", | 196 | .name = "d2d_clkdm", |
| 180 | .pwrdm_name = "core_pwrdm", | 197 | .pwrdm = { .name = "core_pwrdm" }, |
| 181 | .flags = CLKDM_CAN_HWSUP, | 198 | .flags = CLKDM_CAN_HWSUP, |
| 182 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, | 199 | .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK, |
| 183 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 200 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -185,7 +202,7 @@ static struct clockdomain d2d_clkdm = { | |||
| 185 | 202 | ||
| 186 | static struct clockdomain core_l3_34xx_clkdm = { | 203 | static struct clockdomain core_l3_34xx_clkdm = { |
| 187 | .name = "core_l3_clkdm", | 204 | .name = "core_l3_clkdm", |
| 188 | .pwrdm_name = "core_pwrdm", | 205 | .pwrdm = { .name = "core_pwrdm" }, |
| 189 | .flags = CLKDM_CAN_HWSUP, | 206 | .flags = CLKDM_CAN_HWSUP, |
| 190 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, | 207 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK, |
| 191 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 208 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -193,7 +210,7 @@ static struct clockdomain core_l3_34xx_clkdm = { | |||
| 193 | 210 | ||
| 194 | static struct clockdomain core_l4_34xx_clkdm = { | 211 | static struct clockdomain core_l4_34xx_clkdm = { |
| 195 | .name = "core_l4_clkdm", | 212 | .name = "core_l4_clkdm", |
| 196 | .pwrdm_name = "core_pwrdm", | 213 | .pwrdm = { .name = "core_pwrdm" }, |
| 197 | .flags = CLKDM_CAN_HWSUP, | 214 | .flags = CLKDM_CAN_HWSUP, |
| 198 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, | 215 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK, |
| 199 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 216 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -201,7 +218,7 @@ static struct clockdomain core_l4_34xx_clkdm = { | |||
| 201 | 218 | ||
| 202 | static struct clockdomain dss_34xx_clkdm = { | 219 | static struct clockdomain dss_34xx_clkdm = { |
| 203 | .name = "dss_clkdm", | 220 | .name = "dss_clkdm", |
| 204 | .pwrdm_name = "dss_pwrdm", | 221 | .pwrdm = { .name = "dss_pwrdm" }, |
| 205 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 222 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 206 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, | 223 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK, |
| 207 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 224 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -209,7 +226,7 @@ static struct clockdomain dss_34xx_clkdm = { | |||
| 209 | 226 | ||
| 210 | static struct clockdomain cam_clkdm = { | 227 | static struct clockdomain cam_clkdm = { |
| 211 | .name = "cam_clkdm", | 228 | .name = "cam_clkdm", |
| 212 | .pwrdm_name = "cam_pwrdm", | 229 | .pwrdm = { .name = "cam_pwrdm" }, |
| 213 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 230 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 214 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, | 231 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK, |
| 215 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 232 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| @@ -217,28 +234,62 @@ static struct clockdomain cam_clkdm = { | |||
| 217 | 234 | ||
| 218 | static struct clockdomain usbhost_clkdm = { | 235 | static struct clockdomain usbhost_clkdm = { |
| 219 | .name = "usbhost_clkdm", | 236 | .name = "usbhost_clkdm", |
| 220 | .pwrdm_name = "usbhost_pwrdm", | 237 | .pwrdm = { .name = "usbhost_pwrdm" }, |
| 221 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 238 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 222 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, | 239 | .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK, |
| 223 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), | 240 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
| 224 | }; | 241 | }; |
| 225 | 242 | ||
| 226 | static struct clockdomain per_clkdm = { | 243 | static struct clockdomain per_clkdm = { |
| 227 | .name = "per_clkdm", | 244 | .name = "per_clkdm", |
| 228 | .pwrdm_name = "per_pwrdm", | 245 | .pwrdm = { .name = "per_pwrdm" }, |
| 229 | .flags = CLKDM_CAN_HWSUP_SWSUP, | 246 | .flags = CLKDM_CAN_HWSUP_SWSUP, |
| 230 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, | 247 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK, |
| 231 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 248 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 232 | }; | 249 | }; |
| 233 | 250 | ||
| 251 | /* | ||
| 252 | * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is | ||
| 253 | * switched of even if sdti is in use | ||
| 254 | */ | ||
| 234 | static struct clockdomain emu_clkdm = { | 255 | static struct clockdomain emu_clkdm = { |
| 235 | .name = "emu_clkdm", | 256 | .name = "emu_clkdm", |
| 236 | .pwrdm_name = "emu_pwrdm", | 257 | .pwrdm = { .name = "emu_pwrdm" }, |
| 237 | .flags = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP, | 258 | .flags = /* CLKDM_CAN_ENABLE_AUTO | */CLKDM_CAN_SWSUP, |
| 238 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, | 259 | .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK, |
| 239 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 260 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), |
| 240 | }; | 261 | }; |
| 241 | 262 | ||
| 263 | static struct clockdomain dpll1_clkdm = { | ||
| 264 | .name = "dpll1_clkdm", | ||
| 265 | .pwrdm = { .name = "dpll1_pwrdm" }, | ||
| 266 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 267 | }; | ||
| 268 | |||
| 269 | static struct clockdomain dpll2_clkdm = { | ||
| 270 | .name = "dpll2_clkdm", | ||
| 271 | .pwrdm = { .name = "dpll2_pwrdm" }, | ||
| 272 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 273 | }; | ||
| 274 | |||
| 275 | static struct clockdomain dpll3_clkdm = { | ||
| 276 | .name = "dpll3_clkdm", | ||
| 277 | .pwrdm = { .name = "dpll3_pwrdm" }, | ||
| 278 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 279 | }; | ||
| 280 | |||
| 281 | static struct clockdomain dpll4_clkdm = { | ||
| 282 | .name = "dpll4_clkdm", | ||
| 283 | .pwrdm = { .name = "dpll4_pwrdm" }, | ||
| 284 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 285 | }; | ||
| 286 | |||
| 287 | static struct clockdomain dpll5_clkdm = { | ||
| 288 | .name = "dpll5_clkdm", | ||
| 289 | .pwrdm = { .name = "dpll5_pwrdm" }, | ||
| 290 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), | ||
| 291 | }; | ||
| 292 | |||
| 242 | #endif /* CONFIG_ARCH_OMAP34XX */ | 293 | #endif /* CONFIG_ARCH_OMAP34XX */ |
| 243 | 294 | ||
| 244 | /* | 295 | /* |
| @@ -247,14 +298,16 @@ static struct clockdomain emu_clkdm = { | |||
| 247 | 298 | ||
| 248 | static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = { | 299 | static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = { |
| 249 | { | 300 | { |
| 250 | .pwrdm_name = "mpu_pwrdm", | 301 | .pwrdm = { .name = "mpu_pwrdm" }, |
| 251 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | 302 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) |
| 252 | }, | 303 | }, |
| 253 | { | 304 | { |
| 254 | .pwrdm_name = "iva2_pwrdm", | 305 | .pwrdm = { .name = "iva2_pwrdm" }, |
| 255 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) | 306 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430) |
| 256 | }, | 307 | }, |
| 257 | { NULL } | 308 | { |
| 309 | .pwrdm = { .name = NULL }, | ||
| 310 | } | ||
| 258 | }; | 311 | }; |
| 259 | 312 | ||
| 260 | /* | 313 | /* |
| @@ -264,6 +317,8 @@ static struct clkdm_pwrdm_autodep clkdm_pwrdm_autodeps[] = { | |||
| 264 | static struct clockdomain *clockdomains_omap[] = { | 317 | static struct clockdomain *clockdomains_omap[] = { |
| 265 | 318 | ||
| 266 | &wkup_clkdm, | 319 | &wkup_clkdm, |
| 320 | &cm_clkdm, | ||
| 321 | &prm_clkdm, | ||
| 267 | 322 | ||
| 268 | #ifdef CONFIG_ARCH_OMAP2420 | 323 | #ifdef CONFIG_ARCH_OMAP2420 |
| 269 | &mpu_2420_clkdm, | 324 | &mpu_2420_clkdm, |
| @@ -297,6 +352,11 @@ static struct clockdomain *clockdomains_omap[] = { | |||
| 297 | &usbhost_clkdm, | 352 | &usbhost_clkdm, |
| 298 | &per_clkdm, | 353 | &per_clkdm, |
| 299 | &emu_clkdm, | 354 | &emu_clkdm, |
| 355 | &dpll1_clkdm, | ||
| 356 | &dpll2_clkdm, | ||
| 357 | &dpll3_clkdm, | ||
| 358 | &dpll4_clkdm, | ||
| 359 | &dpll5_clkdm, | ||
| 300 | #endif | 360 | #endif |
| 301 | 361 | ||
| 302 | NULL, | 362 | NULL, |
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 1098ecfab861..297a2fe634ea 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h | |||
| @@ -110,35 +110,56 @@ | |||
| 110 | #define OMAP24XX_EN_DES (1 << 0) | 110 | #define OMAP24XX_EN_DES (1 << 0) |
| 111 | 111 | ||
| 112 | /* CM_IDLEST1_CORE specific bits */ | 112 | /* CM_IDLEST1_CORE specific bits */ |
| 113 | #define OMAP24XX_ST_MAILBOXES (1 << 30) | 113 | #define OMAP24XX_ST_MAILBOXES_SHIFT 30 |
| 114 | #define OMAP24XX_ST_WDT4 (1 << 29) | 114 | #define OMAP24XX_ST_MAILBOXES_MASK (1 << 30) |
| 115 | #define OMAP2420_ST_WDT3 (1 << 28) | 115 | #define OMAP24XX_ST_WDT4_SHIFT 29 |
| 116 | #define OMAP24XX_ST_MSPRO (1 << 27) | 116 | #define OMAP24XX_ST_WDT4_MASK (1 << 29) |
| 117 | #define OMAP24XX_ST_FAC (1 << 25) | 117 | #define OMAP2420_ST_WDT3_SHIFT 28 |
| 118 | #define OMAP2420_ST_EAC (1 << 24) | 118 | #define OMAP2420_ST_WDT3_MASK (1 << 28) |
| 119 | #define OMAP24XX_ST_HDQ (1 << 23) | 119 | #define OMAP24XX_ST_MSPRO_SHIFT 27 |
| 120 | #define OMAP24XX_ST_I2C2 (1 << 20) | 120 | #define OMAP24XX_ST_MSPRO_MASK (1 << 27) |
| 121 | #define OMAP24XX_ST_I2C1 (1 << 19) | 121 | #define OMAP24XX_ST_FAC_SHIFT 25 |
| 122 | #define OMAP24XX_ST_MCBSP2 (1 << 16) | 122 | #define OMAP24XX_ST_FAC_MASK (1 << 25) |
| 123 | #define OMAP24XX_ST_MCBSP1 (1 << 15) | 123 | #define OMAP2420_ST_EAC_SHIFT 24 |
| 124 | #define OMAP24XX_ST_DSS (1 << 0) | 124 | #define OMAP2420_ST_EAC_MASK (1 << 24) |
| 125 | #define OMAP24XX_ST_HDQ_SHIFT 23 | ||
| 126 | #define OMAP24XX_ST_HDQ_MASK (1 << 23) | ||
| 127 | #define OMAP2420_ST_I2C2_SHIFT 20 | ||
| 128 | #define OMAP2420_ST_I2C2_MASK (1 << 20) | ||
| 129 | #define OMAP2420_ST_I2C1_SHIFT 19 | ||
| 130 | #define OMAP2420_ST_I2C1_MASK (1 << 19) | ||
| 131 | #define OMAP24XX_ST_MCBSP2_SHIFT 16 | ||
| 132 | #define OMAP24XX_ST_MCBSP2_MASK (1 << 16) | ||
| 133 | #define OMAP24XX_ST_MCBSP1_SHIFT 15 | ||
| 134 | #define OMAP24XX_ST_MCBSP1_MASK (1 << 15) | ||
| 135 | #define OMAP24XX_ST_DSS_SHIFT 0 | ||
| 136 | #define OMAP24XX_ST_DSS_MASK (1 << 0) | ||
| 125 | 137 | ||
| 126 | /* CM_IDLEST2_CORE */ | 138 | /* CM_IDLEST2_CORE */ |
| 127 | #define OMAP2430_ST_MCBSP5 (1 << 5) | 139 | #define OMAP2430_ST_MCBSP5_SHIFT 5 |
| 128 | #define OMAP2430_ST_MCBSP4 (1 << 4) | 140 | #define OMAP2430_ST_MCBSP5_MASK (1 << 5) |
| 129 | #define OMAP2430_ST_MCBSP3 (1 << 3) | 141 | #define OMAP2430_ST_MCBSP4_SHIFT 4 |
| 130 | #define OMAP24XX_ST_SSI (1 << 1) | 142 | #define OMAP2430_ST_MCBSP4_MASK (1 << 4) |
| 143 | #define OMAP2430_ST_MCBSP3_SHIFT 3 | ||
| 144 | #define OMAP2430_ST_MCBSP3_MASK (1 << 3) | ||
| 145 | #define OMAP24XX_ST_SSI_SHIFT 1 | ||
| 146 | #define OMAP24XX_ST_SSI_MASK (1 << 1) | ||
| 131 | 147 | ||
| 132 | /* CM_IDLEST3_CORE */ | 148 | /* CM_IDLEST3_CORE */ |
| 133 | /* 2430 only */ | 149 | /* 2430 only */ |
| 134 | #define OMAP2430_ST_SDRC (1 << 2) | 150 | #define OMAP2430_ST_SDRC_MASK (1 << 2) |
| 135 | 151 | ||
| 136 | /* CM_IDLEST4_CORE */ | 152 | /* CM_IDLEST4_CORE */ |
| 137 | #define OMAP24XX_ST_PKA (1 << 4) | 153 | #define OMAP24XX_ST_PKA_SHIFT 4 |
| 138 | #define OMAP24XX_ST_AES (1 << 3) | 154 | #define OMAP24XX_ST_PKA_MASK (1 << 4) |
| 139 | #define OMAP24XX_ST_RNG (1 << 2) | 155 | #define OMAP24XX_ST_AES_SHIFT 3 |
| 140 | #define OMAP24XX_ST_SHA (1 << 1) | 156 | #define OMAP24XX_ST_AES_MASK (1 << 3) |
| 141 | #define OMAP24XX_ST_DES (1 << 0) | 157 | #define OMAP24XX_ST_RNG_SHIFT 2 |
| 158 | #define OMAP24XX_ST_RNG_MASK (1 << 2) | ||
| 159 | #define OMAP24XX_ST_SHA_SHIFT 1 | ||
| 160 | #define OMAP24XX_ST_SHA_MASK (1 << 1) | ||
| 161 | #define OMAP24XX_ST_DES_SHIFT 0 | ||
| 162 | #define OMAP24XX_ST_DES_MASK (1 << 0) | ||
| 142 | 163 | ||
| 143 | /* CM_AUTOIDLE1_CORE */ | 164 | /* CM_AUTOIDLE1_CORE */ |
| 144 | #define OMAP24XX_AUTO_CAM (1 << 31) | 165 | #define OMAP24XX_AUTO_CAM (1 << 31) |
| @@ -275,11 +296,16 @@ | |||
| 275 | #define OMAP24XX_EN_32KSYNC (1 << 1) | 296 | #define OMAP24XX_EN_32KSYNC (1 << 1) |
| 276 | 297 | ||
| 277 | /* CM_IDLEST_WKUP specific bits */ | 298 | /* CM_IDLEST_WKUP specific bits */ |
| 278 | #define OMAP2430_ST_ICR (1 << 6) | 299 | #define OMAP2430_ST_ICR_SHIFT 6 |
| 279 | #define OMAP24XX_ST_OMAPCTRL (1 << 5) | 300 | #define OMAP2430_ST_ICR_MASK (1 << 6) |
| 280 | #define OMAP24XX_ST_WDT1 (1 << 4) | 301 | #define OMAP24XX_ST_OMAPCTRL_SHIFT 5 |
| 281 | #define OMAP24XX_ST_MPU_WDT (1 << 3) | 302 | #define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5) |
| 282 | #define OMAP24XX_ST_32KSYNC (1 << 1) | 303 | #define OMAP24XX_ST_WDT1_SHIFT 4 |
| 304 | #define OMAP24XX_ST_WDT1_MASK (1 << 4) | ||
| 305 | #define OMAP24XX_ST_MPU_WDT_SHIFT 3 | ||
| 306 | #define OMAP24XX_ST_MPU_WDT_MASK (1 << 3) | ||
| 307 | #define OMAP24XX_ST_32KSYNC_SHIFT 1 | ||
| 308 | #define OMAP24XX_ST_32KSYNC_MASK (1 << 1) | ||
| 283 | 309 | ||
| 284 | /* CM_AUTOIDLE_WKUP */ | 310 | /* CM_AUTOIDLE_WKUP */ |
| 285 | #define OMAP24XX_AUTO_OMAPCTRL (1 << 5) | 311 | #define OMAP24XX_AUTO_OMAPCTRL (1 << 5) |
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 219f5c8d9659..6f3f5a36aae6 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h | |||
| @@ -183,31 +183,58 @@ | |||
| 183 | #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) | 183 | #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) |
| 184 | 184 | ||
| 185 | /* CM_IDLEST1_CORE specific bits */ | 185 | /* CM_IDLEST1_CORE specific bits */ |
| 186 | #define OMAP3430_ST_ICR (1 << 29) | 186 | #define OMAP3430ES2_ST_MMC3_SHIFT 30 |
| 187 | #define OMAP3430_ST_AES2 (1 << 28) | 187 | #define OMAP3430ES2_ST_MMC3_MASK (1 << 30) |
| 188 | #define OMAP3430_ST_SHA12 (1 << 27) | 188 | #define OMAP3430_ST_ICR_SHIFT 29 |
| 189 | #define OMAP3430_ST_DES2 (1 << 26) | 189 | #define OMAP3430_ST_ICR_MASK (1 << 29) |
| 190 | #define OMAP3430_ST_MSPRO (1 << 23) | 190 | #define OMAP3430_ST_AES2_SHIFT 28 |
| 191 | #define OMAP3430_ST_HDQ (1 << 22) | 191 | #define OMAP3430_ST_AES2_MASK (1 << 28) |
| 192 | #define OMAP3430ES1_ST_FAC (1 << 8) | 192 | #define OMAP3430_ST_SHA12_SHIFT 27 |
| 193 | #define OMAP3430ES1_ST_MAILBOXES (1 << 7) | 193 | #define OMAP3430_ST_SHA12_MASK (1 << 27) |
| 194 | #define OMAP3430_ST_OMAPCTRL (1 << 6) | 194 | #define OMAP3430_ST_DES2_SHIFT 26 |
| 195 | #define OMAP3430_ST_SDMA (1 << 2) | 195 | #define OMAP3430_ST_DES2_MASK (1 << 26) |
| 196 | #define OMAP3430_ST_SDRC (1 << 1) | 196 | #define OMAP3430_ST_MSPRO_SHIFT 23 |
| 197 | #define OMAP3430_ST_SSI (1 << 0) | 197 | #define OMAP3430_ST_MSPRO_MASK (1 << 23) |
| 198 | #define OMAP3430_ST_HDQ_SHIFT 22 | ||
| 199 | #define OMAP3430_ST_HDQ_MASK (1 << 22) | ||
| 200 | #define OMAP3430ES1_ST_FAC_SHIFT 8 | ||
| 201 | #define OMAP3430ES1_ST_FAC_MASK (1 << 8) | ||
| 202 | #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 | ||
| 203 | #define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) | ||
| 204 | #define OMAP3430_ST_MAILBOXES_SHIFT 7 | ||
| 205 | #define OMAP3430_ST_MAILBOXES_MASK (1 << 7) | ||
| 206 | #define OMAP3430_ST_OMAPCTRL_SHIFT 6 | ||
| 207 | #define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) | ||
| 208 | #define OMAP3430_ST_SDMA_SHIFT 2 | ||
| 209 | #define OMAP3430_ST_SDMA_MASK (1 << 2) | ||
| 210 | #define OMAP3430_ST_SDRC_SHIFT 1 | ||
| 211 | #define OMAP3430_ST_SDRC_MASK (1 << 1) | ||
| 212 | #define OMAP3430_ST_SSI_STDBY_SHIFT 0 | ||
| 213 | #define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) | ||
| 198 | 214 | ||
| 199 | /* CM_IDLEST2_CORE */ | 215 | /* CM_IDLEST2_CORE */ |
| 200 | #define OMAP3430_ST_PKA (1 << 4) | 216 | #define OMAP3430_ST_PKA_SHIFT 4 |
| 201 | #define OMAP3430_ST_AES1 (1 << 3) | 217 | #define OMAP3430_ST_PKA_MASK (1 << 4) |
| 202 | #define OMAP3430_ST_RNG (1 << 2) | 218 | #define OMAP3430_ST_AES1_SHIFT 3 |
| 203 | #define OMAP3430_ST_SHA11 (1 << 1) | 219 | #define OMAP3430_ST_AES1_MASK (1 << 3) |
| 204 | #define OMAP3430_ST_DES1 (1 << 0) | 220 | #define OMAP3430_ST_RNG_SHIFT 2 |
| 221 | #define OMAP3430_ST_RNG_MASK (1 << 2) | ||
| 222 | #define OMAP3430_ST_SHA11_SHIFT 1 | ||
| 223 | #define OMAP3430_ST_SHA11_MASK (1 << 1) | ||
| 224 | #define OMAP3430_ST_DES1_SHIFT 0 | ||
| 225 | #define OMAP3430_ST_DES1_MASK (1 << 0) | ||
| 205 | 226 | ||
| 206 | /* CM_IDLEST3_CORE */ | 227 | /* CM_IDLEST3_CORE */ |
| 207 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 | 228 | #define OMAP3430ES2_ST_USBTLL_SHIFT 2 |
| 208 | #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) | 229 | #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) |
| 230 | #define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 | ||
| 231 | #define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) | ||
| 209 | 232 | ||
| 210 | /* CM_AUTOIDLE1_CORE */ | 233 | /* CM_AUTOIDLE1_CORE */ |
| 234 | #define OMAP3430ES2_AUTO_MMC3 (1 << 30) | ||
| 235 | #define OMAP3430ES2_AUTO_MMC3_SHIFT 30 | ||
| 236 | #define OMAP3430ES2_AUTO_ICR (1 << 29) | ||
| 237 | #define OMAP3430ES2_AUTO_ICR_SHIFT 29 | ||
| 211 | #define OMAP3430_AUTO_AES2 (1 << 28) | 238 | #define OMAP3430_AUTO_AES2 (1 << 28) |
| 212 | #define OMAP3430_AUTO_AES2_SHIFT 28 | 239 | #define OMAP3430_AUTO_AES2_SHIFT 28 |
| 213 | #define OMAP3430_AUTO_SHA12 (1 << 27) | 240 | #define OMAP3430_AUTO_SHA12 (1 << 27) |
| @@ -276,6 +303,9 @@ | |||
| 276 | #define OMAP3430_AUTO_DES1_SHIFT 0 | 303 | #define OMAP3430_AUTO_DES1_SHIFT 0 |
| 277 | 304 | ||
| 278 | /* CM_AUTOIDLE3_CORE */ | 305 | /* CM_AUTOIDLE3_CORE */ |
| 306 | #define OMAP3430ES2_AUTO_USBHOST (1 << 0) | ||
| 307 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | ||
| 308 | #define OMAP3430ES2_AUTO_USBTLL (1 << 2) | ||
| 279 | #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 | 309 | #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 |
| 280 | #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) | 310 | #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) |
| 281 | 311 | ||
| @@ -332,8 +362,12 @@ | |||
| 332 | #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) | 362 | #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) |
| 333 | 363 | ||
| 334 | /* CM_FCLKEN_SGX */ | 364 | /* CM_FCLKEN_SGX */ |
| 335 | #define OMAP3430ES2_EN_SGX_SHIFT 1 | 365 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 |
| 336 | #define OMAP3430ES2_EN_SGX_MASK (1 << 1) | 366 | #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) |
| 367 | |||
| 368 | /* CM_ICLKEN_SGX */ | ||
| 369 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 | ||
| 370 | #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) | ||
| 337 | 371 | ||
| 338 | /* CM_CLKSEL_SGX */ | 372 | /* CM_CLKSEL_SGX */ |
| 339 | #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 | 373 | #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 |
| @@ -349,6 +383,7 @@ | |||
| 349 | 383 | ||
| 350 | /* CM_FCLKEN_WKUP specific bits */ | 384 | /* CM_FCLKEN_WKUP specific bits */ |
| 351 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 | 385 | #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 |
| 386 | #define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) | ||
| 352 | 387 | ||
| 353 | /* CM_ICLKEN_WKUP specific bits */ | 388 | /* CM_ICLKEN_WKUP specific bits */ |
| 354 | #define OMAP3430_EN_WDT1 (1 << 4) | 389 | #define OMAP3430_EN_WDT1 (1 << 4) |
| @@ -357,11 +392,18 @@ | |||
| 357 | #define OMAP3430_EN_32KSYNC_SHIFT 2 | 392 | #define OMAP3430_EN_32KSYNC_SHIFT 2 |
| 358 | 393 | ||
| 359 | /* CM_IDLEST_WKUP specific bits */ | 394 | /* CM_IDLEST_WKUP specific bits */ |
| 360 | #define OMAP3430_ST_WDT2 (1 << 5) | 395 | #define OMAP3430ES2_ST_USIMOCP_SHIFT 9 |
| 361 | #define OMAP3430_ST_WDT1 (1 << 4) | 396 | #define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) |
| 362 | #define OMAP3430_ST_32KSYNC (1 << 2) | 397 | #define OMAP3430_ST_WDT2_SHIFT 5 |
| 398 | #define OMAP3430_ST_WDT2_MASK (1 << 5) | ||
| 399 | #define OMAP3430_ST_WDT1_SHIFT 4 | ||
| 400 | #define OMAP3430_ST_WDT1_MASK (1 << 4) | ||
| 401 | #define OMAP3430_ST_32KSYNC_SHIFT 2 | ||
| 402 | #define OMAP3430_ST_32KSYNC_MASK (1 << 2) | ||
| 363 | 403 | ||
| 364 | /* CM_AUTOIDLE_WKUP */ | 404 | /* CM_AUTOIDLE_WKUP */ |
| 405 | #define OMAP3430ES2_AUTO_USIMOCP (1 << 9) | ||
| 406 | #define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 | ||
| 365 | #define OMAP3430_AUTO_WDT2 (1 << 5) | 407 | #define OMAP3430_AUTO_WDT2 (1 << 5) |
| 366 | #define OMAP3430_AUTO_WDT2_SHIFT 5 | 408 | #define OMAP3430_AUTO_WDT2_SHIFT 5 |
| 367 | #define OMAP3430_AUTO_WDT1 (1 << 4) | 409 | #define OMAP3430_AUTO_WDT1 (1 << 4) |
| @@ -426,6 +468,8 @@ | |||
| 426 | #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) | 468 | #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) |
| 427 | 469 | ||
| 428 | /* CM_IDLEST2_CKGEN */ | 470 | /* CM_IDLEST2_CKGEN */ |
| 471 | #define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 | ||
| 472 | #define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) | ||
| 429 | #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 | 473 | #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 |
| 430 | #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) | 474 | #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) |
| 431 | #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 | 475 | #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 |
| @@ -449,8 +493,12 @@ | |||
| 449 | #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) | 493 | #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) |
| 450 | #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 | 494 | #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 |
| 451 | #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) | 495 | #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) |
| 452 | #define OMAP3430_SOURCE_54M (1 << 5) | 496 | #define OMAP3430_SOURCE_96M_SHIFT 6 |
| 453 | #define OMAP3430_SOURCE_48M (1 << 3) | 497 | #define OMAP3430_SOURCE_96M_MASK (1 << 6) |
| 498 | #define OMAP3430_SOURCE_54M_SHIFT 5 | ||
| 499 | #define OMAP3430_SOURCE_54M_MASK (1 << 5) | ||
| 500 | #define OMAP3430_SOURCE_48M_SHIFT 3 | ||
| 501 | #define OMAP3430_SOURCE_48M_MASK (1 << 3) | ||
| 454 | 502 | ||
| 455 | /* CM_CLKSEL2_PLL */ | 503 | /* CM_CLKSEL2_PLL */ |
| 456 | #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 | 504 | #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 |
| @@ -493,7 +541,12 @@ | |||
| 493 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 | 541 | #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 |
| 494 | 542 | ||
| 495 | /* CM_IDLEST_DSS */ | 543 | /* CM_IDLEST_DSS */ |
| 496 | #define OMAP3430_ST_DSS (1 << 0) | 544 | #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 |
| 545 | #define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) | ||
| 546 | #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 | ||
| 547 | #define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) | ||
| 548 | #define OMAP3430ES1_ST_DSS_SHIFT 0 | ||
| 549 | #define OMAP3430ES1_ST_DSS_MASK (1 << 0) | ||
| 497 | 550 | ||
| 498 | /* CM_AUTOIDLE_DSS */ | 551 | /* CM_AUTOIDLE_DSS */ |
| 499 | #define OMAP3430_AUTO_DSS (1 << 0) | 552 | #define OMAP3430_AUTO_DSS (1 << 0) |
| @@ -516,6 +569,8 @@ | |||
| 516 | #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) | 569 | #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) |
| 517 | 570 | ||
| 518 | /* CM_FCLKEN_CAM specific bits */ | 571 | /* CM_FCLKEN_CAM specific bits */ |
| 572 | #define OMAP3430_EN_CSI2 (1 << 1) | ||
| 573 | #define OMAP3430_EN_CSI2_SHIFT 1 | ||
| 519 | 574 | ||
| 520 | /* CM_ICLKEN_CAM specific bits */ | 575 | /* CM_ICLKEN_CAM specific bits */ |
| 521 | 576 | ||
| @@ -545,10 +600,14 @@ | |||
| 545 | /* CM_ICLKEN_PER specific bits */ | 600 | /* CM_ICLKEN_PER specific bits */ |
| 546 | 601 | ||
| 547 | /* CM_IDLEST_PER */ | 602 | /* CM_IDLEST_PER */ |
| 548 | #define OMAP3430_ST_WDT3 (1 << 12) | 603 | #define OMAP3430_ST_WDT3_SHIFT 12 |
| 549 | #define OMAP3430_ST_MCBSP4 (1 << 2) | 604 | #define OMAP3430_ST_WDT3_MASK (1 << 12) |
| 550 | #define OMAP3430_ST_MCBSP3 (1 << 1) | 605 | #define OMAP3430_ST_MCBSP4_SHIFT 2 |
| 551 | #define OMAP3430_ST_MCBSP2 (1 << 0) | 606 | #define OMAP3430_ST_MCBSP4_MASK (1 << 2) |
| 607 | #define OMAP3430_ST_MCBSP3_SHIFT 1 | ||
| 608 | #define OMAP3430_ST_MCBSP3_MASK (1 << 1) | ||
| 609 | #define OMAP3430_ST_MCBSP2_SHIFT 0 | ||
| 610 | #define OMAP3430_ST_MCBSP2_MASK (1 << 0) | ||
| 552 | 611 | ||
| 553 | /* CM_AUTOIDLE_PER */ | 612 | /* CM_AUTOIDLE_PER */ |
| 554 | #define OMAP3430_AUTO_GPIO6 (1 << 17) | 613 | #define OMAP3430_AUTO_GPIO6 (1 << 17) |
| @@ -676,6 +735,10 @@ | |||
| 676 | #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) | 735 | #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) |
| 677 | 736 | ||
| 678 | /* CM_IDLEST_USBHOST */ | 737 | /* CM_IDLEST_USBHOST */ |
| 738 | #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 | ||
| 739 | #define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) | ||
| 740 | #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 | ||
| 741 | #define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) | ||
| 679 | 742 | ||
| 680 | /* CM_AUTOIDLE_USBHOST */ | 743 | /* CM_AUTOIDLE_USBHOST */ |
| 681 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 | 744 | #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 |
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index ce03fa750775..d6b4b2f8722f 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c | |||
| @@ -28,13 +28,121 @@ | |||
| 28 | #include <mach/eac.h> | 28 | #include <mach/eac.h> |
| 29 | #include <mach/mmc.h> | 29 | #include <mach/mmc.h> |
| 30 | 30 | ||
| 31 | #if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) | 31 | #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE) |
| 32 | #define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE) | ||
| 33 | 32 | ||
| 34 | static struct resource mbox_resources[] = { | 33 | static struct resource cam_resources[] = { |
| 35 | { | 34 | { |
| 36 | .start = OMAP2_MBOX_BASE, | 35 | .start = OMAP24XX_CAMERA_BASE, |
| 37 | .end = OMAP2_MBOX_BASE + 0x11f, | 36 | .end = OMAP24XX_CAMERA_BASE + 0xfff, |
| 37 | .flags = IORESOURCE_MEM, | ||
| 38 | }, | ||
| 39 | { | ||
| 40 | .start = INT_24XX_CAM_IRQ, | ||
| 41 | .flags = IORESOURCE_IRQ, | ||
| 42 | } | ||
| 43 | }; | ||
| 44 | |||
| 45 | static struct platform_device omap_cam_device = { | ||
| 46 | .name = "omap24xxcam", | ||
| 47 | .id = -1, | ||
| 48 | .num_resources = ARRAY_SIZE(cam_resources), | ||
| 49 | .resource = cam_resources, | ||
| 50 | }; | ||
| 51 | |||
| 52 | static inline void omap_init_camera(void) | ||
| 53 | { | ||
| 54 | platform_device_register(&omap_cam_device); | ||
| 55 | } | ||
| 56 | |||
| 57 | #elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE) | ||
| 58 | |||
| 59 | static struct resource omap3isp_resources[] = { | ||
| 60 | { | ||
| 61 | .start = OMAP3430_ISP_BASE, | ||
| 62 | .end = OMAP3430_ISP_END, | ||
| 63 | .flags = IORESOURCE_MEM, | ||
| 64 | }, | ||
| 65 | { | ||
| 66 | .start = OMAP3430_ISP_CBUFF_BASE, | ||
| 67 | .end = OMAP3430_ISP_CBUFF_END, | ||
| 68 | .flags = IORESOURCE_MEM, | ||
| 69 | }, | ||
| 70 | { | ||
| 71 | .start = OMAP3430_ISP_CCP2_BASE, | ||
| 72 | .end = OMAP3430_ISP_CCP2_END, | ||
| 73 | .flags = IORESOURCE_MEM, | ||
| 74 | }, | ||
| 75 | { | ||
| 76 | .start = OMAP3430_ISP_CCDC_BASE, | ||
| 77 | .end = OMAP3430_ISP_CCDC_END, | ||
| 78 | .flags = IORESOURCE_MEM, | ||
| 79 | }, | ||
| 80 | { | ||
| 81 | .start = OMAP3430_ISP_HIST_BASE, | ||
| 82 | .end = OMAP3430_ISP_HIST_END, | ||
| 83 | .flags = IORESOURCE_MEM, | ||
| 84 | }, | ||
| 85 | { | ||
| 86 | .start = OMAP3430_ISP_H3A_BASE, | ||
| 87 | .end = OMAP3430_ISP_H3A_END, | ||
| 88 | .flags = IORESOURCE_MEM, | ||
| 89 | }, | ||
| 90 | { | ||
| 91 | .start = OMAP3430_ISP_PREV_BASE, | ||
| 92 | .end = OMAP3430_ISP_PREV_END, | ||
| 93 | .flags = IORESOURCE_MEM, | ||
| 94 | }, | ||
| 95 | { | ||
| 96 | .start = OMAP3430_ISP_RESZ_BASE, | ||
| 97 | .end = OMAP3430_ISP_RESZ_END, | ||
| 98 | .flags = IORESOURCE_MEM, | ||
| 99 | }, | ||
| 100 | { | ||
| 101 | .start = OMAP3430_ISP_SBL_BASE, | ||
| 102 | .end = OMAP3430_ISP_SBL_END, | ||
| 103 | .flags = IORESOURCE_MEM, | ||
| 104 | }, | ||
| 105 | { | ||
| 106 | .start = OMAP3430_ISP_CSI2A_BASE, | ||
| 107 | .end = OMAP3430_ISP_CSI2A_END, | ||
| 108 | .flags = IORESOURCE_MEM, | ||
| 109 | }, | ||
| 110 | { | ||
| 111 | .start = OMAP3430_ISP_CSI2PHY_BASE, | ||
| 112 | .end = OMAP3430_ISP_CSI2PHY_END, | ||
| 113 | .flags = IORESOURCE_MEM, | ||
| 114 | }, | ||
| 115 | { | ||
| 116 | .start = INT_34XX_CAM_IRQ, | ||
| 117 | .flags = IORESOURCE_IRQ, | ||
| 118 | } | ||
| 119 | }; | ||
| 120 | |||
| 121 | static struct platform_device omap3isp_device = { | ||
| 122 | .name = "omap3isp", | ||
| 123 | .id = -1, | ||
| 124 | .num_resources = ARRAY_SIZE(omap3isp_resources), | ||
| 125 | .resource = omap3isp_resources, | ||
| 126 | }; | ||
| 127 | |||
| 128 | static inline void omap_init_camera(void) | ||
| 129 | { | ||
| 130 | platform_device_register(&omap3isp_device); | ||
| 131 | } | ||
| 132 | #else | ||
| 133 | static inline void omap_init_camera(void) | ||
| 134 | { | ||
| 135 | } | ||
| 136 | #endif | ||
| 137 | |||
| 138 | #if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE) | ||
| 139 | |||
| 140 | #define MBOX_REG_SIZE 0x120 | ||
| 141 | |||
| 142 | static struct resource omap2_mbox_resources[] = { | ||
| 143 | { | ||
| 144 | .start = OMAP24XX_MAILBOX_BASE, | ||
| 145 | .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, | ||
| 38 | .flags = IORESOURCE_MEM, | 146 | .flags = IORESOURCE_MEM, |
| 39 | }, | 147 | }, |
| 40 | { | 148 | { |
| @@ -47,20 +155,40 @@ static struct resource mbox_resources[] = { | |||
| 47 | }, | 155 | }, |
| 48 | }; | 156 | }; |
| 49 | 157 | ||
| 158 | static struct resource omap3_mbox_resources[] = { | ||
| 159 | { | ||
| 160 | .start = OMAP34XX_MAILBOX_BASE, | ||
| 161 | .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1, | ||
| 162 | .flags = IORESOURCE_MEM, | ||
| 163 | }, | ||
| 164 | { | ||
| 165 | .start = INT_24XX_MAIL_U0_MPU, | ||
| 166 | .flags = IORESOURCE_IRQ, | ||
| 167 | }, | ||
| 168 | }; | ||
| 169 | |||
| 50 | static struct platform_device mbox_device = { | 170 | static struct platform_device mbox_device = { |
| 51 | .name = "mailbox", | 171 | .name = "omap2-mailbox", |
| 52 | .id = -1, | 172 | .id = -1, |
| 53 | .num_resources = ARRAY_SIZE(mbox_resources), | ||
| 54 | .resource = mbox_resources, | ||
| 55 | }; | 173 | }; |
| 56 | 174 | ||
| 57 | static inline void omap_init_mbox(void) | 175 | static inline void omap_init_mbox(void) |
| 58 | { | 176 | { |
| 177 | if (cpu_is_omap2420()) { | ||
| 178 | mbox_device.num_resources = ARRAY_SIZE(omap2_mbox_resources); | ||
| 179 | mbox_device.resource = omap2_mbox_resources; | ||
| 180 | } else if (cpu_is_omap3430()) { | ||
| 181 | mbox_device.num_resources = ARRAY_SIZE(omap3_mbox_resources); | ||
| 182 | mbox_device.resource = omap3_mbox_resources; | ||
| 183 | } else { | ||
| 184 | pr_err("%s: platform not supported\n", __func__); | ||
| 185 | return; | ||
| 186 | } | ||
| 59 | platform_device_register(&mbox_device); | 187 | platform_device_register(&mbox_device); |
| 60 | } | 188 | } |
| 61 | #else | 189 | #else |
| 62 | static inline void omap_init_mbox(void) { } | 190 | static inline void omap_init_mbox(void) { } |
| 63 | #endif | 191 | #endif /* CONFIG_OMAP_MBOX_FWK */ |
| 64 | 192 | ||
| 65 | #if defined(CONFIG_OMAP_STI) | 193 | #if defined(CONFIG_OMAP_STI) |
| 66 | 194 | ||
| @@ -348,11 +476,12 @@ static void __init omap_hsmmc_reset(void) | |||
| 348 | } | 476 | } |
| 349 | 477 | ||
| 350 | dummy_pdev.id = i; | 478 | dummy_pdev.id = i; |
| 351 | iclk = clk_get(dev, "mmchs_ick"); | 479 | dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i); |
| 480 | iclk = clk_get(dev, "ick"); | ||
| 352 | if (iclk && clk_enable(iclk)) | 481 | if (iclk && clk_enable(iclk)) |
| 353 | iclk = NULL; | 482 | iclk = NULL; |
| 354 | 483 | ||
| 355 | fclk = clk_get(dev, "mmchs_fck"); | 484 | fclk = clk_get(dev, "fck"); |
| 356 | if (fclk && clk_enable(fclk)) | 485 | if (fclk && clk_enable(fclk)) |
| 357 | fclk = NULL; | 486 | fclk = NULL; |
| 358 | 487 | ||
| @@ -506,6 +635,7 @@ static int __init omap2_init_devices(void) | |||
| 506 | * in alphabetical order so they're easier to sort through. | 635 | * in alphabetical order so they're easier to sort through. |
| 507 | */ | 636 | */ |
| 508 | omap_hsmmc_reset(); | 637 | omap_hsmmc_reset(); |
| 638 | omap_init_camera(); | ||
| 509 | omap_init_mbox(); | 639 | omap_init_mbox(); |
| 510 | omap_init_mcspi(); | 640 | omap_init_mcspi(); |
| 511 | omap_hdq_init(); | 641 | omap_hdq_init(); |
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index b52a02fc7cd6..34b5914e0f8b 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c | |||
| @@ -217,8 +217,13 @@ void __init omap2_check_revision(void) | |||
| 217 | omap_chip.oc = CHIP_IS_OMAP3430; | 217 | omap_chip.oc = CHIP_IS_OMAP3430; |
| 218 | if (omap_rev() == OMAP3430_REV_ES1_0) | 218 | if (omap_rev() == OMAP3430_REV_ES1_0) |
| 219 | omap_chip.oc |= CHIP_IS_OMAP3430ES1; | 219 | omap_chip.oc |= CHIP_IS_OMAP3430ES1; |
| 220 | else if (omap_rev() > OMAP3430_REV_ES1_0) | 220 | else if (omap_rev() >= OMAP3430_REV_ES2_0 && |
| 221 | omap_rev() <= OMAP3430_REV_ES2_1) | ||
| 221 | omap_chip.oc |= CHIP_IS_OMAP3430ES2; | 222 | omap_chip.oc |= CHIP_IS_OMAP3430ES2; |
| 223 | else if (omap_rev() == OMAP3430_REV_ES3_0) | ||
| 224 | omap_chip.oc |= CHIP_IS_OMAP3430ES3_0; | ||
| 225 | else if (omap_rev() == OMAP3430_REV_ES3_1) | ||
| 226 | omap_chip.oc |= CHIP_IS_OMAP3430ES3_1; | ||
| 222 | } else { | 227 | } else { |
| 223 | pr_err("Uninitialized omap_chip, please fix!\n"); | 228 | pr_err("Uninitialized omap_chip, please fix!\n"); |
| 224 | } | 229 | } |
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 5ea64f926ed5..916fcd3a2328 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
| @@ -27,8 +27,8 @@ | |||
| 27 | #include <mach/mux.h> | 27 | #include <mach/mux.h> |
| 28 | #include <mach/omapfb.h> | 28 | #include <mach/omapfb.h> |
| 29 | #include <mach/sram.h> | 29 | #include <mach/sram.h> |
| 30 | 30 | #include <mach/sdrc.h> | |
| 31 | #include "memory.h" | 31 | #include <mach/gpmc.h> |
| 32 | 32 | ||
| 33 | #include "clock.h" | 33 | #include "clock.h" |
| 34 | 34 | ||
| @@ -195,12 +195,12 @@ void __init omap2_map_common_io(void) | |||
| 195 | omapfb_reserve_sdram(); | 195 | omapfb_reserve_sdram(); |
| 196 | } | 196 | } |
| 197 | 197 | ||
| 198 | void __init omap2_init_common_hw(void) | 198 | void __init omap2_init_common_hw(struct omap_sdrc_params *sp) |
| 199 | { | 199 | { |
| 200 | omap2_mux_init(); | 200 | omap2_mux_init(); |
| 201 | pwrdm_init(powerdomains_omap); | 201 | pwrdm_init(powerdomains_omap); |
| 202 | clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); | 202 | clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); |
| 203 | omap2_clk_init(); | 203 | omap2_clk_init(); |
| 204 | omap2_init_memory(); | 204 | omap2_sdrc_init(sp); |
| 205 | gpmc_init(); | 205 | gpmc_init(); |
| 206 | } | 206 | } |
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c index 32b7af3c610b..fd5b8a5925cc 100644 --- a/arch/arm/mach-omap2/mailbox.c +++ b/arch/arm/mach-omap2/mailbox.c | |||
| @@ -1,9 +1,9 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Mailbox reservation modules for OMAP2 | 2 | * Mailbox reservation modules for OMAP2/3 |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 Nokia Corporation | 4 | * Copyright (C) 2006-2009 Nokia Corporation |
| 5 | * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | 5 | * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> |
| 6 | * and Paul Mundt <paul.mundt@nokia.com> | 6 | * and Paul Mundt |
| 7 | * | 7 | * |
| 8 | * This file is subject to the terms and conditions of the GNU General Public | 8 | * This file is subject to the terms and conditions of the GNU General Public |
| 9 | * License. See the file "COPYING" in the main directory of this archive | 9 | * License. See the file "COPYING" in the main directory of this archive |
| @@ -18,40 +18,22 @@ | |||
| 18 | #include <mach/mailbox.h> | 18 | #include <mach/mailbox.h> |
| 19 | #include <mach/irqs.h> | 19 | #include <mach/irqs.h> |
| 20 | 20 | ||
| 21 | #define MAILBOX_REVISION 0x00 | 21 | #define MAILBOX_REVISION 0x000 |
| 22 | #define MAILBOX_SYSCONFIG 0x10 | 22 | #define MAILBOX_SYSCONFIG 0x010 |
| 23 | #define MAILBOX_SYSSTATUS 0x14 | 23 | #define MAILBOX_SYSSTATUS 0x014 |
| 24 | #define MAILBOX_MESSAGE_0 0x40 | 24 | #define MAILBOX_MESSAGE(m) (0x040 + 4 * (m)) |
| 25 | #define MAILBOX_MESSAGE_1 0x44 | 25 | #define MAILBOX_FIFOSTATUS(m) (0x080 + 4 * (m)) |
| 26 | #define MAILBOX_MESSAGE_2 0x48 | 26 | #define MAILBOX_MSGSTATUS(m) (0x0c0 + 4 * (m)) |
| 27 | #define MAILBOX_MESSAGE_3 0x4c | 27 | #define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u)) |
| 28 | #define MAILBOX_MESSAGE_4 0x50 | 28 | #define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u)) |
| 29 | #define MAILBOX_MESSAGE_5 0x54 | 29 | |
| 30 | #define MAILBOX_FIFOSTATUS_0 0x80 | 30 | #define MAILBOX_IRQ_NEWMSG(u) (1 << (2 * (u))) |
| 31 | #define MAILBOX_FIFOSTATUS_1 0x84 | 31 | #define MAILBOX_IRQ_NOTFULL(u) (1 << (2 * (u) + 1)) |
| 32 | #define MAILBOX_FIFOSTATUS_2 0x88 | 32 | |
| 33 | #define MAILBOX_FIFOSTATUS_3 0x8c | 33 | #define MBOX_REG_SIZE 0x120 |
| 34 | #define MAILBOX_FIFOSTATUS_4 0x90 | 34 | #define MBOX_NR_REGS (MBOX_REG_SIZE / sizeof(u32)) |
| 35 | #define MAILBOX_FIFOSTATUS_5 0x94 | 35 | |
| 36 | #define MAILBOX_MSGSTATUS_0 0xc0 | 36 | static void __iomem *mbox_base; |
| 37 | #define MAILBOX_MSGSTATUS_1 0xc4 | ||
| 38 | #define MAILBOX_MSGSTATUS_2 0xc8 | ||
| 39 | #define MAILBOX_MSGSTATUS_3 0xcc | ||
| 40 | #define MAILBOX_MSGSTATUS_4 0xd0 | ||
| 41 | #define MAILBOX_MSGSTATUS_5 0xd4 | ||
| 42 | #define MAILBOX_IRQSTATUS_0 0x100 | ||
| 43 | #define MAILBOX_IRQENABLE_0 0x104 | ||
| 44 | #define MAILBOX_IRQSTATUS_1 0x108 | ||
| 45 | #define MAILBOX_IRQENABLE_1 0x10c | ||
| 46 | #define MAILBOX_IRQSTATUS_2 0x110 | ||
| 47 | #define MAILBOX_IRQENABLE_2 0x114 | ||
| 48 | #define MAILBOX_IRQSTATUS_3 0x118 | ||
| 49 | #define MAILBOX_IRQENABLE_3 0x11c | ||
| 50 | |||
| 51 | static unsigned long mbox_base; | ||
| 52 | |||
| 53 | #define MAILBOX_IRQ_NOTFULL(n) (1 << (2 * (n) + 1)) | ||
| 54 | #define MAILBOX_IRQ_NEWMSG(n) (1 << (2 * (n))) | ||
| 55 | 37 | ||
| 56 | struct omap_mbox2_fifo { | 38 | struct omap_mbox2_fifo { |
| 57 | unsigned long msg; | 39 | unsigned long msg; |
| @@ -66,6 +48,7 @@ struct omap_mbox2_priv { | |||
| 66 | unsigned long irqstatus; | 48 | unsigned long irqstatus; |
| 67 | u32 newmsg_bit; | 49 | u32 newmsg_bit; |
| 68 | u32 notfull_bit; | 50 | u32 notfull_bit; |
| 51 | u32 ctx[MBOX_NR_REGS]; | ||
| 69 | }; | 52 | }; |
| 70 | 53 | ||
| 71 | static struct clk *mbox_ick_handle; | 54 | static struct clk *mbox_ick_handle; |
| @@ -73,14 +56,14 @@ static struct clk *mbox_ick_handle; | |||
| 73 | static void omap2_mbox_enable_irq(struct omap_mbox *mbox, | 56 | static void omap2_mbox_enable_irq(struct omap_mbox *mbox, |
| 74 | omap_mbox_type_t irq); | 57 | omap_mbox_type_t irq); |
| 75 | 58 | ||
| 76 | static inline unsigned int mbox_read_reg(unsigned int reg) | 59 | static inline unsigned int mbox_read_reg(size_t ofs) |
| 77 | { | 60 | { |
| 78 | return __raw_readl(mbox_base + reg); | 61 | return __raw_readl(mbox_base + ofs); |
| 79 | } | 62 | } |
| 80 | 63 | ||
| 81 | static inline void mbox_write_reg(unsigned int val, unsigned int reg) | 64 | static inline void mbox_write_reg(u32 val, size_t ofs) |
| 82 | { | 65 | { |
| 83 | __raw_writel(val, mbox_base + reg); | 66 | __raw_writel(val, mbox_base + ofs); |
| 84 | } | 67 | } |
| 85 | 68 | ||
| 86 | /* Mailbox H/W preparations */ | 69 | /* Mailbox H/W preparations */ |
| @@ -95,6 +78,9 @@ static int omap2_mbox_startup(struct omap_mbox *mbox) | |||
| 95 | } | 78 | } |
| 96 | clk_enable(mbox_ick_handle); | 79 | clk_enable(mbox_ick_handle); |
| 97 | 80 | ||
| 81 | l = mbox_read_reg(MAILBOX_REVISION); | ||
| 82 | pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f)); | ||
| 83 | |||
| 98 | /* set smart-idle & autoidle */ | 84 | /* set smart-idle & autoidle */ |
| 99 | l = mbox_read_reg(MAILBOX_SYSCONFIG); | 85 | l = mbox_read_reg(MAILBOX_SYSCONFIG); |
| 100 | l |= 0x00000011; | 86 | l |= 0x00000011; |
| @@ -183,6 +169,32 @@ static int omap2_mbox_is_irq(struct omap_mbox *mbox, | |||
| 183 | return (enable & status & bit); | 169 | return (enable & status & bit); |
| 184 | } | 170 | } |
| 185 | 171 | ||
| 172 | static void omap2_mbox_save_ctx(struct omap_mbox *mbox) | ||
| 173 | { | ||
| 174 | int i; | ||
| 175 | struct omap_mbox2_priv *p = mbox->priv; | ||
| 176 | |||
| 177 | for (i = 0; i < MBOX_NR_REGS; i++) { | ||
| 178 | p->ctx[i] = mbox_read_reg(i * sizeof(u32)); | ||
| 179 | |||
| 180 | dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__, | ||
| 181 | i, p->ctx[i]); | ||
| 182 | } | ||
| 183 | } | ||
| 184 | |||
| 185 | static void omap2_mbox_restore_ctx(struct omap_mbox *mbox) | ||
| 186 | { | ||
| 187 | int i; | ||
| 188 | struct omap_mbox2_priv *p = mbox->priv; | ||
| 189 | |||
| 190 | for (i = 0; i < MBOX_NR_REGS; i++) { | ||
| 191 | mbox_write_reg(p->ctx[i], i * sizeof(u32)); | ||
| 192 | |||
| 193 | dev_dbg(mbox->dev, "%s: [%02x] %08x\n", __func__, | ||
| 194 | i, p->ctx[i]); | ||
| 195 | } | ||
| 196 | } | ||
| 197 | |||
| 186 | static struct omap_mbox_ops omap2_mbox_ops = { | 198 | static struct omap_mbox_ops omap2_mbox_ops = { |
| 187 | .type = OMAP_MBOX_TYPE2, | 199 | .type = OMAP_MBOX_TYPE2, |
| 188 | .startup = omap2_mbox_startup, | 200 | .startup = omap2_mbox_startup, |
| @@ -195,6 +207,8 @@ static struct omap_mbox_ops omap2_mbox_ops = { | |||
| 195 | .disable_irq = omap2_mbox_disable_irq, | 207 | .disable_irq = omap2_mbox_disable_irq, |
| 196 | .ack_irq = omap2_mbox_ack_irq, | 208 | .ack_irq = omap2_mbox_ack_irq, |
| 197 | .is_irq = omap2_mbox_is_irq, | 209 | .is_irq = omap2_mbox_is_irq, |
| 210 | .save_ctx = omap2_mbox_save_ctx, | ||
| 211 | .restore_ctx = omap2_mbox_restore_ctx, | ||
| 198 | }; | 212 | }; |
| 199 | 213 | ||
| 200 | /* | 214 | /* |
| @@ -209,15 +223,15 @@ static struct omap_mbox_ops omap2_mbox_ops = { | |||
| 209 | /* DSP */ | 223 | /* DSP */ |
| 210 | static struct omap_mbox2_priv omap2_mbox_dsp_priv = { | 224 | static struct omap_mbox2_priv omap2_mbox_dsp_priv = { |
| 211 | .tx_fifo = { | 225 | .tx_fifo = { |
| 212 | .msg = MAILBOX_MESSAGE_0, | 226 | .msg = MAILBOX_MESSAGE(0), |
| 213 | .fifo_stat = MAILBOX_FIFOSTATUS_0, | 227 | .fifo_stat = MAILBOX_FIFOSTATUS(0), |
| 214 | }, | 228 | }, |
| 215 | .rx_fifo = { | 229 | .rx_fifo = { |
| 216 | .msg = MAILBOX_MESSAGE_1, | 230 | .msg = MAILBOX_MESSAGE(1), |
| 217 | .msg_stat = MAILBOX_MSGSTATUS_1, | 231 | .msg_stat = MAILBOX_MSGSTATUS(1), |
| 218 | }, | 232 | }, |
| 219 | .irqenable = MAILBOX_IRQENABLE_0, | 233 | .irqenable = MAILBOX_IRQENABLE(0), |
| 220 | .irqstatus = MAILBOX_IRQSTATUS_0, | 234 | .irqstatus = MAILBOX_IRQSTATUS(0), |
| 221 | .notfull_bit = MAILBOX_IRQ_NOTFULL(0), | 235 | .notfull_bit = MAILBOX_IRQ_NOTFULL(0), |
| 222 | .newmsg_bit = MAILBOX_IRQ_NEWMSG(1), | 236 | .newmsg_bit = MAILBOX_IRQ_NEWMSG(1), |
| 223 | }; | 237 | }; |
| @@ -229,18 +243,18 @@ struct omap_mbox mbox_dsp_info = { | |||
| 229 | }; | 243 | }; |
| 230 | EXPORT_SYMBOL(mbox_dsp_info); | 244 | EXPORT_SYMBOL(mbox_dsp_info); |
| 231 | 245 | ||
| 232 | /* IVA */ | 246 | #if defined(CONFIG_ARCH_OMAP2420) /* IVA */ |
| 233 | static struct omap_mbox2_priv omap2_mbox_iva_priv = { | 247 | static struct omap_mbox2_priv omap2_mbox_iva_priv = { |
| 234 | .tx_fifo = { | 248 | .tx_fifo = { |
| 235 | .msg = MAILBOX_MESSAGE_2, | 249 | .msg = MAILBOX_MESSAGE(2), |
| 236 | .fifo_stat = MAILBOX_FIFOSTATUS_2, | 250 | .fifo_stat = MAILBOX_FIFOSTATUS(2), |
| 237 | }, | 251 | }, |
| 238 | .rx_fifo = { | 252 | .rx_fifo = { |
| 239 | .msg = MAILBOX_MESSAGE_3, | 253 | .msg = MAILBOX_MESSAGE(3), |
| 240 | .msg_stat = MAILBOX_MSGSTATUS_3, | 254 | .msg_stat = MAILBOX_MSGSTATUS(3), |
| 241 | }, | 255 | }, |
| 242 | .irqenable = MAILBOX_IRQENABLE_3, | 256 | .irqenable = MAILBOX_IRQENABLE(3), |
| 243 | .irqstatus = MAILBOX_IRQSTATUS_3, | 257 | .irqstatus = MAILBOX_IRQSTATUS(3), |
| 244 | .notfull_bit = MAILBOX_IRQ_NOTFULL(2), | 258 | .notfull_bit = MAILBOX_IRQ_NOTFULL(2), |
| 245 | .newmsg_bit = MAILBOX_IRQ_NEWMSG(3), | 259 | .newmsg_bit = MAILBOX_IRQ_NEWMSG(3), |
| 246 | }; | 260 | }; |
| @@ -250,17 +264,12 @@ static struct omap_mbox mbox_iva_info = { | |||
| 250 | .ops = &omap2_mbox_ops, | 264 | .ops = &omap2_mbox_ops, |
| 251 | .priv = &omap2_mbox_iva_priv, | 265 | .priv = &omap2_mbox_iva_priv, |
| 252 | }; | 266 | }; |
| 267 | #endif | ||
| 253 | 268 | ||
| 254 | static int __init omap2_mbox_probe(struct platform_device *pdev) | 269 | static int __devinit omap2_mbox_probe(struct platform_device *pdev) |
| 255 | { | 270 | { |
| 256 | struct resource *res; | 271 | struct resource *res; |
| 257 | int ret = 0; | 272 | int ret; |
| 258 | |||
| 259 | if (pdev->num_resources != 3) { | ||
| 260 | dev_err(&pdev->dev, "invalid number of resources: %d\n", | ||
| 261 | pdev->num_resources); | ||
| 262 | return -ENODEV; | ||
| 263 | } | ||
| 264 | 273 | ||
| 265 | /* MBOX base */ | 274 | /* MBOX base */ |
| 266 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 275 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| @@ -268,42 +277,61 @@ static int __init omap2_mbox_probe(struct platform_device *pdev) | |||
| 268 | dev_err(&pdev->dev, "invalid mem resource\n"); | 277 | dev_err(&pdev->dev, "invalid mem resource\n"); |
| 269 | return -ENODEV; | 278 | return -ENODEV; |
| 270 | } | 279 | } |
| 271 | mbox_base = res->start; | 280 | mbox_base = ioremap(res->start, res->end - res->start); |
| 281 | if (!mbox_base) | ||
| 282 | return -ENOMEM; | ||
| 272 | 283 | ||
| 273 | /* DSP IRQ */ | 284 | /* DSP or IVA2 IRQ */ |
| 274 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | 285 | mbox_dsp_info.irq = platform_get_irq(pdev, 0); |
| 275 | if (unlikely(!res)) { | 286 | if (mbox_dsp_info.irq < 0) { |
| 276 | dev_err(&pdev->dev, "invalid irq resource\n"); | 287 | dev_err(&pdev->dev, "invalid irq resource\n"); |
| 277 | return -ENODEV; | 288 | ret = -ENODEV; |
| 289 | goto err_dsp; | ||
| 278 | } | 290 | } |
| 279 | mbox_dsp_info.irq = res->start; | ||
| 280 | 291 | ||
| 281 | ret = omap_mbox_register(&mbox_dsp_info); | 292 | ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info); |
| 282 | 293 | if (ret) | |
| 283 | /* IVA IRQ */ | 294 | goto err_dsp; |
| 284 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); | 295 | |
| 285 | if (unlikely(!res)) { | 296 | #if defined(CONFIG_ARCH_OMAP2420) /* IVA */ |
| 286 | dev_err(&pdev->dev, "invalid irq resource\n"); | 297 | if (cpu_is_omap2420()) { |
| 287 | return -ENODEV; | 298 | /* IVA IRQ */ |
| 299 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); | ||
| 300 | if (unlikely(!res)) { | ||
| 301 | dev_err(&pdev->dev, "invalid irq resource\n"); | ||
| 302 | ret = -ENODEV; | ||
| 303 | goto err_iva1; | ||
| 304 | } | ||
| 305 | mbox_iva_info.irq = res->start; | ||
| 306 | ret = omap_mbox_register(&pdev->dev, &mbox_iva_info); | ||
| 307 | if (ret) | ||
| 308 | goto err_iva1; | ||
| 288 | } | 309 | } |
| 289 | mbox_iva_info.irq = res->start; | 310 | #endif |
| 290 | 311 | return 0; | |
| 291 | ret = omap_mbox_register(&mbox_iva_info); | ||
| 292 | 312 | ||
| 313 | err_iva1: | ||
| 314 | omap_mbox_unregister(&mbox_dsp_info); | ||
| 315 | err_dsp: | ||
| 316 | iounmap(mbox_base); | ||
| 293 | return ret; | 317 | return ret; |
| 294 | } | 318 | } |
| 295 | 319 | ||
| 296 | static int omap2_mbox_remove(struct platform_device *pdev) | 320 | static int __devexit omap2_mbox_remove(struct platform_device *pdev) |
| 297 | { | 321 | { |
| 322 | #if defined(CONFIG_ARCH_OMAP2420) | ||
| 323 | omap_mbox_unregister(&mbox_iva_info); | ||
| 324 | #endif | ||
| 298 | omap_mbox_unregister(&mbox_dsp_info); | 325 | omap_mbox_unregister(&mbox_dsp_info); |
| 326 | iounmap(mbox_base); | ||
| 299 | return 0; | 327 | return 0; |
| 300 | } | 328 | } |
| 301 | 329 | ||
| 302 | static struct platform_driver omap2_mbox_driver = { | 330 | static struct platform_driver omap2_mbox_driver = { |
| 303 | .probe = omap2_mbox_probe, | 331 | .probe = omap2_mbox_probe, |
| 304 | .remove = omap2_mbox_remove, | 332 | .remove = __devexit_p(omap2_mbox_remove), |
| 305 | .driver = { | 333 | .driver = { |
| 306 | .name = "mailbox", | 334 | .name = "omap2-mailbox", |
| 307 | }, | 335 | }, |
| 308 | }; | 336 | }; |
| 309 | 337 | ||
| @@ -320,4 +348,7 @@ static void __exit omap2_mbox_exit(void) | |||
| 320 | module_init(omap2_mbox_init); | 348 | module_init(omap2_mbox_init); |
| 321 | module_exit(omap2_mbox_exit); | 349 | module_exit(omap2_mbox_exit); |
| 322 | 350 | ||
| 323 | MODULE_LICENSE("GPL"); | 351 | MODULE_LICENSE("GPL v2"); |
| 352 | MODULE_DESCRIPTION("omap mailbox: omap2/3 architecture specific functions"); | ||
| 353 | MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU@nokia.com>, Paul Mundt"); | ||
| 354 | MODULE_ALIAS("platform:omap2-mailbox"); | ||
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c index a9e631fc1134..a5c0f0435cd6 100644 --- a/arch/arm/mach-omap2/mcbsp.c +++ b/arch/arm/mach-omap2/mcbsp.c | |||
| @@ -24,8 +24,6 @@ | |||
| 24 | #include <mach/cpu.h> | 24 | #include <mach/cpu.h> |
| 25 | #include <mach/mcbsp.h> | 25 | #include <mach/mcbsp.h> |
| 26 | 26 | ||
| 27 | const char *clk_names[] = { "mcbsp_ick", "mcbsp_fck" }; | ||
| 28 | |||
| 29 | static void omap2_mcbsp2_mux_setup(void) | 27 | static void omap2_mcbsp2_mux_setup(void) |
| 30 | { | 28 | { |
| 31 | omap_cfg_reg(Y15_24XX_MCBSP2_CLKX); | 29 | omap_cfg_reg(Y15_24XX_MCBSP2_CLKX); |
| @@ -57,8 +55,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { | |||
| 57 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, | 55 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
| 58 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, | 56 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
| 59 | .ops = &omap2_mcbsp_ops, | 57 | .ops = &omap2_mcbsp_ops, |
| 60 | .clk_names = clk_names, | ||
| 61 | .num_clks = 2, | ||
| 62 | }, | 58 | }, |
| 63 | { | 59 | { |
| 64 | .phys_base = OMAP24XX_MCBSP2_BASE, | 60 | .phys_base = OMAP24XX_MCBSP2_BASE, |
| @@ -67,8 +63,6 @@ static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = { | |||
| 67 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | 63 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
| 68 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, | 64 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
| 69 | .ops = &omap2_mcbsp_ops, | 65 | .ops = &omap2_mcbsp_ops, |
| 70 | .clk_names = clk_names, | ||
| 71 | .num_clks = 2, | ||
| 72 | }, | 66 | }, |
| 73 | }; | 67 | }; |
| 74 | #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) | 68 | #define OMAP2420_MCBSP_PDATA_SZ ARRAY_SIZE(omap2420_mcbsp_pdata) |
| @@ -86,8 +80,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
| 86 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, | 80 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
| 87 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, | 81 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
| 88 | .ops = &omap2_mcbsp_ops, | 82 | .ops = &omap2_mcbsp_ops, |
| 89 | .clk_names = clk_names, | ||
| 90 | .num_clks = 2, | ||
| 91 | }, | 83 | }, |
| 92 | { | 84 | { |
| 93 | .phys_base = OMAP24XX_MCBSP2_BASE, | 85 | .phys_base = OMAP24XX_MCBSP2_BASE, |
| @@ -96,8 +88,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
| 96 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | 88 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
| 97 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, | 89 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
| 98 | .ops = &omap2_mcbsp_ops, | 90 | .ops = &omap2_mcbsp_ops, |
| 99 | .clk_names = clk_names, | ||
| 100 | .num_clks = 2, | ||
| 101 | }, | 91 | }, |
| 102 | { | 92 | { |
| 103 | .phys_base = OMAP2430_MCBSP3_BASE, | 93 | .phys_base = OMAP2430_MCBSP3_BASE, |
| @@ -106,8 +96,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
| 106 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, | 96 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, |
| 107 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, | 97 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, |
| 108 | .ops = &omap2_mcbsp_ops, | 98 | .ops = &omap2_mcbsp_ops, |
| 109 | .clk_names = clk_names, | ||
| 110 | .num_clks = 2, | ||
| 111 | }, | 99 | }, |
| 112 | { | 100 | { |
| 113 | .phys_base = OMAP2430_MCBSP4_BASE, | 101 | .phys_base = OMAP2430_MCBSP4_BASE, |
| @@ -116,8 +104,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
| 116 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, | 104 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, |
| 117 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, | 105 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, |
| 118 | .ops = &omap2_mcbsp_ops, | 106 | .ops = &omap2_mcbsp_ops, |
| 119 | .clk_names = clk_names, | ||
| 120 | .num_clks = 2, | ||
| 121 | }, | 107 | }, |
| 122 | { | 108 | { |
| 123 | .phys_base = OMAP2430_MCBSP5_BASE, | 109 | .phys_base = OMAP2430_MCBSP5_BASE, |
| @@ -126,8 +112,6 @@ static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = { | |||
| 126 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, | 112 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, |
| 127 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, | 113 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, |
| 128 | .ops = &omap2_mcbsp_ops, | 114 | .ops = &omap2_mcbsp_ops, |
| 129 | .clk_names = clk_names, | ||
| 130 | .num_clks = 2, | ||
| 131 | }, | 115 | }, |
| 132 | }; | 116 | }; |
| 133 | #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) | 117 | #define OMAP2430_MCBSP_PDATA_SZ ARRAY_SIZE(omap2430_mcbsp_pdata) |
| @@ -145,8 +129,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 145 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, | 129 | .rx_irq = INT_24XX_MCBSP1_IRQ_RX, |
| 146 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, | 130 | .tx_irq = INT_24XX_MCBSP1_IRQ_TX, |
| 147 | .ops = &omap2_mcbsp_ops, | 131 | .ops = &omap2_mcbsp_ops, |
| 148 | .clk_names = clk_names, | ||
| 149 | .num_clks = 2, | ||
| 150 | }, | 132 | }, |
| 151 | { | 133 | { |
| 152 | .phys_base = OMAP34XX_MCBSP2_BASE, | 134 | .phys_base = OMAP34XX_MCBSP2_BASE, |
| @@ -155,8 +137,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 155 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, | 137 | .rx_irq = INT_24XX_MCBSP2_IRQ_RX, |
| 156 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, | 138 | .tx_irq = INT_24XX_MCBSP2_IRQ_TX, |
| 157 | .ops = &omap2_mcbsp_ops, | 139 | .ops = &omap2_mcbsp_ops, |
| 158 | .clk_names = clk_names, | ||
| 159 | .num_clks = 2, | ||
| 160 | }, | 140 | }, |
| 161 | { | 141 | { |
| 162 | .phys_base = OMAP34XX_MCBSP3_BASE, | 142 | .phys_base = OMAP34XX_MCBSP3_BASE, |
| @@ -165,8 +145,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 165 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, | 145 | .rx_irq = INT_24XX_MCBSP3_IRQ_RX, |
| 166 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, | 146 | .tx_irq = INT_24XX_MCBSP3_IRQ_TX, |
| 167 | .ops = &omap2_mcbsp_ops, | 147 | .ops = &omap2_mcbsp_ops, |
| 168 | .clk_names = clk_names, | ||
| 169 | .num_clks = 2, | ||
| 170 | }, | 148 | }, |
| 171 | { | 149 | { |
| 172 | .phys_base = OMAP34XX_MCBSP4_BASE, | 150 | .phys_base = OMAP34XX_MCBSP4_BASE, |
| @@ -175,8 +153,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 175 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, | 153 | .rx_irq = INT_24XX_MCBSP4_IRQ_RX, |
| 176 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, | 154 | .tx_irq = INT_24XX_MCBSP4_IRQ_TX, |
| 177 | .ops = &omap2_mcbsp_ops, | 155 | .ops = &omap2_mcbsp_ops, |
| 178 | .clk_names = clk_names, | ||
| 179 | .num_clks = 2, | ||
| 180 | }, | 156 | }, |
| 181 | { | 157 | { |
| 182 | .phys_base = OMAP34XX_MCBSP5_BASE, | 158 | .phys_base = OMAP34XX_MCBSP5_BASE, |
| @@ -185,8 +161,6 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = { | |||
| 185 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, | 161 | .rx_irq = INT_24XX_MCBSP5_IRQ_RX, |
| 186 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, | 162 | .tx_irq = INT_24XX_MCBSP5_IRQ_TX, |
| 187 | .ops = &omap2_mcbsp_ops, | 163 | .ops = &omap2_mcbsp_ops, |
| 188 | .clk_names = clk_names, | ||
| 189 | .num_clks = 2, | ||
| 190 | }, | 164 | }, |
| 191 | }; | 165 | }; |
| 192 | #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) | 166 | #define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata) |
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h deleted file mode 100644 index bb3db80a7c46..000000000000 --- a/arch/arm/mach-omap2/memory.h +++ /dev/null | |||
| @@ -1,43 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/memory.h | ||
| 3 | * | ||
| 4 | * Interface for memory timing related functions for OMAP24XX | ||
| 5 | * | ||
| 6 | * Copyright (C) 2005 Texas Instruments Inc. | ||
| 7 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 8 | * | ||
| 9 | * Copyright (C) 2005 Nokia Corporation | ||
| 10 | * Tony Lindgren <tony@atomide.com> | ||
| 11 | * | ||
| 12 | * This program is free software; you can redistribute it and/or modify | ||
| 13 | * it under the terms of the GNU General Public License version 2 as | ||
| 14 | * published by the Free Software Foundation. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef ARCH_ARM_MACH_OMAP2_MEMORY_H | ||
| 18 | #define ARCH_ARM_MACH_OMAP2_MEMORY_H | ||
| 19 | |||
| 20 | /* Memory timings */ | ||
| 21 | #define M_DDR 1 | ||
| 22 | #define M_LOCK_CTRL (1 << 2) | ||
| 23 | #define M_UNLOCK 0 | ||
| 24 | #define M_LOCK 1 | ||
| 25 | |||
| 26 | struct memory_timings { | ||
| 27 | u32 m_type; /* ddr = 1, sdr = 0 */ | ||
| 28 | u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */ | ||
| 29 | u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */ | ||
| 30 | u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */ | ||
| 31 | u32 base_cs; /* base chip select to use for calculations */ | ||
| 32 | }; | ||
| 33 | |||
| 34 | extern void omap2_init_memory_params(u32 force_lock_to_unlock_mode); | ||
| 35 | extern u32 omap2_memory_get_slow_dll_ctrl(void); | ||
| 36 | extern u32 omap2_memory_get_fast_dll_ctrl(void); | ||
| 37 | extern u32 omap2_memory_get_type(void); | ||
| 38 | u32 omap2_dll_force_needed(void); | ||
| 39 | u32 omap2_reprogram_sdrc(u32 level, u32 force); | ||
| 40 | void __init omap2_init_memory(void); | ||
| 41 | void __init gpmc_init(void); | ||
| 42 | |||
| 43 | #endif | ||
diff --git a/arch/arm/mach-omap2/mmc-twl4030.c b/arch/arm/mach-omap2/mmc-twl4030.c index 437f52073f6e..dc40b3e72206 100644 --- a/arch/arm/mach-omap2/mmc-twl4030.c +++ b/arch/arm/mach-omap2/mmc-twl4030.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <linux/delay.h> | 17 | #include <linux/delay.h> |
| 18 | #include <linux/gpio.h> | 18 | #include <linux/gpio.h> |
| 19 | #include <linux/i2c/twl4030.h> | 19 | #include <linux/i2c/twl4030.h> |
| 20 | #include <linux/regulator/machine.h> | ||
| 20 | 21 | ||
| 21 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
| 22 | #include <mach/control.h> | 23 | #include <mach/control.h> |
| @@ -44,6 +45,7 @@ | |||
| 44 | #define VMMC2_315V 0x0c | 45 | #define VMMC2_315V 0x0c |
| 45 | #define VMMC2_300V 0x0b | 46 | #define VMMC2_300V 0x0b |
| 46 | #define VMMC2_285V 0x0a | 47 | #define VMMC2_285V 0x0a |
| 48 | #define VMMC2_280V 0x09 | ||
| 47 | #define VMMC2_260V 0x08 | 49 | #define VMMC2_260V 0x08 |
| 48 | #define VMMC2_185V 0x06 | 50 | #define VMMC2_185V 0x06 |
| 49 | #define VMMC2_DEDICATED 0x2E | 51 | #define VMMC2_DEDICATED 0x2E |
| @@ -59,8 +61,8 @@ static struct twl_mmc_controller { | |||
| 59 | struct omap_mmc_platform_data *mmc; | 61 | struct omap_mmc_platform_data *mmc; |
| 60 | u8 twl_vmmc_dev_grp; | 62 | u8 twl_vmmc_dev_grp; |
| 61 | u8 twl_mmc_dedicated; | 63 | u8 twl_mmc_dedicated; |
| 62 | char name[HSMMC_NAME_LEN]; | 64 | char name[HSMMC_NAME_LEN + 1]; |
| 63 | } hsmmc[] = { | 65 | } hsmmc[OMAP34XX_NR_MMC] = { |
| 64 | { | 66 | { |
| 65 | .twl_vmmc_dev_grp = VMMC1_DEV_GRP, | 67 | .twl_vmmc_dev_grp = VMMC1_DEV_GRP, |
| 66 | .twl_mmc_dedicated = VMMC1_DEDICATED, | 68 | .twl_mmc_dedicated = VMMC1_DEDICATED, |
| @@ -98,6 +100,14 @@ static int twl_mmc_get_ro(struct device *dev, int slot) | |||
| 98 | return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); | 100 | return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); |
| 99 | } | 101 | } |
| 100 | 102 | ||
| 103 | static int twl_mmc_get_cover_state(struct device *dev, int slot) | ||
| 104 | { | ||
| 105 | struct omap_mmc_platform_data *mmc = dev->platform_data; | ||
| 106 | |||
| 107 | /* NOTE: assumes card detect signal is active-low */ | ||
| 108 | return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | ||
| 109 | } | ||
| 110 | |||
| 101 | /* | 111 | /* |
| 102 | * MMC Slot Initialization. | 112 | * MMC Slot Initialization. |
| 103 | */ | 113 | */ |
| @@ -166,66 +176,85 @@ static int twl_mmc_resume(struct device *dev, int slot) | |||
| 166 | /* | 176 | /* |
| 167 | * Sets the MMC voltage in twl4030 | 177 | * Sets the MMC voltage in twl4030 |
| 168 | */ | 178 | */ |
| 179 | |||
| 180 | #define MMC1_OCR (MMC_VDD_165_195 \ | ||
| 181 | |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32) | ||
| 182 | #define MMC2_OCR (MMC_VDD_165_195 \ | ||
| 183 | |MMC_VDD_25_26|MMC_VDD_26_27|MMC_VDD_27_28 \ | ||
| 184 | |MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31|MMC_VDD_31_32) | ||
| 185 | |||
| 169 | static int twl_mmc_set_voltage(struct twl_mmc_controller *c, int vdd) | 186 | static int twl_mmc_set_voltage(struct twl_mmc_controller *c, int vdd) |
| 170 | { | 187 | { |
| 171 | int ret; | 188 | int ret; |
| 172 | u8 vmmc, dev_grp_val; | 189 | u8 vmmc = 0, dev_grp_val; |
| 173 | 190 | ||
| 174 | switch (1 << vdd) { | 191 | if (!vdd) |
| 175 | case MMC_VDD_35_36: | 192 | goto doit; |
| 176 | case MMC_VDD_34_35: | 193 | |
| 177 | case MMC_VDD_33_34: | 194 | if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) { |
| 178 | case MMC_VDD_32_33: | 195 | /* VMMC1: max 220 mA. And for 8-bit mode, |
| 179 | case MMC_VDD_31_32: | 196 | * VSIM: max 50 mA |
| 180 | case MMC_VDD_30_31: | 197 | */ |
| 181 | if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) | 198 | switch (1 << vdd) { |
| 182 | vmmc = VMMC1_315V; | 199 | case MMC_VDD_165_195: |
| 183 | else | ||
| 184 | vmmc = VMMC2_315V; | ||
| 185 | break; | ||
| 186 | case MMC_VDD_29_30: | ||
| 187 | if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) | ||
| 188 | vmmc = VMMC1_315V; | ||
| 189 | else | ||
| 190 | vmmc = VMMC2_300V; | ||
| 191 | break; | ||
| 192 | case MMC_VDD_27_28: | ||
| 193 | case MMC_VDD_26_27: | ||
| 194 | if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) | ||
| 195 | vmmc = VMMC1_285V; | ||
| 196 | else | ||
| 197 | vmmc = VMMC2_285V; | ||
| 198 | break; | ||
| 199 | case MMC_VDD_25_26: | ||
| 200 | case MMC_VDD_24_25: | ||
| 201 | case MMC_VDD_23_24: | ||
| 202 | case MMC_VDD_22_23: | ||
| 203 | case MMC_VDD_21_22: | ||
| 204 | case MMC_VDD_20_21: | ||
| 205 | if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) | ||
| 206 | vmmc = VMMC1_285V; | ||
| 207 | else | ||
| 208 | vmmc = VMMC2_260V; | ||
| 209 | break; | ||
| 210 | case MMC_VDD_165_195: | ||
| 211 | if (c->twl_vmmc_dev_grp == VMMC1_DEV_GRP) | ||
| 212 | vmmc = VMMC1_185V; | 200 | vmmc = VMMC1_185V; |
| 213 | else | 201 | /* and VSIM_180V */ |
| 202 | break; | ||
| 203 | case MMC_VDD_28_29: | ||
| 204 | vmmc = VMMC1_285V; | ||
| 205 | /* and VSIM_280V */ | ||
| 206 | break; | ||
| 207 | case MMC_VDD_29_30: | ||
| 208 | case MMC_VDD_30_31: | ||
| 209 | vmmc = VMMC1_300V; | ||
| 210 | /* and VSIM_300V */ | ||
| 211 | break; | ||
| 212 | case MMC_VDD_31_32: | ||
| 213 | vmmc = VMMC1_315V; | ||
| 214 | /* error if VSIM needed */ | ||
| 215 | break; | ||
| 216 | default: | ||
| 217 | return -EINVAL; | ||
| 218 | } | ||
| 219 | } else if (c->twl_vmmc_dev_grp == VMMC2_DEV_GRP) { | ||
| 220 | /* VMMC2: max 100 mA */ | ||
| 221 | switch (1 << vdd) { | ||
| 222 | case MMC_VDD_165_195: | ||
| 214 | vmmc = VMMC2_185V; | 223 | vmmc = VMMC2_185V; |
| 215 | break; | 224 | break; |
| 216 | default: | 225 | case MMC_VDD_25_26: |
| 217 | vmmc = 0; | 226 | case MMC_VDD_26_27: |
| 218 | break; | 227 | vmmc = VMMC2_260V; |
| 228 | break; | ||
| 229 | case MMC_VDD_27_28: | ||
| 230 | vmmc = VMMC2_280V; | ||
| 231 | break; | ||
| 232 | case MMC_VDD_28_29: | ||
| 233 | vmmc = VMMC2_285V; | ||
| 234 | break; | ||
| 235 | case MMC_VDD_29_30: | ||
| 236 | case MMC_VDD_30_31: | ||
| 237 | vmmc = VMMC2_300V; | ||
| 238 | break; | ||
| 239 | case MMC_VDD_31_32: | ||
| 240 | vmmc = VMMC2_315V; | ||
| 241 | break; | ||
| 242 | default: | ||
| 243 | return -EINVAL; | ||
| 244 | } | ||
| 245 | } else { | ||
| 246 | return -EINVAL; | ||
| 219 | } | 247 | } |
| 220 | 248 | ||
| 221 | if (vmmc) | 249 | doit: |
| 250 | if (vdd) | ||
| 222 | dev_grp_val = VMMC_DEV_GRP_P1; /* Power up */ | 251 | dev_grp_val = VMMC_DEV_GRP_P1; /* Power up */ |
| 223 | else | 252 | else |
| 224 | dev_grp_val = LDO_CLR; /* Power down */ | 253 | dev_grp_val = LDO_CLR; /* Power down */ |
| 225 | 254 | ||
| 226 | ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, | 255 | ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, |
| 227 | dev_grp_val, c->twl_vmmc_dev_grp); | 256 | dev_grp_val, c->twl_vmmc_dev_grp); |
| 228 | if (ret) | 257 | if (ret || !vdd) |
| 229 | return ret; | 258 | return ret; |
| 230 | 259 | ||
| 231 | ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, | 260 | ret = twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, |
| @@ -242,6 +271,14 @@ static int twl_mmc1_set_power(struct device *dev, int slot, int power_on, | |||
| 242 | struct twl_mmc_controller *c = &hsmmc[0]; | 271 | struct twl_mmc_controller *c = &hsmmc[0]; |
| 243 | struct omap_mmc_platform_data *mmc = dev->platform_data; | 272 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
| 244 | 273 | ||
| 274 | /* | ||
| 275 | * Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the | ||
| 276 | * card using the same TWL VMMC1 supply (hsmmc[0]); OMAP has both | ||
| 277 | * 1.8V and 3.0V modes, controlled by the PBIAS register. | ||
| 278 | * | ||
| 279 | * In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which | ||
| 280 | * is most naturally TWL VSIM; those pins also use PBIAS. | ||
| 281 | */ | ||
| 245 | if (power_on) { | 282 | if (power_on) { |
| 246 | if (cpu_is_omap2430()) { | 283 | if (cpu_is_omap2430()) { |
| 247 | reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1); | 284 | reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1); |
| @@ -298,6 +335,12 @@ static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vd | |||
| 298 | struct twl_mmc_controller *c = &hsmmc[1]; | 335 | struct twl_mmc_controller *c = &hsmmc[1]; |
| 299 | struct omap_mmc_platform_data *mmc = dev->platform_data; | 336 | struct omap_mmc_platform_data *mmc = dev->platform_data; |
| 300 | 337 | ||
| 338 | /* | ||
| 339 | * Assume TWL VMMC2 (hsmmc[1]) is used only to power the card ... OMAP | ||
| 340 | * VDDS is used to power the pins, optionally with a transceiver to | ||
| 341 | * support cards using voltages other than VDDS (1.8V nominal). When a | ||
| 342 | * transceiver is used, DAT3..7 are muxed as transceiver control pins. | ||
| 343 | */ | ||
| 301 | if (power_on) { | 344 | if (power_on) { |
| 302 | if (mmc->slots[0].internal_clock) { | 345 | if (mmc->slots[0].internal_clock) { |
| 303 | u32 reg; | 346 | u32 reg; |
| @@ -314,6 +357,16 @@ static int twl_mmc2_set_power(struct device *dev, int slot, int power_on, int vd | |||
| 314 | return ret; | 357 | return ret; |
| 315 | } | 358 | } |
| 316 | 359 | ||
| 360 | static int twl_mmc3_set_power(struct device *dev, int slot, int power_on, | ||
| 361 | int vdd) | ||
| 362 | { | ||
| 363 | /* | ||
| 364 | * Assume MMC3 has self-powered device connected, for example on-board | ||
| 365 | * chip with external power source. | ||
| 366 | */ | ||
| 367 | return 0; | ||
| 368 | } | ||
| 369 | |||
| 317 | static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; | 370 | static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata; |
| 318 | 371 | ||
| 319 | void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) | 372 | void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) |
| @@ -349,13 +402,13 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) | |||
| 349 | return; | 402 | return; |
| 350 | } | 403 | } |
| 351 | 404 | ||
| 352 | sprintf(twl->name, "mmc%islot%i", c->mmc, 1); | 405 | if (c->name) |
| 406 | strncpy(twl->name, c->name, HSMMC_NAME_LEN); | ||
| 407 | else | ||
| 408 | snprintf(twl->name, ARRAY_SIZE(twl->name), | ||
| 409 | "mmc%islot%i", c->mmc, 1); | ||
| 353 | mmc->slots[0].name = twl->name; | 410 | mmc->slots[0].name = twl->name; |
| 354 | mmc->nr_slots = 1; | 411 | mmc->nr_slots = 1; |
| 355 | mmc->slots[0].ocr_mask = MMC_VDD_165_195 | | ||
| 356 | MMC_VDD_26_27 | MMC_VDD_27_28 | | ||
| 357 | MMC_VDD_29_30 | | ||
| 358 | MMC_VDD_30_31 | MMC_VDD_31_32; | ||
| 359 | mmc->slots[0].wires = c->wires; | 412 | mmc->slots[0].wires = c->wires; |
| 360 | mmc->slots[0].internal_clock = !c->ext_clock; | 413 | mmc->slots[0].internal_clock = !c->ext_clock; |
| 361 | mmc->dma_mask = 0xffffffff; | 414 | mmc->dma_mask = 0xffffffff; |
| @@ -369,7 +422,10 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) | |||
| 369 | 422 | ||
| 370 | mmc->slots[0].switch_pin = c->gpio_cd; | 423 | mmc->slots[0].switch_pin = c->gpio_cd; |
| 371 | mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd); | 424 | mmc->slots[0].card_detect_irq = gpio_to_irq(c->gpio_cd); |
| 372 | mmc->slots[0].card_detect = twl_mmc_card_detect; | 425 | if (c->cover_only) |
| 426 | mmc->slots[0].get_cover_state = twl_mmc_get_cover_state; | ||
| 427 | else | ||
| 428 | mmc->slots[0].card_detect = twl_mmc_card_detect; | ||
| 373 | } else | 429 | } else |
| 374 | mmc->slots[0].switch_pin = -EINVAL; | 430 | mmc->slots[0].switch_pin = -EINVAL; |
| 375 | 431 | ||
| @@ -385,24 +441,43 @@ void __init twl4030_mmc_init(struct twl4030_hsmmc_info *controllers) | |||
| 385 | 441 | ||
| 386 | /* NOTE: we assume OMAP's MMC1 and MMC2 use | 442 | /* NOTE: we assume OMAP's MMC1 and MMC2 use |
| 387 | * the TWL4030's VMMC1 and VMMC2, respectively; | 443 | * the TWL4030's VMMC1 and VMMC2, respectively; |
| 388 | * and that OMAP's MMC3 isn't used. | 444 | * and that MMC3 device has it's own power source. |
| 389 | */ | 445 | */ |
| 390 | 446 | ||
| 391 | switch (c->mmc) { | 447 | switch (c->mmc) { |
| 392 | case 1: | 448 | case 1: |
| 393 | mmc->slots[0].set_power = twl_mmc1_set_power; | 449 | mmc->slots[0].set_power = twl_mmc1_set_power; |
| 450 | mmc->slots[0].ocr_mask = MMC1_OCR; | ||
| 394 | break; | 451 | break; |
| 395 | case 2: | 452 | case 2: |
| 396 | mmc->slots[0].set_power = twl_mmc2_set_power; | 453 | mmc->slots[0].set_power = twl_mmc2_set_power; |
| 454 | if (c->transceiver) | ||
| 455 | mmc->slots[0].ocr_mask = MMC2_OCR; | ||
| 456 | else | ||
| 457 | mmc->slots[0].ocr_mask = MMC_VDD_165_195; | ||
| 458 | break; | ||
| 459 | case 3: | ||
| 460 | mmc->slots[0].set_power = twl_mmc3_set_power; | ||
| 461 | mmc->slots[0].ocr_mask = MMC_VDD_165_195; | ||
| 397 | break; | 462 | break; |
| 398 | default: | 463 | default: |
| 399 | pr_err("MMC%d configuration not supported!\n", c->mmc); | 464 | pr_err("MMC%d configuration not supported!\n", c->mmc); |
| 465 | kfree(mmc); | ||
| 400 | continue; | 466 | continue; |
| 401 | } | 467 | } |
| 402 | hsmmc_data[c->mmc - 1] = mmc; | 468 | hsmmc_data[c->mmc - 1] = mmc; |
| 403 | } | 469 | } |
| 404 | 470 | ||
| 405 | omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); | 471 | omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC); |
| 472 | |||
| 473 | /* pass the device nodes back to board setup code */ | ||
| 474 | for (c = controllers; c->mmc; c++) { | ||
| 475 | struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1]; | ||
| 476 | |||
| 477 | if (!c->mmc || c->mmc > nr_hsmmc) | ||
| 478 | continue; | ||
| 479 | c->dev = mmc->dev; | ||
| 480 | } | ||
| 406 | } | 481 | } |
| 407 | 482 | ||
| 408 | #endif | 483 | #endif |
diff --git a/arch/arm/mach-omap2/mmc-twl4030.h b/arch/arm/mach-omap2/mmc-twl4030.h index e1c8076400ca..ea59e8624290 100644 --- a/arch/arm/mach-omap2/mmc-twl4030.h +++ b/arch/arm/mach-omap2/mmc-twl4030.h | |||
| @@ -9,9 +9,13 @@ | |||
| 9 | struct twl4030_hsmmc_info { | 9 | struct twl4030_hsmmc_info { |
| 10 | u8 mmc; /* controller 1/2/3 */ | 10 | u8 mmc; /* controller 1/2/3 */ |
| 11 | u8 wires; /* 1/4/8 wires */ | 11 | u8 wires; /* 1/4/8 wires */ |
| 12 | bool transceiver; /* MMC-2 option */ | ||
| 13 | bool ext_clock; /* use external pin for input clock */ | ||
| 14 | bool cover_only; /* No card detect - just cover switch */ | ||
| 12 | int gpio_cd; /* or -EINVAL */ | 15 | int gpio_cd; /* or -EINVAL */ |
| 13 | int gpio_wp; /* or -EINVAL */ | 16 | int gpio_wp; /* or -EINVAL */ |
| 14 | int ext_clock:1; /* use external pin for input clock */ | 17 | char *name; /* or NULL for default */ |
| 18 | struct device *dev; /* returned: pointer to mmc adapter */ | ||
| 15 | }; | 19 | }; |
| 16 | 20 | ||
| 17 | #if defined(CONFIG_TWL4030_CORE) && \ | 21 | #if defined(CONFIG_TWL4030_CORE) && \ |
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index dacb41f130c0..026c4fc883a7 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c | |||
| @@ -453,10 +453,37 @@ MUX_CFG_34XX("AC1_3430_USB3FS_PHY_MM3_TXEN_N", 0x18a, | |||
| 453 | 453 | ||
| 454 | 454 | ||
| 455 | /* 34XX GPIO - bidirectional, unless the name has an "_OUT" suffix. | 455 | /* 34XX GPIO - bidirectional, unless the name has an "_OUT" suffix. |
| 456 | * (Always specify PIN_INPUT, except for names suffixed by "_OUT".) | ||
| 456 | * No internal pullup/pulldown without "_UP" or "_DOWN" suffix. | 457 | * No internal pullup/pulldown without "_UP" or "_DOWN" suffix. |
| 457 | */ | 458 | */ |
| 459 | MUX_CFG_34XX("AF26_34XX_GPIO0", 0x1e0, | ||
| 460 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
| 461 | MUX_CFG_34XX("AF22_34XX_GPIO9", 0xa18, | ||
| 462 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
| 458 | MUX_CFG_34XX("AH8_34XX_GPIO29", 0x5fa, | 463 | MUX_CFG_34XX("AH8_34XX_GPIO29", 0x5fa, |
| 459 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | 464 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) |
| 465 | MUX_CFG_34XX("U8_34XX_GPIO54_OUT", 0x0b4, | ||
| 466 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) | ||
| 467 | MUX_CFG_34XX("U8_34XX_GPIO54_DOWN", 0x0b4, | ||
| 468 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLDOWN) | ||
| 469 | MUX_CFG_34XX("L8_34XX_GPIO63", 0x0ce, | ||
| 470 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
| 471 | MUX_CFG_34XX("G25_34XX_GPIO86_OUT", 0x0fc, | ||
| 472 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) | ||
| 473 | MUX_CFG_34XX("AG4_34XX_GPIO134_OUT", 0x160, | ||
| 474 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) | ||
| 475 | MUX_CFG_34XX("AE4_34XX_GPIO136_OUT", 0x164, | ||
| 476 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) | ||
| 477 | MUX_CFG_34XX("AF6_34XX_GPIO140_UP", 0x16c, | ||
| 478 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT_PULLUP) | ||
| 479 | MUX_CFG_34XX("AE6_34XX_GPIO141", 0x16e, | ||
| 480 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
| 481 | MUX_CFG_34XX("AF5_34XX_GPIO142", 0x170, | ||
| 482 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
| 483 | MUX_CFG_34XX("AE5_34XX_GPIO143", 0x172, | ||
| 484 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | ||
| 485 | MUX_CFG_34XX("H19_34XX_GPIO164_OUT", 0x19c, | ||
| 486 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_OUTPUT) | ||
| 460 | MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6, | 487 | MUX_CFG_34XX("J25_34XX_GPIO170", 0x1c6, |
| 461 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) | 488 | OMAP34XX_MUX_MODE4 | OMAP34XX_PIN_INPUT) |
| 462 | }; | 489 | }; |
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 55361c16c9d9..ea8ceaed09cb 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c | |||
| @@ -103,7 +103,7 @@ static struct platform_suspend_ops omap_pm_ops = { | |||
| 103 | .valid = suspend_valid_only_mem, | 103 | .valid = suspend_valid_only_mem, |
| 104 | }; | 104 | }; |
| 105 | 105 | ||
| 106 | int __init omap2_pm_init(void) | 106 | static int __init omap2_pm_init(void) |
| 107 | { | 107 | { |
| 108 | return 0; | 108 | return 0; |
| 109 | } | 109 | } |
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h index 1e151faebbd3..691470ea4c6a 100644 --- a/arch/arm/mach-omap2/powerdomains.h +++ b/arch/arm/mach-omap2/powerdomains.h | |||
| @@ -171,13 +171,19 @@ static struct powerdomain *powerdomains_omap[] __initdata = { | |||
| 171 | &iva2_pwrdm, | 171 | &iva2_pwrdm, |
| 172 | &mpu_34xx_pwrdm, | 172 | &mpu_34xx_pwrdm, |
| 173 | &neon_pwrdm, | 173 | &neon_pwrdm, |
| 174 | &core_34xx_pwrdm, | 174 | &core_34xx_pre_es3_1_pwrdm, |
| 175 | &core_34xx_es3_1_pwrdm, | ||
| 175 | &cam_pwrdm, | 176 | &cam_pwrdm, |
| 176 | &dss_pwrdm, | 177 | &dss_pwrdm, |
| 177 | &per_pwrdm, | 178 | &per_pwrdm, |
| 178 | &emu_pwrdm, | 179 | &emu_pwrdm, |
| 179 | &sgx_pwrdm, | 180 | &sgx_pwrdm, |
| 180 | &usbhost_pwrdm, | 181 | &usbhost_pwrdm, |
| 182 | &dpll1_pwrdm, | ||
| 183 | &dpll2_pwrdm, | ||
| 184 | &dpll3_pwrdm, | ||
| 185 | &dpll4_pwrdm, | ||
| 186 | &dpll5_pwrdm, | ||
| 181 | #endif | 187 | #endif |
| 182 | 188 | ||
| 183 | NULL | 189 | NULL |
diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index f573f7108398..4dcf94b800ab 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h | |||
| @@ -200,12 +200,33 @@ static struct powerdomain mpu_34xx_pwrdm = { | |||
| 200 | }; | 200 | }; |
| 201 | 201 | ||
| 202 | /* No wkdeps or sleepdeps for 34xx core apparently */ | 202 | /* No wkdeps or sleepdeps for 34xx core apparently */ |
| 203 | static struct powerdomain core_34xx_pwrdm = { | 203 | static struct powerdomain core_34xx_pre_es3_1_pwrdm = { |
| 204 | .name = "core_pwrdm", | 204 | .name = "core_pwrdm", |
| 205 | .prcm_offs = CORE_MOD, | 205 | .prcm_offs = CORE_MOD, |
| 206 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | 206 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | |
| 207 | CHIP_IS_OMAP3430ES2 | | ||
| 208 | CHIP_IS_OMAP3430ES3_0), | ||
| 209 | .pwrsts = PWRSTS_OFF_RET_ON, | ||
| 210 | .dep_bit = OMAP3430_EN_CORE_SHIFT, | ||
| 211 | .banks = 2, | ||
| 212 | .pwrsts_mem_ret = { | ||
| 213 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ | ||
| 214 | [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ | ||
| 215 | }, | ||
| 216 | .pwrsts_mem_on = { | ||
| 217 | [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ | ||
| 218 | [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ | ||
| 219 | }, | ||
| 220 | }; | ||
| 221 | |||
| 222 | /* No wkdeps or sleepdeps for 34xx core apparently */ | ||
| 223 | static struct powerdomain core_34xx_es3_1_pwrdm = { | ||
| 224 | .name = "core_pwrdm", | ||
| 225 | .prcm_offs = CORE_MOD, | ||
| 226 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), | ||
| 207 | .pwrsts = PWRSTS_OFF_RET_ON, | 227 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 208 | .dep_bit = OMAP3430_EN_CORE_SHIFT, | 228 | .dep_bit = OMAP3430_EN_CORE_SHIFT, |
| 229 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ | ||
| 209 | .banks = 2, | 230 | .banks = 2, |
| 210 | .pwrsts_mem_ret = { | 231 | .pwrsts_mem_ret = { |
| 211 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ | 232 | [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ |
| @@ -236,14 +257,19 @@ static struct powerdomain dss_pwrdm = { | |||
| 236 | }, | 257 | }, |
| 237 | }; | 258 | }; |
| 238 | 259 | ||
| 260 | /* | ||
| 261 | * Although the 34XX TRM Rev K Table 4-371 notes that retention is a | ||
| 262 | * possible SGX powerstate, the SGX device itself does not support | ||
| 263 | * retention. | ||
| 264 | */ | ||
| 239 | static struct powerdomain sgx_pwrdm = { | 265 | static struct powerdomain sgx_pwrdm = { |
| 240 | .name = "sgx_pwrdm", | 266 | .name = "sgx_pwrdm", |
| 241 | .prcm_offs = OMAP3430ES2_SGX_MOD, | 267 | .prcm_offs = OMAP3430ES2_SGX_MOD, |
| 242 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), | 268 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
| 243 | .wkdep_srcs = gfx_sgx_wkdeps, | 269 | .wkdep_srcs = gfx_sgx_wkdeps, |
| 244 | .sleepdep_srcs = cam_gfx_sleepdeps, | 270 | .sleepdep_srcs = cam_gfx_sleepdeps, |
| 245 | /* XXX This is accurate for 3430 SGX, but what about GFX? */ | 271 | /* XXX This is accurate for 3430 SGX, but what about GFX? */ |
| 246 | .pwrsts = PWRSTS_OFF_RET_ON, | 272 | .pwrsts = PWRSTS_OFF_ON, |
| 247 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 273 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
| 248 | .banks = 1, | 274 | .banks = 1, |
| 249 | .pwrsts_mem_ret = { | 275 | .pwrsts_mem_ret = { |
| @@ -307,11 +333,12 @@ static struct powerdomain neon_pwrdm = { | |||
| 307 | static struct powerdomain usbhost_pwrdm = { | 333 | static struct powerdomain usbhost_pwrdm = { |
| 308 | .name = "usbhost_pwrdm", | 334 | .name = "usbhost_pwrdm", |
| 309 | .prcm_offs = OMAP3430ES2_USBHOST_MOD, | 335 | .prcm_offs = OMAP3430ES2_USBHOST_MOD, |
| 310 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES2), | 336 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), |
| 311 | .wkdep_srcs = per_usbhost_wkdeps, | 337 | .wkdep_srcs = per_usbhost_wkdeps, |
| 312 | .sleepdep_srcs = dss_per_usbhost_sleepdeps, | 338 | .sleepdep_srcs = dss_per_usbhost_sleepdeps, |
| 313 | .pwrsts = PWRSTS_OFF_RET_ON, | 339 | .pwrsts = PWRSTS_OFF_RET_ON, |
| 314 | .pwrsts_logic_ret = PWRDM_POWER_RET, | 340 | .pwrsts_logic_ret = PWRDM_POWER_RET, |
| 341 | .flags = PWRDM_HAS_HDWR_SAR, /* for USBHOST ctrlr only */ | ||
| 315 | .banks = 1, | 342 | .banks = 1, |
| 316 | .pwrsts_mem_ret = { | 343 | .pwrsts_mem_ret = { |
| 317 | [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ | 344 | [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ |
| @@ -321,6 +348,37 @@ static struct powerdomain usbhost_pwrdm = { | |||
| 321 | }, | 348 | }, |
| 322 | }; | 349 | }; |
| 323 | 350 | ||
| 351 | static struct powerdomain dpll1_pwrdm = { | ||
| 352 | .name = "dpll1_pwrdm", | ||
| 353 | .prcm_offs = MPU_MOD, | ||
| 354 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 355 | }; | ||
| 356 | |||
| 357 | static struct powerdomain dpll2_pwrdm = { | ||
| 358 | .name = "dpll2_pwrdm", | ||
| 359 | .prcm_offs = OMAP3430_IVA2_MOD, | ||
| 360 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 361 | }; | ||
| 362 | |||
| 363 | static struct powerdomain dpll3_pwrdm = { | ||
| 364 | .name = "dpll3_pwrdm", | ||
| 365 | .prcm_offs = PLL_MOD, | ||
| 366 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 367 | }; | ||
| 368 | |||
| 369 | static struct powerdomain dpll4_pwrdm = { | ||
| 370 | .name = "dpll4_pwrdm", | ||
| 371 | .prcm_offs = PLL_MOD, | ||
| 372 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), | ||
| 373 | }; | ||
| 374 | |||
| 375 | static struct powerdomain dpll5_pwrdm = { | ||
| 376 | .name = "dpll5_pwrdm", | ||
| 377 | .prcm_offs = PLL_MOD, | ||
| 378 | .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2), | ||
| 379 | }; | ||
| 380 | |||
| 381 | |||
| 324 | #endif /* CONFIG_ARCH_OMAP34XX */ | 382 | #endif /* CONFIG_ARCH_OMAP34XX */ |
| 325 | 383 | ||
| 326 | 384 | ||
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 4a32822ff3fc..812d50ee495d 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h | |||
| @@ -113,33 +113,58 @@ | |||
| 113 | #define OMAP2430_EN_USBHS (1 << 6) | 113 | #define OMAP2430_EN_USBHS (1 << 6) |
| 114 | 114 | ||
| 115 | /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ | 115 | /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ |
| 116 | #define OMAP2420_ST_MMC (1 << 26) | 116 | #define OMAP2420_ST_MMC_SHIFT 26 |
| 117 | #define OMAP24XX_ST_UART2 (1 << 22) | 117 | #define OMAP2420_ST_MMC_MASK (1 << 26) |
| 118 | #define OMAP24XX_ST_UART1 (1 << 21) | 118 | #define OMAP24XX_ST_UART2_SHIFT 22 |
| 119 | #define OMAP24XX_ST_MCSPI2 (1 << 18) | 119 | #define OMAP24XX_ST_UART2_MASK (1 << 22) |
| 120 | #define OMAP24XX_ST_MCSPI1 (1 << 17) | 120 | #define OMAP24XX_ST_UART1_SHIFT 21 |
| 121 | #define OMAP24XX_ST_GPT12 (1 << 14) | 121 | #define OMAP24XX_ST_UART1_MASK (1 << 21) |
| 122 | #define OMAP24XX_ST_GPT11 (1 << 13) | 122 | #define OMAP24XX_ST_MCSPI2_SHIFT 18 |
| 123 | #define OMAP24XX_ST_GPT10 (1 << 12) | 123 | #define OMAP24XX_ST_MCSPI2_MASK (1 << 18) |
| 124 | #define OMAP24XX_ST_GPT9 (1 << 11) | 124 | #define OMAP24XX_ST_MCSPI1_SHIFT 17 |
| 125 | #define OMAP24XX_ST_GPT8 (1 << 10) | 125 | #define OMAP24XX_ST_MCSPI1_MASK (1 << 17) |
| 126 | #define OMAP24XX_ST_GPT7 (1 << 9) | 126 | #define OMAP24XX_ST_GPT12_SHIFT 14 |
| 127 | #define OMAP24XX_ST_GPT6 (1 << 8) | 127 | #define OMAP24XX_ST_GPT12_MASK (1 << 14) |
| 128 | #define OMAP24XX_ST_GPT5 (1 << 7) | 128 | #define OMAP24XX_ST_GPT11_SHIFT 13 |
| 129 | #define OMAP24XX_ST_GPT4 (1 << 6) | 129 | #define OMAP24XX_ST_GPT11_MASK (1 << 13) |
| 130 | #define OMAP24XX_ST_GPT3 (1 << 5) | 130 | #define OMAP24XX_ST_GPT10_SHIFT 12 |
| 131 | #define OMAP24XX_ST_GPT2 (1 << 4) | 131 | #define OMAP24XX_ST_GPT10_MASK (1 << 12) |
| 132 | #define OMAP2420_ST_VLYNQ (1 << 3) | 132 | #define OMAP24XX_ST_GPT9_SHIFT 11 |
| 133 | #define OMAP24XX_ST_GPT9_MASK (1 << 11) | ||
| 134 | #define OMAP24XX_ST_GPT8_SHIFT 10 | ||
| 135 | #define OMAP24XX_ST_GPT8_MASK (1 << 10) | ||
| 136 | #define OMAP24XX_ST_GPT7_SHIFT 9 | ||
| 137 | #define OMAP24XX_ST_GPT7_MASK (1 << 9) | ||
| 138 | #define OMAP24XX_ST_GPT6_SHIFT 8 | ||
| 139 | #define OMAP24XX_ST_GPT6_MASK (1 << 8) | ||
| 140 | #define OMAP24XX_ST_GPT5_SHIFT 7 | ||
| 141 | #define OMAP24XX_ST_GPT5_MASK (1 << 7) | ||
| 142 | #define OMAP24XX_ST_GPT4_SHIFT 6 | ||
| 143 | #define OMAP24XX_ST_GPT4_MASK (1 << 6) | ||
| 144 | #define OMAP24XX_ST_GPT3_SHIFT 5 | ||
| 145 | #define OMAP24XX_ST_GPT3_MASK (1 << 5) | ||
| 146 | #define OMAP24XX_ST_GPT2_SHIFT 4 | ||
| 147 | #define OMAP24XX_ST_GPT2_MASK (1 << 4) | ||
| 148 | #define OMAP2420_ST_VLYNQ_SHIFT 3 | ||
| 149 | #define OMAP2420_ST_VLYNQ_MASK (1 << 3) | ||
| 133 | 150 | ||
| 134 | /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ | 151 | /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ |
| 135 | #define OMAP2430_ST_MDM_INTC (1 << 11) | 152 | #define OMAP2430_ST_MDM_INTC_SHIFT 11 |
| 136 | #define OMAP2430_ST_GPIO5 (1 << 10) | 153 | #define OMAP2430_ST_MDM_INTC_MASK (1 << 11) |
| 137 | #define OMAP2430_ST_MCSPI3 (1 << 9) | 154 | #define OMAP2430_ST_GPIO5_SHIFT 10 |
| 138 | #define OMAP2430_ST_MMCHS2 (1 << 8) | 155 | #define OMAP2430_ST_GPIO5_MASK (1 << 10) |
| 139 | #define OMAP2430_ST_MMCHS1 (1 << 7) | 156 | #define OMAP2430_ST_MCSPI3_SHIFT 9 |
| 140 | #define OMAP2430_ST_USBHS (1 << 6) | 157 | #define OMAP2430_ST_MCSPI3_MASK (1 << 9) |
| 141 | #define OMAP24XX_ST_UART3 (1 << 2) | 158 | #define OMAP2430_ST_MMCHS2_SHIFT 8 |
| 142 | #define OMAP24XX_ST_USB (1 << 0) | 159 | #define OMAP2430_ST_MMCHS2_MASK (1 << 8) |
| 160 | #define OMAP2430_ST_MMCHS1_SHIFT 7 | ||
| 161 | #define OMAP2430_ST_MMCHS1_MASK (1 << 7) | ||
| 162 | #define OMAP2430_ST_USBHS_SHIFT 6 | ||
| 163 | #define OMAP2430_ST_USBHS_MASK (1 << 6) | ||
| 164 | #define OMAP24XX_ST_UART3_SHIFT 2 | ||
| 165 | #define OMAP24XX_ST_UART3_MASK (1 << 2) | ||
| 166 | #define OMAP24XX_ST_USB_SHIFT 0 | ||
| 167 | #define OMAP24XX_ST_USB_MASK (1 << 0) | ||
| 143 | 168 | ||
| 144 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | 169 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ |
| 145 | #define OMAP24XX_EN_GPIOS_SHIFT 2 | 170 | #define OMAP24XX_EN_GPIOS_SHIFT 2 |
| @@ -148,11 +173,13 @@ | |||
| 148 | #define OMAP24XX_EN_GPT1 (1 << 0) | 173 | #define OMAP24XX_EN_GPT1 (1 << 0) |
| 149 | 174 | ||
| 150 | /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ | 175 | /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ |
| 151 | #define OMAP24XX_ST_GPIOS (1 << 2) | 176 | #define OMAP24XX_ST_GPIOS_SHIFT (1 << 2) |
| 152 | #define OMAP24XX_ST_GPT1 (1 << 0) | 177 | #define OMAP24XX_ST_GPIOS_MASK 2 |
| 178 | #define OMAP24XX_ST_GPT1_SHIFT (1 << 0) | ||
| 179 | #define OMAP24XX_ST_GPT1_MASK 0 | ||
| 153 | 180 | ||
| 154 | /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ | 181 | /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ |
| 155 | #define OMAP2430_ST_MDM (1 << 0) | 182 | #define OMAP2430_ST_MDM_SHIFT (1 << 0) |
| 156 | 183 | ||
| 157 | 184 | ||
| 158 | /* 3430 register bits shared between CM & PRM registers */ | 185 | /* 3430 register bits shared between CM & PRM registers */ |
| @@ -205,24 +232,46 @@ | |||
| 205 | #define OMAP3430_EN_HSOTGUSB_SHIFT 4 | 232 | #define OMAP3430_EN_HSOTGUSB_SHIFT 4 |
| 206 | 233 | ||
| 207 | /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ | 234 | /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ |
| 208 | #define OMAP3430_ST_MMC2 (1 << 25) | 235 | #define OMAP3430_ST_MMC2_SHIFT 25 |
| 209 | #define OMAP3430_ST_MMC1 (1 << 24) | 236 | #define OMAP3430_ST_MMC2_MASK (1 << 25) |
| 210 | #define OMAP3430_ST_MCSPI4 (1 << 21) | 237 | #define OMAP3430_ST_MMC1_SHIFT 24 |
| 211 | #define OMAP3430_ST_MCSPI3 (1 << 20) | 238 | #define OMAP3430_ST_MMC1_MASK (1 << 24) |
| 212 | #define OMAP3430_ST_MCSPI2 (1 << 19) | 239 | #define OMAP3430_ST_MCSPI4_SHIFT 21 |
| 213 | #define OMAP3430_ST_MCSPI1 (1 << 18) | 240 | #define OMAP3430_ST_MCSPI4_MASK (1 << 21) |
| 214 | #define OMAP3430_ST_I2C3 (1 << 17) | 241 | #define OMAP3430_ST_MCSPI3_SHIFT 20 |
| 215 | #define OMAP3430_ST_I2C2 (1 << 16) | 242 | #define OMAP3430_ST_MCSPI3_MASK (1 << 20) |
| 216 | #define OMAP3430_ST_I2C1 (1 << 15) | 243 | #define OMAP3430_ST_MCSPI2_SHIFT 19 |
| 217 | #define OMAP3430_ST_UART2 (1 << 14) | 244 | #define OMAP3430_ST_MCSPI2_MASK (1 << 19) |
| 218 | #define OMAP3430_ST_UART1 (1 << 13) | 245 | #define OMAP3430_ST_MCSPI1_SHIFT 18 |
| 219 | #define OMAP3430_ST_GPT11 (1 << 12) | 246 | #define OMAP3430_ST_MCSPI1_MASK (1 << 18) |
| 220 | #define OMAP3430_ST_GPT10 (1 << 11) | 247 | #define OMAP3430_ST_I2C3_SHIFT 17 |
| 221 | #define OMAP3430_ST_MCBSP5 (1 << 10) | 248 | #define OMAP3430_ST_I2C3_MASK (1 << 17) |
| 222 | #define OMAP3430_ST_MCBSP1 (1 << 9) | 249 | #define OMAP3430_ST_I2C2_SHIFT 16 |
| 223 | #define OMAP3430_ST_FSHOSTUSB (1 << 5) | 250 | #define OMAP3430_ST_I2C2_MASK (1 << 16) |
| 224 | #define OMAP3430_ST_HSOTGUSB (1 << 4) | 251 | #define OMAP3430_ST_I2C1_SHIFT 15 |
| 225 | #define OMAP3430_ST_D2D (1 << 3) | 252 | #define OMAP3430_ST_I2C1_MASK (1 << 15) |
| 253 | #define OMAP3430_ST_UART2_SHIFT 14 | ||
| 254 | #define OMAP3430_ST_UART2_MASK (1 << 14) | ||
| 255 | #define OMAP3430_ST_UART1_SHIFT 13 | ||
| 256 | #define OMAP3430_ST_UART1_MASK (1 << 13) | ||
| 257 | #define OMAP3430_ST_GPT11_SHIFT 12 | ||
| 258 | #define OMAP3430_ST_GPT11_MASK (1 << 12) | ||
| 259 | #define OMAP3430_ST_GPT10_SHIFT 11 | ||
| 260 | #define OMAP3430_ST_GPT10_MASK (1 << 11) | ||
| 261 | #define OMAP3430_ST_MCBSP5_SHIFT 10 | ||
| 262 | #define OMAP3430_ST_MCBSP5_MASK (1 << 10) | ||
| 263 | #define OMAP3430_ST_MCBSP1_SHIFT 9 | ||
| 264 | #define OMAP3430_ST_MCBSP1_MASK (1 << 9) | ||
| 265 | #define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5 | ||
| 266 | #define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5) | ||
| 267 | #define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4 | ||
| 268 | #define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4) | ||
| 269 | #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5 | ||
| 270 | #define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5) | ||
| 271 | #define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4 | ||
| 272 | #define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4) | ||
| 273 | #define OMAP3430_ST_D2D_SHIFT 3 | ||
| 274 | #define OMAP3430_ST_D2D_MASK (1 << 3) | ||
| 226 | 275 | ||
| 227 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | 276 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ |
| 228 | #define OMAP3430_EN_GPIO1 (1 << 3) | 277 | #define OMAP3430_EN_GPIO1 (1 << 3) |
| @@ -241,11 +290,16 @@ | |||
| 241 | #define OMAP3430_EN_GPT12_SHIFT 1 | 290 | #define OMAP3430_EN_GPT12_SHIFT 1 |
| 242 | 291 | ||
| 243 | /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ | 292 | /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ |
| 244 | #define OMAP3430_ST_SR2 (1 << 7) | 293 | #define OMAP3430_ST_SR2_SHIFT 7 |
| 245 | #define OMAP3430_ST_SR1 (1 << 6) | 294 | #define OMAP3430_ST_SR2_MASK (1 << 7) |
| 246 | #define OMAP3430_ST_GPIO1 (1 << 3) | 295 | #define OMAP3430_ST_SR1_SHIFT 6 |
| 247 | #define OMAP3430_ST_GPT12 (1 << 1) | 296 | #define OMAP3430_ST_SR1_MASK (1 << 6) |
| 248 | #define OMAP3430_ST_GPT1 (1 << 0) | 297 | #define OMAP3430_ST_GPIO1_SHIFT 3 |
| 298 | #define OMAP3430_ST_GPIO1_MASK (1 << 3) | ||
| 299 | #define OMAP3430_ST_GPT12_SHIFT 1 | ||
| 300 | #define OMAP3430_ST_GPT12_MASK (1 << 1) | ||
| 301 | #define OMAP3430_ST_GPT1_SHIFT 0 | ||
| 302 | #define OMAP3430_ST_GPT1_MASK (1 << 0) | ||
| 249 | 303 | ||
| 250 | /* | 304 | /* |
| 251 | * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, | 305 | * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, |
| @@ -296,20 +350,34 @@ | |||
| 296 | #define OMAP3430_EN_MCBSP2_SHIFT 0 | 350 | #define OMAP3430_EN_MCBSP2_SHIFT 0 |
| 297 | 351 | ||
| 298 | /* CM_IDLEST_PER, PM_WKST_PER shared bits */ | 352 | /* CM_IDLEST_PER, PM_WKST_PER shared bits */ |
| 299 | #define OMAP3430_ST_GPIO6 (1 << 17) | 353 | #define OMAP3430_ST_GPIO6_SHIFT 17 |
| 300 | #define OMAP3430_ST_GPIO5 (1 << 16) | 354 | #define OMAP3430_ST_GPIO6_MASK (1 << 17) |
| 301 | #define OMAP3430_ST_GPIO4 (1 << 15) | 355 | #define OMAP3430_ST_GPIO5_SHIFT 16 |
| 302 | #define OMAP3430_ST_GPIO3 (1 << 14) | 356 | #define OMAP3430_ST_GPIO5_MASK (1 << 16) |
| 303 | #define OMAP3430_ST_GPIO2 (1 << 13) | 357 | #define OMAP3430_ST_GPIO4_SHIFT 15 |
| 304 | #define OMAP3430_ST_UART3 (1 << 11) | 358 | #define OMAP3430_ST_GPIO4_MASK (1 << 15) |
| 305 | #define OMAP3430_ST_GPT9 (1 << 10) | 359 | #define OMAP3430_ST_GPIO3_SHIFT 14 |
| 306 | #define OMAP3430_ST_GPT8 (1 << 9) | 360 | #define OMAP3430_ST_GPIO3_MASK (1 << 14) |
| 307 | #define OMAP3430_ST_GPT7 (1 << 8) | 361 | #define OMAP3430_ST_GPIO2_SHIFT 13 |
| 308 | #define OMAP3430_ST_GPT6 (1 << 7) | 362 | #define OMAP3430_ST_GPIO2_MASK (1 << 13) |
| 309 | #define OMAP3430_ST_GPT5 (1 << 6) | 363 | #define OMAP3430_ST_UART3_SHIFT 11 |
| 310 | #define OMAP3430_ST_GPT4 (1 << 5) | 364 | #define OMAP3430_ST_UART3_MASK (1 << 11) |
| 311 | #define OMAP3430_ST_GPT3 (1 << 4) | 365 | #define OMAP3430_ST_GPT9_SHIFT 10 |
| 312 | #define OMAP3430_ST_GPT2 (1 << 3) | 366 | #define OMAP3430_ST_GPT9_MASK (1 << 10) |
| 367 | #define OMAP3430_ST_GPT8_SHIFT 9 | ||
| 368 | #define OMAP3430_ST_GPT8_MASK (1 << 9) | ||
| 369 | #define OMAP3430_ST_GPT7_SHIFT 8 | ||
| 370 | #define OMAP3430_ST_GPT7_MASK (1 << 8) | ||
| 371 | #define OMAP3430_ST_GPT6_SHIFT 7 | ||
| 372 | #define OMAP3430_ST_GPT6_MASK (1 << 7) | ||
| 373 | #define OMAP3430_ST_GPT5_SHIFT 6 | ||
| 374 | #define OMAP3430_ST_GPT5_MASK (1 << 6) | ||
| 375 | #define OMAP3430_ST_GPT4_SHIFT 5 | ||
| 376 | #define OMAP3430_ST_GPT4_MASK (1 << 5) | ||
| 377 | #define OMAP3430_ST_GPT3_SHIFT 4 | ||
| 378 | #define OMAP3430_ST_GPT3_MASK (1 << 4) | ||
| 379 | #define OMAP3430_ST_GPT2_SHIFT 3 | ||
| 380 | #define OMAP3430_ST_GPT2_MASK (1 << 3) | ||
| 313 | 381 | ||
| 314 | /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ | 382 | /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ |
| 315 | #define OMAP3430_EN_CORE_SHIFT 0 | 383 | #define OMAP3430_EN_CORE_SHIFT 0 |
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 5b5ecfe6c999..c6a7940f4287 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h | |||
| @@ -366,6 +366,7 @@ | |||
| 366 | 366 | ||
| 367 | /* PM_WKEN_WKUP specific bits */ | 367 | /* PM_WKEN_WKUP specific bits */ |
| 368 | #define OMAP3430_EN_IO (1 << 8) | 368 | #define OMAP3430_EN_IO (1 << 8) |
| 369 | #define OMAP3430_EN_GPIO1 (1 << 3) | ||
| 369 | 370 | ||
| 370 | /* PM_MPUGRPSEL_WKUP specific bits */ | 371 | /* PM_MPUGRPSEL_WKUP specific bits */ |
| 371 | 372 | ||
| @@ -452,6 +453,14 @@ | |||
| 452 | #define OMAP3430_CMDRA0_MASK (0xff << 0) | 453 | #define OMAP3430_CMDRA0_MASK (0xff << 0) |
| 453 | 454 | ||
| 454 | /* PRM_VC_CMD_VAL_0 specific bits */ | 455 | /* PRM_VC_CMD_VAL_0 specific bits */ |
| 456 | #define OMAP3430_VC_CMD_ON_SHIFT 24 | ||
| 457 | #define OMAP3430_VC_CMD_ON_MASK (0xFF << 24) | ||
| 458 | #define OMAP3430_VC_CMD_ONLP_SHIFT 16 | ||
| 459 | #define OMAP3430_VC_CMD_ONLP_MASK (0xFF << 16) | ||
| 460 | #define OMAP3430_VC_CMD_RET_SHIFT 8 | ||
| 461 | #define OMAP3430_VC_CMD_RET_MASK (0xFF << 8) | ||
| 462 | #define OMAP3430_VC_CMD_OFF_SHIFT 0 | ||
| 463 | #define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0) | ||
| 455 | 464 | ||
| 456 | /* PRM_VC_CMD_VAL_1 specific bits */ | 465 | /* PRM_VC_CMD_VAL_1 specific bits */ |
| 457 | 466 | ||
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index e4dc4b17881d..826d326b8062 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h | |||
| @@ -141,6 +141,19 @@ | |||
| 141 | #define PM_PWSTCTRL 0x00e0 | 141 | #define PM_PWSTCTRL 0x00e0 |
| 142 | #define PM_PWSTST 0x00e4 | 142 | #define PM_PWSTST 0x00e4 |
| 143 | 143 | ||
| 144 | /* Omap2 specific registers */ | ||
| 145 | #define OMAP24XX_PM_WKEN2 0x00a4 | ||
| 146 | #define OMAP24XX_PM_WKST2 0x00b4 | ||
| 147 | |||
| 148 | #define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ | ||
| 149 | #define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ | ||
| 150 | #define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 | ||
| 151 | #define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc | ||
| 152 | |||
| 153 | /* Omap3 specific registers */ | ||
| 154 | #define OMAP3430ES2_PM_WKEN3 0x00f0 | ||
| 155 | #define OMAP3430ES2_PM_WKST3 0x00b8 | ||
| 156 | |||
| 144 | #define OMAP3430_PM_MPUGRPSEL 0x00a4 | 157 | #define OMAP3430_PM_MPUGRPSEL 0x00a4 |
| 145 | #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL | 158 | #define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL |
| 146 | 159 | ||
| @@ -153,16 +166,6 @@ | |||
| 153 | #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc | 166 | #define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc |
| 154 | 167 | ||
| 155 | 168 | ||
| 156 | /* Architecture-specific registers */ | ||
| 157 | |||
| 158 | #define OMAP24XX_PM_WKEN2 0x00a4 | ||
| 159 | #define OMAP24XX_PM_WKST2 0x00b4 | ||
| 160 | |||
| 161 | #define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ | ||
| 162 | #define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ | ||
| 163 | #define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 | ||
| 164 | #define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc | ||
| 165 | |||
| 166 | #ifndef __ASSEMBLER__ | 169 | #ifndef __ASSEMBLER__ |
| 167 | 170 | ||
| 168 | /* Power/reset management domain register get/set */ | 171 | /* Power/reset management domain register get/set */ |
| @@ -228,7 +231,6 @@ static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) | |||
| 228 | #define OMAP_RSTTIME1_SHIFT 0 | 231 | #define OMAP_RSTTIME1_SHIFT 0 |
| 229 | #define OMAP_RSTTIME1_MASK (0xff << 0) | 232 | #define OMAP_RSTTIME1_MASK (0xff << 0) |
| 230 | 233 | ||
| 231 | |||
| 232 | /* PRM_RSTCTRL */ | 234 | /* PRM_RSTCTRL */ |
| 233 | /* Named RM_RSTCTRL_WKUP on the 24xx */ | 235 | /* Named RM_RSTCTRL_WKUP on the 24xx */ |
| 234 | /* 2420 calls RST_DPLL3 'RST_DPLL' */ | 236 | /* 2420 calls RST_DPLL3 'RST_DPLL' */ |
diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c new file mode 100644 index 000000000000..2a30060cb4b7 --- /dev/null +++ b/arch/arm/mach-omap2/sdrc.c | |||
| @@ -0,0 +1,93 @@ | |||
| 1 | /* | ||
| 2 | * SMS/SDRC (SDRAM controller) common code for OMAP2/3 | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005, 2008 Texas Instruments Inc. | ||
| 5 | * Copyright (C) 2005, 2008 Nokia Corporation | ||
| 6 | * | ||
| 7 | * Tony Lindgren <tony@atomide.com> | ||
| 8 | * Paul Walmsley | ||
| 9 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | #undef DEBUG | ||
| 16 | |||
| 17 | #include <linux/module.h> | ||
| 18 | #include <linux/kernel.h> | ||
| 19 | #include <linux/device.h> | ||
| 20 | #include <linux/list.h> | ||
| 21 | #include <linux/errno.h> | ||
| 22 | #include <linux/delay.h> | ||
| 23 | #include <linux/clk.h> | ||
| 24 | #include <linux/io.h> | ||
| 25 | |||
| 26 | #include <mach/common.h> | ||
| 27 | #include <mach/clock.h> | ||
| 28 | #include <mach/sram.h> | ||
| 29 | |||
| 30 | #include "prm.h" | ||
| 31 | |||
| 32 | #include <mach/sdrc.h> | ||
| 33 | #include "sdrc.h" | ||
| 34 | |||
| 35 | static struct omap_sdrc_params *sdrc_init_params; | ||
| 36 | |||
| 37 | void __iomem *omap2_sdrc_base; | ||
| 38 | void __iomem *omap2_sms_base; | ||
| 39 | |||
| 40 | |||
| 41 | /** | ||
| 42 | * omap2_sdrc_get_params - return SDRC register values for a given clock rate | ||
| 43 | * @r: SDRC clock rate (in Hz) | ||
| 44 | * | ||
| 45 | * Return pre-calculated values for the SDRC_ACTIM_CTRLA, | ||
| 46 | * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL, and SDRC_MR registers, for a given | ||
| 47 | * SDRC clock rate 'r'. These parameters control various timing | ||
| 48 | * delays in the SDRAM controller that are expressed in terms of the | ||
| 49 | * number of SDRC clock cycles to wait; hence the clock rate | ||
| 50 | * dependency. Note that sdrc_init_params must be sorted rate | ||
| 51 | * descending. Also assumes that both chip-selects use the same | ||
| 52 | * timing parameters. Returns a struct omap_sdrc_params * upon | ||
| 53 | * success, or NULL upon failure. | ||
| 54 | */ | ||
| 55 | struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r) | ||
| 56 | { | ||
| 57 | struct omap_sdrc_params *sp; | ||
| 58 | |||
| 59 | sp = sdrc_init_params; | ||
| 60 | |||
| 61 | while (sp->rate != r) | ||
| 62 | sp++; | ||
| 63 | |||
| 64 | if (!sp->rate) | ||
| 65 | return NULL; | ||
| 66 | |||
| 67 | return sp; | ||
| 68 | } | ||
| 69 | |||
| 70 | |||
| 71 | void __init omap2_set_globals_sdrc(struct omap_globals *omap2_globals) | ||
| 72 | { | ||
| 73 | omap2_sdrc_base = omap2_globals->sdrc; | ||
| 74 | omap2_sms_base = omap2_globals->sms; | ||
| 75 | } | ||
| 76 | |||
| 77 | /* turn on smart idle modes for SDRAM scheduler and controller */ | ||
| 78 | void __init omap2_sdrc_init(struct omap_sdrc_params *sp) | ||
| 79 | { | ||
| 80 | u32 l; | ||
| 81 | |||
| 82 | l = sms_read_reg(SMS_SYSCONFIG); | ||
| 83 | l &= ~(0x3 << 3); | ||
| 84 | l |= (0x2 << 3); | ||
| 85 | sms_write_reg(l, SMS_SYSCONFIG); | ||
| 86 | |||
| 87 | l = sdrc_read_reg(SDRC_SYSCONFIG); | ||
| 88 | l &= ~(0x3 << 3); | ||
| 89 | l |= (0x2 << 3); | ||
| 90 | sdrc_write_reg(l, SDRC_SYSCONFIG); | ||
| 91 | |||
| 92 | sdrc_init_params = sp; | ||
| 93 | } | ||
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/sdrc2xxx.c index 882c70224292..0afdad5ae9fb 100644 --- a/arch/arm/mach-omap2/memory.c +++ b/arch/arm/mach-omap2/sdrc2xxx.c | |||
| @@ -1,13 +1,14 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-omap2/memory.c | 2 | * linux/arch/arm/mach-omap2/sdrc2xxx.c |
| 3 | * | 3 | * |
| 4 | * Memory timing related functions for OMAP24XX | 4 | * SDRAM timing related functions for OMAP2xxx |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2005 Texas Instruments Inc. | 6 | * Copyright (C) 2005, 2008 Texas Instruments Inc. |
| 7 | * Richard Woodruff <r-woodruff2@ti.com> | 7 | * Copyright (C) 2005, 2008 Nokia Corporation |
| 8 | * | 8 | * |
| 9 | * Copyright (C) 2005 Nokia Corporation | ||
| 10 | * Tony Lindgren <tony@atomide.com> | 9 | * Tony Lindgren <tony@atomide.com> |
| 10 | * Paul Walmsley | ||
| 11 | * Richard Woodruff <r-woodruff2@ti.com> | ||
| 11 | * | 12 | * |
| 12 | * This program is free software; you can redistribute it and/or modify | 13 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License version 2 as | 14 | * it under the terms of the GNU General Public License version 2 as |
| @@ -28,27 +29,31 @@ | |||
| 28 | #include <mach/sram.h> | 29 | #include <mach/sram.h> |
| 29 | 30 | ||
| 30 | #include "prm.h" | 31 | #include "prm.h" |
| 31 | 32 | #include "clock.h" | |
| 32 | #include "memory.h" | 33 | #include <mach/sdrc.h> |
| 33 | #include "sdrc.h" | 34 | #include "sdrc.h" |
| 34 | 35 | ||
| 35 | void __iomem *omap2_sdrc_base; | 36 | /* Memory timing, DLL mode flags */ |
| 36 | void __iomem *omap2_sms_base; | 37 | #define M_DDR 1 |
| 38 | #define M_LOCK_CTRL (1 << 2) | ||
| 39 | #define M_UNLOCK 0 | ||
| 40 | #define M_LOCK 1 | ||
| 41 | |||
| 37 | 42 | ||
| 38 | static struct memory_timings mem_timings; | 43 | static struct memory_timings mem_timings; |
| 39 | static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2; | 44 | static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2; |
| 40 | 45 | ||
| 41 | u32 omap2_memory_get_slow_dll_ctrl(void) | 46 | static u32 omap2xxx_sdrc_get_slow_dll_ctrl(void) |
| 42 | { | 47 | { |
| 43 | return mem_timings.slow_dll_ctrl; | 48 | return mem_timings.slow_dll_ctrl; |
| 44 | } | 49 | } |
| 45 | 50 | ||
| 46 | u32 omap2_memory_get_fast_dll_ctrl(void) | 51 | static u32 omap2xxx_sdrc_get_fast_dll_ctrl(void) |
| 47 | { | 52 | { |
| 48 | return mem_timings.fast_dll_ctrl; | 53 | return mem_timings.fast_dll_ctrl; |
| 49 | } | 54 | } |
| 50 | 55 | ||
| 51 | u32 omap2_memory_get_type(void) | 56 | static u32 omap2xxx_sdrc_get_type(void) |
| 52 | { | 57 | { |
| 53 | return mem_timings.m_type; | 58 | return mem_timings.m_type; |
| 54 | } | 59 | } |
| @@ -57,7 +62,7 @@ u32 omap2_memory_get_type(void) | |||
| 57 | * Check the DLL lock state, and return tue if running in unlock mode. | 62 | * Check the DLL lock state, and return tue if running in unlock mode. |
| 58 | * This is needed to compensate for the shifted DLL value in unlock mode. | 63 | * This is needed to compensate for the shifted DLL value in unlock mode. |
| 59 | */ | 64 | */ |
| 60 | u32 omap2_dll_force_needed(void) | 65 | u32 omap2xxx_sdrc_dll_is_unlocked(void) |
| 61 | { | 66 | { |
| 62 | /* dlla and dllb are a set */ | 67 | /* dlla and dllb are a set */ |
| 63 | u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL); | 68 | u32 dll_state = sdrc_read_reg(SDRC_DLLA_CTRL); |
| @@ -72,8 +77,10 @@ u32 omap2_dll_force_needed(void) | |||
| 72 | * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC. | 77 | * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC. |
| 73 | * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or | 78 | * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or |
| 74 | * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2) | 79 | * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2) |
| 80 | * | ||
| 81 | * Used by the clock framework during CORE DPLL changes | ||
| 75 | */ | 82 | */ |
| 76 | u32 omap2_reprogram_sdrc(u32 level, u32 force) | 83 | u32 omap2xxx_sdrc_reprogram(u32 level, u32 force) |
| 77 | { | 84 | { |
| 78 | u32 dll_ctrl, m_type; | 85 | u32 dll_ctrl, m_type; |
| 79 | u32 prev = curr_perf_level; | 86 | u32 prev = curr_perf_level; |
| @@ -82,15 +89,14 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force) | |||
| 82 | if ((curr_perf_level == level) && !force) | 89 | if ((curr_perf_level == level) && !force) |
| 83 | return prev; | 90 | return prev; |
| 84 | 91 | ||
| 85 | if (level == CORE_CLK_SRC_DPLL) { | 92 | if (level == CORE_CLK_SRC_DPLL) |
| 86 | dll_ctrl = omap2_memory_get_slow_dll_ctrl(); | 93 | dll_ctrl = omap2xxx_sdrc_get_slow_dll_ctrl(); |
| 87 | } else if (level == CORE_CLK_SRC_DPLL_X2) { | 94 | else if (level == CORE_CLK_SRC_DPLL_X2) |
| 88 | dll_ctrl = omap2_memory_get_fast_dll_ctrl(); | 95 | dll_ctrl = omap2xxx_sdrc_get_fast_dll_ctrl(); |
| 89 | } else { | 96 | else |
| 90 | return prev; | 97 | return prev; |
| 91 | } | ||
| 92 | 98 | ||
| 93 | m_type = omap2_memory_get_type(); | 99 | m_type = omap2xxx_sdrc_get_type(); |
| 94 | 100 | ||
| 95 | local_irq_save(flags); | 101 | local_irq_save(flags); |
| 96 | __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); | 102 | __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP); |
| @@ -101,23 +107,14 @@ u32 omap2_reprogram_sdrc(u32 level, u32 force) | |||
| 101 | return prev; | 107 | return prev; |
| 102 | } | 108 | } |
| 103 | 109 | ||
| 104 | #if !defined(CONFIG_ARCH_OMAP2) | 110 | /* Used by the clock framework during CORE DPLL changes */ |
| 105 | void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, | 111 | void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode) |
| 106 | u32 base_cs, u32 force_unlock) | ||
| 107 | { | ||
| 108 | } | ||
| 109 | void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, | ||
| 110 | u32 mem_type) | ||
| 111 | { | ||
| 112 | } | ||
| 113 | #endif | ||
| 114 | |||
| 115 | void omap2_init_memory_params(u32 force_lock_to_unlock_mode) | ||
| 116 | { | 112 | { |
| 117 | unsigned long dll_cnt; | 113 | unsigned long dll_cnt; |
| 118 | u32 fast_dll = 0; | 114 | u32 fast_dll = 0; |
| 119 | 115 | ||
| 120 | mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */ | 116 | /* DDR = 1, SDR = 0 */ |
| 117 | mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); | ||
| 121 | 118 | ||
| 122 | /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. | 119 | /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others. |
| 123 | * In the case of 2422, its ok to use CS1 instead of CS0. | 120 | * In the case of 2422, its ok to use CS1 instead of CS0. |
| @@ -164,28 +161,3 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode) | |||
| 164 | /* 90 degree phase for anything below 133Mhz + disable DLL filter */ | 161 | /* 90 degree phase for anything below 133Mhz + disable DLL filter */ |
| 165 | mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); | 162 | mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); |
| 166 | } | 163 | } |
| 167 | |||
| 168 | void __init omap2_set_globals_memory(struct omap_globals *omap2_globals) | ||
| 169 | { | ||
| 170 | omap2_sdrc_base = omap2_globals->sdrc; | ||
| 171 | omap2_sms_base = omap2_globals->sms; | ||
| 172 | } | ||
| 173 | |||
| 174 | /* turn on smart idle modes for SDRAM scheduler and controller */ | ||
| 175 | void __init omap2_init_memory(void) | ||
| 176 | { | ||
| 177 | u32 l; | ||
| 178 | |||
| 179 | if (!cpu_is_omap2420()) | ||
| 180 | return; | ||
| 181 | |||
| 182 | l = sms_read_reg(SMS_SYSCONFIG); | ||
| 183 | l &= ~(0x3 << 3); | ||
| 184 | l |= (0x2 << 3); | ||
| 185 | sms_write_reg(l, SMS_SYSCONFIG); | ||
| 186 | |||
| 187 | l = sdrc_read_reg(SDRC_SYSCONFIG); | ||
| 188 | l &= ~(0x3 << 3); | ||
| 189 | l |= (0x2 << 3); | ||
| 190 | sdrc_write_reg(l, SDRC_SYSCONFIG); | ||
| 191 | } | ||
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c new file mode 100644 index 000000000000..fc74e913c415 --- /dev/null +++ b/arch/arm/mach-omap2/usb-musb.c | |||
| @@ -0,0 +1,187 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-omap2/usb-musb.c | ||
| 3 | * | ||
| 4 | * This file will contain the board specific details for the | ||
| 5 | * MENTOR USB OTG controller on OMAP3430 | ||
| 6 | * | ||
| 7 | * Copyright (C) 2007-2008 Texas Instruments | ||
| 8 | * Copyright (C) 2008 Nokia Corporation | ||
| 9 | * Author: Vikram Pandita | ||
| 10 | * | ||
| 11 | * Generalization by: | ||
| 12 | * Felipe Balbi <felipe.balbi@nokia.com> | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License version 2 as | ||
| 16 | * published by the Free Software Foundation. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/types.h> | ||
| 20 | #include <linux/errno.h> | ||
| 21 | #include <linux/delay.h> | ||
| 22 | #include <linux/platform_device.h> | ||
| 23 | #include <linux/clk.h> | ||
| 24 | #include <linux/dma-mapping.h> | ||
| 25 | #include <linux/io.h> | ||
| 26 | |||
| 27 | #include <linux/usb/musb.h> | ||
| 28 | |||
| 29 | #include <mach/hardware.h> | ||
| 30 | #include <mach/irqs.h> | ||
| 31 | #include <mach/pm.h> | ||
| 32 | #include <mach/mux.h> | ||
| 33 | #include <mach/usb.h> | ||
| 34 | |||
| 35 | static struct resource musb_resources[] = { | ||
| 36 | [0] = { /* start and end set dynamically */ | ||
| 37 | .flags = IORESOURCE_MEM, | ||
| 38 | }, | ||
| 39 | [1] = { /* general IRQ */ | ||
| 40 | .start = INT_243X_HS_USB_MC, | ||
| 41 | .flags = IORESOURCE_IRQ, | ||
| 42 | }, | ||
| 43 | [2] = { /* DMA IRQ */ | ||
| 44 | .start = INT_243X_HS_USB_DMA, | ||
| 45 | .flags = IORESOURCE_IRQ, | ||
| 46 | }, | ||
| 47 | }; | ||
| 48 | |||
| 49 | static int clk_on; | ||
| 50 | |||
| 51 | static int musb_set_clock(struct clk *clk, int state) | ||
| 52 | { | ||
| 53 | if (state) { | ||
| 54 | if (clk_on > 0) | ||
| 55 | return -ENODEV; | ||
| 56 | |||
| 57 | clk_enable(clk); | ||
| 58 | clk_on = 1; | ||
| 59 | } else { | ||
| 60 | if (clk_on == 0) | ||
| 61 | return -ENODEV; | ||
| 62 | |||
| 63 | clk_disable(clk); | ||
| 64 | clk_on = 0; | ||
| 65 | } | ||
| 66 | |||
| 67 | return 0; | ||
| 68 | } | ||
| 69 | |||
| 70 | static struct musb_hdrc_eps_bits musb_eps[] = { | ||
| 71 | { "ep1_tx", 10, }, | ||
| 72 | { "ep1_rx", 10, }, | ||
| 73 | { "ep2_tx", 9, }, | ||
| 74 | { "ep2_rx", 9, }, | ||
| 75 | { "ep3_tx", 3, }, | ||
| 76 | { "ep3_rx", 3, }, | ||
| 77 | { "ep4_tx", 3, }, | ||
| 78 | { "ep4_rx", 3, }, | ||
| 79 | { "ep5_tx", 3, }, | ||
| 80 | { "ep5_rx", 3, }, | ||
| 81 | { "ep6_tx", 3, }, | ||
| 82 | { "ep6_rx", 3, }, | ||
| 83 | { "ep7_tx", 3, }, | ||
| 84 | { "ep7_rx", 3, }, | ||
| 85 | { "ep8_tx", 2, }, | ||
| 86 | { "ep8_rx", 2, }, | ||
| 87 | { "ep9_tx", 2, }, | ||
| 88 | { "ep9_rx", 2, }, | ||
| 89 | { "ep10_tx", 2, }, | ||
| 90 | { "ep10_rx", 2, }, | ||
| 91 | { "ep11_tx", 2, }, | ||
| 92 | { "ep11_rx", 2, }, | ||
| 93 | { "ep12_tx", 2, }, | ||
| 94 | { "ep12_rx", 2, }, | ||
| 95 | { "ep13_tx", 2, }, | ||
| 96 | { "ep13_rx", 2, }, | ||
| 97 | { "ep14_tx", 2, }, | ||
| 98 | { "ep14_rx", 2, }, | ||
| 99 | { "ep15_tx", 2, }, | ||
| 100 | { "ep15_rx", 2, }, | ||
| 101 | }; | ||
| 102 | |||
| 103 | static struct musb_hdrc_config musb_config = { | ||
| 104 | .multipoint = 1, | ||
| 105 | .dyn_fifo = 1, | ||
| 106 | .soft_con = 1, | ||
| 107 | .dma = 1, | ||
| 108 | .num_eps = 16, | ||
| 109 | .dma_channels = 7, | ||
| 110 | .dma_req_chan = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3), | ||
| 111 | .ram_bits = 12, | ||
| 112 | .eps_bits = musb_eps, | ||
| 113 | }; | ||
| 114 | |||
| 115 | static struct musb_hdrc_platform_data musb_plat = { | ||
| 116 | #ifdef CONFIG_USB_MUSB_OTG | ||
| 117 | .mode = MUSB_OTG, | ||
| 118 | #elif defined(CONFIG_USB_MUSB_HDRC_HCD) | ||
| 119 | .mode = MUSB_HOST, | ||
| 120 | #elif defined(CONFIG_USB_GADGET_MUSB_HDRC) | ||
| 121 | .mode = MUSB_PERIPHERAL, | ||
| 122 | #endif | ||
| 123 | /* .clock is set dynamically */ | ||
| 124 | .set_clock = musb_set_clock, | ||
| 125 | .config = &musb_config, | ||
| 126 | |||
| 127 | /* REVISIT charge pump on TWL4030 can supply up to | ||
| 128 | * 100 mA ... but this value is board-specific, like | ||
| 129 | * "mode", and should be passed to usb_musb_init(). | ||
| 130 | */ | ||
| 131 | .power = 50, /* up to 100 mA */ | ||
| 132 | }; | ||
| 133 | |||
| 134 | static u64 musb_dmamask = DMA_32BIT_MASK; | ||
| 135 | |||
| 136 | static struct platform_device musb_device = { | ||
| 137 | .name = "musb_hdrc", | ||
| 138 | .id = -1, | ||
| 139 | .dev = { | ||
| 140 | .dma_mask = &musb_dmamask, | ||
| 141 | .coherent_dma_mask = DMA_32BIT_MASK, | ||
| 142 | .platform_data = &musb_plat, | ||
| 143 | }, | ||
| 144 | .num_resources = ARRAY_SIZE(musb_resources), | ||
| 145 | .resource = musb_resources, | ||
| 146 | }; | ||
| 147 | |||
| 148 | #ifdef CONFIG_NOP_USB_XCEIV | ||
| 149 | static u64 nop_xceiv_dmamask = DMA_32BIT_MASK; | ||
| 150 | |||
| 151 | static struct platform_device nop_xceiv_device = { | ||
| 152 | .name = "nop_usb_xceiv", | ||
| 153 | .id = -1, | ||
| 154 | .dev = { | ||
| 155 | .dma_mask = &nop_xceiv_dmamask, | ||
| 156 | .coherent_dma_mask = DMA_32BIT_MASK, | ||
| 157 | .platform_data = NULL, | ||
| 158 | }, | ||
| 159 | }; | ||
| 160 | #endif | ||
| 161 | |||
| 162 | void __init usb_musb_init(void) | ||
| 163 | { | ||
| 164 | if (cpu_is_omap243x()) | ||
| 165 | musb_resources[0].start = OMAP243X_HS_BASE; | ||
| 166 | else | ||
| 167 | musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; | ||
| 168 | musb_resources[0].end = musb_resources[0].start + SZ_8K - 1; | ||
| 169 | |||
| 170 | /* | ||
| 171 | * REVISIT: This line can be removed once all the platforms using | ||
| 172 | * musb_core.c have been converted to use use clkdev. | ||
| 173 | */ | ||
| 174 | musb_plat.clock = "ick"; | ||
| 175 | |||
| 176 | #ifdef CONFIG_NOP_USB_XCEIV | ||
| 177 | if (platform_device_register(&nop_xceiv_device) < 0) { | ||
| 178 | printk(KERN_ERR "Unable to register NOP-XCEIV device\n"); | ||
| 179 | return; | ||
| 180 | } | ||
| 181 | #endif | ||
| 182 | |||
| 183 | if (platform_device_register(&musb_device) < 0) { | ||
| 184 | printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); | ||
| 185 | return; | ||
| 186 | } | ||
| 187 | } | ||
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index f59a8d0e0824..2c7035d8dcbf 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig | |||
| @@ -71,6 +71,7 @@ config MACH_WRT350N_V2 | |||
| 71 | 71 | ||
| 72 | config MACH_TS78XX | 72 | config MACH_TS78XX |
| 73 | bool "Technologic Systems TS-78xx" | 73 | bool "Technologic Systems TS-78xx" |
| 74 | select PM | ||
| 74 | help | 75 | help |
| 75 | Say 'Y' here if you want your kernel to support the | 76 | Say 'Y' here if you want your kernel to support the |
| 76 | Technologic Systems TS-78xx platform. | 77 | Technologic Systems TS-78xx platform. |
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 0a623379789f..8a0e49d84256 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c | |||
| @@ -431,6 +431,10 @@ void __init orion5x_uart1_init(void) | |||
| 431 | /***************************************************************************** | 431 | /***************************************************************************** |
| 432 | * XOR engine | 432 | * XOR engine |
| 433 | ****************************************************************************/ | 433 | ****************************************************************************/ |
| 434 | struct mv_xor_platform_shared_data orion5x_xor_shared_data = { | ||
| 435 | .dram = &orion5x_mbus_dram_info, | ||
| 436 | }; | ||
| 437 | |||
| 434 | static struct resource orion5x_xor_shared_resources[] = { | 438 | static struct resource orion5x_xor_shared_resources[] = { |
| 435 | { | 439 | { |
| 436 | .name = "xor low", | 440 | .name = "xor low", |
| @@ -448,6 +452,9 @@ static struct resource orion5x_xor_shared_resources[] = { | |||
| 448 | static struct platform_device orion5x_xor_shared = { | 452 | static struct platform_device orion5x_xor_shared = { |
| 449 | .name = MV_XOR_SHARED_NAME, | 453 | .name = MV_XOR_SHARED_NAME, |
| 450 | .id = 0, | 454 | .id = 0, |
| 455 | .dev = { | ||
| 456 | .platform_data = &orion5x_xor_shared_data, | ||
| 457 | }, | ||
| 451 | .num_resources = ARRAY_SIZE(orion5x_xor_shared_resources), | 458 | .num_resources = ARRAY_SIZE(orion5x_xor_shared_resources), |
| 452 | .resource = orion5x_xor_shared_resources, | 459 | .resource = orion5x_xor_shared_resources, |
| 453 | }; | 460 | }; |
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c index 0722d6510df1..b31ca4cef365 100644 --- a/arch/arm/mach-orion5x/dns323-setup.c +++ b/arch/arm/mach-orion5x/dns323-setup.c | |||
| @@ -76,7 +76,7 @@ static int __init dns323_dev_id(void) | |||
| 76 | 76 | ||
| 77 | static int __init dns323_pci_init(void) | 77 | static int __init dns323_pci_init(void) |
| 78 | { | 78 | { |
| 79 | /* The 5182 doesn't really use it's PCI bus, and initialising PCI | 79 | /* The 5182 doesn't really use its PCI bus, and initialising PCI |
| 80 | * gets in the way of initialising the SATA controller. | 80 | * gets in the way of initialising the SATA controller. |
| 81 | */ | 81 | */ |
| 82 | if (machine_is_dns323() && dns323_dev_id() != MV88F5182_DEV_ID) | 82 | if (machine_is_dns323() && dns323_dev_id() != MV88F5182_DEV_ID) |
| @@ -418,7 +418,7 @@ static void __init dns323_init(void) | |||
| 418 | orion5x_i2c_init(); | 418 | orion5x_i2c_init(); |
| 419 | orion5x_uart0_init(); | 419 | orion5x_uart0_init(); |
| 420 | 420 | ||
| 421 | /* The 5182 has it's SATA controller on-chip, and needs it's own little | 421 | /* The 5182 has its SATA controller on-chip, and needs its own little |
| 422 | * init routine. | 422 | * init routine. |
| 423 | */ | 423 | */ |
| 424 | if (dns323_dev_id() == MV88F5182_DEV_ID) | 424 | if (dns323_dev_id() == MV88F5182_DEV_ID) |
diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h index 08e430757890..9b8db1dcfa83 100644 --- a/arch/arm/mach-orion5x/include/mach/system.h +++ b/arch/arm/mach-orion5x/include/mach/system.h | |||
| @@ -19,7 +19,7 @@ static inline void arch_idle(void) | |||
| 19 | cpu_do_idle(); | 19 | cpu_do_idle(); |
| 20 | } | 20 | } |
| 21 | 21 | ||
| 22 | static inline void arch_reset(char mode) | 22 | static inline void arch_reset(char mode, const char *cmd) |
| 23 | { | 23 | { |
| 24 | /* | 24 | /* |
| 25 | * Enable and issue soft reset | 25 | * Enable and issue soft reset |
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c index e0c43b8beb72..c9bf6b81a80d 100644 --- a/arch/arm/mach-orion5x/lsmini-setup.c +++ b/arch/arm/mach-orion5x/lsmini-setup.c | |||
| @@ -186,7 +186,7 @@ static struct mv_sata_platform_data lsmini_sata_data = { | |||
| 186 | 186 | ||
| 187 | static void lsmini_power_off(void) | 187 | static void lsmini_power_off(void) |
| 188 | { | 188 | { |
| 189 | arch_reset(0); | 189 | arch_reset(0, NULL); |
| 190 | } | 190 | } |
| 191 | 191 | ||
| 192 | 192 | ||
diff --git a/arch/arm/mach-orion5x/ts78xx-fpga.h b/arch/arm/mach-orion5x/ts78xx-fpga.h new file mode 100644 index 000000000000..0f9cdf458952 --- /dev/null +++ b/arch/arm/mach-orion5x/ts78xx-fpga.h | |||
| @@ -0,0 +1,35 @@ | |||
| 1 | #define FPGAID(_magic, _rev) ((_magic << 8) + _rev) | ||
| 2 | |||
| 3 | /* | ||
| 4 | * get yer id's from http://ts78xx.digriz.org.uk/ | ||
| 5 | * do *not* make up your own or 'borrow' any! | ||
| 6 | */ | ||
| 7 | enum fpga_ids { | ||
| 8 | /* Technologic Systems */ | ||
| 9 | TS7800_REV_1 = FPGAID(0x00b480, 0x01), | ||
| 10 | TS7800_REV_2 = FPGAID(0x00b480, 0x02), | ||
| 11 | TS7800_REV_3 = FPGAID(0x00b480, 0x03), | ||
| 12 | TS7800_REV_4 = FPGAID(0x00b480, 0x04), | ||
| 13 | TS7800_REV_5 = FPGAID(0x00b480, 0x05), | ||
| 14 | |||
| 15 | /* Unaffordable & Expensive */ | ||
| 16 | UAE_DUMMY = FPGAID(0xffffff, 0x01), | ||
| 17 | }; | ||
| 18 | |||
| 19 | struct fpga_device { | ||
| 20 | unsigned present:1; | ||
| 21 | unsigned init:1; | ||
| 22 | }; | ||
| 23 | |||
| 24 | struct fpga_devices { | ||
| 25 | /* Technologic Systems */ | ||
| 26 | struct fpga_device ts_rtc; | ||
| 27 | struct fpga_device ts_nand; | ||
| 28 | }; | ||
| 29 | |||
| 30 | struct ts78xx_fpga_data { | ||
| 31 | unsigned int id; | ||
| 32 | int state; | ||
| 33 | |||
| 34 | struct fpga_devices supports; | ||
| 35 | }; | ||
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index 1368e9fd1a06..9a6b397f972d 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c | |||
| @@ -10,17 +10,20 @@ | |||
| 10 | 10 | ||
| 11 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
| 12 | #include <linux/init.h> | 12 | #include <linux/init.h> |
| 13 | #include <linux/sysfs.h> | ||
| 13 | #include <linux/platform_device.h> | 14 | #include <linux/platform_device.h> |
| 14 | #include <linux/mtd/physmap.h> | ||
| 15 | #include <linux/mv643xx_eth.h> | 15 | #include <linux/mv643xx_eth.h> |
| 16 | #include <linux/ata_platform.h> | 16 | #include <linux/ata_platform.h> |
| 17 | #include <linux/m48t86.h> | 17 | #include <linux/m48t86.h> |
| 18 | #include <linux/mtd/nand.h> | ||
| 19 | #include <linux/mtd/partitions.h> | ||
| 18 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
| 19 | #include <asm/mach/arch.h> | 21 | #include <asm/mach/arch.h> |
| 20 | #include <asm/mach/map.h> | 22 | #include <asm/mach/map.h> |
| 21 | #include <mach/orion5x.h> | 23 | #include <mach/orion5x.h> |
| 22 | #include "common.h" | 24 | #include "common.h" |
| 23 | #include "mpp.h" | 25 | #include "mpp.h" |
| 26 | #include "ts78xx-fpga.h" | ||
| 24 | 27 | ||
| 25 | /***************************************************************************** | 28 | /***************************************************************************** |
| 26 | * TS-78xx Info | 29 | * TS-78xx Info |
| @@ -33,18 +36,11 @@ | |||
| 33 | #define TS78XX_FPGA_REGS_VIRT_BASE 0xff900000 | 36 | #define TS78XX_FPGA_REGS_VIRT_BASE 0xff900000 |
| 34 | #define TS78XX_FPGA_REGS_SIZE SZ_1M | 37 | #define TS78XX_FPGA_REGS_SIZE SZ_1M |
| 35 | 38 | ||
| 36 | #define TS78XX_FPGA_REGS_SYSCON_ID (TS78XX_FPGA_REGS_VIRT_BASE | 0x000) | 39 | static struct ts78xx_fpga_data ts78xx_fpga = { |
| 37 | #define TS78XX_FPGA_REGS_SYSCON_LCDI (TS78XX_FPGA_REGS_VIRT_BASE | 0x004) | 40 | .id = 0, |
| 38 | #define TS78XX_FPGA_REGS_SYSCON_LCDO (TS78XX_FPGA_REGS_VIRT_BASE | 0x008) | 41 | .state = 1, |
| 39 | 42 | /* .supports = ... - populated by ts78xx_fpga_supports() */ | |
| 40 | #define TS78XX_FPGA_REGS_RTC_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x808) | 43 | }; |
| 41 | #define TS78XX_FPGA_REGS_RTC_DATA (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c) | ||
| 42 | |||
| 43 | /* | ||
| 44 | * 512kB NOR flash Device | ||
| 45 | */ | ||
| 46 | #define TS78XX_NOR_BOOT_BASE 0xff800000 | ||
| 47 | #define TS78XX_NOR_BOOT_SIZE SZ_512K | ||
| 48 | 44 | ||
| 49 | /***************************************************************************** | 45 | /***************************************************************************** |
| 50 | * I/O Address Mapping | 46 | * I/O Address Mapping |
| @@ -65,73 +61,47 @@ void __init ts78xx_map_io(void) | |||
| 65 | } | 61 | } |
| 66 | 62 | ||
| 67 | /***************************************************************************** | 63 | /***************************************************************************** |
| 68 | * 512kB NOR Boot Flash - the chip is a M25P40 | 64 | * Ethernet |
| 69 | ****************************************************************************/ | 65 | ****************************************************************************/ |
| 70 | static struct mtd_partition ts78xx_nor_boot_flash_resources[] = { | 66 | static struct mv643xx_eth_platform_data ts78xx_eth_data = { |
| 71 | { | 67 | .phy_addr = MV643XX_ETH_PHY_ADDR(0), |
| 72 | .name = "ts-bootrom", | ||
| 73 | .offset = 0, | ||
| 74 | /* only the first 256kB is used */ | ||
| 75 | .size = SZ_256K, | ||
| 76 | .mask_flags = MTD_WRITEABLE, | ||
| 77 | }, | ||
| 78 | }; | ||
| 79 | |||
| 80 | static struct physmap_flash_data ts78xx_nor_boot_flash_data = { | ||
| 81 | .width = 1, | ||
| 82 | .parts = ts78xx_nor_boot_flash_resources, | ||
| 83 | .nr_parts = ARRAY_SIZE(ts78xx_nor_boot_flash_resources), | ||
| 84 | }; | ||
| 85 | |||
| 86 | static struct resource ts78xx_nor_boot_flash_resource = { | ||
| 87 | .flags = IORESOURCE_MEM, | ||
| 88 | .start = TS78XX_NOR_BOOT_BASE, | ||
| 89 | .end = TS78XX_NOR_BOOT_BASE + TS78XX_NOR_BOOT_SIZE - 1, | ||
| 90 | }; | ||
| 91 | |||
| 92 | static struct platform_device ts78xx_nor_boot_flash = { | ||
| 93 | .name = "physmap-flash", | ||
| 94 | .id = -1, | ||
| 95 | .dev = { | ||
| 96 | .platform_data = &ts78xx_nor_boot_flash_data, | ||
| 97 | }, | ||
| 98 | .num_resources = 1, | ||
| 99 | .resource = &ts78xx_nor_boot_flash_resource, | ||
| 100 | }; | 68 | }; |
| 101 | 69 | ||
| 102 | /***************************************************************************** | 70 | /***************************************************************************** |
| 103 | * Ethernet | 71 | * SATA |
| 104 | ****************************************************************************/ | 72 | ****************************************************************************/ |
| 105 | static struct mv643xx_eth_platform_data ts78xx_eth_data = { | 73 | static struct mv_sata_platform_data ts78xx_sata_data = { |
| 106 | .phy_addr = MV643XX_ETH_PHY_ADDR(0), | 74 | .n_ports = 2, |
| 107 | }; | 75 | }; |
| 108 | 76 | ||
| 109 | /***************************************************************************** | 77 | /***************************************************************************** |
| 110 | * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c | 78 | * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c |
| 111 | ****************************************************************************/ | 79 | ****************************************************************************/ |
| 112 | #ifdef CONFIG_RTC_DRV_M48T86 | 80 | #define TS_RTC_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x808) |
| 113 | static unsigned char ts78xx_rtc_readbyte(unsigned long addr) | 81 | #define TS_RTC_DATA (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c) |
| 82 | |||
| 83 | static unsigned char ts78xx_ts_rtc_readbyte(unsigned long addr) | ||
| 114 | { | 84 | { |
| 115 | writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL); | 85 | writeb(addr, TS_RTC_CTRL); |
| 116 | return readb(TS78XX_FPGA_REGS_RTC_DATA); | 86 | return readb(TS_RTC_DATA); |
| 117 | } | 87 | } |
| 118 | 88 | ||
| 119 | static void ts78xx_rtc_writebyte(unsigned char value, unsigned long addr) | 89 | static void ts78xx_ts_rtc_writebyte(unsigned char value, unsigned long addr) |
| 120 | { | 90 | { |
| 121 | writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL); | 91 | writeb(addr, TS_RTC_CTRL); |
| 122 | writeb(value, TS78XX_FPGA_REGS_RTC_DATA); | 92 | writeb(value, TS_RTC_DATA); |
| 123 | } | 93 | } |
| 124 | 94 | ||
| 125 | static struct m48t86_ops ts78xx_rtc_ops = { | 95 | static struct m48t86_ops ts78xx_ts_rtc_ops = { |
| 126 | .readbyte = ts78xx_rtc_readbyte, | 96 | .readbyte = ts78xx_ts_rtc_readbyte, |
| 127 | .writebyte = ts78xx_rtc_writebyte, | 97 | .writebyte = ts78xx_ts_rtc_writebyte, |
| 128 | }; | 98 | }; |
| 129 | 99 | ||
| 130 | static struct platform_device ts78xx_rtc_device = { | 100 | static struct platform_device ts78xx_ts_rtc_device = { |
| 131 | .name = "rtc-m48t86", | 101 | .name = "rtc-m48t86", |
| 132 | .id = -1, | 102 | .id = -1, |
| 133 | .dev = { | 103 | .dev = { |
| 134 | .platform_data = &ts78xx_rtc_ops, | 104 | .platform_data = &ts78xx_ts_rtc_ops, |
| 135 | }, | 105 | }, |
| 136 | .num_resources = 0, | 106 | .num_resources = 0, |
| 137 | }; | 107 | }; |
| @@ -146,59 +116,314 @@ static struct platform_device ts78xx_rtc_device = { | |||
| 146 | * TODO: track down a guinea pig without an RTC to see if we can work out a | 116 | * TODO: track down a guinea pig without an RTC to see if we can work out a |
| 147 | * better RTC detection routine | 117 | * better RTC detection routine |
| 148 | */ | 118 | */ |
| 149 | static int __init ts78xx_rtc_init(void) | 119 | static int ts78xx_ts_rtc_load(void) |
| 150 | { | 120 | { |
| 121 | int rc; | ||
| 151 | unsigned char tmp_rtc0, tmp_rtc1; | 122 | unsigned char tmp_rtc0, tmp_rtc1; |
| 152 | 123 | ||
| 153 | tmp_rtc0 = ts78xx_rtc_readbyte(126); | 124 | tmp_rtc0 = ts78xx_ts_rtc_readbyte(126); |
| 154 | tmp_rtc1 = ts78xx_rtc_readbyte(127); | 125 | tmp_rtc1 = ts78xx_ts_rtc_readbyte(127); |
| 155 | 126 | ||
| 156 | ts78xx_rtc_writebyte(0x00, 126); | 127 | ts78xx_ts_rtc_writebyte(0x00, 126); |
| 157 | ts78xx_rtc_writebyte(0x55, 127); | 128 | ts78xx_ts_rtc_writebyte(0x55, 127); |
| 158 | if (ts78xx_rtc_readbyte(127) == 0x55) { | 129 | if (ts78xx_ts_rtc_readbyte(127) == 0x55) { |
| 159 | ts78xx_rtc_writebyte(0xaa, 127); | 130 | ts78xx_ts_rtc_writebyte(0xaa, 127); |
| 160 | if (ts78xx_rtc_readbyte(127) == 0xaa | 131 | if (ts78xx_ts_rtc_readbyte(127) == 0xaa |
| 161 | && ts78xx_rtc_readbyte(126) == 0x00) { | 132 | && ts78xx_ts_rtc_readbyte(126) == 0x00) { |
| 162 | ts78xx_rtc_writebyte(tmp_rtc0, 126); | 133 | ts78xx_ts_rtc_writebyte(tmp_rtc0, 126); |
| 163 | ts78xx_rtc_writebyte(tmp_rtc1, 127); | 134 | ts78xx_ts_rtc_writebyte(tmp_rtc1, 127); |
| 164 | platform_device_register(&ts78xx_rtc_device); | 135 | |
| 165 | return 1; | 136 | if (ts78xx_fpga.supports.ts_rtc.init == 0) { |
| 137 | rc = platform_device_register(&ts78xx_ts_rtc_device); | ||
| 138 | if (!rc) | ||
| 139 | ts78xx_fpga.supports.ts_rtc.init = 1; | ||
| 140 | } else | ||
| 141 | rc = platform_device_add(&ts78xx_ts_rtc_device); | ||
| 142 | |||
| 143 | return rc; | ||
| 166 | } | 144 | } |
| 167 | } | 145 | } |
| 168 | 146 | ||
| 169 | return 0; | 147 | return -ENODEV; |
| 170 | }; | 148 | }; |
| 171 | #else | 149 | |
| 172 | static int __init ts78xx_rtc_init(void) | 150 | static void ts78xx_ts_rtc_unload(void) |
| 173 | { | 151 | { |
| 174 | return 0; | 152 | platform_device_del(&ts78xx_ts_rtc_device); |
| 175 | } | 153 | } |
| 176 | #endif | ||
| 177 | 154 | ||
| 178 | /***************************************************************************** | 155 | /***************************************************************************** |
| 179 | * SATA | 156 | * NAND Flash |
| 180 | ****************************************************************************/ | 157 | ****************************************************************************/ |
| 181 | static struct mv_sata_platform_data ts78xx_sata_data = { | 158 | #define TS_NAND_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x800) /* VIRT */ |
| 182 | .n_ports = 2, | 159 | #define TS_NAND_DATA (TS78XX_FPGA_REGS_PHYS_BASE | 0x804) /* PHYS */ |
| 160 | |||
| 161 | /* | ||
| 162 | * hardware specific access to control-lines | ||
| 163 | * | ||
| 164 | * ctrl: | ||
| 165 | * NAND_NCE: bit 0 -> bit 2 | ||
| 166 | * NAND_CLE: bit 1 -> bit 1 | ||
| 167 | * NAND_ALE: bit 2 -> bit 0 | ||
| 168 | */ | ||
| 169 | static void ts78xx_ts_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, | ||
| 170 | unsigned int ctrl) | ||
| 171 | { | ||
| 172 | struct nand_chip *this = mtd->priv; | ||
| 173 | |||
| 174 | if (ctrl & NAND_CTRL_CHANGE) { | ||
| 175 | unsigned char bits; | ||
| 176 | |||
| 177 | bits = (ctrl & NAND_NCE) << 2; | ||
| 178 | bits |= ctrl & NAND_CLE; | ||
| 179 | bits |= (ctrl & NAND_ALE) >> 2; | ||
| 180 | |||
| 181 | writeb((readb(TS_NAND_CTRL) & ~0x7) | bits, TS_NAND_CTRL); | ||
| 182 | } | ||
| 183 | |||
| 184 | if (cmd != NAND_CMD_NONE) | ||
| 185 | writeb(cmd, this->IO_ADDR_W); | ||
| 186 | } | ||
| 187 | |||
| 188 | static int ts78xx_ts_nand_dev_ready(struct mtd_info *mtd) | ||
| 189 | { | ||
| 190 | return readb(TS_NAND_CTRL) & 0x20; | ||
| 191 | } | ||
| 192 | |||
| 193 | const char *ts_nand_part_probes[] = { "cmdlinepart", NULL }; | ||
| 194 | |||
| 195 | static struct mtd_partition ts78xx_ts_nand_parts[] = { | ||
| 196 | { | ||
| 197 | .name = "mbr", | ||
| 198 | .offset = 0, | ||
| 199 | .size = SZ_128K, | ||
| 200 | .mask_flags = MTD_WRITEABLE, | ||
| 201 | }, { | ||
| 202 | .name = "kernel", | ||
| 203 | .offset = MTDPART_OFS_APPEND, | ||
| 204 | .size = SZ_4M, | ||
| 205 | }, { | ||
| 206 | .name = "initrd", | ||
| 207 | .offset = MTDPART_OFS_APPEND, | ||
| 208 | .size = SZ_4M, | ||
| 209 | }, { | ||
| 210 | .name = "rootfs", | ||
| 211 | .offset = MTDPART_OFS_APPEND, | ||
| 212 | .size = MTDPART_SIZ_FULL, | ||
| 213 | } | ||
| 183 | }; | 214 | }; |
| 184 | 215 | ||
| 216 | static struct platform_nand_data ts78xx_ts_nand_data = { | ||
| 217 | .chip = { | ||
| 218 | .part_probe_types = ts_nand_part_probes, | ||
| 219 | .partitions = ts78xx_ts_nand_parts, | ||
| 220 | .nr_partitions = ARRAY_SIZE(ts78xx_ts_nand_parts), | ||
| 221 | .chip_delay = 15, | ||
| 222 | .options = NAND_USE_FLASH_BBT, | ||
| 223 | }, | ||
| 224 | .ctrl = { | ||
| 225 | /* | ||
| 226 | * The HW ECC offloading functions, used to give about a 9% | ||
| 227 | * performance increase for 'dd if=/dev/mtdblockX' and 5% for | ||
| 228 | * nanddump. This all however was changed by git commit | ||
| 229 | * e6cf5df1838c28bb060ac45b5585e48e71bbc740 so now there is | ||
| 230 | * no performance advantage to be had so we no longer bother | ||
| 231 | */ | ||
| 232 | .cmd_ctrl = ts78xx_ts_nand_cmd_ctrl, | ||
| 233 | .dev_ready = ts78xx_ts_nand_dev_ready, | ||
| 234 | }, | ||
| 235 | }; | ||
| 236 | |||
| 237 | static struct resource ts78xx_ts_nand_resources = { | ||
| 238 | .start = TS_NAND_DATA, | ||
| 239 | .end = TS_NAND_DATA + 4, | ||
| 240 | .flags = IORESOURCE_IO, | ||
| 241 | }; | ||
| 242 | |||
| 243 | static struct platform_device ts78xx_ts_nand_device = { | ||
| 244 | .name = "gen_nand", | ||
| 245 | .id = -1, | ||
| 246 | .dev = { | ||
| 247 | .platform_data = &ts78xx_ts_nand_data, | ||
| 248 | }, | ||
| 249 | .resource = &ts78xx_ts_nand_resources, | ||
| 250 | .num_resources = 1, | ||
| 251 | }; | ||
| 252 | |||
| 253 | static int ts78xx_ts_nand_load(void) | ||
| 254 | { | ||
| 255 | int rc; | ||
| 256 | |||
| 257 | if (ts78xx_fpga.supports.ts_nand.init == 0) { | ||
| 258 | rc = platform_device_register(&ts78xx_ts_nand_device); | ||
| 259 | if (!rc) | ||
| 260 | ts78xx_fpga.supports.ts_nand.init = 1; | ||
| 261 | } else | ||
| 262 | rc = platform_device_add(&ts78xx_ts_nand_device); | ||
| 263 | |||
| 264 | return rc; | ||
| 265 | }; | ||
| 266 | |||
| 267 | static void ts78xx_ts_nand_unload(void) | ||
| 268 | { | ||
| 269 | platform_device_del(&ts78xx_ts_nand_device); | ||
| 270 | } | ||
| 271 | |||
| 185 | /***************************************************************************** | 272 | /***************************************************************************** |
| 186 | * print some information regarding the board | 273 | * FPGA 'hotplug' support code |
| 187 | ****************************************************************************/ | 274 | ****************************************************************************/ |
| 188 | static void __init ts78xx_print_board_id(void) | 275 | static void ts78xx_fpga_devices_zero_init(void) |
| 189 | { | 276 | { |
| 190 | unsigned int board_info; | 277 | ts78xx_fpga.supports.ts_rtc.init = 0; |
| 191 | 278 | ts78xx_fpga.supports.ts_nand.init = 0; | |
| 192 | board_info = readl(TS78XX_FPGA_REGS_SYSCON_ID); | 279 | } |
| 193 | printk(KERN_INFO "TS-78xx Info: FPGA rev=%.2x, Board Magic=%.6x, ", | 280 | |
| 194 | board_info & 0xff, | 281 | static void ts78xx_fpga_supports(void) |
| 195 | (board_info >> 8) & 0xffffff); | 282 | { |
| 196 | board_info = readl(TS78XX_FPGA_REGS_SYSCON_LCDI); | 283 | /* TODO: put this 'table' into ts78xx-fpga.h */ |
| 197 | printk("JP1=%d, JP2=%d\n", | 284 | switch (ts78xx_fpga.id) { |
| 198 | (board_info >> 30) & 0x1, | 285 | case TS7800_REV_1: |
| 199 | (board_info >> 31) & 0x1); | 286 | case TS7800_REV_2: |
| 287 | case TS7800_REV_3: | ||
| 288 | case TS7800_REV_4: | ||
| 289 | case TS7800_REV_5: | ||
| 290 | ts78xx_fpga.supports.ts_rtc.present = 1; | ||
| 291 | ts78xx_fpga.supports.ts_nand.present = 1; | ||
| 292 | break; | ||
| 293 | default: | ||
| 294 | ts78xx_fpga.supports.ts_rtc.present = 0; | ||
| 295 | ts78xx_fpga.supports.ts_nand.present = 0; | ||
| 296 | } | ||
| 297 | } | ||
| 298 | |||
| 299 | static int ts78xx_fpga_load_devices(void) | ||
| 300 | { | ||
| 301 | int tmp, ret = 0; | ||
| 302 | |||
| 303 | if (ts78xx_fpga.supports.ts_rtc.present == 1) { | ||
| 304 | tmp = ts78xx_ts_rtc_load(); | ||
| 305 | if (tmp) { | ||
| 306 | printk(KERN_INFO "TS-78xx: RTC not registered\n"); | ||
| 307 | ts78xx_fpga.supports.ts_rtc.present = 0; | ||
| 308 | } | ||
| 309 | ret |= tmp; | ||
| 310 | } | ||
| 311 | if (ts78xx_fpga.supports.ts_nand.present == 1) { | ||
| 312 | tmp = ts78xx_ts_nand_load(); | ||
| 313 | if (tmp) { | ||
| 314 | printk(KERN_INFO "TS-78xx: NAND not registered\n"); | ||
| 315 | ts78xx_fpga.supports.ts_nand.present = 0; | ||
| 316 | } | ||
| 317 | ret |= tmp; | ||
| 318 | } | ||
| 319 | |||
| 320 | return ret; | ||
| 321 | } | ||
| 322 | |||
| 323 | static int ts78xx_fpga_unload_devices(void) | ||
| 324 | { | ||
| 325 | int ret = 0; | ||
| 326 | |||
| 327 | if (ts78xx_fpga.supports.ts_rtc.present == 1) | ||
| 328 | ts78xx_ts_rtc_unload(); | ||
| 329 | if (ts78xx_fpga.supports.ts_nand.present == 1) | ||
| 330 | ts78xx_ts_nand_unload(); | ||
| 331 | |||
| 332 | return ret; | ||
| 333 | } | ||
| 334 | |||
| 335 | static int ts78xx_fpga_load(void) | ||
| 336 | { | ||
| 337 | ts78xx_fpga.id = readl(TS78XX_FPGA_REGS_VIRT_BASE); | ||
| 338 | |||
| 339 | printk(KERN_INFO "TS-78xx FPGA: magic=0x%.6x, rev=0x%.2x\n", | ||
| 340 | (ts78xx_fpga.id >> 8) & 0xffffff, | ||
| 341 | ts78xx_fpga.id & 0xff); | ||
| 342 | |||
| 343 | ts78xx_fpga_supports(); | ||
| 344 | |||
| 345 | if (ts78xx_fpga_load_devices()) { | ||
| 346 | ts78xx_fpga.state = -1; | ||
| 347 | return -EBUSY; | ||
| 348 | } | ||
| 349 | |||
| 350 | return 0; | ||
| 200 | }; | 351 | }; |
| 201 | 352 | ||
| 353 | static int ts78xx_fpga_unload(void) | ||
| 354 | { | ||
| 355 | unsigned int fpga_id; | ||
| 356 | |||
| 357 | fpga_id = readl(TS78XX_FPGA_REGS_VIRT_BASE); | ||
| 358 | |||
| 359 | /* | ||
| 360 | * There does not seem to be a feasible way to block access to the GPIO | ||
| 361 | * pins from userspace (/dev/mem). This if clause should hopefully warn | ||
| 362 | * those foolish enough not to follow 'policy' :) | ||
| 363 | * | ||
| 364 | * UrJTAG SVN since r1381 can be used to reprogram the FPGA | ||
| 365 | */ | ||
| 366 | if (ts78xx_fpga.id != fpga_id) { | ||
| 367 | printk(KERN_ERR "TS-78xx FPGA: magic/rev mismatch\n" | ||
| 368 | "TS-78xx FPGA: was 0x%.6x/%.2x but now 0x%.6x/%.2x\n", | ||
| 369 | (ts78xx_fpga.id >> 8) & 0xffffff, ts78xx_fpga.id & 0xff, | ||
| 370 | (fpga_id >> 8) & 0xffffff, fpga_id & 0xff); | ||
| 371 | ts78xx_fpga.state = -1; | ||
| 372 | return -EBUSY; | ||
| 373 | } | ||
| 374 | |||
| 375 | if (ts78xx_fpga_unload_devices()) { | ||
| 376 | ts78xx_fpga.state = -1; | ||
| 377 | return -EBUSY; | ||
| 378 | } | ||
| 379 | |||
| 380 | return 0; | ||
| 381 | }; | ||
| 382 | |||
| 383 | static ssize_t ts78xx_fpga_show(struct kobject *kobj, | ||
| 384 | struct kobj_attribute *attr, char *buf) | ||
| 385 | { | ||
| 386 | if (ts78xx_fpga.state < 0) | ||
| 387 | return sprintf(buf, "borked\n"); | ||
| 388 | |||
| 389 | return sprintf(buf, "%s\n", (ts78xx_fpga.state) ? "online" : "offline"); | ||
| 390 | } | ||
| 391 | |||
| 392 | static ssize_t ts78xx_fpga_store(struct kobject *kobj, | ||
| 393 | struct kobj_attribute *attr, const char *buf, size_t n) | ||
| 394 | { | ||
| 395 | int value, ret; | ||
| 396 | |||
| 397 | if (ts78xx_fpga.state < 0) { | ||
| 398 | printk(KERN_ERR "TS-78xx FPGA: borked, you must powercycle asap\n"); | ||
| 399 | return -EBUSY; | ||
| 400 | } | ||
| 401 | |||
| 402 | if (strncmp(buf, "online", sizeof("online") - 1) == 0) | ||
| 403 | value = 1; | ||
| 404 | else if (strncmp(buf, "offline", sizeof("offline") - 1) == 0) | ||
| 405 | value = 0; | ||
| 406 | else { | ||
| 407 | printk(KERN_ERR "ts78xx_fpga_store: Invalid value\n"); | ||
| 408 | return -EINVAL; | ||
| 409 | } | ||
| 410 | |||
| 411 | if (ts78xx_fpga.state == value) | ||
| 412 | return n; | ||
| 413 | |||
| 414 | ret = (ts78xx_fpga.state == 0) | ||
| 415 | ? ts78xx_fpga_load() | ||
| 416 | : ts78xx_fpga_unload(); | ||
| 417 | |||
| 418 | if (!(ret < 0)) | ||
| 419 | ts78xx_fpga.state = value; | ||
| 420 | |||
| 421 | return n; | ||
| 422 | } | ||
| 423 | |||
| 424 | static struct kobj_attribute ts78xx_fpga_attr = | ||
| 425 | __ATTR(ts78xx_fpga, 0644, ts78xx_fpga_show, ts78xx_fpga_store); | ||
| 426 | |||
| 202 | /***************************************************************************** | 427 | /***************************************************************************** |
| 203 | * General Setup | 428 | * General Setup |
| 204 | ****************************************************************************/ | 429 | ****************************************************************************/ |
| @@ -223,30 +448,29 @@ static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = { | |||
| 223 | { 17, MPP_UART }, | 448 | { 17, MPP_UART }, |
| 224 | { 18, MPP_UART }, | 449 | { 18, MPP_UART }, |
| 225 | { 19, MPP_UART }, | 450 | { 19, MPP_UART }, |
| 451 | /* | ||
| 452 | * MPP[20] PCI Clock Out 1 | ||
| 453 | * MPP[21] PCI Clock Out 0 | ||
| 454 | * MPP[22] Unused | ||
| 455 | * MPP[23] Unused | ||
| 456 | * MPP[24] Unused | ||
| 457 | * MPP[25] Unused | ||
| 458 | */ | ||
| 226 | { -1 }, | 459 | { -1 }, |
| 227 | }; | 460 | }; |
| 228 | 461 | ||
| 229 | static void __init ts78xx_init(void) | 462 | static void __init ts78xx_init(void) |
| 230 | { | 463 | { |
| 464 | int ret; | ||
| 465 | |||
| 231 | /* | 466 | /* |
| 232 | * Setup basic Orion functions. Need to be called early. | 467 | * Setup basic Orion functions. Need to be called early. |
| 233 | */ | 468 | */ |
| 234 | orion5x_init(); | 469 | orion5x_init(); |
| 235 | 470 | ||
| 236 | ts78xx_print_board_id(); | ||
| 237 | |||
| 238 | orion5x_mpp_conf(ts78xx_mpp_modes); | 471 | orion5x_mpp_conf(ts78xx_mpp_modes); |
| 239 | 472 | ||
| 240 | /* | 473 | /* |
| 241 | * MPP[20] PCI Clock Out 1 | ||
| 242 | * MPP[21] PCI Clock Out 0 | ||
| 243 | * MPP[22] Unused | ||
| 244 | * MPP[23] Unused | ||
| 245 | * MPP[24] Unused | ||
| 246 | * MPP[25] Unused | ||
| 247 | */ | ||
| 248 | |||
| 249 | /* | ||
| 250 | * Configure peripherals. | 474 | * Configure peripherals. |
| 251 | */ | 475 | */ |
| 252 | orion5x_ehci0_init(); | 476 | orion5x_ehci0_init(); |
| @@ -257,12 +481,12 @@ static void __init ts78xx_init(void) | |||
| 257 | orion5x_uart1_init(); | 481 | orion5x_uart1_init(); |
| 258 | orion5x_xor_init(); | 482 | orion5x_xor_init(); |
| 259 | 483 | ||
| 260 | orion5x_setup_dev_boot_win(TS78XX_NOR_BOOT_BASE, | 484 | /* FPGA init */ |
| 261 | TS78XX_NOR_BOOT_SIZE); | 485 | ts78xx_fpga_devices_zero_init(); |
| 262 | platform_device_register(&ts78xx_nor_boot_flash); | 486 | ret = ts78xx_fpga_load(); |
| 263 | 487 | ret = sysfs_create_file(power_kobj, &ts78xx_fpga_attr.attr); | |
| 264 | if (!ts78xx_rtc_init()) | 488 | if (ret) |
| 265 | printk(KERN_INFO "TS-78xx RTC not detected or enabled\n"); | 489 | printk(KERN_ERR "sysfs_create_file failed: %d\n", ret); |
| 266 | } | 490 | } |
| 267 | 491 | ||
| 268 | MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC") | 492 | MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC") |
diff --git a/arch/arm/mach-pnx4008/include/mach/system.h b/arch/arm/mach-pnx4008/include/mach/system.h index e12e7abfcbcf..5dda2bb55f8d 100644 --- a/arch/arm/mach-pnx4008/include/mach/system.h +++ b/arch/arm/mach-pnx4008/include/mach/system.h | |||
| @@ -30,7 +30,7 @@ static void arch_idle(void) | |||
| 30 | cpu_do_idle(); | 30 | cpu_do_idle(); |
| 31 | } | 31 | } |
| 32 | 32 | ||
| 33 | static inline void arch_reset(char mode) | 33 | static inline void arch_reset(char mode, const char *cmd) |
| 34 | { | 34 | { |
| 35 | cpu_reset(0); | 35 | cpu_reset(0); |
| 36 | } | 36 | } |
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig index 8eea7306f29b..96a2006cb597 100644 --- a/arch/arm/mach-pxa/Kconfig +++ b/arch/arm/mach-pxa/Kconfig | |||
| @@ -40,6 +40,9 @@ choice | |||
| 40 | config GUMSTIX_AM200EPD | 40 | config GUMSTIX_AM200EPD |
| 41 | bool "Enable AM200EPD board support" | 41 | bool "Enable AM200EPD board support" |
| 42 | 42 | ||
| 43 | config GUMSTIX_AM300EPD | ||
| 44 | bool "Enable AM300EPD board support" | ||
| 45 | |||
| 43 | endchoice | 46 | endchoice |
| 44 | 47 | ||
| 45 | config MACH_INTELMOTE2 | 48 | config MACH_INTELMOTE2 |
| @@ -254,10 +257,24 @@ config MACH_EM_X270 | |||
| 254 | bool "CompuLab EM-x270 platform" | 257 | bool "CompuLab EM-x270 platform" |
| 255 | select PXA27x | 258 | select PXA27x |
| 256 | 259 | ||
| 260 | config MACH_EXEDA | ||
| 261 | bool "CompuLab eXeda platform" | ||
| 262 | select PXA27x | ||
| 263 | |||
| 257 | config MACH_COLIBRI | 264 | config MACH_COLIBRI |
| 258 | bool "Toradex Colibri PX27x" | 265 | bool "Toradex Colibri PXA270" |
| 259 | select PXA27x | 266 | select PXA27x |
| 260 | 267 | ||
| 268 | config MACH_COLIBRI300 | ||
| 269 | bool "Toradex Colibri PXA300/310" | ||
| 270 | select PXA3xx | ||
| 271 | select CPU_PXA300 | ||
| 272 | |||
| 273 | config MACH_COLIBRI320 | ||
| 274 | bool "Toradex Colibri PXA320" | ||
| 275 | select PXA3xx | ||
| 276 | select CPU_PXA320 | ||
| 277 | |||
| 261 | config MACH_ZYLONITE | 278 | config MACH_ZYLONITE |
| 262 | bool "PXA3xx Development Platform (aka Zylonite)" | 279 | bool "PXA3xx Development Platform (aka Zylonite)" |
| 263 | select PXA3xx | 280 | select PXA3xx |
| @@ -295,8 +312,15 @@ config MACH_MAGICIAN | |||
| 295 | bool "Enable HTC Magician Support" | 312 | bool "Enable HTC Magician Support" |
| 296 | select PXA27x | 313 | select PXA27x |
| 297 | select IWMMXT | 314 | select IWMMXT |
| 315 | select PXA_SSP | ||
| 316 | select HAVE_PWM | ||
| 298 | select PXA_HAVE_BOARD_IRQS | 317 | select PXA_HAVE_BOARD_IRQS |
| 299 | 318 | ||
| 319 | config MACH_HIMALAYA | ||
| 320 | bool "HTC Himalaya Support" | ||
| 321 | select CPU_PXA26x | ||
| 322 | select FB_W100 | ||
| 323 | |||
| 300 | config MACH_MIOA701 | 324 | config MACH_MIOA701 |
| 301 | bool "Mitac Mio A701 Support" | 325 | bool "Mitac Mio A701 Support" |
| 302 | select PXA27x | 326 | select PXA27x |
| @@ -319,6 +343,16 @@ config ARCH_PXA_PALM | |||
| 319 | bool "PXA based Palm PDAs" | 343 | bool "PXA based Palm PDAs" |
| 320 | select HAVE_PWM | 344 | select HAVE_PWM |
| 321 | 345 | ||
| 346 | config MACH_PALMT5 | ||
| 347 | bool "Palm Tungsten|T5" | ||
| 348 | default y | ||
| 349 | depends on ARCH_PXA_PALM | ||
| 350 | select PXA27x | ||
| 351 | select IWMMXT | ||
| 352 | help | ||
| 353 | Say Y here if you intend to run this kernel on a Palm Tungsten|T5 | ||
| 354 | handheld computer. | ||
| 355 | |||
| 322 | config MACH_PALMTX | 356 | config MACH_PALMTX |
| 323 | bool "Palm T|X" | 357 | bool "Palm T|X" |
| 324 | default y | 358 | default y |
| @@ -339,6 +373,16 @@ config MACH_PALMZ72 | |||
| 339 | Say Y here if you intend to run this kernel on Palm Zire 72 | 373 | Say Y here if you intend to run this kernel on Palm Zire 72 |
| 340 | handheld computer. | 374 | handheld computer. |
| 341 | 375 | ||
| 376 | config MACH_PALMLD | ||
| 377 | bool "Palm LifeDrive" | ||
| 378 | default y | ||
| 379 | depends on ARCH_PXA_PALM | ||
| 380 | select PXA27x | ||
| 381 | select IWMMXT | ||
| 382 | help | ||
| 383 | Say Y here if you intend to run this kernel on a Palm LifeDrive | ||
| 384 | handheld computer. | ||
| 385 | |||
| 342 | config MACH_PCM990_BASEBOARD | 386 | config MACH_PCM990_BASEBOARD |
| 343 | bool "PHYTEC PCM-990 development board" | 387 | bool "PHYTEC PCM-990 development board" |
| 344 | select HAVE_PWM | 388 | select HAVE_PWM |
| @@ -359,6 +403,18 @@ config PCM990_DISPLAY_NONE | |||
| 359 | 403 | ||
| 360 | endchoice | 404 | endchoice |
| 361 | 405 | ||
| 406 | config MACH_CSB726 | ||
| 407 | bool "Enable Cogent CSB726 System On a Module" | ||
| 408 | select PXA27x | ||
| 409 | select IWMMXT | ||
| 410 | help | ||
| 411 | Say Y here if you intend to run this kernel on a Cogent | ||
| 412 | CSB726 System On Module. | ||
| 413 | |||
| 414 | config CSB726_CSB701 | ||
| 415 | bool "Enable supprot for CSB701 baseboard" | ||
| 416 | depends on MACH_CSB726 | ||
| 417 | |||
| 362 | config PXA_EZX | 418 | config PXA_EZX |
| 363 | bool "Motorola EZX Platform" | 419 | bool "Motorola EZX Platform" |
| 364 | select PXA27x | 420 | select PXA27x |
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile index 7b28bb561d63..c80e1bac4945 100644 --- a/arch/arm/mach-pxa/Makefile +++ b/arch/arm/mach-pxa/Makefile | |||
| @@ -3,8 +3,8 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Common support (must be linked before board specific support) | 5 | # Common support (must be linked before board specific support) |
| 6 | obj-y += clock.o devices.o generic.o irq.o dma.o \ | 6 | obj-y += clock.o devices.o generic.o irq.o \ |
| 7 | time.o gpio.o reset.o | 7 | time.o reset.o |
| 8 | obj-$(CONFIG_PM) += pm.o sleep.o standby.o | 8 | obj-$(CONFIG_PM) += pm.o sleep.o standby.o |
| 9 | 9 | ||
| 10 | ifeq ($(CONFIG_CPU_FREQ),y) | 10 | ifeq ($(CONFIG_CPU_FREQ),y) |
| @@ -28,13 +28,16 @@ obj-$(CONFIG_CPU_PXA930) += pxa930.o | |||
| 28 | # Specific board support | 28 | # Specific board support |
| 29 | obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o | 29 | obj-$(CONFIG_ARCH_GUMSTIX) += gumstix.o |
| 30 | obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o | 30 | obj-$(CONFIG_GUMSTIX_AM200EPD) += am200epd.o |
| 31 | obj-$(CONFIG_GUMSTIX_AM300EPD) += am300epd.o | ||
| 31 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o | 32 | obj-$(CONFIG_ARCH_LUBBOCK) += lubbock.o |
| 32 | obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o | 33 | obj-$(CONFIG_MACH_LOGICPD_PXA270) += lpd270.o |
| 33 | obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o | 34 | obj-$(CONFIG_MACH_MAINSTONE) += mainstone.o |
| 34 | obj-$(CONFIG_MACH_MP900C) += mp900.o | 35 | obj-$(CONFIG_MACH_MP900C) += mp900.o |
| 35 | obj-$(CONFIG_ARCH_PXA_IDP) += idp.o | 36 | obj-$(CONFIG_ARCH_PXA_IDP) += idp.o |
| 36 | obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o | 37 | obj-$(CONFIG_MACH_TRIZEPS4) += trizeps4.o |
| 37 | obj-$(CONFIG_MACH_COLIBRI) += colibri.o | 38 | obj-$(CONFIG_MACH_COLIBRI) += colibri-pxa270.o |
| 39 | obj-$(CONFIG_MACH_COLIBRI300) += colibri-pxa3xx.o colibri-pxa300.o | ||
| 40 | obj-$(CONFIG_MACH_COLIBRI320) += colibri-pxa3xx.o colibri-pxa320.o | ||
| 38 | obj-$(CONFIG_MACH_H5000) += h5000.o | 41 | obj-$(CONFIG_MACH_H5000) += h5000.o |
| 39 | obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o | 42 | obj-$(CONFIG_PXA_SHARP_C7xx) += corgi.o sharpsl_pm.o corgi_pm.o |
| 40 | obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o | 43 | obj-$(CONFIG_PXA_SHARP_Cxx00) += spitz.o sharpsl_pm.o spitz_pm.o |
| @@ -45,6 +48,7 @@ obj-$(CONFIG_MACH_PCM990_BASEBOARD) += pcm990-baseboard.o | |||
| 45 | obj-$(CONFIG_MACH_TOSA) += tosa.o | 48 | obj-$(CONFIG_MACH_TOSA) += tosa.o |
| 46 | obj-$(CONFIG_MACH_EM_X270) += em-x270.o | 49 | obj-$(CONFIG_MACH_EM_X270) += em-x270.o |
| 47 | obj-$(CONFIG_MACH_MAGICIAN) += magician.o | 50 | obj-$(CONFIG_MACH_MAGICIAN) += magician.o |
| 51 | obj-$(CONFIG_MACH_HIMALAYA) += himalaya.o | ||
| 48 | obj-$(CONFIG_MACH_MIOA701) += mioa701.o mioa701_bootresume.o | 52 | obj-$(CONFIG_MACH_MIOA701) += mioa701.o mioa701_bootresume.o |
| 49 | obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o | 53 | obj-$(CONFIG_ARCH_PXA_ESERIES) += eseries.o |
| 50 | obj-$(CONFIG_MACH_E330) += e330.o | 54 | obj-$(CONFIG_MACH_E330) += e330.o |
| @@ -53,7 +57,9 @@ obj-$(CONFIG_MACH_E740) += e740.o | |||
| 53 | obj-$(CONFIG_MACH_E750) += e750.o | 57 | obj-$(CONFIG_MACH_E750) += e750.o |
| 54 | obj-$(CONFIG_MACH_E400) += e400.o | 58 | obj-$(CONFIG_MACH_E400) += e400.o |
| 55 | obj-$(CONFIG_MACH_E800) += e800.o | 59 | obj-$(CONFIG_MACH_E800) += e800.o |
| 60 | obj-$(CONFIG_MACH_PALMT5) += palmt5.o | ||
| 56 | obj-$(CONFIG_MACH_PALMTX) += palmtx.o | 61 | obj-$(CONFIG_MACH_PALMTX) += palmtx.o |
| 62 | obj-$(CONFIG_MACH_PALMLD) += palmld.o | ||
| 57 | obj-$(CONFIG_MACH_PALMZ72) += palmz72.o | 63 | obj-$(CONFIG_MACH_PALMZ72) += palmz72.o |
| 58 | obj-$(CONFIG_ARCH_VIPER) += viper.o | 64 | obj-$(CONFIG_ARCH_VIPER) += viper.o |
| 59 | 65 | ||
| @@ -71,6 +77,8 @@ obj-$(CONFIG_MACH_CM_X300) += cm-x300.o | |||
| 71 | obj-$(CONFIG_PXA_EZX) += ezx.o | 77 | obj-$(CONFIG_PXA_EZX) += ezx.o |
| 72 | 78 | ||
| 73 | obj-$(CONFIG_MACH_INTELMOTE2) += imote2.o | 79 | obj-$(CONFIG_MACH_INTELMOTE2) += imote2.o |
| 80 | obj-$(CONFIG_MACH_CSB726) += csb726.o | ||
| 81 | obj-$(CONFIG_CSB726_CSB701) += csb701.o | ||
| 74 | 82 | ||
| 75 | # Support for blinky lights | 83 | # Support for blinky lights |
| 76 | led-y := leds.o | 84 | led-y := leds.o |
diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c index 77ee80e5e47b..3499fada73ae 100644 --- a/arch/arm/mach-pxa/am200epd.c +++ b/arch/arm/mach-pxa/am200epd.c | |||
| @@ -30,8 +30,8 @@ | |||
| 30 | #include <linux/irq.h> | 30 | #include <linux/irq.h> |
| 31 | #include <linux/gpio.h> | 31 | #include <linux/gpio.h> |
| 32 | 32 | ||
| 33 | #include <mach/pxa25x.h> | ||
| 33 | #include <mach/gumstix.h> | 34 | #include <mach/gumstix.h> |
| 34 | #include <mach/mfp-pxa25x.h> | ||
| 35 | #include <mach/pxafb.h> | 35 | #include <mach/pxafb.h> |
| 36 | 36 | ||
| 37 | #include "generic.h" | 37 | #include "generic.h" |
diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c new file mode 100644 index 000000000000..4bd10a17332e --- /dev/null +++ b/arch/arm/mach-pxa/am300epd.c | |||
| @@ -0,0 +1,295 @@ | |||
| 1 | /* | ||
| 2 | * am300epd.c -- Platform device for AM300 EPD kit | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008, Jaya Kumar | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file COPYING in the main directory of this archive for | ||
| 8 | * more details. | ||
| 9 | * | ||
| 10 | * This work was made possible by help and equipment support from E-Ink | ||
| 11 | * Corporation. http://support.eink.com/community | ||
| 12 | * | ||
| 13 | * This driver is written to be used with the Broadsheet display controller. | ||
| 14 | * on the AM300 EPD prototype kit/development kit with an E-Ink 800x600 | ||
| 15 | * Vizplex EPD on a Gumstix board using the Broadsheet interface board. | ||
| 16 | * | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/module.h> | ||
| 20 | #include <linux/kernel.h> | ||
| 21 | #include <linux/errno.h> | ||
| 22 | #include <linux/string.h> | ||
| 23 | #include <linux/delay.h> | ||
| 24 | #include <linux/interrupt.h> | ||
| 25 | #include <linux/fb.h> | ||
| 26 | #include <linux/init.h> | ||
| 27 | #include <linux/platform_device.h> | ||
| 28 | #include <linux/irq.h> | ||
| 29 | #include <linux/gpio.h> | ||
| 30 | |||
| 31 | #include <mach/gumstix.h> | ||
| 32 | #include <mach/mfp-pxa25x.h> | ||
| 33 | #include <mach/pxafb.h> | ||
| 34 | |||
| 35 | #include "generic.h" | ||
| 36 | |||
| 37 | #include <video/broadsheetfb.h> | ||
| 38 | |||
| 39 | static unsigned int panel_type = 6; | ||
| 40 | static struct platform_device *am300_device; | ||
| 41 | static struct broadsheet_board am300_board; | ||
| 42 | |||
| 43 | static unsigned long am300_pin_config[] __initdata = { | ||
| 44 | GPIO16_GPIO, | ||
| 45 | GPIO17_GPIO, | ||
| 46 | GPIO32_GPIO, | ||
| 47 | GPIO48_GPIO, | ||
| 48 | GPIO49_GPIO, | ||
| 49 | GPIO51_GPIO, | ||
| 50 | GPIO74_GPIO, | ||
| 51 | GPIO75_GPIO, | ||
| 52 | GPIO76_GPIO, | ||
| 53 | GPIO77_GPIO, | ||
| 54 | |||
| 55 | /* this is the 16-bit hdb bus 58-73 */ | ||
| 56 | GPIO58_GPIO, | ||
| 57 | GPIO59_GPIO, | ||
| 58 | GPIO60_GPIO, | ||
| 59 | GPIO61_GPIO, | ||
| 60 | |||
| 61 | GPIO62_GPIO, | ||
| 62 | GPIO63_GPIO, | ||
| 63 | GPIO64_GPIO, | ||
| 64 | GPIO65_GPIO, | ||
| 65 | |||
| 66 | GPIO66_GPIO, | ||
| 67 | GPIO67_GPIO, | ||
| 68 | GPIO68_GPIO, | ||
| 69 | GPIO69_GPIO, | ||
| 70 | |||
| 71 | GPIO70_GPIO, | ||
| 72 | GPIO71_GPIO, | ||
| 73 | GPIO72_GPIO, | ||
| 74 | GPIO73_GPIO, | ||
| 75 | }; | ||
| 76 | |||
| 77 | /* register offsets for gpio control */ | ||
| 78 | #define PWR_GPIO_PIN 16 | ||
| 79 | #define CFG_GPIO_PIN 17 | ||
| 80 | #define RDY_GPIO_PIN 32 | ||
| 81 | #define DC_GPIO_PIN 48 | ||
| 82 | #define RST_GPIO_PIN 49 | ||
| 83 | #define LED_GPIO_PIN 51 | ||
| 84 | #define RD_GPIO_PIN 74 | ||
| 85 | #define WR_GPIO_PIN 75 | ||
| 86 | #define CS_GPIO_PIN 76 | ||
| 87 | #define IRQ_GPIO_PIN 77 | ||
| 88 | |||
| 89 | /* hdb bus */ | ||
| 90 | #define DB0_GPIO_PIN 58 | ||
| 91 | #define DB15_GPIO_PIN 73 | ||
| 92 | |||
| 93 | static int gpios[] = { PWR_GPIO_PIN, CFG_GPIO_PIN, RDY_GPIO_PIN, DC_GPIO_PIN, | ||
| 94 | RST_GPIO_PIN, RD_GPIO_PIN, WR_GPIO_PIN, CS_GPIO_PIN, | ||
| 95 | IRQ_GPIO_PIN, LED_GPIO_PIN }; | ||
| 96 | static char *gpio_names[] = { "PWR", "CFG", "RDY", "DC", "RST", "RD", "WR", | ||
| 97 | "CS", "IRQ", "LED" }; | ||
| 98 | |||
| 99 | static int am300_wait_event(struct broadsheetfb_par *par) | ||
| 100 | { | ||
| 101 | /* todo: improve err recovery */ | ||
| 102 | wait_event(par->waitq, gpio_get_value(RDY_GPIO_PIN)); | ||
| 103 | return 0; | ||
| 104 | } | ||
| 105 | |||
| 106 | static int am300_init_gpio_regs(struct broadsheetfb_par *par) | ||
| 107 | { | ||
| 108 | int i; | ||
| 109 | int err; | ||
| 110 | char dbname[8]; | ||
| 111 | |||
| 112 | for (i = 0; i < ARRAY_SIZE(gpios); i++) { | ||
| 113 | err = gpio_request(gpios[i], gpio_names[i]); | ||
| 114 | if (err) { | ||
| 115 | dev_err(&am300_device->dev, "failed requesting " | ||
| 116 | "gpio %s, err=%d\n", gpio_names[i], err); | ||
| 117 | goto err_req_gpio; | ||
| 118 | } | ||
| 119 | } | ||
| 120 | |||
| 121 | /* we also need to take care of the hdb bus */ | ||
| 122 | for (i = DB0_GPIO_PIN; i <= DB15_GPIO_PIN; i++) { | ||
| 123 | sprintf(dbname, "DB%d", i); | ||
| 124 | err = gpio_request(i, dbname); | ||
| 125 | if (err) { | ||
| 126 | dev_err(&am300_device->dev, "failed requesting " | ||
| 127 | "gpio %d, err=%d\n", i, err); | ||
| 128 | while (i >= DB0_GPIO_PIN) | ||
| 129 | gpio_free(i--); | ||
| 130 | i = ARRAY_SIZE(gpios) - 1; | ||
| 131 | goto err_req_gpio; | ||
| 132 | } | ||
| 133 | } | ||
| 134 | |||
| 135 | /* setup the outputs and init values */ | ||
| 136 | gpio_direction_output(PWR_GPIO_PIN, 0); | ||
| 137 | gpio_direction_output(CFG_GPIO_PIN, 1); | ||
| 138 | gpio_direction_output(DC_GPIO_PIN, 0); | ||
| 139 | gpio_direction_output(RD_GPIO_PIN, 1); | ||
| 140 | gpio_direction_output(WR_GPIO_PIN, 1); | ||
| 141 | gpio_direction_output(CS_GPIO_PIN, 1); | ||
| 142 | gpio_direction_output(RST_GPIO_PIN, 0); | ||
| 143 | |||
| 144 | /* setup the inputs */ | ||
| 145 | gpio_direction_input(RDY_GPIO_PIN); | ||
| 146 | gpio_direction_input(IRQ_GPIO_PIN); | ||
| 147 | |||
| 148 | /* start the hdb bus as an input */ | ||
| 149 | for (i = DB0_GPIO_PIN; i <= DB15_GPIO_PIN; i++) | ||
| 150 | gpio_direction_output(i, 0); | ||
| 151 | |||
| 152 | /* go into command mode */ | ||
| 153 | gpio_set_value(CFG_GPIO_PIN, 1); | ||
| 154 | gpio_set_value(RST_GPIO_PIN, 0); | ||
| 155 | msleep(10); | ||
| 156 | gpio_set_value(RST_GPIO_PIN, 1); | ||
| 157 | msleep(10); | ||
| 158 | am300_wait_event(par); | ||
| 159 | |||
| 160 | return 0; | ||
| 161 | |||
| 162 | err_req_gpio: | ||
| 163 | while (i > 0) | ||
| 164 | gpio_free(gpios[i--]); | ||
| 165 | |||
| 166 | return err; | ||
| 167 | } | ||
| 168 | |||
| 169 | static int am300_init_board(struct broadsheetfb_par *par) | ||
| 170 | { | ||
| 171 | return am300_init_gpio_regs(par); | ||
| 172 | } | ||
| 173 | |||
| 174 | static void am300_cleanup(struct broadsheetfb_par *par) | ||
| 175 | { | ||
| 176 | int i; | ||
| 177 | |||
| 178 | free_irq(IRQ_GPIO(RDY_GPIO_PIN), par); | ||
| 179 | |||
| 180 | for (i = 0; i < ARRAY_SIZE(gpios); i++) | ||
| 181 | gpio_free(gpios[i]); | ||
| 182 | |||
| 183 | for (i = DB0_GPIO_PIN; i <= DB15_GPIO_PIN; i++) | ||
| 184 | gpio_free(i); | ||
| 185 | |||
| 186 | } | ||
| 187 | |||
| 188 | static u16 am300_get_hdb(struct broadsheetfb_par *par) | ||
| 189 | { | ||
| 190 | u16 res = 0; | ||
| 191 | int i; | ||
| 192 | |||
| 193 | for (i = 0; i <= (DB15_GPIO_PIN - DB0_GPIO_PIN) ; i++) | ||
| 194 | res |= (gpio_get_value(DB0_GPIO_PIN + i)) ? (1 << i) : 0; | ||
| 195 | |||
| 196 | return res; | ||
| 197 | } | ||
| 198 | |||
| 199 | static void am300_set_hdb(struct broadsheetfb_par *par, u16 data) | ||
| 200 | { | ||
| 201 | int i; | ||
| 202 | |||
| 203 | for (i = 0; i <= (DB15_GPIO_PIN - DB0_GPIO_PIN) ; i++) | ||
| 204 | gpio_set_value(DB0_GPIO_PIN + i, (data >> i) & 0x01); | ||
| 205 | } | ||
| 206 | |||
| 207 | |||
| 208 | static void am300_set_ctl(struct broadsheetfb_par *par, unsigned char bit, | ||
| 209 | u8 state) | ||
| 210 | { | ||
| 211 | switch (bit) { | ||
| 212 | case BS_CS: | ||
| 213 | gpio_set_value(CS_GPIO_PIN, state); | ||
| 214 | break; | ||
| 215 | case BS_DC: | ||
| 216 | gpio_set_value(DC_GPIO_PIN, state); | ||
| 217 | break; | ||
| 218 | case BS_WR: | ||
| 219 | gpio_set_value(WR_GPIO_PIN, state); | ||
| 220 | break; | ||
| 221 | } | ||
| 222 | } | ||
| 223 | |||
| 224 | static int am300_get_panel_type(void) | ||
| 225 | { | ||
| 226 | return panel_type; | ||
| 227 | } | ||
| 228 | |||
| 229 | static irqreturn_t am300_handle_irq(int irq, void *dev_id) | ||
| 230 | { | ||
| 231 | struct broadsheetfb_par *par = dev_id; | ||
| 232 | |||
| 233 | wake_up(&par->waitq); | ||
| 234 | return IRQ_HANDLED; | ||
| 235 | } | ||
| 236 | |||
| 237 | static int am300_setup_irq(struct fb_info *info) | ||
| 238 | { | ||
| 239 | int ret; | ||
| 240 | struct broadsheetfb_par *par = info->par; | ||
| 241 | |||
| 242 | ret = request_irq(IRQ_GPIO(RDY_GPIO_PIN), am300_handle_irq, | ||
| 243 | IRQF_DISABLED|IRQF_TRIGGER_RISING, | ||
| 244 | "AM300", par); | ||
| 245 | if (ret) | ||
| 246 | dev_err(&am300_device->dev, "request_irq failed: %d\n", ret); | ||
| 247 | |||
| 248 | return ret; | ||
| 249 | } | ||
| 250 | |||
| 251 | static struct broadsheet_board am300_board = { | ||
| 252 | .owner = THIS_MODULE, | ||
| 253 | .init = am300_init_board, | ||
| 254 | .cleanup = am300_cleanup, | ||
| 255 | .set_hdb = am300_set_hdb, | ||
| 256 | .get_hdb = am300_get_hdb, | ||
| 257 | .set_ctl = am300_set_ctl, | ||
| 258 | .wait_for_rdy = am300_wait_event, | ||
| 259 | .get_panel_type = am300_get_panel_type, | ||
| 260 | .setup_irq = am300_setup_irq, | ||
| 261 | }; | ||
| 262 | |||
| 263 | int __init am300_init(void) | ||
| 264 | { | ||
| 265 | int ret; | ||
| 266 | |||
| 267 | pxa2xx_mfp_config(ARRAY_AND_SIZE(am300_pin_config)); | ||
| 268 | |||
| 269 | /* request our platform independent driver */ | ||
| 270 | request_module("broadsheetfb"); | ||
| 271 | |||
| 272 | am300_device = platform_device_alloc("broadsheetfb", -1); | ||
| 273 | if (!am300_device) | ||
| 274 | return -ENOMEM; | ||
| 275 | |||
| 276 | /* the am300_board that will be seen by broadsheetfb is a copy */ | ||
| 277 | platform_device_add_data(am300_device, &am300_board, | ||
| 278 | sizeof(am300_board)); | ||
| 279 | |||
| 280 | ret = platform_device_add(am300_device); | ||
| 281 | |||
| 282 | if (ret) { | ||
| 283 | platform_device_put(am300_device); | ||
| 284 | return ret; | ||
| 285 | } | ||
| 286 | |||
| 287 | return 0; | ||
| 288 | } | ||
| 289 | |||
| 290 | module_param(panel_type, uint, 0); | ||
| 291 | MODULE_PARM_DESC(panel_type, "Select the panel type: 6, 8, 97"); | ||
| 292 | |||
| 293 | MODULE_DESCRIPTION("board driver for am300 epd kit"); | ||
| 294 | MODULE_AUTHOR("Jaya Kumar"); | ||
| 295 | MODULE_LICENSE("GPL"); | ||
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c index 40b774084514..db52d2c4791d 100644 --- a/arch/arm/mach-pxa/clock.c +++ b/arch/arm/mach-pxa/clock.c | |||
| @@ -87,7 +87,7 @@ void clks_register(struct clk_lookup *clks, size_t num) | |||
| 87 | clkdev_add(&clks[i]); | 87 | clkdev_add(&clks[i]); |
| 88 | } | 88 | } |
| 89 | 89 | ||
| 90 | int clk_add_alias(char *alias, struct device *alias_dev, char *id, | 90 | int clk_add_alias(const char *alias, const char *alias_dev_name, char *id, |
| 91 | struct device *dev) | 91 | struct device *dev) |
| 92 | { | 92 | { |
| 93 | struct clk *r = clk_get(dev, id); | 93 | struct clk *r = clk_get(dev, id); |
| @@ -96,7 +96,7 @@ int clk_add_alias(char *alias, struct device *alias_dev, char *id, | |||
| 96 | if (!r) | 96 | if (!r) |
| 97 | return -ENODEV; | 97 | return -ENODEV; |
| 98 | 98 | ||
| 99 | l = clkdev_alloc(r, alias, alias_dev ? dev_name(alias_dev) : NULL); | 99 | l = clkdev_alloc(r, alias, alias_dev_name); |
| 100 | clk_put(r); | 100 | clk_put(r); |
| 101 | if (!l) | 101 | if (!l) |
| 102 | return -ENODEV; | 102 | return -ENODEV; |
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h index 4e9c613c6767..5599bceff738 100644 --- a/arch/arm/mach-pxa/clock.h +++ b/arch/arm/mach-pxa/clock.h | |||
| @@ -69,6 +69,6 @@ extern void clk_pxa3xx_cken_disable(struct clk *); | |||
| 69 | #endif | 69 | #endif |
| 70 | 70 | ||
| 71 | void clks_register(struct clk_lookup *clks, size_t num); | 71 | void clks_register(struct clk_lookup *clks, size_t num); |
| 72 | int clk_add_alias(char *alias, struct device *alias_dev, char *id, | 72 | int clk_add_alias(const char *alias, const char *alias_name, char *id, |
| 73 | struct device *dev); | 73 | struct device *dev); |
| 74 | 74 | ||
diff --git a/arch/arm/mach-pxa/cm-x255.c b/arch/arm/mach-pxa/cm-x255.c index 83a4cdf08176..253fd76142d6 100644 --- a/arch/arm/mach-pxa/cm-x255.c +++ b/arch/arm/mach-pxa/cm-x255.c | |||
| @@ -22,10 +22,8 @@ | |||
| 22 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
| 23 | #include <asm/mach/map.h> | 23 | #include <asm/mach/map.h> |
| 24 | 24 | ||
| 25 | #include <mach/pxa2xx-regs.h> | 25 | #include <mach/pxa25x.h> |
| 26 | #include <mach/mfp-pxa25x.h> | ||
| 27 | #include <mach/pxa2xx_spi.h> | 26 | #include <mach/pxa2xx_spi.h> |
| 28 | #include <mach/bitfield.h> | ||
| 29 | 27 | ||
| 30 | #include "generic.h" | 28 | #include "generic.h" |
| 31 | 29 | ||
diff --git a/arch/arm/mach-pxa/cm-x270.c b/arch/arm/mach-pxa/cm-x270.c index df83b97f303f..34576ba5f5fd 100644 --- a/arch/arm/mach-pxa/cm-x270.c +++ b/arch/arm/mach-pxa/cm-x270.c | |||
| @@ -17,7 +17,7 @@ | |||
| 17 | #include <linux/rtc-v3020.h> | 17 | #include <linux/rtc-v3020.h> |
| 18 | #include <video/mbxfb.h> | 18 | #include <video/mbxfb.h> |
| 19 | 19 | ||
| 20 | #include <mach/mfp-pxa27x.h> | 20 | #include <mach/pxa27x.h> |
| 21 | #include <mach/ohci.h> | 21 | #include <mach/ohci.h> |
| 22 | #include <mach/mmc.h> | 22 | #include <mach/mmc.h> |
| 23 | 23 | ||
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c index 3156b25f6e9d..7873fa3d8fa4 100644 --- a/arch/arm/mach-pxa/cm-x2xx-pci.c +++ b/arch/arm/mach-pxa/cm-x2xx-pci.c | |||
| @@ -22,7 +22,6 @@ | |||
| 22 | #include <linux/gpio.h> | 22 | #include <linux/gpio.h> |
| 23 | 23 | ||
| 24 | #include <asm/mach/pci.h> | 24 | #include <asm/mach/pci.h> |
| 25 | #include <mach/pxa-regs.h> | ||
| 26 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
| 27 | 26 | ||
| 28 | #include <asm/hardware/it8152.h> | 27 | #include <asm/hardware/it8152.h> |
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c index d99fd9e4d888..117b5435f8d5 100644 --- a/arch/arm/mach-pxa/cm-x2xx.c +++ b/arch/arm/mach-pxa/cm-x2xx.c | |||
| @@ -22,8 +22,6 @@ | |||
| 22 | #include <asm/mach/map.h> | 22 | #include <asm/mach/map.h> |
| 23 | 23 | ||
| 24 | #include <mach/pxa2xx-regs.h> | 24 | #include <mach/pxa2xx-regs.h> |
| 25 | #include <mach/mfp-pxa27x.h> | ||
| 26 | #include <mach/pxa-regs.h> | ||
| 27 | #include <mach/audio.h> | 25 | #include <mach/audio.h> |
| 28 | #include <mach/pxafb.h> | 26 | #include <mach/pxafb.h> |
| 29 | 27 | ||
| @@ -96,7 +94,7 @@ static struct resource cmx270_dm9000_resource[] = { | |||
| 96 | }; | 94 | }; |
| 97 | 95 | ||
| 98 | static struct dm9000_plat_data cmx270_dm9000_platdata = { | 96 | static struct dm9000_plat_data cmx270_dm9000_platdata = { |
| 99 | .flags = DM9000_PLATF_32BITONLY, | 97 | .flags = DM9000_PLATF_32BITONLY | DM9000_PLATF_NO_EEPROM, |
| 100 | }; | 98 | }; |
| 101 | 99 | ||
| 102 | static struct platform_device cmx2xx_dm9000_device = { | 100 | static struct platform_device cmx2xx_dm9000_device = { |
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c index ff0c577cd1ac..a9f48b1cb54a 100644 --- a/arch/arm/mach-pxa/cm-x300.c +++ b/arch/arm/mach-pxa/cm-x300.c | |||
| @@ -28,9 +28,7 @@ | |||
| 28 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 29 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
| 30 | 30 | ||
| 31 | #include <mach/mfp-pxa300.h> | 31 | #include <mach/pxa300.h> |
| 32 | |||
| 33 | #include <mach/hardware.h> | ||
| 34 | #include <mach/pxafb.h> | 32 | #include <mach/pxafb.h> |
| 35 | #include <mach/mmc.h> | 33 | #include <mach/mmc.h> |
| 36 | #include <mach/ohci.h> | 34 | #include <mach/ohci.h> |
| @@ -162,7 +160,7 @@ static struct resource dm9000_resources[] = { | |||
| 162 | }; | 160 | }; |
| 163 | 161 | ||
| 164 | static struct dm9000_plat_data cm_x300_dm9000_platdata = { | 162 | static struct dm9000_plat_data cm_x300_dm9000_platdata = { |
| 165 | .flags = DM9000_PLATF_16BITONLY, | 163 | .flags = DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM, |
| 166 | }; | 164 | }; |
| 167 | 165 | ||
| 168 | static struct platform_device dm9000_device = { | 166 | static struct platform_device dm9000_device = { |
diff --git a/arch/arm/mach-pxa/colibri.c b/arch/arm/mach-pxa/colibri-pxa270.c index e8473624427e..01bcfaae75bc 100644 --- a/arch/arm/mach-pxa/colibri.c +++ b/arch/arm/mach-pxa/colibri-pxa270.c | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-pxa/colibri.c | 2 | * linux/arch/arm/mach-pxa/colibri-pxa270.c |
| 3 | * | 3 | * |
| 4 | * Support for Toradex PXA27x based Colibri module | 4 | * Support for Toradex PXA270 based Colibri module |
| 5 | * Daniel Mack <daniel@caiaq.de> | 5 | * Daniel Mack <daniel@caiaq.de> |
| 6 | * | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
| @@ -20,6 +20,7 @@ | |||
| 20 | #include <linux/mtd/mtd.h> | 20 | #include <linux/mtd/mtd.h> |
| 21 | #include <linux/mtd/partitions.h> | 21 | #include <linux/mtd/partitions.h> |
| 22 | #include <linux/mtd/physmap.h> | 22 | #include <linux/mtd/physmap.h> |
| 23 | #include <linux/gpio.h> | ||
| 23 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
| 24 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
| 25 | #include <asm/irq.h> | 26 | #include <asm/irq.h> |
| @@ -28,20 +29,23 @@ | |||
| 28 | #include <asm/mach/map.h> | 29 | #include <asm/mach/map.h> |
| 29 | #include <asm/mach/irq.h> | 30 | #include <asm/mach/irq.h> |
| 30 | #include <asm/mach/flash.h> | 31 | #include <asm/mach/flash.h> |
| 31 | #include <mach/pxa-regs.h> | 32 | |
| 32 | #include <mach/mfp-pxa27x.h> | 33 | #include <mach/pxa27x.h> |
| 33 | #include <mach/colibri.h> | 34 | #include <mach/colibri.h> |
| 34 | 35 | ||
| 35 | #include "generic.h" | 36 | #include "generic.h" |
| 36 | #include "devices.h" | 37 | #include "devices.h" |
| 37 | 38 | ||
| 38 | static unsigned long colibri_pin_config[] __initdata = { | 39 | /* |
| 40 | * GPIO configuration | ||
| 41 | */ | ||
| 42 | static mfp_cfg_t colibri_pxa270_pin_config[] __initdata = { | ||
| 39 | GPIO78_nCS_2, /* Ethernet CS */ | 43 | GPIO78_nCS_2, /* Ethernet CS */ |
| 40 | GPIO114_GPIO, /* Ethernet IRQ */ | 44 | GPIO114_GPIO, /* Ethernet IRQ */ |
| 41 | }; | 45 | }; |
| 42 | 46 | ||
| 43 | /* | 47 | /* |
| 44 | * Flash | 48 | * NOR flash |
| 45 | */ | 49 | */ |
| 46 | static struct mtd_partition colibri_partitions[] = { | 50 | static struct mtd_partition colibri_partitions[] = { |
| 47 | { | 51 | { |
| @@ -70,39 +74,40 @@ static struct physmap_flash_data colibri_flash_data[] = { | |||
| 70 | } | 74 | } |
| 71 | }; | 75 | }; |
| 72 | 76 | ||
| 73 | static struct resource flash_resource = { | 77 | static struct resource colibri_pxa270_flash_resource = { |
| 74 | .start = PXA_CS0_PHYS, | 78 | .start = PXA_CS0_PHYS, |
| 75 | .end = PXA_CS0_PHYS + SZ_32M - 1, | 79 | .end = PXA_CS0_PHYS + SZ_32M - 1, |
| 76 | .flags = IORESOURCE_MEM, | 80 | .flags = IORESOURCE_MEM, |
| 77 | }; | 81 | }; |
| 78 | 82 | ||
| 79 | static struct platform_device flash_device = { | 83 | static struct platform_device colibri_pxa270_flash_device = { |
| 80 | .name = "physmap-flash", | 84 | .name = "physmap-flash", |
| 81 | .id = 0, | 85 | .id = 0, |
| 82 | .dev = { | 86 | .dev = { |
| 83 | .platform_data = colibri_flash_data, | 87 | .platform_data = colibri_flash_data, |
| 84 | }, | 88 | }, |
| 85 | .resource = &flash_resource, | 89 | .resource = &colibri_pxa270_flash_resource, |
| 86 | .num_resources = 1, | 90 | .num_resources = 1, |
| 87 | }; | 91 | }; |
| 88 | 92 | ||
| 89 | /* | 93 | /* |
| 90 | * DM9000 Ethernet | 94 | * DM9000 Ethernet |
| 91 | */ | 95 | */ |
| 96 | #if defined(CONFIG_DM9000) | ||
| 92 | static struct resource dm9000_resources[] = { | 97 | static struct resource dm9000_resources[] = { |
| 93 | [0] = { | 98 | [0] = { |
| 94 | .start = COLIBRI_ETH_PHYS, | 99 | .start = COLIBRI_PXA270_ETH_PHYS, |
| 95 | .end = COLIBRI_ETH_PHYS + 3, | 100 | .end = COLIBRI_PXA270_ETH_PHYS + 3, |
| 96 | .flags = IORESOURCE_MEM, | 101 | .flags = IORESOURCE_MEM, |
| 97 | }, | 102 | }, |
| 98 | [1] = { | 103 | [1] = { |
| 99 | .start = COLIBRI_ETH_PHYS + 4, | 104 | .start = COLIBRI_PXA270_ETH_PHYS + 4, |
| 100 | .end = COLIBRI_ETH_PHYS + 4 + 500, | 105 | .end = COLIBRI_PXA270_ETH_PHYS + 4 + 500, |
| 101 | .flags = IORESOURCE_MEM, | 106 | .flags = IORESOURCE_MEM, |
| 102 | }, | 107 | }, |
| 103 | [2] = { | 108 | [2] = { |
| 104 | .start = COLIBRI_ETH_IRQ, | 109 | .start = COLIBRI_PXA270_ETH_IRQ, |
| 105 | .end = COLIBRI_ETH_IRQ, | 110 | .end = COLIBRI_PXA270_ETH_IRQ, |
| 106 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING, | 111 | .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING, |
| 107 | }, | 112 | }, |
| 108 | }; | 113 | }; |
| @@ -113,25 +118,28 @@ static struct platform_device dm9000_device = { | |||
| 113 | .num_resources = ARRAY_SIZE(dm9000_resources), | 118 | .num_resources = ARRAY_SIZE(dm9000_resources), |
| 114 | .resource = dm9000_resources, | 119 | .resource = dm9000_resources, |
| 115 | }; | 120 | }; |
| 121 | #endif /* CONFIG_DM9000 */ | ||
| 116 | 122 | ||
| 117 | static struct platform_device *colibri_devices[] __initdata = { | 123 | static struct platform_device *colibri_pxa270_devices[] __initdata = { |
| 118 | &flash_device, | 124 | &colibri_pxa270_flash_device, |
| 125 | #if defined(CONFIG_DM9000) | ||
| 119 | &dm9000_device, | 126 | &dm9000_device, |
| 127 | #endif | ||
| 120 | }; | 128 | }; |
| 121 | 129 | ||
| 122 | static void __init colibri_init(void) | 130 | static void __init colibri_pxa270_init(void) |
| 123 | { | 131 | { |
| 124 | pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pin_config)); | 132 | pxa2xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa270_pin_config)); |
| 125 | 133 | platform_add_devices(ARRAY_AND_SIZE(colibri_pxa270_devices)); | |
| 126 | platform_add_devices(colibri_devices, ARRAY_SIZE(colibri_devices)); | ||
| 127 | } | 134 | } |
| 128 | 135 | ||
| 129 | MACHINE_START(COLIBRI, "Toradex Colibri PXA27x") | 136 | MACHINE_START(COLIBRI, "Toradex Colibri PXA270") |
| 130 | .phys_io = 0x40000000, | 137 | .phys_io = 0x40000000, |
| 131 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | 138 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, |
| 132 | .boot_params = COLIBRI_SDRAM_BASE + 0x100, | 139 | .boot_params = COLIBRI_SDRAM_BASE + 0x100, |
| 133 | .init_machine = colibri_init, | 140 | .init_machine = colibri_pxa270_init, |
| 134 | .map_io = pxa_map_io, | 141 | .map_io = pxa_map_io, |
| 135 | .init_irq = pxa27x_init_irq, | 142 | .init_irq = pxa27x_init_irq, |
| 136 | .timer = &pxa_timer, | 143 | .timer = &pxa_timer, |
| 137 | MACHINE_END | 144 | MACHINE_END |
| 145 | |||
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c new file mode 100644 index 000000000000..169ab552c21a --- /dev/null +++ b/arch/arm/mach-pxa/colibri-pxa300.c | |||
| @@ -0,0 +1,190 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-pxa/colibri-pxa300.c | ||
| 3 | * | ||
| 4 | * Support for Toradex PXA300/310 based Colibri module | ||
| 5 | * | ||
| 6 | * Daniel Mack <daniel@caiaq.de> | ||
| 7 | * Matthias Meier <matthias.j.meier@gmx.net> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/gpio.h> | ||
| 18 | #include <net/ax88796.h> | ||
| 19 | |||
| 20 | #include <asm/mach-types.h> | ||
| 21 | #include <asm/sizes.h> | ||
| 22 | #include <asm/mach/arch.h> | ||
| 23 | #include <asm/mach/irq.h> | ||
| 24 | |||
| 25 | #include <mach/pxa300.h> | ||
| 26 | #include <mach/colibri.h> | ||
| 27 | #include <mach/ohci.h> | ||
| 28 | #include <mach/pxafb.h> | ||
| 29 | |||
| 30 | #include "generic.h" | ||
| 31 | #include "devices.h" | ||
| 32 | |||
| 33 | #if defined(CONFIG_AX88796) | ||
| 34 | #define COLIBRI_ETH_IRQ_GPIO mfp_to_gpio(GPIO26_GPIO) | ||
| 35 | /* | ||
| 36 | * Asix AX88796 Ethernet | ||
| 37 | */ | ||
| 38 | static struct ax_plat_data colibri_asix_platdata = { | ||
| 39 | .flags = AXFLG_MAC_FROMDEV, | ||
| 40 | .wordlength = 2 | ||
| 41 | }; | ||
| 42 | |||
| 43 | static struct resource colibri_asix_resource[] = { | ||
| 44 | [0] = { | ||
| 45 | .start = PXA3xx_CS2_PHYS, | ||
| 46 | .end = PXA3xx_CS2_PHYS + (0x20 * 2) - 1, | ||
| 47 | .flags = IORESOURCE_MEM, | ||
| 48 | }, | ||
| 49 | [1] = { | ||
| 50 | .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), | ||
| 51 | .end = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), | ||
| 52 | .flags = IORESOURCE_IRQ | ||
| 53 | } | ||
| 54 | }; | ||
| 55 | |||
| 56 | static struct platform_device asix_device = { | ||
| 57 | .name = "ax88796", | ||
| 58 | .id = 0, | ||
| 59 | .num_resources = ARRAY_SIZE(colibri_asix_resource), | ||
| 60 | .resource = colibri_asix_resource, | ||
| 61 | .dev = { | ||
| 62 | .platform_data = &colibri_asix_platdata | ||
| 63 | } | ||
| 64 | }; | ||
| 65 | |||
| 66 | static mfp_cfg_t colibri_pxa300_eth_pin_config[] __initdata = { | ||
| 67 | GPIO1_nCS2, /* AX88796 chip select */ | ||
| 68 | GPIO26_GPIO | MFP_PULL_HIGH /* AX88796 IRQ */ | ||
| 69 | }; | ||
| 70 | |||
| 71 | static void __init colibri_pxa300_init_eth(void) | ||
| 72 | { | ||
| 73 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_eth_pin_config)); | ||
| 74 | set_irq_type(gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), IRQ_TYPE_EDGE_FALLING); | ||
| 75 | platform_device_register(&asix_device); | ||
| 76 | } | ||
| 77 | #else | ||
| 78 | static inline void __init colibri_pxa300_init_eth(void) {} | ||
| 79 | #endif /* CONFIG_AX88796 */ | ||
| 80 | |||
| 81 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 82 | static mfp_cfg_t colibri_pxa300_usb_pin_config[] __initdata = { | ||
| 83 | GPIO0_2_USBH_PEN, | ||
| 84 | GPIO1_2_USBH_PWR, | ||
| 85 | }; | ||
| 86 | |||
| 87 | static struct pxaohci_platform_data colibri_pxa300_ohci_info = { | ||
| 88 | .port_mode = PMM_GLOBAL_MODE, | ||
| 89 | .flags = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW, | ||
| 90 | }; | ||
| 91 | |||
| 92 | void __init colibri_pxa300_init_ohci(void) | ||
| 93 | { | ||
| 94 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_usb_pin_config)); | ||
| 95 | pxa_set_ohci_info(&colibri_pxa300_ohci_info); | ||
| 96 | } | ||
| 97 | #else | ||
| 98 | static inline void colibri_pxa300_init_ohci(void) {} | ||
| 99 | #endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */ | ||
| 100 | |||
| 101 | static mfp_cfg_t colibri_pxa300_mmc_pin_config[] __initdata = { | ||
| 102 | GPIO7_MMC1_CLK, | ||
| 103 | GPIO14_MMC1_CMD, | ||
| 104 | GPIO3_MMC1_DAT0, | ||
| 105 | GPIO4_MMC1_DAT1, | ||
| 106 | GPIO5_MMC1_DAT2, | ||
| 107 | GPIO6_MMC1_DAT3, | ||
| 108 | }; | ||
| 109 | |||
| 110 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) | ||
| 111 | static mfp_cfg_t colibri_pxa300_lcd_pin_config[] __initdata = { | ||
| 112 | GPIO54_LCD_LDD_0, | ||
| 113 | GPIO55_LCD_LDD_1, | ||
| 114 | GPIO56_LCD_LDD_2, | ||
| 115 | GPIO57_LCD_LDD_3, | ||
| 116 | GPIO58_LCD_LDD_4, | ||
| 117 | GPIO59_LCD_LDD_5, | ||
| 118 | GPIO60_LCD_LDD_6, | ||
| 119 | GPIO61_LCD_LDD_7, | ||
| 120 | GPIO62_LCD_LDD_8, | ||
| 121 | GPIO63_LCD_LDD_9, | ||
| 122 | GPIO64_LCD_LDD_10, | ||
| 123 | GPIO65_LCD_LDD_11, | ||
| 124 | GPIO66_LCD_LDD_12, | ||
| 125 | GPIO67_LCD_LDD_13, | ||
| 126 | GPIO68_LCD_LDD_14, | ||
| 127 | GPIO69_LCD_LDD_15, | ||
| 128 | GPIO70_LCD_LDD_16, | ||
| 129 | GPIO71_LCD_LDD_17, | ||
| 130 | GPIO62_LCD_CS_N, | ||
| 131 | GPIO72_LCD_FCLK, | ||
| 132 | GPIO73_LCD_LCLK, | ||
| 133 | GPIO74_LCD_PCLK, | ||
| 134 | GPIO75_LCD_BIAS, | ||
| 135 | GPIO76_LCD_VSYNC, | ||
| 136 | }; | ||
| 137 | |||
| 138 | static void __init colibri_pxa300_init_lcd(void) | ||
| 139 | { | ||
| 140 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa300_lcd_pin_config)); | ||
| 141 | } | ||
| 142 | |||
| 143 | #else | ||
| 144 | static inline void colibri_pxa300_init_lcd(void) {} | ||
| 145 | #endif /* CONFIG_FB_PXA || CONFIG_FB_PXA_MODULE */ | ||
| 146 | |||
| 147 | #if defined(SND_AC97_CODEC) || defined(SND_AC97_CODEC_MODULE) | ||
| 148 | static mfp_cfg_t colibri_pxa310_ac97_pin_config[] __initdata = { | ||
| 149 | GPIO24_AC97_SYSCLK, | ||
| 150 | GPIO23_AC97_nACRESET, | ||
| 151 | GPIO25_AC97_SDATA_IN_0, | ||
| 152 | GPIO27_AC97_SDATA_OUT, | ||
| 153 | GPIO28_AC97_SYNC, | ||
| 154 | GPIO29_AC97_BITCLK | ||
| 155 | }; | ||
| 156 | |||
| 157 | static inline void __init colibri_pxa310_init_ac97(void) | ||
| 158 | { | ||
| 159 | /* no AC97 codec on Colibri PXA300 */ | ||
| 160 | if (!cpu_is_pxa310()) | ||
| 161 | return; | ||
| 162 | |||
| 163 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa310_ac97_pin_config)); | ||
| 164 | pxa_set_ac97_info(NULL); | ||
| 165 | } | ||
| 166 | #else | ||
| 167 | static inline void colibri_pxa310_init_ac97(void) {} | ||
| 168 | #endif | ||
| 169 | |||
| 170 | void __init colibri_pxa300_init(void) | ||
| 171 | { | ||
| 172 | colibri_pxa300_init_eth(); | ||
| 173 | colibri_pxa300_init_ohci(); | ||
| 174 | colibri_pxa300_init_lcd(); | ||
| 175 | colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO49_GPIO)); | ||
| 176 | colibri_pxa310_init_ac97(); | ||
| 177 | colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa300_mmc_pin_config), | ||
| 178 | mfp_to_gpio(MFP_PIN_GPIO13)); | ||
| 179 | } | ||
| 180 | |||
| 181 | MACHINE_START(COLIBRI300, "Toradex Colibri PXA300") | ||
| 182 | .phys_io = 0x40000000, | ||
| 183 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 184 | .boot_params = COLIBRI_SDRAM_BASE + 0x100, | ||
| 185 | .init_machine = colibri_pxa300_init, | ||
| 186 | .map_io = pxa_map_io, | ||
| 187 | .init_irq = pxa3xx_init_irq, | ||
| 188 | .timer = &pxa_timer, | ||
| 189 | MACHINE_END | ||
| 190 | |||
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c new file mode 100644 index 000000000000..573a9a1dd529 --- /dev/null +++ b/arch/arm/mach-pxa/colibri-pxa320.c | |||
| @@ -0,0 +1,187 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-pxa/colibri-pxa320.c | ||
| 3 | * | ||
| 4 | * Support for Toradex PXA320/310 based Colibri module | ||
| 5 | * | ||
| 6 | * Daniel Mack <daniel@caiaq.de> | ||
| 7 | * Matthias Meier <matthias.j.meier@gmx.net> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/platform_device.h> | ||
| 17 | #include <linux/gpio.h> | ||
| 18 | #include <net/ax88796.h> | ||
| 19 | |||
| 20 | #include <asm/mach-types.h> | ||
| 21 | #include <asm/sizes.h> | ||
| 22 | #include <asm/mach/arch.h> | ||
| 23 | #include <asm/mach/irq.h> | ||
| 24 | |||
| 25 | #include <mach/pxa3xx-regs.h> | ||
| 26 | #include <mach/mfp-pxa320.h> | ||
| 27 | #include <mach/colibri.h> | ||
| 28 | #include <mach/pxafb.h> | ||
| 29 | #include <mach/ohci.h> | ||
| 30 | |||
| 31 | #include "generic.h" | ||
| 32 | #include "devices.h" | ||
| 33 | |||
| 34 | #if defined(CONFIG_AX88796) | ||
| 35 | #define COLIBRI_ETH_IRQ_GPIO mfp_to_gpio(GPIO36_GPIO) | ||
| 36 | |||
| 37 | /* | ||
| 38 | * Asix AX88796 Ethernet | ||
| 39 | */ | ||
| 40 | static struct ax_plat_data colibri_asix_platdata = { | ||
| 41 | .flags = AXFLG_MAC_FROMDEV, | ||
| 42 | .wordlength = 2 | ||
| 43 | }; | ||
| 44 | |||
| 45 | static struct resource colibri_asix_resource[] = { | ||
| 46 | [0] = { | ||
| 47 | .start = PXA3xx_CS2_PHYS, | ||
| 48 | .end = PXA3xx_CS2_PHYS + (0x20 * 2) - 1, | ||
| 49 | .flags = IORESOURCE_MEM, | ||
| 50 | }, | ||
| 51 | [1] = { | ||
| 52 | .start = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), | ||
| 53 | .end = gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), | ||
| 54 | .flags = IORESOURCE_IRQ | ||
| 55 | } | ||
| 56 | }; | ||
| 57 | |||
| 58 | static struct platform_device asix_device = { | ||
| 59 | .name = "ax88796", | ||
| 60 | .id = 0, | ||
| 61 | .num_resources = ARRAY_SIZE(colibri_asix_resource), | ||
| 62 | .resource = colibri_asix_resource, | ||
| 63 | .dev = { | ||
| 64 | .platform_data = &colibri_asix_platdata | ||
| 65 | } | ||
| 66 | }; | ||
| 67 | |||
| 68 | static mfp_cfg_t colibri_pxa320_eth_pin_config[] __initdata = { | ||
| 69 | GPIO3_nCS2, /* AX88796 chip select */ | ||
| 70 | GPIO36_GPIO | MFP_PULL_HIGH /* AX88796 IRQ */ | ||
| 71 | }; | ||
| 72 | |||
| 73 | static void __init colibri_pxa320_init_eth(void) | ||
| 74 | { | ||
| 75 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_eth_pin_config)); | ||
| 76 | set_irq_type(gpio_to_irq(COLIBRI_ETH_IRQ_GPIO), IRQ_TYPE_EDGE_FALLING); | ||
| 77 | platform_device_register(&asix_device); | ||
| 78 | } | ||
| 79 | #else | ||
| 80 | static inline void __init colibri_pxa320_init_eth(void) {} | ||
| 81 | #endif /* CONFIG_AX88796 */ | ||
| 82 | |||
| 83 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | ||
| 84 | static mfp_cfg_t colibri_pxa320_usb_pin_config[] __initdata = { | ||
| 85 | GPIO2_2_USBH_PEN, | ||
| 86 | GPIO3_2_USBH_PWR, | ||
| 87 | }; | ||
| 88 | |||
| 89 | static struct pxaohci_platform_data colibri_pxa320_ohci_info = { | ||
| 90 | .port_mode = PMM_GLOBAL_MODE, | ||
| 91 | .flags = ENABLE_PORT1 | POWER_CONTROL_LOW | POWER_SENSE_LOW, | ||
| 92 | }; | ||
| 93 | |||
| 94 | void __init colibri_pxa320_init_ohci(void) | ||
| 95 | { | ||
| 96 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_usb_pin_config)); | ||
| 97 | pxa_set_ohci_info(&colibri_pxa320_ohci_info); | ||
| 98 | } | ||
| 99 | #else | ||
| 100 | static inline void colibri_pxa320_init_ohci(void) {} | ||
| 101 | #endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */ | ||
| 102 | |||
| 103 | static mfp_cfg_t colibri_pxa320_mmc_pin_config[] __initdata = { | ||
| 104 | GPIO22_MMC1_CLK, | ||
| 105 | GPIO23_MMC1_CMD, | ||
| 106 | GPIO18_MMC1_DAT0, | ||
| 107 | GPIO19_MMC1_DAT1, | ||
| 108 | GPIO20_MMC1_DAT2, | ||
| 109 | GPIO21_MMC1_DAT3 | ||
| 110 | }; | ||
| 111 | |||
| 112 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) | ||
| 113 | static mfp_cfg_t colibri_pxa320_lcd_pin_config[] __initdata = { | ||
| 114 | GPIO6_2_LCD_LDD_0, | ||
| 115 | GPIO7_2_LCD_LDD_1, | ||
| 116 | GPIO8_2_LCD_LDD_2, | ||
| 117 | GPIO9_2_LCD_LDD_3, | ||
| 118 | GPIO10_2_LCD_LDD_4, | ||
| 119 | GPIO11_2_LCD_LDD_5, | ||
| 120 | GPIO12_2_LCD_LDD_6, | ||
| 121 | GPIO13_2_LCD_LDD_7, | ||
| 122 | GPIO63_LCD_LDD_8, | ||
| 123 | GPIO64_LCD_LDD_9, | ||
| 124 | GPIO65_LCD_LDD_10, | ||
| 125 | GPIO66_LCD_LDD_11, | ||
| 126 | GPIO67_LCD_LDD_12, | ||
| 127 | GPIO68_LCD_LDD_13, | ||
| 128 | GPIO69_LCD_LDD_14, | ||
| 129 | GPIO70_LCD_LDD_15, | ||
| 130 | GPIO71_LCD_LDD_16, | ||
| 131 | GPIO72_LCD_LDD_17, | ||
| 132 | GPIO73_LCD_CS_N, | ||
| 133 | GPIO74_LCD_VSYNC, | ||
| 134 | GPIO14_2_LCD_FCLK, | ||
| 135 | GPIO15_2_LCD_LCLK, | ||
| 136 | GPIO16_2_LCD_PCLK, | ||
| 137 | GPIO17_2_LCD_BIAS, | ||
| 138 | }; | ||
| 139 | |||
| 140 | static void __init colibri_pxa320_init_lcd(void) | ||
| 141 | { | ||
| 142 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_lcd_pin_config)); | ||
| 143 | } | ||
| 144 | #else | ||
| 145 | static inline void colibri_pxa320_init_lcd(void) {} | ||
| 146 | #endif | ||
| 147 | |||
| 148 | #if defined(SND_AC97_CODEC) || defined(SND_AC97_CODEC_MODULE) | ||
| 149 | static mfp_cfg_t colibri_pxa320_ac97_pin_config[] __initdata = { | ||
| 150 | GPIO34_AC97_SYSCLK, | ||
| 151 | GPIO35_AC97_SDATA_IN_0, | ||
| 152 | GPIO37_AC97_SDATA_OUT, | ||
| 153 | GPIO38_AC97_SYNC, | ||
| 154 | GPIO39_AC97_BITCLK, | ||
| 155 | GPIO40_AC97_nACRESET | ||
| 156 | }; | ||
| 157 | |||
| 158 | static inline void __init colibri_pxa320_init_ac97(void) | ||
| 159 | { | ||
| 160 | pxa3xx_mfp_config(ARRAY_AND_SIZE(colibri_pxa320_ac97_pin_config)); | ||
| 161 | pxa_set_ac97_info(NULL); | ||
| 162 | } | ||
| 163 | #else | ||
| 164 | static inline void colibri_pxa320_init_ac97(void) {} | ||
| 165 | #endif | ||
| 166 | |||
| 167 | void __init colibri_pxa320_init(void) | ||
| 168 | { | ||
| 169 | colibri_pxa320_init_eth(); | ||
| 170 | colibri_pxa320_init_ohci(); | ||
| 171 | colibri_pxa320_init_lcd(); | ||
| 172 | colibri_pxa3xx_init_lcd(mfp_to_gpio(GPIO39_GPIO)); | ||
| 173 | colibri_pxa320_init_ac97(); | ||
| 174 | colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa320_mmc_pin_config), | ||
| 175 | mfp_to_gpio(MFP_PIN_GPIO28)); | ||
| 176 | } | ||
| 177 | |||
| 178 | MACHINE_START(COLIBRI320, "Toradex Colibri PXA320") | ||
| 179 | .phys_io = 0x40000000, | ||
| 180 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 181 | .boot_params = COLIBRI_SDRAM_BASE + 0x100, | ||
| 182 | .init_machine = colibri_pxa320_init, | ||
| 183 | .map_io = pxa_map_io, | ||
| 184 | .init_irq = pxa3xx_init_irq, | ||
| 185 | .timer = &pxa_timer, | ||
| 186 | MACHINE_END | ||
| 187 | |||
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c b/arch/arm/mach-pxa/colibri-pxa3xx.c new file mode 100644 index 000000000000..12d0afc54aa5 --- /dev/null +++ b/arch/arm/mach-pxa/colibri-pxa3xx.c | |||
| @@ -0,0 +1,121 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-pxa/colibri-pxa3xx.c | ||
| 3 | * | ||
| 4 | * Common functions for all Toradex PXA3xx modules | ||
| 5 | * | ||
| 6 | * Daniel Mack <daniel@caiaq.de> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/init.h> | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/platform_device.h> | ||
| 16 | #include <linux/gpio.h> | ||
| 17 | #include <asm/mach-types.h> | ||
| 18 | #include <mach/hardware.h> | ||
| 19 | #include <asm/sizes.h> | ||
| 20 | #include <asm/mach/arch.h> | ||
| 21 | #include <asm/mach/irq.h> | ||
| 22 | #include <mach/pxa3xx-regs.h> | ||
| 23 | #include <mach/mfp-pxa300.h> | ||
| 24 | #include <mach/colibri.h> | ||
| 25 | #include <mach/mmc.h> | ||
| 26 | #include <mach/pxafb.h> | ||
| 27 | |||
| 28 | #include "generic.h" | ||
| 29 | #include "devices.h" | ||
| 30 | |||
| 31 | #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) | ||
| 32 | static int mmc_detect_pin; | ||
| 33 | |||
| 34 | static int colibri_pxa3xx_mci_init(struct device *dev, | ||
| 35 | irq_handler_t colibri_mmc_detect_int, | ||
| 36 | void *data) | ||
| 37 | { | ||
| 38 | int ret; | ||
| 39 | |||
| 40 | ret = gpio_request(mmc_detect_pin, "mmc card detect"); | ||
| 41 | if (ret) | ||
| 42 | return ret; | ||
| 43 | |||
| 44 | gpio_direction_input(mmc_detect_pin); | ||
| 45 | ret = request_irq(gpio_to_irq(mmc_detect_pin), colibri_mmc_detect_int, | ||
| 46 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | ||
| 47 | "MMC card detect", data); | ||
| 48 | if (ret) { | ||
| 49 | gpio_free(mmc_detect_pin); | ||
| 50 | return ret; | ||
| 51 | } | ||
| 52 | |||
| 53 | return 0; | ||
| 54 | } | ||
| 55 | |||
| 56 | static void colibri_pxa3xx_mci_exit(struct device *dev, void *data) | ||
| 57 | { | ||
| 58 | free_irq(mmc_detect_pin, data); | ||
| 59 | gpio_free(gpio_to_irq(mmc_detect_pin)); | ||
| 60 | } | ||
| 61 | |||
| 62 | static struct pxamci_platform_data colibri_pxa3xx_mci_platform_data = { | ||
| 63 | .detect_delay = 20, | ||
| 64 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, | ||
| 65 | .init = colibri_pxa3xx_mci_init, | ||
| 66 | .exit = colibri_pxa3xx_mci_exit, | ||
| 67 | }; | ||
| 68 | |||
| 69 | void __init colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin) | ||
| 70 | { | ||
| 71 | pxa3xx_mfp_config(pins, len); | ||
| 72 | mmc_detect_pin = detect_pin; | ||
| 73 | pxa_set_mci_info(&colibri_pxa3xx_mci_platform_data); | ||
| 74 | } | ||
| 75 | #endif /* CONFIG_MMC_PXA || CONFIG_MMC_PXA_MODULE */ | ||
| 76 | |||
| 77 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) | ||
| 78 | static int lcd_bl_pin; | ||
| 79 | |||
| 80 | /* | ||
| 81 | * LCD panel (Sharp LQ043T3DX02) | ||
| 82 | */ | ||
| 83 | static void colibri_lcd_backlight(int on) | ||
| 84 | { | ||
| 85 | gpio_set_value(lcd_bl_pin, !!on); | ||
| 86 | } | ||
| 87 | |||
| 88 | static struct pxafb_mode_info sharp_lq43_mode = { | ||
| 89 | .pixclock = 101936, | ||
| 90 | .xres = 480, | ||
| 91 | .yres = 272, | ||
| 92 | .bpp = 32, | ||
| 93 | .depth = 18, | ||
| 94 | .hsync_len = 41, | ||
| 95 | .left_margin = 2, | ||
| 96 | .right_margin = 2, | ||
| 97 | .vsync_len = 10, | ||
| 98 | .upper_margin = 2, | ||
| 99 | .lower_margin = 2, | ||
| 100 | .sync = 0, | ||
| 101 | .cmap_greyscale = 0, | ||
| 102 | }; | ||
| 103 | |||
| 104 | static struct pxafb_mach_info sharp_lq43_info = { | ||
| 105 | .modes = &sharp_lq43_mode, | ||
| 106 | .num_modes = 1, | ||
| 107 | .cmap_inverse = 0, | ||
| 108 | .cmap_static = 0, | ||
| 109 | .lcd_conn = LCD_COLOR_TFT_18BPP, | ||
| 110 | .pxafb_backlight_power = colibri_lcd_backlight, | ||
| 111 | }; | ||
| 112 | |||
| 113 | void __init colibri_pxa3xx_init_lcd(int bl_pin) | ||
| 114 | { | ||
| 115 | lcd_bl_pin = bl_pin; | ||
| 116 | gpio_request(bl_pin, "lcd backlight"); | ||
| 117 | gpio_direction_output(bl_pin, 0); | ||
| 118 | set_pxa_fb_info(&sharp_lq43_info); | ||
| 119 | } | ||
| 120 | #endif | ||
| 121 | |||
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index a8d91b6c136b..cdf21dd135b4 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c | |||
| @@ -41,9 +41,7 @@ | |||
| 41 | #include <asm/mach/map.h> | 41 | #include <asm/mach/map.h> |
| 42 | #include <asm/mach/irq.h> | 42 | #include <asm/mach/irq.h> |
| 43 | 43 | ||
| 44 | #include <mach/pxa-regs.h> | 44 | #include <mach/pxa25x.h> |
| 45 | #include <mach/pxa2xx-regs.h> | ||
| 46 | #include <mach/mfp-pxa25x.h> | ||
| 47 | #include <mach/i2c.h> | 45 | #include <mach/i2c.h> |
| 48 | #include <mach/irda.h> | 46 | #include <mach/irda.h> |
| 49 | #include <mach/mmc.h> | 47 | #include <mach/mmc.h> |
| @@ -637,16 +635,16 @@ static void corgi_poweroff(void) | |||
| 637 | /* Green LED off tells the bootloader to halt */ | 635 | /* Green LED off tells the bootloader to halt */ |
| 638 | gpio_set_value(CORGI_GPIO_LED_GREEN, 0); | 636 | gpio_set_value(CORGI_GPIO_LED_GREEN, 0); |
| 639 | 637 | ||
| 640 | arm_machine_restart('h'); | 638 | arm_machine_restart('h', NULL); |
| 641 | } | 639 | } |
| 642 | 640 | ||
| 643 | static void corgi_restart(char mode) | 641 | static void corgi_restart(char mode, const char *cmd) |
| 644 | { | 642 | { |
| 645 | if (!machine_is_corgi()) | 643 | if (!machine_is_corgi()) |
| 646 | /* Green LED on tells the bootloader to reboot */ | 644 | /* Green LED on tells the bootloader to reboot */ |
| 647 | gpio_set_value(CORGI_GPIO_LED_GREEN, 1); | 645 | gpio_set_value(CORGI_GPIO_LED_GREEN, 1); |
| 648 | 646 | ||
| 649 | arm_machine_restart('h'); | 647 | arm_machine_restart('h', cmd); |
| 650 | } | 648 | } |
| 651 | 649 | ||
| 652 | static void __init corgi_init(void) | 650 | static void __init corgi_init(void) |
diff --git a/arch/arm/mach-pxa/corgi_lcd.c b/arch/arm/mach-pxa/corgi_lcd.c index 411607bc1fc2..d9b96319d498 100644 --- a/arch/arm/mach-pxa/corgi_lcd.c +++ b/arch/arm/mach-pxa/corgi_lcd.c | |||
| @@ -22,7 +22,6 @@ | |||
| 22 | #include <linux/string.h> | 22 | #include <linux/string.h> |
| 23 | #include <mach/corgi.h> | 23 | #include <mach/corgi.h> |
| 24 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
| 25 | #include <mach/pxa-regs.h> | ||
| 26 | #include <mach/sharpsl.h> | 25 | #include <mach/sharpsl.h> |
| 27 | #include <mach/spitz.h> | 26 | #include <mach/spitz.h> |
| 28 | #include <asm/hardware/scoop.h> | 27 | #include <asm/hardware/scoop.h> |
diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c index e35259032813..7f04b3a761d1 100644 --- a/arch/arm/mach-pxa/corgi_pm.c +++ b/arch/arm/mach-pxa/corgi_pm.c | |||
| @@ -24,7 +24,6 @@ | |||
| 24 | 24 | ||
| 25 | #include <mach/sharpsl.h> | 25 | #include <mach/sharpsl.h> |
| 26 | #include <mach/corgi.h> | 26 | #include <mach/corgi.h> |
| 27 | #include <mach/pxa-regs.h> | ||
| 28 | #include <mach/pxa2xx-regs.h> | 27 | #include <mach/pxa2xx-regs.h> |
| 29 | #include <mach/pxa2xx-gpio.h> | 28 | #include <mach/pxa2xx-gpio.h> |
| 30 | #include "sharpsl.h" | 29 | #include "sharpsl.h" |
diff --git a/arch/arm/mach-pxa/corgi_ssp.c b/arch/arm/mach-pxa/corgi_ssp.c index 8e2f2215c4ba..a5ee70735e04 100644 --- a/arch/arm/mach-pxa/corgi_ssp.c +++ b/arch/arm/mach-pxa/corgi_ssp.c | |||
| @@ -20,7 +20,6 @@ | |||
| 20 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
| 21 | 21 | ||
| 22 | #include <mach/ssp.h> | 22 | #include <mach/ssp.h> |
| 23 | #include <mach/pxa-regs.h> | ||
| 24 | #include <mach/pxa2xx-gpio.h> | 23 | #include <mach/pxa2xx-gpio.h> |
| 25 | #include <mach/regs-ssp.h> | 24 | #include <mach/regs-ssp.h> |
| 26 | #include "sharpsl.h" | 25 | #include "sharpsl.h" |
diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c index 771dd4eac935..083a1d851d49 100644 --- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c +++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c | |||
| @@ -37,8 +37,6 @@ | |||
| 37 | #include <linux/init.h> | 37 | #include <linux/init.h> |
| 38 | #include <linux/cpufreq.h> | 38 | #include <linux/cpufreq.h> |
| 39 | 39 | ||
| 40 | #include <mach/hardware.h> | ||
| 41 | #include <mach/pxa-regs.h> | ||
| 42 | #include <mach/pxa2xx-regs.h> | 40 | #include <mach/pxa2xx-regs.h> |
| 43 | 41 | ||
| 44 | #ifdef DEBUG | 42 | #ifdef DEBUG |
diff --git a/arch/arm/mach-pxa/cpufreq-pxa3xx.c b/arch/arm/mach-pxa/cpufreq-pxa3xx.c index 968c8309ec37..67f34a8d8e60 100644 --- a/arch/arm/mach-pxa/cpufreq-pxa3xx.c +++ b/arch/arm/mach-pxa/cpufreq-pxa3xx.c | |||
| @@ -15,8 +15,6 @@ | |||
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <linux/cpufreq.h> | 16 | #include <linux/cpufreq.h> |
| 17 | 17 | ||
| 18 | #include <mach/hardware.h> | ||
| 19 | #include <mach/pxa-regs.h> | ||
| 20 | #include <mach/pxa3xx-regs.h> | 18 | #include <mach/pxa3xx-regs.h> |
| 21 | 19 | ||
| 22 | #include "generic.h" | 20 | #include "generic.h" |
diff --git a/arch/arm/mach-pxa/csb701.c b/arch/arm/mach-pxa/csb701.c new file mode 100644 index 000000000000..4a2a2952c374 --- /dev/null +++ b/arch/arm/mach-pxa/csb701.c | |||
| @@ -0,0 +1,61 @@ | |||
| 1 | #include <linux/kernel.h> | ||
| 2 | #include <linux/module.h> | ||
| 3 | #include <linux/platform_device.h> | ||
| 4 | #include <linux/gpio_keys.h> | ||
| 5 | #include <linux/input.h> | ||
| 6 | #include <linux/leds.h> | ||
| 7 | |||
| 8 | static struct gpio_keys_button csb701_buttons[] = { | ||
| 9 | { | ||
| 10 | .code = 0x7, | ||
| 11 | .gpio = 1, | ||
| 12 | .active_low = 1, | ||
| 13 | .desc = "SW2", | ||
| 14 | .type = EV_SW, | ||
| 15 | .wakeup = 1, | ||
| 16 | }, | ||
| 17 | }; | ||
| 18 | |||
| 19 | static struct gpio_keys_platform_data csb701_gpio_keys_data = { | ||
| 20 | .buttons = csb701_buttons, | ||
| 21 | .nbuttons = ARRAY_SIZE(csb701_buttons), | ||
| 22 | }; | ||
| 23 | |||
| 24 | static struct gpio_led csb701_leds[] = { | ||
| 25 | { | ||
| 26 | .name = "csb701:yellow:heartbeat", | ||
| 27 | .default_trigger = "heartbeat", | ||
| 28 | .gpio = 11, | ||
| 29 | .active_low = 1, | ||
| 30 | }, | ||
| 31 | }; | ||
| 32 | |||
| 33 | static struct platform_device csb701_gpio_keys = { | ||
| 34 | .name = "gpio-keys", | ||
| 35 | .id = -1, | ||
| 36 | .dev.platform_data = &csb701_gpio_keys_data, | ||
| 37 | }; | ||
| 38 | |||
| 39 | static struct gpio_led_platform_data csb701_leds_gpio_data = { | ||
| 40 | .leds = csb701_leds, | ||
| 41 | .num_leds = ARRAY_SIZE(csb701_leds), | ||
| 42 | }; | ||
| 43 | |||
| 44 | static struct platform_device csb701_leds_gpio = { | ||
| 45 | .name = "leds-gpio", | ||
| 46 | .id = -1, | ||
| 47 | .dev.platform_data = &csb701_leds_gpio_data, | ||
| 48 | }; | ||
| 49 | |||
| 50 | static struct platform_device *devices[] __initdata = { | ||
| 51 | &csb701_gpio_keys, | ||
| 52 | &csb701_leds_gpio, | ||
| 53 | }; | ||
| 54 | |||
| 55 | static int __init csb701_init(void) | ||
| 56 | { | ||
| 57 | return platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 58 | } | ||
| 59 | |||
| 60 | module_init(csb701_init); | ||
| 61 | |||
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c new file mode 100644 index 000000000000..2b289f83a61a --- /dev/null +++ b/arch/arm/mach-pxa/csb726.c | |||
| @@ -0,0 +1,318 @@ | |||
| 1 | /* | ||
| 2 | * Support for Cogent CSB726 | ||
| 3 | * | ||
| 4 | * Copyright (c) 2008 Dmitry Eremin-Solenikov | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/init.h> | ||
| 13 | #include <linux/io.h> | ||
| 14 | #include <linux/gpio.h> | ||
| 15 | #include <linux/platform_device.h> | ||
| 16 | #include <linux/mtd/physmap.h> | ||
| 17 | #include <linux/mtd/partitions.h> | ||
| 18 | #include <linux/sm501.h> | ||
| 19 | |||
| 20 | #include <asm/mach-types.h> | ||
| 21 | #include <asm/mach/arch.h> | ||
| 22 | #include <mach/csb726.h> | ||
| 23 | #include <mach/mfp-pxa27x.h> | ||
| 24 | #include <mach/i2c.h> | ||
| 25 | #include <mach/mmc.h> | ||
| 26 | #include <mach/ohci.h> | ||
| 27 | #include <mach/pxa2xx-regs.h> | ||
| 28 | |||
| 29 | #include "generic.h" | ||
| 30 | #include "devices.h" | ||
| 31 | |||
| 32 | /* | ||
| 33 | * n/a: 2, 5, 6, 7, 8, 23, 24, 25, 26, 27, 87, 88, 89, | ||
| 34 | * nu: 58 -- 77, 90, 91, 93, 102, 105-108, 114-116, | ||
| 35 | * XXX: 21, | ||
| 36 | * XXX: 79 CS_3 for LAN9215 or PSKTSEL on R2, R3 | ||
| 37 | * XXX: 33 CS_5 for LAN9215 on R1 | ||
| 38 | */ | ||
| 39 | |||
| 40 | static unsigned long csb726_pin_config[] = { | ||
| 41 | GPIO78_nCS_2, /* EXP_CS */ | ||
| 42 | GPIO79_nCS_3, /* SMSC9215 */ | ||
| 43 | GPIO80_nCS_4, /* SM501 */ | ||
| 44 | |||
| 45 | GPIO52_GPIO, /* #SMSC9251 int */ | ||
| 46 | GPIO53_GPIO, /* SM501 int */ | ||
| 47 | |||
| 48 | GPIO1_GPIO, /* GPIO0 */ | ||
| 49 | GPIO11_GPIO, /* GPIO1 */ | ||
| 50 | GPIO9_GPIO, /* GPIO2 */ | ||
| 51 | GPIO10_GPIO, /* GPIO3 */ | ||
| 52 | GPIO16_PWM0_OUT, /* or GPIO4 */ | ||
| 53 | GPIO17_PWM1_OUT, /* or GPIO5 */ | ||
| 54 | GPIO94_GPIO, /* GPIO6 */ | ||
| 55 | GPIO95_GPIO, /* GPIO7 */ | ||
| 56 | GPIO96_GPIO, /* GPIO8 */ | ||
| 57 | GPIO97_GPIO, /* GPIO9 */ | ||
| 58 | GPIO15_GPIO, /* EXP_IRQ */ | ||
| 59 | GPIO18_RDY, /* EXP_WAIT */ | ||
| 60 | |||
| 61 | GPIO0_GPIO, /* PWR_INT */ | ||
| 62 | GPIO104_GPIO, /* PWR_OFF */ | ||
| 63 | |||
| 64 | GPIO12_GPIO, /* touch irq */ | ||
| 65 | |||
| 66 | GPIO13_SSP2_TXD, | ||
| 67 | GPIO14_SSP2_SFRM, | ||
| 68 | MFP_CFG_OUT(GPIO19, AF1, DRIVE_LOW),/* SSP2_SYSCLK */ | ||
| 69 | GPIO22_SSP2_SCLK, | ||
| 70 | |||
| 71 | GPIO81_SSP3_TXD, | ||
| 72 | GPIO82_SSP3_RXD, | ||
| 73 | GPIO83_SSP3_SFRM, | ||
| 74 | GPIO84_SSP3_SCLK, | ||
| 75 | |||
| 76 | GPIO20_GPIO, /* SDIO int */ | ||
| 77 | GPIO32_MMC_CLK, | ||
| 78 | GPIO92_MMC_DAT_0, | ||
| 79 | GPIO109_MMC_DAT_1, | ||
| 80 | GPIO110_MMC_DAT_2, | ||
| 81 | GPIO111_MMC_DAT_3, | ||
| 82 | GPIO112_MMC_CMD, | ||
| 83 | GPIO100_GPIO, /* SD CD */ | ||
| 84 | GPIO101_GPIO, /* SD WP */ | ||
| 85 | |||
| 86 | GPIO28_AC97_BITCLK, | ||
| 87 | GPIO29_AC97_SDATA_IN_0, | ||
| 88 | GPIO30_AC97_SDATA_OUT, | ||
| 89 | GPIO31_AC97_SYNC, | ||
| 90 | GPIO113_AC97_nRESET, | ||
| 91 | |||
| 92 | GPIO34_FFUART_RXD, | ||
| 93 | GPIO35_FFUART_CTS, | ||
| 94 | GPIO36_FFUART_DCD, | ||
| 95 | GPIO37_FFUART_DSR, | ||
| 96 | GPIO38_FFUART_RI, | ||
| 97 | GPIO39_FFUART_TXD, | ||
| 98 | GPIO40_FFUART_DTR, | ||
| 99 | GPIO41_FFUART_RTS, | ||
| 100 | |||
| 101 | GPIO42_BTUART_RXD, | ||
| 102 | GPIO43_BTUART_TXD, | ||
| 103 | GPIO44_BTUART_CTS, | ||
| 104 | GPIO45_BTUART_RTS, | ||
| 105 | |||
| 106 | GPIO46_STUART_RXD, | ||
| 107 | GPIO47_STUART_TXD, | ||
| 108 | |||
| 109 | GPIO48_nPOE, | ||
| 110 | GPIO49_nPWE, | ||
| 111 | GPIO50_nPIOR, | ||
| 112 | GPIO51_nPIOW, | ||
| 113 | GPIO54_nPCE_2, | ||
| 114 | GPIO55_nPREG, | ||
| 115 | GPIO56_nPWAIT, | ||
| 116 | GPIO57_nIOIS16, /* maybe unused */ | ||
| 117 | GPIO85_nPCE_1, | ||
| 118 | GPIO98_GPIO, /* CF IRQ */ | ||
| 119 | GPIO99_GPIO, /* CF CD */ | ||
| 120 | GPIO103_GPIO, /* Reset */ | ||
| 121 | |||
| 122 | GPIO117_I2C_SCL, | ||
| 123 | GPIO118_I2C_SDA, | ||
| 124 | }; | ||
| 125 | |||
| 126 | static struct pxamci_platform_data csb726_mci_data; | ||
| 127 | |||
| 128 | static int csb726_mci_init(struct device *dev, | ||
| 129 | irq_handler_t detect, void *data) | ||
| 130 | { | ||
| 131 | int err; | ||
| 132 | |||
| 133 | csb726_mci_data.detect_delay = msecs_to_jiffies(500); | ||
| 134 | |||
| 135 | err = gpio_request(CSB726_GPIO_MMC_DETECT, "MMC detect"); | ||
| 136 | if (err) | ||
| 137 | goto err_det_req; | ||
| 138 | |||
| 139 | err = gpio_direction_input(CSB726_GPIO_MMC_DETECT); | ||
| 140 | if (err) | ||
| 141 | goto err_det_dir; | ||
| 142 | |||
| 143 | err = gpio_request(CSB726_GPIO_MMC_RO, "MMC ro"); | ||
| 144 | if (err) | ||
| 145 | goto err_ro_req; | ||
| 146 | |||
| 147 | err = gpio_direction_input(CSB726_GPIO_MMC_RO); | ||
| 148 | if (err) | ||
| 149 | goto err_ro_dir; | ||
| 150 | |||
| 151 | err = request_irq(gpio_to_irq(CSB726_GPIO_MMC_DETECT), detect, | ||
| 152 | IRQF_DISABLED, "MMC card detect", data); | ||
| 153 | if (err) | ||
| 154 | goto err_irq; | ||
| 155 | |||
| 156 | return 0; | ||
| 157 | |||
| 158 | err_irq: | ||
| 159 | err_ro_dir: | ||
| 160 | gpio_free(CSB726_GPIO_MMC_RO); | ||
| 161 | err_ro_req: | ||
| 162 | err_det_dir: | ||
| 163 | gpio_free(CSB726_GPIO_MMC_DETECT); | ||
| 164 | err_det_req: | ||
| 165 | return err; | ||
| 166 | } | ||
| 167 | |||
| 168 | static int csb726_mci_get_ro(struct device *dev) | ||
| 169 | { | ||
| 170 | return gpio_get_value(CSB726_GPIO_MMC_RO); | ||
| 171 | } | ||
| 172 | |||
| 173 | static void csb726_mci_exit(struct device *dev, void *data) | ||
| 174 | { | ||
| 175 | free_irq(gpio_to_irq(CSB726_GPIO_MMC_DETECT), data); | ||
| 176 | gpio_free(CSB726_GPIO_MMC_RO); | ||
| 177 | gpio_free(CSB726_GPIO_MMC_DETECT); | ||
| 178 | } | ||
| 179 | |||
| 180 | static struct pxamci_platform_data csb726_mci = { | ||
| 181 | .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34, | ||
| 182 | .init = csb726_mci_init, | ||
| 183 | .get_ro = csb726_mci_get_ro, | ||
| 184 | /* FIXME setpower */ | ||
| 185 | .exit = csb726_mci_exit, | ||
| 186 | }; | ||
| 187 | |||
| 188 | static struct pxaohci_platform_data csb726_ohci_platform_data = { | ||
| 189 | .port_mode = PMM_NPS_MODE, | ||
| 190 | .flags = ENABLE_PORT1 | NO_OC_PROTECTION, | ||
| 191 | }; | ||
| 192 | |||
| 193 | static struct mtd_partition csb726_flash_partitions[] = { | ||
| 194 | { | ||
| 195 | .name = "Bootloader", | ||
| 196 | .offset = 0, | ||
| 197 | .size = CSB726_FLASH_uMON, | ||
| 198 | .mask_flags = MTD_WRITEABLE /* force read-only */ | ||
| 199 | }, | ||
| 200 | { | ||
| 201 | .name = "root", | ||
| 202 | .offset = MTDPART_OFS_APPEND, | ||
| 203 | .size = MTDPART_SIZ_FULL, | ||
| 204 | } | ||
| 205 | }; | ||
| 206 | |||
| 207 | static struct physmap_flash_data csb726_flash_data = { | ||
| 208 | .width = 2, | ||
| 209 | .parts = csb726_flash_partitions, | ||
| 210 | .nr_parts = ARRAY_SIZE(csb726_flash_partitions), | ||
| 211 | }; | ||
| 212 | |||
| 213 | static struct resource csb726_flash_resources[] = { | ||
| 214 | { | ||
| 215 | .start = PXA_CS0_PHYS, | ||
| 216 | .end = PXA_CS0_PHYS + CSB726_FLASH_SIZE - 1 , | ||
| 217 | .flags = IORESOURCE_MEM, | ||
| 218 | } | ||
| 219 | }; | ||
| 220 | |||
| 221 | static struct platform_device csb726_flash = { | ||
| 222 | .name = "physmap-flash", | ||
| 223 | .dev = { | ||
| 224 | .platform_data = &csb726_flash_data, | ||
| 225 | }, | ||
| 226 | .resource = csb726_flash_resources, | ||
| 227 | .num_resources = ARRAY_SIZE(csb726_flash_resources), | ||
| 228 | }; | ||
| 229 | |||
| 230 | static struct resource csb726_sm501_resources[] = { | ||
| 231 | { | ||
| 232 | .start = PXA_CS4_PHYS, | ||
| 233 | .end = PXA_CS4_PHYS + SZ_8M - 1, | ||
| 234 | .flags = IORESOURCE_MEM, | ||
| 235 | .name = "sm501-localmem", | ||
| 236 | }, | ||
| 237 | { | ||
| 238 | .start = PXA_CS4_PHYS + SZ_64M - SZ_2M, | ||
| 239 | .end = PXA_CS4_PHYS + SZ_64M - 1, | ||
| 240 | .flags = IORESOURCE_MEM, | ||
| 241 | .name = "sm501-regs", | ||
| 242 | }, | ||
| 243 | { | ||
| 244 | .start = CSB726_IRQ_SM501, | ||
| 245 | .end = CSB726_IRQ_SM501, | ||
| 246 | .flags = IORESOURCE_IRQ, | ||
| 247 | }, | ||
| 248 | }; | ||
| 249 | |||
| 250 | static struct sm501_initdata csb726_sm501_initdata = { | ||
| 251 | /* .devices = SM501_USE_USB_HOST, */ | ||
| 252 | .devices = SM501_USE_USB_HOST | SM501_USE_UART0 | SM501_USE_UART1, | ||
| 253 | }; | ||
| 254 | |||
| 255 | static struct sm501_platdata csb726_sm501_platdata = { | ||
| 256 | .init = &csb726_sm501_initdata, | ||
| 257 | }; | ||
| 258 | |||
| 259 | static struct platform_device csb726_sm501 = { | ||
| 260 | .name = "sm501", | ||
| 261 | .id = 0, | ||
| 262 | .num_resources = ARRAY_SIZE(csb726_sm501_resources), | ||
| 263 | .resource = csb726_sm501_resources, | ||
| 264 | .dev = { | ||
| 265 | .platform_data = &csb726_sm501_platdata, | ||
| 266 | }, | ||
| 267 | }; | ||
| 268 | |||
| 269 | static struct resource csb726_lan_resources[] = { | ||
| 270 | { | ||
| 271 | .start = PXA_CS3_PHYS, | ||
| 272 | .end = PXA_CS3_PHYS + SZ_64K - 1, | ||
| 273 | .flags = IORESOURCE_MEM, | ||
| 274 | }, | ||
| 275 | { | ||
| 276 | .start = CSB726_IRQ_LAN, | ||
| 277 | .end = CSB726_IRQ_LAN, | ||
| 278 | .flags = IORESOURCE_IRQ, | ||
| 279 | }, | ||
| 280 | }; | ||
| 281 | |||
| 282 | static struct platform_device csb726_lan = { | ||
| 283 | .name = "smc911x", | ||
| 284 | .id = -1, | ||
| 285 | .num_resources = ARRAY_SIZE(csb726_lan_resources), | ||
| 286 | .resource = csb726_lan_resources, | ||
| 287 | }; | ||
| 288 | |||
| 289 | static struct platform_device *devices[] __initdata = { | ||
| 290 | &csb726_flash, | ||
| 291 | &csb726_sm501, | ||
| 292 | &csb726_lan, | ||
| 293 | }; | ||
| 294 | |||
| 295 | static void __init csb726_init(void) | ||
| 296 | { | ||
| 297 | pxa2xx_mfp_config(ARRAY_AND_SIZE(csb726_pin_config)); | ||
| 298 | /* MSC1 = 0x7ffc3ffc; *//* LAN9215/EXP_CS */ | ||
| 299 | /* MSC2 = 0x06697ff4; *//* none/SM501 */ | ||
| 300 | MSC2 = (MSC2 & ~0xffff) | 0x7ff4; /* SM501 */ | ||
| 301 | |||
| 302 | pxa_set_i2c_info(NULL); | ||
| 303 | pxa27x_set_i2c_power_info(NULL); | ||
| 304 | pxa_set_mci_info(&csb726_mci); | ||
| 305 | pxa_set_ohci_info(&csb726_ohci_platform_data); | ||
| 306 | |||
| 307 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 308 | } | ||
| 309 | |||
| 310 | MACHINE_START(CSB726, "Cogent CSB726") | ||
| 311 | .phys_io = 0x40000000, | ||
| 312 | .boot_params = 0xa0000100, | ||
| 313 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 314 | .map_io = pxa_map_io, | ||
| 315 | .init_irq = pxa27x_init_irq, | ||
| 316 | .init_machine = csb726_init, | ||
| 317 | .timer = &pxa_timer, | ||
| 318 | MACHINE_END | ||
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index e16f8e3d58d3..d245e59c51b1 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c | |||
| @@ -4,7 +4,6 @@ | |||
| 4 | #include <linux/platform_device.h> | 4 | #include <linux/platform_device.h> |
| 5 | #include <linux/dma-mapping.h> | 5 | #include <linux/dma-mapping.h> |
| 6 | 6 | ||
| 7 | #include <mach/pxa-regs.h> | ||
| 8 | #include <mach/udc.h> | 7 | #include <mach/udc.h> |
| 9 | #include <mach/pxafb.h> | 8 | #include <mach/pxafb.h> |
| 10 | #include <mach/mmc.h> | 9 | #include <mach/mmc.h> |
diff --git a/arch/arm/mach-pxa/e330.c b/arch/arm/mach-pxa/e330.c index 1bd7f740427c..74d3f8987c5c 100644 --- a/arch/arm/mach-pxa/e330.c +++ b/arch/arm/mach-pxa/e330.c | |||
| @@ -20,9 +20,7 @@ | |||
| 20 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
| 21 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
| 22 | 22 | ||
| 23 | #include <mach/mfp-pxa25x.h> | 23 | #include <mach/pxa25x.h> |
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/pxa-regs.h> | ||
| 26 | #include <mach/eseries-gpio.h> | 24 | #include <mach/eseries-gpio.h> |
| 27 | #include <mach/udc.h> | 25 | #include <mach/udc.h> |
| 28 | 26 | ||
diff --git a/arch/arm/mach-pxa/e350.c b/arch/arm/mach-pxa/e350.c index edcd9d5ce545..080036272131 100644 --- a/arch/arm/mach-pxa/e350.c +++ b/arch/arm/mach-pxa/e350.c | |||
| @@ -21,9 +21,7 @@ | |||
| 21 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
| 22 | 22 | ||
| 23 | #include <mach/irqs.h> | 23 | #include <mach/irqs.h> |
| 24 | #include <mach/mfp-pxa25x.h> | 24 | #include <mach/pxa25x.h> |
| 25 | #include <mach/pxa-regs.h> | ||
| 26 | #include <mach/hardware.h> | ||
| 27 | #include <mach/eseries-gpio.h> | 25 | #include <mach/eseries-gpio.h> |
| 28 | #include <mach/udc.h> | 26 | #include <mach/udc.h> |
| 29 | 27 | ||
diff --git a/arch/arm/mach-pxa/e400.c b/arch/arm/mach-pxa/e400.c index 77bb8e2c48c0..ed9c0c3f64a2 100644 --- a/arch/arm/mach-pxa/e400.c +++ b/arch/arm/mach-pxa/e400.c | |||
| @@ -22,9 +22,7 @@ | |||
| 22 | #include <asm/mach/arch.h> | 22 | #include <asm/mach/arch.h> |
| 23 | #include <asm/mach-types.h> | 23 | #include <asm/mach-types.h> |
| 24 | 24 | ||
| 25 | #include <mach/mfp-pxa25x.h> | 25 | #include <mach/pxa25x.h> |
| 26 | #include <mach/pxa-regs.h> | ||
| 27 | #include <mach/hardware.h> | ||
| 28 | #include <mach/eseries-gpio.h> | 26 | #include <mach/eseries-gpio.h> |
| 29 | #include <mach/pxafb.h> | 27 | #include <mach/pxafb.h> |
| 30 | #include <mach/udc.h> | 28 | #include <mach/udc.h> |
diff --git a/arch/arm/mach-pxa/e740.c b/arch/arm/mach-pxa/e740.c index 6d48e00f4f0b..54af7ed1397e 100644 --- a/arch/arm/mach-pxa/e740.c +++ b/arch/arm/mach-pxa/e740.c | |||
| @@ -24,9 +24,7 @@ | |||
| 24 | #include <asm/mach/arch.h> | 24 | #include <asm/mach/arch.h> |
| 25 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
| 26 | 26 | ||
| 27 | #include <mach/mfp-pxa25x.h> | 27 | #include <mach/pxa25x.h> |
| 28 | #include <mach/pxa-regs.h> | ||
| 29 | #include <mach/hardware.h> | ||
| 30 | #include <mach/eseries-gpio.h> | 28 | #include <mach/eseries-gpio.h> |
| 31 | #include <mach/udc.h> | 29 | #include <mach/udc.h> |
| 32 | #include <mach/irda.h> | 30 | #include <mach/irda.h> |
| @@ -189,7 +187,7 @@ static void __init e740_init(void) | |||
| 189 | { | 187 | { |
| 190 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config)); | 188 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config)); |
| 191 | eseries_register_clks(); | 189 | eseries_register_clks(); |
| 192 | clk_add_alias("CLK_CK48M", &e740_t7l66xb_device.dev, | 190 | clk_add_alias("CLK_CK48M", e740_t7l66xb_device.name, |
| 193 | "UDCCLK", &pxa25x_device_udc.dev), | 191 | "UDCCLK", &pxa25x_device_udc.dev), |
| 194 | eseries_get_tmio_gpios(); | 192 | eseries_get_tmio_gpios(); |
| 195 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 193 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
diff --git a/arch/arm/mach-pxa/e750.c b/arch/arm/mach-pxa/e750.c index be1ab8edb973..16ae72150b1b 100644 --- a/arch/arm/mach-pxa/e750.c +++ b/arch/arm/mach-pxa/e750.c | |||
| @@ -23,9 +23,7 @@ | |||
| 23 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 24 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
| 25 | 25 | ||
| 26 | #include <mach/mfp-pxa25x.h> | 26 | #include <mach/pxa25x.h> |
| 27 | #include <mach/pxa-regs.h> | ||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <mach/eseries-gpio.h> | 27 | #include <mach/eseries-gpio.h> |
| 30 | #include <mach/udc.h> | 28 | #include <mach/udc.h> |
| 31 | #include <mach/irda.h> | 29 | #include <mach/irda.h> |
| @@ -190,7 +188,7 @@ static struct platform_device *devices[] __initdata = { | |||
| 190 | static void __init e750_init(void) | 188 | static void __init e750_init(void) |
| 191 | { | 189 | { |
| 192 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config)); | 190 | pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config)); |
| 193 | clk_add_alias("CLK_CK3P6MI", &e750_tc6393xb_device.dev, | 191 | clk_add_alias("CLK_CK3P6MI", e750_tc6393xb_device.name, |
| 194 | "GPIO11_CLK", NULL), | 192 | "GPIO11_CLK", NULL), |
| 195 | eseries_get_tmio_gpios(); | 193 | eseries_get_tmio_gpios(); |
| 196 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 194 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
diff --git a/arch/arm/mach-pxa/e800.c b/arch/arm/mach-pxa/e800.c index cc9b1293e866..74ab09812a72 100644 --- a/arch/arm/mach-pxa/e800.c +++ b/arch/arm/mach-pxa/e800.c | |||
| @@ -23,9 +23,7 @@ | |||
| 23 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 24 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
| 25 | 25 | ||
| 26 | #include <mach/mfp-pxa25x.h> | 26 | #include <mach/pxa25x.h> |
| 27 | #include <mach/pxa-regs.h> | ||
| 28 | #include <mach/hardware.h> | ||
| 29 | #include <mach/eseries-gpio.h> | 27 | #include <mach/eseries-gpio.h> |
| 30 | #include <mach/udc.h> | 28 | #include <mach/udc.h> |
| 31 | #include <mach/irqs.h> | 29 | #include <mach/irqs.h> |
| @@ -196,7 +194,7 @@ static struct platform_device *devices[] __initdata = { | |||
| 196 | 194 | ||
| 197 | static void __init e800_init(void) | 195 | static void __init e800_init(void) |
| 198 | { | 196 | { |
| 199 | clk_add_alias("CLK_CK3P6MI", &e800_tc6393xb_device.dev, | 197 | clk_add_alias("CLK_CK3P6MI", e800_tc6393xb_device.name, |
| 200 | "GPIO11_CLK", NULL), | 198 | "GPIO11_CLK", NULL), |
| 201 | eseries_get_tmio_gpios(); | 199 | eseries_get_tmio_gpios(); |
| 202 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 200 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index f5ed8038ede5..920dfb8d36da 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c | |||
| @@ -11,40 +11,63 @@ | |||
| 11 | 11 | ||
| 12 | #include <linux/irq.h> | 12 | #include <linux/irq.h> |
| 13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/delay.h> | ||
| 14 | 15 | ||
| 15 | #include <linux/dm9000.h> | 16 | #include <linux/dm9000.h> |
| 16 | #include <linux/rtc-v3020.h> | 17 | #include <linux/rtc-v3020.h> |
| 17 | #include <linux/mtd/nand.h> | 18 | #include <linux/mtd/nand.h> |
| 18 | #include <linux/mtd/partitions.h> | 19 | #include <linux/mtd/partitions.h> |
| 20 | #include <linux/mtd/physmap.h> | ||
| 19 | #include <linux/input.h> | 21 | #include <linux/input.h> |
| 20 | #include <linux/gpio_keys.h> | 22 | #include <linux/gpio_keys.h> |
| 21 | #include <linux/gpio.h> | 23 | #include <linux/gpio.h> |
| 24 | #include <linux/mfd/da903x.h> | ||
| 25 | #include <linux/regulator/machine.h> | ||
| 26 | #include <linux/spi/spi.h> | ||
| 27 | #include <linux/spi/tdo24m.h> | ||
| 28 | #include <linux/power_supply.h> | ||
| 29 | #include <linux/apm-emulation.h> | ||
| 30 | |||
| 31 | #include <media/soc_camera.h> | ||
| 22 | 32 | ||
| 23 | #include <asm/mach-types.h> | 33 | #include <asm/mach-types.h> |
| 24 | #include <asm/mach/arch.h> | 34 | #include <asm/mach/arch.h> |
| 25 | 35 | ||
| 26 | #include <mach/mfp-pxa27x.h> | 36 | #include <mach/pxa27x.h> |
| 27 | #include <mach/pxa-regs.h> | ||
| 28 | #include <mach/pxa27x-udc.h> | 37 | #include <mach/pxa27x-udc.h> |
| 29 | #include <mach/audio.h> | 38 | #include <mach/audio.h> |
| 30 | #include <mach/pxafb.h> | 39 | #include <mach/pxafb.h> |
| 31 | #include <mach/ohci.h> | 40 | #include <mach/ohci.h> |
| 32 | #include <mach/mmc.h> | 41 | #include <mach/mmc.h> |
| 33 | #include <mach/pxa27x_keypad.h> | 42 | #include <mach/pxa27x_keypad.h> |
| 43 | #include <mach/i2c.h> | ||
| 44 | #include <mach/camera.h> | ||
| 45 | #include <mach/pxa2xx_spi.h> | ||
| 34 | 46 | ||
| 35 | #include "generic.h" | 47 | #include "generic.h" |
| 48 | #include "devices.h" | ||
| 36 | 49 | ||
| 37 | /* GPIO IRQ usage */ | 50 | /* EM-X270 specific GPIOs */ |
| 38 | #define GPIO41_ETHIRQ (41) | ||
| 39 | #define GPIO13_MMC_CD (13) | 51 | #define GPIO13_MMC_CD (13) |
| 52 | #define GPIO95_MMC_WP (95) | ||
| 53 | #define GPIO56_NAND_RB (56) | ||
| 54 | |||
| 55 | /* eXeda specific GPIOs */ | ||
| 56 | #define GPIO114_MMC_CD (114) | ||
| 57 | #define GPIO20_NAND_RB (20) | ||
| 58 | #define GPIO38_SD_PWEN (38) | ||
| 59 | |||
| 60 | /* common GPIOs */ | ||
| 61 | #define GPIO11_NAND_CS (11) | ||
| 62 | #define GPIO93_CAM_RESET (93) | ||
| 63 | #define GPIO41_ETHIRQ (41) | ||
| 40 | #define EM_X270_ETHIRQ IRQ_GPIO(GPIO41_ETHIRQ) | 64 | #define EM_X270_ETHIRQ IRQ_GPIO(GPIO41_ETHIRQ) |
| 41 | #define EM_X270_MMC_CD IRQ_GPIO(GPIO13_MMC_CD) | ||
| 42 | 65 | ||
| 43 | /* NAND control GPIOs */ | 66 | static int mmc_cd; |
| 44 | #define GPIO11_NAND_CS (11) | 67 | static int nand_rb; |
| 45 | #define GPIO56_NAND_RB (56) | 68 | static int dm9000_flags; |
| 46 | 69 | ||
| 47 | static unsigned long em_x270_pin_config[] = { | 70 | static unsigned long common_pin_config[] = { |
| 48 | /* AC'97 */ | 71 | /* AC'97 */ |
| 49 | GPIO28_AC97_BITCLK, | 72 | GPIO28_AC97_BITCLK, |
| 50 | GPIO29_AC97_SDATA_IN_0, | 73 | GPIO29_AC97_SDATA_IN_0, |
| @@ -150,21 +173,32 @@ static unsigned long em_x270_pin_config[] = { | |||
| 150 | GPIO18_RDY, | 173 | GPIO18_RDY, |
| 151 | 174 | ||
| 152 | /* GPIO */ | 175 | /* GPIO */ |
| 153 | GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, | 176 | GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH, /* sleep/resume button */ |
| 154 | 177 | ||
| 155 | /* power controls */ | 178 | /* power controls */ |
| 156 | GPIO20_GPIO | MFP_LPM_DRIVE_LOW, /* GPRS_PWEN */ | 179 | GPIO20_GPIO | MFP_LPM_DRIVE_LOW, /* GPRS_PWEN */ |
| 180 | GPIO93_GPIO | MFP_LPM_DRIVE_LOW, /* Camera reset */ | ||
| 157 | GPIO115_GPIO | MFP_LPM_DRIVE_LOW, /* WLAN_PWEN */ | 181 | GPIO115_GPIO | MFP_LPM_DRIVE_LOW, /* WLAN_PWEN */ |
| 158 | 182 | ||
| 159 | /* NAND controls */ | 183 | /* NAND controls */ |
| 160 | GPIO11_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */ | 184 | GPIO11_GPIO | MFP_LPM_DRIVE_HIGH, /* NAND CE# */ |
| 161 | GPIO56_GPIO, /* NAND Ready/Busy */ | ||
| 162 | 185 | ||
| 163 | /* interrupts */ | 186 | /* interrupts */ |
| 164 | GPIO13_GPIO, /* MMC card detect */ | ||
| 165 | GPIO41_GPIO, /* DM9000 interrupt */ | 187 | GPIO41_GPIO, /* DM9000 interrupt */ |
| 166 | }; | 188 | }; |
| 167 | 189 | ||
| 190 | static unsigned long em_x270_pin_config[] = { | ||
| 191 | GPIO13_GPIO, /* MMC card detect */ | ||
| 192 | GPIO56_GPIO, /* NAND Ready/Busy */ | ||
| 193 | GPIO95_GPIO, /* MMC Write protect */ | ||
| 194 | }; | ||
| 195 | |||
| 196 | static unsigned long exeda_pin_config[] = { | ||
| 197 | GPIO20_GPIO, /* NAND Ready/Busy */ | ||
| 198 | GPIO38_GPIO | MFP_LPM_DRIVE_LOW, /* SD slot power */ | ||
| 199 | GPIO114_GPIO, /* MMC card detect */ | ||
| 200 | }; | ||
| 201 | |||
| 168 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) | 202 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) |
| 169 | static struct resource em_x270_dm9000_resource[] = { | 203 | static struct resource em_x270_dm9000_resource[] = { |
| 170 | [0] = { | 204 | [0] = { |
| @@ -185,7 +219,7 @@ static struct resource em_x270_dm9000_resource[] = { | |||
| 185 | }; | 219 | }; |
| 186 | 220 | ||
| 187 | static struct dm9000_plat_data em_x270_dm9000_platdata = { | 221 | static struct dm9000_plat_data em_x270_dm9000_platdata = { |
| 188 | .flags = DM9000_PLATF_32BITONLY, | 222 | .flags = DM9000_PLATF_NO_EEPROM, |
| 189 | }; | 223 | }; |
| 190 | 224 | ||
| 191 | static struct platform_device em_x270_dm9000 = { | 225 | static struct platform_device em_x270_dm9000 = { |
| @@ -200,6 +234,7 @@ static struct platform_device em_x270_dm9000 = { | |||
| 200 | 234 | ||
| 201 | static void __init em_x270_init_dm9000(void) | 235 | static void __init em_x270_init_dm9000(void) |
| 202 | { | 236 | { |
| 237 | em_x270_dm9000_platdata.flags |= dm9000_flags; | ||
| 203 | platform_device_register(&em_x270_dm9000); | 238 | platform_device_register(&em_x270_dm9000); |
| 204 | } | 239 | } |
| 205 | #else | 240 | #else |
| @@ -289,7 +324,7 @@ static int em_x270_nand_device_ready(struct mtd_info *mtd) | |||
| 289 | { | 324 | { |
| 290 | dsb(); | 325 | dsb(); |
| 291 | 326 | ||
| 292 | return gpio_get_value(GPIO56_NAND_RB); | 327 | return gpio_get_value(nand_rb); |
| 293 | } | 328 | } |
| 294 | 329 | ||
| 295 | static struct mtd_partition em_x270_partition_info[] = { | 330 | static struct mtd_partition em_x270_partition_info[] = { |
| @@ -354,14 +389,14 @@ static void __init em_x270_init_nand(void) | |||
| 354 | 389 | ||
| 355 | gpio_direction_output(GPIO11_NAND_CS, 1); | 390 | gpio_direction_output(GPIO11_NAND_CS, 1); |
| 356 | 391 | ||
| 357 | err = gpio_request(GPIO56_NAND_RB, "NAND R/B"); | 392 | err = gpio_request(nand_rb, "NAND R/B"); |
| 358 | if (err) { | 393 | if (err) { |
| 359 | pr_warning("EM-X270: failed to request NAND R/B gpio\n"); | 394 | pr_warning("EM-X270: failed to request NAND R/B gpio\n"); |
| 360 | gpio_free(GPIO11_NAND_CS); | 395 | gpio_free(GPIO11_NAND_CS); |
| 361 | return; | 396 | return; |
| 362 | } | 397 | } |
| 363 | 398 | ||
| 364 | gpio_direction_input(GPIO56_NAND_RB); | 399 | gpio_direction_input(nand_rb); |
| 365 | 400 | ||
| 366 | platform_device_register(&em_x270_nand); | 401 | platform_device_register(&em_x270_nand); |
| 367 | } | 402 | } |
| @@ -369,6 +404,61 @@ static void __init em_x270_init_nand(void) | |||
| 369 | static inline void em_x270_init_nand(void) {} | 404 | static inline void em_x270_init_nand(void) {} |
| 370 | #endif | 405 | #endif |
| 371 | 406 | ||
| 407 | #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE) | ||
| 408 | static struct mtd_partition em_x270_nor_parts[] = { | ||
| 409 | { | ||
| 410 | .name = "Bootloader", | ||
| 411 | .offset = 0x00000000, | ||
| 412 | .size = 0x00050000, | ||
| 413 | .mask_flags = MTD_WRITEABLE /* force read-only */ | ||
| 414 | }, { | ||
| 415 | .name = "Environment", | ||
| 416 | .offset = 0x00050000, | ||
| 417 | .size = 0x00010000, | ||
| 418 | }, { | ||
| 419 | .name = "Reserved", | ||
| 420 | .offset = 0x00060000, | ||
| 421 | .size = 0x00050000, | ||
| 422 | .mask_flags = MTD_WRITEABLE /* force read-only */ | ||
| 423 | }, { | ||
| 424 | .name = "Splashscreen", | ||
| 425 | .offset = 0x000b0000, | ||
| 426 | .size = 0x00050000, | ||
| 427 | } | ||
| 428 | }; | ||
| 429 | |||
| 430 | static struct physmap_flash_data em_x270_nor_data[] = { | ||
| 431 | [0] = { | ||
| 432 | .width = 2, | ||
| 433 | .parts = em_x270_nor_parts, | ||
| 434 | .nr_parts = ARRAY_SIZE(em_x270_nor_parts), | ||
| 435 | }, | ||
| 436 | }; | ||
| 437 | |||
| 438 | static struct resource em_x270_nor_flash_resource = { | ||
| 439 | .start = PXA_CS0_PHYS, | ||
| 440 | .end = PXA_CS0_PHYS + SZ_1M - 1, | ||
| 441 | .flags = IORESOURCE_MEM, | ||
| 442 | }; | ||
| 443 | |||
| 444 | static struct platform_device em_x270_physmap_flash = { | ||
| 445 | .name = "physmap-flash", | ||
| 446 | .id = 0, | ||
| 447 | .num_resources = 1, | ||
| 448 | .resource = &em_x270_nor_flash_resource, | ||
| 449 | .dev = { | ||
| 450 | .platform_data = &em_x270_nor_data, | ||
| 451 | }, | ||
| 452 | }; | ||
| 453 | |||
| 454 | static void __init em_x270_init_nor(void) | ||
| 455 | { | ||
| 456 | platform_device_register(&em_x270_physmap_flash); | ||
| 457 | } | ||
| 458 | #else | ||
| 459 | static inline void em_x270_init_nor(void) {} | ||
| 460 | #endif | ||
| 461 | |||
| 372 | /* PXA27x OHCI controller setup */ | 462 | /* PXA27x OHCI controller setup */ |
| 373 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | 463 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) |
| 374 | static int em_x270_ohci_init(struct device *dev) | 464 | static int em_x270_ohci_init(struct device *dev) |
| @@ -395,40 +485,93 @@ static inline void em_x270_init_ohci(void) {} | |||
| 395 | 485 | ||
| 396 | /* MCI controller setup */ | 486 | /* MCI controller setup */ |
| 397 | #if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE) | 487 | #if defined(CONFIG_MMC) || defined(CONFIG_MMC_MODULE) |
| 488 | static struct regulator *em_x270_sdio_ldo; | ||
| 489 | |||
| 398 | static int em_x270_mci_init(struct device *dev, | 490 | static int em_x270_mci_init(struct device *dev, |
| 399 | irq_handler_t em_x270_detect_int, | 491 | irq_handler_t em_x270_detect_int, |
| 400 | void *data) | 492 | void *data) |
| 401 | { | 493 | { |
| 402 | int err = request_irq(EM_X270_MMC_CD, em_x270_detect_int, | 494 | int err; |
| 403 | IRQF_DISABLED | IRQF_TRIGGER_FALLING, | 495 | |
| 496 | em_x270_sdio_ldo = regulator_get(dev, "vcc sdio"); | ||
| 497 | if (IS_ERR(em_x270_sdio_ldo)) { | ||
| 498 | dev_err(dev, "can't request SDIO power supply: %ld\n", | ||
| 499 | PTR_ERR(em_x270_sdio_ldo)); | ||
| 500 | return PTR_ERR(em_x270_sdio_ldo); | ||
| 501 | } | ||
| 502 | |||
| 503 | err = request_irq(gpio_to_irq(mmc_cd), em_x270_detect_int, | ||
| 504 | IRQF_DISABLED | IRQF_TRIGGER_RISING | | ||
| 505 | IRQF_TRIGGER_FALLING, | ||
| 404 | "MMC card detect", data); | 506 | "MMC card detect", data); |
| 405 | if (err) { | 507 | if (err) { |
| 406 | printk(KERN_ERR "%s: can't request MMC card detect IRQ: %d\n", | 508 | dev_err(dev, "can't request MMC card detect IRQ: %d\n", err); |
| 407 | __func__, err); | 509 | goto err_irq; |
| 408 | return err; | 510 | } |
| 511 | |||
| 512 | if (machine_is_em_x270()) { | ||
| 513 | err = gpio_request(GPIO95_MMC_WP, "MMC WP"); | ||
| 514 | if (err) { | ||
| 515 | dev_err(dev, "can't request MMC write protect: %d\n", | ||
| 516 | err); | ||
| 517 | goto err_gpio_wp; | ||
| 518 | } | ||
| 519 | gpio_direction_input(GPIO95_MMC_WP); | ||
| 520 | } else { | ||
| 521 | err = gpio_request(GPIO38_SD_PWEN, "sdio power"); | ||
| 522 | if (err) { | ||
| 523 | dev_err(dev, "can't request MMC power control : %d\n", | ||
| 524 | err); | ||
| 525 | goto err_gpio_wp; | ||
| 526 | } | ||
| 527 | gpio_direction_output(GPIO38_SD_PWEN, 1); | ||
| 409 | } | 528 | } |
| 410 | 529 | ||
| 411 | return 0; | 530 | return 0; |
| 531 | |||
| 532 | err_gpio_wp: | ||
| 533 | free_irq(gpio_to_irq(mmc_cd), data); | ||
| 534 | err_irq: | ||
| 535 | regulator_put(em_x270_sdio_ldo); | ||
| 536 | |||
| 537 | return err; | ||
| 412 | } | 538 | } |
| 413 | 539 | ||
| 414 | static void em_x270_mci_setpower(struct device *dev, unsigned int vdd) | 540 | static void em_x270_mci_setpower(struct device *dev, unsigned int vdd) |
| 415 | { | 541 | { |
| 416 | /* | 542 | struct pxamci_platform_data* p_d = dev->platform_data; |
| 417 | FIXME: current hardware implementation does not allow to | 543 | |
| 418 | enable/disable MMC power. This will be fixed in next HW releases, | 544 | if ((1 << vdd) & p_d->ocr_mask) { |
| 419 | and we'll need to add implmentation here. | 545 | int vdd_uV = (2000 + (vdd - __ffs(MMC_VDD_20_21)) * 100) * 1000; |
| 420 | */ | 546 | |
| 421 | return; | 547 | regulator_set_voltage(em_x270_sdio_ldo, vdd_uV, vdd_uV); |
| 548 | regulator_enable(em_x270_sdio_ldo); | ||
| 549 | } else { | ||
| 550 | regulator_disable(em_x270_sdio_ldo); | ||
| 551 | } | ||
| 422 | } | 552 | } |
| 423 | 553 | ||
| 424 | static void em_x270_mci_exit(struct device *dev, void *data) | 554 | static void em_x270_mci_exit(struct device *dev, void *data) |
| 425 | { | 555 | { |
| 426 | int irq = gpio_to_irq(GPIO13_MMC_CD); | 556 | free_irq(gpio_to_irq(mmc_cd), data); |
| 427 | free_irq(irq, data); | 557 | regulator_put(em_x270_sdio_ldo); |
| 558 | |||
| 559 | if (machine_is_em_x270()) | ||
| 560 | gpio_free(GPIO95_MMC_WP); | ||
| 561 | else | ||
| 562 | gpio_free(GPIO38_SD_PWEN); | ||
| 563 | } | ||
| 564 | |||
| 565 | static int em_x270_mci_get_ro(struct device *dev) | ||
| 566 | { | ||
| 567 | return gpio_get_value(GPIO95_MMC_WP); | ||
| 428 | } | 568 | } |
| 429 | 569 | ||
| 430 | static struct pxamci_platform_data em_x270_mci_platform_data = { | 570 | static struct pxamci_platform_data em_x270_mci_platform_data = { |
| 431 | .ocr_mask = MMC_VDD_28_29|MMC_VDD_29_30|MMC_VDD_30_31, | 571 | .ocr_mask = MMC_VDD_20_21|MMC_VDD_21_22|MMC_VDD_22_23| |
| 572 | MMC_VDD_24_25|MMC_VDD_25_26|MMC_VDD_26_27| | ||
| 573 | MMC_VDD_27_28|MMC_VDD_28_29|MMC_VDD_29_30| | ||
| 574 | MMC_VDD_30_31|MMC_VDD_31_32, | ||
| 432 | .init = em_x270_mci_init, | 575 | .init = em_x270_mci_init, |
| 433 | .setpower = em_x270_mci_setpower, | 576 | .setpower = em_x270_mci_setpower, |
| 434 | .exit = em_x270_mci_exit, | 577 | .exit = em_x270_mci_exit, |
| @@ -436,33 +579,53 @@ static struct pxamci_platform_data em_x270_mci_platform_data = { | |||
| 436 | 579 | ||
| 437 | static void __init em_x270_init_mmc(void) | 580 | static void __init em_x270_init_mmc(void) |
| 438 | { | 581 | { |
| 582 | if (machine_is_em_x270()) | ||
| 583 | em_x270_mci_platform_data.get_ro = em_x270_mci_get_ro; | ||
| 584 | |||
| 585 | em_x270_mci_platform_data.detect_delay = msecs_to_jiffies(250); | ||
| 439 | pxa_set_mci_info(&em_x270_mci_platform_data); | 586 | pxa_set_mci_info(&em_x270_mci_platform_data); |
| 440 | } | 587 | } |
| 441 | #else | 588 | #else |
| 442 | static inline void em_x270_init_mmc(void) {} | 589 | static inline void em_x270_init_mmc(void) {} |
| 443 | #endif | 590 | #endif |
| 444 | 591 | ||
| 445 | /* LCD 480x640 */ | 592 | /* LCD */ |
| 446 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) | 593 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) |
| 447 | static struct pxafb_mode_info em_x270_lcd_mode = { | 594 | static struct pxafb_mode_info em_x270_lcd_modes[] = { |
| 448 | .pixclock = 50000, | 595 | [0] = { |
| 449 | .bpp = 16, | 596 | .pixclock = 38250, |
| 450 | .xres = 480, | 597 | .bpp = 16, |
| 451 | .yres = 640, | 598 | .xres = 480, |
| 452 | .hsync_len = 8, | 599 | .yres = 640, |
| 453 | .vsync_len = 2, | 600 | .hsync_len = 8, |
| 454 | .left_margin = 8, | 601 | .vsync_len = 2, |
| 455 | .upper_margin = 0, | 602 | .left_margin = 8, |
| 456 | .right_margin = 24, | 603 | .upper_margin = 2, |
| 457 | .lower_margin = 4, | 604 | .right_margin = 24, |
| 458 | .cmap_greyscale = 0, | 605 | .lower_margin = 4, |
| 606 | .sync = 0, | ||
| 607 | }, | ||
| 608 | [1] = { | ||
| 609 | .pixclock = 153800, | ||
| 610 | .bpp = 16, | ||
| 611 | .xres = 240, | ||
| 612 | .yres = 320, | ||
| 613 | .hsync_len = 8, | ||
| 614 | .vsync_len = 2, | ||
| 615 | .left_margin = 8, | ||
| 616 | .upper_margin = 2, | ||
| 617 | .right_margin = 88, | ||
| 618 | .lower_margin = 2, | ||
| 619 | .sync = 0, | ||
| 620 | }, | ||
| 459 | }; | 621 | }; |
| 460 | 622 | ||
| 461 | static struct pxafb_mach_info em_x270_lcd = { | 623 | static struct pxafb_mach_info em_x270_lcd = { |
| 462 | .modes = &em_x270_lcd_mode, | 624 | .modes = em_x270_lcd_modes, |
| 463 | .num_modes = 1, | 625 | .num_modes = 2, |
| 464 | .lcd_conn = LCD_COLOR_TFT_16BPP, | 626 | .lcd_conn = LCD_COLOR_TFT_16BPP, |
| 465 | }; | 627 | }; |
| 628 | |||
| 466 | static void __init em_x270_init_lcd(void) | 629 | static void __init em_x270_init_lcd(void) |
| 467 | { | 630 | { |
| 468 | set_pxa_fb_info(&em_x270_lcd); | 631 | set_pxa_fb_info(&em_x270_lcd); |
| @@ -471,6 +634,40 @@ static void __init em_x270_init_lcd(void) | |||
| 471 | static inline void em_x270_init_lcd(void) {} | 634 | static inline void em_x270_init_lcd(void) {} |
| 472 | #endif | 635 | #endif |
| 473 | 636 | ||
| 637 | #if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE) | ||
| 638 | static struct pxa2xx_spi_master em_x270_spi_info = { | ||
| 639 | .num_chipselect = 1, | ||
| 640 | }; | ||
| 641 | |||
| 642 | static struct pxa2xx_spi_chip em_x270_tdo24m_chip = { | ||
| 643 | .rx_threshold = 1, | ||
| 644 | .tx_threshold = 1, | ||
| 645 | }; | ||
| 646 | |||
| 647 | static struct tdo24m_platform_data em_x270_tdo24m_pdata = { | ||
| 648 | .model = TDO35S, | ||
| 649 | }; | ||
| 650 | |||
| 651 | static struct spi_board_info em_x270_spi_devices[] __initdata = { | ||
| 652 | { | ||
| 653 | .modalias = "tdo24m", | ||
| 654 | .max_speed_hz = 1000000, | ||
| 655 | .bus_num = 1, | ||
| 656 | .chip_select = 0, | ||
| 657 | .controller_data = &em_x270_tdo24m_chip, | ||
| 658 | .platform_data = &em_x270_tdo24m_pdata, | ||
| 659 | }, | ||
| 660 | }; | ||
| 661 | |||
| 662 | static void __init em_x270_init_spi(void) | ||
| 663 | { | ||
| 664 | pxa2xx_set_spi_info(1, &em_x270_spi_info); | ||
| 665 | spi_register_board_info(ARRAY_AND_SIZE(em_x270_spi_devices)); | ||
| 666 | } | ||
| 667 | #else | ||
| 668 | static inline void em_x270_init_spi(void) {} | ||
| 669 | #endif | ||
| 670 | |||
| 474 | #if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE) | 671 | #if defined(CONFIG_SND_PXA2XX_AC97) || defined(CONFIG_SND_PXA2XX_AC97_MODULE) |
| 475 | static void __init em_x270_init_ac97(void) | 672 | static void __init em_x270_init_ac97(void) |
| 476 | { | 673 | { |
| @@ -481,23 +678,76 @@ static inline void em_x270_init_ac97(void) {} | |||
| 481 | #endif | 678 | #endif |
| 482 | 679 | ||
| 483 | #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE) | 680 | #if defined(CONFIG_KEYBOARD_PXA27x) || defined(CONFIG_KEYBOARD_PXA27x_MODULE) |
| 484 | static unsigned int em_x270_matrix_keys[] = { | 681 | static unsigned int em_x270_module_matrix_keys[] = { |
| 485 | KEY(0, 0, KEY_A), KEY(1, 0, KEY_UP), KEY(2, 1, KEY_B), | 682 | KEY(0, 0, KEY_A), KEY(1, 0, KEY_UP), KEY(2, 1, KEY_B), |
| 486 | KEY(0, 2, KEY_LEFT), KEY(1, 1, KEY_ENTER), KEY(2, 0, KEY_RIGHT), | 683 | KEY(0, 2, KEY_LEFT), KEY(1, 1, KEY_ENTER), KEY(2, 0, KEY_RIGHT), |
| 487 | KEY(0, 1, KEY_C), KEY(1, 2, KEY_DOWN), KEY(2, 2, KEY_D), | 684 | KEY(0, 1, KEY_C), KEY(1, 2, KEY_DOWN), KEY(2, 2, KEY_D), |
| 488 | }; | 685 | }; |
| 489 | 686 | ||
| 490 | struct pxa27x_keypad_platform_data em_x270_keypad_info = { | 687 | struct pxa27x_keypad_platform_data em_x270_module_keypad_info = { |
| 491 | /* code map for the matrix keys */ | 688 | /* code map for the matrix keys */ |
| 492 | .matrix_key_rows = 3, | 689 | .matrix_key_rows = 3, |
| 493 | .matrix_key_cols = 3, | 690 | .matrix_key_cols = 3, |
| 494 | .matrix_key_map = em_x270_matrix_keys, | 691 | .matrix_key_map = em_x270_module_matrix_keys, |
| 495 | .matrix_key_map_size = ARRAY_SIZE(em_x270_matrix_keys), | 692 | .matrix_key_map_size = ARRAY_SIZE(em_x270_module_matrix_keys), |
| 693 | }; | ||
| 694 | |||
| 695 | static unsigned int em_x270_exeda_matrix_keys[] = { | ||
| 696 | KEY(0, 0, KEY_RIGHTSHIFT), KEY(0, 1, KEY_RIGHTCTRL), | ||
| 697 | KEY(0, 2, KEY_RIGHTALT), KEY(0, 3, KEY_SPACE), | ||
| 698 | KEY(0, 4, KEY_LEFTALT), KEY(0, 5, KEY_LEFTCTRL), | ||
| 699 | KEY(0, 6, KEY_ENTER), KEY(0, 7, KEY_SLASH), | ||
| 700 | |||
| 701 | KEY(1, 0, KEY_DOT), KEY(1, 1, KEY_M), | ||
| 702 | KEY(1, 2, KEY_N), KEY(1, 3, KEY_B), | ||
| 703 | KEY(1, 4, KEY_V), KEY(1, 5, KEY_C), | ||
| 704 | KEY(1, 6, KEY_X), KEY(1, 7, KEY_Z), | ||
| 705 | |||
| 706 | KEY(2, 0, KEY_LEFTSHIFT), KEY(2, 1, KEY_SEMICOLON), | ||
| 707 | KEY(2, 2, KEY_L), KEY(2, 3, KEY_K), | ||
| 708 | KEY(2, 4, KEY_J), KEY(2, 5, KEY_H), | ||
| 709 | KEY(2, 6, KEY_G), KEY(2, 7, KEY_F), | ||
| 710 | |||
| 711 | KEY(3, 0, KEY_D), KEY(3, 1, KEY_S), | ||
| 712 | KEY(3, 2, KEY_A), KEY(3, 3, KEY_TAB), | ||
| 713 | KEY(3, 4, KEY_BACKSPACE), KEY(3, 5, KEY_P), | ||
| 714 | KEY(3, 6, KEY_O), KEY(3, 7, KEY_I), | ||
| 715 | |||
| 716 | KEY(4, 0, KEY_U), KEY(4, 1, KEY_Y), | ||
| 717 | KEY(4, 2, KEY_T), KEY(4, 3, KEY_R), | ||
| 718 | KEY(4, 4, KEY_E), KEY(4, 5, KEY_W), | ||
| 719 | KEY(4, 6, KEY_Q), KEY(4, 7, KEY_MINUS), | ||
| 720 | |||
| 721 | KEY(5, 0, KEY_0), KEY(5, 1, KEY_9), | ||
| 722 | KEY(5, 2, KEY_8), KEY(5, 3, KEY_7), | ||
| 723 | KEY(5, 4, KEY_6), KEY(5, 5, KEY_5), | ||
| 724 | KEY(5, 6, KEY_4), KEY(5, 7, KEY_3), | ||
| 725 | |||
| 726 | KEY(6, 0, KEY_2), KEY(6, 1, KEY_1), | ||
| 727 | KEY(6, 2, KEY_ENTER), KEY(6, 3, KEY_END), | ||
| 728 | KEY(6, 4, KEY_DOWN), KEY(6, 5, KEY_UP), | ||
| 729 | KEY(6, 6, KEY_MENU), KEY(6, 7, KEY_F1), | ||
| 730 | |||
| 731 | KEY(7, 0, KEY_LEFT), KEY(7, 1, KEY_RIGHT), | ||
| 732 | KEY(7, 2, KEY_BACK), KEY(7, 3, KEY_HOME), | ||
| 733 | KEY(7, 4, 0), KEY(7, 5, 0), | ||
| 734 | KEY(7, 6, 0), KEY(7, 7, 0), | ||
| 735 | }; | ||
| 736 | |||
| 737 | struct pxa27x_keypad_platform_data em_x270_exeda_keypad_info = { | ||
| 738 | /* code map for the matrix keys */ | ||
| 739 | .matrix_key_rows = 8, | ||
| 740 | .matrix_key_cols = 8, | ||
| 741 | .matrix_key_map = em_x270_exeda_matrix_keys, | ||
| 742 | .matrix_key_map_size = ARRAY_SIZE(em_x270_exeda_matrix_keys), | ||
| 496 | }; | 743 | }; |
| 497 | 744 | ||
| 498 | static void __init em_x270_init_keypad(void) | 745 | static void __init em_x270_init_keypad(void) |
| 499 | { | 746 | { |
| 500 | pxa_set_keypad_info(&em_x270_keypad_info); | 747 | if (machine_is_em_x270()) |
| 748 | pxa_set_keypad_info(&em_x270_module_keypad_info); | ||
| 749 | else | ||
| 750 | pxa_set_keypad_info(&em_x270_exeda_keypad_info); | ||
| 501 | } | 751 | } |
| 502 | #else | 752 | #else |
| 503 | static inline void em_x270_init_keypad(void) {} | 753 | static inline void em_x270_init_keypad(void) {} |
| @@ -535,19 +785,264 @@ static void __init em_x270_init_gpio_keys(void) | |||
| 535 | static inline void em_x270_init_gpio_keys(void) {} | 785 | static inline void em_x270_init_gpio_keys(void) {} |
| 536 | #endif | 786 | #endif |
| 537 | 787 | ||
| 538 | static void __init em_x270_init(void) | 788 | /* Quick Capture Interface and sensor setup */ |
| 789 | #if defined(CONFIG_VIDEO_PXA27x) || defined(CONFIG_VIDEO_PXA27x_MODULE) | ||
| 790 | static struct regulator *em_x270_camera_ldo; | ||
| 791 | |||
| 792 | static int em_x270_sensor_init(struct device *dev) | ||
| 539 | { | 793 | { |
| 794 | int ret; | ||
| 795 | |||
| 796 | ret = gpio_request(GPIO93_CAM_RESET, "camera reset"); | ||
| 797 | if (ret) | ||
| 798 | return ret; | ||
| 799 | |||
| 800 | gpio_direction_output(GPIO93_CAM_RESET, 0); | ||
| 801 | |||
| 802 | em_x270_camera_ldo = regulator_get(NULL, "vcc cam"); | ||
| 803 | if (em_x270_camera_ldo == NULL) { | ||
| 804 | gpio_free(GPIO93_CAM_RESET); | ||
| 805 | return -ENODEV; | ||
| 806 | } | ||
| 807 | |||
| 808 | ret = regulator_enable(em_x270_camera_ldo); | ||
| 809 | if (ret) { | ||
| 810 | regulator_put(em_x270_camera_ldo); | ||
| 811 | gpio_free(GPIO93_CAM_RESET); | ||
| 812 | return ret; | ||
| 813 | } | ||
| 814 | |||
| 815 | gpio_set_value(GPIO93_CAM_RESET, 1); | ||
| 816 | |||
| 817 | return 0; | ||
| 818 | } | ||
| 819 | |||
| 820 | struct pxacamera_platform_data em_x270_camera_platform_data = { | ||
| 821 | .init = em_x270_sensor_init, | ||
| 822 | .flags = PXA_CAMERA_MASTER | PXA_CAMERA_DATAWIDTH_8 | | ||
| 823 | PXA_CAMERA_PCLK_EN | PXA_CAMERA_MCLK_EN, | ||
| 824 | .mclk_10khz = 2600, | ||
| 825 | }; | ||
| 826 | |||
| 827 | static int em_x270_sensor_power(struct device *dev, int on) | ||
| 828 | { | ||
| 829 | int ret; | ||
| 830 | int is_on = regulator_is_enabled(em_x270_camera_ldo); | ||
| 831 | |||
| 832 | if (on == is_on) | ||
| 833 | return 0; | ||
| 834 | |||
| 835 | gpio_set_value(GPIO93_CAM_RESET, !on); | ||
| 836 | |||
| 837 | if (on) | ||
| 838 | ret = regulator_enable(em_x270_camera_ldo); | ||
| 839 | else | ||
| 840 | ret = regulator_disable(em_x270_camera_ldo); | ||
| 841 | |||
| 842 | if (ret) | ||
| 843 | return ret; | ||
| 844 | |||
| 845 | gpio_set_value(GPIO93_CAM_RESET, on); | ||
| 846 | |||
| 847 | return 0; | ||
| 848 | } | ||
| 849 | |||
| 850 | static struct soc_camera_link iclink = { | ||
| 851 | .bus_id = 0, | ||
| 852 | .power = em_x270_sensor_power, | ||
| 853 | }; | ||
| 854 | |||
| 855 | static struct i2c_board_info em_x270_i2c_cam_info[] = { | ||
| 856 | { | ||
| 857 | I2C_BOARD_INFO("mt9m111", 0x48), | ||
| 858 | .platform_data = &iclink, | ||
| 859 | }, | ||
| 860 | }; | ||
| 861 | |||
| 862 | static struct i2c_pxa_platform_data em_x270_i2c_info = { | ||
| 863 | .fast_mode = 1, | ||
| 864 | }; | ||
| 865 | |||
| 866 | static void __init em_x270_init_camera(void) | ||
| 867 | { | ||
| 868 | pxa_set_i2c_info(&em_x270_i2c_info); | ||
| 869 | i2c_register_board_info(0, ARRAY_AND_SIZE(em_x270_i2c_cam_info)); | ||
| 870 | pxa_set_camera_info(&em_x270_camera_platform_data); | ||
| 871 | } | ||
| 872 | #else | ||
| 873 | static inline void em_x270_init_camera(void) {} | ||
| 874 | #endif | ||
| 875 | |||
| 876 | /* DA9030 related initializations */ | ||
| 877 | #define REGULATOR_CONSUMER(_name, _dev, _supply) \ | ||
| 878 | static struct regulator_consumer_supply _name##_consumers[] = { \ | ||
| 879 | { \ | ||
| 880 | .dev = _dev, \ | ||
| 881 | .supply = _supply, \ | ||
| 882 | }, \ | ||
| 883 | } | ||
| 884 | |||
| 885 | REGULATOR_CONSUMER(ldo3, NULL, "vcc gps"); | ||
| 886 | REGULATOR_CONSUMER(ldo5, NULL, "vcc cam"); | ||
| 887 | REGULATOR_CONSUMER(ldo10, &pxa_device_mci.dev, "vcc sdio"); | ||
| 888 | REGULATOR_CONSUMER(ldo12, NULL, "vcc usb"); | ||
| 889 | REGULATOR_CONSUMER(ldo19, NULL, "vcc gprs"); | ||
| 890 | |||
| 891 | #define REGULATOR_INIT(_ldo, _min_uV, _max_uV, _ops_mask) \ | ||
| 892 | static struct regulator_init_data _ldo##_data = { \ | ||
| 893 | .constraints = { \ | ||
| 894 | .min_uV = _min_uV, \ | ||
| 895 | .max_uV = _max_uV, \ | ||
| 896 | .state_mem = { \ | ||
| 897 | .enabled = 0, \ | ||
| 898 | }, \ | ||
| 899 | .valid_ops_mask = _ops_mask, \ | ||
| 900 | }, \ | ||
| 901 | .num_consumer_supplies = ARRAY_SIZE(_ldo##_consumers), \ | ||
| 902 | .consumer_supplies = _ldo##_consumers, \ | ||
| 903 | }; | ||
| 904 | |||
| 905 | REGULATOR_INIT(ldo3, 3200000, 3200000, REGULATOR_CHANGE_STATUS); | ||
| 906 | REGULATOR_INIT(ldo5, 3000000, 3000000, REGULATOR_CHANGE_STATUS); | ||
| 907 | REGULATOR_INIT(ldo10, 2000000, 3200000, | ||
| 908 | REGULATOR_CHANGE_STATUS | REGULATOR_CHANGE_VOLTAGE); | ||
| 909 | REGULATOR_INIT(ldo12, 3000000, 3000000, REGULATOR_CHANGE_STATUS); | ||
| 910 | REGULATOR_INIT(ldo19, 3200000, 3200000, REGULATOR_CHANGE_STATUS); | ||
| 911 | |||
| 912 | struct led_info em_x270_led_info = { | ||
| 913 | .name = "em-x270:orange", | ||
| 914 | .default_trigger = "battery-charging-or-full", | ||
| 915 | }; | ||
| 916 | |||
| 917 | struct power_supply_info em_x270_psy_info = { | ||
| 918 | .name = "LP555597P6H-FPS", | ||
| 919 | .technology = POWER_SUPPLY_TECHNOLOGY_LIPO, | ||
| 920 | .voltage_max_design = 4200000, | ||
| 921 | .voltage_min_design = 3000000, | ||
| 922 | .use_for_apm = 1, | ||
| 923 | }; | ||
| 924 | |||
| 925 | static void em_x270_battery_low(void) | ||
| 926 | { | ||
| 927 | apm_queue_event(APM_LOW_BATTERY); | ||
| 928 | } | ||
| 929 | |||
| 930 | static void em_x270_battery_critical(void) | ||
| 931 | { | ||
| 932 | apm_queue_event(APM_CRITICAL_SUSPEND); | ||
| 933 | } | ||
| 934 | |||
| 935 | struct da9030_battery_info em_x270_batterty_info = { | ||
| 936 | .battery_info = &em_x270_psy_info, | ||
| 937 | |||
| 938 | .charge_milliamp = 1000, | ||
| 939 | .charge_millivolt = 4200, | ||
| 940 | |||
| 941 | .vbat_low = 3600, | ||
| 942 | .vbat_crit = 3400, | ||
| 943 | .vbat_charge_start = 4100, | ||
| 944 | .vbat_charge_stop = 4200, | ||
| 945 | .vbat_charge_restart = 4000, | ||
| 946 | |||
| 947 | .vcharge_min = 3200, | ||
| 948 | .vcharge_max = 5500, | ||
| 949 | |||
| 950 | .tbat_low = 197, | ||
| 951 | .tbat_high = 78, | ||
| 952 | .tbat_restart = 100, | ||
| 953 | |||
| 954 | .batmon_interval = 0, | ||
| 955 | |||
| 956 | .battery_low = em_x270_battery_low, | ||
| 957 | .battery_critical = em_x270_battery_critical, | ||
| 958 | }; | ||
| 959 | |||
| 960 | #define DA9030_SUBDEV(_name, _id, _pdata) \ | ||
| 961 | { \ | ||
| 962 | .name = "da903x-" #_name, \ | ||
| 963 | .id = DA9030_ID_##_id, \ | ||
| 964 | .platform_data = _pdata, \ | ||
| 965 | } | ||
| 966 | |||
| 967 | #define DA9030_LDO(num) DA9030_SUBDEV(regulator, LDO##num, &ldo##num##_data) | ||
| 968 | |||
| 969 | struct da903x_subdev_info em_x270_da9030_subdevs[] = { | ||
| 970 | DA9030_LDO(3), | ||
| 971 | DA9030_LDO(5), | ||
| 972 | DA9030_LDO(10), | ||
| 973 | DA9030_LDO(12), | ||
| 974 | DA9030_LDO(19), | ||
| 975 | |||
| 976 | DA9030_SUBDEV(led, LED_PC, &em_x270_led_info), | ||
| 977 | DA9030_SUBDEV(backlight, WLED, &em_x270_led_info), | ||
| 978 | DA9030_SUBDEV(battery, BAT, &em_x270_batterty_info), | ||
| 979 | }; | ||
| 980 | |||
| 981 | static struct da903x_platform_data em_x270_da9030_info = { | ||
| 982 | .num_subdevs = ARRAY_SIZE(em_x270_da9030_subdevs), | ||
| 983 | .subdevs = em_x270_da9030_subdevs, | ||
| 984 | }; | ||
| 985 | |||
| 986 | static struct i2c_board_info em_x270_i2c_pmic_info = { | ||
| 987 | I2C_BOARD_INFO("da9030", 0x49), | ||
| 988 | .irq = IRQ_GPIO(0), | ||
| 989 | .platform_data = &em_x270_da9030_info, | ||
| 990 | }; | ||
| 991 | |||
| 992 | static struct i2c_pxa_platform_data em_x270_pwr_i2c_info = { | ||
| 993 | .use_pio = 1, | ||
| 994 | }; | ||
| 995 | |||
| 996 | static void __init em_x270_init_da9030(void) | ||
| 997 | { | ||
| 998 | pxa27x_set_i2c_power_info(&em_x270_pwr_i2c_info); | ||
| 999 | i2c_register_board_info(1, &em_x270_i2c_pmic_info, 1); | ||
| 1000 | } | ||
| 1001 | |||
| 1002 | static void __init em_x270_module_init(void) | ||
| 1003 | { | ||
| 1004 | pr_info("%s\n", __func__); | ||
| 540 | pxa2xx_mfp_config(ARRAY_AND_SIZE(em_x270_pin_config)); | 1005 | pxa2xx_mfp_config(ARRAY_AND_SIZE(em_x270_pin_config)); |
| 541 | 1006 | ||
| 1007 | mmc_cd = GPIO13_MMC_CD; | ||
| 1008 | nand_rb = GPIO56_NAND_RB; | ||
| 1009 | dm9000_flags = DM9000_PLATF_32BITONLY; | ||
| 1010 | } | ||
| 1011 | |||
| 1012 | static void __init em_x270_exeda_init(void) | ||
| 1013 | { | ||
| 1014 | pr_info("%s\n", __func__); | ||
| 1015 | pxa2xx_mfp_config(ARRAY_AND_SIZE(exeda_pin_config)); | ||
| 1016 | |||
| 1017 | mmc_cd = GPIO114_MMC_CD; | ||
| 1018 | nand_rb = GPIO20_NAND_RB; | ||
| 1019 | dm9000_flags = DM9000_PLATF_16BITONLY; | ||
| 1020 | } | ||
| 1021 | |||
| 1022 | static void __init em_x270_init(void) | ||
| 1023 | { | ||
| 1024 | pxa2xx_mfp_config(ARRAY_AND_SIZE(common_pin_config)); | ||
| 1025 | |||
| 1026 | if (machine_is_em_x270()) | ||
| 1027 | em_x270_module_init(); | ||
| 1028 | else if (machine_is_exeda()) | ||
| 1029 | em_x270_exeda_init(); | ||
| 1030 | else | ||
| 1031 | panic("Unsupported machine: %d\n", machine_arch_type); | ||
| 1032 | |||
| 1033 | em_x270_init_da9030(); | ||
| 542 | em_x270_init_dm9000(); | 1034 | em_x270_init_dm9000(); |
| 543 | em_x270_init_rtc(); | 1035 | em_x270_init_rtc(); |
| 544 | em_x270_init_nand(); | 1036 | em_x270_init_nand(); |
| 1037 | em_x270_init_nor(); | ||
| 545 | em_x270_init_lcd(); | 1038 | em_x270_init_lcd(); |
| 546 | em_x270_init_mmc(); | 1039 | em_x270_init_mmc(); |
| 547 | em_x270_init_ohci(); | 1040 | em_x270_init_ohci(); |
| 548 | em_x270_init_keypad(); | 1041 | em_x270_init_keypad(); |
| 549 | em_x270_init_gpio_keys(); | 1042 | em_x270_init_gpio_keys(); |
| 550 | em_x270_init_ac97(); | 1043 | em_x270_init_ac97(); |
| 1044 | em_x270_init_camera(); | ||
| 1045 | em_x270_init_spi(); | ||
| 551 | } | 1046 | } |
| 552 | 1047 | ||
| 553 | MACHINE_START(EM_X270, "Compulab EM-X270") | 1048 | MACHINE_START(EM_X270, "Compulab EM-X270") |
| @@ -559,3 +1054,13 @@ MACHINE_START(EM_X270, "Compulab EM-X270") | |||
| 559 | .timer = &pxa_timer, | 1054 | .timer = &pxa_timer, |
| 560 | .init_machine = em_x270_init, | 1055 | .init_machine = em_x270_init, |
| 561 | MACHINE_END | 1056 | MACHINE_END |
| 1057 | |||
| 1058 | MACHINE_START(EXEDA, "Compulab eXeda") | ||
| 1059 | .boot_params = 0xa0000100, | ||
| 1060 | .phys_io = 0x40000000, | ||
| 1061 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 1062 | .map_io = pxa_map_io, | ||
| 1063 | .init_irq = pxa27x_init_irq, | ||
| 1064 | .timer = &pxa_timer, | ||
| 1065 | .init_machine = em_x270_init, | ||
| 1066 | MACHINE_END | ||
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c index dfce7d5b659e..c60dadf847a6 100644 --- a/arch/arm/mach-pxa/eseries.c +++ b/arch/arm/mach-pxa/eseries.c | |||
| @@ -20,8 +20,7 @@ | |||
| 20 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
| 21 | #include <asm/mach-types.h> | 21 | #include <asm/mach-types.h> |
| 22 | 22 | ||
| 23 | #include <mach/mfp-pxa25x.h> | 23 | #include <mach/pxa25x.h> |
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/eseries-gpio.h> | 24 | #include <mach/eseries-gpio.h> |
| 26 | #include <mach/udc.h> | 25 | #include <mach/udc.h> |
| 27 | #include <mach/irda.h> | 26 | #include <mach/irda.h> |
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c index df5f822f3b6c..92ba16e1b6fc 100644 --- a/arch/arm/mach-pxa/ezx.c +++ b/arch/arm/mach-pxa/ezx.c | |||
| @@ -19,18 +19,16 @@ | |||
| 19 | #include <linux/input.h> | 19 | #include <linux/input.h> |
| 20 | 20 | ||
| 21 | #include <asm/setup.h> | 21 | #include <asm/setup.h> |
| 22 | #include <asm/mach-types.h> | ||
| 23 | #include <asm/mach/arch.h> | ||
| 24 | |||
| 25 | #include <mach/pxa27x.h> | ||
| 22 | #include <mach/pxafb.h> | 26 | #include <mach/pxafb.h> |
| 23 | #include <mach/ohci.h> | 27 | #include <mach/ohci.h> |
| 24 | #include <mach/i2c.h> | 28 | #include <mach/i2c.h> |
| 25 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
| 26 | #include <mach/pxa27x_keypad.h> | 30 | #include <mach/pxa27x_keypad.h> |
| 27 | 31 | ||
| 28 | #include <mach/mfp-pxa27x.h> | ||
| 29 | #include <mach/pxa-regs.h> | ||
| 30 | #include <mach/pxa2xx-regs.h> | ||
| 31 | #include <asm/mach-types.h> | ||
| 32 | #include <asm/mach/arch.h> | ||
| 33 | |||
| 34 | #include "devices.h" | 32 | #include "devices.h" |
| 35 | #include "generic.h" | 33 | #include "generic.h" |
| 36 | 34 | ||
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 0ccc91c92c44..3126a35aa002 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c | |||
| @@ -26,8 +26,9 @@ | |||
| 26 | #include <asm/mach/map.h> | 26 | #include <asm/mach/map.h> |
| 27 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
| 28 | 28 | ||
| 29 | #include <mach/pxa-regs.h> | ||
| 30 | #include <mach/reset.h> | 29 | #include <mach/reset.h> |
| 30 | #include <mach/gpio.h> | ||
| 31 | #include <mach/pxa2xx-gpio.h> | ||
| 31 | 32 | ||
| 32 | #include "generic.h" | 33 | #include "generic.h" |
| 33 | 34 | ||
| @@ -127,3 +128,33 @@ void __init pxa_map_io(void) | |||
| 127 | iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); | 128 | iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc)); |
| 128 | get_clk_frequency_khz(1); | 129 | get_clk_frequency_khz(1); |
| 129 | } | 130 | } |
| 131 | |||
| 132 | /* | ||
| 133 | * Configure pins for GPIO or other functions | ||
| 134 | */ | ||
| 135 | int pxa_gpio_mode(int gpio_mode) | ||
| 136 | { | ||
| 137 | unsigned long flags; | ||
| 138 | int gpio = gpio_mode & GPIO_MD_MASK_NR; | ||
| 139 | int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; | ||
| 140 | int gafr; | ||
| 141 | |||
| 142 | if (gpio > pxa_last_gpio) | ||
| 143 | return -EINVAL; | ||
| 144 | |||
| 145 | local_irq_save(flags); | ||
| 146 | if (gpio_mode & GPIO_DFLT_LOW) | ||
| 147 | GPCR(gpio) = GPIO_bit(gpio); | ||
| 148 | else if (gpio_mode & GPIO_DFLT_HIGH) | ||
| 149 | GPSR(gpio) = GPIO_bit(gpio); | ||
| 150 | if (gpio_mode & GPIO_MD_MASK_DIR) | ||
| 151 | GPDR(gpio) |= GPIO_bit(gpio); | ||
| 152 | else | ||
| 153 | GPDR(gpio) &= ~GPIO_bit(gpio); | ||
| 154 | gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2)); | ||
| 155 | GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2)); | ||
| 156 | local_irq_restore(flags); | ||
| 157 | |||
| 158 | return 0; | ||
| 159 | } | ||
| 160 | EXPORT_SYMBOL(pxa_gpio_mode); | ||
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h index dc876a8e6668..3465268ca716 100644 --- a/arch/arm/mach-pxa/generic.h +++ b/arch/arm/mach-pxa/generic.h | |||
| @@ -9,20 +9,17 @@ | |||
| 9 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
| 10 | */ | 10 | */ |
| 11 | 11 | ||
| 12 | typedef int (*set_wake_t)(unsigned int, unsigned int); | ||
| 13 | |||
| 14 | struct sys_timer; | 12 | struct sys_timer; |
| 15 | 13 | ||
| 16 | extern struct sys_timer pxa_timer; | 14 | extern struct sys_timer pxa_timer; |
| 17 | extern void __init pxa_init_irq(int irq_nr, set_wake_t fn); | 15 | extern void __init pxa_init_irq(int irq_nr, |
| 18 | extern void __init pxa_init_gpio(int gpio_nr, set_wake_t fn); | 16 | int (*set_wake)(unsigned int, unsigned int)); |
| 19 | extern void __init pxa25x_init_irq(void); | 17 | extern void __init pxa25x_init_irq(void); |
| 20 | extern void __init pxa27x_init_irq(void); | 18 | extern void __init pxa27x_init_irq(void); |
| 21 | extern void __init pxa3xx_init_irq(void); | 19 | extern void __init pxa3xx_init_irq(void); |
| 22 | extern void __init pxa_map_io(void); | 20 | extern void __init pxa_map_io(void); |
| 23 | 21 | ||
| 24 | extern unsigned int get_clk_frequency_khz(int info); | 22 | extern unsigned int get_clk_frequency_khz(int info); |
| 25 | extern int pxa_last_gpio; | ||
| 26 | 23 | ||
| 27 | #define SET_BANK(__nr,__start,__size) \ | 24 | #define SET_BANK(__nr,__start,__size) \ |
| 28 | mi->bank[__nr].start = (__start), \ | 25 | mi->bank[__nr].start = (__start), \ |
diff --git a/arch/arm/mach-pxa/gpio.c b/arch/arm/mach-pxa/gpio.c deleted file mode 100644 index 5fec1e479cb3..000000000000 --- a/arch/arm/mach-pxa/gpio.c +++ /dev/null | |||
| @@ -1,453 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-pxa/gpio.c | ||
| 3 | * | ||
| 4 | * Generic PXA GPIO handling | ||
| 5 | * | ||
| 6 | * Author: Nicolas Pitre | ||
| 7 | * Created: Jun 15, 2001 | ||
| 8 | * Copyright: MontaVista Software Inc. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/module.h> | ||
| 17 | #include <linux/irq.h> | ||
| 18 | #include <linux/sysdev.h> | ||
| 19 | #include <linux/io.h> | ||
| 20 | |||
| 21 | #include <asm/gpio.h> | ||
| 22 | #include <mach/hardware.h> | ||
| 23 | #include <mach/pxa-regs.h> | ||
| 24 | #include <mach/pxa2xx-gpio.h> | ||
| 25 | |||
| 26 | #include "generic.h" | ||
| 27 | |||
| 28 | #define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) | ||
| 29 | #define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) | ||
| 30 | #define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) | ||
| 31 | #define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) | ||
| 32 | |||
| 33 | #define GPLR_OFFSET 0x00 | ||
| 34 | #define GPDR_OFFSET 0x0C | ||
| 35 | #define GPSR_OFFSET 0x18 | ||
| 36 | #define GPCR_OFFSET 0x24 | ||
| 37 | #define GRER_OFFSET 0x30 | ||
| 38 | #define GFER_OFFSET 0x3C | ||
| 39 | #define GEDR_OFFSET 0x48 | ||
| 40 | |||
| 41 | struct pxa_gpio_chip { | ||
| 42 | struct gpio_chip chip; | ||
| 43 | void __iomem *regbase; | ||
| 44 | }; | ||
| 45 | |||
| 46 | int pxa_last_gpio; | ||
| 47 | |||
| 48 | #ifdef CONFIG_CPU_PXA26x | ||
| 49 | /* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, | ||
| 50 | * as well as their Alternate Function value being '1' for GPIO in GAFRx. | ||
| 51 | */ | ||
| 52 | static int __gpio_is_inverted(unsigned gpio) | ||
| 53 | { | ||
| 54 | return cpu_is_pxa25x() && gpio > 85; | ||
| 55 | } | ||
| 56 | #else | ||
| 57 | #define __gpio_is_inverted(gpio) (0) | ||
| 58 | #endif | ||
| 59 | |||
| 60 | /* | ||
| 61 | * Configure pins for GPIO or other functions | ||
| 62 | */ | ||
| 63 | int pxa_gpio_mode(int gpio_mode) | ||
| 64 | { | ||
| 65 | unsigned long flags; | ||
| 66 | int gpio = gpio_mode & GPIO_MD_MASK_NR; | ||
| 67 | int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; | ||
| 68 | int gafr; | ||
| 69 | |||
| 70 | if (gpio > pxa_last_gpio) | ||
| 71 | return -EINVAL; | ||
| 72 | |||
| 73 | local_irq_save(flags); | ||
| 74 | if (gpio_mode & GPIO_DFLT_LOW) | ||
| 75 | GPCR(gpio) = GPIO_bit(gpio); | ||
| 76 | else if (gpio_mode & GPIO_DFLT_HIGH) | ||
| 77 | GPSR(gpio) = GPIO_bit(gpio); | ||
| 78 | if (gpio_mode & GPIO_MD_MASK_DIR) | ||
| 79 | GPDR(gpio) |= GPIO_bit(gpio); | ||
| 80 | else | ||
| 81 | GPDR(gpio) &= ~GPIO_bit(gpio); | ||
| 82 | gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2)); | ||
| 83 | GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2)); | ||
| 84 | local_irq_restore(flags); | ||
| 85 | |||
| 86 | return 0; | ||
| 87 | } | ||
| 88 | EXPORT_SYMBOL(pxa_gpio_mode); | ||
| 89 | |||
| 90 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | ||
| 91 | { | ||
| 92 | unsigned long flags; | ||
| 93 | u32 mask = 1 << offset; | ||
| 94 | u32 value; | ||
| 95 | struct pxa_gpio_chip *pxa; | ||
| 96 | void __iomem *gpdr; | ||
| 97 | |||
| 98 | pxa = container_of(chip, struct pxa_gpio_chip, chip); | ||
| 99 | gpdr = pxa->regbase + GPDR_OFFSET; | ||
| 100 | local_irq_save(flags); | ||
| 101 | value = __raw_readl(gpdr); | ||
| 102 | if (__gpio_is_inverted(chip->base + offset)) | ||
| 103 | value |= mask; | ||
| 104 | else | ||
| 105 | value &= ~mask; | ||
| 106 | __raw_writel(value, gpdr); | ||
| 107 | local_irq_restore(flags); | ||
| 108 | |||
| 109 | return 0; | ||
| 110 | } | ||
| 111 | |||
| 112 | static int pxa_gpio_direction_output(struct gpio_chip *chip, | ||
| 113 | unsigned offset, int value) | ||
| 114 | { | ||
| 115 | unsigned long flags; | ||
| 116 | u32 mask = 1 << offset; | ||
| 117 | u32 tmp; | ||
| 118 | struct pxa_gpio_chip *pxa; | ||
| 119 | void __iomem *gpdr; | ||
| 120 | |||
| 121 | pxa = container_of(chip, struct pxa_gpio_chip, chip); | ||
| 122 | __raw_writel(mask, | ||
| 123 | pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET)); | ||
| 124 | gpdr = pxa->regbase + GPDR_OFFSET; | ||
| 125 | local_irq_save(flags); | ||
| 126 | tmp = __raw_readl(gpdr); | ||
| 127 | if (__gpio_is_inverted(chip->base + offset)) | ||
| 128 | tmp &= ~mask; | ||
| 129 | else | ||
| 130 | tmp |= mask; | ||
| 131 | __raw_writel(tmp, gpdr); | ||
| 132 | local_irq_restore(flags); | ||
| 133 | |||
| 134 | return 0; | ||
| 135 | } | ||
| 136 | |||
| 137 | /* | ||
| 138 | * Return GPIO level | ||
| 139 | */ | ||
| 140 | static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) | ||
| 141 | { | ||
| 142 | u32 mask = 1 << offset; | ||
| 143 | struct pxa_gpio_chip *pxa; | ||
| 144 | |||
| 145 | pxa = container_of(chip, struct pxa_gpio_chip, chip); | ||
| 146 | return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask; | ||
| 147 | } | ||
| 148 | |||
| 149 | /* | ||
| 150 | * Set output GPIO level | ||
| 151 | */ | ||
| 152 | static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | ||
| 153 | { | ||
| 154 | u32 mask = 1 << offset; | ||
| 155 | struct pxa_gpio_chip *pxa; | ||
| 156 | |||
| 157 | pxa = container_of(chip, struct pxa_gpio_chip, chip); | ||
| 158 | |||
| 159 | if (value) | ||
| 160 | __raw_writel(mask, pxa->regbase + GPSR_OFFSET); | ||
| 161 | else | ||
| 162 | __raw_writel(mask, pxa->regbase + GPCR_OFFSET); | ||
| 163 | } | ||
| 164 | |||
| 165 | #define GPIO_CHIP(_n) \ | ||
| 166 | [_n] = { \ | ||
| 167 | .regbase = GPIO##_n##_BASE, \ | ||
| 168 | .chip = { \ | ||
| 169 | .label = "gpio-" #_n, \ | ||
| 170 | .direction_input = pxa_gpio_direction_input, \ | ||
| 171 | .direction_output = pxa_gpio_direction_output, \ | ||
| 172 | .get = pxa_gpio_get, \ | ||
| 173 | .set = pxa_gpio_set, \ | ||
| 174 | .base = (_n) * 32, \ | ||
| 175 | .ngpio = 32, \ | ||
| 176 | }, \ | ||
| 177 | } | ||
| 178 | |||
| 179 | static struct pxa_gpio_chip pxa_gpio_chip[] = { | ||
| 180 | GPIO_CHIP(0), | ||
| 181 | GPIO_CHIP(1), | ||
| 182 | GPIO_CHIP(2), | ||
| 183 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
| 184 | GPIO_CHIP(3), | ||
| 185 | #endif | ||
| 186 | }; | ||
| 187 | |||
| 188 | /* | ||
| 189 | * PXA GPIO edge detection for IRQs: | ||
| 190 | * IRQs are generated on Falling-Edge, Rising-Edge, or both. | ||
| 191 | * Use this instead of directly setting GRER/GFER. | ||
| 192 | */ | ||
| 193 | |||
| 194 | static unsigned long GPIO_IRQ_rising_edge[4]; | ||
| 195 | static unsigned long GPIO_IRQ_falling_edge[4]; | ||
| 196 | static unsigned long GPIO_IRQ_mask[4]; | ||
| 197 | |||
| 198 | /* | ||
| 199 | * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate | ||
| 200 | * function of a GPIO, and GPDRx cannot be altered once configured. It | ||
| 201 | * is attributed as "occupied" here (I know this terminology isn't | ||
| 202 | * accurate, you are welcome to propose a better one :-) | ||
| 203 | */ | ||
| 204 | static int __gpio_is_occupied(unsigned gpio) | ||
| 205 | { | ||
| 206 | if (cpu_is_pxa27x() || cpu_is_pxa25x()) { | ||
| 207 | int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3; | ||
| 208 | int dir = GPDR(gpio) & GPIO_bit(gpio); | ||
| 209 | |||
| 210 | if (__gpio_is_inverted(gpio)) | ||
| 211 | return af != 1 || dir == 0; | ||
| 212 | else | ||
| 213 | return af != 0 || dir != 0; | ||
| 214 | } | ||
| 215 | |||
| 216 | return 0; | ||
| 217 | } | ||
| 218 | |||
| 219 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | ||
| 220 | { | ||
| 221 | int gpio, idx; | ||
| 222 | |||
| 223 | gpio = IRQ_TO_GPIO(irq); | ||
| 224 | idx = gpio >> 5; | ||
| 225 | |||
| 226 | if (type == IRQ_TYPE_PROBE) { | ||
| 227 | /* Don't mess with enabled GPIOs using preconfigured edges or | ||
| 228 | * GPIOs set to alternate function or to output during probe | ||
| 229 | */ | ||
| 230 | if ((GPIO_IRQ_rising_edge[idx] & GPIO_bit(gpio)) || | ||
| 231 | (GPIO_IRQ_falling_edge[idx] & GPIO_bit(gpio))) | ||
| 232 | return 0; | ||
| 233 | |||
| 234 | if (__gpio_is_occupied(gpio)) | ||
| 235 | return 0; | ||
| 236 | |||
| 237 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | ||
| 238 | } | ||
| 239 | |||
| 240 | if (__gpio_is_inverted(gpio)) | ||
| 241 | GPDR(gpio) |= GPIO_bit(gpio); | ||
| 242 | else | ||
| 243 | GPDR(gpio) &= ~GPIO_bit(gpio); | ||
| 244 | |||
| 245 | if (type & IRQ_TYPE_EDGE_RISING) | ||
| 246 | __set_bit(gpio, GPIO_IRQ_rising_edge); | ||
| 247 | else | ||
| 248 | __clear_bit(gpio, GPIO_IRQ_rising_edge); | ||
| 249 | |||
| 250 | if (type & IRQ_TYPE_EDGE_FALLING) | ||
| 251 | __set_bit(gpio, GPIO_IRQ_falling_edge); | ||
| 252 | else | ||
| 253 | __clear_bit(gpio, GPIO_IRQ_falling_edge); | ||
| 254 | |||
| 255 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; | ||
| 256 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; | ||
| 257 | |||
| 258 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio, | ||
| 259 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), | ||
| 260 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); | ||
| 261 | return 0; | ||
| 262 | } | ||
| 263 | |||
| 264 | /* | ||
| 265 | * GPIO IRQs must be acknowledged. This is for GPIO 0 and 1. | ||
| 266 | */ | ||
| 267 | |||
| 268 | static void pxa_ack_low_gpio(unsigned int irq) | ||
| 269 | { | ||
| 270 | GEDR0 = (1 << (irq - IRQ_GPIO0)); | ||
| 271 | } | ||
| 272 | |||
| 273 | static void pxa_mask_low_gpio(unsigned int irq) | ||
| 274 | { | ||
| 275 | ICMR &= ~(1 << (irq - PXA_IRQ(0))); | ||
| 276 | } | ||
| 277 | |||
| 278 | static void pxa_unmask_low_gpio(unsigned int irq) | ||
| 279 | { | ||
| 280 | ICMR |= 1 << (irq - PXA_IRQ(0)); | ||
| 281 | } | ||
| 282 | |||
| 283 | static struct irq_chip pxa_low_gpio_chip = { | ||
| 284 | .name = "GPIO-l", | ||
| 285 | .ack = pxa_ack_low_gpio, | ||
| 286 | .mask = pxa_mask_low_gpio, | ||
| 287 | .unmask = pxa_unmask_low_gpio, | ||
| 288 | .set_type = pxa_gpio_irq_type, | ||
| 289 | }; | ||
| 290 | |||
| 291 | /* | ||
| 292 | * Demux handler for GPIO>=2 edge detect interrupts | ||
| 293 | */ | ||
| 294 | |||
| 295 | #define GEDR_BITS (sizeof(gedr) * BITS_PER_BYTE) | ||
| 296 | |||
| 297 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) | ||
| 298 | { | ||
| 299 | int loop, bit, n; | ||
| 300 | unsigned long gedr[4]; | ||
| 301 | |||
| 302 | do { | ||
| 303 | gedr[0] = GEDR0 & GPIO_IRQ_mask[0] & ~3; | ||
| 304 | gedr[1] = GEDR1 & GPIO_IRQ_mask[1]; | ||
| 305 | gedr[2] = GEDR2 & GPIO_IRQ_mask[2]; | ||
| 306 | gedr[3] = GEDR3 & GPIO_IRQ_mask[3]; | ||
| 307 | |||
| 308 | GEDR0 = gedr[0]; GEDR1 = gedr[1]; | ||
| 309 | GEDR2 = gedr[2]; GEDR3 = gedr[3]; | ||
| 310 | |||
| 311 | loop = 0; | ||
| 312 | bit = find_first_bit(gedr, GEDR_BITS); | ||
| 313 | while (bit < GEDR_BITS) { | ||
| 314 | loop = 1; | ||
| 315 | |||
| 316 | n = PXA_GPIO_IRQ_BASE + bit; | ||
| 317 | generic_handle_irq(n); | ||
| 318 | |||
| 319 | bit = find_next_bit(gedr, GEDR_BITS, bit + 1); | ||
| 320 | } | ||
| 321 | } while (loop); | ||
| 322 | } | ||
| 323 | |||
| 324 | static void pxa_ack_muxed_gpio(unsigned int irq) | ||
| 325 | { | ||
| 326 | int gpio = irq - IRQ_GPIO(2) + 2; | ||
| 327 | GEDR(gpio) = GPIO_bit(gpio); | ||
| 328 | } | ||
| 329 | |||
| 330 | static void pxa_mask_muxed_gpio(unsigned int irq) | ||
| 331 | { | ||
| 332 | int gpio = irq - IRQ_GPIO(2) + 2; | ||
| 333 | __clear_bit(gpio, GPIO_IRQ_mask); | ||
| 334 | GRER(gpio) &= ~GPIO_bit(gpio); | ||
| 335 | GFER(gpio) &= ~GPIO_bit(gpio); | ||
| 336 | } | ||
| 337 | |||
| 338 | static void pxa_unmask_muxed_gpio(unsigned int irq) | ||
| 339 | { | ||
| 340 | int gpio = irq - IRQ_GPIO(2) + 2; | ||
| 341 | int idx = gpio >> 5; | ||
| 342 | __set_bit(gpio, GPIO_IRQ_mask); | ||
| 343 | GRER(gpio) = GPIO_IRQ_rising_edge[idx] & GPIO_IRQ_mask[idx]; | ||
| 344 | GFER(gpio) = GPIO_IRQ_falling_edge[idx] & GPIO_IRQ_mask[idx]; | ||
| 345 | } | ||
| 346 | |||
| 347 | static struct irq_chip pxa_muxed_gpio_chip = { | ||
| 348 | .name = "GPIO", | ||
| 349 | .ack = pxa_ack_muxed_gpio, | ||
| 350 | .mask = pxa_mask_muxed_gpio, | ||
| 351 | .unmask = pxa_unmask_muxed_gpio, | ||
| 352 | .set_type = pxa_gpio_irq_type, | ||
| 353 | }; | ||
| 354 | |||
| 355 | void __init pxa_init_gpio(int gpio_nr, set_wake_t fn) | ||
| 356 | { | ||
| 357 | int irq, i, gpio; | ||
| 358 | |||
| 359 | pxa_last_gpio = gpio_nr - 1; | ||
| 360 | |||
| 361 | /* clear all GPIO edge detects */ | ||
| 362 | for (i = 0; i < gpio_nr; i += 32) { | ||
| 363 | GFER(i) = 0; | ||
| 364 | GRER(i) = 0; | ||
| 365 | GEDR(i) = GEDR(i); | ||
| 366 | } | ||
| 367 | |||
| 368 | /* GPIO 0 and 1 must have their mask bit always set */ | ||
| 369 | GPIO_IRQ_mask[0] = 3; | ||
| 370 | |||
| 371 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | ||
| 372 | set_irq_chip(irq, &pxa_low_gpio_chip); | ||
| 373 | set_irq_handler(irq, handle_edge_irq); | ||
| 374 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
| 375 | } | ||
| 376 | |||
| 377 | for (irq = IRQ_GPIO(2); irq < IRQ_GPIO(gpio_nr); irq++) { | ||
| 378 | set_irq_chip(irq, &pxa_muxed_gpio_chip); | ||
| 379 | set_irq_handler(irq, handle_edge_irq); | ||
| 380 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
| 381 | } | ||
| 382 | |||
| 383 | /* Install handler for GPIO>=2 edge detect interrupts */ | ||
| 384 | set_irq_chained_handler(IRQ_GPIO_2_x, pxa_gpio_demux_handler); | ||
| 385 | |||
| 386 | pxa_low_gpio_chip.set_wake = fn; | ||
| 387 | pxa_muxed_gpio_chip.set_wake = fn; | ||
| 388 | |||
| 389 | /* add a GPIO chip for each register bank. | ||
| 390 | * the last PXA25x register only contains 21 GPIOs | ||
| 391 | */ | ||
| 392 | for (gpio = 0, i = 0; gpio < gpio_nr; gpio += 32, i++) { | ||
| 393 | if (gpio + 32 > gpio_nr) | ||
| 394 | pxa_gpio_chip[i].chip.ngpio = gpio_nr - gpio; | ||
| 395 | gpiochip_add(&pxa_gpio_chip[i].chip); | ||
| 396 | } | ||
| 397 | } | ||
| 398 | |||
| 399 | #ifdef CONFIG_PM | ||
| 400 | |||
| 401 | static unsigned long saved_gplr[4]; | ||
| 402 | static unsigned long saved_gpdr[4]; | ||
| 403 | static unsigned long saved_grer[4]; | ||
| 404 | static unsigned long saved_gfer[4]; | ||
| 405 | |||
| 406 | static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state) | ||
| 407 | { | ||
| 408 | int i, gpio; | ||
| 409 | |||
| 410 | for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) { | ||
| 411 | saved_gplr[i] = GPLR(gpio); | ||
| 412 | saved_gpdr[i] = GPDR(gpio); | ||
| 413 | saved_grer[i] = GRER(gpio); | ||
| 414 | saved_gfer[i] = GFER(gpio); | ||
| 415 | |||
| 416 | /* Clear GPIO transition detect bits */ | ||
| 417 | GEDR(gpio) = GEDR(gpio); | ||
| 418 | } | ||
| 419 | return 0; | ||
| 420 | } | ||
| 421 | |||
| 422 | static int pxa_gpio_resume(struct sys_device *dev) | ||
| 423 | { | ||
| 424 | int i, gpio; | ||
| 425 | |||
| 426 | for (gpio = 0, i = 0; gpio < pxa_last_gpio; gpio += 32, i++) { | ||
| 427 | /* restore level with set/clear */ | ||
| 428 | GPSR(gpio) = saved_gplr[i]; | ||
| 429 | GPCR(gpio) = ~saved_gplr[i]; | ||
| 430 | |||
| 431 | GRER(gpio) = saved_grer[i]; | ||
| 432 | GFER(gpio) = saved_gfer[i]; | ||
| 433 | GPDR(gpio) = saved_gpdr[i]; | ||
| 434 | } | ||
| 435 | return 0; | ||
| 436 | } | ||
| 437 | #else | ||
| 438 | #define pxa_gpio_suspend NULL | ||
| 439 | #define pxa_gpio_resume NULL | ||
| 440 | #endif | ||
| 441 | |||
| 442 | struct sysdev_class pxa_gpio_sysclass = { | ||
| 443 | .name = "gpio", | ||
| 444 | .suspend = pxa_gpio_suspend, | ||
| 445 | .resume = pxa_gpio_resume, | ||
| 446 | }; | ||
| 447 | |||
| 448 | static int __init pxa_gpio_init(void) | ||
| 449 | { | ||
| 450 | return sysdev_class_register(&pxa_gpio_sysclass); | ||
| 451 | } | ||
| 452 | |||
| 453 | core_initcall(pxa_gpio_init); | ||
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index e296ce11658c..ca9912ea78d9 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c | |||
| @@ -38,14 +38,12 @@ | |||
| 38 | #include <asm/mach/map.h> | 38 | #include <asm/mach/map.h> |
| 39 | #include <asm/mach/irq.h> | 39 | #include <asm/mach/irq.h> |
| 40 | #include <asm/mach/flash.h> | 40 | #include <asm/mach/flash.h> |
| 41 | |||
| 42 | #include <mach/pxa25x.h> | ||
| 41 | #include <mach/mmc.h> | 43 | #include <mach/mmc.h> |
| 42 | #include <mach/udc.h> | 44 | #include <mach/udc.h> |
| 43 | #include <mach/gumstix.h> | 45 | #include <mach/gumstix.h> |
| 44 | 46 | ||
| 45 | #include <mach/pxa-regs.h> | ||
| 46 | #include <mach/pxa2xx-regs.h> | ||
| 47 | #include <mach/mfp-pxa25x.h> | ||
| 48 | |||
| 49 | #include "generic.h" | 47 | #include "generic.h" |
| 50 | 48 | ||
| 51 | static struct resource flash_resource = { | 49 | static struct resource flash_resource = { |
| @@ -191,6 +189,11 @@ int __attribute__((weak)) am200_init(void) | |||
| 191 | return 0; | 189 | return 0; |
| 192 | } | 190 | } |
| 193 | 191 | ||
| 192 | int __attribute__((weak)) am300_init(void) | ||
| 193 | { | ||
| 194 | return 0; | ||
| 195 | } | ||
| 196 | |||
| 194 | static void __init carrier_board_init(void) | 197 | static void __init carrier_board_init(void) |
| 195 | { | 198 | { |
| 196 | /* | 199 | /* |
| @@ -198,6 +201,7 @@ static void __init carrier_board_init(void) | |||
| 198 | * they cannot be detected programatically | 201 | * they cannot be detected programatically |
| 199 | */ | 202 | */ |
| 200 | am200_init(); | 203 | am200_init(); |
| 204 | am300_init(); | ||
| 201 | } | 205 | } |
| 202 | 206 | ||
| 203 | static void __init gumstix_init(void) | 207 | static void __init gumstix_init(void) |
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c index da6e4422c0f3..6a197fb5c095 100644 --- a/arch/arm/mach-pxa/h5000.c +++ b/arch/arm/mach-pxa/h5000.c | |||
| @@ -24,14 +24,15 @@ | |||
| 24 | #include <linux/mtd/mtd.h> | 24 | #include <linux/mtd/mtd.h> |
| 25 | #include <linux/mtd/partitions.h> | 25 | #include <linux/mtd/partitions.h> |
| 26 | #include <linux/mtd/physmap.h> | 26 | #include <linux/mtd/physmap.h> |
| 27 | |||
| 27 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 28 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
| 29 | #include <asm/mach/map.h> | 30 | #include <asm/mach/map.h> |
| 31 | |||
| 32 | #include <mach/pxa25x.h> | ||
| 30 | #include <mach/h5000.h> | 33 | #include <mach/h5000.h> |
| 31 | #include <mach/pxa-regs.h> | ||
| 32 | #include <mach/pxa2xx-regs.h> | ||
| 33 | #include <mach/mfp-pxa25x.h> | ||
| 34 | #include <mach/udc.h> | 34 | #include <mach/udc.h> |
| 35 | |||
| 35 | #include "generic.h" | 36 | #include "generic.h" |
| 36 | 37 | ||
| 37 | /* | 38 | /* |
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c new file mode 100644 index 000000000000..cea99fe65b97 --- /dev/null +++ b/arch/arm/mach-pxa/himalaya.c | |||
| @@ -0,0 +1,166 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mach-pxa/himalaya.c | ||
| 3 | * | ||
| 4 | * Hardware definitions for the HTC Himalaya | ||
| 5 | * | ||
| 6 | * Based on 2.6.21-hh20's himalaya.c and himalaya_lcd.c | ||
| 7 | * | ||
| 8 | * Copyright (c) 2008 Zbynek Michl <Zbynek.Michl@seznam.cz> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/init.h> | ||
| 17 | #include <linux/device.h> | ||
| 18 | #include <linux/fb.h> | ||
| 19 | #include <linux/platform_device.h> | ||
| 20 | |||
| 21 | #include <video/w100fb.h> | ||
| 22 | |||
| 23 | #include <asm/setup.h> | ||
| 24 | #include <asm/mach-types.h> | ||
| 25 | #include <asm/mach/arch.h> | ||
| 26 | |||
| 27 | #include <mach/mfp-pxa25x.h> | ||
| 28 | #include <mach/hardware.h> | ||
| 29 | |||
| 30 | #include "generic.h" | ||
| 31 | |||
| 32 | /* ---------------------- Himalaya LCD definitions -------------------- */ | ||
| 33 | |||
| 34 | static struct w100_gen_regs himalaya_lcd_regs = { | ||
| 35 | .lcd_format = 0x00000003, | ||
| 36 | .lcdd_cntl1 = 0x00000000, | ||
| 37 | .lcdd_cntl2 = 0x0003ffff, | ||
| 38 | .genlcd_cntl1 = 0x00fff003, | ||
| 39 | .genlcd_cntl2 = 0x00000003, | ||
| 40 | .genlcd_cntl3 = 0x000102aa, | ||
| 41 | }; | ||
| 42 | |||
| 43 | static struct w100_mode himalaya4_lcd_mode = { | ||
| 44 | .xres = 240, | ||
| 45 | .yres = 320, | ||
| 46 | .left_margin = 0, | ||
| 47 | .right_margin = 31, | ||
| 48 | .upper_margin = 15, | ||
| 49 | .lower_margin = 0, | ||
| 50 | .crtc_ss = 0x80150014, | ||
| 51 | .crtc_ls = 0xa0fb00f7, | ||
| 52 | .crtc_gs = 0xc0080007, | ||
| 53 | .crtc_vpos_gs = 0x00080007, | ||
| 54 | .crtc_rev = 0x0000000a, | ||
| 55 | .crtc_dclk = 0x81700030, | ||
| 56 | .crtc_gclk = 0x8015010f, | ||
| 57 | .crtc_goe = 0x00000000, | ||
| 58 | .pll_freq = 80, | ||
| 59 | .pixclk_divider = 15, | ||
| 60 | .pixclk_divider_rotated = 15, | ||
| 61 | .pixclk_src = CLK_SRC_PLL, | ||
| 62 | .sysclk_divider = 0, | ||
| 63 | .sysclk_src = CLK_SRC_PLL, | ||
| 64 | }; | ||
| 65 | |||
| 66 | static struct w100_mode himalaya6_lcd_mode = { | ||
| 67 | .xres = 240, | ||
| 68 | .yres = 320, | ||
| 69 | .left_margin = 9, | ||
| 70 | .right_margin = 8, | ||
| 71 | .upper_margin = 5, | ||
| 72 | .lower_margin = 4, | ||
| 73 | .crtc_ss = 0x80150014, | ||
| 74 | .crtc_ls = 0xa0fb00f7, | ||
| 75 | .crtc_gs = 0xc0080007, | ||
| 76 | .crtc_vpos_gs = 0x00080007, | ||
| 77 | .crtc_rev = 0x0000000a, | ||
| 78 | .crtc_dclk = 0xa1700030, | ||
| 79 | .crtc_gclk = 0x8015010f, | ||
| 80 | .crtc_goe = 0x00000000, | ||
| 81 | .pll_freq = 95, | ||
| 82 | .pixclk_divider = 0xb, | ||
| 83 | .pixclk_divider_rotated = 4, | ||
| 84 | .pixclk_src = CLK_SRC_PLL, | ||
| 85 | .sysclk_divider = 1, | ||
| 86 | .sysclk_src = CLK_SRC_PLL, | ||
| 87 | }; | ||
| 88 | |||
| 89 | static struct w100_gpio_regs himalaya_w100_gpio_info = { | ||
| 90 | .init_data1 = 0xffff0000, /* GPIO_DATA */ | ||
| 91 | .gpio_dir1 = 0x00000000, /* GPIO_CNTL1 */ | ||
| 92 | .gpio_oe1 = 0x003c0000, /* GPIO_CNTL2 */ | ||
| 93 | .init_data2 = 0x00000000, /* GPIO_DATA2 */ | ||
| 94 | .gpio_dir2 = 0x00000000, /* GPIO_CNTL3 */ | ||
| 95 | .gpio_oe2 = 0x00000000, /* GPIO_CNTL4 */ | ||
| 96 | }; | ||
| 97 | |||
| 98 | static struct w100fb_mach_info himalaya_fb_info = { | ||
| 99 | .num_modes = 1, | ||
| 100 | .regs = &himalaya_lcd_regs, | ||
| 101 | .gpio = &himalaya_w100_gpio_info, | ||
| 102 | .xtal_freq = 16000000, | ||
| 103 | }; | ||
| 104 | |||
| 105 | static struct resource himalaya_fb_resources[] = { | ||
| 106 | [0] = { | ||
| 107 | .start = 0x08000000, | ||
| 108 | .end = 0x08ffffff, | ||
| 109 | .flags = IORESOURCE_MEM, | ||
| 110 | }, | ||
| 111 | }; | ||
| 112 | |||
| 113 | static struct platform_device himalaya_fb_device = { | ||
| 114 | .name = "w100fb", | ||
| 115 | .id = -1, | ||
| 116 | .dev = { | ||
| 117 | .platform_data = &himalaya_fb_info, | ||
| 118 | }, | ||
| 119 | .num_resources = ARRAY_SIZE(himalaya_fb_resources), | ||
| 120 | .resource = himalaya_fb_resources, | ||
| 121 | }; | ||
| 122 | |||
| 123 | /* ----------------------------------------------------------------------- */ | ||
| 124 | |||
| 125 | static struct platform_device *devices[] __initdata = { | ||
| 126 | &himalaya_fb_device, | ||
| 127 | }; | ||
| 128 | |||
| 129 | static void __init himalaya_lcd_init(void) | ||
| 130 | { | ||
| 131 | int himalaya_boardid; | ||
| 132 | |||
| 133 | himalaya_boardid = 0x4; /* hardcoded (detection needs ASIC3 functions) */ | ||
| 134 | printk(KERN_INFO "himalaya LCD Driver init. boardid=%d\n", | ||
| 135 | himalaya_boardid); | ||
| 136 | |||
| 137 | switch (himalaya_boardid) { | ||
| 138 | case 0x4: | ||
| 139 | himalaya_fb_info.modelist = &himalaya4_lcd_mode; | ||
| 140 | break; | ||
| 141 | case 0x6: | ||
| 142 | himalaya_fb_info.modelist = &himalaya6_lcd_mode; | ||
| 143 | break; | ||
| 144 | default: | ||
| 145 | printk(KERN_INFO "himalaya lcd_init: unknown boardid=%d. Using 0x4\n", | ||
| 146 | himalaya_boardid); | ||
| 147 | himalaya_fb_info.modelist = &himalaya4_lcd_mode; | ||
| 148 | } | ||
| 149 | } | ||
| 150 | |||
| 151 | static void __init himalaya_init(void) | ||
| 152 | { | ||
| 153 | himalaya_lcd_init(); | ||
| 154 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 155 | } | ||
| 156 | |||
| 157 | |||
| 158 | MACHINE_START(HIMALAYA, "HTC Himalaya") | ||
| 159 | .phys_io = 0x40000000, | ||
| 160 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 161 | .boot_params = 0xa0000100, | ||
| 162 | .map_io = pxa_map_io, | ||
| 163 | .init_irq = pxa25x_init_irq, | ||
| 164 | .init_machine = himalaya_init, | ||
| 165 | .timer = &pxa_timer, | ||
| 166 | MACHINE_END | ||
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c index 013b15baa034..b6243b59d9be 100644 --- a/arch/arm/mach-pxa/idp.c +++ b/arch/arm/mach-pxa/idp.c | |||
| @@ -31,8 +31,7 @@ | |||
| 31 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
| 32 | #include <asm/mach/map.h> | 32 | #include <asm/mach/map.h> |
| 33 | 33 | ||
| 34 | #include <mach/pxa-regs.h> | 34 | #include <mach/pxa25x.h> |
| 35 | #include <mach/mfp-pxa25x.h> | ||
| 36 | #include <mach/idp.h> | 35 | #include <mach/idp.h> |
| 37 | #include <mach/pxafb.h> | 36 | #include <mach/pxafb.h> |
| 38 | #include <mach/bitfield.h> | 37 | #include <mach/bitfield.h> |
diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c index 364c5e271330..2121309b2474 100644 --- a/arch/arm/mach-pxa/imote2.c +++ b/arch/arm/mach-pxa/imote2.c | |||
| @@ -28,11 +28,8 @@ | |||
| 28 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
| 29 | #include <asm/mach/flash.h> | 29 | #include <asm/mach/flash.h> |
| 30 | 30 | ||
| 31 | #include <mach/pxa27x.h> | ||
| 31 | #include <mach/i2c.h> | 32 | #include <mach/i2c.h> |
| 32 | #include <mach/pxa-regs.h> | ||
| 33 | #include <mach/pxa2xx-regs.h> | ||
| 34 | #include <mach/mfp-pxa27x.h> | ||
| 35 | #include <mach/regs-ssp.h> | ||
| 36 | #include <mach/udc.h> | 33 | #include <mach/udc.h> |
| 37 | #include <mach/mmc.h> | 34 | #include <mach/mmc.h> |
| 38 | #include <mach/pxa2xx_spi.h> | 35 | #include <mach/pxa2xx_spi.h> |
diff --git a/arch/arm/mach-pxa/include/mach/colibri.h b/arch/arm/mach-pxa/include/mach/colibri.h index 2ae373fb5675..3f2a01d6a03c 100644 --- a/arch/arm/mach-pxa/include/mach/colibri.h +++ b/arch/arm/mach-pxa/include/mach/colibri.h | |||
| @@ -1,19 +1,31 @@ | |||
| 1 | #ifndef _COLIBRI_H_ | 1 | #ifndef _COLIBRI_H_ |
| 2 | #define _COLIBRI_H_ | 2 | #define _COLIBRI_H_ |
| 3 | /* | ||
| 4 | * common settings for all modules | ||
| 5 | */ | ||
| 6 | |||
| 7 | #if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE) | ||
| 8 | extern void colibri_pxa3xx_init_mmc(mfp_cfg_t *pins, int len, int detect_pin); | ||
| 9 | #else | ||
| 10 | static inline void colibri_pxa3xx_init_mmc(mfp_cfg_t *, int, int) {} | ||
| 11 | #endif | ||
| 12 | |||
| 13 | #if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE) | ||
| 14 | extern void colibri_pxa3xx_init_lcd(int bl_pin); | ||
| 15 | #else | ||
| 16 | static inline void colibri_pxa3xx_init_lcd(int) {} | ||
| 17 | #endif | ||
| 3 | 18 | ||
| 4 | /* physical memory regions */ | 19 | /* physical memory regions */ |
| 5 | #define COLIBRI_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ | ||
| 6 | #define COLIBRI_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet DM9000 region */ | ||
| 7 | #define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */ | 20 | #define COLIBRI_SDRAM_BASE 0xa0000000 /* SDRAM region */ |
| 8 | 21 | ||
| 9 | /* virtual memory regions */ | 22 | /* definitions for Colibri PXA270 */ |
| 10 | #define COLIBRI_DISK_VIRT 0xF0000000 /* Disk On Chip region */ | ||
| 11 | 23 | ||
| 12 | /* size of flash */ | 24 | #define COLIBRI_PXA270_FLASH_PHYS (PXA_CS0_PHYS) /* Flash region */ |
| 13 | #define COLIBRI_FLASH_SIZE 0x02000000 /* Flash size 32 MB */ | 25 | #define COLIBRI_PXA270_ETH_PHYS (PXA_CS2_PHYS) /* Ethernet */ |
| 14 | 26 | #define COLIBRI_PXA270_ETH_IRQ_GPIO 114 | |
| 15 | /* Ethernet Controller Davicom DM9000 */ | 27 | #define COLIBRI_PXA270_ETH_IRQ \ |
| 16 | #define GPIO_DM9000 114 | 28 | gpio_to_irq(mfp_to_gpio(COLIBRI_PXA270_ETH_IRQ_GPIO)) |
| 17 | #define COLIBRI_ETH_IRQ IRQ_GPIO(GPIO_DM9000) | ||
| 18 | 29 | ||
| 19 | #endif /* _COLIBRI_H_ */ | 30 | #endif /* _COLIBRI_H_ */ |
| 31 | |||
diff --git a/arch/arm/mach-pxa/include/mach/csb726.h b/arch/arm/mach-pxa/include/mach/csb726.h new file mode 100644 index 000000000000..747ab1a71f2f --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/csb726.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * Support for Cogent CSB726 | ||
| 3 | * | ||
| 4 | * Copyright (c) 2008 Dmitry Baryshkov | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | #ifndef CSB726_H | ||
| 12 | #define CSB726_H | ||
| 13 | |||
| 14 | #define CSB726_GPIO_IRQ_LAN 52 | ||
| 15 | #define CSB726_GPIO_IRQ_SM501 53 | ||
| 16 | #define CSB726_GPIO_MMC_DETECT 100 | ||
| 17 | #define CSB726_GPIO_MMC_RO 101 | ||
| 18 | |||
| 19 | #define CSB726_FLASH_SIZE (64 * 1024 * 1024) | ||
| 20 | #define CSB726_FLASH_uMON (8 * 1024 * 1024) | ||
| 21 | |||
| 22 | #define CSB726_IRQ_LAN gpio_to_irq(CSB726_GPIO_IRQ_LAN) | ||
| 23 | #define CSB726_IRQ_SM501 gpio_to_irq(CSB726_GPIO_IRQ_SM501) | ||
| 24 | |||
| 25 | #endif | ||
| 26 | |||
diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h index 7804637a6df3..5bd55894a48d 100644 --- a/arch/arm/mach-pxa/include/mach/dma.h +++ b/arch/arm/mach-pxa/include/mach/dma.h | |||
| @@ -12,35 +12,10 @@ | |||
| 12 | #ifndef __ASM_ARCH_DMA_H | 12 | #ifndef __ASM_ARCH_DMA_H |
| 13 | #define __ASM_ARCH_DMA_H | 13 | #define __ASM_ARCH_DMA_H |
| 14 | 14 | ||
| 15 | /* | 15 | #include <mach/hardware.h> |
| 16 | * Descriptor structure for PXA's DMA engine | ||
| 17 | * Note: this structure must always be aligned to a 16-byte boundary. | ||
| 18 | */ | ||
| 19 | |||
| 20 | typedef struct pxa_dma_desc { | ||
| 21 | volatile u32 ddadr; /* Points to the next descriptor + flags */ | ||
| 22 | volatile u32 dsadr; /* DSADR value for the current transfer */ | ||
| 23 | volatile u32 dtadr; /* DTADR value for the current transfer */ | ||
| 24 | volatile u32 dcmd; /* DCMD value for the current transfer */ | ||
| 25 | } pxa_dma_desc; | ||
| 26 | |||
| 27 | typedef enum { | ||
| 28 | DMA_PRIO_HIGH = 0, | ||
| 29 | DMA_PRIO_MEDIUM = 1, | ||
| 30 | DMA_PRIO_LOW = 2 | ||
| 31 | } pxa_dma_prio; | ||
| 32 | |||
| 33 | /* | ||
| 34 | * DMA registration | ||
| 35 | */ | ||
| 36 | |||
| 37 | int __init pxa_init_dma(int num_ch); | ||
| 38 | |||
| 39 | int pxa_request_dma (char *name, | ||
| 40 | pxa_dma_prio prio, | ||
| 41 | void (*irq_handler)(int, void *), | ||
| 42 | void *data); | ||
| 43 | 16 | ||
| 44 | void pxa_free_dma (int dma_ch); | 17 | /* DMA Controller Registers Definitions */ |
| 18 | #define DMAC_REGS_VIRT io_p2v(0x40000000) | ||
| 45 | 19 | ||
| 20 | #include <plat/dma.h> | ||
| 46 | #endif /* _ASM_ARCH_DMA_H */ | 21 | #endif /* _ASM_ARCH_DMA_H */ |
diff --git a/arch/arm/mach-pxa/include/mach/gpio.h b/arch/arm/mach-pxa/include/mach/gpio.h index 2c538d8c362d..b024a8b37439 100644 --- a/arch/arm/mach-pxa/include/mach/gpio.h +++ b/arch/arm/mach-pxa/include/mach/gpio.h | |||
| @@ -24,42 +24,118 @@ | |||
| 24 | #ifndef __ASM_ARCH_PXA_GPIO_H | 24 | #ifndef __ASM_ARCH_PXA_GPIO_H |
| 25 | #define __ASM_ARCH_PXA_GPIO_H | 25 | #define __ASM_ARCH_PXA_GPIO_H |
| 26 | 26 | ||
| 27 | #include <mach/pxa-regs.h> | 27 | #include <mach/irqs.h> |
| 28 | #include <asm/irq.h> | ||
| 29 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
| 30 | |||
| 31 | #include <asm-generic/gpio.h> | 29 | #include <asm-generic/gpio.h> |
| 32 | 30 | ||
| 31 | #define GPIO_REGS_VIRT io_p2v(0x40E00000) | ||
| 32 | |||
| 33 | #define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2)) | ||
| 34 | #define GPIO_REG(x) (*(volatile u32 *)(GPIO_REGS_VIRT + (x))) | ||
| 35 | |||
| 36 | /* GPIO Pin Level Registers */ | ||
| 37 | #define GPLR0 GPIO_REG(BANK_OFF(0) + 0x00) | ||
| 38 | #define GPLR1 GPIO_REG(BANK_OFF(1) + 0x00) | ||
| 39 | #define GPLR2 GPIO_REG(BANK_OFF(2) + 0x00) | ||
| 40 | #define GPLR3 GPIO_REG(BANK_OFF(3) + 0x00) | ||
| 41 | |||
| 42 | /* GPIO Pin Direction Registers */ | ||
| 43 | #define GPDR0 GPIO_REG(BANK_OFF(0) + 0x0c) | ||
| 44 | #define GPDR1 GPIO_REG(BANK_OFF(1) + 0x0c) | ||
| 45 | #define GPDR2 GPIO_REG(BANK_OFF(2) + 0x0c) | ||
| 46 | #define GPDR3 GPIO_REG(BANK_OFF(3) + 0x0c) | ||
| 47 | |||
| 48 | /* GPIO Pin Output Set Registers */ | ||
| 49 | #define GPSR0 GPIO_REG(BANK_OFF(0) + 0x18) | ||
| 50 | #define GPSR1 GPIO_REG(BANK_OFF(1) + 0x18) | ||
| 51 | #define GPSR2 GPIO_REG(BANK_OFF(2) + 0x18) | ||
| 52 | #define GPSR3 GPIO_REG(BANK_OFF(3) + 0x18) | ||
| 53 | |||
| 54 | /* GPIO Pin Output Clear Registers */ | ||
| 55 | #define GPCR0 GPIO_REG(BANK_OFF(0) + 0x24) | ||
| 56 | #define GPCR1 GPIO_REG(BANK_OFF(1) + 0x24) | ||
| 57 | #define GPCR2 GPIO_REG(BANK_OFF(2) + 0x24) | ||
| 58 | #define GPCR3 GPIO_REG(BANK_OFF(3) + 0x24) | ||
| 59 | |||
| 60 | /* GPIO Rising Edge Detect Registers */ | ||
| 61 | #define GRER0 GPIO_REG(BANK_OFF(0) + 0x30) | ||
| 62 | #define GRER1 GPIO_REG(BANK_OFF(1) + 0x30) | ||
| 63 | #define GRER2 GPIO_REG(BANK_OFF(2) + 0x30) | ||
| 64 | #define GRER3 GPIO_REG(BANK_OFF(3) + 0x30) | ||
| 65 | |||
| 66 | /* GPIO Falling Edge Detect Registers */ | ||
| 67 | #define GFER0 GPIO_REG(BANK_OFF(0) + 0x3c) | ||
| 68 | #define GFER1 GPIO_REG(BANK_OFF(1) + 0x3c) | ||
| 69 | #define GFER2 GPIO_REG(BANK_OFF(2) + 0x3c) | ||
| 70 | #define GFER3 GPIO_REG(BANK_OFF(3) + 0x3c) | ||
| 71 | |||
| 72 | /* GPIO Edge Detect Status Registers */ | ||
| 73 | #define GEDR0 GPIO_REG(BANK_OFF(0) + 0x48) | ||
| 74 | #define GEDR1 GPIO_REG(BANK_OFF(1) + 0x48) | ||
| 75 | #define GEDR2 GPIO_REG(BANK_OFF(2) + 0x48) | ||
| 76 | #define GEDR3 GPIO_REG(BANK_OFF(3) + 0x48) | ||
| 77 | |||
| 78 | /* GPIO Alternate Function Select Registers */ | ||
| 79 | #define GAFR0_L GPIO_REG(0x0054) | ||
| 80 | #define GAFR0_U GPIO_REG(0x0058) | ||
| 81 | #define GAFR1_L GPIO_REG(0x005C) | ||
| 82 | #define GAFR1_U GPIO_REG(0x0060) | ||
| 83 | #define GAFR2_L GPIO_REG(0x0064) | ||
| 84 | #define GAFR2_U GPIO_REG(0x0068) | ||
| 85 | #define GAFR3_L GPIO_REG(0x006C) | ||
| 86 | #define GAFR3_U GPIO_REG(0x0070) | ||
| 87 | |||
| 88 | /* More handy macros. The argument is a literal GPIO number. */ | ||
| 89 | |||
| 90 | #define GPIO_bit(x) (1 << ((x) & 0x1f)) | ||
| 91 | |||
| 92 | #define GPLR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x00) | ||
| 93 | #define GPDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x0c) | ||
| 94 | #define GPSR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x18) | ||
| 95 | #define GPCR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x24) | ||
| 96 | #define GRER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x30) | ||
| 97 | #define GFER(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x3c) | ||
| 98 | #define GEDR(x) GPIO_REG(BANK_OFF((x) >> 5) + 0x48) | ||
| 99 | #define GAFR(x) GPIO_REG(0x54 + (((x) & 0x70) >> 2)) | ||
| 100 | |||
| 33 | 101 | ||
| 34 | /* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85). | ||
| 35 | * Those cases currently cause holes in the GPIO number space. | ||
| 36 | */ | ||
| 37 | #define NR_BUILTIN_GPIO 128 | 102 | #define NR_BUILTIN_GPIO 128 |
| 38 | 103 | ||
| 39 | static inline int gpio_get_value(unsigned gpio) | 104 | #define gpio_to_bank(gpio) ((gpio) >> 5) |
| 105 | #define gpio_to_irq(gpio) IRQ_GPIO(gpio) | ||
| 106 | #define irq_to_gpio(irq) IRQ_TO_GPIO(irq) | ||
| 107 | |||
| 108 | #ifdef CONFIG_CPU_PXA26x | ||
| 109 | /* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted, | ||
| 110 | * as well as their Alternate Function value being '1' for GPIO in GAFRx. | ||
| 111 | */ | ||
| 112 | static inline int __gpio_is_inverted(unsigned gpio) | ||
| 40 | { | 113 | { |
| 41 | if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) | 114 | return cpu_is_pxa25x() && gpio > 85; |
| 42 | return GPLR(gpio) & GPIO_bit(gpio); | ||
| 43 | else | ||
| 44 | return __gpio_get_value(gpio); | ||
| 45 | } | 115 | } |
| 116 | #else | ||
| 117 | static inline int __gpio_is_inverted(unsigned gpio) { return 0; } | ||
| 118 | #endif | ||
| 46 | 119 | ||
| 47 | static inline void gpio_set_value(unsigned gpio, int value) | 120 | /* |
| 121 | * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate | ||
| 122 | * function of a GPIO, and GPDRx cannot be altered once configured. It | ||
| 123 | * is attributed as "occupied" here (I know this terminology isn't | ||
| 124 | * accurate, you are welcome to propose a better one :-) | ||
| 125 | */ | ||
| 126 | static inline int __gpio_is_occupied(unsigned gpio) | ||
| 48 | { | 127 | { |
| 49 | if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) { | 128 | if (cpu_is_pxa27x() || cpu_is_pxa25x()) { |
| 50 | if (value) | 129 | int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3; |
| 51 | GPSR(gpio) = GPIO_bit(gpio); | 130 | int dir = GPDR(gpio) & GPIO_bit(gpio); |
| 131 | |||
| 132 | if (__gpio_is_inverted(gpio)) | ||
| 133 | return af != 1 || dir == 0; | ||
| 52 | else | 134 | else |
| 53 | GPCR(gpio) = GPIO_bit(gpio); | 135 | return af != 0 || dir != 0; |
| 54 | } else { | 136 | } else |
| 55 | __gpio_set_value(gpio, value); | 137 | return GPDR(gpio) & GPIO_bit(gpio); |
| 56 | } | ||
| 57 | } | 138 | } |
| 58 | 139 | ||
| 59 | #define gpio_cansleep __gpio_cansleep | 140 | #include <plat/gpio.h> |
| 60 | |||
| 61 | #define gpio_to_irq(gpio) IRQ_GPIO(gpio) | ||
| 62 | #define irq_to_gpio(irq) IRQ_TO_GPIO(irq) | ||
| 63 | |||
| 64 | |||
| 65 | #endif | 141 | #endif |
diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h index 099f54a41de4..06abd4160607 100644 --- a/arch/arm/mach-pxa/include/mach/gumstix.h +++ b/arch/arm/mach-pxa/include/mach/gumstix.h | |||
| @@ -97,4 +97,5 @@ has detected a cable insertion; driven low otherwise. */ | |||
| 97 | 97 | ||
| 98 | /* for expansion boards that can't be programatically detected */ | 98 | /* for expansion boards that can't be programatically detected */ |
| 99 | extern int am200_init(void); | 99 | extern int am200_init(void); |
| 100 | extern int am300_init(void); | ||
| 100 | 101 | ||
diff --git a/arch/arm/mach-pxa/include/mach/lubbock.h b/arch/arm/mach-pxa/include/mach/lubbock.h index 4cb24154a5a8..751b74811d0f 100644 --- a/arch/arm/mach-pxa/include/mach/lubbock.h +++ b/arch/arm/mach-pxa/include/mach/lubbock.h | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | 25 | ||
| 26 | /* FPGA register virtual addresses */ | 26 | /* FPGA register virtual addresses */ |
| 27 | #define LUB_WHOAMI __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000) | 27 | #define LUB_WHOAMI __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000) |
| 28 | #define LUB_HEXLED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x010) | ||
| 29 | #define LUB_DISC_BLNK_LED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040) | 28 | #define LUB_DISC_BLNK_LED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040) |
| 30 | #define LUB_CONF_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050) | 29 | #define LUB_CONF_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050) |
| 31 | #define LUB_USER_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060) | 30 | #define LUB_USER_SWITCHES __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060) |
diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h index 38d68d99f585..82a399f3f9f2 100644 --- a/arch/arm/mach-pxa/include/mach/magician.h +++ b/arch/arm/mach-pxa/include/mach/magician.h | |||
| @@ -69,7 +69,7 @@ | |||
| 69 | #define IRQ_MAGICIAN_SD (IRQ_BOARD_START + 0) | 69 | #define IRQ_MAGICIAN_SD (IRQ_BOARD_START + 0) |
| 70 | #define IRQ_MAGICIAN_EP (IRQ_BOARD_START + 1) | 70 | #define IRQ_MAGICIAN_EP (IRQ_BOARD_START + 1) |
| 71 | #define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2) | 71 | #define IRQ_MAGICIAN_BT (IRQ_BOARD_START + 2) |
| 72 | #define IRQ_MAGICIAN_AC (IRQ_BOARD_START + 3) | 72 | #define IRQ_MAGICIAN_VBUS (IRQ_BOARD_START + 3) |
| 73 | 73 | ||
| 74 | /* | 74 | /* |
| 75 | * CPLD EGPIOs | 75 | * CPLD EGPIOs |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h index a72869b73ee3..b13dc0269a6d 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa25x.h | |||
| @@ -1,7 +1,6 @@ | |||
| 1 | #ifndef __ASM_ARCH_MFP_PXA25X_H | 1 | #ifndef __ASM_ARCH_MFP_PXA25X_H |
| 2 | #define __ASM_ARCH_MFP_PXA25X_H | 2 | #define __ASM_ARCH_MFP_PXA25X_H |
| 3 | 3 | ||
| 4 | #include <mach/mfp.h> | ||
| 5 | #include <mach/mfp-pxa2xx.h> | 4 | #include <mach/mfp-pxa2xx.h> |
| 6 | 5 | ||
| 7 | /* GPIO */ | 6 | /* GPIO */ |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h index da4f85a4f990..6543c05f47ed 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa27x.h | |||
| @@ -8,7 +8,6 @@ | |||
| 8 | * specific controller, and this should work in most cases. | 8 | * specific controller, and this should work in most cases. |
| 9 | */ | 9 | */ |
| 10 | 10 | ||
| 11 | #include <mach/mfp.h> | ||
| 12 | #include <mach/mfp-pxa2xx.h> | 11 | #include <mach/mfp-pxa2xx.h> |
| 13 | 12 | ||
| 14 | /* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN | 13 | /* Note: GPIO3/GPIO4 will be driven by Power I2C when PCFR/PI2C_EN |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h index 3e9211591e20..658b28ed129b 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | #ifndef __ASM_ARCH_MFP_PXA2XX_H | 1 | #ifndef __ASM_ARCH_MFP_PXA2XX_H |
| 2 | #define __ASM_ARCH_MFP_PXA2XX_H | 2 | #define __ASM_ARCH_MFP_PXA2XX_H |
| 3 | 3 | ||
| 4 | #include <mach/mfp.h> | 4 | #include <plat/mfp.h> |
| 5 | 5 | ||
| 6 | /* | 6 | /* |
| 7 | * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx: | 7 | * the following MFP_xxx bit definitions in mfp.h are re-used for pxa2xx: |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h index bc1fb33a6e70..ae8441192ef0 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa300.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa300.h | |||
| @@ -15,7 +15,6 @@ | |||
| 15 | #ifndef __ASM_ARCH_MFP_PXA300_H | 15 | #ifndef __ASM_ARCH_MFP_PXA300_H |
| 16 | #define __ASM_ARCH_MFP_PXA300_H | 16 | #define __ASM_ARCH_MFP_PXA300_H |
| 17 | 17 | ||
| 18 | #include <mach/mfp.h> | ||
| 19 | #include <mach/mfp-pxa3xx.h> | 18 | #include <mach/mfp-pxa3xx.h> |
| 20 | 19 | ||
| 21 | /* GPIO */ | 20 | /* GPIO */ |
| @@ -41,6 +40,7 @@ | |||
| 41 | #endif | 40 | #endif |
| 42 | 41 | ||
| 43 | /* Chip Select */ | 42 | /* Chip Select */ |
| 43 | #define GPIO1_nCS2 MFP_CFG(GPIO1, AF1) | ||
| 44 | #define GPIO2_nCS3 MFP_CFG(GPIO2, AF1) | 44 | #define GPIO2_nCS3 MFP_CFG(GPIO2, AF1) |
| 45 | 45 | ||
| 46 | /* AC97 */ | 46 | /* AC97 */ |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h index 67f8385ea548..07897e61d05a 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa320.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa320.h | |||
| @@ -15,7 +15,6 @@ | |||
| 15 | #ifndef __ASM_ARCH_MFP_PXA320_H | 15 | #ifndef __ASM_ARCH_MFP_PXA320_H |
| 16 | #define __ASM_ARCH_MFP_PXA320_H | 16 | #define __ASM_ARCH_MFP_PXA320_H |
| 17 | 17 | ||
| 18 | #include <mach/mfp.h> | ||
| 19 | #include <mach/mfp-pxa3xx.h> | 18 | #include <mach/mfp-pxa3xx.h> |
| 20 | 19 | ||
| 21 | /* GPIO */ | 20 | /* GPIO */ |
| @@ -38,6 +37,7 @@ | |||
| 38 | #define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0) | 37 | #define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0) |
| 39 | 38 | ||
| 40 | /* Chip Select */ | 39 | /* Chip Select */ |
| 40 | #define GPIO3_nCS2 MFP_CFG(GPIO3, AF1) | ||
| 41 | #define GPIO4_nCS3 MFP_CFG(GPIO4, AF1) | 41 | #define GPIO4_nCS3 MFP_CFG(GPIO4, AF1) |
| 42 | 42 | ||
| 43 | /* AC97 */ | 43 | /* AC97 */ |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h index 1f6b35c015d0..d375195d982b 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa3xx.h | |||
| @@ -1,68 +1,9 @@ | |||
| 1 | #ifndef __ASM_ARCH_MFP_PXA3XX_H | 1 | #ifndef __ASM_ARCH_MFP_PXA3XX_H |
| 2 | #define __ASM_ARCH_MFP_PXA3XX_H | 2 | #define __ASM_ARCH_MFP_PXA3XX_H |
| 3 | 3 | ||
| 4 | #define MFPR_BASE (0x40e10000) | 4 | #include <plat/mfp.h> |
| 5 | #define MFPR_SIZE (PAGE_SIZE) | ||
| 6 | |||
| 7 | /* MFPR register bit definitions */ | ||
| 8 | #define MFPR_PULL_SEL (0x1 << 15) | ||
| 9 | #define MFPR_PULLUP_EN (0x1 << 14) | ||
| 10 | #define MFPR_PULLDOWN_EN (0x1 << 13) | ||
| 11 | #define MFPR_SLEEP_SEL (0x1 << 9) | ||
| 12 | #define MFPR_SLEEP_OE_N (0x1 << 7) | ||
| 13 | #define MFPR_EDGE_CLEAR (0x1 << 6) | ||
| 14 | #define MFPR_EDGE_FALL_EN (0x1 << 5) | ||
| 15 | #define MFPR_EDGE_RISE_EN (0x1 << 4) | ||
| 16 | |||
| 17 | #define MFPR_SLEEP_DATA(x) ((x) << 8) | ||
| 18 | #define MFPR_DRIVE(x) (((x) & 0x7) << 10) | ||
| 19 | #define MFPR_AF_SEL(x) (((x) & 0x7) << 0) | ||
| 20 | 5 | ||
| 21 | #define MFPR_EDGE_NONE (0) | 6 | #define MFPR_BASE (0x40e10000) |
| 22 | #define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN) | ||
| 23 | #define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN) | ||
| 24 | #define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL) | ||
| 25 | |||
| 26 | /* | ||
| 27 | * Table that determines the low power modes outputs, with actual settings | ||
| 28 | * used in parentheses for don't-care values. Except for the float output, | ||
| 29 | * the configured driven and pulled levels match, so if there is a need for | ||
| 30 | * non-LPM pulled output, the same configuration could probably be used. | ||
| 31 | * | ||
| 32 | * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel | ||
| 33 | * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) | ||
| 34 | * | ||
| 35 | * Input 0 X(0) X(0) X(0) 0 | ||
| 36 | * Drive 0 0 0 0 X(1) 0 | ||
| 37 | * Drive 1 0 1 X(1) 0 0 | ||
| 38 | * Pull hi (1) 1 X(1) 1 0 0 | ||
| 39 | * Pull lo (0) 1 X(0) 0 1 0 | ||
| 40 | * Z (float) 1 X(0) 0 0 0 | ||
| 41 | */ | ||
| 42 | #define MFPR_LPM_INPUT (0) | ||
| 43 | #define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN) | ||
| 44 | #define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN) | ||
| 45 | #define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N) | ||
| 46 | #define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N) | ||
| 47 | #define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N) | ||
| 48 | #define MFPR_LPM_MASK (0xe080) | ||
| 49 | |||
| 50 | /* | ||
| 51 | * The pullup and pulldown state of the MFP pin at run mode is by default | ||
| 52 | * determined by the selected alternate function. In case that some buggy | ||
| 53 | * devices need to override this default behavior, the definitions below | ||
| 54 | * indicates the setting of corresponding MFPR bits | ||
| 55 | * | ||
| 56 | * Definition pull_sel pullup_en pulldown_en | ||
| 57 | * MFPR_PULL_NONE 0 0 0 | ||
| 58 | * MFPR_PULL_LOW 1 0 1 | ||
| 59 | * MFPR_PULL_HIGH 1 1 0 | ||
| 60 | * MFPR_PULL_BOTH 1 1 1 | ||
| 61 | */ | ||
| 62 | #define MFPR_PULL_NONE (0) | ||
| 63 | #define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN) | ||
| 64 | #define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN) | ||
| 65 | #define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN) | ||
| 66 | 7 | ||
| 67 | /* PXA3xx common MFP configurations - processor specific ones defined | 8 | /* PXA3xx common MFP configurations - processor specific ones defined |
| 68 | * in mfp-pxa300.h and mfp-pxa320.h | 9 | * in mfp-pxa300.h and mfp-pxa320.h |
| @@ -197,56 +138,21 @@ | |||
| 197 | #define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) | 138 | #define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) |
| 198 | #define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) | 139 | #define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) |
| 199 | 140 | ||
| 200 | /* | 141 | /* NOTE: usage of these two functions is not recommended, |
| 201 | * each MFP pin will have a MFPR register, since the offset of the | 142 | * use pxa3xx_mfp_config() instead. |
| 202 | * register varies between processors, the processor specific code | ||
| 203 | * should initialize the pin offsets by pxa3xx_mfp_init_addr() | ||
| 204 | * | ||
| 205 | * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map" | ||
| 206 | * structure, which represents a range of MFP pins from "start" to | ||
| 207 | * "end", with the offset begining at "offset", to define a single | ||
| 208 | * pin, let "end" = -1 | ||
| 209 | * | ||
| 210 | * use | ||
| 211 | * | ||
| 212 | * MFP_ADDR_X() to define a range of pins | ||
| 213 | * MFP_ADDR() to define a single pin | ||
| 214 | * MFP_ADDR_END to signal the end of pin offset definitions | ||
| 215 | */ | ||
| 216 | struct pxa3xx_mfp_addr_map { | ||
| 217 | unsigned int start; | ||
| 218 | unsigned int end; | ||
| 219 | unsigned long offset; | ||
| 220 | }; | ||
| 221 | |||
| 222 | #define MFP_ADDR_X(start, end, offset) \ | ||
| 223 | { MFP_PIN_##start, MFP_PIN_##end, offset } | ||
| 224 | |||
| 225 | #define MFP_ADDR(pin, offset) \ | ||
| 226 | { MFP_PIN_##pin, -1, offset } | ||
| 227 | |||
| 228 | #define MFP_ADDR_END { MFP_PIN_INVALID, 0 } | ||
| 229 | |||
| 230 | /* | ||
| 231 | * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access | ||
| 232 | * to the MFPR register | ||
| 233 | */ | ||
| 234 | unsigned long pxa3xx_mfp_read(int mfp); | ||
| 235 | void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val); | ||
| 236 | |||
| 237 | /* | ||
| 238 | * pxa3xx_mfp_config - configure the MFPR registers | ||
| 239 | * | ||
| 240 | * used by board specific initialization code | ||
| 241 | */ | ||
| 242 | void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num); | ||
| 243 | |||
| 244 | /* | ||
| 245 | * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin | ||
| 246 | * index and MFPR register offset | ||
| 247 | * | ||
| 248 | * used by processor specific code | ||
| 249 | */ | 143 | */ |
| 250 | void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *); | 144 | static inline unsigned long pxa3xx_mfp_read(int mfp) |
| 251 | void __init pxa3xx_init_mfp(void); | 145 | { |
| 146 | return mfp_read(mfp); | ||
| 147 | } | ||
| 148 | |||
| 149 | static inline void pxa3xx_mfp_write(int mfp, unsigned long val) | ||
| 150 | { | ||
| 151 | mfp_write(mfp, val); | ||
| 152 | } | ||
| 153 | |||
| 154 | static inline void pxa3xx_mfp_config(unsigned long *mfp_cfg, int num) | ||
| 155 | { | ||
| 156 | mfp_config(mfp_cfg, num); | ||
| 157 | } | ||
| 252 | #endif /* __ASM_ARCH_MFP_PXA3XX_H */ | 158 | #endif /* __ASM_ARCH_MFP_PXA3XX_H */ |
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h index fa73f56a1372..0d119d3b9221 100644 --- a/arch/arm/mach-pxa/include/mach/mfp-pxa930.h +++ b/arch/arm/mach-pxa/include/mach/mfp-pxa930.h | |||
| @@ -13,7 +13,6 @@ | |||
| 13 | #ifndef __ASM_ARCH_MFP_PXA9xx_H | 13 | #ifndef __ASM_ARCH_MFP_PXA9xx_H |
| 14 | #define __ASM_ARCH_MFP_PXA9xx_H | 14 | #define __ASM_ARCH_MFP_PXA9xx_H |
| 15 | 15 | ||
| 16 | #include <mach/mfp.h> | ||
| 17 | #include <mach/mfp-pxa3xx.h> | 16 | #include <mach/mfp-pxa3xx.h> |
| 18 | 17 | ||
| 19 | /* GPIO */ | 18 | /* GPIO */ |
diff --git a/arch/arm/mach-pxa/include/mach/mtd-xip.h b/arch/arm/mach-pxa/include/mach/mtd-xip.h index cfca8155be72..297387ec3618 100644 --- a/arch/arm/mach-pxa/include/mach/mtd-xip.h +++ b/arch/arm/mach-pxa/include/mach/mtd-xip.h | |||
| @@ -15,8 +15,8 @@ | |||
| 15 | #ifndef __ARCH_PXA_MTD_XIP_H__ | 15 | #ifndef __ARCH_PXA_MTD_XIP_H__ |
| 16 | #define __ARCH_PXA_MTD_XIP_H__ | 16 | #define __ARCH_PXA_MTD_XIP_H__ |
| 17 | 17 | ||
| 18 | #include <mach/hardware.h> | 18 | #include <mach/regs-ost.h> |
| 19 | #include <mach/pxa-regs.h> | 19 | #include <mach/regs-intc.h> |
| 20 | 20 | ||
| 21 | #define xip_irqpending() (ICIP & ICMR) | 21 | #define xip_irqpending() (ICIP & ICMR) |
| 22 | 22 | ||
diff --git a/arch/arm/mach-pxa/include/mach/palmld.h b/arch/arm/mach-pxa/include/mach/palmld.h new file mode 100644 index 000000000000..7c295a48d784 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/palmld.h | |||
| @@ -0,0 +1,109 @@ | |||
| 1 | /* | ||
| 2 | * GPIOs and interrupts for Palm LifeDrive Handheld Computer | ||
| 3 | * | ||
| 4 | * Authors: Alex Osborne <ato@meshy.org> | ||
| 5 | * Marek Vasut <marek.vasut@gmail.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | * | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef _INCLUDE_PALMLD_H_ | ||
| 14 | #define _INCLUDE_PALMLD_H_ | ||
| 15 | |||
| 16 | /** HERE ARE GPIOs **/ | ||
| 17 | |||
| 18 | /* GPIOs */ | ||
| 19 | #define GPIO_NR_PALMLD_GPIO_RESET 1 | ||
| 20 | #define GPIO_NR_PALMLD_POWER_DETECT 4 | ||
| 21 | #define GPIO_NR_PALMLD_HOTSYNC_BUTTON_N 10 | ||
| 22 | #define GPIO_NR_PALMLD_POWER_SWITCH 12 | ||
| 23 | #define GPIO_NR_PALMLD_EARPHONE_DETECT 13 | ||
| 24 | #define GPIO_NR_PALMLD_LOCK_SWITCH 15 | ||
| 25 | |||
| 26 | /* SD/MMC */ | ||
| 27 | #define GPIO_NR_PALMLD_SD_DETECT_N 14 | ||
| 28 | #define GPIO_NR_PALMLD_SD_POWER 114 | ||
| 29 | #define GPIO_NR_PALMLD_SD_READONLY 116 | ||
| 30 | |||
| 31 | /* TOUCHSCREEN */ | ||
| 32 | #define GPIO_NR_PALMLD_WM9712_IRQ 27 | ||
| 33 | |||
| 34 | /* IRDA */ | ||
| 35 | #define GPIO_NR_PALMLD_IR_DISABLE 108 | ||
| 36 | |||
| 37 | /* LCD/BACKLIGHT */ | ||
| 38 | #define GPIO_NR_PALMLD_BL_POWER 19 | ||
| 39 | #define GPIO_NR_PALMLD_LCD_POWER 96 | ||
| 40 | |||
| 41 | /* LCD BORDER */ | ||
| 42 | #define GPIO_NR_PALMLD_BORDER_SWITCH 21 | ||
| 43 | #define GPIO_NR_PALMLD_BORDER_SELECT 22 | ||
| 44 | |||
| 45 | /* BLUETOOTH */ | ||
| 46 | #define GPIO_NR_PALMLD_BT_POWER 17 | ||
| 47 | #define GPIO_NR_PALMLD_BT_RESET 83 | ||
| 48 | |||
| 49 | /* PCMCIA (WiFi) */ | ||
| 50 | #define GPIO_NR_PALMLD_PCMCIA_READY 38 | ||
| 51 | #define GPIO_NR_PALMLD_PCMCIA_POWER 36 | ||
| 52 | #define GPIO_NR_PALMLD_PCMCIA_RESET 81 | ||
| 53 | |||
| 54 | /* LEDs */ | ||
| 55 | #define GPIO_NR_PALMLD_LED_GREEN 52 | ||
| 56 | #define GPIO_NR_PALMLD_LED_AMBER 94 | ||
| 57 | |||
| 58 | /* IDE */ | ||
| 59 | #define GPIO_NR_PALMLD_IDE_IRQ 95 | ||
| 60 | #define GPIO_NR_PALMLD_IDE_RESET 98 | ||
| 61 | #define GPIO_NR_PALMLD_IDE_PWEN 115 | ||
| 62 | |||
| 63 | /* USB */ | ||
| 64 | #define GPIO_NR_PALMLD_USB_DETECT_N 3 | ||
| 65 | #define GPIO_NR_PALMLD_USB_READY 86 | ||
| 66 | #define GPIO_NR_PALMLD_USB_RESET 88 | ||
| 67 | #define GPIO_NR_PALMLD_USB_INT 106 | ||
| 68 | #define GPIO_NR_PALMLD_USB_POWER 118 | ||
| 69 | /* 20, 53 and 86 are usb related too */ | ||
| 70 | |||
| 71 | /* INTERRUPTS */ | ||
| 72 | #define IRQ_GPIO_PALMLD_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMLD_GPIO_RESET) | ||
| 73 | #define IRQ_GPIO_PALMLD_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMLD_SD_DETECT_N) | ||
| 74 | #define IRQ_GPIO_PALMLD_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMLD_WM9712_IRQ) | ||
| 75 | #define IRQ_GPIO_PALMLD_IDE_IRQ IRQ_GPIO(GPIO_NR_PALMLD_IDE_IRQ) | ||
| 76 | |||
| 77 | |||
| 78 | /** HERE ARE INIT VALUES **/ | ||
| 79 | |||
| 80 | /* IO mappings */ | ||
| 81 | #define PALMLD_USB_PHYS PXA_CS2_PHYS | ||
| 82 | #define PALMLD_USB_VIRT 0xf0000000 | ||
| 83 | #define PALMLD_USB_SIZE 0x00100000 | ||
| 84 | |||
| 85 | #define PALMLD_IDE_PHYS 0x20000000 | ||
| 86 | #define PALMLD_IDE_VIRT 0xf1000000 | ||
| 87 | #define PALMLD_IDE_SIZE 0x00100000 | ||
| 88 | |||
| 89 | #define PALMLD_PHYS_IO_START 0x40000000 | ||
| 90 | |||
| 91 | /* BATTERY */ | ||
| 92 | #define PALMLD_BAT_MAX_VOLTAGE 4000 /* 4.00V maximum voltage */ | ||
| 93 | #define PALMLD_BAT_MIN_VOLTAGE 3550 /* 3.55V critical voltage */ | ||
| 94 | #define PALMLD_BAT_MAX_CURRENT 0 /* unknokn */ | ||
| 95 | #define PALMLD_BAT_MIN_CURRENT 0 /* unknown */ | ||
| 96 | #define PALMLD_BAT_MAX_CHARGE 1 /* unknown */ | ||
| 97 | #define PALMLD_BAT_MIN_CHARGE 1 /* unknown */ | ||
| 98 | #define PALMLD_MAX_LIFE_MINS 240 /* on-life in minutes */ | ||
| 99 | |||
| 100 | #define PALMLD_BAT_MEASURE_DELAY (HZ * 1) | ||
| 101 | |||
| 102 | /* BACKLIGHT */ | ||
| 103 | #define PALMLD_MAX_INTENSITY 0xFE | ||
| 104 | #define PALMLD_DEFAULT_INTENSITY 0x7E | ||
| 105 | #define PALMLD_LIMIT_MASK 0x7F | ||
| 106 | #define PALMLD_PRESCALER 0x3F | ||
| 107 | #define PALMLD_PERIOD_NS 3500 | ||
| 108 | |||
| 109 | #endif | ||
diff --git a/arch/arm/mach-pxa/include/mach/palmt5.h b/arch/arm/mach-pxa/include/mach/palmt5.h new file mode 100644 index 000000000000..94db2881f048 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/palmt5.h | |||
| @@ -0,0 +1,84 @@ | |||
| 1 | /* | ||
| 2 | * GPIOs and interrupts for Palm Tungsten|T5 Handheld Computer | ||
| 3 | * | ||
| 4 | * Authors: Ales Snuparek <snuparek@atlas.cz> | ||
| 5 | * Marek Vasut <marek.vasut@gmail.com> | ||
| 6 | * Justin Kendrick <twilightsentry@gmail.com> | ||
| 7 | * RichardT5 <richard_t5@users.sourceforge.net> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef _INCLUDE_PALMT5_H_ | ||
| 16 | #define _INCLUDE_PALMT5_H_ | ||
| 17 | |||
| 18 | /** HERE ARE GPIOs **/ | ||
| 19 | |||
| 20 | /* GPIOs */ | ||
| 21 | #define GPIO_NR_PALMT5_GPIO_RESET 1 | ||
| 22 | |||
| 23 | #define GPIO_NR_PALMT5_POWER_DETECT 90 | ||
| 24 | #define GPIO_NR_PALMT5_HOTSYNC_BUTTON_N 10 | ||
| 25 | #define GPIO_NR_PALMT5_EARPHONE_DETECT 107 | ||
| 26 | |||
| 27 | /* SD/MMC */ | ||
| 28 | #define GPIO_NR_PALMT5_SD_DETECT_N 14 | ||
| 29 | #define GPIO_NR_PALMT5_SD_POWER 114 | ||
| 30 | #define GPIO_NR_PALMT5_SD_READONLY 115 | ||
| 31 | |||
| 32 | /* TOUCHSCREEN */ | ||
| 33 | #define GPIO_NR_PALMT5_WM9712_IRQ 27 | ||
| 34 | |||
| 35 | /* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ | ||
| 36 | #define GPIO_NR_PALMT5_IR_DISABLE 40 | ||
| 37 | |||
| 38 | /* USB */ | ||
| 39 | #define GPIO_NR_PALMT5_USB_DETECT_N 15 | ||
| 40 | #define GPIO_NR_PALMT5_USB_POWER 95 | ||
| 41 | #define GPIO_NR_PALMT5_USB_PULLUP 93 | ||
| 42 | |||
| 43 | /* LCD/BACKLIGHT */ | ||
| 44 | #define GPIO_NR_PALMT5_BL_POWER 84 | ||
| 45 | #define GPIO_NR_PALMT5_LCD_POWER 96 | ||
| 46 | |||
| 47 | /* BLUETOOTH */ | ||
| 48 | #define GPIO_NR_PALMT5_BT_POWER 17 | ||
| 49 | #define GPIO_NR_PALMT5_BT_RESET 83 | ||
| 50 | |||
| 51 | /* INTERRUPTS */ | ||
| 52 | #define IRQ_GPIO_PALMT5_SD_DETECT_N IRQ_GPIO(GPIO_NR_PALMT5_SD_DETECT_N) | ||
| 53 | #define IRQ_GPIO_PALMT5_WM9712_IRQ IRQ_GPIO(GPIO_NR_PALMT5_WM9712_IRQ) | ||
| 54 | #define IRQ_GPIO_PALMT5_USB_DETECT IRQ_GPIO(GPIO_NR_PALMT5_USB_DETECT) | ||
| 55 | #define IRQ_GPIO_PALMT5_GPIO_RESET IRQ_GPIO(GPIO_NR_PALMT5_GPIO_RESET) | ||
| 56 | |||
| 57 | /** HERE ARE INIT VALUES **/ | ||
| 58 | |||
| 59 | /* Various addresses */ | ||
| 60 | #define PALMT5_PHYS_RAM_START 0xa0000000 | ||
| 61 | #define PALMT5_PHYS_IO_START 0x40000000 | ||
| 62 | |||
| 63 | /* TOUCHSCREEN */ | ||
| 64 | #define AC97_LINK_FRAME 21 | ||
| 65 | |||
| 66 | /* BATTERY */ | ||
| 67 | #define PALMT5_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ | ||
| 68 | #define PALMT5_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ | ||
| 69 | #define PALMT5_BAT_MAX_CURRENT 0 /* unknokn */ | ||
| 70 | #define PALMT5_BAT_MIN_CURRENT 0 /* unknown */ | ||
| 71 | #define PALMT5_BAT_MAX_CHARGE 1 /* unknown */ | ||
| 72 | #define PALMT5_BAT_MIN_CHARGE 1 /* unknown */ | ||
| 73 | #define PALMT5_MAX_LIFE_MINS 360 /* on-life in minutes */ | ||
| 74 | |||
| 75 | #define PALMT5_BAT_MEASURE_DELAY (HZ * 1) | ||
| 76 | |||
| 77 | /* BACKLIGHT */ | ||
| 78 | #define PALMT5_MAX_INTENSITY 0xFE | ||
| 79 | #define PALMT5_DEFAULT_INTENSITY 0x7E | ||
| 80 | #define PALMT5_LIMIT_MASK 0x7F | ||
| 81 | #define PALMT5_PRESCALER 0x3F | ||
| 82 | #define PALMT5_PERIOD_NS 3500 | ||
| 83 | |||
| 84 | #endif | ||
diff --git a/arch/arm/mach-pxa/include/mach/pm.h b/arch/arm/mach-pxa/include/mach/pm.h index 83342469acac..a6eeef8a075f 100644 --- a/arch/arm/mach-pxa/include/mach/pm.h +++ b/arch/arm/mach-pxa/include/mach/pm.h | |||
| @@ -27,3 +27,13 @@ extern void pxa27x_cpu_suspend(unsigned int); | |||
| 27 | extern void pxa_cpu_resume(void); | 27 | extern void pxa_cpu_resume(void); |
| 28 | 28 | ||
| 29 | extern int pxa_pm_enter(suspend_state_t state); | 29 | extern int pxa_pm_enter(suspend_state_t state); |
| 30 | |||
| 31 | /* NOTE: this is for PM debugging on Lubbock, it's really a big | ||
| 32 | * ugly, but let's keep the crap minimum here, instead of direct | ||
| 33 | * accessing the LUBBOCK CPLD registers in arch/arm/mach-pxa/pm.c | ||
| 34 | */ | ||
| 35 | #ifdef CONFIG_ARCH_LUBBOCK | ||
| 36 | extern void lubbock_set_hexled(uint32_t value); | ||
| 37 | #else | ||
| 38 | #define lubbock_set_hexled(x) | ||
| 39 | #endif | ||
diff --git a/arch/arm/mach-pxa/include/mach/pxa-regs.h b/arch/arm/mach-pxa/include/mach/pxa-regs.h deleted file mode 100644 index 31d615aa7723..000000000000 --- a/arch/arm/mach-pxa/include/mach/pxa-regs.h +++ /dev/null | |||
| @@ -1,263 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-pxa/include/mach/pxa-regs.h | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Created: Jun 15, 2001 | ||
| 6 | * Copyright: MontaVista Software Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __PXA_REGS_H | ||
| 14 | #define __PXA_REGS_H | ||
| 15 | |||
| 16 | #include <mach/hardware.h> | ||
| 17 | |||
| 18 | /* | ||
| 19 | * PXA Chip selects | ||
| 20 | */ | ||
| 21 | |||
| 22 | #define PXA_CS0_PHYS 0x00000000 | ||
| 23 | #define PXA_CS1_PHYS 0x04000000 | ||
| 24 | #define PXA_CS2_PHYS 0x08000000 | ||
| 25 | #define PXA_CS3_PHYS 0x0C000000 | ||
| 26 | #define PXA_CS4_PHYS 0x10000000 | ||
| 27 | #define PXA_CS5_PHYS 0x14000000 | ||
| 28 | |||
| 29 | |||
| 30 | /* | ||
| 31 | * Personal Computer Memory Card International Association (PCMCIA) sockets | ||
| 32 | */ | ||
| 33 | |||
| 34 | #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ | ||
| 35 | #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ | ||
| 36 | #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ | ||
| 37 | #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ | ||
| 38 | #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ | ||
| 39 | |||
| 40 | #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ | ||
| 41 | #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ | ||
| 42 | #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ | ||
| 43 | #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ | ||
| 44 | |||
| 45 | #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ | ||
| 46 | #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ | ||
| 47 | #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ | ||
| 48 | #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ | ||
| 49 | |||
| 50 | #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ | ||
| 51 | (0x20000000 + (Nb)*PCMCIASp) | ||
| 52 | #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */ | ||
| 53 | #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ | ||
| 54 | (_PCMCIA (Nb) + 2*PCMCIAPrtSp) | ||
| 55 | #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ | ||
| 56 | (_PCMCIA (Nb) + 3*PCMCIAPrtSp) | ||
| 57 | |||
| 58 | #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */ | ||
| 59 | #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */ | ||
| 60 | #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */ | ||
| 61 | #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */ | ||
| 62 | |||
| 63 | #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */ | ||
| 64 | #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */ | ||
| 65 | #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */ | ||
| 66 | #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */ | ||
| 67 | |||
| 68 | |||
| 69 | |||
| 70 | /* | ||
| 71 | * DMA Controller | ||
| 72 | */ | ||
| 73 | #define DCSR(x) __REG2(0x40000000, (x) << 2) | ||
| 74 | |||
| 75 | #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ | ||
| 76 | #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ | ||
| 77 | #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ | ||
| 78 | #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ | ||
| 79 | #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ | ||
| 80 | #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ | ||
| 81 | #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ | ||
| 82 | #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ | ||
| 83 | |||
| 84 | #if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | ||
| 85 | #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ | ||
| 86 | #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ | ||
| 87 | #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ | ||
| 88 | #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ | ||
| 89 | #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ | ||
| 90 | #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ | ||
| 91 | #define DCSR_EORINTR (1 << 9) /* The end of Receive */ | ||
| 92 | #endif | ||
| 93 | |||
| 94 | #define DALGN __REG(0x400000a0) /* DMA Alignment Register */ | ||
| 95 | #define DINT __REG(0x400000f0) /* DMA Interrupt Register */ | ||
| 96 | |||
| 97 | #define DRCMR(n) (*(((n) < 64) ? \ | ||
| 98 | &__REG2(0x40000100, ((n) & 0x3f) << 2) : \ | ||
| 99 | &__REG2(0x40001100, ((n) & 0x3f) << 2))) | ||
| 100 | |||
| 101 | #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ | ||
| 102 | #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ | ||
| 103 | |||
| 104 | #define DDADR(x) __REG2(0x40000200, (x) << 4) | ||
| 105 | #define DSADR(x) __REG2(0x40000204, (x) << 4) | ||
| 106 | #define DTADR(x) __REG2(0x40000208, (x) << 4) | ||
| 107 | #define DCMD(x) __REG2(0x4000020c, (x) << 4) | ||
| 108 | |||
| 109 | #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ | ||
| 110 | #define DDADR_STOP (1 << 0) /* Stop (read / write) */ | ||
| 111 | |||
| 112 | #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ | ||
| 113 | #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ | ||
| 114 | #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ | ||
| 115 | #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ | ||
| 116 | #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ | ||
| 117 | #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ | ||
| 118 | #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ | ||
| 119 | #define DCMD_BURST8 (1 << 16) /* 8 byte burst */ | ||
| 120 | #define DCMD_BURST16 (2 << 16) /* 16 byte burst */ | ||
| 121 | #define DCMD_BURST32 (3 << 16) /* 32 byte burst */ | ||
| 122 | #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ | ||
| 123 | #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ | ||
| 124 | #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ | ||
| 125 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | ||
| 126 | |||
| 127 | /* | ||
| 128 | * Real Time Clock | ||
| 129 | */ | ||
| 130 | |||
| 131 | #define RCNR __REG(0x40900000) /* RTC Count Register */ | ||
| 132 | #define RTAR __REG(0x40900004) /* RTC Alarm Register */ | ||
| 133 | #define RTSR __REG(0x40900008) /* RTC Status Register */ | ||
| 134 | #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ | ||
| 135 | #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ | ||
| 136 | |||
| 137 | #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ | ||
| 138 | #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ | ||
| 139 | #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ | ||
| 140 | #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ | ||
| 141 | #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ | ||
| 142 | #define RTSR_AL (1 << 0) /* RTC alarm detected */ | ||
| 143 | |||
| 144 | |||
| 145 | /* | ||
| 146 | * OS Timer & Match Registers | ||
| 147 | */ | ||
| 148 | |||
| 149 | #define OSMR0 __REG(0x40A00000) /* */ | ||
| 150 | #define OSMR1 __REG(0x40A00004) /* */ | ||
| 151 | #define OSMR2 __REG(0x40A00008) /* */ | ||
| 152 | #define OSMR3 __REG(0x40A0000C) /* */ | ||
| 153 | #define OSMR4 __REG(0x40A00080) /* */ | ||
| 154 | #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ | ||
| 155 | #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ | ||
| 156 | #define OMCR4 __REG(0x40A000C0) /* */ | ||
| 157 | #define OSSR __REG(0x40A00014) /* OS Timer Status Register */ | ||
| 158 | #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ | ||
| 159 | #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ | ||
| 160 | |||
| 161 | #define OSSR_M3 (1 << 3) /* Match status channel 3 */ | ||
| 162 | #define OSSR_M2 (1 << 2) /* Match status channel 2 */ | ||
| 163 | #define OSSR_M1 (1 << 1) /* Match status channel 1 */ | ||
| 164 | #define OSSR_M0 (1 << 0) /* Match status channel 0 */ | ||
| 165 | |||
| 166 | #define OWER_WME (1 << 0) /* Watchdog Match Enable */ | ||
| 167 | |||
| 168 | #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ | ||
| 169 | #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ | ||
| 170 | #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ | ||
| 171 | #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ | ||
| 172 | |||
| 173 | |||
| 174 | /* | ||
| 175 | * Interrupt Controller | ||
| 176 | */ | ||
| 177 | |||
| 178 | #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ | ||
| 179 | #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ | ||
| 180 | #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ | ||
| 181 | #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ | ||
| 182 | #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ | ||
| 183 | #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ | ||
| 184 | |||
| 185 | #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ | ||
| 186 | #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ | ||
| 187 | #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ | ||
| 188 | #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ | ||
| 189 | #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ | ||
| 190 | |||
| 191 | /* | ||
| 192 | * General Purpose I/O | ||
| 193 | */ | ||
| 194 | |||
| 195 | #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ | ||
| 196 | #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ | ||
| 197 | #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ | ||
| 198 | |||
| 199 | #define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */ | ||
| 200 | #define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */ | ||
| 201 | #define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */ | ||
| 202 | |||
| 203 | #define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */ | ||
| 204 | #define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */ | ||
| 205 | #define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */ | ||
| 206 | |||
| 207 | #define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */ | ||
| 208 | #define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */ | ||
| 209 | #define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */ | ||
| 210 | |||
| 211 | #define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */ | ||
| 212 | #define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */ | ||
| 213 | #define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */ | ||
| 214 | |||
| 215 | #define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ | ||
| 216 | #define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */ | ||
| 217 | #define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */ | ||
| 218 | |||
| 219 | #define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */ | ||
| 220 | #define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */ | ||
| 221 | #define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */ | ||
| 222 | |||
| 223 | #define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */ | ||
| 224 | #define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */ | ||
| 225 | #define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */ | ||
| 226 | #define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */ | ||
| 227 | #define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */ | ||
| 228 | #define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO<95-80> */ | ||
| 229 | #define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */ | ||
| 230 | #define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */ | ||
| 231 | |||
| 232 | #define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ | ||
| 233 | #define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ | ||
| 234 | #define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ | ||
| 235 | #define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */ | ||
| 236 | #define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ | ||
| 237 | #define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */ | ||
| 238 | #define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ | ||
| 239 | |||
| 240 | /* More handy macros. The argument is a literal GPIO number. */ | ||
| 241 | |||
| 242 | #define GPIO_bit(x) (1 << ((x) & 0x1f)) | ||
| 243 | |||
| 244 | #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) | ||
| 245 | #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) | ||
| 246 | #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) | ||
| 247 | #define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) | ||
| 248 | #define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) | ||
| 249 | #define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) | ||
| 250 | #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) | ||
| 251 | #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) | ||
| 252 | |||
| 253 | #define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3)) | ||
| 254 | #define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3)) | ||
| 255 | #define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3)) | ||
| 256 | #define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3)) | ||
| 257 | #define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3)) | ||
| 258 | #define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3)) | ||
| 259 | #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) | ||
| 260 | #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ | ||
| 261 | ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) | ||
| 262 | |||
| 263 | #endif | ||
diff --git a/arch/arm/mach-pxa/include/mach/pxa25x.h b/arch/arm/mach-pxa/include/mach/pxa25x.h new file mode 100644 index 000000000000..508c3ba1f4d0 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa25x.h | |||
| @@ -0,0 +1,8 @@ | |||
| 1 | #ifndef __MACH_PXA25x_H | ||
| 2 | #define __MACH_PXA25x_H | ||
| 3 | |||
| 4 | #include <mach/hardware.h> | ||
| 5 | #include <mach/pxa2xx-regs.h> | ||
| 6 | #include <mach/mfp-pxa25x.h> | ||
| 7 | |||
| 8 | #endif /* __MACH_PXA25x_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x.h b/arch/arm/mach-pxa/include/mach/pxa27x.h new file mode 100644 index 000000000000..6876e16c2970 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa27x.h | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | #ifndef __MACH_PXA27x_H | ||
| 2 | #define __MACH_PXA27x_H | ||
| 3 | |||
| 4 | #include <mach/hardware.h> | ||
| 5 | #include <mach/pxa2xx-regs.h> | ||
| 6 | #include <mach/mfp-pxa27x.h> | ||
| 7 | |||
| 8 | #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ | ||
| 9 | |||
| 10 | #define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ | ||
| 11 | #define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ | ||
| 12 | #define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ | ||
| 13 | #define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ | ||
| 14 | #define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ | ||
| 15 | #define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ | ||
| 16 | #define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ | ||
| 17 | #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ | ||
| 18 | #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ | ||
| 19 | #endif /* __MACH_PXA27x_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h index d83393e25273..1209c44aa6f1 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-gpio.h | |||
| @@ -3,6 +3,8 @@ | |||
| 3 | 3 | ||
| 4 | #warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h | 4 | #warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h |
| 5 | 5 | ||
| 6 | #include <mach/gpio.h> | ||
| 7 | |||
| 6 | /* GPIO alternate function assignments */ | 8 | /* GPIO alternate function assignments */ |
| 7 | 9 | ||
| 8 | #define GPIO1_RST 1 /* reset */ | 10 | #define GPIO1_RST 1 /* reset */ |
diff --git a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h index 77102d695cc7..4fcddd9cab76 100644 --- a/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa2xx-regs.h | |||
| @@ -14,6 +14,19 @@ | |||
| 14 | #ifndef __PXA2XX_REGS_H | 14 | #ifndef __PXA2XX_REGS_H |
| 15 | #define __PXA2XX_REGS_H | 15 | #define __PXA2XX_REGS_H |
| 16 | 16 | ||
| 17 | #include <mach/hardware.h> | ||
| 18 | |||
| 19 | /* | ||
| 20 | * PXA Chip selects | ||
| 21 | */ | ||
| 22 | |||
| 23 | #define PXA_CS0_PHYS 0x00000000 | ||
| 24 | #define PXA_CS1_PHYS 0x04000000 | ||
| 25 | #define PXA_CS2_PHYS 0x08000000 | ||
| 26 | #define PXA_CS3_PHYS 0x0C000000 | ||
| 27 | #define PXA_CS4_PHYS 0x10000000 | ||
| 28 | #define PXA_CS5_PHYS 0x14000000 | ||
| 29 | |||
| 17 | /* | 30 | /* |
| 18 | * Memory controller | 31 | * Memory controller |
| 19 | */ | 32 | */ |
| @@ -69,24 +82,6 @@ | |||
| 69 | #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ | 82 | #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ |
| 70 | #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ | 83 | #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ |
| 71 | 84 | ||
| 72 | |||
| 73 | #ifdef CONFIG_PXA27x | ||
| 74 | |||
| 75 | #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ | ||
| 76 | |||
| 77 | #define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ | ||
| 78 | #define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ | ||
| 79 | #define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */ | ||
| 80 | #define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */ | ||
| 81 | #define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */ | ||
| 82 | #define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */ | ||
| 83 | #define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */ | ||
| 84 | #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ | ||
| 85 | #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ | ||
| 86 | |||
| 87 | #endif | ||
| 88 | |||
| 89 | |||
| 90 | /* | 85 | /* |
| 91 | * Power Manager | 86 | * Power Manager |
| 92 | */ | 87 | */ |
diff --git a/arch/arm/mach-pxa/include/mach/pxa300.h b/arch/arm/mach-pxa/include/mach/pxa300.h new file mode 100644 index 000000000000..2f33076c9e48 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa300.h | |||
| @@ -0,0 +1,8 @@ | |||
| 1 | #ifndef __MACH_PXA300_H | ||
| 2 | #define __MACH_PXA300_H | ||
| 3 | |||
| 4 | #include <mach/hardware.h> | ||
| 5 | #include <mach/pxa3xx-regs.h> | ||
| 6 | #include <mach/mfp-pxa300.h> | ||
| 7 | |||
| 8 | #endif /* __MACH_PXA300_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/pxa320.h b/arch/arm/mach-pxa/include/mach/pxa320.h new file mode 100644 index 000000000000..cab78e903273 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa320.h | |||
| @@ -0,0 +1,9 @@ | |||
| 1 | #ifndef __MACH_PXA320_H | ||
| 2 | #define __MACH_PXA320_H | ||
| 3 | |||
| 4 | #include <mach/hardware.h> | ||
| 5 | #include <mach/pxa3xx-regs.h> | ||
| 6 | #include <mach/mfp-pxa320.h> | ||
| 7 | |||
| 8 | #endif /* __MACH_PXA320_H */ | ||
| 9 | |||
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h index bcf3fb2c4b3a..7d1a059b3d43 100644 --- a/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h +++ b/arch/arm/mach-pxa/include/mach/pxa3xx-regs.h | |||
| @@ -13,6 +13,17 @@ | |||
| 13 | #ifndef __ASM_ARCH_PXA3XX_REGS_H | 13 | #ifndef __ASM_ARCH_PXA3XX_REGS_H |
| 14 | #define __ASM_ARCH_PXA3XX_REGS_H | 14 | #define __ASM_ARCH_PXA3XX_REGS_H |
| 15 | 15 | ||
| 16 | #include <mach/hardware.h> | ||
| 17 | |||
| 18 | /* | ||
| 19 | * Static Chip Selects | ||
| 20 | */ | ||
| 21 | |||
| 22 | #define PXA300_CS0_PHYS (0x00000000) /* PXA300/PXA310 _only_ */ | ||
| 23 | #define PXA300_CS1_PHYS (0x30000000) /* PXA300/PXA310 _only_ */ | ||
| 24 | #define PXA3xx_CS2_PHYS (0x10000000) | ||
| 25 | #define PXA3xx_CS3_PHYS (0x14000000) | ||
| 26 | |||
| 16 | /* | 27 | /* |
| 17 | * Oscillator Configuration Register (OSCC) | 28 | * Oscillator Configuration Register (OSCC) |
| 18 | */ | 29 | */ |
diff --git a/arch/arm/mach-pxa/include/mach/pxa930.h b/arch/arm/mach-pxa/include/mach/pxa930.h new file mode 100644 index 000000000000..d45f76a9b54d --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/pxa930.h | |||
| @@ -0,0 +1,8 @@ | |||
| 1 | #ifndef __MACH_PXA930_H | ||
| 2 | #define __MACH_PXA930_H | ||
| 3 | |||
| 4 | #include <mach/hardware.h> | ||
| 5 | #include <mach/pxa3xx-regs.h> | ||
| 6 | #include <mach/mfp-pxa930.h> | ||
| 7 | |||
| 8 | #endif /* __MACH_PXA930_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h new file mode 100644 index 000000000000..ad23e74b762f --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-intc.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | #ifndef __ASM_MACH_REGS_INTC_H | ||
| 2 | #define __ASM_MACH_REGS_INTC_H | ||
| 3 | |||
| 4 | #include <mach/hardware.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * Interrupt Controller | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ | ||
| 11 | #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ | ||
| 12 | #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ | ||
| 13 | #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ | ||
| 14 | #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ | ||
| 15 | #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ | ||
| 16 | |||
| 17 | #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ | ||
| 18 | #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ | ||
| 19 | #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ | ||
| 20 | #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ | ||
| 21 | #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ | ||
| 22 | |||
| 23 | #endif /* __ASM_MACH_REGS_INTC_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/regs-ost.h b/arch/arm/mach-pxa/include/mach/regs-ost.h new file mode 100644 index 000000000000..a3e5f86ef67e --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-ost.h | |||
| @@ -0,0 +1,34 @@ | |||
| 1 | #ifndef __ASM_MACH_REGS_OST_H | ||
| 2 | #define __ASM_MACH_REGS_OST_H | ||
| 3 | |||
| 4 | #include <mach/hardware.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * OS Timer & Match Registers | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define OSMR0 __REG(0x40A00000) /* */ | ||
| 11 | #define OSMR1 __REG(0x40A00004) /* */ | ||
| 12 | #define OSMR2 __REG(0x40A00008) /* */ | ||
| 13 | #define OSMR3 __REG(0x40A0000C) /* */ | ||
| 14 | #define OSMR4 __REG(0x40A00080) /* */ | ||
| 15 | #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ | ||
| 16 | #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ | ||
| 17 | #define OMCR4 __REG(0x40A000C0) /* */ | ||
| 18 | #define OSSR __REG(0x40A00014) /* OS Timer Status Register */ | ||
| 19 | #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ | ||
| 20 | #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ | ||
| 21 | |||
| 22 | #define OSSR_M3 (1 << 3) /* Match status channel 3 */ | ||
| 23 | #define OSSR_M2 (1 << 2) /* Match status channel 2 */ | ||
| 24 | #define OSSR_M1 (1 << 1) /* Match status channel 1 */ | ||
| 25 | #define OSSR_M0 (1 << 0) /* Match status channel 0 */ | ||
| 26 | |||
| 27 | #define OWER_WME (1 << 0) /* Watchdog Match Enable */ | ||
| 28 | |||
| 29 | #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */ | ||
| 30 | #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */ | ||
| 31 | #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ | ||
| 32 | #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ | ||
| 33 | |||
| 34 | #endif /* __ASM_MACH_REGS_OST_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/regs-rtc.h b/arch/arm/mach-pxa/include/mach/regs-rtc.h new file mode 100644 index 000000000000..f0e4a589bbe1 --- /dev/null +++ b/arch/arm/mach-pxa/include/mach/regs-rtc.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | #ifndef __ASM_MACH_REGS_RTC_H | ||
| 2 | #define __ASM_MACH_REGS_RTC_H | ||
| 3 | |||
| 4 | #include <mach/hardware.h> | ||
| 5 | |||
| 6 | /* | ||
| 7 | * Real Time Clock | ||
| 8 | */ | ||
| 9 | |||
| 10 | #define RCNR __REG(0x40900000) /* RTC Count Register */ | ||
| 11 | #define RTAR __REG(0x40900004) /* RTC Alarm Register */ | ||
| 12 | #define RTSR __REG(0x40900008) /* RTC Status Register */ | ||
| 13 | #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ | ||
| 14 | #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ | ||
| 15 | |||
| 16 | #define RTSR_PICE (1 << 15) /* Periodic interrupt count enable */ | ||
| 17 | #define RTSR_PIALE (1 << 14) /* Periodic interrupt Alarm enable */ | ||
| 18 | #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ | ||
| 19 | #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ | ||
| 20 | #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ | ||
| 21 | #define RTSR_AL (1 << 0) /* RTC alarm detected */ | ||
| 22 | |||
| 23 | #endif /* __ASM_MACH_REGS_RTC_H */ | ||
diff --git a/arch/arm/mach-pxa/include/mach/regs-ssp.h b/arch/arm/mach-pxa/include/mach/regs-ssp.h index cf31986f6f05..8152be683881 100644 --- a/arch/arm/mach-pxa/include/mach/regs-ssp.h +++ b/arch/arm/mach-pxa/include/mach/regs-ssp.h | |||
| @@ -37,7 +37,6 @@ | |||
| 37 | #if defined(CONFIG_PXA25x) | 37 | #if defined(CONFIG_PXA25x) |
| 38 | #define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ | 38 | #define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */ |
| 39 | #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ | 39 | #define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */ |
| 40 | |||
| 41 | #elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) | 40 | #elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) |
| 42 | #define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ | 41 | #define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */ |
| 43 | #define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ | 42 | #define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */ |
diff --git a/arch/arm/mach-pxa/include/mach/system.h b/arch/arm/mach-pxa/include/mach/system.h index 0f381e692999..d1fce8b6d105 100644 --- a/arch/arm/mach-pxa/include/mach/system.h +++ b/arch/arm/mach-pxa/include/mach/system.h | |||
| @@ -13,7 +13,6 @@ | |||
| 13 | #include <asm/proc-fns.h> | 13 | #include <asm/proc-fns.h> |
| 14 | #include "hardware.h" | 14 | #include "hardware.h" |
| 15 | #include "pxa2xx-regs.h" | 15 | #include "pxa2xx-regs.h" |
| 16 | #include "pxa-regs.h" | ||
| 17 | 16 | ||
| 18 | static inline void arch_idle(void) | 17 | static inline void arch_idle(void) |
| 19 | { | 18 | { |
| @@ -21,4 +20,4 @@ static inline void arch_idle(void) | |||
| 21 | } | 20 | } |
| 22 | 21 | ||
| 23 | 22 | ||
| 24 | void arch_reset(char mode); | 23 | void arch_reset(char mode, const char *cmd); |
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h index f4b029c03957..5706cea95d11 100644 --- a/arch/arm/mach-pxa/include/mach/uncompress.h +++ b/arch/arm/mach-pxa/include/mach/uncompress.h | |||
| @@ -35,7 +35,8 @@ static inline void flush(void) | |||
| 35 | 35 | ||
| 36 | static inline void arch_decomp_setup(void) | 36 | static inline void arch_decomp_setup(void) |
| 37 | { | 37 | { |
| 38 | if (machine_is_littleton() || machine_is_intelmote2()) | 38 | if (machine_is_littleton() || machine_is_intelmote2() |
| 39 | || machine_is_csb726()) | ||
| 39 | UART = STUART; | 40 | UART = STUART; |
| 40 | } | 41 | } |
| 41 | 42 | ||
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index fa69c3a6a38e..f6e0300e4f64 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
| @@ -20,7 +20,8 @@ | |||
| 20 | #include <mach/hardware.h> | 20 | #include <mach/hardware.h> |
| 21 | #include <asm/irq.h> | 21 | #include <asm/irq.h> |
| 22 | #include <asm/mach/irq.h> | 22 | #include <asm/mach/irq.h> |
| 23 | #include <mach/pxa-regs.h> | 23 | #include <mach/gpio.h> |
| 24 | #include <mach/regs-intc.h> | ||
| 24 | 25 | ||
| 25 | #include "generic.h" | 26 | #include "generic.h" |
| 26 | 27 | ||
| @@ -51,6 +52,72 @@ static struct irq_chip pxa_internal_irq_chip = { | |||
| 51 | .unmask = pxa_unmask_irq, | 52 | .unmask = pxa_unmask_irq, |
| 52 | }; | 53 | }; |
| 53 | 54 | ||
| 55 | /* | ||
| 56 | * GPIO IRQs for GPIO 0 and 1 | ||
| 57 | */ | ||
| 58 | static int pxa_set_low_gpio_type(unsigned int irq, unsigned int type) | ||
| 59 | { | ||
| 60 | int gpio = irq - IRQ_GPIO0; | ||
| 61 | |||
| 62 | if (__gpio_is_occupied(gpio)) { | ||
| 63 | pr_err("%s failed: GPIO is configured\n", __func__); | ||
| 64 | return -EINVAL; | ||
| 65 | } | ||
| 66 | |||
| 67 | if (type & IRQ_TYPE_EDGE_RISING) | ||
| 68 | GRER0 |= GPIO_bit(gpio); | ||
| 69 | else | ||
| 70 | GRER0 &= ~GPIO_bit(gpio); | ||
| 71 | |||
| 72 | if (type & IRQ_TYPE_EDGE_FALLING) | ||
| 73 | GFER0 |= GPIO_bit(gpio); | ||
| 74 | else | ||
| 75 | GFER0 &= ~GPIO_bit(gpio); | ||
| 76 | |||
| 77 | return 0; | ||
| 78 | } | ||
| 79 | |||
| 80 | static void pxa_ack_low_gpio(unsigned int irq) | ||
| 81 | { | ||
| 82 | GEDR0 = (1 << (irq - IRQ_GPIO0)); | ||
| 83 | } | ||
| 84 | |||
| 85 | static void pxa_mask_low_gpio(unsigned int irq) | ||
| 86 | { | ||
| 87 | ICMR &= ~(1 << (irq - PXA_IRQ(0))); | ||
| 88 | } | ||
| 89 | |||
| 90 | static void pxa_unmask_low_gpio(unsigned int irq) | ||
| 91 | { | ||
| 92 | ICMR |= 1 << (irq - PXA_IRQ(0)); | ||
| 93 | } | ||
| 94 | |||
| 95 | static struct irq_chip pxa_low_gpio_chip = { | ||
| 96 | .name = "GPIO-l", | ||
| 97 | .ack = pxa_ack_low_gpio, | ||
| 98 | .mask = pxa_mask_low_gpio, | ||
| 99 | .unmask = pxa_unmask_low_gpio, | ||
| 100 | .set_type = pxa_set_low_gpio_type, | ||
| 101 | }; | ||
| 102 | |||
| 103 | static void __init pxa_init_low_gpio_irq(set_wake_t fn) | ||
| 104 | { | ||
| 105 | int irq; | ||
| 106 | |||
| 107 | /* clear edge detection on GPIO 0 and 1 */ | ||
| 108 | GFER0 &= ~0x3; | ||
| 109 | GRER0 &= ~0x3; | ||
| 110 | GEDR0 = 0x3; | ||
| 111 | |||
| 112 | for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { | ||
| 113 | set_irq_chip(irq, &pxa_low_gpio_chip); | ||
| 114 | set_irq_handler(irq, handle_edge_irq); | ||
| 115 | set_irq_flags(irq, IRQF_VALID); | ||
| 116 | } | ||
| 117 | |||
| 118 | pxa_low_gpio_chip.set_wake = fn; | ||
| 119 | } | ||
| 120 | |||
| 54 | void __init pxa_init_irq(int irq_nr, set_wake_t fn) | 121 | void __init pxa_init_irq(int irq_nr, set_wake_t fn) |
| 55 | { | 122 | { |
| 56 | int irq; | 123 | int irq; |
| @@ -72,6 +139,7 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn) | |||
| 72 | } | 139 | } |
| 73 | 140 | ||
| 74 | pxa_internal_irq_chip.set_wake = fn; | 141 | pxa_internal_irq_chip.set_wake = fn; |
| 142 | pxa_init_low_gpio_irq(fn); | ||
| 75 | } | 143 | } |
| 76 | 144 | ||
| 77 | #ifdef CONFIG_PM | 145 | #ifdef CONFIG_PM |
diff --git a/arch/arm/mach-pxa/leds-idp.c b/arch/arm/mach-pxa/leds-idp.c index 18b20d469410..8b9c17142d5a 100644 --- a/arch/arm/mach-pxa/leds-idp.c +++ b/arch/arm/mach-pxa/leds-idp.c | |||
| @@ -18,7 +18,7 @@ | |||
| 18 | #include <asm/leds.h> | 18 | #include <asm/leds.h> |
| 19 | #include <asm/system.h> | 19 | #include <asm/system.h> |
| 20 | 20 | ||
| 21 | #include <mach/pxa-regs.h> | 21 | #include <mach/pxa25x.h> |
| 22 | #include <mach/idp.h> | 22 | #include <mach/idp.h> |
| 23 | 23 | ||
| 24 | #include "leds.h" | 24 | #include "leds.h" |
diff --git a/arch/arm/mach-pxa/leds-lubbock.c b/arch/arm/mach-pxa/leds-lubbock.c index 1a258029c33c..e26d5efe1969 100644 --- a/arch/arm/mach-pxa/leds-lubbock.c +++ b/arch/arm/mach-pxa/leds-lubbock.c | |||
| @@ -16,7 +16,7 @@ | |||
| 16 | #include <mach/hardware.h> | 16 | #include <mach/hardware.h> |
| 17 | #include <asm/leds.h> | 17 | #include <asm/leds.h> |
| 18 | #include <asm/system.h> | 18 | #include <asm/system.h> |
| 19 | #include <mach/pxa-regs.h> | 19 | #include <mach/pxa25x.h> |
| 20 | #include <mach/lubbock.h> | 20 | #include <mach/lubbock.h> |
| 21 | 21 | ||
| 22 | #include "leds.h" | 22 | #include "leds.h" |
diff --git a/arch/arm/mach-pxa/leds-mainstone.c b/arch/arm/mach-pxa/leds-mainstone.c index 95e06b849634..db4af5eee8b2 100644 --- a/arch/arm/mach-pxa/leds-mainstone.c +++ b/arch/arm/mach-pxa/leds-mainstone.c | |||
| @@ -16,7 +16,7 @@ | |||
| 16 | #include <asm/leds.h> | 16 | #include <asm/leds.h> |
| 17 | #include <asm/system.h> | 17 | #include <asm/system.h> |
| 18 | 18 | ||
| 19 | #include <mach/pxa-regs.h> | 19 | #include <mach/pxa27x.h> |
| 20 | #include <mach/mainstone.h> | 20 | #include <mach/mainstone.h> |
| 21 | 21 | ||
| 22 | #include "leds.h" | 22 | #include "leds.h" |
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c index 31da7f3c06f6..e13f6a81c223 100644 --- a/arch/arm/mach-pxa/littleton.c +++ b/arch/arm/mach-pxa/littleton.c | |||
| @@ -39,8 +39,7 @@ | |||
| 39 | #include <asm/mach/map.h> | 39 | #include <asm/mach/map.h> |
| 40 | #include <asm/mach/irq.h> | 40 | #include <asm/mach/irq.h> |
| 41 | 41 | ||
| 42 | #include <mach/pxa-regs.h> | 42 | #include <mach/pxa300.h> |
| 43 | #include <mach/mfp-pxa300.h> | ||
| 44 | #include <mach/pxafb.h> | 43 | #include <mach/pxafb.h> |
| 45 | #include <mach/ssp.h> | 44 | #include <mach/ssp.h> |
| 46 | #include <mach/pxa2xx_spi.h> | 45 | #include <mach/pxa2xx_spi.h> |
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c index de3f67daaacf..d64395f26a3e 100644 --- a/arch/arm/mach-pxa/lpd270.c +++ b/arch/arm/mach-pxa/lpd270.c | |||
| @@ -38,9 +38,8 @@ | |||
| 38 | #include <asm/mach/irq.h> | 38 | #include <asm/mach/irq.h> |
| 39 | #include <asm/mach/flash.h> | 39 | #include <asm/mach/flash.h> |
| 40 | 40 | ||
| 41 | #include <mach/pxa-regs.h> | 41 | #include <mach/pxa27x.h> |
| 42 | #include <mach/pxa2xx-regs.h> | 42 | #include <mach/gpio.h> |
| 43 | #include <mach/mfp-pxa27x.h> | ||
| 44 | #include <mach/lpd270.h> | 43 | #include <mach/lpd270.h> |
| 45 | #include <mach/audio.h> | 44 | #include <mach/audio.h> |
| 46 | #include <mach/pxafb.h> | 45 | #include <mach/pxafb.h> |
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c index bff704354c1a..f04c8333dff7 100644 --- a/arch/arm/mach-pxa/lubbock.c +++ b/arch/arm/mach-pxa/lubbock.c | |||
| @@ -41,15 +41,15 @@ | |||
| 41 | 41 | ||
| 42 | #include <asm/hardware/sa1111.h> | 42 | #include <asm/hardware/sa1111.h> |
| 43 | 43 | ||
| 44 | #include <mach/pxa-regs.h> | 44 | #include <mach/pxa25x.h> |
| 45 | #include <mach/pxa2xx-regs.h> | 45 | #include <mach/gpio.h> |
| 46 | #include <mach/mfp-pxa25x.h> | ||
| 47 | #include <mach/audio.h> | 46 | #include <mach/audio.h> |
| 48 | #include <mach/lubbock.h> | 47 | #include <mach/lubbock.h> |
| 49 | #include <mach/udc.h> | 48 | #include <mach/udc.h> |
| 50 | #include <mach/irda.h> | 49 | #include <mach/irda.h> |
| 51 | #include <mach/pxafb.h> | 50 | #include <mach/pxafb.h> |
| 52 | #include <mach/mmc.h> | 51 | #include <mach/mmc.h> |
| 52 | #include <mach/pm.h> | ||
| 53 | 53 | ||
| 54 | #include "generic.h" | 54 | #include "generic.h" |
| 55 | #include "clock.h" | 55 | #include "clock.h" |
| @@ -113,8 +113,14 @@ static unsigned long lubbock_pin_config[] __initdata = { | |||
| 113 | GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, | 113 | GPIO1_GPIO | WAKEUP_ON_EDGE_RISE, |
| 114 | }; | 114 | }; |
| 115 | 115 | ||
| 116 | #define LUB_HEXLED __LUB_REG(LUBBOCK_FPGA_PHYS + 0x010) | ||
| 116 | #define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080) | 117 | #define LUB_MISC_WR __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080) |
| 117 | 118 | ||
| 119 | void lubbock_set_hexled(uint32_t value) | ||
| 120 | { | ||
| 121 | LUB_HEXLED = value; | ||
| 122 | } | ||
| 123 | |||
| 118 | void lubbock_set_misc_wr(unsigned int mask, unsigned int set) | 124 | void lubbock_set_misc_wr(unsigned int mask, unsigned int set) |
| 119 | { | 125 | { |
| 120 | unsigned long flags; | 126 | unsigned long flags; |
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index 21b821e1a60d..d46b36746be2 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c | |||
| @@ -25,14 +25,14 @@ | |||
| 25 | #include <linux/mtd/physmap.h> | 25 | #include <linux/mtd/physmap.h> |
| 26 | #include <linux/pda_power.h> | 26 | #include <linux/pda_power.h> |
| 27 | #include <linux/pwm_backlight.h> | 27 | #include <linux/pwm_backlight.h> |
| 28 | #include <linux/usb/gpio_vbus.h> | ||
| 28 | 29 | ||
| 29 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
| 30 | #include <asm/mach-types.h> | 31 | #include <asm/mach-types.h> |
| 31 | #include <asm/mach/arch.h> | 32 | #include <asm/mach/arch.h> |
| 33 | |||
| 34 | #include <mach/pxa27x.h> | ||
| 32 | #include <mach/magician.h> | 35 | #include <mach/magician.h> |
| 33 | #include <mach/mfp-pxa27x.h> | ||
| 34 | #include <mach/pxa-regs.h> | ||
| 35 | #include <mach/pxa2xx-regs.h> | ||
| 36 | #include <mach/pxafb.h> | 36 | #include <mach/pxafb.h> |
| 37 | #include <mach/i2c.h> | 37 | #include <mach/i2c.h> |
| 38 | #include <mach/mmc.h> | 38 | #include <mach/mmc.h> |
| @@ -66,6 +66,11 @@ static unsigned long magician_pin_config[] __initdata = { | |||
| 66 | GPIO31_I2S_SYNC, | 66 | GPIO31_I2S_SYNC, |
| 67 | GPIO113_I2S_SYSCLK, | 67 | GPIO113_I2S_SYSCLK, |
| 68 | 68 | ||
| 69 | /* SSP 1 */ | ||
| 70 | GPIO23_SSP1_SCLK, | ||
| 71 | GPIO24_SSP1_SFRM, | ||
| 72 | GPIO25_SSP1_TXD, | ||
| 73 | |||
| 69 | /* SSP 2 */ | 74 | /* SSP 2 */ |
| 70 | GPIO19_SSP2_SCLK, | 75 | GPIO19_SSP2_SCLK, |
| 71 | GPIO14_SSP2_SFRM, | 76 | GPIO14_SSP2_SFRM, |
| @@ -148,22 +153,31 @@ static struct pxaficp_platform_data magician_ficp_info = { | |||
| 148 | * GPIO Keys | 153 | * GPIO Keys |
| 149 | */ | 154 | */ |
| 150 | 155 | ||
| 156 | #define INIT_KEY(_code, _gpio, _desc) \ | ||
| 157 | { \ | ||
| 158 | .code = KEY_##_code, \ | ||
| 159 | .gpio = _gpio, \ | ||
| 160 | .desc = _desc, \ | ||
| 161 | .type = EV_KEY, \ | ||
| 162 | .wakeup = 1, \ | ||
| 163 | } | ||
| 164 | |||
| 151 | static struct gpio_keys_button magician_button_table[] = { | 165 | static struct gpio_keys_button magician_button_table[] = { |
| 152 | {KEY_POWER, GPIO0_MAGICIAN_KEY_POWER, 0, "Power button"}, | 166 | INIT_KEY(POWER, GPIO0_MAGICIAN_KEY_POWER, "Power button"), |
| 153 | {KEY_ESC, GPIO37_MAGICIAN_KEY_HANGUP, 0, "Hangup button"}, | 167 | INIT_KEY(ESC, GPIO37_MAGICIAN_KEY_HANGUP, "Hangup button"), |
| 154 | {KEY_F10, GPIO38_MAGICIAN_KEY_CONTACTS, 0, "Contacts button"}, | 168 | INIT_KEY(F10, GPIO38_MAGICIAN_KEY_CONTACTS, "Contacts button"), |
| 155 | {KEY_CALENDAR, GPIO90_MAGICIAN_KEY_CALENDAR, 0, "Calendar button"}, | 169 | INIT_KEY(CALENDAR, GPIO90_MAGICIAN_KEY_CALENDAR, "Calendar button"), |
| 156 | {KEY_CAMERA, GPIO91_MAGICIAN_KEY_CAMERA, 0, "Camera button"}, | 170 | INIT_KEY(CAMERA, GPIO91_MAGICIAN_KEY_CAMERA, "Camera button"), |
| 157 | {KEY_UP, GPIO93_MAGICIAN_KEY_UP, 0, "Up button"}, | 171 | INIT_KEY(UP, GPIO93_MAGICIAN_KEY_UP, "Up button"), |
| 158 | {KEY_DOWN, GPIO94_MAGICIAN_KEY_DOWN, 0, "Down button"}, | 172 | INIT_KEY(DOWN, GPIO94_MAGICIAN_KEY_DOWN, "Down button"), |
| 159 | {KEY_LEFT, GPIO95_MAGICIAN_KEY_LEFT, 0, "Left button"}, | 173 | INIT_KEY(LEFT, GPIO95_MAGICIAN_KEY_LEFT, "Left button"), |
| 160 | {KEY_RIGHT, GPIO96_MAGICIAN_KEY_RIGHT, 0, "Right button"}, | 174 | INIT_KEY(RIGHT, GPIO96_MAGICIAN_KEY_RIGHT, "Right button"), |
| 161 | {KEY_KPENTER, GPIO97_MAGICIAN_KEY_ENTER, 0, "Action button"}, | 175 | INIT_KEY(KPENTER, GPIO97_MAGICIAN_KEY_ENTER, "Action button"), |
| 162 | {KEY_RECORD, GPIO98_MAGICIAN_KEY_RECORD, 0, "Record button"}, | 176 | INIT_KEY(RECORD, GPIO98_MAGICIAN_KEY_RECORD, "Record button"), |
| 163 | {KEY_VOLUMEUP, GPIO100_MAGICIAN_KEY_VOL_UP, 0, "Volume up"}, | 177 | INIT_KEY(VOLUMEUP, GPIO100_MAGICIAN_KEY_VOL_UP, "Volume up"), |
| 164 | {KEY_VOLUMEDOWN, GPIO101_MAGICIAN_KEY_VOL_DOWN, 0, "Volume down"}, | 178 | INIT_KEY(VOLUMEDOWN, GPIO101_MAGICIAN_KEY_VOL_DOWN, "Volume down"), |
| 165 | {KEY_PHONE, GPIO102_MAGICIAN_KEY_PHONE, 0, "Phone button"}, | 179 | INIT_KEY(PHONE, GPIO102_MAGICIAN_KEY_PHONE, "Phone button"), |
| 166 | {KEY_PLAY, GPIO99_MAGICIAN_HEADPHONE_IN, 0, "Headset button"}, | 180 | INIT_KEY(PLAY, GPIO99_MAGICIAN_HEADPHONE_IN, "Headset button"), |
| 167 | }; | 181 | }; |
| 168 | 182 | ||
| 169 | static struct gpio_keys_platform_data gpio_keys_data = { | 183 | static struct gpio_keys_platform_data gpio_keys_data = { |
| @@ -189,7 +203,7 @@ static struct platform_device gpio_keys = { | |||
| 189 | static struct resource egpio_resources[] = { | 203 | static struct resource egpio_resources[] = { |
| 190 | [0] = { | 204 | [0] = { |
| 191 | .start = PXA_CS3_PHYS, | 205 | .start = PXA_CS3_PHYS, |
| 192 | .end = PXA_CS3_PHYS + 0x20, | 206 | .end = PXA_CS3_PHYS + 0x20 - 1, |
| 193 | .flags = IORESOURCE_MEM, | 207 | .flags = IORESOURCE_MEM, |
| 194 | }, | 208 | }, |
| 195 | [1] = { | 209 | [1] = { |
| @@ -420,7 +434,7 @@ static struct gpio_led gpio_leds[] = { | |||
| 420 | }, | 434 | }, |
| 421 | { | 435 | { |
| 422 | .name = "magician::phone_bl", | 436 | .name = "magician::phone_bl", |
| 423 | .default_trigger = "none", | 437 | .default_trigger = "backlight", |
| 424 | .gpio = GPIO103_MAGICIAN_LED_KP, | 438 | .gpio = GPIO103_MAGICIAN_LED_KP, |
| 425 | }, | 439 | }, |
| 426 | }; | 440 | }; |
| @@ -468,8 +482,6 @@ static struct pasic3_led pasic3_leds[] = { | |||
| 468 | }, | 482 | }, |
| 469 | }; | 483 | }; |
| 470 | 484 | ||
| 471 | static struct platform_device pasic3; | ||
| 472 | |||
| 473 | static struct pasic3_leds_machinfo pasic3_leds_info = { | 485 | static struct pasic3_leds_machinfo pasic3_leds_info = { |
| 474 | .num_leds = ARRAY_SIZE(pasic3_leds), | 486 | .num_leds = ARRAY_SIZE(pasic3_leds), |
| 475 | .power_gpio = EGPIO_MAGICIAN_LED_POWER, | 487 | .power_gpio = EGPIO_MAGICIAN_LED_POWER, |
| @@ -511,6 +523,31 @@ static struct platform_device pasic3 = { | |||
| 511 | }; | 523 | }; |
| 512 | 524 | ||
| 513 | /* | 525 | /* |
| 526 | * USB "Transceiver" | ||
| 527 | */ | ||
| 528 | |||
| 529 | static struct resource gpio_vbus_resource = { | ||
| 530 | .flags = IORESOURCE_IRQ, | ||
| 531 | .start = IRQ_MAGICIAN_VBUS, | ||
| 532 | .end = IRQ_MAGICIAN_VBUS, | ||
| 533 | }; | ||
| 534 | |||
| 535 | static struct gpio_vbus_mach_info gpio_vbus_info = { | ||
| 536 | .gpio_pullup = GPIO27_MAGICIAN_USBC_PUEN, | ||
| 537 | .gpio_vbus = EGPIO_MAGICIAN_CABLE_STATE_USB, | ||
| 538 | }; | ||
| 539 | |||
| 540 | static struct platform_device gpio_vbus = { | ||
| 541 | .name = "gpio-vbus", | ||
| 542 | .id = -1, | ||
| 543 | .num_resources = 1, | ||
| 544 | .resource = &gpio_vbus_resource, | ||
| 545 | .dev = { | ||
| 546 | .platform_data = &gpio_vbus_info, | ||
| 547 | }, | ||
| 548 | }; | ||
| 549 | |||
| 550 | /* | ||
| 514 | * External power | 551 | * External power |
| 515 | */ | 552 | */ |
| 516 | 553 | ||
| @@ -586,15 +623,17 @@ static struct pda_power_pdata power_supply_info = { | |||
| 586 | static struct resource power_supply_resources[] = { | 623 | static struct resource power_supply_resources[] = { |
| 587 | [0] = { | 624 | [0] = { |
| 588 | .name = "ac", | 625 | .name = "ac", |
| 589 | .flags = IORESOURCE_IRQ, | 626 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | |
| 590 | .start = IRQ_MAGICIAN_AC, | 627 | IORESOURCE_IRQ_LOWEDGE, |
| 591 | .end = IRQ_MAGICIAN_AC, | 628 | .start = IRQ_MAGICIAN_VBUS, |
| 629 | .end = IRQ_MAGICIAN_VBUS, | ||
| 592 | }, | 630 | }, |
| 593 | [1] = { | 631 | [1] = { |
| 594 | .name = "usb", | 632 | .name = "usb", |
| 595 | .flags = IORESOURCE_IRQ, | 633 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE | |
| 596 | .start = IRQ_MAGICIAN_AC, | 634 | IORESOURCE_IRQ_LOWEDGE, |
| 597 | .end = IRQ_MAGICIAN_AC, | 635 | .start = IRQ_MAGICIAN_VBUS, |
| 636 | .end = IRQ_MAGICIAN_VBUS, | ||
| 598 | }, | 637 | }, |
| 599 | }; | 638 | }; |
| 600 | 639 | ||
| @@ -688,11 +727,9 @@ static void magician_set_vpp(struct map_info *map, int vpp) | |||
| 688 | gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp); | 727 | gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp); |
| 689 | } | 728 | } |
| 690 | 729 | ||
| 691 | #define PXA_CS_SIZE 0x04000000 | ||
| 692 | |||
| 693 | static struct resource strataflash_resource = { | 730 | static struct resource strataflash_resource = { |
| 694 | .start = PXA_CS0_PHYS, | 731 | .start = PXA_CS0_PHYS, |
| 695 | .end = PXA_CS0_PHYS + PXA_CS_SIZE - 1, | 732 | .end = PXA_CS0_PHYS + SZ_64M - 1, |
| 696 | .flags = IORESOURCE_MEM, | 733 | .flags = IORESOURCE_MEM, |
| 697 | }; | 734 | }; |
| 698 | 735 | ||
| @@ -720,6 +757,7 @@ static struct platform_device *devices[] __initdata = { | |||
| 720 | &egpio, | 757 | &egpio, |
| 721 | &backlight, | 758 | &backlight, |
| 722 | &pasic3, | 759 | &pasic3, |
| 760 | &gpio_vbus, | ||
| 723 | &power_supply, | 761 | &power_supply, |
| 724 | &strataflash, | 762 | &strataflash, |
| 725 | &leds_gpio, | 763 | &leds_gpio, |
| @@ -743,6 +781,7 @@ static void __init magician_init(void) | |||
| 743 | gpio_direction_output(GPIO83_MAGICIAN_nIR_EN, 1); | 781 | gpio_direction_output(GPIO83_MAGICIAN_nIR_EN, 1); |
| 744 | pxa_set_ficp_info(&magician_ficp_info); | 782 | pxa_set_ficp_info(&magician_ficp_info); |
| 745 | } | 783 | } |
| 784 | pxa27x_set_i2c_power_info(NULL); | ||
| 746 | pxa_set_i2c_info(NULL); | 785 | pxa_set_i2c_info(NULL); |
| 747 | pxa_set_mci_info(&magician_mci_info); | 786 | pxa_set_mci_info(&magician_mci_info); |
| 748 | pxa_set_ohci_info(&magician_ohci_info); | 787 | pxa_set_ohci_info(&magician_ohci_info); |
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 5f224968043c..a6c8429e975f 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c | |||
| @@ -41,9 +41,8 @@ | |||
| 41 | #include <asm/mach/irq.h> | 41 | #include <asm/mach/irq.h> |
| 42 | #include <asm/mach/flash.h> | 42 | #include <asm/mach/flash.h> |
| 43 | 43 | ||
| 44 | #include <mach/pxa-regs.h> | 44 | #include <mach/pxa27x.h> |
| 45 | #include <mach/pxa2xx-regs.h> | 45 | #include <mach/gpio.h> |
| 46 | #include <mach/mfp-pxa27x.h> | ||
| 47 | #include <mach/mainstone.h> | 46 | #include <mach/mainstone.h> |
| 48 | #include <mach/audio.h> | 47 | #include <mach/audio.h> |
| 49 | #include <mach/pxafb.h> | 48 | #include <mach/pxafb.h> |
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c index 33626de8cbf6..7ffb91d64c39 100644 --- a/arch/arm/mach-pxa/mfp-pxa2xx.c +++ b/arch/arm/mach-pxa/mfp-pxa2xx.c | |||
| @@ -18,15 +18,12 @@ | |||
| 18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
| 19 | #include <linux/sysdev.h> | 19 | #include <linux/sysdev.h> |
| 20 | 20 | ||
| 21 | #include <mach/hardware.h> | 21 | #include <mach/gpio.h> |
| 22 | #include <mach/pxa-regs.h> | ||
| 23 | #include <mach/pxa2xx-regs.h> | 22 | #include <mach/pxa2xx-regs.h> |
| 24 | #include <mach/mfp-pxa2xx.h> | 23 | #include <mach/mfp-pxa2xx.h> |
| 25 | 24 | ||
| 26 | #include "generic.h" | 25 | #include "generic.h" |
| 27 | 26 | ||
| 28 | #define gpio_to_bank(gpio) ((gpio) >> 5) | ||
| 29 | |||
| 30 | #define PGSR(x) __REG2(0x40F00020, (x) << 2) | 27 | #define PGSR(x) __REG2(0x40F00020, (x) << 2) |
| 31 | #define __GAFR(u, x) __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3) | 28 | #define __GAFR(u, x) __REG2((u) ? 0x40E00058 : 0x40E00054, (x) << 3) |
| 32 | #define GAFR_L(x) __GAFR(0, x) | 29 | #define GAFR_L(x) __GAFR(0, x) |
diff --git a/arch/arm/mach-pxa/mfp-pxa3xx.c b/arch/arm/mach-pxa/mfp-pxa3xx.c index eb197a6e8e94..7a270eecd480 100644 --- a/arch/arm/mach-pxa/mfp-pxa3xx.c +++ b/arch/arm/mach-pxa/mfp-pxa3xx.c | |||
| @@ -20,183 +20,9 @@ | |||
| 20 | #include <linux/sysdev.h> | 20 | #include <linux/sysdev.h> |
| 21 | 21 | ||
| 22 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
| 23 | #include <mach/mfp.h> | ||
| 24 | #include <mach/mfp-pxa3xx.h> | 23 | #include <mach/mfp-pxa3xx.h> |
| 25 | #include <mach/pxa3xx-regs.h> | 24 | #include <mach/pxa3xx-regs.h> |
| 26 | 25 | ||
| 27 | /* mfp_spin_lock is used to ensure that MFP register configuration | ||
| 28 | * (most likely a read-modify-write operation) is atomic, and that | ||
| 29 | * mfp_table[] is consistent | ||
| 30 | */ | ||
| 31 | static DEFINE_SPINLOCK(mfp_spin_lock); | ||
| 32 | |||
| 33 | static void __iomem *mfpr_mmio_base = (void __iomem *)&__REG(MFPR_BASE); | ||
| 34 | |||
| 35 | struct pxa3xx_mfp_pin { | ||
| 36 | unsigned long config; /* -1 for not configured */ | ||
| 37 | unsigned long mfpr_off; /* MFPRxx Register offset */ | ||
| 38 | unsigned long mfpr_run; /* Run-Mode Register Value */ | ||
| 39 | unsigned long mfpr_lpm; /* Low Power Mode Register Value */ | ||
| 40 | }; | ||
| 41 | |||
| 42 | static struct pxa3xx_mfp_pin mfp_table[MFP_PIN_MAX]; | ||
| 43 | |||
| 44 | /* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */ | ||
| 45 | static const unsigned long mfpr_lpm[] = { | ||
| 46 | MFPR_LPM_INPUT, | ||
| 47 | MFPR_LPM_DRIVE_LOW, | ||
| 48 | MFPR_LPM_DRIVE_HIGH, | ||
| 49 | MFPR_LPM_PULL_LOW, | ||
| 50 | MFPR_LPM_PULL_HIGH, | ||
| 51 | MFPR_LPM_FLOAT, | ||
| 52 | }; | ||
| 53 | |||
| 54 | /* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */ | ||
| 55 | static const unsigned long mfpr_pull[] = { | ||
| 56 | MFPR_PULL_NONE, | ||
| 57 | MFPR_PULL_LOW, | ||
| 58 | MFPR_PULL_HIGH, | ||
| 59 | MFPR_PULL_BOTH, | ||
| 60 | }; | ||
| 61 | |||
| 62 | /* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */ | ||
| 63 | static const unsigned long mfpr_edge[] = { | ||
| 64 | MFPR_EDGE_NONE, | ||
| 65 | MFPR_EDGE_RISE, | ||
| 66 | MFPR_EDGE_FALL, | ||
| 67 | MFPR_EDGE_BOTH, | ||
| 68 | }; | ||
| 69 | |||
| 70 | #define mfpr_readl(off) \ | ||
| 71 | __raw_readl(mfpr_mmio_base + (off)) | ||
| 72 | |||
| 73 | #define mfpr_writel(off, val) \ | ||
| 74 | __raw_writel(val, mfpr_mmio_base + (off)) | ||
| 75 | |||
| 76 | #define mfp_configured(p) ((p)->config != -1) | ||
| 77 | |||
| 78 | /* | ||
| 79 | * perform a read-back of any MFPR register to make sure the | ||
| 80 | * previous writings are finished | ||
| 81 | */ | ||
| 82 | #define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0) | ||
| 83 | |||
| 84 | static inline void __mfp_config_run(struct pxa3xx_mfp_pin *p) | ||
| 85 | { | ||
| 86 | if (mfp_configured(p)) | ||
| 87 | mfpr_writel(p->mfpr_off, p->mfpr_run); | ||
| 88 | } | ||
| 89 | |||
| 90 | static inline void __mfp_config_lpm(struct pxa3xx_mfp_pin *p) | ||
| 91 | { | ||
| 92 | if (mfp_configured(p)) { | ||
| 93 | unsigned long mfpr_clr = (p->mfpr_run & ~MFPR_EDGE_BOTH) | MFPR_EDGE_CLEAR; | ||
| 94 | if (mfpr_clr != p->mfpr_run) | ||
| 95 | mfpr_writel(p->mfpr_off, mfpr_clr); | ||
| 96 | if (p->mfpr_lpm != mfpr_clr) | ||
| 97 | mfpr_writel(p->mfpr_off, p->mfpr_lpm); | ||
| 98 | } | ||
| 99 | } | ||
| 100 | |||
| 101 | void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num) | ||
| 102 | { | ||
| 103 | unsigned long flags; | ||
| 104 | int i; | ||
| 105 | |||
| 106 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
| 107 | |||
| 108 | for (i = 0; i < num; i++, mfp_cfgs++) { | ||
| 109 | unsigned long tmp, c = *mfp_cfgs; | ||
| 110 | struct pxa3xx_mfp_pin *p; | ||
| 111 | int pin, af, drv, lpm, edge, pull; | ||
| 112 | |||
| 113 | pin = MFP_PIN(c); | ||
| 114 | BUG_ON(pin >= MFP_PIN_MAX); | ||
| 115 | p = &mfp_table[pin]; | ||
| 116 | |||
| 117 | af = MFP_AF(c); | ||
| 118 | drv = MFP_DS(c); | ||
| 119 | lpm = MFP_LPM_STATE(c); | ||
| 120 | edge = MFP_LPM_EDGE(c); | ||
| 121 | pull = MFP_PULL(c); | ||
| 122 | |||
| 123 | /* run-mode pull settings will conflict with MFPR bits of | ||
| 124 | * low power mode state, calculate mfpr_run and mfpr_lpm | ||
| 125 | * individually if pull != MFP_PULL_NONE | ||
| 126 | */ | ||
| 127 | tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv); | ||
| 128 | |||
| 129 | if (likely(pull == MFP_PULL_NONE)) { | ||
| 130 | p->mfpr_run = tmp | mfpr_lpm[lpm] | mfpr_edge[edge]; | ||
| 131 | p->mfpr_lpm = p->mfpr_run; | ||
| 132 | } else { | ||
| 133 | p->mfpr_lpm = tmp | mfpr_lpm[lpm] | mfpr_edge[edge]; | ||
| 134 | p->mfpr_run = tmp | mfpr_pull[pull]; | ||
| 135 | } | ||
| 136 | |||
| 137 | p->config = c; __mfp_config_run(p); | ||
| 138 | } | ||
| 139 | |||
| 140 | mfpr_sync(); | ||
| 141 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
| 142 | } | ||
| 143 | |||
| 144 | unsigned long pxa3xx_mfp_read(int mfp) | ||
| 145 | { | ||
| 146 | unsigned long val, flags; | ||
| 147 | |||
| 148 | BUG_ON(mfp >= MFP_PIN_MAX); | ||
| 149 | |||
| 150 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
| 151 | val = mfpr_readl(mfp_table[mfp].mfpr_off); | ||
| 152 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
| 153 | |||
| 154 | return val; | ||
| 155 | } | ||
| 156 | |||
| 157 | void pxa3xx_mfp_write(int mfp, unsigned long val) | ||
| 158 | { | ||
| 159 | unsigned long flags; | ||
| 160 | |||
| 161 | BUG_ON(mfp >= MFP_PIN_MAX); | ||
| 162 | |||
| 163 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
| 164 | mfpr_writel(mfp_table[mfp].mfpr_off, val); | ||
| 165 | mfpr_sync(); | ||
| 166 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
| 167 | } | ||
| 168 | |||
| 169 | void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *map) | ||
| 170 | { | ||
| 171 | struct pxa3xx_mfp_addr_map *p; | ||
| 172 | unsigned long offset, flags; | ||
| 173 | int i; | ||
| 174 | |||
| 175 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
| 176 | |||
| 177 | for (p = map; p->start != MFP_PIN_INVALID; p++) { | ||
| 178 | offset = p->offset; | ||
| 179 | i = p->start; | ||
| 180 | |||
| 181 | do { | ||
| 182 | mfp_table[i].mfpr_off = offset; | ||
| 183 | mfp_table[i].mfpr_run = 0; | ||
| 184 | mfp_table[i].mfpr_lpm = 0; | ||
| 185 | offset += 4; i++; | ||
| 186 | } while ((i <= p->end) && (p->end != -1)); | ||
| 187 | } | ||
| 188 | |||
| 189 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
| 190 | } | ||
| 191 | |||
| 192 | void __init pxa3xx_init_mfp(void) | ||
| 193 | { | ||
| 194 | int i; | ||
| 195 | |||
| 196 | for (i = 0; i < ARRAY_SIZE(mfp_table); i++) | ||
| 197 | mfp_table[i].config = -1; | ||
| 198 | } | ||
| 199 | |||
| 200 | #ifdef CONFIG_PM | 26 | #ifdef CONFIG_PM |
| 201 | /* | 27 | /* |
| 202 | * Configure the MFPs appropriately for suspend/resume. | 28 | * Configure the MFPs appropriately for suspend/resume. |
| @@ -207,23 +33,13 @@ void __init pxa3xx_init_mfp(void) | |||
| 207 | */ | 33 | */ |
| 208 | static int pxa3xx_mfp_suspend(struct sys_device *d, pm_message_t state) | 34 | static int pxa3xx_mfp_suspend(struct sys_device *d, pm_message_t state) |
| 209 | { | 35 | { |
| 210 | int pin; | 36 | mfp_config_lpm(); |
| 211 | |||
| 212 | for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++) { | ||
| 213 | struct pxa3xx_mfp_pin *p = &mfp_table[pin]; | ||
| 214 | __mfp_config_lpm(p); | ||
| 215 | } | ||
| 216 | return 0; | 37 | return 0; |
| 217 | } | 38 | } |
| 218 | 39 | ||
| 219 | static int pxa3xx_mfp_resume(struct sys_device *d) | 40 | static int pxa3xx_mfp_resume(struct sys_device *d) |
| 220 | { | 41 | { |
| 221 | int pin; | 42 | mfp_config_run(); |
| 222 | |||
| 223 | for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++) { | ||
| 224 | struct pxa3xx_mfp_pin *p = &mfp_table[pin]; | ||
| 225 | __mfp_config_run(p); | ||
| 226 | } | ||
| 227 | 43 | ||
| 228 | /* clear RDH bit when MFP settings are restored | 44 | /* clear RDH bit when MFP settings are restored |
| 229 | * | 45 | * |
| @@ -231,7 +47,6 @@ static int pxa3xx_mfp_resume(struct sys_device *d) | |||
| 231 | * preserve them here in case they will be referenced later | 47 | * preserve them here in case they will be referenced later |
| 232 | */ | 48 | */ |
| 233 | ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); | 49 | ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); |
| 234 | |||
| 235 | return 0; | 50 | return 0; |
| 236 | } | 51 | } |
| 237 | #else | 52 | #else |
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c index 2b427e015b6f..97c93a7a285c 100644 --- a/arch/arm/mach-pxa/mioa701.c +++ b/arch/arm/mach-pxa/mioa701.c | |||
| @@ -36,13 +36,15 @@ | |||
| 36 | #include <linux/power_supply.h> | 36 | #include <linux/power_supply.h> |
| 37 | #include <linux/wm97xx_batt.h> | 37 | #include <linux/wm97xx_batt.h> |
| 38 | #include <linux/mtd/physmap.h> | 38 | #include <linux/mtd/physmap.h> |
| 39 | #include <linux/usb/gpio_vbus.h> | ||
| 39 | 40 | ||
| 40 | #include <asm/mach-types.h> | 41 | #include <asm/mach-types.h> |
| 41 | #include <asm/mach/arch.h> | 42 | #include <asm/mach/arch.h> |
| 42 | #include <mach/mfp-pxa27x.h> | 43 | |
| 44 | #include <mach/pxa27x.h> | ||
| 45 | #include <mach/regs-rtc.h> | ||
| 43 | #include <mach/pxa27x_keypad.h> | 46 | #include <mach/pxa27x_keypad.h> |
| 44 | #include <mach/pxafb.h> | 47 | #include <mach/pxafb.h> |
| 45 | #include <mach/pxa2xx-regs.h> | ||
| 46 | #include <mach/mmc.h> | 48 | #include <mach/mmc.h> |
| 47 | #include <mach/udc.h> | 49 | #include <mach/udc.h> |
| 48 | #include <mach/pxa27x-udc.h> | 50 | #include <mach/pxa27x-udc.h> |
| @@ -411,21 +413,6 @@ static void gsm_exit(void) | |||
| 411 | /* | 413 | /* |
| 412 | * USB UDC | 414 | * USB UDC |
| 413 | */ | 415 | */ |
| 414 | static void udc_power_command(int cmd) | ||
| 415 | { | ||
| 416 | switch (cmd) { | ||
| 417 | case PXA2XX_UDC_CMD_DISCONNECT: | ||
| 418 | gpio_set_value(GPIO22_USB_ENABLE, 0); | ||
| 419 | break; | ||
| 420 | case PXA2XX_UDC_CMD_CONNECT: | ||
| 421 | gpio_set_value(GPIO22_USB_ENABLE, 1); | ||
| 422 | break; | ||
| 423 | default: | ||
| 424 | printk(KERN_INFO "udc_control: unknown command (0x%x)!\n", cmd); | ||
| 425 | break; | ||
| 426 | } | ||
| 427 | } | ||
| 428 | |||
| 429 | static int is_usb_connected(void) | 416 | static int is_usb_connected(void) |
| 430 | { | 417 | { |
| 431 | return !gpio_get_value(GPIO13_nUSB_DETECT); | 418 | return !gpio_get_value(GPIO13_nUSB_DETECT); |
| @@ -433,24 +420,15 @@ static int is_usb_connected(void) | |||
| 433 | 420 | ||
| 434 | static struct pxa2xx_udc_mach_info mioa701_udc_info = { | 421 | static struct pxa2xx_udc_mach_info mioa701_udc_info = { |
| 435 | .udc_is_connected = is_usb_connected, | 422 | .udc_is_connected = is_usb_connected, |
| 436 | .udc_command = udc_power_command, | 423 | .gpio_pullup = GPIO22_USB_ENABLE, |
| 437 | }; | 424 | }; |
| 438 | 425 | ||
| 439 | struct gpio_ress udc_gpios[] = { | 426 | struct gpio_vbus_mach_info gpio_vbus_data = { |
| 440 | MIO_GPIO_OUT(GPIO22_USB_ENABLE, 0, "USB Vbus enable") | 427 | .gpio_vbus = GPIO13_nUSB_DETECT, |
| 428 | .gpio_vbus_inverted = 1, | ||
| 429 | .gpio_pullup = -1, | ||
| 441 | }; | 430 | }; |
| 442 | 431 | ||
| 443 | static int __init udc_init(void) | ||
| 444 | { | ||
| 445 | pxa_set_udc_info(&mioa701_udc_info); | ||
| 446 | return mio_gpio_request(ARRAY_AND_SIZE(udc_gpios)); | ||
| 447 | } | ||
| 448 | |||
| 449 | static void udc_exit(void) | ||
| 450 | { | ||
| 451 | mio_gpio_free(ARRAY_AND_SIZE(udc_gpios)); | ||
| 452 | } | ||
| 453 | |||
| 454 | /* | 432 | /* |
| 455 | * SDIO/MMC Card controller | 433 | * SDIO/MMC Card controller |
| 456 | */ | 434 | */ |
| @@ -789,6 +767,7 @@ MIO_SIMPLE_DEV(pxa2xx_ac97, "pxa2xx-ac97", NULL) | |||
| 789 | MIO_PARENT_DEV(mio_wm9713_codec, "wm9713-codec", &pxa2xx_ac97.dev, NULL) | 767 | MIO_PARENT_DEV(mio_wm9713_codec, "wm9713-codec", &pxa2xx_ac97.dev, NULL) |
| 790 | MIO_SIMPLE_DEV(mioa701_sound, "mioa701-wm9713", NULL) | 768 | MIO_SIMPLE_DEV(mioa701_sound, "mioa701-wm9713", NULL) |
| 791 | MIO_SIMPLE_DEV(mioa701_board, "mioa701-board", NULL) | 769 | MIO_SIMPLE_DEV(mioa701_board, "mioa701-board", NULL) |
| 770 | MIO_SIMPLE_DEV(gpio_vbus, "gpio-vbus", &gpio_vbus_data); | ||
| 792 | 771 | ||
| 793 | static struct platform_device *devices[] __initdata = { | 772 | static struct platform_device *devices[] __initdata = { |
| 794 | &mioa701_gpio_keys, | 773 | &mioa701_gpio_keys, |
| @@ -800,7 +779,8 @@ static struct platform_device *devices[] __initdata = { | |||
| 800 | &mioa701_sound, | 779 | &mioa701_sound, |
| 801 | &power_dev, | 780 | &power_dev, |
| 802 | &strataflash, | 781 | &strataflash, |
| 803 | &mioa701_board | 782 | &gpio_vbus, |
| 783 | &mioa701_board, | ||
| 804 | }; | 784 | }; |
| 805 | 785 | ||
| 806 | static void mioa701_machine_exit(void); | 786 | static void mioa701_machine_exit(void); |
| @@ -808,13 +788,13 @@ static void mioa701_machine_exit(void); | |||
| 808 | static void mioa701_poweroff(void) | 788 | static void mioa701_poweroff(void) |
| 809 | { | 789 | { |
| 810 | mioa701_machine_exit(); | 790 | mioa701_machine_exit(); |
| 811 | arm_machine_restart('s'); | 791 | arm_machine_restart('s', NULL); |
| 812 | } | 792 | } |
| 813 | 793 | ||
| 814 | static void mioa701_restart(char c) | 794 | static void mioa701_restart(char c, const char *cmd) |
| 815 | { | 795 | { |
| 816 | mioa701_machine_exit(); | 796 | mioa701_machine_exit(); |
| 817 | arm_machine_restart('s'); | 797 | arm_machine_restart('s', cmd); |
| 818 | } | 798 | } |
| 819 | 799 | ||
| 820 | struct gpio_ress global_gpios[] = { | 800 | struct gpio_ress global_gpios[] = { |
| @@ -837,7 +817,7 @@ static void __init mioa701_machine_init(void) | |||
| 837 | pxa_set_mci_info(&mioa701_mci_info); | 817 | pxa_set_mci_info(&mioa701_mci_info); |
| 838 | pxa_set_keypad_info(&mioa701_keypad_info); | 818 | pxa_set_keypad_info(&mioa701_keypad_info); |
| 839 | wm97xx_bat_set_pdata(&mioa701_battery_data); | 819 | wm97xx_bat_set_pdata(&mioa701_battery_data); |
| 840 | udc_init(); | 820 | pxa_set_udc_info(&mioa701_udc_info); |
| 841 | pm_power_off = mioa701_poweroff; | 821 | pm_power_off = mioa701_poweroff; |
| 842 | arm_pm_restart = mioa701_restart; | 822 | arm_pm_restart = mioa701_restart; |
| 843 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 823 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| @@ -850,7 +830,6 @@ static void __init mioa701_machine_init(void) | |||
| 850 | 830 | ||
| 851 | static void mioa701_machine_exit(void) | 831 | static void mioa701_machine_exit(void) |
| 852 | { | 832 | { |
| 853 | udc_exit(); | ||
| 854 | bootstrap_exit(); | 833 | bootstrap_exit(); |
| 855 | gsm_exit(); | 834 | gsm_exit(); |
| 856 | } | 835 | } |
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c index 8a73814126b1..a65713ce019e 100644 --- a/arch/arm/mach-pxa/mp900.c +++ b/arch/arm/mach-pxa/mp900.c | |||
| @@ -19,10 +19,10 @@ | |||
| 19 | #include <linux/types.h> | 19 | #include <linux/types.h> |
| 20 | #include <linux/usb/isp116x.h> | 20 | #include <linux/usb/isp116x.h> |
| 21 | 21 | ||
| 22 | #include <mach/hardware.h> | ||
| 23 | #include <mach/pxa-regs.h> | ||
| 24 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
| 25 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
| 24 | |||
| 25 | #include <mach/pxa25x.h> | ||
| 26 | #include "generic.h" | 26 | #include "generic.h" |
| 27 | 27 | ||
| 28 | static void isp116x_pfm_delay(struct device *dev, int delay) | 28 | static void isp116x_pfm_delay(struct device *dev, int delay) |
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c new file mode 100644 index 000000000000..8587477a9bb7 --- /dev/null +++ b/arch/arm/mach-pxa/palmld.c | |||
| @@ -0,0 +1,565 @@ | |||
| 1 | /* | ||
| 2 | * Hardware definitions for Palm LifeDrive | ||
| 3 | * | ||
| 4 | * Author: Marek Vasut <marek.vasut@gmail.com> | ||
| 5 | * | ||
| 6 | * Based on work of: | ||
| 7 | * Alex Osborne <ato@meshy.org> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | * | ||
| 13 | * (find more info at www.hackndev.com) | ||
| 14 | * | ||
| 15 | */ | ||
| 16 | |||
| 17 | #include <linux/platform_device.h> | ||
| 18 | #include <linux/delay.h> | ||
| 19 | #include <linux/irq.h> | ||
| 20 | #include <linux/gpio_keys.h> | ||
| 21 | #include <linux/input.h> | ||
| 22 | #include <linux/pda_power.h> | ||
| 23 | #include <linux/pwm_backlight.h> | ||
| 24 | #include <linux/gpio.h> | ||
| 25 | #include <linux/wm97xx_batt.h> | ||
| 26 | #include <linux/power_supply.h> | ||
| 27 | |||
| 28 | #include <asm/mach-types.h> | ||
| 29 | #include <asm/mach/arch.h> | ||
| 30 | #include <asm/mach/map.h> | ||
| 31 | |||
| 32 | #include <mach/pxa27x.h> | ||
| 33 | #include <mach/audio.h> | ||
| 34 | #include <mach/palmld.h> | ||
| 35 | #include <mach/mmc.h> | ||
| 36 | #include <mach/pxafb.h> | ||
| 37 | #include <mach/irda.h> | ||
| 38 | #include <mach/pxa27x_keypad.h> | ||
| 39 | #include <mach/palmasoc.h> | ||
| 40 | |||
| 41 | #include "generic.h" | ||
| 42 | #include "devices.h" | ||
| 43 | |||
| 44 | /****************************************************************************** | ||
| 45 | * Pin configuration | ||
| 46 | ******************************************************************************/ | ||
| 47 | static unsigned long palmld_pin_config[] __initdata = { | ||
| 48 | /* MMC */ | ||
| 49 | GPIO32_MMC_CLK, | ||
| 50 | GPIO92_MMC_DAT_0, | ||
| 51 | GPIO109_MMC_DAT_1, | ||
| 52 | GPIO110_MMC_DAT_2, | ||
| 53 | GPIO111_MMC_DAT_3, | ||
| 54 | GPIO112_MMC_CMD, | ||
| 55 | GPIO14_GPIO, /* SD detect */ | ||
| 56 | GPIO114_GPIO, /* SD power */ | ||
| 57 | GPIO116_GPIO, /* SD r/o switch */ | ||
| 58 | |||
| 59 | /* AC97 */ | ||
| 60 | GPIO28_AC97_BITCLK, | ||
| 61 | GPIO29_AC97_SDATA_IN_0, | ||
| 62 | GPIO30_AC97_SDATA_OUT, | ||
| 63 | GPIO31_AC97_SYNC, | ||
| 64 | |||
| 65 | /* IrDA */ | ||
| 66 | GPIO108_GPIO, /* ir disable */ | ||
| 67 | GPIO46_FICP_RXD, | ||
| 68 | GPIO47_FICP_TXD, | ||
| 69 | |||
| 70 | /* MATRIX KEYPAD */ | ||
| 71 | GPIO100_KP_MKIN_0, | ||
| 72 | GPIO101_KP_MKIN_1, | ||
| 73 | GPIO102_KP_MKIN_2, | ||
| 74 | GPIO97_KP_MKIN_3, | ||
| 75 | GPIO103_KP_MKOUT_0, | ||
| 76 | GPIO104_KP_MKOUT_1, | ||
| 77 | GPIO105_KP_MKOUT_2, | ||
| 78 | |||
| 79 | /* LCD */ | ||
| 80 | GPIO58_LCD_LDD_0, | ||
| 81 | GPIO59_LCD_LDD_1, | ||
| 82 | GPIO60_LCD_LDD_2, | ||
| 83 | GPIO61_LCD_LDD_3, | ||
| 84 | GPIO62_LCD_LDD_4, | ||
| 85 | GPIO63_LCD_LDD_5, | ||
| 86 | GPIO64_LCD_LDD_6, | ||
| 87 | GPIO65_LCD_LDD_7, | ||
| 88 | GPIO66_LCD_LDD_8, | ||
| 89 | GPIO67_LCD_LDD_9, | ||
| 90 | GPIO68_LCD_LDD_10, | ||
| 91 | GPIO69_LCD_LDD_11, | ||
| 92 | GPIO70_LCD_LDD_12, | ||
| 93 | GPIO71_LCD_LDD_13, | ||
| 94 | GPIO72_LCD_LDD_14, | ||
| 95 | GPIO73_LCD_LDD_15, | ||
| 96 | GPIO74_LCD_FCLK, | ||
| 97 | GPIO75_LCD_LCLK, | ||
| 98 | GPIO76_LCD_PCLK, | ||
| 99 | GPIO77_LCD_BIAS, | ||
| 100 | |||
| 101 | /* PWM */ | ||
| 102 | GPIO16_PWM0_OUT, | ||
| 103 | |||
| 104 | /* GPIO KEYS */ | ||
| 105 | GPIO10_GPIO, /* hotsync button */ | ||
| 106 | GPIO12_GPIO, /* power switch */ | ||
| 107 | GPIO15_GPIO, /* lock switch */ | ||
| 108 | |||
| 109 | /* LEDs */ | ||
| 110 | GPIO52_GPIO, /* green led */ | ||
| 111 | GPIO94_GPIO, /* orange led */ | ||
| 112 | |||
| 113 | /* PCMCIA */ | ||
| 114 | GPIO48_nPOE, | ||
| 115 | GPIO49_nPWE, | ||
| 116 | GPIO50_nPIOR, | ||
| 117 | GPIO51_nPIOW, | ||
| 118 | GPIO85_nPCE_1, | ||
| 119 | GPIO54_nPCE_2, | ||
| 120 | GPIO79_PSKTSEL, | ||
| 121 | GPIO55_nPREG, | ||
| 122 | GPIO56_nPWAIT, | ||
| 123 | GPIO57_nIOIS16, | ||
| 124 | GPIO36_GPIO, /* wifi power */ | ||
| 125 | GPIO38_GPIO, /* wifi ready */ | ||
| 126 | GPIO81_GPIO, /* wifi reset */ | ||
| 127 | |||
| 128 | /* HDD */ | ||
| 129 | GPIO95_GPIO, /* HDD irq */ | ||
| 130 | GPIO115_GPIO, /* HDD power */ | ||
| 131 | |||
| 132 | /* MISC */ | ||
| 133 | GPIO13_GPIO, /* earphone detect */ | ||
| 134 | }; | ||
| 135 | |||
| 136 | /****************************************************************************** | ||
| 137 | * SD/MMC card controller | ||
| 138 | ******************************************************************************/ | ||
| 139 | static int palmld_mci_init(struct device *dev, irq_handler_t palmld_detect_int, | ||
| 140 | void *data) | ||
| 141 | { | ||
| 142 | int err = 0; | ||
| 143 | |||
| 144 | /* Setup an interrupt for detecting card insert/remove events */ | ||
| 145 | err = gpio_request(GPIO_NR_PALMLD_SD_DETECT_N, "SD IRQ"); | ||
| 146 | if (err) | ||
| 147 | goto err; | ||
| 148 | err = gpio_direction_input(GPIO_NR_PALMLD_SD_DETECT_N); | ||
| 149 | if (err) | ||
| 150 | goto err2; | ||
| 151 | err = request_irq(gpio_to_irq(GPIO_NR_PALMLD_SD_DETECT_N), | ||
| 152 | palmld_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM | | ||
| 153 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | ||
| 154 | "SD/MMC card detect", data); | ||
| 155 | if (err) { | ||
| 156 | printk(KERN_ERR "%s: cannot request SD/MMC card detect IRQ\n", | ||
| 157 | __func__); | ||
| 158 | goto err2; | ||
| 159 | } | ||
| 160 | |||
| 161 | err = gpio_request(GPIO_NR_PALMLD_SD_POWER, "SD_POWER"); | ||
| 162 | if (err) | ||
| 163 | goto err3; | ||
| 164 | err = gpio_direction_output(GPIO_NR_PALMLD_SD_POWER, 0); | ||
| 165 | if (err) | ||
| 166 | goto err4; | ||
| 167 | |||
| 168 | err = gpio_request(GPIO_NR_PALMLD_SD_READONLY, "SD_READONLY"); | ||
| 169 | if (err) | ||
| 170 | goto err4; | ||
| 171 | err = gpio_direction_input(GPIO_NR_PALMLD_SD_READONLY); | ||
| 172 | if (err) | ||
| 173 | goto err5; | ||
| 174 | |||
| 175 | printk(KERN_DEBUG "%s: irq registered\n", __func__); | ||
| 176 | |||
| 177 | return 0; | ||
| 178 | |||
| 179 | err5: | ||
| 180 | gpio_free(GPIO_NR_PALMLD_SD_READONLY); | ||
| 181 | err4: | ||
| 182 | gpio_free(GPIO_NR_PALMLD_SD_POWER); | ||
| 183 | err3: | ||
| 184 | free_irq(gpio_to_irq(GPIO_NR_PALMLD_SD_DETECT_N), data); | ||
| 185 | err2: | ||
| 186 | gpio_free(GPIO_NR_PALMLD_SD_DETECT_N); | ||
| 187 | err: | ||
| 188 | return err; | ||
| 189 | } | ||
| 190 | |||
| 191 | static void palmld_mci_exit(struct device *dev, void *data) | ||
| 192 | { | ||
| 193 | gpio_free(GPIO_NR_PALMLD_SD_READONLY); | ||
| 194 | gpio_free(GPIO_NR_PALMLD_SD_POWER); | ||
| 195 | free_irq(gpio_to_irq(GPIO_NR_PALMLD_SD_DETECT_N), data); | ||
| 196 | gpio_free(GPIO_NR_PALMLD_SD_DETECT_N); | ||
| 197 | } | ||
| 198 | |||
| 199 | static void palmld_mci_power(struct device *dev, unsigned int vdd) | ||
| 200 | { | ||
| 201 | struct pxamci_platform_data *p_d = dev->platform_data; | ||
| 202 | gpio_set_value(GPIO_NR_PALMLD_SD_POWER, p_d->ocr_mask & (1 << vdd)); | ||
| 203 | } | ||
| 204 | |||
| 205 | static int palmld_mci_get_ro(struct device *dev) | ||
| 206 | { | ||
| 207 | return gpio_get_value(GPIO_NR_PALMLD_SD_READONLY); | ||
| 208 | } | ||
| 209 | |||
| 210 | static struct pxamci_platform_data palmld_mci_platform_data = { | ||
| 211 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, | ||
| 212 | .setpower = palmld_mci_power, | ||
| 213 | .get_ro = palmld_mci_get_ro, | ||
| 214 | .init = palmld_mci_init, | ||
| 215 | .exit = palmld_mci_exit, | ||
| 216 | }; | ||
| 217 | |||
| 218 | /****************************************************************************** | ||
| 219 | * GPIO keyboard | ||
| 220 | ******************************************************************************/ | ||
| 221 | static unsigned int palmld_matrix_keys[] = { | ||
| 222 | KEY(0, 1, KEY_F2), | ||
| 223 | KEY(0, 2, KEY_UP), | ||
| 224 | |||
| 225 | KEY(1, 0, KEY_F3), | ||
| 226 | KEY(1, 1, KEY_F4), | ||
| 227 | KEY(1, 2, KEY_RIGHT), | ||
| 228 | |||
| 229 | KEY(2, 0, KEY_F1), | ||
| 230 | KEY(2, 1, KEY_F5), | ||
| 231 | KEY(2, 2, KEY_DOWN), | ||
| 232 | |||
| 233 | KEY(3, 0, KEY_F6), | ||
| 234 | KEY(3, 1, KEY_ENTER), | ||
| 235 | KEY(3, 2, KEY_LEFT), | ||
| 236 | }; | ||
| 237 | |||
| 238 | static struct pxa27x_keypad_platform_data palmld_keypad_platform_data = { | ||
| 239 | .matrix_key_rows = 4, | ||
| 240 | .matrix_key_cols = 3, | ||
| 241 | .matrix_key_map = palmld_matrix_keys, | ||
| 242 | .matrix_key_map_size = ARRAY_SIZE(palmld_matrix_keys), | ||
| 243 | |||
| 244 | .debounce_interval = 30, | ||
| 245 | }; | ||
| 246 | |||
| 247 | /****************************************************************************** | ||
| 248 | * GPIO keys | ||
| 249 | ******************************************************************************/ | ||
| 250 | static struct gpio_keys_button palmld_pxa_buttons[] = { | ||
| 251 | {KEY_F8, GPIO_NR_PALMLD_HOTSYNC_BUTTON_N, 1, "HotSync Button" }, | ||
| 252 | {KEY_F9, GPIO_NR_PALMLD_LOCK_SWITCH, 0, "Lock Switch" }, | ||
| 253 | {KEY_POWER, GPIO_NR_PALMLD_POWER_SWITCH, 0, "Power Switch" }, | ||
| 254 | }; | ||
| 255 | |||
| 256 | static struct gpio_keys_platform_data palmld_pxa_keys_data = { | ||
| 257 | .buttons = palmld_pxa_buttons, | ||
| 258 | .nbuttons = ARRAY_SIZE(palmld_pxa_buttons), | ||
| 259 | }; | ||
| 260 | |||
| 261 | static struct platform_device palmld_pxa_keys = { | ||
| 262 | .name = "gpio-keys", | ||
| 263 | .id = -1, | ||
| 264 | .dev = { | ||
| 265 | .platform_data = &palmld_pxa_keys_data, | ||
| 266 | }, | ||
| 267 | }; | ||
| 268 | |||
| 269 | /****************************************************************************** | ||
| 270 | * Backlight | ||
| 271 | ******************************************************************************/ | ||
| 272 | static int palmld_backlight_init(struct device *dev) | ||
| 273 | { | ||
| 274 | int ret; | ||
| 275 | |||
| 276 | ret = gpio_request(GPIO_NR_PALMLD_BL_POWER, "BL POWER"); | ||
| 277 | if (ret) | ||
| 278 | goto err; | ||
| 279 | ret = gpio_direction_output(GPIO_NR_PALMLD_BL_POWER, 0); | ||
| 280 | if (ret) | ||
| 281 | goto err2; | ||
| 282 | ret = gpio_request(GPIO_NR_PALMLD_LCD_POWER, "LCD POWER"); | ||
| 283 | if (ret) | ||
| 284 | goto err2; | ||
| 285 | ret = gpio_direction_output(GPIO_NR_PALMLD_LCD_POWER, 0); | ||
| 286 | if (ret) | ||
| 287 | goto err3; | ||
| 288 | |||
| 289 | return 0; | ||
| 290 | err3: | ||
| 291 | gpio_free(GPIO_NR_PALMLD_LCD_POWER); | ||
| 292 | err2: | ||
| 293 | gpio_free(GPIO_NR_PALMLD_BL_POWER); | ||
| 294 | err: | ||
| 295 | return ret; | ||
| 296 | } | ||
| 297 | |||
| 298 | static int palmld_backlight_notify(int brightness) | ||
| 299 | { | ||
| 300 | gpio_set_value(GPIO_NR_PALMLD_BL_POWER, brightness); | ||
| 301 | gpio_set_value(GPIO_NR_PALMLD_LCD_POWER, brightness); | ||
| 302 | return brightness; | ||
| 303 | } | ||
| 304 | |||
| 305 | static void palmld_backlight_exit(struct device *dev) | ||
| 306 | { | ||
| 307 | gpio_free(GPIO_NR_PALMLD_BL_POWER); | ||
| 308 | gpio_free(GPIO_NR_PALMLD_LCD_POWER); | ||
| 309 | } | ||
| 310 | |||
| 311 | static struct platform_pwm_backlight_data palmld_backlight_data = { | ||
| 312 | .pwm_id = 0, | ||
| 313 | .max_brightness = PALMLD_MAX_INTENSITY, | ||
| 314 | .dft_brightness = PALMLD_MAX_INTENSITY, | ||
| 315 | .pwm_period_ns = PALMLD_PERIOD_NS, | ||
| 316 | .init = palmld_backlight_init, | ||
| 317 | .notify = palmld_backlight_notify, | ||
| 318 | .exit = palmld_backlight_exit, | ||
| 319 | }; | ||
| 320 | |||
| 321 | static struct platform_device palmld_backlight = { | ||
| 322 | .name = "pwm-backlight", | ||
| 323 | .dev = { | ||
| 324 | .parent = &pxa27x_device_pwm0.dev, | ||
| 325 | .platform_data = &palmld_backlight_data, | ||
| 326 | }, | ||
| 327 | }; | ||
| 328 | |||
| 329 | /****************************************************************************** | ||
| 330 | * IrDA | ||
| 331 | ******************************************************************************/ | ||
| 332 | static int palmld_irda_startup(struct device *dev) | ||
| 333 | { | ||
| 334 | int err; | ||
| 335 | err = gpio_request(GPIO_NR_PALMLD_IR_DISABLE, "IR DISABLE"); | ||
| 336 | if (err) | ||
| 337 | goto err; | ||
| 338 | err = gpio_direction_output(GPIO_NR_PALMLD_IR_DISABLE, 1); | ||
| 339 | if (err) | ||
| 340 | gpio_free(GPIO_NR_PALMLD_IR_DISABLE); | ||
| 341 | err: | ||
| 342 | return err; | ||
| 343 | } | ||
| 344 | |||
| 345 | static void palmld_irda_shutdown(struct device *dev) | ||
| 346 | { | ||
| 347 | gpio_free(GPIO_NR_PALMLD_IR_DISABLE); | ||
| 348 | } | ||
| 349 | |||
| 350 | static void palmld_irda_transceiver_mode(struct device *dev, int mode) | ||
| 351 | { | ||
| 352 | gpio_set_value(GPIO_NR_PALMLD_IR_DISABLE, mode & IR_OFF); | ||
| 353 | pxa2xx_transceiver_mode(dev, mode); | ||
| 354 | } | ||
| 355 | |||
| 356 | static struct pxaficp_platform_data palmld_ficp_platform_data = { | ||
| 357 | .startup = palmld_irda_startup, | ||
| 358 | .shutdown = palmld_irda_shutdown, | ||
| 359 | .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF, | ||
| 360 | .transceiver_mode = palmld_irda_transceiver_mode, | ||
| 361 | }; | ||
| 362 | |||
| 363 | /****************************************************************************** | ||
| 364 | * LEDs | ||
| 365 | ******************************************************************************/ | ||
| 366 | struct gpio_led gpio_leds[] = { | ||
| 367 | { | ||
| 368 | .name = "palmld:green:led", | ||
| 369 | .default_trigger = "none", | ||
| 370 | .gpio = GPIO_NR_PALMLD_LED_GREEN, | ||
| 371 | }, { | ||
| 372 | .name = "palmld:amber:led", | ||
| 373 | .default_trigger = "none", | ||
| 374 | .gpio = GPIO_NR_PALMLD_LED_AMBER, | ||
| 375 | }, | ||
| 376 | }; | ||
| 377 | |||
| 378 | static struct gpio_led_platform_data gpio_led_info = { | ||
| 379 | .leds = gpio_leds, | ||
| 380 | .num_leds = ARRAY_SIZE(gpio_leds), | ||
| 381 | }; | ||
| 382 | |||
| 383 | static struct platform_device palmld_leds = { | ||
| 384 | .name = "leds-gpio", | ||
| 385 | .id = -1, | ||
| 386 | .dev = { | ||
| 387 | .platform_data = &gpio_led_info, | ||
| 388 | } | ||
| 389 | }; | ||
| 390 | |||
| 391 | /****************************************************************************** | ||
| 392 | * Power supply | ||
| 393 | ******************************************************************************/ | ||
| 394 | static int power_supply_init(struct device *dev) | ||
| 395 | { | ||
| 396 | int ret; | ||
| 397 | |||
| 398 | ret = gpio_request(GPIO_NR_PALMLD_POWER_DETECT, "CABLE_STATE_AC"); | ||
| 399 | if (ret) | ||
| 400 | goto err1; | ||
| 401 | ret = gpio_direction_input(GPIO_NR_PALMLD_POWER_DETECT); | ||
| 402 | if (ret) | ||
| 403 | goto err2; | ||
| 404 | |||
| 405 | ret = gpio_request(GPIO_NR_PALMLD_USB_DETECT_N, "CABLE_STATE_USB"); | ||
| 406 | if (ret) | ||
| 407 | goto err2; | ||
| 408 | ret = gpio_direction_input(GPIO_NR_PALMLD_USB_DETECT_N); | ||
| 409 | if (ret) | ||
| 410 | goto err3; | ||
| 411 | |||
| 412 | return 0; | ||
| 413 | |||
| 414 | err3: | ||
| 415 | gpio_free(GPIO_NR_PALMLD_USB_DETECT_N); | ||
| 416 | err2: | ||
| 417 | gpio_free(GPIO_NR_PALMLD_POWER_DETECT); | ||
| 418 | err1: | ||
| 419 | return ret; | ||
| 420 | } | ||
| 421 | |||
| 422 | static int palmld_is_ac_online(void) | ||
| 423 | { | ||
| 424 | return gpio_get_value(GPIO_NR_PALMLD_POWER_DETECT); | ||
| 425 | } | ||
| 426 | |||
| 427 | static int palmld_is_usb_online(void) | ||
| 428 | { | ||
| 429 | return !gpio_get_value(GPIO_NR_PALMLD_USB_DETECT_N); | ||
| 430 | } | ||
| 431 | |||
| 432 | static void power_supply_exit(struct device *dev) | ||
| 433 | { | ||
| 434 | gpio_free(GPIO_NR_PALMLD_USB_DETECT_N); | ||
| 435 | gpio_free(GPIO_NR_PALMLD_POWER_DETECT); | ||
| 436 | } | ||
| 437 | |||
| 438 | static char *palmld_supplicants[] = { | ||
| 439 | "main-battery", | ||
| 440 | }; | ||
| 441 | |||
| 442 | static struct pda_power_pdata power_supply_info = { | ||
| 443 | .init = power_supply_init, | ||
| 444 | .is_ac_online = palmld_is_ac_online, | ||
| 445 | .is_usb_online = palmld_is_usb_online, | ||
| 446 | .exit = power_supply_exit, | ||
| 447 | .supplied_to = palmld_supplicants, | ||
| 448 | .num_supplicants = ARRAY_SIZE(palmld_supplicants), | ||
| 449 | }; | ||
| 450 | |||
| 451 | static struct platform_device power_supply = { | ||
| 452 | .name = "pda-power", | ||
| 453 | .id = -1, | ||
| 454 | .dev = { | ||
| 455 | .platform_data = &power_supply_info, | ||
| 456 | }, | ||
| 457 | }; | ||
| 458 | |||
| 459 | /****************************************************************************** | ||
| 460 | * WM97xx battery | ||
| 461 | ******************************************************************************/ | ||
| 462 | static struct wm97xx_batt_info wm97xx_batt_pdata = { | ||
| 463 | .batt_aux = WM97XX_AUX_ID3, | ||
| 464 | .temp_aux = WM97XX_AUX_ID2, | ||
| 465 | .charge_gpio = -1, | ||
| 466 | .max_voltage = PALMLD_BAT_MAX_VOLTAGE, | ||
| 467 | .min_voltage = PALMLD_BAT_MIN_VOLTAGE, | ||
| 468 | .batt_mult = 1000, | ||
| 469 | .batt_div = 414, | ||
| 470 | .temp_mult = 1, | ||
| 471 | .temp_div = 1, | ||
| 472 | .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO, | ||
| 473 | .batt_name = "main-batt", | ||
| 474 | }; | ||
| 475 | |||
| 476 | /****************************************************************************** | ||
| 477 | * aSoC audio | ||
| 478 | ******************************************************************************/ | ||
| 479 | static struct palm27x_asoc_info palm27x_asoc_pdata = { | ||
| 480 | .jack_gpio = GPIO_NR_PALMLD_EARPHONE_DETECT, | ||
| 481 | }; | ||
| 482 | |||
| 483 | /****************************************************************************** | ||
| 484 | * Framebuffer | ||
| 485 | ******************************************************************************/ | ||
| 486 | static struct pxafb_mode_info palmld_lcd_modes[] = { | ||
| 487 | { | ||
| 488 | .pixclock = 57692, | ||
| 489 | .xres = 320, | ||
| 490 | .yres = 480, | ||
| 491 | .bpp = 16, | ||
| 492 | |||
| 493 | .left_margin = 32, | ||
| 494 | .right_margin = 1, | ||
| 495 | .upper_margin = 7, | ||
| 496 | .lower_margin = 1, | ||
| 497 | |||
| 498 | .hsync_len = 4, | ||
| 499 | .vsync_len = 1, | ||
| 500 | }, | ||
| 501 | }; | ||
| 502 | |||
| 503 | static struct pxafb_mach_info palmld_lcd_screen = { | ||
| 504 | .modes = palmld_lcd_modes, | ||
| 505 | .num_modes = ARRAY_SIZE(palmld_lcd_modes), | ||
| 506 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, | ||
| 507 | }; | ||
| 508 | |||
| 509 | /****************************************************************************** | ||
| 510 | * Machine init | ||
| 511 | ******************************************************************************/ | ||
| 512 | static struct platform_device *devices[] __initdata = { | ||
| 513 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | ||
| 514 | &palmld_pxa_keys, | ||
| 515 | #endif | ||
| 516 | &palmld_backlight, | ||
| 517 | &palmld_leds, | ||
| 518 | &power_supply, | ||
| 519 | }; | ||
| 520 | |||
| 521 | static struct map_desc palmld_io_desc[] __initdata = { | ||
| 522 | { | ||
| 523 | .virtual = PALMLD_IDE_VIRT, | ||
| 524 | .pfn = __phys_to_pfn(PALMLD_IDE_PHYS), | ||
| 525 | .length = PALMLD_IDE_SIZE, | ||
| 526 | .type = MT_DEVICE | ||
| 527 | }, | ||
| 528 | { | ||
| 529 | .virtual = PALMLD_USB_VIRT, | ||
| 530 | .pfn = __phys_to_pfn(PALMLD_USB_PHYS), | ||
| 531 | .length = PALMLD_USB_SIZE, | ||
| 532 | .type = MT_DEVICE | ||
| 533 | }, | ||
| 534 | }; | ||
| 535 | |||
| 536 | static void __init palmld_map_io(void) | ||
| 537 | { | ||
| 538 | pxa_map_io(); | ||
| 539 | iotable_init(palmld_io_desc, ARRAY_SIZE(palmld_io_desc)); | ||
| 540 | } | ||
| 541 | |||
| 542 | static void __init palmld_init(void) | ||
| 543 | { | ||
| 544 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmld_pin_config)); | ||
| 545 | |||
| 546 | set_pxa_fb_info(&palmld_lcd_screen); | ||
| 547 | pxa_set_mci_info(&palmld_mci_platform_data); | ||
| 548 | pxa_set_ac97_info(NULL); | ||
| 549 | pxa_set_ficp_info(&palmld_ficp_platform_data); | ||
| 550 | pxa_set_keypad_info(&palmld_keypad_platform_data); | ||
| 551 | wm97xx_bat_set_pdata(&wm97xx_batt_pdata); | ||
| 552 | palm27x_asoc_set_pdata(&palm27x_asoc_pdata); | ||
| 553 | |||
| 554 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 555 | } | ||
| 556 | |||
| 557 | MACHINE_START(PALMLD, "Palm LifeDrive") | ||
| 558 | .phys_io = PALMLD_PHYS_IO_START, | ||
| 559 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 560 | .boot_params = 0xa0000100, | ||
| 561 | .map_io = palmld_map_io, | ||
| 562 | .init_irq = pxa27x_init_irq, | ||
| 563 | .timer = &pxa_timer, | ||
| 564 | .init_machine = palmld_init | ||
| 565 | MACHINE_END | ||
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c new file mode 100644 index 000000000000..9521c7b33492 --- /dev/null +++ b/arch/arm/mach-pxa/palmt5.c | |||
| @@ -0,0 +1,496 @@ | |||
| 1 | /* | ||
| 2 | * Hardware definitions for Palm Tungsten|T5 | ||
| 3 | * | ||
| 4 | * Author: Marek Vasut <marek.vasut@gmail.com> | ||
| 5 | * | ||
| 6 | * Based on work of: | ||
| 7 | * Ales Snuparek <snuparek@atlas.cz> | ||
| 8 | * Justin Kendrick <twilightsentry@gmail.com> | ||
| 9 | * RichardT5 <richard_t5@users.sourceforge.net> | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | * | ||
| 15 | * (find more info at www.hackndev.com) | ||
| 16 | * | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/platform_device.h> | ||
| 20 | #include <linux/delay.h> | ||
| 21 | #include <linux/irq.h> | ||
| 22 | #include <linux/gpio_keys.h> | ||
| 23 | #include <linux/input.h> | ||
| 24 | #include <linux/pda_power.h> | ||
| 25 | #include <linux/pwm_backlight.h> | ||
| 26 | #include <linux/gpio.h> | ||
| 27 | #include <linux/wm97xx_batt.h> | ||
| 28 | #include <linux/power_supply.h> | ||
| 29 | |||
| 30 | #include <asm/mach-types.h> | ||
| 31 | #include <asm/mach/arch.h> | ||
| 32 | #include <asm/mach/map.h> | ||
| 33 | |||
| 34 | #include <mach/pxa27x.h> | ||
| 35 | #include <mach/audio.h> | ||
| 36 | #include <mach/palmt5.h> | ||
| 37 | #include <mach/mmc.h> | ||
| 38 | #include <mach/pxafb.h> | ||
| 39 | #include <mach/irda.h> | ||
| 40 | #include <mach/pxa27x_keypad.h> | ||
| 41 | #include <mach/udc.h> | ||
| 42 | #include <mach/palmasoc.h> | ||
| 43 | |||
| 44 | #include "generic.h" | ||
| 45 | #include "devices.h" | ||
| 46 | |||
| 47 | /****************************************************************************** | ||
| 48 | * Pin configuration | ||
| 49 | ******************************************************************************/ | ||
| 50 | static unsigned long palmt5_pin_config[] __initdata = { | ||
| 51 | /* MMC */ | ||
| 52 | GPIO32_MMC_CLK, | ||
| 53 | GPIO92_MMC_DAT_0, | ||
| 54 | GPIO109_MMC_DAT_1, | ||
| 55 | GPIO110_MMC_DAT_2, | ||
| 56 | GPIO111_MMC_DAT_3, | ||
| 57 | GPIO112_MMC_CMD, | ||
| 58 | GPIO14_GPIO, /* SD detect */ | ||
| 59 | GPIO114_GPIO, /* SD power */ | ||
| 60 | GPIO115_GPIO, /* SD r/o switch */ | ||
| 61 | |||
| 62 | /* AC97 */ | ||
| 63 | GPIO28_AC97_BITCLK, | ||
| 64 | GPIO29_AC97_SDATA_IN_0, | ||
| 65 | GPIO30_AC97_SDATA_OUT, | ||
| 66 | GPIO31_AC97_SYNC, | ||
| 67 | |||
| 68 | /* IrDA */ | ||
| 69 | GPIO40_GPIO, /* ir disable */ | ||
| 70 | GPIO46_FICP_RXD, | ||
| 71 | GPIO47_FICP_TXD, | ||
| 72 | |||
| 73 | /* USB */ | ||
| 74 | GPIO15_GPIO, /* usb detect */ | ||
| 75 | GPIO95_GPIO, /* usb power */ | ||
| 76 | |||
| 77 | /* MATRIX KEYPAD */ | ||
| 78 | GPIO100_KP_MKIN_0, | ||
| 79 | GPIO101_KP_MKIN_1, | ||
| 80 | GPIO102_KP_MKIN_2, | ||
| 81 | GPIO97_KP_MKIN_3, | ||
| 82 | GPIO103_KP_MKOUT_0, | ||
| 83 | GPIO104_KP_MKOUT_1, | ||
| 84 | GPIO105_KP_MKOUT_2, | ||
| 85 | |||
| 86 | /* LCD */ | ||
| 87 | GPIO58_LCD_LDD_0, | ||
| 88 | GPIO59_LCD_LDD_1, | ||
| 89 | GPIO60_LCD_LDD_2, | ||
| 90 | GPIO61_LCD_LDD_3, | ||
| 91 | GPIO62_LCD_LDD_4, | ||
| 92 | GPIO63_LCD_LDD_5, | ||
| 93 | GPIO64_LCD_LDD_6, | ||
| 94 | GPIO65_LCD_LDD_7, | ||
| 95 | GPIO66_LCD_LDD_8, | ||
| 96 | GPIO67_LCD_LDD_9, | ||
| 97 | GPIO68_LCD_LDD_10, | ||
| 98 | GPIO69_LCD_LDD_11, | ||
| 99 | GPIO70_LCD_LDD_12, | ||
| 100 | GPIO71_LCD_LDD_13, | ||
| 101 | GPIO72_LCD_LDD_14, | ||
| 102 | GPIO73_LCD_LDD_15, | ||
| 103 | GPIO74_LCD_FCLK, | ||
| 104 | GPIO75_LCD_LCLK, | ||
| 105 | GPIO76_LCD_PCLK, | ||
| 106 | GPIO77_LCD_BIAS, | ||
| 107 | |||
| 108 | /* PWM */ | ||
| 109 | GPIO16_PWM0_OUT, | ||
| 110 | |||
| 111 | /* MISC */ | ||
| 112 | GPIO10_GPIO, /* hotsync button */ | ||
| 113 | GPIO90_GPIO, /* power detect */ | ||
| 114 | GPIO107_GPIO, /* earphone detect */ | ||
| 115 | }; | ||
| 116 | |||
| 117 | /****************************************************************************** | ||
| 118 | * SD/MMC card controller | ||
| 119 | ******************************************************************************/ | ||
| 120 | static int palmt5_mci_init(struct device *dev, irq_handler_t palmt5_detect_int, | ||
| 121 | void *data) | ||
| 122 | { | ||
| 123 | int err = 0; | ||
| 124 | |||
| 125 | /* Setup an interrupt for detecting card insert/remove events */ | ||
| 126 | err = gpio_request(GPIO_NR_PALMT5_SD_DETECT_N, "SD IRQ"); | ||
| 127 | if (err) | ||
| 128 | goto err; | ||
| 129 | err = gpio_direction_input(GPIO_NR_PALMT5_SD_DETECT_N); | ||
| 130 | if (err) | ||
| 131 | goto err2; | ||
| 132 | err = request_irq(gpio_to_irq(GPIO_NR_PALMT5_SD_DETECT_N), | ||
| 133 | palmt5_detect_int, IRQF_DISABLED | IRQF_SAMPLE_RANDOM | | ||
| 134 | IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, | ||
| 135 | "SD/MMC card detect", data); | ||
| 136 | if (err) { | ||
| 137 | printk(KERN_ERR "%s: cannot request SD/MMC card detect IRQ\n", | ||
| 138 | __func__); | ||
| 139 | goto err2; | ||
| 140 | } | ||
| 141 | |||
| 142 | err = gpio_request(GPIO_NR_PALMT5_SD_POWER, "SD_POWER"); | ||
| 143 | if (err) | ||
| 144 | goto err3; | ||
| 145 | err = gpio_direction_output(GPIO_NR_PALMT5_SD_POWER, 0); | ||
| 146 | if (err) | ||
| 147 | goto err4; | ||
| 148 | |||
| 149 | err = gpio_request(GPIO_NR_PALMT5_SD_READONLY, "SD_READONLY"); | ||
| 150 | if (err) | ||
| 151 | goto err4; | ||
| 152 | err = gpio_direction_input(GPIO_NR_PALMT5_SD_READONLY); | ||
| 153 | if (err) | ||
| 154 | goto err5; | ||
| 155 | |||
| 156 | printk(KERN_DEBUG "%s: irq registered\n", __func__); | ||
| 157 | |||
| 158 | return 0; | ||
| 159 | |||
| 160 | err5: | ||
| 161 | gpio_free(GPIO_NR_PALMT5_SD_READONLY); | ||
| 162 | err4: | ||
| 163 | gpio_free(GPIO_NR_PALMT5_SD_POWER); | ||
| 164 | err3: | ||
| 165 | free_irq(gpio_to_irq(GPIO_NR_PALMT5_SD_DETECT_N), data); | ||
| 166 | err2: | ||
| 167 | gpio_free(GPIO_NR_PALMT5_SD_DETECT_N); | ||
| 168 | err: | ||
| 169 | return err; | ||
| 170 | } | ||
| 171 | |||
| 172 | static void palmt5_mci_exit(struct device *dev, void *data) | ||
| 173 | { | ||
| 174 | gpio_free(GPIO_NR_PALMT5_SD_READONLY); | ||
| 175 | gpio_free(GPIO_NR_PALMT5_SD_POWER); | ||
| 176 | free_irq(IRQ_GPIO_PALMT5_SD_DETECT_N, data); | ||
| 177 | gpio_free(GPIO_NR_PALMT5_SD_DETECT_N); | ||
| 178 | } | ||
| 179 | |||
| 180 | static void palmt5_mci_power(struct device *dev, unsigned int vdd) | ||
| 181 | { | ||
| 182 | struct pxamci_platform_data *p_d = dev->platform_data; | ||
| 183 | gpio_set_value(GPIO_NR_PALMT5_SD_POWER, p_d->ocr_mask & (1 << vdd)); | ||
| 184 | } | ||
| 185 | |||
| 186 | static int palmt5_mci_get_ro(struct device *dev) | ||
| 187 | { | ||
| 188 | return gpio_get_value(GPIO_NR_PALMT5_SD_READONLY); | ||
| 189 | } | ||
| 190 | |||
| 191 | static struct pxamci_platform_data palmt5_mci_platform_data = { | ||
| 192 | .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, | ||
| 193 | .setpower = palmt5_mci_power, | ||
| 194 | .get_ro = palmt5_mci_get_ro, | ||
| 195 | .init = palmt5_mci_init, | ||
| 196 | .exit = palmt5_mci_exit, | ||
| 197 | }; | ||
| 198 | |||
| 199 | /****************************************************************************** | ||
| 200 | * GPIO keyboard | ||
| 201 | ******************************************************************************/ | ||
| 202 | static unsigned int palmt5_matrix_keys[] = { | ||
| 203 | KEY(0, 0, KEY_POWER), | ||
| 204 | KEY(0, 1, KEY_F1), | ||
| 205 | KEY(0, 2, KEY_ENTER), | ||
| 206 | |||
| 207 | KEY(1, 0, KEY_F2), | ||
| 208 | KEY(1, 1, KEY_F3), | ||
| 209 | KEY(1, 2, KEY_F4), | ||
| 210 | |||
| 211 | KEY(2, 0, KEY_UP), | ||
| 212 | KEY(2, 2, KEY_DOWN), | ||
| 213 | |||
| 214 | KEY(3, 0, KEY_RIGHT), | ||
| 215 | KEY(3, 2, KEY_LEFT), | ||
| 216 | }; | ||
| 217 | |||
| 218 | static struct pxa27x_keypad_platform_data palmt5_keypad_platform_data = { | ||
| 219 | .matrix_key_rows = 4, | ||
| 220 | .matrix_key_cols = 3, | ||
| 221 | .matrix_key_map = palmt5_matrix_keys, | ||
| 222 | .matrix_key_map_size = ARRAY_SIZE(palmt5_matrix_keys), | ||
| 223 | |||
| 224 | .debounce_interval = 30, | ||
| 225 | }; | ||
| 226 | |||
| 227 | /****************************************************************************** | ||
| 228 | * GPIO keys | ||
| 229 | ******************************************************************************/ | ||
| 230 | static struct gpio_keys_button palmt5_pxa_buttons[] = { | ||
| 231 | {KEY_F8, GPIO_NR_PALMT5_HOTSYNC_BUTTON_N, 1, "HotSync Button" }, | ||
| 232 | }; | ||
| 233 | |||
| 234 | static struct gpio_keys_platform_data palmt5_pxa_keys_data = { | ||
| 235 | .buttons = palmt5_pxa_buttons, | ||
| 236 | .nbuttons = ARRAY_SIZE(palmt5_pxa_buttons), | ||
| 237 | }; | ||
| 238 | |||
| 239 | static struct platform_device palmt5_pxa_keys = { | ||
| 240 | .name = "gpio-keys", | ||
| 241 | .id = -1, | ||
| 242 | .dev = { | ||
| 243 | .platform_data = &palmt5_pxa_keys_data, | ||
| 244 | }, | ||
| 245 | }; | ||
| 246 | |||
| 247 | /****************************************************************************** | ||
| 248 | * Backlight | ||
| 249 | ******************************************************************************/ | ||
| 250 | static int palmt5_backlight_init(struct device *dev) | ||
| 251 | { | ||
| 252 | int ret; | ||
| 253 | |||
| 254 | ret = gpio_request(GPIO_NR_PALMT5_BL_POWER, "BL POWER"); | ||
| 255 | if (ret) | ||
| 256 | goto err; | ||
| 257 | ret = gpio_direction_output(GPIO_NR_PALMT5_BL_POWER, 0); | ||
| 258 | if (ret) | ||
| 259 | goto err2; | ||
| 260 | ret = gpio_request(GPIO_NR_PALMT5_LCD_POWER, "LCD POWER"); | ||
| 261 | if (ret) | ||
| 262 | goto err2; | ||
| 263 | ret = gpio_direction_output(GPIO_NR_PALMT5_LCD_POWER, 0); | ||
| 264 | if (ret) | ||
| 265 | goto err3; | ||
| 266 | |||
| 267 | return 0; | ||
| 268 | err3: | ||
| 269 | gpio_free(GPIO_NR_PALMT5_LCD_POWER); | ||
| 270 | err2: | ||
| 271 | gpio_free(GPIO_NR_PALMT5_BL_POWER); | ||
| 272 | err: | ||
| 273 | return ret; | ||
| 274 | } | ||
| 275 | |||
| 276 | static int palmt5_backlight_notify(int brightness) | ||
| 277 | { | ||
| 278 | gpio_set_value(GPIO_NR_PALMT5_BL_POWER, brightness); | ||
| 279 | gpio_set_value(GPIO_NR_PALMT5_LCD_POWER, brightness); | ||
| 280 | return brightness; | ||
| 281 | } | ||
| 282 | |||
| 283 | static void palmt5_backlight_exit(struct device *dev) | ||
| 284 | { | ||
| 285 | gpio_free(GPIO_NR_PALMT5_BL_POWER); | ||
| 286 | gpio_free(GPIO_NR_PALMT5_LCD_POWER); | ||
| 287 | } | ||
| 288 | |||
| 289 | static struct platform_pwm_backlight_data palmt5_backlight_data = { | ||
| 290 | .pwm_id = 0, | ||
| 291 | .max_brightness = PALMT5_MAX_INTENSITY, | ||
| 292 | .dft_brightness = PALMT5_MAX_INTENSITY, | ||
| 293 | .pwm_period_ns = PALMT5_PERIOD_NS, | ||
| 294 | .init = palmt5_backlight_init, | ||
| 295 | .notify = palmt5_backlight_notify, | ||
| 296 | .exit = palmt5_backlight_exit, | ||
| 297 | }; | ||
| 298 | |||
| 299 | static struct platform_device palmt5_backlight = { | ||
| 300 | .name = "pwm-backlight", | ||
| 301 | .dev = { | ||
| 302 | .parent = &pxa27x_device_pwm0.dev, | ||
| 303 | .platform_data = &palmt5_backlight_data, | ||
| 304 | }, | ||
| 305 | }; | ||
| 306 | |||
| 307 | /****************************************************************************** | ||
| 308 | * IrDA | ||
| 309 | ******************************************************************************/ | ||
| 310 | static int palmt5_irda_startup(struct device *dev) | ||
| 311 | { | ||
| 312 | int err; | ||
| 313 | err = gpio_request(GPIO_NR_PALMT5_IR_DISABLE, "IR DISABLE"); | ||
| 314 | if (err) | ||
| 315 | goto err; | ||
| 316 | err = gpio_direction_output(GPIO_NR_PALMT5_IR_DISABLE, 1); | ||
| 317 | if (err) | ||
| 318 | gpio_free(GPIO_NR_PALMT5_IR_DISABLE); | ||
| 319 | err: | ||
| 320 | return err; | ||
| 321 | } | ||
| 322 | |||
| 323 | static void palmt5_irda_shutdown(struct device *dev) | ||
| 324 | { | ||
| 325 | gpio_free(GPIO_NR_PALMT5_IR_DISABLE); | ||
| 326 | } | ||
| 327 | |||
| 328 | static void palmt5_irda_transceiver_mode(struct device *dev, int mode) | ||
| 329 | { | ||
| 330 | gpio_set_value(GPIO_NR_PALMT5_IR_DISABLE, mode & IR_OFF); | ||
| 331 | pxa2xx_transceiver_mode(dev, mode); | ||
| 332 | } | ||
| 333 | |||
| 334 | static struct pxaficp_platform_data palmt5_ficp_platform_data = { | ||
| 335 | .startup = palmt5_irda_startup, | ||
| 336 | .shutdown = palmt5_irda_shutdown, | ||
| 337 | .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF, | ||
| 338 | .transceiver_mode = palmt5_irda_transceiver_mode, | ||
| 339 | }; | ||
| 340 | |||
| 341 | /****************************************************************************** | ||
| 342 | * UDC | ||
| 343 | ******************************************************************************/ | ||
| 344 | static struct pxa2xx_udc_mach_info palmt5_udc_info __initdata = { | ||
| 345 | .gpio_vbus = GPIO_NR_PALMT5_USB_DETECT_N, | ||
| 346 | .gpio_vbus_inverted = 1, | ||
| 347 | .gpio_pullup = GPIO_NR_PALMT5_USB_POWER, | ||
| 348 | .gpio_pullup_inverted = 0, | ||
| 349 | }; | ||
| 350 | |||
| 351 | /****************************************************************************** | ||
| 352 | * Power supply | ||
| 353 | ******************************************************************************/ | ||
| 354 | static int power_supply_init(struct device *dev) | ||
| 355 | { | ||
| 356 | int ret; | ||
| 357 | |||
| 358 | ret = gpio_request(GPIO_NR_PALMT5_POWER_DETECT, "CABLE_STATE_AC"); | ||
| 359 | if (ret) | ||
| 360 | goto err1; | ||
| 361 | ret = gpio_direction_input(GPIO_NR_PALMT5_POWER_DETECT); | ||
| 362 | if (ret) | ||
| 363 | goto err2; | ||
| 364 | |||
| 365 | return 0; | ||
| 366 | err2: | ||
| 367 | gpio_free(GPIO_NR_PALMT5_POWER_DETECT); | ||
| 368 | err1: | ||
| 369 | return ret; | ||
| 370 | } | ||
| 371 | |||
| 372 | static int palmt5_is_ac_online(void) | ||
| 373 | { | ||
| 374 | return gpio_get_value(GPIO_NR_PALMT5_POWER_DETECT); | ||
| 375 | } | ||
| 376 | |||
| 377 | static void power_supply_exit(struct device *dev) | ||
| 378 | { | ||
| 379 | gpio_free(GPIO_NR_PALMT5_POWER_DETECT); | ||
| 380 | } | ||
| 381 | |||
| 382 | static char *palmt5_supplicants[] = { | ||
| 383 | "main-battery", | ||
| 384 | }; | ||
| 385 | |||
| 386 | static struct pda_power_pdata power_supply_info = { | ||
| 387 | .init = power_supply_init, | ||
| 388 | .is_ac_online = palmt5_is_ac_online, | ||
| 389 | .exit = power_supply_exit, | ||
| 390 | .supplied_to = palmt5_supplicants, | ||
| 391 | .num_supplicants = ARRAY_SIZE(palmt5_supplicants), | ||
| 392 | }; | ||
| 393 | |||
| 394 | static struct platform_device power_supply = { | ||
| 395 | .name = "pda-power", | ||
| 396 | .id = -1, | ||
| 397 | .dev = { | ||
| 398 | .platform_data = &power_supply_info, | ||
| 399 | }, | ||
| 400 | }; | ||
| 401 | |||
| 402 | /****************************************************************************** | ||
| 403 | * WM97xx battery | ||
| 404 | ******************************************************************************/ | ||
| 405 | static struct wm97xx_batt_info wm97xx_batt_pdata = { | ||
| 406 | .batt_aux = WM97XX_AUX_ID3, | ||
| 407 | .temp_aux = WM97XX_AUX_ID2, | ||
| 408 | .charge_gpio = -1, | ||
| 409 | .max_voltage = PALMT5_BAT_MAX_VOLTAGE, | ||
| 410 | .min_voltage = PALMT5_BAT_MIN_VOLTAGE, | ||
| 411 | .batt_mult = 1000, | ||
| 412 | .batt_div = 414, | ||
| 413 | .temp_mult = 1, | ||
| 414 | .temp_div = 1, | ||
| 415 | .batt_tech = POWER_SUPPLY_TECHNOLOGY_LIPO, | ||
| 416 | .batt_name = "main-batt", | ||
| 417 | }; | ||
| 418 | |||
| 419 | /****************************************************************************** | ||
| 420 | * aSoC audio | ||
| 421 | ******************************************************************************/ | ||
| 422 | static struct palm27x_asoc_info palm27x_asoc_pdata = { | ||
| 423 | .jack_gpio = GPIO_NR_PALMT5_EARPHONE_DETECT, | ||
| 424 | }; | ||
| 425 | |||
| 426 | /****************************************************************************** | ||
| 427 | * Framebuffer | ||
| 428 | ******************************************************************************/ | ||
| 429 | static struct pxafb_mode_info palmt5_lcd_modes[] = { | ||
| 430 | { | ||
| 431 | .pixclock = 57692, | ||
| 432 | .xres = 320, | ||
| 433 | .yres = 480, | ||
| 434 | .bpp = 16, | ||
| 435 | |||
| 436 | .left_margin = 32, | ||
| 437 | .right_margin = 1, | ||
| 438 | .upper_margin = 7, | ||
| 439 | .lower_margin = 1, | ||
| 440 | |||
| 441 | .hsync_len = 4, | ||
| 442 | .vsync_len = 1, | ||
| 443 | }, | ||
| 444 | }; | ||
| 445 | |||
| 446 | static struct pxafb_mach_info palmt5_lcd_screen = { | ||
| 447 | .modes = palmt5_lcd_modes, | ||
| 448 | .num_modes = ARRAY_SIZE(palmt5_lcd_modes), | ||
| 449 | .lcd_conn = LCD_COLOR_TFT_16BPP | LCD_PCLK_EDGE_FALL, | ||
| 450 | }; | ||
| 451 | |||
| 452 | /****************************************************************************** | ||
| 453 | * Machine init | ||
| 454 | ******************************************************************************/ | ||
| 455 | static struct platform_device *devices[] __initdata = { | ||
| 456 | #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) | ||
| 457 | &palmt5_pxa_keys, | ||
| 458 | #endif | ||
| 459 | &palmt5_backlight, | ||
| 460 | &power_supply, | ||
| 461 | }; | ||
| 462 | |||
| 463 | /* setup udc GPIOs initial state */ | ||
| 464 | static void __init palmt5_udc_init(void) | ||
| 465 | { | ||
| 466 | if (!gpio_request(GPIO_NR_PALMT5_USB_POWER, "UDC Vbus")) { | ||
| 467 | gpio_direction_output(GPIO_NR_PALMT5_USB_POWER, 1); | ||
| 468 | gpio_free(GPIO_NR_PALMT5_USB_POWER); | ||
| 469 | } | ||
| 470 | } | ||
| 471 | |||
| 472 | static void __init palmt5_init(void) | ||
| 473 | { | ||
| 474 | pxa2xx_mfp_config(ARRAY_AND_SIZE(palmt5_pin_config)); | ||
| 475 | |||
| 476 | set_pxa_fb_info(&palmt5_lcd_screen); | ||
| 477 | pxa_set_mci_info(&palmt5_mci_platform_data); | ||
| 478 | palmt5_udc_init(); | ||
| 479 | pxa_set_udc_info(&palmt5_udc_info); | ||
| 480 | pxa_set_ac97_info(NULL); | ||
| 481 | pxa_set_ficp_info(&palmt5_ficp_platform_data); | ||
| 482 | pxa_set_keypad_info(&palmt5_keypad_platform_data); | ||
| 483 | wm97xx_bat_set_pdata(&wm97xx_batt_pdata); | ||
| 484 | palm27x_asoc_set_pdata(&palm27x_asoc_pdata); | ||
| 485 | platform_add_devices(devices, ARRAY_SIZE(devices)); | ||
| 486 | } | ||
| 487 | |||
| 488 | MACHINE_START(PALMT5, "Palm Tungsten|T5") | ||
| 489 | .phys_io = PALMT5_PHYS_IO_START, | ||
| 490 | .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc, | ||
| 491 | .boot_params = 0xa0000100, | ||
| 492 | .map_io = pxa_map_io, | ||
| 493 | .init_irq = pxa27x_init_irq, | ||
| 494 | .timer = &pxa_timer, | ||
| 495 | .init_machine = palmt5_init | ||
| 496 | MACHINE_END | ||
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c index a9d94f5dbec4..b490c0924619 100644 --- a/arch/arm/mach-pxa/palmtx.c +++ b/arch/arm/mach-pxa/palmtx.c | |||
| @@ -32,12 +32,11 @@ | |||
| 32 | #include <asm/mach/arch.h> | 32 | #include <asm/mach/arch.h> |
| 33 | #include <asm/mach/map.h> | 33 | #include <asm/mach/map.h> |
| 34 | 34 | ||
| 35 | #include <mach/pxa27x.h> | ||
| 35 | #include <mach/audio.h> | 36 | #include <mach/audio.h> |
| 36 | #include <mach/palmtx.h> | 37 | #include <mach/palmtx.h> |
| 37 | #include <mach/mmc.h> | 38 | #include <mach/mmc.h> |
| 38 | #include <mach/pxafb.h> | 39 | #include <mach/pxafb.h> |
| 39 | #include <mach/pxa-regs.h> | ||
| 40 | #include <mach/mfp-pxa27x.h> | ||
| 41 | #include <mach/irda.h> | 40 | #include <mach/irda.h> |
| 42 | #include <mach/pxa27x_keypad.h> | 41 | #include <mach/pxa27x_keypad.h> |
| 43 | #include <mach/udc.h> | 42 | #include <mach/udc.h> |
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c index 2f730da3bba8..b88eb4dd2c84 100644 --- a/arch/arm/mach-pxa/palmz72.c +++ b/arch/arm/mach-pxa/palmz72.c | |||
| @@ -33,13 +33,11 @@ | |||
| 33 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
| 34 | #include <asm/mach/map.h> | 34 | #include <asm/mach/map.h> |
| 35 | 35 | ||
| 36 | #include <mach/pxa27x.h> | ||
| 36 | #include <mach/audio.h> | 37 | #include <mach/audio.h> |
| 37 | #include <mach/palmz72.h> | 38 | #include <mach/palmz72.h> |
| 38 | #include <mach/mmc.h> | 39 | #include <mach/mmc.h> |
| 39 | #include <mach/pxafb.h> | 40 | #include <mach/pxafb.h> |
| 40 | #include <mach/pxa-regs.h> | ||
| 41 | #include <mach/pxa2xx-regs.h> | ||
| 42 | #include <mach/mfp-pxa27x.h> | ||
| 43 | #include <mach/irda.h> | 41 | #include <mach/irda.h> |
| 44 | #include <mach/pxa27x_keypad.h> | 42 | #include <mach/pxa27x_keypad.h> |
| 45 | #include <mach/udc.h> | 43 | #include <mach/udc.h> |
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c index 36135a02fdc7..6abfa2979c61 100644 --- a/arch/arm/mach-pxa/pcm027.c +++ b/arch/arm/mach-pxa/pcm027.c | |||
| @@ -29,10 +29,7 @@ | |||
| 29 | 29 | ||
| 30 | #include <asm/mach-types.h> | 30 | #include <asm/mach-types.h> |
| 31 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
| 32 | #include <mach/hardware.h> | 32 | #include <mach/pxa27x.h> |
| 33 | #include <mach/pxa-regs.h> | ||
| 34 | #include <mach/mfp-pxa27x.h> | ||
| 35 | #include <mach/pxa2xx-regs.h> | ||
| 36 | #include <mach/pxa2xx_spi.h> | 33 | #include <mach/pxa2xx_spi.h> |
| 37 | #include <mach/pcm027.h> | 34 | #include <mach/pcm027.h> |
| 38 | #include "generic.h" | 35 | #include "generic.h" |
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 34841c72815f..f46698e20c1f 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c | |||
| @@ -31,13 +31,12 @@ | |||
| 31 | #include <mach/i2c.h> | 31 | #include <mach/i2c.h> |
| 32 | #include <mach/camera.h> | 32 | #include <mach/camera.h> |
| 33 | #include <asm/mach/map.h> | 33 | #include <asm/mach/map.h> |
| 34 | #include <mach/pxa-regs.h> | 34 | #include <mach/pxa27x.h> |
| 35 | #include <mach/audio.h> | 35 | #include <mach/audio.h> |
| 36 | #include <mach/mmc.h> | 36 | #include <mach/mmc.h> |
| 37 | #include <mach/ohci.h> | 37 | #include <mach/ohci.h> |
| 38 | #include <mach/pcm990_baseboard.h> | 38 | #include <mach/pcm990_baseboard.h> |
| 39 | #include <mach/pxafb.h> | 39 | #include <mach/pxafb.h> |
| 40 | #include <mach/mfp-pxa27x.h> | ||
| 41 | 40 | ||
| 42 | #include "devices.h" | 41 | #include "devices.h" |
| 43 | #include "generic.h" | 42 | #include "generic.h" |
diff --git a/arch/arm/mach-pxa/pm.c b/arch/arm/mach-pxa/pm.c index 164eb0bb6321..884b174c8ead 100644 --- a/arch/arm/mach-pxa/pm.c +++ b/arch/arm/mach-pxa/pm.c | |||
| @@ -14,15 +14,8 @@ | |||
| 14 | #include <linux/module.h> | 14 | #include <linux/module.h> |
| 15 | #include <linux/suspend.h> | 15 | #include <linux/suspend.h> |
| 16 | #include <linux/errno.h> | 16 | #include <linux/errno.h> |
| 17 | #include <linux/time.h> | ||
| 18 | 17 | ||
| 19 | #include <mach/hardware.h> | ||
| 20 | #include <asm/memory.h> | ||
| 21 | #include <asm/system.h> | ||
| 22 | #include <mach/pm.h> | 18 | #include <mach/pm.h> |
| 23 | #include <mach/pxa-regs.h> | ||
| 24 | #include <mach/lubbock.h> | ||
| 25 | #include <asm/mach/time.h> | ||
| 26 | 19 | ||
| 27 | struct pxa_cpu_pm_fns *pxa_cpu_pm_fns; | 20 | struct pxa_cpu_pm_fns *pxa_cpu_pm_fns; |
| 28 | static unsigned long *sleep_save; | 21 | static unsigned long *sleep_save; |
| @@ -57,9 +50,9 @@ int pxa_pm_enter(suspend_state_t state) | |||
| 57 | 50 | ||
| 58 | /* if invalid, display message and wait for a hardware reset */ | 51 | /* if invalid, display message and wait for a hardware reset */ |
| 59 | if (checksum != sleep_save_checksum) { | 52 | if (checksum != sleep_save_checksum) { |
| 60 | #ifdef CONFIG_ARCH_LUBBOCK | 53 | |
| 61 | LUB_HEXLED = 0xbadbadc5; | 54 | lubbock_set_hexled(0xbadbadc5); |
| 62 | #endif | 55 | |
| 63 | while (1) | 56 | while (1) |
| 64 | pxa_cpu_pm_fns->enter(state); | 57 | pxa_cpu_pm_fns->enter(state); |
| 65 | } | 58 | } |
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c index f9093beba752..036bbde4d221 100644 --- a/arch/arm/mach-pxa/poodle.c +++ b/arch/arm/mach-pxa/poodle.c | |||
| @@ -36,9 +36,7 @@ | |||
| 36 | #include <asm/mach/map.h> | 36 | #include <asm/mach/map.h> |
| 37 | #include <asm/mach/irq.h> | 37 | #include <asm/mach/irq.h> |
| 38 | 38 | ||
| 39 | #include <mach/pxa-regs.h> | 39 | #include <mach/pxa25x.h> |
| 40 | #include <mach/pxa2xx-regs.h> | ||
| 41 | #include <mach/mfp-pxa25x.h> | ||
| 42 | #include <mach/mmc.h> | 40 | #include <mach/mmc.h> |
| 43 | #include <mach/udc.h> | 41 | #include <mach/udc.h> |
| 44 | #include <mach/i2c.h> | 42 | #include <mach/i2c.h> |
| @@ -503,12 +501,12 @@ static struct platform_device *devices[] __initdata = { | |||
| 503 | 501 | ||
| 504 | static void poodle_poweroff(void) | 502 | static void poodle_poweroff(void) |
| 505 | { | 503 | { |
| 506 | arm_machine_restart('h'); | 504 | arm_machine_restart('h', NULL); |
| 507 | } | 505 | } |
| 508 | 506 | ||
| 509 | static void poodle_restart(char mode) | 507 | static void poodle_restart(char mode, const char *cmd) |
| 510 | { | 508 | { |
| 511 | arm_machine_restart('h'); | 509 | arm_machine_restart('h', cmd); |
| 512 | } | 510 | } |
| 513 | 511 | ||
| 514 | static void __init poodle_init(void) | 512 | static void __init poodle_init(void) |
diff --git a/arch/arm/mach-pxa/pwm.c b/arch/arm/mach-pxa/pwm.c index 3ca7ffc6904b..fcdd374437a8 100644 --- a/arch/arm/mach-pxa/pwm.c +++ b/arch/arm/mach-pxa/pwm.c | |||
| @@ -20,7 +20,6 @@ | |||
| 20 | #include <linux/pwm.h> | 20 | #include <linux/pwm.h> |
| 21 | 21 | ||
| 22 | #include <asm/div64.h> | 22 | #include <asm/div64.h> |
| 23 | #include <mach/pxa-regs.h> | ||
| 24 | 23 | ||
| 25 | /* PWM registers and bits definitions */ | 24 | /* PWM registers and bits definitions */ |
| 26 | #define PWMCR (0x00) | 25 | #define PWMCR (0x00) |
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 6c57522e2469..77c2693cfeef 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c | |||
| @@ -25,9 +25,8 @@ | |||
| 25 | 25 | ||
| 26 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
| 27 | #include <mach/irqs.h> | 27 | #include <mach/irqs.h> |
| 28 | #include <mach/pxa-regs.h> | 28 | #include <mach/gpio.h> |
| 29 | #include <mach/pxa2xx-regs.h> | 29 | #include <mach/pxa25x.h> |
| 30 | #include <mach/mfp-pxa25x.h> | ||
| 31 | #include <mach/reset.h> | 30 | #include <mach/reset.h> |
| 32 | #include <mach/pm.h> | 31 | #include <mach/pm.h> |
| 33 | #include <mach/dma.h> | 32 | #include <mach/dma.h> |
| @@ -310,14 +309,14 @@ set_pwer: | |||
| 310 | void __init pxa25x_init_irq(void) | 309 | void __init pxa25x_init_irq(void) |
| 311 | { | 310 | { |
| 312 | pxa_init_irq(32, pxa25x_set_wake); | 311 | pxa_init_irq(32, pxa25x_set_wake); |
| 313 | pxa_init_gpio(85, pxa25x_set_wake); | 312 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 84, pxa25x_set_wake); |
| 314 | } | 313 | } |
| 315 | 314 | ||
| 316 | #ifdef CONFIG_CPU_PXA26x | 315 | #ifdef CONFIG_CPU_PXA26x |
| 317 | void __init pxa26x_init_irq(void) | 316 | void __init pxa26x_init_irq(void) |
| 318 | { | 317 | { |
| 319 | pxa_init_irq(32, pxa25x_set_wake); | 318 | pxa_init_irq(32, pxa25x_set_wake); |
| 320 | pxa_init_gpio(90, pxa25x_set_wake); | 319 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 89, pxa25x_set_wake); |
| 321 | } | 320 | } |
| 322 | #endif | 321 | #endif |
| 323 | 322 | ||
| @@ -355,7 +354,7 @@ static int __init pxa25x_init(void) | |||
| 355 | 354 | ||
| 356 | clks_register(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs)); | 355 | clks_register(pxa25x_clkregs, ARRAY_SIZE(pxa25x_clkregs)); |
| 357 | 356 | ||
| 358 | if ((ret = pxa_init_dma(16))) | 357 | if ((ret = pxa_init_dma(IRQ_DMA, 16))) |
| 359 | return ret; | 358 | return ret; |
| 360 | 359 | ||
| 361 | pxa25x_init_pm(); | 360 | pxa25x_init_pm(); |
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 411bec54fdc4..a425ec71e657 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c | |||
| @@ -21,9 +21,8 @@ | |||
| 21 | #include <mach/hardware.h> | 21 | #include <mach/hardware.h> |
| 22 | #include <asm/irq.h> | 22 | #include <asm/irq.h> |
| 23 | #include <mach/irqs.h> | 23 | #include <mach/irqs.h> |
| 24 | #include <mach/pxa-regs.h> | 24 | #include <mach/gpio.h> |
| 25 | #include <mach/pxa2xx-regs.h> | 25 | #include <mach/pxa27x.h> |
| 26 | #include <mach/mfp-pxa27x.h> | ||
| 27 | #include <mach/reset.h> | 26 | #include <mach/reset.h> |
| 28 | #include <mach/ohci.h> | 27 | #include <mach/ohci.h> |
| 29 | #include <mach/pm.h> | 28 | #include <mach/pm.h> |
| @@ -332,7 +331,7 @@ static int pxa27x_set_wake(unsigned int irq, unsigned int on) | |||
| 332 | void __init pxa27x_init_irq(void) | 331 | void __init pxa27x_init_irq(void) |
| 333 | { | 332 | { |
| 334 | pxa_init_irq(34, pxa27x_set_wake); | 333 | pxa_init_irq(34, pxa27x_set_wake); |
| 335 | pxa_init_gpio(121, pxa27x_set_wake); | 334 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 120, pxa27x_set_wake); |
| 336 | } | 335 | } |
| 337 | 336 | ||
| 338 | /* | 337 | /* |
| @@ -381,7 +380,7 @@ static int __init pxa27x_init(void) | |||
| 381 | 380 | ||
| 382 | clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs)); | 381 | clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs)); |
| 383 | 382 | ||
| 384 | if ((ret = pxa_init_dma(32))) | 383 | if ((ret = pxa_init_dma(IRQ_DMA, 32))) |
| 385 | return ret; | 384 | return ret; |
| 386 | 385 | ||
| 387 | pxa27x_init_pm(); | 386 | pxa27x_init_pm(); |
diff --git a/arch/arm/mach-pxa/pxa2xx.c b/arch/arm/mach-pxa/pxa2xx.c index 73d04d81c75a..2f3394f85917 100644 --- a/arch/arm/mach-pxa/pxa2xx.c +++ b/arch/arm/mach-pxa/pxa2xx.c | |||
| @@ -16,7 +16,6 @@ | |||
| 16 | 16 | ||
| 17 | #include <mach/hardware.h> | 17 | #include <mach/hardware.h> |
| 18 | #include <mach/pxa2xx-regs.h> | 18 | #include <mach/pxa2xx-regs.h> |
| 19 | #include <mach/mfp-pxa2xx.h> | ||
| 20 | #include <mach/mfp-pxa25x.h> | 19 | #include <mach/mfp-pxa25x.h> |
| 21 | #include <mach/reset.h> | 20 | #include <mach/reset.h> |
| 22 | #include <mach/irda.h> | 21 | #include <mach/irda.h> |
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c index 83fb609b6eb7..4ba6d21f851c 100644 --- a/arch/arm/mach-pxa/pxa300.c +++ b/arch/arm/mach-pxa/pxa300.c | |||
| @@ -17,15 +17,13 @@ | |||
| 17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
| 19 | 19 | ||
| 20 | #include <mach/hardware.h> | 20 | #include <mach/pxa300.h> |
| 21 | #include <mach/pxa3xx-regs.h> | ||
| 22 | #include <mach/mfp-pxa300.h> | ||
| 23 | 21 | ||
| 24 | #include "generic.h" | 22 | #include "generic.h" |
| 25 | #include "devices.h" | 23 | #include "devices.h" |
| 26 | #include "clock.h" | 24 | #include "clock.h" |
| 27 | 25 | ||
| 28 | static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = { | 26 | static struct mfp_addr_map pxa300_mfp_addr_map[] __initdata = { |
| 29 | 27 | ||
| 30 | MFP_ADDR_X(GPIO0, GPIO2, 0x00b4), | 28 | MFP_ADDR_X(GPIO0, GPIO2, 0x00b4), |
| 31 | MFP_ADDR_X(GPIO3, GPIO26, 0x027c), | 29 | MFP_ADDR_X(GPIO3, GPIO26, 0x027c), |
| @@ -74,7 +72,7 @@ static struct pxa3xx_mfp_addr_map pxa300_mfp_addr_map[] __initdata = { | |||
| 74 | }; | 72 | }; |
| 75 | 73 | ||
| 76 | /* override pxa300 MFP register addresses */ | 74 | /* override pxa300 MFP register addresses */ |
| 77 | static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = { | 75 | static struct mfp_addr_map pxa310_mfp_addr_map[] __initdata = { |
| 78 | MFP_ADDR_X(GPIO30, GPIO98, 0x0418), | 76 | MFP_ADDR_X(GPIO30, GPIO98, 0x0418), |
| 79 | MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C), | 77 | MFP_ADDR_X(GPIO7_2, GPIO12_2, 0x052C), |
| 80 | 78 | ||
| @@ -100,13 +98,13 @@ static struct clk_lookup pxa310_clkregs[] = { | |||
| 100 | static int __init pxa300_init(void) | 98 | static int __init pxa300_init(void) |
| 101 | { | 99 | { |
| 102 | if (cpu_is_pxa300() || cpu_is_pxa310()) { | 100 | if (cpu_is_pxa300() || cpu_is_pxa310()) { |
| 103 | pxa3xx_init_mfp(); | 101 | mfp_init_base(io_p2v(MFPR_BASE)); |
| 104 | pxa3xx_mfp_init_addr(pxa300_mfp_addr_map); | 102 | mfp_init_addr(pxa300_mfp_addr_map); |
| 105 | clks_register(ARRAY_AND_SIZE(common_clkregs)); | 103 | clks_register(ARRAY_AND_SIZE(common_clkregs)); |
| 106 | } | 104 | } |
| 107 | 105 | ||
| 108 | if (cpu_is_pxa310()) { | 106 | if (cpu_is_pxa310()) { |
| 109 | pxa3xx_mfp_init_addr(pxa310_mfp_addr_map); | 107 | mfp_init_addr(pxa310_mfp_addr_map); |
| 110 | clks_register(ARRAY_AND_SIZE(pxa310_clkregs)); | 108 | clks_register(ARRAY_AND_SIZE(pxa310_clkregs)); |
| 111 | } | 109 | } |
| 112 | 110 | ||
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c index 36f066196fa2..8b3d97efadab 100644 --- a/arch/arm/mach-pxa/pxa320.c +++ b/arch/arm/mach-pxa/pxa320.c | |||
| @@ -17,16 +17,13 @@ | |||
| 17 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
| 18 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
| 19 | 19 | ||
| 20 | #include <mach/hardware.h> | 20 | #include <mach/pxa320.h> |
| 21 | #include <mach/mfp.h> | ||
| 22 | #include <mach/pxa3xx-regs.h> | ||
| 23 | #include <mach/mfp-pxa320.h> | ||
| 24 | 21 | ||
| 25 | #include "generic.h" | 22 | #include "generic.h" |
| 26 | #include "devices.h" | 23 | #include "devices.h" |
| 27 | #include "clock.h" | 24 | #include "clock.h" |
| 28 | 25 | ||
| 29 | static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = { | 26 | static struct mfp_addr_map pxa320_mfp_addr_map[] __initdata = { |
| 30 | 27 | ||
| 31 | MFP_ADDR_X(GPIO0, GPIO4, 0x0124), | 28 | MFP_ADDR_X(GPIO0, GPIO4, 0x0124), |
| 32 | MFP_ADDR_X(GPIO5, GPIO9, 0x028C), | 29 | MFP_ADDR_X(GPIO5, GPIO9, 0x028C), |
| @@ -89,8 +86,8 @@ static struct clk_lookup pxa320_clkregs[] = { | |||
| 89 | static int __init pxa320_init(void) | 86 | static int __init pxa320_init(void) |
| 90 | { | 87 | { |
| 91 | if (cpu_is_pxa320()) { | 88 | if (cpu_is_pxa320()) { |
| 92 | pxa3xx_init_mfp(); | 89 | mfp_init_base(io_p2v(MFPR_BASE)); |
| 93 | pxa3xx_mfp_init_addr(pxa320_mfp_addr_map); | 90 | mfp_init_addr(pxa320_mfp_addr_map); |
| 94 | clks_register(ARRAY_AND_SIZE(pxa320_clkregs)); | 91 | clks_register(ARRAY_AND_SIZE(pxa320_clkregs)); |
| 95 | } | 92 | } |
| 96 | 93 | ||
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 490893824e78..b02d4544dc95 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/sysdev.h> | 23 | #include <linux/sysdev.h> |
| 24 | 24 | ||
| 25 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
| 26 | #include <mach/gpio.h> | ||
| 26 | #include <mach/pxa3xx-regs.h> | 27 | #include <mach/pxa3xx-regs.h> |
| 27 | #include <mach/reset.h> | 28 | #include <mach/reset.h> |
| 28 | #include <mach/ohci.h> | 29 | #include <mach/ohci.h> |
| @@ -538,7 +539,7 @@ void __init pxa3xx_init_irq(void) | |||
| 538 | __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); | 539 | __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); |
| 539 | 540 | ||
| 540 | pxa_init_irq(56, pxa3xx_set_wake); | 541 | pxa_init_irq(56, pxa3xx_set_wake); |
| 541 | pxa_init_gpio(128, NULL); | 542 | pxa_init_gpio(IRQ_GPIO_2_x, 2, 127, NULL); |
| 542 | } | 543 | } |
| 543 | 544 | ||
| 544 | /* | 545 | /* |
| @@ -594,7 +595,7 @@ static int __init pxa3xx_init(void) | |||
| 594 | 595 | ||
| 595 | clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); | 596 | clks_register(pxa3xx_clkregs, ARRAY_SIZE(pxa3xx_clkregs)); |
| 596 | 597 | ||
| 597 | if ((ret = pxa_init_dma(32))) | 598 | if ((ret = pxa_init_dma(IRQ_DMA, 32))) |
| 598 | return ret; | 599 | return ret; |
| 599 | 600 | ||
| 600 | pxa3xx_init_pm(); | 601 | pxa3xx_init_pm(); |
diff --git a/arch/arm/mach-pxa/pxa930.c b/arch/arm/mach-pxa/pxa930.c index 13e6bfdfff60..71131742fffd 100644 --- a/arch/arm/mach-pxa/pxa930.c +++ b/arch/arm/mach-pxa/pxa930.c | |||
| @@ -16,10 +16,9 @@ | |||
| 16 | #include <linux/irq.h> | 16 | #include <linux/irq.h> |
| 17 | #include <linux/dma-mapping.h> | 17 | #include <linux/dma-mapping.h> |
| 18 | 18 | ||
| 19 | #include <mach/hardware.h> | 19 | #include <mach/pxa930.h> |
| 20 | #include <mach/mfp-pxa930.h> | ||
| 21 | 20 | ||
| 22 | static struct pxa3xx_mfp_addr_map pxa930_mfp_addr_map[] __initdata = { | 21 | static struct mfp_addr_map pxa930_mfp_addr_map[] __initdata = { |
| 23 | 22 | ||
| 24 | MFP_ADDR(GPIO0, 0x02e0), | 23 | MFP_ADDR(GPIO0, 0x02e0), |
| 25 | MFP_ADDR(GPIO1, 0x02dc), | 24 | MFP_ADDR(GPIO1, 0x02dc), |
| @@ -180,8 +179,8 @@ static struct pxa3xx_mfp_addr_map pxa930_mfp_addr_map[] __initdata = { | |||
| 180 | static int __init pxa930_init(void) | 179 | static int __init pxa930_init(void) |
| 181 | { | 180 | { |
| 182 | if (cpu_is_pxa930()) { | 181 | if (cpu_is_pxa930()) { |
| 183 | pxa3xx_init_mfp(); | 182 | mfp_init_base(io_p2v(MFPR_BASE)); |
| 184 | pxa3xx_mfp_init_addr(pxa930_mfp_addr_map); | 183 | mfp_init_addr(pxa930_mfp_addr_map); |
| 185 | } | 184 | } |
| 186 | 185 | ||
| 187 | return 0; | 186 | return 0; |
diff --git a/arch/arm/mach-pxa/reset.c b/arch/arm/mach-pxa/reset.c index 00b2dc2a1074..df29d45fb4e7 100644 --- a/arch/arm/mach-pxa/reset.c +++ b/arch/arm/mach-pxa/reset.c | |||
| @@ -10,7 +10,7 @@ | |||
| 10 | #include <linux/io.h> | 10 | #include <linux/io.h> |
| 11 | #include <asm/proc-fns.h> | 11 | #include <asm/proc-fns.h> |
| 12 | 12 | ||
| 13 | #include <mach/pxa-regs.h> | 13 | #include <mach/regs-ost.h> |
| 14 | #include <mach/reset.h> | 14 | #include <mach/reset.h> |
| 15 | 15 | ||
| 16 | unsigned int reset_status; | 16 | unsigned int reset_status; |
| @@ -81,7 +81,7 @@ static void do_hw_reset(void) | |||
| 81 | OSMR3 = OSCR + 368640; /* ... in 100 ms */ | 81 | OSMR3 = OSCR + 368640; /* ... in 100 ms */ |
| 82 | } | 82 | } |
| 83 | 83 | ||
| 84 | void arch_reset(char mode) | 84 | void arch_reset(char mode, const char *cmd) |
| 85 | { | 85 | { |
| 86 | clear_reset_status(RESET_STATUS_ALL); | 86 | clear_reset_status(RESET_STATUS_ALL); |
| 87 | 87 | ||
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c index 5d02a7325586..ff8239991430 100644 --- a/arch/arm/mach-pxa/saar.c +++ b/arch/arm/mach-pxa/saar.c | |||
| @@ -25,11 +25,9 @@ | |||
| 25 | 25 | ||
| 26 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
| 27 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| 28 | #include <mach/hardware.h> | 28 | |
| 29 | #include <mach/pxa3xx-regs.h> | 29 | #include <mach/pxa930.h> |
| 30 | #include <mach/mfp-pxa930.h> | ||
| 31 | #include <mach/i2c.h> | 30 | #include <mach/i2c.h> |
| 32 | #include <mach/regs-lcd.h> | ||
| 33 | #include <mach/pxafb.h> | 31 | #include <mach/pxafb.h> |
| 34 | 32 | ||
| 35 | #include "devices.h" | 33 | #include "devices.h" |
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index f0845c1b001c..16b4ec67e3b6 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c | |||
| @@ -25,7 +25,6 @@ | |||
| 25 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
| 26 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
| 27 | #include <mach/pm.h> | 27 | #include <mach/pm.h> |
| 28 | #include <mach/pxa-regs.h> | ||
| 29 | #include <mach/pxa2xx-gpio.h> | 28 | #include <mach/pxa2xx-gpio.h> |
| 30 | #include <mach/sharpsl.h> | 29 | #include <mach/sharpsl.h> |
| 31 | #include "sharpsl.h" | 30 | #include "sharpsl.h" |
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index a62c8375eb53..2ed95f369cfc 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S | |||
| @@ -15,7 +15,6 @@ | |||
| 15 | #include <asm/assembler.h> | 15 | #include <asm/assembler.h> |
| 16 | #include <mach/hardware.h> | 16 | #include <mach/hardware.h> |
| 17 | 17 | ||
| 18 | #include <mach/pxa-regs.h> | ||
| 19 | #include <mach/pxa2xx-regs.h> | 18 | #include <mach/pxa2xx-regs.h> |
| 20 | 19 | ||
| 21 | #define MDREFR_KDIV 0x200a4000 // all banks | 20 | #define MDREFR_KDIV 0x200a4000 // all banks |
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 6d447c9ce8ab..7a0a430222cf 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c | |||
| @@ -44,9 +44,7 @@ | |||
| 44 | #include <asm/mach/map.h> | 44 | #include <asm/mach/map.h> |
| 45 | #include <asm/mach/irq.h> | 45 | #include <asm/mach/irq.h> |
| 46 | 46 | ||
| 47 | #include <mach/pxa-regs.h> | 47 | #include <mach/pxa27x.h> |
| 48 | #include <mach/pxa2xx-regs.h> | ||
| 49 | #include <mach/mfp-pxa27x.h> | ||
| 50 | #include <mach/pxa27x-udc.h> | 48 | #include <mach/pxa27x-udc.h> |
| 51 | #include <mach/reset.h> | 49 | #include <mach/reset.h> |
| 52 | #include <mach/i2c.h> | 50 | #include <mach/i2c.h> |
| @@ -703,10 +701,10 @@ static struct platform_device *devices[] __initdata = { | |||
| 703 | 701 | ||
| 704 | static void spitz_poweroff(void) | 702 | static void spitz_poweroff(void) |
| 705 | { | 703 | { |
| 706 | arm_machine_restart('g'); | 704 | arm_machine_restart('g', NULL); |
| 707 | } | 705 | } |
| 708 | 706 | ||
| 709 | static void spitz_restart(char mode) | 707 | static void spitz_restart(char mode, const char *cmd) |
| 710 | { | 708 | { |
| 711 | /* Bootloader magic for a reboot */ | 709 | /* Bootloader magic for a reboot */ |
| 712 | if((MSC0 & 0xffff0000) == 0x7ff00000) | 710 | if((MSC0 & 0xffff0000) == 0x7ff00000) |
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c index 072e77cfe5a3..2e4490562c9e 100644 --- a/arch/arm/mach-pxa/spitz_pm.c +++ b/arch/arm/mach-pxa/spitz_pm.c | |||
| @@ -24,7 +24,6 @@ | |||
| 24 | 24 | ||
| 25 | #include <mach/sharpsl.h> | 25 | #include <mach/sharpsl.h> |
| 26 | #include <mach/spitz.h> | 26 | #include <mach/spitz.h> |
| 27 | #include <mach/pxa-regs.h> | ||
| 28 | #include <mach/pxa2xx-regs.h> | 27 | #include <mach/pxa2xx-regs.h> |
| 29 | #include <mach/pxa2xx-gpio.h> | 28 | #include <mach/pxa2xx-gpio.h> |
| 30 | #include "sharpsl.h" | 29 | #include "sharpsl.h" |
diff --git a/arch/arm/mach-pxa/ssp.c b/arch/arm/mach-pxa/ssp.c index 6f42004db3ed..965e38c6bafe 100644 --- a/arch/arm/mach-pxa/ssp.c +++ b/arch/arm/mach-pxa/ssp.c | |||
| @@ -33,7 +33,6 @@ | |||
| 33 | #include <asm/irq.h> | 33 | #include <asm/irq.h> |
| 34 | #include <mach/hardware.h> | 34 | #include <mach/hardware.h> |
| 35 | #include <mach/ssp.h> | 35 | #include <mach/ssp.h> |
| 36 | #include <mach/pxa-regs.h> | ||
| 37 | #include <mach/regs-ssp.h> | 36 | #include <mach/regs-ssp.h> |
| 38 | 37 | ||
| 39 | #define TIMEOUT 100000 | 38 | #define TIMEOUT 100000 |
diff --git a/arch/arm/mach-pxa/standby.S b/arch/arm/mach-pxa/standby.S index f3821cfda72f..29f5f5c180b7 100644 --- a/arch/arm/mach-pxa/standby.S +++ b/arch/arm/mach-pxa/standby.S | |||
| @@ -13,7 +13,6 @@ | |||
| 13 | #include <asm/assembler.h> | 13 | #include <asm/assembler.h> |
| 14 | #include <mach/hardware.h> | 14 | #include <mach/hardware.h> |
| 15 | 15 | ||
| 16 | #include <mach/pxa-regs.h> | ||
| 17 | #include <mach/pxa2xx-regs.h> | 16 | #include <mach/pxa2xx-regs.h> |
| 18 | 17 | ||
| 19 | .text | 18 | .text |
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c index 58ef08a5224b..b75353a2ec75 100644 --- a/arch/arm/mach-pxa/tavorevb.c +++ b/arch/arm/mach-pxa/tavorevb.c | |||
| @@ -22,9 +22,8 @@ | |||
| 22 | 22 | ||
| 23 | #include <asm/mach-types.h> | 23 | #include <asm/mach-types.h> |
| 24 | #include <asm/mach/arch.h> | 24 | #include <asm/mach/arch.h> |
| 25 | #include <mach/hardware.h> | 25 | |
| 26 | #include <mach/pxa3xx-regs.h> | 26 | #include <mach/pxa930.h> |
| 27 | #include <mach/mfp-pxa930.h> | ||
| 28 | #include <mach/pxafb.h> | 27 | #include <mach/pxafb.h> |
| 29 | #include <mach/pxa27x_keypad.h> | 28 | #include <mach/pxa27x_keypad.h> |
| 30 | 29 | ||
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index 95656a72268d..8eb3830fbb0b 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c | |||
| @@ -22,8 +22,7 @@ | |||
| 22 | #include <asm/div64.h> | 22 | #include <asm/div64.h> |
| 23 | #include <asm/mach/irq.h> | 23 | #include <asm/mach/irq.h> |
| 24 | #include <asm/mach/time.h> | 24 | #include <asm/mach/time.h> |
| 25 | #include <mach/hardware.h> | 25 | #include <mach/regs-ost.h> |
| 26 | #include <mach/pxa-regs.h> | ||
| 27 | 26 | ||
| 28 | /* | 27 | /* |
| 29 | * This is PXA's sched_clock implementation. This has a resolution | 28 | * This is PXA's sched_clock implementation. This has a resolution |
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c index 3332e5d0356c..6e8ade6ae339 100644 --- a/arch/arm/mach-pxa/tosa.c +++ b/arch/arm/mach-pxa/tosa.c | |||
| @@ -36,8 +36,8 @@ | |||
| 36 | 36 | ||
| 37 | #include <asm/setup.h> | 37 | #include <asm/setup.h> |
| 38 | #include <asm/mach-types.h> | 38 | #include <asm/mach-types.h> |
| 39 | #include <mach/pxa2xx-regs.h> | 39 | |
| 40 | #include <mach/mfp-pxa25x.h> | 40 | #include <mach/pxa25x.h> |
| 41 | #include <mach/reset.h> | 41 | #include <mach/reset.h> |
| 42 | #include <mach/irda.h> | 42 | #include <mach/irda.h> |
| 43 | #include <mach/i2c.h> | 43 | #include <mach/i2c.h> |
| @@ -876,10 +876,10 @@ static struct platform_device *devices[] __initdata = { | |||
| 876 | 876 | ||
| 877 | static void tosa_poweroff(void) | 877 | static void tosa_poweroff(void) |
| 878 | { | 878 | { |
| 879 | arm_machine_restart('g'); | 879 | arm_machine_restart('g', NULL); |
| 880 | } | 880 | } |
| 881 | 881 | ||
| 882 | static void tosa_restart(char mode) | 882 | static void tosa_restart(char mode, const char *cmd) |
| 883 | { | 883 | { |
| 884 | /* Bootloader magic for a reboot */ | 884 | /* Bootloader magic for a reboot */ |
| 885 | if((MSC0 & 0xffff0000) == 0x7ff00000) | 885 | if((MSC0 & 0xffff0000) == 0x7ff00000) |
| @@ -919,7 +919,7 @@ static void __init tosa_init(void) | |||
| 919 | pxa2xx_set_spi_info(2, &pxa_ssp_master_info); | 919 | pxa2xx_set_spi_info(2, &pxa_ssp_master_info); |
| 920 | spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); | 920 | spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); |
| 921 | 921 | ||
| 922 | clk_add_alias("CLK_CK3P6MI", &tc6393xb_device.dev, "GPIO11_CLK", NULL); | 922 | clk_add_alias("CLK_CK3P6MI", tc6393xb_device.name, "GPIO11_CLK", NULL); |
| 923 | 923 | ||
| 924 | platform_add_devices(devices, ARRAY_SIZE(devices)); | 924 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 925 | } | 925 | } |
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index a72e3add743c..f79c9cb70ae4 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c | |||
| @@ -39,10 +39,7 @@ | |||
| 39 | #include <asm/mach/irq.h> | 39 | #include <asm/mach/irq.h> |
| 40 | #include <asm/mach/flash.h> | 40 | #include <asm/mach/flash.h> |
| 41 | 41 | ||
| 42 | #include <mach/hardware.h> | 42 | #include <mach/pxa27x.h> |
| 43 | #include <mach/pxa-regs.h> | ||
| 44 | #include <mach/pxa2xx-regs.h> | ||
| 45 | #include <mach/mfp-pxa27x.h> | ||
| 46 | #include <mach/pxa2xx_spi.h> | 43 | #include <mach/pxa2xx_spi.h> |
| 47 | #include <mach/trizeps4.h> | 44 | #include <mach/trizeps4.h> |
| 48 | #include <mach/audio.h> | 45 | #include <mach/audio.h> |
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c index 4b3120dbc049..0e65344e9f53 100644 --- a/arch/arm/mach-pxa/viper.c +++ b/arch/arm/mach-pxa/viper.c | |||
| @@ -42,12 +42,9 @@ | |||
| 42 | #include <linux/mtd/partitions.h> | 42 | #include <linux/mtd/partitions.h> |
| 43 | #include <linux/mtd/physmap.h> | 43 | #include <linux/mtd/physmap.h> |
| 44 | 44 | ||
| 45 | #include <mach/pxa-regs.h> | 45 | #include <mach/pxa25x.h> |
| 46 | #include <mach/pxa2xx-regs.h> | ||
| 47 | #include <mach/bitfield.h> | ||
| 48 | #include <mach/audio.h> | 46 | #include <mach/audio.h> |
| 49 | #include <mach/pxafb.h> | 47 | #include <mach/pxafb.h> |
| 50 | #include <mach/mfp-pxa25x.h> | ||
| 51 | #include <mach/i2c.h> | 48 | #include <mach/i2c.h> |
| 52 | #include <mach/viper.h> | 49 | #include <mach/viper.h> |
| 53 | 50 | ||
| @@ -956,7 +953,7 @@ static struct map_desc viper_io_desc[] __initdata = { | |||
| 956 | }, | 953 | }, |
| 957 | { | 954 | { |
| 958 | .virtual = VIPER_PC104IO_BASE, | 955 | .virtual = VIPER_PC104IO_BASE, |
| 959 | .pfn = __phys_to_pfn(_PCMCIA1IO), | 956 | .pfn = __phys_to_pfn(0x30000000), |
| 960 | .length = 0x00800000, | 957 | .length = 0x00800000, |
| 961 | .type = MT_DEVICE, | 958 | .type = MT_DEVICE, |
| 962 | }, | 959 | }, |
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c index 46538885a58a..c1f73205d078 100644 --- a/arch/arm/mach-pxa/zylonite_pxa300.c +++ b/arch/arm/mach-pxa/zylonite_pxa300.c | |||
| @@ -18,9 +18,9 @@ | |||
| 18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
| 19 | #include <linux/i2c.h> | 19 | #include <linux/i2c.h> |
| 20 | #include <linux/i2c/pca953x.h> | 20 | #include <linux/i2c/pca953x.h> |
| 21 | #include <linux/gpio.h> | ||
| 21 | 22 | ||
| 22 | #include <asm/gpio.h> | 23 | #include <mach/pxa300.h> |
| 23 | #include <mach/mfp-pxa300.h> | ||
| 24 | #include <mach/i2c.h> | 24 | #include <mach/i2c.h> |
| 25 | #include <mach/zylonite.h> | 25 | #include <mach/zylonite.h> |
| 26 | 26 | ||
diff --git a/arch/arm/mach-pxa/zylonite_pxa320.c b/arch/arm/mach-pxa/zylonite_pxa320.c index 28e4e623780b..4e1c488c6906 100644 --- a/arch/arm/mach-pxa/zylonite_pxa320.c +++ b/arch/arm/mach-pxa/zylonite_pxa320.c | |||
| @@ -18,7 +18,7 @@ | |||
| 18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
| 19 | #include <linux/gpio.h> | 19 | #include <linux/gpio.h> |
| 20 | 20 | ||
| 21 | #include <mach/mfp-pxa320.h> | 21 | #include <mach/pxa320.h> |
| 22 | #include <mach/zylonite.h> | 22 | #include <mach/zylonite.h> |
| 23 | 23 | ||
| 24 | #include "generic.h" | 24 | #include "generic.h" |
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index ad911854eb4c..b6ec10627776 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig | |||
| @@ -35,6 +35,7 @@ config MACH_REALVIEW_PB11MP | |||
| 35 | bool "Support RealView/PB11MPCore platform" | 35 | bool "Support RealView/PB11MPCore platform" |
| 36 | select CPU_V6 | 36 | select CPU_V6 |
| 37 | select ARM_GIC | 37 | select ARM_GIC |
| 38 | select HAVE_PATA_PLATFORM | ||
| 38 | help | 39 | help |
| 39 | Include support for the ARM(R) RealView MPCore Platform Baseboard. | 40 | Include support for the ARM(R) RealView MPCore Platform Baseboard. |
| 40 | PB11MPCore is a platform with an on-board ARM11MPCore and has | 41 | PB11MPCore is a platform with an on-board ARM11MPCore and has |
| @@ -51,6 +52,7 @@ config MACH_REALVIEW_PBA8 | |||
| 51 | bool "Support RealView/PB-A8 platform" | 52 | bool "Support RealView/PB-A8 platform" |
| 52 | select CPU_V7 | 53 | select CPU_V7 |
| 53 | select ARM_GIC | 54 | select ARM_GIC |
| 55 | select HAVE_PATA_PLATFORM | ||
| 54 | help | 56 | help |
| 55 | Include support for the ARM(R) RealView Cortex-A8 Platform Baseboard. | 57 | Include support for the ARM(R) RealView Cortex-A8 Platform Baseboard. |
| 56 | PB-A8 is a platform with an on-board Cortex-A8 and has support for | 58 | PB-A8 is a platform with an on-board Cortex-A8 and has support for |
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index bd2aa4f16141..d6766685cfc7 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | #include <linux/clockchips.h> | 29 | #include <linux/clockchips.h> |
| 30 | #include <linux/io.h> | 30 | #include <linux/io.h> |
| 31 | #include <linux/smc911x.h> | 31 | #include <linux/smc911x.h> |
| 32 | #include <linux/ata_platform.h> | ||
| 32 | 33 | ||
| 33 | #include <asm/clkdev.h> | 34 | #include <asm/clkdev.h> |
| 34 | #include <asm/system.h> | 35 | #include <asm/system.h> |
| @@ -150,6 +151,44 @@ int realview_eth_register(const char *name, struct resource *res) | |||
| 150 | return platform_device_register(&realview_eth_device); | 151 | return platform_device_register(&realview_eth_device); |
| 151 | } | 152 | } |
| 152 | 153 | ||
| 154 | struct platform_device realview_usb_device = { | ||
| 155 | .name = "isp1760", | ||
| 156 | .num_resources = 2, | ||
| 157 | }; | ||
| 158 | |||
| 159 | int realview_usb_register(struct resource *res) | ||
| 160 | { | ||
| 161 | realview_usb_device.resource = res; | ||
| 162 | return platform_device_register(&realview_usb_device); | ||
| 163 | } | ||
| 164 | |||
| 165 | static struct pata_platform_info pata_platform_data = { | ||
| 166 | .ioport_shift = 1, | ||
| 167 | }; | ||
| 168 | |||
| 169 | static struct resource pata_resources[] = { | ||
| 170 | [0] = { | ||
| 171 | .start = REALVIEW_CF_BASE, | ||
| 172 | .end = REALVIEW_CF_BASE + 0xff, | ||
| 173 | .flags = IORESOURCE_MEM, | ||
| 174 | }, | ||
| 175 | [1] = { | ||
| 176 | .start = REALVIEW_CF_BASE + 0x100, | ||
| 177 | .end = REALVIEW_CF_BASE + SZ_4K - 1, | ||
| 178 | .flags = IORESOURCE_MEM, | ||
| 179 | }, | ||
| 180 | }; | ||
| 181 | |||
| 182 | struct platform_device realview_cf_device = { | ||
| 183 | .name = "pata_platform", | ||
| 184 | .id = -1, | ||
| 185 | .num_resources = ARRAY_SIZE(pata_resources), | ||
| 186 | .resource = pata_resources, | ||
| 187 | .dev = { | ||
| 188 | .platform_data = &pata_platform_data, | ||
| 189 | }, | ||
| 190 | }; | ||
| 191 | |||
| 153 | static struct resource realview_i2c_resource = { | 192 | static struct resource realview_i2c_resource = { |
| 154 | .start = REALVIEW_I2C_BASE, | 193 | .start = REALVIEW_I2C_BASE, |
| 155 | .end = REALVIEW_I2C_BASE + SZ_4K - 1, | 194 | .end = REALVIEW_I2C_BASE + SZ_4K - 1, |
| @@ -158,11 +197,25 @@ static struct resource realview_i2c_resource = { | |||
| 158 | 197 | ||
| 159 | struct platform_device realview_i2c_device = { | 198 | struct platform_device realview_i2c_device = { |
| 160 | .name = "versatile-i2c", | 199 | .name = "versatile-i2c", |
| 161 | .id = -1, | 200 | .id = 0, |
| 162 | .num_resources = 1, | 201 | .num_resources = 1, |
| 163 | .resource = &realview_i2c_resource, | 202 | .resource = &realview_i2c_resource, |
| 164 | }; | 203 | }; |
| 165 | 204 | ||
| 205 | static struct i2c_board_info realview_i2c_board_info[] = { | ||
| 206 | { | ||
| 207 | I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1), | ||
| 208 | .type = "ds1338", | ||
| 209 | }, | ||
| 210 | }; | ||
| 211 | |||
| 212 | static int __init realview_i2c_init(void) | ||
| 213 | { | ||
| 214 | return i2c_register_board_info(0, realview_i2c_board_info, | ||
| 215 | ARRAY_SIZE(realview_i2c_board_info)); | ||
| 216 | } | ||
| 217 | arch_initcall(realview_i2c_init); | ||
| 218 | |||
| 166 | #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET) | 219 | #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET) |
| 167 | 220 | ||
| 168 | static unsigned int realview_mmc_status(struct device *dev) | 221 | static unsigned int realview_mmc_status(struct device *dev) |
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h index 44269b162d49..21c08637683b 100644 --- a/arch/arm/mach-realview/core.h +++ b/arch/arm/mach-realview/core.h | |||
| @@ -45,6 +45,7 @@ static struct amba_device name##_device = { \ | |||
| 45 | } | 45 | } |
| 46 | 46 | ||
| 47 | extern struct platform_device realview_flash_device; | 47 | extern struct platform_device realview_flash_device; |
| 48 | extern struct platform_device realview_cf_device; | ||
| 48 | extern struct platform_device realview_i2c_device; | 49 | extern struct platform_device realview_i2c_device; |
| 49 | extern struct mmc_platform_data realview_mmc0_plat_data; | 50 | extern struct mmc_platform_data realview_mmc0_plat_data; |
| 50 | extern struct mmc_platform_data realview_mmc1_plat_data; | 51 | extern struct mmc_platform_data realview_mmc1_plat_data; |
| @@ -62,5 +63,6 @@ extern void realview_leds_event(led_event_t ledevt); | |||
| 62 | extern void realview_timer_init(unsigned int timer_irq); | 63 | extern void realview_timer_init(unsigned int timer_irq); |
| 63 | extern int realview_flash_register(struct resource *res, u32 num); | 64 | extern int realview_flash_register(struct resource *res, u32 num); |
| 64 | extern int realview_eth_register(const char *name, struct resource *res); | 65 | extern int realview_eth_register(const char *name, struct resource *res); |
| 66 | extern int realview_usb_register(struct resource *res); | ||
| 65 | 67 | ||
| 66 | #endif | 68 | #endif |
diff --git a/arch/arm/mach-realview/include/mach/board-pba8.h b/arch/arm/mach-realview/include/mach/board-pba8.h index c8bed8f58bab..307f97b16e5b 100644 --- a/arch/arm/mach-realview/include/mach/board-pba8.h +++ b/arch/arm/mach-realview/include/mach/board-pba8.h | |||
| @@ -45,8 +45,6 @@ | |||
| 45 | #define REALVIEW_PBA8_DMC_BASE 0x100E0000 /* DMC configuration */ | 45 | #define REALVIEW_PBA8_DMC_BASE 0x100E0000 /* DMC configuration */ |
| 46 | #define REALVIEW_PBA8_SMC_BASE 0x100E1000 /* SMC configuration */ | 46 | #define REALVIEW_PBA8_SMC_BASE 0x100E1000 /* SMC configuration */ |
| 47 | #define REALVIEW_PBA8_CAN_BASE 0x100E2000 /* CAN bus */ | 47 | #define REALVIEW_PBA8_CAN_BASE 0x100E2000 /* CAN bus */ |
| 48 | #define REALVIEW_PBA8_CF_BASE 0x18000000 /* Compact flash */ | ||
| 49 | #define REALVIEW_PBA8_CF_MEM_BASE 0x18003000 /* SMC for Compact flash */ | ||
| 50 | #define REALVIEW_PBA8_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */ | 48 | #define REALVIEW_PBA8_GIC_CPU_BASE 0x1E000000 /* Generic interrupt controller CPU interface */ |
| 51 | #define REALVIEW_PBA8_FLASH0_BASE 0x40000000 | 49 | #define REALVIEW_PBA8_FLASH0_BASE 0x40000000 |
| 52 | #define REALVIEW_PBA8_FLASH0_SIZE SZ_64M | 50 | #define REALVIEW_PBA8_FLASH0_SIZE SZ_64M |
diff --git a/arch/arm/mach-realview/include/mach/platform.h b/arch/arm/mach-realview/include/mach/platform.h index 793a3a332712..c8f50835fed2 100644 --- a/arch/arm/mach-realview/include/mach/platform.h +++ b/arch/arm/mach-realview/include/mach/platform.h | |||
| @@ -204,6 +204,12 @@ | |||
| 204 | #define REALVIEW_LT_BASE 0x80000000 /* Logic Tile expansion */ | 204 | #define REALVIEW_LT_BASE 0x80000000 /* Logic Tile expansion */ |
| 205 | 205 | ||
| 206 | /* | 206 | /* |
| 207 | * CompactFlash | ||
| 208 | */ | ||
| 209 | #define REALVIEW_CF_BASE 0x18000000 /* CompactFlash */ | ||
| 210 | #define REALVIEW_CF_MEM_BASE 0x18003000 /* SMC for CompactFlash */ | ||
| 211 | |||
| 212 | /* | ||
| 207 | * Disk on Chip | 213 | * Disk on Chip |
| 208 | */ | 214 | */ |
| 209 | #define REALVIEW_DOC_BASE 0x2C000000 | 215 | #define REALVIEW_DOC_BASE 0x2C000000 |
diff --git a/arch/arm/mach-realview/include/mach/system.h b/arch/arm/mach-realview/include/mach/system.h index a2f61c78adbf..1a15a441e027 100644 --- a/arch/arm/mach-realview/include/mach/system.h +++ b/arch/arm/mach-realview/include/mach/system.h | |||
| @@ -34,7 +34,7 @@ static inline void arch_idle(void) | |||
| 34 | cpu_do_idle(); | 34 | cpu_do_idle(); |
| 35 | } | 35 | } |
| 36 | 36 | ||
| 37 | static inline void arch_reset(char mode) | 37 | static inline void arch_reset(char mode, const char *cmd) |
| 38 | { | 38 | { |
| 39 | void __iomem *hdr_ctrl = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET; | 39 | void __iomem *hdr_ctrl = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_RESETCTL_OFFSET; |
| 40 | unsigned int val; | 40 | unsigned int val; |
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c index bed39ed97613..c20fbef122b3 100644 --- a/arch/arm/mach-realview/realview_eb.c +++ b/arch/arm/mach-realview/realview_eb.c | |||
| @@ -264,6 +264,19 @@ static int eth_device_register(void) | |||
| 264 | return realview_eth_register(name, realview_eb_eth_resources); | 264 | return realview_eth_register(name, realview_eb_eth_resources); |
| 265 | } | 265 | } |
| 266 | 266 | ||
| 267 | static struct resource realview_eb_isp1761_resources[] = { | ||
| 268 | [0] = { | ||
| 269 | .start = REALVIEW_EB_USB_BASE, | ||
| 270 | .end = REALVIEW_EB_USB_BASE + SZ_128K - 1, | ||
| 271 | .flags = IORESOURCE_MEM, | ||
| 272 | }, | ||
| 273 | [1] = { | ||
| 274 | .start = IRQ_EB_USB, | ||
| 275 | .end = IRQ_EB_USB, | ||
| 276 | .flags = IORESOURCE_IRQ, | ||
| 277 | }, | ||
| 278 | }; | ||
| 279 | |||
| 267 | static void __init gic_init_irq(void) | 280 | static void __init gic_init_irq(void) |
| 268 | { | 281 | { |
| 269 | if (core_tile_eb11mp() || core_tile_a9mp()) { | 282 | if (core_tile_eb11mp() || core_tile_a9mp()) { |
| @@ -323,6 +336,8 @@ static void realview_eb11mp_fixup(void) | |||
| 323 | /* platform devices */ | 336 | /* platform devices */ |
| 324 | realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH; | 337 | realview_eb_eth_resources[1].start = IRQ_EB11MP_ETH; |
| 325 | realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH; | 338 | realview_eb_eth_resources[1].end = IRQ_EB11MP_ETH; |
| 339 | realview_eb_isp1761_resources[1].start = IRQ_EB11MP_USB; | ||
| 340 | realview_eb_isp1761_resources[1].end = IRQ_EB11MP_USB; | ||
| 326 | } | 341 | } |
| 327 | 342 | ||
| 328 | static void __init realview_eb_timer_init(void) | 343 | static void __init realview_eb_timer_init(void) |
| @@ -366,6 +381,7 @@ static void __init realview_eb_init(void) | |||
| 366 | realview_flash_register(&realview_eb_flash_resource, 1); | 381 | realview_flash_register(&realview_eb_flash_resource, 1); |
| 367 | platform_device_register(&realview_i2c_device); | 382 | platform_device_register(&realview_i2c_device); |
| 368 | eth_device_register(); | 383 | eth_device_register(); |
| 384 | realview_usb_register(realview_eb_isp1761_resources); | ||
| 369 | 385 | ||
| 370 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | 386 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { |
| 371 | struct amba_device *d = amba_devs[i]; | 387 | struct amba_device *d = amba_devs[i]; |
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c index 8f0683c22140..a64b84a7a3df 100644 --- a/arch/arm/mach-realview/realview_pb1176.c +++ b/arch/arm/mach-realview/realview_pb1176.c | |||
| @@ -222,6 +222,19 @@ static struct resource realview_pb1176_smsc911x_resources[] = { | |||
| 222 | }, | 222 | }, |
| 223 | }; | 223 | }; |
| 224 | 224 | ||
| 225 | static struct resource realview_pb1176_isp1761_resources[] = { | ||
| 226 | [0] = { | ||
| 227 | .start = REALVIEW_PB1176_USB_BASE, | ||
| 228 | .end = REALVIEW_PB1176_USB_BASE + SZ_128K - 1, | ||
| 229 | .flags = IORESOURCE_MEM, | ||
| 230 | }, | ||
| 231 | [1] = { | ||
| 232 | .start = IRQ_PB1176_USB, | ||
| 233 | .end = IRQ_PB1176_USB, | ||
| 234 | .flags = IORESOURCE_IRQ, | ||
| 235 | }, | ||
| 236 | }; | ||
| 237 | |||
| 225 | static void __init gic_init_irq(void) | 238 | static void __init gic_init_irq(void) |
| 226 | { | 239 | { |
| 227 | /* ARM1176 DevChip GIC, primary */ | 240 | /* ARM1176 DevChip GIC, primary */ |
| @@ -260,6 +273,8 @@ static void __init realview_pb1176_init(void) | |||
| 260 | 273 | ||
| 261 | realview_flash_register(&realview_pb1176_flash_resource, 1); | 274 | realview_flash_register(&realview_pb1176_flash_resource, 1); |
| 262 | realview_eth_register(NULL, realview_pb1176_smsc911x_resources); | 275 | realview_eth_register(NULL, realview_pb1176_smsc911x_resources); |
| 276 | platform_device_register(&realview_i2c_device); | ||
| 277 | realview_usb_register(realview_pb1176_isp1761_resources); | ||
| 263 | 278 | ||
| 264 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | 279 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { |
| 265 | struct amba_device *d = amba_devs[i]; | 280 | struct amba_device *d = amba_devs[i]; |
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c index 3ebdb2dadd6f..ea1e60eca359 100644 --- a/arch/arm/mach-realview/realview_pb11mp.c +++ b/arch/arm/mach-realview/realview_pb11mp.c | |||
| @@ -230,31 +230,19 @@ static struct resource realview_pb11mp_smsc911x_resources[] = { | |||
| 230 | }, | 230 | }, |
| 231 | }; | 231 | }; |
| 232 | 232 | ||
| 233 | struct resource realview_pb11mp_cf_resources[] = { | 233 | static struct resource realview_pb11mp_isp1761_resources[] = { |
| 234 | [0] = { | 234 | [0] = { |
| 235 | .start = REALVIEW_PB11MP_CF_BASE, | 235 | .start = REALVIEW_PB11MP_USB_BASE, |
| 236 | .end = REALVIEW_PB11MP_CF_BASE + SZ_4K - 1, | 236 | .end = REALVIEW_PB11MP_USB_BASE + SZ_128K - 1, |
| 237 | .flags = IORESOURCE_MEM, | 237 | .flags = IORESOURCE_MEM, |
| 238 | }, | 238 | }, |
| 239 | [1] = { | 239 | [1] = { |
| 240 | .start = REALVIEW_PB11MP_CF_MEM_BASE, | 240 | .start = IRQ_TC11MP_USB, |
| 241 | .end = REALVIEW_PB11MP_CF_MEM_BASE + SZ_4K - 1, | 241 | .end = IRQ_TC11MP_USB, |
| 242 | .flags = IORESOURCE_MEM, | ||
| 243 | }, | ||
| 244 | [2] = { | ||
| 245 | .start = -1, /* FIXME: Find correct irq */ | ||
| 246 | .end = -1, | ||
| 247 | .flags = IORESOURCE_IRQ, | 242 | .flags = IORESOURCE_IRQ, |
| 248 | }, | 243 | }, |
| 249 | }; | 244 | }; |
| 250 | 245 | ||
| 251 | struct platform_device realview_pb11mp_cf_device = { | ||
| 252 | .name = "compactflash", | ||
| 253 | .id = 0, | ||
| 254 | .num_resources = ARRAY_SIZE(realview_pb11mp_cf_resources), | ||
| 255 | .resource = realview_pb11mp_cf_resources, | ||
| 256 | }; | ||
| 257 | |||
| 258 | static void __init gic_init_irq(void) | 246 | static void __init gic_init_irq(void) |
| 259 | { | 247 | { |
| 260 | unsigned int pldctrl; | 248 | unsigned int pldctrl; |
| @@ -308,7 +296,8 @@ static void __init realview_pb11mp_init(void) | |||
| 308 | ARRAY_SIZE(realview_pb11mp_flash_resource)); | 296 | ARRAY_SIZE(realview_pb11mp_flash_resource)); |
| 309 | realview_eth_register(NULL, realview_pb11mp_smsc911x_resources); | 297 | realview_eth_register(NULL, realview_pb11mp_smsc911x_resources); |
| 310 | platform_device_register(&realview_i2c_device); | 298 | platform_device_register(&realview_i2c_device); |
| 311 | platform_device_register(&realview_pb11mp_cf_device); | 299 | platform_device_register(&realview_cf_device); |
| 300 | realview_usb_register(realview_pb11mp_isp1761_resources); | ||
| 312 | 301 | ||
| 313 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | 302 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { |
| 314 | struct amba_device *d = amba_devs[i]; | 303 | struct amba_device *d = amba_devs[i]; |
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c index 34c94435d2d8..d6ac1eb86576 100644 --- a/arch/arm/mach-realview/realview_pba8.c +++ b/arch/arm/mach-realview/realview_pba8.c | |||
| @@ -221,31 +221,19 @@ static struct resource realview_pba8_smsc911x_resources[] = { | |||
| 221 | }, | 221 | }, |
| 222 | }; | 222 | }; |
| 223 | 223 | ||
| 224 | struct resource realview_pba8_cf_resources[] = { | 224 | static struct resource realview_pba8_isp1761_resources[] = { |
| 225 | [0] = { | 225 | [0] = { |
| 226 | .start = REALVIEW_PBA8_CF_BASE, | 226 | .start = REALVIEW_PBA8_USB_BASE, |
| 227 | .end = REALVIEW_PBA8_CF_BASE + SZ_4K - 1, | 227 | .end = REALVIEW_PBA8_USB_BASE + SZ_128K - 1, |
| 228 | .flags = IORESOURCE_MEM, | 228 | .flags = IORESOURCE_MEM, |
| 229 | }, | 229 | }, |
| 230 | [1] = { | 230 | [1] = { |
| 231 | .start = REALVIEW_PBA8_CF_MEM_BASE, | 231 | .start = IRQ_PBA8_USB, |
| 232 | .end = REALVIEW_PBA8_CF_MEM_BASE + SZ_4K - 1, | 232 | .end = IRQ_PBA8_USB, |
| 233 | .flags = IORESOURCE_MEM, | ||
| 234 | }, | ||
| 235 | [2] = { | ||
| 236 | .start = -1, /* FIXME: Find correct irq */ | ||
| 237 | .end = -1, | ||
| 238 | .flags = IORESOURCE_IRQ, | 233 | .flags = IORESOURCE_IRQ, |
| 239 | }, | 234 | }, |
| 240 | }; | 235 | }; |
| 241 | 236 | ||
| 242 | struct platform_device realview_pba8_cf_device = { | ||
| 243 | .name = "compactflash", | ||
| 244 | .id = 0, | ||
| 245 | .num_resources = ARRAY_SIZE(realview_pba8_cf_resources), | ||
| 246 | .resource = realview_pba8_cf_resources, | ||
| 247 | }; | ||
| 248 | |||
| 249 | static void __init gic_init_irq(void) | 237 | static void __init gic_init_irq(void) |
| 250 | { | 238 | { |
| 251 | /* ARM PB-A8 on-board GIC */ | 239 | /* ARM PB-A8 on-board GIC */ |
| @@ -276,7 +264,8 @@ static void __init realview_pba8_init(void) | |||
| 276 | ARRAY_SIZE(realview_pba8_flash_resource)); | 264 | ARRAY_SIZE(realview_pba8_flash_resource)); |
| 277 | realview_eth_register(NULL, realview_pba8_smsc911x_resources); | 265 | realview_eth_register(NULL, realview_pba8_smsc911x_resources); |
| 278 | platform_device_register(&realview_i2c_device); | 266 | platform_device_register(&realview_i2c_device); |
| 279 | platform_device_register(&realview_pba8_cf_device); | 267 | platform_device_register(&realview_cf_device); |
| 268 | realview_usb_register(realview_pba8_isp1761_resources); | ||
| 280 | 269 | ||
| 281 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | 270 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { |
| 282 | struct amba_device *d = amba_devs[i]; | 271 | struct amba_device *d = amba_devs[i]; |
diff --git a/arch/arm/mach-rpc/dma.c b/arch/arm/mach-rpc/dma.c index 7958a30f8932..c47d974d52bd 100644 --- a/arch/arm/mach-rpc/dma.c +++ b/arch/arm/mach-rpc/dma.c | |||
| @@ -26,6 +26,16 @@ | |||
| 26 | #include <asm/mach/dma.h> | 26 | #include <asm/mach/dma.h> |
| 27 | #include <asm/hardware/iomd.h> | 27 | #include <asm/hardware/iomd.h> |
| 28 | 28 | ||
| 29 | struct iomd_dma { | ||
| 30 | struct dma_struct dma; | ||
| 31 | unsigned int state; | ||
| 32 | unsigned long base; /* Controller base address */ | ||
| 33 | int irq; /* Controller IRQ */ | ||
| 34 | struct scatterlist cur_sg; /* Current controller buffer */ | ||
| 35 | dma_addr_t dma_addr; | ||
| 36 | unsigned int dma_len; | ||
| 37 | }; | ||
| 38 | |||
| 29 | #if 0 | 39 | #if 0 |
| 30 | typedef enum { | 40 | typedef enum { |
| 31 | dma_size_8 = 1, | 41 | dma_size_8 = 1, |
| @@ -44,15 +54,15 @@ typedef enum { | |||
| 44 | #define CR (IOMD_IO0CR - IOMD_IO0CURA) | 54 | #define CR (IOMD_IO0CR - IOMD_IO0CURA) |
| 45 | #define ST (IOMD_IO0ST - IOMD_IO0CURA) | 55 | #define ST (IOMD_IO0ST - IOMD_IO0CURA) |
| 46 | 56 | ||
| 47 | static void iomd_get_next_sg(struct scatterlist *sg, dma_t *dma) | 57 | static void iomd_get_next_sg(struct scatterlist *sg, struct iomd_dma *idma) |
| 48 | { | 58 | { |
| 49 | unsigned long end, offset, flags = 0; | 59 | unsigned long end, offset, flags = 0; |
| 50 | 60 | ||
| 51 | if (dma->sg) { | 61 | if (idma->dma.sg) { |
| 52 | sg->dma_address = dma->sg->dma_address; | 62 | sg->dma_address = idma->dma_addr; |
| 53 | offset = sg->dma_address & ~PAGE_MASK; | 63 | offset = sg->dma_address & ~PAGE_MASK; |
| 54 | 64 | ||
| 55 | end = offset + dma->sg->length; | 65 | end = offset + idma->dma_len; |
| 56 | 66 | ||
| 57 | if (end > PAGE_SIZE) | 67 | if (end > PAGE_SIZE) |
| 58 | end = PAGE_SIZE; | 68 | end = PAGE_SIZE; |
| @@ -62,15 +72,17 @@ static void iomd_get_next_sg(struct scatterlist *sg, dma_t *dma) | |||
| 62 | 72 | ||
| 63 | sg->length = end - TRANSFER_SIZE; | 73 | sg->length = end - TRANSFER_SIZE; |
| 64 | 74 | ||
| 65 | dma->sg->length -= end - offset; | 75 | idma->dma_len -= end - offset; |
| 66 | dma->sg->dma_address += end - offset; | 76 | idma->dma_addr += end - offset; |
| 67 | 77 | ||
| 68 | if (dma->sg->length == 0) { | 78 | if (idma->dma_len == 0) { |
| 69 | if (dma->sgcount > 1) { | 79 | if (idma->dma.sgcount > 1) { |
| 70 | dma->sg++; | 80 | idma->dma.sg = sg_next(idma->dma.sg); |
| 71 | dma->sgcount--; | 81 | idma->dma_addr = idma->dma.sg->dma_address; |
| 82 | idma->dma_len = idma->dma.sg->length; | ||
| 83 | idma->dma.sgcount--; | ||
| 72 | } else { | 84 | } else { |
| 73 | dma->sg = NULL; | 85 | idma->dma.sg = NULL; |
| 74 | flags |= DMA_END_S; | 86 | flags |= DMA_END_S; |
| 75 | } | 87 | } |
| 76 | } | 88 | } |
| @@ -85,8 +97,8 @@ static void iomd_get_next_sg(struct scatterlist *sg, dma_t *dma) | |||
| 85 | 97 | ||
| 86 | static irqreturn_t iomd_dma_handle(int irq, void *dev_id) | 98 | static irqreturn_t iomd_dma_handle(int irq, void *dev_id) |
| 87 | { | 99 | { |
| 88 | dma_t *dma = (dma_t *)dev_id; | 100 | struct iomd_dma *idma = dev_id; |
| 89 | unsigned long base = dma->dma_base; | 101 | unsigned long base = idma->base; |
| 90 | 102 | ||
| 91 | do { | 103 | do { |
| 92 | unsigned int status; | 104 | unsigned int status; |
| @@ -95,93 +107,99 @@ static irqreturn_t iomd_dma_handle(int irq, void *dev_id) | |||
| 95 | if (!(status & DMA_ST_INT)) | 107 | if (!(status & DMA_ST_INT)) |
| 96 | return IRQ_HANDLED; | 108 | return IRQ_HANDLED; |
| 97 | 109 | ||
| 98 | if ((dma->state ^ status) & DMA_ST_AB) | 110 | if ((idma->state ^ status) & DMA_ST_AB) |
| 99 | iomd_get_next_sg(&dma->cur_sg, dma); | 111 | iomd_get_next_sg(&idma->cur_sg, idma); |
| 100 | 112 | ||
| 101 | switch (status & (DMA_ST_OFL | DMA_ST_AB)) { | 113 | switch (status & (DMA_ST_OFL | DMA_ST_AB)) { |
| 102 | case DMA_ST_OFL: /* OIA */ | 114 | case DMA_ST_OFL: /* OIA */ |
| 103 | case DMA_ST_AB: /* .IB */ | 115 | case DMA_ST_AB: /* .IB */ |
| 104 | iomd_writel(dma->cur_sg.dma_address, base + CURA); | 116 | iomd_writel(idma->cur_sg.dma_address, base + CURA); |
| 105 | iomd_writel(dma->cur_sg.length, base + ENDA); | 117 | iomd_writel(idma->cur_sg.length, base + ENDA); |
| 106 | dma->state = DMA_ST_AB; | 118 | idma->state = DMA_ST_AB; |
| 107 | break; | 119 | break; |
| 108 | 120 | ||
| 109 | case DMA_ST_OFL | DMA_ST_AB: /* OIB */ | 121 | case DMA_ST_OFL | DMA_ST_AB: /* OIB */ |
| 110 | case 0: /* .IA */ | 122 | case 0: /* .IA */ |
| 111 | iomd_writel(dma->cur_sg.dma_address, base + CURB); | 123 | iomd_writel(idma->cur_sg.dma_address, base + CURB); |
| 112 | iomd_writel(dma->cur_sg.length, base + ENDB); | 124 | iomd_writel(idma->cur_sg.length, base + ENDB); |
| 113 | dma->state = 0; | 125 | idma->state = 0; |
| 114 | break; | 126 | break; |
| 115 | } | 127 | } |
| 116 | 128 | ||
| 117 | if (status & DMA_ST_OFL && | 129 | if (status & DMA_ST_OFL && |
| 118 | dma->cur_sg.length == (DMA_END_S|DMA_END_L)) | 130 | idma->cur_sg.length == (DMA_END_S|DMA_END_L)) |
| 119 | break; | 131 | break; |
| 120 | } while (1); | 132 | } while (1); |
| 121 | 133 | ||
| 122 | dma->state = ~DMA_ST_AB; | 134 | idma->state = ~DMA_ST_AB; |
| 123 | disable_irq(irq); | 135 | disable_irq(irq); |
| 124 | 136 | ||
| 125 | return IRQ_HANDLED; | 137 | return IRQ_HANDLED; |
| 126 | } | 138 | } |
| 127 | 139 | ||
| 128 | static int iomd_request_dma(dmach_t channel, dma_t *dma) | 140 | static int iomd_request_dma(unsigned int chan, dma_t *dma) |
| 129 | { | 141 | { |
| 130 | return request_irq(dma->dma_irq, iomd_dma_handle, | 142 | struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); |
| 131 | IRQF_DISABLED, dma->device_id, dma); | 143 | |
| 144 | return request_irq(idma->irq, iomd_dma_handle, | ||
| 145 | IRQF_DISABLED, idma->dma.device_id, idma); | ||
| 132 | } | 146 | } |
| 133 | 147 | ||
| 134 | static void iomd_free_dma(dmach_t channel, dma_t *dma) | 148 | static void iomd_free_dma(unsigned int chan, dma_t *dma) |
| 135 | { | 149 | { |
| 136 | free_irq(dma->dma_irq, dma); | 150 | struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); |
| 151 | |||
| 152 | free_irq(idma->irq, idma); | ||
| 137 | } | 153 | } |
| 138 | 154 | ||
| 139 | static void iomd_enable_dma(dmach_t channel, dma_t *dma) | 155 | static void iomd_enable_dma(unsigned int chan, dma_t *dma) |
| 140 | { | 156 | { |
| 141 | unsigned long dma_base = dma->dma_base; | 157 | struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); |
| 158 | unsigned long dma_base = idma->base; | ||
| 142 | unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E; | 159 | unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E; |
| 143 | 160 | ||
| 144 | if (dma->invalid) { | 161 | if (idma->dma.invalid) { |
| 145 | dma->invalid = 0; | 162 | idma->dma.invalid = 0; |
| 146 | 163 | ||
| 147 | /* | 164 | /* |
| 148 | * Cope with ISA-style drivers which expect cache | 165 | * Cope with ISA-style drivers which expect cache |
| 149 | * coherence. | 166 | * coherence. |
| 150 | */ | 167 | */ |
| 151 | if (!dma->sg) { | 168 | if (!idma->dma.sg) { |
| 152 | dma->sg = &dma->buf; | 169 | idma->dma.sg = &idma->dma.buf; |
| 153 | dma->sgcount = 1; | 170 | idma->dma.sgcount = 1; |
| 154 | dma->buf.length = dma->count; | 171 | idma->dma.buf.length = idma->dma.count; |
| 155 | dma->buf.dma_address = dma_map_single(NULL, | 172 | idma->dma.buf.dma_address = dma_map_single(NULL, |
| 156 | dma->addr, dma->count, | 173 | idma->dma.addr, idma->dma.count, |
| 157 | dma->dma_mode == DMA_MODE_READ ? | 174 | idma->dma.dma_mode == DMA_MODE_READ ? |
| 158 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | 175 | DMA_FROM_DEVICE : DMA_TO_DEVICE); |
| 159 | } | 176 | } |
| 160 | 177 | ||
| 161 | iomd_writeb(DMA_CR_C, dma_base + CR); | 178 | iomd_writeb(DMA_CR_C, dma_base + CR); |
| 162 | dma->state = DMA_ST_AB; | 179 | idma->state = DMA_ST_AB; |
| 163 | } | 180 | } |
| 164 | 181 | ||
| 165 | if (dma->dma_mode == DMA_MODE_READ) | 182 | if (idma->dma.dma_mode == DMA_MODE_READ) |
| 166 | ctrl |= DMA_CR_D; | 183 | ctrl |= DMA_CR_D; |
| 167 | 184 | ||
| 168 | iomd_writeb(ctrl, dma_base + CR); | 185 | iomd_writeb(ctrl, dma_base + CR); |
| 169 | enable_irq(dma->dma_irq); | 186 | enable_irq(idma->irq); |
| 170 | } | 187 | } |
| 171 | 188 | ||
| 172 | static void iomd_disable_dma(dmach_t channel, dma_t *dma) | 189 | static void iomd_disable_dma(unsigned int chan, dma_t *dma) |
| 173 | { | 190 | { |
| 174 | unsigned long dma_base = dma->dma_base; | 191 | struct iomd_dma *idma = container_of(dma, struct iomd_dma, dma); |
| 192 | unsigned long dma_base = idma->base; | ||
| 175 | unsigned long flags; | 193 | unsigned long flags; |
| 176 | 194 | ||
| 177 | local_irq_save(flags); | 195 | local_irq_save(flags); |
| 178 | if (dma->state != ~DMA_ST_AB) | 196 | if (idma->state != ~DMA_ST_AB) |
| 179 | disable_irq(dma->dma_irq); | 197 | disable_irq(idma->irq); |
| 180 | iomd_writeb(0, dma_base + CR); | 198 | iomd_writeb(0, dma_base + CR); |
| 181 | local_irq_restore(flags); | 199 | local_irq_restore(flags); |
| 182 | } | 200 | } |
| 183 | 201 | ||
| 184 | static int iomd_set_dma_speed(dmach_t channel, dma_t *dma, int cycle) | 202 | static int iomd_set_dma_speed(unsigned int chan, dma_t *dma, int cycle) |
| 185 | { | 203 | { |
| 186 | int tcr, speed; | 204 | int tcr, speed; |
| 187 | 205 | ||
| @@ -197,7 +215,7 @@ static int iomd_set_dma_speed(dmach_t channel, dma_t *dma, int cycle) | |||
| 197 | tcr = iomd_readb(IOMD_DMATCR); | 215 | tcr = iomd_readb(IOMD_DMATCR); |
| 198 | speed &= 3; | 216 | speed &= 3; |
| 199 | 217 | ||
| 200 | switch (channel) { | 218 | switch (chan) { |
| 201 | case DMA_0: | 219 | case DMA_0: |
| 202 | tcr = (tcr & ~0x03) | speed; | 220 | tcr = (tcr & ~0x03) | speed; |
| 203 | break; | 221 | break; |
| @@ -236,16 +254,22 @@ static struct fiq_handler fh = { | |||
| 236 | .name = "floppydma" | 254 | .name = "floppydma" |
| 237 | }; | 255 | }; |
| 238 | 256 | ||
| 239 | static void floppy_enable_dma(dmach_t channel, dma_t *dma) | 257 | struct floppy_dma { |
| 258 | struct dma_struct dma; | ||
| 259 | unsigned int fiq; | ||
| 260 | }; | ||
| 261 | |||
| 262 | static void floppy_enable_dma(unsigned int chan, dma_t *dma) | ||
| 240 | { | 263 | { |
| 264 | struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma); | ||
| 241 | void *fiqhandler_start; | 265 | void *fiqhandler_start; |
| 242 | unsigned int fiqhandler_length; | 266 | unsigned int fiqhandler_length; |
| 243 | struct pt_regs regs; | 267 | struct pt_regs regs; |
| 244 | 268 | ||
| 245 | if (dma->sg) | 269 | if (fdma->dma.sg) |
| 246 | BUG(); | 270 | BUG(); |
| 247 | 271 | ||
| 248 | if (dma->dma_mode == DMA_MODE_READ) { | 272 | if (fdma->dma.dma_mode == DMA_MODE_READ) { |
| 249 | extern unsigned char floppy_fiqin_start, floppy_fiqin_end; | 273 | extern unsigned char floppy_fiqin_start, floppy_fiqin_end; |
| 250 | fiqhandler_start = &floppy_fiqin_start; | 274 | fiqhandler_start = &floppy_fiqin_start; |
| 251 | fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start; | 275 | fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start; |
| @@ -255,8 +279,8 @@ static void floppy_enable_dma(dmach_t channel, dma_t *dma) | |||
| 255 | fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start; | 279 | fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start; |
| 256 | } | 280 | } |
| 257 | 281 | ||
| 258 | regs.ARM_r9 = dma->count; | 282 | regs.ARM_r9 = fdma->dma.count; |
| 259 | regs.ARM_r10 = (unsigned long)dma->addr; | 283 | regs.ARM_r10 = (unsigned long)fdma->dma.addr; |
| 260 | regs.ARM_fp = (unsigned long)FLOPPYDMA_BASE; | 284 | regs.ARM_fp = (unsigned long)FLOPPYDMA_BASE; |
| 261 | 285 | ||
| 262 | if (claim_fiq(&fh)) { | 286 | if (claim_fiq(&fh)) { |
| @@ -266,16 +290,17 @@ static void floppy_enable_dma(dmach_t channel, dma_t *dma) | |||
| 266 | 290 | ||
| 267 | set_fiq_handler(fiqhandler_start, fiqhandler_length); | 291 | set_fiq_handler(fiqhandler_start, fiqhandler_length); |
| 268 | set_fiq_regs(®s); | 292 | set_fiq_regs(®s); |
| 269 | enable_fiq(dma->dma_irq); | 293 | enable_fiq(fdma->fiq); |
| 270 | } | 294 | } |
| 271 | 295 | ||
| 272 | static void floppy_disable_dma(dmach_t channel, dma_t *dma) | 296 | static void floppy_disable_dma(unsigned int chan, dma_t *dma) |
| 273 | { | 297 | { |
| 274 | disable_fiq(dma->dma_irq); | 298 | struct floppy_dma *fdma = container_of(dma, struct floppy_dma, dma); |
| 299 | disable_fiq(fdma->fiq); | ||
| 275 | release_fiq(&fh); | 300 | release_fiq(&fh); |
| 276 | } | 301 | } |
| 277 | 302 | ||
| 278 | static int floppy_get_residue(dmach_t channel, dma_t *dma) | 303 | static int floppy_get_residue(unsigned int chan, dma_t *dma) |
| 279 | { | 304 | { |
| 280 | struct pt_regs regs; | 305 | struct pt_regs regs; |
| 281 | get_fiq_regs(®s); | 306 | get_fiq_regs(®s); |
| @@ -292,7 +317,7 @@ static struct dma_ops floppy_dma_ops = { | |||
| 292 | /* | 317 | /* |
| 293 | * This is virtual DMA - we don't need anything here. | 318 | * This is virtual DMA - we don't need anything here. |
| 294 | */ | 319 | */ |
| 295 | static void sound_enable_disable_dma(dmach_t channel, dma_t *dma) | 320 | static void sound_enable_disable_dma(unsigned int chan, dma_t *dma) |
| 296 | { | 321 | { |
| 297 | } | 322 | } |
| 298 | 323 | ||
| @@ -302,8 +327,24 @@ static struct dma_ops sound_dma_ops = { | |||
| 302 | .disable = sound_enable_disable_dma, | 327 | .disable = sound_enable_disable_dma, |
| 303 | }; | 328 | }; |
| 304 | 329 | ||
| 305 | void __init arch_dma_init(dma_t *dma) | 330 | static struct iomd_dma iomd_dma[6]; |
| 331 | |||
| 332 | static struct floppy_dma floppy_dma = { | ||
| 333 | .dma = { | ||
| 334 | .d_ops = &floppy_dma_ops, | ||
| 335 | }, | ||
| 336 | .fiq = FIQ_FLOPPYDATA, | ||
| 337 | }; | ||
| 338 | |||
| 339 | static dma_t sound_dma = { | ||
| 340 | .d_ops = &sound_dma_ops, | ||
| 341 | }; | ||
| 342 | |||
| 343 | static int __init rpc_dma_init(void) | ||
| 306 | { | 344 | { |
| 345 | unsigned int i; | ||
| 346 | int ret; | ||
| 347 | |||
| 307 | iomd_writeb(0, IOMD_IO0CR); | 348 | iomd_writeb(0, IOMD_IO0CR); |
| 308 | iomd_writeb(0, IOMD_IO1CR); | 349 | iomd_writeb(0, IOMD_IO1CR); |
| 309 | iomd_writeb(0, IOMD_IO2CR); | 350 | iomd_writeb(0, IOMD_IO2CR); |
| @@ -311,31 +352,39 @@ void __init arch_dma_init(dma_t *dma) | |||
| 311 | 352 | ||
| 312 | iomd_writeb(0xa0, IOMD_DMATCR); | 353 | iomd_writeb(0xa0, IOMD_DMATCR); |
| 313 | 354 | ||
| 314 | dma[DMA_0].dma_base = IOMD_IO0CURA; | ||
| 315 | dma[DMA_0].dma_irq = IRQ_DMA0; | ||
| 316 | dma[DMA_0].d_ops = &iomd_dma_ops; | ||
| 317 | dma[DMA_1].dma_base = IOMD_IO1CURA; | ||
| 318 | dma[DMA_1].dma_irq = IRQ_DMA1; | ||
| 319 | dma[DMA_1].d_ops = &iomd_dma_ops; | ||
| 320 | dma[DMA_2].dma_base = IOMD_IO2CURA; | ||
| 321 | dma[DMA_2].dma_irq = IRQ_DMA2; | ||
| 322 | dma[DMA_2].d_ops = &iomd_dma_ops; | ||
| 323 | dma[DMA_3].dma_base = IOMD_IO3CURA; | ||
| 324 | dma[DMA_3].dma_irq = IRQ_DMA3; | ||
| 325 | dma[DMA_3].d_ops = &iomd_dma_ops; | ||
| 326 | dma[DMA_S0].dma_base = IOMD_SD0CURA; | ||
| 327 | dma[DMA_S0].dma_irq = IRQ_DMAS0; | ||
| 328 | dma[DMA_S0].d_ops = &iomd_dma_ops; | ||
| 329 | dma[DMA_S1].dma_base = IOMD_SD1CURA; | ||
| 330 | dma[DMA_S1].dma_irq = IRQ_DMAS1; | ||
| 331 | dma[DMA_S1].d_ops = &iomd_dma_ops; | ||
| 332 | dma[DMA_VIRTUAL_FLOPPY].dma_irq = FIQ_FLOPPYDATA; | ||
| 333 | dma[DMA_VIRTUAL_FLOPPY].d_ops = &floppy_dma_ops; | ||
| 334 | dma[DMA_VIRTUAL_SOUND].d_ops = &sound_dma_ops; | ||
| 335 | |||
| 336 | /* | 355 | /* |
| 337 | * Setup DMA channels 2,3 to be for podules | 356 | * Setup DMA channels 2,3 to be for podules |
| 338 | * and channels 0,1 for internal devices | 357 | * and channels 0,1 for internal devices |
| 339 | */ | 358 | */ |
| 340 | iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT); | 359 | iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT); |
| 360 | |||
| 361 | iomd_dma[DMA_0].base = IOMD_IO0CURA; | ||
| 362 | iomd_dma[DMA_0].irq = IRQ_DMA0; | ||
| 363 | iomd_dma[DMA_1].base = IOMD_IO1CURA; | ||
| 364 | iomd_dma[DMA_1].irq = IRQ_DMA1; | ||
| 365 | iomd_dma[DMA_2].base = IOMD_IO2CURA; | ||
| 366 | iomd_dma[DMA_2].irq = IRQ_DMA2; | ||
| 367 | iomd_dma[DMA_3].base = IOMD_IO3CURA; | ||
| 368 | iomd_dma[DMA_3].irq = IRQ_DMA3; | ||
| 369 | iomd_dma[DMA_S0].base = IOMD_SD0CURA; | ||
| 370 | iomd_dma[DMA_S0].irq = IRQ_DMAS0; | ||
| 371 | iomd_dma[DMA_S1].base = IOMD_SD1CURA; | ||
| 372 | iomd_dma[DMA_S1].irq = IRQ_DMAS1; | ||
| 373 | |||
| 374 | for (i = DMA_0; i <= DMA_S1; i++) { | ||
| 375 | iomd_dma[i].dma.d_ops = &iomd_dma_ops; | ||
| 376 | |||
| 377 | ret = isa_dma_add(i, &iomd_dma[i].dma); | ||
| 378 | if (ret) | ||
| 379 | printk("IOMDDMA%u: unable to register: %d\n", i, ret); | ||
| 380 | } | ||
| 381 | |||
| 382 | ret = isa_dma_add(DMA_VIRTUAL_FLOPPY, &floppy_dma.dma); | ||
| 383 | if (ret) | ||
| 384 | printk("IOMDFLOPPY: unable to register: %d\n", ret); | ||
| 385 | ret = isa_dma_add(DMA_VIRTUAL_SOUND, &sound_dma); | ||
| 386 | if (ret) | ||
| 387 | printk("IOMDSOUND: unable to register: %d\n", ret); | ||
| 388 | return 0; | ||
| 341 | } | 389 | } |
| 390 | core_initcall(rpc_dma_init); | ||
diff --git a/arch/arm/mach-rpc/include/mach/isa-dma.h b/arch/arm/mach-rpc/include/mach/isa-dma.h index bad720548587..67bfc6719c34 100644 --- a/arch/arm/mach-rpc/include/mach/isa-dma.h +++ b/arch/arm/mach-rpc/include/mach/isa-dma.h | |||
| @@ -23,5 +23,7 @@ | |||
| 23 | 23 | ||
| 24 | #define DMA_FLOPPY DMA_VIRTUAL_FLOPPY | 24 | #define DMA_FLOPPY DMA_VIRTUAL_FLOPPY |
| 25 | 25 | ||
| 26 | #define IOMD_DMA_BOUNDARY (PAGE_SIZE - 1) | ||
| 27 | |||
| 26 | #endif /* _ASM_ARCH_DMA_H */ | 28 | #endif /* _ASM_ARCH_DMA_H */ |
| 27 | 29 | ||
diff --git a/arch/arm/mach-rpc/include/mach/system.h b/arch/arm/mach-rpc/include/mach/system.h index bd7268ba17e2..45c7b935dc45 100644 --- a/arch/arm/mach-rpc/include/mach/system.h +++ b/arch/arm/mach-rpc/include/mach/system.h | |||
| @@ -16,7 +16,7 @@ static inline void arch_idle(void) | |||
| 16 | cpu_do_idle(); | 16 | cpu_do_idle(); |
| 17 | } | 17 | } |
| 18 | 18 | ||
| 19 | static inline void arch_reset(char mode) | 19 | static inline void arch_reset(char mode, const char *cmd) |
| 20 | { | 20 | { |
| 21 | iomd_writeb(0, IOMD_ROMCR0); | 21 | iomd_writeb(0, IOMD_ROMCR0); |
| 22 | 22 | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h new file mode 100644 index 000000000000..ce1ec69806a1 --- /dev/null +++ b/arch/arm/mach-s3c2410/include/mach/gpio-nrs.h | |||
| @@ -0,0 +1,23 @@ | |||
| 1 | /* arch/arm/mach-s3c2410/include/mach/gpio-nrs.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2008 Simtec Electronics | ||
| 4 | * http://armlinux.simtec.co.uk/ | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * S3C2410 - GPIO bank numbering | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) | ||
| 15 | |||
| 16 | #define S3C2410_GPIO_BANKA (32*0) | ||
| 17 | #define S3C2410_GPIO_BANKB (32*1) | ||
| 18 | #define S3C2410_GPIO_BANKC (32*2) | ||
| 19 | #define S3C2410_GPIO_BANKD (32*3) | ||
| 20 | #define S3C2410_GPIO_BANKE (32*4) | ||
| 21 | #define S3C2410_GPIO_BANKF (32*5) | ||
| 22 | #define S3C2410_GPIO_BANKG (32*6) | ||
| 23 | #define S3C2410_GPIO_BANKH (32*7) | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h index 00476a573bbe..51a88cf9526b 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio.h | |||
| @@ -23,3 +23,6 @@ | |||
| 23 | #define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA) | 23 | #define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA) |
| 24 | 24 | ||
| 25 | #include <asm-generic/gpio.h> | 25 | #include <asm-generic/gpio.h> |
| 26 | #include <mach/gpio-nrs.h> | ||
| 27 | |||
| 28 | #define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32) | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h index 49efce8cd4a7..2a2384ffa7b1 100644 --- a/arch/arm/mach-s3c2410/include/mach/irqs.h +++ b/arch/arm/mach-s3c2410/include/mach/irqs.h | |||
| @@ -80,7 +80,7 @@ | |||
| 80 | #define IRQ_EINT22 S3C2410_IRQ(50) | 80 | #define IRQ_EINT22 S3C2410_IRQ(50) |
| 81 | #define IRQ_EINT23 S3C2410_IRQ(51) | 81 | #define IRQ_EINT23 S3C2410_IRQ(51) |
| 82 | 82 | ||
| 83 | 83 | #define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4) | |
| 84 | #define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) | 84 | #define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x))) |
| 85 | 85 | ||
| 86 | #define IRQ_LCD_FIFO S3C2410_IRQ(52) | 86 | #define IRQ_LCD_FIFO S3C2410_IRQ(52) |
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h index 321077613067..35a03df473fc 100644 --- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h +++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h | |||
| @@ -14,16 +14,7 @@ | |||
| 14 | #ifndef __ASM_ARCH_REGS_GPIO_H | 14 | #ifndef __ASM_ARCH_REGS_GPIO_H |
| 15 | #define __ASM_ARCH_REGS_GPIO_H | 15 | #define __ASM_ARCH_REGS_GPIO_H |
| 16 | 16 | ||
| 17 | #define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) | 17 | #include <mach/gpio-nrs.h> |
| 18 | |||
| 19 | #define S3C2410_GPIO_BANKA (32*0) | ||
| 20 | #define S3C2410_GPIO_BANKB (32*1) | ||
| 21 | #define S3C2410_GPIO_BANKC (32*2) | ||
| 22 | #define S3C2410_GPIO_BANKD (32*3) | ||
| 23 | #define S3C2410_GPIO_BANKE (32*4) | ||
| 24 | #define S3C2410_GPIO_BANKF (32*5) | ||
| 25 | #define S3C2410_GPIO_BANKG (32*6) | ||
| 26 | #define S3C2410_GPIO_BANKH (32*7) | ||
| 27 | 18 | ||
| 28 | #ifdef CONFIG_CPU_S3C2400 | 19 | #ifdef CONFIG_CPU_S3C2400 |
| 29 | #define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) | 20 | #define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) |
diff --git a/arch/arm/mach-s3c2410/include/mach/system-reset.h b/arch/arm/mach-s3c2410/include/mach/system-reset.h index 7613d0a384ba..b8687f71c304 100644 --- a/arch/arm/mach-s3c2410/include/mach/system-reset.h +++ b/arch/arm/mach-s3c2410/include/mach/system-reset.h | |||
| @@ -22,7 +22,7 @@ | |||
| 22 | extern void (*s3c24xx_reset_hook)(void); | 22 | extern void (*s3c24xx_reset_hook)(void); |
| 23 | 23 | ||
| 24 | static void | 24 | static void |
| 25 | arch_reset(char mode) | 25 | arch_reset(char mode, const char *cmd) |
| 26 | { | 26 | { |
| 27 | struct clk *wdtclk; | 27 | struct clk *wdtclk; |
| 28 | 28 | ||
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c index 821a1668c3ac..7a7c4da4c256 100644 --- a/arch/arm/mach-s3c2410/mach-h1940.c +++ b/arch/arm/mach-s3c2410/mach-h1940.c | |||
| @@ -203,7 +203,7 @@ static void __init h1940_map_io(void) | |||
| 203 | #ifdef CONFIG_PM_H1940 | 203 | #ifdef CONFIG_PM_H1940 |
| 204 | memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); | 204 | memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); |
| 205 | #endif | 205 | #endif |
| 206 | s3c2410_pm_init(); | 206 | s3c_pm_init(); |
| 207 | } | 207 | } |
| 208 | 208 | ||
| 209 | static void __init h1940_init_irq(void) | 209 | static void __init h1940_init_irq(void) |
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c index 9678a53ceeb1..9f1ba9b63f70 100644 --- a/arch/arm/mach-s3c2410/mach-qt2410.c +++ b/arch/arm/mach-s3c2410/mach-qt2410.c | |||
| @@ -355,7 +355,7 @@ static void __init qt2410_machine_init(void) | |||
| 355 | s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); | 355 | s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT); |
| 356 | 356 | ||
| 357 | platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); | 357 | platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices)); |
| 358 | s3c2410_pm_init(); | 358 | s3c_pm_init(); |
| 359 | } | 359 | } |
| 360 | 360 | ||
| 361 | MACHINE_START(QT2410, "QT2410") | 361 | MACHINE_START(QT2410, "QT2410") |
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c index a6970f613192..87fc481d92d4 100644 --- a/arch/arm/mach-s3c2410/pm.c +++ b/arch/arm/mach-s3c2410/pm.c | |||
| @@ -37,21 +37,14 @@ | |||
| 37 | #include <plat/cpu.h> | 37 | #include <plat/cpu.h> |
| 38 | #include <plat/pm.h> | 38 | #include <plat/pm.h> |
| 39 | 39 | ||
| 40 | #ifdef CONFIG_S3C2410_PM_DEBUG | ||
| 41 | extern void pm_dbg(const char *fmt, ...); | ||
| 42 | #define DBG(fmt...) pm_dbg(fmt) | ||
| 43 | #else | ||
| 44 | #define DBG(fmt...) printk(KERN_DEBUG fmt) | ||
| 45 | #endif | ||
| 46 | |||
| 47 | static void s3c2410_pm_prepare(void) | 40 | static void s3c2410_pm_prepare(void) |
| 48 | { | 41 | { |
| 49 | /* ensure at least GSTATUS3 has the resume address */ | 42 | /* ensure at least GSTATUS3 has the resume address */ |
| 50 | 43 | ||
| 51 | __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3); | 44 | __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3); |
| 52 | 45 | ||
| 53 | DBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); | 46 | S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); |
| 54 | DBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); | 47 | S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); |
| 55 | 48 | ||
| 56 | if (machine_is_h1940()) { | 49 | if (machine_is_h1940()) { |
| 57 | void *base = phys_to_virt(H1940_SUSPEND_CHECK); | 50 | void *base = phys_to_virt(H1940_SUSPEND_CHECK); |
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c index ecddbbb34832..72c266aee141 100644 --- a/arch/arm/mach-s3c2412/mach-jive.c +++ b/arch/arm/mach-s3c2412/mach-jive.c | |||
| @@ -494,7 +494,7 @@ static int jive_pm_suspend(struct sys_device *sd, pm_message_t state) | |||
| 494 | * correct address to resume from. */ | 494 | * correct address to resume from. */ |
| 495 | 495 | ||
| 496 | __raw_writel(0x2BED, S3C2412_INFORM0); | 496 | __raw_writel(0x2BED, S3C2412_INFORM0); |
| 497 | __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1); | 497 | __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); |
| 498 | 498 | ||
| 499 | return 0; | 499 | return 0; |
| 500 | } | 500 | } |
| @@ -630,7 +630,7 @@ static void __init jive_machine_init(void) | |||
| 630 | 630 | ||
| 631 | /* initialise the power management now we've setup everything. */ | 631 | /* initialise the power management now we've setup everything. */ |
| 632 | 632 | ||
| 633 | s3c2410_pm_init(); | 633 | s3c_pm_init(); |
| 634 | 634 | ||
| 635 | s3c_device_nand.dev.platform_data = &jive_nand_info; | 635 | s3c_device_nand.dev.platform_data = &jive_nand_info; |
| 636 | 636 | ||
diff --git a/arch/arm/mach-s3c2412/pm.c b/arch/arm/mach-s3c2412/pm.c index 217e9e4ed45f..c9cfe40e21f6 100644 --- a/arch/arm/mach-s3c2412/pm.c +++ b/arch/arm/mach-s3c2412/pm.c | |||
| @@ -85,7 +85,7 @@ static struct sleep_save s3c2412_sleep[] = { | |||
| 85 | 85 | ||
| 86 | static int s3c2412_pm_suspend(struct sys_device *dev, pm_message_t state) | 86 | static int s3c2412_pm_suspend(struct sys_device *dev, pm_message_t state) |
| 87 | { | 87 | { |
| 88 | s3c2410_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); | 88 | s3c_pm_do_save(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); |
| 89 | return 0; | 89 | return 0; |
| 90 | } | 90 | } |
| 91 | 91 | ||
| @@ -98,7 +98,7 @@ static int s3c2412_pm_resume(struct sys_device *dev) | |||
| 98 | tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE; | 98 | tmp |= S3C2412_PWRCFG_STANDBYWFI_IDLE; |
| 99 | __raw_writel(tmp, S3C2412_PWRCFG); | 99 | __raw_writel(tmp, S3C2412_PWRCFG); |
| 100 | 100 | ||
| 101 | s3c2410_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); | 101 | s3c_pm_do_restore(s3c2412_sleep, ARRAY_SIZE(s3c2412_sleep)); |
| 102 | return 0; | 102 | return 0; |
| 103 | } | 103 | } |
| 104 | 104 | ||
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c index 12d378f84ad2..bc8d8d1ebd1a 100644 --- a/arch/arm/mach-s3c2440/mach-rx3715.c +++ b/arch/arm/mach-s3c2440/mach-rx3715.c | |||
| @@ -203,7 +203,7 @@ static void __init rx3715_init_machine(void) | |||
| 203 | #ifdef CONFIG_PM_H1940 | 203 | #ifdef CONFIG_PM_H1940 |
| 204 | memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); | 204 | memcpy(phys_to_virt(H1940_SUSPEND_RESUMEAT), h1940_pm_return, 1024); |
| 205 | #endif | 205 | #endif |
| 206 | s3c2410_pm_init(); | 206 | s3c_pm_init(); |
| 207 | 207 | ||
| 208 | s3c24xx_fb_set_platdata(&rx3715_fb_info); | 208 | s3c24xx_fb_set_platdata(&rx3715_fb_info); |
| 209 | platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices)); | 209 | platform_add_devices(rx3715_devices, ARRAY_SIZE(rx3715_devices)); |
diff --git a/arch/arm/mach-s3c24a0/include/mach/irqs.h b/arch/arm/mach-s3c24a0/include/mach/irqs.h index ae8c0e359783..83ce2a7a9dae 100644 --- a/arch/arm/mach-s3c24a0/include/mach/irqs.h +++ b/arch/arm/mach-s3c24a0/include/mach/irqs.h | |||
| @@ -70,6 +70,8 @@ | |||
| 70 | #define IRQ_EINT17 S3C2410_IRQ(49) | 70 | #define IRQ_EINT17 S3C2410_IRQ(49) |
| 71 | #define IRQ_EINT18 S3C2410_IRQ(50) | 71 | #define IRQ_EINT18 S3C2410_IRQ(50) |
| 72 | 72 | ||
| 73 | #define IRQ_EINT_BIT(x) ((x) - IRQ_EINT00) | ||
| 74 | |||
| 73 | /* SUB IRQS */ | 75 | /* SUB IRQS */ |
| 74 | #define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */ | 76 | #define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */ |
| 75 | #define IRQ_S3CUART_TX0 S3C2410_IRQ(52) | 77 | #define IRQ_S3CUART_TX0 S3C2410_IRQ(52) |
diff --git a/arch/arm/mach-s3c6400/include/mach/system.h b/arch/arm/mach-s3c6400/include/mach/system.h index 652bbc403f0b..090cfd969bc7 100644 --- a/arch/arm/mach-s3c6400/include/mach/system.h +++ b/arch/arm/mach-s3c6400/include/mach/system.h | |||
| @@ -16,7 +16,7 @@ static void arch_idle(void) | |||
| 16 | /* nothing here yet */ | 16 | /* nothing here yet */ |
| 17 | } | 17 | } |
| 18 | 18 | ||
| 19 | static void arch_reset(char mode) | 19 | static void arch_reset(char mode, const char *cmd) |
| 20 | { | 20 | { |
| 21 | /* nothing here yet */ | 21 | /* nothing here yet */ |
| 22 | } | 22 | } |
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig index f99d9013905f..81ffff7ed498 100644 --- a/arch/arm/mach-sa1100/Kconfig +++ b/arch/arm/mach-sa1100/Kconfig | |||
| @@ -71,19 +71,9 @@ config SA1100_H3600 | |||
| 71 | <http://www.handhelds.org/Compaq/index.html#iPAQ_H3600> | 71 | <http://www.handhelds.org/Compaq/index.html#iPAQ_H3600> |
| 72 | <http://www.compaq.com/products/handhelds/pocketpc/> | 72 | <http://www.compaq.com/products/handhelds/pocketpc/> |
| 73 | 73 | ||
| 74 | config SA1100_H3800 | ||
| 75 | bool "Compaq iPAQ H3800" | ||
| 76 | help | ||
| 77 | Say Y here if you intend to run this kernel on the Compaq iPAQ H3800 | ||
| 78 | series handheld computer. Information about this machine and the | ||
| 79 | Linux port to this machine can be found at: | ||
| 80 | |||
| 81 | <http://www.handhelds.org/Compaq/index.html#iPAQ_H3800> | ||
| 82 | <http://www.compaq.com/products/handhelds/pocketpc/> | ||
| 83 | |||
| 84 | config SA1100_H3XXX | 74 | config SA1100_H3XXX |
| 85 | bool | 75 | bool |
| 86 | depends on SA1100_H3100 || SA1100_H3600 || SA1100_H3800 | 76 | depends on SA1100_H3100 || SA1100_H3600 |
| 87 | default y | 77 | default y |
| 88 | 78 | ||
| 89 | config SA1100_BADGE4 | 79 | config SA1100_BADGE4 |
| @@ -157,15 +147,6 @@ config SA1100_SSP | |||
| 157 | This isn't for audio support, but for attached sensors and | 147 | This isn't for audio support, but for attached sensors and |
| 158 | other devices, eg for BadgePAD 4 sensor support. | 148 | other devices, eg for BadgePAD 4 sensor support. |
| 159 | 149 | ||
| 160 | config H3600_SLEEVE | ||
| 161 | tristate "Compaq iPAQ Handheld sleeve support" | ||
| 162 | depends on SA1100_H3100 || SA1100_H3600 | ||
| 163 | help | ||
| 164 | Choose this option to enable support for extension packs (sleeves) | ||
| 165 | for the Compaq iPAQ H3XXX series of handheld computers. This option | ||
| 166 | is required for the CF, PCMCIA, Bluetooth and GSM/GPRS extension | ||
| 167 | packs. | ||
| 168 | |||
| 169 | endmenu | 150 | endmenu |
| 170 | 151 | ||
| 171 | endif | 152 | endif |
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c index 2052eb88c961..bbf2ebcc3066 100644 --- a/arch/arm/mach-sa1100/collie.c +++ b/arch/arm/mach-sa1100/collie.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <linux/mtd/mtd.h> | 25 | #include <linux/mtd/mtd.h> |
| 26 | #include <linux/mtd/partitions.h> | 26 | #include <linux/mtd/partitions.h> |
| 27 | #include <linux/timer.h> | 27 | #include <linux/timer.h> |
| 28 | #include <linux/gpio.h> | ||
| 28 | 29 | ||
| 29 | #include <mach/hardware.h> | 30 | #include <mach/hardware.h> |
| 30 | #include <asm/mach-types.h> | 31 | #include <asm/mach-types.h> |
| @@ -145,7 +146,8 @@ static struct locomo_driver collie_uart_driver = { | |||
| 145 | .remove = collie_uart_remove, | 146 | .remove = collie_uart_remove, |
| 146 | }; | 147 | }; |
| 147 | 148 | ||
| 148 | static int __init collie_uart_init(void) { | 149 | static int __init collie_uart_init(void) |
| 150 | { | ||
| 149 | return locomo_driver_register(&collie_uart_driver); | 151 | return locomo_driver_register(&collie_uart_driver); |
| 150 | } | 152 | } |
| 151 | device_initcall(collie_uart_init); | 153 | device_initcall(collie_uart_init); |
| @@ -195,18 +197,34 @@ static struct mtd_partition collie_partitions[] = { | |||
| 195 | } | 197 | } |
| 196 | }; | 198 | }; |
| 197 | 199 | ||
| 200 | static int collie_flash_init(void) | ||
| 201 | { | ||
| 202 | int rc = gpio_request(COLLIE_GPIO_VPEN, "flash Vpp enable"); | ||
| 203 | if (rc) | ||
| 204 | return rc; | ||
| 205 | |||
| 206 | rc = gpio_direction_output(COLLIE_GPIO_VPEN, 1); | ||
| 207 | if (rc) | ||
| 208 | gpio_free(COLLIE_GPIO_VPEN); | ||
| 209 | |||
| 210 | return rc; | ||
| 211 | } | ||
| 212 | |||
| 198 | static void collie_set_vpp(int vpp) | 213 | static void collie_set_vpp(int vpp) |
| 199 | { | 214 | { |
| 200 | write_scoop_reg(&colliescoop_device.dev, SCOOP_GPCR, read_scoop_reg(&colliescoop_device.dev, SCOOP_GPCR) | COLLIE_SCP_VPEN); | 215 | gpio_set_value(COLLIE_GPIO_VPEN, vpp); |
| 201 | if (vpp) | 216 | } |
| 202 | write_scoop_reg(&colliescoop_device.dev, SCOOP_GPWR, read_scoop_reg(&colliescoop_device.dev, SCOOP_GPWR) | COLLIE_SCP_VPEN); | 217 | |
| 203 | else | 218 | static void collie_flash_exit(void) |
| 204 | write_scoop_reg(&colliescoop_device.dev, SCOOP_GPWR, read_scoop_reg(&colliescoop_device.dev, SCOOP_GPWR) & ~COLLIE_SCP_VPEN); | 219 | { |
| 220 | gpio_free(COLLIE_GPIO_VPEN); | ||
| 205 | } | 221 | } |
| 206 | 222 | ||
| 207 | static struct flash_platform_data collie_flash_data = { | 223 | static struct flash_platform_data collie_flash_data = { |
| 208 | .map_name = "cfi_probe", | 224 | .map_name = "cfi_probe", |
| 225 | .init = collie_flash_init, | ||
| 209 | .set_vpp = collie_set_vpp, | 226 | .set_vpp = collie_set_vpp, |
| 227 | .exit = collie_flash_exit, | ||
| 210 | .parts = collie_partitions, | 228 | .parts = collie_partitions, |
| 211 | .nr_parts = ARRAY_SIZE(collie_partitions), | 229 | .nr_parts = ARRAY_SIZE(collie_partitions), |
| 212 | }; | 230 | }; |
diff --git a/arch/arm/mach-sa1100/collie_pm.c b/arch/arm/mach-sa1100/collie_pm.c index b39307f26b52..444f266ecc06 100644 --- a/arch/arm/mach-sa1100/collie_pm.c +++ b/arch/arm/mach-sa1100/collie_pm.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/interrupt.h> | 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/device.h> | 23 | #include <linux/device.h> |
| 24 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/gpio.h> | ||
| 25 | 26 | ||
| 26 | #include <asm/irq.h> | 27 | #include <asm/irq.h> |
| 27 | #include <mach/hardware.h> | 28 | #include <mach/hardware.h> |
| @@ -58,6 +59,9 @@ static void collie_charger_init(void) | |||
| 58 | return; | 59 | return; |
| 59 | } | 60 | } |
| 60 | 61 | ||
| 62 | gpio_request(COLLIE_GPIO_CHARGE_ON, "charge on"); | ||
| 63 | gpio_direction_output(COLLIE_GPIO_CHARGE_ON, 1); | ||
| 64 | |||
| 61 | ucb1x00_io_set_dir(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON | COLLIE_TC35143_GPIO_TMP_ON | | 65 | ucb1x00_io_set_dir(ucb, 0, COLLIE_TC35143_GPIO_MBAT_ON | COLLIE_TC35143_GPIO_TMP_ON | |
| 62 | COLLIE_TC35143_GPIO_BBAT_ON); | 66 | COLLIE_TC35143_GPIO_BBAT_ON); |
| 63 | return; | 67 | return; |
| @@ -73,17 +77,11 @@ static void collie_measure_temp(int on) | |||
| 73 | 77 | ||
| 74 | static void collie_charge(int on) | 78 | static void collie_charge(int on) |
| 75 | { | 79 | { |
| 76 | extern struct platform_device colliescoop_device; | ||
| 77 | |||
| 78 | /* Zaurus seems to contain LTC1731; it should know when to | 80 | /* Zaurus seems to contain LTC1731; it should know when to |
| 79 | * stop charging itself, so setting charge on should be | 81 | * stop charging itself, so setting charge on should be |
| 80 | * relatively harmless (as long as it is not done too often). | 82 | * relatively harmless (as long as it is not done too often). |
| 81 | */ | 83 | */ |
| 82 | if (on) { | 84 | gpio_set_value(COLLIE_GPIO_CHARGE_ON, on); |
| 83 | set_scoop_gpio(&colliescoop_device.dev, COLLIE_SCP_CHARGE_ON); | ||
| 84 | } else { | ||
| 85 | reset_scoop_gpio(&colliescoop_device.dev, COLLIE_SCP_CHARGE_ON); | ||
| 86 | } | ||
| 87 | } | 85 | } |
| 88 | 86 | ||
| 89 | static void collie_discharge(int on) | 87 | static void collie_discharge(int on) |
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c index af25a78d705d..0eb2f159578b 100644 --- a/arch/arm/mach-sa1100/h3600.c +++ b/arch/arm/mach-sa1100/h3600.c | |||
| @@ -42,19 +42,12 @@ | |||
| 42 | #include <asm/mach/serial_sa1100.h> | 42 | #include <asm/mach/serial_sa1100.h> |
| 43 | 43 | ||
| 44 | #include <mach/h3600.h> | 44 | #include <mach/h3600.h> |
| 45 | |||
| 46 | #if defined (CONFIG_SA1100_H3600) || defined (CONFIG_SA1100_H3100) | ||
| 47 | #include <mach/h3600_gpio.h> | 45 | #include <mach/h3600_gpio.h> |
| 48 | #endif | ||
| 49 | |||
| 50 | #ifdef CONFIG_SA1100_H3800 | ||
| 51 | #include <mach/h3600_asic.h> | ||
| 52 | #endif | ||
| 53 | 46 | ||
| 54 | #include "generic.h" | 47 | #include "generic.h" |
| 55 | 48 | ||
| 56 | struct ipaq_model_ops ipaq_model_ops; | 49 | void (*assign_h3600_egpio)(enum ipaq_egpio_type x, int level); |
| 57 | EXPORT_SYMBOL(ipaq_model_ops); | 50 | EXPORT_SYMBOL(assign_h3600_egpio); |
| 58 | 51 | ||
| 59 | static struct mtd_partition h3xxx_partitions[] = { | 52 | static struct mtd_partition h3xxx_partitions[] = { |
| 60 | { | 53 | { |
| @@ -63,41 +56,9 @@ static struct mtd_partition h3xxx_partitions[] = { | |||
| 63 | .offset = 0, | 56 | .offset = 0, |
| 64 | .mask_flags = MTD_WRITEABLE, /* force read-only */ | 57 | .mask_flags = MTD_WRITEABLE, /* force read-only */ |
| 65 | }, { | 58 | }, { |
| 66 | #ifdef CONFIG_MTD_2PARTS_IPAQ | 59 | .name = "H3XXX rootfs", |
| 67 | .name = "H3XXX root jffs2", | ||
| 68 | .size = MTDPART_SIZ_FULL, | 60 | .size = MTDPART_SIZ_FULL, |
| 69 | .offset = 0x00040000, | 61 | .offset = 0x00040000, |
| 70 | #else | ||
| 71 | .name = "H3XXX kernel", | ||
| 72 | .size = 0x00080000, | ||
| 73 | .offset = 0x00040000, | ||
| 74 | }, { | ||
| 75 | .name = "H3XXX params", | ||
| 76 | .size = 0x00040000, | ||
| 77 | .offset = 0x000C0000, | ||
| 78 | }, { | ||
| 79 | #ifdef CONFIG_JFFS2_FS | ||
| 80 | .name = "H3XXX root jffs2", | ||
| 81 | .size = MTDPART_SIZ_FULL, | ||
| 82 | .offset = 0x00100000, | ||
| 83 | #else | ||
| 84 | .name = "H3XXX initrd", | ||
| 85 | .size = 0x00100000, | ||
| 86 | .offset = 0x00100000, | ||
| 87 | }, { | ||
| 88 | .name = "H3XXX root cramfs", | ||
| 89 | .size = 0x00300000, | ||
| 90 | .offset = 0x00200000, | ||
| 91 | }, { | ||
| 92 | .name = "H3XXX usr cramfs", | ||
| 93 | .size = 0x00800000, | ||
| 94 | .offset = 0x00500000, | ||
| 95 | }, { | ||
| 96 | .name = "H3XXX usr local", | ||
| 97 | .size = MTDPART_SIZ_FULL, | ||
| 98 | .offset = 0x00d00000, | ||
| 99 | #endif | ||
| 100 | #endif | ||
| 101 | } | 62 | } |
| 102 | }; | 63 | }; |
| 103 | 64 | ||
| @@ -131,11 +92,7 @@ static int h3600_irda_set_power(struct device *dev, unsigned int state) | |||
| 131 | 92 | ||
| 132 | static void h3600_irda_set_speed(struct device *dev, unsigned int speed) | 93 | static void h3600_irda_set_speed(struct device *dev, unsigned int speed) |
| 133 | { | 94 | { |
| 134 | if (speed < 4000000) { | 95 | assign_h3600_egpio(IPAQ_EGPIO_IR_FSEL, !(speed < 4000000)); |
| 135 | clr_h3600_egpio(IPAQ_EGPIO_IR_FSEL); | ||
| 136 | } else { | ||
| 137 | set_h3600_egpio(IPAQ_EGPIO_IR_FSEL); | ||
| 138 | } | ||
| 139 | } | 96 | } |
| 140 | 97 | ||
| 141 | static struct irda_platform_data h3600_irda_data = { | 98 | static struct irda_platform_data h3600_irda_data = { |
| @@ -266,12 +223,6 @@ static void __init h3xxx_map_io(void) | |||
| 266 | sa1100fb_lcd_power = h3xxx_lcd_power; | 223 | sa1100fb_lcd_power = h3xxx_lcd_power; |
| 267 | } | 224 | } |
| 268 | 225 | ||
| 269 | static __inline__ void do_blank(int setp) | ||
| 270 | { | ||
| 271 | if (ipaq_model_ops.blank_callback) | ||
| 272 | ipaq_model_ops.blank_callback(1-setp); | ||
| 273 | } | ||
| 274 | |||
| 275 | /************************* H3100 *************************/ | 226 | /************************* H3100 *************************/ |
| 276 | 227 | ||
| 277 | #ifdef CONFIG_SA1100_H3100 | 228 | #ifdef CONFIG_SA1100_H3100 |
| @@ -289,7 +240,6 @@ static void h3100_control_egpio(enum ipaq_egpio_type x, int setp) | |||
| 289 | case IPAQ_EGPIO_LCD_POWER: | 240 | case IPAQ_EGPIO_LCD_POWER: |
| 290 | egpio |= EGPIO_H3600_LCD_ON; | 241 | egpio |= EGPIO_H3600_LCD_ON; |
| 291 | gpio |= GPIO_H3100_LCD_3V_ON; | 242 | gpio |= GPIO_H3100_LCD_3V_ON; |
| 292 | do_blank(setp); | ||
| 293 | break; | 243 | break; |
| 294 | case IPAQ_EGPIO_LCD_ENABLE: | 244 | case IPAQ_EGPIO_LCD_ENABLE: |
| 295 | break; | 245 | break; |
| @@ -343,25 +293,6 @@ static void h3100_control_egpio(enum ipaq_egpio_type x, int setp) | |||
| 343 | } | 293 | } |
| 344 | } | 294 | } |
| 345 | 295 | ||
| 346 | static unsigned long h3100_read_egpio(void) | ||
| 347 | { | ||
| 348 | return h3100_egpio; | ||
| 349 | } | ||
| 350 | |||
| 351 | static int h3100_pm_callback(int req) | ||
| 352 | { | ||
| 353 | if (ipaq_model_ops.pm_callback_aux) | ||
| 354 | return ipaq_model_ops.pm_callback_aux(req); | ||
| 355 | return 0; | ||
| 356 | } | ||
| 357 | |||
| 358 | static struct ipaq_model_ops h3100_model_ops __initdata = { | ||
| 359 | .generic_name = "3100", | ||
| 360 | .control = h3100_control_egpio, | ||
| 361 | .read = h3100_read_egpio, | ||
| 362 | .pm_callback = h3100_pm_callback | ||
| 363 | }; | ||
| 364 | |||
| 365 | #define H3100_DIRECT_EGPIO (GPIO_H3100_BT_ON \ | 296 | #define H3100_DIRECT_EGPIO (GPIO_H3100_BT_ON \ |
| 366 | | GPIO_H3100_GPIO3 \ | 297 | | GPIO_H3100_GPIO3 \ |
| 367 | | GPIO_H3100_QMUTE \ | 298 | | GPIO_H3100_QMUTE \ |
| @@ -387,7 +318,7 @@ static void __init h3100_map_io(void) | |||
| 387 | GAFR &= ~H3100_DIRECT_EGPIO; | 318 | GAFR &= ~H3100_DIRECT_EGPIO; |
| 388 | 319 | ||
| 389 | H3100_EGPIO = h3100_egpio; | 320 | H3100_EGPIO = h3100_egpio; |
| 390 | ipaq_model_ops = h3100_model_ops; | 321 | assign_h3600_egpio = h3100_control_egpio; |
| 391 | } | 322 | } |
| 392 | 323 | ||
| 393 | MACHINE_START(H3100, "Compaq iPAQ H3100") | 324 | MACHINE_START(H3100, "Compaq iPAQ H3100") |
| @@ -420,7 +351,6 @@ static void h3600_control_egpio(enum ipaq_egpio_type x, int setp) | |||
| 420 | EGPIO_H3600_LCD_PCI | | 351 | EGPIO_H3600_LCD_PCI | |
| 421 | EGPIO_H3600_LCD_5V_ON | | 352 | EGPIO_H3600_LCD_5V_ON | |
| 422 | EGPIO_H3600_LVDD_ON; | 353 | EGPIO_H3600_LVDD_ON; |
| 423 | do_blank(setp); | ||
| 424 | break; | 354 | break; |
| 425 | case IPAQ_EGPIO_LCD_ENABLE: | 355 | case IPAQ_EGPIO_LCD_ENABLE: |
| 426 | break; | 356 | break; |
| @@ -471,25 +401,6 @@ static void h3600_control_egpio(enum ipaq_egpio_type x, int setp) | |||
| 471 | } | 401 | } |
| 472 | } | 402 | } |
| 473 | 403 | ||
| 474 | static unsigned long h3600_read_egpio(void) | ||
| 475 | { | ||
| 476 | return h3600_egpio; | ||
| 477 | } | ||
| 478 | |||
| 479 | static int h3600_pm_callback(int req) | ||
| 480 | { | ||
| 481 | if (ipaq_model_ops.pm_callback_aux) | ||
| 482 | return ipaq_model_ops.pm_callback_aux(req); | ||
| 483 | return 0; | ||
| 484 | } | ||
| 485 | |||
| 486 | static struct ipaq_model_ops h3600_model_ops __initdata = { | ||
| 487 | .generic_name = "3600", | ||
| 488 | .control = h3600_control_egpio, | ||
| 489 | .read = h3600_read_egpio, | ||
| 490 | .pm_callback = h3600_pm_callback | ||
| 491 | }; | ||
| 492 | |||
| 493 | static void __init h3600_map_io(void) | 404 | static void __init h3600_map_io(void) |
| 494 | { | 405 | { |
| 495 | h3xxx_map_io(); | 406 | h3xxx_map_io(); |
| @@ -504,7 +415,7 @@ static void __init h3600_map_io(void) | |||
| 504 | GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8; | 415 | GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8; |
| 505 | 416 | ||
| 506 | H3600_EGPIO = h3600_egpio; /* Maintains across sleep? */ | 417 | H3600_EGPIO = h3600_egpio; /* Maintains across sleep? */ |
| 507 | ipaq_model_ops = h3600_model_ops; | 418 | assign_h3600_egpio = h3600_control_egpio; |
| 508 | } | 419 | } |
| 509 | 420 | ||
| 510 | MACHINE_START(H3600, "Compaq iPAQ H3600") | 421 | MACHINE_START(H3600, "Compaq iPAQ H3600") |
| @@ -519,388 +430,3 @@ MACHINE_END | |||
| 519 | 430 | ||
| 520 | #endif /* CONFIG_SA1100_H3600 */ | 431 | #endif /* CONFIG_SA1100_H3600 */ |
| 521 | 432 | ||
| 522 | #ifdef CONFIG_SA1100_H3800 | ||
| 523 | |||
| 524 | #define SET_ASIC1(x) \ | ||
| 525 | do {if (setp) { H3800_ASIC1_GPIO_OUT |= (x); } else { H3800_ASIC1_GPIO_OUT &= ~(x); }} while(0) | ||
| 526 | |||
| 527 | #define SET_ASIC2(x) \ | ||
| 528 | do {if (setp) { H3800_ASIC2_GPIOPIOD |= (x); } else { H3800_ASIC2_GPIOPIOD &= ~(x); }} while(0) | ||
| 529 | |||
| 530 | #define CLEAR_ASIC1(x) \ | ||
| 531 | do {if (setp) { H3800_ASIC1_GPIO_OUT &= ~(x); } else { H3800_ASIC1_GPIO_OUT |= (x); }} while(0) | ||
| 532 | |||
| 533 | #define CLEAR_ASIC2(x) \ | ||
| 534 | do {if (setp) { H3800_ASIC2_GPIOPIOD &= ~(x); } else { H3800_ASIC2_GPIOPIOD |= (x); }} while(0) | ||
| 535 | |||
| 536 | |||
| 537 | /* | ||
| 538 | On screen enable, we get | ||
| 539 | |||
| 540 | h3800_video_power_on(1) | ||
| 541 | LCD controller starts | ||
| 542 | h3800_video_lcd_enable(1) | ||
| 543 | |||
| 544 | On screen disable, we get | ||
| 545 | |||
| 546 | h3800_video_lcd_enable(0) | ||
| 547 | LCD controller stops | ||
| 548 | h3800_video_power_on(0) | ||
| 549 | */ | ||
| 550 | |||
| 551 | |||
| 552 | static void h3800_video_power_on(int setp) | ||
| 553 | { | ||
| 554 | if (setp) { | ||
| 555 | H3800_ASIC1_GPIO_OUT |= GPIO1_LCD_ON; | ||
| 556 | msleep(30); | ||
| 557 | H3800_ASIC1_GPIO_OUT |= GPIO1_VGL_ON; | ||
| 558 | msleep(5); | ||
| 559 | H3800_ASIC1_GPIO_OUT |= GPIO1_VGH_ON; | ||
| 560 | msleep(50); | ||
| 561 | H3800_ASIC1_GPIO_OUT |= GPIO1_LCD_5V_ON; | ||
| 562 | msleep(5); | ||
| 563 | } else { | ||
| 564 | msleep(5); | ||
| 565 | H3800_ASIC1_GPIO_OUT &= ~GPIO1_LCD_5V_ON; | ||
| 566 | msleep(50); | ||
| 567 | H3800_ASIC1_GPIO_OUT &= ~GPIO1_VGL_ON; | ||
| 568 | msleep(5); | ||
| 569 | H3800_ASIC1_GPIO_OUT &= ~GPIO1_VGH_ON; | ||
| 570 | msleep(100); | ||
| 571 | H3800_ASIC1_GPIO_OUT &= ~GPIO1_LCD_ON; | ||
| 572 | } | ||
| 573 | } | ||
| 574 | |||
| 575 | static void h3800_video_lcd_enable(int setp) | ||
| 576 | { | ||
| 577 | if (setp) { | ||
| 578 | msleep(17); // Wait one from before turning on | ||
| 579 | H3800_ASIC1_GPIO_OUT |= GPIO1_LCD_PCI; | ||
| 580 | } else { | ||
| 581 | H3800_ASIC1_GPIO_OUT &= ~GPIO1_LCD_PCI; | ||
| 582 | msleep(30); // Wait before turning off | ||
| 583 | } | ||
| 584 | } | ||
| 585 | |||
| 586 | |||
| 587 | static void h3800_control_egpio(enum ipaq_egpio_type x, int setp) | ||
| 588 | { | ||
| 589 | switch (x) { | ||
| 590 | case IPAQ_EGPIO_LCD_POWER: | ||
| 591 | h3800_video_power_on(setp); | ||
| 592 | break; | ||
| 593 | case IPAQ_EGPIO_LCD_ENABLE: | ||
| 594 | h3800_video_lcd_enable(setp); | ||
| 595 | break; | ||
| 596 | case IPAQ_EGPIO_CODEC_NRESET: | ||
| 597 | case IPAQ_EGPIO_AUDIO_ON: | ||
| 598 | case IPAQ_EGPIO_QMUTE: | ||
| 599 | printk("%s: error - should not be called\n", __func__); | ||
| 600 | break; | ||
| 601 | case IPAQ_EGPIO_OPT_NVRAM_ON: | ||
| 602 | SET_ASIC2(GPIO2_OPT_ON_NVRAM); | ||
| 603 | break; | ||
| 604 | case IPAQ_EGPIO_OPT_ON: | ||
| 605 | SET_ASIC2(GPIO2_OPT_ON); | ||
| 606 | break; | ||
| 607 | case IPAQ_EGPIO_CARD_RESET: | ||
| 608 | SET_ASIC2(GPIO2_OPT_PCM_RESET); | ||
| 609 | break; | ||
| 610 | case IPAQ_EGPIO_OPT_RESET: | ||
| 611 | SET_ASIC2(GPIO2_OPT_RESET); | ||
| 612 | break; | ||
| 613 | case IPAQ_EGPIO_IR_ON: | ||
| 614 | CLEAR_ASIC1(GPIO1_IR_ON_N); | ||
| 615 | break; | ||
| 616 | case IPAQ_EGPIO_IR_FSEL: | ||
| 617 | break; | ||
| 618 | case IPAQ_EGPIO_RS232_ON: | ||
| 619 | SET_ASIC1(GPIO1_RS232_ON); | ||
| 620 | break; | ||
| 621 | case IPAQ_EGPIO_VPP_ON: | ||
| 622 | H3800_ASIC2_FlashWP_VPP_ON = setp; | ||
| 623 | break; | ||
| 624 | } | ||
| 625 | } | ||
| 626 | |||
| 627 | static unsigned long h3800_read_egpio(void) | ||
| 628 | { | ||
| 629 | return H3800_ASIC1_GPIO_OUT | (H3800_ASIC2_GPIOPIOD << 16); | ||
| 630 | } | ||
| 631 | |||
| 632 | /* We need to fix ASIC2 GPIO over suspend/resume. At the moment, | ||
| 633 | it doesn't appear that ASIC1 GPIO has the same problem */ | ||
| 634 | |||
| 635 | static int h3800_pm_callback(int req) | ||
| 636 | { | ||
| 637 | static u16 asic1_data; | ||
| 638 | static u16 asic2_data; | ||
| 639 | int result = 0; | ||
| 640 | |||
| 641 | printk("%s %d\n", __func__, req); | ||
| 642 | |||
| 643 | switch (req) { | ||
| 644 | case PM_RESUME: | ||
| 645 | MSC2 = (MSC2 & 0x0000ffff) | 0xE4510000; /* Set MSC2 correctly */ | ||
| 646 | |||
| 647 | H3800_ASIC2_GPIOPIOD = asic2_data; | ||
| 648 | H3800_ASIC2_GPIODIR = GPIO2_PEN_IRQ | ||
| 649 | | GPIO2_SD_DETECT | ||
| 650 | | GPIO2_EAR_IN_N | ||
| 651 | | GPIO2_USB_DETECT_N | ||
| 652 | | GPIO2_SD_CON_SLT; | ||
| 653 | |||
| 654 | H3800_ASIC1_GPIO_OUT = asic1_data; | ||
| 655 | |||
| 656 | if (ipaq_model_ops.pm_callback_aux) | ||
| 657 | result = ipaq_model_ops.pm_callback_aux(req); | ||
| 658 | break; | ||
| 659 | |||
| 660 | case PM_SUSPEND: | ||
| 661 | if (ipaq_model_ops.pm_callback_aux && | ||
| 662 | ((result = ipaq_model_ops.pm_callback_aux(req)) != 0)) | ||
| 663 | return result; | ||
| 664 | |||
| 665 | asic1_data = H3800_ASIC1_GPIO_OUT; | ||
| 666 | asic2_data = H3800_ASIC2_GPIOPIOD; | ||
| 667 | break; | ||
| 668 | default: | ||
| 669 | printk("%s: unrecognized PM callback\n", __func__); | ||
| 670 | break; | ||
| 671 | } | ||
| 672 | return result; | ||
| 673 | } | ||
| 674 | |||
| 675 | static struct ipaq_model_ops h3800_model_ops __initdata = { | ||
| 676 | .generic_name = "3800", | ||
| 677 | .control = h3800_control_egpio, | ||
| 678 | .read = h3800_read_egpio, | ||
| 679 | .pm_callback = h3800_pm_callback | ||
| 680 | }; | ||
| 681 | |||
| 682 | #define MAX_ASIC_ISR_LOOPS 20 | ||
| 683 | |||
| 684 | /* The order of these is important - see #include <mach/irqs.h> */ | ||
| 685 | static u32 kpio_irq_mask[] = { | ||
| 686 | KPIO_KEY_ALL, | ||
| 687 | KPIO_SPI_INT, | ||
| 688 | KPIO_OWM_INT, | ||
| 689 | KPIO_ADC_INT, | ||
| 690 | KPIO_UART_0_INT, | ||
| 691 | KPIO_UART_1_INT, | ||
| 692 | KPIO_TIMER_0_INT, | ||
| 693 | KPIO_TIMER_1_INT, | ||
| 694 | KPIO_TIMER_2_INT | ||
| 695 | }; | ||
| 696 | |||
| 697 | static u32 gpio_irq_mask[] = { | ||
| 698 | GPIO2_PEN_IRQ, | ||
| 699 | GPIO2_SD_DETECT, | ||
| 700 | GPIO2_EAR_IN_N, | ||
| 701 | GPIO2_USB_DETECT_N, | ||
| 702 | GPIO2_SD_CON_SLT, | ||
| 703 | }; | ||
| 704 | |||
| 705 | static void h3800_IRQ_demux(unsigned int irq, struct irq_desc *desc) | ||
| 706 | { | ||
| 707 | int i; | ||
| 708 | |||
| 709 | if (0) printk("%s: interrupt received\n", __func__); | ||
| 710 | |||
| 711 | desc->chip->ack(irq); | ||
| 712 | |||
| 713 | for (i = 0; i < MAX_ASIC_ISR_LOOPS && (GPLR & GPIO_H3800_ASIC); i++) { | ||
| 714 | u32 irq; | ||
| 715 | int j; | ||
| 716 | |||
| 717 | /* KPIO */ | ||
| 718 | irq = H3800_ASIC2_KPIINTFLAG; | ||
| 719 | if (0) printk("%s KPIO 0x%08X\n", __func__, irq); | ||
| 720 | for (j = 0; j < H3800_KPIO_IRQ_COUNT; j++) | ||
| 721 | if (irq & kpio_irq_mask[j]) | ||
| 722 | handle_edge_irq(H3800_KPIO_IRQ_COUNT + j, irq_desc + H3800_KPIO_IRQ_COUNT + j); | ||
| 723 | |||
| 724 | /* GPIO2 */ | ||
| 725 | irq = H3800_ASIC2_GPIINTFLAG; | ||
| 726 | if (0) printk("%s GPIO 0x%08X\n", __func__, irq); | ||
| 727 | for (j = 0; j < H3800_GPIO_IRQ_COUNT; j++) | ||
| 728 | if (irq & gpio_irq_mask[j]) | ||
| 729 | handle_edge_irq(H3800_GPIO_IRQ_COUNT + j, irq_desc + H3800_GPIO_IRQ_COUNT + j); | ||
| 730 | } | ||
| 731 | |||
| 732 | if (i >= MAX_ASIC_ISR_LOOPS) | ||
| 733 | printk("%s: interrupt processing overrun\n", __func__); | ||
| 734 | |||
| 735 | /* For level-based interrupts */ | ||
| 736 | desc->chip->unmask(irq); | ||
| 737 | |||
| 738 | } | ||
| 739 | |||
| 740 | static struct irqaction h3800_irq = { | ||
| 741 | .name = "h3800_asic", | ||
| 742 | .handler = h3800_IRQ_demux, | ||
| 743 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, | ||
| 744 | }; | ||
| 745 | |||
| 746 | u32 kpio_int_shadow = 0; | ||
| 747 | |||
| 748 | |||
| 749 | /* mask_ack <- IRQ is first serviced. | ||
| 750 | mask <- IRQ is disabled. | ||
| 751 | unmask <- IRQ is enabled | ||
| 752 | |||
| 753 | The INTCLR registers are poorly documented. I believe that writing | ||
| 754 | a "1" to the register clears the specific interrupt, but the documentation | ||
| 755 | indicates writing a "0" clears the interrupt. In any case, they shouldn't | ||
| 756 | be read (that's the INTFLAG register) | ||
| 757 | */ | ||
| 758 | |||
| 759 | static void h3800_mask_ack_kpio_irq(unsigned int irq) | ||
| 760 | { | ||
| 761 | u32 mask = kpio_irq_mask[irq - H3800_KPIO_IRQ_START]; | ||
| 762 | kpio_int_shadow &= ~mask; | ||
| 763 | H3800_ASIC2_KPIINTSTAT = kpio_int_shadow; | ||
| 764 | H3800_ASIC2_KPIINTCLR = mask; | ||
| 765 | } | ||
| 766 | |||
| 767 | static void h3800_mask_kpio_irq(unsigned int irq) | ||
| 768 | { | ||
| 769 | u32 mask = kpio_irq_mask[irq - H3800_KPIO_IRQ_START]; | ||
| 770 | kpio_int_shadow &= ~mask; | ||
| 771 | H3800_ASIC2_KPIINTSTAT = kpio_int_shadow; | ||
| 772 | } | ||
| 773 | |||
| 774 | static void h3800_unmask_kpio_irq(unsigned int irq) | ||
| 775 | { | ||
| 776 | u32 mask = kpio_irq_mask[irq - H3800_KPIO_IRQ_START]; | ||
| 777 | kpio_int_shadow |= mask; | ||
| 778 | H3800_ASIC2_KPIINTSTAT = kpio_int_shadow; | ||
| 779 | } | ||
| 780 | |||
| 781 | static void h3800_mask_ack_gpio_irq(unsigned int irq) | ||
| 782 | { | ||
| 783 | u32 mask = gpio_irq_mask[irq - H3800_GPIO_IRQ_START]; | ||
| 784 | H3800_ASIC2_GPIINTSTAT &= ~mask; | ||
| 785 | H3800_ASIC2_GPIINTCLR = mask; | ||
| 786 | } | ||
| 787 | |||
| 788 | static void h3800_mask_gpio_irq(unsigned int irq) | ||
| 789 | { | ||
| 790 | u32 mask = gpio_irq_mask[irq - H3800_GPIO_IRQ_START]; | ||
| 791 | H3800_ASIC2_GPIINTSTAT &= ~mask; | ||
| 792 | } | ||
| 793 | |||
| 794 | static void h3800_unmask_gpio_irq(unsigned int irq) | ||
| 795 | { | ||
| 796 | u32 mask = gpio_irq_mask[irq - H3800_GPIO_IRQ_START]; | ||
| 797 | H3800_ASIC2_GPIINTSTAT |= mask; | ||
| 798 | } | ||
| 799 | |||
| 800 | static void __init h3800_init_irq(void) | ||
| 801 | { | ||
| 802 | int i; | ||
| 803 | |||
| 804 | /* Initialize standard IRQs */ | ||
| 805 | sa1100_init_irq(); | ||
| 806 | |||
| 807 | /* Disable all IRQs and set up clock */ | ||
| 808 | H3800_ASIC2_KPIINTSTAT = 0; /* Disable all interrupts */ | ||
| 809 | H3800_ASIC2_GPIINTSTAT = 0; | ||
| 810 | |||
| 811 | H3800_ASIC2_KPIINTCLR = 0; /* Clear all KPIO interrupts */ | ||
| 812 | H3800_ASIC2_GPIINTCLR = 0; /* Clear all GPIO interrupts */ | ||
| 813 | |||
| 814 | // H3800_ASIC2_KPIINTCLR = 0xffff; /* Clear all KPIO interrupts */ | ||
| 815 | // H3800_ASIC2_GPIINTCLR = 0xffff; /* Clear all GPIO interrupts */ | ||
| 816 | |||
| 817 | H3800_ASIC2_CLOCK_Enable |= ASIC2_CLOCK_EX0; /* 32 kHZ crystal on */ | ||
| 818 | H3800_ASIC2_INTR_ClockPrescale |= ASIC2_INTCPS_SET; | ||
| 819 | H3800_ASIC2_INTR_ClockPrescale = ASIC2_INTCPS_CPS(0x0e) | ASIC2_INTCPS_SET; | ||
| 820 | H3800_ASIC2_INTR_TimerSet = 1; | ||
| 821 | |||
| 822 | #if 0 | ||
| 823 | for (i = 0; i < H3800_KPIO_IRQ_COUNT; i++) { | ||
| 824 | int irq = i + H3800_KPIO_IRQ_START; | ||
| 825 | irq_desc[irq].valid = 1; | ||
| 826 | irq_desc[irq].probe_ok = 1; | ||
| 827 | set_irq_chip(irq, &h3800_kpio_irqchip); | ||
| 828 | } | ||
| 829 | |||
| 830 | for (i = 0; i < H3800_GPIO_IRQ_COUNT; i++) { | ||
| 831 | int irq = i + H3800_GPIO_IRQ_START; | ||
| 832 | irq_desc[irq].valid = 1; | ||
| 833 | irq_desc[irq].probe_ok = 1; | ||
| 834 | set_irq_chip(irq, &h3800_gpio_irqchip); | ||
| 835 | } | ||
| 836 | #endif | ||
| 837 | set_irq_type(IRQ_GPIO_H3800_ASIC, IRQ_TYPE_EDGE_RISING); | ||
| 838 | set_irq_chained_handler(IRQ_GPIO_H3800_ASIC, h3800_IRQ_demux); | ||
| 839 | } | ||
| 840 | |||
| 841 | |||
| 842 | #define ASIC1_OUTPUTS 0x7fff /* First 15 bits are used */ | ||
| 843 | |||
| 844 | static void __init h3800_map_io(void) | ||
| 845 | { | ||
| 846 | h3xxx_map_io(); | ||
| 847 | |||
| 848 | /* Add wakeup on AC plug/unplug */ | ||
| 849 | PWER |= PWER_GPIO12; | ||
| 850 | |||
| 851 | /* Initialize h3800-specific values here */ | ||
| 852 | GPCR = 0x0fffffff; /* All outputs are set low by default */ | ||
| 853 | GAFR = GPIO_H3800_CLK_OUT | | ||
| 854 | GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 | | ||
| 855 | GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8; | ||
| 856 | GPDR = GPIO_H3800_CLK_OUT | | ||
| 857 | GPIO_H3600_COM_RTS | GPIO_H3600_L3_CLOCK | | ||
| 858 | GPIO_H3600_L3_MODE | GPIO_H3600_L3_DATA | | ||
| 859 | GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12 | | ||
| 860 | GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8; | ||
| 861 | TUCR = TUCR_3_6864MHz; /* Seems to be used only for the Bluetooth UART */ | ||
| 862 | |||
| 863 | /* Fix the memory bus */ | ||
| 864 | MSC2 = (MSC2 & 0x0000ffff) | 0xE4510000; | ||
| 865 | |||
| 866 | /* Set up ASIC #1 */ | ||
| 867 | H3800_ASIC1_GPIO_DIR = ASIC1_OUTPUTS; /* All outputs */ | ||
| 868 | H3800_ASIC1_GPIO_MASK = ASIC1_OUTPUTS; /* No interrupts */ | ||
| 869 | H3800_ASIC1_GPIO_SLEEP_MASK = ASIC1_OUTPUTS; | ||
| 870 | H3800_ASIC1_GPIO_SLEEP_DIR = ASIC1_OUTPUTS; | ||
| 871 | H3800_ASIC1_GPIO_SLEEP_OUT = GPIO1_EAR_ON_N; | ||
| 872 | H3800_ASIC1_GPIO_BATT_FAULT_DIR = ASIC1_OUTPUTS; | ||
| 873 | H3800_ASIC1_GPIO_BATT_FAULT_OUT = GPIO1_EAR_ON_N; | ||
| 874 | |||
| 875 | H3800_ASIC1_GPIO_OUT = GPIO1_IR_ON_N | ||
| 876 | | GPIO1_RS232_ON | ||
| 877 | | GPIO1_EAR_ON_N; | ||
| 878 | |||
| 879 | /* Set up ASIC #2 */ | ||
| 880 | H3800_ASIC2_GPIOPIOD = GPIO2_IN_Y1_N | GPIO2_IN_X1_N; | ||
| 881 | H3800_ASIC2_GPOBFSTAT = GPIO2_IN_Y1_N | GPIO2_IN_X1_N; | ||
| 882 | |||
| 883 | H3800_ASIC2_GPIODIR = GPIO2_PEN_IRQ | ||
| 884 | | GPIO2_SD_DETECT | ||
| 885 | | GPIO2_EAR_IN_N | ||
| 886 | | GPIO2_USB_DETECT_N | ||
| 887 | | GPIO2_SD_CON_SLT; | ||
| 888 | |||
| 889 | /* TODO : Set sleep states & battery fault states */ | ||
| 890 | |||
| 891 | /* Clear VPP Enable */ | ||
| 892 | H3800_ASIC2_FlashWP_VPP_ON = 0; | ||
| 893 | ipaq_model_ops = h3800_model_ops; | ||
| 894 | } | ||
| 895 | |||
| 896 | MACHINE_START(H3800, "Compaq iPAQ H3800") | ||
| 897 | .phys_io = 0x80000000, | ||
| 898 | .io_pg_offst = ((0xf8000000) >> 18) & 0xfffc, | ||
| 899 | .boot_params = 0xc0000100, | ||
| 900 | .map_io = h3800_map_io, | ||
| 901 | .init_irq = h3800_init_irq, | ||
| 902 | .timer = &sa1100_timer, | ||
| 903 | .init_machine = h3xxx_mach_init, | ||
| 904 | MACHINE_END | ||
| 905 | |||
| 906 | #endif /* CONFIG_SA1100_H3800 */ | ||
diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h index 69e962416e3f..9efb569cdb60 100644 --- a/arch/arm/mach-sa1100/include/mach/collie.h +++ b/arch/arm/mach-sa1100/include/mach/collie.h | |||
| @@ -14,21 +14,21 @@ | |||
| 14 | #define __ASM_ARCH_COLLIE_H | 14 | #define __ASM_ARCH_COLLIE_H |
| 15 | 15 | ||
| 16 | 16 | ||
| 17 | #define COLLIE_SCP_CHARGE_ON SCOOP_GPCR_PA11 | 17 | #define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1) |
| 18 | #define COLLIE_GPIO_CHARGE_ON (COLLIE_SCOOP_GPIO_BASE + 0) | ||
| 18 | #define COLLIE_SCP_DIAG_BOOT1 SCOOP_GPCR_PA12 | 19 | #define COLLIE_SCP_DIAG_BOOT1 SCOOP_GPCR_PA12 |
| 19 | #define COLLIE_SCP_DIAG_BOOT2 SCOOP_GPCR_PA13 | 20 | #define COLLIE_SCP_DIAG_BOOT2 SCOOP_GPCR_PA13 |
| 20 | #define COLLIE_SCP_MUTE_L SCOOP_GPCR_PA14 | 21 | #define COLLIE_SCP_MUTE_L SCOOP_GPCR_PA14 |
| 21 | #define COLLIE_SCP_MUTE_R SCOOP_GPCR_PA15 | 22 | #define COLLIE_SCP_MUTE_R SCOOP_GPCR_PA15 |
| 22 | #define COLLIE_SCP_5VON SCOOP_GPCR_PA16 | 23 | #define COLLIE_SCP_5VON SCOOP_GPCR_PA16 |
| 23 | #define COLLIE_SCP_AMP_ON SCOOP_GPCR_PA17 | 24 | #define COLLIE_SCP_AMP_ON SCOOP_GPCR_PA17 |
| 24 | #define COLLIE_SCP_VPEN SCOOP_GPCR_PA18 | 25 | #define COLLIE_GPIO_VPEN (COLLIE_SCOOP_GPIO_BASE + 7) |
| 25 | #define COLLIE_SCP_LB_VOL_CHG SCOOP_GPCR_PA19 | 26 | #define COLLIE_SCP_LB_VOL_CHG SCOOP_GPCR_PA19 |
| 26 | 27 | ||
| 27 | #define COLLIE_SCOOP_IO_DIR ( COLLIE_SCP_CHARGE_ON | COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \ | 28 | #define COLLIE_SCOOP_IO_DIR ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \ |
| 28 | COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | COLLIE_SCP_VPEN | \ | 29 | COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | \ |
| 29 | COLLIE_SCP_LB_VOL_CHG ) | 30 | COLLIE_SCP_LB_VOL_CHG ) |
| 30 | #define COLLIE_SCOOP_IO_OUT ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | COLLIE_SCP_VPEN | \ | 31 | #define COLLIE_SCOOP_IO_OUT ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R ) |
| 31 | COLLIE_SCP_CHARGE_ON ) | ||
| 32 | 32 | ||
| 33 | /* GPIOs for which the generic definition doesn't say much */ | 33 | /* GPIOs for which the generic definition doesn't say much */ |
| 34 | 34 | ||
diff --git a/arch/arm/mach-sa1100/include/mach/h3600.h b/arch/arm/mach-sa1100/include/mach/h3600.h index 9cc47fddb335..2827faa47421 100644 --- a/arch/arm/mach-sa1100/include/mach/h3600.h +++ b/arch/arm/mach-sa1100/include/mach/h3600.h | |||
| @@ -29,7 +29,7 @@ typedef int __bitwise pm_request_t; | |||
| 29 | #define PM_RESUME ((__force pm_request_t) 2) /* enter D0 */ | 29 | #define PM_RESUME ((__force pm_request_t) 2) /* enter D0 */ |
| 30 | 30 | ||
| 31 | /* generalized support for H3xxx series Compaq Pocket PC's */ | 31 | /* generalized support for H3xxx series Compaq Pocket PC's */ |
| 32 | #define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800()) | 32 | #define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600()) |
| 33 | 33 | ||
| 34 | /* Physical memory regions corresponding to chip selects */ | 34 | /* Physical memory regions corresponding to chip selects */ |
| 35 | #define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000) | 35 | #define H3600_EGPIO_PHYS (SA1100_CS5_PHYS + 0x01000000) |
| @@ -93,76 +93,7 @@ enum ipaq_egpio_type { | |||
| 93 | IPAQ_EGPIO_LCD_ENABLE, /* Enable/disable LCD controller */ | 93 | IPAQ_EGPIO_LCD_ENABLE, /* Enable/disable LCD controller */ |
| 94 | }; | 94 | }; |
| 95 | 95 | ||
| 96 | struct ipaq_model_ops { | 96 | extern void (*assign_h3600_egpio)(enum ipaq_egpio_type x, int level); |
| 97 | const char *generic_name; | ||
| 98 | void (*control)(enum ipaq_egpio_type, int); | ||
| 99 | unsigned long (*read)(void); | ||
| 100 | void (*blank_callback)(int blank); | ||
| 101 | int (*pm_callback)(int req); /* Primary model callback */ | ||
| 102 | int (*pm_callback_aux)(int req); /* Secondary callback (used by HAL modules) */ | ||
| 103 | }; | ||
| 104 | |||
| 105 | extern struct ipaq_model_ops ipaq_model_ops; | ||
| 106 | |||
| 107 | static __inline__ const char * h3600_generic_name(void) | ||
| 108 | { | ||
| 109 | return ipaq_model_ops.generic_name; | ||
| 110 | } | ||
| 111 | |||
| 112 | static __inline__ void assign_h3600_egpio(enum ipaq_egpio_type x, int level) | ||
| 113 | { | ||
| 114 | if (ipaq_model_ops.control) | ||
| 115 | ipaq_model_ops.control(x,level); | ||
| 116 | } | ||
| 117 | |||
| 118 | static __inline__ void clr_h3600_egpio(enum ipaq_egpio_type x) | ||
| 119 | { | ||
| 120 | if (ipaq_model_ops.control) | ||
| 121 | ipaq_model_ops.control(x,0); | ||
| 122 | } | ||
| 123 | |||
| 124 | static __inline__ void set_h3600_egpio(enum ipaq_egpio_type x) | ||
| 125 | { | ||
| 126 | if (ipaq_model_ops.control) | ||
| 127 | ipaq_model_ops.control(x,1); | ||
| 128 | } | ||
| 129 | |||
| 130 | static __inline__ unsigned long read_h3600_egpio(void) | ||
| 131 | { | ||
| 132 | if (ipaq_model_ops.read) | ||
| 133 | return ipaq_model_ops.read(); | ||
| 134 | return 0; | ||
| 135 | } | ||
| 136 | |||
| 137 | static __inline__ int h3600_register_blank_callback(void (*f)(int)) | ||
| 138 | { | ||
| 139 | ipaq_model_ops.blank_callback = f; | ||
| 140 | return 0; | ||
| 141 | } | ||
| 142 | |||
| 143 | static __inline__ void h3600_unregister_blank_callback(void (*f)(int)) | ||
| 144 | { | ||
| 145 | ipaq_model_ops.blank_callback = NULL; | ||
| 146 | } | ||
| 147 | |||
| 148 | |||
| 149 | static __inline__ int h3600_register_pm_callback(int (*f)(int)) | ||
| 150 | { | ||
| 151 | ipaq_model_ops.pm_callback_aux = f; | ||
| 152 | return 0; | ||
| 153 | } | ||
| 154 | |||
| 155 | static __inline__ void h3600_unregister_pm_callback(int (*f)(int)) | ||
| 156 | { | ||
| 157 | ipaq_model_ops.pm_callback_aux = NULL; | ||
| 158 | } | ||
| 159 | |||
| 160 | static __inline__ int h3600_power_management(int req) | ||
| 161 | { | ||
| 162 | if (ipaq_model_ops.pm_callback) | ||
| 163 | return ipaq_model_ops.pm_callback(req); | ||
| 164 | return 0; | ||
| 165 | } | ||
| 166 | 97 | ||
| 167 | #endif /* ASSEMBLY */ | 98 | #endif /* ASSEMBLY */ |
| 168 | 99 | ||
diff --git a/arch/arm/mach-sa1100/include/mach/h3600_gpio.h b/arch/arm/mach-sa1100/include/mach/h3600_gpio.h index 62b0b7879685..a36ca76d018b 100644 --- a/arch/arm/mach-sa1100/include/mach/h3600_gpio.h +++ b/arch/arm/mach-sa1100/include/mach/h3600_gpio.h | |||
| @@ -48,22 +48,11 @@ | |||
| 48 | #define GPIO_H3600_OPT_LOCK GPIO_GPIO (22) | 48 | #define GPIO_H3600_OPT_LOCK GPIO_GPIO (22) |
| 49 | #define GPIO_H3600_OPT_DET GPIO_GPIO (27) | 49 | #define GPIO_H3600_OPT_DET GPIO_GPIO (27) |
| 50 | 50 | ||
| 51 | /* H3800 specific pins */ | ||
| 52 | #define GPIO_H3800_AC_IN GPIO_GPIO (12) | ||
| 53 | #define GPIO_H3800_COM_DSR GPIO_GPIO (13) | ||
| 54 | #define GPIO_H3800_MMC_INT GPIO_GPIO (18) | ||
| 55 | #define GPIO_H3800_NOPT_IND GPIO_GPIO (20) /* Almost exactly the same as GPIO_H3600_OPT_DET */ | ||
| 56 | #define GPIO_H3800_OPT_BAT_FAULT GPIO_GPIO (22) | ||
| 57 | #define GPIO_H3800_CLK_OUT GPIO_GPIO (27) | ||
| 58 | |||
| 59 | /****************************************************/ | 51 | /****************************************************/ |
| 60 | 52 | ||
| 61 | #define IRQ_GPIO_H3600_ACTION_BUTTON IRQ_GPIO18 | 53 | #define IRQ_GPIO_H3600_ACTION_BUTTON IRQ_GPIO18 |
| 62 | #define IRQ_GPIO_H3600_OPT_DET IRQ_GPIO27 | 54 | #define IRQ_GPIO_H3600_OPT_DET IRQ_GPIO27 |
| 63 | 55 | ||
| 64 | #define IRQ_GPIO_H3800_MMC_INT IRQ_GPIO18 | ||
| 65 | #define IRQ_GPIO_H3800_NOPT_IND IRQ_GPIO20 /* almost same as OPT_DET */ | ||
| 66 | |||
| 67 | /* H3100 / 3600 EGPIO pins */ | 56 | /* H3100 / 3600 EGPIO pins */ |
| 68 | #define EGPIO_H3600_VPP_ON (1 << 0) | 57 | #define EGPIO_H3600_VPP_ON (1 << 0) |
| 69 | #define EGPIO_H3600_CARD_RESET (1 << 1) /* reset the attached pcmcia/compactflash card. active high. */ | 58 | #define EGPIO_H3600_CARD_RESET (1 << 1) /* reset the attached pcmcia/compactflash card. active high. */ |
| @@ -84,457 +73,5 @@ | |||
| 84 | #define EGPIO_H3600_LCD_5V_ON (1 << 14) /* enable 5V to LCD. active high. */ | 73 | #define EGPIO_H3600_LCD_5V_ON (1 << 14) /* enable 5V to LCD. active high. */ |
| 85 | #define EGPIO_H3600_LVDD_ON (1 << 15) /* enable 9V and -6.5V to LCD. */ | 74 | #define EGPIO_H3600_LVDD_ON (1 << 15) /* enable 9V and -6.5V to LCD. */ |
| 86 | 75 | ||
| 87 | /********************* H3800, ASIC #2 ********************/ | ||
| 88 | |||
| 89 | #define _H3800_ASIC2_Base (H3600_EGPIO_VIRT) | ||
| 90 | #define H3800_ASIC2_OFFSET(s,x,y) \ | ||
| 91 | (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _Base + _H3800_ASIC2_ ## x ## _ ## y))) | ||
| 92 | #define H3800_ASIC2_NOFFSET(s,x,n,y) \ | ||
| 93 | (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _ ## n ## _Base + _H3800_ASIC2_ ## x ## _ ## y))) | ||
| 94 | |||
| 95 | #define _H3800_ASIC2_GPIO_Base 0x0000 | ||
| 96 | #define _H3800_ASIC2_GPIO_Direction 0x0000 /* R/W, 16 bits 1:input, 0:output */ | ||
| 97 | #define _H3800_ASIC2_GPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */ | ||
| 98 | #define _H3800_ASIC2_GPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */ | ||
| 99 | #define _H3800_ASIC2_GPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */ | ||
| 100 | #define _H3800_ASIC2_GPIO_InterruptClear 0x0010 /* W, 12 bits */ | ||
| 101 | #define _H3800_ASIC2_GPIO_InterruptFlag 0x0010 /* R, 12 bits - reads int status */ | ||
| 102 | #define _H3800_ASIC2_GPIO_Data 0x0014 /* R/W, 16 bits */ | ||
| 103 | #define _H3800_ASIC2_GPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */ | ||
| 104 | #define _H3800_ASIC2_GPIO_InterruptEnable 0x001c /* R/W, 12 bits 1:enable interrupt */ | ||
| 105 | #define _H3800_ASIC2_GPIO_Alternate 0x003c /* R/W, 12+1 bits - set alternate functions */ | ||
| 106 | |||
| 107 | #define H3800_ASIC2_GPIO_Direction H3800_ASIC2_OFFSET( u16, GPIO, Direction ) | ||
| 108 | #define H3800_ASIC2_GPIO_InterruptType H3800_ASIC2_OFFSET( u16, GPIO, InterruptType ) | ||
| 109 | #define H3800_ASIC2_GPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, GPIO, InterruptEdgeType ) | ||
| 110 | #define H3800_ASIC2_GPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, GPIO, InterruptLevelType ) | ||
| 111 | #define H3800_ASIC2_GPIO_InterruptClear H3800_ASIC2_OFFSET( u16, GPIO, InterruptClear ) | ||
| 112 | #define H3800_ASIC2_GPIO_InterruptFlag H3800_ASIC2_OFFSET( u16, GPIO, InterruptFlag ) | ||
| 113 | #define H3800_ASIC2_GPIO_Data H3800_ASIC2_OFFSET( u16, GPIO, Data ) | ||
| 114 | #define H3800_ASIC2_GPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, GPIO, BattFaultOut ) | ||
| 115 | #define H3800_ASIC2_GPIO_InterruptEnable H3800_ASIC2_OFFSET( u16, GPIO, InterruptEnable ) | ||
| 116 | #define H3800_ASIC2_GPIO_Alternate H3800_ASIC2_OFFSET( u16, GPIO, Alternate ) | ||
| 117 | |||
| 118 | #define GPIO_H3800_ASIC2_IN_Y1_N (1 << 0) /* Output: Touchscreen Y1 */ | ||
| 119 | #define GPIO_H3800_ASIC2_IN_X0 (1 << 1) /* Output: Touchscreen X0 */ | ||
| 120 | #define GPIO_H3800_ASIC2_IN_Y0 (1 << 2) /* Output: Touchscreen Y0 */ | ||
| 121 | #define GPIO_H3800_ASIC2_IN_X1_N (1 << 3) /* Output: Touchscreen X1 */ | ||
| 122 | #define GPIO_H3800_ASIC2_BT_RST (1 << 4) /* Output: Bluetooth reset */ | ||
| 123 | #define GPIO_H3800_ASIC2_PEN_IRQ (1 << 5) /* Input : Pen down */ | ||
| 124 | #define GPIO_H3800_ASIC2_SD_DETECT (1 << 6) /* Input : SD detect */ | ||
| 125 | #define GPIO_H3800_ASIC2_EAR_IN_N (1 << 7) /* Input : Audio jack plug inserted */ | ||
| 126 | #define GPIO_H3800_ASIC2_OPT_PCM_RESET (1 << 8) /* Output: */ | ||
| 127 | #define GPIO_H3800_ASIC2_OPT_RESET (1 << 9) /* Output: */ | ||
| 128 | #define GPIO_H3800_ASIC2_USB_DETECT_N (1 << 10) /* Input : */ | ||
| 129 | #define GPIO_H3800_ASIC2_SD_CON_SLT (1 << 11) /* Input : */ | ||
| 130 | |||
| 131 | #define _H3800_ASIC2_KPIO_Base 0x0200 | ||
| 132 | #define _H3800_ASIC2_KPIO_Direction 0x0000 /* R/W, 12 bits 1:input, 0:output */ | ||
| 133 | #define _H3800_ASIC2_KPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */ | ||
| 134 | #define _H3800_ASIC2_KPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */ | ||
| 135 | #define _H3800_ASIC2_KPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */ | ||
| 136 | #define _H3800_ASIC2_KPIO_InterruptClear 0x0010 /* W, 20 bits - 8 special */ | ||
| 137 | #define _H3800_ASIC2_KPIO_InterruptFlag 0x0010 /* R, 20 bits - 8 special - reads int status */ | ||
| 138 | #define _H3800_ASIC2_KPIO_Data 0x0014 /* R/W, 16 bits */ | ||
| 139 | #define _H3800_ASIC2_KPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */ | ||
| 140 | #define _H3800_ASIC2_KPIO_InterruptEnable 0x001c /* R/W, 20 bits - 8 special */ | ||
| 141 | #define _H3800_ASIC2_KPIO_Alternate 0x003c /* R/W, 6 bits */ | ||
| 142 | |||
| 143 | #define H3800_ASIC2_KPIO_Direction H3800_ASIC2_OFFSET( u16, KPIO, Direction ) | ||
| 144 | #define H3800_ASIC2_KPIO_InterruptType H3800_ASIC2_OFFSET( u16, KPIO, InterruptType ) | ||
| 145 | #define H3800_ASIC2_KPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, KPIO, InterruptEdgeType ) | ||
| 146 | #define H3800_ASIC2_KPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, KPIO, InterruptLevelType ) | ||
| 147 | #define H3800_ASIC2_KPIO_InterruptClear H3800_ASIC2_OFFSET( u32, KPIO, InterruptClear ) | ||
| 148 | #define H3800_ASIC2_KPIO_InterruptFlag H3800_ASIC2_OFFSET( u32, KPIO, InterruptFlag ) | ||
| 149 | #define H3800_ASIC2_KPIO_Data H3800_ASIC2_OFFSET( u16, KPIO, Data ) | ||
| 150 | #define H3800_ASIC2_KPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, KPIO, BattFaultOut ) | ||
| 151 | #define H3800_ASIC2_KPIO_InterruptEnable H3800_ASIC2_OFFSET( u32, KPIO, InterruptEnable ) | ||
| 152 | #define H3800_ASIC2_KPIO_Alternate H3800_ASIC2_OFFSET( u16, KPIO, Alternate ) | ||
| 153 | |||
| 154 | #define H3800_ASIC2_KPIO_SPI_INT ( 1 << 16 ) | ||
| 155 | #define H3800_ASIC2_KPIO_OWM_INT ( 1 << 17 ) | ||
| 156 | #define H3800_ASIC2_KPIO_ADC_INT ( 1 << 18 ) | ||
| 157 | #define H3800_ASIC2_KPIO_UART_0_INT ( 1 << 19 ) | ||
| 158 | #define H3800_ASIC2_KPIO_UART_1_INT ( 1 << 20 ) | ||
| 159 | #define H3800_ASIC2_KPIO_TIMER_0_INT ( 1 << 21 ) | ||
| 160 | #define H3800_ASIC2_KPIO_TIMER_1_INT ( 1 << 22 ) | ||
| 161 | #define H3800_ASIC2_KPIO_TIMER_2_INT ( 1 << 23 ) | ||
| 162 | |||
| 163 | #define KPIO_H3800_ASIC2_RECORD_BTN_N (1 << 0) /* Record button */ | ||
| 164 | #define KPIO_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Keypad */ | ||
| 165 | #define KPIO_H3800_ASIC2_KEY_5W2_N (1 << 2) /* */ | ||
| 166 | #define KPIO_H3800_ASIC2_KEY_5W3_N (1 << 3) /* */ | ||
| 167 | #define KPIO_H3800_ASIC2_KEY_5W4_N (1 << 4) /* */ | ||
| 168 | #define KPIO_H3800_ASIC2_KEY_5W5_N (1 << 5) /* */ | ||
| 169 | #define KPIO_H3800_ASIC2_KEY_LEFT_N (1 << 6) /* */ | ||
| 170 | #define KPIO_H3800_ASIC2_KEY_RIGHT_N (1 << 7) /* */ | ||
| 171 | #define KPIO_H3800_ASIC2_KEY_AP1_N (1 << 8) /* Old "Calendar" */ | ||
| 172 | #define KPIO_H3800_ASIC2_KEY_AP2_N (1 << 9) /* Old "Schedule" */ | ||
| 173 | #define KPIO_H3800_ASIC2_KEY_AP3_N (1 << 10) /* Old "Q" */ | ||
| 174 | #define KPIO_H3800_ASIC2_KEY_AP4_N (1 << 11) /* Old "Undo" */ | ||
| 175 | |||
| 176 | /* Alternate KPIO functions (set by default) */ | ||
| 177 | #define KPIO_ALT_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Action key */ | ||
| 178 | #define KPIO_ALT_H3800_ASIC2_KEY_5W2_N (1 << 2) /* J1 of keypad input */ | ||
| 179 | #define KPIO_ALT_H3800_ASIC2_KEY_5W3_N (1 << 3) /* J2 of keypad input */ | ||
| 180 | #define KPIO_ALT_H3800_ASIC2_KEY_5W4_N (1 << 4) /* J3 of keypad input */ | ||
| 181 | #define KPIO_ALT_H3800_ASIC2_KEY_5W5_N (1 << 5) /* J4 of keypad input */ | ||
| 182 | |||
| 183 | #define _H3800_ASIC2_SPI_Base 0x0400 | ||
| 184 | #define _H3800_ASIC2_SPI_Control 0x0000 /* R/W 8 bits */ | ||
| 185 | #define _H3800_ASIC2_SPI_Data 0x0004 /* R/W 8 bits */ | ||
| 186 | #define _H3800_ASIC2_SPI_ChipSelectDisabled 0x0008 /* W 8 bits */ | ||
| 187 | |||
| 188 | #define H3800_ASIC2_SPI_Control H3800_ASIC2_OFFSET( u8, SPI, Control ) | ||
| 189 | #define H3800_ASIC2_SPI_Data H3800_ASIC2_OFFSET( u8, SPI, Data ) | ||
| 190 | #define H3800_ASIC2_SPI_ChipSelectDisabled H3800_ASIC2_OFFSET( u8, SPI, ChipSelectDisabled ) | ||
| 191 | |||
| 192 | #define _H3800_ASIC2_PWM_0_Base 0x0600 | ||
| 193 | #define _H3800_ASIC2_PWM_1_Base 0x0700 | ||
| 194 | #define _H3800_ASIC2_PWM_TimeBase 0x0000 /* R/W 6 bits */ | ||
| 195 | #define _H3800_ASIC2_PWM_PeriodTime 0x0004 /* R/W 12 bits */ | ||
| 196 | #define _H3800_ASIC2_PWM_DutyTime 0x0008 /* R/W 12 bits */ | ||
| 197 | |||
| 198 | #define H3800_ASIC2_PWM_0_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 0, TimeBase ) | ||
| 199 | #define H3800_ASIC2_PWM_0_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 0, PeriodTime ) | ||
| 200 | #define H3800_ASIC2_PWM_0_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 0, DutyTime ) | ||
| 201 | |||
| 202 | #define H3800_ASIC2_PWM_1_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 1, TimeBase ) | ||
| 203 | #define H3800_ASIC2_PWM_1_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 1, PeriodTime ) | ||
| 204 | #define H3800_ASIC2_PWM_1_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 1, DutyTime ) | ||
| 205 | |||
| 206 | #define H3800_ASIC2_PWM_TIMEBASE_MASK 0xf /* Low 4 bits sets time base, max = 8 */ | ||
| 207 | #define H3800_ASIC2_PWM_TIMEBASE_ENABLE ( 1 << 4 ) /* Enable clock */ | ||
| 208 | #define H3800_ASIC2_PWM_TIMEBASE_CLEAR ( 1 << 5 ) /* Clear the PWM */ | ||
| 209 | |||
| 210 | #define _H3800_ASIC2_LED_0_Base 0x0800 | ||
| 211 | #define _H3800_ASIC2_LED_1_Base 0x0880 | ||
| 212 | #define _H3800_ASIC2_LED_2_Base 0x0900 | ||
| 213 | #define _H3800_ASIC2_LED_TimeBase 0x0000 /* R/W 7 bits */ | ||
| 214 | #define _H3800_ASIC2_LED_PeriodTime 0x0004 /* R/W 12 bits */ | ||
| 215 | #define _H3800_ASIC2_LED_DutyTime 0x0008 /* R/W 12 bits */ | ||
| 216 | #define _H3800_ASIC2_LED_AutoStopCount 0x000c /* R/W 16 bits */ | ||
| 217 | |||
| 218 | #define H3800_ASIC2_LED_0_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 0, TimeBase ) | ||
| 219 | #define H3800_ASIC2_LED_0_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 0, PeriodTime ) | ||
| 220 | #define H3800_ASIC2_LED_0_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 0, DutyTime ) | ||
| 221 | #define H3800_ASIC2_LED_0_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 0, AutoStopClock ) | ||
| 222 | |||
| 223 | #define H3800_ASIC2_LED_1_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 1, TimeBase ) | ||
| 224 | #define H3800_ASIC2_LED_1_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 1, PeriodTime ) | ||
| 225 | #define H3800_ASIC2_LED_1_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 1, DutyTime ) | ||
| 226 | #define H3800_ASIC2_LED_1_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 1, AutoStopClock ) | ||
| 227 | |||
| 228 | #define H3800_ASIC2_LED_2_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 2, TimeBase ) | ||
| 229 | #define H3800_ASIC2_LED_2_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 2, PeriodTime ) | ||
| 230 | #define H3800_ASIC2_LED_2_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 2, DutyTime ) | ||
| 231 | #define H3800_ASIC2_LED_2_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 2, AutoStopClock ) | ||
| 232 | |||
| 233 | #define H3800_ASIC2_LED_TIMEBASE_MASK 0x0f /* Low 4 bits sets time base, max = 13 */ | ||
| 234 | #define H3800_ASIC2_LED_TIMEBASE_BLINK ( 1 << 4 ) /* Enable blinking */ | ||
| 235 | #define H3800_ASIC2_LED_TIMEBASE_AUTOSTOP ( 1 << 5 ) | ||
| 236 | #define H3800_ASIC2_LED_TIMEBASE_ALWAYS ( 1 << 6 ) /* Enable blink always */ | ||
| 237 | |||
| 238 | #define _H3800_ASIC2_UART_0_Base 0x0A00 | ||
| 239 | #define _H3800_ASIC2_UART_1_Base 0x0C00 | ||
| 240 | #define _H3800_ASIC2_UART_Receive 0x0000 /* R 8 bits */ | ||
| 241 | #define _H3800_ASIC2_UART_Transmit 0x0000 /* W 8 bits */ | ||
| 242 | #define _H3800_ASIC2_UART_IntEnable 0x0004 /* R/W 8 bits */ | ||
| 243 | #define _H3800_ASIC2_UART_IntVerify 0x0008 /* R/W 8 bits */ | ||
| 244 | #define _H3800_ASIC2_UART_FIFOControl 0x000c /* R/W 8 bits */ | ||
| 245 | #define _H3800_ASIC2_UART_LineControl 0x0010 /* R/W 8 bits */ | ||
| 246 | #define _H3800_ASIC2_UART_ModemStatus 0x0014 /* R/W 8 bits */ | ||
| 247 | #define _H3800_ASIC2_UART_LineStatus 0x0018 /* R/W 8 bits */ | ||
| 248 | #define _H3800_ASIC2_UART_ScratchPad 0x001c /* R/W 8 bits */ | ||
| 249 | #define _H3800_ASIC2_UART_DivisorLatchL 0x0020 /* R/W 8 bits */ | ||
| 250 | #define _H3800_ASIC2_UART_DivisorLatchH 0x0024 /* R/W 8 bits */ | ||
| 251 | |||
| 252 | #define H3800_ASIC2_UART_0_Receive H3800_ASIC2_NOFFSET( u8, UART, 0, Receive ) | ||
| 253 | #define H3800_ASIC2_UART_0_Transmit H3800_ASIC2_NOFFSET( u8, UART, 0, Transmit ) | ||
| 254 | #define H3800_ASIC2_UART_0_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 0, IntEnable ) | ||
| 255 | #define H3800_ASIC2_UART_0_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 0, IntVerify ) | ||
| 256 | #define H3800_ASIC2_UART_0_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 0, FIFOControl ) | ||
| 257 | #define H3800_ASIC2_UART_0_LineControl H3800_ASIC2_NOFFSET( u8, UART, 0, LineControl ) | ||
| 258 | #define H3800_ASIC2_UART_0_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 0, ModemStatus ) | ||
| 259 | #define H3800_ASIC2_UART_0_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 0, LineStatus ) | ||
| 260 | #define H3800_ASIC2_UART_0_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 0, ScratchPad ) | ||
| 261 | #define H3800_ASIC2_UART_0_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchL ) | ||
| 262 | #define H3800_ASIC2_UART_0_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchH ) | ||
| 263 | |||
| 264 | #define H3800_ASIC2_UART_1_Receive H3800_ASIC2_NOFFSET( u8, UART, 1, Receive ) | ||
| 265 | #define H3800_ASIC2_UART_1_Transmit H3800_ASIC2_NOFFSET( u8, UART, 1, Transmit ) | ||
| 266 | #define H3800_ASIC2_UART_1_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 1, IntEnable ) | ||
| 267 | #define H3800_ASIC2_UART_1_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 1, IntVerify ) | ||
| 268 | #define H3800_ASIC2_UART_1_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 1, FIFOControl ) | ||
| 269 | #define H3800_ASIC2_UART_1_LineControl H3800_ASIC2_NOFFSET( u8, UART, 1, LineControl ) | ||
| 270 | #define H3800_ASIC2_UART_1_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 1, ModemStatus ) | ||
| 271 | #define H3800_ASIC2_UART_1_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 1, LineStatus ) | ||
| 272 | #define H3800_ASIC2_UART_1_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 1, ScratchPad ) | ||
| 273 | #define H3800_ASIC2_UART_1_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchL ) | ||
| 274 | #define H3800_ASIC2_UART_1_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchH ) | ||
| 275 | |||
| 276 | #define _H3800_ASIC2_TIMER_Base 0x0E00 | ||
| 277 | #define _H3800_ASIC2_TIMER_Command 0x0000 /* R/W 8 bits */ | ||
| 278 | |||
| 279 | #define H3800_ASIC2_TIMER_Command H3800_ASIC2_OFFSET( u8, Timer, Command ) | ||
| 280 | |||
| 281 | #define H3800_ASIC2_TIMER_GAT_0 ( 1 << 0 ) /* Gate enable, counter 0 */ | ||
| 282 | #define H3800_ASIC2_TIMER_GAT_1 ( 1 << 1 ) /* Gate enable, counter 1 */ | ||
| 283 | #define H3800_ASIC2_TIMER_GAT_2 ( 1 << 2 ) /* Gate enable, counter 2 */ | ||
| 284 | #define H3800_ASIC2_TIMER_CLK_0 ( 1 << 3 ) /* Clock enable, counter 0 */ | ||
| 285 | #define H3800_ASIC2_TIMER_CLK_1 ( 1 << 4 ) /* Clock enable, counter 1 */ | ||
| 286 | #define H3800_ASIC2_TIMER_CLK_2 ( 1 << 5 ) /* Clock enable, counter 2 */ | ||
| 287 | #define H3800_ASIC2_TIMER_MODE_0 ( 1 << 6 ) /* Mode 0 enable, counter 0 */ | ||
| 288 | #define H3800_ASIC2_TIMER_MODE_1 ( 1 << 7 ) /* Mode 0 enable, counter 1 */ | ||
| 289 | |||
| 290 | #define _H3800_ASIC2_CLOCK_Base 0x1000 | ||
| 291 | #define _H3800_ASIC2_CLOCK_Enable 0x0000 /* R/W 18 bits */ | ||
| 292 | |||
| 293 | #define H3800_ASIC2_CLOCK_Enable H3800_ASIC2_OFFSET( u32, CLOCK, Enable ) | ||
| 294 | |||
| 295 | #define H3800_ASIC2_CLOCK_AUDIO_1 0x0001 /* Enable 4.1 MHz clock for 8Khz and 4khz sample rate */ | ||
| 296 | #define H3800_ASIC2_CLOCK_AUDIO_2 0x0002 /* Enable 12.3 MHz clock for 48Khz and 32khz sample rate */ | ||
| 297 | #define H3800_ASIC2_CLOCK_AUDIO_3 0x0004 /* Enable 5.6 MHz clock for 11 kHZ sample rate */ | ||
| 298 | #define H3800_ASIC2_CLOCK_AUDIO_4 0x0008 /* Enable 11.289 MHz clock for 44 and 22 kHz sample rate */ | ||
| 299 | #define H3800_ASIC2_CLOCK_ADC ( 1 << 4 ) /* 1.024 MHz clock to ADC */ | ||
| 300 | #define H3800_ASIC2_CLOCK_SPI ( 1 << 5 ) /* 4.096 MHz clock to SPI */ | ||
| 301 | #define H3800_ASIC2_CLOCK_OWM ( 1 << 6 ) /* 4.096 MHz clock to OWM */ | ||
| 302 | #define H3800_ASIC2_CLOCK_PWM ( 1 << 7 ) /* 2.048 MHz clock to PWM */ | ||
| 303 | #define H3800_ASIC2_CLOCK_UART_1 ( 1 << 8 ) /* 24.576 MHz clock to UART1 (turn off bit 16) */ | ||
| 304 | #define H3800_ASIC2_CLOCK_UART_0 ( 1 << 9 ) /* 24.576 MHz clock to UART0 (turn off bit 17) */ | ||
| 305 | #define H3800_ASIC2_CLOCK_SD_1 ( 1 << 10 ) /* 16.934 MHz to SD */ | ||
| 306 | #define H3800_ASIC2_CLOCK_SD_2 ( 2 << 10 ) /* 24.576 MHz to SD */ | ||
| 307 | #define H3800_ASIC2_CLOCK_SD_3 ( 3 << 10 ) /* 33.869 MHz to SD */ | ||
| 308 | #define H3800_ASIC2_CLOCK_SD_4 ( 4 << 10 ) /* 49.152 MHz to SD */ | ||
| 309 | #define H3800_ASIC2_CLOCK_EX0 ( 1 << 13 ) /* Enable 32.768 kHz crystal */ | ||
| 310 | #define H3800_ASIC2_CLOCK_EX1 ( 1 << 14 ) /* Enable 24.576 MHz crystal */ | ||
| 311 | #define H3800_ASIC2_CLOCK_EX2 ( 1 << 15 ) /* Enable 33.869 MHz crystal */ | ||
| 312 | #define H3800_ASIC2_CLOCK_SLOW_UART_1 ( 1 << 16 ) /* Enable 3.686 MHz to UART1 (turn off bit 8) */ | ||
| 313 | #define H3800_ASIC2_CLOCK_SLOW_UART_0 ( 1 << 17 ) /* Enable 3.686 MHz to UART0 (turn off bit 9) */ | ||
| 314 | |||
| 315 | #define _H3800_ASIC2_ADC_Base 0x1200 | ||
| 316 | #define _H3800_ASIC2_ADC_Multiplexer 0x0000 /* R/W 4 bits - low 3 bits set channel */ | ||
| 317 | #define _H3800_ASIC2_ADC_ControlStatus 0x0004 /* R/W 8 bits */ | ||
| 318 | #define _H3800_ASIC2_ADC_Data 0x0008 /* R 10 bits */ | ||
| 319 | |||
| 320 | #define H3800_ASIC2_ADC_Multiplexer H3800_ASIC2_OFFSET( u8, ADC, Multiplexer ) | ||
| 321 | #define H3800_ASIC2_ADC_ControlStatus H3800_ASIC2_OFFSET( u8, ADC, ControlStatus ) | ||
| 322 | #define H3800_ASIC2_ADC_Data H3800_ASIC2_OFFSET( u16, ADC, Data ) | ||
| 323 | |||
| 324 | #define H3600_ASIC2_ADC_MUX_CHANNEL_MASK 0x07 /* Low 3 bits sets channel. max = 4 */ | ||
| 325 | #define H3600_ASIC2_ADC_MUX_CLKEN ( 1 << 3 ) /* Enable clock */ | ||
| 326 | |||
| 327 | #define H3600_ASIC2_ADC_CSR_ADPS_MASK 0x0f /* Low 4 bits sets prescale, max = 8 */ | ||
| 328 | #define H3600_ASIC2_ADC_CSR_FREE_RUN ( 1 << 4 ) | ||
| 329 | #define H3600_ASIC2_ADC_CSR_INT_ENABLE ( 1 << 5 ) | ||
| 330 | #define H3600_ASIC2_ADC_CSR_START ( 1 << 6 ) /* Set to start conversion. Goes to 0 when done */ | ||
| 331 | #define H3600_ASIC2_ADC_CSR_ENABLE ( 1 << 7 ) /* 1:power up ADC, 0:power down */ | ||
| 332 | |||
| 333 | |||
| 334 | #define _H3800_ASIC2_INTR_Base 0x1600 | ||
| 335 | #define _H3800_ASIC2_INTR_MaskAndFlag 0x0000 /* R/(W) 8bits */ | ||
| 336 | #define _H3800_ASIC2_INTR_ClockPrescale 0x0004 /* R/(W) 5bits */ | ||
| 337 | #define _H3800_ASIC2_INTR_TimerSet 0x0008 /* R/(W) 8bits */ | ||
| 338 | |||
| 339 | #define H3800_ASIC2_INTR_MaskAndFlag H3800_ASIC2_OFFSET( u8, INTR, MaskAndFlag ) | ||
| 340 | #define H3800_ASIC2_INTR_ClockPrescale H3800_ASIC2_OFFSET( u8, INTR, ClockPrescale ) | ||
| 341 | #define H3800_ASIC2_INTR_TimerSet H3800_ASIC2_OFFSET( u8, INTR, TimerSet ) | ||
| 342 | |||
| 343 | #define H3800_ASIC2_INTR_GLOBAL_MASK ( 1 << 0 ) /* Global interrupt mask */ | ||
| 344 | #define H3800_ASIC2_INTR_POWER_ON_RESET ( 1 << 1 ) /* 01: Power on reset (bits 1 & 2 ) */ | ||
| 345 | #define H3800_ASIC2_INTR_EXTERNAL_RESET ( 2 << 1 ) /* 10: External reset (bits 1 & 2 ) */ | ||
| 346 | #define H3800_ASIC2_INTR_MASK_UART_0 ( 1 << 4 ) | ||
| 347 | #define H3800_ASIC2_INTR_MASK_UART_1 ( 1 << 5 ) | ||
| 348 | #define H3800_ASIC2_INTR_MASK_TIMER ( 1 << 6 ) | ||
| 349 | #define H3800_ASIC2_INTR_MASK_OWM ( 1 << 7 ) | ||
| 350 | |||
| 351 | #define H3800_ASIC2_INTR_CLOCK_PRESCALE 0x0f /* 4 bits, max 14 */ | ||
| 352 | #define H3800_ASIC2_INTR_SET ( 1 << 4 ) /* Time base enable */ | ||
| 353 | |||
| 354 | |||
| 355 | #define _H3800_ASIC2_OWM_Base 0x1800 | ||
| 356 | #define _H3800_ASIC2_OWM_Command 0x0000 /* R/W 4 bits command register */ | ||
| 357 | #define _H3800_ASIC2_OWM_Data 0x0004 /* R/W 8 bits, transmit / receive buffer */ | ||
| 358 | #define _H3800_ASIC2_OWM_Interrupt 0x0008 /* R/W Command register */ | ||
| 359 | #define _H3800_ASIC2_OWM_InterruptEnable 0x000c /* R/W Command register */ | ||
| 360 | #define _H3800_ASIC2_OWM_ClockDivisor 0x0010 /* R/W 5 bits of divisor and pre-scale */ | ||
| 361 | |||
| 362 | #define H3800_ASIC2_OWM_Command H3800_ASIC2_OFFSET( u8, OWM, Command ) | ||
| 363 | #define H3800_ASIC2_OWM_Data H3800_ASIC2_OFFSET( u8, OWM, Data ) | ||
| 364 | #define H3800_ASIC2_OWM_Interrupt H3800_ASIC2_OFFSET( u8, OWM, Interrupt ) | ||
| 365 | #define H3800_ASIC2_OWM_InterruptEnable H3800_ASIC2_OFFSET( u8, OWM, InterruptEnable ) | ||
| 366 | #define H3800_ASIC2_OWM_ClockDivisor H3800_ASIC2_OFFSET( u8, OWM, ClockDivisor ) | ||
| 367 | |||
| 368 | #define H3800_ASIC2_OWM_CMD_ONE_WIRE_RESET ( 1 << 0 ) /* Set to force reset on 1-wire bus */ | ||
| 369 | #define H3800_ASIC2_OWM_CMD_SRA ( 1 << 1 ) /* Set to switch to Search ROM accelerator mode */ | ||
| 370 | #define H3800_ASIC2_OWM_CMD_DQ_OUTPUT ( 1 << 2 ) /* Write only - forces bus low */ | ||
| 371 | #define H3800_ASIC2_OWM_CMD_DQ_INPUT ( 1 << 3 ) /* Read only - reflects state of bus */ | ||
| 372 | |||
| 373 | #define H3800_ASIC2_OWM_INT_PD ( 1 << 0 ) /* Presence detect */ | ||
| 374 | #define H3800_ASIC2_OWM_INT_PDR ( 1 << 1 ) /* Presence detect result */ | ||
| 375 | #define H3800_ASIC2_OWM_INT_TBE ( 1 << 2 ) /* Transmit buffer empty */ | ||
| 376 | #define H3800_ASIC2_OWM_INT_TEMT ( 1 << 3 ) /* Transmit shift register empty */ | ||
| 377 | #define H3800_ASIC2_OWM_INT_RBF ( 1 << 4 ) /* Receive buffer full */ | ||
| 378 | |||
| 379 | #define H3800_ASIC2_OWM_INTEN_EPD ( 1 << 0 ) /* Enable receive buffer full interrupt */ | ||
| 380 | #define H3800_ASIC2_OWM_INTEN_IAS ( 1 << 1 ) /* Enable transmit shift register empty interrupt */ | ||
| 381 | #define H3800_ASIC2_OWM_INTEN_ETBE ( 1 << 2 ) /* Enable transmit buffer empty interrupt */ | ||
| 382 | #define H3800_ASIC2_OWM_INTEN_ETMT ( 1 << 3 ) /* INTR active state */ | ||
| 383 | #define H3800_ASIC2_OWM_INTEN_ERBF ( 1 << 4 ) /* Enable presence detect interrupt */ | ||
| 384 | |||
| 385 | #define _H3800_ASIC2_FlashCtl_Base 0x1A00 | ||
| 386 | |||
| 387 | /****************************************************/ | ||
| 388 | /* H3800, ASIC #1 | ||
| 389 | * This ASIC is accesed through ASIC #2, and | ||
| 390 | * mapped into the 1c00 - 1f00 region | ||
| 391 | */ | ||
| 392 | |||
| 393 | #define H3800_ASIC1_OFFSET(s,x,y) \ | ||
| 394 | (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC1_ ## x ## _Base + (_H3800_ASIC1_ ## x ## _ ## y << 1)))) | ||
| 395 | |||
| 396 | #define _H3800_ASIC1_MMC_Base 0x1c00 | ||
| 397 | |||
| 398 | #define _H3800_ASIC1_MMC_StartStopClock 0x00 /* R/W 8bit */ | ||
| 399 | #define _H3800_ASIC1_MMC_Status 0x02 /* R See below, default 0x0040 */ | ||
| 400 | #define _H3800_ASIC1_MMC_ClockRate 0x04 /* R/W 8bit, low 3 bits are clock divisor */ | ||
| 401 | #define _H3800_ASIC1_MMC_SPIRegister 0x08 /* R/W 8bit, see below */ | ||
| 402 | #define _H3800_ASIC1_MMC_CmdDataCont 0x0a /* R/W 8bit, write to start MMC adapter */ | ||
| 403 | #define _H3800_ASIC1_MMC_ResponseTimeout 0x0c /* R/W 8bit, clocks before response timeout */ | ||
| 404 | #define _H3800_ASIC1_MMC_ReadTimeout 0x0e /* R/W 16bit, clocks before received data timeout */ | ||
| 405 | #define _H3800_ASIC1_MMC_BlockLength 0x10 /* R/W 10bit */ | ||
| 406 | #define _H3800_ASIC1_MMC_NumOfBlocks 0x12 /* R/W 16bit, in block mode, number of blocks */ | ||
| 407 | #define _H3800_ASIC1_MMC_InterruptMask 0x1a /* R/W 8bit */ | ||
| 408 | #define _H3800_ASIC1_MMC_CommandNumber 0x1c /* R/W 6 bits */ | ||
| 409 | #define _H3800_ASIC1_MMC_ArgumentH 0x1e /* R/W 16 bits */ | ||
| 410 | #define _H3800_ASIC1_MMC_ArgumentL 0x20 /* R/W 16 bits */ | ||
| 411 | #define _H3800_ASIC1_MMC_ResFifo 0x22 /* R 8 x 16 bits - contains response FIFO */ | ||
| 412 | #define _H3800_ASIC1_MMC_BufferPartFull 0x28 /* R/W 8 bits */ | ||
| 413 | |||
| 414 | #define H3800_ASIC1_MMC_StartStopClock H3800_ASIC1_OFFSET( u8, MMC, StartStopClock ) | ||
| 415 | #define H3800_ASIC1_MMC_Status H3800_ASIC1_OFFSET( u16, MMC, Status ) | ||
| 416 | #define H3800_ASIC1_MMC_ClockRate H3800_ASIC1_OFFSET( u8, MMC, ClockRate ) | ||
| 417 | #define H3800_ASIC1_MMC_SPIRegister H3800_ASIC1_OFFSET( u8, MMC, SPIRegister ) | ||
| 418 | #define H3800_ASIC1_MMC_CmdDataCont H3800_ASIC1_OFFSET( u8, MMC, CmdDataCont ) | ||
| 419 | #define H3800_ASIC1_MMC_ResponseTimeout H3800_ASIC1_OFFSET( u8, MMC, ResponseTimeout ) | ||
| 420 | #define H3800_ASIC1_MMC_ReadTimeout H3800_ASIC1_OFFSET( u16, MMC, ReadTimeout ) | ||
| 421 | #define H3800_ASIC1_MMC_BlockLength H3800_ASIC1_OFFSET( u16, MMC, BlockLength ) | ||
| 422 | #define H3800_ASIC1_MMC_NumOfBlocks H3800_ASIC1_OFFSET( u16, MMC, NumOfBlocks ) | ||
| 423 | #define H3800_ASIC1_MMC_InterruptMask H3800_ASIC1_OFFSET( u8, MMC, InterruptMask ) | ||
| 424 | #define H3800_ASIC1_MMC_CommandNumber H3800_ASIC1_OFFSET( u8, MMC, CommandNumber ) | ||
| 425 | #define H3800_ASIC1_MMC_ArgumentH H3800_ASIC1_OFFSET( u16, MMC, ArgumentH ) | ||
| 426 | #define H3800_ASIC1_MMC_ArgumentL H3800_ASIC1_OFFSET( u16, MMC, ArgumentL ) | ||
| 427 | #define H3800_ASIC1_MMC_ResFifo H3800_ASIC1_OFFSET( u16, MMC, ResFifo ) | ||
| 428 | #define H3800_ASIC1_MMC_BufferPartFull H3800_ASIC1_OFFSET( u8, MMC, BufferPartFull ) | ||
| 429 | |||
| 430 | #define H3800_ASIC1_MMC_STOP_CLOCK (1 << 0) /* Write to "StartStopClock" register */ | ||
| 431 | #define H3800_ASIC1_MMC_START_CLOCK (1 << 1) | ||
| 432 | |||
| 433 | #define H3800_ASIC1_MMC_STATUS_READ_TIMEOUT (1 << 0) | ||
| 434 | #define H3800_ASIC1_MMC_STATUS_RESPONSE_TIMEOUT (1 << 1) | ||
| 435 | #define H3800_ASIC1_MMC_STATUS_CRC_WRITE_ERROR (1 << 2) | ||
| 436 | #define H3800_ASIC1_MMC_STATUS_CRC_READ_ERROR (1 << 3) | ||
| 437 | #define H3800_ASIC1_MMC_STATUS_SPI_READ_ERROR (1 << 4) /* SPI data token error received */ | ||
| 438 | #define H3800_ASIC1_MMC_STATUS_CRC_RESPONSE_ERROR (1 << 5) | ||
| 439 | #define H3800_ASIC1_MMC_STATUS_FIFO_EMPTY (1 << 6) | ||
| 440 | #define H3800_ASIC1_MMC_STATUS_FIFO_FULL (1 << 7) | ||
| 441 | #define H3800_ASIC1_MMC_STATUS_CLOCK_ENABLE (1 << 8) /* MultiMediaCard clock stopped */ | ||
| 442 | #define H3800_ASIC1_MMC_STATUS_DATA_TRANSFER_DONE (1 << 11) /* Write operation, indicates transfer finished */ | ||
| 443 | #define H3800_ASIC1_MMC_STATUS_END_PROGRAM (1 << 12) /* End write and read operations */ | ||
| 444 | #define H3800_ASIC1_MMC_STATUS_END_COMMAND_RESPONSE (1 << 13) /* End command response */ | ||
| 445 | |||
| 446 | #define H3800_ASIC1_MMC_SPI_REG_SPI_ENABLE (1 << 0) /* Enables SPI mode */ | ||
| 447 | #define H3800_ASIC1_MMC_SPI_REG_CRC_ON (1 << 1) /* 1:turn on CRC */ | ||
| 448 | #define H3800_ASIC1_MMC_SPI_REG_SPI_CS_ENABLE (1 << 2) /* 1:turn on SPI CS */ | ||
| 449 | #define H3800_ASIC1_MMC_SPI_REG_CS_ADDRESS_MASK 0x38 /* Bits 3,4,5 are the SPI CS relative address */ | ||
| 450 | |||
| 451 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_NO_RESPONSE 0x00 | ||
| 452 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R1 0x01 | ||
| 453 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R2 0x02 | ||
| 454 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R3 0x03 | ||
| 455 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_DATA_ENABLE (1 << 2) /* This command contains a data transfer */ | ||
| 456 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_WRITE (1 << 3) /* This data transfer is a write */ | ||
| 457 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_STREAM_MODE (1 << 4) /* This data transfer is in stream mode */ | ||
| 458 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_BUSY_BIT (1 << 5) /* Busy signal expected after current cmd */ | ||
| 459 | #define H3800_ASIC1_MMC_CMD_DATA_CONT_INITIALIZE (1 << 6) /* Enables the 80 bits for initializing card */ | ||
| 460 | |||
| 461 | #define H3800_ASIC1_MMC_INT_MASK_DATA_TRANSFER_DONE (1 << 0) | ||
| 462 | #define H3800_ASIC1_MMC_INT_MASK_PROGRAM_DONE (1 << 1) | ||
| 463 | #define H3800_ASIC1_MMC_INT_MASK_END_COMMAND_RESPONSE (1 << 2) | ||
| 464 | #define H3800_ASIC1_MMC_INT_MASK_BUFFER_READY (1 << 3) | ||
| 465 | |||
| 466 | #define H3800_ASIC1_MMC_BUFFER_PART_FULL (1 << 0) | ||
| 467 | |||
| 468 | /********* GPIO **********/ | ||
| 469 | |||
| 470 | #define _H3800_ASIC1_GPIO_Base 0x1e00 | ||
| 471 | |||
| 472 | #define _H3800_ASIC1_GPIO_Mask 0x30 /* R/W 0:don't mask, 1:mask interrupt */ | ||
| 473 | #define _H3800_ASIC1_GPIO_Direction 0x32 /* R/W 0:input, 1:output */ | ||
| 474 | #define _H3800_ASIC1_GPIO_Out 0x34 /* R/W 0:output low, 1:output high */ | ||
| 475 | #define _H3800_ASIC1_GPIO_TriggerType 0x36 /* R/W 0:level, 1:edge */ | ||
| 476 | #define _H3800_ASIC1_GPIO_EdgeTrigger 0x38 /* R/W 0:falling, 1:rising */ | ||
| 477 | #define _H3800_ASIC1_GPIO_LevelTrigger 0x3A /* R/W 0:low, 1:high level detect */ | ||
| 478 | #define _H3800_ASIC1_GPIO_LevelStatus 0x3C /* R/W 0:none, 1:detect */ | ||
| 479 | #define _H3800_ASIC1_GPIO_EdgeStatus 0x3E /* R/W 0:none, 1:detect */ | ||
| 480 | #define _H3800_ASIC1_GPIO_State 0x40 /* R See masks below (default 0) */ | ||
| 481 | #define _H3800_ASIC1_GPIO_Reset 0x42 /* R/W See masks below (default 0x04) */ | ||
| 482 | #define _H3800_ASIC1_GPIO_SleepMask 0x44 /* R/W 0:don't mask, 1:mask trigger in sleep mode */ | ||
| 483 | #define _H3800_ASIC1_GPIO_SleepDir 0x46 /* R/W direction 0:input, 1:output in sleep mode */ | ||
| 484 | #define _H3800_ASIC1_GPIO_SleepOut 0x48 /* R/W level 0:low, 1:high in sleep mode */ | ||
| 485 | #define _H3800_ASIC1_GPIO_Status 0x4A /* R Pin status */ | ||
| 486 | #define _H3800_ASIC1_GPIO_BattFaultDir 0x4C /* R/W direction 0:input, 1:output in batt_fault */ | ||
| 487 | #define _H3800_ASIC1_GPIO_BattFaultOut 0x4E /* R/W level 0:low, 1:high in batt_fault */ | ||
| 488 | |||
| 489 | #define H3800_ASIC1_GPIO_Mask H3800_ASIC1_OFFSET( u16, GPIO, Mask ) | ||
| 490 | #define H3800_ASIC1_GPIO_Direction H3800_ASIC1_OFFSET( u16, GPIO, Direction ) | ||
| 491 | #define H3800_ASIC1_GPIO_Out H3800_ASIC1_OFFSET( u16, GPIO, Out ) | ||
| 492 | #define H3800_ASIC1_GPIO_TriggerType H3800_ASIC1_OFFSET( u16, GPIO, TriggerType ) | ||
| 493 | #define H3800_ASIC1_GPIO_EdgeTrigger H3800_ASIC1_OFFSET( u16, GPIO, EdgeTrigger ) | ||
| 494 | #define H3800_ASIC1_GPIO_LevelTrigger H3800_ASIC1_OFFSET( u16, GPIO, LevelTrigger ) | ||
| 495 | #define H3800_ASIC1_GPIO_LevelStatus H3800_ASIC1_OFFSET( u16, GPIO, LevelStatus ) | ||
| 496 | #define H3800_ASIC1_GPIO_EdgeStatus H3800_ASIC1_OFFSET( u16, GPIO, EdgeStatus ) | ||
| 497 | #define H3800_ASIC1_GPIO_State H3800_ASIC1_OFFSET( u8, GPIO, State ) | ||
| 498 | #define H3800_ASIC1_GPIO_Reset H3800_ASIC1_OFFSET( u8, GPIO, Reset ) | ||
| 499 | #define H3800_ASIC1_GPIO_SleepMask H3800_ASIC1_OFFSET( u16, GPIO, SleepMask ) | ||
| 500 | #define H3800_ASIC1_GPIO_SleepDir H3800_ASIC1_OFFSET( u16, GPIO, SleepDir ) | ||
| 501 | #define H3800_ASIC1_GPIO_SleepOut H3800_ASIC1_OFFSET( u16, GPIO, SleepOut ) | ||
| 502 | #define H3800_ASIC1_GPIO_Status H3800_ASIC1_OFFSET( u16, GPIO, Status ) | ||
| 503 | #define H3800_ASIC1_GPIO_BattFaultDir H3800_ASIC1_OFFSET( u16, GPIO, BattFaultDir ) | ||
| 504 | #define H3800_ASIC1_GPIO_BattFaultOut H3800_ASIC1_OFFSET( u16, GPIO, BattFaultOut ) | ||
| 505 | |||
| 506 | #define H3800_ASIC1_GPIO_STATE_MASK (1 << 0) | ||
| 507 | #define H3800_ASIC1_GPIO_STATE_DIRECTION (1 << 1) | ||
| 508 | #define H3800_ASIC1_GPIO_STATE_OUT (1 << 2) | ||
| 509 | #define H3800_ASIC1_GPIO_STATE_TRIGGER_TYPE (1 << 3) | ||
| 510 | #define H3800_ASIC1_GPIO_STATE_EDGE_TRIGGER (1 << 4) | ||
| 511 | #define H3800_ASIC1_GPIO_STATE_LEVEL_TRIGGER (1 << 5) | ||
| 512 | |||
| 513 | #define H3800_ASIC1_GPIO_RESET_SOFTWARE (1 << 0) | ||
| 514 | #define H3800_ASIC1_GPIO_RESET_AUTO_SLEEP (1 << 1) | ||
| 515 | #define H3800_ASIC1_GPIO_RESET_FIRST_PWR_ON (1 << 2) | ||
| 516 | |||
| 517 | /* These are all outputs */ | ||
| 518 | #define GPIO_H3800_ASIC1_IR_ON_N (1 << 0) /* Apply power to the IR Module */ | ||
| 519 | #define GPIO_H3800_ASIC1_SD_PWR_ON (1 << 1) /* Secure Digital power on */ | ||
| 520 | #define GPIO_H3800_ASIC1_RS232_ON (1 << 2) /* Turn on power to the RS232 chip ? */ | ||
| 521 | #define GPIO_H3800_ASIC1_PULSE_GEN (1 << 3) /* Goes to speaker / earphone */ | ||
| 522 | #define GPIO_H3800_ASIC1_CH_TIMER (1 << 4) /* */ | ||
| 523 | #define GPIO_H3800_ASIC1_LCD_5V_ON (1 << 5) /* Enables LCD_5V */ | ||
| 524 | #define GPIO_H3800_ASIC1_LCD_ON (1 << 6) /* Enables LCD_3V */ | ||
| 525 | #define GPIO_H3800_ASIC1_LCD_PCI (1 << 7) /* Connects to PDWN on LCD controller */ | ||
| 526 | #define GPIO_H3800_ASIC1_VGH_ON (1 << 8) /* Drives VGH on the LCD (+9??) */ | ||
| 527 | #define GPIO_H3800_ASIC1_VGL_ON (1 << 9) /* Drivers VGL on the LCD (-6??) */ | ||
| 528 | #define GPIO_H3800_ASIC1_FL_PWR_ON (1 << 10) /* Frontlight power on */ | ||
| 529 | #define GPIO_H3800_ASIC1_BT_PWR_ON (1 << 11) /* Bluetooth power on */ | ||
| 530 | #define GPIO_H3800_ASIC1_SPK_ON (1 << 12) /* */ | ||
| 531 | #define GPIO_H3800_ASIC1_EAR_ON_N (1 << 13) /* */ | ||
| 532 | #define GPIO_H3800_ASIC1_AUD_PWR_ON (1 << 14) /* */ | ||
| 533 | |||
| 534 | /* Write enable for the flash */ | ||
| 535 | |||
| 536 | #define _H3800_ASIC1_FlashWP_Base 0x1F00 | ||
| 537 | #define _H3800_ASIC1_FlashWP_VPP_ON 0x00 /* R 1: write, 0: protect */ | ||
| 538 | #define H3800_ASIC1_FlashWP_VPP_ON H3800_ASIC1_OFFSET( u8, FlashWP, VPP_ON ) | ||
| 539 | 76 | ||
| 540 | #endif /* _INCLUDE_H3600_GPIO_H_ */ | 77 | #endif /* _INCLUDE_H3600_GPIO_H_ */ |
diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h index 0cb36609b3ac..ae81f80b0cf9 100644 --- a/arch/arm/mach-sa1100/include/mach/irqs.h +++ b/arch/arm/mach-sa1100/include/mach/irqs.h | |||
| @@ -153,8 +153,6 @@ | |||
| 153 | */ | 153 | */ |
| 154 | #ifdef CONFIG_SA1111 | 154 | #ifdef CONFIG_SA1111 |
| 155 | #define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1) | 155 | #define NR_IRQS (IRQ_S1_BVD1_STSCHG + 1) |
| 156 | #elif defined(CONFIG_SA1100_H3800) | ||
| 157 | #define NR_IRQS (IRQ_BOARD_END) | ||
| 158 | #elif defined(CONFIG_SHARP_LOCOMO) | 156 | #elif defined(CONFIG_SHARP_LOCOMO) |
| 159 | #define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) | 157 | #define NR_IRQS (IRQ_LOCOMO_SPI_TEND + 1) |
| 160 | #else | 158 | #else |
| @@ -175,23 +173,3 @@ | |||
| 175 | #define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) | 173 | #define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) |
| 176 | #define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) | 174 | #define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) |
| 177 | 175 | ||
| 178 | /* H3800-specific IRQs (CONFIG_SA1100_H3800) */ | ||
| 179 | #define H3800_KPIO_IRQ_START (IRQ_BOARD_START) | ||
| 180 | #define IRQ_H3800_KEY (IRQ_BOARD_START + 0) | ||
| 181 | #define IRQ_H3800_SPI (IRQ_BOARD_START + 1) | ||
| 182 | #define IRQ_H3800_OWM (IRQ_BOARD_START + 2) | ||
| 183 | #define IRQ_H3800_ADC (IRQ_BOARD_START + 3) | ||
| 184 | #define IRQ_H3800_UART_0 (IRQ_BOARD_START + 4) | ||
| 185 | #define IRQ_H3800_UART_1 (IRQ_BOARD_START + 5) | ||
| 186 | #define IRQ_H3800_TIMER_0 (IRQ_BOARD_START + 6) | ||
| 187 | #define IRQ_H3800_TIMER_1 (IRQ_BOARD_START + 7) | ||
| 188 | #define IRQ_H3800_TIMER_2 (IRQ_BOARD_START + 8) | ||
| 189 | #define H3800_KPIO_IRQ_COUNT 9 | ||
| 190 | |||
| 191 | #define H3800_GPIO_IRQ_START (IRQ_BOARD_START + 9) | ||
| 192 | #define IRQ_H3800_PEN (IRQ_BOARD_START + 9) | ||
| 193 | #define IRQ_H3800_SD_DETECT (IRQ_BOARD_START + 10) | ||
| 194 | #define IRQ_H3800_EAR_IN (IRQ_BOARD_START + 11) | ||
| 195 | #define IRQ_H3800_USB_DETECT (IRQ_BOARD_START + 12) | ||
| 196 | #define IRQ_H3800_SD_CON_SLT (IRQ_BOARD_START + 13) | ||
| 197 | #define H3800_GPIO_IRQ_COUNT 5 | ||
diff --git a/arch/arm/mach-sa1100/include/mach/system.h b/arch/arm/mach-sa1100/include/mach/system.h index 63755ca5b1b4..942b153e251d 100644 --- a/arch/arm/mach-sa1100/include/mach/system.h +++ b/arch/arm/mach-sa1100/include/mach/system.h | |||
| @@ -10,7 +10,7 @@ static inline void arch_idle(void) | |||
| 10 | cpu_do_idle(); | 10 | cpu_do_idle(); |
| 11 | } | 11 | } |
| 12 | 12 | ||
| 13 | static inline void arch_reset(char mode) | 13 | static inline void arch_reset(char mode, const char *cmd) |
| 14 | { | 14 | { |
| 15 | if (mode == 's') { | 15 | if (mode == 's') { |
| 16 | /* Jump into ROM at address 0 */ | 16 | /* Jump into ROM at address 0 */ |
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c index 81848aa96424..fd776bb666cd 100644 --- a/arch/arm/mach-sa1100/jornada720.c +++ b/arch/arm/mach-sa1100/jornada720.c | |||
| @@ -226,12 +226,22 @@ static struct platform_device jornada_ssp_device = { | |||
| 226 | .id = -1, | 226 | .id = -1, |
| 227 | }; | 227 | }; |
| 228 | 228 | ||
| 229 | static struct platform_device jornada_kbd_device = { | ||
| 230 | .name = "jornada720_kbd", | ||
| 231 | .id = -1, | ||
| 232 | }; | ||
| 233 | |||
| 234 | static struct platform_device jornada_ts_device = { | ||
| 235 | .name = "jornada_ts", | ||
| 236 | .id = -1, | ||
| 237 | }; | ||
| 238 | |||
| 229 | static struct platform_device *devices[] __initdata = { | 239 | static struct platform_device *devices[] __initdata = { |
| 230 | &sa1111_device, | 240 | &sa1111_device, |
| 231 | #ifdef CONFIG_SA1100_JORNADA720_SSP | ||
| 232 | &jornada_ssp_device, | 241 | &jornada_ssp_device, |
| 233 | #endif | ||
| 234 | &s1d13xxxfb_device, | 242 | &s1d13xxxfb_device, |
| 243 | &jornada_kbd_device, | ||
| 244 | &jornada_ts_device, | ||
| 235 | }; | 245 | }; |
| 236 | 246 | ||
| 237 | static int __init jornada720_init(void) | 247 | static int __init jornada720_init(void) |
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c index a23fd3d0163a..358d875ace14 100644 --- a/arch/arm/mach-shark/core.c +++ b/arch/arm/mach-shark/core.c | |||
| @@ -16,12 +16,28 @@ | |||
| 16 | #include <asm/leds.h> | 16 | #include <asm/leds.h> |
| 17 | #include <asm/param.h> | 17 | #include <asm/param.h> |
| 18 | 18 | ||
| 19 | #include <mach/hardware.h> | ||
| 20 | |||
| 21 | #include <asm/mach/map.h> | 19 | #include <asm/mach/map.h> |
| 22 | #include <asm/mach/arch.h> | 20 | #include <asm/mach/arch.h> |
| 23 | #include <asm/mach/time.h> | 21 | #include <asm/mach/time.h> |
| 24 | 22 | ||
| 23 | #define IO_BASE 0xe0000000 | ||
| 24 | #define IO_SIZE 0x08000000 | ||
| 25 | #define IO_START 0x40000000 | ||
| 26 | #define ROMCARD_SIZE 0x08000000 | ||
| 27 | #define ROMCARD_START 0x10000000 | ||
| 28 | |||
| 29 | void arch_reset(char mode, const char *cmd) | ||
| 30 | { | ||
| 31 | short temp; | ||
| 32 | local_irq_disable(); | ||
| 33 | /* Reset the Machine via pc[3] of the sequoia chipset */ | ||
| 34 | outw(0x09,0x24); | ||
| 35 | temp=inw(0x26); | ||
| 36 | temp = temp | (1<<3) | (1<<10); | ||
| 37 | outw(0x09,0x24); | ||
| 38 | outw(temp,0x26); | ||
| 39 | } | ||
| 40 | |||
| 25 | static struct plat_serial8250_port serial_platform_data[] = { | 41 | static struct plat_serial8250_port serial_platform_data[] = { |
| 26 | { | 42 | { |
| 27 | .iobase = 0x3f8, | 43 | .iobase = 0x3f8, |
| @@ -50,14 +66,38 @@ static struct platform_device serial_device = { | |||
| 50 | }, | 66 | }, |
| 51 | }; | 67 | }; |
| 52 | 68 | ||
| 69 | static struct resource rtc_resources[] = { | ||
| 70 | [0] = { | ||
| 71 | .start = 0x70, | ||
| 72 | .end = 0x73, | ||
| 73 | .flags = IORESOURCE_IO, | ||
| 74 | }, | ||
| 75 | [1] = { | ||
| 76 | .start = IRQ_ISA_RTC_ALARM, | ||
| 77 | .end = IRQ_ISA_RTC_ALARM, | ||
| 78 | .flags = IORESOURCE_IRQ, | ||
| 79 | } | ||
| 80 | }; | ||
| 81 | |||
| 82 | static struct platform_device rtc_device = { | ||
| 83 | .name = "rtc_cmos", | ||
| 84 | .id = -1, | ||
| 85 | .resource = rtc_resources, | ||
| 86 | .num_resources = ARRAY_SIZE(rtc_resources), | ||
| 87 | }; | ||
| 88 | |||
| 53 | static int __init shark_init(void) | 89 | static int __init shark_init(void) |
| 54 | { | 90 | { |
| 55 | int ret; | 91 | int ret; |
| 56 | 92 | ||
| 57 | if (machine_is_shark()) | 93 | if (machine_is_shark()) |
| 94 | { | ||
| 95 | ret = platform_device_register(&rtc_device); | ||
| 96 | if (ret) printk(KERN_ERR "Unable to register RTC device: %d\n", ret); | ||
| 58 | ret = platform_device_register(&serial_device); | 97 | ret = platform_device_register(&serial_device); |
| 59 | 98 | if (ret) printk(KERN_ERR "Unable to register Serial device: %d\n", ret); | |
| 60 | return ret; | 99 | } |
| 100 | return 0; | ||
| 61 | } | 101 | } |
| 62 | 102 | ||
| 63 | arch_initcall(shark_init); | 103 | arch_initcall(shark_init); |
diff --git a/arch/arm/mach-shark/dma.c b/arch/arm/mach-shark/dma.c index 6774b8d5d13d..10b5b8b3272a 100644 --- a/arch/arm/mach-shark/dma.c +++ b/arch/arm/mach-shark/dma.c | |||
| @@ -13,9 +13,11 @@ | |||
| 13 | #include <asm/dma.h> | 13 | #include <asm/dma.h> |
| 14 | #include <asm/mach/dma.h> | 14 | #include <asm/mach/dma.h> |
| 15 | 15 | ||
| 16 | void __init arch_dma_init(dma_t *dma) | 16 | static int __init shark_dma_init(void) |
| 17 | { | 17 | { |
| 18 | #ifdef CONFIG_ISA_DMA | 18 | #ifdef CONFIG_ISA_DMA |
| 19 | isa_init_dma(dma); | 19 | isa_init_dma(); |
| 20 | #endif | 20 | #endif |
| 21 | return 0; | ||
| 21 | } | 22 | } |
| 23 | core_initcall(shark_dma_init); | ||
diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S index 0836cb78b29a..f97a7626bd58 100644 --- a/arch/arm/mach-shark/include/mach/debug-macro.S +++ b/arch/arm/mach-shark/include/mach/debug-macro.S | |||
| @@ -27,5 +27,3 @@ | |||
| 27 | bne 1001b | 27 | bne 1001b |
| 28 | .endm | 28 | .endm |
| 29 | 29 | ||
| 30 | .macro waituart,rd,rx | ||
| 31 | .endm | ||
diff --git a/arch/arm/mach-shark/include/mach/framebuffer.h b/arch/arm/mach-shark/include/mach/framebuffer.h new file mode 100644 index 000000000000..84a5bf6e5ba3 --- /dev/null +++ b/arch/arm/mach-shark/include/mach/framebuffer.h | |||
| @@ -0,0 +1,16 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mach-shark/include/mach/framebuffer.h | ||
| 3 | * | ||
| 4 | * by Alexander Schulz | ||
| 5 | * | ||
| 6 | */ | ||
| 7 | |||
| 8 | #ifndef __ASM_ARCH_FRAMEBUFFER_H | ||
| 9 | #define __ASM_ARCH_FRAMEBUFFER_H | ||
| 10 | |||
| 11 | /* defines for the Framebuffer */ | ||
| 12 | #define FB_START 0x06000000 | ||
| 13 | #define FB_SIZE 0x01000000 | ||
| 14 | |||
| 15 | #endif | ||
| 16 | |||
diff --git a/arch/arm/mach-shark/include/mach/hardware.h b/arch/arm/mach-shark/include/mach/hardware.h index 01bf76099ce5..94d84b27a0cb 100644 --- a/arch/arm/mach-shark/include/mach/hardware.h +++ b/arch/arm/mach-shark/include/mach/hardware.h | |||
| @@ -10,35 +10,8 @@ | |||
| 10 | #ifndef __ASM_ARCH_HARDWARE_H | 10 | #ifndef __ASM_ARCH_HARDWARE_H |
| 11 | #define __ASM_ARCH_HARDWARE_H | 11 | #define __ASM_ARCH_HARDWARE_H |
| 12 | 12 | ||
| 13 | #ifndef __ASSEMBLY__ | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Mapping areas | ||
| 17 | */ | ||
| 18 | #define IO_BASE 0xe0000000 | ||
| 19 | |||
| 20 | #else | ||
| 21 | |||
| 22 | #define IO_BASE 0 | ||
| 23 | |||
| 24 | #endif | ||
| 25 | |||
| 26 | #define IO_SIZE 0x08000000 | ||
| 27 | #define IO_START 0x40000000 | ||
| 28 | #define ROMCARD_SIZE 0x08000000 | ||
| 29 | #define ROMCARD_START 0x10000000 | ||
| 30 | |||
| 31 | |||
| 32 | /* defines for the Framebuffer */ | ||
| 33 | #define FB_START 0x06000000 | ||
| 34 | #define FB_SIZE 0x01000000 | ||
| 35 | |||
| 36 | #define UNCACHEABLE_ADDR 0xdf010000 | 13 | #define UNCACHEABLE_ADDR 0xdf010000 |
| 37 | 14 | ||
| 38 | #define SEQUOIA_LED_GREEN (1<<6) | ||
| 39 | #define SEQUOIA_LED_AMBER (1<<5) | ||
| 40 | #define SEQUOIA_LED_BACK (1<<7) | ||
| 41 | |||
| 42 | #define pcibios_assign_all_busses() 1 | 15 | #define pcibios_assign_all_busses() 1 |
| 43 | 16 | ||
| 44 | #define PCIBIOS_MIN_IO 0x6000 | 17 | #define PCIBIOS_MIN_IO 0x6000 |
diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h index c5cee829fc87..9ccbcecc430b 100644 --- a/arch/arm/mach-shark/include/mach/io.h +++ b/arch/arm/mach-shark/include/mach/io.h | |||
| @@ -11,10 +11,10 @@ | |||
| 11 | #ifndef __ASM_ARM_ARCH_IO_H | 11 | #ifndef __ASM_ARM_ARCH_IO_H |
| 12 | #define __ASM_ARM_ARCH_IO_H | 12 | #define __ASM_ARM_ARCH_IO_H |
| 13 | 13 | ||
| 14 | #define PCIO_BASE 0xe0000000 | 14 | #define IO_SPACE_LIMIT 0xffffffff |
| 15 | #define IO_SPACE_LIMIT 0xffffffff | ||
| 16 | 15 | ||
| 17 | #define __io(a) ((void __iomem *)(PCIO_BASE + (a))) | 16 | #define __io(a) ((void __iomem *)(0xe0000000 + (a))) |
| 18 | #define __mem_pci(addr) (addr) | 17 | |
| 18 | #define __mem_pci(addr) (addr) | ||
| 19 | 19 | ||
| 20 | #endif | 20 | #endif |
diff --git a/arch/arm/mach-shark/include/mach/irqs.h b/arch/arm/mach-shark/include/mach/irqs.h index 0586acd7cdd5..c8e8a4e1f61a 100644 --- a/arch/arm/mach-shark/include/mach/irqs.h +++ b/arch/arm/mach-shark/include/mach/irqs.h | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | #define NR_IRQS 16 | 7 | #define NR_IRQS 16 |
| 8 | 8 | ||
| 9 | #define IRQ_ISA_KEYBOARD 1 | 9 | #define IRQ_ISA_KEYBOARD 1 |
| 10 | #define RTC_IRQ 8 | 10 | #define IRQ_ISA_RTC_ALARM 8 |
| 11 | #define I8042_KBD_IRQ 1 | 11 | #define I8042_KBD_IRQ 1 |
| 12 | #define I8042_AUX_IRQ 12 | 12 | #define I8042_AUX_IRQ 12 |
| 13 | #define IRQ_HARDDISK 14 | 13 | #define IRQ_HARDDISK 14 |
diff --git a/arch/arm/mach-shark/include/mach/isa-dma.h b/arch/arm/mach-shark/include/mach/isa-dma.h index 864298ff3927..96c43b8f8dda 100644 --- a/arch/arm/mach-shark/include/mach/isa-dma.h +++ b/arch/arm/mach-shark/include/mach/isa-dma.h | |||
| @@ -6,10 +6,6 @@ | |||
| 6 | #ifndef __ASM_ARCH_DMA_H | 6 | #ifndef __ASM_ARCH_DMA_H |
| 7 | #define __ASM_ARCH_DMA_H | 7 | #define __ASM_ARCH_DMA_H |
| 8 | 8 | ||
| 9 | /* Use only the lowest 4MB, nothing else works. | ||
| 10 | * The rest is not DMAable. See dev / .properties | ||
| 11 | * in OpenFirmware. | ||
| 12 | */ | ||
| 13 | #define MAX_DMA_CHANNELS 8 | 9 | #define MAX_DMA_CHANNELS 8 |
| 14 | #define DMA_ISA_CASCADE 4 | 10 | #define DMA_ISA_CASCADE 4 |
| 15 | 11 | ||
diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h index c5ab038925d6..3053e5b7f168 100644 --- a/arch/arm/mach-shark/include/mach/memory.h +++ b/arch/arm/mach-shark/include/mach/memory.h | |||
| @@ -23,6 +23,7 @@ static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsig | |||
| 23 | { | 23 | { |
| 24 | if (node != 0) return; | 24 | if (node != 0) return; |
| 25 | /* Only the first 4 MB (=1024 Pages) are usable for DMA */ | 25 | /* Only the first 4 MB (=1024 Pages) are usable for DMA */ |
| 26 | /* See dev / -> .properties in OpenFirmware. */ | ||
| 26 | zone_size[1] = zone_size[0] - 1024; | 27 | zone_size[1] = zone_size[0] - 1024; |
| 27 | zone_size[0] = 1024; | 28 | zone_size[0] = 1024; |
| 28 | zhole_size[1] = zhole_size[0]; | 29 | zhole_size[1] = zhole_size[0]; |
diff --git a/arch/arm/mach-shark/include/mach/system.h b/arch/arm/mach-shark/include/mach/system.h index e45bd734a03e..21c373b30bbc 100644 --- a/arch/arm/mach-shark/include/mach/system.h +++ b/arch/arm/mach-shark/include/mach/system.h | |||
| @@ -6,20 +6,8 @@ | |||
| 6 | #ifndef __ASM_ARCH_SYSTEM_H | 6 | #ifndef __ASM_ARCH_SYSTEM_H |
| 7 | #define __ASM_ARCH_SYSTEM_H | 7 | #define __ASM_ARCH_SYSTEM_H |
| 8 | 8 | ||
| 9 | #include <linux/io.h> | 9 | /* Found in arch/mach-shark/core.c */ |
| 10 | 10 | extern void arch_reset(char mode, const char *cmd); | |
| 11 | static void arch_reset(char mode) | ||
| 12 | { | ||
| 13 | short temp; | ||
| 14 | local_irq_disable(); | ||
| 15 | /* Reset the Machine via pc[3] of the sequoia chipset */ | ||
| 16 | outw(0x09,0x24); | ||
| 17 | temp=inw(0x26); | ||
| 18 | temp = temp | (1<<3) | (1<<10); | ||
| 19 | outw(0x09,0x24); | ||
| 20 | outw(temp,0x26); | ||
| 21 | |||
| 22 | } | ||
| 23 | 11 | ||
| 24 | static inline void arch_idle(void) | 12 | static inline void arch_idle(void) |
| 25 | { | 13 | { |
diff --git a/arch/arm/mach-shark/include/mach/uncompress.h b/arch/arm/mach-shark/include/mach/uncompress.h index 3725e1633418..22ccab4c3c5e 100644 --- a/arch/arm/mach-shark/include/mach/uncompress.h +++ b/arch/arm/mach-shark/include/mach/uncompress.h | |||
| @@ -11,7 +11,7 @@ | |||
| 11 | 11 | ||
| 12 | static inline void putc(int c) | 12 | static inline void putc(int c) |
| 13 | { | 13 | { |
| 14 | int t; | 14 | volatile int t; |
| 15 | 15 | ||
| 16 | SERIAL_BASE[0] = c; | 16 | SERIAL_BASE[0] = c; |
| 17 | t=0x10000; | 17 | t=0x10000; |
diff --git a/arch/arm/mach-shark/leds.c b/arch/arm/mach-shark/leds.c index 8bd8d6bb4d92..c9e32de4adf9 100644 --- a/arch/arm/mach-shark/leds.c +++ b/arch/arm/mach-shark/leds.c | |||
| @@ -22,12 +22,16 @@ | |||
| 22 | #include <linux/ioport.h> | 22 | #include <linux/ioport.h> |
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | 24 | ||
| 25 | #include <mach/hardware.h> | ||
| 26 | #include <asm/leds.h> | 25 | #include <asm/leds.h> |
| 27 | #include <asm/system.h> | 26 | #include <asm/system.h> |
| 28 | 27 | ||
| 29 | #define LED_STATE_ENABLED 1 | 28 | #define LED_STATE_ENABLED 1 |
| 30 | #define LED_STATE_CLAIMED 2 | 29 | #define LED_STATE_CLAIMED 2 |
| 30 | |||
| 31 | #define SEQUOIA_LED_GREEN (1<<6) | ||
| 32 | #define SEQUOIA_LED_AMBER (1<<5) | ||
| 33 | #define SEQUOIA_LED_BACK (1<<7) | ||
| 34 | |||
| 31 | static char led_state; | 35 | static char led_state; |
| 32 | static short hw_led_state; | 36 | static short hw_led_state; |
| 33 | static short saved_state; | 37 | static short saved_state; |
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index 1c43494f5c42..565776680d8c 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c | |||
| @@ -335,11 +335,25 @@ static struct resource versatile_i2c_resource = { | |||
| 335 | 335 | ||
| 336 | static struct platform_device versatile_i2c_device = { | 336 | static struct platform_device versatile_i2c_device = { |
| 337 | .name = "versatile-i2c", | 337 | .name = "versatile-i2c", |
| 338 | .id = -1, | 338 | .id = 0, |
| 339 | .num_resources = 1, | 339 | .num_resources = 1, |
| 340 | .resource = &versatile_i2c_resource, | 340 | .resource = &versatile_i2c_resource, |
| 341 | }; | 341 | }; |
| 342 | 342 | ||
| 343 | static struct i2c_board_info versatile_i2c_board_info[] = { | ||
| 344 | { | ||
| 345 | I2C_BOARD_INFO("rtc-ds1307", 0xd0 >> 1), | ||
| 346 | .type = "ds1338", | ||
| 347 | }, | ||
| 348 | }; | ||
| 349 | |||
| 350 | static int __init versatile_i2c_init(void) | ||
| 351 | { | ||
| 352 | return i2c_register_board_info(0, versatile_i2c_board_info, | ||
| 353 | ARRAY_SIZE(versatile_i2c_board_info)); | ||
| 354 | } | ||
| 355 | arch_initcall(versatile_i2c_init); | ||
| 356 | |||
| 343 | #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET) | 357 | #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET) |
| 344 | 358 | ||
| 345 | unsigned int mmc_status(struct device *dev) | 359 | unsigned int mmc_status(struct device *dev) |
diff --git a/arch/arm/mach-versatile/include/mach/system.h b/arch/arm/mach-versatile/include/mach/system.h index c59e6100c7e3..8ffc12a7cb25 100644 --- a/arch/arm/mach-versatile/include/mach/system.h +++ b/arch/arm/mach-versatile/include/mach/system.h | |||
| @@ -34,7 +34,7 @@ static inline void arch_idle(void) | |||
| 34 | cpu_do_idle(); | 34 | cpu_do_idle(); |
| 35 | } | 35 | } |
| 36 | 36 | ||
| 37 | static inline void arch_reset(char mode) | 37 | static inline void arch_reset(char mode, const char *cmd) |
| 38 | { | 38 | { |
| 39 | u32 val; | 39 | u32 val; |
| 40 | 40 | ||
diff --git a/arch/arm/mach-w90x900/cpu.h b/arch/arm/mach-w90x900/cpu.h index 40ff40845df0..de29ddcb9459 100644 --- a/arch/arm/mach-w90x900/cpu.h +++ b/arch/arm/mach-w90x900/cpu.h | |||
| @@ -43,35 +43,16 @@ extern void w90p910_init_io(struct map_desc *mach_desc, int size); | |||
| 43 | extern void w90p910_init_uarts(struct w90x900_uartcfg *cfg, int no); | 43 | extern void w90p910_init_uarts(struct w90x900_uartcfg *cfg, int no); |
| 44 | extern void w90p910_init_clocks(int xtal); | 44 | extern void w90p910_init_clocks(int xtal); |
| 45 | extern void w90p910_map_io(struct map_desc *mach_desc, int size); | 45 | extern void w90p910_map_io(struct map_desc *mach_desc, int size); |
| 46 | extern struct platform_device w90p910_serial_device; | ||
| 46 | extern struct sys_timer w90x900_timer; | 47 | extern struct sys_timer w90x900_timer; |
| 47 | 48 | ||
| 48 | #define W90X900_RES(name) \ | 49 | #define W90X900_8250PORT(name) \ |
| 49 | struct resource w90x900_##name##_resource[] = { \ | 50 | { \ |
| 50 | [0] = { \ | 51 | .membase = name##_BA, \ |
| 51 | .start = name##_PA, \ | 52 | .mapbase = name##_PA, \ |
| 52 | .end = name##_PA + 0x0ff, \ | 53 | .irq = IRQ_##name, \ |
| 53 | .flags = IORESOURCE_MEM, \ | 54 | .uartclk = 11313600, \ |
| 54 | }, \ | 55 | .regshift = 2, \ |
| 55 | [1] = { \ | 56 | .iotype = UPIO_MEM, \ |
| 56 | .start = IRQ_##name, \ | 57 | .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ |
| 57 | .end = IRQ_##name, \ | ||
| 58 | .flags = IORESOURCE_IRQ, \ | ||
| 59 | } \ | ||
| 60 | } | ||
| 61 | |||
| 62 | #define W90X900_DEVICE(devname, regname, devid, platdevname) \ | ||
| 63 | struct platform_device w90x900_##devname = { \ | ||
| 64 | .name = platdevname, \ | ||
| 65 | .id = devid, \ | ||
| 66 | .num_resources = ARRAY_SIZE(w90x900_##regname##_resource), \ | ||
| 67 | .resource = w90x900_##regname##_resource, \ | ||
| 68 | } | ||
| 69 | |||
| 70 | #define W90X900_UARTCFG(port, flag, uc, ulc, ufc) \ | ||
| 71 | { \ | ||
| 72 | .hwport = port, \ | ||
| 73 | .flags = flag, \ | ||
| 74 | .ucon = uc, \ | ||
| 75 | .ulcon = ulc, \ | ||
| 76 | .ufcon = ufc, \ | ||
| 77 | } | 58 | } |
diff --git a/arch/arm/mach-w90x900/include/mach/system.h b/arch/arm/mach-w90x900/include/mach/system.h index 93753f922618..940640066857 100644 --- a/arch/arm/mach-w90x900/include/mach/system.h +++ b/arch/arm/mach-w90x900/include/mach/system.h | |||
| @@ -21,7 +21,7 @@ static void arch_idle(void) | |||
| 21 | { | 21 | { |
| 22 | } | 22 | } |
| 23 | 23 | ||
| 24 | static void arch_reset(char mode) | 24 | static void arch_reset(char mode, const char *cmd) |
| 25 | { | 25 | { |
| 26 | cpu_reset(0); | 26 | cpu_reset(0); |
| 27 | } | 27 | } |
diff --git a/arch/arm/mach-w90x900/mach-w90p910evb.c b/arch/arm/mach-w90x900/mach-w90p910evb.c index 9ebc93f48530..726ff6798a56 100644 --- a/arch/arm/mach-w90x900/mach-w90p910evb.c +++ b/arch/arm/mach-w90x900/mach-w90p910evb.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/timer.h> | 22 | #include <linux/timer.h> |
| 23 | #include <linux/init.h> | 23 | #include <linux/init.h> |
| 24 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
| 25 | #include <linux/mtd/physmap.h> | ||
| 25 | 26 | ||
| 26 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| 27 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
| @@ -32,28 +33,67 @@ | |||
| 32 | #include <mach/map.h> | 33 | #include <mach/map.h> |
| 33 | 34 | ||
| 34 | #include "cpu.h" | 35 | #include "cpu.h" |
| 36 | /*w90p910 evb norflash driver data */ | ||
| 35 | 37 | ||
| 36 | static struct map_desc w90p910_iodesc[] __initdata = { | 38 | #define W90P910_FLASH_BASE 0xA0000000 |
| 39 | #define W90P910_FLASH_SIZE 0x400000 | ||
| 40 | |||
| 41 | static struct mtd_partition w90p910_flash_partitions[] = { | ||
| 42 | { | ||
| 43 | .name = "NOR Partition 1 for kernel (960K)", | ||
| 44 | .size = 0xF0000, | ||
| 45 | .offset = 0x10000, | ||
| 46 | }, | ||
| 47 | { | ||
| 48 | .name = "NOR Partition 2 for image (1M)", | ||
| 49 | .size = 0x100000, | ||
| 50 | .offset = 0x100000, | ||
| 51 | }, | ||
| 52 | { | ||
| 53 | .name = "NOR Partition 3 for user (2M)", | ||
| 54 | .size = 0x200000, | ||
| 55 | .offset = 0x00200000, | ||
| 56 | } | ||
| 37 | }; | 57 | }; |
| 38 | 58 | ||
| 39 | static struct w90x900_uartcfg w90p910_uartcfgs[] = { | 59 | static struct physmap_flash_data w90p910_flash_data = { |
| 40 | W90X900_UARTCFG(0, 0, 0, 0, 0), | 60 | .width = 2, |
| 41 | W90X900_UARTCFG(1, 0, 0, 0, 0), | 61 | .parts = w90p910_flash_partitions, |
| 42 | W90X900_UARTCFG(2, 0, 0, 0, 0), | 62 | .nr_parts = ARRAY_SIZE(w90p910_flash_partitions), |
| 43 | W90X900_UARTCFG(3, 0, 0, 0, 0), | 63 | }; |
| 44 | W90X900_UARTCFG(4, 0, 0, 0, 0), | 64 | |
| 65 | static struct resource w90p910_flash_resources[] = { | ||
| 66 | { | ||
| 67 | .start = W90P910_FLASH_BASE, | ||
| 68 | .end = W90P910_FLASH_BASE + W90P910_FLASH_SIZE - 1, | ||
| 69 | .flags = IORESOURCE_MEM, | ||
| 70 | } | ||
| 71 | }; | ||
| 72 | |||
| 73 | static struct platform_device w90p910_flash_device = { | ||
| 74 | .name = "physmap-flash", | ||
| 75 | .id = 0, | ||
| 76 | .dev = { | ||
| 77 | .platform_data = &w90p910_flash_data, | ||
| 78 | }, | ||
| 79 | .resource = w90p910_flash_resources, | ||
| 80 | .num_resources = ARRAY_SIZE(w90p910_flash_resources), | ||
| 81 | }; | ||
| 82 | |||
| 83 | static struct map_desc w90p910_iodesc[] __initdata = { | ||
| 45 | }; | 84 | }; |
| 46 | 85 | ||
| 47 | /*Here should be your evb resourse,such as LCD*/ | 86 | /*Here should be your evb resourse,such as LCD*/ |
| 48 | 87 | ||
| 49 | static struct platform_device *w90p910evb_dev[] __initdata = { | 88 | static struct platform_device *w90p910evb_dev[] __initdata = { |
| 89 | &w90p910_serial_device, | ||
| 90 | &w90p910_flash_device, | ||
| 50 | }; | 91 | }; |
| 51 | 92 | ||
| 52 | static void __init w90p910evb_map_io(void) | 93 | static void __init w90p910evb_map_io(void) |
| 53 | { | 94 | { |
| 54 | w90p910_map_io(w90p910_iodesc, ARRAY_SIZE(w90p910_iodesc)); | 95 | w90p910_map_io(w90p910_iodesc, ARRAY_SIZE(w90p910_iodesc)); |
| 55 | w90p910_init_clocks(0); | 96 | w90p910_init_clocks(0); |
| 56 | w90p910_init_uarts(w90p910_uartcfgs, ARRAY_SIZE(w90p910_uartcfgs)); | ||
| 57 | } | 97 | } |
| 58 | 98 | ||
| 59 | static void __init w90p910evb_init(void) | 99 | static void __init w90p910evb_init(void) |
diff --git a/arch/arm/mach-w90x900/w90p910.c b/arch/arm/mach-w90x900/w90p910.c index aa783bc94310..2bcbaa681b99 100644 --- a/arch/arm/mach-w90x900/w90p910.c +++ b/arch/arm/mach-w90x900/w90p910.c | |||
| @@ -25,6 +25,7 @@ | |||
| 25 | #include <linux/init.h> | 25 | #include <linux/init.h> |
| 26 | #include <linux/platform_device.h> | 26 | #include <linux/platform_device.h> |
| 27 | #include <linux/io.h> | 27 | #include <linux/io.h> |
| 28 | #include <linux/serial_8250.h> | ||
| 28 | 29 | ||
| 29 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
| 30 | #include <asm/mach/map.h> | 31 | #include <asm/mach/map.h> |
| @@ -36,12 +37,6 @@ | |||
| 36 | 37 | ||
| 37 | #include "cpu.h" | 38 | #include "cpu.h" |
| 38 | 39 | ||
| 39 | /*W90P910 has five uarts*/ | ||
| 40 | |||
| 41 | #define MAX_UART_COUNT 5 | ||
| 42 | static int uart_count; | ||
| 43 | static struct platform_device *uart_devs[MAX_UART_COUNT-1]; | ||
| 44 | |||
| 45 | /* Initial IO mappings */ | 40 | /* Initial IO mappings */ |
| 46 | 41 | ||
| 47 | static struct map_desc w90p910_iodesc[] __initdata = { | 42 | static struct map_desc w90p910_iodesc[] __initdata = { |
| @@ -53,48 +48,19 @@ static struct map_desc w90p910_iodesc[] __initdata = { | |||
| 53 | /*IODESC_ENT(LCD),*/ | 48 | /*IODESC_ENT(LCD),*/ |
| 54 | }; | 49 | }; |
| 55 | 50 | ||
| 56 | /*Init the dev resource*/ | 51 | /* Initial serial platform data */ |
| 57 | |||
| 58 | static W90X900_RES(UART0); | ||
| 59 | static W90X900_RES(UART1); | ||
| 60 | static W90X900_RES(UART2); | ||
| 61 | static W90X900_RES(UART3); | ||
| 62 | static W90X900_RES(UART4); | ||
| 63 | static W90X900_DEVICE(uart0, UART0, 0, "w90x900-uart"); | ||
| 64 | static W90X900_DEVICE(uart1, UART1, 1, "w90x900-uart"); | ||
| 65 | static W90X900_DEVICE(uart2, UART2, 2, "w90x900-uart"); | ||
| 66 | static W90X900_DEVICE(uart3, UART3, 3, "w90x900-uart"); | ||
| 67 | static W90X900_DEVICE(uart4, UART4, 4, "w90x900-uart"); | ||
| 68 | |||
| 69 | static struct platform_device *uart_devices[] __initdata = { | ||
| 70 | &w90x900_uart0, | ||
| 71 | &w90x900_uart1, | ||
| 72 | &w90x900_uart2, | ||
| 73 | &w90x900_uart3, | ||
| 74 | &w90x900_uart4 | ||
| 75 | }; | ||
| 76 | 52 | ||
| 77 | /*Init W90P910 uart device*/ | 53 | struct plat_serial8250_port w90p910_uart_data[] = { |
| 54 | W90X900_8250PORT(UART0), | ||
| 55 | }; | ||
| 78 | 56 | ||
| 79 | void __init w90p910_init_uarts(struct w90x900_uartcfg *cfg, int no) | 57 | struct platform_device w90p910_serial_device = { |
| 80 | { | 58 | .name = "serial8250", |
| 81 | struct platform_device *platdev; | 59 | .id = PLAT8250_DEV_PLATFORM, |
| 82 | int uart, uartdev; | 60 | .dev = { |
| 83 | 61 | .platform_data = w90p910_uart_data, | |
| 84 | /*By min() to judge count of uart be used indeed*/ | 62 | }, |
| 85 | 63 | }; | |
| 86 | uartdev = ARRAY_SIZE(uart_devices); | ||
| 87 | no = min(uartdev, no); | ||
| 88 | |||
| 89 | for (uart = 0; uart < no; uart++, cfg++) { | ||
| 90 | if (cfg->hwport != uart) | ||
| 91 | printk(KERN_ERR "w90x900_uartcfg[%d] error\n", uart); | ||
| 92 | platdev = uart_devices[cfg->hwport]; | ||
| 93 | uart_devs[uart] = platdev; | ||
| 94 | platdev->dev.platform_data = cfg; | ||
| 95 | } | ||
| 96 | uart_count = uart; | ||
| 97 | } | ||
| 98 | 64 | ||
| 99 | /*Init W90P910 evb io*/ | 65 | /*Init W90P910 evb io*/ |
| 100 | 66 | ||
| @@ -122,13 +88,6 @@ static int __init w90p910_init_cpu(void) | |||
| 122 | 88 | ||
| 123 | static int __init w90x900_arch_init(void) | 89 | static int __init w90x900_arch_init(void) |
| 124 | { | 90 | { |
| 125 | int ret; | 91 | return w90p910_init_cpu(); |
| 126 | |||
| 127 | ret = w90p910_init_cpu(); | ||
| 128 | if (ret != 0) | ||
| 129 | return ret; | ||
| 130 | |||
| 131 | return platform_add_devices(uart_devs, uart_count); | ||
| 132 | |||
| 133 | } | 92 | } |
| 134 | arch_initcall(w90x900_arch_init); | 93 | arch_initcall(w90x900_arch_init); |
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index d490f3773c01..a6230f7a24c8 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig | |||
| @@ -340,6 +340,17 @@ config CPU_XSC3 | |||
| 340 | select CPU_TLB_V4WBI if MMU | 340 | select CPU_TLB_V4WBI if MMU |
| 341 | select IO_36 | 341 | select IO_36 |
| 342 | 342 | ||
| 343 | # Marvell PJ1 (Mohawk) | ||
| 344 | config CPU_MOHAWK | ||
| 345 | bool | ||
| 346 | select CPU_32v5 | ||
| 347 | select CPU_ABRT_EV5T | ||
| 348 | select CPU_PABRT_NOIFAR | ||
| 349 | select CPU_CACHE_VIVT | ||
| 350 | select CPU_CP15_MMU | ||
| 351 | select CPU_TLB_V4WBI if MMU | ||
| 352 | select CPU_COPY_V4WB if MMU | ||
| 353 | |||
| 343 | # Feroceon | 354 | # Feroceon |
| 344 | config CPU_FEROCEON | 355 | config CPU_FEROCEON |
| 345 | bool | 356 | bool |
| @@ -569,7 +580,7 @@ comment "Processor Features" | |||
| 569 | 580 | ||
| 570 | config ARM_THUMB | 581 | config ARM_THUMB |
| 571 | bool "Support Thumb user binaries" | 582 | bool "Support Thumb user binaries" |
| 572 | depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON | 583 | depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V7 || CPU_FEROCEON |
| 573 | default y | 584 | default y |
| 574 | help | 585 | help |
| 575 | Say Y if you want to include kernel support for running user space | 586 | Say Y if you want to include kernel support for running user space |
| @@ -653,7 +664,7 @@ config CPU_CACHE_ROUND_ROBIN | |||
| 653 | 664 | ||
| 654 | config CPU_BPREDICT_DISABLE | 665 | config CPU_BPREDICT_DISABLE |
| 655 | bool "Disable branch prediction" | 666 | bool "Disable branch prediction" |
| 656 | depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7 | 667 | depends on CPU_ARM1020 || CPU_V6 || CPU_MOHAWK || CPU_XSC3 || CPU_V7 |
| 657 | help | 668 | help |
| 658 | Say Y here to disable branch prediction. If unsure, say N. | 669 | Say Y here to disable branch prediction. If unsure, say N. |
| 659 | 670 | ||
| @@ -704,7 +715,8 @@ config CACHE_FEROCEON_L2_WRITETHROUGH | |||
| 704 | 715 | ||
| 705 | config CACHE_L2X0 | 716 | config CACHE_L2X0 |
| 706 | bool "Enable the L2x0 outer cache controller" | 717 | bool "Enable the L2x0 outer cache controller" |
| 707 | depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || REALVIEW_EB_A9MP | 718 | depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \ |
| 719 | REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 | ||
| 708 | default y | 720 | default y |
| 709 | select OUTER_CACHE | 721 | select OUTER_CACHE |
| 710 | help | 722 | help |
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile index 480f78a3611a..c264683538bc 100644 --- a/arch/arm/mm/Makefile +++ b/arch/arm/mm/Makefile | |||
| @@ -16,6 +16,7 @@ obj-$(CONFIG_MODULES) += proc-syms.o | |||
| 16 | 16 | ||
| 17 | obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o | 17 | obj-$(CONFIG_ALIGNMENT_TRAP) += alignment.o |
| 18 | obj-$(CONFIG_DISCONTIGMEM) += discontig.o | 18 | obj-$(CONFIG_DISCONTIGMEM) += discontig.o |
| 19 | obj-$(CONFIG_HIGHMEM) += highmem.o | ||
| 19 | 20 | ||
| 20 | obj-$(CONFIG_CPU_ABRT_NOMMU) += abort-nommu.o | 21 | obj-$(CONFIG_CPU_ABRT_NOMMU) += abort-nommu.o |
| 21 | obj-$(CONFIG_CPU_ABRT_EV4) += abort-ev4.o | 22 | obj-$(CONFIG_CPU_ABRT_EV4) += abort-ev4.o |
| @@ -70,6 +71,7 @@ obj-$(CONFIG_CPU_SA110) += proc-sa110.o | |||
| 70 | obj-$(CONFIG_CPU_SA1100) += proc-sa1100.o | 71 | obj-$(CONFIG_CPU_SA1100) += proc-sa1100.o |
| 71 | obj-$(CONFIG_CPU_XSCALE) += proc-xscale.o | 72 | obj-$(CONFIG_CPU_XSCALE) += proc-xscale.o |
| 72 | obj-$(CONFIG_CPU_XSC3) += proc-xsc3.o | 73 | obj-$(CONFIG_CPU_XSC3) += proc-xsc3.o |
| 74 | obj-$(CONFIG_CPU_MOHAWK) += proc-mohawk.o | ||
| 73 | obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o | 75 | obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o |
| 74 | obj-$(CONFIG_CPU_V6) += proc-v6.o | 76 | obj-$(CONFIG_CPU_V6) += proc-v6.o |
| 75 | obj-$(CONFIG_CPU_V7) += proc-v7.o | 77 | obj-$(CONFIG_CPU_V7) += proc-v7.o |
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c index 80cd207cbaea..d6dd83826f8a 100644 --- a/arch/arm/mm/cache-feroceon-l2.c +++ b/arch/arm/mm/cache-feroceon-l2.c | |||
| @@ -14,8 +14,12 @@ | |||
| 14 | 14 | ||
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <asm/cacheflush.h> | 16 | #include <asm/cacheflush.h> |
| 17 | #include <asm/kmap_types.h> | ||
| 18 | #include <asm/fixmap.h> | ||
| 19 | #include <asm/pgtable.h> | ||
| 20 | #include <asm/tlbflush.h> | ||
| 17 | #include <plat/cache-feroceon-l2.h> | 21 | #include <plat/cache-feroceon-l2.h> |
| 18 | 22 | #include "mm.h" | |
| 19 | 23 | ||
| 20 | /* | 24 | /* |
| 21 | * Low-level cache maintenance operations. | 25 | * Low-level cache maintenance operations. |
| @@ -34,14 +38,36 @@ | |||
| 34 | * The range operations require two successive cp15 writes, in | 38 | * The range operations require two successive cp15 writes, in |
| 35 | * between which we don't want to be preempted. | 39 | * between which we don't want to be preempted. |
| 36 | */ | 40 | */ |
| 41 | |||
| 42 | static inline unsigned long l2_start_va(unsigned long paddr) | ||
| 43 | { | ||
| 44 | #ifdef CONFIG_HIGHMEM | ||
| 45 | /* | ||
| 46 | * Let's do our own fixmap stuff in a minimal way here. | ||
| 47 | * Because range ops can't be done on physical addresses, | ||
| 48 | * we simply install a virtual mapping for it only for the | ||
| 49 | * TLB lookup to occur, hence no need to flush the untouched | ||
| 50 | * memory mapping. This is protected with the disabling of | ||
| 51 | * interrupts by the caller. | ||
| 52 | */ | ||
| 53 | unsigned long idx = KM_L2_CACHE + KM_TYPE_NR * smp_processor_id(); | ||
| 54 | unsigned long vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); | ||
| 55 | set_pte_ext(TOP_PTE(vaddr), pfn_pte(paddr >> PAGE_SHIFT, PAGE_KERNEL), 0); | ||
| 56 | local_flush_tlb_kernel_page(vaddr); | ||
| 57 | return vaddr + (paddr & ~PAGE_MASK); | ||
| 58 | #else | ||
| 59 | return __phys_to_virt(paddr); | ||
| 60 | #endif | ||
| 61 | } | ||
| 62 | |||
| 37 | static inline void l2_clean_pa(unsigned long addr) | 63 | static inline void l2_clean_pa(unsigned long addr) |
| 38 | { | 64 | { |
| 39 | __asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr)); | 65 | __asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr)); |
| 40 | } | 66 | } |
| 41 | 67 | ||
| 42 | static inline void l2_clean_mva_range(unsigned long start, unsigned long end) | 68 | static inline void l2_clean_pa_range(unsigned long start, unsigned long end) |
| 43 | { | 69 | { |
| 44 | unsigned long flags; | 70 | unsigned long va_start, va_end, flags; |
| 45 | 71 | ||
| 46 | /* | 72 | /* |
| 47 | * Make sure 'start' and 'end' reference the same page, as | 73 | * Make sure 'start' and 'end' reference the same page, as |
| @@ -51,17 +77,14 @@ static inline void l2_clean_mva_range(unsigned long start, unsigned long end) | |||
| 51 | BUG_ON((start ^ end) >> PAGE_SHIFT); | 77 | BUG_ON((start ^ end) >> PAGE_SHIFT); |
| 52 | 78 | ||
| 53 | raw_local_irq_save(flags); | 79 | raw_local_irq_save(flags); |
| 80 | va_start = l2_start_va(start); | ||
| 81 | va_end = va_start + (end - start); | ||
| 54 | __asm__("mcr p15, 1, %0, c15, c9, 4\n\t" | 82 | __asm__("mcr p15, 1, %0, c15, c9, 4\n\t" |
| 55 | "mcr p15, 1, %1, c15, c9, 5" | 83 | "mcr p15, 1, %1, c15, c9, 5" |
| 56 | : : "r" (start), "r" (end)); | 84 | : : "r" (va_start), "r" (va_end)); |
| 57 | raw_local_irq_restore(flags); | 85 | raw_local_irq_restore(flags); |
| 58 | } | 86 | } |
| 59 | 87 | ||
| 60 | static inline void l2_clean_pa_range(unsigned long start, unsigned long end) | ||
| 61 | { | ||
| 62 | l2_clean_mva_range(__phys_to_virt(start), __phys_to_virt(end)); | ||
| 63 | } | ||
| 64 | |||
| 65 | static inline void l2_clean_inv_pa(unsigned long addr) | 88 | static inline void l2_clean_inv_pa(unsigned long addr) |
| 66 | { | 89 | { |
| 67 | __asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr)); | 90 | __asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr)); |
| @@ -72,9 +95,9 @@ static inline void l2_inv_pa(unsigned long addr) | |||
| 72 | __asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr)); | 95 | __asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr)); |
| 73 | } | 96 | } |
| 74 | 97 | ||
| 75 | static inline void l2_inv_mva_range(unsigned long start, unsigned long end) | 98 | static inline void l2_inv_pa_range(unsigned long start, unsigned long end) |
| 76 | { | 99 | { |
| 77 | unsigned long flags; | 100 | unsigned long va_start, va_end, flags; |
| 78 | 101 | ||
| 79 | /* | 102 | /* |
| 80 | * Make sure 'start' and 'end' reference the same page, as | 103 | * Make sure 'start' and 'end' reference the same page, as |
| @@ -84,17 +107,14 @@ static inline void l2_inv_mva_range(unsigned long start, unsigned long end) | |||
| 84 | BUG_ON((start ^ end) >> PAGE_SHIFT); | 107 | BUG_ON((start ^ end) >> PAGE_SHIFT); |
| 85 | 108 | ||
| 86 | raw_local_irq_save(flags); | 109 | raw_local_irq_save(flags); |
| 110 | va_start = l2_start_va(start); | ||
| 111 | va_end = va_start + (end - start); | ||
| 87 | __asm__("mcr p15, 1, %0, c15, c11, 4\n\t" | 112 | __asm__("mcr p15, 1, %0, c15, c11, 4\n\t" |
| 88 | "mcr p15, 1, %1, c15, c11, 5" | 113 | "mcr p15, 1, %1, c15, c11, 5" |
| 89 | : : "r" (start), "r" (end)); | 114 | : : "r" (va_start), "r" (va_end)); |
| 90 | raw_local_irq_restore(flags); | 115 | raw_local_irq_restore(flags); |
| 91 | } | 116 | } |
| 92 | 117 | ||
| 93 | static inline void l2_inv_pa_range(unsigned long start, unsigned long end) | ||
| 94 | { | ||
| 95 | l2_inv_mva_range(__phys_to_virt(start), __phys_to_virt(end)); | ||
| 96 | } | ||
| 97 | |||
| 98 | 118 | ||
| 99 | /* | 119 | /* |
| 100 | * Linux primitives. | 120 | * Linux primitives. |
diff --git a/arch/arm/mm/cache-xsc3l2.c b/arch/arm/mm/cache-xsc3l2.c index 464de893a988..5d180cb0bd94 100644 --- a/arch/arm/mm/cache-xsc3l2.c +++ b/arch/arm/mm/cache-xsc3l2.c | |||
| @@ -17,12 +17,14 @@ | |||
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | */ | 18 | */ |
| 19 | #include <linux/init.h> | 19 | #include <linux/init.h> |
| 20 | #include <linux/spinlock.h> | ||
| 21 | #include <linux/io.h> | ||
| 22 | |||
| 23 | #include <asm/system.h> | 20 | #include <asm/system.h> |
| 24 | #include <asm/cputype.h> | 21 | #include <asm/cputype.h> |
| 25 | #include <asm/cacheflush.h> | 22 | #include <asm/cacheflush.h> |
| 23 | #include <asm/kmap_types.h> | ||
| 24 | #include <asm/fixmap.h> | ||
| 25 | #include <asm/pgtable.h> | ||
| 26 | #include <asm/tlbflush.h> | ||
| 27 | #include "mm.h" | ||
| 26 | 28 | ||
| 27 | #define CR_L2 (1 << 26) | 29 | #define CR_L2 (1 << 26) |
| 28 | 30 | ||
| @@ -47,21 +49,11 @@ static inline void xsc3_l2_clean_mva(unsigned long addr) | |||
| 47 | __asm__("mcr p15, 1, %0, c7, c11, 1" : : "r" (addr)); | 49 | __asm__("mcr p15, 1, %0, c7, c11, 1" : : "r" (addr)); |
| 48 | } | 50 | } |
| 49 | 51 | ||
| 50 | static inline void xsc3_l2_clean_pa(unsigned long addr) | ||
| 51 | { | ||
| 52 | xsc3_l2_clean_mva(__phys_to_virt(addr)); | ||
| 53 | } | ||
| 54 | |||
| 55 | static inline void xsc3_l2_inv_mva(unsigned long addr) | 52 | static inline void xsc3_l2_inv_mva(unsigned long addr) |
| 56 | { | 53 | { |
| 57 | __asm__("mcr p15, 1, %0, c7, c7, 1" : : "r" (addr)); | 54 | __asm__("mcr p15, 1, %0, c7, c7, 1" : : "r" (addr)); |
| 58 | } | 55 | } |
| 59 | 56 | ||
| 60 | static inline void xsc3_l2_inv_pa(unsigned long addr) | ||
| 61 | { | ||
| 62 | xsc3_l2_inv_mva(__phys_to_virt(addr)); | ||
| 63 | } | ||
| 64 | |||
| 65 | static inline void xsc3_l2_inv_all(void) | 57 | static inline void xsc3_l2_inv_all(void) |
| 66 | { | 58 | { |
| 67 | unsigned long l2ctype, set_way; | 59 | unsigned long l2ctype, set_way; |
| @@ -79,50 +71,103 @@ static inline void xsc3_l2_inv_all(void) | |||
| 79 | dsb(); | 71 | dsb(); |
| 80 | } | 72 | } |
| 81 | 73 | ||
| 74 | #ifdef CONFIG_HIGHMEM | ||
| 75 | #define l2_map_save_flags(x) raw_local_save_flags(x) | ||
| 76 | #define l2_map_restore_flags(x) raw_local_irq_restore(x) | ||
| 77 | #else | ||
| 78 | #define l2_map_save_flags(x) ((x) = 0) | ||
| 79 | #define l2_map_restore_flags(x) ((void)(x)) | ||
| 80 | #endif | ||
| 81 | |||
| 82 | static inline unsigned long l2_map_va(unsigned long pa, unsigned long prev_va, | ||
| 83 | unsigned long flags) | ||
| 84 | { | ||
| 85 | #ifdef CONFIG_HIGHMEM | ||
| 86 | unsigned long va = prev_va & PAGE_MASK; | ||
| 87 | unsigned long pa_offset = pa << (32 - PAGE_SHIFT); | ||
| 88 | if (unlikely(pa_offset < (prev_va << (32 - PAGE_SHIFT)))) { | ||
| 89 | /* | ||
| 90 | * Switching to a new page. Because cache ops are | ||
| 91 | * using virtual addresses only, we must put a mapping | ||
| 92 | * in place for it. We also enable interrupts for a | ||
| 93 | * short while and disable them again to protect this | ||
| 94 | * mapping. | ||
| 95 | */ | ||
| 96 | unsigned long idx; | ||
| 97 | raw_local_irq_restore(flags); | ||
| 98 | idx = KM_L2_CACHE + KM_TYPE_NR * smp_processor_id(); | ||
| 99 | va = __fix_to_virt(FIX_KMAP_BEGIN + idx); | ||
| 100 | raw_local_irq_restore(flags | PSR_I_BIT); | ||
| 101 | set_pte_ext(TOP_PTE(va), pfn_pte(pa >> PAGE_SHIFT, PAGE_KERNEL), 0); | ||
| 102 | local_flush_tlb_kernel_page(va); | ||
| 103 | } | ||
| 104 | return va + (pa_offset >> (32 - PAGE_SHIFT)); | ||
| 105 | #else | ||
| 106 | return __phys_to_virt(pa); | ||
| 107 | #endif | ||
| 108 | } | ||
| 109 | |||
| 82 | static void xsc3_l2_inv_range(unsigned long start, unsigned long end) | 110 | static void xsc3_l2_inv_range(unsigned long start, unsigned long end) |
| 83 | { | 111 | { |
| 112 | unsigned long vaddr, flags; | ||
| 113 | |||
| 84 | if (start == 0 && end == -1ul) { | 114 | if (start == 0 && end == -1ul) { |
| 85 | xsc3_l2_inv_all(); | 115 | xsc3_l2_inv_all(); |
| 86 | return; | 116 | return; |
| 87 | } | 117 | } |
| 88 | 118 | ||
| 119 | vaddr = -1; /* to force the first mapping */ | ||
| 120 | l2_map_save_flags(flags); | ||
| 121 | |||
| 89 | /* | 122 | /* |
| 90 | * Clean and invalidate partial first cache line. | 123 | * Clean and invalidate partial first cache line. |
| 91 | */ | 124 | */ |
| 92 | if (start & (CACHE_LINE_SIZE - 1)) { | 125 | if (start & (CACHE_LINE_SIZE - 1)) { |
| 93 | xsc3_l2_clean_pa(start & ~(CACHE_LINE_SIZE - 1)); | 126 | vaddr = l2_map_va(start & ~(CACHE_LINE_SIZE - 1), vaddr, flags); |
| 94 | xsc3_l2_inv_pa(start & ~(CACHE_LINE_SIZE - 1)); | 127 | xsc3_l2_clean_mva(vaddr); |
| 128 | xsc3_l2_inv_mva(vaddr); | ||
| 95 | start = (start | (CACHE_LINE_SIZE - 1)) + 1; | 129 | start = (start | (CACHE_LINE_SIZE - 1)) + 1; |
| 96 | } | 130 | } |
| 97 | 131 | ||
| 98 | /* | 132 | /* |
| 99 | * Clean and invalidate partial last cache line. | 133 | * Invalidate all full cache lines between 'start' and 'end'. |
| 100 | */ | 134 | */ |
| 101 | if (start < end && (end & (CACHE_LINE_SIZE - 1))) { | 135 | while (start < (end & ~(CACHE_LINE_SIZE - 1))) { |
| 102 | xsc3_l2_clean_pa(end & ~(CACHE_LINE_SIZE - 1)); | 136 | vaddr = l2_map_va(start, vaddr, flags); |
| 103 | xsc3_l2_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); | 137 | xsc3_l2_inv_mva(vaddr); |
| 104 | end &= ~(CACHE_LINE_SIZE - 1); | 138 | start += CACHE_LINE_SIZE; |
| 105 | } | 139 | } |
| 106 | 140 | ||
| 107 | /* | 141 | /* |
| 108 | * Invalidate all full cache lines between 'start' and 'end'. | 142 | * Clean and invalidate partial last cache line. |
| 109 | */ | 143 | */ |
| 110 | while (start < end) { | 144 | if (start < end) { |
| 111 | xsc3_l2_inv_pa(start); | 145 | vaddr = l2_map_va(start, vaddr, flags); |
| 112 | start += CACHE_LINE_SIZE; | 146 | xsc3_l2_clean_mva(vaddr); |
| 147 | xsc3_l2_inv_mva(vaddr); | ||
| 113 | } | 148 | } |
| 114 | 149 | ||
| 150 | l2_map_restore_flags(flags); | ||
| 151 | |||
| 115 | dsb(); | 152 | dsb(); |
| 116 | } | 153 | } |
| 117 | 154 | ||
| 118 | static void xsc3_l2_clean_range(unsigned long start, unsigned long end) | 155 | static void xsc3_l2_clean_range(unsigned long start, unsigned long end) |
| 119 | { | 156 | { |
| 157 | unsigned long vaddr, flags; | ||
| 158 | |||
| 159 | vaddr = -1; /* to force the first mapping */ | ||
| 160 | l2_map_save_flags(flags); | ||
| 161 | |||
| 120 | start &= ~(CACHE_LINE_SIZE - 1); | 162 | start &= ~(CACHE_LINE_SIZE - 1); |
| 121 | while (start < end) { | 163 | while (start < end) { |
| 122 | xsc3_l2_clean_pa(start); | 164 | vaddr = l2_map_va(start, vaddr, flags); |
| 165 | xsc3_l2_clean_mva(vaddr); | ||
| 123 | start += CACHE_LINE_SIZE; | 166 | start += CACHE_LINE_SIZE; |
| 124 | } | 167 | } |
| 125 | 168 | ||
| 169 | l2_map_restore_flags(flags); | ||
| 170 | |||
| 126 | dsb(); | 171 | dsb(); |
| 127 | } | 172 | } |
| 128 | 173 | ||
| @@ -148,18 +193,26 @@ static inline void xsc3_l2_flush_all(void) | |||
| 148 | 193 | ||
| 149 | static void xsc3_l2_flush_range(unsigned long start, unsigned long end) | 194 | static void xsc3_l2_flush_range(unsigned long start, unsigned long end) |
| 150 | { | 195 | { |
| 196 | unsigned long vaddr, flags; | ||
| 197 | |||
| 151 | if (start == 0 && end == -1ul) { | 198 | if (start == 0 && end == -1ul) { |
| 152 | xsc3_l2_flush_all(); | 199 | xsc3_l2_flush_all(); |
| 153 | return; | 200 | return; |
| 154 | } | 201 | } |
| 155 | 202 | ||
| 203 | vaddr = -1; /* to force the first mapping */ | ||
| 204 | l2_map_save_flags(flags); | ||
| 205 | |||
| 156 | start &= ~(CACHE_LINE_SIZE - 1); | 206 | start &= ~(CACHE_LINE_SIZE - 1); |
| 157 | while (start < end) { | 207 | while (start < end) { |
| 158 | xsc3_l2_clean_pa(start); | 208 | vaddr = l2_map_va(start, vaddr, flags); |
| 159 | xsc3_l2_inv_pa(start); | 209 | xsc3_l2_clean_mva(vaddr); |
| 210 | xsc3_l2_inv_mva(vaddr); | ||
| 160 | start += CACHE_LINE_SIZE; | 211 | start += CACHE_LINE_SIZE; |
| 161 | } | 212 | } |
| 162 | 213 | ||
| 214 | l2_map_restore_flags(flags); | ||
| 215 | |||
| 163 | dsb(); | 216 | dsb(); |
| 164 | } | 217 | } |
| 165 | 218 | ||
diff --git a/arch/arm/mm/copypage-feroceon.c b/arch/arm/mm/copypage-feroceon.c index c3ba6a94da0c..70997d5bee2d 100644 --- a/arch/arm/mm/copypage-feroceon.c +++ b/arch/arm/mm/copypage-feroceon.c | |||
| @@ -13,7 +13,7 @@ | |||
| 13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
| 14 | #include <linux/highmem.h> | 14 | #include <linux/highmem.h> |
| 15 | 15 | ||
| 16 | static void __attribute__((naked)) | 16 | static void __naked |
| 17 | feroceon_copy_user_page(void *kto, const void *kfrom) | 17 | feroceon_copy_user_page(void *kto, const void *kfrom) |
| 18 | { | 18 | { |
| 19 | asm("\ | 19 | asm("\ |
diff --git a/arch/arm/mm/copypage-v3.c b/arch/arm/mm/copypage-v3.c index 70ed96c8af8e..de9c06854ad7 100644 --- a/arch/arm/mm/copypage-v3.c +++ b/arch/arm/mm/copypage-v3.c | |||
| @@ -15,7 +15,7 @@ | |||
| 15 | * | 15 | * |
| 16 | * FIXME: do we need to handle cache stuff... | 16 | * FIXME: do we need to handle cache stuff... |
| 17 | */ | 17 | */ |
| 18 | static void __attribute__((naked)) | 18 | static void __naked |
| 19 | v3_copy_user_page(void *kto, const void *kfrom) | 19 | v3_copy_user_page(void *kto, const void *kfrom) |
| 20 | { | 20 | { |
| 21 | asm("\n\ | 21 | asm("\n\ |
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c index 1601698b9800..7370a7142b04 100644 --- a/arch/arm/mm/copypage-v4mc.c +++ b/arch/arm/mm/copypage-v4mc.c | |||
| @@ -44,7 +44,7 @@ static DEFINE_SPINLOCK(minicache_lock); | |||
| 44 | * instruction. If your processor does not supply this, you have to write your | 44 | * instruction. If your processor does not supply this, you have to write your |
| 45 | * own copy_user_highpage that does the right thing. | 45 | * own copy_user_highpage that does the right thing. |
| 46 | */ | 46 | */ |
| 47 | static void __attribute__((naked)) | 47 | static void __naked |
| 48 | mc_copy_user_page(void *from, void *to) | 48 | mc_copy_user_page(void *from, void *to) |
| 49 | { | 49 | { |
| 50 | asm volatile( | 50 | asm volatile( |
diff --git a/arch/arm/mm/copypage-v4wb.c b/arch/arm/mm/copypage-v4wb.c index 3ec93dab7656..9ab098414227 100644 --- a/arch/arm/mm/copypage-v4wb.c +++ b/arch/arm/mm/copypage-v4wb.c | |||
| @@ -22,7 +22,7 @@ | |||
| 22 | * instruction. If your processor does not supply this, you have to write your | 22 | * instruction. If your processor does not supply this, you have to write your |
| 23 | * own copy_user_highpage that does the right thing. | 23 | * own copy_user_highpage that does the right thing. |
| 24 | */ | 24 | */ |
| 25 | static void __attribute__((naked)) | 25 | static void __naked |
| 26 | v4wb_copy_user_page(void *kto, const void *kfrom) | 26 | v4wb_copy_user_page(void *kto, const void *kfrom) |
| 27 | { | 27 | { |
| 28 | asm("\ | 28 | asm("\ |
diff --git a/arch/arm/mm/copypage-v4wt.c b/arch/arm/mm/copypage-v4wt.c index 0f1188efae45..300efafd6643 100644 --- a/arch/arm/mm/copypage-v4wt.c +++ b/arch/arm/mm/copypage-v4wt.c | |||
| @@ -20,7 +20,7 @@ | |||
| 20 | * dirty data in the cache. However, we do have to ensure that | 20 | * dirty data in the cache. However, we do have to ensure that |
| 21 | * subsequent reads are up to date. | 21 | * subsequent reads are up to date. |
| 22 | */ | 22 | */ |
| 23 | static void __attribute__((naked)) | 23 | static void __naked |
| 24 | v4wt_copy_user_page(void *kto, const void *kfrom) | 24 | v4wt_copy_user_page(void *kto, const void *kfrom) |
| 25 | { | 25 | { |
| 26 | asm("\ | 26 | asm("\ |
diff --git a/arch/arm/mm/copypage-xsc3.c b/arch/arm/mm/copypage-xsc3.c index 39a994542cad..bc4525f5ab23 100644 --- a/arch/arm/mm/copypage-xsc3.c +++ b/arch/arm/mm/copypage-xsc3.c | |||
| @@ -29,7 +29,7 @@ | |||
| 29 | * if we eventually end up using our copied page. | 29 | * if we eventually end up using our copied page. |
| 30 | * | 30 | * |
| 31 | */ | 31 | */ |
| 32 | static void __attribute__((naked)) | 32 | static void __naked |
| 33 | xsc3_mc_copy_user_page(void *kto, const void *kfrom) | 33 | xsc3_mc_copy_user_page(void *kto, const void *kfrom) |
| 34 | { | 34 | { |
| 35 | asm("\ | 35 | asm("\ |
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c index d18f2397ee2d..76824d3e966a 100644 --- a/arch/arm/mm/copypage-xscale.c +++ b/arch/arm/mm/copypage-xscale.c | |||
| @@ -42,7 +42,7 @@ static DEFINE_SPINLOCK(minicache_lock); | |||
| 42 | * Dcache aliasing issue. The writes will be forwarded to the write buffer, | 42 | * Dcache aliasing issue. The writes will be forwarded to the write buffer, |
| 43 | * and merged as appropriate. | 43 | * and merged as appropriate. |
| 44 | */ | 44 | */ |
| 45 | static void __attribute__((naked)) | 45 | static void __naked |
| 46 | mc_copy_user_page(void *from, void *to) | 46 | mc_copy_user_page(void *from, void *to) |
| 47 | { | 47 | { |
| 48 | /* | 48 | /* |
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index 310e479309ef..510c179b0ac8 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <linux/dma-mapping.h> | 19 | #include <linux/dma-mapping.h> |
| 20 | 20 | ||
| 21 | #include <asm/memory.h> | 21 | #include <asm/memory.h> |
| 22 | #include <asm/highmem.h> | ||
| 22 | #include <asm/cacheflush.h> | 23 | #include <asm/cacheflush.h> |
| 23 | #include <asm/tlbflush.h> | 24 | #include <asm/tlbflush.h> |
| 24 | #include <asm/sizes.h> | 25 | #include <asm/sizes.h> |
| @@ -490,29 +491,101 @@ core_initcall(consistent_init); | |||
| 490 | */ | 491 | */ |
| 491 | void dma_cache_maint(const void *start, size_t size, int direction) | 492 | void dma_cache_maint(const void *start, size_t size, int direction) |
| 492 | { | 493 | { |
| 493 | const void *end = start + size; | 494 | void (*inner_op)(const void *, const void *); |
| 495 | void (*outer_op)(unsigned long, unsigned long); | ||
| 494 | 496 | ||
| 495 | BUG_ON(!virt_addr_valid(start) || !virt_addr_valid(end - 1)); | 497 | BUG_ON(!virt_addr_valid(start) || !virt_addr_valid(start + size - 1)); |
| 496 | 498 | ||
| 497 | switch (direction) { | 499 | switch (direction) { |
| 498 | case DMA_FROM_DEVICE: /* invalidate only */ | 500 | case DMA_FROM_DEVICE: /* invalidate only */ |
| 499 | dmac_inv_range(start, end); | 501 | inner_op = dmac_inv_range; |
| 500 | outer_inv_range(__pa(start), __pa(end)); | 502 | outer_op = outer_inv_range; |
| 501 | break; | 503 | break; |
| 502 | case DMA_TO_DEVICE: /* writeback only */ | 504 | case DMA_TO_DEVICE: /* writeback only */ |
| 503 | dmac_clean_range(start, end); | 505 | inner_op = dmac_clean_range; |
| 504 | outer_clean_range(__pa(start), __pa(end)); | 506 | outer_op = outer_clean_range; |
| 505 | break; | 507 | break; |
| 506 | case DMA_BIDIRECTIONAL: /* writeback and invalidate */ | 508 | case DMA_BIDIRECTIONAL: /* writeback and invalidate */ |
| 507 | dmac_flush_range(start, end); | 509 | inner_op = dmac_flush_range; |
| 508 | outer_flush_range(__pa(start), __pa(end)); | 510 | outer_op = outer_flush_range; |
| 509 | break; | 511 | break; |
| 510 | default: | 512 | default: |
| 511 | BUG(); | 513 | BUG(); |
| 512 | } | 514 | } |
| 515 | |||
| 516 | inner_op(start, start + size); | ||
| 517 | outer_op(__pa(start), __pa(start) + size); | ||
| 513 | } | 518 | } |
| 514 | EXPORT_SYMBOL(dma_cache_maint); | 519 | EXPORT_SYMBOL(dma_cache_maint); |
| 515 | 520 | ||
| 521 | static void dma_cache_maint_contiguous(struct page *page, unsigned long offset, | ||
| 522 | size_t size, int direction) | ||
| 523 | { | ||
| 524 | void *vaddr; | ||
| 525 | unsigned long paddr; | ||
| 526 | void (*inner_op)(const void *, const void *); | ||
| 527 | void (*outer_op)(unsigned long, unsigned long); | ||
| 528 | |||
| 529 | switch (direction) { | ||
| 530 | case DMA_FROM_DEVICE: /* invalidate only */ | ||
| 531 | inner_op = dmac_inv_range; | ||
| 532 | outer_op = outer_inv_range; | ||
| 533 | break; | ||
| 534 | case DMA_TO_DEVICE: /* writeback only */ | ||
| 535 | inner_op = dmac_clean_range; | ||
| 536 | outer_op = outer_clean_range; | ||
| 537 | break; | ||
| 538 | case DMA_BIDIRECTIONAL: /* writeback and invalidate */ | ||
| 539 | inner_op = dmac_flush_range; | ||
| 540 | outer_op = outer_flush_range; | ||
| 541 | break; | ||
| 542 | default: | ||
| 543 | BUG(); | ||
| 544 | } | ||
| 545 | |||
| 546 | if (!PageHighMem(page)) { | ||
| 547 | vaddr = page_address(page) + offset; | ||
| 548 | inner_op(vaddr, vaddr + size); | ||
| 549 | } else { | ||
| 550 | vaddr = kmap_high_get(page); | ||
| 551 | if (vaddr) { | ||
| 552 | vaddr += offset; | ||
| 553 | inner_op(vaddr, vaddr + size); | ||
| 554 | kunmap_high(page); | ||
| 555 | } | ||
| 556 | } | ||
| 557 | |||
| 558 | paddr = page_to_phys(page) + offset; | ||
| 559 | outer_op(paddr, paddr + size); | ||
| 560 | } | ||
| 561 | |||
| 562 | void dma_cache_maint_page(struct page *page, unsigned long offset, | ||
| 563 | size_t size, int dir) | ||
| 564 | { | ||
| 565 | /* | ||
| 566 | * A single sg entry may refer to multiple physically contiguous | ||
| 567 | * pages. But we still need to process highmem pages individually. | ||
| 568 | * If highmem is not configured then the bulk of this loop gets | ||
| 569 | * optimized out. | ||
| 570 | */ | ||
| 571 | size_t left = size; | ||
| 572 | do { | ||
| 573 | size_t len = left; | ||
| 574 | if (PageHighMem(page) && len + offset > PAGE_SIZE) { | ||
| 575 | if (offset >= PAGE_SIZE) { | ||
| 576 | page += offset / PAGE_SIZE; | ||
| 577 | offset %= PAGE_SIZE; | ||
| 578 | } | ||
| 579 | len = PAGE_SIZE - offset; | ||
| 580 | } | ||
| 581 | dma_cache_maint_contiguous(page, offset, len, dir); | ||
| 582 | offset = 0; | ||
| 583 | page++; | ||
| 584 | left -= len; | ||
| 585 | } while (left); | ||
| 586 | } | ||
| 587 | EXPORT_SYMBOL(dma_cache_maint_page); | ||
| 588 | |||
| 516 | /** | 589 | /** |
| 517 | * dma_map_sg - map a set of SG buffers for streaming mode DMA | 590 | * dma_map_sg - map a set of SG buffers for streaming mode DMA |
| 518 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | 591 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
| @@ -610,7 +683,8 @@ void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |||
| 610 | continue; | 683 | continue; |
| 611 | 684 | ||
| 612 | if (!arch_is_coherent()) | 685 | if (!arch_is_coherent()) |
| 613 | dma_cache_maint(sg_virt(s), s->length, dir); | 686 | dma_cache_maint_page(sg_page(s), s->offset, |
| 687 | s->length, dir); | ||
| 614 | } | 688 | } |
| 615 | } | 689 | } |
| 616 | EXPORT_SYMBOL(dma_sync_sg_for_device); | 690 | EXPORT_SYMBOL(dma_sync_sg_for_device); |
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c index 0fa9bf388f0b..4e283481cee1 100644 --- a/arch/arm/mm/flush.c +++ b/arch/arm/mm/flush.c | |||
| @@ -192,7 +192,7 @@ void flush_dcache_page(struct page *page) | |||
| 192 | struct address_space *mapping = page_mapping(page); | 192 | struct address_space *mapping = page_mapping(page); |
| 193 | 193 | ||
| 194 | #ifndef CONFIG_SMP | 194 | #ifndef CONFIG_SMP |
| 195 | if (mapping && !mapping_mapped(mapping)) | 195 | if (!PageHighMem(page) && mapping && !mapping_mapped(mapping)) |
| 196 | set_bit(PG_dcache_dirty, &page->flags); | 196 | set_bit(PG_dcache_dirty, &page->flags); |
| 197 | else | 197 | else |
| 198 | #endif | 198 | #endif |
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c new file mode 100644 index 000000000000..a34954d9df7d --- /dev/null +++ b/arch/arm/mm/highmem.c | |||
| @@ -0,0 +1,116 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/mm/highmem.c -- ARM highmem support | ||
| 3 | * | ||
| 4 | * Author: Nicolas Pitre | ||
| 5 | * Created: september 8, 2008 | ||
| 6 | * Copyright: Marvell Semiconductors Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #include <linux/module.h> | ||
| 14 | #include <linux/highmem.h> | ||
| 15 | #include <linux/interrupt.h> | ||
| 16 | #include <asm/fixmap.h> | ||
| 17 | #include <asm/cacheflush.h> | ||
| 18 | #include <asm/tlbflush.h> | ||
| 19 | #include "mm.h" | ||
| 20 | |||
| 21 | void *kmap(struct page *page) | ||
| 22 | { | ||
| 23 | might_sleep(); | ||
| 24 | if (!PageHighMem(page)) | ||
| 25 | return page_address(page); | ||
| 26 | return kmap_high(page); | ||
| 27 | } | ||
| 28 | EXPORT_SYMBOL(kmap); | ||
| 29 | |||
| 30 | void kunmap(struct page *page) | ||
| 31 | { | ||
| 32 | BUG_ON(in_interrupt()); | ||
| 33 | if (!PageHighMem(page)) | ||
| 34 | return; | ||
| 35 | kunmap_high(page); | ||
| 36 | } | ||
| 37 | EXPORT_SYMBOL(kunmap); | ||
| 38 | |||
| 39 | void *kmap_atomic(struct page *page, enum km_type type) | ||
| 40 | { | ||
| 41 | unsigned int idx; | ||
| 42 | unsigned long vaddr; | ||
| 43 | |||
| 44 | pagefault_disable(); | ||
| 45 | if (!PageHighMem(page)) | ||
| 46 | return page_address(page); | ||
| 47 | |||
| 48 | idx = type + KM_TYPE_NR * smp_processor_id(); | ||
| 49 | vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); | ||
| 50 | #ifdef CONFIG_DEBUG_HIGHMEM | ||
| 51 | /* | ||
| 52 | * With debugging enabled, kunmap_atomic forces that entry to 0. | ||
| 53 | * Make sure it was indeed properly unmapped. | ||
| 54 | */ | ||
| 55 | BUG_ON(!pte_none(*(TOP_PTE(vaddr)))); | ||
| 56 | #endif | ||
| 57 | set_pte_ext(TOP_PTE(vaddr), mk_pte(page, kmap_prot), 0); | ||
| 58 | /* | ||
| 59 | * When debugging is off, kunmap_atomic leaves the previous mapping | ||
| 60 | * in place, so this TLB flush ensures the TLB is updated with the | ||
| 61 | * new mapping. | ||
| 62 | */ | ||
| 63 | local_flush_tlb_kernel_page(vaddr); | ||
| 64 | |||
| 65 | return (void *)vaddr; | ||
| 66 | } | ||
| 67 | EXPORT_SYMBOL(kmap_atomic); | ||
| 68 | |||
| 69 | void kunmap_atomic(void *kvaddr, enum km_type type) | ||
| 70 | { | ||
| 71 | unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK; | ||
| 72 | unsigned int idx = type + KM_TYPE_NR * smp_processor_id(); | ||
| 73 | |||
| 74 | if (kvaddr >= (void *)FIXADDR_START) { | ||
| 75 | __cpuc_flush_dcache_page((void *)vaddr); | ||
| 76 | #ifdef CONFIG_DEBUG_HIGHMEM | ||
| 77 | BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx)); | ||
| 78 | set_pte_ext(TOP_PTE(vaddr), __pte(0), 0); | ||
| 79 | local_flush_tlb_kernel_page(vaddr); | ||
| 80 | #else | ||
| 81 | (void) idx; /* to kill a warning */ | ||
| 82 | #endif | ||
| 83 | } | ||
| 84 | pagefault_enable(); | ||
| 85 | } | ||
| 86 | EXPORT_SYMBOL(kunmap_atomic); | ||
| 87 | |||
| 88 | void *kmap_atomic_pfn(unsigned long pfn, enum km_type type) | ||
| 89 | { | ||
| 90 | unsigned int idx; | ||
| 91 | unsigned long vaddr; | ||
| 92 | |||
| 93 | pagefault_disable(); | ||
| 94 | |||
| 95 | idx = type + KM_TYPE_NR * smp_processor_id(); | ||
| 96 | vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); | ||
| 97 | #ifdef CONFIG_DEBUG_HIGHMEM | ||
| 98 | BUG_ON(!pte_none(*(TOP_PTE(vaddr)))); | ||
| 99 | #endif | ||
| 100 | set_pte_ext(TOP_PTE(vaddr), pfn_pte(pfn, kmap_prot), 0); | ||
| 101 | local_flush_tlb_kernel_page(vaddr); | ||
| 102 | |||
| 103 | return (void *)vaddr; | ||
| 104 | } | ||
| 105 | |||
| 106 | struct page *kmap_atomic_to_page(const void *ptr) | ||
| 107 | { | ||
| 108 | unsigned long vaddr = (unsigned long)ptr; | ||
| 109 | pte_t *pte; | ||
| 110 | |||
| 111 | if (vaddr < FIXADDR_START) | ||
| 112 | return virt_to_page(ptr); | ||
| 113 | |||
| 114 | pte = TOP_PTE(vaddr); | ||
| 115 | return pte_page(*pte); | ||
| 116 | } | ||
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c index 34df4d9d03a6..8277802ec859 100644 --- a/arch/arm/mm/init.c +++ b/arch/arm/mm/init.c | |||
| @@ -15,6 +15,7 @@ | |||
| 15 | #include <linux/mman.h> | 15 | #include <linux/mman.h> |
| 16 | #include <linux/nodemask.h> | 16 | #include <linux/nodemask.h> |
| 17 | #include <linux/initrd.h> | 17 | #include <linux/initrd.h> |
| 18 | #include <linux/highmem.h> | ||
| 18 | 19 | ||
| 19 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
| 20 | #include <asm/sections.h> | 21 | #include <asm/sections.h> |
| @@ -382,7 +383,7 @@ void __init bootmem_init(void) | |||
| 382 | for_each_node(node) | 383 | for_each_node(node) |
| 383 | bootmem_free_node(node, mi); | 384 | bootmem_free_node(node, mi); |
| 384 | 385 | ||
| 385 | high_memory = __va(memend_pfn << PAGE_SHIFT); | 386 | high_memory = __va((memend_pfn << PAGE_SHIFT) - 1) + 1; |
| 386 | 387 | ||
| 387 | /* | 388 | /* |
| 388 | * This doesn't seem to be used by the Linux memory manager any | 389 | * This doesn't seem to be used by the Linux memory manager any |
| @@ -485,7 +486,7 @@ void __init mem_init(void) | |||
| 485 | int i, node; | 486 | int i, node; |
| 486 | 487 | ||
| 487 | #ifndef CONFIG_DISCONTIGMEM | 488 | #ifndef CONFIG_DISCONTIGMEM |
| 488 | max_mapnr = virt_to_page(high_memory) - mem_map; | 489 | max_mapnr = pfn_to_page(max_pfn + PHYS_PFN_OFFSET) - mem_map; |
| 489 | #endif | 490 | #endif |
| 490 | 491 | ||
| 491 | /* this will put all unused low memory onto the freelists */ | 492 | /* this will put all unused low memory onto the freelists */ |
| @@ -504,6 +505,19 @@ void __init mem_init(void) | |||
| 504 | __phys_to_pfn(__pa(swapper_pg_dir)), NULL); | 505 | __phys_to_pfn(__pa(swapper_pg_dir)), NULL); |
| 505 | #endif | 506 | #endif |
| 506 | 507 | ||
| 508 | #ifdef CONFIG_HIGHMEM | ||
| 509 | /* set highmem page free */ | ||
| 510 | for_each_online_node(node) { | ||
| 511 | for_each_nodebank (i, &meminfo, node) { | ||
| 512 | unsigned long start = bank_pfn_start(&meminfo.bank[i]); | ||
| 513 | unsigned long end = bank_pfn_end(&meminfo.bank[i]); | ||
| 514 | if (start >= max_low_pfn + PHYS_PFN_OFFSET) | ||
| 515 | totalhigh_pages += free_area(start, end, NULL); | ||
| 516 | } | ||
| 517 | } | ||
| 518 | totalram_pages += totalhigh_pages; | ||
| 519 | #endif | ||
| 520 | |||
| 507 | /* | 521 | /* |
| 508 | * Since our memory may not be contiguous, calculate the | 522 | * Since our memory may not be contiguous, calculate the |
| 509 | * real number of pages we have in this system | 523 | * real number of pages we have in this system |
| @@ -521,9 +535,10 @@ void __init mem_init(void) | |||
| 521 | initsize = __init_end - __init_begin; | 535 | initsize = __init_end - __init_begin; |
| 522 | 536 | ||
| 523 | printk(KERN_NOTICE "Memory: %luKB available (%dK code, " | 537 | printk(KERN_NOTICE "Memory: %luKB available (%dK code, " |
| 524 | "%dK data, %dK init)\n", | 538 | "%dK data, %dK init, %luK highmem)\n", |
| 525 | (unsigned long) nr_free_pages() << (PAGE_SHIFT-10), | 539 | (unsigned long) nr_free_pages() << (PAGE_SHIFT-10), |
| 526 | codesize >> 10, datasize >> 10, initsize >> 10); | 540 | codesize >> 10, datasize >> 10, initsize >> 10, |
| 541 | (unsigned long) (totalhigh_pages << (PAGE_SHIFT-10))); | ||
| 527 | 542 | ||
| 528 | if (PAGE_SIZE >= 16384 && num_physpages <= 128) { | 543 | if (PAGE_SIZE >= 16384 && num_physpages <= 128) { |
| 529 | extern int sysctl_overcommit_memory; | 544 | extern int sysctl_overcommit_memory; |
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index 95bbe112965e..c4f6f05198e0 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h | |||
| @@ -1,7 +1,6 @@ | |||
| 1 | /* the upper-most page table pointer */ | ||
| 2 | |||
| 3 | #ifdef CONFIG_MMU | 1 | #ifdef CONFIG_MMU |
| 4 | 2 | ||
| 3 | /* the upper-most page table pointer */ | ||
| 5 | extern pmd_t *top_pmd; | 4 | extern pmd_t *top_pmd; |
| 6 | 5 | ||
| 7 | #define TOP_PTE(x) pte_offset_kernel(top_pmd, x) | 6 | #define TOP_PTE(x) pte_offset_kernel(top_pmd, x) |
diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c index 5358fcc7f61e..f7457fea6de8 100644 --- a/arch/arm/mm/mmap.c +++ b/arch/arm/mm/mmap.c | |||
| @@ -124,7 +124,7 @@ int valid_phys_addr_range(unsigned long addr, size_t size) | |||
| 124 | { | 124 | { |
| 125 | if (addr < PHYS_OFFSET) | 125 | if (addr < PHYS_OFFSET) |
| 126 | return 0; | 126 | return 0; |
| 127 | if (addr + size > __pa(high_memory)) | 127 | if (addr + size >= __pa(high_memory - 1)) |
| 128 | return 0; | 128 | return 0; |
| 129 | 129 | ||
| 130 | return 1; | 130 | return 1; |
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index d4d082c5c2d4..1585814f8414 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c | |||
| @@ -18,9 +18,11 @@ | |||
| 18 | #include <asm/cputype.h> | 18 | #include <asm/cputype.h> |
| 19 | #include <asm/mach-types.h> | 19 | #include <asm/mach-types.h> |
| 20 | #include <asm/sections.h> | 20 | #include <asm/sections.h> |
| 21 | #include <asm/cachetype.h> | ||
| 21 | #include <asm/setup.h> | 22 | #include <asm/setup.h> |
| 22 | #include <asm/sizes.h> | 23 | #include <asm/sizes.h> |
| 23 | #include <asm/tlb.h> | 24 | #include <asm/tlb.h> |
| 25 | #include <asm/highmem.h> | ||
| 24 | 26 | ||
| 25 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
| 26 | #include <asm/mach/map.h> | 28 | #include <asm/mach/map.h> |
| @@ -243,6 +245,10 @@ static struct mem_type mem_types[] = { | |||
| 243 | .prot_sect = PMD_TYPE_SECT, | 245 | .prot_sect = PMD_TYPE_SECT, |
| 244 | .domain = DOMAIN_KERNEL, | 246 | .domain = DOMAIN_KERNEL, |
| 245 | }, | 247 | }, |
| 248 | [MT_MEMORY_NONCACHED] = { | ||
| 249 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, | ||
| 250 | .domain = DOMAIN_KERNEL, | ||
| 251 | }, | ||
| 246 | }; | 252 | }; |
| 247 | 253 | ||
| 248 | const struct mem_type *get_mem_type(unsigned int type) | 254 | const struct mem_type *get_mem_type(unsigned int type) |
| @@ -406,9 +412,28 @@ static void __init build_mem_type_table(void) | |||
| 406 | kern_pgprot |= L_PTE_SHARED; | 412 | kern_pgprot |= L_PTE_SHARED; |
| 407 | vecs_pgprot |= L_PTE_SHARED; | 413 | vecs_pgprot |= L_PTE_SHARED; |
| 408 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; | 414 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; |
| 415 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; | ||
| 409 | #endif | 416 | #endif |
| 410 | } | 417 | } |
| 411 | 418 | ||
| 419 | /* | ||
| 420 | * Non-cacheable Normal - intended for memory areas that must | ||
| 421 | * not cause dirty cache line writebacks when used | ||
| 422 | */ | ||
| 423 | if (cpu_arch >= CPU_ARCH_ARMv6) { | ||
| 424 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | ||
| 425 | /* Non-cacheable Normal is XCB = 001 */ | ||
| 426 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | ||
| 427 | PMD_SECT_BUFFERED; | ||
| 428 | } else { | ||
| 429 | /* For both ARMv6 and non-TEX-remapping ARMv7 */ | ||
| 430 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | ||
| 431 | PMD_SECT_TEX(1); | ||
| 432 | } | ||
| 433 | } else { | ||
| 434 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; | ||
| 435 | } | ||
| 436 | |||
| 412 | for (i = 0; i < 16; i++) { | 437 | for (i = 0; i < 16; i++) { |
| 413 | unsigned long v = pgprot_val(protection_map[i]); | 438 | unsigned long v = pgprot_val(protection_map[i]); |
| 414 | protection_map[i] = __pgprot(v | user_pgprot); | 439 | protection_map[i] = __pgprot(v | user_pgprot); |
| @@ -677,6 +702,10 @@ static void __init sanity_check_meminfo(void) | |||
| 677 | if (meminfo.nr_banks >= NR_BANKS) { | 702 | if (meminfo.nr_banks >= NR_BANKS) { |
| 678 | printk(KERN_CRIT "NR_BANKS too low, " | 703 | printk(KERN_CRIT "NR_BANKS too low, " |
| 679 | "ignoring high memory\n"); | 704 | "ignoring high memory\n"); |
| 705 | } else if (cache_is_vipt_aliasing()) { | ||
| 706 | printk(KERN_CRIT "HIGHMEM is not yet supported " | ||
| 707 | "with VIPT aliasing cache, " | ||
| 708 | "ignoring high memory\n"); | ||
| 680 | } else { | 709 | } else { |
| 681 | memmove(bank + 1, bank, | 710 | memmove(bank + 1, bank, |
| 682 | (meminfo.nr_banks - i) * sizeof(*bank)); | 711 | (meminfo.nr_banks - i) * sizeof(*bank)); |
| @@ -895,6 +924,17 @@ static void __init devicemaps_init(struct machine_desc *mdesc) | |||
| 895 | flush_cache_all(); | 924 | flush_cache_all(); |
| 896 | } | 925 | } |
| 897 | 926 | ||
| 927 | static void __init kmap_init(void) | ||
| 928 | { | ||
| 929 | #ifdef CONFIG_HIGHMEM | ||
| 930 | pmd_t *pmd = pmd_off_k(PKMAP_BASE); | ||
| 931 | pte_t *pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t)); | ||
| 932 | BUG_ON(!pmd_none(*pmd) || !pte); | ||
| 933 | __pmd_populate(pmd, __pa(pte) | _PAGE_KERNEL_TABLE); | ||
| 934 | pkmap_page_table = pte + PTRS_PER_PTE; | ||
| 935 | #endif | ||
| 936 | } | ||
| 937 | |||
| 898 | /* | 938 | /* |
| 899 | * paging_init() sets up the page tables, initialises the zone memory | 939 | * paging_init() sets up the page tables, initialises the zone memory |
| 900 | * maps, and sets up the zero page, bad page and bad page tables. | 940 | * maps, and sets up the zero page, bad page and bad page tables. |
| @@ -908,6 +948,7 @@ void __init paging_init(struct machine_desc *mdesc) | |||
| 908 | prepare_page_table(); | 948 | prepare_page_table(); |
| 909 | bootmem_init(); | 949 | bootmem_init(); |
| 910 | devicemaps_init(mdesc); | 950 | devicemaps_init(mdesc); |
| 951 | kmap_init(); | ||
| 911 | 952 | ||
| 912 | top_pmd = pmd_off_k(0xffff0000); | 953 | top_pmd = pmd_off_k(0xffff0000); |
| 913 | 954 | ||
diff --git a/arch/arm/mm/proc-mohawk.S b/arch/arm/mm/proc-mohawk.S new file mode 100644 index 000000000000..540f5078496b --- /dev/null +++ b/arch/arm/mm/proc-mohawk.S | |||
| @@ -0,0 +1,416 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/mm/proc-mohawk.S: MMU functions for Marvell PJ1 core | ||
| 3 | * | ||
| 4 | * PJ1 (codename Mohawk) is a hybrid of the xscale3 and Marvell's own core. | ||
| 5 | * | ||
| 6 | * Heavily based on proc-arm926.S and proc-xsc3.S | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #include <linux/linkage.h> | ||
| 24 | #include <linux/init.h> | ||
| 25 | #include <asm/assembler.h> | ||
| 26 | #include <asm/hwcap.h> | ||
| 27 | #include <asm/pgtable-hwdef.h> | ||
| 28 | #include <asm/pgtable.h> | ||
| 29 | #include <asm/page.h> | ||
| 30 | #include <asm/ptrace.h> | ||
| 31 | #include "proc-macros.S" | ||
| 32 | |||
| 33 | /* | ||
| 34 | * This is the maximum size of an area which will be flushed. If the | ||
| 35 | * area is larger than this, then we flush the whole cache. | ||
| 36 | */ | ||
| 37 | #define CACHE_DLIMIT 32768 | ||
| 38 | |||
| 39 | /* | ||
| 40 | * The cache line size of the L1 D cache. | ||
| 41 | */ | ||
| 42 | #define CACHE_DLINESIZE 32 | ||
| 43 | |||
| 44 | /* | ||
| 45 | * cpu_mohawk_proc_init() | ||
| 46 | */ | ||
| 47 | ENTRY(cpu_mohawk_proc_init) | ||
| 48 | mov pc, lr | ||
| 49 | |||
| 50 | /* | ||
| 51 | * cpu_mohawk_proc_fin() | ||
| 52 | */ | ||
| 53 | ENTRY(cpu_mohawk_proc_fin) | ||
| 54 | stmfd sp!, {lr} | ||
| 55 | mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE | ||
| 56 | msr cpsr_c, ip | ||
| 57 | bl mohawk_flush_kern_cache_all | ||
| 58 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register | ||
| 59 | bic r0, r0, #0x1800 @ ...iz........... | ||
| 60 | bic r0, r0, #0x0006 @ .............ca. | ||
| 61 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | ||
| 62 | ldmfd sp!, {pc} | ||
| 63 | |||
| 64 | /* | ||
| 65 | * cpu_mohawk_reset(loc) | ||
| 66 | * | ||
| 67 | * Perform a soft reset of the system. Put the CPU into the | ||
| 68 | * same state as it would be if it had been reset, and branch | ||
| 69 | * to what would be the reset vector. | ||
| 70 | * | ||
| 71 | * loc: location to jump to for soft reset | ||
| 72 | * | ||
| 73 | * (same as arm926) | ||
| 74 | */ | ||
| 75 | .align 5 | ||
| 76 | ENTRY(cpu_mohawk_reset) | ||
| 77 | mov ip, #0 | ||
| 78 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | ||
| 79 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | ||
| 80 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | ||
| 81 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register | ||
| 82 | bic ip, ip, #0x0007 @ .............cam | ||
| 83 | bic ip, ip, #0x1100 @ ...i...s........ | ||
| 84 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | ||
| 85 | mov pc, r0 | ||
| 86 | |||
| 87 | /* | ||
| 88 | * cpu_mohawk_do_idle() | ||
| 89 | * | ||
| 90 | * Called with IRQs disabled | ||
| 91 | */ | ||
| 92 | .align 5 | ||
| 93 | ENTRY(cpu_mohawk_do_idle) | ||
| 94 | mov r0, #0 | ||
| 95 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | ||
| 96 | mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt | ||
| 97 | mov pc, lr | ||
| 98 | |||
| 99 | /* | ||
| 100 | * flush_user_cache_all() | ||
| 101 | * | ||
| 102 | * Clean and invalidate all cache entries in a particular | ||
| 103 | * address space. | ||
| 104 | */ | ||
| 105 | ENTRY(mohawk_flush_user_cache_all) | ||
| 106 | /* FALLTHROUGH */ | ||
| 107 | |||
| 108 | /* | ||
| 109 | * flush_kern_cache_all() | ||
| 110 | * | ||
| 111 | * Clean and invalidate the entire cache. | ||
| 112 | */ | ||
| 113 | ENTRY(mohawk_flush_kern_cache_all) | ||
| 114 | mov r2, #VM_EXEC | ||
| 115 | mov ip, #0 | ||
| 116 | __flush_whole_cache: | ||
| 117 | mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache | ||
| 118 | tst r2, #VM_EXEC | ||
| 119 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | ||
| 120 | mcrne p15, 0, ip, c7, c10, 0 @ drain write buffer | ||
| 121 | mov pc, lr | ||
| 122 | |||
| 123 | /* | ||
| 124 | * flush_user_cache_range(start, end, flags) | ||
| 125 | * | ||
| 126 | * Clean and invalidate a range of cache entries in the | ||
| 127 | * specified address range. | ||
| 128 | * | ||
| 129 | * - start - start address (inclusive) | ||
| 130 | * - end - end address (exclusive) | ||
| 131 | * - flags - vm_flags describing address space | ||
| 132 | * | ||
| 133 | * (same as arm926) | ||
| 134 | */ | ||
| 135 | ENTRY(mohawk_flush_user_cache_range) | ||
| 136 | mov ip, #0 | ||
| 137 | sub r3, r1, r0 @ calculate total size | ||
| 138 | cmp r3, #CACHE_DLIMIT | ||
| 139 | bgt __flush_whole_cache | ||
| 140 | 1: tst r2, #VM_EXEC | ||
| 141 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry | ||
| 142 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | ||
| 143 | add r0, r0, #CACHE_DLINESIZE | ||
| 144 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry | ||
| 145 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | ||
| 146 | add r0, r0, #CACHE_DLINESIZE | ||
| 147 | cmp r0, r1 | ||
| 148 | blo 1b | ||
| 149 | tst r2, #VM_EXEC | ||
| 150 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | ||
| 151 | mov pc, lr | ||
| 152 | |||
| 153 | /* | ||
| 154 | * coherent_kern_range(start, end) | ||
| 155 | * | ||
| 156 | * Ensure coherency between the Icache and the Dcache in the | ||
| 157 | * region described by start, end. If you have non-snooping | ||
| 158 | * Harvard caches, you need to implement this function. | ||
| 159 | * | ||
| 160 | * - start - virtual start address | ||
| 161 | * - end - virtual end address | ||
| 162 | */ | ||
| 163 | ENTRY(mohawk_coherent_kern_range) | ||
| 164 | /* FALLTHROUGH */ | ||
| 165 | |||
| 166 | /* | ||
| 167 | * coherent_user_range(start, end) | ||
| 168 | * | ||
| 169 | * Ensure coherency between the Icache and the Dcache in the | ||
| 170 | * region described by start, end. If you have non-snooping | ||
| 171 | * Harvard caches, you need to implement this function. | ||
| 172 | * | ||
| 173 | * - start - virtual start address | ||
| 174 | * - end - virtual end address | ||
| 175 | * | ||
| 176 | * (same as arm926) | ||
| 177 | */ | ||
| 178 | ENTRY(mohawk_coherent_user_range) | ||
| 179 | bic r0, r0, #CACHE_DLINESIZE - 1 | ||
| 180 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | ||
| 181 | mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry | ||
| 182 | add r0, r0, #CACHE_DLINESIZE | ||
| 183 | cmp r0, r1 | ||
| 184 | blo 1b | ||
| 185 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | ||
| 186 | mov pc, lr | ||
| 187 | |||
| 188 | /* | ||
| 189 | * flush_kern_dcache_page(void *page) | ||
| 190 | * | ||
| 191 | * Ensure no D cache aliasing occurs, either with itself or | ||
| 192 | * the I cache | ||
| 193 | * | ||
| 194 | * - addr - page aligned address | ||
| 195 | */ | ||
| 196 | ENTRY(mohawk_flush_kern_dcache_page) | ||
| 197 | add r1, r0, #PAGE_SZ | ||
| 198 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | ||
| 199 | add r0, r0, #CACHE_DLINESIZE | ||
| 200 | cmp r0, r1 | ||
| 201 | blo 1b | ||
| 202 | mov r0, #0 | ||
| 203 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | ||
| 204 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | ||
| 205 | mov pc, lr | ||
| 206 | |||
| 207 | /* | ||
| 208 | * dma_inv_range(start, end) | ||
| 209 | * | ||
| 210 | * Invalidate (discard) the specified virtual address range. | ||
| 211 | * May not write back any entries. If 'start' or 'end' | ||
| 212 | * are not cache line aligned, those lines must be written | ||
| 213 | * back. | ||
| 214 | * | ||
| 215 | * - start - virtual start address | ||
| 216 | * - end - virtual end address | ||
| 217 | * | ||
| 218 | * (same as v4wb) | ||
| 219 | */ | ||
| 220 | ENTRY(mohawk_dma_inv_range) | ||
| 221 | tst r0, #CACHE_DLINESIZE - 1 | ||
| 222 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | ||
| 223 | tst r1, #CACHE_DLINESIZE - 1 | ||
| 224 | mcrne p15, 0, r1, c7, c10, 1 @ clean D entry | ||
| 225 | bic r0, r0, #CACHE_DLINESIZE - 1 | ||
| 226 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | ||
| 227 | add r0, r0, #CACHE_DLINESIZE | ||
| 228 | cmp r0, r1 | ||
| 229 | blo 1b | ||
| 230 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | ||
| 231 | mov pc, lr | ||
| 232 | |||
| 233 | /* | ||
| 234 | * dma_clean_range(start, end) | ||
| 235 | * | ||
| 236 | * Clean the specified virtual address range. | ||
| 237 | * | ||
| 238 | * - start - virtual start address | ||
| 239 | * - end - virtual end address | ||
| 240 | * | ||
| 241 | * (same as v4wb) | ||
| 242 | */ | ||
| 243 | ENTRY(mohawk_dma_clean_range) | ||
| 244 | bic r0, r0, #CACHE_DLINESIZE - 1 | ||
| 245 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | ||
| 246 | add r0, r0, #CACHE_DLINESIZE | ||
| 247 | cmp r0, r1 | ||
| 248 | blo 1b | ||
| 249 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | ||
| 250 | mov pc, lr | ||
| 251 | |||
| 252 | /* | ||
| 253 | * dma_flush_range(start, end) | ||
| 254 | * | ||
| 255 | * Clean and invalidate the specified virtual address range. | ||
| 256 | * | ||
| 257 | * - start - virtual start address | ||
| 258 | * - end - virtual end address | ||
| 259 | */ | ||
| 260 | ENTRY(mohawk_dma_flush_range) | ||
| 261 | bic r0, r0, #CACHE_DLINESIZE - 1 | ||
| 262 | 1: | ||
| 263 | mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | ||
| 264 | add r0, r0, #CACHE_DLINESIZE | ||
| 265 | cmp r0, r1 | ||
| 266 | blo 1b | ||
| 267 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | ||
| 268 | mov pc, lr | ||
| 269 | |||
| 270 | ENTRY(mohawk_cache_fns) | ||
| 271 | .long mohawk_flush_kern_cache_all | ||
| 272 | .long mohawk_flush_user_cache_all | ||
| 273 | .long mohawk_flush_user_cache_range | ||
| 274 | .long mohawk_coherent_kern_range | ||
| 275 | .long mohawk_coherent_user_range | ||
| 276 | .long mohawk_flush_kern_dcache_page | ||
| 277 | .long mohawk_dma_inv_range | ||
| 278 | .long mohawk_dma_clean_range | ||
| 279 | .long mohawk_dma_flush_range | ||
| 280 | |||
| 281 | ENTRY(cpu_mohawk_dcache_clean_area) | ||
| 282 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | ||
| 283 | add r0, r0, #CACHE_DLINESIZE | ||
| 284 | subs r1, r1, #CACHE_DLINESIZE | ||
| 285 | bhi 1b | ||
| 286 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | ||
| 287 | mov pc, lr | ||
| 288 | |||
| 289 | /* | ||
| 290 | * cpu_mohawk_switch_mm(pgd) | ||
| 291 | * | ||
| 292 | * Set the translation base pointer to be as described by pgd. | ||
| 293 | * | ||
| 294 | * pgd: new page tables | ||
| 295 | */ | ||
| 296 | .align 5 | ||
| 297 | ENTRY(cpu_mohawk_switch_mm) | ||
| 298 | mov ip, #0 | ||
| 299 | mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache | ||
| 300 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache | ||
| 301 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | ||
| 302 | orr r0, r0, #0x18 @ cache the page table in L2 | ||
| 303 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer | ||
| 304 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | ||
| 305 | mov pc, lr | ||
| 306 | |||
| 307 | /* | ||
| 308 | * cpu_mohawk_set_pte_ext(ptep, pte, ext) | ||
| 309 | * | ||
| 310 | * Set a PTE and flush it out | ||
| 311 | */ | ||
| 312 | .align 5 | ||
| 313 | ENTRY(cpu_mohawk_set_pte_ext) | ||
| 314 | armv3_set_pte_ext | ||
| 315 | mov r0, r0 | ||
| 316 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | ||
| 317 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | ||
| 318 | mov pc, lr | ||
| 319 | |||
| 320 | __INIT | ||
| 321 | |||
| 322 | .type __mohawk_setup, #function | ||
| 323 | __mohawk_setup: | ||
| 324 | mov r0, #0 | ||
| 325 | mcr p15, 0, r0, c7, c7 @ invalidate I,D caches | ||
| 326 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | ||
| 327 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs | ||
| 328 | orr r4, r4, #0x18 @ cache the page table in L2 | ||
| 329 | mcr p15, 0, r4, c2, c0, 0 @ load page table pointer | ||
| 330 | |||
| 331 | mov r0, #0 @ don't allow CP access | ||
| 332 | mcr p15, 0, r0, c15, c1, 0 @ write CP access register | ||
| 333 | |||
| 334 | adr r5, mohawk_crval | ||
| 335 | ldmia r5, {r5, r6} | ||
| 336 | mrc p15, 0, r0, c1, c0 @ get control register | ||
| 337 | bic r0, r0, r5 | ||
| 338 | orr r0, r0, r6 | ||
| 339 | mov pc, lr | ||
| 340 | |||
| 341 | .size __mohawk_setup, . - __mohawk_setup | ||
| 342 | |||
| 343 | /* | ||
| 344 | * R | ||
| 345 | * .RVI ZFRS BLDP WCAM | ||
| 346 | * .011 1001 ..00 0101 | ||
| 347 | * | ||
| 348 | */ | ||
| 349 | .type mohawk_crval, #object | ||
| 350 | mohawk_crval: | ||
| 351 | crval clear=0x00007f3f, mmuset=0x00003905, ucset=0x00001134 | ||
| 352 | |||
| 353 | __INITDATA | ||
| 354 | |||
| 355 | /* | ||
| 356 | * Purpose : Function pointers used to access above functions - all calls | ||
| 357 | * come through these | ||
| 358 | */ | ||
| 359 | .type mohawk_processor_functions, #object | ||
| 360 | mohawk_processor_functions: | ||
| 361 | .word v5t_early_abort | ||
| 362 | .word pabort_noifar | ||
| 363 | .word cpu_mohawk_proc_init | ||
| 364 | .word cpu_mohawk_proc_fin | ||
| 365 | .word cpu_mohawk_reset | ||
| 366 | .word cpu_mohawk_do_idle | ||
| 367 | .word cpu_mohawk_dcache_clean_area | ||
| 368 | .word cpu_mohawk_switch_mm | ||
| 369 | .word cpu_mohawk_set_pte_ext | ||
| 370 | .size mohawk_processor_functions, . - mohawk_processor_functions | ||
| 371 | |||
| 372 | .section ".rodata" | ||
| 373 | |||
| 374 | .type cpu_arch_name, #object | ||
| 375 | cpu_arch_name: | ||
| 376 | .asciz "armv5te" | ||
| 377 | .size cpu_arch_name, . - cpu_arch_name | ||
| 378 | |||
| 379 | .type cpu_elf_name, #object | ||
| 380 | cpu_elf_name: | ||
| 381 | .asciz "v5" | ||
| 382 | .size cpu_elf_name, . - cpu_elf_name | ||
| 383 | |||
| 384 | .type cpu_mohawk_name, #object | ||
| 385 | cpu_mohawk_name: | ||
| 386 | .asciz "Marvell 88SV331x" | ||
| 387 | .size cpu_mohawk_name, . - cpu_mohawk_name | ||
| 388 | |||
| 389 | .align | ||
| 390 | |||
| 391 | .section ".proc.info.init", #alloc, #execinstr | ||
| 392 | |||
| 393 | .type __88sv331x_proc_info,#object | ||
| 394 | __88sv331x_proc_info: | ||
| 395 | .long 0x56158000 @ Marvell 88SV331x (MOHAWK) | ||
| 396 | .long 0xfffff000 | ||
| 397 | .long PMD_TYPE_SECT | \ | ||
| 398 | PMD_SECT_BUFFERABLE | \ | ||
| 399 | PMD_SECT_CACHEABLE | \ | ||
| 400 | PMD_BIT4 | \ | ||
| 401 | PMD_SECT_AP_WRITE | \ | ||
| 402 | PMD_SECT_AP_READ | ||
| 403 | .long PMD_TYPE_SECT | \ | ||
| 404 | PMD_BIT4 | \ | ||
| 405 | PMD_SECT_AP_WRITE | \ | ||
| 406 | PMD_SECT_AP_READ | ||
| 407 | b __mohawk_setup | ||
| 408 | .long cpu_arch_name | ||
| 409 | .long cpu_elf_name | ||
| 410 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP | ||
| 411 | .long cpu_mohawk_name | ||
| 412 | .long mohawk_processor_functions | ||
| 413 | .long v4wbi_tlb_fns | ||
| 414 | .long v4wb_user_fns | ||
| 415 | .long mohawk_cache_fns | ||
| 416 | .size __88sv331x_proc_info, . - __88sv331x_proc_info | ||
diff --git a/arch/arm/oprofile/backtrace.c b/arch/arm/oprofile/backtrace.c index cefc21c2eee4..d805a52b5032 100644 --- a/arch/arm/oprofile/backtrace.c +++ b/arch/arm/oprofile/backtrace.c | |||
| @@ -18,15 +18,14 @@ | |||
| 18 | #include <linux/mm.h> | 18 | #include <linux/mm.h> |
| 19 | #include <linux/uaccess.h> | 19 | #include <linux/uaccess.h> |
| 20 | #include <asm/ptrace.h> | 20 | #include <asm/ptrace.h> |
| 21 | 21 | #include <asm/stacktrace.h> | |
| 22 | #include "../kernel/stacktrace.h" | ||
| 23 | 22 | ||
| 24 | static int report_trace(struct stackframe *frame, void *d) | 23 | static int report_trace(struct stackframe *frame, void *d) |
| 25 | { | 24 | { |
| 26 | unsigned int *depth = d; | 25 | unsigned int *depth = d; |
| 27 | 26 | ||
| 28 | if (*depth) { | 27 | if (*depth) { |
| 29 | oprofile_add_trace(frame->lr); | 28 | oprofile_add_trace(frame->pc); |
| 30 | (*depth)--; | 29 | (*depth)--; |
| 31 | } | 30 | } |
| 32 | 31 | ||
| @@ -70,9 +69,12 @@ void arm_backtrace(struct pt_regs * const regs, unsigned int depth) | |||
| 70 | struct frame_tail *tail = ((struct frame_tail *) regs->ARM_fp) - 1; | 69 | struct frame_tail *tail = ((struct frame_tail *) regs->ARM_fp) - 1; |
| 71 | 70 | ||
| 72 | if (!user_mode(regs)) { | 71 | if (!user_mode(regs)) { |
| 73 | unsigned long base = ((unsigned long)regs) & ~(THREAD_SIZE - 1); | 72 | struct stackframe frame; |
| 74 | walk_stackframe(regs->ARM_fp, base, base + THREAD_SIZE, | 73 | frame.fp = regs->ARM_fp; |
| 75 | report_trace, &depth); | 74 | frame.sp = regs->ARM_sp; |
| 75 | frame.lr = regs->ARM_lr; | ||
| 76 | frame.pc = regs->ARM_pc; | ||
| 77 | walk_stackframe(&frame, report_trace, &depth); | ||
| 76 | return; | 78 | return; |
| 77 | } | 79 | } |
| 78 | 80 | ||
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig index 9cc2b16fdf79..17d0e9906d5f 100644 --- a/arch/arm/plat-mxc/Kconfig +++ b/arch/arm/plat-mxc/Kconfig | |||
| @@ -3,7 +3,7 @@ if ARCH_MXC | |||
| 3 | menu "Freescale MXC Implementations" | 3 | menu "Freescale MXC Implementations" |
| 4 | 4 | ||
| 5 | choice | 5 | choice |
| 6 | prompt "MXC/iMX Base Type" | 6 | prompt "Freescale CPU family:" |
| 7 | default ARCH_MX3 | 7 | default ARCH_MX3 |
| 8 | 8 | ||
| 9 | config ARCH_MX1 | 9 | config ARCH_MX1 |
| @@ -15,12 +15,14 @@ config ARCH_MX1 | |||
| 15 | config ARCH_MX2 | 15 | config ARCH_MX2 |
| 16 | bool "MX2-based" | 16 | bool "MX2-based" |
| 17 | select CPU_ARM926T | 17 | select CPU_ARM926T |
| 18 | select COMMON_CLKDEV | ||
| 18 | help | 19 | help |
| 19 | This enables support for systems based on the Freescale i.MX2 family | 20 | This enables support for systems based on the Freescale i.MX2 family |
| 20 | 21 | ||
| 21 | config ARCH_MX3 | 22 | config ARCH_MX3 |
| 22 | bool "MX3-based" | 23 | bool "MX3-based" |
| 23 | select CPU_V6 | 24 | select CPU_V6 |
| 25 | select COMMON_CLKDEV | ||
| 24 | help | 26 | help |
| 25 | This enables support for systems based on the Freescale i.MX3 family | 27 | This enables support for systems based on the Freescale i.MX3 family |
| 26 | 28 | ||
| @@ -43,4 +45,10 @@ config MXC_IRQ_PRIOR | |||
| 43 | requirements for timing. | 45 | requirements for timing. |
| 44 | Say N here, unless you have a specialized requirement. | 46 | Say N here, unless you have a specialized requirement. |
| 45 | 47 | ||
| 48 | config MXC_PWM | ||
| 49 | tristate "Enable PWM driver" | ||
| 50 | depends on ARCH_MXC | ||
| 51 | help | ||
| 52 | Enable support for the i.MX PWM controller(s). | ||
| 53 | |||
| 46 | endif | 54 | endif |
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile index db74a929179d..564fd4ebf38a 100644 --- a/arch/arm/plat-mxc/Makefile +++ b/arch/arm/plat-mxc/Makefile | |||
| @@ -3,7 +3,8 @@ | |||
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | # Common support | 5 | # Common support |
| 6 | obj-y := irq.o clock.o gpio.o time.o devices.o | 6 | obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o |
| 7 | 7 | ||
| 8 | obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o | 8 | obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o |
| 9 | obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o | 9 | obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o |
| 10 | obj-$(CONFIG_MXC_PWM) += pwm.o | ||
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c index 0a38f0b396eb..92e13566cd4f 100644 --- a/arch/arm/plat-mxc/clock.c +++ b/arch/arm/plat-mxc/clock.c | |||
| @@ -48,6 +48,11 @@ static DEFINE_MUTEX(clocks_mutex); | |||
| 48 | *-------------------------------------------------------------------------*/ | 48 | *-------------------------------------------------------------------------*/ |
| 49 | 49 | ||
| 50 | /* | 50 | /* |
| 51 | * All the code inside #ifndef CONFIG_COMMON_CLKDEV can be removed once all | ||
| 52 | * MXC architectures have switched to using clkdev. | ||
| 53 | */ | ||
| 54 | #ifndef CONFIG_COMMON_CLKDEV | ||
| 55 | /* | ||
| 51 | * Retrieve a clock by name. | 56 | * Retrieve a clock by name. |
| 52 | * | 57 | * |
| 53 | * Note that we first try to use device id on the bus | 58 | * Note that we first try to use device id on the bus |
| @@ -110,6 +115,7 @@ found: | |||
| 110 | return clk; | 115 | return clk; |
| 111 | } | 116 | } |
| 112 | EXPORT_SYMBOL(clk_get); | 117 | EXPORT_SYMBOL(clk_get); |
| 118 | #endif | ||
| 113 | 119 | ||
| 114 | static void __clk_disable(struct clk *clk) | 120 | static void __clk_disable(struct clk *clk) |
| 115 | { | 121 | { |
| @@ -187,6 +193,7 @@ unsigned long clk_get_rate(struct clk *clk) | |||
| 187 | } | 193 | } |
| 188 | EXPORT_SYMBOL(clk_get_rate); | 194 | EXPORT_SYMBOL(clk_get_rate); |
| 189 | 195 | ||
| 196 | #ifndef CONFIG_COMMON_CLKDEV | ||
| 190 | /* Decrement the clock's module reference count */ | 197 | /* Decrement the clock's module reference count */ |
| 191 | void clk_put(struct clk *clk) | 198 | void clk_put(struct clk *clk) |
| 192 | { | 199 | { |
| @@ -194,6 +201,7 @@ void clk_put(struct clk *clk) | |||
| 194 | module_put(clk->owner); | 201 | module_put(clk->owner); |
| 195 | } | 202 | } |
| 196 | EXPORT_SYMBOL(clk_put); | 203 | EXPORT_SYMBOL(clk_put); |
| 204 | #endif | ||
| 197 | 205 | ||
| 198 | /* Round the requested clock rate to the nearest supported | 206 | /* Round the requested clock rate to the nearest supported |
| 199 | * rate that is less than or equal to the requested rate. | 207 | * rate that is less than or equal to the requested rate. |
| @@ -257,6 +265,7 @@ struct clk *clk_get_parent(struct clk *clk) | |||
| 257 | } | 265 | } |
| 258 | EXPORT_SYMBOL(clk_get_parent); | 266 | EXPORT_SYMBOL(clk_get_parent); |
| 259 | 267 | ||
| 268 | #ifndef CONFIG_COMMON_CLKDEV | ||
| 260 | /* | 269 | /* |
| 261 | * Add a new clock to the clock tree. | 270 | * Add a new clock to the clock tree. |
| 262 | */ | 271 | */ |
| @@ -327,4 +336,49 @@ static int __init mxc_setup_proc_entry(void) | |||
| 327 | } | 336 | } |
| 328 | 337 | ||
| 329 | late_initcall(mxc_setup_proc_entry); | 338 | late_initcall(mxc_setup_proc_entry); |
| 339 | #endif /* CONFIG_PROC_FS */ | ||
| 340 | #endif | ||
| 341 | |||
| 342 | /* | ||
| 343 | * Get the resulting clock rate from a PLL register value and the input | ||
| 344 | * frequency. PLLs with this register layout can at least be found on | ||
| 345 | * MX1, MX21, MX27 and MX31 | ||
| 346 | * | ||
| 347 | * mfi + mfn / (mfd + 1) | ||
| 348 | * f = 2 * f_ref * -------------------- | ||
| 349 | * pd + 1 | ||
| 350 | */ | ||
| 351 | unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq) | ||
| 352 | { | ||
| 353 | long long ll; | ||
| 354 | int mfn_abs; | ||
| 355 | unsigned int mfi, mfn, mfd, pd; | ||
| 356 | |||
| 357 | mfi = (reg_val >> 10) & 0xf; | ||
| 358 | mfn = reg_val & 0x3ff; | ||
| 359 | mfd = (reg_val >> 16) & 0x3ff; | ||
| 360 | pd = (reg_val >> 26) & 0xf; | ||
| 361 | |||
| 362 | mfi = mfi <= 5 ? 5 : mfi; | ||
| 363 | |||
| 364 | mfn_abs = mfn; | ||
| 365 | |||
| 366 | #if !defined CONFIG_ARCH_MX1 && !defined CONFIG_ARCH_MX21 | ||
| 367 | if (mfn >= 0x200) { | ||
| 368 | mfn |= 0xFFFFFE00; | ||
| 369 | mfn_abs = -mfn; | ||
| 370 | } | ||
| 330 | #endif | 371 | #endif |
| 372 | |||
| 373 | freq *= 2; | ||
| 374 | freq /= pd + 1; | ||
| 375 | |||
| 376 | ll = (unsigned long long)freq * mfn_abs; | ||
| 377 | |||
| 378 | do_div(ll, mfd + 1); | ||
| 379 | if (mfn < 0) | ||
| 380 | ll = -ll; | ||
| 381 | ll = (freq * mfi) + ll; | ||
| 382 | |||
| 383 | return ll; | ||
| 384 | } | ||
diff --git a/arch/arm/plat-mxc/cpu.c b/arch/arm/plat-mxc/cpu.c new file mode 100644 index 000000000000..386e0d52cf58 --- /dev/null +++ b/arch/arm/plat-mxc/cpu.c | |||
| @@ -0,0 +1,11 @@ | |||
| 1 | |||
| 2 | #include <linux/module.h> | ||
| 3 | |||
| 4 | unsigned int __mxc_cpu_type; | ||
| 5 | EXPORT_SYMBOL(__mxc_cpu_type); | ||
| 6 | |||
| 7 | void mxc_set_cpu_type(unsigned int type) | ||
| 8 | { | ||
| 9 | __mxc_cpu_type = type; | ||
| 10 | } | ||
| 11 | |||
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c index c66748267c45..56f2fb5cc456 100644 --- a/arch/arm/plat-mxc/devices.c +++ b/arch/arm/plat-mxc/devices.c | |||
| @@ -19,6 +19,7 @@ | |||
| 19 | #include <linux/kernel.h> | 19 | #include <linux/kernel.h> |
| 20 | #include <linux/init.h> | 20 | #include <linux/init.h> |
| 21 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
| 22 | #include <mach/common.h> | ||
| 22 | 23 | ||
| 23 | int __init mxc_register_device(struct platform_device *pdev, void *data) | 24 | int __init mxc_register_device(struct platform_device *pdev, void *data) |
| 24 | { | 25 | { |
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c index 2905ec758758..e364a5ed10f1 100644 --- a/arch/arm/plat-mxc/dma-mx1-mx2.c +++ b/arch/arm/plat-mxc/dma-mx1-mx2.c | |||
| @@ -113,7 +113,7 @@ struct imx_dma_channel { | |||
| 113 | void (*err_handler) (int, void *, int errcode); | 113 | void (*err_handler) (int, void *, int errcode); |
| 114 | void (*prog_handler) (int, void *, struct scatterlist *); | 114 | void (*prog_handler) (int, void *, struct scatterlist *); |
| 115 | void *data; | 115 | void *data; |
| 116 | unsigned int dma_mode; | 116 | unsigned int dma_mode; |
| 117 | struct scatterlist *sg; | 117 | struct scatterlist *sg; |
| 118 | unsigned int resbytes; | 118 | unsigned int resbytes; |
| 119 | int dma_num; | 119 | int dma_num; |
| @@ -802,7 +802,7 @@ static int __init imx_dma_init(void) | |||
| 802 | int ret = 0; | 802 | int ret = 0; |
| 803 | int i; | 803 | int i; |
| 804 | 804 | ||
| 805 | dma_clk = clk_get(NULL, "dma_clk"); | 805 | dma_clk = clk_get(NULL, "dma"); |
| 806 | clk_enable(dma_clk); | 806 | clk_enable(dma_clk); |
| 807 | 807 | ||
| 808 | /* reset DMA module */ | 808 | /* reset DMA module */ |
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c index ccbd94adc668..c6483bad8a26 100644 --- a/arch/arm/plat-mxc/gpio.c +++ b/arch/arm/plat-mxc/gpio.c | |||
| @@ -200,8 +200,8 @@ static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |||
| 200 | static int mxc_gpio_direction_output(struct gpio_chip *chip, | 200 | static int mxc_gpio_direction_output(struct gpio_chip *chip, |
| 201 | unsigned offset, int value) | 201 | unsigned offset, int value) |
| 202 | { | 202 | { |
| 203 | _set_gpio_direction(chip, offset, 1); | ||
| 204 | mxc_gpio_set(chip, offset, value); | 203 | mxc_gpio_set(chip, offset, value); |
| 204 | _set_gpio_direction(chip, offset, 1); | ||
| 205 | return 0; | 205 | return 0; |
| 206 | } | 206 | } |
| 207 | 207 | ||
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h index 8f34a05afc87..1cac9d1135cd 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h +++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h | |||
| @@ -48,7 +48,8 @@ | |||
| 48 | * Base address of PBC controller, CS4 | 48 | * Base address of PBC controller, CS4 |
| 49 | */ | 49 | */ |
| 50 | #define PBC_BASE_ADDRESS 0xEB000000 | 50 | #define PBC_BASE_ADDRESS 0xEB000000 |
| 51 | #define PBC_REG_ADDR(offset) (PBC_BASE_ADDRESS + (offset)) | 51 | #define PBC_REG_ADDR(offset) (void __force __iomem *) \ |
| 52 | (PBC_BASE_ADDRESS + (offset)) | ||
| 52 | 53 | ||
| 53 | /* | 54 | /* |
| 54 | * PBC Interupt name definitions | 55 | * PBC Interupt name definitions |
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h index 451d510d08c3..318c72ada13d 100644 --- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h +++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h | |||
| @@ -11,6 +11,8 @@ | |||
| 11 | #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ | 11 | #ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__ |
| 12 | #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ | 12 | #define __ASM_ARCH_MXC_BOARD_MX31ADS_H__ |
| 13 | 13 | ||
| 14 | #include <mach/hardware.h> | ||
| 15 | |||
| 14 | /* Base address of PBC controller */ | 16 | /* Base address of PBC controller */ |
| 15 | #define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) | 17 | #define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR) |
| 16 | /* Offsets for the PBC Controller register */ | 18 | /* Offsets for the PBC Controller register */ |
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h new file mode 100644 index 000000000000..f8aef1babb75 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ | ||
| 20 | #define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ | ||
| 21 | |||
| 22 | /* mandatory for CONFIG_LL_DEBUG */ | ||
| 23 | |||
| 24 | #define MXC_LL_UART_PADDR UART1_BASE_ADDR | ||
| 25 | #define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000) | ||
| 26 | |||
| 27 | #ifndef __ASSEMBLY__ | ||
| 28 | |||
| 29 | enum mx31moboard_boards { | ||
| 30 | MX31NOBOARD = 0, | ||
| 31 | MX31DEVBOARD = 1, | ||
| 32 | MX31MARXBOT = 2, | ||
| 33 | }; | ||
| 34 | |||
| 35 | /* | ||
| 36 | * This CPU module needs a baseboard to work. After basic initializing | ||
| 37 | * its own devices, it calls baseboard's init function. | ||
| 38 | */ | ||
| 39 | |||
| 40 | extern void mx31moboard_devboard_init(void); | ||
| 41 | extern void mx31moboard_marxbot_init(void); | ||
| 42 | |||
| 43 | #endif | ||
| 44 | |||
| 45 | #endif /* __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h new file mode 100644 index 000000000000..4ff762dd45cf --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/board-qong.h | |||
| @@ -0,0 +1,22 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MXC_BOARD_QONG_H__ | ||
| 12 | #define __ASM_ARCH_MXC_BOARD_QONG_H__ | ||
| 13 | |||
| 14 | /* mandatory for CONFIG_LL_DEBUG */ | ||
| 15 | |||
| 16 | #define MXC_LL_UART_PADDR UART1_BASE_ADDR | ||
| 17 | #define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) | ||
| 18 | |||
| 19 | /* NOR FLASH */ | ||
| 20 | #define QONG_NOR_SIZE (128*1024*1024) | ||
| 21 | |||
| 22 | #endif /* __ASM_ARCH_MXC_BOARD_QONG_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/clkdev.h b/arch/arm/plat-mxc/include/mach/clkdev.h new file mode 100644 index 000000000000..04b37a89801c --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/clkdev.h | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | #ifndef __ASM_MACH_CLKDEV_H | ||
| 2 | #define __ASM_MACH_CLKDEV_H | ||
| 3 | |||
| 4 | #define __clk_get(clk) ({ 1; }) | ||
| 5 | #define __clk_put(clk) do { } while (0) | ||
| 6 | |||
| 7 | #endif | ||
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h index d21f78e78819..43a82d0c534d 100644 --- a/arch/arm/plat-mxc/include/mach/clock.h +++ b/arch/arm/plat-mxc/include/mach/clock.h | |||
| @@ -26,9 +26,13 @@ | |||
| 26 | struct module; | 26 | struct module; |
| 27 | 27 | ||
| 28 | struct clk { | 28 | struct clk { |
| 29 | #ifndef CONFIG_COMMON_CLKDEV | ||
| 30 | /* As soon as i.MX1 and i.MX31 switched to clkdev, this | ||
| 31 | * block can go away */ | ||
| 29 | struct list_head node; | 32 | struct list_head node; |
| 30 | struct module *owner; | 33 | struct module *owner; |
| 31 | const char *name; | 34 | const char *name; |
| 35 | #endif | ||
| 32 | int id; | 36 | int id; |
| 33 | /* Source clock this clk depends on */ | 37 | /* Source clock this clk depends on */ |
| 34 | struct clk *parent; | 38 | struct clk *parent; |
| @@ -63,5 +67,7 @@ struct clk { | |||
| 63 | int clk_register(struct clk *clk); | 67 | int clk_register(struct clk *clk); |
| 64 | void clk_unregister(struct clk *clk); | 68 | void clk_unregister(struct clk *clk); |
| 65 | 69 | ||
| 70 | unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref); | ||
| 71 | |||
| 66 | #endif /* __ASSEMBLY__ */ | 72 | #endif /* __ASSEMBLY__ */ |
| 67 | #endif /* __ASM_ARCH_MXC_CLOCK_H__ */ | 73 | #endif /* __ASM_ARCH_MXC_CLOCK_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 6350287a59b9..b2f9b72644db 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h | |||
| @@ -12,12 +12,18 @@ | |||
| 12 | #define __ASM_ARCH_MXC_COMMON_H__ | 12 | #define __ASM_ARCH_MXC_COMMON_H__ |
| 13 | 13 | ||
| 14 | struct platform_device; | 14 | struct platform_device; |
| 15 | struct clk; | ||
| 15 | 16 | ||
| 16 | extern void mxc_map_io(void); | 17 | extern void mxc_map_io(void); |
| 17 | extern void mxc_init_irq(void); | 18 | extern void mxc_init_irq(void); |
| 18 | extern void mxc_timer_init(const char *clk_timer); | 19 | extern void mxc_timer_init(struct clk *timer_clk); |
| 19 | extern int mxc_clocks_init(unsigned long fref); | 20 | extern int mx1_clocks_init(unsigned long fref); |
| 21 | extern int mx21_clocks_init(unsigned long lref, unsigned long fref); | ||
| 22 | extern int mx27_clocks_init(unsigned long fref); | ||
| 23 | extern int mx31_clocks_init(unsigned long fref); | ||
| 24 | extern int mx35_clocks_init(void); | ||
| 20 | extern int mxc_register_gpios(void); | 25 | extern int mxc_register_gpios(void); |
| 21 | extern int mxc_register_device(struct platform_device *pdev, void *data); | 26 | extern int mxc_register_device(struct platform_device *pdev, void *data); |
| 27 | extern void mxc_set_cpu_type(unsigned int type); | ||
| 22 | 28 | ||
| 23 | #endif | 29 | #endif |
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S index 602768b427e2..4f773148bc20 100644 --- a/arch/arm/plat-mxc/include/mach/debug-macro.S +++ b/arch/arm/plat-mxc/include/mach/debug-macro.S | |||
| @@ -31,6 +31,9 @@ | |||
| 31 | #ifdef CONFIG_MACH_MX31_3DS | 31 | #ifdef CONFIG_MACH_MX31_3DS |
| 32 | #include <mach/board-mx31pdk.h> | 32 | #include <mach/board-mx31pdk.h> |
| 33 | #endif | 33 | #endif |
| 34 | #ifdef CONFIG_MACH_QONG | ||
| 35 | #include <mach/board-qong.h> | ||
| 36 | #endif | ||
| 34 | .macro addruart,rx | 37 | .macro addruart,rx |
| 35 | mrc p15, 0, \rx, c1, c0 | 38 | mrc p15, 0, \rx, c1, c0 |
| 36 | tst \rx, #1 @ MMU enabled? | 39 | tst \rx, #1 @ MMU enabled? |
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index a612d8bb73c8..42e4ee37ca1f 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h | |||
| @@ -23,10 +23,16 @@ | |||
| 23 | #include <asm/sizes.h> | 23 | #include <asm/sizes.h> |
| 24 | 24 | ||
| 25 | #ifdef CONFIG_ARCH_MX3 | 25 | #ifdef CONFIG_ARCH_MX3 |
| 26 | # include <mach/mx31.h> | 26 | #include <mach/mx3x.h> |
| 27 | #include <mach/mx31.h> | ||
| 28 | #include <mach/mx35.h> | ||
| 27 | #endif | 29 | #endif |
| 28 | 30 | ||
| 29 | #ifdef CONFIG_ARCH_MX2 | 31 | #ifdef CONFIG_ARCH_MX2 |
| 32 | # include <mach/mx2x.h> | ||
| 33 | # ifdef CONFIG_MACH_MX21 | ||
| 34 | # include <mach/mx21.h> | ||
| 35 | # endif | ||
| 30 | # ifdef CONFIG_MACH_MX27 | 36 | # ifdef CONFIG_MACH_MX27 |
| 31 | # include <mach/mx27.h> | 37 | # include <mach/mx27.h> |
| 32 | # endif | 38 | # endif |
diff --git a/arch/arm/mach-imx/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h index 870d0d939616..762a7b0430e2 100644 --- a/arch/arm/mach-imx/include/mach/imxfb.h +++ b/arch/arm/plat-mxc/include/mach/imxfb.h | |||
| @@ -76,6 +76,9 @@ struct imx_fb_platform_data { | |||
| 76 | u_char * fixed_screen_cpu; | 76 | u_char * fixed_screen_cpu; |
| 77 | dma_addr_t fixed_screen_dma; | 77 | dma_addr_t fixed_screen_dma; |
| 78 | 78 | ||
| 79 | int (*init)(struct platform_device*); | ||
| 80 | int (*exit)(struct platform_device*); | ||
| 81 | |||
| 79 | void (*lcd_power)(int); | 82 | void (*lcd_power)(int); |
| 80 | void (*backlight_power)(int); | 83 | void (*backlight_power)(int); |
| 81 | }; | 84 | }; |
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h deleted file mode 100644 index 95a383be628e..000000000000 --- a/arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h +++ /dev/null | |||
| @@ -1,416 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef _MXC_GPIO_MX1_MX2_H | ||
| 20 | #define _MXC_GPIO_MX1_MX2_H | ||
| 21 | |||
| 22 | #include <linux/io.h> | ||
| 23 | |||
| 24 | /* | ||
| 25 | * GPIO Module and I/O Multiplexer | ||
| 26 | * x = 0..3 for reg_A, reg_B, reg_C, reg_D | ||
| 27 | */ | ||
| 28 | #define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR) | ||
| 29 | #define MXC_DDIR(x) (0x00 + ((x) << 8)) | ||
| 30 | #define MXC_OCR1(x) (0x04 + ((x) << 8)) | ||
| 31 | #define MXC_OCR2(x) (0x08 + ((x) << 8)) | ||
| 32 | #define MXC_ICONFA1(x) (0x0c + ((x) << 8)) | ||
| 33 | #define MXC_ICONFA2(x) (0x10 + ((x) << 8)) | ||
| 34 | #define MXC_ICONFB1(x) (0x14 + ((x) << 8)) | ||
| 35 | #define MXC_ICONFB2(x) (0x18 + ((x) << 8)) | ||
| 36 | #define MXC_DR(x) (0x1c + ((x) << 8)) | ||
| 37 | #define MXC_GIUS(x) (0x20 + ((x) << 8)) | ||
| 38 | #define MXC_SSR(x) (0x24 + ((x) << 8)) | ||
| 39 | #define MXC_ICR1(x) (0x28 + ((x) << 8)) | ||
| 40 | #define MXC_ICR2(x) (0x2c + ((x) << 8)) | ||
| 41 | #define MXC_IMR(x) (0x30 + ((x) << 8)) | ||
| 42 | #define MXC_ISR(x) (0x34 + ((x) << 8)) | ||
| 43 | #define MXC_GPR(x) (0x38 + ((x) << 8)) | ||
| 44 | #define MXC_SWR(x) (0x3c + ((x) << 8)) | ||
| 45 | #define MXC_PUEN(x) (0x40 + ((x) << 8)) | ||
| 46 | |||
| 47 | #ifdef CONFIG_ARCH_MX1 | ||
| 48 | # define GPIO_PORT_MAX 3 | ||
| 49 | #endif | ||
| 50 | #ifdef CONFIG_ARCH_MX2 | ||
| 51 | # define GPIO_PORT_MAX 5 | ||
| 52 | #endif | ||
| 53 | |||
| 54 | #ifndef GPIO_PORT_MAX | ||
| 55 | # error "GPIO config port count unknown!" | ||
| 56 | #endif | ||
| 57 | |||
| 58 | #define GPIO_PIN_MASK 0x1f | ||
| 59 | |||
| 60 | #define GPIO_PORT_SHIFT 5 | ||
| 61 | #define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) | ||
| 62 | |||
| 63 | #define GPIO_PORTA (0 << GPIO_PORT_SHIFT) | ||
| 64 | #define GPIO_PORTB (1 << GPIO_PORT_SHIFT) | ||
| 65 | #define GPIO_PORTC (2 << GPIO_PORT_SHIFT) | ||
| 66 | #define GPIO_PORTD (3 << GPIO_PORT_SHIFT) | ||
| 67 | #define GPIO_PORTE (4 << GPIO_PORT_SHIFT) | ||
| 68 | #define GPIO_PORTF (5 << GPIO_PORT_SHIFT) | ||
| 69 | |||
| 70 | #define GPIO_OUT (1 << 8) | ||
| 71 | #define GPIO_IN (0 << 8) | ||
| 72 | #define GPIO_PUEN (1 << 9) | ||
| 73 | |||
| 74 | #define GPIO_PF (1 << 10) | ||
| 75 | #define GPIO_AF (1 << 11) | ||
| 76 | |||
| 77 | #define GPIO_OCR_SHIFT 12 | ||
| 78 | #define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) | ||
| 79 | #define GPIO_AIN (0 << GPIO_OCR_SHIFT) | ||
| 80 | #define GPIO_BIN (1 << GPIO_OCR_SHIFT) | ||
| 81 | #define GPIO_CIN (2 << GPIO_OCR_SHIFT) | ||
| 82 | #define GPIO_GPIO (3 << GPIO_OCR_SHIFT) | ||
| 83 | |||
| 84 | #define GPIO_AOUT_SHIFT 14 | ||
| 85 | #define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) | ||
| 86 | #define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) | ||
| 87 | #define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) | ||
| 88 | #define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) | ||
| 89 | #define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) | ||
| 90 | |||
| 91 | #define GPIO_BOUT_SHIFT 16 | ||
| 92 | #define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) | ||
| 93 | #define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) | ||
| 94 | #define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) | ||
| 95 | #define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) | ||
| 96 | #define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) | ||
| 97 | |||
| 98 | extern void mxc_gpio_mode(int gpio_mode); | ||
| 99 | extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, | ||
| 100 | const char *label); | ||
| 101 | extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); | ||
| 102 | |||
| 103 | /*-------------------------------------------------------------------------*/ | ||
| 104 | |||
| 105 | /* assignements for GPIO alternate/primary functions */ | ||
| 106 | |||
| 107 | /* FIXME: This list is not completed. The correct directions are | ||
| 108 | * missing on some (many) pins | ||
| 109 | */ | ||
| 110 | #ifdef CONFIG_ARCH_MX1 | ||
| 111 | #define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_OUT | 0) | ||
| 112 | #define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0) | ||
| 113 | #define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_IN | 1) | ||
| 114 | #define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1) | ||
| 115 | #define PA2_PF_PWM0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2) | ||
| 116 | #define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3) | ||
| 117 | #define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4) | ||
| 118 | #define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5) | ||
| 119 | #define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6) | ||
| 120 | #define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7) | ||
| 121 | #define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8) | ||
| 122 | #define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9) | ||
| 123 | #define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10) | ||
| 124 | #define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11) | ||
| 125 | #define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12) | ||
| 126 | #define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13) | ||
| 127 | #define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14) | ||
| 128 | #define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15) | ||
| 129 | #define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16) | ||
| 130 | #define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17) | ||
| 131 | #define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_OUT | 17) | ||
| 132 | #define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18) | ||
| 133 | #define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19) | ||
| 134 | #define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20) | ||
| 135 | #define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21) | ||
| 136 | #define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22) | ||
| 137 | #define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23) | ||
| 138 | #define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24) | ||
| 139 | #define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24) | ||
| 140 | #define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25) | ||
| 141 | #define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25) | ||
| 142 | #define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26) | ||
| 143 | #define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26) | ||
| 144 | #define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27) | ||
| 145 | #define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27) | ||
| 146 | #define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28) | ||
| 147 | #define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28) | ||
| 148 | #define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29) | ||
| 149 | #define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29) | ||
| 150 | #define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30) | ||
| 151 | #define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30) | ||
| 152 | #define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31) | ||
| 153 | #define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31) | ||
| 154 | #define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8) | ||
| 155 | #define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8) | ||
| 156 | #define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9) | ||
| 157 | #define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9) | ||
| 158 | #define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10) | ||
| 159 | #define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10) | ||
| 160 | #define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11) | ||
| 161 | #define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11) | ||
| 162 | #define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12) | ||
| 163 | #define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12) | ||
| 164 | #define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13) | ||
| 165 | #define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13) | ||
| 166 | #define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14) | ||
| 167 | #define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15) | ||
| 168 | #define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_IN | GPIO_AF | 16) | ||
| 169 | #define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_OUT | GPIO_AF | 17) | ||
| 170 | #define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18) | ||
| 171 | #define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19) | ||
| 172 | #define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20) | ||
| 173 | #define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21) | ||
| 174 | #define PB22_PFUSBD_RCV (GPIO_PORTB | GPIO_PF | 22) | ||
| 175 | #define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23) | ||
| 176 | #define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24) | ||
| 177 | #define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25) | ||
| 178 | #define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26) | ||
| 179 | #define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27) | ||
| 180 | #define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_OUT | GPIO_PF | 28) | ||
| 181 | #define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 29) | ||
| 182 | #define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_OUT | GPIO_PF | 30) | ||
| 183 | #define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_IN | GPIO_PF | 31) | ||
| 184 | #define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3) | ||
| 185 | #define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4) | ||
| 186 | #define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_IN | GPIO_PF | 5) | ||
| 187 | #define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6) | ||
| 188 | #define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7) | ||
| 189 | #define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8) | ||
| 190 | #define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) | ||
| 191 | #define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_IN | GPIO_PF | 10) | ||
| 192 | #define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) | ||
| 193 | #define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 12) | ||
| 194 | #define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13) | ||
| 195 | #define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14) | ||
| 196 | #define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15) | ||
| 197 | #define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16) | ||
| 198 | #define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17) | ||
| 199 | #define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24) | ||
| 200 | #define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25) | ||
| 201 | #define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_IN | 26) | ||
| 202 | #define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27) | ||
| 203 | #define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28) | ||
| 204 | #define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_IN | 29) | ||
| 205 | #define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30) | ||
| 206 | #define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_IN | 31) | ||
| 207 | #define PD6_PF_LSCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6) | ||
| 208 | #define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7) | ||
| 209 | #define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_IN | GPIO_AF | 7) | ||
| 210 | #define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7) | ||
| 211 | #define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8) | ||
| 212 | #define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8) | ||
| 213 | #define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8) | ||
| 214 | #define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9) | ||
| 215 | #define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9) | ||
| 216 | #define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_IN | 9) | ||
| 217 | #define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10) | ||
| 218 | #define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10) | ||
| 219 | #define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_OUT | 10) | ||
| 220 | #define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11) | ||
| 221 | #define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12) | ||
| 222 | #define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13) | ||
| 223 | #define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 14) | ||
| 224 | #define PD15_PF_LD0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 15) | ||
| 225 | #define PD16_PF_LD1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 16) | ||
| 226 | #define PD17_PF_LD2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) | ||
| 227 | #define PD18_PF_LD3 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) | ||
| 228 | #define PD19_PF_LD4 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 19) | ||
| 229 | #define PD20_PF_LD5 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 20) | ||
| 230 | #define PD21_PF_LD6 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 21) | ||
| 231 | #define PD22_PF_LD7 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 22) | ||
| 232 | #define PD23_PF_LD8 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 23) | ||
| 233 | #define PD24_PF_LD9 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 24) | ||
| 234 | #define PD25_PF_LD10 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25) | ||
| 235 | #define PD26_PF_LD11 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26) | ||
| 236 | #define PD27_PF_LD12 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27) | ||
| 237 | #define PD28_PF_LD13 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28) | ||
| 238 | #define PD29_PF_LD14 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29) | ||
| 239 | #define PD30_PF_LD15 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30) | ||
| 240 | #define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31) | ||
| 241 | #define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31) | ||
| 242 | #endif | ||
| 243 | |||
| 244 | #ifdef CONFIG_ARCH_MX2 | ||
| 245 | #define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) | ||
| 246 | #define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) | ||
| 247 | #define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) | ||
| 248 | #define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) | ||
| 249 | #define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) | ||
| 250 | #define PA5_PF_LSCLK (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5) | ||
| 251 | #define PA6_PF_LD0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6) | ||
| 252 | #define PA7_PF_LD1 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7) | ||
| 253 | #define PA8_PF_LD2 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 8) | ||
| 254 | #define PA9_PF_LD3 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 9) | ||
| 255 | #define PA10_PF_LD4 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 10) | ||
| 256 | #define PA11_PF_LD5 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 11) | ||
| 257 | #define PA12_PF_LD6 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 12) | ||
| 258 | #define PA13_PF_LD7 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 13) | ||
| 259 | #define PA14_PF_LD8 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 14) | ||
| 260 | #define PA15_PF_LD9 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15) | ||
| 261 | #define PA16_PF_LD10 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16) | ||
| 262 | #define PA17_PF_LD11 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 17) | ||
| 263 | #define PA18_PF_LD12 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 18) | ||
| 264 | #define PA19_PF_LD13 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 19) | ||
| 265 | #define PA20_PF_LD14 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 20) | ||
| 266 | #define PA21_PF_LD15 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 21) | ||
| 267 | #define PA22_PF_LD16 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 22) | ||
| 268 | #define PA23_PF_LD17 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 23) | ||
| 269 | #define PA24_PF_REV (GPIO_PORTA | GPIO_OUT | GPIO_PF | 24) | ||
| 270 | #define PA25_PF_CLS (GPIO_PORTA | GPIO_OUT | GPIO_PF | 25) | ||
| 271 | #define PA26_PF_PS (GPIO_PORTA | GPIO_OUT | GPIO_PF | 26) | ||
| 272 | #define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_OUT | GPIO_PF | 27) | ||
| 273 | #define PA28_PF_HSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 28) | ||
| 274 | #define PA29_PF_VSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29) | ||
| 275 | #define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30) | ||
| 276 | #define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31) | ||
| 277 | #define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) | ||
| 278 | #define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) | ||
| 279 | #define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) | ||
| 280 | #define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) | ||
| 281 | #define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) | ||
| 282 | #define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) | ||
| 283 | #define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10) | ||
| 284 | #define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10) | ||
| 285 | #define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11) | ||
| 286 | #define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 11) | ||
| 287 | #define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 12) | ||
| 288 | #define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 12) | ||
| 289 | #define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 13) | ||
| 290 | #define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 13) | ||
| 291 | #define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 14) | ||
| 292 | #define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_OUT | GPIO_PF | 15) | ||
| 293 | #define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_OUT | GPIO_PF | 16) | ||
| 294 | #define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 17) | ||
| 295 | #define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 18) | ||
| 296 | #define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 18) | ||
| 297 | #define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 19) | ||
| 298 | #define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 19) | ||
| 299 | #define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 20) | ||
| 300 | #define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20) | ||
| 301 | #define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21) | ||
| 302 | #define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 21) | ||
| 303 | #define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) | ||
| 304 | #define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23) | ||
| 305 | #define PB24_PF_USB_OC_B (GPIO_PORTB | GPIO_PF | 24) | ||
| 306 | #define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) | ||
| 307 | #define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26) | ||
| 308 | #define PB27_PF_USBH1_OE_B (GPIO_PORTB | GPIO_PF | 27) | ||
| 309 | #define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28) | ||
| 310 | #define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29) | ||
| 311 | #define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30) | ||
| 312 | #define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31) | ||
| 313 | #define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 26) | ||
| 314 | #define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28) | ||
| 315 | #define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29) | ||
| 316 | #define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 31) | ||
| 317 | #define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_IN | GPIO_PF | 5) | ||
| 318 | #define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_IN | GPIO_PF | 6) | ||
| 319 | #define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7) | ||
| 320 | #define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8) | ||
| 321 | #define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) | ||
| 322 | #define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10) | ||
| 323 | #define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) | ||
| 324 | #define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12) | ||
| 325 | #define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13) | ||
| 326 | #define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 16) | ||
| 327 | #define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 17) | ||
| 328 | #define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 18) | ||
| 329 | #define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 19) | ||
| 330 | #define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 20) | ||
| 331 | #define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 21) | ||
| 332 | #define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 22) | ||
| 333 | #define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 23) | ||
| 334 | #define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 24) | ||
| 335 | #define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 25) | ||
| 336 | #define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 26) | ||
| 337 | #define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 27) | ||
| 338 | #define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 28) | ||
| 339 | #define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 29) | ||
| 340 | #define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 30) | ||
| 341 | #define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 31) | ||
| 342 | #define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0) | ||
| 343 | #define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1) | ||
| 344 | #define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2) | ||
| 345 | #define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3) | ||
| 346 | #define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4) | ||
| 347 | #define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5) | ||
| 348 | #define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6) | ||
| 349 | #define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7) | ||
| 350 | #define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8) | ||
| 351 | #define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9) | ||
| 352 | #define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10) | ||
| 353 | #define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11) | ||
| 354 | #define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12) | ||
| 355 | #define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13) | ||
| 356 | #define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14) | ||
| 357 | #define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15) | ||
| 358 | #define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16) | ||
| 359 | #define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) | ||
| 360 | #define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) | ||
| 361 | #define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) | ||
| 362 | #define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) | ||
| 363 | #define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) | ||
| 364 | #define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) | ||
| 365 | #define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) | ||
| 366 | #define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) | ||
| 367 | #define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25) | ||
| 368 | #define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26) | ||
| 369 | #define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) | ||
| 370 | #define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27) | ||
| 371 | #define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28) | ||
| 372 | #define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29) | ||
| 373 | #define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_IN | GPIO_PF | 30) | ||
| 374 | #define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_OUT | GPIO_PF | 31) | ||
| 375 | #define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) | ||
| 376 | #define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0) | ||
| 377 | #define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1) | ||
| 378 | #define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2) | ||
| 379 | #define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) | ||
| 380 | #define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) | ||
| 381 | #define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) | ||
| 382 | #define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7) | ||
| 383 | #define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8) | ||
| 384 | #define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9) | ||
| 385 | #define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10) | ||
| 386 | #define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11) | ||
| 387 | #define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) | ||
| 388 | #define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) | ||
| 389 | #define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) | ||
| 390 | #define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) | ||
| 391 | #define PE16_AF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 16) | ||
| 392 | #define PE16_PF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 16) | ||
| 393 | #define PE18_PF_SDHC1_D0 (GPIO_PORTE | GPIO_PF | 18) | ||
| 394 | #define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_IN | GPIO_AF | 18) | ||
| 395 | #define PE19_PF_SDHC1_D1 (GPIO_PORTE | GPIO_PF | 19) | ||
| 396 | #define PE20_PF_SDHC1_D2 (GPIO_PORTE | GPIO_PF | 20) | ||
| 397 | #define PE21_PF_SDHC1_D3 (GPIO_PORTE | GPIO_PF | 21) | ||
| 398 | #define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21) | ||
| 399 | #define PE22_PF_SDHC1_CMD (GPIO_PORTE | GPIO_PF | 22) | ||
| 400 | #define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22) | ||
| 401 | #define PE22_PF_SDHC1_CLK (GPIO_PORTE | GPIO_PF | 23) | ||
| 402 | #define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23) | ||
| 403 | #define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24) | ||
| 404 | #define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25) | ||
| 405 | #endif | ||
| 406 | |||
| 407 | /* decode irq number to use with IMR(x), ISR(x) and friends */ | ||
| 408 | #define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5) | ||
| 409 | |||
| 410 | #define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x) | ||
| 411 | #define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) | ||
| 412 | #define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) | ||
| 413 | #define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) | ||
| 414 | #define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x) | ||
| 415 | |||
| 416 | #endif /* _MXC_GPIO_MX1_MX2_H */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx1.h b/arch/arm/plat-mxc/include/mach/iomux-mx1.h new file mode 100644 index 000000000000..bf23305c19cc --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx1.h | |||
| @@ -0,0 +1,166 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef _MXC_IOMUX_MX1_H | ||
| 20 | #define _MXC_IOMUX_MX1_H | ||
| 21 | |||
| 22 | #ifndef GPIO_PORTA | ||
| 23 | #error Please include mach/iomux.h | ||
| 24 | #endif | ||
| 25 | |||
| 26 | /* FIXME: This list is not completed. The correct directions are | ||
| 27 | * missing on some (many) pins | ||
| 28 | */ | ||
| 29 | |||
| 30 | |||
| 31 | /* Primary GPIO pin functions */ | ||
| 32 | |||
| 33 | #define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) | ||
| 34 | #define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0) | ||
| 35 | #define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 1) | ||
| 36 | #define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1) | ||
| 37 | #define PA2_PF_PWM0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 2) | ||
| 38 | #define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3) | ||
| 39 | #define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4) | ||
| 40 | #define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5) | ||
| 41 | #define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6) | ||
| 42 | #define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7) | ||
| 43 | #define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8) | ||
| 44 | #define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9) | ||
| 45 | #define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10) | ||
| 46 | #define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11) | ||
| 47 | #define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12) | ||
| 48 | #define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13) | ||
| 49 | #define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14) | ||
| 50 | #define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) | ||
| 51 | #define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) | ||
| 52 | #define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17) | ||
| 53 | #define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) | ||
| 54 | #define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18) | ||
| 55 | #define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19) | ||
| 56 | #define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20) | ||
| 57 | #define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21) | ||
| 58 | #define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22) | ||
| 59 | #define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23) | ||
| 60 | #define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24) | ||
| 61 | #define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24) | ||
| 62 | #define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25) | ||
| 63 | #define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25) | ||
| 64 | #define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26) | ||
| 65 | #define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26) | ||
| 66 | #define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27) | ||
| 67 | #define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27) | ||
| 68 | #define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28) | ||
| 69 | #define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28) | ||
| 70 | #define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29) | ||
| 71 | #define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29) | ||
| 72 | #define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30) | ||
| 73 | #define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30) | ||
| 74 | #define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31) | ||
| 75 | #define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31) | ||
| 76 | #define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8) | ||
| 77 | #define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8) | ||
| 78 | #define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9) | ||
| 79 | #define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9) | ||
| 80 | #define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10) | ||
| 81 | #define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10) | ||
| 82 | #define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11) | ||
| 83 | #define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11) | ||
| 84 | #define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12) | ||
| 85 | #define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12) | ||
| 86 | #define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13) | ||
| 87 | #define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13) | ||
| 88 | #define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14) | ||
| 89 | #define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15) | ||
| 90 | #define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_AF | GPIO_IN | 16) | ||
| 91 | #define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_AF | GPIO_OUT | 17) | ||
| 92 | #define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18) | ||
| 93 | #define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19) | ||
| 94 | #define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20) | ||
| 95 | #define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21) | ||
| 96 | #define PB22_PF_USBD_RCV (GPIO_PORTB | GPIO_PF | 22) | ||
| 97 | #define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23) | ||
| 98 | #define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24) | ||
| 99 | #define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25) | ||
| 100 | #define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26) | ||
| 101 | #define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27) | ||
| 102 | #define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_PF | GPIO_OUT | 28) | ||
| 103 | #define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_PF | GPIO_IN | 29) | ||
| 104 | #define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_PF | GPIO_OUT | 30) | ||
| 105 | #define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_PF | GPIO_IN | 31) | ||
| 106 | #define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3) | ||
| 107 | #define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4) | ||
| 108 | #define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) | ||
| 109 | #define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_PF | GPIO_OUT | 6) | ||
| 110 | #define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7) | ||
| 111 | #define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8) | ||
| 112 | #define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) | ||
| 113 | #define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_PF | GPIO_IN | 10) | ||
| 114 | #define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) | ||
| 115 | #define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 12) | ||
| 116 | #define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13) | ||
| 117 | #define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14) | ||
| 118 | #define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15) | ||
| 119 | #define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16) | ||
| 120 | #define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17) | ||
| 121 | #define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 24) | ||
| 122 | #define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 25) | ||
| 123 | #define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 26) | ||
| 124 | #define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 27) | ||
| 125 | #define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 28) | ||
| 126 | #define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 29) | ||
| 127 | #define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30) | ||
| 128 | #define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 31) | ||
| 129 | #define PD6_PF_LSCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 6) | ||
| 130 | #define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7) | ||
| 131 | #define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_AF | GPIO_IN | 7) | ||
| 132 | #define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7) | ||
| 133 | #define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8) | ||
| 134 | #define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_AF | GPIO_OUT | 8) | ||
| 135 | #define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8) | ||
| 136 | #define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9) | ||
| 137 | #define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_AF | GPIO_OUT | 9) | ||
| 138 | #define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 9) | ||
| 139 | #define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_PF | GPIO_OUT | 10) | ||
| 140 | #define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_AF | GPIO_OUT | 10) | ||
| 141 | #define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 10) | ||
| 142 | #define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_PF | GPIO_OUT | 11) | ||
| 143 | #define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_PF | GPIO_OUT | 12) | ||
| 144 | #define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 13) | ||
| 145 | #define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_PF | GPIO_OUT | 14) | ||
| 146 | #define PD15_PF_LD0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 15) | ||
| 147 | #define PD16_PF_LD1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 16) | ||
| 148 | #define PD17_PF_LD2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) | ||
| 149 | #define PD18_PF_LD3 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) | ||
| 150 | #define PD19_PF_LD4 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 19) | ||
| 151 | #define PD20_PF_LD5 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 20) | ||
| 152 | #define PD21_PF_LD6 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 21) | ||
| 153 | #define PD22_PF_LD7 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 22) | ||
| 154 | #define PD23_PF_LD8 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 23) | ||
| 155 | #define PD24_PF_LD9 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 24) | ||
| 156 | #define PD25_PF_LD10 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) | ||
| 157 | #define PD26_PF_LD11 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) | ||
| 158 | #define PD27_PF_LD12 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) | ||
| 159 | #define PD28_PF_LD13 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) | ||
| 160 | #define PD29_PF_LD14 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) | ||
| 161 | #define PD30_PF_LD15 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 30) | ||
| 162 | #define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31) | ||
| 163 | #define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31) | ||
| 164 | |||
| 165 | |||
| 166 | #endif | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx21.h b/arch/arm/plat-mxc/include/mach/iomux-mx21.h new file mode 100644 index 000000000000..63aaa972e275 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx21.h | |||
| @@ -0,0 +1,126 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or | ||
| 5 | * modify it under the terms of the GNU General Public License | ||
| 6 | * as published by the Free Software Foundation; either version 2 | ||
| 7 | * of the License, or (at your option) any later version. | ||
| 8 | * This program is distributed in the hope that it will be useful, | ||
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 11 | * GNU General Public License for more details. | ||
| 12 | * | ||
| 13 | * You should have received a copy of the GNU General Public License | ||
| 14 | * along with this program; if not, write to the Free Software | ||
| 15 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 16 | * MA 02110-1301, USA. | ||
| 17 | */ | ||
| 18 | |||
| 19 | #ifndef _MXC_IOMUX_MX21_H | ||
| 20 | #define _MXC_IOMUX_MX21_H | ||
| 21 | |||
| 22 | #ifndef GPIO_PORTA | ||
| 23 | #error Please include mach/iomux.h | ||
| 24 | #endif | ||
| 25 | |||
| 26 | |||
| 27 | /* Primary GPIO pin functions */ | ||
| 28 | |||
| 29 | #define PB22_PF_USBH1_BYP (GPIO_PORTB | GPIO_PF | 22) | ||
| 30 | #define PB25_PF_USBH1_ON (GPIO_PORTB | GPIO_PF | 25) | ||
| 31 | #define PC5_PF_USBOTG_SDA (GPIO_PORTC | GPIO_PF | 5) | ||
| 32 | #define PC6_PF_USBOTG_SCL (GPIO_PORTC | GPIO_PF | 6) | ||
| 33 | #define PC7_PF_USBOTG_ON (GPIO_PORTC | GPIO_PF | 7) | ||
| 34 | #define PC8_PF_USBOTG_FS (GPIO_PORTC | GPIO_PF | 8) | ||
| 35 | #define PC9_PF_USBOTG_OE (GPIO_PORTC | GPIO_PF | 9) | ||
| 36 | #define PC10_PF_USBOTG_TXDM (GPIO_PORTC | GPIO_PF | 10) | ||
| 37 | #define PC11_PF_USBOTG_TXDP (GPIO_PORTC | GPIO_PF | 11) | ||
| 38 | #define PC12_PF_USBOTG_RXDM (GPIO_PORTC | GPIO_PF | 12) | ||
| 39 | #define PC13_PF_USBOTG_RXDP (GPIO_PORTC | GPIO_PF | 13) | ||
| 40 | #define PC16_PF_SAP_FS (GPIO_PORTC | GPIO_PF | 16) | ||
| 41 | #define PC17_PF_SAP_RXD (GPIO_PORTC | GPIO_PF | 17) | ||
| 42 | #define PC18_PF_SAP_TXD (GPIO_PORTC | GPIO_PF | 18) | ||
| 43 | #define PC19_PF_SAP_CLK (GPIO_PORTC | GPIO_PF | 19) | ||
| 44 | #define PE0_PF_TEST_WB2 (GPIO_PORTE | GPIO_PF | 0) | ||
| 45 | #define PE1_PF_TEST_WB1 (GPIO_PORTE | GPIO_PF | 1) | ||
| 46 | #define PE2_PF_TEST_WB0 (GPIO_PORTE | GPIO_PF | 2) | ||
| 47 | #define PF1_PF_NFCE (GPIO_PORTF | GPIO_PF | 1) | ||
| 48 | #define PF3_PF_NFCLE (GPIO_PORTF | GPIO_PF | 3) | ||
| 49 | #define PF7_PF_NFIO0 (GPIO_PORTF | GPIO_PF | 7) | ||
| 50 | #define PF8_PF_NFIO1 (GPIO_PORTF | GPIO_PF | 8) | ||
| 51 | #define PF9_PF_NFIO2 (GPIO_PORTF | GPIO_PF | 9) | ||
| 52 | #define PF10_PF_NFIO3 (GPIO_PORTF | GPIO_PF | 10) | ||
| 53 | #define PF11_PF_NFIO4 (GPIO_PORTF | GPIO_PF | 11) | ||
| 54 | #define PF12_PF_NFIO5 (GPIO_PORTF | GPIO_PF | 12) | ||
| 55 | #define PF13_PF_NFIO6 (GPIO_PORTF | GPIO_PF | 13) | ||
| 56 | #define PF14_PF_NFIO7 (GPIO_PORTF | GPIO_PF | 14) | ||
| 57 | #define PF16_PF_RES (GPIO_PORTF | GPIO_PF | 16) | ||
| 58 | |||
| 59 | /* Alternate GPIO pin functions */ | ||
| 60 | |||
| 61 | #define PA5_AF_BMI_CLK_CS (GPIO_PORTA | GPIO_AF | 5) | ||
| 62 | #define PA6_AF_BMI_D0 (GPIO_PORTA | GPIO_AF | 6) | ||
| 63 | #define PA7_AF_BMI_D1 (GPIO_PORTA | GPIO_AF | 7) | ||
| 64 | #define PA8_AF_BMI_D2 (GPIO_PORTA | GPIO_AF | 8) | ||
| 65 | #define PA9_AF_BMI_D3 (GPIO_PORTA | GPIO_AF | 9) | ||
| 66 | #define PA10_AF_BMI_D4 (GPIO_PORTA | GPIO_AF | 10) | ||
| 67 | #define PA11_AF_BMI_D5 (GPIO_PORTA | GPIO_AF | 11) | ||
| 68 | #define PA12_AF_BMI_D6 (GPIO_PORTA | GPIO_AF | 12) | ||
| 69 | #define PA13_AF_BMI_D7 (GPIO_PORTA | GPIO_AF | 13) | ||
| 70 | #define PA14_AF_BMI_D8 (GPIO_PORTA | GPIO_AF | 14) | ||
| 71 | #define PA15_AF_BMI_D9 (GPIO_PORTA | GPIO_AF | 15) | ||
| 72 | #define PA16_AF_BMI_D10 (GPIO_PORTA | GPIO_AF | 16) | ||
| 73 | #define PA17_AF_BMI_D11 (GPIO_PORTA | GPIO_AF | 17) | ||
| 74 | #define PA18_AF_BMI_D12 (GPIO_PORTA | GPIO_AF | 18) | ||
| 75 | #define PA19_AF_BMI_D13 (GPIO_PORTA | GPIO_AF | 19) | ||
| 76 | #define PA20_AF_BMI_D14 (GPIO_PORTA | GPIO_AF | 20) | ||
| 77 | #define PA21_AF_BMI_D15 (GPIO_PORTA | GPIO_AF | 21) | ||
| 78 | #define PA22_AF_BMI_READ_REQ (GPIO_PORTA | GPIO_AF | 22) | ||
| 79 | #define PA23_AF_BMI_WRITE (GPIO_PORTA | GPIO_AF | 23) | ||
| 80 | #define PA29_AF_BMI_RX_FULL (GPIO_PORTA | GPIO_AF | 29) | ||
| 81 | #define PA30_AF_BMI_READ (GPIO_PORTA | GPIO_AF | 30) | ||
| 82 | |||
| 83 | /* AIN GPIO pin functions */ | ||
| 84 | |||
| 85 | #define PC14_AIN_SYS_CLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) | ||
| 86 | #define PD21_AIN_USBH2_FS (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 21) | ||
| 87 | #define PD22_AIN_USBH2_OE (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 22) | ||
| 88 | #define PD23_AIN_USBH2_TXDM (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 23) | ||
| 89 | #define PD24_AIN_USBH2_TXDP (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 24) | ||
| 90 | #define PE8_AIN_IR_TXD (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 8) | ||
| 91 | #define PF0_AIN_PC_RST (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 0) | ||
| 92 | #define PF1_AIN_PC_CE1 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 1) | ||
| 93 | #define PF2_AIN_PC_CE2 (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 2) | ||
| 94 | #define PF3_AIN_PC_POE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 3) | ||
| 95 | #define PF4_AIN_PC_OE (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 4) | ||
| 96 | #define PF5_AIN_PC_RW (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 5) | ||
| 97 | |||
| 98 | /* BIN GPIO pin functions */ | ||
| 99 | |||
| 100 | #define PC14_BIN_SYS_CLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) | ||
| 101 | #define PD27_BIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_BIN | GPIO_OUT | 27) | ||
| 102 | |||
| 103 | /* CIN GPIO pin functions */ | ||
| 104 | |||
| 105 | #define PB26_CIN_USBH1_RXDAT (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 26) | ||
| 106 | |||
| 107 | /* AOUT GPIO pin functions */ | ||
| 108 | |||
| 109 | #define PA29_AOUT_BMI_WAIT (GPIO_PORTA | GPIO_AOUT | GPIO_IN | 29) | ||
| 110 | #define PD19_AOUT_USBH2_RXDM (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 19) | ||
| 111 | #define PD20_AOUT_USBH2_RXDP (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 20) | ||
| 112 | #define PD25_AOUT_EXT_DMAREQ (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 25) | ||
| 113 | #define PD26_AOUT_USBOTG_RXDAT (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 26) | ||
| 114 | #define PE9_AOUT_IR_RXD (GPIO_PORTE | GPIO_AOUT | GPIO_IN | 9) | ||
| 115 | #define PF6_AOUT_PC_BVD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 6) | ||
| 116 | #define PF7_AOUT_PC_BVD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 7) | ||
| 117 | #define PF8_AOUT_PC_VS2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 8) | ||
| 118 | #define PF9_AOUT_PC_VS1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 9) | ||
| 119 | #define PF10_AOUT_PC_WP (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 10) | ||
| 120 | #define PF11_AOUT_PC_READY (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 11) | ||
| 121 | #define PF12_AOUT_PC_WAIT (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 12) | ||
| 122 | #define PF13_AOUT_PC_CD2 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 13) | ||
| 123 | #define PF14_AOUT_PC_CD1 (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 14) | ||
| 124 | |||
| 125 | |||
| 126 | #endif | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx27.h b/arch/arm/plat-mxc/include/mach/iomux-mx27.h new file mode 100644 index 000000000000..5ac158b70f61 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx27.h | |||
| @@ -0,0 +1,207 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
| 3 | * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef _MXC_IOMUX_MX27_H | ||
| 21 | #define _MXC_IOMUX_MX27_H | ||
| 22 | |||
| 23 | #ifndef GPIO_PORTA | ||
| 24 | #error Please include mach/iomux.h | ||
| 25 | #endif | ||
| 26 | |||
| 27 | |||
| 28 | /* Primary GPIO pin functions */ | ||
| 29 | |||
| 30 | #define PA0_PF_USBH2_CLK (GPIO_PORTA | GPIO_PF | 0) | ||
| 31 | #define PA1_PF_USBH2_DIR (GPIO_PORTA | GPIO_PF | 1) | ||
| 32 | #define PA2_PF_USBH2_DATA7 (GPIO_PORTA | GPIO_PF | 2) | ||
| 33 | #define PA3_PF_USBH2_NXT (GPIO_PORTA | GPIO_PF | 3) | ||
| 34 | #define PA4_PF_USBH2_STP (GPIO_PORTA | GPIO_PF | 4) | ||
| 35 | #define PB22_PF_USBH1_SUSP (GPIO_PORTB | GPIO_PF | 22) | ||
| 36 | #define PB25_PF_USBH1_RCV (GPIO_PORTB | GPIO_PF | 25) | ||
| 37 | #define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_PF | GPIO_IN | 5) | ||
| 38 | #define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_PF | GPIO_IN | 6) | ||
| 39 | #define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 7) | ||
| 40 | #define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 8) | ||
| 41 | #define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 9) | ||
| 42 | #define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 10) | ||
| 43 | #define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 11) | ||
| 44 | #define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 12) | ||
| 45 | #define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_PF | GPIO_OUT | 13) | ||
| 46 | #define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 16) | ||
| 47 | #define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 17) | ||
| 48 | #define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 18) | ||
| 49 | #define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 19) | ||
| 50 | #define PC25_AF_GPT5_TIN (GPIO_PORTC | GPIO_AF | 25) | ||
| 51 | #define PC27_AF_GPT4_TIN (GPIO_PORTC | GPIO_AF | 27) | ||
| 52 | #define PD0_PF_SD3_CMD (GPIO_PORTD | GPIO_PF | 0) | ||
| 53 | #define PD1_PF_SD3_CLK (GPIO_PORTD | GPIO_PF | 1) | ||
| 54 | #define PD2_PF_ATA_DATA0 (GPIO_PORTD | GPIO_PF | 2) | ||
| 55 | #define PD3_PF_ATA_DATA1 (GPIO_PORTD | GPIO_PF | 3) | ||
| 56 | #define PD4_PF_ATA_DATA2 (GPIO_PORTD | GPIO_PF | 4) | ||
| 57 | #define PD5_PF_ATA_DATA3 (GPIO_PORTD | GPIO_PF | 5) | ||
| 58 | #define PD6_PF_ATA_DATA4 (GPIO_PORTD | GPIO_PF | 6) | ||
| 59 | #define PD7_PF_ATA_DATA5 (GPIO_PORTD | GPIO_PF | 7) | ||
| 60 | #define PD8_PF_ATA_DATA6 (GPIO_PORTD | GPIO_PF | 8) | ||
| 61 | #define PD9_PF_ATA_DATA7 (GPIO_PORTD | GPIO_PF | 9) | ||
| 62 | #define PD10_PF_ATA_DATA8 (GPIO_PORTD | GPIO_PF | 10) | ||
| 63 | #define PD11_PF_ATA_DATA9 (GPIO_PORTD | GPIO_PF | 11) | ||
| 64 | #define PD12_PF_ATA_DATA10 (GPIO_PORTD | GPIO_PF | 12) | ||
| 65 | #define PD13_PF_ATA_DATA11 (GPIO_PORTD | GPIO_PF | 13) | ||
| 66 | #define PD14_PF_ATA_DATA12 (GPIO_PORTD | GPIO_PF | 14) | ||
| 67 | #define PD15_PF_ATA_DATA13 (GPIO_PORTD | GPIO_PF | 15) | ||
| 68 | #define PD16_PF_ATA_DATA14 (GPIO_PORTD | GPIO_PF | 16) | ||
| 69 | #define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_PF | GPIO_OUT | 0) | ||
| 70 | #define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_PF | GPIO_OUT | 1) | ||
| 71 | #define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_PF | GPIO_OUT | 2) | ||
| 72 | #define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 24) | ||
| 73 | #define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_PF | GPIO_OUT | 25) | ||
| 74 | #define PF1_PF_NFCLE (GPIO_PORTF | GPIO_PF | 1) | ||
| 75 | #define PF3_PF_NFCE (GPIO_PORTF | GPIO_PF | 3) | ||
| 76 | #define PF7_PF_PC_POE (GPIO_PORTF | GPIO_PF | 7) | ||
| 77 | #define PF8_PF_PC_RW (GPIO_PORTF | GPIO_PF | 8) | ||
| 78 | #define PF9_PF_PC_IOIS16 (GPIO_PORTF | GPIO_PF | 9) | ||
| 79 | #define PF10_PF_PC_RST (GPIO_PORTF | GPIO_PF | 10) | ||
| 80 | #define PF11_PF_PC_BVD2 (GPIO_PORTF | GPIO_PF | 11) | ||
| 81 | #define PF12_PF_PC_BVD1 (GPIO_PORTF | GPIO_PF | 12) | ||
| 82 | #define PF13_PF_PC_VS2 (GPIO_PORTF | GPIO_PF | 13) | ||
| 83 | #define PF14_PF_PC_VS1 (GPIO_PORTF | GPIO_PF | 14) | ||
| 84 | #define PF16_PF_PC_PWRON (GPIO_PORTF | GPIO_PF | 16) | ||
| 85 | #define PF17_PF_PC_READY (GPIO_PORTF | GPIO_PF | 17) | ||
| 86 | #define PF18_PF_PC_WAIT (GPIO_PORTF | GPIO_PF | 18) | ||
| 87 | #define PF19_PF_PC_CD2 (GPIO_PORTF | GPIO_PF | 19) | ||
| 88 | #define PF20_PF_PC_CD1 (GPIO_PORTF | GPIO_PF | 20) | ||
| 89 | #define PF23_PF_ATA_DATA15 (GPIO_PORTF | GPIO_PF | 23) | ||
| 90 | |||
| 91 | /* Alternate GPIO pin functions */ | ||
| 92 | |||
| 93 | #define PB4_AF_MSHC_DATA0 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 4) | ||
| 94 | #define PB5_AF_MSHC_DATA1 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 5) | ||
| 95 | #define PB6_AF_MSHC_DATA2 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 6) | ||
| 96 | #define PB7_AF_MSHC_DATA4 (GPIO_PORTB | GPIO_AF | GPIO_OUT | 7) | ||
| 97 | #define PB8_AF_MSHC_BS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 8) | ||
| 98 | #define PB9_AF_MSHC_SCLK (GPIO_PORTB | GPIO_AF | GPIO_OUT | 9) | ||
| 99 | #define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 10) | ||
| 100 | #define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 11) | ||
| 101 | #define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 12) | ||
| 102 | #define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 13) | ||
| 103 | #define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 18) | ||
| 104 | #define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 19) | ||
| 105 | #define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 20) | ||
| 106 | #define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 21) | ||
| 107 | #define PC8_AF_FEC_MDIO (GPIO_PORTC | GPIO_AF | GPIO_IN | 8) | ||
| 108 | #define PC24_AF_GPT5_TOUT (GPIO_PORTC | GPIO_AF | 24) | ||
| 109 | #define PC26_AF_GPT4_TOUT (GPIO_PORTC | GPIO_AF | 26) | ||
| 110 | #define PD1_AF_ETMTRACE_PKT15 (GPIO_PORTD | GPIO_AF | 1) | ||
| 111 | #define PD6_AF_ETMTRACE_PKT14 (GPIO_PORTD | GPIO_AF | 6) | ||
| 112 | #define PD7_AF_ETMTRACE_PKT13 (GPIO_PORTD | GPIO_AF | 7) | ||
| 113 | #define PD9_AF_ETMTRACE_PKT12 (GPIO_PORTD | GPIO_AF | 9) | ||
| 114 | #define PD2_AF_SD3_D0 (GPIO_PORTD | GPIO_AF | 2) | ||
| 115 | #define PD3_AF_SD3_D1 (GPIO_PORTD | GPIO_AF | 3) | ||
| 116 | #define PD4_AF_SD3_D2 (GPIO_PORTD | GPIO_AF | 4) | ||
| 117 | #define PD5_AF_SD3_D3 (GPIO_PORTD | GPIO_AF | 5) | ||
| 118 | #define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_AF | GPIO_IN | 8) | ||
| 119 | #define PD10_AF_ETMTRACE_PKT11 (GPIO_PORTD | GPIO_AF | 10) | ||
| 120 | #define PD11_AF_ETMTRACE_PKT10 (GPIO_PORTD | GPIO_AF | 11) | ||
| 121 | #define PD12_AF_ETMTRACE_PKT9 (GPIO_PORTD | GPIO_AF | 12) | ||
| 122 | #define PD13_AF_ETMTRACE_PKT8 (GPIO_PORTD | GPIO_AF | 13) | ||
| 123 | #define PD14_AF_ETMTRACE_PKT7 (GPIO_PORTD | GPIO_AF | 14) | ||
| 124 | #define PD15_AF_ETMTRACE_PKT6 (GPIO_PORTD | GPIO_AF | 15) | ||
| 125 | #define PD16_AF_ETMTRACE_PKT5 (GPIO_PORTD | GPIO_AF | 16) | ||
| 126 | #define PF1_AF_ETMTRACE_PKT0 (GPIO_PORTF | GPIO_AF | 1) | ||
| 127 | #define PF3_AF_ETMTRACE_PKT2 (GPIO_PORTF | GPIO_AF | 3) | ||
| 128 | #define PF5_AF_ETMPIPESTAT11 (GPIO_PORTF | GPIO_AF | 5) | ||
| 129 | #define PF7_AF_ATA_BUFFER_EN (GPIO_PORTF | GPIO_AF | 7) | ||
| 130 | #define PF8_AF_ATA_IORDY (GPIO_PORTF | GPIO_AF | 8) | ||
| 131 | #define PF9_AF_ATA_INTRQ (GPIO_PORTF | GPIO_AF | 9) | ||
| 132 | #define PF10_AF_ATA_RESET (GPIO_PORTF | GPIO_AF | 10) | ||
| 133 | #define PF11_AF_ATA_DMACK (GPIO_PORTF | GPIO_AF | 11) | ||
| 134 | #define PF12_AF_ATA_DMAREQ (GPIO_PORTF | GPIO_AF | 12) | ||
| 135 | #define PF13_AF_ATA_DA0 (GPIO_PORTF | GPIO_AF | 13) | ||
| 136 | #define PF14_AF_ATA_DA1 (GPIO_PORTF | GPIO_AF | 14) | ||
| 137 | #define PF15_AF_ETMTRACE_SYNC (GPIO_PORTF | GPIO_AF | 15) | ||
| 138 | #define PF16_AF_ATA_DA2 (GPIO_PORTF | GPIO_AF | 16) | ||
| 139 | #define PF17_AF_ATA_CS0 (GPIO_PORTF | GPIO_AF | 17) | ||
| 140 | #define PF18_AF_ATA_CS1 (GPIO_PORTF | GPIO_AF | 18) | ||
| 141 | #define PF19_AF_ATA_DIOW (GPIO_PORTF | GPIO_AF | 19) | ||
| 142 | #define PF20_AF_ATA_DIOR (GPIO_PORTF | GPIO_AF | 20) | ||
| 143 | #define PF22_AF_ETMTRACE_CLK (GPIO_PORTF | GPIO_AF | 22) | ||
| 144 | #define PF23_AF_ETMTRACE_PKT4 (GPIO_PORTF | GPIO_AF | 23) | ||
| 145 | |||
| 146 | /* AIN GPIO pin functions */ | ||
| 147 | |||
| 148 | #define PC14_AIN_SSI1_MCLK (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 14) | ||
| 149 | #define PC15_AIN_GPT6_TOUT (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 15) | ||
| 150 | #define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 0) | ||
| 151 | #define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 1) | ||
| 152 | #define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 2) | ||
| 153 | #define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 3) | ||
| 154 | #define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 9) | ||
| 155 | #define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 16) | ||
| 156 | #define PD27_AIN_EXT_DMA_GRANT (GPIO_PORTD | GPIO_AIN | GPIO_OUT | 27) | ||
| 157 | #define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_AIN | GPIO_OUT | 23) | ||
| 158 | |||
| 159 | /* BIN GPIO pin functions */ | ||
| 160 | |||
| 161 | #define PC14_BIN_SSI2_MCLK (GPIO_PORTC | GPIO_BIN | GPIO_OUT | 14) | ||
| 162 | |||
| 163 | /* CIN GPIO pin functions */ | ||
| 164 | |||
| 165 | #define PD2_CIN_SLCDC1_DAT0 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 2) | ||
| 166 | #define PD3_CIN_SLCDC1_DAT1 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 3) | ||
| 167 | #define PD4_CIN_SLCDC1_DAT2 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 4) | ||
| 168 | #define PD5_CIN_SLCDC1_DAT3 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 5) | ||
| 169 | #define PD6_CIN_SLCDC1_DAT4 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 6) | ||
| 170 | #define PD7_CIN_SLCDC1_DAT5 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 7) | ||
| 171 | #define PD8_CIN_SLCDC1_DAT6 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 8) | ||
| 172 | #define PD9_CIN_SLCDC1_DAT7 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 9) | ||
| 173 | #define PD10_CIN_SLCDC1_DAT8 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 10) | ||
| 174 | #define PD11_CIN_SLCDC1_DAT9 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 11) | ||
| 175 | #define PD12_CIN_SLCDC1_DAT10 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 12) | ||
| 176 | #define PD13_CIN_SLCDC1_DAT11 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 13) | ||
| 177 | #define PD14_CIN_SLCDC1_DAT12 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 14) | ||
| 178 | #define PD15_CIN_SLCDC1_DAT13 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 15) | ||
| 179 | #define PD16_CIN_SLCDC1_DAT14 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 16) | ||
| 180 | #define PD23_CIN_SLCDC1_DAT15 (GPIO_PORTD | GPIO_CIN | GPIO_OUT | 23) | ||
| 181 | #define PF27_CIN_EXT_DMA_GRANT (GPIO_PORTF | GPIO_CIN | GPIO_OUT | 27) | ||
| 182 | /* LCDC_TESTx on PBxx omitted, because it's not clear what they do */ | ||
| 183 | |||
| 184 | /* AOUT GPIO pin functions */ | ||
| 185 | |||
| 186 | #define PC14_AOUT_GPT6_TIN (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 14) | ||
| 187 | #define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 4) | ||
| 188 | #define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 5) | ||
| 189 | #define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 6) | ||
| 190 | #define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 7) | ||
| 191 | #define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 10) | ||
| 192 | #define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 11) | ||
| 193 | #define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 12) | ||
| 194 | #define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 13) | ||
| 195 | #define PD14_AOUT_FEC_RX_CLK (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 14) | ||
| 196 | #define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_AOUT | GPIO_IN | 15) | ||
| 197 | |||
| 198 | #define PC17_BOUT_PC_IOIS16 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 17) | ||
| 199 | #define PC18_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 18) | ||
| 200 | #define PC19_BOUT_PC_BVD1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 19) | ||
| 201 | #define PC28_BOUT_PC_BVD2 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 28) | ||
| 202 | #define PC29_BOUT_PC_VS1 (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 29) | ||
| 203 | #define PC30_BOUT_PC_READY (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 30) | ||
| 204 | #define PC31_BOUT_PC_WAIT (GPIO_PORTC | GPIO_BOUT | GPIO_IN | 31) | ||
| 205 | |||
| 206 | |||
| 207 | #endif /* _MXC_GPIO_MX1_MX2_H */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx2x.h b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h new file mode 100644 index 000000000000..fb5ae638e79f --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux-mx2x.h | |||
| @@ -0,0 +1,237 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
| 3 | * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef _MXC_IOMUX_MX2x_H | ||
| 21 | #define _MXC_IOMUX_MX2x_H | ||
| 22 | |||
| 23 | #ifndef GPIO_PORTA | ||
| 24 | #error Please include mach/iomux.h | ||
| 25 | #endif | ||
| 26 | |||
| 27 | |||
| 28 | /* Primary GPIO pin functions */ | ||
| 29 | |||
| 30 | #define PA5_PF_LSCLK (GPIO_PORTA | GPIO_PF | GPIO_OUT | 5) | ||
| 31 | #define PA6_PF_LD0 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 6) | ||
| 32 | #define PA7_PF_LD1 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 7) | ||
| 33 | #define PA8_PF_LD2 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 8) | ||
| 34 | #define PA9_PF_LD3 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 9) | ||
| 35 | #define PA10_PF_LD4 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 10) | ||
| 36 | #define PA11_PF_LD5 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 11) | ||
| 37 | #define PA12_PF_LD6 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 12) | ||
| 38 | #define PA13_PF_LD7 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 13) | ||
| 39 | #define PA14_PF_LD8 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 14) | ||
| 40 | #define PA15_PF_LD9 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 15) | ||
| 41 | #define PA16_PF_LD10 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 16) | ||
| 42 | #define PA17_PF_LD11 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 17) | ||
| 43 | #define PA18_PF_LD12 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 18) | ||
| 44 | #define PA19_PF_LD13 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 19) | ||
| 45 | #define PA20_PF_LD14 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 20) | ||
| 46 | #define PA21_PF_LD15 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 21) | ||
| 47 | #define PA22_PF_LD16 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 22) | ||
| 48 | #define PA23_PF_LD17 (GPIO_PORTA | GPIO_PF | GPIO_OUT | 23) | ||
| 49 | #define PA24_PF_REV (GPIO_PORTA | GPIO_PF | GPIO_OUT | 24) | ||
| 50 | #define PA25_PF_CLS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 25) | ||
| 51 | #define PA26_PF_PS (GPIO_PORTA | GPIO_PF | GPIO_OUT | 26) | ||
| 52 | #define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_PF | GPIO_OUT | 27) | ||
| 53 | #define PA28_PF_HSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 28) | ||
| 54 | #define PA29_PF_VSYNC (GPIO_PORTA | GPIO_PF | GPIO_OUT | 29) | ||
| 55 | #define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_PF | GPIO_OUT | 30) | ||
| 56 | #define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_PF | GPIO_OUT | 31) | ||
| 57 | #define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) | ||
| 58 | #define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) | ||
| 59 | #define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) | ||
| 60 | #define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) | ||
| 61 | #define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) | ||
| 62 | #define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) | ||
| 63 | #define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 10) | ||
| 64 | #define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 11) | ||
| 65 | #define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 12) | ||
| 66 | #define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 13) | ||
| 67 | #define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 14) | ||
| 68 | #define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 15) | ||
| 69 | #define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_PF | GPIO_OUT | 16) | ||
| 70 | #define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 17) | ||
| 71 | #define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 18) | ||
| 72 | #define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_PF | GPIO_OUT | 19) | ||
| 73 | #define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 20) | ||
| 74 | #define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_PF | GPIO_OUT | 21) | ||
| 75 | #define PB23_PF_USB_PWR (GPIO_PORTB | GPIO_PF | 23) | ||
| 76 | #define PB24_PF_USB_OC (GPIO_PORTB | GPIO_PF | 24) | ||
| 77 | #define PB26_PF_USBH1_FS (GPIO_PORTB | GPIO_PF | 26) | ||
| 78 | #define PB27_PF_USBH1_OE (GPIO_PORTB | GPIO_PF | 27) | ||
| 79 | #define PB28_PF_USBH1_TXDM (GPIO_PORTB | GPIO_PF | 28) | ||
| 80 | #define PB29_PF_USBH1_TXDP (GPIO_PORTB | GPIO_PF | 29) | ||
| 81 | #define PB30_PF_USBH1_RXDM (GPIO_PORTB | GPIO_PF | 30) | ||
| 82 | #define PB31_PF_USBH1_RXDP (GPIO_PORTB | GPIO_PF | 31) | ||
| 83 | #define PC14_PF_TOUT (GPIO_PORTC | GPIO_PF | 14) | ||
| 84 | #define PC15_PF_TIN (GPIO_PORTC | GPIO_PF | 15) | ||
| 85 | #define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 20) | ||
| 86 | #define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 21) | ||
| 87 | #define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 22) | ||
| 88 | #define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 23) | ||
| 89 | #define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 24) | ||
| 90 | #define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 25) | ||
| 91 | #define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 26) | ||
| 92 | #define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 27) | ||
| 93 | #define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_PF | GPIO_IN | 28) | ||
| 94 | #define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 29) | ||
| 95 | #define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_PF | GPIO_IN | 30) | ||
| 96 | #define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_PF | GPIO_IN | 31) | ||
| 97 | #define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_PF | GPIO_OUT | 17) | ||
| 98 | #define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 18) | ||
| 99 | #define PD19_PF_CSPI2_SS2 (GPIO_PORTD | GPIO_PF | 19) | ||
| 100 | #define PD20_PF_CSPI2_SS1 (GPIO_PORTD | GPIO_PF | 20) | ||
| 101 | #define PD21_PF_CSPI2_SS0 (GPIO_PORTD | GPIO_PF | 21) | ||
| 102 | #define PD22_PF_CSPI2_SCLK (GPIO_PORTD | GPIO_PF | 22) | ||
| 103 | #define PD23_PF_CSPI2_MISO (GPIO_PORTD | GPIO_PF | 23) | ||
| 104 | #define PD24_PF_CSPI2_MOSI (GPIO_PORTD | GPIO_PF | 24) | ||
| 105 | #define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_PF | GPIO_OUT | 25) | ||
| 106 | #define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 26) | ||
| 107 | #define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 27) | ||
| 108 | #define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_PF | GPIO_OUT | 28) | ||
| 109 | #define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_PF | GPIO_OUT | 29) | ||
| 110 | #define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_PF | GPIO_IN | 30) | ||
| 111 | #define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_PF | GPIO_OUT | 31) | ||
| 112 | #define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 3) | ||
| 113 | #define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 4) | ||
| 114 | #define PE5_PF_PWMO (GPIO_PORTE | GPIO_PF | 5) | ||
| 115 | #define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 6) | ||
| 116 | #define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 7) | ||
| 117 | #define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 8) | ||
| 118 | #define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 9) | ||
| 119 | #define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 10) | ||
| 120 | #define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 11) | ||
| 121 | #define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_PF | GPIO_OUT | 12) | ||
| 122 | #define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_PF | GPIO_IN | 13) | ||
| 123 | #define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_PF | GPIO_OUT | 14) | ||
| 124 | #define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_PF | GPIO_IN | 15) | ||
| 125 | #define PE16_PF_RTCK (GPIO_PORTE | GPIO_PF | GPIO_OUT | 16) | ||
| 126 | #define PE17_PF_RESET_OUT (GPIO_PORTE | GPIO_PF | 17) | ||
| 127 | #define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) | ||
| 128 | #define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) | ||
| 129 | #define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) | ||
| 130 | #define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) | ||
| 131 | #define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) | ||
| 132 | #define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) | ||
| 133 | #define PF0_PF_NRFB (GPIO_PORTF | GPIO_PF | 0) | ||
| 134 | #define PF2_PF_NFWP (GPIO_PORTF | GPIO_PF | 2) | ||
| 135 | #define PF4_PF_NFALE (GPIO_PORTF | GPIO_PF | 4) | ||
| 136 | #define PF5_PF_NFRE (GPIO_PORTF | GPIO_PF | 5) | ||
| 137 | #define PF6_PF_NFWE (GPIO_PORTF | GPIO_PF | 6) | ||
| 138 | #define PF15_PF_CLKO (GPIO_PORTF | GPIO_PF | 15) | ||
| 139 | #define PF21_PF_CS4 (GPIO_PORTF | GPIO_PF | 21) | ||
| 140 | #define PF22_PF_CS5 (GPIO_PORTF | GPIO_PF | 22) | ||
| 141 | |||
| 142 | /* Alternate GPIO pin functions */ | ||
| 143 | |||
| 144 | #define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_AF | GPIO_IN | 26) | ||
| 145 | #define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_AF | GPIO_OUT | 28) | ||
| 146 | #define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_AF | GPIO_OUT | 29) | ||
| 147 | #define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_AF | GPIO_IN | 31) | ||
| 148 | #define PC28_AF_SLCDC2_D0 (GPIO_PORTC | GPIO_AF | 28) | ||
| 149 | #define PC29_AF_SLCDC2_RS (GPIO_PORTC | GPIO_AF | 29) | ||
| 150 | #define PC30_AF_SLCDC2_CS (GPIO_PORTC | GPIO_AF | 30) | ||
| 151 | #define PC31_AF_SLCDC2_CLK (GPIO_PORTC | GPIO_AF | 31) | ||
| 152 | #define PD19_AF_USBH2_DATA4 (GPIO_PORTD | GPIO_AF | 19) | ||
| 153 | #define PD20_AF_USBH2_DATA3 (GPIO_PORTD | GPIO_AF | 20) | ||
| 154 | #define PD21_AF_USBH2_DATA6 (GPIO_PORTD | GPIO_AF | 21) | ||
| 155 | #define PD22_AF_USBH2_DATA0 (GPIO_PORTD | GPIO_AF | 22) | ||
| 156 | #define PD23_AF_USBH2_DATA2 (GPIO_PORTD | GPIO_AF | 23) | ||
| 157 | #define PD24_AF_USBH2_DATA1 (GPIO_PORTD | GPIO_AF | 24) | ||
| 158 | #define PD26_AF_USBH2_DATA5 (GPIO_PORTD | GPIO_AF | 26) | ||
| 159 | #define PE0_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 0) | ||
| 160 | #define PE1_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 1) | ||
| 161 | #define PE2_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 2) | ||
| 162 | #define PE3_AF_KP_COL7 (GPIO_PORTE | GPIO_AF | 3) | ||
| 163 | #define PE4_AF_KP_ROW7 (GPIO_PORTE | GPIO_AF | 4) | ||
| 164 | #define PE6_AF_KP_COL6 (GPIO_PORTE | GPIO_AF | 6) | ||
| 165 | #define PE7_AF_KP_ROW6 (GPIO_PORTE | GPIO_AF | 7) | ||
| 166 | #define PE16_AF_OWIRE (GPIO_PORTE | GPIO_AF | 16) | ||
| 167 | #define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_AF | GPIO_IN | 18) | ||
| 168 | #define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_AF | GPIO_OUT | 21) | ||
| 169 | #define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_AF | GPIO_OUT | 22) | ||
| 170 | #define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_AF | GPIO_OUT | 23) | ||
| 171 | |||
| 172 | /* AIN GPIO pin functions */ | ||
| 173 | |||
| 174 | #define PA6_AIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 6) | ||
| 175 | #define PA7_AIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 7) | ||
| 176 | #define PA8_AIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 8) | ||
| 177 | #define PA0_AIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 0) | ||
| 178 | #define PA11_AIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 11) | ||
| 179 | #define PA13_AIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 13) | ||
| 180 | #define PA15_AIN_SLCDC1_DAT9 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 15) | ||
| 181 | #define PA17_AIN_SLCDC1_DAT11 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 17) | ||
| 182 | #define PA19_AIN_SLCDC1_DAT13 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 19) | ||
| 183 | #define PA21_AIN_SLCDC1_DAT15 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 21) | ||
| 184 | #define PA22_AIN_EXT_DMAGRANT (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 22) | ||
| 185 | #define PA24_AIN_SLCDC1_D0 (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 24) | ||
| 186 | #define PA25_AIN_SLCDC1_RS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 25) | ||
| 187 | #define PA26_AIN_SLCDC1_CS (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 26) | ||
| 188 | #define PA27_AIN_SLCDC1_CLK (GPIO_PORTA | GPIO_AIN | GPIO_OUT | 27) | ||
| 189 | #define PB6_AIN_SLCDC1_D0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 6) | ||
| 190 | #define PB7_AIN_SLCDC1_RS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 7) | ||
| 191 | #define PB8_AIN_SLCDC1_CS (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 8) | ||
| 192 | #define PB9_AIN_SLCDC1_CLK (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 9) | ||
| 193 | #define PB25_AIN_SLCDC1_DAT0 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 25) | ||
| 194 | #define PB26_AIN_SLCDC1_DAT1 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 26) | ||
| 195 | #define PB27_AIN_SLCDC1_DAT2 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 27) | ||
| 196 | #define PB28_AIN_SLCDC1_DAT3 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 28) | ||
| 197 | #define PB29_AIN_SLCDC1_DAT4 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 29) | ||
| 198 | #define PB30_AIN_SLCDC1_DAT5 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 30) | ||
| 199 | #define PB31_AIN_SLCDC1_DAT6 (GPIO_PORTB | GPIO_AIN | GPIO_OUT | 31) | ||
| 200 | #define PC5_AIN_SLCDC1_DAT7 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 5) | ||
| 201 | #define PC6_AIN_SLCDC1_DAT8 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 6) | ||
| 202 | #define PC7_AIN_SLCDC1_DAT9 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 7) | ||
| 203 | #define PC8_AIN_SLCDC1_DAT10 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 8) | ||
| 204 | #define PC9_AIN_SLCDC1_DAT11 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 9) | ||
| 205 | #define PC10_AIN_SLCDC1_DAT12 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 10) | ||
| 206 | #define PC11_AIN_SLCDC1_DAT13 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 11) | ||
| 207 | #define PC12_AIN_SLCDC1_DAT14 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 12) | ||
| 208 | #define PC13_AIN_SLCDC1_DAT15 (GPIO_PORTC | GPIO_AIN | GPIO_OUT | 13) | ||
| 209 | #define PE5_AIN_PC_SPKOUT (GPIO_PORTE | GPIO_AIN | GPIO_OUT | 5) | ||
| 210 | |||
| 211 | /* BIN GPIO pin functions */ | ||
| 212 | |||
| 213 | #define PE5_BIN_TOUT2 (GPIO_PORTE | GPIO_BIN | GPIO_OUT | 5) | ||
| 214 | |||
| 215 | /* CIN GPIO pin functions */ | ||
| 216 | |||
| 217 | #define PA14_CIN_SLCDC1_DAT0 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 14) | ||
| 218 | #define PA15_CIN_SLCDC1_DAT1 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 15) | ||
| 219 | #define PA16_CIN_SLCDC1_DAT2 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 16) | ||
| 220 | #define PA17_CIN_SLCDC1_DAT3 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 17) | ||
| 221 | #define PA18_CIN_SLCDC1_DAT4 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 18) | ||
| 222 | #define PA19_CIN_SLCDC1_DAT5 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 19) | ||
| 223 | #define PA20_CIN_SLCDC1_DAT6 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 20) | ||
| 224 | #define PA21_CIN_SLCDC1_DAT7 (GPIO_PORTA | GPIO_CIN | GPIO_OUT | 21) | ||
| 225 | #define PB30_CIN_UART4_CTS (GPIO_PORTB | GPIO_CIN | GPIO_OUT | 30) | ||
| 226 | #define PE5_CIN_TOUT3 (GPIO_PORTE | GPIO_CIN | GPIO_OUT | 5) | ||
| 227 | |||
| 228 | /* AOUT GPIO pin functions */ | ||
| 229 | |||
| 230 | #define PB29_AOUT_UART4_RXD (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 29) | ||
| 231 | #define PB31_AOUT_UART4_RTS (GPIO_PORTB | GPIO_AOUT | GPIO_IN | 31) | ||
| 232 | #define PC8_AOUT_USBOTG_TXR_INT (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 8) | ||
| 233 | #define PC15_AOUT_WKGD (GPIO_PORTC | GPIO_AOUT | GPIO_IN | 15) | ||
| 234 | #define PF21_AOUT_DTACK (GPIO_PORTF | GPIO_AOUT | GPIO_IN | 21) | ||
| 235 | |||
| 236 | |||
| 237 | #endif | ||
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h index c9198c0aea18..ab838cfe94f9 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h | |||
| @@ -92,7 +92,7 @@ enum iomux_gp_func { | |||
| 92 | MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, | 92 | MUX_EXTDMAREQ2_MBX_SEL = 1 << 15, |
| 93 | MUX_TAMPER_DETECT_EN = 1 << 16, | 93 | MUX_TAMPER_DETECT_EN = 1 << 16, |
| 94 | MUX_PGP_USB_4WIRE = 1 << 17, | 94 | MUX_PGP_USB_4WIRE = 1 << 17, |
| 95 | MUX_PGB_USB_COMMON = 1 << 18, | 95 | MUX_PGP_USB_COMMON = 1 << 18, |
| 96 | MUX_SDHC_MEMSTICK1 = 1 << 19, | 96 | MUX_SDHC_MEMSTICK1 = 1 << 19, |
| 97 | MUX_SDHC_MEMSTICK2 = 1 << 20, | 97 | MUX_SDHC_MEMSTICK2 = 1 << 20, |
| 98 | MUX_PGP_SPLL_BYP = 1 << 21, | 98 | MUX_PGP_SPLL_BYP = 1 << 21, |
| @@ -109,21 +109,44 @@ enum iomux_gp_func { | |||
| 109 | }; | 109 | }; |
| 110 | 110 | ||
| 111 | /* | 111 | /* |
| 112 | * This function enables/disables the general purpose function for a particular | 112 | * setups a single pin: |
| 113 | * signal. | 113 | * - reserves the pin so that it is not claimed by another driver |
| 114 | * - setups the iomux according to the configuration | ||
| 115 | * - if the pin is configured as a GPIO, we claim it throug kernel gpiolib | ||
| 116 | */ | ||
| 117 | int mxc_iomux_setup_pin(const unsigned int pin, const char *label); | ||
| 118 | /* | ||
| 119 | * setups mutliple pins | ||
| 120 | * convenient way to call the above function with tables | ||
| 114 | */ | 121 | */ |
| 115 | void iomux_config_gpr(enum iomux_gp_func , bool); | 122 | int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count, |
| 123 | const char *label); | ||
| 116 | 124 | ||
| 117 | /* | 125 | /* |
| 118 | * set the mode for a IOMUX pin. | 126 | * releases a single pin: |
| 127 | * - make it available for a future use by another driver | ||
| 128 | * - frees the GPIO if the pin was configured as GPIO | ||
| 129 | * - DOES NOT reconfigure the IOMUX in its reset state | ||
| 119 | */ | 130 | */ |
| 120 | int mxc_iomux_mode(unsigned int); | 131 | void mxc_iomux_release_pin(const unsigned int pin); |
| 132 | /* | ||
| 133 | * releases multiple pins | ||
| 134 | * convenvient way to call the above function with tables | ||
| 135 | */ | ||
| 136 | void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count); | ||
| 121 | 137 | ||
| 122 | /* | 138 | /* |
| 123 | * This function enables/disables the general purpose function for a particular | 139 | * This function enables/disables the general purpose function for a particular |
| 124 | * signal. | 140 | * signal. |
| 125 | */ | 141 | */ |
| 126 | void mxc_iomux_set_gpr(enum iomux_gp_func, bool); | 142 | void mxc_iomux_set_gpr(enum iomux_gp_func, bool en); |
| 143 | |||
| 144 | /* | ||
| 145 | * This function only configures the iomux hardware. | ||
| 146 | * It is called by the setup functions and should not be called directly anymore. | ||
| 147 | * It is here visible for backward compatibility | ||
| 148 | */ | ||
| 149 | int mxc_iomux_mode(unsigned int pin_mode); | ||
| 127 | 150 | ||
| 128 | #define IOMUX_PADNUM_MASK 0x1ff | 151 | #define IOMUX_PADNUM_MASK 0x1ff |
| 129 | #define IOMUX_GPIONUM_SHIFT 9 | 152 | #define IOMUX_GPIONUM_SHIFT 9 |
| @@ -144,6 +167,11 @@ void mxc_iomux_set_gpr(enum iomux_gp_func, bool); | |||
| 144 | MXC_GPIO_IRQ_START) | 167 | MXC_GPIO_IRQ_START) |
| 145 | 168 | ||
| 146 | /* | 169 | /* |
| 170 | * The number of gpio devices among the pads | ||
| 171 | */ | ||
| 172 | #define GPIO_PORT_MAX 3 | ||
| 173 | |||
| 174 | /* | ||
| 147 | * This enumeration is constructed based on the Section | 175 | * This enumeration is constructed based on the Section |
| 148 | * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated | 176 | * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated |
| 149 | * value is constructed based on the rules described above. | 177 | * value is constructed based on the rules described above. |
| @@ -480,6 +508,9 @@ enum iomux_pins { | |||
| 480 | MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327), | 508 | MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327), |
| 481 | }; | 509 | }; |
| 482 | 510 | ||
| 511 | #define PIN_MAX 327 | ||
| 512 | #define NB_PORTS 12 /* NB_PINS/32, we chose 32 pins per "PORT" */ | ||
| 513 | |||
| 483 | /* | 514 | /* |
| 484 | * Convenience values for use with mxc_iomux_mode() | 515 | * Convenience values for use with mxc_iomux_mode() |
| 485 | * | 516 | * |
| @@ -507,7 +538,9 @@ enum iomux_pins { | |||
| 507 | #define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC) | 538 | #define MX31_PIN_CSPI1_SS1__SS1 IOMUX_MODE(MX31_PIN_CSPI1_SS1, IOMUX_CONFIG_FUNC) |
| 508 | #define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC) | 539 | #define MX31_PIN_CSPI1_SS2__SS2 IOMUX_MODE(MX31_PIN_CSPI1_SS2, IOMUX_CONFIG_FUNC) |
| 509 | #define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC) | 540 | #define MX31_PIN_CSPI2_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_FUNC) |
| 541 | #define MX31_PIN_CSPI2_MOSI__SCL IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1) | ||
| 510 | #define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC) | 542 | #define MX31_PIN_CSPI2_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_FUNC) |
| 543 | #define MX31_PIN_CSPI2_MISO__SDA IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1) | ||
| 511 | #define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC) | 544 | #define MX31_PIN_CSPI2_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI2_SCLK, IOMUX_CONFIG_FUNC) |
| 512 | #define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC) | 545 | #define MX31_PIN_CSPI2_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI2_SPI_RDY, IOMUX_CONFIG_FUNC) |
| 513 | #define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC) | 546 | #define MX31_PIN_CSPI2_SS0__SS0 IOMUX_MODE(MX31_PIN_CSPI2_SS0, IOMUX_CONFIG_FUNC) |
| @@ -525,6 +558,33 @@ enum iomux_pins { | |||
| 525 | #define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC) | 558 | #define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC) |
| 526 | #define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC) | 559 | #define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC) |
| 527 | #define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC) | 560 | #define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC) |
| 561 | #define MX31_PIN_LD0__LD0 IOMUX_MODE(MX31_PIN_LD0, IOMUX_CONFIG_FUNC) | ||
| 562 | #define MX31_PIN_LD1__LD1 IOMUX_MODE(MX31_PIN_LD1, IOMUX_CONFIG_FUNC) | ||
| 563 | #define MX31_PIN_LD2__LD2 IOMUX_MODE(MX31_PIN_LD2, IOMUX_CONFIG_FUNC) | ||
| 564 | #define MX31_PIN_LD3__LD3 IOMUX_MODE(MX31_PIN_LD3, IOMUX_CONFIG_FUNC) | ||
| 565 | #define MX31_PIN_LD4__LD4 IOMUX_MODE(MX31_PIN_LD4, IOMUX_CONFIG_FUNC) | ||
| 566 | #define MX31_PIN_LD5__LD5 IOMUX_MODE(MX31_PIN_LD5, IOMUX_CONFIG_FUNC) | ||
| 567 | #define MX31_PIN_LD6__LD6 IOMUX_MODE(MX31_PIN_LD6, IOMUX_CONFIG_FUNC) | ||
| 568 | #define MX31_PIN_LD7__LD7 IOMUX_MODE(MX31_PIN_LD7, IOMUX_CONFIG_FUNC) | ||
| 569 | #define MX31_PIN_LD8__LD8 IOMUX_MODE(MX31_PIN_LD8, IOMUX_CONFIG_FUNC) | ||
| 570 | #define MX31_PIN_LD9__LD9 IOMUX_MODE(MX31_PIN_LD9, IOMUX_CONFIG_FUNC) | ||
| 571 | #define MX31_PIN_LD10__LD10 IOMUX_MODE(MX31_PIN_LD10, IOMUX_CONFIG_FUNC) | ||
| 572 | #define MX31_PIN_LD11__LD11 IOMUX_MODE(MX31_PIN_LD11, IOMUX_CONFIG_FUNC) | ||
| 573 | #define MX31_PIN_LD12__LD12 IOMUX_MODE(MX31_PIN_LD12, IOMUX_CONFIG_FUNC) | ||
| 574 | #define MX31_PIN_LD13__LD13 IOMUX_MODE(MX31_PIN_LD13, IOMUX_CONFIG_FUNC) | ||
| 575 | #define MX31_PIN_LD14__LD14 IOMUX_MODE(MX31_PIN_LD14, IOMUX_CONFIG_FUNC) | ||
| 576 | #define MX31_PIN_LD15__LD15 IOMUX_MODE(MX31_PIN_LD15, IOMUX_CONFIG_FUNC) | ||
| 577 | #define MX31_PIN_LD16__LD16 IOMUX_MODE(MX31_PIN_LD16, IOMUX_CONFIG_FUNC) | ||
| 578 | #define MX31_PIN_LD17__LD17 IOMUX_MODE(MX31_PIN_LD17, IOMUX_CONFIG_FUNC) | ||
| 579 | #define MX31_PIN_VSYNC3__VSYNC3 IOMUX_MODE(MX31_PIN_VSYNC3, IOMUX_CONFIG_FUNC) | ||
| 580 | #define MX31_PIN_HSYNC__HSYNC IOMUX_MODE(MX31_PIN_HSYNC, IOMUX_CONFIG_FUNC) | ||
| 581 | #define MX31_PIN_FPSHIFT__FPSHIFT IOMUX_MODE(MX31_PIN_FPSHIFT, IOMUX_CONFIG_FUNC) | ||
| 582 | #define MX31_PIN_DRDY0__DRDY0 IOMUX_MODE(MX31_PIN_DRDY0, IOMUX_CONFIG_FUNC) | ||
| 583 | #define MX31_PIN_D3_REV__D3_REV IOMUX_MODE(MX31_PIN_D3_REV, IOMUX_CONFIG_FUNC) | ||
| 584 | #define MX31_PIN_CONTRAST__CONTRAST IOMUX_MODE(MX31_PIN_CONTRAST, IOMUX_CONFIG_FUNC) | ||
| 585 | #define MX31_PIN_D3_SPL__D3_SPL IOMUX_MODE(MX31_PIN_D3_SPL, IOMUX_CONFIG_FUNC) | ||
| 586 | #define MX31_PIN_D3_CLS__D3_CLS IOMUX_MODE(MX31_PIN_D3_CLS, IOMUX_CONFIG_FUNC) | ||
| 587 | #define MX31_PIN_LCS0__GPI03_23 IOMUX_MODE(MX31_PIN_LCS0, IOMUX_CONFIG_GPIO) | ||
| 528 | 588 | ||
| 529 | /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 | 589 | /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0 |
| 530 | * cspi1_ss1*/ | 590 | * cspi1_ss1*/ |
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h new file mode 100644 index 000000000000..171f8adc1109 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/iomux.h | |||
| @@ -0,0 +1,127 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de> | ||
| 3 | * Copyright (C) 2009 by Holger Schurig <hs4233@mail.mn-solutions.de> | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License | ||
| 7 | * as published by the Free Software Foundation; either version 2 | ||
| 8 | * of the License, or (at your option) any later version. | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 17 | * MA 02110-1301, USA. | ||
| 18 | */ | ||
| 19 | |||
| 20 | #ifndef _MXC_IOMUX_H | ||
| 21 | #define _MXC_IOMUX_H | ||
| 22 | |||
| 23 | /* | ||
| 24 | * GPIO Module and I/O Multiplexer | ||
| 25 | * x = 0..3 for reg_A, reg_B, reg_C, reg_D | ||
| 26 | */ | ||
| 27 | #define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR) | ||
| 28 | #define MXC_DDIR(x) (0x00 + ((x) << 8)) | ||
| 29 | #define MXC_OCR1(x) (0x04 + ((x) << 8)) | ||
| 30 | #define MXC_OCR2(x) (0x08 + ((x) << 8)) | ||
| 31 | #define MXC_ICONFA1(x) (0x0c + ((x) << 8)) | ||
| 32 | #define MXC_ICONFA2(x) (0x10 + ((x) << 8)) | ||
| 33 | #define MXC_ICONFB1(x) (0x14 + ((x) << 8)) | ||
| 34 | #define MXC_ICONFB2(x) (0x18 + ((x) << 8)) | ||
| 35 | #define MXC_DR(x) (0x1c + ((x) << 8)) | ||
| 36 | #define MXC_GIUS(x) (0x20 + ((x) << 8)) | ||
| 37 | #define MXC_SSR(x) (0x24 + ((x) << 8)) | ||
| 38 | #define MXC_ICR1(x) (0x28 + ((x) << 8)) | ||
| 39 | #define MXC_ICR2(x) (0x2c + ((x) << 8)) | ||
| 40 | #define MXC_IMR(x) (0x30 + ((x) << 8)) | ||
| 41 | #define MXC_ISR(x) (0x34 + ((x) << 8)) | ||
| 42 | #define MXC_GPR(x) (0x38 + ((x) << 8)) | ||
| 43 | #define MXC_SWR(x) (0x3c + ((x) << 8)) | ||
| 44 | #define MXC_PUEN(x) (0x40 + ((x) << 8)) | ||
| 45 | |||
| 46 | #ifdef CONFIG_ARCH_MX1 | ||
| 47 | # define GPIO_PORT_MAX 3 | ||
| 48 | #endif | ||
| 49 | #ifdef CONFIG_ARCH_MX2 | ||
| 50 | # define GPIO_PORT_MAX 5 | ||
| 51 | #endif | ||
| 52 | |||
| 53 | #ifndef GPIO_PORT_MAX | ||
| 54 | # error "GPIO config port count unknown!" | ||
| 55 | #endif | ||
| 56 | |||
| 57 | #define GPIO_PIN_MASK 0x1f | ||
| 58 | |||
| 59 | #define GPIO_PORT_SHIFT 5 | ||
| 60 | #define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) | ||
| 61 | |||
| 62 | #define GPIO_PORTA (0 << GPIO_PORT_SHIFT) | ||
| 63 | #define GPIO_PORTB (1 << GPIO_PORT_SHIFT) | ||
| 64 | #define GPIO_PORTC (2 << GPIO_PORT_SHIFT) | ||
| 65 | #define GPIO_PORTD (3 << GPIO_PORT_SHIFT) | ||
| 66 | #define GPIO_PORTE (4 << GPIO_PORT_SHIFT) | ||
| 67 | #define GPIO_PORTF (5 << GPIO_PORT_SHIFT) | ||
| 68 | |||
| 69 | #define GPIO_OUT (1 << 8) | ||
| 70 | #define GPIO_IN (0 << 8) | ||
| 71 | #define GPIO_PUEN (1 << 9) | ||
| 72 | |||
| 73 | #define GPIO_PF (1 << 10) | ||
| 74 | #define GPIO_AF (1 << 11) | ||
| 75 | |||
| 76 | #define GPIO_OCR_SHIFT 12 | ||
| 77 | #define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) | ||
| 78 | #define GPIO_AIN (0 << GPIO_OCR_SHIFT) | ||
| 79 | #define GPIO_BIN (1 << GPIO_OCR_SHIFT) | ||
| 80 | #define GPIO_CIN (2 << GPIO_OCR_SHIFT) | ||
| 81 | #define GPIO_GPIO (3 << GPIO_OCR_SHIFT) | ||
| 82 | |||
| 83 | #define GPIO_AOUT_SHIFT 14 | ||
| 84 | #define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) | ||
| 85 | #define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) | ||
| 86 | #define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) | ||
| 87 | #define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) | ||
| 88 | #define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) | ||
| 89 | |||
| 90 | #define GPIO_BOUT_SHIFT 16 | ||
| 91 | #define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) | ||
| 92 | #define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) | ||
| 93 | #define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) | ||
| 94 | #define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) | ||
| 95 | #define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) | ||
| 96 | |||
| 97 | |||
| 98 | #ifdef CONFIG_ARCH_MX1 | ||
| 99 | #include <mach/iomux-mx1.h> | ||
| 100 | #endif | ||
| 101 | #ifdef CONFIG_ARCH_MX2 | ||
| 102 | #include <mach/iomux-mx2x.h> | ||
| 103 | #ifdef CONFIG_MACH_MX21 | ||
| 104 | #include <mach/iomux-mx21.h> | ||
| 105 | #endif | ||
| 106 | #ifdef CONFIG_MACH_MX27 | ||
| 107 | #include <mach/iomux-mx27.h> | ||
| 108 | #endif | ||
| 109 | #endif | ||
| 110 | |||
| 111 | |||
| 112 | /* decode irq number to use with IMR(x), ISR(x) and friends */ | ||
| 113 | #define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5) | ||
| 114 | |||
| 115 | #define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x) | ||
| 116 | #define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x) | ||
| 117 | #define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x) | ||
| 118 | #define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x) | ||
| 119 | #define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x) | ||
| 120 | |||
| 121 | |||
| 122 | extern void mxc_gpio_mode(int gpio_mode); | ||
| 123 | extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count, | ||
| 124 | const char *label); | ||
| 125 | extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count); | ||
| 126 | |||
| 127 | #endif | ||
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 0b808399097f..e0783e619580 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h | |||
| @@ -14,7 +14,12 @@ | |||
| 14 | #if defined CONFIG_ARCH_MX1 | 14 | #if defined CONFIG_ARCH_MX1 |
| 15 | #define PHYS_OFFSET UL(0x08000000) | 15 | #define PHYS_OFFSET UL(0x08000000) |
| 16 | #elif defined CONFIG_ARCH_MX2 | 16 | #elif defined CONFIG_ARCH_MX2 |
| 17 | #ifdef CONFIG_MACH_MX21 | ||
| 18 | #define PHYS_OFFSET UL(0xC0000000) | ||
| 19 | #endif | ||
| 20 | #ifdef CONFIG_MACH_MX27 | ||
| 17 | #define PHYS_OFFSET UL(0xA0000000) | 21 | #define PHYS_OFFSET UL(0xA0000000) |
| 22 | #endif | ||
| 18 | #elif defined CONFIG_ARCH_MX3 | 23 | #elif defined CONFIG_ARCH_MX3 |
| 19 | #define PHYS_OFFSET UL(0x80000000) | 24 | #define PHYS_OFFSET UL(0x80000000) |
| 20 | #endif | 25 | #endif |
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h new file mode 100644 index 000000000000..e8c4cf56c24e --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx21.h | |||
| @@ -0,0 +1,78 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de | ||
| 5 | * | ||
| 6 | * This contains i.MX21-specific hardware definitions. For those | ||
| 7 | * hardware pieces that are common between i.MX21 and i.MX27, have a | ||
| 8 | * look at mx2x.h. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or | ||
| 11 | * modify it under the terms of the GNU General Public License | ||
| 12 | * as published by the Free Software Foundation; either version 2 | ||
| 13 | * of the License, or (at your option) any later version. | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this program; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 22 | * MA 02110-1301, USA. | ||
| 23 | */ | ||
| 24 | |||
| 25 | #ifndef __ASM_ARCH_MXC_MX21_H__ | ||
| 26 | #define __ASM_ARCH_MXC_MX21_H__ | ||
| 27 | |||
| 28 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ | ||
| 29 | #error "Do not include directly." | ||
| 30 | #endif | ||
| 31 | |||
| 32 | |||
| 33 | /* Memory regions and CS */ | ||
| 34 | #define SDRAM_BASE_ADDR 0xC0000000 | ||
| 35 | #define CSD1_BASE_ADDR 0xC4000000 | ||
| 36 | |||
| 37 | #define CS0_BASE_ADDR 0xC8000000 | ||
| 38 | #define CS1_BASE_ADDR 0xCC000000 | ||
| 39 | #define CS2_BASE_ADDR 0xD0000000 | ||
| 40 | #define CS3_BASE_ADDR 0xD1000000 | ||
| 41 | #define CS4_BASE_ADDR 0xD2000000 | ||
| 42 | #define CS5_BASE_ADDR 0xDD000000 | ||
| 43 | #define PCMCIA_MEM_BASE_ADDR 0xD4000000 | ||
| 44 | |||
| 45 | /* NAND, SDRAM, WEIM etc controllers */ | ||
| 46 | #define X_MEMC_BASE_ADDR 0xDF000000 | ||
| 47 | #define X_MEMC_BASE_ADDR_VIRT 0xF4200000 | ||
| 48 | #define X_MEMC_SIZE SZ_256K | ||
| 49 | |||
| 50 | #define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) | ||
| 51 | #define EIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) | ||
| 52 | #define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) | ||
| 53 | #define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) | ||
| 54 | |||
| 55 | #define IRAM_BASE_ADDR 0xFFFFE800 /* internal ram */ | ||
| 56 | |||
| 57 | /* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */ | ||
| 58 | #define ARCH_NR_GPIOS (6*32 + 16) | ||
| 59 | |||
| 60 | /* fixed interrupt numbers */ | ||
| 61 | #define MXC_INT_USBCTRL 58 | ||
| 62 | #define MXC_INT_USBCTRL 58 | ||
| 63 | #define MXC_INT_USBMNP 57 | ||
| 64 | #define MXC_INT_USBFUNC 56 | ||
| 65 | #define MXC_INT_USBHOST 55 | ||
| 66 | #define MXC_INT_USBDMA 54 | ||
| 67 | #define MXC_INT_USBWKUP 53 | ||
| 68 | #define MXC_INT_EMMADEC 50 | ||
| 69 | #define MXC_INT_EMMAENC 49 | ||
| 70 | #define MXC_INT_BMI 30 | ||
| 71 | #define MXC_INT_FIRI 9 | ||
| 72 | |||
| 73 | /* fixed DMA request numbers */ | ||
| 74 | #define DMA_REQ_BMI_RX 29 | ||
| 75 | #define DMA_REQ_BMI_TX 28 | ||
| 76 | #define DMA_REQ_FIRI_RX 4 | ||
| 77 | |||
| 78 | #endif /* __ASM_ARCH_MXC_MX21_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 0313be720552..6e93f2c0b7bb 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h | |||
| @@ -2,6 +2,10 @@ | |||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de |
| 4 | * | 4 | * |
| 5 | * This contains i.MX27-specific hardware definitions. For those | ||
| 6 | * hardware pieces that are common between i.MX21 and i.MX27, have a | ||
| 7 | * look at mx2x.h. | ||
| 8 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | 9 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License | 10 | * modify it under the terms of the GNU General Public License |
| 7 | * as published by the Free Software Foundation; either version 2 | 11 | * as published by the Free Software Foundation; either version 2 |
| @@ -27,35 +31,6 @@ | |||
| 27 | /* IRAM */ | 31 | /* IRAM */ |
| 28 | #define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ | 32 | #define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */ |
| 29 | 33 | ||
| 30 | /* Register offests */ | ||
| 31 | #define AIPI_BASE_ADDR 0x10000000 | ||
| 32 | #define AIPI_BASE_ADDR_VIRT 0xF4000000 | ||
| 33 | #define AIPI_SIZE SZ_1M | ||
| 34 | |||
| 35 | #define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000) | ||
| 36 | #define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000) | ||
| 37 | #define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000) | ||
| 38 | #define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000) | ||
| 39 | #define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000) | ||
| 40 | #define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000) | ||
| 41 | #define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000) | ||
| 42 | #define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000) | ||
| 43 | #define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000) | ||
| 44 | #define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000) | ||
| 45 | #define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000) | ||
| 46 | #define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000) | ||
| 47 | #define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000) | ||
| 48 | #define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000) | ||
| 49 | #define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000) | ||
| 50 | #define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000) | ||
| 51 | #define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000) | ||
| 52 | #define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000) | ||
| 53 | #define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000) | ||
| 54 | #define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000) | ||
| 55 | #define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000) | ||
| 56 | #define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000) | ||
| 57 | |||
| 58 | #define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000) | ||
| 59 | #define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000) | 34 | #define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000) |
| 60 | #define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000) | 35 | #define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000) |
| 61 | #define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000) | 36 | #define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000) |
| @@ -64,55 +39,24 @@ | |||
| 64 | #define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000) | 39 | #define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000) |
| 65 | #define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000) | 40 | #define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000) |
| 66 | #define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000) | 41 | #define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000) |
| 67 | |||
| 68 | #define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000) | ||
| 69 | #define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000) | ||
| 70 | #define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000) | 42 | #define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000) |
| 71 | #define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000) | ||
| 72 | /* for mx27*/ | ||
| 73 | #define OTG_BASE_ADDR USBOTG_BASE_ADDR | 43 | #define OTG_BASE_ADDR USBOTG_BASE_ADDR |
| 74 | #define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000) | 44 | #define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000) |
| 75 | #define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000) | ||
| 76 | #define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400) | ||
| 77 | #define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000) | ||
| 78 | #define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800) | ||
| 79 | #define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000) | 45 | #define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000) |
| 80 | |||
| 81 | #define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000) | 46 | #define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000) |
| 82 | #define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000) | 47 | #define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000) |
| 83 | #define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000) | 48 | #define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000) |
| 84 | #define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000) | 49 | #define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000) |
| 85 | #define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000) | 50 | #define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000) |
| 86 | 51 | ||
| 87 | #define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000) | 52 | /* ROM patch */ |
| 88 | #define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000) | ||
| 89 | |||
| 90 | /* ROMP and AVIC */ | ||
| 91 | #define ROMP_BASE_ADDR 0x10041000 | 53 | #define ROMP_BASE_ADDR 0x10041000 |
| 92 | 54 | ||
| 93 | #define AVIC_BASE_ADDR 0x10040000 | ||
| 94 | |||
| 95 | #define SAHB1_BASE_ADDR 0x80000000 | ||
| 96 | #define SAHB1_BASE_ADDR_VIRT 0xF4100000 | ||
| 97 | #define SAHB1_SIZE SZ_1M | ||
| 98 | |||
| 99 | #define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000) | ||
| 100 | #define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000) | 55 | #define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000) |
| 101 | 56 | ||
| 102 | /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ | ||
| 103 | #define X_MEMC_BASE_ADDR 0xD8000000 | ||
| 104 | #define X_MEMC_BASE_ADDR_VIRT 0xF4200000 | ||
| 105 | #define X_MEMC_SIZE SZ_1M | ||
| 106 | |||
| 107 | #define NFC_BASE_ADDR (X_MEMC_BASE_ADDR) | ||
| 108 | #define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) | ||
| 109 | #define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) | ||
| 110 | #define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) | ||
| 111 | #define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) | ||
| 112 | |||
| 113 | /* Memory regions and CS */ | 57 | /* Memory regions and CS */ |
| 114 | #define SDRAM_BASE_ADDR 0xA0000000 | 58 | #define SDRAM_BASE_ADDR 0xA0000000 |
| 115 | #define CSD1_BASE_ADDR 0xB0000000 | 59 | #define CSD1_BASE_ADDR 0xB0000000 |
| 116 | 60 | ||
| 117 | #define CS0_BASE_ADDR 0xC0000000 | 61 | #define CS0_BASE_ADDR 0xC0000000 |
| 118 | #define CS1_BASE_ADDR 0xC8000000 | 62 | #define CS1_BASE_ADDR 0xC8000000 |
| @@ -122,44 +66,20 @@ | |||
| 122 | #define CS5_BASE_ADDR 0xD6000000 | 66 | #define CS5_BASE_ADDR 0xD6000000 |
| 123 | #define PCMCIA_MEM_BASE_ADDR 0xDC000000 | 67 | #define PCMCIA_MEM_BASE_ADDR 0xDC000000 |
| 124 | 68 | ||
| 125 | /* | 69 | /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ |
| 126 | * This macro defines the physical to virtual address mapping for all the | 70 | #define X_MEMC_BASE_ADDR 0xD8000000 |
| 127 | * peripheral modules. It is used by passing in the physical address as x | 71 | #define X_MEMC_BASE_ADDR_VIRT 0xF4200000 |
| 128 | * and returning the virtual address. If the physical address is not mapped, | 72 | #define X_MEMC_SIZE SZ_1M |
| 129 | * it returns 0xDEADBEEF | ||
| 130 | */ | ||
| 131 | #define IO_ADDRESS(x) \ | ||
| 132 | (void __iomem *) \ | ||
| 133 | (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \ | ||
| 134 | AIPI_IO_ADDRESS(x) : \ | ||
| 135 | ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \ | ||
| 136 | SAHB1_IO_ADDRESS(x) : \ | ||
| 137 | ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \ | ||
| 138 | X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF) | ||
| 139 | |||
| 140 | /* define the address mapping macros: in physical address order */ | ||
| 141 | #define AIPI_IO_ADDRESS(x) \ | ||
| 142 | (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT) | ||
| 143 | |||
| 144 | #define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x) | ||
| 145 | |||
| 146 | #define SAHB1_IO_ADDRESS(x) \ | ||
| 147 | (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT) | ||
| 148 | |||
| 149 | #define CS4_IO_ADDRESS(x) \ | ||
| 150 | (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) | ||
| 151 | |||
| 152 | #define X_MEMC_IO_ADDRESS(x) \ | ||
| 153 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 154 | 73 | ||
| 155 | #define PCMCIA_IO_ADDRESS(x) \ | 74 | #define NFC_BASE_ADDR (X_MEMC_BASE_ADDR) |
| 156 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | 75 | #define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) |
| 76 | #define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) | ||
| 77 | #define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) | ||
| 78 | #define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) | ||
| 157 | 79 | ||
| 158 | /* fixed interrput numbers */ | 80 | /* fixed interrupt numbers */ |
| 159 | #define MXC_INT_CCM 63 | 81 | #define MXC_INT_CCM 63 |
| 160 | #define MXC_INT_IIM 62 | 82 | #define MXC_INT_IIM 62 |
| 161 | #define MXC_INT_LCDC 61 | ||
| 162 | #define MXC_INT_SLCDC 60 | ||
| 163 | #define MXC_INT_SAHARA 59 | 83 | #define MXC_INT_SAHARA 59 |
| 164 | #define MXC_INT_SCC_SCM 58 | 84 | #define MXC_INT_SCC_SCM 58 |
| 165 | #define MXC_INT_SCC_SMN 57 | 85 | #define MXC_INT_SCC_SMN 57 |
| @@ -167,54 +87,12 @@ | |||
| 167 | #define MXC_INT_USB2 55 | 87 | #define MXC_INT_USB2 55 |
| 168 | #define MXC_INT_USB1 54 | 88 | #define MXC_INT_USB1 54 |
| 169 | #define MXC_INT_VPU 53 | 89 | #define MXC_INT_VPU 53 |
| 170 | #define MXC_INT_EMMAPP 52 | ||
| 171 | #define MXC_INT_EMMAPRP 51 | ||
| 172 | #define MXC_INT_FEC 50 | 90 | #define MXC_INT_FEC 50 |
| 173 | #define MXC_INT_UART5 49 | 91 | #define MXC_INT_UART5 49 |
| 174 | #define MXC_INT_UART6 48 | 92 | #define MXC_INT_UART6 48 |
| 175 | #define MXC_INT_DMACH15 47 | ||
| 176 | #define MXC_INT_DMACH14 46 | ||
| 177 | #define MXC_INT_DMACH13 45 | ||
| 178 | #define MXC_INT_DMACH12 44 | ||
| 179 | #define MXC_INT_DMACH11 43 | ||
| 180 | #define MXC_INT_DMACH10 42 | ||
| 181 | #define MXC_INT_DMACH9 41 | ||
| 182 | #define MXC_INT_DMACH8 40 | ||
| 183 | #define MXC_INT_DMACH7 39 | ||
| 184 | #define MXC_INT_DMACH6 38 | ||
| 185 | #define MXC_INT_DMACH5 37 | ||
| 186 | #define MXC_INT_DMACH4 36 | ||
| 187 | #define MXC_INT_DMACH3 35 | ||
| 188 | #define MXC_INT_DMACH2 34 | ||
| 189 | #define MXC_INT_DMACH1 33 | ||
| 190 | #define MXC_INT_DMACH0 32 | ||
| 191 | #define MXC_INT_CSI 31 | ||
| 192 | #define MXC_INT_ATA 30 | 93 | #define MXC_INT_ATA 30 |
| 193 | #define MXC_INT_NANDFC 29 | ||
| 194 | #define MXC_INT_PCMCIA 28 | ||
| 195 | #define MXC_INT_WDOG 27 | ||
| 196 | #define MXC_INT_GPT1 26 | ||
| 197 | #define MXC_INT_GPT2 25 | ||
| 198 | #define MXC_INT_GPT3 24 | ||
| 199 | #define MXC_INT_GPT INT_GPT1 | ||
| 200 | #define MXC_INT_PWM 23 | ||
| 201 | #define MXC_INT_RTC 22 | ||
| 202 | #define MXC_INT_KPP 21 | ||
| 203 | #define MXC_INT_UART1 20 | ||
| 204 | #define MXC_INT_UART2 19 | ||
| 205 | #define MXC_INT_UART3 18 | ||
| 206 | #define MXC_INT_UART4 17 | ||
| 207 | #define MXC_INT_CSPI1 16 | ||
| 208 | #define MXC_INT_CSPI2 15 | ||
| 209 | #define MXC_INT_SSI1 14 | ||
| 210 | #define MXC_INT_SSI2 13 | ||
| 211 | #define MXC_INT_I2C 12 | ||
| 212 | #define MXC_INT_SDHC1 11 | ||
| 213 | #define MXC_INT_SDHC2 10 | ||
| 214 | #define MXC_INT_SDHC3 9 | 94 | #define MXC_INT_SDHC3 9 |
| 215 | #define MXC_INT_GPIO 8 | ||
| 216 | #define MXC_INT_SDHC 7 | 95 | #define MXC_INT_SDHC 7 |
| 217 | #define MXC_INT_CSPI3 6 | ||
| 218 | #define MXC_INT_RTIC 5 | 96 | #define MXC_INT_RTIC 5 |
| 219 | #define MXC_INT_GPT4 4 | 97 | #define MXC_INT_GPT4 4 |
| 220 | #define MXC_INT_GPT5 3 | 98 | #define MXC_INT_GPT5 3 |
| @@ -228,36 +106,9 @@ | |||
| 228 | #define DMA_REQ_UART6_TX 34 | 106 | #define DMA_REQ_UART6_TX 34 |
| 229 | #define DMA_REQ_UART5_RX 33 | 107 | #define DMA_REQ_UART5_RX 33 |
| 230 | #define DMA_REQ_UART5_TX 32 | 108 | #define DMA_REQ_UART5_TX 32 |
| 231 | #define DMA_REQ_CSI_RX 31 | ||
| 232 | #define DMA_REQ_CSI_STAT 30 | ||
| 233 | #define DMA_REQ_ATA_RCV 29 | 109 | #define DMA_REQ_ATA_RCV 29 |
| 234 | #define DMA_REQ_ATA_TX 28 | 110 | #define DMA_REQ_ATA_TX 28 |
| 235 | #define DMA_REQ_UART1_TX 27 | ||
| 236 | #define DMA_REQ_UART1_RX 26 | ||
| 237 | #define DMA_REQ_UART2_TX 25 | ||
| 238 | #define DMA_REQ_UART2_RX 24 | ||
| 239 | #define DMA_REQ_UART3_TX 23 | ||
| 240 | #define DMA_REQ_UART3_RX 22 | ||
| 241 | #define DMA_REQ_UART4_TX 21 | ||
| 242 | #define DMA_REQ_UART4_RX 20 | ||
| 243 | #define DMA_REQ_CSPI1_TX 19 | ||
| 244 | #define DMA_REQ_CSPI1_RX 18 | ||
| 245 | #define DMA_REQ_CSPI2_TX 17 | ||
| 246 | #define DMA_REQ_CSPI2_RX 16 | ||
| 247 | #define DMA_REQ_SSI1_TX1 15 | ||
| 248 | #define DMA_REQ_SSI1_RX1 14 | ||
| 249 | #define DMA_REQ_SSI1_TX0 13 | ||
| 250 | #define DMA_REQ_SSI1_RX0 12 | ||
| 251 | #define DMA_REQ_SSI2_TX1 11 | ||
| 252 | #define DMA_REQ_SSI2_RX1 10 | ||
| 253 | #define DMA_REQ_SSI2_TX0 9 | ||
| 254 | #define DMA_REQ_SSI2_RX0 8 | ||
| 255 | #define DMA_REQ_SDHC1 7 | ||
| 256 | #define DMA_REQ_SDHC2 6 | ||
| 257 | #define DMA_REQ_MSHC 4 | 111 | #define DMA_REQ_MSHC 4 |
| 258 | #define DMA_REQ_EXT 3 | ||
| 259 | #define DMA_REQ_CSPI3_TX 2 | ||
| 260 | #define DMA_REQ_CSPI3_RX 1 | ||
| 261 | 112 | ||
| 262 | /* silicon revisions specific to i.MX27 */ | 113 | /* silicon revisions specific to i.MX27 */ |
| 263 | #define CHIP_REV_1_0 0x00 | 114 | #define CHIP_REV_1_0 0x00 |
| @@ -267,25 +118,8 @@ | |||
| 267 | extern int mx27_revision(void); | 118 | extern int mx27_revision(void); |
| 268 | #endif | 119 | #endif |
| 269 | 120 | ||
| 270 | /* gpio and gpio based interrupt handling */ | ||
| 271 | #define GPIO_DR 0x1C | ||
| 272 | #define GPIO_GDIR 0x00 | ||
| 273 | #define GPIO_PSR 0x24 | ||
| 274 | #define GPIO_ICR1 0x28 | ||
| 275 | #define GPIO_ICR2 0x2C | ||
| 276 | #define GPIO_IMR 0x30 | ||
| 277 | #define GPIO_ISR 0x34 | ||
| 278 | #define GPIO_INT_LOW_LEV 0x3 | ||
| 279 | #define GPIO_INT_HIGH_LEV 0x2 | ||
| 280 | #define GPIO_INT_RISE_EDGE 0x0 | ||
| 281 | #define GPIO_INT_FALL_EDGE 0x1 | ||
| 282 | #define GPIO_INT_NONE 0x4 | ||
| 283 | |||
| 284 | /* Mandatory defines used globally */ | 121 | /* Mandatory defines used globally */ |
| 285 | 122 | ||
| 286 | /* this is an i.MX27 CPU */ | ||
| 287 | #define cpu_is_mx27() (1) | ||
| 288 | |||
| 289 | /* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */ | 123 | /* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */ |
| 290 | #define ARCH_NR_GPIOS (192 + 16) | 124 | #define ARCH_NR_GPIOS (192 + 16) |
| 291 | 125 | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h new file mode 100644 index 000000000000..fc40d3ab8c5b --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx2x.h | |||
| @@ -0,0 +1,200 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | ||
| 4 | * | ||
| 5 | * This contains hardware definitions that are common between i.MX21 and | ||
| 6 | * i.MX27. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or | ||
| 9 | * modify it under the terms of the GNU General Public License | ||
| 10 | * as published by the Free Software Foundation; either version 2 | ||
| 11 | * of the License, or (at your option) any later version. | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | ||
| 20 | * MA 02110-1301, USA. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef __ASM_ARCH_MXC_MX2x_H__ | ||
| 24 | #define __ASM_ARCH_MXC_MX2x_H__ | ||
| 25 | |||
| 26 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ | ||
| 27 | #error "Do not include directly." | ||
| 28 | #endif | ||
| 29 | |||
| 30 | /* The following addresses are common between i.MX21 and i.MX27 */ | ||
| 31 | |||
| 32 | /* Register offests */ | ||
| 33 | #define AIPI_BASE_ADDR 0x10000000 | ||
| 34 | #define AIPI_BASE_ADDR_VIRT 0xF4000000 | ||
| 35 | #define AIPI_SIZE SZ_1M | ||
| 36 | |||
| 37 | #define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000) | ||
| 38 | #define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000) | ||
| 39 | #define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000) | ||
| 40 | #define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000) | ||
| 41 | #define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000) | ||
| 42 | #define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000) | ||
| 43 | #define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000) | ||
| 44 | #define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000) | ||
| 45 | #define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000) | ||
| 46 | #define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000) | ||
| 47 | #define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000) | ||
| 48 | #define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000) | ||
| 49 | #define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000) | ||
| 50 | #define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000) | ||
| 51 | #define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000) | ||
| 52 | #define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000) | ||
| 53 | #define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000) | ||
| 54 | #define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000) | ||
| 55 | #define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000) | ||
| 56 | #define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000) | ||
| 57 | #define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000) | ||
| 58 | #define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000) | ||
| 59 | #define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000) | ||
| 60 | #define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000) | ||
| 61 | #define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000) | ||
| 62 | #define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000) | ||
| 63 | #define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000) | ||
| 64 | #define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400) | ||
| 65 | #define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000) | ||
| 66 | #define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800) | ||
| 67 | #define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000) | ||
| 68 | #define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000) | ||
| 69 | |||
| 70 | #define AVIC_BASE_ADDR 0x10040000 | ||
| 71 | |||
| 72 | #define SAHB1_BASE_ADDR 0x80000000 | ||
| 73 | #define SAHB1_BASE_ADDR_VIRT 0xF4100000 | ||
| 74 | #define SAHB1_SIZE SZ_1M | ||
| 75 | |||
| 76 | #define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000) | ||
| 77 | |||
| 78 | /* | ||
| 79 | * This macro defines the physical to virtual address mapping for all the | ||
| 80 | * peripheral modules. It is used by passing in the physical address as x | ||
| 81 | * and returning the virtual address. If the physical address is not mapped, | ||
| 82 | * it returns 0xDEADBEEF | ||
| 83 | */ | ||
| 84 | #define IO_ADDRESS(x) \ | ||
| 85 | (void __force __iomem *) \ | ||
| 86 | (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \ | ||
| 87 | AIPI_IO_ADDRESS(x) : \ | ||
| 88 | ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \ | ||
| 89 | SAHB1_IO_ADDRESS(x) : \ | ||
| 90 | ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \ | ||
| 91 | X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF) | ||
| 92 | |||
| 93 | /* define the address mapping macros: in physical address order */ | ||
| 94 | #define AIPI_IO_ADDRESS(x) \ | ||
| 95 | (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT) | ||
| 96 | |||
| 97 | #define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x) | ||
| 98 | |||
| 99 | #define SAHB1_IO_ADDRESS(x) \ | ||
| 100 | (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT) | ||
| 101 | |||
| 102 | #define CS4_IO_ADDRESS(x) \ | ||
| 103 | (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) | ||
| 104 | |||
| 105 | #define X_MEMC_IO_ADDRESS(x) \ | ||
| 106 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 107 | |||
| 108 | #define PCMCIA_IO_ADDRESS(x) \ | ||
| 109 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 110 | |||
| 111 | /* fixed interrupt numbers */ | ||
| 112 | #define MXC_INT_LCDC 61 | ||
| 113 | #define MXC_INT_SLCDC 60 | ||
| 114 | #define MXC_INT_EMMAPP 52 | ||
| 115 | #define MXC_INT_EMMAPRP 51 | ||
| 116 | #define MXC_INT_DMACH15 47 | ||
| 117 | #define MXC_INT_DMACH14 46 | ||
| 118 | #define MXC_INT_DMACH13 45 | ||
| 119 | #define MXC_INT_DMACH12 44 | ||
| 120 | #define MXC_INT_DMACH11 43 | ||
| 121 | #define MXC_INT_DMACH10 42 | ||
| 122 | #define MXC_INT_DMACH9 41 | ||
| 123 | #define MXC_INT_DMACH8 40 | ||
| 124 | #define MXC_INT_DMACH7 39 | ||
| 125 | #define MXC_INT_DMACH6 38 | ||
| 126 | #define MXC_INT_DMACH5 37 | ||
| 127 | #define MXC_INT_DMACH4 36 | ||
| 128 | #define MXC_INT_DMACH3 35 | ||
| 129 | #define MXC_INT_DMACH2 34 | ||
| 130 | #define MXC_INT_DMACH1 33 | ||
| 131 | #define MXC_INT_DMACH0 32 | ||
| 132 | #define MXC_INT_CSI 31 | ||
| 133 | #define MXC_INT_NANDFC 29 | ||
| 134 | #define MXC_INT_PCMCIA 28 | ||
| 135 | #define MXC_INT_WDOG 27 | ||
| 136 | #define MXC_INT_GPT1 26 | ||
| 137 | #define MXC_INT_GPT2 25 | ||
| 138 | #define MXC_INT_GPT3 24 | ||
| 139 | #define MXC_INT_GPT INT_GPT1 | ||
| 140 | #define MXC_INT_PWM 23 | ||
| 141 | #define MXC_INT_RTC 22 | ||
| 142 | #define MXC_INT_KPP 21 | ||
| 143 | #define MXC_INT_UART1 20 | ||
| 144 | #define MXC_INT_UART2 19 | ||
| 145 | #define MXC_INT_UART3 18 | ||
| 146 | #define MXC_INT_UART4 17 | ||
| 147 | #define MXC_INT_CSPI1 16 | ||
| 148 | #define MXC_INT_CSPI2 15 | ||
| 149 | #define MXC_INT_SSI1 14 | ||
| 150 | #define MXC_INT_SSI2 13 | ||
| 151 | #define MXC_INT_I2C 12 | ||
| 152 | #define MXC_INT_SDHC1 11 | ||
| 153 | #define MXC_INT_SDHC2 10 | ||
| 154 | #define MXC_INT_GPIO 8 | ||
| 155 | #define MXC_INT_CSPI3 6 | ||
| 156 | |||
| 157 | /* gpio and gpio based interrupt handling */ | ||
| 158 | #define GPIO_DR 0x1C | ||
| 159 | #define GPIO_GDIR 0x00 | ||
| 160 | #define GPIO_PSR 0x24 | ||
| 161 | #define GPIO_ICR1 0x28 | ||
| 162 | #define GPIO_ICR2 0x2C | ||
| 163 | #define GPIO_IMR 0x30 | ||
| 164 | #define GPIO_ISR 0x34 | ||
| 165 | #define GPIO_INT_LOW_LEV 0x3 | ||
| 166 | #define GPIO_INT_HIGH_LEV 0x2 | ||
| 167 | #define GPIO_INT_RISE_EDGE 0x0 | ||
| 168 | #define GPIO_INT_FALL_EDGE 0x1 | ||
| 169 | #define GPIO_INT_NONE 0x4 | ||
| 170 | |||
| 171 | /* fixed DMA request numbers */ | ||
| 172 | #define DMA_REQ_CSI_RX 31 | ||
| 173 | #define DMA_REQ_CSI_STAT 30 | ||
| 174 | #define DMA_REQ_UART1_TX 27 | ||
| 175 | #define DMA_REQ_UART1_RX 26 | ||
| 176 | #define DMA_REQ_UART2_TX 25 | ||
| 177 | #define DMA_REQ_UART2_RX 24 | ||
| 178 | #define DMA_REQ_UART3_TX 23 | ||
| 179 | #define DMA_REQ_UART3_RX 22 | ||
| 180 | #define DMA_REQ_UART4_TX 21 | ||
| 181 | #define DMA_REQ_UART4_RX 20 | ||
| 182 | #define DMA_REQ_CSPI1_TX 19 | ||
| 183 | #define DMA_REQ_CSPI1_RX 18 | ||
| 184 | #define DMA_REQ_CSPI2_TX 17 | ||
| 185 | #define DMA_REQ_CSPI2_RX 16 | ||
| 186 | #define DMA_REQ_SSI1_TX1 15 | ||
| 187 | #define DMA_REQ_SSI1_RX1 14 | ||
| 188 | #define DMA_REQ_SSI1_TX0 13 | ||
| 189 | #define DMA_REQ_SSI1_RX0 12 | ||
| 190 | #define DMA_REQ_SSI2_TX1 11 | ||
| 191 | #define DMA_REQ_SSI2_RX1 10 | ||
| 192 | #define DMA_REQ_SSI2_TX0 9 | ||
| 193 | #define DMA_REQ_SSI2_RX0 8 | ||
| 194 | #define DMA_REQ_SDHC1 7 | ||
| 195 | #define DMA_REQ_SDHC2 6 | ||
| 196 | #define DMA_REQ_EXT 3 | ||
| 197 | #define DMA_REQ_CSPI3_TX 2 | ||
| 198 | #define DMA_REQ_CSPI3_RX 1 | ||
| 199 | |||
| 200 | #endif /* __ASM_ARCH_MXC_MX2x_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index de026654b00e..0b06941b6139 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h | |||
| @@ -1,360 +1,45 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MXC_MX31_H__ | ||
| 12 | #define __ASM_ARCH_MXC_MX31_H__ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ | ||
| 15 | #error "Do not include directly." | ||
| 16 | #endif | ||
| 17 | |||
| 18 | /* | ||
| 19 | * MX31 memory map: | ||
| 20 | * | ||
| 21 | * Virt Phys Size What | ||
| 22 | * --------------------------------------------------------------------------- | ||
| 23 | * F8000000 1FFC0000 16K IRAM | ||
| 24 | * F9000000 30000000 256M L2CC | ||
| 25 | * FC000000 43F00000 1M AIPS 1 | ||
| 26 | * FC100000 50000000 1M SPBA | ||
| 27 | * FC200000 53F00000 1M AIPS 2 | ||
| 28 | * FC500000 60000000 128M ROMPATCH | ||
| 29 | * FC400000 68000000 128M AVIC | ||
| 30 | * 70000000 256M IPU (MAX M2) | ||
| 31 | * 80000000 256M CSD0 SDRAM/DDR | ||
| 32 | * 90000000 256M CSD1 SDRAM/DDR | ||
| 33 | * A0000000 128M CS0 Flash | ||
| 34 | * A8000000 128M CS1 Flash | ||
| 35 | * B0000000 32M CS2 | ||
| 36 | * B2000000 32M CS3 | ||
| 37 | * F4000000 B4000000 32M CS4 | ||
| 38 | * B6000000 32M CS5 | ||
| 39 | * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers | ||
| 40 | * C0000000 64M PCMCIA/CF | ||
| 41 | */ | ||
| 42 | |||
| 43 | #define CS0_BASE_ADDR 0xA0000000 | ||
| 44 | #define CS1_BASE_ADDR 0xA8000000 | ||
| 45 | #define CS2_BASE_ADDR 0xB0000000 | ||
| 46 | #define CS3_BASE_ADDR 0xB2000000 | ||
| 47 | |||
| 48 | #define CS4_BASE_ADDR 0xB4000000 | ||
| 49 | #define CS4_BASE_ADDR_VIRT 0xF4000000 | ||
| 50 | #define CS4_SIZE SZ_32M | ||
| 51 | |||
| 52 | #define CS5_BASE_ADDR 0xB6000000 | ||
| 53 | #define PCMCIA_MEM_BASE_ADDR 0xBC000000 | ||
| 54 | |||
| 55 | /* | ||
| 56 | * IRAM | 2 | * IRAM |
| 57 | */ | 3 | */ |
| 58 | #define IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ | 4 | #define MX31_IRAM_BASE_ADDR 0x1FFC0000 /* internal ram */ |
| 59 | #define IRAM_BASE_ADDR_VIRT 0xF8000000 | 5 | #define MX31_IRAM_SIZE SZ_16K |
| 60 | #define IRAM_SIZE SZ_16K | ||
| 61 | |||
| 62 | /* | ||
| 63 | * L2CC | ||
| 64 | */ | ||
| 65 | #define L2CC_BASE_ADDR 0x30000000 | ||
| 66 | #define L2CC_BASE_ADDR_VIRT 0xF9000000 | ||
| 67 | #define L2CC_SIZE SZ_1M | ||
| 68 | |||
| 69 | /* | ||
| 70 | * AIPS 1 | ||
| 71 | */ | ||
| 72 | #define AIPS1_BASE_ADDR 0x43F00000 | ||
| 73 | #define AIPS1_BASE_ADDR_VIRT 0xFC000000 | ||
| 74 | #define AIPS1_SIZE SZ_1M | ||
| 75 | 6 | ||
| 76 | #define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000) | ||
| 77 | #define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000) | ||
| 78 | #define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000) | ||
| 79 | #define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000) | ||
| 80 | #define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000) | ||
| 81 | #define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000) | ||
| 82 | #define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) | ||
| 83 | #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) | ||
| 84 | #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) | 7 | #define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) |
| 85 | #define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) | 8 | #define ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) |
| 86 | #define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) | ||
| 87 | #define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) | ||
| 88 | #define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) | ||
| 89 | #define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) | ||
| 90 | #define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) | ||
| 91 | #define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) | ||
| 92 | #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) | ||
| 93 | #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) | ||
| 94 | #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) | 9 | #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) |
| 95 | #define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) | 10 | #define UART5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) |
| 96 | #define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) | ||
| 97 | #define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) | ||
| 98 | |||
| 99 | /* | ||
| 100 | * SPBA global module enabled #0 | ||
| 101 | */ | ||
| 102 | #define SPBA0_BASE_ADDR 0x50000000 | ||
| 103 | #define SPBA0_BASE_ADDR_VIRT 0xFC100000 | ||
| 104 | #define SPBA0_SIZE SZ_1M | ||
| 105 | 11 | ||
| 106 | #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) | 12 | #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) |
| 107 | #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) | 13 | #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) |
| 108 | #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) | ||
| 109 | #define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) | ||
| 110 | #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) | ||
| 111 | #define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) | 14 | #define SIM1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00018000) |
| 112 | #define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000) | 15 | #define IIM_BASE_ADDR (SPBA0_BASE_ADDR + 0x0001C000) |
| 113 | #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) | ||
| 114 | #define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) | ||
| 115 | #define MSHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) | ||
| 116 | #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) | ||
| 117 | 16 | ||
| 118 | /* | ||
| 119 | * AIPS 2 | ||
| 120 | */ | ||
| 121 | #define AIPS2_BASE_ADDR 0x53F00000 | ||
| 122 | #define AIPS2_BASE_ADDR_VIRT 0xFC200000 | ||
| 123 | #define AIPS2_SIZE SZ_1M | ||
| 124 | #define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) | ||
| 125 | #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) | 17 | #define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) |
| 126 | #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) | 18 | #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008C000) |
| 127 | #define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) | ||
| 128 | #define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) | ||
| 129 | #define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) | ||
| 130 | #define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) | ||
| 131 | #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) | ||
| 132 | #define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000) | 19 | #define SCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AE000) |
| 133 | #define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000) | 20 | #define SMN_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AF000) |
| 134 | #define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) | ||
| 135 | #define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) | ||
| 136 | #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) | ||
| 137 | #define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) | 21 | #define MPEG4_ENC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) |
| 138 | #define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) | ||
| 139 | #define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) | ||
| 140 | #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000) | ||
| 141 | #define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) | ||
| 142 | #define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) | ||
| 143 | #define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) | ||
| 144 | #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) | ||
| 145 | |||
| 146 | /* | ||
| 147 | * ROMP and AVIC | ||
| 148 | */ | ||
| 149 | #define ROMP_BASE_ADDR 0x60000000 | ||
| 150 | #define ROMP_BASE_ADDR_VIRT 0xFC500000 | ||
| 151 | #define ROMP_SIZE SZ_1M | ||
| 152 | |||
| 153 | #define AVIC_BASE_ADDR 0x68000000 | ||
| 154 | #define AVIC_BASE_ADDR_VIRT 0xFC400000 | ||
| 155 | #define AVIC_SIZE SZ_1M | ||
| 156 | |||
| 157 | /* | ||
| 158 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | ||
| 159 | */ | ||
| 160 | #define X_MEMC_BASE_ADDR 0xB8000000 | ||
| 161 | #define X_MEMC_BASE_ADDR_VIRT 0xFC320000 | ||
| 162 | #define X_MEMC_SIZE SZ_64K | ||
| 163 | 22 | ||
| 164 | #define NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) | 23 | #define MX31_NFC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x0000) |
| 165 | #define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) | ||
| 166 | #define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) | ||
| 167 | #define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) | ||
| 168 | #define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) | ||
| 169 | #define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR | ||
| 170 | 24 | ||
| 171 | /* | ||
| 172 | * Memory regions and CS | ||
| 173 | */ | ||
| 174 | #define IPU_MEM_BASE_ADDR 0x70000000 | ||
| 175 | #define CSD0_BASE_ADDR 0x80000000 | ||
| 176 | #define CSD1_BASE_ADDR 0x90000000 | ||
| 177 | #define CS0_BASE_ADDR 0xA0000000 | ||
| 178 | #define CS1_BASE_ADDR 0xA8000000 | ||
| 179 | #define CS2_BASE_ADDR 0xB0000000 | ||
| 180 | #define CS3_BASE_ADDR 0xB2000000 | ||
| 181 | |||
| 182 | #define CS4_BASE_ADDR 0xB4000000 | ||
| 183 | #define CS4_BASE_ADDR_VIRT 0xF4000000 | ||
| 184 | #define CS4_SIZE SZ_32M | ||
| 185 | |||
| 186 | #define CS5_BASE_ADDR 0xB6000000 | ||
| 187 | #define PCMCIA_MEM_BASE_ADDR 0xBC000000 | ||
| 188 | |||
| 189 | /*! | ||
| 190 | * This macro defines the physical to virtual address mapping for all the | ||
| 191 | * peripheral modules. It is used by passing in the physical address as x | ||
| 192 | * and returning the virtual address. If the physical address is not mapped, | ||
| 193 | * it returns 0xDEADBEEF | ||
| 194 | */ | ||
| 195 | #define IO_ADDRESS(x) \ | ||
| 196 | (void __iomem *) \ | ||
| 197 | (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\ | ||
| 198 | ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\ | ||
| 199 | ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ | ||
| 200 | ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\ | ||
| 201 | ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\ | ||
| 202 | ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\ | ||
| 203 | ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\ | ||
| 204 | ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\ | ||
| 205 | ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\ | ||
| 206 | 0xDEADBEEF) | ||
| 207 | |||
| 208 | /* | ||
| 209 | * define the address mapping macros: in physical address order | ||
| 210 | */ | ||
| 211 | |||
| 212 | #define IRAM_IO_ADDRESS(x) \ | ||
| 213 | (((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT) | ||
| 214 | |||
| 215 | #define L2CC_IO_ADDRESS(x) \ | ||
| 216 | (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT) | ||
| 217 | |||
| 218 | #define AIPS1_IO_ADDRESS(x) \ | ||
| 219 | (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) | ||
| 220 | |||
| 221 | #define SPBA0_IO_ADDRESS(x) \ | ||
| 222 | (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT) | ||
| 223 | |||
| 224 | #define AIPS2_IO_ADDRESS(x) \ | ||
| 225 | (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) | ||
| 226 | |||
| 227 | #define ROMP_IO_ADDRESS(x) \ | ||
| 228 | (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT) | ||
| 229 | |||
| 230 | #define AVIC_IO_ADDRESS(x) \ | ||
| 231 | (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT) | ||
| 232 | |||
| 233 | #define CS4_IO_ADDRESS(x) \ | ||
| 234 | (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) | ||
| 235 | |||
| 236 | #define X_MEMC_IO_ADDRESS(x) \ | ||
| 237 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 238 | |||
| 239 | #define PCMCIA_IO_ADDRESS(x) \ | ||
| 240 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 241 | |||
| 242 | /* | ||
| 243 | * Interrupt numbers | ||
| 244 | */ | ||
| 245 | #define MXC_INT_PEN_ADS7843 0 | ||
| 246 | #define MXC_INT_RESV1 1 | ||
| 247 | #define MXC_INT_CS8900A 2 | ||
| 248 | #define MXC_INT_I2C3 3 | ||
| 249 | #define MXC_INT_I2C2 4 | ||
| 250 | #define MXC_INT_MPEG4_ENCODER 5 | 25 | #define MXC_INT_MPEG4_ENCODER 5 |
| 251 | #define MXC_INT_RTIC 6 | ||
| 252 | #define MXC_INT_FIRI 7 | 26 | #define MXC_INT_FIRI 7 |
| 253 | #define MXC_INT_MMC_SDHC2 8 | 27 | #define MX31_INT_MMC_SDHC2 8 |
| 254 | #define MXC_INT_MMC_SDHC1 9 | 28 | #define MXC_INT_MMC_SDHC1 9 |
| 255 | #define MXC_INT_I2C 10 | 29 | #define MX31_INT_SSI2 11 |
| 256 | #define MXC_INT_SSI2 11 | 30 | #define MX31_INT_SSI1 12 |
| 257 | #define MXC_INT_SSI1 12 | ||
| 258 | #define MXC_INT_CSPI2 13 | ||
| 259 | #define MXC_INT_CSPI1 14 | ||
| 260 | #define MXC_INT_ATA 15 | ||
| 261 | #define MXC_INT_MBX 16 | 31 | #define MXC_INT_MBX 16 |
| 262 | #define MXC_INT_CSPI3 17 | 32 | #define MXC_INT_CSPI3 17 |
| 263 | #define MXC_INT_UART3 18 | ||
| 264 | #define MXC_INT_IIM 19 | ||
| 265 | #define MXC_INT_SIM2 20 | 33 | #define MXC_INT_SIM2 20 |
| 266 | #define MXC_INT_SIM1 21 | 34 | #define MXC_INT_SIM1 21 |
| 267 | #define MXC_INT_RNGA 22 | 35 | #define MXC_INT_CCM_DVFS 31 |
| 268 | #define MXC_INT_EVTMON 23 | ||
| 269 | #define MXC_INT_KPP 24 | ||
| 270 | #define MXC_INT_RTC 25 | ||
| 271 | #define MXC_INT_PWM 26 | ||
| 272 | #define MXC_INT_EPIT2 27 | ||
| 273 | #define MXC_INT_EPIT1 28 | ||
| 274 | #define MXC_INT_GPT 29 | ||
| 275 | #define MXC_INT_RESV30 30 | ||
| 276 | #define MXC_INT_RESV31 31 | ||
| 277 | #define MXC_INT_UART2 32 | ||
| 278 | #define MXC_INT_NANDFC 33 | ||
| 279 | #define MXC_INT_SDMA 34 | ||
| 280 | #define MXC_INT_USB1 35 | 36 | #define MXC_INT_USB1 35 |
| 281 | #define MXC_INT_USB2 36 | 37 | #define MXC_INT_USB2 36 |
| 282 | #define MXC_INT_USB3 37 | 38 | #define MXC_INT_USB3 37 |
| 283 | #define MXC_INT_USB4 38 | 39 | #define MXC_INT_USB4 38 |
| 284 | #define MXC_INT_MSHC1 39 | ||
| 285 | #define MXC_INT_MSHC2 40 | 40 | #define MXC_INT_MSHC2 40 |
| 286 | #define MXC_INT_IPU_ERR 41 | ||
| 287 | #define MXC_INT_IPU_SYN 42 | ||
| 288 | #define MXC_INT_RESV43 43 | ||
| 289 | #define MXC_INT_RESV44 44 | ||
| 290 | #define MXC_INT_UART1 45 | ||
| 291 | #define MXC_INT_UART4 46 | 41 | #define MXC_INT_UART4 46 |
| 292 | #define MXC_INT_UART5 47 | 42 | #define MXC_INT_UART5 47 |
| 293 | #define MXC_INT_ECT 48 | ||
| 294 | #define MXC_INT_SCC_SCM 49 | ||
| 295 | #define MXC_INT_SCC_SMN 50 | ||
| 296 | #define MXC_INT_GPIO2 51 | ||
| 297 | #define MXC_INT_GPIO1 52 | ||
| 298 | #define MXC_INT_CCM 53 | 43 | #define MXC_INT_CCM 53 |
| 299 | #define MXC_INT_PCMCIA 54 | 44 | #define MXC_INT_PCMCIA 54 |
| 300 | #define MXC_INT_WDOG 55 | ||
| 301 | #define MXC_INT_GPIO3 56 | ||
| 302 | #define MXC_INT_RESV57 57 | ||
| 303 | #define MXC_INT_EXT_POWER 58 | ||
| 304 | #define MXC_INT_EXT_TEMPER 59 | ||
| 305 | #define MXC_INT_EXT_SENSOR60 60 | ||
| 306 | #define MXC_INT_EXT_SENSOR61 61 | ||
| 307 | #define MXC_INT_EXT_WDOG 62 | ||
| 308 | #define MXC_INT_EXT_TV 63 | ||
| 309 | |||
| 310 | #define PROD_SIGNATURE 0x1 /* For MX31 */ | ||
| 311 | |||
| 312 | /* silicon revisions specific to i.MX31 */ | ||
| 313 | #define CHIP_REV_1_0 0x10 | ||
| 314 | #define CHIP_REV_1_1 0x11 | ||
| 315 | #define CHIP_REV_1_2 0x12 | ||
| 316 | #define CHIP_REV_1_3 0x13 | ||
| 317 | #define CHIP_REV_2_0 0x20 | ||
| 318 | #define CHIP_REV_2_1 0x21 | ||
| 319 | #define CHIP_REV_2_2 0x22 | ||
| 320 | #define CHIP_REV_2_3 0x23 | ||
| 321 | #define CHIP_REV_3_0 0x30 | ||
| 322 | #define CHIP_REV_3_1 0x31 | ||
| 323 | #define CHIP_REV_3_2 0x32 | ||
| 324 | |||
| 325 | #define SYSTEM_REV_MIN CHIP_REV_1_0 | ||
| 326 | #define SYSTEM_REV_NUM 3 | ||
| 327 | |||
| 328 | /* gpio and gpio based interrupt handling */ | ||
| 329 | #define GPIO_DR 0x00 | ||
| 330 | #define GPIO_GDIR 0x04 | ||
| 331 | #define GPIO_PSR 0x08 | ||
| 332 | #define GPIO_ICR1 0x0C | ||
| 333 | #define GPIO_ICR2 0x10 | ||
| 334 | #define GPIO_IMR 0x14 | ||
| 335 | #define GPIO_ISR 0x18 | ||
| 336 | #define GPIO_INT_LOW_LEV 0x0 | ||
| 337 | #define GPIO_INT_HIGH_LEV 0x1 | ||
| 338 | #define GPIO_INT_RISE_EDGE 0x2 | ||
| 339 | #define GPIO_INT_FALL_EDGE 0x3 | ||
| 340 | #define GPIO_INT_NONE 0x4 | ||
| 341 | |||
| 342 | /* Mandatory defines used globally */ | ||
| 343 | |||
| 344 | /* this CPU supports up to 96 GPIOs */ | ||
| 345 | #define ARCH_NR_GPIOS 96 | ||
| 346 | |||
| 347 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) | ||
| 348 | |||
| 349 | /* this is a i.MX31 CPU */ | ||
| 350 | #define cpu_is_mx31() (1) | ||
| 351 | |||
| 352 | extern unsigned int system_rev; | ||
| 353 | |||
| 354 | static inline int mx31_revision(void) | ||
| 355 | { | ||
| 356 | return system_rev; | ||
| 357 | } | ||
| 358 | #endif | ||
| 359 | 45 | ||
| 360 | #endif /* __ASM_ARCH_MXC_MX31_H__ */ | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h new file mode 100644 index 000000000000..6465fefb42e3 --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx35.h | |||
| @@ -0,0 +1,29 @@ | |||
| 1 | /* | ||
| 2 | * IRAM | ||
| 3 | */ | ||
| 4 | #define MX35_IRAM_BASE_ADDR 0x10000000 /* internal ram */ | ||
| 5 | #define MX35_IRAM_SIZE SZ_128K | ||
| 6 | |||
| 7 | #define MXC_FEC_BASE_ADDR 0x50038000 | ||
| 8 | #define MX35_NFC_BASE_ADDR 0xBB000000 | ||
| 9 | |||
| 10 | /* | ||
| 11 | * Interrupt numbers | ||
| 12 | */ | ||
| 13 | #define MXC_INT_OWIRE 2 | ||
| 14 | #define MX35_INT_MMC_SDHC1 7 | ||
| 15 | #define MXC_INT_MMC_SDHC2 8 | ||
| 16 | #define MXC_INT_MMC_SDHC3 9 | ||
| 17 | #define MX35_INT_SSI1 11 | ||
| 18 | #define MX35_INT_SSI2 12 | ||
| 19 | #define MXC_INT_GPU2D 16 | ||
| 20 | #define MXC_INT_ASRC 17 | ||
| 21 | #define MXC_INT_USBHS 35 | ||
| 22 | #define MXC_INT_USBOTG 37 | ||
| 23 | #define MXC_INT_ESAI 40 | ||
| 24 | #define MXC_INT_CAN1 43 | ||
| 25 | #define MXC_INT_CAN2 44 | ||
| 26 | #define MXC_INT_MLB 46 | ||
| 27 | #define MXC_INT_SPDIF 47 | ||
| 28 | #define MXC_INT_FEC 57 | ||
| 29 | |||
diff --git a/arch/arm/plat-mxc/include/mach/mx3fb.h b/arch/arm/plat-mxc/include/mach/mx3fb.h index e391a76ca87d..ac24c5c4bc83 100644 --- a/arch/arm/plat-mxc/include/mach/mx3fb.h +++ b/arch/arm/plat-mxc/include/mach/mx3fb.h | |||
| @@ -14,25 +14,25 @@ | |||
| 14 | #include <linux/fb.h> | 14 | #include <linux/fb.h> |
| 15 | 15 | ||
| 16 | /* Proprietary FB_SYNC_ flags */ | 16 | /* Proprietary FB_SYNC_ flags */ |
| 17 | #define FB_SYNC_OE_ACT_HIGH 0x80000000 | 17 | #define FB_SYNC_OE_ACT_HIGH 0x80000000 |
| 18 | #define FB_SYNC_CLK_INVERT 0x40000000 | 18 | #define FB_SYNC_CLK_INVERT 0x40000000 |
| 19 | #define FB_SYNC_DATA_INVERT 0x20000000 | 19 | #define FB_SYNC_DATA_INVERT 0x20000000 |
| 20 | #define FB_SYNC_CLK_IDLE_EN 0x10000000 | 20 | #define FB_SYNC_CLK_IDLE_EN 0x10000000 |
| 21 | #define FB_SYNC_SHARP_MODE 0x08000000 | 21 | #define FB_SYNC_SHARP_MODE 0x08000000 |
| 22 | #define FB_SYNC_SWAP_RGB 0x04000000 | 22 | #define FB_SYNC_SWAP_RGB 0x04000000 |
| 23 | #define FB_SYNC_CLK_SEL_EN 0x02000000 | 23 | #define FB_SYNC_CLK_SEL_EN 0x02000000 |
| 24 | 24 | ||
| 25 | /** | 25 | /** |
| 26 | * struct mx3fb_platform_data - mx3fb platform data | 26 | * struct mx3fb_platform_data - mx3fb platform data |
| 27 | * | 27 | * |
| 28 | * @dma_dev: pointer to the dma-device, used for dma-slave connection | 28 | * @dma_dev: pointer to the dma-device, used for dma-slave connection |
| 29 | * @mode: pointer to a platform-provided per mxc_register_fb() videomode | 29 | * @mode: pointer to a platform-provided per mxc_register_fb() videomode |
| 30 | */ | 30 | */ |
| 31 | struct mx3fb_platform_data { | 31 | struct mx3fb_platform_data { |
| 32 | struct device *dma_dev; | 32 | struct device *dma_dev; |
| 33 | const char *name; | 33 | const char *name; |
| 34 | const struct fb_videomode *mode; | 34 | const struct fb_videomode *mode; |
| 35 | int num_modes; | 35 | int num_modes; |
| 36 | }; | 36 | }; |
| 37 | 37 | ||
| 38 | #endif | 38 | #endif |
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h new file mode 100644 index 000000000000..3878c6085d5c --- /dev/null +++ b/arch/arm/plat-mxc/include/mach/mx3x.h | |||
| @@ -0,0 +1,290 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | ||
| 3 | */ | ||
| 4 | |||
| 5 | /* | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __ASM_ARCH_MXC_MX31_H__ | ||
| 12 | #define __ASM_ARCH_MXC_MX31_H__ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_MXC_HARDWARE_H__ | ||
| 15 | #error "Do not include directly." | ||
| 16 | #endif | ||
| 17 | |||
| 18 | /* | ||
| 19 | * MX31 memory map: | ||
| 20 | * | ||
| 21 | * Virt Phys Size What | ||
| 22 | * --------------------------------------------------------------------------- | ||
| 23 | * FC000000 43F00000 1M AIPS 1 | ||
| 24 | * FC100000 50000000 1M SPBA | ||
| 25 | * FC200000 53F00000 1M AIPS 2 | ||
| 26 | * FC500000 60000000 128M ROMPATCH | ||
| 27 | * FC400000 68000000 128M AVIC | ||
| 28 | * 70000000 256M IPU (MAX M2) | ||
| 29 | * 80000000 256M CSD0 SDRAM/DDR | ||
| 30 | * 90000000 256M CSD1 SDRAM/DDR | ||
| 31 | * A0000000 128M CS0 Flash | ||
| 32 | * A8000000 128M CS1 Flash | ||
| 33 | * B0000000 32M CS2 | ||
| 34 | * B2000000 32M CS3 | ||
| 35 | * F4000000 B4000000 32M CS4 | ||
| 36 | * B6000000 32M CS5 | ||
| 37 | * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers | ||
| 38 | * C0000000 64M PCMCIA/CF | ||
| 39 | */ | ||
| 40 | |||
| 41 | #define CS0_BASE_ADDR 0xA0000000 | ||
| 42 | #define CS1_BASE_ADDR 0xA8000000 | ||
| 43 | #define CS2_BASE_ADDR 0xB0000000 | ||
| 44 | #define CS3_BASE_ADDR 0xB2000000 | ||
| 45 | |||
| 46 | #define CS4_BASE_ADDR 0xB4000000 | ||
| 47 | #define CS4_BASE_ADDR_VIRT 0xF4000000 | ||
| 48 | #define CS4_SIZE SZ_32M | ||
| 49 | |||
| 50 | #define CS5_BASE_ADDR 0xB6000000 | ||
| 51 | #define PCMCIA_MEM_BASE_ADDR 0xBC000000 | ||
| 52 | |||
| 53 | /* | ||
| 54 | * L2CC | ||
| 55 | */ | ||
| 56 | #define L2CC_BASE_ADDR 0x30000000 | ||
| 57 | #define L2CC_SIZE SZ_1M | ||
| 58 | |||
| 59 | /* | ||
| 60 | * AIPS 1 | ||
| 61 | */ | ||
| 62 | #define AIPS1_BASE_ADDR 0x43F00000 | ||
| 63 | #define AIPS1_BASE_ADDR_VIRT 0xFC000000 | ||
| 64 | #define AIPS1_SIZE SZ_1M | ||
| 65 | |||
| 66 | #define MAX_BASE_ADDR (AIPS1_BASE_ADDR + 0x00004000) | ||
| 67 | #define EVTMON_BASE_ADDR (AIPS1_BASE_ADDR + 0x00008000) | ||
| 68 | #define CLKCTL_BASE_ADDR (AIPS1_BASE_ADDR + 0x0000C000) | ||
| 69 | #define ETB_SLOT4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00010000) | ||
| 70 | #define ETB_SLOT5_BASE_ADDR (AIPS1_BASE_ADDR + 0x00014000) | ||
| 71 | #define ECT_CTIO_BASE_ADDR (AIPS1_BASE_ADDR + 0x00018000) | ||
| 72 | #define I2C_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) | ||
| 73 | #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) | ||
| 74 | #define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) | ||
| 75 | #define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) | ||
| 76 | #define I2C2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) | ||
| 77 | #define OWIRE_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) | ||
| 78 | #define SSI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) | ||
| 79 | #define CSPI1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) | ||
| 80 | #define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) | ||
| 81 | #define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) | ||
| 82 | #define ECT_IP1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) | ||
| 83 | #define ECT_IP2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) | ||
| 84 | |||
| 85 | /* | ||
| 86 | * SPBA global module enabled #0 | ||
| 87 | */ | ||
| 88 | #define SPBA0_BASE_ADDR 0x50000000 | ||
| 89 | #define SPBA0_BASE_ADDR_VIRT 0xFC100000 | ||
| 90 | #define SPBA0_SIZE SZ_1M | ||
| 91 | |||
| 92 | #define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) | ||
| 93 | #define CSPI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) | ||
| 94 | #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) | ||
| 95 | #define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) | ||
| 96 | #define MSHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) | ||
| 97 | #define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) | ||
| 98 | |||
| 99 | /* | ||
| 100 | * AIPS 2 | ||
| 101 | */ | ||
| 102 | #define AIPS2_BASE_ADDR 0x53F00000 | ||
| 103 | #define AIPS2_BASE_ADDR_VIRT 0xFC200000 | ||
| 104 | #define AIPS2_SIZE SZ_1M | ||
| 105 | #define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) | ||
| 106 | #define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) | ||
| 107 | #define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) | ||
| 108 | #define EPIT2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) | ||
| 109 | #define GPIO3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) | ||
| 110 | #define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) | ||
| 111 | #define RNGA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) | ||
| 112 | #define IPU_CTRL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) | ||
| 113 | #define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) | ||
| 114 | #define GPIO1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) | ||
| 115 | #define GPIO2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) | ||
| 116 | #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D4000) | ||
| 117 | #define RTC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) | ||
| 118 | #define WDOG_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) | ||
| 119 | #define PWM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) | ||
| 120 | #define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) | ||
| 121 | |||
| 122 | /* | ||
| 123 | * ROMP and AVIC | ||
| 124 | */ | ||
| 125 | #define ROMP_BASE_ADDR 0x60000000 | ||
| 126 | #define ROMP_BASE_ADDR_VIRT 0xFC500000 | ||
| 127 | #define ROMP_SIZE SZ_1M | ||
| 128 | |||
| 129 | #define AVIC_BASE_ADDR 0x68000000 | ||
| 130 | #define AVIC_BASE_ADDR_VIRT 0xFC400000 | ||
| 131 | #define AVIC_SIZE SZ_1M | ||
| 132 | |||
| 133 | /* | ||
| 134 | * NAND, SDRAM, WEIM, M3IF, EMI controllers | ||
| 135 | */ | ||
| 136 | #define X_MEMC_BASE_ADDR 0xB8000000 | ||
| 137 | #define X_MEMC_BASE_ADDR_VIRT 0xFC320000 | ||
| 138 | #define X_MEMC_SIZE SZ_64K | ||
| 139 | |||
| 140 | #define ESDCTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000) | ||
| 141 | #define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000) | ||
| 142 | #define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000) | ||
| 143 | #define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000) | ||
| 144 | #define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR | ||
| 145 | |||
| 146 | /* | ||
| 147 | * Memory regions and CS | ||
| 148 | */ | ||
| 149 | #define IPU_MEM_BASE_ADDR 0x70000000 | ||
| 150 | #define CSD0_BASE_ADDR 0x80000000 | ||
| 151 | #define CSD1_BASE_ADDR 0x90000000 | ||
| 152 | |||
| 153 | /*! | ||
| 154 | * This macro defines the physical to virtual address mapping for all the | ||
| 155 | * peripheral modules. It is used by passing in the physical address as x | ||
| 156 | * and returning the virtual address. If the physical address is not mapped, | ||
| 157 | * it returns 0xDEADBEEF | ||
| 158 | */ | ||
| 159 | #define IO_ADDRESS(x) \ | ||
| 160 | (void __force __iomem *) \ | ||
| 161 | (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ | ||
| 162 | ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\ | ||
| 163 | ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\ | ||
| 164 | ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\ | ||
| 165 | ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\ | ||
| 166 | ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\ | ||
| 167 | ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\ | ||
| 168 | 0xDEADBEEF) | ||
| 169 | |||
| 170 | /* | ||
| 171 | * define the address mapping macros: in physical address order | ||
| 172 | */ | ||
| 173 | #define L2CC_IO_ADDRESS(x) \ | ||
| 174 | (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT) | ||
| 175 | |||
| 176 | #define AIPS1_IO_ADDRESS(x) \ | ||
| 177 | (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT) | ||
| 178 | |||
| 179 | #define SPBA0_IO_ADDRESS(x) \ | ||
| 180 | (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT) | ||
| 181 | |||
| 182 | #define AIPS2_IO_ADDRESS(x) \ | ||
| 183 | (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT) | ||
| 184 | |||
| 185 | #define ROMP_IO_ADDRESS(x) \ | ||
| 186 | (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT) | ||
| 187 | |||
| 188 | #define AVIC_IO_ADDRESS(x) \ | ||
| 189 | (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT) | ||
| 190 | |||
| 191 | #define CS4_IO_ADDRESS(x) \ | ||
| 192 | (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT) | ||
| 193 | |||
| 194 | #define X_MEMC_IO_ADDRESS(x) \ | ||
| 195 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 196 | |||
| 197 | #define PCMCIA_IO_ADDRESS(x) \ | ||
| 198 | (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT) | ||
| 199 | |||
| 200 | /* | ||
| 201 | * Interrupt numbers | ||
| 202 | */ | ||
| 203 | #define MXC_INT_I2C3 3 | ||
| 204 | #define MXC_INT_I2C2 4 | ||
| 205 | #define MXC_INT_RTIC 6 | ||
| 206 | #define MXC_INT_I2C 10 | ||
| 207 | #define MXC_INT_CSPI2 13 | ||
| 208 | #define MXC_INT_CSPI1 14 | ||
| 209 | #define MXC_INT_ATA 15 | ||
| 210 | #define MXC_INT_UART3 18 | ||
| 211 | #define MXC_INT_IIM 19 | ||
| 212 | #define MXC_INT_RNGA 22 | ||
| 213 | #define MXC_INT_EVTMON 23 | ||
| 214 | #define MXC_INT_KPP 24 | ||
| 215 | #define MXC_INT_RTC 25 | ||
| 216 | #define MXC_INT_PWM 26 | ||
| 217 | #define MXC_INT_EPIT2 27 | ||
| 218 | #define MXC_INT_EPIT1 28 | ||
| 219 | #define MXC_INT_GPT 29 | ||
| 220 | #define MXC_INT_POWER_FAIL 30 | ||
| 221 | #define MXC_INT_UART2 32 | ||
| 222 | #define MXC_INT_NANDFC 33 | ||
| 223 | #define MXC_INT_SDMA 34 | ||
| 224 | #define MXC_INT_MSHC1 39 | ||
| 225 | #define MXC_INT_IPU_ERR 41 | ||
| 226 | #define MXC_INT_IPU_SYN 42 | ||
| 227 | #define MXC_INT_UART1 45 | ||
| 228 | #define MXC_INT_ECT 48 | ||
| 229 | #define MXC_INT_SCC_SCM 49 | ||
| 230 | #define MXC_INT_SCC_SMN 50 | ||
| 231 | #define MXC_INT_GPIO2 51 | ||
| 232 | #define MXC_INT_GPIO1 52 | ||
| 233 | #define MXC_INT_WDOG 55 | ||
| 234 | #define MXC_INT_GPIO3 56 | ||
| 235 | #define MXC_INT_EXT_POWER 58 | ||
| 236 | #define MXC_INT_EXT_TEMPER 59 | ||
| 237 | #define MXC_INT_EXT_SENSOR60 60 | ||
| 238 | #define MXC_INT_EXT_SENSOR61 61 | ||
| 239 | #define MXC_INT_EXT_WDOG 62 | ||
| 240 | #define MXC_INT_EXT_TV 63 | ||
| 241 | |||
| 242 | #define PROD_SIGNATURE 0x1 /* For MX31 */ | ||
| 243 | |||
| 244 | /* silicon revisions specific to i.MX31 */ | ||
| 245 | #define CHIP_REV_1_0 0x10 | ||
| 246 | #define CHIP_REV_1_1 0x11 | ||
| 247 | #define CHIP_REV_1_2 0x12 | ||
| 248 | #define CHIP_REV_1_3 0x13 | ||
| 249 | #define CHIP_REV_2_0 0x20 | ||
| 250 | #define CHIP_REV_2_1 0x21 | ||
| 251 | #define CHIP_REV_2_2 0x22 | ||
| 252 | #define CHIP_REV_2_3 0x23 | ||
| 253 | #define CHIP_REV_3_0 0x30 | ||
| 254 | #define CHIP_REV_3_1 0x31 | ||
| 255 | #define CHIP_REV_3_2 0x32 | ||
| 256 | |||
| 257 | #define SYSTEM_REV_MIN CHIP_REV_1_0 | ||
| 258 | #define SYSTEM_REV_NUM 3 | ||
| 259 | |||
| 260 | /* gpio and gpio based interrupt handling */ | ||
| 261 | #define GPIO_DR 0x00 | ||
| 262 | #define GPIO_GDIR 0x04 | ||
| 263 | #define GPIO_PSR 0x08 | ||
| 264 | #define GPIO_ICR1 0x0C | ||
| 265 | #define GPIO_ICR2 0x10 | ||
| 266 | #define GPIO_IMR 0x14 | ||
| 267 | #define GPIO_ISR 0x18 | ||
| 268 | #define GPIO_INT_LOW_LEV 0x0 | ||
| 269 | #define GPIO_INT_HIGH_LEV 0x1 | ||
| 270 | #define GPIO_INT_RISE_EDGE 0x2 | ||
| 271 | #define GPIO_INT_FALL_EDGE 0x3 | ||
| 272 | #define GPIO_INT_NONE 0x4 | ||
| 273 | |||
| 274 | /* Mandatory defines used globally */ | ||
| 275 | |||
| 276 | /* this CPU supports up to 96 GPIOs */ | ||
| 277 | #define ARCH_NR_GPIOS 96 | ||
| 278 | |||
| 279 | #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) | ||
| 280 | |||
| 281 | extern unsigned int system_rev; | ||
| 282 | |||
| 283 | static inline int mx31_revision(void) | ||
| 284 | { | ||
| 285 | return system_rev; | ||
| 286 | } | ||
| 287 | #endif | ||
| 288 | |||
| 289 | #endif /* __ASM_ARCH_MXC_MX31_H__ */ | ||
| 290 | |||
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index f6caab062131..5fa2a07f4eaf 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h | |||
| @@ -24,13 +24,74 @@ | |||
| 24 | #error "Do not include directly." | 24 | #error "Do not include directly." |
| 25 | #endif | 25 | #endif |
| 26 | 26 | ||
| 27 | /* clean up all things that are not used */ | 27 | #define MXC_CPU_MX1 1 |
| 28 | #ifndef CONFIG_ARCH_MX3 | 28 | #define MXC_CPU_MX21 21 |
| 29 | # define cpu_is_mx31() (0) | 29 | #define MXC_CPU_MX27 27 |
| 30 | #define MXC_CPU_MX31 31 | ||
| 31 | #define MXC_CPU_MX35 35 | ||
| 32 | |||
| 33 | #ifndef __ASSEMBLY__ | ||
| 34 | extern unsigned int __mxc_cpu_type; | ||
| 35 | #endif | ||
| 36 | |||
| 37 | #ifdef CONFIG_ARCH_MX1 | ||
| 38 | # ifdef mxc_cpu_type | ||
| 39 | # undef mxc_cpu_type | ||
| 40 | # define mxc_cpu_type __mxc_cpu_type | ||
| 41 | # else | ||
| 42 | # define mxc_cpu_type MXC_CPU_MX1 | ||
| 43 | # endif | ||
| 44 | # define cpu_is_mx1() (mxc_cpu_type == MXC_CPU_MX1) | ||
| 45 | #else | ||
| 46 | # define cpu_is_mx1() (0) | ||
| 47 | #endif | ||
| 48 | |||
| 49 | #ifdef CONFIG_MACH_MX21 | ||
| 50 | # ifdef mxc_cpu_type | ||
| 51 | # undef mxc_cpu_type | ||
| 52 | # define mxc_cpu_type __mxc_cpu_type | ||
| 53 | # else | ||
| 54 | # define mxc_cpu_type MXC_CPU_MX21 | ||
| 55 | # endif | ||
| 56 | # define cpu_is_mx21() (mxc_cpu_type == MXC_CPU_MX21) | ||
| 57 | #else | ||
| 58 | # define cpu_is_mx21() (0) | ||
| 30 | #endif | 59 | #endif |
| 31 | 60 | ||
| 32 | #ifndef CONFIG_MACH_MX27 | 61 | #ifdef CONFIG_MACH_MX27 |
| 33 | # define cpu_is_mx27() (0) | 62 | # ifdef mxc_cpu_type |
| 63 | # undef mxc_cpu_type | ||
| 64 | # define mxc_cpu_type __mxc_cpu_type | ||
| 65 | # else | ||
| 66 | # define mxc_cpu_type MXC_CPU_MX27 | ||
| 67 | # endif | ||
| 68 | # define cpu_is_mx27() (mxc_cpu_type == MXC_CPU_MX27) | ||
| 69 | #else | ||
| 70 | # define cpu_is_mx27() (0) | ||
| 71 | #endif | ||
| 72 | |||
| 73 | #ifdef CONFIG_ARCH_MX31 | ||
| 74 | # ifdef mxc_cpu_type | ||
| 75 | # undef mxc_cpu_type | ||
| 76 | # define mxc_cpu_type __mxc_cpu_type | ||
| 77 | # else | ||
| 78 | # define mxc_cpu_type MXC_CPU_MX31 | ||
| 79 | # endif | ||
| 80 | # define cpu_is_mx31() (mxc_cpu_type == MXC_CPU_MX31) | ||
| 81 | #else | ||
| 82 | # define cpu_is_mx31() (0) | ||
| 83 | #endif | ||
| 84 | |||
| 85 | #ifdef CONFIG_ARCH_MX35 | ||
| 86 | # ifdef mxc_cpu_type | ||
| 87 | # undef mxc_cpu_type | ||
| 88 | # define mxc_cpu_type __mxc_cpu_type | ||
| 89 | # else | ||
| 90 | # define mxc_cpu_type MXC_CPU_MX35 | ||
| 91 | # endif | ||
| 92 | # define cpu_is_mx35() (mxc_cpu_type == MXC_CPU_MX35) | ||
| 93 | #else | ||
| 94 | # define cpu_is_mx35() (0) | ||
| 34 | #endif | 95 | #endif |
| 35 | 96 | ||
| 36 | #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) | 97 | #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2) |
| @@ -39,4 +100,7 @@ | |||
| 39 | #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) | 100 | #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) |
| 40 | #endif | 101 | #endif |
| 41 | 102 | ||
| 103 | #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) | ||
| 104 | #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) | ||
| 105 | |||
| 42 | #endif /* __ASM_ARCH_MXC_H__ */ | 106 | #endif /* __ASM_ARCH_MXC_H__ */ |
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index bbfc37465fc5..cd03ebaa49bc 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h | |||
| @@ -26,7 +26,7 @@ static inline void arch_idle(void) | |||
| 26 | cpu_do_idle(); | 26 | cpu_do_idle(); |
| 27 | } | 27 | } |
| 28 | 28 | ||
| 29 | static inline void arch_reset(char mode) | 29 | static inline void arch_reset(char mode, const char *cmd) |
| 30 | { | 30 | { |
| 31 | cpu_reset(0); | 31 | cpu_reset(0); |
| 32 | } | 32 | } |
diff --git a/arch/arm/plat-mxc/iomux-mx1-mx2.c b/arch/arm/plat-mxc/iomux-mx1-mx2.c index df6f18395686..a37163ce280b 100644 --- a/arch/arm/plat-mxc/iomux-mx1-mx2.c +++ b/arch/arm/plat-mxc/iomux-mx1-mx2.c | |||
| @@ -32,7 +32,7 @@ | |||
| 32 | 32 | ||
| 33 | #include <mach/hardware.h> | 33 | #include <mach/hardware.h> |
| 34 | #include <asm/mach/map.h> | 34 | #include <asm/mach/map.h> |
| 35 | #include <mach/iomux-mx1-mx2.h> | 35 | #include <mach/iomux.h> |
| 36 | 36 | ||
| 37 | void mxc_gpio_mode(int gpio_mode) | 37 | void mxc_gpio_mode(int gpio_mode) |
| 38 | { | 38 | { |
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c new file mode 100644 index 000000000000..9bffbc507cc2 --- /dev/null +++ b/arch/arm/plat-mxc/pwm.c | |||
| @@ -0,0 +1,300 @@ | |||
| 1 | /* | ||
| 2 | * simple driver for PWM (Pulse Width Modulator) controller | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License version 2 as | ||
| 6 | * published by the Free Software Foundation. | ||
| 7 | * | ||
| 8 | * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com> | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/module.h> | ||
| 12 | #include <linux/kernel.h> | ||
| 13 | #include <linux/platform_device.h> | ||
| 14 | #include <linux/err.h> | ||
| 15 | #include <linux/clk.h> | ||
| 16 | #include <linux/io.h> | ||
| 17 | #include <linux/pwm.h> | ||
| 18 | |||
| 19 | #if defined CONFIG_ARCH_MX1 || defined CONFIG_ARCH_MX21 | ||
| 20 | #define PWM_VER_1 | ||
| 21 | |||
| 22 | #define PWMCR 0x00 /* PWM Control Register */ | ||
| 23 | #define PWMSR 0x04 /* PWM Sample Register */ | ||
| 24 | #define PWMPR 0x08 /* PWM Period Register */ | ||
| 25 | #define PWMCNR 0x0C /* PWM Counter Register */ | ||
| 26 | |||
| 27 | #define PWMCR_HCTR (1 << 18) /* Halfword FIFO Data Swapping */ | ||
| 28 | #define PWMCR_BCTR (1 << 17) /* Byte FIFO Data Swapping */ | ||
| 29 | #define PWMCR_SWR (1 << 16) /* Software Reset */ | ||
| 30 | #define PWMCR_CLKSRC_PERCLK (0 << 15) /* PERCLK Clock Source */ | ||
| 31 | #define PWMCR_CLKSRC_CLK32 (1 << 15) /* 32KHz Clock Source */ | ||
| 32 | #define PWMCR_PRESCALER(x) (((x - 1) & 0x7F) << 8) /* PRESCALER */ | ||
| 33 | #define PWMCR_IRQ (1 << 7) /* Interrupt Request */ | ||
| 34 | #define PWMCR_IRQEN (1 << 6) /* Interrupt Request Enable */ | ||
| 35 | #define PWMCR_FIFOAV (1 << 5) /* FIFO Available */ | ||
| 36 | #define PWMCR_EN (1 << 4) /* Enables/Disables the PWM */ | ||
| 37 | #define PWMCR_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */ | ||
| 38 | #define PWMCR_DIV(x) (((x) & 0x03) << 0) /* Clock divider 2/4/8/16 */ | ||
| 39 | |||
| 40 | #define MAX_DIV (128 * 16) | ||
| 41 | #endif | ||
| 42 | |||
| 43 | #if defined CONFIG_MACH_MX27 || defined CONFIG_ARCH_MX31 | ||
| 44 | #define PWM_VER_2 | ||
| 45 | |||
| 46 | #define PWMCR 0x00 /* PWM Control Register */ | ||
| 47 | #define PWMSR 0x04 /* PWM Status Register */ | ||
| 48 | #define PWMIR 0x08 /* PWM Interrupt Register */ | ||
| 49 | #define PWMSAR 0x0C /* PWM Sample Register */ | ||
| 50 | #define PWMPR 0x10 /* PWM Period Register */ | ||
| 51 | #define PWMCNR 0x14 /* PWM Counter Register */ | ||
| 52 | |||
| 53 | #define PWMCR_EN (1 << 0) /* Enables/Disables the PWM */ | ||
| 54 | #define PWMCR_REPEAT(x) (((x) & 0x03) << 1) /* Sample Repeats */ | ||
| 55 | #define PWMCR_SWR (1 << 3) /* Software Reset */ | ||
| 56 | #define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)/* PRESCALER */ | ||
| 57 | #define PWMCR_CLKSRC(x) (((x) & 0x3) << 16) | ||
| 58 | #define PWMCR_CLKSRC_OFF (0 << 16) | ||
| 59 | #define PWMCR_CLKSRC_IPG (1 << 16) | ||
| 60 | #define PWMCR_CLKSRC_IPG_HIGH (2 << 16) | ||
| 61 | #define PWMCR_CLKSRC_CLK32 (3 << 16) | ||
| 62 | #define PWMCR_POUTC | ||
| 63 | #define PWMCR_HCTR (1 << 20) /* Halfword FIFO Data Swapping */ | ||
| 64 | #define PWMCR_BCTR (1 << 21) /* Byte FIFO Data Swapping */ | ||
| 65 | #define PWMCR_DBGEN (1 << 22) /* Debug Mode */ | ||
| 66 | #define PWMCR_WAITEN (1 << 23) /* Wait Mode */ | ||
| 67 | #define PWMCR_DOZEN (1 << 24) /* Doze Mode */ | ||
| 68 | #define PWMCR_STOPEN (1 << 25) /* Stop Mode */ | ||
| 69 | #define PWMCR_FWM(x) (((x) & 0x3) << 26) /* FIFO Water Mark */ | ||
| 70 | |||
| 71 | #define MAX_DIV 4096 | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */ | ||
| 75 | #define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */ | ||
| 76 | #define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */ | ||
| 77 | |||
| 78 | struct pwm_device { | ||
| 79 | struct list_head node; | ||
| 80 | struct platform_device *pdev; | ||
| 81 | |||
| 82 | const char *label; | ||
| 83 | struct clk *clk; | ||
| 84 | |||
| 85 | int clk_enabled; | ||
| 86 | void __iomem *mmio_base; | ||
| 87 | |||
| 88 | unsigned int use_count; | ||
| 89 | unsigned int pwm_id; | ||
| 90 | }; | ||
| 91 | |||
| 92 | int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) | ||
| 93 | { | ||
| 94 | unsigned long long c; | ||
| 95 | unsigned long period_cycles, duty_cycles, prescale; | ||
| 96 | |||
| 97 | if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) | ||
| 98 | return -EINVAL; | ||
| 99 | |||
| 100 | c = clk_get_rate(pwm->clk); | ||
| 101 | c = c * period_ns; | ||
| 102 | do_div(c, 1000000000); | ||
| 103 | period_cycles = c; | ||
| 104 | |||
| 105 | prescale = period_cycles / 0x10000 + 1; | ||
| 106 | |||
| 107 | period_cycles /= prescale; | ||
| 108 | c = (unsigned long long)period_cycles * duty_ns; | ||
| 109 | do_div(c, period_ns); | ||
| 110 | duty_cycles = c; | ||
| 111 | |||
| 112 | #ifdef PWM_VER_2 | ||
| 113 | writel(duty_cycles, pwm->mmio_base + PWMSAR); | ||
| 114 | writel(period_cycles, pwm->mmio_base + PWMPR); | ||
| 115 | writel(PWMCR_PRESCALER(prescale - 1) | PWMCR_CLKSRC_IPG_HIGH | PWMCR_EN, | ||
| 116 | pwm->mmio_base + PWMCR); | ||
| 117 | #elif defined PWM_VER_1 | ||
| 118 | #error PWM not yet working on MX1 / MX21 | ||
| 119 | #endif | ||
| 120 | |||
| 121 | return 0; | ||
| 122 | } | ||
| 123 | EXPORT_SYMBOL(pwm_config); | ||
| 124 | |||
| 125 | int pwm_enable(struct pwm_device *pwm) | ||
| 126 | { | ||
| 127 | int rc = 0; | ||
| 128 | |||
| 129 | if (!pwm->clk_enabled) { | ||
| 130 | rc = clk_enable(pwm->clk); | ||
| 131 | if (!rc) | ||
| 132 | pwm->clk_enabled = 1; | ||
| 133 | } | ||
| 134 | return rc; | ||
| 135 | } | ||
| 136 | EXPORT_SYMBOL(pwm_enable); | ||
| 137 | |||
| 138 | void pwm_disable(struct pwm_device *pwm) | ||
| 139 | { | ||
| 140 | if (pwm->clk_enabled) { | ||
| 141 | clk_disable(pwm->clk); | ||
| 142 | pwm->clk_enabled = 0; | ||
| 143 | } | ||
| 144 | } | ||
| 145 | EXPORT_SYMBOL(pwm_disable); | ||
| 146 | |||
| 147 | static DEFINE_MUTEX(pwm_lock); | ||
| 148 | static LIST_HEAD(pwm_list); | ||
| 149 | |||
| 150 | struct pwm_device *pwm_request(int pwm_id, const char *label) | ||
| 151 | { | ||
| 152 | struct pwm_device *pwm; | ||
| 153 | int found = 0; | ||
| 154 | |||
| 155 | mutex_lock(&pwm_lock); | ||
| 156 | |||
| 157 | list_for_each_entry(pwm, &pwm_list, node) { | ||
| 158 | if (pwm->pwm_id == pwm_id) { | ||
| 159 | found = 1; | ||
| 160 | break; | ||
| 161 | } | ||
| 162 | } | ||
| 163 | |||
| 164 | if (found) { | ||
| 165 | if (pwm->use_count == 0) { | ||
| 166 | pwm->use_count++; | ||
| 167 | pwm->label = label; | ||
| 168 | } else | ||
| 169 | pwm = ERR_PTR(-EBUSY); | ||
| 170 | } else | ||
| 171 | pwm = ERR_PTR(-ENOENT); | ||
| 172 | |||
| 173 | mutex_unlock(&pwm_lock); | ||
| 174 | return pwm; | ||
| 175 | } | ||
| 176 | EXPORT_SYMBOL(pwm_request); | ||
| 177 | |||
| 178 | void pwm_free(struct pwm_device *pwm) | ||
| 179 | { | ||
| 180 | mutex_lock(&pwm_lock); | ||
| 181 | |||
| 182 | if (pwm->use_count) { | ||
| 183 | pwm->use_count--; | ||
| 184 | pwm->label = NULL; | ||
| 185 | } else | ||
| 186 | pr_warning("PWM device already freed\n"); | ||
| 187 | |||
| 188 | mutex_unlock(&pwm_lock); | ||
| 189 | } | ||
| 190 | EXPORT_SYMBOL(pwm_free); | ||
| 191 | |||
| 192 | static int __devinit mxc_pwm_probe(struct platform_device *pdev) | ||
| 193 | { | ||
| 194 | struct pwm_device *pwm; | ||
| 195 | struct resource *r; | ||
| 196 | int ret = 0; | ||
| 197 | |||
| 198 | pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL); | ||
| 199 | if (pwm == NULL) { | ||
| 200 | dev_err(&pdev->dev, "failed to allocate memory\n"); | ||
| 201 | return -ENOMEM; | ||
| 202 | } | ||
| 203 | |||
| 204 | pwm->clk = clk_get(&pdev->dev, "pwm"); | ||
| 205 | |||
| 206 | if (IS_ERR(pwm->clk)) { | ||
| 207 | ret = PTR_ERR(pwm->clk); | ||
| 208 | goto err_free; | ||
| 209 | } | ||
| 210 | |||
| 211 | pwm->clk_enabled = 0; | ||
| 212 | |||
| 213 | pwm->use_count = 0; | ||
| 214 | pwm->pwm_id = pdev->id; | ||
| 215 | pwm->pdev = pdev; | ||
| 216 | |||
| 217 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 218 | if (r == NULL) { | ||
| 219 | dev_err(&pdev->dev, "no memory resource defined\n"); | ||
| 220 | ret = -ENODEV; | ||
| 221 | goto err_free_clk; | ||
| 222 | } | ||
| 223 | |||
| 224 | r = request_mem_region(r->start, r->end - r->start + 1, pdev->name); | ||
| 225 | if (r == NULL) { | ||
| 226 | dev_err(&pdev->dev, "failed to request memory resource\n"); | ||
| 227 | ret = -EBUSY; | ||
| 228 | goto err_free_clk; | ||
| 229 | } | ||
| 230 | |||
| 231 | pwm->mmio_base = ioremap(r->start, r->end - r->start + 1); | ||
| 232 | if (pwm->mmio_base == NULL) { | ||
| 233 | dev_err(&pdev->dev, "failed to ioremap() registers\n"); | ||
| 234 | ret = -ENODEV; | ||
| 235 | goto err_free_mem; | ||
| 236 | } | ||
| 237 | |||
| 238 | mutex_lock(&pwm_lock); | ||
| 239 | list_add_tail(&pwm->node, &pwm_list); | ||
| 240 | mutex_unlock(&pwm_lock); | ||
| 241 | |||
| 242 | platform_set_drvdata(pdev, pwm); | ||
| 243 | return 0; | ||
| 244 | |||
| 245 | err_free_mem: | ||
| 246 | release_mem_region(r->start, r->end - r->start + 1); | ||
| 247 | err_free_clk: | ||
| 248 | clk_put(pwm->clk); | ||
| 249 | err_free: | ||
| 250 | kfree(pwm); | ||
| 251 | return ret; | ||
| 252 | } | ||
| 253 | |||
| 254 | static int __devexit mxc_pwm_remove(struct platform_device *pdev) | ||
| 255 | { | ||
| 256 | struct pwm_device *pwm; | ||
| 257 | struct resource *r; | ||
| 258 | |||
| 259 | pwm = platform_get_drvdata(pdev); | ||
| 260 | if (pwm == NULL) | ||
| 261 | return -ENODEV; | ||
| 262 | |||
| 263 | mutex_lock(&pwm_lock); | ||
| 264 | list_del(&pwm->node); | ||
| 265 | mutex_unlock(&pwm_lock); | ||
| 266 | |||
| 267 | iounmap(pwm->mmio_base); | ||
| 268 | |||
| 269 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 270 | release_mem_region(r->start, r->end - r->start + 1); | ||
| 271 | |||
| 272 | clk_put(pwm->clk); | ||
| 273 | |||
| 274 | kfree(pwm); | ||
| 275 | return 0; | ||
| 276 | } | ||
| 277 | |||
| 278 | static struct platform_driver mxc_pwm_driver = { | ||
| 279 | .driver = { | ||
| 280 | .name = "mxc_pwm", | ||
| 281 | }, | ||
| 282 | .probe = mxc_pwm_probe, | ||
| 283 | .remove = __devexit_p(mxc_pwm_remove), | ||
| 284 | }; | ||
| 285 | |||
| 286 | static int __init mxc_pwm_init(void) | ||
| 287 | { | ||
| 288 | return platform_driver_register(&mxc_pwm_driver); | ||
| 289 | } | ||
| 290 | arch_initcall(mxc_pwm_init); | ||
| 291 | |||
| 292 | static void __exit mxc_pwm_exit(void) | ||
| 293 | { | ||
| 294 | platform_driver_unregister(&mxc_pwm_driver); | ||
| 295 | } | ||
| 296 | module_exit(mxc_pwm_exit); | ||
| 297 | |||
| 298 | MODULE_LICENSE("GPL v2"); | ||
| 299 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); | ||
| 300 | |||
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c index 758a1293bcfa..ef1b3cd85bd3 100644 --- a/arch/arm/plat-mxc/time.c +++ b/arch/arm/plat-mxc/time.c | |||
| @@ -34,9 +34,6 @@ | |||
| 34 | static struct clock_event_device clockevent_mxc; | 34 | static struct clock_event_device clockevent_mxc; |
| 35 | static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; | 35 | static enum clock_event_mode clockevent_mode = CLOCK_EVT_MODE_UNUSED; |
| 36 | 36 | ||
| 37 | /* clock source for the timer */ | ||
| 38 | static struct clk *timer_clk; | ||
| 39 | |||
| 40 | /* clock source */ | 37 | /* clock source */ |
| 41 | 38 | ||
| 42 | static cycle_t mxc_get_cycles(void) | 39 | static cycle_t mxc_get_cycles(void) |
| @@ -53,13 +50,11 @@ static struct clocksource clocksource_mxc = { | |||
| 53 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 50 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 54 | }; | 51 | }; |
| 55 | 52 | ||
| 56 | static int __init mxc_clocksource_init(void) | 53 | static int __init mxc_clocksource_init(struct clk *timer_clk) |
| 57 | { | 54 | { |
| 58 | unsigned int clock; | 55 | unsigned int c = clk_get_rate(timer_clk); |
| 59 | |||
| 60 | clock = clk_get_rate(timer_clk); | ||
| 61 | 56 | ||
| 62 | clocksource_mxc.mult = clocksource_hz2mult(clock, | 57 | clocksource_mxc.mult = clocksource_hz2mult(c, |
| 63 | clocksource_mxc.shift); | 58 | clocksource_mxc.shift); |
| 64 | clocksource_register(&clocksource_mxc); | 59 | clocksource_register(&clocksource_mxc); |
| 65 | 60 | ||
| @@ -177,13 +172,11 @@ static struct clock_event_device clockevent_mxc = { | |||
| 177 | .rating = 200, | 172 | .rating = 200, |
| 178 | }; | 173 | }; |
| 179 | 174 | ||
| 180 | static int __init mxc_clockevent_init(void) | 175 | static int __init mxc_clockevent_init(struct clk *timer_clk) |
| 181 | { | 176 | { |
| 182 | unsigned int clock; | 177 | unsigned int c = clk_get_rate(timer_clk); |
| 183 | |||
| 184 | clock = clk_get_rate(timer_clk); | ||
| 185 | 178 | ||
| 186 | clockevent_mxc.mult = div_sc(clock, NSEC_PER_SEC, | 179 | clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC, |
| 187 | clockevent_mxc.shift); | 180 | clockevent_mxc.shift); |
| 188 | clockevent_mxc.max_delta_ns = | 181 | clockevent_mxc.max_delta_ns = |
| 189 | clockevent_delta2ns(0xfffffffe, &clockevent_mxc); | 182 | clockevent_delta2ns(0xfffffffe, &clockevent_mxc); |
| @@ -197,14 +190,8 @@ static int __init mxc_clockevent_init(void) | |||
| 197 | return 0; | 190 | return 0; |
| 198 | } | 191 | } |
| 199 | 192 | ||
| 200 | void __init mxc_timer_init(const char *clk_timer) | 193 | void __init mxc_timer_init(struct clk *timer_clk) |
| 201 | { | 194 | { |
| 202 | timer_clk = clk_get(NULL, clk_timer); | ||
| 203 | if (!timer_clk) { | ||
| 204 | printk(KERN_ERR"Cannot determine timer clock. Giving up.\n"); | ||
| 205 | return; | ||
| 206 | } | ||
| 207 | |||
| 208 | clk_enable(timer_clk); | 195 | clk_enable(timer_clk); |
| 209 | 196 | ||
| 210 | /* | 197 | /* |
| @@ -219,10 +206,9 @@ void __init mxc_timer_init(const char *clk_timer) | |||
| 219 | TIMER_BASE + MXC_TCTL); | 206 | TIMER_BASE + MXC_TCTL); |
| 220 | 207 | ||
| 221 | /* init and register the timer to the framework */ | 208 | /* init and register the timer to the framework */ |
| 222 | mxc_clocksource_init(); | 209 | mxc_clocksource_init(timer_clk); |
| 223 | mxc_clockevent_init(); | 210 | mxc_clockevent_init(timer_clk); |
| 224 | 211 | ||
| 225 | /* Make irqs happen */ | 212 | /* Make irqs happen */ |
| 226 | setup_irq(TIMER_INTERRUPT, &mxc_timer_irq); | 213 | setup_irq(TIMER_INTERRUPT, &mxc_timer_irq); |
| 227 | } | 214 | } |
| 228 | |||
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index 46d3b0b9ce69..9dd68fafb374 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig | |||
| @@ -11,14 +11,17 @@ choice | |||
| 11 | 11 | ||
| 12 | config ARCH_OMAP1 | 12 | config ARCH_OMAP1 |
| 13 | bool "TI OMAP1" | 13 | bool "TI OMAP1" |
| 14 | select COMMON_CLKDEV | ||
| 14 | 15 | ||
| 15 | config ARCH_OMAP2 | 16 | config ARCH_OMAP2 |
| 16 | bool "TI OMAP2" | 17 | bool "TI OMAP2" |
| 17 | select CPU_V6 | 18 | select CPU_V6 |
| 19 | select COMMON_CLKDEV | ||
| 18 | 20 | ||
| 19 | config ARCH_OMAP3 | 21 | config ARCH_OMAP3 |
| 20 | bool "TI OMAP3" | 22 | bool "TI OMAP3" |
| 21 | select CPU_V7 | 23 | select CPU_V7 |
| 24 | select COMMON_CLKDEV | ||
| 22 | 25 | ||
| 23 | endchoice | 26 | endchoice |
| 24 | 27 | ||
| @@ -104,6 +107,14 @@ config OMAP_MCBSP | |||
| 104 | Say Y here if you want support for the OMAP Multichannel | 107 | Say Y here if you want support for the OMAP Multichannel |
| 105 | Buffered Serial Port. | 108 | Buffered Serial Port. |
| 106 | 109 | ||
| 110 | config OMAP_MBOX_FWK | ||
| 111 | tristate "Mailbox framework support" | ||
| 112 | depends on ARCH_OMAP | ||
| 113 | default n | ||
| 114 | help | ||
| 115 | Say Y here if you want to use OMAP Mailbox framework support for | ||
| 116 | DSP, IVA1.0 and IVA2 in OMAP1/2/3. | ||
| 117 | |||
| 107 | choice | 118 | choice |
| 108 | prompt "System timer" | 119 | prompt "System timer" |
| 109 | default OMAP_MPU_TIMER | 120 | default OMAP_MPU_TIMER |
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile index deaff58878a2..04a100cfb8e5 100644 --- a/arch/arm/plat-omap/Makefile +++ b/arch/arm/plat-omap/Makefile | |||
| @@ -18,7 +18,8 @@ obj-$(CONFIG_CPU_FREQ) += cpu-omap.o | |||
| 18 | obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o | 18 | obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o |
| 19 | obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o | 19 | obj-$(CONFIG_OMAP_DEBUG_DEVICES) += debug-devices.o |
| 20 | obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o | 20 | obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o |
| 21 | obj-$(CONFIG_I2C_OMAP) += i2c.o | 21 | i2c-omap-$(CONFIG_I2C_OMAP) := i2c.o |
| 22 | obj-y += $(i2c-omap-m) $(i2c-omap-y) | ||
| 22 | 23 | ||
| 23 | # OMAP mailbox framework | 24 | # OMAP mailbox framework |
| 24 | obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o | 25 | obj-$(CONFIG_OMAP_MBOX_FWK) += mailbox.o |
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c index be6aab9c6834..2e0614552ac8 100644 --- a/arch/arm/plat-omap/clock.c +++ b/arch/arm/plat-omap/clock.c | |||
| @@ -36,44 +36,6 @@ static struct clk_functions *arch_clock; | |||
| 36 | * Standard clock functions defined in include/linux/clk.h | 36 | * Standard clock functions defined in include/linux/clk.h |
| 37 | *-------------------------------------------------------------------------*/ | 37 | *-------------------------------------------------------------------------*/ |
| 38 | 38 | ||
| 39 | /* | ||
| 40 | * Returns a clock. Note that we first try to use device id on the bus | ||
| 41 | * and clock name. If this fails, we try to use clock name only. | ||
| 42 | */ | ||
| 43 | struct clk * clk_get(struct device *dev, const char *id) | ||
| 44 | { | ||
| 45 | struct clk *p, *clk = ERR_PTR(-ENOENT); | ||
| 46 | int idno; | ||
| 47 | |||
| 48 | if (dev == NULL || dev->bus != &platform_bus_type) | ||
| 49 | idno = -1; | ||
| 50 | else | ||
| 51 | idno = to_platform_device(dev)->id; | ||
| 52 | |||
| 53 | mutex_lock(&clocks_mutex); | ||
| 54 | |||
| 55 | list_for_each_entry(p, &clocks, node) { | ||
| 56 | if (p->id == idno && | ||
| 57 | strcmp(id, p->name) == 0 && try_module_get(p->owner)) { | ||
| 58 | clk = p; | ||
| 59 | goto found; | ||
| 60 | } | ||
| 61 | } | ||
| 62 | |||
| 63 | list_for_each_entry(p, &clocks, node) { | ||
| 64 | if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) { | ||
| 65 | clk = p; | ||
| 66 | break; | ||
| 67 | } | ||
| 68 | } | ||
| 69 | |||
| 70 | found: | ||
| 71 | mutex_unlock(&clocks_mutex); | ||
| 72 | |||
| 73 | return clk; | ||
| 74 | } | ||
| 75 | EXPORT_SYMBOL(clk_get); | ||
| 76 | |||
| 77 | int clk_enable(struct clk *clk) | 39 | int clk_enable(struct clk *clk) |
| 78 | { | 40 | { |
| 79 | unsigned long flags; | 41 | unsigned long flags; |
| @@ -114,22 +76,6 @@ out: | |||
| 114 | } | 76 | } |
| 115 | EXPORT_SYMBOL(clk_disable); | 77 | EXPORT_SYMBOL(clk_disable); |
| 116 | 78 | ||
| 117 | int clk_get_usecount(struct clk *clk) | ||
| 118 | { | ||
| 119 | unsigned long flags; | ||
| 120 | int ret = 0; | ||
| 121 | |||
| 122 | if (clk == NULL || IS_ERR(clk)) | ||
| 123 | return 0; | ||
| 124 | |||
| 125 | spin_lock_irqsave(&clockfw_lock, flags); | ||
| 126 | ret = clk->usecount; | ||
| 127 | spin_unlock_irqrestore(&clockfw_lock, flags); | ||
| 128 | |||
| 129 | return ret; | ||
| 130 | } | ||
| 131 | EXPORT_SYMBOL(clk_get_usecount); | ||
| 132 | |||
| 133 | unsigned long clk_get_rate(struct clk *clk) | 79 | unsigned long clk_get_rate(struct clk *clk) |
| 134 | { | 80 | { |
| 135 | unsigned long flags; | 81 | unsigned long flags; |
| @@ -146,13 +92,6 @@ unsigned long clk_get_rate(struct clk *clk) | |||
| 146 | } | 92 | } |
| 147 | EXPORT_SYMBOL(clk_get_rate); | 93 | EXPORT_SYMBOL(clk_get_rate); |
| 148 | 94 | ||
| 149 | void clk_put(struct clk *clk) | ||
| 150 | { | ||
| 151 | if (clk && !IS_ERR(clk)) | ||
| 152 | module_put(clk->owner); | ||
| 153 | } | ||
| 154 | EXPORT_SYMBOL(clk_put); | ||
| 155 | |||
| 156 | /*------------------------------------------------------------------------- | 95 | /*------------------------------------------------------------------------- |
| 157 | * Optional clock functions defined in include/linux/clk.h | 96 | * Optional clock functions defined in include/linux/clk.h |
| 158 | *-------------------------------------------------------------------------*/ | 97 | *-------------------------------------------------------------------------*/ |
| @@ -185,6 +124,11 @@ int clk_set_rate(struct clk *clk, unsigned long rate) | |||
| 185 | spin_lock_irqsave(&clockfw_lock, flags); | 124 | spin_lock_irqsave(&clockfw_lock, flags); |
| 186 | if (arch_clock->clk_set_rate) | 125 | if (arch_clock->clk_set_rate) |
| 187 | ret = arch_clock->clk_set_rate(clk, rate); | 126 | ret = arch_clock->clk_set_rate(clk, rate); |
| 127 | if (ret == 0) { | ||
| 128 | if (clk->recalc) | ||
| 129 | clk->rate = clk->recalc(clk); | ||
| 130 | propagate_rate(clk); | ||
| 131 | } | ||
| 188 | spin_unlock_irqrestore(&clockfw_lock, flags); | 132 | spin_unlock_irqrestore(&clockfw_lock, flags); |
| 189 | 133 | ||
| 190 | return ret; | 134 | return ret; |
| @@ -200,8 +144,16 @@ int clk_set_parent(struct clk *clk, struct clk *parent) | |||
| 200 | return ret; | 144 | return ret; |
| 201 | 145 | ||
| 202 | spin_lock_irqsave(&clockfw_lock, flags); | 146 | spin_lock_irqsave(&clockfw_lock, flags); |
| 203 | if (arch_clock->clk_set_parent) | 147 | if (clk->usecount == 0) { |
| 204 | ret = arch_clock->clk_set_parent(clk, parent); | 148 | if (arch_clock->clk_set_parent) |
| 149 | ret = arch_clock->clk_set_parent(clk, parent); | ||
| 150 | if (ret == 0) { | ||
| 151 | if (clk->recalc) | ||
| 152 | clk->rate = clk->recalc(clk); | ||
| 153 | propagate_rate(clk); | ||
| 154 | } | ||
| 155 | } else | ||
| 156 | ret = -EBUSY; | ||
| 205 | spin_unlock_irqrestore(&clockfw_lock, flags); | 157 | spin_unlock_irqrestore(&clockfw_lock, flags); |
| 206 | 158 | ||
| 207 | return ret; | 159 | return ret; |
| @@ -210,18 +162,7 @@ EXPORT_SYMBOL(clk_set_parent); | |||
| 210 | 162 | ||
| 211 | struct clk *clk_get_parent(struct clk *clk) | 163 | struct clk *clk_get_parent(struct clk *clk) |
| 212 | { | 164 | { |
| 213 | unsigned long flags; | 165 | return clk->parent; |
| 214 | struct clk * ret = NULL; | ||
| 215 | |||
| 216 | if (clk == NULL || IS_ERR(clk)) | ||
| 217 | return ret; | ||
| 218 | |||
| 219 | spin_lock_irqsave(&clockfw_lock, flags); | ||
| 220 | if (arch_clock->clk_get_parent) | ||
| 221 | ret = arch_clock->clk_get_parent(clk); | ||
| 222 | spin_unlock_irqrestore(&clockfw_lock, flags); | ||
| 223 | |||
| 224 | return ret; | ||
| 225 | } | 166 | } |
| 226 | EXPORT_SYMBOL(clk_get_parent); | 167 | EXPORT_SYMBOL(clk_get_parent); |
| 227 | 168 | ||
| @@ -250,14 +191,20 @@ static int __init omap_clk_setup(char *str) | |||
| 250 | __setup("mpurate=", omap_clk_setup); | 191 | __setup("mpurate=", omap_clk_setup); |
| 251 | 192 | ||
| 252 | /* Used for clocks that always have same value as the parent clock */ | 193 | /* Used for clocks that always have same value as the parent clock */ |
| 253 | void followparent_recalc(struct clk *clk) | 194 | unsigned long followparent_recalc(struct clk *clk) |
| 254 | { | 195 | { |
| 255 | if (clk == NULL || IS_ERR(clk)) | 196 | return clk->parent->rate; |
| 256 | return; | 197 | } |
| 257 | 198 | ||
| 258 | clk->rate = clk->parent->rate; | 199 | void clk_reparent(struct clk *child, struct clk *parent) |
| 259 | if (unlikely(clk->flags & RATE_PROPAGATES)) | 200 | { |
| 260 | propagate_rate(clk); | 201 | list_del_init(&child->sibling); |
| 202 | if (parent) | ||
| 203 | list_add(&child->sibling, &parent->children); | ||
| 204 | child->parent = parent; | ||
| 205 | |||
| 206 | /* now do the debugfs renaming to reattach the child | ||
| 207 | to the proper parent */ | ||
| 261 | } | 208 | } |
| 262 | 209 | ||
| 263 | /* Propagate rate to children */ | 210 | /* Propagate rate to children */ |
| @@ -265,17 +212,15 @@ void propagate_rate(struct clk * tclk) | |||
| 265 | { | 212 | { |
| 266 | struct clk *clkp; | 213 | struct clk *clkp; |
| 267 | 214 | ||
| 268 | if (tclk == NULL || IS_ERR(tclk)) | 215 | list_for_each_entry(clkp, &tclk->children, sibling) { |
| 269 | return; | 216 | if (clkp->recalc) |
| 270 | 217 | clkp->rate = clkp->recalc(clkp); | |
| 271 | list_for_each_entry(clkp, &clocks, node) { | 218 | propagate_rate(clkp); |
| 272 | if (likely(clkp->parent != tclk)) | ||
| 273 | continue; | ||
| 274 | if (likely((u32)clkp->recalc)) | ||
| 275 | clkp->recalc(clkp); | ||
| 276 | } | 219 | } |
| 277 | } | 220 | } |
| 278 | 221 | ||
| 222 | static LIST_HEAD(root_clks); | ||
| 223 | |||
| 279 | /** | 224 | /** |
| 280 | * recalculate_root_clocks - recalculate and propagate all root clocks | 225 | * recalculate_root_clocks - recalculate and propagate all root clocks |
| 281 | * | 226 | * |
| @@ -287,18 +232,35 @@ void recalculate_root_clocks(void) | |||
| 287 | { | 232 | { |
| 288 | struct clk *clkp; | 233 | struct clk *clkp; |
| 289 | 234 | ||
| 290 | list_for_each_entry(clkp, &clocks, node) { | 235 | list_for_each_entry(clkp, &root_clks, sibling) { |
| 291 | if (unlikely(!clkp->parent) && likely((u32)clkp->recalc)) | 236 | if (clkp->recalc) |
| 292 | clkp->recalc(clkp); | 237 | clkp->rate = clkp->recalc(clkp); |
| 238 | propagate_rate(clkp); | ||
| 293 | } | 239 | } |
| 294 | } | 240 | } |
| 295 | 241 | ||
| 242 | void clk_init_one(struct clk *clk) | ||
| 243 | { | ||
| 244 | INIT_LIST_HEAD(&clk->children); | ||
| 245 | } | ||
| 246 | |||
| 296 | int clk_register(struct clk *clk) | 247 | int clk_register(struct clk *clk) |
| 297 | { | 248 | { |
| 298 | if (clk == NULL || IS_ERR(clk)) | 249 | if (clk == NULL || IS_ERR(clk)) |
| 299 | return -EINVAL; | 250 | return -EINVAL; |
| 300 | 251 | ||
| 252 | /* | ||
| 253 | * trap out already registered clocks | ||
| 254 | */ | ||
| 255 | if (clk->node.next || clk->node.prev) | ||
| 256 | return 0; | ||
| 257 | |||
| 301 | mutex_lock(&clocks_mutex); | 258 | mutex_lock(&clocks_mutex); |
| 259 | if (clk->parent) | ||
| 260 | list_add(&clk->sibling, &clk->parent->children); | ||
| 261 | else | ||
| 262 | list_add(&clk->sibling, &root_clks); | ||
| 263 | |||
| 302 | list_add(&clk->node, &clocks); | 264 | list_add(&clk->node, &clocks); |
| 303 | if (clk->init) | 265 | if (clk->init) |
| 304 | clk->init(clk); | 266 | clk->init(clk); |
| @@ -314,39 +276,12 @@ void clk_unregister(struct clk *clk) | |||
| 314 | return; | 276 | return; |
| 315 | 277 | ||
| 316 | mutex_lock(&clocks_mutex); | 278 | mutex_lock(&clocks_mutex); |
| 279 | list_del(&clk->sibling); | ||
| 317 | list_del(&clk->node); | 280 | list_del(&clk->node); |
| 318 | mutex_unlock(&clocks_mutex); | 281 | mutex_unlock(&clocks_mutex); |
| 319 | } | 282 | } |
| 320 | EXPORT_SYMBOL(clk_unregister); | 283 | EXPORT_SYMBOL(clk_unregister); |
| 321 | 284 | ||
| 322 | void clk_deny_idle(struct clk *clk) | ||
| 323 | { | ||
| 324 | unsigned long flags; | ||
| 325 | |||
| 326 | if (clk == NULL || IS_ERR(clk)) | ||
| 327 | return; | ||
| 328 | |||
| 329 | spin_lock_irqsave(&clockfw_lock, flags); | ||
| 330 | if (arch_clock->clk_deny_idle) | ||
| 331 | arch_clock->clk_deny_idle(clk); | ||
| 332 | spin_unlock_irqrestore(&clockfw_lock, flags); | ||
| 333 | } | ||
| 334 | EXPORT_SYMBOL(clk_deny_idle); | ||
| 335 | |||
| 336 | void clk_allow_idle(struct clk *clk) | ||
| 337 | { | ||
| 338 | unsigned long flags; | ||
| 339 | |||
| 340 | if (clk == NULL || IS_ERR(clk)) | ||
| 341 | return; | ||
| 342 | |||
| 343 | spin_lock_irqsave(&clockfw_lock, flags); | ||
| 344 | if (arch_clock->clk_allow_idle) | ||
| 345 | arch_clock->clk_allow_idle(clk); | ||
| 346 | spin_unlock_irqrestore(&clockfw_lock, flags); | ||
| 347 | } | ||
| 348 | EXPORT_SYMBOL(clk_allow_idle); | ||
| 349 | |||
| 350 | void clk_enable_init_clocks(void) | 285 | void clk_enable_init_clocks(void) |
| 351 | { | 286 | { |
| 352 | struct clk *clkp; | 287 | struct clk *clkp; |
| @@ -358,6 +293,23 @@ void clk_enable_init_clocks(void) | |||
| 358 | } | 293 | } |
| 359 | EXPORT_SYMBOL(clk_enable_init_clocks); | 294 | EXPORT_SYMBOL(clk_enable_init_clocks); |
| 360 | 295 | ||
| 296 | /* | ||
| 297 | * Low level helpers | ||
| 298 | */ | ||
| 299 | static int clkll_enable_null(struct clk *clk) | ||
| 300 | { | ||
| 301 | return 0; | ||
| 302 | } | ||
| 303 | |||
| 304 | static void clkll_disable_null(struct clk *clk) | ||
| 305 | { | ||
| 306 | } | ||
| 307 | |||
| 308 | const struct clkops clkops_null = { | ||
| 309 | .enable = clkll_enable_null, | ||
| 310 | .disable = clkll_disable_null, | ||
| 311 | }; | ||
| 312 | |||
| 361 | #ifdef CONFIG_CPU_FREQ | 313 | #ifdef CONFIG_CPU_FREQ |
| 362 | void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) | 314 | void clk_init_cpufreq_table(struct cpufreq_frequency_table **table) |
| 363 | { | 315 | { |
| @@ -383,8 +335,10 @@ static int __init clk_disable_unused(void) | |||
| 383 | unsigned long flags; | 335 | unsigned long flags; |
| 384 | 336 | ||
| 385 | list_for_each_entry(ck, &clocks, node) { | 337 | list_for_each_entry(ck, &clocks, node) { |
| 386 | if (ck->usecount > 0 || (ck->flags & ALWAYS_ENABLED) || | 338 | if (ck->ops == &clkops_null) |
| 387 | ck->enable_reg == 0) | 339 | continue; |
| 340 | |||
| 341 | if (ck->usecount > 0 || ck->enable_reg == 0) | ||
| 388 | continue; | 342 | continue; |
| 389 | 343 | ||
| 390 | spin_lock_irqsave(&clockfw_lock, flags); | 344 | spin_lock_irqsave(&clockfw_lock, flags); |
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c index 0843b8882f93..d1797147732f 100644 --- a/arch/arm/plat-omap/common.c +++ b/arch/arm/plat-omap/common.c | |||
| @@ -200,20 +200,16 @@ static struct clocksource clocksource_32k = { | |||
| 200 | }; | 200 | }; |
| 201 | 201 | ||
| 202 | /* | 202 | /* |
| 203 | * Rounds down to nearest nsec. | ||
| 204 | */ | ||
| 205 | unsigned long long omap_32k_ticks_to_nsecs(unsigned long ticks_32k) | ||
| 206 | { | ||
| 207 | return cyc2ns(&clocksource_32k, ticks_32k); | ||
| 208 | } | ||
| 209 | |||
| 210 | /* | ||
| 211 | * Returns current time from boot in nsecs. It's OK for this to wrap | 203 | * Returns current time from boot in nsecs. It's OK for this to wrap |
| 212 | * around for now, as it's just a relative time stamp. | 204 | * around for now, as it's just a relative time stamp. |
| 213 | */ | 205 | */ |
| 214 | unsigned long long sched_clock(void) | 206 | unsigned long long sched_clock(void) |
| 215 | { | 207 | { |
| 216 | return omap_32k_ticks_to_nsecs(omap_32k_read()); | 208 | unsigned long long ret; |
| 209 | |||
| 210 | ret = (unsigned long long)omap_32k_read(); | ||
| 211 | ret = (ret * clocksource_32k.mult_orig) >> clocksource_32k.shift; | ||
| 212 | return ret; | ||
| 217 | } | 213 | } |
| 218 | 214 | ||
| 219 | static int __init omap_init_clocksource_32k(void) | 215 | static int __init omap_init_clocksource_32k(void) |
| @@ -249,7 +245,7 @@ static struct omap_globals *omap2_globals; | |||
| 249 | static void __init __omap2_set_globals(void) | 245 | static void __init __omap2_set_globals(void) |
| 250 | { | 246 | { |
| 251 | omap2_set_globals_tap(omap2_globals); | 247 | omap2_set_globals_tap(omap2_globals); |
| 252 | omap2_set_globals_memory(omap2_globals); | 248 | omap2_set_globals_sdrc(omap2_globals); |
| 253 | omap2_set_globals_control(omap2_globals); | 249 | omap2_set_globals_control(omap2_globals); |
| 254 | omap2_set_globals_prcm(omap2_globals); | 250 | omap2_set_globals_prcm(omap2_globals); |
| 255 | } | 251 | } |
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c index b2690242a390..843e8af64066 100644 --- a/arch/arm/plat-omap/cpu-omap.c +++ b/arch/arm/plat-omap/cpu-omap.c | |||
| @@ -23,10 +23,13 @@ | |||
| 23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
| 24 | 24 | ||
| 25 | #include <mach/hardware.h> | 25 | #include <mach/hardware.h> |
| 26 | #include <mach/clock.h> | ||
| 26 | #include <asm/system.h> | 27 | #include <asm/system.h> |
| 27 | 28 | ||
| 28 | #define VERY_HI_RATE 900000000 | 29 | #define VERY_HI_RATE 900000000 |
| 29 | 30 | ||
| 31 | static struct cpufreq_frequency_table *freq_table; | ||
| 32 | |||
| 30 | #ifdef CONFIG_ARCH_OMAP1 | 33 | #ifdef CONFIG_ARCH_OMAP1 |
| 31 | #define MPU_CLK "mpu" | 34 | #define MPU_CLK "mpu" |
| 32 | #else | 35 | #else |
| @@ -39,6 +42,9 @@ static struct clk *mpu_clk; | |||
| 39 | 42 | ||
| 40 | int omap_verify_speed(struct cpufreq_policy *policy) | 43 | int omap_verify_speed(struct cpufreq_policy *policy) |
| 41 | { | 44 | { |
| 45 | if (freq_table) | ||
| 46 | return cpufreq_frequency_table_verify(policy, freq_table); | ||
| 47 | |||
| 42 | if (policy->cpu) | 48 | if (policy->cpu) |
| 43 | return -EINVAL; | 49 | return -EINVAL; |
| 44 | 50 | ||
| @@ -70,12 +76,26 @@ static int omap_target(struct cpufreq_policy *policy, | |||
| 70 | struct cpufreq_freqs freqs; | 76 | struct cpufreq_freqs freqs; |
| 71 | int ret = 0; | 77 | int ret = 0; |
| 72 | 78 | ||
| 79 | /* Ensure desired rate is within allowed range. Some govenors | ||
| 80 | * (ondemand) will just pass target_freq=0 to get the minimum. */ | ||
| 81 | if (target_freq < policy->cpuinfo.min_freq) | ||
| 82 | target_freq = policy->cpuinfo.min_freq; | ||
| 83 | if (target_freq > policy->cpuinfo.max_freq) | ||
| 84 | target_freq = policy->cpuinfo.max_freq; | ||
| 85 | |||
| 73 | freqs.old = omap_getspeed(0); | 86 | freqs.old = omap_getspeed(0); |
| 74 | freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000; | 87 | freqs.new = clk_round_rate(mpu_clk, target_freq * 1000) / 1000; |
| 75 | freqs.cpu = 0; | 88 | freqs.cpu = 0; |
| 76 | 89 | ||
| 90 | if (freqs.old == freqs.new) | ||
| 91 | return ret; | ||
| 92 | |||
| 77 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); | 93 | cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); |
| 78 | ret = clk_set_rate(mpu_clk, target_freq * 1000); | 94 | #ifdef CONFIG_CPU_FREQ_DEBUG |
| 95 | printk(KERN_DEBUG "cpufreq-omap: transition: %u --> %u\n", | ||
| 96 | freqs.old, freqs.new); | ||
| 97 | #endif | ||
| 98 | ret = clk_set_rate(mpu_clk, freqs.new * 1000); | ||
| 79 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); | 99 | cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); |
| 80 | 100 | ||
| 81 | return ret; | 101 | return ret; |
| @@ -83,16 +103,31 @@ static int omap_target(struct cpufreq_policy *policy, | |||
| 83 | 103 | ||
| 84 | static int __init omap_cpu_init(struct cpufreq_policy *policy) | 104 | static int __init omap_cpu_init(struct cpufreq_policy *policy) |
| 85 | { | 105 | { |
| 106 | int result = 0; | ||
| 107 | |||
| 86 | mpu_clk = clk_get(NULL, MPU_CLK); | 108 | mpu_clk = clk_get(NULL, MPU_CLK); |
| 87 | if (IS_ERR(mpu_clk)) | 109 | if (IS_ERR(mpu_clk)) |
| 88 | return PTR_ERR(mpu_clk); | 110 | return PTR_ERR(mpu_clk); |
| 89 | 111 | ||
| 90 | if (policy->cpu != 0) | 112 | if (policy->cpu != 0) |
| 91 | return -EINVAL; | 113 | return -EINVAL; |
| 114 | |||
| 92 | policy->cur = policy->min = policy->max = omap_getspeed(0); | 115 | policy->cur = policy->min = policy->max = omap_getspeed(0); |
| 93 | policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000; | 116 | |
| 94 | policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, VERY_HI_RATE) / 1000; | 117 | clk_init_cpufreq_table(&freq_table); |
| 95 | policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL; | 118 | if (freq_table) { |
| 119 | result = cpufreq_frequency_table_cpuinfo(policy, freq_table); | ||
| 120 | if (!result) | ||
| 121 | cpufreq_frequency_table_get_attr(freq_table, | ||
| 122 | policy->cpu); | ||
| 123 | } else { | ||
| 124 | policy->cpuinfo.min_freq = clk_round_rate(mpu_clk, 0) / 1000; | ||
| 125 | policy->cpuinfo.max_freq = clk_round_rate(mpu_clk, | ||
| 126 | VERY_HI_RATE) / 1000; | ||
| 127 | } | ||
| 128 | |||
| 129 | /* FIXME: what's the actual transition time? */ | ||
| 130 | policy->cpuinfo.transition_latency = 10 * 1000 * 1000; | ||
| 96 | 131 | ||
| 97 | return 0; | 132 | return 0; |
| 98 | } | 133 | } |
| @@ -103,6 +138,11 @@ static int omap_cpu_exit(struct cpufreq_policy *policy) | |||
| 103 | return 0; | 138 | return 0; |
| 104 | } | 139 | } |
| 105 | 140 | ||
| 141 | static struct freq_attr *omap_cpufreq_attr[] = { | ||
| 142 | &cpufreq_freq_attr_scaling_available_freqs, | ||
| 143 | NULL, | ||
| 144 | }; | ||
| 145 | |||
| 106 | static struct cpufreq_driver omap_driver = { | 146 | static struct cpufreq_driver omap_driver = { |
| 107 | .flags = CPUFREQ_STICKY, | 147 | .flags = CPUFREQ_STICKY, |
| 108 | .verify = omap_verify_speed, | 148 | .verify = omap_verify_speed, |
| @@ -111,6 +151,7 @@ static struct cpufreq_driver omap_driver = { | |||
| 111 | .init = omap_cpu_init, | 151 | .init = omap_cpu_init, |
| 112 | .exit = omap_cpu_exit, | 152 | .exit = omap_cpu_exit, |
| 113 | .name = "omap", | 153 | .name = "omap", |
| 154 | .attr = omap_cpufreq_attr, | ||
| 114 | }; | 155 | }; |
| 115 | 156 | ||
| 116 | static int __init omap_cpufreq_init(void) | 157 | static int __init omap_cpufreq_init(void) |
| @@ -119,3 +160,11 @@ static int __init omap_cpufreq_init(void) | |||
| 119 | } | 160 | } |
| 120 | 161 | ||
| 121 | arch_initcall(omap_cpufreq_init); | 162 | arch_initcall(omap_cpufreq_init); |
| 163 | |||
| 164 | /* | ||
| 165 | * if ever we want to remove this, upon cleanup call: | ||
| 166 | * | ||
| 167 | * cpufreq_unregister_driver() | ||
| 168 | * cpufreq_frequency_table_put_attr() | ||
| 169 | */ | ||
| 170 | |||
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c index 208dbb121f47..87fb7ff41794 100644 --- a/arch/arm/plat-omap/devices.c +++ b/arch/arm/plat-omap/devices.c | |||
| @@ -228,6 +228,9 @@ int __init omap_mmc_add(const char *name, int id, unsigned long base, | |||
| 228 | ret = platform_device_add(pdev); | 228 | ret = platform_device_add(pdev); |
| 229 | if (ret) | 229 | if (ret) |
| 230 | goto fail; | 230 | goto fail; |
| 231 | |||
| 232 | /* return device handle to board setup code */ | ||
| 233 | data->dev = &pdev->dev; | ||
| 231 | return 0; | 234 | return 0; |
| 232 | 235 | ||
| 233 | fail: | 236 | fail: |
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 47ec77af4ccb..21cc0142b97a 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c | |||
| @@ -123,6 +123,7 @@ static struct dma_link_info *dma_linked_lch; | |||
| 123 | 123 | ||
| 124 | static int dma_lch_count; | 124 | static int dma_lch_count; |
| 125 | static int dma_chan_count; | 125 | static int dma_chan_count; |
| 126 | static int omap_dma_reserve_channels; | ||
| 126 | 127 | ||
| 127 | static spinlock_t dma_chan_lock; | 128 | static spinlock_t dma_chan_lock; |
| 128 | static struct omap_dma_lch *dma_chan; | 129 | static struct omap_dma_lch *dma_chan; |
| @@ -737,7 +738,7 @@ int omap_request_dma(int dev_id, const char *dev_name, | |||
| 737 | * id. | 738 | * id. |
| 738 | */ | 739 | */ |
| 739 | dma_write(dev_id | (1 << 10), CCR(free_ch)); | 740 | dma_write(dev_id | (1 << 10), CCR(free_ch)); |
| 740 | } else if (cpu_is_omap730() || cpu_is_omap15xx()) { | 741 | } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) { |
| 741 | dma_write(dev_id, CCR(free_ch)); | 742 | dma_write(dev_id, CCR(free_ch)); |
| 742 | } | 743 | } |
| 743 | 744 | ||
| @@ -1900,7 +1901,7 @@ static int omap2_dma_handle_ch(int ch) | |||
| 1900 | /* STATUS register count is from 1-32 while our is 0-31 */ | 1901 | /* STATUS register count is from 1-32 while our is 0-31 */ |
| 1901 | static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) | 1902 | static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) |
| 1902 | { | 1903 | { |
| 1903 | u32 val; | 1904 | u32 val, enable_reg; |
| 1904 | int i; | 1905 | int i; |
| 1905 | 1906 | ||
| 1906 | val = dma_read(IRQSTATUS_L0); | 1907 | val = dma_read(IRQSTATUS_L0); |
| @@ -1909,6 +1910,8 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id) | |||
| 1909 | printk(KERN_WARNING "Spurious DMA IRQ\n"); | 1910 | printk(KERN_WARNING "Spurious DMA IRQ\n"); |
| 1910 | return IRQ_HANDLED; | 1911 | return IRQ_HANDLED; |
| 1911 | } | 1912 | } |
| 1913 | enable_reg = dma_read(IRQENABLE_L0); | ||
| 1914 | val &= enable_reg; /* Dispatch only relevant interrupts */ | ||
| 1912 | for (i = 0; i < dma_lch_count && val != 0; i++) { | 1915 | for (i = 0; i < dma_lch_count && val != 0; i++) { |
| 1913 | if (val & 1) | 1916 | if (val & 1) |
| 1914 | omap2_dma_handle_ch(i); | 1917 | omap2_dma_handle_ch(i); |
| @@ -2321,6 +2324,10 @@ static int __init omap_init_dma(void) | |||
| 2321 | return -ENODEV; | 2324 | return -ENODEV; |
| 2322 | } | 2325 | } |
| 2323 | 2326 | ||
| 2327 | if (cpu_class_is_omap2() && omap_dma_reserve_channels | ||
| 2328 | && (omap_dma_reserve_channels <= dma_lch_count)) | ||
| 2329 | dma_lch_count = omap_dma_reserve_channels; | ||
| 2330 | |||
| 2324 | dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count, | 2331 | dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count, |
| 2325 | GFP_KERNEL); | 2332 | GFP_KERNEL); |
| 2326 | if (!dma_chan) | 2333 | if (!dma_chan) |
| @@ -2339,7 +2346,7 @@ static int __init omap_init_dma(void) | |||
| 2339 | printk(KERN_INFO "DMA support for OMAP15xx initialized\n"); | 2346 | printk(KERN_INFO "DMA support for OMAP15xx initialized\n"); |
| 2340 | dma_chan_count = 9; | 2347 | dma_chan_count = 9; |
| 2341 | enable_1510_mode = 1; | 2348 | enable_1510_mode = 1; |
| 2342 | } else if (cpu_is_omap16xx() || cpu_is_omap730()) { | 2349 | } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) { |
| 2343 | printk(KERN_INFO "OMAP DMA hardware version %d\n", | 2350 | printk(KERN_INFO "OMAP DMA hardware version %d\n", |
| 2344 | dma_read(HW_ID)); | 2351 | dma_read(HW_ID)); |
| 2345 | printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", | 2352 | printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", |
| @@ -2371,7 +2378,7 @@ static int __init omap_init_dma(void) | |||
| 2371 | u8 revision = dma_read(REVISION) & 0xff; | 2378 | u8 revision = dma_read(REVISION) & 0xff; |
| 2372 | printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", | 2379 | printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", |
| 2373 | revision >> 4, revision & 0xf); | 2380 | revision >> 4, revision & 0xf); |
| 2374 | dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT; | 2381 | dma_chan_count = dma_lch_count; |
| 2375 | } else { | 2382 | } else { |
| 2376 | dma_chan_count = 0; | 2383 | dma_chan_count = 0; |
| 2377 | return 0; | 2384 | return 0; |
| @@ -2437,4 +2444,17 @@ static int __init omap_init_dma(void) | |||
| 2437 | 2444 | ||
| 2438 | arch_initcall(omap_init_dma); | 2445 | arch_initcall(omap_init_dma); |
| 2439 | 2446 | ||
| 2447 | /* | ||
| 2448 | * Reserve the omap SDMA channels using cmdline bootarg | ||
| 2449 | * "omap_dma_reserve_ch=". The valid range is 1 to 32 | ||
| 2450 | */ | ||
| 2451 | static int __init omap_dma_cmdline_reserve_ch(char *str) | ||
| 2452 | { | ||
| 2453 | if (get_option(&str, &omap_dma_reserve_channels) != 1) | ||
| 2454 | omap_dma_reserve_channels = 0; | ||
| 2455 | return 1; | ||
| 2456 | } | ||
| 2457 | |||
| 2458 | __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch); | ||
| 2459 | |||
| 2440 | 2460 | ||
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c index e4f0ce04ba92..bfd47570cc91 100644 --- a/arch/arm/plat-omap/dmtimer.c +++ b/arch/arm/plat-omap/dmtimer.c | |||
| @@ -33,6 +33,7 @@ | |||
| 33 | #include <linux/clk.h> | 33 | #include <linux/clk.h> |
| 34 | #include <linux/delay.h> | 34 | #include <linux/delay.h> |
| 35 | #include <linux/io.h> | 35 | #include <linux/io.h> |
| 36 | #include <linux/module.h> | ||
| 36 | #include <mach/hardware.h> | 37 | #include <mach/hardware.h> |
| 37 | #include <mach/dmtimer.h> | 38 | #include <mach/dmtimer.h> |
| 38 | #include <mach/irqs.h> | 39 | #include <mach/irqs.h> |
| @@ -362,6 +363,7 @@ struct omap_dm_timer *omap_dm_timer_request(void) | |||
| 362 | 363 | ||
| 363 | return timer; | 364 | return timer; |
| 364 | } | 365 | } |
| 366 | EXPORT_SYMBOL_GPL(omap_dm_timer_request); | ||
| 365 | 367 | ||
| 366 | struct omap_dm_timer *omap_dm_timer_request_specific(int id) | 368 | struct omap_dm_timer *omap_dm_timer_request_specific(int id) |
| 367 | { | 369 | { |
| @@ -385,6 +387,7 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id) | |||
| 385 | 387 | ||
| 386 | return timer; | 388 | return timer; |
| 387 | } | 389 | } |
| 390 | EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific); | ||
| 388 | 391 | ||
| 389 | void omap_dm_timer_free(struct omap_dm_timer *timer) | 392 | void omap_dm_timer_free(struct omap_dm_timer *timer) |
| 390 | { | 393 | { |
| @@ -395,6 +398,7 @@ void omap_dm_timer_free(struct omap_dm_timer *timer) | |||
| 395 | WARN_ON(!timer->reserved); | 398 | WARN_ON(!timer->reserved); |
| 396 | timer->reserved = 0; | 399 | timer->reserved = 0; |
| 397 | } | 400 | } |
| 401 | EXPORT_SYMBOL_GPL(omap_dm_timer_free); | ||
| 398 | 402 | ||
| 399 | void omap_dm_timer_enable(struct omap_dm_timer *timer) | 403 | void omap_dm_timer_enable(struct omap_dm_timer *timer) |
| 400 | { | 404 | { |
| @@ -406,6 +410,7 @@ void omap_dm_timer_enable(struct omap_dm_timer *timer) | |||
| 406 | 410 | ||
| 407 | timer->enabled = 1; | 411 | timer->enabled = 1; |
| 408 | } | 412 | } |
| 413 | EXPORT_SYMBOL_GPL(omap_dm_timer_enable); | ||
| 409 | 414 | ||
| 410 | void omap_dm_timer_disable(struct omap_dm_timer *timer) | 415 | void omap_dm_timer_disable(struct omap_dm_timer *timer) |
| 411 | { | 416 | { |
| @@ -417,11 +422,13 @@ void omap_dm_timer_disable(struct omap_dm_timer *timer) | |||
| 417 | 422 | ||
| 418 | timer->enabled = 0; | 423 | timer->enabled = 0; |
| 419 | } | 424 | } |
| 425 | EXPORT_SYMBOL_GPL(omap_dm_timer_disable); | ||
| 420 | 426 | ||
| 421 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer) | 427 | int omap_dm_timer_get_irq(struct omap_dm_timer *timer) |
| 422 | { | 428 | { |
| 423 | return timer->irq; | 429 | return timer->irq; |
| 424 | } | 430 | } |
| 431 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq); | ||
| 425 | 432 | ||
| 426 | #if defined(CONFIG_ARCH_OMAP1) | 433 | #if defined(CONFIG_ARCH_OMAP1) |
| 427 | 434 | ||
| @@ -452,6 +459,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |||
| 452 | 459 | ||
| 453 | return inputmask; | 460 | return inputmask; |
| 454 | } | 461 | } |
| 462 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); | ||
| 455 | 463 | ||
| 456 | #elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3) | 464 | #elif defined(CONFIG_ARCH_OMAP2) || defined (CONFIG_ARCH_OMAP3) |
| 457 | 465 | ||
| @@ -459,6 +467,7 @@ struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer) | |||
| 459 | { | 467 | { |
| 460 | return timer->fclk; | 468 | return timer->fclk; |
| 461 | } | 469 | } |
| 470 | EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk); | ||
| 462 | 471 | ||
| 463 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | 472 | __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) |
| 464 | { | 473 | { |
| @@ -466,6 +475,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask) | |||
| 466 | 475 | ||
| 467 | return 0; | 476 | return 0; |
| 468 | } | 477 | } |
| 478 | EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask); | ||
| 469 | 479 | ||
| 470 | #endif | 480 | #endif |
| 471 | 481 | ||
| @@ -473,6 +483,7 @@ void omap_dm_timer_trigger(struct omap_dm_timer *timer) | |||
| 473 | { | 483 | { |
| 474 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); | 484 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
| 475 | } | 485 | } |
| 486 | EXPORT_SYMBOL_GPL(omap_dm_timer_trigger); | ||
| 476 | 487 | ||
| 477 | void omap_dm_timer_start(struct omap_dm_timer *timer) | 488 | void omap_dm_timer_start(struct omap_dm_timer *timer) |
| 478 | { | 489 | { |
| @@ -484,6 +495,7 @@ void omap_dm_timer_start(struct omap_dm_timer *timer) | |||
| 484 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | 495 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
| 485 | } | 496 | } |
| 486 | } | 497 | } |
| 498 | EXPORT_SYMBOL_GPL(omap_dm_timer_start); | ||
| 487 | 499 | ||
| 488 | void omap_dm_timer_stop(struct omap_dm_timer *timer) | 500 | void omap_dm_timer_stop(struct omap_dm_timer *timer) |
| 489 | { | 501 | { |
| @@ -495,6 +507,7 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer) | |||
| 495 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | 507 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
| 496 | } | 508 | } |
| 497 | } | 509 | } |
| 510 | EXPORT_SYMBOL_GPL(omap_dm_timer_stop); | ||
| 498 | 511 | ||
| 499 | #ifdef CONFIG_ARCH_OMAP1 | 512 | #ifdef CONFIG_ARCH_OMAP1 |
| 500 | 513 | ||
| @@ -507,6 +520,7 @@ void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) | |||
| 507 | l |= source << n; | 520 | l |= source << n; |
| 508 | omap_writel(l, MOD_CONF_CTRL_1); | 521 | omap_writel(l, MOD_CONF_CTRL_1); |
| 509 | } | 522 | } |
| 523 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); | ||
| 510 | 524 | ||
| 511 | #else | 525 | #else |
| 512 | 526 | ||
| @@ -523,6 +537,7 @@ void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source) | |||
| 523 | * cause an abort. */ | 537 | * cause an abort. */ |
| 524 | __delay(150000); | 538 | __delay(150000); |
| 525 | } | 539 | } |
| 540 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_source); | ||
| 526 | 541 | ||
| 527 | #endif | 542 | #endif |
| 528 | 543 | ||
| @@ -541,6 +556,7 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, | |||
| 541 | 556 | ||
| 542 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); | 557 | omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); |
| 543 | } | 558 | } |
| 559 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load); | ||
| 544 | 560 | ||
| 545 | /* Optimized set_load which removes costly spin wait in timer_start */ | 561 | /* Optimized set_load which removes costly spin wait in timer_start */ |
| 546 | void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, | 562 | void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, |
| @@ -560,6 +576,7 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, | |||
| 560 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load); | 576 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load); |
| 561 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | 577 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
| 562 | } | 578 | } |
| 579 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start); | ||
| 563 | 580 | ||
| 564 | void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, | 581 | void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, |
| 565 | unsigned int match) | 582 | unsigned int match) |
| @@ -574,6 +591,7 @@ void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, | |||
| 574 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | 591 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
| 575 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); | 592 | omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); |
| 576 | } | 593 | } |
| 594 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_match); | ||
| 577 | 595 | ||
| 578 | void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, | 596 | void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, |
| 579 | int toggle, int trigger) | 597 | int toggle, int trigger) |
| @@ -590,6 +608,7 @@ void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, | |||
| 590 | l |= trigger << 10; | 608 | l |= trigger << 10; |
| 591 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | 609 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
| 592 | } | 610 | } |
| 611 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm); | ||
| 593 | 612 | ||
| 594 | void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) | 613 | void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) |
| 595 | { | 614 | { |
| @@ -603,6 +622,7 @@ void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler) | |||
| 603 | } | 622 | } |
| 604 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); | 623 | omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); |
| 605 | } | 624 | } |
| 625 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler); | ||
| 606 | 626 | ||
| 607 | void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, | 627 | void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, |
| 608 | unsigned int value) | 628 | unsigned int value) |
| @@ -610,6 +630,7 @@ void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, | |||
| 610 | omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value); | 630 | omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value); |
| 611 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value); | 631 | omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value); |
| 612 | } | 632 | } |
| 633 | EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable); | ||
| 613 | 634 | ||
| 614 | unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) | 635 | unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) |
| 615 | { | 636 | { |
| @@ -619,11 +640,13 @@ unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer) | |||
| 619 | 640 | ||
| 620 | return l; | 641 | return l; |
| 621 | } | 642 | } |
| 643 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_status); | ||
| 622 | 644 | ||
| 623 | void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) | 645 | void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value) |
| 624 | { | 646 | { |
| 625 | omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value); | 647 | omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value); |
| 626 | } | 648 | } |
| 649 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_status); | ||
| 627 | 650 | ||
| 628 | unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) | 651 | unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) |
| 629 | { | 652 | { |
| @@ -633,11 +656,13 @@ unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer) | |||
| 633 | 656 | ||
| 634 | return l; | 657 | return l; |
| 635 | } | 658 | } |
| 659 | EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter); | ||
| 636 | 660 | ||
| 637 | void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) | 661 | void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value) |
| 638 | { | 662 | { |
| 639 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); | 663 | omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, value); |
| 640 | } | 664 | } |
| 665 | EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter); | ||
| 641 | 666 | ||
| 642 | int omap_dm_timers_active(void) | 667 | int omap_dm_timers_active(void) |
| 643 | { | 668 | { |
| @@ -658,6 +683,7 @@ int omap_dm_timers_active(void) | |||
| 658 | } | 683 | } |
| 659 | return 0; | 684 | return 0; |
| 660 | } | 685 | } |
| 686 | EXPORT_SYMBOL_GPL(omap_dm_timers_active); | ||
| 661 | 687 | ||
| 662 | int __init omap_dm_timer_init(void) | 688 | int __init omap_dm_timer_init(void) |
| 663 | { | 689 | { |
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index f856a90b264e..d3fa41e3d8c5 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c | |||
| @@ -81,6 +81,22 @@ | |||
| 81 | #define OMAP730_GPIO_INT_STATUS 0x14 | 81 | #define OMAP730_GPIO_INT_STATUS 0x14 |
| 82 | 82 | ||
| 83 | /* | 83 | /* |
| 84 | * OMAP850 specific GPIO registers | ||
| 85 | */ | ||
| 86 | #define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000) | ||
| 87 | #define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800) | ||
| 88 | #define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000) | ||
| 89 | #define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800) | ||
| 90 | #define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000) | ||
| 91 | #define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800) | ||
| 92 | #define OMAP850_GPIO_DATA_INPUT 0x00 | ||
| 93 | #define OMAP850_GPIO_DATA_OUTPUT 0x04 | ||
| 94 | #define OMAP850_GPIO_DIR_CONTROL 0x08 | ||
| 95 | #define OMAP850_GPIO_INT_CONTROL 0x0c | ||
| 96 | #define OMAP850_GPIO_INT_MASK 0x10 | ||
| 97 | #define OMAP850_GPIO_INT_STATUS 0x14 | ||
| 98 | |||
| 99 | /* | ||
| 84 | * omap24xx specific GPIO registers | 100 | * omap24xx specific GPIO registers |
| 85 | */ | 101 | */ |
| 86 | #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000) | 102 | #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000) |
| @@ -159,7 +175,8 @@ struct gpio_bank { | |||
| 159 | #define METHOD_GPIO_1510 1 | 175 | #define METHOD_GPIO_1510 1 |
| 160 | #define METHOD_GPIO_1610 2 | 176 | #define METHOD_GPIO_1610 2 |
| 161 | #define METHOD_GPIO_730 3 | 177 | #define METHOD_GPIO_730 3 |
| 162 | #define METHOD_GPIO_24XX 4 | 178 | #define METHOD_GPIO_850 4 |
| 179 | #define METHOD_GPIO_24XX 5 | ||
| 163 | 180 | ||
| 164 | #ifdef CONFIG_ARCH_OMAP16XX | 181 | #ifdef CONFIG_ARCH_OMAP16XX |
| 165 | static struct gpio_bank gpio_bank_1610[5] = { | 182 | static struct gpio_bank gpio_bank_1610[5] = { |
| @@ -190,6 +207,19 @@ static struct gpio_bank gpio_bank_730[7] = { | |||
| 190 | }; | 207 | }; |
| 191 | #endif | 208 | #endif |
| 192 | 209 | ||
| 210 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 211 | static struct gpio_bank gpio_bank_850[7] = { | ||
| 212 | { OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO }, | ||
| 213 | { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 }, | ||
| 214 | { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 }, | ||
| 215 | { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 }, | ||
| 216 | { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 }, | ||
| 217 | { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 }, | ||
| 218 | { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 }, | ||
| 219 | }; | ||
| 220 | #endif | ||
| 221 | |||
| 222 | |||
| 193 | #ifdef CONFIG_ARCH_OMAP24XX | 223 | #ifdef CONFIG_ARCH_OMAP24XX |
| 194 | 224 | ||
| 195 | static struct gpio_bank gpio_bank_242x[4] = { | 225 | static struct gpio_bank gpio_bank_242x[4] = { |
| @@ -236,7 +266,7 @@ static inline struct gpio_bank *get_gpio_bank(int gpio) | |||
| 236 | return &gpio_bank[0]; | 266 | return &gpio_bank[0]; |
| 237 | return &gpio_bank[1 + (gpio >> 4)]; | 267 | return &gpio_bank[1 + (gpio >> 4)]; |
| 238 | } | 268 | } |
| 239 | if (cpu_is_omap730()) { | 269 | if (cpu_is_omap7xx()) { |
| 240 | if (OMAP_GPIO_IS_MPUIO(gpio)) | 270 | if (OMAP_GPIO_IS_MPUIO(gpio)) |
| 241 | return &gpio_bank[0]; | 271 | return &gpio_bank[0]; |
| 242 | return &gpio_bank[1 + (gpio >> 5)]; | 272 | return &gpio_bank[1 + (gpio >> 5)]; |
| @@ -251,7 +281,7 @@ static inline struct gpio_bank *get_gpio_bank(int gpio) | |||
| 251 | 281 | ||
| 252 | static inline int get_gpio_index(int gpio) | 282 | static inline int get_gpio_index(int gpio) |
| 253 | { | 283 | { |
| 254 | if (cpu_is_omap730()) | 284 | if (cpu_is_omap7xx()) |
| 255 | return gpio & 0x1f; | 285 | return gpio & 0x1f; |
| 256 | if (cpu_is_omap24xx()) | 286 | if (cpu_is_omap24xx()) |
| 257 | return gpio & 0x1f; | 287 | return gpio & 0x1f; |
| @@ -273,7 +303,7 @@ static inline int gpio_valid(int gpio) | |||
| 273 | return 0; | 303 | return 0; |
| 274 | if ((cpu_is_omap16xx()) && gpio < 64) | 304 | if ((cpu_is_omap16xx()) && gpio < 64) |
| 275 | return 0; | 305 | return 0; |
| 276 | if (cpu_is_omap730() && gpio < 192) | 306 | if (cpu_is_omap7xx() && gpio < 192) |
| 277 | return 0; | 307 | return 0; |
| 278 | if (cpu_is_omap24xx() && gpio < 128) | 308 | if (cpu_is_omap24xx() && gpio < 128) |
| 279 | return 0; | 309 | return 0; |
| @@ -318,6 +348,11 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | |||
| 318 | reg += OMAP730_GPIO_DIR_CONTROL; | 348 | reg += OMAP730_GPIO_DIR_CONTROL; |
| 319 | break; | 349 | break; |
| 320 | #endif | 350 | #endif |
| 351 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 352 | case METHOD_GPIO_850: | ||
| 353 | reg += OMAP850_GPIO_DIR_CONTROL; | ||
| 354 | break; | ||
| 355 | #endif | ||
| 321 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 356 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 322 | case METHOD_GPIO_24XX: | 357 | case METHOD_GPIO_24XX: |
| 323 | reg += OMAP24XX_GPIO_OE; | 358 | reg += OMAP24XX_GPIO_OE; |
| @@ -380,6 +415,16 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable) | |||
| 380 | l &= ~(1 << gpio); | 415 | l &= ~(1 << gpio); |
| 381 | break; | 416 | break; |
| 382 | #endif | 417 | #endif |
| 418 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 419 | case METHOD_GPIO_850: | ||
| 420 | reg += OMAP850_GPIO_DATA_OUTPUT; | ||
| 421 | l = __raw_readl(reg); | ||
| 422 | if (enable) | ||
| 423 | l |= 1 << gpio; | ||
| 424 | else | ||
| 425 | l &= ~(1 << gpio); | ||
| 426 | break; | ||
| 427 | #endif | ||
| 383 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 428 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 384 | case METHOD_GPIO_24XX: | 429 | case METHOD_GPIO_24XX: |
| 385 | if (enable) | 430 | if (enable) |
| @@ -426,6 +471,11 @@ static int __omap_get_gpio_datain(int gpio) | |||
| 426 | reg += OMAP730_GPIO_DATA_INPUT; | 471 | reg += OMAP730_GPIO_DATA_INPUT; |
| 427 | break; | 472 | break; |
| 428 | #endif | 473 | #endif |
| 474 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 475 | case METHOD_GPIO_850: | ||
| 476 | reg += OMAP850_GPIO_DATA_INPUT; | ||
| 477 | break; | ||
| 478 | #endif | ||
| 429 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 479 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 430 | case METHOD_GPIO_24XX: | 480 | case METHOD_GPIO_24XX: |
| 431 | reg += OMAP24XX_GPIO_DATAIN; | 481 | reg += OMAP24XX_GPIO_DATAIN; |
| @@ -598,6 +648,18 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) | |||
| 598 | goto bad; | 648 | goto bad; |
| 599 | break; | 649 | break; |
| 600 | #endif | 650 | #endif |
| 651 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 652 | case METHOD_GPIO_850: | ||
| 653 | reg += OMAP850_GPIO_INT_CONTROL; | ||
| 654 | l = __raw_readl(reg); | ||
| 655 | if (trigger & IRQ_TYPE_EDGE_RISING) | ||
| 656 | l |= 1 << gpio; | ||
| 657 | else if (trigger & IRQ_TYPE_EDGE_FALLING) | ||
| 658 | l &= ~(1 << gpio); | ||
| 659 | else | ||
| 660 | goto bad; | ||
| 661 | break; | ||
| 662 | #endif | ||
| 601 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 663 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 602 | case METHOD_GPIO_24XX: | 664 | case METHOD_GPIO_24XX: |
| 603 | set_24xx_gpio_triggering(bank, gpio, trigger); | 665 | set_24xx_gpio_triggering(bank, gpio, trigger); |
| @@ -678,6 +740,11 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) | |||
| 678 | reg += OMAP730_GPIO_INT_STATUS; | 740 | reg += OMAP730_GPIO_INT_STATUS; |
| 679 | break; | 741 | break; |
| 680 | #endif | 742 | #endif |
| 743 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 744 | case METHOD_GPIO_850: | ||
| 745 | reg += OMAP850_GPIO_INT_STATUS; | ||
| 746 | break; | ||
| 747 | #endif | ||
| 681 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 748 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 682 | case METHOD_GPIO_24XX: | 749 | case METHOD_GPIO_24XX: |
| 683 | reg += OMAP24XX_GPIO_IRQSTATUS1; | 750 | reg += OMAP24XX_GPIO_IRQSTATUS1; |
| @@ -736,6 +803,13 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) | |||
| 736 | inv = 1; | 803 | inv = 1; |
| 737 | break; | 804 | break; |
| 738 | #endif | 805 | #endif |
| 806 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 807 | case METHOD_GPIO_850: | ||
| 808 | reg += OMAP850_GPIO_INT_MASK; | ||
| 809 | mask = 0xffffffff; | ||
| 810 | inv = 1; | ||
| 811 | break; | ||
| 812 | #endif | ||
| 739 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 813 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 740 | case METHOD_GPIO_24XX: | 814 | case METHOD_GPIO_24XX: |
| 741 | reg += OMAP24XX_GPIO_IRQENABLE1; | 815 | reg += OMAP24XX_GPIO_IRQENABLE1; |
| @@ -799,6 +873,16 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab | |||
| 799 | l |= gpio_mask; | 873 | l |= gpio_mask; |
| 800 | break; | 874 | break; |
| 801 | #endif | 875 | #endif |
| 876 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 877 | case METHOD_GPIO_850: | ||
| 878 | reg += OMAP850_GPIO_INT_MASK; | ||
| 879 | l = __raw_readl(reg); | ||
| 880 | if (enable) | ||
| 881 | l &= ~(gpio_mask); | ||
| 882 | else | ||
| 883 | l |= gpio_mask; | ||
| 884 | break; | ||
| 885 | #endif | ||
| 802 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 886 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 803 | case METHOD_GPIO_24XX: | 887 | case METHOD_GPIO_24XX: |
| 804 | if (enable) | 888 | if (enable) |
| @@ -983,6 +1067,10 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |||
| 983 | if (bank->method == METHOD_GPIO_730) | 1067 | if (bank->method == METHOD_GPIO_730) |
| 984 | isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; | 1068 | isr_reg = bank->base + OMAP730_GPIO_INT_STATUS; |
| 985 | #endif | 1069 | #endif |
| 1070 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 1071 | if (bank->method == METHOD_GPIO_850) | ||
| 1072 | isr_reg = bank->base + OMAP850_GPIO_INT_STATUS; | ||
| 1073 | #endif | ||
| 986 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) | 1074 | #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) |
| 987 | if (bank->method == METHOD_GPIO_24XX) | 1075 | if (bank->method == METHOD_GPIO_24XX) |
| 988 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; | 1076 | isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1; |
| @@ -1372,6 +1460,13 @@ static int __init _omap_gpio_init(void) | |||
| 1372 | gpio_bank = gpio_bank_730; | 1460 | gpio_bank = gpio_bank_730; |
| 1373 | } | 1461 | } |
| 1374 | #endif | 1462 | #endif |
| 1463 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 1464 | if (cpu_is_omap850()) { | ||
| 1465 | printk(KERN_INFO "OMAP850 GPIO hardware\n"); | ||
| 1466 | gpio_bank_count = 7; | ||
| 1467 | gpio_bank = gpio_bank_850; | ||
| 1468 | } | ||
| 1469 | #endif | ||
| 1375 | 1470 | ||
| 1376 | #ifdef CONFIG_ARCH_OMAP24XX | 1471 | #ifdef CONFIG_ARCH_OMAP24XX |
| 1377 | if (cpu_is_omap242x()) { | 1472 | if (cpu_is_omap242x()) { |
| @@ -1420,7 +1515,7 @@ static int __init _omap_gpio_init(void) | |||
| 1420 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); | 1515 | __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1); |
| 1421 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); | 1516 | __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG); |
| 1422 | } | 1517 | } |
| 1423 | if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) { | 1518 | if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) { |
| 1424 | __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); | 1519 | __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK); |
| 1425 | __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); | 1520 | __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS); |
| 1426 | 1521 | ||
| @@ -1743,6 +1838,9 @@ static int gpio_is_input(struct gpio_bank *bank, int mask) | |||
| 1743 | case METHOD_GPIO_730: | 1838 | case METHOD_GPIO_730: |
| 1744 | reg += OMAP730_GPIO_DIR_CONTROL; | 1839 | reg += OMAP730_GPIO_DIR_CONTROL; |
| 1745 | break; | 1840 | break; |
| 1841 | case METHOD_GPIO_850: | ||
| 1842 | reg += OMAP850_GPIO_DIR_CONTROL; | ||
| 1843 | break; | ||
| 1746 | case METHOD_GPIO_24XX: | 1844 | case METHOD_GPIO_24XX: |
| 1747 | reg += OMAP24XX_GPIO_OE; | 1845 | reg += OMAP24XX_GPIO_OE; |
| 1748 | break; | 1846 | break; |
| @@ -1762,7 +1860,8 @@ static int dbg_gpio_show(struct seq_file *s, void *unused) | |||
| 1762 | 1860 | ||
| 1763 | if (bank_is_mpuio(bank)) | 1861 | if (bank_is_mpuio(bank)) |
| 1764 | gpio = OMAP_MPUIO(0); | 1862 | gpio = OMAP_MPUIO(0); |
| 1765 | else if (cpu_class_is_omap2() || cpu_is_omap730()) | 1863 | else if (cpu_class_is_omap2() || cpu_is_omap730() || |
| 1864 | cpu_is_omap850()) | ||
| 1766 | bankwidth = 32; | 1865 | bankwidth = 32; |
| 1767 | 1866 | ||
| 1768 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { | 1867 | for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) { |
diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index 467531edefd3..a303071d5e36 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c | |||
| @@ -98,6 +98,8 @@ static const int omap34xx_pins[][2] = { | |||
| 98 | static const int omap34xx_pins[][2] = {}; | 98 | static const int omap34xx_pins[][2] = {}; |
| 99 | #endif | 99 | #endif |
| 100 | 100 | ||
| 101 | #define OMAP_I2C_CMDLINE_SETUP (BIT(31)) | ||
| 102 | |||
| 101 | static void __init omap_i2c_mux_pins(int bus) | 103 | static void __init omap_i2c_mux_pins(int bus) |
| 102 | { | 104 | { |
| 103 | int scl, sda; | 105 | int scl, sda; |
| @@ -119,14 +121,9 @@ static void __init omap_i2c_mux_pins(int bus) | |||
| 119 | omap_cfg_reg(scl); | 121 | omap_cfg_reg(scl); |
| 120 | } | 122 | } |
| 121 | 123 | ||
| 122 | int __init omap_register_i2c_bus(int bus_id, u32 clkrate, | 124 | static int __init omap_i2c_nr_ports(void) |
| 123 | struct i2c_board_info const *info, | ||
| 124 | unsigned len) | ||
| 125 | { | 125 | { |
| 126 | int ports, err; | 126 | int ports = 0; |
| 127 | struct platform_device *pdev; | ||
| 128 | struct resource *res; | ||
| 129 | resource_size_t base, irq; | ||
| 130 | 127 | ||
| 131 | if (cpu_class_is_omap1()) | 128 | if (cpu_class_is_omap1()) |
| 132 | ports = 1; | 129 | ports = 1; |
| @@ -135,17 +132,16 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate, | |||
| 135 | else if (cpu_is_omap34xx()) | 132 | else if (cpu_is_omap34xx()) |
| 136 | ports = 3; | 133 | ports = 3; |
| 137 | 134 | ||
| 138 | BUG_ON(bus_id < 1 || bus_id > ports); | 135 | return ports; |
| 136 | } | ||
| 139 | 137 | ||
| 140 | if (info) { | 138 | static int __init omap_i2c_add_bus(int bus_id) |
| 141 | err = i2c_register_board_info(bus_id, info, len); | 139 | { |
| 142 | if (err) | 140 | struct platform_device *pdev; |
| 143 | return err; | 141 | struct resource *res; |
| 144 | } | 142 | resource_size_t base, irq; |
| 145 | 143 | ||
| 146 | pdev = &omap_i2c_devices[bus_id - 1]; | 144 | pdev = &omap_i2c_devices[bus_id - 1]; |
| 147 | *(u32 *)pdev->dev.platform_data = clkrate; | ||
| 148 | |||
| 149 | if (bus_id == 1) { | 145 | if (bus_id == 1) { |
| 150 | res = pdev->resource; | 146 | res = pdev->resource; |
| 151 | if (cpu_class_is_omap1()) { | 147 | if (cpu_class_is_omap1()) { |
| @@ -163,3 +159,81 @@ int __init omap_register_i2c_bus(int bus_id, u32 clkrate, | |||
| 163 | omap_i2c_mux_pins(bus_id - 1); | 159 | omap_i2c_mux_pins(bus_id - 1); |
| 164 | return platform_device_register(pdev); | 160 | return platform_device_register(pdev); |
| 165 | } | 161 | } |
| 162 | |||
| 163 | /** | ||
| 164 | * omap_i2c_bus_setup - Process command line options for the I2C bus speed | ||
| 165 | * @str: String of options | ||
| 166 | * | ||
| 167 | * This function allow to override the default I2C bus speed for given I2C | ||
| 168 | * bus with a command line option. | ||
| 169 | * | ||
| 170 | * Format: i2c_bus=bus_id,clkrate (in kHz) | ||
| 171 | * | ||
| 172 | * Returns 1 on success, 0 otherwise. | ||
| 173 | */ | ||
| 174 | static int __init omap_i2c_bus_setup(char *str) | ||
| 175 | { | ||
| 176 | int ports; | ||
| 177 | int ints[3]; | ||
| 178 | |||
| 179 | ports = omap_i2c_nr_ports(); | ||
| 180 | get_options(str, 3, ints); | ||
| 181 | if (ints[0] < 2 || ints[1] < 1 || ints[1] > ports) | ||
| 182 | return 0; | ||
| 183 | i2c_rate[ints[1] - 1] = ints[2]; | ||
| 184 | i2c_rate[ints[1] - 1] |= OMAP_I2C_CMDLINE_SETUP; | ||
| 185 | |||
| 186 | return 1; | ||
| 187 | } | ||
| 188 | __setup("i2c_bus=", omap_i2c_bus_setup); | ||
| 189 | |||
| 190 | /* | ||
| 191 | * Register busses defined in command line but that are not registered with | ||
| 192 | * omap_register_i2c_bus from board initialization code. | ||
| 193 | */ | ||
| 194 | static int __init omap_register_i2c_bus_cmdline(void) | ||
| 195 | { | ||
| 196 | int i, err = 0; | ||
| 197 | |||
| 198 | for (i = 0; i < ARRAY_SIZE(i2c_rate); i++) | ||
| 199 | if (i2c_rate[i] & OMAP_I2C_CMDLINE_SETUP) { | ||
| 200 | i2c_rate[i] &= ~OMAP_I2C_CMDLINE_SETUP; | ||
| 201 | err = omap_i2c_add_bus(i + 1); | ||
| 202 | if (err) | ||
| 203 | goto out; | ||
| 204 | } | ||
| 205 | |||
| 206 | out: | ||
| 207 | return err; | ||
| 208 | } | ||
| 209 | subsys_initcall(omap_register_i2c_bus_cmdline); | ||
| 210 | |||
| 211 | /** | ||
| 212 | * omap_register_i2c_bus - register I2C bus with device descriptors | ||
| 213 | * @bus_id: bus id counting from number 1 | ||
| 214 | * @clkrate: clock rate of the bus in kHz | ||
| 215 | * @info: pointer into I2C device descriptor table or NULL | ||
| 216 | * @len: number of descriptors in the table | ||
| 217 | * | ||
| 218 | * Returns 0 on success or an error code. | ||
| 219 | */ | ||
| 220 | int __init omap_register_i2c_bus(int bus_id, u32 clkrate, | ||
| 221 | struct i2c_board_info const *info, | ||
| 222 | unsigned len) | ||
| 223 | { | ||
| 224 | int err; | ||
| 225 | |||
| 226 | BUG_ON(bus_id < 1 || bus_id > omap_i2c_nr_ports()); | ||
| 227 | |||
| 228 | if (info) { | ||
| 229 | err = i2c_register_board_info(bus_id, info, len); | ||
| 230 | if (err) | ||
| 231 | return err; | ||
| 232 | } | ||
| 233 | |||
| 234 | if (!i2c_rate[bus_id - 1]) | ||
| 235 | i2c_rate[bus_id - 1] = clkrate; | ||
| 236 | i2c_rate[bus_id - 1] &= ~OMAP_I2C_CMDLINE_SETUP; | ||
| 237 | |||
| 238 | return omap_i2c_add_bus(bus_id); | ||
| 239 | } | ||
diff --git a/arch/arm/plat-omap/include/mach/board-2430sdp.h b/arch/arm/plat-omap/include/mach/board-2430sdp.h deleted file mode 100644 index 10d449ea7ed0..000000000000 --- a/arch/arm/plat-omap/include/mach/board-2430sdp.h +++ /dev/null | |||
| @@ -1,41 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-2430sdp.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP2430 SDP board. | ||
| 5 | * | ||
| 6 | * Based on board-h4.h by Dirk Behme <dirk.behme@de.bosch.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP_2430SDP_H | ||
| 30 | #define __ASM_ARCH_OMAP_2430SDP_H | ||
| 31 | |||
| 32 | /* Placeholder for 2430SDP specific defines */ | ||
| 33 | #define OMAP24XX_ETHR_START 0x08000300 | ||
| 34 | #define OMAP24XX_ETHR_GPIO_IRQ 149 | ||
| 35 | #define SDP2430_CS0_BASE 0x04000000 | ||
| 36 | |||
| 37 | /* Function prototypes */ | ||
| 38 | extern void sdp2430_flash_init(void); | ||
| 39 | extern void sdp2430_usb_init(void); | ||
| 40 | |||
| 41 | #endif /* __ASM_ARCH_OMAP_2430SDP_H */ | ||
diff --git a/arch/arm/plat-omap/include/mach/board-apollon.h b/arch/arm/plat-omap/include/mach/board-apollon.h deleted file mode 100644 index 61bd5e8f09b1..000000000000 --- a/arch/arm/plat-omap/include/mach/board-apollon.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-apollon.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for Samsung OMAP24XX Apollon board. | ||
| 5 | * | ||
| 6 | * Initial creation by Kyungmin Park <kyungmin.park@samsung.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP_APOLLON_H | ||
| 30 | #define __ASM_ARCH_OMAP_APOLLON_H | ||
| 31 | |||
| 32 | #include <mach/cpu.h> | ||
| 33 | |||
| 34 | extern void apollon_mmc_init(void); | ||
| 35 | |||
| 36 | static inline int apollon_plus(void) | ||
| 37 | { | ||
| 38 | /* The apollon plus has IDCODE revision 5 */ | ||
| 39 | return omap_rev() & 0xc0; | ||
| 40 | } | ||
| 41 | |||
| 42 | /* Placeholder for APOLLON specific defines */ | ||
| 43 | #define APOLLON_ETHR_GPIO_IRQ 74 | ||
| 44 | |||
| 45 | #endif /* __ASM_ARCH_OMAP_APOLLON_H */ | ||
| 46 | |||
diff --git a/arch/arm/plat-omap/include/mach/board-fsample.h b/arch/arm/plat-omap/include/mach/board-fsample.h deleted file mode 100644 index cb3c5ae12776..000000000000 --- a/arch/arm/plat-omap/include/mach/board-fsample.h +++ /dev/null | |||
| @@ -1,51 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-fsample.h | ||
| 3 | * | ||
| 4 | * Board-specific goodies for TI F-Sample. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2006 Google, Inc. | ||
| 7 | * Author: Brian Swetland <swetland@google.com> | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __ASM_ARCH_OMAP_FSAMPLE_H | ||
| 15 | #define __ASM_ARCH_OMAP_FSAMPLE_H | ||
| 16 | |||
| 17 | /* fsample is pretty close to p2-sample */ | ||
| 18 | #include <mach/board-perseus2.h> | ||
| 19 | |||
| 20 | #define fsample_cpld_read(reg) __raw_readb(reg) | ||
| 21 | #define fsample_cpld_write(val, reg) __raw_writeb(val, reg) | ||
| 22 | |||
| 23 | #define FSAMPLE_CPLD_BASE 0xE8100000 | ||
| 24 | #define FSAMPLE_CPLD_SIZE SZ_4K | ||
| 25 | #define FSAMPLE_CPLD_START 0x05080000 | ||
| 26 | |||
| 27 | #define FSAMPLE_CPLD_REG_A (FSAMPLE_CPLD_BASE + 0x00) | ||
| 28 | #define FSAMPLE_CPLD_SWITCH (FSAMPLE_CPLD_BASE + 0x02) | ||
| 29 | #define FSAMPLE_CPLD_UART (FSAMPLE_CPLD_BASE + 0x02) | ||
| 30 | #define FSAMPLE_CPLD_REG_B (FSAMPLE_CPLD_BASE + 0x04) | ||
| 31 | #define FSAMPLE_CPLD_VERSION (FSAMPLE_CPLD_BASE + 0x06) | ||
| 32 | #define FSAMPLE_CPLD_SET_CLR (FSAMPLE_CPLD_BASE + 0x06) | ||
| 33 | |||
| 34 | #define FSAMPLE_CPLD_BIT_BT_RESET 0 | ||
| 35 | #define FSAMPLE_CPLD_BIT_LCD_RESET 1 | ||
| 36 | #define FSAMPLE_CPLD_BIT_CAM_PWDN 2 | ||
| 37 | #define FSAMPLE_CPLD_BIT_CHARGER_ENABLE 3 | ||
| 38 | #define FSAMPLE_CPLD_BIT_SD_MMC_EN 4 | ||
| 39 | #define FSAMPLE_CPLD_BIT_aGPS_PWREN 5 | ||
| 40 | #define FSAMPLE_CPLD_BIT_BACKLIGHT 6 | ||
| 41 | #define FSAMPLE_CPLD_BIT_aGPS_EN_RESET 7 | ||
| 42 | #define FSAMPLE_CPLD_BIT_aGPS_SLEEPx_N 8 | ||
| 43 | #define FSAMPLE_CPLD_BIT_OTG_RESET 9 | ||
| 44 | |||
| 45 | #define fsample_cpld_set(bit) \ | ||
| 46 | fsample_cpld_write((((bit) & 15) << 4) | 0x0f, FSAMPLE_CPLD_SET_CLR) | ||
| 47 | |||
| 48 | #define fsample_cpld_clear(bit) \ | ||
| 49 | fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR) | ||
| 50 | |||
| 51 | #endif | ||
diff --git a/arch/arm/plat-omap/include/mach/board-h4.h b/arch/arm/plat-omap/include/mach/board-h4.h deleted file mode 100644 index 7c3fa0f0a65e..000000000000 --- a/arch/arm/plat-omap/include/mach/board-h4.h +++ /dev/null | |||
| @@ -1,38 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-h4.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP2420 H4 board. | ||
| 5 | * | ||
| 6 | * Initial creation by Dirk Behme <dirk.behme@de.bosch.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP_H4_H | ||
| 30 | #define __ASM_ARCH_OMAP_H4_H | ||
| 31 | |||
| 32 | /* MMC Prototypes */ | ||
| 33 | extern void h4_mmc_init(void); | ||
| 34 | |||
| 35 | /* Placeholder for H4 specific defines */ | ||
| 36 | #define OMAP24XX_ETHR_GPIO_IRQ 92 | ||
| 37 | #endif /* __ASM_ARCH_OMAP_H4_H */ | ||
| 38 | |||
diff --git a/arch/arm/plat-omap/include/mach/board-innovator.h b/arch/arm/plat-omap/include/mach/board-innovator.h deleted file mode 100644 index 5ae3e79b9f9c..000000000000 --- a/arch/arm/plat-omap/include/mach/board-innovator.h +++ /dev/null | |||
| @@ -1,52 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-innovator.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001 RidgeRun, Inc. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License as published by the | ||
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 9 | * option) any later version. | ||
| 10 | * | ||
| 11 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 14 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 15 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 16 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 17 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 18 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 19 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 20 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 21 | * | ||
| 22 | * You should have received a copy of the GNU General Public License along | ||
| 23 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 24 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 25 | */ | ||
| 26 | #ifndef __ASM_ARCH_OMAP_INNOVATOR_H | ||
| 27 | #define __ASM_ARCH_OMAP_INNOVATOR_H | ||
| 28 | |||
| 29 | #if defined (CONFIG_ARCH_OMAP15XX) | ||
| 30 | |||
| 31 | #ifndef OMAP_SDRAM_DEVICE | ||
| 32 | #define OMAP_SDRAM_DEVICE D256M_1X16_4B | ||
| 33 | #endif | ||
| 34 | |||
| 35 | #define OMAP1510P1_IMIF_PRI_VALUE 0x00 | ||
| 36 | #define OMAP1510P1_EMIFS_PRI_VALUE 0x00 | ||
| 37 | #define OMAP1510P1_EMIFF_PRI_VALUE 0x00 | ||
| 38 | |||
| 39 | #ifndef __ASSEMBLY__ | ||
| 40 | void fpga_write(unsigned char val, int reg); | ||
| 41 | unsigned char fpga_read(int reg); | ||
| 42 | #endif | ||
| 43 | |||
| 44 | #endif /* CONFIG_ARCH_OMAP15XX */ | ||
| 45 | |||
| 46 | #if defined (CONFIG_ARCH_OMAP16XX) | ||
| 47 | |||
| 48 | /* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ | ||
| 49 | #define INNOVATOR1610_ETHR_START 0x04000300 | ||
| 50 | |||
| 51 | #endif /* CONFIG_ARCH_OMAP1610 */ | ||
| 52 | #endif /* __ASM_ARCH_OMAP_INNOVATOR_H */ | ||
diff --git a/arch/arm/plat-omap/include/mach/board-ldp.h b/arch/arm/plat-omap/include/mach/board-ldp.h deleted file mode 100644 index f23399665212..000000000000 --- a/arch/arm/plat-omap/include/mach/board-ldp.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-ldp.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP3 LDP. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2008 Texas Instruments Inc. | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP_LDP_H | ||
| 30 | #define __ASM_ARCH_OMAP_LDP_H | ||
| 31 | |||
| 32 | extern void twl4030_bci_battery_init(void); | ||
| 33 | |||
| 34 | #define TWL4030_IRQNUM INT_34XX_SYS_NIRQ | ||
| 35 | #define LDP_SMC911X_CS 1 | ||
| 36 | #define LDP_SMC911X_GPIO 152 | ||
| 37 | #define DEBUG_BASE 0x08000000 | ||
| 38 | #define OMAP34XX_ETHR_START DEBUG_BASE | ||
| 39 | #endif /* __ASM_ARCH_OMAP_LDP_H */ | ||
diff --git a/arch/arm/plat-omap/include/mach/board-nokia.h b/arch/arm/plat-omap/include/mach/board-nokia.h deleted file mode 100644 index 2abbe001af8c..000000000000 --- a/arch/arm/plat-omap/include/mach/board-nokia.h +++ /dev/null | |||
| @@ -1,54 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-nokia.h | ||
| 3 | * | ||
| 4 | * Information structures for Nokia-specific board config data | ||
| 5 | * | ||
| 6 | * Copyright (C) 2005 Nokia Corporation | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef _OMAP_BOARD_NOKIA_H | ||
| 10 | #define _OMAP_BOARD_NOKIA_H | ||
| 11 | |||
| 12 | #include <linux/types.h> | ||
| 13 | |||
| 14 | #define OMAP_TAG_NOKIA_BT 0x4e01 | ||
| 15 | #define OMAP_TAG_WLAN_CX3110X 0x4e02 | ||
| 16 | #define OMAP_TAG_CBUS 0x4e03 | ||
| 17 | #define OMAP_TAG_EM_ASIC_BB5 0x4e04 | ||
| 18 | |||
| 19 | |||
| 20 | #define BT_CHIP_CSR 1 | ||
| 21 | #define BT_CHIP_TI 2 | ||
| 22 | |||
| 23 | #define BT_SYSCLK_12 1 | ||
| 24 | #define BT_SYSCLK_38_4 2 | ||
| 25 | |||
| 26 | struct omap_bluetooth_config { | ||
| 27 | u8 chip_type; | ||
| 28 | u8 bt_wakeup_gpio; | ||
| 29 | u8 host_wakeup_gpio; | ||
| 30 | u8 reset_gpio; | ||
| 31 | u8 bt_uart; | ||
| 32 | u8 bd_addr[6]; | ||
| 33 | u8 bt_sysclk; | ||
| 34 | }; | ||
| 35 | |||
| 36 | struct omap_wlan_cx3110x_config { | ||
| 37 | u8 chip_type; | ||
| 38 | s16 power_gpio; | ||
| 39 | s16 irq_gpio; | ||
| 40 | s16 spi_cs_gpio; | ||
| 41 | }; | ||
| 42 | |||
| 43 | struct omap_cbus_config { | ||
| 44 | s16 clk_gpio; | ||
| 45 | s16 dat_gpio; | ||
| 46 | s16 sel_gpio; | ||
| 47 | }; | ||
| 48 | |||
| 49 | struct omap_em_asic_bb5_config { | ||
| 50 | s16 retu_irq_gpio; | ||
| 51 | s16 tahvo_irq_gpio; | ||
| 52 | }; | ||
| 53 | |||
| 54 | #endif | ||
diff --git a/arch/arm/plat-omap/include/mach/board-omap3beagle.h b/arch/arm/plat-omap/include/mach/board-omap3beagle.h deleted file mode 100644 index 3080d52d877a..000000000000 --- a/arch/arm/plat-omap/include/mach/board-omap3beagle.h +++ /dev/null | |||
| @@ -1,33 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-omap3beagle.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP3 BEAGLE. | ||
| 5 | * | ||
| 6 | * Initial creation by Syed Mohammed Khasim <khasim@ti.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP3_BEAGLE_H | ||
| 30 | #define __ASM_ARCH_OMAP3_BEAGLE_H | ||
| 31 | |||
| 32 | #endif /* __ASM_ARCH_OMAP3_BEAGLE_H */ | ||
| 33 | |||
diff --git a/arch/arm/plat-omap/include/mach/board-osk.h b/arch/arm/plat-omap/include/mach/board-osk.h deleted file mode 100644 index 3850cb1f220a..000000000000 --- a/arch/arm/plat-omap/include/mach/board-osk.h +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-osk.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for TI OMAP5912 OSK board. | ||
| 5 | * | ||
| 6 | * Written by Dirk Behme <dirk.behme@de.bosch.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify it | ||
| 9 | * under the terms of the GNU General Public License as published by the | ||
| 10 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 11 | * option) any later version. | ||
| 12 | * | ||
| 13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License along | ||
| 25 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 27 | */ | ||
| 28 | |||
| 29 | #ifndef __ASM_ARCH_OMAP_OSK_H | ||
| 30 | #define __ASM_ARCH_OMAP_OSK_H | ||
| 31 | |||
| 32 | /* At OMAP5912 OSK the Ethernet is directly connected to CS1 */ | ||
| 33 | #define OMAP_OSK_ETHR_START 0x04800300 | ||
| 34 | |||
| 35 | /* TPS65010 has four GPIOs. nPG and LED2 can be treated like GPIOs with | ||
| 36 | * alternate pin configurations for hardware-controlled blinking. | ||
| 37 | */ | ||
| 38 | #define OSK_TPS_GPIO_BASE (OMAP_MAX_GPIO_LINES + 16 /* MPUIO */) | ||
| 39 | # define OSK_TPS_GPIO_USB_PWR_EN (OSK_TPS_GPIO_BASE + 0) | ||
| 40 | # define OSK_TPS_GPIO_LED_D3 (OSK_TPS_GPIO_BASE + 1) | ||
| 41 | # define OSK_TPS_GPIO_LAN_RESET (OSK_TPS_GPIO_BASE + 2) | ||
| 42 | # define OSK_TPS_GPIO_DSP_PWR_EN (OSK_TPS_GPIO_BASE + 3) | ||
| 43 | # define OSK_TPS_GPIO_LED_D9 (OSK_TPS_GPIO_BASE + 4) | ||
| 44 | # define OSK_TPS_GPIO_LED_D2 (OSK_TPS_GPIO_BASE + 5) | ||
| 45 | |||
| 46 | #endif /* __ASM_ARCH_OMAP_OSK_H */ | ||
| 47 | |||
diff --git a/arch/arm/plat-omap/include/mach/board-overo.h b/arch/arm/plat-omap/include/mach/board-overo.h deleted file mode 100644 index 7ecae66966d1..000000000000 --- a/arch/arm/plat-omap/include/mach/board-overo.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * board-overo.h (Gumstix Overo) | ||
| 3 | * | ||
| 4 | * Initial code: Steve Sakoman <steve@sakoman.com> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify it | ||
| 7 | * under the terms of the GNU General Public License as published by the | ||
| 8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 9 | * option) any later version. | ||
| 10 | * | ||
| 11 | * You should have received a copy of the GNU General Public License along | ||
| 12 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 13 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_ARCH_OVERO_H | ||
| 17 | #define __ASM_ARCH_OVERO_H | ||
| 18 | |||
| 19 | #define OVERO_GPIO_BT_XGATE 15 | ||
| 20 | #define OVERO_GPIO_W2W_NRESET 16 | ||
| 21 | #define OVERO_GPIO_BT_NRESET 164 | ||
| 22 | #define OVERO_GPIO_USBH_CPEN 168 | ||
| 23 | #define OVERO_GPIO_USBH_NRESET 183 | ||
| 24 | |||
| 25 | #endif /* ____ASM_ARCH_OVERO_H */ | ||
| 26 | |||
diff --git a/arch/arm/plat-omap/include/mach/board-palmte.h b/arch/arm/plat-omap/include/mach/board-palmte.h deleted file mode 100644 index 6906cdebbcfb..000000000000 --- a/arch/arm/plat-omap/include/mach/board-palmte.h +++ /dev/null | |||
| @@ -1,32 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-palmte.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for the Palm Tungsten E device. | ||
| 5 | * | ||
| 6 | * Maintainters : http://palmtelinux.sf.net | ||
| 7 | * palmtelinux-developpers@lists.sf.net | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __OMAP_BOARD_PALMTE_H | ||
| 15 | #define __OMAP_BOARD_PALMTE_H | ||
| 16 | |||
| 17 | #define PALMTE_USBDETECT_GPIO 0 | ||
| 18 | #define PALMTE_USB_OR_DC_GPIO 1 | ||
| 19 | #define PALMTE_TSC_GPIO 4 | ||
| 20 | #define PALMTE_PINTDAV_GPIO 6 | ||
| 21 | #define PALMTE_MMC_WP_GPIO 8 | ||
| 22 | #define PALMTE_MMC_POWER_GPIO 9 | ||
| 23 | #define PALMTE_HDQ_GPIO 11 | ||
| 24 | #define PALMTE_HEADPHONES_GPIO 14 | ||
| 25 | #define PALMTE_SPEAKER_GPIO 15 | ||
| 26 | #define PALMTE_DC_GPIO OMAP_MPUIO(2) | ||
| 27 | #define PALMTE_MMC_SWITCH_GPIO OMAP_MPUIO(4) | ||
| 28 | #define PALMTE_MMC1_GPIO OMAP_MPUIO(6) | ||
| 29 | #define PALMTE_MMC2_GPIO OMAP_MPUIO(7) | ||
| 30 | #define PALMTE_MMC3_GPIO OMAP_MPUIO(11) | ||
| 31 | |||
| 32 | #endif /* __OMAP_BOARD_PALMTE_H */ | ||
diff --git a/arch/arm/plat-omap/include/mach/board-palmtt.h b/arch/arm/plat-omap/include/mach/board-palmtt.h deleted file mode 100644 index e79f382b5931..000000000000 --- a/arch/arm/plat-omap/include/mach/board-palmtt.h +++ /dev/null | |||
| @@ -1,23 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-palmte.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for the Palm Tungsten|T device. | ||
| 5 | * | ||
| 6 | * Maintainters : Marek Vasut <marek.vasut@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __OMAP_BOARD_PALMTT_H | ||
| 14 | #define __OMAP_BOARD_PALMTT_H | ||
| 15 | |||
| 16 | #define PALMTT_USBDETECT_GPIO 0 | ||
| 17 | #define PALMTT_CABLE_GPIO 1 | ||
| 18 | #define PALMTT_LED_GPIO 3 | ||
| 19 | #define PALMTT_PENIRQ_GPIO 6 | ||
| 20 | #define PALMTT_MMC_WP_GPIO 8 | ||
| 21 | #define PALMTT_HDQ_GPIO 11 | ||
| 22 | |||
| 23 | #endif /* __OMAP_BOARD_PALMTT_H */ | ||
diff --git a/arch/arm/plat-omap/include/mach/board-palmz71.h b/arch/arm/plat-omap/include/mach/board-palmz71.h deleted file mode 100644 index b1d7d579b313..000000000000 --- a/arch/arm/plat-omap/include/mach/board-palmz71.h +++ /dev/null | |||
| @@ -1,26 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-palmz71.h | ||
| 3 | * | ||
| 4 | * Hardware definitions for the Palm Zire71 device. | ||
| 5 | * | ||
| 6 | * Maintainters : Marek Vasut <marek.vasut@gmail.com> | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef __OMAP_BOARD_PALMZ71_H | ||
| 14 | #define __OMAP_BOARD_PALMZ71_H | ||
| 15 | |||
| 16 | #define PALMZ71_USBDETECT_GPIO 0 | ||
| 17 | #define PALMZ71_PENIRQ_GPIO 6 | ||
| 18 | #define PALMZ71_MMC_WP_GPIO 8 | ||
| 19 | #define PALMZ71_HDQ_GPIO 11 | ||
| 20 | |||
| 21 | #define PALMZ71_HOTSYNC_GPIO OMAP_MPUIO(1) | ||
| 22 | #define PALMZ71_CABLE_GPIO OMAP_MPUIO(2) | ||
| 23 | #define PALMZ71_SLIDER_GPIO OMAP_MPUIO(3) | ||
| 24 | #define PALMZ71_MMC_IN_GPIO OMAP_MPUIO(4) | ||
| 25 | |||
| 26 | #endif /* __OMAP_BOARD_PALMZ71_H */ | ||
diff --git a/arch/arm/plat-omap/include/mach/board-perseus2.h b/arch/arm/plat-omap/include/mach/board-perseus2.h deleted file mode 100644 index c06c3d717d57..000000000000 --- a/arch/arm/plat-omap/include/mach/board-perseus2.h +++ /dev/null | |||
| @@ -1,39 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-omap/include/mach/board-perseus2.h | ||
| 3 | * | ||
| 4 | * Copyright 2003 by Texas Instruments Incorporated | ||
| 5 | * OMAP730 / Perseus2 support by Jean Pihet | ||
| 6 | * | ||
| 7 | * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com) | ||
| 8 | * Author: RidgeRun, Inc. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify it | ||
| 11 | * under the terms of the GNU General Public License as published by the | ||
| 12 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 13 | * option) any later version. | ||
| 14 | * | ||
| 15 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 16 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 17 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 18 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 19 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 20 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 21 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 22 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 23 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 24 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 25 | * | ||
| 26 | * You should have received a copy of the GNU General Public License along | ||
| 27 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 28 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 29 | */ | ||
| 30 | #ifndef __ASM_ARCH_OMAP_PERSEUS2_H | ||
| 31 | #define __ASM_ARCH_OMAP_PERSEUS2_H | ||
| 32 | |||
| 33 | #include <mach/fpga.h> | ||
| 34 | |||
| 35 | #ifndef OMAP_SDRAM_DEVICE | ||
| 36 | #define OMAP_SDRAM_DEVICE D256M_1X16_4B | ||
| 37 | #endif | ||
| 38 | |||
| 39 | #endif | ||
diff --git a/arch/arm/plat-omap/include/mach/board-voiceblue.h b/arch/arm/plat-omap/include/mach/board-voiceblue.h index ed6d346ee123..27916b210f57 100644 --- a/arch/arm/plat-omap/include/mach/board-voiceblue.h +++ b/arch/arm/plat-omap/include/mach/board-voiceblue.h | |||
| @@ -14,7 +14,6 @@ | |||
| 14 | extern void voiceblue_wdt_enable(void); | 14 | extern void voiceblue_wdt_enable(void); |
| 15 | extern void voiceblue_wdt_disable(void); | 15 | extern void voiceblue_wdt_disable(void); |
| 16 | extern void voiceblue_wdt_ping(void); | 16 | extern void voiceblue_wdt_ping(void); |
| 17 | extern void voiceblue_reset(void); | ||
| 18 | 17 | ||
| 19 | #endif /* __ASM_ARCH_VOICEBLUE_H */ | 18 | #endif /* __ASM_ARCH_VOICEBLUE_H */ |
| 20 | 19 | ||
diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/mach/board.h index 9466772fc7c8..50ea79a0efa2 100644 --- a/arch/arm/plat-omap/include/mach/board.h +++ b/arch/arm/plat-omap/include/mach/board.h | |||
| @@ -17,7 +17,6 @@ | |||
| 17 | /* Different peripheral ids */ | 17 | /* Different peripheral ids */ |
| 18 | #define OMAP_TAG_CLOCK 0x4f01 | 18 | #define OMAP_TAG_CLOCK 0x4f01 |
| 19 | #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 | 19 | #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 |
| 20 | #define OMAP_TAG_USB 0x4f04 | ||
| 21 | #define OMAP_TAG_LCD 0x4f05 | 20 | #define OMAP_TAG_LCD 0x4f05 |
| 22 | #define OMAP_TAG_GPIO_SWITCH 0x4f06 | 21 | #define OMAP_TAG_GPIO_SWITCH 0x4f06 |
| 23 | #define OMAP_TAG_UART 0x4f07 | 22 | #define OMAP_TAG_UART 0x4f07 |
| @@ -133,9 +132,6 @@ struct omap_version_config { | |||
| 133 | char version[12]; | 132 | char version[12]; |
| 134 | }; | 133 | }; |
| 135 | 134 | ||
| 136 | |||
| 137 | #include <mach/board-nokia.h> | ||
| 138 | |||
| 139 | struct omap_board_config_entry { | 135 | struct omap_board_config_entry { |
| 140 | u16 tag; | 136 | u16 tag; |
| 141 | u16 len; | 137 | u16 len; |
diff --git a/arch/arm/plat-omap/include/mach/clkdev.h b/arch/arm/plat-omap/include/mach/clkdev.h new file mode 100644 index 000000000000..730c49d1ebd8 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/clkdev.h | |||
| @@ -0,0 +1,13 @@ | |||
| 1 | #ifndef __MACH_CLKDEV_H | ||
| 2 | #define __MACH_CLKDEV_H | ||
| 3 | |||
| 4 | static inline int __clk_get(struct clk *clk) | ||
| 5 | { | ||
| 6 | return 1; | ||
| 7 | } | ||
| 8 | |||
| 9 | static inline void __clk_put(struct clk *clk) | ||
| 10 | { | ||
| 11 | } | ||
| 12 | |||
| 13 | #endif | ||
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h index 719298554ed7..073a2c5569f0 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/mach/clock.h | |||
| @@ -17,11 +17,16 @@ struct module; | |||
| 17 | struct clk; | 17 | struct clk; |
| 18 | struct clockdomain; | 18 | struct clockdomain; |
| 19 | 19 | ||
| 20 | struct clkops { | ||
| 21 | int (*enable)(struct clk *); | ||
| 22 | void (*disable)(struct clk *); | ||
| 23 | }; | ||
| 24 | |||
| 20 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | 25 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 21 | 26 | ||
| 22 | struct clksel_rate { | 27 | struct clksel_rate { |
| 23 | u8 div; | ||
| 24 | u32 val; | 28 | u32 val; |
| 29 | u8 div; | ||
| 25 | u8 flags; | 30 | u8 flags; |
| 26 | }; | 31 | }; |
| 27 | 32 | ||
| @@ -34,24 +39,28 @@ struct dpll_data { | |||
| 34 | void __iomem *mult_div1_reg; | 39 | void __iomem *mult_div1_reg; |
| 35 | u32 mult_mask; | 40 | u32 mult_mask; |
| 36 | u32 div1_mask; | 41 | u32 div1_mask; |
| 42 | struct clk *clk_bypass; | ||
| 43 | struct clk *clk_ref; | ||
| 44 | void __iomem *control_reg; | ||
| 45 | u32 enable_mask; | ||
| 46 | unsigned int rate_tolerance; | ||
| 47 | unsigned long last_rounded_rate; | ||
| 37 | u16 last_rounded_m; | 48 | u16 last_rounded_m; |
| 38 | u8 last_rounded_n; | 49 | u8 last_rounded_n; |
| 39 | unsigned long last_rounded_rate; | 50 | u8 min_divider; |
| 40 | unsigned int rate_tolerance; | ||
| 41 | u16 max_multiplier; | ||
| 42 | u8 max_divider; | 51 | u8 max_divider; |
| 43 | u32 max_tolerance; | 52 | u32 max_tolerance; |
| 53 | u16 max_multiplier; | ||
| 44 | # if defined(CONFIG_ARCH_OMAP3) | 54 | # if defined(CONFIG_ARCH_OMAP3) |
| 45 | u8 modes; | 55 | u8 modes; |
| 46 | void __iomem *control_reg; | 56 | void __iomem *autoidle_reg; |
| 47 | u32 enable_mask; | 57 | void __iomem *idlest_reg; |
| 58 | u32 autoidle_mask; | ||
| 59 | u32 freqsel_mask; | ||
| 60 | u32 idlest_mask; | ||
| 48 | u8 auto_recal_bit; | 61 | u8 auto_recal_bit; |
| 49 | u8 recal_en_bit; | 62 | u8 recal_en_bit; |
| 50 | u8 recal_st_bit; | 63 | u8 recal_st_bit; |
| 51 | void __iomem *autoidle_reg; | ||
| 52 | u32 autoidle_mask; | ||
| 53 | void __iomem *idlest_reg; | ||
| 54 | u8 idlest_bit; | ||
| 55 | # endif | 64 | # endif |
| 56 | }; | 65 | }; |
| 57 | 66 | ||
| @@ -59,21 +68,21 @@ struct dpll_data { | |||
| 59 | 68 | ||
| 60 | struct clk { | 69 | struct clk { |
| 61 | struct list_head node; | 70 | struct list_head node; |
| 62 | struct module *owner; | 71 | const struct clkops *ops; |
| 63 | const char *name; | 72 | const char *name; |
| 64 | int id; | 73 | int id; |
| 65 | struct clk *parent; | 74 | struct clk *parent; |
| 75 | struct list_head children; | ||
| 76 | struct list_head sibling; /* node for children */ | ||
| 66 | unsigned long rate; | 77 | unsigned long rate; |
| 67 | __u32 flags; | 78 | __u32 flags; |
| 68 | void __iomem *enable_reg; | 79 | void __iomem *enable_reg; |
| 69 | __u8 enable_bit; | 80 | unsigned long (*recalc)(struct clk *); |
| 70 | __s8 usecount; | ||
| 71 | void (*recalc)(struct clk *); | ||
| 72 | int (*set_rate)(struct clk *, unsigned long); | 81 | int (*set_rate)(struct clk *, unsigned long); |
| 73 | long (*round_rate)(struct clk *, unsigned long); | 82 | long (*round_rate)(struct clk *, unsigned long); |
| 74 | void (*init)(struct clk *); | 83 | void (*init)(struct clk *); |
| 75 | int (*enable)(struct clk *); | 84 | __u8 enable_bit; |
| 76 | void (*disable)(struct clk *); | 85 | __s8 usecount; |
| 77 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | 86 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
| 78 | u8 fixed_div; | 87 | u8 fixed_div; |
| 79 | void __iomem *clksel_reg; | 88 | void __iomem *clksel_reg; |
| @@ -99,7 +108,6 @@ struct clk_functions { | |||
| 99 | long (*clk_round_rate)(struct clk *clk, unsigned long rate); | 108 | long (*clk_round_rate)(struct clk *clk, unsigned long rate); |
| 100 | int (*clk_set_rate)(struct clk *clk, unsigned long rate); | 109 | int (*clk_set_rate)(struct clk *clk, unsigned long rate); |
| 101 | int (*clk_set_parent)(struct clk *clk, struct clk *parent); | 110 | int (*clk_set_parent)(struct clk *clk, struct clk *parent); |
| 102 | struct clk * (*clk_get_parent)(struct clk *clk); | ||
| 103 | void (*clk_allow_idle)(struct clk *clk); | 111 | void (*clk_allow_idle)(struct clk *clk); |
| 104 | void (*clk_deny_idle)(struct clk *clk); | 112 | void (*clk_deny_idle)(struct clk *clk); |
| 105 | void (*clk_disable_unused)(struct clk *clk); | 113 | void (*clk_disable_unused)(struct clk *clk); |
| @@ -110,42 +118,33 @@ struct clk_functions { | |||
| 110 | 118 | ||
| 111 | extern unsigned int mpurate; | 119 | extern unsigned int mpurate; |
| 112 | 120 | ||
| 113 | extern int clk_init(struct clk_functions * custom_clocks); | 121 | extern int clk_init(struct clk_functions *custom_clocks); |
| 122 | extern void clk_init_one(struct clk *clk); | ||
| 114 | extern int clk_register(struct clk *clk); | 123 | extern int clk_register(struct clk *clk); |
| 124 | extern void clk_reparent(struct clk *child, struct clk *parent); | ||
| 115 | extern void clk_unregister(struct clk *clk); | 125 | extern void clk_unregister(struct clk *clk); |
| 116 | extern void propagate_rate(struct clk *clk); | 126 | extern void propagate_rate(struct clk *clk); |
| 117 | extern void recalculate_root_clocks(void); | 127 | extern void recalculate_root_clocks(void); |
| 118 | extern void followparent_recalc(struct clk * clk); | 128 | extern unsigned long followparent_recalc(struct clk *clk); |
| 119 | extern void clk_allow_idle(struct clk *clk); | ||
| 120 | extern void clk_deny_idle(struct clk *clk); | ||
| 121 | extern int clk_get_usecount(struct clk *clk); | ||
| 122 | extern void clk_enable_init_clocks(void); | 129 | extern void clk_enable_init_clocks(void); |
| 130 | #ifdef CONFIG_CPU_FREQ | ||
| 131 | extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table); | ||
| 132 | #endif | ||
| 133 | |||
| 134 | extern const struct clkops clkops_null; | ||
| 123 | 135 | ||
| 124 | /* Clock flags */ | 136 | /* Clock flags */ |
| 125 | #define RATE_CKCTL (1 << 0) /* Main fixed ratio clocks */ | 137 | /* bit 0 is free */ |
| 126 | #define RATE_FIXED (1 << 1) /* Fixed clock rate */ | 138 | #define RATE_FIXED (1 << 1) /* Fixed clock rate */ |
| 127 | #define RATE_PROPAGATES (1 << 2) /* Program children too */ | 139 | /* bits 2-4 are free */ |
| 128 | #define VIRTUAL_CLOCK (1 << 3) /* Composite clock from table */ | ||
| 129 | #define ALWAYS_ENABLED (1 << 4) /* Clock cannot be disabled */ | ||
| 130 | #define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ | 140 | #define ENABLE_REG_32BIT (1 << 5) /* Use 32-bit access */ |
| 131 | #define VIRTUAL_IO_ADDRESS (1 << 6) /* Clock in virtual address */ | ||
| 132 | #define CLOCK_IDLE_CONTROL (1 << 7) | 141 | #define CLOCK_IDLE_CONTROL (1 << 7) |
| 133 | #define CLOCK_NO_IDLE_PARENT (1 << 8) | 142 | #define CLOCK_NO_IDLE_PARENT (1 << 8) |
| 134 | #define DELAYED_APP (1 << 9) /* Delay application of clock */ | 143 | #define DELAYED_APP (1 << 9) /* Delay application of clock */ |
| 135 | #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ | 144 | #define CONFIG_PARTICIPANT (1 << 10) /* Fundamental clock */ |
| 136 | #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ | 145 | #define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */ |
| 137 | #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ | 146 | #define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */ |
| 138 | /* bits 13-20 are currently free */ | 147 | /* bits 13-31 are currently free */ |
| 139 | #define CLOCK_IN_OMAP310 (1 << 21) | ||
| 140 | #define CLOCK_IN_OMAP730 (1 << 22) | ||
| 141 | #define CLOCK_IN_OMAP1510 (1 << 23) | ||
| 142 | #define CLOCK_IN_OMAP16XX (1 << 24) | ||
| 143 | #define CLOCK_IN_OMAP242X (1 << 25) | ||
| 144 | #define CLOCK_IN_OMAP243X (1 << 26) | ||
| 145 | #define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */ | ||
| 146 | #define PARENT_CONTROLS_CLOCK (1 << 28) | ||
| 147 | #define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */ | ||
| 148 | #define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */ | ||
| 149 | 148 | ||
| 150 | /* Clksel_rate flags */ | 149 | /* Clksel_rate flags */ |
| 151 | #define DEFAULT_RATE (1 << 0) | 150 | #define DEFAULT_RATE (1 << 0) |
| @@ -157,9 +156,4 @@ extern void clk_enable_init_clocks(void); | |||
| 157 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) | 156 | #define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X) |
| 158 | 157 | ||
| 159 | 158 | ||
| 160 | /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */ | ||
| 161 | #define CORE_CLK_SRC_32K 0 | ||
| 162 | #define CORE_CLK_SRC_DPLL 1 | ||
| 163 | #define CORE_CLK_SRC_DPLL_X2 2 | ||
| 164 | |||
| 165 | #endif | 159 | #endif |
diff --git a/arch/arm/plat-omap/include/mach/clockdomain.h b/arch/arm/plat-omap/include/mach/clockdomain.h index 1f51f0173784..b9d0dd2da89b 100644 --- a/arch/arm/plat-omap/include/mach/clockdomain.h +++ b/arch/arm/plat-omap/include/mach/clockdomain.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/include/asm-arm/arch-omap/clockdomain.h | 2 | * arch/arm/plat-omap/include/mach/clockdomain.h |
| 3 | * | 3 | * |
| 4 | * OMAP2/3 clockdomain framework functions | 4 | * OMAP2/3 clockdomain framework functions |
| 5 | * | 5 | * |
| @@ -48,11 +48,13 @@ | |||
| 48 | */ | 48 | */ |
| 49 | struct clkdm_pwrdm_autodep { | 49 | struct clkdm_pwrdm_autodep { |
| 50 | 50 | ||
| 51 | /* Name of the powerdomain to add a wkdep/sleepdep on */ | 51 | union { |
| 52 | const char *pwrdm_name; | 52 | /* Name of the powerdomain to add a wkdep/sleepdep on */ |
| 53 | const char *name; | ||
| 53 | 54 | ||
| 54 | /* Powerdomain pointer (looked up at clkdm_init() time) */ | 55 | /* Powerdomain pointer (looked up at clkdm_init() time) */ |
| 55 | struct powerdomain *pwrdm; | 56 | struct powerdomain *ptr; |
| 57 | } pwrdm; | ||
| 56 | 58 | ||
| 57 | /* OMAP chip types that this clockdomain dep is valid on */ | 59 | /* OMAP chip types that this clockdomain dep is valid on */ |
| 58 | const struct omap_chip_id omap_chip; | 60 | const struct omap_chip_id omap_chip; |
| @@ -64,8 +66,13 @@ struct clockdomain { | |||
| 64 | /* Clockdomain name */ | 66 | /* Clockdomain name */ |
| 65 | const char *name; | 67 | const char *name; |
| 66 | 68 | ||
| 67 | /* Powerdomain enclosing this clockdomain */ | 69 | union { |
| 68 | const char *pwrdm_name; | 70 | /* Powerdomain enclosing this clockdomain */ |
| 71 | const char *name; | ||
| 72 | |||
| 73 | /* Powerdomain pointer assigned at clkdm_register() */ | ||
| 74 | struct powerdomain *ptr; | ||
| 75 | } pwrdm; | ||
| 69 | 76 | ||
| 70 | /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */ | 77 | /* CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg */ |
| 71 | const u16 clktrctrl_mask; | 78 | const u16 clktrctrl_mask; |
| @@ -79,9 +86,6 @@ struct clockdomain { | |||
| 79 | /* Usecount tracking */ | 86 | /* Usecount tracking */ |
| 80 | atomic_t usecount; | 87 | atomic_t usecount; |
| 81 | 88 | ||
| 82 | /* Powerdomain pointer assigned at clkdm_register() */ | ||
| 83 | struct powerdomain *pwrdm; | ||
| 84 | |||
| 85 | struct list_head node; | 89 | struct list_head node; |
| 86 | 90 | ||
| 87 | }; | 91 | }; |
diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/mach/common.h index ef70e2b0f054..0ecf36deb17b 100644 --- a/arch/arm/plat-omap/include/mach/common.h +++ b/arch/arm/plat-omap/include/mach/common.h | |||
| @@ -35,7 +35,7 @@ extern void omap_map_common_io(void); | |||
| 35 | extern struct sys_timer omap_timer; | 35 | extern struct sys_timer omap_timer; |
| 36 | extern void omap_serial_init(void); | 36 | extern void omap_serial_init(void); |
| 37 | extern void omap_serial_enable_clocks(int enable); | 37 | extern void omap_serial_enable_clocks(int enable); |
| 38 | #ifdef CONFIG_I2C_OMAP | 38 | #if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE) |
| 39 | extern int omap_register_i2c_bus(int bus_id, u32 clkrate, | 39 | extern int omap_register_i2c_bus(int bus_id, u32 clkrate, |
| 40 | struct i2c_board_info const *info, | 40 | struct i2c_board_info const *info, |
| 41 | unsigned len); | 41 | unsigned len); |
| @@ -65,7 +65,7 @@ void omap2_set_globals_343x(void); | |||
| 65 | 65 | ||
| 66 | /* These get called from omap2_set_globals_xxxx(), do not call these */ | 66 | /* These get called from omap2_set_globals_xxxx(), do not call these */ |
| 67 | void omap2_set_globals_tap(struct omap_globals *); | 67 | void omap2_set_globals_tap(struct omap_globals *); |
| 68 | void omap2_set_globals_memory(struct omap_globals *); | 68 | void omap2_set_globals_sdrc(struct omap_globals *); |
| 69 | void omap2_set_globals_control(struct omap_globals *); | 69 | void omap2_set_globals_control(struct omap_globals *); |
| 70 | void omap2_set_globals_prcm(struct omap_globals *); | 70 | void omap2_set_globals_prcm(struct omap_globals *); |
| 71 | 71 | ||
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h index a8e1178a9468..98b144252364 100644 --- a/arch/arm/plat-omap/include/mach/cpu.h +++ b/arch/arm/plat-omap/include/mach/cpu.h | |||
| @@ -56,6 +56,14 @@ unsigned int omap_rev(void); | |||
| 56 | # define OMAP_NAME omap730 | 56 | # define OMAP_NAME omap730 |
| 57 | # endif | 57 | # endif |
| 58 | #endif | 58 | #endif |
| 59 | #ifdef CONFIG_ARCH_OMAP850 | ||
| 60 | # ifdef OMAP_NAME | ||
| 61 | # undef MULTI_OMAP1 | ||
| 62 | # define MULTI_OMAP1 | ||
| 63 | # else | ||
| 64 | # define OMAP_NAME omap850 | ||
| 65 | # endif | ||
| 66 | #endif | ||
| 59 | #ifdef CONFIG_ARCH_OMAP15XX | 67 | #ifdef CONFIG_ARCH_OMAP15XX |
| 60 | # ifdef OMAP_NAME | 68 | # ifdef OMAP_NAME |
| 61 | # undef MULTI_OMAP1 | 69 | # undef MULTI_OMAP1 |
| @@ -105,7 +113,7 @@ unsigned int omap_rev(void); | |||
| 105 | /* | 113 | /* |
| 106 | * Macros to group OMAP into cpu classes. | 114 | * Macros to group OMAP into cpu classes. |
| 107 | * These can be used in most places. | 115 | * These can be used in most places. |
| 108 | * cpu_is_omap7xx(): True for OMAP730 | 116 | * cpu_is_omap7xx(): True for OMAP730, OMAP850 |
| 109 | * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310 | 117 | * cpu_is_omap15xx(): True for OMAP1510, OMAP5910 and OMAP310 |
| 110 | * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710 | 118 | * cpu_is_omap16xx(): True for OMAP1610, OMAP5912 and OMAP1710 |
| 111 | * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430 | 119 | * cpu_is_omap24xx(): True for OMAP2420, OMAP2422, OMAP2423, OMAP2430 |
| @@ -153,6 +161,10 @@ IS_OMAP_SUBCLASS(343x, 0x343) | |||
| 153 | # undef cpu_is_omap7xx | 161 | # undef cpu_is_omap7xx |
| 154 | # define cpu_is_omap7xx() is_omap7xx() | 162 | # define cpu_is_omap7xx() is_omap7xx() |
| 155 | # endif | 163 | # endif |
| 164 | # if defined(CONFIG_ARCH_OMAP850) | ||
| 165 | # undef cpu_is_omap7xx | ||
| 166 | # define cpu_is_omap7xx() is_omap7xx() | ||
| 167 | # endif | ||
| 156 | # if defined(CONFIG_ARCH_OMAP15XX) | 168 | # if defined(CONFIG_ARCH_OMAP15XX) |
| 157 | # undef cpu_is_omap15xx | 169 | # undef cpu_is_omap15xx |
| 158 | # define cpu_is_omap15xx() is_omap15xx() | 170 | # define cpu_is_omap15xx() is_omap15xx() |
| @@ -166,6 +178,10 @@ IS_OMAP_SUBCLASS(343x, 0x343) | |||
| 166 | # undef cpu_is_omap7xx | 178 | # undef cpu_is_omap7xx |
| 167 | # define cpu_is_omap7xx() 1 | 179 | # define cpu_is_omap7xx() 1 |
| 168 | # endif | 180 | # endif |
| 181 | # if defined(CONFIG_ARCH_OMAP850) | ||
| 182 | # undef cpu_is_omap7xx | ||
| 183 | # define cpu_is_omap7xx() 1 | ||
| 184 | # endif | ||
| 169 | # if defined(CONFIG_ARCH_OMAP15XX) | 185 | # if defined(CONFIG_ARCH_OMAP15XX) |
| 170 | # undef cpu_is_omap15xx | 186 | # undef cpu_is_omap15xx |
| 171 | # define cpu_is_omap15xx() 1 | 187 | # define cpu_is_omap15xx() 1 |
| @@ -219,6 +235,7 @@ IS_OMAP_SUBCLASS(343x, 0x343) | |||
| 219 | * These are only rarely needed. | 235 | * These are only rarely needed. |
| 220 | * cpu_is_omap330(): True for OMAP330 | 236 | * cpu_is_omap330(): True for OMAP330 |
| 221 | * cpu_is_omap730(): True for OMAP730 | 237 | * cpu_is_omap730(): True for OMAP730 |
| 238 | * cpu_is_omap850(): True for OMAP850 | ||
| 222 | * cpu_is_omap1510(): True for OMAP1510 | 239 | * cpu_is_omap1510(): True for OMAP1510 |
| 223 | * cpu_is_omap1610(): True for OMAP1610 | 240 | * cpu_is_omap1610(): True for OMAP1610 |
| 224 | * cpu_is_omap1611(): True for OMAP1611 | 241 | * cpu_is_omap1611(): True for OMAP1611 |
| @@ -241,6 +258,7 @@ static inline int is_omap ##type (void) \ | |||
| 241 | 258 | ||
| 242 | IS_OMAP_TYPE(310, 0x0310) | 259 | IS_OMAP_TYPE(310, 0x0310) |
| 243 | IS_OMAP_TYPE(730, 0x0730) | 260 | IS_OMAP_TYPE(730, 0x0730) |
| 261 | IS_OMAP_TYPE(850, 0x0850) | ||
| 244 | IS_OMAP_TYPE(1510, 0x1510) | 262 | IS_OMAP_TYPE(1510, 0x1510) |
| 245 | IS_OMAP_TYPE(1610, 0x1610) | 263 | IS_OMAP_TYPE(1610, 0x1610) |
| 246 | IS_OMAP_TYPE(1611, 0x1611) | 264 | IS_OMAP_TYPE(1611, 0x1611) |
| @@ -255,6 +273,7 @@ IS_OMAP_TYPE(3430, 0x3430) | |||
| 255 | 273 | ||
| 256 | #define cpu_is_omap310() 0 | 274 | #define cpu_is_omap310() 0 |
| 257 | #define cpu_is_omap730() 0 | 275 | #define cpu_is_omap730() 0 |
| 276 | #define cpu_is_omap850() 0 | ||
| 258 | #define cpu_is_omap1510() 0 | 277 | #define cpu_is_omap1510() 0 |
| 259 | #define cpu_is_omap1610() 0 | 278 | #define cpu_is_omap1610() 0 |
| 260 | #define cpu_is_omap5912() 0 | 279 | #define cpu_is_omap5912() 0 |
| @@ -272,12 +291,22 @@ IS_OMAP_TYPE(3430, 0x3430) | |||
| 272 | # undef cpu_is_omap730 | 291 | # undef cpu_is_omap730 |
| 273 | # define cpu_is_omap730() is_omap730() | 292 | # define cpu_is_omap730() is_omap730() |
| 274 | # endif | 293 | # endif |
| 294 | # if defined(CONFIG_ARCH_OMAP850) | ||
| 295 | # undef cpu_is_omap850 | ||
| 296 | # define cpu_is_omap850() is_omap850() | ||
| 297 | # endif | ||
| 275 | #else | 298 | #else |
| 276 | # if defined(CONFIG_ARCH_OMAP730) | 299 | # if defined(CONFIG_ARCH_OMAP730) |
| 277 | # undef cpu_is_omap730 | 300 | # undef cpu_is_omap730 |
| 278 | # define cpu_is_omap730() 1 | 301 | # define cpu_is_omap730() 1 |
| 279 | # endif | 302 | # endif |
| 280 | #endif | 303 | #endif |
| 304 | #else | ||
| 305 | # if defined(CONFIG_ARCH_OMAP850) | ||
| 306 | # undef cpu_is_omap850 | ||
| 307 | # define cpu_is_omap850() 1 | ||
| 308 | # endif | ||
| 309 | #endif | ||
| 281 | 310 | ||
| 282 | /* | 311 | /* |
| 283 | * Whether we have MULTI_OMAP1 or not, we still need to distinguish | 312 | * Whether we have MULTI_OMAP1 or not, we still need to distinguish |
| @@ -320,7 +349,7 @@ IS_OMAP_TYPE(3430, 0x3430) | |||
| 320 | #endif | 349 | #endif |
| 321 | 350 | ||
| 322 | /* Macros to detect if we have OMAP1 or OMAP2 */ | 351 | /* Macros to detect if we have OMAP1 or OMAP2 */ |
| 323 | #define cpu_class_is_omap1() (cpu_is_omap730() || cpu_is_omap15xx() || \ | 352 | #define cpu_class_is_omap1() (cpu_is_omap7xx() || cpu_is_omap15xx() || \ |
| 324 | cpu_is_omap16xx()) | 353 | cpu_is_omap16xx()) |
| 325 | #define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx()) | 354 | #define cpu_class_is_omap2() (cpu_is_omap24xx() || cpu_is_omap34xx()) |
| 326 | 355 | ||
| @@ -355,13 +384,27 @@ IS_OMAP_TYPE(3430, 0x3430) | |||
| 355 | * use omap_chip_is(). | 384 | * use omap_chip_is(). |
| 356 | * | 385 | * |
| 357 | */ | 386 | */ |
| 358 | #define CHIP_IS_OMAP2420 (1 << 0) | 387 | #define CHIP_IS_OMAP2420 (1 << 0) |
| 359 | #define CHIP_IS_OMAP2430 (1 << 1) | 388 | #define CHIP_IS_OMAP2430 (1 << 1) |
| 360 | #define CHIP_IS_OMAP3430 (1 << 2) | 389 | #define CHIP_IS_OMAP3430 (1 << 2) |
| 361 | #define CHIP_IS_OMAP3430ES1 (1 << 3) | 390 | #define CHIP_IS_OMAP3430ES1 (1 << 3) |
| 362 | #define CHIP_IS_OMAP3430ES2 (1 << 4) | 391 | #define CHIP_IS_OMAP3430ES2 (1 << 4) |
| 392 | #define CHIP_IS_OMAP3430ES3_0 (1 << 5) | ||
| 393 | #define CHIP_IS_OMAP3430ES3_1 (1 << 6) | ||
| 394 | |||
| 395 | #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) | ||
| 396 | |||
| 397 | /* | ||
| 398 | * "GE" here represents "greater than or equal to" in terms of ES | ||
| 399 | * levels. So CHIP_GE_OMAP3430ES2 is intended to match all OMAP3430 | ||
| 400 | * chips at ES2 and beyond, but not, for example, any OMAP lines after | ||
| 401 | * OMAP3. | ||
| 402 | */ | ||
| 403 | #define CHIP_GE_OMAP3430ES2 (CHIP_IS_OMAP3430ES2 | \ | ||
| 404 | CHIP_IS_OMAP3430ES3_0 | \ | ||
| 405 | CHIP_IS_OMAP3430ES3_1) | ||
| 406 | #define CHIP_GE_OMAP3430ES3_1 (CHIP_IS_OMAP3430ES3_1) | ||
| 363 | 407 | ||
| 364 | #define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430) | ||
| 365 | 408 | ||
| 366 | int omap_chip_is(struct omap_chip_id oci); | 409 | int omap_chip_is(struct omap_chip_id oci); |
| 367 | int omap_type(void); | 410 | int omap_type(void); |
| @@ -378,5 +421,3 @@ int omap_type(void); | |||
| 378 | void omap2_check_revision(void); | 421 | void omap2_check_revision(void); |
| 379 | 422 | ||
| 380 | #endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */ | 423 | #endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */ |
| 381 | |||
| 382 | #endif | ||
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h index 8d9dfe314387..2b22a8799bc6 100644 --- a/arch/arm/plat-omap/include/mach/gpio.h +++ b/arch/arm/plat-omap/include/mach/gpio.h | |||
| @@ -31,7 +31,8 @@ | |||
| 31 | 31 | ||
| 32 | #define OMAP_MPUIO_BASE 0xfffb5000 | 32 | #define OMAP_MPUIO_BASE 0xfffb5000 |
| 33 | 33 | ||
| 34 | #ifdef CONFIG_ARCH_OMAP730 | 34 | #if (defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)) |
| 35 | |||
| 35 | #define OMAP_MPUIO_INPUT_LATCH 0x00 | 36 | #define OMAP_MPUIO_INPUT_LATCH 0x00 |
| 36 | #define OMAP_MPUIO_OUTPUT 0x02 | 37 | #define OMAP_MPUIO_OUTPUT 0x02 |
| 37 | #define OMAP_MPUIO_IO_CNTL 0x04 | 38 | #define OMAP_MPUIO_IO_CNTL 0x04 |
diff --git a/arch/arm/plat-omap/include/mach/gpmc.h b/arch/arm/plat-omap/include/mach/gpmc.h index 45b678439bb7..921b16532ff5 100644 --- a/arch/arm/plat-omap/include/mach/gpmc.h +++ b/arch/arm/plat-omap/include/mach/gpmc.h | |||
| @@ -103,6 +103,6 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); | |||
| 103 | extern void gpmc_cs_free(int cs); | 103 | extern void gpmc_cs_free(int cs); |
| 104 | extern int gpmc_cs_set_reserved(int cs, int reserved); | 104 | extern int gpmc_cs_set_reserved(int cs, int reserved); |
| 105 | extern int gpmc_cs_reserved(int cs); | 105 | extern int gpmc_cs_reserved(int cs); |
| 106 | extern void gpmc_init(void); | 106 | extern void __init gpmc_init(void); |
| 107 | 107 | ||
| 108 | #endif | 108 | #endif |
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h index 6589ddbb63b2..3dc423ed3e80 100644 --- a/arch/arm/plat-omap/include/mach/hardware.h +++ b/arch/arm/plat-omap/include/mach/hardware.h | |||
| @@ -286,78 +286,4 @@ | |||
| 286 | #include "omap24xx.h" | 286 | #include "omap24xx.h" |
| 287 | #include "omap34xx.h" | 287 | #include "omap34xx.h" |
| 288 | 288 | ||
| 289 | #ifndef __ASSEMBLER__ | ||
| 290 | |||
| 291 | /* | ||
| 292 | * --------------------------------------------------------------------------- | ||
| 293 | * Board specific defines | ||
| 294 | * --------------------------------------------------------------------------- | ||
| 295 | */ | ||
| 296 | |||
| 297 | #ifdef CONFIG_MACH_OMAP_INNOVATOR | ||
| 298 | #include "board-innovator.h" | ||
| 299 | #endif | ||
| 300 | |||
| 301 | #ifdef CONFIG_MACH_OMAP_H2 | ||
| 302 | #include "board-h2.h" | ||
| 303 | #endif | ||
| 304 | |||
| 305 | #ifdef CONFIG_MACH_OMAP_PERSEUS2 | ||
| 306 | #include "board-perseus2.h" | ||
| 307 | #endif | ||
| 308 | |||
| 309 | #ifdef CONFIG_MACH_OMAP_FSAMPLE | ||
| 310 | #include "board-fsample.h" | ||
| 311 | #endif | ||
| 312 | |||
| 313 | #ifdef CONFIG_MACH_OMAP_H3 | ||
| 314 | #include "board-h3.h" | ||
| 315 | #endif | ||
| 316 | |||
| 317 | #ifdef CONFIG_MACH_OMAP_H4 | ||
| 318 | #include "board-h4.h" | ||
| 319 | #endif | ||
| 320 | |||
| 321 | #ifdef CONFIG_MACH_OMAP_2430SDP | ||
| 322 | #include "board-2430sdp.h" | ||
| 323 | #endif | ||
| 324 | |||
| 325 | #ifdef CONFIG_MACH_OMAP3_BEAGLE | ||
| 326 | #include "board-omap3beagle.h" | ||
| 327 | #endif | ||
| 328 | |||
| 329 | #ifdef CONFIG_MACH_OMAP_LDP | ||
| 330 | #include "board-ldp.h" | ||
| 331 | #endif | ||
| 332 | |||
| 333 | #ifdef CONFIG_MACH_OMAP_APOLLON | ||
| 334 | #include "board-apollon.h" | ||
| 335 | #endif | ||
| 336 | |||
| 337 | #ifdef CONFIG_MACH_OMAP_OSK | ||
| 338 | #include "board-osk.h" | ||
| 339 | #endif | ||
| 340 | |||
| 341 | #ifdef CONFIG_MACH_VOICEBLUE | ||
| 342 | #include "board-voiceblue.h" | ||
| 343 | #endif | ||
| 344 | |||
| 345 | #ifdef CONFIG_MACH_OMAP_PALMTE | ||
| 346 | #include "board-palmte.h" | ||
| 347 | #endif | ||
| 348 | |||
| 349 | #ifdef CONFIG_MACH_OMAP_PALMZ71 | ||
| 350 | #include "board-palmz71.h" | ||
| 351 | #endif | ||
| 352 | |||
| 353 | #ifdef CONFIG_MACH_OMAP_PALMTT | ||
| 354 | #include "board-palmtt.h" | ||
| 355 | #endif | ||
| 356 | |||
| 357 | #ifdef CONFIG_MACH_SX1 | ||
| 358 | #include "board-sx1.h" | ||
| 359 | #endif | ||
| 360 | |||
| 361 | #endif /* !__ASSEMBLER__ */ | ||
| 362 | |||
| 363 | #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ | 289 | #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ |
diff --git a/arch/arm/plat-omap/include/mach/io.h b/arch/arm/plat-omap/include/mach/io.h index d92bf7964481..0610d7e2b3d7 100644 --- a/arch/arm/plat-omap/include/mach/io.h +++ b/arch/arm/plat-omap/include/mach/io.h | |||
| @@ -185,11 +185,13 @@ | |||
| 185 | #define omap_writew(v,a) __raw_writew(v, IO_ADDRESS(a)) | 185 | #define omap_writew(v,a) __raw_writew(v, IO_ADDRESS(a)) |
| 186 | #define omap_writel(v,a) __raw_writel(v, IO_ADDRESS(a)) | 186 | #define omap_writel(v,a) __raw_writel(v, IO_ADDRESS(a)) |
| 187 | 187 | ||
| 188 | struct omap_sdrc_params; | ||
| 189 | |||
| 188 | extern void omap1_map_common_io(void); | 190 | extern void omap1_map_common_io(void); |
| 189 | extern void omap1_init_common_hw(void); | 191 | extern void omap1_init_common_hw(void); |
| 190 | 192 | ||
| 191 | extern void omap2_map_common_io(void); | 193 | extern void omap2_map_common_io(void); |
| 192 | extern void omap2_init_common_hw(void); | 194 | extern void omap2_init_common_hw(struct omap_sdrc_params *sp); |
| 193 | 195 | ||
| 194 | #define __arch_ioremap(p,s,t) omap_ioremap(p,s,t) | 196 | #define __arch_ioremap(p,s,t) omap_ioremap(p,s,t) |
| 195 | #define __arch_iounmap(v) omap_iounmap(v) | 197 | #define __arch_iounmap(v) omap_iounmap(v) |
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h index bed5274c910a..7f57ee66f364 100644 --- a/arch/arm/plat-omap/include/mach/irqs.h +++ b/arch/arm/plat-omap/include/mach/irqs.h | |||
| @@ -105,6 +105,29 @@ | |||
| 105 | #define INT_730_SPGIO_WR 29 | 105 | #define INT_730_SPGIO_WR 29 |
| 106 | 106 | ||
| 107 | /* | 107 | /* |
| 108 | * OMAP-850 specific IRQ numbers for interrupt handler 1 | ||
| 109 | */ | ||
| 110 | #define INT_850_IH2_FIQ 0 | ||
| 111 | #define INT_850_IH2_IRQ 1 | ||
| 112 | #define INT_850_USB_NON_ISO 2 | ||
| 113 | #define INT_850_USB_ISO 3 | ||
| 114 | #define INT_850_ICR 4 | ||
| 115 | #define INT_850_EAC 5 | ||
| 116 | #define INT_850_GPIO_BANK1 6 | ||
| 117 | #define INT_850_GPIO_BANK2 7 | ||
| 118 | #define INT_850_GPIO_BANK3 8 | ||
| 119 | #define INT_850_McBSP2TX 10 | ||
| 120 | #define INT_850_McBSP2RX 11 | ||
| 121 | #define INT_850_McBSP2RX_OVF 12 | ||
| 122 | #define INT_850_LCD_LINE 14 | ||
| 123 | #define INT_850_GSM_PROTECT 15 | ||
| 124 | #define INT_850_TIMER3 16 | ||
| 125 | #define INT_850_GPIO_BANK5 17 | ||
| 126 | #define INT_850_GPIO_BANK6 18 | ||
| 127 | #define INT_850_SPGIO_WR 29 | ||
| 128 | |||
| 129 | |||
| 130 | /* | ||
| 108 | * IRQ numbers for interrupt handler 2 | 131 | * IRQ numbers for interrupt handler 2 |
| 109 | * | 132 | * |
| 110 | * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below | 133 | * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below |
| @@ -237,6 +260,64 @@ | |||
| 237 | #define INT_730_DMA_CH15 (62 + IH2_BASE) | 260 | #define INT_730_DMA_CH15 (62 + IH2_BASE) |
| 238 | #define INT_730_NAND (63 + IH2_BASE) | 261 | #define INT_730_NAND (63 + IH2_BASE) |
| 239 | 262 | ||
| 263 | /* | ||
| 264 | * OMAP-850 specific IRQ numbers for interrupt handler 2 | ||
| 265 | */ | ||
| 266 | #define INT_850_HW_ERRORS (0 + IH2_BASE) | ||
| 267 | #define INT_850_NFIQ_PWR_FAIL (1 + IH2_BASE) | ||
| 268 | #define INT_850_CFCD (2 + IH2_BASE) | ||
| 269 | #define INT_850_CFIREQ (3 + IH2_BASE) | ||
| 270 | #define INT_850_I2C (4 + IH2_BASE) | ||
| 271 | #define INT_850_PCC (5 + IH2_BASE) | ||
| 272 | #define INT_850_MPU_EXT_NIRQ (6 + IH2_BASE) | ||
| 273 | #define INT_850_SPI_100K_1 (7 + IH2_BASE) | ||
| 274 | #define INT_850_SYREN_SPI (8 + IH2_BASE) | ||
| 275 | #define INT_850_VLYNQ (9 + IH2_BASE) | ||
| 276 | #define INT_850_GPIO_BANK4 (10 + IH2_BASE) | ||
| 277 | #define INT_850_McBSP1TX (11 + IH2_BASE) | ||
| 278 | #define INT_850_McBSP1RX (12 + IH2_BASE) | ||
| 279 | #define INT_850_McBSP1RX_OF (13 + IH2_BASE) | ||
| 280 | #define INT_850_UART_MODEM_IRDA_2 (14 + IH2_BASE) | ||
| 281 | #define INT_850_UART_MODEM_1 (15 + IH2_BASE) | ||
| 282 | #define INT_850_MCSI (16 + IH2_BASE) | ||
| 283 | #define INT_850_uWireTX (17 + IH2_BASE) | ||
| 284 | #define INT_850_uWireRX (18 + IH2_BASE) | ||
| 285 | #define INT_850_SMC_CD (19 + IH2_BASE) | ||
| 286 | #define INT_850_SMC_IREQ (20 + IH2_BASE) | ||
| 287 | #define INT_850_HDQ_1WIRE (21 + IH2_BASE) | ||
| 288 | #define INT_850_TIMER32K (22 + IH2_BASE) | ||
| 289 | #define INT_850_MMC_SDIO (23 + IH2_BASE) | ||
| 290 | #define INT_850_UPLD (24 + IH2_BASE) | ||
| 291 | #define INT_850_USB_HHC_1 (27 + IH2_BASE) | ||
| 292 | #define INT_850_USB_HHC_2 (28 + IH2_BASE) | ||
| 293 | #define INT_850_USB_GENI (29 + IH2_BASE) | ||
| 294 | #define INT_850_USB_OTG (30 + IH2_BASE) | ||
| 295 | #define INT_850_CAMERA_IF (31 + IH2_BASE) | ||
| 296 | #define INT_850_RNG (32 + IH2_BASE) | ||
| 297 | #define INT_850_DUAL_MODE_TIMER (33 + IH2_BASE) | ||
| 298 | #define INT_850_DBB_RF_EN (34 + IH2_BASE) | ||
| 299 | #define INT_850_MPUIO_KEYPAD (35 + IH2_BASE) | ||
| 300 | #define INT_850_SHA1_MD5 (36 + IH2_BASE) | ||
| 301 | #define INT_850_SPI_100K_2 (37 + IH2_BASE) | ||
| 302 | #define INT_850_RNG_IDLE (38 + IH2_BASE) | ||
| 303 | #define INT_850_MPUIO (39 + IH2_BASE) | ||
| 304 | #define INT_850_LLPC_LCD_CTRL_CAN_BE_OFF (40 + IH2_BASE) | ||
| 305 | #define INT_850_LLPC_OE_FALLING (41 + IH2_BASE) | ||
| 306 | #define INT_850_LLPC_OE_RISING (42 + IH2_BASE) | ||
| 307 | #define INT_850_LLPC_VSYNC (43 + IH2_BASE) | ||
| 308 | #define INT_850_WAKE_UP_REQ (46 + IH2_BASE) | ||
| 309 | #define INT_850_DMA_CH6 (53 + IH2_BASE) | ||
| 310 | #define INT_850_DMA_CH7 (54 + IH2_BASE) | ||
| 311 | #define INT_850_DMA_CH8 (55 + IH2_BASE) | ||
| 312 | #define INT_850_DMA_CH9 (56 + IH2_BASE) | ||
| 313 | #define INT_850_DMA_CH10 (57 + IH2_BASE) | ||
| 314 | #define INT_850_DMA_CH11 (58 + IH2_BASE) | ||
| 315 | #define INT_850_DMA_CH12 (59 + IH2_BASE) | ||
| 316 | #define INT_850_DMA_CH13 (60 + IH2_BASE) | ||
| 317 | #define INT_850_DMA_CH14 (61 + IH2_BASE) | ||
| 318 | #define INT_850_DMA_CH15 (62 + IH2_BASE) | ||
| 319 | #define INT_850_NAND (63 + IH2_BASE) | ||
| 320 | |||
| 240 | #define INT_24XX_SYS_NIRQ 7 | 321 | #define INT_24XX_SYS_NIRQ 7 |
| 241 | #define INT_24XX_SDMA_IRQ0 12 | 322 | #define INT_24XX_SDMA_IRQ0 12 |
| 242 | #define INT_24XX_SDMA_IRQ1 13 | 323 | #define INT_24XX_SDMA_IRQ1 13 |
| @@ -341,7 +422,7 @@ | |||
| 341 | 422 | ||
| 342 | #define INT_34XX_BENCH_MPU_EMUL 3 | 423 | #define INT_34XX_BENCH_MPU_EMUL 3 |
| 343 | 424 | ||
| 344 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and | 425 | /* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730/850) and |
| 345 | * 16 MPUIO lines */ | 426 | * 16 MPUIO lines */ |
| 346 | #define OMAP_MAX_GPIO_LINES 192 | 427 | #define OMAP_MAX_GPIO_LINES 192 |
| 347 | #define IH_GPIO_BASE (128 + IH2_BASE) | 428 | #define IH_GPIO_BASE (128 + IH2_BASE) |
diff --git a/arch/arm/plat-omap/include/mach/mailbox.h b/arch/arm/plat-omap/include/mach/mailbox.h index 7cbed9332e16..b7a6991814ec 100644 --- a/arch/arm/plat-omap/include/mach/mailbox.h +++ b/arch/arm/plat-omap/include/mach/mailbox.h | |||
| @@ -33,6 +33,9 @@ struct omap_mbox_ops { | |||
| 33 | void (*disable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); | 33 | void (*disable_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); |
| 34 | void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); | 34 | void (*ack_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); |
| 35 | int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); | 35 | int (*is_irq)(struct omap_mbox *mbox, omap_mbox_irq_t irq); |
| 36 | /* ctx */ | ||
| 37 | void (*save_ctx)(struct omap_mbox *mbox); | ||
| 38 | void (*restore_ctx)(struct omap_mbox *mbox); | ||
| 36 | }; | 39 | }; |
| 37 | 40 | ||
| 38 | struct omap_mbox_queue { | 41 | struct omap_mbox_queue { |
| @@ -53,7 +56,7 @@ struct omap_mbox { | |||
| 53 | 56 | ||
| 54 | mbox_msg_t seq_snd, seq_rcv; | 57 | mbox_msg_t seq_snd, seq_rcv; |
| 55 | 58 | ||
| 56 | struct device dev; | 59 | struct device *dev; |
| 57 | 60 | ||
| 58 | struct omap_mbox *next; | 61 | struct omap_mbox *next; |
| 59 | void *priv; | 62 | void *priv; |
| @@ -67,7 +70,27 @@ void omap_mbox_init_seq(struct omap_mbox *); | |||
| 67 | struct omap_mbox *omap_mbox_get(const char *); | 70 | struct omap_mbox *omap_mbox_get(const char *); |
| 68 | void omap_mbox_put(struct omap_mbox *); | 71 | void omap_mbox_put(struct omap_mbox *); |
| 69 | 72 | ||
| 70 | int omap_mbox_register(struct omap_mbox *); | 73 | int omap_mbox_register(struct device *parent, struct omap_mbox *); |
| 71 | int omap_mbox_unregister(struct omap_mbox *); | 74 | int omap_mbox_unregister(struct omap_mbox *); |
| 72 | 75 | ||
| 76 | static inline void omap_mbox_save_ctx(struct omap_mbox *mbox) | ||
| 77 | { | ||
| 78 | if (!mbox->ops->save_ctx) { | ||
| 79 | dev_err(mbox->dev, "%s:\tno save\n", __func__); | ||
| 80 | return; | ||
| 81 | } | ||
| 82 | |||
| 83 | mbox->ops->save_ctx(mbox); | ||
| 84 | } | ||
| 85 | |||
| 86 | static inline void omap_mbox_restore_ctx(struct omap_mbox *mbox) | ||
| 87 | { | ||
| 88 | if (!mbox->ops->restore_ctx) { | ||
| 89 | dev_err(mbox->dev, "%s:\tno restore\n", __func__); | ||
| 90 | return; | ||
| 91 | } | ||
| 92 | |||
| 93 | mbox->ops->restore_ctx(mbox); | ||
| 94 | } | ||
| 95 | |||
| 73 | #endif /* MAILBOX_H */ | 96 | #endif /* MAILBOX_H */ |
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h index 113c2466c86a..bb154ea76769 100644 --- a/arch/arm/plat-omap/include/mach/mcbsp.h +++ b/arch/arm/plat-omap/include/mach/mcbsp.h | |||
| @@ -344,8 +344,6 @@ struct omap_mcbsp_platform_data { | |||
| 344 | u8 dma_rx_sync, dma_tx_sync; | 344 | u8 dma_rx_sync, dma_tx_sync; |
| 345 | u16 rx_irq, tx_irq; | 345 | u16 rx_irq, tx_irq; |
| 346 | struct omap_mcbsp_ops *ops; | 346 | struct omap_mcbsp_ops *ops; |
| 347 | char const **clk_names; | ||
| 348 | int num_clks; | ||
| 349 | }; | 347 | }; |
| 350 | 348 | ||
| 351 | struct omap_mcbsp { | 349 | struct omap_mcbsp { |
| @@ -377,8 +375,8 @@ struct omap_mcbsp { | |||
| 377 | /* Protect the field .free, while checking if the mcbsp is in use */ | 375 | /* Protect the field .free, while checking if the mcbsp is in use */ |
| 378 | spinlock_t lock; | 376 | spinlock_t lock; |
| 379 | struct omap_mcbsp_platform_data *pdata; | 377 | struct omap_mcbsp_platform_data *pdata; |
| 380 | struct clk **clks; | 378 | struct clk *iclk; |
| 381 | int num_clks; | 379 | struct clk *fclk; |
| 382 | }; | 380 | }; |
| 383 | extern struct omap_mcbsp **mcbsp_ptr; | 381 | extern struct omap_mcbsp **mcbsp_ptr; |
| 384 | extern int omap_mcbsp_count; | 382 | extern int omap_mcbsp_count; |
diff --git a/arch/arm/plat-omap/include/mach/memory.h b/arch/arm/plat-omap/include/mach/memory.h index d6b5ca6c7da2..99ed564d9277 100644 --- a/arch/arm/plat-omap/include/mach/memory.h +++ b/arch/arm/plat-omap/include/mach/memory.h | |||
| @@ -61,9 +61,11 @@ | |||
| 61 | #define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET) | 61 | #define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET) |
| 62 | #define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0)) | 62 | #define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0)) |
| 63 | 63 | ||
| 64 | #define __arch_page_to_dma(dev, page) ({is_lbus_device(dev) ? \ | 64 | #define __arch_page_to_dma(dev, page) \ |
| 65 | (dma_addr_t)virt_to_lbus(page_address(page)) : \ | 65 | ({ dma_addr_t __dma = page_to_phys(page); \ |
| 66 | (dma_addr_t)__virt_to_phys(page_address(page));}) | 66 | if (is_lbus_device(dev)) \ |
| 67 | __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \ | ||
| 68 | __dma; }) | ||
| 67 | 69 | ||
| 68 | #define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \ | 70 | #define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \ |
| 69 | lbus_to_virt(addr) : \ | 71 | lbus_to_virt(addr) : \ |
diff --git a/arch/arm/plat-omap/include/mach/mmc.h b/arch/arm/plat-omap/include/mach/mmc.h index 73a9e15031b1..4435bd434e17 100644 --- a/arch/arm/plat-omap/include/mach/mmc.h +++ b/arch/arm/plat-omap/include/mach/mmc.h | |||
| @@ -37,6 +37,8 @@ | |||
| 37 | #define OMAP_MMC_MAX_SLOTS 2 | 37 | #define OMAP_MMC_MAX_SLOTS 2 |
| 38 | 38 | ||
| 39 | struct omap_mmc_platform_data { | 39 | struct omap_mmc_platform_data { |
| 40 | /* back-link to device */ | ||
| 41 | struct device *dev; | ||
| 40 | 42 | ||
| 41 | /* number of slots per controller */ | 43 | /* number of slots per controller */ |
| 42 | unsigned nr_slots:2; | 44 | unsigned nr_slots:2; |
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h index f4362b8682c7..85a621705766 100644 --- a/arch/arm/plat-omap/include/mach/mux.h +++ b/arch/arm/plat-omap/include/mach/mux.h | |||
| @@ -61,6 +61,16 @@ | |||
| 61 | .pull_bit = bit, \ | 61 | .pull_bit = bit, \ |
| 62 | .pull_val = status, | 62 | .pull_val = status, |
| 63 | 63 | ||
| 64 | #define MUX_REG_850(reg, mode_offset, mode) .mux_reg_name = "OMAP850_IO_CONF_"#reg, \ | ||
| 65 | .mux_reg = OMAP850_IO_CONF_##reg, \ | ||
| 66 | .mask_offset = mode_offset, \ | ||
| 67 | .mask = mode, | ||
| 68 | |||
| 69 | #define PULL_REG_850(reg, bit, status) .pull_name = "OMAP850_IO_CONF_"#reg, \ | ||
| 70 | .pull_reg = OMAP850_IO_CONF_##reg, \ | ||
| 71 | .pull_bit = bit, \ | ||
| 72 | .pull_val = status, | ||
| 73 | |||
| 64 | #else | 74 | #else |
| 65 | 75 | ||
| 66 | #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ | 76 | #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \ |
| @@ -83,6 +93,15 @@ | |||
| 83 | .pull_bit = bit, \ | 93 | .pull_bit = bit, \ |
| 84 | .pull_val = status, | 94 | .pull_val = status, |
| 85 | 95 | ||
| 96 | #define MUX_REG_850(reg, mode_offset, mode) \ | ||
| 97 | .mux_reg = OMAP850_IO_CONF_##reg, \ | ||
| 98 | .mask_offset = mode_offset, \ | ||
| 99 | .mask = mode, | ||
| 100 | |||
| 101 | #define PULL_REG_850(reg, bit, status) .pull_reg = OMAP850_IO_CONF_##reg, \ | ||
| 102 | .pull_bit = bit, \ | ||
| 103 | .pull_val = status, | ||
| 104 | |||
| 86 | #endif /* CONFIG_OMAP_MUX_DEBUG */ | 105 | #endif /* CONFIG_OMAP_MUX_DEBUG */ |
| 87 | 106 | ||
| 88 | #define MUX_CFG(desc, mux_reg, mode_offset, mode, \ | 107 | #define MUX_CFG(desc, mux_reg, mode_offset, mode, \ |
| @@ -98,7 +117,7 @@ | |||
| 98 | 117 | ||
| 99 | 118 | ||
| 100 | /* | 119 | /* |
| 101 | * OMAP730 has a slightly different config for the pin mux. | 120 | * OMAP730/850 has a slightly different config for the pin mux. |
| 102 | * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and | 121 | * - config regs are the OMAP730_IO_CONF_x regs (see omap730.h) regs and |
| 103 | * not the FUNC_MUX_CTRL_x regs from hardware.h | 122 | * not the FUNC_MUX_CTRL_x regs from hardware.h |
| 104 | * - for pull-up/down, only has one enable bit which is is in the same register | 123 | * - for pull-up/down, only has one enable bit which is is in the same register |
| @@ -114,6 +133,17 @@ | |||
| 114 | PU_PD_REG(NA, 0) \ | 133 | PU_PD_REG(NA, 0) \ |
| 115 | }, | 134 | }, |
| 116 | 135 | ||
| 136 | #define MUX_CFG_850(desc, mux_reg, mode_offset, mode, \ | ||
| 137 | pull_bit, pull_status, debug_status)\ | ||
| 138 | { \ | ||
| 139 | .name = desc, \ | ||
| 140 | .debug = debug_status, \ | ||
| 141 | MUX_REG_850(mux_reg, mode_offset, mode) \ | ||
| 142 | PULL_REG_850(mux_reg, pull_bit, pull_status) \ | ||
| 143 | PU_PD_REG(NA, 0) \ | ||
| 144 | }, | ||
| 145 | |||
| 146 | |||
| 117 | #define MUX_CFG_24XX(desc, reg_offset, mode, \ | 147 | #define MUX_CFG_24XX(desc, reg_offset, mode, \ |
| 118 | pull_en, pull_mode, dbg) \ | 148 | pull_en, pull_mode, dbg) \ |
| 119 | { \ | 149 | { \ |
| @@ -221,6 +251,26 @@ enum omap730_index { | |||
| 221 | W17_730_USB_VBUSI, | 251 | W17_730_USB_VBUSI, |
| 222 | }; | 252 | }; |
| 223 | 253 | ||
| 254 | enum omap850_index { | ||
| 255 | /* OMAP 850 keyboard */ | ||
| 256 | E2_850_KBR0, | ||
| 257 | J7_850_KBR1, | ||
| 258 | E1_850_KBR2, | ||
| 259 | F3_850_KBR3, | ||
| 260 | D2_850_KBR4, | ||
| 261 | C2_850_KBC0, | ||
| 262 | D3_850_KBC1, | ||
| 263 | E4_850_KBC2, | ||
| 264 | F4_850_KBC3, | ||
| 265 | E3_850_KBC4, | ||
| 266 | |||
| 267 | /* USB */ | ||
| 268 | AA17_850_USB_DM, | ||
| 269 | W16_850_USB_PU_EN, | ||
| 270 | W17_850_USB_VBUSI, | ||
| 271 | }; | ||
| 272 | |||
| 273 | |||
| 224 | enum omap1xxx_index { | 274 | enum omap1xxx_index { |
| 225 | /* UART1 (BT_UART_GATING)*/ | 275 | /* UART1 (BT_UART_GATING)*/ |
| 226 | UART1_TX = 0, | 276 | UART1_TX = 0, |
| @@ -788,7 +838,20 @@ enum omap34xx_index { | |||
| 788 | * - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown | 838 | * - "_DOWN" suffix (GPIO3_DOWN) with internal pulldown |
| 789 | * - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx) | 839 | * - "_OUT" suffix (GPIO3_OUT) for output-only pins (unlike 24xx) |
| 790 | */ | 840 | */ |
| 841 | AF26_34XX_GPIO0, | ||
| 842 | AF22_34XX_GPIO9, | ||
| 791 | AH8_34XX_GPIO29, | 843 | AH8_34XX_GPIO29, |
| 844 | U8_34XX_GPIO54_OUT, | ||
| 845 | U8_34XX_GPIO54_DOWN, | ||
| 846 | L8_34XX_GPIO63, | ||
| 847 | G25_34XX_GPIO86_OUT, | ||
| 848 | AG4_34XX_GPIO134_OUT, | ||
| 849 | AE4_34XX_GPIO136_OUT, | ||
| 850 | AF6_34XX_GPIO140_UP, | ||
| 851 | AE6_34XX_GPIO141, | ||
| 852 | AF5_34XX_GPIO142, | ||
| 853 | AE5_34XX_GPIO143, | ||
| 854 | H19_34XX_GPIO164_OUT, | ||
| 792 | J25_34XX_GPIO170, | 855 | J25_34XX_GPIO170, |
| 793 | }; | 856 | }; |
| 794 | 857 | ||
diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/mach/omap34xx.h index 8e0479fff05a..1b1c35d21697 100644 --- a/arch/arm/plat-omap/include/mach/omap34xx.h +++ b/arch/arm/plat-omap/include/mach/omap34xx.h | |||
| @@ -49,6 +49,33 @@ | |||
| 49 | #define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE | 49 | #define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE |
| 50 | 50 | ||
| 51 | #define OMAP34XX_IC_BASE 0x48200000 | 51 | #define OMAP34XX_IC_BASE 0x48200000 |
| 52 | |||
| 53 | #define OMAP3430_ISP_BASE (L4_34XX_BASE + 0xBC000) | ||
| 54 | #define OMAP3430_ISP_CBUFF_BASE (OMAP3430_ISP_BASE + 0x0100) | ||
| 55 | #define OMAP3430_ISP_CCP2_BASE (OMAP3430_ISP_BASE + 0x0400) | ||
| 56 | #define OMAP3430_ISP_CCDC_BASE (OMAP3430_ISP_BASE + 0x0600) | ||
| 57 | #define OMAP3430_ISP_HIST_BASE (OMAP3430_ISP_BASE + 0x0A00) | ||
| 58 | #define OMAP3430_ISP_H3A_BASE (OMAP3430_ISP_BASE + 0x0C00) | ||
| 59 | #define OMAP3430_ISP_PREV_BASE (OMAP3430_ISP_BASE + 0x0E00) | ||
| 60 | #define OMAP3430_ISP_RESZ_BASE (OMAP3430_ISP_BASE + 0x1000) | ||
| 61 | #define OMAP3430_ISP_SBL_BASE (OMAP3430_ISP_BASE + 0x1200) | ||
| 62 | #define OMAP3430_ISP_MMU_BASE (OMAP3430_ISP_BASE + 0x1400) | ||
| 63 | #define OMAP3430_ISP_CSI2A_BASE (OMAP3430_ISP_BASE + 0x1800) | ||
| 64 | #define OMAP3430_ISP_CSI2PHY_BASE (OMAP3430_ISP_BASE + 0x1970) | ||
| 65 | |||
| 66 | #define OMAP3430_ISP_END (OMAP3430_ISP_BASE + 0x06F) | ||
| 67 | #define OMAP3430_ISP_CBUFF_END (OMAP3430_ISP_CBUFF_BASE + 0x077) | ||
| 68 | #define OMAP3430_ISP_CCP2_END (OMAP3430_ISP_CCP2_BASE + 0x1EF) | ||
| 69 | #define OMAP3430_ISP_CCDC_END (OMAP3430_ISP_CCDC_BASE + 0x0A7) | ||
| 70 | #define OMAP3430_ISP_HIST_END (OMAP3430_ISP_HIST_BASE + 0x047) | ||
| 71 | #define OMAP3430_ISP_H3A_END (OMAP3430_ISP_H3A_BASE + 0x05F) | ||
| 72 | #define OMAP3430_ISP_PREV_END (OMAP3430_ISP_PREV_BASE + 0x09F) | ||
| 73 | #define OMAP3430_ISP_RESZ_END (OMAP3430_ISP_RESZ_BASE + 0x0AB) | ||
| 74 | #define OMAP3430_ISP_SBL_END (OMAP3430_ISP_SBL_BASE + 0x0FB) | ||
| 75 | #define OMAP3430_ISP_MMU_END (OMAP3430_ISP_MMU_BASE + 0x06F) | ||
| 76 | #define OMAP3430_ISP_CSI2A_END (OMAP3430_ISP_CSI2A_BASE + 0x16F) | ||
| 77 | #define OMAP3430_ISP_CSI2PHY_END (OMAP3430_ISP_CSI2PHY_BASE + 0x007) | ||
| 78 | |||
| 52 | #define OMAP34XX_IVA_INTC_BASE 0x40000000 | 79 | #define OMAP34XX_IVA_INTC_BASE 0x40000000 |
| 53 | #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) | 80 | #define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000) |
| 54 | #define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000) | 81 | #define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000) |
| @@ -61,6 +88,7 @@ | |||
| 61 | #define OMAP2_CM_BASE OMAP3430_CM_BASE | 88 | #define OMAP2_CM_BASE OMAP3430_CM_BASE |
| 62 | #define OMAP2_PRM_BASE OMAP3430_PRM_BASE | 89 | #define OMAP2_PRM_BASE OMAP3430_PRM_BASE |
| 63 | #define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE) | 90 | #define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE) |
| 91 | #define OMAP34XX_MAILBOX_BASE (L4_34XX_BASE + 0x94000) | ||
| 64 | 92 | ||
| 65 | #endif | 93 | #endif |
| 66 | 94 | ||
diff --git a/arch/arm/plat-omap/include/mach/omap850.h b/arch/arm/plat-omap/include/mach/omap850.h new file mode 100644 index 000000000000..c33f67981712 --- /dev/null +++ b/arch/arm/plat-omap/include/mach/omap850.h | |||
| @@ -0,0 +1,102 @@ | |||
| 1 | /* arch/arm/plat-omap/include/mach/omap850.h | ||
| 2 | * | ||
| 3 | * Hardware definitions for TI OMAP850 processor. | ||
| 4 | * | ||
| 5 | * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify it | ||
| 8 | * under the terms of the GNU General Public License as published by the | ||
| 9 | * Free Software Foundation; either version 2 of the License, or (at your | ||
| 10 | * option) any later version. | ||
| 11 | * | ||
| 12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | ||
| 13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | ||
| 14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | ||
| 15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | ||
| 16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | ||
| 17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | ||
| 18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | ||
| 19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | ||
| 20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | ||
| 21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
| 22 | * | ||
| 23 | * You should have received a copy of the GNU General Public License along | ||
| 24 | * with this program; if not, write to the Free Software Foundation, Inc., | ||
| 25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 26 | */ | ||
| 27 | |||
| 28 | #ifndef __ASM_ARCH_OMAP850_H | ||
| 29 | #define __ASM_ARCH_OMAP850_H | ||
| 30 | |||
| 31 | /* | ||
| 32 | * ---------------------------------------------------------------------------- | ||
| 33 | * Base addresses | ||
| 34 | * ---------------------------------------------------------------------------- | ||
| 35 | */ | ||
| 36 | |||
| 37 | /* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */ | ||
| 38 | |||
| 39 | #define OMAP850_DSP_BASE 0xE0000000 | ||
| 40 | #define OMAP850_DSP_SIZE 0x50000 | ||
| 41 | #define OMAP850_DSP_START 0xE0000000 | ||
| 42 | |||
| 43 | #define OMAP850_DSPREG_BASE 0xE1000000 | ||
| 44 | #define OMAP850_DSPREG_SIZE SZ_128K | ||
| 45 | #define OMAP850_DSPREG_START 0xE1000000 | ||
| 46 | |||
| 47 | /* | ||
| 48 | * ---------------------------------------------------------------------------- | ||
| 49 | * OMAP850 specific configuration registers | ||
| 50 | * ---------------------------------------------------------------------------- | ||
| 51 | */ | ||
| 52 | #define OMAP850_CONFIG_BASE 0xfffe1000 | ||
| 53 | #define OMAP850_IO_CONF_0 0xfffe1070 | ||
| 54 | #define OMAP850_IO_CONF_1 0xfffe1074 | ||
| 55 | #define OMAP850_IO_CONF_2 0xfffe1078 | ||
| 56 | #define OMAP850_IO_CONF_3 0xfffe107c | ||
| 57 | #define OMAP850_IO_CONF_4 0xfffe1080 | ||
| 58 | #define OMAP850_IO_CONF_5 0xfffe1084 | ||
| 59 | #define OMAP850_IO_CONF_6 0xfffe1088 | ||
| 60 | #define OMAP850_IO_CONF_7 0xfffe108c | ||
| 61 | #define OMAP850_IO_CONF_8 0xfffe1090 | ||
| 62 | #define OMAP850_IO_CONF_9 0xfffe1094 | ||
| 63 | #define OMAP850_IO_CONF_10 0xfffe1098 | ||
| 64 | #define OMAP850_IO_CONF_11 0xfffe109c | ||
| 65 | #define OMAP850_IO_CONF_12 0xfffe10a0 | ||
| 66 | #define OMAP850_IO_CONF_13 0xfffe10a4 | ||
| 67 | |||
| 68 | #define OMAP850_MODE_1 0xfffe1010 | ||
| 69 | #define OMAP850_MODE_2 0xfffe1014 | ||
| 70 | |||
| 71 | /* CSMI specials: in terms of base + offset */ | ||
| 72 | #define OMAP850_MODE2_OFFSET 0x14 | ||
| 73 | |||
| 74 | /* | ||
| 75 | * ---------------------------------------------------------------------------- | ||
| 76 | * OMAP850 traffic controller configuration registers | ||
| 77 | * ---------------------------------------------------------------------------- | ||
| 78 | */ | ||
| 79 | #define OMAP850_FLASH_CFG_0 0xfffecc10 | ||
| 80 | #define OMAP850_FLASH_ACFG_0 0xfffecc50 | ||
| 81 | #define OMAP850_FLASH_CFG_1 0xfffecc14 | ||
| 82 | #define OMAP850_FLASH_ACFG_1 0xfffecc54 | ||
| 83 | |||
| 84 | /* | ||
| 85 | * ---------------------------------------------------------------------------- | ||
| 86 | * OMAP850 DSP control registers | ||
| 87 | * ---------------------------------------------------------------------------- | ||
| 88 | */ | ||
| 89 | #define OMAP850_ICR_BASE 0xfffbb800 | ||
| 90 | #define OMAP850_DSP_M_CTL 0xfffbb804 | ||
| 91 | #define OMAP850_DSP_MMU_BASE 0xfffed200 | ||
| 92 | |||
| 93 | /* | ||
| 94 | * ---------------------------------------------------------------------------- | ||
| 95 | * OMAP850 PCC_UPLD configuration registers | ||
| 96 | * ---------------------------------------------------------------------------- | ||
| 97 | */ | ||
| 98 | #define OMAP850_PCC_UPLD_CTRL_BASE (0xfffe0900) | ||
| 99 | #define OMAP850_PCC_UPLD_CTRL (OMAP850_PCC_UPLD_CTRL_BASE + 0x00) | ||
| 100 | |||
| 101 | #endif /* __ASM_ARCH_OMAP850_H */ | ||
| 102 | |||
diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h index 2a9c27ad4c37..ce6ee7927537 100644 --- a/arch/arm/plat-omap/include/mach/pm.h +++ b/arch/arm/plat-omap/include/mach/pm.h | |||
| @@ -108,7 +108,7 @@ | |||
| 108 | !defined(CONFIG_ARCH_OMAP15XX) && \ | 108 | !defined(CONFIG_ARCH_OMAP15XX) && \ |
| 109 | !defined(CONFIG_ARCH_OMAP16XX) && \ | 109 | !defined(CONFIG_ARCH_OMAP16XX) && \ |
| 110 | !defined(CONFIG_ARCH_OMAP24XX) | 110 | !defined(CONFIG_ARCH_OMAP24XX) |
| 111 | #error "Power management for this processor not implemented yet" | 111 | #warning "Power management for this processor not implemented yet" |
| 112 | #endif | 112 | #endif |
| 113 | 113 | ||
| 114 | #ifndef __ASSEMBLER__ | 114 | #ifndef __ASSEMBLER__ |
| @@ -118,18 +118,6 @@ | |||
| 118 | extern void prevent_idle_sleep(void); | 118 | extern void prevent_idle_sleep(void); |
| 119 | extern void allow_idle_sleep(void); | 119 | extern void allow_idle_sleep(void); |
| 120 | 120 | ||
| 121 | /** | ||
| 122 | * clk_deny_idle - Prevents the clock from being idled during MPU idle | ||
| 123 | * @clk: clock signal handle | ||
| 124 | */ | ||
| 125 | void clk_deny_idle(struct clk *clk); | ||
| 126 | |||
| 127 | /** | ||
| 128 | * clk_allow_idle - Counters previous clk_deny_idle | ||
| 129 | * @clk: clock signal handle | ||
| 130 | */ | ||
| 131 | void clk_allow_idle(struct clk *clk); | ||
| 132 | |||
| 133 | extern void omap_pm_idle(void); | 121 | extern void omap_pm_idle(void); |
| 134 | extern void omap_pm_suspend(void); | 122 | extern void omap_pm_suspend(void); |
| 135 | extern void omap730_cpu_suspend(unsigned short, unsigned short); | 123 | extern void omap730_cpu_suspend(unsigned short, unsigned short); |
diff --git a/arch/arm/plat-omap/include/mach/powerdomain.h b/arch/arm/plat-omap/include/mach/powerdomain.h index 2806a9c8e4d7..69c9e675d8ee 100644 --- a/arch/arm/plat-omap/include/mach/powerdomain.h +++ b/arch/arm/plat-omap/include/mach/powerdomain.h | |||
| @@ -50,9 +50,9 @@ | |||
| 50 | 50 | ||
| 51 | /* | 51 | /* |
| 52 | * Maximum number of clockdomains that can be associated with a powerdomain. | 52 | * Maximum number of clockdomains that can be associated with a powerdomain. |
| 53 | * CORE powerdomain is probably the worst case. | 53 | * CORE powerdomain on OMAP3 is the worst case |
| 54 | */ | 54 | */ |
| 55 | #define PWRDM_MAX_CLKDMS 3 | 55 | #define PWRDM_MAX_CLKDMS 4 |
| 56 | 56 | ||
| 57 | /* XXX A completely arbitrary number. What is reasonable here? */ | 57 | /* XXX A completely arbitrary number. What is reasonable here? */ |
| 58 | #define PWRDM_TRANSITION_BAILOUT 100000 | 58 | #define PWRDM_TRANSITION_BAILOUT 100000 |
| @@ -145,6 +145,7 @@ int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); | |||
| 145 | 145 | ||
| 146 | int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); | 146 | int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); |
| 147 | int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); | 147 | int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); |
| 148 | int pwrdm_read_pwrst(struct powerdomain *pwrdm); | ||
| 148 | int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); | 149 | int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); |
| 149 | int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); | 150 | int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); |
| 150 | 151 | ||
diff --git a/arch/arm/plat-omap/include/mach/prcm.h b/arch/arm/plat-omap/include/mach/prcm.h index 56eba0fd6f6a..24ac3c715912 100644 --- a/arch/arm/plat-omap/include/mach/prcm.h +++ b/arch/arm/plat-omap/include/mach/prcm.h | |||
| @@ -20,10 +20,11 @@ | |||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | */ | 21 | */ |
| 22 | 22 | ||
| 23 | #ifndef __ASM_ARM_ARCH_DPM_PRCM_H | 23 | #ifndef __ASM_ARM_ARCH_OMAP_PRCM_H |
| 24 | #define __ASM_ARM_ARCH_DPM_PRCM_H | 24 | #define __ASM_ARM_ARCH_OMAP_PRCM_H |
| 25 | 25 | ||
| 26 | u32 omap_prcm_get_reset_sources(void); | 26 | u32 omap_prcm_get_reset_sources(void); |
| 27 | void omap_prcm_arch_reset(char mode); | ||
| 27 | 28 | ||
| 28 | #endif | 29 | #endif |
| 29 | 30 | ||
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h index a98c6c3beb2c..adc73522491f 100644 --- a/arch/arm/plat-omap/include/mach/sdrc.h +++ b/arch/arm/plat-omap/include/mach/sdrc.h | |||
| @@ -4,10 +4,12 @@ | |||
| 4 | /* | 4 | /* |
| 5 | * OMAP2/3 SDRC/SMS register definitions | 5 | * OMAP2/3 SDRC/SMS register definitions |
| 6 | * | 6 | * |
| 7 | * Copyright (C) 2007 Texas Instruments, Inc. | 7 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
| 8 | * Copyright (C) 2007 Nokia Corporation | 8 | * Copyright (C) 2007-2008 Nokia Corporation |
| 9 | * | 9 | * |
| 10 | * Written by Paul Walmsley | 10 | * Tony Lindgren |
| 11 | * Paul Walmsley | ||
| 12 | * Richard Woodruff | ||
| 11 | * | 13 | * |
| 12 | * This program is free software; you can redistribute it and/or modify | 14 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License version 2 as | 15 | * it under the terms of the GNU General Public License version 2 as |
| @@ -64,14 +66,62 @@ | |||
| 64 | * SMS register access | 66 | * SMS register access |
| 65 | */ | 67 | */ |
| 66 | 68 | ||
| 67 | 69 | #define OMAP242X_SMS_REGADDR(reg) \ | |
| 68 | #define OMAP242X_SMS_REGADDR(reg) IO_ADDRESS(OMAP2420_SMS_BASE + reg) | 70 | (void __iomem *)IO_ADDRESS(OMAP2420_SMS_BASE + reg) |
| 69 | #define OMAP243X_SMS_REGADDR(reg) IO_ADDRESS(OMAP243X_SMS_BASE + reg) | 71 | #define OMAP243X_SMS_REGADDR(reg) \ |
| 70 | #define OMAP343X_SMS_REGADDR(reg) IO_ADDRESS(OMAP343X_SMS_BASE + reg) | 72 | (void __iomem *)IO_ADDRESS(OMAP243X_SMS_BASE + reg) |
| 73 | #define OMAP343X_SMS_REGADDR(reg) \ | ||
| 74 | (void __iomem *)IO_ADDRESS(OMAP343X_SMS_BASE + reg) | ||
| 71 | 75 | ||
| 72 | /* SMS register offsets - read/write with sms_{read,write}_reg() */ | 76 | /* SMS register offsets - read/write with sms_{read,write}_reg() */ |
| 73 | 77 | ||
| 74 | #define SMS_SYSCONFIG 0x010 | 78 | #define SMS_SYSCONFIG 0x010 |
| 75 | /* REVISIT: fill in other SMS registers here */ | 79 | /* REVISIT: fill in other SMS registers here */ |
| 76 | 80 | ||
| 81 | |||
| 82 | #ifndef __ASSEMBLER__ | ||
| 83 | |||
| 84 | /** | ||
| 85 | * struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate | ||
| 86 | * @rate: SDRC clock rate (in Hz) | ||
| 87 | * @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate | ||
| 88 | * @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate | ||
| 89 | * @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate | ||
| 90 | * @mr: Value to program to SDRC_MR for this rate | ||
| 91 | * | ||
| 92 | * This structure holds a pre-computed set of register values for the | ||
| 93 | * SDRC for a given SDRC clock rate and SDRAM chip. These are | ||
| 94 | * intended to be pre-computed and specified in an array in the board-*.c | ||
| 95 | * files. The structure is keyed off the 'rate' field. | ||
| 96 | */ | ||
| 97 | struct omap_sdrc_params { | ||
| 98 | unsigned long rate; | ||
| 99 | u32 actim_ctrla; | ||
| 100 | u32 actim_ctrlb; | ||
| 101 | u32 rfr_ctrl; | ||
| 102 | u32 mr; | ||
| 103 | }; | ||
| 104 | |||
| 105 | void __init omap2_sdrc_init(struct omap_sdrc_params *sp); | ||
| 106 | struct omap_sdrc_params *omap2_sdrc_get_params(unsigned long r); | ||
| 107 | |||
| 108 | #ifdef CONFIG_ARCH_OMAP2 | ||
| 109 | |||
| 110 | struct memory_timings { | ||
| 111 | u32 m_type; /* ddr = 1, sdr = 0 */ | ||
| 112 | u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */ | ||
| 113 | u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */ | ||
| 114 | u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */ | ||
| 115 | u32 base_cs; /* base chip select to use for calculations */ | ||
| 116 | }; | ||
| 117 | |||
| 118 | extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode); | ||
| 119 | |||
| 120 | u32 omap2xxx_sdrc_dll_is_unlocked(void); | ||
| 121 | u32 omap2xxx_sdrc_reprogram(u32 level, u32 force); | ||
| 122 | |||
| 123 | #endif /* CONFIG_ARCH_OMAP2 */ | ||
| 124 | |||
| 125 | #endif /* __ASSEMBLER__ */ | ||
| 126 | |||
| 77 | #endif | 127 | #endif |
diff --git a/arch/arm/plat-omap/include/mach/system.h b/arch/arm/plat-omap/include/mach/system.h index 06923f261545..1060e345423b 100644 --- a/arch/arm/plat-omap/include/mach/system.h +++ b/arch/arm/plat-omap/include/mach/system.h | |||
| @@ -9,12 +9,14 @@ | |||
| 9 | #include <asm/mach-types.h> | 9 | #include <asm/mach-types.h> |
| 10 | #include <mach/hardware.h> | 10 | #include <mach/hardware.h> |
| 11 | 11 | ||
| 12 | #include <mach/prcm.h> | ||
| 13 | |||
| 12 | #ifndef CONFIG_MACH_VOICEBLUE | 14 | #ifndef CONFIG_MACH_VOICEBLUE |
| 13 | #define voiceblue_reset() do {} while (0) | 15 | #define voiceblue_reset() do {} while (0) |
| 16 | #else | ||
| 17 | extern void voiceblue_reset(void); | ||
| 14 | #endif | 18 | #endif |
| 15 | 19 | ||
| 16 | extern void omap_prcm_arch_reset(char mode); | ||
| 17 | |||
| 18 | static inline void arch_idle(void) | 20 | static inline void arch_idle(void) |
| 19 | { | 21 | { |
| 20 | cpu_do_idle(); | 22 | cpu_do_idle(); |
| @@ -38,7 +40,7 @@ static inline void omap1_arch_reset(char mode) | |||
| 38 | omap_writew(1, ARM_RSTCT1); | 40 | omap_writew(1, ARM_RSTCT1); |
| 39 | } | 41 | } |
| 40 | 42 | ||
| 41 | static inline void arch_reset(char mode) | 43 | static inline void arch_reset(char mode, const char *cmd) |
| 42 | { | 44 | { |
| 43 | if (!cpu_class_is_omap2()) | 45 | if (!cpu_class_is_omap2()) |
| 44 | omap1_arch_reset(mode); | 46 | omap1_arch_reset(mode); |
diff --git a/arch/arm/plat-omap/include/mach/usb.h b/arch/arm/plat-omap/include/mach/usb.h index a56a610950c2..69f0ceed500b 100644 --- a/arch/arm/plat-omap/include/mach/usb.h +++ b/arch/arm/plat-omap/include/mach/usb.h | |||
| @@ -27,8 +27,18 @@ | |||
| 27 | #define UDC_BASE OMAP2_UDC_BASE | 27 | #define UDC_BASE OMAP2_UDC_BASE |
| 28 | #define OMAP_OHCI_BASE OMAP2_OHCI_BASE | 28 | #define OMAP_OHCI_BASE OMAP2_OHCI_BASE |
| 29 | 29 | ||
| 30 | #ifdef CONFIG_USB_MUSB_SOC | ||
| 31 | extern void usb_musb_init(void); | ||
| 32 | #else | ||
| 33 | static inline void usb_musb_init(void) | ||
| 34 | { | ||
| 35 | } | ||
| 36 | #endif | ||
| 37 | |||
| 30 | #endif | 38 | #endif |
| 31 | 39 | ||
| 40 | void omap_usb_init(struct omap_usb_config *pdata); | ||
| 41 | |||
| 32 | /*-------------------------------------------------------------------------*/ | 42 | /*-------------------------------------------------------------------------*/ |
| 33 | 43 | ||
| 34 | /* | 44 | /* |
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c index b52ce053e6f2..0abfbaa59871 100644 --- a/arch/arm/plat-omap/mailbox.c +++ b/arch/arm/plat-omap/mailbox.c | |||
| @@ -1,10 +1,9 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * OMAP mailbox driver | 2 | * OMAP mailbox driver |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2006 Nokia Corporation. All rights reserved. | 4 | * Copyright (C) 2006-2009 Nokia Corporation. All rights reserved. |
| 5 | * | 5 | * |
| 6 | * Contact: Toshihiro Kobayashi <toshihiro.kobayashi@nokia.com> | 6 | * Contact: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> |
| 7 | * Restructured by Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
| 8 | * | 7 | * |
| 9 | * This program is free software; you can redistribute it and/or | 8 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License | 9 | * modify it under the terms of the GNU General Public License |
| @@ -22,21 +21,98 @@ | |||
| 22 | * | 21 | * |
| 23 | */ | 22 | */ |
| 24 | 23 | ||
| 25 | #include <linux/init.h> | ||
| 26 | #include <linux/module.h> | 24 | #include <linux/module.h> |
| 27 | #include <linux/sched.h> | ||
| 28 | #include <linux/interrupt.h> | 25 | #include <linux/interrupt.h> |
| 29 | #include <linux/device.h> | 26 | #include <linux/device.h> |
| 30 | #include <linux/blkdev.h> | ||
| 31 | #include <linux/err.h> | ||
| 32 | #include <linux/delay.h> | 27 | #include <linux/delay.h> |
| 33 | #include <linux/io.h> | 28 | |
| 34 | #include <mach/mailbox.h> | 29 | #include <mach/mailbox.h> |
| 35 | #include "mailbox.h" | 30 | |
| 31 | static int enable_seq_bit; | ||
| 32 | module_param(enable_seq_bit, bool, 0); | ||
| 33 | MODULE_PARM_DESC(enable_seq_bit, "Enable sequence bit checking."); | ||
| 36 | 34 | ||
| 37 | static struct omap_mbox *mboxes; | 35 | static struct omap_mbox *mboxes; |
| 38 | static DEFINE_RWLOCK(mboxes_lock); | 36 | static DEFINE_RWLOCK(mboxes_lock); |
| 39 | 37 | ||
| 38 | /* | ||
| 39 | * Mailbox sequence bit API | ||
| 40 | */ | ||
| 41 | |||
| 42 | /* seq_rcv should be initialized with any value other than | ||
| 43 | * 0 and 1 << 31, to allow either value for the first | ||
| 44 | * message. */ | ||
| 45 | static inline void mbox_seq_init(struct omap_mbox *mbox) | ||
| 46 | { | ||
| 47 | if (!enable_seq_bit) | ||
| 48 | return; | ||
| 49 | |||
| 50 | /* any value other than 0 and 1 << 31 */ | ||
| 51 | mbox->seq_rcv = 0xffffffff; | ||
| 52 | } | ||
| 53 | |||
| 54 | static inline void mbox_seq_toggle(struct omap_mbox *mbox, mbox_msg_t * msg) | ||
| 55 | { | ||
| 56 | if (!enable_seq_bit) | ||
| 57 | return; | ||
| 58 | |||
| 59 | /* add seq_snd to msg */ | ||
| 60 | *msg = (*msg & 0x7fffffff) | mbox->seq_snd; | ||
| 61 | /* flip seq_snd */ | ||
| 62 | mbox->seq_snd ^= 1 << 31; | ||
| 63 | } | ||
| 64 | |||
| 65 | static inline int mbox_seq_test(struct omap_mbox *mbox, mbox_msg_t msg) | ||
| 66 | { | ||
| 67 | mbox_msg_t seq; | ||
| 68 | |||
| 69 | if (!enable_seq_bit) | ||
| 70 | return 0; | ||
| 71 | |||
| 72 | seq = msg & (1 << 31); | ||
| 73 | if (seq == mbox->seq_rcv) | ||
| 74 | return -1; | ||
| 75 | mbox->seq_rcv = seq; | ||
| 76 | return 0; | ||
| 77 | } | ||
| 78 | |||
| 79 | /* Mailbox FIFO handle functions */ | ||
| 80 | static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox) | ||
| 81 | { | ||
| 82 | return mbox->ops->fifo_read(mbox); | ||
| 83 | } | ||
| 84 | static inline void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) | ||
| 85 | { | ||
| 86 | mbox->ops->fifo_write(mbox, msg); | ||
| 87 | } | ||
| 88 | static inline int mbox_fifo_empty(struct omap_mbox *mbox) | ||
| 89 | { | ||
| 90 | return mbox->ops->fifo_empty(mbox); | ||
| 91 | } | ||
| 92 | static inline int mbox_fifo_full(struct omap_mbox *mbox) | ||
| 93 | { | ||
| 94 | return mbox->ops->fifo_full(mbox); | ||
| 95 | } | ||
| 96 | |||
| 97 | /* Mailbox IRQ handle functions */ | ||
| 98 | static inline void enable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | ||
| 99 | { | ||
| 100 | mbox->ops->enable_irq(mbox, irq); | ||
| 101 | } | ||
| 102 | static inline void disable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | ||
| 103 | { | ||
| 104 | mbox->ops->disable_irq(mbox, irq); | ||
| 105 | } | ||
| 106 | static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | ||
| 107 | { | ||
| 108 | if (mbox->ops->ack_irq) | ||
| 109 | mbox->ops->ack_irq(mbox, irq); | ||
| 110 | } | ||
| 111 | static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | ||
| 112 | { | ||
| 113 | return mbox->ops->is_irq(mbox, irq); | ||
| 114 | } | ||
| 115 | |||
| 40 | /* Mailbox Sequence Bit function */ | 116 | /* Mailbox Sequence Bit function */ |
| 41 | void omap_mbox_init_seq(struct omap_mbox *mbox) | 117 | void omap_mbox_init_seq(struct omap_mbox *mbox) |
| 42 | { | 118 | { |
| @@ -136,7 +212,7 @@ static void mbox_rx_work(struct work_struct *work) | |||
| 136 | unsigned long flags; | 212 | unsigned long flags; |
| 137 | 213 | ||
| 138 | if (mbox->rxq->callback == NULL) { | 214 | if (mbox->rxq->callback == NULL) { |
| 139 | sysfs_notify(&mbox->dev.kobj, NULL, "mbox"); | 215 | sysfs_notify(&mbox->dev->kobj, NULL, "mbox"); |
| 140 | return; | 216 | return; |
| 141 | } | 217 | } |
| 142 | 218 | ||
| @@ -204,7 +280,7 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox) | |||
| 204 | /* no more messages in the fifo. clear IRQ source. */ | 280 | /* no more messages in the fifo. clear IRQ source. */ |
| 205 | ack_mbox_irq(mbox, IRQ_RX); | 281 | ack_mbox_irq(mbox, IRQ_RX); |
| 206 | enable_mbox_irq(mbox, IRQ_RX); | 282 | enable_mbox_irq(mbox, IRQ_RX); |
| 207 | nomem: | 283 | nomem: |
| 208 | schedule_work(&mbox->rxq->work); | 284 | schedule_work(&mbox->rxq->work); |
| 209 | } | 285 | } |
| 210 | 286 | ||
| @@ -286,7 +362,7 @@ static ssize_t mbox_show(struct class *class, char *buf) | |||
| 286 | static CLASS_ATTR(mbox, S_IRUGO, mbox_show, NULL); | 362 | static CLASS_ATTR(mbox, S_IRUGO, mbox_show, NULL); |
| 287 | 363 | ||
| 288 | static struct class omap_mbox_class = { | 364 | static struct class omap_mbox_class = { |
| 289 | .name = "omap_mbox", | 365 | .name = "omap-mailbox", |
| 290 | }; | 366 | }; |
| 291 | 367 | ||
| 292 | static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, | 368 | static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox, |
| @@ -333,21 +409,6 @@ static int omap_mbox_init(struct omap_mbox *mbox) | |||
| 333 | return ret; | 409 | return ret; |
| 334 | } | 410 | } |
| 335 | 411 | ||
| 336 | mbox->dev.class = &omap_mbox_class; | ||
| 337 | dev_set_name(&mbox->dev, "%s", mbox->name); | ||
| 338 | dev_set_drvdata(&mbox->dev, mbox); | ||
| 339 | |||
| 340 | ret = device_register(&mbox->dev); | ||
| 341 | if (unlikely(ret)) | ||
| 342 | goto fail_device_reg; | ||
| 343 | |||
| 344 | ret = device_create_file(&mbox->dev, &dev_attr_mbox); | ||
| 345 | if (unlikely(ret)) { | ||
| 346 | printk(KERN_ERR | ||
| 347 | "device_create_file failed: %d\n", ret); | ||
| 348 | goto fail_create_mbox; | ||
| 349 | } | ||
| 350 | |||
| 351 | ret = request_irq(mbox->irq, mbox_interrupt, IRQF_DISABLED, | 412 | ret = request_irq(mbox->irq, mbox_interrupt, IRQF_DISABLED, |
| 352 | mbox->name, mbox); | 413 | mbox->name, mbox); |
| 353 | if (unlikely(ret)) { | 414 | if (unlikely(ret)) { |
| @@ -377,10 +438,6 @@ static int omap_mbox_init(struct omap_mbox *mbox) | |||
| 377 | fail_alloc_txq: | 438 | fail_alloc_txq: |
| 378 | free_irq(mbox->irq, mbox); | 439 | free_irq(mbox->irq, mbox); |
| 379 | fail_request_irq: | 440 | fail_request_irq: |
| 380 | device_remove_file(&mbox->dev, &dev_attr_mbox); | ||
| 381 | fail_create_mbox: | ||
| 382 | device_unregister(&mbox->dev); | ||
| 383 | fail_device_reg: | ||
| 384 | if (unlikely(mbox->ops->shutdown)) | 441 | if (unlikely(mbox->ops->shutdown)) |
| 385 | mbox->ops->shutdown(mbox); | 442 | mbox->ops->shutdown(mbox); |
| 386 | 443 | ||
| @@ -393,8 +450,6 @@ static void omap_mbox_fini(struct omap_mbox *mbox) | |||
| 393 | mbox_queue_free(mbox->rxq); | 450 | mbox_queue_free(mbox->rxq); |
| 394 | 451 | ||
| 395 | free_irq(mbox->irq, mbox); | 452 | free_irq(mbox->irq, mbox); |
| 396 | device_remove_file(&mbox->dev, &dev_attr_mbox); | ||
| 397 | class_unregister(&omap_mbox_class); | ||
| 398 | 453 | ||
| 399 | if (unlikely(mbox->ops->shutdown)) | 454 | if (unlikely(mbox->ops->shutdown)) |
| 400 | mbox->ops->shutdown(mbox); | 455 | mbox->ops->shutdown(mbox); |
| @@ -440,7 +495,7 @@ void omap_mbox_put(struct omap_mbox *mbox) | |||
| 440 | } | 495 | } |
| 441 | EXPORT_SYMBOL(omap_mbox_put); | 496 | EXPORT_SYMBOL(omap_mbox_put); |
| 442 | 497 | ||
| 443 | int omap_mbox_register(struct omap_mbox *mbox) | 498 | int omap_mbox_register(struct device *parent, struct omap_mbox *mbox) |
| 444 | { | 499 | { |
| 445 | int ret = 0; | 500 | int ret = 0; |
| 446 | struct omap_mbox **tmp; | 501 | struct omap_mbox **tmp; |
| @@ -450,14 +505,31 @@ int omap_mbox_register(struct omap_mbox *mbox) | |||
| 450 | if (mbox->next) | 505 | if (mbox->next) |
| 451 | return -EBUSY; | 506 | return -EBUSY; |
| 452 | 507 | ||
| 508 | mbox->dev = device_create(&omap_mbox_class, | ||
| 509 | parent, 0, mbox, "%s", mbox->name); | ||
| 510 | if (IS_ERR(mbox->dev)) | ||
| 511 | return PTR_ERR(mbox->dev); | ||
| 512 | |||
| 513 | ret = device_create_file(mbox->dev, &dev_attr_mbox); | ||
| 514 | if (ret) | ||
| 515 | goto err_sysfs; | ||
| 516 | |||
| 453 | write_lock(&mboxes_lock); | 517 | write_lock(&mboxes_lock); |
| 454 | tmp = find_mboxes(mbox->name); | 518 | tmp = find_mboxes(mbox->name); |
| 455 | if (*tmp) | 519 | if (*tmp) { |
| 456 | ret = -EBUSY; | 520 | ret = -EBUSY; |
| 457 | else | 521 | write_unlock(&mboxes_lock); |
| 458 | *tmp = mbox; | 522 | goto err_find; |
| 523 | } | ||
| 524 | *tmp = mbox; | ||
| 459 | write_unlock(&mboxes_lock); | 525 | write_unlock(&mboxes_lock); |
| 460 | 526 | ||
| 527 | return 0; | ||
| 528 | |||
| 529 | err_find: | ||
| 530 | device_remove_file(mbox->dev, &dev_attr_mbox); | ||
| 531 | err_sysfs: | ||
| 532 | device_unregister(mbox->dev); | ||
| 461 | return ret; | 533 | return ret; |
| 462 | } | 534 | } |
| 463 | EXPORT_SYMBOL(omap_mbox_register); | 535 | EXPORT_SYMBOL(omap_mbox_register); |
| @@ -473,6 +545,8 @@ int omap_mbox_unregister(struct omap_mbox *mbox) | |||
| 473 | *tmp = mbox->next; | 545 | *tmp = mbox->next; |
| 474 | mbox->next = NULL; | 546 | mbox->next = NULL; |
| 475 | write_unlock(&mboxes_lock); | 547 | write_unlock(&mboxes_lock); |
| 548 | device_remove_file(mbox->dev, &dev_attr_mbox); | ||
| 549 | device_unregister(mbox->dev); | ||
| 476 | return 0; | 550 | return 0; |
| 477 | } | 551 | } |
| 478 | tmp = &(*tmp)->next; | 552 | tmp = &(*tmp)->next; |
| @@ -501,4 +575,6 @@ static void __exit omap_mbox_class_exit(void) | |||
| 501 | subsys_initcall(omap_mbox_class_init); | 575 | subsys_initcall(omap_mbox_class_init); |
| 502 | module_exit(omap_mbox_class_exit); | 576 | module_exit(omap_mbox_class_exit); |
| 503 | 577 | ||
| 504 | MODULE_LICENSE("GPL"); | 578 | MODULE_LICENSE("GPL v2"); |
| 579 | MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging"); | ||
| 580 | MODULE_AUTHOR("Toshihiro Kobayashi and Hiroshi DOYU"); | ||
diff --git a/arch/arm/plat-omap/mailbox.h b/arch/arm/plat-omap/mailbox.h deleted file mode 100644 index 67c6740b8ad5..000000000000 --- a/arch/arm/plat-omap/mailbox.h +++ /dev/null | |||
| @@ -1,100 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Mailbox internal functions | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Nokia Corporation | ||
| 5 | * Written by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com> | ||
| 6 | * | ||
| 7 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 8 | * License. See the file "COPYING" in the main directory of this archive | ||
| 9 | * for more details. | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef __ARCH_ARM_PLAT_MAILBOX_H | ||
| 13 | #define __ARCH_ARM_PLAT_MAILBOX_H | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Mailbox sequence bit API | ||
| 17 | */ | ||
| 18 | #if defined(CONFIG_ARCH_OMAP1) | ||
| 19 | # define MBOX_USE_SEQ_BIT | ||
| 20 | #elif defined(CONFIG_ARCH_OMAP2) | ||
| 21 | # define MBOX_USE_SEQ_BIT | ||
| 22 | #endif | ||
| 23 | |||
| 24 | #ifdef MBOX_USE_SEQ_BIT | ||
| 25 | /* seq_rcv should be initialized with any value other than | ||
| 26 | * 0 and 1 << 31, to allow either value for the first | ||
| 27 | * message. */ | ||
| 28 | static inline void mbox_seq_init(struct omap_mbox *mbox) | ||
| 29 | { | ||
| 30 | /* any value other than 0 and 1 << 31 */ | ||
| 31 | mbox->seq_rcv = 0xffffffff; | ||
| 32 | } | ||
| 33 | |||
| 34 | static inline void mbox_seq_toggle(struct omap_mbox *mbox, mbox_msg_t * msg) | ||
| 35 | { | ||
| 36 | /* add seq_snd to msg */ | ||
| 37 | *msg = (*msg & 0x7fffffff) | mbox->seq_snd; | ||
| 38 | /* flip seq_snd */ | ||
| 39 | mbox->seq_snd ^= 1 << 31; | ||
| 40 | } | ||
| 41 | |||
| 42 | static inline int mbox_seq_test(struct omap_mbox *mbox, mbox_msg_t msg) | ||
| 43 | { | ||
| 44 | mbox_msg_t seq = msg & (1 << 31); | ||
| 45 | if (seq == mbox->seq_rcv) | ||
| 46 | return -1; | ||
| 47 | mbox->seq_rcv = seq; | ||
| 48 | return 0; | ||
| 49 | } | ||
| 50 | #else | ||
| 51 | static inline void mbox_seq_init(struct omap_mbox *mbox) | ||
| 52 | { | ||
| 53 | } | ||
| 54 | static inline void mbox_seq_toggle(struct omap_mbox *mbox, mbox_msg_t * msg) | ||
| 55 | { | ||
| 56 | } | ||
| 57 | static inline int mbox_seq_test(struct omap_mbox *mbox, mbox_msg_t msg) | ||
| 58 | { | ||
| 59 | return 0; | ||
| 60 | } | ||
| 61 | #endif | ||
| 62 | |||
| 63 | /* Mailbox FIFO handle functions */ | ||
| 64 | static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox) | ||
| 65 | { | ||
| 66 | return mbox->ops->fifo_read(mbox); | ||
| 67 | } | ||
| 68 | static inline void mbox_fifo_write(struct omap_mbox *mbox, mbox_msg_t msg) | ||
| 69 | { | ||
| 70 | mbox->ops->fifo_write(mbox, msg); | ||
| 71 | } | ||
| 72 | static inline int mbox_fifo_empty(struct omap_mbox *mbox) | ||
| 73 | { | ||
| 74 | return mbox->ops->fifo_empty(mbox); | ||
| 75 | } | ||
| 76 | static inline int mbox_fifo_full(struct omap_mbox *mbox) | ||
| 77 | { | ||
| 78 | return mbox->ops->fifo_full(mbox); | ||
| 79 | } | ||
| 80 | |||
| 81 | /* Mailbox IRQ handle functions */ | ||
| 82 | static inline void enable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | ||
| 83 | { | ||
| 84 | mbox->ops->enable_irq(mbox, irq); | ||
| 85 | } | ||
| 86 | static inline void disable_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | ||
| 87 | { | ||
| 88 | mbox->ops->disable_irq(mbox, irq); | ||
| 89 | } | ||
| 90 | static inline void ack_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | ||
| 91 | { | ||
| 92 | if (mbox->ops->ack_irq) | ||
| 93 | mbox->ops->ack_irq(mbox, irq); | ||
| 94 | } | ||
| 95 | static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq) | ||
| 96 | { | ||
| 97 | return mbox->ops->is_irq(mbox, irq); | ||
| 98 | } | ||
| 99 | |||
| 100 | #endif /* __ARCH_ARM_PLAT_MAILBOX_H */ | ||
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index e5842e30e534..28b0a824b8cf 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c | |||
| @@ -214,7 +214,6 @@ EXPORT_SYMBOL(omap_mcbsp_set_io_type); | |||
| 214 | int omap_mcbsp_request(unsigned int id) | 214 | int omap_mcbsp_request(unsigned int id) |
| 215 | { | 215 | { |
| 216 | struct omap_mcbsp *mcbsp; | 216 | struct omap_mcbsp *mcbsp; |
| 217 | int i; | ||
| 218 | int err; | 217 | int err; |
| 219 | 218 | ||
| 220 | if (!omap_mcbsp_check_valid_id(id)) { | 219 | if (!omap_mcbsp_check_valid_id(id)) { |
| @@ -223,23 +222,23 @@ int omap_mcbsp_request(unsigned int id) | |||
| 223 | } | 222 | } |
| 224 | mcbsp = id_to_mcbsp_ptr(id); | 223 | mcbsp = id_to_mcbsp_ptr(id); |
| 225 | 224 | ||
| 226 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request) | ||
| 227 | mcbsp->pdata->ops->request(id); | ||
| 228 | |||
| 229 | for (i = 0; i < mcbsp->num_clks; i++) | ||
| 230 | clk_enable(mcbsp->clks[i]); | ||
| 231 | |||
| 232 | spin_lock(&mcbsp->lock); | 225 | spin_lock(&mcbsp->lock); |
| 233 | if (!mcbsp->free) { | 226 | if (!mcbsp->free) { |
| 234 | dev_err(mcbsp->dev, "McBSP%d is currently in use\n", | 227 | dev_err(mcbsp->dev, "McBSP%d is currently in use\n", |
| 235 | mcbsp->id); | 228 | mcbsp->id); |
| 236 | spin_unlock(&mcbsp->lock); | 229 | spin_unlock(&mcbsp->lock); |
| 237 | return -1; | 230 | return -EBUSY; |
| 238 | } | 231 | } |
| 239 | 232 | ||
| 240 | mcbsp->free = 0; | 233 | mcbsp->free = 0; |
| 241 | spin_unlock(&mcbsp->lock); | 234 | spin_unlock(&mcbsp->lock); |
| 242 | 235 | ||
| 236 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request) | ||
| 237 | mcbsp->pdata->ops->request(id); | ||
| 238 | |||
| 239 | clk_enable(mcbsp->iclk); | ||
| 240 | clk_enable(mcbsp->fclk); | ||
| 241 | |||
| 243 | /* | 242 | /* |
| 244 | * Make sure that transmitter, receiver and sample-rate generator are | 243 | * Make sure that transmitter, receiver and sample-rate generator are |
| 245 | * not running before activating IRQs. | 244 | * not running before activating IRQs. |
| @@ -278,7 +277,6 @@ EXPORT_SYMBOL(omap_mcbsp_request); | |||
| 278 | void omap_mcbsp_free(unsigned int id) | 277 | void omap_mcbsp_free(unsigned int id) |
| 279 | { | 278 | { |
| 280 | struct omap_mcbsp *mcbsp; | 279 | struct omap_mcbsp *mcbsp; |
| 281 | int i; | ||
| 282 | 280 | ||
| 283 | if (!omap_mcbsp_check_valid_id(id)) { | 281 | if (!omap_mcbsp_check_valid_id(id)) { |
| 284 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); | 282 | printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1); |
| @@ -289,8 +287,14 @@ void omap_mcbsp_free(unsigned int id) | |||
| 289 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) | 287 | if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free) |
| 290 | mcbsp->pdata->ops->free(id); | 288 | mcbsp->pdata->ops->free(id); |
| 291 | 289 | ||
| 292 | for (i = mcbsp->num_clks - 1; i >= 0; i--) | 290 | clk_disable(mcbsp->fclk); |
| 293 | clk_disable(mcbsp->clks[i]); | 291 | clk_disable(mcbsp->iclk); |
| 292 | |||
| 293 | if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { | ||
| 294 | /* Free IRQs */ | ||
| 295 | free_irq(mcbsp->rx_irq, (void *)mcbsp); | ||
| 296 | free_irq(mcbsp->tx_irq, (void *)mcbsp); | ||
| 297 | } | ||
| 294 | 298 | ||
| 295 | spin_lock(&mcbsp->lock); | 299 | spin_lock(&mcbsp->lock); |
| 296 | if (mcbsp->free) { | 300 | if (mcbsp->free) { |
| @@ -302,12 +306,6 @@ void omap_mcbsp_free(unsigned int id) | |||
| 302 | 306 | ||
| 303 | mcbsp->free = 1; | 307 | mcbsp->free = 1; |
| 304 | spin_unlock(&mcbsp->lock); | 308 | spin_unlock(&mcbsp->lock); |
| 305 | |||
| 306 | if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) { | ||
| 307 | /* Free IRQs */ | ||
| 308 | free_irq(mcbsp->rx_irq, (void *)mcbsp); | ||
| 309 | free_irq(mcbsp->tx_irq, (void *)mcbsp); | ||
| 310 | } | ||
| 311 | } | 309 | } |
| 312 | EXPORT_SYMBOL(omap_mcbsp_free); | 310 | EXPORT_SYMBOL(omap_mcbsp_free); |
| 313 | 311 | ||
| @@ -876,7 +874,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) | |||
| 876 | struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data; | 874 | struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data; |
| 877 | struct omap_mcbsp *mcbsp; | 875 | struct omap_mcbsp *mcbsp; |
| 878 | int id = pdev->id - 1; | 876 | int id = pdev->id - 1; |
| 879 | int i; | ||
| 880 | int ret = 0; | 877 | int ret = 0; |
| 881 | 878 | ||
| 882 | if (!pdata) { | 879 | if (!pdata) { |
| @@ -899,7 +896,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) | |||
| 899 | ret = -ENOMEM; | 896 | ret = -ENOMEM; |
| 900 | goto exit; | 897 | goto exit; |
| 901 | } | 898 | } |
| 902 | mcbsp_ptr[id] = mcbsp; | ||
| 903 | 899 | ||
| 904 | spin_lock_init(&mcbsp->lock); | 900 | spin_lock_init(&mcbsp->lock); |
| 905 | mcbsp->id = id + 1; | 901 | mcbsp->id = id + 1; |
| @@ -921,39 +917,32 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) | |||
| 921 | mcbsp->dma_rx_sync = pdata->dma_rx_sync; | 917 | mcbsp->dma_rx_sync = pdata->dma_rx_sync; |
| 922 | mcbsp->dma_tx_sync = pdata->dma_tx_sync; | 918 | mcbsp->dma_tx_sync = pdata->dma_tx_sync; |
| 923 | 919 | ||
| 924 | if (pdata->num_clks) { | 920 | mcbsp->iclk = clk_get(&pdev->dev, "ick"); |
| 925 | mcbsp->num_clks = pdata->num_clks; | 921 | if (IS_ERR(mcbsp->iclk)) { |
| 926 | mcbsp->clks = kzalloc(mcbsp->num_clks * sizeof(struct clk *), | 922 | ret = PTR_ERR(mcbsp->iclk); |
| 927 | GFP_KERNEL); | 923 | dev_err(&pdev->dev, "unable to get ick: %d\n", ret); |
| 928 | if (!mcbsp->clks) { | 924 | goto err_iclk; |
| 929 | ret = -ENOMEM; | 925 | } |
| 930 | goto exit; | ||
| 931 | } | ||
| 932 | for (i = 0; i < mcbsp->num_clks; i++) { | ||
| 933 | mcbsp->clks[i] = clk_get(&pdev->dev, pdata->clk_names[i]); | ||
| 934 | if (IS_ERR(mcbsp->clks[i])) { | ||
| 935 | dev_err(&pdev->dev, | ||
| 936 | "Invalid %s configuration for McBSP%d.\n", | ||
| 937 | pdata->clk_names[i], mcbsp->id); | ||
| 938 | ret = PTR_ERR(mcbsp->clks[i]); | ||
| 939 | goto err_clk; | ||
| 940 | } | ||
| 941 | } | ||
| 942 | 926 | ||
| 927 | mcbsp->fclk = clk_get(&pdev->dev, "fck"); | ||
| 928 | if (IS_ERR(mcbsp->fclk)) { | ||
| 929 | ret = PTR_ERR(mcbsp->fclk); | ||
| 930 | dev_err(&pdev->dev, "unable to get fck: %d\n", ret); | ||
| 931 | goto err_fclk; | ||
| 943 | } | 932 | } |
| 944 | 933 | ||
| 945 | mcbsp->pdata = pdata; | 934 | mcbsp->pdata = pdata; |
| 946 | mcbsp->dev = &pdev->dev; | 935 | mcbsp->dev = &pdev->dev; |
| 936 | mcbsp_ptr[id] = mcbsp; | ||
| 947 | platform_set_drvdata(pdev, mcbsp); | 937 | platform_set_drvdata(pdev, mcbsp); |
| 948 | return 0; | 938 | return 0; |
| 949 | 939 | ||
| 950 | err_clk: | 940 | err_fclk: |
| 951 | while (i--) | 941 | clk_put(mcbsp->iclk); |
| 952 | clk_put(mcbsp->clks[i]); | 942 | err_iclk: |
| 953 | kfree(mcbsp->clks); | ||
| 954 | iounmap(mcbsp->io_base); | 943 | iounmap(mcbsp->io_base); |
| 955 | err_ioremap: | 944 | err_ioremap: |
| 956 | mcbsp->free = 0; | 945 | kfree(mcbsp); |
| 957 | exit: | 946 | exit: |
| 958 | return ret; | 947 | return ret; |
| 959 | } | 948 | } |
| @@ -961,7 +950,6 @@ exit: | |||
| 961 | static int __devexit omap_mcbsp_remove(struct platform_device *pdev) | 950 | static int __devexit omap_mcbsp_remove(struct platform_device *pdev) |
| 962 | { | 951 | { |
| 963 | struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); | 952 | struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev); |
| 964 | int i; | ||
| 965 | 953 | ||
| 966 | platform_set_drvdata(pdev, NULL); | 954 | platform_set_drvdata(pdev, NULL); |
| 967 | if (mcbsp) { | 955 | if (mcbsp) { |
| @@ -970,18 +958,15 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev) | |||
| 970 | mcbsp->pdata->ops->free) | 958 | mcbsp->pdata->ops->free) |
| 971 | mcbsp->pdata->ops->free(mcbsp->id); | 959 | mcbsp->pdata->ops->free(mcbsp->id); |
| 972 | 960 | ||
| 973 | for (i = mcbsp->num_clks - 1; i >= 0; i--) { | 961 | clk_disable(mcbsp->fclk); |
| 974 | clk_disable(mcbsp->clks[i]); | 962 | clk_disable(mcbsp->iclk); |
| 975 | clk_put(mcbsp->clks[i]); | 963 | clk_put(mcbsp->fclk); |
| 976 | } | 964 | clk_put(mcbsp->iclk); |
| 977 | 965 | ||
| 978 | iounmap(mcbsp->io_base); | 966 | iounmap(mcbsp->io_base); |
| 979 | 967 | ||
| 980 | if (mcbsp->num_clks) { | 968 | mcbsp->fclk = NULL; |
| 981 | kfree(mcbsp->clks); | 969 | mcbsp->iclk = NULL; |
| 982 | mcbsp->clks = NULL; | ||
| 983 | mcbsp->num_clks = 0; | ||
| 984 | } | ||
| 985 | mcbsp->free = 0; | 970 | mcbsp->free = 0; |
| 986 | mcbsp->dev = NULL; | 971 | mcbsp->dev = NULL; |
| 987 | } | 972 | } |
| @@ -1002,4 +987,3 @@ int __init omap_mcbsp_init(void) | |||
| 1002 | /* Register the McBSP driver */ | 987 | /* Register the McBSP driver */ |
| 1003 | return platform_driver_register(&omap_mcbsp_driver); | 988 | return platform_driver_register(&omap_mcbsp_driver); |
| 1004 | } | 989 | } |
| 1005 | |||
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index be7bcaf2b832..fa5297d643d3 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c | |||
| @@ -148,7 +148,7 @@ void __init omap_detect_sram(void) | |||
| 148 | omap_sram_base = OMAP1_SRAM_VA; | 148 | omap_sram_base = OMAP1_SRAM_VA; |
| 149 | omap_sram_start = OMAP1_SRAM_PA; | 149 | omap_sram_start = OMAP1_SRAM_PA; |
| 150 | 150 | ||
| 151 | if (cpu_is_omap730()) | 151 | if (cpu_is_omap7xx()) |
| 152 | omap_sram_size = 0x32000; /* 200K */ | 152 | omap_sram_size = 0x32000; /* 200K */ |
| 153 | else if (cpu_is_omap15xx()) | 153 | else if (cpu_is_omap15xx()) |
| 154 | omap_sram_size = 0x30000; /* 192K */ | 154 | omap_sram_size = 0x30000; /* 192K */ |
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c index e278de6862ae..509f2ed99e21 100644 --- a/arch/arm/plat-omap/usb.c +++ b/arch/arm/plat-omap/usb.c | |||
| @@ -729,30 +729,13 @@ static inline void omap_1510_usb_init(struct omap_usb_config *config) {} | |||
| 729 | 729 | ||
| 730 | /*-------------------------------------------------------------------------*/ | 730 | /*-------------------------------------------------------------------------*/ |
| 731 | 731 | ||
| 732 | static struct omap_usb_config platform_data; | 732 | void __init omap_usb_init(struct omap_usb_config *pdata) |
| 733 | |||
| 734 | static int __init | ||
| 735 | omap_usb_init(void) | ||
| 736 | { | 733 | { |
| 737 | const struct omap_usb_config *config; | ||
| 738 | |||
| 739 | config = omap_get_config(OMAP_TAG_USB, struct omap_usb_config); | ||
| 740 | if (config == NULL) { | ||
| 741 | printk(KERN_ERR "USB: No board-specific " | ||
| 742 | "platform config found\n"); | ||
| 743 | return -ENODEV; | ||
| 744 | } | ||
| 745 | platform_data = *config; | ||
| 746 | |||
| 747 | if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx()) | 734 | if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx()) |
| 748 | omap_otg_init(&platform_data); | 735 | omap_otg_init(pdata); |
| 749 | else if (cpu_is_omap15xx()) | 736 | else if (cpu_is_omap15xx()) |
| 750 | omap_1510_usb_init(&platform_data); | 737 | omap_1510_usb_init(pdata); |
| 751 | else { | 738 | else |
| 752 | printk(KERN_ERR "USB: No init for your chip yet\n"); | 739 | printk(KERN_ERR "USB: No init for your chip yet\n"); |
| 753 | return -ENODEV; | ||
| 754 | } | ||
| 755 | return 0; | ||
| 756 | } | 740 | } |
| 757 | 741 | ||
| 758 | subsys_initcall(omap_usb_init); | ||
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c index 0d12c2164766..32eb9e33bebb 100644 --- a/arch/arm/plat-orion/gpio.c +++ b/arch/arm/plat-orion/gpio.c | |||
| @@ -19,7 +19,8 @@ | |||
| 19 | 19 | ||
| 20 | static DEFINE_SPINLOCK(gpio_lock); | 20 | static DEFINE_SPINLOCK(gpio_lock); |
| 21 | static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ | 21 | static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ |
| 22 | static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; | 22 | static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)]; |
| 23 | static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)]; | ||
| 23 | 24 | ||
| 24 | static inline void __set_direction(unsigned pin, int input) | 25 | static inline void __set_direction(unsigned pin, int input) |
| 25 | { | 26 | { |
| @@ -53,7 +54,7 @@ int gpio_direction_input(unsigned pin) | |||
| 53 | { | 54 | { |
| 54 | unsigned long flags; | 55 | unsigned long flags; |
| 55 | 56 | ||
| 56 | if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { | 57 | if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid_input)) { |
| 57 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); | 58 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); |
| 58 | return -EINVAL; | 59 | return -EINVAL; |
| 59 | } | 60 | } |
| @@ -83,7 +84,7 @@ int gpio_direction_output(unsigned pin, int value) | |||
| 83 | unsigned long flags; | 84 | unsigned long flags; |
| 84 | u32 u; | 85 | u32 u; |
| 85 | 86 | ||
| 86 | if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { | 87 | if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid_output)) { |
| 87 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); | 88 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); |
| 88 | return -EINVAL; | 89 | return -EINVAL; |
| 89 | } | 90 | } |
| @@ -161,7 +162,9 @@ int gpio_request(unsigned pin, const char *label) | |||
| 161 | unsigned long flags; | 162 | unsigned long flags; |
| 162 | int ret; | 163 | int ret; |
| 163 | 164 | ||
| 164 | if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { | 165 | if (pin >= GPIO_MAX || |
| 166 | !(test_bit(pin, gpio_valid_input) || | ||
| 167 | test_bit(pin, gpio_valid_output))) { | ||
| 165 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); | 168 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); |
| 166 | return -EINVAL; | 169 | return -EINVAL; |
| 167 | } | 170 | } |
| @@ -183,7 +186,9 @@ EXPORT_SYMBOL(gpio_request); | |||
| 183 | 186 | ||
| 184 | void gpio_free(unsigned pin) | 187 | void gpio_free(unsigned pin) |
| 185 | { | 188 | { |
| 186 | if (pin >= GPIO_MAX || !test_bit(pin, gpio_valid)) { | 189 | if (pin >= GPIO_MAX || |
| 190 | !(test_bit(pin, gpio_valid_input) || | ||
| 191 | test_bit(pin, gpio_valid_output))) { | ||
| 187 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); | 192 | pr_debug("%s: invalid GPIO %d\n", __func__, pin); |
| 188 | return; | 193 | return; |
| 189 | } | 194 | } |
| @@ -208,12 +213,18 @@ void __init orion_gpio_set_unused(unsigned pin) | |||
| 208 | __set_direction(pin, 0); | 213 | __set_direction(pin, 0); |
| 209 | } | 214 | } |
| 210 | 215 | ||
| 211 | void __init orion_gpio_set_valid(unsigned pin, int valid) | 216 | void __init orion_gpio_set_valid(unsigned pin, int mode) |
| 212 | { | 217 | { |
| 213 | if (valid) | 218 | if (mode == 1) |
| 214 | __set_bit(pin, gpio_valid); | 219 | mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK; |
| 220 | if (mode & GPIO_INPUT_OK) | ||
| 221 | __set_bit(pin, gpio_valid_input); | ||
| 215 | else | 222 | else |
| 216 | __clear_bit(pin, gpio_valid); | 223 | __clear_bit(pin, gpio_valid_input); |
| 224 | if (mode & GPIO_OUTPUT_OK) | ||
| 225 | __set_bit(pin, gpio_valid_output); | ||
| 226 | else | ||
| 227 | __clear_bit(pin, gpio_valid_output); | ||
| 217 | } | 228 | } |
| 218 | 229 | ||
| 219 | void orion_gpio_set_blink(unsigned pin, int blink) | 230 | void orion_gpio_set_blink(unsigned pin, int blink) |
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h index ec743e82c876..33f6c6aec185 100644 --- a/arch/arm/plat-orion/include/plat/gpio.h +++ b/arch/arm/plat-orion/include/plat/gpio.h | |||
| @@ -25,9 +25,13 @@ void gpio_set_value(unsigned pin, int value); | |||
| 25 | * Orion-specific GPIO API extensions. | 25 | * Orion-specific GPIO API extensions. |
| 26 | */ | 26 | */ |
| 27 | void orion_gpio_set_unused(unsigned pin); | 27 | void orion_gpio_set_unused(unsigned pin); |
| 28 | void orion_gpio_set_valid(unsigned pin, int valid); | ||
| 29 | void orion_gpio_set_blink(unsigned pin, int blink); | 28 | void orion_gpio_set_blink(unsigned pin, int blink); |
| 30 | 29 | ||
| 30 | #define GPIO_BIDI_OK (1 << 0) | ||
| 31 | #define GPIO_INPUT_OK (1 << 1) | ||
| 32 | #define GPIO_OUTPUT_OK (1 << 2) | ||
| 33 | void orion_gpio_set_valid(unsigned pin, int mode); | ||
| 34 | |||
| 31 | /* | 35 | /* |
| 32 | * GPIO interrupt handling. | 36 | * GPIO interrupt handling. |
| 33 | */ | 37 | */ |
diff --git a/arch/arm/plat-orion/include/plat/mvsdio.h b/arch/arm/plat-orion/include/plat/mvsdio.h new file mode 100644 index 000000000000..14ca88676002 --- /dev/null +++ b/arch/arm/plat-orion/include/plat/mvsdio.h | |||
| @@ -0,0 +1,21 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-orion/include/plat/mvsdio.h | ||
| 3 | * | ||
| 4 | * This file is licensed under the terms of the GNU General Public | ||
| 5 | * License version 2. This program is licensed "as is" without any | ||
| 6 | * warranty of any kind, whether express or implied. | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef __MACH_MVSDIO_H | ||
| 10 | #define __MACH_MVSDIO_H | ||
| 11 | |||
| 12 | #include <linux/mbus.h> | ||
| 13 | |||
| 14 | struct mvsdio_platform_data { | ||
| 15 | struct mbus_dram_target_info *dram; | ||
| 16 | unsigned int clock; | ||
| 17 | int gpio_card_detect; | ||
| 18 | int gpio_write_protect; | ||
| 19 | }; | ||
| 20 | |||
| 21 | #endif | ||
diff --git a/arch/arm/plat-pxa/Kconfig b/arch/arm/plat-pxa/Kconfig new file mode 100644 index 000000000000..b158e98038ed --- /dev/null +++ b/arch/arm/plat-pxa/Kconfig | |||
| @@ -0,0 +1,3 @@ | |||
| 1 | if PLAT_PXA | ||
| 2 | |||
| 3 | endif | ||
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile new file mode 100644 index 000000000000..4be37235f57b --- /dev/null +++ b/arch/arm/plat-pxa/Makefile | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | # | ||
| 2 | # Makefile for code common across different PXA processor families | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-y := dma.o mfp.o | ||
| 6 | |||
| 7 | obj-$(CONFIG_GENERIC_GPIO) += gpio.o | ||
diff --git a/arch/arm/mach-pxa/dma.c b/arch/arm/plat-pxa/dma.c index 7de17fc5d54b..70aeee407f7d 100644 --- a/arch/arm/mach-pxa/dma.c +++ b/arch/arm/plat-pxa/dma.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * linux/arch/arm/mach-pxa/dma.c | 2 | * linux/arch/arm/plat-pxa/dma.c |
| 3 | * | 3 | * |
| 4 | * PXA DMA registration and IRQ dispatching | 4 | * PXA DMA registration and IRQ dispatching |
| 5 | * | 5 | * |
| @@ -23,8 +23,6 @@ | |||
| 23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
| 24 | #include <mach/dma.h> | 24 | #include <mach/dma.h> |
| 25 | 25 | ||
| 26 | #include <mach/pxa-regs.h> | ||
| 27 | |||
| 28 | struct dma_channel { | 26 | struct dma_channel { |
| 29 | char *name; | 27 | char *name; |
| 30 | pxa_dma_prio prio; | 28 | pxa_dma_prio prio; |
| @@ -36,8 +34,8 @@ static struct dma_channel *dma_channels; | |||
| 36 | static int num_dma_channels; | 34 | static int num_dma_channels; |
| 37 | 35 | ||
| 38 | int pxa_request_dma (char *name, pxa_dma_prio prio, | 36 | int pxa_request_dma (char *name, pxa_dma_prio prio, |
| 39 | void (*irq_handler)(int, void *), | 37 | void (*irq_handler)(int, void *), |
| 40 | void *data) | 38 | void *data) |
| 41 | { | 39 | { |
| 42 | unsigned long flags; | 40 | unsigned long flags; |
| 43 | int i, found = 0; | 41 | int i, found = 0; |
| @@ -113,7 +111,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id) | |||
| 113 | return IRQ_HANDLED; | 111 | return IRQ_HANDLED; |
| 114 | } | 112 | } |
| 115 | 113 | ||
| 116 | int __init pxa_init_dma(int num_ch) | 114 | int __init pxa_init_dma(int irq, int num_ch) |
| 117 | { | 115 | { |
| 118 | int i, ret; | 116 | int i, ret; |
| 119 | 117 | ||
| @@ -131,7 +129,7 @@ int __init pxa_init_dma(int num_ch) | |||
| 131 | dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW); | 129 | dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW); |
| 132 | } | 130 | } |
| 133 | 131 | ||
| 134 | ret = request_irq(IRQ_DMA, dma_irq_handler, IRQF_DISABLED, "DMA", NULL); | 132 | ret = request_irq(irq, dma_irq_handler, IRQF_DISABLED, "DMA", NULL); |
| 135 | if (ret) { | 133 | if (ret) { |
| 136 | printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n"); | 134 | printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n"); |
| 137 | kfree(dma_channels); | 135 | kfree(dma_channels); |
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c new file mode 100644 index 000000000000..af819bf21b63 --- /dev/null +++ b/arch/arm/plat-pxa/gpio.c | |||
| @@ -0,0 +1,337 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/plat-pxa/gpio.c | ||
| 3 | * | ||
| 4 | * Generic PXA GPIO handling | ||
| 5 | * | ||
| 6 | * Author: Nicolas Pitre | ||
| 7 | * Created: Jun 15, 2001 | ||
| 8 | * Copyright: MontaVista Software Inc. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/irq.h> | ||
| 17 | #include <linux/io.h> | ||
| 18 | #include <linux/sysdev.h> | ||
| 19 | #include <linux/bootmem.h> | ||
| 20 | |||
| 21 | #include <mach/gpio.h> | ||
| 22 | |||
| 23 | int pxa_last_gpio; | ||
| 24 | |||
| 25 | struct pxa_gpio_chip { | ||
| 26 | struct gpio_chip chip; | ||
| 27 | void __iomem *regbase; | ||
| 28 | char label[10]; | ||
| 29 | |||
| 30 | unsigned long irq_mask; | ||
| 31 | unsigned long irq_edge_rise; | ||
| 32 | unsigned long irq_edge_fall; | ||
| 33 | |||
| 34 | #ifdef CONFIG_PM | ||
| 35 | unsigned long saved_gplr; | ||
| 36 | unsigned long saved_gpdr; | ||
| 37 | unsigned long saved_grer; | ||
| 38 | unsigned long saved_gfer; | ||
| 39 | #endif | ||
| 40 | }; | ||
| 41 | |||
| 42 | static DEFINE_SPINLOCK(gpio_lock); | ||
| 43 | static struct pxa_gpio_chip *pxa_gpio_chips; | ||
| 44 | |||
| 45 | #define for_each_gpio_chip(i, c) \ | ||
| 46 | for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++) | ||
| 47 | |||
| 48 | static inline void __iomem *gpio_chip_base(struct gpio_chip *c) | ||
| 49 | { | ||
| 50 | return container_of(c, struct pxa_gpio_chip, chip)->regbase; | ||
| 51 | } | ||
| 52 | |||
| 53 | static inline struct pxa_gpio_chip *gpio_to_chip(unsigned gpio) | ||
| 54 | { | ||
| 55 | return &pxa_gpio_chips[gpio_to_bank(gpio)]; | ||
| 56 | } | ||
| 57 | |||
| 58 | static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | ||
| 59 | { | ||
| 60 | void __iomem *base = gpio_chip_base(chip); | ||
| 61 | uint32_t value, mask = 1 << offset; | ||
| 62 | unsigned long flags; | ||
| 63 | |||
| 64 | spin_lock_irqsave(&gpio_lock, flags); | ||
| 65 | |||
| 66 | value = __raw_readl(base + GPDR_OFFSET); | ||
| 67 | if (__gpio_is_inverted(chip->base + offset)) | ||
| 68 | value |= mask; | ||
| 69 | else | ||
| 70 | value &= ~mask; | ||
| 71 | __raw_writel(value, base + GPDR_OFFSET); | ||
| 72 | |||
| 73 | spin_unlock_irqrestore(&gpio_lock, flags); | ||
| 74 | return 0; | ||
| 75 | } | ||
| 76 | |||
| 77 | static int pxa_gpio_direction_output(struct gpio_chip *chip, | ||
| 78 | unsigned offset, int value) | ||
| 79 | { | ||
| 80 | void __iomem *base = gpio_chip_base(chip); | ||
| 81 | uint32_t tmp, mask = 1 << offset; | ||
| 82 | unsigned long flags; | ||
| 83 | |||
| 84 | __raw_writel(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET)); | ||
| 85 | |||
| 86 | spin_lock_irqsave(&gpio_lock, flags); | ||
| 87 | |||
| 88 | tmp = __raw_readl(base + GPDR_OFFSET); | ||
| 89 | if (__gpio_is_inverted(chip->base + offset)) | ||
| 90 | tmp &= ~mask; | ||
| 91 | else | ||
| 92 | tmp |= mask; | ||
| 93 | __raw_writel(tmp, base + GPDR_OFFSET); | ||
| 94 | |||
| 95 | spin_unlock_irqrestore(&gpio_lock, flags); | ||
| 96 | return 0; | ||
| 97 | } | ||
| 98 | |||
| 99 | static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset) | ||
| 100 | { | ||
| 101 | return __raw_readl(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset); | ||
| 102 | } | ||
| 103 | |||
| 104 | static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | ||
| 105 | { | ||
| 106 | __raw_writel(1 << offset, gpio_chip_base(chip) + | ||
| 107 | (value ? GPSR_OFFSET : GPCR_OFFSET)); | ||
| 108 | } | ||
| 109 | |||
| 110 | static int __init pxa_init_gpio_chip(int gpio_end) | ||
| 111 | { | ||
| 112 | int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1; | ||
| 113 | struct pxa_gpio_chip *chips; | ||
| 114 | |||
| 115 | /* this is early, we have to use bootmem allocator, and we really | ||
| 116 | * want this to be allocated dynamically for different 'gpio_end' | ||
| 117 | */ | ||
| 118 | chips = alloc_bootmem_low(nbanks * sizeof(struct pxa_gpio_chip)); | ||
| 119 | if (chips == NULL) { | ||
| 120 | pr_err("%s: failed to allocate GPIO chips\n", __func__); | ||
| 121 | return -ENOMEM; | ||
| 122 | } | ||
| 123 | |||
| 124 | for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) { | ||
| 125 | struct gpio_chip *c = &chips[i].chip; | ||
| 126 | |||
| 127 | sprintf(chips[i].label, "gpio-%d", i); | ||
| 128 | chips[i].regbase = (void __iomem *)GPIO_BANK(i); | ||
| 129 | |||
| 130 | c->base = gpio; | ||
| 131 | c->label = chips[i].label; | ||
| 132 | |||
| 133 | c->direction_input = pxa_gpio_direction_input; | ||
| 134 | c->direction_output = pxa_gpio_direction_output; | ||
| 135 | c->get = pxa_gpio_get; | ||
| 136 | c->set = pxa_gpio_set; | ||
| 137 | |||
| 138 | /* number of GPIOs on last bank may be less than 32 */ | ||
| 139 | c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32; | ||
| 140 | gpiochip_add(c); | ||
| 141 | } | ||
| 142 | pxa_gpio_chips = chips; | ||
| 143 | return 0; | ||
| 144 | } | ||
| 145 | |||
| 146 | static int pxa_gpio_irq_type(unsigned int irq, unsigned int type) | ||
| 147 | { | ||
| 148 | struct pxa_gpio_chip *c; | ||
| 149 | int gpio = irq_to_gpio(irq); | ||
| 150 | unsigned long gpdr, mask = GPIO_bit(gpio); | ||
| 151 | |||
| 152 | c = gpio_to_chip(gpio); | ||
| 153 | |||
| 154 | if (type == IRQ_TYPE_PROBE) { | ||
| 155 | /* Don't mess with enabled GPIOs using preconfigured edges or | ||
| 156 | * GPIOs set to alternate function or to output during probe | ||
| 157 | */ | ||
| 158 | if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio)) | ||
| 159 | return 0; | ||
| 160 | |||
| 161 | if (__gpio_is_occupied(gpio)) | ||
| 162 | return 0; | ||
| 163 | |||
| 164 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; | ||
| 165 | } | ||
| 166 | |||
| 167 | gpdr = __raw_readl(c->regbase + GPDR_OFFSET); | ||
| 168 | |||
| 169 | if (__gpio_is_inverted(gpio)) | ||
| 170 | __raw_writel(gpdr | mask, c->regbase + GPDR_OFFSET); | ||
| 171 | else | ||
| 172 | __raw_writel(gpdr & ~mask, c->regbase + GPDR_OFFSET); | ||
| 173 | |||
| 174 | if (type & IRQ_TYPE_EDGE_RISING) | ||
| 175 | c->irq_edge_rise |= mask; | ||
| 176 | else | ||
| 177 | c->irq_edge_rise &= ~mask; | ||
| 178 | |||
| 179 | if (type & IRQ_TYPE_EDGE_FALLING) | ||
| 180 | c->irq_edge_fall |= mask; | ||
| 181 | else | ||
| 182 | c->irq_edge_fall &= ~mask; | ||
| 183 | |||
| 184 | __raw_writel(c->irq_edge_rise & c->irq_mask, c->regbase + GRER_OFFSET); | ||
| 185 | __raw_writel(c->irq_edge_fall & c->irq_mask, c->regbase + GFER_OFFSET); | ||
| 186 | |||
| 187 | pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, irq, gpio, | ||
| 188 | ((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""), | ||
| 189 | ((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : "")); | ||
| 190 | return 0; | ||
| 191 | } | ||
| 192 | |||
| 193 | static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc) | ||
| 194 | { | ||
| 195 | struct pxa_gpio_chip *c; | ||
| 196 | int loop, gpio, gpio_base, n; | ||
| 197 | unsigned long gedr; | ||
| 198 | |||
| 199 | do { | ||
| 200 | loop = 0; | ||
| 201 | for_each_gpio_chip(gpio, c) { | ||
| 202 | gpio_base = c->chip.base; | ||
| 203 | |||
| 204 | gedr = __raw_readl(c->regbase + GEDR_OFFSET); | ||
| 205 | gedr = gedr & c->irq_mask; | ||
| 206 | __raw_writel(gedr, c->regbase + GEDR_OFFSET); | ||
| 207 | |||
| 208 | n = find_first_bit(&gedr, BITS_PER_LONG); | ||
| 209 | while (n < BITS_PER_LONG) { | ||
| 210 | loop = 1; | ||
| 211 | |||
| 212 | generic_handle_irq(gpio_to_irq(gpio_base + n)); | ||
| 213 | n = find_next_bit(&gedr, BITS_PER_LONG, n + 1); | ||
| 214 | } | ||
| 215 | } | ||
| 216 | } while (loop); | ||
| 217 | } | ||
| 218 | |||
| 219 | static void pxa_ack_muxed_gpio(unsigned int irq) | ||
| 220 | { | ||
| 221 | int gpio = irq_to_gpio(irq); | ||
| 222 | struct pxa_gpio_chip *c = gpio_to_chip(gpio); | ||
| 223 | |||
| 224 | __raw_writel(GPIO_bit(gpio), c->regbase + GEDR_OFFSET); | ||
| 225 | } | ||
| 226 | |||
| 227 | static void pxa_mask_muxed_gpio(unsigned int irq) | ||
| 228 | { | ||
| 229 | int gpio = irq_to_gpio(irq); | ||
| 230 | struct pxa_gpio_chip *c = gpio_to_chip(gpio); | ||
| 231 | uint32_t grer, gfer; | ||
| 232 | |||
| 233 | c->irq_mask &= ~GPIO_bit(gpio); | ||
| 234 | |||
| 235 | grer = __raw_readl(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio); | ||
| 236 | gfer = __raw_readl(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio); | ||
| 237 | __raw_writel(grer, c->regbase + GRER_OFFSET); | ||
| 238 | __raw_writel(gfer, c->regbase + GFER_OFFSET); | ||
| 239 | } | ||
| 240 | |||
| 241 | static void pxa_unmask_muxed_gpio(unsigned int irq) | ||
| 242 | { | ||
| 243 | int gpio = irq_to_gpio(irq); | ||
| 244 | struct pxa_gpio_chip *c = gpio_to_chip(gpio); | ||
| 245 | |||
| 246 | c->irq_mask |= GPIO_bit(gpio); | ||
| 247 | __raw_writel(c->irq_edge_rise & c->irq_mask, c->regbase + GRER_OFFSET); | ||
| 248 | __raw_writel(c->irq_edge_fall & c->irq_mask, c->regbase + GFER_OFFSET); | ||
| 249 | } | ||
| 250 | |||
| 251 | static struct irq_chip pxa_muxed_gpio_chip = { | ||
| 252 | .name = "GPIO", | ||
| 253 | .ack = pxa_ack_muxed_gpio, | ||
| 254 | .mask = pxa_mask_muxed_gpio, | ||
| 255 | .unmask = pxa_unmask_muxed_gpio, | ||
| 256 | .set_type = pxa_gpio_irq_type, | ||
| 257 | }; | ||
| 258 | |||
| 259 | void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn) | ||
| 260 | { | ||
| 261 | struct pxa_gpio_chip *c; | ||
| 262 | int gpio, irq; | ||
| 263 | |||
| 264 | pxa_last_gpio = end; | ||
| 265 | |||
| 266 | /* Initialize GPIO chips */ | ||
| 267 | pxa_init_gpio_chip(end); | ||
| 268 | |||
| 269 | /* clear all GPIO edge detects */ | ||
| 270 | for_each_gpio_chip(gpio, c) { | ||
| 271 | __raw_writel(0, c->regbase + GFER_OFFSET); | ||
| 272 | __raw_writel(0, c->regbase + GRER_OFFSET); | ||
| 273 | __raw_writel(~0,c->regbase + GEDR_OFFSET); | ||
| 274 | } | ||
| 275 | |||
| 276 | for (irq = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) { | ||
| 277 | set_irq_chip(irq, &pxa_muxed_gpio_chip); | ||
| 278 | set_irq_handler(irq, handle_edge_irq); | ||
| 279 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | ||
| 280 | } | ||
| 281 | |||
| 282 | /* Install handler for GPIO>=2 edge detect interrupts */ | ||
| 283 | set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler); | ||
| 284 | pxa_muxed_gpio_chip.set_wake = fn; | ||
| 285 | } | ||
| 286 | |||
| 287 | #ifdef CONFIG_PM | ||
| 288 | static int pxa_gpio_suspend(struct sys_device *dev, pm_message_t state) | ||
| 289 | { | ||
| 290 | struct pxa_gpio_chip *c; | ||
| 291 | int gpio; | ||
| 292 | |||
| 293 | for_each_gpio_chip(gpio, c) { | ||
| 294 | c->saved_gplr = __raw_readl(c->regbase + GPLR_OFFSET); | ||
| 295 | c->saved_gpdr = __raw_readl(c->regbase + GPDR_OFFSET); | ||
| 296 | c->saved_grer = __raw_readl(c->regbase + GRER_OFFSET); | ||
| 297 | c->saved_gfer = __raw_readl(c->regbase + GFER_OFFSET); | ||
| 298 | |||
| 299 | /* Clear GPIO transition detect bits */ | ||
| 300 | __raw_writel(0xffffffff, c->regbase + GEDR_OFFSET); | ||
| 301 | } | ||
| 302 | return 0; | ||
| 303 | } | ||
| 304 | |||
| 305 | static int pxa_gpio_resume(struct sys_device *dev) | ||
| 306 | { | ||
| 307 | struct pxa_gpio_chip *c; | ||
| 308 | int gpio; | ||
| 309 | |||
| 310 | for_each_gpio_chip(gpio, c) { | ||
| 311 | /* restore level with set/clear */ | ||
| 312 | __raw_writel( c->saved_gplr, c->regbase + GPSR_OFFSET); | ||
| 313 | __raw_writel(~c->saved_gplr, c->regbase + GPCR_OFFSET); | ||
| 314 | |||
| 315 | __raw_writel(c->saved_grer, c->regbase + GRER_OFFSET); | ||
| 316 | __raw_writel(c->saved_gfer, c->regbase + GFER_OFFSET); | ||
| 317 | __raw_writel(c->saved_gpdr, c->regbase + GPDR_OFFSET); | ||
| 318 | } | ||
| 319 | return 0; | ||
| 320 | } | ||
| 321 | #else | ||
| 322 | #define pxa_gpio_suspend NULL | ||
| 323 | #define pxa_gpio_resume NULL | ||
| 324 | #endif | ||
| 325 | |||
| 326 | struct sysdev_class pxa_gpio_sysclass = { | ||
| 327 | .name = "gpio", | ||
| 328 | .suspend = pxa_gpio_suspend, | ||
| 329 | .resume = pxa_gpio_resume, | ||
| 330 | }; | ||
| 331 | |||
| 332 | static int __init pxa_gpio_init(void) | ||
| 333 | { | ||
| 334 | return sysdev_class_register(&pxa_gpio_sysclass); | ||
| 335 | } | ||
| 336 | |||
| 337 | core_initcall(pxa_gpio_init); | ||
diff --git a/arch/arm/plat-pxa/include/plat/dma.h b/arch/arm/plat-pxa/include/plat/dma.h new file mode 100644 index 000000000000..a7b91dc06852 --- /dev/null +++ b/arch/arm/plat-pxa/include/plat/dma.h | |||
| @@ -0,0 +1,85 @@ | |||
| 1 | #ifndef __PLAT_DMA_H | ||
| 2 | #define __PLAT_DMA_H | ||
| 3 | |||
| 4 | #define DMAC_REG(x) (*((volatile u32 *)(DMAC_REGS_VIRT + (x)))) | ||
| 5 | |||
| 6 | #define DCSR(n) DMAC_REG((n) << 2) | ||
| 7 | #define DALGN DMAC_REG(0x00a0) /* DMA Alignment Register */ | ||
| 8 | #define DINT DMAC_REG(0x00f0) /* DMA Interrupt Register */ | ||
| 9 | #define DDADR(n) DMAC_REG(0x0200 + ((n) << 4)) | ||
| 10 | #define DSADR(n) DMAC_REG(0x0204 + ((n) << 4)) | ||
| 11 | #define DTADR(n) DMAC_REG(0x0208 + ((n) << 4)) | ||
| 12 | #define DCMD(n) DMAC_REG(0x020c + ((n) << 4)) | ||
| 13 | #define DRCMR(n) DMAC_REG((((n) < 64) ? 0x0100 : 0x1100) + \ | ||
| 14 | (((n) & 0x3f) << 2)) | ||
| 15 | |||
| 16 | #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ | ||
| 17 | #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ | ||
| 18 | #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */ | ||
| 19 | #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */ | ||
| 20 | #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */ | ||
| 21 | #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */ | ||
| 22 | #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ | ||
| 23 | #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ | ||
| 24 | |||
| 25 | #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */ | ||
| 26 | #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */ | ||
| 27 | #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */ | ||
| 28 | #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */ | ||
| 29 | #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */ | ||
| 30 | #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */ | ||
| 31 | #define DCSR_EORINTR (1 << 9) /* The end of Receive */ | ||
| 32 | |||
| 33 | #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ | ||
| 34 | #define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */ | ||
| 35 | |||
| 36 | #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ | ||
| 37 | #define DDADR_STOP (1 << 0) /* Stop (read / write) */ | ||
| 38 | |||
| 39 | #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */ | ||
| 40 | #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */ | ||
| 41 | #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */ | ||
| 42 | #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */ | ||
| 43 | #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */ | ||
| 44 | #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */ | ||
| 45 | #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */ | ||
| 46 | #define DCMD_BURST8 (1 << 16) /* 8 byte burst */ | ||
| 47 | #define DCMD_BURST16 (2 << 16) /* 16 byte burst */ | ||
| 48 | #define DCMD_BURST32 (3 << 16) /* 32 byte burst */ | ||
| 49 | #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */ | ||
| 50 | #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */ | ||
| 51 | #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */ | ||
| 52 | #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */ | ||
| 53 | |||
| 54 | /* | ||
| 55 | * Descriptor structure for PXA's DMA engine | ||
| 56 | * Note: this structure must always be aligned to a 16-byte boundary. | ||
| 57 | */ | ||
| 58 | |||
| 59 | typedef struct pxa_dma_desc { | ||
| 60 | volatile u32 ddadr; /* Points to the next descriptor + flags */ | ||
| 61 | volatile u32 dsadr; /* DSADR value for the current transfer */ | ||
| 62 | volatile u32 dtadr; /* DTADR value for the current transfer */ | ||
| 63 | volatile u32 dcmd; /* DCMD value for the current transfer */ | ||
| 64 | } pxa_dma_desc; | ||
| 65 | |||
| 66 | typedef enum { | ||
| 67 | DMA_PRIO_HIGH = 0, | ||
| 68 | DMA_PRIO_MEDIUM = 1, | ||
| 69 | DMA_PRIO_LOW = 2 | ||
| 70 | } pxa_dma_prio; | ||
| 71 | |||
| 72 | /* | ||
| 73 | * DMA registration | ||
| 74 | */ | ||
| 75 | |||
| 76 | int __init pxa_init_dma(int irq, int num_ch); | ||
| 77 | |||
| 78 | int pxa_request_dma (char *name, | ||
| 79 | pxa_dma_prio prio, | ||
| 80 | void (*irq_handler)(int, void *), | ||
| 81 | void *data); | ||
| 82 | |||
| 83 | void pxa_free_dma (int dma_ch); | ||
| 84 | |||
| 85 | #endif /* __PLAT_DMA_H */ | ||
diff --git a/arch/arm/plat-pxa/include/plat/gpio.h b/arch/arm/plat-pxa/include/plat/gpio.h new file mode 100644 index 000000000000..44248cb926a5 --- /dev/null +++ b/arch/arm/plat-pxa/include/plat/gpio.h | |||
| @@ -0,0 +1,62 @@ | |||
| 1 | #ifndef __PLAT_GPIO_H | ||
| 2 | #define __PLAT_GPIO_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with | ||
| 6 | * one set of registers. The register offsets are organized below: | ||
| 7 | * | ||
| 8 | * GPLR GPDR GPSR GPCR GRER GFER GEDR | ||
| 9 | * BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048 | ||
| 10 | * BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C | ||
| 11 | * BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050 | ||
| 12 | * | ||
| 13 | * BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148 | ||
| 14 | * BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C | ||
| 15 | * BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150 | ||
| 16 | * | ||
| 17 | * NOTE: | ||
| 18 | * BANK 3 is only available on PXA27x and later processors. | ||
| 19 | * BANK 4 and 5 are only available on PXA935 | ||
| 20 | */ | ||
| 21 | |||
| 22 | #define GPIO_BANK(n) (GPIO_REGS_VIRT + BANK_OFF(n)) | ||
| 23 | |||
| 24 | #define GPLR_OFFSET 0x00 | ||
| 25 | #define GPDR_OFFSET 0x0C | ||
| 26 | #define GPSR_OFFSET 0x18 | ||
| 27 | #define GPCR_OFFSET 0x24 | ||
| 28 | #define GRER_OFFSET 0x30 | ||
| 29 | #define GFER_OFFSET 0x3C | ||
| 30 | #define GEDR_OFFSET 0x48 | ||
| 31 | |||
| 32 | static inline int gpio_get_value(unsigned gpio) | ||
| 33 | { | ||
| 34 | if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) | ||
| 35 | return GPLR(gpio) & GPIO_bit(gpio); | ||
| 36 | else | ||
| 37 | return __gpio_get_value(gpio); | ||
| 38 | } | ||
| 39 | |||
| 40 | static inline void gpio_set_value(unsigned gpio, int value) | ||
| 41 | { | ||
| 42 | if (__builtin_constant_p(gpio) && (gpio < NR_BUILTIN_GPIO)) { | ||
| 43 | if (value) | ||
| 44 | GPSR(gpio) = GPIO_bit(gpio); | ||
| 45 | else | ||
| 46 | GPCR(gpio) = GPIO_bit(gpio); | ||
| 47 | } else | ||
| 48 | __gpio_set_value(gpio, value); | ||
| 49 | } | ||
| 50 | |||
| 51 | #define gpio_cansleep __gpio_cansleep | ||
| 52 | |||
| 53 | /* NOTE: some PXAs have fewer on-chip GPIOs (like PXA255, with 85). | ||
| 54 | * Those cases currently cause holes in the GPIO number space, the | ||
| 55 | * actual number of the last GPIO is recorded by 'pxa_last_gpio'. | ||
| 56 | */ | ||
| 57 | extern int pxa_last_gpio; | ||
| 58 | |||
| 59 | typedef int (*set_wake_t)(unsigned int irq, unsigned int on); | ||
| 60 | |||
| 61 | extern void pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn); | ||
| 62 | #endif /* __PLAT_GPIO_H */ | ||
diff --git a/arch/arm/plat-pxa/include/plat/mfp.h b/arch/arm/plat-pxa/include/plat/mfp.h new file mode 100644 index 000000000000..64019464c8db --- /dev/null +++ b/arch/arm/plat-pxa/include/plat/mfp.h | |||
| @@ -0,0 +1,399 @@ | |||
| 1 | /* | ||
| 2 | * arch/arm/plat-pxa/include/plat/mfp.h | ||
| 3 | * | ||
| 4 | * Common Multi-Function Pin Definitions | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007 Marvell International Ltd. | ||
| 7 | * | ||
| 8 | * 2007-8-21: eric miao <eric.miao@marvell.com> | ||
| 9 | * initial version | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef __ASM_PLAT_MFP_H | ||
| 17 | #define __ASM_PLAT_MFP_H | ||
| 18 | |||
| 19 | #define mfp_to_gpio(m) ((m) % 128) | ||
| 20 | |||
| 21 | /* list of all the configurable MFP pins */ | ||
| 22 | enum { | ||
| 23 | MFP_PIN_INVALID = -1, | ||
| 24 | |||
| 25 | MFP_PIN_GPIO0 = 0, | ||
| 26 | MFP_PIN_GPIO1, | ||
| 27 | MFP_PIN_GPIO2, | ||
| 28 | MFP_PIN_GPIO3, | ||
| 29 | MFP_PIN_GPIO4, | ||
| 30 | MFP_PIN_GPIO5, | ||
| 31 | MFP_PIN_GPIO6, | ||
| 32 | MFP_PIN_GPIO7, | ||
| 33 | MFP_PIN_GPIO8, | ||
| 34 | MFP_PIN_GPIO9, | ||
| 35 | MFP_PIN_GPIO10, | ||
| 36 | MFP_PIN_GPIO11, | ||
| 37 | MFP_PIN_GPIO12, | ||
| 38 | MFP_PIN_GPIO13, | ||
| 39 | MFP_PIN_GPIO14, | ||
| 40 | MFP_PIN_GPIO15, | ||
| 41 | MFP_PIN_GPIO16, | ||
| 42 | MFP_PIN_GPIO17, | ||
| 43 | MFP_PIN_GPIO18, | ||
| 44 | MFP_PIN_GPIO19, | ||
| 45 | MFP_PIN_GPIO20, | ||
| 46 | MFP_PIN_GPIO21, | ||
| 47 | MFP_PIN_GPIO22, | ||
| 48 | MFP_PIN_GPIO23, | ||
| 49 | MFP_PIN_GPIO24, | ||
| 50 | MFP_PIN_GPIO25, | ||
| 51 | MFP_PIN_GPIO26, | ||
| 52 | MFP_PIN_GPIO27, | ||
| 53 | MFP_PIN_GPIO28, | ||
| 54 | MFP_PIN_GPIO29, | ||
| 55 | MFP_PIN_GPIO30, | ||
| 56 | MFP_PIN_GPIO31, | ||
| 57 | MFP_PIN_GPIO32, | ||
| 58 | MFP_PIN_GPIO33, | ||
| 59 | MFP_PIN_GPIO34, | ||
| 60 | MFP_PIN_GPIO35, | ||
| 61 | MFP_PIN_GPIO36, | ||
| 62 | MFP_PIN_GPIO37, | ||
| 63 | MFP_PIN_GPIO38, | ||
| 64 | MFP_PIN_GPIO39, | ||
| 65 | MFP_PIN_GPIO40, | ||
| 66 | MFP_PIN_GPIO41, | ||
| 67 | MFP_PIN_GPIO42, | ||
| 68 | MFP_PIN_GPIO43, | ||
| 69 | MFP_PIN_GPIO44, | ||
| 70 | MFP_PIN_GPIO45, | ||
| 71 | MFP_PIN_GPIO46, | ||
| 72 | MFP_PIN_GPIO47, | ||
| 73 | MFP_PIN_GPIO48, | ||
| 74 | MFP_PIN_GPIO49, | ||
| 75 | MFP_PIN_GPIO50, | ||
| 76 | MFP_PIN_GPIO51, | ||
| 77 | MFP_PIN_GPIO52, | ||
| 78 | MFP_PIN_GPIO53, | ||
| 79 | MFP_PIN_GPIO54, | ||
| 80 | MFP_PIN_GPIO55, | ||
| 81 | MFP_PIN_GPIO56, | ||
| 82 | MFP_PIN_GPIO57, | ||
| 83 | MFP_PIN_GPIO58, | ||
| 84 | MFP_PIN_GPIO59, | ||
| 85 | MFP_PIN_GPIO60, | ||
| 86 | MFP_PIN_GPIO61, | ||
| 87 | MFP_PIN_GPIO62, | ||
| 88 | MFP_PIN_GPIO63, | ||
| 89 | MFP_PIN_GPIO64, | ||
| 90 | MFP_PIN_GPIO65, | ||
| 91 | MFP_PIN_GPIO66, | ||
| 92 | MFP_PIN_GPIO67, | ||
| 93 | MFP_PIN_GPIO68, | ||
| 94 | MFP_PIN_GPIO69, | ||
| 95 | MFP_PIN_GPIO70, | ||
| 96 | MFP_PIN_GPIO71, | ||
| 97 | MFP_PIN_GPIO72, | ||
| 98 | MFP_PIN_GPIO73, | ||
| 99 | MFP_PIN_GPIO74, | ||
| 100 | MFP_PIN_GPIO75, | ||
| 101 | MFP_PIN_GPIO76, | ||
| 102 | MFP_PIN_GPIO77, | ||
| 103 | MFP_PIN_GPIO78, | ||
| 104 | MFP_PIN_GPIO79, | ||
| 105 | MFP_PIN_GPIO80, | ||
| 106 | MFP_PIN_GPIO81, | ||
| 107 | MFP_PIN_GPIO82, | ||
| 108 | MFP_PIN_GPIO83, | ||
| 109 | MFP_PIN_GPIO84, | ||
| 110 | MFP_PIN_GPIO85, | ||
| 111 | MFP_PIN_GPIO86, | ||
| 112 | MFP_PIN_GPIO87, | ||
| 113 | MFP_PIN_GPIO88, | ||
| 114 | MFP_PIN_GPIO89, | ||
| 115 | MFP_PIN_GPIO90, | ||
| 116 | MFP_PIN_GPIO91, | ||
| 117 | MFP_PIN_GPIO92, | ||
| 118 | MFP_PIN_GPIO93, | ||
| 119 | MFP_PIN_GPIO94, | ||
| 120 | MFP_PIN_GPIO95, | ||
| 121 | MFP_PIN_GPIO96, | ||
| 122 | MFP_PIN_GPIO97, | ||
| 123 | MFP_PIN_GPIO98, | ||
| 124 | MFP_PIN_GPIO99, | ||
| 125 | MFP_PIN_GPIO100, | ||
| 126 | MFP_PIN_GPIO101, | ||
| 127 | MFP_PIN_GPIO102, | ||
| 128 | MFP_PIN_GPIO103, | ||
| 129 | MFP_PIN_GPIO104, | ||
| 130 | MFP_PIN_GPIO105, | ||
| 131 | MFP_PIN_GPIO106, | ||
| 132 | MFP_PIN_GPIO107, | ||
| 133 | MFP_PIN_GPIO108, | ||
| 134 | MFP_PIN_GPIO109, | ||
| 135 | MFP_PIN_GPIO110, | ||
| 136 | MFP_PIN_GPIO111, | ||
| 137 | MFP_PIN_GPIO112, | ||
| 138 | MFP_PIN_GPIO113, | ||
| 139 | MFP_PIN_GPIO114, | ||
| 140 | MFP_PIN_GPIO115, | ||
| 141 | MFP_PIN_GPIO116, | ||
| 142 | MFP_PIN_GPIO117, | ||
| 143 | MFP_PIN_GPIO118, | ||
| 144 | MFP_PIN_GPIO119, | ||
| 145 | MFP_PIN_GPIO120, | ||
| 146 | MFP_PIN_GPIO121, | ||
| 147 | MFP_PIN_GPIO122, | ||
| 148 | MFP_PIN_GPIO123, | ||
| 149 | MFP_PIN_GPIO124, | ||
| 150 | MFP_PIN_GPIO125, | ||
| 151 | MFP_PIN_GPIO126, | ||
| 152 | MFP_PIN_GPIO127, | ||
| 153 | MFP_PIN_GPIO0_2, | ||
| 154 | MFP_PIN_GPIO1_2, | ||
| 155 | MFP_PIN_GPIO2_2, | ||
| 156 | MFP_PIN_GPIO3_2, | ||
| 157 | MFP_PIN_GPIO4_2, | ||
| 158 | MFP_PIN_GPIO5_2, | ||
| 159 | MFP_PIN_GPIO6_2, | ||
| 160 | MFP_PIN_GPIO7_2, | ||
| 161 | MFP_PIN_GPIO8_2, | ||
| 162 | MFP_PIN_GPIO9_2, | ||
| 163 | MFP_PIN_GPIO10_2, | ||
| 164 | MFP_PIN_GPIO11_2, | ||
| 165 | MFP_PIN_GPIO12_2, | ||
| 166 | MFP_PIN_GPIO13_2, | ||
| 167 | MFP_PIN_GPIO14_2, | ||
| 168 | MFP_PIN_GPIO15_2, | ||
| 169 | MFP_PIN_GPIO16_2, | ||
| 170 | MFP_PIN_GPIO17_2, | ||
| 171 | |||
| 172 | MFP_PIN_ULPI_STP, | ||
| 173 | MFP_PIN_ULPI_NXT, | ||
| 174 | MFP_PIN_ULPI_DIR, | ||
| 175 | |||
| 176 | MFP_PIN_nXCVREN, | ||
| 177 | MFP_PIN_DF_CLE_nOE, | ||
| 178 | MFP_PIN_DF_nADV1_ALE, | ||
| 179 | MFP_PIN_DF_SCLK_E, | ||
| 180 | MFP_PIN_DF_SCLK_S, | ||
| 181 | MFP_PIN_nBE0, | ||
| 182 | MFP_PIN_nBE1, | ||
| 183 | MFP_PIN_DF_nADV2_ALE, | ||
| 184 | MFP_PIN_DF_INT_RnB, | ||
| 185 | MFP_PIN_DF_nCS0, | ||
| 186 | MFP_PIN_DF_nCS1, | ||
| 187 | MFP_PIN_nLUA, | ||
| 188 | MFP_PIN_nLLA, | ||
| 189 | MFP_PIN_DF_nWE, | ||
| 190 | MFP_PIN_DF_ALE_nWE, | ||
| 191 | MFP_PIN_DF_nRE_nOE, | ||
| 192 | MFP_PIN_DF_ADDR0, | ||
| 193 | MFP_PIN_DF_ADDR1, | ||
| 194 | MFP_PIN_DF_ADDR2, | ||
| 195 | MFP_PIN_DF_ADDR3, | ||
| 196 | MFP_PIN_DF_IO0, | ||
| 197 | MFP_PIN_DF_IO1, | ||
| 198 | MFP_PIN_DF_IO2, | ||
| 199 | MFP_PIN_DF_IO3, | ||
| 200 | MFP_PIN_DF_IO4, | ||
| 201 | MFP_PIN_DF_IO5, | ||
| 202 | MFP_PIN_DF_IO6, | ||
| 203 | MFP_PIN_DF_IO7, | ||
| 204 | MFP_PIN_DF_IO8, | ||
| 205 | MFP_PIN_DF_IO9, | ||
| 206 | MFP_PIN_DF_IO10, | ||
| 207 | MFP_PIN_DF_IO11, | ||
| 208 | MFP_PIN_DF_IO12, | ||
| 209 | MFP_PIN_DF_IO13, | ||
| 210 | MFP_PIN_DF_IO14, | ||
| 211 | MFP_PIN_DF_IO15, | ||
| 212 | MFP_PIN_DF_nCS0_SM_nCS2, | ||
| 213 | MFP_PIN_DF_nCS1_SM_nCS3, | ||
| 214 | MFP_PIN_SM_nCS0, | ||
| 215 | MFP_PIN_SM_nCS1, | ||
| 216 | MFP_PIN_DF_WEn, | ||
| 217 | MFP_PIN_DF_REn, | ||
| 218 | MFP_PIN_DF_CLE_SM_OEn, | ||
| 219 | MFP_PIN_DF_ALE_SM_WEn, | ||
| 220 | MFP_PIN_DF_RDY0, | ||
| 221 | MFP_PIN_DF_RDY1, | ||
| 222 | |||
| 223 | MFP_PIN_SM_SCLK, | ||
| 224 | MFP_PIN_SM_BE0, | ||
| 225 | MFP_PIN_SM_BE1, | ||
| 226 | MFP_PIN_SM_ADV, | ||
| 227 | MFP_PIN_SM_ADVMUX, | ||
| 228 | MFP_PIN_SM_RDY, | ||
| 229 | |||
| 230 | MFP_PIN_MMC1_DAT7, | ||
| 231 | MFP_PIN_MMC1_DAT6, | ||
| 232 | MFP_PIN_MMC1_DAT5, | ||
| 233 | MFP_PIN_MMC1_DAT4, | ||
| 234 | MFP_PIN_MMC1_DAT3, | ||
| 235 | MFP_PIN_MMC1_DAT2, | ||
| 236 | MFP_PIN_MMC1_DAT1, | ||
| 237 | MFP_PIN_MMC1_DAT0, | ||
| 238 | MFP_PIN_MMC1_CMD, | ||
| 239 | MFP_PIN_MMC1_CLK, | ||
| 240 | MFP_PIN_MMC1_CD, | ||
| 241 | MFP_PIN_MMC1_WP, | ||
| 242 | |||
| 243 | /* additional pins on PXA930 */ | ||
| 244 | MFP_PIN_GSIM_UIO, | ||
| 245 | MFP_PIN_GSIM_UCLK, | ||
| 246 | MFP_PIN_GSIM_UDET, | ||
| 247 | MFP_PIN_GSIM_nURST, | ||
| 248 | MFP_PIN_PMIC_INT, | ||
| 249 | MFP_PIN_RDY, | ||
| 250 | |||
| 251 | MFP_PIN_MAX, | ||
| 252 | }; | ||
| 253 | |||
| 254 | /* | ||
| 255 | * a possible MFP configuration is represented by a 32-bit integer | ||
| 256 | * | ||
| 257 | * bit 0.. 9 - MFP Pin Number (1024 Pins Maximum) | ||
| 258 | * bit 10..12 - Alternate Function Selection | ||
| 259 | * bit 13..15 - Drive Strength | ||
| 260 | * bit 16..18 - Low Power Mode State | ||
| 261 | * bit 19..20 - Low Power Mode Edge Detection | ||
| 262 | * bit 21..22 - Run Mode Pull State | ||
| 263 | * | ||
| 264 | * to facilitate the definition, the following macros are provided | ||
| 265 | * | ||
| 266 | * MFP_CFG_DEFAULT - default MFP configuration value, with | ||
| 267 | * alternate function = 0, | ||
| 268 | * drive strength = fast 3mA (MFP_DS03X) | ||
| 269 | * low power mode = default | ||
| 270 | * edge detection = none | ||
| 271 | * | ||
| 272 | * MFP_CFG - default MFPR value with alternate function | ||
| 273 | * MFP_CFG_DRV - default MFPR value with alternate function and | ||
| 274 | * pin drive strength | ||
| 275 | * MFP_CFG_LPM - default MFPR value with alternate function and | ||
| 276 | * low power mode | ||
| 277 | * MFP_CFG_X - default MFPR value with alternate function, | ||
| 278 | * pin drive strength and low power mode | ||
| 279 | */ | ||
| 280 | |||
| 281 | typedef unsigned long mfp_cfg_t; | ||
| 282 | |||
| 283 | #define MFP_PIN(x) ((x) & 0x3ff) | ||
| 284 | |||
| 285 | #define MFP_AF0 (0x0 << 10) | ||
| 286 | #define MFP_AF1 (0x1 << 10) | ||
| 287 | #define MFP_AF2 (0x2 << 10) | ||
| 288 | #define MFP_AF3 (0x3 << 10) | ||
| 289 | #define MFP_AF4 (0x4 << 10) | ||
| 290 | #define MFP_AF5 (0x5 << 10) | ||
| 291 | #define MFP_AF6 (0x6 << 10) | ||
| 292 | #define MFP_AF7 (0x7 << 10) | ||
| 293 | #define MFP_AF_MASK (0x7 << 10) | ||
| 294 | #define MFP_AF(x) (((x) >> 10) & 0x7) | ||
| 295 | |||
| 296 | #define MFP_DS01X (0x0 << 13) | ||
| 297 | #define MFP_DS02X (0x1 << 13) | ||
| 298 | #define MFP_DS03X (0x2 << 13) | ||
| 299 | #define MFP_DS04X (0x3 << 13) | ||
| 300 | #define MFP_DS06X (0x4 << 13) | ||
| 301 | #define MFP_DS08X (0x5 << 13) | ||
| 302 | #define MFP_DS10X (0x6 << 13) | ||
| 303 | #define MFP_DS13X (0x7 << 13) | ||
| 304 | #define MFP_DS_MASK (0x7 << 13) | ||
| 305 | #define MFP_DS(x) (((x) >> 13) & 0x7) | ||
| 306 | |||
| 307 | #define MFP_LPM_DEFAULT (0x0 << 16) | ||
| 308 | #define MFP_LPM_DRIVE_LOW (0x1 << 16) | ||
| 309 | #define MFP_LPM_DRIVE_HIGH (0x2 << 16) | ||
| 310 | #define MFP_LPM_PULL_LOW (0x3 << 16) | ||
| 311 | #define MFP_LPM_PULL_HIGH (0x4 << 16) | ||
| 312 | #define MFP_LPM_FLOAT (0x5 << 16) | ||
| 313 | #define MFP_LPM_INPUT (0x6 << 16) | ||
| 314 | #define MFP_LPM_STATE_MASK (0x7 << 16) | ||
| 315 | #define MFP_LPM_STATE(x) (((x) >> 16) & 0x7) | ||
| 316 | |||
| 317 | #define MFP_LPM_EDGE_NONE (0x0 << 19) | ||
| 318 | #define MFP_LPM_EDGE_RISE (0x1 << 19) | ||
| 319 | #define MFP_LPM_EDGE_FALL (0x2 << 19) | ||
| 320 | #define MFP_LPM_EDGE_BOTH (0x3 << 19) | ||
| 321 | #define MFP_LPM_EDGE_MASK (0x3 << 19) | ||
| 322 | #define MFP_LPM_EDGE(x) (((x) >> 19) & 0x3) | ||
| 323 | |||
| 324 | #define MFP_PULL_NONE (0x0 << 21) | ||
| 325 | #define MFP_PULL_LOW (0x1 << 21) | ||
| 326 | #define MFP_PULL_HIGH (0x2 << 21) | ||
| 327 | #define MFP_PULL_BOTH (0x3 << 21) | ||
| 328 | #define MFP_PULL_MASK (0x3 << 21) | ||
| 329 | #define MFP_PULL(x) (((x) >> 21) & 0x3) | ||
| 330 | |||
| 331 | #define MFP_CFG_DEFAULT (MFP_AF0 | MFP_DS03X | MFP_LPM_DEFAULT |\ | ||
| 332 | MFP_LPM_EDGE_NONE | MFP_PULL_NONE) | ||
| 333 | |||
| 334 | #define MFP_CFG(pin, af) \ | ||
| 335 | ((MFP_CFG_DEFAULT & ~MFP_AF_MASK) |\ | ||
| 336 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af)) | ||
| 337 | |||
| 338 | #define MFP_CFG_DRV(pin, af, drv) \ | ||
| 339 | ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK)) |\ | ||
| 340 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv)) | ||
| 341 | |||
| 342 | #define MFP_CFG_LPM(pin, af, lpm) \ | ||
| 343 | ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_LPM_STATE_MASK)) |\ | ||
| 344 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_LPM_##lpm)) | ||
| 345 | |||
| 346 | #define MFP_CFG_X(pin, af, drv, lpm) \ | ||
| 347 | ((MFP_CFG_DEFAULT & ~(MFP_AF_MASK | MFP_DS_MASK | MFP_LPM_STATE_MASK)) |\ | ||
| 348 | (MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_##drv | MFP_LPM_##lpm)) | ||
| 349 | |||
| 350 | #if defined(CONFIG_PXA3xx) || defined(CONFIG_ARCH_MMP) | ||
| 351 | /* | ||
| 352 | * each MFP pin will have a MFPR register, since the offset of the | ||
| 353 | * register varies between processors, the processor specific code | ||
| 354 | * should initialize the pin offsets by mfp_init() | ||
| 355 | * | ||
| 356 | * mfp_init_base() - accepts a virtual base for all MFPR registers and | ||
| 357 | * initialize the MFP table to a default state | ||
| 358 | * | ||
| 359 | * mfp_init_addr() - accepts a table of "mfp_addr_map" structure, which | ||
| 360 | * represents a range of MFP pins from "start" to "end", with the offset | ||
| 361 | * begining at "offset", to define a single pin, let "end" = -1. | ||
| 362 | * | ||
| 363 | * use | ||
| 364 | * | ||
| 365 | * MFP_ADDR_X() to define a range of pins | ||
| 366 | * MFP_ADDR() to define a single pin | ||
| 367 | * MFP_ADDR_END to signal the end of pin offset definitions | ||
| 368 | */ | ||
| 369 | struct mfp_addr_map { | ||
| 370 | unsigned int start; | ||
| 371 | unsigned int end; | ||
| 372 | unsigned long offset; | ||
| 373 | }; | ||
| 374 | |||
| 375 | #define MFP_ADDR_X(start, end, offset) \ | ||
| 376 | { MFP_PIN_##start, MFP_PIN_##end, offset } | ||
| 377 | |||
| 378 | #define MFP_ADDR(pin, offset) \ | ||
| 379 | { MFP_PIN_##pin, -1, offset } | ||
| 380 | |||
| 381 | #define MFP_ADDR_END { MFP_PIN_INVALID, 0 } | ||
| 382 | |||
| 383 | void __init mfp_init_base(unsigned long mfpr_base); | ||
| 384 | void __init mfp_init_addr(struct mfp_addr_map *map); | ||
| 385 | |||
| 386 | /* | ||
| 387 | * mfp_{read, write}() - for direct read/write access to the MFPR register | ||
| 388 | * mfp_config() - for configuring a group of MFPR registers | ||
| 389 | * mfp_config_lpm() - configuring all low power MFPR registers for suspend | ||
| 390 | * mfp_config_run() - configuring all run time MFPR registers after resume | ||
| 391 | */ | ||
| 392 | unsigned long mfp_read(int mfp); | ||
| 393 | void mfp_write(int mfp, unsigned long mfpr_val); | ||
| 394 | void mfp_config(unsigned long *mfp_cfgs, int num); | ||
| 395 | void mfp_config_run(void); | ||
| 396 | void mfp_config_lpm(void); | ||
| 397 | #endif /* CONFIG_PXA3xx || CONFIG_ARCH_MMP */ | ||
| 398 | |||
| 399 | #endif /* __ASM_PLAT_MFP_H */ | ||
diff --git a/arch/arm/plat-pxa/mfp.c b/arch/arm/plat-pxa/mfp.c new file mode 100644 index 000000000000..e716c622a17c --- /dev/null +++ b/arch/arm/plat-pxa/mfp.c | |||
| @@ -0,0 +1,278 @@ | |||
| 1 | /* | ||
| 2 | * linux/arch/arm/plat-pxa/mfp.c | ||
| 3 | * | ||
| 4 | * Multi-Function Pin Support | ||
| 5 | * | ||
| 6 | * Copyright (C) 2007 Marvell Internation Ltd. | ||
| 7 | * | ||
| 8 | * 2007-08-21: eric miao <eric.miao@marvell.com> | ||
| 9 | * initial version | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License version 2 as | ||
| 13 | * published by the Free Software Foundation. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #include <linux/module.h> | ||
| 17 | #include <linux/kernel.h> | ||
| 18 | #include <linux/init.h> | ||
| 19 | #include <linux/io.h> | ||
| 20 | #include <linux/sysdev.h> | ||
| 21 | |||
| 22 | #include <plat/mfp.h> | ||
| 23 | |||
| 24 | #define MFPR_SIZE (PAGE_SIZE) | ||
| 25 | |||
| 26 | /* MFPR register bit definitions */ | ||
| 27 | #define MFPR_PULL_SEL (0x1 << 15) | ||
| 28 | #define MFPR_PULLUP_EN (0x1 << 14) | ||
| 29 | #define MFPR_PULLDOWN_EN (0x1 << 13) | ||
| 30 | #define MFPR_SLEEP_SEL (0x1 << 9) | ||
| 31 | #define MFPR_SLEEP_OE_N (0x1 << 7) | ||
| 32 | #define MFPR_EDGE_CLEAR (0x1 << 6) | ||
| 33 | #define MFPR_EDGE_FALL_EN (0x1 << 5) | ||
| 34 | #define MFPR_EDGE_RISE_EN (0x1 << 4) | ||
| 35 | |||
| 36 | #define MFPR_SLEEP_DATA(x) ((x) << 8) | ||
| 37 | #define MFPR_DRIVE(x) (((x) & 0x7) << 10) | ||
| 38 | #define MFPR_AF_SEL(x) (((x) & 0x7) << 0) | ||
| 39 | |||
| 40 | #define MFPR_EDGE_NONE (0) | ||
| 41 | #define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN) | ||
| 42 | #define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN) | ||
| 43 | #define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL) | ||
| 44 | |||
| 45 | /* | ||
| 46 | * Table that determines the low power modes outputs, with actual settings | ||
| 47 | * used in parentheses for don't-care values. Except for the float output, | ||
| 48 | * the configured driven and pulled levels match, so if there is a need for | ||
| 49 | * non-LPM pulled output, the same configuration could probably be used. | ||
| 50 | * | ||
| 51 | * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel | ||
| 52 | * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) | ||
| 53 | * | ||
| 54 | * Input 0 X(0) X(0) X(0) 0 | ||
| 55 | * Drive 0 0 0 0 X(1) 0 | ||
| 56 | * Drive 1 0 1 X(1) 0 0 | ||
| 57 | * Pull hi (1) 1 X(1) 1 0 0 | ||
| 58 | * Pull lo (0) 1 X(0) 0 1 0 | ||
| 59 | * Z (float) 1 X(0) 0 0 0 | ||
| 60 | */ | ||
| 61 | #define MFPR_LPM_INPUT (0) | ||
| 62 | #define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN) | ||
| 63 | #define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN) | ||
| 64 | #define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N) | ||
| 65 | #define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N) | ||
| 66 | #define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N) | ||
| 67 | #define MFPR_LPM_MASK (0xe080) | ||
| 68 | |||
| 69 | /* | ||
| 70 | * The pullup and pulldown state of the MFP pin at run mode is by default | ||
| 71 | * determined by the selected alternate function. In case that some buggy | ||
| 72 | * devices need to override this default behavior, the definitions below | ||
| 73 | * indicates the setting of corresponding MFPR bits | ||
| 74 | * | ||
| 75 | * Definition pull_sel pullup_en pulldown_en | ||
| 76 | * MFPR_PULL_NONE 0 0 0 | ||
| 77 | * MFPR_PULL_LOW 1 0 1 | ||
| 78 | * MFPR_PULL_HIGH 1 1 0 | ||
| 79 | * MFPR_PULL_BOTH 1 1 1 | ||
| 80 | */ | ||
| 81 | #define MFPR_PULL_NONE (0) | ||
| 82 | #define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN) | ||
| 83 | #define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN) | ||
| 84 | #define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN) | ||
| 85 | |||
| 86 | /* mfp_spin_lock is used to ensure that MFP register configuration | ||
| 87 | * (most likely a read-modify-write operation) is atomic, and that | ||
| 88 | * mfp_table[] is consistent | ||
| 89 | */ | ||
| 90 | static DEFINE_SPINLOCK(mfp_spin_lock); | ||
| 91 | |||
| 92 | static void __iomem *mfpr_mmio_base; | ||
| 93 | |||
| 94 | struct mfp_pin { | ||
| 95 | unsigned long config; /* -1 for not configured */ | ||
| 96 | unsigned long mfpr_off; /* MFPRxx Register offset */ | ||
| 97 | unsigned long mfpr_run; /* Run-Mode Register Value */ | ||
| 98 | unsigned long mfpr_lpm; /* Low Power Mode Register Value */ | ||
| 99 | }; | ||
| 100 | |||
| 101 | static struct mfp_pin mfp_table[MFP_PIN_MAX]; | ||
| 102 | |||
| 103 | /* mapping of MFP_LPM_* definitions to MFPR_LPM_* register bits */ | ||
| 104 | static const unsigned long mfpr_lpm[] = { | ||
| 105 | MFPR_LPM_INPUT, | ||
| 106 | MFPR_LPM_DRIVE_LOW, | ||
| 107 | MFPR_LPM_DRIVE_HIGH, | ||
| 108 | MFPR_LPM_PULL_LOW, | ||
| 109 | MFPR_LPM_PULL_HIGH, | ||
| 110 | MFPR_LPM_FLOAT, | ||
| 111 | }; | ||
| 112 | |||
| 113 | /* mapping of MFP_PULL_* definitions to MFPR_PULL_* register bits */ | ||
| 114 | static const unsigned long mfpr_pull[] = { | ||
| 115 | MFPR_PULL_NONE, | ||
| 116 | MFPR_PULL_LOW, | ||
| 117 | MFPR_PULL_HIGH, | ||
| 118 | MFPR_PULL_BOTH, | ||
| 119 | }; | ||
| 120 | |||
| 121 | /* mapping of MFP_LPM_EDGE_* definitions to MFPR_EDGE_* register bits */ | ||
| 122 | static const unsigned long mfpr_edge[] = { | ||
| 123 | MFPR_EDGE_NONE, | ||
| 124 | MFPR_EDGE_RISE, | ||
| 125 | MFPR_EDGE_FALL, | ||
| 126 | MFPR_EDGE_BOTH, | ||
| 127 | }; | ||
| 128 | |||
| 129 | #define mfpr_readl(off) \ | ||
| 130 | __raw_readl(mfpr_mmio_base + (off)) | ||
| 131 | |||
| 132 | #define mfpr_writel(off, val) \ | ||
| 133 | __raw_writel(val, mfpr_mmio_base + (off)) | ||
| 134 | |||
| 135 | #define mfp_configured(p) ((p)->config != -1) | ||
| 136 | |||
| 137 | /* | ||
| 138 | * perform a read-back of any MFPR register to make sure the | ||
| 139 | * previous writings are finished | ||
| 140 | */ | ||
| 141 | #define mfpr_sync() (void)__raw_readl(mfpr_mmio_base + 0) | ||
| 142 | |||
| 143 | static inline void __mfp_config_run(struct mfp_pin *p) | ||
| 144 | { | ||
| 145 | if (mfp_configured(p)) | ||
| 146 | mfpr_writel(p->mfpr_off, p->mfpr_run); | ||
| 147 | } | ||
| 148 | |||
| 149 | static inline void __mfp_config_lpm(struct mfp_pin *p) | ||
| 150 | { | ||
| 151 | if (mfp_configured(p)) { | ||
| 152 | unsigned long mfpr_clr = (p->mfpr_run & ~MFPR_EDGE_BOTH) | MFPR_EDGE_CLEAR; | ||
| 153 | if (mfpr_clr != p->mfpr_run) | ||
| 154 | mfpr_writel(p->mfpr_off, mfpr_clr); | ||
| 155 | if (p->mfpr_lpm != mfpr_clr) | ||
| 156 | mfpr_writel(p->mfpr_off, p->mfpr_lpm); | ||
| 157 | } | ||
| 158 | } | ||
| 159 | |||
| 160 | void mfp_config(unsigned long *mfp_cfgs, int num) | ||
| 161 | { | ||
| 162 | unsigned long flags; | ||
| 163 | int i; | ||
| 164 | |||
| 165 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
| 166 | |||
| 167 | for (i = 0; i < num; i++, mfp_cfgs++) { | ||
| 168 | unsigned long tmp, c = *mfp_cfgs; | ||
| 169 | struct mfp_pin *p; | ||
| 170 | int pin, af, drv, lpm, edge, pull; | ||
| 171 | |||
| 172 | pin = MFP_PIN(c); | ||
| 173 | BUG_ON(pin >= MFP_PIN_MAX); | ||
| 174 | p = &mfp_table[pin]; | ||
| 175 | |||
| 176 | af = MFP_AF(c); | ||
| 177 | drv = MFP_DS(c); | ||
| 178 | lpm = MFP_LPM_STATE(c); | ||
| 179 | edge = MFP_LPM_EDGE(c); | ||
| 180 | pull = MFP_PULL(c); | ||
| 181 | |||
| 182 | /* run-mode pull settings will conflict with MFPR bits of | ||
| 183 | * low power mode state, calculate mfpr_run and mfpr_lpm | ||
| 184 | * individually if pull != MFP_PULL_NONE | ||
| 185 | */ | ||
| 186 | tmp = MFPR_AF_SEL(af) | MFPR_DRIVE(drv); | ||
| 187 | |||
| 188 | if (likely(pull == MFP_PULL_NONE)) { | ||
| 189 | p->mfpr_run = tmp | mfpr_lpm[lpm] | mfpr_edge[edge]; | ||
| 190 | p->mfpr_lpm = p->mfpr_run; | ||
| 191 | } else { | ||
| 192 | p->mfpr_lpm = tmp | mfpr_lpm[lpm] | mfpr_edge[edge]; | ||
| 193 | p->mfpr_run = tmp | mfpr_pull[pull]; | ||
| 194 | } | ||
| 195 | |||
| 196 | p->config = c; __mfp_config_run(p); | ||
| 197 | } | ||
| 198 | |||
| 199 | mfpr_sync(); | ||
| 200 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
| 201 | } | ||
| 202 | |||
| 203 | unsigned long mfp_read(int mfp) | ||
| 204 | { | ||
| 205 | unsigned long val, flags; | ||
| 206 | |||
| 207 | BUG_ON(mfp >= MFP_PIN_MAX); | ||
| 208 | |||
| 209 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
| 210 | val = mfpr_readl(mfp_table[mfp].mfpr_off); | ||
| 211 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
| 212 | |||
| 213 | return val; | ||
| 214 | } | ||
| 215 | |||
| 216 | void mfp_write(int mfp, unsigned long val) | ||
| 217 | { | ||
| 218 | unsigned long flags; | ||
| 219 | |||
| 220 | BUG_ON(mfp >= MFP_PIN_MAX); | ||
| 221 | |||
| 222 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
| 223 | mfpr_writel(mfp_table[mfp].mfpr_off, val); | ||
| 224 | mfpr_sync(); | ||
| 225 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
| 226 | } | ||
| 227 | |||
| 228 | void __init mfp_init_base(unsigned long mfpr_base) | ||
| 229 | { | ||
| 230 | int i; | ||
| 231 | |||
| 232 | /* initialize the table with default - unconfigured */ | ||
| 233 | for (i = 0; i < ARRAY_SIZE(mfp_table); i++) | ||
| 234 | mfp_table[i].config = -1; | ||
| 235 | |||
| 236 | mfpr_mmio_base = (void __iomem *)mfpr_base; | ||
| 237 | } | ||
| 238 | |||
| 239 | void __init mfp_init_addr(struct mfp_addr_map *map) | ||
| 240 | { | ||
| 241 | struct mfp_addr_map *p; | ||
| 242 | unsigned long offset, flags; | ||
| 243 | int i; | ||
| 244 | |||
| 245 | spin_lock_irqsave(&mfp_spin_lock, flags); | ||
| 246 | |||
| 247 | for (p = map; p->start != MFP_PIN_INVALID; p++) { | ||
| 248 | offset = p->offset; | ||
| 249 | i = p->start; | ||
| 250 | |||
| 251 | do { | ||
| 252 | mfp_table[i].mfpr_off = offset; | ||
| 253 | mfp_table[i].mfpr_run = 0; | ||
| 254 | mfp_table[i].mfpr_lpm = 0; | ||
| 255 | offset += 4; i++; | ||
| 256 | } while ((i <= p->end) && (p->end != -1)); | ||
| 257 | } | ||
| 258 | |||
| 259 | spin_unlock_irqrestore(&mfp_spin_lock, flags); | ||
| 260 | } | ||
| 261 | |||
| 262 | void mfp_config_lpm(void) | ||
| 263 | { | ||
| 264 | struct mfp_pin *p = &mfp_table[0]; | ||
| 265 | int pin; | ||
| 266 | |||
| 267 | for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++) | ||
| 268 | __mfp_config_lpm(p); | ||
| 269 | } | ||
| 270 | |||
| 271 | void mfp_config_run(void) | ||
| 272 | { | ||
| 273 | struct mfp_pin *p = &mfp_table[0]; | ||
| 274 | int pin; | ||
| 275 | |||
| 276 | for (pin = 0; pin < ARRAY_SIZE(mfp_table); pin++, p++) | ||
| 277 | __mfp_config_run(p); | ||
| 278 | } | ||
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile index 39195f972d5e..8d7815d25a51 100644 --- a/arch/arm/plat-s3c/Makefile +++ b/arch/arm/plat-s3c/Makefile | |||
| @@ -18,6 +18,11 @@ obj-y += pwm-clock.o | |||
| 18 | obj-y += gpio.o | 18 | obj-y += gpio.o |
| 19 | obj-y += gpio-config.o | 19 | obj-y += gpio-config.o |
| 20 | 20 | ||
| 21 | # PM support | ||
| 22 | |||
| 23 | obj-$(CONFIG_PM) += pm.o | ||
| 24 | obj-$(CONFIG_S3C2410_PM_CHECK) += pm-check.o | ||
| 25 | |||
| 21 | # devices | 26 | # devices |
| 22 | 27 | ||
| 23 | obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o | 28 | obj-$(CONFIG_S3C_DEV_HSMMC) += dev-hsmmc.o |
diff --git a/arch/arm/plat-s3c/include/plat/pm.h b/arch/arm/plat-s3c/include/plat/pm.h new file mode 100644 index 000000000000..3779775133a9 --- /dev/null +++ b/arch/arm/plat-s3c/include/plat/pm.h | |||
| @@ -0,0 +1,174 @@ | |||
| 1 | /* linux/include/asm-arm/plat-s3c24xx/pm.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2004 Simtec Electronics | ||
| 4 | * http://armlinux.simtec.co.uk/ | ||
| 5 | * Written by Ben Dooks, <ben@simtec.co.uk> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | |||
| 12 | /* s3c_pm_init | ||
| 13 | * | ||
| 14 | * called from board at initialisation time to setup the power | ||
| 15 | * management | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifdef CONFIG_PM | ||
| 19 | |||
| 20 | extern __init int s3c_pm_init(void); | ||
| 21 | |||
| 22 | #else | ||
| 23 | |||
| 24 | static inline int s3c_pm_init(void) | ||
| 25 | { | ||
| 26 | return 0; | ||
| 27 | } | ||
| 28 | #endif | ||
| 29 | |||
| 30 | /* configuration for the IRQ mask over sleep */ | ||
| 31 | extern unsigned long s3c_irqwake_intmask; | ||
| 32 | extern unsigned long s3c_irqwake_eintmask; | ||
| 33 | |||
| 34 | /* IRQ masks for IRQs allowed to go to sleep (see irq.c) */ | ||
| 35 | extern unsigned long s3c_irqwake_intallow; | ||
| 36 | extern unsigned long s3c_irqwake_eintallow; | ||
| 37 | |||
| 38 | /* per-cpu sleep functions */ | ||
| 39 | |||
| 40 | extern void (*pm_cpu_prep)(void); | ||
| 41 | extern void (*pm_cpu_sleep)(void); | ||
| 42 | |||
| 43 | /* Flags for PM Control */ | ||
| 44 | |||
| 45 | extern unsigned long s3c_pm_flags; | ||
| 46 | |||
| 47 | /* from sleep.S */ | ||
| 48 | |||
| 49 | extern int s3c_cpu_save(unsigned long *saveblk); | ||
| 50 | extern void s3c_cpu_resume(void); | ||
| 51 | |||
| 52 | extern void s3c2410_cpu_suspend(void); | ||
| 53 | |||
| 54 | extern unsigned long s3c_sleep_save_phys; | ||
| 55 | |||
| 56 | /* sleep save info */ | ||
| 57 | |||
| 58 | /** | ||
| 59 | * struct sleep_save - save information for shared peripherals. | ||
| 60 | * @reg: Pointer to the register to save. | ||
| 61 | * @val: Holder for the value saved from reg. | ||
| 62 | * | ||
| 63 | * This describes a list of registers which is used by the pm core and | ||
| 64 | * other subsystem to save and restore register values over suspend. | ||
| 65 | */ | ||
| 66 | struct sleep_save { | ||
| 67 | void __iomem *reg; | ||
| 68 | unsigned long val; | ||
| 69 | }; | ||
| 70 | |||
| 71 | #define SAVE_ITEM(x) \ | ||
| 72 | { .reg = (x) } | ||
| 73 | |||
| 74 | /** | ||
| 75 | * struct pm_uart_save - save block for core UART | ||
| 76 | * @ulcon: Save value for S3C2410_ULCON | ||
| 77 | * @ucon: Save value for S3C2410_UCON | ||
| 78 | * @ufcon: Save value for S3C2410_UFCON | ||
| 79 | * @umcon: Save value for S3C2410_UMCON | ||
| 80 | * @ubrdiv: Save value for S3C2410_UBRDIV | ||
| 81 | * | ||
| 82 | * Save block for UART registers to be held over sleep and restored if they | ||
| 83 | * are needed (say by debug). | ||
| 84 | */ | ||
| 85 | struct pm_uart_save { | ||
| 86 | u32 ulcon; | ||
| 87 | u32 ucon; | ||
| 88 | u32 ufcon; | ||
| 89 | u32 umcon; | ||
| 90 | u32 ubrdiv; | ||
| 91 | }; | ||
| 92 | |||
| 93 | /* helper functions to save/restore lists of registers. */ | ||
| 94 | |||
| 95 | extern void s3c_pm_do_save(struct sleep_save *ptr, int count); | ||
| 96 | extern void s3c_pm_do_restore(struct sleep_save *ptr, int count); | ||
| 97 | extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count); | ||
| 98 | |||
| 99 | #ifdef CONFIG_PM | ||
| 100 | extern int s3c_irqext_wake(unsigned int irqno, unsigned int state); | ||
| 101 | extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state); | ||
| 102 | extern int s3c24xx_irq_resume(struct sys_device *dev); | ||
| 103 | #else | ||
| 104 | #define s3c_irqext_wake NULL | ||
| 105 | #define s3c24xx_irq_suspend NULL | ||
| 106 | #define s3c24xx_irq_resume NULL | ||
| 107 | #endif | ||
| 108 | |||
| 109 | /* PM debug functions */ | ||
| 110 | |||
| 111 | #ifdef CONFIG_S3C2410_PM_DEBUG | ||
| 112 | /** | ||
| 113 | * s3c_pm_dbg() - low level debug function for use in suspend/resume. | ||
| 114 | * @msg: The message to print. | ||
| 115 | * | ||
| 116 | * This function is used mainly to debug the resume process before the system | ||
| 117 | * can rely on printk/console output. It uses the low-level debugging output | ||
| 118 | * routine printascii() to do its work. | ||
| 119 | */ | ||
| 120 | extern void s3c_pm_dbg(const char *msg, ...); | ||
| 121 | |||
| 122 | #define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt) | ||
| 123 | #else | ||
| 124 | #define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt) | ||
| 125 | #endif | ||
| 126 | |||
| 127 | /* suspend memory checking */ | ||
| 128 | |||
| 129 | #ifdef CONFIG_S3C2410_PM_CHECK | ||
| 130 | extern void s3c_pm_check_prepare(void); | ||
| 131 | extern void s3c_pm_check_restore(void); | ||
| 132 | extern void s3c_pm_check_cleanup(void); | ||
| 133 | extern void s3c_pm_check_store(void); | ||
| 134 | #else | ||
| 135 | #define s3c_pm_check_prepare() do { } while(0) | ||
| 136 | #define s3c_pm_check_restore() do { } while(0) | ||
| 137 | #define s3c_pm_check_cleanup() do { } while(0) | ||
| 138 | #define s3c_pm_check_store() do { } while(0) | ||
| 139 | #endif | ||
| 140 | |||
| 141 | /** | ||
| 142 | * s3c_pm_configure_extint() - ensure pins are correctly set for IRQ | ||
| 143 | * | ||
| 144 | * Setup all the necessary GPIO pins for waking the system on external | ||
| 145 | * interrupt. | ||
| 146 | */ | ||
| 147 | extern void s3c_pm_configure_extint(void); | ||
| 148 | |||
| 149 | /** | ||
| 150 | * s3c_pm_restore_gpios() - restore the state of the gpios after sleep. | ||
| 151 | * | ||
| 152 | * Restore the state of the GPIO pins after sleep, which may involve ensuring | ||
| 153 | * that we do not glitch the state of the pins from that the bootloader's | ||
| 154 | * resume code has done. | ||
| 155 | */ | ||
| 156 | extern void s3c_pm_restore_gpios(void); | ||
| 157 | |||
| 158 | /** | ||
| 159 | * s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep. | ||
| 160 | * | ||
| 161 | * Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios(). | ||
| 162 | */ | ||
| 163 | extern void s3c_pm_save_gpios(void); | ||
| 164 | |||
| 165 | /** | ||
| 166 | * s3c_pm_cb_flushcache - callback for assembly code | ||
| 167 | * | ||
| 168 | * Callback to issue flush_cache_all() as this call is | ||
| 169 | * not a directly callable object. | ||
| 170 | */ | ||
| 171 | extern void s3c_pm_cb_flushcache(void); | ||
| 172 | |||
| 173 | extern void s3c_pm_save_core(void); | ||
| 174 | extern void s3c_pm_restore_core(void); | ||
diff --git a/arch/arm/plat-s3c/include/plat/uncompress.h b/arch/arm/plat-s3c/include/plat/uncompress.h index 6061de87f225..dc66a477f62e 100644 --- a/arch/arm/plat-s3c/include/plat/uncompress.h +++ b/arch/arm/plat-s3c/include/plat/uncompress.h | |||
| @@ -90,7 +90,10 @@ static inline void flush(void) | |||
| 90 | { | 90 | { |
| 91 | } | 91 | } |
| 92 | 92 | ||
| 93 | #define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0) | 93 | #define __raw_writel(d, ad) \ |
| 94 | do { \ | ||
| 95 | *((volatile unsigned int __force *)(ad)) = (d); \ | ||
| 96 | } while (0) | ||
| 94 | 97 | ||
| 95 | /* CONFIG_S3C_BOOT_WATCHDOG | 98 | /* CONFIG_S3C_BOOT_WATCHDOG |
| 96 | * | 99 | * |
diff --git a/arch/arm/plat-s3c/pm-check.c b/arch/arm/plat-s3c/pm-check.c new file mode 100644 index 000000000000..39f2555564da --- /dev/null +++ b/arch/arm/plat-s3c/pm-check.c | |||
| @@ -0,0 +1,242 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c/pm-check.c | ||
| 2 | * originally in linux/arch/arm/plat-s3c24xx/pm.c | ||
| 3 | * | ||
| 4 | * Copyright (c) 2004,2006,2008 Simtec Electronics | ||
| 5 | * http://armlinux.simtec.co.uk | ||
| 6 | * Ben Dooks <ben@simtec.co.uk> | ||
| 7 | * | ||
| 8 | * S3C Power Mangament - suspend/resume memory corruptiuon check. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/kernel.h> | ||
| 16 | #include <linux/suspend.h> | ||
| 17 | #include <linux/init.h> | ||
| 18 | #include <linux/crc32.h> | ||
| 19 | #include <linux/ioport.h> | ||
| 20 | |||
| 21 | #include <plat/pm.h> | ||
| 22 | |||
| 23 | #if CONFIG_S3C2410_PM_CHECK_CHUNKSIZE < 1 | ||
| 24 | #error CONFIG_S3C2410_PM_CHECK_CHUNKSIZE must be a positive non-zero value | ||
| 25 | #endif | ||
| 26 | |||
| 27 | /* suspend checking code... | ||
| 28 | * | ||
| 29 | * this next area does a set of crc checks over all the installed | ||
| 30 | * memory, so the system can verify if the resume was ok. | ||
| 31 | * | ||
| 32 | * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, | ||
| 33 | * increasing it will mean that the area corrupted will be less easy to spot, | ||
| 34 | * and reducing the size will cause the CRC save area to grow | ||
| 35 | */ | ||
| 36 | |||
| 37 | #define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024) | ||
| 38 | |||
| 39 | static u32 crc_size; /* size needed for the crc block */ | ||
| 40 | static u32 *crcs; /* allocated over suspend/resume */ | ||
| 41 | |||
| 42 | typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg); | ||
| 43 | |||
| 44 | /* s3c_pm_run_res | ||
| 45 | * | ||
| 46 | * go through the given resource list, and look for system ram | ||
| 47 | */ | ||
| 48 | |||
| 49 | static void s3c_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg) | ||
| 50 | { | ||
| 51 | while (ptr != NULL) { | ||
| 52 | if (ptr->child != NULL) | ||
| 53 | s3c_pm_run_res(ptr->child, fn, arg); | ||
| 54 | |||
| 55 | if ((ptr->flags & IORESOURCE_MEM) && | ||
| 56 | strcmp(ptr->name, "System RAM") == 0) { | ||
| 57 | S3C_PMDBG("Found system RAM at %08lx..%08lx\n", | ||
| 58 | (unsigned long)ptr->start, | ||
| 59 | (unsigned long)ptr->end); | ||
| 60 | arg = (fn)(ptr, arg); | ||
| 61 | } | ||
| 62 | |||
| 63 | ptr = ptr->sibling; | ||
| 64 | } | ||
| 65 | } | ||
| 66 | |||
| 67 | static void s3c_pm_run_sysram(run_fn_t fn, u32 *arg) | ||
| 68 | { | ||
| 69 | s3c_pm_run_res(&iomem_resource, fn, arg); | ||
| 70 | } | ||
| 71 | |||
| 72 | static u32 *s3c_pm_countram(struct resource *res, u32 *val) | ||
| 73 | { | ||
| 74 | u32 size = (u32)(res->end - res->start)+1; | ||
| 75 | |||
| 76 | size += CHECK_CHUNKSIZE-1; | ||
| 77 | size /= CHECK_CHUNKSIZE; | ||
| 78 | |||
| 79 | S3C_PMDBG("Area %08lx..%08lx, %d blocks\n", | ||
| 80 | (unsigned long)res->start, (unsigned long)res->end, size); | ||
| 81 | |||
| 82 | *val += size * sizeof(u32); | ||
| 83 | return val; | ||
| 84 | } | ||
| 85 | |||
| 86 | /* s3c_pm_prepare_check | ||
| 87 | * | ||
| 88 | * prepare the necessary information for creating the CRCs. This | ||
| 89 | * must be done before the final save, as it will require memory | ||
| 90 | * allocating, and thus touching bits of the kernel we do not | ||
| 91 | * know about. | ||
| 92 | */ | ||
| 93 | |||
| 94 | void s3c_pm_check_prepare(void) | ||
| 95 | { | ||
| 96 | crc_size = 0; | ||
| 97 | |||
| 98 | s3c_pm_run_sysram(s3c_pm_countram, &crc_size); | ||
| 99 | |||
| 100 | S3C_PMDBG("s3c_pm_prepare_check: %u checks needed\n", crc_size); | ||
| 101 | |||
| 102 | crcs = kmalloc(crc_size+4, GFP_KERNEL); | ||
| 103 | if (crcs == NULL) | ||
| 104 | printk(KERN_ERR "Cannot allocated CRC save area\n"); | ||
| 105 | } | ||
| 106 | |||
| 107 | static u32 *s3c_pm_makecheck(struct resource *res, u32 *val) | ||
| 108 | { | ||
| 109 | unsigned long addr, left; | ||
| 110 | |||
| 111 | for (addr = res->start; addr < res->end; | ||
| 112 | addr += CHECK_CHUNKSIZE) { | ||
| 113 | left = res->end - addr; | ||
| 114 | |||
| 115 | if (left > CHECK_CHUNKSIZE) | ||
| 116 | left = CHECK_CHUNKSIZE; | ||
| 117 | |||
| 118 | *val = crc32_le(~0, phys_to_virt(addr), left); | ||
| 119 | val++; | ||
| 120 | } | ||
| 121 | |||
| 122 | return val; | ||
| 123 | } | ||
| 124 | |||
| 125 | /* s3c_pm_check_store | ||
| 126 | * | ||
| 127 | * compute the CRC values for the memory blocks before the final | ||
| 128 | * sleep. | ||
| 129 | */ | ||
| 130 | |||
| 131 | void s3c_pm_check_store(void) | ||
| 132 | { | ||
| 133 | if (crcs != NULL) | ||
| 134 | s3c_pm_run_sysram(s3c_pm_makecheck, crcs); | ||
| 135 | } | ||
| 136 | |||
| 137 | /* in_region | ||
| 138 | * | ||
| 139 | * return TRUE if the area defined by ptr..ptr+size contains the | ||
| 140 | * what..what+whatsz | ||
| 141 | */ | ||
| 142 | |||
| 143 | static inline int in_region(void *ptr, int size, void *what, size_t whatsz) | ||
| 144 | { | ||
| 145 | if ((what+whatsz) < ptr) | ||
| 146 | return 0; | ||
| 147 | |||
| 148 | if (what > (ptr+size)) | ||
| 149 | return 0; | ||
| 150 | |||
| 151 | return 1; | ||
| 152 | } | ||
| 153 | |||
| 154 | /** | ||
| 155 | * s3c_pm_runcheck() - helper to check a resource on restore. | ||
| 156 | * @res: The resource to check | ||
| 157 | * @vak: Pointer to list of CRC32 values to check. | ||
| 158 | * | ||
| 159 | * Called from the s3c_pm_check_restore() via s3c_pm_run_sysram(), this | ||
| 160 | * function runs the given memory resource checking it against the stored | ||
| 161 | * CRC to ensure that memory is restored. The function tries to skip as | ||
| 162 | * many of the areas used during the suspend process. | ||
| 163 | */ | ||
| 164 | static u32 *s3c_pm_runcheck(struct resource *res, u32 *val) | ||
| 165 | { | ||
| 166 | void *save_at = phys_to_virt(s3c_sleep_save_phys); | ||
| 167 | unsigned long addr; | ||
| 168 | unsigned long left; | ||
| 169 | void *stkpage; | ||
| 170 | void *ptr; | ||
| 171 | u32 calc; | ||
| 172 | |||
| 173 | stkpage = (void *)((u32)&calc & ~PAGE_MASK); | ||
| 174 | |||
| 175 | for (addr = res->start; addr < res->end; | ||
| 176 | addr += CHECK_CHUNKSIZE) { | ||
| 177 | left = res->end - addr; | ||
| 178 | |||
| 179 | if (left > CHECK_CHUNKSIZE) | ||
| 180 | left = CHECK_CHUNKSIZE; | ||
| 181 | |||
| 182 | ptr = phys_to_virt(addr); | ||
| 183 | |||
| 184 | if (in_region(ptr, left, stkpage, 4096)) { | ||
| 185 | S3C_PMDBG("skipping %08lx, has stack in\n", addr); | ||
| 186 | goto skip_check; | ||
| 187 | } | ||
| 188 | |||
| 189 | if (in_region(ptr, left, crcs, crc_size)) { | ||
| 190 | S3C_PMDBG("skipping %08lx, has crc block in\n", addr); | ||
| 191 | goto skip_check; | ||
| 192 | } | ||
| 193 | |||
| 194 | if (in_region(ptr, left, save_at, 32*4 )) { | ||
| 195 | S3C_PMDBG("skipping %08lx, has save block in\n", addr); | ||
| 196 | goto skip_check; | ||
| 197 | } | ||
| 198 | |||
| 199 | /* calculate and check the checksum */ | ||
| 200 | |||
| 201 | calc = crc32_le(~0, ptr, left); | ||
| 202 | if (calc != *val) { | ||
| 203 | printk(KERN_ERR "Restore CRC error at " | ||
| 204 | "%08lx (%08x vs %08x)\n", addr, calc, *val); | ||
| 205 | |||
| 206 | S3C_PMDBG("Restore CRC error at %08lx (%08x vs %08x)\n", | ||
| 207 | addr, calc, *val); | ||
| 208 | } | ||
| 209 | |||
| 210 | skip_check: | ||
| 211 | val++; | ||
| 212 | } | ||
| 213 | |||
| 214 | return val; | ||
| 215 | } | ||
| 216 | |||
| 217 | /** | ||
| 218 | * s3c_pm_check_restore() - memory check called on resume | ||
| 219 | * | ||
| 220 | * check the CRCs after the restore event and free the memory used | ||
| 221 | * to hold them | ||
| 222 | */ | ||
| 223 | void s3c_pm_check_restore(void) | ||
| 224 | { | ||
| 225 | if (crcs != NULL) | ||
| 226 | s3c_pm_run_sysram(s3c_pm_runcheck, crcs); | ||
| 227 | } | ||
| 228 | |||
| 229 | /** | ||
| 230 | * s3c_pm_check_cleanup() - free memory resources | ||
| 231 | * | ||
| 232 | * Free the resources that where allocated by the suspend | ||
| 233 | * memory check code. We do this separately from the | ||
| 234 | * s3c_pm_check_restore() function as we cannot call any | ||
| 235 | * functions that might sleep during that resume. | ||
| 236 | */ | ||
| 237 | void s3c_pm_check_cleanup(void) | ||
| 238 | { | ||
| 239 | kfree(crcs); | ||
| 240 | crcs = NULL; | ||
| 241 | } | ||
| 242 | |||
diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c new file mode 100644 index 000000000000..061182ca66e3 --- /dev/null +++ b/arch/arm/plat-s3c/pm.c | |||
| @@ -0,0 +1,363 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c/pm.c | ||
| 2 | * | ||
| 3 | * Copyright 2008 Openmoko, Inc. | ||
| 4 | * Copyright 2004,2006,2008 Simtec Electronics | ||
| 5 | * Ben Dooks <ben@simtec.co.uk> | ||
| 6 | * http://armlinux.simtec.co.uk/ | ||
| 7 | * | ||
| 8 | * S3C common power management (suspend to ram) support. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License version 2 as | ||
| 12 | * published by the Free Software Foundation. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #include <linux/init.h> | ||
| 16 | #include <linux/suspend.h> | ||
| 17 | #include <linux/errno.h> | ||
| 18 | #include <linux/delay.h> | ||
| 19 | #include <linux/serial_core.h> | ||
| 20 | #include <linux/io.h> | ||
| 21 | |||
| 22 | #include <asm/cacheflush.h> | ||
| 23 | #include <mach/hardware.h> | ||
| 24 | |||
| 25 | #include <plat/regs-serial.h> | ||
| 26 | #include <mach/regs-clock.h> | ||
| 27 | #include <mach/regs-gpio.h> | ||
| 28 | #include <mach/regs-mem.h> | ||
| 29 | #include <mach/regs-irq.h> | ||
| 30 | #include <asm/irq.h> | ||
| 31 | |||
| 32 | #include <plat/pm.h> | ||
| 33 | #include <plat/pm-core.h> | ||
| 34 | |||
| 35 | /* for external use */ | ||
| 36 | |||
| 37 | unsigned long s3c_pm_flags; | ||
| 38 | |||
| 39 | /* Debug code: | ||
| 40 | * | ||
| 41 | * This code supports debug output to the low level UARTs for use on | ||
| 42 | * resume before the console layer is available. | ||
| 43 | */ | ||
| 44 | |||
| 45 | #ifdef CONFIG_S3C2410_PM_DEBUG | ||
| 46 | extern void printascii(const char *); | ||
| 47 | |||
| 48 | void s3c_pm_dbg(const char *fmt, ...) | ||
| 49 | { | ||
| 50 | va_list va; | ||
| 51 | char buff[256]; | ||
| 52 | |||
| 53 | va_start(va, fmt); | ||
| 54 | vsprintf(buff, fmt, va); | ||
| 55 | va_end(va); | ||
| 56 | |||
| 57 | printascii(buff); | ||
| 58 | } | ||
| 59 | |||
| 60 | static inline void s3c_pm_debug_init(void) | ||
| 61 | { | ||
| 62 | /* restart uart clocks so we can use them to output */ | ||
| 63 | s3c_pm_debug_init_uart(); | ||
| 64 | } | ||
| 65 | |||
| 66 | #else | ||
| 67 | #define s3c_pm_debug_init() do { } while(0) | ||
| 68 | |||
| 69 | #endif /* CONFIG_S3C2410_PM_DEBUG */ | ||
| 70 | |||
| 71 | /* Save the UART configurations if we are configured for debug. */ | ||
| 72 | |||
| 73 | #ifdef CONFIG_S3C2410_PM_DEBUG | ||
| 74 | |||
| 75 | struct pm_uart_save uart_save[CONFIG_SERIAL_SAMSUNG_UARTS]; | ||
| 76 | |||
| 77 | static void s3c_pm_save_uart(unsigned int uart, struct pm_uart_save *save) | ||
| 78 | { | ||
| 79 | void __iomem *regs = S3C_VA_UARTx(uart); | ||
| 80 | |||
| 81 | save->ulcon = __raw_readl(regs + S3C2410_ULCON); | ||
| 82 | save->ucon = __raw_readl(regs + S3C2410_UCON); | ||
| 83 | save->ufcon = __raw_readl(regs + S3C2410_UFCON); | ||
| 84 | save->umcon = __raw_readl(regs + S3C2410_UMCON); | ||
| 85 | save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); | ||
| 86 | } | ||
| 87 | |||
| 88 | static void s3c_pm_save_uarts(void) | ||
| 89 | { | ||
| 90 | struct pm_uart_save *save = uart_save; | ||
| 91 | unsigned int uart; | ||
| 92 | |||
| 93 | for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++) | ||
| 94 | s3c_pm_save_uart(uart, save); | ||
| 95 | } | ||
| 96 | |||
| 97 | static void s3c_pm_restore_uart(unsigned int uart, struct pm_uart_save *save) | ||
| 98 | { | ||
| 99 | void __iomem *regs = S3C_VA_UARTx(uart); | ||
| 100 | |||
| 101 | __raw_writel(save->ulcon, regs + S3C2410_ULCON); | ||
| 102 | __raw_writel(save->ucon, regs + S3C2410_UCON); | ||
| 103 | __raw_writel(save->ufcon, regs + S3C2410_UFCON); | ||
| 104 | __raw_writel(save->umcon, regs + S3C2410_UMCON); | ||
| 105 | __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV); | ||
| 106 | } | ||
| 107 | |||
| 108 | static void s3c_pm_restore_uarts(void) | ||
| 109 | { | ||
| 110 | struct pm_uart_save *save = uart_save; | ||
| 111 | unsigned int uart; | ||
| 112 | |||
| 113 | for (uart = 0; uart < CONFIG_SERIAL_SAMSUNG_UARTS; uart++, save++) | ||
| 114 | s3c_pm_restore_uart(uart, save); | ||
| 115 | } | ||
| 116 | #else | ||
| 117 | static void s3c_pm_save_uarts(void) { } | ||
| 118 | static void s3c_pm_restore_uarts(void) { } | ||
| 119 | #endif | ||
| 120 | |||
| 121 | /* The IRQ ext-int code goes here, it is too small to currently bother | ||
| 122 | * with its own file. */ | ||
| 123 | |||
| 124 | unsigned long s3c_irqwake_intmask = 0xffffffffL; | ||
| 125 | unsigned long s3c_irqwake_eintmask = 0xffffffffL; | ||
| 126 | |||
| 127 | int s3c_irqext_wake(unsigned int irqno, unsigned int state) | ||
| 128 | { | ||
| 129 | unsigned long bit = 1L << IRQ_EINT_BIT(irqno); | ||
| 130 | |||
| 131 | if (!(s3c_irqwake_eintallow & bit)) | ||
| 132 | return -ENOENT; | ||
| 133 | |||
| 134 | printk(KERN_INFO "wake %s for irq %d\n", | ||
| 135 | state ? "enabled" : "disabled", irqno); | ||
| 136 | |||
| 137 | if (!state) | ||
| 138 | s3c_irqwake_eintmask |= bit; | ||
| 139 | else | ||
| 140 | s3c_irqwake_eintmask &= ~bit; | ||
| 141 | |||
| 142 | return 0; | ||
| 143 | } | ||
| 144 | |||
| 145 | /* helper functions to save and restore register state */ | ||
| 146 | |||
| 147 | /** | ||
| 148 | * s3c_pm_do_save() - save a set of registers for restoration on resume. | ||
| 149 | * @ptr: Pointer to an array of registers. | ||
| 150 | * @count: Size of the ptr array. | ||
| 151 | * | ||
| 152 | * Run through the list of registers given, saving their contents in the | ||
| 153 | * array for later restoration when we wakeup. | ||
| 154 | */ | ||
| 155 | void s3c_pm_do_save(struct sleep_save *ptr, int count) | ||
| 156 | { | ||
| 157 | for (; count > 0; count--, ptr++) { | ||
| 158 | ptr->val = __raw_readl(ptr->reg); | ||
| 159 | S3C_PMDBG("saved %p value %08lx\n", ptr->reg, ptr->val); | ||
| 160 | } | ||
| 161 | } | ||
| 162 | |||
| 163 | /** | ||
| 164 | * s3c_pm_do_restore() - restore register values from the save list. | ||
| 165 | * @ptr: Pointer to an array of registers. | ||
| 166 | * @count: Size of the ptr array. | ||
| 167 | * | ||
| 168 | * Restore the register values saved from s3c_pm_do_save(). | ||
| 169 | * | ||
| 170 | * Note, we do not use S3C_PMDBG() in here, as the system may not have | ||
| 171 | * restore the UARTs state yet | ||
| 172 | */ | ||
| 173 | |||
| 174 | void s3c_pm_do_restore(struct sleep_save *ptr, int count) | ||
| 175 | { | ||
| 176 | for (; count > 0; count--, ptr++) { | ||
| 177 | printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", | ||
| 178 | ptr->reg, ptr->val, __raw_readl(ptr->reg)); | ||
| 179 | |||
| 180 | __raw_writel(ptr->val, ptr->reg); | ||
| 181 | } | ||
| 182 | } | ||
| 183 | |||
| 184 | /** | ||
| 185 | * s3c_pm_do_restore_core() - early restore register values from save list. | ||
| 186 | * | ||
| 187 | * This is similar to s3c_pm_do_restore() except we try and minimise the | ||
| 188 | * side effects of the function in case registers that hardware might need | ||
| 189 | * to work has been restored. | ||
| 190 | * | ||
| 191 | * WARNING: Do not put any debug in here that may effect memory or use | ||
| 192 | * peripherals, as things may be changing! | ||
| 193 | */ | ||
| 194 | |||
| 195 | void s3c_pm_do_restore_core(struct sleep_save *ptr, int count) | ||
| 196 | { | ||
| 197 | for (; count > 0; count--, ptr++) | ||
| 198 | __raw_writel(ptr->val, ptr->reg); | ||
| 199 | } | ||
| 200 | |||
| 201 | /* s3c2410_pm_show_resume_irqs | ||
| 202 | * | ||
| 203 | * print any IRQs asserted at resume time (ie, we woke from) | ||
| 204 | */ | ||
| 205 | static void s3c_pm_show_resume_irqs(int start, unsigned long which, | ||
| 206 | unsigned long mask) | ||
| 207 | { | ||
| 208 | int i; | ||
| 209 | |||
| 210 | which &= ~mask; | ||
| 211 | |||
| 212 | for (i = 0; i <= 31; i++) { | ||
| 213 | if (which & (1L<<i)) { | ||
| 214 | S3C_PMDBG("IRQ %d asserted at resume\n", start+i); | ||
| 215 | } | ||
| 216 | } | ||
| 217 | } | ||
| 218 | |||
| 219 | |||
| 220 | void (*pm_cpu_prep)(void); | ||
| 221 | void (*pm_cpu_sleep)(void); | ||
| 222 | |||
| 223 | #define any_allowed(mask, allow) (((mask) & (allow)) != (allow)) | ||
| 224 | |||
| 225 | /* s3c_pm_enter | ||
| 226 | * | ||
| 227 | * central control for sleep/resume process | ||
| 228 | */ | ||
| 229 | |||
| 230 | static int s3c_pm_enter(suspend_state_t state) | ||
| 231 | { | ||
| 232 | static unsigned long regs_save[16]; | ||
| 233 | |||
| 234 | /* ensure the debug is initialised (if enabled) */ | ||
| 235 | |||
| 236 | s3c_pm_debug_init(); | ||
| 237 | |||
| 238 | S3C_PMDBG("%s(%d)\n", __func__, state); | ||
| 239 | |||
| 240 | if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) { | ||
| 241 | printk(KERN_ERR "%s: error: no cpu sleep function\n", __func__); | ||
| 242 | return -EINVAL; | ||
| 243 | } | ||
| 244 | |||
| 245 | /* check if we have anything to wake-up with... bad things seem | ||
| 246 | * to happen if you suspend with no wakeup (system will often | ||
| 247 | * require a full power-cycle) | ||
| 248 | */ | ||
| 249 | |||
| 250 | if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && | ||
| 251 | !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) { | ||
| 252 | printk(KERN_ERR "%s: No wake-up sources!\n", __func__); | ||
| 253 | printk(KERN_ERR "%s: Aborting sleep\n", __func__); | ||
| 254 | return -EINVAL; | ||
| 255 | } | ||
| 256 | |||
| 257 | /* store the physical address of the register recovery block */ | ||
| 258 | |||
| 259 | s3c_sleep_save_phys = virt_to_phys(regs_save); | ||
| 260 | |||
| 261 | S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys); | ||
| 262 | |||
| 263 | /* save all necessary core registers not covered by the drivers */ | ||
| 264 | |||
| 265 | s3c_pm_save_gpios(); | ||
| 266 | s3c_pm_save_uarts(); | ||
| 267 | s3c_pm_save_core(); | ||
| 268 | |||
| 269 | /* set the irq configuration for wake */ | ||
| 270 | |||
| 271 | s3c_pm_configure_extint(); | ||
| 272 | |||
| 273 | S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n", | ||
| 274 | s3c_irqwake_intmask, s3c_irqwake_eintmask); | ||
| 275 | |||
| 276 | s3c_pm_arch_prepare_irqs(); | ||
| 277 | |||
| 278 | /* call cpu specific preparation */ | ||
| 279 | |||
| 280 | pm_cpu_prep(); | ||
| 281 | |||
| 282 | /* flush cache back to ram */ | ||
| 283 | |||
| 284 | flush_cache_all(); | ||
| 285 | |||
| 286 | s3c_pm_check_store(); | ||
| 287 | |||
| 288 | /* send the cpu to sleep... */ | ||
| 289 | |||
| 290 | s3c_pm_arch_stop_clocks(); | ||
| 291 | |||
| 292 | /* s3c_cpu_save will also act as our return point from when | ||
| 293 | * we resume as it saves its own register state and restores it | ||
| 294 | * during the resume. */ | ||
| 295 | |||
| 296 | s3c_cpu_save(regs_save); | ||
| 297 | |||
| 298 | /* restore the cpu state using the kernel's cpu init code. */ | ||
| 299 | |||
| 300 | cpu_init(); | ||
| 301 | |||
| 302 | /* restore the system state */ | ||
| 303 | |||
| 304 | s3c_pm_restore_core(); | ||
| 305 | s3c_pm_restore_uarts(); | ||
| 306 | s3c_pm_restore_gpios(); | ||
| 307 | |||
| 308 | s3c_pm_debug_init(); | ||
| 309 | |||
| 310 | /* check what irq (if any) restored the system */ | ||
| 311 | |||
| 312 | s3c_pm_arch_show_resume_irqs(); | ||
| 313 | |||
| 314 | S3C_PMDBG("%s: post sleep, preparing to return\n", __func__); | ||
| 315 | |||
| 316 | s3c_pm_check_restore(); | ||
| 317 | |||
| 318 | /* ok, let's return from sleep */ | ||
| 319 | |||
| 320 | S3C_PMDBG("S3C PM Resume (post-restore)\n"); | ||
| 321 | return 0; | ||
| 322 | } | ||
| 323 | |||
| 324 | /* callback from assembly code */ | ||
| 325 | void s3c_pm_cb_flushcache(void) | ||
| 326 | { | ||
| 327 | flush_cache_all(); | ||
| 328 | } | ||
| 329 | |||
| 330 | static int s3c_pm_prepare(void) | ||
| 331 | { | ||
| 332 | /* prepare check area if configured */ | ||
| 333 | |||
| 334 | s3c_pm_check_prepare(); | ||
| 335 | return 0; | ||
| 336 | } | ||
| 337 | |||
| 338 | static void s3c_pm_finish(void) | ||
| 339 | { | ||
| 340 | s3c_pm_check_cleanup(); | ||
| 341 | } | ||
| 342 | |||
| 343 | static struct platform_suspend_ops s3c_pm_ops = { | ||
| 344 | .enter = s3c_pm_enter, | ||
| 345 | .prepare = s3c_pm_prepare, | ||
| 346 | .finish = s3c_pm_finish, | ||
| 347 | .valid = suspend_valid_only_mem, | ||
| 348 | }; | ||
| 349 | |||
| 350 | /* s3c_pm_init | ||
| 351 | * | ||
| 352 | * Attach the power management functions. This should be called | ||
| 353 | * from the board specific initialisation if the board supports | ||
| 354 | * it. | ||
| 355 | */ | ||
| 356 | |||
| 357 | int __init s3c_pm_init(void) | ||
| 358 | { | ||
| 359 | printk("S3C Power Management, Copyright 2004 Simtec Electronics\n"); | ||
| 360 | |||
| 361 | suspend_set_ops(&s3c_pm_ops); | ||
| 362 | return 0; | ||
| 363 | } | ||
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index 1e0767b266b8..636cb12711df 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile | |||
| @@ -27,6 +27,7 @@ obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o | |||
| 27 | obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o | 27 | obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o |
| 28 | obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o | 28 | obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o |
| 29 | obj-$(CONFIG_PM) += pm.o | 29 | obj-$(CONFIG_PM) += pm.o |
| 30 | obj-$(CONFIG_PM) += irq-pm.o | ||
| 30 | obj-$(CONFIG_PM) += sleep.o | 31 | obj-$(CONFIG_PM) += sleep.o |
| 31 | obj-$(CONFIG_HAVE_PWM) += pwm.o | 32 | obj-$(CONFIG_HAVE_PWM) += pwm.o |
| 32 | obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o | 33 | obj-$(CONFIG_S3C2410_CLOCK) += s3c2410-clock.o |
diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c index 3d4837021ac7..1a8347cec20a 100644 --- a/arch/arm/plat-s3c24xx/common-smdk.c +++ b/arch/arm/plat-s3c24xx/common-smdk.c | |||
| @@ -201,5 +201,5 @@ void __init smdk_machine_init(void) | |||
| 201 | 201 | ||
| 202 | platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); | 202 | platform_add_devices(smdk_devs, ARRAY_SIZE(smdk_devs)); |
| 203 | 203 | ||
| 204 | s3c2410_pm_init(); | 204 | s3c_pm_init(); |
| 205 | } | 205 | } |
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c index 542062f8cbc1..1932b7e0da15 100644 --- a/arch/arm/plat-s3c24xx/cpu.c +++ b/arch/arm/plat-s3c24xx/cpu.c | |||
| @@ -182,7 +182,7 @@ static unsigned long s3c24xx_read_idcode_v4(void) | |||
| 182 | * with the caches enabled. It seems at least the S3C2440 has a problem | 182 | * with the caches enabled. It seems at least the S3C2440 has a problem |
| 183 | * resetting if there is bus activity interrupted by the reset. | 183 | * resetting if there is bus activity interrupted by the reset. |
| 184 | */ | 184 | */ |
| 185 | static void s3c24xx_pm_restart(char mode) | 185 | static void s3c24xx_pm_restart(char mode, const char *cmd) |
| 186 | { | 186 | { |
| 187 | if (mode != 's') { | 187 | if (mode != 's') { |
| 188 | unsigned long flags; | 188 | unsigned long flags; |
| @@ -191,12 +191,12 @@ static void s3c24xx_pm_restart(char mode) | |||
| 191 | __cpuc_flush_kern_all(); | 191 | __cpuc_flush_kern_all(); |
| 192 | __cpuc_flush_user_all(); | 192 | __cpuc_flush_user_all(); |
| 193 | 193 | ||
| 194 | arch_reset(mode); | 194 | arch_reset(mode, cmd); |
| 195 | local_irq_restore(flags); | 195 | local_irq_restore(flags); |
| 196 | } | 196 | } |
| 197 | 197 | ||
| 198 | /* fallback, or unhandled */ | 198 | /* fallback, or unhandled */ |
| 199 | arm_machine_restart(mode); | 199 | arm_machine_restart(mode, cmd); |
| 200 | } | 200 | } |
| 201 | 201 | ||
| 202 | void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) | 202 | void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) |
diff --git a/arch/arm/plat-s3c24xx/include/plat/irq.h b/arch/arm/plat-s3c24xx/include/plat/irq.h index 45746a995343..69e1be8bec35 100644 --- a/arch/arm/plat-s3c24xx/include/plat/irq.h +++ b/arch/arm/plat-s3c24xx/include/plat/irq.h | |||
| @@ -10,6 +10,12 @@ | |||
| 10 | * published by the Free Software Foundation. | 10 | * published by the Free Software Foundation. |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #include <linux/io.h> | ||
| 14 | |||
| 15 | #include <mach/hardware.h> | ||
| 16 | #include <mach/regs-irq.h> | ||
| 17 | #include <mach/regs-gpio.h> | ||
| 18 | |||
| 13 | #define irqdbf(x...) | 19 | #define irqdbf(x...) |
| 14 | #define irqdbf2(x...) | 20 | #define irqdbf2(x...) |
| 15 | 21 | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/map.h b/arch/arm/plat-s3c24xx/include/plat/map.h index fef8ea8b8e1e..eed8f78e7593 100644 --- a/arch/arm/plat-s3c24xx/include/plat/map.h +++ b/arch/arm/plat-s3c24xx/include/plat/map.h | |||
| @@ -31,6 +31,8 @@ | |||
| 31 | #define S3C24XX_SZ_UART SZ_1M | 31 | #define S3C24XX_SZ_UART SZ_1M |
| 32 | #define S3C_UART_OFFSET (0x4000) | 32 | #define S3C_UART_OFFSET (0x4000) |
| 33 | 33 | ||
| 34 | #define S3C_VA_UARTx(uart) (S3C_VA_UART + ((uart * S3C_UART_OFFSET))) | ||
| 35 | |||
| 34 | /* Timers */ | 36 | /* Timers */ |
| 35 | #define S3C24XX_VA_TIMER S3C_VA_TIMER | 37 | #define S3C24XX_VA_TIMER S3C_VA_TIMER |
| 36 | #define S3C2410_PA_TIMER (0x51000000) | 38 | #define S3C2410_PA_TIMER (0x51000000) |
diff --git a/arch/arm/plat-s3c24xx/include/plat/pm-core.h b/arch/arm/plat-s3c24xx/include/plat/pm-core.h new file mode 100644 index 000000000000..c75882113e04 --- /dev/null +++ b/arch/arm/plat-s3c24xx/include/plat/pm-core.h | |||
| @@ -0,0 +1,59 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/include/plat/pll.h | ||
| 2 | * | ||
| 3 | * Copyright 2008 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * http://armlinux.simtec.co.uk/ | ||
| 6 | * | ||
| 7 | * S3C24xx - PM core support for arch/arm/plat-s3c/pm.c | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | static inline void s3c_pm_debug_init_uart(void) | ||
| 15 | { | ||
| 16 | unsigned long tmp = __raw_readl(S3C2410_CLKCON); | ||
| 17 | |||
| 18 | /* re-start uart clocks */ | ||
| 19 | tmp |= S3C2410_CLKCON_UART0; | ||
| 20 | tmp |= S3C2410_CLKCON_UART1; | ||
| 21 | tmp |= S3C2410_CLKCON_UART2; | ||
| 22 | |||
| 23 | __raw_writel(tmp, S3C2410_CLKCON); | ||
| 24 | udelay(10); | ||
| 25 | } | ||
| 26 | |||
| 27 | static inline void s3c_pm_arch_prepare_irqs(void) | ||
| 28 | { | ||
| 29 | __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK); | ||
| 30 | __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK); | ||
| 31 | |||
| 32 | /* ack any outstanding external interrupts before we go to sleep */ | ||
| 33 | |||
| 34 | __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); | ||
| 35 | __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); | ||
| 36 | __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); | ||
| 37 | |||
| 38 | } | ||
| 39 | |||
| 40 | static inline void s3c_pm_arch_stop_clocks(void) | ||
| 41 | { | ||
| 42 | __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ | ||
| 43 | } | ||
| 44 | |||
| 45 | static void s3c_pm_show_resume_irqs(int start, unsigned long which, | ||
| 46 | unsigned long mask); | ||
| 47 | |||
| 48 | static inline void s3c_pm_arch_show_resume_irqs(void) | ||
| 49 | { | ||
| 50 | S3C_PMDBG("post sleep: IRQs 0x%08x, 0x%08x\n", | ||
| 51 | __raw_readl(S3C2410_SRCPND), | ||
| 52 | __raw_readl(S3C2410_EINTPEND)); | ||
| 53 | |||
| 54 | s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), | ||
| 55 | s3c_irqwake_intmask); | ||
| 56 | |||
| 57 | s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), | ||
| 58 | s3c_irqwake_eintmask); | ||
| 59 | } | ||
diff --git a/arch/arm/plat-s3c24xx/include/plat/pm.h b/arch/arm/plat-s3c24xx/include/plat/pm.h deleted file mode 100644 index cc623667e48a..000000000000 --- a/arch/arm/plat-s3c24xx/include/plat/pm.h +++ /dev/null | |||
| @@ -1,73 +0,0 @@ | |||
| 1 | /* linux/include/asm-arm/plat-s3c24xx/pm.h | ||
| 2 | * | ||
| 3 | * Copyright (c) 2004 Simtec Electronics | ||
| 4 | * Written by Ben Dooks, <ben@simtec.co.uk> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | /* s3c2410_pm_init | ||
| 12 | * | ||
| 13 | * called from board at initialisation time to setup the power | ||
| 14 | * management | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifdef CONFIG_PM | ||
| 18 | |||
| 19 | extern __init int s3c2410_pm_init(void); | ||
| 20 | |||
| 21 | #else | ||
| 22 | |||
| 23 | static inline int s3c2410_pm_init(void) | ||
| 24 | { | ||
| 25 | return 0; | ||
| 26 | } | ||
| 27 | #endif | ||
| 28 | |||
| 29 | /* configuration for the IRQ mask over sleep */ | ||
| 30 | extern unsigned long s3c_irqwake_intmask; | ||
| 31 | extern unsigned long s3c_irqwake_eintmask; | ||
| 32 | |||
| 33 | /* IRQ masks for IRQs allowed to go to sleep (see irq.c) */ | ||
| 34 | extern unsigned long s3c_irqwake_intallow; | ||
| 35 | extern unsigned long s3c_irqwake_eintallow; | ||
| 36 | |||
| 37 | /* per-cpu sleep functions */ | ||
| 38 | |||
| 39 | extern void (*pm_cpu_prep)(void); | ||
| 40 | extern void (*pm_cpu_sleep)(void); | ||
| 41 | |||
| 42 | /* Flags for PM Control */ | ||
| 43 | |||
| 44 | extern unsigned long s3c_pm_flags; | ||
| 45 | |||
| 46 | /* from sleep.S */ | ||
| 47 | |||
| 48 | extern int s3c2410_cpu_save(unsigned long *saveblk); | ||
| 49 | extern void s3c2410_cpu_suspend(void); | ||
| 50 | extern void s3c2410_cpu_resume(void); | ||
| 51 | |||
| 52 | extern unsigned long s3c2410_sleep_save_phys; | ||
| 53 | |||
| 54 | /* sleep save info */ | ||
| 55 | |||
| 56 | struct sleep_save { | ||
| 57 | void __iomem *reg; | ||
| 58 | unsigned long val; | ||
| 59 | }; | ||
| 60 | |||
| 61 | #define SAVE_ITEM(x) \ | ||
| 62 | { .reg = (x) } | ||
| 63 | |||
| 64 | extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count); | ||
| 65 | extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count); | ||
| 66 | |||
| 67 | #ifdef CONFIG_PM | ||
| 68 | extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state); | ||
| 69 | extern int s3c24xx_irq_resume(struct sys_device *dev); | ||
| 70 | #else | ||
| 71 | #define s3c24xx_irq_suspend NULL | ||
| 72 | #define s3c24xx_irq_resume NULL | ||
| 73 | #endif | ||
diff --git a/arch/arm/plat-s3c24xx/irq-pm.c b/arch/arm/plat-s3c24xx/irq-pm.c new file mode 100644 index 000000000000..b7acf1a8ecd2 --- /dev/null +++ b/arch/arm/plat-s3c24xx/irq-pm.c | |||
| @@ -0,0 +1,95 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/irq-om.c | ||
| 2 | * | ||
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | ||
| 4 | * Ben Dooks <ben@simtec.co.uk> | ||
| 5 | * http://armlinux.simtec.co.uk/ | ||
| 6 | * | ||
| 7 | * S3C24XX - IRQ PM code | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License version 2 as | ||
| 11 | * published by the Free Software Foundation. | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <linux/init.h> | ||
| 15 | #include <linux/module.h> | ||
| 16 | #include <linux/interrupt.h> | ||
| 17 | #include <linux/sysdev.h> | ||
| 18 | |||
| 19 | #include <plat/cpu.h> | ||
| 20 | #include <plat/pm.h> | ||
| 21 | #include <plat/irq.h> | ||
| 22 | |||
| 23 | /* state for IRQs over sleep */ | ||
| 24 | |||
| 25 | /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources | ||
| 26 | * | ||
| 27 | * set bit to 1 in allow bitfield to enable the wakeup settings on it | ||
| 28 | */ | ||
| 29 | |||
| 30 | unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL; | ||
| 31 | unsigned long s3c_irqwake_eintallow = 0x0000fff0L; | ||
| 32 | |||
| 33 | int s3c_irq_wake(unsigned int irqno, unsigned int state) | ||
| 34 | { | ||
| 35 | unsigned long irqbit = 1 << (irqno - IRQ_EINT0); | ||
| 36 | |||
| 37 | if (!(s3c_irqwake_intallow & irqbit)) | ||
| 38 | return -ENOENT; | ||
| 39 | |||
| 40 | printk(KERN_INFO "wake %s for irq %d\n", | ||
| 41 | state ? "enabled" : "disabled", irqno); | ||
| 42 | |||
| 43 | if (!state) | ||
| 44 | s3c_irqwake_intmask |= irqbit; | ||
| 45 | else | ||
| 46 | s3c_irqwake_intmask &= ~irqbit; | ||
| 47 | |||
| 48 | return 0; | ||
| 49 | } | ||
| 50 | |||
| 51 | static struct sleep_save irq_save[] = { | ||
| 52 | SAVE_ITEM(S3C2410_INTMSK), | ||
| 53 | SAVE_ITEM(S3C2410_INTSUBMSK), | ||
| 54 | }; | ||
| 55 | |||
| 56 | /* the extint values move between the s3c2410/s3c2440 and the s3c2412 | ||
| 57 | * so we use an array to hold them, and to calculate the address of | ||
| 58 | * the register at run-time | ||
| 59 | */ | ||
| 60 | |||
| 61 | static unsigned long save_extint[3]; | ||
| 62 | static unsigned long save_eintflt[4]; | ||
| 63 | static unsigned long save_eintmask; | ||
| 64 | |||
| 65 | int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state) | ||
| 66 | { | ||
| 67 | unsigned int i; | ||
| 68 | |||
| 69 | for (i = 0; i < ARRAY_SIZE(save_extint); i++) | ||
| 70 | save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4)); | ||
| 71 | |||
| 72 | for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) | ||
| 73 | save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4)); | ||
| 74 | |||
| 75 | s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); | ||
| 76 | save_eintmask = __raw_readl(S3C24XX_EINTMASK); | ||
| 77 | |||
| 78 | return 0; | ||
| 79 | } | ||
| 80 | |||
| 81 | int s3c24xx_irq_resume(struct sys_device *dev) | ||
| 82 | { | ||
| 83 | unsigned int i; | ||
| 84 | |||
| 85 | for (i = 0; i < ARRAY_SIZE(save_extint); i++) | ||
| 86 | __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4)); | ||
| 87 | |||
| 88 | for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) | ||
| 89 | __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4)); | ||
| 90 | |||
| 91 | s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); | ||
| 92 | __raw_writel(save_eintmask, S3C24XX_EINTMASK); | ||
| 93 | |||
| 94 | return 0; | ||
| 95 | } | ||
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c index 0192ecdc1442..958737775ad2 100644 --- a/arch/arm/plat-s3c24xx/irq.c +++ b/arch/arm/plat-s3c24xx/irq.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* linux/arch/arm/plat-s3c24xx/irq.c | 1 | /* linux/arch/arm/plat-s3c24xx/irq.c |
| 2 | * | 2 | * |
| 3 | * Copyright (c) 2003,2004 Simtec Electronics | 3 | * Copyright (c) 2003,2004 Simtec Electronics |
| 4 | * Ben Dooks <ben@simtec.co.uk> | 4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify | 6 | * This program is free software; you can redistribute it and/or modify |
| @@ -16,38 +16,6 @@ | |||
| 16 | * You should have received a copy of the GNU General Public License | 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software | 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 19 | * | ||
| 20 | * Changelog: | ||
| 21 | * | ||
| 22 | * 22-Jul-2004 Ben Dooks <ben@simtec.co.uk> | ||
| 23 | * Fixed compile warnings | ||
| 24 | * | ||
| 25 | * 22-Jul-2004 Roc Wu <cooloney@yahoo.com.cn> | ||
| 26 | * Fixed s3c_extirq_type | ||
| 27 | * | ||
| 28 | * 21-Jul-2004 Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org> | ||
| 29 | * Addition of ADC/TC demux | ||
| 30 | * | ||
| 31 | * 04-Oct-2004 Klaus Fetscher <k.fetscher@fetron.de> | ||
| 32 | * Fix for set_irq_type() on low EINT numbers | ||
| 33 | * | ||
| 34 | * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk> | ||
| 35 | * Tidy up KF's patch and sort out new release | ||
| 36 | * | ||
| 37 | * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk> | ||
| 38 | * Add support for power management controls | ||
| 39 | * | ||
| 40 | * 04-Nov-2004 Ben Dooks | ||
| 41 | * Fix standard IRQ wake for EINT0..4 and RTC | ||
| 42 | * | ||
| 43 | * 22-Feb-2005 Ben Dooks | ||
| 44 | * Fixed edge-triggering on ADC IRQ | ||
| 45 | * | ||
| 46 | * 28-Jun-2005 Ben Dooks | ||
| 47 | * Mark IRQ_LCD valid | ||
| 48 | * | ||
| 49 | * 25-Jul-2005 Ben Dooks | ||
| 50 | * Split the S3C2440 IRQ code to separate file | ||
| 51 | */ | 19 | */ |
| 52 | 20 | ||
| 53 | #include <linux/init.h> | 21 | #include <linux/init.h> |
| @@ -55,81 +23,16 @@ | |||
| 55 | #include <linux/interrupt.h> | 23 | #include <linux/interrupt.h> |
| 56 | #include <linux/ioport.h> | 24 | #include <linux/ioport.h> |
| 57 | #include <linux/sysdev.h> | 25 | #include <linux/sysdev.h> |
| 58 | #include <linux/io.h> | ||
| 59 | 26 | ||
| 60 | #include <mach/hardware.h> | ||
| 61 | #include <asm/irq.h> | 27 | #include <asm/irq.h> |
| 62 | |||
| 63 | #include <asm/mach/irq.h> | 28 | #include <asm/mach/irq.h> |
| 64 | 29 | ||
| 65 | #include <plat/regs-irqtype.h> | 30 | #include <plat/regs-irqtype.h> |
| 66 | #include <mach/regs-irq.h> | ||
| 67 | #include <mach/regs-gpio.h> | ||
| 68 | 31 | ||
| 69 | #include <plat/cpu.h> | 32 | #include <plat/cpu.h> |
| 70 | #include <plat/pm.h> | 33 | #include <plat/pm.h> |
| 71 | #include <plat/irq.h> | 34 | #include <plat/irq.h> |
| 72 | 35 | ||
| 73 | /* wakeup irq control */ | ||
| 74 | |||
| 75 | #ifdef CONFIG_PM | ||
| 76 | |||
| 77 | /* state for IRQs over sleep */ | ||
| 78 | |||
| 79 | /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources | ||
| 80 | * | ||
| 81 | * set bit to 1 in allow bitfield to enable the wakeup settings on it | ||
| 82 | */ | ||
| 83 | |||
| 84 | unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL; | ||
| 85 | unsigned long s3c_irqwake_intmask = 0xffffffffL; | ||
| 86 | unsigned long s3c_irqwake_eintallow = 0x0000fff0L; | ||
| 87 | unsigned long s3c_irqwake_eintmask = 0xffffffffL; | ||
| 88 | |||
| 89 | int | ||
| 90 | s3c_irq_wake(unsigned int irqno, unsigned int state) | ||
| 91 | { | ||
| 92 | unsigned long irqbit = 1 << (irqno - IRQ_EINT0); | ||
| 93 | |||
| 94 | if (!(s3c_irqwake_intallow & irqbit)) | ||
| 95 | return -ENOENT; | ||
| 96 | |||
| 97 | printk(KERN_INFO "wake %s for irq %d\n", | ||
| 98 | state ? "enabled" : "disabled", irqno); | ||
| 99 | |||
| 100 | if (!state) | ||
| 101 | s3c_irqwake_intmask |= irqbit; | ||
| 102 | else | ||
| 103 | s3c_irqwake_intmask &= ~irqbit; | ||
| 104 | |||
| 105 | return 0; | ||
| 106 | } | ||
| 107 | |||
| 108 | static int | ||
| 109 | s3c_irqext_wake(unsigned int irqno, unsigned int state) | ||
| 110 | { | ||
| 111 | unsigned long bit = 1L << (irqno - EXTINT_OFF); | ||
| 112 | |||
| 113 | if (!(s3c_irqwake_eintallow & bit)) | ||
| 114 | return -ENOENT; | ||
| 115 | |||
| 116 | printk(KERN_INFO "wake %s for irq %d\n", | ||
| 117 | state ? "enabled" : "disabled", irqno); | ||
| 118 | |||
| 119 | if (!state) | ||
| 120 | s3c_irqwake_eintmask |= bit; | ||
| 121 | else | ||
| 122 | s3c_irqwake_eintmask &= ~bit; | ||
| 123 | |||
| 124 | return 0; | ||
| 125 | } | ||
| 126 | |||
| 127 | #else | ||
| 128 | #define s3c_irqext_wake NULL | ||
| 129 | #define s3c_irq_wake NULL | ||
| 130 | #endif | ||
| 131 | |||
| 132 | |||
| 133 | static void | 36 | static void |
| 134 | s3c_irq_mask(unsigned int irqno) | 37 | s3c_irq_mask(unsigned int irqno) |
| 135 | { | 38 | { |
| @@ -590,59 +493,6 @@ s3c_irq_demux_extint4t7(unsigned int irq, | |||
| 590 | } | 493 | } |
| 591 | } | 494 | } |
| 592 | 495 | ||
| 593 | #ifdef CONFIG_PM | ||
| 594 | |||
| 595 | static struct sleep_save irq_save[] = { | ||
| 596 | SAVE_ITEM(S3C2410_INTMSK), | ||
| 597 | SAVE_ITEM(S3C2410_INTSUBMSK), | ||
| 598 | }; | ||
| 599 | |||
| 600 | /* the extint values move between the s3c2410/s3c2440 and the s3c2412 | ||
| 601 | * so we use an array to hold them, and to calculate the address of | ||
| 602 | * the register at run-time | ||
| 603 | */ | ||
| 604 | |||
| 605 | static unsigned long save_extint[3]; | ||
| 606 | static unsigned long save_eintflt[4]; | ||
| 607 | static unsigned long save_eintmask; | ||
| 608 | |||
| 609 | int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state) | ||
| 610 | { | ||
| 611 | unsigned int i; | ||
| 612 | |||
| 613 | for (i = 0; i < ARRAY_SIZE(save_extint); i++) | ||
| 614 | save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4)); | ||
| 615 | |||
| 616 | for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) | ||
| 617 | save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4)); | ||
| 618 | |||
| 619 | s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); | ||
| 620 | save_eintmask = __raw_readl(S3C24XX_EINTMASK); | ||
| 621 | |||
| 622 | return 0; | ||
| 623 | } | ||
| 624 | |||
| 625 | int s3c24xx_irq_resume(struct sys_device *dev) | ||
| 626 | { | ||
| 627 | unsigned int i; | ||
| 628 | |||
| 629 | for (i = 0; i < ARRAY_SIZE(save_extint); i++) | ||
| 630 | __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4)); | ||
| 631 | |||
| 632 | for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) | ||
| 633 | __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4)); | ||
| 634 | |||
| 635 | s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); | ||
| 636 | __raw_writel(save_eintmask, S3C24XX_EINTMASK); | ||
| 637 | |||
| 638 | return 0; | ||
| 639 | } | ||
| 640 | |||
| 641 | #else | ||
| 642 | #define s3c24xx_irq_suspend NULL | ||
| 643 | #define s3c24xx_irq_resume NULL | ||
| 644 | #endif | ||
| 645 | |||
| 646 | /* s3c24xx_init_irq | 496 | /* s3c24xx_init_irq |
| 647 | * | 497 | * |
| 648 | * Initialise S3C2410 IRQ system | 498 | * Initialise S3C2410 IRQ system |
diff --git a/arch/arm/plat-s3c24xx/pm-simtec.c b/arch/arm/plat-s3c24xx/pm-simtec.c index 21dfa74773d1..da0d3217d3e3 100644 --- a/arch/arm/plat-s3c24xx/pm-simtec.c +++ b/arch/arm/plat-s3c24xx/pm-simtec.c | |||
| @@ -61,7 +61,7 @@ static __init int pm_simtec_init(void) | |||
| 61 | 61 | ||
| 62 | __raw_writel(gstatus4, S3C2410_GSTATUS4); | 62 | __raw_writel(gstatus4, S3C2410_GSTATUS4); |
| 63 | 63 | ||
| 64 | return s3c2410_pm_init(); | 64 | return s3c_pm_init(); |
| 65 | } | 65 | } |
| 66 | 66 | ||
| 67 | arch_initcall(pm_simtec_init); | 67 | arch_initcall(pm_simtec_init); |
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c index 34ef18e5b2a1..062a29339a91 100644 --- a/arch/arm/plat-s3c24xx/pm.c +++ b/arch/arm/plat-s3c24xx/pm.c | |||
| @@ -31,14 +31,9 @@ | |||
| 31 | #include <linux/errno.h> | 31 | #include <linux/errno.h> |
| 32 | #include <linux/time.h> | 32 | #include <linux/time.h> |
| 33 | #include <linux/interrupt.h> | 33 | #include <linux/interrupt.h> |
| 34 | #include <linux/crc32.h> | ||
| 35 | #include <linux/ioport.h> | ||
| 36 | #include <linux/serial_core.h> | 34 | #include <linux/serial_core.h> |
| 37 | #include <linux/io.h> | 35 | #include <linux/io.h> |
| 38 | 36 | ||
| 39 | #include <asm/cacheflush.h> | ||
| 40 | #include <mach/hardware.h> | ||
| 41 | |||
| 42 | #include <plat/regs-serial.h> | 37 | #include <plat/regs-serial.h> |
| 43 | #include <mach/regs-clock.h> | 38 | #include <mach/regs-clock.h> |
| 44 | #include <mach/regs-gpio.h> | 39 | #include <mach/regs-gpio.h> |
| @@ -49,10 +44,6 @@ | |||
| 49 | 44 | ||
| 50 | #include <plat/pm.h> | 45 | #include <plat/pm.h> |
| 51 | 46 | ||
| 52 | /* for external use */ | ||
| 53 | |||
| 54 | unsigned long s3c_pm_flags; | ||
| 55 | |||
| 56 | #define PFX "s3c24xx-pm: " | 47 | #define PFX "s3c24xx-pm: " |
| 57 | 48 | ||
| 58 | static struct sleep_save core_save[] = { | 49 | static struct sleep_save core_save[] = { |
| @@ -120,328 +111,14 @@ static struct sleep_save misc_save[] = { | |||
| 120 | SAVE_ITEM(S3C2410_DCLKCON), | 111 | SAVE_ITEM(S3C2410_DCLKCON), |
| 121 | }; | 112 | }; |
| 122 | 113 | ||
| 123 | #ifdef CONFIG_S3C2410_PM_DEBUG | ||
| 124 | |||
| 125 | #define SAVE_UART(va) \ | ||
| 126 | SAVE_ITEM((va) + S3C2410_ULCON), \ | ||
| 127 | SAVE_ITEM((va) + S3C2410_UCON), \ | ||
| 128 | SAVE_ITEM((va) + S3C2410_UFCON), \ | ||
| 129 | SAVE_ITEM((va) + S3C2410_UMCON), \ | ||
| 130 | SAVE_ITEM((va) + S3C2410_UBRDIV) | ||
| 131 | |||
| 132 | static struct sleep_save uart_save[] = { | ||
| 133 | SAVE_UART(S3C24XX_VA_UART0), | ||
| 134 | SAVE_UART(S3C24XX_VA_UART1), | ||
| 135 | #ifndef CONFIG_CPU_S3C2400 | ||
| 136 | SAVE_UART(S3C24XX_VA_UART2), | ||
| 137 | #endif | ||
| 138 | }; | ||
| 139 | |||
| 140 | /* debug | ||
| 141 | * | ||
| 142 | * we send the debug to printascii() to allow it to be seen if the | ||
| 143 | * system never wakes up from the sleep | ||
| 144 | */ | ||
| 145 | |||
| 146 | extern void printascii(const char *); | ||
| 147 | |||
| 148 | void pm_dbg(const char *fmt, ...) | ||
| 149 | { | ||
| 150 | va_list va; | ||
| 151 | char buff[256]; | ||
| 152 | |||
| 153 | va_start(va, fmt); | ||
| 154 | vsprintf(buff, fmt, va); | ||
| 155 | va_end(va); | ||
| 156 | |||
| 157 | printascii(buff); | ||
| 158 | } | ||
| 159 | |||
| 160 | static void s3c2410_pm_debug_init(void) | ||
| 161 | { | ||
| 162 | unsigned long tmp = __raw_readl(S3C2410_CLKCON); | ||
| 163 | |||
| 164 | /* re-start uart clocks */ | ||
| 165 | tmp |= S3C2410_CLKCON_UART0; | ||
| 166 | tmp |= S3C2410_CLKCON_UART1; | ||
| 167 | tmp |= S3C2410_CLKCON_UART2; | ||
| 168 | |||
| 169 | __raw_writel(tmp, S3C2410_CLKCON); | ||
| 170 | udelay(10); | ||
| 171 | } | ||
| 172 | |||
| 173 | #define DBG(fmt...) pm_dbg(fmt) | ||
| 174 | #else | ||
| 175 | #define DBG(fmt...) printk(KERN_DEBUG fmt) | ||
| 176 | |||
| 177 | #define s3c2410_pm_debug_init() do { } while(0) | ||
| 178 | |||
| 179 | static struct sleep_save uart_save[] = {}; | ||
| 180 | #endif | ||
| 181 | |||
| 182 | #if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0 | ||
| 183 | |||
| 184 | /* suspend checking code... | ||
| 185 | * | ||
| 186 | * this next area does a set of crc checks over all the installed | ||
| 187 | * memory, so the system can verify if the resume was ok. | ||
| 188 | * | ||
| 189 | * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC, | ||
| 190 | * increasing it will mean that the area corrupted will be less easy to spot, | ||
| 191 | * and reducing the size will cause the CRC save area to grow | ||
| 192 | */ | ||
| 193 | |||
| 194 | #define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024) | ||
| 195 | |||
| 196 | static u32 crc_size; /* size needed for the crc block */ | ||
| 197 | static u32 *crcs; /* allocated over suspend/resume */ | ||
| 198 | |||
| 199 | typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg); | ||
| 200 | |||
| 201 | /* s3c2410_pm_run_res | ||
| 202 | * | ||
| 203 | * go thorugh the given resource list, and look for system ram | ||
| 204 | */ | ||
| 205 | |||
| 206 | static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg) | ||
| 207 | { | ||
| 208 | while (ptr != NULL) { | ||
| 209 | if (ptr->child != NULL) | ||
| 210 | s3c2410_pm_run_res(ptr->child, fn, arg); | ||
| 211 | |||
| 212 | if ((ptr->flags & IORESOURCE_MEM) && | ||
| 213 | strcmp(ptr->name, "System RAM") == 0) { | ||
| 214 | DBG("Found system RAM at %08lx..%08lx\n", | ||
| 215 | ptr->start, ptr->end); | ||
| 216 | arg = (fn)(ptr, arg); | ||
| 217 | } | ||
| 218 | |||
| 219 | ptr = ptr->sibling; | ||
| 220 | } | ||
| 221 | } | ||
| 222 | |||
| 223 | static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg) | ||
| 224 | { | ||
| 225 | s3c2410_pm_run_res(&iomem_resource, fn, arg); | ||
| 226 | } | ||
| 227 | |||
| 228 | static u32 *s3c2410_pm_countram(struct resource *res, u32 *val) | ||
| 229 | { | ||
| 230 | u32 size = (u32)(res->end - res->start)+1; | ||
| 231 | |||
| 232 | size += CHECK_CHUNKSIZE-1; | ||
| 233 | size /= CHECK_CHUNKSIZE; | ||
| 234 | |||
| 235 | DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size); | ||
| 236 | |||
| 237 | *val += size * sizeof(u32); | ||
| 238 | return val; | ||
| 239 | } | ||
| 240 | |||
| 241 | /* s3c2410_pm_prepare_check | ||
| 242 | * | ||
| 243 | * prepare the necessary information for creating the CRCs. This | ||
| 244 | * must be done before the final save, as it will require memory | ||
| 245 | * allocating, and thus touching bits of the kernel we do not | ||
| 246 | * know about. | ||
| 247 | */ | ||
| 248 | |||
| 249 | static void s3c2410_pm_check_prepare(void) | ||
| 250 | { | ||
| 251 | crc_size = 0; | ||
| 252 | |||
| 253 | s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size); | ||
| 254 | |||
| 255 | DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size); | ||
| 256 | |||
| 257 | crcs = kmalloc(crc_size+4, GFP_KERNEL); | ||
| 258 | if (crcs == NULL) | ||
| 259 | printk(KERN_ERR "Cannot allocated CRC save area\n"); | ||
| 260 | } | ||
| 261 | |||
| 262 | static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val) | ||
| 263 | { | ||
| 264 | unsigned long addr, left; | ||
| 265 | |||
| 266 | for (addr = res->start; addr < res->end; | ||
| 267 | addr += CHECK_CHUNKSIZE) { | ||
| 268 | left = res->end - addr; | ||
| 269 | |||
| 270 | if (left > CHECK_CHUNKSIZE) | ||
| 271 | left = CHECK_CHUNKSIZE; | ||
| 272 | |||
| 273 | *val = crc32_le(~0, phys_to_virt(addr), left); | ||
| 274 | val++; | ||
| 275 | } | ||
| 276 | |||
| 277 | return val; | ||
| 278 | } | ||
| 279 | |||
| 280 | /* s3c2410_pm_check_store | ||
| 281 | * | ||
| 282 | * compute the CRC values for the memory blocks before the final | ||
| 283 | * sleep. | ||
| 284 | */ | ||
| 285 | |||
| 286 | static void s3c2410_pm_check_store(void) | ||
| 287 | { | ||
| 288 | if (crcs != NULL) | ||
| 289 | s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs); | ||
| 290 | } | ||
| 291 | |||
| 292 | /* in_region | ||
| 293 | * | ||
| 294 | * return TRUE if the area defined by ptr..ptr+size contatins the | ||
| 295 | * what..what+whatsz | ||
| 296 | */ | ||
| 297 | |||
| 298 | static inline int in_region(void *ptr, int size, void *what, size_t whatsz) | ||
| 299 | { | ||
| 300 | if ((what+whatsz) < ptr) | ||
| 301 | return 0; | ||
| 302 | |||
| 303 | if (what > (ptr+size)) | ||
| 304 | return 0; | ||
| 305 | |||
| 306 | return 1; | ||
| 307 | } | ||
| 308 | |||
| 309 | static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val) | ||
| 310 | { | ||
| 311 | void *save_at = phys_to_virt(s3c2410_sleep_save_phys); | ||
| 312 | unsigned long addr; | ||
| 313 | unsigned long left; | ||
| 314 | void *ptr; | ||
| 315 | u32 calc; | ||
| 316 | |||
| 317 | for (addr = res->start; addr < res->end; | ||
| 318 | addr += CHECK_CHUNKSIZE) { | ||
| 319 | left = res->end - addr; | ||
| 320 | |||
| 321 | if (left > CHECK_CHUNKSIZE) | ||
| 322 | left = CHECK_CHUNKSIZE; | ||
| 323 | |||
| 324 | ptr = phys_to_virt(addr); | ||
| 325 | |||
| 326 | if (in_region(ptr, left, crcs, crc_size)) { | ||
| 327 | DBG("skipping %08lx, has crc block in\n", addr); | ||
| 328 | goto skip_check; | ||
| 329 | } | ||
| 330 | |||
| 331 | if (in_region(ptr, left, save_at, 32*4 )) { | ||
| 332 | DBG("skipping %08lx, has save block in\n", addr); | ||
| 333 | goto skip_check; | ||
| 334 | } | ||
| 335 | |||
| 336 | /* calculate and check the checksum */ | ||
| 337 | |||
| 338 | calc = crc32_le(~0, ptr, left); | ||
| 339 | if (calc != *val) { | ||
| 340 | printk(KERN_ERR PFX "Restore CRC error at " | ||
| 341 | "%08lx (%08x vs %08x)\n", addr, calc, *val); | ||
| 342 | |||
| 343 | DBG("Restore CRC error at %08lx (%08x vs %08x)\n", | ||
| 344 | addr, calc, *val); | ||
| 345 | } | ||
| 346 | |||
| 347 | skip_check: | ||
| 348 | val++; | ||
| 349 | } | ||
| 350 | |||
| 351 | return val; | ||
| 352 | } | ||
| 353 | |||
| 354 | /* s3c2410_pm_check_restore | ||
| 355 | * | ||
| 356 | * check the CRCs after the restore event and free the memory used | ||
| 357 | * to hold them | ||
| 358 | */ | ||
| 359 | |||
| 360 | static void s3c2410_pm_check_restore(void) | ||
| 361 | { | ||
| 362 | if (crcs != NULL) { | ||
| 363 | s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs); | ||
| 364 | kfree(crcs); | ||
| 365 | crcs = NULL; | ||
| 366 | } | ||
| 367 | } | ||
| 368 | |||
| 369 | #else | ||
| 370 | |||
| 371 | #define s3c2410_pm_check_prepare() do { } while(0) | ||
| 372 | #define s3c2410_pm_check_restore() do { } while(0) | ||
| 373 | #define s3c2410_pm_check_store() do { } while(0) | ||
| 374 | #endif | ||
| 375 | |||
| 376 | /* helper functions to save and restore register state */ | ||
| 377 | |||
| 378 | void s3c2410_pm_do_save(struct sleep_save *ptr, int count) | ||
| 379 | { | ||
| 380 | for (; count > 0; count--, ptr++) { | ||
| 381 | ptr->val = __raw_readl(ptr->reg); | ||
| 382 | DBG("saved %p value %08lx\n", ptr->reg, ptr->val); | ||
| 383 | } | ||
| 384 | } | ||
| 385 | |||
| 386 | /* s3c2410_pm_do_restore | ||
| 387 | * | ||
| 388 | * restore the system from the given list of saved registers | ||
| 389 | * | ||
| 390 | * Note, we do not use DBG() in here, as the system may not have | ||
| 391 | * restore the UARTs state yet | ||
| 392 | */ | ||
| 393 | |||
| 394 | void s3c2410_pm_do_restore(struct sleep_save *ptr, int count) | ||
| 395 | { | ||
| 396 | for (; count > 0; count--, ptr++) { | ||
| 397 | printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", | ||
| 398 | ptr->reg, ptr->val, __raw_readl(ptr->reg)); | ||
| 399 | |||
| 400 | __raw_writel(ptr->val, ptr->reg); | ||
| 401 | } | ||
| 402 | } | ||
| 403 | |||
| 404 | /* s3c2410_pm_do_restore_core | ||
| 405 | * | ||
| 406 | * similar to s3c2410_pm_do_restore_core | ||
| 407 | * | ||
| 408 | * WARNING: Do not put any debug in here that may effect memory or use | ||
| 409 | * peripherals, as things may be changing! | ||
| 410 | */ | ||
| 411 | |||
| 412 | static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count) | ||
| 413 | { | ||
| 414 | for (; count > 0; count--, ptr++) { | ||
| 415 | __raw_writel(ptr->val, ptr->reg); | ||
| 416 | } | ||
| 417 | } | ||
| 418 | 114 | ||
| 419 | /* s3c2410_pm_show_resume_irqs | 115 | /* s3c_pm_check_resume_pin |
| 420 | * | ||
| 421 | * print any IRQs asserted at resume time (ie, we woke from) | ||
| 422 | */ | ||
| 423 | |||
| 424 | static void s3c2410_pm_show_resume_irqs(int start, unsigned long which, | ||
| 425 | unsigned long mask) | ||
| 426 | { | ||
| 427 | int i; | ||
| 428 | |||
| 429 | which &= ~mask; | ||
| 430 | |||
| 431 | for (i = 0; i <= 31; i++) { | ||
| 432 | if ((which) & (1L<<i)) { | ||
| 433 | DBG("IRQ %d asserted at resume\n", start+i); | ||
| 434 | } | ||
| 435 | } | ||
| 436 | } | ||
| 437 | |||
| 438 | /* s3c2410_pm_check_resume_pin | ||
| 439 | * | 116 | * |
| 440 | * check to see if the pin is configured correctly for sleep mode, and | 117 | * check to see if the pin is configured correctly for sleep mode, and |
| 441 | * make any necessary adjustments if it is not | 118 | * make any necessary adjustments if it is not |
| 442 | */ | 119 | */ |
| 443 | 120 | ||
| 444 | static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) | 121 | static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) |
| 445 | { | 122 | { |
| 446 | unsigned long irqstate; | 123 | unsigned long irqstate; |
| 447 | unsigned long pinstate; | 124 | unsigned long pinstate; |
| @@ -456,21 +133,21 @@ static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs) | |||
| 456 | 133 | ||
| 457 | if (!irqstate) { | 134 | if (!irqstate) { |
| 458 | if (pinstate == S3C2410_GPIO_IRQ) | 135 | if (pinstate == S3C2410_GPIO_IRQ) |
| 459 | DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin); | 136 | S3C_PMDBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin); |
| 460 | } else { | 137 | } else { |
| 461 | if (pinstate == S3C2410_GPIO_IRQ) { | 138 | if (pinstate == S3C2410_GPIO_IRQ) { |
| 462 | DBG("Disabling IRQ %d (pin %d)\n", irq, pin); | 139 | S3C_PMDBG("Disabling IRQ %d (pin %d)\n", irq, pin); |
| 463 | s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); | 140 | s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT); |
| 464 | } | 141 | } |
| 465 | } | 142 | } |
| 466 | } | 143 | } |
| 467 | 144 | ||
| 468 | /* s3c2410_pm_configure_extint | 145 | /* s3c_pm_configure_extint |
| 469 | * | 146 | * |
| 470 | * configure all external interrupt pins | 147 | * configure all external interrupt pins |
| 471 | */ | 148 | */ |
| 472 | 149 | ||
| 473 | static void s3c2410_pm_configure_extint(void) | 150 | void s3c_pm_configure_extint(void) |
| 474 | { | 151 | { |
| 475 | int pin; | 152 | int pin; |
| 476 | 153 | ||
| @@ -480,11 +157,11 @@ static void s3c2410_pm_configure_extint(void) | |||
| 480 | */ | 157 | */ |
| 481 | 158 | ||
| 482 | for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) { | 159 | for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) { |
| 483 | s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0); | 160 | s3c_pm_check_resume_pin(pin, pin - S3C2410_GPF0); |
| 484 | } | 161 | } |
| 485 | 162 | ||
| 486 | for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) { | 163 | for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) { |
| 487 | s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8); | 164 | s3c_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8); |
| 488 | } | 165 | } |
| 489 | } | 166 | } |
| 490 | 167 | ||
| @@ -494,12 +171,12 @@ static void s3c2410_pm_configure_extint(void) | |||
| 494 | #define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON) | 171 | #define OFFS_DAT (S3C2410_GPADAT - S3C2410_GPACON) |
| 495 | #define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON) | 172 | #define OFFS_UP (S3C2410_GPBUP - S3C2410_GPBCON) |
| 496 | 173 | ||
| 497 | /* s3c2410_pm_save_gpios() | 174 | /* s3c_pm_save_gpios() |
| 498 | * | 175 | * |
| 499 | * Save the state of the GPIOs | 176 | * Save the state of the GPIOs |
| 500 | */ | 177 | */ |
| 501 | 178 | ||
| 502 | static void s3c2410_pm_save_gpios(void) | 179 | void s3c_pm_save_gpios(void) |
| 503 | { | 180 | { |
| 504 | struct gpio_sleep *gps = gpio_save; | 181 | struct gpio_sleep *gps = gpio_save; |
| 505 | unsigned int gpio; | 182 | unsigned int gpio; |
| @@ -538,7 +215,10 @@ static inline int is_out(unsigned long con) | |||
| 538 | return con == 1; | 215 | return con == 1; |
| 539 | } | 216 | } |
| 540 | 217 | ||
| 541 | /* s3c2410_pm_restore_gpio() | 218 | /** |
| 219 | * s3c2410_pm_restore_gpio() - restore the given GPIO bank | ||
| 220 | * @index: The number of the GPIO bank being resumed. | ||
| 221 | * @gps: The sleep confgiuration for the bank. | ||
| 542 | * | 222 | * |
| 543 | * Restore one of the GPIO banks that was saved during suspend. This is | 223 | * Restore one of the GPIO banks that was saved during suspend. This is |
| 544 | * not as simple as once thought, due to the possibility of glitches | 224 | * not as simple as once thought, due to the possibility of glitches |
| @@ -646,8 +326,8 @@ static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps) | |||
| 646 | __raw_writel(gps->gpup, base + OFFS_UP); | 326 | __raw_writel(gps->gpup, base + OFFS_UP); |
| 647 | } | 327 | } |
| 648 | 328 | ||
| 649 | DBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n", | 329 | S3C_PMDBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n", |
| 650 | index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); | 330 | index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); |
| 651 | } | 331 | } |
| 652 | 332 | ||
| 653 | 333 | ||
| @@ -656,7 +336,7 @@ static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps) | |||
| 656 | * Restore the state of the GPIOs | 336 | * Restore the state of the GPIOs |
| 657 | */ | 337 | */ |
| 658 | 338 | ||
| 659 | static void s3c2410_pm_restore_gpios(void) | 339 | void s3c_pm_restore_gpios(void) |
| 660 | { | 340 | { |
| 661 | struct gpio_sleep *gps = gpio_save; | 341 | struct gpio_sleep *gps = gpio_save; |
| 662 | int gpio; | 342 | int gpio; |
| @@ -666,150 +346,15 @@ static void s3c2410_pm_restore_gpios(void) | |||
| 666 | } | 346 | } |
| 667 | } | 347 | } |
| 668 | 348 | ||
| 669 | void (*pm_cpu_prep)(void); | 349 | void s3c_pm_restore_core(void) |
| 670 | void (*pm_cpu_sleep)(void); | ||
| 671 | |||
| 672 | #define any_allowed(mask, allow) (((mask) & (allow)) != (allow)) | ||
| 673 | |||
| 674 | /* s3c2410_pm_enter | ||
| 675 | * | ||
| 676 | * central control for sleep/resume process | ||
| 677 | */ | ||
| 678 | |||
| 679 | static int s3c2410_pm_enter(suspend_state_t state) | ||
| 680 | { | 350 | { |
| 681 | unsigned long regs_save[16]; | 351 | s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); |
| 682 | 352 | s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); | |
| 683 | /* ensure the debug is initialised (if enabled) */ | ||
| 684 | |||
| 685 | s3c2410_pm_debug_init(); | ||
| 686 | |||
| 687 | DBG("s3c2410_pm_enter(%d)\n", state); | ||
| 688 | |||
| 689 | if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) { | ||
| 690 | printk(KERN_ERR PFX "error: no cpu sleep functions set\n"); | ||
| 691 | return -EINVAL; | ||
| 692 | } | ||
| 693 | |||
| 694 | /* check if we have anything to wake-up with... bad things seem | ||
| 695 | * to happen if you suspend with no wakeup (system will often | ||
| 696 | * require a full power-cycle) | ||
| 697 | */ | ||
| 698 | |||
| 699 | if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) && | ||
| 700 | !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) { | ||
| 701 | printk(KERN_ERR PFX "No sources enabled for wake-up!\n"); | ||
| 702 | printk(KERN_ERR PFX "Aborting sleep\n"); | ||
| 703 | return -EINVAL; | ||
| 704 | } | ||
| 705 | |||
| 706 | /* prepare check area if configured */ | ||
| 707 | |||
| 708 | s3c2410_pm_check_prepare(); | ||
| 709 | |||
| 710 | /* store the physical address of the register recovery block */ | ||
| 711 | |||
| 712 | s3c2410_sleep_save_phys = virt_to_phys(regs_save); | ||
| 713 | |||
| 714 | DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys); | ||
| 715 | |||
| 716 | /* save all necessary core registers not covered by the drivers */ | ||
| 717 | |||
| 718 | s3c2410_pm_save_gpios(); | ||
| 719 | s3c2410_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); | ||
| 720 | s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save)); | ||
| 721 | s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save)); | ||
| 722 | |||
| 723 | /* set the irq configuration for wake */ | ||
| 724 | |||
| 725 | s3c2410_pm_configure_extint(); | ||
| 726 | |||
| 727 | DBG("sleep: irq wakeup masks: %08lx,%08lx\n", | ||
| 728 | s3c_irqwake_intmask, s3c_irqwake_eintmask); | ||
| 729 | |||
| 730 | __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK); | ||
| 731 | __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK); | ||
| 732 | |||
| 733 | /* ack any outstanding external interrupts before we go to sleep */ | ||
| 734 | |||
| 735 | __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); | ||
| 736 | __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); | ||
| 737 | __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); | ||
| 738 | |||
| 739 | /* call cpu specific preparation */ | ||
| 740 | |||
| 741 | pm_cpu_prep(); | ||
| 742 | |||
| 743 | /* flush cache back to ram */ | ||
| 744 | |||
| 745 | flush_cache_all(); | ||
| 746 | |||
| 747 | s3c2410_pm_check_store(); | ||
| 748 | |||
| 749 | /* send the cpu to sleep... */ | ||
| 750 | |||
| 751 | __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ | ||
| 752 | |||
| 753 | /* s3c2410_cpu_save will also act as our return point from when | ||
| 754 | * we resume as it saves its own register state, so use the return | ||
| 755 | * code to differentiate return from save and return from sleep */ | ||
| 756 | |||
| 757 | if (s3c2410_cpu_save(regs_save) == 0) { | ||
| 758 | flush_cache_all(); | ||
| 759 | pm_cpu_sleep(); | ||
| 760 | } | ||
| 761 | |||
| 762 | /* restore the cpu state */ | ||
| 763 | |||
| 764 | cpu_init(); | ||
| 765 | |||
| 766 | /* restore the system state */ | ||
| 767 | |||
| 768 | s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save)); | ||
| 769 | s3c2410_pm_do_restore(misc_save, ARRAY_SIZE(misc_save)); | ||
| 770 | s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save)); | ||
| 771 | s3c2410_pm_restore_gpios(); | ||
| 772 | |||
| 773 | s3c2410_pm_debug_init(); | ||
| 774 | |||
| 775 | /* check what irq (if any) restored the system */ | ||
| 776 | |||
| 777 | DBG("post sleep: IRQs 0x%08x, 0x%08x\n", | ||
| 778 | __raw_readl(S3C2410_SRCPND), | ||
| 779 | __raw_readl(S3C2410_EINTPEND)); | ||
| 780 | |||
| 781 | s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), | ||
| 782 | s3c_irqwake_intmask); | ||
| 783 | |||
| 784 | s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), | ||
| 785 | s3c_irqwake_eintmask); | ||
| 786 | |||
| 787 | DBG("post sleep, preparing to return\n"); | ||
| 788 | |||
| 789 | s3c2410_pm_check_restore(); | ||
| 790 | |||
| 791 | /* ok, let's return from sleep */ | ||
| 792 | |||
| 793 | DBG("S3C2410 PM Resume (post-restore)\n"); | ||
| 794 | return 0; | ||
| 795 | } | 353 | } |
| 796 | 354 | ||
| 797 | static struct platform_suspend_ops s3c2410_pm_ops = { | 355 | void s3c_pm_save_core(void) |
| 798 | .enter = s3c2410_pm_enter, | ||
| 799 | .valid = suspend_valid_only_mem, | ||
| 800 | }; | ||
| 801 | |||
| 802 | /* s3c2410_pm_init | ||
| 803 | * | ||
| 804 | * Attach the power management functions. This should be called | ||
| 805 | * from the board specific initialisation if the board supports | ||
| 806 | * it. | ||
| 807 | */ | ||
| 808 | |||
| 809 | int __init s3c2410_pm_init(void) | ||
| 810 | { | 356 | { |
| 811 | printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n"); | 357 | s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save)); |
| 812 | 358 | s3c_pm_do_save(core_save, ARRAY_SIZE(core_save)); | |
| 813 | suspend_set_ops(&s3c2410_pm_ops); | ||
| 814 | return 0; | ||
| 815 | } | 359 | } |
| 360 | |||
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c index c1de6bb0101b..1364317d421e 100644 --- a/arch/arm/plat-s3c24xx/s3c244x.c +++ b/arch/arm/plat-s3c24xx/s3c244x.c | |||
| @@ -145,13 +145,13 @@ static struct sleep_save s3c244x_sleep[] = { | |||
| 145 | 145 | ||
| 146 | static int s3c244x_suspend(struct sys_device *dev, pm_message_t state) | 146 | static int s3c244x_suspend(struct sys_device *dev, pm_message_t state) |
| 147 | { | 147 | { |
| 148 | s3c2410_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); | 148 | s3c_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); |
| 149 | return 0; | 149 | return 0; |
| 150 | } | 150 | } |
| 151 | 151 | ||
| 152 | static int s3c244x_resume(struct sys_device *dev) | 152 | static int s3c244x_resume(struct sys_device *dev) |
| 153 | { | 153 | { |
| 154 | s3c2410_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); | 154 | s3c_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep)); |
| 155 | return 0; | 155 | return 0; |
| 156 | } | 156 | } |
| 157 | 157 | ||
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S index 76594b212802..e73e3b6e88d2 100644 --- a/arch/arm/plat-s3c24xx/sleep.S +++ b/arch/arm/plat-s3c24xx/sleep.S | |||
| @@ -41,25 +41,13 @@ | |||
| 41 | 41 | ||
| 42 | .text | 42 | .text |
| 43 | 43 | ||
| 44 | /* s3c2410_cpu_save | 44 | /* s3c_cpu_save |
| 45 | * | ||
| 46 | * save enough of the CPU state to allow us to re-start | ||
| 47 | * pm.c code. as we store items like the sp/lr, we will | ||
| 48 | * end up returning from this function when the cpu resumes | ||
| 49 | * so the return value is set to mark this. | ||
| 50 | * | ||
| 51 | * This arangement means we avoid having to flush the cache | ||
| 52 | * from this code. | ||
| 53 | * | 45 | * |
| 54 | * entry: | 46 | * entry: |
| 55 | * r0 = pointer to save block | 47 | * r0 = save address (virtual addr of s3c_sleep_save_phys) |
| 56 | * | ||
| 57 | * exit: | ||
| 58 | * r0 = 0 => we stored everything | ||
| 59 | * 1 => resumed from sleep | ||
| 60 | */ | 48 | */ |
| 61 | 49 | ||
| 62 | ENTRY(s3c2410_cpu_save) | 50 | ENTRY(s3c_cpu_save) |
| 63 | stmfd sp!, { r4 - r12, lr } | 51 | stmfd sp!, { r4 - r12, lr } |
| 64 | 52 | ||
| 65 | @@ store co-processor registers | 53 | @@ store co-processor registers |
| @@ -71,20 +59,25 @@ ENTRY(s3c2410_cpu_save) | |||
| 71 | 59 | ||
| 72 | stmia r0, { r4 - r13 } | 60 | stmia r0, { r4 - r13 } |
| 73 | 61 | ||
| 74 | mov r0, #0 | 62 | @@ write our state back to RAM |
| 75 | ldmfd sp, { r4 - r12, pc } | 63 | bl s3c_pm_cb_flushcache |
| 76 | 64 | ||
| 65 | @@ jump to final code to send system to sleep | ||
| 66 | ldr r0, =pm_cpu_sleep | ||
| 67 | @@ldr pc, [ r0 ] | ||
| 68 | ldr r0, [ r0 ] | ||
| 69 | mov pc, r0 | ||
| 70 | |||
| 77 | @@ return to the caller, after having the MMU | 71 | @@ return to the caller, after having the MMU |
| 78 | @@ turned on, this restores the last bits from the | 72 | @@ turned on, this restores the last bits from the |
| 79 | @@ stack | 73 | @@ stack |
| 80 | resume_with_mmu: | 74 | resume_with_mmu: |
| 81 | mov r0, #1 | ||
| 82 | ldmfd sp!, { r4 - r12, pc } | 75 | ldmfd sp!, { r4 - r12, pc } |
| 83 | 76 | ||
| 84 | .ltorg | 77 | .ltorg |
| 85 | 78 | ||
| 86 | @@ the next bits sit in the .data segment, even though they | 79 | @@ the next bits sit in the .data segment, even though they |
| 87 | @@ happen to be code... the s3c2410_sleep_save_phys needs to be | 80 | @@ happen to be code... the s3c_sleep_save_phys needs to be |
| 88 | @@ accessed by the resume code before it can restore the MMU. | 81 | @@ accessed by the resume code before it can restore the MMU. |
| 89 | @@ This means that the variable has to be close enough for the | 82 | @@ This means that the variable has to be close enough for the |
| 90 | @@ code to read it... since the .text segment needs to be RO, | 83 | @@ code to read it... since the .text segment needs to be RO, |
| @@ -92,19 +85,19 @@ resume_with_mmu: | |||
| 92 | 85 | ||
| 93 | .data | 86 | .data |
| 94 | 87 | ||
| 95 | .global s3c2410_sleep_save_phys | 88 | .global s3c_sleep_save_phys |
| 96 | s3c2410_sleep_save_phys: | 89 | s3c_sleep_save_phys: |
| 97 | .word 0 | 90 | .word 0 |
| 98 | 91 | ||
| 99 | 92 | ||
| 100 | /* sleep magic, to allow the bootloader to check for an valid | 93 | /* sleep magic, to allow the bootloader to check for an valid |
| 101 | * image to resume to. Must be the first word before the | 94 | * image to resume to. Must be the first word before the |
| 102 | * s3c2410_cpu_resume entry. | 95 | * s3c_cpu_resume entry. |
| 103 | */ | 96 | */ |
| 104 | 97 | ||
| 105 | .word 0x2bedf00d | 98 | .word 0x2bedf00d |
| 106 | 99 | ||
| 107 | /* s3c2410_cpu_resume | 100 | /* s3c_cpu_resume |
| 108 | * | 101 | * |
| 109 | * resume code entry for bootloader to call | 102 | * resume code entry for bootloader to call |
| 110 | * | 103 | * |
| @@ -113,7 +106,7 @@ s3c2410_sleep_save_phys: | |||
| 113 | * must not write to the code segment (code is read-only) | 106 | * must not write to the code segment (code is read-only) |
| 114 | */ | 107 | */ |
| 115 | 108 | ||
| 116 | ENTRY(s3c2410_cpu_resume) | 109 | ENTRY(s3c_cpu_resume) |
| 117 | mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE | 110 | mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE |
| 118 | msr cpsr_c, r0 | 111 | msr cpsr_c, r0 |
| 119 | 112 | ||
| @@ -145,7 +138,7 @@ ENTRY(s3c2410_cpu_resume) | |||
| 145 | mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs | 138 | mcr p15, 0, r1, c8, c7, 0 @@ invalidate I & D TLBs |
| 146 | mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches | 139 | mcr p15, 0, r1, c7, c7, 0 @@ invalidate I & D caches |
| 147 | 140 | ||
| 148 | ldr r0, s3c2410_sleep_save_phys @ address of restore block | 141 | ldr r0, s3c_sleep_save_phys @ address of restore block |
| 149 | ldmia r0, { r4 - r13 } | 142 | ldmia r0, { r4 - r13 } |
| 150 | 143 | ||
| 151 | mcr p15, 0, r4, c13, c0, 0 @ PID | 144 | mcr p15, 0, r4, c13, c0, 0 @ PID |
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index fd23c0e9e698..945e0d237a1d 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types | |||
| @@ -12,7 +12,7 @@ | |||
| 12 | # | 12 | # |
| 13 | # http://www.arm.linux.org.uk/developer/machines/?action=new | 13 | # http://www.arm.linux.org.uk/developer/machines/?action=new |
| 14 | # | 14 | # |
| 15 | # Last update: Sun Nov 30 16:39:36 2008 | 15 | # Last update: Mon Mar 23 20:09:01 2009 |
| 16 | # | 16 | # |
| 17 | # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number | 17 | # machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number |
| 18 | # | 18 | # |
| @@ -1811,7 +1811,7 @@ pilz_pmi5 MACH_PILZ_PMI5 PILZ_PMI5 1820 | |||
| 1811 | jade MACH_JADE JADE 1821 | 1811 | jade MACH_JADE JADE 1821 |
| 1812 | ks8695_softplc MACH_KS8695_SOFTPLC KS8695_SOFTPLC 1822 | 1812 | ks8695_softplc MACH_KS8695_SOFTPLC KS8695_SOFTPLC 1822 |
| 1813 | gprisc3 MACH_GPRISC3 GPRISC3 1823 | 1813 | gprisc3 MACH_GPRISC3 GPRISC3 1823 |
| 1814 | stamp9260 MACH_STAMP9260 STAMP9260 1824 | 1814 | stamp9g20 MACH_STAMP9G20 STAMP9G20 1824 |
| 1815 | smdk6430 MACH_SMDK6430 SMDK6430 1825 | 1815 | smdk6430 MACH_SMDK6430 SMDK6430 1825 |
| 1816 | smdkc100 MACH_SMDKC100 SMDKC100 1826 | 1816 | smdkc100 MACH_SMDKC100 SMDKC100 1826 |
| 1817 | tavorevb MACH_TAVOREVB TAVOREVB 1827 | 1817 | tavorevb MACH_TAVOREVB TAVOREVB 1827 |
| @@ -1993,4 +1993,142 @@ spark MACH_SPARK SPARK 2002 | |||
| 1993 | benzina MACH_BENZINA BENZINA 2003 | 1993 | benzina MACH_BENZINA BENZINA 2003 |
| 1994 | blaze MACH_BLAZE BLAZE 2004 | 1994 | blaze MACH_BLAZE BLAZE 2004 |
| 1995 | linkstation_ls_hgl MACH_LINKSTATION_LS_HGL LINKSTATION_LS_HGL 2005 | 1995 | linkstation_ls_hgl MACH_LINKSTATION_LS_HGL LINKSTATION_LS_HGL 2005 |
| 1996 | htcvenus MACH_HTCVENUS HTCVENUS 2006 | 1996 | htckovsky MACH_HTCVENUS HTCVENUS 2006 |
| 1997 | sony_prs505 MACH_SONY_PRS505 SONY_PRS505 2007 | ||
| 1998 | hanlin_v3 MACH_HANLIN_V3 HANLIN_V3 2008 | ||
| 1999 | sapphira MACH_SAPPHIRA SAPPHIRA 2009 | ||
| 2000 | dack_sda_01 MACH_DACK_SDA_01 DACK_SDA_01 2010 | ||
| 2001 | armbox MACH_ARMBOX ARMBOX 2011 | ||
| 2002 | harris_rvp MACH_HARRIS_RVP HARRIS_RVP 2012 | ||
| 2003 | ribaldo MACH_RIBALDO RIBALDO 2013 | ||
| 2004 | agora MACH_AGORA AGORA 2014 | ||
| 2005 | omap3_mini MACH_OMAP3_MINI OMAP3_MINI 2015 | ||
| 2006 | a9sam6432_b MACH_A9SAM6432_B A9SAM6432_B 2016 | ||
| 2007 | usg2410 MACH_USG2410 USG2410 2017 | ||
| 2008 | pc72052_i10_revb MACH_PC72052_I10_REVB PC72052_I10_REVB 2018 | ||
| 2009 | mx35_exm32 MACH_MX35_EXM32 MX35_EXM32 2019 | ||
| 2010 | topas910 MACH_TOPAS910 TOPAS910 2020 | ||
| 2011 | hyena MACH_HYENA HYENA 2021 | ||
| 2012 | pospax MACH_POSPAX POSPAX 2022 | ||
| 2013 | hdl_gx MACH_HDL_GX HDL_GX 2023 | ||
| 2014 | ctera_4bay MACH_CTERA_4BAY CTERA_4BAY 2024 | ||
| 2015 | ctera_plug_c MACH_CTERA_PLUG_C CTERA_PLUG_C 2025 | ||
| 2016 | crwea_plug_i MACH_CRWEA_PLUG_I CRWEA_PLUG_I 2026 | ||
| 2017 | egauge2 MACH_EGAUGE2 EGAUGE2 2027 | ||
| 2018 | didj MACH_DIDJ DIDJ 2028 | ||
| 2019 | m_s3c2443 MACH_MEISTER MEISTER 2029 | ||
| 2020 | htcblackstone MACH_HTCBLACKSTONE HTCBLACKSTONE 2030 | ||
| 2021 | cpuat9g20 MACH_CPUAT9G20 CPUAT9G20 2031 | ||
| 2022 | smdk6440 MACH_SMDK6440 SMDK6440 2032 | ||
| 2023 | omap_35xx_mvp MACH_OMAP_35XX_MVP OMAP_35XX_MVP 2033 | ||
| 2024 | ctera_plug_i MACH_CTERA_PLUG_I CTERA_PLUG_I 2034 | ||
| 2025 | pvg610_100 MACH_PVG610 PVG610 2035 | ||
| 2026 | hprw6815 MACH_HPRW6815 HPRW6815 2036 | ||
| 2027 | omap3_oswald MACH_OMAP3_OSWALD OMAP3_OSWALD 2037 | ||
| 2028 | nas4220b MACH_NAS4220B NAS4220B 2038 | ||
| 2029 | htcraphael_cdma MACH_HTCRAPHAEL_CDMA HTCRAPHAEL_CDMA 2039 | ||
| 2030 | htcdiamond_cdma MACH_HTCDIAMOND_CDMA HTCDIAMOND_CDMA 2040 | ||
| 2031 | scaler MACH_SCALER SCALER 2041 | ||
| 2032 | zylonite2 MACH_ZYLONITE2 ZYLONITE2 2042 | ||
| 2033 | aspenite MACH_ASPENITE ASPENITE 2043 | ||
| 2034 | teton MACH_TETON TETON 2044 | ||
| 2035 | ttc_dkb MACH_TTC_DKB TTC_DKB 2045 | ||
| 2036 | bishop2 MACH_BISHOP2 BISHOP2 2046 | ||
| 2037 | ippv5 MACH_IPPV5 IPPV5 2047 | ||
| 2038 | farm926 MACH_FARM926 FARM926 2048 | ||
| 2039 | mmccpu MACH_MMCCPU MMCCPU 2049 | ||
| 2040 | sgmsfl MACH_SGMSFL SGMSFL 2050 | ||
| 2041 | tt8000 MACH_TT8000 TT8000 2051 | ||
| 2042 | zrn4300lp MACH_ZRN4300LP ZRN4300LP 2052 | ||
| 2043 | mptc MACH_MPTC MPTC 2053 | ||
| 2044 | h6051 MACH_H6051 H6051 2054 | ||
| 2045 | pvg610_101 MACH_PVG610_101 PVG610_101 2055 | ||
| 2046 | stamp9261_pc_evb MACH_STAMP9261_PC_EVB STAMP9261_PC_EVB 2056 | ||
| 2047 | pelco_odysseus MACH_PELCO_ODYSSEUS PELCO_ODYSSEUS 2057 | ||
| 2048 | tny_a9260 MACH_TNY_A9260 TNY_A9260 2058 | ||
| 2049 | tny_a9g20 MACH_TNY_A9G20 TNY_A9G20 2059 | ||
| 2050 | aesop_mp2530f MACH_AESOP_MP2530F AESOP_MP2530F 2060 | ||
| 2051 | dx900 MACH_DX900 DX900 2061 | ||
| 2052 | cpodc2 MACH_CPODC2 CPODC2 2062 | ||
| 2053 | tilt_8925 MACH_TILT_8925 TILT_8925 2063 | ||
| 2054 | davinci_dm357_evm MACH_DAVINCI_DM357_EVM DAVINCI_DM357_EVM 2064 | ||
| 2055 | swordfish MACH_SWORDFISH SWORDFISH 2065 | ||
| 2056 | corvus MACH_CORVUS CORVUS 2066 | ||
| 2057 | taurus MACH_TAURUS TAURUS 2067 | ||
| 2058 | axm MACH_AXM AXM 2068 | ||
| 2059 | axc MACH_AXC AXC 2069 | ||
| 2060 | baby MACH_BABY BABY 2070 | ||
| 2061 | mp200 MACH_MP200 MP200 2071 | ||
| 2062 | pcm043 MACH_PCM043 PCM043 2072 | ||
| 2063 | hanlin_v3c MACH_HANLIN_V3C HANLIN_V3C 2073 | ||
| 2064 | kbk9g20 MACH_KBK9G20 KBK9G20 2074 | ||
| 2065 | adsturbog5 MACH_ADSTURBOG5 ADSTURBOG5 2075 | ||
| 2066 | avenger_lite1 MACH_AVENGER_LITE1 AVENGER_LITE1 2076 | ||
| 2067 | suc82x MACH_SUC SUC 2077 | ||
| 2068 | at91sam7s256 MACH_AT91SAM7S256 AT91SAM7S256 2078 | ||
| 2069 | mendoza MACH_MENDOZA MENDOZA 2079 | ||
| 2070 | kira MACH_KIRA KIRA 2080 | ||
| 2071 | mx1hbm MACH_MX1HBM MX1HBM 2081 | ||
| 2072 | quatro43xx MACH_QUATRO43XX QUATRO43XX 2082 | ||
| 2073 | quatro4230 MACH_QUATRO4230 QUATRO4230 2083 | ||
| 2074 | nsb400 MACH_NSB400 NSB400 2084 | ||
| 2075 | drp255 MACH_DRP255 DRP255 2085 | ||
| 2076 | thoth MACH_THOTH THOTH 2086 | ||
| 2077 | firestone MACH_FIRESTONE FIRESTONE 2087 | ||
| 2078 | asusp750 MACH_ASUSP750 ASUSP750 2088 | ||
| 2079 | ctera_dl MACH_CTERA_DL CTERA_DL 2089 | ||
| 2080 | socr MACH_SOCR SOCR 2090 | ||
| 2081 | htcoxygen MACH_HTCOXYGEN HTCOXYGEN 2091 | ||
| 2082 | heroc MACH_HEROC HEROC 2092 | ||
| 2083 | zeno6800 MACH_ZENO6800 ZENO6800 2093 | ||
| 2084 | sc2mcs MACH_SC2MCS SC2MCS 2094 | ||
| 2085 | gene100 MACH_GENE100 GENE100 2095 | ||
| 2086 | as353x MACH_AS353X AS353X 2096 | ||
| 2087 | sheevaplug MACH_SHEEVAPLUG SHEEVAPLUG 2097 | ||
| 2088 | at91sam9g20 MACH_AT91SAM9G20 AT91SAM9G20 2098 | ||
| 2089 | mv88f6192gtw_fe MACH_MV88F6192GTW_FE MV88F6192GTW_FE 2099 | ||
| 2090 | cc9200 MACH_CC9200 CC9200 2100 | ||
| 2091 | sm9200 MACH_SM9200 SM9200 2101 | ||
| 2092 | tp9200 MACH_TP9200 TP9200 2102 | ||
| 2093 | snapperdv MACH_SNAPPERDV SNAPPERDV 2103 | ||
| 2094 | avengers_lite MACH_AVENGERS_LITE AVENGERS_LITE 2104 | ||
| 2095 | avengers_lite1 MACH_AVENGERS_LITE1 AVENGERS_LITE1 2105 | ||
| 2096 | omap3axon MACH_OMAP3AXON OMAP3AXON 2106 | ||
| 2097 | ma8xx MACH_MA8XX MA8XX 2107 | ||
| 2098 | mp201ek MACH_MP201EK MP201EK 2108 | ||
| 2099 | davinci_tux MACH_DAVINCI_TUX DAVINCI_TUX 2109 | ||
| 2100 | mpa1600 MACH_MPA1600 MPA1600 2110 | ||
| 2101 | pelco_troy MACH_PELCO_TROY PELCO_TROY 2111 | ||
| 2102 | nsb667 MACH_NSB667 NSB667 2112 | ||
| 2103 | rovers5_4mpix MACH_ROVERS5_4MPIX ROVERS5_4MPIX 2113 | ||
| 2104 | twocom MACH_TWOCOM TWOCOM 2114 | ||
| 2105 | ubisys_p9_rcu3r2 MACH_UBISYS_P9_RCU3R2 UBISYS_P9_RCU3R2 2115 | ||
| 2106 | hero_espresso MACH_HERO_ESPRESSO HERO_ESPRESSO 2116 | ||
| 2107 | afeusb MACH_AFEUSB AFEUSB 2117 | ||
| 2108 | t830 MACH_T830 T830 2118 | ||
| 2109 | spd8020_cc MACH_SPD8020_CC SPD8020_CC 2119 | ||
| 2110 | om_3d7k MACH_OM_3D7K OM_3D7K 2120 | ||
| 2111 | picocom2 MACH_PICOCOM2 PICOCOM2 2121 | ||
| 2112 | uwg4mx27 MACH_UWG4MX27 UWG4MX27 2122 | ||
| 2113 | uwg4mx31 MACH_UWG4MX31 UWG4MX31 2123 | ||
| 2114 | cherry MACH_CHERRY CHERRY 2124 | ||
| 2115 | mx51_babbage MACH_MX51_BABBAGE MX51_BABBAGE 2125 | ||
| 2116 | s3c2440turkiye MACH_S3C2440TURKIYE S3C2440TURKIYE 2126 | ||
| 2117 | tx37 MACH_TX37 TX37 2127 | ||
| 2118 | sbc2800_9g20 MACH_SBC2800_9G20 SBC2800_9G20 2128 | ||
| 2119 | benzglb MACH_BENZGLB BENZGLB 2129 | ||
| 2120 | benztd MACH_BENZTD BENZTD 2130 | ||
| 2121 | cartesio_plus MACH_CARTESIO_PLUS CARTESIO_PLUS 2131 | ||
| 2122 | solrad_g20 MACH_SOLRAD_G20 SOLRAD_G20 2132 | ||
| 2123 | mx27wallace MACH_MX27WALLACE MX27WALLACE 2133 | ||
| 2124 | fmzwebmodul MACH_FMZWEBMODUL FMZWEBMODUL 2134 | ||
| 2125 | rd78x00_masa MACH_RD78X00_MASA RD78X00_MASA 2135 | ||
| 2126 | smallogger MACH_SMALLOGGER SMALLOGGER 2136 | ||
| 2127 | ccw9p9215 MACH_CCW9P9215 CCW9P9215 2137 | ||
| 2128 | dm355_leopard MACH_DM355_LEOPARD DM355_LEOPARD 2138 | ||
| 2129 | ts219 MACH_TS219 TS219 2139 | ||
| 2130 | tny_a9263 MACH_TNY_A9263 TNY_A9263 2140 | ||
| 2131 | apollo MACH_APOLLO APOLLO 2141 | ||
| 2132 | at91cap9stk MACH_AT91CAP9STK AT91CAP9STK 2142 | ||
| 2133 | spc300 MACH_SPC300 SPC300 2143 | ||
| 2134 | eko MACH_EKO EKO 2144 | ||
diff --git a/arch/arm/vfp/vfp.h b/arch/arm/vfp/vfp.h index 8de86e4feada..c8c98dd44ad4 100644 --- a/arch/arm/vfp/vfp.h +++ b/arch/arm/vfp/vfp.h | |||
| @@ -377,6 +377,4 @@ struct op { | |||
| 377 | u32 flags; | 377 | u32 flags; |
| 378 | }; | 378 | }; |
| 379 | 379 | ||
| 380 | #if defined(CONFIG_SMP) || defined(CONFIG_PM) | ||
| 381 | extern void vfp_save_state(void *location, u32 fpexc); | 380 | extern void vfp_save_state(void *location, u32 fpexc); |
| 382 | #endif | ||
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index c92a08bd6a86..a5a4e57763c3 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S | |||
| @@ -172,7 +172,6 @@ process_exception: | |||
| 172 | @ retry the faulted instruction | 172 | @ retry the faulted instruction |
| 173 | ENDPROC(vfp_support_entry) | 173 | ENDPROC(vfp_support_entry) |
| 174 | 174 | ||
| 175 | #if defined(CONFIG_SMP) || defined(CONFIG_PM) | ||
| 176 | ENTRY(vfp_save_state) | 175 | ENTRY(vfp_save_state) |
| 177 | @ Save the current VFP state | 176 | @ Save the current VFP state |
| 178 | @ r0 - save location | 177 | @ r0 - save location |
| @@ -190,7 +189,6 @@ ENTRY(vfp_save_state) | |||
| 190 | stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2 | 189 | stmia r0, {r1, r2, r3, r12} @ save FPEXC, FPSCR, FPINST, FPINST2 |
| 191 | mov pc, lr | 190 | mov pc, lr |
| 192 | ENDPROC(vfp_save_state) | 191 | ENDPROC(vfp_save_state) |
| 193 | #endif | ||
| 194 | 192 | ||
| 195 | last_VFP_context_address: | 193 | last_VFP_context_address: |
| 196 | .word last_VFP_context | 194 | .word last_VFP_context |
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c index 9f476a1be2ca..75457b30d813 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c | |||
| @@ -377,6 +377,55 @@ static void vfp_pm_init(void) | |||
| 377 | static inline void vfp_pm_init(void) { } | 377 | static inline void vfp_pm_init(void) { } |
| 378 | #endif /* CONFIG_PM */ | 378 | #endif /* CONFIG_PM */ |
| 379 | 379 | ||
| 380 | /* | ||
| 381 | * Synchronise the hardware VFP state of a thread other than current with the | ||
| 382 | * saved one. This function is used by the ptrace mechanism. | ||
| 383 | */ | ||
| 384 | #ifdef CONFIG_SMP | ||
| 385 | void vfp_sync_state(struct thread_info *thread) | ||
| 386 | { | ||
| 387 | /* | ||
| 388 | * On SMP systems, the VFP state is automatically saved at every | ||
| 389 | * context switch. We mark the thread VFP state as belonging to a | ||
| 390 | * non-existent CPU so that the saved one will be reloaded when | ||
| 391 | * needed. | ||
| 392 | */ | ||
| 393 | thread->vfpstate.hard.cpu = NR_CPUS; | ||
| 394 | } | ||
| 395 | #else | ||
| 396 | void vfp_sync_state(struct thread_info *thread) | ||
| 397 | { | ||
| 398 | unsigned int cpu = get_cpu(); | ||
| 399 | u32 fpexc = fmrx(FPEXC); | ||
| 400 | |||
| 401 | /* | ||
| 402 | * If VFP is enabled, the previous state was already saved and | ||
| 403 | * last_VFP_context updated. | ||
| 404 | */ | ||
| 405 | if (fpexc & FPEXC_EN) | ||
| 406 | goto out; | ||
| 407 | |||
| 408 | if (!last_VFP_context[cpu]) | ||
| 409 | goto out; | ||
| 410 | |||
| 411 | /* | ||
| 412 | * Save the last VFP state on this CPU. | ||
| 413 | */ | ||
| 414 | fmxr(FPEXC, fpexc | FPEXC_EN); | ||
| 415 | vfp_save_state(last_VFP_context[cpu], fpexc); | ||
| 416 | fmxr(FPEXC, fpexc); | ||
| 417 | |||
| 418 | /* | ||
| 419 | * Set the context to NULL to force a reload the next time the thread | ||
| 420 | * uses the VFP. | ||
| 421 | */ | ||
| 422 | last_VFP_context[cpu] = NULL; | ||
| 423 | |||
| 424 | out: | ||
| 425 | put_cpu(); | ||
| 426 | } | ||
| 427 | #endif | ||
| 428 | |||
| 380 | #include <linux/smp.h> | 429 | #include <linux/smp.h> |
| 381 | 430 | ||
| 382 | /* | 431 | /* |
| @@ -427,6 +476,18 @@ static int __init vfp_init(void) | |||
| 427 | * in place; report VFP support to userspace. | 476 | * in place; report VFP support to userspace. |
| 428 | */ | 477 | */ |
| 429 | elf_hwcap |= HWCAP_VFP; | 478 | elf_hwcap |= HWCAP_VFP; |
| 479 | #ifdef CONFIG_VFPv3 | ||
| 480 | if (VFP_arch >= 3) { | ||
| 481 | elf_hwcap |= HWCAP_VFPv3; | ||
| 482 | |||
| 483 | /* | ||
| 484 | * Check for VFPv3 D16. CPUs in this configuration | ||
| 485 | * only have 16 x 64bit registers. | ||
| 486 | */ | ||
| 487 | if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK)) == 1) | ||
| 488 | elf_hwcap |= HWCAP_VFPv3D16; | ||
| 489 | } | ||
| 490 | #endif | ||
| 430 | #ifdef CONFIG_NEON | 491 | #ifdef CONFIG_NEON |
| 431 | /* | 492 | /* |
| 432 | * Check for the presence of the Advanced SIMD | 493 | * Check for the presence of the Advanced SIMD |
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig index 8f1f97d56e1e..0c1f86e3e44a 100644 --- a/arch/blackfin/Kconfig +++ b/arch/blackfin/Kconfig | |||
| @@ -1129,6 +1129,7 @@ endchoice | |||
| 1129 | 1129 | ||
| 1130 | config PM_WAKEUP_BY_GPIO | 1130 | config PM_WAKEUP_BY_GPIO |
| 1131 | bool "Allow Wakeup from Standby by GPIO" | 1131 | bool "Allow Wakeup from Standby by GPIO" |
| 1132 | depends on PM && !BF54x | ||
| 1132 | 1133 | ||
| 1133 | config PM_WAKEUP_GPIO_NUMBER | 1134 | config PM_WAKEUP_GPIO_NUMBER |
| 1134 | int "GPIO number" | 1135 | int "GPIO number" |
| @@ -1168,6 +1169,12 @@ config PM_BFIN_WAKE_GP | |||
| 1168 | default n | 1169 | default n |
| 1169 | help | 1170 | help |
| 1170 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) | 1171 | Enable General-Purpose Wake-Up (Voltage Regulator Power-Up) |
| 1172 | (all processors, except ADSP-BF549). This option sets | ||
| 1173 | the general-purpose wake-up enable (GPWE) control bit to enable | ||
| 1174 | wake-up upon detection of an active low signal on the /GPW (PH7) pin. | ||
| 1175 | On ADSP-BF549 this option enables the the same functionality on the | ||
| 1176 | /MRXON pin also PH7. | ||
| 1177 | |||
| 1171 | endmenu | 1178 | endmenu |
| 1172 | 1179 | ||
| 1173 | menu "CPU Frequency scaling" | 1180 | menu "CPU Frequency scaling" |
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug index 5f981d9ca625..79e7e63ab709 100644 --- a/arch/blackfin/Kconfig.debug +++ b/arch/blackfin/Kconfig.debug | |||
| @@ -21,12 +21,6 @@ config DEBUG_STACK_USAGE | |||
| 21 | config HAVE_ARCH_KGDB | 21 | config HAVE_ARCH_KGDB |
| 22 | def_bool y | 22 | def_bool y |
| 23 | 23 | ||
| 24 | config KGDB_TESTCASE | ||
| 25 | tristate "KGDB: for test case in expect" | ||
| 26 | default n | ||
| 27 | help | ||
| 28 | This is a kgdb test case for automated testing. | ||
| 29 | |||
| 30 | config DEBUG_VERBOSE | 24 | config DEBUG_VERBOSE |
| 31 | bool "Verbose fault messages" | 25 | bool "Verbose fault messages" |
| 32 | default y | 26 | default y |
diff --git a/arch/blackfin/configs/BF518F-EZBRD_defconfig b/arch/blackfin/configs/BF518F-EZBRD_defconfig index 4fdb9e04759f..281f4b60e603 100644 --- a/arch/blackfin/configs/BF518F-EZBRD_defconfig +++ b/arch/blackfin/configs/BF518F-EZBRD_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.28-rc2 | 3 | # Linux kernel version: 2.6.28 |
| 4 | # Fri Jan 9 17:58:41 2009 | 4 | # Fri Feb 20 10:01:44 2009 |
| 5 | # | 5 | # |
| 6 | # CONFIG_MMU is not set | 6 | # CONFIG_MMU is not set |
| 7 | # CONFIG_FPU is not set | 7 | # CONFIG_FPU is not set |
| @@ -133,10 +133,15 @@ CONFIG_BF518=y | |||
| 133 | # CONFIG_BF538 is not set | 133 | # CONFIG_BF538 is not set |
| 134 | # CONFIG_BF539 is not set | 134 | # CONFIG_BF539 is not set |
| 135 | # CONFIG_BF542 is not set | 135 | # CONFIG_BF542 is not set |
| 136 | # CONFIG_BF542M is not set | ||
| 136 | # CONFIG_BF544 is not set | 137 | # CONFIG_BF544 is not set |
| 138 | # CONFIG_BF544M is not set | ||
| 137 | # CONFIG_BF547 is not set | 139 | # CONFIG_BF547 is not set |
| 140 | # CONFIG_BF547M is not set | ||
| 138 | # CONFIG_BF548 is not set | 141 | # CONFIG_BF548 is not set |
| 142 | # CONFIG_BF548M is not set | ||
| 139 | # CONFIG_BF549 is not set | 143 | # CONFIG_BF549 is not set |
| 144 | # CONFIG_BF549M is not set | ||
| 140 | # CONFIG_BF561 is not set | 145 | # CONFIG_BF561 is not set |
| 141 | CONFIG_BF_REV_MIN=0 | 146 | CONFIG_BF_REV_MIN=0 |
| 142 | CONFIG_BF_REV_MAX=2 | 147 | CONFIG_BF_REV_MAX=2 |
| @@ -426,7 +431,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 426 | # CONFIG_TIPC is not set | 431 | # CONFIG_TIPC is not set |
| 427 | # CONFIG_ATM is not set | 432 | # CONFIG_ATM is not set |
| 428 | # CONFIG_BRIDGE is not set | 433 | # CONFIG_BRIDGE is not set |
| 429 | # CONFIG_NET_DSA is not set | 434 | CONFIG_NET_DSA=y |
| 435 | # CONFIG_NET_DSA_TAG_DSA is not set | ||
| 436 | # CONFIG_NET_DSA_TAG_EDSA is not set | ||
| 437 | # CONFIG_NET_DSA_TAG_TRAILER is not set | ||
| 438 | CONFIG_NET_DSA_TAG_STPID=y | ||
| 439 | # CONFIG_NET_DSA_MV88E6XXX is not set | ||
| 440 | # CONFIG_NET_DSA_MV88E6060 is not set | ||
| 441 | # CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set | ||
| 442 | # CONFIG_NET_DSA_MV88E6131 is not set | ||
| 443 | # CONFIG_NET_DSA_MV88E6123_61_65 is not set | ||
| 444 | CONFIG_NET_DSA_KSZ8893M=y | ||
| 430 | # CONFIG_VLAN_8021Q is not set | 445 | # CONFIG_VLAN_8021Q is not set |
| 431 | # CONFIG_DECNET is not set | 446 | # CONFIG_DECNET is not set |
| 432 | # CONFIG_LLC2 is not set | 447 | # CONFIG_LLC2 is not set |
| @@ -529,6 +544,8 @@ CONFIG_MTD_COMPLEX_MAPPINGS=y | |||
| 529 | # | 544 | # |
| 530 | # Self-contained MTD device drivers | 545 | # Self-contained MTD device drivers |
| 531 | # | 546 | # |
| 547 | # CONFIG_MTD_DATAFLASH is not set | ||
| 548 | # CONFIG_MTD_M25P80 is not set | ||
| 532 | # CONFIG_MTD_SLRAM is not set | 549 | # CONFIG_MTD_SLRAM is not set |
| 533 | # CONFIG_MTD_PHRAM is not set | 550 | # CONFIG_MTD_PHRAM is not set |
| 534 | # CONFIG_MTD_MTDRAM is not set | 551 | # CONFIG_MTD_MTDRAM is not set |
| @@ -561,7 +578,9 @@ CONFIG_BLK_DEV_RAM_SIZE=4096 | |||
| 561 | # CONFIG_BLK_DEV_HD is not set | 578 | # CONFIG_BLK_DEV_HD is not set |
| 562 | CONFIG_MISC_DEVICES=y | 579 | CONFIG_MISC_DEVICES=y |
| 563 | # CONFIG_EEPROM_93CX6 is not set | 580 | # CONFIG_EEPROM_93CX6 is not set |
| 581 | # CONFIG_ICS932S401 is not set | ||
| 564 | # CONFIG_ENCLOSURE_SERVICES is not set | 582 | # CONFIG_ENCLOSURE_SERVICES is not set |
| 583 | # CONFIG_C2PORT is not set | ||
| 565 | CONFIG_HAVE_IDE=y | 584 | CONFIG_HAVE_IDE=y |
| 566 | # CONFIG_IDE is not set | 585 | # CONFIG_IDE is not set |
| 567 | 586 | ||
| @@ -607,6 +626,7 @@ CONFIG_BFIN_RX_DESC_NUM=20 | |||
| 607 | # CONFIG_SMC91X is not set | 626 | # CONFIG_SMC91X is not set |
| 608 | # CONFIG_SMSC911X is not set | 627 | # CONFIG_SMSC911X is not set |
| 609 | # CONFIG_DM9000 is not set | 628 | # CONFIG_DM9000 is not set |
| 629 | # CONFIG_ENC28J60 is not set | ||
| 610 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | 630 | # CONFIG_IBM_NEW_EMAC_ZMII is not set |
| 611 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 631 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 612 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 632 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| @@ -764,7 +784,23 @@ CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100 | |||
| 764 | # CONFIG_I2C_DEBUG_ALGO is not set | 784 | # CONFIG_I2C_DEBUG_ALGO is not set |
| 765 | # CONFIG_I2C_DEBUG_BUS is not set | 785 | # CONFIG_I2C_DEBUG_BUS is not set |
| 766 | # CONFIG_I2C_DEBUG_CHIP is not set | 786 | # CONFIG_I2C_DEBUG_CHIP is not set |
| 767 | # CONFIG_SPI is not set | 787 | CONFIG_SPI=y |
| 788 | # CONFIG_SPI_DEBUG is not set | ||
| 789 | CONFIG_SPI_MASTER=y | ||
| 790 | |||
| 791 | # | ||
| 792 | # SPI Master Controller Drivers | ||
| 793 | # | ||
| 794 | CONFIG_SPI_BFIN=y | ||
| 795 | # CONFIG_SPI_BFIN_LOCK is not set | ||
| 796 | # CONFIG_SPI_BITBANG is not set | ||
| 797 | |||
| 798 | # | ||
| 799 | # SPI Protocol Masters | ||
| 800 | # | ||
| 801 | # CONFIG_SPI_AT25 is not set | ||
| 802 | # CONFIG_SPI_SPIDEV is not set | ||
| 803 | # CONFIG_SPI_TLE62X0 is not set | ||
| 768 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | 804 | CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y |
| 769 | # CONFIG_GPIOLIB is not set | 805 | # CONFIG_GPIOLIB is not set |
| 770 | # CONFIG_W1 is not set | 806 | # CONFIG_W1 is not set |
| @@ -788,8 +824,10 @@ CONFIG_BFIN_WDT=y | |||
| 788 | # CONFIG_MFD_SM501 is not set | 824 | # CONFIG_MFD_SM501 is not set |
| 789 | # CONFIG_HTC_PASIC3 is not set | 825 | # CONFIG_HTC_PASIC3 is not set |
| 790 | # CONFIG_MFD_TMIO is not set | 826 | # CONFIG_MFD_TMIO is not set |
| 827 | # CONFIG_PMIC_DA903X is not set | ||
| 791 | # CONFIG_MFD_WM8400 is not set | 828 | # CONFIG_MFD_WM8400 is not set |
| 792 | # CONFIG_MFD_WM8350_I2C is not set | 829 | # CONFIG_MFD_WM8350_I2C is not set |
| 830 | # CONFIG_REGULATOR is not set | ||
| 793 | 831 | ||
| 794 | # | 832 | # |
| 795 | # Multimedia devices | 833 | # Multimedia devices |
| @@ -861,10 +899,18 @@ CONFIG_RTC_INTF_DEV=y | |||
| 861 | # CONFIG_RTC_DRV_M41T80 is not set | 899 | # CONFIG_RTC_DRV_M41T80 is not set |
| 862 | # CONFIG_RTC_DRV_S35390A is not set | 900 | # CONFIG_RTC_DRV_S35390A is not set |
| 863 | # CONFIG_RTC_DRV_FM3130 is not set | 901 | # CONFIG_RTC_DRV_FM3130 is not set |
| 902 | # CONFIG_RTC_DRV_RX8581 is not set | ||
| 864 | 903 | ||
| 865 | # | 904 | # |
| 866 | # SPI RTC drivers | 905 | # SPI RTC drivers |
| 867 | # | 906 | # |
| 907 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 908 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 909 | # CONFIG_RTC_DRV_DS1390 is not set | ||
| 910 | # CONFIG_RTC_DRV_MAX6902 is not set | ||
| 911 | # CONFIG_RTC_DRV_R9701 is not set | ||
| 912 | # CONFIG_RTC_DRV_RS5C348 is not set | ||
| 913 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 868 | 914 | ||
| 869 | # | 915 | # |
| 870 | # Platform RTC drivers | 916 | # Platform RTC drivers |
| @@ -1062,12 +1108,20 @@ CONFIG_DEBUG_INFO=y | |||
| 1062 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | 1108 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set |
| 1063 | # CONFIG_FAULT_INJECTION is not set | 1109 | # CONFIG_FAULT_INJECTION is not set |
| 1064 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 1110 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 1111 | |||
| 1112 | # | ||
| 1113 | # Tracers | ||
| 1114 | # | ||
| 1115 | # CONFIG_SCHED_TRACER is not set | ||
| 1116 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1117 | # CONFIG_BOOT_TRACER is not set | ||
| 1065 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | 1118 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set |
| 1066 | # CONFIG_SAMPLES is not set | 1119 | # CONFIG_SAMPLES is not set |
| 1067 | CONFIG_HAVE_ARCH_KGDB=y | 1120 | CONFIG_HAVE_ARCH_KGDB=y |
| 1068 | # CONFIG_KGDB is not set | 1121 | # CONFIG_KGDB is not set |
| 1069 | # CONFIG_DEBUG_STACKOVERFLOW is not set | 1122 | # CONFIG_DEBUG_STACKOVERFLOW is not set |
| 1070 | # CONFIG_DEBUG_STACK_USAGE is not set | 1123 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 1124 | # CONFIG_KGDB_TESTCASE is not set | ||
| 1071 | CONFIG_DEBUG_VERBOSE=y | 1125 | CONFIG_DEBUG_VERBOSE=y |
| 1072 | CONFIG_DEBUG_MMRS=y | 1126 | CONFIG_DEBUG_MMRS=y |
| 1073 | # CONFIG_DEBUG_HWERR is not set | 1127 | # CONFIG_DEBUG_HWERR is not set |
| @@ -1100,6 +1154,7 @@ CONFIG_CRYPTO=y | |||
| 1100 | # | 1154 | # |
| 1101 | # CONFIG_CRYPTO_FIPS is not set | 1155 | # CONFIG_CRYPTO_FIPS is not set |
| 1102 | # CONFIG_CRYPTO_MANAGER is not set | 1156 | # CONFIG_CRYPTO_MANAGER is not set |
| 1157 | # CONFIG_CRYPTO_MANAGER2 is not set | ||
| 1103 | # CONFIG_CRYPTO_GF128MUL is not set | 1158 | # CONFIG_CRYPTO_GF128MUL is not set |
| 1104 | # CONFIG_CRYPTO_NULL is not set | 1159 | # CONFIG_CRYPTO_NULL is not set |
| 1105 | # CONFIG_CRYPTO_CRYPTD is not set | 1160 | # CONFIG_CRYPTO_CRYPTD is not set |
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig index 833128b39724..a50050f17706 100644 --- a/arch/blackfin/configs/BF527-EZKIT_defconfig +++ b/arch/blackfin/configs/BF527-EZKIT_defconfig | |||
| @@ -327,8 +327,8 @@ CONFIG_BFIN_ICACHE=y | |||
| 327 | CONFIG_BFIN_DCACHE=y | 327 | CONFIG_BFIN_DCACHE=y |
| 328 | # CONFIG_BFIN_DCACHE_BANKA is not set | 328 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 329 | # CONFIG_BFIN_ICACHE_LOCK is not set | 329 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 330 | # CONFIG_BFIN_WB is not set | 330 | CONFIG_BFIN_WB=y |
| 331 | CONFIG_BFIN_WT=y | 331 | # CONFIG_BFIN_WT is not set |
| 332 | # CONFIG_MPU is not set | 332 | # CONFIG_MPU is not set |
| 333 | 333 | ||
| 334 | # | 334 | # |
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig index 334c94b51c40..0a2a00d63887 100644 --- a/arch/blackfin/configs/BF533-EZKIT_defconfig +++ b/arch/blackfin/configs/BF533-EZKIT_defconfig | |||
| @@ -290,8 +290,8 @@ CONFIG_BFIN_ICACHE=y | |||
| 290 | CONFIG_BFIN_DCACHE=y | 290 | CONFIG_BFIN_DCACHE=y |
| 291 | # CONFIG_BFIN_DCACHE_BANKA is not set | 291 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 292 | # CONFIG_BFIN_ICACHE_LOCK is not set | 292 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 293 | # CONFIG_BFIN_WB is not set | 293 | CONFIG_BFIN_WB=y |
| 294 | CONFIG_BFIN_WT=y | 294 | # CONFIG_BFIN_WT is not set |
| 295 | # CONFIG_MPU is not set | 295 | # CONFIG_MPU is not set |
| 296 | 296 | ||
| 297 | # | 297 | # |
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig index 9d733436e300..eb027587a355 100644 --- a/arch/blackfin/configs/BF533-STAMP_defconfig +++ b/arch/blackfin/configs/BF533-STAMP_defconfig | |||
| @@ -290,8 +290,8 @@ CONFIG_BFIN_ICACHE=y | |||
| 290 | CONFIG_BFIN_DCACHE=y | 290 | CONFIG_BFIN_DCACHE=y |
| 291 | # CONFIG_BFIN_DCACHE_BANKA is not set | 291 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 292 | # CONFIG_BFIN_ICACHE_LOCK is not set | 292 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 293 | # CONFIG_BFIN_WB is not set | 293 | CONFIG_BFIN_WB=y |
| 294 | CONFIG_BFIN_WT=y | 294 | # CONFIG_BFIN_WT is not set |
| 295 | # CONFIG_MPU is not set | 295 | # CONFIG_MPU is not set |
| 296 | 296 | ||
| 297 | # | 297 | # |
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig index 4fb4108d3103..9e62b9f40eb1 100644 --- a/arch/blackfin/configs/BF537-STAMP_defconfig +++ b/arch/blackfin/configs/BF537-STAMP_defconfig | |||
| @@ -298,8 +298,8 @@ CONFIG_BFIN_ICACHE=y | |||
| 298 | CONFIG_BFIN_DCACHE=y | 298 | CONFIG_BFIN_DCACHE=y |
| 299 | # CONFIG_BFIN_DCACHE_BANKA is not set | 299 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 300 | # CONFIG_BFIN_ICACHE_LOCK is not set | 300 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 301 | # CONFIG_BFIN_WB is not set | 301 | CONFIG_BFIN_WB=y |
| 302 | CONFIG_BFIN_WT=y | 302 | # CONFIG_BFIN_WT is not set |
| 303 | # CONFIG_MPU is not set | 303 | # CONFIG_MPU is not set |
| 304 | 304 | ||
| 305 | # | 305 | # |
| @@ -568,15 +568,7 @@ CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | |||
| 568 | # CONFIG_MTD_DOC2000 is not set | 568 | # CONFIG_MTD_DOC2000 is not set |
| 569 | # CONFIG_MTD_DOC2001 is not set | 569 | # CONFIG_MTD_DOC2001 is not set |
| 570 | # CONFIG_MTD_DOC2001PLUS is not set | 570 | # CONFIG_MTD_DOC2001PLUS is not set |
| 571 | CONFIG_MTD_NAND=m | 571 | # CONFIG_MTD_NAND is not set |
| 572 | # CONFIG_MTD_NAND_VERIFY_WRITE is not set | ||
| 573 | # CONFIG_MTD_NAND_ECC_SMC is not set | ||
| 574 | # CONFIG_MTD_NAND_MUSEUM_IDS is not set | ||
| 575 | # CONFIG_MTD_NAND_BFIN is not set | ||
| 576 | CONFIG_MTD_NAND_IDS=m | ||
| 577 | # CONFIG_MTD_NAND_DISKONCHIP is not set | ||
| 578 | # CONFIG_MTD_NAND_NANDSIM is not set | ||
| 579 | CONFIG_MTD_NAND_PLATFORM=m | ||
| 580 | # CONFIG_MTD_ONENAND is not set | 572 | # CONFIG_MTD_ONENAND is not set |
| 581 | 573 | ||
| 582 | # | 574 | # |
diff --git a/arch/blackfin/configs/BF538-EZKIT_defconfig b/arch/blackfin/configs/BF538-EZKIT_defconfig index cb32f5624a1b..dd6ad6be1c87 100644 --- a/arch/blackfin/configs/BF538-EZKIT_defconfig +++ b/arch/blackfin/configs/BF538-EZKIT_defconfig | |||
| @@ -306,8 +306,8 @@ CONFIG_BFIN_ICACHE=y | |||
| 306 | CONFIG_BFIN_DCACHE=y | 306 | CONFIG_BFIN_DCACHE=y |
| 307 | # CONFIG_BFIN_DCACHE_BANKA is not set | 307 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 308 | # CONFIG_BFIN_ICACHE_LOCK is not set | 308 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 309 | # CONFIG_BFIN_WB is not set | 309 | CONFIG_BFIN_WB=y |
| 310 | CONFIG_BFIN_WT=y | 310 | # CONFIG_BFIN_WT is not set |
| 311 | # CONFIG_MPU is not set | 311 | # CONFIG_MPU is not set |
| 312 | 312 | ||
| 313 | # | 313 | # |
diff --git a/arch/blackfin/configs/BF548-EZKIT_defconfig b/arch/blackfin/configs/BF548-EZKIT_defconfig index 0f8697618aa5..6bc2fb1b2a70 100644 --- a/arch/blackfin/configs/BF548-EZKIT_defconfig +++ b/arch/blackfin/configs/BF548-EZKIT_defconfig | |||
| @@ -361,8 +361,8 @@ CONFIG_BFIN_ICACHE=y | |||
| 361 | CONFIG_BFIN_DCACHE=y | 361 | CONFIG_BFIN_DCACHE=y |
| 362 | # CONFIG_BFIN_DCACHE_BANKA is not set | 362 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 363 | # CONFIG_BFIN_ICACHE_LOCK is not set | 363 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 364 | # CONFIG_BFIN_WB is not set | 364 | CONFIG_BFIN_WB=y |
| 365 | CONFIG_BFIN_WT=y | 365 | # CONFIG_BFIN_WT is not set |
| 366 | # CONFIG_BFIN_L2_CACHEABLE is not set | 366 | # CONFIG_BFIN_L2_CACHEABLE is not set |
| 367 | # CONFIG_MPU is not set | 367 | # CONFIG_MPU is not set |
| 368 | 368 | ||
| @@ -680,7 +680,7 @@ CONFIG_SCSI=y | |||
| 680 | CONFIG_SCSI_DMA=y | 680 | CONFIG_SCSI_DMA=y |
| 681 | # CONFIG_SCSI_TGT is not set | 681 | # CONFIG_SCSI_TGT is not set |
| 682 | # CONFIG_SCSI_NETLINK is not set | 682 | # CONFIG_SCSI_NETLINK is not set |
| 683 | CONFIG_SCSI_PROC_FS=y | 683 | # CONFIG_SCSI_PROC_FS is not set |
| 684 | 684 | ||
| 685 | # | 685 | # |
| 686 | # SCSI support type (disk, tape, CD-ROM) | 686 | # SCSI support type (disk, tape, CD-ROM) |
diff --git a/arch/blackfin/configs/BF561-EZKIT_defconfig b/arch/blackfin/configs/BF561-EZKIT_defconfig index 042c7adfccfa..69714fb3e608 100644 --- a/arch/blackfin/configs/BF561-EZKIT_defconfig +++ b/arch/blackfin/configs/BF561-EZKIT_defconfig | |||
| @@ -329,8 +329,8 @@ CONFIG_BFIN_ICACHE=y | |||
| 329 | CONFIG_BFIN_DCACHE=y | 329 | CONFIG_BFIN_DCACHE=y |
| 330 | # CONFIG_BFIN_DCACHE_BANKA is not set | 330 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 331 | # CONFIG_BFIN_ICACHE_LOCK is not set | 331 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 332 | # CONFIG_BFIN_WB is not set | 332 | CONFIG_BFIN_WB=y |
| 333 | CONFIG_BFIN_WT=y | 333 | # CONFIG_BFIN_WT is not set |
| 334 | # CONFIG_BFIN_L2_CACHEABLE is not set | 334 | # CONFIG_BFIN_L2_CACHEABLE is not set |
| 335 | # CONFIG_MPU is not set | 335 | # CONFIG_MPU is not set |
| 336 | 336 | ||
diff --git a/arch/blackfin/configs/BlackStamp_defconfig b/arch/blackfin/configs/BlackStamp_defconfig index 3a20e281d23c..017c6ea071b5 100644 --- a/arch/blackfin/configs/BlackStamp_defconfig +++ b/arch/blackfin/configs/BlackStamp_defconfig | |||
| @@ -288,8 +288,8 @@ CONFIG_BFIN_ICACHE=y | |||
| 288 | CONFIG_BFIN_DCACHE=y | 288 | CONFIG_BFIN_DCACHE=y |
| 289 | # CONFIG_BFIN_DCACHE_BANKA is not set | 289 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 290 | # CONFIG_BFIN_ICACHE_LOCK is not set | 290 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 291 | # CONFIG_BFIN_WB is not set | 291 | CONFIG_BFIN_WB=y |
| 292 | CONFIG_BFIN_WT=y | 292 | # CONFIG_BFIN_WT is not set |
| 293 | # CONFIG_MPU is not set | 293 | # CONFIG_MPU is not set |
| 294 | 294 | ||
| 295 | # | 295 | # |
diff --git a/arch/blackfin/configs/CM-BF527_defconfig b/arch/blackfin/configs/CM-BF527_defconfig index 865ed85a5760..d880ef786770 100644 --- a/arch/blackfin/configs/CM-BF527_defconfig +++ b/arch/blackfin/configs/CM-BF527_defconfig | |||
| @@ -332,8 +332,8 @@ CONFIG_BFIN_ICACHE=y | |||
| 332 | CONFIG_BFIN_DCACHE=y | 332 | CONFIG_BFIN_DCACHE=y |
| 333 | # CONFIG_BFIN_DCACHE_BANKA is not set | 333 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 334 | # CONFIG_BFIN_ICACHE_LOCK is not set | 334 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 335 | # CONFIG_BFIN_WB is not set | 335 | CONFIG_BFIN_WB=y |
| 336 | CONFIG_BFIN_WT=y | 336 | # CONFIG_BFIN_WT is not set |
| 337 | # CONFIG_MPU is not set | 337 | # CONFIG_MPU is not set |
| 338 | 338 | ||
| 339 | # | 339 | # |
diff --git a/arch/blackfin/configs/CM-BF548_defconfig b/arch/blackfin/configs/CM-BF548_defconfig index efe9741b1f14..f410430b4e3d 100644 --- a/arch/blackfin/configs/CM-BF548_defconfig +++ b/arch/blackfin/configs/CM-BF548_defconfig | |||
| @@ -336,8 +336,8 @@ CONFIG_BFIN_ICACHE=y | |||
| 336 | CONFIG_BFIN_DCACHE=y | 336 | CONFIG_BFIN_DCACHE=y |
| 337 | # CONFIG_BFIN_DCACHE_BANKA is not set | 337 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 338 | # CONFIG_BFIN_ICACHE_LOCK is not set | 338 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 339 | # CONFIG_BFIN_WB is not set | 339 | CONFIG_BFIN_WB=y |
| 340 | CONFIG_BFIN_WT=y | 340 | # CONFIG_BFIN_WT is not set |
| 341 | CONFIG_L1_MAX_PIECE=16 | 341 | CONFIG_L1_MAX_PIECE=16 |
| 342 | # CONFIG_MPU is not set | 342 | # CONFIG_MPU is not set |
| 343 | 343 | ||
| @@ -595,7 +595,7 @@ CONFIG_SCSI=y | |||
| 595 | CONFIG_SCSI_DMA=y | 595 | CONFIG_SCSI_DMA=y |
| 596 | # CONFIG_SCSI_TGT is not set | 596 | # CONFIG_SCSI_TGT is not set |
| 597 | # CONFIG_SCSI_NETLINK is not set | 597 | # CONFIG_SCSI_NETLINK is not set |
| 598 | CONFIG_SCSI_PROC_FS=y | 598 | # CONFIG_SCSI_PROC_FS is not set |
| 599 | 599 | ||
| 600 | # | 600 | # |
| 601 | # SCSI support type (disk, tape, CD-ROM) | 601 | # SCSI support type (disk, tape, CD-ROM) |
diff --git a/arch/blackfin/configs/IP0X_defconfig b/arch/blackfin/configs/IP0X_defconfig index eae83b5de92f..7db93874c987 100644 --- a/arch/blackfin/configs/IP0X_defconfig +++ b/arch/blackfin/configs/IP0X_defconfig | |||
| @@ -612,7 +612,7 @@ CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | |||
| 612 | CONFIG_SCSI=y | 612 | CONFIG_SCSI=y |
| 613 | # CONFIG_SCSI_TGT is not set | 613 | # CONFIG_SCSI_TGT is not set |
| 614 | # CONFIG_SCSI_NETLINK is not set | 614 | # CONFIG_SCSI_NETLINK is not set |
| 615 | CONFIG_SCSI_PROC_FS=y | 615 | # CONFIG_SCSI_PROC_FS is not set |
| 616 | 616 | ||
| 617 | # | 617 | # |
| 618 | # SCSI support type (disk, tape, CD-ROM) | 618 | # SCSI support type (disk, tape, CD-ROM) |
diff --git a/arch/blackfin/configs/SRV1_defconfig b/arch/blackfin/configs/SRV1_defconfig index fa580affc9d6..a46529c6ade3 100644 --- a/arch/blackfin/configs/SRV1_defconfig +++ b/arch/blackfin/configs/SRV1_defconfig | |||
| @@ -282,8 +282,8 @@ CONFIG_BFIN_ICACHE=y | |||
| 282 | CONFIG_BFIN_DCACHE=y | 282 | CONFIG_BFIN_DCACHE=y |
| 283 | # CONFIG_BFIN_DCACHE_BANKA is not set | 283 | # CONFIG_BFIN_DCACHE_BANKA is not set |
| 284 | # CONFIG_BFIN_ICACHE_LOCK is not set | 284 | # CONFIG_BFIN_ICACHE_LOCK is not set |
| 285 | # CONFIG_BFIN_WB is not set | 285 | CONFIG_BFIN_WB=y |
| 286 | CONFIG_BFIN_WT=y | 286 | # CONFIG_BFIN_WT is not set |
| 287 | CONFIG_L1_MAX_PIECE=16 | 287 | CONFIG_L1_MAX_PIECE=16 |
| 288 | 288 | ||
| 289 | # | 289 | # |
diff --git a/arch/blackfin/include/asm/Kbuild b/arch/blackfin/include/asm/Kbuild index 606ecfdcc962..09c31418cc08 100644 --- a/arch/blackfin/include/asm/Kbuild +++ b/arch/blackfin/include/asm/Kbuild | |||
| @@ -1,3 +1,4 @@ | |||
| 1 | include include/asm-generic/Kbuild.asm | 1 | include include/asm-generic/Kbuild.asm |
| 2 | 2 | ||
| 3 | unifdef-y += bfin_sport.h | ||
| 3 | unifdef-y += fixed_code.h | 4 | unifdef-y += fixed_code.h |
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h index fe88a2c19213..65a651db5b07 100644 --- a/arch/blackfin/include/asm/bfin_sport.h +++ b/arch/blackfin/include/asm/bfin_sport.h | |||
| @@ -1,30 +1,9 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * File: include/asm-blackfin/bfin_sport.h | 2 | * bfin_sport.h - userspace header for bfin sport driver |
| 3 | * Based on: | ||
| 4 | * Author: Roy Huang (roy.huang@analog.com) | ||
| 5 | * | 3 | * |
| 6 | * Created: Thu Aug. 24 2006 | 4 | * Copyright 2004-2008 Analog Devices Inc. |
| 7 | * Description: | ||
| 8 | * | 5 | * |
| 9 | * Modified: | 6 | * Licensed under the GPL-2 or later. |
| 10 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 11 | * | ||
| 12 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 13 | * | ||
| 14 | * This program is free software; you can redistribute it and/or modify | ||
| 15 | * it under the terms of the GNU General Public License as published by | ||
| 16 | * the Free Software Foundation; either version 2 of the License, or | ||
| 17 | * (at your option) any later version. | ||
| 18 | * | ||
| 19 | * This program is distributed in the hope that it will be useful, | ||
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 22 | * GNU General Public License for more details. | ||
| 23 | * | ||
| 24 | * You should have received a copy of the GNU General Public License | ||
| 25 | * along with this program; if not, see the file COPYING, or write | ||
| 26 | * to the Free Software Foundation, Inc., | ||
| 27 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 28 | */ | 7 | */ |
| 29 | 8 | ||
| 30 | #ifndef __BFIN_SPORT_H__ | 9 | #ifndef __BFIN_SPORT_H__ |
| @@ -42,11 +21,10 @@ | |||
| 42 | #define NORM_FORMAT 0x0 | 21 | #define NORM_FORMAT 0x0 |
| 43 | #define ALAW_FORMAT 0x2 | 22 | #define ALAW_FORMAT 0x2 |
| 44 | #define ULAW_FORMAT 0x3 | 23 | #define ULAW_FORMAT 0x3 |
| 45 | struct sport_register; | ||
| 46 | 24 | ||
| 47 | /* Function driver which use sport must initialize the structure */ | 25 | /* Function driver which use sport must initialize the structure */ |
| 48 | struct sport_config { | 26 | struct sport_config { |
| 49 | /*TDM (multichannels), I2S or other mode */ | 27 | /* TDM (multichannels), I2S or other mode */ |
| 50 | unsigned int mode:3; | 28 | unsigned int mode:3; |
| 51 | 29 | ||
| 52 | /* if TDM mode is selected, channels must be set */ | 30 | /* if TDM mode is selected, channels must be set */ |
| @@ -72,12 +50,18 @@ struct sport_config { | |||
| 72 | int serial_clk; | 50 | int serial_clk; |
| 73 | int fsync_clk; | 51 | int fsync_clk; |
| 74 | 52 | ||
| 75 | unsigned int data_format:2; /*Normal, u-law or a-law */ | 53 | unsigned int data_format:2; /* Normal, u-law or a-law */ |
| 76 | 54 | ||
| 77 | int word_len; /* How length of the word in bits, 3-32 bits */ | 55 | int word_len; /* How length of the word in bits, 3-32 bits */ |
| 78 | int dma_enabled; | 56 | int dma_enabled; |
| 79 | }; | 57 | }; |
| 80 | 58 | ||
| 59 | /* Userspace interface */ | ||
| 60 | #define SPORT_IOC_MAGIC 'P' | ||
| 61 | #define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config) | ||
| 62 | |||
| 63 | #ifdef __KERNEL__ | ||
| 64 | |||
| 81 | struct sport_register { | 65 | struct sport_register { |
| 82 | unsigned short tcr1; | 66 | unsigned short tcr1; |
| 83 | unsigned short reserved0; | 67 | unsigned short reserved0; |
| @@ -117,9 +101,6 @@ struct sport_register { | |||
| 117 | unsigned long mrcs3; | 101 | unsigned long mrcs3; |
| 118 | }; | 102 | }; |
| 119 | 103 | ||
| 120 | #define SPORT_IOC_MAGIC 'P' | ||
| 121 | #define SPORT_IOC_CONFIG _IOWR('P', 0x01, struct sport_config) | ||
| 122 | |||
| 123 | struct sport_dev { | 104 | struct sport_dev { |
| 124 | struct cdev cdev; /* Char device structure */ | 105 | struct cdev cdev; /* Char device structure */ |
| 125 | 106 | ||
| @@ -149,6 +130,8 @@ struct sport_dev { | |||
| 149 | struct sport_config config; | 130 | struct sport_config config; |
| 150 | }; | 131 | }; |
| 151 | 132 | ||
| 133 | #endif | ||
| 134 | |||
| 152 | #define SPORT_TCR1 0 | 135 | #define SPORT_TCR1 0 |
| 153 | #define SPORT_TCR2 1 | 136 | #define SPORT_TCR2 1 |
| 154 | #define SPORT_TCLKDIV 2 | 137 | #define SPORT_TCLKDIV 2 |
| @@ -169,4 +152,4 @@ struct sport_dev { | |||
| 169 | #define SPORT_MRCS2 22 | 152 | #define SPORT_MRCS2 22 |
| 170 | #define SPORT_MRCS3 23 | 153 | #define SPORT_MRCS3 23 |
| 171 | 154 | ||
| 172 | #endif /*__BFIN_SPORT_H__*/ | 155 | #endif |
diff --git a/arch/blackfin/include/asm/ipipe.h b/arch/blackfin/include/asm/ipipe.h index 76f53d8b9a0d..343b56361ec9 100644 --- a/arch/blackfin/include/asm/ipipe.h +++ b/arch/blackfin/include/asm/ipipe.h | |||
| @@ -35,9 +35,9 @@ | |||
| 35 | #include <asm/atomic.h> | 35 | #include <asm/atomic.h> |
| 36 | #include <asm/traps.h> | 36 | #include <asm/traps.h> |
| 37 | 37 | ||
| 38 | #define IPIPE_ARCH_STRING "1.8-00" | 38 | #define IPIPE_ARCH_STRING "1.9-00" |
| 39 | #define IPIPE_MAJOR_NUMBER 1 | 39 | #define IPIPE_MAJOR_NUMBER 1 |
| 40 | #define IPIPE_MINOR_NUMBER 8 | 40 | #define IPIPE_MINOR_NUMBER 9 |
| 41 | #define IPIPE_PATCH_NUMBER 0 | 41 | #define IPIPE_PATCH_NUMBER 0 |
| 42 | 42 | ||
| 43 | #ifdef CONFIG_SMP | 43 | #ifdef CONFIG_SMP |
| @@ -83,9 +83,9 @@ struct ipipe_sysinfo { | |||
| 83 | "%2 = CYCLES2\n" \ | 83 | "%2 = CYCLES2\n" \ |
| 84 | "CC = %2 == %0\n" \ | 84 | "CC = %2 == %0\n" \ |
| 85 | "if ! CC jump 1b\n" \ | 85 | "if ! CC jump 1b\n" \ |
| 86 | : "=r" (((unsigned long *)&t)[1]), \ | 86 | : "=d,a" (((unsigned long *)&t)[1]), \ |
| 87 | "=r" (((unsigned long *)&t)[0]), \ | 87 | "=d,a" (((unsigned long *)&t)[0]), \ |
| 88 | "=r" (__cy2) \ | 88 | "=d,a" (__cy2) \ |
| 89 | : /*no input*/ : "CC"); \ | 89 | : /*no input*/ : "CC"); \ |
| 90 | t; \ | 90 | t; \ |
| 91 | }) | 91 | }) |
| @@ -118,35 +118,40 @@ void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, | |||
| 118 | 118 | ||
| 119 | #define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq)) | 119 | #define __ipipe_disable_irq(irq) (irq_desc[irq].chip->mask(irq)) |
| 120 | 120 | ||
| 121 | #define __ipipe_lock_root() \ | 121 | static inline int __ipipe_check_tickdev(const char *devname) |
| 122 | set_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags) | 122 | { |
| 123 | return 1; | ||
| 124 | } | ||
| 123 | 125 | ||
| 124 | #define __ipipe_unlock_root() \ | 126 | static inline void __ipipe_lock_root(void) |
| 125 | clear_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags) | 127 | { |
| 128 | set_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)); | ||
| 129 | } | ||
| 130 | |||
| 131 | static inline void __ipipe_unlock_root(void) | ||
| 132 | { | ||
| 133 | clear_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status)); | ||
| 134 | } | ||
| 126 | 135 | ||
| 127 | void __ipipe_enable_pipeline(void); | 136 | void __ipipe_enable_pipeline(void); |
| 128 | 137 | ||
| 129 | #define __ipipe_hook_critical_ipi(ipd) do { } while (0) | 138 | #define __ipipe_hook_critical_ipi(ipd) do { } while (0) |
| 130 | 139 | ||
| 131 | #define __ipipe_sync_pipeline(syncmask) \ | 140 | #define __ipipe_sync_pipeline ___ipipe_sync_pipeline |
| 132 | do { \ | 141 | void ___ipipe_sync_pipeline(unsigned long syncmask); |
| 133 | struct ipipe_domain *ipd = ipipe_current_domain; \ | ||
| 134 | if (likely(ipd != ipipe_root_domain || !test_bit(IPIPE_ROOTLOCK_FLAG, &ipd->flags))) \ | ||
| 135 | __ipipe_sync_stage(syncmask); \ | ||
| 136 | } while (0) | ||
| 137 | 142 | ||
| 138 | void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs); | 143 | void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs); |
| 139 | 144 | ||
| 140 | int __ipipe_get_irq_priority(unsigned irq); | 145 | int __ipipe_get_irq_priority(unsigned irq); |
| 141 | 146 | ||
| 142 | int __ipipe_get_irqthread_priority(unsigned irq); | ||
| 143 | |||
| 144 | void __ipipe_stall_root_raw(void); | 147 | void __ipipe_stall_root_raw(void); |
| 145 | 148 | ||
| 146 | void __ipipe_unstall_root_raw(void); | 149 | void __ipipe_unstall_root_raw(void); |
| 147 | 150 | ||
| 148 | void __ipipe_serial_debug(const char *fmt, ...); | 151 | void __ipipe_serial_debug(const char *fmt, ...); |
| 149 | 152 | ||
| 153 | asmlinkage void __ipipe_call_irqtail(unsigned long addr); | ||
| 154 | |||
| 150 | DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs); | 155 | DECLARE_PER_CPU(struct pt_regs, __ipipe_tick_regs); |
| 151 | 156 | ||
| 152 | extern unsigned long __ipipe_core_clock; | 157 | extern unsigned long __ipipe_core_clock; |
| @@ -162,42 +167,25 @@ static inline unsigned long __ipipe_ffnz(unsigned long ul) | |||
| 162 | 167 | ||
| 163 | #define __ipipe_run_irqtail() /* Must be a macro */ \ | 168 | #define __ipipe_run_irqtail() /* Must be a macro */ \ |
| 164 | do { \ | 169 | do { \ |
| 165 | asmlinkage void __ipipe_call_irqtail(void); \ | ||
| 166 | unsigned long __pending; \ | 170 | unsigned long __pending; \ |
| 167 | CSYNC(); \ | 171 | CSYNC(); \ |
| 168 | __pending = bfin_read_IPEND(); \ | 172 | __pending = bfin_read_IPEND(); \ |
| 169 | if (__pending & 0x8000) { \ | 173 | if (__pending & 0x8000) { \ |
| 170 | __pending &= ~0x8010; \ | 174 | __pending &= ~0x8010; \ |
| 171 | if (__pending && (__pending & (__pending - 1)) == 0) \ | 175 | if (__pending && (__pending & (__pending - 1)) == 0) \ |
| 172 | __ipipe_call_irqtail(); \ | 176 | __ipipe_call_irqtail(__ipipe_irq_tail_hook); \ |
| 173 | } \ | 177 | } \ |
| 174 | } while (0) | 178 | } while (0) |
| 175 | 179 | ||
| 176 | #define __ipipe_run_isr(ipd, irq) \ | 180 | #define __ipipe_run_isr(ipd, irq) \ |
| 177 | do { \ | 181 | do { \ |
| 178 | if (ipd == ipipe_root_domain) { \ | 182 | if (ipd == ipipe_root_domain) { \ |
| 179 | /* \ | 183 | local_irq_enable_hw(); \ |
| 180 | * Note: the I-pipe implements a threaded interrupt model on \ | 184 | if (ipipe_virtual_irq_p(irq)) \ |
| 181 | * this arch for Linux external IRQs. The interrupt handler we \ | ||
| 182 | * call here only wakes up the associated IRQ thread. \ | ||
| 183 | */ \ | ||
| 184 | if (ipipe_virtual_irq_p(irq)) { \ | ||
| 185 | /* No irqtail here; virtual interrupts have no effect \ | ||
| 186 | on IPEND so there is no need for processing \ | ||
| 187 | deferral. */ \ | ||
| 188 | local_irq_enable_nohead(ipd); \ | ||
| 189 | ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ | 185 | ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \ |
| 190 | local_irq_disable_nohead(ipd); \ | 186 | else \ |
| 191 | } else \ | ||
| 192 | /* \ | ||
| 193 | * No need to run the irqtail here either; \ | ||
| 194 | * we can't be preempted by hw IRQs, so \ | ||
| 195 | * non-Linux IRQs cannot stack over the short \ | ||
| 196 | * thread wakeup code. Which in turn means \ | ||
| 197 | * that no irqtail condition could be pending \ | ||
| 198 | * for domains above Linux in the pipeline. \ | ||
| 199 | */ \ | ||
| 200 | ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \ | 187 | ipd->irqs[irq].handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); \ |
| 188 | local_irq_disable_hw(); \ | ||
| 201 | } else { \ | 189 | } else { \ |
| 202 | __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ | 190 | __clear_bit(IPIPE_SYNC_FLAG, &ipipe_cpudom_var(ipd, status)); \ |
| 203 | local_irq_enable_nohead(ipd); \ | 191 | local_irq_enable_nohead(ipd); \ |
| @@ -217,42 +205,24 @@ void ipipe_init_irq_threads(void); | |||
| 217 | 205 | ||
| 218 | int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); | 206 | int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); |
| 219 | 207 | ||
| 220 | #define IS_SYSIRQ(irq) ((irq) > IRQ_CORETMR && (irq) <= SYS_IRQS) | 208 | #ifdef CONFIG_GENERIC_CLOCKEVENTS |
| 221 | #define IS_GPIOIRQ(irq) ((irq) >= GPIO_IRQ_BASE && (irq) < NR_IRQS) | 209 | #define IRQ_SYSTMR IRQ_CORETMR |
| 222 | 210 | #define IRQ_PRIOTMR IRQ_CORETMR | |
| 211 | #else | ||
| 223 | #define IRQ_SYSTMR IRQ_TIMER0 | 212 | #define IRQ_SYSTMR IRQ_TIMER0 |
| 224 | #define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 | 213 | #define IRQ_PRIOTMR CONFIG_IRQ_TIMER0 |
| 214 | #endif | ||
| 225 | 215 | ||
| 226 | #if defined(CONFIG_BF531) || defined(CONFIG_BF532) || defined(CONFIG_BF533) | 216 | #ifdef CONFIG_BF561 |
| 227 | #define PRIO_GPIODEMUX(irq) CONFIG_PFA | ||
| 228 | #elif defined(CONFIG_BF534) || defined(CONFIG_BF536) || defined(CONFIG_BF537) | ||
| 229 | #define PRIO_GPIODEMUX(irq) CONFIG_IRQ_PROG_INTA | ||
| 230 | #elif defined(CONFIG_BF52x) | ||
| 231 | #define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PORTF_INTA ? CONFIG_IRQ_PORTF_INTA : \ | ||
| 232 | (irq) == IRQ_PORTG_INTA ? CONFIG_IRQ_PORTG_INTA : \ | ||
| 233 | (irq) == IRQ_PORTH_INTA ? CONFIG_IRQ_PORTH_INTA : \ | ||
| 234 | -1) | ||
| 235 | #elif defined(CONFIG_BF561) | ||
| 236 | #define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PROG0_INTA ? CONFIG_IRQ_PROG0_INTA : \ | ||
| 237 | (irq) == IRQ_PROG1_INTA ? CONFIG_IRQ_PROG1_INTA : \ | ||
| 238 | (irq) == IRQ_PROG2_INTA ? CONFIG_IRQ_PROG2_INTA : \ | ||
| 239 | -1) | ||
| 240 | #define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val) | 217 | #define bfin_write_TIMER_DISABLE(val) bfin_write_TMRS8_DISABLE(val) |
| 241 | #define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val) | 218 | #define bfin_write_TIMER_ENABLE(val) bfin_write_TMRS8_ENABLE(val) |
| 242 | #define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val) | 219 | #define bfin_write_TIMER_STATUS(val) bfin_write_TMRS8_STATUS(val) |
| 243 | #define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS() | 220 | #define bfin_read_TIMER_STATUS() bfin_read_TMRS8_STATUS() |
| 244 | #elif defined(CONFIG_BF54x) | 221 | #elif defined(CONFIG_BF54x) |
| 245 | #define PRIO_GPIODEMUX(irq) ((irq) == IRQ_PINT0 ? CONFIG_IRQ_PINT0 : \ | ||
| 246 | (irq) == IRQ_PINT1 ? CONFIG_IRQ_PINT1 : \ | ||
| 247 | (irq) == IRQ_PINT2 ? CONFIG_IRQ_PINT2 : \ | ||
| 248 | (irq) == IRQ_PINT3 ? CONFIG_IRQ_PINT3 : \ | ||
| 249 | -1) | ||
| 250 | #define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val) | 222 | #define bfin_write_TIMER_DISABLE(val) bfin_write_TIMER_DISABLE0(val) |
| 251 | #define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val) | 223 | #define bfin_write_TIMER_ENABLE(val) bfin_write_TIMER_ENABLE0(val) |
| 252 | #define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val) | 224 | #define bfin_write_TIMER_STATUS(val) bfin_write_TIMER_STATUS0(val) |
| 253 | #define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val) | 225 | #define bfin_read_TIMER_STATUS(val) bfin_read_TIMER_STATUS0(val) |
| 254 | #else | ||
| 255 | # error "no PRIO_GPIODEMUX() for this part" | ||
| 256 | #endif | 226 | #endif |
| 257 | 227 | ||
| 258 | #define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0) | 228 | #define __ipipe_root_tick_p(regs) ((regs->ipend & 0x10) != 0) |
| @@ -275,4 +245,6 @@ int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc); | |||
| 275 | 245 | ||
| 276 | #endif /* !CONFIG_IPIPE */ | 246 | #endif /* !CONFIG_IPIPE */ |
| 277 | 247 | ||
| 248 | #define ipipe_update_tick_evtdev(evtdev) do { } while (0) | ||
| 249 | |||
| 278 | #endif /* !__ASM_BLACKFIN_IPIPE_H */ | 250 | #endif /* !__ASM_BLACKFIN_IPIPE_H */ |
diff --git a/arch/blackfin/include/asm/ipipe_base.h b/arch/blackfin/include/asm/ipipe_base.h index cb1025aeabcf..3e8acbd1a3be 100644 --- a/arch/blackfin/include/asm/ipipe_base.h +++ b/arch/blackfin/include/asm/ipipe_base.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* -*- linux-c -*- | 1 | /* -*- linux-c -*- |
| 2 | * include/asm-blackfin/_baseipipe.h | 2 | * include/asm-blackfin/ipipe_base.h |
| 3 | * | 3 | * |
| 4 | * Copyright (C) 2007 Philippe Gerum. | 4 | * Copyright (C) 2007 Philippe Gerum. |
| 5 | * | 5 | * |
| @@ -27,8 +27,9 @@ | |||
| 27 | #define IPIPE_NR_XIRQS NR_IRQS | 27 | #define IPIPE_NR_XIRQS NR_IRQS |
| 28 | #define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */ | 28 | #define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */ |
| 29 | 29 | ||
| 30 | /* Blackfin-specific, global domain flags */ | 30 | /* Blackfin-specific, per-cpu pipeline status */ |
| 31 | #define IPIPE_ROOTLOCK_FLAG 1 /* Lock pipeline for root */ | 31 | #define IPIPE_SYNCDEFER_FLAG 15 |
| 32 | #define IPIPE_SYNCDEFER_MASK (1L << IPIPE_SYNCDEFER_MASK) | ||
| 32 | 33 | ||
| 33 | /* Blackfin traps -- i.e. exception vector numbers */ | 34 | /* Blackfin traps -- i.e. exception vector numbers */ |
| 34 | #define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */ | 35 | #define IPIPE_NR_FAULTS 52 /* We leave a gap after VEC_ILL_RES. */ |
| @@ -48,11 +49,6 @@ | |||
| 48 | 49 | ||
| 49 | #ifndef __ASSEMBLY__ | 50 | #ifndef __ASSEMBLY__ |
| 50 | 51 | ||
| 51 | #include <linux/bitops.h> | ||
| 52 | |||
| 53 | extern int test_bit(int nr, const void *addr); | ||
| 54 | |||
| 55 | |||
| 56 | extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ | 52 | extern unsigned long __ipipe_root_status; /* Alias to ipipe_root_cpudom_var(status) */ |
| 57 | 53 | ||
| 58 | static inline void __ipipe_stall_root(void) | 54 | static inline void __ipipe_stall_root(void) |
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h index 3d977909ce7d..7645e85a5f6f 100644 --- a/arch/blackfin/include/asm/irq.h +++ b/arch/blackfin/include/asm/irq.h | |||
| @@ -61,20 +61,38 @@ void __ipipe_restore_root(unsigned long flags); | |||
| 61 | #define raw_irqs_disabled_flags(flags) (!irqs_enabled_from_flags_hw(flags)) | 61 | #define raw_irqs_disabled_flags(flags) (!irqs_enabled_from_flags_hw(flags)) |
| 62 | #define local_test_iflag_hw(x) irqs_enabled_from_flags_hw(x) | 62 | #define local_test_iflag_hw(x) irqs_enabled_from_flags_hw(x) |
| 63 | 63 | ||
| 64 | #define local_save_flags(x) \ | 64 | #define local_save_flags(x) \ |
| 65 | do { \ | 65 | do { \ |
| 66 | (x) = __ipipe_test_root() ? \ | 66 | (x) = __ipipe_test_root() ? \ |
| 67 | __all_masked_irq_flags : bfin_irq_flags; \ | 67 | __all_masked_irq_flags : bfin_irq_flags; \ |
| 68 | barrier(); \ | ||
| 68 | } while (0) | 69 | } while (0) |
| 69 | 70 | ||
| 70 | #define local_irq_save(x) \ | 71 | #define local_irq_save(x) \ |
| 71 | do { \ | 72 | do { \ |
| 72 | (x) = __ipipe_test_and_stall_root(); \ | 73 | (x) = __ipipe_test_and_stall_root() ? \ |
| 74 | __all_masked_irq_flags : bfin_irq_flags; \ | ||
| 75 | barrier(); \ | ||
| 76 | } while (0) | ||
| 77 | |||
| 78 | static inline void local_irq_restore(unsigned long x) | ||
| 79 | { | ||
| 80 | barrier(); | ||
| 81 | __ipipe_restore_root(x == __all_masked_irq_flags); | ||
| 82 | } | ||
| 83 | |||
| 84 | #define local_irq_disable() \ | ||
| 85 | do { \ | ||
| 86 | __ipipe_stall_root(); \ | ||
| 87 | barrier(); \ | ||
| 73 | } while (0) | 88 | } while (0) |
| 74 | 89 | ||
| 75 | #define local_irq_restore(x) __ipipe_restore_root(x) | 90 | static inline void local_irq_enable(void) |
| 76 | #define local_irq_disable() __ipipe_stall_root() | 91 | { |
| 77 | #define local_irq_enable() __ipipe_unstall_root() | 92 | barrier(); |
| 93 | __ipipe_unstall_root(); | ||
| 94 | } | ||
| 95 | |||
| 78 | #define irqs_disabled() __ipipe_test_root() | 96 | #define irqs_disabled() __ipipe_test_root() |
| 79 | 97 | ||
| 80 | #define local_save_flags_hw(x) \ | 98 | #define local_save_flags_hw(x) \ |
diff --git a/arch/blackfin/include/asm/thread_info.h b/arch/blackfin/include/asm/thread_info.h index e721ce55956c..2920087516f2 100644 --- a/arch/blackfin/include/asm/thread_info.h +++ b/arch/blackfin/include/asm/thread_info.h | |||
| @@ -122,6 +122,7 @@ static inline struct thread_info *current_thread_info(void) | |||
| 122 | #define TIF_MEMDIE 4 | 122 | #define TIF_MEMDIE 4 |
| 123 | #define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ | 123 | #define TIF_RESTORE_SIGMASK 5 /* restore signal mask in do_signal() */ |
| 124 | #define TIF_FREEZE 6 /* is freezing for suspend */ | 124 | #define TIF_FREEZE 6 /* is freezing for suspend */ |
| 125 | #define TIF_IRQ_SYNC 7 /* sync pipeline stage */ | ||
| 125 | 126 | ||
| 126 | /* as above, but as bit values */ | 127 | /* as above, but as bit values */ |
| 127 | #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) | 128 | #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) |
| @@ -130,6 +131,7 @@ static inline struct thread_info *current_thread_info(void) | |||
| 130 | #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) | 131 | #define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) |
| 131 | #define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) | 132 | #define _TIF_RESTORE_SIGMASK (1<<TIF_RESTORE_SIGMASK) |
| 132 | #define _TIF_FREEZE (1<<TIF_FREEZE) | 133 | #define _TIF_FREEZE (1<<TIF_FREEZE) |
| 134 | #define _TIF_IRQ_SYNC (1<<TIF_IRQ_SYNC) | ||
| 133 | 135 | ||
| 134 | #define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ | 136 | #define _TIF_WORK_MASK 0x0000FFFE /* work to do on interrupt/exception return */ |
| 135 | 137 | ||
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile index 4a92a86824b7..fd4d4328a0f2 100644 --- a/arch/blackfin/kernel/Makefile +++ b/arch/blackfin/kernel/Makefile | |||
| @@ -15,13 +15,15 @@ else | |||
| 15 | obj-y += time.o | 15 | obj-y += time.o |
| 16 | endif | 16 | endif |
| 17 | 17 | ||
| 18 | CFLAGS_kgdb_test.o := -mlong-calls -O0 | ||
| 19 | |||
| 20 | obj-$(CONFIG_IPIPE) += ipipe.o | 18 | obj-$(CONFIG_IPIPE) += ipipe.o |
| 21 | obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o | 19 | obj-$(CONFIG_IPIPE_TRACE_MCOUNT) += mcount.o |
| 22 | obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o | 20 | obj-$(CONFIG_BFIN_GPTIMERS) += gptimers.o |
| 23 | obj-$(CONFIG_CPLB_INFO) += cplbinfo.o | 21 | obj-$(CONFIG_CPLB_INFO) += cplbinfo.o |
| 24 | obj-$(CONFIG_MODULES) += module.o | 22 | obj-$(CONFIG_MODULES) += module.o |
| 25 | obj-$(CONFIG_KGDB) += kgdb.o | 23 | obj-$(CONFIG_KGDB) += kgdb.o |
| 26 | obj-$(CONFIG_KGDB_TESTCASE) += kgdb_test.o | 24 | obj-$(CONFIG_KGDB_TESTS) += kgdb_test.o |
| 27 | obj-$(CONFIG_EARLY_PRINTK) += early_printk.o | 25 | obj-$(CONFIG_EARLY_PRINTK) += early_printk.o |
| 26 | |||
| 27 | # the kgdb test puts code into L2 and without linker | ||
| 28 | # relaxation, we need to force long calls to/from it | ||
| 29 | CFLAGS_kgdb_test.o := -mlong-calls -O0 | ||
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c index 0e28f7595733..d6c067782e63 100644 --- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c +++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c | |||
| @@ -53,9 +53,13 @@ void __init generate_cplb_tables_cpu(unsigned int cpu) | |||
| 53 | 53 | ||
| 54 | i_d = i_i = 0; | 54 | i_d = i_i = 0; |
| 55 | 55 | ||
| 56 | #ifdef CONFIG_DEBUG_HUNT_FOR_ZERO | ||
| 56 | /* Set up the zero page. */ | 57 | /* Set up the zero page. */ |
| 57 | d_tbl[i_d].addr = 0; | 58 | d_tbl[i_d].addr = 0; |
| 58 | d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB; | 59 | d_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB; |
| 60 | i_tbl[i_i].addr = 0; | ||
| 61 | i_tbl[i_i++].data = SDRAM_OOPS | PAGE_SIZE_1KB; | ||
| 62 | #endif | ||
| 59 | 63 | ||
| 60 | /* Cover kernel memory with 4M pages. */ | 64 | /* Cover kernel memory with 4M pages. */ |
| 61 | addr = 0; | 65 | addr = 0; |
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c index 339be5a3ae6a..a5de8d45424c 100644 --- a/arch/blackfin/kernel/ipipe.c +++ b/arch/blackfin/kernel/ipipe.c | |||
| @@ -35,14 +35,8 @@ | |||
| 35 | #include <asm/atomic.h> | 35 | #include <asm/atomic.h> |
| 36 | #include <asm/io.h> | 36 | #include <asm/io.h> |
| 37 | 37 | ||
| 38 | static int create_irq_threads; | ||
| 39 | |||
| 40 | DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs); | 38 | DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs); |
| 41 | 39 | ||
| 42 | static DEFINE_PER_CPU(unsigned long, pending_irqthread_mask); | ||
| 43 | |||
| 44 | static DEFINE_PER_CPU(int [IVG13 + 1], pending_irq_count); | ||
| 45 | |||
| 46 | asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); | 40 | asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs); |
| 47 | 41 | ||
| 48 | static void __ipipe_no_irqtail(void); | 42 | static void __ipipe_no_irqtail(void); |
| @@ -93,6 +87,7 @@ void __ipipe_enable_pipeline(void) | |||
| 93 | */ | 87 | */ |
| 94 | void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) | 88 | void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) |
| 95 | { | 89 | { |
| 90 | struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); | ||
| 96 | struct ipipe_domain *this_domain, *next_domain; | 91 | struct ipipe_domain *this_domain, *next_domain; |
| 97 | struct list_head *head, *pos; | 92 | struct list_head *head, *pos; |
| 98 | int m_ack, s = -1; | 93 | int m_ack, s = -1; |
| @@ -104,7 +99,6 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) | |||
| 104 | * interrupt. | 99 | * interrupt. |
| 105 | */ | 100 | */ |
| 106 | m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR); | 101 | m_ack = (regs == NULL || irq == IRQ_SYSTMR || irq == IRQ_CORETMR); |
| 107 | |||
| 108 | this_domain = ipipe_current_domain; | 102 | this_domain = ipipe_current_domain; |
| 109 | 103 | ||
| 110 | if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control))) | 104 | if (unlikely(test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control))) |
| @@ -114,49 +108,28 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) | |||
| 114 | next_domain = list_entry(head, struct ipipe_domain, p_link); | 108 | next_domain = list_entry(head, struct ipipe_domain, p_link); |
| 115 | if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) { | 109 | if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) { |
| 116 | if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) | 110 | if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) |
| 117 | next_domain->irqs[irq].acknowledge(irq, irq_desc + irq); | 111 | next_domain->irqs[irq].acknowledge(irq, irq_to_desc(irq)); |
| 118 | if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)) | 112 | if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status)) |
| 119 | s = __test_and_set_bit(IPIPE_STALL_FLAG, | 113 | s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status); |
| 120 | &ipipe_root_cpudom_var(status)); | ||
| 121 | __ipipe_dispatch_wired(next_domain, irq); | 114 | __ipipe_dispatch_wired(next_domain, irq); |
| 122 | goto finalize; | 115 | goto out; |
| 123 | return; | ||
| 124 | } | 116 | } |
| 125 | } | 117 | } |
| 126 | 118 | ||
| 127 | /* Ack the interrupt. */ | 119 | /* Ack the interrupt. */ |
| 128 | 120 | ||
| 129 | pos = head; | 121 | pos = head; |
| 130 | |||
| 131 | while (pos != &__ipipe_pipeline) { | 122 | while (pos != &__ipipe_pipeline) { |
| 132 | next_domain = list_entry(pos, struct ipipe_domain, p_link); | 123 | next_domain = list_entry(pos, struct ipipe_domain, p_link); |
| 133 | /* | ||
| 134 | * For each domain handling the incoming IRQ, mark it | ||
| 135 | * as pending in its log. | ||
| 136 | */ | ||
| 137 | if (test_bit(IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) { | 124 | if (test_bit(IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) { |
| 138 | /* | ||
| 139 | * Domains that handle this IRQ are polled for | ||
| 140 | * acknowledging it by decreasing priority | ||
| 141 | * order. The interrupt must be made pending | ||
| 142 | * _first_ in the domain's status flags before | ||
| 143 | * the PIC is unlocked. | ||
| 144 | */ | ||
| 145 | __ipipe_set_irq_pending(next_domain, irq); | 125 | __ipipe_set_irq_pending(next_domain, irq); |
| 146 | |||
| 147 | if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) { | 126 | if (!m_ack && next_domain->irqs[irq].acknowledge != NULL) { |
| 148 | next_domain->irqs[irq].acknowledge(irq, irq_desc + irq); | 127 | next_domain->irqs[irq].acknowledge(irq, irq_to_desc(irq)); |
| 149 | m_ack = 1; | 128 | m_ack = 1; |
| 150 | } | 129 | } |
| 151 | } | 130 | } |
| 152 | |||
| 153 | /* | ||
| 154 | * If the domain does not want the IRQ to be passed | ||
| 155 | * down the interrupt pipe, exit the loop now. | ||
| 156 | */ | ||
| 157 | if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control)) | 131 | if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control)) |
| 158 | break; | 132 | break; |
| 159 | |||
| 160 | pos = next_domain->p_link.next; | 133 | pos = next_domain->p_link.next; |
| 161 | } | 134 | } |
| 162 | 135 | ||
| @@ -166,18 +139,24 @@ void __ipipe_handle_irq(unsigned irq, struct pt_regs *regs) | |||
| 166 | * immediately to the current domain if the interrupt has been | 139 | * immediately to the current domain if the interrupt has been |
| 167 | * marked as 'sticky'. This search does not go beyond the | 140 | * marked as 'sticky'. This search does not go beyond the |
| 168 | * current domain in the pipeline. We also enforce the | 141 | * current domain in the pipeline. We also enforce the |
| 169 | * additional root stage lock (blackfin-specific). */ | 142 | * additional root stage lock (blackfin-specific). |
| 143 | */ | ||
| 144 | if (test_bit(IPIPE_SYNCDEFER_FLAG, &p->status)) | ||
| 145 | s = __test_and_set_bit(IPIPE_STALL_FLAG, &p->status); | ||
| 170 | 146 | ||
| 171 | if (test_bit(IPIPE_ROOTLOCK_FLAG, &ipipe_root_domain->flags)) | 147 | /* |
| 172 | s = __test_and_set_bit(IPIPE_STALL_FLAG, | 148 | * If the interrupt preempted the head domain, then do not |
| 173 | &ipipe_root_cpudom_var(status)); | 149 | * even try to walk the pipeline, unless an interrupt is |
| 174 | finalize: | 150 | * pending for it. |
| 151 | */ | ||
| 152 | if (test_bit(IPIPE_AHEAD_FLAG, &this_domain->flags) && | ||
| 153 | ipipe_head_cpudom_var(irqpend_himask) == 0) | ||
| 154 | goto out; | ||
| 175 | 155 | ||
| 176 | __ipipe_walk_pipeline(head); | 156 | __ipipe_walk_pipeline(head); |
| 177 | 157 | out: | |
| 178 | if (!s) | 158 | if (!s) |
| 179 | __clear_bit(IPIPE_STALL_FLAG, | 159 | __clear_bit(IPIPE_STALL_FLAG, &p->status); |
| 180 | &ipipe_root_cpudom_var(status)); | ||
| 181 | } | 160 | } |
| 182 | 161 | ||
| 183 | int __ipipe_check_root(void) | 162 | int __ipipe_check_root(void) |
| @@ -187,7 +166,7 @@ int __ipipe_check_root(void) | |||
| 187 | 166 | ||
| 188 | void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq) | 167 | void __ipipe_enable_irqdesc(struct ipipe_domain *ipd, unsigned irq) |
| 189 | { | 168 | { |
| 190 | struct irq_desc *desc = irq_desc + irq; | 169 | struct irq_desc *desc = irq_to_desc(irq); |
| 191 | int prio = desc->ic_prio; | 170 | int prio = desc->ic_prio; |
| 192 | 171 | ||
| 193 | desc->depth = 0; | 172 | desc->depth = 0; |
| @@ -199,7 +178,7 @@ EXPORT_SYMBOL(__ipipe_enable_irqdesc); | |||
| 199 | 178 | ||
| 200 | void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq) | 179 | void __ipipe_disable_irqdesc(struct ipipe_domain *ipd, unsigned irq) |
| 201 | { | 180 | { |
| 202 | struct irq_desc *desc = irq_desc + irq; | 181 | struct irq_desc *desc = irq_to_desc(irq); |
| 203 | int prio = desc->ic_prio; | 182 | int prio = desc->ic_prio; |
| 204 | 183 | ||
| 205 | if (ipd != &ipipe_root && | 184 | if (ipd != &ipipe_root && |
| @@ -236,15 +215,18 @@ int __ipipe_syscall_root(struct pt_regs *regs) | |||
| 236 | { | 215 | { |
| 237 | unsigned long flags; | 216 | unsigned long flags; |
| 238 | 217 | ||
| 239 | /* We need to run the IRQ tail hook whenever we don't | 218 | /* |
| 219 | * We need to run the IRQ tail hook whenever we don't | ||
| 240 | * propagate a syscall to higher domains, because we know that | 220 | * propagate a syscall to higher domains, because we know that |
| 241 | * important operations might be pending there (e.g. Xenomai | 221 | * important operations might be pending there (e.g. Xenomai |
| 242 | * deferred rescheduling). */ | 222 | * deferred rescheduling). |
| 223 | */ | ||
| 243 | 224 | ||
| 244 | if (!__ipipe_syscall_watched_p(current, regs->orig_p0)) { | 225 | if (regs->orig_p0 < NR_syscalls) { |
| 245 | void (*hook)(void) = (void (*)(void))__ipipe_irq_tail_hook; | 226 | void (*hook)(void) = (void (*)(void))__ipipe_irq_tail_hook; |
| 246 | hook(); | 227 | hook(); |
| 247 | return 0; | 228 | if ((current->flags & PF_EVNOTIFY) == 0) |
| 229 | return 0; | ||
| 248 | } | 230 | } |
| 249 | 231 | ||
| 250 | /* | 232 | /* |
| @@ -312,112 +294,46 @@ int ipipe_trigger_irq(unsigned irq) | |||
| 312 | { | 294 | { |
| 313 | unsigned long flags; | 295 | unsigned long flags; |
| 314 | 296 | ||
| 297 | #ifdef CONFIG_IPIPE_DEBUG | ||
| 315 | if (irq >= IPIPE_NR_IRQS || | 298 | if (irq >= IPIPE_NR_IRQS || |
| 316 | (ipipe_virtual_irq_p(irq) | 299 | (ipipe_virtual_irq_p(irq) |
| 317 | && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map))) | 300 | && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map))) |
| 318 | return -EINVAL; | 301 | return -EINVAL; |
| 302 | #endif | ||
| 319 | 303 | ||
| 320 | local_irq_save_hw(flags); | 304 | local_irq_save_hw(flags); |
| 321 | |||
| 322 | __ipipe_handle_irq(irq, NULL); | 305 | __ipipe_handle_irq(irq, NULL); |
| 323 | |||
| 324 | local_irq_restore_hw(flags); | 306 | local_irq_restore_hw(flags); |
| 325 | 307 | ||
| 326 | return 1; | 308 | return 1; |
| 327 | } | 309 | } |
| 328 | 310 | ||
| 329 | /* Move Linux IRQ to threads. */ | 311 | asmlinkage void __ipipe_sync_root(void) |
| 330 | |||
| 331 | static int do_irqd(void *__desc) | ||
| 332 | { | 312 | { |
| 333 | struct irq_desc *desc = __desc; | 313 | unsigned long flags; |
| 334 | unsigned irq = desc - irq_desc; | ||
| 335 | int thrprio = desc->thr_prio; | ||
| 336 | int thrmask = 1 << thrprio; | ||
| 337 | int cpu = smp_processor_id(); | ||
| 338 | cpumask_t cpumask; | ||
| 339 | |||
| 340 | sigfillset(¤t->blocked); | ||
| 341 | current->flags |= PF_NOFREEZE; | ||
| 342 | cpumask = cpumask_of_cpu(cpu); | ||
| 343 | set_cpus_allowed(current, cpumask); | ||
| 344 | ipipe_setscheduler_root(current, SCHED_FIFO, 50 + thrprio); | ||
| 345 | |||
| 346 | while (!kthread_should_stop()) { | ||
| 347 | local_irq_disable(); | ||
| 348 | if (!(desc->status & IRQ_SCHEDULED)) { | ||
| 349 | set_current_state(TASK_INTERRUPTIBLE); | ||
| 350 | resched: | ||
| 351 | local_irq_enable(); | ||
| 352 | schedule(); | ||
| 353 | local_irq_disable(); | ||
| 354 | } | ||
| 355 | __set_current_state(TASK_RUNNING); | ||
| 356 | /* | ||
| 357 | * If higher priority interrupt servers are ready to | ||
| 358 | * run, reschedule immediately. We need this for the | ||
| 359 | * GPIO demux IRQ handler to unmask the interrupt line | ||
| 360 | * _last_, after all GPIO IRQs have run. | ||
| 361 | */ | ||
| 362 | if (per_cpu(pending_irqthread_mask, cpu) & ~(thrmask|(thrmask-1))) | ||
| 363 | goto resched; | ||
| 364 | if (--per_cpu(pending_irq_count[thrprio], cpu) == 0) | ||
| 365 | per_cpu(pending_irqthread_mask, cpu) &= ~thrmask; | ||
| 366 | desc->status &= ~IRQ_SCHEDULED; | ||
| 367 | desc->thr_handler(irq, &__raw_get_cpu_var(__ipipe_tick_regs)); | ||
| 368 | local_irq_enable(); | ||
| 369 | } | ||
| 370 | __set_current_state(TASK_RUNNING); | ||
| 371 | return 0; | ||
| 372 | } | ||
| 373 | 314 | ||
| 374 | static void kick_irqd(unsigned irq, void *cookie) | 315 | BUG_ON(irqs_disabled()); |
| 375 | { | ||
| 376 | struct irq_desc *desc = irq_desc + irq; | ||
| 377 | int thrprio = desc->thr_prio; | ||
| 378 | int thrmask = 1 << thrprio; | ||
| 379 | int cpu = smp_processor_id(); | ||
| 380 | |||
| 381 | if (!(desc->status & IRQ_SCHEDULED)) { | ||
| 382 | desc->status |= IRQ_SCHEDULED; | ||
| 383 | per_cpu(pending_irqthread_mask, cpu) |= thrmask; | ||
| 384 | ++per_cpu(pending_irq_count[thrprio], cpu); | ||
| 385 | wake_up_process(desc->thread); | ||
| 386 | } | ||
| 387 | } | ||
| 388 | 316 | ||
| 389 | int ipipe_start_irq_thread(unsigned irq, struct irq_desc *desc) | 317 | local_irq_save_hw(flags); |
| 390 | { | ||
| 391 | if (desc->thread || !create_irq_threads) | ||
| 392 | return 0; | ||
| 393 | |||
| 394 | desc->thread = kthread_create(do_irqd, desc, "IRQ %d", irq); | ||
| 395 | if (desc->thread == NULL) { | ||
| 396 | printk(KERN_ERR "irqd: could not create IRQ thread %d!\n", irq); | ||
| 397 | return -ENOMEM; | ||
| 398 | } | ||
| 399 | 318 | ||
| 400 | wake_up_process(desc->thread); | 319 | clear_thread_flag(TIF_IRQ_SYNC); |
| 401 | 320 | ||
| 402 | desc->thr_handler = ipipe_root_domain->irqs[irq].handler; | 321 | if (ipipe_root_cpudom_var(irqpend_himask) != 0) |
| 403 | ipipe_root_domain->irqs[irq].handler = &kick_irqd; | 322 | __ipipe_sync_pipeline(IPIPE_IRQMASK_ANY); |
| 404 | 323 | ||
| 405 | return 0; | 324 | local_irq_restore_hw(flags); |
| 406 | } | 325 | } |
| 407 | 326 | ||
| 408 | void __init ipipe_init_irq_threads(void) | 327 | void ___ipipe_sync_pipeline(unsigned long syncmask) |
| 409 | { | 328 | { |
| 410 | unsigned irq; | 329 | struct ipipe_domain *ipd = ipipe_current_domain; |
| 411 | struct irq_desc *desc; | ||
| 412 | |||
| 413 | create_irq_threads = 1; | ||
| 414 | 330 | ||
| 415 | for (irq = 0; irq < NR_IRQS; irq++) { | 331 | if (ipd == ipipe_root_domain) { |
| 416 | desc = irq_desc + irq; | 332 | if (test_bit(IPIPE_SYNCDEFER_FLAG, &ipipe_root_cpudom_var(status))) |
| 417 | if (desc->action != NULL || | 333 | return; |
| 418 | (desc->status & IRQ_NOREQUEST) != 0) | ||
| 419 | ipipe_start_irq_thread(irq, desc); | ||
| 420 | } | 334 | } |
| 335 | |||
| 336 | __ipipe_sync_stage(syncmask); | ||
| 421 | } | 337 | } |
| 422 | 338 | ||
| 423 | EXPORT_SYMBOL(show_stack); | 339 | EXPORT_SYMBOL(show_stack); |
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c index 75724eee6494..7fd126564846 100644 --- a/arch/blackfin/kernel/irqchip.c +++ b/arch/blackfin/kernel/irqchip.c | |||
| @@ -144,11 +144,15 @@ asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs) | |||
| 144 | #endif | 144 | #endif |
| 145 | generic_handle_irq(irq); | 145 | generic_handle_irq(irq); |
| 146 | 146 | ||
| 147 | #ifndef CONFIG_IPIPE /* Useless and bugous over the I-pipe: IRQs are threaded. */ | 147 | #ifndef CONFIG_IPIPE |
| 148 | /* If we're the only interrupt running (ignoring IRQ15 which is for | 148 | /* |
| 149 | syscalls), lower our priority to IRQ14 so that softirqs run at | 149 | * If we're the only interrupt running (ignoring IRQ15 which |
| 150 | that level. If there's another, lower-level interrupt, irq_exit | 150 | * is for syscalls), lower our priority to IRQ14 so that |
| 151 | will defer softirqs to that. */ | 151 | * softirqs run at that level. If there's another, |
| 152 | * lower-level interrupt, irq_exit will defer softirqs to | ||
| 153 | * that. If the interrupt pipeline is enabled, we are already | ||
| 154 | * running at IRQ14 priority, so we don't need this code. | ||
| 155 | */ | ||
| 152 | CSYNC(); | 156 | CSYNC(); |
| 153 | pending = bfin_read_IPEND() & ~0x8000; | 157 | pending = bfin_read_IPEND() & ~0x8000; |
| 154 | other_ints = pending & (pending - 1); | 158 | other_ints = pending & (pending - 1); |
diff --git a/arch/blackfin/kernel/kgdb_test.c b/arch/blackfin/kernel/kgdb_test.c index 3dba9c17304a..dbcf3e45cb0b 100644 --- a/arch/blackfin/kernel/kgdb_test.c +++ b/arch/blackfin/kernel/kgdb_test.c | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | static char cmdline[256]; | 20 | static char cmdline[256]; |
| 21 | static unsigned long len; | 21 | static unsigned long len; |
| 22 | 22 | ||
| 23 | #ifndef CONFIG_SMP | ||
| 23 | static int num1 __attribute__((l1_data)); | 24 | static int num1 __attribute__((l1_data)); |
| 24 | 25 | ||
| 25 | void kgdb_l1_test(void) __attribute__((l1_text)); | 26 | void kgdb_l1_test(void) __attribute__((l1_text)); |
| @@ -32,6 +33,8 @@ void kgdb_l1_test(void) | |||
| 32 | printk(KERN_ALERT "L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); | 33 | printk(KERN_ALERT "L1(after change) : data variable addr = 0x%p, data value is %d\n", &num1, num1); |
| 33 | return ; | 34 | return ; |
| 34 | } | 35 | } |
| 36 | #endif | ||
| 37 | |||
| 35 | #if L2_LENGTH | 38 | #if L2_LENGTH |
| 36 | 39 | ||
| 37 | static int num2 __attribute__((l2)); | 40 | static int num2 __attribute__((l2)); |
| @@ -59,10 +62,12 @@ int kgdb_test(char *name, int len, int count, int z) | |||
| 59 | static int test_proc_output(char *buf) | 62 | static int test_proc_output(char *buf) |
| 60 | { | 63 | { |
| 61 | kgdb_test("hello world!", 12, 0x55, 0x10); | 64 | kgdb_test("hello world!", 12, 0x55, 0x10); |
| 65 | #ifndef CONFIG_SMP | ||
| 62 | kgdb_l1_test(); | 66 | kgdb_l1_test(); |
| 63 | #if L2_LENGTH | 67 | #endif |
| 68 | #if L2_LENGTH | ||
| 64 | kgdb_l2_test(); | 69 | kgdb_l2_test(); |
| 65 | #endif | 70 | #endif |
| 66 | 71 | ||
| 67 | return 0; | 72 | return 0; |
| 68 | } | 73 | } |
diff --git a/arch/blackfin/kernel/ptrace.c b/arch/blackfin/kernel/ptrace.c index 594e325b40e4..d76618db50df 100644 --- a/arch/blackfin/kernel/ptrace.c +++ b/arch/blackfin/kernel/ptrace.c | |||
| @@ -45,6 +45,7 @@ | |||
| 45 | #include <asm/asm-offsets.h> | 45 | #include <asm/asm-offsets.h> |
| 46 | #include <asm/dma.h> | 46 | #include <asm/dma.h> |
| 47 | #include <asm/fixed_code.h> | 47 | #include <asm/fixed_code.h> |
| 48 | #include <asm/cacheflush.h> | ||
| 48 | #include <asm/mem_map.h> | 49 | #include <asm/mem_map.h> |
| 49 | 50 | ||
| 50 | #define TEXT_OFFSET 0 | 51 | #define TEXT_OFFSET 0 |
| @@ -240,7 +241,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) | |||
| 240 | 241 | ||
| 241 | } else if (addr >= FIXED_CODE_START | 242 | } else if (addr >= FIXED_CODE_START |
| 242 | && addr + sizeof(tmp) <= FIXED_CODE_END) { | 243 | && addr + sizeof(tmp) <= FIXED_CODE_END) { |
| 243 | memcpy(&tmp, (const void *)(addr), sizeof(tmp)); | 244 | copy_from_user_page(0, 0, 0, &tmp, (const void *)(addr), sizeof(tmp)); |
| 244 | copied = sizeof(tmp); | 245 | copied = sizeof(tmp); |
| 245 | 246 | ||
| 246 | } else | 247 | } else |
| @@ -320,7 +321,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) | |||
| 320 | 321 | ||
| 321 | } else if (addr >= FIXED_CODE_START | 322 | } else if (addr >= FIXED_CODE_START |
| 322 | && addr + sizeof(data) <= FIXED_CODE_END) { | 323 | && addr + sizeof(data) <= FIXED_CODE_END) { |
| 323 | memcpy((void *)(addr), &data, sizeof(data)); | 324 | copy_to_user_page(0, 0, 0, (void *)(addr), &data, sizeof(data)); |
| 324 | copied = sizeof(data); | 325 | copied = sizeof(data); |
| 325 | 326 | ||
| 326 | } else | 327 | } else |
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c index e5c116230800..a58687bdee6a 100644 --- a/arch/blackfin/kernel/setup.c +++ b/arch/blackfin/kernel/setup.c | |||
| @@ -889,6 +889,10 @@ void __init setup_arch(char **cmdline_p) | |||
| 889 | CPU, bfin_revid()); | 889 | CPU, bfin_revid()); |
| 890 | } | 890 | } |
| 891 | 891 | ||
| 892 | /* We can't run on BF548-0.1 due to ANOMALY 05000448 */ | ||
| 893 | if (bfin_cpuid() == 0x27de && bfin_revid() == 1) | ||
| 894 | panic("You can't run on this processor due to 05000448\n"); | ||
| 895 | |||
| 892 | printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); | 896 | printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n"); |
| 893 | 897 | ||
| 894 | printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", | 898 | printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n", |
| @@ -1141,12 +1145,12 @@ static int show_cpuinfo(struct seq_file *m, void *v) | |||
| 1141 | icache_size = 0; | 1145 | icache_size = 0; |
| 1142 | 1146 | ||
| 1143 | seq_printf(m, "cache size\t: %d KB(L1 icache) " | 1147 | seq_printf(m, "cache size\t: %d KB(L1 icache) " |
| 1144 | "%d KB(L1 dcache-%s) %d KB(L2 cache)\n", | 1148 | "%d KB(L1 dcache%s) %d KB(L2 cache)\n", |
| 1145 | icache_size, dcache_size, | 1149 | icache_size, dcache_size, |
| 1146 | #if defined CONFIG_BFIN_WB | 1150 | #if defined CONFIG_BFIN_WB |
| 1147 | "wb" | 1151 | "-wb" |
| 1148 | #elif defined CONFIG_BFIN_WT | 1152 | #elif defined CONFIG_BFIN_WT |
| 1149 | "wt" | 1153 | "-wt" |
| 1150 | #endif | 1154 | #endif |
| 1151 | "", 0); | 1155 | "", 0); |
| 1152 | 1156 | ||
diff --git a/arch/blackfin/kernel/time.c b/arch/blackfin/kernel/time.c index 172b4c588467..1bbacfbd4c5d 100644 --- a/arch/blackfin/kernel/time.c +++ b/arch/blackfin/kernel/time.c | |||
| @@ -134,7 +134,10 @@ irqreturn_t timer_interrupt(int irq, void *dummy) | |||
| 134 | 134 | ||
| 135 | write_seqlock(&xtime_lock); | 135 | write_seqlock(&xtime_lock); |
| 136 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE) | 136 | #if defined(CONFIG_TICK_SOURCE_SYSTMR0) && !defined(CONFIG_IPIPE) |
| 137 | /* FIXME: Here TIMIL0 is not set when IPIPE enabled, why? */ | 137 | /* |
| 138 | * TIMIL0 is latched in __ipipe_grab_irq() when the I-Pipe is | ||
| 139 | * enabled. | ||
| 140 | */ | ||
| 138 | if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) { | 141 | if (get_gptimer_status(0) & TIMER_STATUS_TIMIL0) { |
| 139 | #endif | 142 | #endif |
| 140 | do_timer(1); | 143 | do_timer(1); |
diff --git a/arch/blackfin/mach-bf518/boards/ezbrd.c b/arch/blackfin/mach-bf518/boards/ezbrd.c index 0e175342112e..41f2eacfef20 100644 --- a/arch/blackfin/mach-bf518/boards/ezbrd.c +++ b/arch/blackfin/mach-bf518/boards/ezbrd.c | |||
| @@ -113,7 +113,6 @@ static struct platform_device bfin_mac_device = { | |||
| 113 | .name = "bfin_mac", | 113 | .name = "bfin_mac", |
| 114 | .dev.platform_data = &bfin_mii_bus, | 114 | .dev.platform_data = &bfin_mii_bus, |
| 115 | }; | 115 | }; |
| 116 | #endif | ||
| 117 | 116 | ||
| 118 | #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) | 117 | #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) |
| 119 | static struct dsa_platform_data ksz8893m_switch_data = { | 118 | static struct dsa_platform_data ksz8893m_switch_data = { |
| @@ -132,6 +131,7 @@ static struct platform_device ksz8893m_switch_device = { | |||
| 132 | .dev.platform_data = &ksz8893m_switch_data, | 131 | .dev.platform_data = &ksz8893m_switch_data, |
| 133 | }; | 132 | }; |
| 134 | #endif | 133 | #endif |
| 134 | #endif | ||
| 135 | 135 | ||
| 136 | #if defined(CONFIG_MTD_M25P80) \ | 136 | #if defined(CONFIG_MTD_M25P80) \ |
| 137 | || defined(CONFIG_MTD_M25P80_MODULE) | 137 | || defined(CONFIG_MTD_M25P80_MODULE) |
| @@ -171,6 +171,7 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { | |||
| 171 | }; | 171 | }; |
| 172 | #endif | 172 | #endif |
| 173 | 173 | ||
| 174 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | ||
| 174 | #if defined(CONFIG_NET_DSA_KSZ8893M) \ | 175 | #if defined(CONFIG_NET_DSA_KSZ8893M) \ |
| 175 | || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) | 176 | || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) |
| 176 | /* SPI SWITCH CHIP */ | 177 | /* SPI SWITCH CHIP */ |
| @@ -179,10 +180,11 @@ static struct bfin5xx_spi_chip spi_switch_info = { | |||
| 179 | .bits_per_word = 8, | 180 | .bits_per_word = 8, |
| 180 | }; | 181 | }; |
| 181 | #endif | 182 | #endif |
| 183 | #endif | ||
| 182 | 184 | ||
| 183 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 185 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 184 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | 186 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
| 185 | .enable_dma = 1, | 187 | .enable_dma = 0, |
| 186 | .bits_per_word = 8, | 188 | .bits_per_word = 8, |
| 187 | }; | 189 | }; |
| 188 | #endif | 190 | #endif |
| @@ -259,6 +261,7 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 259 | }, | 261 | }, |
| 260 | #endif | 262 | #endif |
| 261 | 263 | ||
| 264 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | ||
| 262 | #if defined(CONFIG_NET_DSA_KSZ8893M) \ | 265 | #if defined(CONFIG_NET_DSA_KSZ8893M) \ |
| 263 | || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) | 266 | || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) |
| 264 | { | 267 | { |
| @@ -271,24 +274,15 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 271 | .mode = SPI_MODE_3, | 274 | .mode = SPI_MODE_3, |
| 272 | }, | 275 | }, |
| 273 | #endif | 276 | #endif |
| 277 | #endif | ||
| 274 | 278 | ||
| 275 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 279 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 276 | { | 280 | { |
| 277 | .modalias = "spi_mmc_dummy", | 281 | .modalias = "mmc_spi", |
| 278 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | 282 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ |
| 279 | .bus_num = 0, | 283 | .bus_num = 0, |
| 280 | .chip_select = 0, | 284 | .chip_select = 5, |
| 281 | .platform_data = NULL, | 285 | .controller_data = &mmc_spi_chip_info, |
| 282 | .controller_data = &spi_mmc_chip_info, | ||
| 283 | .mode = SPI_MODE_3, | ||
| 284 | }, | ||
| 285 | { | ||
| 286 | .modalias = "spi_mmc", | ||
| 287 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
| 288 | .bus_num = 0, | ||
| 289 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, | ||
| 290 | .platform_data = NULL, | ||
| 291 | .controller_data = &spi_mmc_chip_info, | ||
| 292 | .mode = SPI_MODE_3, | 286 | .mode = SPI_MODE_3, |
| 293 | }, | 287 | }, |
| 294 | #endif | 288 | #endif |
| @@ -630,11 +624,10 @@ static struct platform_device *stamp_devices[] __initdata = { | |||
| 630 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | 624 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
| 631 | &bfin_mii_bus, | 625 | &bfin_mii_bus, |
| 632 | &bfin_mac_device, | 626 | &bfin_mac_device, |
| 633 | #endif | ||
| 634 | |||
| 635 | #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) | 627 | #if defined(CONFIG_NET_DSA_KSZ8893M) || defined(CONFIG_NET_DSA_KSZ8893M_MODULE) |
| 636 | &ksz8893m_switch_device, | 628 | &ksz8893m_switch_device, |
| 637 | #endif | 629 | #endif |
| 630 | #endif | ||
| 638 | 631 | ||
| 639 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | 632 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
| 640 | &bfin_spi0_device, | 633 | &bfin_spi0_device, |
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h index e5b4bef0edae..c847bb101076 100644 --- a/arch/blackfin/mach-bf518/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h | |||
| @@ -2,12 +2,12 @@ | |||
| 2 | * File: include/asm-blackfin/mach-bf518/anomaly.h | 2 | * File: include/asm-blackfin/mach-bf518/anomaly.h |
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 4 | * | 4 | * |
| 5 | * Copyright (C) 2004-2008 Analog Devices Inc. | 5 | * Copyright (C) 2004-2009 Analog Devices Inc. |
| 6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* This file shoule be up to date with: | 9 | /* This file shoule be up to date with: |
| 10 | * - ???? | 10 | * - Revision B, 02/03/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #ifndef _MACH_ANOMALY_H_ | 13 | #ifndef _MACH_ANOMALY_H_ |
| @@ -19,6 +19,8 @@ | |||
| 19 | #define ANOMALY_05000122 (1) | 19 | #define ANOMALY_05000122 (1) |
| 20 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ | 20 | /* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
| 21 | #define ANOMALY_05000245 (1) | 21 | #define ANOMALY_05000245 (1) |
| 22 | /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */ | ||
| 23 | #define ANOMALY_05000254 (1) | ||
| 22 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | 24 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
| 23 | #define ANOMALY_05000265 (1) | 25 | #define ANOMALY_05000265 (1) |
| 24 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ | 26 | /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
| @@ -53,6 +55,12 @@ | |||
| 53 | #define ANOMALY_05000443 (1) | 55 | #define ANOMALY_05000443 (1) |
| 54 | /* Incorrect L1 Instruction Bank B Memory Map Location */ | 56 | /* Incorrect L1 Instruction Bank B Memory Map Location */ |
| 55 | #define ANOMALY_05000444 (1) | 57 | #define ANOMALY_05000444 (1) |
| 58 | /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */ | ||
| 59 | #define ANOMALY_05000452 (1) | ||
| 60 | /* PWM_TRIPB Signal Not Available on PG10 */ | ||
| 61 | #define ANOMALY_05000453 (1) | ||
| 62 | /* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */ | ||
| 63 | #define ANOMALY_05000455 (1) | ||
| 56 | 64 | ||
| 57 | /* Anomalies that don't exist on this proc */ | 65 | /* Anomalies that don't exist on this proc */ |
| 58 | #define ANOMALY_05000125 (0) | 66 | #define ANOMALY_05000125 (0) |
| @@ -65,15 +73,20 @@ | |||
| 65 | #define ANOMALY_05000263 (0) | 73 | #define ANOMALY_05000263 (0) |
| 66 | #define ANOMALY_05000266 (0) | 74 | #define ANOMALY_05000266 (0) |
| 67 | #define ANOMALY_05000273 (0) | 75 | #define ANOMALY_05000273 (0) |
| 76 | #define ANOMALY_05000278 (0) | ||
| 68 | #define ANOMALY_05000285 (0) | 77 | #define ANOMALY_05000285 (0) |
| 78 | #define ANOMALY_05000305 (0) | ||
| 69 | #define ANOMALY_05000307 (0) | 79 | #define ANOMALY_05000307 (0) |
| 70 | #define ANOMALY_05000311 (0) | 80 | #define ANOMALY_05000311 (0) |
| 71 | #define ANOMALY_05000312 (0) | 81 | #define ANOMALY_05000312 (0) |
| 72 | #define ANOMALY_05000323 (0) | 82 | #define ANOMALY_05000323 (0) |
| 73 | #define ANOMALY_05000353 (0) | 83 | #define ANOMALY_05000353 (0) |
| 74 | #define ANOMALY_05000363 (0) | 84 | #define ANOMALY_05000363 (0) |
| 85 | #define ANOMALY_05000380 (0) | ||
| 75 | #define ANOMALY_05000386 (0) | 86 | #define ANOMALY_05000386 (0) |
| 76 | #define ANOMALY_05000412 (0) | 87 | #define ANOMALY_05000412 (0) |
| 77 | #define ANOMALY_05000432 (0) | 88 | #define ANOMALY_05000432 (0) |
| 89 | #define ANOMALY_05000447 (0) | ||
| 90 | #define ANOMALY_05000448 (0) | ||
| 78 | 91 | ||
| 79 | #endif | 92 | #endif |
diff --git a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h index b50a63b975a2..e21c1c3e4ec7 100644 --- a/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf518/include/mach/bfin_serial_5xx.h | |||
| @@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = { | |||
| 144 | CH_UART0_TX, | 144 | CH_UART0_TX, |
| 145 | CH_UART0_RX, | 145 | CH_UART0_RX, |
| 146 | #endif | 146 | #endif |
| 147 | #ifdef CONFIG_BFIN_UART0_CTSRTS | 147 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 148 | CONFIG_UART0_CTS_PIN, | 148 | CONFIG_UART0_CTS_PIN, |
| 149 | CONFIG_UART0_RTS_PIN, | 149 | CONFIG_UART0_RTS_PIN, |
| 150 | #endif | 150 | #endif |
| @@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = { | |||
| 158 | CH_UART1_TX, | 158 | CH_UART1_TX, |
| 159 | CH_UART1_RX, | 159 | CH_UART1_RX, |
| 160 | #endif | 160 | #endif |
| 161 | #ifdef CONFIG_BFIN_UART1_CTSRTS | 161 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 162 | CONFIG_UART1_CTS_PIN, | 162 | CONFIG_UART1_CTS_PIN, |
| 163 | CONFIG_UART1_RTS_PIN, | 163 | CONFIG_UART1_RTS_PIN, |
| 164 | #endif | 164 | #endif |
diff --git a/arch/blackfin/mach-bf527/boards/cm_bf527.c b/arch/blackfin/mach-bf527/boards/cm_bf527.c index 856c097b5317..48e69eecdba4 100644 --- a/arch/blackfin/mach-bf527/boards/cm_bf527.c +++ b/arch/blackfin/mach-bf527/boards/cm_bf527.c | |||
| @@ -487,9 +487,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | |||
| 487 | }; | 487 | }; |
| 488 | #endif | 488 | #endif |
| 489 | 489 | ||
| 490 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 490 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 491 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | 491 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
| 492 | .enable_dma = 1, | 492 | .enable_dma = 0, |
| 493 | .bits_per_word = 8, | 493 | .bits_per_word = 8, |
| 494 | }; | 494 | }; |
| 495 | #endif | 495 | #endif |
| @@ -585,23 +585,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 585 | .controller_data = &ad9960_spi_chip_info, | 585 | .controller_data = &ad9960_spi_chip_info, |
| 586 | }, | 586 | }, |
| 587 | #endif | 587 | #endif |
| 588 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 588 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 589 | { | 589 | { |
| 590 | .modalias = "spi_mmc_dummy", | 590 | .modalias = "mmc_spi", |
| 591 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | 591 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ |
| 592 | .bus_num = 0, | ||
| 593 | .chip_select = 0, | ||
| 594 | .platform_data = NULL, | ||
| 595 | .controller_data = &spi_mmc_chip_info, | ||
| 596 | .mode = SPI_MODE_3, | ||
| 597 | }, | ||
| 598 | { | ||
| 599 | .modalias = "spi_mmc", | ||
| 600 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
| 601 | .bus_num = 0, | 592 | .bus_num = 0, |
| 602 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, | 593 | .chip_select = 5, |
| 603 | .platform_data = NULL, | 594 | .controller_data = &mmc_spi_chip_info, |
| 604 | .controller_data = &spi_mmc_chip_info, | ||
| 605 | .mode = SPI_MODE_3, | 595 | .mode = SPI_MODE_3, |
| 606 | }, | 596 | }, |
| 607 | #endif | 597 | #endif |
diff --git a/arch/blackfin/mach-bf527/boards/ezbrd.c b/arch/blackfin/mach-bf527/boards/ezbrd.c index 83606fcdde27..7fe480e4ebe8 100644 --- a/arch/blackfin/mach-bf527/boards/ezbrd.c +++ b/arch/blackfin/mach-bf527/boards/ezbrd.c | |||
| @@ -256,9 +256,9 @@ static struct bfin5xx_spi_chip spi_adc_chip_info = { | |||
| 256 | }; | 256 | }; |
| 257 | #endif | 257 | #endif |
| 258 | 258 | ||
| 259 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 259 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 260 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | 260 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
| 261 | .enable_dma = 1, | 261 | .enable_dma = 0, |
| 262 | .bits_per_word = 8, | 262 | .bits_per_word = 8, |
| 263 | }; | 263 | }; |
| 264 | #endif | 264 | #endif |
| @@ -366,23 +366,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 366 | }, | 366 | }, |
| 367 | #endif | 367 | #endif |
| 368 | 368 | ||
| 369 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 369 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 370 | { | 370 | { |
| 371 | .modalias = "spi_mmc_dummy", | 371 | .modalias = "mmc_spi", |
| 372 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | 372 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ |
| 373 | .bus_num = 0, | 373 | .bus_num = 0, |
| 374 | .chip_select = 0, | 374 | .chip_select = 5, |
| 375 | .platform_data = NULL, | 375 | .controller_data = &mmc_spi_chip_info, |
| 376 | .controller_data = &spi_mmc_chip_info, | ||
| 377 | .mode = SPI_MODE_3, | ||
| 378 | }, | ||
| 379 | { | ||
| 380 | .modalias = "spi_mmc", | ||
| 381 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
| 382 | .bus_num = 0, | ||
| 383 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, | ||
| 384 | .platform_data = NULL, | ||
| 385 | .controller_data = &spi_mmc_chip_info, | ||
| 386 | .mode = SPI_MODE_3, | 376 | .mode = SPI_MODE_3, |
| 387 | }, | 377 | }, |
| 388 | #endif | 378 | #endif |
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h index 035e8d835058..df6808d8a6ef 100644 --- a/arch/blackfin/mach-bf527/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * File: include/asm-blackfin/mach-bf527/anomaly.h | 2 | * File: include/asm-blackfin/mach-bf527/anomaly.h |
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 4 | * | 4 | * |
| 5 | * Copyright (C) 2004-2008 Analog Devices Inc. | 5 | * Copyright (C) 2004-2009 Analog Devices Inc. |
| 6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| @@ -167,12 +167,16 @@ | |||
| 167 | #define ANOMALY_05000263 (0) | 167 | #define ANOMALY_05000263 (0) |
| 168 | #define ANOMALY_05000266 (0) | 168 | #define ANOMALY_05000266 (0) |
| 169 | #define ANOMALY_05000273 (0) | 169 | #define ANOMALY_05000273 (0) |
| 170 | #define ANOMALY_05000278 (0) | ||
| 170 | #define ANOMALY_05000285 (0) | 171 | #define ANOMALY_05000285 (0) |
| 172 | #define ANOMALY_05000305 (0) | ||
| 171 | #define ANOMALY_05000307 (0) | 173 | #define ANOMALY_05000307 (0) |
| 172 | #define ANOMALY_05000311 (0) | 174 | #define ANOMALY_05000311 (0) |
| 173 | #define ANOMALY_05000312 (0) | 175 | #define ANOMALY_05000312 (0) |
| 174 | #define ANOMALY_05000323 (0) | 176 | #define ANOMALY_05000323 (0) |
| 175 | #define ANOMALY_05000363 (0) | 177 | #define ANOMALY_05000363 (0) |
| 176 | #define ANOMALY_05000412 (0) | 178 | #define ANOMALY_05000412 (0) |
| 179 | #define ANOMALY_05000447 (0) | ||
| 180 | #define ANOMALY_05000448 (0) | ||
| 177 | 181 | ||
| 178 | #endif | 182 | #endif |
diff --git a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h index 75722d6008b0..e8c41fd842b5 100644 --- a/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf527/include/mach/bfin_serial_5xx.h | |||
| @@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = { | |||
| 144 | CH_UART0_TX, | 144 | CH_UART0_TX, |
| 145 | CH_UART0_RX, | 145 | CH_UART0_RX, |
| 146 | #endif | 146 | #endif |
| 147 | #ifdef CONFIG_BFIN_UART0_CTSRTS | 147 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 148 | CONFIG_UART0_CTS_PIN, | 148 | CONFIG_UART0_CTS_PIN, |
| 149 | CONFIG_UART0_RTS_PIN, | 149 | CONFIG_UART0_RTS_PIN, |
| 150 | #endif | 150 | #endif |
| @@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = { | |||
| 158 | CH_UART1_TX, | 158 | CH_UART1_TX, |
| 159 | CH_UART1_RX, | 159 | CH_UART1_RX, |
| 160 | #endif | 160 | #endif |
| 161 | #ifdef CONFIG_BFIN_UART1_CTSRTS | 161 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 162 | CONFIG_UART1_CTS_PIN, | 162 | CONFIG_UART1_CTS_PIN, |
| 163 | CONFIG_UART1_RTS_PIN, | 163 | CONFIG_UART1_RTS_PIN, |
| 164 | #endif | 164 | #endif |
diff --git a/arch/blackfin/mach-bf533/boards/Kconfig b/arch/blackfin/mach-bf533/boards/Kconfig index 308c98dc5aba..8d8b3e7321e6 100644 --- a/arch/blackfin/mach-bf533/boards/Kconfig +++ b/arch/blackfin/mach-bf533/boards/Kconfig | |||
| @@ -38,9 +38,4 @@ config BFIN532_IP0X | |||
| 38 | help | 38 | help |
| 39 | Core support for IP04/IP04 open hardware IP-PBX. | 39 | Core support for IP04/IP04 open hardware IP-PBX. |
| 40 | 40 | ||
| 41 | config GENERIC_BF533_BOARD | ||
| 42 | bool "Generic" | ||
| 43 | help | ||
| 44 | Generic or Custom board support. | ||
| 45 | |||
| 46 | endchoice | 41 | endchoice |
diff --git a/arch/blackfin/mach-bf533/boards/Makefile b/arch/blackfin/mach-bf533/boards/Makefile index 9afbe72b484f..ff1e832f80d2 100644 --- a/arch/blackfin/mach-bf533/boards/Makefile +++ b/arch/blackfin/mach-bf533/boards/Makefile | |||
| @@ -2,7 +2,6 @@ | |||
| 2 | # arch/blackfin/mach-bf533/boards/Makefile | 2 | # arch/blackfin/mach-bf533/boards/Makefile |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | obj-$(CONFIG_GENERIC_BF533_BOARD) += generic_board.o | ||
| 6 | obj-$(CONFIG_BFIN533_STAMP) += stamp.o | 5 | obj-$(CONFIG_BFIN533_STAMP) += stamp.o |
| 7 | obj-$(CONFIG_BFIN532_IP0X) += ip0x.o | 6 | obj-$(CONFIG_BFIN532_IP0X) += ip0x.o |
| 8 | obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o | 7 | obj-$(CONFIG_BFIN533_EZKIT) += ezkit.o |
diff --git a/arch/blackfin/mach-bf533/boards/blackstamp.c b/arch/blackfin/mach-bf533/boards/blackstamp.c index 015c18f85e7f..0765872a8ada 100644 --- a/arch/blackfin/mach-bf533/boards/blackstamp.c +++ b/arch/blackfin/mach-bf533/boards/blackstamp.c | |||
| @@ -101,9 +101,9 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { | |||
| 101 | }; | 101 | }; |
| 102 | #endif | 102 | #endif |
| 103 | 103 | ||
| 104 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 104 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 105 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | 105 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
| 106 | .enable_dma = 1, | 106 | .enable_dma = 0, |
| 107 | .bits_per_word = 8, | 107 | .bits_per_word = 8, |
| 108 | }; | 108 | }; |
| 109 | #endif | 109 | #endif |
| @@ -129,23 +129,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 129 | }, | 129 | }, |
| 130 | #endif | 130 | #endif |
| 131 | 131 | ||
| 132 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 132 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 133 | { | ||
| 134 | .modalias = "spi_mmc_dummy", | ||
| 135 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | ||
| 136 | .bus_num = 0, | ||
| 137 | .chip_select = 0, | ||
| 138 | .platform_data = NULL, | ||
| 139 | .controller_data = &spi_mmc_chip_info, | ||
| 140 | .mode = SPI_MODE_3, | ||
| 141 | }, | ||
| 142 | { | 133 | { |
| 143 | .modalias = "spi_mmc", | 134 | .modalias = "mmc_spi", |
| 144 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ | 135 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ |
| 145 | .bus_num = 0, | 136 | .bus_num = 0, |
| 146 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, | 137 | .chip_select = 5, |
| 147 | .platform_data = NULL, | 138 | .controller_data = &mmc_spi_chip_info, |
| 148 | .controller_data = &spi_mmc_chip_info, | ||
| 149 | .mode = SPI_MODE_3, | 139 | .mode = SPI_MODE_3, |
| 150 | }, | 140 | }, |
| 151 | #endif | 141 | #endif |
diff --git a/arch/blackfin/mach-bf533/boards/cm_bf533.c b/arch/blackfin/mach-bf533/boards/cm_bf533.c index e7061c7e8c42..e8974878d8c2 100644 --- a/arch/blackfin/mach-bf533/boards/cm_bf533.c +++ b/arch/blackfin/mach-bf533/boards/cm_bf533.c | |||
| @@ -96,9 +96,9 @@ static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | |||
| 96 | }; | 96 | }; |
| 97 | #endif | 97 | #endif |
| 98 | 98 | ||
| 99 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 99 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 100 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | 100 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
| 101 | .enable_dma = 1, | 101 | .enable_dma = 0, |
| 102 | .bits_per_word = 8, | 102 | .bits_per_word = 8, |
| 103 | }; | 103 | }; |
| 104 | #endif | 104 | #endif |
| @@ -138,23 +138,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 138 | }, | 138 | }, |
| 139 | #endif | 139 | #endif |
| 140 | 140 | ||
| 141 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 141 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 142 | { | ||
| 143 | .modalias = "spi_mmc_dummy", | ||
| 144 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
| 145 | .bus_num = 0, | ||
| 146 | .chip_select = 0, | ||
| 147 | .platform_data = NULL, | ||
| 148 | .controller_data = &spi_mmc_chip_info, | ||
| 149 | .mode = SPI_MODE_3, | ||
| 150 | }, | ||
| 151 | { | 142 | { |
| 152 | .modalias = "spi_mmc", | 143 | .modalias = "mmc_spi", |
| 153 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | 144 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ |
| 154 | .bus_num = 0, | 145 | .bus_num = 0, |
| 155 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, | 146 | .chip_select = 5, |
| 156 | .platform_data = NULL, | 147 | .controller_data = &mmc_spi_chip_info, |
| 157 | .controller_data = &spi_mmc_chip_info, | ||
| 158 | .mode = SPI_MODE_3, | 148 | .mode = SPI_MODE_3, |
| 159 | }, | 149 | }, |
| 160 | #endif | 150 | #endif |
diff --git a/arch/blackfin/mach-bf533/boards/generic_board.c b/arch/blackfin/mach-bf533/boards/generic_board.c deleted file mode 100644 index 986eeec53b1f..000000000000 --- a/arch/blackfin/mach-bf533/boards/generic_board.c +++ /dev/null | |||
| @@ -1,126 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf533/generic_board.c | ||
| 3 | * Based on: arch/blackfin/mach-bf533/ezkit.c | ||
| 4 | * Author: Aidan Williams <aidan@nicta.com.au> | ||
| 5 | * | ||
| 6 | * Created: 2005 | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2005 National ICT Australia (NICTA) | ||
| 11 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2 of the License, or | ||
| 18 | * (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; if not, see the file COPYING, or write | ||
| 27 | * to the Free Software Foundation, Inc., | ||
| 28 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 29 | */ | ||
| 30 | |||
| 31 | #include <linux/device.h> | ||
| 32 | #include <linux/platform_device.h> | ||
| 33 | #include <linux/irq.h> | ||
| 34 | |||
| 35 | /* | ||
| 36 | * Name the Board for the /proc/cpuinfo | ||
| 37 | */ | ||
| 38 | const char bfin_board_name[] = "UNKNOWN BOARD"; | ||
| 39 | |||
| 40 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | ||
| 41 | static struct platform_device rtc_device = { | ||
| 42 | .name = "rtc-bfin", | ||
| 43 | .id = -1, | ||
| 44 | }; | ||
| 45 | #endif | ||
| 46 | |||
| 47 | /* | ||
| 48 | * Driver needs to know address, irq and flag pin. | ||
| 49 | */ | ||
| 50 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | ||
| 51 | static struct resource smc91x_resources[] = { | ||
| 52 | { | ||
| 53 | .start = 0x20300300, | ||
| 54 | .end = 0x20300300 + 16, | ||
| 55 | .flags = IORESOURCE_MEM, | ||
| 56 | }, { | ||
| 57 | .start = IRQ_PROG_INTB, | ||
| 58 | .end = IRQ_PROG_INTB, | ||
| 59 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | ||
| 60 | }, { | ||
| 61 | .start = IRQ_PF7, | ||
| 62 | .end = IRQ_PF7, | ||
| 63 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | ||
| 64 | }, | ||
| 65 | }; | ||
| 66 | |||
| 67 | static struct platform_device smc91x_device = { | ||
| 68 | .name = "smc91x", | ||
| 69 | .id = 0, | ||
| 70 | .num_resources = ARRAY_SIZE(smc91x_resources), | ||
| 71 | .resource = smc91x_resources, | ||
| 72 | }; | ||
| 73 | #endif | ||
| 74 | |||
| 75 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
| 76 | #ifdef CONFIG_BFIN_SIR0 | ||
| 77 | static struct resource bfin_sir0_resources[] = { | ||
| 78 | { | ||
| 79 | .start = 0xFFC00400, | ||
| 80 | .end = 0xFFC004FF, | ||
| 81 | .flags = IORESOURCE_MEM, | ||
| 82 | }, | ||
| 83 | { | ||
| 84 | .start = IRQ_UART0_RX, | ||
| 85 | .end = IRQ_UART0_RX+1, | ||
| 86 | .flags = IORESOURCE_IRQ, | ||
| 87 | }, | ||
| 88 | { | ||
| 89 | .start = CH_UART0_RX, | ||
| 90 | .end = CH_UART0_RX+1, | ||
| 91 | .flags = IORESOURCE_DMA, | ||
| 92 | }, | ||
| 93 | }; | ||
| 94 | |||
| 95 | static struct platform_device bfin_sir0_device = { | ||
| 96 | .name = "bfin_sir", | ||
| 97 | .id = 0, | ||
| 98 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 99 | .resource = bfin_sir0_resources, | ||
| 100 | }; | ||
| 101 | #endif | ||
| 102 | #endif | ||
| 103 | |||
| 104 | static struct platform_device *generic_board_devices[] __initdata = { | ||
| 105 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | ||
| 106 | &rtc_device, | ||
| 107 | #endif | ||
| 108 | |||
| 109 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | ||
| 110 | &smc91x_device, | ||
| 111 | #endif | ||
| 112 | |||
| 113 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
| 114 | #ifdef CONFIG_BFIN_SIR0 | ||
| 115 | &bfin_sir0_device, | ||
| 116 | #endif | ||
| 117 | #endif | ||
| 118 | }; | ||
| 119 | |||
| 120 | static int __init generic_board_init(void) | ||
| 121 | { | ||
| 122 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | ||
| 123 | return platform_add_devices(generic_board_devices, ARRAY_SIZE(generic_board_devices)); | ||
| 124 | } | ||
| 125 | |||
| 126 | arch_initcall(generic_board_init); | ||
diff --git a/arch/blackfin/mach-bf533/boards/ip0x.c b/arch/blackfin/mach-bf533/boards/ip0x.c index e30b1b7d1442..f19b63378b12 100644 --- a/arch/blackfin/mach-bf533/boards/ip0x.c +++ b/arch/blackfin/mach-bf533/boards/ip0x.c | |||
| @@ -127,8 +127,8 @@ static struct platform_device dm9000_device2 = { | |||
| 127 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | 127 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) |
| 128 | /* all SPI peripherals info goes here */ | 128 | /* all SPI peripherals info goes here */ |
| 129 | 129 | ||
| 130 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 130 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 131 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | 131 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
| 132 | /* | 132 | /* |
| 133 | * CPOL (Clock Polarity) | 133 | * CPOL (Clock Polarity) |
| 134 | * 0 - Active high SCK | 134 | * 0 - Active high SCK |
| @@ -152,14 +152,13 @@ static struct bfin5xx_spi_chip spi_mmc_chip_info = { | |||
| 152 | /* Notice: for blackfin, the speed_hz is the value of register | 152 | /* Notice: for blackfin, the speed_hz is the value of register |
| 153 | * SPI_BAUD, not the real baudrate */ | 153 | * SPI_BAUD, not the real baudrate */ |
| 154 | static struct spi_board_info bfin_spi_board_info[] __initdata = { | 154 | static struct spi_board_info bfin_spi_board_info[] __initdata = { |
| 155 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 155 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 156 | { | 156 | { |
| 157 | .modalias = "spi_mmc", | 157 | .modalias = "mmc_spi", |
| 158 | .max_speed_hz = 2, | 158 | .max_speed_hz = 2, |
| 159 | .bus_num = 1, | 159 | .bus_num = 1, |
| 160 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, | 160 | .chip_select = 5, |
| 161 | .platform_data = NULL, | 161 | .controller_data = &mmc_spi_chip_info, |
| 162 | .controller_data = &spi_mmc_chip_info, | ||
| 163 | }, | 162 | }, |
| 164 | #endif | 163 | #endif |
| 165 | }; | 164 | }; |
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h index 0d3a03429fb9..1cf893e2e55b 100644 --- a/arch/blackfin/mach-bf533/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * File: include/asm-blackfin/mach-bf533/anomaly.h | 2 | * File: include/asm-blackfin/mach-bf533/anomaly.h |
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 4 | * | 4 | * |
| 5 | * Copyright (C) 2004-2008 Analog Devices Inc. | 5 | * Copyright (C) 2004-2009 Analog Devices Inc. |
| 6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| @@ -160,7 +160,7 @@ | |||
| 160 | #define ANOMALY_05000301 (__SILICON_REVISION__ < 6) | 160 | #define ANOMALY_05000301 (__SILICON_REVISION__ < 6) |
| 161 | /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ | 161 | /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ |
| 162 | #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) | 162 | #define ANOMALY_05000302 (__SILICON_REVISION__ < 5) |
| 163 | /* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ | 163 | /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ |
| 164 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) | 164 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) |
| 165 | /* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ | 165 | /* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ |
| 166 | #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) | 166 | #define ANOMALY_05000306 (__SILICON_REVISION__ < 5) |
| @@ -278,9 +278,12 @@ | |||
| 278 | #define ANOMALY_05000266 (0) | 278 | #define ANOMALY_05000266 (0) |
| 279 | #define ANOMALY_05000323 (0) | 279 | #define ANOMALY_05000323 (0) |
| 280 | #define ANOMALY_05000353 (1) | 280 | #define ANOMALY_05000353 (1) |
| 281 | #define ANOMALY_05000380 (0) | ||
| 281 | #define ANOMALY_05000386 (1) | 282 | #define ANOMALY_05000386 (1) |
| 282 | #define ANOMALY_05000412 (0) | 283 | #define ANOMALY_05000412 (0) |
| 283 | #define ANOMALY_05000432 (0) | 284 | #define ANOMALY_05000432 (0) |
| 284 | #define ANOMALY_05000435 (0) | 285 | #define ANOMALY_05000435 (0) |
| 286 | #define ANOMALY_05000447 (0) | ||
| 287 | #define ANOMALY_05000448 (0) | ||
| 285 | 288 | ||
| 286 | #endif | 289 | #endif |
diff --git a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h index f3d9e495230c..5f517f53b0fd 100644 --- a/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf533/include/mach/bfin_serial_5xx.h | |||
| @@ -134,7 +134,7 @@ struct bfin_serial_res bfin_serial_resource[] = { | |||
| 134 | CH_UART_TX, | 134 | CH_UART_TX, |
| 135 | CH_UART_RX, | 135 | CH_UART_RX, |
| 136 | #endif | 136 | #endif |
| 137 | #ifdef CONFIG_BFIN_UART0_CTSRTS | 137 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 138 | CONFIG_UART0_CTS_PIN, | 138 | CONFIG_UART0_CTS_PIN, |
| 139 | CONFIG_UART0_RTS_PIN, | 139 | CONFIG_UART0_RTS_PIN, |
| 140 | #endif | 140 | #endif |
diff --git a/arch/blackfin/mach-bf537/boards/Kconfig b/arch/blackfin/mach-bf537/boards/Kconfig index 42a57b0acb29..77c59da87e85 100644 --- a/arch/blackfin/mach-bf537/boards/Kconfig +++ b/arch/blackfin/mach-bf537/boards/Kconfig | |||
| @@ -33,9 +33,4 @@ config CAMSIG_MINOTAUR | |||
| 33 | help | 33 | help |
| 34 | Board supply package for CSP Minotaur | 34 | Board supply package for CSP Minotaur |
| 35 | 35 | ||
| 36 | config GENERIC_BF537_BOARD | ||
| 37 | bool "Generic" | ||
| 38 | help | ||
| 39 | Generic or Custom board support. | ||
| 40 | |||
| 41 | endchoice | 36 | endchoice |
diff --git a/arch/blackfin/mach-bf537/boards/Makefile b/arch/blackfin/mach-bf537/boards/Makefile index 7168cc14afd8..68b98a7af6a6 100644 --- a/arch/blackfin/mach-bf537/boards/Makefile +++ b/arch/blackfin/mach-bf537/boards/Makefile | |||
| @@ -2,7 +2,6 @@ | |||
| 2 | # arch/blackfin/mach-bf537/boards/Makefile | 2 | # arch/blackfin/mach-bf537/boards/Makefile |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | obj-$(CONFIG_GENERIC_BF537_BOARD) += generic_board.o | ||
| 6 | obj-$(CONFIG_BFIN537_STAMP) += stamp.o | 5 | obj-$(CONFIG_BFIN537_STAMP) += stamp.o |
| 7 | obj-$(CONFIG_BFIN537_BLUETECHNIX_CM) += cm_bf537.o | 6 | obj-$(CONFIG_BFIN537_BLUETECHNIX_CM) += cm_bf537.o |
| 8 | obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o | 7 | obj-$(CONFIG_BFIN537_BLUETECHNIX_TCM) += tcm_bf537.o |
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537.c b/arch/blackfin/mach-bf537/boards/cm_bf537.c index 9cd8fb2a30d3..41c75b9bfac0 100644 --- a/arch/blackfin/mach-bf537/boards/cm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/cm_bf537.c | |||
| @@ -108,9 +108,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | |||
| 108 | }; | 108 | }; |
| 109 | #endif | 109 | #endif |
| 110 | 110 | ||
| 111 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 111 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 112 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | 112 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
| 113 | .enable_dma = 1, | 113 | .enable_dma = 0, |
| 114 | .bits_per_word = 8, | 114 | .bits_per_word = 8, |
| 115 | }; | 115 | }; |
| 116 | #endif | 116 | #endif |
| @@ -160,23 +160,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 160 | }, | 160 | }, |
| 161 | #endif | 161 | #endif |
| 162 | 162 | ||
| 163 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 163 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 164 | { | ||
| 165 | .modalias = "spi_mmc_dummy", | ||
| 166 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
| 167 | .bus_num = 0, | ||
| 168 | .chip_select = 7, | ||
| 169 | .platform_data = NULL, | ||
| 170 | .controller_data = &spi_mmc_chip_info, | ||
| 171 | .mode = SPI_MODE_3, | ||
| 172 | }, | ||
| 173 | { | 164 | { |
| 174 | .modalias = "spi_mmc", | 165 | .modalias = "mmc_spi", |
| 175 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | 166 | .max_speed_hz = 20000000, /* max spi clock (SCK) speed in HZ */ |
| 176 | .bus_num = 0, | 167 | .bus_num = 0, |
| 177 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, | 168 | .chip_select = 1, |
| 178 | .platform_data = NULL, | 169 | .controller_data = &mmc_spi_chip_info, |
| 179 | .controller_data = &spi_mmc_chip_info, | ||
| 180 | .mode = SPI_MODE_3, | 170 | .mode = SPI_MODE_3, |
| 181 | }, | 171 | }, |
| 182 | #endif | 172 | #endif |
diff --git a/arch/blackfin/mach-bf537/boards/generic_board.c b/arch/blackfin/mach-bf537/boards/generic_board.c deleted file mode 100644 index da710fdc4569..000000000000 --- a/arch/blackfin/mach-bf537/boards/generic_board.c +++ /dev/null | |||
| @@ -1,745 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf537/boards/generic_board.c | ||
| 3 | * Based on: arch/blackfin/mach-bf533/boards/ezkit.c | ||
| 4 | * Author: Aidan Williams <aidan@nicta.com.au> | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2005 National ICT Australia (NICTA) | ||
| 11 | * Copyright 2004-2008 Analog Devices Inc. | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2 of the License, or | ||
| 18 | * (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; if not, see the file COPYING, or write | ||
| 27 | * to the Free Software Foundation, Inc., | ||
| 28 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 29 | */ | ||
| 30 | |||
| 31 | #include <linux/device.h> | ||
| 32 | #include <linux/etherdevice.h> | ||
| 33 | #include <linux/platform_device.h> | ||
| 34 | #include <linux/mtd/mtd.h> | ||
| 35 | #include <linux/mtd/partitions.h> | ||
| 36 | #include <linux/spi/spi.h> | ||
| 37 | #include <linux/spi/flash.h> | ||
| 38 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | ||
| 39 | #include <linux/usb/isp1362.h> | ||
| 40 | #endif | ||
| 41 | #include <linux/irq.h> | ||
| 42 | #include <linux/interrupt.h> | ||
| 43 | #include <linux/usb/sl811.h> | ||
| 44 | #include <asm/dma.h> | ||
| 45 | #include <asm/bfin5xx_spi.h> | ||
| 46 | #include <asm/reboot.h> | ||
| 47 | #include <asm/portmux.h> | ||
| 48 | #include <linux/spi/ad7877.h> | ||
| 49 | |||
| 50 | /* | ||
| 51 | * Name the Board for the /proc/cpuinfo | ||
| 52 | */ | ||
| 53 | const char bfin_board_name[] = "UNKNOWN BOARD"; | ||
| 54 | |||
| 55 | /* | ||
| 56 | * Driver needs to know address, irq and flag pin. | ||
| 57 | */ | ||
| 58 | |||
| 59 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) | ||
| 60 | #include <linux/usb/isp1760.h> | ||
| 61 | static struct resource bfin_isp1760_resources[] = { | ||
| 62 | [0] = { | ||
| 63 | .start = 0x203C0000, | ||
| 64 | .end = 0x203C0000 + 0x000fffff, | ||
| 65 | .flags = IORESOURCE_MEM, | ||
| 66 | }, | ||
| 67 | [1] = { | ||
| 68 | .start = IRQ_PF7, | ||
| 69 | .end = IRQ_PF7, | ||
| 70 | .flags = IORESOURCE_IRQ, | ||
| 71 | }, | ||
| 72 | }; | ||
| 73 | |||
| 74 | static struct isp1760_platform_data isp1760_priv = { | ||
| 75 | .is_isp1761 = 0, | ||
| 76 | .port1_disable = 0, | ||
| 77 | .bus_width_16 = 1, | ||
| 78 | .port1_otg = 0, | ||
| 79 | .analog_oc = 0, | ||
| 80 | .dack_polarity_high = 0, | ||
| 81 | .dreq_polarity_high = 0, | ||
| 82 | }; | ||
| 83 | |||
| 84 | static struct platform_device bfin_isp1760_device = { | ||
| 85 | .name = "isp1760-hcd", | ||
| 86 | .id = 0, | ||
| 87 | .dev = { | ||
| 88 | .platform_data = &isp1760_priv, | ||
| 89 | }, | ||
| 90 | .num_resources = ARRAY_SIZE(bfin_isp1760_resources), | ||
| 91 | .resource = bfin_isp1760_resources, | ||
| 92 | }; | ||
| 93 | #endif | ||
| 94 | |||
| 95 | #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) | ||
| 96 | static struct resource bfin_pcmcia_cf_resources[] = { | ||
| 97 | { | ||
| 98 | .start = 0x20310000, /* IO PORT */ | ||
| 99 | .end = 0x20312000, | ||
| 100 | .flags = IORESOURCE_MEM, | ||
| 101 | }, { | ||
| 102 | .start = 0x20311000, /* Attribute Memory */ | ||
| 103 | .end = 0x20311FFF, | ||
| 104 | .flags = IORESOURCE_MEM, | ||
| 105 | }, { | ||
| 106 | .start = IRQ_PF4, | ||
| 107 | .end = IRQ_PF4, | ||
| 108 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | ||
| 109 | }, { | ||
| 110 | .start = 6, /* Card Detect PF6 */ | ||
| 111 | .end = 6, | ||
| 112 | .flags = IORESOURCE_IRQ, | ||
| 113 | }, | ||
| 114 | }; | ||
| 115 | |||
| 116 | static struct platform_device bfin_pcmcia_cf_device = { | ||
| 117 | .name = "bfin_cf_pcmcia", | ||
| 118 | .id = -1, | ||
| 119 | .num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources), | ||
| 120 | .resource = bfin_pcmcia_cf_resources, | ||
| 121 | }; | ||
| 122 | #endif | ||
| 123 | |||
| 124 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | ||
| 125 | static struct platform_device rtc_device = { | ||
| 126 | .name = "rtc-bfin", | ||
| 127 | .id = -1, | ||
| 128 | }; | ||
| 129 | #endif | ||
| 130 | |||
| 131 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | ||
| 132 | static struct resource smc91x_resources[] = { | ||
| 133 | { | ||
| 134 | .name = "smc91x-regs", | ||
| 135 | .start = 0x20300300, | ||
| 136 | .end = 0x20300300 + 16, | ||
| 137 | .flags = IORESOURCE_MEM, | ||
| 138 | }, { | ||
| 139 | |||
| 140 | .start = IRQ_PF7, | ||
| 141 | .end = IRQ_PF7, | ||
| 142 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | ||
| 143 | }, | ||
| 144 | }; | ||
| 145 | static struct platform_device smc91x_device = { | ||
| 146 | .name = "smc91x", | ||
| 147 | .id = 0, | ||
| 148 | .num_resources = ARRAY_SIZE(smc91x_resources), | ||
| 149 | .resource = smc91x_resources, | ||
| 150 | }; | ||
| 151 | #endif | ||
| 152 | |||
| 153 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) | ||
| 154 | static struct resource dm9000_resources[] = { | ||
| 155 | [0] = { | ||
| 156 | .start = 0x203FB800, | ||
| 157 | .end = 0x203FB800 + 1, | ||
| 158 | .flags = IORESOURCE_MEM, | ||
| 159 | }, | ||
| 160 | [1] = { | ||
| 161 | .start = 0x203FB800 + 4, | ||
| 162 | .end = 0x203FB800 + 5, | ||
| 163 | .flags = IORESOURCE_MEM, | ||
| 164 | }, | ||
| 165 | [2] = { | ||
| 166 | .start = IRQ_PF9, | ||
| 167 | .end = IRQ_PF9, | ||
| 168 | .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE), | ||
| 169 | }, | ||
| 170 | }; | ||
| 171 | |||
| 172 | static struct platform_device dm9000_device = { | ||
| 173 | .name = "dm9000", | ||
| 174 | .id = -1, | ||
| 175 | .num_resources = ARRAY_SIZE(dm9000_resources), | ||
| 176 | .resource = dm9000_resources, | ||
| 177 | }; | ||
| 178 | #endif | ||
| 179 | |||
| 180 | #if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE) | ||
| 181 | static struct resource sl811_hcd_resources[] = { | ||
| 182 | { | ||
| 183 | .start = 0x20340000, | ||
| 184 | .end = 0x20340000, | ||
| 185 | .flags = IORESOURCE_MEM, | ||
| 186 | }, { | ||
| 187 | .start = 0x20340004, | ||
| 188 | .end = 0x20340004, | ||
| 189 | .flags = IORESOURCE_MEM, | ||
| 190 | }, { | ||
| 191 | .start = CONFIG_USB_SL811_BFIN_IRQ, | ||
| 192 | .end = CONFIG_USB_SL811_BFIN_IRQ, | ||
| 193 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | ||
| 194 | }, | ||
| 195 | }; | ||
| 196 | |||
| 197 | #if defined(CONFIG_USB_SL811_BFIN_USE_VBUS) | ||
| 198 | void sl811_port_power(struct device *dev, int is_on) | ||
| 199 | { | ||
| 200 | gpio_request(CONFIG_USB_SL811_BFIN_GPIO_VBUS, "usb:SL811_VBUS"); | ||
| 201 | gpio_direction_output(CONFIG_USB_SL811_BFIN_GPIO_VBUS, is_on); | ||
| 202 | |||
| 203 | } | ||
| 204 | #endif | ||
| 205 | |||
| 206 | static struct sl811_platform_data sl811_priv = { | ||
| 207 | .potpg = 10, | ||
| 208 | .power = 250, /* == 500mA */ | ||
| 209 | #if defined(CONFIG_USB_SL811_BFIN_USE_VBUS) | ||
| 210 | .port_power = &sl811_port_power, | ||
| 211 | #endif | ||
| 212 | }; | ||
| 213 | |||
| 214 | static struct platform_device sl811_hcd_device = { | ||
| 215 | .name = "sl811-hcd", | ||
| 216 | .id = 0, | ||
| 217 | .dev = { | ||
| 218 | .platform_data = &sl811_priv, | ||
| 219 | }, | ||
| 220 | .num_resources = ARRAY_SIZE(sl811_hcd_resources), | ||
| 221 | .resource = sl811_hcd_resources, | ||
| 222 | }; | ||
| 223 | #endif | ||
| 224 | |||
| 225 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | ||
| 226 | static struct resource isp1362_hcd_resources[] = { | ||
| 227 | { | ||
| 228 | .start = 0x20360000, | ||
| 229 | .end = 0x20360000, | ||
| 230 | .flags = IORESOURCE_MEM, | ||
| 231 | }, { | ||
| 232 | .start = 0x20360004, | ||
| 233 | .end = 0x20360004, | ||
| 234 | .flags = IORESOURCE_MEM, | ||
| 235 | }, { | ||
| 236 | .start = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, | ||
| 237 | .end = CONFIG_USB_ISP1362_BFIN_GPIO_IRQ, | ||
| 238 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | ||
| 239 | }, | ||
| 240 | }; | ||
| 241 | |||
| 242 | static struct isp1362_platform_data isp1362_priv = { | ||
| 243 | .sel15Kres = 1, | ||
| 244 | .clknotstop = 0, | ||
| 245 | .oc_enable = 0, | ||
| 246 | .int_act_high = 0, | ||
| 247 | .int_edge_triggered = 0, | ||
| 248 | .remote_wakeup_connected = 0, | ||
| 249 | .no_power_switching = 1, | ||
| 250 | .power_switching_mode = 0, | ||
| 251 | }; | ||
| 252 | |||
| 253 | static struct platform_device isp1362_hcd_device = { | ||
| 254 | .name = "isp1362-hcd", | ||
| 255 | .id = 0, | ||
| 256 | .dev = { | ||
| 257 | .platform_data = &isp1362_priv, | ||
| 258 | }, | ||
| 259 | .num_resources = ARRAY_SIZE(isp1362_hcd_resources), | ||
| 260 | .resource = isp1362_hcd_resources, | ||
| 261 | }; | ||
| 262 | #endif | ||
| 263 | |||
| 264 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | ||
| 265 | static struct platform_device bfin_mii_bus = { | ||
| 266 | .name = "bfin_mii_bus", | ||
| 267 | }; | ||
| 268 | |||
| 269 | static struct platform_device bfin_mac_device = { | ||
| 270 | .name = "bfin_mac", | ||
| 271 | .dev.platform_data = &bfin_mii_bus, | ||
| 272 | }; | ||
| 273 | #endif | ||
| 274 | |||
| 275 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | ||
| 276 | static struct resource net2272_bfin_resources[] = { | ||
| 277 | { | ||
| 278 | .start = 0x20300000, | ||
| 279 | .end = 0x20300000 + 0x100, | ||
| 280 | .flags = IORESOURCE_MEM, | ||
| 281 | }, { | ||
| 282 | .start = IRQ_PF7, | ||
| 283 | .end = IRQ_PF7, | ||
| 284 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | ||
| 285 | }, | ||
| 286 | }; | ||
| 287 | |||
| 288 | static struct platform_device net2272_bfin_device = { | ||
| 289 | .name = "net2272", | ||
| 290 | .id = -1, | ||
| 291 | .num_resources = ARRAY_SIZE(net2272_bfin_resources), | ||
| 292 | .resource = net2272_bfin_resources, | ||
| 293 | }; | ||
| 294 | #endif | ||
| 295 | |||
| 296 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | ||
| 297 | /* all SPI peripherals info goes here */ | ||
| 298 | |||
| 299 | #if defined(CONFIG_MTD_M25P80) \ | ||
| 300 | || defined(CONFIG_MTD_M25P80_MODULE) | ||
| 301 | static struct mtd_partition bfin_spi_flash_partitions[] = { | ||
| 302 | { | ||
| 303 | .name = "bootloader(spi)", | ||
| 304 | .size = 0x00020000, | ||
| 305 | .offset = 0, | ||
| 306 | .mask_flags = MTD_CAP_ROM | ||
| 307 | }, { | ||
| 308 | .name = "linux kernel(spi)", | ||
| 309 | .size = 0xe0000, | ||
| 310 | .offset = 0x20000 | ||
| 311 | }, { | ||
| 312 | .name = "file system(spi)", | ||
| 313 | .size = 0x700000, | ||
| 314 | .offset = 0x00100000, | ||
| 315 | } | ||
| 316 | }; | ||
| 317 | |||
| 318 | static struct flash_platform_data bfin_spi_flash_data = { | ||
| 319 | .name = "m25p80", | ||
| 320 | .parts = bfin_spi_flash_partitions, | ||
| 321 | .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), | ||
| 322 | .type = "m25p64", | ||
| 323 | }; | ||
| 324 | |||
| 325 | /* SPI flash chip (m25p64) */ | ||
| 326 | static struct bfin5xx_spi_chip spi_flash_chip_info = { | ||
| 327 | .enable_dma = 0, /* use dma transfer with this chip*/ | ||
| 328 | .bits_per_word = 8, | ||
| 329 | }; | ||
| 330 | #endif | ||
| 331 | |||
| 332 | #if defined(CONFIG_SPI_ADC_BF533) \ | ||
| 333 | || defined(CONFIG_SPI_ADC_BF533_MODULE) | ||
| 334 | /* SPI ADC chip */ | ||
| 335 | static struct bfin5xx_spi_chip spi_adc_chip_info = { | ||
| 336 | .enable_dma = 1, /* use dma transfer with this chip*/ | ||
| 337 | .bits_per_word = 16, | ||
| 338 | }; | ||
| 339 | #endif | ||
| 340 | |||
| 341 | #if defined(CONFIG_SND_BLACKFIN_AD1836) \ | ||
| 342 | || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | ||
| 343 | static struct bfin5xx_spi_chip ad1836_spi_chip_info = { | ||
| 344 | .enable_dma = 0, | ||
| 345 | .bits_per_word = 16, | ||
| 346 | }; | ||
| 347 | #endif | ||
| 348 | |||
| 349 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | ||
| 350 | static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | ||
| 351 | .enable_dma = 0, | ||
| 352 | .bits_per_word = 16, | ||
| 353 | }; | ||
| 354 | #endif | ||
| 355 | |||
| 356 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | ||
| 357 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | ||
| 358 | .enable_dma = 1, | ||
| 359 | .bits_per_word = 8, | ||
| 360 | }; | ||
| 361 | #endif | ||
| 362 | |||
| 363 | #if defined(CONFIG_PBX) | ||
| 364 | static struct bfin5xx_spi_chip spi_si3xxx_chip_info = { | ||
| 365 | .ctl_reg = 0x4, /* send zero */ | ||
| 366 | .enable_dma = 0, | ||
| 367 | .bits_per_word = 8, | ||
| 368 | .cs_change_per_word = 1, | ||
| 369 | }; | ||
| 370 | #endif | ||
| 371 | |||
| 372 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | ||
| 373 | static struct bfin5xx_spi_chip spi_ad7877_chip_info = { | ||
| 374 | .enable_dma = 0, | ||
| 375 | .bits_per_word = 16, | ||
| 376 | }; | ||
| 377 | |||
| 378 | static const struct ad7877_platform_data bfin_ad7877_ts_info = { | ||
| 379 | .model = 7877, | ||
| 380 | .vref_delay_usecs = 50, /* internal, no capacitor */ | ||
| 381 | .x_plate_ohms = 419, | ||
| 382 | .y_plate_ohms = 486, | ||
| 383 | .pressure_max = 1000, | ||
| 384 | .pressure_min = 0, | ||
| 385 | .stopacq_polarity = 1, | ||
| 386 | .first_conversion_delay = 3, | ||
| 387 | .acquisition_time = 1, | ||
| 388 | .averaging = 1, | ||
| 389 | .pen_down_acc_interval = 1, | ||
| 390 | }; | ||
| 391 | #endif | ||
| 392 | |||
| 393 | static struct spi_board_info bfin_spi_board_info[] __initdata = { | ||
| 394 | #if defined(CONFIG_MTD_M25P80) \ | ||
| 395 | || defined(CONFIG_MTD_M25P80_MODULE) | ||
| 396 | { | ||
| 397 | /* the modalias must be the same as spi device driver name */ | ||
| 398 | .modalias = "m25p80", /* Name of spi_driver for this device */ | ||
| 399 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
| 400 | .bus_num = 0, /* Framework bus number */ | ||
| 401 | .chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/ | ||
| 402 | .platform_data = &bfin_spi_flash_data, | ||
| 403 | .controller_data = &spi_flash_chip_info, | ||
| 404 | .mode = SPI_MODE_3, | ||
| 405 | }, | ||
| 406 | #endif | ||
| 407 | |||
| 408 | #if defined(CONFIG_SPI_ADC_BF533) \ | ||
| 409 | || defined(CONFIG_SPI_ADC_BF533_MODULE) | ||
| 410 | { | ||
| 411 | .modalias = "bfin_spi_adc", /* Name of spi_driver for this device */ | ||
| 412 | .max_speed_hz = 6250000, /* max spi clock (SCK) speed in HZ */ | ||
| 413 | .bus_num = 0, /* Framework bus number */ | ||
| 414 | .chip_select = 1, /* Framework chip select. */ | ||
| 415 | .platform_data = NULL, /* No spi_driver specific config */ | ||
| 416 | .controller_data = &spi_adc_chip_info, | ||
| 417 | }, | ||
| 418 | #endif | ||
| 419 | |||
| 420 | #if defined(CONFIG_SND_BLACKFIN_AD1836) \ | ||
| 421 | || defined(CONFIG_SND_BLACKFIN_AD1836_MODULE) | ||
| 422 | { | ||
| 423 | .modalias = "ad1836-spi", | ||
| 424 | .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ | ||
| 425 | .bus_num = 0, | ||
| 426 | .chip_select = CONFIG_SND_BLACKFIN_SPI_PFBIT, | ||
| 427 | .controller_data = &ad1836_spi_chip_info, | ||
| 428 | }, | ||
| 429 | #endif | ||
| 430 | #if defined(CONFIG_AD9960) || defined(CONFIG_AD9960_MODULE) | ||
| 431 | { | ||
| 432 | .modalias = "ad9960-spi", | ||
| 433 | .max_speed_hz = 10000000, /* max spi clock (SCK) speed in HZ */ | ||
| 434 | .bus_num = 0, | ||
| 435 | .chip_select = 1, | ||
| 436 | .controller_data = &ad9960_spi_chip_info, | ||
| 437 | }, | ||
| 438 | #endif | ||
| 439 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | ||
| 440 | { | ||
| 441 | .modalias = "spi_mmc_dummy", | ||
| 442 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
| 443 | .bus_num = 0, | ||
| 444 | .chip_select = 0, | ||
| 445 | .platform_data = NULL, | ||
| 446 | .controller_data = &spi_mmc_chip_info, | ||
| 447 | .mode = SPI_MODE_3, | ||
| 448 | }, | ||
| 449 | { | ||
| 450 | .modalias = "spi_mmc", | ||
| 451 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
| 452 | .bus_num = 0, | ||
| 453 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, | ||
| 454 | .platform_data = NULL, | ||
| 455 | .controller_data = &spi_mmc_chip_info, | ||
| 456 | .mode = SPI_MODE_3, | ||
| 457 | }, | ||
| 458 | #endif | ||
| 459 | #if defined(CONFIG_PBX) | ||
| 460 | { | ||
| 461 | .modalias = "fxs-spi", | ||
| 462 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
| 463 | .bus_num = 0, | ||
| 464 | .chip_select = 8 - CONFIG_J11_JUMPER, | ||
| 465 | .controller_data = &spi_si3xxx_chip_info, | ||
| 466 | .mode = SPI_MODE_3, | ||
| 467 | }, | ||
| 468 | { | ||
| 469 | .modalias = "fxo-spi", | ||
| 470 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
| 471 | .bus_num = 0, | ||
| 472 | .chip_select = 8 - CONFIG_J19_JUMPER, | ||
| 473 | .controller_data = &spi_si3xxx_chip_info, | ||
| 474 | .mode = SPI_MODE_3, | ||
| 475 | }, | ||
| 476 | #endif | ||
| 477 | #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE) | ||
| 478 | { | ||
| 479 | .modalias = "ad7877", | ||
| 480 | .platform_data = &bfin_ad7877_ts_info, | ||
| 481 | .irq = IRQ_PF6, | ||
| 482 | .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ | ||
| 483 | .bus_num = 0, | ||
| 484 | .chip_select = 1, | ||
| 485 | .controller_data = &spi_ad7877_chip_info, | ||
| 486 | }, | ||
| 487 | #endif | ||
| 488 | }; | ||
| 489 | |||
| 490 | /* SPI controller data */ | ||
| 491 | static struct bfin5xx_spi_master bfin_spi0_info = { | ||
| 492 | .num_chipselect = 8, | ||
| 493 | .enable_dma = 1, /* master has the ability to do dma transfer */ | ||
| 494 | .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, | ||
| 495 | }; | ||
| 496 | |||
| 497 | /* SPI (0) */ | ||
| 498 | static struct resource bfin_spi0_resource[] = { | ||
| 499 | [0] = { | ||
| 500 | .start = SPI0_REGBASE, | ||
| 501 | .end = SPI0_REGBASE + 0xFF, | ||
| 502 | .flags = IORESOURCE_MEM, | ||
| 503 | }, | ||
| 504 | [1] = { | ||
| 505 | .start = CH_SPI, | ||
| 506 | .end = CH_SPI, | ||
| 507 | .flags = IORESOURCE_IRQ, | ||
| 508 | }, | ||
| 509 | }; | ||
| 510 | |||
| 511 | static struct platform_device bfin_spi0_device = { | ||
| 512 | .name = "bfin-spi", | ||
| 513 | .id = 0, /* Bus number */ | ||
| 514 | .num_resources = ARRAY_SIZE(bfin_spi0_resource), | ||
| 515 | .resource = bfin_spi0_resource, | ||
| 516 | .dev = { | ||
| 517 | .platform_data = &bfin_spi0_info, /* Passed to driver */ | ||
| 518 | }, | ||
| 519 | }; | ||
| 520 | #endif /* spi master and devices */ | ||
| 521 | |||
| 522 | #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) | ||
| 523 | static struct platform_device bfin_fb_device = { | ||
| 524 | .name = "bf537-lq035", | ||
| 525 | }; | ||
| 526 | #endif | ||
| 527 | |||
| 528 | #if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE) | ||
| 529 | static struct platform_device bfin_fb_adv7393_device = { | ||
| 530 | .name = "bfin-adv7393", | ||
| 531 | }; | ||
| 532 | #endif | ||
| 533 | |||
| 534 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | ||
| 535 | static struct resource bfin_uart_resources[] = { | ||
| 536 | { | ||
| 537 | .start = 0xFFC00400, | ||
| 538 | .end = 0xFFC004FF, | ||
| 539 | .flags = IORESOURCE_MEM, | ||
| 540 | }, { | ||
| 541 | .start = 0xFFC02000, | ||
| 542 | .end = 0xFFC020FF, | ||
| 543 | .flags = IORESOURCE_MEM, | ||
| 544 | }, | ||
| 545 | }; | ||
| 546 | |||
| 547 | static struct platform_device bfin_uart_device = { | ||
| 548 | .name = "bfin-uart", | ||
| 549 | .id = 1, | ||
| 550 | .num_resources = ARRAY_SIZE(bfin_uart_resources), | ||
| 551 | .resource = bfin_uart_resources, | ||
| 552 | }; | ||
| 553 | #endif | ||
| 554 | |||
| 555 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
| 556 | #ifdef CONFIG_BFIN_SIR0 | ||
| 557 | static struct resource bfin_sir0_resources[] = { | ||
| 558 | { | ||
| 559 | .start = 0xFFC00400, | ||
| 560 | .end = 0xFFC004FF, | ||
| 561 | .flags = IORESOURCE_MEM, | ||
| 562 | }, | ||
| 563 | { | ||
| 564 | .start = IRQ_UART0_RX, | ||
| 565 | .end = IRQ_UART0_RX+1, | ||
| 566 | .flags = IORESOURCE_IRQ, | ||
| 567 | }, | ||
| 568 | { | ||
| 569 | .start = CH_UART0_RX, | ||
| 570 | .end = CH_UART0_RX+1, | ||
| 571 | .flags = IORESOURCE_DMA, | ||
| 572 | }, | ||
| 573 | }; | ||
| 574 | |||
| 575 | static struct platform_device bfin_sir0_device = { | ||
| 576 | .name = "bfin_sir", | ||
| 577 | .id = 0, | ||
| 578 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 579 | .resource = bfin_sir0_resources, | ||
| 580 | }; | ||
| 581 | #endif | ||
| 582 | #ifdef CONFIG_BFIN_SIR1 | ||
| 583 | static struct resource bfin_sir1_resources[] = { | ||
| 584 | { | ||
| 585 | .start = 0xFFC02000, | ||
| 586 | .end = 0xFFC020FF, | ||
| 587 | .flags = IORESOURCE_MEM, | ||
| 588 | }, | ||
| 589 | { | ||
| 590 | .start = IRQ_UART1_RX, | ||
| 591 | .end = IRQ_UART1_RX+1, | ||
| 592 | .flags = IORESOURCE_IRQ, | ||
| 593 | }, | ||
| 594 | { | ||
| 595 | .start = CH_UART1_RX, | ||
| 596 | .end = CH_UART1_RX+1, | ||
| 597 | .flags = IORESOURCE_DMA, | ||
| 598 | }, | ||
| 599 | }; | ||
| 600 | |||
| 601 | static struct platform_device bfin_sir1_device = { | ||
| 602 | .name = "bfin_sir", | ||
| 603 | .id = 1, | ||
| 604 | .num_resources = ARRAY_SIZE(bfin_sir1_resources), | ||
| 605 | .resource = bfin_sir1_resources, | ||
| 606 | }; | ||
| 607 | #endif | ||
| 608 | #endif | ||
| 609 | |||
| 610 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | ||
| 611 | static struct resource bfin_twi0_resource[] = { | ||
| 612 | [0] = { | ||
| 613 | .start = TWI0_REGBASE, | ||
| 614 | .end = TWI0_REGBASE + 0xFF, | ||
| 615 | .flags = IORESOURCE_MEM, | ||
| 616 | }, | ||
| 617 | [1] = { | ||
| 618 | .start = IRQ_TWI, | ||
| 619 | .end = IRQ_TWI, | ||
| 620 | .flags = IORESOURCE_IRQ, | ||
| 621 | }, | ||
| 622 | }; | ||
| 623 | |||
| 624 | static struct platform_device i2c_bfin_twi_device = { | ||
| 625 | .name = "i2c-bfin-twi", | ||
| 626 | .id = 0, | ||
| 627 | .num_resources = ARRAY_SIZE(bfin_twi0_resource), | ||
| 628 | .resource = bfin_twi0_resource, | ||
| 629 | }; | ||
| 630 | #endif | ||
| 631 | |||
| 632 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | ||
| 633 | static struct platform_device bfin_sport0_uart_device = { | ||
| 634 | .name = "bfin-sport-uart", | ||
| 635 | .id = 0, | ||
| 636 | }; | ||
| 637 | |||
| 638 | static struct platform_device bfin_sport1_uart_device = { | ||
| 639 | .name = "bfin-sport-uart", | ||
| 640 | .id = 1, | ||
| 641 | }; | ||
| 642 | #endif | ||
| 643 | |||
| 644 | static struct platform_device *stamp_devices[] __initdata = { | ||
| 645 | #if defined(CONFIG_BFIN_CFPCMCIA) || defined(CONFIG_BFIN_CFPCMCIA_MODULE) | ||
| 646 | &bfin_pcmcia_cf_device, | ||
| 647 | #endif | ||
| 648 | |||
| 649 | #if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) | ||
| 650 | &rtc_device, | ||
| 651 | #endif | ||
| 652 | |||
| 653 | #if defined(CONFIG_USB_SL811_HCD) || defined(CONFIG_USB_SL811_HCD_MODULE) | ||
| 654 | &sl811_hcd_device, | ||
| 655 | #endif | ||
| 656 | |||
| 657 | #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE) | ||
| 658 | &isp1362_hcd_device, | ||
| 659 | #endif | ||
| 660 | |||
| 661 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | ||
| 662 | &smc91x_device, | ||
| 663 | #endif | ||
| 664 | |||
| 665 | #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE) | ||
| 666 | &dm9000_device, | ||
| 667 | #endif | ||
| 668 | |||
| 669 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | ||
| 670 | &bfin_mii_bus, | ||
| 671 | &bfin_mac_device, | ||
| 672 | #endif | ||
| 673 | |||
| 674 | #if defined(CONFIG_USB_NET2272) || defined(CONFIG_USB_NET2272_MODULE) | ||
| 675 | &net2272_bfin_device, | ||
| 676 | #endif | ||
| 677 | |||
| 678 | #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE) | ||
| 679 | &bfin_isp1760_device, | ||
| 680 | #endif | ||
| 681 | |||
| 682 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | ||
| 683 | &bfin_spi0_device, | ||
| 684 | #endif | ||
| 685 | |||
| 686 | #if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) | ||
| 687 | &bfin_fb_device, | ||
| 688 | #endif | ||
| 689 | |||
| 690 | #if defined(CONFIG_FB_BFIN_7393) || defined(CONFIG_FB_BFIN_7393_MODULE) | ||
| 691 | &bfin_fb_adv7393_device, | ||
| 692 | #endif | ||
| 693 | |||
| 694 | #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE) | ||
| 695 | &bfin_uart_device, | ||
| 696 | #endif | ||
| 697 | |||
| 698 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
| 699 | #ifdef CONFIG_BFIN_SIR0 | ||
| 700 | &bfin_sir0_device, | ||
| 701 | #endif | ||
| 702 | #ifdef CONFIG_BFIN_SIR1 | ||
| 703 | &bfin_sir1_device, | ||
| 704 | #endif | ||
| 705 | #endif | ||
| 706 | |||
| 707 | #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE) | ||
| 708 | &i2c_bfin_twi_device, | ||
| 709 | #endif | ||
| 710 | |||
| 711 | #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) | ||
| 712 | &bfin_sport0_uart_device, | ||
| 713 | &bfin_sport1_uart_device, | ||
| 714 | #endif | ||
| 715 | }; | ||
| 716 | |||
| 717 | static int __init generic_init(void) | ||
| 718 | { | ||
| 719 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | ||
| 720 | platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices)); | ||
| 721 | #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE) | ||
| 722 | spi_register_board_info(bfin_spi_board_info, | ||
| 723 | ARRAY_SIZE(bfin_spi_board_info)); | ||
| 724 | #endif | ||
| 725 | |||
| 726 | return 0; | ||
| 727 | } | ||
| 728 | |||
| 729 | arch_initcall(generic_init); | ||
| 730 | |||
| 731 | void native_machine_restart(char *cmd) | ||
| 732 | { | ||
| 733 | /* workaround reboot hang when booting from SPI */ | ||
| 734 | if ((bfin_read_SYSCR() & 0x7) == 0x3) | ||
| 735 | bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS); | ||
| 736 | } | ||
| 737 | |||
| 738 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) | ||
| 739 | void bfin_get_ether_addr(char *addr) | ||
| 740 | { | ||
| 741 | random_ether_addr(addr); | ||
| 742 | printk(KERN_WARNING "%s:%s: Setting Ethernet MAC to a random one\n", __FILE__, __func__); | ||
| 743 | } | ||
| 744 | EXPORT_SYMBOL(bfin_get_ether_addr); | ||
| 745 | #endif | ||
diff --git a/arch/blackfin/mach-bf537/boards/minotaur.c b/arch/blackfin/mach-bf537/boards/minotaur.c index db7d3a385e4b..3c159819e555 100644 --- a/arch/blackfin/mach-bf537/boards/minotaur.c +++ b/arch/blackfin/mach-bf537/boards/minotaur.c | |||
| @@ -134,9 +134,9 @@ static struct bfin5xx_spi_chip spi_flash_chip_info = { | |||
| 134 | }; | 134 | }; |
| 135 | #endif | 135 | #endif |
| 136 | 136 | ||
| 137 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 137 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 138 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | 138 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
| 139 | .enable_dma = 1, | 139 | .enable_dma = 0, |
| 140 | .bits_per_word = 8, | 140 | .bits_per_word = 8, |
| 141 | }; | 141 | }; |
| 142 | #endif | 142 | #endif |
| @@ -156,23 +156,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 156 | }, | 156 | }, |
| 157 | #endif | 157 | #endif |
| 158 | 158 | ||
| 159 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 159 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 160 | { | 160 | { |
| 161 | .modalias = "spi_mmc_dummy", | 161 | .modalias = "mmc_spi", |
| 162 | .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ | 162 | .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ |
| 163 | .bus_num = 0, | 163 | .bus_num = 0, |
| 164 | .chip_select = 0, | 164 | .chip_select = 5, |
| 165 | .platform_data = NULL, | 165 | .controller_data = &mmc_spi_chip_info, |
| 166 | .controller_data = &spi_mmc_chip_info, | ||
| 167 | .mode = SPI_MODE_3, | ||
| 168 | }, | ||
| 169 | { | ||
| 170 | .modalias = "spi_mmc", | ||
| 171 | .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ | ||
| 172 | .bus_num = 0, | ||
| 173 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, | ||
| 174 | .platform_data = NULL, | ||
| 175 | .controller_data = &spi_mmc_chip_info, | ||
| 176 | .mode = SPI_MODE_3, | 166 | .mode = SPI_MODE_3, |
| 177 | }, | 167 | }, |
| 178 | #endif | 168 | #endif |
diff --git a/arch/blackfin/mach-bf537/boards/pnav10.c b/arch/blackfin/mach-bf537/boards/pnav10.c index 590eb3a139b7..4e1de1e53f89 100644 --- a/arch/blackfin/mach-bf537/boards/pnav10.c +++ b/arch/blackfin/mach-bf537/boards/pnav10.c | |||
| @@ -289,9 +289,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | |||
| 289 | }; | 289 | }; |
| 290 | #endif | 290 | #endif |
| 291 | 291 | ||
| 292 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 292 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 293 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | 293 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
| 294 | .enable_dma = 1, | 294 | .enable_dma = 0, |
| 295 | .bits_per_word = 8, | 295 | .bits_per_word = 8, |
| 296 | }; | 296 | }; |
| 297 | #endif | 297 | #endif |
| @@ -364,23 +364,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 364 | .controller_data = &ad9960_spi_chip_info, | 364 | .controller_data = &ad9960_spi_chip_info, |
| 365 | }, | 365 | }, |
| 366 | #endif | 366 | #endif |
| 367 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 367 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 368 | { | ||
| 369 | .modalias = "spi_mmc_dummy", | ||
| 370 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
| 371 | .bus_num = 0, | ||
| 372 | .chip_select = 7, | ||
| 373 | .platform_data = NULL, | ||
| 374 | .controller_data = &spi_mmc_chip_info, | ||
| 375 | .mode = SPI_MODE_3, | ||
| 376 | }, | ||
| 377 | { | 368 | { |
| 378 | .modalias = "spi_mmc", | 369 | .modalias = "mmc_spi", |
| 379 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | 370 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ |
| 380 | .bus_num = 0, | 371 | .bus_num = 0, |
| 381 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, | 372 | .chip_select = 5, |
| 382 | .platform_data = NULL, | 373 | .controller_data = &mmc_spi_chip_info, |
| 383 | .controller_data = &spi_mmc_chip_info, | ||
| 384 | .mode = SPI_MODE_3, | 374 | .mode = SPI_MODE_3, |
| 385 | }, | 375 | }, |
| 386 | #endif | 376 | #endif |
diff --git a/arch/blackfin/mach-bf537/boards/tcm_bf537.c b/arch/blackfin/mach-bf537/boards/tcm_bf537.c index 3f4f203a06ec..53ad10f3cd76 100644 --- a/arch/blackfin/mach-bf537/boards/tcm_bf537.c +++ b/arch/blackfin/mach-bf537/boards/tcm_bf537.c | |||
| @@ -108,9 +108,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | |||
| 108 | }; | 108 | }; |
| 109 | #endif | 109 | #endif |
| 110 | 110 | ||
| 111 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 111 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 112 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | 112 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
| 113 | .enable_dma = 1, | 113 | .enable_dma = 0, |
| 114 | .bits_per_word = 8, | 114 | .bits_per_word = 8, |
| 115 | }; | 115 | }; |
| 116 | #endif | 116 | #endif |
| @@ -160,23 +160,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 160 | }, | 160 | }, |
| 161 | #endif | 161 | #endif |
| 162 | 162 | ||
| 163 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 163 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 164 | { | ||
| 165 | .modalias = "spi_mmc_dummy", | ||
| 166 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | ||
| 167 | .bus_num = 0, | ||
| 168 | .chip_select = 7, | ||
| 169 | .platform_data = NULL, | ||
| 170 | .controller_data = &spi_mmc_chip_info, | ||
| 171 | .mode = SPI_MODE_3, | ||
| 172 | }, | ||
| 173 | { | 164 | { |
| 174 | .modalias = "spi_mmc", | 165 | .modalias = "mmc_spi", |
| 175 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | 166 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ |
| 176 | .bus_num = 0, | 167 | .bus_num = 0, |
| 177 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, | 168 | .chip_select = 5, |
| 178 | .platform_data = NULL, | 169 | .controller_data = &mmc_spi_chip_info, |
| 179 | .controller_data = &spi_mmc_chip_info, | ||
| 180 | .mode = SPI_MODE_3, | 170 | .mode = SPI_MODE_3, |
| 181 | }, | 171 | }, |
| 182 | #endif | 172 | #endif |
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h index 9cb39121d1cb..1bfd80c26c90 100644 --- a/arch/blackfin/mach-bf537/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * File: include/asm-blackfin/mach-bf537/anomaly.h | 2 | * File: include/asm-blackfin/mach-bf537/anomaly.h |
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 4 | * | 4 | * |
| 5 | * Copyright (C) 2004-2008 Analog Devices Inc. | 5 | * Copyright (C) 2004-2009 Analog Devices Inc. |
| 6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| @@ -110,7 +110,7 @@ | |||
| 110 | #define ANOMALY_05000301 (1) | 110 | #define ANOMALY_05000301 (1) |
| 111 | /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ | 111 | /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */ |
| 112 | #define ANOMALY_05000304 (__SILICON_REVISION__ < 3) | 112 | #define ANOMALY_05000304 (__SILICON_REVISION__ < 3) |
| 113 | /* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ | 113 | /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ |
| 114 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 3) | 114 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 3) |
| 115 | /* SCKELOW Bit Does Not Maintain State Through Hibernate */ | 115 | /* SCKELOW Bit Does Not Maintain State Through Hibernate */ |
| 116 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 3) | 116 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 3) |
| @@ -168,9 +168,12 @@ | |||
| 168 | #define ANOMALY_05000323 (0) | 168 | #define ANOMALY_05000323 (0) |
| 169 | #define ANOMALY_05000353 (1) | 169 | #define ANOMALY_05000353 (1) |
| 170 | #define ANOMALY_05000363 (0) | 170 | #define ANOMALY_05000363 (0) |
| 171 | #define ANOMALY_05000380 (0) | ||
| 171 | #define ANOMALY_05000386 (1) | 172 | #define ANOMALY_05000386 (1) |
| 172 | #define ANOMALY_05000412 (0) | 173 | #define ANOMALY_05000412 (0) |
| 173 | #define ANOMALY_05000432 (0) | 174 | #define ANOMALY_05000432 (0) |
| 174 | #define ANOMALY_05000435 (0) | 175 | #define ANOMALY_05000435 (0) |
| 176 | #define ANOMALY_05000447 (0) | ||
| 177 | #define ANOMALY_05000448 (0) | ||
| 175 | 178 | ||
| 176 | #endif | 179 | #endif |
diff --git a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h index b3f87e1d16a2..9e34700844a2 100644 --- a/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf537/include/mach/bfin_serial_5xx.h | |||
| @@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = { | |||
| 144 | CH_UART0_TX, | 144 | CH_UART0_TX, |
| 145 | CH_UART0_RX, | 145 | CH_UART0_RX, |
| 146 | #endif | 146 | #endif |
| 147 | #ifdef CONFIG_BFIN_UART0_CTSRTS | 147 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 148 | CONFIG_UART0_CTS_PIN, | 148 | CONFIG_UART0_CTS_PIN, |
| 149 | CONFIG_UART0_RTS_PIN, | 149 | CONFIG_UART0_RTS_PIN, |
| 150 | #endif | 150 | #endif |
| @@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = { | |||
| 158 | CH_UART1_TX, | 158 | CH_UART1_TX, |
| 159 | CH_UART1_RX, | 159 | CH_UART1_RX, |
| 160 | #endif | 160 | #endif |
| 161 | #ifdef CONFIG_BFIN_UART1_CTSRTS | 161 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 162 | CONFIG_UART1_CTS_PIN, | 162 | CONFIG_UART1_CTS_PIN, |
| 163 | CONFIG_UART1_RTS_PIN, | 163 | CONFIG_UART1_RTS_PIN, |
| 164 | #endif | 164 | #endif |
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h index e130b4f8a05d..3a5699827363 100644 --- a/arch/blackfin/mach-bf538/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * File: include/asm-blackfin/mach-bf538/anomaly.h | 2 | * File: include/asm-blackfin/mach-bf538/anomaly.h |
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 4 | * | 4 | * |
| 5 | * Copyright (C) 2004-2008 Analog Devices Inc. | 5 | * Copyright (C) 2004-2009 Analog Devices Inc. |
| 6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| @@ -120,13 +120,17 @@ | |||
| 120 | #define ANOMALY_05000198 (0) | 120 | #define ANOMALY_05000198 (0) |
| 121 | #define ANOMALY_05000230 (0) | 121 | #define ANOMALY_05000230 (0) |
| 122 | #define ANOMALY_05000263 (0) | 122 | #define ANOMALY_05000263 (0) |
| 123 | #define ANOMALY_05000305 (0) | ||
| 123 | #define ANOMALY_05000311 (0) | 124 | #define ANOMALY_05000311 (0) |
| 124 | #define ANOMALY_05000323 (0) | 125 | #define ANOMALY_05000323 (0) |
| 125 | #define ANOMALY_05000353 (1) | 126 | #define ANOMALY_05000353 (1) |
| 126 | #define ANOMALY_05000363 (0) | 127 | #define ANOMALY_05000363 (0) |
| 128 | #define ANOMALY_05000380 (0) | ||
| 127 | #define ANOMALY_05000386 (1) | 129 | #define ANOMALY_05000386 (1) |
| 128 | #define ANOMALY_05000412 (0) | 130 | #define ANOMALY_05000412 (0) |
| 129 | #define ANOMALY_05000432 (0) | 131 | #define ANOMALY_05000432 (0) |
| 130 | #define ANOMALY_05000435 (0) | 132 | #define ANOMALY_05000435 (0) |
| 133 | #define ANOMALY_05000447 (0) | ||
| 134 | #define ANOMALY_05000448 (0) | ||
| 131 | 135 | ||
| 132 | #endif | 136 | #endif |
diff --git a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h index 40503b6b89a3..3c2811ebecdd 100644 --- a/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf538/include/mach/bfin_serial_5xx.h | |||
| @@ -144,7 +144,7 @@ struct bfin_serial_res bfin_serial_resource[] = { | |||
| 144 | CH_UART0_TX, | 144 | CH_UART0_TX, |
| 145 | CH_UART0_RX, | 145 | CH_UART0_RX, |
| 146 | #endif | 146 | #endif |
| 147 | #ifdef CONFIG_BFIN_UART0_CTSRTS | 147 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 148 | CONFIG_UART0_CTS_PIN, | 148 | CONFIG_UART0_CTS_PIN, |
| 149 | CONFIG_UART0_RTS_PIN, | 149 | CONFIG_UART0_RTS_PIN, |
| 150 | #endif | 150 | #endif |
| @@ -158,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = { | |||
| 158 | CH_UART1_TX, | 158 | CH_UART1_TX, |
| 159 | CH_UART1_RX, | 159 | CH_UART1_RX, |
| 160 | #endif | 160 | #endif |
| 161 | #ifdef CONFIG_BFIN_UART1_CTSRTS | 161 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 162 | CONFIG_UART1_CTS_PIN, | 162 | CONFIG_UART1_CTS_PIN, |
| 163 | CONFIG_UART1_RTS_PIN, | 163 | CONFIG_UART1_RTS_PIN, |
| 164 | #endif | 164 | #endif |
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h index 23d03c52f4b4..882e40ccf0d1 100644 --- a/arch/blackfin/mach-bf548/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h | |||
| @@ -2,12 +2,12 @@ | |||
| 2 | * File: include/asm-blackfin/mach-bf548/anomaly.h | 2 | * File: include/asm-blackfin/mach-bf548/anomaly.h |
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 4 | * | 4 | * |
| 5 | * Copyright (C) 2004-2008 Analog Devices Inc. | 5 | * Copyright (C) 2004-2009 Analog Devices Inc. |
| 6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| 9 | /* This file shoule be up to date with: | 9 | /* This file shoule be up to date with: |
| 10 | * - Revision G, 08/07/2008; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List | 10 | * - Revision H, 01/16/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List |
| 11 | */ | 11 | */ |
| 12 | 12 | ||
| 13 | #ifndef _MACH_ANOMALY_H_ | 13 | #ifndef _MACH_ANOMALY_H_ |
| @@ -91,8 +91,6 @@ | |||
| 91 | #define ANOMALY_05000371 (__SILICON_REVISION__ < 2) | 91 | #define ANOMALY_05000371 (__SILICON_REVISION__ < 2) |
| 92 | /* USB DP/DM Data Pins May Lose State When Entering Hibernate */ | 92 | /* USB DP/DM Data Pins May Lose State When Entering Hibernate */ |
| 93 | #define ANOMALY_05000372 (__SILICON_REVISION__ < 1) | 93 | #define ANOMALY_05000372 (__SILICON_REVISION__ < 1) |
| 94 | /* Mobile DDR Operation Not Functional */ | ||
| 95 | #define ANOMALY_05000377 (1) | ||
| 96 | /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ | 94 | /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ |
| 97 | #define ANOMALY_05000378 (__SILICON_REVISION__ < 2) | 95 | #define ANOMALY_05000378 (__SILICON_REVISION__ < 2) |
| 98 | /* 16-Bit NAND FLASH Boot Mode Is Not Functional */ | 96 | /* 16-Bit NAND FLASH Boot Mode Is Not Functional */ |
| @@ -157,8 +155,22 @@ | |||
| 157 | #define ANOMALY_05000429 (__SILICON_REVISION__ < 2) | 155 | #define ANOMALY_05000429 (__SILICON_REVISION__ < 2) |
| 158 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ | 156 | /* Software System Reset Corrupts PLL_LOCKCNT Register */ |
| 159 | #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) | 157 | #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2) |
| 158 | /* Incorrect Use of Stack in Lockbox Firmware During Authentication */ | ||
| 159 | #define ANOMALY_05000431 (__SILICON_REVISION__ < 3) | ||
| 160 | /* OTP Write Accesses Not Supported */ | ||
| 161 | #define ANOMALY_05000442 (__SILICON_REVISION__ < 1) | ||
| 160 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ | 162 | /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */ |
| 161 | #define ANOMALY_05000443 (1) | 163 | #define ANOMALY_05000443 (1) |
| 164 | /* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */ | ||
| 165 | #define ANOMALY_05000446 (1) | ||
| 166 | /* UART IrDA Receiver Fails on Extended Bit Pulses */ | ||
| 167 | #define ANOMALY_05000447 (1) | ||
| 168 | /* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */ | ||
| 169 | #define ANOMALY_05000448 (__SILICON_REVISION__ == 1) | ||
| 170 | /* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */ | ||
| 171 | #define ANOMALY_05000449 (__SILICON_REVISION__ == 1) | ||
| 172 | /* USB DMA Mode 1 Short Packet Data Corruption */ | ||
| 173 | #define ANOMALY_05000450 (1 | ||
| 162 | 174 | ||
| 163 | /* Anomalies that don't exist on this proc */ | 175 | /* Anomalies that don't exist on this proc */ |
| 164 | #define ANOMALY_05000125 (0) | 176 | #define ANOMALY_05000125 (0) |
| @@ -171,6 +183,8 @@ | |||
| 171 | #define ANOMALY_05000263 (0) | 183 | #define ANOMALY_05000263 (0) |
| 172 | #define ANOMALY_05000266 (0) | 184 | #define ANOMALY_05000266 (0) |
| 173 | #define ANOMALY_05000273 (0) | 185 | #define ANOMALY_05000273 (0) |
| 186 | #define ANOMALY_05000278 (0) | ||
| 187 | #define ANOMALY_05000305 (0) | ||
| 174 | #define ANOMALY_05000307 (0) | 188 | #define ANOMALY_05000307 (0) |
| 175 | #define ANOMALY_05000311 (0) | 189 | #define ANOMALY_05000311 (0) |
| 176 | #define ANOMALY_05000323 (0) | 190 | #define ANOMALY_05000323 (0) |
diff --git a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h index e4cf35e7ab9f..c05e79cba257 100644 --- a/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf548/include/mach/bfin_serial_5xx.h | |||
| @@ -63,7 +63,7 @@ | |||
| 63 | #define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) | 63 | #define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v) |
| 64 | #define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) | 64 | #define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF) |
| 65 | 65 | ||
| 66 | #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) | 66 | #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART2_CTSRTS) |
| 67 | # define CONFIG_SERIAL_BFIN_CTSRTS | 67 | # define CONFIG_SERIAL_BFIN_CTSRTS |
| 68 | 68 | ||
| 69 | # ifndef CONFIG_UART0_CTS_PIN | 69 | # ifndef CONFIG_UART0_CTS_PIN |
| @@ -74,12 +74,12 @@ | |||
| 74 | # define CONFIG_UART0_RTS_PIN -1 | 74 | # define CONFIG_UART0_RTS_PIN -1 |
| 75 | # endif | 75 | # endif |
| 76 | 76 | ||
| 77 | # ifndef CONFIG_UART1_CTS_PIN | 77 | # ifndef CONFIG_UART2_CTS_PIN |
| 78 | # define CONFIG_UART1_CTS_PIN -1 | 78 | # define CONFIG_UART2_CTS_PIN -1 |
| 79 | # endif | 79 | # endif |
| 80 | 80 | ||
| 81 | # ifndef CONFIG_UART1_RTS_PIN | 81 | # ifndef CONFIG_UART2_RTS_PIN |
| 82 | # define CONFIG_UART1_RTS_PIN -1 | 82 | # define CONFIG_UART2_RTS_PIN -1 |
| 83 | # endif | 83 | # endif |
| 84 | #endif | 84 | #endif |
| 85 | 85 | ||
| @@ -130,7 +130,7 @@ struct bfin_serial_res bfin_serial_resource[] = { | |||
| 130 | CH_UART0_TX, | 130 | CH_UART0_TX, |
| 131 | CH_UART0_RX, | 131 | CH_UART0_RX, |
| 132 | #endif | 132 | #endif |
| 133 | #ifdef CONFIG_BFIN_UART0_CTSRTS | 133 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 134 | CONFIG_UART0_CTS_PIN, | 134 | CONFIG_UART0_CTS_PIN, |
| 135 | CONFIG_UART0_RTS_PIN, | 135 | CONFIG_UART0_RTS_PIN, |
| 136 | #endif | 136 | #endif |
| @@ -144,6 +144,10 @@ struct bfin_serial_res bfin_serial_resource[] = { | |||
| 144 | CH_UART1_TX, | 144 | CH_UART1_TX, |
| 145 | CH_UART1_RX, | 145 | CH_UART1_RX, |
| 146 | #endif | 146 | #endif |
| 147 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | ||
| 148 | 0, | ||
| 149 | 0, | ||
| 150 | #endif | ||
| 147 | }, | 151 | }, |
| 148 | #endif | 152 | #endif |
| 149 | #ifdef CONFIG_SERIAL_BFIN_UART2 | 153 | #ifdef CONFIG_SERIAL_BFIN_UART2 |
| @@ -154,7 +158,7 @@ struct bfin_serial_res bfin_serial_resource[] = { | |||
| 154 | CH_UART2_TX, | 158 | CH_UART2_TX, |
| 155 | CH_UART2_RX, | 159 | CH_UART2_RX, |
| 156 | #endif | 160 | #endif |
| 157 | #ifdef CONFIG_BFIN_UART2_CTSRTS | 161 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 158 | CONFIG_UART2_CTS_PIN, | 162 | CONFIG_UART2_CTS_PIN, |
| 159 | CONFIG_UART2_RTS_PIN, | 163 | CONFIG_UART2_RTS_PIN, |
| 160 | #endif | 164 | #endif |
| @@ -168,6 +172,10 @@ struct bfin_serial_res bfin_serial_resource[] = { | |||
| 168 | CH_UART3_TX, | 172 | CH_UART3_TX, |
| 169 | CH_UART3_RX, | 173 | CH_UART3_RX, |
| 170 | #endif | 174 | #endif |
| 175 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | ||
| 176 | 0, | ||
| 177 | 0, | ||
| 178 | #endif | ||
| 171 | }, | 179 | }, |
| 172 | #endif | 180 | #endif |
| 173 | }; | 181 | }; |
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h index 60299a71e090..f194625f6821 100644 --- a/arch/blackfin/mach-bf548/include/mach/irq.h +++ b/arch/blackfin/mach-bf548/include/mach/irq.h | |||
| @@ -123,8 +123,8 @@ Events (highest priority) EMU 0 | |||
| 123 | #define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ | 123 | #define IRQ_MXVR_ERROR BFIN_IRQ(51) /* MXVR Status (Error) Interrupt */ |
| 124 | #define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ | 124 | #define IRQ_MXVR_MSG BFIN_IRQ(52) /* MXVR Message Interrupt */ |
| 125 | #define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ | 125 | #define IRQ_MXVR_PKT BFIN_IRQ(53) /* MXVR Packet Interrupt */ |
| 126 | #define IRQ_EPP1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ | 126 | #define IRQ_EPPI1_ERROR BFIN_IRQ(54) /* EPPI1 Error Interrupt */ |
| 127 | #define IRQ_EPP2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ | 127 | #define IRQ_EPPI2_ERROR BFIN_IRQ(55) /* EPPI2 Error Interrupt */ |
| 128 | #define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ | 128 | #define IRQ_UART3_ERROR BFIN_IRQ(56) /* UART3 Status (Error) Interrupt */ |
| 129 | #define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ | 129 | #define IRQ_HOST_ERROR BFIN_IRQ(57) /* HOST Status (Error) Interrupt */ |
| 130 | #define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ | 130 | #define IRQ_PIXC_ERROR BFIN_IRQ(59) /* PIXC Status (Error) Interrupt */ |
| @@ -361,8 +361,8 @@ Events (highest priority) EMU 0 | |||
| 361 | #define IRQ_UART2_ERR IRQ_UART2_ERROR | 361 | #define IRQ_UART2_ERR IRQ_UART2_ERROR |
| 362 | #define IRQ_CAN0_ERR IRQ_CAN0_ERROR | 362 | #define IRQ_CAN0_ERR IRQ_CAN0_ERROR |
| 363 | #define IRQ_MXVR_ERR IRQ_MXVR_ERROR | 363 | #define IRQ_MXVR_ERR IRQ_MXVR_ERROR |
| 364 | #define IRQ_EPP1_ERR IRQ_EPP1_ERROR | 364 | #define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR |
| 365 | #define IRQ_EPP2_ERR IRQ_EPP2_ERROR | 365 | #define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR |
| 366 | #define IRQ_UART3_ERR IRQ_UART3_ERROR | 366 | #define IRQ_UART3_ERR IRQ_UART3_ERROR |
| 367 | #define IRQ_HOST_ERR IRQ_HOST_ERROR | 367 | #define IRQ_HOST_ERR IRQ_HOST_ERROR |
| 368 | #define IRQ_PIXC_ERR IRQ_PIXC_ERROR | 368 | #define IRQ_PIXC_ERR IRQ_PIXC_ERROR |
diff --git a/arch/blackfin/mach-bf561/boards/Kconfig b/arch/blackfin/mach-bf561/boards/Kconfig index e41a67b1fb53..e4bc6d7c5a6a 100644 --- a/arch/blackfin/mach-bf561/boards/Kconfig +++ b/arch/blackfin/mach-bf561/boards/Kconfig | |||
| @@ -19,9 +19,4 @@ config BFIN561_BLUETECHNIX_CM | |||
| 19 | help | 19 | help |
| 20 | CM-BF561 support for EVAL- and DEV-Board. | 20 | CM-BF561 support for EVAL- and DEV-Board. |
| 21 | 21 | ||
| 22 | config GENERIC_BF561_BOARD | ||
| 23 | bool "Generic" | ||
| 24 | help | ||
| 25 | Generic or Custom board support. | ||
| 26 | |||
| 27 | endchoice | 22 | endchoice |
diff --git a/arch/blackfin/mach-bf561/boards/Makefile b/arch/blackfin/mach-bf561/boards/Makefile index 04add010b568..3a152559e957 100644 --- a/arch/blackfin/mach-bf561/boards/Makefile +++ b/arch/blackfin/mach-bf561/boards/Makefile | |||
| @@ -2,7 +2,6 @@ | |||
| 2 | # arch/blackfin/mach-bf561/boards/Makefile | 2 | # arch/blackfin/mach-bf561/boards/Makefile |
| 3 | # | 3 | # |
| 4 | 4 | ||
| 5 | obj-$(CONFIG_GENERIC_BF561_BOARD) += generic_board.o | ||
| 6 | obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o | 5 | obj-$(CONFIG_BFIN561_BLUETECHNIX_CM) += cm_bf561.o |
| 7 | obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o | 6 | obj-$(CONFIG_BFIN561_EZKIT) += ezkit.o |
| 8 | obj-$(CONFIG_BFIN561_TEPLA) += tepla.o | 7 | obj-$(CONFIG_BFIN561_TEPLA) += tepla.o |
diff --git a/arch/blackfin/mach-bf561/boards/cm_bf561.c b/arch/blackfin/mach-bf561/boards/cm_bf561.c index 6880d1ebfe60..f623c6b0719f 100644 --- a/arch/blackfin/mach-bf561/boards/cm_bf561.c +++ b/arch/blackfin/mach-bf561/boards/cm_bf561.c | |||
| @@ -105,9 +105,9 @@ static struct bfin5xx_spi_chip ad9960_spi_chip_info = { | |||
| 105 | }; | 105 | }; |
| 106 | #endif | 106 | #endif |
| 107 | 107 | ||
| 108 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 108 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 109 | static struct bfin5xx_spi_chip spi_mmc_chip_info = { | 109 | static struct bfin5xx_spi_chip mmc_spi_chip_info = { |
| 110 | .enable_dma = 1, | 110 | .enable_dma = 0, |
| 111 | .bits_per_word = 8, | 111 | .bits_per_word = 8, |
| 112 | }; | 112 | }; |
| 113 | #endif | 113 | #endif |
| @@ -155,14 +155,13 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = { | |||
| 155 | .controller_data = &ad9960_spi_chip_info, | 155 | .controller_data = &ad9960_spi_chip_info, |
| 156 | }, | 156 | }, |
| 157 | #endif | 157 | #endif |
| 158 | #if defined(CONFIG_SPI_MMC) || defined(CONFIG_SPI_MMC_MODULE) | 158 | #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE) |
| 159 | { | 159 | { |
| 160 | .modalias = "spi_mmc", | 160 | .modalias = "mmc_spi", |
| 161 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ | 161 | .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ |
| 162 | .bus_num = 0, | 162 | .bus_num = 0, |
| 163 | .chip_select = CONFIG_SPI_MMC_CS_CHAN, | 163 | .chip_select = 5, |
| 164 | .platform_data = NULL, | 164 | .controller_data = &mmc_spi_chip_info, |
| 165 | .controller_data = &spi_mmc_chip_info, | ||
| 166 | .mode = SPI_MODE_3, | 165 | .mode = SPI_MODE_3, |
| 167 | }, | 166 | }, |
| 168 | #endif | 167 | #endif |
diff --git a/arch/blackfin/mach-bf561/boards/generic_board.c b/arch/blackfin/mach-bf561/boards/generic_board.c deleted file mode 100644 index 0ba366a0e696..000000000000 --- a/arch/blackfin/mach-bf561/boards/generic_board.c +++ /dev/null | |||
| @@ -1,113 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * File: arch/blackfin/mach-bf561/generic_board.c | ||
| 3 | * Based on: arch/blackfin/mach-bf533/ezkit.c | ||
| 4 | * Author: Aidan Williams <aidan@nicta.com.au> | ||
| 5 | * | ||
| 6 | * Created: | ||
| 7 | * Description: | ||
| 8 | * | ||
| 9 | * Modified: | ||
| 10 | * Copyright 2005 National ICT Australia (NICTA) | ||
| 11 | * Copyright 2004-2006 Analog Devices Inc. | ||
| 12 | * | ||
| 13 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2 of the License, or | ||
| 18 | * (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; if not, see the file COPYING, or write | ||
| 27 | * to the Free Software Foundation, Inc., | ||
| 28 | * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | ||
| 29 | */ | ||
| 30 | |||
| 31 | #include <linux/device.h> | ||
| 32 | #include <linux/platform_device.h> | ||
| 33 | #include <linux/irq.h> | ||
| 34 | |||
| 35 | const char bfin_board_name[] = "UNKNOWN BOARD"; | ||
| 36 | |||
| 37 | /* | ||
| 38 | * Driver needs to know address, irq and flag pin. | ||
| 39 | */ | ||
| 40 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | ||
| 41 | static struct resource smc91x_resources[] = { | ||
| 42 | { | ||
| 43 | .start = 0x2C010300, | ||
| 44 | .end = 0x2C010300 + 16, | ||
| 45 | .flags = IORESOURCE_MEM, | ||
| 46 | }, { | ||
| 47 | .start = IRQ_PROG_INTB, | ||
| 48 | .end = IRQ_PROG_INTB, | ||
| 49 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | ||
| 50 | }, { | ||
| 51 | .start = IRQ_PF9, | ||
| 52 | .end = IRQ_PF9, | ||
| 53 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, | ||
| 54 | }, | ||
| 55 | }; | ||
| 56 | |||
| 57 | static struct platform_device smc91x_device = { | ||
| 58 | .name = "smc91x", | ||
| 59 | .id = 0, | ||
| 60 | .num_resources = ARRAY_SIZE(smc91x_resources), | ||
| 61 | .resource = smc91x_resources, | ||
| 62 | }; | ||
| 63 | #endif | ||
| 64 | |||
| 65 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
| 66 | #ifdef CONFIG_BFIN_SIR0 | ||
| 67 | static struct resource bfin_sir0_resources[] = { | ||
| 68 | { | ||
| 69 | .start = 0xFFC00400, | ||
| 70 | .end = 0xFFC004FF, | ||
| 71 | .flags = IORESOURCE_MEM, | ||
| 72 | }, | ||
| 73 | { | ||
| 74 | .start = IRQ_UART0_RX, | ||
| 75 | .end = IRQ_UART0_RX+1, | ||
| 76 | .flags = IORESOURCE_IRQ, | ||
| 77 | }, | ||
| 78 | { | ||
| 79 | .start = CH_UART0_RX, | ||
| 80 | .end = CH_UART0_RX+1, | ||
| 81 | .flags = IORESOURCE_DMA, | ||
| 82 | }, | ||
| 83 | }; | ||
| 84 | |||
| 85 | static struct platform_device bfin_sir0_device = { | ||
| 86 | .name = "bfin_sir", | ||
| 87 | .id = 0, | ||
| 88 | .num_resources = ARRAY_SIZE(bfin_sir0_resources), | ||
| 89 | .resource = bfin_sir0_resources, | ||
| 90 | }; | ||
| 91 | #endif | ||
| 92 | #endif | ||
| 93 | |||
| 94 | static struct platform_device *generic_board_devices[] __initdata = { | ||
| 95 | #if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE) | ||
| 96 | &smc91x_device, | ||
| 97 | #endif | ||
| 98 | |||
| 99 | #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE) | ||
| 100 | #ifdef CONFIG_BFIN_SIR0 | ||
| 101 | &bfin_sir0_device, | ||
| 102 | #endif | ||
| 103 | #endif | ||
| 104 | }; | ||
| 105 | |||
| 106 | static int __init generic_board_init(void) | ||
| 107 | { | ||
| 108 | printk(KERN_INFO "%s(): registering device resources\n", __func__); | ||
| 109 | return platform_add_devices(generic_board_devices, | ||
| 110 | ARRAY_SIZE(generic_board_devices)); | ||
| 111 | } | ||
| 112 | |||
| 113 | arch_initcall(generic_board_init); | ||
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h index 1a9e17562821..d0b0b3506440 100644 --- a/arch/blackfin/mach-bf561/include/mach/anomaly.h +++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h | |||
| @@ -2,7 +2,7 @@ | |||
| 2 | * File: include/asm-blackfin/mach-bf561/anomaly.h | 2 | * File: include/asm-blackfin/mach-bf561/anomaly.h |
| 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
| 4 | * | 4 | * |
| 5 | * Copyright (C) 2004-2008 Analog Devices Inc. | 5 | * Copyright (C) 2004-2009 Analog Devices Inc. |
| 6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
| 7 | */ | 7 | */ |
| 8 | 8 | ||
| @@ -224,7 +224,7 @@ | |||
| 224 | #define ANOMALY_05000301 (1) | 224 | #define ANOMALY_05000301 (1) |
| 225 | /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ | 225 | /* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */ |
| 226 | #define ANOMALY_05000302 (1) | 226 | #define ANOMALY_05000302 (1) |
| 227 | /* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */ | 227 | /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */ |
| 228 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) | 228 | #define ANOMALY_05000305 (__SILICON_REVISION__ < 5) |
| 229 | /* SCKELOW Bit Does Not Maintain State Through Hibernate */ | 229 | /* SCKELOW Bit Does Not Maintain State Through Hibernate */ |
| 230 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 5) | 230 | #define ANOMALY_05000307 (__SILICON_REVISION__ < 5) |
| @@ -283,8 +283,11 @@ | |||
| 283 | #define ANOMALY_05000273 (0) | 283 | #define ANOMALY_05000273 (0) |
| 284 | #define ANOMALY_05000311 (0) | 284 | #define ANOMALY_05000311 (0) |
| 285 | #define ANOMALY_05000353 (1) | 285 | #define ANOMALY_05000353 (1) |
| 286 | #define ANOMALY_05000380 (0) | ||
| 286 | #define ANOMALY_05000386 (1) | 287 | #define ANOMALY_05000386 (1) |
| 287 | #define ANOMALY_05000432 (0) | 288 | #define ANOMALY_05000432 (0) |
| 288 | #define ANOMALY_05000435 (0) | 289 | #define ANOMALY_05000435 (0) |
| 290 | #define ANOMALY_05000447 (0) | ||
| 291 | #define ANOMALY_05000448 (0) | ||
| 289 | 292 | ||
| 290 | #endif | 293 | #endif |
diff --git a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h index 043bfcf26c52..ca8c5f645209 100644 --- a/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h +++ b/arch/blackfin/mach-bf561/include/mach/bfin_serial_5xx.h | |||
| @@ -134,7 +134,7 @@ struct bfin_serial_res bfin_serial_resource[] = { | |||
| 134 | CH_UART_TX, | 134 | CH_UART_TX, |
| 135 | CH_UART_RX, | 135 | CH_UART_RX, |
| 136 | #endif | 136 | #endif |
| 137 | #ifdef CONFIG_BFIN_UART0_CTSRTS | 137 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
| 138 | CONFIG_UART0_CTS_PIN, | 138 | CONFIG_UART0_CTS_PIN, |
| 139 | CONFIG_UART0_RTS_PIN, | 139 | CONFIG_UART0_RTS_PIN, |
| 140 | #endif | 140 | #endif |
diff --git a/arch/blackfin/mach-common/arch_checks.c b/arch/blackfin/mach-common/arch_checks.c index 98133b968f7b..80d39b2f9db2 100644 --- a/arch/blackfin/mach-common/arch_checks.c +++ b/arch/blackfin/mach-common/arch_checks.c | |||
| @@ -62,3 +62,12 @@ | |||
| 62 | #if (CONFIG_BOOT_LOAD & 0x3) | 62 | #if (CONFIG_BOOT_LOAD & 0x3) |
| 63 | # error "The kernel load address must be 4 byte aligned" | 63 | # error "The kernel load address must be 4 byte aligned" |
| 64 | #endif | 64 | #endif |
| 65 | |||
| 66 | /* The entire kernel must be able to make a 24bit pcrel call to start of L1 */ | ||
| 67 | #if ((0xffffffff - L1_CODE_START + 1) + CONFIG_BOOT_LOAD) > 0x1000000 | ||
| 68 | # error "The kernel load address is too high; keep it below 10meg for safety" | ||
| 69 | #endif | ||
| 70 | |||
| 71 | #if ANOMALY_05000448 | ||
| 72 | # error You are using a part with anomaly 05000448, this issue causes random memory read/write failures - that means random crashes. | ||
| 73 | #endif | ||
diff --git a/arch/blackfin/mach-common/cache.S b/arch/blackfin/mach-common/cache.S index 3c98dacbf289..aa0648c6a9fe 100644 --- a/arch/blackfin/mach-common/cache.S +++ b/arch/blackfin/mach-common/cache.S | |||
| @@ -66,11 +66,33 @@ | |||
| 66 | 66 | ||
| 67 | /* Invalidate all instruction cache lines assocoiated with this memory area */ | 67 | /* Invalidate all instruction cache lines assocoiated with this memory area */ |
| 68 | ENTRY(_blackfin_icache_flush_range) | 68 | ENTRY(_blackfin_icache_flush_range) |
| 69 | /* | ||
| 70 | * Walkaround to avoid loading wrong instruction after invalidating icache | ||
| 71 | * and following sequence is met. | ||
| 72 | * | ||
| 73 | * 1) One instruction address is cached in the instruction cache. | ||
| 74 | * 2) This instruction in SDRAM is changed. | ||
| 75 | * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range(). | ||
| 76 | * 4) This instruction is executed again, but the old one is loaded. | ||
| 77 | */ | ||
| 78 | P0 = R0; | ||
| 79 | IFLUSH[P0]; | ||
| 69 | do_flush IFLUSH, , nop | 80 | do_flush IFLUSH, , nop |
| 70 | ENDPROC(_blackfin_icache_flush_range) | 81 | ENDPROC(_blackfin_icache_flush_range) |
| 71 | 82 | ||
| 72 | /* Flush all cache lines assocoiated with this area of memory. */ | 83 | /* Flush all cache lines assocoiated with this area of memory. */ |
| 73 | ENTRY(_blackfin_icache_dcache_flush_range) | 84 | ENTRY(_blackfin_icache_dcache_flush_range) |
| 85 | /* | ||
| 86 | * Walkaround to avoid loading wrong instruction after invalidating icache | ||
| 87 | * and following sequence is met. | ||
| 88 | * | ||
| 89 | * 1) One instruction address is cached in the instruction cache. | ||
| 90 | * 2) This instruction in SDRAM is changed. | ||
| 91 | * 3) IFLASH[P0] is executed only once in blackfin_icache_flush_range(). | ||
| 92 | * 4) This instruction is executed again, but the old one is loaded. | ||
| 93 | */ | ||
| 94 | P0 = R0; | ||
| 95 | IFLUSH[P0]; | ||
| 74 | do_flush FLUSH, IFLUSH | 96 | do_flush FLUSH, IFLUSH |
| 75 | ENDPROC(_blackfin_icache_dcache_flush_range) | 97 | ENDPROC(_blackfin_icache_dcache_flush_range) |
| 76 | 98 | ||
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c index 9dddb6f8cc85..35393651359b 100644 --- a/arch/blackfin/mach-common/clocks-init.c +++ b/arch/blackfin/mach-common/clocks-init.c | |||
| @@ -17,7 +17,7 @@ | |||
| 17 | #define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ | 17 | #define SDGCTL_WIDTH (1 << 31) /* SDRAM external data path width */ |
| 18 | #define PLL_CTL_VAL \ | 18 | #define PLL_CTL_VAL \ |
| 19 | (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ | 19 | (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \ |
| 20 | (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0)) | 20 | (PLL_BYPASS << 8) | (ANOMALY_05000305 ? 0 : 0x8000)) |
| 21 | 21 | ||
| 22 | __attribute__((l1_text)) | 22 | __attribute__((l1_text)) |
| 23 | static void do_sync(void) | 23 | static void do_sync(void) |
diff --git a/arch/blackfin/mach-common/dpmc_modes.S b/arch/blackfin/mach-common/dpmc_modes.S index 4da50bcd9300..8009a512fb11 100644 --- a/arch/blackfin/mach-common/dpmc_modes.S +++ b/arch/blackfin/mach-common/dpmc_modes.S | |||
| @@ -376,10 +376,22 @@ ENTRY(_do_hibernate) | |||
| 376 | #endif | 376 | #endif |
| 377 | 377 | ||
| 378 | #ifdef PINT0_ASSIGN | 378 | #ifdef PINT0_ASSIGN |
| 379 | PM_SYS_PUSH(PINT0_MASK_SET) | ||
| 380 | PM_SYS_PUSH(PINT1_MASK_SET) | ||
| 381 | PM_SYS_PUSH(PINT2_MASK_SET) | ||
| 382 | PM_SYS_PUSH(PINT3_MASK_SET) | ||
| 379 | PM_SYS_PUSH(PINT0_ASSIGN) | 383 | PM_SYS_PUSH(PINT0_ASSIGN) |
| 380 | PM_SYS_PUSH(PINT1_ASSIGN) | 384 | PM_SYS_PUSH(PINT1_ASSIGN) |
| 381 | PM_SYS_PUSH(PINT2_ASSIGN) | 385 | PM_SYS_PUSH(PINT2_ASSIGN) |
| 382 | PM_SYS_PUSH(PINT3_ASSIGN) | 386 | PM_SYS_PUSH(PINT3_ASSIGN) |
| 387 | PM_SYS_PUSH(PINT0_INVERT_SET) | ||
| 388 | PM_SYS_PUSH(PINT1_INVERT_SET) | ||
| 389 | PM_SYS_PUSH(PINT2_INVERT_SET) | ||
| 390 | PM_SYS_PUSH(PINT3_INVERT_SET) | ||
| 391 | PM_SYS_PUSH(PINT0_EDGE_SET) | ||
| 392 | PM_SYS_PUSH(PINT1_EDGE_SET) | ||
| 393 | PM_SYS_PUSH(PINT2_EDGE_SET) | ||
| 394 | PM_SYS_PUSH(PINT3_EDGE_SET) | ||
| 383 | #endif | 395 | #endif |
| 384 | 396 | ||
| 385 | PM_SYS_PUSH(EBIU_AMBCTL0) | 397 | PM_SYS_PUSH(EBIU_AMBCTL0) |
| @@ -714,10 +726,22 @@ ENTRY(_do_hibernate) | |||
| 714 | PM_SYS_POP(EBIU_AMBCTL0) | 726 | PM_SYS_POP(EBIU_AMBCTL0) |
| 715 | 727 | ||
| 716 | #ifdef PINT0_ASSIGN | 728 | #ifdef PINT0_ASSIGN |
| 729 | PM_SYS_POP(PINT3_EDGE_SET) | ||
| 730 | PM_SYS_POP(PINT2_EDGE_SET) | ||
| 731 | PM_SYS_POP(PINT1_EDGE_SET) | ||
| 732 | PM_SYS_POP(PINT0_EDGE_SET) | ||
| 733 | PM_SYS_POP(PINT3_INVERT_SET) | ||
| 734 | PM_SYS_POP(PINT2_INVERT_SET) | ||
| 735 | PM_SYS_POP(PINT1_INVERT_SET) | ||
| 736 | PM_SYS_POP(PINT0_INVERT_SET) | ||
| 717 | PM_SYS_POP(PINT3_ASSIGN) | 737 | PM_SYS_POP(PINT3_ASSIGN) |
| 718 | PM_SYS_POP(PINT2_ASSIGN) | 738 | PM_SYS_POP(PINT2_ASSIGN) |
| 719 | PM_SYS_POP(PINT1_ASSIGN) | 739 | PM_SYS_POP(PINT1_ASSIGN) |
| 720 | PM_SYS_POP(PINT0_ASSIGN) | 740 | PM_SYS_POP(PINT0_ASSIGN) |
| 741 | PM_SYS_POP(PINT3_MASK_SET) | ||
| 742 | PM_SYS_POP(PINT2_MASK_SET) | ||
| 743 | PM_SYS_POP(PINT1_MASK_SET) | ||
| 744 | PM_SYS_POP(PINT0_MASK_SET) | ||
| 721 | #endif | 745 | #endif |
| 722 | 746 | ||
| 723 | #ifdef SICA_IWR1 | 747 | #ifdef SICA_IWR1 |
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S index 88de053bbe8e..21e65a339a22 100644 --- a/arch/blackfin/mach-common/entry.S +++ b/arch/blackfin/mach-common/entry.S | |||
| @@ -600,6 +600,19 @@ ENTRY(_system_call) | |||
| 600 | p2 = [p2]; | 600 | p2 = [p2]; |
| 601 | 601 | ||
| 602 | [p2+(TASK_THREAD+THREAD_KSP)] = sp; | 602 | [p2+(TASK_THREAD+THREAD_KSP)] = sp; |
| 603 | #ifdef CONFIG_IPIPE | ||
| 604 | r0 = sp; | ||
| 605 | SP += -12; | ||
| 606 | call ___ipipe_syscall_root; | ||
| 607 | SP += 12; | ||
| 608 | cc = r0 == 1; | ||
| 609 | if cc jump .Lsyscall_really_exit; | ||
| 610 | cc = r0 == -1; | ||
| 611 | if cc jump .Lresume_userspace; | ||
| 612 | r3 = [sp + PT_R3]; | ||
| 613 | r4 = [sp + PT_R4]; | ||
| 614 | p0 = [sp + PT_ORIG_P0]; | ||
| 615 | #endif /* CONFIG_IPIPE */ | ||
| 603 | 616 | ||
| 604 | /* Check the System Call */ | 617 | /* Check the System Call */ |
| 605 | r7 = __NR_syscall; | 618 | r7 = __NR_syscall; |
| @@ -654,6 +667,17 @@ ENTRY(_system_call) | |||
| 654 | r7 = r7 & r4; | 667 | r7 = r7 & r4; |
| 655 | 668 | ||
| 656 | .Lsyscall_resched: | 669 | .Lsyscall_resched: |
| 670 | #ifdef CONFIG_IPIPE | ||
| 671 | cc = BITTST(r7, TIF_IRQ_SYNC); | ||
| 672 | if !cc jump .Lsyscall_no_irqsync; | ||
| 673 | [--sp] = reti; | ||
| 674 | r0 = [sp++]; | ||
| 675 | SP += -12; | ||
| 676 | call ___ipipe_sync_root; | ||
| 677 | SP += 12; | ||
| 678 | jump .Lresume_userspace_1; | ||
| 679 | .Lsyscall_no_irqsync: | ||
| 680 | #endif | ||
| 657 | cc = BITTST(r7, TIF_NEED_RESCHED); | 681 | cc = BITTST(r7, TIF_NEED_RESCHED); |
| 658 | if !cc jump .Lsyscall_sigpending; | 682 | if !cc jump .Lsyscall_sigpending; |
| 659 | 683 | ||
| @@ -685,6 +709,10 @@ ENTRY(_system_call) | |||
| 685 | .Lsyscall_really_exit: | 709 | .Lsyscall_really_exit: |
| 686 | r5 = [sp + PT_RESERVED]; | 710 | r5 = [sp + PT_RESERVED]; |
| 687 | rets = r5; | 711 | rets = r5; |
| 712 | #ifdef CONFIG_IPIPE | ||
| 713 | [--sp] = reti; | ||
| 714 | r5 = [sp++]; | ||
| 715 | #endif /* CONFIG_IPIPE */ | ||
| 688 | rts; | 716 | rts; |
| 689 | ENDPROC(_system_call) | 717 | ENDPROC(_system_call) |
| 690 | 718 | ||
| @@ -771,6 +799,15 @@ _new_old_task: | |||
| 771 | ENDPROC(_resume) | 799 | ENDPROC(_resume) |
| 772 | 800 | ||
| 773 | ENTRY(_ret_from_exception) | 801 | ENTRY(_ret_from_exception) |
| 802 | #ifdef CONFIG_IPIPE | ||
| 803 | [--sp] = rets; | ||
| 804 | SP += -12; | ||
| 805 | call ___ipipe_check_root | ||
| 806 | SP += 12 | ||
| 807 | rets = [sp++]; | ||
| 808 | cc = r0 == 0; | ||
| 809 | if cc jump 4f; /* not on behalf of Linux, get out */ | ||
| 810 | #endif /* CONFIG_IPIPE */ | ||
| 774 | p2.l = lo(IPEND); | 811 | p2.l = lo(IPEND); |
| 775 | p2.h = hi(IPEND); | 812 | p2.h = hi(IPEND); |
| 776 | 813 | ||
| @@ -827,6 +864,28 @@ ENTRY(_ret_from_exception) | |||
| 827 | rts; | 864 | rts; |
| 828 | ENDPROC(_ret_from_exception) | 865 | ENDPROC(_ret_from_exception) |
| 829 | 866 | ||
| 867 | #ifdef CONFIG_IPIPE | ||
| 868 | |||
| 869 | _sync_root_irqs: | ||
| 870 | [--sp] = reti; /* Reenable interrupts */ | ||
| 871 | r0 = [sp++]; | ||
| 872 | jump.l ___ipipe_sync_root | ||
| 873 | |||
| 874 | _resume_kernel_from_int: | ||
| 875 | r0.l = _sync_root_irqs | ||
| 876 | r0.h = _sync_root_irqs | ||
| 877 | [--sp] = rets; | ||
| 878 | [--sp] = ( r7:4, p5:3 ); | ||
| 879 | SP += -12; | ||
| 880 | call ___ipipe_call_irqtail | ||
| 881 | SP += 12; | ||
| 882 | ( r7:4, p5:3 ) = [sp++]; | ||
| 883 | rets = [sp++]; | ||
| 884 | rts | ||
| 885 | #else | ||
| 886 | #define _resume_kernel_from_int 2f | ||
| 887 | #endif | ||
| 888 | |||
| 830 | ENTRY(_return_from_int) | 889 | ENTRY(_return_from_int) |
| 831 | /* If someone else already raised IRQ 15, do nothing. */ | 890 | /* If someone else already raised IRQ 15, do nothing. */ |
| 832 | csync; | 891 | csync; |
| @@ -848,7 +907,7 @@ ENTRY(_return_from_int) | |||
| 848 | r1 = r0 - r1; | 907 | r1 = r0 - r1; |
| 849 | r2 = r0 & r1; | 908 | r2 = r0 & r1; |
| 850 | cc = r2 == 0; | 909 | cc = r2 == 0; |
| 851 | if !cc jump 2f; | 910 | if !cc jump _resume_kernel_from_int; |
| 852 | 911 | ||
| 853 | /* Lower the interrupt level to 15. */ | 912 | /* Lower the interrupt level to 15. */ |
| 854 | p0.l = lo(EVT15); | 913 | p0.l = lo(EVT15); |
diff --git a/arch/blackfin/mach-common/interrupt.S b/arch/blackfin/mach-common/interrupt.S index 43c4eb9acb65..0069c2dd4625 100644 --- a/arch/blackfin/mach-common/interrupt.S +++ b/arch/blackfin/mach-common/interrupt.S | |||
| @@ -235,6 +235,7 @@ ENDPROC(_evt_system_call) | |||
| 235 | 235 | ||
| 236 | #ifdef CONFIG_IPIPE | 236 | #ifdef CONFIG_IPIPE |
| 237 | ENTRY(___ipipe_call_irqtail) | 237 | ENTRY(___ipipe_call_irqtail) |
| 238 | p0 = r0; | ||
| 238 | r0.l = 1f; | 239 | r0.l = 1f; |
| 239 | r0.h = 1f; | 240 | r0.h = 1f; |
| 240 | reti = r0; | 241 | reti = r0; |
| @@ -242,9 +243,6 @@ ENTRY(___ipipe_call_irqtail) | |||
| 242 | 1: | 243 | 1: |
| 243 | [--sp] = rets; | 244 | [--sp] = rets; |
| 244 | [--sp] = ( r7:4, p5:3 ); | 245 | [--sp] = ( r7:4, p5:3 ); |
| 245 | p0.l = ___ipipe_irq_tail_hook; | ||
| 246 | p0.h = ___ipipe_irq_tail_hook; | ||
| 247 | p0 = [p0]; | ||
| 248 | sp += -12; | 246 | sp += -12; |
| 249 | call (p0); | 247 | call (p0); |
| 250 | sp += 12; | 248 | sp += 12; |
| @@ -259,7 +257,7 @@ ENTRY(___ipipe_call_irqtail) | |||
| 259 | p0.h = hi(EVT14); | 257 | p0.h = hi(EVT14); |
| 260 | [p0] = r0; | 258 | [p0] = r0; |
| 261 | csync; | 259 | csync; |
| 262 | r0 = 0x401f; | 260 | r0 = 0x401f (z); |
| 263 | sti r0; | 261 | sti r0; |
| 264 | raise 14; | 262 | raise 14; |
| 265 | [--sp] = reti; /* IRQs on. */ | 263 | [--sp] = reti; /* IRQs on. */ |
| @@ -277,11 +275,7 @@ ENTRY(___ipipe_call_irqtail) | |||
| 277 | p0.h = _bfin_irq_flags; | 275 | p0.h = _bfin_irq_flags; |
| 278 | r0 = [p0]; | 276 | r0 = [p0]; |
| 279 | sti r0; | 277 | sti r0; |
| 280 | #if 0 /* FIXME: this actually raises scheduling latencies */ | ||
| 281 | /* Reenable interrupts */ | ||
| 282 | [--sp] = reti; | ||
| 283 | r0 = [sp++]; | ||
| 284 | #endif | ||
| 285 | rts; | 278 | rts; |
| 286 | ENDPROC(___ipipe_call_irqtail) | 279 | ENDPROC(___ipipe_call_irqtail) |
| 280 | |||
| 287 | #endif /* CONFIG_IPIPE */ | 281 | #endif /* CONFIG_IPIPE */ |
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c index 202494568c6c..a7d7b2dd4059 100644 --- a/arch/blackfin/mach-common/ints-priority.c +++ b/arch/blackfin/mach-common/ints-priority.c | |||
| @@ -161,11 +161,15 @@ static void bfin_core_unmask_irq(unsigned int irq) | |||
| 161 | 161 | ||
| 162 | static void bfin_internal_mask_irq(unsigned int irq) | 162 | static void bfin_internal_mask_irq(unsigned int irq) |
| 163 | { | 163 | { |
| 164 | unsigned long flags; | ||
| 165 | |||
| 164 | #ifdef CONFIG_BF53x | 166 | #ifdef CONFIG_BF53x |
| 167 | local_irq_save_hw(flags); | ||
| 165 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & | 168 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & |
| 166 | ~(1 << SIC_SYSIRQ(irq))); | 169 | ~(1 << SIC_SYSIRQ(irq))); |
| 167 | #else | 170 | #else |
| 168 | unsigned mask_bank, mask_bit; | 171 | unsigned mask_bank, mask_bit; |
| 172 | local_irq_save_hw(flags); | ||
| 169 | mask_bank = SIC_SYSIRQ(irq) / 32; | 173 | mask_bank = SIC_SYSIRQ(irq) / 32; |
| 170 | mask_bit = SIC_SYSIRQ(irq) % 32; | 174 | mask_bit = SIC_SYSIRQ(irq) % 32; |
| 171 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & | 175 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & |
| @@ -175,15 +179,20 @@ static void bfin_internal_mask_irq(unsigned int irq) | |||
| 175 | ~(1 << mask_bit)); | 179 | ~(1 << mask_bit)); |
| 176 | #endif | 180 | #endif |
| 177 | #endif | 181 | #endif |
| 182 | local_irq_restore_hw(flags); | ||
| 178 | } | 183 | } |
| 179 | 184 | ||
| 180 | static void bfin_internal_unmask_irq(unsigned int irq) | 185 | static void bfin_internal_unmask_irq(unsigned int irq) |
| 181 | { | 186 | { |
| 187 | unsigned long flags; | ||
| 188 | |||
| 182 | #ifdef CONFIG_BF53x | 189 | #ifdef CONFIG_BF53x |
| 190 | local_irq_save_hw(flags); | ||
| 183 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | | 191 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | |
| 184 | (1 << SIC_SYSIRQ(irq))); | 192 | (1 << SIC_SYSIRQ(irq))); |
| 185 | #else | 193 | #else |
| 186 | unsigned mask_bank, mask_bit; | 194 | unsigned mask_bank, mask_bit; |
| 195 | local_irq_save_hw(flags); | ||
| 187 | mask_bank = SIC_SYSIRQ(irq) / 32; | 196 | mask_bank = SIC_SYSIRQ(irq) / 32; |
| 188 | mask_bit = SIC_SYSIRQ(irq) % 32; | 197 | mask_bit = SIC_SYSIRQ(irq) % 32; |
| 189 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | | 198 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) | |
| @@ -193,6 +202,7 @@ static void bfin_internal_unmask_irq(unsigned int irq) | |||
| 193 | (1 << mask_bit)); | 202 | (1 << mask_bit)); |
| 194 | #endif | 203 | #endif |
| 195 | #endif | 204 | #endif |
| 205 | local_irq_restore_hw(flags); | ||
| 196 | } | 206 | } |
| 197 | 207 | ||
| 198 | #ifdef CONFIG_PM | 208 | #ifdef CONFIG_PM |
| @@ -390,7 +400,7 @@ static void bfin_demux_error_irq(unsigned int int_err_irq, | |||
| 390 | static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) | 400 | static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) |
| 391 | { | 401 | { |
| 392 | #ifdef CONFIG_IPIPE | 402 | #ifdef CONFIG_IPIPE |
| 393 | _set_irq_handler(irq, handle_edge_irq); | 403 | _set_irq_handler(irq, handle_level_irq); |
| 394 | #else | 404 | #else |
| 395 | struct irq_desc *desc = irq_desc + irq; | 405 | struct irq_desc *desc = irq_desc + irq; |
| 396 | /* May not call generic set_irq_handler() due to spinlock | 406 | /* May not call generic set_irq_handler() due to spinlock |
| @@ -1055,13 +1065,18 @@ int __init init_arch_irq(void) | |||
| 1055 | #endif | 1065 | #endif |
| 1056 | default: | 1066 | default: |
| 1057 | #ifdef CONFIG_IPIPE | 1067 | #ifdef CONFIG_IPIPE |
| 1058 | /* | 1068 | /* |
| 1059 | * We want internal interrupt sources to be masked, because | 1069 | * We want internal interrupt sources to be |
| 1060 | * ISRs may trigger interrupts recursively (e.g. DMA), but | 1070 | * masked, because ISRs may trigger interrupts |
| 1061 | * interrupts are _not_ masked at CPU level. So let's handle | 1071 | * recursively (e.g. DMA), but interrupts are |
| 1062 | * them as level interrupts. | 1072 | * _not_ masked at CPU level. So let's handle |
| 1063 | */ | 1073 | * most of them as level interrupts, except |
| 1064 | set_irq_handler(irq, handle_level_irq); | 1074 | * the timer interrupt which is special. |
| 1075 | */ | ||
| 1076 | if (irq == IRQ_SYSTMR || irq == IRQ_CORETMR) | ||
| 1077 | set_irq_handler(irq, handle_simple_irq); | ||
| 1078 | else | ||
| 1079 | set_irq_handler(irq, handle_level_irq); | ||
| 1065 | #else /* !CONFIG_IPIPE */ | 1080 | #else /* !CONFIG_IPIPE */ |
| 1066 | set_irq_handler(irq, handle_simple_irq); | 1081 | set_irq_handler(irq, handle_simple_irq); |
| 1067 | #endif /* !CONFIG_IPIPE */ | 1082 | #endif /* !CONFIG_IPIPE */ |
| @@ -1123,9 +1138,8 @@ int __init init_arch_irq(void) | |||
| 1123 | 1138 | ||
| 1124 | #ifdef CONFIG_IPIPE | 1139 | #ifdef CONFIG_IPIPE |
| 1125 | for (irq = 0; irq < NR_IRQS; irq++) { | 1140 | for (irq = 0; irq < NR_IRQS; irq++) { |
| 1126 | struct irq_desc *desc = irq_desc + irq; | 1141 | struct irq_desc *desc = irq_to_desc(irq); |
| 1127 | desc->ic_prio = __ipipe_get_irq_priority(irq); | 1142 | desc->ic_prio = __ipipe_get_irq_priority(irq); |
| 1128 | desc->thr_prio = __ipipe_get_irqthread_priority(irq); | ||
| 1129 | } | 1143 | } |
| 1130 | #endif /* CONFIG_IPIPE */ | 1144 | #endif /* CONFIG_IPIPE */ |
| 1131 | 1145 | ||
| @@ -1208,76 +1222,21 @@ int __ipipe_get_irq_priority(unsigned irq) | |||
| 1208 | return IVG15; | 1222 | return IVG15; |
| 1209 | } | 1223 | } |
| 1210 | 1224 | ||
| 1211 | int __ipipe_get_irqthread_priority(unsigned irq) | ||
| 1212 | { | ||
| 1213 | int ient, prio; | ||
| 1214 | int demux_irq; | ||
| 1215 | |||
| 1216 | /* The returned priority value is rescaled to [0..IVG13+1] | ||
| 1217 | * with 0 being the lowest effective priority level. */ | ||
| 1218 | |||
| 1219 | if (irq <= IRQ_CORETMR) | ||
| 1220 | return IVG13 - irq + 1; | ||
| 1221 | |||
| 1222 | /* GPIO IRQs are given the priority of the demux | ||
| 1223 | * interrupt. */ | ||
| 1224 | if (IS_GPIOIRQ(irq)) { | ||
| 1225 | #if defined(CONFIG_BF54x) | ||
| 1226 | u32 bank = PINT_2_BANK(irq2pint_lut[irq - SYS_IRQS]); | ||
| 1227 | demux_irq = (bank == 0 ? IRQ_PINT0 : | ||
| 1228 | bank == 1 ? IRQ_PINT1 : | ||
| 1229 | bank == 2 ? IRQ_PINT2 : | ||
| 1230 | IRQ_PINT3); | ||
| 1231 | #elif defined(CONFIG_BF561) | ||
| 1232 | demux_irq = (irq >= IRQ_PF32 ? IRQ_PROG2_INTA : | ||
| 1233 | irq >= IRQ_PF16 ? IRQ_PROG1_INTA : | ||
| 1234 | IRQ_PROG0_INTA); | ||
| 1235 | #elif defined(CONFIG_BF52x) | ||
| 1236 | demux_irq = (irq >= IRQ_PH0 ? IRQ_PORTH_INTA : | ||
| 1237 | irq >= IRQ_PG0 ? IRQ_PORTG_INTA : | ||
| 1238 | IRQ_PORTF_INTA); | ||
| 1239 | #else | ||
| 1240 | demux_irq = irq; | ||
| 1241 | #endif | ||
| 1242 | return IVG13 - PRIO_GPIODEMUX(demux_irq) + 1; | ||
| 1243 | } | ||
| 1244 | |||
| 1245 | /* The GPIO demux interrupt is given a lower priority | ||
| 1246 | * than the GPIO IRQs, so that its threaded handler | ||
| 1247 | * unmasks the interrupt line after the decoded IRQs | ||
| 1248 | * have been processed. */ | ||
| 1249 | prio = PRIO_GPIODEMUX(irq); | ||
| 1250 | /* demux irq? */ | ||
| 1251 | if (prio != -1) | ||
| 1252 | return IVG13 - prio; | ||
| 1253 | |||
| 1254 | for (ient = 0; ient < NR_PERI_INTS; ient++) { | ||
| 1255 | struct ivgx *ivg = ivg_table + ient; | ||
| 1256 | if (ivg->irqno == irq) { | ||
| 1257 | for (prio = 0; prio <= IVG13-IVG7; prio++) { | ||
| 1258 | if (ivg7_13[prio].ifirst <= ivg && | ||
| 1259 | ivg7_13[prio].istop > ivg) | ||
| 1260 | return IVG7 - prio; | ||
| 1261 | } | ||
| 1262 | } | ||
| 1263 | } | ||
| 1264 | |||
| 1265 | return 0; | ||
| 1266 | } | ||
| 1267 | |||
| 1268 | /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */ | 1225 | /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */ |
| 1269 | #ifdef CONFIG_DO_IRQ_L1 | 1226 | #ifdef CONFIG_DO_IRQ_L1 |
| 1270 | __attribute__((l1_text)) | 1227 | __attribute__((l1_text)) |
| 1271 | #endif | 1228 | #endif |
| 1272 | asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) | 1229 | asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) |
| 1273 | { | 1230 | { |
| 1231 | struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); | ||
| 1232 | struct ipipe_domain *this_domain = ipipe_current_domain; | ||
| 1274 | struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; | 1233 | struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop; |
| 1275 | struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; | 1234 | struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst; |
| 1276 | int irq; | 1235 | int irq, s; |
| 1277 | 1236 | ||
| 1278 | if (likely(vec == EVT_IVTMR_P)) { | 1237 | if (likely(vec == EVT_IVTMR_P)) { |
| 1279 | irq = IRQ_CORETMR; | 1238 | irq = IRQ_CORETMR; |
| 1280 | goto handle_irq; | 1239 | goto core_tick; |
| 1281 | } | 1240 | } |
| 1282 | 1241 | ||
| 1283 | SSYNC(); | 1242 | SSYNC(); |
| @@ -1319,24 +1278,39 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) | |||
| 1319 | irq = ivg->irqno; | 1278 | irq = ivg->irqno; |
| 1320 | 1279 | ||
| 1321 | if (irq == IRQ_SYSTMR) { | 1280 | if (irq == IRQ_SYSTMR) { |
| 1281 | #ifdef CONFIG_GENERIC_CLOCKEVENTS | ||
| 1282 | core_tick: | ||
| 1283 | #else | ||
| 1322 | bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ | 1284 | bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ |
| 1285 | #endif | ||
| 1323 | /* This is basically what we need from the register frame. */ | 1286 | /* This is basically what we need from the register frame. */ |
| 1324 | __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend; | 1287 | __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend; |
| 1325 | __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc; | 1288 | __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc; |
| 1326 | if (!ipipe_root_domain_p) | 1289 | if (this_domain != ipipe_root_domain) |
| 1327 | __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; | ||
| 1328 | else | ||
| 1329 | __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10; | 1290 | __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10; |
| 1291 | else | ||
| 1292 | __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; | ||
| 1330 | } | 1293 | } |
| 1331 | 1294 | ||
| 1332 | handle_irq: | 1295 | #ifndef CONFIG_GENERIC_CLOCKEVENTS |
| 1296 | core_tick: | ||
| 1297 | #endif | ||
| 1298 | if (this_domain == ipipe_root_domain) { | ||
| 1299 | s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status); | ||
| 1300 | barrier(); | ||
| 1301 | } | ||
| 1333 | 1302 | ||
| 1334 | ipipe_trace_irq_entry(irq); | 1303 | ipipe_trace_irq_entry(irq); |
| 1335 | __ipipe_handle_irq(irq, regs); | 1304 | __ipipe_handle_irq(irq, regs); |
| 1336 | ipipe_trace_irq_exit(irq); | 1305 | ipipe_trace_irq_exit(irq); |
| 1337 | 1306 | ||
| 1338 | if (ipipe_root_domain_p) | 1307 | if (this_domain == ipipe_root_domain) { |
| 1339 | return !test_bit(IPIPE_STALL_FLAG, &ipipe_root_cpudom_var(status)); | 1308 | set_thread_flag(TIF_IRQ_SYNC); |
| 1309 | if (!s) { | ||
| 1310 | __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status); | ||
| 1311 | return !test_bit(IPIPE_STALL_FLAG, &p->status); | ||
| 1312 | } | ||
| 1313 | } | ||
| 1340 | 1314 | ||
| 1341 | return 0; | 1315 | return 0; |
| 1342 | } | 1316 | } |
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c index 77c992847094..93eab6146079 100644 --- a/arch/blackfin/mach-common/smp.c +++ b/arch/blackfin/mach-common/smp.c | |||
| @@ -158,10 +158,14 @@ static irqreturn_t ipi_handler(int irq, void *dev_instance) | |||
| 158 | kfree(msg); | 158 | kfree(msg); |
| 159 | break; | 159 | break; |
| 160 | case BFIN_IPI_CALL_FUNC: | 160 | case BFIN_IPI_CALL_FUNC: |
| 161 | spin_unlock(&msg_queue->lock); | ||
| 161 | ipi_call_function(cpu, msg); | 162 | ipi_call_function(cpu, msg); |
| 163 | spin_lock(&msg_queue->lock); | ||
| 162 | break; | 164 | break; |
| 163 | case BFIN_IPI_CPU_STOP: | 165 | case BFIN_IPI_CPU_STOP: |
| 166 | spin_unlock(&msg_queue->lock); | ||
| 164 | ipi_cpu_stop(cpu); | 167 | ipi_cpu_stop(cpu); |
| 168 | spin_lock(&msg_queue->lock); | ||
| 165 | kfree(msg); | 169 | kfree(msg); |
| 166 | break; | 170 | break; |
| 167 | default: | 171 | default: |
| @@ -457,7 +461,7 @@ void smp_icache_flush_range_others(unsigned long start, unsigned long end) | |||
| 457 | smp_flush_data.start = start; | 461 | smp_flush_data.start = start; |
| 458 | smp_flush_data.end = end; | 462 | smp_flush_data.end = end; |
| 459 | 463 | ||
| 460 | if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 1)) | 464 | if (smp_call_function(&ipi_flush_icache, &smp_flush_data, 0)) |
| 461 | printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n"); | 465 | printk(KERN_WARNING "SMP: failed to run I-cache flush request on other CPUs\n"); |
| 462 | } | 466 | } |
| 463 | EXPORT_SYMBOL_GPL(smp_icache_flush_range_others); | 467 | EXPORT_SYMBOL_GPL(smp_icache_flush_range_others); |
diff --git a/arch/blackfin/mm/init.c b/arch/blackfin/mm/init.c index d0532b72bba5..9c3629b9a689 100644 --- a/arch/blackfin/mm/init.c +++ b/arch/blackfin/mm/init.c | |||
| @@ -104,7 +104,7 @@ void __init paging_init(void) | |||
| 104 | } | 104 | } |
| 105 | } | 105 | } |
| 106 | 106 | ||
| 107 | asmlinkage void init_pda(void) | 107 | asmlinkage void __init init_pda(void) |
| 108 | { | 108 | { |
| 109 | unsigned int cpu = raw_smp_processor_id(); | 109 | unsigned int cpu = raw_smp_processor_id(); |
| 110 | 110 | ||
diff --git a/arch/ia64/sn/pci/pcibr/pcibr_dma.c b/arch/ia64/sn/pci/pcibr/pcibr_dma.c index e626e50a938a..060df4aa9916 100644 --- a/arch/ia64/sn/pci/pcibr/pcibr_dma.c +++ b/arch/ia64/sn/pci/pcibr/pcibr_dma.c | |||
| @@ -135,11 +135,10 @@ pcibr_dmatrans_direct64(struct pcidev_info * info, u64 paddr, | |||
| 135 | if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS) | 135 | if (SN_DMA_ADDRTYPE(dma_flags) == SN_DMA_ADDR_PHYS) |
| 136 | pci_addr = IS_PIC_SOFT(pcibus_info) ? | 136 | pci_addr = IS_PIC_SOFT(pcibus_info) ? |
| 137 | PHYS_TO_DMA(paddr) : | 137 | PHYS_TO_DMA(paddr) : |
| 138 | PHYS_TO_TIODMA(paddr) | dma_attributes; | 138 | PHYS_TO_TIODMA(paddr); |
| 139 | else | 139 | else |
| 140 | pci_addr = IS_PIC_SOFT(pcibus_info) ? | 140 | pci_addr = paddr; |
| 141 | paddr : | 141 | pci_addr |= dma_attributes; |
| 142 | paddr | dma_attributes; | ||
| 143 | 142 | ||
| 144 | /* Handle Bus mode */ | 143 | /* Handle Bus mode */ |
| 145 | if (IS_PCIX(pcibus_info)) | 144 | if (IS_PCIX(pcibus_info)) |
diff --git a/arch/m68k/include/asm/param.h b/arch/m68k/include/asm/param.h index 40d1112a4588..85c41b75aa78 100644 --- a/arch/m68k/include/asm/param.h +++ b/arch/m68k/include/asm/param.h | |||
| @@ -1,5 +1,26 @@ | |||
| 1 | #ifndef _M68K_PARAM_H | ||
| 2 | #define _M68K_PARAM_H | ||
| 3 | |||
| 4 | #ifdef __KERNEL__ | ||
| 5 | # define HZ CONFIG_HZ /* Internal kernel timer frequency */ | ||
| 6 | # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ | ||
| 7 | # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ | ||
| 8 | #endif | ||
| 9 | |||
| 10 | #ifndef HZ | ||
| 11 | #define HZ 100 | ||
| 12 | #endif | ||
| 13 | |||
| 1 | #ifdef __uClinux__ | 14 | #ifdef __uClinux__ |
| 2 | #include "param_no.h" | 15 | #define EXEC_PAGESIZE 4096 |
| 3 | #else | 16 | #else |
| 4 | #include "param_mm.h" | 17 | #define EXEC_PAGESIZE 8192 |
| 18 | #endif | ||
| 19 | |||
| 20 | #ifndef NOGROUP | ||
| 21 | #define NOGROUP (-1) | ||
| 5 | #endif | 22 | #endif |
| 23 | |||
| 24 | #define MAXHOSTNAMELEN 64 /* max length of hostname */ | ||
| 25 | |||
| 26 | #endif /* _M68K_PARAM_H */ | ||
diff --git a/arch/m68k/include/asm/param_mm.h b/arch/m68k/include/asm/param_mm.h deleted file mode 100644 index 536a27888358..000000000000 --- a/arch/m68k/include/asm/param_mm.h +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | #ifndef _M68K_PARAM_H | ||
| 2 | #define _M68K_PARAM_H | ||
| 3 | |||
| 4 | #ifdef __KERNEL__ | ||
| 5 | # define HZ CONFIG_HZ /* Internal kernel timer frequency */ | ||
| 6 | # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ | ||
| 7 | # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ | ||
| 8 | #endif | ||
| 9 | |||
| 10 | #ifndef HZ | ||
| 11 | #define HZ 100 | ||
| 12 | #endif | ||
| 13 | |||
| 14 | #define EXEC_PAGESIZE 8192 | ||
| 15 | |||
| 16 | #ifndef NOGROUP | ||
| 17 | #define NOGROUP (-1) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #define MAXHOSTNAMELEN 64 /* max length of hostname */ | ||
| 21 | |||
| 22 | #endif /* _M68K_PARAM_H */ | ||
diff --git a/arch/m68k/include/asm/param_no.h b/arch/m68k/include/asm/param_no.h deleted file mode 100644 index 6044397adb64..000000000000 --- a/arch/m68k/include/asm/param_no.h +++ /dev/null | |||
| @@ -1,22 +0,0 @@ | |||
| 1 | #ifndef _M68KNOMMU_PARAM_H | ||
| 2 | #define _M68KNOMMU_PARAM_H | ||
| 3 | |||
| 4 | #ifdef __KERNEL__ | ||
| 5 | #define HZ CONFIG_HZ | ||
| 6 | #define USER_HZ HZ | ||
| 7 | #define CLOCKS_PER_SEC (USER_HZ) | ||
| 8 | #endif | ||
| 9 | |||
| 10 | #ifndef HZ | ||
| 11 | #define HZ 100 | ||
| 12 | #endif | ||
| 13 | |||
| 14 | #define EXEC_PAGESIZE 4096 | ||
| 15 | |||
| 16 | #ifndef NOGROUP | ||
| 17 | #define NOGROUP (-1) | ||
| 18 | #endif | ||
| 19 | |||
| 20 | #define MAXHOSTNAMELEN 64 /* max length of hostname */ | ||
| 21 | |||
| 22 | #endif /* _M68KNOMMU_PARAM_H */ | ||
diff --git a/arch/m68k/include/asm/ptrace.h b/arch/m68k/include/asm/ptrace.h index e83cd2f66101..8c9194b98548 100644 --- a/arch/m68k/include/asm/ptrace.h +++ b/arch/m68k/include/asm/ptrace.h | |||
| @@ -1,5 +1,87 @@ | |||
| 1 | #ifdef __uClinux__ | 1 | #ifndef _M68K_PTRACE_H |
| 2 | #include "ptrace_no.h" | 2 | #define _M68K_PTRACE_H |
| 3 | |||
| 4 | #define PT_D1 0 | ||
| 5 | #define PT_D2 1 | ||
| 6 | #define PT_D3 2 | ||
| 7 | #define PT_D4 3 | ||
| 8 | #define PT_D5 4 | ||
| 9 | #define PT_D6 5 | ||
| 10 | #define PT_D7 6 | ||
| 11 | #define PT_A0 7 | ||
| 12 | #define PT_A1 8 | ||
| 13 | #define PT_A2 9 | ||
| 14 | #define PT_A3 10 | ||
| 15 | #define PT_A4 11 | ||
| 16 | #define PT_A5 12 | ||
| 17 | #define PT_A6 13 | ||
| 18 | #define PT_D0 14 | ||
| 19 | #define PT_USP 15 | ||
| 20 | #define PT_ORIG_D0 16 | ||
| 21 | #define PT_SR 17 | ||
| 22 | #define PT_PC 18 | ||
| 23 | |||
| 24 | #ifndef __ASSEMBLY__ | ||
| 25 | |||
| 26 | /* this struct defines the way the registers are stored on the | ||
| 27 | stack during a system call. */ | ||
| 28 | |||
| 29 | struct pt_regs { | ||
| 30 | long d1; | ||
| 31 | long d2; | ||
| 32 | long d3; | ||
| 33 | long d4; | ||
| 34 | long d5; | ||
| 35 | long a0; | ||
| 36 | long a1; | ||
| 37 | long a2; | ||
| 38 | long d0; | ||
| 39 | long orig_d0; | ||
| 40 | long stkadj; | ||
| 41 | #ifdef CONFIG_COLDFIRE | ||
| 42 | unsigned format : 4; /* frame format specifier */ | ||
| 43 | unsigned vector : 12; /* vector offset */ | ||
| 44 | unsigned short sr; | ||
| 45 | unsigned long pc; | ||
| 3 | #else | 46 | #else |
| 4 | #include "ptrace_mm.h" | 47 | unsigned short sr; |
| 48 | unsigned long pc; | ||
| 49 | unsigned format : 4; /* frame format specifier */ | ||
| 50 | unsigned vector : 12; /* vector offset */ | ||
| 5 | #endif | 51 | #endif |
| 52 | }; | ||
| 53 | |||
| 54 | /* | ||
| 55 | * This is the extended stack used by signal handlers and the context | ||
| 56 | * switcher: it's pushed after the normal "struct pt_regs". | ||
| 57 | */ | ||
| 58 | struct switch_stack { | ||
| 59 | unsigned long d6; | ||
| 60 | unsigned long d7; | ||
| 61 | unsigned long a3; | ||
| 62 | unsigned long a4; | ||
| 63 | unsigned long a5; | ||
| 64 | unsigned long a6; | ||
| 65 | unsigned long retpc; | ||
| 66 | }; | ||
| 67 | |||
| 68 | /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ | ||
| 69 | #define PTRACE_GETREGS 12 | ||
| 70 | #define PTRACE_SETREGS 13 | ||
| 71 | #define PTRACE_GETFPREGS 14 | ||
| 72 | #define PTRACE_SETFPREGS 15 | ||
| 73 | |||
| 74 | #ifdef __KERNEL__ | ||
| 75 | |||
| 76 | #ifndef PS_S | ||
| 77 | #define PS_S (0x2000) | ||
| 78 | #define PS_M (0x1000) | ||
| 79 | #endif | ||
| 80 | |||
| 81 | #define user_mode(regs) (!((regs)->sr & PS_S)) | ||
| 82 | #define instruction_pointer(regs) ((regs)->pc) | ||
| 83 | #define profile_pc(regs) instruction_pointer(regs) | ||
| 84 | extern void show_regs(struct pt_regs *); | ||
| 85 | #endif /* __KERNEL__ */ | ||
| 86 | #endif /* __ASSEMBLY__ */ | ||
| 87 | #endif /* _M68K_PTRACE_H */ | ||
diff --git a/arch/m68k/include/asm/ptrace_mm.h b/arch/m68k/include/asm/ptrace_mm.h deleted file mode 100644 index 57e763d79bf4..000000000000 --- a/arch/m68k/include/asm/ptrace_mm.h +++ /dev/null | |||
| @@ -1,80 +0,0 @@ | |||
| 1 | #ifndef _M68K_PTRACE_H | ||
| 2 | #define _M68K_PTRACE_H | ||
| 3 | |||
| 4 | #define PT_D1 0 | ||
| 5 | #define PT_D2 1 | ||
| 6 | #define PT_D3 2 | ||
| 7 | #define PT_D4 3 | ||
| 8 | #define PT_D5 4 | ||
| 9 | #define PT_D6 5 | ||
| 10 | #define PT_D7 6 | ||
| 11 | #define PT_A0 7 | ||
| 12 | #define PT_A1 8 | ||
| 13 | #define PT_A2 9 | ||
| 14 | #define PT_A3 10 | ||
| 15 | #define PT_A4 11 | ||
| 16 | #define PT_A5 12 | ||
| 17 | #define PT_A6 13 | ||
| 18 | #define PT_D0 14 | ||
| 19 | #define PT_USP 15 | ||
| 20 | #define PT_ORIG_D0 16 | ||
| 21 | #define PT_SR 17 | ||
| 22 | #define PT_PC 18 | ||
| 23 | |||
| 24 | #ifndef __ASSEMBLY__ | ||
| 25 | |||
| 26 | /* this struct defines the way the registers are stored on the | ||
| 27 | stack during a system call. */ | ||
| 28 | |||
| 29 | struct pt_regs { | ||
| 30 | long d1; | ||
| 31 | long d2; | ||
| 32 | long d3; | ||
| 33 | long d4; | ||
| 34 | long d5; | ||
| 35 | long a0; | ||
| 36 | long a1; | ||
| 37 | long a2; | ||
| 38 | long d0; | ||
| 39 | long orig_d0; | ||
| 40 | long stkadj; | ||
| 41 | unsigned short sr; | ||
| 42 | unsigned long pc; | ||
| 43 | unsigned format : 4; /* frame format specifier */ | ||
| 44 | unsigned vector : 12; /* vector offset */ | ||
| 45 | }; | ||
| 46 | |||
| 47 | /* | ||
| 48 | * This is the extended stack used by signal handlers and the context | ||
| 49 | * switcher: it's pushed after the normal "struct pt_regs". | ||
| 50 | */ | ||
| 51 | struct switch_stack { | ||
| 52 | unsigned long d6; | ||
| 53 | unsigned long d7; | ||
| 54 | unsigned long a3; | ||
| 55 | unsigned long a4; | ||
| 56 | unsigned long a5; | ||
| 57 | unsigned long a6; | ||
| 58 | unsigned long retpc; | ||
| 59 | }; | ||
| 60 | |||
| 61 | /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ | ||
| 62 | #define PTRACE_GETREGS 12 | ||
| 63 | #define PTRACE_SETREGS 13 | ||
| 64 | #define PTRACE_GETFPREGS 14 | ||
| 65 | #define PTRACE_SETFPREGS 15 | ||
| 66 | |||
| 67 | #ifdef __KERNEL__ | ||
| 68 | |||
| 69 | #ifndef PS_S | ||
| 70 | #define PS_S (0x2000) | ||
| 71 | #define PS_M (0x1000) | ||
| 72 | #endif | ||
| 73 | |||
| 74 | #define user_mode(regs) (!((regs)->sr & PS_S)) | ||
| 75 | #define instruction_pointer(regs) ((regs)->pc) | ||
| 76 | #define profile_pc(regs) instruction_pointer(regs) | ||
| 77 | extern void show_regs(struct pt_regs *); | ||
| 78 | #endif /* __KERNEL__ */ | ||
| 79 | #endif /* __ASSEMBLY__ */ | ||
| 80 | #endif /* _M68K_PTRACE_H */ | ||
diff --git a/arch/m68k/include/asm/ptrace_no.h b/arch/m68k/include/asm/ptrace_no.h deleted file mode 100644 index 8c9194b98548..000000000000 --- a/arch/m68k/include/asm/ptrace_no.h +++ /dev/null | |||
| @@ -1,87 +0,0 @@ | |||
| 1 | #ifndef _M68K_PTRACE_H | ||
| 2 | #define _M68K_PTRACE_H | ||
| 3 | |||
| 4 | #define PT_D1 0 | ||
| 5 | #define PT_D2 1 | ||
| 6 | #define PT_D3 2 | ||
| 7 | #define PT_D4 3 | ||
| 8 | #define PT_D5 4 | ||
| 9 | #define PT_D6 5 | ||
| 10 | #define PT_D7 6 | ||
| 11 | #define PT_A0 7 | ||
| 12 | #define PT_A1 8 | ||
| 13 | #define PT_A2 9 | ||
| 14 | #define PT_A3 10 | ||
| 15 | #define PT_A4 11 | ||
| 16 | #define PT_A5 12 | ||
| 17 | #define PT_A6 13 | ||
| 18 | #define PT_D0 14 | ||
| 19 | #define PT_USP 15 | ||
| 20 | #define PT_ORIG_D0 16 | ||
| 21 | #define PT_SR 17 | ||
| 22 | #define PT_PC 18 | ||
| 23 | |||
| 24 | #ifndef __ASSEMBLY__ | ||
| 25 | |||
| 26 | /* this struct defines the way the registers are stored on the | ||
| 27 | stack during a system call. */ | ||
| 28 | |||
| 29 | struct pt_regs { | ||
| 30 | long d1; | ||
| 31 | long d2; | ||
| 32 | long d3; | ||
| 33 | long d4; | ||
| 34 | long d5; | ||
| 35 | long a0; | ||
| 36 | long a1; | ||
| 37 | long a2; | ||
| 38 | long d0; | ||
| 39 | long orig_d0; | ||
| 40 | long stkadj; | ||
| 41 | #ifdef CONFIG_COLDFIRE | ||
| 42 | unsigned format : 4; /* frame format specifier */ | ||
| 43 | unsigned vector : 12; /* vector offset */ | ||
| 44 | unsigned short sr; | ||
| 45 | unsigned long pc; | ||
| 46 | #else | ||
| 47 | unsigned short sr; | ||
| 48 | unsigned long pc; | ||
| 49 | unsigned format : 4; /* frame format specifier */ | ||
| 50 | unsigned vector : 12; /* vector offset */ | ||
| 51 | #endif | ||
| 52 | }; | ||
| 53 | |||
| 54 | /* | ||
| 55 | * This is the extended stack used by signal handlers and the context | ||
| 56 | * switcher: it's pushed after the normal "struct pt_regs". | ||
| 57 | */ | ||
| 58 | struct switch_stack { | ||
| 59 | unsigned long d6; | ||
| 60 | unsigned long d7; | ||
| 61 | unsigned long a3; | ||
| 62 | unsigned long a4; | ||
| 63 | unsigned long a5; | ||
| 64 | unsigned long a6; | ||
| 65 | unsigned long retpc; | ||
| 66 | }; | ||
| 67 | |||
| 68 | /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ | ||
| 69 | #define PTRACE_GETREGS 12 | ||
| 70 | #define PTRACE_SETREGS 13 | ||
| 71 | #define PTRACE_GETFPREGS 14 | ||
| 72 | #define PTRACE_SETFPREGS 15 | ||
| 73 | |||
| 74 | #ifdef __KERNEL__ | ||
| 75 | |||
| 76 | #ifndef PS_S | ||
| 77 | #define PS_S (0x2000) | ||
| 78 | #define PS_M (0x1000) | ||
| 79 | #endif | ||
| 80 | |||
| 81 | #define user_mode(regs) (!((regs)->sr & PS_S)) | ||
| 82 | #define instruction_pointer(regs) ((regs)->pc) | ||
| 83 | #define profile_pc(regs) instruction_pointer(regs) | ||
| 84 | extern void show_regs(struct pt_regs *); | ||
| 85 | #endif /* __KERNEL__ */ | ||
| 86 | #endif /* __ASSEMBLY__ */ | ||
| 87 | #endif /* _M68K_PTRACE_H */ | ||
diff --git a/arch/m68k/include/asm/setup.h b/arch/m68k/include/asm/setup.h index 842f86f75ccd..4dfb3952b375 100644 --- a/arch/m68k/include/asm/setup.h +++ b/arch/m68k/include/asm/setup.h | |||
| @@ -1,5 +1,376 @@ | |||
| 1 | #ifdef __uClinux__ | 1 | /* |
| 2 | #include "setup_no.h" | 2 | ** asm/setup.h -- Definition of the Linux/m68k setup information |
| 3 | ** | ||
| 4 | ** Copyright 1992 by Greg Harp | ||
| 5 | ** | ||
| 6 | ** This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | ** License. See the file COPYING in the main directory of this archive | ||
| 8 | ** for more details. | ||
| 9 | ** | ||
| 10 | ** Created 09/29/92 by Greg Harp | ||
| 11 | ** | ||
| 12 | ** 5/2/94 Roman Hodek: | ||
| 13 | ** Added bi_atari part of the machine dependent union bi_un; for now it | ||
| 14 | ** contains just a model field to distinguish between TT and Falcon. | ||
| 15 | ** 26/7/96 Roman Zippel: | ||
| 16 | ** Renamed to setup.h; added some useful macros to allow gcc some | ||
| 17 | ** optimizations if possible. | ||
| 18 | ** 5/10/96 Geert Uytterhoeven: | ||
| 19 | ** Redesign of the boot information structure; moved boot information | ||
| 20 | ** structure to bootinfo.h | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef _M68K_SETUP_H | ||
| 24 | #define _M68K_SETUP_H | ||
| 25 | |||
| 26 | |||
| 27 | |||
| 28 | /* | ||
| 29 | * Linux/m68k Architectures | ||
| 30 | */ | ||
| 31 | |||
| 32 | #define MACH_AMIGA 1 | ||
| 33 | #define MACH_ATARI 2 | ||
| 34 | #define MACH_MAC 3 | ||
| 35 | #define MACH_APOLLO 4 | ||
| 36 | #define MACH_SUN3 5 | ||
| 37 | #define MACH_MVME147 6 | ||
| 38 | #define MACH_MVME16x 7 | ||
| 39 | #define MACH_BVME6000 8 | ||
| 40 | #define MACH_HP300 9 | ||
| 41 | #define MACH_Q40 10 | ||
| 42 | #define MACH_SUN3X 11 | ||
| 43 | |||
| 44 | #define COMMAND_LINE_SIZE 256 | ||
| 45 | |||
| 46 | #ifdef __KERNEL__ | ||
| 47 | |||
| 48 | #define CL_SIZE COMMAND_LINE_SIZE | ||
| 49 | |||
| 50 | #ifndef __ASSEMBLY__ | ||
| 51 | extern unsigned long m68k_machtype; | ||
| 52 | #endif /* !__ASSEMBLY__ */ | ||
| 53 | |||
| 54 | #if !defined(CONFIG_AMIGA) | ||
| 55 | # define MACH_IS_AMIGA (0) | ||
| 56 | #elif defined(CONFIG_ATARI) || defined(CONFIG_MAC) || defined(CONFIG_APOLLO) \ | ||
| 57 | || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ | ||
| 58 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 59 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 60 | # define MACH_IS_AMIGA (m68k_machtype == MACH_AMIGA) | ||
| 3 | #else | 61 | #else |
| 4 | #include "setup_mm.h" | 62 | # define MACH_AMIGA_ONLY |
| 63 | # define MACH_IS_AMIGA (1) | ||
| 64 | # define MACH_TYPE (MACH_AMIGA) | ||
| 5 | #endif | 65 | #endif |
| 66 | |||
| 67 | #if !defined(CONFIG_ATARI) | ||
| 68 | # define MACH_IS_ATARI (0) | ||
| 69 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_APOLLO) \ | ||
| 70 | || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ | ||
| 71 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 72 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 73 | # define MACH_IS_ATARI (m68k_machtype == MACH_ATARI) | ||
| 74 | #else | ||
| 75 | # define MACH_ATARI_ONLY | ||
| 76 | # define MACH_IS_ATARI (1) | ||
| 77 | # define MACH_TYPE (MACH_ATARI) | ||
| 78 | #endif | ||
| 79 | |||
| 80 | #if !defined(CONFIG_MAC) | ||
| 81 | # define MACH_IS_MAC (0) | ||
| 82 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_ATARI) || defined(CONFIG_APOLLO) \ | ||
| 83 | || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ | ||
| 84 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 85 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 86 | # define MACH_IS_MAC (m68k_machtype == MACH_MAC) | ||
| 87 | #else | ||
| 88 | # define MACH_MAC_ONLY | ||
| 89 | # define MACH_IS_MAC (1) | ||
| 90 | # define MACH_TYPE (MACH_MAC) | ||
| 91 | #endif | ||
| 92 | |||
| 93 | #if defined(CONFIG_SUN3) | ||
| 94 | #define MACH_IS_SUN3 (1) | ||
| 95 | #define MACH_SUN3_ONLY (1) | ||
| 96 | #define MACH_TYPE (MACH_SUN3) | ||
| 97 | #else | ||
| 98 | #define MACH_IS_SUN3 (0) | ||
| 99 | #endif | ||
| 100 | |||
| 101 | #if !defined (CONFIG_APOLLO) | ||
| 102 | # define MACH_IS_APOLLO (0) | ||
| 103 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 104 | || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ | ||
| 105 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 106 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 107 | # define MACH_IS_APOLLO (m68k_machtype == MACH_APOLLO) | ||
| 108 | #else | ||
| 109 | # define MACH_APOLLO_ONLY | ||
| 110 | # define MACH_IS_APOLLO (1) | ||
| 111 | # define MACH_TYPE (MACH_APOLLO) | ||
| 112 | #endif | ||
| 113 | |||
| 114 | #if !defined (CONFIG_MVME147) | ||
| 115 | # define MACH_IS_MVME147 (0) | ||
| 116 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 117 | || defined(CONFIG_APOLLO) || defined(CONFIG_BVME6000) \ | ||
| 118 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 119 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME16x) | ||
| 120 | # define MACH_IS_MVME147 (m68k_machtype == MACH_MVME147) | ||
| 121 | #else | ||
| 122 | # define MACH_MVME147_ONLY | ||
| 123 | # define MACH_IS_MVME147 (1) | ||
| 124 | # define MACH_TYPE (MACH_MVME147) | ||
| 125 | #endif | ||
| 126 | |||
| 127 | #if !defined (CONFIG_MVME16x) | ||
| 128 | # define MACH_IS_MVME16x (0) | ||
| 129 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 130 | || defined(CONFIG_APOLLO) || defined(CONFIG_BVME6000) \ | ||
| 131 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 132 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 133 | # define MACH_IS_MVME16x (m68k_machtype == MACH_MVME16x) | ||
| 134 | #else | ||
| 135 | # define MACH_MVME16x_ONLY | ||
| 136 | # define MACH_IS_MVME16x (1) | ||
| 137 | # define MACH_TYPE (MACH_MVME16x) | ||
| 138 | #endif | ||
| 139 | |||
| 140 | #if !defined (CONFIG_BVME6000) | ||
| 141 | # define MACH_IS_BVME6000 (0) | ||
| 142 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 143 | || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ | ||
| 144 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 145 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 146 | # define MACH_IS_BVME6000 (m68k_machtype == MACH_BVME6000) | ||
| 147 | #else | ||
| 148 | # define MACH_BVME6000_ONLY | ||
| 149 | # define MACH_IS_BVME6000 (1) | ||
| 150 | # define MACH_TYPE (MACH_BVME6000) | ||
| 151 | #endif | ||
| 152 | |||
| 153 | #if !defined (CONFIG_HP300) | ||
| 154 | # define MACH_IS_HP300 (0) | ||
| 155 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 156 | || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ | ||
| 157 | || defined(CONFIG_BVME6000) || defined(CONFIG_Q40) \ | ||
| 158 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 159 | # define MACH_IS_HP300 (m68k_machtype == MACH_HP300) | ||
| 160 | #else | ||
| 161 | # define MACH_HP300_ONLY | ||
| 162 | # define MACH_IS_HP300 (1) | ||
| 163 | # define MACH_TYPE (MACH_HP300) | ||
| 164 | #endif | ||
| 165 | |||
| 166 | #if !defined (CONFIG_Q40) | ||
| 167 | # define MACH_IS_Q40 (0) | ||
| 168 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 169 | || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ | ||
| 170 | || defined(CONFIG_BVME6000) || defined(CONFIG_HP300) \ | ||
| 171 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 172 | # define MACH_IS_Q40 (m68k_machtype == MACH_Q40) | ||
| 173 | #else | ||
| 174 | # define MACH_Q40_ONLY | ||
| 175 | # define MACH_IS_Q40 (1) | ||
| 176 | # define MACH_TYPE (MACH_Q40) | ||
| 177 | #endif | ||
| 178 | |||
| 179 | #if !defined (CONFIG_SUN3X) | ||
| 180 | # define MACH_IS_SUN3X (0) | ||
| 181 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 182 | || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ | ||
| 183 | || defined(CONFIG_BVME6000) || defined(CONFIG_HP300) \ | ||
| 184 | || defined(CONFIG_Q40) || defined(CONFIG_MVME147) | ||
| 185 | # define MACH_IS_SUN3X (m68k_machtype == MACH_SUN3X) | ||
| 186 | #else | ||
| 187 | # define CONFIG_SUN3X_ONLY | ||
| 188 | # define MACH_IS_SUN3X (1) | ||
| 189 | # define MACH_TYPE (MACH_SUN3X) | ||
| 190 | #endif | ||
| 191 | |||
| 192 | #ifndef MACH_TYPE | ||
| 193 | # define MACH_TYPE (m68k_machtype) | ||
| 194 | #endif | ||
| 195 | |||
| 196 | #endif /* __KERNEL__ */ | ||
| 197 | |||
| 198 | |||
| 199 | /* | ||
| 200 | * CPU, FPU and MMU types | ||
| 201 | * | ||
| 202 | * Note: we may rely on the following equalities: | ||
| 203 | * | ||
| 204 | * CPU_68020 == MMU_68851 | ||
| 205 | * CPU_68030 == MMU_68030 | ||
| 206 | * CPU_68040 == FPU_68040 == MMU_68040 | ||
| 207 | * CPU_68060 == FPU_68060 == MMU_68060 | ||
| 208 | */ | ||
| 209 | |||
| 210 | #define CPUB_68020 0 | ||
| 211 | #define CPUB_68030 1 | ||
| 212 | #define CPUB_68040 2 | ||
| 213 | #define CPUB_68060 3 | ||
| 214 | |||
| 215 | #define CPU_68020 (1<<CPUB_68020) | ||
| 216 | #define CPU_68030 (1<<CPUB_68030) | ||
| 217 | #define CPU_68040 (1<<CPUB_68040) | ||
| 218 | #define CPU_68060 (1<<CPUB_68060) | ||
| 219 | |||
| 220 | #define FPUB_68881 0 | ||
| 221 | #define FPUB_68882 1 | ||
| 222 | #define FPUB_68040 2 /* Internal FPU */ | ||
| 223 | #define FPUB_68060 3 /* Internal FPU */ | ||
| 224 | #define FPUB_SUNFPA 4 /* Sun-3 FPA */ | ||
| 225 | |||
| 226 | #define FPU_68881 (1<<FPUB_68881) | ||
| 227 | #define FPU_68882 (1<<FPUB_68882) | ||
| 228 | #define FPU_68040 (1<<FPUB_68040) | ||
| 229 | #define FPU_68060 (1<<FPUB_68060) | ||
| 230 | #define FPU_SUNFPA (1<<FPUB_SUNFPA) | ||
| 231 | |||
| 232 | #define MMUB_68851 0 | ||
| 233 | #define MMUB_68030 1 /* Internal MMU */ | ||
| 234 | #define MMUB_68040 2 /* Internal MMU */ | ||
| 235 | #define MMUB_68060 3 /* Internal MMU */ | ||
| 236 | #define MMUB_APOLLO 4 /* Custom Apollo */ | ||
| 237 | #define MMUB_SUN3 5 /* Custom Sun-3 */ | ||
| 238 | |||
| 239 | #define MMU_68851 (1<<MMUB_68851) | ||
| 240 | #define MMU_68030 (1<<MMUB_68030) | ||
| 241 | #define MMU_68040 (1<<MMUB_68040) | ||
| 242 | #define MMU_68060 (1<<MMUB_68060) | ||
| 243 | #define MMU_SUN3 (1<<MMUB_SUN3) | ||
| 244 | #define MMU_APOLLO (1<<MMUB_APOLLO) | ||
| 245 | |||
| 246 | #ifdef __KERNEL__ | ||
| 247 | |||
| 248 | #ifndef __ASSEMBLY__ | ||
| 249 | extern unsigned long m68k_cputype; | ||
| 250 | extern unsigned long m68k_fputype; | ||
| 251 | extern unsigned long m68k_mmutype; | ||
| 252 | #ifdef CONFIG_VME | ||
| 253 | extern unsigned long vme_brdtype; | ||
| 254 | #endif | ||
| 255 | |||
| 256 | /* | ||
| 257 | * m68k_is040or060 is != 0 for a '040 or higher; | ||
| 258 | * used numbers are 4 for 68040 and 6 for 68060. | ||
| 259 | */ | ||
| 260 | |||
| 261 | extern int m68k_is040or060; | ||
| 262 | #endif /* !__ASSEMBLY__ */ | ||
| 263 | |||
| 264 | #if !defined(CONFIG_M68020) | ||
| 265 | # define CPU_IS_020 (0) | ||
| 266 | # define MMU_IS_851 (0) | ||
| 267 | # define MMU_IS_SUN3 (0) | ||
| 268 | #elif defined(CONFIG_M68030) || defined(CONFIG_M68040) || defined(CONFIG_M68060) | ||
| 269 | # define CPU_IS_020 (m68k_cputype & CPU_68020) | ||
| 270 | # define MMU_IS_851 (m68k_mmutype & MMU_68851) | ||
| 271 | # define MMU_IS_SUN3 (0) /* Sun3 not supported with other CPU enabled */ | ||
| 272 | #else | ||
| 273 | # define CPU_M68020_ONLY | ||
| 274 | # define CPU_IS_020 (1) | ||
| 275 | #ifdef MACH_SUN3_ONLY | ||
| 276 | # define MMU_IS_SUN3 (1) | ||
| 277 | # define MMU_IS_851 (0) | ||
| 278 | #else | ||
| 279 | # define MMU_IS_SUN3 (0) | ||
| 280 | # define MMU_IS_851 (1) | ||
| 281 | #endif | ||
| 282 | #endif | ||
| 283 | |||
| 284 | #if !defined(CONFIG_M68030) | ||
| 285 | # define CPU_IS_030 (0) | ||
| 286 | # define MMU_IS_030 (0) | ||
| 287 | #elif defined(CONFIG_M68020) || defined(CONFIG_M68040) || defined(CONFIG_M68060) | ||
| 288 | # define CPU_IS_030 (m68k_cputype & CPU_68030) | ||
| 289 | # define MMU_IS_030 (m68k_mmutype & MMU_68030) | ||
| 290 | #else | ||
| 291 | # define CPU_M68030_ONLY | ||
| 292 | # define CPU_IS_030 (1) | ||
| 293 | # define MMU_IS_030 (1) | ||
| 294 | #endif | ||
| 295 | |||
| 296 | #if !defined(CONFIG_M68040) | ||
| 297 | # define CPU_IS_040 (0) | ||
| 298 | # define MMU_IS_040 (0) | ||
| 299 | #elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68060) | ||
| 300 | # define CPU_IS_040 (m68k_cputype & CPU_68040) | ||
| 301 | # define MMU_IS_040 (m68k_mmutype & MMU_68040) | ||
| 302 | #else | ||
| 303 | # define CPU_M68040_ONLY | ||
| 304 | # define CPU_IS_040 (1) | ||
| 305 | # define MMU_IS_040 (1) | ||
| 306 | #endif | ||
| 307 | |||
| 308 | #if !defined(CONFIG_M68060) | ||
| 309 | # define CPU_IS_060 (0) | ||
| 310 | # define MMU_IS_060 (0) | ||
| 311 | #elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68040) | ||
| 312 | # define CPU_IS_060 (m68k_cputype & CPU_68060) | ||
| 313 | # define MMU_IS_060 (m68k_mmutype & MMU_68060) | ||
| 314 | #else | ||
| 315 | # define CPU_M68060_ONLY | ||
| 316 | # define CPU_IS_060 (1) | ||
| 317 | # define MMU_IS_060 (1) | ||
| 318 | #endif | ||
| 319 | |||
| 320 | #if !defined(CONFIG_M68020) && !defined(CONFIG_M68030) | ||
| 321 | # define CPU_IS_020_OR_030 (0) | ||
| 322 | #else | ||
| 323 | # define CPU_M68020_OR_M68030 | ||
| 324 | # if defined(CONFIG_M68040) || defined(CONFIG_M68060) | ||
| 325 | # define CPU_IS_020_OR_030 (!m68k_is040or060) | ||
| 326 | # else | ||
| 327 | # define CPU_M68020_OR_M68030_ONLY | ||
| 328 | # define CPU_IS_020_OR_030 (1) | ||
| 329 | # endif | ||
| 330 | #endif | ||
| 331 | |||
| 332 | #if !defined(CONFIG_M68040) && !defined(CONFIG_M68060) | ||
| 333 | # define CPU_IS_040_OR_060 (0) | ||
| 334 | #else | ||
| 335 | # define CPU_M68040_OR_M68060 | ||
| 336 | # if defined(CONFIG_M68020) || defined(CONFIG_M68030) | ||
| 337 | # define CPU_IS_040_OR_060 (m68k_is040or060) | ||
| 338 | # else | ||
| 339 | # define CPU_M68040_OR_M68060_ONLY | ||
| 340 | # define CPU_IS_040_OR_060 (1) | ||
| 341 | # endif | ||
| 342 | #endif | ||
| 343 | |||
| 344 | #define CPU_TYPE (m68k_cputype) | ||
| 345 | |||
| 346 | #ifdef CONFIG_M68KFPU_EMU | ||
| 347 | # ifdef CONFIG_M68KFPU_EMU_ONLY | ||
| 348 | # define FPU_IS_EMU (1) | ||
| 349 | # else | ||
| 350 | # define FPU_IS_EMU (!m68k_fputype) | ||
| 351 | # endif | ||
| 352 | #else | ||
| 353 | # define FPU_IS_EMU (0) | ||
| 354 | #endif | ||
| 355 | |||
| 356 | |||
| 357 | /* | ||
| 358 | * Miscellaneous | ||
| 359 | */ | ||
| 360 | |||
| 361 | #define NUM_MEMINFO 4 | ||
| 362 | |||
| 363 | #ifndef __ASSEMBLY__ | ||
| 364 | struct mem_info { | ||
| 365 | unsigned long addr; /* physical address of memory chunk */ | ||
| 366 | unsigned long size; /* length of memory chunk (in bytes) */ | ||
| 367 | }; | ||
| 368 | |||
| 369 | extern int m68k_num_memory; /* # of memory blocks found (and used) */ | ||
| 370 | extern int m68k_realnum_memory; /* real # of memory blocks found */ | ||
| 371 | extern struct mem_info m68k_memory[NUM_MEMINFO];/* memory description */ | ||
| 372 | #endif | ||
| 373 | |||
| 374 | #endif /* __KERNEL__ */ | ||
| 375 | |||
| 376 | #endif /* _M68K_SETUP_H */ | ||
diff --git a/arch/m68k/include/asm/setup_mm.h b/arch/m68k/include/asm/setup_mm.h deleted file mode 100644 index 4dfb3952b375..000000000000 --- a/arch/m68k/include/asm/setup_mm.h +++ /dev/null | |||
| @@ -1,376 +0,0 @@ | |||
| 1 | /* | ||
| 2 | ** asm/setup.h -- Definition of the Linux/m68k setup information | ||
| 3 | ** | ||
| 4 | ** Copyright 1992 by Greg Harp | ||
| 5 | ** | ||
| 6 | ** This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | ** License. See the file COPYING in the main directory of this archive | ||
| 8 | ** for more details. | ||
| 9 | ** | ||
| 10 | ** Created 09/29/92 by Greg Harp | ||
| 11 | ** | ||
| 12 | ** 5/2/94 Roman Hodek: | ||
| 13 | ** Added bi_atari part of the machine dependent union bi_un; for now it | ||
| 14 | ** contains just a model field to distinguish between TT and Falcon. | ||
| 15 | ** 26/7/96 Roman Zippel: | ||
| 16 | ** Renamed to setup.h; added some useful macros to allow gcc some | ||
| 17 | ** optimizations if possible. | ||
| 18 | ** 5/10/96 Geert Uytterhoeven: | ||
| 19 | ** Redesign of the boot information structure; moved boot information | ||
| 20 | ** structure to bootinfo.h | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef _M68K_SETUP_H | ||
| 24 | #define _M68K_SETUP_H | ||
| 25 | |||
| 26 | |||
| 27 | |||
| 28 | /* | ||
| 29 | * Linux/m68k Architectures | ||
| 30 | */ | ||
| 31 | |||
| 32 | #define MACH_AMIGA 1 | ||
| 33 | #define MACH_ATARI 2 | ||
| 34 | #define MACH_MAC 3 | ||
| 35 | #define MACH_APOLLO 4 | ||
| 36 | #define MACH_SUN3 5 | ||
| 37 | #define MACH_MVME147 6 | ||
| 38 | #define MACH_MVME16x 7 | ||
| 39 | #define MACH_BVME6000 8 | ||
| 40 | #define MACH_HP300 9 | ||
| 41 | #define MACH_Q40 10 | ||
| 42 | #define MACH_SUN3X 11 | ||
| 43 | |||
| 44 | #define COMMAND_LINE_SIZE 256 | ||
| 45 | |||
| 46 | #ifdef __KERNEL__ | ||
| 47 | |||
| 48 | #define CL_SIZE COMMAND_LINE_SIZE | ||
| 49 | |||
| 50 | #ifndef __ASSEMBLY__ | ||
| 51 | extern unsigned long m68k_machtype; | ||
| 52 | #endif /* !__ASSEMBLY__ */ | ||
| 53 | |||
| 54 | #if !defined(CONFIG_AMIGA) | ||
| 55 | # define MACH_IS_AMIGA (0) | ||
| 56 | #elif defined(CONFIG_ATARI) || defined(CONFIG_MAC) || defined(CONFIG_APOLLO) \ | ||
| 57 | || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ | ||
| 58 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 59 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 60 | # define MACH_IS_AMIGA (m68k_machtype == MACH_AMIGA) | ||
| 61 | #else | ||
| 62 | # define MACH_AMIGA_ONLY | ||
| 63 | # define MACH_IS_AMIGA (1) | ||
| 64 | # define MACH_TYPE (MACH_AMIGA) | ||
| 65 | #endif | ||
| 66 | |||
| 67 | #if !defined(CONFIG_ATARI) | ||
| 68 | # define MACH_IS_ATARI (0) | ||
| 69 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_APOLLO) \ | ||
| 70 | || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ | ||
| 71 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 72 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 73 | # define MACH_IS_ATARI (m68k_machtype == MACH_ATARI) | ||
| 74 | #else | ||
| 75 | # define MACH_ATARI_ONLY | ||
| 76 | # define MACH_IS_ATARI (1) | ||
| 77 | # define MACH_TYPE (MACH_ATARI) | ||
| 78 | #endif | ||
| 79 | |||
| 80 | #if !defined(CONFIG_MAC) | ||
| 81 | # define MACH_IS_MAC (0) | ||
| 82 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_ATARI) || defined(CONFIG_APOLLO) \ | ||
| 83 | || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ | ||
| 84 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 85 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 86 | # define MACH_IS_MAC (m68k_machtype == MACH_MAC) | ||
| 87 | #else | ||
| 88 | # define MACH_MAC_ONLY | ||
| 89 | # define MACH_IS_MAC (1) | ||
| 90 | # define MACH_TYPE (MACH_MAC) | ||
| 91 | #endif | ||
| 92 | |||
| 93 | #if defined(CONFIG_SUN3) | ||
| 94 | #define MACH_IS_SUN3 (1) | ||
| 95 | #define MACH_SUN3_ONLY (1) | ||
| 96 | #define MACH_TYPE (MACH_SUN3) | ||
| 97 | #else | ||
| 98 | #define MACH_IS_SUN3 (0) | ||
| 99 | #endif | ||
| 100 | |||
| 101 | #if !defined (CONFIG_APOLLO) | ||
| 102 | # define MACH_IS_APOLLO (0) | ||
| 103 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 104 | || defined(CONFIG_MVME16x) || defined(CONFIG_BVME6000) \ | ||
| 105 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 106 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 107 | # define MACH_IS_APOLLO (m68k_machtype == MACH_APOLLO) | ||
| 108 | #else | ||
| 109 | # define MACH_APOLLO_ONLY | ||
| 110 | # define MACH_IS_APOLLO (1) | ||
| 111 | # define MACH_TYPE (MACH_APOLLO) | ||
| 112 | #endif | ||
| 113 | |||
| 114 | #if !defined (CONFIG_MVME147) | ||
| 115 | # define MACH_IS_MVME147 (0) | ||
| 116 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 117 | || defined(CONFIG_APOLLO) || defined(CONFIG_BVME6000) \ | ||
| 118 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 119 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME16x) | ||
| 120 | # define MACH_IS_MVME147 (m68k_machtype == MACH_MVME147) | ||
| 121 | #else | ||
| 122 | # define MACH_MVME147_ONLY | ||
| 123 | # define MACH_IS_MVME147 (1) | ||
| 124 | # define MACH_TYPE (MACH_MVME147) | ||
| 125 | #endif | ||
| 126 | |||
| 127 | #if !defined (CONFIG_MVME16x) | ||
| 128 | # define MACH_IS_MVME16x (0) | ||
| 129 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 130 | || defined(CONFIG_APOLLO) || defined(CONFIG_BVME6000) \ | ||
| 131 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 132 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 133 | # define MACH_IS_MVME16x (m68k_machtype == MACH_MVME16x) | ||
| 134 | #else | ||
| 135 | # define MACH_MVME16x_ONLY | ||
| 136 | # define MACH_IS_MVME16x (1) | ||
| 137 | # define MACH_TYPE (MACH_MVME16x) | ||
| 138 | #endif | ||
| 139 | |||
| 140 | #if !defined (CONFIG_BVME6000) | ||
| 141 | # define MACH_IS_BVME6000 (0) | ||
| 142 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 143 | || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ | ||
| 144 | || defined(CONFIG_HP300) || defined(CONFIG_Q40) \ | ||
| 145 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 146 | # define MACH_IS_BVME6000 (m68k_machtype == MACH_BVME6000) | ||
| 147 | #else | ||
| 148 | # define MACH_BVME6000_ONLY | ||
| 149 | # define MACH_IS_BVME6000 (1) | ||
| 150 | # define MACH_TYPE (MACH_BVME6000) | ||
| 151 | #endif | ||
| 152 | |||
| 153 | #if !defined (CONFIG_HP300) | ||
| 154 | # define MACH_IS_HP300 (0) | ||
| 155 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 156 | || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ | ||
| 157 | || defined(CONFIG_BVME6000) || defined(CONFIG_Q40) \ | ||
| 158 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 159 | # define MACH_IS_HP300 (m68k_machtype == MACH_HP300) | ||
| 160 | #else | ||
| 161 | # define MACH_HP300_ONLY | ||
| 162 | # define MACH_IS_HP300 (1) | ||
| 163 | # define MACH_TYPE (MACH_HP300) | ||
| 164 | #endif | ||
| 165 | |||
| 166 | #if !defined (CONFIG_Q40) | ||
| 167 | # define MACH_IS_Q40 (0) | ||
| 168 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 169 | || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ | ||
| 170 | || defined(CONFIG_BVME6000) || defined(CONFIG_HP300) \ | ||
| 171 | || defined(CONFIG_SUN3X) || defined(CONFIG_MVME147) | ||
| 172 | # define MACH_IS_Q40 (m68k_machtype == MACH_Q40) | ||
| 173 | #else | ||
| 174 | # define MACH_Q40_ONLY | ||
| 175 | # define MACH_IS_Q40 (1) | ||
| 176 | # define MACH_TYPE (MACH_Q40) | ||
| 177 | #endif | ||
| 178 | |||
| 179 | #if !defined (CONFIG_SUN3X) | ||
| 180 | # define MACH_IS_SUN3X (0) | ||
| 181 | #elif defined(CONFIG_AMIGA) || defined(CONFIG_MAC) || defined(CONFIG_ATARI) \ | ||
| 182 | || defined(CONFIG_APOLLO) || defined(CONFIG_MVME16x) \ | ||
| 183 | || defined(CONFIG_BVME6000) || defined(CONFIG_HP300) \ | ||
| 184 | || defined(CONFIG_Q40) || defined(CONFIG_MVME147) | ||
| 185 | # define MACH_IS_SUN3X (m68k_machtype == MACH_SUN3X) | ||
| 186 | #else | ||
| 187 | # define CONFIG_SUN3X_ONLY | ||
| 188 | # define MACH_IS_SUN3X (1) | ||
| 189 | # define MACH_TYPE (MACH_SUN3X) | ||
| 190 | #endif | ||
| 191 | |||
| 192 | #ifndef MACH_TYPE | ||
| 193 | # define MACH_TYPE (m68k_machtype) | ||
| 194 | #endif | ||
| 195 | |||
| 196 | #endif /* __KERNEL__ */ | ||
| 197 | |||
| 198 | |||
| 199 | /* | ||
| 200 | * CPU, FPU and MMU types | ||
| 201 | * | ||
| 202 | * Note: we may rely on the following equalities: | ||
| 203 | * | ||
| 204 | * CPU_68020 == MMU_68851 | ||
| 205 | * CPU_68030 == MMU_68030 | ||
| 206 | * CPU_68040 == FPU_68040 == MMU_68040 | ||
| 207 | * CPU_68060 == FPU_68060 == MMU_68060 | ||
| 208 | */ | ||
| 209 | |||
| 210 | #define CPUB_68020 0 | ||
| 211 | #define CPUB_68030 1 | ||
| 212 | #define CPUB_68040 2 | ||
| 213 | #define CPUB_68060 3 | ||
| 214 | |||
| 215 | #define CPU_68020 (1<<CPUB_68020) | ||
| 216 | #define CPU_68030 (1<<CPUB_68030) | ||
| 217 | #define CPU_68040 (1<<CPUB_68040) | ||
| 218 | #define CPU_68060 (1<<CPUB_68060) | ||
| 219 | |||
| 220 | #define FPUB_68881 0 | ||
| 221 | #define FPUB_68882 1 | ||
| 222 | #define FPUB_68040 2 /* Internal FPU */ | ||
| 223 | #define FPUB_68060 3 /* Internal FPU */ | ||
| 224 | #define FPUB_SUNFPA 4 /* Sun-3 FPA */ | ||
| 225 | |||
| 226 | #define FPU_68881 (1<<FPUB_68881) | ||
| 227 | #define FPU_68882 (1<<FPUB_68882) | ||
| 228 | #define FPU_68040 (1<<FPUB_68040) | ||
| 229 | #define FPU_68060 (1<<FPUB_68060) | ||
| 230 | #define FPU_SUNFPA (1<<FPUB_SUNFPA) | ||
| 231 | |||
| 232 | #define MMUB_68851 0 | ||
| 233 | #define MMUB_68030 1 /* Internal MMU */ | ||
| 234 | #define MMUB_68040 2 /* Internal MMU */ | ||
| 235 | #define MMUB_68060 3 /* Internal MMU */ | ||
| 236 | #define MMUB_APOLLO 4 /* Custom Apollo */ | ||
| 237 | #define MMUB_SUN3 5 /* Custom Sun-3 */ | ||
| 238 | |||
| 239 | #define MMU_68851 (1<<MMUB_68851) | ||
| 240 | #define MMU_68030 (1<<MMUB_68030) | ||
| 241 | #define MMU_68040 (1<<MMUB_68040) | ||
| 242 | #define MMU_68060 (1<<MMUB_68060) | ||
| 243 | #define MMU_SUN3 (1<<MMUB_SUN3) | ||
| 244 | #define MMU_APOLLO (1<<MMUB_APOLLO) | ||
| 245 | |||
| 246 | #ifdef __KERNEL__ | ||
| 247 | |||
| 248 | #ifndef __ASSEMBLY__ | ||
| 249 | extern unsigned long m68k_cputype; | ||
| 250 | extern unsigned long m68k_fputype; | ||
| 251 | extern unsigned long m68k_mmutype; | ||
| 252 | #ifdef CONFIG_VME | ||
| 253 | extern unsigned long vme_brdtype; | ||
| 254 | #endif | ||
| 255 | |||
| 256 | /* | ||
| 257 | * m68k_is040or060 is != 0 for a '040 or higher; | ||
| 258 | * used numbers are 4 for 68040 and 6 for 68060. | ||
| 259 | */ | ||
| 260 | |||
| 261 | extern int m68k_is040or060; | ||
| 262 | #endif /* !__ASSEMBLY__ */ | ||
| 263 | |||
| 264 | #if !defined(CONFIG_M68020) | ||
| 265 | # define CPU_IS_020 (0) | ||
| 266 | # define MMU_IS_851 (0) | ||
| 267 | # define MMU_IS_SUN3 (0) | ||
| 268 | #elif defined(CONFIG_M68030) || defined(CONFIG_M68040) || defined(CONFIG_M68060) | ||
| 269 | # define CPU_IS_020 (m68k_cputype & CPU_68020) | ||
| 270 | # define MMU_IS_851 (m68k_mmutype & MMU_68851) | ||
| 271 | # define MMU_IS_SUN3 (0) /* Sun3 not supported with other CPU enabled */ | ||
| 272 | #else | ||
| 273 | # define CPU_M68020_ONLY | ||
| 274 | # define CPU_IS_020 (1) | ||
| 275 | #ifdef MACH_SUN3_ONLY | ||
| 276 | # define MMU_IS_SUN3 (1) | ||
| 277 | # define MMU_IS_851 (0) | ||
| 278 | #else | ||
| 279 | # define MMU_IS_SUN3 (0) | ||
| 280 | # define MMU_IS_851 (1) | ||
| 281 | #endif | ||
| 282 | #endif | ||
| 283 | |||
| 284 | #if !defined(CONFIG_M68030) | ||
| 285 | # define CPU_IS_030 (0) | ||
| 286 | # define MMU_IS_030 (0) | ||
| 287 | #elif defined(CONFIG_M68020) || defined(CONFIG_M68040) || defined(CONFIG_M68060) | ||
| 288 | # define CPU_IS_030 (m68k_cputype & CPU_68030) | ||
| 289 | # define MMU_IS_030 (m68k_mmutype & MMU_68030) | ||
| 290 | #else | ||
| 291 | # define CPU_M68030_ONLY | ||
| 292 | # define CPU_IS_030 (1) | ||
| 293 | # define MMU_IS_030 (1) | ||
| 294 | #endif | ||
| 295 | |||
| 296 | #if !defined(CONFIG_M68040) | ||
| 297 | # define CPU_IS_040 (0) | ||
| 298 | # define MMU_IS_040 (0) | ||
| 299 | #elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68060) | ||
| 300 | # define CPU_IS_040 (m68k_cputype & CPU_68040) | ||
| 301 | # define MMU_IS_040 (m68k_mmutype & MMU_68040) | ||
| 302 | #else | ||
| 303 | # define CPU_M68040_ONLY | ||
| 304 | # define CPU_IS_040 (1) | ||
| 305 | # define MMU_IS_040 (1) | ||
| 306 | #endif | ||
| 307 | |||
| 308 | #if !defined(CONFIG_M68060) | ||
| 309 | # define CPU_IS_060 (0) | ||
| 310 | # define MMU_IS_060 (0) | ||
| 311 | #elif defined(CONFIG_M68020) || defined(CONFIG_M68030) || defined(CONFIG_M68040) | ||
| 312 | # define CPU_IS_060 (m68k_cputype & CPU_68060) | ||
| 313 | # define MMU_IS_060 (m68k_mmutype & MMU_68060) | ||
| 314 | #else | ||
| 315 | # define CPU_M68060_ONLY | ||
| 316 | # define CPU_IS_060 (1) | ||
| 317 | # define MMU_IS_060 (1) | ||
| 318 | #endif | ||
| 319 | |||
| 320 | #if !defined(CONFIG_M68020) && !defined(CONFIG_M68030) | ||
| 321 | # define CPU_IS_020_OR_030 (0) | ||
| 322 | #else | ||
| 323 | # define CPU_M68020_OR_M68030 | ||
| 324 | # if defined(CONFIG_M68040) || defined(CONFIG_M68060) | ||
| 325 | # define CPU_IS_020_OR_030 (!m68k_is040or060) | ||
| 326 | # else | ||
| 327 | # define CPU_M68020_OR_M68030_ONLY | ||
| 328 | # define CPU_IS_020_OR_030 (1) | ||
| 329 | # endif | ||
| 330 | #endif | ||
| 331 | |||
| 332 | #if !defined(CONFIG_M68040) && !defined(CONFIG_M68060) | ||
| 333 | # define CPU_IS_040_OR_060 (0) | ||
| 334 | #else | ||
| 335 | # define CPU_M68040_OR_M68060 | ||
| 336 | # if defined(CONFIG_M68020) || defined(CONFIG_M68030) | ||
| 337 | # define CPU_IS_040_OR_060 (m68k_is040or060) | ||
| 338 | # else | ||
| 339 | # define CPU_M68040_OR_M68060_ONLY | ||
| 340 | # define CPU_IS_040_OR_060 (1) | ||
| 341 | # endif | ||
| 342 | #endif | ||
| 343 | |||
| 344 | #define CPU_TYPE (m68k_cputype) | ||
| 345 | |||
| 346 | #ifdef CONFIG_M68KFPU_EMU | ||
| 347 | # ifdef CONFIG_M68KFPU_EMU_ONLY | ||
| 348 | # define FPU_IS_EMU (1) | ||
| 349 | # else | ||
| 350 | # define FPU_IS_EMU (!m68k_fputype) | ||
| 351 | # endif | ||
| 352 | #else | ||
| 353 | # define FPU_IS_EMU (0) | ||
| 354 | #endif | ||
| 355 | |||
| 356 | |||
| 357 | /* | ||
| 358 | * Miscellaneous | ||
| 359 | */ | ||
| 360 | |||
| 361 | #define NUM_MEMINFO 4 | ||
| 362 | |||
| 363 | #ifndef __ASSEMBLY__ | ||
| 364 | struct mem_info { | ||
| 365 | unsigned long addr; /* physical address of memory chunk */ | ||
| 366 | unsigned long size; /* length of memory chunk (in bytes) */ | ||
| 367 | }; | ||
| 368 | |||
| 369 | extern int m68k_num_memory; /* # of memory blocks found (and used) */ | ||
| 370 | extern int m68k_realnum_memory; /* real # of memory blocks found */ | ||
| 371 | extern struct mem_info m68k_memory[NUM_MEMINFO];/* memory description */ | ||
| 372 | #endif | ||
| 373 | |||
| 374 | #endif /* __KERNEL__ */ | ||
| 375 | |||
| 376 | #endif /* _M68K_SETUP_H */ | ||
diff --git a/arch/m68k/include/asm/setup_no.h b/arch/m68k/include/asm/setup_no.h deleted file mode 100644 index 45d286ce9398..000000000000 --- a/arch/m68k/include/asm/setup_no.h +++ /dev/null | |||
| @@ -1,10 +0,0 @@ | |||
| 1 | #ifdef __KERNEL__ | ||
| 2 | |||
| 3 | #include <asm/setup_mm.h> | ||
| 4 | |||
| 5 | /* We have a bigger command line buffer. */ | ||
| 6 | #undef COMMAND_LINE_SIZE | ||
| 7 | |||
| 8 | #endif /* __KERNEL__ */ | ||
| 9 | |||
| 10 | #define COMMAND_LINE_SIZE 512 | ||
diff --git a/arch/m68k/include/asm/sigcontext.h b/arch/m68k/include/asm/sigcontext.h index bff6d40345a9..523db2a51cf3 100644 --- a/arch/m68k/include/asm/sigcontext.h +++ b/arch/m68k/include/asm/sigcontext.h | |||
| @@ -1,5 +1,24 @@ | |||
| 1 | #ifndef _ASM_M68k_SIGCONTEXT_H | ||
| 2 | #define _ASM_M68k_SIGCONTEXT_H | ||
| 3 | |||
| 4 | struct sigcontext { | ||
| 5 | unsigned long sc_mask; /* old sigmask */ | ||
| 6 | unsigned long sc_usp; /* old user stack pointer */ | ||
| 7 | unsigned long sc_d0; | ||
| 8 | unsigned long sc_d1; | ||
| 9 | unsigned long sc_a0; | ||
| 10 | unsigned long sc_a1; | ||
| 1 | #ifdef __uClinux__ | 11 | #ifdef __uClinux__ |
| 2 | #include "sigcontext_no.h" | 12 | unsigned long sc_a5; |
| 3 | #else | 13 | #endif |
| 4 | #include "sigcontext_mm.h" | 14 | unsigned short sc_sr; |
| 15 | unsigned long sc_pc; | ||
| 16 | unsigned short sc_formatvec; | ||
| 17 | #ifndef __uClinux__ | ||
| 18 | unsigned long sc_fpregs[2*3]; /* room for two fp registers */ | ||
| 19 | unsigned long sc_fpcntl[3]; | ||
| 20 | unsigned char sc_fpstate[216]; | ||
| 21 | #endif | ||
| 22 | }; | ||
| 23 | |||
| 5 | #endif | 24 | #endif |
diff --git a/arch/m68k/include/asm/sigcontext_mm.h b/arch/m68k/include/asm/sigcontext_mm.h deleted file mode 100644 index 64fbe34cf26f..000000000000 --- a/arch/m68k/include/asm/sigcontext_mm.h +++ /dev/null | |||
| @@ -1,19 +0,0 @@ | |||
| 1 | #ifndef _ASM_M68k_SIGCONTEXT_H | ||
| 2 | #define _ASM_M68k_SIGCONTEXT_H | ||
| 3 | |||
| 4 | struct sigcontext { | ||
| 5 | unsigned long sc_mask; /* old sigmask */ | ||
| 6 | unsigned long sc_usp; /* old user stack pointer */ | ||
| 7 | unsigned long sc_d0; | ||
| 8 | unsigned long sc_d1; | ||
| 9 | unsigned long sc_a0; | ||
| 10 | unsigned long sc_a1; | ||
| 11 | unsigned short sc_sr; | ||
| 12 | unsigned long sc_pc; | ||
| 13 | unsigned short sc_formatvec; | ||
| 14 | unsigned long sc_fpregs[2*3]; /* room for two fp registers */ | ||
| 15 | unsigned long sc_fpcntl[3]; | ||
| 16 | unsigned char sc_fpstate[216]; | ||
| 17 | }; | ||
| 18 | |||
| 19 | #endif | ||
diff --git a/arch/m68k/include/asm/sigcontext_no.h b/arch/m68k/include/asm/sigcontext_no.h deleted file mode 100644 index 36c293fc133d..000000000000 --- a/arch/m68k/include/asm/sigcontext_no.h +++ /dev/null | |||
| @@ -1,17 +0,0 @@ | |||
| 1 | #ifndef _ASM_M68KNOMMU_SIGCONTEXT_H | ||
| 2 | #define _ASM_M68KNOMMU_SIGCONTEXT_H | ||
| 3 | |||
| 4 | struct sigcontext { | ||
| 5 | unsigned long sc_mask; /* old sigmask */ | ||
| 6 | unsigned long sc_usp; /* old user stack pointer */ | ||
| 7 | unsigned long sc_d0; | ||
| 8 | unsigned long sc_d1; | ||
| 9 | unsigned long sc_a0; | ||
| 10 | unsigned long sc_a1; | ||
| 11 | unsigned long sc_a5; | ||
| 12 | unsigned short sc_sr; | ||
| 13 | unsigned long sc_pc; | ||
| 14 | unsigned short sc_formatvec; | ||
| 15 | }; | ||
| 16 | |||
| 17 | #endif | ||
diff --git a/arch/m68k/include/asm/siginfo.h b/arch/m68k/include/asm/siginfo.h index 61219d7affc8..ca7dde8fd223 100644 --- a/arch/m68k/include/asm/siginfo.h +++ b/arch/m68k/include/asm/siginfo.h | |||
| @@ -1,5 +1,97 @@ | |||
| 1 | #ifdef __uClinux__ | 1 | #ifndef _M68K_SIGINFO_H |
| 2 | #include "siginfo_no.h" | 2 | #define _M68K_SIGINFO_H |
| 3 | |||
| 4 | #ifndef __uClinux__ | ||
| 5 | #define HAVE_ARCH_SIGINFO_T | ||
| 6 | #define HAVE_ARCH_COPY_SIGINFO | ||
| 7 | #endif | ||
| 8 | |||
| 9 | #include <asm-generic/siginfo.h> | ||
| 10 | |||
| 11 | #ifndef __uClinux__ | ||
| 12 | |||
| 13 | typedef struct siginfo { | ||
| 14 | int si_signo; | ||
| 15 | int si_errno; | ||
| 16 | int si_code; | ||
| 17 | |||
| 18 | union { | ||
| 19 | int _pad[SI_PAD_SIZE]; | ||
| 20 | |||
| 21 | /* kill() */ | ||
| 22 | struct { | ||
| 23 | __kernel_pid_t _pid; /* sender's pid */ | ||
| 24 | __kernel_uid_t _uid; /* backwards compatibility */ | ||
| 25 | __kernel_uid32_t _uid32; /* sender's uid */ | ||
| 26 | } _kill; | ||
| 27 | |||
| 28 | /* POSIX.1b timers */ | ||
| 29 | struct { | ||
| 30 | timer_t _tid; /* timer id */ | ||
| 31 | int _overrun; /* overrun count */ | ||
| 32 | char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)]; | ||
| 33 | sigval_t _sigval; /* same as below */ | ||
| 34 | int _sys_private; /* not to be passed to user */ | ||
| 35 | } _timer; | ||
| 36 | |||
| 37 | /* POSIX.1b signals */ | ||
| 38 | struct { | ||
| 39 | __kernel_pid_t _pid; /* sender's pid */ | ||
| 40 | __kernel_uid_t _uid; /* backwards compatibility */ | ||
| 41 | sigval_t _sigval; | ||
| 42 | __kernel_uid32_t _uid32; /* sender's uid */ | ||
| 43 | } _rt; | ||
| 44 | |||
| 45 | /* SIGCHLD */ | ||
| 46 | struct { | ||
| 47 | __kernel_pid_t _pid; /* which child */ | ||
| 48 | __kernel_uid_t _uid; /* backwards compatibility */ | ||
| 49 | int _status; /* exit code */ | ||
| 50 | clock_t _utime; | ||
| 51 | clock_t _stime; | ||
| 52 | __kernel_uid32_t _uid32; /* sender's uid */ | ||
| 53 | } _sigchld; | ||
| 54 | |||
| 55 | /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ | ||
| 56 | struct { | ||
| 57 | void *_addr; /* faulting insn/memory ref. */ | ||
| 58 | } _sigfault; | ||
| 59 | |||
| 60 | /* SIGPOLL */ | ||
| 61 | struct { | ||
| 62 | int _band; /* POLL_IN, POLL_OUT, POLL_MSG */ | ||
| 63 | int _fd; | ||
| 64 | } _sigpoll; | ||
| 65 | } _sifields; | ||
| 66 | } siginfo_t; | ||
| 67 | |||
| 68 | #define UID16_SIGINFO_COMPAT_NEEDED | ||
| 69 | |||
| 70 | /* | ||
| 71 | * How these fields are to be accessed. | ||
| 72 | */ | ||
| 73 | #undef si_uid | ||
| 74 | #ifdef __KERNEL__ | ||
| 75 | #define si_uid _sifields._kill._uid32 | ||
| 76 | #define si_uid16 _sifields._kill._uid | ||
| 3 | #else | 77 | #else |
| 4 | #include "siginfo_mm.h" | 78 | #define si_uid _sifields._kill._uid |
| 79 | #endif | ||
| 80 | |||
| 81 | #ifdef __KERNEL__ | ||
| 82 | |||
| 83 | #include <linux/string.h> | ||
| 84 | |||
| 85 | static inline void copy_siginfo(struct siginfo *to, struct siginfo *from) | ||
| 86 | { | ||
| 87 | if (from->si_code < 0) | ||
| 88 | memcpy(to, from, sizeof(*to)); | ||
| 89 | else | ||
| 90 | /* _sigchld is currently the largest know union member */ | ||
| 91 | memcpy(to, from, 3*sizeof(int) + sizeof(from->_sifields._sigchld)); | ||
| 92 | } | ||
| 93 | |||
| 94 | #endif /* __KERNEL__ */ | ||
| 95 | #endif /* !__uClinux__ */ | ||
| 96 | |||
| 5 | #endif | 97 | #endif |
diff --git a/arch/m68k/include/asm/siginfo_mm.h b/arch/m68k/include/asm/siginfo_mm.h deleted file mode 100644 index 05a8d6d90b58..000000000000 --- a/arch/m68k/include/asm/siginfo_mm.h +++ /dev/null | |||
| @@ -1,92 +0,0 @@ | |||
| 1 | #ifndef _M68K_SIGINFO_H | ||
| 2 | #define _M68K_SIGINFO_H | ||
| 3 | |||
| 4 | #define HAVE_ARCH_SIGINFO_T | ||
| 5 | #define HAVE_ARCH_COPY_SIGINFO | ||
| 6 | |||
| 7 | #include <asm-generic/siginfo.h> | ||
| 8 | |||
| 9 | typedef struct siginfo { | ||
| 10 | int si_signo; | ||
| 11 | int si_errno; | ||
| 12 | int si_code; | ||
| 13 | |||
| 14 | union { | ||
| 15 | int _pad[SI_PAD_SIZE]; | ||
| 16 | |||
| 17 | /* kill() */ | ||
| 18 | struct { | ||
| 19 | __kernel_pid_t _pid; /* sender's pid */ | ||
| 20 | __kernel_uid_t _uid; /* backwards compatibility */ | ||
| 21 | __kernel_uid32_t _uid32; /* sender's uid */ | ||
| 22 | } _kill; | ||
| 23 | |||
| 24 | /* POSIX.1b timers */ | ||
| 25 | struct { | ||
| 26 | timer_t _tid; /* timer id */ | ||
| 27 | int _overrun; /* overrun count */ | ||
| 28 | char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)]; | ||
| 29 | sigval_t _sigval; /* same as below */ | ||
| 30 | int _sys_private; /* not to be passed to user */ | ||
| 31 | } _timer; | ||
| 32 | |||
| 33 | /* POSIX.1b signals */ | ||
| 34 | struct { | ||
| 35 | __kernel_pid_t _pid; /* sender's pid */ | ||
| 36 | __kernel_uid_t _uid; /* backwards compatibility */ | ||
| 37 | sigval_t _sigval; | ||
| 38 | __kernel_uid32_t _uid32; /* sender's uid */ | ||
| 39 | } _rt; | ||
| 40 | |||
| 41 | /* SIGCHLD */ | ||
| 42 | struct { | ||
| 43 | __kernel_pid_t _pid; /* which child */ | ||
| 44 | __kernel_uid_t _uid; /* backwards compatibility */ | ||
| 45 | int _status; /* exit code */ | ||
| 46 | clock_t _utime; | ||
| 47 | clock_t _stime; | ||
| 48 | __kernel_uid32_t _uid32; /* sender's uid */ | ||
| 49 | } _sigchld; | ||
| 50 | |||
| 51 | /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */ | ||
| 52 | struct { | ||
| 53 | void *_addr; /* faulting insn/memory ref. */ | ||
| 54 | } _sigfault; | ||
| 55 | |||
| 56 | /* SIGPOLL */ | ||
| 57 | struct { | ||
| 58 | int _band; /* POLL_IN, POLL_OUT, POLL_MSG */ | ||
| 59 | int _fd; | ||
| 60 | } _sigpoll; | ||
| 61 | } _sifields; | ||
| 62 | } siginfo_t; | ||
| 63 | |||
| 64 | #define UID16_SIGINFO_COMPAT_NEEDED | ||
| 65 | |||
| 66 | /* | ||
| 67 | * How these fields are to be accessed. | ||
| 68 | */ | ||
| 69 | #undef si_uid | ||
| 70 | #ifdef __KERNEL__ | ||
| 71 | #define si_uid _sifields._kill._uid32 | ||
| 72 | #define si_uid16 _sifields._kill._uid | ||
| 73 | #else | ||
| 74 | #define si_uid _sifields._kill._uid | ||
| 75 | #endif | ||
| 76 | |||
| 77 | #ifdef __KERNEL__ | ||
| 78 | |||
| 79 | #include <linux/string.h> | ||
| 80 | |||
| 81 | static inline void copy_siginfo(struct siginfo *to, struct siginfo *from) | ||
| 82 | { | ||
| 83 | if (from->si_code < 0) | ||
| 84 | memcpy(to, from, sizeof(*to)); | ||
| 85 | else | ||
| 86 | /* _sigchld is currently the largest know union member */ | ||
| 87 | memcpy(to, from, 3*sizeof(int) + sizeof(from->_sifields._sigchld)); | ||
| 88 | } | ||
| 89 | |||
| 90 | #endif /* __KERNEL__ */ | ||
| 91 | |||
| 92 | #endif | ||
diff --git a/arch/m68k/include/asm/siginfo_no.h b/arch/m68k/include/asm/siginfo_no.h deleted file mode 100644 index b18e5f4064ae..000000000000 --- a/arch/m68k/include/asm/siginfo_no.h +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | #ifndef _M68KNOMMU_SIGINFO_H | ||
| 2 | #define _M68KNOMMU_SIGINFO_H | ||
| 3 | |||
| 4 | #include <asm-generic/siginfo.h> | ||
| 5 | |||
| 6 | #endif | ||
diff --git a/arch/m68k/include/asm/signal.h b/arch/m68k/include/asm/signal.h index 3c19988bd93c..08788fdefde0 100644 --- a/arch/m68k/include/asm/signal.h +++ b/arch/m68k/include/asm/signal.h | |||
| @@ -1,5 +1,213 @@ | |||
| 1 | #ifdef __uClinux__ | 1 | #ifndef _M68K_SIGNAL_H |
| 2 | #include "signal_no.h" | 2 | #define _M68K_SIGNAL_H |
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | |||
| 6 | /* Avoid too many header ordering problems. */ | ||
| 7 | struct siginfo; | ||
| 8 | |||
| 9 | #ifdef __KERNEL__ | ||
| 10 | /* Most things should be clean enough to redefine this at will, if care | ||
| 11 | is taken to make libc match. */ | ||
| 12 | |||
| 13 | #define _NSIG 64 | ||
| 14 | #define _NSIG_BPW 32 | ||
| 15 | #define _NSIG_WORDS (_NSIG / _NSIG_BPW) | ||
| 16 | |||
| 17 | typedef unsigned long old_sigset_t; /* at least 32 bits */ | ||
| 18 | |||
| 19 | typedef struct { | ||
| 20 | unsigned long sig[_NSIG_WORDS]; | ||
| 21 | } sigset_t; | ||
| 22 | |||
| 3 | #else | 23 | #else |
| 4 | #include "signal_mm.h" | 24 | /* Here we must cater to libcs that poke about in kernel headers. */ |
| 5 | #endif | 25 | |
| 26 | #define NSIG 32 | ||
| 27 | typedef unsigned long sigset_t; | ||
| 28 | |||
| 29 | #endif /* __KERNEL__ */ | ||
| 30 | |||
| 31 | #define SIGHUP 1 | ||
| 32 | #define SIGINT 2 | ||
| 33 | #define SIGQUIT 3 | ||
| 34 | #define SIGILL 4 | ||
| 35 | #define SIGTRAP 5 | ||
| 36 | #define SIGABRT 6 | ||
| 37 | #define SIGIOT 6 | ||
| 38 | #define SIGBUS 7 | ||
| 39 | #define SIGFPE 8 | ||
| 40 | #define SIGKILL 9 | ||
| 41 | #define SIGUSR1 10 | ||
| 42 | #define SIGSEGV 11 | ||
| 43 | #define SIGUSR2 12 | ||
| 44 | #define SIGPIPE 13 | ||
| 45 | #define SIGALRM 14 | ||
| 46 | #define SIGTERM 15 | ||
| 47 | #define SIGSTKFLT 16 | ||
| 48 | #define SIGCHLD 17 | ||
| 49 | #define SIGCONT 18 | ||
| 50 | #define SIGSTOP 19 | ||
| 51 | #define SIGTSTP 20 | ||
| 52 | #define SIGTTIN 21 | ||
| 53 | #define SIGTTOU 22 | ||
| 54 | #define SIGURG 23 | ||
| 55 | #define SIGXCPU 24 | ||
| 56 | #define SIGXFSZ 25 | ||
| 57 | #define SIGVTALRM 26 | ||
| 58 | #define SIGPROF 27 | ||
| 59 | #define SIGWINCH 28 | ||
| 60 | #define SIGIO 29 | ||
| 61 | #define SIGPOLL SIGIO | ||
| 62 | /* | ||
| 63 | #define SIGLOST 29 | ||
| 64 | */ | ||
| 65 | #define SIGPWR 30 | ||
| 66 | #define SIGSYS 31 | ||
| 67 | #define SIGUNUSED 31 | ||
| 68 | |||
| 69 | /* These should not be considered constants from userland. */ | ||
| 70 | #define SIGRTMIN 32 | ||
| 71 | #define SIGRTMAX _NSIG | ||
| 72 | |||
| 73 | /* | ||
| 74 | * SA_FLAGS values: | ||
| 75 | * | ||
| 76 | * SA_ONSTACK indicates that a registered stack_t will be used. | ||
| 77 | * SA_RESTART flag to get restarting signals (which were the default long ago) | ||
| 78 | * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. | ||
| 79 | * SA_RESETHAND clears the handler when the signal is delivered. | ||
| 80 | * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. | ||
| 81 | * SA_NODEFER prevents the current signal from being masked in the handler. | ||
| 82 | * | ||
| 83 | * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single | ||
| 84 | * Unix names RESETHAND and NODEFER respectively. | ||
| 85 | */ | ||
| 86 | #define SA_NOCLDSTOP 0x00000001 | ||
| 87 | #define SA_NOCLDWAIT 0x00000002 | ||
| 88 | #define SA_SIGINFO 0x00000004 | ||
| 89 | #define SA_ONSTACK 0x08000000 | ||
| 90 | #define SA_RESTART 0x10000000 | ||
| 91 | #define SA_NODEFER 0x40000000 | ||
| 92 | #define SA_RESETHAND 0x80000000 | ||
| 93 | |||
| 94 | #define SA_NOMASK SA_NODEFER | ||
| 95 | #define SA_ONESHOT SA_RESETHAND | ||
| 96 | |||
| 97 | /* | ||
| 98 | * sigaltstack controls | ||
| 99 | */ | ||
| 100 | #define SS_ONSTACK 1 | ||
| 101 | #define SS_DISABLE 2 | ||
| 102 | |||
| 103 | #define MINSIGSTKSZ 2048 | ||
| 104 | #define SIGSTKSZ 8192 | ||
| 105 | |||
| 106 | #include <asm-generic/signal.h> | ||
| 107 | |||
| 108 | #ifdef __KERNEL__ | ||
| 109 | struct old_sigaction { | ||
| 110 | __sighandler_t sa_handler; | ||
| 111 | old_sigset_t sa_mask; | ||
| 112 | unsigned long sa_flags; | ||
| 113 | __sigrestore_t sa_restorer; | ||
| 114 | }; | ||
| 115 | |||
| 116 | struct sigaction { | ||
| 117 | __sighandler_t sa_handler; | ||
| 118 | unsigned long sa_flags; | ||
| 119 | __sigrestore_t sa_restorer; | ||
| 120 | sigset_t sa_mask; /* mask last for extensibility */ | ||
| 121 | }; | ||
| 122 | |||
| 123 | struct k_sigaction { | ||
| 124 | struct sigaction sa; | ||
| 125 | }; | ||
| 126 | #else | ||
| 127 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 128 | |||
| 129 | struct sigaction { | ||
| 130 | union { | ||
| 131 | __sighandler_t _sa_handler; | ||
| 132 | void (*_sa_sigaction)(int, struct siginfo *, void *); | ||
| 133 | } _u; | ||
| 134 | sigset_t sa_mask; | ||
| 135 | unsigned long sa_flags; | ||
| 136 | void (*sa_restorer)(void); | ||
| 137 | }; | ||
| 138 | |||
| 139 | #define sa_handler _u._sa_handler | ||
| 140 | #define sa_sigaction _u._sa_sigaction | ||
| 141 | |||
| 142 | #endif /* __KERNEL__ */ | ||
| 143 | |||
| 144 | typedef struct sigaltstack { | ||
| 145 | void __user *ss_sp; | ||
| 146 | int ss_flags; | ||
| 147 | size_t ss_size; | ||
| 148 | } stack_t; | ||
| 149 | |||
| 150 | #ifdef __KERNEL__ | ||
| 151 | #include <asm/sigcontext.h> | ||
| 152 | |||
| 153 | #ifndef __uClinux__ | ||
| 154 | #define __HAVE_ARCH_SIG_BITOPS | ||
| 155 | |||
| 156 | static inline void sigaddset(sigset_t *set, int _sig) | ||
| 157 | { | ||
| 158 | asm ("bfset %0{%1,#1}" | ||
| 159 | : "+od" (*set) | ||
| 160 | : "id" ((_sig - 1) ^ 31) | ||
| 161 | : "cc"); | ||
| 162 | } | ||
| 163 | |||
| 164 | static inline void sigdelset(sigset_t *set, int _sig) | ||
| 165 | { | ||
| 166 | asm ("bfclr %0{%1,#1}" | ||
| 167 | : "+od" (*set) | ||
| 168 | : "id" ((_sig - 1) ^ 31) | ||
| 169 | : "cc"); | ||
| 170 | } | ||
| 171 | |||
| 172 | static inline int __const_sigismember(sigset_t *set, int _sig) | ||
| 173 | { | ||
| 174 | unsigned long sig = _sig - 1; | ||
| 175 | return 1 & (set->sig[sig / _NSIG_BPW] >> (sig % _NSIG_BPW)); | ||
| 176 | } | ||
| 177 | |||
| 178 | static inline int __gen_sigismember(sigset_t *set, int _sig) | ||
| 179 | { | ||
| 180 | int ret; | ||
| 181 | asm ("bfextu %1{%2,#1},%0" | ||
| 182 | : "=d" (ret) | ||
| 183 | : "od" (*set), "id" ((_sig-1) ^ 31) | ||
| 184 | : "cc"); | ||
| 185 | return ret; | ||
| 186 | } | ||
| 187 | |||
| 188 | #define sigismember(set,sig) \ | ||
| 189 | (__builtin_constant_p(sig) ? \ | ||
| 190 | __const_sigismember(set,sig) : \ | ||
| 191 | __gen_sigismember(set,sig)) | ||
| 192 | |||
| 193 | static inline int sigfindinword(unsigned long word) | ||
| 194 | { | ||
| 195 | asm ("bfffo %1{#0,#0},%0" | ||
| 196 | : "=d" (word) | ||
| 197 | : "d" (word & -word) | ||
| 198 | : "cc"); | ||
| 199 | return word ^ 31; | ||
| 200 | } | ||
| 201 | |||
| 202 | struct pt_regs; | ||
| 203 | extern void ptrace_signal_deliver(struct pt_regs *regs, void *cookie); | ||
| 204 | |||
| 205 | #else | ||
| 206 | |||
| 207 | #undef __HAVE_ARCH_SIG_BITOPS | ||
| 208 | #define ptrace_signal_deliver(regs, cookie) do { } while (0) | ||
| 209 | |||
| 210 | #endif /* __uClinux__ */ | ||
| 211 | #endif /* __KERNEL__ */ | ||
| 212 | |||
| 213 | #endif /* _M68K_SIGNAL_H */ | ||
diff --git a/arch/m68k/include/asm/signal_mm.h b/arch/m68k/include/asm/signal_mm.h deleted file mode 100644 index 3db8a81942f1..000000000000 --- a/arch/m68k/include/asm/signal_mm.h +++ /dev/null | |||
| @@ -1,206 +0,0 @@ | |||
| 1 | #ifndef _M68K_SIGNAL_H | ||
| 2 | #define _M68K_SIGNAL_H | ||
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | |||
| 6 | /* Avoid too many header ordering problems. */ | ||
| 7 | struct siginfo; | ||
| 8 | |||
| 9 | #ifdef __KERNEL__ | ||
| 10 | /* Most things should be clean enough to redefine this at will, if care | ||
| 11 | is taken to make libc match. */ | ||
| 12 | |||
| 13 | #define _NSIG 64 | ||
| 14 | #define _NSIG_BPW 32 | ||
| 15 | #define _NSIG_WORDS (_NSIG / _NSIG_BPW) | ||
| 16 | |||
| 17 | typedef unsigned long old_sigset_t; /* at least 32 bits */ | ||
| 18 | |||
| 19 | typedef struct { | ||
| 20 | unsigned long sig[_NSIG_WORDS]; | ||
| 21 | } sigset_t; | ||
| 22 | |||
| 23 | #else | ||
| 24 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 25 | |||
| 26 | #define NSIG 32 | ||
| 27 | typedef unsigned long sigset_t; | ||
| 28 | |||
| 29 | #endif /* __KERNEL__ */ | ||
| 30 | |||
| 31 | #define SIGHUP 1 | ||
| 32 | #define SIGINT 2 | ||
| 33 | #define SIGQUIT 3 | ||
| 34 | #define SIGILL 4 | ||
| 35 | #define SIGTRAP 5 | ||
| 36 | #define SIGABRT 6 | ||
| 37 | #define SIGIOT 6 | ||
| 38 | #define SIGBUS 7 | ||
| 39 | #define SIGFPE 8 | ||
| 40 | #define SIGKILL 9 | ||
| 41 | #define SIGUSR1 10 | ||
| 42 | #define SIGSEGV 11 | ||
| 43 | #define SIGUSR2 12 | ||
| 44 | #define SIGPIPE 13 | ||
| 45 | #define SIGALRM 14 | ||
| 46 | #define SIGTERM 15 | ||
| 47 | #define SIGSTKFLT 16 | ||
| 48 | #define SIGCHLD 17 | ||
| 49 | #define SIGCONT 18 | ||
| 50 | #define SIGSTOP 19 | ||
| 51 | #define SIGTSTP 20 | ||
| 52 | #define SIGTTIN 21 | ||
| 53 | #define SIGTTOU 22 | ||
| 54 | #define SIGURG 23 | ||
| 55 | #define SIGXCPU 24 | ||
| 56 | #define SIGXFSZ 25 | ||
| 57 | #define SIGVTALRM 26 | ||
| 58 | #define SIGPROF 27 | ||
| 59 | #define SIGWINCH 28 | ||
| 60 | #define SIGIO 29 | ||
| 61 | #define SIGPOLL SIGIO | ||
| 62 | /* | ||
| 63 | #define SIGLOST 29 | ||
| 64 | */ | ||
| 65 | #define SIGPWR 30 | ||
| 66 | #define SIGSYS 31 | ||
| 67 | #define SIGUNUSED 31 | ||
| 68 | |||
| 69 | /* These should not be considered constants from userland. */ | ||
| 70 | #define SIGRTMIN 32 | ||
| 71 | #define SIGRTMAX _NSIG | ||
| 72 | |||
| 73 | /* | ||
| 74 | * SA_FLAGS values: | ||
| 75 | * | ||
| 76 | * SA_ONSTACK indicates that a registered stack_t will be used. | ||
| 77 | * SA_RESTART flag to get restarting signals (which were the default long ago) | ||
| 78 | * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. | ||
| 79 | * SA_RESETHAND clears the handler when the signal is delivered. | ||
| 80 | * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. | ||
| 81 | * SA_NODEFER prevents the current signal from being masked in the handler. | ||
| 82 | * | ||
| 83 | * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single | ||
| 84 | * Unix names RESETHAND and NODEFER respectively. | ||
| 85 | */ | ||
| 86 | #define SA_NOCLDSTOP 0x00000001 | ||
| 87 | #define SA_NOCLDWAIT 0x00000002 | ||
| 88 | #define SA_SIGINFO 0x00000004 | ||
| 89 | #define SA_ONSTACK 0x08000000 | ||
| 90 | #define SA_RESTART 0x10000000 | ||
| 91 | #define SA_NODEFER 0x40000000 | ||
| 92 | #define SA_RESETHAND 0x80000000 | ||
| 93 | |||
| 94 | #define SA_NOMASK SA_NODEFER | ||
| 95 | #define SA_ONESHOT SA_RESETHAND | ||
| 96 | |||
| 97 | /* | ||
| 98 | * sigaltstack controls | ||
| 99 | */ | ||
| 100 | #define SS_ONSTACK 1 | ||
| 101 | #define SS_DISABLE 2 | ||
| 102 | |||
| 103 | #define MINSIGSTKSZ 2048 | ||
| 104 | #define SIGSTKSZ 8192 | ||
| 105 | |||
| 106 | #include <asm-generic/signal.h> | ||
| 107 | |||
| 108 | #ifdef __KERNEL__ | ||
| 109 | struct old_sigaction { | ||
| 110 | __sighandler_t sa_handler; | ||
| 111 | old_sigset_t sa_mask; | ||
| 112 | unsigned long sa_flags; | ||
| 113 | __sigrestore_t sa_restorer; | ||
| 114 | }; | ||
| 115 | |||
| 116 | struct sigaction { | ||
| 117 | __sighandler_t sa_handler; | ||
| 118 | unsigned long sa_flags; | ||
| 119 | __sigrestore_t sa_restorer; | ||
| 120 | sigset_t sa_mask; /* mask last for extensibility */ | ||
| 121 | }; | ||
| 122 | |||
| 123 | struct k_sigaction { | ||
| 124 | struct sigaction sa; | ||
| 125 | }; | ||
| 126 | #else | ||
| 127 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 128 | |||
| 129 | struct sigaction { | ||
| 130 | union { | ||
| 131 | __sighandler_t _sa_handler; | ||
| 132 | void (*_sa_sigaction)(int, struct siginfo *, void *); | ||
| 133 | } _u; | ||
| 134 | sigset_t sa_mask; | ||
| 135 | unsigned long sa_flags; | ||
| 136 | void (*sa_restorer)(void); | ||
| 137 | }; | ||
| 138 | |||
| 139 | #define sa_handler _u._sa_handler | ||
| 140 | #define sa_sigaction _u._sa_sigaction | ||
| 141 | |||
| 142 | #endif /* __KERNEL__ */ | ||
| 143 | |||
| 144 | typedef struct sigaltstack { | ||
| 145 | void __user *ss_sp; | ||
| 146 | int ss_flags; | ||
| 147 | size_t ss_size; | ||
| 148 | } stack_t; | ||
| 149 | |||
| 150 | #ifdef __KERNEL__ | ||
| 151 | #include <asm/sigcontext.h> | ||
| 152 | |||
| 153 | #define __HAVE_ARCH_SIG_BITOPS | ||
| 154 | |||
| 155 | static inline void sigaddset(sigset_t *set, int _sig) | ||
| 156 | { | ||
| 157 | asm ("bfset %0{%1,#1}" | ||
| 158 | : "+od" (*set) | ||
| 159 | : "id" ((_sig - 1) ^ 31) | ||
| 160 | : "cc"); | ||
| 161 | } | ||
| 162 | |||
| 163 | static inline void sigdelset(sigset_t *set, int _sig) | ||
| 164 | { | ||
| 165 | asm ("bfclr %0{%1,#1}" | ||
| 166 | : "+od" (*set) | ||
| 167 | : "id" ((_sig - 1) ^ 31) | ||
| 168 | : "cc"); | ||
| 169 | } | ||
| 170 | |||
| 171 | static inline int __const_sigismember(sigset_t *set, int _sig) | ||
| 172 | { | ||
| 173 | unsigned long sig = _sig - 1; | ||
| 174 | return 1 & (set->sig[sig / _NSIG_BPW] >> (sig % _NSIG_BPW)); | ||
| 175 | } | ||
| 176 | |||
| 177 | static inline int __gen_sigismember(sigset_t *set, int _sig) | ||
| 178 | { | ||
| 179 | int ret; | ||
| 180 | asm ("bfextu %1{%2,#1},%0" | ||
| 181 | : "=d" (ret) | ||
| 182 | : "od" (*set), "id" ((_sig-1) ^ 31) | ||
| 183 | : "cc"); | ||
| 184 | return ret; | ||
| 185 | } | ||
| 186 | |||
| 187 | #define sigismember(set,sig) \ | ||
| 188 | (__builtin_constant_p(sig) ? \ | ||
| 189 | __const_sigismember(set,sig) : \ | ||
| 190 | __gen_sigismember(set,sig)) | ||
| 191 | |||
| 192 | static inline int sigfindinword(unsigned long word) | ||
| 193 | { | ||
| 194 | asm ("bfffo %1{#0,#0},%0" | ||
| 195 | : "=d" (word) | ||
| 196 | : "d" (word & -word) | ||
| 197 | : "cc"); | ||
| 198 | return word ^ 31; | ||
| 199 | } | ||
| 200 | |||
| 201 | struct pt_regs; | ||
| 202 | extern void ptrace_signal_deliver(struct pt_regs *regs, void *cookie); | ||
| 203 | |||
| 204 | #endif /* __KERNEL__ */ | ||
| 205 | |||
| 206 | #endif /* _M68K_SIGNAL_H */ | ||
diff --git a/arch/m68k/include/asm/signal_no.h b/arch/m68k/include/asm/signal_no.h deleted file mode 100644 index 216c08be54a0..000000000000 --- a/arch/m68k/include/asm/signal_no.h +++ /dev/null | |||
| @@ -1,159 +0,0 @@ | |||
| 1 | #ifndef _M68KNOMMU_SIGNAL_H | ||
| 2 | #define _M68KNOMMU_SIGNAL_H | ||
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | |||
| 6 | /* Avoid too many header ordering problems. */ | ||
| 7 | struct siginfo; | ||
| 8 | |||
| 9 | #ifdef __KERNEL__ | ||
| 10 | /* Most things should be clean enough to redefine this at will, if care | ||
| 11 | is taken to make libc match. */ | ||
| 12 | |||
| 13 | #define _NSIG 64 | ||
| 14 | #define _NSIG_BPW 32 | ||
| 15 | #define _NSIG_WORDS (_NSIG / _NSIG_BPW) | ||
| 16 | |||
| 17 | typedef unsigned long old_sigset_t; /* at least 32 bits */ | ||
| 18 | |||
| 19 | typedef struct { | ||
| 20 | unsigned long sig[_NSIG_WORDS]; | ||
| 21 | } sigset_t; | ||
| 22 | |||
| 23 | #else | ||
| 24 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 25 | |||
| 26 | #define NSIG 32 | ||
| 27 | typedef unsigned long sigset_t; | ||
| 28 | |||
| 29 | #endif /* __KERNEL__ */ | ||
| 30 | |||
| 31 | #define SIGHUP 1 | ||
| 32 | #define SIGINT 2 | ||
| 33 | #define SIGQUIT 3 | ||
| 34 | #define SIGILL 4 | ||
| 35 | #define SIGTRAP 5 | ||
| 36 | #define SIGABRT 6 | ||
| 37 | #define SIGIOT 6 | ||
| 38 | #define SIGBUS 7 | ||
| 39 | #define SIGFPE 8 | ||
| 40 | #define SIGKILL 9 | ||
| 41 | #define SIGUSR1 10 | ||
| 42 | #define SIGSEGV 11 | ||
| 43 | #define SIGUSR2 12 | ||
| 44 | #define SIGPIPE 13 | ||
| 45 | #define SIGALRM 14 | ||
| 46 | #define SIGTERM 15 | ||
| 47 | #define SIGSTKFLT 16 | ||
| 48 | #define SIGCHLD 17 | ||
| 49 | #define SIGCONT 18 | ||
| 50 | #define SIGSTOP 19 | ||
| 51 | #define SIGTSTP 20 | ||
| 52 | #define SIGTTIN 21 | ||
| 53 | #define SIGTTOU 22 | ||
| 54 | #define SIGURG 23 | ||
| 55 | #define SIGXCPU 24 | ||
| 56 | #define SIGXFSZ 25 | ||
| 57 | #define SIGVTALRM 26 | ||
| 58 | #define SIGPROF 27 | ||
| 59 | #define SIGWINCH 28 | ||
| 60 | #define SIGIO 29 | ||
| 61 | #define SIGPOLL SIGIO | ||
| 62 | /* | ||
| 63 | #define SIGLOST 29 | ||
| 64 | */ | ||
| 65 | #define SIGPWR 30 | ||
| 66 | #define SIGSYS 31 | ||
| 67 | #define SIGUNUSED 31 | ||
| 68 | |||
| 69 | /* These should not be considered constants from userland. */ | ||
| 70 | #define SIGRTMIN 32 | ||
| 71 | #define SIGRTMAX _NSIG | ||
| 72 | |||
| 73 | /* | ||
| 74 | * SA_FLAGS values: | ||
| 75 | * | ||
| 76 | * SA_ONSTACK indicates that a registered stack_t will be used. | ||
| 77 | * SA_RESTART flag to get restarting signals (which were the default long ago) | ||
| 78 | * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. | ||
| 79 | * SA_RESETHAND clears the handler when the signal is delivered. | ||
| 80 | * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. | ||
| 81 | * SA_NODEFER prevents the current signal from being masked in the handler. | ||
| 82 | * | ||
| 83 | * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single | ||
| 84 | * Unix names RESETHAND and NODEFER respectively. | ||
| 85 | */ | ||
| 86 | #define SA_NOCLDSTOP 0x00000001 | ||
| 87 | #define SA_NOCLDWAIT 0x00000002 | ||
| 88 | #define SA_SIGINFO 0x00000004 | ||
| 89 | #define SA_ONSTACK 0x08000000 | ||
| 90 | #define SA_RESTART 0x10000000 | ||
| 91 | #define SA_NODEFER 0x40000000 | ||
| 92 | #define SA_RESETHAND 0x80000000 | ||
| 93 | |||
| 94 | #define SA_NOMASK SA_NODEFER | ||
| 95 | #define SA_ONESHOT SA_RESETHAND | ||
| 96 | |||
| 97 | /* | ||
| 98 | * sigaltstack controls | ||
| 99 | */ | ||
| 100 | #define SS_ONSTACK 1 | ||
| 101 | #define SS_DISABLE 2 | ||
| 102 | |||
| 103 | #define MINSIGSTKSZ 2048 | ||
| 104 | #define SIGSTKSZ 8192 | ||
| 105 | |||
| 106 | #include <asm-generic/signal.h> | ||
| 107 | |||
| 108 | #ifdef __KERNEL__ | ||
| 109 | struct old_sigaction { | ||
| 110 | __sighandler_t sa_handler; | ||
| 111 | old_sigset_t sa_mask; | ||
| 112 | unsigned long sa_flags; | ||
| 113 | void (*sa_restorer)(void); | ||
| 114 | }; | ||
| 115 | |||
| 116 | struct sigaction { | ||
| 117 | __sighandler_t sa_handler; | ||
| 118 | unsigned long sa_flags; | ||
| 119 | void (*sa_restorer)(void); | ||
| 120 | sigset_t sa_mask; /* mask last for extensibility */ | ||
| 121 | }; | ||
| 122 | |||
| 123 | struct k_sigaction { | ||
| 124 | struct sigaction sa; | ||
| 125 | }; | ||
| 126 | #else | ||
| 127 | /* Here we must cater to libcs that poke about in kernel headers. */ | ||
| 128 | |||
| 129 | struct sigaction { | ||
| 130 | union { | ||
| 131 | __sighandler_t _sa_handler; | ||
| 132 | void (*_sa_sigaction)(int, struct siginfo *, void *); | ||
| 133 | } _u; | ||
| 134 | sigset_t sa_mask; | ||
| 135 | unsigned long sa_flags; | ||
| 136 | void (*sa_restorer)(void); | ||
| 137 | }; | ||
| 138 | |||
| 139 | #define sa_handler _u._sa_handler | ||
| 140 | #define sa_sigaction _u._sa_sigaction | ||
| 141 | |||
| 142 | #endif /* __KERNEL__ */ | ||
| 143 | |||
| 144 | typedef struct sigaltstack { | ||
| 145 | void *ss_sp; | ||
| 146 | int ss_flags; | ||
| 147 | size_t ss_size; | ||
| 148 | } stack_t; | ||
| 149 | |||
| 150 | #ifdef __KERNEL__ | ||
| 151 | |||
| 152 | #include <asm/sigcontext.h> | ||
| 153 | #undef __HAVE_ARCH_SIG_BITOPS | ||
| 154 | |||
| 155 | #define ptrace_signal_deliver(regs, cookie) do { } while (0) | ||
| 156 | |||
| 157 | #endif /* __KERNEL__ */ | ||
| 158 | |||
| 159 | #endif /* _M68KNOMMU_SIGNAL_H */ | ||
diff --git a/arch/m68k/include/asm/swab.h b/arch/m68k/include/asm/swab.h index 7d7dde1c73ec..9e3054ea59e9 100644 --- a/arch/m68k/include/asm/swab.h +++ b/arch/m68k/include/asm/swab.h | |||
| @@ -1,5 +1,27 @@ | |||
| 1 | #ifdef __uClinux__ | 1 | #ifndef _M68K_SWAB_H |
| 2 | #include "swab_no.h" | 2 | #define _M68K_SWAB_H |
| 3 | #else | 3 | |
| 4 | #include "swab_mm.h" | 4 | #include <asm/types.h> |
| 5 | #include <linux/compiler.h> | ||
| 6 | |||
| 7 | #define __SWAB_64_THRU_32__ | ||
| 8 | |||
| 9 | #if defined (__mcfisaaplus__) || defined (__mcfisac__) | ||
| 10 | static inline __attribute_const__ __u32 __arch_swab32(__u32 val) | ||
| 11 | { | ||
| 12 | __asm__("byterev %0" : "=d" (val) : "0" (val)); | ||
| 13 | return val; | ||
| 14 | } | ||
| 15 | |||
| 16 | #define __arch_swab32 __arch_swab32 | ||
| 17 | #elif !defined(__uClinux__) | ||
| 18 | |||
| 19 | static inline __attribute_const__ __u32 __arch_swab32(__u32 val) | ||
| 20 | { | ||
| 21 | __asm__("rolw #8,%0; swap %0; rolw #8,%0" : "=d" (val) : "0" (val)); | ||
| 22 | return val; | ||
| 23 | } | ||
| 24 | #define __arch_swab32 __arch_swab32 | ||
| 5 | #endif | 25 | #endif |
| 26 | |||
| 27 | #endif /* _M68K_SWAB_H */ | ||
diff --git a/arch/m68k/include/asm/swab_mm.h b/arch/m68k/include/asm/swab_mm.h deleted file mode 100644 index 7221e3066825..000000000000 --- a/arch/m68k/include/asm/swab_mm.h +++ /dev/null | |||
| @@ -1,16 +0,0 @@ | |||
| 1 | #ifndef _M68K_SWAB_H | ||
| 2 | #define _M68K_SWAB_H | ||
| 3 | |||
| 4 | #include <asm/types.h> | ||
| 5 | #include <linux/compiler.h> | ||
| 6 | |||
| 7 | #define __SWAB_64_THRU_32__ | ||
| 8 | |||
| 9 | static inline __attribute_const__ __u32 __arch_swab32(__u32 val) | ||
| 10 | { | ||
| 11 | __asm__("rolw #8,%0; swap %0; rolw #8,%0" : "=d" (val) : "0" (val)); | ||
| 12 | return val; | ||
| 13 | } | ||
| 14 | #define __arch_swab32 __arch_swab32 | ||
| 15 | |||
| 16 | #endif /* _M68K_SWAB_H */ | ||
diff --git a/arch/m68k/include/asm/swab_no.h b/arch/m68k/include/asm/swab_no.h deleted file mode 100644 index e582257db300..000000000000 --- a/arch/m68k/include/asm/swab_no.h +++ /dev/null | |||
| @@ -1,24 +0,0 @@ | |||
| 1 | #ifndef _M68KNOMMU_SWAB_H | ||
| 2 | #define _M68KNOMMU_SWAB_H | ||
| 3 | |||
| 4 | #include <linux/types.h> | ||
| 5 | |||
| 6 | #if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__) | ||
| 7 | # define __SWAB_64_THRU_32__ | ||
| 8 | #endif | ||
| 9 | |||
| 10 | #if defined (__mcfisaaplus__) || defined (__mcfisac__) | ||
| 11 | static inline __attribute_const__ __u32 __arch_swab32(__u32 val) | ||
| 12 | { | ||
| 13 | asm( | ||
| 14 | "byterev %0" | ||
| 15 | : "=d" (val) | ||
| 16 | : "0" (val) | ||
| 17 | ); | ||
| 18 | return val; | ||
| 19 | } | ||
| 20 | |||
| 21 | #define __arch_swab32 __arch_swab32 | ||
| 22 | #endif | ||
| 23 | |||
| 24 | #endif /* _M68KNOMMU_SWAB_H */ | ||
diff --git a/arch/m68k/include/asm/unistd.h b/arch/m68k/include/asm/unistd.h index df1d9d4cb1fd..3c19027331fa 100644 --- a/arch/m68k/include/asm/unistd.h +++ b/arch/m68k/include/asm/unistd.h | |||
| @@ -1,5 +1,372 @@ | |||
| 1 | #ifdef __uClinux__ | 1 | #ifndef _ASM_M68K_UNISTD_H_ |
| 2 | #include "unistd_no.h" | 2 | #define _ASM_M68K_UNISTD_H_ |
| 3 | #else | 3 | |
| 4 | #include "unistd_mm.h" | 4 | /* |
| 5 | #endif | 5 | * This file contains the system call numbers. |
| 6 | */ | ||
| 7 | |||
| 8 | #define __NR_restart_syscall 0 | ||
| 9 | #define __NR_exit 1 | ||
| 10 | #define __NR_fork 2 | ||
| 11 | #define __NR_read 3 | ||
| 12 | #define __NR_write 4 | ||
| 13 | #define __NR_open 5 | ||
| 14 | #define __NR_close 6 | ||
| 15 | #define __NR_waitpid 7 | ||
| 16 | #define __NR_creat 8 | ||
| 17 | #define __NR_link 9 | ||
| 18 | #define __NR_unlink 10 | ||
| 19 | #define __NR_execve 11 | ||
| 20 | #define __NR_chdir 12 | ||
| 21 | #define __NR_time 13 | ||
| 22 | #define __NR_mknod 14 | ||
| 23 | #define __NR_chmod 15 | ||
| 24 | #define __NR_chown 16 | ||
| 25 | #define __NR_break 17 | ||
| 26 | #define __NR_oldstat 18 | ||
| 27 | #define __NR_lseek 19 | ||
| 28 | #define __NR_getpid 20 | ||
| 29 | #define __NR_mount 21 | ||
| 30 | #define __NR_umount 22 | ||
| 31 | #define __NR_setuid 23 | ||
| 32 | #define __NR_getuid 24 | ||
| 33 | #define __NR_stime 25 | ||
| 34 | #define __NR_ptrace 26 | ||
| 35 | #define __NR_alarm 27 | ||
| 36 | #define __NR_oldfstat 28 | ||
| 37 | #define __NR_pause 29 | ||
| 38 | #define __NR_utime 30 | ||
| 39 | #define __NR_stty 31 | ||
| 40 | #define __NR_gtty 32 | ||
| 41 | #define __NR_access 33 | ||
| 42 | #define __NR_nice 34 | ||
| 43 | #define __NR_ftime 35 | ||
| 44 | #define __NR_sync 36 | ||
| 45 | #define __NR_kill 37 | ||
| 46 | #define __NR_rename 38 | ||
| 47 | #define __NR_mkdir 39 | ||
| 48 | #define __NR_rmdir 40 | ||
| 49 | #define __NR_dup 41 | ||
| 50 | #define __NR_pipe 42 | ||
| 51 | #define __NR_times 43 | ||
| 52 | #define __NR_prof 44 | ||
| 53 | #define __NR_brk 45 | ||
| 54 | #define __NR_setgid 46 | ||
| 55 | #define __NR_getgid 47 | ||
| 56 | #define __NR_signal 48 | ||
| 57 | #define __NR_geteuid 49 | ||
| 58 | #define __NR_getegid 50 | ||
| 59 | #define __NR_acct 51 | ||
| 60 | #define __NR_umount2 52 | ||
| 61 | #define __NR_lock 53 | ||
| 62 | #define __NR_ioctl 54 | ||
| 63 | #define __NR_fcntl 55 | ||
| 64 | #define __NR_mpx 56 | ||
| 65 | #define __NR_setpgid 57 | ||
| 66 | #define __NR_ulimit 58 | ||
| 67 | #define __NR_oldolduname 59 | ||
| 68 | #define __NR_umask 60 | ||
| 69 | #define __NR_chroot 61 | ||
| 70 | #define __NR_ustat 62 | ||
| 71 | #define __NR_dup2 63 | ||
| 72 | #define __NR_getppid 64 | ||
| 73 | #define __NR_getpgrp 65 | ||
| 74 | #define __NR_setsid 66 | ||
| 75 | #define __NR_sigaction 67 | ||
| 76 | #define __NR_sgetmask 68 | ||
| 77 | #define __NR_ssetmask 69 | ||
| 78 | #define __NR_setreuid 70 | ||
| 79 | #define __NR_setregid 71 | ||
| 80 | #define __NR_sigsuspend 72 | ||
| 81 | #define __NR_sigpending 73 | ||
| 82 | #define __NR_sethostname 74 | ||
| 83 | #define __NR_setrlimit 75 | ||
| 84 | #define __NR_getrlimit 76 | ||
| 85 | #define __NR_getrusage 77 | ||
| 86 | #define __NR_gettimeofday 78 | ||
| 87 | #define __NR_settimeofday 79 | ||
| 88 | #define __NR_getgroups 80 | ||
| 89 | #define __NR_setgroups 81 | ||
| 90 | #define __NR_select 82 | ||
| 91 | #define __NR_symlink 83 | ||
| 92 | #define __NR_oldlstat 84 | ||
| 93 | #define __NR_readlink 85 | ||
| 94 | #define __NR_uselib 86 | ||
| 95 | #define __NR_swapon 87 | ||
| 96 | #define __NR_reboot 88 | ||
| 97 | #define __NR_readdir 89 | ||
| 98 | #define __NR_mmap 90 | ||
| 99 | #define __NR_munmap 91 | ||
| 100 | #define __NR_truncate 92 | ||
| 101 | #define __NR_ftruncate 93 | ||
| 102 | #define __NR_fchmod 94 | ||
| 103 | #define __NR_fchown 95 | ||
| 104 | #define __NR_getpriority 96 | ||
| 105 | #define __NR_setpriority 97 | ||
| 106 | #define __NR_profil 98 | ||
| 107 | #define __NR_statfs 99 | ||
| 108 | #define __NR_fstatfs 100 | ||
| 109 | #define __NR_ioperm 101 | ||
| 110 | #define __NR_socketcall 102 | ||
| 111 | #define __NR_syslog 103 | ||
| 112 | #define __NR_setitimer 104 | ||
| 113 | #define __NR_getitimer 105 | ||
| 114 | #define __NR_stat 106 | ||
| 115 | #define __NR_lstat 107 | ||
| 116 | #define __NR_fstat 108 | ||
| 117 | #define __NR_olduname 109 | ||
| 118 | #define __NR_iopl /* 110 */ not supported | ||
| 119 | #define __NR_vhangup 111 | ||
| 120 | #define __NR_idle /* 112 */ Obsolete | ||
| 121 | #define __NR_vm86 /* 113 */ not supported | ||
| 122 | #define __NR_wait4 114 | ||
| 123 | #define __NR_swapoff 115 | ||
| 124 | #define __NR_sysinfo 116 | ||
| 125 | #define __NR_ipc 117 | ||
| 126 | #define __NR_fsync 118 | ||
| 127 | #define __NR_sigreturn 119 | ||
| 128 | #define __NR_clone 120 | ||
| 129 | #define __NR_setdomainname 121 | ||
| 130 | #define __NR_uname 122 | ||
| 131 | #define __NR_cacheflush 123 | ||
| 132 | #define __NR_adjtimex 124 | ||
| 133 | #define __NR_mprotect 125 | ||
| 134 | #define __NR_sigprocmask 126 | ||
| 135 | #define __NR_create_module 127 | ||
| 136 | #define __NR_init_module 128 | ||
| 137 | #define __NR_delete_module 129 | ||
| 138 | #define __NR_get_kernel_syms 130 | ||
| 139 | #define __NR_quotactl 131 | ||
| 140 | #define __NR_getpgid 132 | ||
| 141 | #define __NR_fchdir 133 | ||
| 142 | #define __NR_bdflush 134 | ||
| 143 | #define __NR_sysfs 135 | ||
| 144 | #define __NR_personality 136 | ||
| 145 | #define __NR_afs_syscall 137 /* Syscall for Andrew File System */ | ||
| 146 | #define __NR_setfsuid 138 | ||
| 147 | #define __NR_setfsgid 139 | ||
| 148 | #define __NR__llseek 140 | ||
| 149 | #define __NR_getdents 141 | ||
| 150 | #define __NR__newselect 142 | ||
| 151 | #define __NR_flock 143 | ||
| 152 | #define __NR_msync 144 | ||
| 153 | #define __NR_readv 145 | ||
| 154 | #define __NR_writev 146 | ||
| 155 | #define __NR_getsid 147 | ||
| 156 | #define __NR_fdatasync 148 | ||
| 157 | #define __NR__sysctl 149 | ||
| 158 | #define __NR_mlock 150 | ||
| 159 | #define __NR_munlock 151 | ||
| 160 | #define __NR_mlockall 152 | ||
| 161 | #define __NR_munlockall 153 | ||
| 162 | #define __NR_sched_setparam 154 | ||
| 163 | #define __NR_sched_getparam 155 | ||
| 164 | #define __NR_sched_setscheduler 156 | ||
| 165 | #define __NR_sched_getscheduler 157 | ||
| 166 | #define __NR_sched_yield 158 | ||
| 167 | #define __NR_sched_get_priority_max 159 | ||
| 168 | #define __NR_sched_get_priority_min 160 | ||
| 169 | #define __NR_sched_rr_get_interval 161 | ||
| 170 | #define __NR_nanosleep 162 | ||
| 171 | #define __NR_mremap 163 | ||
| 172 | #define __NR_setresuid 164 | ||
| 173 | #define __NR_getresuid 165 | ||
| 174 | #define __NR_getpagesize 166 | ||
| 175 | #define __NR_query_module 167 | ||
| 176 | #define __NR_poll 168 | ||
| 177 | #define __NR_nfsservctl 169 | ||
| 178 | #define __NR_setresgid 170 | ||
| 179 | #define __NR_getresgid 171 | ||
| 180 | #define __NR_prctl 172 | ||
| 181 | #define __NR_rt_sigreturn 173 | ||
| 182 | #define __NR_rt_sigaction 174 | ||
| 183 | #define __NR_rt_sigprocmask 175 | ||
| 184 | #define __NR_rt_sigpending 176 | ||
| 185 | #define __NR_rt_sigtimedwait 177 | ||
| 186 | #define __NR_rt_sigqueueinfo 178 | ||
| 187 | #define __NR_rt_sigsuspend 179 | ||
| 188 | #define __NR_pread64 180 | ||
| 189 | #define __NR_pwrite64 181 | ||
| 190 | #define __NR_lchown 182 | ||
| 191 | #define __NR_getcwd 183 | ||
| 192 | #define __NR_capget 184 | ||
| 193 | #define __NR_capset 185 | ||
| 194 | #define __NR_sigaltstack 186 | ||
| 195 | #define __NR_sendfile 187 | ||
| 196 | #define __NR_getpmsg 188 /* some people actually want streams */ | ||
| 197 | #define __NR_putpmsg 189 /* some people actually want streams */ | ||
| 198 | #define __NR_vfork 190 | ||
| 199 | #define __NR_ugetrlimit 191 | ||
| 200 | #define __NR_mmap2 192 | ||
| 201 | #define __NR_truncate64 193 | ||
| 202 | #define __NR_ftruncate64 194 | ||
| 203 | #define __NR_stat64 195 | ||
| 204 | #define __NR_lstat64 196 | ||
| 205 | #define __NR_fstat64 197 | ||
| 206 | #define __NR_chown32 198 | ||
| 207 | #define __NR_getuid32 199 | ||
| 208 | #define __NR_getgid32 200 | ||
| 209 | #define __NR_geteuid32 201 | ||
| 210 | #define __NR_getegid32 202 | ||
| 211 | #define __NR_setreuid32 203 | ||
| 212 | #define __NR_setregid32 204 | ||
| 213 | #define __NR_getgroups32 205 | ||
| 214 | #define __NR_setgroups32 206 | ||
| 215 | #define __NR_fchown32 207 | ||
| 216 | #define __NR_setresuid32 208 | ||
| 217 | #define __NR_getresuid32 209 | ||
| 218 | #define __NR_setresgid32 210 | ||
| 219 | #define __NR_getresgid32 211 | ||
| 220 | #define __NR_lchown32 212 | ||
| 221 | #define __NR_setuid32 213 | ||
| 222 | #define __NR_setgid32 214 | ||
| 223 | #define __NR_setfsuid32 215 | ||
| 224 | #define __NR_setfsgid32 216 | ||
| 225 | #define __NR_pivot_root 217 | ||
| 226 | #define __NR_getdents64 220 | ||
| 227 | #define __NR_gettid 221 | ||
| 228 | #define __NR_tkill 222 | ||
| 229 | #define __NR_setxattr 223 | ||
| 230 | #define __NR_lsetxattr 224 | ||
| 231 | #define __NR_fsetxattr 225 | ||
| 232 | #define __NR_getxattr 226 | ||
| 233 | #define __NR_lgetxattr 227 | ||
| 234 | #define __NR_fgetxattr 228 | ||
| 235 | #define __NR_listxattr 229 | ||
| 236 | #define __NR_llistxattr 230 | ||
| 237 | #define __NR_flistxattr 231 | ||
| 238 | #define __NR_removexattr 232 | ||
| 239 | #define __NR_lremovexattr 233 | ||
| 240 | #define __NR_fremovexattr 234 | ||
| 241 | #define __NR_futex 235 | ||
| 242 | #define __NR_sendfile64 236 | ||
| 243 | #define __NR_mincore 237 | ||
| 244 | #define __NR_madvise 238 | ||
| 245 | #define __NR_fcntl64 239 | ||
| 246 | #define __NR_readahead 240 | ||
| 247 | #define __NR_io_setup 241 | ||
| 248 | #define __NR_io_destroy 242 | ||
| 249 | #define __NR_io_getevents 243 | ||
| 250 | #define __NR_io_submit 244 | ||
| 251 | #define __NR_io_cancel 245 | ||
| 252 | #define __NR_fadvise64 246 | ||
| 253 | #define __NR_exit_group 247 | ||
| 254 | #define __NR_lookup_dcookie 248 | ||
| 255 | #define __NR_epoll_create 249 | ||
| 256 | #define __NR_epoll_ctl 250 | ||
| 257 | #define __NR_epoll_wait 251 | ||
| 258 | #define __NR_remap_file_pages 252 | ||
| 259 | #define __NR_set_tid_address 253 | ||
| 260 | #define __NR_timer_create 254 | ||
| 261 | #define __NR_timer_settime 255 | ||
| 262 | #define __NR_timer_gettime 256 | ||
| 263 | #define __NR_timer_getoverrun 257 | ||
| 264 | #define __NR_timer_delete 258 | ||
| 265 | #define __NR_clock_settime 259 | ||
| 266 | #define __NR_clock_gettime 260 | ||
| 267 | #define __NR_clock_getres 261 | ||
| 268 | #define __NR_clock_nanosleep 262 | ||
| 269 | #define __NR_statfs64 263 | ||
| 270 | #define __NR_fstatfs64 264 | ||
| 271 | #define __NR_tgkill 265 | ||
| 272 | #define __NR_utimes 266 | ||
| 273 | #define __NR_fadvise64_64 267 | ||
| 274 | #define __NR_mbind 268 | ||
| 275 | #define __NR_get_mempolicy 269 | ||
| 276 | #define __NR_set_mempolicy 270 | ||
| 277 | #define __NR_mq_open 271 | ||
| 278 | #define __NR_mq_unlink 272 | ||
| 279 | #define __NR_mq_timedsend 273 | ||
| 280 | #define __NR_mq_timedreceive 274 | ||
| 281 | #define __NR_mq_notify 275 | ||
| 282 | #define __NR_mq_getsetattr 276 | ||
| 283 | #define __NR_waitid 277 | ||
| 284 | #define __NR_vserver 278 | ||
| 285 | #define __NR_add_key 279 | ||
| 286 | #define __NR_request_key 280 | ||
| 287 | #define __NR_keyctl 281 | ||
| 288 | #define __NR_ioprio_set 282 | ||
| 289 | #define __NR_ioprio_get 283 | ||
| 290 | #define __NR_inotify_init 284 | ||
| 291 | #define __NR_inotify_add_watch 285 | ||
| 292 | #define __NR_inotify_rm_watch 286 | ||
| 293 | #define __NR_migrate_pages 287 | ||
| 294 | #define __NR_openat 288 | ||
| 295 | #define __NR_mkdirat 289 | ||
| 296 | #define __NR_mknodat 290 | ||
| 297 | #define __NR_fchownat 291 | ||
| 298 | #define __NR_futimesat 292 | ||
| 299 | #define __NR_fstatat64 293 | ||
| 300 | #define __NR_unlinkat 294 | ||
| 301 | #define __NR_renameat 295 | ||
| 302 | #define __NR_linkat 296 | ||
| 303 | #define __NR_symlinkat 297 | ||
| 304 | #define __NR_readlinkat 298 | ||
| 305 | #define __NR_fchmodat 299 | ||
| 306 | #define __NR_faccessat 300 | ||
| 307 | #define __NR_pselect6 301 | ||
| 308 | #define __NR_ppoll 302 | ||
| 309 | #define __NR_unshare 303 | ||
| 310 | #define __NR_set_robust_list 304 | ||
| 311 | #define __NR_get_robust_list 305 | ||
| 312 | #define __NR_splice 306 | ||
| 313 | #define __NR_sync_file_range 307 | ||
| 314 | #define __NR_tee 308 | ||
| 315 | #define __NR_vmsplice 309 | ||
| 316 | #define __NR_move_pages 310 | ||
| 317 | #define __NR_sched_setaffinity 311 | ||
| 318 | #define __NR_sched_getaffinity 312 | ||
| 319 | #define __NR_kexec_load 313 | ||
| 320 | #define __NR_getcpu 314 | ||
| 321 | #define __NR_epoll_pwait 315 | ||
| 322 | #define __NR_utimensat 316 | ||
| 323 | #define __NR_signalfd 317 | ||
| 324 | #define __NR_timerfd_create 318 | ||
| 325 | #define __NR_eventfd 319 | ||
| 326 | #define __NR_fallocate 320 | ||
| 327 | #define __NR_timerfd_settime 321 | ||
| 328 | #define __NR_timerfd_gettime 322 | ||
| 329 | #define __NR_signalfd4 323 | ||
| 330 | #define __NR_eventfd2 324 | ||
| 331 | #define __NR_epoll_create1 325 | ||
| 332 | #define __NR_dup3 326 | ||
| 333 | #define __NR_pipe2 327 | ||
| 334 | #define __NR_inotify_init1 328 | ||
| 335 | |||
| 336 | #ifdef __KERNEL__ | ||
| 337 | |||
| 338 | #define NR_syscalls 329 | ||
| 339 | |||
| 340 | #define __ARCH_WANT_IPC_PARSE_VERSION | ||
| 341 | #define __ARCH_WANT_OLD_READDIR | ||
| 342 | #define __ARCH_WANT_OLD_STAT | ||
| 343 | #define __ARCH_WANT_STAT64 | ||
| 344 | #define __ARCH_WANT_SYS_ALARM | ||
| 345 | #define __ARCH_WANT_SYS_GETHOSTNAME | ||
| 346 | #define __ARCH_WANT_SYS_PAUSE | ||
| 347 | #define __ARCH_WANT_SYS_SGETMASK | ||
| 348 | #define __ARCH_WANT_SYS_SIGNAL | ||
| 349 | #define __ARCH_WANT_SYS_TIME | ||
| 350 | #define __ARCH_WANT_SYS_UTIME | ||
| 351 | #define __ARCH_WANT_SYS_WAITPID | ||
| 352 | #define __ARCH_WANT_SYS_SOCKETCALL | ||
| 353 | #define __ARCH_WANT_SYS_FADVISE64 | ||
| 354 | #define __ARCH_WANT_SYS_GETPGRP | ||
| 355 | #define __ARCH_WANT_SYS_LLSEEK | ||
| 356 | #define __ARCH_WANT_SYS_NICE | ||
| 357 | #define __ARCH_WANT_SYS_OLD_GETRLIMIT | ||
| 358 | #define __ARCH_WANT_SYS_OLDUMOUNT | ||
| 359 | #define __ARCH_WANT_SYS_SIGPENDING | ||
| 360 | #define __ARCH_WANT_SYS_SIGPROCMASK | ||
| 361 | #define __ARCH_WANT_SYS_RT_SIGACTION | ||
| 362 | |||
| 363 | /* | ||
| 364 | * "Conditional" syscalls | ||
| 365 | * | ||
| 366 | * What we want is __attribute__((weak,alias("sys_ni_syscall"))), | ||
| 367 | * but it doesn't work on all toolchains, so we just do it by hand | ||
| 368 | */ | ||
| 369 | #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") | ||
| 370 | |||
| 371 | #endif /* __KERNEL__ */ | ||
| 372 | #endif /* _ASM_M68K_UNISTD_H_ */ | ||
diff --git a/arch/m68k/include/asm/unistd_mm.h b/arch/m68k/include/asm/unistd_mm.h deleted file mode 100644 index 3c19027331fa..000000000000 --- a/arch/m68k/include/asm/unistd_mm.h +++ /dev/null | |||
| @@ -1,372 +0,0 @@ | |||
| 1 | #ifndef _ASM_M68K_UNISTD_H_ | ||
| 2 | #define _ASM_M68K_UNISTD_H_ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file contains the system call numbers. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #define __NR_restart_syscall 0 | ||
| 9 | #define __NR_exit 1 | ||
| 10 | #define __NR_fork 2 | ||
| 11 | #define __NR_read 3 | ||
| 12 | #define __NR_write 4 | ||
| 13 | #define __NR_open 5 | ||
| 14 | #define __NR_close 6 | ||
| 15 | #define __NR_waitpid 7 | ||
| 16 | #define __NR_creat 8 | ||
| 17 | #define __NR_link 9 | ||
| 18 | #define __NR_unlink 10 | ||
| 19 | #define __NR_execve 11 | ||
| 20 | #define __NR_chdir 12 | ||
| 21 | #define __NR_time 13 | ||
| 22 | #define __NR_mknod 14 | ||
| 23 | #define __NR_chmod 15 | ||
| 24 | #define __NR_chown 16 | ||
| 25 | #define __NR_break 17 | ||
| 26 | #define __NR_oldstat 18 | ||
| 27 | #define __NR_lseek 19 | ||
| 28 | #define __NR_getpid 20 | ||
| 29 | #define __NR_mount 21 | ||
| 30 | #define __NR_umount 22 | ||
| 31 | #define __NR_setuid 23 | ||
| 32 | #define __NR_getuid 24 | ||
| 33 | #define __NR_stime 25 | ||
| 34 | #define __NR_ptrace 26 | ||
| 35 | #define __NR_alarm 27 | ||
| 36 | #define __NR_oldfstat 28 | ||
| 37 | #define __NR_pause 29 | ||
| 38 | #define __NR_utime 30 | ||
| 39 | #define __NR_stty 31 | ||
| 40 | #define __NR_gtty 32 | ||
| 41 | #define __NR_access 33 | ||
| 42 | #define __NR_nice 34 | ||
| 43 | #define __NR_ftime 35 | ||
| 44 | #define __NR_sync 36 | ||
| 45 | #define __NR_kill 37 | ||
| 46 | #define __NR_rename 38 | ||
| 47 | #define __NR_mkdir 39 | ||
| 48 | #define __NR_rmdir 40 | ||
| 49 | #define __NR_dup 41 | ||
| 50 | #define __NR_pipe 42 | ||
| 51 | #define __NR_times 43 | ||
| 52 | #define __NR_prof 44 | ||
| 53 | #define __NR_brk 45 | ||
| 54 | #define __NR_setgid 46 | ||
| 55 | #define __NR_getgid 47 | ||
| 56 | #define __NR_signal 48 | ||
| 57 | #define __NR_geteuid 49 | ||
| 58 | #define __NR_getegid 50 | ||
| 59 | #define __NR_acct 51 | ||
| 60 | #define __NR_umount2 52 | ||
| 61 | #define __NR_lock 53 | ||
| 62 | #define __NR_ioctl 54 | ||
| 63 | #define __NR_fcntl 55 | ||
| 64 | #define __NR_mpx 56 | ||
| 65 | #define __NR_setpgid 57 | ||
| 66 | #define __NR_ulimit 58 | ||
| 67 | #define __NR_oldolduname 59 | ||
| 68 | #define __NR_umask 60 | ||
| 69 | #define __NR_chroot 61 | ||
| 70 | #define __NR_ustat 62 | ||
| 71 | #define __NR_dup2 63 | ||
| 72 | #define __NR_getppid 64 | ||
| 73 | #define __NR_getpgrp 65 | ||
| 74 | #define __NR_setsid 66 | ||
| 75 | #define __NR_sigaction 67 | ||
| 76 | #define __NR_sgetmask 68 | ||
| 77 | #define __NR_ssetmask 69 | ||
| 78 | #define __NR_setreuid 70 | ||
| 79 | #define __NR_setregid 71 | ||
| 80 | #define __NR_sigsuspend 72 | ||
| 81 | #define __NR_sigpending 73 | ||
| 82 | #define __NR_sethostname 74 | ||
| 83 | #define __NR_setrlimit 75 | ||
| 84 | #define __NR_getrlimit 76 | ||
| 85 | #define __NR_getrusage 77 | ||
| 86 | #define __NR_gettimeofday 78 | ||
| 87 | #define __NR_settimeofday 79 | ||
| 88 | #define __NR_getgroups 80 | ||
| 89 | #define __NR_setgroups 81 | ||
| 90 | #define __NR_select 82 | ||
| 91 | #define __NR_symlink 83 | ||
| 92 | #define __NR_oldlstat 84 | ||
| 93 | #define __NR_readlink 85 | ||
| 94 | #define __NR_uselib 86 | ||
| 95 | #define __NR_swapon 87 | ||
| 96 | #define __NR_reboot 88 | ||
| 97 | #define __NR_readdir 89 | ||
| 98 | #define __NR_mmap 90 | ||
| 99 | #define __NR_munmap 91 | ||
| 100 | #define __NR_truncate 92 | ||
| 101 | #define __NR_ftruncate 93 | ||
| 102 | #define __NR_fchmod 94 | ||
| 103 | #define __NR_fchown 95 | ||
| 104 | #define __NR_getpriority 96 | ||
| 105 | #define __NR_setpriority 97 | ||
| 106 | #define __NR_profil 98 | ||
| 107 | #define __NR_statfs 99 | ||
| 108 | #define __NR_fstatfs 100 | ||
| 109 | #define __NR_ioperm 101 | ||
| 110 | #define __NR_socketcall 102 | ||
| 111 | #define __NR_syslog 103 | ||
| 112 | #define __NR_setitimer 104 | ||
| 113 | #define __NR_getitimer 105 | ||
| 114 | #define __NR_stat 106 | ||
| 115 | #define __NR_lstat 107 | ||
| 116 | #define __NR_fstat 108 | ||
| 117 | #define __NR_olduname 109 | ||
| 118 | #define __NR_iopl /* 110 */ not supported | ||
| 119 | #define __NR_vhangup 111 | ||
| 120 | #define __NR_idle /* 112 */ Obsolete | ||
| 121 | #define __NR_vm86 /* 113 */ not supported | ||
| 122 | #define __NR_wait4 114 | ||
| 123 | #define __NR_swapoff 115 | ||
| 124 | #define __NR_sysinfo 116 | ||
| 125 | #define __NR_ipc 117 | ||
| 126 | #define __NR_fsync 118 | ||
| 127 | #define __NR_sigreturn 119 | ||
| 128 | #define __NR_clone 120 | ||
| 129 | #define __NR_setdomainname 121 | ||
| 130 | #define __NR_uname 122 | ||
| 131 | #define __NR_cacheflush 123 | ||
| 132 | #define __NR_adjtimex 124 | ||
| 133 | #define __NR_mprotect 125 | ||
| 134 | #define __NR_sigprocmask 126 | ||
| 135 | #define __NR_create_module 127 | ||
| 136 | #define __NR_init_module 128 | ||
| 137 | #define __NR_delete_module 129 | ||
| 138 | #define __NR_get_kernel_syms 130 | ||
| 139 | #define __NR_quotactl 131 | ||
| 140 | #define __NR_getpgid 132 | ||
| 141 | #define __NR_fchdir 133 | ||
| 142 | #define __NR_bdflush 134 | ||
| 143 | #define __NR_sysfs 135 | ||
| 144 | #define __NR_personality 136 | ||
| 145 | #define __NR_afs_syscall 137 /* Syscall for Andrew File System */ | ||
| 146 | #define __NR_setfsuid 138 | ||
| 147 | #define __NR_setfsgid 139 | ||
| 148 | #define __NR__llseek 140 | ||
| 149 | #define __NR_getdents 141 | ||
| 150 | #define __NR__newselect 142 | ||
| 151 | #define __NR_flock 143 | ||
| 152 | #define __NR_msync 144 | ||
| 153 | #define __NR_readv 145 | ||
| 154 | #define __NR_writev 146 | ||
| 155 | #define __NR_getsid 147 | ||
| 156 | #define __NR_fdatasync 148 | ||
| 157 | #define __NR__sysctl 149 | ||
| 158 | #define __NR_mlock 150 | ||
| 159 | #define __NR_munlock 151 | ||
| 160 | #define __NR_mlockall 152 | ||
| 161 | #define __NR_munlockall 153 | ||
| 162 | #define __NR_sched_setparam 154 | ||
| 163 | #define __NR_sched_getparam 155 | ||
| 164 | #define __NR_sched_setscheduler 156 | ||
| 165 | #define __NR_sched_getscheduler 157 | ||
| 166 | #define __NR_sched_yield 158 | ||
| 167 | #define __NR_sched_get_priority_max 159 | ||
| 168 | #define __NR_sched_get_priority_min 160 | ||
| 169 | #define __NR_sched_rr_get_interval 161 | ||
| 170 | #define __NR_nanosleep 162 | ||
| 171 | #define __NR_mremap 163 | ||
| 172 | #define __NR_setresuid 164 | ||
| 173 | #define __NR_getresuid 165 | ||
| 174 | #define __NR_getpagesize 166 | ||
| 175 | #define __NR_query_module 167 | ||
| 176 | #define __NR_poll 168 | ||
| 177 | #define __NR_nfsservctl 169 | ||
| 178 | #define __NR_setresgid 170 | ||
| 179 | #define __NR_getresgid 171 | ||
| 180 | #define __NR_prctl 172 | ||
| 181 | #define __NR_rt_sigreturn 173 | ||
| 182 | #define __NR_rt_sigaction 174 | ||
| 183 | #define __NR_rt_sigprocmask 175 | ||
| 184 | #define __NR_rt_sigpending 176 | ||
| 185 | #define __NR_rt_sigtimedwait 177 | ||
| 186 | #define __NR_rt_sigqueueinfo 178 | ||
| 187 | #define __NR_rt_sigsuspend 179 | ||
| 188 | #define __NR_pread64 180 | ||
| 189 | #define __NR_pwrite64 181 | ||
| 190 | #define __NR_lchown 182 | ||
| 191 | #define __NR_getcwd 183 | ||
| 192 | #define __NR_capget 184 | ||
| 193 | #define __NR_capset 185 | ||
| 194 | #define __NR_sigaltstack 186 | ||
| 195 | #define __NR_sendfile 187 | ||
| 196 | #define __NR_getpmsg 188 /* some people actually want streams */ | ||
| 197 | #define __NR_putpmsg 189 /* some people actually want streams */ | ||
| 198 | #define __NR_vfork 190 | ||
| 199 | #define __NR_ugetrlimit 191 | ||
| 200 | #define __NR_mmap2 192 | ||
| 201 | #define __NR_truncate64 193 | ||
| 202 | #define __NR_ftruncate64 194 | ||
| 203 | #define __NR_stat64 195 | ||
| 204 | #define __NR_lstat64 196 | ||
| 205 | #define __NR_fstat64 197 | ||
| 206 | #define __NR_chown32 198 | ||
| 207 | #define __NR_getuid32 199 | ||
| 208 | #define __NR_getgid32 200 | ||
| 209 | #define __NR_geteuid32 201 | ||
| 210 | #define __NR_getegid32 202 | ||
| 211 | #define __NR_setreuid32 203 | ||
| 212 | #define __NR_setregid32 204 | ||
| 213 | #define __NR_getgroups32 205 | ||
| 214 | #define __NR_setgroups32 206 | ||
| 215 | #define __NR_fchown32 207 | ||
| 216 | #define __NR_setresuid32 208 | ||
| 217 | #define __NR_getresuid32 209 | ||
| 218 | #define __NR_setresgid32 210 | ||
| 219 | #define __NR_getresgid32 211 | ||
| 220 | #define __NR_lchown32 212 | ||
| 221 | #define __NR_setuid32 213 | ||
| 222 | #define __NR_setgid32 214 | ||
| 223 | #define __NR_setfsuid32 215 | ||
| 224 | #define __NR_setfsgid32 216 | ||
| 225 | #define __NR_pivot_root 217 | ||
| 226 | #define __NR_getdents64 220 | ||
| 227 | #define __NR_gettid 221 | ||
| 228 | #define __NR_tkill 222 | ||
| 229 | #define __NR_setxattr 223 | ||
| 230 | #define __NR_lsetxattr 224 | ||
| 231 | #define __NR_fsetxattr 225 | ||
| 232 | #define __NR_getxattr 226 | ||
| 233 | #define __NR_lgetxattr 227 | ||
| 234 | #define __NR_fgetxattr 228 | ||
| 235 | #define __NR_listxattr 229 | ||
| 236 | #define __NR_llistxattr 230 | ||
| 237 | #define __NR_flistxattr 231 | ||
| 238 | #define __NR_removexattr 232 | ||
| 239 | #define __NR_lremovexattr 233 | ||
| 240 | #define __NR_fremovexattr 234 | ||
| 241 | #define __NR_futex 235 | ||
| 242 | #define __NR_sendfile64 236 | ||
| 243 | #define __NR_mincore 237 | ||
| 244 | #define __NR_madvise 238 | ||
| 245 | #define __NR_fcntl64 239 | ||
| 246 | #define __NR_readahead 240 | ||
| 247 | #define __NR_io_setup 241 | ||
| 248 | #define __NR_io_destroy 242 | ||
| 249 | #define __NR_io_getevents 243 | ||
| 250 | #define __NR_io_submit 244 | ||
| 251 | #define __NR_io_cancel 245 | ||
| 252 | #define __NR_fadvise64 246 | ||
| 253 | #define __NR_exit_group 247 | ||
| 254 | #define __NR_lookup_dcookie 248 | ||
| 255 | #define __NR_epoll_create 249 | ||
| 256 | #define __NR_epoll_ctl 250 | ||
| 257 | #define __NR_epoll_wait 251 | ||
| 258 | #define __NR_remap_file_pages 252 | ||
| 259 | #define __NR_set_tid_address 253 | ||
| 260 | #define __NR_timer_create 254 | ||
| 261 | #define __NR_timer_settime 255 | ||
| 262 | #define __NR_timer_gettime 256 | ||
| 263 | #define __NR_timer_getoverrun 257 | ||
| 264 | #define __NR_timer_delete 258 | ||
| 265 | #define __NR_clock_settime 259 | ||
| 266 | #define __NR_clock_gettime 260 | ||
| 267 | #define __NR_clock_getres 261 | ||
| 268 | #define __NR_clock_nanosleep 262 | ||
| 269 | #define __NR_statfs64 263 | ||
| 270 | #define __NR_fstatfs64 264 | ||
| 271 | #define __NR_tgkill 265 | ||
| 272 | #define __NR_utimes 266 | ||
| 273 | #define __NR_fadvise64_64 267 | ||
| 274 | #define __NR_mbind 268 | ||
| 275 | #define __NR_get_mempolicy 269 | ||
| 276 | #define __NR_set_mempolicy 270 | ||
| 277 | #define __NR_mq_open 271 | ||
| 278 | #define __NR_mq_unlink 272 | ||
| 279 | #define __NR_mq_timedsend 273 | ||
| 280 | #define __NR_mq_timedreceive 274 | ||
| 281 | #define __NR_mq_notify 275 | ||
| 282 | #define __NR_mq_getsetattr 276 | ||
| 283 | #define __NR_waitid 277 | ||
| 284 | #define __NR_vserver 278 | ||
| 285 | #define __NR_add_key 279 | ||
| 286 | #define __NR_request_key 280 | ||
| 287 | #define __NR_keyctl 281 | ||
| 288 | #define __NR_ioprio_set 282 | ||
| 289 | #define __NR_ioprio_get 283 | ||
| 290 | #define __NR_inotify_init 284 | ||
| 291 | #define __NR_inotify_add_watch 285 | ||
| 292 | #define __NR_inotify_rm_watch 286 | ||
| 293 | #define __NR_migrate_pages 287 | ||
| 294 | #define __NR_openat 288 | ||
| 295 | #define __NR_mkdirat 289 | ||
| 296 | #define __NR_mknodat 290 | ||
| 297 | #define __NR_fchownat 291 | ||
| 298 | #define __NR_futimesat 292 | ||
| 299 | #define __NR_fstatat64 293 | ||
| 300 | #define __NR_unlinkat 294 | ||
| 301 | #define __NR_renameat 295 | ||
| 302 | #define __NR_linkat 296 | ||
| 303 | #define __NR_symlinkat 297 | ||
| 304 | #define __NR_readlinkat 298 | ||
| 305 | #define __NR_fchmodat 299 | ||
| 306 | #define __NR_faccessat 300 | ||
| 307 | #define __NR_pselect6 301 | ||
| 308 | #define __NR_ppoll 302 | ||
| 309 | #define __NR_unshare 303 | ||
| 310 | #define __NR_set_robust_list 304 | ||
| 311 | #define __NR_get_robust_list 305 | ||
| 312 | #define __NR_splice 306 | ||
| 313 | #define __NR_sync_file_range 307 | ||
| 314 | #define __NR_tee 308 | ||
| 315 | #define __NR_vmsplice 309 | ||
| 316 | #define __NR_move_pages 310 | ||
| 317 | #define __NR_sched_setaffinity 311 | ||
| 318 | #define __NR_sched_getaffinity 312 | ||
| 319 | #define __NR_kexec_load 313 | ||
| 320 | #define __NR_getcpu 314 | ||
| 321 | #define __NR_epoll_pwait 315 | ||
| 322 | #define __NR_utimensat 316 | ||
| 323 | #define __NR_signalfd 317 | ||
| 324 | #define __NR_timerfd_create 318 | ||
| 325 | #define __NR_eventfd 319 | ||
| 326 | #define __NR_fallocate 320 | ||
| 327 | #define __NR_timerfd_settime 321 | ||
| 328 | #define __NR_timerfd_gettime 322 | ||
| 329 | #define __NR_signalfd4 323 | ||
| 330 | #define __NR_eventfd2 324 | ||
| 331 | #define __NR_epoll_create1 325 | ||
| 332 | #define __NR_dup3 326 | ||
| 333 | #define __NR_pipe2 327 | ||
| 334 | #define __NR_inotify_init1 328 | ||
| 335 | |||
| 336 | #ifdef __KERNEL__ | ||
| 337 | |||
| 338 | #define NR_syscalls 329 | ||
| 339 | |||
| 340 | #define __ARCH_WANT_IPC_PARSE_VERSION | ||
| 341 | #define __ARCH_WANT_OLD_READDIR | ||
| 342 | #define __ARCH_WANT_OLD_STAT | ||
| 343 | #define __ARCH_WANT_STAT64 | ||
| 344 | #define __ARCH_WANT_SYS_ALARM | ||
| 345 | #define __ARCH_WANT_SYS_GETHOSTNAME | ||
| 346 | #define __ARCH_WANT_SYS_PAUSE | ||
| 347 | #define __ARCH_WANT_SYS_SGETMASK | ||
| 348 | #define __ARCH_WANT_SYS_SIGNAL | ||
| 349 | #define __ARCH_WANT_SYS_TIME | ||
| 350 | #define __ARCH_WANT_SYS_UTIME | ||
| 351 | #define __ARCH_WANT_SYS_WAITPID | ||
| 352 | #define __ARCH_WANT_SYS_SOCKETCALL | ||
| 353 | #define __ARCH_WANT_SYS_FADVISE64 | ||
| 354 | #define __ARCH_WANT_SYS_GETPGRP | ||
| 355 | #define __ARCH_WANT_SYS_LLSEEK | ||
| 356 | #define __ARCH_WANT_SYS_NICE | ||
| 357 | #define __ARCH_WANT_SYS_OLD_GETRLIMIT | ||
| 358 | #define __ARCH_WANT_SYS_OLDUMOUNT | ||
| 359 | #define __ARCH_WANT_SYS_SIGPENDING | ||
| 360 | #define __ARCH_WANT_SYS_SIGPROCMASK | ||
| 361 | #define __ARCH_WANT_SYS_RT_SIGACTION | ||
| 362 | |||
| 363 | /* | ||
| 364 | * "Conditional" syscalls | ||
| 365 | * | ||
| 366 | * What we want is __attribute__((weak,alias("sys_ni_syscall"))), | ||
| 367 | * but it doesn't work on all toolchains, so we just do it by hand | ||
| 368 | */ | ||
| 369 | #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") | ||
| 370 | |||
| 371 | #endif /* __KERNEL__ */ | ||
| 372 | #endif /* _ASM_M68K_UNISTD_H_ */ | ||
diff --git a/arch/m68k/include/asm/unistd_no.h b/arch/m68k/include/asm/unistd_no.h deleted file mode 100644 index b034a2f7b444..000000000000 --- a/arch/m68k/include/asm/unistd_no.h +++ /dev/null | |||
| @@ -1,372 +0,0 @@ | |||
| 1 | #ifndef _ASM_M68K_UNISTD_H_ | ||
| 2 | #define _ASM_M68K_UNISTD_H_ | ||
| 3 | |||
| 4 | /* | ||
| 5 | * This file contains the system call numbers. | ||
| 6 | */ | ||
| 7 | |||
| 8 | #define __NR_restart_syscall 0 | ||
| 9 | #define __NR_exit 1 | ||
| 10 | #define __NR_fork 2 | ||
| 11 | #define __NR_read 3 | ||
| 12 | #define __NR_write 4 | ||
| 13 | #define __NR_open 5 | ||
| 14 | #define __NR_close 6 | ||
| 15 | #define __NR_waitpid 7 | ||
| 16 | #define __NR_creat 8 | ||
| 17 | #define __NR_link 9 | ||
| 18 | #define __NR_unlink 10 | ||
| 19 | #define __NR_execve 11 | ||
| 20 | #define __NR_chdir 12 | ||
| 21 | #define __NR_time 13 | ||
| 22 | #define __NR_mknod 14 | ||
| 23 | #define __NR_chmod 15 | ||
| 24 | #define __NR_chown 16 | ||
| 25 | #define __NR_break 17 | ||
| 26 | #define __NR_oldstat 18 | ||
| 27 | #define __NR_lseek 19 | ||
| 28 | #define __NR_getpid 20 | ||
| 29 | #define __NR_mount 21 | ||
| 30 | #define __NR_umount 22 | ||
| 31 | #define __NR_setuid 23 | ||
| 32 | #define __NR_getuid 24 | ||
| 33 | #define __NR_stime 25 | ||
| 34 | #define __NR_ptrace 26 | ||
| 35 | #define __NR_alarm 27 | ||
| 36 | #define __NR_oldfstat 28 | ||
| 37 | #define __NR_pause 29 | ||
| 38 | #define __NR_utime 30 | ||
| 39 | #define __NR_stty 31 | ||
| 40 | #define __NR_gtty 32 | ||
| 41 | #define __NR_access 33 | ||
| 42 | #define __NR_nice 34 | ||
| 43 | #define __NR_ftime 35 | ||
| 44 | #define __NR_sync 36 | ||
| 45 | #define __NR_kill 37 | ||
| 46 | #define __NR_rename 38 | ||
| 47 | #define __NR_mkdir 39 | ||
| 48 | #define __NR_rmdir 40 | ||
| 49 | #define __NR_dup 41 | ||
| 50 | #define __NR_pipe 42 | ||
| 51 | #define __NR_times 43 | ||
| 52 | #define __NR_prof 44 | ||
| 53 | #define __NR_brk 45 | ||
| 54 | #define __NR_setgid 46 | ||
| 55 | #define __NR_getgid 47 | ||
| 56 | #define __NR_signal 48 | ||
| 57 | #define __NR_geteuid 49 | ||
| 58 | #define __NR_getegid 50 | ||
| 59 | #define __NR_acct 51 | ||
| 60 | #define __NR_umount2 52 | ||
| 61 | #define __NR_lock 53 | ||
| 62 | #define __NR_ioctl 54 | ||
| 63 | #define __NR_fcntl 55 | ||
| 64 | #define __NR_mpx 56 | ||
| 65 | #define __NR_setpgid 57 | ||
| 66 | #define __NR_ulimit 58 | ||
| 67 | #define __NR_oldolduname 59 | ||
| 68 | #define __NR_umask 60 | ||
| 69 | #define __NR_chroot 61 | ||
| 70 | #define __NR_ustat 62 | ||
| 71 | #define __NR_dup2 63 | ||
| 72 | #define __NR_getppid 64 | ||
| 73 | #define __NR_getpgrp 65 | ||
| 74 | #define __NR_setsid 66 | ||
| 75 | #define __NR_sigaction 67 | ||
| 76 | #define __NR_sgetmask 68 | ||
| 77 | #define __NR_ssetmask 69 | ||
| 78 | #define __NR_setreuid 70 | ||
| 79 | #define __NR_setregid 71 | ||
| 80 | #define __NR_sigsuspend 72 | ||
| 81 | #define __NR_sigpending 73 | ||
| 82 | #define __NR_sethostname 74 | ||
| 83 | #define __NR_setrlimit 75 | ||
| 84 | #define __NR_getrlimit 76 | ||
| 85 | #define __NR_getrusage 77 | ||
| 86 | #define __NR_gettimeofday 78 | ||
| 87 | #define __NR_settimeofday 79 | ||
| 88 | #define __NR_getgroups 80 | ||
| 89 | #define __NR_setgroups 81 | ||
| 90 | #define __NR_select 82 | ||
| 91 | #define __NR_symlink 83 | ||
| 92 | #define __NR_oldlstat 84 | ||
| 93 | #define __NR_readlink 85 | ||
| 94 | #define __NR_uselib 86 | ||
| 95 | #define __NR_swapon 87 | ||
| 96 | #define __NR_reboot 88 | ||
| 97 | #define __NR_readdir 89 | ||
| 98 | #define __NR_mmap 90 | ||
| 99 | #define __NR_munmap 91 | ||
| 100 | #define __NR_truncate 92 | ||
| 101 | #define __NR_ftruncate 93 | ||
| 102 | #define __NR_fchmod 94 | ||
| 103 | #define __NR_fchown 95 | ||
| 104 | #define __NR_getpriority 96 | ||
| 105 | #define __NR_setpriority 97 | ||
| 106 | #define __NR_profil 98 | ||
| 107 | #define __NR_statfs 99 | ||
| 108 | #define __NR_fstatfs 100 | ||
| 109 | #define __NR_ioperm 101 | ||
| 110 | #define __NR_socketcall 102 | ||
| 111 | #define __NR_syslog 103 | ||
| 112 | #define __NR_setitimer 104 | ||
| 113 | #define __NR_getitimer 105 | ||
| 114 | #define __NR_stat 106 | ||
| 115 | #define __NR_lstat 107 | ||
| 116 | #define __NR_fstat 108 | ||
| 117 | #define __NR_olduname 109 | ||
| 118 | #define __NR_iopl /* 110 */ not supported | ||
| 119 | #define __NR_vhangup 111 | ||
| 120 | #define __NR_idle /* 112 */ Obsolete | ||
| 121 | #define __NR_vm86 /* 113 */ not supported | ||
| 122 | #define __NR_wait4 114 | ||
| 123 | #define __NR_swapoff 115 | ||
| 124 | #define __NR_sysinfo 116 | ||
| 125 | #define __NR_ipc 117 | ||
| 126 | #define __NR_fsync 118 | ||
| 127 | #define __NR_sigreturn 119 | ||
| 128 | #define __NR_clone 120 | ||
| 129 | #define __NR_setdomainname 121 | ||
| 130 | #define __NR_uname 122 | ||
| 131 | #define __NR_cacheflush 123 | ||
| 132 | #define __NR_adjtimex 124 | ||
| 133 | #define __NR_mprotect 125 | ||
| 134 | #define __NR_sigprocmask 126 | ||
| 135 | #define __NR_create_module 127 | ||
| 136 | #define __NR_init_module 128 | ||
| 137 | #define __NR_delete_module 129 | ||
| 138 | #define __NR_get_kernel_syms 130 | ||
| 139 | #define __NR_quotactl 131 | ||
| 140 | #define __NR_getpgid 132 | ||
| 141 | #define __NR_fchdir 133 | ||
| 142 | #define __NR_bdflush 134 | ||
| 143 | #define __NR_sysfs 135 | ||
| 144 | #define __NR_personality 136 | ||
| 145 | #define __NR_afs_syscall 137 /* Syscall for Andrew File System */ | ||
| 146 | #define __NR_setfsuid 138 | ||
| 147 | #define __NR_setfsgid 139 | ||
| 148 | #define __NR__llseek 140 | ||
| 149 | #define __NR_getdents 141 | ||
| 150 | #define __NR__newselect 142 | ||
| 151 | #define __NR_flock 143 | ||
| 152 | #define __NR_msync 144 | ||
| 153 | #define __NR_readv 145 | ||
| 154 | #define __NR_writev 146 | ||
| 155 | #define __NR_getsid 147 | ||
| 156 | #define __NR_fdatasync 148 | ||
| 157 | #define __NR__sysctl 149 | ||
| 158 | #define __NR_mlock 150 | ||
| 159 | #define __NR_munlock 151 | ||
| 160 | #define __NR_mlockall 152 | ||
| 161 | #define __NR_munlockall 153 | ||
| 162 | #define __NR_sched_setparam 154 | ||
| 163 | #define __NR_sched_getparam 155 | ||
| 164 | #define __NR_sched_setscheduler 156 | ||
| 165 | #define __NR_sched_getscheduler 157 | ||
| 166 | #define __NR_sched_yield 158 | ||
| 167 | #define __NR_sched_get_priority_max 159 | ||
| 168 | #define __NR_sched_get_priority_min 160 | ||
| 169 | #define __NR_sched_rr_get_interval 161 | ||
| 170 | #define __NR_nanosleep 162 | ||
| 171 | #define __NR_mremap 163 | ||
| 172 | #define __NR_setresuid 164 | ||
| 173 | #define __NR_getresuid 165 | ||
| 174 | #define __NR_getpagesize 166 | ||
| 175 | #define __NR_query_module 167 | ||
| 176 | #define __NR_poll 168 | ||
| 177 | #define __NR_nfsservctl 169 | ||
| 178 | #define __NR_setresgid 170 | ||
| 179 | #define __NR_getresgid 171 | ||
| 180 | #define __NR_prctl 172 | ||
| 181 | #define __NR_rt_sigreturn 173 | ||
| 182 | #define __NR_rt_sigaction 174 | ||
| 183 | #define __NR_rt_sigprocmask 175 | ||
| 184 | #define __NR_rt_sigpending 176 | ||
| 185 | #define __NR_rt_sigtimedwait 177 | ||
| 186 | #define __NR_rt_sigqueueinfo 178 | ||
| 187 | #define __NR_rt_sigsuspend 179 | ||
| 188 | #define __NR_pread64 180 | ||
| 189 | #define __NR_pwrite64 181 | ||
| 190 | #define __NR_lchown 182 | ||
| 191 | #define __NR_getcwd 183 | ||
| 192 | #define __NR_capget 184 | ||
| 193 | #define __NR_capset 185 | ||
| 194 | #define __NR_sigaltstack 186 | ||
| 195 | #define __NR_sendfile 187 | ||
| 196 | #define __NR_getpmsg 188 /* some people actually want streams */ | ||
| 197 | #define __NR_putpmsg 189 /* some people actually want streams */ | ||
| 198 | #define __NR_vfork 190 | ||
| 199 | #define __NR_ugetrlimit 191 | ||
| 200 | #define __NR_mmap2 192 | ||
| 201 | #define __NR_truncate64 193 | ||
| 202 | #define __NR_ftruncate64 194 | ||
| 203 | #define __NR_stat64 195 | ||
| 204 | #define __NR_lstat64 196 | ||
| 205 | #define __NR_fstat64 197 | ||
| 206 | #define __NR_chown32 198 | ||
| 207 | #define __NR_getuid32 199 | ||
| 208 | #define __NR_getgid32 200 | ||
| 209 | #define __NR_geteuid32 201 | ||
| 210 | #define __NR_getegid32 202 | ||
| 211 | #define __NR_setreuid32 203 | ||
| 212 | #define __NR_setregid32 204 | ||
| 213 | #define __NR_getgroups32 205 | ||
| 214 | #define __NR_setgroups32 206 | ||
| 215 | #define __NR_fchown32 207 | ||
| 216 | #define __NR_setresuid32 208 | ||
| 217 | #define __NR_getresuid32 209 | ||
| 218 | #define __NR_setresgid32 210 | ||
| 219 | #define __NR_getresgid32 211 | ||
| 220 | #define __NR_lchown32 212 | ||
| 221 | #define __NR_setuid32 213 | ||
| 222 | #define __NR_setgid32 214 | ||
| 223 | #define __NR_setfsuid32 215 | ||
| 224 | #define __NR_setfsgid32 216 | ||
| 225 | #define __NR_pivot_root 217 | ||
| 226 | #define __NR_getdents64 220 | ||
| 227 | #define __NR_gettid 221 | ||
| 228 | #define __NR_tkill 222 | ||
| 229 | #define __NR_setxattr 223 | ||
| 230 | #define __NR_lsetxattr 224 | ||
| 231 | #define __NR_fsetxattr 225 | ||
| 232 | #define __NR_getxattr 226 | ||
| 233 | #define __NR_lgetxattr 227 | ||
| 234 | #define __NR_fgetxattr 228 | ||
| 235 | #define __NR_listxattr 229 | ||
| 236 | #define __NR_llistxattr 230 | ||
| 237 | #define __NR_flistxattr 231 | ||
| 238 | #define __NR_removexattr 232 | ||
| 239 | #define __NR_lremovexattr 233 | ||
| 240 | #define __NR_fremovexattr 234 | ||
| 241 | #define __NR_futex 235 | ||
| 242 | #define __NR_sendfile64 236 | ||
| 243 | #define __NR_mincore 237 | ||
| 244 | #define __NR_madvise 238 | ||
| 245 | #define __NR_fcntl64 239 | ||
| 246 | #define __NR_readahead 240 | ||
| 247 | #define __NR_io_setup 241 | ||
| 248 | #define __NR_io_destroy 242 | ||
| 249 | #define __NR_io_getevents 243 | ||
| 250 | #define __NR_io_submit 244 | ||
| 251 | #define __NR_io_cancel 245 | ||
| 252 | #define __NR_fadvise64 246 | ||
| 253 | #define __NR_exit_group 247 | ||
| 254 | #define __NR_lookup_dcookie 248 | ||
| 255 | #define __NR_epoll_create 249 | ||
| 256 | #define __NR_epoll_ctl 250 | ||
| 257 | #define __NR_epoll_wait 251 | ||
| 258 | #define __NR_remap_file_pages 252 | ||
| 259 | #define __NR_set_tid_address 253 | ||
| 260 | #define __NR_timer_create 254 | ||
| 261 | #define __NR_timer_settime 255 | ||
| 262 | #define __NR_timer_gettime 256 | ||
| 263 | #define __NR_timer_getoverrun 257 | ||
| 264 | #define __NR_timer_delete 258 | ||
| 265 | #define __NR_clock_settime 259 | ||
| 266 | #define __NR_clock_gettime 260 | ||
| 267 | #define __NR_clock_getres 261 | ||
| 268 | #define __NR_clock_nanosleep 262 | ||
| 269 | #define __NR_statfs64 263 | ||
| 270 | #define __NR_fstatfs64 264 | ||
| 271 | #define __NR_tgkill 265 | ||
| 272 | #define __NR_utimes 266 | ||
| 273 | #define __NR_fadvise64_64 267 | ||
| 274 | #define __NR_mbind 268 | ||
| 275 | #define __NR_get_mempolicy 269 | ||
| 276 | #define __NR_set_mempolicy 270 | ||
| 277 | #define __NR_mq_open 271 | ||
| 278 | #define __NR_mq_unlink 272 | ||
| 279 | #define __NR_mq_timedsend 273 | ||
| 280 | #define __NR_mq_timedreceive 274 | ||
| 281 | #define __NR_mq_notify 275 | ||
| 282 | #define __NR_mq_getsetattr 276 | ||
| 283 | #define __NR_waitid 277 | ||
| 284 | #define __NR_vserver 278 | ||
| 285 | #define __NR_add_key 279 | ||
| 286 | #define __NR_request_key 280 | ||
| 287 | #define __NR_keyctl 281 | ||
| 288 | #define __NR_ioprio_set 282 | ||
| 289 | #define __NR_ioprio_get 283 | ||
| 290 | #define __NR_inotify_init 284 | ||
| 291 | #define __NR_inotify_add_watch 285 | ||
| 292 | #define __NR_inotify_rm_watch 286 | ||
| 293 | #define __NR_migrate_pages 287 | ||
| 294 | #define __NR_openat 288 | ||
| 295 | #define __NR_mkdirat 289 | ||
| 296 | #define __NR_mknodat 290 | ||
| 297 | #define __NR_fchownat 291 | ||
| 298 | #define __NR_futimesat 292 | ||
| 299 | #define __NR_fstatat64 293 | ||
| 300 | #define __NR_unlinkat 294 | ||
| 301 | #define __NR_renameat 295 | ||
| 302 | #define __NR_linkat 296 | ||
| 303 | #define __NR_symlinkat 297 | ||
| 304 | #define __NR_readlinkat 298 | ||
| 305 | #define __NR_fchmodat 299 | ||
| 306 | #define __NR_faccessat 300 | ||
| 307 | #define __NR_pselect6 301 | ||
| 308 | #define __NR_ppoll 302 | ||
| 309 | #define __NR_unshare 303 | ||
| 310 | #define __NR_set_robust_list 304 | ||
| 311 | #define __NR_get_robust_list 305 | ||
| 312 | #define __NR_splice 306 | ||
| 313 | #define __NR_sync_file_range 307 | ||
| 314 | #define __NR_tee 308 | ||
| 315 | #define __NR_vmsplice 309 | ||
| 316 | #define __NR_move_pages 310 | ||
| 317 | #define __NR_sched_setaffinity 311 | ||
| 318 | #define __NR_sched_getaffinity 312 | ||
| 319 | #define __NR_kexec_load 313 | ||
| 320 | #define __NR_getcpu 314 | ||
| 321 | #define __NR_epoll_pwait 315 | ||
| 322 | #define __NR_utimensat 316 | ||
| 323 | #define __NR_signalfd 317 | ||
| 324 | #define __NR_timerfd_create 318 | ||
| 325 | #define __NR_eventfd 319 | ||
| 326 | #define __NR_fallocate 320 | ||
| 327 | #define __NR_timerfd_settime 321 | ||
| 328 | #define __NR_timerfd_gettime 322 | ||
| 329 | #define __NR_signalfd4 323 | ||
| 330 | #define __NR_eventfd2 324 | ||
| 331 | #define __NR_epoll_create1 325 | ||
| 332 | #define __NR_dup3 326 | ||
| 333 | #define __NR_pipe2 327 | ||
| 334 | #define __NR_inotify_init1 328 | ||
| 335 | |||
| 336 | #ifdef __KERNEL__ | ||
| 337 | |||
| 338 | #define NR_syscalls 329 | ||
| 339 | |||
| 340 | #define __ARCH_WANT_IPC_PARSE_VERSION | ||
| 341 | #define __ARCH_WANT_OLD_READDIR | ||
| 342 | #define __ARCH_WANT_OLD_STAT | ||
| 343 | #define __ARCH_WANT_STAT64 | ||
| 344 | #define __ARCH_WANT_SYS_ALARM | ||
| 345 | #define __ARCH_WANT_SYS_GETHOSTNAME | ||
| 346 | #define __ARCH_WANT_SYS_PAUSE | ||
| 347 | #define __ARCH_WANT_SYS_SGETMASK | ||
| 348 | #define __ARCH_WANT_SYS_SIGNAL | ||
| 349 | #define __ARCH_WANT_SYS_TIME | ||
| 350 | #define __ARCH_WANT_SYS_UTIME | ||
| 351 | #define __ARCH_WANT_SYS_WAITPID | ||
| 352 | #define __ARCH_WANT_SYS_SOCKETCALL | ||
| 353 | #define __ARCH_WANT_SYS_FADVISE64 | ||
| 354 | #define __ARCH_WANT_SYS_GETPGRP | ||
| 355 | #define __ARCH_WANT_SYS_LLSEEK | ||
| 356 | #define __ARCH_WANT_SYS_NICE | ||
| 357 | #define __ARCH_WANT_SYS_OLD_GETRLIMIT | ||
| 358 | #define __ARCH_WANT_SYS_OLDUMOUNT | ||
| 359 | #define __ARCH_WANT_SYS_SIGPENDING | ||
| 360 | #define __ARCH_WANT_SYS_SIGPROCMASK | ||
| 361 | #define __ARCH_WANT_SYS_RT_SIGACTION | ||
| 362 | |||
| 363 | /* | ||
| 364 | * "Conditional" syscalls | ||
| 365 | * | ||
| 366 | * What we want is __attribute__((weak,alias("sys_ni_syscall"))), | ||
| 367 | * but it doesn't work on all toolchains, so we just do it by hand | ||
| 368 | */ | ||
| 369 | #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") | ||
| 370 | |||
| 371 | #endif /* __KERNEL__ */ | ||
| 372 | #endif /* _ASM_M68K_UNISTD_H_ */ | ||
diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c index d01a5d2b7557..db902540bf2c 100644 --- a/arch/m68knommu/platform/5206e/config.c +++ b/arch/m68knommu/platform/5206e/config.c | |||
| @@ -17,6 +17,7 @@ | |||
| 17 | #include <asm/coldfire.h> | 17 | #include <asm/coldfire.h> |
| 18 | #include <asm/mcfsim.h> | 18 | #include <asm/mcfsim.h> |
| 19 | #include <asm/mcfdma.h> | 19 | #include <asm/mcfdma.h> |
| 20 | #include <asm/mcfuart.h> | ||
| 20 | 21 | ||
| 21 | /***************************************************************************/ | 22 | /***************************************************************************/ |
| 22 | 23 | ||
diff --git a/arch/m68knommu/platform/528x/config.c b/arch/m68knommu/platform/528x/config.c index dfdb5c2ed8e6..44baeb225dc7 100644 --- a/arch/m68knommu/platform/528x/config.c +++ b/arch/m68knommu/platform/528x/config.c | |||
| @@ -24,7 +24,6 @@ | |||
| 24 | #include <asm/coldfire.h> | 24 | #include <asm/coldfire.h> |
| 25 | #include <asm/mcfsim.h> | 25 | #include <asm/mcfsim.h> |
| 26 | #include <asm/mcfuart.h> | 26 | #include <asm/mcfuart.h> |
| 27 | #include <asm/mcfqspi.h> | ||
| 28 | 27 | ||
| 29 | #ifdef CONFIG_MTD_PARTITIONS | 28 | #ifdef CONFIG_MTD_PARTITIONS |
| 30 | #include <linux/mtd/partitions.h> | 29 | #include <linux/mtd/partitions.h> |
| @@ -33,233 +32,6 @@ | |||
| 33 | /***************************************************************************/ | 32 | /***************************************************************************/ |
| 34 | 33 | ||
| 35 | void coldfire_reset(void); | 34 | void coldfire_reset(void); |
| 36 | static void coldfire_qspi_cs_control(u8 cs, u8 command); | ||
| 37 | |||
| 38 | /***************************************************************************/ | ||
| 39 | |||
| 40 | #if defined(CONFIG_SPI) | ||
| 41 | |||
| 42 | #if defined(CONFIG_WILDFIRE) | ||
| 43 | #define SPI_NUM_CHIPSELECTS 0x02 | ||
| 44 | #define SPI_PAR_VAL 0x07 /* Enable DIN, DOUT, CLK */ | ||
| 45 | #define SPI_CS_MASK 0x18 | ||
| 46 | |||
| 47 | #define FLASH_BLOCKSIZE (1024*64) | ||
| 48 | #define FLASH_NUMBLOCKS 16 | ||
| 49 | #define FLASH_TYPE "m25p80" | ||
| 50 | |||
| 51 | #define M25P80_CS 0 | ||
| 52 | #define MMC_CS 1 | ||
| 53 | |||
| 54 | #ifdef CONFIG_MTD_PARTITIONS | ||
| 55 | static struct mtd_partition stm25p_partitions[] = { | ||
| 56 | /* sflash */ | ||
| 57 | [0] = { | ||
| 58 | .name = "stm25p80", | ||
| 59 | .offset = 0x00000000, | ||
| 60 | .size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS, | ||
| 61 | .mask_flags = 0 | ||
| 62 | } | ||
| 63 | }; | ||
| 64 | |||
| 65 | #endif | ||
| 66 | |||
| 67 | #elif defined(CONFIG_WILDFIREMOD) | ||
| 68 | |||
| 69 | #define SPI_NUM_CHIPSELECTS 0x08 | ||
| 70 | #define SPI_PAR_VAL 0x07 /* Enable DIN, DOUT, CLK */ | ||
| 71 | #define SPI_CS_MASK 0x78 | ||
| 72 | |||
| 73 | #define FLASH_BLOCKSIZE (1024*64) | ||
| 74 | #define FLASH_NUMBLOCKS 64 | ||
| 75 | #define FLASH_TYPE "m25p32" | ||
| 76 | /* Reserve 1M for the kernel parition */ | ||
| 77 | #define FLASH_KERNEL_SIZE (1024 * 1024) | ||
| 78 | |||
| 79 | #define M25P80_CS 5 | ||
| 80 | #define MMC_CS 6 | ||
| 81 | |||
| 82 | #ifdef CONFIG_MTD_PARTITIONS | ||
| 83 | static struct mtd_partition stm25p_partitions[] = { | ||
| 84 | /* sflash */ | ||
| 85 | [0] = { | ||
| 86 | .name = "kernel", | ||
| 87 | .offset = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS - FLASH_KERNEL_SIZE, | ||
| 88 | .size = FLASH_KERNEL_SIZE, | ||
| 89 | .mask_flags = 0 | ||
| 90 | }, | ||
| 91 | [1] = { | ||
| 92 | .name = "image", | ||
| 93 | .offset = 0x00000000, | ||
| 94 | .size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS - FLASH_KERNEL_SIZE, | ||
| 95 | .mask_flags = 0 | ||
| 96 | }, | ||
| 97 | [2] = { | ||
| 98 | .name = "all", | ||
| 99 | .offset = 0x00000000, | ||
| 100 | .size = FLASH_BLOCKSIZE * FLASH_NUMBLOCKS, | ||
| 101 | .mask_flags = 0 | ||
| 102 | } | ||
| 103 | }; | ||
| 104 | #endif | ||
| 105 | |||
| 106 | #else | ||
| 107 | #define SPI_NUM_CHIPSELECTS 0x04 | ||
| 108 | #define SPI_PAR_VAL 0x7F /* Enable DIN, DOUT, CLK, CS0 - CS4 */ | ||
| 109 | #endif | ||
| 110 | |||
| 111 | #ifdef MMC_CS | ||
| 112 | static struct coldfire_spi_chip flash_chip_info = { | ||
| 113 | .mode = SPI_MODE_0, | ||
| 114 | .bits_per_word = 16, | ||
| 115 | .del_cs_to_clk = 17, | ||
| 116 | .del_after_trans = 1, | ||
| 117 | .void_write_data = 0 | ||
| 118 | }; | ||
| 119 | |||
| 120 | static struct coldfire_spi_chip mmc_chip_info = { | ||
| 121 | .mode = SPI_MODE_0, | ||
| 122 | .bits_per_word = 16, | ||
| 123 | .del_cs_to_clk = 17, | ||
| 124 | .del_after_trans = 1, | ||
| 125 | .void_write_data = 0xFFFF | ||
| 126 | }; | ||
| 127 | #endif | ||
| 128 | |||
| 129 | #ifdef M25P80_CS | ||
| 130 | static struct flash_platform_data stm25p80_platform_data = { | ||
| 131 | .name = "ST M25P80 SPI Flash chip", | ||
| 132 | #ifdef CONFIG_MTD_PARTITIONS | ||
| 133 | .parts = stm25p_partitions, | ||
| 134 | .nr_parts = sizeof(stm25p_partitions) / sizeof(*stm25p_partitions), | ||
| 135 | #endif | ||
| 136 | .type = FLASH_TYPE | ||
| 137 | }; | ||
| 138 | #endif | ||
| 139 | |||
| 140 | static struct spi_board_info spi_board_info[] __initdata = { | ||
| 141 | #ifdef M25P80_CS | ||
| 142 | { | ||
| 143 | .modalias = "m25p80", | ||
| 144 | .max_speed_hz = 16000000, | ||
| 145 | .bus_num = 1, | ||
| 146 | .chip_select = M25P80_CS, | ||
| 147 | .platform_data = &stm25p80_platform_data, | ||
| 148 | .controller_data = &flash_chip_info | ||
| 149 | }, | ||
| 150 | #endif | ||
| 151 | #ifdef MMC_CS | ||
| 152 | { | ||
| 153 | .modalias = "mmc_spi", | ||
| 154 | .max_speed_hz = 16000000, | ||
| 155 | .bus_num = 1, | ||
| 156 | .chip_select = MMC_CS, | ||
| 157 | .controller_data = &mmc_chip_info | ||
| 158 | } | ||
| 159 | #endif | ||
| 160 | }; | ||
| 161 | |||
| 162 | static struct coldfire_spi_master coldfire_master_info = { | ||
| 163 | .bus_num = 1, | ||
| 164 | .num_chipselect = SPI_NUM_CHIPSELECTS, | ||
| 165 | .irq_source = MCF5282_QSPI_IRQ_SOURCE, | ||
| 166 | .irq_vector = MCF5282_QSPI_IRQ_VECTOR, | ||
| 167 | .irq_mask = ((0x01 << MCF5282_QSPI_IRQ_SOURCE) | 0x01), | ||
| 168 | .irq_lp = 0x2B, /* Level 5 and Priority 3 */ | ||
| 169 | .par_val = SPI_PAR_VAL, | ||
| 170 | .cs_control = coldfire_qspi_cs_control, | ||
| 171 | }; | ||
| 172 | |||
| 173 | static struct resource coldfire_spi_resources[] = { | ||
| 174 | [0] = { | ||
| 175 | .name = "qspi-par", | ||
| 176 | .start = MCF5282_QSPI_PAR, | ||
| 177 | .end = MCF5282_QSPI_PAR, | ||
| 178 | .flags = IORESOURCE_MEM | ||
| 179 | }, | ||
| 180 | |||
| 181 | [1] = { | ||
| 182 | .name = "qspi-module", | ||
| 183 | .start = MCF5282_QSPI_QMR, | ||
| 184 | .end = MCF5282_QSPI_QMR + 0x18, | ||
| 185 | .flags = IORESOURCE_MEM | ||
| 186 | }, | ||
| 187 | |||
| 188 | [2] = { | ||
| 189 | .name = "qspi-int-level", | ||
| 190 | .start = MCF5282_INTC0 + MCFINTC_ICR0 + MCF5282_QSPI_IRQ_SOURCE, | ||
| 191 | .end = MCF5282_INTC0 + MCFINTC_ICR0 + MCF5282_QSPI_IRQ_SOURCE, | ||
| 192 | .flags = IORESOURCE_MEM | ||
| 193 | }, | ||
| 194 | |||
| 195 | [3] = { | ||
| 196 | .name = "qspi-int-mask", | ||
| 197 | .start = MCF5282_INTC0 + MCFINTC_IMRL, | ||
| 198 | .end = MCF5282_INTC0 + MCFINTC_IMRL, | ||
| 199 | .flags = IORESOURCE_MEM | ||
| 200 | } | ||
| 201 | }; | ||
| 202 | |||
| 203 | static struct platform_device coldfire_spi = { | ||
| 204 | .name = "spi_coldfire", | ||
| 205 | .id = -1, | ||
| 206 | .resource = coldfire_spi_resources, | ||
| 207 | .num_resources = ARRAY_SIZE(coldfire_spi_resources), | ||
| 208 | .dev = { | ||
| 209 | .platform_data = &coldfire_master_info, | ||
| 210 | } | ||
| 211 | }; | ||
| 212 | |||
| 213 | static void coldfire_qspi_cs_control(u8 cs, u8 command) | ||
| 214 | { | ||
| 215 | u8 cs_bit = ((0x01 << cs) << 3) & SPI_CS_MASK; | ||
| 216 | |||
| 217 | #if defined(CONFIG_WILDFIRE) | ||
| 218 | u8 cs_mask = ~(((0x01 << cs) << 3) & SPI_CS_MASK); | ||
| 219 | #endif | ||
| 220 | #if defined(CONFIG_WILDFIREMOD) | ||
| 221 | u8 cs_mask = (cs << 3) & SPI_CS_MASK; | ||
| 222 | #endif | ||
| 223 | |||
| 224 | /* | ||
| 225 | * Don't do anything if the chip select is not | ||
| 226 | * one of the port qs pins. | ||
| 227 | */ | ||
| 228 | if (command & QSPI_CS_INIT) { | ||
| 229 | #if defined(CONFIG_WILDFIRE) | ||
| 230 | MCF5282_GPIO_DDRQS |= cs_bit; | ||
| 231 | MCF5282_GPIO_PQSPAR &= ~cs_bit; | ||
| 232 | #endif | ||
| 233 | |||
| 234 | #if defined(CONFIG_WILDFIREMOD) | ||
| 235 | MCF5282_GPIO_DDRQS |= SPI_CS_MASK; | ||
| 236 | MCF5282_GPIO_PQSPAR &= ~SPI_CS_MASK; | ||
| 237 | #endif | ||
| 238 | } | ||
| 239 | |||
| 240 | if (command & QSPI_CS_ASSERT) { | ||
| 241 | MCF5282_GPIO_PORTQS &= ~SPI_CS_MASK; | ||
| 242 | MCF5282_GPIO_PORTQS |= cs_mask; | ||
| 243 | } else if (command & QSPI_CS_DROP) { | ||
| 244 | MCF5282_GPIO_PORTQS |= SPI_CS_MASK; | ||
| 245 | } | ||
| 246 | } | ||
| 247 | |||
| 248 | static int __init spi_dev_init(void) | ||
| 249 | { | ||
| 250 | int retval; | ||
| 251 | |||
| 252 | retval = platform_device_register(&coldfire_spi); | ||
| 253 | if (retval < 0) | ||
| 254 | return retval; | ||
| 255 | |||
| 256 | if (ARRAY_SIZE(spi_board_info)) | ||
| 257 | retval = spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); | ||
| 258 | |||
| 259 | return retval; | ||
| 260 | } | ||
| 261 | |||
| 262 | #endif /* CONFIG_SPI */ | ||
| 263 | 35 | ||
| 264 | /***************************************************************************/ | 36 | /***************************************************************************/ |
| 265 | 37 | ||
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e61465a18c7e..206cb7953b0c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig | |||
| @@ -238,8 +238,12 @@ config MIPS_SIM | |||
| 238 | This option enables support for MIPS Technologies MIPSsim software | 238 | This option enables support for MIPS Technologies MIPSsim software |
| 239 | emulator. | 239 | emulator. |
| 240 | 240 | ||
| 241 | config MACH_EMMA | 241 | config NEC_MARKEINS |
| 242 | bool "NEC EMMA series based machines" | 242 | bool "NEC EMMA2RH Mark-eins board" |
| 243 | select SOC_EMMA2RH | ||
| 244 | select HW_HAS_PCI | ||
| 245 | help | ||
| 246 | This enables support for the NEC Electronics Mark-eins boards. | ||
| 243 | 247 | ||
| 244 | config MACH_VR41XX | 248 | config MACH_VR41XX |
| 245 | bool "NEC VR4100 series based machines" | 249 | bool "NEC VR4100 series based machines" |
| @@ -637,7 +641,6 @@ endchoice | |||
| 637 | 641 | ||
| 638 | source "arch/mips/alchemy/Kconfig" | 642 | source "arch/mips/alchemy/Kconfig" |
| 639 | source "arch/mips/basler/excite/Kconfig" | 643 | source "arch/mips/basler/excite/Kconfig" |
| 640 | source "arch/mips/emma/Kconfig" | ||
| 641 | source "arch/mips/jazz/Kconfig" | 644 | source "arch/mips/jazz/Kconfig" |
| 642 | source "arch/mips/lasat/Kconfig" | 645 | source "arch/mips/lasat/Kconfig" |
| 643 | source "arch/mips/pmc-sierra/Kconfig" | 646 | source "arch/mips/pmc-sierra/Kconfig" |
| @@ -895,6 +898,18 @@ config MIPS_RM9122 | |||
| 895 | bool | 898 | bool |
| 896 | select SERIAL_RM9000 | 899 | select SERIAL_RM9000 |
| 897 | 900 | ||
| 901 | config SOC_EMMA2RH | ||
| 902 | bool | ||
| 903 | select CEVT_R4K | ||
| 904 | select CSRC_R4K | ||
| 905 | select DMA_NONCOHERENT | ||
| 906 | select IRQ_CPU | ||
| 907 | select SWAP_IO_SPACE | ||
| 908 | select SYS_HAS_CPU_R5500 | ||
| 909 | select SYS_SUPPORTS_32BIT_KERNEL | ||
| 910 | select SYS_SUPPORTS_64BIT_KERNEL | ||
| 911 | select SYS_SUPPORTS_BIG_ENDIAN | ||
| 912 | |||
| 898 | config SOC_PNX833X | 913 | config SOC_PNX833X |
| 899 | bool | 914 | bool |
| 900 | select CEVT_R4K | 915 | select CEVT_R4K |
| @@ -930,11 +945,6 @@ config SOC_PNX8550 | |||
| 930 | config SWAP_IO_SPACE | 945 | config SWAP_IO_SPACE |
| 931 | bool | 946 | bool |
| 932 | 947 | ||
| 933 | config EMMA2RH | ||
| 934 | bool | ||
| 935 | depends on MARKEINS | ||
| 936 | default y | ||
| 937 | |||
| 938 | config SERIAL_RM9000 | 948 | config SERIAL_RM9000 |
| 939 | bool | 949 | bool |
| 940 | 950 | ||
diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 21b00e95daef..22dab2e14348 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile | |||
| @@ -416,7 +416,7 @@ load-$(CONFIG_PNX8550_STB810) += 0xffffffff80060000 | |||
| 416 | # | 416 | # |
| 417 | # Common NEC EMMAXXX | 417 | # Common NEC EMMAXXX |
| 418 | # | 418 | # |
| 419 | core-$(CONFIG_SOC_EMMA) += arch/mips/emma/common/ | 419 | core-$(CONFIG_SOC_EMMA2RH) += arch/mips/emma/common/ |
| 420 | cflags-$(CONFIG_SOC_EMMA2RH) += -I$(srctree)/arch/mips/include/asm/mach-emma2rh | 420 | cflags-$(CONFIG_SOC_EMMA2RH) += -I$(srctree)/arch/mips/include/asm/mach-emma2rh |
| 421 | 421 | ||
| 422 | # | 422 | # |
diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index f2baea3039bb..0208723adf28 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig | |||
| @@ -512,7 +512,7 @@ CONFIG_MD_LINEAR=m | |||
| 512 | CONFIG_MD_RAID0=y | 512 | CONFIG_MD_RAID0=y |
| 513 | CONFIG_MD_RAID1=y | 513 | CONFIG_MD_RAID1=y |
| 514 | CONFIG_MD_RAID10=m | 514 | CONFIG_MD_RAID10=m |
| 515 | CONFIG_MD_RAID456=m | 515 | CONFIG_MD_RAID456=y |
| 516 | CONFIG_MD_RAID5_RESHAPE=y | 516 | CONFIG_MD_RAID5_RESHAPE=y |
| 517 | CONFIG_MD_MULTIPATH=m | 517 | CONFIG_MD_MULTIPATH=m |
| 518 | CONFIG_MD_FAULTY=m | 518 | CONFIG_MD_FAULTY=m |
diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index 9d5bd2a0af3d..5380f1f582d9 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.26-rc9 | 3 | # Linux kernel version: 2.6.29-rc7 |
| 4 | # Fri Jul 11 23:01:36 2008 | 4 | # Wed Mar 4 23:07:16 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_MIPS=y | 6 | CONFIG_MIPS=y |
| 7 | 7 | ||
| @@ -18,8 +18,10 @@ CONFIG_MIPS=y | |||
| 18 | # CONFIG_LEMOTE_FULONG is not set | 18 | # CONFIG_LEMOTE_FULONG is not set |
| 19 | # CONFIG_MIPS_MALTA is not set | 19 | # CONFIG_MIPS_MALTA is not set |
| 20 | # CONFIG_MIPS_SIM is not set | 20 | # CONFIG_MIPS_SIM is not set |
| 21 | # CONFIG_MARKEINS is not set | 21 | # CONFIG_MACH_EMMA is not set |
| 22 | # CONFIG_MACH_VR41XX is not set | 22 | # CONFIG_MACH_VR41XX is not set |
| 23 | # CONFIG_NXP_STB220 is not set | ||
| 24 | # CONFIG_NXP_STB225 is not set | ||
| 23 | # CONFIG_PNX8550_JBS is not set | 25 | # CONFIG_PNX8550_JBS is not set |
| 24 | # CONFIG_PNX8550_STB810 is not set | 26 | # CONFIG_PNX8550_STB810 is not set |
| 25 | # CONFIG_PMC_MSP is not set | 27 | # CONFIG_PMC_MSP is not set |
| @@ -39,7 +41,11 @@ CONFIG_MIPS=y | |||
| 39 | # CONFIG_SNI_RM is not set | 41 | # CONFIG_SNI_RM is not set |
| 40 | CONFIG_MACH_TX39XX=y | 42 | CONFIG_MACH_TX39XX=y |
| 41 | # CONFIG_MACH_TX49XX is not set | 43 | # CONFIG_MACH_TX49XX is not set |
| 44 | # CONFIG_MIKROTIK_RB532 is not set | ||
| 42 | # CONFIG_WR_PPMC is not set | 45 | # CONFIG_WR_PPMC is not set |
| 46 | # CONFIG_CAVIUM_OCTEON_SIMULATOR is not set | ||
| 47 | # CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set | ||
| 48 | CONFIG_MACH_TXX9=y | ||
| 43 | CONFIG_TOSHIBA_JMR3927=y | 49 | CONFIG_TOSHIBA_JMR3927=y |
| 44 | CONFIG_SOC_TX3927=y | 50 | CONFIG_SOC_TX3927=y |
| 45 | # CONFIG_TOSHIBA_FPCIB0 is not set | 51 | # CONFIG_TOSHIBA_FPCIB0 is not set |
| @@ -54,12 +60,14 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y | |||
| 54 | CONFIG_GENERIC_CLOCKEVENTS=y | 60 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 55 | CONFIG_GENERIC_TIME=y | 61 | CONFIG_GENERIC_TIME=y |
| 56 | CONFIG_GENERIC_CMOS_UPDATE=y | 62 | CONFIG_GENERIC_CMOS_UPDATE=y |
| 57 | CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y | 63 | CONFIG_SCHED_OMIT_FRAME_POINTER=y |
| 58 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | 64 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| 59 | CONFIG_CEVT_TXX9=y | 65 | CONFIG_CEVT_TXX9=y |
| 60 | CONFIG_GPIO_TXX9=y | 66 | CONFIG_GPIO_TXX9=y |
| 61 | CONFIG_DMA_NONCOHERENT=y | 67 | CONFIG_DMA_NONCOHERENT=y |
| 62 | CONFIG_DMA_NEED_PCI_MAP_STATE=y | 68 | CONFIG_DMA_NEED_PCI_MAP_STATE=y |
| 69 | CONFIG_EARLY_PRINTK=y | ||
| 70 | CONFIG_SYS_HAS_EARLY_PRINTK=y | ||
| 63 | # CONFIG_HOTPLUG_CPU is not set | 71 | # CONFIG_HOTPLUG_CPU is not set |
| 64 | # CONFIG_NO_IOPORT is not set | 72 | # CONFIG_NO_IOPORT is not set |
| 65 | CONFIG_GENERIC_GPIO=y | 73 | CONFIG_GENERIC_GPIO=y |
| @@ -87,6 +95,7 @@ CONFIG_CPU_TX39XX=y | |||
| 87 | # CONFIG_CPU_TX49XX is not set | 95 | # CONFIG_CPU_TX49XX is not set |
| 88 | # CONFIG_CPU_R5000 is not set | 96 | # CONFIG_CPU_R5000 is not set |
| 89 | # CONFIG_CPU_R5432 is not set | 97 | # CONFIG_CPU_R5432 is not set |
| 98 | # CONFIG_CPU_R5500 is not set | ||
| 90 | # CONFIG_CPU_R6000 is not set | 99 | # CONFIG_CPU_R6000 is not set |
| 91 | # CONFIG_CPU_NEVADA is not set | 100 | # CONFIG_CPU_NEVADA is not set |
| 92 | # CONFIG_CPU_R8000 is not set | 101 | # CONFIG_CPU_R8000 is not set |
| @@ -94,6 +103,7 @@ CONFIG_CPU_TX39XX=y | |||
| 94 | # CONFIG_CPU_RM7000 is not set | 103 | # CONFIG_CPU_RM7000 is not set |
| 95 | # CONFIG_CPU_RM9000 is not set | 104 | # CONFIG_CPU_RM9000 is not set |
| 96 | # CONFIG_CPU_SB1 is not set | 105 | # CONFIG_CPU_SB1 is not set |
| 106 | # CONFIG_CPU_CAVIUM_OCTEON is not set | ||
| 97 | CONFIG_SYS_HAS_CPU_TX39XX=y | 107 | CONFIG_SYS_HAS_CPU_TX39XX=y |
| 98 | CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y | 108 | CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y |
| 99 | CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y | 109 | CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y |
| @@ -117,14 +127,12 @@ CONFIG_ARCH_FLATMEM_ENABLE=y | |||
| 117 | CONFIG_ARCH_POPULATES_NODE_MAP=y | 127 | CONFIG_ARCH_POPULATES_NODE_MAP=y |
| 118 | CONFIG_FLATMEM=y | 128 | CONFIG_FLATMEM=y |
| 119 | CONFIG_FLAT_NODE_MEM_MAP=y | 129 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 120 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 121 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 122 | CONFIG_PAGEFLAGS_EXTENDED=y | 130 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 123 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 131 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 124 | # CONFIG_RESOURCES_64BIT is not set | 132 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 125 | CONFIG_ZONE_DMA_FLAG=0 | 133 | CONFIG_ZONE_DMA_FLAG=0 |
| 126 | CONFIG_VIRT_TO_BUS=y | 134 | CONFIG_VIRT_TO_BUS=y |
| 127 | # CONFIG_TICK_ONESHOT is not set | 135 | CONFIG_UNEVICTABLE_LRU=y |
| 128 | # CONFIG_NO_HZ is not set | 136 | # CONFIG_NO_HZ is not set |
| 129 | # CONFIG_HIGH_RES_TIMERS is not set | 137 | # CONFIG_HIGH_RES_TIMERS is not set |
| 130 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y | 138 | CONFIG_GENERIC_CLOCKEVENTS_BUILD=y |
| @@ -159,6 +167,15 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 159 | # CONFIG_BSD_PROCESS_ACCT is not set | 167 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 160 | # CONFIG_TASKSTATS is not set | 168 | # CONFIG_TASKSTATS is not set |
| 161 | # CONFIG_AUDIT is not set | 169 | # CONFIG_AUDIT is not set |
| 170 | |||
| 171 | # | ||
| 172 | # RCU Subsystem | ||
| 173 | # | ||
| 174 | CONFIG_CLASSIC_RCU=y | ||
| 175 | # CONFIG_TREE_RCU is not set | ||
| 176 | # CONFIG_PREEMPT_RCU is not set | ||
| 177 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 178 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 162 | # CONFIG_IKCONFIG is not set | 179 | # CONFIG_IKCONFIG is not set |
| 163 | CONFIG_LOG_BUF_SHIFT=14 | 180 | CONFIG_LOG_BUF_SHIFT=14 |
| 164 | # CONFIG_CGROUPS is not set | 181 | # CONFIG_CGROUPS is not set |
| @@ -171,7 +188,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y | |||
| 171 | CONFIG_SYSCTL=y | 188 | CONFIG_SYSCTL=y |
| 172 | CONFIG_EMBEDDED=y | 189 | CONFIG_EMBEDDED=y |
| 173 | CONFIG_SYSCTL_SYSCALL=y | 190 | CONFIG_SYSCTL_SYSCALL=y |
| 174 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 175 | CONFIG_KALLSYMS=y | 191 | CONFIG_KALLSYMS=y |
| 176 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 192 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 177 | # CONFIG_HOTPLUG is not set | 193 | # CONFIG_HOTPLUG is not set |
| @@ -188,26 +204,23 @@ CONFIG_SIGNALFD=y | |||
| 188 | CONFIG_TIMERFD=y | 204 | CONFIG_TIMERFD=y |
| 189 | CONFIG_EVENTFD=y | 205 | CONFIG_EVENTFD=y |
| 190 | CONFIG_SHMEM=y | 206 | CONFIG_SHMEM=y |
| 207 | CONFIG_AIO=y | ||
| 191 | CONFIG_VM_EVENT_COUNTERS=y | 208 | CONFIG_VM_EVENT_COUNTERS=y |
| 209 | CONFIG_PCI_QUIRKS=y | ||
| 192 | CONFIG_SLAB=y | 210 | CONFIG_SLAB=y |
| 193 | # CONFIG_SLUB is not set | 211 | # CONFIG_SLUB is not set |
| 194 | # CONFIG_SLOB is not set | 212 | # CONFIG_SLOB is not set |
| 195 | # CONFIG_PROFILING is not set | 213 | # CONFIG_PROFILING is not set |
| 196 | # CONFIG_MARKERS is not set | ||
| 197 | CONFIG_HAVE_OPROFILE=y | 214 | CONFIG_HAVE_OPROFILE=y |
| 198 | # CONFIG_HAVE_KPROBES is not set | 215 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 199 | # CONFIG_HAVE_KRETPROBES is not set | ||
| 200 | # CONFIG_HAVE_DMA_ATTRS is not set | ||
| 201 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 202 | CONFIG_SLABINFO=y | 216 | CONFIG_SLABINFO=y |
| 203 | CONFIG_RT_MUTEXES=y | 217 | CONFIG_RT_MUTEXES=y |
| 204 | # CONFIG_TINY_SHMEM is not set | ||
| 205 | CONFIG_BASE_SMALL=0 | 218 | CONFIG_BASE_SMALL=0 |
| 206 | # CONFIG_MODULES is not set | 219 | # CONFIG_MODULES is not set |
| 207 | CONFIG_BLOCK=y | 220 | CONFIG_BLOCK=y |
| 208 | # CONFIG_LBD is not set | 221 | # CONFIG_LBD is not set |
| 209 | # CONFIG_BLK_DEV_IO_TRACE is not set | 222 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 210 | # CONFIG_LSF is not set | 223 | # CONFIG_BLK_DEV_INTEGRITY is not set |
| 211 | 224 | ||
| 212 | # | 225 | # |
| 213 | # IO Schedulers | 226 | # IO Schedulers |
| @@ -221,7 +234,7 @@ CONFIG_IOSCHED_CFQ=y | |||
| 221 | CONFIG_DEFAULT_CFQ=y | 234 | CONFIG_DEFAULT_CFQ=y |
| 222 | # CONFIG_DEFAULT_NOOP is not set | 235 | # CONFIG_DEFAULT_NOOP is not set |
| 223 | CONFIG_DEFAULT_IOSCHED="cfq" | 236 | CONFIG_DEFAULT_IOSCHED="cfq" |
| 224 | CONFIG_CLASSIC_RCU=y | 237 | # CONFIG_FREEZER is not set |
| 225 | 238 | ||
| 226 | # | 239 | # |
| 227 | # Bus options (PCI, PCMCIA, EISA, ISA, TC) | 240 | # Bus options (PCI, PCMCIA, EISA, ISA, TC) |
| @@ -231,12 +244,15 @@ CONFIG_PCI=y | |||
| 231 | CONFIG_PCI_DOMAINS=y | 244 | CONFIG_PCI_DOMAINS=y |
| 232 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 245 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 233 | CONFIG_PCI_LEGACY=y | 246 | CONFIG_PCI_LEGACY=y |
| 247 | # CONFIG_PCI_STUB is not set | ||
| 234 | CONFIG_MMU=y | 248 | CONFIG_MMU=y |
| 235 | 249 | ||
| 236 | # | 250 | # |
| 237 | # Executable file formats | 251 | # Executable file formats |
| 238 | # | 252 | # |
| 239 | CONFIG_BINFMT_ELF=y | 253 | CONFIG_BINFMT_ELF=y |
| 254 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 255 | # CONFIG_HAVE_AOUT is not set | ||
| 240 | # CONFIG_BINFMT_MISC is not set | 256 | # CONFIG_BINFMT_MISC is not set |
| 241 | CONFIG_TRAD_SIGNALS=y | 257 | CONFIG_TRAD_SIGNALS=y |
| 242 | 258 | ||
| @@ -245,15 +261,12 @@ CONFIG_TRAD_SIGNALS=y | |||
| 245 | # | 261 | # |
| 246 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | 262 | CONFIG_ARCH_SUSPEND_POSSIBLE=y |
| 247 | # CONFIG_PM is not set | 263 | # CONFIG_PM is not set |
| 248 | |||
| 249 | # | ||
| 250 | # Networking | ||
| 251 | # | ||
| 252 | CONFIG_NET=y | 264 | CONFIG_NET=y |
| 253 | 265 | ||
| 254 | # | 266 | # |
| 255 | # Networking options | 267 | # Networking options |
| 256 | # | 268 | # |
| 269 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 257 | CONFIG_PACKET=y | 270 | CONFIG_PACKET=y |
| 258 | # CONFIG_PACKET_MMAP is not set | 271 | # CONFIG_PACKET_MMAP is not set |
| 259 | CONFIG_UNIX=y | 272 | CONFIG_UNIX=y |
| @@ -293,6 +306,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 293 | # CONFIG_IPX is not set | 306 | # CONFIG_IPX is not set |
| 294 | # CONFIG_ATALK is not set | 307 | # CONFIG_ATALK is not set |
| 295 | # CONFIG_NET_SCHED is not set | 308 | # CONFIG_NET_SCHED is not set |
| 309 | # CONFIG_DCB is not set | ||
| 296 | 310 | ||
| 297 | # | 311 | # |
| 298 | # Network testing | 312 | # Network testing |
| @@ -302,14 +316,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 302 | # CONFIG_CAN is not set | 316 | # CONFIG_CAN is not set |
| 303 | # CONFIG_IRDA is not set | 317 | # CONFIG_IRDA is not set |
| 304 | # CONFIG_BT is not set | 318 | # CONFIG_BT is not set |
| 305 | 319 | # CONFIG_PHONET is not set | |
| 306 | # | 320 | # CONFIG_WIRELESS is not set |
| 307 | # Wireless | 321 | # CONFIG_WIMAX is not set |
| 308 | # | ||
| 309 | # CONFIG_CFG80211 is not set | ||
| 310 | # CONFIG_WIRELESS_EXT is not set | ||
| 311 | # CONFIG_MAC80211 is not set | ||
| 312 | # CONFIG_IEEE80211 is not set | ||
| 313 | # CONFIG_RFKILL is not set | 322 | # CONFIG_RFKILL is not set |
| 314 | 323 | ||
| 315 | # | 324 | # |
| @@ -323,7 +332,89 @@ CONFIG_STANDALONE=y | |||
| 323 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 332 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 324 | # CONFIG_SYS_HYPERVISOR is not set | 333 | # CONFIG_SYS_HYPERVISOR is not set |
| 325 | # CONFIG_CONNECTOR is not set | 334 | # CONFIG_CONNECTOR is not set |
| 326 | # CONFIG_MTD is not set | 335 | CONFIG_MTD=y |
| 336 | # CONFIG_MTD_DEBUG is not set | ||
| 337 | # CONFIG_MTD_CONCAT is not set | ||
| 338 | CONFIG_MTD_PARTITIONS=y | ||
| 339 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 340 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 341 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 342 | |||
| 343 | # | ||
| 344 | # User Modules And Translation Layers | ||
| 345 | # | ||
| 346 | CONFIG_MTD_CHAR=y | ||
| 347 | # CONFIG_MTD_BLKDEVS is not set | ||
| 348 | # CONFIG_MTD_BLOCK is not set | ||
| 349 | # CONFIG_MTD_BLOCK_RO is not set | ||
| 350 | # CONFIG_FTL is not set | ||
| 351 | # CONFIG_NFTL is not set | ||
| 352 | # CONFIG_INFTL is not set | ||
| 353 | # CONFIG_RFD_FTL is not set | ||
| 354 | # CONFIG_SSFDC is not set | ||
| 355 | # CONFIG_MTD_OOPS is not set | ||
| 356 | |||
| 357 | # | ||
| 358 | # RAM/ROM/Flash chip drivers | ||
| 359 | # | ||
| 360 | CONFIG_MTD_CFI=y | ||
| 361 | CONFIG_MTD_JEDECPROBE=y | ||
| 362 | CONFIG_MTD_GEN_PROBE=y | ||
| 363 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 364 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 365 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 366 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 367 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 368 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 369 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 370 | CONFIG_MTD_CFI_I1=y | ||
| 371 | CONFIG_MTD_CFI_I2=y | ||
| 372 | # CONFIG_MTD_CFI_I4 is not set | ||
| 373 | # CONFIG_MTD_CFI_I8 is not set | ||
| 374 | # CONFIG_MTD_CFI_INTELEXT is not set | ||
| 375 | CONFIG_MTD_CFI_AMDSTD=y | ||
| 376 | # CONFIG_MTD_CFI_STAA is not set | ||
| 377 | CONFIG_MTD_CFI_UTIL=y | ||
| 378 | # CONFIG_MTD_RAM is not set | ||
| 379 | # CONFIG_MTD_ROM is not set | ||
| 380 | # CONFIG_MTD_ABSENT is not set | ||
| 381 | |||
| 382 | # | ||
| 383 | # Mapping drivers for chip access | ||
| 384 | # | ||
| 385 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 386 | CONFIG_MTD_PHYSMAP=y | ||
| 387 | # CONFIG_MTD_PHYSMAP_COMPAT is not set | ||
| 388 | # CONFIG_MTD_INTEL_VR_NOR is not set | ||
| 389 | # CONFIG_MTD_PLATRAM is not set | ||
| 390 | |||
| 391 | # | ||
| 392 | # Self-contained MTD device drivers | ||
| 393 | # | ||
| 394 | # CONFIG_MTD_PMC551 is not set | ||
| 395 | # CONFIG_MTD_SLRAM is not set | ||
| 396 | # CONFIG_MTD_PHRAM is not set | ||
| 397 | # CONFIG_MTD_MTDRAM is not set | ||
| 398 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 399 | |||
| 400 | # | ||
| 401 | # Disk-On-Chip Device Drivers | ||
| 402 | # | ||
| 403 | # CONFIG_MTD_DOC2000 is not set | ||
| 404 | # CONFIG_MTD_DOC2001 is not set | ||
| 405 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 406 | # CONFIG_MTD_NAND is not set | ||
| 407 | # CONFIG_MTD_ONENAND is not set | ||
| 408 | |||
| 409 | # | ||
| 410 | # LPDDR flash memory drivers | ||
| 411 | # | ||
| 412 | # CONFIG_MTD_LPDDR is not set | ||
| 413 | |||
| 414 | # | ||
| 415 | # UBI - Unsorted block images | ||
| 416 | # | ||
| 417 | # CONFIG_MTD_UBI is not set | ||
| 327 | # CONFIG_PARPORT is not set | 418 | # CONFIG_PARPORT is not set |
| 328 | CONFIG_BLK_DEV=y | 419 | CONFIG_BLK_DEV=y |
| 329 | # CONFIG_BLK_CPQ_DA is not set | 420 | # CONFIG_BLK_CPQ_DA is not set |
| @@ -336,6 +427,7 @@ CONFIG_BLK_DEV=y | |||
| 336 | # CONFIG_BLK_DEV_RAM is not set | 427 | # CONFIG_BLK_DEV_RAM is not set |
| 337 | # CONFIG_CDROM_PKTCDVD is not set | 428 | # CONFIG_CDROM_PKTCDVD is not set |
| 338 | # CONFIG_ATA_OVER_ETH is not set | 429 | # CONFIG_ATA_OVER_ETH is not set |
| 430 | # CONFIG_BLK_DEV_HD is not set | ||
| 339 | # CONFIG_MISC_DEVICES is not set | 431 | # CONFIG_MISC_DEVICES is not set |
| 340 | CONFIG_HAVE_IDE=y | 432 | CONFIG_HAVE_IDE=y |
| 341 | # CONFIG_IDE is not set | 433 | # CONFIG_IDE is not set |
| @@ -361,7 +453,6 @@ CONFIG_HAVE_IDE=y | |||
| 361 | # CONFIG_IEEE1394 is not set | 453 | # CONFIG_IEEE1394 is not set |
| 362 | # CONFIG_I2O is not set | 454 | # CONFIG_I2O is not set |
| 363 | CONFIG_NETDEVICES=y | 455 | CONFIG_NETDEVICES=y |
| 364 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 365 | # CONFIG_DUMMY is not set | 456 | # CONFIG_DUMMY is not set |
| 366 | # CONFIG_BONDING is not set | 457 | # CONFIG_BONDING is not set |
| 367 | # CONFIG_EQUALIZER is not set | 458 | # CONFIG_EQUALIZER is not set |
| @@ -383,6 +474,9 @@ CONFIG_PHYLIB=y | |||
| 383 | # CONFIG_BROADCOM_PHY is not set | 474 | # CONFIG_BROADCOM_PHY is not set |
| 384 | # CONFIG_ICPLUS_PHY is not set | 475 | # CONFIG_ICPLUS_PHY is not set |
| 385 | # CONFIG_REALTEK_PHY is not set | 476 | # CONFIG_REALTEK_PHY is not set |
| 477 | # CONFIG_NATIONAL_PHY is not set | ||
| 478 | # CONFIG_STE10XP is not set | ||
| 479 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 386 | # CONFIG_FIXED_PHY is not set | 480 | # CONFIG_FIXED_PHY is not set |
| 387 | # CONFIG_MDIO_BITBANG is not set | 481 | # CONFIG_MDIO_BITBANG is not set |
| 388 | CONFIG_NET_ETHERNET=y | 482 | CONFIG_NET_ETHERNET=y |
| @@ -392,6 +486,7 @@ CONFIG_NET_ETHERNET=y | |||
| 392 | # CONFIG_SUNGEM is not set | 486 | # CONFIG_SUNGEM is not set |
| 393 | # CONFIG_CASSINI is not set | 487 | # CONFIG_CASSINI is not set |
| 394 | # CONFIG_NET_VENDOR_3COM is not set | 488 | # CONFIG_NET_VENDOR_3COM is not set |
| 489 | # CONFIG_SMC91X is not set | ||
| 395 | # CONFIG_DM9000 is not set | 490 | # CONFIG_DM9000 is not set |
| 396 | # CONFIG_NET_TULIP is not set | 491 | # CONFIG_NET_TULIP is not set |
| 397 | # CONFIG_HP100 is not set | 492 | # CONFIG_HP100 is not set |
| @@ -399,6 +494,9 @@ CONFIG_NET_ETHERNET=y | |||
| 399 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 494 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 400 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 495 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 401 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 496 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 497 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 498 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 499 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 402 | CONFIG_NET_PCI=y | 500 | CONFIG_NET_PCI=y |
| 403 | # CONFIG_PCNET32 is not set | 501 | # CONFIG_PCNET32 is not set |
| 404 | # CONFIG_AMD8111_ETH is not set | 502 | # CONFIG_AMD8111_ETH is not set |
| @@ -406,7 +504,6 @@ CONFIG_NET_PCI=y | |||
| 406 | # CONFIG_B44 is not set | 504 | # CONFIG_B44 is not set |
| 407 | # CONFIG_FORCEDETH is not set | 505 | # CONFIG_FORCEDETH is not set |
| 408 | CONFIG_TC35815=y | 506 | CONFIG_TC35815=y |
| 409 | # CONFIG_EEPRO100 is not set | ||
| 410 | # CONFIG_E100 is not set | 507 | # CONFIG_E100 is not set |
| 411 | # CONFIG_FEALNX is not set | 508 | # CONFIG_FEALNX is not set |
| 412 | # CONFIG_NATSEMI is not set | 509 | # CONFIG_NATSEMI is not set |
| @@ -415,9 +512,11 @@ CONFIG_TC35815=y | |||
| 415 | # CONFIG_R6040 is not set | 512 | # CONFIG_R6040 is not set |
| 416 | # CONFIG_SIS900 is not set | 513 | # CONFIG_SIS900 is not set |
| 417 | # CONFIG_EPIC100 is not set | 514 | # CONFIG_EPIC100 is not set |
| 515 | # CONFIG_SMSC9420 is not set | ||
| 418 | # CONFIG_SUNDANCE is not set | 516 | # CONFIG_SUNDANCE is not set |
| 419 | # CONFIG_TLAN is not set | 517 | # CONFIG_TLAN is not set |
| 420 | # CONFIG_VIA_RHINE is not set | 518 | # CONFIG_VIA_RHINE is not set |
| 519 | # CONFIG_ATL2 is not set | ||
| 421 | # CONFIG_NETDEV_1000 is not set | 520 | # CONFIG_NETDEV_1000 is not set |
| 422 | # CONFIG_NETDEV_10000 is not set | 521 | # CONFIG_NETDEV_10000 is not set |
| 423 | # CONFIG_TR is not set | 522 | # CONFIG_TR is not set |
| @@ -428,6 +527,10 @@ CONFIG_TC35815=y | |||
| 428 | # CONFIG_WLAN_PRE80211 is not set | 527 | # CONFIG_WLAN_PRE80211 is not set |
| 429 | # CONFIG_WLAN_80211 is not set | 528 | # CONFIG_WLAN_80211 is not set |
| 430 | # CONFIG_IWLWIFI_LEDS is not set | 529 | # CONFIG_IWLWIFI_LEDS is not set |
| 530 | |||
| 531 | # | ||
| 532 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 533 | # | ||
| 431 | # CONFIG_WAN is not set | 534 | # CONFIG_WAN is not set |
| 432 | # CONFIG_FDDI is not set | 535 | # CONFIG_FDDI is not set |
| 433 | # CONFIG_PPP is not set | 536 | # CONFIG_PPP is not set |
| @@ -440,27 +543,7 @@ CONFIG_TC35815=y | |||
| 440 | # | 543 | # |
| 441 | # Input device support | 544 | # Input device support |
| 442 | # | 545 | # |
| 443 | CONFIG_INPUT=y | 546 | # CONFIG_INPUT is not set |
| 444 | # CONFIG_INPUT_FF_MEMLESS is not set | ||
| 445 | # CONFIG_INPUT_POLLDEV is not set | ||
| 446 | |||
| 447 | # | ||
| 448 | # Userland interfaces | ||
| 449 | # | ||
| 450 | # CONFIG_INPUT_MOUSEDEV is not set | ||
| 451 | # CONFIG_INPUT_JOYDEV is not set | ||
| 452 | # CONFIG_INPUT_EVDEV is not set | ||
| 453 | # CONFIG_INPUT_EVBUG is not set | ||
| 454 | |||
| 455 | # | ||
| 456 | # Input Device Drivers | ||
| 457 | # | ||
| 458 | # CONFIG_INPUT_KEYBOARD is not set | ||
| 459 | # CONFIG_INPUT_MOUSE is not set | ||
| 460 | # CONFIG_INPUT_JOYSTICK is not set | ||
| 461 | # CONFIG_INPUT_TABLET is not set | ||
| 462 | # CONFIG_INPUT_TOUCHSCREEN is not set | ||
| 463 | # CONFIG_INPUT_MISC is not set | ||
| 464 | 547 | ||
| 465 | # | 548 | # |
| 466 | # Hardware I/O ports | 549 | # Hardware I/O ports |
| @@ -517,10 +600,11 @@ CONFIG_LEGACY_PTY_COUNT=256 | |||
| 517 | CONFIG_DEVPORT=y | 600 | CONFIG_DEVPORT=y |
| 518 | # CONFIG_I2C is not set | 601 | # CONFIG_I2C is not set |
| 519 | # CONFIG_SPI is not set | 602 | # CONFIG_SPI is not set |
| 520 | CONFIG_HAVE_GPIO_LIB=y | 603 | CONFIG_ARCH_REQUIRE_GPIOLIB=y |
| 604 | CONFIG_GPIOLIB=y | ||
| 521 | 605 | ||
| 522 | # | 606 | # |
| 523 | # GPIO Support | 607 | # Memory mapped GPIO expanders: |
| 524 | # | 608 | # |
| 525 | 609 | ||
| 526 | # | 610 | # |
| @@ -528,6 +612,11 @@ CONFIG_HAVE_GPIO_LIB=y | |||
| 528 | # | 612 | # |
| 529 | 613 | ||
| 530 | # | 614 | # |
| 615 | # PCI GPIO expanders: | ||
| 616 | # | ||
| 617 | # CONFIG_GPIO_BT8XX is not set | ||
| 618 | |||
| 619 | # | ||
| 531 | # SPI GPIO expanders: | 620 | # SPI GPIO expanders: |
| 532 | # | 621 | # |
| 533 | # CONFIG_W1 is not set | 622 | # CONFIG_W1 is not set |
| @@ -542,6 +631,7 @@ CONFIG_WATCHDOG=y | |||
| 542 | # Watchdog Device Drivers | 631 | # Watchdog Device Drivers |
| 543 | # | 632 | # |
| 544 | # CONFIG_SOFT_WATCHDOG is not set | 633 | # CONFIG_SOFT_WATCHDOG is not set |
| 634 | # CONFIG_ALIM7101_WDT is not set | ||
| 545 | CONFIG_TXX9_WDT=y | 635 | CONFIG_TXX9_WDT=y |
| 546 | 636 | ||
| 547 | # | 637 | # |
| @@ -549,18 +639,21 @@ CONFIG_TXX9_WDT=y | |||
| 549 | # | 639 | # |
| 550 | # CONFIG_PCIPCWATCHDOG is not set | 640 | # CONFIG_PCIPCWATCHDOG is not set |
| 551 | # CONFIG_WDTPCI is not set | 641 | # CONFIG_WDTPCI is not set |
| 642 | CONFIG_SSB_POSSIBLE=y | ||
| 552 | 643 | ||
| 553 | # | 644 | # |
| 554 | # Sonics Silicon Backplane | 645 | # Sonics Silicon Backplane |
| 555 | # | 646 | # |
| 556 | CONFIG_SSB_POSSIBLE=y | ||
| 557 | # CONFIG_SSB is not set | 647 | # CONFIG_SSB is not set |
| 558 | 648 | ||
| 559 | # | 649 | # |
| 560 | # Multifunction device drivers | 650 | # Multifunction device drivers |
| 561 | # | 651 | # |
| 652 | # CONFIG_MFD_CORE is not set | ||
| 562 | # CONFIG_MFD_SM501 is not set | 653 | # CONFIG_MFD_SM501 is not set |
| 563 | # CONFIG_HTC_PASIC3 is not set | 654 | # CONFIG_HTC_PASIC3 is not set |
| 655 | # CONFIG_MFD_TMIO is not set | ||
| 656 | # CONFIG_REGULATOR is not set | ||
| 564 | 657 | ||
| 565 | # | 658 | # |
| 566 | # Multimedia devices | 659 | # Multimedia devices |
| @@ -591,16 +684,26 @@ CONFIG_SSB_POSSIBLE=y | |||
| 591 | # Display device support | 684 | # Display device support |
| 592 | # | 685 | # |
| 593 | # CONFIG_DISPLAY_SUPPORT is not set | 686 | # CONFIG_DISPLAY_SUPPORT is not set |
| 594 | |||
| 595 | # | ||
| 596 | # Sound | ||
| 597 | # | ||
| 598 | # CONFIG_SOUND is not set | 687 | # CONFIG_SOUND is not set |
| 599 | # CONFIG_HID_SUPPORT is not set | ||
| 600 | # CONFIG_USB_SUPPORT is not set | 688 | # CONFIG_USB_SUPPORT is not set |
| 601 | # CONFIG_MMC is not set | 689 | # CONFIG_MMC is not set |
| 602 | # CONFIG_MEMSTICK is not set | 690 | # CONFIG_MEMSTICK is not set |
| 603 | # CONFIG_NEW_LEDS is not set | 691 | CONFIG_NEW_LEDS=y |
| 692 | CONFIG_LEDS_CLASS=y | ||
| 693 | |||
| 694 | # | ||
| 695 | # LED drivers | ||
| 696 | # | ||
| 697 | CONFIG_LEDS_GPIO=y | ||
| 698 | |||
| 699 | # | ||
| 700 | # LED Triggers | ||
| 701 | # | ||
| 702 | CONFIG_LEDS_TRIGGERS=y | ||
| 703 | # CONFIG_LEDS_TRIGGER_TIMER is not set | ||
| 704 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 705 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 706 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | ||
| 604 | # CONFIG_ACCESSIBILITY is not set | 707 | # CONFIG_ACCESSIBILITY is not set |
| 605 | # CONFIG_INFINIBAND is not set | 708 | # CONFIG_INFINIBAND is not set |
| 606 | CONFIG_RTC_LIB=y | 709 | CONFIG_RTC_LIB=y |
| @@ -626,27 +729,34 @@ CONFIG_RTC_INTF_DEV=y | |||
| 626 | # Platform RTC drivers | 729 | # Platform RTC drivers |
| 627 | # | 730 | # |
| 628 | # CONFIG_RTC_DRV_CMOS is not set | 731 | # CONFIG_RTC_DRV_CMOS is not set |
| 732 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 629 | # CONFIG_RTC_DRV_DS1511 is not set | 733 | # CONFIG_RTC_DRV_DS1511 is not set |
| 630 | # CONFIG_RTC_DRV_DS1553 is not set | 734 | # CONFIG_RTC_DRV_DS1553 is not set |
| 631 | CONFIG_RTC_DRV_DS1742=y | 735 | CONFIG_RTC_DRV_DS1742=y |
| 632 | # CONFIG_RTC_DRV_STK17TA8 is not set | 736 | # CONFIG_RTC_DRV_STK17TA8 is not set |
| 633 | # CONFIG_RTC_DRV_M48T86 is not set | 737 | # CONFIG_RTC_DRV_M48T86 is not set |
| 738 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 634 | # CONFIG_RTC_DRV_M48T59 is not set | 739 | # CONFIG_RTC_DRV_M48T59 is not set |
| 740 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 635 | # CONFIG_RTC_DRV_V3020 is not set | 741 | # CONFIG_RTC_DRV_V3020 is not set |
| 636 | 742 | ||
| 637 | # | 743 | # |
| 638 | # on-CPU RTC drivers | 744 | # on-CPU RTC drivers |
| 639 | # | 745 | # |
| 746 | # CONFIG_DMADEVICES is not set | ||
| 640 | # CONFIG_UIO is not set | 747 | # CONFIG_UIO is not set |
| 748 | # CONFIG_STAGING is not set | ||
| 641 | 749 | ||
| 642 | # | 750 | # |
| 643 | # File systems | 751 | # File systems |
| 644 | # | 752 | # |
| 645 | # CONFIG_EXT2_FS is not set | 753 | # CONFIG_EXT2_FS is not set |
| 646 | # CONFIG_EXT3_FS is not set | 754 | # CONFIG_EXT3_FS is not set |
| 755 | # CONFIG_EXT4_FS is not set | ||
| 647 | # CONFIG_REISERFS_FS is not set | 756 | # CONFIG_REISERFS_FS is not set |
| 648 | # CONFIG_JFS_FS is not set | 757 | # CONFIG_JFS_FS is not set |
| 649 | # CONFIG_FS_POSIX_ACL is not set | 758 | # CONFIG_FS_POSIX_ACL is not set |
| 759 | CONFIG_FILE_LOCKING=y | ||
| 650 | # CONFIG_XFS_FS is not set | 760 | # CONFIG_XFS_FS is not set |
| 651 | # CONFIG_OCFS2_FS is not set | 761 | # CONFIG_OCFS2_FS is not set |
| 652 | CONFIG_DNOTIFY=y | 762 | CONFIG_DNOTIFY=y |
| @@ -676,28 +786,17 @@ CONFIG_INOTIFY_USER=y | |||
| 676 | CONFIG_PROC_FS=y | 786 | CONFIG_PROC_FS=y |
| 677 | CONFIG_PROC_KCORE=y | 787 | CONFIG_PROC_KCORE=y |
| 678 | CONFIG_PROC_SYSCTL=y | 788 | CONFIG_PROC_SYSCTL=y |
| 789 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 679 | CONFIG_SYSFS=y | 790 | CONFIG_SYSFS=y |
| 680 | # CONFIG_TMPFS is not set | 791 | # CONFIG_TMPFS is not set |
| 681 | # CONFIG_HUGETLB_PAGE is not set | 792 | # CONFIG_HUGETLB_PAGE is not set |
| 682 | # CONFIG_CONFIGFS_FS is not set | 793 | # CONFIG_CONFIGFS_FS is not set |
| 683 | 794 | # CONFIG_MISC_FILESYSTEMS is not set | |
| 684 | # | ||
| 685 | # Miscellaneous filesystems | ||
| 686 | # | ||
| 687 | # CONFIG_HFSPLUS_FS is not set | ||
| 688 | # CONFIG_CRAMFS is not set | ||
| 689 | # CONFIG_VXFS_FS is not set | ||
| 690 | # CONFIG_MINIX_FS is not set | ||
| 691 | # CONFIG_HPFS_FS is not set | ||
| 692 | # CONFIG_QNX4FS_FS is not set | ||
| 693 | # CONFIG_ROMFS_FS is not set | ||
| 694 | # CONFIG_SYSV_FS is not set | ||
| 695 | # CONFIG_UFS_FS is not set | ||
| 696 | CONFIG_NETWORK_FILESYSTEMS=y | 795 | CONFIG_NETWORK_FILESYSTEMS=y |
| 697 | CONFIG_NFS_FS=y | 796 | CONFIG_NFS_FS=y |
| 698 | # CONFIG_NFS_V3 is not set | 797 | # CONFIG_NFS_V3 is not set |
| 699 | # CONFIG_NFSD is not set | ||
| 700 | CONFIG_ROOT_NFS=y | 798 | CONFIG_ROOT_NFS=y |
| 799 | # CONFIG_NFSD is not set | ||
| 701 | CONFIG_LOCKD=y | 800 | CONFIG_LOCKD=y |
| 702 | CONFIG_NFS_COMMON=y | 801 | CONFIG_NFS_COMMON=y |
| 703 | CONFIG_SUNRPC=y | 802 | CONFIG_SUNRPC=y |
| @@ -726,7 +825,16 @@ CONFIG_FRAME_WARN=1024 | |||
| 726 | # CONFIG_DEBUG_FS is not set | 825 | # CONFIG_DEBUG_FS is not set |
| 727 | # CONFIG_HEADERS_CHECK is not set | 826 | # CONFIG_HEADERS_CHECK is not set |
| 728 | # CONFIG_DEBUG_KERNEL is not set | 827 | # CONFIG_DEBUG_KERNEL is not set |
| 828 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 829 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 830 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 831 | |||
| 832 | # | ||
| 833 | # Tracers | ||
| 834 | # | ||
| 835 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 729 | # CONFIG_SAMPLES is not set | 836 | # CONFIG_SAMPLES is not set |
| 837 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 730 | CONFIG_CMDLINE="" | 838 | CONFIG_CMDLINE="" |
| 731 | 839 | ||
| 732 | # | 840 | # |
| @@ -734,15 +842,18 @@ CONFIG_CMDLINE="" | |||
| 734 | # | 842 | # |
| 735 | # CONFIG_KEYS is not set | 843 | # CONFIG_KEYS is not set |
| 736 | # CONFIG_SECURITY is not set | 844 | # CONFIG_SECURITY is not set |
| 845 | # CONFIG_SECURITYFS is not set | ||
| 846 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 737 | # CONFIG_CRYPTO is not set | 847 | # CONFIG_CRYPTO is not set |
| 738 | 848 | ||
| 739 | # | 849 | # |
| 740 | # Library routines | 850 | # Library routines |
| 741 | # | 851 | # |
| 742 | CONFIG_BITREVERSE=y | 852 | CONFIG_BITREVERSE=y |
| 743 | # CONFIG_GENERIC_FIND_FIRST_BIT is not set | 853 | CONFIG_GENERIC_FIND_LAST_BIT=y |
| 744 | # CONFIG_CRC_CCITT is not set | 854 | # CONFIG_CRC_CCITT is not set |
| 745 | # CONFIG_CRC16 is not set | 855 | # CONFIG_CRC16 is not set |
| 856 | # CONFIG_CRC_T10DIF is not set | ||
| 746 | # CONFIG_CRC_ITU_T is not set | 857 | # CONFIG_CRC_ITU_T is not set |
| 747 | CONFIG_CRC32=y | 858 | CONFIG_CRC32=y |
| 748 | # CONFIG_CRC7 is not set | 859 | # CONFIG_CRC7 is not set |
diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/markeins_defconfig index fea9bc9865a3..bad8901f8f3c 100644 --- a/arch/mips/configs/emma2rh_defconfig +++ b/arch/mips/configs/markeins_defconfig | |||
| @@ -35,7 +35,7 @@ CONFIG_ZONE_DMA=y | |||
| 35 | # CONFIG_PNX8550_STB810 is not set | 35 | # CONFIG_PNX8550_STB810 is not set |
| 36 | # CONFIG_MACH_VR41XX is not set | 36 | # CONFIG_MACH_VR41XX is not set |
| 37 | # CONFIG_PMC_YOSEMITE is not set | 37 | # CONFIG_PMC_YOSEMITE is not set |
| 38 | CONFIG_MARKEINS=y | 38 | CONFIG_NEC_MARKEINS=y |
| 39 | # CONFIG_SGI_IP22 is not set | 39 | # CONFIG_SGI_IP22 is not set |
| 40 | # CONFIG_SGI_IP27 is not set | 40 | # CONFIG_SGI_IP27 is not set |
| 41 | # CONFIG_SGI_IP32 is not set | 41 | # CONFIG_SGI_IP32 is not set |
| @@ -68,7 +68,7 @@ CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y | |||
| 68 | CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y | 68 | CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y |
| 69 | CONFIG_IRQ_CPU=y | 69 | CONFIG_IRQ_CPU=y |
| 70 | CONFIG_SWAP_IO_SPACE=y | 70 | CONFIG_SWAP_IO_SPACE=y |
| 71 | CONFIG_EMMA2RH=y | 71 | CONFIG_SOC_EMMA2RH=y |
| 72 | CONFIG_MIPS_L1_CACHE_SHIFT=5 | 72 | CONFIG_MIPS_L1_CACHE_SHIFT=5 |
| 73 | 73 | ||
| 74 | # | 74 | # |
| @@ -574,9 +574,9 @@ CONFIG_MTD_CFI_UTIL=y | |||
| 574 | # | 574 | # |
| 575 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | 575 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set |
| 576 | CONFIG_MTD_PHYSMAP=y | 576 | CONFIG_MTD_PHYSMAP=y |
| 577 | CONFIG_MTD_PHYSMAP_START=0x1e000000 | 577 | CONFIG_MTD_PHYSMAP_START=0x0 |
| 578 | CONFIG_MTD_PHYSMAP_LEN=0x02000000 | 578 | CONFIG_MTD_PHYSMAP_LEN=0x0 |
| 579 | CONFIG_MTD_PHYSMAP_BANKWIDTH=2 | 579 | CONFIG_MTD_PHYSMAP_BANKWIDTH=0 |
| 580 | # CONFIG_MTD_PLATRAM is not set | 580 | # CONFIG_MTD_PLATRAM is not set |
| 581 | 581 | ||
| 582 | # | 582 | # |
diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig index 83d5c58662c8..1efe977497dd 100644 --- a/arch/mips/configs/rbtx49xx_defconfig +++ b/arch/mips/configs/rbtx49xx_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.26-rc9 | 3 | # Linux kernel version: 2.6.29-rc7 |
| 4 | # Fri Jul 11 23:03:21 2008 | 4 | # Wed Mar 4 23:08:06 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_MIPS=y | 6 | CONFIG_MIPS=y |
| 7 | 7 | ||
| @@ -18,8 +18,10 @@ CONFIG_MIPS=y | |||
| 18 | # CONFIG_LEMOTE_FULONG is not set | 18 | # CONFIG_LEMOTE_FULONG is not set |
| 19 | # CONFIG_MIPS_MALTA is not set | 19 | # CONFIG_MIPS_MALTA is not set |
| 20 | # CONFIG_MIPS_SIM is not set | 20 | # CONFIG_MIPS_SIM is not set |
| 21 | # CONFIG_MARKEINS is not set | 21 | # CONFIG_MACH_EMMA is not set |
| 22 | # CONFIG_MACH_VR41XX is not set | 22 | # CONFIG_MACH_VR41XX is not set |
| 23 | # CONFIG_NXP_STB220 is not set | ||
| 24 | # CONFIG_NXP_STB225 is not set | ||
| 23 | # CONFIG_PNX8550_JBS is not set | 25 | # CONFIG_PNX8550_JBS is not set |
| 24 | # CONFIG_PNX8550_STB810 is not set | 26 | # CONFIG_PNX8550_STB810 is not set |
| 25 | # CONFIG_PMC_MSP is not set | 27 | # CONFIG_PMC_MSP is not set |
| @@ -39,20 +41,28 @@ CONFIG_MIPS=y | |||
| 39 | # CONFIG_SNI_RM is not set | 41 | # CONFIG_SNI_RM is not set |
| 40 | # CONFIG_MACH_TX39XX is not set | 42 | # CONFIG_MACH_TX39XX is not set |
| 41 | CONFIG_MACH_TX49XX=y | 43 | CONFIG_MACH_TX49XX=y |
| 44 | # CONFIG_MIKROTIK_RB532 is not set | ||
| 42 | # CONFIG_WR_PPMC is not set | 45 | # CONFIG_WR_PPMC is not set |
| 46 | # CONFIG_CAVIUM_OCTEON_SIMULATOR is not set | ||
| 47 | # CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set | ||
| 48 | CONFIG_MACH_TXX9=y | ||
| 43 | CONFIG_TOSHIBA_RBTX4927=y | 49 | CONFIG_TOSHIBA_RBTX4927=y |
| 44 | CONFIG_TOSHIBA_RBTX4938=y | 50 | CONFIG_TOSHIBA_RBTX4938=y |
| 51 | CONFIG_TOSHIBA_RBTX4939=y | ||
| 45 | CONFIG_SOC_TX4927=y | 52 | CONFIG_SOC_TX4927=y |
| 46 | CONFIG_SOC_TX4938=y | 53 | CONFIG_SOC_TX4938=y |
| 54 | CONFIG_SOC_TX4939=y | ||
| 55 | CONFIG_TXX9_7SEGLED=y | ||
| 47 | # CONFIG_TOSHIBA_FPCIB0 is not set | 56 | # CONFIG_TOSHIBA_FPCIB0 is not set |
| 48 | CONFIG_PICMG_PCI_BACKPLANE_DEFAULT=y | 57 | CONFIG_PICMG_PCI_BACKPLANE_DEFAULT=y |
| 49 | 58 | ||
| 50 | # | 59 | # |
| 51 | # Multiplex Pin Select | 60 | # Multiplex Pin Select |
| 52 | # | 61 | # |
| 53 | CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61=y | 62 | # CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 is not set |
| 54 | # CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND is not set | 63 | # CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND is not set |
| 55 | # CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA is not set | 64 | # CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA is not set |
| 65 | CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP=y | ||
| 56 | CONFIG_PCI_TX4927=y | 66 | CONFIG_PCI_TX4927=y |
| 57 | CONFIG_RWSEM_GENERIC_SPINLOCK=y | 67 | CONFIG_RWSEM_GENERIC_SPINLOCK=y |
| 58 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set | 68 | # CONFIG_ARCH_HAS_ILOG2_U32 is not set |
| @@ -64,14 +74,18 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y | |||
| 64 | CONFIG_GENERIC_CLOCKEVENTS=y | 74 | CONFIG_GENERIC_CLOCKEVENTS=y |
| 65 | CONFIG_GENERIC_TIME=y | 75 | CONFIG_GENERIC_TIME=y |
| 66 | CONFIG_GENERIC_CMOS_UPDATE=y | 76 | CONFIG_GENERIC_CMOS_UPDATE=y |
| 67 | CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y | 77 | CONFIG_SCHED_OMIT_FRAME_POINTER=y |
| 68 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y | 78 | CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y |
| 79 | CONFIG_CEVT_R4K_LIB=y | ||
| 69 | CONFIG_CEVT_R4K=y | 80 | CONFIG_CEVT_R4K=y |
| 70 | CONFIG_CEVT_TXX9=y | 81 | CONFIG_CEVT_TXX9=y |
| 82 | CONFIG_CSRC_R4K_LIB=y | ||
| 71 | CONFIG_CSRC_R4K=y | 83 | CONFIG_CSRC_R4K=y |
| 72 | CONFIG_GPIO_TXX9=y | 84 | CONFIG_GPIO_TXX9=y |
| 73 | CONFIG_DMA_NONCOHERENT=y | 85 | CONFIG_DMA_NONCOHERENT=y |
| 74 | CONFIG_DMA_NEED_PCI_MAP_STATE=y | 86 | CONFIG_DMA_NEED_PCI_MAP_STATE=y |
| 87 | CONFIG_EARLY_PRINTK=y | ||
| 88 | CONFIG_SYS_HAS_EARLY_PRINTK=y | ||
| 75 | # CONFIG_HOTPLUG_CPU is not set | 89 | # CONFIG_HOTPLUG_CPU is not set |
| 76 | # CONFIG_NO_IOPORT is not set | 90 | # CONFIG_NO_IOPORT is not set |
| 77 | CONFIG_GENERIC_GPIO=y | 91 | CONFIG_GENERIC_GPIO=y |
| @@ -100,6 +114,7 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 | |||
| 100 | CONFIG_CPU_TX49XX=y | 114 | CONFIG_CPU_TX49XX=y |
| 101 | # CONFIG_CPU_R5000 is not set | 115 | # CONFIG_CPU_R5000 is not set |
| 102 | # CONFIG_CPU_R5432 is not set | 116 | # CONFIG_CPU_R5432 is not set |
| 117 | # CONFIG_CPU_R5500 is not set | ||
| 103 | # CONFIG_CPU_R6000 is not set | 118 | # CONFIG_CPU_R6000 is not set |
| 104 | # CONFIG_CPU_NEVADA is not set | 119 | # CONFIG_CPU_NEVADA is not set |
| 105 | # CONFIG_CPU_R8000 is not set | 120 | # CONFIG_CPU_R8000 is not set |
| @@ -107,6 +122,7 @@ CONFIG_CPU_TX49XX=y | |||
| 107 | # CONFIG_CPU_RM7000 is not set | 122 | # CONFIG_CPU_RM7000 is not set |
| 108 | # CONFIG_CPU_RM9000 is not set | 123 | # CONFIG_CPU_RM9000 is not set |
| 109 | # CONFIG_CPU_SB1 is not set | 124 | # CONFIG_CPU_SB1 is not set |
| 125 | # CONFIG_CPU_CAVIUM_OCTEON is not set | ||
| 110 | CONFIG_SYS_HAS_CPU_TX49XX=y | 126 | CONFIG_SYS_HAS_CPU_TX49XX=y |
| 111 | CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y | 127 | CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y |
| 112 | CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y | 128 | CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y |
| @@ -134,13 +150,12 @@ CONFIG_ARCH_FLATMEM_ENABLE=y | |||
| 134 | CONFIG_ARCH_POPULATES_NODE_MAP=y | 150 | CONFIG_ARCH_POPULATES_NODE_MAP=y |
| 135 | CONFIG_FLATMEM=y | 151 | CONFIG_FLATMEM=y |
| 136 | CONFIG_FLAT_NODE_MEM_MAP=y | 152 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 137 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 138 | # CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set | ||
| 139 | CONFIG_PAGEFLAGS_EXTENDED=y | 153 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 140 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 154 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 141 | # CONFIG_RESOURCES_64BIT is not set | 155 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 142 | CONFIG_ZONE_DMA_FLAG=0 | 156 | CONFIG_ZONE_DMA_FLAG=0 |
| 143 | CONFIG_VIRT_TO_BUS=y | 157 | CONFIG_VIRT_TO_BUS=y |
| 158 | CONFIG_UNEVICTABLE_LRU=y | ||
| 144 | CONFIG_TICK_ONESHOT=y | 159 | CONFIG_TICK_ONESHOT=y |
| 145 | CONFIG_NO_HZ=y | 160 | CONFIG_NO_HZ=y |
| 146 | CONFIG_HIGH_RES_TIMERS=y | 161 | CONFIG_HIGH_RES_TIMERS=y |
| @@ -176,6 +191,15 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 176 | # CONFIG_BSD_PROCESS_ACCT is not set | 191 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 177 | # CONFIG_TASKSTATS is not set | 192 | # CONFIG_TASKSTATS is not set |
| 178 | # CONFIG_AUDIT is not set | 193 | # CONFIG_AUDIT is not set |
| 194 | |||
| 195 | # | ||
| 196 | # RCU Subsystem | ||
| 197 | # | ||
| 198 | CONFIG_CLASSIC_RCU=y | ||
| 199 | # CONFIG_TREE_RCU is not set | ||
| 200 | # CONFIG_PREEMPT_RCU is not set | ||
| 201 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 202 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 179 | CONFIG_IKCONFIG=y | 203 | CONFIG_IKCONFIG=y |
| 180 | CONFIG_IKCONFIG_PROC=y | 204 | CONFIG_IKCONFIG_PROC=y |
| 181 | CONFIG_LOG_BUF_SHIFT=14 | 205 | CONFIG_LOG_BUF_SHIFT=14 |
| @@ -190,7 +214,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y | |||
| 190 | CONFIG_SYSCTL=y | 214 | CONFIG_SYSCTL=y |
| 191 | CONFIG_EMBEDDED=y | 215 | CONFIG_EMBEDDED=y |
| 192 | CONFIG_SYSCTL_SYSCALL=y | 216 | CONFIG_SYSCTL_SYSCALL=y |
| 193 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 194 | CONFIG_KALLSYMS=y | 217 | CONFIG_KALLSYMS=y |
| 195 | # CONFIG_KALLSYMS_EXTRA_PASS is not set | 218 | # CONFIG_KALLSYMS_EXTRA_PASS is not set |
| 196 | # CONFIG_HOTPLUG is not set | 219 | # CONFIG_HOTPLUG is not set |
| @@ -207,30 +230,26 @@ CONFIG_SIGNALFD=y | |||
| 207 | CONFIG_TIMERFD=y | 230 | CONFIG_TIMERFD=y |
| 208 | CONFIG_EVENTFD=y | 231 | CONFIG_EVENTFD=y |
| 209 | CONFIG_SHMEM=y | 232 | CONFIG_SHMEM=y |
| 233 | CONFIG_AIO=y | ||
| 210 | CONFIG_VM_EVENT_COUNTERS=y | 234 | CONFIG_VM_EVENT_COUNTERS=y |
| 235 | CONFIG_PCI_QUIRKS=y | ||
| 211 | CONFIG_SLAB=y | 236 | CONFIG_SLAB=y |
| 212 | # CONFIG_SLUB is not set | 237 | # CONFIG_SLUB is not set |
| 213 | # CONFIG_SLOB is not set | 238 | # CONFIG_SLOB is not set |
| 214 | # CONFIG_PROFILING is not set | 239 | # CONFIG_PROFILING is not set |
| 215 | # CONFIG_MARKERS is not set | ||
| 216 | CONFIG_HAVE_OPROFILE=y | 240 | CONFIG_HAVE_OPROFILE=y |
| 217 | # CONFIG_HAVE_KPROBES is not set | 241 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 218 | # CONFIG_HAVE_KRETPROBES is not set | ||
| 219 | # CONFIG_HAVE_DMA_ATTRS is not set | ||
| 220 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 221 | CONFIG_SLABINFO=y | 242 | CONFIG_SLABINFO=y |
| 222 | # CONFIG_TINY_SHMEM is not set | ||
| 223 | CONFIG_BASE_SMALL=0 | 243 | CONFIG_BASE_SMALL=0 |
| 224 | CONFIG_MODULES=y | 244 | CONFIG_MODULES=y |
| 225 | # CONFIG_MODULE_FORCE_LOAD is not set | 245 | # CONFIG_MODULE_FORCE_LOAD is not set |
| 226 | # CONFIG_MODULE_UNLOAD is not set | 246 | CONFIG_MODULE_UNLOAD=y |
| 227 | # CONFIG_MODVERSIONS is not set | 247 | # CONFIG_MODVERSIONS is not set |
| 228 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 248 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 229 | CONFIG_KMOD=y | ||
| 230 | CONFIG_BLOCK=y | 249 | CONFIG_BLOCK=y |
| 231 | # CONFIG_LBD is not set | 250 | # CONFIG_LBD is not set |
| 232 | # CONFIG_BLK_DEV_IO_TRACE is not set | 251 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 233 | # CONFIG_LSF is not set | 252 | # CONFIG_BLK_DEV_INTEGRITY is not set |
| 234 | 253 | ||
| 235 | # | 254 | # |
| 236 | # IO Schedulers | 255 | # IO Schedulers |
| @@ -244,7 +263,8 @@ CONFIG_DEFAULT_AS=y | |||
| 244 | # CONFIG_DEFAULT_CFQ is not set | 263 | # CONFIG_DEFAULT_CFQ is not set |
| 245 | # CONFIG_DEFAULT_NOOP is not set | 264 | # CONFIG_DEFAULT_NOOP is not set |
| 246 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 265 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 247 | CONFIG_CLASSIC_RCU=y | 266 | # CONFIG_PROBE_INITRD_HEADER is not set |
| 267 | # CONFIG_FREEZER is not set | ||
| 248 | 268 | ||
| 249 | # | 269 | # |
| 250 | # Bus options (PCI, PCMCIA, EISA, ISA, TC) | 270 | # Bus options (PCI, PCMCIA, EISA, ISA, TC) |
| @@ -254,12 +274,15 @@ CONFIG_PCI=y | |||
| 254 | CONFIG_PCI_DOMAINS=y | 274 | CONFIG_PCI_DOMAINS=y |
| 255 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 275 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 256 | # CONFIG_PCI_LEGACY is not set | 276 | # CONFIG_PCI_LEGACY is not set |
| 277 | # CONFIG_PCI_STUB is not set | ||
| 257 | CONFIG_MMU=y | 278 | CONFIG_MMU=y |
| 258 | 279 | ||
| 259 | # | 280 | # |
| 260 | # Executable file formats | 281 | # Executable file formats |
| 261 | # | 282 | # |
| 262 | CONFIG_BINFMT_ELF=y | 283 | CONFIG_BINFMT_ELF=y |
| 284 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 285 | # CONFIG_HAVE_AOUT is not set | ||
| 263 | # CONFIG_BINFMT_MISC is not set | 286 | # CONFIG_BINFMT_MISC is not set |
| 264 | CONFIG_TRAD_SIGNALS=y | 287 | CONFIG_TRAD_SIGNALS=y |
| 265 | 288 | ||
| @@ -268,15 +291,12 @@ CONFIG_TRAD_SIGNALS=y | |||
| 268 | # | 291 | # |
| 269 | CONFIG_ARCH_SUSPEND_POSSIBLE=y | 292 | CONFIG_ARCH_SUSPEND_POSSIBLE=y |
| 270 | # CONFIG_PM is not set | 293 | # CONFIG_PM is not set |
| 271 | |||
| 272 | # | ||
| 273 | # Networking | ||
| 274 | # | ||
| 275 | CONFIG_NET=y | 294 | CONFIG_NET=y |
| 276 | 295 | ||
| 277 | # | 296 | # |
| 278 | # Networking options | 297 | # Networking options |
| 279 | # | 298 | # |
| 299 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 280 | CONFIG_PACKET=y | 300 | CONFIG_PACKET=y |
| 281 | # CONFIG_PACKET_MMAP is not set | 301 | # CONFIG_PACKET_MMAP is not set |
| 282 | CONFIG_UNIX=y | 302 | CONFIG_UNIX=y |
| @@ -318,6 +338,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 318 | # CONFIG_IPX is not set | 338 | # CONFIG_IPX is not set |
| 319 | # CONFIG_ATALK is not set | 339 | # CONFIG_ATALK is not set |
| 320 | # CONFIG_NET_SCHED is not set | 340 | # CONFIG_NET_SCHED is not set |
| 341 | # CONFIG_DCB is not set | ||
| 321 | 342 | ||
| 322 | # | 343 | # |
| 323 | # Network testing | 344 | # Network testing |
| @@ -327,14 +348,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic" | |||
| 327 | # CONFIG_CAN is not set | 348 | # CONFIG_CAN is not set |
| 328 | # CONFIG_IRDA is not set | 349 | # CONFIG_IRDA is not set |
| 329 | # CONFIG_BT is not set | 350 | # CONFIG_BT is not set |
| 330 | 351 | # CONFIG_PHONET is not set | |
| 331 | # | 352 | # CONFIG_WIRELESS is not set |
| 332 | # Wireless | 353 | # CONFIG_WIMAX is not set |
| 333 | # | ||
| 334 | # CONFIG_CFG80211 is not set | ||
| 335 | # CONFIG_WIRELESS_EXT is not set | ||
| 336 | # CONFIG_MAC80211 is not set | ||
| 337 | # CONFIG_IEEE80211 is not set | ||
| 338 | # CONFIG_RFKILL is not set | 354 | # CONFIG_RFKILL is not set |
| 339 | 355 | ||
| 340 | # | 356 | # |
| @@ -348,7 +364,90 @@ CONFIG_STANDALONE=y | |||
| 348 | CONFIG_PREVENT_FIRMWARE_BUILD=y | 364 | CONFIG_PREVENT_FIRMWARE_BUILD=y |
| 349 | # CONFIG_SYS_HYPERVISOR is not set | 365 | # CONFIG_SYS_HYPERVISOR is not set |
| 350 | # CONFIG_CONNECTOR is not set | 366 | # CONFIG_CONNECTOR is not set |
| 351 | # CONFIG_MTD is not set | 367 | CONFIG_MTD=y |
| 368 | # CONFIG_MTD_DEBUG is not set | ||
| 369 | # CONFIG_MTD_CONCAT is not set | ||
| 370 | CONFIG_MTD_PARTITIONS=y | ||
| 371 | # CONFIG_MTD_TESTS is not set | ||
| 372 | # CONFIG_MTD_REDBOOT_PARTS is not set | ||
| 373 | CONFIG_MTD_CMDLINE_PARTS=y | ||
| 374 | # CONFIG_MTD_AR7_PARTS is not set | ||
| 375 | |||
| 376 | # | ||
| 377 | # User Modules And Translation Layers | ||
| 378 | # | ||
| 379 | CONFIG_MTD_CHAR=y | ||
| 380 | # CONFIG_MTD_BLKDEVS is not set | ||
| 381 | # CONFIG_MTD_BLOCK is not set | ||
| 382 | # CONFIG_MTD_BLOCK_RO is not set | ||
| 383 | # CONFIG_FTL is not set | ||
| 384 | # CONFIG_NFTL is not set | ||
| 385 | # CONFIG_INFTL is not set | ||
| 386 | # CONFIG_RFD_FTL is not set | ||
| 387 | # CONFIG_SSFDC is not set | ||
| 388 | # CONFIG_MTD_OOPS is not set | ||
| 389 | |||
| 390 | # | ||
| 391 | # RAM/ROM/Flash chip drivers | ||
| 392 | # | ||
| 393 | CONFIG_MTD_CFI=y | ||
| 394 | CONFIG_MTD_JEDECPROBE=y | ||
| 395 | CONFIG_MTD_GEN_PROBE=y | ||
| 396 | # CONFIG_MTD_CFI_ADV_OPTIONS is not set | ||
| 397 | CONFIG_MTD_MAP_BANK_WIDTH_1=y | ||
| 398 | CONFIG_MTD_MAP_BANK_WIDTH_2=y | ||
| 399 | CONFIG_MTD_MAP_BANK_WIDTH_4=y | ||
| 400 | # CONFIG_MTD_MAP_BANK_WIDTH_8 is not set | ||
| 401 | # CONFIG_MTD_MAP_BANK_WIDTH_16 is not set | ||
| 402 | # CONFIG_MTD_MAP_BANK_WIDTH_32 is not set | ||
| 403 | CONFIG_MTD_CFI_I1=y | ||
| 404 | CONFIG_MTD_CFI_I2=y | ||
| 405 | # CONFIG_MTD_CFI_I4 is not set | ||
| 406 | # CONFIG_MTD_CFI_I8 is not set | ||
| 407 | # CONFIG_MTD_CFI_INTELEXT is not set | ||
| 408 | CONFIG_MTD_CFI_AMDSTD=y | ||
| 409 | # CONFIG_MTD_CFI_STAA is not set | ||
| 410 | CONFIG_MTD_CFI_UTIL=y | ||
| 411 | # CONFIG_MTD_RAM is not set | ||
| 412 | # CONFIG_MTD_ROM is not set | ||
| 413 | # CONFIG_MTD_ABSENT is not set | ||
| 414 | |||
| 415 | # | ||
| 416 | # Mapping drivers for chip access | ||
| 417 | # | ||
| 418 | # CONFIG_MTD_COMPLEX_MAPPINGS is not set | ||
| 419 | CONFIG_MTD_PHYSMAP=y | ||
| 420 | # CONFIG_MTD_PHYSMAP_COMPAT is not set | ||
| 421 | # CONFIG_MTD_INTEL_VR_NOR is not set | ||
| 422 | # CONFIG_MTD_PLATRAM is not set | ||
| 423 | |||
| 424 | # | ||
| 425 | # Self-contained MTD device drivers | ||
| 426 | # | ||
| 427 | # CONFIG_MTD_PMC551 is not set | ||
| 428 | # CONFIG_MTD_SLRAM is not set | ||
| 429 | # CONFIG_MTD_PHRAM is not set | ||
| 430 | # CONFIG_MTD_MTDRAM is not set | ||
| 431 | # CONFIG_MTD_BLOCK2MTD is not set | ||
| 432 | |||
| 433 | # | ||
| 434 | # Disk-On-Chip Device Drivers | ||
| 435 | # | ||
| 436 | # CONFIG_MTD_DOC2000 is not set | ||
| 437 | # CONFIG_MTD_DOC2001 is not set | ||
| 438 | # CONFIG_MTD_DOC2001PLUS is not set | ||
| 439 | # CONFIG_MTD_NAND is not set | ||
| 440 | # CONFIG_MTD_ONENAND is not set | ||
| 441 | |||
| 442 | # | ||
| 443 | # LPDDR flash memory drivers | ||
| 444 | # | ||
| 445 | # CONFIG_MTD_LPDDR is not set | ||
| 446 | |||
| 447 | # | ||
| 448 | # UBI - Unsorted block images | ||
| 449 | # | ||
| 450 | # CONFIG_MTD_UBI is not set | ||
| 352 | # CONFIG_PARPORT is not set | 451 | # CONFIG_PARPORT is not set |
| 353 | CONFIG_BLK_DEV=y | 452 | CONFIG_BLK_DEV=y |
| 354 | # CONFIG_BLK_CPQ_DA is not set | 453 | # CONFIG_BLK_CPQ_DA is not set |
| @@ -365,9 +464,60 @@ CONFIG_BLK_DEV_RAM_SIZE=8192 | |||
| 365 | # CONFIG_BLK_DEV_XIP is not set | 464 | # CONFIG_BLK_DEV_XIP is not set |
| 366 | # CONFIG_CDROM_PKTCDVD is not set | 465 | # CONFIG_CDROM_PKTCDVD is not set |
| 367 | # CONFIG_ATA_OVER_ETH is not set | 466 | # CONFIG_ATA_OVER_ETH is not set |
| 467 | # CONFIG_BLK_DEV_HD is not set | ||
| 368 | # CONFIG_MISC_DEVICES is not set | 468 | # CONFIG_MISC_DEVICES is not set |
| 369 | CONFIG_HAVE_IDE=y | 469 | CONFIG_HAVE_IDE=y |
| 370 | # CONFIG_IDE is not set | 470 | CONFIG_IDE=y |
| 471 | |||
| 472 | # | ||
| 473 | # Please see Documentation/ide/ide.txt for help/info on IDE drives | ||
| 474 | # | ||
| 475 | CONFIG_IDE_TIMINGS=y | ||
| 476 | # CONFIG_BLK_DEV_IDE_SATA is not set | ||
| 477 | CONFIG_IDE_GD=y | ||
| 478 | CONFIG_IDE_GD_ATA=y | ||
| 479 | # CONFIG_IDE_GD_ATAPI is not set | ||
| 480 | # CONFIG_BLK_DEV_IDECD is not set | ||
| 481 | # CONFIG_BLK_DEV_IDETAPE is not set | ||
| 482 | # CONFIG_IDE_TASK_IOCTL is not set | ||
| 483 | CONFIG_IDE_PROC_FS=y | ||
| 484 | |||
| 485 | # | ||
| 486 | # IDE chipset support/bugfixes | ||
| 487 | # | ||
| 488 | # CONFIG_IDE_GENERIC is not set | ||
| 489 | # CONFIG_BLK_DEV_PLATFORM is not set | ||
| 490 | CONFIG_BLK_DEV_IDEDMA_SFF=y | ||
| 491 | |||
| 492 | # | ||
| 493 | # PCI IDE chipsets support | ||
| 494 | # | ||
| 495 | # CONFIG_BLK_DEV_GENERIC is not set | ||
| 496 | # CONFIG_BLK_DEV_AEC62XX is not set | ||
| 497 | # CONFIG_BLK_DEV_ALI15X3 is not set | ||
| 498 | # CONFIG_BLK_DEV_AMD74XX is not set | ||
| 499 | # CONFIG_BLK_DEV_CMD64X is not set | ||
| 500 | # CONFIG_BLK_DEV_TRIFLEX is not set | ||
| 501 | # CONFIG_BLK_DEV_CS5530 is not set | ||
| 502 | # CONFIG_BLK_DEV_HPT366 is not set | ||
| 503 | # CONFIG_BLK_DEV_JMICRON is not set | ||
| 504 | # CONFIG_BLK_DEV_SC1200 is not set | ||
| 505 | # CONFIG_BLK_DEV_PIIX is not set | ||
| 506 | # CONFIG_BLK_DEV_IT8172 is not set | ||
| 507 | # CONFIG_BLK_DEV_IT8213 is not set | ||
| 508 | # CONFIG_BLK_DEV_IT821X is not set | ||
| 509 | # CONFIG_BLK_DEV_NS87415 is not set | ||
| 510 | # CONFIG_BLK_DEV_PDC202XX_OLD is not set | ||
| 511 | # CONFIG_BLK_DEV_PDC202XX_NEW is not set | ||
| 512 | # CONFIG_BLK_DEV_SVWKS is not set | ||
| 513 | # CONFIG_BLK_DEV_SIIMAGE is not set | ||
| 514 | # CONFIG_BLK_DEV_SLC90E66 is not set | ||
| 515 | # CONFIG_BLK_DEV_TRM290 is not set | ||
| 516 | # CONFIG_BLK_DEV_VIA82CXXX is not set | ||
| 517 | # CONFIG_BLK_DEV_TC86C001 is not set | ||
| 518 | CONFIG_BLK_DEV_IDE_TX4938=y | ||
| 519 | CONFIG_BLK_DEV_IDE_TX4939=y | ||
| 520 | CONFIG_BLK_DEV_IDEDMA=y | ||
| 371 | 521 | ||
| 372 | # | 522 | # |
| 373 | # SCSI device support | 523 | # SCSI device support |
| @@ -390,7 +540,6 @@ CONFIG_HAVE_IDE=y | |||
| 390 | # CONFIG_IEEE1394 is not set | 540 | # CONFIG_IEEE1394 is not set |
| 391 | # CONFIG_I2O is not set | 541 | # CONFIG_I2O is not set |
| 392 | CONFIG_NETDEVICES=y | 542 | CONFIG_NETDEVICES=y |
| 393 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 394 | # CONFIG_DUMMY is not set | 543 | # CONFIG_DUMMY is not set |
| 395 | # CONFIG_BONDING is not set | 544 | # CONFIG_BONDING is not set |
| 396 | # CONFIG_EQUALIZER is not set | 545 | # CONFIG_EQUALIZER is not set |
| @@ -412,15 +561,19 @@ CONFIG_PHYLIB=y | |||
| 412 | # CONFIG_BROADCOM_PHY is not set | 561 | # CONFIG_BROADCOM_PHY is not set |
| 413 | # CONFIG_ICPLUS_PHY is not set | 562 | # CONFIG_ICPLUS_PHY is not set |
| 414 | # CONFIG_REALTEK_PHY is not set | 563 | # CONFIG_REALTEK_PHY is not set |
| 564 | # CONFIG_NATIONAL_PHY is not set | ||
| 565 | # CONFIG_STE10XP is not set | ||
| 566 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 415 | # CONFIG_FIXED_PHY is not set | 567 | # CONFIG_FIXED_PHY is not set |
| 416 | # CONFIG_MDIO_BITBANG is not set | 568 | # CONFIG_MDIO_BITBANG is not set |
| 417 | CONFIG_NET_ETHERNET=y | 569 | CONFIG_NET_ETHERNET=y |
| 418 | # CONFIG_MII is not set | 570 | CONFIG_MII=y |
| 419 | # CONFIG_AX88796 is not set | 571 | # CONFIG_AX88796 is not set |
| 420 | # CONFIG_HAPPYMEAL is not set | 572 | # CONFIG_HAPPYMEAL is not set |
| 421 | # CONFIG_SUNGEM is not set | 573 | # CONFIG_SUNGEM is not set |
| 422 | # CONFIG_CASSINI is not set | 574 | # CONFIG_CASSINI is not set |
| 423 | # CONFIG_NET_VENDOR_3COM is not set | 575 | # CONFIG_NET_VENDOR_3COM is not set |
| 576 | CONFIG_SMC91X=y | ||
| 424 | # CONFIG_DM9000 is not set | 577 | # CONFIG_DM9000 is not set |
| 425 | # CONFIG_NET_TULIP is not set | 578 | # CONFIG_NET_TULIP is not set |
| 426 | # CONFIG_HP100 is not set | 579 | # CONFIG_HP100 is not set |
| @@ -429,6 +582,9 @@ CONFIG_NE2000=y | |||
| 429 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 582 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 430 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 583 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 431 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 584 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 585 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 586 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 587 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 432 | CONFIG_NET_PCI=y | 588 | CONFIG_NET_PCI=y |
| 433 | # CONFIG_PCNET32 is not set | 589 | # CONFIG_PCNET32 is not set |
| 434 | # CONFIG_AMD8111_ETH is not set | 590 | # CONFIG_AMD8111_ETH is not set |
| @@ -436,7 +592,6 @@ CONFIG_NET_PCI=y | |||
| 436 | # CONFIG_B44 is not set | 592 | # CONFIG_B44 is not set |
| 437 | # CONFIG_FORCEDETH is not set | 593 | # CONFIG_FORCEDETH is not set |
| 438 | CONFIG_TC35815=y | 594 | CONFIG_TC35815=y |
| 439 | # CONFIG_EEPRO100 is not set | ||
| 440 | # CONFIG_E100 is not set | 595 | # CONFIG_E100 is not set |
| 441 | # CONFIG_FEALNX is not set | 596 | # CONFIG_FEALNX is not set |
| 442 | # CONFIG_NATSEMI is not set | 597 | # CONFIG_NATSEMI is not set |
| @@ -445,9 +600,11 @@ CONFIG_TC35815=y | |||
| 445 | # CONFIG_R6040 is not set | 600 | # CONFIG_R6040 is not set |
| 446 | # CONFIG_SIS900 is not set | 601 | # CONFIG_SIS900 is not set |
| 447 | # CONFIG_EPIC100 is not set | 602 | # CONFIG_EPIC100 is not set |
| 603 | # CONFIG_SMSC9420 is not set | ||
| 448 | # CONFIG_SUNDANCE is not set | 604 | # CONFIG_SUNDANCE is not set |
| 449 | # CONFIG_TLAN is not set | 605 | # CONFIG_TLAN is not set |
| 450 | # CONFIG_VIA_RHINE is not set | 606 | # CONFIG_VIA_RHINE is not set |
| 607 | # CONFIG_ATL2 is not set | ||
| 451 | # CONFIG_NETDEV_1000 is not set | 608 | # CONFIG_NETDEV_1000 is not set |
| 452 | # CONFIG_NETDEV_10000 is not set | 609 | # CONFIG_NETDEV_10000 is not set |
| 453 | # CONFIG_TR is not set | 610 | # CONFIG_TR is not set |
| @@ -458,6 +615,10 @@ CONFIG_TC35815=y | |||
| 458 | # CONFIG_WLAN_PRE80211 is not set | 615 | # CONFIG_WLAN_PRE80211 is not set |
| 459 | # CONFIG_WLAN_80211 is not set | 616 | # CONFIG_WLAN_80211 is not set |
| 460 | # CONFIG_IWLWIFI_LEDS is not set | 617 | # CONFIG_IWLWIFI_LEDS is not set |
| 618 | |||
| 619 | # | ||
| 620 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 621 | # | ||
| 461 | # CONFIG_WAN is not set | 622 | # CONFIG_WAN is not set |
| 462 | # CONFIG_FDDI is not set | 623 | # CONFIG_FDDI is not set |
| 463 | # CONFIG_PPP is not set | 624 | # CONFIG_PPP is not set |
| @@ -502,6 +663,7 @@ CONFIG_SERIAL_TXX9_CONSOLE=y | |||
| 502 | CONFIG_SERIAL_TXX9_STDSERIAL=y | 663 | CONFIG_SERIAL_TXX9_STDSERIAL=y |
| 503 | # CONFIG_SERIAL_JSM is not set | 664 | # CONFIG_SERIAL_JSM is not set |
| 504 | CONFIG_UNIX98_PTYS=y | 665 | CONFIG_UNIX98_PTYS=y |
| 666 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 505 | CONFIG_LEGACY_PTYS=y | 667 | CONFIG_LEGACY_PTYS=y |
| 506 | CONFIG_LEGACY_PTY_COUNT=256 | 668 | CONFIG_LEGACY_PTY_COUNT=256 |
| 507 | # CONFIG_IPMI_HANDLER is not set | 669 | # CONFIG_IPMI_HANDLER is not set |
| @@ -517,17 +679,19 @@ CONFIG_SPI_MASTER=y | |||
| 517 | # | 679 | # |
| 518 | # SPI Master Controller Drivers | 680 | # SPI Master Controller Drivers |
| 519 | # | 681 | # |
| 682 | # CONFIG_SPI_BITBANG is not set | ||
| 683 | # CONFIG_SPI_GPIO is not set | ||
| 520 | CONFIG_SPI_TXX9=y | 684 | CONFIG_SPI_TXX9=y |
| 521 | 685 | ||
| 522 | # | 686 | # |
| 523 | # SPI Protocol Masters | 687 | # SPI Protocol Masters |
| 524 | # | 688 | # |
| 525 | CONFIG_EEPROM_AT25=y | ||
| 526 | # CONFIG_SPI_TLE62X0 is not set | 689 | # CONFIG_SPI_TLE62X0 is not set |
| 527 | CONFIG_HAVE_GPIO_LIB=y | 690 | CONFIG_ARCH_REQUIRE_GPIOLIB=y |
| 691 | CONFIG_GPIOLIB=y | ||
| 528 | 692 | ||
| 529 | # | 693 | # |
| 530 | # GPIO Support | 694 | # Memory mapped GPIO expanders: |
| 531 | # | 695 | # |
| 532 | 696 | ||
| 533 | # | 697 | # |
| @@ -535,8 +699,14 @@ CONFIG_HAVE_GPIO_LIB=y | |||
| 535 | # | 699 | # |
| 536 | 700 | ||
| 537 | # | 701 | # |
| 702 | # PCI GPIO expanders: | ||
| 703 | # | ||
| 704 | # CONFIG_GPIO_BT8XX is not set | ||
| 705 | |||
| 706 | # | ||
| 538 | # SPI GPIO expanders: | 707 | # SPI GPIO expanders: |
| 539 | # | 708 | # |
| 709 | # CONFIG_GPIO_MAX7301 is not set | ||
| 540 | # CONFIG_GPIO_MCP23S08 is not set | 710 | # CONFIG_GPIO_MCP23S08 is not set |
| 541 | # CONFIG_W1 is not set | 711 | # CONFIG_W1 is not set |
| 542 | # CONFIG_POWER_SUPPLY is not set | 712 | # CONFIG_POWER_SUPPLY is not set |
| @@ -550,6 +720,7 @@ CONFIG_WATCHDOG=y | |||
| 550 | # Watchdog Device Drivers | 720 | # Watchdog Device Drivers |
| 551 | # | 721 | # |
| 552 | # CONFIG_SOFT_WATCHDOG is not set | 722 | # CONFIG_SOFT_WATCHDOG is not set |
| 723 | # CONFIG_ALIM7101_WDT is not set | ||
| 553 | CONFIG_TXX9_WDT=m | 724 | CONFIG_TXX9_WDT=m |
| 554 | 725 | ||
| 555 | # | 726 | # |
| @@ -557,18 +728,21 @@ CONFIG_TXX9_WDT=m | |||
| 557 | # | 728 | # |
| 558 | # CONFIG_PCIPCWATCHDOG is not set | 729 | # CONFIG_PCIPCWATCHDOG is not set |
| 559 | # CONFIG_WDTPCI is not set | 730 | # CONFIG_WDTPCI is not set |
| 731 | CONFIG_SSB_POSSIBLE=y | ||
| 560 | 732 | ||
| 561 | # | 733 | # |
| 562 | # Sonics Silicon Backplane | 734 | # Sonics Silicon Backplane |
| 563 | # | 735 | # |
| 564 | CONFIG_SSB_POSSIBLE=y | ||
| 565 | # CONFIG_SSB is not set | 736 | # CONFIG_SSB is not set |
| 566 | 737 | ||
| 567 | # | 738 | # |
| 568 | # Multifunction device drivers | 739 | # Multifunction device drivers |
| 569 | # | 740 | # |
| 741 | # CONFIG_MFD_CORE is not set | ||
| 570 | # CONFIG_MFD_SM501 is not set | 742 | # CONFIG_MFD_SM501 is not set |
| 571 | # CONFIG_HTC_PASIC3 is not set | 743 | # CONFIG_HTC_PASIC3 is not set |
| 744 | # CONFIG_MFD_TMIO is not set | ||
| 745 | # CONFIG_REGULATOR is not set | ||
| 572 | 746 | ||
| 573 | # | 747 | # |
| 574 | # Multimedia devices | 748 | # Multimedia devices |
| @@ -599,15 +773,27 @@ CONFIG_SSB_POSSIBLE=y | |||
| 599 | # Display device support | 773 | # Display device support |
| 600 | # | 774 | # |
| 601 | # CONFIG_DISPLAY_SUPPORT is not set | 775 | # CONFIG_DISPLAY_SUPPORT is not set |
| 602 | |||
| 603 | # | ||
| 604 | # Sound | ||
| 605 | # | ||
| 606 | # CONFIG_SOUND is not set | 776 | # CONFIG_SOUND is not set |
| 607 | # CONFIG_USB_SUPPORT is not set | 777 | # CONFIG_USB_SUPPORT is not set |
| 608 | # CONFIG_MMC is not set | 778 | # CONFIG_MMC is not set |
| 609 | # CONFIG_MEMSTICK is not set | 779 | # CONFIG_MEMSTICK is not set |
| 610 | # CONFIG_NEW_LEDS is not set | 780 | CONFIG_NEW_LEDS=y |
| 781 | CONFIG_LEDS_CLASS=y | ||
| 782 | |||
| 783 | # | ||
| 784 | # LED drivers | ||
| 785 | # | ||
| 786 | CONFIG_LEDS_GPIO=y | ||
| 787 | |||
| 788 | # | ||
| 789 | # LED Triggers | ||
| 790 | # | ||
| 791 | CONFIG_LEDS_TRIGGERS=y | ||
| 792 | # CONFIG_LEDS_TRIGGER_TIMER is not set | ||
| 793 | CONFIG_LEDS_TRIGGER_IDE_DISK=y | ||
| 794 | CONFIG_LEDS_TRIGGER_HEARTBEAT=y | ||
| 795 | # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set | ||
| 796 | # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set | ||
| 611 | # CONFIG_ACCESSIBILITY is not set | 797 | # CONFIG_ACCESSIBILITY is not set |
| 612 | # CONFIG_INFINIBAND is not set | 798 | # CONFIG_INFINIBAND is not set |
| 613 | CONFIG_RTC_LIB=y | 799 | CONFIG_RTC_LIB=y |
| @@ -628,35 +814,47 @@ CONFIG_RTC_INTF_DEV_UIE_EMUL=y | |||
| 628 | # | 814 | # |
| 629 | # SPI RTC drivers | 815 | # SPI RTC drivers |
| 630 | # | 816 | # |
| 817 | # CONFIG_RTC_DRV_M41T94 is not set | ||
| 818 | # CONFIG_RTC_DRV_DS1305 is not set | ||
| 819 | # CONFIG_RTC_DRV_DS1390 is not set | ||
| 631 | # CONFIG_RTC_DRV_MAX6902 is not set | 820 | # CONFIG_RTC_DRV_MAX6902 is not set |
| 632 | # CONFIG_RTC_DRV_R9701 is not set | 821 | # CONFIG_RTC_DRV_R9701 is not set |
| 633 | CONFIG_RTC_DRV_RS5C348=y | 822 | CONFIG_RTC_DRV_RS5C348=y |
| 823 | # CONFIG_RTC_DRV_DS3234 is not set | ||
| 634 | 824 | ||
| 635 | # | 825 | # |
| 636 | # Platform RTC drivers | 826 | # Platform RTC drivers |
| 637 | # | 827 | # |
| 638 | # CONFIG_RTC_DRV_CMOS is not set | 828 | # CONFIG_RTC_DRV_CMOS is not set |
| 829 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 639 | # CONFIG_RTC_DRV_DS1511 is not set | 830 | # CONFIG_RTC_DRV_DS1511 is not set |
| 640 | # CONFIG_RTC_DRV_DS1553 is not set | 831 | # CONFIG_RTC_DRV_DS1553 is not set |
| 641 | CONFIG_RTC_DRV_DS1742=y | 832 | CONFIG_RTC_DRV_DS1742=y |
| 642 | # CONFIG_RTC_DRV_STK17TA8 is not set | 833 | # CONFIG_RTC_DRV_STK17TA8 is not set |
| 643 | # CONFIG_RTC_DRV_M48T86 is not set | 834 | # CONFIG_RTC_DRV_M48T86 is not set |
| 835 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 644 | # CONFIG_RTC_DRV_M48T59 is not set | 836 | # CONFIG_RTC_DRV_M48T59 is not set |
| 837 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 645 | # CONFIG_RTC_DRV_V3020 is not set | 838 | # CONFIG_RTC_DRV_V3020 is not set |
| 646 | 839 | ||
| 647 | # | 840 | # |
| 648 | # on-CPU RTC drivers | 841 | # on-CPU RTC drivers |
| 649 | # | 842 | # |
| 843 | CONFIG_RTC_DRV_TX4939=y | ||
| 844 | # CONFIG_DMADEVICES is not set | ||
| 650 | # CONFIG_UIO is not set | 845 | # CONFIG_UIO is not set |
| 846 | # CONFIG_STAGING is not set | ||
| 651 | 847 | ||
| 652 | # | 848 | # |
| 653 | # File systems | 849 | # File systems |
| 654 | # | 850 | # |
| 655 | # CONFIG_EXT2_FS is not set | 851 | # CONFIG_EXT2_FS is not set |
| 656 | # CONFIG_EXT3_FS is not set | 852 | # CONFIG_EXT3_FS is not set |
| 853 | # CONFIG_EXT4_FS is not set | ||
| 657 | # CONFIG_REISERFS_FS is not set | 854 | # CONFIG_REISERFS_FS is not set |
| 658 | # CONFIG_JFS_FS is not set | 855 | # CONFIG_JFS_FS is not set |
| 659 | CONFIG_FS_POSIX_ACL=y | 856 | CONFIG_FS_POSIX_ACL=y |
| 857 | CONFIG_FILE_LOCKING=y | ||
| 660 | # CONFIG_XFS_FS is not set | 858 | # CONFIG_XFS_FS is not set |
| 661 | # CONFIG_OCFS2_FS is not set | 859 | # CONFIG_OCFS2_FS is not set |
| 662 | # CONFIG_DNOTIFY is not set | 860 | # CONFIG_DNOTIFY is not set |
| @@ -687,30 +885,19 @@ CONFIG_GENERIC_ACL=y | |||
| 687 | CONFIG_PROC_FS=y | 885 | CONFIG_PROC_FS=y |
| 688 | # CONFIG_PROC_KCORE is not set | 886 | # CONFIG_PROC_KCORE is not set |
| 689 | CONFIG_PROC_SYSCTL=y | 887 | CONFIG_PROC_SYSCTL=y |
| 888 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 690 | CONFIG_SYSFS=y | 889 | CONFIG_SYSFS=y |
| 691 | CONFIG_TMPFS=y | 890 | CONFIG_TMPFS=y |
| 692 | CONFIG_TMPFS_POSIX_ACL=y | 891 | CONFIG_TMPFS_POSIX_ACL=y |
| 693 | # CONFIG_HUGETLB_PAGE is not set | 892 | # CONFIG_HUGETLB_PAGE is not set |
| 694 | # CONFIG_CONFIGFS_FS is not set | 893 | # CONFIG_CONFIGFS_FS is not set |
| 695 | 894 | # CONFIG_MISC_FILESYSTEMS is not set | |
| 696 | # | ||
| 697 | # Miscellaneous filesystems | ||
| 698 | # | ||
| 699 | # CONFIG_HFSPLUS_FS is not set | ||
| 700 | # CONFIG_CRAMFS is not set | ||
| 701 | # CONFIG_VXFS_FS is not set | ||
| 702 | # CONFIG_MINIX_FS is not set | ||
| 703 | # CONFIG_HPFS_FS is not set | ||
| 704 | # CONFIG_QNX4FS_FS is not set | ||
| 705 | # CONFIG_ROMFS_FS is not set | ||
| 706 | # CONFIG_SYSV_FS is not set | ||
| 707 | # CONFIG_UFS_FS is not set | ||
| 708 | CONFIG_NETWORK_FILESYSTEMS=y | 895 | CONFIG_NETWORK_FILESYSTEMS=y |
| 709 | CONFIG_NFS_FS=y | 896 | CONFIG_NFS_FS=y |
| 710 | CONFIG_NFS_V3=y | 897 | CONFIG_NFS_V3=y |
| 711 | # CONFIG_NFS_V3_ACL is not set | 898 | # CONFIG_NFS_V3_ACL is not set |
| 712 | # CONFIG_NFSD is not set | ||
| 713 | CONFIG_ROOT_NFS=y | 899 | CONFIG_ROOT_NFS=y |
| 900 | # CONFIG_NFSD is not set | ||
| 714 | CONFIG_LOCKD=y | 901 | CONFIG_LOCKD=y |
| 715 | CONFIG_LOCKD_V4=y | 902 | CONFIG_LOCKD_V4=y |
| 716 | CONFIG_NFS_COMMON=y | 903 | CONFIG_NFS_COMMON=y |
| @@ -740,7 +927,16 @@ CONFIG_FRAME_WARN=1024 | |||
| 740 | CONFIG_DEBUG_FS=y | 927 | CONFIG_DEBUG_FS=y |
| 741 | # CONFIG_HEADERS_CHECK is not set | 928 | # CONFIG_HEADERS_CHECK is not set |
| 742 | # CONFIG_DEBUG_KERNEL is not set | 929 | # CONFIG_DEBUG_KERNEL is not set |
| 930 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 931 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 932 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
| 933 | |||
| 934 | # | ||
| 935 | # Tracers | ||
| 936 | # | ||
| 937 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 743 | # CONFIG_SAMPLES is not set | 938 | # CONFIG_SAMPLES is not set |
| 939 | CONFIG_HAVE_ARCH_KGDB=y | ||
| 744 | CONFIG_CMDLINE="" | 940 | CONFIG_CMDLINE="" |
| 745 | 941 | ||
| 746 | # | 942 | # |
| @@ -748,15 +944,18 @@ CONFIG_CMDLINE="" | |||
| 748 | # | 944 | # |
| 749 | # CONFIG_KEYS is not set | 945 | # CONFIG_KEYS is not set |
| 750 | # CONFIG_SECURITY is not set | 946 | # CONFIG_SECURITY is not set |
| 947 | # CONFIG_SECURITYFS is not set | ||
| 948 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 751 | # CONFIG_CRYPTO is not set | 949 | # CONFIG_CRYPTO is not set |
| 752 | 950 | ||
| 753 | # | 951 | # |
| 754 | # Library routines | 952 | # Library routines |
| 755 | # | 953 | # |
| 756 | CONFIG_BITREVERSE=y | 954 | CONFIG_BITREVERSE=y |
| 757 | # CONFIG_GENERIC_FIND_FIRST_BIT is not set | 955 | CONFIG_GENERIC_FIND_LAST_BIT=y |
| 758 | # CONFIG_CRC_CCITT is not set | 956 | # CONFIG_CRC_CCITT is not set |
| 759 | # CONFIG_CRC16 is not set | 957 | # CONFIG_CRC16 is not set |
| 958 | # CONFIG_CRC_T10DIF is not set | ||
| 760 | # CONFIG_CRC_ITU_T is not set | 959 | # CONFIG_CRC_ITU_T is not set |
| 761 | CONFIG_CRC32=y | 960 | CONFIG_CRC32=y |
| 762 | # CONFIG_CRC7 is not set | 961 | # CONFIG_CRC7 is not set |
diff --git a/arch/mips/emma/Kconfig b/arch/mips/emma/Kconfig deleted file mode 100644 index 9669c72123c9..000000000000 --- a/arch/mips/emma/Kconfig +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | choice | ||
| 2 | prompt "Machine type" | ||
| 3 | depends on MACH_EMMA | ||
| 4 | default NEC_MARKEINS | ||
| 5 | |||
| 6 | config NEC_MARKEINS | ||
| 7 | bool "NEC EMMA2RH Mark-eins board" | ||
| 8 | select SOC_EMMA2RH | ||
| 9 | select HW_HAS_PCI | ||
| 10 | help | ||
| 11 | This enables support for the NEC Electronics Mark-eins boards. | ||
| 12 | |||
| 13 | endchoice | ||
| 14 | |||
| 15 | config SOC_EMMA2RH | ||
| 16 | bool | ||
| 17 | select SOC_EMMA | ||
| 18 | select SYS_HAS_CPU_R5500 | ||
| 19 | select SYS_SUPPORTS_32BIT_KERNEL | ||
| 20 | select SYS_SUPPORTS_64BIT_KERNEL | ||
| 21 | |||
| 22 | config SOC_EMMA | ||
| 23 | bool | ||
| 24 | select CEVT_R4K | ||
| 25 | select CSRC_R4K | ||
| 26 | select DMA_NONCOHERENT | ||
| 27 | select IRQ_CPU | ||
| 28 | select SWAP_IO_SPACE | ||
| 29 | select SYS_SUPPORTS_BIG_ENDIAN | ||
diff --git a/arch/mips/emma/markeins/platform.c b/arch/mips/emma/markeins/platform.c index 88e87f6b3442..d5f47e4f0d18 100644 --- a/arch/mips/emma/markeins/platform.c +++ b/arch/mips/emma/markeins/platform.c | |||
| @@ -141,13 +141,6 @@ static struct platform_device serial_emma = { | |||
| 141 | }, | 141 | }, |
| 142 | }; | 142 | }; |
| 143 | 143 | ||
| 144 | static struct platform_device *devices[] = { | ||
| 145 | &i2c_emma_devices[0], | ||
| 146 | &i2c_emma_devices[1], | ||
| 147 | &i2c_emma_devices[2], | ||
| 148 | &serial_emma, | ||
| 149 | }; | ||
| 150 | |||
| 151 | static struct mtd_partition markeins_parts[] = { | 144 | static struct mtd_partition markeins_parts[] = { |
| 152 | [0] = { | 145 | [0] = { |
| 153 | .name = "RootFS", | 146 | .name = "RootFS", |
| @@ -181,11 +174,39 @@ static struct mtd_partition markeins_parts[] = { | |||
| 181 | }, | 174 | }, |
| 182 | }; | 175 | }; |
| 183 | 176 | ||
| 177 | static struct physmap_flash_data markeins_flash_data = { | ||
| 178 | .width = 2, | ||
| 179 | .nr_parts = ARRAY_SIZE(markeins_parts), | ||
| 180 | .parts = markeins_parts | ||
| 181 | }; | ||
| 182 | |||
| 183 | static struct resource markeins_flash_resource = { | ||
| 184 | .start = 0x1e000000, | ||
| 185 | .end = 0x02000000, | ||
| 186 | .flags = IORESOURCE_MEM | ||
| 187 | }; | ||
| 188 | |||
| 189 | static struct platform_device markeins_flash_device = { | ||
| 190 | .name = "physmap-flash", | ||
| 191 | .id = 0, | ||
| 192 | .dev = { | ||
| 193 | .platform_data = &markeins_flash_data, | ||
| 194 | }, | ||
| 195 | .num_resources = 1, | ||
| 196 | .resource = &markeins_flash_resource, | ||
| 197 | }; | ||
| 198 | |||
| 199 | static struct platform_device *devices[] = { | ||
| 200 | i2c_emma_devices, | ||
| 201 | i2c_emma_devices + 1, | ||
| 202 | i2c_emma_devices + 2, | ||
| 203 | &serial_emma, | ||
| 204 | &markeins_flash_device, | ||
| 205 | }; | ||
| 206 | |||
| 184 | static int __init platform_devices_setup(void) | 207 | static int __init platform_devices_setup(void) |
| 185 | { | 208 | { |
| 186 | physmap_set_partitions(markeins_parts, ARRAY_SIZE(markeins_parts)); | ||
| 187 | return platform_add_devices(devices, ARRAY_SIZE(devices)); | 209 | return platform_add_devices(devices, ARRAY_SIZE(devices)); |
| 188 | } | 210 | } |
| 189 | 211 | ||
| 190 | arch_initcall(platform_devices_setup); | 212 | arch_initcall(platform_devices_setup); |
| 191 | |||
diff --git a/arch/mips/include/asm/compat.h b/arch/mips/include/asm/compat.h index ac5d541368e9..6c5b40905dd6 100644 --- a/arch/mips/include/asm/compat.h +++ b/arch/mips/include/asm/compat.h | |||
| @@ -3,6 +3,8 @@ | |||
| 3 | /* | 3 | /* |
| 4 | * Architecture specific compatibility types | 4 | * Architecture specific compatibility types |
| 5 | */ | 5 | */ |
| 6 | #include <linux/seccomp.h> | ||
| 7 | #include <linux/thread_info.h> | ||
| 6 | #include <linux/types.h> | 8 | #include <linux/types.h> |
| 7 | #include <asm/page.h> | 9 | #include <asm/page.h> |
| 8 | #include <asm/ptrace.h> | 10 | #include <asm/ptrace.h> |
| @@ -218,4 +220,9 @@ struct compat_shmid64_ds { | |||
| 218 | compat_ulong_t __unused2; | 220 | compat_ulong_t __unused2; |
| 219 | }; | 221 | }; |
| 220 | 222 | ||
| 223 | static inline int is_compat_task(void) | ||
| 224 | { | ||
| 225 | return test_thread_flag(TIF_32BIT); | ||
| 226 | } | ||
| 227 | |||
| 221 | #endif /* _ASM_COMPAT_H */ | 228 | #endif /* _ASM_COMPAT_H */ |
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index 43baed16a109..134e1fc8f4d6 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h | |||
| @@ -138,7 +138,8 @@ do { \ | |||
| 138 | __instruction_hazard(); \ | 138 | __instruction_hazard(); \ |
| 139 | } while (0) | 139 | } while (0) |
| 140 | 140 | ||
| 141 | #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) | 141 | #elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ |
| 142 | defined(CONFIG_CPU_R5500) | ||
| 142 | 143 | ||
| 143 | /* | 144 | /* |
| 144 | * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. | 145 | * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. |
diff --git a/arch/mips/include/asm/prefetch.h b/arch/mips/include/asm/prefetch.h index 17850834ccb0..a56594f360ee 100644 --- a/arch/mips/include/asm/prefetch.h +++ b/arch/mips/include/asm/prefetch.h | |||
| @@ -26,7 +26,7 @@ | |||
| 26 | * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in | 26 | * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in |
| 27 | * current versions due to erratum G105. | 27 | * current versions due to erratum G105. |
| 28 | * | 28 | * |
| 29 | * VR7701 only implements the Load prefetch. | 29 | * VR5500 (including VR5701 and VR7701) only implement load prefetch. |
| 30 | * | 30 | * |
| 31 | * Finally MIPS32 and MIPS64 implement all of the following hints. | 31 | * Finally MIPS32 and MIPS64 implement all of the following hints. |
| 32 | */ | 32 | */ |
diff --git a/arch/mips/include/asm/seccomp.h b/arch/mips/include/asm/seccomp.h index a6772e9507f5..ae6306ebdcad 100644 --- a/arch/mips/include/asm/seccomp.h +++ b/arch/mips/include/asm/seccomp.h | |||
| @@ -15,8 +15,6 @@ | |||
| 15 | */ | 15 | */ |
| 16 | #ifdef CONFIG_MIPS32_O32 | 16 | #ifdef CONFIG_MIPS32_O32 |
| 17 | 17 | ||
| 18 | #define TIF_32BIT TIF_32BIT_REGS | ||
| 19 | |||
| 20 | #define __NR_seccomp_read_32 4003 | 18 | #define __NR_seccomp_read_32 4003 |
| 21 | #define __NR_seccomp_write_32 4004 | 19 | #define __NR_seccomp_write_32 4004 |
| 22 | #define __NR_seccomp_exit_32 4001 | 20 | #define __NR_seccomp_exit_32 4001 |
| @@ -24,8 +22,6 @@ | |||
| 24 | 22 | ||
| 25 | #elif defined(CONFIG_MIPS32_N32) | 23 | #elif defined(CONFIG_MIPS32_N32) |
| 26 | 24 | ||
| 27 | #define TIF_32BIT _TIF_32BIT_ADDR | ||
| 28 | |||
| 29 | #define __NR_seccomp_read_32 6000 | 25 | #define __NR_seccomp_read_32 6000 |
| 30 | #define __NR_seccomp_write_32 6001 | 26 | #define __NR_seccomp_write_32 6001 |
| 31 | #define __NR_seccomp_exit_32 6058 | 27 | #define __NR_seccomp_exit_32 6058 |
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index 3f76de73c943..676aa2ae1913 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h | |||
| @@ -127,6 +127,12 @@ register struct thread_info *__current_thread_info __asm__("$28"); | |||
| 127 | #define TIF_LOAD_WATCH 25 /* If set, load watch registers */ | 127 | #define TIF_LOAD_WATCH 25 /* If set, load watch registers */ |
| 128 | #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ | 128 | #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ |
| 129 | 129 | ||
| 130 | #ifdef CONFIG_MIPS32_O32 | ||
| 131 | #define TIF_32BIT TIF_32BIT_REGS | ||
| 132 | #elif defined(CONFIG_MIPS32_N32) | ||
| 133 | #define TIF_32BIT _TIF_32BIT_ADDR | ||
| 134 | #endif /* CONFIG_MIPS32_O32 */ | ||
| 135 | |||
| 130 | #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) | 136 | #define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) |
| 131 | #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) | 137 | #define _TIF_SIGPENDING (1<<TIF_SIGPENDING) |
| 132 | #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) | 138 | #define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) |
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index a7162a4484cf..1bdbcad3bb74 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c | |||
| @@ -149,6 +149,7 @@ void __init check_wait(void) | |||
| 149 | case CPU_R4650: | 149 | case CPU_R4650: |
| 150 | case CPU_R4700: | 150 | case CPU_R4700: |
| 151 | case CPU_R5000: | 151 | case CPU_R5000: |
| 152 | case CPU_R5500: | ||
| 152 | case CPU_NEVADA: | 153 | case CPU_NEVADA: |
| 153 | case CPU_4KC: | 154 | case CPU_4KC: |
| 154 | case CPU_4KEC: | 155 | case CPU_4KEC: |
diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index 2f8452b404c7..1a86f84fa947 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c | |||
| @@ -235,7 +235,7 @@ SYSCALL_DEFINE6(32_ipc, u32, call, long, first, long, second, long, third, | |||
| 235 | #else | 235 | #else |
| 236 | 236 | ||
| 237 | SYSCALL_DEFINE6(32_ipc, u32, call, int, first, int, second, int, third, | 237 | SYSCALL_DEFINE6(32_ipc, u32, call, int, first, int, second, int, third, |
| 238 | u32, ptr, u32 fifth) | 238 | u32, ptr, u32, fifth) |
| 239 | { | 239 | { |
| 240 | return -ENOSYS; | 240 | return -ENOSYS; |
| 241 | } | 241 | } |
diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 1417c6494858..48060c635acd 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c | |||
| @@ -172,8 +172,9 @@ static void __cpuinit set_prefetch_parameters(void) | |||
| 172 | */ | 172 | */ |
| 173 | cache_line_size = cpu_dcache_line_size(); | 173 | cache_line_size = cpu_dcache_line_size(); |
| 174 | switch (current_cpu_type()) { | 174 | switch (current_cpu_type()) { |
| 175 | case CPU_R5500: | ||
| 175 | case CPU_TX49XX: | 176 | case CPU_TX49XX: |
| 176 | /* TX49 supports only Pref_Load */ | 177 | /* These processors only support the Pref_Load. */ |
| 177 | pref_bias_copy_load = 256; | 178 | pref_bias_copy_load = 256; |
| 178 | break; | 179 | break; |
| 179 | 180 | ||
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 42942038d0fd..f335cf6cdd78 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c | |||
| @@ -318,6 +318,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, | |||
| 318 | case CPU_BCM4710: | 318 | case CPU_BCM4710: |
| 319 | case CPU_LOONGSON2: | 319 | case CPU_LOONGSON2: |
| 320 | case CPU_CAVIUM_OCTEON: | 320 | case CPU_CAVIUM_OCTEON: |
| 321 | case CPU_R5500: | ||
| 321 | if (m4kc_tlbp_war()) | 322 | if (m4kc_tlbp_war()) |
| 322 | uasm_i_nop(p); | 323 | uasm_i_nop(p); |
| 323 | tlbw(p); | 324 | tlbw(p); |
diff --git a/arch/parisc/configs/712_defconfig b/arch/parisc/configs/712_defconfig index 9fc96e727165..bf34a28895fa 100644 --- a/arch/parisc/configs/712_defconfig +++ b/arch/parisc/configs/712_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.23 | 3 | # Linux kernel version: 2.6.29-rc8 |
| 4 | # Fri Oct 12 21:00:07 2007 | 4 | # Fri Mar 13 01:32:55 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_PARISC=y | 6 | CONFIG_PARISC=y |
| 7 | CONFIG_MMU=y | 7 | CONFIG_MMU=y |
| @@ -33,17 +33,35 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 33 | CONFIG_POSIX_MQUEUE=y | 33 | CONFIG_POSIX_MQUEUE=y |
| 34 | # CONFIG_BSD_PROCESS_ACCT is not set | 34 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 35 | # CONFIG_TASKSTATS is not set | 35 | # CONFIG_TASKSTATS is not set |
| 36 | # CONFIG_USER_NS is not set | ||
| 37 | # CONFIG_AUDIT is not set | 36 | # CONFIG_AUDIT is not set |
| 37 | |||
| 38 | # | ||
| 39 | # RCU Subsystem | ||
| 40 | # | ||
| 41 | CONFIG_CLASSIC_RCU=y | ||
| 42 | # CONFIG_TREE_RCU is not set | ||
| 43 | # CONFIG_PREEMPT_RCU is not set | ||
| 44 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 45 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 38 | CONFIG_IKCONFIG=y | 46 | CONFIG_IKCONFIG=y |
| 39 | CONFIG_IKCONFIG_PROC=y | 47 | CONFIG_IKCONFIG_PROC=y |
| 40 | CONFIG_LOG_BUF_SHIFT=16 | 48 | CONFIG_LOG_BUF_SHIFT=16 |
| 49 | # CONFIG_GROUP_SCHED is not set | ||
| 50 | # CONFIG_CGROUPS is not set | ||
| 41 | CONFIG_SYSFS_DEPRECATED=y | 51 | CONFIG_SYSFS_DEPRECATED=y |
| 52 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 42 | # CONFIG_RELAY is not set | 53 | # CONFIG_RELAY is not set |
| 54 | CONFIG_NAMESPACES=y | ||
| 55 | # CONFIG_UTS_NS is not set | ||
| 56 | # CONFIG_IPC_NS is not set | ||
| 57 | # CONFIG_USER_NS is not set | ||
| 58 | # CONFIG_PID_NS is not set | ||
| 59 | # CONFIG_NET_NS is not set | ||
| 43 | CONFIG_BLK_DEV_INITRD=y | 60 | CONFIG_BLK_DEV_INITRD=y |
| 44 | CONFIG_INITRAMFS_SOURCE="" | 61 | CONFIG_INITRAMFS_SOURCE="" |
| 45 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 62 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 46 | CONFIG_SYSCTL=y | 63 | CONFIG_SYSCTL=y |
| 64 | CONFIG_ANON_INODES=y | ||
| 47 | # CONFIG_EMBEDDED is not set | 65 | # CONFIG_EMBEDDED is not set |
| 48 | CONFIG_SYSCTL_SYSCALL=y | 66 | CONFIG_SYSCTL_SYSCALL=y |
| 49 | CONFIG_KALLSYMS=y | 67 | CONFIG_KALLSYMS=y |
| @@ -55,29 +73,38 @@ CONFIG_BUG=y | |||
| 55 | CONFIG_ELF_CORE=y | 73 | CONFIG_ELF_CORE=y |
| 56 | CONFIG_BASE_FULL=y | 74 | CONFIG_BASE_FULL=y |
| 57 | CONFIG_FUTEX=y | 75 | CONFIG_FUTEX=y |
| 58 | CONFIG_ANON_INODES=y | ||
| 59 | CONFIG_EPOLL=y | 76 | CONFIG_EPOLL=y |
| 60 | CONFIG_SIGNALFD=y | 77 | CONFIG_SIGNALFD=y |
| 78 | CONFIG_TIMERFD=y | ||
| 61 | CONFIG_EVENTFD=y | 79 | CONFIG_EVENTFD=y |
| 62 | CONFIG_SHMEM=y | 80 | CONFIG_SHMEM=y |
| 81 | CONFIG_AIO=y | ||
| 63 | CONFIG_VM_EVENT_COUNTERS=y | 82 | CONFIG_VM_EVENT_COUNTERS=y |
| 83 | CONFIG_COMPAT_BRK=y | ||
| 64 | CONFIG_SLAB=y | 84 | CONFIG_SLAB=y |
| 65 | # CONFIG_SLUB is not set | 85 | # CONFIG_SLUB is not set |
| 66 | # CONFIG_SLOB is not set | 86 | # CONFIG_SLOB is not set |
| 87 | CONFIG_PROFILING=y | ||
| 88 | CONFIG_TRACEPOINTS=y | ||
| 89 | # CONFIG_MARKERS is not set | ||
| 90 | CONFIG_OPROFILE=m | ||
| 91 | CONFIG_HAVE_OPROFILE=y | ||
| 92 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 93 | CONFIG_SLABINFO=y | ||
| 67 | CONFIG_RT_MUTEXES=y | 94 | CONFIG_RT_MUTEXES=y |
| 68 | # CONFIG_TINY_SHMEM is not set | ||
| 69 | CONFIG_BASE_SMALL=0 | 95 | CONFIG_BASE_SMALL=0 |
| 70 | CONFIG_MODULES=y | 96 | CONFIG_MODULES=y |
| 97 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 71 | CONFIG_MODULE_UNLOAD=y | 98 | CONFIG_MODULE_UNLOAD=y |
| 72 | CONFIG_MODULE_FORCE_UNLOAD=y | 99 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 73 | # CONFIG_MODVERSIONS is not set | 100 | # CONFIG_MODVERSIONS is not set |
| 74 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 101 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 75 | CONFIG_KMOD=y | 102 | CONFIG_INIT_ALL_POSSIBLE=y |
| 76 | CONFIG_BLOCK=y | 103 | CONFIG_BLOCK=y |
| 77 | # CONFIG_LBD is not set | 104 | # CONFIG_LBD is not set |
| 78 | # CONFIG_BLK_DEV_IO_TRACE is not set | 105 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 79 | # CONFIG_LSF is not set | ||
| 80 | # CONFIG_BLK_DEV_BSG is not set | 106 | # CONFIG_BLK_DEV_BSG is not set |
| 107 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 81 | 108 | ||
| 82 | # | 109 | # |
| 83 | # IO Schedulers | 110 | # IO Schedulers |
| @@ -91,6 +118,7 @@ CONFIG_DEFAULT_AS=y | |||
| 91 | # CONFIG_DEFAULT_CFQ is not set | 118 | # CONFIG_DEFAULT_CFQ is not set |
| 92 | # CONFIG_DEFAULT_NOOP is not set | 119 | # CONFIG_DEFAULT_NOOP is not set |
| 93 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 120 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 121 | # CONFIG_FREEZER is not set | ||
| 94 | 122 | ||
| 95 | # | 123 | # |
| 96 | # Processor type and features | 124 | # Processor type and features |
| @@ -114,17 +142,19 @@ CONFIG_HZ_250=y | |||
| 114 | # CONFIG_HZ_300 is not set | 142 | # CONFIG_HZ_300 is not set |
| 115 | # CONFIG_HZ_1000 is not set | 143 | # CONFIG_HZ_1000 is not set |
| 116 | CONFIG_HZ=250 | 144 | CONFIG_HZ=250 |
| 145 | # CONFIG_SCHED_HRTICK is not set | ||
| 117 | CONFIG_SELECT_MEMORY_MODEL=y | 146 | CONFIG_SELECT_MEMORY_MODEL=y |
| 118 | CONFIG_FLATMEM_MANUAL=y | 147 | CONFIG_FLATMEM_MANUAL=y |
| 119 | # CONFIG_DISCONTIGMEM_MANUAL is not set | 148 | # CONFIG_DISCONTIGMEM_MANUAL is not set |
| 120 | # CONFIG_SPARSEMEM_MANUAL is not set | 149 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 121 | CONFIG_FLATMEM=y | 150 | CONFIG_FLATMEM=y |
| 122 | CONFIG_FLAT_NODE_MEM_MAP=y | 151 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 123 | # CONFIG_SPARSEMEM_STATIC is not set | 152 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 124 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 153 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 125 | # CONFIG_RESOURCES_64BIT is not set | 154 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 126 | CONFIG_ZONE_DMA_FLAG=0 | 155 | CONFIG_ZONE_DMA_FLAG=0 |
| 127 | CONFIG_VIRT_TO_BUS=y | 156 | CONFIG_VIRT_TO_BUS=y |
| 157 | CONFIG_UNEVICTABLE_LRU=y | ||
| 128 | # CONFIG_HPUX is not set | 158 | # CONFIG_HPUX is not set |
| 129 | 159 | ||
| 130 | # | 160 | # |
| @@ -138,10 +168,6 @@ CONFIG_GSC_LASI=y | |||
| 138 | # CONFIG_EISA is not set | 168 | # CONFIG_EISA is not set |
| 139 | # CONFIG_PCI is not set | 169 | # CONFIG_PCI is not set |
| 140 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 170 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 141 | |||
| 142 | # | ||
| 143 | # PCCARD (PCMCIA/CardBus) support | ||
| 144 | # | ||
| 145 | # CONFIG_PCCARD is not set | 171 | # CONFIG_PCCARD is not set |
| 146 | 172 | ||
| 147 | # | 173 | # |
| @@ -156,16 +182,15 @@ CONFIG_PDC_STABLE=y | |||
| 156 | # Executable file formats | 182 | # Executable file formats |
| 157 | # | 183 | # |
| 158 | CONFIG_BINFMT_ELF=y | 184 | CONFIG_BINFMT_ELF=y |
| 185 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 186 | # CONFIG_HAVE_AOUT is not set | ||
| 159 | CONFIG_BINFMT_MISC=m | 187 | CONFIG_BINFMT_MISC=m |
| 160 | |||
| 161 | # | ||
| 162 | # Networking | ||
| 163 | # | ||
| 164 | CONFIG_NET=y | 188 | CONFIG_NET=y |
| 165 | 189 | ||
| 166 | # | 190 | # |
| 167 | # Networking options | 191 | # Networking options |
| 168 | # | 192 | # |
| 193 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 169 | CONFIG_PACKET=y | 194 | CONFIG_PACKET=y |
| 170 | CONFIG_PACKET_MMAP=y | 195 | CONFIG_PACKET_MMAP=y |
| 171 | CONFIG_UNIX=y | 196 | CONFIG_UNIX=y |
| @@ -173,6 +198,7 @@ CONFIG_XFRM=y | |||
| 173 | CONFIG_XFRM_USER=m | 198 | CONFIG_XFRM_USER=m |
| 174 | # CONFIG_XFRM_SUB_POLICY is not set | 199 | # CONFIG_XFRM_SUB_POLICY is not set |
| 175 | # CONFIG_XFRM_MIGRATE is not set | 200 | # CONFIG_XFRM_MIGRATE is not set |
| 201 | # CONFIG_XFRM_STATISTICS is not set | ||
| 176 | CONFIG_NET_KEY=m | 202 | CONFIG_NET_KEY=m |
| 177 | # CONFIG_NET_KEY_MIGRATE is not set | 203 | # CONFIG_NET_KEY_MIGRATE is not set |
| 178 | CONFIG_INET=y | 204 | CONFIG_INET=y |
| @@ -203,25 +229,25 @@ CONFIG_INET_TCP_DIAG=m | |||
| 203 | CONFIG_TCP_CONG_CUBIC=y | 229 | CONFIG_TCP_CONG_CUBIC=y |
| 204 | CONFIG_DEFAULT_TCP_CONG="cubic" | 230 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 205 | # CONFIG_TCP_MD5SIG is not set | 231 | # CONFIG_TCP_MD5SIG is not set |
| 206 | # CONFIG_IP_VS is not set | ||
| 207 | # CONFIG_IPV6 is not set | 232 | # CONFIG_IPV6 is not set |
| 208 | # CONFIG_INET6_XFRM_TUNNEL is not set | ||
| 209 | # CONFIG_INET6_TUNNEL is not set | ||
| 210 | # CONFIG_NETWORK_SECMARK is not set | 233 | # CONFIG_NETWORK_SECMARK is not set |
| 211 | CONFIG_NETFILTER=y | 234 | CONFIG_NETFILTER=y |
| 212 | # CONFIG_NETFILTER_DEBUG is not set | 235 | # CONFIG_NETFILTER_DEBUG is not set |
| 236 | CONFIG_NETFILTER_ADVANCED=y | ||
| 213 | 237 | ||
| 214 | # | 238 | # |
| 215 | # Core Netfilter Configuration | 239 | # Core Netfilter Configuration |
| 216 | # | 240 | # |
| 217 | # CONFIG_NETFILTER_NETLINK is not set | 241 | # CONFIG_NETFILTER_NETLINK_QUEUE is not set |
| 218 | # CONFIG_NF_CONNTRACK_ENABLED is not set | 242 | # CONFIG_NETFILTER_NETLINK_LOG is not set |
| 219 | # CONFIG_NF_CONNTRACK is not set | 243 | # CONFIG_NF_CONNTRACK is not set |
| 220 | # CONFIG_NETFILTER_XTABLES is not set | 244 | # CONFIG_NETFILTER_XTABLES is not set |
| 245 | # CONFIG_IP_VS is not set | ||
| 221 | 246 | ||
| 222 | # | 247 | # |
| 223 | # IP: Netfilter Configuration | 248 | # IP: Netfilter Configuration |
| 224 | # | 249 | # |
| 250 | # CONFIG_NF_DEFRAG_IPV4 is not set | ||
| 225 | CONFIG_IP_NF_QUEUE=m | 251 | CONFIG_IP_NF_QUEUE=m |
| 226 | # CONFIG_IP_NF_IPTABLES is not set | 252 | # CONFIG_IP_NF_IPTABLES is not set |
| 227 | # CONFIG_IP_NF_ARPTABLES is not set | 253 | # CONFIG_IP_NF_ARPTABLES is not set |
| @@ -230,6 +256,7 @@ CONFIG_IP_NF_QUEUE=m | |||
| 230 | # CONFIG_TIPC is not set | 256 | # CONFIG_TIPC is not set |
| 231 | # CONFIG_ATM is not set | 257 | # CONFIG_ATM is not set |
| 232 | # CONFIG_BRIDGE is not set | 258 | # CONFIG_BRIDGE is not set |
| 259 | # CONFIG_NET_DSA is not set | ||
| 233 | # CONFIG_VLAN_8021Q is not set | 260 | # CONFIG_VLAN_8021Q is not set |
| 234 | # CONFIG_DECNET is not set | 261 | # CONFIG_DECNET is not set |
| 235 | CONFIG_LLC=m | 262 | CONFIG_LLC=m |
| @@ -240,28 +267,26 @@ CONFIG_LLC2=m | |||
| 240 | # CONFIG_LAPB is not set | 267 | # CONFIG_LAPB is not set |
| 241 | # CONFIG_ECONET is not set | 268 | # CONFIG_ECONET is not set |
| 242 | # CONFIG_WAN_ROUTER is not set | 269 | # CONFIG_WAN_ROUTER is not set |
| 243 | |||
| 244 | # | ||
| 245 | # QoS and/or fair queueing | ||
| 246 | # | ||
| 247 | # CONFIG_NET_SCHED is not set | 270 | # CONFIG_NET_SCHED is not set |
| 271 | # CONFIG_DCB is not set | ||
| 248 | 272 | ||
| 249 | # | 273 | # |
| 250 | # Network testing | 274 | # Network testing |
| 251 | # | 275 | # |
| 252 | CONFIG_NET_PKTGEN=m | 276 | CONFIG_NET_PKTGEN=m |
| 253 | # CONFIG_HAMRADIO is not set | 277 | # CONFIG_HAMRADIO is not set |
| 278 | # CONFIG_CAN is not set | ||
| 254 | # CONFIG_IRDA is not set | 279 | # CONFIG_IRDA is not set |
| 255 | # CONFIG_BT is not set | 280 | # CONFIG_BT is not set |
| 256 | # CONFIG_AF_RXRPC is not set | 281 | # CONFIG_AF_RXRPC is not set |
| 257 | 282 | # CONFIG_PHONET is not set | |
| 258 | # | 283 | CONFIG_WIRELESS=y |
| 259 | # Wireless | ||
| 260 | # | ||
| 261 | # CONFIG_CFG80211 is not set | 284 | # CONFIG_CFG80211 is not set |
| 285 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 262 | # CONFIG_WIRELESS_EXT is not set | 286 | # CONFIG_WIRELESS_EXT is not set |
| 287 | # CONFIG_LIB80211 is not set | ||
| 263 | # CONFIG_MAC80211 is not set | 288 | # CONFIG_MAC80211 is not set |
| 264 | # CONFIG_IEEE80211 is not set | 289 | # CONFIG_WIMAX is not set |
| 265 | # CONFIG_RFKILL is not set | 290 | # CONFIG_RFKILL is not set |
| 266 | # CONFIG_NET_9P is not set | 291 | # CONFIG_NET_9P is not set |
| 267 | 292 | ||
| @@ -276,6 +301,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |||
| 276 | # CONFIG_STANDALONE is not set | 301 | # CONFIG_STANDALONE is not set |
| 277 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | 302 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set |
| 278 | CONFIG_FW_LOADER=y | 303 | CONFIG_FW_LOADER=y |
| 304 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 305 | CONFIG_EXTRA_FIRMWARE="" | ||
| 279 | # CONFIG_DEBUG_DRIVER is not set | 306 | # CONFIG_DEBUG_DRIVER is not set |
| 280 | # CONFIG_DEBUG_DEVRES is not set | 307 | # CONFIG_DEBUG_DEVRES is not set |
| 281 | # CONFIG_SYS_HYPERVISOR is not set | 308 | # CONFIG_SYS_HYPERVISOR is not set |
| @@ -298,11 +325,19 @@ CONFIG_BLK_DEV_CRYPTOLOOP=y | |||
| 298 | CONFIG_BLK_DEV_RAM=y | 325 | CONFIG_BLK_DEV_RAM=y |
| 299 | CONFIG_BLK_DEV_RAM_COUNT=16 | 326 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 300 | CONFIG_BLK_DEV_RAM_SIZE=6144 | 327 | CONFIG_BLK_DEV_RAM_SIZE=6144 |
| 301 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 328 | # CONFIG_BLK_DEV_XIP is not set |
| 302 | # CONFIG_CDROM_PKTCDVD is not set | 329 | # CONFIG_CDROM_PKTCDVD is not set |
| 303 | CONFIG_ATA_OVER_ETH=m | 330 | CONFIG_ATA_OVER_ETH=m |
| 331 | # CONFIG_BLK_DEV_HD is not set | ||
| 304 | CONFIG_MISC_DEVICES=y | 332 | CONFIG_MISC_DEVICES=y |
| 333 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 334 | # CONFIG_C2PORT is not set | ||
| 335 | |||
| 336 | # | ||
| 337 | # EEPROM support | ||
| 338 | # | ||
| 305 | # CONFIG_EEPROM_93CX6 is not set | 339 | # CONFIG_EEPROM_93CX6 is not set |
| 340 | CONFIG_HAVE_IDE=y | ||
| 306 | # CONFIG_IDE is not set | 341 | # CONFIG_IDE is not set |
| 307 | 342 | ||
| 308 | # | 343 | # |
| @@ -342,14 +377,17 @@ CONFIG_SCSI_SPI_ATTRS=y | |||
| 342 | # CONFIG_SCSI_FC_ATTRS is not set | 377 | # CONFIG_SCSI_FC_ATTRS is not set |
| 343 | CONFIG_SCSI_ISCSI_ATTRS=m | 378 | CONFIG_SCSI_ISCSI_ATTRS=m |
| 344 | # CONFIG_SCSI_SAS_LIBSAS is not set | 379 | # CONFIG_SCSI_SAS_LIBSAS is not set |
| 380 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 345 | CONFIG_SCSI_LOWLEVEL=y | 381 | CONFIG_SCSI_LOWLEVEL=y |
| 346 | # CONFIG_ISCSI_TCP is not set | 382 | # CONFIG_ISCSI_TCP is not set |
| 383 | # CONFIG_LIBFC is not set | ||
| 347 | # CONFIG_SCSI_PPA is not set | 384 | # CONFIG_SCSI_PPA is not set |
| 348 | # CONFIG_SCSI_IMM is not set | 385 | # CONFIG_SCSI_IMM is not set |
| 349 | CONFIG_SCSI_LASI700=y | 386 | CONFIG_SCSI_LASI700=y |
| 350 | CONFIG_53C700_LE_ON_BE=y | 387 | CONFIG_53C700_LE_ON_BE=y |
| 351 | # CONFIG_SCSI_ZALON is not set | 388 | # CONFIG_SCSI_ZALON is not set |
| 352 | CONFIG_SCSI_DEBUG=m | 389 | CONFIG_SCSI_DEBUG=m |
| 390 | # CONFIG_SCSI_DH is not set | ||
| 353 | # CONFIG_ATA is not set | 391 | # CONFIG_ATA is not set |
| 354 | CONFIG_MD=y | 392 | CONFIG_MD=y |
| 355 | CONFIG_BLK_DEV_MD=m | 393 | CONFIG_BLK_DEV_MD=m |
| @@ -362,7 +400,6 @@ CONFIG_MD_RAID1=m | |||
| 362 | # CONFIG_MD_FAULTY is not set | 400 | # CONFIG_MD_FAULTY is not set |
| 363 | # CONFIG_BLK_DEV_DM is not set | 401 | # CONFIG_BLK_DEV_DM is not set |
| 364 | CONFIG_NETDEVICES=y | 402 | CONFIG_NETDEVICES=y |
| 365 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 366 | CONFIG_DUMMY=m | 403 | CONFIG_DUMMY=m |
| 367 | CONFIG_BONDING=m | 404 | CONFIG_BONDING=m |
| 368 | # CONFIG_MACVLAN is not set | 405 | # CONFIG_MACVLAN is not set |
| @@ -377,6 +414,9 @@ CONFIG_LASI_82596=y | |||
| 377 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 414 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 378 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 415 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 379 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 416 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 417 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 418 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 419 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 380 | # CONFIG_B44 is not set | 420 | # CONFIG_B44 is not set |
| 381 | # CONFIG_NET_POCKET is not set | 421 | # CONFIG_NET_POCKET is not set |
| 382 | CONFIG_NETDEV_1000=y | 422 | CONFIG_NETDEV_1000=y |
| @@ -387,6 +427,11 @@ CONFIG_NETDEV_10000=y | |||
| 387 | # | 427 | # |
| 388 | # CONFIG_WLAN_PRE80211 is not set | 428 | # CONFIG_WLAN_PRE80211 is not set |
| 389 | # CONFIG_WLAN_80211 is not set | 429 | # CONFIG_WLAN_80211 is not set |
| 430 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 431 | |||
| 432 | # | ||
| 433 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 434 | # | ||
| 390 | # CONFIG_WAN is not set | 435 | # CONFIG_WAN is not set |
| 391 | # CONFIG_PLIP is not set | 436 | # CONFIG_PLIP is not set |
| 392 | CONFIG_PPP=m | 437 | CONFIG_PPP=m |
| @@ -401,7 +446,6 @@ CONFIG_PPPOE=m | |||
| 401 | # CONFIG_PPPOL2TP is not set | 446 | # CONFIG_PPPOL2TP is not set |
| 402 | # CONFIG_SLIP is not set | 447 | # CONFIG_SLIP is not set |
| 403 | CONFIG_SLHC=m | 448 | CONFIG_SLHC=m |
| 404 | # CONFIG_SHAPER is not set | ||
| 405 | # CONFIG_NETCONSOLE is not set | 449 | # CONFIG_NETCONSOLE is not set |
| 406 | # CONFIG_NETPOLL is not set | 450 | # CONFIG_NETPOLL is not set |
| 407 | # CONFIG_NET_POLL_CONTROLLER is not set | 451 | # CONFIG_NET_POLL_CONTROLLER is not set |
| @@ -423,7 +467,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y | |||
| 423 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | 467 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 |
| 424 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | 468 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 |
| 425 | # CONFIG_INPUT_JOYDEV is not set | 469 | # CONFIG_INPUT_JOYDEV is not set |
| 426 | # CONFIG_INPUT_TSDEV is not set | ||
| 427 | # CONFIG_INPUT_EVDEV is not set | 470 | # CONFIG_INPUT_EVDEV is not set |
| 428 | # CONFIG_INPUT_EVBUG is not set | 471 | # CONFIG_INPUT_EVBUG is not set |
| 429 | 472 | ||
| @@ -446,8 +489,8 @@ CONFIG_MOUSE_PS2=y | |||
| 446 | CONFIG_MOUSE_PS2_ALPS=y | 489 | CONFIG_MOUSE_PS2_ALPS=y |
| 447 | CONFIG_MOUSE_PS2_LOGIPS2PP=y | 490 | CONFIG_MOUSE_PS2_LOGIPS2PP=y |
| 448 | CONFIG_MOUSE_PS2_SYNAPTICS=y | 491 | CONFIG_MOUSE_PS2_SYNAPTICS=y |
| 449 | CONFIG_MOUSE_PS2_LIFEBOOK=y | ||
| 450 | CONFIG_MOUSE_PS2_TRACKPOINT=y | 492 | CONFIG_MOUSE_PS2_TRACKPOINT=y |
| 493 | # CONFIG_MOUSE_PS2_ELANTECH is not set | ||
| 451 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | 494 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set |
| 452 | CONFIG_MOUSE_SERIAL=m | 495 | CONFIG_MOUSE_SERIAL=m |
| 453 | # CONFIG_MOUSE_VSXXXAA is not set | 496 | # CONFIG_MOUSE_VSXXXAA is not set |
| @@ -474,9 +517,11 @@ CONFIG_SERIO_LIBPS2=y | |||
| 474 | # Character devices | 517 | # Character devices |
| 475 | # | 518 | # |
| 476 | CONFIG_VT=y | 519 | CONFIG_VT=y |
| 520 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 477 | CONFIG_VT_CONSOLE=y | 521 | CONFIG_VT_CONSOLE=y |
| 478 | CONFIG_HW_CONSOLE=y | 522 | CONFIG_HW_CONSOLE=y |
| 479 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | 523 | # CONFIG_VT_HW_CONSOLE_BINDING is not set |
| 524 | CONFIG_DEVKMEM=y | ||
| 480 | # CONFIG_SERIAL_NONSTANDARD is not set | 525 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 481 | 526 | ||
| 482 | # | 527 | # |
| @@ -501,72 +546,76 @@ CONFIG_PDC_CONSOLE=y | |||
| 501 | CONFIG_SERIAL_CORE=y | 546 | CONFIG_SERIAL_CORE=y |
| 502 | CONFIG_SERIAL_CORE_CONSOLE=y | 547 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 503 | CONFIG_UNIX98_PTYS=y | 548 | CONFIG_UNIX98_PTYS=y |
| 549 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 504 | CONFIG_LEGACY_PTYS=y | 550 | CONFIG_LEGACY_PTYS=y |
| 505 | CONFIG_LEGACY_PTY_COUNT=64 | 551 | CONFIG_LEGACY_PTY_COUNT=64 |
| 506 | CONFIG_PRINTER=m | 552 | CONFIG_PRINTER=m |
| 507 | # CONFIG_LP_CONSOLE is not set | 553 | # CONFIG_LP_CONSOLE is not set |
| 508 | CONFIG_PPDEV=m | 554 | CONFIG_PPDEV=m |
| 509 | # CONFIG_TIPAR is not set | ||
| 510 | # CONFIG_IPMI_HANDLER is not set | 555 | # CONFIG_IPMI_HANDLER is not set |
| 511 | # CONFIG_WATCHDOG is not set | ||
| 512 | # CONFIG_HW_RANDOM is not set | 556 | # CONFIG_HW_RANDOM is not set |
| 513 | CONFIG_GEN_RTC=y | ||
| 514 | CONFIG_GEN_RTC_X=y | ||
| 515 | # CONFIG_R3964 is not set | 557 | # CONFIG_R3964 is not set |
| 516 | CONFIG_RAW_DRIVER=y | 558 | CONFIG_RAW_DRIVER=y |
| 517 | CONFIG_MAX_RAW_DEVS=256 | 559 | CONFIG_MAX_RAW_DEVS=256 |
| 518 | # CONFIG_TCG_TPM is not set | 560 | # CONFIG_TCG_TPM is not set |
| 519 | # CONFIG_I2C is not set | 561 | # CONFIG_I2C is not set |
| 520 | |||
| 521 | # | ||
| 522 | # SPI support | ||
| 523 | # | ||
| 524 | # CONFIG_SPI is not set | 562 | # CONFIG_SPI is not set |
| 525 | # CONFIG_SPI_MASTER is not set | ||
| 526 | # CONFIG_W1 is not set | 563 | # CONFIG_W1 is not set |
| 527 | # CONFIG_POWER_SUPPLY is not set | 564 | # CONFIG_POWER_SUPPLY is not set |
| 528 | # CONFIG_HWMON is not set | 565 | # CONFIG_HWMON is not set |
| 566 | # CONFIG_THERMAL is not set | ||
| 567 | # CONFIG_THERMAL_HWMON is not set | ||
| 568 | # CONFIG_WATCHDOG is not set | ||
| 569 | CONFIG_SSB_POSSIBLE=y | ||
| 529 | 570 | ||
| 530 | # | 571 | # |
| 531 | # Sonics Silicon Backplane | 572 | # Sonics Silicon Backplane |
| 532 | # | 573 | # |
| 533 | CONFIG_SSB_POSSIBLE=y | ||
| 534 | # CONFIG_SSB is not set | 574 | # CONFIG_SSB is not set |
| 535 | 575 | ||
| 536 | # | 576 | # |
| 537 | # Multifunction device drivers | 577 | # Multifunction device drivers |
| 538 | # | 578 | # |
| 579 | # CONFIG_MFD_CORE is not set | ||
| 539 | # CONFIG_MFD_SM501 is not set | 580 | # CONFIG_MFD_SM501 is not set |
| 581 | # CONFIG_HTC_PASIC3 is not set | ||
| 582 | # CONFIG_MFD_TMIO is not set | ||
| 583 | # CONFIG_REGULATOR is not set | ||
| 540 | 584 | ||
| 541 | # | 585 | # |
| 542 | # Multimedia devices | 586 | # Multimedia devices |
| 543 | # | 587 | # |
| 588 | |||
| 589 | # | ||
| 590 | # Multimedia core support | ||
| 591 | # | ||
| 544 | # CONFIG_VIDEO_DEV is not set | 592 | # CONFIG_VIDEO_DEV is not set |
| 545 | # CONFIG_DVB_CORE is not set | 593 | # CONFIG_DVB_CORE is not set |
| 546 | # CONFIG_DAB is not set | 594 | # CONFIG_VIDEO_MEDIA is not set |
| 547 | 595 | ||
| 548 | # | 596 | # |
| 549 | # Graphics support | 597 | # Multimedia drivers |
| 550 | # | 598 | # |
| 551 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 599 | # CONFIG_DAB is not set |
| 552 | 600 | ||
| 553 | # | 601 | # |
| 554 | # Display device support | 602 | # Graphics support |
| 555 | # | 603 | # |
| 556 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 557 | # CONFIG_VGASTATE is not set | 604 | # CONFIG_VGASTATE is not set |
| 558 | CONFIG_VIDEO_OUTPUT_CONTROL=m | 605 | CONFIG_VIDEO_OUTPUT_CONTROL=m |
| 559 | CONFIG_FB=y | 606 | CONFIG_FB=y |
| 560 | # CONFIG_FIRMWARE_EDID is not set | 607 | # CONFIG_FIRMWARE_EDID is not set |
| 561 | # CONFIG_FB_DDC is not set | 608 | # CONFIG_FB_DDC is not set |
| 609 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 562 | CONFIG_FB_CFB_FILLRECT=y | 610 | CONFIG_FB_CFB_FILLRECT=y |
| 563 | CONFIG_FB_CFB_COPYAREA=y | 611 | CONFIG_FB_CFB_COPYAREA=y |
| 564 | CONFIG_FB_CFB_IMAGEBLIT=y | 612 | CONFIG_FB_CFB_IMAGEBLIT=y |
| 613 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 565 | # CONFIG_FB_SYS_FILLRECT is not set | 614 | # CONFIG_FB_SYS_FILLRECT is not set |
| 566 | # CONFIG_FB_SYS_COPYAREA is not set | 615 | # CONFIG_FB_SYS_COPYAREA is not set |
| 567 | # CONFIG_FB_SYS_IMAGEBLIT is not set | 616 | # CONFIG_FB_SYS_IMAGEBLIT is not set |
| 617 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 568 | # CONFIG_FB_SYS_FOPS is not set | 618 | # CONFIG_FB_SYS_FOPS is not set |
| 569 | CONFIG_FB_DEFERRED_IO=y | ||
| 570 | # CONFIG_FB_SVGALIB is not set | 619 | # CONFIG_FB_SVGALIB is not set |
| 571 | # CONFIG_FB_MACMODES is not set | 620 | # CONFIG_FB_MACMODES is not set |
| 572 | # CONFIG_FB_BACKLIGHT is not set | 621 | # CONFIG_FB_BACKLIGHT is not set |
| @@ -579,6 +628,14 @@ CONFIG_FB_TILEBLITTING=y | |||
| 579 | CONFIG_FB_STI=y | 628 | CONFIG_FB_STI=y |
| 580 | # CONFIG_FB_S1D13XXX is not set | 629 | # CONFIG_FB_S1D13XXX is not set |
| 581 | # CONFIG_FB_VIRTUAL is not set | 630 | # CONFIG_FB_VIRTUAL is not set |
| 631 | # CONFIG_FB_METRONOME is not set | ||
| 632 | # CONFIG_FB_MB862XX is not set | ||
| 633 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 634 | |||
| 635 | # | ||
| 636 | # Display device support | ||
| 637 | # | ||
| 638 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 582 | 639 | ||
| 583 | # | 640 | # |
| 584 | # Console display driver support | 641 | # Console display driver support |
| @@ -606,15 +663,8 @@ CONFIG_LOGO=y | |||
| 606 | # CONFIG_LOGO_LINUX_VGA16 is not set | 663 | # CONFIG_LOGO_LINUX_VGA16 is not set |
| 607 | # CONFIG_LOGO_LINUX_CLUT224 is not set | 664 | # CONFIG_LOGO_LINUX_CLUT224 is not set |
| 608 | CONFIG_LOGO_PARISC_CLUT224=y | 665 | CONFIG_LOGO_PARISC_CLUT224=y |
| 609 | |||
| 610 | # | ||
| 611 | # Sound | ||
| 612 | # | ||
| 613 | CONFIG_SOUND=y | 666 | CONFIG_SOUND=y |
| 614 | 667 | CONFIG_SOUND_OSS_CORE=y | |
| 615 | # | ||
| 616 | # Advanced Linux Sound Architecture | ||
| 617 | # | ||
| 618 | CONFIG_SND=y | 668 | CONFIG_SND=y |
| 619 | CONFIG_SND_TIMER=y | 669 | CONFIG_SND_TIMER=y |
| 620 | CONFIG_SND_PCM=y | 670 | CONFIG_SND_PCM=y |
| @@ -630,10 +680,7 @@ CONFIG_SND_SUPPORT_OLD_API=y | |||
| 630 | CONFIG_SND_VERBOSE_PROCFS=y | 680 | CONFIG_SND_VERBOSE_PROCFS=y |
| 631 | # CONFIG_SND_VERBOSE_PRINTK is not set | 681 | # CONFIG_SND_VERBOSE_PRINTK is not set |
| 632 | # CONFIG_SND_DEBUG is not set | 682 | # CONFIG_SND_DEBUG is not set |
| 633 | 683 | CONFIG_SND_DRIVERS=y | |
| 634 | # | ||
| 635 | # Generic devices | ||
| 636 | # | ||
| 637 | # CONFIG_SND_DUMMY is not set | 684 | # CONFIG_SND_DUMMY is not set |
| 638 | # CONFIG_SND_VIRMIDI is not set | 685 | # CONFIG_SND_VIRMIDI is not set |
| 639 | # CONFIG_SND_MTPAV is not set | 686 | # CONFIG_SND_MTPAV is not set |
| @@ -641,63 +688,82 @@ CONFIG_SND_VERBOSE_PROCFS=y | |||
| 641 | # CONFIG_SND_SERIAL_U16550 is not set | 688 | # CONFIG_SND_SERIAL_U16550 is not set |
| 642 | # CONFIG_SND_MPU401 is not set | 689 | # CONFIG_SND_MPU401 is not set |
| 643 | # CONFIG_SND_PORTMAN2X4 is not set | 690 | # CONFIG_SND_PORTMAN2X4 is not set |
| 644 | 691 | CONFIG_SND_GSC=y | |
| 645 | # | ||
| 646 | # GSC devices | ||
| 647 | # | ||
| 648 | CONFIG_SND_HARMONY=y | 692 | CONFIG_SND_HARMONY=y |
| 649 | |||
| 650 | # | ||
| 651 | # System on Chip audio support | ||
| 652 | # | ||
| 653 | # CONFIG_SND_SOC is not set | 693 | # CONFIG_SND_SOC is not set |
| 654 | |||
| 655 | # | ||
| 656 | # SoC Audio support for SuperH | ||
| 657 | # | ||
| 658 | |||
| 659 | # | ||
| 660 | # Open Sound System | ||
| 661 | # | ||
| 662 | # CONFIG_SOUND_PRIME is not set | 694 | # CONFIG_SOUND_PRIME is not set |
| 663 | CONFIG_HID_SUPPORT=y | 695 | CONFIG_HID_SUPPORT=y |
| 664 | CONFIG_HID=y | 696 | CONFIG_HID=y |
| 665 | CONFIG_HID_DEBUG=y | 697 | CONFIG_HID_DEBUG=y |
| 698 | # CONFIG_HIDRAW is not set | ||
| 699 | # CONFIG_HID_PID is not set | ||
| 700 | |||
| 701 | # | ||
| 702 | # Special HID drivers | ||
| 703 | # | ||
| 704 | CONFIG_HID_COMPAT=y | ||
| 666 | CONFIG_USB_SUPPORT=y | 705 | CONFIG_USB_SUPPORT=y |
| 667 | # CONFIG_USB_ARCH_HAS_HCD is not set | 706 | # CONFIG_USB_ARCH_HAS_HCD is not set |
| 668 | # CONFIG_USB_ARCH_HAS_OHCI is not set | 707 | # CONFIG_USB_ARCH_HAS_OHCI is not set |
| 669 | # CONFIG_USB_ARCH_HAS_EHCI is not set | 708 | # CONFIG_USB_ARCH_HAS_EHCI is not set |
| 670 | 709 | ||
| 671 | # | 710 | # |
| 672 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 711 | # Enable Host or Gadget support to see Inventra options |
| 673 | # | 712 | # |
| 674 | 713 | ||
| 675 | # | 714 | # |
| 676 | # USB Gadget Support | 715 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; |
| 677 | # | 716 | # |
| 678 | # CONFIG_USB_GADGET is not set | 717 | # CONFIG_USB_GADGET is not set |
| 718 | |||
| 719 | # | ||
| 720 | # OTG and related infrastructure | ||
| 721 | # | ||
| 679 | # CONFIG_MMC is not set | 722 | # CONFIG_MMC is not set |
| 723 | # CONFIG_MEMSTICK is not set | ||
| 680 | # CONFIG_NEW_LEDS is not set | 724 | # CONFIG_NEW_LEDS is not set |
| 681 | # CONFIG_RTC_CLASS is not set | 725 | # CONFIG_ACCESSIBILITY is not set |
| 726 | CONFIG_RTC_LIB=y | ||
| 727 | CONFIG_RTC_CLASS=y | ||
| 728 | CONFIG_RTC_HCTOSYS=y | ||
| 729 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 730 | # CONFIG_RTC_DEBUG is not set | ||
| 682 | 731 | ||
| 683 | # | 732 | # |
| 684 | # DMA Engine support | 733 | # RTC interfaces |
| 685 | # | 734 | # |
| 686 | # CONFIG_DMA_ENGINE is not set | 735 | CONFIG_RTC_INTF_SYSFS=y |
| 736 | CONFIG_RTC_INTF_PROC=y | ||
| 737 | CONFIG_RTC_INTF_DEV=y | ||
| 738 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 739 | # CONFIG_RTC_DRV_TEST is not set | ||
| 687 | 740 | ||
| 688 | # | 741 | # |
| 689 | # DMA Clients | 742 | # SPI RTC drivers |
| 690 | # | 743 | # |
| 691 | 744 | ||
| 692 | # | 745 | # |
| 693 | # DMA Devices | 746 | # Platform RTC drivers |
| 694 | # | 747 | # |
| 695 | # CONFIG_AUXDISPLAY is not set | 748 | # CONFIG_RTC_DRV_DS1286 is not set |
| 749 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 750 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 751 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 752 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 753 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 754 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 755 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 756 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 757 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 696 | 758 | ||
| 697 | # | 759 | # |
| 698 | # Userspace I/O | 760 | # on-CPU RTC drivers |
| 699 | # | 761 | # |
| 762 | CONFIG_RTC_DRV_PARISC=y | ||
| 763 | # CONFIG_DMADEVICES is not set | ||
| 764 | # CONFIG_AUXDISPLAY is not set | ||
| 700 | # CONFIG_UIO is not set | 765 | # CONFIG_UIO is not set |
| 766 | # CONFIG_STAGING is not set | ||
| 701 | 767 | ||
| 702 | # | 768 | # |
| 703 | # File systems | 769 | # File systems |
| @@ -707,7 +773,7 @@ CONFIG_EXT2_FS=y | |||
| 707 | # CONFIG_EXT2_FS_XIP is not set | 773 | # CONFIG_EXT2_FS_XIP is not set |
| 708 | CONFIG_EXT3_FS=y | 774 | CONFIG_EXT3_FS=y |
| 709 | # CONFIG_EXT3_FS_XATTR is not set | 775 | # CONFIG_EXT3_FS_XATTR is not set |
| 710 | # CONFIG_EXT4DEV_FS is not set | 776 | # CONFIG_EXT4_FS is not set |
| 711 | CONFIG_JBD=y | 777 | CONFIG_JBD=y |
| 712 | # CONFIG_JBD_DEBUG is not set | 778 | # CONFIG_JBD_DEBUG is not set |
| 713 | # CONFIG_REISERFS_FS is not set | 779 | # CONFIG_REISERFS_FS is not set |
| @@ -717,19 +783,18 @@ CONFIG_JFS_FS=m | |||
| 717 | # CONFIG_JFS_DEBUG is not set | 783 | # CONFIG_JFS_DEBUG is not set |
| 718 | # CONFIG_JFS_STATISTICS is not set | 784 | # CONFIG_JFS_STATISTICS is not set |
| 719 | CONFIG_FS_POSIX_ACL=y | 785 | CONFIG_FS_POSIX_ACL=y |
| 786 | CONFIG_FILE_LOCKING=y | ||
| 720 | CONFIG_XFS_FS=m | 787 | CONFIG_XFS_FS=m |
| 721 | # CONFIG_XFS_QUOTA is not set | 788 | # CONFIG_XFS_QUOTA is not set |
| 722 | # CONFIG_XFS_SECURITY is not set | ||
| 723 | # CONFIG_XFS_POSIX_ACL is not set | 789 | # CONFIG_XFS_POSIX_ACL is not set |
| 724 | # CONFIG_XFS_RT is not set | 790 | # CONFIG_XFS_RT is not set |
| 725 | # CONFIG_GFS2_FS is not set | 791 | # CONFIG_XFS_DEBUG is not set |
| 726 | # CONFIG_OCFS2_FS is not set | 792 | # CONFIG_OCFS2_FS is not set |
| 727 | # CONFIG_MINIX_FS is not set | 793 | # CONFIG_BTRFS_FS is not set |
| 728 | # CONFIG_ROMFS_FS is not set | 794 | CONFIG_DNOTIFY=y |
| 729 | CONFIG_INOTIFY=y | 795 | CONFIG_INOTIFY=y |
| 730 | CONFIG_INOTIFY_USER=y | 796 | CONFIG_INOTIFY_USER=y |
| 731 | # CONFIG_QUOTA is not set | 797 | # CONFIG_QUOTA is not set |
| 732 | CONFIG_DNOTIFY=y | ||
| 733 | # CONFIG_AUTOFS_FS is not set | 798 | # CONFIG_AUTOFS_FS is not set |
| 734 | CONFIG_AUTOFS4_FS=y | 799 | CONFIG_AUTOFS4_FS=y |
| 735 | # CONFIG_FUSE_FS is not set | 800 | # CONFIG_FUSE_FS is not set |
| @@ -759,16 +824,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | |||
| 759 | CONFIG_PROC_FS=y | 824 | CONFIG_PROC_FS=y |
| 760 | CONFIG_PROC_KCORE=y | 825 | CONFIG_PROC_KCORE=y |
| 761 | CONFIG_PROC_SYSCTL=y | 826 | CONFIG_PROC_SYSCTL=y |
| 827 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 762 | CONFIG_SYSFS=y | 828 | CONFIG_SYSFS=y |
| 763 | CONFIG_TMPFS=y | 829 | CONFIG_TMPFS=y |
| 764 | # CONFIG_TMPFS_POSIX_ACL is not set | 830 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 765 | # CONFIG_HUGETLB_PAGE is not set | 831 | # CONFIG_HUGETLB_PAGE is not set |
| 766 | CONFIG_RAMFS=y | ||
| 767 | # CONFIG_CONFIGFS_FS is not set | 832 | # CONFIG_CONFIGFS_FS is not set |
| 768 | 833 | CONFIG_MISC_FILESYSTEMS=y | |
| 769 | # | ||
| 770 | # Miscellaneous filesystems | ||
| 771 | # | ||
| 772 | # CONFIG_ADFS_FS is not set | 834 | # CONFIG_ADFS_FS is not set |
| 773 | # CONFIG_AFFS_FS is not set | 835 | # CONFIG_AFFS_FS is not set |
| 774 | # CONFIG_ECRYPT_FS is not set | 836 | # CONFIG_ECRYPT_FS is not set |
| @@ -778,35 +840,34 @@ CONFIG_RAMFS=y | |||
| 778 | # CONFIG_BFS_FS is not set | 840 | # CONFIG_BFS_FS is not set |
| 779 | # CONFIG_EFS_FS is not set | 841 | # CONFIG_EFS_FS is not set |
| 780 | # CONFIG_CRAMFS is not set | 842 | # CONFIG_CRAMFS is not set |
| 843 | # CONFIG_SQUASHFS is not set | ||
| 781 | # CONFIG_VXFS_FS is not set | 844 | # CONFIG_VXFS_FS is not set |
| 845 | # CONFIG_MINIX_FS is not set | ||
| 846 | # CONFIG_OMFS_FS is not set | ||
| 782 | # CONFIG_HPFS_FS is not set | 847 | # CONFIG_HPFS_FS is not set |
| 783 | # CONFIG_QNX4FS_FS is not set | 848 | # CONFIG_QNX4FS_FS is not set |
| 849 | # CONFIG_ROMFS_FS is not set | ||
| 784 | # CONFIG_SYSV_FS is not set | 850 | # CONFIG_SYSV_FS is not set |
| 785 | CONFIG_UFS_FS=m | 851 | CONFIG_UFS_FS=m |
| 786 | # CONFIG_UFS_FS_WRITE is not set | 852 | # CONFIG_UFS_FS_WRITE is not set |
| 787 | # CONFIG_UFS_DEBUG is not set | 853 | # CONFIG_UFS_DEBUG is not set |
| 788 | 854 | CONFIG_NETWORK_FILESYSTEMS=y | |
| 789 | # | ||
| 790 | # Network File Systems | ||
| 791 | # | ||
| 792 | CONFIG_NFS_FS=y | 855 | CONFIG_NFS_FS=y |
| 793 | CONFIG_NFS_V3=y | 856 | CONFIG_NFS_V3=y |
| 794 | # CONFIG_NFS_V3_ACL is not set | 857 | # CONFIG_NFS_V3_ACL is not set |
| 795 | CONFIG_NFS_V4=y | 858 | CONFIG_NFS_V4=y |
| 796 | CONFIG_NFS_DIRECTIO=y | 859 | CONFIG_ROOT_NFS=y |
| 797 | CONFIG_NFSD=m | 860 | CONFIG_NFSD=m |
| 798 | CONFIG_NFSD_V3=y | 861 | CONFIG_NFSD_V3=y |
| 799 | # CONFIG_NFSD_V3_ACL is not set | 862 | # CONFIG_NFSD_V3_ACL is not set |
| 800 | CONFIG_NFSD_V4=y | 863 | CONFIG_NFSD_V4=y |
| 801 | CONFIG_NFSD_TCP=y | ||
| 802 | CONFIG_ROOT_NFS=y | ||
| 803 | CONFIG_LOCKD=y | 864 | CONFIG_LOCKD=y |
| 804 | CONFIG_LOCKD_V4=y | 865 | CONFIG_LOCKD_V4=y |
| 805 | CONFIG_EXPORTFS=m | 866 | CONFIG_EXPORTFS=m |
| 806 | CONFIG_NFS_COMMON=y | 867 | CONFIG_NFS_COMMON=y |
| 807 | CONFIG_SUNRPC=y | 868 | CONFIG_SUNRPC=y |
| 808 | CONFIG_SUNRPC_GSS=y | 869 | CONFIG_SUNRPC_GSS=y |
| 809 | # CONFIG_SUNRPC_BIND34 is not set | 870 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 810 | CONFIG_RPCSEC_GSS_KRB5=y | 871 | CONFIG_RPCSEC_GSS_KRB5=y |
| 811 | CONFIG_RPCSEC_GSS_SPKM3=m | 872 | CONFIG_RPCSEC_GSS_SPKM3=m |
| 812 | CONFIG_SMB_FS=m | 873 | CONFIG_SMB_FS=m |
| @@ -815,6 +876,7 @@ CONFIG_SMB_NLS_REMOTE="cp437" | |||
| 815 | CONFIG_CIFS=m | 876 | CONFIG_CIFS=m |
| 816 | # CONFIG_CIFS_STATS is not set | 877 | # CONFIG_CIFS_STATS is not set |
| 817 | # CONFIG_CIFS_WEAK_PW_HASH is not set | 878 | # CONFIG_CIFS_WEAK_PW_HASH is not set |
| 879 | # CONFIG_CIFS_UPCALL is not set | ||
| 818 | # CONFIG_CIFS_XATTR is not set | 880 | # CONFIG_CIFS_XATTR is not set |
| 819 | # CONFIG_CIFS_DEBUG2 is not set | 881 | # CONFIG_CIFS_DEBUG2 is not set |
| 820 | # CONFIG_CIFS_EXPERIMENTAL is not set | 882 | # CONFIG_CIFS_EXPERIMENTAL is not set |
| @@ -827,10 +889,6 @@ CONFIG_CIFS=m | |||
| 827 | # | 889 | # |
| 828 | # CONFIG_PARTITION_ADVANCED is not set | 890 | # CONFIG_PARTITION_ADVANCED is not set |
| 829 | CONFIG_MSDOS_PARTITION=y | 891 | CONFIG_MSDOS_PARTITION=y |
| 830 | |||
| 831 | # | ||
| 832 | # Native Language Support | ||
| 833 | # | ||
| 834 | CONFIG_NLS=y | 892 | CONFIG_NLS=y |
| 835 | CONFIG_NLS_DEFAULT="iso8859-1" | 893 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 836 | CONFIG_NLS_CODEPAGE_437=m | 894 | CONFIG_NLS_CODEPAGE_437=m |
| @@ -871,33 +929,28 @@ CONFIG_NLS_ISO8859_15=m | |||
| 871 | CONFIG_NLS_KOI8_R=m | 929 | CONFIG_NLS_KOI8_R=m |
| 872 | CONFIG_NLS_KOI8_U=m | 930 | CONFIG_NLS_KOI8_U=m |
| 873 | CONFIG_NLS_UTF8=m | 931 | CONFIG_NLS_UTF8=m |
| 874 | |||
| 875 | # | ||
| 876 | # Distributed Lock Manager | ||
| 877 | # | ||
| 878 | # CONFIG_DLM is not set | 932 | # CONFIG_DLM is not set |
| 879 | 933 | ||
| 880 | # | 934 | # |
| 881 | # Profiling support | ||
| 882 | # | ||
| 883 | CONFIG_PROFILING=y | ||
| 884 | CONFIG_OPROFILE=m | ||
| 885 | |||
| 886 | # | ||
| 887 | # Kernel hacking | 935 | # Kernel hacking |
| 888 | # | 936 | # |
| 889 | # CONFIG_PRINTK_TIME is not set | 937 | # CONFIG_PRINTK_TIME is not set |
| 938 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 890 | CONFIG_ENABLE_MUST_CHECK=y | 939 | CONFIG_ENABLE_MUST_CHECK=y |
| 940 | CONFIG_FRAME_WARN=1024 | ||
| 891 | CONFIG_MAGIC_SYSRQ=y | 941 | CONFIG_MAGIC_SYSRQ=y |
| 892 | # CONFIG_UNUSED_SYMBOLS is not set | 942 | # CONFIG_UNUSED_SYMBOLS is not set |
| 893 | # CONFIG_DEBUG_FS is not set | 943 | CONFIG_DEBUG_FS=y |
| 894 | # CONFIG_HEADERS_CHECK is not set | 944 | # CONFIG_HEADERS_CHECK is not set |
| 895 | CONFIG_DEBUG_KERNEL=y | 945 | CONFIG_DEBUG_KERNEL=y |
| 896 | # CONFIG_DEBUG_SHIRQ is not set | 946 | # CONFIG_DEBUG_SHIRQ is not set |
| 897 | CONFIG_DETECT_SOFTLOCKUP=y | 947 | CONFIG_DETECT_SOFTLOCKUP=y |
| 948 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 949 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 898 | CONFIG_SCHED_DEBUG=y | 950 | CONFIG_SCHED_DEBUG=y |
| 899 | # CONFIG_SCHEDSTATS is not set | 951 | # CONFIG_SCHEDSTATS is not set |
| 900 | # CONFIG_TIMER_STATS is not set | 952 | # CONFIG_TIMER_STATS is not set |
| 953 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 901 | # CONFIG_DEBUG_SLAB is not set | 954 | # CONFIG_DEBUG_SLAB is not set |
| 902 | # CONFIG_DEBUG_RT_MUTEXES is not set | 955 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| 903 | # CONFIG_RT_MUTEX_TESTER is not set | 956 | # CONFIG_RT_MUTEX_TESTER is not set |
| @@ -909,10 +962,32 @@ CONFIG_DEBUG_MUTEXES=y | |||
| 909 | CONFIG_DEBUG_BUGVERBOSE=y | 962 | CONFIG_DEBUG_BUGVERBOSE=y |
| 910 | # CONFIG_DEBUG_INFO is not set | 963 | # CONFIG_DEBUG_INFO is not set |
| 911 | # CONFIG_DEBUG_VM is not set | 964 | # CONFIG_DEBUG_VM is not set |
| 965 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 966 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 912 | # CONFIG_DEBUG_LIST is not set | 967 | # CONFIG_DEBUG_LIST is not set |
| 913 | CONFIG_FORCED_INLINING=y | 968 | # CONFIG_DEBUG_SG is not set |
| 969 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 970 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 914 | # CONFIG_RCU_TORTURE_TEST is not set | 971 | # CONFIG_RCU_TORTURE_TEST is not set |
| 972 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 973 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 974 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 915 | # CONFIG_FAULT_INJECTION is not set | 975 | # CONFIG_FAULT_INJECTION is not set |
| 976 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 977 | CONFIG_NOP_TRACER=y | ||
| 978 | CONFIG_RING_BUFFER=y | ||
| 979 | CONFIG_TRACING=y | ||
| 980 | |||
| 981 | # | ||
| 982 | # Tracers | ||
| 983 | # | ||
| 984 | # CONFIG_SCHED_TRACER is not set | ||
| 985 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 986 | # CONFIG_BOOT_TRACER is not set | ||
| 987 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 988 | # CONFIG_FTRACE_STARTUP_TEST is not set | ||
| 989 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 990 | # CONFIG_SAMPLES is not set | ||
| 916 | CONFIG_DEBUG_RODATA=y | 991 | CONFIG_DEBUG_RODATA=y |
| 917 | 992 | ||
| 918 | # | 993 | # |
| @@ -921,57 +996,113 @@ CONFIG_DEBUG_RODATA=y | |||
| 921 | CONFIG_KEYS=y | 996 | CONFIG_KEYS=y |
| 922 | CONFIG_KEYS_DEBUG_PROC_KEYS=y | 997 | CONFIG_KEYS_DEBUG_PROC_KEYS=y |
| 923 | # CONFIG_SECURITY is not set | 998 | # CONFIG_SECURITY is not set |
| 999 | # CONFIG_SECURITYFS is not set | ||
| 1000 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 924 | CONFIG_CRYPTO=y | 1001 | CONFIG_CRYPTO=y |
| 1002 | |||
| 1003 | # | ||
| 1004 | # Crypto core or helper | ||
| 1005 | # | ||
| 1006 | # CONFIG_CRYPTO_FIPS is not set | ||
| 925 | CONFIG_CRYPTO_ALGAPI=y | 1007 | CONFIG_CRYPTO_ALGAPI=y |
| 1008 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1009 | CONFIG_CRYPTO_AEAD=m | ||
| 1010 | CONFIG_CRYPTO_AEAD2=y | ||
| 926 | CONFIG_CRYPTO_BLKCIPHER=y | 1011 | CONFIG_CRYPTO_BLKCIPHER=y |
| 1012 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 927 | CONFIG_CRYPTO_HASH=y | 1013 | CONFIG_CRYPTO_HASH=y |
| 1014 | CONFIG_CRYPTO_HASH2=y | ||
| 1015 | CONFIG_CRYPTO_RNG2=y | ||
| 928 | CONFIG_CRYPTO_MANAGER=y | 1016 | CONFIG_CRYPTO_MANAGER=y |
| 1017 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1018 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1019 | CONFIG_CRYPTO_NULL=m | ||
| 1020 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1021 | CONFIG_CRYPTO_AUTHENC=m | ||
| 1022 | CONFIG_CRYPTO_TEST=m | ||
| 1023 | |||
| 1024 | # | ||
| 1025 | # Authenticated Encryption with Associated Data | ||
| 1026 | # | ||
| 1027 | # CONFIG_CRYPTO_CCM is not set | ||
| 1028 | # CONFIG_CRYPTO_GCM is not set | ||
| 1029 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1030 | |||
| 1031 | # | ||
| 1032 | # Block modes | ||
| 1033 | # | ||
| 1034 | CONFIG_CRYPTO_CBC=y | ||
| 1035 | # CONFIG_CRYPTO_CTR is not set | ||
| 1036 | # CONFIG_CRYPTO_CTS is not set | ||
| 1037 | CONFIG_CRYPTO_ECB=m | ||
| 1038 | # CONFIG_CRYPTO_LRW is not set | ||
| 1039 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1040 | # CONFIG_CRYPTO_XTS is not set | ||
| 1041 | |||
| 1042 | # | ||
| 1043 | # Hash modes | ||
| 1044 | # | ||
| 929 | CONFIG_CRYPTO_HMAC=y | 1045 | CONFIG_CRYPTO_HMAC=y |
| 930 | # CONFIG_CRYPTO_XCBC is not set | 1046 | # CONFIG_CRYPTO_XCBC is not set |
| 931 | CONFIG_CRYPTO_NULL=m | 1047 | |
| 1048 | # | ||
| 1049 | # Digest | ||
| 1050 | # | ||
| 1051 | CONFIG_CRYPTO_CRC32C=m | ||
| 932 | CONFIG_CRYPTO_MD4=m | 1052 | CONFIG_CRYPTO_MD4=m |
| 933 | CONFIG_CRYPTO_MD5=y | 1053 | CONFIG_CRYPTO_MD5=y |
| 1054 | CONFIG_CRYPTO_MICHAEL_MIC=m | ||
| 1055 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1056 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1057 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1058 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 934 | CONFIG_CRYPTO_SHA1=m | 1059 | CONFIG_CRYPTO_SHA1=m |
| 935 | CONFIG_CRYPTO_SHA256=m | 1060 | CONFIG_CRYPTO_SHA256=m |
| 936 | CONFIG_CRYPTO_SHA512=m | 1061 | CONFIG_CRYPTO_SHA512=m |
| 937 | CONFIG_CRYPTO_WP512=m | ||
| 938 | CONFIG_CRYPTO_TGR192=m | 1062 | CONFIG_CRYPTO_TGR192=m |
| 939 | # CONFIG_CRYPTO_GF128MUL is not set | 1063 | CONFIG_CRYPTO_WP512=m |
| 940 | CONFIG_CRYPTO_ECB=m | 1064 | |
| 941 | CONFIG_CRYPTO_CBC=y | 1065 | # |
| 942 | # CONFIG_CRYPTO_PCBC is not set | 1066 | # Ciphers |
| 943 | # CONFIG_CRYPTO_LRW is not set | 1067 | # |
| 944 | # CONFIG_CRYPTO_XTS is not set | ||
| 945 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 946 | CONFIG_CRYPTO_DES=y | ||
| 947 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 948 | CONFIG_CRYPTO_BLOWFISH=m | ||
| 949 | CONFIG_CRYPTO_TWOFISH=m | ||
| 950 | CONFIG_CRYPTO_TWOFISH_COMMON=m | ||
| 951 | CONFIG_CRYPTO_SERPENT=m | ||
| 952 | CONFIG_CRYPTO_AES=m | 1068 | CONFIG_CRYPTO_AES=m |
| 1069 | CONFIG_CRYPTO_ANUBIS=m | ||
| 1070 | CONFIG_CRYPTO_ARC4=m | ||
| 1071 | CONFIG_CRYPTO_BLOWFISH=m | ||
| 1072 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 953 | CONFIG_CRYPTO_CAST5=m | 1073 | CONFIG_CRYPTO_CAST5=m |
| 954 | CONFIG_CRYPTO_CAST6=m | 1074 | CONFIG_CRYPTO_CAST6=m |
| 955 | CONFIG_CRYPTO_TEA=m | 1075 | CONFIG_CRYPTO_DES=y |
| 956 | CONFIG_CRYPTO_ARC4=m | 1076 | # CONFIG_CRYPTO_FCRYPT is not set |
| 957 | CONFIG_CRYPTO_KHAZAD=m | 1077 | CONFIG_CRYPTO_KHAZAD=m |
| 958 | CONFIG_CRYPTO_ANUBIS=m | 1078 | # CONFIG_CRYPTO_SALSA20 is not set |
| 959 | # CONFIG_CRYPTO_SEED is not set | 1079 | # CONFIG_CRYPTO_SEED is not set |
| 1080 | CONFIG_CRYPTO_SERPENT=m | ||
| 1081 | CONFIG_CRYPTO_TEA=m | ||
| 1082 | CONFIG_CRYPTO_TWOFISH=m | ||
| 1083 | CONFIG_CRYPTO_TWOFISH_COMMON=m | ||
| 1084 | |||
| 1085 | # | ||
| 1086 | # Compression | ||
| 1087 | # | ||
| 960 | CONFIG_CRYPTO_DEFLATE=m | 1088 | CONFIG_CRYPTO_DEFLATE=m |
| 961 | CONFIG_CRYPTO_MICHAEL_MIC=m | 1089 | # CONFIG_CRYPTO_LZO is not set |
| 962 | CONFIG_CRYPTO_CRC32C=m | 1090 | |
| 963 | # CONFIG_CRYPTO_CAMELLIA is not set | 1091 | # |
| 964 | CONFIG_CRYPTO_TEST=m | 1092 | # Random Number Generation |
| 965 | # CONFIG_CRYPTO_AUTHENC is not set | 1093 | # |
| 1094 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 966 | # CONFIG_CRYPTO_HW is not set | 1095 | # CONFIG_CRYPTO_HW is not set |
| 967 | 1096 | ||
| 968 | # | 1097 | # |
| 969 | # Library routines | 1098 | # Library routines |
| 970 | # | 1099 | # |
| 971 | CONFIG_BITREVERSE=y | 1100 | CONFIG_BITREVERSE=y |
| 1101 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 972 | CONFIG_CRC_CCITT=m | 1102 | CONFIG_CRC_CCITT=m |
| 973 | # CONFIG_CRC16 is not set | 1103 | # CONFIG_CRC16 is not set |
| 974 | # CONFIG_CRC_ITU_T is not set | 1104 | # CONFIG_CRC_T10DIF is not set |
| 1105 | CONFIG_CRC_ITU_T=m | ||
| 975 | CONFIG_CRC32=y | 1106 | CONFIG_CRC32=y |
| 976 | # CONFIG_CRC7 is not set | 1107 | # CONFIG_CRC7 is not set |
| 977 | CONFIG_LIBCRC32C=m | 1108 | CONFIG_LIBCRC32C=m |
diff --git a/arch/parisc/configs/a500_defconfig b/arch/parisc/configs/a500_defconfig index ddacc72e38fb..f12e4b8349d9 100644 --- a/arch/parisc/configs/a500_defconfig +++ b/arch/parisc/configs/a500_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.23 | 3 | # Linux kernel version: 2.6.29-rc8 |
| 4 | # Fri Oct 12 21:12:44 2007 | 4 | # Fri Mar 13 01:32:56 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_PARISC=y | 6 | CONFIG_PARISC=y |
| 7 | CONFIG_MMU=y | 7 | CONFIG_MMU=y |
| @@ -34,18 +34,30 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 34 | CONFIG_POSIX_MQUEUE=y | 34 | CONFIG_POSIX_MQUEUE=y |
| 35 | # CONFIG_BSD_PROCESS_ACCT is not set | 35 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 36 | # CONFIG_TASKSTATS is not set | 36 | # CONFIG_TASKSTATS is not set |
| 37 | # CONFIG_USER_NS is not set | ||
| 38 | # CONFIG_AUDIT is not set | 37 | # CONFIG_AUDIT is not set |
| 38 | |||
| 39 | # | ||
| 40 | # RCU Subsystem | ||
| 41 | # | ||
| 42 | CONFIG_CLASSIC_RCU=y | ||
| 43 | # CONFIG_TREE_RCU is not set | ||
| 44 | # CONFIG_PREEMPT_RCU is not set | ||
| 45 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 46 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 39 | CONFIG_IKCONFIG=y | 47 | CONFIG_IKCONFIG=y |
| 40 | CONFIG_IKCONFIG_PROC=y | 48 | CONFIG_IKCONFIG_PROC=y |
| 41 | CONFIG_LOG_BUF_SHIFT=16 | 49 | CONFIG_LOG_BUF_SHIFT=16 |
| 42 | # CONFIG_CPUSETS is not set | 50 | # CONFIG_GROUP_SCHED is not set |
| 51 | # CONFIG_CGROUPS is not set | ||
| 43 | CONFIG_SYSFS_DEPRECATED=y | 52 | CONFIG_SYSFS_DEPRECATED=y |
| 53 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 44 | # CONFIG_RELAY is not set | 54 | # CONFIG_RELAY is not set |
| 55 | # CONFIG_NAMESPACES is not set | ||
| 45 | CONFIG_BLK_DEV_INITRD=y | 56 | CONFIG_BLK_DEV_INITRD=y |
| 46 | CONFIG_INITRAMFS_SOURCE="" | 57 | CONFIG_INITRAMFS_SOURCE="" |
| 47 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 58 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 48 | CONFIG_SYSCTL=y | 59 | CONFIG_SYSCTL=y |
| 60 | CONFIG_ANON_INODES=y | ||
| 49 | CONFIG_EMBEDDED=y | 61 | CONFIG_EMBEDDED=y |
| 50 | CONFIG_SYSCTL_SYSCALL=y | 62 | CONFIG_SYSCTL_SYSCALL=y |
| 51 | CONFIG_KALLSYMS=y | 63 | CONFIG_KALLSYMS=y |
| @@ -57,28 +69,40 @@ CONFIG_BUG=y | |||
| 57 | CONFIG_ELF_CORE=y | 69 | CONFIG_ELF_CORE=y |
| 58 | CONFIG_BASE_FULL=y | 70 | CONFIG_BASE_FULL=y |
| 59 | CONFIG_FUTEX=y | 71 | CONFIG_FUTEX=y |
| 60 | CONFIG_ANON_INODES=y | ||
| 61 | CONFIG_EPOLL=y | 72 | CONFIG_EPOLL=y |
| 62 | CONFIG_SIGNALFD=y | 73 | CONFIG_SIGNALFD=y |
| 74 | CONFIG_TIMERFD=y | ||
| 63 | CONFIG_EVENTFD=y | 75 | CONFIG_EVENTFD=y |
| 64 | CONFIG_SHMEM=y | 76 | CONFIG_SHMEM=y |
| 77 | CONFIG_AIO=y | ||
| 65 | CONFIG_VM_EVENT_COUNTERS=y | 78 | CONFIG_VM_EVENT_COUNTERS=y |
| 79 | CONFIG_PCI_QUIRKS=y | ||
| 80 | CONFIG_COMPAT_BRK=y | ||
| 66 | CONFIG_SLAB=y | 81 | CONFIG_SLAB=y |
| 67 | # CONFIG_SLUB is not set | 82 | # CONFIG_SLUB is not set |
| 68 | # CONFIG_SLOB is not set | 83 | # CONFIG_SLOB is not set |
| 84 | CONFIG_PROFILING=y | ||
| 85 | CONFIG_TRACEPOINTS=y | ||
| 86 | # CONFIG_MARKERS is not set | ||
| 87 | CONFIG_OPROFILE=m | ||
| 88 | CONFIG_HAVE_OPROFILE=y | ||
| 89 | CONFIG_USE_GENERIC_SMP_HELPERS=y | ||
| 90 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 91 | CONFIG_SLABINFO=y | ||
| 69 | CONFIG_RT_MUTEXES=y | 92 | CONFIG_RT_MUTEXES=y |
| 70 | # CONFIG_TINY_SHMEM is not set | ||
| 71 | CONFIG_BASE_SMALL=0 | 93 | CONFIG_BASE_SMALL=0 |
| 72 | CONFIG_MODULES=y | 94 | CONFIG_MODULES=y |
| 95 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 73 | CONFIG_MODULE_UNLOAD=y | 96 | CONFIG_MODULE_UNLOAD=y |
| 74 | CONFIG_MODULE_FORCE_UNLOAD=y | 97 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 75 | # CONFIG_MODVERSIONS is not set | 98 | # CONFIG_MODVERSIONS is not set |
| 76 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 99 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 77 | CONFIG_KMOD=y | 100 | CONFIG_INIT_ALL_POSSIBLE=y |
| 78 | CONFIG_STOP_MACHINE=y | 101 | CONFIG_STOP_MACHINE=y |
| 79 | CONFIG_BLOCK=y | 102 | CONFIG_BLOCK=y |
| 80 | # CONFIG_BLK_DEV_IO_TRACE is not set | 103 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 81 | # CONFIG_BLK_DEV_BSG is not set | 104 | # CONFIG_BLK_DEV_BSG is not set |
| 105 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 82 | CONFIG_BLOCK_COMPAT=y | 106 | CONFIG_BLOCK_COMPAT=y |
| 83 | 107 | ||
| 84 | # | 108 | # |
| @@ -93,6 +117,7 @@ CONFIG_IOSCHED_CFQ=y | |||
| 93 | CONFIG_DEFAULT_CFQ=y | 117 | CONFIG_DEFAULT_CFQ=y |
| 94 | # CONFIG_DEFAULT_NOOP is not set | 118 | # CONFIG_DEFAULT_NOOP is not set |
| 95 | CONFIG_DEFAULT_IOSCHED="cfq" | 119 | CONFIG_DEFAULT_IOSCHED="cfq" |
| 120 | # CONFIG_FREEZER is not set | ||
| 96 | 121 | ||
| 97 | # | 122 | # |
| 98 | # Processor type and features | 123 | # Processor type and features |
| @@ -118,12 +143,12 @@ CONFIG_NODES_SHIFT=3 | |||
| 118 | CONFIG_PREEMPT_NONE=y | 143 | CONFIG_PREEMPT_NONE=y |
| 119 | # CONFIG_PREEMPT_VOLUNTARY is not set | 144 | # CONFIG_PREEMPT_VOLUNTARY is not set |
| 120 | # CONFIG_PREEMPT is not set | 145 | # CONFIG_PREEMPT is not set |
| 121 | CONFIG_PREEMPT_BKL=y | ||
| 122 | # CONFIG_HZ_100 is not set | 146 | # CONFIG_HZ_100 is not set |
| 123 | CONFIG_HZ_250=y | 147 | CONFIG_HZ_250=y |
| 124 | # CONFIG_HZ_300 is not set | 148 | # CONFIG_HZ_300 is not set |
| 125 | # CONFIG_HZ_1000 is not set | 149 | # CONFIG_HZ_1000 is not set |
| 126 | CONFIG_HZ=250 | 150 | CONFIG_HZ=250 |
| 151 | # CONFIG_SCHED_HRTICK is not set | ||
| 127 | CONFIG_SELECT_MEMORY_MODEL=y | 152 | CONFIG_SELECT_MEMORY_MODEL=y |
| 128 | # CONFIG_FLATMEM_MANUAL is not set | 153 | # CONFIG_FLATMEM_MANUAL is not set |
| 129 | CONFIG_DISCONTIGMEM_MANUAL=y | 154 | CONFIG_DISCONTIGMEM_MANUAL=y |
| @@ -131,11 +156,12 @@ CONFIG_DISCONTIGMEM_MANUAL=y | |||
| 131 | CONFIG_DISCONTIGMEM=y | 156 | CONFIG_DISCONTIGMEM=y |
| 132 | CONFIG_FLAT_NODE_MEM_MAP=y | 157 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 133 | CONFIG_NEED_MULTIPLE_NODES=y | 158 | CONFIG_NEED_MULTIPLE_NODES=y |
| 134 | # CONFIG_SPARSEMEM_STATIC is not set | 159 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 135 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 160 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 136 | CONFIG_RESOURCES_64BIT=y | 161 | CONFIG_PHYS_ADDR_T_64BIT=y |
| 137 | CONFIG_ZONE_DMA_FLAG=0 | 162 | CONFIG_ZONE_DMA_FLAG=0 |
| 138 | CONFIG_VIRT_TO_BUS=y | 163 | CONFIG_VIRT_TO_BUS=y |
| 164 | CONFIG_UNEVICTABLE_LRU=y | ||
| 139 | CONFIG_COMPAT=y | 165 | CONFIG_COMPAT=y |
| 140 | CONFIG_NR_CPUS=8 | 166 | CONFIG_NR_CPUS=8 |
| 141 | 167 | ||
| @@ -145,14 +171,13 @@ CONFIG_NR_CPUS=8 | |||
| 145 | # CONFIG_GSC is not set | 171 | # CONFIG_GSC is not set |
| 146 | CONFIG_PCI=y | 172 | CONFIG_PCI=y |
| 147 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 173 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 174 | CONFIG_PCI_LEGACY=y | ||
| 148 | # CONFIG_PCI_DEBUG is not set | 175 | # CONFIG_PCI_DEBUG is not set |
| 176 | # CONFIG_PCI_STUB is not set | ||
| 149 | CONFIG_PCI_LBA=y | 177 | CONFIG_PCI_LBA=y |
| 150 | CONFIG_IOSAPIC=y | 178 | CONFIG_IOSAPIC=y |
| 151 | CONFIG_IOMMU_SBA=y | 179 | CONFIG_IOMMU_SBA=y |
| 152 | 180 | CONFIG_IOMMU_HELPER=y | |
| 153 | # | ||
| 154 | # PCCARD (PCMCIA/CardBus) support | ||
| 155 | # | ||
| 156 | CONFIG_PCCARD=m | 181 | CONFIG_PCCARD=m |
| 157 | # CONFIG_PCMCIA_DEBUG is not set | 182 | # CONFIG_PCMCIA_DEBUG is not set |
| 158 | CONFIG_PCMCIA=m | 183 | CONFIG_PCMCIA=m |
| @@ -187,16 +212,15 @@ CONFIG_PDC_STABLE=y | |||
| 187 | # Executable file formats | 212 | # Executable file formats |
| 188 | # | 213 | # |
| 189 | CONFIG_BINFMT_ELF=y | 214 | CONFIG_BINFMT_ELF=y |
| 215 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 216 | # CONFIG_HAVE_AOUT is not set | ||
| 190 | # CONFIG_BINFMT_MISC is not set | 217 | # CONFIG_BINFMT_MISC is not set |
| 191 | |||
| 192 | # | ||
| 193 | # Networking | ||
| 194 | # | ||
| 195 | CONFIG_NET=y | 218 | CONFIG_NET=y |
| 196 | 219 | ||
| 197 | # | 220 | # |
| 198 | # Networking options | 221 | # Networking options |
| 199 | # | 222 | # |
| 223 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 200 | CONFIG_PACKET=y | 224 | CONFIG_PACKET=y |
| 201 | CONFIG_PACKET_MMAP=y | 225 | CONFIG_PACKET_MMAP=y |
| 202 | CONFIG_UNIX=y | 226 | CONFIG_UNIX=y |
| @@ -204,6 +228,8 @@ CONFIG_XFRM=y | |||
| 204 | CONFIG_XFRM_USER=m | 228 | CONFIG_XFRM_USER=m |
| 205 | # CONFIG_XFRM_SUB_POLICY is not set | 229 | # CONFIG_XFRM_SUB_POLICY is not set |
| 206 | # CONFIG_XFRM_MIGRATE is not set | 230 | # CONFIG_XFRM_MIGRATE is not set |
| 231 | # CONFIG_XFRM_STATISTICS is not set | ||
| 232 | CONFIG_XFRM_IPCOMP=m | ||
| 207 | CONFIG_NET_KEY=m | 233 | CONFIG_NET_KEY=m |
| 208 | # CONFIG_NET_KEY_MIGRATE is not set | 234 | # CONFIG_NET_KEY_MIGRATE is not set |
| 209 | CONFIG_INET=y | 235 | CONFIG_INET=y |
| @@ -234,7 +260,6 @@ CONFIG_INET_TCP_DIAG=y | |||
| 234 | CONFIG_TCP_CONG_CUBIC=y | 260 | CONFIG_TCP_CONG_CUBIC=y |
| 235 | CONFIG_DEFAULT_TCP_CONG="cubic" | 261 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 236 | # CONFIG_TCP_MD5SIG is not set | 262 | # CONFIG_TCP_MD5SIG is not set |
| 237 | # CONFIG_IP_VS is not set | ||
| 238 | CONFIG_IPV6=m | 263 | CONFIG_IPV6=m |
| 239 | # CONFIG_IPV6_PRIVACY is not set | 264 | # CONFIG_IPV6_PRIVACY is not set |
| 240 | # CONFIG_IPV6_ROUTER_PREF is not set | 265 | # CONFIG_IPV6_ROUTER_PREF is not set |
| @@ -250,66 +275,72 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=m | |||
| 250 | CONFIG_INET6_XFRM_MODE_BEET=m | 275 | CONFIG_INET6_XFRM_MODE_BEET=m |
| 251 | # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set | 276 | # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set |
| 252 | CONFIG_IPV6_SIT=m | 277 | CONFIG_IPV6_SIT=m |
| 278 | CONFIG_IPV6_NDISC_NODETYPE=y | ||
| 253 | CONFIG_IPV6_TUNNEL=m | 279 | CONFIG_IPV6_TUNNEL=m |
| 254 | # CONFIG_IPV6_MULTIPLE_TABLES is not set | 280 | # CONFIG_IPV6_MULTIPLE_TABLES is not set |
| 281 | # CONFIG_IPV6_MROUTE is not set | ||
| 255 | # CONFIG_NETWORK_SECMARK is not set | 282 | # CONFIG_NETWORK_SECMARK is not set |
| 256 | CONFIG_NETFILTER=y | 283 | CONFIG_NETFILTER=y |
| 257 | # CONFIG_NETFILTER_DEBUG is not set | 284 | # CONFIG_NETFILTER_DEBUG is not set |
| 285 | CONFIG_NETFILTER_ADVANCED=y | ||
| 258 | 286 | ||
| 259 | # | 287 | # |
| 260 | # Core Netfilter Configuration | 288 | # Core Netfilter Configuration |
| 261 | # | 289 | # |
| 262 | # CONFIG_NETFILTER_NETLINK is not set | 290 | # CONFIG_NETFILTER_NETLINK_QUEUE is not set |
| 263 | # CONFIG_NF_CONNTRACK_ENABLED is not set | 291 | # CONFIG_NETFILTER_NETLINK_LOG is not set |
| 264 | # CONFIG_NF_CONNTRACK is not set | 292 | # CONFIG_NF_CONNTRACK is not set |
| 265 | CONFIG_NETFILTER_XTABLES=m | 293 | CONFIG_NETFILTER_XTABLES=m |
| 266 | # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set | 294 | # CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set |
| 267 | # CONFIG_NETFILTER_XT_TARGET_DSCP is not set | 295 | # CONFIG_NETFILTER_XT_TARGET_DSCP is not set |
| 268 | # CONFIG_NETFILTER_XT_TARGET_MARK is not set | 296 | # CONFIG_NETFILTER_XT_TARGET_MARK is not set |
| 269 | # CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set | ||
| 270 | # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set | 297 | # CONFIG_NETFILTER_XT_TARGET_NFLOG is not set |
| 298 | # CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set | ||
| 299 | # CONFIG_NETFILTER_XT_TARGET_RATEEST is not set | ||
| 271 | # CONFIG_NETFILTER_XT_TARGET_TRACE is not set | 300 | # CONFIG_NETFILTER_XT_TARGET_TRACE is not set |
| 272 | # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set | 301 | # CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set |
| 302 | # CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set | ||
| 273 | # CONFIG_NETFILTER_XT_MATCH_COMMENT is not set | 303 | # CONFIG_NETFILTER_XT_MATCH_COMMENT is not set |
| 274 | # CONFIG_NETFILTER_XT_MATCH_DCCP is not set | 304 | # CONFIG_NETFILTER_XT_MATCH_DCCP is not set |
| 275 | # CONFIG_NETFILTER_XT_MATCH_DSCP is not set | 305 | # CONFIG_NETFILTER_XT_MATCH_DSCP is not set |
| 276 | # CONFIG_NETFILTER_XT_MATCH_ESP is not set | 306 | # CONFIG_NETFILTER_XT_MATCH_ESP is not set |
| 307 | # CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set | ||
| 308 | # CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set | ||
| 277 | # CONFIG_NETFILTER_XT_MATCH_LENGTH is not set | 309 | # CONFIG_NETFILTER_XT_MATCH_LENGTH is not set |
| 278 | # CONFIG_NETFILTER_XT_MATCH_LIMIT is not set | 310 | # CONFIG_NETFILTER_XT_MATCH_LIMIT is not set |
| 279 | # CONFIG_NETFILTER_XT_MATCH_MAC is not set | 311 | # CONFIG_NETFILTER_XT_MATCH_MAC is not set |
| 280 | # CONFIG_NETFILTER_XT_MATCH_MARK is not set | 312 | # CONFIG_NETFILTER_XT_MATCH_MARK is not set |
| 281 | # CONFIG_NETFILTER_XT_MATCH_POLICY is not set | ||
| 282 | # CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set | 313 | # CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set |
| 314 | # CONFIG_NETFILTER_XT_MATCH_OWNER is not set | ||
| 315 | # CONFIG_NETFILTER_XT_MATCH_POLICY is not set | ||
| 283 | # CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set | 316 | # CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set |
| 284 | # CONFIG_NETFILTER_XT_MATCH_QUOTA is not set | 317 | # CONFIG_NETFILTER_XT_MATCH_QUOTA is not set |
| 318 | # CONFIG_NETFILTER_XT_MATCH_RATEEST is not set | ||
| 285 | # CONFIG_NETFILTER_XT_MATCH_REALM is not set | 319 | # CONFIG_NETFILTER_XT_MATCH_REALM is not set |
| 320 | # CONFIG_NETFILTER_XT_MATCH_RECENT is not set | ||
| 286 | # CONFIG_NETFILTER_XT_MATCH_SCTP is not set | 321 | # CONFIG_NETFILTER_XT_MATCH_SCTP is not set |
| 287 | # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set | 322 | # CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set |
| 288 | # CONFIG_NETFILTER_XT_MATCH_STRING is not set | 323 | # CONFIG_NETFILTER_XT_MATCH_STRING is not set |
| 289 | # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set | 324 | # CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set |
| 290 | # CONFIG_NETFILTER_XT_MATCH_TIME is not set | 325 | # CONFIG_NETFILTER_XT_MATCH_TIME is not set |
| 291 | # CONFIG_NETFILTER_XT_MATCH_U32 is not set | 326 | # CONFIG_NETFILTER_XT_MATCH_U32 is not set |
| 292 | # CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set | 327 | # CONFIG_IP_VS is not set |
| 293 | 328 | ||
| 294 | # | 329 | # |
| 295 | # IP: Netfilter Configuration | 330 | # IP: Netfilter Configuration |
| 296 | # | 331 | # |
| 332 | # CONFIG_NF_DEFRAG_IPV4 is not set | ||
| 297 | CONFIG_IP_NF_QUEUE=m | 333 | CONFIG_IP_NF_QUEUE=m |
| 298 | CONFIG_IP_NF_IPTABLES=m | 334 | CONFIG_IP_NF_IPTABLES=m |
| 299 | CONFIG_IP_NF_MATCH_IPRANGE=m | 335 | # CONFIG_IP_NF_MATCH_ADDRTYPE is not set |
| 300 | CONFIG_IP_NF_MATCH_TOS=m | ||
| 301 | CONFIG_IP_NF_MATCH_RECENT=m | ||
| 302 | CONFIG_IP_NF_MATCH_ECN=m | ||
| 303 | # CONFIG_IP_NF_MATCH_AH is not set | 336 | # CONFIG_IP_NF_MATCH_AH is not set |
| 337 | CONFIG_IP_NF_MATCH_ECN=m | ||
| 304 | CONFIG_IP_NF_MATCH_TTL=m | 338 | CONFIG_IP_NF_MATCH_TTL=m |
| 305 | CONFIG_IP_NF_MATCH_OWNER=m | ||
| 306 | # CONFIG_IP_NF_MATCH_ADDRTYPE is not set | ||
| 307 | CONFIG_IP_NF_FILTER=m | 339 | CONFIG_IP_NF_FILTER=m |
| 308 | CONFIG_IP_NF_TARGET_REJECT=m | 340 | CONFIG_IP_NF_TARGET_REJECT=m |
| 309 | CONFIG_IP_NF_TARGET_LOG=m | 341 | CONFIG_IP_NF_TARGET_LOG=m |
| 310 | CONFIG_IP_NF_TARGET_ULOG=m | 342 | CONFIG_IP_NF_TARGET_ULOG=m |
| 311 | CONFIG_IP_NF_MANGLE=m | 343 | CONFIG_IP_NF_MANGLE=m |
| 312 | CONFIG_IP_NF_TARGET_TOS=m | ||
| 313 | CONFIG_IP_NF_TARGET_ECN=m | 344 | CONFIG_IP_NF_TARGET_ECN=m |
| 314 | # CONFIG_IP_NF_TARGET_TTL is not set | 345 | # CONFIG_IP_NF_TARGET_TTL is not set |
| 315 | CONFIG_IP_NF_RAW=m | 346 | CONFIG_IP_NF_RAW=m |
| @@ -318,33 +349,30 @@ CONFIG_IP_NF_ARPFILTER=m | |||
| 318 | CONFIG_IP_NF_ARP_MANGLE=m | 349 | CONFIG_IP_NF_ARP_MANGLE=m |
| 319 | 350 | ||
| 320 | # | 351 | # |
| 321 | # IPv6: Netfilter Configuration (EXPERIMENTAL) | 352 | # IPv6: Netfilter Configuration |
| 322 | # | 353 | # |
| 323 | # CONFIG_IP6_NF_QUEUE is not set | 354 | # CONFIG_IP6_NF_QUEUE is not set |
| 324 | CONFIG_IP6_NF_IPTABLES=m | 355 | CONFIG_IP6_NF_IPTABLES=m |
| 325 | CONFIG_IP6_NF_MATCH_RT=m | 356 | # CONFIG_IP6_NF_MATCH_AH is not set |
| 326 | CONFIG_IP6_NF_MATCH_OPTS=m | 357 | # CONFIG_IP6_NF_MATCH_EUI64 is not set |
| 327 | CONFIG_IP6_NF_MATCH_FRAG=m | 358 | CONFIG_IP6_NF_MATCH_FRAG=m |
| 359 | CONFIG_IP6_NF_MATCH_OPTS=m | ||
| 328 | CONFIG_IP6_NF_MATCH_HL=m | 360 | CONFIG_IP6_NF_MATCH_HL=m |
| 329 | # CONFIG_IP6_NF_MATCH_OWNER is not set | ||
| 330 | CONFIG_IP6_NF_MATCH_IPV6HEADER=m | 361 | CONFIG_IP6_NF_MATCH_IPV6HEADER=m |
| 331 | # CONFIG_IP6_NF_MATCH_AH is not set | ||
| 332 | # CONFIG_IP6_NF_MATCH_MH is not set | 362 | # CONFIG_IP6_NF_MATCH_MH is not set |
| 333 | # CONFIG_IP6_NF_MATCH_EUI64 is not set | 363 | CONFIG_IP6_NF_MATCH_RT=m |
| 334 | CONFIG_IP6_NF_FILTER=m | ||
| 335 | CONFIG_IP6_NF_TARGET_LOG=m | 364 | CONFIG_IP6_NF_TARGET_LOG=m |
| 365 | CONFIG_IP6_NF_FILTER=m | ||
| 336 | CONFIG_IP6_NF_TARGET_REJECT=m | 366 | CONFIG_IP6_NF_TARGET_REJECT=m |
| 337 | CONFIG_IP6_NF_MANGLE=m | 367 | CONFIG_IP6_NF_MANGLE=m |
| 338 | # CONFIG_IP6_NF_TARGET_HL is not set | 368 | # CONFIG_IP6_NF_TARGET_HL is not set |
| 339 | CONFIG_IP6_NF_RAW=m | 369 | CONFIG_IP6_NF_RAW=m |
| 340 | CONFIG_IP_DCCP=m | 370 | CONFIG_IP_DCCP=m |
| 341 | CONFIG_INET_DCCP_DIAG=m | 371 | CONFIG_INET_DCCP_DIAG=m |
| 342 | CONFIG_IP_DCCP_ACKVEC=y | ||
| 343 | 372 | ||
| 344 | # | 373 | # |
| 345 | # DCCP CCIDs Configuration (EXPERIMENTAL) | 374 | # DCCP CCIDs Configuration (EXPERIMENTAL) |
| 346 | # | 375 | # |
| 347 | CONFIG_IP_DCCP_CCID2=m | ||
| 348 | # CONFIG_IP_DCCP_CCID2_DEBUG is not set | 376 | # CONFIG_IP_DCCP_CCID2_DEBUG is not set |
| 349 | # CONFIG_IP_DCCP_CCID3 is not set | 377 | # CONFIG_IP_DCCP_CCID3 is not set |
| 350 | 378 | ||
| @@ -356,6 +384,7 @@ CONFIG_IP_DCCP_CCID2=m | |||
| 356 | # CONFIG_TIPC is not set | 384 | # CONFIG_TIPC is not set |
| 357 | # CONFIG_ATM is not set | 385 | # CONFIG_ATM is not set |
| 358 | # CONFIG_BRIDGE is not set | 386 | # CONFIG_BRIDGE is not set |
| 387 | # CONFIG_NET_DSA is not set | ||
| 359 | # CONFIG_VLAN_8021Q is not set | 388 | # CONFIG_VLAN_8021Q is not set |
| 360 | # CONFIG_DECNET is not set | 389 | # CONFIG_DECNET is not set |
| 361 | CONFIG_LLC=m | 390 | CONFIG_LLC=m |
| @@ -366,28 +395,26 @@ CONFIG_LLC2=m | |||
| 366 | # CONFIG_LAPB is not set | 395 | # CONFIG_LAPB is not set |
| 367 | # CONFIG_ECONET is not set | 396 | # CONFIG_ECONET is not set |
| 368 | # CONFIG_WAN_ROUTER is not set | 397 | # CONFIG_WAN_ROUTER is not set |
| 369 | |||
| 370 | # | ||
| 371 | # QoS and/or fair queueing | ||
| 372 | # | ||
| 373 | # CONFIG_NET_SCHED is not set | 398 | # CONFIG_NET_SCHED is not set |
| 399 | # CONFIG_DCB is not set | ||
| 374 | 400 | ||
| 375 | # | 401 | # |
| 376 | # Network testing | 402 | # Network testing |
| 377 | # | 403 | # |
| 378 | CONFIG_NET_PKTGEN=m | 404 | CONFIG_NET_PKTGEN=m |
| 379 | # CONFIG_HAMRADIO is not set | 405 | # CONFIG_HAMRADIO is not set |
| 406 | # CONFIG_CAN is not set | ||
| 380 | # CONFIG_IRDA is not set | 407 | # CONFIG_IRDA is not set |
| 381 | # CONFIG_BT is not set | 408 | # CONFIG_BT is not set |
| 382 | # CONFIG_AF_RXRPC is not set | 409 | # CONFIG_AF_RXRPC is not set |
| 383 | 410 | # CONFIG_PHONET is not set | |
| 384 | # | 411 | CONFIG_WIRELESS=y |
| 385 | # Wireless | ||
| 386 | # | ||
| 387 | # CONFIG_CFG80211 is not set | 412 | # CONFIG_CFG80211 is not set |
| 413 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 388 | # CONFIG_WIRELESS_EXT is not set | 414 | # CONFIG_WIRELESS_EXT is not set |
| 415 | # CONFIG_LIB80211 is not set | ||
| 389 | # CONFIG_MAC80211 is not set | 416 | # CONFIG_MAC80211 is not set |
| 390 | # CONFIG_IEEE80211 is not set | 417 | # CONFIG_WIMAX is not set |
| 391 | # CONFIG_RFKILL is not set | 418 | # CONFIG_RFKILL is not set |
| 392 | # CONFIG_NET_9P is not set | 419 | # CONFIG_NET_9P is not set |
| 393 | 420 | ||
| @@ -402,6 +429,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |||
| 402 | # CONFIG_STANDALONE is not set | 429 | # CONFIG_STANDALONE is not set |
| 403 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | 430 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set |
| 404 | CONFIG_FW_LOADER=y | 431 | CONFIG_FW_LOADER=y |
| 432 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 433 | CONFIG_EXTRA_FIRMWARE="" | ||
| 405 | # CONFIG_DEBUG_DRIVER is not set | 434 | # CONFIG_DEBUG_DRIVER is not set |
| 406 | # CONFIG_DEBUG_DEVRES is not set | 435 | # CONFIG_DEBUG_DEVRES is not set |
| 407 | # CONFIG_SYS_HYPERVISOR is not set | 436 | # CONFIG_SYS_HYPERVISOR is not set |
| @@ -421,14 +450,23 @@ CONFIG_BLK_DEV_LOOP=y | |||
| 421 | CONFIG_BLK_DEV_RAM=y | 450 | CONFIG_BLK_DEV_RAM=y |
| 422 | CONFIG_BLK_DEV_RAM_COUNT=16 | 451 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 423 | CONFIG_BLK_DEV_RAM_SIZE=6144 | 452 | CONFIG_BLK_DEV_RAM_SIZE=6144 |
| 424 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 453 | # CONFIG_BLK_DEV_XIP is not set |
| 425 | # CONFIG_CDROM_PKTCDVD is not set | 454 | # CONFIG_CDROM_PKTCDVD is not set |
| 426 | # CONFIG_ATA_OVER_ETH is not set | 455 | # CONFIG_ATA_OVER_ETH is not set |
| 456 | # CONFIG_BLK_DEV_HD is not set | ||
| 427 | CONFIG_MISC_DEVICES=y | 457 | CONFIG_MISC_DEVICES=y |
| 428 | # CONFIG_PHANTOM is not set | 458 | # CONFIG_PHANTOM is not set |
| 429 | # CONFIG_EEPROM_93CX6 is not set | ||
| 430 | # CONFIG_SGI_IOC4 is not set | 459 | # CONFIG_SGI_IOC4 is not set |
| 431 | # CONFIG_TIFM_CORE is not set | 460 | # CONFIG_TIFM_CORE is not set |
| 461 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 462 | # CONFIG_HP_ILO is not set | ||
| 463 | # CONFIG_C2PORT is not set | ||
| 464 | |||
| 465 | # | ||
| 466 | # EEPROM support | ||
| 467 | # | ||
| 468 | # CONFIG_EEPROM_93CX6 is not set | ||
| 469 | CONFIG_HAVE_IDE=y | ||
| 432 | # CONFIG_IDE is not set | 470 | # CONFIG_IDE is not set |
| 433 | 471 | ||
| 434 | # | 472 | # |
| @@ -468,8 +506,10 @@ CONFIG_SCSI_SPI_ATTRS=y | |||
| 468 | CONFIG_SCSI_FC_ATTRS=m | 506 | CONFIG_SCSI_FC_ATTRS=m |
| 469 | CONFIG_SCSI_ISCSI_ATTRS=m | 507 | CONFIG_SCSI_ISCSI_ATTRS=m |
| 470 | # CONFIG_SCSI_SAS_LIBSAS is not set | 508 | # CONFIG_SCSI_SAS_LIBSAS is not set |
| 509 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 471 | CONFIG_SCSI_LOWLEVEL=y | 510 | CONFIG_SCSI_LOWLEVEL=y |
| 472 | # CONFIG_ISCSI_TCP is not set | 511 | # CONFIG_ISCSI_TCP is not set |
| 512 | # CONFIG_SCSI_CXGB3_ISCSI is not set | ||
| 473 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set | 513 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set |
| 474 | # CONFIG_SCSI_3W_9XXX is not set | 514 | # CONFIG_SCSI_3W_9XXX is not set |
| 475 | # CONFIG_SCSI_ACARD is not set | 515 | # CONFIG_SCSI_ACARD is not set |
| @@ -478,16 +518,21 @@ CONFIG_SCSI_LOWLEVEL=y | |||
| 478 | # CONFIG_SCSI_AIC7XXX_OLD is not set | 518 | # CONFIG_SCSI_AIC7XXX_OLD is not set |
| 479 | # CONFIG_SCSI_AIC79XX is not set | 519 | # CONFIG_SCSI_AIC79XX is not set |
| 480 | # CONFIG_SCSI_AIC94XX is not set | 520 | # CONFIG_SCSI_AIC94XX is not set |
| 521 | # CONFIG_SCSI_DPT_I2O is not set | ||
| 522 | # CONFIG_SCSI_ADVANSYS is not set | ||
| 481 | # CONFIG_SCSI_ARCMSR is not set | 523 | # CONFIG_SCSI_ARCMSR is not set |
| 482 | # CONFIG_MEGARAID_NEWGEN is not set | 524 | # CONFIG_MEGARAID_NEWGEN is not set |
| 483 | # CONFIG_MEGARAID_LEGACY is not set | 525 | # CONFIG_MEGARAID_LEGACY is not set |
| 484 | # CONFIG_MEGARAID_SAS is not set | 526 | # CONFIG_MEGARAID_SAS is not set |
| 485 | # CONFIG_SCSI_HPTIOP is not set | 527 | # CONFIG_SCSI_HPTIOP is not set |
| 528 | # CONFIG_LIBFC is not set | ||
| 529 | # CONFIG_FCOE is not set | ||
| 486 | # CONFIG_SCSI_DMX3191D is not set | 530 | # CONFIG_SCSI_DMX3191D is not set |
| 487 | # CONFIG_SCSI_FUTURE_DOMAIN is not set | 531 | # CONFIG_SCSI_FUTURE_DOMAIN is not set |
| 488 | # CONFIG_SCSI_IPS is not set | 532 | # CONFIG_SCSI_IPS is not set |
| 489 | # CONFIG_SCSI_INITIO is not set | 533 | # CONFIG_SCSI_INITIO is not set |
| 490 | # CONFIG_SCSI_INIA100 is not set | 534 | # CONFIG_SCSI_INIA100 is not set |
| 535 | # CONFIG_SCSI_MVSAS is not set | ||
| 491 | # CONFIG_SCSI_STEX is not set | 536 | # CONFIG_SCSI_STEX is not set |
| 492 | CONFIG_SCSI_SYM53C8XX_2=y | 537 | CONFIG_SCSI_SYM53C8XX_2=y |
| 493 | CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 | 538 | CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 |
| @@ -503,9 +548,11 @@ CONFIG_SCSI_QLOGIC_1280=m | |||
| 503 | CONFIG_SCSI_DEBUG=m | 548 | CONFIG_SCSI_DEBUG=m |
| 504 | # CONFIG_SCSI_SRP is not set | 549 | # CONFIG_SCSI_SRP is not set |
| 505 | # CONFIG_SCSI_LOWLEVEL_PCMCIA is not set | 550 | # CONFIG_SCSI_LOWLEVEL_PCMCIA is not set |
| 551 | # CONFIG_SCSI_DH is not set | ||
| 506 | # CONFIG_ATA is not set | 552 | # CONFIG_ATA is not set |
| 507 | CONFIG_MD=y | 553 | CONFIG_MD=y |
| 508 | CONFIG_BLK_DEV_MD=y | 554 | CONFIG_BLK_DEV_MD=y |
| 555 | CONFIG_MD_AUTODETECT=y | ||
| 509 | CONFIG_MD_LINEAR=y | 556 | CONFIG_MD_LINEAR=y |
| 510 | CONFIG_MD_RAID0=y | 557 | CONFIG_MD_RAID0=y |
| 511 | CONFIG_MD_RAID1=y | 558 | CONFIG_MD_RAID1=y |
| @@ -514,10 +561,6 @@ CONFIG_MD_RAID1=y | |||
| 514 | # CONFIG_MD_MULTIPATH is not set | 561 | # CONFIG_MD_MULTIPATH is not set |
| 515 | # CONFIG_MD_FAULTY is not set | 562 | # CONFIG_MD_FAULTY is not set |
| 516 | # CONFIG_BLK_DEV_DM is not set | 563 | # CONFIG_BLK_DEV_DM is not set |
| 517 | |||
| 518 | # | ||
| 519 | # Fusion MPT device support | ||
| 520 | # | ||
| 521 | CONFIG_FUSION=y | 564 | CONFIG_FUSION=y |
| 522 | CONFIG_FUSION_SPI=m | 565 | CONFIG_FUSION_SPI=m |
| 523 | CONFIG_FUSION_FC=m | 566 | CONFIG_FUSION_FC=m |
| @@ -529,20 +572,40 @@ CONFIG_FUSION_CTL=m | |||
| 529 | # | 572 | # |
| 530 | # IEEE 1394 (FireWire) support | 573 | # IEEE 1394 (FireWire) support |
| 531 | # | 574 | # |
| 575 | |||
| 576 | # | ||
| 577 | # Enable only one of the two stacks, unless you know what you are doing | ||
| 578 | # | ||
| 532 | # CONFIG_FIREWIRE is not set | 579 | # CONFIG_FIREWIRE is not set |
| 533 | # CONFIG_IEEE1394 is not set | 580 | # CONFIG_IEEE1394 is not set |
| 534 | # CONFIG_I2O is not set | 581 | # CONFIG_I2O is not set |
| 535 | CONFIG_NETDEVICES=y | 582 | CONFIG_NETDEVICES=y |
| 536 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 537 | CONFIG_DUMMY=m | 583 | CONFIG_DUMMY=m |
| 538 | CONFIG_BONDING=m | 584 | CONFIG_BONDING=m |
| 539 | # CONFIG_MACVLAN is not set | 585 | # CONFIG_MACVLAN is not set |
| 540 | # CONFIG_EQUALIZER is not set | 586 | # CONFIG_EQUALIZER is not set |
| 541 | CONFIG_TUN=m | 587 | CONFIG_TUN=m |
| 542 | # CONFIG_VETH is not set | 588 | # CONFIG_VETH is not set |
| 543 | # CONFIG_IP1000 is not set | ||
| 544 | # CONFIG_ARCNET is not set | 589 | # CONFIG_ARCNET is not set |
| 545 | # CONFIG_PHYLIB is not set | 590 | CONFIG_PHYLIB=m |
| 591 | |||
| 592 | # | ||
| 593 | # MII PHY device drivers | ||
| 594 | # | ||
| 595 | # CONFIG_MARVELL_PHY is not set | ||
| 596 | # CONFIG_DAVICOM_PHY is not set | ||
| 597 | # CONFIG_QSEMI_PHY is not set | ||
| 598 | # CONFIG_LXT_PHY is not set | ||
| 599 | # CONFIG_CICADA_PHY is not set | ||
| 600 | # CONFIG_VITESSE_PHY is not set | ||
| 601 | # CONFIG_SMSC_PHY is not set | ||
| 602 | # CONFIG_BROADCOM_PHY is not set | ||
| 603 | # CONFIG_ICPLUS_PHY is not set | ||
| 604 | # CONFIG_REALTEK_PHY is not set | ||
| 605 | # CONFIG_NATIONAL_PHY is not set | ||
| 606 | # CONFIG_STE10XP is not set | ||
| 607 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 608 | # CONFIG_MDIO_BITBANG is not set | ||
| 546 | CONFIG_NET_ETHERNET=y | 609 | CONFIG_NET_ETHERNET=y |
| 547 | CONFIG_MII=m | 610 | CONFIG_MII=m |
| 548 | # CONFIG_HAPPYMEAL is not set | 611 | # CONFIG_HAPPYMEAL is not set |
| @@ -567,33 +630,38 @@ CONFIG_HP100=m | |||
| 567 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 630 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 568 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 631 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 569 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 632 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 633 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 634 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 635 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 570 | CONFIG_NET_PCI=y | 636 | CONFIG_NET_PCI=y |
| 571 | CONFIG_PCNET32=m | 637 | CONFIG_PCNET32=m |
| 572 | # CONFIG_PCNET32_NAPI is not set | ||
| 573 | # CONFIG_AMD8111_ETH is not set | 638 | # CONFIG_AMD8111_ETH is not set |
| 574 | # CONFIG_ADAPTEC_STARFIRE is not set | 639 | # CONFIG_ADAPTEC_STARFIRE is not set |
| 575 | # CONFIG_B44 is not set | 640 | # CONFIG_B44 is not set |
| 576 | # CONFIG_FORCEDETH is not set | 641 | # CONFIG_FORCEDETH is not set |
| 577 | # CONFIG_EEPRO100 is not set | ||
| 578 | CONFIG_E100=m | 642 | CONFIG_E100=m |
| 579 | # CONFIG_FEALNX is not set | 643 | # CONFIG_FEALNX is not set |
| 580 | # CONFIG_NATSEMI is not set | 644 | # CONFIG_NATSEMI is not set |
| 581 | # CONFIG_NE2K_PCI is not set | 645 | # CONFIG_NE2K_PCI is not set |
| 582 | # CONFIG_8139CP is not set | 646 | # CONFIG_8139CP is not set |
| 583 | # CONFIG_8139TOO is not set | 647 | # CONFIG_8139TOO is not set |
| 648 | # CONFIG_R6040 is not set | ||
| 584 | # CONFIG_SIS900 is not set | 649 | # CONFIG_SIS900 is not set |
| 585 | # CONFIG_EPIC100 is not set | 650 | # CONFIG_EPIC100 is not set |
| 651 | # CONFIG_SMSC9420 is not set | ||
| 586 | # CONFIG_SUNDANCE is not set | 652 | # CONFIG_SUNDANCE is not set |
| 653 | # CONFIG_TLAN is not set | ||
| 587 | # CONFIG_VIA_RHINE is not set | 654 | # CONFIG_VIA_RHINE is not set |
| 588 | # CONFIG_SC92031 is not set | 655 | # CONFIG_SC92031 is not set |
| 656 | # CONFIG_ATL2 is not set | ||
| 589 | CONFIG_NETDEV_1000=y | 657 | CONFIG_NETDEV_1000=y |
| 590 | CONFIG_ACENIC=m | 658 | CONFIG_ACENIC=m |
| 591 | CONFIG_ACENIC_OMIT_TIGON_I=y | 659 | CONFIG_ACENIC_OMIT_TIGON_I=y |
| 592 | # CONFIG_DL2K is not set | 660 | # CONFIG_DL2K is not set |
| 593 | CONFIG_E1000=m | 661 | CONFIG_E1000=m |
| 594 | CONFIG_E1000_NAPI=y | ||
| 595 | # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set | ||
| 596 | # CONFIG_E1000E is not set | 662 | # CONFIG_E1000E is not set |
| 663 | # CONFIG_IP1000 is not set | ||
| 664 | # CONFIG_IGB is not set | ||
| 597 | # CONFIG_NS83820 is not set | 665 | # CONFIG_NS83820 is not set |
| 598 | # CONFIG_HAMACHI is not set | 666 | # CONFIG_HAMACHI is not set |
| 599 | # CONFIG_YELLOWFIN is not set | 667 | # CONFIG_YELLOWFIN is not set |
| @@ -601,23 +669,31 @@ CONFIG_E1000_NAPI=y | |||
| 601 | # CONFIG_SIS190 is not set | 669 | # CONFIG_SIS190 is not set |
| 602 | # CONFIG_SKGE is not set | 670 | # CONFIG_SKGE is not set |
| 603 | # CONFIG_SKY2 is not set | 671 | # CONFIG_SKY2 is not set |
| 604 | # CONFIG_SK98LIN is not set | ||
| 605 | # CONFIG_VIA_VELOCITY is not set | 672 | # CONFIG_VIA_VELOCITY is not set |
| 606 | CONFIG_TIGON3=m | 673 | CONFIG_TIGON3=m |
| 607 | # CONFIG_BNX2 is not set | 674 | # CONFIG_BNX2 is not set |
| 608 | # CONFIG_QLA3XXX is not set | 675 | # CONFIG_QLA3XXX is not set |
| 609 | # CONFIG_ATL1 is not set | 676 | # CONFIG_ATL1 is not set |
| 677 | # CONFIG_ATL1E is not set | ||
| 678 | # CONFIG_ATL1C is not set | ||
| 679 | # CONFIG_JME is not set | ||
| 610 | CONFIG_NETDEV_10000=y | 680 | CONFIG_NETDEV_10000=y |
| 611 | # CONFIG_CHELSIO_T1 is not set | 681 | # CONFIG_CHELSIO_T1 is not set |
| 682 | CONFIG_CHELSIO_T3_DEPENDS=y | ||
| 612 | # CONFIG_CHELSIO_T3 is not set | 683 | # CONFIG_CHELSIO_T3 is not set |
| 684 | # CONFIG_ENIC is not set | ||
| 613 | # CONFIG_IXGBE is not set | 685 | # CONFIG_IXGBE is not set |
| 614 | # CONFIG_IXGB is not set | 686 | # CONFIG_IXGB is not set |
| 615 | # CONFIG_S2IO is not set | 687 | # CONFIG_S2IO is not set |
| 616 | # CONFIG_MYRI10GE is not set | 688 | # CONFIG_MYRI10GE is not set |
| 617 | # CONFIG_NETXEN_NIC is not set | 689 | # CONFIG_NETXEN_NIC is not set |
| 618 | # CONFIG_NIU is not set | 690 | # CONFIG_NIU is not set |
| 691 | # CONFIG_MLX4_EN is not set | ||
| 619 | # CONFIG_MLX4_CORE is not set | 692 | # CONFIG_MLX4_CORE is not set |
| 620 | # CONFIG_TEHUTI is not set | 693 | # CONFIG_TEHUTI is not set |
| 694 | # CONFIG_BNX2X is not set | ||
| 695 | # CONFIG_QLGE is not set | ||
| 696 | # CONFIG_SFC is not set | ||
| 621 | # CONFIG_TR is not set | 697 | # CONFIG_TR is not set |
| 622 | 698 | ||
| 623 | # | 699 | # |
| @@ -625,6 +701,11 @@ CONFIG_NETDEV_10000=y | |||
| 625 | # | 701 | # |
| 626 | # CONFIG_WLAN_PRE80211 is not set | 702 | # CONFIG_WLAN_PRE80211 is not set |
| 627 | # CONFIG_WLAN_80211 is not set | 703 | # CONFIG_WLAN_80211 is not set |
| 704 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 705 | |||
| 706 | # | ||
| 707 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 708 | # | ||
| 628 | CONFIG_NET_PCMCIA=y | 709 | CONFIG_NET_PCMCIA=y |
| 629 | CONFIG_PCMCIA_3C589=m | 710 | CONFIG_PCMCIA_3C589=m |
| 630 | CONFIG_PCMCIA_3C574=m | 711 | CONFIG_PCMCIA_3C574=m |
| @@ -650,7 +731,6 @@ CONFIG_PPP_BSDCOMP=m | |||
| 650 | # CONFIG_SLIP is not set | 731 | # CONFIG_SLIP is not set |
| 651 | CONFIG_SLHC=m | 732 | CONFIG_SLHC=m |
| 652 | # CONFIG_NET_FC is not set | 733 | # CONFIG_NET_FC is not set |
| 653 | # CONFIG_SHAPER is not set | ||
| 654 | # CONFIG_NETCONSOLE is not set | 734 | # CONFIG_NETCONSOLE is not set |
| 655 | # CONFIG_NETPOLL is not set | 735 | # CONFIG_NETPOLL is not set |
| 656 | # CONFIG_NET_POLL_CONTROLLER is not set | 736 | # CONFIG_NET_POLL_CONTROLLER is not set |
| @@ -669,7 +749,6 @@ CONFIG_INPUT=y | |||
| 669 | # | 749 | # |
| 670 | # CONFIG_INPUT_MOUSEDEV is not set | 750 | # CONFIG_INPUT_MOUSEDEV is not set |
| 671 | # CONFIG_INPUT_JOYDEV is not set | 751 | # CONFIG_INPUT_JOYDEV is not set |
| 672 | # CONFIG_INPUT_TSDEV is not set | ||
| 673 | # CONFIG_INPUT_EVDEV is not set | 752 | # CONFIG_INPUT_EVDEV is not set |
| 674 | # CONFIG_INPUT_EVBUG is not set | 753 | # CONFIG_INPUT_EVBUG is not set |
| 675 | 754 | ||
| @@ -693,10 +772,13 @@ CONFIG_INPUT=y | |||
| 693 | # Character devices | 772 | # Character devices |
| 694 | # | 773 | # |
| 695 | CONFIG_VT=y | 774 | CONFIG_VT=y |
| 775 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 696 | CONFIG_VT_CONSOLE=y | 776 | CONFIG_VT_CONSOLE=y |
| 697 | CONFIG_HW_CONSOLE=y | 777 | CONFIG_HW_CONSOLE=y |
| 698 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | 778 | # CONFIG_VT_HW_CONSOLE_BINDING is not set |
| 779 | CONFIG_DEVKMEM=y | ||
| 699 | # CONFIG_SERIAL_NONSTANDARD is not set | 780 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 781 | # CONFIG_NOZOMI is not set | ||
| 700 | 782 | ||
| 701 | # | 783 | # |
| 702 | # Serial drivers | 784 | # Serial drivers |
| @@ -721,17 +803,12 @@ CONFIG_SERIAL_CORE=y | |||
| 721 | CONFIG_SERIAL_CORE_CONSOLE=y | 803 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 722 | # CONFIG_SERIAL_JSM is not set | 804 | # CONFIG_SERIAL_JSM is not set |
| 723 | CONFIG_UNIX98_PTYS=y | 805 | CONFIG_UNIX98_PTYS=y |
| 806 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 724 | # CONFIG_LEGACY_PTYS is not set | 807 | # CONFIG_LEGACY_PTYS is not set |
| 725 | # CONFIG_IPMI_HANDLER is not set | 808 | # CONFIG_IPMI_HANDLER is not set |
| 726 | # CONFIG_WATCHDOG is not set | ||
| 727 | # CONFIG_HW_RANDOM is not set | 809 | # CONFIG_HW_RANDOM is not set |
| 728 | CONFIG_GEN_RTC=y | ||
| 729 | CONFIG_GEN_RTC_X=y | ||
| 730 | # CONFIG_R3964 is not set | 810 | # CONFIG_R3964 is not set |
| 731 | # CONFIG_APPLICOM is not set | 811 | # CONFIG_APPLICOM is not set |
| 732 | CONFIG_AGP=y | ||
| 733 | CONFIG_AGP_PARISC=y | ||
| 734 | # CONFIG_DRM is not set | ||
| 735 | 812 | ||
| 736 | # | 813 | # |
| 737 | # PCMCIA character devices | 814 | # PCMCIA character devices |
| @@ -739,51 +816,66 @@ CONFIG_AGP_PARISC=y | |||
| 739 | # CONFIG_SYNCLINK_CS is not set | 816 | # CONFIG_SYNCLINK_CS is not set |
| 740 | # CONFIG_CARDMAN_4000 is not set | 817 | # CONFIG_CARDMAN_4000 is not set |
| 741 | # CONFIG_CARDMAN_4040 is not set | 818 | # CONFIG_CARDMAN_4040 is not set |
| 819 | # CONFIG_IPWIRELESS is not set | ||
| 742 | CONFIG_RAW_DRIVER=y | 820 | CONFIG_RAW_DRIVER=y |
| 743 | CONFIG_MAX_RAW_DEVS=256 | 821 | CONFIG_MAX_RAW_DEVS=256 |
| 744 | # CONFIG_TCG_TPM is not set | 822 | # CONFIG_TCG_TPM is not set |
| 745 | CONFIG_DEVPORT=y | 823 | CONFIG_DEVPORT=y |
| 746 | # CONFIG_I2C is not set | 824 | # CONFIG_I2C is not set |
| 747 | |||
| 748 | # | ||
| 749 | # SPI support | ||
| 750 | # | ||
| 751 | # CONFIG_SPI is not set | 825 | # CONFIG_SPI is not set |
| 752 | # CONFIG_SPI_MASTER is not set | ||
| 753 | # CONFIG_W1 is not set | 826 | # CONFIG_W1 is not set |
| 754 | # CONFIG_POWER_SUPPLY is not set | 827 | # CONFIG_POWER_SUPPLY is not set |
| 755 | # CONFIG_HWMON is not set | 828 | # CONFIG_HWMON is not set |
| 829 | # CONFIG_THERMAL is not set | ||
| 830 | # CONFIG_THERMAL_HWMON is not set | ||
| 831 | # CONFIG_WATCHDOG is not set | ||
| 832 | CONFIG_SSB_POSSIBLE=y | ||
| 756 | 833 | ||
| 757 | # | 834 | # |
| 758 | # Sonics Silicon Backplane | 835 | # Sonics Silicon Backplane |
| 759 | # | 836 | # |
| 760 | CONFIG_SSB_POSSIBLE=y | ||
| 761 | # CONFIG_SSB is not set | 837 | # CONFIG_SSB is not set |
| 762 | 838 | ||
| 763 | # | 839 | # |
| 764 | # Multifunction device drivers | 840 | # Multifunction device drivers |
| 765 | # | 841 | # |
| 842 | # CONFIG_MFD_CORE is not set | ||
| 766 | # CONFIG_MFD_SM501 is not set | 843 | # CONFIG_MFD_SM501 is not set |
| 844 | # CONFIG_HTC_PASIC3 is not set | ||
| 845 | # CONFIG_MFD_TMIO is not set | ||
| 846 | # CONFIG_REGULATOR is not set | ||
| 767 | 847 | ||
| 768 | # | 848 | # |
| 769 | # Multimedia devices | 849 | # Multimedia devices |
| 770 | # | 850 | # |
| 851 | |||
| 852 | # | ||
| 853 | # Multimedia core support | ||
| 854 | # | ||
| 771 | # CONFIG_VIDEO_DEV is not set | 855 | # CONFIG_VIDEO_DEV is not set |
| 772 | # CONFIG_DVB_CORE is not set | 856 | # CONFIG_DVB_CORE is not set |
| 857 | # CONFIG_VIDEO_MEDIA is not set | ||
| 858 | |||
| 859 | # | ||
| 860 | # Multimedia drivers | ||
| 861 | # | ||
| 773 | # CONFIG_DAB is not set | 862 | # CONFIG_DAB is not set |
| 774 | 863 | ||
| 775 | # | 864 | # |
| 776 | # Graphics support | 865 | # Graphics support |
| 777 | # | 866 | # |
| 867 | CONFIG_AGP=y | ||
| 868 | CONFIG_AGP_PARISC=y | ||
| 869 | # CONFIG_DRM is not set | ||
| 870 | # CONFIG_VGASTATE is not set | ||
| 871 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 872 | # CONFIG_FB is not set | ||
| 778 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 873 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set |
| 779 | 874 | ||
| 780 | # | 875 | # |
| 781 | # Display device support | 876 | # Display device support |
| 782 | # | 877 | # |
| 783 | # CONFIG_DISPLAY_SUPPORT is not set | 878 | # CONFIG_DISPLAY_SUPPORT is not set |
| 784 | # CONFIG_VGASTATE is not set | ||
| 785 | # CONFIG_VIDEO_OUTPUT_CONTROL is not set | ||
| 786 | # CONFIG_FB is not set | ||
| 787 | 879 | ||
| 788 | # | 880 | # |
| 789 | # Console display driver support | 881 | # Console display driver support |
| @@ -792,50 +884,83 @@ CONFIG_DUMMY_CONSOLE=y | |||
| 792 | CONFIG_DUMMY_CONSOLE_COLUMNS=160 | 884 | CONFIG_DUMMY_CONSOLE_COLUMNS=160 |
| 793 | CONFIG_DUMMY_CONSOLE_ROWS=64 | 885 | CONFIG_DUMMY_CONSOLE_ROWS=64 |
| 794 | # CONFIG_STI_CONSOLE is not set | 886 | # CONFIG_STI_CONSOLE is not set |
| 795 | |||
| 796 | # | ||
| 797 | # Sound | ||
| 798 | # | ||
| 799 | # CONFIG_SOUND is not set | 887 | # CONFIG_SOUND is not set |
| 800 | CONFIG_HID_SUPPORT=y | 888 | CONFIG_HID_SUPPORT=y |
| 801 | CONFIG_HID=y | 889 | CONFIG_HID=y |
| 802 | # CONFIG_HID_DEBUG is not set | 890 | # CONFIG_HID_DEBUG is not set |
| 891 | # CONFIG_HIDRAW is not set | ||
| 892 | # CONFIG_HID_PID is not set | ||
| 893 | |||
| 894 | # | ||
| 895 | # Special HID drivers | ||
| 896 | # | ||
| 897 | CONFIG_HID_COMPAT=y | ||
| 803 | CONFIG_USB_SUPPORT=y | 898 | CONFIG_USB_SUPPORT=y |
| 804 | CONFIG_USB_ARCH_HAS_HCD=y | 899 | CONFIG_USB_ARCH_HAS_HCD=y |
| 805 | CONFIG_USB_ARCH_HAS_OHCI=y | 900 | CONFIG_USB_ARCH_HAS_OHCI=y |
| 806 | CONFIG_USB_ARCH_HAS_EHCI=y | 901 | CONFIG_USB_ARCH_HAS_EHCI=y |
| 807 | # CONFIG_USB is not set | 902 | # CONFIG_USB is not set |
| 903 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 904 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
| 808 | 905 | ||
| 809 | # | 906 | # |
| 810 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 907 | # Enable Host or Gadget support to see Inventra options |
| 811 | # | 908 | # |
| 812 | 909 | ||
| 813 | # | 910 | # |
| 814 | # USB Gadget Support | 911 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; |
| 815 | # | 912 | # |
| 816 | # CONFIG_USB_GADGET is not set | 913 | # CONFIG_USB_GADGET is not set |
| 914 | |||
| 915 | # | ||
| 916 | # OTG and related infrastructure | ||
| 917 | # | ||
| 918 | # CONFIG_UWB is not set | ||
| 817 | # CONFIG_MMC is not set | 919 | # CONFIG_MMC is not set |
| 920 | # CONFIG_MEMSTICK is not set | ||
| 818 | # CONFIG_NEW_LEDS is not set | 921 | # CONFIG_NEW_LEDS is not set |
| 922 | # CONFIG_ACCESSIBILITY is not set | ||
| 819 | # CONFIG_INFINIBAND is not set | 923 | # CONFIG_INFINIBAND is not set |
| 820 | # CONFIG_RTC_CLASS is not set | 924 | CONFIG_RTC_LIB=y |
| 925 | CONFIG_RTC_CLASS=y | ||
| 926 | CONFIG_RTC_HCTOSYS=y | ||
| 927 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 928 | # CONFIG_RTC_DEBUG is not set | ||
| 821 | 929 | ||
| 822 | # | 930 | # |
| 823 | # DMA Engine support | 931 | # RTC interfaces |
| 824 | # | 932 | # |
| 825 | # CONFIG_DMA_ENGINE is not set | 933 | CONFIG_RTC_INTF_SYSFS=y |
| 934 | CONFIG_RTC_INTF_PROC=y | ||
| 935 | CONFIG_RTC_INTF_DEV=y | ||
| 936 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 937 | # CONFIG_RTC_DRV_TEST is not set | ||
| 826 | 938 | ||
| 827 | # | 939 | # |
| 828 | # DMA Clients | 940 | # SPI RTC drivers |
| 829 | # | 941 | # |
| 830 | 942 | ||
| 831 | # | 943 | # |
| 832 | # DMA Devices | 944 | # Platform RTC drivers |
| 833 | # | 945 | # |
| 946 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 947 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 948 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 949 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 950 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 951 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 952 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 953 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 954 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 955 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 834 | 956 | ||
| 835 | # | 957 | # |
| 836 | # Userspace I/O | 958 | # on-CPU RTC drivers |
| 837 | # | 959 | # |
| 960 | CONFIG_RTC_DRV_PARISC=y | ||
| 961 | # CONFIG_DMADEVICES is not set | ||
| 838 | # CONFIG_UIO is not set | 962 | # CONFIG_UIO is not set |
| 963 | # CONFIG_STAGING is not set | ||
| 839 | 964 | ||
| 840 | # | 965 | # |
| 841 | # File systems | 966 | # File systems |
| @@ -845,7 +970,7 @@ CONFIG_EXT2_FS=y | |||
| 845 | # CONFIG_EXT2_FS_XIP is not set | 970 | # CONFIG_EXT2_FS_XIP is not set |
| 846 | CONFIG_EXT3_FS=y | 971 | CONFIG_EXT3_FS=y |
| 847 | # CONFIG_EXT3_FS_XATTR is not set | 972 | # CONFIG_EXT3_FS_XATTR is not set |
| 848 | # CONFIG_EXT4DEV_FS is not set | 973 | # CONFIG_EXT4_FS is not set |
| 849 | CONFIG_JBD=y | 974 | CONFIG_JBD=y |
| 850 | # CONFIG_JBD_DEBUG is not set | 975 | # CONFIG_JBD_DEBUG is not set |
| 851 | # CONFIG_REISERFS_FS is not set | 976 | # CONFIG_REISERFS_FS is not set |
| @@ -855,19 +980,19 @@ CONFIG_JFS_FS=m | |||
| 855 | # CONFIG_JFS_DEBUG is not set | 980 | # CONFIG_JFS_DEBUG is not set |
| 856 | # CONFIG_JFS_STATISTICS is not set | 981 | # CONFIG_JFS_STATISTICS is not set |
| 857 | CONFIG_FS_POSIX_ACL=y | 982 | CONFIG_FS_POSIX_ACL=y |
| 983 | CONFIG_FILE_LOCKING=y | ||
| 858 | CONFIG_XFS_FS=m | 984 | CONFIG_XFS_FS=m |
| 859 | # CONFIG_XFS_QUOTA is not set | 985 | # CONFIG_XFS_QUOTA is not set |
| 860 | # CONFIG_XFS_SECURITY is not set | ||
| 861 | # CONFIG_XFS_POSIX_ACL is not set | 986 | # CONFIG_XFS_POSIX_ACL is not set |
| 862 | # CONFIG_XFS_RT is not set | 987 | # CONFIG_XFS_RT is not set |
| 988 | # CONFIG_XFS_DEBUG is not set | ||
| 863 | # CONFIG_GFS2_FS is not set | 989 | # CONFIG_GFS2_FS is not set |
| 864 | # CONFIG_OCFS2_FS is not set | 990 | # CONFIG_OCFS2_FS is not set |
| 865 | # CONFIG_MINIX_FS is not set | 991 | # CONFIG_BTRFS_FS is not set |
| 866 | # CONFIG_ROMFS_FS is not set | 992 | CONFIG_DNOTIFY=y |
| 867 | CONFIG_INOTIFY=y | 993 | CONFIG_INOTIFY=y |
| 868 | CONFIG_INOTIFY_USER=y | 994 | CONFIG_INOTIFY_USER=y |
| 869 | # CONFIG_QUOTA is not set | 995 | # CONFIG_QUOTA is not set |
| 870 | CONFIG_DNOTIFY=y | ||
| 871 | # CONFIG_AUTOFS_FS is not set | 996 | # CONFIG_AUTOFS_FS is not set |
| 872 | CONFIG_AUTOFS4_FS=y | 997 | CONFIG_AUTOFS4_FS=y |
| 873 | # CONFIG_FUSE_FS is not set | 998 | # CONFIG_FUSE_FS is not set |
| @@ -897,16 +1022,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | |||
| 897 | CONFIG_PROC_FS=y | 1022 | CONFIG_PROC_FS=y |
| 898 | CONFIG_PROC_KCORE=y | 1023 | CONFIG_PROC_KCORE=y |
| 899 | CONFIG_PROC_SYSCTL=y | 1024 | CONFIG_PROC_SYSCTL=y |
| 1025 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 900 | CONFIG_SYSFS=y | 1026 | CONFIG_SYSFS=y |
| 901 | CONFIG_TMPFS=y | 1027 | CONFIG_TMPFS=y |
| 902 | # CONFIG_TMPFS_POSIX_ACL is not set | 1028 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 903 | # CONFIG_HUGETLB_PAGE is not set | 1029 | # CONFIG_HUGETLB_PAGE is not set |
| 904 | CONFIG_RAMFS=y | ||
| 905 | # CONFIG_CONFIGFS_FS is not set | 1030 | # CONFIG_CONFIGFS_FS is not set |
| 906 | 1031 | CONFIG_MISC_FILESYSTEMS=y | |
| 907 | # | ||
| 908 | # Miscellaneous filesystems | ||
| 909 | # | ||
| 910 | # CONFIG_ADFS_FS is not set | 1032 | # CONFIG_ADFS_FS is not set |
| 911 | # CONFIG_AFFS_FS is not set | 1033 | # CONFIG_AFFS_FS is not set |
| 912 | # CONFIG_ECRYPT_FS is not set | 1034 | # CONFIG_ECRYPT_FS is not set |
| @@ -916,34 +1038,33 @@ CONFIG_RAMFS=y | |||
| 916 | # CONFIG_BFS_FS is not set | 1038 | # CONFIG_BFS_FS is not set |
| 917 | # CONFIG_EFS_FS is not set | 1039 | # CONFIG_EFS_FS is not set |
| 918 | # CONFIG_CRAMFS is not set | 1040 | # CONFIG_CRAMFS is not set |
| 1041 | # CONFIG_SQUASHFS is not set | ||
| 919 | # CONFIG_VXFS_FS is not set | 1042 | # CONFIG_VXFS_FS is not set |
| 1043 | # CONFIG_MINIX_FS is not set | ||
| 1044 | # CONFIG_OMFS_FS is not set | ||
| 920 | # CONFIG_HPFS_FS is not set | 1045 | # CONFIG_HPFS_FS is not set |
| 921 | # CONFIG_QNX4FS_FS is not set | 1046 | # CONFIG_QNX4FS_FS is not set |
| 1047 | # CONFIG_ROMFS_FS is not set | ||
| 922 | # CONFIG_SYSV_FS is not set | 1048 | # CONFIG_SYSV_FS is not set |
| 923 | CONFIG_UFS_FS=m | 1049 | CONFIG_UFS_FS=m |
| 924 | # CONFIG_UFS_FS_WRITE is not set | 1050 | # CONFIG_UFS_FS_WRITE is not set |
| 925 | # CONFIG_UFS_DEBUG is not set | 1051 | # CONFIG_UFS_DEBUG is not set |
| 926 | 1052 | CONFIG_NETWORK_FILESYSTEMS=y | |
| 927 | # | ||
| 928 | # Network File Systems | ||
| 929 | # | ||
| 930 | CONFIG_NFS_FS=m | 1053 | CONFIG_NFS_FS=m |
| 931 | CONFIG_NFS_V3=y | 1054 | CONFIG_NFS_V3=y |
| 932 | # CONFIG_NFS_V3_ACL is not set | 1055 | # CONFIG_NFS_V3_ACL is not set |
| 933 | CONFIG_NFS_V4=y | 1056 | CONFIG_NFS_V4=y |
| 934 | CONFIG_NFS_DIRECTIO=y | ||
| 935 | CONFIG_NFSD=m | 1057 | CONFIG_NFSD=m |
| 936 | CONFIG_NFSD_V3=y | 1058 | CONFIG_NFSD_V3=y |
| 937 | # CONFIG_NFSD_V3_ACL is not set | 1059 | # CONFIG_NFSD_V3_ACL is not set |
| 938 | CONFIG_NFSD_V4=y | 1060 | CONFIG_NFSD_V4=y |
| 939 | CONFIG_NFSD_TCP=y | ||
| 940 | CONFIG_LOCKD=m | 1061 | CONFIG_LOCKD=m |
| 941 | CONFIG_LOCKD_V4=y | 1062 | CONFIG_LOCKD_V4=y |
| 942 | CONFIG_EXPORTFS=m | 1063 | CONFIG_EXPORTFS=m |
| 943 | CONFIG_NFS_COMMON=y | 1064 | CONFIG_NFS_COMMON=y |
| 944 | CONFIG_SUNRPC=m | 1065 | CONFIG_SUNRPC=m |
| 945 | CONFIG_SUNRPC_GSS=m | 1066 | CONFIG_SUNRPC_GSS=m |
| 946 | # CONFIG_SUNRPC_BIND34 is not set | 1067 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 947 | CONFIG_RPCSEC_GSS_KRB5=m | 1068 | CONFIG_RPCSEC_GSS_KRB5=m |
| 948 | CONFIG_RPCSEC_GSS_SPKM3=m | 1069 | CONFIG_RPCSEC_GSS_SPKM3=m |
| 949 | CONFIG_SMB_FS=m | 1070 | CONFIG_SMB_FS=m |
| @@ -952,6 +1073,7 @@ CONFIG_SMB_NLS_REMOTE="cp437" | |||
| 952 | CONFIG_CIFS=m | 1073 | CONFIG_CIFS=m |
| 953 | # CONFIG_CIFS_STATS is not set | 1074 | # CONFIG_CIFS_STATS is not set |
| 954 | # CONFIG_CIFS_WEAK_PW_HASH is not set | 1075 | # CONFIG_CIFS_WEAK_PW_HASH is not set |
| 1076 | # CONFIG_CIFS_UPCALL is not set | ||
| 955 | # CONFIG_CIFS_XATTR is not set | 1077 | # CONFIG_CIFS_XATTR is not set |
| 956 | # CONFIG_CIFS_DEBUG2 is not set | 1078 | # CONFIG_CIFS_DEBUG2 is not set |
| 957 | # CONFIG_CIFS_EXPERIMENTAL is not set | 1079 | # CONFIG_CIFS_EXPERIMENTAL is not set |
| @@ -964,10 +1086,6 @@ CONFIG_CIFS=m | |||
| 964 | # | 1086 | # |
| 965 | # CONFIG_PARTITION_ADVANCED is not set | 1087 | # CONFIG_PARTITION_ADVANCED is not set |
| 966 | CONFIG_MSDOS_PARTITION=y | 1088 | CONFIG_MSDOS_PARTITION=y |
| 967 | |||
| 968 | # | ||
| 969 | # Native Language Support | ||
| 970 | # | ||
| 971 | CONFIG_NLS=y | 1089 | CONFIG_NLS=y |
| 972 | CONFIG_NLS_DEFAULT="iso8859-1" | 1090 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 973 | CONFIG_NLS_CODEPAGE_437=m | 1091 | CONFIG_NLS_CODEPAGE_437=m |
| @@ -1008,33 +1126,28 @@ CONFIG_NLS_ISO8859_15=m | |||
| 1008 | # CONFIG_NLS_KOI8_R is not set | 1126 | # CONFIG_NLS_KOI8_R is not set |
| 1009 | # CONFIG_NLS_KOI8_U is not set | 1127 | # CONFIG_NLS_KOI8_U is not set |
| 1010 | CONFIG_NLS_UTF8=m | 1128 | CONFIG_NLS_UTF8=m |
| 1011 | |||
| 1012 | # | ||
| 1013 | # Distributed Lock Manager | ||
| 1014 | # | ||
| 1015 | # CONFIG_DLM is not set | 1129 | # CONFIG_DLM is not set |
| 1016 | 1130 | ||
| 1017 | # | 1131 | # |
| 1018 | # Profiling support | ||
| 1019 | # | ||
| 1020 | CONFIG_PROFILING=y | ||
| 1021 | CONFIG_OPROFILE=m | ||
| 1022 | |||
| 1023 | # | ||
| 1024 | # Kernel hacking | 1132 | # Kernel hacking |
| 1025 | # | 1133 | # |
| 1026 | # CONFIG_PRINTK_TIME is not set | 1134 | # CONFIG_PRINTK_TIME is not set |
| 1135 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1027 | CONFIG_ENABLE_MUST_CHECK=y | 1136 | CONFIG_ENABLE_MUST_CHECK=y |
| 1137 | CONFIG_FRAME_WARN=2048 | ||
| 1028 | CONFIG_MAGIC_SYSRQ=y | 1138 | CONFIG_MAGIC_SYSRQ=y |
| 1029 | # CONFIG_UNUSED_SYMBOLS is not set | 1139 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1030 | # CONFIG_DEBUG_FS is not set | 1140 | CONFIG_DEBUG_FS=y |
| 1031 | CONFIG_HEADERS_CHECK=y | 1141 | CONFIG_HEADERS_CHECK=y |
| 1032 | CONFIG_DEBUG_KERNEL=y | 1142 | CONFIG_DEBUG_KERNEL=y |
| 1033 | # CONFIG_DEBUG_SHIRQ is not set | 1143 | # CONFIG_DEBUG_SHIRQ is not set |
| 1034 | CONFIG_DETECT_SOFTLOCKUP=y | 1144 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1145 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1146 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1035 | CONFIG_SCHED_DEBUG=y | 1147 | CONFIG_SCHED_DEBUG=y |
| 1036 | # CONFIG_SCHEDSTATS is not set | 1148 | # CONFIG_SCHEDSTATS is not set |
| 1037 | # CONFIG_TIMER_STATS is not set | 1149 | # CONFIG_TIMER_STATS is not set |
| 1150 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1038 | # CONFIG_DEBUG_SLAB is not set | 1151 | # CONFIG_DEBUG_SLAB is not set |
| 1039 | # CONFIG_DEBUG_RT_MUTEXES is not set | 1152 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| 1040 | # CONFIG_RT_MUTEX_TESTER is not set | 1153 | # CONFIG_RT_MUTEX_TESTER is not set |
| @@ -1046,10 +1159,33 @@ CONFIG_SCHED_DEBUG=y | |||
| 1046 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1159 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 1047 | # CONFIG_DEBUG_INFO is not set | 1160 | # CONFIG_DEBUG_INFO is not set |
| 1048 | # CONFIG_DEBUG_VM is not set | 1161 | # CONFIG_DEBUG_VM is not set |
| 1162 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1163 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1049 | # CONFIG_DEBUG_LIST is not set | 1164 | # CONFIG_DEBUG_LIST is not set |
| 1050 | CONFIG_FORCED_INLINING=y | 1165 | # CONFIG_DEBUG_SG is not set |
| 1166 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1167 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1051 | # CONFIG_RCU_TORTURE_TEST is not set | 1168 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1169 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1170 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1171 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1052 | # CONFIG_FAULT_INJECTION is not set | 1172 | # CONFIG_FAULT_INJECTION is not set |
| 1173 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1174 | CONFIG_NOP_TRACER=y | ||
| 1175 | CONFIG_RING_BUFFER=y | ||
| 1176 | CONFIG_TRACING=y | ||
| 1177 | |||
| 1178 | # | ||
| 1179 | # Tracers | ||
| 1180 | # | ||
| 1181 | # CONFIG_SCHED_TRACER is not set | ||
| 1182 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1183 | # CONFIG_BOOT_TRACER is not set | ||
| 1184 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1185 | # CONFIG_FTRACE_STARTUP_TEST is not set | ||
| 1186 | # CONFIG_BUILD_DOCSRC is not set | ||
| 1187 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1188 | # CONFIG_SAMPLES is not set | ||
| 1053 | # CONFIG_DEBUG_RODATA is not set | 1189 | # CONFIG_DEBUG_RODATA is not set |
| 1054 | 1190 | ||
| 1055 | # | 1191 | # |
| @@ -1058,56 +1194,112 @@ CONFIG_FORCED_INLINING=y | |||
| 1058 | CONFIG_KEYS=y | 1194 | CONFIG_KEYS=y |
| 1059 | CONFIG_KEYS_DEBUG_PROC_KEYS=y | 1195 | CONFIG_KEYS_DEBUG_PROC_KEYS=y |
| 1060 | # CONFIG_SECURITY is not set | 1196 | # CONFIG_SECURITY is not set |
| 1197 | # CONFIG_SECURITYFS is not set | ||
| 1198 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1061 | CONFIG_CRYPTO=y | 1199 | CONFIG_CRYPTO=y |
| 1200 | |||
| 1201 | # | ||
| 1202 | # Crypto core or helper | ||
| 1203 | # | ||
| 1204 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1062 | CONFIG_CRYPTO_ALGAPI=y | 1205 | CONFIG_CRYPTO_ALGAPI=y |
| 1206 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1207 | CONFIG_CRYPTO_AEAD=m | ||
| 1208 | CONFIG_CRYPTO_AEAD2=y | ||
| 1063 | CONFIG_CRYPTO_BLKCIPHER=m | 1209 | CONFIG_CRYPTO_BLKCIPHER=m |
| 1210 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1064 | CONFIG_CRYPTO_HASH=y | 1211 | CONFIG_CRYPTO_HASH=y |
| 1212 | CONFIG_CRYPTO_HASH2=y | ||
| 1213 | CONFIG_CRYPTO_RNG2=y | ||
| 1065 | CONFIG_CRYPTO_MANAGER=y | 1214 | CONFIG_CRYPTO_MANAGER=y |
| 1215 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1216 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1217 | CONFIG_CRYPTO_NULL=m | ||
| 1218 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1219 | CONFIG_CRYPTO_AUTHENC=m | ||
| 1220 | CONFIG_CRYPTO_TEST=m | ||
| 1221 | |||
| 1222 | # | ||
| 1223 | # Authenticated Encryption with Associated Data | ||
| 1224 | # | ||
| 1225 | # CONFIG_CRYPTO_CCM is not set | ||
| 1226 | # CONFIG_CRYPTO_GCM is not set | ||
| 1227 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1228 | |||
| 1229 | # | ||
| 1230 | # Block modes | ||
| 1231 | # | ||
| 1232 | CONFIG_CRYPTO_CBC=m | ||
| 1233 | # CONFIG_CRYPTO_CTR is not set | ||
| 1234 | # CONFIG_CRYPTO_CTS is not set | ||
| 1235 | # CONFIG_CRYPTO_ECB is not set | ||
| 1236 | # CONFIG_CRYPTO_LRW is not set | ||
| 1237 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1238 | # CONFIG_CRYPTO_XTS is not set | ||
| 1239 | |||
| 1240 | # | ||
| 1241 | # Hash modes | ||
| 1242 | # | ||
| 1066 | CONFIG_CRYPTO_HMAC=y | 1243 | CONFIG_CRYPTO_HMAC=y |
| 1067 | # CONFIG_CRYPTO_XCBC is not set | 1244 | # CONFIG_CRYPTO_XCBC is not set |
| 1068 | CONFIG_CRYPTO_NULL=m | 1245 | |
| 1246 | # | ||
| 1247 | # Digest | ||
| 1248 | # | ||
| 1249 | CONFIG_CRYPTO_CRC32C=m | ||
| 1069 | # CONFIG_CRYPTO_MD4 is not set | 1250 | # CONFIG_CRYPTO_MD4 is not set |
| 1070 | CONFIG_CRYPTO_MD5=y | 1251 | CONFIG_CRYPTO_MD5=y |
| 1252 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1253 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1254 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1255 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1256 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1071 | CONFIG_CRYPTO_SHA1=m | 1257 | CONFIG_CRYPTO_SHA1=m |
| 1072 | # CONFIG_CRYPTO_SHA256 is not set | 1258 | # CONFIG_CRYPTO_SHA256 is not set |
| 1073 | # CONFIG_CRYPTO_SHA512 is not set | 1259 | # CONFIG_CRYPTO_SHA512 is not set |
| 1074 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1075 | # CONFIG_CRYPTO_TGR192 is not set | 1260 | # CONFIG_CRYPTO_TGR192 is not set |
| 1076 | # CONFIG_CRYPTO_GF128MUL is not set | 1261 | # CONFIG_CRYPTO_WP512 is not set |
| 1077 | # CONFIG_CRYPTO_ECB is not set | 1262 | |
| 1078 | CONFIG_CRYPTO_CBC=m | 1263 | # |
| 1079 | # CONFIG_CRYPTO_PCBC is not set | 1264 | # Ciphers |
| 1080 | # CONFIG_CRYPTO_LRW is not set | 1265 | # |
| 1081 | # CONFIG_CRYPTO_XTS is not set | ||
| 1082 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1083 | CONFIG_CRYPTO_DES=m | ||
| 1084 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1085 | CONFIG_CRYPTO_BLOWFISH=m | ||
| 1086 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1087 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1088 | # CONFIG_CRYPTO_AES is not set | 1266 | # CONFIG_CRYPTO_AES is not set |
| 1267 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1268 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1269 | CONFIG_CRYPTO_BLOWFISH=m | ||
| 1270 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1089 | CONFIG_CRYPTO_CAST5=m | 1271 | CONFIG_CRYPTO_CAST5=m |
| 1090 | # CONFIG_CRYPTO_CAST6 is not set | 1272 | # CONFIG_CRYPTO_CAST6 is not set |
| 1091 | # CONFIG_CRYPTO_TEA is not set | 1273 | CONFIG_CRYPTO_DES=m |
| 1092 | # CONFIG_CRYPTO_ARC4 is not set | 1274 | # CONFIG_CRYPTO_FCRYPT is not set |
| 1093 | # CONFIG_CRYPTO_KHAZAD is not set | 1275 | # CONFIG_CRYPTO_KHAZAD is not set |
| 1094 | # CONFIG_CRYPTO_ANUBIS is not set | 1276 | # CONFIG_CRYPTO_SALSA20 is not set |
| 1095 | # CONFIG_CRYPTO_SEED is not set | 1277 | # CONFIG_CRYPTO_SEED is not set |
| 1278 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1279 | # CONFIG_CRYPTO_TEA is not set | ||
| 1280 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1281 | |||
| 1282 | # | ||
| 1283 | # Compression | ||
| 1284 | # | ||
| 1096 | CONFIG_CRYPTO_DEFLATE=m | 1285 | CONFIG_CRYPTO_DEFLATE=m |
| 1097 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | 1286 | # CONFIG_CRYPTO_LZO is not set |
| 1098 | CONFIG_CRYPTO_CRC32C=m | 1287 | |
| 1099 | # CONFIG_CRYPTO_CAMELLIA is not set | 1288 | # |
| 1100 | CONFIG_CRYPTO_TEST=m | 1289 | # Random Number Generation |
| 1101 | # CONFIG_CRYPTO_AUTHENC is not set | 1290 | # |
| 1291 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1102 | # CONFIG_CRYPTO_HW is not set | 1292 | # CONFIG_CRYPTO_HW is not set |
| 1103 | 1293 | ||
| 1104 | # | 1294 | # |
| 1105 | # Library routines | 1295 | # Library routines |
| 1106 | # | 1296 | # |
| 1107 | CONFIG_BITREVERSE=y | 1297 | CONFIG_BITREVERSE=y |
| 1298 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1108 | CONFIG_CRC_CCITT=m | 1299 | CONFIG_CRC_CCITT=m |
| 1109 | # CONFIG_CRC16 is not set | 1300 | # CONFIG_CRC16 is not set |
| 1110 | # CONFIG_CRC_ITU_T is not set | 1301 | # CONFIG_CRC_T10DIF is not set |
| 1302 | CONFIG_CRC_ITU_T=m | ||
| 1111 | CONFIG_CRC32=y | 1303 | CONFIG_CRC32=y |
| 1112 | # CONFIG_CRC7 is not set | 1304 | # CONFIG_CRC7 is not set |
| 1113 | CONFIG_LIBCRC32C=m | 1305 | CONFIG_LIBCRC32C=m |
diff --git a/arch/parisc/configs/b180_defconfig b/arch/parisc/configs/b180_defconfig index 1bf22c9a4614..98bb05ee6e8d 100644 --- a/arch/parisc/configs/b180_defconfig +++ b/arch/parisc/configs/b180_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.23 | 3 | # Linux kernel version: 2.6.29-rc8 |
| 4 | # Fri Oct 12 21:16:46 2007 | 4 | # Fri Mar 13 01:32:57 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_PARISC=y | 6 | CONFIG_PARISC=y |
| 7 | CONFIG_MMU=y | 7 | CONFIG_MMU=y |
| @@ -33,13 +33,29 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 33 | # CONFIG_BSD_PROCESS_ACCT is not set | 33 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 34 | # CONFIG_TASKSTATS is not set | 34 | # CONFIG_TASKSTATS is not set |
| 35 | # CONFIG_AUDIT is not set | 35 | # CONFIG_AUDIT is not set |
| 36 | |||
| 37 | # | ||
| 38 | # RCU Subsystem | ||
| 39 | # | ||
| 40 | CONFIG_CLASSIC_RCU=y | ||
| 41 | # CONFIG_TREE_RCU is not set | ||
| 42 | # CONFIG_PREEMPT_RCU is not set | ||
| 43 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 44 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 36 | CONFIG_IKCONFIG=y | 45 | CONFIG_IKCONFIG=y |
| 37 | CONFIG_IKCONFIG_PROC=y | 46 | CONFIG_IKCONFIG_PROC=y |
| 38 | CONFIG_LOG_BUF_SHIFT=16 | 47 | CONFIG_LOG_BUF_SHIFT=16 |
| 48 | # CONFIG_CGROUPS is not set | ||
| 39 | CONFIG_SYSFS_DEPRECATED=y | 49 | CONFIG_SYSFS_DEPRECATED=y |
| 50 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 40 | # CONFIG_RELAY is not set | 51 | # CONFIG_RELAY is not set |
| 52 | CONFIG_NAMESPACES=y | ||
| 53 | # CONFIG_UTS_NS is not set | ||
| 54 | # CONFIG_IPC_NS is not set | ||
| 41 | # CONFIG_BLK_DEV_INITRD is not set | 55 | # CONFIG_BLK_DEV_INITRD is not set |
| 56 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | ||
| 42 | CONFIG_SYSCTL=y | 57 | CONFIG_SYSCTL=y |
| 58 | CONFIG_ANON_INODES=y | ||
| 43 | # CONFIG_EMBEDDED is not set | 59 | # CONFIG_EMBEDDED is not set |
| 44 | CONFIG_SYSCTL_SYSCALL=y | 60 | CONFIG_SYSCTL_SYSCALL=y |
| 45 | CONFIG_KALLSYMS=y | 61 | CONFIG_KALLSYMS=y |
| @@ -51,27 +67,34 @@ CONFIG_BUG=y | |||
| 51 | CONFIG_ELF_CORE=y | 67 | CONFIG_ELF_CORE=y |
| 52 | CONFIG_BASE_FULL=y | 68 | CONFIG_BASE_FULL=y |
| 53 | CONFIG_FUTEX=y | 69 | CONFIG_FUTEX=y |
| 54 | CONFIG_ANON_INODES=y | ||
| 55 | CONFIG_EPOLL=y | 70 | CONFIG_EPOLL=y |
| 56 | CONFIG_SIGNALFD=y | 71 | CONFIG_SIGNALFD=y |
| 72 | CONFIG_TIMERFD=y | ||
| 57 | CONFIG_EVENTFD=y | 73 | CONFIG_EVENTFD=y |
| 58 | CONFIG_SHMEM=y | 74 | CONFIG_SHMEM=y |
| 75 | CONFIG_AIO=y | ||
| 59 | CONFIG_VM_EVENT_COUNTERS=y | 76 | CONFIG_VM_EVENT_COUNTERS=y |
| 77 | CONFIG_PCI_QUIRKS=y | ||
| 78 | CONFIG_COMPAT_BRK=y | ||
| 60 | CONFIG_SLAB=y | 79 | CONFIG_SLAB=y |
| 61 | # CONFIG_SLUB is not set | 80 | # CONFIG_SLUB is not set |
| 62 | # CONFIG_SLOB is not set | 81 | # CONFIG_SLOB is not set |
| 82 | # CONFIG_PROFILING is not set | ||
| 83 | CONFIG_HAVE_OPROFILE=y | ||
| 84 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 85 | CONFIG_SLABINFO=y | ||
| 63 | CONFIG_RT_MUTEXES=y | 86 | CONFIG_RT_MUTEXES=y |
| 64 | # CONFIG_TINY_SHMEM is not set | ||
| 65 | CONFIG_BASE_SMALL=0 | 87 | CONFIG_BASE_SMALL=0 |
| 66 | CONFIG_MODULES=y | 88 | CONFIG_MODULES=y |
| 89 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 67 | # CONFIG_MODULE_UNLOAD is not set | 90 | # CONFIG_MODULE_UNLOAD is not set |
| 68 | CONFIG_MODVERSIONS=y | 91 | CONFIG_MODVERSIONS=y |
| 69 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 92 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 70 | # CONFIG_KMOD is not set | 93 | CONFIG_INIT_ALL_POSSIBLE=y |
| 71 | CONFIG_BLOCK=y | 94 | CONFIG_BLOCK=y |
| 72 | # CONFIG_LBD is not set | 95 | # CONFIG_LBD is not set |
| 73 | # CONFIG_BLK_DEV_IO_TRACE is not set | 96 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 74 | # CONFIG_LSF is not set | 97 | # CONFIG_BLK_DEV_INTEGRITY is not set |
| 75 | 98 | ||
| 76 | # | 99 | # |
| 77 | # IO Schedulers | 100 | # IO Schedulers |
| @@ -85,6 +108,7 @@ CONFIG_IOSCHED_CFQ=y | |||
| 85 | CONFIG_DEFAULT_CFQ=y | 108 | CONFIG_DEFAULT_CFQ=y |
| 86 | # CONFIG_DEFAULT_NOOP is not set | 109 | # CONFIG_DEFAULT_NOOP is not set |
| 87 | CONFIG_DEFAULT_IOSCHED="cfq" | 110 | CONFIG_DEFAULT_IOSCHED="cfq" |
| 111 | # CONFIG_FREEZER is not set | ||
| 88 | 112 | ||
| 89 | # | 113 | # |
| 90 | # Processor type and features | 114 | # Processor type and features |
| @@ -108,13 +132,15 @@ CONFIG_HZ_250=y | |||
| 108 | # CONFIG_HZ_300 is not set | 132 | # CONFIG_HZ_300 is not set |
| 109 | # CONFIG_HZ_1000 is not set | 133 | # CONFIG_HZ_1000 is not set |
| 110 | CONFIG_HZ=250 | 134 | CONFIG_HZ=250 |
| 135 | # CONFIG_SCHED_HRTICK is not set | ||
| 111 | CONFIG_FLATMEM=y | 136 | CONFIG_FLATMEM=y |
| 112 | CONFIG_FLAT_NODE_MEM_MAP=y | 137 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 113 | # CONFIG_SPARSEMEM_STATIC is not set | 138 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 114 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 139 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 115 | # CONFIG_RESOURCES_64BIT is not set | 140 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 116 | CONFIG_ZONE_DMA_FLAG=0 | 141 | CONFIG_ZONE_DMA_FLAG=0 |
| 117 | CONFIG_VIRT_TO_BUS=y | 142 | CONFIG_VIRT_TO_BUS=y |
| 143 | CONFIG_UNEVICTABLE_LRU=y | ||
| 118 | # CONFIG_HPUX is not set | 144 | # CONFIG_HPUX is not set |
| 119 | 145 | ||
| 120 | # | 146 | # |
| @@ -130,14 +156,14 @@ CONFIG_EISA_NAMES=y | |||
| 130 | CONFIG_ISA=y | 156 | CONFIG_ISA=y |
| 131 | CONFIG_PCI=y | 157 | CONFIG_PCI=y |
| 132 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 158 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 159 | CONFIG_PCI_LEGACY=y | ||
| 133 | # CONFIG_PCI_DEBUG is not set | 160 | # CONFIG_PCI_DEBUG is not set |
| 161 | # CONFIG_PCI_STUB is not set | ||
| 134 | CONFIG_GSC_DINO=y | 162 | CONFIG_GSC_DINO=y |
| 135 | # CONFIG_PCI_LBA is not set | 163 | # CONFIG_PCI_LBA is not set |
| 136 | 164 | CONFIG_IOMMU_HELPER=y | |
| 137 | # | ||
| 138 | # PCCARD (PCMCIA/CardBus) support | ||
| 139 | # | ||
| 140 | # CONFIG_PCCARD is not set | 165 | # CONFIG_PCCARD is not set |
| 166 | # CONFIG_HOTPLUG_PCI is not set | ||
| 141 | 167 | ||
| 142 | # | 168 | # |
| 143 | # PA-RISC specific drivers | 169 | # PA-RISC specific drivers |
| @@ -151,16 +177,15 @@ CONFIG_PDC_STABLE=y | |||
| 151 | # Executable file formats | 177 | # Executable file formats |
| 152 | # | 178 | # |
| 153 | CONFIG_BINFMT_ELF=y | 179 | CONFIG_BINFMT_ELF=y |
| 180 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 181 | # CONFIG_HAVE_AOUT is not set | ||
| 154 | # CONFIG_BINFMT_MISC is not set | 182 | # CONFIG_BINFMT_MISC is not set |
| 155 | |||
| 156 | # | ||
| 157 | # Networking | ||
| 158 | # | ||
| 159 | CONFIG_NET=y | 183 | CONFIG_NET=y |
| 160 | 184 | ||
| 161 | # | 185 | # |
| 162 | # Networking options | 186 | # Networking options |
| 163 | # | 187 | # |
| 188 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 164 | CONFIG_PACKET=y | 189 | CONFIG_PACKET=y |
| 165 | CONFIG_PACKET_MMAP=y | 190 | CONFIG_PACKET_MMAP=y |
| 166 | CONFIG_UNIX=y | 191 | CONFIG_UNIX=y |
| @@ -205,36 +230,37 @@ CONFIG_INET6_XFRM_MODE_TRANSPORT=y | |||
| 205 | CONFIG_INET6_XFRM_MODE_TUNNEL=y | 230 | CONFIG_INET6_XFRM_MODE_TUNNEL=y |
| 206 | CONFIG_INET6_XFRM_MODE_BEET=y | 231 | CONFIG_INET6_XFRM_MODE_BEET=y |
| 207 | CONFIG_IPV6_SIT=y | 232 | CONFIG_IPV6_SIT=y |
| 233 | CONFIG_IPV6_NDISC_NODETYPE=y | ||
| 208 | # CONFIG_IPV6_TUNNEL is not set | 234 | # CONFIG_IPV6_TUNNEL is not set |
| 209 | # CONFIG_NETLABEL is not set | 235 | # CONFIG_NETLABEL is not set |
| 210 | # CONFIG_NETWORK_SECMARK is not set | 236 | # CONFIG_NETWORK_SECMARK is not set |
| 211 | # CONFIG_NETFILTER is not set | 237 | # CONFIG_NETFILTER is not set |
| 238 | # CONFIG_ATM is not set | ||
| 212 | # CONFIG_BRIDGE is not set | 239 | # CONFIG_BRIDGE is not set |
| 213 | # CONFIG_VLAN_8021Q is not set | 240 | # CONFIG_VLAN_8021Q is not set |
| 214 | # CONFIG_DECNET is not set | 241 | # CONFIG_DECNET is not set |
| 215 | # CONFIG_LLC2 is not set | 242 | # CONFIG_LLC2 is not set |
| 216 | # CONFIG_IPX is not set | 243 | # CONFIG_IPX is not set |
| 217 | # CONFIG_ATALK is not set | 244 | # CONFIG_ATALK is not set |
| 218 | |||
| 219 | # | ||
| 220 | # QoS and/or fair queueing | ||
| 221 | # | ||
| 222 | # CONFIG_NET_SCHED is not set | 245 | # CONFIG_NET_SCHED is not set |
| 246 | # CONFIG_DCB is not set | ||
| 223 | 247 | ||
| 224 | # | 248 | # |
| 225 | # Network testing | 249 | # Network testing |
| 226 | # | 250 | # |
| 227 | # CONFIG_NET_PKTGEN is not set | 251 | # CONFIG_NET_PKTGEN is not set |
| 228 | # CONFIG_HAMRADIO is not set | 252 | # CONFIG_HAMRADIO is not set |
| 253 | # CONFIG_CAN is not set | ||
| 229 | # CONFIG_IRDA is not set | 254 | # CONFIG_IRDA is not set |
| 230 | # CONFIG_BT is not set | 255 | # CONFIG_BT is not set |
| 231 | 256 | # CONFIG_PHONET is not set | |
| 232 | # | 257 | CONFIG_WIRELESS=y |
| 233 | # Wireless | ||
| 234 | # | ||
| 235 | # CONFIG_CFG80211 is not set | 258 | # CONFIG_CFG80211 is not set |
| 259 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 236 | # CONFIG_WIRELESS_EXT is not set | 260 | # CONFIG_WIRELESS_EXT is not set |
| 237 | # CONFIG_IEEE80211 is not set | 261 | # CONFIG_LIB80211 is not set |
| 262 | # CONFIG_MAC80211 is not set | ||
| 263 | # CONFIG_WIMAX is not set | ||
| 238 | # CONFIG_RFKILL is not set | 264 | # CONFIG_RFKILL is not set |
| 239 | 265 | ||
| 240 | # | 266 | # |
| @@ -247,7 +273,9 @@ CONFIG_IPV6_SIT=y | |||
| 247 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | 273 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
| 248 | CONFIG_STANDALONE=y | 274 | CONFIG_STANDALONE=y |
| 249 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | 275 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set |
| 250 | # CONFIG_FW_LOADER is not set | 276 | CONFIG_FW_LOADER=y |
| 277 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 278 | CONFIG_EXTRA_FIRMWARE="" | ||
| 251 | # CONFIG_DEBUG_DRIVER is not set | 279 | # CONFIG_DEBUG_DRIVER is not set |
| 252 | # CONFIG_DEBUG_DEVRES is not set | 280 | # CONFIG_DEBUG_DEVRES is not set |
| 253 | # CONFIG_SYS_HYPERVISOR is not set | 281 | # CONFIG_SYS_HYPERVISOR is not set |
| @@ -275,10 +303,18 @@ CONFIG_BLK_DEV_CRYPTOLOOP=y | |||
| 275 | CONFIG_CDROM_PKTCDVD=m | 303 | CONFIG_CDROM_PKTCDVD=m |
| 276 | CONFIG_CDROM_PKTCDVD_BUFFERS=8 | 304 | CONFIG_CDROM_PKTCDVD_BUFFERS=8 |
| 277 | CONFIG_ATA_OVER_ETH=y | 305 | CONFIG_ATA_OVER_ETH=y |
| 306 | # CONFIG_BLK_DEV_HD is not set | ||
| 278 | CONFIG_MISC_DEVICES=y | 307 | CONFIG_MISC_DEVICES=y |
| 279 | # CONFIG_PHANTOM is not set | 308 | # CONFIG_PHANTOM is not set |
| 280 | # CONFIG_EEPROM_93CX6 is not set | ||
| 281 | # CONFIG_SGI_IOC4 is not set | 309 | # CONFIG_SGI_IOC4 is not set |
| 310 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 311 | # CONFIG_HP_ILO is not set | ||
| 312 | |||
| 313 | # | ||
| 314 | # EEPROM support | ||
| 315 | # | ||
| 316 | # CONFIG_EEPROM_93CX6 is not set | ||
| 317 | CONFIG_HAVE_IDE=y | ||
| 282 | # CONFIG_IDE is not set | 318 | # CONFIG_IDE is not set |
| 283 | 319 | ||
| 284 | # | 320 | # |
| @@ -317,8 +353,10 @@ CONFIG_SCSI_SPI_ATTRS=y | |||
| 317 | # CONFIG_SCSI_FC_ATTRS is not set | 353 | # CONFIG_SCSI_FC_ATTRS is not set |
| 318 | # CONFIG_SCSI_ISCSI_ATTRS is not set | 354 | # CONFIG_SCSI_ISCSI_ATTRS is not set |
| 319 | # CONFIG_SCSI_SAS_LIBSAS is not set | 355 | # CONFIG_SCSI_SAS_LIBSAS is not set |
| 356 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 320 | CONFIG_SCSI_LOWLEVEL=y | 357 | CONFIG_SCSI_LOWLEVEL=y |
| 321 | # CONFIG_ISCSI_TCP is not set | 358 | # CONFIG_ISCSI_TCP is not set |
| 359 | # CONFIG_SCSI_CXGB3_ISCSI is not set | ||
| 322 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set | 360 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set |
| 323 | # CONFIG_SCSI_3W_9XXX is not set | 361 | # CONFIG_SCSI_3W_9XXX is not set |
| 324 | # CONFIG_SCSI_ACARD is not set | 362 | # CONFIG_SCSI_ACARD is not set |
| @@ -330,12 +368,15 @@ CONFIG_SCSI_LOWLEVEL=y | |||
| 330 | # CONFIG_SCSI_AIC79XX is not set | 368 | # CONFIG_SCSI_AIC79XX is not set |
| 331 | # CONFIG_SCSI_AIC94XX is not set | 369 | # CONFIG_SCSI_AIC94XX is not set |
| 332 | # CONFIG_SCSI_DPT_I2O is not set | 370 | # CONFIG_SCSI_DPT_I2O is not set |
| 371 | # CONFIG_SCSI_ADVANSYS is not set | ||
| 333 | # CONFIG_SCSI_IN2000 is not set | 372 | # CONFIG_SCSI_IN2000 is not set |
| 334 | # CONFIG_SCSI_ARCMSR is not set | 373 | # CONFIG_SCSI_ARCMSR is not set |
| 335 | # CONFIG_MEGARAID_NEWGEN is not set | 374 | # CONFIG_MEGARAID_NEWGEN is not set |
| 336 | # CONFIG_MEGARAID_LEGACY is not set | 375 | # CONFIG_MEGARAID_LEGACY is not set |
| 337 | # CONFIG_MEGARAID_SAS is not set | 376 | # CONFIG_MEGARAID_SAS is not set |
| 338 | # CONFIG_SCSI_HPTIOP is not set | 377 | # CONFIG_SCSI_HPTIOP is not set |
| 378 | # CONFIG_LIBFC is not set | ||
| 379 | # CONFIG_FCOE is not set | ||
| 339 | # CONFIG_SCSI_DMX3191D is not set | 380 | # CONFIG_SCSI_DMX3191D is not set |
| 340 | # CONFIG_SCSI_DTC3280 is not set | 381 | # CONFIG_SCSI_DTC3280 is not set |
| 341 | # CONFIG_SCSI_FUTURE_DOMAIN is not set | 382 | # CONFIG_SCSI_FUTURE_DOMAIN is not set |
| @@ -346,6 +387,7 @@ CONFIG_SCSI_LOWLEVEL=y | |||
| 346 | # CONFIG_SCSI_INIA100 is not set | 387 | # CONFIG_SCSI_INIA100 is not set |
| 347 | # CONFIG_SCSI_PPA is not set | 388 | # CONFIG_SCSI_PPA is not set |
| 348 | # CONFIG_SCSI_IMM is not set | 389 | # CONFIG_SCSI_IMM is not set |
| 390 | # CONFIG_SCSI_MVSAS is not set | ||
| 349 | # CONFIG_SCSI_NCR53C406A is not set | 391 | # CONFIG_SCSI_NCR53C406A is not set |
| 350 | CONFIG_SCSI_LASI700=y | 392 | CONFIG_SCSI_LASI700=y |
| 351 | CONFIG_53C700_LE_ON_BE=y | 393 | CONFIG_53C700_LE_ON_BE=y |
| @@ -360,7 +402,6 @@ CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS=8 | |||
| 360 | CONFIG_SCSI_NCR53C8XX_MAX_TAGS=32 | 402 | CONFIG_SCSI_NCR53C8XX_MAX_TAGS=32 |
| 361 | CONFIG_SCSI_NCR53C8XX_SYNC=40 | 403 | CONFIG_SCSI_NCR53C8XX_SYNC=40 |
| 362 | # CONFIG_SCSI_PAS16 is not set | 404 | # CONFIG_SCSI_PAS16 is not set |
| 363 | # CONFIG_SCSI_PSI240I is not set | ||
| 364 | # CONFIG_SCSI_QLOGIC_FAS is not set | 405 | # CONFIG_SCSI_QLOGIC_FAS is not set |
| 365 | # CONFIG_SCSI_QLOGIC_1280 is not set | 406 | # CONFIG_SCSI_QLOGIC_1280 is not set |
| 366 | # CONFIG_SCSI_QLA_FC is not set | 407 | # CONFIG_SCSI_QLA_FC is not set |
| @@ -373,9 +414,11 @@ CONFIG_SCSI_NCR53C8XX_SYNC=40 | |||
| 373 | # CONFIG_SCSI_NSP32 is not set | 414 | # CONFIG_SCSI_NSP32 is not set |
| 374 | # CONFIG_SCSI_DEBUG is not set | 415 | # CONFIG_SCSI_DEBUG is not set |
| 375 | # CONFIG_SCSI_SRP is not set | 416 | # CONFIG_SCSI_SRP is not set |
| 417 | # CONFIG_SCSI_DH is not set | ||
| 376 | # CONFIG_ATA is not set | 418 | # CONFIG_ATA is not set |
| 377 | CONFIG_MD=y | 419 | CONFIG_MD=y |
| 378 | CONFIG_BLK_DEV_MD=y | 420 | CONFIG_BLK_DEV_MD=y |
| 421 | CONFIG_MD_AUTODETECT=y | ||
| 379 | CONFIG_MD_LINEAR=y | 422 | CONFIG_MD_LINEAR=y |
| 380 | CONFIG_MD_RAID0=y | 423 | CONFIG_MD_RAID0=y |
| 381 | CONFIG_MD_RAID1=y | 424 | CONFIG_MD_RAID1=y |
| @@ -383,26 +426,18 @@ CONFIG_MD_RAID1=y | |||
| 383 | # CONFIG_MD_MULTIPATH is not set | 426 | # CONFIG_MD_MULTIPATH is not set |
| 384 | # CONFIG_MD_FAULTY is not set | 427 | # CONFIG_MD_FAULTY is not set |
| 385 | # CONFIG_BLK_DEV_DM is not set | 428 | # CONFIG_BLK_DEV_DM is not set |
| 386 | |||
| 387 | # | ||
| 388 | # Fusion MPT device support | ||
| 389 | # | ||
| 390 | # CONFIG_FUSION is not set | 429 | # CONFIG_FUSION is not set |
| 391 | # CONFIG_FUSION_SPI is not set | ||
| 392 | # CONFIG_FUSION_FC is not set | ||
| 393 | # CONFIG_FUSION_SAS is not set | ||
| 394 | 430 | ||
| 395 | # | 431 | # |
| 396 | # IEEE 1394 (FireWire) support | 432 | # IEEE 1394 (FireWire) support |
| 397 | # | 433 | # |
| 398 | 434 | ||
| 399 | # | 435 | # |
| 400 | # An alternative FireWire stack is available with EXPERIMENTAL=y | 436 | # A new alternative FireWire stack is available with EXPERIMENTAL=y |
| 401 | # | 437 | # |
| 402 | # CONFIG_IEEE1394 is not set | 438 | # CONFIG_IEEE1394 is not set |
| 403 | # CONFIG_I2O is not set | 439 | # CONFIG_I2O is not set |
| 404 | CONFIG_NETDEVICES=y | 440 | CONFIG_NETDEVICES=y |
| 405 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 406 | # CONFIG_DUMMY is not set | 441 | # CONFIG_DUMMY is not set |
| 407 | # CONFIG_BONDING is not set | 442 | # CONFIG_BONDING is not set |
| 408 | # CONFIG_EQUALIZER is not set | 443 | # CONFIG_EQUALIZER is not set |
| @@ -434,36 +469,49 @@ CONFIG_TULIP=y | |||
| 434 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 469 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 435 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 470 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 436 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 471 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 472 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 473 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 474 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 437 | # CONFIG_NET_PCI is not set | 475 | # CONFIG_NET_PCI is not set |
| 438 | # CONFIG_B44 is not set | 476 | # CONFIG_B44 is not set |
| 477 | # CONFIG_CS89x0 is not set | ||
| 439 | # CONFIG_NET_POCKET is not set | 478 | # CONFIG_NET_POCKET is not set |
| 479 | # CONFIG_ATL2 is not set | ||
| 440 | CONFIG_NETDEV_1000=y | 480 | CONFIG_NETDEV_1000=y |
| 441 | # CONFIG_ACENIC is not set | 481 | # CONFIG_ACENIC is not set |
| 442 | # CONFIG_DL2K is not set | 482 | # CONFIG_DL2K is not set |
| 443 | # CONFIG_E1000 is not set | 483 | # CONFIG_E1000 is not set |
| 444 | # CONFIG_E1000E is not set | 484 | # CONFIG_E1000E is not set |
| 485 | # CONFIG_IGB is not set | ||
| 445 | # CONFIG_NS83820 is not set | 486 | # CONFIG_NS83820 is not set |
| 446 | # CONFIG_HAMACHI is not set | 487 | # CONFIG_HAMACHI is not set |
| 447 | # CONFIG_R8169 is not set | 488 | # CONFIG_R8169 is not set |
| 448 | # CONFIG_SIS190 is not set | 489 | # CONFIG_SIS190 is not set |
| 449 | # CONFIG_SKGE is not set | 490 | # CONFIG_SKGE is not set |
| 450 | # CONFIG_SKY2 is not set | 491 | # CONFIG_SKY2 is not set |
| 451 | # CONFIG_SK98LIN is not set | ||
| 452 | # CONFIG_VIA_VELOCITY is not set | 492 | # CONFIG_VIA_VELOCITY is not set |
| 453 | # CONFIG_TIGON3 is not set | 493 | # CONFIG_TIGON3 is not set |
| 454 | # CONFIG_BNX2 is not set | 494 | # CONFIG_BNX2 is not set |
| 455 | # CONFIG_QLA3XXX is not set | 495 | # CONFIG_QLA3XXX is not set |
| 496 | # CONFIG_ATL1 is not set | ||
| 497 | # CONFIG_JME is not set | ||
| 456 | CONFIG_NETDEV_10000=y | 498 | CONFIG_NETDEV_10000=y |
| 457 | # CONFIG_CHELSIO_T1 is not set | 499 | # CONFIG_CHELSIO_T1 is not set |
| 500 | CONFIG_CHELSIO_T3_DEPENDS=y | ||
| 458 | # CONFIG_CHELSIO_T3 is not set | 501 | # CONFIG_CHELSIO_T3 is not set |
| 502 | # CONFIG_ENIC is not set | ||
| 459 | # CONFIG_IXGBE is not set | 503 | # CONFIG_IXGBE is not set |
| 460 | # CONFIG_IXGB is not set | 504 | # CONFIG_IXGB is not set |
| 461 | # CONFIG_S2IO is not set | 505 | # CONFIG_S2IO is not set |
| 462 | # CONFIG_MYRI10GE is not set | 506 | # CONFIG_MYRI10GE is not set |
| 463 | # CONFIG_NETXEN_NIC is not set | 507 | # CONFIG_NETXEN_NIC is not set |
| 464 | # CONFIG_NIU is not set | 508 | # CONFIG_NIU is not set |
| 509 | # CONFIG_MLX4_EN is not set | ||
| 465 | # CONFIG_MLX4_CORE is not set | 510 | # CONFIG_MLX4_CORE is not set |
| 466 | # CONFIG_TEHUTI is not set | 511 | # CONFIG_TEHUTI is not set |
| 512 | # CONFIG_BNX2X is not set | ||
| 513 | # CONFIG_QLGE is not set | ||
| 514 | # CONFIG_SFC is not set | ||
| 467 | # CONFIG_TR is not set | 515 | # CONFIG_TR is not set |
| 468 | 516 | ||
| 469 | # | 517 | # |
| @@ -471,6 +519,11 @@ CONFIG_NETDEV_10000=y | |||
| 471 | # | 519 | # |
| 472 | # CONFIG_WLAN_PRE80211 is not set | 520 | # CONFIG_WLAN_PRE80211 is not set |
| 473 | # CONFIG_WLAN_80211 is not set | 521 | # CONFIG_WLAN_80211 is not set |
| 522 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 523 | |||
| 524 | # | ||
| 525 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 526 | # | ||
| 474 | # CONFIG_WAN is not set | 527 | # CONFIG_WAN is not set |
| 475 | # CONFIG_FDDI is not set | 528 | # CONFIG_FDDI is not set |
| 476 | # CONFIG_PLIP is not set | 529 | # CONFIG_PLIP is not set |
| @@ -503,7 +556,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y | |||
| 503 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | 556 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 |
| 504 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | 557 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 |
| 505 | # CONFIG_INPUT_JOYDEV is not set | 558 | # CONFIG_INPUT_JOYDEV is not set |
| 506 | # CONFIG_INPUT_TSDEV is not set | ||
| 507 | CONFIG_INPUT_EVDEV=y | 559 | CONFIG_INPUT_EVDEV=y |
| 508 | # CONFIG_INPUT_EVBUG is not set | 560 | # CONFIG_INPUT_EVBUG is not set |
| 509 | 561 | ||
| @@ -526,11 +578,12 @@ CONFIG_MOUSE_PS2=y | |||
| 526 | CONFIG_MOUSE_PS2_ALPS=y | 578 | CONFIG_MOUSE_PS2_ALPS=y |
| 527 | CONFIG_MOUSE_PS2_LOGIPS2PP=y | 579 | CONFIG_MOUSE_PS2_LOGIPS2PP=y |
| 528 | CONFIG_MOUSE_PS2_SYNAPTICS=y | 580 | CONFIG_MOUSE_PS2_SYNAPTICS=y |
| 529 | CONFIG_MOUSE_PS2_LIFEBOOK=y | ||
| 530 | CONFIG_MOUSE_PS2_TRACKPOINT=y | 581 | CONFIG_MOUSE_PS2_TRACKPOINT=y |
| 582 | # CONFIG_MOUSE_PS2_ELANTECH is not set | ||
| 531 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | 583 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set |
| 532 | # CONFIG_MOUSE_SERIAL is not set | 584 | # CONFIG_MOUSE_SERIAL is not set |
| 533 | # CONFIG_MOUSE_APPLETOUCH is not set | 585 | # CONFIG_MOUSE_APPLETOUCH is not set |
| 586 | # CONFIG_MOUSE_BCM5974 is not set | ||
| 534 | # CONFIG_MOUSE_INPORT is not set | 587 | # CONFIG_MOUSE_INPORT is not set |
| 535 | # CONFIG_MOUSE_LOGIBM is not set | 588 | # CONFIG_MOUSE_LOGIBM is not set |
| 536 | # CONFIG_MOUSE_PC110PAD is not set | 589 | # CONFIG_MOUSE_PC110PAD is not set |
| @@ -564,9 +617,11 @@ CONFIG_SERIO_LIBPS2=y | |||
| 564 | # Character devices | 617 | # Character devices |
| 565 | # | 618 | # |
| 566 | CONFIG_VT=y | 619 | CONFIG_VT=y |
| 620 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 567 | CONFIG_VT_CONSOLE=y | 621 | CONFIG_VT_CONSOLE=y |
| 568 | CONFIG_HW_CONSOLE=y | 622 | CONFIG_HW_CONSOLE=y |
| 569 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | 623 | # CONFIG_VT_HW_CONSOLE_BINDING is not set |
| 624 | CONFIG_DEVKMEM=y | ||
| 570 | # CONFIG_SERIAL_NONSTANDARD is not set | 625 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 571 | 626 | ||
| 572 | # | 627 | # |
| @@ -598,75 +653,79 @@ CONFIG_SERIAL_CORE=y | |||
| 598 | CONFIG_SERIAL_CORE_CONSOLE=y | 653 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 599 | # CONFIG_SERIAL_JSM is not set | 654 | # CONFIG_SERIAL_JSM is not set |
| 600 | CONFIG_UNIX98_PTYS=y | 655 | CONFIG_UNIX98_PTYS=y |
| 656 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 601 | CONFIG_LEGACY_PTYS=y | 657 | CONFIG_LEGACY_PTYS=y |
| 602 | CONFIG_LEGACY_PTY_COUNT=256 | 658 | CONFIG_LEGACY_PTY_COUNT=256 |
| 603 | CONFIG_PRINTER=y | 659 | CONFIG_PRINTER=y |
| 604 | # CONFIG_LP_CONSOLE is not set | 660 | # CONFIG_LP_CONSOLE is not set |
| 605 | # CONFIG_PPDEV is not set | 661 | # CONFIG_PPDEV is not set |
| 606 | # CONFIG_TIPAR is not set | ||
| 607 | # CONFIG_IPMI_HANDLER is not set | 662 | # CONFIG_IPMI_HANDLER is not set |
| 608 | # CONFIG_WATCHDOG is not set | ||
| 609 | # CONFIG_HW_RANDOM is not set | 663 | # CONFIG_HW_RANDOM is not set |
| 610 | CONFIG_GEN_RTC=y | ||
| 611 | # CONFIG_GEN_RTC_X is not set | ||
| 612 | # CONFIG_DTLK is not set | 664 | # CONFIG_DTLK is not set |
| 613 | # CONFIG_R3964 is not set | 665 | # CONFIG_R3964 is not set |
| 614 | # CONFIG_APPLICOM is not set | 666 | # CONFIG_APPLICOM is not set |
| 615 | # CONFIG_AGP is not set | ||
| 616 | # CONFIG_DRM is not set | ||
| 617 | # CONFIG_RAW_DRIVER is not set | 667 | # CONFIG_RAW_DRIVER is not set |
| 618 | CONFIG_DEVPORT=y | 668 | CONFIG_DEVPORT=y |
| 619 | # CONFIG_I2C is not set | 669 | # CONFIG_I2C is not set |
| 620 | |||
| 621 | # | ||
| 622 | # SPI support | ||
| 623 | # | ||
| 624 | # CONFIG_SPI is not set | 670 | # CONFIG_SPI is not set |
| 625 | # CONFIG_SPI_MASTER is not set | ||
| 626 | # CONFIG_W1 is not set | 671 | # CONFIG_W1 is not set |
| 627 | # CONFIG_POWER_SUPPLY is not set | 672 | # CONFIG_POWER_SUPPLY is not set |
| 628 | # CONFIG_HWMON is not set | 673 | # CONFIG_HWMON is not set |
| 674 | # CONFIG_THERMAL is not set | ||
| 675 | # CONFIG_THERMAL_HWMON is not set | ||
| 676 | # CONFIG_WATCHDOG is not set | ||
| 677 | CONFIG_SSB_POSSIBLE=y | ||
| 629 | 678 | ||
| 630 | # | 679 | # |
| 631 | # Sonics Silicon Backplane | 680 | # Sonics Silicon Backplane |
| 632 | # | 681 | # |
| 633 | CONFIG_SSB_POSSIBLE=y | ||
| 634 | # CONFIG_SSB is not set | 682 | # CONFIG_SSB is not set |
| 635 | 683 | ||
| 636 | # | 684 | # |
| 637 | # Multifunction device drivers | 685 | # Multifunction device drivers |
| 638 | # | 686 | # |
| 687 | # CONFIG_MFD_CORE is not set | ||
| 639 | # CONFIG_MFD_SM501 is not set | 688 | # CONFIG_MFD_SM501 is not set |
| 689 | # CONFIG_HTC_PASIC3 is not set | ||
| 690 | # CONFIG_MFD_TMIO is not set | ||
| 691 | # CONFIG_REGULATOR is not set | ||
| 640 | 692 | ||
| 641 | # | 693 | # |
| 642 | # Multimedia devices | 694 | # Multimedia devices |
| 643 | # | 695 | # |
| 696 | |||
| 697 | # | ||
| 698 | # Multimedia core support | ||
| 699 | # | ||
| 644 | # CONFIG_VIDEO_DEV is not set | 700 | # CONFIG_VIDEO_DEV is not set |
| 645 | # CONFIG_DVB_CORE is not set | 701 | # CONFIG_DVB_CORE is not set |
| 646 | # CONFIG_DAB is not set | 702 | # CONFIG_VIDEO_MEDIA is not set |
| 647 | 703 | ||
| 648 | # | 704 | # |
| 649 | # Graphics support | 705 | # Multimedia drivers |
| 650 | # | 706 | # |
| 651 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 707 | # CONFIG_DAB is not set |
| 652 | 708 | ||
| 653 | # | 709 | # |
| 654 | # Display device support | 710 | # Graphics support |
| 655 | # | 711 | # |
| 656 | # CONFIG_DISPLAY_SUPPORT is not set | 712 | # CONFIG_AGP is not set |
| 713 | # CONFIG_DRM is not set | ||
| 657 | # CONFIG_VGASTATE is not set | 714 | # CONFIG_VGASTATE is not set |
| 658 | CONFIG_VIDEO_OUTPUT_CONTROL=m | 715 | CONFIG_VIDEO_OUTPUT_CONTROL=m |
| 659 | CONFIG_FB=y | 716 | CONFIG_FB=y |
| 660 | # CONFIG_FIRMWARE_EDID is not set | 717 | # CONFIG_FIRMWARE_EDID is not set |
| 661 | # CONFIG_FB_DDC is not set | 718 | # CONFIG_FB_DDC is not set |
| 719 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 662 | CONFIG_FB_CFB_FILLRECT=y | 720 | CONFIG_FB_CFB_FILLRECT=y |
| 663 | CONFIG_FB_CFB_COPYAREA=y | 721 | CONFIG_FB_CFB_COPYAREA=y |
| 664 | CONFIG_FB_CFB_IMAGEBLIT=y | 722 | CONFIG_FB_CFB_IMAGEBLIT=y |
| 723 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 665 | # CONFIG_FB_SYS_FILLRECT is not set | 724 | # CONFIG_FB_SYS_FILLRECT is not set |
| 666 | # CONFIG_FB_SYS_COPYAREA is not set | 725 | # CONFIG_FB_SYS_COPYAREA is not set |
| 667 | # CONFIG_FB_SYS_IMAGEBLIT is not set | 726 | # CONFIG_FB_SYS_IMAGEBLIT is not set |
| 727 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 668 | # CONFIG_FB_SYS_FOPS is not set | 728 | # CONFIG_FB_SYS_FOPS is not set |
| 669 | CONFIG_FB_DEFERRED_IO=y | ||
| 670 | # CONFIG_FB_SVGALIB is not set | 729 | # CONFIG_FB_SVGALIB is not set |
| 671 | # CONFIG_FB_MACMODES is not set | 730 | # CONFIG_FB_MACMODES is not set |
| 672 | # CONFIG_FB_BACKLIGHT is not set | 731 | # CONFIG_FB_BACKLIGHT is not set |
| @@ -691,6 +750,7 @@ CONFIG_FB_STI=y | |||
| 691 | # CONFIG_FB_ATY is not set | 750 | # CONFIG_FB_ATY is not set |
| 692 | # CONFIG_FB_S3 is not set | 751 | # CONFIG_FB_S3 is not set |
| 693 | # CONFIG_FB_SIS is not set | 752 | # CONFIG_FB_SIS is not set |
| 753 | # CONFIG_FB_VIA is not set | ||
| 694 | # CONFIG_FB_NEOMAGIC is not set | 754 | # CONFIG_FB_NEOMAGIC is not set |
| 695 | # CONFIG_FB_KYRO is not set | 755 | # CONFIG_FB_KYRO is not set |
| 696 | # CONFIG_FB_3DFX is not set | 756 | # CONFIG_FB_3DFX is not set |
| @@ -698,7 +758,16 @@ CONFIG_FB_STI=y | |||
| 698 | # CONFIG_FB_VT8623 is not set | 758 | # CONFIG_FB_VT8623 is not set |
| 699 | # CONFIG_FB_TRIDENT is not set | 759 | # CONFIG_FB_TRIDENT is not set |
| 700 | # CONFIG_FB_ARK is not set | 760 | # CONFIG_FB_ARK is not set |
| 761 | # CONFIG_FB_CARMINE is not set | ||
| 701 | # CONFIG_FB_VIRTUAL is not set | 762 | # CONFIG_FB_VIRTUAL is not set |
| 763 | # CONFIG_FB_METRONOME is not set | ||
| 764 | # CONFIG_FB_MB862XX is not set | ||
| 765 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 766 | |||
| 767 | # | ||
| 768 | # Display device support | ||
| 769 | # | ||
| 770 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 702 | 771 | ||
| 703 | # | 772 | # |
| 704 | # Console display driver support | 773 | # Console display driver support |
| @@ -718,15 +787,8 @@ CONFIG_LOGO_LINUX_MONO=y | |||
| 718 | CONFIG_LOGO_LINUX_VGA16=y | 787 | CONFIG_LOGO_LINUX_VGA16=y |
| 719 | CONFIG_LOGO_LINUX_CLUT224=y | 788 | CONFIG_LOGO_LINUX_CLUT224=y |
| 720 | CONFIG_LOGO_PARISC_CLUT224=y | 789 | CONFIG_LOGO_PARISC_CLUT224=y |
| 721 | |||
| 722 | # | ||
| 723 | # Sound | ||
| 724 | # | ||
| 725 | CONFIG_SOUND=y | 790 | CONFIG_SOUND=y |
| 726 | 791 | CONFIG_SOUND_OSS_CORE=y | |
| 727 | # | ||
| 728 | # Advanced Linux Sound Architecture | ||
| 729 | # | ||
| 730 | CONFIG_SND=y | 792 | CONFIG_SND=y |
| 731 | CONFIG_SND_TIMER=y | 793 | CONFIG_SND_TIMER=y |
| 732 | CONFIG_SND_PCM=y | 794 | CONFIG_SND_PCM=y |
| @@ -742,10 +804,7 @@ CONFIG_SND_SUPPORT_OLD_API=y | |||
| 742 | CONFIG_SND_VERBOSE_PROCFS=y | 804 | CONFIG_SND_VERBOSE_PROCFS=y |
| 743 | # CONFIG_SND_VERBOSE_PRINTK is not set | 805 | # CONFIG_SND_VERBOSE_PRINTK is not set |
| 744 | # CONFIG_SND_DEBUG is not set | 806 | # CONFIG_SND_DEBUG is not set |
| 745 | 807 | CONFIG_SND_DRIVERS=y | |
| 746 | # | ||
| 747 | # Generic devices | ||
| 748 | # | ||
| 749 | # CONFIG_SND_DUMMY is not set | 808 | # CONFIG_SND_DUMMY is not set |
| 750 | # CONFIG_SND_VIRMIDI is not set | 809 | # CONFIG_SND_VIRMIDI is not set |
| 751 | # CONFIG_SND_MTPAV is not set | 810 | # CONFIG_SND_MTPAV is not set |
| @@ -753,10 +812,7 @@ CONFIG_SND_VERBOSE_PROCFS=y | |||
| 753 | # CONFIG_SND_SERIAL_U16550 is not set | 812 | # CONFIG_SND_SERIAL_U16550 is not set |
| 754 | # CONFIG_SND_MPU401 is not set | 813 | # CONFIG_SND_MPU401 is not set |
| 755 | # CONFIG_SND_PORTMAN2X4 is not set | 814 | # CONFIG_SND_PORTMAN2X4 is not set |
| 756 | 815 | CONFIG_SND_PCI=y | |
| 757 | # | ||
| 758 | # PCI devices | ||
| 759 | # | ||
| 760 | # CONFIG_SND_AD1889 is not set | 816 | # CONFIG_SND_AD1889 is not set |
| 761 | # CONFIG_SND_ALS300 is not set | 817 | # CONFIG_SND_ALS300 is not set |
| 762 | # CONFIG_SND_ALI5451 is not set | 818 | # CONFIG_SND_ALI5451 is not set |
| @@ -765,9 +821,11 @@ CONFIG_SND_VERBOSE_PROCFS=y | |||
| 765 | # CONFIG_SND_AU8810 is not set | 821 | # CONFIG_SND_AU8810 is not set |
| 766 | # CONFIG_SND_AU8820 is not set | 822 | # CONFIG_SND_AU8820 is not set |
| 767 | # CONFIG_SND_AU8830 is not set | 823 | # CONFIG_SND_AU8830 is not set |
| 824 | # CONFIG_SND_AW2 is not set | ||
| 768 | # CONFIG_SND_BT87X is not set | 825 | # CONFIG_SND_BT87X is not set |
| 769 | # CONFIG_SND_CA0106 is not set | 826 | # CONFIG_SND_CA0106 is not set |
| 770 | # CONFIG_SND_CMIPCI is not set | 827 | # CONFIG_SND_CMIPCI is not set |
| 828 | # CONFIG_SND_OXYGEN is not set | ||
| 771 | # CONFIG_SND_CS4281 is not set | 829 | # CONFIG_SND_CS4281 is not set |
| 772 | # CONFIG_SND_CS46XX is not set | 830 | # CONFIG_SND_CS46XX is not set |
| 773 | # CONFIG_SND_DARLA20 is not set | 831 | # CONFIG_SND_DARLA20 is not set |
| @@ -792,6 +850,7 @@ CONFIG_SND_VERBOSE_PROCFS=y | |||
| 792 | # CONFIG_SND_HDA_INTEL is not set | 850 | # CONFIG_SND_HDA_INTEL is not set |
| 793 | # CONFIG_SND_HDSP is not set | 851 | # CONFIG_SND_HDSP is not set |
| 794 | # CONFIG_SND_HDSPM is not set | 852 | # CONFIG_SND_HDSPM is not set |
| 853 | # CONFIG_SND_HIFIER is not set | ||
| 795 | # CONFIG_SND_ICE1712 is not set | 854 | # CONFIG_SND_ICE1712 is not set |
| 796 | # CONFIG_SND_ICE1724 is not set | 855 | # CONFIG_SND_ICE1724 is not set |
| 797 | # CONFIG_SND_INTEL8X0 is not set | 856 | # CONFIG_SND_INTEL8X0 is not set |
| @@ -809,30 +868,23 @@ CONFIG_SND_VERBOSE_PROCFS=y | |||
| 809 | # CONFIG_SND_TRIDENT is not set | 868 | # CONFIG_SND_TRIDENT is not set |
| 810 | # CONFIG_SND_VIA82XX is not set | 869 | # CONFIG_SND_VIA82XX is not set |
| 811 | # CONFIG_SND_VIA82XX_MODEM is not set | 870 | # CONFIG_SND_VIA82XX_MODEM is not set |
| 871 | # CONFIG_SND_VIRTUOSO is not set | ||
| 812 | # CONFIG_SND_VX222 is not set | 872 | # CONFIG_SND_VX222 is not set |
| 813 | # CONFIG_SND_YMFPCI is not set | 873 | # CONFIG_SND_YMFPCI is not set |
| 814 | 874 | CONFIG_SND_GSC=y | |
| 815 | # | ||
| 816 | # GSC devices | ||
| 817 | # | ||
| 818 | CONFIG_SND_HARMONY=y | 875 | CONFIG_SND_HARMONY=y |
| 819 | |||
| 820 | # | ||
| 821 | # System on Chip audio support | ||
| 822 | # | ||
| 823 | # CONFIG_SND_SOC is not set | 876 | # CONFIG_SND_SOC is not set |
| 824 | |||
| 825 | # | ||
| 826 | # SoC Audio support for SuperH | ||
| 827 | # | ||
| 828 | |||
| 829 | # | ||
| 830 | # Open Sound System | ||
| 831 | # | ||
| 832 | # CONFIG_SOUND_PRIME is not set | 877 | # CONFIG_SOUND_PRIME is not set |
| 833 | CONFIG_HID_SUPPORT=y | 878 | CONFIG_HID_SUPPORT=y |
| 834 | CONFIG_HID=y | 879 | CONFIG_HID=y |
| 835 | CONFIG_HID_DEBUG=y | 880 | CONFIG_HID_DEBUG=y |
| 881 | # CONFIG_HIDRAW is not set | ||
| 882 | # CONFIG_HID_PID is not set | ||
| 883 | |||
| 884 | # | ||
| 885 | # Special HID drivers | ||
| 886 | # | ||
| 887 | CONFIG_HID_COMPAT=y | ||
| 836 | CONFIG_USB_SUPPORT=y | 888 | CONFIG_USB_SUPPORT=y |
| 837 | CONFIG_USB_ARCH_HAS_HCD=y | 889 | CONFIG_USB_ARCH_HAS_HCD=y |
| 838 | CONFIG_USB_ARCH_HAS_OHCI=y | 890 | CONFIG_USB_ARCH_HAS_OHCI=y |
| @@ -840,36 +892,63 @@ CONFIG_USB_ARCH_HAS_EHCI=y | |||
| 840 | # CONFIG_USB is not set | 892 | # CONFIG_USB is not set |
| 841 | 893 | ||
| 842 | # | 894 | # |
| 843 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 895 | # Enable Host or Gadget support to see Inventra options |
| 844 | # | 896 | # |
| 845 | 897 | ||
| 846 | # | 898 | # |
| 847 | # USB Gadget Support | 899 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; |
| 848 | # | 900 | # |
| 849 | # CONFIG_USB_GADGET is not set | 901 | # CONFIG_USB_GADGET is not set |
| 902 | |||
| 903 | # | ||
| 904 | # OTG and related infrastructure | ||
| 905 | # | ||
| 850 | # CONFIG_MMC is not set | 906 | # CONFIG_MMC is not set |
| 907 | # CONFIG_MEMSTICK is not set | ||
| 851 | # CONFIG_NEW_LEDS is not set | 908 | # CONFIG_NEW_LEDS is not set |
| 909 | # CONFIG_ACCESSIBILITY is not set | ||
| 852 | # CONFIG_INFINIBAND is not set | 910 | # CONFIG_INFINIBAND is not set |
| 853 | # CONFIG_RTC_CLASS is not set | 911 | CONFIG_RTC_LIB=y |
| 912 | CONFIG_RTC_CLASS=y | ||
| 913 | CONFIG_RTC_HCTOSYS=y | ||
| 914 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 915 | # CONFIG_RTC_DEBUG is not set | ||
| 854 | 916 | ||
| 855 | # | 917 | # |
| 856 | # DMA Engine support | 918 | # RTC interfaces |
| 857 | # | 919 | # |
| 858 | # CONFIG_DMA_ENGINE is not set | 920 | CONFIG_RTC_INTF_SYSFS=y |
| 921 | CONFIG_RTC_INTF_PROC=y | ||
| 922 | CONFIG_RTC_INTF_DEV=y | ||
| 923 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 924 | # CONFIG_RTC_DRV_TEST is not set | ||
| 859 | 925 | ||
| 860 | # | 926 | # |
| 861 | # DMA Clients | 927 | # SPI RTC drivers |
| 862 | # | 928 | # |
| 863 | 929 | ||
| 864 | # | 930 | # |
| 865 | # DMA Devices | 931 | # Platform RTC drivers |
| 866 | # | 932 | # |
| 867 | # CONFIG_AUXDISPLAY is not set | 933 | # CONFIG_RTC_DRV_DS1286 is not set |
| 934 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 935 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 936 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 937 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 938 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 939 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 940 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 941 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 942 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 868 | 943 | ||
| 869 | # | 944 | # |
| 870 | # Userspace I/O | 945 | # on-CPU RTC drivers |
| 871 | # | 946 | # |
| 947 | CONFIG_RTC_DRV_PARISC=y | ||
| 948 | # CONFIG_DMADEVICES is not set | ||
| 949 | # CONFIG_AUXDISPLAY is not set | ||
| 872 | # CONFIG_UIO is not set | 950 | # CONFIG_UIO is not set |
| 951 | # CONFIG_STAGING is not set | ||
| 873 | 952 | ||
| 874 | # | 953 | # |
| 875 | # File systems | 954 | # File systems |
| @@ -879,19 +958,18 @@ CONFIG_EXT2_FS=y | |||
| 879 | # CONFIG_EXT2_FS_XIP is not set | 958 | # CONFIG_EXT2_FS_XIP is not set |
| 880 | CONFIG_EXT3_FS=y | 959 | CONFIG_EXT3_FS=y |
| 881 | # CONFIG_EXT3_FS_XATTR is not set | 960 | # CONFIG_EXT3_FS_XATTR is not set |
| 961 | # CONFIG_EXT4_FS is not set | ||
| 882 | CONFIG_JBD=y | 962 | CONFIG_JBD=y |
| 883 | # CONFIG_JBD_DEBUG is not set | ||
| 884 | # CONFIG_REISERFS_FS is not set | 963 | # CONFIG_REISERFS_FS is not set |
| 885 | # CONFIG_JFS_FS is not set | 964 | # CONFIG_JFS_FS is not set |
| 886 | # CONFIG_FS_POSIX_ACL is not set | 965 | # CONFIG_FS_POSIX_ACL is not set |
| 966 | CONFIG_FILE_LOCKING=y | ||
| 887 | # CONFIG_XFS_FS is not set | 967 | # CONFIG_XFS_FS is not set |
| 888 | # CONFIG_OCFS2_FS is not set | 968 | # CONFIG_OCFS2_FS is not set |
| 889 | # CONFIG_MINIX_FS is not set | 969 | CONFIG_DNOTIFY=y |
| 890 | # CONFIG_ROMFS_FS is not set | ||
| 891 | CONFIG_INOTIFY=y | 970 | CONFIG_INOTIFY=y |
| 892 | CONFIG_INOTIFY_USER=y | 971 | CONFIG_INOTIFY_USER=y |
| 893 | # CONFIG_QUOTA is not set | 972 | # CONFIG_QUOTA is not set |
| 894 | CONFIG_DNOTIFY=y | ||
| 895 | # CONFIG_AUTOFS_FS is not set | 973 | # CONFIG_AUTOFS_FS is not set |
| 896 | CONFIG_AUTOFS4_FS=y | 974 | CONFIG_AUTOFS4_FS=y |
| 897 | # CONFIG_FUSE_FS is not set | 975 | # CONFIG_FUSE_FS is not set |
| @@ -917,35 +995,32 @@ CONFIG_JOLIET=y | |||
| 917 | CONFIG_PROC_FS=y | 995 | CONFIG_PROC_FS=y |
| 918 | CONFIG_PROC_KCORE=y | 996 | CONFIG_PROC_KCORE=y |
| 919 | CONFIG_PROC_SYSCTL=y | 997 | CONFIG_PROC_SYSCTL=y |
| 998 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 920 | CONFIG_SYSFS=y | 999 | CONFIG_SYSFS=y |
| 921 | CONFIG_TMPFS=y | 1000 | CONFIG_TMPFS=y |
| 922 | # CONFIG_TMPFS_POSIX_ACL is not set | 1001 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 923 | # CONFIG_HUGETLB_PAGE is not set | 1002 | # CONFIG_HUGETLB_PAGE is not set |
| 924 | CONFIG_RAMFS=y | 1003 | # CONFIG_CONFIGFS_FS is not set |
| 925 | 1004 | CONFIG_MISC_FILESYSTEMS=y | |
| 926 | # | ||
| 927 | # Miscellaneous filesystems | ||
| 928 | # | ||
| 929 | # CONFIG_HFSPLUS_FS is not set | 1005 | # CONFIG_HFSPLUS_FS is not set |
| 930 | # CONFIG_CRAMFS is not set | 1006 | # CONFIG_CRAMFS is not set |
| 1007 | # CONFIG_SQUASHFS is not set | ||
| 931 | # CONFIG_VXFS_FS is not set | 1008 | # CONFIG_VXFS_FS is not set |
| 1009 | # CONFIG_MINIX_FS is not set | ||
| 1010 | # CONFIG_OMFS_FS is not set | ||
| 932 | # CONFIG_HPFS_FS is not set | 1011 | # CONFIG_HPFS_FS is not set |
| 933 | # CONFIG_QNX4FS_FS is not set | 1012 | # CONFIG_QNX4FS_FS is not set |
| 1013 | # CONFIG_ROMFS_FS is not set | ||
| 934 | # CONFIG_SYSV_FS is not set | 1014 | # CONFIG_SYSV_FS is not set |
| 935 | # CONFIG_UFS_FS is not set | 1015 | # CONFIG_UFS_FS is not set |
| 936 | 1016 | CONFIG_NETWORK_FILESYSTEMS=y | |
| 937 | # | ||
| 938 | # Network File Systems | ||
| 939 | # | ||
| 940 | CONFIG_NFS_FS=y | 1017 | CONFIG_NFS_FS=y |
| 941 | CONFIG_NFS_V3=y | 1018 | CONFIG_NFS_V3=y |
| 942 | # CONFIG_NFS_V3_ACL is not set | 1019 | # CONFIG_NFS_V3_ACL is not set |
| 943 | # CONFIG_NFS_DIRECTIO is not set | 1020 | CONFIG_ROOT_NFS=y |
| 944 | CONFIG_NFSD=y | 1021 | CONFIG_NFSD=y |
| 945 | CONFIG_NFSD_V3=y | 1022 | CONFIG_NFSD_V3=y |
| 946 | # CONFIG_NFSD_V3_ACL is not set | 1023 | # CONFIG_NFSD_V3_ACL is not set |
| 947 | CONFIG_NFSD_TCP=y | ||
| 948 | CONFIG_ROOT_NFS=y | ||
| 949 | CONFIG_LOCKD=y | 1024 | CONFIG_LOCKD=y |
| 950 | CONFIG_LOCKD_V4=y | 1025 | CONFIG_LOCKD_V4=y |
| 951 | CONFIG_EXPORTFS=y | 1026 | CONFIG_EXPORTFS=y |
| @@ -962,10 +1037,6 @@ CONFIG_SMB_FS=y | |||
| 962 | # | 1037 | # |
| 963 | # CONFIG_PARTITION_ADVANCED is not set | 1038 | # CONFIG_PARTITION_ADVANCED is not set |
| 964 | CONFIG_MSDOS_PARTITION=y | 1039 | CONFIG_MSDOS_PARTITION=y |
| 965 | |||
| 966 | # | ||
| 967 | # Native Language Support | ||
| 968 | # | ||
| 969 | CONFIG_NLS=y | 1040 | CONFIG_NLS=y |
| 970 | CONFIG_NLS_DEFAULT="iso8859-1" | 1041 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 971 | CONFIG_NLS_CODEPAGE_437=m | 1042 | CONFIG_NLS_CODEPAGE_437=m |
| @@ -1011,7 +1082,9 @@ CONFIG_NLS_UTF8=m | |||
| 1011 | # Kernel hacking | 1082 | # Kernel hacking |
| 1012 | # | 1083 | # |
| 1013 | # CONFIG_PRINTK_TIME is not set | 1084 | # CONFIG_PRINTK_TIME is not set |
| 1085 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1014 | CONFIG_ENABLE_MUST_CHECK=y | 1086 | CONFIG_ENABLE_MUST_CHECK=y |
| 1087 | CONFIG_FRAME_WARN=1024 | ||
| 1015 | CONFIG_MAGIC_SYSRQ=y | 1088 | CONFIG_MAGIC_SYSRQ=y |
| 1016 | # CONFIG_UNUSED_SYMBOLS is not set | 1089 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1017 | # CONFIG_DEBUG_FS is not set | 1090 | # CONFIG_DEBUG_FS is not set |
| @@ -1019,9 +1092,12 @@ CONFIG_HEADERS_CHECK=y | |||
| 1019 | CONFIG_DEBUG_KERNEL=y | 1092 | CONFIG_DEBUG_KERNEL=y |
| 1020 | # CONFIG_DEBUG_SHIRQ is not set | 1093 | # CONFIG_DEBUG_SHIRQ is not set |
| 1021 | CONFIG_DETECT_SOFTLOCKUP=y | 1094 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1095 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1096 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1022 | CONFIG_SCHED_DEBUG=y | 1097 | CONFIG_SCHED_DEBUG=y |
| 1023 | # CONFIG_SCHEDSTATS is not set | 1098 | # CONFIG_SCHEDSTATS is not set |
| 1024 | # CONFIG_TIMER_STATS is not set | 1099 | # CONFIG_TIMER_STATS is not set |
| 1100 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1025 | # CONFIG_DEBUG_SLAB is not set | 1101 | # CONFIG_DEBUG_SLAB is not set |
| 1026 | # CONFIG_DEBUG_RT_MUTEXES is not set | 1102 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| 1027 | # CONFIG_RT_MUTEX_TESTER is not set | 1103 | # CONFIG_RT_MUTEX_TESTER is not set |
| @@ -1033,10 +1109,29 @@ CONFIG_SCHED_DEBUG=y | |||
| 1033 | CONFIG_DEBUG_BUGVERBOSE=y | 1109 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1034 | # CONFIG_DEBUG_INFO is not set | 1110 | # CONFIG_DEBUG_INFO is not set |
| 1035 | # CONFIG_DEBUG_VM is not set | 1111 | # CONFIG_DEBUG_VM is not set |
| 1112 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1113 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 1036 | # CONFIG_DEBUG_LIST is not set | 1114 | # CONFIG_DEBUG_LIST is not set |
| 1037 | CONFIG_FORCED_INLINING=y | 1115 | # CONFIG_DEBUG_SG is not set |
| 1116 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1117 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1038 | # CONFIG_RCU_TORTURE_TEST is not set | 1118 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1119 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1120 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1121 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1039 | # CONFIG_FAULT_INJECTION is not set | 1122 | # CONFIG_FAULT_INJECTION is not set |
| 1123 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1124 | |||
| 1125 | # | ||
| 1126 | # Tracers | ||
| 1127 | # | ||
| 1128 | # CONFIG_SCHED_TRACER is not set | ||
| 1129 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1130 | # CONFIG_BOOT_TRACER is not set | ||
| 1131 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1132 | # CONFIG_BUILD_DOCSRC is not set | ||
| 1133 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1134 | # CONFIG_SAMPLES is not set | ||
| 1040 | # CONFIG_DEBUG_RODATA is not set | 1135 | # CONFIG_DEBUG_RODATA is not set |
| 1041 | 1136 | ||
| 1042 | # | 1137 | # |
| @@ -1044,52 +1139,108 @@ CONFIG_FORCED_INLINING=y | |||
| 1044 | # | 1139 | # |
| 1045 | # CONFIG_KEYS is not set | 1140 | # CONFIG_KEYS is not set |
| 1046 | CONFIG_SECURITY=y | 1141 | CONFIG_SECURITY=y |
| 1142 | # CONFIG_SECURITYFS is not set | ||
| 1047 | # CONFIG_SECURITY_NETWORK is not set | 1143 | # CONFIG_SECURITY_NETWORK is not set |
| 1048 | CONFIG_SECURITY_CAPABILITIES=y | 1144 | # CONFIG_SECURITY_PATH is not set |
| 1145 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1146 | CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0 | ||
| 1049 | CONFIG_CRYPTO=y | 1147 | CONFIG_CRYPTO=y |
| 1148 | |||
| 1149 | # | ||
| 1150 | # Crypto core or helper | ||
| 1151 | # | ||
| 1152 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1050 | CONFIG_CRYPTO_ALGAPI=y | 1153 | CONFIG_CRYPTO_ALGAPI=y |
| 1154 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1155 | CONFIG_CRYPTO_AEAD2=y | ||
| 1051 | CONFIG_CRYPTO_BLKCIPHER=y | 1156 | CONFIG_CRYPTO_BLKCIPHER=y |
| 1157 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1158 | CONFIG_CRYPTO_HASH2=y | ||
| 1159 | CONFIG_CRYPTO_RNG2=y | ||
| 1052 | CONFIG_CRYPTO_MANAGER=y | 1160 | CONFIG_CRYPTO_MANAGER=y |
| 1053 | # CONFIG_CRYPTO_HMAC is not set | 1161 | CONFIG_CRYPTO_MANAGER2=y |
| 1054 | # CONFIG_CRYPTO_NULL is not set | 1162 | # CONFIG_CRYPTO_NULL is not set |
| 1163 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1164 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1165 | # CONFIG_CRYPTO_TEST is not set | ||
| 1166 | |||
| 1167 | # | ||
| 1168 | # Authenticated Encryption with Associated Data | ||
| 1169 | # | ||
| 1170 | # CONFIG_CRYPTO_CCM is not set | ||
| 1171 | # CONFIG_CRYPTO_GCM is not set | ||
| 1172 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1173 | |||
| 1174 | # | ||
| 1175 | # Block modes | ||
| 1176 | # | ||
| 1177 | CONFIG_CRYPTO_CBC=y | ||
| 1178 | # CONFIG_CRYPTO_CTR is not set | ||
| 1179 | # CONFIG_CRYPTO_CTS is not set | ||
| 1180 | # CONFIG_CRYPTO_ECB is not set | ||
| 1181 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1182 | |||
| 1183 | # | ||
| 1184 | # Hash modes | ||
| 1185 | # | ||
| 1186 | # CONFIG_CRYPTO_HMAC is not set | ||
| 1187 | |||
| 1188 | # | ||
| 1189 | # Digest | ||
| 1190 | # | ||
| 1191 | # CONFIG_CRYPTO_CRC32C is not set | ||
| 1055 | # CONFIG_CRYPTO_MD4 is not set | 1192 | # CONFIG_CRYPTO_MD4 is not set |
| 1056 | # CONFIG_CRYPTO_MD5 is not set | 1193 | # CONFIG_CRYPTO_MD5 is not set |
| 1194 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1195 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1196 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1197 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1198 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1057 | # CONFIG_CRYPTO_SHA1 is not set | 1199 | # CONFIG_CRYPTO_SHA1 is not set |
| 1058 | # CONFIG_CRYPTO_SHA256 is not set | 1200 | # CONFIG_CRYPTO_SHA256 is not set |
| 1059 | # CONFIG_CRYPTO_SHA512 is not set | 1201 | # CONFIG_CRYPTO_SHA512 is not set |
| 1060 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1061 | # CONFIG_CRYPTO_TGR192 is not set | 1202 | # CONFIG_CRYPTO_TGR192 is not set |
| 1062 | # CONFIG_CRYPTO_ECB is not set | 1203 | # CONFIG_CRYPTO_WP512 is not set |
| 1063 | CONFIG_CRYPTO_CBC=y | 1204 | |
| 1064 | # CONFIG_CRYPTO_PCBC is not set | 1205 | # |
| 1065 | # CONFIG_CRYPTO_CRYPTD is not set | 1206 | # Ciphers |
| 1066 | # CONFIG_CRYPTO_DES is not set | 1207 | # |
| 1067 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1068 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1069 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1070 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1071 | # CONFIG_CRYPTO_AES is not set | 1208 | # CONFIG_CRYPTO_AES is not set |
| 1209 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1210 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1211 | # CONFIG_CRYPTO_BLOWFISH is not set | ||
| 1212 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1072 | # CONFIG_CRYPTO_CAST5 is not set | 1213 | # CONFIG_CRYPTO_CAST5 is not set |
| 1073 | # CONFIG_CRYPTO_CAST6 is not set | 1214 | # CONFIG_CRYPTO_CAST6 is not set |
| 1074 | # CONFIG_CRYPTO_TEA is not set | 1215 | # CONFIG_CRYPTO_DES is not set |
| 1075 | # CONFIG_CRYPTO_ARC4 is not set | 1216 | # CONFIG_CRYPTO_FCRYPT is not set |
| 1076 | # CONFIG_CRYPTO_KHAZAD is not set | 1217 | # CONFIG_CRYPTO_KHAZAD is not set |
| 1077 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1078 | # CONFIG_CRYPTO_SEED is not set | 1218 | # CONFIG_CRYPTO_SEED is not set |
| 1219 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1220 | # CONFIG_CRYPTO_TEA is not set | ||
| 1221 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1222 | |||
| 1223 | # | ||
| 1224 | # Compression | ||
| 1225 | # | ||
| 1079 | # CONFIG_CRYPTO_DEFLATE is not set | 1226 | # CONFIG_CRYPTO_DEFLATE is not set |
| 1080 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | 1227 | # CONFIG_CRYPTO_LZO is not set |
| 1081 | # CONFIG_CRYPTO_CRC32C is not set | 1228 | |
| 1082 | # CONFIG_CRYPTO_CAMELLIA is not set | 1229 | # |
| 1083 | # CONFIG_CRYPTO_TEST is not set | 1230 | # Random Number Generation |
| 1084 | # CONFIG_CRYPTO_AUTHENC is not set | 1231 | # |
| 1232 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1085 | CONFIG_CRYPTO_HW=y | 1233 | CONFIG_CRYPTO_HW=y |
| 1234 | # CONFIG_CRYPTO_DEV_HIFN_795X is not set | ||
| 1086 | 1235 | ||
| 1087 | # | 1236 | # |
| 1088 | # Library routines | 1237 | # Library routines |
| 1089 | # | 1238 | # |
| 1090 | CONFIG_BITREVERSE=y | 1239 | CONFIG_BITREVERSE=y |
| 1240 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1091 | # CONFIG_CRC_CCITT is not set | 1241 | # CONFIG_CRC_CCITT is not set |
| 1092 | # CONFIG_CRC16 is not set | 1242 | # CONFIG_CRC16 is not set |
| 1243 | # CONFIG_CRC_T10DIF is not set | ||
| 1093 | # CONFIG_CRC_ITU_T is not set | 1244 | # CONFIG_CRC_ITU_T is not set |
| 1094 | CONFIG_CRC32=y | 1245 | CONFIG_CRC32=y |
| 1095 | # CONFIG_CRC7 is not set | 1246 | # CONFIG_CRC7 is not set |
diff --git a/arch/parisc/configs/c3000_defconfig b/arch/parisc/configs/c3000_defconfig index c6def3c1d209..0aa8014f758c 100644 --- a/arch/parisc/configs/c3000_defconfig +++ b/arch/parisc/configs/c3000_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.23 | 3 | # Linux kernel version: 2.6.29-rc8 |
| 4 | # Fri Oct 12 21:24:00 2007 | 4 | # Fri Mar 13 01:32:58 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_PARISC=y | 6 | CONFIG_PARISC=y |
| 7 | CONFIG_MMU=y | 7 | CONFIG_MMU=y |
| @@ -33,16 +33,29 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 33 | # CONFIG_POSIX_MQUEUE is not set | 33 | # CONFIG_POSIX_MQUEUE is not set |
| 34 | # CONFIG_BSD_PROCESS_ACCT is not set | 34 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 35 | # CONFIG_TASKSTATS is not set | 35 | # CONFIG_TASKSTATS is not set |
| 36 | # CONFIG_USER_NS is not set | ||
| 37 | # CONFIG_AUDIT is not set | 36 | # CONFIG_AUDIT is not set |
| 37 | |||
| 38 | # | ||
| 39 | # RCU Subsystem | ||
| 40 | # | ||
| 41 | CONFIG_CLASSIC_RCU=y | ||
| 42 | # CONFIG_TREE_RCU is not set | ||
| 43 | # CONFIG_PREEMPT_RCU is not set | ||
| 44 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 45 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 38 | CONFIG_IKCONFIG=y | 46 | CONFIG_IKCONFIG=y |
| 39 | CONFIG_IKCONFIG_PROC=y | 47 | CONFIG_IKCONFIG_PROC=y |
| 40 | CONFIG_LOG_BUF_SHIFT=16 | 48 | CONFIG_LOG_BUF_SHIFT=16 |
| 49 | # CONFIG_GROUP_SCHED is not set | ||
| 50 | # CONFIG_CGROUPS is not set | ||
| 41 | CONFIG_SYSFS_DEPRECATED=y | 51 | CONFIG_SYSFS_DEPRECATED=y |
| 52 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 42 | # CONFIG_RELAY is not set | 53 | # CONFIG_RELAY is not set |
| 54 | # CONFIG_NAMESPACES is not set | ||
| 43 | # CONFIG_BLK_DEV_INITRD is not set | 55 | # CONFIG_BLK_DEV_INITRD is not set |
| 44 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set | 56 | # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set |
| 45 | CONFIG_SYSCTL=y | 57 | CONFIG_SYSCTL=y |
| 58 | CONFIG_ANON_INODES=y | ||
| 46 | CONFIG_EMBEDDED=y | 59 | CONFIG_EMBEDDED=y |
| 47 | CONFIG_SYSCTL_SYSCALL=y | 60 | CONFIG_SYSCTL_SYSCALL=y |
| 48 | CONFIG_KALLSYMS=y | 61 | CONFIG_KALLSYMS=y |
| @@ -54,29 +67,39 @@ CONFIG_BUG=y | |||
| 54 | CONFIG_ELF_CORE=y | 67 | CONFIG_ELF_CORE=y |
| 55 | CONFIG_BASE_FULL=y | 68 | CONFIG_BASE_FULL=y |
| 56 | CONFIG_FUTEX=y | 69 | CONFIG_FUTEX=y |
| 57 | CONFIG_ANON_INODES=y | ||
| 58 | CONFIG_EPOLL=y | 70 | CONFIG_EPOLL=y |
| 59 | CONFIG_SIGNALFD=y | 71 | CONFIG_SIGNALFD=y |
| 72 | CONFIG_TIMERFD=y | ||
| 60 | CONFIG_EVENTFD=y | 73 | CONFIG_EVENTFD=y |
| 61 | CONFIG_SHMEM=y | 74 | CONFIG_SHMEM=y |
| 75 | CONFIG_AIO=y | ||
| 62 | CONFIG_VM_EVENT_COUNTERS=y | 76 | CONFIG_VM_EVENT_COUNTERS=y |
| 77 | CONFIG_PCI_QUIRKS=y | ||
| 78 | CONFIG_COMPAT_BRK=y | ||
| 63 | CONFIG_SLAB=y | 79 | CONFIG_SLAB=y |
| 64 | # CONFIG_SLUB is not set | 80 | # CONFIG_SLUB is not set |
| 65 | # CONFIG_SLOB is not set | 81 | # CONFIG_SLOB is not set |
| 82 | CONFIG_PROFILING=y | ||
| 83 | CONFIG_TRACEPOINTS=y | ||
| 84 | # CONFIG_MARKERS is not set | ||
| 85 | CONFIG_OPROFILE=m | ||
| 86 | CONFIG_HAVE_OPROFILE=y | ||
| 87 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 88 | CONFIG_SLABINFO=y | ||
| 66 | CONFIG_RT_MUTEXES=y | 89 | CONFIG_RT_MUTEXES=y |
| 67 | # CONFIG_TINY_SHMEM is not set | ||
| 68 | CONFIG_BASE_SMALL=0 | 90 | CONFIG_BASE_SMALL=0 |
| 69 | CONFIG_MODULES=y | 91 | CONFIG_MODULES=y |
| 92 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 70 | CONFIG_MODULE_UNLOAD=y | 93 | CONFIG_MODULE_UNLOAD=y |
| 71 | CONFIG_MODULE_FORCE_UNLOAD=y | 94 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 72 | # CONFIG_MODVERSIONS is not set | 95 | # CONFIG_MODVERSIONS is not set |
| 73 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 96 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 74 | CONFIG_KMOD=y | 97 | CONFIG_INIT_ALL_POSSIBLE=y |
| 75 | CONFIG_BLOCK=y | 98 | CONFIG_BLOCK=y |
| 76 | # CONFIG_LBD is not set | 99 | # CONFIG_LBD is not set |
| 77 | # CONFIG_BLK_DEV_IO_TRACE is not set | 100 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 78 | # CONFIG_LSF is not set | ||
| 79 | # CONFIG_BLK_DEV_BSG is not set | 101 | # CONFIG_BLK_DEV_BSG is not set |
| 102 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 80 | 103 | ||
| 81 | # | 104 | # |
| 82 | # IO Schedulers | 105 | # IO Schedulers |
| @@ -90,6 +113,7 @@ CONFIG_DEFAULT_AS=y | |||
| 90 | # CONFIG_DEFAULT_CFQ is not set | 113 | # CONFIG_DEFAULT_CFQ is not set |
| 91 | # CONFIG_DEFAULT_NOOP is not set | 114 | # CONFIG_DEFAULT_NOOP is not set |
| 92 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 115 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 116 | # CONFIG_FREEZER is not set | ||
| 93 | 117 | ||
| 94 | # | 118 | # |
| 95 | # Processor type and features | 119 | # Processor type and features |
| @@ -115,17 +139,19 @@ CONFIG_HZ_250=y | |||
| 115 | # CONFIG_HZ_300 is not set | 139 | # CONFIG_HZ_300 is not set |
| 116 | # CONFIG_HZ_1000 is not set | 140 | # CONFIG_HZ_1000 is not set |
| 117 | CONFIG_HZ=250 | 141 | CONFIG_HZ=250 |
| 142 | # CONFIG_SCHED_HRTICK is not set | ||
| 118 | CONFIG_SELECT_MEMORY_MODEL=y | 143 | CONFIG_SELECT_MEMORY_MODEL=y |
| 119 | CONFIG_FLATMEM_MANUAL=y | 144 | CONFIG_FLATMEM_MANUAL=y |
| 120 | # CONFIG_DISCONTIGMEM_MANUAL is not set | 145 | # CONFIG_DISCONTIGMEM_MANUAL is not set |
| 121 | # CONFIG_SPARSEMEM_MANUAL is not set | 146 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 122 | CONFIG_FLATMEM=y | 147 | CONFIG_FLATMEM=y |
| 123 | CONFIG_FLAT_NODE_MEM_MAP=y | 148 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 124 | # CONFIG_SPARSEMEM_STATIC is not set | 149 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 125 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 150 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 126 | # CONFIG_RESOURCES_64BIT is not set | 151 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 127 | CONFIG_ZONE_DMA_FLAG=0 | 152 | CONFIG_ZONE_DMA_FLAG=0 |
| 128 | CONFIG_VIRT_TO_BUS=y | 153 | CONFIG_VIRT_TO_BUS=y |
| 154 | CONFIG_UNEVICTABLE_LRU=y | ||
| 129 | # CONFIG_HPUX is not set | 155 | # CONFIG_HPUX is not set |
| 130 | 156 | ||
| 131 | # | 157 | # |
| @@ -134,14 +160,13 @@ CONFIG_VIRT_TO_BUS=y | |||
| 134 | # CONFIG_GSC is not set | 160 | # CONFIG_GSC is not set |
| 135 | CONFIG_PCI=y | 161 | CONFIG_PCI=y |
| 136 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 162 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 163 | CONFIG_PCI_LEGACY=y | ||
| 137 | # CONFIG_PCI_DEBUG is not set | 164 | # CONFIG_PCI_DEBUG is not set |
| 165 | # CONFIG_PCI_STUB is not set | ||
| 138 | CONFIG_PCI_LBA=y | 166 | CONFIG_PCI_LBA=y |
| 139 | CONFIG_IOSAPIC=y | 167 | CONFIG_IOSAPIC=y |
| 140 | CONFIG_IOMMU_SBA=y | 168 | CONFIG_IOMMU_SBA=y |
| 141 | 169 | CONFIG_IOMMU_HELPER=y | |
| 142 | # | ||
| 143 | # PCCARD (PCMCIA/CardBus) support | ||
| 144 | # | ||
| 145 | # CONFIG_PCCARD is not set | 170 | # CONFIG_PCCARD is not set |
| 146 | # CONFIG_HOTPLUG_PCI is not set | 171 | # CONFIG_HOTPLUG_PCI is not set |
| 147 | 172 | ||
| @@ -158,16 +183,15 @@ CONFIG_PDC_STABLE=y | |||
| 158 | # Executable file formats | 183 | # Executable file formats |
| 159 | # | 184 | # |
| 160 | CONFIG_BINFMT_ELF=y | 185 | CONFIG_BINFMT_ELF=y |
| 186 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 187 | # CONFIG_HAVE_AOUT is not set | ||
| 161 | # CONFIG_BINFMT_MISC is not set | 188 | # CONFIG_BINFMT_MISC is not set |
| 162 | |||
| 163 | # | ||
| 164 | # Networking | ||
| 165 | # | ||
| 166 | CONFIG_NET=y | 189 | CONFIG_NET=y |
| 167 | 190 | ||
| 168 | # | 191 | # |
| 169 | # Networking options | 192 | # Networking options |
| 170 | # | 193 | # |
| 194 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 171 | CONFIG_PACKET=y | 195 | CONFIG_PACKET=y |
| 172 | CONFIG_PACKET_MMAP=y | 196 | CONFIG_PACKET_MMAP=y |
| 173 | CONFIG_UNIX=y | 197 | CONFIG_UNIX=y |
| @@ -175,6 +199,8 @@ CONFIG_XFRM=y | |||
| 175 | CONFIG_XFRM_USER=m | 199 | CONFIG_XFRM_USER=m |
| 176 | # CONFIG_XFRM_SUB_POLICY is not set | 200 | # CONFIG_XFRM_SUB_POLICY is not set |
| 177 | # CONFIG_XFRM_MIGRATE is not set | 201 | # CONFIG_XFRM_MIGRATE is not set |
| 202 | # CONFIG_XFRM_STATISTICS is not set | ||
| 203 | CONFIG_XFRM_IPCOMP=m | ||
| 178 | CONFIG_NET_KEY=m | 204 | CONFIG_NET_KEY=m |
| 179 | # CONFIG_NET_KEY_MIGRATE is not set | 205 | # CONFIG_NET_KEY_MIGRATE is not set |
| 180 | CONFIG_INET=y | 206 | CONFIG_INET=y |
| @@ -204,7 +230,6 @@ CONFIG_INET_XFRM_MODE_BEET=y | |||
| 204 | CONFIG_TCP_CONG_CUBIC=y | 230 | CONFIG_TCP_CONG_CUBIC=y |
| 205 | CONFIG_DEFAULT_TCP_CONG="cubic" | 231 | CONFIG_DEFAULT_TCP_CONG="cubic" |
| 206 | # CONFIG_TCP_MD5SIG is not set | 232 | # CONFIG_TCP_MD5SIG is not set |
| 207 | # CONFIG_IP_VS is not set | ||
| 208 | CONFIG_IPV6=m | 233 | CONFIG_IPV6=m |
| 209 | # CONFIG_IPV6_PRIVACY is not set | 234 | # CONFIG_IPV6_PRIVACY is not set |
| 210 | # CONFIG_IPV6_ROUTER_PREF is not set | 235 | # CONFIG_IPV6_ROUTER_PREF is not set |
| @@ -220,29 +245,34 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=m | |||
| 220 | CONFIG_INET6_XFRM_MODE_BEET=m | 245 | CONFIG_INET6_XFRM_MODE_BEET=m |
| 221 | # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set | 246 | # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set |
| 222 | CONFIG_IPV6_SIT=m | 247 | CONFIG_IPV6_SIT=m |
| 248 | CONFIG_IPV6_NDISC_NODETYPE=y | ||
| 223 | CONFIG_IPV6_TUNNEL=m | 249 | CONFIG_IPV6_TUNNEL=m |
| 224 | # CONFIG_IPV6_MULTIPLE_TABLES is not set | 250 | # CONFIG_IPV6_MULTIPLE_TABLES is not set |
| 251 | # CONFIG_IPV6_MROUTE is not set | ||
| 225 | # CONFIG_NETWORK_SECMARK is not set | 252 | # CONFIG_NETWORK_SECMARK is not set |
| 226 | CONFIG_NETFILTER=y | 253 | CONFIG_NETFILTER=y |
| 227 | CONFIG_NETFILTER_DEBUG=y | 254 | CONFIG_NETFILTER_DEBUG=y |
| 255 | CONFIG_NETFILTER_ADVANCED=y | ||
| 228 | 256 | ||
| 229 | # | 257 | # |
| 230 | # Core Netfilter Configuration | 258 | # Core Netfilter Configuration |
| 231 | # | 259 | # |
| 232 | # CONFIG_NETFILTER_NETLINK is not set | 260 | # CONFIG_NETFILTER_NETLINK_QUEUE is not set |
| 233 | # CONFIG_NF_CONNTRACK_ENABLED is not set | 261 | # CONFIG_NETFILTER_NETLINK_LOG is not set |
| 234 | # CONFIG_NF_CONNTRACK is not set | 262 | # CONFIG_NF_CONNTRACK is not set |
| 235 | # CONFIG_NETFILTER_XTABLES is not set | 263 | # CONFIG_NETFILTER_XTABLES is not set |
| 264 | # CONFIG_IP_VS is not set | ||
| 236 | 265 | ||
| 237 | # | 266 | # |
| 238 | # IP: Netfilter Configuration | 267 | # IP: Netfilter Configuration |
| 239 | # | 268 | # |
| 269 | # CONFIG_NF_DEFRAG_IPV4 is not set | ||
| 240 | CONFIG_IP_NF_QUEUE=m | 270 | CONFIG_IP_NF_QUEUE=m |
| 241 | # CONFIG_IP_NF_IPTABLES is not set | 271 | # CONFIG_IP_NF_IPTABLES is not set |
| 242 | # CONFIG_IP_NF_ARPTABLES is not set | 272 | # CONFIG_IP_NF_ARPTABLES is not set |
| 243 | 273 | ||
| 244 | # | 274 | # |
| 245 | # IPv6: Netfilter Configuration (EXPERIMENTAL) | 275 | # IPv6: Netfilter Configuration |
| 246 | # | 276 | # |
| 247 | # CONFIG_IP6_NF_QUEUE is not set | 277 | # CONFIG_IP6_NF_QUEUE is not set |
| 248 | # CONFIG_IP6_NF_IPTABLES is not set | 278 | # CONFIG_IP6_NF_IPTABLES is not set |
| @@ -251,6 +281,7 @@ CONFIG_IP_NF_QUEUE=m | |||
| 251 | # CONFIG_TIPC is not set | 281 | # CONFIG_TIPC is not set |
| 252 | # CONFIG_ATM is not set | 282 | # CONFIG_ATM is not set |
| 253 | # CONFIG_BRIDGE is not set | 283 | # CONFIG_BRIDGE is not set |
| 284 | # CONFIG_NET_DSA is not set | ||
| 254 | # CONFIG_VLAN_8021Q is not set | 285 | # CONFIG_VLAN_8021Q is not set |
| 255 | # CONFIG_DECNET is not set | 286 | # CONFIG_DECNET is not set |
| 256 | # CONFIG_LLC2 is not set | 287 | # CONFIG_LLC2 is not set |
| @@ -260,28 +291,26 @@ CONFIG_IP_NF_QUEUE=m | |||
| 260 | # CONFIG_LAPB is not set | 291 | # CONFIG_LAPB is not set |
| 261 | # CONFIG_ECONET is not set | 292 | # CONFIG_ECONET is not set |
| 262 | # CONFIG_WAN_ROUTER is not set | 293 | # CONFIG_WAN_ROUTER is not set |
| 263 | |||
| 264 | # | ||
| 265 | # QoS and/or fair queueing | ||
| 266 | # | ||
| 267 | # CONFIG_NET_SCHED is not set | 294 | # CONFIG_NET_SCHED is not set |
| 295 | # CONFIG_DCB is not set | ||
| 268 | 296 | ||
| 269 | # | 297 | # |
| 270 | # Network testing | 298 | # Network testing |
| 271 | # | 299 | # |
| 272 | CONFIG_NET_PKTGEN=m | 300 | CONFIG_NET_PKTGEN=m |
| 273 | # CONFIG_HAMRADIO is not set | 301 | # CONFIG_HAMRADIO is not set |
| 302 | # CONFIG_CAN is not set | ||
| 274 | # CONFIG_IRDA is not set | 303 | # CONFIG_IRDA is not set |
| 275 | # CONFIG_BT is not set | 304 | # CONFIG_BT is not set |
| 276 | # CONFIG_AF_RXRPC is not set | 305 | # CONFIG_AF_RXRPC is not set |
| 277 | 306 | # CONFIG_PHONET is not set | |
| 278 | # | 307 | CONFIG_WIRELESS=y |
| 279 | # Wireless | ||
| 280 | # | ||
| 281 | # CONFIG_CFG80211 is not set | 308 | # CONFIG_CFG80211 is not set |
| 309 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 282 | # CONFIG_WIRELESS_EXT is not set | 310 | # CONFIG_WIRELESS_EXT is not set |
| 311 | # CONFIG_LIB80211 is not set | ||
| 283 | # CONFIG_MAC80211 is not set | 312 | # CONFIG_MAC80211 is not set |
| 284 | # CONFIG_IEEE80211 is not set | 313 | # CONFIG_WIMAX is not set |
| 285 | # CONFIG_RFKILL is not set | 314 | # CONFIG_RFKILL is not set |
| 286 | # CONFIG_NET_9P is not set | 315 | # CONFIG_NET_9P is not set |
| 287 | 316 | ||
| @@ -296,6 +325,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |||
| 296 | # CONFIG_STANDALONE is not set | 325 | # CONFIG_STANDALONE is not set |
| 297 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | 326 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set |
| 298 | CONFIG_FW_LOADER=y | 327 | CONFIG_FW_LOADER=y |
| 328 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 329 | CONFIG_EXTRA_FIRMWARE="" | ||
| 299 | # CONFIG_DEBUG_DRIVER is not set | 330 | # CONFIG_DEBUG_DRIVER is not set |
| 300 | # CONFIG_DEBUG_DEVRES is not set | 331 | # CONFIG_DEBUG_DEVRES is not set |
| 301 | # CONFIG_SYS_HYPERVISOR is not set | 332 | # CONFIG_SYS_HYPERVISOR is not set |
| @@ -316,59 +347,62 @@ CONFIG_BLK_DEV_CRYPTOLOOP=m | |||
| 316 | # CONFIG_BLK_DEV_RAM is not set | 347 | # CONFIG_BLK_DEV_RAM is not set |
| 317 | # CONFIG_CDROM_PKTCDVD is not set | 348 | # CONFIG_CDROM_PKTCDVD is not set |
| 318 | # CONFIG_ATA_OVER_ETH is not set | 349 | # CONFIG_ATA_OVER_ETH is not set |
| 350 | # CONFIG_BLK_DEV_HD is not set | ||
| 319 | CONFIG_MISC_DEVICES=y | 351 | CONFIG_MISC_DEVICES=y |
| 320 | # CONFIG_PHANTOM is not set | 352 | # CONFIG_PHANTOM is not set |
| 321 | # CONFIG_EEPROM_93CX6 is not set | ||
| 322 | # CONFIG_SGI_IOC4 is not set | 353 | # CONFIG_SGI_IOC4 is not set |
| 323 | # CONFIG_TIFM_CORE is not set | 354 | # CONFIG_TIFM_CORE is not set |
| 355 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 356 | # CONFIG_HP_ILO is not set | ||
| 357 | # CONFIG_C2PORT is not set | ||
| 358 | |||
| 359 | # | ||
| 360 | # EEPROM support | ||
| 361 | # | ||
| 362 | # CONFIG_EEPROM_93CX6 is not set | ||
| 363 | CONFIG_HAVE_IDE=y | ||
| 324 | CONFIG_IDE=y | 364 | CONFIG_IDE=y |
| 325 | CONFIG_IDE_MAX_HWIFS=4 | ||
| 326 | CONFIG_BLK_DEV_IDE=y | ||
| 327 | 365 | ||
| 328 | # | 366 | # |
| 329 | # Please see Documentation/ide.txt for help/info on IDE drives | 367 | # Please see Documentation/ide/ide.txt for help/info on IDE drives |
| 330 | # | 368 | # |
| 369 | CONFIG_IDE_ATAPI=y | ||
| 331 | # CONFIG_BLK_DEV_IDE_SATA is not set | 370 | # CONFIG_BLK_DEV_IDE_SATA is not set |
| 332 | CONFIG_BLK_DEV_IDEDISK=m | 371 | CONFIG_IDE_GD=y |
| 333 | # CONFIG_IDEDISK_MULTI_MODE is not set | 372 | CONFIG_IDE_GD_ATA=y |
| 373 | # CONFIG_IDE_GD_ATAPI is not set | ||
| 334 | CONFIG_BLK_DEV_IDECD=y | 374 | CONFIG_BLK_DEV_IDECD=y |
| 375 | CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y | ||
| 335 | # CONFIG_BLK_DEV_IDETAPE is not set | 376 | # CONFIG_BLK_DEV_IDETAPE is not set |
| 336 | # CONFIG_BLK_DEV_IDEFLOPPY is not set | ||
| 337 | CONFIG_BLK_DEV_IDESCSI=y | ||
| 338 | # CONFIG_IDE_TASK_IOCTL is not set | 377 | # CONFIG_IDE_TASK_IOCTL is not set |
| 339 | CONFIG_IDE_PROC_FS=y | 378 | CONFIG_IDE_PROC_FS=y |
| 340 | 379 | ||
| 341 | # | 380 | # |
| 342 | # IDE chipset support/bugfixes | 381 | # IDE chipset support/bugfixes |
| 343 | # | 382 | # |
| 344 | CONFIG_IDE_GENERIC=y | ||
| 345 | # CONFIG_BLK_DEV_PLATFORM is not set | 383 | # CONFIG_BLK_DEV_PLATFORM is not set |
| 384 | CONFIG_BLK_DEV_IDEDMA_SFF=y | ||
| 346 | 385 | ||
| 347 | # | 386 | # |
| 348 | # PCI IDE chipsets support | 387 | # PCI IDE chipsets support |
| 349 | # | 388 | # |
| 350 | CONFIG_BLK_DEV_IDEPCI=y | 389 | CONFIG_BLK_DEV_IDEPCI=y |
| 351 | CONFIG_IDEPCI_SHARE_IRQ=y | ||
| 352 | CONFIG_IDEPCI_PCIBUS_ORDER=y | 390 | CONFIG_IDEPCI_PCIBUS_ORDER=y |
| 353 | # CONFIG_BLK_DEV_OFFBOARD is not set | ||
| 354 | # CONFIG_BLK_DEV_GENERIC is not set | 391 | # CONFIG_BLK_DEV_GENERIC is not set |
| 355 | # CONFIG_BLK_DEV_OPTI621 is not set | 392 | # CONFIG_BLK_DEV_OPTI621 is not set |
| 356 | CONFIG_BLK_DEV_IDEDMA_PCI=y | 393 | CONFIG_BLK_DEV_IDEDMA_PCI=y |
| 357 | # CONFIG_BLK_DEV_IDEDMA_FORCED is not set | ||
| 358 | CONFIG_IDEDMA_ONLYDISK=y | ||
| 359 | # CONFIG_BLK_DEV_AEC62XX is not set | 394 | # CONFIG_BLK_DEV_AEC62XX is not set |
| 360 | # CONFIG_BLK_DEV_ALI15X3 is not set | 395 | # CONFIG_BLK_DEV_ALI15X3 is not set |
| 361 | # CONFIG_BLK_DEV_AMD74XX is not set | 396 | # CONFIG_BLK_DEV_AMD74XX is not set |
| 362 | # CONFIG_BLK_DEV_CMD64X is not set | 397 | # CONFIG_BLK_DEV_CMD64X is not set |
| 363 | # CONFIG_BLK_DEV_TRIFLEX is not set | 398 | # CONFIG_BLK_DEV_TRIFLEX is not set |
| 364 | # CONFIG_BLK_DEV_CY82C693 is not set | ||
| 365 | # CONFIG_BLK_DEV_CS5520 is not set | 399 | # CONFIG_BLK_DEV_CS5520 is not set |
| 366 | # CONFIG_BLK_DEV_CS5530 is not set | 400 | # CONFIG_BLK_DEV_CS5530 is not set |
| 367 | # CONFIG_BLK_DEV_HPT34X is not set | ||
| 368 | # CONFIG_BLK_DEV_HPT366 is not set | 401 | # CONFIG_BLK_DEV_HPT366 is not set |
| 369 | # CONFIG_BLK_DEV_JMICRON is not set | 402 | # CONFIG_BLK_DEV_JMICRON is not set |
| 370 | # CONFIG_BLK_DEV_SC1200 is not set | 403 | # CONFIG_BLK_DEV_SC1200 is not set |
| 371 | # CONFIG_BLK_DEV_PIIX is not set | 404 | # CONFIG_BLK_DEV_PIIX is not set |
| 405 | # CONFIG_BLK_DEV_IT8172 is not set | ||
| 372 | # CONFIG_BLK_DEV_IT8213 is not set | 406 | # CONFIG_BLK_DEV_IT8213 is not set |
| 373 | # CONFIG_BLK_DEV_IT821X is not set | 407 | # CONFIG_BLK_DEV_IT821X is not set |
| 374 | CONFIG_BLK_DEV_NS87415=y | 408 | CONFIG_BLK_DEV_NS87415=y |
| @@ -380,10 +414,7 @@ CONFIG_BLK_DEV_SIIMAGE=m | |||
| 380 | # CONFIG_BLK_DEV_TRM290 is not set | 414 | # CONFIG_BLK_DEV_TRM290 is not set |
| 381 | # CONFIG_BLK_DEV_VIA82CXXX is not set | 415 | # CONFIG_BLK_DEV_VIA82CXXX is not set |
| 382 | # CONFIG_BLK_DEV_TC86C001 is not set | 416 | # CONFIG_BLK_DEV_TC86C001 is not set |
| 383 | # CONFIG_IDE_ARM is not set | ||
| 384 | CONFIG_BLK_DEV_IDEDMA=y | 417 | CONFIG_BLK_DEV_IDEDMA=y |
| 385 | # CONFIG_IDEDMA_IVB is not set | ||
| 386 | # CONFIG_BLK_DEV_HD is not set | ||
| 387 | 418 | ||
| 388 | # | 419 | # |
| 389 | # SCSI device support | 420 | # SCSI device support |
| @@ -422,8 +453,10 @@ CONFIG_SCSI_SPI_ATTRS=y | |||
| 422 | # CONFIG_SCSI_FC_ATTRS is not set | 453 | # CONFIG_SCSI_FC_ATTRS is not set |
| 423 | CONFIG_SCSI_ISCSI_ATTRS=m | 454 | CONFIG_SCSI_ISCSI_ATTRS=m |
| 424 | # CONFIG_SCSI_SAS_LIBSAS is not set | 455 | # CONFIG_SCSI_SAS_LIBSAS is not set |
| 456 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 425 | CONFIG_SCSI_LOWLEVEL=y | 457 | CONFIG_SCSI_LOWLEVEL=y |
| 426 | # CONFIG_ISCSI_TCP is not set | 458 | # CONFIG_ISCSI_TCP is not set |
| 459 | # CONFIG_SCSI_CXGB3_ISCSI is not set | ||
| 427 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set | 460 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set |
| 428 | # CONFIG_SCSI_3W_9XXX is not set | 461 | # CONFIG_SCSI_3W_9XXX is not set |
| 429 | # CONFIG_SCSI_ACARD is not set | 462 | # CONFIG_SCSI_ACARD is not set |
| @@ -433,16 +466,20 @@ CONFIG_SCSI_LOWLEVEL=y | |||
| 433 | # CONFIG_SCSI_AIC79XX is not set | 466 | # CONFIG_SCSI_AIC79XX is not set |
| 434 | # CONFIG_SCSI_AIC94XX is not set | 467 | # CONFIG_SCSI_AIC94XX is not set |
| 435 | # CONFIG_SCSI_DPT_I2O is not set | 468 | # CONFIG_SCSI_DPT_I2O is not set |
| 469 | # CONFIG_SCSI_ADVANSYS is not set | ||
| 436 | # CONFIG_SCSI_ARCMSR is not set | 470 | # CONFIG_SCSI_ARCMSR is not set |
| 437 | # CONFIG_MEGARAID_NEWGEN is not set | 471 | # CONFIG_MEGARAID_NEWGEN is not set |
| 438 | # CONFIG_MEGARAID_LEGACY is not set | 472 | # CONFIG_MEGARAID_LEGACY is not set |
| 439 | # CONFIG_MEGARAID_SAS is not set | 473 | # CONFIG_MEGARAID_SAS is not set |
| 440 | # CONFIG_SCSI_HPTIOP is not set | 474 | # CONFIG_SCSI_HPTIOP is not set |
| 475 | # CONFIG_LIBFC is not set | ||
| 476 | # CONFIG_FCOE is not set | ||
| 441 | # CONFIG_SCSI_DMX3191D is not set | 477 | # CONFIG_SCSI_DMX3191D is not set |
| 442 | # CONFIG_SCSI_FUTURE_DOMAIN is not set | 478 | # CONFIG_SCSI_FUTURE_DOMAIN is not set |
| 443 | # CONFIG_SCSI_IPS is not set | 479 | # CONFIG_SCSI_IPS is not set |
| 444 | # CONFIG_SCSI_INITIO is not set | 480 | # CONFIG_SCSI_INITIO is not set |
| 445 | # CONFIG_SCSI_INIA100 is not set | 481 | # CONFIG_SCSI_INIA100 is not set |
| 482 | # CONFIG_SCSI_MVSAS is not set | ||
| 446 | # CONFIG_SCSI_STEX is not set | 483 | # CONFIG_SCSI_STEX is not set |
| 447 | CONFIG_SCSI_SYM53C8XX_2=y | 484 | CONFIG_SCSI_SYM53C8XX_2=y |
| 448 | CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0 | 485 | CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0 |
| @@ -458,9 +495,11 @@ CONFIG_SCSI_SYM53C8XX_MMIO=y | |||
| 458 | # CONFIG_SCSI_NSP32 is not set | 495 | # CONFIG_SCSI_NSP32 is not set |
| 459 | CONFIG_SCSI_DEBUG=m | 496 | CONFIG_SCSI_DEBUG=m |
| 460 | # CONFIG_SCSI_SRP is not set | 497 | # CONFIG_SCSI_SRP is not set |
| 498 | # CONFIG_SCSI_DH is not set | ||
| 461 | # CONFIG_ATA is not set | 499 | # CONFIG_ATA is not set |
| 462 | CONFIG_MD=y | 500 | CONFIG_MD=y |
| 463 | CONFIG_BLK_DEV_MD=y | 501 | CONFIG_BLK_DEV_MD=y |
| 502 | CONFIG_MD_AUTODETECT=y | ||
| 464 | CONFIG_MD_LINEAR=y | 503 | CONFIG_MD_LINEAR=y |
| 465 | CONFIG_MD_RAID0=y | 504 | CONFIG_MD_RAID0=y |
| 466 | CONFIG_MD_RAID1=y | 505 | CONFIG_MD_RAID1=y |
| @@ -475,13 +514,8 @@ CONFIG_DM_SNAPSHOT=m | |||
| 475 | CONFIG_DM_MIRROR=m | 514 | CONFIG_DM_MIRROR=m |
| 476 | CONFIG_DM_ZERO=m | 515 | CONFIG_DM_ZERO=m |
| 477 | CONFIG_DM_MULTIPATH=m | 516 | CONFIG_DM_MULTIPATH=m |
| 478 | # CONFIG_DM_MULTIPATH_EMC is not set | ||
| 479 | # CONFIG_DM_MULTIPATH_RDAC is not set | ||
| 480 | # CONFIG_DM_DELAY is not set | 517 | # CONFIG_DM_DELAY is not set |
| 481 | 518 | # CONFIG_DM_UEVENT is not set | |
| 482 | # | ||
| 483 | # Fusion MPT device support | ||
| 484 | # | ||
| 485 | CONFIG_FUSION=y | 519 | CONFIG_FUSION=y |
| 486 | CONFIG_FUSION_SPI=m | 520 | CONFIG_FUSION_SPI=m |
| 487 | # CONFIG_FUSION_FC is not set | 521 | # CONFIG_FUSION_FC is not set |
| @@ -493,20 +527,40 @@ CONFIG_FUSION_CTL=m | |||
| 493 | # | 527 | # |
| 494 | # IEEE 1394 (FireWire) support | 528 | # IEEE 1394 (FireWire) support |
| 495 | # | 529 | # |
| 530 | |||
| 531 | # | ||
| 532 | # Enable only one of the two stacks, unless you know what you are doing | ||
| 533 | # | ||
| 496 | # CONFIG_FIREWIRE is not set | 534 | # CONFIG_FIREWIRE is not set |
| 497 | # CONFIG_IEEE1394 is not set | 535 | # CONFIG_IEEE1394 is not set |
| 498 | # CONFIG_I2O is not set | 536 | # CONFIG_I2O is not set |
| 499 | CONFIG_NETDEVICES=y | 537 | CONFIG_NETDEVICES=y |
| 500 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 501 | CONFIG_DUMMY=m | 538 | CONFIG_DUMMY=m |
| 502 | CONFIG_BONDING=m | 539 | CONFIG_BONDING=m |
| 503 | # CONFIG_MACVLAN is not set | 540 | # CONFIG_MACVLAN is not set |
| 504 | # CONFIG_EQUALIZER is not set | 541 | # CONFIG_EQUALIZER is not set |
| 505 | CONFIG_TUN=m | 542 | CONFIG_TUN=m |
| 506 | # CONFIG_VETH is not set | 543 | # CONFIG_VETH is not set |
| 507 | # CONFIG_IP1000 is not set | ||
| 508 | # CONFIG_ARCNET is not set | 544 | # CONFIG_ARCNET is not set |
| 509 | # CONFIG_PHYLIB is not set | 545 | CONFIG_PHYLIB=m |
| 546 | |||
| 547 | # | ||
| 548 | # MII PHY device drivers | ||
| 549 | # | ||
| 550 | # CONFIG_MARVELL_PHY is not set | ||
| 551 | # CONFIG_DAVICOM_PHY is not set | ||
| 552 | # CONFIG_QSEMI_PHY is not set | ||
| 553 | # CONFIG_LXT_PHY is not set | ||
| 554 | # CONFIG_CICADA_PHY is not set | ||
| 555 | # CONFIG_VITESSE_PHY is not set | ||
| 556 | # CONFIG_SMSC_PHY is not set | ||
| 557 | # CONFIG_BROADCOM_PHY is not set | ||
| 558 | # CONFIG_ICPLUS_PHY is not set | ||
| 559 | # CONFIG_REALTEK_PHY is not set | ||
| 560 | # CONFIG_NATIONAL_PHY is not set | ||
| 561 | # CONFIG_STE10XP is not set | ||
| 562 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 563 | # CONFIG_MDIO_BITBANG is not set | ||
| 510 | CONFIG_NET_ETHERNET=y | 564 | CONFIG_NET_ETHERNET=y |
| 511 | CONFIG_MII=m | 565 | CONFIG_MII=m |
| 512 | # CONFIG_HAPPYMEAL is not set | 566 | # CONFIG_HAPPYMEAL is not set |
| @@ -528,33 +582,38 @@ CONFIG_TULIP_MMIO=y | |||
| 528 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 582 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 529 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 583 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 530 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 584 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 585 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 586 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 587 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 531 | CONFIG_NET_PCI=y | 588 | CONFIG_NET_PCI=y |
| 532 | # CONFIG_PCNET32 is not set | 589 | # CONFIG_PCNET32 is not set |
| 533 | # CONFIG_AMD8111_ETH is not set | 590 | # CONFIG_AMD8111_ETH is not set |
| 534 | # CONFIG_ADAPTEC_STARFIRE is not set | 591 | # CONFIG_ADAPTEC_STARFIRE is not set |
| 535 | # CONFIG_B44 is not set | 592 | # CONFIG_B44 is not set |
| 536 | # CONFIG_FORCEDETH is not set | 593 | # CONFIG_FORCEDETH is not set |
| 537 | # CONFIG_EEPRO100 is not set | ||
| 538 | CONFIG_E100=m | 594 | CONFIG_E100=m |
| 539 | # CONFIG_FEALNX is not set | 595 | # CONFIG_FEALNX is not set |
| 540 | # CONFIG_NATSEMI is not set | 596 | # CONFIG_NATSEMI is not set |
| 541 | # CONFIG_NE2K_PCI is not set | 597 | # CONFIG_NE2K_PCI is not set |
| 542 | # CONFIG_8139CP is not set | 598 | # CONFIG_8139CP is not set |
| 543 | # CONFIG_8139TOO is not set | 599 | # CONFIG_8139TOO is not set |
| 600 | # CONFIG_R6040 is not set | ||
| 544 | # CONFIG_SIS900 is not set | 601 | # CONFIG_SIS900 is not set |
| 545 | # CONFIG_EPIC100 is not set | 602 | # CONFIG_EPIC100 is not set |
| 603 | # CONFIG_SMSC9420 is not set | ||
| 546 | # CONFIG_SUNDANCE is not set | 604 | # CONFIG_SUNDANCE is not set |
| 547 | # CONFIG_TLAN is not set | 605 | # CONFIG_TLAN is not set |
| 548 | # CONFIG_VIA_RHINE is not set | 606 | # CONFIG_VIA_RHINE is not set |
| 549 | # CONFIG_SC92031 is not set | 607 | # CONFIG_SC92031 is not set |
| 608 | # CONFIG_ATL2 is not set | ||
| 550 | CONFIG_NETDEV_1000=y | 609 | CONFIG_NETDEV_1000=y |
| 551 | CONFIG_ACENIC=m | 610 | CONFIG_ACENIC=m |
| 552 | # CONFIG_ACENIC_OMIT_TIGON_I is not set | 611 | # CONFIG_ACENIC_OMIT_TIGON_I is not set |
| 553 | # CONFIG_DL2K is not set | 612 | # CONFIG_DL2K is not set |
| 554 | CONFIG_E1000=m | 613 | CONFIG_E1000=m |
| 555 | # CONFIG_E1000_NAPI is not set | ||
| 556 | # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set | ||
| 557 | # CONFIG_E1000E is not set | 614 | # CONFIG_E1000E is not set |
| 615 | # CONFIG_IP1000 is not set | ||
| 616 | # CONFIG_IGB is not set | ||
| 558 | # CONFIG_NS83820 is not set | 617 | # CONFIG_NS83820 is not set |
| 559 | # CONFIG_HAMACHI is not set | 618 | # CONFIG_HAMACHI is not set |
| 560 | # CONFIG_YELLOWFIN is not set | 619 | # CONFIG_YELLOWFIN is not set |
| @@ -562,23 +621,31 @@ CONFIG_E1000=m | |||
| 562 | # CONFIG_SIS190 is not set | 621 | # CONFIG_SIS190 is not set |
| 563 | # CONFIG_SKGE is not set | 622 | # CONFIG_SKGE is not set |
| 564 | # CONFIG_SKY2 is not set | 623 | # CONFIG_SKY2 is not set |
| 565 | # CONFIG_SK98LIN is not set | ||
| 566 | # CONFIG_VIA_VELOCITY is not set | 624 | # CONFIG_VIA_VELOCITY is not set |
| 567 | CONFIG_TIGON3=m | 625 | CONFIG_TIGON3=m |
| 568 | # CONFIG_BNX2 is not set | 626 | # CONFIG_BNX2 is not set |
| 569 | # CONFIG_QLA3XXX is not set | 627 | # CONFIG_QLA3XXX is not set |
| 570 | # CONFIG_ATL1 is not set | 628 | # CONFIG_ATL1 is not set |
| 629 | # CONFIG_ATL1E is not set | ||
| 630 | # CONFIG_ATL1C is not set | ||
| 631 | # CONFIG_JME is not set | ||
| 571 | CONFIG_NETDEV_10000=y | 632 | CONFIG_NETDEV_10000=y |
| 572 | # CONFIG_CHELSIO_T1 is not set | 633 | # CONFIG_CHELSIO_T1 is not set |
| 634 | CONFIG_CHELSIO_T3_DEPENDS=y | ||
| 573 | # CONFIG_CHELSIO_T3 is not set | 635 | # CONFIG_CHELSIO_T3 is not set |
| 636 | # CONFIG_ENIC is not set | ||
| 574 | # CONFIG_IXGBE is not set | 637 | # CONFIG_IXGBE is not set |
| 575 | # CONFIG_IXGB is not set | 638 | # CONFIG_IXGB is not set |
| 576 | # CONFIG_S2IO is not set | 639 | # CONFIG_S2IO is not set |
| 577 | # CONFIG_MYRI10GE is not set | 640 | # CONFIG_MYRI10GE is not set |
| 578 | # CONFIG_NETXEN_NIC is not set | 641 | # CONFIG_NETXEN_NIC is not set |
| 579 | # CONFIG_NIU is not set | 642 | # CONFIG_NIU is not set |
| 643 | # CONFIG_MLX4_EN is not set | ||
| 580 | # CONFIG_MLX4_CORE is not set | 644 | # CONFIG_MLX4_CORE is not set |
| 581 | # CONFIG_TEHUTI is not set | 645 | # CONFIG_TEHUTI is not set |
| 646 | # CONFIG_BNX2X is not set | ||
| 647 | # CONFIG_QLGE is not set | ||
| 648 | # CONFIG_SFC is not set | ||
| 582 | # CONFIG_TR is not set | 649 | # CONFIG_TR is not set |
| 583 | 650 | ||
| 584 | # | 651 | # |
| @@ -586,6 +653,11 @@ CONFIG_NETDEV_10000=y | |||
| 586 | # | 653 | # |
| 587 | # CONFIG_WLAN_PRE80211 is not set | 654 | # CONFIG_WLAN_PRE80211 is not set |
| 588 | # CONFIG_WLAN_80211 is not set | 655 | # CONFIG_WLAN_80211 is not set |
| 656 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 657 | |||
| 658 | # | ||
| 659 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 660 | # | ||
| 589 | 661 | ||
| 590 | # | 662 | # |
| 591 | # USB Network Adapters | 663 | # USB Network Adapters |
| @@ -594,7 +666,6 @@ CONFIG_NETDEV_10000=y | |||
| 594 | # CONFIG_USB_KAWETH is not set | 666 | # CONFIG_USB_KAWETH is not set |
| 595 | # CONFIG_USB_PEGASUS is not set | 667 | # CONFIG_USB_PEGASUS is not set |
| 596 | # CONFIG_USB_RTL8150 is not set | 668 | # CONFIG_USB_RTL8150 is not set |
| 597 | # CONFIG_USB_USBNET_MII is not set | ||
| 598 | # CONFIG_USB_USBNET is not set | 669 | # CONFIG_USB_USBNET is not set |
| 599 | # CONFIG_WAN is not set | 670 | # CONFIG_WAN is not set |
| 600 | # CONFIG_FDDI is not set | 671 | # CONFIG_FDDI is not set |
| @@ -612,7 +683,6 @@ CONFIG_PPPOE=m | |||
| 612 | # CONFIG_SLIP is not set | 683 | # CONFIG_SLIP is not set |
| 613 | CONFIG_SLHC=m | 684 | CONFIG_SLHC=m |
| 614 | # CONFIG_NET_FC is not set | 685 | # CONFIG_NET_FC is not set |
| 615 | # CONFIG_SHAPER is not set | ||
| 616 | # CONFIG_NETCONSOLE is not set | 686 | # CONFIG_NETCONSOLE is not set |
| 617 | # CONFIG_NETPOLL is not set | 687 | # CONFIG_NETPOLL is not set |
| 618 | # CONFIG_NET_POLL_CONTROLLER is not set | 688 | # CONFIG_NET_POLL_CONTROLLER is not set |
| @@ -634,7 +704,6 @@ CONFIG_INPUT_MOUSEDEV=y | |||
| 634 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1600 | 704 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1600 |
| 635 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=1200 | 705 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=1200 |
| 636 | # CONFIG_INPUT_JOYDEV is not set | 706 | # CONFIG_INPUT_JOYDEV is not set |
| 637 | # CONFIG_INPUT_TSDEV is not set | ||
| 638 | # CONFIG_INPUT_EVDEV is not set | 707 | # CONFIG_INPUT_EVDEV is not set |
| 639 | # CONFIG_INPUT_EVBUG is not set | 708 | # CONFIG_INPUT_EVBUG is not set |
| 640 | 709 | ||
| @@ -652,6 +721,7 @@ CONFIG_INPUT_MOUSE=y | |||
| 652 | # CONFIG_MOUSE_PS2 is not set | 721 | # CONFIG_MOUSE_PS2 is not set |
| 653 | # CONFIG_MOUSE_SERIAL is not set | 722 | # CONFIG_MOUSE_SERIAL is not set |
| 654 | # CONFIG_MOUSE_APPLETOUCH is not set | 723 | # CONFIG_MOUSE_APPLETOUCH is not set |
| 724 | # CONFIG_MOUSE_BCM5974 is not set | ||
| 655 | # CONFIG_MOUSE_VSXXXAA is not set | 725 | # CONFIG_MOUSE_VSXXXAA is not set |
| 656 | # CONFIG_INPUT_JOYSTICK is not set | 726 | # CONFIG_INPUT_JOYSTICK is not set |
| 657 | # CONFIG_INPUT_TABLET is not set | 727 | # CONFIG_INPUT_TABLET is not set |
| @@ -672,10 +742,13 @@ CONFIG_SERIO_LIBPS2=m | |||
| 672 | # Character devices | 742 | # Character devices |
| 673 | # | 743 | # |
| 674 | CONFIG_VT=y | 744 | CONFIG_VT=y |
| 745 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 675 | CONFIG_VT_CONSOLE=y | 746 | CONFIG_VT_CONSOLE=y |
| 676 | CONFIG_HW_CONSOLE=y | 747 | CONFIG_HW_CONSOLE=y |
| 677 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | 748 | # CONFIG_VT_HW_CONSOLE_BINDING is not set |
| 749 | CONFIG_DEVKMEM=y | ||
| 678 | # CONFIG_SERIAL_NONSTANDARD is not set | 750 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 751 | # CONFIG_NOZOMI is not set | ||
| 679 | 752 | ||
| 680 | # | 753 | # |
| 681 | # Serial drivers | 754 | # Serial drivers |
| @@ -699,72 +772,77 @@ CONFIG_SERIAL_CORE=y | |||
| 699 | CONFIG_SERIAL_CORE_CONSOLE=y | 772 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 700 | # CONFIG_SERIAL_JSM is not set | 773 | # CONFIG_SERIAL_JSM is not set |
| 701 | CONFIG_UNIX98_PTYS=y | 774 | CONFIG_UNIX98_PTYS=y |
| 775 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 702 | CONFIG_LEGACY_PTYS=y | 776 | CONFIG_LEGACY_PTYS=y |
| 703 | CONFIG_LEGACY_PTY_COUNT=256 | 777 | CONFIG_LEGACY_PTY_COUNT=256 |
| 704 | # CONFIG_IPMI_HANDLER is not set | 778 | # CONFIG_IPMI_HANDLER is not set |
| 705 | # CONFIG_WATCHDOG is not set | ||
| 706 | # CONFIG_HW_RANDOM is not set | 779 | # CONFIG_HW_RANDOM is not set |
| 707 | CONFIG_GEN_RTC=y | ||
| 708 | CONFIG_GEN_RTC_X=y | ||
| 709 | # CONFIG_R3964 is not set | 780 | # CONFIG_R3964 is not set |
| 710 | # CONFIG_APPLICOM is not set | 781 | # CONFIG_APPLICOM is not set |
| 711 | # CONFIG_AGP is not set | ||
| 712 | # CONFIG_DRM is not set | ||
| 713 | CONFIG_RAW_DRIVER=y | 782 | CONFIG_RAW_DRIVER=y |
| 714 | CONFIG_MAX_RAW_DEVS=256 | 783 | CONFIG_MAX_RAW_DEVS=256 |
| 715 | # CONFIG_TCG_TPM is not set | 784 | # CONFIG_TCG_TPM is not set |
| 716 | CONFIG_DEVPORT=y | 785 | CONFIG_DEVPORT=y |
| 717 | # CONFIG_I2C is not set | 786 | # CONFIG_I2C is not set |
| 718 | |||
| 719 | # | ||
| 720 | # SPI support | ||
| 721 | # | ||
| 722 | # CONFIG_SPI is not set | 787 | # CONFIG_SPI is not set |
| 723 | # CONFIG_SPI_MASTER is not set | ||
| 724 | # CONFIG_W1 is not set | 788 | # CONFIG_W1 is not set |
| 725 | # CONFIG_POWER_SUPPLY is not set | 789 | # CONFIG_POWER_SUPPLY is not set |
| 726 | # CONFIG_HWMON is not set | 790 | # CONFIG_HWMON is not set |
| 791 | # CONFIG_THERMAL is not set | ||
| 792 | # CONFIG_THERMAL_HWMON is not set | ||
| 793 | # CONFIG_WATCHDOG is not set | ||
| 794 | CONFIG_SSB_POSSIBLE=y | ||
| 727 | 795 | ||
| 728 | # | 796 | # |
| 729 | # Sonics Silicon Backplane | 797 | # Sonics Silicon Backplane |
| 730 | # | 798 | # |
| 731 | CONFIG_SSB_POSSIBLE=y | ||
| 732 | # CONFIG_SSB is not set | 799 | # CONFIG_SSB is not set |
| 733 | 800 | ||
| 734 | # | 801 | # |
| 735 | # Multifunction device drivers | 802 | # Multifunction device drivers |
| 736 | # | 803 | # |
| 804 | # CONFIG_MFD_CORE is not set | ||
| 737 | # CONFIG_MFD_SM501 is not set | 805 | # CONFIG_MFD_SM501 is not set |
| 806 | # CONFIG_HTC_PASIC3 is not set | ||
| 807 | # CONFIG_MFD_TMIO is not set | ||
| 808 | # CONFIG_REGULATOR is not set | ||
| 738 | 809 | ||
| 739 | # | 810 | # |
| 740 | # Multimedia devices | 811 | # Multimedia devices |
| 741 | # | 812 | # |
| 813 | |||
| 814 | # | ||
| 815 | # Multimedia core support | ||
| 816 | # | ||
| 742 | # CONFIG_VIDEO_DEV is not set | 817 | # CONFIG_VIDEO_DEV is not set |
| 743 | # CONFIG_DVB_CORE is not set | 818 | # CONFIG_DVB_CORE is not set |
| 744 | # CONFIG_DAB is not set | 819 | # CONFIG_VIDEO_MEDIA is not set |
| 745 | 820 | ||
| 746 | # | 821 | # |
| 747 | # Graphics support | 822 | # Multimedia drivers |
| 748 | # | 823 | # |
| 749 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 824 | # CONFIG_DAB is not set |
| 750 | 825 | ||
| 751 | # | 826 | # |
| 752 | # Display device support | 827 | # Graphics support |
| 753 | # | 828 | # |
| 754 | # CONFIG_DISPLAY_SUPPORT is not set | 829 | # CONFIG_AGP is not set |
| 830 | # CONFIG_DRM is not set | ||
| 755 | # CONFIG_VGASTATE is not set | 831 | # CONFIG_VGASTATE is not set |
| 756 | CONFIG_VIDEO_OUTPUT_CONTROL=m | 832 | CONFIG_VIDEO_OUTPUT_CONTROL=m |
| 757 | CONFIG_FB=y | 833 | CONFIG_FB=y |
| 758 | # CONFIG_FIRMWARE_EDID is not set | 834 | # CONFIG_FIRMWARE_EDID is not set |
| 759 | # CONFIG_FB_DDC is not set | 835 | # CONFIG_FB_DDC is not set |
| 836 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 760 | CONFIG_FB_CFB_FILLRECT=y | 837 | CONFIG_FB_CFB_FILLRECT=y |
| 761 | CONFIG_FB_CFB_COPYAREA=y | 838 | CONFIG_FB_CFB_COPYAREA=y |
| 762 | CONFIG_FB_CFB_IMAGEBLIT=y | 839 | CONFIG_FB_CFB_IMAGEBLIT=y |
| 840 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 763 | # CONFIG_FB_SYS_FILLRECT is not set | 841 | # CONFIG_FB_SYS_FILLRECT is not set |
| 764 | # CONFIG_FB_SYS_COPYAREA is not set | 842 | # CONFIG_FB_SYS_COPYAREA is not set |
| 765 | # CONFIG_FB_SYS_IMAGEBLIT is not set | 843 | # CONFIG_FB_SYS_IMAGEBLIT is not set |
| 844 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 766 | # CONFIG_FB_SYS_FOPS is not set | 845 | # CONFIG_FB_SYS_FOPS is not set |
| 767 | CONFIG_FB_DEFERRED_IO=y | ||
| 768 | # CONFIG_FB_SVGALIB is not set | 846 | # CONFIG_FB_SVGALIB is not set |
| 769 | # CONFIG_FB_MACMODES is not set | 847 | # CONFIG_FB_MACMODES is not set |
| 770 | # CONFIG_FB_BACKLIGHT is not set | 848 | # CONFIG_FB_BACKLIGHT is not set |
| @@ -790,6 +868,7 @@ CONFIG_FB_STI=y | |||
| 790 | # CONFIG_FB_S3 is not set | 868 | # CONFIG_FB_S3 is not set |
| 791 | # CONFIG_FB_SAVAGE is not set | 869 | # CONFIG_FB_SAVAGE is not set |
| 792 | # CONFIG_FB_SIS is not set | 870 | # CONFIG_FB_SIS is not set |
| 871 | # CONFIG_FB_VIA is not set | ||
| 793 | # CONFIG_FB_NEOMAGIC is not set | 872 | # CONFIG_FB_NEOMAGIC is not set |
| 794 | # CONFIG_FB_KYRO is not set | 873 | # CONFIG_FB_KYRO is not set |
| 795 | # CONFIG_FB_3DFX is not set | 874 | # CONFIG_FB_3DFX is not set |
| @@ -798,7 +877,16 @@ CONFIG_FB_STI=y | |||
| 798 | # CONFIG_FB_TRIDENT is not set | 877 | # CONFIG_FB_TRIDENT is not set |
| 799 | # CONFIG_FB_ARK is not set | 878 | # CONFIG_FB_ARK is not set |
| 800 | # CONFIG_FB_PM3 is not set | 879 | # CONFIG_FB_PM3 is not set |
| 880 | # CONFIG_FB_CARMINE is not set | ||
| 801 | # CONFIG_FB_VIRTUAL is not set | 881 | # CONFIG_FB_VIRTUAL is not set |
| 882 | # CONFIG_FB_METRONOME is not set | ||
| 883 | # CONFIG_FB_MB862XX is not set | ||
| 884 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 885 | |||
| 886 | # | ||
| 887 | # Display device support | ||
| 888 | # | ||
| 889 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 802 | 890 | ||
| 803 | # | 891 | # |
| 804 | # Console display driver support | 892 | # Console display driver support |
| @@ -818,15 +906,8 @@ CONFIG_LOGO=y | |||
| 818 | # CONFIG_LOGO_LINUX_VGA16 is not set | 906 | # CONFIG_LOGO_LINUX_VGA16 is not set |
| 819 | # CONFIG_LOGO_LINUX_CLUT224 is not set | 907 | # CONFIG_LOGO_LINUX_CLUT224 is not set |
| 820 | CONFIG_LOGO_PARISC_CLUT224=y | 908 | CONFIG_LOGO_PARISC_CLUT224=y |
| 821 | |||
| 822 | # | ||
| 823 | # Sound | ||
| 824 | # | ||
| 825 | CONFIG_SOUND=y | 909 | CONFIG_SOUND=y |
| 826 | 910 | CONFIG_SOUND_OSS_CORE=y | |
| 827 | # | ||
| 828 | # Advanced Linux Sound Architecture | ||
| 829 | # | ||
| 830 | CONFIG_SND=y | 911 | CONFIG_SND=y |
| 831 | CONFIG_SND_TIMER=y | 912 | CONFIG_SND_TIMER=y |
| 832 | CONFIG_SND_PCM=y | 913 | CONFIG_SND_PCM=y |
| @@ -842,20 +923,16 @@ CONFIG_SND_SUPPORT_OLD_API=y | |||
| 842 | CONFIG_SND_VERBOSE_PROCFS=y | 923 | CONFIG_SND_VERBOSE_PROCFS=y |
| 843 | # CONFIG_SND_VERBOSE_PRINTK is not set | 924 | # CONFIG_SND_VERBOSE_PRINTK is not set |
| 844 | # CONFIG_SND_DEBUG is not set | 925 | # CONFIG_SND_DEBUG is not set |
| 845 | 926 | CONFIG_SND_VMASTER=y | |
| 846 | # | ||
| 847 | # Generic devices | ||
| 848 | # | ||
| 849 | CONFIG_SND_AC97_CODEC=y | 927 | CONFIG_SND_AC97_CODEC=y |
| 928 | CONFIG_SND_DRIVERS=y | ||
| 850 | # CONFIG_SND_DUMMY is not set | 929 | # CONFIG_SND_DUMMY is not set |
| 851 | # CONFIG_SND_VIRMIDI is not set | 930 | # CONFIG_SND_VIRMIDI is not set |
| 852 | # CONFIG_SND_MTPAV is not set | 931 | # CONFIG_SND_MTPAV is not set |
| 853 | # CONFIG_SND_SERIAL_U16550 is not set | 932 | # CONFIG_SND_SERIAL_U16550 is not set |
| 854 | # CONFIG_SND_MPU401 is not set | 933 | # CONFIG_SND_MPU401 is not set |
| 855 | 934 | # CONFIG_SND_AC97_POWER_SAVE is not set | |
| 856 | # | 935 | CONFIG_SND_PCI=y |
| 857 | # PCI devices | ||
| 858 | # | ||
| 859 | CONFIG_SND_AD1889=y | 936 | CONFIG_SND_AD1889=y |
| 860 | # CONFIG_SND_ALS300 is not set | 937 | # CONFIG_SND_ALS300 is not set |
| 861 | # CONFIG_SND_ALI5451 is not set | 938 | # CONFIG_SND_ALI5451 is not set |
| @@ -864,10 +941,12 @@ CONFIG_SND_AD1889=y | |||
| 864 | # CONFIG_SND_AU8810 is not set | 941 | # CONFIG_SND_AU8810 is not set |
| 865 | # CONFIG_SND_AU8820 is not set | 942 | # CONFIG_SND_AU8820 is not set |
| 866 | # CONFIG_SND_AU8830 is not set | 943 | # CONFIG_SND_AU8830 is not set |
| 944 | # CONFIG_SND_AW2 is not set | ||
| 867 | # CONFIG_SND_AZT3328 is not set | 945 | # CONFIG_SND_AZT3328 is not set |
| 868 | # CONFIG_SND_BT87X is not set | 946 | # CONFIG_SND_BT87X is not set |
| 869 | # CONFIG_SND_CA0106 is not set | 947 | # CONFIG_SND_CA0106 is not set |
| 870 | # CONFIG_SND_CMIPCI is not set | 948 | # CONFIG_SND_CMIPCI is not set |
| 949 | # CONFIG_SND_OXYGEN is not set | ||
| 871 | # CONFIG_SND_CS4281 is not set | 950 | # CONFIG_SND_CS4281 is not set |
| 872 | # CONFIG_SND_CS46XX is not set | 951 | # CONFIG_SND_CS46XX is not set |
| 873 | # CONFIG_SND_DARLA20 is not set | 952 | # CONFIG_SND_DARLA20 is not set |
| @@ -892,6 +971,7 @@ CONFIG_SND_AD1889=y | |||
| 892 | # CONFIG_SND_HDA_INTEL is not set | 971 | # CONFIG_SND_HDA_INTEL is not set |
| 893 | # CONFIG_SND_HDSP is not set | 972 | # CONFIG_SND_HDSP is not set |
| 894 | # CONFIG_SND_HDSPM is not set | 973 | # CONFIG_SND_HDSPM is not set |
| 974 | # CONFIG_SND_HIFIER is not set | ||
| 895 | # CONFIG_SND_ICE1712 is not set | 975 | # CONFIG_SND_ICE1712 is not set |
| 896 | # CONFIG_SND_ICE1724 is not set | 976 | # CONFIG_SND_ICE1724 is not set |
| 897 | # CONFIG_SND_INTEL8X0 is not set | 977 | # CONFIG_SND_INTEL8X0 is not set |
| @@ -909,47 +989,59 @@ CONFIG_SND_AD1889=y | |||
| 909 | # CONFIG_SND_TRIDENT is not set | 989 | # CONFIG_SND_TRIDENT is not set |
| 910 | # CONFIG_SND_VIA82XX is not set | 990 | # CONFIG_SND_VIA82XX is not set |
| 911 | # CONFIG_SND_VIA82XX_MODEM is not set | 991 | # CONFIG_SND_VIA82XX_MODEM is not set |
| 992 | # CONFIG_SND_VIRTUOSO is not set | ||
| 912 | # CONFIG_SND_VX222 is not set | 993 | # CONFIG_SND_VX222 is not set |
| 913 | # CONFIG_SND_YMFPCI is not set | 994 | # CONFIG_SND_YMFPCI is not set |
| 914 | # CONFIG_SND_AC97_POWER_SAVE is not set | 995 | CONFIG_SND_USB=y |
| 915 | |||
| 916 | # | ||
| 917 | # USB devices | ||
| 918 | # | ||
| 919 | # CONFIG_SND_USB_AUDIO is not set | 996 | # CONFIG_SND_USB_AUDIO is not set |
| 920 | # CONFIG_SND_USB_CAIAQ is not set | 997 | # CONFIG_SND_USB_CAIAQ is not set |
| 921 | |||
| 922 | # | ||
| 923 | # System on Chip audio support | ||
| 924 | # | ||
| 925 | # CONFIG_SND_SOC is not set | 998 | # CONFIG_SND_SOC is not set |
| 926 | |||
| 927 | # | ||
| 928 | # SoC Audio support for SuperH | ||
| 929 | # | ||
| 930 | |||
| 931 | # | ||
| 932 | # Open Sound System | ||
| 933 | # | ||
| 934 | # CONFIG_SOUND_PRIME is not set | 999 | # CONFIG_SOUND_PRIME is not set |
| 935 | CONFIG_AC97_BUS=y | 1000 | CONFIG_AC97_BUS=y |
| 936 | CONFIG_HID_SUPPORT=y | 1001 | CONFIG_HID_SUPPORT=y |
| 937 | CONFIG_HID=y | 1002 | CONFIG_HID=y |
| 938 | # CONFIG_HID_DEBUG is not set | 1003 | # CONFIG_HID_DEBUG is not set |
| 1004 | # CONFIG_HIDRAW is not set | ||
| 939 | 1005 | ||
| 940 | # | 1006 | # |
| 941 | # USB Input Devices | 1007 | # USB Input Devices |
| 942 | # | 1008 | # |
| 943 | CONFIG_USB_HID=y | 1009 | CONFIG_USB_HID=y |
| 944 | # CONFIG_USB_HIDINPUT_POWERBOOK is not set | 1010 | # CONFIG_HID_PID is not set |
| 945 | # CONFIG_HID_FF is not set | ||
| 946 | CONFIG_USB_HIDDEV=y | 1011 | CONFIG_USB_HIDDEV=y |
| 1012 | |||
| 1013 | # | ||
| 1014 | # Special HID drivers | ||
| 1015 | # | ||
| 1016 | CONFIG_HID_COMPAT=y | ||
| 1017 | # CONFIG_HID_A4TECH is not set | ||
| 1018 | # CONFIG_HID_APPLE is not set | ||
| 1019 | # CONFIG_HID_BELKIN is not set | ||
| 1020 | # CONFIG_HID_CHERRY is not set | ||
| 1021 | # CONFIG_HID_CHICONY is not set | ||
| 1022 | # CONFIG_HID_CYPRESS is not set | ||
| 1023 | # CONFIG_HID_EZKEY is not set | ||
| 1024 | # CONFIG_HID_GYRATION is not set | ||
| 1025 | # CONFIG_HID_LOGITECH is not set | ||
| 1026 | # CONFIG_HID_MICROSOFT is not set | ||
| 1027 | # CONFIG_HID_MONTEREY is not set | ||
| 1028 | # CONFIG_HID_NTRIG is not set | ||
| 1029 | # CONFIG_HID_PANTHERLORD is not set | ||
| 1030 | # CONFIG_HID_PETALYNX is not set | ||
| 1031 | # CONFIG_HID_SAMSUNG is not set | ||
| 1032 | # CONFIG_HID_SONY is not set | ||
| 1033 | # CONFIG_HID_SUNPLUS is not set | ||
| 1034 | # CONFIG_GREENASIA_FF is not set | ||
| 1035 | # CONFIG_HID_TOPSEED is not set | ||
| 1036 | # CONFIG_THRUSTMASTER_FF is not set | ||
| 1037 | # CONFIG_ZEROPLUS_FF is not set | ||
| 947 | CONFIG_USB_SUPPORT=y | 1038 | CONFIG_USB_SUPPORT=y |
| 948 | CONFIG_USB_ARCH_HAS_HCD=y | 1039 | CONFIG_USB_ARCH_HAS_HCD=y |
| 949 | CONFIG_USB_ARCH_HAS_OHCI=y | 1040 | CONFIG_USB_ARCH_HAS_OHCI=y |
| 950 | CONFIG_USB_ARCH_HAS_EHCI=y | 1041 | CONFIG_USB_ARCH_HAS_EHCI=y |
| 951 | CONFIG_USB=y | 1042 | CONFIG_USB=y |
| 952 | CONFIG_USB_DEBUG=y | 1043 | CONFIG_USB_DEBUG=y |
| 1044 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 953 | 1045 | ||
| 954 | # | 1046 | # |
| 955 | # Miscellaneous USB options | 1047 | # Miscellaneous USB options |
| @@ -958,12 +1050,20 @@ CONFIG_USB_DEVICEFS=y | |||
| 958 | CONFIG_USB_DEVICE_CLASS=y | 1050 | CONFIG_USB_DEVICE_CLASS=y |
| 959 | # CONFIG_USB_DYNAMIC_MINORS is not set | 1051 | # CONFIG_USB_DYNAMIC_MINORS is not set |
| 960 | # CONFIG_USB_OTG is not set | 1052 | # CONFIG_USB_OTG is not set |
| 1053 | # CONFIG_USB_OTG_WHITELIST is not set | ||
| 1054 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
| 1055 | # CONFIG_USB_MON is not set | ||
| 1056 | # CONFIG_USB_WUSB is not set | ||
| 1057 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 961 | 1058 | ||
| 962 | # | 1059 | # |
| 963 | # USB Host Controller Drivers | 1060 | # USB Host Controller Drivers |
| 964 | # | 1061 | # |
| 1062 | # CONFIG_USB_C67X00_HCD is not set | ||
| 965 | # CONFIG_USB_EHCI_HCD is not set | 1063 | # CONFIG_USB_EHCI_HCD is not set |
| 1064 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 966 | # CONFIG_USB_ISP116X_HCD is not set | 1065 | # CONFIG_USB_ISP116X_HCD is not set |
| 1066 | # CONFIG_USB_ISP1760_HCD is not set | ||
| 967 | CONFIG_USB_OHCI_HCD=y | 1067 | CONFIG_USB_OHCI_HCD=y |
| 968 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | 1068 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set |
| 969 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | 1069 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set |
| @@ -971,32 +1071,37 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y | |||
| 971 | # CONFIG_USB_UHCI_HCD is not set | 1071 | # CONFIG_USB_UHCI_HCD is not set |
| 972 | # CONFIG_USB_SL811_HCD is not set | 1072 | # CONFIG_USB_SL811_HCD is not set |
| 973 | # CONFIG_USB_R8A66597_HCD is not set | 1073 | # CONFIG_USB_R8A66597_HCD is not set |
| 1074 | # CONFIG_USB_WHCI_HCD is not set | ||
| 1075 | # CONFIG_USB_HWA_HCD is not set | ||
| 974 | 1076 | ||
| 975 | # | 1077 | # |
| 976 | # USB Device Class drivers | 1078 | # USB Device Class drivers |
| 977 | # | 1079 | # |
| 978 | # CONFIG_USB_ACM is not set | 1080 | # CONFIG_USB_ACM is not set |
| 979 | CONFIG_USB_PRINTER=m | 1081 | CONFIG_USB_PRINTER=m |
| 1082 | # CONFIG_USB_WDM is not set | ||
| 1083 | # CONFIG_USB_TMC is not set | ||
| 980 | 1084 | ||
| 981 | # | 1085 | # |
| 982 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 1086 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; |
| 983 | # | 1087 | # |
| 984 | 1088 | ||
| 985 | # | 1089 | # |
| 986 | # may also be needed; see USB_STORAGE Help for more information | 1090 | # see USB_STORAGE Help for more information |
| 987 | # | 1091 | # |
| 988 | CONFIG_USB_STORAGE=m | 1092 | CONFIG_USB_STORAGE=m |
| 989 | # CONFIG_USB_STORAGE_DEBUG is not set | 1093 | # CONFIG_USB_STORAGE_DEBUG is not set |
| 990 | # CONFIG_USB_STORAGE_DATAFAB is not set | 1094 | # CONFIG_USB_STORAGE_DATAFAB is not set |
| 991 | # CONFIG_USB_STORAGE_FREECOM is not set | 1095 | # CONFIG_USB_STORAGE_FREECOM is not set |
| 992 | # CONFIG_USB_STORAGE_ISD200 is not set | 1096 | # CONFIG_USB_STORAGE_ISD200 is not set |
| 993 | CONFIG_USB_STORAGE_DPCM=y | ||
| 994 | CONFIG_USB_STORAGE_USBAT=y | 1097 | CONFIG_USB_STORAGE_USBAT=y |
| 995 | CONFIG_USB_STORAGE_SDDR09=y | 1098 | CONFIG_USB_STORAGE_SDDR09=y |
| 996 | CONFIG_USB_STORAGE_SDDR55=y | 1099 | CONFIG_USB_STORAGE_SDDR55=y |
| 997 | CONFIG_USB_STORAGE_JUMPSHOT=y | 1100 | CONFIG_USB_STORAGE_JUMPSHOT=y |
| 998 | # CONFIG_USB_STORAGE_ALAUDA is not set | 1101 | # CONFIG_USB_STORAGE_ALAUDA is not set |
| 1102 | # CONFIG_USB_STORAGE_ONETOUCH is not set | ||
| 999 | # CONFIG_USB_STORAGE_KARMA is not set | 1103 | # CONFIG_USB_STORAGE_KARMA is not set |
| 1104 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | ||
| 1000 | # CONFIG_USB_LIBUSUAL is not set | 1105 | # CONFIG_USB_LIBUSUAL is not set |
| 1001 | 1106 | ||
| 1002 | # | 1107 | # |
| @@ -1004,15 +1109,10 @@ CONFIG_USB_STORAGE_JUMPSHOT=y | |||
| 1004 | # | 1109 | # |
| 1005 | CONFIG_USB_MDC800=m | 1110 | CONFIG_USB_MDC800=m |
| 1006 | CONFIG_USB_MICROTEK=m | 1111 | CONFIG_USB_MICROTEK=m |
| 1007 | # CONFIG_USB_MON is not set | ||
| 1008 | 1112 | ||
| 1009 | # | 1113 | # |
| 1010 | # USB port drivers | 1114 | # USB port drivers |
| 1011 | # | 1115 | # |
| 1012 | |||
| 1013 | # | ||
| 1014 | # USB Serial Converter support | ||
| 1015 | # | ||
| 1016 | # CONFIG_USB_SERIAL is not set | 1116 | # CONFIG_USB_SERIAL is not set |
| 1017 | 1117 | ||
| 1018 | # | 1118 | # |
| @@ -1021,7 +1121,7 @@ CONFIG_USB_MICROTEK=m | |||
| 1021 | # CONFIG_USB_EMI62 is not set | 1121 | # CONFIG_USB_EMI62 is not set |
| 1022 | # CONFIG_USB_EMI26 is not set | 1122 | # CONFIG_USB_EMI26 is not set |
| 1023 | # CONFIG_USB_ADUTUX is not set | 1123 | # CONFIG_USB_ADUTUX is not set |
| 1024 | # CONFIG_USB_AUERSWALD is not set | 1124 | # CONFIG_USB_SEVSEG is not set |
| 1025 | # CONFIG_USB_RIO500 is not set | 1125 | # CONFIG_USB_RIO500 is not set |
| 1026 | CONFIG_USB_LEGOTOWER=m | 1126 | CONFIG_USB_LEGOTOWER=m |
| 1027 | # CONFIG_USB_LCD is not set | 1127 | # CONFIG_USB_LCD is not set |
| @@ -1037,37 +1137,59 @@ CONFIG_USB_LEGOTOWER=m | |||
| 1037 | # CONFIG_USB_TRANCEVIBRATOR is not set | 1137 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 1038 | # CONFIG_USB_IOWARRIOR is not set | 1138 | # CONFIG_USB_IOWARRIOR is not set |
| 1039 | # CONFIG_USB_TEST is not set | 1139 | # CONFIG_USB_TEST is not set |
| 1140 | # CONFIG_USB_ISIGHTFW is not set | ||
| 1141 | # CONFIG_USB_VST is not set | ||
| 1142 | # CONFIG_USB_GADGET is not set | ||
| 1040 | 1143 | ||
| 1041 | # | 1144 | # |
| 1042 | # USB DSL modem support | 1145 | # OTG and related infrastructure |
| 1043 | # | ||
| 1044 | |||
| 1045 | # | ||
| 1046 | # USB Gadget Support | ||
| 1047 | # | 1146 | # |
| 1048 | # CONFIG_USB_GADGET is not set | 1147 | # CONFIG_UWB is not set |
| 1049 | # CONFIG_MMC is not set | 1148 | # CONFIG_MMC is not set |
| 1149 | # CONFIG_MEMSTICK is not set | ||
| 1050 | # CONFIG_NEW_LEDS is not set | 1150 | # CONFIG_NEW_LEDS is not set |
| 1151 | # CONFIG_ACCESSIBILITY is not set | ||
| 1051 | # CONFIG_INFINIBAND is not set | 1152 | # CONFIG_INFINIBAND is not set |
| 1052 | # CONFIG_RTC_CLASS is not set | 1153 | CONFIG_RTC_LIB=y |
| 1154 | CONFIG_RTC_CLASS=y | ||
| 1155 | CONFIG_RTC_HCTOSYS=y | ||
| 1156 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 1157 | # CONFIG_RTC_DEBUG is not set | ||
| 1053 | 1158 | ||
| 1054 | # | 1159 | # |
| 1055 | # DMA Engine support | 1160 | # RTC interfaces |
| 1056 | # | 1161 | # |
| 1057 | # CONFIG_DMA_ENGINE is not set | 1162 | CONFIG_RTC_INTF_SYSFS=y |
| 1163 | CONFIG_RTC_INTF_PROC=y | ||
| 1164 | CONFIG_RTC_INTF_DEV=y | ||
| 1165 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 1166 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1058 | 1167 | ||
| 1059 | # | 1168 | # |
| 1060 | # DMA Clients | 1169 | # SPI RTC drivers |
| 1061 | # | 1170 | # |
| 1062 | 1171 | ||
| 1063 | # | 1172 | # |
| 1064 | # DMA Devices | 1173 | # Platform RTC drivers |
| 1065 | # | 1174 | # |
| 1175 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1176 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1177 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1178 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1179 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1180 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1181 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1182 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1183 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1184 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 1066 | 1185 | ||
| 1067 | # | 1186 | # |
| 1068 | # Userspace I/O | 1187 | # on-CPU RTC drivers |
| 1069 | # | 1188 | # |
| 1189 | CONFIG_RTC_DRV_PARISC=y | ||
| 1190 | # CONFIG_DMADEVICES is not set | ||
| 1070 | # CONFIG_UIO is not set | 1191 | # CONFIG_UIO is not set |
| 1192 | # CONFIG_STAGING is not set | ||
| 1071 | 1193 | ||
| 1072 | # | 1194 | # |
| 1073 | # File systems | 1195 | # File systems |
| @@ -1077,25 +1199,24 @@ CONFIG_EXT2_FS=y | |||
| 1077 | # CONFIG_EXT2_FS_XIP is not set | 1199 | # CONFIG_EXT2_FS_XIP is not set |
| 1078 | CONFIG_EXT3_FS=y | 1200 | CONFIG_EXT3_FS=y |
| 1079 | # CONFIG_EXT3_FS_XATTR is not set | 1201 | # CONFIG_EXT3_FS_XATTR is not set |
| 1080 | # CONFIG_EXT4DEV_FS is not set | 1202 | # CONFIG_EXT4_FS is not set |
| 1081 | CONFIG_JBD=y | 1203 | CONFIG_JBD=y |
| 1082 | # CONFIG_JBD_DEBUG is not set | 1204 | # CONFIG_JBD_DEBUG is not set |
| 1083 | # CONFIG_REISERFS_FS is not set | 1205 | # CONFIG_REISERFS_FS is not set |
| 1084 | # CONFIG_JFS_FS is not set | 1206 | # CONFIG_JFS_FS is not set |
| 1085 | # CONFIG_FS_POSIX_ACL is not set | 1207 | # CONFIG_FS_POSIX_ACL is not set |
| 1208 | CONFIG_FILE_LOCKING=y | ||
| 1086 | CONFIG_XFS_FS=m | 1209 | CONFIG_XFS_FS=m |
| 1087 | # CONFIG_XFS_QUOTA is not set | 1210 | # CONFIG_XFS_QUOTA is not set |
| 1088 | # CONFIG_XFS_SECURITY is not set | ||
| 1089 | # CONFIG_XFS_POSIX_ACL is not set | 1211 | # CONFIG_XFS_POSIX_ACL is not set |
| 1090 | # CONFIG_XFS_RT is not set | 1212 | # CONFIG_XFS_RT is not set |
| 1091 | # CONFIG_GFS2_FS is not set | 1213 | # CONFIG_XFS_DEBUG is not set |
| 1092 | # CONFIG_OCFS2_FS is not set | 1214 | # CONFIG_OCFS2_FS is not set |
| 1093 | # CONFIG_MINIX_FS is not set | 1215 | # CONFIG_BTRFS_FS is not set |
| 1094 | # CONFIG_ROMFS_FS is not set | 1216 | CONFIG_DNOTIFY=y |
| 1095 | CONFIG_INOTIFY=y | 1217 | CONFIG_INOTIFY=y |
| 1096 | CONFIG_INOTIFY_USER=y | 1218 | CONFIG_INOTIFY_USER=y |
| 1097 | # CONFIG_QUOTA is not set | 1219 | # CONFIG_QUOTA is not set |
| 1098 | CONFIG_DNOTIFY=y | ||
| 1099 | # CONFIG_AUTOFS_FS is not set | 1220 | # CONFIG_AUTOFS_FS is not set |
| 1100 | CONFIG_AUTOFS4_FS=y | 1221 | CONFIG_AUTOFS4_FS=y |
| 1101 | # CONFIG_FUSE_FS is not set | 1222 | # CONFIG_FUSE_FS is not set |
| @@ -1124,16 +1245,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | |||
| 1124 | CONFIG_PROC_FS=y | 1245 | CONFIG_PROC_FS=y |
| 1125 | CONFIG_PROC_KCORE=y | 1246 | CONFIG_PROC_KCORE=y |
| 1126 | CONFIG_PROC_SYSCTL=y | 1247 | CONFIG_PROC_SYSCTL=y |
| 1248 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1127 | CONFIG_SYSFS=y | 1249 | CONFIG_SYSFS=y |
| 1128 | CONFIG_TMPFS=y | 1250 | CONFIG_TMPFS=y |
| 1129 | # CONFIG_TMPFS_POSIX_ACL is not set | 1251 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 1130 | # CONFIG_HUGETLB_PAGE is not set | 1252 | # CONFIG_HUGETLB_PAGE is not set |
| 1131 | CONFIG_RAMFS=y | ||
| 1132 | # CONFIG_CONFIGFS_FS is not set | 1253 | # CONFIG_CONFIGFS_FS is not set |
| 1133 | 1254 | CONFIG_MISC_FILESYSTEMS=y | |
| 1134 | # | ||
| 1135 | # Miscellaneous filesystems | ||
| 1136 | # | ||
| 1137 | # CONFIG_ADFS_FS is not set | 1255 | # CONFIG_ADFS_FS is not set |
| 1138 | # CONFIG_AFFS_FS is not set | 1256 | # CONFIG_AFFS_FS is not set |
| 1139 | # CONFIG_HFS_FS is not set | 1257 | # CONFIG_HFS_FS is not set |
| @@ -1142,32 +1260,31 @@ CONFIG_RAMFS=y | |||
| 1142 | # CONFIG_BFS_FS is not set | 1260 | # CONFIG_BFS_FS is not set |
| 1143 | # CONFIG_EFS_FS is not set | 1261 | # CONFIG_EFS_FS is not set |
| 1144 | # CONFIG_CRAMFS is not set | 1262 | # CONFIG_CRAMFS is not set |
| 1263 | # CONFIG_SQUASHFS is not set | ||
| 1145 | # CONFIG_VXFS_FS is not set | 1264 | # CONFIG_VXFS_FS is not set |
| 1265 | # CONFIG_MINIX_FS is not set | ||
| 1266 | # CONFIG_OMFS_FS is not set | ||
| 1146 | # CONFIG_HPFS_FS is not set | 1267 | # CONFIG_HPFS_FS is not set |
| 1147 | # CONFIG_QNX4FS_FS is not set | 1268 | # CONFIG_QNX4FS_FS is not set |
| 1269 | # CONFIG_ROMFS_FS is not set | ||
| 1148 | # CONFIG_SYSV_FS is not set | 1270 | # CONFIG_SYSV_FS is not set |
| 1149 | # CONFIG_UFS_FS is not set | 1271 | # CONFIG_UFS_FS is not set |
| 1150 | 1272 | CONFIG_NETWORK_FILESYSTEMS=y | |
| 1151 | # | ||
| 1152 | # Network File Systems | ||
| 1153 | # | ||
| 1154 | CONFIG_NFS_FS=y | 1273 | CONFIG_NFS_FS=y |
| 1155 | CONFIG_NFS_V3=y | 1274 | CONFIG_NFS_V3=y |
| 1156 | # CONFIG_NFS_V3_ACL is not set | 1275 | # CONFIG_NFS_V3_ACL is not set |
| 1157 | # CONFIG_NFS_V4 is not set | 1276 | # CONFIG_NFS_V4 is not set |
| 1158 | # CONFIG_NFS_DIRECTIO is not set | 1277 | CONFIG_ROOT_NFS=y |
| 1159 | CONFIG_NFSD=y | 1278 | CONFIG_NFSD=y |
| 1160 | CONFIG_NFSD_V3=y | 1279 | CONFIG_NFSD_V3=y |
| 1161 | # CONFIG_NFSD_V3_ACL is not set | 1280 | # CONFIG_NFSD_V3_ACL is not set |
| 1162 | # CONFIG_NFSD_V4 is not set | 1281 | # CONFIG_NFSD_V4 is not set |
| 1163 | # CONFIG_NFSD_TCP is not set | ||
| 1164 | CONFIG_ROOT_NFS=y | ||
| 1165 | CONFIG_LOCKD=y | 1282 | CONFIG_LOCKD=y |
| 1166 | CONFIG_LOCKD_V4=y | 1283 | CONFIG_LOCKD_V4=y |
| 1167 | CONFIG_EXPORTFS=y | 1284 | CONFIG_EXPORTFS=y |
| 1168 | CONFIG_NFS_COMMON=y | 1285 | CONFIG_NFS_COMMON=y |
| 1169 | CONFIG_SUNRPC=y | 1286 | CONFIG_SUNRPC=y |
| 1170 | # CONFIG_SUNRPC_BIND34 is not set | 1287 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 1171 | # CONFIG_RPCSEC_GSS_KRB5 is not set | 1288 | # CONFIG_RPCSEC_GSS_KRB5 is not set |
| 1172 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1289 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1173 | # CONFIG_SMB_FS is not set | 1290 | # CONFIG_SMB_FS is not set |
| @@ -1181,10 +1298,6 @@ CONFIG_SUNRPC=y | |||
| 1181 | # | 1298 | # |
| 1182 | # CONFIG_PARTITION_ADVANCED is not set | 1299 | # CONFIG_PARTITION_ADVANCED is not set |
| 1183 | CONFIG_MSDOS_PARTITION=y | 1300 | CONFIG_MSDOS_PARTITION=y |
| 1184 | |||
| 1185 | # | ||
| 1186 | # Native Language Support | ||
| 1187 | # | ||
| 1188 | CONFIG_NLS=y | 1301 | CONFIG_NLS=y |
| 1189 | CONFIG_NLS_DEFAULT="iso8859-1" | 1302 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 1190 | CONFIG_NLS_CODEPAGE_437=m | 1303 | CONFIG_NLS_CODEPAGE_437=m |
| @@ -1225,33 +1338,28 @@ CONFIG_NLS_ISO8859_15=m | |||
| 1225 | # CONFIG_NLS_KOI8_R is not set | 1338 | # CONFIG_NLS_KOI8_R is not set |
| 1226 | # CONFIG_NLS_KOI8_U is not set | 1339 | # CONFIG_NLS_KOI8_U is not set |
| 1227 | CONFIG_NLS_UTF8=m | 1340 | CONFIG_NLS_UTF8=m |
| 1228 | |||
| 1229 | # | ||
| 1230 | # Distributed Lock Manager | ||
| 1231 | # | ||
| 1232 | # CONFIG_DLM is not set | 1341 | # CONFIG_DLM is not set |
| 1233 | 1342 | ||
| 1234 | # | 1343 | # |
| 1235 | # Profiling support | ||
| 1236 | # | ||
| 1237 | CONFIG_PROFILING=y | ||
| 1238 | CONFIG_OPROFILE=m | ||
| 1239 | |||
| 1240 | # | ||
| 1241 | # Kernel hacking | 1344 | # Kernel hacking |
| 1242 | # | 1345 | # |
| 1243 | # CONFIG_PRINTK_TIME is not set | 1346 | # CONFIG_PRINTK_TIME is not set |
| 1347 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1244 | CONFIG_ENABLE_MUST_CHECK=y | 1348 | CONFIG_ENABLE_MUST_CHECK=y |
| 1349 | CONFIG_FRAME_WARN=1024 | ||
| 1245 | CONFIG_MAGIC_SYSRQ=y | 1350 | CONFIG_MAGIC_SYSRQ=y |
| 1246 | # CONFIG_UNUSED_SYMBOLS is not set | 1351 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1247 | # CONFIG_DEBUG_FS is not set | 1352 | CONFIG_DEBUG_FS=y |
| 1248 | CONFIG_HEADERS_CHECK=y | 1353 | CONFIG_HEADERS_CHECK=y |
| 1249 | CONFIG_DEBUG_KERNEL=y | 1354 | CONFIG_DEBUG_KERNEL=y |
| 1250 | # CONFIG_DEBUG_SHIRQ is not set | 1355 | # CONFIG_DEBUG_SHIRQ is not set |
| 1251 | CONFIG_DETECT_SOFTLOCKUP=y | 1356 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1357 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1358 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1252 | CONFIG_SCHED_DEBUG=y | 1359 | CONFIG_SCHED_DEBUG=y |
| 1253 | # CONFIG_SCHEDSTATS is not set | 1360 | # CONFIG_SCHEDSTATS is not set |
| 1254 | # CONFIG_TIMER_STATS is not set | 1361 | # CONFIG_TIMER_STATS is not set |
| 1362 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1255 | # CONFIG_DEBUG_SLAB is not set | 1363 | # CONFIG_DEBUG_SLAB is not set |
| 1256 | # CONFIG_DEBUG_RT_MUTEXES is not set | 1364 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| 1257 | # CONFIG_RT_MUTEX_TESTER is not set | 1365 | # CONFIG_RT_MUTEX_TESTER is not set |
| @@ -1263,10 +1371,33 @@ CONFIG_DEBUG_MUTEXES=y | |||
| 1263 | # CONFIG_DEBUG_BUGVERBOSE is not set | 1371 | # CONFIG_DEBUG_BUGVERBOSE is not set |
| 1264 | # CONFIG_DEBUG_INFO is not set | 1372 | # CONFIG_DEBUG_INFO is not set |
| 1265 | # CONFIG_DEBUG_VM is not set | 1373 | # CONFIG_DEBUG_VM is not set |
| 1374 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1375 | # CONFIG_DEBUG_MEMORY_INIT is not set | ||
| 1266 | # CONFIG_DEBUG_LIST is not set | 1376 | # CONFIG_DEBUG_LIST is not set |
| 1267 | CONFIG_FORCED_INLINING=y | 1377 | # CONFIG_DEBUG_SG is not set |
| 1378 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1379 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1268 | # CONFIG_RCU_TORTURE_TEST is not set | 1380 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1381 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1382 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1383 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1269 | # CONFIG_FAULT_INJECTION is not set | 1384 | # CONFIG_FAULT_INJECTION is not set |
| 1385 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1386 | CONFIG_NOP_TRACER=y | ||
| 1387 | CONFIG_RING_BUFFER=y | ||
| 1388 | CONFIG_TRACING=y | ||
| 1389 | |||
| 1390 | # | ||
| 1391 | # Tracers | ||
| 1392 | # | ||
| 1393 | # CONFIG_SCHED_TRACER is not set | ||
| 1394 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1395 | # CONFIG_BOOT_TRACER is not set | ||
| 1396 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1397 | # CONFIG_FTRACE_STARTUP_TEST is not set | ||
| 1398 | # CONFIG_BUILD_DOCSRC is not set | ||
| 1399 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1400 | # CONFIG_SAMPLES is not set | ||
| 1270 | CONFIG_DEBUG_RODATA=y | 1401 | CONFIG_DEBUG_RODATA=y |
| 1271 | 1402 | ||
| 1272 | # | 1403 | # |
| @@ -1274,54 +1405,110 @@ CONFIG_DEBUG_RODATA=y | |||
| 1274 | # | 1405 | # |
| 1275 | # CONFIG_KEYS is not set | 1406 | # CONFIG_KEYS is not set |
| 1276 | # CONFIG_SECURITY is not set | 1407 | # CONFIG_SECURITY is not set |
| 1408 | # CONFIG_SECURITYFS is not set | ||
| 1409 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1277 | CONFIG_CRYPTO=y | 1410 | CONFIG_CRYPTO=y |
| 1411 | |||
| 1412 | # | ||
| 1413 | # Crypto core or helper | ||
| 1414 | # | ||
| 1415 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1278 | CONFIG_CRYPTO_ALGAPI=m | 1416 | CONFIG_CRYPTO_ALGAPI=m |
| 1417 | CONFIG_CRYPTO_ALGAPI2=m | ||
| 1418 | CONFIG_CRYPTO_AEAD2=m | ||
| 1279 | CONFIG_CRYPTO_BLKCIPHER=m | 1419 | CONFIG_CRYPTO_BLKCIPHER=m |
| 1420 | CONFIG_CRYPTO_BLKCIPHER2=m | ||
| 1421 | CONFIG_CRYPTO_HASH=m | ||
| 1422 | CONFIG_CRYPTO_HASH2=m | ||
| 1423 | CONFIG_CRYPTO_RNG2=m | ||
| 1280 | CONFIG_CRYPTO_MANAGER=m | 1424 | CONFIG_CRYPTO_MANAGER=m |
| 1425 | CONFIG_CRYPTO_MANAGER2=m | ||
| 1426 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1427 | CONFIG_CRYPTO_NULL=m | ||
| 1428 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1429 | # CONFIG_CRYPTO_AUTHENC is not set | ||
| 1430 | CONFIG_CRYPTO_TEST=m | ||
| 1431 | |||
| 1432 | # | ||
| 1433 | # Authenticated Encryption with Associated Data | ||
| 1434 | # | ||
| 1435 | # CONFIG_CRYPTO_CCM is not set | ||
| 1436 | # CONFIG_CRYPTO_GCM is not set | ||
| 1437 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1438 | |||
| 1439 | # | ||
| 1440 | # Block modes | ||
| 1441 | # | ||
| 1442 | CONFIG_CRYPTO_CBC=m | ||
| 1443 | # CONFIG_CRYPTO_CTR is not set | ||
| 1444 | # CONFIG_CRYPTO_CTS is not set | ||
| 1445 | # CONFIG_CRYPTO_ECB is not set | ||
| 1446 | # CONFIG_CRYPTO_LRW is not set | ||
| 1447 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1448 | # CONFIG_CRYPTO_XTS is not set | ||
| 1449 | |||
| 1450 | # | ||
| 1451 | # Hash modes | ||
| 1452 | # | ||
| 1281 | # CONFIG_CRYPTO_HMAC is not set | 1453 | # CONFIG_CRYPTO_HMAC is not set |
| 1282 | # CONFIG_CRYPTO_XCBC is not set | 1454 | # CONFIG_CRYPTO_XCBC is not set |
| 1283 | CONFIG_CRYPTO_NULL=m | 1455 | |
| 1456 | # | ||
| 1457 | # Digest | ||
| 1458 | # | ||
| 1459 | CONFIG_CRYPTO_CRC32C=m | ||
| 1284 | # CONFIG_CRYPTO_MD4 is not set | 1460 | # CONFIG_CRYPTO_MD4 is not set |
| 1285 | CONFIG_CRYPTO_MD5=m | 1461 | CONFIG_CRYPTO_MD5=m |
| 1462 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | ||
| 1463 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1464 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1465 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1466 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1286 | # CONFIG_CRYPTO_SHA1 is not set | 1467 | # CONFIG_CRYPTO_SHA1 is not set |
| 1287 | # CONFIG_CRYPTO_SHA256 is not set | 1468 | # CONFIG_CRYPTO_SHA256 is not set |
| 1288 | # CONFIG_CRYPTO_SHA512 is not set | 1469 | # CONFIG_CRYPTO_SHA512 is not set |
| 1289 | # CONFIG_CRYPTO_WP512 is not set | ||
| 1290 | # CONFIG_CRYPTO_TGR192 is not set | 1470 | # CONFIG_CRYPTO_TGR192 is not set |
| 1291 | # CONFIG_CRYPTO_GF128MUL is not set | 1471 | # CONFIG_CRYPTO_WP512 is not set |
| 1292 | # CONFIG_CRYPTO_ECB is not set | 1472 | |
| 1293 | CONFIG_CRYPTO_CBC=m | 1473 | # |
| 1294 | # CONFIG_CRYPTO_PCBC is not set | 1474 | # Ciphers |
| 1295 | # CONFIG_CRYPTO_LRW is not set | 1475 | # |
| 1296 | # CONFIG_CRYPTO_XTS is not set | ||
| 1297 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1298 | CONFIG_CRYPTO_DES=m | ||
| 1299 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1300 | CONFIG_CRYPTO_BLOWFISH=m | ||
| 1301 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1302 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1303 | # CONFIG_CRYPTO_AES is not set | 1476 | # CONFIG_CRYPTO_AES is not set |
| 1477 | # CONFIG_CRYPTO_ANUBIS is not set | ||
| 1478 | # CONFIG_CRYPTO_ARC4 is not set | ||
| 1479 | CONFIG_CRYPTO_BLOWFISH=m | ||
| 1480 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1304 | # CONFIG_CRYPTO_CAST5 is not set | 1481 | # CONFIG_CRYPTO_CAST5 is not set |
| 1305 | # CONFIG_CRYPTO_CAST6 is not set | 1482 | # CONFIG_CRYPTO_CAST6 is not set |
| 1306 | # CONFIG_CRYPTO_TEA is not set | 1483 | CONFIG_CRYPTO_DES=m |
| 1307 | # CONFIG_CRYPTO_ARC4 is not set | 1484 | # CONFIG_CRYPTO_FCRYPT is not set |
| 1308 | # CONFIG_CRYPTO_KHAZAD is not set | 1485 | # CONFIG_CRYPTO_KHAZAD is not set |
| 1309 | # CONFIG_CRYPTO_ANUBIS is not set | 1486 | # CONFIG_CRYPTO_SALSA20 is not set |
| 1310 | # CONFIG_CRYPTO_SEED is not set | 1487 | # CONFIG_CRYPTO_SEED is not set |
| 1488 | # CONFIG_CRYPTO_SERPENT is not set | ||
| 1489 | # CONFIG_CRYPTO_TEA is not set | ||
| 1490 | # CONFIG_CRYPTO_TWOFISH is not set | ||
| 1491 | |||
| 1492 | # | ||
| 1493 | # Compression | ||
| 1494 | # | ||
| 1311 | CONFIG_CRYPTO_DEFLATE=m | 1495 | CONFIG_CRYPTO_DEFLATE=m |
| 1312 | # CONFIG_CRYPTO_MICHAEL_MIC is not set | 1496 | # CONFIG_CRYPTO_LZO is not set |
| 1313 | CONFIG_CRYPTO_CRC32C=m | 1497 | |
| 1314 | # CONFIG_CRYPTO_CAMELLIA is not set | 1498 | # |
| 1315 | CONFIG_CRYPTO_TEST=m | 1499 | # Random Number Generation |
| 1316 | # CONFIG_CRYPTO_AUTHENC is not set | 1500 | # |
| 1501 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1317 | # CONFIG_CRYPTO_HW is not set | 1502 | # CONFIG_CRYPTO_HW is not set |
| 1318 | 1503 | ||
| 1319 | # | 1504 | # |
| 1320 | # Library routines | 1505 | # Library routines |
| 1321 | # | 1506 | # |
| 1322 | CONFIG_BITREVERSE=y | 1507 | CONFIG_BITREVERSE=y |
| 1508 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1323 | CONFIG_CRC_CCITT=m | 1509 | CONFIG_CRC_CCITT=m |
| 1324 | # CONFIG_CRC16 is not set | 1510 | # CONFIG_CRC16 is not set |
| 1511 | # CONFIG_CRC_T10DIF is not set | ||
| 1325 | # CONFIG_CRC_ITU_T is not set | 1512 | # CONFIG_CRC_ITU_T is not set |
| 1326 | CONFIG_CRC32=y | 1513 | CONFIG_CRC32=y |
| 1327 | # CONFIG_CRC7 is not set | 1514 | # CONFIG_CRC7 is not set |
diff --git a/arch/parisc/configs/default_defconfig b/arch/parisc/configs/default_defconfig index 448a757b06c6..283a96c1b5ea 100644 --- a/arch/parisc/configs/default_defconfig +++ b/arch/parisc/configs/default_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.23 | 3 | # Linux kernel version: 2.6.29-rc8 |
| 4 | # Fri Oct 12 20:54:57 2007 | 4 | # Fri Mar 13 01:32:59 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_PARISC=y | 6 | CONFIG_PARISC=y |
| 7 | CONFIG_MMU=y | 7 | CONFIG_MMU=y |
| @@ -33,17 +33,35 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 33 | CONFIG_POSIX_MQUEUE=y | 33 | CONFIG_POSIX_MQUEUE=y |
| 34 | # CONFIG_BSD_PROCESS_ACCT is not set | 34 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 35 | # CONFIG_TASKSTATS is not set | 35 | # CONFIG_TASKSTATS is not set |
| 36 | # CONFIG_USER_NS is not set | ||
| 37 | # CONFIG_AUDIT is not set | 36 | # CONFIG_AUDIT is not set |
| 37 | |||
| 38 | # | ||
| 39 | # RCU Subsystem | ||
| 40 | # | ||
| 41 | CONFIG_CLASSIC_RCU=y | ||
| 42 | # CONFIG_TREE_RCU is not set | ||
| 43 | # CONFIG_PREEMPT_RCU is not set | ||
| 44 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 45 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 38 | CONFIG_IKCONFIG=y | 46 | CONFIG_IKCONFIG=y |
| 39 | CONFIG_IKCONFIG_PROC=y | 47 | CONFIG_IKCONFIG_PROC=y |
| 40 | CONFIG_LOG_BUF_SHIFT=16 | 48 | CONFIG_LOG_BUF_SHIFT=16 |
| 49 | # CONFIG_GROUP_SCHED is not set | ||
| 50 | # CONFIG_CGROUPS is not set | ||
| 41 | CONFIG_SYSFS_DEPRECATED=y | 51 | CONFIG_SYSFS_DEPRECATED=y |
| 52 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
| 42 | # CONFIG_RELAY is not set | 53 | # CONFIG_RELAY is not set |
| 54 | CONFIG_NAMESPACES=y | ||
| 55 | # CONFIG_UTS_NS is not set | ||
| 56 | # CONFIG_IPC_NS is not set | ||
| 57 | # CONFIG_USER_NS is not set | ||
| 58 | # CONFIG_PID_NS is not set | ||
| 59 | # CONFIG_NET_NS is not set | ||
| 43 | CONFIG_BLK_DEV_INITRD=y | 60 | CONFIG_BLK_DEV_INITRD=y |
| 44 | CONFIG_INITRAMFS_SOURCE="" | 61 | CONFIG_INITRAMFS_SOURCE="" |
| 45 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 62 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 46 | CONFIG_SYSCTL=y | 63 | CONFIG_SYSCTL=y |
| 64 | CONFIG_ANON_INODES=y | ||
| 47 | # CONFIG_EMBEDDED is not set | 65 | # CONFIG_EMBEDDED is not set |
| 48 | CONFIG_SYSCTL_SYSCALL=y | 66 | CONFIG_SYSCTL_SYSCALL=y |
| 49 | CONFIG_KALLSYMS=y | 67 | CONFIG_KALLSYMS=y |
| @@ -55,29 +73,39 @@ CONFIG_BUG=y | |||
| 55 | CONFIG_ELF_CORE=y | 73 | CONFIG_ELF_CORE=y |
| 56 | CONFIG_BASE_FULL=y | 74 | CONFIG_BASE_FULL=y |
| 57 | CONFIG_FUTEX=y | 75 | CONFIG_FUTEX=y |
| 58 | CONFIG_ANON_INODES=y | ||
| 59 | CONFIG_EPOLL=y | 76 | CONFIG_EPOLL=y |
| 60 | CONFIG_SIGNALFD=y | 77 | CONFIG_SIGNALFD=y |
| 78 | CONFIG_TIMERFD=y | ||
| 61 | CONFIG_EVENTFD=y | 79 | CONFIG_EVENTFD=y |
| 62 | CONFIG_SHMEM=y | 80 | CONFIG_SHMEM=y |
| 81 | CONFIG_AIO=y | ||
| 63 | CONFIG_VM_EVENT_COUNTERS=y | 82 | CONFIG_VM_EVENT_COUNTERS=y |
| 83 | CONFIG_PCI_QUIRKS=y | ||
| 84 | CONFIG_COMPAT_BRK=y | ||
| 64 | CONFIG_SLAB=y | 85 | CONFIG_SLAB=y |
| 65 | # CONFIG_SLUB is not set | 86 | # CONFIG_SLUB is not set |
| 66 | # CONFIG_SLOB is not set | 87 | # CONFIG_SLOB is not set |
| 88 | CONFIG_PROFILING=y | ||
| 89 | CONFIG_TRACEPOINTS=y | ||
| 90 | # CONFIG_MARKERS is not set | ||
| 91 | CONFIG_OPROFILE=m | ||
| 92 | CONFIG_HAVE_OPROFILE=y | ||
| 93 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | ||
| 94 | CONFIG_SLABINFO=y | ||
| 67 | CONFIG_RT_MUTEXES=y | 95 | CONFIG_RT_MUTEXES=y |
| 68 | # CONFIG_TINY_SHMEM is not set | ||
| 69 | CONFIG_BASE_SMALL=0 | 96 | CONFIG_BASE_SMALL=0 |
| 70 | CONFIG_MODULES=y | 97 | CONFIG_MODULES=y |
| 98 | # CONFIG_MODULE_FORCE_LOAD is not set | ||
| 71 | CONFIG_MODULE_UNLOAD=y | 99 | CONFIG_MODULE_UNLOAD=y |
| 72 | CONFIG_MODULE_FORCE_UNLOAD=y | 100 | CONFIG_MODULE_FORCE_UNLOAD=y |
| 73 | # CONFIG_MODVERSIONS is not set | 101 | # CONFIG_MODVERSIONS is not set |
| 74 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 102 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 75 | CONFIG_KMOD=y | 103 | CONFIG_INIT_ALL_POSSIBLE=y |
| 76 | CONFIG_BLOCK=y | 104 | CONFIG_BLOCK=y |
| 77 | # CONFIG_LBD is not set | 105 | # CONFIG_LBD is not set |
| 78 | # CONFIG_BLK_DEV_IO_TRACE is not set | 106 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| 79 | # CONFIG_LSF is not set | ||
| 80 | # CONFIG_BLK_DEV_BSG is not set | 107 | # CONFIG_BLK_DEV_BSG is not set |
| 108 | # CONFIG_BLK_DEV_INTEGRITY is not set | ||
| 81 | 109 | ||
| 82 | # | 110 | # |
| 83 | # IO Schedulers | 111 | # IO Schedulers |
| @@ -91,6 +119,7 @@ CONFIG_DEFAULT_AS=y | |||
| 91 | # CONFIG_DEFAULT_CFQ is not set | 119 | # CONFIG_DEFAULT_CFQ is not set |
| 92 | # CONFIG_DEFAULT_NOOP is not set | 120 | # CONFIG_DEFAULT_NOOP is not set |
| 93 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 121 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 122 | # CONFIG_FREEZER is not set | ||
| 94 | 123 | ||
| 95 | # | 124 | # |
| 96 | # Processor type and features | 125 | # Processor type and features |
| @@ -114,17 +143,19 @@ CONFIG_HZ_250=y | |||
| 114 | # CONFIG_HZ_300 is not set | 143 | # CONFIG_HZ_300 is not set |
| 115 | # CONFIG_HZ_1000 is not set | 144 | # CONFIG_HZ_1000 is not set |
| 116 | CONFIG_HZ=250 | 145 | CONFIG_HZ=250 |
| 146 | # CONFIG_SCHED_HRTICK is not set | ||
| 117 | CONFIG_SELECT_MEMORY_MODEL=y | 147 | CONFIG_SELECT_MEMORY_MODEL=y |
| 118 | CONFIG_FLATMEM_MANUAL=y | 148 | CONFIG_FLATMEM_MANUAL=y |
| 119 | # CONFIG_DISCONTIGMEM_MANUAL is not set | 149 | # CONFIG_DISCONTIGMEM_MANUAL is not set |
| 120 | # CONFIG_SPARSEMEM_MANUAL is not set | 150 | # CONFIG_SPARSEMEM_MANUAL is not set |
| 121 | CONFIG_FLATMEM=y | 151 | CONFIG_FLATMEM=y |
| 122 | CONFIG_FLAT_NODE_MEM_MAP=y | 152 | CONFIG_FLAT_NODE_MEM_MAP=y |
| 123 | # CONFIG_SPARSEMEM_STATIC is not set | 153 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 124 | CONFIG_SPLIT_PTLOCK_CPUS=4096 | 154 | CONFIG_SPLIT_PTLOCK_CPUS=4096 |
| 125 | # CONFIG_RESOURCES_64BIT is not set | 155 | # CONFIG_PHYS_ADDR_T_64BIT is not set |
| 126 | CONFIG_ZONE_DMA_FLAG=0 | 156 | CONFIG_ZONE_DMA_FLAG=0 |
| 127 | CONFIG_VIRT_TO_BUS=y | 157 | CONFIG_VIRT_TO_BUS=y |
| 158 | CONFIG_UNEVICTABLE_LRU=y | ||
| 128 | # CONFIG_HPUX is not set | 159 | # CONFIG_HPUX is not set |
| 129 | 160 | ||
| 130 | # | 161 | # |
| @@ -140,15 +171,14 @@ CONFIG_EISA_NAMES=y | |||
| 140 | # CONFIG_ISA is not set | 171 | # CONFIG_ISA is not set |
| 141 | CONFIG_PCI=y | 172 | CONFIG_PCI=y |
| 142 | # CONFIG_ARCH_SUPPORTS_MSI is not set | 173 | # CONFIG_ARCH_SUPPORTS_MSI is not set |
| 174 | CONFIG_PCI_LEGACY=y | ||
| 143 | # CONFIG_PCI_DEBUG is not set | 175 | # CONFIG_PCI_DEBUG is not set |
| 176 | # CONFIG_PCI_STUB is not set | ||
| 144 | CONFIG_GSC_DINO=y | 177 | CONFIG_GSC_DINO=y |
| 145 | CONFIG_PCI_LBA=y | 178 | CONFIG_PCI_LBA=y |
| 146 | CONFIG_IOSAPIC=y | 179 | CONFIG_IOSAPIC=y |
| 147 | CONFIG_IOMMU_SBA=y | 180 | CONFIG_IOMMU_SBA=y |
| 148 | 181 | CONFIG_IOMMU_HELPER=y | |
| 149 | # | ||
| 150 | # PCCARD (PCMCIA/CardBus) support | ||
| 151 | # | ||
| 152 | CONFIG_PCCARD=y | 182 | CONFIG_PCCARD=y |
| 153 | # CONFIG_PCMCIA_DEBUG is not set | 183 | # CONFIG_PCMCIA_DEBUG is not set |
| 154 | CONFIG_PCMCIA=y | 184 | CONFIG_PCMCIA=y |
| @@ -183,16 +213,15 @@ CONFIG_PDC_STABLE=y | |||
| 183 | # Executable file formats | 213 | # Executable file formats |
| 184 | # | 214 | # |
| 185 | CONFIG_BINFMT_ELF=y | 215 | CONFIG_BINFMT_ELF=y |
| 216 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 217 | # CONFIG_HAVE_AOUT is not set | ||
| 186 | CONFIG_BINFMT_MISC=m | 218 | CONFIG_BINFMT_MISC=m |
| 187 | |||
| 188 | # | ||
| 189 | # Networking | ||
| 190 | # | ||
| 191 | CONFIG_NET=y | 219 | CONFIG_NET=y |
| 192 | 220 | ||
| 193 | # | 221 | # |
| 194 | # Networking options | 222 | # Networking options |
| 195 | # | 223 | # |
| 224 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 196 | CONFIG_PACKET=y | 225 | CONFIG_PACKET=y |
| 197 | CONFIG_PACKET_MMAP=y | 226 | CONFIG_PACKET_MMAP=y |
| 198 | CONFIG_UNIX=y | 227 | CONFIG_UNIX=y |
| @@ -200,6 +229,8 @@ CONFIG_XFRM=y | |||
| 200 | CONFIG_XFRM_USER=m | 229 | CONFIG_XFRM_USER=m |
| 201 | # CONFIG_XFRM_SUB_POLICY is not set | 230 | # CONFIG_XFRM_SUB_POLICY is not set |
| 202 | # CONFIG_XFRM_MIGRATE is not set | 231 | # CONFIG_XFRM_MIGRATE is not set |
| 232 | # CONFIG_XFRM_STATISTICS is not set | ||
| 233 | CONFIG_XFRM_IPCOMP=y | ||
| 203 | CONFIG_NET_KEY=m | 234 | CONFIG_NET_KEY=m |
| 204 | # CONFIG_NET_KEY_MIGRATE is not set | 235 | # CONFIG_NET_KEY_MIGRATE is not set |
| 205 | CONFIG_INET=y | 236 | CONFIG_INET=y |
| @@ -245,8 +276,10 @@ CONFIG_INET6_XFRM_MODE_TUNNEL=y | |||
| 245 | CONFIG_INET6_XFRM_MODE_BEET=y | 276 | CONFIG_INET6_XFRM_MODE_BEET=y |
| 246 | # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set | 277 | # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set |
| 247 | CONFIG_IPV6_SIT=y | 278 | CONFIG_IPV6_SIT=y |
| 279 | CONFIG_IPV6_NDISC_NODETYPE=y | ||
| 248 | # CONFIG_IPV6_TUNNEL is not set | 280 | # CONFIG_IPV6_TUNNEL is not set |
| 249 | # CONFIG_IPV6_MULTIPLE_TABLES is not set | 281 | # CONFIG_IPV6_MULTIPLE_TABLES is not set |
| 282 | # CONFIG_IPV6_MROUTE is not set | ||
| 250 | # CONFIG_NETWORK_SECMARK is not set | 283 | # CONFIG_NETWORK_SECMARK is not set |
| 251 | # CONFIG_NETFILTER is not set | 284 | # CONFIG_NETFILTER is not set |
| 252 | # CONFIG_IP_DCCP is not set | 285 | # CONFIG_IP_DCCP is not set |
| @@ -254,6 +287,7 @@ CONFIG_IPV6_SIT=y | |||
| 254 | # CONFIG_TIPC is not set | 287 | # CONFIG_TIPC is not set |
| 255 | # CONFIG_ATM is not set | 288 | # CONFIG_ATM is not set |
| 256 | # CONFIG_BRIDGE is not set | 289 | # CONFIG_BRIDGE is not set |
| 290 | # CONFIG_NET_DSA is not set | ||
| 257 | # CONFIG_VLAN_8021Q is not set | 291 | # CONFIG_VLAN_8021Q is not set |
| 258 | # CONFIG_DECNET is not set | 292 | # CONFIG_DECNET is not set |
| 259 | CONFIG_LLC=m | 293 | CONFIG_LLC=m |
| @@ -264,28 +298,26 @@ CONFIG_LLC2=m | |||
| 264 | # CONFIG_LAPB is not set | 298 | # CONFIG_LAPB is not set |
| 265 | # CONFIG_ECONET is not set | 299 | # CONFIG_ECONET is not set |
| 266 | # CONFIG_WAN_ROUTER is not set | 300 | # CONFIG_WAN_ROUTER is not set |
| 267 | |||
| 268 | # | ||
| 269 | # QoS and/or fair queueing | ||
| 270 | # | ||
| 271 | # CONFIG_NET_SCHED is not set | 301 | # CONFIG_NET_SCHED is not set |
| 302 | # CONFIG_DCB is not set | ||
| 272 | 303 | ||
| 273 | # | 304 | # |
| 274 | # Network testing | 305 | # Network testing |
| 275 | # | 306 | # |
| 276 | # CONFIG_NET_PKTGEN is not set | 307 | # CONFIG_NET_PKTGEN is not set |
| 277 | # CONFIG_HAMRADIO is not set | 308 | # CONFIG_HAMRADIO is not set |
| 309 | # CONFIG_CAN is not set | ||
| 278 | # CONFIG_IRDA is not set | 310 | # CONFIG_IRDA is not set |
| 279 | # CONFIG_BT is not set | 311 | # CONFIG_BT is not set |
| 280 | # CONFIG_AF_RXRPC is not set | 312 | # CONFIG_AF_RXRPC is not set |
| 281 | 313 | # CONFIG_PHONET is not set | |
| 282 | # | 314 | CONFIG_WIRELESS=y |
| 283 | # Wireless | ||
| 284 | # | ||
| 285 | # CONFIG_CFG80211 is not set | 315 | # CONFIG_CFG80211 is not set |
| 316 | CONFIG_WIRELESS_OLD_REGULATORY=y | ||
| 286 | # CONFIG_WIRELESS_EXT is not set | 317 | # CONFIG_WIRELESS_EXT is not set |
| 318 | # CONFIG_LIB80211 is not set | ||
| 287 | # CONFIG_MAC80211 is not set | 319 | # CONFIG_MAC80211 is not set |
| 288 | # CONFIG_IEEE80211 is not set | 320 | # CONFIG_WIMAX is not set |
| 289 | # CONFIG_RFKILL is not set | 321 | # CONFIG_RFKILL is not set |
| 290 | # CONFIG_NET_9P is not set | 322 | # CONFIG_NET_9P is not set |
| 291 | 323 | ||
| @@ -300,6 +332,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | |||
| 300 | # CONFIG_STANDALONE is not set | 332 | # CONFIG_STANDALONE is not set |
| 301 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | 333 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set |
| 302 | CONFIG_FW_LOADER=y | 334 | CONFIG_FW_LOADER=y |
| 335 | CONFIG_FIRMWARE_IN_KERNEL=y | ||
| 336 | CONFIG_EXTRA_FIRMWARE="" | ||
| 303 | # CONFIG_DEBUG_DRIVER is not set | 337 | # CONFIG_DEBUG_DRIVER is not set |
| 304 | # CONFIG_DEBUG_DEVRES is not set | 338 | # CONFIG_DEBUG_DEVRES is not set |
| 305 | # CONFIG_SYS_HYPERVISOR is not set | 339 | # CONFIG_SYS_HYPERVISOR is not set |
| @@ -330,63 +364,68 @@ CONFIG_BLK_DEV_CRYPTOLOOP=y | |||
| 330 | CONFIG_BLK_DEV_RAM=y | 364 | CONFIG_BLK_DEV_RAM=y |
| 331 | CONFIG_BLK_DEV_RAM_COUNT=16 | 365 | CONFIG_BLK_DEV_RAM_COUNT=16 |
| 332 | CONFIG_BLK_DEV_RAM_SIZE=6144 | 366 | CONFIG_BLK_DEV_RAM_SIZE=6144 |
| 333 | CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 | 367 | # CONFIG_BLK_DEV_XIP is not set |
| 334 | # CONFIG_CDROM_PKTCDVD is not set | 368 | # CONFIG_CDROM_PKTCDVD is not set |
| 335 | # CONFIG_ATA_OVER_ETH is not set | 369 | # CONFIG_ATA_OVER_ETH is not set |
| 370 | # CONFIG_BLK_DEV_HD is not set | ||
| 336 | CONFIG_MISC_DEVICES=y | 371 | CONFIG_MISC_DEVICES=y |
| 337 | # CONFIG_PHANTOM is not set | 372 | # CONFIG_PHANTOM is not set |
| 338 | # CONFIG_EEPROM_93CX6 is not set | ||
| 339 | # CONFIG_SGI_IOC4 is not set | 373 | # CONFIG_SGI_IOC4 is not set |
| 340 | # CONFIG_TIFM_CORE is not set | 374 | # CONFIG_TIFM_CORE is not set |
| 375 | # CONFIG_ENCLOSURE_SERVICES is not set | ||
| 376 | # CONFIG_HP_ILO is not set | ||
| 377 | # CONFIG_C2PORT is not set | ||
| 378 | |||
| 379 | # | ||
| 380 | # EEPROM support | ||
| 381 | # | ||
| 382 | # CONFIG_EEPROM_93CX6 is not set | ||
| 383 | CONFIG_HAVE_IDE=y | ||
| 341 | CONFIG_IDE=y | 384 | CONFIG_IDE=y |
| 342 | CONFIG_BLK_DEV_IDE=y | ||
| 343 | 385 | ||
| 344 | # | 386 | # |
| 345 | # Please see Documentation/ide.txt for help/info on IDE drives | 387 | # Please see Documentation/ide/ide.txt for help/info on IDE drives |
| 346 | # | 388 | # |
| 389 | CONFIG_IDE_ATAPI=y | ||
| 347 | # CONFIG_BLK_DEV_IDE_SATA is not set | 390 | # CONFIG_BLK_DEV_IDE_SATA is not set |
| 348 | CONFIG_BLK_DEV_IDEDISK=y | 391 | CONFIG_IDE_GD=y |
| 349 | CONFIG_IDEDISK_MULTI_MODE=y | 392 | CONFIG_IDE_GD_ATA=y |
| 393 | # CONFIG_IDE_GD_ATAPI is not set | ||
| 350 | CONFIG_BLK_DEV_IDECS=y | 394 | CONFIG_BLK_DEV_IDECS=y |
| 351 | # CONFIG_BLK_DEV_DELKIN is not set | 395 | # CONFIG_BLK_DEV_DELKIN is not set |
| 352 | CONFIG_BLK_DEV_IDECD=y | 396 | CONFIG_BLK_DEV_IDECD=y |
| 397 | CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y | ||
| 353 | # CONFIG_BLK_DEV_IDETAPE is not set | 398 | # CONFIG_BLK_DEV_IDETAPE is not set |
| 354 | # CONFIG_BLK_DEV_IDEFLOPPY is not set | ||
| 355 | CONFIG_BLK_DEV_IDESCSI=y | ||
| 356 | # CONFIG_IDE_TASK_IOCTL is not set | 399 | # CONFIG_IDE_TASK_IOCTL is not set |
| 357 | CONFIG_IDE_PROC_FS=y | 400 | CONFIG_IDE_PROC_FS=y |
| 358 | 401 | ||
| 359 | # | 402 | # |
| 360 | # IDE chipset support/bugfixes | 403 | # IDE chipset support/bugfixes |
| 361 | # | 404 | # |
| 362 | CONFIG_IDE_GENERIC=y | ||
| 363 | # CONFIG_BLK_DEV_PLATFORM is not set | 405 | # CONFIG_BLK_DEV_PLATFORM is not set |
| 406 | CONFIG_BLK_DEV_IDEDMA_SFF=y | ||
| 364 | 407 | ||
| 365 | # | 408 | # |
| 366 | # PCI IDE chipsets support | 409 | # PCI IDE chipsets support |
| 367 | # | 410 | # |
| 368 | CONFIG_BLK_DEV_IDEPCI=y | 411 | CONFIG_BLK_DEV_IDEPCI=y |
| 369 | CONFIG_IDEPCI_SHARE_IRQ=y | ||
| 370 | CONFIG_IDEPCI_PCIBUS_ORDER=y | 412 | CONFIG_IDEPCI_PCIBUS_ORDER=y |
| 371 | # CONFIG_BLK_DEV_OFFBOARD is not set | 413 | # CONFIG_BLK_DEV_OFFBOARD is not set |
| 372 | CONFIG_BLK_DEV_GENERIC=y | 414 | CONFIG_BLK_DEV_GENERIC=y |
| 373 | # CONFIG_BLK_DEV_OPTI621 is not set | 415 | # CONFIG_BLK_DEV_OPTI621 is not set |
| 374 | CONFIG_BLK_DEV_IDEDMA_PCI=y | 416 | CONFIG_BLK_DEV_IDEDMA_PCI=y |
| 375 | # CONFIG_BLK_DEV_IDEDMA_FORCED is not set | ||
| 376 | CONFIG_IDEDMA_ONLYDISK=y | ||
| 377 | # CONFIG_BLK_DEV_AEC62XX is not set | 417 | # CONFIG_BLK_DEV_AEC62XX is not set |
| 378 | # CONFIG_BLK_DEV_ALI15X3 is not set | 418 | # CONFIG_BLK_DEV_ALI15X3 is not set |
| 379 | # CONFIG_BLK_DEV_AMD74XX is not set | 419 | # CONFIG_BLK_DEV_AMD74XX is not set |
| 380 | # CONFIG_BLK_DEV_CMD64X is not set | 420 | # CONFIG_BLK_DEV_CMD64X is not set |
| 381 | # CONFIG_BLK_DEV_TRIFLEX is not set | 421 | # CONFIG_BLK_DEV_TRIFLEX is not set |
| 382 | # CONFIG_BLK_DEV_CY82C693 is not set | ||
| 383 | # CONFIG_BLK_DEV_CS5520 is not set | 422 | # CONFIG_BLK_DEV_CS5520 is not set |
| 384 | # CONFIG_BLK_DEV_CS5530 is not set | 423 | # CONFIG_BLK_DEV_CS5530 is not set |
| 385 | # CONFIG_BLK_DEV_HPT34X is not set | ||
| 386 | # CONFIG_BLK_DEV_HPT366 is not set | 424 | # CONFIG_BLK_DEV_HPT366 is not set |
| 387 | # CONFIG_BLK_DEV_JMICRON is not set | 425 | # CONFIG_BLK_DEV_JMICRON is not set |
| 388 | # CONFIG_BLK_DEV_SC1200 is not set | 426 | # CONFIG_BLK_DEV_SC1200 is not set |
| 389 | # CONFIG_BLK_DEV_PIIX is not set | 427 | # CONFIG_BLK_DEV_PIIX is not set |
| 428 | # CONFIG_BLK_DEV_IT8172 is not set | ||
| 390 | # CONFIG_BLK_DEV_IT8213 is not set | 429 | # CONFIG_BLK_DEV_IT8213 is not set |
| 391 | # CONFIG_BLK_DEV_IT821X is not set | 430 | # CONFIG_BLK_DEV_IT821X is not set |
| 392 | CONFIG_BLK_DEV_NS87415=y | 431 | CONFIG_BLK_DEV_NS87415=y |
| @@ -398,10 +437,7 @@ CONFIG_BLK_DEV_NS87415=y | |||
| 398 | # CONFIG_BLK_DEV_TRM290 is not set | 437 | # CONFIG_BLK_DEV_TRM290 is not set |
| 399 | # CONFIG_BLK_DEV_VIA82CXXX is not set | 438 | # CONFIG_BLK_DEV_VIA82CXXX is not set |
| 400 | # CONFIG_BLK_DEV_TC86C001 is not set | 439 | # CONFIG_BLK_DEV_TC86C001 is not set |
| 401 | # CONFIG_IDE_ARM is not set | ||
| 402 | CONFIG_BLK_DEV_IDEDMA=y | 440 | CONFIG_BLK_DEV_IDEDMA=y |
| 403 | # CONFIG_IDEDMA_IVB is not set | ||
| 404 | # CONFIG_BLK_DEV_HD is not set | ||
| 405 | 441 | ||
| 406 | # | 442 | # |
| 407 | # SCSI device support | 443 | # SCSI device support |
| @@ -440,8 +476,10 @@ CONFIG_SCSI_SPI_ATTRS=y | |||
| 440 | # CONFIG_SCSI_FC_ATTRS is not set | 476 | # CONFIG_SCSI_FC_ATTRS is not set |
| 441 | # CONFIG_SCSI_ISCSI_ATTRS is not set | 477 | # CONFIG_SCSI_ISCSI_ATTRS is not set |
| 442 | # CONFIG_SCSI_SAS_LIBSAS is not set | 478 | # CONFIG_SCSI_SAS_LIBSAS is not set |
| 479 | # CONFIG_SCSI_SRP_ATTRS is not set | ||
| 443 | CONFIG_SCSI_LOWLEVEL=y | 480 | CONFIG_SCSI_LOWLEVEL=y |
| 444 | # CONFIG_ISCSI_TCP is not set | 481 | # CONFIG_ISCSI_TCP is not set |
| 482 | # CONFIG_SCSI_CXGB3_ISCSI is not set | ||
| 445 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set | 483 | # CONFIG_BLK_DEV_3W_XXXX_RAID is not set |
| 446 | # CONFIG_SCSI_3W_9XXX is not set | 484 | # CONFIG_SCSI_3W_9XXX is not set |
| 447 | # CONFIG_SCSI_ACARD is not set | 485 | # CONFIG_SCSI_ACARD is not set |
| @@ -452,11 +490,14 @@ CONFIG_SCSI_LOWLEVEL=y | |||
| 452 | # CONFIG_SCSI_AIC79XX is not set | 490 | # CONFIG_SCSI_AIC79XX is not set |
| 453 | # CONFIG_SCSI_AIC94XX is not set | 491 | # CONFIG_SCSI_AIC94XX is not set |
| 454 | # CONFIG_SCSI_DPT_I2O is not set | 492 | # CONFIG_SCSI_DPT_I2O is not set |
| 493 | # CONFIG_SCSI_ADVANSYS is not set | ||
| 455 | # CONFIG_SCSI_ARCMSR is not set | 494 | # CONFIG_SCSI_ARCMSR is not set |
| 456 | # CONFIG_MEGARAID_NEWGEN is not set | 495 | # CONFIG_MEGARAID_NEWGEN is not set |
| 457 | # CONFIG_MEGARAID_LEGACY is not set | 496 | # CONFIG_MEGARAID_LEGACY is not set |
| 458 | # CONFIG_MEGARAID_SAS is not set | 497 | # CONFIG_MEGARAID_SAS is not set |
| 459 | # CONFIG_SCSI_HPTIOP is not set | 498 | # CONFIG_SCSI_HPTIOP is not set |
| 499 | # CONFIG_LIBFC is not set | ||
| 500 | # CONFIG_FCOE is not set | ||
| 460 | # CONFIG_SCSI_DMX3191D is not set | 501 | # CONFIG_SCSI_DMX3191D is not set |
| 461 | # CONFIG_SCSI_FUTURE_DOMAIN is not set | 502 | # CONFIG_SCSI_FUTURE_DOMAIN is not set |
| 462 | # CONFIG_SCSI_IPS is not set | 503 | # CONFIG_SCSI_IPS is not set |
| @@ -464,6 +505,7 @@ CONFIG_SCSI_LOWLEVEL=y | |||
| 464 | # CONFIG_SCSI_INIA100 is not set | 505 | # CONFIG_SCSI_INIA100 is not set |
| 465 | # CONFIG_SCSI_PPA is not set | 506 | # CONFIG_SCSI_PPA is not set |
| 466 | # CONFIG_SCSI_IMM is not set | 507 | # CONFIG_SCSI_IMM is not set |
| 508 | # CONFIG_SCSI_MVSAS is not set | ||
| 467 | CONFIG_SCSI_LASI700=y | 509 | CONFIG_SCSI_LASI700=y |
| 468 | CONFIG_53C700_LE_ON_BE=y | 510 | CONFIG_53C700_LE_ON_BE=y |
| 469 | # CONFIG_SCSI_STEX is not set | 511 | # CONFIG_SCSI_STEX is not set |
| @@ -487,9 +529,11 @@ CONFIG_SCSI_NCR53C8XX_SYNC=20 | |||
| 487 | # CONFIG_SCSI_DEBUG is not set | 529 | # CONFIG_SCSI_DEBUG is not set |
| 488 | # CONFIG_SCSI_SRP is not set | 530 | # CONFIG_SCSI_SRP is not set |
| 489 | # CONFIG_SCSI_LOWLEVEL_PCMCIA is not set | 531 | # CONFIG_SCSI_LOWLEVEL_PCMCIA is not set |
| 532 | # CONFIG_SCSI_DH is not set | ||
| 490 | # CONFIG_ATA is not set | 533 | # CONFIG_ATA is not set |
| 491 | CONFIG_MD=y | 534 | CONFIG_MD=y |
| 492 | CONFIG_BLK_DEV_MD=y | 535 | CONFIG_BLK_DEV_MD=y |
| 536 | CONFIG_MD_AUTODETECT=y | ||
| 493 | CONFIG_MD_LINEAR=y | 537 | CONFIG_MD_LINEAR=y |
| 494 | CONFIG_MD_RAID0=y | 538 | CONFIG_MD_RAID0=y |
| 495 | CONFIG_MD_RAID1=y | 539 | CONFIG_MD_RAID1=y |
| @@ -505,32 +549,47 @@ CONFIG_BLK_DEV_DM=y | |||
| 505 | # CONFIG_DM_ZERO is not set | 549 | # CONFIG_DM_ZERO is not set |
| 506 | # CONFIG_DM_MULTIPATH is not set | 550 | # CONFIG_DM_MULTIPATH is not set |
| 507 | # CONFIG_DM_DELAY is not set | 551 | # CONFIG_DM_DELAY is not set |
| 552 | # CONFIG_DM_UEVENT is not set | ||
| 553 | # CONFIG_FUSION is not set | ||
| 508 | 554 | ||
| 509 | # | 555 | # |
| 510 | # Fusion MPT device support | 556 | # IEEE 1394 (FireWire) support |
| 511 | # | 557 | # |
| 512 | # CONFIG_FUSION is not set | ||
| 513 | # CONFIG_FUSION_SPI is not set | ||
| 514 | # CONFIG_FUSION_FC is not set | ||
| 515 | # CONFIG_FUSION_SAS is not set | ||
| 516 | 558 | ||
| 517 | # | 559 | # |
| 518 | # IEEE 1394 (FireWire) support | 560 | # Enable only one of the two stacks, unless you know what you are doing |
| 519 | # | 561 | # |
| 520 | # CONFIG_FIREWIRE is not set | 562 | # CONFIG_FIREWIRE is not set |
| 521 | # CONFIG_IEEE1394 is not set | 563 | # CONFIG_IEEE1394 is not set |
| 522 | # CONFIG_I2O is not set | 564 | # CONFIG_I2O is not set |
| 523 | CONFIG_NETDEVICES=y | 565 | CONFIG_NETDEVICES=y |
| 524 | # CONFIG_NETDEVICES_MULTIQUEUE is not set | ||
| 525 | CONFIG_DUMMY=m | 566 | CONFIG_DUMMY=m |
| 526 | CONFIG_BONDING=m | 567 | CONFIG_BONDING=m |
| 527 | # CONFIG_MACVLAN is not set | 568 | # CONFIG_MACVLAN is not set |
| 528 | # CONFIG_EQUALIZER is not set | 569 | # CONFIG_EQUALIZER is not set |
| 529 | CONFIG_TUN=m | 570 | CONFIG_TUN=m |
| 530 | # CONFIG_VETH is not set | 571 | # CONFIG_VETH is not set |
| 531 | # CONFIG_IP1000 is not set | ||
| 532 | # CONFIG_ARCNET is not set | 572 | # CONFIG_ARCNET is not set |
| 533 | # CONFIG_PHYLIB is not set | 573 | CONFIG_PHYLIB=y |
| 574 | |||
| 575 | # | ||
| 576 | # MII PHY device drivers | ||
| 577 | # | ||
| 578 | # CONFIG_MARVELL_PHY is not set | ||
| 579 | # CONFIG_DAVICOM_PHY is not set | ||
| 580 | # CONFIG_QSEMI_PHY is not set | ||
| 581 | # CONFIG_LXT_PHY is not set | ||
| 582 | # CONFIG_CICADA_PHY is not set | ||
| 583 | # CONFIG_VITESSE_PHY is not set | ||
| 584 | # CONFIG_SMSC_PHY is not set | ||
| 585 | # CONFIG_BROADCOM_PHY is not set | ||
| 586 | # CONFIG_ICPLUS_PHY is not set | ||
| 587 | # CONFIG_REALTEK_PHY is not set | ||
| 588 | # CONFIG_NATIONAL_PHY is not set | ||
| 589 | # CONFIG_STE10XP is not set | ||
| 590 | # CONFIG_LSI_ET1011C_PHY is not set | ||
| 591 | # CONFIG_FIXED_PHY is not set | ||
| 592 | # CONFIG_MDIO_BITBANG is not set | ||
| 534 | CONFIG_NET_ETHERNET=y | 593 | CONFIG_NET_ETHERNET=y |
| 535 | CONFIG_MII=m | 594 | CONFIG_MII=m |
| 536 | CONFIG_LASI_82596=y | 595 | CONFIG_LASI_82596=y |
| @@ -550,13 +609,15 @@ CONFIG_TULIP=y | |||
| 550 | # CONFIG_DM9102 is not set | 609 | # CONFIG_DM9102 is not set |
| 551 | # CONFIG_ULI526X is not set | 610 | # CONFIG_ULI526X is not set |
| 552 | # CONFIG_PCMCIA_XIRCOM is not set | 611 | # CONFIG_PCMCIA_XIRCOM is not set |
| 553 | # CONFIG_PCMCIA_XIRTULIP is not set | ||
| 554 | # CONFIG_DEPCA is not set | 612 | # CONFIG_DEPCA is not set |
| 555 | # CONFIG_HP100 is not set | 613 | # CONFIG_HP100 is not set |
| 556 | # CONFIG_IBM_NEW_EMAC_ZMII is not set | 614 | # CONFIG_IBM_NEW_EMAC_ZMII is not set |
| 557 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 615 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 558 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 616 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 559 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 617 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 618 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 619 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 620 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 560 | CONFIG_NET_PCI=y | 621 | CONFIG_NET_PCI=y |
| 561 | # CONFIG_PCNET32 is not set | 622 | # CONFIG_PCNET32 is not set |
| 562 | # CONFIG_AMD8111_ETH is not set | 623 | # CONFIG_AMD8111_ETH is not set |
| @@ -564,7 +625,7 @@ CONFIG_NET_PCI=y | |||
| 564 | # CONFIG_AC3200 is not set | 625 | # CONFIG_AC3200 is not set |
| 565 | # CONFIG_B44 is not set | 626 | # CONFIG_B44 is not set |
| 566 | # CONFIG_FORCEDETH is not set | 627 | # CONFIG_FORCEDETH is not set |
| 567 | # CONFIG_EEPRO100 is not set | 628 | # CONFIG_CS89x0 is not set |
| 568 | # CONFIG_E100 is not set | 629 | # CONFIG_E100 is not set |
| 569 | # CONFIG_LNE390 is not set | 630 | # CONFIG_LNE390 is not set |
| 570 | # CONFIG_FEALNX is not set | 631 | # CONFIG_FEALNX is not set |
| @@ -574,19 +635,24 @@ CONFIG_NET_PCI=y | |||
| 574 | # CONFIG_ES3210 is not set | 635 | # CONFIG_ES3210 is not set |
| 575 | # CONFIG_8139CP is not set | 636 | # CONFIG_8139CP is not set |
| 576 | # CONFIG_8139TOO is not set | 637 | # CONFIG_8139TOO is not set |
| 638 | # CONFIG_R6040 is not set | ||
| 577 | # CONFIG_SIS900 is not set | 639 | # CONFIG_SIS900 is not set |
| 578 | # CONFIG_EPIC100 is not set | 640 | # CONFIG_EPIC100 is not set |
| 641 | # CONFIG_SMSC9420 is not set | ||
| 579 | # CONFIG_SUNDANCE is not set | 642 | # CONFIG_SUNDANCE is not set |
| 580 | # CONFIG_TLAN is not set | 643 | # CONFIG_TLAN is not set |
| 581 | # CONFIG_VIA_RHINE is not set | 644 | # CONFIG_VIA_RHINE is not set |
| 582 | # CONFIG_SC92031 is not set | 645 | # CONFIG_SC92031 is not set |
| 583 | # CONFIG_NET_POCKET is not set | 646 | # CONFIG_NET_POCKET is not set |
| 647 | # CONFIG_ATL2 is not set | ||
| 584 | CONFIG_NETDEV_1000=y | 648 | CONFIG_NETDEV_1000=y |
| 585 | CONFIG_ACENIC=y | 649 | CONFIG_ACENIC=y |
| 586 | # CONFIG_ACENIC_OMIT_TIGON_I is not set | 650 | # CONFIG_ACENIC_OMIT_TIGON_I is not set |
| 587 | # CONFIG_DL2K is not set | 651 | # CONFIG_DL2K is not set |
| 588 | # CONFIG_E1000 is not set | 652 | # CONFIG_E1000 is not set |
| 589 | # CONFIG_E1000E is not set | 653 | # CONFIG_E1000E is not set |
| 654 | # CONFIG_IP1000 is not set | ||
| 655 | # CONFIG_IGB is not set | ||
| 590 | # CONFIG_NS83820 is not set | 656 | # CONFIG_NS83820 is not set |
| 591 | # CONFIG_HAMACHI is not set | 657 | # CONFIG_HAMACHI is not set |
| 592 | # CONFIG_YELLOWFIN is not set | 658 | # CONFIG_YELLOWFIN is not set |
| @@ -594,23 +660,31 @@ CONFIG_ACENIC=y | |||
| 594 | # CONFIG_SIS190 is not set | 660 | # CONFIG_SIS190 is not set |
| 595 | # CONFIG_SKGE is not set | 661 | # CONFIG_SKGE is not set |
| 596 | # CONFIG_SKY2 is not set | 662 | # CONFIG_SKY2 is not set |
| 597 | # CONFIG_SK98LIN is not set | ||
| 598 | # CONFIG_VIA_VELOCITY is not set | 663 | # CONFIG_VIA_VELOCITY is not set |
| 599 | CONFIG_TIGON3=y | 664 | CONFIG_TIGON3=y |
| 600 | # CONFIG_BNX2 is not set | 665 | # CONFIG_BNX2 is not set |
| 601 | # CONFIG_QLA3XXX is not set | 666 | # CONFIG_QLA3XXX is not set |
| 602 | # CONFIG_ATL1 is not set | 667 | # CONFIG_ATL1 is not set |
| 668 | # CONFIG_ATL1E is not set | ||
| 669 | # CONFIG_ATL1C is not set | ||
| 670 | # CONFIG_JME is not set | ||
| 603 | CONFIG_NETDEV_10000=y | 671 | CONFIG_NETDEV_10000=y |
| 604 | # CONFIG_CHELSIO_T1 is not set | 672 | # CONFIG_CHELSIO_T1 is not set |
| 673 | CONFIG_CHELSIO_T3_DEPENDS=y | ||
| 605 | # CONFIG_CHELSIO_T3 is not set | 674 | # CONFIG_CHELSIO_T3 is not set |
| 675 | # CONFIG_ENIC is not set | ||
| 606 | # CONFIG_IXGBE is not set | 676 | # CONFIG_IXGBE is not set |
| 607 | # CONFIG_IXGB is not set | 677 | # CONFIG_IXGB is not set |
| 608 | # CONFIG_S2IO is not set | 678 | # CONFIG_S2IO is not set |
| 609 | # CONFIG_MYRI10GE is not set | 679 | # CONFIG_MYRI10GE is not set |
| 610 | # CONFIG_NETXEN_NIC is not set | 680 | # CONFIG_NETXEN_NIC is not set |
| 611 | # CONFIG_NIU is not set | 681 | # CONFIG_NIU is not set |
| 682 | # CONFIG_MLX4_EN is not set | ||
| 612 | # CONFIG_MLX4_CORE is not set | 683 | # CONFIG_MLX4_CORE is not set |
| 613 | # CONFIG_TEHUTI is not set | 684 | # CONFIG_TEHUTI is not set |
| 685 | # CONFIG_BNX2X is not set | ||
| 686 | # CONFIG_QLGE is not set | ||
| 687 | # CONFIG_SFC is not set | ||
| 614 | # CONFIG_TR is not set | 688 | # CONFIG_TR is not set |
| 615 | 689 | ||
| 616 | # | 690 | # |
| @@ -618,6 +692,11 @@ CONFIG_NETDEV_10000=y | |||
| 618 | # | 692 | # |
| 619 | # CONFIG_WLAN_PRE80211 is not set | 693 | # CONFIG_WLAN_PRE80211 is not set |
| 620 | # CONFIG_WLAN_80211 is not set | 694 | # CONFIG_WLAN_80211 is not set |
| 695 | # CONFIG_IWLWIFI_LEDS is not set | ||
| 696 | |||
| 697 | # | ||
| 698 | # Enable WiMAX (Networking options) to see the WiMAX drivers | ||
| 699 | # | ||
| 621 | 700 | ||
| 622 | # | 701 | # |
| 623 | # USB Network Adapters | 702 | # USB Network Adapters |
| @@ -626,7 +705,6 @@ CONFIG_NETDEV_10000=y | |||
| 626 | # CONFIG_USB_KAWETH is not set | 705 | # CONFIG_USB_KAWETH is not set |
| 627 | # CONFIG_USB_PEGASUS is not set | 706 | # CONFIG_USB_PEGASUS is not set |
| 628 | # CONFIG_USB_RTL8150 is not set | 707 | # CONFIG_USB_RTL8150 is not set |
| 629 | # CONFIG_USB_USBNET_MII is not set | ||
| 630 | # CONFIG_USB_USBNET is not set | 708 | # CONFIG_USB_USBNET is not set |
| 631 | CONFIG_NET_PCMCIA=y | 709 | CONFIG_NET_PCMCIA=y |
| 632 | # CONFIG_PCMCIA_3C589 is not set | 710 | # CONFIG_PCMCIA_3C589 is not set |
| @@ -654,7 +732,6 @@ CONFIG_PPPOE=m | |||
| 654 | # CONFIG_SLIP is not set | 732 | # CONFIG_SLIP is not set |
| 655 | CONFIG_SLHC=m | 733 | CONFIG_SLHC=m |
| 656 | # CONFIG_NET_FC is not set | 734 | # CONFIG_NET_FC is not set |
| 657 | # CONFIG_SHAPER is not set | ||
| 658 | # CONFIG_NETCONSOLE is not set | 735 | # CONFIG_NETCONSOLE is not set |
| 659 | # CONFIG_NETPOLL is not set | 736 | # CONFIG_NETPOLL is not set |
| 660 | # CONFIG_NET_POLL_CONTROLLER is not set | 737 | # CONFIG_NET_POLL_CONTROLLER is not set |
| @@ -676,7 +753,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y | |||
| 676 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 | 753 | CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 |
| 677 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 | 754 | CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 |
| 678 | # CONFIG_INPUT_JOYDEV is not set | 755 | # CONFIG_INPUT_JOYDEV is not set |
| 679 | # CONFIG_INPUT_TSDEV is not set | ||
| 680 | # CONFIG_INPUT_EVDEV is not set | 756 | # CONFIG_INPUT_EVDEV is not set |
| 681 | # CONFIG_INPUT_EVBUG is not set | 757 | # CONFIG_INPUT_EVBUG is not set |
| 682 | 758 | ||
| @@ -699,11 +775,12 @@ CONFIG_MOUSE_PS2=y | |||
| 699 | CONFIG_MOUSE_PS2_ALPS=y | 775 | CONFIG_MOUSE_PS2_ALPS=y |
| 700 | CONFIG_MOUSE_PS2_LOGIPS2PP=y | 776 | CONFIG_MOUSE_PS2_LOGIPS2PP=y |
| 701 | CONFIG_MOUSE_PS2_SYNAPTICS=y | 777 | CONFIG_MOUSE_PS2_SYNAPTICS=y |
| 702 | CONFIG_MOUSE_PS2_LIFEBOOK=y | ||
| 703 | CONFIG_MOUSE_PS2_TRACKPOINT=y | 778 | CONFIG_MOUSE_PS2_TRACKPOINT=y |
| 779 | # CONFIG_MOUSE_PS2_ELANTECH is not set | ||
| 704 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set | 780 | # CONFIG_MOUSE_PS2_TOUCHKIT is not set |
| 705 | CONFIG_MOUSE_SERIAL=y | 781 | CONFIG_MOUSE_SERIAL=y |
| 706 | # CONFIG_MOUSE_APPLETOUCH is not set | 782 | # CONFIG_MOUSE_APPLETOUCH is not set |
| 783 | # CONFIG_MOUSE_BCM5974 is not set | ||
| 707 | # CONFIG_MOUSE_VSXXXAA is not set | 784 | # CONFIG_MOUSE_VSXXXAA is not set |
| 708 | CONFIG_MOUSE_HIL=y | 785 | CONFIG_MOUSE_HIL=y |
| 709 | # CONFIG_INPUT_JOYSTICK is not set | 786 | # CONFIG_INPUT_JOYSTICK is not set |
| @@ -729,10 +806,13 @@ CONFIG_SERIO_LIBPS2=y | |||
| 729 | # Character devices | 806 | # Character devices |
| 730 | # | 807 | # |
| 731 | CONFIG_VT=y | 808 | CONFIG_VT=y |
| 809 | CONFIG_CONSOLE_TRANSLATIONS=y | ||
| 732 | CONFIG_VT_CONSOLE=y | 810 | CONFIG_VT_CONSOLE=y |
| 733 | CONFIG_HW_CONSOLE=y | 811 | CONFIG_HW_CONSOLE=y |
| 734 | # CONFIG_VT_HW_CONSOLE_BINDING is not set | 812 | # CONFIG_VT_HW_CONSOLE_BINDING is not set |
| 813 | CONFIG_DEVKMEM=y | ||
| 735 | # CONFIG_SERIAL_NONSTANDARD is not set | 814 | # CONFIG_SERIAL_NONSTANDARD is not set |
| 815 | # CONFIG_NOZOMI is not set | ||
| 736 | 816 | ||
| 737 | # | 817 | # |
| 738 | # Serial drivers | 818 | # Serial drivers |
| @@ -759,21 +839,16 @@ CONFIG_SERIAL_CORE=y | |||
| 759 | CONFIG_SERIAL_CORE_CONSOLE=y | 839 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 760 | # CONFIG_SERIAL_JSM is not set | 840 | # CONFIG_SERIAL_JSM is not set |
| 761 | CONFIG_UNIX98_PTYS=y | 841 | CONFIG_UNIX98_PTYS=y |
| 842 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 762 | CONFIG_LEGACY_PTYS=y | 843 | CONFIG_LEGACY_PTYS=y |
| 763 | CONFIG_LEGACY_PTY_COUNT=64 | 844 | CONFIG_LEGACY_PTY_COUNT=64 |
| 764 | CONFIG_PRINTER=m | 845 | CONFIG_PRINTER=m |
| 765 | # CONFIG_LP_CONSOLE is not set | 846 | # CONFIG_LP_CONSOLE is not set |
| 766 | CONFIG_PPDEV=m | 847 | CONFIG_PPDEV=m |
| 767 | # CONFIG_TIPAR is not set | ||
| 768 | # CONFIG_IPMI_HANDLER is not set | 848 | # CONFIG_IPMI_HANDLER is not set |
| 769 | # CONFIG_WATCHDOG is not set | ||
| 770 | # CONFIG_HW_RANDOM is not set | 849 | # CONFIG_HW_RANDOM is not set |
| 771 | CONFIG_GEN_RTC=y | ||
| 772 | CONFIG_GEN_RTC_X=y | ||
| 773 | # CONFIG_R3964 is not set | 850 | # CONFIG_R3964 is not set |
| 774 | # CONFIG_APPLICOM is not set | 851 | # CONFIG_APPLICOM is not set |
| 775 | # CONFIG_AGP is not set | ||
| 776 | # CONFIG_DRM is not set | ||
| 777 | 852 | ||
| 778 | # | 853 | # |
| 779 | # PCMCIA character devices | 854 | # PCMCIA character devices |
| @@ -781,60 +856,70 @@ CONFIG_GEN_RTC_X=y | |||
| 781 | # CONFIG_SYNCLINK_CS is not set | 856 | # CONFIG_SYNCLINK_CS is not set |
| 782 | # CONFIG_CARDMAN_4000 is not set | 857 | # CONFIG_CARDMAN_4000 is not set |
| 783 | # CONFIG_CARDMAN_4040 is not set | 858 | # CONFIG_CARDMAN_4040 is not set |
| 859 | # CONFIG_IPWIRELESS is not set | ||
| 784 | # CONFIG_RAW_DRIVER is not set | 860 | # CONFIG_RAW_DRIVER is not set |
| 785 | # CONFIG_TCG_TPM is not set | 861 | # CONFIG_TCG_TPM is not set |
| 786 | CONFIG_DEVPORT=y | 862 | CONFIG_DEVPORT=y |
| 787 | # CONFIG_I2C is not set | 863 | # CONFIG_I2C is not set |
| 788 | |||
| 789 | # | ||
| 790 | # SPI support | ||
| 791 | # | ||
| 792 | # CONFIG_SPI is not set | 864 | # CONFIG_SPI is not set |
| 793 | # CONFIG_SPI_MASTER is not set | ||
| 794 | # CONFIG_W1 is not set | 865 | # CONFIG_W1 is not set |
| 795 | # CONFIG_POWER_SUPPLY is not set | 866 | # CONFIG_POWER_SUPPLY is not set |
| 796 | # CONFIG_HWMON is not set | 867 | # CONFIG_HWMON is not set |
| 868 | # CONFIG_THERMAL is not set | ||
| 869 | # CONFIG_THERMAL_HWMON is not set | ||
| 870 | # CONFIG_WATCHDOG is not set | ||
| 871 | CONFIG_SSB_POSSIBLE=y | ||
| 797 | 872 | ||
| 798 | # | 873 | # |
| 799 | # Sonics Silicon Backplane | 874 | # Sonics Silicon Backplane |
| 800 | # | 875 | # |
| 801 | CONFIG_SSB_POSSIBLE=y | ||
| 802 | # CONFIG_SSB is not set | 876 | # CONFIG_SSB is not set |
| 803 | 877 | ||
| 804 | # | 878 | # |
| 805 | # Multifunction device drivers | 879 | # Multifunction device drivers |
| 806 | # | 880 | # |
| 881 | # CONFIG_MFD_CORE is not set | ||
| 807 | # CONFIG_MFD_SM501 is not set | 882 | # CONFIG_MFD_SM501 is not set |
| 883 | # CONFIG_HTC_PASIC3 is not set | ||
| 884 | # CONFIG_MFD_TMIO is not set | ||
| 885 | # CONFIG_REGULATOR is not set | ||
| 808 | 886 | ||
| 809 | # | 887 | # |
| 810 | # Multimedia devices | 888 | # Multimedia devices |
| 811 | # | 889 | # |
| 890 | |||
| 891 | # | ||
| 892 | # Multimedia core support | ||
| 893 | # | ||
| 812 | # CONFIG_VIDEO_DEV is not set | 894 | # CONFIG_VIDEO_DEV is not set |
| 813 | # CONFIG_DVB_CORE is not set | 895 | # CONFIG_DVB_CORE is not set |
| 814 | # CONFIG_DAB is not set | 896 | # CONFIG_VIDEO_MEDIA is not set |
| 815 | 897 | ||
| 816 | # | 898 | # |
| 817 | # Graphics support | 899 | # Multimedia drivers |
| 818 | # | 900 | # |
| 819 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 901 | # CONFIG_DAB is not set |
| 820 | 902 | ||
| 821 | # | 903 | # |
| 822 | # Display device support | 904 | # Graphics support |
| 823 | # | 905 | # |
| 824 | # CONFIG_DISPLAY_SUPPORT is not set | 906 | # CONFIG_AGP is not set |
| 907 | # CONFIG_DRM is not set | ||
| 825 | # CONFIG_VGASTATE is not set | 908 | # CONFIG_VGASTATE is not set |
| 826 | CONFIG_VIDEO_OUTPUT_CONTROL=m | 909 | CONFIG_VIDEO_OUTPUT_CONTROL=m |
| 827 | CONFIG_FB=y | 910 | CONFIG_FB=y |
| 828 | # CONFIG_FIRMWARE_EDID is not set | 911 | # CONFIG_FIRMWARE_EDID is not set |
| 829 | # CONFIG_FB_DDC is not set | 912 | # CONFIG_FB_DDC is not set |
| 913 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 830 | CONFIG_FB_CFB_FILLRECT=y | 914 | CONFIG_FB_CFB_FILLRECT=y |
| 831 | CONFIG_FB_CFB_COPYAREA=y | 915 | CONFIG_FB_CFB_COPYAREA=y |
| 832 | CONFIG_FB_CFB_IMAGEBLIT=y | 916 | CONFIG_FB_CFB_IMAGEBLIT=y |
| 917 | # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set | ||
| 833 | # CONFIG_FB_SYS_FILLRECT is not set | 918 | # CONFIG_FB_SYS_FILLRECT is not set |
| 834 | # CONFIG_FB_SYS_COPYAREA is not set | 919 | # CONFIG_FB_SYS_COPYAREA is not set |
| 835 | # CONFIG_FB_SYS_IMAGEBLIT is not set | 920 | # CONFIG_FB_SYS_IMAGEBLIT is not set |
| 921 | # CONFIG_FB_FOREIGN_ENDIAN is not set | ||
| 836 | # CONFIG_FB_SYS_FOPS is not set | 922 | # CONFIG_FB_SYS_FOPS is not set |
| 837 | CONFIG_FB_DEFERRED_IO=y | ||
| 838 | # CONFIG_FB_SVGALIB is not set | 923 | # CONFIG_FB_SVGALIB is not set |
| 839 | # CONFIG_FB_MACMODES is not set | 924 | # CONFIG_FB_MACMODES is not set |
| 840 | # CONFIG_FB_BACKLIGHT is not set | 925 | # CONFIG_FB_BACKLIGHT is not set |
| @@ -860,6 +945,7 @@ CONFIG_FB_STI=y | |||
| 860 | # CONFIG_FB_S3 is not set | 945 | # CONFIG_FB_S3 is not set |
| 861 | # CONFIG_FB_SAVAGE is not set | 946 | # CONFIG_FB_SAVAGE is not set |
| 862 | # CONFIG_FB_SIS is not set | 947 | # CONFIG_FB_SIS is not set |
| 948 | # CONFIG_FB_VIA is not set | ||
| 863 | # CONFIG_FB_NEOMAGIC is not set | 949 | # CONFIG_FB_NEOMAGIC is not set |
| 864 | # CONFIG_FB_KYRO is not set | 950 | # CONFIG_FB_KYRO is not set |
| 865 | # CONFIG_FB_3DFX is not set | 951 | # CONFIG_FB_3DFX is not set |
| @@ -868,7 +954,16 @@ CONFIG_FB_STI=y | |||
| 868 | # CONFIG_FB_TRIDENT is not set | 954 | # CONFIG_FB_TRIDENT is not set |
| 869 | # CONFIG_FB_ARK is not set | 955 | # CONFIG_FB_ARK is not set |
| 870 | # CONFIG_FB_PM3 is not set | 956 | # CONFIG_FB_PM3 is not set |
| 957 | # CONFIG_FB_CARMINE is not set | ||
| 871 | # CONFIG_FB_VIRTUAL is not set | 958 | # CONFIG_FB_VIRTUAL is not set |
| 959 | # CONFIG_FB_METRONOME is not set | ||
| 960 | # CONFIG_FB_MB862XX is not set | ||
| 961 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | ||
| 962 | |||
| 963 | # | ||
| 964 | # Display device support | ||
| 965 | # | ||
| 966 | # CONFIG_DISPLAY_SUPPORT is not set | ||
| 872 | 967 | ||
| 873 | # | 968 | # |
| 874 | # Console display driver support | 969 | # Console display driver support |
| @@ -896,15 +991,8 @@ CONFIG_LOGO=y | |||
| 896 | # CONFIG_LOGO_LINUX_VGA16 is not set | 991 | # CONFIG_LOGO_LINUX_VGA16 is not set |
| 897 | # CONFIG_LOGO_LINUX_CLUT224 is not set | 992 | # CONFIG_LOGO_LINUX_CLUT224 is not set |
| 898 | CONFIG_LOGO_PARISC_CLUT224=y | 993 | CONFIG_LOGO_PARISC_CLUT224=y |
| 899 | |||
| 900 | # | ||
| 901 | # Sound | ||
| 902 | # | ||
| 903 | CONFIG_SOUND=y | 994 | CONFIG_SOUND=y |
| 904 | 995 | CONFIG_SOUND_OSS_CORE=y | |
| 905 | # | ||
| 906 | # Advanced Linux Sound Architecture | ||
| 907 | # | ||
| 908 | CONFIG_SND=y | 996 | CONFIG_SND=y |
| 909 | CONFIG_SND_TIMER=y | 997 | CONFIG_SND_TIMER=y |
| 910 | CONFIG_SND_PCM=y | 998 | CONFIG_SND_PCM=y |
| @@ -920,11 +1008,9 @@ CONFIG_SND_SUPPORT_OLD_API=y | |||
| 920 | CONFIG_SND_VERBOSE_PROCFS=y | 1008 | CONFIG_SND_VERBOSE_PROCFS=y |
| 921 | # CONFIG_SND_VERBOSE_PRINTK is not set | 1009 | # CONFIG_SND_VERBOSE_PRINTK is not set |
| 922 | # CONFIG_SND_DEBUG is not set | 1010 | # CONFIG_SND_DEBUG is not set |
| 923 | 1011 | CONFIG_SND_VMASTER=y | |
| 924 | # | ||
| 925 | # Generic devices | ||
| 926 | # | ||
| 927 | CONFIG_SND_AC97_CODEC=y | 1012 | CONFIG_SND_AC97_CODEC=y |
| 1013 | CONFIG_SND_DRIVERS=y | ||
| 928 | # CONFIG_SND_DUMMY is not set | 1014 | # CONFIG_SND_DUMMY is not set |
| 929 | # CONFIG_SND_VIRMIDI is not set | 1015 | # CONFIG_SND_VIRMIDI is not set |
| 930 | # CONFIG_SND_MTPAV is not set | 1016 | # CONFIG_SND_MTPAV is not set |
| @@ -932,10 +1018,8 @@ CONFIG_SND_AC97_CODEC=y | |||
| 932 | # CONFIG_SND_SERIAL_U16550 is not set | 1018 | # CONFIG_SND_SERIAL_U16550 is not set |
| 933 | # CONFIG_SND_MPU401 is not set | 1019 | # CONFIG_SND_MPU401 is not set |
| 934 | # CONFIG_SND_PORTMAN2X4 is not set | 1020 | # CONFIG_SND_PORTMAN2X4 is not set |
| 935 | 1021 | # CONFIG_SND_AC97_POWER_SAVE is not set | |
| 936 | # | 1022 | CONFIG_SND_PCI=y |
| 937 | # PCI devices | ||
| 938 | # | ||
| 939 | CONFIG_SND_AD1889=y | 1023 | CONFIG_SND_AD1889=y |
| 940 | # CONFIG_SND_ALS300 is not set | 1024 | # CONFIG_SND_ALS300 is not set |
| 941 | # CONFIG_SND_ALI5451 is not set | 1025 | # CONFIG_SND_ALI5451 is not set |
| @@ -944,10 +1028,12 @@ CONFIG_SND_AD1889=y | |||
| 944 | # CONFIG_SND_AU8810 is not set | 1028 | # CONFIG_SND_AU8810 is not set |
| 945 | # CONFIG_SND_AU8820 is not set | 1029 | # CONFIG_SND_AU8820 is not set |
| 946 | # CONFIG_SND_AU8830 is not set | 1030 | # CONFIG_SND_AU8830 is not set |
| 1031 | # CONFIG_SND_AW2 is not set | ||
| 947 | # CONFIG_SND_AZT3328 is not set | 1032 | # CONFIG_SND_AZT3328 is not set |
| 948 | # CONFIG_SND_BT87X is not set | 1033 | # CONFIG_SND_BT87X is not set |
| 949 | # CONFIG_SND_CA0106 is not set | 1034 | # CONFIG_SND_CA0106 is not set |
| 950 | # CONFIG_SND_CMIPCI is not set | 1035 | # CONFIG_SND_CMIPCI is not set |
| 1036 | # CONFIG_SND_OXYGEN is not set | ||
| 951 | # CONFIG_SND_CS4281 is not set | 1037 | # CONFIG_SND_CS4281 is not set |
| 952 | # CONFIG_SND_CS46XX is not set | 1038 | # CONFIG_SND_CS46XX is not set |
| 953 | # CONFIG_SND_DARLA20 is not set | 1039 | # CONFIG_SND_DARLA20 is not set |
| @@ -972,6 +1058,7 @@ CONFIG_SND_AD1889=y | |||
| 972 | # CONFIG_SND_HDA_INTEL is not set | 1058 | # CONFIG_SND_HDA_INTEL is not set |
| 973 | # CONFIG_SND_HDSP is not set | 1059 | # CONFIG_SND_HDSP is not set |
| 974 | # CONFIG_SND_HDSPM is not set | 1060 | # CONFIG_SND_HDSPM is not set |
| 1061 | # CONFIG_SND_HIFIER is not set | ||
| 975 | # CONFIG_SND_ICE1712 is not set | 1062 | # CONFIG_SND_ICE1712 is not set |
| 976 | # CONFIG_SND_ICE1724 is not set | 1063 | # CONFIG_SND_ICE1724 is not set |
| 977 | # CONFIG_SND_INTEL8X0 is not set | 1064 | # CONFIG_SND_INTEL8X0 is not set |
| @@ -989,58 +1076,67 @@ CONFIG_SND_AD1889=y | |||
| 989 | # CONFIG_SND_TRIDENT is not set | 1076 | # CONFIG_SND_TRIDENT is not set |
| 990 | # CONFIG_SND_VIA82XX is not set | 1077 | # CONFIG_SND_VIA82XX is not set |
| 991 | # CONFIG_SND_VIA82XX_MODEM is not set | 1078 | # CONFIG_SND_VIA82XX_MODEM is not set |
| 1079 | # CONFIG_SND_VIRTUOSO is not set | ||
| 992 | # CONFIG_SND_VX222 is not set | 1080 | # CONFIG_SND_VX222 is not set |
| 993 | # CONFIG_SND_YMFPCI is not set | 1081 | # CONFIG_SND_YMFPCI is not set |
| 994 | # CONFIG_SND_AC97_POWER_SAVE is not set | 1082 | CONFIG_SND_USB=y |
| 995 | |||
| 996 | # | ||
| 997 | # USB devices | ||
| 998 | # | ||
| 999 | # CONFIG_SND_USB_AUDIO is not set | 1083 | # CONFIG_SND_USB_AUDIO is not set |
| 1000 | # CONFIG_SND_USB_CAIAQ is not set | 1084 | # CONFIG_SND_USB_CAIAQ is not set |
| 1001 | 1085 | CONFIG_SND_PCMCIA=y | |
| 1002 | # | ||
| 1003 | # PCMCIA devices | ||
| 1004 | # | ||
| 1005 | # CONFIG_SND_VXPOCKET is not set | 1086 | # CONFIG_SND_VXPOCKET is not set |
| 1006 | # CONFIG_SND_PDAUDIOCF is not set | 1087 | # CONFIG_SND_PDAUDIOCF is not set |
| 1007 | 1088 | CONFIG_SND_GSC=y | |
| 1008 | # | ||
| 1009 | # GSC devices | ||
| 1010 | # | ||
| 1011 | CONFIG_SND_HARMONY=y | 1089 | CONFIG_SND_HARMONY=y |
| 1012 | |||
| 1013 | # | ||
| 1014 | # System on Chip audio support | ||
| 1015 | # | ||
| 1016 | # CONFIG_SND_SOC is not set | 1090 | # CONFIG_SND_SOC is not set |
| 1017 | |||
| 1018 | # | ||
| 1019 | # SoC Audio support for SuperH | ||
| 1020 | # | ||
| 1021 | |||
| 1022 | # | ||
| 1023 | # Open Sound System | ||
| 1024 | # | ||
| 1025 | # CONFIG_SOUND_PRIME is not set | 1091 | # CONFIG_SOUND_PRIME is not set |
| 1026 | CONFIG_AC97_BUS=y | 1092 | CONFIG_AC97_BUS=y |
| 1027 | CONFIG_HID_SUPPORT=y | 1093 | CONFIG_HID_SUPPORT=y |
| 1028 | CONFIG_HID=y | 1094 | CONFIG_HID=y |
| 1029 | CONFIG_HID_DEBUG=y | 1095 | CONFIG_HID_DEBUG=y |
| 1096 | # CONFIG_HIDRAW is not set | ||
| 1030 | 1097 | ||
| 1031 | # | 1098 | # |
| 1032 | # USB Input Devices | 1099 | # USB Input Devices |
| 1033 | # | 1100 | # |
| 1034 | CONFIG_USB_HID=y | 1101 | CONFIG_USB_HID=y |
| 1035 | # CONFIG_USB_HIDINPUT_POWERBOOK is not set | 1102 | # CONFIG_HID_PID is not set |
| 1036 | # CONFIG_HID_FF is not set | ||
| 1037 | # CONFIG_USB_HIDDEV is not set | 1103 | # CONFIG_USB_HIDDEV is not set |
| 1104 | |||
| 1105 | # | ||
| 1106 | # Special HID drivers | ||
| 1107 | # | ||
| 1108 | CONFIG_HID_COMPAT=y | ||
| 1109 | CONFIG_HID_A4TECH=y | ||
| 1110 | CONFIG_HID_APPLE=y | ||
| 1111 | CONFIG_HID_BELKIN=y | ||
| 1112 | CONFIG_HID_CHERRY=y | ||
| 1113 | CONFIG_HID_CHICONY=y | ||
| 1114 | CONFIG_HID_CYPRESS=y | ||
| 1115 | CONFIG_HID_EZKEY=y | ||
| 1116 | CONFIG_HID_GYRATION=y | ||
| 1117 | CONFIG_HID_LOGITECH=y | ||
| 1118 | # CONFIG_LOGITECH_FF is not set | ||
| 1119 | # CONFIG_LOGIRUMBLEPAD2_FF is not set | ||
| 1120 | CONFIG_HID_MICROSOFT=y | ||
| 1121 | CONFIG_HID_MONTEREY=y | ||
| 1122 | CONFIG_HID_NTRIG=y | ||
| 1123 | CONFIG_HID_PANTHERLORD=y | ||
| 1124 | # CONFIG_PANTHERLORD_FF is not set | ||
| 1125 | CONFIG_HID_PETALYNX=y | ||
| 1126 | CONFIG_HID_SAMSUNG=y | ||
| 1127 | CONFIG_HID_SONY=y | ||
| 1128 | CONFIG_HID_SUNPLUS=y | ||
| 1129 | # CONFIG_GREENASIA_FF is not set | ||
| 1130 | CONFIG_HID_TOPSEED=y | ||
| 1131 | # CONFIG_THRUSTMASTER_FF is not set | ||
| 1132 | # CONFIG_ZEROPLUS_FF is not set | ||
| 1038 | CONFIG_USB_SUPPORT=y | 1133 | CONFIG_USB_SUPPORT=y |
| 1039 | CONFIG_USB_ARCH_HAS_HCD=y | 1134 | CONFIG_USB_ARCH_HAS_HCD=y |
| 1040 | CONFIG_USB_ARCH_HAS_OHCI=y | 1135 | CONFIG_USB_ARCH_HAS_OHCI=y |
| 1041 | CONFIG_USB_ARCH_HAS_EHCI=y | 1136 | CONFIG_USB_ARCH_HAS_EHCI=y |
| 1042 | CONFIG_USB=y | 1137 | CONFIG_USB=y |
| 1043 | # CONFIG_USB_DEBUG is not set | 1138 | # CONFIG_USB_DEBUG is not set |
| 1139 | # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set | ||
| 1044 | 1140 | ||
| 1045 | # | 1141 | # |
| 1046 | # Miscellaneous USB options | 1142 | # Miscellaneous USB options |
| @@ -1049,12 +1145,18 @@ CONFIG_USB_DEVICEFS=y | |||
| 1049 | CONFIG_USB_DEVICE_CLASS=y | 1145 | CONFIG_USB_DEVICE_CLASS=y |
| 1050 | # CONFIG_USB_DYNAMIC_MINORS is not set | 1146 | # CONFIG_USB_DYNAMIC_MINORS is not set |
| 1051 | # CONFIG_USB_OTG is not set | 1147 | # CONFIG_USB_OTG is not set |
| 1148 | CONFIG_USB_MON=y | ||
| 1149 | # CONFIG_USB_WUSB is not set | ||
| 1150 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 1052 | 1151 | ||
| 1053 | # | 1152 | # |
| 1054 | # USB Host Controller Drivers | 1153 | # USB Host Controller Drivers |
| 1055 | # | 1154 | # |
| 1155 | # CONFIG_USB_C67X00_HCD is not set | ||
| 1056 | # CONFIG_USB_EHCI_HCD is not set | 1156 | # CONFIG_USB_EHCI_HCD is not set |
| 1157 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 1057 | # CONFIG_USB_ISP116X_HCD is not set | 1158 | # CONFIG_USB_ISP116X_HCD is not set |
| 1159 | # CONFIG_USB_ISP1760_HCD is not set | ||
| 1058 | CONFIG_USB_OHCI_HCD=y | 1160 | CONFIG_USB_OHCI_HCD=y |
| 1059 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set | 1161 | # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set |
| 1060 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set | 1162 | # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set |
| @@ -1062,19 +1164,23 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y | |||
| 1062 | CONFIG_USB_UHCI_HCD=y | 1164 | CONFIG_USB_UHCI_HCD=y |
| 1063 | # CONFIG_USB_SL811_HCD is not set | 1165 | # CONFIG_USB_SL811_HCD is not set |
| 1064 | # CONFIG_USB_R8A66597_HCD is not set | 1166 | # CONFIG_USB_R8A66597_HCD is not set |
| 1167 | # CONFIG_USB_WHCI_HCD is not set | ||
| 1168 | # CONFIG_USB_HWA_HCD is not set | ||
| 1065 | 1169 | ||
| 1066 | # | 1170 | # |
| 1067 | # USB Device Class drivers | 1171 | # USB Device Class drivers |
| 1068 | # | 1172 | # |
| 1069 | # CONFIG_USB_ACM is not set | 1173 | # CONFIG_USB_ACM is not set |
| 1070 | # CONFIG_USB_PRINTER is not set | 1174 | # CONFIG_USB_PRINTER is not set |
| 1175 | # CONFIG_USB_WDM is not set | ||
| 1176 | # CONFIG_USB_TMC is not set | ||
| 1071 | 1177 | ||
| 1072 | # | 1178 | # |
| 1073 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 1179 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; |
| 1074 | # | 1180 | # |
| 1075 | 1181 | ||
| 1076 | # | 1182 | # |
| 1077 | # may also be needed; see USB_STORAGE Help for more information | 1183 | # see USB_STORAGE Help for more information |
| 1078 | # | 1184 | # |
| 1079 | # CONFIG_USB_STORAGE is not set | 1185 | # CONFIG_USB_STORAGE is not set |
| 1080 | # CONFIG_USB_LIBUSUAL is not set | 1186 | # CONFIG_USB_LIBUSUAL is not set |
| @@ -1084,16 +1190,11 @@ CONFIG_USB_UHCI_HCD=y | |||
| 1084 | # | 1190 | # |
| 1085 | # CONFIG_USB_MDC800 is not set | 1191 | # CONFIG_USB_MDC800 is not set |
| 1086 | # CONFIG_USB_MICROTEK is not set | 1192 | # CONFIG_USB_MICROTEK is not set |
| 1087 | CONFIG_USB_MON=y | ||
| 1088 | 1193 | ||
| 1089 | # | 1194 | # |
| 1090 | # USB port drivers | 1195 | # USB port drivers |
| 1091 | # | 1196 | # |
| 1092 | # CONFIG_USB_USS720 is not set | 1197 | # CONFIG_USB_USS720 is not set |
| 1093 | |||
| 1094 | # | ||
| 1095 | # USB Serial Converter support | ||
| 1096 | # | ||
| 1097 | # CONFIG_USB_SERIAL is not set | 1198 | # CONFIG_USB_SERIAL is not set |
| 1098 | 1199 | ||
| 1099 | # | 1200 | # |
| @@ -1102,7 +1203,7 @@ CONFIG_USB_MON=y | |||
| 1102 | # CONFIG_USB_EMI62 is not set | 1203 | # CONFIG_USB_EMI62 is not set |
| 1103 | # CONFIG_USB_EMI26 is not set | 1204 | # CONFIG_USB_EMI26 is not set |
| 1104 | # CONFIG_USB_ADUTUX is not set | 1205 | # CONFIG_USB_ADUTUX is not set |
| 1105 | # CONFIG_USB_AUERSWALD is not set | 1206 | # CONFIG_USB_SEVSEG is not set |
| 1106 | # CONFIG_USB_RIO500 is not set | 1207 | # CONFIG_USB_RIO500 is not set |
| 1107 | # CONFIG_USB_LEGOTOWER is not set | 1208 | # CONFIG_USB_LEGOTOWER is not set |
| 1108 | # CONFIG_USB_LCD is not set | 1209 | # CONFIG_USB_LCD is not set |
| @@ -1118,38 +1219,60 @@ CONFIG_USB_MON=y | |||
| 1118 | # CONFIG_USB_TRANCEVIBRATOR is not set | 1219 | # CONFIG_USB_TRANCEVIBRATOR is not set |
| 1119 | # CONFIG_USB_IOWARRIOR is not set | 1220 | # CONFIG_USB_IOWARRIOR is not set |
| 1120 | # CONFIG_USB_TEST is not set | 1221 | # CONFIG_USB_TEST is not set |
| 1222 | # CONFIG_USB_ISIGHTFW is not set | ||
| 1223 | # CONFIG_USB_VST is not set | ||
| 1224 | # CONFIG_USB_GADGET is not set | ||
| 1121 | 1225 | ||
| 1122 | # | 1226 | # |
| 1123 | # USB DSL modem support | 1227 | # OTG and related infrastructure |
| 1124 | # | ||
| 1125 | |||
| 1126 | # | ||
| 1127 | # USB Gadget Support | ||
| 1128 | # | 1228 | # |
| 1129 | # CONFIG_USB_GADGET is not set | 1229 | # CONFIG_UWB is not set |
| 1130 | # CONFIG_MMC is not set | 1230 | # CONFIG_MMC is not set |
| 1231 | # CONFIG_MEMSTICK is not set | ||
| 1131 | # CONFIG_NEW_LEDS is not set | 1232 | # CONFIG_NEW_LEDS is not set |
| 1233 | # CONFIG_ACCESSIBILITY is not set | ||
| 1132 | # CONFIG_INFINIBAND is not set | 1234 | # CONFIG_INFINIBAND is not set |
| 1133 | # CONFIG_RTC_CLASS is not set | 1235 | CONFIG_RTC_LIB=y |
| 1236 | CONFIG_RTC_CLASS=y | ||
| 1237 | CONFIG_RTC_HCTOSYS=y | ||
| 1238 | CONFIG_RTC_HCTOSYS_DEVICE="rtc0" | ||
| 1239 | # CONFIG_RTC_DEBUG is not set | ||
| 1134 | 1240 | ||
| 1135 | # | 1241 | # |
| 1136 | # DMA Engine support | 1242 | # RTC interfaces |
| 1137 | # | 1243 | # |
| 1138 | # CONFIG_DMA_ENGINE is not set | 1244 | CONFIG_RTC_INTF_SYSFS=y |
| 1245 | CONFIG_RTC_INTF_PROC=y | ||
| 1246 | CONFIG_RTC_INTF_DEV=y | ||
| 1247 | # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set | ||
| 1248 | # CONFIG_RTC_DRV_TEST is not set | ||
| 1139 | 1249 | ||
| 1140 | # | 1250 | # |
| 1141 | # DMA Clients | 1251 | # SPI RTC drivers |
| 1142 | # | 1252 | # |
| 1143 | 1253 | ||
| 1144 | # | 1254 | # |
| 1145 | # DMA Devices | 1255 | # Platform RTC drivers |
| 1146 | # | 1256 | # |
| 1147 | # CONFIG_AUXDISPLAY is not set | 1257 | # CONFIG_RTC_DRV_DS1286 is not set |
| 1258 | # CONFIG_RTC_DRV_DS1511 is not set | ||
| 1259 | # CONFIG_RTC_DRV_DS1553 is not set | ||
| 1260 | # CONFIG_RTC_DRV_DS1742 is not set | ||
| 1261 | # CONFIG_RTC_DRV_STK17TA8 is not set | ||
| 1262 | # CONFIG_RTC_DRV_M48T86 is not set | ||
| 1263 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1264 | # CONFIG_RTC_DRV_M48T59 is not set | ||
| 1265 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1266 | # CONFIG_RTC_DRV_V3020 is not set | ||
| 1148 | 1267 | ||
| 1149 | # | 1268 | # |
| 1150 | # Userspace I/O | 1269 | # on-CPU RTC drivers |
| 1151 | # | 1270 | # |
| 1271 | CONFIG_RTC_DRV_PARISC=y | ||
| 1272 | # CONFIG_DMADEVICES is not set | ||
| 1273 | # CONFIG_AUXDISPLAY is not set | ||
| 1152 | # CONFIG_UIO is not set | 1274 | # CONFIG_UIO is not set |
| 1275 | # CONFIG_STAGING is not set | ||
| 1153 | 1276 | ||
| 1154 | # | 1277 | # |
| 1155 | # File systems | 1278 | # File systems |
| @@ -1159,21 +1282,20 @@ CONFIG_EXT2_FS=y | |||
| 1159 | # CONFIG_EXT2_FS_XIP is not set | 1282 | # CONFIG_EXT2_FS_XIP is not set |
| 1160 | CONFIG_EXT3_FS=y | 1283 | CONFIG_EXT3_FS=y |
| 1161 | # CONFIG_EXT3_FS_XATTR is not set | 1284 | # CONFIG_EXT3_FS_XATTR is not set |
| 1162 | # CONFIG_EXT4DEV_FS is not set | 1285 | # CONFIG_EXT4_FS is not set |
| 1163 | CONFIG_JBD=y | 1286 | CONFIG_JBD=y |
| 1164 | # CONFIG_JBD_DEBUG is not set | 1287 | # CONFIG_JBD_DEBUG is not set |
| 1165 | # CONFIG_REISERFS_FS is not set | 1288 | # CONFIG_REISERFS_FS is not set |
| 1166 | # CONFIG_JFS_FS is not set | 1289 | # CONFIG_JFS_FS is not set |
| 1167 | CONFIG_FS_POSIX_ACL=y | 1290 | CONFIG_FS_POSIX_ACL=y |
| 1291 | CONFIG_FILE_LOCKING=y | ||
| 1168 | # CONFIG_XFS_FS is not set | 1292 | # CONFIG_XFS_FS is not set |
| 1169 | # CONFIG_GFS2_FS is not set | ||
| 1170 | # CONFIG_OCFS2_FS is not set | 1293 | # CONFIG_OCFS2_FS is not set |
| 1171 | # CONFIG_MINIX_FS is not set | 1294 | # CONFIG_BTRFS_FS is not set |
| 1172 | # CONFIG_ROMFS_FS is not set | 1295 | CONFIG_DNOTIFY=y |
| 1173 | CONFIG_INOTIFY=y | 1296 | CONFIG_INOTIFY=y |
| 1174 | CONFIG_INOTIFY_USER=y | 1297 | CONFIG_INOTIFY_USER=y |
| 1175 | # CONFIG_QUOTA is not set | 1298 | # CONFIG_QUOTA is not set |
| 1176 | CONFIG_DNOTIFY=y | ||
| 1177 | CONFIG_AUTOFS_FS=y | 1299 | CONFIG_AUTOFS_FS=y |
| 1178 | # CONFIG_AUTOFS4_FS is not set | 1300 | # CONFIG_AUTOFS4_FS is not set |
| 1179 | # CONFIG_FUSE_FS is not set | 1301 | # CONFIG_FUSE_FS is not set |
| @@ -1202,16 +1324,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | |||
| 1202 | CONFIG_PROC_FS=y | 1324 | CONFIG_PROC_FS=y |
| 1203 | CONFIG_PROC_KCORE=y | 1325 | CONFIG_PROC_KCORE=y |
| 1204 | CONFIG_PROC_SYSCTL=y | 1326 | CONFIG_PROC_SYSCTL=y |
| 1327 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1205 | CONFIG_SYSFS=y | 1328 | CONFIG_SYSFS=y |
| 1206 | CONFIG_TMPFS=y | 1329 | CONFIG_TMPFS=y |
| 1207 | # CONFIG_TMPFS_POSIX_ACL is not set | 1330 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 1208 | # CONFIG_HUGETLB_PAGE is not set | 1331 | # CONFIG_HUGETLB_PAGE is not set |
| 1209 | CONFIG_RAMFS=y | ||
| 1210 | # CONFIG_CONFIGFS_FS is not set | 1332 | # CONFIG_CONFIGFS_FS is not set |
| 1211 | 1333 | CONFIG_MISC_FILESYSTEMS=y | |
| 1212 | # | ||
| 1213 | # Miscellaneous filesystems | ||
| 1214 | # | ||
| 1215 | # CONFIG_ADFS_FS is not set | 1334 | # CONFIG_ADFS_FS is not set |
| 1216 | # CONFIG_AFFS_FS is not set | 1335 | # CONFIG_AFFS_FS is not set |
| 1217 | # CONFIG_ECRYPT_FS is not set | 1336 | # CONFIG_ECRYPT_FS is not set |
| @@ -1221,33 +1340,32 @@ CONFIG_RAMFS=y | |||
| 1221 | # CONFIG_BFS_FS is not set | 1340 | # CONFIG_BFS_FS is not set |
| 1222 | # CONFIG_EFS_FS is not set | 1341 | # CONFIG_EFS_FS is not set |
| 1223 | # CONFIG_CRAMFS is not set | 1342 | # CONFIG_CRAMFS is not set |
| 1343 | # CONFIG_SQUASHFS is not set | ||
| 1224 | # CONFIG_VXFS_FS is not set | 1344 | # CONFIG_VXFS_FS is not set |
| 1345 | # CONFIG_MINIX_FS is not set | ||
| 1346 | # CONFIG_OMFS_FS is not set | ||
| 1225 | # CONFIG_HPFS_FS is not set | 1347 | # CONFIG_HPFS_FS is not set |
| 1226 | # CONFIG_QNX4FS_FS is not set | 1348 | # CONFIG_QNX4FS_FS is not set |
| 1349 | # CONFIG_ROMFS_FS is not set | ||
| 1227 | # CONFIG_SYSV_FS is not set | 1350 | # CONFIG_SYSV_FS is not set |
| 1228 | # CONFIG_UFS_FS is not set | 1351 | # CONFIG_UFS_FS is not set |
| 1229 | 1352 | CONFIG_NETWORK_FILESYSTEMS=y | |
| 1230 | # | ||
| 1231 | # Network File Systems | ||
| 1232 | # | ||
| 1233 | CONFIG_NFS_FS=y | 1353 | CONFIG_NFS_FS=y |
| 1234 | CONFIG_NFS_V3=y | 1354 | CONFIG_NFS_V3=y |
| 1235 | # CONFIG_NFS_V3_ACL is not set | 1355 | # CONFIG_NFS_V3_ACL is not set |
| 1236 | # CONFIG_NFS_V4 is not set | 1356 | # CONFIG_NFS_V4 is not set |
| 1237 | # CONFIG_NFS_DIRECTIO is not set | 1357 | CONFIG_ROOT_NFS=y |
| 1238 | CONFIG_NFSD=y | 1358 | CONFIG_NFSD=y |
| 1239 | CONFIG_NFSD_V3=y | 1359 | CONFIG_NFSD_V3=y |
| 1240 | # CONFIG_NFSD_V3_ACL is not set | 1360 | # CONFIG_NFSD_V3_ACL is not set |
| 1241 | CONFIG_NFSD_V4=y | 1361 | CONFIG_NFSD_V4=y |
| 1242 | CONFIG_NFSD_TCP=y | ||
| 1243 | CONFIG_ROOT_NFS=y | ||
| 1244 | CONFIG_LOCKD=y | 1362 | CONFIG_LOCKD=y |
| 1245 | CONFIG_LOCKD_V4=y | 1363 | CONFIG_LOCKD_V4=y |
| 1246 | CONFIG_EXPORTFS=y | 1364 | CONFIG_EXPORTFS=y |
| 1247 | CONFIG_NFS_COMMON=y | 1365 | CONFIG_NFS_COMMON=y |
| 1248 | CONFIG_SUNRPC=y | 1366 | CONFIG_SUNRPC=y |
| 1249 | CONFIG_SUNRPC_GSS=y | 1367 | CONFIG_SUNRPC_GSS=y |
| 1250 | # CONFIG_SUNRPC_BIND34 is not set | 1368 | # CONFIG_SUNRPC_REGISTER_V4 is not set |
| 1251 | CONFIG_RPCSEC_GSS_KRB5=y | 1369 | CONFIG_RPCSEC_GSS_KRB5=y |
| 1252 | CONFIG_RPCSEC_GSS_SPKM3=m | 1370 | CONFIG_RPCSEC_GSS_SPKM3=m |
| 1253 | CONFIG_SMB_FS=m | 1371 | CONFIG_SMB_FS=m |
| @@ -1256,6 +1374,7 @@ CONFIG_SMB_NLS_REMOTE="cp437" | |||
| 1256 | CONFIG_CIFS=m | 1374 | CONFIG_CIFS=m |
| 1257 | # CONFIG_CIFS_STATS is not set | 1375 | # CONFIG_CIFS_STATS is not set |
| 1258 | # CONFIG_CIFS_WEAK_PW_HASH is not set | 1376 | # CONFIG_CIFS_WEAK_PW_HASH is not set |
| 1377 | # CONFIG_CIFS_UPCALL is not set | ||
| 1259 | # CONFIG_CIFS_XATTR is not set | 1378 | # CONFIG_CIFS_XATTR is not set |
| 1260 | # CONFIG_CIFS_DEBUG2 is not set | 1379 | # CONFIG_CIFS_DEBUG2 is not set |
| 1261 | # CONFIG_CIFS_EXPERIMENTAL is not set | 1380 | # CONFIG_CIFS_EXPERIMENTAL is not set |
| @@ -1268,10 +1387,6 @@ CONFIG_CIFS=m | |||
| 1268 | # | 1387 | # |
| 1269 | # CONFIG_PARTITION_ADVANCED is not set | 1388 | # CONFIG_PARTITION_ADVANCED is not set |
| 1270 | CONFIG_MSDOS_PARTITION=y | 1389 | CONFIG_MSDOS_PARTITION=y |
| 1271 | |||
| 1272 | # | ||
| 1273 | # Native Language Support | ||
| 1274 | # | ||
| 1275 | CONFIG_NLS=y | 1390 | CONFIG_NLS=y |
| 1276 | CONFIG_NLS_DEFAULT="iso8859-1" | 1391 | CONFIG_NLS_DEFAULT="iso8859-1" |
| 1277 | CONFIG_NLS_CODEPAGE_437=y | 1392 | CONFIG_NLS_CODEPAGE_437=y |
| @@ -1312,33 +1427,28 @@ CONFIG_NLS_ISO8859_15=m | |||
| 1312 | CONFIG_NLS_KOI8_R=m | 1427 | CONFIG_NLS_KOI8_R=m |
| 1313 | CONFIG_NLS_KOI8_U=m | 1428 | CONFIG_NLS_KOI8_U=m |
| 1314 | CONFIG_NLS_UTF8=y | 1429 | CONFIG_NLS_UTF8=y |
| 1315 | |||
| 1316 | # | ||
| 1317 | # Distributed Lock Manager | ||
| 1318 | # | ||
| 1319 | # CONFIG_DLM is not set | 1430 | # CONFIG_DLM is not set |
| 1320 | 1431 | ||
| 1321 | # | 1432 | # |
| 1322 | # Profiling support | ||
| 1323 | # | ||
| 1324 | CONFIG_PROFILING=y | ||
| 1325 | CONFIG_OPROFILE=m | ||
| 1326 | |||
| 1327 | # | ||
| 1328 | # Kernel hacking | 1433 | # Kernel hacking |
| 1329 | # | 1434 | # |
| 1330 | # CONFIG_PRINTK_TIME is not set | 1435 | # CONFIG_PRINTK_TIME is not set |
| 1436 | CONFIG_ENABLE_WARN_DEPRECATED=y | ||
| 1331 | CONFIG_ENABLE_MUST_CHECK=y | 1437 | CONFIG_ENABLE_MUST_CHECK=y |
| 1438 | CONFIG_FRAME_WARN=1024 | ||
| 1332 | CONFIG_MAGIC_SYSRQ=y | 1439 | CONFIG_MAGIC_SYSRQ=y |
| 1333 | # CONFIG_UNUSED_SYMBOLS is not set | 1440 | # CONFIG_UNUSED_SYMBOLS is not set |
| 1334 | # CONFIG_DEBUG_FS is not set | 1441 | CONFIG_DEBUG_FS=y |
| 1335 | CONFIG_HEADERS_CHECK=y | 1442 | CONFIG_HEADERS_CHECK=y |
| 1336 | CONFIG_DEBUG_KERNEL=y | 1443 | CONFIG_DEBUG_KERNEL=y |
| 1337 | # CONFIG_DEBUG_SHIRQ is not set | 1444 | # CONFIG_DEBUG_SHIRQ is not set |
| 1338 | CONFIG_DETECT_SOFTLOCKUP=y | 1445 | CONFIG_DETECT_SOFTLOCKUP=y |
| 1446 | # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set | ||
| 1447 | CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 | ||
| 1339 | CONFIG_SCHED_DEBUG=y | 1448 | CONFIG_SCHED_DEBUG=y |
| 1340 | # CONFIG_SCHEDSTATS is not set | 1449 | # CONFIG_SCHEDSTATS is not set |
| 1341 | # CONFIG_TIMER_STATS is not set | 1450 | # CONFIG_TIMER_STATS is not set |
| 1451 | # CONFIG_DEBUG_OBJECTS is not set | ||
| 1342 | # CONFIG_DEBUG_SLAB is not set | 1452 | # CONFIG_DEBUG_SLAB is not set |
| 1343 | # CONFIG_DEBUG_RT_MUTEXES is not set | 1453 | # CONFIG_DEBUG_RT_MUTEXES is not set |
| 1344 | # CONFIG_RT_MUTEX_TESTER is not set | 1454 | # CONFIG_RT_MUTEX_TESTER is not set |
| @@ -1350,10 +1460,33 @@ CONFIG_DEBUG_MUTEXES=y | |||
| 1350 | CONFIG_DEBUG_BUGVERBOSE=y | 1460 | CONFIG_DEBUG_BUGVERBOSE=y |
| 1351 | # CONFIG_DEBUG_INFO is not set | 1461 | # CONFIG_DEBUG_INFO is not set |
| 1352 | # CONFIG_DEBUG_VM is not set | 1462 | # CONFIG_DEBUG_VM is not set |
| 1463 | # CONFIG_DEBUG_WRITECOUNT is not set | ||
| 1464 | CONFIG_DEBUG_MEMORY_INIT=y | ||
| 1353 | # CONFIG_DEBUG_LIST is not set | 1465 | # CONFIG_DEBUG_LIST is not set |
| 1354 | CONFIG_FORCED_INLINING=y | 1466 | # CONFIG_DEBUG_SG is not set |
| 1467 | # CONFIG_DEBUG_NOTIFIERS is not set | ||
| 1468 | # CONFIG_BOOT_PRINTK_DELAY is not set | ||
| 1355 | # CONFIG_RCU_TORTURE_TEST is not set | 1469 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1470 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1471 | # CONFIG_BACKTRACE_SELF_TEST is not set | ||
| 1472 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1356 | # CONFIG_FAULT_INJECTION is not set | 1473 | # CONFIG_FAULT_INJECTION is not set |
| 1474 | # CONFIG_SYSCTL_SYSCALL_CHECK is not set | ||
| 1475 | CONFIG_NOP_TRACER=y | ||
| 1476 | CONFIG_RING_BUFFER=y | ||
| 1477 | CONFIG_TRACING=y | ||
| 1478 | |||
| 1479 | # | ||
| 1480 | # Tracers | ||
| 1481 | # | ||
| 1482 | # CONFIG_SCHED_TRACER is not set | ||
| 1483 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | ||
| 1484 | # CONFIG_BOOT_TRACER is not set | ||
| 1485 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1486 | # CONFIG_FTRACE_STARTUP_TEST is not set | ||
| 1487 | # CONFIG_BUILD_DOCSRC is not set | ||
| 1488 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1489 | # CONFIG_SAMPLES is not set | ||
| 1357 | # CONFIG_DEBUG_RODATA is not set | 1490 | # CONFIG_DEBUG_RODATA is not set |
| 1358 | 1491 | ||
| 1359 | # | 1492 | # |
| @@ -1362,56 +1495,112 @@ CONFIG_FORCED_INLINING=y | |||
| 1362 | CONFIG_KEYS=y | 1495 | CONFIG_KEYS=y |
| 1363 | CONFIG_KEYS_DEBUG_PROC_KEYS=y | 1496 | CONFIG_KEYS_DEBUG_PROC_KEYS=y |
| 1364 | # CONFIG_SECURITY is not set | 1497 | # CONFIG_SECURITY is not set |
| 1498 | # CONFIG_SECURITYFS is not set | ||
| 1499 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | ||
| 1365 | CONFIG_CRYPTO=y | 1500 | CONFIG_CRYPTO=y |
| 1501 | |||
| 1502 | # | ||
| 1503 | # Crypto core or helper | ||
| 1504 | # | ||
| 1505 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1366 | CONFIG_CRYPTO_ALGAPI=y | 1506 | CONFIG_CRYPTO_ALGAPI=y |
| 1507 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1508 | CONFIG_CRYPTO_AEAD=y | ||
| 1509 | CONFIG_CRYPTO_AEAD2=y | ||
| 1367 | CONFIG_CRYPTO_BLKCIPHER=y | 1510 | CONFIG_CRYPTO_BLKCIPHER=y |
| 1511 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1368 | CONFIG_CRYPTO_HASH=y | 1512 | CONFIG_CRYPTO_HASH=y |
| 1513 | CONFIG_CRYPTO_HASH2=y | ||
| 1514 | CONFIG_CRYPTO_RNG2=y | ||
| 1369 | CONFIG_CRYPTO_MANAGER=y | 1515 | CONFIG_CRYPTO_MANAGER=y |
| 1516 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1517 | # CONFIG_CRYPTO_GF128MUL is not set | ||
| 1518 | CONFIG_CRYPTO_NULL=m | ||
| 1519 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1520 | CONFIG_CRYPTO_AUTHENC=y | ||
| 1521 | CONFIG_CRYPTO_TEST=m | ||
| 1522 | |||
| 1523 | # | ||
| 1524 | # Authenticated Encryption with Associated Data | ||
| 1525 | # | ||
| 1526 | # CONFIG_CRYPTO_CCM is not set | ||
| 1527 | # CONFIG_CRYPTO_GCM is not set | ||
| 1528 | # CONFIG_CRYPTO_SEQIV is not set | ||
| 1529 | |||
| 1530 | # | ||
| 1531 | # Block modes | ||
| 1532 | # | ||
| 1533 | CONFIG_CRYPTO_CBC=y | ||
| 1534 | # CONFIG_CRYPTO_CTR is not set | ||
| 1535 | # CONFIG_CRYPTO_CTS is not set | ||
| 1536 | # CONFIG_CRYPTO_ECB is not set | ||
| 1537 | # CONFIG_CRYPTO_LRW is not set | ||
| 1538 | # CONFIG_CRYPTO_PCBC is not set | ||
| 1539 | # CONFIG_CRYPTO_XTS is not set | ||
| 1540 | |||
| 1541 | # | ||
| 1542 | # Hash modes | ||
| 1543 | # | ||
| 1370 | CONFIG_CRYPTO_HMAC=y | 1544 | CONFIG_CRYPTO_HMAC=y |
| 1371 | # CONFIG_CRYPTO_XCBC is not set | 1545 | # CONFIG_CRYPTO_XCBC is not set |
| 1372 | CONFIG_CRYPTO_NULL=m | 1546 | |
| 1547 | # | ||
| 1548 | # Digest | ||
| 1549 | # | ||
| 1550 | CONFIG_CRYPTO_CRC32C=m | ||
| 1373 | CONFIG_CRYPTO_MD4=m | 1551 | CONFIG_CRYPTO_MD4=m |
| 1374 | CONFIG_CRYPTO_MD5=y | 1552 | CONFIG_CRYPTO_MD5=y |
| 1553 | CONFIG_CRYPTO_MICHAEL_MIC=m | ||
| 1554 | # CONFIG_CRYPTO_RMD128 is not set | ||
| 1555 | # CONFIG_CRYPTO_RMD160 is not set | ||
| 1556 | # CONFIG_CRYPTO_RMD256 is not set | ||
| 1557 | # CONFIG_CRYPTO_RMD320 is not set | ||
| 1375 | CONFIG_CRYPTO_SHA1=y | 1558 | CONFIG_CRYPTO_SHA1=y |
| 1376 | CONFIG_CRYPTO_SHA256=m | 1559 | CONFIG_CRYPTO_SHA256=m |
| 1377 | CONFIG_CRYPTO_SHA512=m | 1560 | CONFIG_CRYPTO_SHA512=m |
| 1378 | CONFIG_CRYPTO_WP512=m | ||
| 1379 | CONFIG_CRYPTO_TGR192=m | 1561 | CONFIG_CRYPTO_TGR192=m |
| 1380 | # CONFIG_CRYPTO_GF128MUL is not set | 1562 | CONFIG_CRYPTO_WP512=m |
| 1381 | # CONFIG_CRYPTO_ECB is not set | 1563 | |
| 1382 | CONFIG_CRYPTO_CBC=y | 1564 | # |
| 1383 | # CONFIG_CRYPTO_PCBC is not set | 1565 | # Ciphers |
| 1384 | # CONFIG_CRYPTO_LRW is not set | 1566 | # |
| 1385 | # CONFIG_CRYPTO_XTS is not set | ||
| 1386 | # CONFIG_CRYPTO_CRYPTD is not set | ||
| 1387 | CONFIG_CRYPTO_DES=y | ||
| 1388 | # CONFIG_CRYPTO_FCRYPT is not set | ||
| 1389 | CONFIG_CRYPTO_BLOWFISH=m | ||
| 1390 | CONFIG_CRYPTO_TWOFISH=m | ||
| 1391 | CONFIG_CRYPTO_TWOFISH_COMMON=m | ||
| 1392 | CONFIG_CRYPTO_SERPENT=m | ||
| 1393 | CONFIG_CRYPTO_AES=m | 1567 | CONFIG_CRYPTO_AES=m |
| 1568 | CONFIG_CRYPTO_ANUBIS=m | ||
| 1569 | CONFIG_CRYPTO_ARC4=m | ||
| 1570 | CONFIG_CRYPTO_BLOWFISH=m | ||
| 1571 | # CONFIG_CRYPTO_CAMELLIA is not set | ||
| 1394 | CONFIG_CRYPTO_CAST5=m | 1572 | CONFIG_CRYPTO_CAST5=m |
| 1395 | CONFIG_CRYPTO_CAST6=m | 1573 | CONFIG_CRYPTO_CAST6=m |
| 1396 | CONFIG_CRYPTO_TEA=m | 1574 | CONFIG_CRYPTO_DES=y |
| 1397 | CONFIG_CRYPTO_ARC4=m | 1575 | # CONFIG_CRYPTO_FCRYPT is not set |
| 1398 | CONFIG_CRYPTO_KHAZAD=m | 1576 | CONFIG_CRYPTO_KHAZAD=m |
| 1399 | CONFIG_CRYPTO_ANUBIS=m | 1577 | # CONFIG_CRYPTO_SALSA20 is not set |
| 1400 | # CONFIG_CRYPTO_SEED is not set | 1578 | # CONFIG_CRYPTO_SEED is not set |
| 1579 | CONFIG_CRYPTO_SERPENT=m | ||
| 1580 | CONFIG_CRYPTO_TEA=m | ||
| 1581 | CONFIG_CRYPTO_TWOFISH=m | ||
| 1582 | CONFIG_CRYPTO_TWOFISH_COMMON=m | ||
| 1583 | |||
| 1584 | # | ||
| 1585 | # Compression | ||
| 1586 | # | ||
| 1401 | CONFIG_CRYPTO_DEFLATE=y | 1587 | CONFIG_CRYPTO_DEFLATE=y |
| 1402 | CONFIG_CRYPTO_MICHAEL_MIC=m | 1588 | # CONFIG_CRYPTO_LZO is not set |
| 1403 | CONFIG_CRYPTO_CRC32C=m | 1589 | |
| 1404 | # CONFIG_CRYPTO_CAMELLIA is not set | 1590 | # |
| 1405 | CONFIG_CRYPTO_TEST=m | 1591 | # Random Number Generation |
| 1406 | # CONFIG_CRYPTO_AUTHENC is not set | 1592 | # |
| 1593 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1407 | # CONFIG_CRYPTO_HW is not set | 1594 | # CONFIG_CRYPTO_HW is not set |
| 1408 | 1595 | ||
| 1409 | # | 1596 | # |
| 1410 | # Library routines | 1597 | # Library routines |
| 1411 | # | 1598 | # |
| 1412 | CONFIG_BITREVERSE=y | 1599 | CONFIG_BITREVERSE=y |
| 1600 | CONFIG_GENERIC_FIND_LAST_BIT=y | ||
| 1413 | CONFIG_CRC_CCITT=m | 1601 | CONFIG_CRC_CCITT=m |
| 1414 | # CONFIG_CRC16 is not set | 1602 | # CONFIG_CRC16 is not set |
| 1603 | # CONFIG_CRC_T10DIF is not set | ||
| 1415 | # CONFIG_CRC_ITU_T is not set | 1604 | # CONFIG_CRC_ITU_T is not set |
| 1416 | CONFIG_CRC32=y | 1605 | CONFIG_CRC32=y |
| 1417 | # CONFIG_CRC7 is not set | 1606 | # CONFIG_CRC7 is not set |
diff --git a/arch/parisc/hpux/fs.c b/arch/parisc/hpux/fs.c index bd9a4db3bd4c..5cbe9f9e5d9e 100644 --- a/arch/parisc/hpux/fs.c +++ b/arch/parisc/hpux/fs.c | |||
| @@ -137,7 +137,6 @@ int hpux_getdents(unsigned int fd, struct hpux_dirent __user *dirent, unsigned i | |||
| 137 | error = count - buf.count; | 137 | error = count - buf.count; |
| 138 | } | 138 | } |
| 139 | 139 | ||
| 140 | out_putf: | ||
| 141 | fput(file); | 140 | fput(file); |
| 142 | out: | 141 | out: |
| 143 | return error; | 142 | return error; |
diff --git a/arch/parisc/include/asm/assembly.h b/arch/parisc/include/asm/assembly.h index ffb208840ecc..89fb40005e3f 100644 --- a/arch/parisc/include/asm/assembly.h +++ b/arch/parisc/include/asm/assembly.h | |||
| @@ -79,6 +79,7 @@ | |||
| 79 | 79 | ||
| 80 | #include <asm/asm-offsets.h> | 80 | #include <asm/asm-offsets.h> |
| 81 | #include <asm/page.h> | 81 | #include <asm/page.h> |
| 82 | #include <asm/types.h> | ||
| 82 | 83 | ||
| 83 | #include <asm/asmregs.h> | 84 | #include <asm/asmregs.h> |
| 84 | 85 | ||
| @@ -129,27 +130,27 @@ | |||
| 129 | 130 | ||
| 130 | /* Shift Left - note the r and t can NOT be the same! */ | 131 | /* Shift Left - note the r and t can NOT be the same! */ |
| 131 | .macro shl r, sa, t | 132 | .macro shl r, sa, t |
| 132 | dep,z \r, 31-\sa, 32-\sa, \t | 133 | dep,z \r, 31-(\sa), 32-(\sa), \t |
| 133 | .endm | 134 | .endm |
| 134 | 135 | ||
| 135 | /* The PA 2.0 shift left */ | 136 | /* The PA 2.0 shift left */ |
| 136 | .macro shlw r, sa, t | 137 | .macro shlw r, sa, t |
| 137 | depw,z \r, 31-\sa, 32-\sa, \t | 138 | depw,z \r, 31-(\sa), 32-(\sa), \t |
| 138 | .endm | 139 | .endm |
| 139 | 140 | ||
| 140 | /* And the PA 2.0W shift left */ | 141 | /* And the PA 2.0W shift left */ |
| 141 | .macro shld r, sa, t | 142 | .macro shld r, sa, t |
| 142 | depd,z \r, 63-\sa, 64-\sa, \t | 143 | depd,z \r, 63-(\sa), 64-(\sa), \t |
| 143 | .endm | 144 | .endm |
| 144 | 145 | ||
| 145 | /* Shift Right - note the r and t can NOT be the same! */ | 146 | /* Shift Right - note the r and t can NOT be the same! */ |
| 146 | .macro shr r, sa, t | 147 | .macro shr r, sa, t |
| 147 | extru \r, 31-\sa, 32-\sa, \t | 148 | extru \r, 31-(\sa), 32-(\sa), \t |
| 148 | .endm | 149 | .endm |
| 149 | 150 | ||
| 150 | /* pa20w version of shift right */ | 151 | /* pa20w version of shift right */ |
| 151 | .macro shrd r, sa, t | 152 | .macro shrd r, sa, t |
| 152 | extrd,u \r, 63-\sa, 64-\sa, \t | 153 | extrd,u \r, 63-(\sa), 64-(\sa), \t |
| 153 | .endm | 154 | .endm |
| 154 | 155 | ||
| 155 | /* load 32-bit 'value' into 'reg' compensating for the ldil | 156 | /* load 32-bit 'value' into 'reg' compensating for the ldil |
diff --git a/arch/parisc/include/asm/io.h b/arch/parisc/include/asm/io.h index d3031d1f9d03..1f6d2ae7aba5 100644 --- a/arch/parisc/include/asm/io.h +++ b/arch/parisc/include/asm/io.h | |||
| @@ -174,15 +174,48 @@ static inline void __raw_writeq(unsigned long long b, volatile void __iomem *add | |||
| 174 | *(volatile unsigned long long __force *) addr = b; | 174 | *(volatile unsigned long long __force *) addr = b; |
| 175 | } | 175 | } |
| 176 | 176 | ||
| 177 | /* readb can never be const, so use __fswab instead of le*_to_cpu */ | 177 | static inline unsigned char readb(const volatile void __iomem *addr) |
| 178 | #define readb(addr) __raw_readb(addr) | 178 | { |
| 179 | #define readw(addr) le16_to_cpu(__raw_readw(addr)) | 179 | return __raw_readb(addr); |
| 180 | #define readl(addr) le32_to_cpu(__raw_readl(addr)) | 180 | } |
| 181 | #define readq(addr) le64_to_cpu(__raw_readq(addr)) | 181 | static inline unsigned short readw(const volatile void __iomem *addr) |
| 182 | #define writeb(b, addr) __raw_writeb(b, addr) | 182 | { |
| 183 | #define writew(b, addr) __raw_writew(cpu_to_le16(b), addr) | 183 | return le16_to_cpu(__raw_readw(addr)); |
| 184 | #define writel(b, addr) __raw_writel(cpu_to_le32(b), addr) | 184 | } |
| 185 | #define writeq(b, addr) __raw_writeq(cpu_to_le64(b), addr) | 185 | static inline unsigned int readl(const volatile void __iomem *addr) |
| 186 | { | ||
| 187 | return le32_to_cpu(__raw_readl(addr)); | ||
| 188 | } | ||
| 189 | static inline unsigned long long readq(const volatile void __iomem *addr) | ||
| 190 | { | ||
| 191 | return le64_to_cpu(__raw_readq(addr)); | ||
| 192 | } | ||
| 193 | |||
| 194 | static inline void writeb(unsigned char b, volatile void __iomem *addr) | ||
| 195 | { | ||
| 196 | __raw_writeb(b, addr); | ||
| 197 | } | ||
| 198 | static inline void writew(unsigned short w, volatile void __iomem *addr) | ||
| 199 | { | ||
| 200 | __raw_writew(cpu_to_le16(w), addr); | ||
| 201 | } | ||
| 202 | static inline void writel(unsigned int l, volatile void __iomem *addr) | ||
| 203 | { | ||
| 204 | __raw_writel(cpu_to_le32(l), addr); | ||
| 205 | } | ||
| 206 | static inline void writeq(unsigned long long q, volatile void __iomem *addr) | ||
| 207 | { | ||
| 208 | __raw_writeq(cpu_to_le64(q), addr); | ||
| 209 | } | ||
| 210 | |||
| 211 | #define readb readb | ||
| 212 | #define readw readw | ||
| 213 | #define readl readl | ||
| 214 | #define readq readq | ||
| 215 | #define writeb writeb | ||
| 216 | #define writew writew | ||
| 217 | #define writel writel | ||
| 218 | #define writeq writeq | ||
| 186 | 219 | ||
| 187 | #define readb_relaxed(addr) readb(addr) | 220 | #define readb_relaxed(addr) readb(addr) |
| 188 | #define readw_relaxed(addr) readw(addr) | 221 | #define readw_relaxed(addr) readw(addr) |
diff --git a/arch/parisc/include/asm/irq.h b/arch/parisc/include/asm/irq.h index 399c81981ed5..dfa26b67f919 100644 --- a/arch/parisc/include/asm/irq.h +++ b/arch/parisc/include/asm/irq.h | |||
| @@ -49,7 +49,7 @@ extern unsigned long txn_alloc_addr(unsigned int); | |||
| 49 | extern unsigned long txn_affinity_addr(unsigned int irq, int cpu); | 49 | extern unsigned long txn_affinity_addr(unsigned int irq, int cpu); |
| 50 | 50 | ||
| 51 | extern int cpu_claim_irq(unsigned int irq, struct irq_chip *, void *); | 51 | extern int cpu_claim_irq(unsigned int irq, struct irq_chip *, void *); |
| 52 | extern int cpu_check_affinity(unsigned int irq, cpumask_t *dest); | 52 | extern int cpu_check_affinity(unsigned int irq, const struct cpumask *dest); |
| 53 | 53 | ||
| 54 | /* soft power switch support (power.c) */ | 54 | /* soft power switch support (power.c) */ |
| 55 | extern struct tasklet_struct power_tasklet; | 55 | extern struct tasklet_struct power_tasklet; |
diff --git a/arch/parisc/include/asm/uaccess.h b/arch/parisc/include/asm/uaccess.h index 1c6dbb6f6e56..cd4c0b2a8e70 100644 --- a/arch/parisc/include/asm/uaccess.h +++ b/arch/parisc/include/asm/uaccess.h | |||
| @@ -241,6 +241,7 @@ unsigned long copy_in_user(void __user *dst, const void __user *src, unsigned lo | |||
| 241 | #define __copy_to_user_inatomic __copy_to_user | 241 | #define __copy_to_user_inatomic __copy_to_user |
| 242 | #define __copy_from_user_inatomic __copy_from_user | 242 | #define __copy_from_user_inatomic __copy_from_user |
| 243 | 243 | ||
| 244 | struct pt_regs; | ||
| 244 | int fixup_exception(struct pt_regs *regs); | 245 | int fixup_exception(struct pt_regs *regs); |
| 245 | 246 | ||
| 246 | #endif /* __PARISC_UACCESS_H */ | 247 | #endif /* __PARISC_UACCESS_H */ |
diff --git a/arch/parisc/kernel/cache.c b/arch/parisc/kernel/cache.c index 5259d8c20676..837530ea32e7 100644 --- a/arch/parisc/kernel/cache.c +++ b/arch/parisc/kernel/cache.c | |||
| @@ -551,10 +551,7 @@ void flush_cache_range(struct vm_area_struct *vma, | |||
| 551 | { | 551 | { |
| 552 | int sr3; | 552 | int sr3; |
| 553 | 553 | ||
| 554 | if (!vma->vm_mm->context) { | 554 | BUG_ON(!vma->vm_mm->context); |
| 555 | BUG(); | ||
| 556 | return; | ||
| 557 | } | ||
| 558 | 555 | ||
| 559 | sr3 = mfsp(3); | 556 | sr3 = mfsp(3); |
| 560 | if (vma->vm_mm->context == sr3) { | 557 | if (vma->vm_mm->context == sr3) { |
diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S index d1fa4edd2d80..0db9fdcb7709 100644 --- a/arch/parisc/kernel/entry.S +++ b/arch/parisc/kernel/entry.S | |||
| @@ -368,7 +368,7 @@ | |||
| 368 | * abstractions for the macros */ | 368 | * abstractions for the macros */ |
| 369 | .macro EXTR reg1,start,length,reg2 | 369 | .macro EXTR reg1,start,length,reg2 |
| 370 | #ifdef CONFIG_64BIT | 370 | #ifdef CONFIG_64BIT |
| 371 | extrd,u \reg1,32+\start,\length,\reg2 | 371 | extrd,u \reg1,32+(\start),\length,\reg2 |
| 372 | #else | 372 | #else |
| 373 | extrw,u \reg1,\start,\length,\reg2 | 373 | extrw,u \reg1,\start,\length,\reg2 |
| 374 | #endif | 374 | #endif |
| @@ -376,7 +376,7 @@ | |||
| 376 | 376 | ||
| 377 | .macro DEP reg1,start,length,reg2 | 377 | .macro DEP reg1,start,length,reg2 |
| 378 | #ifdef CONFIG_64BIT | 378 | #ifdef CONFIG_64BIT |
| 379 | depd \reg1,32+\start,\length,\reg2 | 379 | depd \reg1,32+(\start),\length,\reg2 |
| 380 | #else | 380 | #else |
| 381 | depw \reg1,\start,\length,\reg2 | 381 | depw \reg1,\start,\length,\reg2 |
| 382 | #endif | 382 | #endif |
| @@ -384,7 +384,7 @@ | |||
| 384 | 384 | ||
| 385 | .macro DEPI val,start,length,reg | 385 | .macro DEPI val,start,length,reg |
| 386 | #ifdef CONFIG_64BIT | 386 | #ifdef CONFIG_64BIT |
| 387 | depdi \val,32+\start,\length,\reg | 387 | depdi \val,32+(\start),\length,\reg |
| 388 | #else | 388 | #else |
| 389 | depwi \val,\start,\length,\reg | 389 | depwi \val,\start,\length,\reg |
| 390 | #endif | 390 | #endif |
diff --git a/arch/parisc/kernel/firmware.c b/arch/parisc/kernel/firmware.c index 03f26bd75bd8..f6d241238a78 100644 --- a/arch/parisc/kernel/firmware.c +++ b/arch/parisc/kernel/firmware.c | |||
| @@ -151,7 +151,7 @@ static void convert_to_wide(unsigned long *addr) | |||
| 151 | } | 151 | } |
| 152 | 152 | ||
| 153 | #ifdef CONFIG_64BIT | 153 | #ifdef CONFIG_64BIT |
| 154 | void __init set_firmware_width_unlocked(void) | 154 | void __cpuinit set_firmware_width_unlocked(void) |
| 155 | { | 155 | { |
| 156 | int ret; | 156 | int ret; |
| 157 | 157 | ||
| @@ -168,7 +168,7 @@ void __init set_firmware_width_unlocked(void) | |||
| 168 | * This function must be called before any pdc_* function that uses the | 168 | * This function must be called before any pdc_* function that uses the |
| 169 | * convert_to_wide function. | 169 | * convert_to_wide function. |
| 170 | */ | 170 | */ |
| 171 | void __init set_firmware_width(void) | 171 | void __cpuinit set_firmware_width(void) |
| 172 | { | 172 | { |
| 173 | unsigned long flags; | 173 | unsigned long flags; |
| 174 | spin_lock_irqsave(&pdc_lock, flags); | 174 | spin_lock_irqsave(&pdc_lock, flags); |
| @@ -176,11 +176,11 @@ void __init set_firmware_width(void) | |||
| 176 | spin_unlock_irqrestore(&pdc_lock, flags); | 176 | spin_unlock_irqrestore(&pdc_lock, flags); |
| 177 | } | 177 | } |
| 178 | #else | 178 | #else |
| 179 | void __init set_firmware_width_unlocked(void) { | 179 | void __cpuinit set_firmware_width_unlocked(void) { |
| 180 | return; | 180 | return; |
| 181 | } | 181 | } |
| 182 | 182 | ||
| 183 | void __init set_firmware_width(void) { | 183 | void __cpuinit set_firmware_width(void) { |
| 184 | return; | 184 | return; |
| 185 | } | 185 | } |
| 186 | #endif /*CONFIG_64BIT*/ | 186 | #endif /*CONFIG_64BIT*/ |
| @@ -302,7 +302,7 @@ int pdc_chassis_warn(unsigned long *warn) | |||
| 302 | return retval; | 302 | return retval; |
| 303 | } | 303 | } |
| 304 | 304 | ||
| 305 | int __init pdc_coproc_cfg_unlocked(struct pdc_coproc_cfg *pdc_coproc_info) | 305 | int __cpuinit pdc_coproc_cfg_unlocked(struct pdc_coproc_cfg *pdc_coproc_info) |
| 306 | { | 306 | { |
| 307 | int ret; | 307 | int ret; |
| 308 | 308 | ||
| @@ -323,7 +323,7 @@ int __init pdc_coproc_cfg_unlocked(struct pdc_coproc_cfg *pdc_coproc_info) | |||
| 323 | * This PDC call returns the presence and status of all the coprocessors | 323 | * This PDC call returns the presence and status of all the coprocessors |
| 324 | * attached to the processor. | 324 | * attached to the processor. |
| 325 | */ | 325 | */ |
| 326 | int __init pdc_coproc_cfg(struct pdc_coproc_cfg *pdc_coproc_info) | 326 | int __cpuinit pdc_coproc_cfg(struct pdc_coproc_cfg *pdc_coproc_info) |
| 327 | { | 327 | { |
| 328 | int ret; | 328 | int ret; |
| 329 | unsigned long flags; | 329 | unsigned long flags; |
diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c index ac2c822928c7..29e70e16ede8 100644 --- a/arch/parisc/kernel/irq.c +++ b/arch/parisc/kernel/irq.c | |||
| @@ -112,7 +112,7 @@ void cpu_end_irq(unsigned int irq) | |||
| 112 | } | 112 | } |
| 113 | 113 | ||
| 114 | #ifdef CONFIG_SMP | 114 | #ifdef CONFIG_SMP |
| 115 | int cpu_check_affinity(unsigned int irq, cpumask_t *dest) | 115 | int cpu_check_affinity(unsigned int irq, const struct cpumask *dest) |
| 116 | { | 116 | { |
| 117 | int cpu_dest; | 117 | int cpu_dest; |
| 118 | 118 | ||
| @@ -120,23 +120,25 @@ int cpu_check_affinity(unsigned int irq, cpumask_t *dest) | |||
| 120 | if (CHECK_IRQ_PER_CPU(irq)) { | 120 | if (CHECK_IRQ_PER_CPU(irq)) { |
| 121 | /* Bad linux design decision. The mask has already | 121 | /* Bad linux design decision. The mask has already |
| 122 | * been set; we must reset it */ | 122 | * been set; we must reset it */ |
| 123 | irq_desc[irq].affinity = CPU_MASK_ALL; | 123 | cpumask_setall(&irq_desc[irq].affinity); |
| 124 | return -EINVAL; | 124 | return -EINVAL; |
| 125 | } | 125 | } |
| 126 | 126 | ||
| 127 | /* whatever mask they set, we just allow one CPU */ | 127 | /* whatever mask they set, we just allow one CPU */ |
| 128 | cpu_dest = first_cpu(*dest); | 128 | cpu_dest = first_cpu(*dest); |
| 129 | *dest = cpumask_of_cpu(cpu_dest); | ||
| 130 | 129 | ||
| 131 | return 0; | 130 | return cpu_dest; |
| 132 | } | 131 | } |
| 133 | 132 | ||
| 134 | static void cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest) | 133 | static void cpu_set_affinity_irq(unsigned int irq, const struct cpumask *dest) |
| 135 | { | 134 | { |
| 136 | if (cpu_check_affinity(irq, dest)) | 135 | int cpu_dest; |
| 136 | |||
| 137 | cpu_dest = cpu_check_affinity(irq, dest); | ||
| 138 | if (cpu_dest < 0) | ||
| 137 | return; | 139 | return; |
| 138 | 140 | ||
| 139 | irq_desc[irq].affinity = *dest; | 141 | cpumask_copy(&irq_desc[irq].affinity, &cpumask_of_cpu(cpu_dest)); |
| 140 | } | 142 | } |
| 141 | #endif | 143 | #endif |
| 142 | 144 | ||
| @@ -295,7 +297,7 @@ int txn_alloc_irq(unsigned int bits_wide) | |||
| 295 | unsigned long txn_affinity_addr(unsigned int irq, int cpu) | 297 | unsigned long txn_affinity_addr(unsigned int irq, int cpu) |
| 296 | { | 298 | { |
| 297 | #ifdef CONFIG_SMP | 299 | #ifdef CONFIG_SMP |
| 298 | irq_desc[irq].affinity = cpumask_of_cpu(cpu); | 300 | cpumask_copy(&irq_desc[irq].affinity, cpumask_of(cpu)); |
| 299 | #endif | 301 | #endif |
| 300 | 302 | ||
| 301 | return per_cpu(cpu_data, cpu).txn_addr; | 303 | return per_cpu(cpu_data, cpu).txn_addr; |
| @@ -352,7 +354,7 @@ void do_cpu_irq_mask(struct pt_regs *regs) | |||
| 352 | irq = eirr_to_irq(eirr_val); | 354 | irq = eirr_to_irq(eirr_val); |
| 353 | 355 | ||
| 354 | #ifdef CONFIG_SMP | 356 | #ifdef CONFIG_SMP |
| 355 | dest = irq_desc[irq].affinity; | 357 | cpumask_copy(&dest, &irq_desc[irq].affinity); |
| 356 | if (CHECK_IRQ_PER_CPU(irq_desc[irq].status) && | 358 | if (CHECK_IRQ_PER_CPU(irq_desc[irq].status) && |
| 357 | !cpu_isset(smp_processor_id(), dest)) { | 359 | !cpu_isset(smp_processor_id(), dest)) { |
| 358 | int cpu = first_cpu(dest); | 360 | int cpu = first_cpu(dest); |
diff --git a/arch/parisc/kernel/pci-dma.c b/arch/parisc/kernel/pci-dma.c index df47895db828..7d927eac932b 100644 --- a/arch/parisc/kernel/pci-dma.c +++ b/arch/parisc/kernel/pci-dma.c | |||
| @@ -447,10 +447,7 @@ static void pa11_dma_free_consistent (struct device *dev, size_t size, void *vad | |||
| 447 | 447 | ||
| 448 | static dma_addr_t pa11_dma_map_single(struct device *dev, void *addr, size_t size, enum dma_data_direction direction) | 448 | static dma_addr_t pa11_dma_map_single(struct device *dev, void *addr, size_t size, enum dma_data_direction direction) |
| 449 | { | 449 | { |
| 450 | if (direction == DMA_NONE) { | 450 | BUG_ON(direction == DMA_NONE); |
| 451 | printk(KERN_ERR "pa11_dma_map_single(PCI_DMA_NONE) called by %p\n", __builtin_return_address(0)); | ||
| 452 | BUG(); | ||
| 453 | } | ||
| 454 | 451 | ||
| 455 | flush_kernel_dcache_range((unsigned long) addr, size); | 452 | flush_kernel_dcache_range((unsigned long) addr, size); |
| 456 | return virt_to_phys(addr); | 453 | return virt_to_phys(addr); |
| @@ -458,10 +455,7 @@ static dma_addr_t pa11_dma_map_single(struct device *dev, void *addr, size_t siz | |||
| 458 | 455 | ||
| 459 | static void pa11_dma_unmap_single(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) | 456 | static void pa11_dma_unmap_single(struct device *dev, dma_addr_t dma_handle, size_t size, enum dma_data_direction direction) |
| 460 | { | 457 | { |
| 461 | if (direction == DMA_NONE) { | 458 | BUG_ON(direction == DMA_NONE); |
| 462 | printk(KERN_ERR "pa11_dma_unmap_single(PCI_DMA_NONE) called by %p\n", __builtin_return_address(0)); | ||
| 463 | BUG(); | ||
| 464 | } | ||
| 465 | 459 | ||
| 466 | if (direction == DMA_TO_DEVICE) | 460 | if (direction == DMA_TO_DEVICE) |
| 467 | return; | 461 | return; |
| @@ -480,8 +474,7 @@ static int pa11_dma_map_sg(struct device *dev, struct scatterlist *sglist, int n | |||
| 480 | { | 474 | { |
| 481 | int i; | 475 | int i; |
| 482 | 476 | ||
| 483 | if (direction == DMA_NONE) | 477 | BUG_ON(direction == DMA_NONE); |
| 484 | BUG(); | ||
| 485 | 478 | ||
| 486 | for (i = 0; i < nents; i++, sglist++ ) { | 479 | for (i = 0; i < nents; i++, sglist++ ) { |
| 487 | unsigned long vaddr = sg_virt_addr(sglist); | 480 | unsigned long vaddr = sg_virt_addr(sglist); |
| @@ -496,8 +489,7 @@ static void pa11_dma_unmap_sg(struct device *dev, struct scatterlist *sglist, in | |||
| 496 | { | 489 | { |
| 497 | int i; | 490 | int i; |
| 498 | 491 | ||
| 499 | if (direction == DMA_NONE) | 492 | BUG_ON(direction == DMA_NONE); |
| 500 | BUG(); | ||
| 501 | 493 | ||
| 502 | if (direction == DMA_TO_DEVICE) | 494 | if (direction == DMA_TO_DEVICE) |
| 503 | return; | 495 | return; |
| @@ -511,16 +503,14 @@ static void pa11_dma_unmap_sg(struct device *dev, struct scatterlist *sglist, in | |||
| 511 | 503 | ||
| 512 | static void pa11_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, unsigned long offset, size_t size, enum dma_data_direction direction) | 504 | static void pa11_dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle, unsigned long offset, size_t size, enum dma_data_direction direction) |
| 513 | { | 505 | { |
| 514 | if (direction == DMA_NONE) | 506 | BUG_ON(direction == DMA_NONE); |
| 515 | BUG(); | ||
| 516 | 507 | ||
| 517 | flush_kernel_dcache_range((unsigned long) phys_to_virt(dma_handle) + offset, size); | 508 | flush_kernel_dcache_range((unsigned long) phys_to_virt(dma_handle) + offset, size); |
| 518 | } | 509 | } |
| 519 | 510 | ||
| 520 | static void pa11_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, unsigned long offset, size_t size, enum dma_data_direction direction) | 511 | static void pa11_dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle, unsigned long offset, size_t size, enum dma_data_direction direction) |
| 521 | { | 512 | { |
| 522 | if (direction == DMA_NONE) | 513 | BUG_ON(direction == DMA_NONE); |
| 523 | BUG(); | ||
| 524 | 514 | ||
| 525 | flush_kernel_dcache_range((unsigned long) phys_to_virt(dma_handle) + offset, size); | 515 | flush_kernel_dcache_range((unsigned long) phys_to_virt(dma_handle) + offset, size); |
| 526 | } | 516 | } |
diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c index 7c155c254e72..9d704d9831d1 100644 --- a/arch/parisc/mm/init.c +++ b/arch/parisc/mm/init.c | |||
| @@ -304,10 +304,8 @@ static void __init setup_bootmem(void) | |||
| 304 | */ | 304 | */ |
| 305 | max_low_pfn = max_pfn; | 305 | max_low_pfn = max_pfn; |
| 306 | 306 | ||
| 307 | if ((bootmap_pfn - bootmap_start_pfn) != bootmap_pages) { | 307 | /* bootmap sizing messed up? */ |
| 308 | printk(KERN_WARNING "WARNING! bootmap sizing is messed up!\n"); | 308 | BUG_ON((bootmap_pfn - bootmap_start_pfn) != bootmap_pages); |
| 309 | BUG(); | ||
| 310 | } | ||
| 311 | 309 | ||
| 312 | /* reserve PAGE0 pdc memory, kernel text/data/bss & bootmap */ | 310 | /* reserve PAGE0 pdc memory, kernel text/data/bss & bootmap */ |
| 313 | 311 | ||
diff --git a/arch/powerpc/configs/40x/virtex_defconfig b/arch/powerpc/configs/40x/virtex_defconfig index b6888384dd74..f5698f962e58 100644 --- a/arch/powerpc/configs/40x/virtex_defconfig +++ b/arch/powerpc/configs/40x/virtex_defconfig | |||
| @@ -686,7 +686,7 @@ CONFIG_SERIAL_UARTLITE_CONSOLE=y | |||
| 686 | CONFIG_SERIAL_CORE=y | 686 | CONFIG_SERIAL_CORE=y |
| 687 | CONFIG_SERIAL_CORE_CONSOLE=y | 687 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 688 | # CONFIG_SERIAL_JSM is not set | 688 | # CONFIG_SERIAL_JSM is not set |
| 689 | # CONFIG_SERIAL_OF_PLATFORM is not set | 689 | CONFIG_SERIAL_OF_PLATFORM=y |
| 690 | # CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set | 690 | # CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set |
| 691 | CONFIG_UNIX98_PTYS=y | 691 | CONFIG_UNIX98_PTYS=y |
| 692 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | 692 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set |
diff --git a/arch/powerpc/configs/44x/virtex5_defconfig b/arch/powerpc/configs/44x/virtex5_defconfig index 15aab1ca6384..1bf0a63614b1 100644 --- a/arch/powerpc/configs/44x/virtex5_defconfig +++ b/arch/powerpc/configs/44x/virtex5_defconfig | |||
| @@ -691,7 +691,7 @@ CONFIG_SERIAL_UARTLITE_CONSOLE=y | |||
| 691 | CONFIG_SERIAL_CORE=y | 691 | CONFIG_SERIAL_CORE=y |
| 692 | CONFIG_SERIAL_CORE_CONSOLE=y | 692 | CONFIG_SERIAL_CORE_CONSOLE=y |
| 693 | # CONFIG_SERIAL_JSM is not set | 693 | # CONFIG_SERIAL_JSM is not set |
| 694 | # CONFIG_SERIAL_OF_PLATFORM is not set | 694 | CONFIG_SERIAL_OF_PLATFORM=y |
| 695 | # CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set | 695 | # CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL is not set |
| 696 | CONFIG_UNIX98_PTYS=y | 696 | CONFIG_UNIX98_PTYS=y |
| 697 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | 697 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set |
diff --git a/arch/powerpc/configs/linkstation_defconfig b/arch/powerpc/configs/linkstation_defconfig index aa5855a156de..15900dcf0bfa 100644 --- a/arch/powerpc/configs/linkstation_defconfig +++ b/arch/powerpc/configs/linkstation_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.29-rc2 | 3 | # Linux kernel version: 2.6.29-rc6 |
| 4 | # Mon Jan 26 15:35:29 2009 | 4 | # Fri Mar 6 00:07:38 2009 |
| 5 | # | 5 | # |
| 6 | # CONFIG_PPC64 is not set | 6 | # CONFIG_PPC64 is not set |
| 7 | 7 | ||
| @@ -71,6 +71,15 @@ CONFIG_POSIX_MQUEUE=y | |||
| 71 | # CONFIG_BSD_PROCESS_ACCT is not set | 71 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 72 | # CONFIG_TASKSTATS is not set | 72 | # CONFIG_TASKSTATS is not set |
| 73 | # CONFIG_AUDIT is not set | 73 | # CONFIG_AUDIT is not set |
| 74 | |||
| 75 | # | ||
| 76 | # RCU Subsystem | ||
| 77 | # | ||
| 78 | CONFIG_CLASSIC_RCU=y | ||
| 79 | # CONFIG_TREE_RCU is not set | ||
| 80 | # CONFIG_PREEMPT_RCU is not set | ||
| 81 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 82 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 74 | CONFIG_IKCONFIG=y | 83 | CONFIG_IKCONFIG=y |
| 75 | CONFIG_IKCONFIG_PROC=y | 84 | CONFIG_IKCONFIG_PROC=y |
| 76 | CONFIG_LOG_BUF_SHIFT=14 | 85 | CONFIG_LOG_BUF_SHIFT=14 |
| @@ -88,6 +97,7 @@ CONFIG_NAMESPACES=y | |||
| 88 | # CONFIG_IPC_NS is not set | 97 | # CONFIG_IPC_NS is not set |
| 89 | # CONFIG_USER_NS is not set | 98 | # CONFIG_USER_NS is not set |
| 90 | # CONFIG_PID_NS is not set | 99 | # CONFIG_PID_NS is not set |
| 100 | # CONFIG_NET_NS is not set | ||
| 91 | CONFIG_BLK_DEV_INITRD=y | 101 | CONFIG_BLK_DEV_INITRD=y |
| 92 | CONFIG_INITRAMFS_SOURCE="" | 102 | CONFIG_INITRAMFS_SOURCE="" |
| 93 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 103 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| @@ -153,11 +163,6 @@ CONFIG_DEFAULT_AS=y | |||
| 153 | # CONFIG_DEFAULT_CFQ is not set | 163 | # CONFIG_DEFAULT_CFQ is not set |
| 154 | # CONFIG_DEFAULT_NOOP is not set | 164 | # CONFIG_DEFAULT_NOOP is not set |
| 155 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 165 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 156 | CONFIG_CLASSIC_RCU=y | ||
| 157 | # CONFIG_TREE_RCU is not set | ||
| 158 | # CONFIG_PREEMPT_RCU is not set | ||
| 159 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 160 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 161 | # CONFIG_FREEZER is not set | 166 | # CONFIG_FREEZER is not set |
| 162 | 167 | ||
| 163 | # | 168 | # |
| @@ -294,7 +299,6 @@ CONFIG_NET=y | |||
| 294 | # | 299 | # |
| 295 | # Networking options | 300 | # Networking options |
| 296 | # | 301 | # |
| 297 | # CONFIG_NET_NS is not set | ||
| 298 | CONFIG_COMPAT_NET_DEV_OPS=y | 302 | CONFIG_COMPAT_NET_DEV_OPS=y |
| 299 | CONFIG_PACKET=y | 303 | CONFIG_PACKET=y |
| 300 | CONFIG_PACKET_MMAP=y | 304 | CONFIG_PACKET_MMAP=y |
| @@ -508,8 +512,8 @@ CONFIG_MTD_CONCAT=y | |||
| 508 | CONFIG_MTD_PARTITIONS=y | 512 | CONFIG_MTD_PARTITIONS=y |
| 509 | # CONFIG_MTD_TESTS is not set | 513 | # CONFIG_MTD_TESTS is not set |
| 510 | # CONFIG_MTD_REDBOOT_PARTS is not set | 514 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 511 | # CONFIG_MTD_CMDLINE_PARTS is not set | 515 | CONFIG_MTD_CMDLINE_PARTS=y |
| 512 | # CONFIG_MTD_OF_PARTS is not set | 516 | CONFIG_MTD_OF_PARTS=y |
| 513 | # CONFIG_MTD_AR7_PARTS is not set | 517 | # CONFIG_MTD_AR7_PARTS is not set |
| 514 | 518 | ||
| 515 | # | 519 | # |
| @@ -587,7 +591,6 @@ CONFIG_MTD_PHYSMAP=y | |||
| 587 | # LPDDR flash memory drivers | 591 | # LPDDR flash memory drivers |
| 588 | # | 592 | # |
| 589 | # CONFIG_MTD_LPDDR is not set | 593 | # CONFIG_MTD_LPDDR is not set |
| 590 | # CONFIG_MTD_QINFO_PROBE is not set | ||
| 591 | 594 | ||
| 592 | # | 595 | # |
| 593 | # UBI - Unsorted block images | 596 | # UBI - Unsorted block images |
| @@ -617,13 +620,19 @@ CONFIG_BLK_DEV_RAM_SIZE=8192 | |||
| 617 | # CONFIG_BLK_DEV_HD is not set | 620 | # CONFIG_BLK_DEV_HD is not set |
| 618 | CONFIG_MISC_DEVICES=y | 621 | CONFIG_MISC_DEVICES=y |
| 619 | # CONFIG_PHANTOM is not set | 622 | # CONFIG_PHANTOM is not set |
| 620 | # CONFIG_EEPROM_93CX6 is not set | ||
| 621 | # CONFIG_SGI_IOC4 is not set | 623 | # CONFIG_SGI_IOC4 is not set |
| 622 | # CONFIG_TIFM_CORE is not set | 624 | # CONFIG_TIFM_CORE is not set |
| 623 | # CONFIG_ICS932S401 is not set | 625 | # CONFIG_ICS932S401 is not set |
| 624 | # CONFIG_ENCLOSURE_SERVICES is not set | 626 | # CONFIG_ENCLOSURE_SERVICES is not set |
| 625 | # CONFIG_HP_ILO is not set | 627 | # CONFIG_HP_ILO is not set |
| 626 | # CONFIG_C2PORT is not set | 628 | # CONFIG_C2PORT is not set |
| 629 | |||
| 630 | # | ||
| 631 | # EEPROM support | ||
| 632 | # | ||
| 633 | # CONFIG_EEPROM_AT24 is not set | ||
| 634 | CONFIG_EEPROM_LEGACY=m | ||
| 635 | # CONFIG_EEPROM_93CX6 is not set | ||
| 627 | CONFIG_HAVE_IDE=y | 636 | CONFIG_HAVE_IDE=y |
| 628 | # CONFIG_IDE is not set | 637 | # CONFIG_IDE is not set |
| 629 | 638 | ||
| @@ -839,6 +848,7 @@ CONFIG_R8169=y | |||
| 839 | # CONFIG_QLA3XXX is not set | 848 | # CONFIG_QLA3XXX is not set |
| 840 | # CONFIG_ATL1 is not set | 849 | # CONFIG_ATL1 is not set |
| 841 | # CONFIG_ATL1E is not set | 850 | # CONFIG_ATL1E is not set |
| 851 | # CONFIG_ATL1C is not set | ||
| 842 | # CONFIG_JME is not set | 852 | # CONFIG_JME is not set |
| 843 | CONFIG_NETDEV_10000=y | 853 | CONFIG_NETDEV_10000=y |
| 844 | # CONFIG_CHELSIO_T1 is not set | 854 | # CONFIG_CHELSIO_T1 is not set |
| @@ -1037,8 +1047,6 @@ CONFIG_I2C_MPC=y | |||
| 1037 | # Miscellaneous I2C Chip support | 1047 | # Miscellaneous I2C Chip support |
| 1038 | # | 1048 | # |
| 1039 | # CONFIG_DS1682 is not set | 1049 | # CONFIG_DS1682 is not set |
| 1040 | # CONFIG_EEPROM_AT24 is not set | ||
| 1041 | CONFIG_EEPROM_LEGACY=m | ||
| 1042 | # CONFIG_SENSORS_PCF8574 is not set | 1050 | # CONFIG_SENSORS_PCF8574 is not set |
| 1043 | # CONFIG_PCF8575 is not set | 1051 | # CONFIG_PCF8575 is not set |
| 1044 | # CONFIG_SENSORS_PCA9539 is not set | 1052 | # CONFIG_SENSORS_PCA9539 is not set |
diff --git a/arch/powerpc/configs/ps3_defconfig b/arch/powerpc/configs/ps3_defconfig index b6eee7c93cdd..ac14f5245d2a 100644 --- a/arch/powerpc/configs/ps3_defconfig +++ b/arch/powerpc/configs/ps3_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.27-rc3 | 3 | # Linux kernel version: 2.6.29-rc8 |
| 4 | # Wed Aug 20 08:16:53 2008 | 4 | # Fri Mar 13 09:28:45 2009 |
| 5 | # | 5 | # |
| 6 | CONFIG_PPC64=y | 6 | CONFIG_PPC64=y |
| 7 | 7 | ||
| @@ -16,13 +16,14 @@ CONFIG_PPC_FPU=y | |||
| 16 | CONFIG_ALTIVEC=y | 16 | CONFIG_ALTIVEC=y |
| 17 | # CONFIG_VSX is not set | 17 | # CONFIG_VSX is not set |
| 18 | CONFIG_PPC_STD_MMU=y | 18 | CONFIG_PPC_STD_MMU=y |
| 19 | CONFIG_PPC_STD_MMU_64=y | ||
| 19 | CONFIG_PPC_MM_SLICES=y | 20 | CONFIG_PPC_MM_SLICES=y |
| 20 | CONFIG_VIRT_CPU_ACCOUNTING=y | 21 | CONFIG_VIRT_CPU_ACCOUNTING=y |
| 21 | CONFIG_SMP=y | 22 | CONFIG_SMP=y |
| 22 | CONFIG_NR_CPUS=2 | 23 | CONFIG_NR_CPUS=2 |
| 23 | CONFIG_64BIT=y | 24 | CONFIG_64BIT=y |
| 24 | CONFIG_WORD_SIZE=64 | 25 | CONFIG_WORD_SIZE=64 |
| 25 | CONFIG_PPC_MERGE=y | 26 | CONFIG_ARCH_PHYS_ADDR_T_64BIT=y |
| 26 | CONFIG_MMU=y | 27 | CONFIG_MMU=y |
| 27 | CONFIG_GENERIC_CMOS_UPDATE=y | 28 | CONFIG_GENERIC_CMOS_UPDATE=y |
| 28 | CONFIG_GENERIC_TIME=y | 29 | CONFIG_GENERIC_TIME=y |
| @@ -46,7 +47,7 @@ CONFIG_PPC=y | |||
| 46 | CONFIG_EARLY_PRINTK=y | 47 | CONFIG_EARLY_PRINTK=y |
| 47 | CONFIG_COMPAT=y | 48 | CONFIG_COMPAT=y |
| 48 | CONFIG_SYSVIPC_COMPAT=y | 49 | CONFIG_SYSVIPC_COMPAT=y |
| 49 | CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y | 50 | CONFIG_SCHED_OMIT_FRAME_POINTER=y |
| 50 | CONFIG_ARCH_MAY_HAVE_PC_FDC=y | 51 | CONFIG_ARCH_MAY_HAVE_PC_FDC=y |
| 51 | CONFIG_PPC_OF=y | 52 | CONFIG_PPC_OF=y |
| 52 | CONFIG_OF=y | 53 | CONFIG_OF=y |
| @@ -74,10 +75,19 @@ CONFIG_POSIX_MQUEUE=y | |||
| 74 | # CONFIG_BSD_PROCESS_ACCT is not set | 75 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 75 | # CONFIG_TASKSTATS is not set | 76 | # CONFIG_TASKSTATS is not set |
| 76 | # CONFIG_AUDIT is not set | 77 | # CONFIG_AUDIT is not set |
| 78 | |||
| 79 | # | ||
| 80 | # RCU Subsystem | ||
| 81 | # | ||
| 82 | CONFIG_CLASSIC_RCU=y | ||
| 83 | # CONFIG_TREE_RCU is not set | ||
| 84 | # CONFIG_PREEMPT_RCU is not set | ||
| 85 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 86 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 77 | # CONFIG_IKCONFIG is not set | 87 | # CONFIG_IKCONFIG is not set |
| 78 | CONFIG_LOG_BUF_SHIFT=17 | 88 | CONFIG_LOG_BUF_SHIFT=17 |
| 79 | # CONFIG_CGROUPS is not set | ||
| 80 | # CONFIG_GROUP_SCHED is not set | 89 | # CONFIG_GROUP_SCHED is not set |
| 90 | # CONFIG_CGROUPS is not set | ||
| 81 | CONFIG_SYSFS_DEPRECATED=y | 91 | CONFIG_SYSFS_DEPRECATED=y |
| 82 | CONFIG_SYSFS_DEPRECATED_V2=y | 92 | CONFIG_SYSFS_DEPRECATED_V2=y |
| 83 | # CONFIG_RELAY is not set | 93 | # CONFIG_RELAY is not set |
| @@ -86,11 +96,13 @@ CONFIG_NAMESPACES=y | |||
| 86 | # CONFIG_IPC_NS is not set | 96 | # CONFIG_IPC_NS is not set |
| 87 | # CONFIG_USER_NS is not set | 97 | # CONFIG_USER_NS is not set |
| 88 | # CONFIG_PID_NS is not set | 98 | # CONFIG_PID_NS is not set |
| 99 | # CONFIG_NET_NS is not set | ||
| 89 | CONFIG_BLK_DEV_INITRD=y | 100 | CONFIG_BLK_DEV_INITRD=y |
| 90 | CONFIG_INITRAMFS_SOURCE="" | 101 | CONFIG_INITRAMFS_SOURCE="" |
| 91 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y | 102 | CONFIG_CC_OPTIMIZE_FOR_SIZE=y |
| 92 | CONFIG_SYSCTL=y | 103 | CONFIG_SYSCTL=y |
| 93 | # CONFIG_EMBEDDED is not set | 104 | CONFIG_ANON_INODES=y |
| 105 | CONFIG_EMBEDDED=y | ||
| 94 | CONFIG_SYSCTL_SYSCALL=y | 106 | CONFIG_SYSCTL_SYSCALL=y |
| 95 | CONFIG_KALLSYMS=y | 107 | CONFIG_KALLSYMS=y |
| 96 | CONFIG_KALLSYMS_ALL=y | 108 | CONFIG_KALLSYMS_ALL=y |
| @@ -99,37 +111,36 @@ CONFIG_HOTPLUG=y | |||
| 99 | CONFIG_PRINTK=y | 111 | CONFIG_PRINTK=y |
| 100 | CONFIG_BUG=y | 112 | CONFIG_BUG=y |
| 101 | CONFIG_ELF_CORE=y | 113 | CONFIG_ELF_CORE=y |
| 102 | # CONFIG_COMPAT_BRK is not set | ||
| 103 | CONFIG_BASE_FULL=y | 114 | CONFIG_BASE_FULL=y |
| 104 | CONFIG_FUTEX=y | 115 | CONFIG_FUTEX=y |
| 105 | CONFIG_ANON_INODES=y | ||
| 106 | CONFIG_EPOLL=y | 116 | CONFIG_EPOLL=y |
| 107 | CONFIG_SIGNALFD=y | 117 | CONFIG_SIGNALFD=y |
| 108 | CONFIG_TIMERFD=y | 118 | CONFIG_TIMERFD=y |
| 109 | CONFIG_EVENTFD=y | 119 | CONFIG_EVENTFD=y |
| 110 | CONFIG_SHMEM=y | 120 | CONFIG_SHMEM=y |
| 121 | CONFIG_AIO=y | ||
| 111 | CONFIG_VM_EVENT_COUNTERS=y | 122 | CONFIG_VM_EVENT_COUNTERS=y |
| 123 | # CONFIG_COMPAT_BRK is not set | ||
| 112 | CONFIG_SLAB=y | 124 | CONFIG_SLAB=y |
| 113 | # CONFIG_SLUB is not set | 125 | # CONFIG_SLUB is not set |
| 114 | # CONFIG_SLOB is not set | 126 | # CONFIG_SLOB is not set |
| 115 | CONFIG_PROFILING=y | 127 | CONFIG_PROFILING=y |
| 116 | # CONFIG_MARKERS is not set | 128 | CONFIG_TRACEPOINTS=y |
| 129 | CONFIG_MARKERS=y | ||
| 117 | CONFIG_OPROFILE=m | 130 | CONFIG_OPROFILE=m |
| 118 | CONFIG_HAVE_OPROFILE=y | 131 | CONFIG_HAVE_OPROFILE=y |
| 119 | # CONFIG_KPROBES is not set | 132 | # CONFIG_KPROBES is not set |
| 120 | CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y | 133 | CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y |
| 134 | CONFIG_HAVE_SYSCALL_WRAPPERS=y | ||
| 121 | CONFIG_HAVE_IOREMAP_PROT=y | 135 | CONFIG_HAVE_IOREMAP_PROT=y |
| 122 | CONFIG_HAVE_KPROBES=y | 136 | CONFIG_HAVE_KPROBES=y |
| 123 | CONFIG_HAVE_KRETPROBES=y | 137 | CONFIG_HAVE_KRETPROBES=y |
| 124 | CONFIG_HAVE_ARCH_TRACEHOOK=y | 138 | CONFIG_HAVE_ARCH_TRACEHOOK=y |
| 125 | CONFIG_HAVE_DMA_ATTRS=y | 139 | CONFIG_HAVE_DMA_ATTRS=y |
| 126 | CONFIG_USE_GENERIC_SMP_HELPERS=y | 140 | CONFIG_USE_GENERIC_SMP_HELPERS=y |
| 127 | # CONFIG_HAVE_CLK is not set | ||
| 128 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 129 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set | 141 | # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set |
| 130 | CONFIG_SLABINFO=y | 142 | CONFIG_SLABINFO=y |
| 131 | CONFIG_RT_MUTEXES=y | 143 | CONFIG_RT_MUTEXES=y |
| 132 | # CONFIG_TINY_SHMEM is not set | ||
| 133 | CONFIG_BASE_SMALL=0 | 144 | CONFIG_BASE_SMALL=0 |
| 134 | CONFIG_MODULES=y | 145 | CONFIG_MODULES=y |
| 135 | # CONFIG_MODULE_FORCE_LOAD is not set | 146 | # CONFIG_MODULE_FORCE_LOAD is not set |
| @@ -137,7 +148,6 @@ CONFIG_MODULE_UNLOAD=y | |||
| 137 | # CONFIG_MODULE_FORCE_UNLOAD is not set | 148 | # CONFIG_MODULE_FORCE_UNLOAD is not set |
| 138 | # CONFIG_MODVERSIONS is not set | 149 | # CONFIG_MODVERSIONS is not set |
| 139 | # CONFIG_MODULE_SRCVERSION_ALL is not set | 150 | # CONFIG_MODULE_SRCVERSION_ALL is not set |
| 140 | CONFIG_KMOD=y | ||
| 141 | CONFIG_STOP_MACHINE=y | 151 | CONFIG_STOP_MACHINE=y |
| 142 | CONFIG_BLOCK=y | 152 | CONFIG_BLOCK=y |
| 143 | # CONFIG_BLK_DEV_IO_TRACE is not set | 153 | # CONFIG_BLK_DEV_IO_TRACE is not set |
| @@ -157,7 +167,7 @@ CONFIG_DEFAULT_AS=y | |||
| 157 | # CONFIG_DEFAULT_CFQ is not set | 167 | # CONFIG_DEFAULT_CFQ is not set |
| 158 | # CONFIG_DEFAULT_NOOP is not set | 168 | # CONFIG_DEFAULT_NOOP is not set |
| 159 | CONFIG_DEFAULT_IOSCHED="anticipatory" | 169 | CONFIG_DEFAULT_IOSCHED="anticipatory" |
| 160 | CONFIG_CLASSIC_RCU=y | 170 | # CONFIG_FREEZER is not set |
| 161 | 171 | ||
| 162 | # | 172 | # |
| 163 | # Platform support | 173 | # Platform support |
| @@ -183,18 +193,20 @@ CONFIG_PS3_STORAGE=y | |||
| 183 | CONFIG_PS3_DISK=y | 193 | CONFIG_PS3_DISK=y |
| 184 | CONFIG_PS3_ROM=y | 194 | CONFIG_PS3_ROM=y |
| 185 | CONFIG_PS3_FLASH=y | 195 | CONFIG_PS3_FLASH=y |
| 186 | CONFIG_OPROFILE_PS3=y | 196 | CONFIG_PS3_VRAM=m |
| 187 | CONFIG_PS3_LPM=m | 197 | CONFIG_PS3_LPM=m |
| 188 | CONFIG_PPC_CELL=y | 198 | CONFIG_PPC_CELL=y |
| 189 | # CONFIG_PPC_CELL_NATIVE is not set | 199 | # CONFIG_PPC_CELL_NATIVE is not set |
| 190 | # CONFIG_PPC_IBM_CELL_BLADE is not set | 200 | # CONFIG_PPC_IBM_CELL_BLADE is not set |
| 191 | # CONFIG_PPC_CELLEB is not set | 201 | # CONFIG_PPC_CELLEB is not set |
| 202 | # CONFIG_PPC_CELL_QPACE is not set | ||
| 192 | 203 | ||
| 193 | # | 204 | # |
| 194 | # Cell Broadband Engine options | 205 | # Cell Broadband Engine options |
| 195 | # | 206 | # |
| 196 | CONFIG_SPU_FS=y | 207 | CONFIG_SPU_FS=y |
| 197 | CONFIG_SPU_FS_64K_LS=y | 208 | CONFIG_SPU_FS_64K_LS=y |
| 209 | # CONFIG_SPU_TRACE is not set | ||
| 198 | CONFIG_SPU_BASE=y | 210 | CONFIG_SPU_BASE=y |
| 199 | # CONFIG_PQ2ADS is not set | 211 | # CONFIG_PQ2ADS is not set |
| 200 | # CONFIG_IPIC is not set | 212 | # CONFIG_IPIC is not set |
| @@ -210,6 +222,7 @@ CONFIG_SPU_BASE=y | |||
| 210 | # CONFIG_GENERIC_IOMAP is not set | 222 | # CONFIG_GENERIC_IOMAP is not set |
| 211 | # CONFIG_CPU_FREQ is not set | 223 | # CONFIG_CPU_FREQ is not set |
| 212 | # CONFIG_FSL_ULI1575 is not set | 224 | # CONFIG_FSL_ULI1575 is not set |
| 225 | # CONFIG_SIMPLE_GPIO is not set | ||
| 213 | 226 | ||
| 214 | # | 227 | # |
| 215 | # Kernel options | 228 | # Kernel options |
| @@ -229,6 +242,8 @@ CONFIG_PREEMPT_NONE=y | |||
| 229 | # CONFIG_PREEMPT is not set | 242 | # CONFIG_PREEMPT is not set |
| 230 | CONFIG_BINFMT_ELF=y | 243 | CONFIG_BINFMT_ELF=y |
| 231 | CONFIG_COMPAT_BINFMT_ELF=y | 244 | CONFIG_COMPAT_BINFMT_ELF=y |
| 245 | # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set | ||
| 246 | # CONFIG_HAVE_AOUT is not set | ||
| 232 | CONFIG_BINFMT_MISC=y | 247 | CONFIG_BINFMT_MISC=y |
| 233 | CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y | 248 | CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y |
| 234 | # CONFIG_IOMMU_VMERGE is not set | 249 | # CONFIG_IOMMU_VMERGE is not set |
| @@ -251,7 +266,6 @@ CONFIG_SELECT_MEMORY_MODEL=y | |||
| 251 | CONFIG_SPARSEMEM_MANUAL=y | 266 | CONFIG_SPARSEMEM_MANUAL=y |
| 252 | CONFIG_SPARSEMEM=y | 267 | CONFIG_SPARSEMEM=y |
| 253 | CONFIG_HAVE_MEMORY_PRESENT=y | 268 | CONFIG_HAVE_MEMORY_PRESENT=y |
| 254 | # CONFIG_SPARSEMEM_STATIC is not set | ||
| 255 | CONFIG_SPARSEMEM_EXTREME=y | 269 | CONFIG_SPARSEMEM_EXTREME=y |
| 256 | CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y | 270 | CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y |
| 257 | # CONFIG_SPARSEMEM_VMEMMAP is not set | 271 | # CONFIG_SPARSEMEM_VMEMMAP is not set |
| @@ -261,11 +275,14 @@ CONFIG_MEMORY_HOTPLUG_SPARSE=y | |||
| 261 | CONFIG_PAGEFLAGS_EXTENDED=y | 275 | CONFIG_PAGEFLAGS_EXTENDED=y |
| 262 | CONFIG_SPLIT_PTLOCK_CPUS=4 | 276 | CONFIG_SPLIT_PTLOCK_CPUS=4 |
| 263 | CONFIG_MIGRATION=y | 277 | CONFIG_MIGRATION=y |
| 264 | CONFIG_RESOURCES_64BIT=y | 278 | CONFIG_PHYS_ADDR_T_64BIT=y |
| 265 | CONFIG_ZONE_DMA_FLAG=1 | 279 | CONFIG_ZONE_DMA_FLAG=1 |
| 266 | CONFIG_BOUNCE=y | 280 | CONFIG_BOUNCE=y |
| 281 | CONFIG_UNEVICTABLE_LRU=y | ||
| 267 | CONFIG_ARCH_MEMORY_PROBE=y | 282 | CONFIG_ARCH_MEMORY_PROBE=y |
| 268 | CONFIG_PPC_HAS_HASH_64K=y | 283 | CONFIG_PPC_HAS_HASH_64K=y |
| 284 | CONFIG_PPC_4K_PAGES=y | ||
| 285 | # CONFIG_PPC_16K_PAGES is not set | ||
| 269 | # CONFIG_PPC_64K_PAGES is not set | 286 | # CONFIG_PPC_64K_PAGES is not set |
| 270 | CONFIG_FORCE_MAX_ZONEORDER=13 | 287 | CONFIG_FORCE_MAX_ZONEORDER=13 |
| 271 | CONFIG_SCHED_SMT=y | 288 | CONFIG_SCHED_SMT=y |
| @@ -299,6 +316,7 @@ CONFIG_NET=y | |||
| 299 | # | 316 | # |
| 300 | # Networking options | 317 | # Networking options |
| 301 | # | 318 | # |
| 319 | CONFIG_COMPAT_NET_DEV_OPS=y | ||
| 302 | CONFIG_PACKET=y | 320 | CONFIG_PACKET=y |
| 303 | CONFIG_PACKET_MMAP=y | 321 | CONFIG_PACKET_MMAP=y |
| 304 | CONFIG_UNIX=y | 322 | CONFIG_UNIX=y |
| @@ -361,6 +379,7 @@ CONFIG_IPV6_NDISC_NODETYPE=y | |||
| 361 | # CONFIG_TIPC is not set | 379 | # CONFIG_TIPC is not set |
| 362 | # CONFIG_ATM is not set | 380 | # CONFIG_ATM is not set |
| 363 | # CONFIG_BRIDGE is not set | 381 | # CONFIG_BRIDGE is not set |
| 382 | # CONFIG_NET_DSA is not set | ||
| 364 | # CONFIG_VLAN_8021Q is not set | 383 | # CONFIG_VLAN_8021Q is not set |
| 365 | # CONFIG_DECNET is not set | 384 | # CONFIG_DECNET is not set |
| 366 | # CONFIG_LLC2 is not set | 385 | # CONFIG_LLC2 is not set |
| @@ -371,6 +390,7 @@ CONFIG_IPV6_NDISC_NODETYPE=y | |||
| 371 | # CONFIG_ECONET is not set | 390 | # CONFIG_ECONET is not set |
| 372 | # CONFIG_WAN_ROUTER is not set | 391 | # CONFIG_WAN_ROUTER is not set |
| 373 | # CONFIG_NET_SCHED is not set | 392 | # CONFIG_NET_SCHED is not set |
| 393 | # CONFIG_DCB is not set | ||
| 374 | 394 | ||
| 375 | # | 395 | # |
| 376 | # Network testing | 396 | # Network testing |
| @@ -392,39 +412,37 @@ CONFIG_BT_HIDP=m | |||
| 392 | # | 412 | # |
| 393 | # Bluetooth device drivers | 413 | # Bluetooth device drivers |
| 394 | # | 414 | # |
| 395 | CONFIG_BT_HCIUSB=m | 415 | CONFIG_BT_HCIBTUSB=m |
| 396 | CONFIG_BT_HCIUSB_SCO=y | ||
| 397 | # CONFIG_BT_HCIUART is not set | 416 | # CONFIG_BT_HCIUART is not set |
| 398 | # CONFIG_BT_HCIBCM203X is not set | 417 | # CONFIG_BT_HCIBCM203X is not set |
| 399 | # CONFIG_BT_HCIBPA10X is not set | 418 | # CONFIG_BT_HCIBPA10X is not set |
| 400 | # CONFIG_BT_HCIBFUSB is not set | 419 | # CONFIG_BT_HCIBFUSB is not set |
| 401 | # CONFIG_BT_HCIVHCI is not set | 420 | # CONFIG_BT_HCIVHCI is not set |
| 402 | # CONFIG_AF_RXRPC is not set | 421 | # CONFIG_AF_RXRPC is not set |
| 403 | 422 | # CONFIG_PHONET is not set | |
| 404 | # | 423 | CONFIG_WIRELESS=y |
| 405 | # Wireless | ||
| 406 | # | ||
| 407 | CONFIG_CFG80211=m | 424 | CONFIG_CFG80211=m |
| 425 | # CONFIG_CFG80211_REG_DEBUG is not set | ||
| 408 | CONFIG_NL80211=y | 426 | CONFIG_NL80211=y |
| 427 | # CONFIG_WIRELESS_OLD_REGULATORY is not set | ||
| 409 | CONFIG_WIRELESS_EXT=y | 428 | CONFIG_WIRELESS_EXT=y |
| 410 | # CONFIG_WIRELESS_EXT_SYSFS is not set | 429 | # CONFIG_WIRELESS_EXT_SYSFS is not set |
| 430 | # CONFIG_LIB80211 is not set | ||
| 411 | CONFIG_MAC80211=m | 431 | CONFIG_MAC80211=m |
| 412 | 432 | ||
| 413 | # | 433 | # |
| 414 | # Rate control algorithm selection | 434 | # Rate control algorithm selection |
| 415 | # | 435 | # |
| 416 | CONFIG_MAC80211_RC_PID=y | 436 | CONFIG_MAC80211_RC_PID=y |
| 437 | # CONFIG_MAC80211_RC_MINSTREL is not set | ||
| 417 | CONFIG_MAC80211_RC_DEFAULT_PID=y | 438 | CONFIG_MAC80211_RC_DEFAULT_PID=y |
| 439 | # CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set | ||
| 418 | CONFIG_MAC80211_RC_DEFAULT="pid" | 440 | CONFIG_MAC80211_RC_DEFAULT="pid" |
| 419 | # CONFIG_MAC80211_MESH is not set | 441 | # CONFIG_MAC80211_MESH is not set |
| 420 | # CONFIG_MAC80211_LEDS is not set | 442 | # CONFIG_MAC80211_LEDS is not set |
| 421 | # CONFIG_MAC80211_DEBUGFS is not set | 443 | # CONFIG_MAC80211_DEBUGFS is not set |
| 422 | # CONFIG_MAC80211_DEBUG_MENU is not set | 444 | # CONFIG_MAC80211_DEBUG_MENU is not set |
| 423 | CONFIG_IEEE80211=m | 445 | # CONFIG_WIMAX is not set |
| 424 | # CONFIG_IEEE80211_DEBUG is not set | ||
| 425 | CONFIG_IEEE80211_CRYPT_WEP=m | ||
| 426 | CONFIG_IEEE80211_CRYPT_CCMP=m | ||
| 427 | CONFIG_IEEE80211_CRYPT_TKIP=m | ||
| 428 | # CONFIG_RFKILL is not set | 446 | # CONFIG_RFKILL is not set |
| 429 | # CONFIG_NET_9P is not set | 447 | # CONFIG_NET_9P is not set |
| 430 | 448 | ||
| @@ -450,6 +468,7 @@ CONFIG_MTD_DEBUG=y | |||
| 450 | CONFIG_MTD_DEBUG_VERBOSE=0 | 468 | CONFIG_MTD_DEBUG_VERBOSE=0 |
| 451 | # CONFIG_MTD_CONCAT is not set | 469 | # CONFIG_MTD_CONCAT is not set |
| 452 | # CONFIG_MTD_PARTITIONS is not set | 470 | # CONFIG_MTD_PARTITIONS is not set |
| 471 | # CONFIG_MTD_TESTS is not set | ||
| 453 | 472 | ||
| 454 | # | 473 | # |
| 455 | # User Modules And Translation Layers | 474 | # User Modules And Translation Layers |
| @@ -494,7 +513,6 @@ CONFIG_MTD_CFI_I2=y | |||
| 494 | # | 513 | # |
| 495 | # CONFIG_MTD_SLRAM is not set | 514 | # CONFIG_MTD_SLRAM is not set |
| 496 | # CONFIG_MTD_PHRAM is not set | 515 | # CONFIG_MTD_PHRAM is not set |
| 497 | CONFIG_MTD_PS3VRAM=y | ||
| 498 | # CONFIG_MTD_MTDRAM is not set | 516 | # CONFIG_MTD_MTDRAM is not set |
| 499 | # CONFIG_MTD_BLOCK2MTD is not set | 517 | # CONFIG_MTD_BLOCK2MTD is not set |
| 500 | 518 | ||
| @@ -508,6 +526,11 @@ CONFIG_MTD_PS3VRAM=y | |||
| 508 | # CONFIG_MTD_ONENAND is not set | 526 | # CONFIG_MTD_ONENAND is not set |
| 509 | 527 | ||
| 510 | # | 528 | # |
| 529 | # LPDDR flash memory drivers | ||
| 530 | # | ||
| 531 | # CONFIG_MTD_LPDDR is not set | ||
| 532 | |||
| 533 | # | ||
| 511 | # UBI - Unsorted block images | 534 | # UBI - Unsorted block images |
| 512 | # | 535 | # |
| 513 | # CONFIG_MTD_UBI is not set | 536 | # CONFIG_MTD_UBI is not set |
| @@ -528,8 +551,13 @@ CONFIG_BLK_DEV_RAM_SIZE=65535 | |||
| 528 | # CONFIG_ATA_OVER_ETH is not set | 551 | # CONFIG_ATA_OVER_ETH is not set |
| 529 | # CONFIG_BLK_DEV_HD is not set | 552 | # CONFIG_BLK_DEV_HD is not set |
| 530 | CONFIG_MISC_DEVICES=y | 553 | CONFIG_MISC_DEVICES=y |
| 531 | # CONFIG_EEPROM_93CX6 is not set | ||
| 532 | # CONFIG_ENCLOSURE_SERVICES is not set | 554 | # CONFIG_ENCLOSURE_SERVICES is not set |
| 555 | # CONFIG_C2PORT is not set | ||
| 556 | |||
| 557 | # | ||
| 558 | # EEPROM support | ||
| 559 | # | ||
| 560 | # CONFIG_EEPROM_93CX6 is not set | ||
| 533 | CONFIG_HAVE_IDE=y | 561 | CONFIG_HAVE_IDE=y |
| 534 | # CONFIG_IDE is not set | 562 | # CONFIG_IDE is not set |
| 535 | 563 | ||
| @@ -575,7 +603,17 @@ CONFIG_SCSI_WAIT_SCAN=m | |||
| 575 | # CONFIG_SCSI_LOWLEVEL is not set | 603 | # CONFIG_SCSI_LOWLEVEL is not set |
| 576 | # CONFIG_SCSI_DH is not set | 604 | # CONFIG_SCSI_DH is not set |
| 577 | # CONFIG_ATA is not set | 605 | # CONFIG_ATA is not set |
| 578 | # CONFIG_MD is not set | 606 | CONFIG_MD=y |
| 607 | # CONFIG_BLK_DEV_MD is not set | ||
| 608 | CONFIG_BLK_DEV_DM=m | ||
| 609 | # CONFIG_DM_DEBUG is not set | ||
| 610 | # CONFIG_DM_CRYPT is not set | ||
| 611 | # CONFIG_DM_SNAPSHOT is not set | ||
| 612 | # CONFIG_DM_MIRROR is not set | ||
| 613 | # CONFIG_DM_ZERO is not set | ||
| 614 | # CONFIG_DM_MULTIPATH is not set | ||
| 615 | # CONFIG_DM_DELAY is not set | ||
| 616 | # CONFIG_DM_UEVENT is not set | ||
| 579 | # CONFIG_MACINTOSH_DRIVERS is not set | 617 | # CONFIG_MACINTOSH_DRIVERS is not set |
| 580 | CONFIG_NETDEVICES=y | 618 | CONFIG_NETDEVICES=y |
| 581 | # CONFIG_DUMMY is not set | 619 | # CONFIG_DUMMY is not set |
| @@ -591,6 +629,9 @@ CONFIG_MII=m | |||
| 591 | # CONFIG_IBM_NEW_EMAC_RGMII is not set | 629 | # CONFIG_IBM_NEW_EMAC_RGMII is not set |
| 592 | # CONFIG_IBM_NEW_EMAC_TAH is not set | 630 | # CONFIG_IBM_NEW_EMAC_TAH is not set |
| 593 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set | 631 | # CONFIG_IBM_NEW_EMAC_EMAC4 is not set |
| 632 | # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set | ||
| 633 | # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set | ||
| 634 | # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set | ||
| 594 | # CONFIG_B44 is not set | 635 | # CONFIG_B44 is not set |
| 595 | CONFIG_NETDEV_1000=y | 636 | CONFIG_NETDEV_1000=y |
| 596 | CONFIG_GELIC_NET=y | 637 | CONFIG_GELIC_NET=y |
| @@ -604,6 +645,7 @@ CONFIG_GELIC_WIRELESS_OLD_PSK_INTERFACE=y | |||
| 604 | # CONFIG_WLAN_PRE80211 is not set | 645 | # CONFIG_WLAN_PRE80211 is not set |
| 605 | CONFIG_WLAN_80211=y | 646 | CONFIG_WLAN_80211=y |
| 606 | # CONFIG_LIBERTAS is not set | 647 | # CONFIG_LIBERTAS is not set |
| 648 | # CONFIG_LIBERTAS_THINFIRM is not set | ||
| 607 | # CONFIG_USB_ZD1201 is not set | 649 | # CONFIG_USB_ZD1201 is not set |
| 608 | # CONFIG_USB_NET_RNDIS_WLAN is not set | 650 | # CONFIG_USB_NET_RNDIS_WLAN is not set |
| 609 | # CONFIG_RTL8187 is not set | 651 | # CONFIG_RTL8187 is not set |
| @@ -615,13 +657,11 @@ CONFIG_WLAN_80211=y | |||
| 615 | # CONFIG_B43LEGACY is not set | 657 | # CONFIG_B43LEGACY is not set |
| 616 | CONFIG_ZD1211RW=m | 658 | CONFIG_ZD1211RW=m |
| 617 | # CONFIG_ZD1211RW_DEBUG is not set | 659 | # CONFIG_ZD1211RW_DEBUG is not set |
| 618 | CONFIG_RT2X00=m | 660 | # CONFIG_RT2X00 is not set |
| 619 | CONFIG_RT2X00_LIB=m | 661 | |
| 620 | CONFIG_RT2X00_LIB_USB=m | 662 | # |
| 621 | CONFIG_RT2X00_LIB_FIRMWARE=y | 663 | # Enable WiMAX (Networking options) to see the WiMAX drivers |
| 622 | # CONFIG_RT2500USB is not set | 664 | # |
| 623 | CONFIG_RT73USB=m | ||
| 624 | # CONFIG_RT2X00_DEBUG is not set | ||
| 625 | 665 | ||
| 626 | # | 666 | # |
| 627 | # USB Network Adapters | 667 | # USB Network Adapters |
| @@ -634,6 +674,7 @@ CONFIG_USB_USBNET=m | |||
| 634 | CONFIG_USB_NET_AX8817X=m | 674 | CONFIG_USB_NET_AX8817X=m |
| 635 | # CONFIG_USB_NET_CDCETHER is not set | 675 | # CONFIG_USB_NET_CDCETHER is not set |
| 636 | # CONFIG_USB_NET_DM9601 is not set | 676 | # CONFIG_USB_NET_DM9601 is not set |
| 677 | # CONFIG_USB_NET_SMSC95XX is not set | ||
| 637 | # CONFIG_USB_NET_GL620A is not set | 678 | # CONFIG_USB_NET_GL620A is not set |
| 638 | # CONFIG_USB_NET_NET1080 is not set | 679 | # CONFIG_USB_NET_NET1080 is not set |
| 639 | # CONFIG_USB_NET_PLUSB is not set | 680 | # CONFIG_USB_NET_PLUSB is not set |
| @@ -664,7 +705,7 @@ CONFIG_SLHC=m | |||
| 664 | # Input device support | 705 | # Input device support |
| 665 | # | 706 | # |
| 666 | CONFIG_INPUT=y | 707 | CONFIG_INPUT=y |
| 667 | # CONFIG_INPUT_FF_MEMLESS is not set | 708 | CONFIG_INPUT_FF_MEMLESS=m |
| 668 | # CONFIG_INPUT_POLLDEV is not set | 709 | # CONFIG_INPUT_POLLDEV is not set |
| 669 | 710 | ||
| 670 | # | 711 | # |
| @@ -735,8 +776,10 @@ CONFIG_DEVKMEM=y | |||
| 735 | # Non-8250 serial port support | 776 | # Non-8250 serial port support |
| 736 | # | 777 | # |
| 737 | CONFIG_UNIX98_PTYS=y | 778 | CONFIG_UNIX98_PTYS=y |
| 779 | # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set | ||
| 738 | CONFIG_LEGACY_PTYS=y | 780 | CONFIG_LEGACY_PTYS=y |
| 739 | CONFIG_LEGACY_PTY_COUNT=16 | 781 | CONFIG_LEGACY_PTY_COUNT=16 |
| 782 | # CONFIG_HVC_UDBG is not set | ||
| 740 | # CONFIG_IPMI_HANDLER is not set | 783 | # CONFIG_IPMI_HANDLER is not set |
| 741 | # CONFIG_HW_RANDOM is not set | 784 | # CONFIG_HW_RANDOM is not set |
| 742 | # CONFIG_R3964 is not set | 785 | # CONFIG_R3964 is not set |
| @@ -753,11 +796,11 @@ CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y | |||
| 753 | # CONFIG_THERMAL is not set | 796 | # CONFIG_THERMAL is not set |
| 754 | # CONFIG_THERMAL_HWMON is not set | 797 | # CONFIG_THERMAL_HWMON is not set |
| 755 | # CONFIG_WATCHDOG is not set | 798 | # CONFIG_WATCHDOG is not set |
| 799 | CONFIG_SSB_POSSIBLE=y | ||
| 756 | 800 | ||
| 757 | # | 801 | # |
| 758 | # Sonics Silicon Backplane | 802 | # Sonics Silicon Backplane |
| 759 | # | 803 | # |
| 760 | CONFIG_SSB_POSSIBLE=y | ||
| 761 | # CONFIG_SSB is not set | 804 | # CONFIG_SSB is not set |
| 762 | 805 | ||
| 763 | # | 806 | # |
| @@ -767,6 +810,7 @@ CONFIG_SSB_POSSIBLE=y | |||
| 767 | # CONFIG_MFD_SM501 is not set | 810 | # CONFIG_MFD_SM501 is not set |
| 768 | # CONFIG_HTC_PASIC3 is not set | 811 | # CONFIG_HTC_PASIC3 is not set |
| 769 | # CONFIG_MFD_TMIO is not set | 812 | # CONFIG_MFD_TMIO is not set |
| 813 | # CONFIG_REGULATOR is not set | ||
| 770 | 814 | ||
| 771 | # | 815 | # |
| 772 | # Multimedia devices | 816 | # Multimedia devices |
| @@ -792,6 +836,7 @@ CONFIG_VIDEO_OUTPUT_CONTROL=m | |||
| 792 | CONFIG_FB=y | 836 | CONFIG_FB=y |
| 793 | # CONFIG_FIRMWARE_EDID is not set | 837 | # CONFIG_FIRMWARE_EDID is not set |
| 794 | # CONFIG_FB_DDC is not set | 838 | # CONFIG_FB_DDC is not set |
| 839 | # CONFIG_FB_BOOT_VESA_SUPPORT is not set | ||
| 795 | # CONFIG_FB_CFB_FILLRECT is not set | 840 | # CONFIG_FB_CFB_FILLRECT is not set |
| 796 | # CONFIG_FB_CFB_COPYAREA is not set | 841 | # CONFIG_FB_CFB_COPYAREA is not set |
| 797 | # CONFIG_FB_CFB_IMAGEBLIT is not set | 842 | # CONFIG_FB_CFB_IMAGEBLIT is not set |
| @@ -817,6 +862,8 @@ CONFIG_FB_SYS_FOPS=y | |||
| 817 | CONFIG_FB_PS3=y | 862 | CONFIG_FB_PS3=y |
| 818 | CONFIG_FB_PS3_DEFAULT_SIZE_M=9 | 863 | CONFIG_FB_PS3_DEFAULT_SIZE_M=9 |
| 819 | # CONFIG_FB_VIRTUAL is not set | 864 | # CONFIG_FB_VIRTUAL is not set |
| 865 | # CONFIG_FB_METRONOME is not set | ||
| 866 | # CONFIG_FB_MB862XX is not set | ||
| 820 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set | 867 | # CONFIG_BACKLIGHT_LCD_SUPPORT is not set |
| 821 | 868 | ||
| 822 | # | 869 | # |
| @@ -841,6 +888,7 @@ CONFIG_FB_LOGO_EXTRA=y | |||
| 841 | # CONFIG_LOGO_LINUX_VGA16 is not set | 888 | # CONFIG_LOGO_LINUX_VGA16 is not set |
| 842 | CONFIG_LOGO_LINUX_CLUT224=y | 889 | CONFIG_LOGO_LINUX_CLUT224=y |
| 843 | CONFIG_SOUND=m | 890 | CONFIG_SOUND=m |
| 891 | # CONFIG_SOUND_OSS_CORE is not set | ||
| 844 | CONFIG_SND=m | 892 | CONFIG_SND=m |
| 845 | CONFIG_SND_TIMER=m | 893 | CONFIG_SND_TIMER=m |
| 846 | CONFIG_SND_PCM=m | 894 | CONFIG_SND_PCM=m |
| @@ -849,6 +897,7 @@ CONFIG_SND_RAWMIDI=m | |||
| 849 | # CONFIG_SND_SEQUENCER is not set | 897 | # CONFIG_SND_SEQUENCER is not set |
| 850 | # CONFIG_SND_MIXER_OSS is not set | 898 | # CONFIG_SND_MIXER_OSS is not set |
| 851 | # CONFIG_SND_PCM_OSS is not set | 899 | # CONFIG_SND_PCM_OSS is not set |
| 900 | # CONFIG_SND_HRTIMER is not set | ||
| 852 | # CONFIG_SND_DYNAMIC_MINORS is not set | 901 | # CONFIG_SND_DYNAMIC_MINORS is not set |
| 853 | CONFIG_SND_SUPPORT_OLD_API=y | 902 | CONFIG_SND_SUPPORT_OLD_API=y |
| 854 | CONFIG_SND_VERBOSE_PROCFS=y | 903 | CONFIG_SND_VERBOSE_PROCFS=y |
| @@ -873,15 +922,40 @@ CONFIG_HIDRAW=y | |||
| 873 | # USB Input Devices | 922 | # USB Input Devices |
| 874 | # | 923 | # |
| 875 | CONFIG_USB_HID=m | 924 | CONFIG_USB_HID=m |
| 876 | # CONFIG_USB_HIDINPUT_POWERBOOK is not set | 925 | # CONFIG_HID_PID is not set |
| 877 | # CONFIG_HID_FF is not set | 926 | CONFIG_USB_HIDDEV=y |
| 878 | # CONFIG_USB_HIDDEV is not set | ||
| 879 | 927 | ||
| 880 | # | 928 | # |
| 881 | # USB HID Boot Protocol drivers | 929 | # USB HID Boot Protocol drivers |
| 882 | # | 930 | # |
| 883 | # CONFIG_USB_KBD is not set | 931 | # CONFIG_USB_KBD is not set |
| 884 | # CONFIG_USB_MOUSE is not set | 932 | # CONFIG_USB_MOUSE is not set |
| 933 | |||
| 934 | # | ||
| 935 | # Special HID drivers | ||
| 936 | # | ||
| 937 | # CONFIG_HID_COMPAT is not set | ||
| 938 | # CONFIG_HID_A4TECH is not set | ||
| 939 | # CONFIG_HID_APPLE is not set | ||
| 940 | # CONFIG_HID_BELKIN is not set | ||
| 941 | # CONFIG_HID_CHERRY is not set | ||
| 942 | # CONFIG_HID_CHICONY is not set | ||
| 943 | # CONFIG_HID_CYPRESS is not set | ||
| 944 | # CONFIG_HID_EZKEY is not set | ||
| 945 | # CONFIG_HID_GYRATION is not set | ||
| 946 | # CONFIG_HID_LOGITECH is not set | ||
| 947 | # CONFIG_HID_MICROSOFT is not set | ||
| 948 | # CONFIG_HID_MONTEREY is not set | ||
| 949 | # CONFIG_HID_NTRIG is not set | ||
| 950 | # CONFIG_HID_PANTHERLORD is not set | ||
| 951 | # CONFIG_HID_PETALYNX is not set | ||
| 952 | # CONFIG_HID_SAMSUNG is not set | ||
| 953 | # CONFIG_HID_SONY is not set | ||
| 954 | # CONFIG_HID_SUNPLUS is not set | ||
| 955 | # CONFIG_GREENASIA_FF is not set | ||
| 956 | # CONFIG_HID_TOPSEED is not set | ||
| 957 | # CONFIG_THRUSTMASTER_FF is not set | ||
| 958 | # CONFIG_ZEROPLUS_FF is not set | ||
| 885 | CONFIG_USB_SUPPORT=y | 959 | CONFIG_USB_SUPPORT=y |
| 886 | CONFIG_USB_ARCH_HAS_HCD=y | 960 | CONFIG_USB_ARCH_HAS_HCD=y |
| 887 | CONFIG_USB_ARCH_HAS_OHCI=y | 961 | CONFIG_USB_ARCH_HAS_OHCI=y |
| @@ -898,7 +972,11 @@ CONFIG_USB_DEVICEFS=y | |||
| 898 | # CONFIG_USB_DYNAMIC_MINORS is not set | 972 | # CONFIG_USB_DYNAMIC_MINORS is not set |
| 899 | CONFIG_USB_SUSPEND=y | 973 | CONFIG_USB_SUSPEND=y |
| 900 | # CONFIG_USB_OTG is not set | 974 | # CONFIG_USB_OTG is not set |
| 901 | CONFIG_USB_MON=y | 975 | # CONFIG_USB_OTG_WHITELIST is not set |
| 976 | # CONFIG_USB_OTG_BLACKLIST_HUB is not set | ||
| 977 | CONFIG_USB_MON=m | ||
| 978 | # CONFIG_USB_WUSB is not set | ||
| 979 | # CONFIG_USB_WUSB_CBAF is not set | ||
| 902 | 980 | ||
| 903 | # | 981 | # |
| 904 | # USB Host Controller Drivers | 982 | # USB Host Controller Drivers |
| @@ -909,6 +987,7 @@ CONFIG_USB_EHCI_HCD=m | |||
| 909 | # CONFIG_USB_EHCI_TT_NEWSCHED is not set | 987 | # CONFIG_USB_EHCI_TT_NEWSCHED is not set |
| 910 | CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y | 988 | CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y |
| 911 | # CONFIG_USB_EHCI_HCD_PPC_OF is not set | 989 | # CONFIG_USB_EHCI_HCD_PPC_OF is not set |
| 990 | # CONFIG_USB_OXU210HP_HCD is not set | ||
| 912 | # CONFIG_USB_ISP116X_HCD is not set | 991 | # CONFIG_USB_ISP116X_HCD is not set |
| 913 | # CONFIG_USB_ISP1760_HCD is not set | 992 | # CONFIG_USB_ISP1760_HCD is not set |
| 914 | CONFIG_USB_OHCI_HCD=m | 993 | CONFIG_USB_OHCI_HCD=m |
| @@ -918,6 +997,7 @@ CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y | |||
| 918 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y | 997 | CONFIG_USB_OHCI_LITTLE_ENDIAN=y |
| 919 | # CONFIG_USB_SL811_HCD is not set | 998 | # CONFIG_USB_SL811_HCD is not set |
| 920 | # CONFIG_USB_R8A66597_HCD is not set | 999 | # CONFIG_USB_R8A66597_HCD is not set |
| 1000 | # CONFIG_USB_HWA_HCD is not set | ||
| 921 | 1001 | ||
| 922 | # | 1002 | # |
| 923 | # Enable Host or Gadget support to see Inventra options | 1003 | # Enable Host or Gadget support to see Inventra options |
| @@ -929,20 +1009,20 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y | |||
| 929 | # CONFIG_USB_ACM is not set | 1009 | # CONFIG_USB_ACM is not set |
| 930 | # CONFIG_USB_PRINTER is not set | 1010 | # CONFIG_USB_PRINTER is not set |
| 931 | # CONFIG_USB_WDM is not set | 1011 | # CONFIG_USB_WDM is not set |
| 1012 | # CONFIG_USB_TMC is not set | ||
| 932 | 1013 | ||
| 933 | # | 1014 | # |
| 934 | # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' | 1015 | # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; |
| 935 | # | 1016 | # |
| 936 | 1017 | ||
| 937 | # | 1018 | # |
| 938 | # may also be needed; see USB_STORAGE Help for more information | 1019 | # see USB_STORAGE Help for more information |
| 939 | # | 1020 | # |
| 940 | CONFIG_USB_STORAGE=m | 1021 | CONFIG_USB_STORAGE=m |
| 941 | # CONFIG_USB_STORAGE_DEBUG is not set | 1022 | # CONFIG_USB_STORAGE_DEBUG is not set |
| 942 | # CONFIG_USB_STORAGE_DATAFAB is not set | 1023 | # CONFIG_USB_STORAGE_DATAFAB is not set |
| 943 | # CONFIG_USB_STORAGE_FREECOM is not set | 1024 | # CONFIG_USB_STORAGE_FREECOM is not set |
| 944 | # CONFIG_USB_STORAGE_ISD200 is not set | 1025 | # CONFIG_USB_STORAGE_ISD200 is not set |
| 945 | # CONFIG_USB_STORAGE_DPCM is not set | ||
| 946 | # CONFIG_USB_STORAGE_USBAT is not set | 1026 | # CONFIG_USB_STORAGE_USBAT is not set |
| 947 | # CONFIG_USB_STORAGE_SDDR09 is not set | 1027 | # CONFIG_USB_STORAGE_SDDR09 is not set |
| 948 | # CONFIG_USB_STORAGE_SDDR55 is not set | 1028 | # CONFIG_USB_STORAGE_SDDR55 is not set |
| @@ -950,7 +1030,6 @@ CONFIG_USB_STORAGE=m | |||
| 950 | # CONFIG_USB_STORAGE_ALAUDA is not set | 1030 | # CONFIG_USB_STORAGE_ALAUDA is not set |
| 951 | # CONFIG_USB_STORAGE_ONETOUCH is not set | 1031 | # CONFIG_USB_STORAGE_ONETOUCH is not set |
| 952 | # CONFIG_USB_STORAGE_KARMA is not set | 1032 | # CONFIG_USB_STORAGE_KARMA is not set |
| 953 | # CONFIG_USB_STORAGE_SIERRA is not set | ||
| 954 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set | 1033 | # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set |
| 955 | # CONFIG_USB_LIBUSUAL is not set | 1034 | # CONFIG_USB_LIBUSUAL is not set |
| 956 | 1035 | ||
| @@ -971,6 +1050,7 @@ CONFIG_USB_STORAGE=m | |||
| 971 | # CONFIG_USB_EMI62 is not set | 1050 | # CONFIG_USB_EMI62 is not set |
| 972 | # CONFIG_USB_EMI26 is not set | 1051 | # CONFIG_USB_EMI26 is not set |
| 973 | # CONFIG_USB_ADUTUX is not set | 1052 | # CONFIG_USB_ADUTUX is not set |
| 1053 | # CONFIG_USB_SEVSEG is not set | ||
| 974 | # CONFIG_USB_RIO500 is not set | 1054 | # CONFIG_USB_RIO500 is not set |
| 975 | # CONFIG_USB_LEGOTOWER is not set | 1055 | # CONFIG_USB_LEGOTOWER is not set |
| 976 | # CONFIG_USB_LCD is not set | 1056 | # CONFIG_USB_LCD is not set |
| @@ -988,7 +1068,12 @@ CONFIG_USB_STORAGE=m | |||
| 988 | # CONFIG_USB_IOWARRIOR is not set | 1068 | # CONFIG_USB_IOWARRIOR is not set |
| 989 | # CONFIG_USB_TEST is not set | 1069 | # CONFIG_USB_TEST is not set |
| 990 | # CONFIG_USB_ISIGHTFW is not set | 1070 | # CONFIG_USB_ISIGHTFW is not set |
| 1071 | # CONFIG_USB_VST is not set | ||
| 991 | # CONFIG_USB_GADGET is not set | 1072 | # CONFIG_USB_GADGET is not set |
| 1073 | |||
| 1074 | # | ||
| 1075 | # OTG and related infrastructure | ||
| 1076 | # | ||
| 992 | # CONFIG_MMC is not set | 1077 | # CONFIG_MMC is not set |
| 993 | # CONFIG_MEMSTICK is not set | 1078 | # CONFIG_MEMSTICK is not set |
| 994 | # CONFIG_NEW_LEDS is not set | 1079 | # CONFIG_NEW_LEDS is not set |
| @@ -1014,12 +1099,15 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1014 | # Platform RTC drivers | 1099 | # Platform RTC drivers |
| 1015 | # | 1100 | # |
| 1016 | # CONFIG_RTC_DRV_CMOS is not set | 1101 | # CONFIG_RTC_DRV_CMOS is not set |
| 1102 | # CONFIG_RTC_DRV_DS1286 is not set | ||
| 1017 | # CONFIG_RTC_DRV_DS1511 is not set | 1103 | # CONFIG_RTC_DRV_DS1511 is not set |
| 1018 | # CONFIG_RTC_DRV_DS1553 is not set | 1104 | # CONFIG_RTC_DRV_DS1553 is not set |
| 1019 | # CONFIG_RTC_DRV_DS1742 is not set | 1105 | # CONFIG_RTC_DRV_DS1742 is not set |
| 1020 | # CONFIG_RTC_DRV_STK17TA8 is not set | 1106 | # CONFIG_RTC_DRV_STK17TA8 is not set |
| 1021 | # CONFIG_RTC_DRV_M48T86 is not set | 1107 | # CONFIG_RTC_DRV_M48T86 is not set |
| 1108 | # CONFIG_RTC_DRV_M48T35 is not set | ||
| 1022 | # CONFIG_RTC_DRV_M48T59 is not set | 1109 | # CONFIG_RTC_DRV_M48T59 is not set |
| 1110 | # CONFIG_RTC_DRV_BQ4802 is not set | ||
| 1023 | # CONFIG_RTC_DRV_V3020 is not set | 1111 | # CONFIG_RTC_DRV_V3020 is not set |
| 1024 | 1112 | ||
| 1025 | # | 1113 | # |
| @@ -1028,6 +1116,7 @@ CONFIG_RTC_INTF_DEV=y | |||
| 1028 | CONFIG_RTC_DRV_PPC=m | 1116 | CONFIG_RTC_DRV_PPC=m |
| 1029 | # CONFIG_DMADEVICES is not set | 1117 | # CONFIG_DMADEVICES is not set |
| 1030 | # CONFIG_UIO is not set | 1118 | # CONFIG_UIO is not set |
| 1119 | # CONFIG_STAGING is not set | ||
| 1031 | 1120 | ||
| 1032 | # | 1121 | # |
| 1033 | # File systems | 1122 | # File systems |
| @@ -1035,26 +1124,35 @@ CONFIG_RTC_DRV_PPC=m | |||
| 1035 | CONFIG_EXT2_FS=m | 1124 | CONFIG_EXT2_FS=m |
| 1036 | # CONFIG_EXT2_FS_XATTR is not set | 1125 | # CONFIG_EXT2_FS_XATTR is not set |
| 1037 | # CONFIG_EXT2_FS_XIP is not set | 1126 | # CONFIG_EXT2_FS_XIP is not set |
| 1038 | CONFIG_EXT3_FS=y | 1127 | CONFIG_EXT3_FS=m |
| 1039 | CONFIG_EXT3_FS_XATTR=y | 1128 | CONFIG_EXT3_FS_XATTR=y |
| 1040 | # CONFIG_EXT3_FS_POSIX_ACL is not set | 1129 | # CONFIG_EXT3_FS_POSIX_ACL is not set |
| 1041 | # CONFIG_EXT3_FS_SECURITY is not set | 1130 | # CONFIG_EXT3_FS_SECURITY is not set |
| 1042 | # CONFIG_EXT4DEV_FS is not set | 1131 | CONFIG_EXT4_FS=y |
| 1043 | CONFIG_JBD=y | 1132 | # CONFIG_EXT4DEV_COMPAT is not set |
| 1133 | CONFIG_EXT4_FS_XATTR=y | ||
| 1134 | # CONFIG_EXT4_FS_POSIX_ACL is not set | ||
| 1135 | # CONFIG_EXT4_FS_SECURITY is not set | ||
| 1136 | CONFIG_JBD=m | ||
| 1044 | # CONFIG_JBD_DEBUG is not set | 1137 | # CONFIG_JBD_DEBUG is not set |
| 1138 | CONFIG_JBD2=y | ||
| 1139 | # CONFIG_JBD2_DEBUG is not set | ||
| 1045 | CONFIG_FS_MBCACHE=y | 1140 | CONFIG_FS_MBCACHE=y |
| 1046 | # CONFIG_REISERFS_FS is not set | 1141 | # CONFIG_REISERFS_FS is not set |
| 1047 | # CONFIG_JFS_FS is not set | 1142 | # CONFIG_JFS_FS is not set |
| 1048 | # CONFIG_FS_POSIX_ACL is not set | 1143 | # CONFIG_FS_POSIX_ACL is not set |
| 1144 | CONFIG_FILE_LOCKING=y | ||
| 1049 | # CONFIG_XFS_FS is not set | 1145 | # CONFIG_XFS_FS is not set |
| 1050 | # CONFIG_GFS2_FS is not set | 1146 | # CONFIG_GFS2_FS is not set |
| 1051 | # CONFIG_OCFS2_FS is not set | 1147 | # CONFIG_OCFS2_FS is not set |
| 1148 | # CONFIG_BTRFS_FS is not set | ||
| 1052 | CONFIG_DNOTIFY=y | 1149 | CONFIG_DNOTIFY=y |
| 1053 | CONFIG_INOTIFY=y | 1150 | CONFIG_INOTIFY=y |
| 1054 | CONFIG_INOTIFY_USER=y | 1151 | CONFIG_INOTIFY_USER=y |
| 1055 | CONFIG_QUOTA=y | 1152 | CONFIG_QUOTA=y |
| 1056 | # CONFIG_QUOTA_NETLINK_INTERFACE is not set | 1153 | # CONFIG_QUOTA_NETLINK_INTERFACE is not set |
| 1057 | CONFIG_PRINT_QUOTA_WARNING=y | 1154 | CONFIG_PRINT_QUOTA_WARNING=y |
| 1155 | CONFIG_QUOTA_TREE=y | ||
| 1058 | # CONFIG_QFMT_V1 is not set | 1156 | # CONFIG_QFMT_V1 is not set |
| 1059 | CONFIG_QFMT_V2=y | 1157 | CONFIG_QFMT_V2=y |
| 1060 | CONFIG_QUOTACTL=y | 1158 | CONFIG_QUOTACTL=y |
| @@ -1087,16 +1185,14 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" | |||
| 1087 | CONFIG_PROC_FS=y | 1185 | CONFIG_PROC_FS=y |
| 1088 | CONFIG_PROC_KCORE=y | 1186 | CONFIG_PROC_KCORE=y |
| 1089 | CONFIG_PROC_SYSCTL=y | 1187 | CONFIG_PROC_SYSCTL=y |
| 1188 | CONFIG_PROC_PAGE_MONITOR=y | ||
| 1090 | CONFIG_SYSFS=y | 1189 | CONFIG_SYSFS=y |
| 1091 | CONFIG_TMPFS=y | 1190 | CONFIG_TMPFS=y |
| 1092 | # CONFIG_TMPFS_POSIX_ACL is not set | 1191 | # CONFIG_TMPFS_POSIX_ACL is not set |
| 1093 | CONFIG_HUGETLBFS=y | 1192 | CONFIG_HUGETLBFS=y |
| 1094 | CONFIG_HUGETLB_PAGE=y | 1193 | CONFIG_HUGETLB_PAGE=y |
| 1095 | # CONFIG_CONFIGFS_FS is not set | 1194 | # CONFIG_CONFIGFS_FS is not set |
| 1096 | 1195 | CONFIG_MISC_FILESYSTEMS=y | |
| 1097 | # | ||
| 1098 | # Miscellaneous filesystems | ||
| 1099 | # | ||
| 1100 | # CONFIG_ADFS_FS is not set | 1196 | # CONFIG_ADFS_FS is not set |
| 1101 | # CONFIG_AFFS_FS is not set | 1197 | # CONFIG_AFFS_FS is not set |
| 1102 | # CONFIG_HFS_FS is not set | 1198 | # CONFIG_HFS_FS is not set |
| @@ -1106,6 +1202,7 @@ CONFIG_HUGETLB_PAGE=y | |||
| 1106 | # CONFIG_EFS_FS is not set | 1202 | # CONFIG_EFS_FS is not set |
| 1107 | # CONFIG_JFFS2_FS is not set | 1203 | # CONFIG_JFFS2_FS is not set |
| 1108 | # CONFIG_CRAMFS is not set | 1204 | # CONFIG_CRAMFS is not set |
| 1205 | # CONFIG_SQUASHFS is not set | ||
| 1109 | # CONFIG_VXFS_FS is not set | 1206 | # CONFIG_VXFS_FS is not set |
| 1110 | # CONFIG_MINIX_FS is not set | 1207 | # CONFIG_MINIX_FS is not set |
| 1111 | # CONFIG_OMFS_FS is not set | 1208 | # CONFIG_OMFS_FS is not set |
| @@ -1126,6 +1223,7 @@ CONFIG_LOCKD_V4=y | |||
| 1126 | CONFIG_NFS_COMMON=y | 1223 | CONFIG_NFS_COMMON=y |
| 1127 | CONFIG_SUNRPC=y | 1224 | CONFIG_SUNRPC=y |
| 1128 | CONFIG_SUNRPC_GSS=y | 1225 | CONFIG_SUNRPC_GSS=y |
| 1226 | # CONFIG_SUNRPC_REGISTER_V4 is not set | ||
| 1129 | CONFIG_RPCSEC_GSS_KRB5=y | 1227 | CONFIG_RPCSEC_GSS_KRB5=y |
| 1130 | # CONFIG_RPCSEC_GSS_SPKM3 is not set | 1228 | # CONFIG_RPCSEC_GSS_SPKM3 is not set |
| 1131 | # CONFIG_SMB_FS is not set | 1229 | # CONFIG_SMB_FS is not set |
| @@ -1190,9 +1288,9 @@ CONFIG_NLS_ISO8859_1=y | |||
| 1190 | # Library routines | 1288 | # Library routines |
| 1191 | # | 1289 | # |
| 1192 | CONFIG_BITREVERSE=y | 1290 | CONFIG_BITREVERSE=y |
| 1193 | # CONFIG_GENERIC_FIND_FIRST_BIT is not set | 1291 | CONFIG_GENERIC_FIND_LAST_BIT=y |
| 1194 | CONFIG_CRC_CCITT=m | 1292 | CONFIG_CRC_CCITT=m |
| 1195 | # CONFIG_CRC16 is not set | 1293 | CONFIG_CRC16=y |
| 1196 | CONFIG_CRC_T10DIF=y | 1294 | CONFIG_CRC_T10DIF=y |
| 1197 | CONFIG_CRC_ITU_T=m | 1295 | CONFIG_CRC_ITU_T=m |
| 1198 | CONFIG_CRC32=y | 1296 | CONFIG_CRC32=y |
| @@ -1250,27 +1348,44 @@ CONFIG_DEBUG_WRITECOUNT=y | |||
| 1250 | CONFIG_DEBUG_MEMORY_INIT=y | 1348 | CONFIG_DEBUG_MEMORY_INIT=y |
| 1251 | CONFIG_DEBUG_LIST=y | 1349 | CONFIG_DEBUG_LIST=y |
| 1252 | # CONFIG_DEBUG_SG is not set | 1350 | # CONFIG_DEBUG_SG is not set |
| 1253 | CONFIG_FRAME_POINTER=y | 1351 | # CONFIG_DEBUG_NOTIFIERS is not set |
| 1254 | # CONFIG_BOOT_PRINTK_DELAY is not set | 1352 | # CONFIG_BOOT_PRINTK_DELAY is not set |
| 1255 | # CONFIG_RCU_TORTURE_TEST is not set | 1353 | # CONFIG_RCU_TORTURE_TEST is not set |
| 1354 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
| 1256 | # CONFIG_BACKTRACE_SELF_TEST is not set | 1355 | # CONFIG_BACKTRACE_SELF_TEST is not set |
| 1356 | # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set | ||
| 1257 | # CONFIG_FAULT_INJECTION is not set | 1357 | # CONFIG_FAULT_INJECTION is not set |
| 1258 | # CONFIG_LATENCYTOP is not set | 1358 | # CONFIG_LATENCYTOP is not set |
| 1259 | CONFIG_SYSCTL_SYSCALL_CHECK=y | 1359 | CONFIG_SYSCTL_SYSCALL_CHECK=y |
| 1260 | CONFIG_HAVE_FTRACE=y | 1360 | CONFIG_NOP_TRACER=y |
| 1361 | CONFIG_HAVE_FUNCTION_TRACER=y | ||
| 1261 | CONFIG_HAVE_DYNAMIC_FTRACE=y | 1362 | CONFIG_HAVE_DYNAMIC_FTRACE=y |
| 1262 | # CONFIG_FTRACE is not set | 1363 | CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y |
| 1364 | CONFIG_RING_BUFFER=y | ||
| 1365 | CONFIG_TRACING=y | ||
| 1366 | |||
| 1367 | # | ||
| 1368 | # Tracers | ||
| 1369 | # | ||
| 1370 | # CONFIG_FUNCTION_TRACER is not set | ||
| 1263 | # CONFIG_IRQSOFF_TRACER is not set | 1371 | # CONFIG_IRQSOFF_TRACER is not set |
| 1264 | # CONFIG_SCHED_TRACER is not set | 1372 | # CONFIG_SCHED_TRACER is not set |
| 1265 | # CONFIG_CONTEXT_SWITCH_TRACER is not set | 1373 | # CONFIG_CONTEXT_SWITCH_TRACER is not set |
| 1374 | # CONFIG_BOOT_TRACER is not set | ||
| 1375 | # CONFIG_TRACE_BRANCH_PROFILING is not set | ||
| 1376 | # CONFIG_STACK_TRACER is not set | ||
| 1377 | # CONFIG_FTRACE_STARTUP_TEST is not set | ||
| 1378 | # CONFIG_DYNAMIC_PRINTK_DEBUG is not set | ||
| 1266 | # CONFIG_SAMPLES is not set | 1379 | # CONFIG_SAMPLES is not set |
| 1267 | CONFIG_HAVE_ARCH_KGDB=y | 1380 | CONFIG_HAVE_ARCH_KGDB=y |
| 1268 | # CONFIG_KGDB is not set | 1381 | # CONFIG_KGDB is not set |
| 1382 | CONFIG_PRINT_STACK_DEPTH=64 | ||
| 1269 | CONFIG_DEBUG_STACKOVERFLOW=y | 1383 | CONFIG_DEBUG_STACKOVERFLOW=y |
| 1270 | # CONFIG_DEBUG_STACK_USAGE is not set | 1384 | # CONFIG_DEBUG_STACK_USAGE is not set |
| 1271 | # CONFIG_DEBUG_PAGEALLOC is not set | 1385 | # CONFIG_DEBUG_PAGEALLOC is not set |
| 1272 | # CONFIG_CODE_PATCHING_SELFTEST is not set | 1386 | # CONFIG_CODE_PATCHING_SELFTEST is not set |
| 1273 | # CONFIG_FTR_FIXUP_SELFTEST is not set | 1387 | # CONFIG_FTR_FIXUP_SELFTEST is not set |
| 1388 | # CONFIG_MSI_BITMAP_SELFTEST is not set | ||
| 1274 | # CONFIG_XMON is not set | 1389 | # CONFIG_XMON is not set |
| 1275 | CONFIG_IRQSTACKS=y | 1390 | CONFIG_IRQSTACKS=y |
| 1276 | # CONFIG_VIRQ_DEBUG is not set | 1391 | # CONFIG_VIRQ_DEBUG is not set |
| @@ -1282,16 +1397,26 @@ CONFIG_IRQSTACKS=y | |||
| 1282 | # | 1397 | # |
| 1283 | # CONFIG_KEYS is not set | 1398 | # CONFIG_KEYS is not set |
| 1284 | # CONFIG_SECURITY is not set | 1399 | # CONFIG_SECURITY is not set |
| 1400 | # CONFIG_SECURITYFS is not set | ||
| 1285 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set | 1401 | # CONFIG_SECURITY_FILE_CAPABILITIES is not set |
| 1286 | CONFIG_CRYPTO=y | 1402 | CONFIG_CRYPTO=y |
| 1287 | 1403 | ||
| 1288 | # | 1404 | # |
| 1289 | # Crypto core or helper | 1405 | # Crypto core or helper |
| 1290 | # | 1406 | # |
| 1407 | # CONFIG_CRYPTO_FIPS is not set | ||
| 1291 | CONFIG_CRYPTO_ALGAPI=y | 1408 | CONFIG_CRYPTO_ALGAPI=y |
| 1409 | CONFIG_CRYPTO_ALGAPI2=y | ||
| 1292 | CONFIG_CRYPTO_AEAD=m | 1410 | CONFIG_CRYPTO_AEAD=m |
| 1411 | CONFIG_CRYPTO_AEAD2=y | ||
| 1293 | CONFIG_CRYPTO_BLKCIPHER=y | 1412 | CONFIG_CRYPTO_BLKCIPHER=y |
| 1413 | CONFIG_CRYPTO_BLKCIPHER2=y | ||
| 1414 | CONFIG_CRYPTO_HASH=y | ||
| 1415 | CONFIG_CRYPTO_HASH2=y | ||
| 1416 | CONFIG_CRYPTO_RNG=m | ||
| 1417 | CONFIG_CRYPTO_RNG2=y | ||
| 1294 | CONFIG_CRYPTO_MANAGER=y | 1418 | CONFIG_CRYPTO_MANAGER=y |
| 1419 | CONFIG_CRYPTO_MANAGER2=y | ||
| 1295 | CONFIG_CRYPTO_GF128MUL=m | 1420 | CONFIG_CRYPTO_GF128MUL=m |
| 1296 | # CONFIG_CRYPTO_NULL is not set | 1421 | # CONFIG_CRYPTO_NULL is not set |
| 1297 | # CONFIG_CRYPTO_CRYPTD is not set | 1422 | # CONFIG_CRYPTO_CRYPTD is not set |
| @@ -1363,6 +1488,11 @@ CONFIG_CRYPTO_SALSA20=m | |||
| 1363 | # | 1488 | # |
| 1364 | # CONFIG_CRYPTO_DEFLATE is not set | 1489 | # CONFIG_CRYPTO_DEFLATE is not set |
| 1365 | CONFIG_CRYPTO_LZO=m | 1490 | CONFIG_CRYPTO_LZO=m |
| 1491 | |||
| 1492 | # | ||
| 1493 | # Random Number Generation | ||
| 1494 | # | ||
| 1495 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
| 1366 | CONFIG_CRYPTO_HW=y | 1496 | CONFIG_CRYPTO_HW=y |
| 1367 | # CONFIG_PPC_CLOCK is not set | 1497 | # CONFIG_PPC_CLOCK is not set |
| 1368 | # CONFIG_VIRTUALIZATION is not set | 1498 | # CONFIG_VIRTUALIZATION is not set |
diff --git a/arch/powerpc/configs/storcenter_defconfig b/arch/powerpc/configs/storcenter_defconfig index 86512c8790d1..94903465ea12 100644 --- a/arch/powerpc/configs/storcenter_defconfig +++ b/arch/powerpc/configs/storcenter_defconfig | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | # | 1 | # |
| 2 | # Automatically generated make config: don't edit | 2 | # Automatically generated make config: don't edit |
| 3 | # Linux kernel version: 2.6.29-rc2 | 3 | # Linux kernel version: 2.6.29-rc6 |
| 4 | # Mon Jan 26 15:35:46 2009 | 4 | # Fri Mar 6 00:09:08 2009 |
| 5 | # | 5 | # |
| 6 | # CONFIG_PPC64 is not set | 6 | # CONFIG_PPC64 is not set |
| 7 | 7 | ||
| @@ -71,6 +71,15 @@ CONFIG_SYSVIPC_SYSCTL=y | |||
| 71 | # CONFIG_BSD_PROCESS_ACCT is not set | 71 | # CONFIG_BSD_PROCESS_ACCT is not set |
| 72 | # CONFIG_TASKSTATS is not set | 72 | # CONFIG_TASKSTATS is not set |
| 73 | # CONFIG_AUDIT is not set | 73 | # CONFIG_AUDIT is not set |
| 74 | |||
| 75 | # | ||
| 76 | # RCU Subsystem | ||
| 77 | # | ||
| 78 | CONFIG_CLASSIC_RCU=y | ||
| 79 | # CONFIG_TREE_RCU is not set | ||
| 80 | # CONFIG_PREEMPT_RCU is not set | ||
| 81 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 82 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 74 | # CONFIG_IKCONFIG is not set | 83 | # CONFIG_IKCONFIG is not set |
| 75 | CONFIG_LOG_BUF_SHIFT=14 | 84 | CONFIG_LOG_BUF_SHIFT=14 |
| 76 | CONFIG_GROUP_SCHED=y | 85 | CONFIG_GROUP_SCHED=y |
| @@ -144,11 +153,6 @@ CONFIG_IOSCHED_CFQ=y | |||
| 144 | CONFIG_DEFAULT_CFQ=y | 153 | CONFIG_DEFAULT_CFQ=y |
| 145 | # CONFIG_DEFAULT_NOOP is not set | 154 | # CONFIG_DEFAULT_NOOP is not set |
| 146 | CONFIG_DEFAULT_IOSCHED="cfq" | 155 | CONFIG_DEFAULT_IOSCHED="cfq" |
| 147 | CONFIG_CLASSIC_RCU=y | ||
| 148 | # CONFIG_TREE_RCU is not set | ||
| 149 | # CONFIG_PREEMPT_RCU is not set | ||
| 150 | # CONFIG_TREE_RCU_TRACE is not set | ||
| 151 | # CONFIG_PREEMPT_RCU_TRACE is not set | ||
| 152 | # CONFIG_FREEZER is not set | 156 | # CONFIG_FREEZER is not set |
| 153 | 157 | ||
| 154 | # | 158 | # |
| @@ -377,8 +381,8 @@ CONFIG_MTD=y | |||
| 377 | CONFIG_MTD_PARTITIONS=y | 381 | CONFIG_MTD_PARTITIONS=y |
| 378 | # CONFIG_MTD_TESTS is not set | 382 | # CONFIG_MTD_TESTS is not set |
| 379 | # CONFIG_MTD_REDBOOT_PARTS is not set | 383 | # CONFIG_MTD_REDBOOT_PARTS is not set |
| 380 | # CONFIG_MTD_CMDLINE_PARTS is not set | 384 | CONFIG_MTD_CMDLINE_PARTS=y |
| 381 | # CONFIG_MTD_OF_PARTS is not set | 385 | CONFIG_MTD_OF_PARTS=y |
| 382 | # CONFIG_MTD_AR7_PARTS is not set | 386 | # CONFIG_MTD_AR7_PARTS is not set |
| 383 | 387 | ||
| 384 | # | 388 | # |
| @@ -452,7 +456,6 @@ CONFIG_MTD_PHYSMAP=y | |||
| 452 | # LPDDR flash memory drivers | 456 | # LPDDR flash memory drivers |
| 453 | # | 457 | # |
| 454 | # CONFIG_MTD_LPDDR is not set | 458 | # CONFIG_MTD_LPDDR is not set |
| 455 | # CONFIG_MTD_QINFO_PROBE is not set | ||
| 456 | 459 | ||
| 457 | # | 460 | # |
| 458 | # UBI - Unsorted block images | 461 | # UBI - Unsorted block images |
| @@ -478,13 +481,19 @@ CONFIG_BLK_DEV=y | |||
| 478 | # CONFIG_BLK_DEV_HD is not set | 481 | # CONFIG_BLK_DEV_HD is not set |
| 479 | CONFIG_MISC_DEVICES=y | 482 | CONFIG_MISC_DEVICES=y |
| 480 | # CONFIG_PHANTOM is not set | 483 | # CONFIG_PHANTOM is not set |
| 481 | # CONFIG_EEPROM_93CX6 is not set | ||
| 482 | # CONFIG_SGI_IOC4 is not set | 484 | # CONFIG_SGI_IOC4 is not set |
| 483 | # CONFIG_TIFM_CORE is not set | 485 | # CONFIG_TIFM_CORE is not set |
| 484 | # CONFIG_ICS932S401 is not set | 486 | # CONFIG_ICS932S401 is not set |
| 485 | # CONFIG_ENCLOSURE_SERVICES is not set | 487 | # CONFIG_ENCLOSURE_SERVICES is not set |
| 486 | # CONFIG_HP_ILO is not set | 488 | # CONFIG_HP_ILO is not set |
| 487 | # CONFIG_C2PORT is not set | 489 | # CONFIG_C2PORT is not set |
| 490 | |||
| 491 | # | ||
| 492 | # EEPROM support | ||
| 493 | # | ||
| 494 | # CONFIG_EEPROM_AT24 is not set | ||
| 495 | # CONFIG_EEPROM_LEGACY is not set | ||
| 496 | # CONFIG_EEPROM_93CX6 is not set | ||
| 488 | CONFIG_HAVE_IDE=y | 497 | CONFIG_HAVE_IDE=y |
| 489 | CONFIG_IDE=y | 498 | CONFIG_IDE=y |
| 490 | 499 | ||
| @@ -677,6 +686,7 @@ CONFIG_R8169=y | |||
| 677 | # CONFIG_QLA3XXX is not set | 686 | # CONFIG_QLA3XXX is not set |
| 678 | # CONFIG_ATL1 is not set | 687 | # CONFIG_ATL1 is not set |
| 679 | # CONFIG_ATL1E is not set | 688 | # CONFIG_ATL1E is not set |
| 689 | # CONFIG_ATL1C is not set | ||
| 680 | # CONFIG_JME is not set | 690 | # CONFIG_JME is not set |
| 681 | # CONFIG_NETDEV_10000 is not set | 691 | # CONFIG_NETDEV_10000 is not set |
| 682 | # CONFIG_TR is not set | 692 | # CONFIG_TR is not set |
| @@ -818,8 +828,6 @@ CONFIG_I2C_MPC=y | |||
| 818 | # Miscellaneous I2C Chip support | 828 | # Miscellaneous I2C Chip support |
| 819 | # | 829 | # |
| 820 | # CONFIG_DS1682 is not set | 830 | # CONFIG_DS1682 is not set |
| 821 | # CONFIG_EEPROM_AT24 is not set | ||
| 822 | # CONFIG_EEPROM_LEGACY is not set | ||
| 823 | # CONFIG_SENSORS_PCF8574 is not set | 831 | # CONFIG_SENSORS_PCF8574 is not set |
| 824 | # CONFIG_PCF8575 is not set | 832 | # CONFIG_PCF8575 is not set |
| 825 | # CONFIG_SENSORS_PCA9539 is not set | 833 | # CONFIG_SENSORS_PCA9539 is not set |
| @@ -1159,6 +1167,7 @@ CONFIG_JFFS2_RTIME=y | |||
| 1159 | # CONFIG_SYSV_FS is not set | 1167 | # CONFIG_SYSV_FS is not set |
| 1160 | # CONFIG_UFS_FS is not set | 1168 | # CONFIG_UFS_FS is not set |
| 1161 | # CONFIG_NETWORK_FILESYSTEMS is not set | 1169 | # CONFIG_NETWORK_FILESYSTEMS is not set |
| 1170 | CONFIG_EXPORTFS=m | ||
| 1162 | 1171 | ||
| 1163 | # | 1172 | # |
| 1164 | # Partition Types | 1173 | # Partition Types |
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 4911104791c3..21172badd708 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h | |||
| @@ -241,9 +241,11 @@ extern const char *powerpc_base_platform; | |||
| 241 | /* We need to mark all pages as being coherent if we're SMP or we have a | 241 | /* We need to mark all pages as being coherent if we're SMP or we have a |
| 242 | * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II | 242 | * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II |
| 243 | * require it for PCI "streaming/prefetch" to work properly. | 243 | * require it for PCI "streaming/prefetch" to work properly. |
| 244 | * This is also required by 52xx family. | ||
| 244 | */ | 245 | */ |
| 245 | #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ | 246 | #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \ |
| 246 | || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) | 247 | || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \ |
| 248 | || defined(CONFIG_PPC_MPC52xx) | ||
| 247 | #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT | 249 | #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT |
| 248 | #else | 250 | #else |
| 249 | #define CPU_FTR_COMMON 0 | 251 | #define CPU_FTR_COMMON 0 |
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index a1c4cfd25ded..d794a637e421 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S | |||
| @@ -511,8 +511,11 @@ InstructionTLBMiss: | |||
| 511 | and r1,r1,r2 /* writable if _RW and _DIRTY */ | 511 | and r1,r1,r2 /* writable if _RW and _DIRTY */ |
| 512 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ | 512 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ |
| 513 | rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ | 513 | rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ |
| 514 | ori r1,r1,0xe14 /* clear out reserved bits and M */ | 514 | ori r1,r1,0xe04 /* clear out reserved bits */ |
| 515 | andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ | 515 | andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ |
| 516 | BEGIN_FTR_SECTION | ||
| 517 | rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */ | ||
| 518 | END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) | ||
| 516 | mtspr SPRN_RPA,r1 | 519 | mtspr SPRN_RPA,r1 |
| 517 | mfspr r3,SPRN_IMISS | 520 | mfspr r3,SPRN_IMISS |
| 518 | tlbli r3 | 521 | tlbli r3 |
| @@ -585,8 +588,11 @@ DataLoadTLBMiss: | |||
| 585 | and r1,r1,r2 /* writable if _RW and _DIRTY */ | 588 | and r1,r1,r2 /* writable if _RW and _DIRTY */ |
| 586 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ | 589 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ |
| 587 | rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ | 590 | rlwimi r3,r3,32-1,31,31 /* _PAGE_USER -> PP lsb */ |
| 588 | ori r1,r1,0xe14 /* clear out reserved bits and M */ | 591 | ori r1,r1,0xe04 /* clear out reserved bits */ |
| 589 | andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ | 592 | andc r1,r3,r1 /* PP = user? (rw&dirty? 2: 3): 0 */ |
| 593 | BEGIN_FTR_SECTION | ||
| 594 | rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */ | ||
| 595 | END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) | ||
| 590 | mtspr SPRN_RPA,r1 | 596 | mtspr SPRN_RPA,r1 |
| 591 | mfspr r3,SPRN_DMISS | 597 | mfspr r3,SPRN_DMISS |
| 592 | tlbld r3 | 598 | tlbld r3 |
| @@ -653,8 +659,11 @@ DataStoreTLBMiss: | |||
| 653 | stw r3,0(r2) /* update PTE (accessed/dirty bits) */ | 659 | stw r3,0(r2) /* update PTE (accessed/dirty bits) */ |
| 654 | /* Convert linux-style PTE to low word of PPC-style PTE */ | 660 | /* Convert linux-style PTE to low word of PPC-style PTE */ |
| 655 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ | 661 | rlwimi r3,r3,32-1,30,30 /* _PAGE_USER -> PP msb */ |
| 656 | li r1,0xe15 /* clear out reserved bits and M */ | 662 | li r1,0xe05 /* clear out reserved bits & PP lsb */ |
| 657 | andc r1,r3,r1 /* PP = user? 2: 0 */ | 663 | andc r1,r3,r1 /* PP = user? 2: 0 */ |
| 664 | BEGIN_FTR_SECTION | ||
| 665 | rlwinm r1,r1,0,~_PAGE_COHERENT /* clear M (coherence not required) */ | ||
| 666 | END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT) | ||
| 658 | mtspr SPRN_RPA,r1 | 667 | mtspr SPRN_RPA,r1 |
| 659 | mfspr r3,SPRN_DMISS | 668 | mfspr r3,SPRN_DMISS |
| 660 | tlbld r3 | 669 | tlbld r3 |
diff --git a/arch/powerpc/platforms/embedded6xx/linkstation.c b/arch/powerpc/platforms/embedded6xx/linkstation.c index 2ca7be65c2d2..244f997de791 100644 --- a/arch/powerpc/platforms/embedded6xx/linkstation.c +++ b/arch/powerpc/platforms/embedded6xx/linkstation.c | |||
| @@ -12,7 +12,6 @@ | |||
| 12 | 12 | ||
| 13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
| 14 | #include <linux/initrd.h> | 14 | #include <linux/initrd.h> |
| 15 | #include <linux/mtd/physmap.h> | ||
| 16 | #include <linux/of_platform.h> | 15 | #include <linux/of_platform.h> |
| 17 | 16 | ||
| 18 | #include <asm/time.h> | 17 | #include <asm/time.h> |
| @@ -22,39 +21,6 @@ | |||
| 22 | 21 | ||
| 23 | #include "mpc10x.h" | 22 | #include "mpc10x.h" |
| 24 | 23 | ||
| 25 | static struct mtd_partition linkstation_physmap_partitions[] = { | ||
| 26 | { | ||
| 27 | .name = "mtd_firmimg", | ||
| 28 | .offset = 0x000000, | ||
| 29 | .size = 0x300000, | ||
| 30 | }, | ||
| 31 | { | ||
| 32 | .name = "mtd_bootcode", | ||
| 33 | .offset = 0x300000, | ||
| 34 | .size = 0x070000, | ||
| 35 | }, | ||
| 36 | { | ||
| 37 | .name = "mtd_status", | ||
| 38 | .offset = 0x370000, | ||
| 39 | .size = 0x010000, | ||
| 40 | }, | ||
| 41 | { | ||
| 42 | .name = "mtd_conf", | ||
| 43 | .offset = 0x380000, | ||
| 44 | .size = 0x080000, | ||
| 45 | }, | ||
| 46 | { | ||
| 47 | .name = "mtd_allflash", | ||
| 48 | .offset = 0x000000, | ||
| 49 | .size = 0x400000, | ||
| 50 | }, | ||
| 51 | { | ||
| 52 | .name = "mtd_data", | ||
| 53 | .offset = 0x310000, | ||
| 54 | .size = 0x0f0000, | ||
| 55 | }, | ||
| 56 | }; | ||
| 57 | |||
| 58 | static __initdata struct of_device_id of_bus_ids[] = { | 24 | static __initdata struct of_device_id of_bus_ids[] = { |
| 59 | { .type = "soc", }, | 25 | { .type = "soc", }, |
| 60 | { .compatible = "simple-bus", }, | 26 | { .compatible = "simple-bus", }, |
| @@ -99,10 +65,6 @@ static int __init linkstation_add_bridge(struct device_node *dev) | |||
| 99 | static void __init linkstation_setup_arch(void) | 65 | static void __init linkstation_setup_arch(void) |
| 100 | { | 66 | { |
| 101 | struct device_node *np; | 67 | struct device_node *np; |
| 102 | #ifdef CONFIG_MTD_PHYSMAP | ||
| 103 | physmap_set_partitions(linkstation_physmap_partitions, | ||
| 104 | ARRAY_SIZE(linkstation_physmap_partitions)); | ||
| 105 | #endif | ||
| 106 | 68 | ||
| 107 | /* Lookup PCI host bridges */ | 69 | /* Lookup PCI host bridges */ |
| 108 | for_each_compatible_node(np, "pci", "mpc10x-pci") | 70 | for_each_compatible_node(np, "pci", "mpc10x-pci") |
diff --git a/arch/powerpc/platforms/embedded6xx/storcenter.c b/arch/powerpc/platforms/embedded6xx/storcenter.c index 8864e4884980..613070e9ddbe 100644 --- a/arch/powerpc/platforms/embedded6xx/storcenter.c +++ b/arch/powerpc/platforms/embedded6xx/storcenter.c | |||
| @@ -14,7 +14,6 @@ | |||
| 14 | #include <linux/kernel.h> | 14 | #include <linux/kernel.h> |
| 15 | #include <linux/pci.h> | 15 | #include <linux/pci.h> |
| 16 | #include <linux/initrd.h> | 16 | #include <linux/initrd.h> |
| 17 | #include <linux/mtd/physmap.h> | ||
| 18 | #include <linux/of_platform.h> | 17 | #include <linux/of_platform.h> |
| 19 | 18 | ||
| 20 | #include <asm/system.h> | 19 | #include <asm/system.h> |
| @@ -26,32 +25,6 @@ | |||
| 26 | #include "mpc10x.h" | 25 | #include "mpc10x.h" |
| 27 | 26 | ||
| 28 | 27 | ||
| 29 | #ifdef CONFIG_MTD_PHYSMAP | ||
| 30 | static struct mtd_partition storcenter_physmap_partitions[] = { | ||
| 31 | { | ||
| 32 | .name = "kernel", | ||
| 33 | .offset = 0x000000, | ||
| 34 | .size = 0x170000, | ||
| 35 | }, | ||
| 36 | { | ||
| 37 | .name = "rootfs", | ||
| 38 | .offset = 0x170000, | ||
| 39 | .size = 0x590000, | ||
| 40 | }, | ||
| 41 | { | ||
| 42 | .name = "uboot", | ||
| 43 | .offset = 0x700000, | ||
| 44 | .size = 0x040000, | ||
| 45 | }, | ||
| 46 | { | ||
| 47 | .name = "config", | ||
| 48 | .offset = 0x740000, | ||
| 49 | .size = 0x0c0000, | ||
| 50 | }, | ||
| 51 | }; | ||
| 52 | #endif | ||
| 53 | |||
| 54 | |||
| 55 | static __initdata struct of_device_id storcenter_of_bus[] = { | 28 | static __initdata struct of_device_id storcenter_of_bus[] = { |
| 56 | { .name = "soc", }, | 29 | { .name = "soc", }, |
| 57 | {}, | 30 | {}, |
| @@ -96,11 +69,6 @@ static void __init storcenter_setup_arch(void) | |||
| 96 | { | 69 | { |
| 97 | struct device_node *np; | 70 | struct device_node *np; |
| 98 | 71 | ||
| 99 | #ifdef CONFIG_MTD_PHYSMAP | ||
| 100 | physmap_set_partitions(storcenter_physmap_partitions, | ||
| 101 | ARRAY_SIZE(storcenter_physmap_partitions)); | ||
| 102 | #endif | ||
| 103 | |||
| 104 | /* Lookup PCI host bridges */ | 72 | /* Lookup PCI host bridges */ |
| 105 | for_each_compatible_node(np, "pci", "mpc10x-pci") | 73 | for_each_compatible_node(np, "pci", "mpc10x-pci") |
| 106 | storcenter_add_bridge(np); | 74 | storcenter_add_bridge(np); |
diff --git a/arch/powerpc/platforms/ps3/Kconfig b/arch/powerpc/platforms/ps3/Kconfig index 920cf7a454b1..740ef56a1550 100644 --- a/arch/powerpc/platforms/ps3/Kconfig +++ b/arch/powerpc/platforms/ps3/Kconfig | |||
| @@ -128,6 +128,13 @@ config PS3_FLASH | |||
| 128 | be disabled on the kernel command line using "ps3flash=off", to | 128 | be disabled on the kernel command line using "ps3flash=off", to |
| 129 | not allocate this fixed buffer. | 129 | not allocate this fixed buffer. |
| 130 | 130 | ||
| 131 | config PS3_VRAM | ||
| 132 | tristate "PS3 Video RAM Storage Driver" | ||
| 133 | depends on FB_PS3=y && BLOCK && m | ||
| 134 | help | ||
| 135 | This driver allows you to use excess PS3 video RAM as volatile | ||
| 136 | storage or system swap. | ||
| 137 | |||
| 131 | config PS3_LPM | 138 | config PS3_LPM |
| 132 | tristate "PS3 Logical Performance Monitor support" | 139 | tristate "PS3 Logical Performance Monitor support" |
| 133 | depends on PPC_PS3 | 140 | depends on PPC_PS3 |
diff --git a/arch/s390/include/asm/mman.h b/arch/s390/include/asm/mman.h index 7839767d837e..da01432e8f44 100644 --- a/arch/s390/include/asm/mman.h +++ b/arch/s390/include/asm/mman.h | |||
| @@ -22,4 +22,9 @@ | |||
| 22 | #define MCL_CURRENT 1 /* lock all current mappings */ | 22 | #define MCL_CURRENT 1 /* lock all current mappings */ |
| 23 | #define MCL_FUTURE 2 /* lock all future mappings */ | 23 | #define MCL_FUTURE 2 /* lock all future mappings */ |
| 24 | 24 | ||
| 25 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) && defined(CONFIG_64BIT) | ||
| 26 | int s390_mmap_check(unsigned long addr, unsigned long len); | ||
| 27 | #define arch_mmap_check(addr,len,flags) s390_mmap_check(addr,len) | ||
| 28 | #endif | ||
| 29 | |||
| 25 | #endif /* __S390_MMAN_H__ */ | 30 | #endif /* __S390_MMAN_H__ */ |
diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h index 066b99502e09..db4523fe38ac 100644 --- a/arch/s390/include/asm/processor.h +++ b/arch/s390/include/asm/processor.h | |||
| @@ -61,7 +61,7 @@ extern void print_cpu_info(struct cpuinfo_S390 *); | |||
| 61 | extern int get_cpu_capability(unsigned int *); | 61 | extern int get_cpu_capability(unsigned int *); |
| 62 | 62 | ||
| 63 | /* | 63 | /* |
| 64 | * User space process size: 2GB for 31 bit, 4TB for 64 bit. | 64 | * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit. |
| 65 | */ | 65 | */ |
| 66 | #ifndef __s390x__ | 66 | #ifndef __s390x__ |
| 67 | 67 | ||
| @@ -70,8 +70,7 @@ extern int get_cpu_capability(unsigned int *); | |||
| 70 | 70 | ||
| 71 | #else /* __s390x__ */ | 71 | #else /* __s390x__ */ |
| 72 | 72 | ||
| 73 | #define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk,TIF_31BIT) ? \ | 73 | #define TASK_SIZE_OF(tsk) ((tsk)->mm->context.asce_limit) |
| 74 | (1UL << 31) : (1UL << 53)) | ||
| 75 | #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ | 74 | #define TASK_UNMAPPED_BASE (test_thread_flag(TIF_31BIT) ? \ |
| 76 | (1UL << 30) : (1UL << 41)) | 75 | (1UL << 30) : (1UL << 41)) |
| 77 | #define TASK_SIZE TASK_SIZE_OF(current) | 76 | #define TASK_SIZE TASK_SIZE_OF(current) |
diff --git a/arch/s390/include/asm/topology.h b/arch/s390/include/asm/topology.h index c93eb50e1d09..c979c3b56ab0 100644 --- a/arch/s390/include/asm/topology.h +++ b/arch/s390/include/asm/topology.h | |||
| @@ -30,6 +30,8 @@ static inline void s390_init_cpu_topology(void) | |||
| 30 | }; | 30 | }; |
| 31 | #endif | 31 | #endif |
| 32 | 32 | ||
| 33 | #define SD_MC_INIT SD_CPU_INIT | ||
| 34 | |||
| 33 | #include <asm-generic/topology.h> | 35 | #include <asm-generic/topology.h> |
| 34 | 36 | ||
| 35 | #endif /* _ASM_S390_TOPOLOGY_H */ | 37 | #endif /* _ASM_S390_TOPOLOGY_H */ |
diff --git a/arch/s390/kernel/mcount.S b/arch/s390/kernel/mcount.S index 397d131a345f..80641224a095 100644 --- a/arch/s390/kernel/mcount.S +++ b/arch/s390/kernel/mcount.S | |||
| @@ -5,6 +5,8 @@ | |||
| 5 | * | 5 | * |
| 6 | */ | 6 | */ |
| 7 | 7 | ||
| 8 | #include <asm/asm-offsets.h> | ||
| 9 | |||
| 8 | #ifndef CONFIG_64BIT | 10 | #ifndef CONFIG_64BIT |
| 9 | .globl _mcount | 11 | .globl _mcount |
| 10 | _mcount: | 12 | _mcount: |
| @@ -14,7 +16,7 @@ _mcount: | |||
| 14 | ahi %r15,-96 | 16 | ahi %r15,-96 |
| 15 | l %r3,100(%r15) | 17 | l %r3,100(%r15) |
| 16 | la %r2,0(%r14) | 18 | la %r2,0(%r14) |
| 17 | st %r1,0(%r15) | 19 | st %r1,__SF_BACKCHAIN(%r15) |
| 18 | la %r3,0(%r3) | 20 | la %r3,0(%r3) |
| 19 | bras %r14,0f | 21 | bras %r14,0f |
| 20 | .long ftrace_trace_function | 22 | .long ftrace_trace_function |
| @@ -38,7 +40,7 @@ _mcount: | |||
| 38 | stg %r14,112(%r15) | 40 | stg %r14,112(%r15) |
| 39 | lgr %r1,%r15 | 41 | lgr %r1,%r15 |
| 40 | aghi %r15,-160 | 42 | aghi %r15,-160 |
| 41 | stg %r1,0(%r15) | 43 | stg %r1,__SF_BACKCHAIN(%r15) |
| 42 | lgr %r2,%r14 | 44 | lgr %r2,%r14 |
| 43 | lg %r3,168(%r15) | 45 | lg %r3,168(%r15) |
| 44 | larl %r14,ftrace_trace_function | 46 | larl %r14,ftrace_trace_function |
diff --git a/arch/s390/lib/div64.c b/arch/s390/lib/div64.c index a5f8300bf3ee..d9e62c0b576a 100644 --- a/arch/s390/lib/div64.c +++ b/arch/s390/lib/div64.c | |||
| @@ -61,7 +61,7 @@ static uint32_t __div64_31(uint64_t *n, uint32_t base) | |||
| 61 | " clr %0,%3\n" | 61 | " clr %0,%3\n" |
| 62 | " jl 0f\n" | 62 | " jl 0f\n" |
| 63 | " slr %0,%3\n" | 63 | " slr %0,%3\n" |
| 64 | " alr %1,%2\n" | 64 | " ahi %1,1\n" |
| 65 | "0:\n" | 65 | "0:\n" |
| 66 | : "+d" (reg2), "+d" (reg3), "=d" (tmp) | 66 | : "+d" (reg2), "+d" (reg3), "=d" (tmp) |
| 67 | : "d" (base), "2" (1UL) : "cc" ); | 67 | : "d" (base), "2" (1UL) : "cc" ); |
diff --git a/arch/s390/lib/uaccess_pt.c b/arch/s390/lib/uaccess_pt.c index d66215b0fde9..b0b84c35b0ad 100644 --- a/arch/s390/lib/uaccess_pt.c +++ b/arch/s390/lib/uaccess_pt.c | |||
| @@ -119,8 +119,6 @@ retry: | |||
| 119 | goto fault; | 119 | goto fault; |
| 120 | 120 | ||
| 121 | pfn = pte_pfn(*pte); | 121 | pfn = pte_pfn(*pte); |
| 122 | if (!pfn_valid(pfn)) | ||
| 123 | goto out; | ||
| 124 | 122 | ||
| 125 | offset = uaddr & (PAGE_SIZE - 1); | 123 | offset = uaddr & (PAGE_SIZE - 1); |
| 126 | size = min(n - done, PAGE_SIZE - offset); | 124 | size = min(n - done, PAGE_SIZE - offset); |
| @@ -135,7 +133,6 @@ retry: | |||
| 135 | done += size; | 133 | done += size; |
| 136 | uaddr += size; | 134 | uaddr += size; |
| 137 | } while (done < n); | 135 | } while (done < n); |
| 138 | out: | ||
| 139 | spin_unlock(&mm->page_table_lock); | 136 | spin_unlock(&mm->page_table_lock); |
| 140 | return n - done; | 137 | return n - done; |
| 141 | fault: | 138 | fault: |
| @@ -163,9 +160,6 @@ retry: | |||
| 163 | goto fault; | 160 | goto fault; |
| 164 | 161 | ||
| 165 | pfn = pte_pfn(*pte); | 162 | pfn = pte_pfn(*pte); |
| 166 | if (!pfn_valid(pfn)) | ||
| 167 | goto out; | ||
| 168 | |||
| 169 | ret = (pfn << PAGE_SHIFT) + (uaddr & (PAGE_SIZE - 1)); | 163 | ret = (pfn << PAGE_SHIFT) + (uaddr & (PAGE_SIZE - 1)); |
| 170 | out: | 164 | out: |
| 171 | return ret; | 165 | return ret; |
| @@ -244,11 +238,6 @@ retry: | |||
| 244 | goto fault; | 238 | goto fault; |
| 245 | 239 | ||
| 246 | pfn = pte_pfn(*pte); | 240 | pfn = pte_pfn(*pte); |
| 247 | if (!pfn_valid(pfn)) { | ||
| 248 | done = -1; | ||
| 249 | goto out; | ||
| 250 | } | ||
| 251 | |||
| 252 | offset = uaddr & (PAGE_SIZE-1); | 241 | offset = uaddr & (PAGE_SIZE-1); |
| 253 | addr = (char *)(pfn << PAGE_SHIFT) + offset; | 242 | addr = (char *)(pfn << PAGE_SHIFT) + offset; |
| 254 | len = min(count - done, PAGE_SIZE - offset); | 243 | len = min(count - done, PAGE_SIZE - offset); |
| @@ -256,7 +245,6 @@ retry: | |||
| 256 | done += len_str; | 245 | done += len_str; |
| 257 | uaddr += len_str; | 246 | uaddr += len_str; |
| 258 | } while ((len_str == len) && (done < count)); | 247 | } while ((len_str == len) && (done < count)); |
| 259 | out: | ||
| 260 | spin_unlock(&mm->page_table_lock); | 248 | spin_unlock(&mm->page_table_lock); |
| 261 | return done + 1; | 249 | return done + 1; |
| 262 | fault: | 250 | fault: |
| @@ -325,12 +313,7 @@ retry: | |||
| 325 | } | 313 | } |
| 326 | 314 | ||
| 327 | pfn_from = pte_pfn(*pte_from); | 315 | pfn_from = pte_pfn(*pte_from); |
| 328 | if (!pfn_valid(pfn_from)) | ||
| 329 | goto out; | ||
| 330 | pfn_to = pte_pfn(*pte_to); | 316 | pfn_to = pte_pfn(*pte_to); |
| 331 | if (!pfn_valid(pfn_to)) | ||
| 332 | goto out; | ||
| 333 | |||
| 334 | offset_from = uaddr_from & (PAGE_SIZE-1); | 317 | offset_from = uaddr_from & (PAGE_SIZE-1); |
| 335 | offset_to = uaddr_from & (PAGE_SIZE-1); | 318 | offset_to = uaddr_from & (PAGE_SIZE-1); |
| 336 | offset_max = max(offset_from, offset_to); | 319 | offset_max = max(offset_from, offset_to); |
| @@ -342,7 +325,6 @@ retry: | |||
| 342 | uaddr_from += size; | 325 | uaddr_from += size; |
| 343 | uaddr_to += size; | 326 | uaddr_to += size; |
| 344 | } while (done < n); | 327 | } while (done < n); |
| 345 | out: | ||
| 346 | spin_unlock(&mm->page_table_lock); | 328 | spin_unlock(&mm->page_table_lock); |
| 347 | return n - done; | 329 | return n - done; |
| 348 | fault: | 330 | fault: |
diff --git a/arch/s390/mm/mmap.c b/arch/s390/mm/mmap.c index 5932a824547a..e008d236cc15 100644 --- a/arch/s390/mm/mmap.c +++ b/arch/s390/mm/mmap.c | |||
| @@ -35,7 +35,7 @@ | |||
| 35 | * Leave an at least ~128 MB hole. | 35 | * Leave an at least ~128 MB hole. |
| 36 | */ | 36 | */ |
| 37 | #define MIN_GAP (128*1024*1024) | 37 | #define MIN_GAP (128*1024*1024) |
| 38 | #define MAX_GAP (TASK_SIZE/6*5) | 38 | #define MAX_GAP (STACK_TOP/6*5) |
| 39 | 39 | ||
| 40 | static inline unsigned long mmap_base(void) | 40 | static inline unsigned long mmap_base(void) |
| 41 | { | 41 | { |
| @@ -46,7 +46,7 @@ static inline unsigned long mmap_base(void) | |||
| 46 | else if (gap > MAX_GAP) | 46 | else if (gap > MAX_GAP) |
| 47 | gap = MAX_GAP; | 47 | gap = MAX_GAP; |
| 48 | 48 | ||
| 49 | return TASK_SIZE - (gap & PAGE_MASK); | 49 | return STACK_TOP - (gap & PAGE_MASK); |
| 50 | } | 50 | } |
| 51 | 51 | ||
| 52 | static inline int mmap_is_legacy(void) | 52 | static inline int mmap_is_legacy(void) |
| @@ -89,42 +89,58 @@ EXPORT_SYMBOL_GPL(arch_pick_mmap_layout); | |||
| 89 | 89 | ||
| 90 | #else | 90 | #else |
| 91 | 91 | ||
| 92 | int s390_mmap_check(unsigned long addr, unsigned long len) | ||
| 93 | { | ||
| 94 | if (!test_thread_flag(TIF_31BIT) && | ||
| 95 | len >= TASK_SIZE && TASK_SIZE < (1UL << 53)) | ||
| 96 | return crst_table_upgrade(current->mm, 1UL << 53); | ||
| 97 | return 0; | ||
| 98 | } | ||
| 99 | |||
| 92 | static unsigned long | 100 | static unsigned long |
| 93 | s390_get_unmapped_area(struct file *filp, unsigned long addr, | 101 | s390_get_unmapped_area(struct file *filp, unsigned long addr, |
| 94 | unsigned long len, unsigned long pgoff, unsigned long flags) | 102 | unsigned long len, unsigned long pgoff, unsigned long flags) |
| 95 | { | 103 | { |
| 96 | struct mm_struct *mm = current->mm; | 104 | struct mm_struct *mm = current->mm; |
| 105 | unsigned long area; | ||
| 97 | int rc; | 106 | int rc; |
| 98 | 107 | ||
| 99 | addr = arch_get_unmapped_area(filp, addr, len, pgoff, flags); | 108 | area = arch_get_unmapped_area(filp, addr, len, pgoff, flags); |
| 100 | if (addr & ~PAGE_MASK) | 109 | if (!(area & ~PAGE_MASK)) |
| 101 | return addr; | 110 | return area; |
| 102 | if (unlikely(mm->context.asce_limit < addr + len)) { | 111 | if (area == -ENOMEM && |
| 103 | rc = crst_table_upgrade(mm, addr + len); | 112 | !test_thread_flag(TIF_31BIT) && TASK_SIZE < (1UL << 53)) { |
| 113 | /* Upgrade the page table to 4 levels and retry. */ | ||
| 114 | rc = crst_table_upgrade(mm, 1UL << 53); | ||
| 104 | if (rc) | 115 | if (rc) |
| 105 | return (unsigned long) rc; | 116 | return (unsigned long) rc; |
| 117 | area = arch_get_unmapped_area(filp, addr, len, pgoff, flags); | ||
| 106 | } | 118 | } |
| 107 | return addr; | 119 | return area; |
| 108 | } | 120 | } |
| 109 | 121 | ||
| 110 | static unsigned long | 122 | static unsigned long |
| 111 | s390_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0, | 123 | s390_get_unmapped_area_topdown(struct file *filp, const unsigned long addr, |
| 112 | const unsigned long len, const unsigned long pgoff, | 124 | const unsigned long len, const unsigned long pgoff, |
| 113 | const unsigned long flags) | 125 | const unsigned long flags) |
| 114 | { | 126 | { |
| 115 | struct mm_struct *mm = current->mm; | 127 | struct mm_struct *mm = current->mm; |
| 116 | unsigned long addr = addr0; | 128 | unsigned long area; |
| 117 | int rc; | 129 | int rc; |
| 118 | 130 | ||
| 119 | addr = arch_get_unmapped_area_topdown(filp, addr, len, pgoff, flags); | 131 | area = arch_get_unmapped_area_topdown(filp, addr, len, pgoff, flags); |
| 120 | if (addr & ~PAGE_MASK) | 132 | if (!(area & ~PAGE_MASK)) |
| 121 | return addr; | 133 | return area; |
| 122 | if (unlikely(mm->context.asce_limit < addr + len)) { | 134 | if (area == -ENOMEM && |
| 123 | rc = crst_table_upgrade(mm, addr + len); | 135 | !test_thread_flag(TIF_31BIT) && TASK_SIZE < (1UL << 53)) { |
| 136 | /* Upgrade the page table to 4 levels and retry. */ | ||
| 137 | rc = crst_table_upgrade(mm, 1UL << 53); | ||
| 124 | if (rc) | 138 | if (rc) |
| 125 | return (unsigned long) rc; | 139 | return (unsigned long) rc; |
| 140 | area = arch_get_unmapped_area_topdown(filp, addr, len, | ||
| 141 | pgoff, flags); | ||
| 126 | } | 142 | } |
| 127 | return addr; | 143 | return area; |
| 128 | } | 144 | } |
| 129 | /* | 145 | /* |
| 130 | * This function, called very early during the creation of a new | 146 | * This function, called very early during the creation of a new |
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c index 0767827540b1..6b6ddc4ea02b 100644 --- a/arch/s390/mm/pgtable.c +++ b/arch/s390/mm/pgtable.c | |||
| @@ -117,6 +117,7 @@ repeat: | |||
| 117 | crst_table_init(table, entry); | 117 | crst_table_init(table, entry); |
| 118 | pgd_populate(mm, (pgd_t *) table, (pud_t *) pgd); | 118 | pgd_populate(mm, (pgd_t *) table, (pud_t *) pgd); |
| 119 | mm->pgd = (pgd_t *) table; | 119 | mm->pgd = (pgd_t *) table; |
| 120 | mm->task_size = mm->context.asce_limit; | ||
| 120 | table = NULL; | 121 | table = NULL; |
| 121 | } | 122 | } |
| 122 | spin_unlock(&mm->page_table_lock); | 123 | spin_unlock(&mm->page_table_lock); |
| @@ -154,6 +155,7 @@ void crst_table_downgrade(struct mm_struct *mm, unsigned long limit) | |||
| 154 | BUG(); | 155 | BUG(); |
| 155 | } | 156 | } |
| 156 | mm->pgd = (pgd_t *) (pgd_val(*pgd) & _REGION_ENTRY_ORIGIN); | 157 | mm->pgd = (pgd_t *) (pgd_val(*pgd) & _REGION_ENTRY_ORIGIN); |
| 158 | mm->task_size = mm->context.asce_limit; | ||
| 157 | crst_table_free(mm, (unsigned long *) pgd); | 159 | crst_table_free(mm, (unsigned long *) pgd); |
| 158 | } | 160 | } |
| 159 | update_mm(mm, current); | 161 | update_mm(mm, current); |
diff --git a/arch/sh/boards/board-ap325rxa.c b/arch/sh/boards/board-ap325rxa.c index 72da416f6162..15b6d450fbf0 100644 --- a/arch/sh/boards/board-ap325rxa.c +++ b/arch/sh/boards/board-ap325rxa.c | |||
| @@ -22,6 +22,7 @@ | |||
| 22 | #include <linux/gpio.h> | 22 | #include <linux/gpio.h> |
| 23 | #include <linux/spi/spi.h> | 23 | #include <linux/spi/spi.h> |
| 24 | #include <linux/spi/spi_gpio.h> | 24 | #include <linux/spi/spi_gpio.h> |
| 25 | #include <media/soc_camera.h> | ||
| 25 | #include <media/soc_camera_platform.h> | 26 | #include <media/soc_camera_platform.h> |
| 26 | #include <media/sh_mobile_ceu.h> | 27 | #include <media/sh_mobile_ceu.h> |
| 27 | #include <video/sh_mobile_lcdc.h> | 28 | #include <video/sh_mobile_lcdc.h> |
diff --git a/arch/sparc/include/asm/pil.h b/arch/sparc/include/asm/pil.h index 32a7efe76d00..266937030546 100644 --- a/arch/sparc/include/asm/pil.h +++ b/arch/sparc/include/asm/pil.h | |||
| @@ -24,6 +24,7 @@ | |||
| 24 | #define PIL_DEVICE_IRQ 5 | 24 | #define PIL_DEVICE_IRQ 5 |
| 25 | #define PIL_SMP_CALL_FUNC_SNGL 6 | 25 | #define PIL_SMP_CALL_FUNC_SNGL 6 |
| 26 | #define PIL_DEFERRED_PCR_WORK 7 | 26 | #define PIL_DEFERRED_PCR_WORK 7 |
| 27 | #define PIL_KGDB_CAPTURE 8 | ||
| 27 | #define PIL_NORMAL_MAX 14 | 28 | #define PIL_NORMAL_MAX 14 |
| 28 | #define PIL_NMI 15 | 29 | #define PIL_NMI 15 |
| 29 | 30 | ||
diff --git a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c index e289376198eb..1c378d8e90c5 100644 --- a/arch/sparc/kernel/irq_64.c +++ b/arch/sparc/kernel/irq_64.c | |||
| @@ -323,17 +323,25 @@ static void sun4u_set_affinity(unsigned int virt_irq, | |||
| 323 | sun4u_irq_enable(virt_irq); | 323 | sun4u_irq_enable(virt_irq); |
| 324 | } | 324 | } |
| 325 | 325 | ||
| 326 | /* Don't do anything. The desc->status check for IRQ_DISABLED in | ||
| 327 | * handler_irq() will skip the handler call and that will leave the | ||
| 328 | * interrupt in the sent state. The next ->enable() call will hit the | ||
| 329 | * ICLR register to reset the state machine. | ||
| 330 | * | ||
| 331 | * This scheme is necessary, instead of clearing the Valid bit in the | ||
| 332 | * IMAP register, to handle the case of IMAP registers being shared by | ||
| 333 | * multiple INOs (and thus ICLR registers). Since we use a different | ||
| 334 | * virtual IRQ for each shared IMAP instance, the generic code thinks | ||
| 335 | * there is only one user so it prematurely calls ->disable() on | ||
| 336 | * free_irq(). | ||
| 337 | * | ||
| 338 | * We have to provide an explicit ->disable() method instead of using | ||
| 339 | * NULL to get the default. The reason is that if the generic code | ||
| 340 | * sees that, it also hooks up a default ->shutdown method which | ||
| 341 | * invokes ->mask() which we do not want. See irq_chip_set_defaults(). | ||
| 342 | */ | ||
| 326 | static void sun4u_irq_disable(unsigned int virt_irq) | 343 | static void sun4u_irq_disable(unsigned int virt_irq) |
| 327 | { | 344 | { |
| 328 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); | ||
| 329 | |||
| 330 | if (likely(data)) { | ||
| 331 | unsigned long imap = data->imap; | ||
| 332 | unsigned long tmp = upa_readq(imap); | ||
| 333 | |||
| 334 | tmp &= ~IMAP_VALID; | ||
| 335 | upa_writeq(tmp, imap); | ||
| 336 | } | ||
| 337 | } | 345 | } |
| 338 | 346 | ||
| 339 | static void sun4u_irq_eoi(unsigned int virt_irq) | 347 | static void sun4u_irq_eoi(unsigned int virt_irq) |
| @@ -746,7 +754,8 @@ void handler_irq(int irq, struct pt_regs *regs) | |||
| 746 | 754 | ||
| 747 | desc = irq_desc + virt_irq; | 755 | desc = irq_desc + virt_irq; |
| 748 | 756 | ||
| 749 | desc->handle_irq(virt_irq, desc); | 757 | if (!(desc->status & IRQ_DISABLED)) |
| 758 | desc->handle_irq(virt_irq, desc); | ||
| 750 | 759 | ||
| 751 | bucket_pa = next_pa; | 760 | bucket_pa = next_pa; |
| 752 | } | 761 | } |
diff --git a/arch/sparc/kernel/kgdb_64.c b/arch/sparc/kernel/kgdb_64.c index fefbe6dc51be..f5a0fd490b59 100644 --- a/arch/sparc/kernel/kgdb_64.c +++ b/arch/sparc/kernel/kgdb_64.c | |||
| @@ -108,7 +108,7 @@ void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs) | |||
| 108 | } | 108 | } |
| 109 | 109 | ||
| 110 | #ifdef CONFIG_SMP | 110 | #ifdef CONFIG_SMP |
| 111 | void smp_kgdb_capture_client(struct pt_regs *regs) | 111 | void smp_kgdb_capture_client(int irq, struct pt_regs *regs) |
| 112 | { | 112 | { |
| 113 | unsigned long flags; | 113 | unsigned long flags; |
| 114 | 114 | ||
diff --git a/arch/sparc/kernel/pci_common.c b/arch/sparc/kernel/pci_common.c index 64e6edf17b9d..b775658a927d 100644 --- a/arch/sparc/kernel/pci_common.c +++ b/arch/sparc/kernel/pci_common.c | |||
| @@ -368,7 +368,7 @@ static void pci_register_iommu_region(struct pci_pbm_info *pbm) | |||
| 368 | const u32 *vdma = of_get_property(pbm->op->node, "virtual-dma", NULL); | 368 | const u32 *vdma = of_get_property(pbm->op->node, "virtual-dma", NULL); |
| 369 | 369 | ||
| 370 | if (vdma) { | 370 | if (vdma) { |
| 371 | struct resource *rp = kmalloc(sizeof(*rp), GFP_KERNEL); | 371 | struct resource *rp = kzalloc(sizeof(*rp), GFP_KERNEL); |
| 372 | 372 | ||
| 373 | if (!rp) { | 373 | if (!rp) { |
| 374 | prom_printf("Cannot allocate IOMMU resource.\n"); | 374 | prom_printf("Cannot allocate IOMMU resource.\n"); |
diff --git a/arch/sparc/kernel/ttable.S b/arch/sparc/kernel/ttable.S index d9bdfb9d5c18..76d837fc47d3 100644 --- a/arch/sparc/kernel/ttable.S +++ b/arch/sparc/kernel/ttable.S | |||
| @@ -64,7 +64,12 @@ tl0_irq6: TRAP_IRQ(smp_call_function_single_client, 6) | |||
| 64 | tl0_irq6: BTRAP(0x46) | 64 | tl0_irq6: BTRAP(0x46) |
| 65 | #endif | 65 | #endif |
| 66 | tl0_irq7: TRAP_IRQ(deferred_pcr_work_irq, 7) | 66 | tl0_irq7: TRAP_IRQ(deferred_pcr_work_irq, 7) |
| 67 | tl0_irq8: BTRAP(0x48) BTRAP(0x49) | 67 | #ifdef CONFIG_KGDB |
| 68 | tl0_irq8: TRAP_IRQ(smp_kgdb_capture_client, 8) | ||
| 69 | #else | ||
| 70 | tl0_irq8: BTRAP(0x48) | ||
| 71 | #endif | ||
| 72 | tl0_irq9: BTRAP(0x49) | ||
| 68 | tl0_irq10: BTRAP(0x4a) BTRAP(0x4b) BTRAP(0x4c) BTRAP(0x4d) | 73 | tl0_irq10: BTRAP(0x4a) BTRAP(0x4b) BTRAP(0x4c) BTRAP(0x4d) |
| 69 | tl0_irq14: TRAP_IRQ(timer_interrupt, 14) | 74 | tl0_irq14: TRAP_IRQ(timer_interrupt, 14) |
| 70 | tl0_irq15: TRAP_NMI_IRQ(perfctr_irq, 15) | 75 | tl0_irq15: TRAP_NMI_IRQ(perfctr_irq, 15) |
diff --git a/arch/sparc/mm/ultra.S b/arch/sparc/mm/ultra.S index 80c788ec7c32..b57a5942ba64 100644 --- a/arch/sparc/mm/ultra.S +++ b/arch/sparc/mm/ultra.S | |||
| @@ -679,28 +679,8 @@ xcall_new_mmu_context_version: | |||
| 679 | #ifdef CONFIG_KGDB | 679 | #ifdef CONFIG_KGDB |
| 680 | .globl xcall_kgdb_capture | 680 | .globl xcall_kgdb_capture |
| 681 | xcall_kgdb_capture: | 681 | xcall_kgdb_capture: |
| 682 | 661: rdpr %pstate, %g2 | 682 | wr %g0, (1 << PIL_KGDB_CAPTURE), %set_softint |
| 683 | wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate | 683 | retry |
| 684 | .section .sun4v_2insn_patch, "ax" | ||
| 685 | .word 661b | ||
| 686 | nop | ||
| 687 | nop | ||
| 688 | .previous | ||
| 689 | |||
| 690 | rdpr %pil, %g2 | ||
| 691 | wrpr %g0, PIL_NORMAL_MAX, %pil | ||
| 692 | sethi %hi(109f), %g7 | ||
| 693 | ba,pt %xcc, etrap_irq | ||
| 694 | 109: or %g7, %lo(109b), %g7 | ||
| 695 | #ifdef CONFIG_TRACE_IRQFLAGS | ||
| 696 | call trace_hardirqs_off | ||
| 697 | nop | ||
| 698 | #endif | ||
| 699 | call smp_kgdb_capture_client | ||
| 700 | add %sp, PTREGS_OFF, %o0 | ||
| 701 | /* Has to be a non-v9 branch due to the large distance. */ | ||
| 702 | ba rtrap_xcall | ||
| 703 | ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 | ||
| 704 | #endif | 684 | #endif |
| 705 | 685 | ||
| 706 | #endif /* CONFIG_SMP */ | 686 | #endif /* CONFIG_SMP */ |
diff --git a/arch/um/kernel/ptrace.c b/arch/um/kernel/ptrace.c index 15e8b7c4de13..8e3d69e4fcb5 100644 --- a/arch/um/kernel/ptrace.c +++ b/arch/um/kernel/ptrace.c | |||
| @@ -64,6 +64,11 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data) | |||
| 64 | ret = poke_user(child, addr, data); | 64 | ret = poke_user(child, addr, data); |
| 65 | break; | 65 | break; |
| 66 | 66 | ||
| 67 | case PTRACE_SYSEMU: | ||
| 68 | case PTRACE_SYSEMU_SINGLESTEP: | ||
| 69 | ret = -EIO; | ||
| 70 | break; | ||
| 71 | |||
| 67 | /* continue and stop at next (return from) syscall */ | 72 | /* continue and stop at next (return from) syscall */ |
| 68 | case PTRACE_SYSCALL: | 73 | case PTRACE_SYSCALL: |
| 69 | /* restart after signal. */ | 74 | /* restart after signal. */ |
diff --git a/arch/um/os-Linux/user_syms.c b/arch/um/os-Linux/user_syms.c index 74f49bb9b125..89b48a116a89 100644 --- a/arch/um/os-Linux/user_syms.c +++ b/arch/um/os-Linux/user_syms.c | |||
| @@ -14,7 +14,6 @@ | |||
| 14 | #undef memset | 14 | #undef memset |
| 15 | 15 | ||
| 16 | extern size_t strlen(const char *); | 16 | extern size_t strlen(const char *); |
| 17 | extern void *memcpy(void *, const void *, size_t); | ||
| 18 | extern void *memmove(void *, const void *, size_t); | 17 | extern void *memmove(void *, const void *, size_t); |
| 19 | extern void *memset(void *, int, size_t); | 18 | extern void *memset(void *, int, size_t); |
| 20 | extern int printf(const char *, ...); | 19 | extern int printf(const char *, ...); |
| @@ -24,7 +23,11 @@ extern int printf(const char *, ...); | |||
| 24 | EXPORT_SYMBOL(strstr); | 23 | EXPORT_SYMBOL(strstr); |
| 25 | #endif | 24 | #endif |
| 26 | 25 | ||
| 26 | #ifndef __x86_64__ | ||
| 27 | extern void *memcpy(void *, const void *, size_t); | ||
| 27 | EXPORT_SYMBOL(memcpy); | 28 | EXPORT_SYMBOL(memcpy); |
| 29 | #endif | ||
| 30 | |||
| 28 | EXPORT_SYMBOL(memmove); | 31 | EXPORT_SYMBOL(memmove); |
| 29 | EXPORT_SYMBOL(memset); | 32 | EXPORT_SYMBOL(memset); |
| 30 | EXPORT_SYMBOL(printf); | 33 | EXPORT_SYMBOL(printf); |
diff --git a/arch/x86/include/asm/efi.h b/arch/x86/include/asm/efi.h index ca5ffb2856b6..edc90f23e708 100644 --- a/arch/x86/include/asm/efi.h +++ b/arch/x86/include/asm/efi.h | |||
| @@ -37,8 +37,6 @@ extern unsigned long asmlinkage efi_call_phys(void *, ...); | |||
| 37 | 37 | ||
| 38 | #else /* !CONFIG_X86_32 */ | 38 | #else /* !CONFIG_X86_32 */ |
| 39 | 39 | ||
| 40 | #define MAX_EFI_IO_PAGES 100 | ||
| 41 | |||
| 42 | extern u64 efi_call0(void *fp); | 40 | extern u64 efi_call0(void *fp); |
| 43 | extern u64 efi_call1(void *fp, u64 arg1); | 41 | extern u64 efi_call1(void *fp, u64 arg1); |
| 44 | extern u64 efi_call2(void *fp, u64 arg1, u64 arg2); | 42 | extern u64 efi_call2(void *fp, u64 arg1, u64 arg2); |
diff --git a/arch/x86/include/asm/fixmap_64.h b/arch/x86/include/asm/fixmap_64.h index 00a30ab9b1a5..8be740977db8 100644 --- a/arch/x86/include/asm/fixmap_64.h +++ b/arch/x86/include/asm/fixmap_64.h | |||
| @@ -16,7 +16,6 @@ | |||
| 16 | #include <asm/apicdef.h> | 16 | #include <asm/apicdef.h> |
| 17 | #include <asm/page.h> | 17 | #include <asm/page.h> |
| 18 | #include <asm/vsyscall.h> | 18 | #include <asm/vsyscall.h> |
| 19 | #include <asm/efi.h> | ||
| 20 | 19 | ||
| 21 | /* | 20 | /* |
| 22 | * Here we define all the compile-time 'special' virtual | 21 | * Here we define all the compile-time 'special' virtual |
| @@ -43,9 +42,6 @@ enum fixed_addresses { | |||
| 43 | FIX_APIC_BASE, /* local (CPU) APIC) -- required for SMP or not */ | 42 | FIX_APIC_BASE, /* local (CPU) APIC) -- required for SMP or not */ |
| 44 | FIX_IO_APIC_BASE_0, | 43 | FIX_IO_APIC_BASE_0, |
| 45 | FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1, | 44 | FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1, |
| 46 | FIX_EFI_IO_MAP_LAST_PAGE, | ||
| 47 | FIX_EFI_IO_MAP_FIRST_PAGE = FIX_EFI_IO_MAP_LAST_PAGE | ||
| 48 | + MAX_EFI_IO_PAGES - 1, | ||
| 49 | #ifdef CONFIG_PARAVIRT | 45 | #ifdef CONFIG_PARAVIRT |
| 50 | FIX_PARAVIRT_BOOTMAP, | 46 | FIX_PARAVIRT_BOOTMAP, |
| 51 | #endif | 47 | #endif |
diff --git a/arch/x86/include/asm/i387.h b/arch/x86/include/asm/i387.h index 48f0004db8c9..71c9e5183982 100644 --- a/arch/x86/include/asm/i387.h +++ b/arch/x86/include/asm/i387.h | |||
| @@ -172,7 +172,13 @@ static inline void __save_init_fpu(struct task_struct *tsk) | |||
| 172 | 172 | ||
| 173 | #else /* CONFIG_X86_32 */ | 173 | #else /* CONFIG_X86_32 */ |
| 174 | 174 | ||
| 175 | extern void finit(void); | 175 | #ifdef CONFIG_MATH_EMULATION |
| 176 | extern void finit_task(struct task_struct *tsk); | ||
| 177 | #else | ||
| 178 | static inline void finit_task(struct task_struct *tsk) | ||
| 179 | { | ||
| 180 | } | ||
| 181 | #endif | ||
| 176 | 182 | ||
| 177 | static inline void tolerant_fwait(void) | 183 | static inline void tolerant_fwait(void) |
| 178 | { | 184 | { |
diff --git a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c index b585e04cbc9e..3178c3acd97e 100644 --- a/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c +++ b/arch/x86/kernel/cpu/cpufreq/p4-clockmod.c | |||
| @@ -277,7 +277,6 @@ static struct cpufreq_driver p4clockmod_driver = { | |||
| 277 | .name = "p4-clockmod", | 277 | .name = "p4-clockmod", |
| 278 | .owner = THIS_MODULE, | 278 | .owner = THIS_MODULE, |
| 279 | .attr = p4clockmod_attr, | 279 | .attr = p4clockmod_attr, |
| 280 | .hide_interface = 1, | ||
| 281 | }; | 280 | }; |
| 282 | 281 | ||
| 283 | 282 | ||
diff --git a/arch/x86/kernel/ds.c b/arch/x86/kernel/ds.c index 169a120587be..87b67e3a765a 100644 --- a/arch/x86/kernel/ds.c +++ b/arch/x86/kernel/ds.c | |||
| @@ -729,7 +729,7 @@ struct pebs_tracer *ds_request_pebs(struct task_struct *task, | |||
| 729 | 729 | ||
| 730 | spin_unlock_irqrestore(&ds_lock, irq); | 730 | spin_unlock_irqrestore(&ds_lock, irq); |
| 731 | 731 | ||
| 732 | ds_write_config(tracer->ds.context, &tracer->trace.ds, ds_bts); | 732 | ds_write_config(tracer->ds.context, &tracer->trace.ds, ds_pebs); |
| 733 | ds_resume_pebs(tracer); | 733 | ds_resume_pebs(tracer); |
| 734 | 734 | ||
| 735 | return tracer; | 735 | return tracer; |
| @@ -1029,5 +1029,4 @@ void ds_copy_thread(struct task_struct *tsk, struct task_struct *father) | |||
| 1029 | 1029 | ||
| 1030 | void ds_exit_thread(struct task_struct *tsk) | 1030 | void ds_exit_thread(struct task_struct *tsk) |
| 1031 | { | 1031 | { |
| 1032 | WARN_ON(tsk->thread.ds_ctx); | ||
| 1033 | } | 1032 | } |
diff --git a/arch/x86/kernel/efi.c b/arch/x86/kernel/efi.c index 1119d247fe11..eb1ef3b67dd5 100644 --- a/arch/x86/kernel/efi.c +++ b/arch/x86/kernel/efi.c | |||
| @@ -467,7 +467,7 @@ void __init efi_enter_virtual_mode(void) | |||
| 467 | efi_memory_desc_t *md; | 467 | efi_memory_desc_t *md; |
| 468 | efi_status_t status; | 468 | efi_status_t status; |
| 469 | unsigned long size; | 469 | unsigned long size; |
| 470 | u64 end, systab, addr, npages; | 470 | u64 end, systab, addr, npages, end_pfn; |
| 471 | void *p, *va; | 471 | void *p, *va; |
| 472 | 472 | ||
| 473 | efi.systab = NULL; | 473 | efi.systab = NULL; |
| @@ -479,7 +479,10 @@ void __init efi_enter_virtual_mode(void) | |||
| 479 | size = md->num_pages << EFI_PAGE_SHIFT; | 479 | size = md->num_pages << EFI_PAGE_SHIFT; |
| 480 | end = md->phys_addr + size; | 480 | end = md->phys_addr + size; |
| 481 | 481 | ||
| 482 | if (PFN_UP(end) <= max_low_pfn_mapped) | 482 | end_pfn = PFN_UP(end); |
| 483 | if (end_pfn <= max_low_pfn_mapped | ||
| 484 | || (end_pfn > (1UL << (32 - PAGE_SHIFT)) | ||
| 485 | && end_pfn <= max_pfn_mapped)) | ||
| 483 | va = __va(md->phys_addr); | 486 | va = __va(md->phys_addr); |
| 484 | else | 487 | else |
| 485 | va = efi_ioremap(md->phys_addr, size); | 488 | va = efi_ioremap(md->phys_addr, size); |
diff --git a/arch/x86/kernel/efi_64.c b/arch/x86/kernel/efi_64.c index 652c5287215f..cb783b92c50c 100644 --- a/arch/x86/kernel/efi_64.c +++ b/arch/x86/kernel/efi_64.c | |||
| @@ -99,24 +99,11 @@ void __init efi_call_phys_epilog(void) | |||
| 99 | 99 | ||
| 100 | void __iomem *__init efi_ioremap(unsigned long phys_addr, unsigned long size) | 100 | void __iomem *__init efi_ioremap(unsigned long phys_addr, unsigned long size) |
| 101 | { | 101 | { |
| 102 | static unsigned pages_mapped __initdata; | 102 | unsigned long last_map_pfn; |
| 103 | unsigned i, pages; | ||
| 104 | unsigned long offset; | ||
| 105 | 103 | ||
| 106 | pages = PFN_UP(phys_addr + size) - PFN_DOWN(phys_addr); | 104 | last_map_pfn = init_memory_mapping(phys_addr, phys_addr + size); |
| 107 | offset = phys_addr & ~PAGE_MASK; | 105 | if ((last_map_pfn << PAGE_SHIFT) < phys_addr + size) |
| 108 | phys_addr &= PAGE_MASK; | ||
| 109 | |||
| 110 | if (pages_mapped + pages > MAX_EFI_IO_PAGES) | ||
| 111 | return NULL; | 106 | return NULL; |
| 112 | 107 | ||
| 113 | for (i = 0; i < pages; i++) { | 108 | return (void __iomem *)__va(phys_addr); |
| 114 | __set_fixmap(FIX_EFI_IO_MAP_FIRST_PAGE - pages_mapped, | ||
| 115 | phys_addr, PAGE_KERNEL); | ||
| 116 | phys_addr += PAGE_SIZE; | ||
| 117 | pages_mapped++; | ||
| 118 | } | ||
| 119 | |||
| 120 | return (void __iomem *)__fix_to_virt(FIX_EFI_IO_MAP_FIRST_PAGE - \ | ||
| 121 | (pages_mapped - pages)) + offset; | ||
| 122 | } | 109 | } |
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c index b0f61f0dcd0a..f2f8540a7f3d 100644 --- a/arch/x86/kernel/i387.c +++ b/arch/x86/kernel/i387.c | |||
| @@ -136,7 +136,7 @@ int init_fpu(struct task_struct *tsk) | |||
| 136 | #ifdef CONFIG_X86_32 | 136 | #ifdef CONFIG_X86_32 |
| 137 | if (!HAVE_HWFP) { | 137 | if (!HAVE_HWFP) { |
| 138 | memset(tsk->thread.xstate, 0, xstate_size); | 138 | memset(tsk->thread.xstate, 0, xstate_size); |
| 139 | finit(); | 139 | finit_task(tsk); |
| 140 | set_stopped_child_used_math(tsk); | 140 | set_stopped_child_used_math(tsk); |
| 141 | return 0; | 141 | return 0; |
| 142 | } | 142 | } |
diff --git a/arch/x86/kernel/kprobes.c b/arch/x86/kernel/kprobes.c index e948b28a5a9a..4558dd3918cf 100644 --- a/arch/x86/kernel/kprobes.c +++ b/arch/x86/kernel/kprobes.c | |||
| @@ -193,6 +193,9 @@ static int __kprobes can_boost(kprobe_opcode_t *opcodes) | |||
| 193 | kprobe_opcode_t opcode; | 193 | kprobe_opcode_t opcode; |
| 194 | kprobe_opcode_t *orig_opcodes = opcodes; | 194 | kprobe_opcode_t *orig_opcodes = opcodes; |
| 195 | 195 | ||
| 196 | if (search_exception_tables(opcodes)) | ||
| 197 | return 0; /* Page fault may occur on this address. */ | ||
| 198 | |||
| 196 | retry: | 199 | retry: |
| 197 | if (opcodes - orig_opcodes > MAX_INSN_SIZE - 1) | 200 | if (opcodes - orig_opcodes > MAX_INSN_SIZE - 1) |
| 198 | return 0; | 201 | return 0; |
diff --git a/arch/x86/kernel/reboot.c b/arch/x86/kernel/reboot.c index 2b46eb41643b..4526b3a75ed2 100644 --- a/arch/x86/kernel/reboot.c +++ b/arch/x86/kernel/reboot.c | |||
| @@ -217,6 +217,14 @@ static struct dmi_system_id __initdata reboot_dmi_table[] = { | |||
| 217 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq"), | 217 | DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq"), |
| 218 | }, | 218 | }, |
| 219 | }, | 219 | }, |
| 220 | { /* Handle problems with rebooting on Dell XPS710 */ | ||
| 221 | .callback = set_bios_reboot, | ||
| 222 | .ident = "Dell XPS710", | ||
| 223 | .matches = { | ||
| 224 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | ||
| 225 | DMI_MATCH(DMI_PRODUCT_NAME, "Dell XPS710"), | ||
| 226 | }, | ||
| 227 | }, | ||
| 220 | { } | 228 | { } |
| 221 | }; | 229 | }; |
| 222 | 230 | ||
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c index c461f6d69074..6a8811a69324 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c | |||
| @@ -770,6 +770,9 @@ void __init setup_arch(char **cmdline_p) | |||
| 770 | 770 | ||
| 771 | finish_e820_parsing(); | 771 | finish_e820_parsing(); |
| 772 | 772 | ||
| 773 | if (efi_enabled) | ||
| 774 | efi_init(); | ||
| 775 | |||
| 773 | dmi_scan_machine(); | 776 | dmi_scan_machine(); |
| 774 | 777 | ||
| 775 | dmi_check_system(bad_bios_dmi_table); | 778 | dmi_check_system(bad_bios_dmi_table); |
| @@ -789,8 +792,6 @@ void __init setup_arch(char **cmdline_p) | |||
| 789 | insert_resource(&iomem_resource, &data_resource); | 792 | insert_resource(&iomem_resource, &data_resource); |
| 790 | insert_resource(&iomem_resource, &bss_resource); | 793 | insert_resource(&iomem_resource, &bss_resource); |
| 791 | 794 | ||
| 792 | if (efi_enabled) | ||
| 793 | efi_init(); | ||
| 794 | 795 | ||
| 795 | #ifdef CONFIG_X86_32 | 796 | #ifdef CONFIG_X86_32 |
| 796 | if (ppro_with_ram_bug()) { | 797 | if (ppro_with_ram_bug()) { |
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 599e58168631..d5cebb52d45b 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c | |||
| @@ -273,30 +273,43 @@ static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) | |||
| 273 | * use the TSC value at the transitions to calculate a pretty | 273 | * use the TSC value at the transitions to calculate a pretty |
| 274 | * good value for the TSC frequencty. | 274 | * good value for the TSC frequencty. |
| 275 | */ | 275 | */ |
| 276 | static inline int pit_expect_msb(unsigned char val) | 276 | static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap) |
| 277 | { | 277 | { |
| 278 | int count = 0; | 278 | int count; |
| 279 | u64 tsc = 0; | ||
| 279 | 280 | ||
| 280 | for (count = 0; count < 50000; count++) { | 281 | for (count = 0; count < 50000; count++) { |
| 281 | /* Ignore LSB */ | 282 | /* Ignore LSB */ |
| 282 | inb(0x42); | 283 | inb(0x42); |
| 283 | if (inb(0x42) != val) | 284 | if (inb(0x42) != val) |
| 284 | break; | 285 | break; |
| 286 | tsc = get_cycles(); | ||
| 285 | } | 287 | } |
| 286 | return count > 50; | 288 | *deltap = get_cycles() - tsc; |
| 289 | *tscp = tsc; | ||
| 290 | |||
| 291 | /* | ||
| 292 | * We require _some_ success, but the quality control | ||
| 293 | * will be based on the error terms on the TSC values. | ||
| 294 | */ | ||
| 295 | return count > 5; | ||
| 287 | } | 296 | } |
| 288 | 297 | ||
| 289 | /* | 298 | /* |
| 290 | * How many MSB values do we want to see? We aim for a | 299 | * How many MSB values do we want to see? We aim for |
| 291 | * 15ms calibration, which assuming a 2us counter read | 300 | * a maximum error rate of 500ppm (in practice the |
| 292 | * error should give us roughly 150 ppm precision for | 301 | * real error is much smaller), but refuse to spend |
| 293 | * the calibration. | 302 | * more than 25ms on it. |
| 294 | */ | 303 | */ |
| 295 | #define QUICK_PIT_MS 15 | 304 | #define MAX_QUICK_PIT_MS 25 |
| 296 | #define QUICK_PIT_ITERATIONS (QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) | 305 | #define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) |
| 297 | 306 | ||
| 298 | static unsigned long quick_pit_calibrate(void) | 307 | static unsigned long quick_pit_calibrate(void) |
| 299 | { | 308 | { |
| 309 | int i; | ||
| 310 | u64 tsc, delta; | ||
| 311 | unsigned long d1, d2; | ||
| 312 | |||
| 300 | /* Set the Gate high, disable speaker */ | 313 | /* Set the Gate high, disable speaker */ |
| 301 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); | 314 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); |
| 302 | 315 | ||
| @@ -315,45 +328,52 @@ static unsigned long quick_pit_calibrate(void) | |||
| 315 | outb(0xff, 0x42); | 328 | outb(0xff, 0x42); |
| 316 | outb(0xff, 0x42); | 329 | outb(0xff, 0x42); |
| 317 | 330 | ||
| 318 | if (pit_expect_msb(0xff)) { | 331 | /* |
| 319 | int i; | 332 | * The PIT starts counting at the next edge, so we |
| 320 | u64 t1, t2, delta; | 333 | * need to delay for a microsecond. The easiest way |
| 321 | unsigned char expect = 0xfe; | 334 | * to do that is to just read back the 16-bit counter |
| 322 | 335 | * once from the PIT. | |
| 323 | t1 = get_cycles(); | 336 | */ |
| 324 | for (i = 0; i < QUICK_PIT_ITERATIONS; i++, expect--) { | 337 | inb(0x42); |
| 325 | if (!pit_expect_msb(expect)) | 338 | inb(0x42); |
| 326 | goto failed; | 339 | |
| 340 | if (pit_expect_msb(0xff, &tsc, &d1)) { | ||
| 341 | for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) { | ||
| 342 | if (!pit_expect_msb(0xff-i, &delta, &d2)) | ||
| 343 | break; | ||
| 344 | |||
| 345 | /* | ||
| 346 | * Iterate until the error is less than 500 ppm | ||
| 347 | */ | ||
| 348 | delta -= tsc; | ||
| 349 | if (d1+d2 < delta >> 11) | ||
| 350 | goto success; | ||
| 327 | } | 351 | } |
| 328 | t2 = get_cycles(); | ||
| 329 | |||
| 330 | /* | ||
| 331 | * Make sure we can rely on the second TSC timestamp: | ||
| 332 | */ | ||
| 333 | if (!pit_expect_msb(expect)) | ||
| 334 | goto failed; | ||
| 335 | |||
| 336 | /* | ||
| 337 | * Ok, if we get here, then we've seen the | ||
| 338 | * MSB of the PIT decrement QUICK_PIT_ITERATIONS | ||
| 339 | * times, and each MSB had many hits, so we never | ||
| 340 | * had any sudden jumps. | ||
| 341 | * | ||
| 342 | * As a result, we can depend on there not being | ||
| 343 | * any odd delays anywhere, and the TSC reads are | ||
| 344 | * reliable. | ||
| 345 | * | ||
| 346 | * kHz = ticks / time-in-seconds / 1000; | ||
| 347 | * kHz = (t2 - t1) / (QPI * 256 / PIT_TICK_RATE) / 1000 | ||
| 348 | * kHz = ((t2 - t1) * PIT_TICK_RATE) / (QPI * 256 * 1000) | ||
| 349 | */ | ||
| 350 | delta = (t2 - t1)*PIT_TICK_RATE; | ||
| 351 | do_div(delta, QUICK_PIT_ITERATIONS*256*1000); | ||
| 352 | printk("Fast TSC calibration using PIT\n"); | ||
| 353 | return delta; | ||
| 354 | } | 352 | } |
| 355 | failed: | 353 | printk("Fast TSC calibration failed\n"); |
| 356 | return 0; | 354 | return 0; |
| 355 | |||
| 356 | success: | ||
| 357 | /* | ||
| 358 | * Ok, if we get here, then we've seen the | ||
| 359 | * MSB of the PIT decrement 'i' times, and the | ||
| 360 | * error has shrunk to less than 500 ppm. | ||
| 361 | * | ||
| 362 | * As a result, we can depend on there not being | ||
| 363 | * any odd delays anywhere, and the TSC reads are | ||
| 364 | * reliable (within the error). We also adjust the | ||
| 365 | * delta to the middle of the error bars, just | ||
| 366 | * because it looks nicer. | ||
| 367 | * | ||
| 368 | * kHz = ticks / time-in-seconds / 1000; | ||
| 369 | * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000 | ||
| 370 | * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000) | ||
| 371 | */ | ||
| 372 | delta += (long)(d2 - d1)/2; | ||
| 373 | delta *= PIT_TICK_RATE; | ||
| 374 | do_div(delta, i*256*1000); | ||
| 375 | printk("Fast TSC calibration using PIT\n"); | ||
| 376 | return delta; | ||
| 357 | } | 377 | } |
| 358 | 378 | ||
| 359 | /** | 379 | /** |
diff --git a/arch/x86/lguest/boot.c b/arch/x86/lguest/boot.c index 92f1c6f3e19d..960a8d9c049c 100644 --- a/arch/x86/lguest/boot.c +++ b/arch/x86/lguest/boot.c | |||
| @@ -343,6 +343,11 @@ static void lguest_cpuid(unsigned int *ax, unsigned int *bx, | |||
| 343 | * flush_tlb_user() for both user and kernel mappings unless | 343 | * flush_tlb_user() for both user and kernel mappings unless |
| 344 | * the Page Global Enable (PGE) feature bit is set. */ | 344 | * the Page Global Enable (PGE) feature bit is set. */ |
| 345 | *dx |= 0x00002000; | 345 | *dx |= 0x00002000; |
| 346 | /* We also lie, and say we're family id 5. 6 or greater | ||
| 347 | * leads to a rdmsr in early_init_intel which we can't handle. | ||
| 348 | * Family ID is returned as bits 8-12 in ax. */ | ||
| 349 | *ax &= 0xFFFFF0FF; | ||
| 350 | *ax |= 0x00000500; | ||
| 346 | break; | 351 | break; |
| 347 | case 0x80000000: | 352 | case 0x80000000: |
| 348 | /* Futureproof this a little: if they ask how much extended | 353 | /* Futureproof this a little: if they ask how much extended |
| @@ -589,19 +594,21 @@ static void __init lguest_init_IRQ(void) | |||
| 589 | /* Some systems map "vectors" to interrupts weirdly. Lguest has | 594 | /* Some systems map "vectors" to interrupts weirdly. Lguest has |
| 590 | * a straightforward 1 to 1 mapping, so force that here. */ | 595 | * a straightforward 1 to 1 mapping, so force that here. */ |
| 591 | __get_cpu_var(vector_irq)[vector] = i; | 596 | __get_cpu_var(vector_irq)[vector] = i; |
| 592 | if (vector != SYSCALL_VECTOR) { | 597 | if (vector != SYSCALL_VECTOR) |
| 593 | set_intr_gate(vector, | 598 | set_intr_gate(vector, interrupt[i]); |
| 594 | interrupt[vector-FIRST_EXTERNAL_VECTOR]); | ||
| 595 | set_irq_chip_and_handler_name(i, &lguest_irq_controller, | ||
| 596 | handle_level_irq, | ||
| 597 | "level"); | ||
| 598 | } | ||
| 599 | } | 599 | } |
| 600 | /* This call is required to set up for 4k stacks, where we have | 600 | /* This call is required to set up for 4k stacks, where we have |
| 601 | * separate stacks for hard and soft interrupts. */ | 601 | * separate stacks for hard and soft interrupts. */ |
| 602 | irq_ctx_init(smp_processor_id()); | 602 | irq_ctx_init(smp_processor_id()); |
| 603 | } | 603 | } |
| 604 | 604 | ||
| 605 | void lguest_setup_irq(unsigned int irq) | ||
| 606 | { | ||
| 607 | irq_to_desc_alloc_cpu(irq, 0); | ||
| 608 | set_irq_chip_and_handler_name(irq, &lguest_irq_controller, | ||
| 609 | handle_level_irq, "level"); | ||
| 610 | } | ||
| 611 | |||
| 605 | /* | 612 | /* |
| 606 | * Time. | 613 | * Time. |
| 607 | * | 614 | * |
diff --git a/arch/x86/math-emu/fpu_aux.c b/arch/x86/math-emu/fpu_aux.c index 491e737ce547..aa0987088774 100644 --- a/arch/x86/math-emu/fpu_aux.c +++ b/arch/x86/math-emu/fpu_aux.c | |||
| @@ -30,20 +30,29 @@ static void fclex(void) | |||
| 30 | } | 30 | } |
| 31 | 31 | ||
| 32 | /* Needs to be externally visible */ | 32 | /* Needs to be externally visible */ |
| 33 | void finit(void) | 33 | void finit_task(struct task_struct *tsk) |
| 34 | { | 34 | { |
| 35 | control_word = 0x037f; | 35 | struct i387_soft_struct *soft = &tsk->thread.xstate->soft; |
| 36 | partial_status = 0; | 36 | struct address *oaddr, *iaddr; |
| 37 | top = 0; /* We don't keep top in the status word internally. */ | 37 | soft->cwd = 0x037f; |
| 38 | fpu_tag_word = 0xffff; | 38 | soft->swd = 0; |
| 39 | soft->ftop = 0; /* We don't keep top in the status word internally. */ | ||
| 40 | soft->twd = 0xffff; | ||
| 39 | /* The behaviour is different from that detailed in | 41 | /* The behaviour is different from that detailed in |
| 40 | Section 15.1.6 of the Intel manual */ | 42 | Section 15.1.6 of the Intel manual */ |
| 41 | operand_address.offset = 0; | 43 | oaddr = (struct address *)&soft->foo; |
| 42 | operand_address.selector = 0; | 44 | oaddr->offset = 0; |
| 43 | instruction_address.offset = 0; | 45 | oaddr->selector = 0; |
| 44 | instruction_address.selector = 0; | 46 | iaddr = (struct address *)&soft->fip; |
| 45 | instruction_address.opcode = 0; | 47 | iaddr->offset = 0; |
| 46 | no_ip_update = 1; | 48 | iaddr->selector = 0; |
| 49 | iaddr->opcode = 0; | ||
| 50 | soft->no_update = 1; | ||
| 51 | } | ||
| 52 | |||
| 53 | void finit(void) | ||
| 54 | { | ||
| 55 | finit_task(current); | ||
| 47 | } | 56 | } |
| 48 | 57 | ||
| 49 | /* | 58 | /* |
diff --git a/arch/x86/mm/kmmio.c b/arch/x86/mm/kmmio.c index 9f205030d9aa..6a518dd08a36 100644 --- a/arch/x86/mm/kmmio.c +++ b/arch/x86/mm/kmmio.c | |||
| @@ -451,23 +451,24 @@ static void rcu_free_kmmio_fault_pages(struct rcu_head *head) | |||
| 451 | 451 | ||
| 452 | static void remove_kmmio_fault_pages(struct rcu_head *head) | 452 | static void remove_kmmio_fault_pages(struct rcu_head *head) |
| 453 | { | 453 | { |
| 454 | struct kmmio_delayed_release *dr = container_of( | 454 | struct kmmio_delayed_release *dr = |
| 455 | head, | 455 | container_of(head, struct kmmio_delayed_release, rcu); |
| 456 | struct kmmio_delayed_release, | ||
| 457 | rcu); | ||
| 458 | struct kmmio_fault_page *p = dr->release_list; | 456 | struct kmmio_fault_page *p = dr->release_list; |
| 459 | struct kmmio_fault_page **prevp = &dr->release_list; | 457 | struct kmmio_fault_page **prevp = &dr->release_list; |
| 460 | unsigned long flags; | 458 | unsigned long flags; |
| 459 | |||
| 461 | spin_lock_irqsave(&kmmio_lock, flags); | 460 | spin_lock_irqsave(&kmmio_lock, flags); |
| 462 | while (p) { | 461 | while (p) { |
| 463 | if (!p->count) | 462 | if (!p->count) { |
| 464 | list_del_rcu(&p->list); | 463 | list_del_rcu(&p->list); |
| 465 | else | 464 | prevp = &p->release_next; |
| 465 | } else { | ||
| 466 | *prevp = p->release_next; | 466 | *prevp = p->release_next; |
| 467 | prevp = &p->release_next; | 467 | } |
| 468 | p = p->release_next; | 468 | p = p->release_next; |
| 469 | } | 469 | } |
| 470 | spin_unlock_irqrestore(&kmmio_lock, flags); | 470 | spin_unlock_irqrestore(&kmmio_lock, flags); |
| 471 | |||
| 471 | /* This is the real RCU destroy call. */ | 472 | /* This is the real RCU destroy call. */ |
| 472 | call_rcu(&dr->rcu, rcu_free_kmmio_fault_pages); | 473 | call_rcu(&dr->rcu, rcu_free_kmmio_fault_pages); |
| 473 | } | 474 | } |
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c index 7be47d1a97e4..7233bd7e357b 100644 --- a/arch/x86/mm/pageattr.c +++ b/arch/x86/mm/pageattr.c | |||
| @@ -515,6 +515,17 @@ static int split_large_page(pte_t *kpte, unsigned long address) | |||
| 515 | * primary protection behavior: | 515 | * primary protection behavior: |
| 516 | */ | 516 | */ |
| 517 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); | 517 | __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE))); |
| 518 | |||
| 519 | /* | ||
| 520 | * Intel Atom errata AAH41 workaround. | ||
| 521 | * | ||
| 522 | * The real fix should be in hw or in a microcode update, but | ||
| 523 | * we also probabilistically try to reduce the window of having | ||
| 524 | * a large TLB mixed with 4K TLBs while instruction fetches are | ||
| 525 | * going on. | ||
| 526 | */ | ||
| 527 | __flush_tlb_all(); | ||
| 528 | |||
| 518 | base = NULL; | 529 | base = NULL; |
| 519 | 530 | ||
| 520 | out_unlock: | 531 | out_unlock: |
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 6c873dceb177..981200830432 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig | |||
| @@ -103,9 +103,6 @@ config MATH_EMULATION | |||
| 103 | help | 103 | help |
| 104 | Can we use information of configuration file? | 104 | Can we use information of configuration file? |
| 105 | 105 | ||
| 106 | config HIGHMEM | ||
| 107 | bool "High memory support" | ||
| 108 | |||
| 109 | endmenu | 106 | endmenu |
| 110 | 107 | ||
| 111 | menu "Platform options" | 108 | menu "Platform options" |
diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c index 9606d2bd1dd9..4ec1633c2941 100644 --- a/arch/xtensa/kernel/setup.c +++ b/arch/xtensa/kernel/setup.c | |||
| @@ -44,6 +44,8 @@ | |||
| 44 | #include <asm/setup.h> | 44 | #include <asm/setup.h> |
| 45 | #include <asm/param.h> | 45 | #include <asm/param.h> |
| 46 | 46 | ||
| 47 | #include <platform/hardware.h> | ||
| 48 | |||
| 47 | #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) | 49 | #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) |
| 48 | struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16}; | 50 | struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16}; |
| 49 | #endif | 51 | #endif |
diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c index c7a021d9f696..c44f830b6c7a 100644 --- a/arch/xtensa/kernel/traps.c +++ b/arch/xtensa/kernel/traps.c | |||
| @@ -30,6 +30,7 @@ | |||
| 30 | #include <linux/stringify.h> | 30 | #include <linux/stringify.h> |
| 31 | #include <linux/kallsyms.h> | 31 | #include <linux/kallsyms.h> |
| 32 | #include <linux/delay.h> | 32 | #include <linux/delay.h> |
| 33 | #include <linux/hardirq.h> | ||
| 33 | 34 | ||
| 34 | #include <asm/ptrace.h> | 35 | #include <asm/ptrace.h> |
| 35 | #include <asm/timex.h> | 36 | #include <asm/timex.h> |
diff --git a/arch/xtensa/mm/fault.c b/arch/xtensa/mm/fault.c index 33f366be323f..bdd860d93f72 100644 --- a/arch/xtensa/mm/fault.c +++ b/arch/xtensa/mm/fault.c | |||
| @@ -14,6 +14,7 @@ | |||
| 14 | 14 | ||
| 15 | #include <linux/mm.h> | 15 | #include <linux/mm.h> |
| 16 | #include <linux/module.h> | 16 | #include <linux/module.h> |
| 17 | #include <linux/hardirq.h> | ||
| 17 | #include <asm/mmu_context.h> | 18 | #include <asm/mmu_context.h> |
| 18 | #include <asm/cacheflush.h> | 19 | #include <asm/cacheflush.h> |
| 19 | #include <asm/hardirq.h> | 20 | #include <asm/hardirq.h> |
diff --git a/arch/xtensa/platforms/iss/console.c b/arch/xtensa/platforms/iss/console.c index efed8897bef3..25d46c84eb08 100644 --- a/arch/xtensa/platforms/iss/console.c +++ b/arch/xtensa/platforms/iss/console.c | |||
| @@ -140,16 +140,14 @@ static void rs_poll(unsigned long priv) | |||
| 140 | } | 140 | } |
| 141 | 141 | ||
| 142 | 142 | ||
| 143 | static void rs_put_char(struct tty_struct *tty, unsigned char ch) | 143 | static int rs_put_char(struct tty_struct *tty, unsigned char ch) |
| 144 | { | 144 | { |
| 145 | char buf[2]; | 145 | char buf[2]; |
| 146 | 146 | ||
| 147 | if (!tty) | ||
| 148 | return; | ||
| 149 | |||
| 150 | buf[0] = ch; | 147 | buf[0] = ch; |
| 151 | buf[1] = '\0'; /* Is this NULL necessary? */ | 148 | buf[1] = '\0'; /* Is this NULL necessary? */ |
| 152 | __simc (SYS_write, 1, (unsigned long) buf, 1, 0, 0); | 149 | __simc (SYS_write, 1, (unsigned long) buf, 1, 0, 0); |
| 150 | return 1; | ||
| 153 | } | 151 | } |
| 154 | 152 | ||
| 155 | static void rs_flush_chars(struct tty_struct *tty) | 153 | static void rs_flush_chars(struct tty_struct *tty) |
diff --git a/block/blk-merge.c b/block/blk-merge.c index a104593e70c3..5a244f05360f 100644 --- a/block/blk-merge.c +++ b/block/blk-merge.c | |||
| @@ -39,14 +39,13 @@ void blk_recalc_rq_sectors(struct request *rq, int nsect) | |||
| 39 | } | 39 | } |
| 40 | 40 | ||
| 41 | static unsigned int __blk_recalc_rq_segments(struct request_queue *q, | 41 | static unsigned int __blk_recalc_rq_segments(struct request_queue *q, |
| 42 | struct bio *bio, | 42 | struct bio *bio) |
| 43 | unsigned int *seg_size_ptr) | ||
| 44 | { | 43 | { |
| 45 | unsigned int phys_size; | 44 | unsigned int phys_size; |
| 46 | struct bio_vec *bv, *bvprv = NULL; | 45 | struct bio_vec *bv, *bvprv = NULL; |
| 47 | int cluster, i, high, highprv = 1; | 46 | int cluster, i, high, highprv = 1; |
| 48 | unsigned int seg_size, nr_phys_segs; | 47 | unsigned int seg_size, nr_phys_segs; |
| 49 | struct bio *fbio; | 48 | struct bio *fbio, *bbio; |
| 50 | 49 | ||
| 51 | if (!bio) | 50 | if (!bio) |
| 52 | return 0; | 51 | return 0; |
| @@ -87,26 +86,20 @@ new_segment: | |||
| 87 | seg_size = bv->bv_len; | 86 | seg_size = bv->bv_len; |
| 88 | highprv = high; | 87 | highprv = high; |
| 89 | } | 88 | } |
| 89 | bbio = bio; | ||
| 90 | } | 90 | } |
| 91 | 91 | ||
| 92 | if (seg_size_ptr) | 92 | if (nr_phys_segs == 1 && seg_size > fbio->bi_seg_front_size) |
| 93 | *seg_size_ptr = seg_size; | 93 | fbio->bi_seg_front_size = seg_size; |
| 94 | if (seg_size > bbio->bi_seg_back_size) | ||
| 95 | bbio->bi_seg_back_size = seg_size; | ||
| 94 | 96 | ||
| 95 | return nr_phys_segs; | 97 | return nr_phys_segs; |
| 96 | } | 98 | } |
| 97 | 99 | ||
| 98 | void blk_recalc_rq_segments(struct request *rq) | 100 | void blk_recalc_rq_segments(struct request *rq) |
| 99 | { | 101 | { |
| 100 | unsigned int seg_size = 0, phys_segs; | 102 | rq->nr_phys_segments = __blk_recalc_rq_segments(rq->q, rq->bio); |
| 101 | |||
| 102 | phys_segs = __blk_recalc_rq_segments(rq->q, rq->bio, &seg_size); | ||
| 103 | |||
| 104 | if (phys_segs == 1 && seg_size > rq->bio->bi_seg_front_size) | ||
| 105 | rq->bio->bi_seg_front_size = seg_size; | ||
| 106 | if (seg_size > rq->biotail->bi_seg_back_size) | ||
| 107 | rq->biotail->bi_seg_back_size = seg_size; | ||
| 108 | |||
| 109 | rq->nr_phys_segments = phys_segs; | ||
| 110 | } | 103 | } |
| 111 | 104 | ||
| 112 | void blk_recount_segments(struct request_queue *q, struct bio *bio) | 105 | void blk_recount_segments(struct request_queue *q, struct bio *bio) |
| @@ -114,7 +107,7 @@ void blk_recount_segments(struct request_queue *q, struct bio *bio) | |||
| 114 | struct bio *nxt = bio->bi_next; | 107 | struct bio *nxt = bio->bi_next; |
| 115 | 108 | ||
| 116 | bio->bi_next = NULL; | 109 | bio->bi_next = NULL; |
| 117 | bio->bi_phys_segments = __blk_recalc_rq_segments(q, bio, NULL); | 110 | bio->bi_phys_segments = __blk_recalc_rq_segments(q, bio); |
| 118 | bio->bi_next = nxt; | 111 | bio->bi_next = nxt; |
| 119 | bio->bi_flags |= (1 << BIO_SEG_VALID); | 112 | bio->bi_flags |= (1 << BIO_SEG_VALID); |
| 120 | } | 113 | } |
diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index 765fd1c56cd6..bee64b73c919 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c | |||
| @@ -758,8 +758,7 @@ static int __init acpi_bus_init(void) | |||
| 758 | acpi_status status = AE_OK; | 758 | acpi_status status = AE_OK; |
| 759 | extern acpi_status acpi_os_initialize1(void); | 759 | extern acpi_status acpi_os_initialize1(void); |
| 760 | 760 | ||
| 761 | 761 | acpi_os_initialize1(); | |
| 762 | status = acpi_os_initialize1(); | ||
| 763 | 762 | ||
| 764 | status = | 763 | status = |
| 765 | acpi_enable_subsystem(ACPI_NO_HARDWARE_INIT | ACPI_NO_ACPI_ENABLE); | 764 | acpi_enable_subsystem(ACPI_NO_HARDWARE_INIT | ACPI_NO_ACPI_ENABLE); |
| @@ -769,12 +768,6 @@ static int __init acpi_bus_init(void) | |||
| 769 | goto error1; | 768 | goto error1; |
| 770 | } | 769 | } |
| 771 | 770 | ||
| 772 | if (ACPI_FAILURE(status)) { | ||
| 773 | printk(KERN_ERR PREFIX | ||
| 774 | "Unable to initialize ACPI OS objects\n"); | ||
| 775 | goto error1; | ||
| 776 | } | ||
| 777 | |||
| 778 | /* | 771 | /* |
| 779 | * ACPI 2.0 requires the EC driver to be loaded and work before | 772 | * ACPI 2.0 requires the EC driver to be loaded and work before |
| 780 | * the EC device is found in the namespace (i.e. before acpi_initialize_objects() | 773 | * the EC device is found in the namespace (i.e. before acpi_initialize_objects() |
diff --git a/drivers/acpi/numa.c b/drivers/acpi/numa.c index c5e292aab0e3..3a0d8ef25c75 100644 --- a/drivers/acpi/numa.c +++ b/drivers/acpi/numa.c | |||
| @@ -277,7 +277,7 @@ int acpi_get_node(acpi_handle *handle) | |||
| 277 | int pxm, node = -1; | 277 | int pxm, node = -1; |
| 278 | 278 | ||
| 279 | pxm = acpi_get_pxm(handle); | 279 | pxm = acpi_get_pxm(handle); |
| 280 | if (pxm >= 0) | 280 | if (pxm >= 0 && pxm < MAX_PXM_DOMAINS) |
| 281 | node = acpi_map_pxm_to_node(pxm); | 281 | node = acpi_map_pxm_to_node(pxm); |
| 282 | 282 | ||
| 283 | return node; | 283 | return node; |
diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c index b3193ec0a2ef..1e35f342957c 100644 --- a/drivers/acpi/osl.c +++ b/drivers/acpi/osl.c | |||
| @@ -1317,54 +1317,6 @@ acpi_os_validate_interface (char *interface) | |||
| 1317 | return AE_SUPPORT; | 1317 | return AE_SUPPORT; |
| 1318 | } | 1318 | } |
| 1319 | 1319 | ||
| 1320 | #ifdef CONFIG_X86 | ||
| 1321 | |||
| 1322 | struct aml_port_desc { | ||
| 1323 | uint start; | ||
| 1324 | uint end; | ||
| 1325 | char* name; | ||
| 1326 | char warned; | ||
| 1327 | }; | ||
| 1328 | |||
| 1329 | static struct aml_port_desc aml_invalid_port_list[] = { | ||
| 1330 | {0x20, 0x21, "PIC0", 0}, | ||
| 1331 | {0xA0, 0xA1, "PIC1", 0}, | ||
| 1332 | {0x4D0, 0x4D1, "ELCR", 0} | ||
| 1333 | }; | ||
| 1334 | |||
| 1335 | /* | ||
| 1336 | * valid_aml_io_address() | ||
| 1337 | * | ||
| 1338 | * if valid, return true | ||
| 1339 | * else invalid, warn once, return false | ||
| 1340 | */ | ||
| 1341 | static bool valid_aml_io_address(uint address, uint length) | ||
| 1342 | { | ||
| 1343 | int i; | ||
| 1344 | int entries = sizeof(aml_invalid_port_list) / sizeof(struct aml_port_desc); | ||
| 1345 | |||
| 1346 | for (i = 0; i < entries; ++i) { | ||
| 1347 | if ((address >= aml_invalid_port_list[i].start && | ||
| 1348 | address <= aml_invalid_port_list[i].end) || | ||
| 1349 | (address + length >= aml_invalid_port_list[i].start && | ||
| 1350 | address + length <= aml_invalid_port_list[i].end)) | ||
| 1351 | { | ||
| 1352 | if (!aml_invalid_port_list[i].warned) | ||
| 1353 | { | ||
| 1354 | printk(KERN_ERR "ACPI: Denied BIOS AML access" | ||
| 1355 | " to invalid port 0x%x+0x%x (%s)\n", | ||
| 1356 | address, length, | ||
| 1357 | aml_invalid_port_list[i].name); | ||
| 1358 | aml_invalid_port_list[i].warned = 1; | ||
| 1359 | } | ||
| 1360 | return false; /* invalid */ | ||
| 1361 | } | ||
| 1362 | } | ||
| 1363 | return true; /* valid */ | ||
| 1364 | } | ||
| 1365 | #else | ||
| 1366 | static inline bool valid_aml_io_address(uint address, uint length) { return true; } | ||
| 1367 | #endif | ||
| 1368 | /****************************************************************************** | 1320 | /****************************************************************************** |
| 1369 | * | 1321 | * |
| 1370 | * FUNCTION: acpi_os_validate_address | 1322 | * FUNCTION: acpi_os_validate_address |
| @@ -1394,8 +1346,6 @@ acpi_os_validate_address ( | |||
| 1394 | 1346 | ||
| 1395 | switch (space_id) { | 1347 | switch (space_id) { |
| 1396 | case ACPI_ADR_SPACE_SYSTEM_IO: | 1348 | case ACPI_ADR_SPACE_SYSTEM_IO: |
| 1397 | if (!valid_aml_io_address(address, length)) | ||
| 1398 | return AE_AML_ILLEGAL_ADDRESS; | ||
| 1399 | case ACPI_ADR_SPACE_SYSTEM_MEMORY: | 1349 | case ACPI_ADR_SPACE_SYSTEM_MEMORY: |
| 1400 | /* Only interference checks against SystemIO and SytemMemory | 1350 | /* Only interference checks against SystemIO and SytemMemory |
| 1401 | are needed */ | 1351 | are needed */ |
diff --git a/drivers/acpi/sleep.c b/drivers/acpi/sleep.c index 519266654f06..00456fccfa38 100644 --- a/drivers/acpi/sleep.c +++ b/drivers/acpi/sleep.c | |||
| @@ -378,6 +378,22 @@ static struct dmi_system_id __initdata acpisleep_dmi_table[] = { | |||
| 378 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), | 378 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
| 379 | }, | 379 | }, |
| 380 | }, | 380 | }, |
| 381 | { | ||
| 382 | .callback = init_old_suspend_ordering, | ||
| 383 | .ident = "Asus Pundit P1-AH2 (M2N8L motherboard)", | ||
| 384 | .matches = { | ||
| 385 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTek Computer INC."), | ||
| 386 | DMI_MATCH(DMI_BOARD_NAME, "M2N8L"), | ||
| 387 | }, | ||
| 388 | }, | ||
| 389 | { | ||
| 390 | .callback = init_set_sci_en_on_resume, | ||
| 391 | .ident = "Toshiba Satellite L300", | ||
| 392 | .matches = { | ||
| 393 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | ||
| 394 | DMI_MATCH(DMI_PRODUCT_NAME, "Satellite L300"), | ||
| 395 | }, | ||
| 396 | }, | ||
| 381 | {}, | 397 | {}, |
| 382 | }; | 398 | }; |
| 383 | #endif /* CONFIG_SUSPEND */ | 399 | #endif /* CONFIG_SUSPEND */ |
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index a603bbf9b1b7..66e012cd3271 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c | |||
| @@ -582,18 +582,18 @@ static const struct pci_device_id ahci_pci_tbl[] = { | |||
| 582 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */ | 582 | { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci }, /* MCP79 */ |
| 583 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */ | 583 | { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci }, /* MCP79 */ |
| 584 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */ | 584 | { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci }, /* MCP79 */ |
| 585 | { PCI_VDEVICE(NVIDIA, 0x0bc8), board_ahci }, /* MCP7B */ | 585 | { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci }, /* MCP89 */ |
| 586 | { PCI_VDEVICE(NVIDIA, 0x0bc9), board_ahci }, /* MCP7B */ | 586 | { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci }, /* MCP89 */ |
| 587 | { PCI_VDEVICE(NVIDIA, 0x0bca), board_ahci }, /* MCP7B */ | 587 | { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci }, /* MCP89 */ |
| 588 | { PCI_VDEVICE(NVIDIA, 0x0bcb), board_ahci }, /* MCP7B */ | 588 | { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci }, /* MCP89 */ |
| 589 | { PCI_VDEVICE(NVIDIA, 0x0bcc), board_ahci }, /* MCP7B */ | 589 | { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci }, /* MCP89 */ |
| 590 | { PCI_VDEVICE(NVIDIA, 0x0bcd), board_ahci }, /* MCP7B */ | 590 | { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci }, /* MCP89 */ |
| 591 | { PCI_VDEVICE(NVIDIA, 0x0bce), board_ahci }, /* MCP7B */ | 591 | { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci }, /* MCP89 */ |
| 592 | { PCI_VDEVICE(NVIDIA, 0x0bcf), board_ahci }, /* MCP7B */ | 592 | { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci }, /* MCP89 */ |
| 593 | { PCI_VDEVICE(NVIDIA, 0x0bc4), board_ahci }, /* MCP7B */ | 593 | { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci }, /* MCP89 */ |
| 594 | { PCI_VDEVICE(NVIDIA, 0x0bc5), board_ahci }, /* MCP7B */ | 594 | { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci }, /* MCP89 */ |
| 595 | { PCI_VDEVICE(NVIDIA, 0x0bc6), board_ahci }, /* MCP7B */ | 595 | { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci }, /* MCP89 */ |
| 596 | { PCI_VDEVICE(NVIDIA, 0x0bc7), board_ahci }, /* MCP7B */ | 596 | { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci }, /* MCP89 */ |
| 597 | 597 | ||
| 598 | /* SiS */ | 598 | /* SiS */ |
| 599 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ | 599 | { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */ |
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c index 54961c0b2c73..ef8b30d577bd 100644 --- a/drivers/ata/ata_piix.c +++ b/drivers/ata/ata_piix.c | |||
| @@ -1289,6 +1289,39 @@ static const int *__devinit piix_init_sata_map(struct pci_dev *pdev, | |||
| 1289 | return map; | 1289 | return map; |
| 1290 | } | 1290 | } |
| 1291 | 1291 | ||
| 1292 | static bool piix_no_sidpr(struct ata_host *host) | ||
| 1293 | { | ||
| 1294 | struct pci_dev *pdev = to_pci_dev(host->dev); | ||
| 1295 | |||
| 1296 | /* | ||
| 1297 | * Samsung DB-P70 only has three ATA ports exposed and | ||
| 1298 | * curiously the unconnected first port reports link online | ||
| 1299 | * while not responding to SRST protocol causing excessive | ||
| 1300 | * detection delay. | ||
| 1301 | * | ||
| 1302 | * Unfortunately, the system doesn't carry enough DMI | ||
| 1303 | * information to identify the machine but does have subsystem | ||
| 1304 | * vendor and device set. As it's unclear whether the | ||
| 1305 | * subsystem vendor/device is used only for this specific | ||
| 1306 | * board, the port can't be disabled solely with the | ||
| 1307 | * information; however, turning off SIDPR access works around | ||
| 1308 | * the problem. Turn it off. | ||
| 1309 | * | ||
| 1310 | * This problem is reported in bnc#441240. | ||
| 1311 | * | ||
| 1312 | * https://bugzilla.novell.com/show_bug.cgi?id=441420 | ||
| 1313 | */ | ||
| 1314 | if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 && | ||
| 1315 | pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG && | ||
| 1316 | pdev->subsystem_device == 0xb049) { | ||
| 1317 | dev_printk(KERN_WARNING, host->dev, | ||
| 1318 | "Samsung DB-P70 detected, disabling SIDPR\n"); | ||
| 1319 | return true; | ||
| 1320 | } | ||
| 1321 | |||
| 1322 | return false; | ||
| 1323 | } | ||
| 1324 | |||
| 1292 | static int __devinit piix_init_sidpr(struct ata_host *host) | 1325 | static int __devinit piix_init_sidpr(struct ata_host *host) |
| 1293 | { | 1326 | { |
| 1294 | struct pci_dev *pdev = to_pci_dev(host->dev); | 1327 | struct pci_dev *pdev = to_pci_dev(host->dev); |
| @@ -1302,6 +1335,10 @@ static int __devinit piix_init_sidpr(struct ata_host *host) | |||
| 1302 | if (hpriv->map[i] == IDE) | 1335 | if (hpriv->map[i] == IDE) |
| 1303 | return 0; | 1336 | return 0; |
| 1304 | 1337 | ||
| 1338 | /* is it blacklisted? */ | ||
| 1339 | if (piix_no_sidpr(host)) | ||
| 1340 | return 0; | ||
| 1341 | |||
| 1305 | if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) | 1342 | if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR)) |
| 1306 | return 0; | 1343 | return 0; |
| 1307 | 1344 | ||
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index 9fbf0595f3d4..060bcd601f57 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c | |||
| @@ -1322,14 +1322,16 @@ static u64 ata_id_n_sectors(const u16 *id) | |||
| 1322 | { | 1322 | { |
| 1323 | if (ata_id_has_lba(id)) { | 1323 | if (ata_id_has_lba(id)) { |
| 1324 | if (ata_id_has_lba48(id)) | 1324 | if (ata_id_has_lba48(id)) |
| 1325 | return ata_id_u64(id, 100); | 1325 | return ata_id_u64(id, ATA_ID_LBA_CAPACITY_2); |
| 1326 | else | 1326 | else |
| 1327 | return ata_id_u32(id, 60); | 1327 | return ata_id_u32(id, ATA_ID_LBA_CAPACITY); |
| 1328 | } else { | 1328 | } else { |
| 1329 | if (ata_id_current_chs_valid(id)) | 1329 | if (ata_id_current_chs_valid(id)) |
| 1330 | return ata_id_u32(id, 57); | 1330 | return id[ATA_ID_CUR_CYLS] * id[ATA_ID_CUR_HEADS] * |
| 1331 | id[ATA_ID_CUR_SECTORS]; | ||
| 1331 | else | 1332 | else |
| 1332 | return id[1] * id[3] * id[6]; | 1333 | return id[ATA_ID_CYLS] * id[ATA_ID_HEADS] * |
| 1334 | id[ATA_ID_SECTORS]; | ||
| 1333 | } | 1335 | } |
| 1334 | } | 1336 | } |
| 1335 | 1337 | ||
| @@ -4612,7 +4614,7 @@ void ata_sg_clean(struct ata_queued_cmd *qc) | |||
| 4612 | VPRINTK("unmapping %u sg elements\n", qc->n_elem); | 4614 | VPRINTK("unmapping %u sg elements\n", qc->n_elem); |
| 4613 | 4615 | ||
| 4614 | if (qc->n_elem) | 4616 | if (qc->n_elem) |
| 4615 | dma_unmap_sg(ap->dev, sg, qc->n_elem, dir); | 4617 | dma_unmap_sg(ap->dev, sg, qc->orig_n_elem, dir); |
| 4616 | 4618 | ||
| 4617 | qc->flags &= ~ATA_QCFLAG_DMAMAP; | 4619 | qc->flags &= ~ATA_QCFLAG_DMAMAP; |
| 4618 | qc->sg = NULL; | 4620 | qc->sg = NULL; |
| @@ -4727,7 +4729,7 @@ static int ata_sg_setup(struct ata_queued_cmd *qc) | |||
| 4727 | return -1; | 4729 | return -1; |
| 4728 | 4730 | ||
| 4729 | DPRINTK("%d sg elements mapped\n", n_elem); | 4731 | DPRINTK("%d sg elements mapped\n", n_elem); |
| 4730 | 4732 | qc->orig_n_elem = qc->n_elem; | |
| 4731 | qc->n_elem = n_elem; | 4733 | qc->n_elem = n_elem; |
| 4732 | qc->flags |= ATA_QCFLAG_DMAMAP; | 4734 | qc->flags |= ATA_QCFLAG_DMAMAP; |
| 4733 | 4735 | ||
diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c index ce2ef0475339..ea890911d4fa 100644 --- a/drivers/ata/libata-eh.c +++ b/drivers/ata/libata-eh.c | |||
| @@ -2423,11 +2423,14 @@ int ata_eh_reset(struct ata_link *link, int classify, | |||
| 2423 | } | 2423 | } |
| 2424 | 2424 | ||
| 2425 | /* prereset() might have cleared ATA_EH_RESET. If so, | 2425 | /* prereset() might have cleared ATA_EH_RESET. If so, |
| 2426 | * bang classes and return. | 2426 | * bang classes, thaw and return. |
| 2427 | */ | 2427 | */ |
| 2428 | if (reset && !(ehc->i.action & ATA_EH_RESET)) { | 2428 | if (reset && !(ehc->i.action & ATA_EH_RESET)) { |
| 2429 | ata_for_each_dev(dev, link, ALL) | 2429 | ata_for_each_dev(dev, link, ALL) |
| 2430 | classes[dev->devno] = ATA_DEV_NONE; | 2430 | classes[dev->devno] = ATA_DEV_NONE; |
| 2431 | if ((ap->pflags & ATA_PFLAG_FROZEN) && | ||
| 2432 | ata_is_host_link(link)) | ||
| 2433 | ata_eh_thaw_port(ap); | ||
| 2431 | rc = 0; | 2434 | rc = 0; |
| 2432 | goto out; | 2435 | goto out; |
| 2433 | } | 2436 | } |
| @@ -2901,7 +2904,7 @@ static int atapi_eh_clear_ua(struct ata_device *dev) | |||
| 2901 | int i; | 2904 | int i; |
| 2902 | 2905 | ||
| 2903 | for (i = 0; i < ATA_EH_UA_TRIES; i++) { | 2906 | for (i = 0; i < ATA_EH_UA_TRIES; i++) { |
| 2904 | u8 sense_buffer[SCSI_SENSE_BUFFERSIZE]; | 2907 | u8 *sense_buffer = dev->link->ap->sector_buf; |
| 2905 | u8 sense_key = 0; | 2908 | u8 sense_key = 0; |
| 2906 | unsigned int err_mask; | 2909 | unsigned int err_mask; |
| 2907 | 2910 | ||
diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c index 714cb046b594..f93dc029dfde 100644 --- a/drivers/ata/libata-sff.c +++ b/drivers/ata/libata-sff.c | |||
| @@ -2066,6 +2066,7 @@ static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask, | |||
| 2066 | iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr); | 2066 | iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr); |
| 2067 | udelay(20); /* FIXME: flush */ | 2067 | udelay(20); /* FIXME: flush */ |
| 2068 | iowrite8(ap->ctl, ioaddr->ctl_addr); | 2068 | iowrite8(ap->ctl, ioaddr->ctl_addr); |
| 2069 | ap->last_ctl = ap->ctl; | ||
| 2069 | 2070 | ||
| 2070 | /* wait the port to become ready */ | 2071 | /* wait the port to become ready */ |
| 2071 | return ata_sff_wait_after_reset(&ap->link, devmask, deadline); | 2072 | return ata_sff_wait_after_reset(&ap->link, devmask, deadline); |
| @@ -2190,8 +2191,10 @@ void ata_sff_postreset(struct ata_link *link, unsigned int *classes) | |||
| 2190 | } | 2191 | } |
| 2191 | 2192 | ||
| 2192 | /* set up device control */ | 2193 | /* set up device control */ |
| 2193 | if (ap->ioaddr.ctl_addr) | 2194 | if (ap->ioaddr.ctl_addr) { |
| 2194 | iowrite8(ap->ctl, ap->ioaddr.ctl_addr); | 2195 | iowrite8(ap->ctl, ap->ioaddr.ctl_addr); |
| 2196 | ap->last_ctl = ap->ctl; | ||
| 2197 | } | ||
| 2195 | } | 2198 | } |
| 2196 | EXPORT_SYMBOL_GPL(ata_sff_postreset); | 2199 | EXPORT_SYMBOL_GPL(ata_sff_postreset); |
| 2197 | 2200 | ||
| @@ -2534,6 +2537,7 @@ void ata_bus_reset(struct ata_port *ap) | |||
| 2534 | if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) { | 2537 | if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) { |
| 2535 | /* set up device control for ATA_FLAG_SATA_RESET */ | 2538 | /* set up device control for ATA_FLAG_SATA_RESET */ |
| 2536 | iowrite8(ap->ctl, ioaddr->ctl_addr); | 2539 | iowrite8(ap->ctl, ioaddr->ctl_addr); |
| 2540 | ap->last_ctl = ap->ctl; | ||
| 2537 | } | 2541 | } |
| 2538 | 2542 | ||
| 2539 | DPRINTK("EXIT\n"); | 2543 | DPRINTK("EXIT\n"); |
diff --git a/drivers/ata/pata_icside.c b/drivers/ata/pata_icside.c index cf9e9848f8b5..d7bc925c524d 100644 --- a/drivers/ata/pata_icside.c +++ b/drivers/ata/pata_icside.c | |||
| @@ -45,8 +45,6 @@ static const struct portinfo pata_icside_portinfo_v6_2 = { | |||
| 45 | .stepping = 6, | 45 | .stepping = 6, |
| 46 | }; | 46 | }; |
| 47 | 47 | ||
| 48 | #define PATA_ICSIDE_MAX_SG 128 | ||
| 49 | |||
| 50 | struct pata_icside_state { | 48 | struct pata_icside_state { |
| 51 | void __iomem *irq_port; | 49 | void __iomem *irq_port; |
| 52 | void __iomem *ioc_base; | 50 | void __iomem *ioc_base; |
| @@ -57,7 +55,6 @@ struct pata_icside_state { | |||
| 57 | u8 disabled; | 55 | u8 disabled; |
| 58 | unsigned int speed[ATA_MAX_DEVICES]; | 56 | unsigned int speed[ATA_MAX_DEVICES]; |
| 59 | } port[2]; | 57 | } port[2]; |
| 60 | struct scatterlist sg[PATA_ICSIDE_MAX_SG]; | ||
| 61 | }; | 58 | }; |
| 62 | 59 | ||
| 63 | struct pata_icside_info { | 60 | struct pata_icside_info { |
| @@ -222,9 +219,7 @@ static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc) | |||
| 222 | { | 219 | { |
| 223 | struct ata_port *ap = qc->ap; | 220 | struct ata_port *ap = qc->ap; |
| 224 | struct pata_icside_state *state = ap->host->private_data; | 221 | struct pata_icside_state *state = ap->host->private_data; |
| 225 | struct scatterlist *sg, *rsg = state->sg; | ||
| 226 | unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE; | 222 | unsigned int write = qc->tf.flags & ATA_TFLAG_WRITE; |
| 227 | unsigned int si; | ||
| 228 | 223 | ||
| 229 | /* | 224 | /* |
| 230 | * We are simplex; BUG if we try to fiddle with DMA | 225 | * We are simplex; BUG if we try to fiddle with DMA |
| @@ -233,20 +228,12 @@ static void pata_icside_bmdma_setup(struct ata_queued_cmd *qc) | |||
| 233 | BUG_ON(dma_channel_active(state->dma)); | 228 | BUG_ON(dma_channel_active(state->dma)); |
| 234 | 229 | ||
| 235 | /* | 230 | /* |
| 236 | * Copy ATAs scattered sg list into a contiguous array of sg | ||
| 237 | */ | ||
| 238 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | ||
| 239 | memcpy(rsg, sg, sizeof(*sg)); | ||
| 240 | rsg++; | ||
| 241 | } | ||
| 242 | |||
| 243 | /* | ||
| 244 | * Route the DMA signals to the correct interface | 231 | * Route the DMA signals to the correct interface |
| 245 | */ | 232 | */ |
| 246 | writeb(state->port[ap->port_no].port_sel, state->ioc_base); | 233 | writeb(state->port[ap->port_no].port_sel, state->ioc_base); |
| 247 | 234 | ||
| 248 | set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]); | 235 | set_dma_speed(state->dma, state->port[ap->port_no].speed[qc->dev->devno]); |
| 249 | set_dma_sg(state->dma, state->sg, rsg - state->sg); | 236 | set_dma_sg(state->dma, qc->sg, qc->n_elem); |
| 250 | set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ); | 237 | set_dma_mode(state->dma, write ? DMA_MODE_WRITE : DMA_MODE_READ); |
| 251 | 238 | ||
| 252 | /* issue r/w command */ | 239 | /* issue r/w command */ |
| @@ -306,8 +293,8 @@ static int icside_dma_init(struct pata_icside_info *info) | |||
| 306 | 293 | ||
| 307 | static struct scsi_host_template pata_icside_sht = { | 294 | static struct scsi_host_template pata_icside_sht = { |
| 308 | ATA_BASE_SHT(DRV_NAME), | 295 | ATA_BASE_SHT(DRV_NAME), |
| 309 | .sg_tablesize = PATA_ICSIDE_MAX_SG, | 296 | .sg_tablesize = SCSI_MAX_SG_CHAIN_SEGMENTS, |
| 310 | .dma_boundary = ~0, /* no dma boundaries */ | 297 | .dma_boundary = IOMD_DMA_BOUNDARY, |
| 311 | }; | 298 | }; |
| 312 | 299 | ||
| 313 | static void pata_icside_postreset(struct ata_link *link, unsigned int *classes) | 300 | static void pata_icside_postreset(struct ata_link *link, unsigned int *classes) |
diff --git a/drivers/ata/sata_mv.c b/drivers/ata/sata_mv.c index 7007edd2d451..74b1080d116d 100644 --- a/drivers/ata/sata_mv.c +++ b/drivers/ata/sata_mv.c | |||
| @@ -2218,12 +2218,13 @@ static irqreturn_t mv_interrupt(int irq, void *dev_instance) | |||
| 2218 | else | 2218 | else |
| 2219 | handled = mv_host_intr(host, pending_irqs); | 2219 | handled = mv_host_intr(host, pending_irqs); |
| 2220 | } | 2220 | } |
| 2221 | spin_unlock(&host->lock); | ||
| 2222 | 2221 | ||
| 2223 | /* for MSI: unmask; interrupt cause bits will retrigger now */ | 2222 | /* for MSI: unmask; interrupt cause bits will retrigger now */ |
| 2224 | if (using_msi) | 2223 | if (using_msi) |
| 2225 | writel(hpriv->main_irq_mask, hpriv->main_irq_mask_addr); | 2224 | writel(hpriv->main_irq_mask, hpriv->main_irq_mask_addr); |
| 2226 | 2225 | ||
| 2226 | spin_unlock(&host->lock); | ||
| 2227 | |||
| 2227 | return IRQ_RETVAL(handled); | 2228 | return IRQ_RETVAL(handled); |
| 2228 | } | 2229 | } |
| 2229 | 2230 | ||
diff --git a/drivers/ata/sata_nv.c b/drivers/ata/sata_nv.c index 55a8eed3f3a3..f65b53785a8f 100644 --- a/drivers/ata/sata_nv.c +++ b/drivers/ata/sata_nv.c | |||
| @@ -2523,7 +2523,7 @@ static void __exit nv_exit(void) | |||
| 2523 | module_init(nv_init); | 2523 | module_init(nv_init); |
| 2524 | module_exit(nv_exit); | 2524 | module_exit(nv_exit); |
| 2525 | module_param_named(adma, adma_enabled, bool, 0444); | 2525 | module_param_named(adma, adma_enabled, bool, 0444); |
| 2526 | MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: true)"); | 2526 | MODULE_PARM_DESC(adma, "Enable use of ADMA (Default: false)"); |
| 2527 | module_param_named(swncq, swncq_enabled, bool, 0444); | 2527 | module_param_named(swncq, swncq_enabled, bool, 0444); |
| 2528 | MODULE_PARM_DESC(swncq, "Enable use of SWNCQ (Default: true)"); | 2528 | MODULE_PARM_DESC(swncq, "Enable use of SWNCQ (Default: true)"); |
| 2529 | 2529 | ||
diff --git a/drivers/base/node.c b/drivers/base/node.c index 43fa90b837ee..f8f578a71b25 100644 --- a/drivers/base/node.c +++ b/drivers/base/node.c | |||
| @@ -303,7 +303,7 @@ int unregister_mem_sect_under_nodes(struct memory_block *mem_blk) | |||
| 303 | sect_start_pfn = section_nr_to_pfn(mem_blk->phys_index); | 303 | sect_start_pfn = section_nr_to_pfn(mem_blk->phys_index); |
| 304 | sect_end_pfn = sect_start_pfn + PAGES_PER_SECTION - 1; | 304 | sect_end_pfn = sect_start_pfn + PAGES_PER_SECTION - 1; |
| 305 | for (pfn = sect_start_pfn; pfn <= sect_end_pfn; pfn++) { | 305 | for (pfn = sect_start_pfn; pfn <= sect_end_pfn; pfn++) { |
| 306 | unsigned int nid; | 306 | int nid; |
| 307 | 307 | ||
| 308 | nid = get_nid_for_pfn(pfn); | 308 | nid = get_nid_for_pfn(pfn); |
| 309 | if (nid < 0) | 309 | if (nid < 0) |
diff --git a/drivers/block/Makefile b/drivers/block/Makefile index 204332b29578..87e120e0a79c 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile | |||
| @@ -9,6 +9,7 @@ obj-$(CONFIG_MAC_FLOPPY) += swim3.o | |||
| 9 | obj-$(CONFIG_BLK_DEV_FD) += floppy.o | 9 | obj-$(CONFIG_BLK_DEV_FD) += floppy.o |
| 10 | obj-$(CONFIG_AMIGA_FLOPPY) += amiflop.o | 10 | obj-$(CONFIG_AMIGA_FLOPPY) += amiflop.o |
| 11 | obj-$(CONFIG_PS3_DISK) += ps3disk.o | 11 | obj-$(CONFIG_PS3_DISK) += ps3disk.o |
| 12 | obj-$(CONFIG_PS3_VRAM) += ps3vram.o | ||
| 12 | obj-$(CONFIG_ATARI_FLOPPY) += ataflop.o | 13 | obj-$(CONFIG_ATARI_FLOPPY) += ataflop.o |
| 13 | obj-$(CONFIG_AMIGA_Z2RAM) += z2ram.o | 14 | obj-$(CONFIG_AMIGA_Z2RAM) += z2ram.o |
| 14 | obj-$(CONFIG_BLK_DEV_RAM) += brd.o | 15 | obj-$(CONFIG_BLK_DEV_RAM) += brd.o |
diff --git a/drivers/block/aoe/aoedev.c b/drivers/block/aoe/aoedev.c index cc250577d405..eeea477d9601 100644 --- a/drivers/block/aoe/aoedev.c +++ b/drivers/block/aoe/aoedev.c | |||
| @@ -173,7 +173,7 @@ skbfree(struct sk_buff *skb) | |||
| 173 | return; | 173 | return; |
| 174 | while (atomic_read(&skb_shinfo(skb)->dataref) != 1 && i-- > 0) | 174 | while (atomic_read(&skb_shinfo(skb)->dataref) != 1 && i-- > 0) |
| 175 | msleep(Sms); | 175 | msleep(Sms); |
| 176 | if (i <= 0) { | 176 | if (i < 0) { |
| 177 | printk(KERN_ERR | 177 | printk(KERN_ERR |
| 178 | "aoe: %s holds ref: %s\n", | 178 | "aoe: %s holds ref: %s\n", |
| 179 | skb->dev ? skb->dev->name : "netif", | 179 | skb->dev ? skb->dev->name : "netif", |
diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c index b5a061114630..4f9b6d792017 100644 --- a/drivers/block/cciss.c +++ b/drivers/block/cciss.c | |||
| @@ -3606,11 +3606,9 @@ static int __devinit cciss_init_one(struct pci_dev *pdev, | |||
| 3606 | if (cciss_hard_reset_controller(pdev) || cciss_reset_msi(pdev)) | 3606 | if (cciss_hard_reset_controller(pdev) || cciss_reset_msi(pdev)) |
| 3607 | return -ENODEV; | 3607 | return -ENODEV; |
| 3608 | 3608 | ||
| 3609 | /* Some devices (notably the HP Smart Array 5i Controller) | 3609 | /* Now try to get the controller to respond to a no-op. Some |
| 3610 | need a little pause here */ | 3610 | devices (notably the HP Smart Array 5i Controller) need |
| 3611 | schedule_timeout_uninterruptible(30*HZ); | 3611 | up to 30 seconds to respond. */ |
| 3612 | |||
| 3613 | /* Now try to get the controller to respond to a no-op */ | ||
| 3614 | for (i=0; i<30; i++) { | 3612 | for (i=0; i<30; i++) { |
| 3615 | if (cciss_noop(pdev) == 0) | 3613 | if (cciss_noop(pdev) == 0) |
| 3616 | break; | 3614 | break; |
diff --git a/drivers/block/loop.c b/drivers/block/loop.c index edbaac6c0573..bf0345577672 100644 --- a/drivers/block/loop.c +++ b/drivers/block/loop.c | |||
| @@ -392,8 +392,7 @@ lo_splice_actor(struct pipe_inode_info *pipe, struct pipe_buffer *buf, | |||
| 392 | struct loop_device *lo = p->lo; | 392 | struct loop_device *lo = p->lo; |
| 393 | struct page *page = buf->page; | 393 | struct page *page = buf->page; |
| 394 | sector_t IV; | 394 | sector_t IV; |
| 395 | size_t size; | 395 | int size, ret; |
| 396 | int ret; | ||
| 397 | 396 | ||
| 398 | ret = buf->ops->confirm(pipe, buf); | 397 | ret = buf->ops->confirm(pipe, buf); |
| 399 | if (unlikely(ret)) | 398 | if (unlikely(ret)) |
diff --git a/drivers/block/ps3vram.c b/drivers/block/ps3vram.c new file mode 100644 index 000000000000..393ed6760d78 --- /dev/null +++ b/drivers/block/ps3vram.c | |||
| @@ -0,0 +1,865 @@ | |||
| 1 | /* | ||
| 2 | * ps3vram - Use extra PS3 video ram as MTD block device. | ||
| 3 | * | ||
| 4 | * Copyright 2009 Sony Corporation | ||
| 5 | * | ||
| 6 | * Based on the MTD ps3vram driver, which is | ||
| 7 | * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com> | ||
| 8 | * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr> | ||
| 9 | */ | ||
| 10 | |||
| 11 | #include <linux/blkdev.h> | ||
| 12 | #include <linux/delay.h> | ||
| 13 | #include <linux/proc_fs.h> | ||
| 14 | #include <linux/seq_file.h> | ||
| 15 | |||
| 16 | #include <asm/firmware.h> | ||
| 17 | #include <asm/lv1call.h> | ||
| 18 | #include <asm/ps3.h> | ||
| 19 | |||
| 20 | |||
| 21 | #define DEVICE_NAME "ps3vram" | ||
| 22 | |||
| 23 | |||
| 24 | #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */ | ||
| 25 | #define XDR_IOIF 0x0c000000 | ||
| 26 | |||
| 27 | #define FIFO_BASE XDR_IOIF | ||
| 28 | #define FIFO_SIZE (64 * 1024) | ||
| 29 | |||
| 30 | #define DMA_PAGE_SIZE (4 * 1024) | ||
| 31 | |||
| 32 | #define CACHE_PAGE_SIZE (256 * 1024) | ||
| 33 | #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE) | ||
| 34 | |||
| 35 | #define CACHE_OFFSET CACHE_PAGE_SIZE | ||
| 36 | #define FIFO_OFFSET 0 | ||
| 37 | |||
| 38 | #define CTRL_PUT 0x10 | ||
| 39 | #define CTRL_GET 0x11 | ||
| 40 | #define CTRL_TOP 0x15 | ||
| 41 | |||
| 42 | #define UPLOAD_SUBCH 1 | ||
| 43 | #define DOWNLOAD_SUBCH 2 | ||
| 44 | |||
| 45 | #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c | ||
| 46 | #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 | ||
| 47 | |||
| 48 | #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601 | ||
| 49 | |||
| 50 | #define CACHE_PAGE_PRESENT 1 | ||
| 51 | #define CACHE_PAGE_DIRTY 2 | ||
| 52 | |||
| 53 | struct ps3vram_tag { | ||
| 54 | unsigned int address; | ||
| 55 | unsigned int flags; | ||
| 56 | }; | ||
| 57 | |||
| 58 | struct ps3vram_cache { | ||
| 59 | unsigned int page_count; | ||
| 60 | unsigned int page_size; | ||
| 61 | struct ps3vram_tag *tags; | ||
| 62 | unsigned int hit; | ||
| 63 | unsigned int miss; | ||
| 64 | }; | ||
| 65 | |||
| 66 | struct ps3vram_priv { | ||
| 67 | struct request_queue *queue; | ||
| 68 | struct gendisk *gendisk; | ||
| 69 | |||
| 70 | u64 size; | ||
| 71 | |||
| 72 | u64 memory_handle; | ||
| 73 | u64 context_handle; | ||
| 74 | u32 *ctrl; | ||
| 75 | u32 *reports; | ||
| 76 | u8 __iomem *ddr_base; | ||
| 77 | u8 *xdr_buf; | ||
| 78 | |||
| 79 | u32 *fifo_base; | ||
| 80 | u32 *fifo_ptr; | ||
| 81 | |||
| 82 | struct ps3vram_cache cache; | ||
| 83 | |||
| 84 | /* Used to serialize cache/DMA operations */ | ||
| 85 | struct mutex lock; | ||
| 86 | }; | ||
| 87 | |||
| 88 | |||
| 89 | static int ps3vram_major; | ||
| 90 | |||
| 91 | |||
| 92 | static struct block_device_operations ps3vram_fops = { | ||
| 93 | .owner = THIS_MODULE, | ||
| 94 | }; | ||
| 95 | |||
| 96 | |||
| 97 | #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */ | ||
| 98 | #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */ | ||
| 99 | #define DMA_NOTIFIER_SIZE 0x40 | ||
| 100 | #define NOTIFIER 7 /* notifier used for completion report */ | ||
| 101 | |||
| 102 | static char *size = "256M"; | ||
| 103 | module_param(size, charp, 0); | ||
| 104 | MODULE_PARM_DESC(size, "memory size"); | ||
| 105 | |||
| 106 | static u32 *ps3vram_get_notifier(u32 *reports, int notifier) | ||
| 107 | { | ||
| 108 | return (void *)reports + DMA_NOTIFIER_OFFSET_BASE + | ||
| 109 | DMA_NOTIFIER_SIZE * notifier; | ||
| 110 | } | ||
| 111 | |||
| 112 | static void ps3vram_notifier_reset(struct ps3_system_bus_device *dev) | ||
| 113 | { | ||
| 114 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 115 | u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER); | ||
| 116 | int i; | ||
| 117 | |||
| 118 | for (i = 0; i < 4; i++) | ||
| 119 | notify[i] = 0xffffffff; | ||
| 120 | } | ||
| 121 | |||
| 122 | static int ps3vram_notifier_wait(struct ps3_system_bus_device *dev, | ||
| 123 | unsigned int timeout_ms) | ||
| 124 | { | ||
| 125 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 126 | u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER); | ||
| 127 | unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); | ||
| 128 | |||
| 129 | do { | ||
| 130 | if (!notify[3]) | ||
| 131 | return 0; | ||
| 132 | msleep(1); | ||
| 133 | } while (time_before(jiffies, timeout)); | ||
| 134 | |||
| 135 | return -ETIMEDOUT; | ||
| 136 | } | ||
| 137 | |||
| 138 | static void ps3vram_init_ring(struct ps3_system_bus_device *dev) | ||
| 139 | { | ||
| 140 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 141 | |||
| 142 | priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET; | ||
| 143 | priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET; | ||
| 144 | } | ||
| 145 | |||
| 146 | static int ps3vram_wait_ring(struct ps3_system_bus_device *dev, | ||
| 147 | unsigned int timeout_ms) | ||
| 148 | { | ||
| 149 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 150 | unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); | ||
| 151 | |||
| 152 | do { | ||
| 153 | if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET]) | ||
| 154 | return 0; | ||
| 155 | msleep(1); | ||
| 156 | } while (time_before(jiffies, timeout)); | ||
| 157 | |||
| 158 | dev_warn(&dev->core, "FIFO timeout (%08x/%08x/%08x)\n", | ||
| 159 | priv->ctrl[CTRL_PUT], priv->ctrl[CTRL_GET], | ||
| 160 | priv->ctrl[CTRL_TOP]); | ||
| 161 | |||
| 162 | return -ETIMEDOUT; | ||
| 163 | } | ||
| 164 | |||
| 165 | static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data) | ||
| 166 | { | ||
| 167 | *(priv->fifo_ptr)++ = data; | ||
| 168 | } | ||
| 169 | |||
| 170 | static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, u32 tag, | ||
| 171 | u32 size) | ||
| 172 | { | ||
| 173 | ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag); | ||
| 174 | } | ||
| 175 | |||
| 176 | static void ps3vram_rewind_ring(struct ps3_system_bus_device *dev) | ||
| 177 | { | ||
| 178 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 179 | int status; | ||
| 180 | |||
| 181 | ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET)); | ||
| 182 | |||
| 183 | priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET; | ||
| 184 | |||
| 185 | /* asking the HV for a blit will kick the FIFO */ | ||
| 186 | status = lv1_gpu_context_attribute(priv->context_handle, | ||
| 187 | L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT, 0, | ||
| 188 | 0, 0, 0); | ||
| 189 | if (status) | ||
| 190 | dev_err(&dev->core, | ||
| 191 | "%s: lv1_gpu_context_attribute failed %d\n", __func__, | ||
| 192 | status); | ||
| 193 | |||
| 194 | priv->fifo_ptr = priv->fifo_base; | ||
| 195 | } | ||
| 196 | |||
| 197 | static void ps3vram_fire_ring(struct ps3_system_bus_device *dev) | ||
| 198 | { | ||
| 199 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 200 | int status; | ||
| 201 | |||
| 202 | mutex_lock(&ps3_gpu_mutex); | ||
| 203 | |||
| 204 | priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET + | ||
| 205 | (priv->fifo_ptr - priv->fifo_base) * sizeof(u32); | ||
| 206 | |||
| 207 | /* asking the HV for a blit will kick the FIFO */ | ||
| 208 | status = lv1_gpu_context_attribute(priv->context_handle, | ||
| 209 | L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT, 0, | ||
| 210 | 0, 0, 0); | ||
| 211 | if (status) | ||
| 212 | dev_err(&dev->core, | ||
| 213 | "%s: lv1_gpu_context_attribute failed %d\n", __func__, | ||
| 214 | status); | ||
| 215 | |||
| 216 | if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) > | ||
| 217 | FIFO_SIZE - 1024) { | ||
| 218 | dev_dbg(&dev->core, "FIFO full, rewinding\n"); | ||
| 219 | ps3vram_wait_ring(dev, 200); | ||
| 220 | ps3vram_rewind_ring(dev); | ||
| 221 | } | ||
| 222 | |||
| 223 | mutex_unlock(&ps3_gpu_mutex); | ||
| 224 | } | ||
| 225 | |||
| 226 | static void ps3vram_bind(struct ps3_system_bus_device *dev) | ||
| 227 | { | ||
| 228 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 229 | |||
| 230 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1); | ||
| 231 | ps3vram_out_ring(priv, 0x31337303); | ||
| 232 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3); | ||
| 233 | ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER); | ||
| 234 | ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */ | ||
| 235 | ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */ | ||
| 236 | |||
| 237 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1); | ||
| 238 | ps3vram_out_ring(priv, 0x3137c0de); | ||
| 239 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3); | ||
| 240 | ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER); | ||
| 241 | ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */ | ||
| 242 | ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */ | ||
| 243 | |||
| 244 | ps3vram_fire_ring(dev); | ||
| 245 | } | ||
| 246 | |||
| 247 | static int ps3vram_upload(struct ps3_system_bus_device *dev, | ||
| 248 | unsigned int src_offset, unsigned int dst_offset, | ||
| 249 | int len, int count) | ||
| 250 | { | ||
| 251 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 252 | |||
| 253 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, | ||
| 254 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | ||
| 255 | ps3vram_out_ring(priv, XDR_IOIF + src_offset); | ||
| 256 | ps3vram_out_ring(priv, dst_offset); | ||
| 257 | ps3vram_out_ring(priv, len); | ||
| 258 | ps3vram_out_ring(priv, len); | ||
| 259 | ps3vram_out_ring(priv, len); | ||
| 260 | ps3vram_out_ring(priv, count); | ||
| 261 | ps3vram_out_ring(priv, (1 << 8) | 1); | ||
| 262 | ps3vram_out_ring(priv, 0); | ||
| 263 | |||
| 264 | ps3vram_notifier_reset(dev); | ||
| 265 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, | ||
| 266 | NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1); | ||
| 267 | ps3vram_out_ring(priv, 0); | ||
| 268 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1); | ||
| 269 | ps3vram_out_ring(priv, 0); | ||
| 270 | ps3vram_fire_ring(dev); | ||
| 271 | if (ps3vram_notifier_wait(dev, 200) < 0) { | ||
| 272 | dev_warn(&dev->core, "%s: Notifier timeout\n", __func__); | ||
| 273 | return -1; | ||
| 274 | } | ||
| 275 | |||
| 276 | return 0; | ||
| 277 | } | ||
| 278 | |||
| 279 | static int ps3vram_download(struct ps3_system_bus_device *dev, | ||
| 280 | unsigned int src_offset, unsigned int dst_offset, | ||
| 281 | int len, int count) | ||
| 282 | { | ||
| 283 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 284 | |||
| 285 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, | ||
| 286 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | ||
| 287 | ps3vram_out_ring(priv, src_offset); | ||
| 288 | ps3vram_out_ring(priv, XDR_IOIF + dst_offset); | ||
| 289 | ps3vram_out_ring(priv, len); | ||
| 290 | ps3vram_out_ring(priv, len); | ||
| 291 | ps3vram_out_ring(priv, len); | ||
| 292 | ps3vram_out_ring(priv, count); | ||
| 293 | ps3vram_out_ring(priv, (1 << 8) | 1); | ||
| 294 | ps3vram_out_ring(priv, 0); | ||
| 295 | |||
| 296 | ps3vram_notifier_reset(dev); | ||
| 297 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, | ||
| 298 | NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1); | ||
| 299 | ps3vram_out_ring(priv, 0); | ||
| 300 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1); | ||
| 301 | ps3vram_out_ring(priv, 0); | ||
| 302 | ps3vram_fire_ring(dev); | ||
| 303 | if (ps3vram_notifier_wait(dev, 200) < 0) { | ||
| 304 | dev_warn(&dev->core, "%s: Notifier timeout\n", __func__); | ||
| 305 | return -1; | ||
| 306 | } | ||
| 307 | |||
| 308 | return 0; | ||
| 309 | } | ||
| 310 | |||
| 311 | static void ps3vram_cache_evict(struct ps3_system_bus_device *dev, int entry) | ||
| 312 | { | ||
| 313 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 314 | struct ps3vram_cache *cache = &priv->cache; | ||
| 315 | |||
| 316 | if (!(cache->tags[entry].flags & CACHE_PAGE_DIRTY)) | ||
| 317 | return; | ||
| 318 | |||
| 319 | dev_dbg(&dev->core, "Flushing %d: 0x%08x\n", entry, | ||
| 320 | cache->tags[entry].address); | ||
| 321 | if (ps3vram_upload(dev, CACHE_OFFSET + entry * cache->page_size, | ||
| 322 | cache->tags[entry].address, DMA_PAGE_SIZE, | ||
| 323 | cache->page_size / DMA_PAGE_SIZE) < 0) { | ||
| 324 | dev_err(&dev->core, | ||
| 325 | "Failed to upload from 0x%x to " "0x%x size 0x%x\n", | ||
| 326 | entry * cache->page_size, cache->tags[entry].address, | ||
| 327 | cache->page_size); | ||
| 328 | } | ||
| 329 | cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY; | ||
| 330 | } | ||
| 331 | |||
| 332 | static void ps3vram_cache_load(struct ps3_system_bus_device *dev, int entry, | ||
| 333 | unsigned int address) | ||
| 334 | { | ||
| 335 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 336 | struct ps3vram_cache *cache = &priv->cache; | ||
| 337 | |||
| 338 | dev_dbg(&dev->core, "Fetching %d: 0x%08x\n", entry, address); | ||
| 339 | if (ps3vram_download(dev, address, | ||
| 340 | CACHE_OFFSET + entry * cache->page_size, | ||
| 341 | DMA_PAGE_SIZE, | ||
| 342 | cache->page_size / DMA_PAGE_SIZE) < 0) { | ||
| 343 | dev_err(&dev->core, | ||
| 344 | "Failed to download from 0x%x to 0x%x size 0x%x\n", | ||
| 345 | address, entry * cache->page_size, cache->page_size); | ||
| 346 | } | ||
| 347 | |||
| 348 | cache->tags[entry].address = address; | ||
| 349 | cache->tags[entry].flags |= CACHE_PAGE_PRESENT; | ||
| 350 | } | ||
| 351 | |||
| 352 | |||
| 353 | static void ps3vram_cache_flush(struct ps3_system_bus_device *dev) | ||
| 354 | { | ||
| 355 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 356 | struct ps3vram_cache *cache = &priv->cache; | ||
| 357 | int i; | ||
| 358 | |||
| 359 | dev_dbg(&dev->core, "FLUSH\n"); | ||
| 360 | for (i = 0; i < cache->page_count; i++) { | ||
| 361 | ps3vram_cache_evict(dev, i); | ||
| 362 | cache->tags[i].flags = 0; | ||
| 363 | } | ||
| 364 | } | ||
| 365 | |||
| 366 | static unsigned int ps3vram_cache_match(struct ps3_system_bus_device *dev, | ||
| 367 | loff_t address) | ||
| 368 | { | ||
| 369 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 370 | struct ps3vram_cache *cache = &priv->cache; | ||
| 371 | unsigned int base; | ||
| 372 | unsigned int offset; | ||
| 373 | int i; | ||
| 374 | static int counter; | ||
| 375 | |||
| 376 | offset = (unsigned int) (address & (cache->page_size - 1)); | ||
| 377 | base = (unsigned int) (address - offset); | ||
| 378 | |||
| 379 | /* fully associative check */ | ||
| 380 | for (i = 0; i < cache->page_count; i++) { | ||
| 381 | if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) && | ||
| 382 | cache->tags[i].address == base) { | ||
| 383 | cache->hit++; | ||
| 384 | dev_dbg(&dev->core, "Found entry %d: 0x%08x\n", i, | ||
| 385 | cache->tags[i].address); | ||
| 386 | return i; | ||
| 387 | } | ||
| 388 | } | ||
| 389 | |||
| 390 | /* choose a random entry */ | ||
| 391 | i = (jiffies + (counter++)) % cache->page_count; | ||
| 392 | dev_dbg(&dev->core, "Using entry %d\n", i); | ||
| 393 | |||
| 394 | ps3vram_cache_evict(dev, i); | ||
| 395 | ps3vram_cache_load(dev, i, base); | ||
| 396 | |||
| 397 | cache->miss++; | ||
| 398 | return i; | ||
| 399 | } | ||
| 400 | |||
| 401 | static int ps3vram_cache_init(struct ps3_system_bus_device *dev) | ||
| 402 | { | ||
| 403 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 404 | |||
| 405 | priv->cache.page_count = CACHE_PAGE_COUNT; | ||
| 406 | priv->cache.page_size = CACHE_PAGE_SIZE; | ||
| 407 | priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) * | ||
| 408 | CACHE_PAGE_COUNT, GFP_KERNEL); | ||
| 409 | if (priv->cache.tags == NULL) { | ||
| 410 | dev_err(&dev->core, "Could not allocate cache tags\n"); | ||
| 411 | return -ENOMEM; | ||
| 412 | } | ||
| 413 | |||
| 414 | dev_info(&dev->core, "Created ram cache: %d entries, %d KiB each\n", | ||
| 415 | CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024); | ||
| 416 | |||
| 417 | return 0; | ||
| 418 | } | ||
| 419 | |||
| 420 | static void ps3vram_cache_cleanup(struct ps3_system_bus_device *dev) | ||
| 421 | { | ||
| 422 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 423 | |||
| 424 | ps3vram_cache_flush(dev); | ||
| 425 | kfree(priv->cache.tags); | ||
| 426 | } | ||
| 427 | |||
| 428 | static int ps3vram_read(struct ps3_system_bus_device *dev, loff_t from, | ||
| 429 | size_t len, size_t *retlen, u_char *buf) | ||
| 430 | { | ||
| 431 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 432 | unsigned int cached, count; | ||
| 433 | |||
| 434 | dev_dbg(&dev->core, "%s: from=0x%08x len=0x%zx\n", __func__, | ||
| 435 | (unsigned int)from, len); | ||
| 436 | |||
| 437 | if (from >= priv->size) | ||
| 438 | return -EIO; | ||
| 439 | |||
| 440 | if (len > priv->size - from) | ||
| 441 | len = priv->size - from; | ||
| 442 | |||
| 443 | /* Copy from vram to buf */ | ||
| 444 | count = len; | ||
| 445 | while (count) { | ||
| 446 | unsigned int offset, avail; | ||
| 447 | unsigned int entry; | ||
| 448 | |||
| 449 | offset = (unsigned int) (from & (priv->cache.page_size - 1)); | ||
| 450 | avail = priv->cache.page_size - offset; | ||
| 451 | |||
| 452 | mutex_lock(&priv->lock); | ||
| 453 | |||
| 454 | entry = ps3vram_cache_match(dev, from); | ||
| 455 | cached = CACHE_OFFSET + entry * priv->cache.page_size + offset; | ||
| 456 | |||
| 457 | dev_dbg(&dev->core, "%s: from=%08x cached=%08x offset=%08x " | ||
| 458 | "avail=%08x count=%08x\n", __func__, | ||
| 459 | (unsigned int)from, cached, offset, avail, count); | ||
| 460 | |||
| 461 | if (avail > count) | ||
| 462 | avail = count; | ||
| 463 | memcpy(buf, priv->xdr_buf + cached, avail); | ||
| 464 | |||
| 465 | mutex_unlock(&priv->lock); | ||
| 466 | |||
| 467 | buf += avail; | ||
| 468 | count -= avail; | ||
| 469 | from += avail; | ||
| 470 | } | ||
| 471 | |||
| 472 | *retlen = len; | ||
| 473 | return 0; | ||
| 474 | } | ||
| 475 | |||
| 476 | static int ps3vram_write(struct ps3_system_bus_device *dev, loff_t to, | ||
| 477 | size_t len, size_t *retlen, const u_char *buf) | ||
| 478 | { | ||
| 479 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 480 | unsigned int cached, count; | ||
| 481 | |||
| 482 | if (to >= priv->size) | ||
| 483 | return -EIO; | ||
| 484 | |||
| 485 | if (len > priv->size - to) | ||
| 486 | len = priv->size - to; | ||
| 487 | |||
| 488 | /* Copy from buf to vram */ | ||
| 489 | count = len; | ||
| 490 | while (count) { | ||
| 491 | unsigned int offset, avail; | ||
| 492 | unsigned int entry; | ||
| 493 | |||
| 494 | offset = (unsigned int) (to & (priv->cache.page_size - 1)); | ||
| 495 | avail = priv->cache.page_size - offset; | ||
| 496 | |||
| 497 | mutex_lock(&priv->lock); | ||
| 498 | |||
| 499 | entry = ps3vram_cache_match(dev, to); | ||
| 500 | cached = CACHE_OFFSET + entry * priv->cache.page_size + offset; | ||
| 501 | |||
| 502 | dev_dbg(&dev->core, "%s: to=%08x cached=%08x offset=%08x " | ||
| 503 | "avail=%08x count=%08x\n", __func__, (unsigned int)to, | ||
| 504 | cached, offset, avail, count); | ||
| 505 | |||
| 506 | if (avail > count) | ||
| 507 | avail = count; | ||
| 508 | memcpy(priv->xdr_buf + cached, buf, avail); | ||
| 509 | |||
| 510 | priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY; | ||
| 511 | |||
| 512 | mutex_unlock(&priv->lock); | ||
| 513 | |||
| 514 | buf += avail; | ||
| 515 | count -= avail; | ||
| 516 | to += avail; | ||
| 517 | } | ||
| 518 | |||
| 519 | *retlen = len; | ||
| 520 | return 0; | ||
| 521 | } | ||
| 522 | |||
| 523 | static int ps3vram_proc_show(struct seq_file *m, void *v) | ||
| 524 | { | ||
| 525 | struct ps3vram_priv *priv = m->private; | ||
| 526 | |||
| 527 | seq_printf(m, "hit:%u\nmiss:%u\n", priv->cache.hit, priv->cache.miss); | ||
| 528 | return 0; | ||
| 529 | } | ||
| 530 | |||
| 531 | static int ps3vram_proc_open(struct inode *inode, struct file *file) | ||
| 532 | { | ||
| 533 | return single_open(file, ps3vram_proc_show, PDE(inode)->data); | ||
| 534 | } | ||
| 535 | |||
| 536 | static const struct file_operations ps3vram_proc_fops = { | ||
| 537 | .owner = THIS_MODULE, | ||
| 538 | .open = ps3vram_proc_open, | ||
| 539 | .read = seq_read, | ||
| 540 | .llseek = seq_lseek, | ||
| 541 | .release = single_release, | ||
| 542 | }; | ||
| 543 | |||
| 544 | static void __devinit ps3vram_proc_init(struct ps3_system_bus_device *dev) | ||
| 545 | { | ||
| 546 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 547 | struct proc_dir_entry *pde; | ||
| 548 | |||
| 549 | pde = proc_create(DEVICE_NAME, 0444, NULL, &ps3vram_proc_fops); | ||
| 550 | if (!pde) { | ||
| 551 | dev_warn(&dev->core, "failed to create /proc entry\n"); | ||
| 552 | return; | ||
| 553 | } | ||
| 554 | |||
| 555 | pde->owner = THIS_MODULE; | ||
| 556 | pde->data = priv; | ||
| 557 | } | ||
| 558 | |||
| 559 | static int ps3vram_make_request(struct request_queue *q, struct bio *bio) | ||
| 560 | { | ||
| 561 | struct ps3_system_bus_device *dev = q->queuedata; | ||
| 562 | int write = bio_data_dir(bio) == WRITE; | ||
| 563 | const char *op = write ? "write" : "read"; | ||
| 564 | loff_t offset = bio->bi_sector << 9; | ||
| 565 | int error = 0; | ||
| 566 | struct bio_vec *bvec; | ||
| 567 | unsigned int i; | ||
| 568 | |||
| 569 | dev_dbg(&dev->core, "%s\n", __func__); | ||
| 570 | |||
| 571 | bio_for_each_segment(bvec, bio, i) { | ||
| 572 | /* PS3 is ppc64, so we don't handle highmem */ | ||
| 573 | char *ptr = page_address(bvec->bv_page) + bvec->bv_offset; | ||
| 574 | size_t len = bvec->bv_len, retlen; | ||
| 575 | |||
| 576 | dev_dbg(&dev->core, " %s %zu bytes at offset %llu\n", op, | ||
| 577 | len, offset); | ||
| 578 | if (write) | ||
| 579 | error = ps3vram_write(dev, offset, len, &retlen, ptr); | ||
| 580 | else | ||
| 581 | error = ps3vram_read(dev, offset, len, &retlen, ptr); | ||
| 582 | |||
| 583 | if (error) { | ||
| 584 | dev_err(&dev->core, "%s failed\n", op); | ||
| 585 | goto out; | ||
| 586 | } | ||
| 587 | |||
| 588 | if (retlen != len) { | ||
| 589 | dev_err(&dev->core, "Short %s\n", op); | ||
| 590 | goto out; | ||
| 591 | } | ||
| 592 | |||
| 593 | offset += len; | ||
| 594 | } | ||
| 595 | |||
| 596 | dev_dbg(&dev->core, "%s completed\n", op); | ||
| 597 | |||
| 598 | out: | ||
| 599 | bio_endio(bio, error); | ||
| 600 | return 0; | ||
| 601 | } | ||
| 602 | |||
| 603 | static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev) | ||
| 604 | { | ||
| 605 | struct ps3vram_priv *priv; | ||
| 606 | int error, status; | ||
| 607 | struct request_queue *queue; | ||
| 608 | struct gendisk *gendisk; | ||
| 609 | u64 ddr_lpar, ctrl_lpar, info_lpar, reports_lpar, ddr_size, | ||
| 610 | reports_size; | ||
| 611 | char *rest; | ||
| 612 | |||
| 613 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | ||
| 614 | if (!priv) { | ||
| 615 | error = -ENOMEM; | ||
| 616 | goto fail; | ||
| 617 | } | ||
| 618 | |||
| 619 | mutex_init(&priv->lock); | ||
| 620 | dev->core.driver_data = priv; | ||
| 621 | |||
| 622 | priv = dev->core.driver_data; | ||
| 623 | |||
| 624 | /* Allocate XDR buffer (1MiB aligned) */ | ||
| 625 | priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL, | ||
| 626 | get_order(XDR_BUF_SIZE)); | ||
| 627 | if (priv->xdr_buf == NULL) { | ||
| 628 | dev_err(&dev->core, "Could not allocate XDR buffer\n"); | ||
| 629 | error = -ENOMEM; | ||
| 630 | goto fail_free_priv; | ||
| 631 | } | ||
| 632 | |||
| 633 | /* Put FIFO at begginning of XDR buffer */ | ||
| 634 | priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET); | ||
| 635 | priv->fifo_ptr = priv->fifo_base; | ||
| 636 | |||
| 637 | /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */ | ||
| 638 | if (ps3_open_hv_device(dev)) { | ||
| 639 | dev_err(&dev->core, "ps3_open_hv_device failed\n"); | ||
| 640 | error = -EAGAIN; | ||
| 641 | goto out_close_gpu; | ||
| 642 | } | ||
| 643 | |||
| 644 | /* Request memory */ | ||
| 645 | status = -1; | ||
| 646 | ddr_size = ALIGN(memparse(size, &rest), 1024*1024); | ||
| 647 | if (!ddr_size) { | ||
| 648 | dev_err(&dev->core, "Specified size is too small\n"); | ||
| 649 | error = -EINVAL; | ||
| 650 | goto out_close_gpu; | ||
| 651 | } | ||
| 652 | |||
| 653 | while (ddr_size > 0) { | ||
| 654 | status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0, | ||
| 655 | &priv->memory_handle, | ||
| 656 | &ddr_lpar); | ||
| 657 | if (!status) | ||
| 658 | break; | ||
| 659 | ddr_size -= 1024*1024; | ||
| 660 | } | ||
| 661 | if (status) { | ||
| 662 | dev_err(&dev->core, "lv1_gpu_memory_allocate failed %d\n", | ||
| 663 | status); | ||
| 664 | error = -ENOMEM; | ||
| 665 | goto out_free_xdr_buf; | ||
| 666 | } | ||
| 667 | |||
| 668 | /* Request context */ | ||
| 669 | status = lv1_gpu_context_allocate(priv->memory_handle, 0, | ||
| 670 | &priv->context_handle, &ctrl_lpar, | ||
| 671 | &info_lpar, &reports_lpar, | ||
| 672 | &reports_size); | ||
| 673 | if (status) { | ||
| 674 | dev_err(&dev->core, "lv1_gpu_context_allocate failed %d\n", | ||
| 675 | status); | ||
| 676 | error = -ENOMEM; | ||
| 677 | goto out_free_memory; | ||
| 678 | } | ||
| 679 | |||
| 680 | /* Map XDR buffer to RSX */ | ||
| 681 | status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, | ||
| 682 | ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)), | ||
| 683 | XDR_BUF_SIZE, 0); | ||
| 684 | if (status) { | ||
| 685 | dev_err(&dev->core, "lv1_gpu_context_iomap failed %d\n", | ||
| 686 | status); | ||
| 687 | error = -ENOMEM; | ||
| 688 | goto out_free_context; | ||
| 689 | } | ||
| 690 | |||
| 691 | priv->ddr_base = ioremap_flags(ddr_lpar, ddr_size, _PAGE_NO_CACHE); | ||
| 692 | |||
| 693 | if (!priv->ddr_base) { | ||
| 694 | dev_err(&dev->core, "ioremap DDR failed\n"); | ||
| 695 | error = -ENOMEM; | ||
| 696 | goto out_free_context; | ||
| 697 | } | ||
| 698 | |||
| 699 | priv->ctrl = ioremap(ctrl_lpar, 64 * 1024); | ||
| 700 | if (!priv->ctrl) { | ||
| 701 | dev_err(&dev->core, "ioremap CTRL failed\n"); | ||
| 702 | error = -ENOMEM; | ||
| 703 | goto out_unmap_vram; | ||
| 704 | } | ||
| 705 | |||
| 706 | priv->reports = ioremap(reports_lpar, reports_size); | ||
| 707 | if (!priv->reports) { | ||
| 708 | dev_err(&dev->core, "ioremap REPORTS failed\n"); | ||
| 709 | error = -ENOMEM; | ||
| 710 | goto out_unmap_ctrl; | ||
| 711 | } | ||
| 712 | |||
| 713 | mutex_lock(&ps3_gpu_mutex); | ||
| 714 | ps3vram_init_ring(dev); | ||
| 715 | mutex_unlock(&ps3_gpu_mutex); | ||
| 716 | |||
| 717 | priv->size = ddr_size; | ||
| 718 | |||
| 719 | ps3vram_bind(dev); | ||
| 720 | |||
| 721 | mutex_lock(&ps3_gpu_mutex); | ||
| 722 | error = ps3vram_wait_ring(dev, 100); | ||
| 723 | mutex_unlock(&ps3_gpu_mutex); | ||
| 724 | if (error < 0) { | ||
| 725 | dev_err(&dev->core, "Failed to initialize channels\n"); | ||
| 726 | error = -ETIMEDOUT; | ||
| 727 | goto out_unmap_reports; | ||
| 728 | } | ||
| 729 | |||
| 730 | ps3vram_cache_init(dev); | ||
| 731 | ps3vram_proc_init(dev); | ||
| 732 | |||
| 733 | queue = blk_alloc_queue(GFP_KERNEL); | ||
| 734 | if (!queue) { | ||
| 735 | dev_err(&dev->core, "blk_alloc_queue failed\n"); | ||
| 736 | error = -ENOMEM; | ||
| 737 | goto out_cache_cleanup; | ||
| 738 | } | ||
| 739 | |||
| 740 | priv->queue = queue; | ||
| 741 | queue->queuedata = dev; | ||
| 742 | blk_queue_make_request(queue, ps3vram_make_request); | ||
| 743 | blk_queue_max_phys_segments(queue, MAX_PHYS_SEGMENTS); | ||
| 744 | blk_queue_max_hw_segments(queue, MAX_HW_SEGMENTS); | ||
| 745 | blk_queue_max_segment_size(queue, MAX_SEGMENT_SIZE); | ||
| 746 | blk_queue_max_sectors(queue, SAFE_MAX_SECTORS); | ||
| 747 | |||
| 748 | gendisk = alloc_disk(1); | ||
| 749 | if (!gendisk) { | ||
| 750 | dev_err(&dev->core, "alloc_disk failed\n"); | ||
| 751 | error = -ENOMEM; | ||
| 752 | goto fail_cleanup_queue; | ||
| 753 | } | ||
| 754 | |||
| 755 | priv->gendisk = gendisk; | ||
| 756 | gendisk->major = ps3vram_major; | ||
| 757 | gendisk->first_minor = 0; | ||
| 758 | gendisk->fops = &ps3vram_fops; | ||
| 759 | gendisk->queue = queue; | ||
| 760 | gendisk->private_data = dev; | ||
| 761 | gendisk->driverfs_dev = &dev->core; | ||
| 762 | strlcpy(gendisk->disk_name, DEVICE_NAME, sizeof(gendisk->disk_name)); | ||
| 763 | set_capacity(gendisk, priv->size >> 9); | ||
| 764 | |||
| 765 | dev_info(&dev->core, "%s: Using %lu MiB of GPU memory\n", | ||
| 766 | gendisk->disk_name, get_capacity(gendisk) >> 11); | ||
| 767 | |||
| 768 | add_disk(gendisk); | ||
| 769 | return 0; | ||
| 770 | |||
| 771 | fail_cleanup_queue: | ||
| 772 | blk_cleanup_queue(queue); | ||
| 773 | out_cache_cleanup: | ||
| 774 | remove_proc_entry(DEVICE_NAME, NULL); | ||
| 775 | ps3vram_cache_cleanup(dev); | ||
| 776 | out_unmap_reports: | ||
| 777 | iounmap(priv->reports); | ||
| 778 | out_unmap_ctrl: | ||
| 779 | iounmap(priv->ctrl); | ||
| 780 | out_unmap_vram: | ||
| 781 | iounmap(priv->ddr_base); | ||
| 782 | out_free_context: | ||
| 783 | lv1_gpu_context_free(priv->context_handle); | ||
| 784 | out_free_memory: | ||
| 785 | lv1_gpu_memory_free(priv->memory_handle); | ||
| 786 | out_close_gpu: | ||
| 787 | ps3_close_hv_device(dev); | ||
| 788 | out_free_xdr_buf: | ||
| 789 | free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE)); | ||
| 790 | fail_free_priv: | ||
| 791 | kfree(priv); | ||
| 792 | dev->core.driver_data = NULL; | ||
| 793 | fail: | ||
| 794 | return error; | ||
| 795 | } | ||
| 796 | |||
| 797 | static int ps3vram_remove(struct ps3_system_bus_device *dev) | ||
| 798 | { | ||
| 799 | struct ps3vram_priv *priv = dev->core.driver_data; | ||
| 800 | |||
| 801 | del_gendisk(priv->gendisk); | ||
| 802 | put_disk(priv->gendisk); | ||
| 803 | blk_cleanup_queue(priv->queue); | ||
| 804 | remove_proc_entry(DEVICE_NAME, NULL); | ||
| 805 | ps3vram_cache_cleanup(dev); | ||
| 806 | iounmap(priv->reports); | ||
| 807 | iounmap(priv->ctrl); | ||
| 808 | iounmap(priv->ddr_base); | ||
| 809 | lv1_gpu_context_free(priv->context_handle); | ||
| 810 | lv1_gpu_memory_free(priv->memory_handle); | ||
| 811 | ps3_close_hv_device(dev); | ||
| 812 | free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE)); | ||
| 813 | kfree(priv); | ||
| 814 | dev->core.driver_data = NULL; | ||
| 815 | return 0; | ||
| 816 | } | ||
| 817 | |||
| 818 | static struct ps3_system_bus_driver ps3vram = { | ||
| 819 | .match_id = PS3_MATCH_ID_GPU, | ||
| 820 | .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK, | ||
| 821 | .core.name = DEVICE_NAME, | ||
| 822 | .core.owner = THIS_MODULE, | ||
| 823 | .probe = ps3vram_probe, | ||
| 824 | .remove = ps3vram_remove, | ||
| 825 | .shutdown = ps3vram_remove, | ||
| 826 | }; | ||
| 827 | |||
| 828 | |||
| 829 | static int __init ps3vram_init(void) | ||
| 830 | { | ||
| 831 | int error; | ||
| 832 | |||
| 833 | if (!firmware_has_feature(FW_FEATURE_PS3_LV1)) | ||
| 834 | return -ENODEV; | ||
| 835 | |||
| 836 | error = register_blkdev(0, DEVICE_NAME); | ||
| 837 | if (error <= 0) { | ||
| 838 | pr_err("%s: register_blkdev failed %d\n", DEVICE_NAME, error); | ||
| 839 | return error; | ||
| 840 | } | ||
| 841 | ps3vram_major = error; | ||
| 842 | |||
| 843 | pr_info("%s: registered block device major %d\n", DEVICE_NAME, | ||
| 844 | ps3vram_major); | ||
| 845 | |||
| 846 | error = ps3_system_bus_driver_register(&ps3vram); | ||
| 847 | if (error) | ||
| 848 | unregister_blkdev(ps3vram_major, DEVICE_NAME); | ||
| 849 | |||
| 850 | return error; | ||
| 851 | } | ||
| 852 | |||
| 853 | static void __exit ps3vram_exit(void) | ||
| 854 | { | ||
| 855 | ps3_system_bus_driver_unregister(&ps3vram); | ||
| 856 | unregister_blkdev(ps3vram_major, DEVICE_NAME); | ||
| 857 | } | ||
| 858 | |||
| 859 | module_init(ps3vram_init); | ||
| 860 | module_exit(ps3vram_exit); | ||
| 861 | |||
| 862 | MODULE_LICENSE("GPL"); | ||
| 863 | MODULE_DESCRIPTION("PS3 Video RAM Storage Driver"); | ||
| 864 | MODULE_AUTHOR("Sony Corporation"); | ||
| 865 | MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK); | ||
diff --git a/drivers/block/xen-blkfront.c b/drivers/block/xen-blkfront.c index b6c8ce254359..8f905089b72b 100644 --- a/drivers/block/xen-blkfront.c +++ b/drivers/block/xen-blkfront.c | |||
| @@ -977,6 +977,8 @@ static void backend_changed(struct xenbus_device *dev, | |||
| 977 | break; | 977 | break; |
| 978 | 978 | ||
| 979 | case XenbusStateClosing: | 979 | case XenbusStateClosing: |
| 980 | if (info->gd == NULL) | ||
| 981 | xenbus_dev_fatal(dev, -ENODEV, "gd is NULL"); | ||
| 980 | bd = bdget_disk(info->gd, 0); | 982 | bd = bdget_disk(info->gd, 0); |
| 981 | if (bd == NULL) | 983 | if (bd == NULL) |
| 982 | xenbus_dev_fatal(dev, -ENODEV, "bdget failed"); | 984 | xenbus_dev_fatal(dev, -ENODEV, "bdget failed"); |
diff --git a/drivers/block/xsysace.c b/drivers/block/xsysace.c index 381d686fc1a3..119be3442f28 100644 --- a/drivers/block/xsysace.c +++ b/drivers/block/xsysace.c | |||
| @@ -489,6 +489,28 @@ static void ace_fsm_dostate(struct ace_device *ace) | |||
| 489 | ace->fsm_state, ace->id_req_count); | 489 | ace->fsm_state, ace->id_req_count); |
| 490 | #endif | 490 | #endif |
| 491 | 491 | ||
| 492 | /* Verify that there is actually a CF in the slot. If not, then | ||
| 493 | * bail out back to the idle state and wake up all the waiters */ | ||
| 494 | status = ace_in32(ace, ACE_STATUS); | ||
| 495 | if ((status & ACE_STATUS_CFDETECT) == 0) { | ||
| 496 | ace->fsm_state = ACE_FSM_STATE_IDLE; | ||
| 497 | ace->media_change = 1; | ||
| 498 | set_capacity(ace->gd, 0); | ||
| 499 | dev_info(ace->dev, "No CF in slot\n"); | ||
| 500 | |||
| 501 | /* Drop all pending requests */ | ||
| 502 | while ((req = elv_next_request(ace->queue)) != NULL) | ||
| 503 | end_request(req, 0); | ||
| 504 | |||
| 505 | /* Drop back to IDLE state and notify waiters */ | ||
| 506 | ace->fsm_state = ACE_FSM_STATE_IDLE; | ||
| 507 | ace->id_result = -EIO; | ||
| 508 | while (ace->id_req_count) { | ||
| 509 | complete(&ace->id_completion); | ||
| 510 | ace->id_req_count--; | ||
| 511 | } | ||
| 512 | } | ||
| 513 | |||
| 492 | switch (ace->fsm_state) { | 514 | switch (ace->fsm_state) { |
| 493 | case ACE_FSM_STATE_IDLE: | 515 | case ACE_FSM_STATE_IDLE: |
| 494 | /* See if there is anything to do */ | 516 | /* See if there is anything to do */ |
diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c index 52f4361eb6e4..d765afda9c2a 100644 --- a/drivers/char/agp/amd64-agp.c +++ b/drivers/char/agp/amd64-agp.c | |||
| @@ -271,15 +271,15 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, | |||
| 271 | nb_order = (nb_order >> 1) & 7; | 271 | nb_order = (nb_order >> 1) & 7; |
| 272 | pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base); | 272 | pci_read_config_dword(nb, AMD64_GARTAPERTUREBASE, &nb_base); |
| 273 | nb_aper = nb_base << 25; | 273 | nb_aper = nb_base << 25; |
| 274 | if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) { | ||
| 275 | return 0; | ||
| 276 | } | ||
| 277 | 274 | ||
| 278 | /* Northbridge seems to contain crap. Try the AGP bridge. */ | 275 | /* Northbridge seems to contain crap. Try the AGP bridge. */ |
| 279 | 276 | ||
| 280 | pci_read_config_word(agp, cap+0x14, &apsize); | 277 | pci_read_config_word(agp, cap+0x14, &apsize); |
| 281 | if (apsize == 0xffff) | 278 | if (apsize == 0xffff) { |
| 279 | if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) | ||
| 280 | return 0; | ||
| 282 | return -1; | 281 | return -1; |
| 282 | } | ||
| 283 | 283 | ||
| 284 | apsize &= 0xfff; | 284 | apsize &= 0xfff; |
| 285 | /* Some BIOS use weird encodings not in the AGPv3 table. */ | 285 | /* Some BIOS use weird encodings not in the AGPv3 table. */ |
| @@ -301,6 +301,11 @@ static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp, | |||
| 301 | order = nb_order; | 301 | order = nb_order; |
| 302 | } | 302 | } |
| 303 | 303 | ||
| 304 | if (nb_order >= order) { | ||
| 305 | if (agp_aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) | ||
| 306 | return 0; | ||
| 307 | } | ||
| 308 | |||
| 304 | dev_info(&agp->dev, "aperture from AGP @ %Lx size %u MB\n", | 309 | dev_info(&agp->dev, "aperture from AGP @ %Lx size %u MB\n", |
| 305 | aper, 32 << order); | 310 | aper, 32 << order); |
| 306 | if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order)) | 311 | if (order < 0 || !agp_aperture_valid(aper, (32*1024*1024)<<order)) |
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index c7714185f831..4373adb2119a 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c | |||
| @@ -633,13 +633,15 @@ static void intel_i830_init_gtt_entries(void) | |||
| 633 | break; | 633 | break; |
| 634 | } | 634 | } |
| 635 | } | 635 | } |
| 636 | if (gtt_entries > 0) | 636 | if (gtt_entries > 0) { |
| 637 | dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n", | 637 | dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n", |
| 638 | gtt_entries / KB(1), local ? "local" : "stolen"); | 638 | gtt_entries / KB(1), local ? "local" : "stolen"); |
| 639 | else | 639 | gtt_entries /= KB(4); |
| 640 | } else { | ||
| 640 | dev_info(&agp_bridge->dev->dev, | 641 | dev_info(&agp_bridge->dev->dev, |
| 641 | "no pre-allocated video memory detected\n"); | 642 | "no pre-allocated video memory detected\n"); |
| 642 | gtt_entries /= KB(4); | 643 | gtt_entries = 0; |
| 644 | } | ||
| 643 | 645 | ||
| 644 | intel_private.gtt_entries = gtt_entries; | 646 | intel_private.gtt_entries = gtt_entries; |
| 645 | } | 647 | } |
diff --git a/drivers/char/agp/parisc-agp.c b/drivers/char/agp/parisc-agp.c index db60539bf67a..699e3422ad93 100644 --- a/drivers/char/agp/parisc-agp.c +++ b/drivers/char/agp/parisc-agp.c | |||
| @@ -359,9 +359,16 @@ fail: | |||
| 359 | return error; | 359 | return error; |
| 360 | } | 360 | } |
| 361 | 361 | ||
| 362 | static struct device *next_device(struct klist_iter *i) { | 362 | static int |
| 363 | struct klist_node * n = klist_next(i); | 363 | find_quicksilver(struct device *dev, void *data) |
| 364 | return n ? container_of(n, struct device, knode_parent) : NULL; | 364 | { |
| 365 | struct parisc_device **lba = data; | ||
| 366 | struct parisc_device *padev = to_parisc_device(dev); | ||
| 367 | |||
| 368 | if (IS_QUICKSILVER(padev)) | ||
| 369 | *lba = padev; | ||
| 370 | |||
| 371 | return 0; | ||
| 365 | } | 372 | } |
| 366 | 373 | ||
| 367 | static int | 374 | static int |
| @@ -372,8 +379,6 @@ parisc_agp_init(void) | |||
| 372 | int err = -1; | 379 | int err = -1; |
| 373 | struct parisc_device *sba = NULL, *lba = NULL; | 380 | struct parisc_device *sba = NULL, *lba = NULL; |
| 374 | struct lba_device *lbadev = NULL; | 381 | struct lba_device *lbadev = NULL; |
| 375 | struct device *dev = NULL; | ||
| 376 | struct klist_iter i; | ||
| 377 | 382 | ||
| 378 | if (!sba_list) | 383 | if (!sba_list) |
| 379 | goto out; | 384 | goto out; |
| @@ -386,13 +391,7 @@ parisc_agp_init(void) | |||
| 386 | } | 391 | } |
| 387 | 392 | ||
| 388 | /* Now search our Pluto for our precious AGP device... */ | 393 | /* Now search our Pluto for our precious AGP device... */ |
| 389 | klist_iter_init(&sba->dev.klist_children, &i); | 394 | device_for_each_child(&sba->dev, &lba, find_quicksilver); |
| 390 | while ((dev = next_device(&i))) { | ||
| 391 | struct parisc_device *padev = to_parisc_device(dev); | ||
| 392 | if (IS_QUICKSILVER(padev)) | ||
| 393 | lba = padev; | ||
| 394 | } | ||
| 395 | klist_iter_exit(&i); | ||
| 396 | 395 | ||
| 397 | if (!lba) { | 396 | if (!lba) { |
| 398 | printk(KERN_INFO DRVPFX "No AGP devices found.\n"); | 397 | printk(KERN_INFO DRVPFX "No AGP devices found.\n"); |
diff --git a/drivers/char/hvcs.c b/drivers/char/hvcs.c index 6e6eb445d374..c76bccf5354d 100644 --- a/drivers/char/hvcs.c +++ b/drivers/char/hvcs.c | |||
| @@ -1139,15 +1139,6 @@ static int hvcs_open(struct tty_struct *tty, struct file *filp) | |||
| 1139 | hvcsd->tty = tty; | 1139 | hvcsd->tty = tty; |
| 1140 | tty->driver_data = hvcsd; | 1140 | tty->driver_data = hvcsd; |
| 1141 | 1141 | ||
| 1142 | /* | ||
| 1143 | * Set this driver to low latency so that we actually have a chance at | ||
| 1144 | * catching a throttled TTY after we flip_buffer_push. Otherwise the | ||
| 1145 | * flush_to_async may not execute until after the kernel_thread has | ||
| 1146 | * yielded and resumed the next flip_buffer_push resulting in data | ||
| 1147 | * loss. | ||
| 1148 | */ | ||
| 1149 | tty->low_latency = 1; | ||
| 1150 | |||
| 1151 | memset(&hvcsd->buffer[0], 0x00, HVCS_BUFF_LEN); | 1142 | memset(&hvcsd->buffer[0], 0x00, HVCS_BUFF_LEN); |
| 1152 | 1143 | ||
| 1153 | /* | 1144 | /* |
diff --git a/drivers/char/hvsi.c b/drivers/char/hvsi.c index 406f8742a260..2989056a9e39 100644 --- a/drivers/char/hvsi.c +++ b/drivers/char/hvsi.c | |||
| @@ -810,7 +810,6 @@ static int hvsi_open(struct tty_struct *tty, struct file *filp) | |||
| 810 | hp = &hvsi_ports[line]; | 810 | hp = &hvsi_ports[line]; |
| 811 | 811 | ||
| 812 | tty->driver_data = hp; | 812 | tty->driver_data = hp; |
| 813 | tty->low_latency = 1; /* avoid throttle/tty_flip_buffer_push race */ | ||
| 814 | 813 | ||
| 815 | mb(); | 814 | mb(); |
| 816 | if (hp->state == HVSI_FSP_DIED) | 815 | if (hp->state == HVSI_FSP_DIED) |
diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c index ba68a4671cb5..538313f9e7ac 100644 --- a/drivers/char/hw_random/omap-rng.c +++ b/drivers/char/hw_random/omap-rng.c | |||
| @@ -102,7 +102,7 @@ static int __init omap_rng_probe(struct platform_device *pdev) | |||
| 102 | return -EBUSY; | 102 | return -EBUSY; |
| 103 | 103 | ||
| 104 | if (cpu_is_omap24xx()) { | 104 | if (cpu_is_omap24xx()) { |
| 105 | rng_ick = clk_get(&pdev->dev, "rng_ick"); | 105 | rng_ick = clk_get(&pdev->dev, "ick"); |
| 106 | if (IS_ERR(rng_ick)) { | 106 | if (IS_ERR(rng_ick)) { |
| 107 | dev_err(&pdev->dev, "Could not get rng_ick\n"); | 107 | dev_err(&pdev->dev, "Could not get rng_ick\n"); |
| 108 | ret = PTR_ERR(rng_ick); | 108 | ret = PTR_ERR(rng_ick); |
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index b55cb67435bd..d6daf3c507d3 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c | |||
| @@ -754,11 +754,6 @@ static struct kobj_type ktype_cpufreq = { | |||
| 754 | .release = cpufreq_sysfs_release, | 754 | .release = cpufreq_sysfs_release, |
| 755 | }; | 755 | }; |
| 756 | 756 | ||
| 757 | static struct kobj_type ktype_empty_cpufreq = { | ||
| 758 | .sysfs_ops = &sysfs_ops, | ||
| 759 | .release = cpufreq_sysfs_release, | ||
| 760 | }; | ||
| 761 | |||
| 762 | 757 | ||
| 763 | /** | 758 | /** |
| 764 | * cpufreq_add_dev - add a CPU device | 759 | * cpufreq_add_dev - add a CPU device |
| @@ -892,36 +887,26 @@ static int cpufreq_add_dev(struct sys_device *sys_dev) | |||
| 892 | memcpy(&new_policy, policy, sizeof(struct cpufreq_policy)); | 887 | memcpy(&new_policy, policy, sizeof(struct cpufreq_policy)); |
| 893 | 888 | ||
| 894 | /* prepare interface data */ | 889 | /* prepare interface data */ |
| 895 | if (!cpufreq_driver->hide_interface) { | 890 | ret = kobject_init_and_add(&policy->kobj, &ktype_cpufreq, &sys_dev->kobj, |
| 896 | ret = kobject_init_and_add(&policy->kobj, &ktype_cpufreq, | 891 | "cpufreq"); |
| 897 | &sys_dev->kobj, "cpufreq"); | 892 | if (ret) |
| 893 | goto err_out_driver_exit; | ||
| 894 | |||
| 895 | /* set up files for this cpu device */ | ||
| 896 | drv_attr = cpufreq_driver->attr; | ||
| 897 | while ((drv_attr) && (*drv_attr)) { | ||
| 898 | ret = sysfs_create_file(&policy->kobj, &((*drv_attr)->attr)); | ||
| 898 | if (ret) | 899 | if (ret) |
| 899 | goto err_out_driver_exit; | 900 | goto err_out_driver_exit; |
| 900 | 901 | drv_attr++; | |
| 901 | /* set up files for this cpu device */ | 902 | } |
| 902 | drv_attr = cpufreq_driver->attr; | 903 | if (cpufreq_driver->get) { |
| 903 | while ((drv_attr) && (*drv_attr)) { | 904 | ret = sysfs_create_file(&policy->kobj, &cpuinfo_cur_freq.attr); |
| 904 | ret = sysfs_create_file(&policy->kobj, | 905 | if (ret) |
| 905 | &((*drv_attr)->attr)); | 906 | goto err_out_driver_exit; |
| 906 | if (ret) | 907 | } |
| 907 | goto err_out_driver_exit; | 908 | if (cpufreq_driver->target) { |
| 908 | drv_attr++; | 909 | ret = sysfs_create_file(&policy->kobj, &scaling_cur_freq.attr); |
| 909 | } | ||
| 910 | if (cpufreq_driver->get) { | ||
| 911 | ret = sysfs_create_file(&policy->kobj, | ||
| 912 | &cpuinfo_cur_freq.attr); | ||
| 913 | if (ret) | ||
| 914 | goto err_out_driver_exit; | ||
| 915 | } | ||
| 916 | if (cpufreq_driver->target) { | ||
| 917 | ret = sysfs_create_file(&policy->kobj, | ||
| 918 | &scaling_cur_freq.attr); | ||
| 919 | if (ret) | ||
| 920 | goto err_out_driver_exit; | ||
| 921 | } | ||
| 922 | } else { | ||
| 923 | ret = kobject_init_and_add(&policy->kobj, &ktype_empty_cpufreq, | ||
| 924 | &sys_dev->kobj, "cpufreq"); | ||
| 925 | if (ret) | 910 | if (ret) |
| 926 | goto err_out_driver_exit; | 911 | goto err_out_driver_exit; |
| 927 | } | 912 | } |
diff --git a/drivers/dca/dca-core.c b/drivers/dca/dca-core.c index 33bd75347518..25b743abfb59 100644 --- a/drivers/dca/dca-core.c +++ b/drivers/dca/dca-core.c | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright(c) 2007 Intel Corporation. All rights reserved. | 2 | * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved. |
| 3 | * | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms of the GNU General Public License as published by the Free | 5 | * under the terms of the GNU General Public License as published by the Free |
diff --git a/drivers/dca/dca-sysfs.c b/drivers/dca/dca-sysfs.c index bb538b9690e0..ee916c9857ee 100644 --- a/drivers/dca/dca-sysfs.c +++ b/drivers/dca/dca-sysfs.c | |||
| @@ -1,3 +1,24 @@ | |||
| 1 | /* | ||
| 2 | * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it | ||
| 5 | * under the terms of the GNU General Public License as published by the Free | ||
| 6 | * Software Foundation; either version 2 of the License, or (at your option) | ||
| 7 | * any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along with | ||
| 15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | ||
| 16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 17 | * | ||
| 18 | * The full GNU General Public License is included in this distribution in the | ||
| 19 | * file called COPYING. | ||
| 20 | */ | ||
| 21 | |||
| 1 | #include <linux/kernel.h> | 22 | #include <linux/kernel.h> |
| 2 | #include <linux/spinlock.h> | 23 | #include <linux/spinlock.h> |
| 3 | #include <linux/device.h> | 24 | #include <linux/device.h> |
diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c index 732fa1ec36ab..e190d8b30700 100644 --- a/drivers/dma/dmatest.c +++ b/drivers/dma/dmatest.c | |||
| @@ -430,13 +430,15 @@ late_initcall(dmatest_init); | |||
| 430 | static void __exit dmatest_exit(void) | 430 | static void __exit dmatest_exit(void) |
| 431 | { | 431 | { |
| 432 | struct dmatest_chan *dtc, *_dtc; | 432 | struct dmatest_chan *dtc, *_dtc; |
| 433 | struct dma_chan *chan; | ||
| 433 | 434 | ||
| 434 | list_for_each_entry_safe(dtc, _dtc, &dmatest_channels, node) { | 435 | list_for_each_entry_safe(dtc, _dtc, &dmatest_channels, node) { |
| 435 | list_del(&dtc->node); | 436 | list_del(&dtc->node); |
| 437 | chan = dtc->chan; | ||
| 436 | dmatest_cleanup_channel(dtc); | 438 | dmatest_cleanup_channel(dtc); |
| 437 | pr_debug("dmatest: dropped channel %s\n", | 439 | pr_debug("dmatest: dropped channel %s\n", |
| 438 | dma_chan_name(dtc->chan)); | 440 | dma_chan_name(chan)); |
| 439 | dma_release_channel(dtc->chan); | 441 | dma_release_channel(chan); |
| 440 | } | 442 | } |
| 441 | } | 443 | } |
| 442 | module_exit(dmatest_exit); | 444 | module_exit(dmatest_exit); |
diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c index 70126a606239..86d6da47f558 100644 --- a/drivers/dma/fsldma.c +++ b/drivers/dma/fsldma.c | |||
| @@ -158,7 +158,8 @@ static void dma_start(struct fsl_dma_chan *fsl_chan) | |||
| 158 | 158 | ||
| 159 | static void dma_halt(struct fsl_dma_chan *fsl_chan) | 159 | static void dma_halt(struct fsl_dma_chan *fsl_chan) |
| 160 | { | 160 | { |
| 161 | int i = 0; | 161 | int i; |
| 162 | |||
| 162 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, | 163 | DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, |
| 163 | DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA, | 164 | DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA, |
| 164 | 32); | 165 | 32); |
| @@ -166,8 +167,11 @@ static void dma_halt(struct fsl_dma_chan *fsl_chan) | |||
| 166 | DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS | 167 | DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS |
| 167 | | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32); | 168 | | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32); |
| 168 | 169 | ||
| 169 | while (!dma_is_idle(fsl_chan) && (i++ < 100)) | 170 | for (i = 0; i < 100; i++) { |
| 171 | if (dma_is_idle(fsl_chan)) | ||
| 172 | break; | ||
| 170 | udelay(10); | 173 | udelay(10); |
| 174 | } | ||
| 171 | if (i >= 100 && !dma_is_idle(fsl_chan)) | 175 | if (i >= 100 && !dma_is_idle(fsl_chan)) |
| 172 | dev_err(fsl_chan->dev, "DMA halt timeout!\n"); | 176 | dev_err(fsl_chan->dev, "DMA halt timeout!\n"); |
| 173 | } | 177 | } |
diff --git a/drivers/dma/ioat.c b/drivers/dma/ioat.c index 4105d6575b64..ed83dd9df192 100644 --- a/drivers/dma/ioat.c +++ b/drivers/dma/ioat.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Intel I/OAT DMA Linux driver | 2 | * Intel I/OAT DMA Linux driver |
| 3 | * Copyright(c) 2007 Intel Corporation. | 3 | * Copyright(c) 2007 - 2009 Intel Corporation. |
| 4 | * | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it | 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, | 6 | * under the terms and conditions of the GNU General Public License, |
diff --git a/drivers/dma/ioat_dca.c b/drivers/dma/ioat_dca.c index 6cf622da0286..c012a1e15043 100644 --- a/drivers/dma/ioat_dca.c +++ b/drivers/dma/ioat_dca.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Intel I/OAT DMA Linux driver | 2 | * Intel I/OAT DMA Linux driver |
| 3 | * Copyright(c) 2007 Intel Corporation. | 3 | * Copyright(c) 2007 - 2009 Intel Corporation. |
| 4 | * | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it | 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, | 6 | * under the terms and conditions of the GNU General Public License, |
| @@ -49,6 +49,23 @@ | |||
| 49 | 49 | ||
| 50 | #define DCA_TAG_MAP_MASK 0xDF | 50 | #define DCA_TAG_MAP_MASK 0xDF |
| 51 | 51 | ||
| 52 | /* expected tag map bytes for I/OAT ver.2 */ | ||
| 53 | #define DCA2_TAG_MAP_BYTE0 0x80 | ||
| 54 | #define DCA2_TAG_MAP_BYTE1 0x0 | ||
| 55 | #define DCA2_TAG_MAP_BYTE2 0x81 | ||
| 56 | #define DCA2_TAG_MAP_BYTE3 0x82 | ||
| 57 | #define DCA2_TAG_MAP_BYTE4 0x82 | ||
| 58 | |||
| 59 | /* verify if tag map matches expected values */ | ||
| 60 | static inline int dca2_tag_map_valid(u8 *tag_map) | ||
| 61 | { | ||
| 62 | return ((tag_map[0] == DCA2_TAG_MAP_BYTE0) && | ||
| 63 | (tag_map[1] == DCA2_TAG_MAP_BYTE1) && | ||
| 64 | (tag_map[2] == DCA2_TAG_MAP_BYTE2) && | ||
| 65 | (tag_map[3] == DCA2_TAG_MAP_BYTE3) && | ||
| 66 | (tag_map[4] == DCA2_TAG_MAP_BYTE4)); | ||
| 67 | } | ||
| 68 | |||
| 52 | /* | 69 | /* |
| 53 | * "Legacy" DCA systems do not implement the DCA register set in the | 70 | * "Legacy" DCA systems do not implement the DCA register set in the |
| 54 | * I/OAT device. Software needs direct support for their tag mappings. | 71 | * I/OAT device. Software needs direct support for their tag mappings. |
| @@ -452,6 +469,13 @@ struct dca_provider *ioat2_dca_init(struct pci_dev *pdev, void __iomem *iobase) | |||
| 452 | ioatdca->tag_map[i] = 0; | 469 | ioatdca->tag_map[i] = 0; |
| 453 | } | 470 | } |
| 454 | 471 | ||
| 472 | if (!dca2_tag_map_valid(ioatdca->tag_map)) { | ||
| 473 | dev_err(&pdev->dev, "APICID_TAG_MAP set incorrectly by BIOS, " | ||
| 474 | "disabling DCA\n"); | ||
| 475 | free_dca_provider(dca); | ||
| 476 | return NULL; | ||
| 477 | } | ||
| 478 | |||
| 455 | err = register_dca_provider(dca, &pdev->dev); | 479 | err = register_dca_provider(dca, &pdev->dev); |
| 456 | if (err) { | 480 | if (err) { |
| 457 | free_dca_provider(dca); | 481 | free_dca_provider(dca); |
diff --git a/drivers/dma/ioat_dma.c b/drivers/dma/ioat_dma.c index b3759c4b6536..5905cd36bcd2 100644 --- a/drivers/dma/ioat_dma.c +++ b/drivers/dma/ioat_dma.c | |||
| @@ -1,6 +1,6 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Intel I/OAT DMA Linux driver | 2 | * Intel I/OAT DMA Linux driver |
| 3 | * Copyright(c) 2004 - 2007 Intel Corporation. | 3 | * Copyright(c) 2004 - 2009 Intel Corporation. |
| 4 | * | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it | 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, | 6 | * under the terms and conditions of the GNU General Public License, |
| @@ -189,11 +189,13 @@ static int ioat_dma_enumerate_channels(struct ioatdma_device *device) | |||
| 189 | ioat_chan->xfercap = xfercap; | 189 | ioat_chan->xfercap = xfercap; |
| 190 | ioat_chan->desccount = 0; | 190 | ioat_chan->desccount = 0; |
| 191 | INIT_DELAYED_WORK(&ioat_chan->work, ioat_dma_chan_reset_part2); | 191 | INIT_DELAYED_WORK(&ioat_chan->work, ioat_dma_chan_reset_part2); |
| 192 | if (ioat_chan->device->version != IOAT_VER_1_2) { | 192 | if (ioat_chan->device->version == IOAT_VER_2_0) |
| 193 | writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | 193 | writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | |
| 194 | | IOAT_DMA_DCA_ANY_CPU, | 194 | IOAT_DMA_DCA_ANY_CPU, |
| 195 | ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); | 195 | ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); |
| 196 | } | 196 | else if (ioat_chan->device->version == IOAT_VER_3_0) |
| 197 | writel(IOAT_DMA_DCA_ANY_CPU, | ||
| 198 | ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); | ||
| 197 | spin_lock_init(&ioat_chan->cleanup_lock); | 199 | spin_lock_init(&ioat_chan->cleanup_lock); |
| 198 | spin_lock_init(&ioat_chan->desc_lock); | 200 | spin_lock_init(&ioat_chan->desc_lock); |
| 199 | INIT_LIST_HEAD(&ioat_chan->free_desc); | 201 | INIT_LIST_HEAD(&ioat_chan->free_desc); |
| @@ -1169,9 +1171,8 @@ static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan) | |||
| 1169 | * up if the client is done with the descriptor | 1171 | * up if the client is done with the descriptor |
| 1170 | */ | 1172 | */ |
| 1171 | if (async_tx_test_ack(&desc->async_tx)) { | 1173 | if (async_tx_test_ack(&desc->async_tx)) { |
| 1172 | list_del(&desc->node); | 1174 | list_move_tail(&desc->node, |
| 1173 | list_add_tail(&desc->node, | 1175 | &ioat_chan->free_desc); |
| 1174 | &ioat_chan->free_desc); | ||
| 1175 | } else | 1176 | } else |
| 1176 | desc->async_tx.cookie = 0; | 1177 | desc->async_tx.cookie = 0; |
| 1177 | } else { | 1178 | } else { |
| @@ -1362,6 +1363,7 @@ static int ioat_dma_self_test(struct ioatdma_device *device) | |||
| 1362 | dma_cookie_t cookie; | 1363 | dma_cookie_t cookie; |
| 1363 | int err = 0; | 1364 | int err = 0; |
| 1364 | struct completion cmp; | 1365 | struct completion cmp; |
| 1366 | unsigned long tmo; | ||
| 1365 | 1367 | ||
| 1366 | src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); | 1368 | src = kzalloc(sizeof(u8) * IOAT_TEST_SIZE, GFP_KERNEL); |
| 1367 | if (!src) | 1369 | if (!src) |
| @@ -1413,9 +1415,10 @@ static int ioat_dma_self_test(struct ioatdma_device *device) | |||
| 1413 | } | 1415 | } |
| 1414 | device->common.device_issue_pending(dma_chan); | 1416 | device->common.device_issue_pending(dma_chan); |
| 1415 | 1417 | ||
| 1416 | wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); | 1418 | tmo = wait_for_completion_timeout(&cmp, msecs_to_jiffies(3000)); |
| 1417 | 1419 | ||
| 1418 | if (device->common.device_is_tx_complete(dma_chan, cookie, NULL, NULL) | 1420 | if (tmo == 0 || |
| 1421 | device->common.device_is_tx_complete(dma_chan, cookie, NULL, NULL) | ||
| 1419 | != DMA_SUCCESS) { | 1422 | != DMA_SUCCESS) { |
| 1420 | dev_err(&device->pdev->dev, | 1423 | dev_err(&device->pdev->dev, |
| 1421 | "Self-test copy timed out, disabling\n"); | 1424 | "Self-test copy timed out, disabling\n"); |
| @@ -1657,6 +1660,13 @@ struct ioatdma_device *ioat_dma_probe(struct pci_dev *pdev, | |||
| 1657 | " %d channels, device version 0x%02x, driver version %s\n", | 1660 | " %d channels, device version 0x%02x, driver version %s\n", |
| 1658 | device->common.chancnt, device->version, IOAT_DMA_VERSION); | 1661 | device->common.chancnt, device->version, IOAT_DMA_VERSION); |
| 1659 | 1662 | ||
| 1663 | if (!device->common.chancnt) { | ||
| 1664 | dev_err(&device->pdev->dev, | ||
| 1665 | "Intel(R) I/OAT DMA Engine problem found: " | ||
| 1666 | "zero channels detected\n"); | ||
| 1667 | goto err_setup_interrupts; | ||
| 1668 | } | ||
| 1669 | |||
| 1660 | err = ioat_dma_setup_interrupts(device); | 1670 | err = ioat_dma_setup_interrupts(device); |
| 1661 | if (err) | 1671 | if (err) |
| 1662 | goto err_setup_interrupts; | 1672 | goto err_setup_interrupts; |
| @@ -1696,6 +1706,9 @@ void ioat_dma_remove(struct ioatdma_device *device) | |||
| 1696 | struct dma_chan *chan, *_chan; | 1706 | struct dma_chan *chan, *_chan; |
| 1697 | struct ioat_dma_chan *ioat_chan; | 1707 | struct ioat_dma_chan *ioat_chan; |
| 1698 | 1708 | ||
| 1709 | if (device->version != IOAT_VER_3_0) | ||
| 1710 | cancel_delayed_work(&device->work); | ||
| 1711 | |||
| 1699 | ioat_dma_remove_interrupts(device); | 1712 | ioat_dma_remove_interrupts(device); |
| 1700 | 1713 | ||
| 1701 | dma_async_device_unregister(&device->common); | 1714 | dma_async_device_unregister(&device->common); |
| @@ -1707,10 +1720,6 @@ void ioat_dma_remove(struct ioatdma_device *device) | |||
| 1707 | pci_release_regions(device->pdev); | 1720 | pci_release_regions(device->pdev); |
| 1708 | pci_disable_device(device->pdev); | 1721 | pci_disable_device(device->pdev); |
| 1709 | 1722 | ||
| 1710 | if (device->version != IOAT_VER_3_0) { | ||
| 1711 | cancel_delayed_work(&device->work); | ||
| 1712 | } | ||
| 1713 | |||
| 1714 | list_for_each_entry_safe(chan, _chan, | 1723 | list_for_each_entry_safe(chan, _chan, |
| 1715 | &device->common.channels, device_node) { | 1724 | &device->common.channels, device_node) { |
| 1716 | ioat_chan = to_ioat_chan(chan); | 1725 | ioat_chan = to_ioat_chan(chan); |
diff --git a/drivers/dma/ioatdma.h b/drivers/dma/ioatdma.h index a3306d0e1372..a52ff4bd4601 100644 --- a/drivers/dma/ioatdma.h +++ b/drivers/dma/ioatdma.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright(c) 2004 - 2007 Intel Corporation. All rights reserved. | 2 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. |
| 3 | * | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms of the GNU General Public License as published by the Free | 5 | * under the terms of the GNU General Public License as published by the Free |
| @@ -29,7 +29,7 @@ | |||
| 29 | #include <linux/pci_ids.h> | 29 | #include <linux/pci_ids.h> |
| 30 | #include <net/tcp.h> | 30 | #include <net/tcp.h> |
| 31 | 31 | ||
| 32 | #define IOAT_DMA_VERSION "3.30" | 32 | #define IOAT_DMA_VERSION "3.64" |
| 33 | 33 | ||
| 34 | enum ioat_interrupt { | 34 | enum ioat_interrupt { |
| 35 | none = 0, | 35 | none = 0, |
| @@ -135,12 +135,14 @@ static inline void ioat_set_tcp_copy_break(struct ioatdma_device *dev) | |||
| 135 | #ifdef CONFIG_NET_DMA | 135 | #ifdef CONFIG_NET_DMA |
| 136 | switch (dev->version) { | 136 | switch (dev->version) { |
| 137 | case IOAT_VER_1_2: | 137 | case IOAT_VER_1_2: |
| 138 | case IOAT_VER_3_0: | ||
| 139 | sysctl_tcp_dma_copybreak = 4096; | 138 | sysctl_tcp_dma_copybreak = 4096; |
| 140 | break; | 139 | break; |
| 141 | case IOAT_VER_2_0: | 140 | case IOAT_VER_2_0: |
| 142 | sysctl_tcp_dma_copybreak = 2048; | 141 | sysctl_tcp_dma_copybreak = 2048; |
| 143 | break; | 142 | break; |
| 143 | case IOAT_VER_3_0: | ||
| 144 | sysctl_tcp_dma_copybreak = 262144; | ||
| 145 | break; | ||
| 144 | } | 146 | } |
| 145 | #endif | 147 | #endif |
| 146 | } | 148 | } |
diff --git a/drivers/dma/ioatdma_hw.h b/drivers/dma/ioatdma_hw.h index f1ae2c776f74..afa57eef86c9 100644 --- a/drivers/dma/ioatdma_hw.h +++ b/drivers/dma/ioatdma_hw.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright(c) 2004 - 2007 Intel Corporation. All rights reserved. | 2 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. |
| 3 | * | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms of the GNU General Public License as published by the Free | 5 | * under the terms of the GNU General Public License as published by the Free |
diff --git a/drivers/dma/ioatdma_registers.h b/drivers/dma/ioatdma_registers.h index 827cb503cac6..49bc277424f8 100644 --- a/drivers/dma/ioatdma_registers.h +++ b/drivers/dma/ioatdma_registers.h | |||
| @@ -1,5 +1,5 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Copyright(c) 2004 - 2007 Intel Corporation. All rights reserved. | 2 | * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved. |
| 3 | * | 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms of the GNU General Public License as published by the Free | 5 | * under the terms of the GNU General Public License as published by the Free |
diff --git a/drivers/dma/iop-adma.c b/drivers/dma/iop-adma.c index 647374acba94..16adbe61cfb2 100644 --- a/drivers/dma/iop-adma.c +++ b/drivers/dma/iop-adma.c | |||
| @@ -928,19 +928,19 @@ iop_adma_xor_zero_sum_self_test(struct iop_adma_device *device) | |||
| 928 | 928 | ||
| 929 | for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) { | 929 | for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) { |
| 930 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); | 930 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); |
| 931 | if (!xor_srcs[src_idx]) | 931 | if (!xor_srcs[src_idx]) { |
| 932 | while (src_idx--) { | 932 | while (src_idx--) |
| 933 | __free_page(xor_srcs[src_idx]); | 933 | __free_page(xor_srcs[src_idx]); |
| 934 | return -ENOMEM; | 934 | return -ENOMEM; |
| 935 | } | 935 | } |
| 936 | } | 936 | } |
| 937 | 937 | ||
| 938 | dest = alloc_page(GFP_KERNEL); | 938 | dest = alloc_page(GFP_KERNEL); |
| 939 | if (!dest) | 939 | if (!dest) { |
| 940 | while (src_idx--) { | 940 | while (src_idx--) |
| 941 | __free_page(xor_srcs[src_idx]); | 941 | __free_page(xor_srcs[src_idx]); |
| 942 | return -ENOMEM; | 942 | return -ENOMEM; |
| 943 | } | 943 | } |
| 944 | 944 | ||
| 945 | /* Fill in src buffers */ | 945 | /* Fill in src buffers */ |
| 946 | for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) { | 946 | for (src_idx = 0; src_idx < IOP_ADMA_NUM_SRC_TEST; src_idx++) { |
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c index 1f154d08e98f..da781d107895 100644 --- a/drivers/dma/ipu/ipu_idmac.c +++ b/drivers/dma/ipu/ipu_idmac.c | |||
| @@ -729,7 +729,7 @@ static int ipu_init_channel_buffer(struct idmac_channel *ichan, | |||
| 729 | 729 | ||
| 730 | ichan->status = IPU_CHANNEL_READY; | 730 | ichan->status = IPU_CHANNEL_READY; |
| 731 | 731 | ||
| 732 | spin_unlock_irqrestore(ipu->lock, flags); | 732 | spin_unlock_irqrestore(&ipu->lock, flags); |
| 733 | 733 | ||
| 734 | return 0; | 734 | return 0; |
| 735 | } | 735 | } |
| @@ -1649,7 +1649,7 @@ static int ipu_probe(struct platform_device *pdev) | |||
| 1649 | } | 1649 | } |
| 1650 | 1650 | ||
| 1651 | /* Get IPU clock */ | 1651 | /* Get IPU clock */ |
| 1652 | ipu_data.ipu_clk = clk_get(&pdev->dev, "ipu_clk"); | 1652 | ipu_data.ipu_clk = clk_get(&pdev->dev, NULL); |
| 1653 | if (IS_ERR(ipu_data.ipu_clk)) { | 1653 | if (IS_ERR(ipu_data.ipu_clk)) { |
| 1654 | ret = PTR_ERR(ipu_data.ipu_clk); | 1654 | ret = PTR_ERR(ipu_data.ipu_clk); |
| 1655 | goto err_clk_get; | 1655 | goto err_clk_get; |
diff --git a/drivers/dma/mv_xor.c b/drivers/dma/mv_xor.c index 5d5d5b31867f..cb7f26fb9f18 100644 --- a/drivers/dma/mv_xor.c +++ b/drivers/dma/mv_xor.c | |||
| @@ -1019,19 +1019,19 @@ mv_xor_xor_self_test(struct mv_xor_device *device) | |||
| 1019 | 1019 | ||
| 1020 | for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) { | 1020 | for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) { |
| 1021 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); | 1021 | xor_srcs[src_idx] = alloc_page(GFP_KERNEL); |
| 1022 | if (!xor_srcs[src_idx]) | 1022 | if (!xor_srcs[src_idx]) { |
| 1023 | while (src_idx--) { | 1023 | while (src_idx--) |
| 1024 | __free_page(xor_srcs[src_idx]); | 1024 | __free_page(xor_srcs[src_idx]); |
| 1025 | return -ENOMEM; | 1025 | return -ENOMEM; |
| 1026 | } | 1026 | } |
| 1027 | } | 1027 | } |
| 1028 | 1028 | ||
| 1029 | dest = alloc_page(GFP_KERNEL); | 1029 | dest = alloc_page(GFP_KERNEL); |
| 1030 | if (!dest) | 1030 | if (!dest) { |
| 1031 | while (src_idx--) { | 1031 | while (src_idx--) |
| 1032 | __free_page(xor_srcs[src_idx]); | 1032 | __free_page(xor_srcs[src_idx]); |
| 1033 | return -ENOMEM; | 1033 | return -ENOMEM; |
| 1034 | } | 1034 | } |
| 1035 | 1035 | ||
| 1036 | /* Fill in src buffers */ | 1036 | /* Fill in src buffers */ |
| 1037 | for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) { | 1037 | for (src_idx = 0; src_idx < MV_XOR_NUM_SRC_TEST; src_idx++) { |
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 6dab63bdc4c1..6d21b9e48b89 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c | |||
| @@ -1105,7 +1105,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) | |||
| 1105 | 1024 * 1024, | 1105 | 1024 * 1024, |
| 1106 | MTRR_TYPE_WRCOMB, 1); | 1106 | MTRR_TYPE_WRCOMB, 1); |
| 1107 | if (dev_priv->mm.gtt_mtrr < 0) { | 1107 | if (dev_priv->mm.gtt_mtrr < 0) { |
| 1108 | DRM_INFO("MTRR allocation failed\n. Graphics " | 1108 | DRM_INFO("MTRR allocation failed. Graphics " |
| 1109 | "performance may suffer.\n"); | 1109 | "performance may suffer.\n"); |
| 1110 | } | 1110 | } |
| 1111 | 1111 | ||
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 17fa40858d26..d6cc9861e0a1 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
| @@ -279,7 +279,6 @@ typedef struct drm_i915_private { | |||
| 279 | u8 saveAR_INDEX; | 279 | u8 saveAR_INDEX; |
| 280 | u8 saveAR[21]; | 280 | u8 saveAR[21]; |
| 281 | u8 saveDACMASK; | 281 | u8 saveDACMASK; |
| 282 | u8 saveDACDATA[256*3]; /* 256 3-byte colors */ | ||
| 283 | u8 saveCR[37]; | 282 | u8 saveCR[37]; |
| 284 | 283 | ||
| 285 | struct { | 284 | struct { |
| @@ -457,6 +456,12 @@ struct drm_i915_gem_object { | |||
| 457 | 456 | ||
| 458 | /** for phy allocated objects */ | 457 | /** for phy allocated objects */ |
| 459 | struct drm_i915_gem_phys_object *phys_obj; | 458 | struct drm_i915_gem_phys_object *phys_obj; |
| 459 | |||
| 460 | /** | ||
| 461 | * Used for checking the object doesn't appear more than once | ||
| 462 | * in an execbuffer object list. | ||
| 463 | */ | ||
| 464 | int in_execbuffer; | ||
| 460 | }; | 465 | }; |
| 461 | 466 | ||
| 462 | /** | 467 | /** |
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 85685bfd12da..37427e4016cb 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c | |||
| @@ -1476,7 +1476,7 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |||
| 1476 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | 1476 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1477 | int regnum = obj_priv->fence_reg; | 1477 | int regnum = obj_priv->fence_reg; |
| 1478 | int tile_width; | 1478 | int tile_width; |
| 1479 | uint32_t val; | 1479 | uint32_t fence_reg, val; |
| 1480 | uint32_t pitch_val; | 1480 | uint32_t pitch_val; |
| 1481 | 1481 | ||
| 1482 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | 1482 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || |
| @@ -1503,7 +1503,11 @@ static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |||
| 1503 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | 1503 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 1504 | val |= I830_FENCE_REG_VALID; | 1504 | val |= I830_FENCE_REG_VALID; |
| 1505 | 1505 | ||
| 1506 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | 1506 | if (regnum < 8) |
| 1507 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | ||
| 1508 | else | ||
| 1509 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | ||
| 1510 | I915_WRITE(fence_reg, val); | ||
| 1507 | } | 1511 | } |
| 1508 | 1512 | ||
| 1509 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | 1513 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) |
| @@ -1557,7 +1561,8 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write) | |||
| 1557 | struct drm_i915_private *dev_priv = dev->dev_private; | 1561 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1558 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | 1562 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1559 | struct drm_i915_fence_reg *reg = NULL; | 1563 | struct drm_i915_fence_reg *reg = NULL; |
| 1560 | int i, ret; | 1564 | struct drm_i915_gem_object *old_obj_priv = NULL; |
| 1565 | int i, ret, avail; | ||
| 1561 | 1566 | ||
| 1562 | switch (obj_priv->tiling_mode) { | 1567 | switch (obj_priv->tiling_mode) { |
| 1563 | case I915_TILING_NONE: | 1568 | case I915_TILING_NONE: |
| @@ -1580,25 +1585,46 @@ i915_gem_object_get_fence_reg(struct drm_gem_object *obj, bool write) | |||
| 1580 | } | 1585 | } |
| 1581 | 1586 | ||
| 1582 | /* First try to find a free reg */ | 1587 | /* First try to find a free reg */ |
| 1588 | try_again: | ||
| 1589 | avail = 0; | ||
| 1583 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | 1590 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 1584 | reg = &dev_priv->fence_regs[i]; | 1591 | reg = &dev_priv->fence_regs[i]; |
| 1585 | if (!reg->obj) | 1592 | if (!reg->obj) |
| 1586 | break; | 1593 | break; |
| 1594 | |||
| 1595 | old_obj_priv = reg->obj->driver_private; | ||
| 1596 | if (!old_obj_priv->pin_count) | ||
| 1597 | avail++; | ||
| 1587 | } | 1598 | } |
| 1588 | 1599 | ||
| 1589 | /* None available, try to steal one or wait for a user to finish */ | 1600 | /* None available, try to steal one or wait for a user to finish */ |
| 1590 | if (i == dev_priv->num_fence_regs) { | 1601 | if (i == dev_priv->num_fence_regs) { |
| 1591 | struct drm_i915_gem_object *old_obj_priv = NULL; | 1602 | uint32_t seqno = dev_priv->mm.next_gem_seqno; |
| 1592 | loff_t offset; | 1603 | loff_t offset; |
| 1593 | 1604 | ||
| 1594 | try_again: | 1605 | if (avail == 0) |
| 1595 | /* Could try to use LRU here instead... */ | 1606 | return -ENOMEM; |
| 1607 | |||
| 1596 | for (i = dev_priv->fence_reg_start; | 1608 | for (i = dev_priv->fence_reg_start; |
| 1597 | i < dev_priv->num_fence_regs; i++) { | 1609 | i < dev_priv->num_fence_regs; i++) { |
| 1610 | uint32_t this_seqno; | ||
| 1611 | |||
| 1598 | reg = &dev_priv->fence_regs[i]; | 1612 | reg = &dev_priv->fence_regs[i]; |
| 1599 | old_obj_priv = reg->obj->driver_private; | 1613 | old_obj_priv = reg->obj->driver_private; |
| 1600 | if (!old_obj_priv->pin_count) | 1614 | |
| 1615 | if (old_obj_priv->pin_count) | ||
| 1616 | continue; | ||
| 1617 | |||
| 1618 | /* i915 uses fences for GPU access to tiled buffers */ | ||
| 1619 | if (IS_I965G(dev) || !old_obj_priv->active) | ||
| 1601 | break; | 1620 | break; |
| 1621 | |||
| 1622 | /* find the seqno of the first available fence */ | ||
| 1623 | this_seqno = old_obj_priv->last_rendering_seqno; | ||
| 1624 | if (this_seqno != 0 && | ||
| 1625 | reg->obj->write_domain == 0 && | ||
| 1626 | i915_seqno_passed(seqno, this_seqno)) | ||
| 1627 | seqno = this_seqno; | ||
| 1602 | } | 1628 | } |
| 1603 | 1629 | ||
| 1604 | /* | 1630 | /* |
| @@ -1606,15 +1632,25 @@ try_again: | |||
| 1606 | * objects to finish before trying again. | 1632 | * objects to finish before trying again. |
| 1607 | */ | 1633 | */ |
| 1608 | if (i == dev_priv->num_fence_regs) { | 1634 | if (i == dev_priv->num_fence_regs) { |
| 1609 | ret = i915_gem_object_set_to_gtt_domain(reg->obj, 0); | 1635 | if (seqno == dev_priv->mm.next_gem_seqno) { |
| 1610 | if (ret) { | 1636 | i915_gem_flush(dev, |
| 1611 | WARN(ret != -ERESTARTSYS, | 1637 | I915_GEM_GPU_DOMAINS, |
| 1612 | "switch to GTT domain failed: %d\n", ret); | 1638 | I915_GEM_GPU_DOMAINS); |
| 1613 | return ret; | 1639 | seqno = i915_add_request(dev, |
| 1640 | I915_GEM_GPU_DOMAINS); | ||
| 1641 | if (seqno == 0) | ||
| 1642 | return -ENOMEM; | ||
| 1614 | } | 1643 | } |
| 1644 | |||
| 1645 | ret = i915_wait_request(dev, seqno); | ||
| 1646 | if (ret) | ||
| 1647 | return ret; | ||
| 1615 | goto try_again; | 1648 | goto try_again; |
| 1616 | } | 1649 | } |
| 1617 | 1650 | ||
| 1651 | BUG_ON(old_obj_priv->active || | ||
| 1652 | (reg->obj->write_domain & I915_GEM_GPU_DOMAINS)); | ||
| 1653 | |||
| 1618 | /* | 1654 | /* |
| 1619 | * Zap this virtual mapping so we can set up a fence again | 1655 | * Zap this virtual mapping so we can set up a fence again |
| 1620 | * for this object next time we need it. | 1656 | * for this object next time we need it. |
| @@ -1655,8 +1691,17 @@ i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |||
| 1655 | 1691 | ||
| 1656 | if (IS_I965G(dev)) | 1692 | if (IS_I965G(dev)) |
| 1657 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); | 1693 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
| 1658 | else | 1694 | else { |
| 1659 | I915_WRITE(FENCE_REG_830_0 + (obj_priv->fence_reg * 4), 0); | 1695 | uint32_t fence_reg; |
| 1696 | |||
| 1697 | if (obj_priv->fence_reg < 8) | ||
| 1698 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | ||
| 1699 | else | ||
| 1700 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - | ||
| 1701 | 8) * 4; | ||
| 1702 | |||
| 1703 | I915_WRITE(fence_reg, 0); | ||
| 1704 | } | ||
| 1660 | 1705 | ||
| 1661 | dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL; | 1706 | dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL; |
| 1662 | obj_priv->fence_reg = I915_FENCE_REG_NONE; | 1707 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
| @@ -2469,6 +2514,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, | |||
| 2469 | struct drm_i915_gem_exec_object *exec_list = NULL; | 2514 | struct drm_i915_gem_exec_object *exec_list = NULL; |
| 2470 | struct drm_gem_object **object_list = NULL; | 2515 | struct drm_gem_object **object_list = NULL; |
| 2471 | struct drm_gem_object *batch_obj; | 2516 | struct drm_gem_object *batch_obj; |
| 2517 | struct drm_i915_gem_object *obj_priv; | ||
| 2472 | int ret, i, pinned = 0; | 2518 | int ret, i, pinned = 0; |
| 2473 | uint64_t exec_offset; | 2519 | uint64_t exec_offset; |
| 2474 | uint32_t seqno, flush_domains; | 2520 | uint32_t seqno, flush_domains; |
| @@ -2533,6 +2579,15 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, | |||
| 2533 | ret = -EBADF; | 2579 | ret = -EBADF; |
| 2534 | goto err; | 2580 | goto err; |
| 2535 | } | 2581 | } |
| 2582 | |||
| 2583 | obj_priv = object_list[i]->driver_private; | ||
| 2584 | if (obj_priv->in_execbuffer) { | ||
| 2585 | DRM_ERROR("Object %p appears more than once in object list\n", | ||
| 2586 | object_list[i]); | ||
| 2587 | ret = -EBADF; | ||
| 2588 | goto err; | ||
| 2589 | } | ||
| 2590 | obj_priv->in_execbuffer = true; | ||
| 2536 | } | 2591 | } |
| 2537 | 2592 | ||
| 2538 | /* Pin and relocate */ | 2593 | /* Pin and relocate */ |
| @@ -2674,8 +2729,13 @@ err: | |||
| 2674 | for (i = 0; i < pinned; i++) | 2729 | for (i = 0; i < pinned; i++) |
| 2675 | i915_gem_object_unpin(object_list[i]); | 2730 | i915_gem_object_unpin(object_list[i]); |
| 2676 | 2731 | ||
| 2677 | for (i = 0; i < args->buffer_count; i++) | 2732 | for (i = 0; i < args->buffer_count; i++) { |
| 2733 | if (object_list[i]) { | ||
| 2734 | obj_priv = object_list[i]->driver_private; | ||
| 2735 | obj_priv->in_execbuffer = false; | ||
| 2736 | } | ||
| 2678 | drm_gem_object_unreference(object_list[i]); | 2737 | drm_gem_object_unreference(object_list[i]); |
| 2738 | } | ||
| 2679 | 2739 | ||
| 2680 | mutex_unlock(&dev->struct_mutex); | 2740 | mutex_unlock(&dev->struct_mutex); |
| 2681 | 2741 | ||
| @@ -2712,17 +2772,24 @@ i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |||
| 2712 | ret = i915_gem_object_bind_to_gtt(obj, alignment); | 2772 | ret = i915_gem_object_bind_to_gtt(obj, alignment); |
| 2713 | if (ret != 0) { | 2773 | if (ret != 0) { |
| 2714 | if (ret != -EBUSY && ret != -ERESTARTSYS) | 2774 | if (ret != -EBUSY && ret != -ERESTARTSYS) |
| 2715 | DRM_ERROR("Failure to bind: %d", ret); | 2775 | DRM_ERROR("Failure to bind: %d\n", ret); |
| 2776 | return ret; | ||
| 2777 | } | ||
| 2778 | } | ||
| 2779 | /* | ||
| 2780 | * Pre-965 chips need a fence register set up in order to | ||
| 2781 | * properly handle tiled surfaces. | ||
| 2782 | */ | ||
| 2783 | if (!IS_I965G(dev) && | ||
| 2784 | obj_priv->fence_reg == I915_FENCE_REG_NONE && | ||
| 2785 | obj_priv->tiling_mode != I915_TILING_NONE) { | ||
| 2786 | ret = i915_gem_object_get_fence_reg(obj, true); | ||
| 2787 | if (ret != 0) { | ||
| 2788 | if (ret != -EBUSY && ret != -ERESTARTSYS) | ||
| 2789 | DRM_ERROR("Failure to install fence: %d\n", | ||
| 2790 | ret); | ||
| 2716 | return ret; | 2791 | return ret; |
| 2717 | } | 2792 | } |
| 2718 | /* | ||
| 2719 | * Pre-965 chips need a fence register set up in order to | ||
| 2720 | * properly handle tiled surfaces. | ||
| 2721 | */ | ||
| 2722 | if (!IS_I965G(dev) && | ||
| 2723 | obj_priv->fence_reg == I915_FENCE_REG_NONE && | ||
| 2724 | obj_priv->tiling_mode != I915_TILING_NONE) | ||
| 2725 | i915_gem_object_get_fence_reg(obj, true); | ||
| 2726 | } | 2793 | } |
| 2727 | obj_priv->pin_count++; | 2794 | obj_priv->pin_count++; |
| 2728 | 2795 | ||
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9d6539a868b3..90600d899413 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
| @@ -184,6 +184,7 @@ | |||
| 184 | * Fence registers | 184 | * Fence registers |
| 185 | */ | 185 | */ |
| 186 | #define FENCE_REG_830_0 0x2000 | 186 | #define FENCE_REG_830_0 0x2000 |
| 187 | #define FENCE_REG_945_8 0x3000 | ||
| 187 | #define I830_FENCE_START_MASK 0x07f80000 | 188 | #define I830_FENCE_START_MASK 0x07f80000 |
| 188 | #define I830_FENCE_TILING_Y_SHIFT 12 | 189 | #define I830_FENCE_TILING_Y_SHIFT 12 |
| 189 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) | 190 | #define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8) |
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 5d84027ee8f3..d669cc2b42c0 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c | |||
| @@ -119,11 +119,6 @@ static void i915_save_vga(struct drm_device *dev) | |||
| 119 | 119 | ||
| 120 | /* VGA color palette registers */ | 120 | /* VGA color palette registers */ |
| 121 | dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK); | 121 | dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK); |
| 122 | /* DACCRX automatically increments during read */ | ||
| 123 | I915_WRITE8(VGA_DACRX, 0); | ||
| 124 | /* Read 3 bytes of color data from each index */ | ||
| 125 | for (i = 0; i < 256 * 3; i++) | ||
| 126 | dev_priv->saveDACDATA[i] = I915_READ8(VGA_DACDATA); | ||
| 127 | 122 | ||
| 128 | /* MSR bits */ | 123 | /* MSR bits */ |
| 129 | dev_priv->saveMSR = I915_READ8(VGA_MSR_READ); | 124 | dev_priv->saveMSR = I915_READ8(VGA_MSR_READ); |
| @@ -225,12 +220,6 @@ static void i915_restore_vga(struct drm_device *dev) | |||
| 225 | 220 | ||
| 226 | /* VGA color palette registers */ | 221 | /* VGA color palette registers */ |
| 227 | I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK); | 222 | I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK); |
| 228 | /* DACCRX automatically increments during read */ | ||
| 229 | I915_WRITE8(VGA_DACWX, 0); | ||
| 230 | /* Read 3 bytes of color data from each index */ | ||
| 231 | for (i = 0; i < 256 * 3; i++) | ||
| 232 | I915_WRITE8(VGA_DACDATA, dev_priv->saveDACDATA[i]); | ||
| 233 | |||
| 234 | } | 223 | } |
| 235 | 224 | ||
| 236 | int i915_save_state(struct drm_device *dev) | 225 | int i915_save_state(struct drm_device *dev) |
diff --git a/drivers/hid/usbhid/hiddev.c b/drivers/hid/usbhid/hiddev.c index 4940e4d70c2d..1f5b5d4c3c34 100644 --- a/drivers/hid/usbhid/hiddev.c +++ b/drivers/hid/usbhid/hiddev.c | |||
| @@ -306,7 +306,7 @@ static int hiddev_open(struct inode *inode, struct file *file) | |||
| 306 | return 0; | 306 | return 0; |
| 307 | bail: | 307 | bail: |
| 308 | file->private_data = NULL; | 308 | file->private_data = NULL; |
| 309 | kfree(list->hiddev); | 309 | kfree(list); |
| 310 | return res; | 310 | return res; |
| 311 | } | 311 | } |
| 312 | 312 | ||
| @@ -323,7 +323,7 @@ static ssize_t hiddev_write(struct file * file, const char __user * buffer, size | |||
| 323 | */ | 323 | */ |
| 324 | static ssize_t hiddev_read(struct file * file, char __user * buffer, size_t count, loff_t *ppos) | 324 | static ssize_t hiddev_read(struct file * file, char __user * buffer, size_t count, loff_t *ppos) |
| 325 | { | 325 | { |
| 326 | DECLARE_WAITQUEUE(wait, current); | 326 | DEFINE_WAIT(wait); |
| 327 | struct hiddev_list *list = file->private_data; | 327 | struct hiddev_list *list = file->private_data; |
| 328 | int event_size; | 328 | int event_size; |
| 329 | int retval; | 329 | int retval; |
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index b84bf066879b..b4eea0292c1a 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig | |||
| @@ -543,8 +543,8 @@ config SENSORS_LM90 | |||
| 543 | help | 543 | help |
| 544 | If you say yes here you get support for National Semiconductor LM90, | 544 | If you say yes here you get support for National Semiconductor LM90, |
| 545 | LM86, LM89 and LM99, Analog Devices ADM1032 and ADT7461, and Maxim | 545 | LM86, LM89 and LM99, Analog Devices ADM1032 and ADT7461, and Maxim |
| 546 | MAX6646, MAX6647, MAX6649, MAX6657, MAX6658, MAX6659, MAX6680 and | 546 | MAX6646, MAX6647, MAX6648, MAX6649, MAX6657, MAX6658, MAX6659, |
| 547 | MAX6681 sensor chips. | 547 | MAX6680, MAX6681 and MAX6692 sensor chips. |
| 548 | 548 | ||
| 549 | This driver can also be built as a module. If so, the module | 549 | This driver can also be built as a module. If so, the module |
| 550 | will be called lm90. | 550 | will be called lm90. |
diff --git a/drivers/hwmon/abituguru3.c b/drivers/hwmon/abituguru3.c index e52b38806d03..ad2b3431b725 100644 --- a/drivers/hwmon/abituguru3.c +++ b/drivers/hwmon/abituguru3.c | |||
| @@ -760,8 +760,11 @@ static int abituguru3_read_increment_offset(struct abituguru3_data *data, | |||
| 760 | 760 | ||
| 761 | for (i = 0; i < offset_count; i++) | 761 | for (i = 0; i < offset_count; i++) |
| 762 | if ((x = abituguru3_read(data, bank, offset + i, count, | 762 | if ((x = abituguru3_read(data, bank, offset + i, count, |
| 763 | buf + i * count)) != count) | 763 | buf + i * count)) != count) { |
| 764 | return i * count + (i && (x < 0)) ? 0 : x; | 764 | if (x < 0) |
| 765 | return x; | ||
| 766 | return i * count + x; | ||
| 767 | } | ||
| 765 | 768 | ||
| 766 | return i * count; | 769 | return i * count; |
| 767 | } | 770 | } |
diff --git a/drivers/hwmon/f75375s.c b/drivers/hwmon/f75375s.c index 1692de369969..18a1ba888165 100644 --- a/drivers/hwmon/f75375s.c +++ b/drivers/hwmon/f75375s.c | |||
| @@ -617,7 +617,7 @@ static void f75375_init(struct i2c_client *client, struct f75375_data *data, | |||
| 617 | static int f75375_probe(struct i2c_client *client, | 617 | static int f75375_probe(struct i2c_client *client, |
| 618 | const struct i2c_device_id *id) | 618 | const struct i2c_device_id *id) |
| 619 | { | 619 | { |
| 620 | struct f75375_data *data = i2c_get_clientdata(client); | 620 | struct f75375_data *data; |
| 621 | struct f75375s_platform_data *f75375s_pdata = client->dev.platform_data; | 621 | struct f75375s_platform_data *f75375s_pdata = client->dev.platform_data; |
| 622 | int err; | 622 | int err; |
| 623 | 623 | ||
diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index 95a99c590da2..9157247fed8e 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c | |||
| @@ -213,7 +213,7 @@ static inline u16 FAN16_TO_REG(long rpm) | |||
| 213 | 213 | ||
| 214 | #define TEMP_TO_REG(val) (SENSORS_LIMIT(((val)<0?(((val)-500)/1000):\ | 214 | #define TEMP_TO_REG(val) (SENSORS_LIMIT(((val)<0?(((val)-500)/1000):\ |
| 215 | ((val)+500)/1000),-128,127)) | 215 | ((val)+500)/1000),-128,127)) |
| 216 | #define TEMP_FROM_REG(val) (((val)>0x80?(val)-0x100:(val))*1000) | 216 | #define TEMP_FROM_REG(val) ((val) * 1000) |
| 217 | 217 | ||
| 218 | #define PWM_TO_REG(val) ((val) >> 1) | 218 | #define PWM_TO_REG(val) ((val) >> 1) |
| 219 | #define PWM_FROM_REG(val) (((val)&0x7f) << 1) | 219 | #define PWM_FROM_REG(val) (((val)&0x7f) << 1) |
| @@ -267,9 +267,9 @@ struct it87_data { | |||
| 267 | u8 has_fan; /* Bitfield, fans enabled */ | 267 | u8 has_fan; /* Bitfield, fans enabled */ |
| 268 | u16 fan[5]; /* Register values, possibly combined */ | 268 | u16 fan[5]; /* Register values, possibly combined */ |
| 269 | u16 fan_min[5]; /* Register values, possibly combined */ | 269 | u16 fan_min[5]; /* Register values, possibly combined */ |
| 270 | u8 temp[3]; /* Register value */ | 270 | s8 temp[3]; /* Register value */ |
| 271 | u8 temp_high[3]; /* Register value */ | 271 | s8 temp_high[3]; /* Register value */ |
| 272 | u8 temp_low[3]; /* Register value */ | 272 | s8 temp_low[3]; /* Register value */ |
| 273 | u8 sensor; /* Register value */ | 273 | u8 sensor; /* Register value */ |
| 274 | u8 fan_div[3]; /* Register encoding, shifted right */ | 274 | u8 fan_div[3]; /* Register encoding, shifted right */ |
| 275 | u8 vid; /* Register encoding, combined */ | 275 | u8 vid; /* Register encoding, combined */ |
diff --git a/drivers/hwmon/lm85.c b/drivers/hwmon/lm85.c index cfc1ee90f5a3..b251d8674b41 100644 --- a/drivers/hwmon/lm85.c +++ b/drivers/hwmon/lm85.c | |||
| @@ -72,6 +72,7 @@ I2C_CLIENT_INSMOD_7(lm85b, lm85c, adm1027, adt7463, adt7468, emc6d100, | |||
| 72 | #define LM85_COMPANY_SMSC 0x5c | 72 | #define LM85_COMPANY_SMSC 0x5c |
| 73 | #define LM85_VERSTEP_VMASK 0xf0 | 73 | #define LM85_VERSTEP_VMASK 0xf0 |
| 74 | #define LM85_VERSTEP_GENERIC 0x60 | 74 | #define LM85_VERSTEP_GENERIC 0x60 |
| 75 | #define LM85_VERSTEP_GENERIC2 0x70 | ||
| 75 | #define LM85_VERSTEP_LM85C 0x60 | 76 | #define LM85_VERSTEP_LM85C 0x60 |
| 76 | #define LM85_VERSTEP_LM85B 0x62 | 77 | #define LM85_VERSTEP_LM85B 0x62 |
| 77 | #define LM85_VERSTEP_ADM1027 0x60 | 78 | #define LM85_VERSTEP_ADM1027 0x60 |
| @@ -334,6 +335,7 @@ static struct lm85_data *lm85_update_device(struct device *dev); | |||
| 334 | static const struct i2c_device_id lm85_id[] = { | 335 | static const struct i2c_device_id lm85_id[] = { |
| 335 | { "adm1027", adm1027 }, | 336 | { "adm1027", adm1027 }, |
| 336 | { "adt7463", adt7463 }, | 337 | { "adt7463", adt7463 }, |
| 338 | { "adt7468", adt7468 }, | ||
| 337 | { "lm85", any_chip }, | 339 | { "lm85", any_chip }, |
| 338 | { "lm85b", lm85b }, | 340 | { "lm85b", lm85b }, |
| 339 | { "lm85c", lm85c }, | 341 | { "lm85c", lm85c }, |
| @@ -408,7 +410,8 @@ static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr, | |||
| 408 | struct lm85_data *data = lm85_update_device(dev); | 410 | struct lm85_data *data = lm85_update_device(dev); |
| 409 | int vid; | 411 | int vid; |
| 410 | 412 | ||
| 411 | if (data->type == adt7463 && (data->vid & 0x80)) { | 413 | if ((data->type == adt7463 || data->type == adt7468) && |
| 414 | (data->vid & 0x80)) { | ||
| 412 | /* 6-pin VID (VRM 10) */ | 415 | /* 6-pin VID (VRM 10) */ |
| 413 | vid = vid_from_reg(data->vid & 0x3f, data->vrm); | 416 | vid = vid_from_reg(data->vid & 0x3f, data->vrm); |
| 414 | } else { | 417 | } else { |
| @@ -1153,7 +1156,8 @@ static int lm85_detect(struct i2c_client *client, int kind, | |||
| 1153 | address, company, verstep); | 1156 | address, company, verstep); |
| 1154 | 1157 | ||
| 1155 | /* All supported chips have the version in common */ | 1158 | /* All supported chips have the version in common */ |
| 1156 | if ((verstep & LM85_VERSTEP_VMASK) != LM85_VERSTEP_GENERIC) { | 1159 | if ((verstep & LM85_VERSTEP_VMASK) != LM85_VERSTEP_GENERIC && |
| 1160 | (verstep & LM85_VERSTEP_VMASK) != LM85_VERSTEP_GENERIC2) { | ||
| 1157 | dev_dbg(&adapter->dev, "Autodetection failed: " | 1161 | dev_dbg(&adapter->dev, "Autodetection failed: " |
| 1158 | "unsupported version\n"); | 1162 | "unsupported version\n"); |
| 1159 | return -ENODEV; | 1163 | return -ENODEV; |
diff --git a/drivers/hwmon/lm90.c b/drivers/hwmon/lm90.c index 96a701866726..1aff7575799d 100644 --- a/drivers/hwmon/lm90.c +++ b/drivers/hwmon/lm90.c | |||
| @@ -32,10 +32,10 @@ | |||
| 32 | * supported by this driver. These chips lack the remote temperature | 32 | * supported by this driver. These chips lack the remote temperature |
| 33 | * offset feature. | 33 | * offset feature. |
| 34 | * | 34 | * |
| 35 | * This driver also supports the MAX6646, MAX6647 and MAX6649 chips | 35 | * This driver also supports the MAX6646, MAX6647, MAX6648, MAX6649 and |
| 36 | * made by Maxim. These are again similar to the LM86, but they use | 36 | * MAX6692 chips made by Maxim. These are again similar to the LM86, |
| 37 | * unsigned temperature values and can report temperatures from 0 to | 37 | * but they use unsigned temperature values and can report temperatures |
| 38 | * 145 degrees. | 38 | * from 0 to 145 degrees. |
| 39 | * | 39 | * |
| 40 | * This driver also supports the MAX6680 and MAX6681, two other sensor | 40 | * This driver also supports the MAX6680 and MAX6681, two other sensor |
| 41 | * chips made by Maxim. These are quite similar to the other Maxim | 41 | * chips made by Maxim. These are quite similar to the other Maxim |
diff --git a/drivers/i2c/busses/i2c-acorn.c b/drivers/i2c/busses/i2c-acorn.c index 9aefb5e5864d..86796488ef4f 100644 --- a/drivers/i2c/busses/i2c-acorn.c +++ b/drivers/i2c/busses/i2c-acorn.c | |||
| @@ -15,9 +15,9 @@ | |||
| 15 | #include <linux/init.h> | 15 | #include <linux/init.h> |
| 16 | #include <linux/i2c.h> | 16 | #include <linux/i2c.h> |
| 17 | #include <linux/i2c-algo-bit.h> | 17 | #include <linux/i2c-algo-bit.h> |
| 18 | #include <linux/io.h> | ||
| 18 | 19 | ||
| 19 | #include <mach/hardware.h> | 20 | #include <mach/hardware.h> |
| 20 | #include <asm/io.h> | ||
| 21 | #include <asm/hardware/ioc.h> | 21 | #include <asm/hardware/ioc.h> |
| 22 | #include <asm/system.h> | 22 | #include <asm/system.h> |
| 23 | 23 | ||
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index be8ee2cac8bb..ece0125a1ee5 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c | |||
| @@ -193,22 +193,24 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg) | |||
| 193 | 193 | ||
| 194 | static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev) | 194 | static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev) |
| 195 | { | 195 | { |
| 196 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { | 196 | int ret; |
| 197 | dev->iclk = clk_get(dev->dev, "i2c_ick"); | 197 | |
| 198 | if (IS_ERR(dev->iclk)) { | 198 | dev->iclk = clk_get(dev->dev, "ick"); |
| 199 | dev->iclk = NULL; | 199 | if (IS_ERR(dev->iclk)) { |
| 200 | return -ENODEV; | 200 | ret = PTR_ERR(dev->iclk); |
| 201 | } | 201 | dev->iclk = NULL; |
| 202 | return ret; | ||
| 202 | } | 203 | } |
| 203 | 204 | ||
| 204 | dev->fclk = clk_get(dev->dev, "i2c_fck"); | 205 | dev->fclk = clk_get(dev->dev, "fck"); |
| 205 | if (IS_ERR(dev->fclk)) { | 206 | if (IS_ERR(dev->fclk)) { |
| 207 | ret = PTR_ERR(dev->fclk); | ||
| 206 | if (dev->iclk != NULL) { | 208 | if (dev->iclk != NULL) { |
| 207 | clk_put(dev->iclk); | 209 | clk_put(dev->iclk); |
| 208 | dev->iclk = NULL; | 210 | dev->iclk = NULL; |
| 209 | } | 211 | } |
| 210 | dev->fclk = NULL; | 212 | dev->fclk = NULL; |
| 211 | return -ENODEV; | 213 | return ret; |
| 212 | } | 214 | } |
| 213 | 215 | ||
| 214 | return 0; | 216 | return 0; |
| @@ -218,18 +220,15 @@ static void omap_i2c_put_clocks(struct omap_i2c_dev *dev) | |||
| 218 | { | 220 | { |
| 219 | clk_put(dev->fclk); | 221 | clk_put(dev->fclk); |
| 220 | dev->fclk = NULL; | 222 | dev->fclk = NULL; |
| 221 | if (dev->iclk != NULL) { | 223 | clk_put(dev->iclk); |
| 222 | clk_put(dev->iclk); | 224 | dev->iclk = NULL; |
| 223 | dev->iclk = NULL; | ||
| 224 | } | ||
| 225 | } | 225 | } |
| 226 | 226 | ||
| 227 | static void omap_i2c_unidle(struct omap_i2c_dev *dev) | 227 | static void omap_i2c_unidle(struct omap_i2c_dev *dev) |
| 228 | { | 228 | { |
| 229 | WARN_ON(!dev->idle); | 229 | WARN_ON(!dev->idle); |
| 230 | 230 | ||
| 231 | if (dev->iclk != NULL) | 231 | clk_enable(dev->iclk); |
| 232 | clk_enable(dev->iclk); | ||
| 233 | clk_enable(dev->fclk); | 232 | clk_enable(dev->fclk); |
| 234 | dev->idle = 0; | 233 | dev->idle = 0; |
| 235 | if (dev->iestate) | 234 | if (dev->iestate) |
| @@ -254,8 +253,7 @@ static void omap_i2c_idle(struct omap_i2c_dev *dev) | |||
| 254 | } | 253 | } |
| 255 | dev->idle = 1; | 254 | dev->idle = 1; |
| 256 | clk_disable(dev->fclk); | 255 | clk_disable(dev->fclk); |
| 257 | if (dev->iclk != NULL) | 256 | clk_disable(dev->iclk); |
| 258 | clk_disable(dev->iclk); | ||
| 259 | } | 257 | } |
| 260 | 258 | ||
| 261 | static int omap_i2c_init(struct omap_i2c_dev *dev) | 259 | static int omap_i2c_init(struct omap_i2c_dev *dev) |
| @@ -312,15 +310,14 @@ static int omap_i2c_init(struct omap_i2c_dev *dev) | |||
| 312 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); | 310 | omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); |
| 313 | 311 | ||
| 314 | if (cpu_class_is_omap1()) { | 312 | if (cpu_class_is_omap1()) { |
| 315 | struct clk *armxor_ck; | 313 | /* |
| 316 | 314 | * The I2C functional clock is the armxor_ck, so there's | |
| 317 | armxor_ck = clk_get(NULL, "armxor_ck"); | 315 | * no need to get "armxor_ck" separately. Now, if OMAP2420 |
| 318 | if (IS_ERR(armxor_ck)) | 316 | * always returns 12MHz for the functional clock, we can |
| 319 | dev_warn(dev->dev, "Could not get armxor_ck\n"); | 317 | * do this bit unconditionally. |
| 320 | else { | 318 | */ |
| 321 | fclk_rate = clk_get_rate(armxor_ck); | 319 | fclk_rate = clk_get_rate(dev->fclk); |
| 322 | clk_put(armxor_ck); | 320 | |
| 323 | } | ||
| 324 | /* TRM for 5912 says the I2C clock must be prescaled to be | 321 | /* TRM for 5912 says the I2C clock must be prescaled to be |
| 325 | * between 7 - 12 MHz. The XOR input clock is typically | 322 | * between 7 - 12 MHz. The XOR input clock is typically |
| 326 | * 12, 13 or 19.2 MHz. So we should have code that produces: | 323 | * 12, 13 or 19.2 MHz. So we should have code that produces: |
diff --git a/drivers/i2c/busses/i2c-versatile.c b/drivers/i2c/busses/i2c-versatile.c index 4678babd3ce6..fede619ba227 100644 --- a/drivers/i2c/busses/i2c-versatile.c +++ b/drivers/i2c/busses/i2c-versatile.c | |||
| @@ -102,7 +102,13 @@ static int i2c_versatile_probe(struct platform_device *dev) | |||
| 102 | i2c->algo = i2c_versatile_algo; | 102 | i2c->algo = i2c_versatile_algo; |
| 103 | i2c->algo.data = i2c; | 103 | i2c->algo.data = i2c; |
| 104 | 104 | ||
| 105 | ret = i2c_bit_add_bus(&i2c->adap); | 105 | if (dev->id >= 0) { |
| 106 | /* static bus numbering */ | ||
| 107 | i2c->adap.nr = dev->id; | ||
| 108 | ret = i2c_bit_add_numbered_bus(&i2c->adap); | ||
| 109 | } else | ||
| 110 | /* dynamic bus numbering */ | ||
| 111 | ret = i2c_bit_add_bus(&i2c->adap); | ||
| 106 | if (ret >= 0) { | 112 | if (ret >= 0) { |
| 107 | platform_set_drvdata(dev, i2c); | 113 | platform_set_drvdata(dev, i2c); |
| 108 | return 0; | 114 | return 0; |
| @@ -146,7 +152,7 @@ static void __exit i2c_versatile_exit(void) | |||
| 146 | platform_driver_unregister(&i2c_versatile_driver); | 152 | platform_driver_unregister(&i2c_versatile_driver); |
| 147 | } | 153 | } |
| 148 | 154 | ||
| 149 | module_init(i2c_versatile_init); | 155 | subsys_initcall(i2c_versatile_init); |
| 150 | module_exit(i2c_versatile_exit); | 156 | module_exit(i2c_versatile_exit); |
| 151 | 157 | ||
| 152 | MODULE_DESCRIPTION("ARM Versatile I2C bus driver"); | 158 | MODULE_DESCRIPTION("ARM Versatile I2C bus driver"); |
diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig index e072903b12f0..5ea3bfad172a 100644 --- a/drivers/ide/Kconfig +++ b/drivers/ide/Kconfig | |||
| @@ -721,6 +721,11 @@ config BLK_DEV_IDE_TX4939 | |||
| 721 | depends on SOC_TX4939 | 721 | depends on SOC_TX4939 |
| 722 | select BLK_DEV_IDEDMA_SFF | 722 | select BLK_DEV_IDEDMA_SFF |
| 723 | 723 | ||
| 724 | config BLK_DEV_IDE_AT91 | ||
| 725 | tristate "Atmel AT91 (SAM9, CAP9, AT572D940HF) IDE support" | ||
| 726 | depends on ARM && ARCH_AT91 && !ARCH_AT91RM9200 && !ARCH_AT91X40 | ||
| 727 | select IDE_TIMINGS | ||
| 728 | |||
| 724 | config IDE_ARM | 729 | config IDE_ARM |
| 725 | tristate "ARM IDE support" | 730 | tristate "ARM IDE support" |
| 726 | depends on ARM && (ARCH_RPC || ARCH_SHARK) | 731 | depends on ARM && (ARCH_RPC || ARCH_SHARK) |
diff --git a/drivers/ide/Makefile b/drivers/ide/Makefile index d0e3d7d5b467..1c326d94aa6d 100644 --- a/drivers/ide/Makefile +++ b/drivers/ide/Makefile | |||
| @@ -116,3 +116,4 @@ obj-$(CONFIG_BLK_DEV_IDE_AU1XXX) += au1xxx-ide.o | |||
| 116 | 116 | ||
| 117 | obj-$(CONFIG_BLK_DEV_IDE_TX4938) += tx4938ide.o | 117 | obj-$(CONFIG_BLK_DEV_IDE_TX4938) += tx4938ide.o |
| 118 | obj-$(CONFIG_BLK_DEV_IDE_TX4939) += tx4939ide.o | 118 | obj-$(CONFIG_BLK_DEV_IDE_TX4939) += tx4939ide.o |
| 119 | obj-$(CONFIG_BLK_DEV_IDE_AT91) += at91_ide.o | ||
diff --git a/drivers/ide/at91_ide.c b/drivers/ide/at91_ide.c new file mode 100644 index 000000000000..1bb50f46388d --- /dev/null +++ b/drivers/ide/at91_ide.c | |||
| @@ -0,0 +1,467 @@ | |||
| 1 | /* | ||
| 2 | * IDE host driver for AT91 (SAM9, CAP9, AT572D940HF) Static Memory Controller | ||
| 3 | * with Compact Flash True IDE logic | ||
| 4 | * | ||
| 5 | * Copyright (c) 2008, 2009 Kelvatek Ltd. | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 20 | * | ||
| 21 | */ | ||
| 22 | |||
| 23 | #include <linux/version.h> | ||
| 24 | #include <linux/kernel.h> | ||
| 25 | #include <linux/module.h> | ||
| 26 | #include <linux/clk.h> | ||
| 27 | #include <linux/err.h> | ||
| 28 | #include <linux/ide.h> | ||
| 29 | #include <linux/platform_device.h> | ||
| 30 | |||
| 31 | #include <mach/board.h> | ||
| 32 | #include <mach/gpio.h> | ||
| 33 | #include <mach/at91sam9263.h> | ||
| 34 | #include <mach/at91sam9_smc.h> | ||
| 35 | #include <mach/at91sam9263_matrix.h> | ||
| 36 | |||
| 37 | #define DRV_NAME "at91_ide" | ||
| 38 | |||
| 39 | #define perr(fmt, args...) pr_err(DRV_NAME ": " fmt, ##args) | ||
| 40 | #define pdbg(fmt, args...) pr_debug("%s " fmt, __func__, ##args) | ||
| 41 | |||
| 42 | /* | ||
| 43 | * Access to IDE device is possible through EBI Static Memory Controller | ||
| 44 | * with Compact Flash logic. For details see EBI and SMC datasheet sections | ||
| 45 | * of any microcontroller from AT91SAM9 family. | ||
| 46 | * | ||
| 47 | * Within SMC chip select address space, lines A[23:21] distinguish Compact | ||
| 48 | * Flash modes (I/O, common memory, attribute memory, True IDE). IDE modes are: | ||
| 49 | * 0x00c0000 - True IDE | ||
| 50 | * 0x00e0000 - Alternate True IDE (Alt Status Register) | ||
| 51 | * | ||
| 52 | * On True IDE mode Task File and Data Register are mapped at the same address. | ||
| 53 | * To distinguish access between these two different bus data width is used: | ||
| 54 | * 8Bit for Task File, 16Bit for Data I/O. | ||
| 55 | * | ||
| 56 | * After initialization we do 8/16 bit flipping (changes in SMC MODE register) | ||
| 57 | * only inside IDE callback routines which are serialized by IDE layer, | ||
| 58 | * so no additional locking needed. | ||
| 59 | */ | ||
| 60 | |||
| 61 | #define TASK_FILE 0x00c00000 | ||
| 62 | #define ALT_MODE 0x00e00000 | ||
| 63 | #define REGS_SIZE 8 | ||
| 64 | |||
| 65 | #define enter_16bit(cs, mode) do { \ | ||
| 66 | mode = at91_sys_read(AT91_SMC_MODE(cs)); \ | ||
| 67 | at91_sys_write(AT91_SMC_MODE(cs), mode | AT91_SMC_DBW_16); \ | ||
| 68 | } while (0) | ||
| 69 | |||
| 70 | #define leave_16bit(cs, mode) at91_sys_write(AT91_SMC_MODE(cs), mode); | ||
| 71 | |||
| 72 | static void set_smc_timings(const u8 chipselect, const u16 cycle, | ||
| 73 | const u16 setup, const u16 pulse, | ||
| 74 | const u16 data_float, int use_iordy) | ||
| 75 | { | ||
| 76 | unsigned long mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | | ||
| 77 | AT91_SMC_BAT_SELECT; | ||
| 78 | |||
| 79 | /* disable or enable waiting for IORDY signal */ | ||
| 80 | if (use_iordy) | ||
| 81 | mode |= AT91_SMC_EXNWMODE_READY; | ||
| 82 | |||
| 83 | /* add data float cycles if needed */ | ||
| 84 | if (data_float) | ||
| 85 | mode |= AT91_SMC_TDF_(data_float); | ||
| 86 | |||
| 87 | at91_sys_write(AT91_SMC_MODE(chipselect), mode); | ||
| 88 | |||
| 89 | /* setup timings in SMC */ | ||
| 90 | at91_sys_write(AT91_SMC_SETUP(chipselect), AT91_SMC_NWESETUP_(setup) | | ||
| 91 | AT91_SMC_NCS_WRSETUP_(0) | | ||
| 92 | AT91_SMC_NRDSETUP_(setup) | | ||
| 93 | AT91_SMC_NCS_RDSETUP_(0)); | ||
| 94 | at91_sys_write(AT91_SMC_PULSE(chipselect), AT91_SMC_NWEPULSE_(pulse) | | ||
| 95 | AT91_SMC_NCS_WRPULSE_(cycle) | | ||
| 96 | AT91_SMC_NRDPULSE_(pulse) | | ||
| 97 | AT91_SMC_NCS_RDPULSE_(cycle)); | ||
| 98 | at91_sys_write(AT91_SMC_CYCLE(chipselect), AT91_SMC_NWECYCLE_(cycle) | | ||
| 99 | AT91_SMC_NRDCYCLE_(cycle)); | ||
| 100 | } | ||
| 101 | |||
| 102 | static unsigned int calc_mck_cycles(unsigned int ns, unsigned int mck_hz) | ||
| 103 | { | ||
| 104 | u64 tmp = ns; | ||
| 105 | |||
| 106 | tmp *= mck_hz; | ||
| 107 | tmp += 1000*1000*1000 - 1; /* round up */ | ||
| 108 | do_div(tmp, 1000*1000*1000); | ||
| 109 | return (unsigned int) tmp; | ||
| 110 | } | ||
| 111 | |||
| 112 | static void apply_timings(const u8 chipselect, const u8 pio, | ||
| 113 | const struct ide_timing *timing, int use_iordy) | ||
| 114 | { | ||
| 115 | unsigned int t0, t1, t2, t6z; | ||
| 116 | unsigned int cycle, setup, pulse, data_float; | ||
| 117 | unsigned int mck_hz; | ||
| 118 | struct clk *mck; | ||
| 119 | |||
| 120 | /* see table 22 of Compact Flash standard 4.1 for the meaning, | ||
| 121 | * we do not stretch active (t2) time, so setup (t1) + hold time (th) | ||
| 122 | * assure at least minimal recovery (t2i) time */ | ||
| 123 | t0 = timing->cyc8b; | ||
| 124 | t1 = timing->setup; | ||
| 125 | t2 = timing->act8b; | ||
| 126 | t6z = (pio < 5) ? 30 : 20; | ||
| 127 | |||
| 128 | pdbg("t0=%u t1=%u t2=%u t6z=%u\n", t0, t1, t2, t6z); | ||
| 129 | |||
| 130 | mck = clk_get(NULL, "mck"); | ||
| 131 | BUG_ON(IS_ERR(mck)); | ||
| 132 | mck_hz = clk_get_rate(mck); | ||
| 133 | pdbg("mck_hz=%u\n", mck_hz); | ||
| 134 | |||
| 135 | cycle = calc_mck_cycles(t0, mck_hz); | ||
| 136 | setup = calc_mck_cycles(t1, mck_hz); | ||
| 137 | pulse = calc_mck_cycles(t2, mck_hz); | ||
| 138 | data_float = calc_mck_cycles(t6z, mck_hz); | ||
| 139 | |||
| 140 | pdbg("cycle=%u setup=%u pulse=%u data_float=%u\n", | ||
| 141 | cycle, setup, pulse, data_float); | ||
| 142 | |||
| 143 | set_smc_timings(chipselect, cycle, setup, pulse, data_float, use_iordy); | ||
| 144 | } | ||
| 145 | |||
| 146 | static void at91_ide_input_data(ide_drive_t *drive, struct request *rq, | ||
| 147 | void *buf, unsigned int len) | ||
| 148 | { | ||
| 149 | ide_hwif_t *hwif = drive->hwif; | ||
| 150 | struct ide_io_ports *io_ports = &hwif->io_ports; | ||
| 151 | u8 chipselect = hwif->select_data; | ||
| 152 | unsigned long mode; | ||
| 153 | |||
| 154 | pdbg("cs %u buf %p len %d\n", chipselect, buf, len); | ||
| 155 | |||
| 156 | len++; | ||
| 157 | |||
| 158 | enter_16bit(chipselect, mode); | ||
| 159 | __ide_mm_insw((void __iomem *) io_ports->data_addr, buf, len / 2); | ||
| 160 | leave_16bit(chipselect, mode); | ||
| 161 | } | ||
| 162 | |||
| 163 | static void at91_ide_output_data(ide_drive_t *drive, struct request *rq, | ||
| 164 | void *buf, unsigned int len) | ||
| 165 | { | ||
| 166 | ide_hwif_t *hwif = drive->hwif; | ||
| 167 | struct ide_io_ports *io_ports = &hwif->io_ports; | ||
| 168 | u8 chipselect = hwif->select_data; | ||
| 169 | unsigned long mode; | ||
| 170 | |||
| 171 | pdbg("cs %u buf %p len %d\n", chipselect, buf, len); | ||
| 172 | |||
| 173 | enter_16bit(chipselect, mode); | ||
| 174 | __ide_mm_outsw((void __iomem *) io_ports->data_addr, buf, len / 2); | ||
| 175 | leave_16bit(chipselect, mode); | ||
| 176 | } | ||
| 177 | |||
| 178 | static u8 ide_mm_inb(unsigned long port) | ||
| 179 | { | ||
| 180 | return readb((void __iomem *) port); | ||
| 181 | } | ||
| 182 | |||
| 183 | static void ide_mm_outb(u8 value, unsigned long port) | ||
| 184 | { | ||
| 185 | writeb(value, (void __iomem *) port); | ||
| 186 | } | ||
| 187 | |||
| 188 | static void at91_ide_tf_load(ide_drive_t *drive, ide_task_t *task) | ||
| 189 | { | ||
| 190 | ide_hwif_t *hwif = drive->hwif; | ||
| 191 | struct ide_io_ports *io_ports = &hwif->io_ports; | ||
| 192 | struct ide_taskfile *tf = &task->tf; | ||
| 193 | u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF; | ||
| 194 | |||
| 195 | if (task->tf_flags & IDE_TFLAG_FLAGGED) | ||
| 196 | HIHI = 0xFF; | ||
| 197 | |||
| 198 | if (task->tf_flags & IDE_TFLAG_OUT_DATA) { | ||
| 199 | u16 data = (tf->hob_data << 8) | tf->data; | ||
| 200 | |||
| 201 | at91_ide_output_data(drive, NULL, &data, 2); | ||
| 202 | } | ||
| 203 | |||
| 204 | if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE) | ||
| 205 | ide_mm_outb(tf->hob_feature, io_ports->feature_addr); | ||
| 206 | if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT) | ||
| 207 | ide_mm_outb(tf->hob_nsect, io_ports->nsect_addr); | ||
| 208 | if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL) | ||
| 209 | ide_mm_outb(tf->hob_lbal, io_ports->lbal_addr); | ||
| 210 | if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM) | ||
| 211 | ide_mm_outb(tf->hob_lbam, io_ports->lbam_addr); | ||
| 212 | if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH) | ||
| 213 | ide_mm_outb(tf->hob_lbah, io_ports->lbah_addr); | ||
| 214 | |||
| 215 | if (task->tf_flags & IDE_TFLAG_OUT_FEATURE) | ||
| 216 | ide_mm_outb(tf->feature, io_ports->feature_addr); | ||
| 217 | if (task->tf_flags & IDE_TFLAG_OUT_NSECT) | ||
| 218 | ide_mm_outb(tf->nsect, io_ports->nsect_addr); | ||
| 219 | if (task->tf_flags & IDE_TFLAG_OUT_LBAL) | ||
| 220 | ide_mm_outb(tf->lbal, io_ports->lbal_addr); | ||
| 221 | if (task->tf_flags & IDE_TFLAG_OUT_LBAM) | ||
| 222 | ide_mm_outb(tf->lbam, io_ports->lbam_addr); | ||
| 223 | if (task->tf_flags & IDE_TFLAG_OUT_LBAH) | ||
| 224 | ide_mm_outb(tf->lbah, io_ports->lbah_addr); | ||
| 225 | |||
| 226 | if (task->tf_flags & IDE_TFLAG_OUT_DEVICE) | ||
| 227 | ide_mm_outb((tf->device & HIHI) | drive->select, io_ports->device_addr); | ||
| 228 | } | ||
| 229 | |||
| 230 | static void at91_ide_tf_read(ide_drive_t *drive, ide_task_t *task) | ||
| 231 | { | ||
| 232 | ide_hwif_t *hwif = drive->hwif; | ||
| 233 | struct ide_io_ports *io_ports = &hwif->io_ports; | ||
| 234 | struct ide_taskfile *tf = &task->tf; | ||
| 235 | |||
| 236 | if (task->tf_flags & IDE_TFLAG_IN_DATA) { | ||
| 237 | u16 data; | ||
| 238 | |||
| 239 | at91_ide_input_data(drive, NULL, &data, 2); | ||
| 240 | tf->data = data & 0xff; | ||
| 241 | tf->hob_data = (data >> 8) & 0xff; | ||
| 242 | } | ||
| 243 | |||
| 244 | /* be sure we're looking at the low order bits */ | ||
| 245 | ide_mm_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr); | ||
| 246 | |||
| 247 | if (task->tf_flags & IDE_TFLAG_IN_FEATURE) | ||
| 248 | tf->feature = ide_mm_inb(io_ports->feature_addr); | ||
| 249 | if (task->tf_flags & IDE_TFLAG_IN_NSECT) | ||
| 250 | tf->nsect = ide_mm_inb(io_ports->nsect_addr); | ||
| 251 | if (task->tf_flags & IDE_TFLAG_IN_LBAL) | ||
| 252 | tf->lbal = ide_mm_inb(io_ports->lbal_addr); | ||
| 253 | if (task->tf_flags & IDE_TFLAG_IN_LBAM) | ||
| 254 | tf->lbam = ide_mm_inb(io_ports->lbam_addr); | ||
| 255 | if (task->tf_flags & IDE_TFLAG_IN_LBAH) | ||
| 256 | tf->lbah = ide_mm_inb(io_ports->lbah_addr); | ||
| 257 | if (task->tf_flags & IDE_TFLAG_IN_DEVICE) | ||
| 258 | tf->device = ide_mm_inb(io_ports->device_addr); | ||
| 259 | |||
| 260 | if (task->tf_flags & IDE_TFLAG_LBA48) { | ||
| 261 | ide_mm_outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr); | ||
| 262 | |||
| 263 | if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE) | ||
| 264 | tf->hob_feature = ide_mm_inb(io_ports->feature_addr); | ||
| 265 | if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT) | ||
| 266 | tf->hob_nsect = ide_mm_inb(io_ports->nsect_addr); | ||
| 267 | if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL) | ||
| 268 | tf->hob_lbal = ide_mm_inb(io_ports->lbal_addr); | ||
| 269 | if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM) | ||
| 270 | tf->hob_lbam = ide_mm_inb(io_ports->lbam_addr); | ||
| 271 | if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH) | ||
| 272 | tf->hob_lbah = ide_mm_inb(io_ports->lbah_addr); | ||
| 273 | } | ||
| 274 | } | ||
| 275 | |||
| 276 | static void at91_ide_set_pio_mode(ide_drive_t *drive, const u8 pio) | ||
| 277 | { | ||
| 278 | struct ide_timing *timing; | ||
| 279 | u8 chipselect = drive->hwif->select_data; | ||
| 280 | int use_iordy = 0; | ||
| 281 | |||
| 282 | pdbg("chipselect %u pio %u\n", chipselect, pio); | ||
| 283 | |||
| 284 | timing = ide_timing_find_mode(XFER_PIO_0 + pio); | ||
| 285 | BUG_ON(!timing); | ||
| 286 | |||
| 287 | if ((pio > 2 || ata_id_has_iordy(drive->id)) && | ||
| 288 | !(ata_id_is_cfa(drive->id) && pio > 4)) | ||
| 289 | use_iordy = 1; | ||
| 290 | |||
| 291 | apply_timings(chipselect, pio, timing, use_iordy); | ||
| 292 | } | ||
| 293 | |||
| 294 | static const struct ide_tp_ops at91_ide_tp_ops = { | ||
| 295 | .exec_command = ide_exec_command, | ||
| 296 | .read_status = ide_read_status, | ||
| 297 | .read_altstatus = ide_read_altstatus, | ||
| 298 | .set_irq = ide_set_irq, | ||
| 299 | |||
| 300 | .tf_load = at91_ide_tf_load, | ||
| 301 | .tf_read = at91_ide_tf_read, | ||
| 302 | |||
| 303 | .input_data = at91_ide_input_data, | ||
| 304 | .output_data = at91_ide_output_data, | ||
| 305 | }; | ||
| 306 | |||
| 307 | static const struct ide_port_ops at91_ide_port_ops = { | ||
| 308 | .set_pio_mode = at91_ide_set_pio_mode, | ||
| 309 | }; | ||
| 310 | |||
| 311 | static const struct ide_port_info at91_ide_port_info __initdata = { | ||
| 312 | .port_ops = &at91_ide_port_ops, | ||
| 313 | .tp_ops = &at91_ide_tp_ops, | ||
| 314 | .host_flags = IDE_HFLAG_MMIO | IDE_HFLAG_NO_DMA | IDE_HFLAG_SINGLE | | ||
| 315 | IDE_HFLAG_NO_IO_32BIT | IDE_HFLAG_UNMASK_IRQS, | ||
| 316 | .pio_mask = ATA_PIO5, | ||
| 317 | }; | ||
| 318 | |||
| 319 | /* | ||
| 320 | * If interrupt is delivered through GPIO, IRQ are triggered on falling | ||
| 321 | * and rising edge of signal. Whereas IDE device request interrupt on high | ||
| 322 | * level (rising edge in our case). This mean we have fake interrupts, so | ||
| 323 | * we need to check interrupt pin and exit instantly from ISR when line | ||
| 324 | * is on low level. | ||
| 325 | */ | ||
| 326 | |||
| 327 | irqreturn_t at91_irq_handler(int irq, void *dev_id) | ||
| 328 | { | ||
| 329 | int ntries = 8; | ||
| 330 | int pin_val1, pin_val2; | ||
| 331 | |||
| 332 | /* additional deglitch, line can be noisy in badly designed PCB */ | ||
| 333 | do { | ||
| 334 | pin_val1 = at91_get_gpio_value(irq); | ||
| 335 | pin_val2 = at91_get_gpio_value(irq); | ||
| 336 | } while (pin_val1 != pin_val2 && --ntries > 0); | ||
| 337 | |||
| 338 | if (pin_val1 == 0 || ntries <= 0) | ||
| 339 | return IRQ_HANDLED; | ||
| 340 | |||
| 341 | return ide_intr(irq, dev_id); | ||
| 342 | } | ||
| 343 | |||
| 344 | static int __init at91_ide_probe(struct platform_device *pdev) | ||
| 345 | { | ||
| 346 | int ret; | ||
| 347 | hw_regs_t hw; | ||
| 348 | hw_regs_t *hws[] = { &hw, NULL, NULL, NULL }; | ||
| 349 | struct ide_host *host; | ||
| 350 | struct resource *res; | ||
| 351 | unsigned long tf_base = 0, ctl_base = 0; | ||
| 352 | struct at91_cf_data *board = pdev->dev.platform_data; | ||
| 353 | |||
| 354 | if (!board) | ||
| 355 | return -ENODEV; | ||
| 356 | |||
| 357 | if (board->det_pin && at91_get_gpio_value(board->det_pin) != 0) { | ||
| 358 | perr("no device detected\n"); | ||
| 359 | return -ENODEV; | ||
| 360 | } | ||
| 361 | |||
| 362 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 363 | if (!res) { | ||
| 364 | perr("can't get memory resource\n"); | ||
| 365 | return -ENODEV; | ||
| 366 | } | ||
| 367 | |||
| 368 | if (!devm_request_mem_region(&pdev->dev, res->start + TASK_FILE, | ||
| 369 | REGS_SIZE, "ide") || | ||
| 370 | !devm_request_mem_region(&pdev->dev, res->start + ALT_MODE, | ||
| 371 | REGS_SIZE, "alt")) { | ||
| 372 | perr("memory resources in use\n"); | ||
| 373 | return -EBUSY; | ||
| 374 | } | ||
| 375 | |||
| 376 | pdbg("chipselect %u irq %u res %08lx\n", board->chipselect, | ||
| 377 | board->irq_pin, (unsigned long) res->start); | ||
| 378 | |||
| 379 | tf_base = (unsigned long) devm_ioremap(&pdev->dev, res->start + TASK_FILE, | ||
| 380 | REGS_SIZE); | ||
| 381 | ctl_base = (unsigned long) devm_ioremap(&pdev->dev, res->start + ALT_MODE, | ||
| 382 | REGS_SIZE); | ||
| 383 | if (!tf_base || !ctl_base) { | ||
| 384 | perr("can't map memory regions\n"); | ||
| 385 | return -EBUSY; | ||
| 386 | } | ||
| 387 | |||
| 388 | memset(&hw, 0, sizeof(hw)); | ||
| 389 | |||
| 390 | if (board->flags & AT91_IDE_SWAP_A0_A2) { | ||
| 391 | /* workaround for stupid hardware bug */ | ||
| 392 | hw.io_ports.data_addr = tf_base + 0; | ||
| 393 | hw.io_ports.error_addr = tf_base + 4; | ||
| 394 | hw.io_ports.nsect_addr = tf_base + 2; | ||
| 395 | hw.io_ports.lbal_addr = tf_base + 6; | ||
| 396 | hw.io_ports.lbam_addr = tf_base + 1; | ||
| 397 | hw.io_ports.lbah_addr = tf_base + 5; | ||
| 398 | hw.io_ports.device_addr = tf_base + 3; | ||
| 399 | hw.io_ports.command_addr = tf_base + 7; | ||
| 400 | hw.io_ports.ctl_addr = ctl_base + 3; | ||
| 401 | } else | ||
| 402 | ide_std_init_ports(&hw, tf_base, ctl_base + 6); | ||
| 403 | |||
| 404 | hw.irq = board->irq_pin; | ||
| 405 | hw.chipset = ide_generic; | ||
| 406 | hw.dev = &pdev->dev; | ||
| 407 | |||
| 408 | host = ide_host_alloc(&at91_ide_port_info, hws); | ||
| 409 | if (!host) { | ||
| 410 | perr("failed to allocate ide host\n"); | ||
| 411 | return -ENOMEM; | ||
| 412 | } | ||
| 413 | |||
| 414 | /* setup Static Memory Controller - PIO 0 as default */ | ||
| 415 | apply_timings(board->chipselect, 0, ide_timing_find_mode(XFER_PIO_0), 0); | ||
| 416 | |||
| 417 | /* with GPIO interrupt we have to do quirks in handler */ | ||
| 418 | if (board->irq_pin >= PIN_BASE) | ||
| 419 | host->irq_handler = at91_irq_handler; | ||
| 420 | |||
| 421 | host->ports[0]->select_data = board->chipselect; | ||
| 422 | |||
| 423 | ret = ide_host_register(host, &at91_ide_port_info, hws); | ||
| 424 | if (ret) { | ||
| 425 | perr("failed to register ide host\n"); | ||
| 426 | goto err_free_host; | ||
| 427 | } | ||
| 428 | platform_set_drvdata(pdev, host); | ||
| 429 | return 0; | ||
| 430 | |||
| 431 | err_free_host: | ||
| 432 | ide_host_free(host); | ||
| 433 | return ret; | ||
| 434 | } | ||
| 435 | |||
| 436 | static int __exit at91_ide_remove(struct platform_device *pdev) | ||
| 437 | { | ||
| 438 | struct ide_host *host = platform_get_drvdata(pdev); | ||
| 439 | |||
| 440 | ide_host_remove(host); | ||
| 441 | return 0; | ||
| 442 | } | ||
| 443 | |||
| 444 | static struct platform_driver at91_ide_driver = { | ||
| 445 | .driver = { | ||
| 446 | .name = DRV_NAME, | ||
| 447 | .owner = THIS_MODULE, | ||
| 448 | }, | ||
| 449 | .remove = __exit_p(at91_ide_remove), | ||
| 450 | }; | ||
| 451 | |||
| 452 | static int __init at91_ide_init(void) | ||
| 453 | { | ||
| 454 | return platform_driver_probe(&at91_ide_driver, at91_ide_probe); | ||
| 455 | } | ||
| 456 | |||
| 457 | static void __exit at91_ide_exit(void) | ||
| 458 | { | ||
| 459 | platform_driver_unregister(&at91_ide_driver); | ||
| 460 | } | ||
| 461 | |||
| 462 | module_init(at91_ide_init); | ||
| 463 | module_exit(at91_ide_exit); | ||
| 464 | |||
| 465 | MODULE_LICENSE("GPL"); | ||
| 466 | MODULE_AUTHOR("Stanislaw Gruszka <stf_xl@wp.pl>"); | ||
| 467 | |||
diff --git a/drivers/ide/ide-atapi.c b/drivers/ide/ide-atapi.c index e96c01260598..e9d042dba0e0 100644 --- a/drivers/ide/ide-atapi.c +++ b/drivers/ide/ide-atapi.c | |||
| @@ -140,6 +140,12 @@ static void ide_queue_pc_head(ide_drive_t *drive, struct gendisk *disk, | |||
| 140 | rq->cmd_flags |= REQ_PREEMPT; | 140 | rq->cmd_flags |= REQ_PREEMPT; |
| 141 | rq->buffer = (char *)pc; | 141 | rq->buffer = (char *)pc; |
| 142 | rq->rq_disk = disk; | 142 | rq->rq_disk = disk; |
| 143 | |||
| 144 | if (pc->req_xfer) { | ||
| 145 | rq->data = pc->buf; | ||
| 146 | rq->data_len = pc->req_xfer; | ||
| 147 | } | ||
| 148 | |||
| 143 | memcpy(rq->cmd, pc->c, 12); | 149 | memcpy(rq->cmd, pc->c, 12); |
| 144 | if (drive->media == ide_tape) | 150 | if (drive->media == ide_tape) |
| 145 | rq->cmd[13] = REQ_IDETAPE_PC1; | 151 | rq->cmd[13] = REQ_IDETAPE_PC1; |
| @@ -159,6 +165,12 @@ int ide_queue_pc_tail(ide_drive_t *drive, struct gendisk *disk, | |||
| 159 | rq = blk_get_request(drive->queue, READ, __GFP_WAIT); | 165 | rq = blk_get_request(drive->queue, READ, __GFP_WAIT); |
| 160 | rq->cmd_type = REQ_TYPE_SPECIAL; | 166 | rq->cmd_type = REQ_TYPE_SPECIAL; |
| 161 | rq->buffer = (char *)pc; | 167 | rq->buffer = (char *)pc; |
| 168 | |||
| 169 | if (pc->req_xfer) { | ||
| 170 | rq->data = pc->buf; | ||
| 171 | rq->data_len = pc->req_xfer; | ||
| 172 | } | ||
| 173 | |||
| 162 | memcpy(rq->cmd, pc->c, 12); | 174 | memcpy(rq->cmd, pc->c, 12); |
| 163 | if (drive->media == ide_tape) | 175 | if (drive->media == ide_tape) |
| 164 | rq->cmd[13] = REQ_IDETAPE_PC1; | 176 | rq->cmd[13] = REQ_IDETAPE_PC1; |
diff --git a/drivers/ide/ide-disk_proc.c b/drivers/ide/ide-disk_proc.c index 1146f4204c6e..1f86dcbd2b1c 100644 --- a/drivers/ide/ide-disk_proc.c +++ b/drivers/ide/ide-disk_proc.c | |||
| @@ -125,5 +125,5 @@ const struct ide_proc_devset ide_disk_settings[] = { | |||
| 125 | IDE_PROC_DEVSET(multcount, 0, 16), | 125 | IDE_PROC_DEVSET(multcount, 0, 16), |
| 126 | IDE_PROC_DEVSET(nowerr, 0, 1), | 126 | IDE_PROC_DEVSET(nowerr, 0, 1), |
| 127 | IDE_PROC_DEVSET(wcache, 0, 1), | 127 | IDE_PROC_DEVSET(wcache, 0, 1), |
| 128 | { 0 }, | 128 | { NULL }, |
| 129 | }; | 129 | }; |
diff --git a/drivers/ide/ide-dma.c b/drivers/ide/ide-dma.c index 72ebab0bc755..059c90bb5ad2 100644 --- a/drivers/ide/ide-dma.c +++ b/drivers/ide/ide-dma.c | |||
| @@ -128,6 +128,7 @@ int ide_build_sglist(ide_drive_t *drive, struct request *rq) | |||
| 128 | { | 128 | { |
| 129 | ide_hwif_t *hwif = drive->hwif; | 129 | ide_hwif_t *hwif = drive->hwif; |
| 130 | struct scatterlist *sg = hwif->sg_table; | 130 | struct scatterlist *sg = hwif->sg_table; |
| 131 | int i; | ||
| 131 | 132 | ||
| 132 | ide_map_sg(drive, rq); | 133 | ide_map_sg(drive, rq); |
| 133 | 134 | ||
| @@ -136,8 +137,13 @@ int ide_build_sglist(ide_drive_t *drive, struct request *rq) | |||
| 136 | else | 137 | else |
| 137 | hwif->sg_dma_direction = DMA_TO_DEVICE; | 138 | hwif->sg_dma_direction = DMA_TO_DEVICE; |
| 138 | 139 | ||
| 139 | return dma_map_sg(hwif->dev, sg, hwif->sg_nents, | 140 | i = dma_map_sg(hwif->dev, sg, hwif->sg_nents, hwif->sg_dma_direction); |
| 140 | hwif->sg_dma_direction); | 141 | if (i) { |
| 142 | hwif->orig_sg_nents = hwif->sg_nents; | ||
| 143 | hwif->sg_nents = i; | ||
| 144 | } | ||
| 145 | |||
| 146 | return i; | ||
| 141 | } | 147 | } |
| 142 | EXPORT_SYMBOL_GPL(ide_build_sglist); | 148 | EXPORT_SYMBOL_GPL(ide_build_sglist); |
| 143 | 149 | ||
| @@ -156,7 +162,7 @@ void ide_destroy_dmatable(ide_drive_t *drive) | |||
| 156 | { | 162 | { |
| 157 | ide_hwif_t *hwif = drive->hwif; | 163 | ide_hwif_t *hwif = drive->hwif; |
| 158 | 164 | ||
| 159 | dma_unmap_sg(hwif->dev, hwif->sg_table, hwif->sg_nents, | 165 | dma_unmap_sg(hwif->dev, hwif->sg_table, hwif->orig_sg_nents, |
| 160 | hwif->sg_dma_direction); | 166 | hwif->sg_dma_direction); |
| 161 | } | 167 | } |
| 162 | EXPORT_SYMBOL_GPL(ide_destroy_dmatable); | 168 | EXPORT_SYMBOL_GPL(ide_destroy_dmatable); |
diff --git a/drivers/ide/ide-floppy.c b/drivers/ide/ide-floppy.c index 3eab1c6c9b31..317ec62c33d4 100644 --- a/drivers/ide/ide-floppy.c +++ b/drivers/ide/ide-floppy.c | |||
| @@ -327,8 +327,10 @@ static ide_startstop_t ide_floppy_do_request(ide_drive_t *drive, | |||
| 327 | return ide_stopped; | 327 | return ide_stopped; |
| 328 | } | 328 | } |
| 329 | 329 | ||
| 330 | ide_init_sg_cmd(drive, rq); | 330 | if (blk_fs_request(rq) || pc->req_xfer) { |
| 331 | ide_map_sg(drive, rq); | 331 | ide_init_sg_cmd(drive, rq); |
| 332 | ide_map_sg(drive, rq); | ||
| 333 | } | ||
| 332 | 334 | ||
| 333 | pc->sg = hwif->sg_table; | 335 | pc->sg = hwif->sg_table; |
| 334 | pc->sg_cnt = hwif->sg_nents; | 336 | pc->sg_cnt = hwif->sg_nents; |
diff --git a/drivers/ide/ide-floppy_proc.c b/drivers/ide/ide-floppy_proc.c index 3ec762cb60ab..fcd4d8153df5 100644 --- a/drivers/ide/ide-floppy_proc.c +++ b/drivers/ide/ide-floppy_proc.c | |||
| @@ -29,5 +29,5 @@ const struct ide_proc_devset ide_floppy_settings[] = { | |||
| 29 | IDE_PROC_DEVSET(bios_head, 0, 255), | 29 | IDE_PROC_DEVSET(bios_head, 0, 255), |
| 30 | IDE_PROC_DEVSET(bios_sect, 0, 63), | 30 | IDE_PROC_DEVSET(bios_sect, 0, 63), |
| 31 | IDE_PROC_DEVSET(ticks, 0, 255), | 31 | IDE_PROC_DEVSET(ticks, 0, 255), |
| 32 | { 0 }, | 32 | { NULL }, |
| 33 | }; | 33 | }; |
diff --git a/drivers/ide/ide-io.c b/drivers/ide/ide-io.c index 9ee51adf567f..a9a6c208288a 100644 --- a/drivers/ide/ide-io.c +++ b/drivers/ide/ide-io.c | |||
| @@ -908,7 +908,7 @@ void ide_timer_expiry (unsigned long data) | |||
| 908 | ide_drive_t *uninitialized_var(drive); | 908 | ide_drive_t *uninitialized_var(drive); |
| 909 | ide_handler_t *handler; | 909 | ide_handler_t *handler; |
| 910 | unsigned long flags; | 910 | unsigned long flags; |
| 911 | unsigned long wait = -1; | 911 | int wait = -1; |
| 912 | int plug_device = 0; | 912 | int plug_device = 0; |
| 913 | 913 | ||
| 914 | spin_lock_irqsave(&hwif->lock, flags); | 914 | spin_lock_irqsave(&hwif->lock, flags); |
| @@ -1162,6 +1162,7 @@ out_early: | |||
| 1162 | 1162 | ||
| 1163 | return irq_ret; | 1163 | return irq_ret; |
| 1164 | } | 1164 | } |
| 1165 | EXPORT_SYMBOL_GPL(ide_intr); | ||
| 1165 | 1166 | ||
| 1166 | /** | 1167 | /** |
| 1167 | * ide_do_drive_cmd - issue IDE special command | 1168 | * ide_do_drive_cmd - issue IDE special command |
diff --git a/drivers/ide/ide-iops.c b/drivers/ide/ide-iops.c index 753b92ebe0ae..b1892bd95c6f 100644 --- a/drivers/ide/ide-iops.c +++ b/drivers/ide/ide-iops.c | |||
| @@ -315,6 +315,8 @@ void ide_output_data(ide_drive_t *drive, struct request *rq, void *buf, | |||
| 315 | u8 io_32bit = drive->io_32bit; | 315 | u8 io_32bit = drive->io_32bit; |
| 316 | u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; | 316 | u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0; |
| 317 | 317 | ||
| 318 | len++; | ||
| 319 | |||
| 318 | if (io_32bit) { | 320 | if (io_32bit) { |
| 319 | unsigned long uninitialized_var(flags); | 321 | unsigned long uninitialized_var(flags); |
| 320 | 322 | ||
diff --git a/drivers/ide/ide-probe.c b/drivers/ide/ide-probe.c index ce0818a993f6..ee8e3e7cad51 100644 --- a/drivers/ide/ide-probe.c +++ b/drivers/ide/ide-probe.c | |||
| @@ -950,6 +950,7 @@ static int ide_port_setup_devices(ide_hwif_t *hwif) | |||
| 950 | static int init_irq (ide_hwif_t *hwif) | 950 | static int init_irq (ide_hwif_t *hwif) |
| 951 | { | 951 | { |
| 952 | struct ide_io_ports *io_ports = &hwif->io_ports; | 952 | struct ide_io_ports *io_ports = &hwif->io_ports; |
| 953 | irq_handler_t irq_handler; | ||
| 953 | int sa = 0; | 954 | int sa = 0; |
| 954 | 955 | ||
| 955 | mutex_lock(&ide_cfg_mtx); | 956 | mutex_lock(&ide_cfg_mtx); |
| @@ -959,6 +960,10 @@ static int init_irq (ide_hwif_t *hwif) | |||
| 959 | hwif->timer.function = &ide_timer_expiry; | 960 | hwif->timer.function = &ide_timer_expiry; |
| 960 | hwif->timer.data = (unsigned long)hwif; | 961 | hwif->timer.data = (unsigned long)hwif; |
| 961 | 962 | ||
| 963 | irq_handler = hwif->host->irq_handler; | ||
| 964 | if (irq_handler == NULL) | ||
| 965 | irq_handler = ide_intr; | ||
| 966 | |||
| 962 | #if defined(__mc68000__) | 967 | #if defined(__mc68000__) |
| 963 | sa = IRQF_SHARED; | 968 | sa = IRQF_SHARED; |
| 964 | #endif /* __mc68000__ */ | 969 | #endif /* __mc68000__ */ |
| @@ -969,7 +974,7 @@ static int init_irq (ide_hwif_t *hwif) | |||
| 969 | if (io_ports->ctl_addr) | 974 | if (io_ports->ctl_addr) |
| 970 | hwif->tp_ops->set_irq(hwif, 1); | 975 | hwif->tp_ops->set_irq(hwif, 1); |
| 971 | 976 | ||
| 972 | if (request_irq(hwif->irq, &ide_intr, sa, hwif->name, hwif)) | 977 | if (request_irq(hwif->irq, irq_handler, sa, hwif->name, hwif)) |
| 973 | goto out_up; | 978 | goto out_up; |
| 974 | 979 | ||
| 975 | if (!hwif->rqsize) { | 980 | if (!hwif->rqsize) { |
diff --git a/drivers/ide/ide-proc.c b/drivers/ide/ide-proc.c index 1d8978b3314a..a7b9287ee0d4 100644 --- a/drivers/ide/ide-proc.c +++ b/drivers/ide/ide-proc.c | |||
| @@ -231,7 +231,7 @@ static const struct ide_proc_devset ide_generic_settings[] = { | |||
| 231 | IDE_PROC_DEVSET(pio_mode, 0, 255), | 231 | IDE_PROC_DEVSET(pio_mode, 0, 255), |
| 232 | IDE_PROC_DEVSET(unmaskirq, 0, 1), | 232 | IDE_PROC_DEVSET(unmaskirq, 0, 1), |
| 233 | IDE_PROC_DEVSET(using_dma, 0, 1), | 233 | IDE_PROC_DEVSET(using_dma, 0, 1), |
| 234 | { 0 }, | 234 | { NULL }, |
| 235 | }; | 235 | }; |
| 236 | 236 | ||
| 237 | static void proc_ide_settings_warn(void) | 237 | static void proc_ide_settings_warn(void) |
diff --git a/drivers/ide/ide-tape.c b/drivers/ide/ide-tape.c index bb450a7608c2..4e6181c7bbda 100644 --- a/drivers/ide/ide-tape.c +++ b/drivers/ide/ide-tape.c | |||
| @@ -2166,7 +2166,7 @@ static const struct ide_proc_devset idetape_settings[] = { | |||
| 2166 | __IDE_PROC_DEVSET(speed, 0, 0xffff, NULL, NULL), | 2166 | __IDE_PROC_DEVSET(speed, 0, 0xffff, NULL, NULL), |
| 2167 | __IDE_PROC_DEVSET(tdsc, IDETAPE_DSC_RW_MIN, IDETAPE_DSC_RW_MAX, | 2167 | __IDE_PROC_DEVSET(tdsc, IDETAPE_DSC_RW_MIN, IDETAPE_DSC_RW_MAX, |
| 2168 | mulf_tdsc, divf_tdsc), | 2168 | mulf_tdsc, divf_tdsc), |
| 2169 | { 0 }, | 2169 | { NULL }, |
| 2170 | }; | 2170 | }; |
| 2171 | #endif | 2171 | #endif |
| 2172 | 2172 | ||
diff --git a/drivers/infiniband/hw/nes/nes_cm.c b/drivers/infiniband/hw/nes/nes_cm.c index a01b4488208b..4a65b96db2c8 100644 --- a/drivers/infiniband/hw/nes/nes_cm.c +++ b/drivers/infiniband/hw/nes/nes_cm.c | |||
| @@ -2490,12 +2490,14 @@ static int nes_disconnect(struct nes_qp *nesqp, int abrupt) | |||
| 2490 | int ret = 0; | 2490 | int ret = 0; |
| 2491 | struct nes_vnic *nesvnic; | 2491 | struct nes_vnic *nesvnic; |
| 2492 | struct nes_device *nesdev; | 2492 | struct nes_device *nesdev; |
| 2493 | struct nes_ib_device *nesibdev; | ||
| 2493 | 2494 | ||
| 2494 | nesvnic = to_nesvnic(nesqp->ibqp.device); | 2495 | nesvnic = to_nesvnic(nesqp->ibqp.device); |
| 2495 | if (!nesvnic) | 2496 | if (!nesvnic) |
| 2496 | return -EINVAL; | 2497 | return -EINVAL; |
| 2497 | 2498 | ||
| 2498 | nesdev = nesvnic->nesdev; | 2499 | nesdev = nesvnic->nesdev; |
| 2500 | nesibdev = nesvnic->nesibdev; | ||
| 2499 | 2501 | ||
| 2500 | nes_debug(NES_DBG_CM, "netdev refcnt = %u.\n", | 2502 | nes_debug(NES_DBG_CM, "netdev refcnt = %u.\n", |
| 2501 | atomic_read(&nesvnic->netdev->refcnt)); | 2503 | atomic_read(&nesvnic->netdev->refcnt)); |
| @@ -2507,6 +2509,8 @@ static int nes_disconnect(struct nes_qp *nesqp, int abrupt) | |||
| 2507 | } else { | 2509 | } else { |
| 2508 | /* Need to free the Last Streaming Mode Message */ | 2510 | /* Need to free the Last Streaming Mode Message */ |
| 2509 | if (nesqp->ietf_frame) { | 2511 | if (nesqp->ietf_frame) { |
| 2512 | if (nesqp->lsmm_mr) | ||
| 2513 | nesibdev->ibdev.dereg_mr(nesqp->lsmm_mr); | ||
| 2510 | pci_free_consistent(nesdev->pcidev, | 2514 | pci_free_consistent(nesdev->pcidev, |
| 2511 | nesqp->private_data_len+sizeof(struct ietf_mpa_frame), | 2515 | nesqp->private_data_len+sizeof(struct ietf_mpa_frame), |
| 2512 | nesqp->ietf_frame, nesqp->ietf_frame_pbase); | 2516 | nesqp->ietf_frame, nesqp->ietf_frame_pbase); |
| @@ -2543,6 +2547,12 @@ int nes_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param) | |||
| 2543 | u32 crc_value; | 2547 | u32 crc_value; |
| 2544 | int ret; | 2548 | int ret; |
| 2545 | int passive_state; | 2549 | int passive_state; |
| 2550 | struct nes_ib_device *nesibdev; | ||
| 2551 | struct ib_mr *ibmr = NULL; | ||
| 2552 | struct ib_phys_buf ibphysbuf; | ||
| 2553 | struct nes_pd *nespd; | ||
| 2554 | |||
| 2555 | |||
| 2546 | 2556 | ||
| 2547 | ibqp = nes_get_qp(cm_id->device, conn_param->qpn); | 2557 | ibqp = nes_get_qp(cm_id->device, conn_param->qpn); |
| 2548 | if (!ibqp) | 2558 | if (!ibqp) |
| @@ -2601,6 +2611,26 @@ int nes_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param) | |||
| 2601 | if (cm_id->remote_addr.sin_addr.s_addr != | 2611 | if (cm_id->remote_addr.sin_addr.s_addr != |
| 2602 | cm_id->local_addr.sin_addr.s_addr) { | 2612 | cm_id->local_addr.sin_addr.s_addr) { |
| 2603 | u64temp = (unsigned long)nesqp; | 2613 | u64temp = (unsigned long)nesqp; |
| 2614 | nesibdev = nesvnic->nesibdev; | ||
| 2615 | nespd = nesqp->nespd; | ||
| 2616 | ibphysbuf.addr = nesqp->ietf_frame_pbase; | ||
| 2617 | ibphysbuf.size = conn_param->private_data_len + | ||
| 2618 | sizeof(struct ietf_mpa_frame); | ||
| 2619 | ibmr = nesibdev->ibdev.reg_phys_mr((struct ib_pd *)nespd, | ||
| 2620 | &ibphysbuf, 1, | ||
| 2621 | IB_ACCESS_LOCAL_WRITE, | ||
| 2622 | (u64 *)&nesqp->ietf_frame); | ||
| 2623 | if (!ibmr) { | ||
| 2624 | nes_debug(NES_DBG_CM, "Unable to register memory region" | ||
| 2625 | "for lSMM for cm_node = %p \n", | ||
| 2626 | cm_node); | ||
| 2627 | return -ENOMEM; | ||
| 2628 | } | ||
| 2629 | |||
| 2630 | ibmr->pd = &nespd->ibpd; | ||
| 2631 | ibmr->device = nespd->ibpd.device; | ||
| 2632 | nesqp->lsmm_mr = ibmr; | ||
| 2633 | |||
| 2604 | u64temp |= NES_SW_CONTEXT_ALIGN>>1; | 2634 | u64temp |= NES_SW_CONTEXT_ALIGN>>1; |
| 2605 | set_wqe_64bit_value(wqe->wqe_words, | 2635 | set_wqe_64bit_value(wqe->wqe_words, |
| 2606 | NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX, | 2636 | NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX, |
| @@ -2611,14 +2641,13 @@ int nes_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param) | |||
| 2611 | wqe->wqe_words[NES_IWARP_SQ_WQE_TOTAL_PAYLOAD_IDX] = | 2641 | wqe->wqe_words[NES_IWARP_SQ_WQE_TOTAL_PAYLOAD_IDX] = |
| 2612 | cpu_to_le32(conn_param->private_data_len + | 2642 | cpu_to_le32(conn_param->private_data_len + |
| 2613 | sizeof(struct ietf_mpa_frame)); | 2643 | sizeof(struct ietf_mpa_frame)); |
| 2614 | wqe->wqe_words[NES_IWARP_SQ_WQE_FRAG0_LOW_IDX] = | 2644 | set_wqe_64bit_value(wqe->wqe_words, |
| 2615 | cpu_to_le32((u32)nesqp->ietf_frame_pbase); | 2645 | NES_IWARP_SQ_WQE_FRAG0_LOW_IDX, |
| 2616 | wqe->wqe_words[NES_IWARP_SQ_WQE_FRAG0_HIGH_IDX] = | 2646 | (u64)nesqp->ietf_frame); |
| 2617 | cpu_to_le32((u32)((u64)nesqp->ietf_frame_pbase >> 32)); | ||
| 2618 | wqe->wqe_words[NES_IWARP_SQ_WQE_LENGTH0_IDX] = | 2647 | wqe->wqe_words[NES_IWARP_SQ_WQE_LENGTH0_IDX] = |
| 2619 | cpu_to_le32(conn_param->private_data_len + | 2648 | cpu_to_le32(conn_param->private_data_len + |
| 2620 | sizeof(struct ietf_mpa_frame)); | 2649 | sizeof(struct ietf_mpa_frame)); |
| 2621 | wqe->wqe_words[NES_IWARP_SQ_WQE_STAG0_IDX] = 0; | 2650 | wqe->wqe_words[NES_IWARP_SQ_WQE_STAG0_IDX] = ibmr->lkey; |
| 2622 | 2651 | ||
| 2623 | nesqp->nesqp_context->ird_ord_sizes |= | 2652 | nesqp->nesqp_context->ird_ord_sizes |= |
| 2624 | cpu_to_le32(NES_QPCONTEXT_ORDIRD_LSMM_PRESENT | | 2653 | cpu_to_le32(NES_QPCONTEXT_ORDIRD_LSMM_PRESENT | |
diff --git a/drivers/infiniband/hw/nes/nes_verbs.c b/drivers/infiniband/hw/nes/nes_verbs.c index 4fdb72454f94..d93a6562817c 100644 --- a/drivers/infiniband/hw/nes/nes_verbs.c +++ b/drivers/infiniband/hw/nes/nes_verbs.c | |||
| @@ -1360,8 +1360,10 @@ static struct ib_qp *nes_create_qp(struct ib_pd *ibpd, | |||
| 1360 | NES_QPCONTEXT_MISC_RQ_SIZE_SHIFT); | 1360 | NES_QPCONTEXT_MISC_RQ_SIZE_SHIFT); |
| 1361 | nesqp->nesqp_context->misc |= cpu_to_le32((u32)nesqp->hwqp.sq_encoded_size << | 1361 | nesqp->nesqp_context->misc |= cpu_to_le32((u32)nesqp->hwqp.sq_encoded_size << |
| 1362 | NES_QPCONTEXT_MISC_SQ_SIZE_SHIFT); | 1362 | NES_QPCONTEXT_MISC_SQ_SIZE_SHIFT); |
| 1363 | if (!udata) { | ||
| 1363 | nesqp->nesqp_context->misc |= cpu_to_le32(NES_QPCONTEXT_MISC_PRIV_EN); | 1364 | nesqp->nesqp_context->misc |= cpu_to_le32(NES_QPCONTEXT_MISC_PRIV_EN); |
| 1364 | nesqp->nesqp_context->misc |= cpu_to_le32(NES_QPCONTEXT_MISC_FAST_REGISTER_EN); | 1365 | nesqp->nesqp_context->misc |= cpu_to_le32(NES_QPCONTEXT_MISC_FAST_REGISTER_EN); |
| 1366 | } | ||
| 1365 | nesqp->nesqp_context->cqs = cpu_to_le32(nesqp->nesscq->hw_cq.cq_number + | 1367 | nesqp->nesqp_context->cqs = cpu_to_le32(nesqp->nesscq->hw_cq.cq_number + |
| 1366 | ((u32)nesqp->nesrcq->hw_cq.cq_number << 16)); | 1368 | ((u32)nesqp->nesrcq->hw_cq.cq_number << 16)); |
| 1367 | u64temp = (u64)nesqp->hwqp.sq_pbase; | 1369 | u64temp = (u64)nesqp->hwqp.sq_pbase; |
diff --git a/drivers/infiniband/hw/nes/nes_verbs.h b/drivers/infiniband/hw/nes/nes_verbs.h index 6c6b4da5184f..ae0ca9bc83bd 100644 --- a/drivers/infiniband/hw/nes/nes_verbs.h +++ b/drivers/infiniband/hw/nes/nes_verbs.h | |||
| @@ -134,6 +134,7 @@ struct nes_qp { | |||
| 134 | struct ietf_mpa_frame *ietf_frame; | 134 | struct ietf_mpa_frame *ietf_frame; |
| 135 | dma_addr_t ietf_frame_pbase; | 135 | dma_addr_t ietf_frame_pbase; |
| 136 | wait_queue_head_t state_waitq; | 136 | wait_queue_head_t state_waitq; |
| 137 | struct ib_mr *lsmm_mr; | ||
| 137 | unsigned long socket; | 138 | unsigned long socket; |
| 138 | struct nes_hw_qp hwqp; | 139 | struct nes_hw_qp hwqp; |
| 139 | struct work_struct work; | 140 | struct work_struct work; |
diff --git a/drivers/input/keyboard/corgikbd.c b/drivers/input/keyboard/corgikbd.c index abb04c82c622..634af6a8e6b3 100644 --- a/drivers/input/keyboard/corgikbd.c +++ b/drivers/input/keyboard/corgikbd.c | |||
| @@ -21,8 +21,6 @@ | |||
| 21 | #include <linux/slab.h> | 21 | #include <linux/slab.h> |
| 22 | 22 | ||
| 23 | #include <mach/corgi.h> | 23 | #include <mach/corgi.h> |
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/pxa-regs.h> | ||
| 26 | #include <mach/pxa2xx-gpio.h> | 24 | #include <mach/pxa2xx-gpio.h> |
| 27 | #include <asm/hardware/scoop.h> | 25 | #include <asm/hardware/scoop.h> |
| 28 | 26 | ||
diff --git a/drivers/input/keyboard/spitzkbd.c b/drivers/input/keyboard/spitzkbd.c index 9d1781a618e9..13967422658c 100644 --- a/drivers/input/keyboard/spitzkbd.c +++ b/drivers/input/keyboard/spitzkbd.c | |||
| @@ -21,8 +21,6 @@ | |||
| 21 | #include <linux/slab.h> | 21 | #include <linux/slab.h> |
| 22 | 22 | ||
| 23 | #include <mach/spitz.h> | 23 | #include <mach/spitz.h> |
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/pxa-regs.h> | ||
| 26 | #include <mach/pxa2xx-gpio.h> | 24 | #include <mach/pxa2xx-gpio.h> |
| 27 | 25 | ||
| 28 | #define KB_ROWS 7 | 26 | #define KB_ROWS 7 |
diff --git a/drivers/input/mouse/rpcmouse.c b/drivers/input/mouse/rpcmouse.c index 56c079ef5018..272deddc8db6 100644 --- a/drivers/input/mouse/rpcmouse.c +++ b/drivers/input/mouse/rpcmouse.c | |||
| @@ -22,10 +22,10 @@ | |||
| 22 | #include <linux/interrupt.h> | 22 | #include <linux/interrupt.h> |
| 23 | #include <linux/init.h> | 23 | #include <linux/init.h> |
| 24 | #include <linux/input.h> | 24 | #include <linux/input.h> |
| 25 | #include <linux/io.h> | ||
| 25 | 26 | ||
| 26 | #include <mach/hardware.h> | 27 | #include <mach/hardware.h> |
| 27 | #include <asm/irq.h> | 28 | #include <asm/irq.h> |
| 28 | #include <asm/io.h> | ||
| 29 | #include <asm/hardware/iomd.h> | 29 | #include <asm/hardware/iomd.h> |
| 30 | 30 | ||
| 31 | MODULE_AUTHOR("Vojtech Pavlik, Russell King"); | 31 | MODULE_AUTHOR("Vojtech Pavlik, Russell King"); |
diff --git a/drivers/input/serio/rpckbd.c b/drivers/input/serio/rpckbd.c index 7f36edd34f8b..ed045c99f84b 100644 --- a/drivers/input/serio/rpckbd.c +++ b/drivers/input/serio/rpckbd.c | |||
| @@ -33,10 +33,10 @@ | |||
| 33 | #include <linux/serio.h> | 33 | #include <linux/serio.h> |
| 34 | #include <linux/err.h> | 34 | #include <linux/err.h> |
| 35 | #include <linux/platform_device.h> | 35 | #include <linux/platform_device.h> |
| 36 | #include <linux/io.h> | ||
| 36 | 37 | ||
| 37 | #include <asm/irq.h> | 38 | #include <asm/irq.h> |
| 38 | #include <mach/hardware.h> | 39 | #include <mach/hardware.h> |
| 39 | #include <asm/io.h> | ||
| 40 | #include <asm/hardware/iomd.h> | 40 | #include <asm/hardware/iomd.h> |
| 41 | #include <asm/system.h> | 41 | #include <asm/system.h> |
| 42 | 42 | ||
diff --git a/drivers/input/touchscreen/corgi_ts.c b/drivers/input/touchscreen/corgi_ts.c index 3fb51b54fe61..94a1919d439d 100644 --- a/drivers/input/touchscreen/corgi_ts.c +++ b/drivers/input/touchscreen/corgi_ts.c | |||
| @@ -21,7 +21,6 @@ | |||
| 21 | 21 | ||
| 22 | #include <mach/sharpsl.h> | 22 | #include <mach/sharpsl.h> |
| 23 | #include <mach/hardware.h> | 23 | #include <mach/hardware.h> |
| 24 | #include <mach/pxa-regs.h> | ||
| 25 | #include <mach/pxa2xx-gpio.h> | 24 | #include <mach/pxa2xx-gpio.h> |
| 26 | 25 | ||
| 27 | 26 | ||
diff --git a/drivers/isdn/gigaset/bas-gigaset.c b/drivers/isdn/gigaset/bas-gigaset.c index 18dd8aacbe8d..831ddce1467b 100644 --- a/drivers/isdn/gigaset/bas-gigaset.c +++ b/drivers/isdn/gigaset/bas-gigaset.c | |||
| @@ -46,6 +46,9 @@ MODULE_PARM_DESC(cidmode, "Call-ID mode"); | |||
| 46 | /* length limit according to Siemens 3070usb-protokoll.doc ch. 2.1 */ | 46 | /* length limit according to Siemens 3070usb-protokoll.doc ch. 2.1 */ |
| 47 | #define IF_WRITEBUF 264 | 47 | #define IF_WRITEBUF 264 |
| 48 | 48 | ||
| 49 | /* interrupt pipe message size according to ibid. ch. 2.2 */ | ||
| 50 | #define IP_MSGSIZE 3 | ||
| 51 | |||
| 49 | /* Values for the Gigaset 307x */ | 52 | /* Values for the Gigaset 307x */ |
| 50 | #define USB_GIGA_VENDOR_ID 0x0681 | 53 | #define USB_GIGA_VENDOR_ID 0x0681 |
| 51 | #define USB_3070_PRODUCT_ID 0x0001 | 54 | #define USB_3070_PRODUCT_ID 0x0001 |
| @@ -110,7 +113,7 @@ struct bas_cardstate { | |||
| 110 | unsigned char *rcvbuf; /* AT reply receive buffer */ | 113 | unsigned char *rcvbuf; /* AT reply receive buffer */ |
| 111 | 114 | ||
| 112 | struct urb *urb_int_in; /* URB for interrupt pipe */ | 115 | struct urb *urb_int_in; /* URB for interrupt pipe */ |
| 113 | unsigned char int_in_buf[3]; | 116 | unsigned char *int_in_buf; |
| 114 | 117 | ||
| 115 | spinlock_t lock; /* locks all following */ | 118 | spinlock_t lock; /* locks all following */ |
| 116 | int basstate; /* bitmap (BS_*) */ | 119 | int basstate; /* bitmap (BS_*) */ |
| @@ -657,7 +660,7 @@ static void read_int_callback(struct urb *urb) | |||
| 657 | } | 660 | } |
| 658 | 661 | ||
| 659 | /* drop incomplete packets even if the missing bytes wouldn't matter */ | 662 | /* drop incomplete packets even if the missing bytes wouldn't matter */ |
| 660 | if (unlikely(urb->actual_length < 3)) { | 663 | if (unlikely(urb->actual_length < IP_MSGSIZE)) { |
| 661 | dev_warn(cs->dev, "incomplete interrupt packet (%d bytes)\n", | 664 | dev_warn(cs->dev, "incomplete interrupt packet (%d bytes)\n", |
| 662 | urb->actual_length); | 665 | urb->actual_length); |
| 663 | goto resubmit; | 666 | goto resubmit; |
| @@ -2127,6 +2130,7 @@ static void gigaset_reinitbcshw(struct bc_state *bcs) | |||
| 2127 | static void gigaset_freecshw(struct cardstate *cs) | 2130 | static void gigaset_freecshw(struct cardstate *cs) |
| 2128 | { | 2131 | { |
| 2129 | /* timers, URBs and rcvbuf are disposed of in disconnect */ | 2132 | /* timers, URBs and rcvbuf are disposed of in disconnect */ |
| 2133 | kfree(cs->hw.bas->int_in_buf); | ||
| 2130 | kfree(cs->hw.bas); | 2134 | kfree(cs->hw.bas); |
| 2131 | cs->hw.bas = NULL; | 2135 | cs->hw.bas = NULL; |
| 2132 | } | 2136 | } |
| @@ -2140,6 +2144,12 @@ static int gigaset_initcshw(struct cardstate *cs) | |||
| 2140 | pr_err("out of memory\n"); | 2144 | pr_err("out of memory\n"); |
| 2141 | return 0; | 2145 | return 0; |
| 2142 | } | 2146 | } |
| 2147 | ucs->int_in_buf = kmalloc(IP_MSGSIZE, GFP_KERNEL); | ||
| 2148 | if (!ucs->int_in_buf) { | ||
| 2149 | kfree(ucs); | ||
| 2150 | pr_err("out of memory\n"); | ||
| 2151 | return 0; | ||
| 2152 | } | ||
| 2143 | 2153 | ||
| 2144 | ucs->urb_cmd_in = NULL; | 2154 | ucs->urb_cmd_in = NULL; |
| 2145 | ucs->urb_cmd_out = NULL; | 2155 | ucs->urb_cmd_out = NULL; |
| @@ -2292,7 +2302,7 @@ static int gigaset_probe(struct usb_interface *interface, | |||
| 2292 | usb_fill_int_urb(ucs->urb_int_in, udev, | 2302 | usb_fill_int_urb(ucs->urb_int_in, udev, |
| 2293 | usb_rcvintpipe(udev, | 2303 | usb_rcvintpipe(udev, |
| 2294 | (endpoint->bEndpointAddress) & 0x0f), | 2304 | (endpoint->bEndpointAddress) & 0x0f), |
| 2295 | ucs->int_in_buf, 3, read_int_callback, cs, | 2305 | ucs->int_in_buf, IP_MSGSIZE, read_int_callback, cs, |
| 2296 | endpoint->bInterval); | 2306 | endpoint->bInterval); |
| 2297 | if ((rc = usb_submit_urb(ucs->urb_int_in, GFP_KERNEL)) != 0) { | 2307 | if ((rc = usb_submit_urb(ucs->urb_int_in, GFP_KERNEL)) != 0) { |
| 2298 | dev_err(cs->dev, "could not submit interrupt URB: %s\n", | 2308 | dev_err(cs->dev, "could not submit interrupt URB: %s\n", |
diff --git a/drivers/lguest/lguest_device.c b/drivers/lguest/lguest_device.c index b4d44e571d76..8132533d71f9 100644 --- a/drivers/lguest/lguest_device.c +++ b/drivers/lguest/lguest_device.c | |||
| @@ -212,6 +212,9 @@ static void lg_notify(struct virtqueue *vq) | |||
| 212 | hcall(LHCALL_NOTIFY, lvq->config.pfn << PAGE_SHIFT, 0, 0); | 212 | hcall(LHCALL_NOTIFY, lvq->config.pfn << PAGE_SHIFT, 0, 0); |
| 213 | } | 213 | } |
| 214 | 214 | ||
| 215 | /* An extern declaration inside a C file is bad form. Don't do it. */ | ||
| 216 | extern void lguest_setup_irq(unsigned int irq); | ||
| 217 | |||
| 215 | /* This routine finds the first virtqueue described in the configuration of | 218 | /* This routine finds the first virtqueue described in the configuration of |
| 216 | * this device and sets it up. | 219 | * this device and sets it up. |
| 217 | * | 220 | * |
| @@ -266,6 +269,9 @@ static struct virtqueue *lg_find_vq(struct virtio_device *vdev, | |||
| 266 | goto unmap; | 269 | goto unmap; |
| 267 | } | 270 | } |
| 268 | 271 | ||
| 272 | /* Make sure the interrupt is allocated. */ | ||
| 273 | lguest_setup_irq(lvq->config.irq); | ||
| 274 | |||
| 269 | /* Tell the interrupt for this virtqueue to go to the virtio_ring | 275 | /* Tell the interrupt for this virtqueue to go to the virtio_ring |
| 270 | * interrupt handler. */ | 276 | * interrupt handler. */ |
| 271 | /* FIXME: We used to have a flag for the Host to tell us we could use | 277 | /* FIXME: We used to have a flag for the Host to tell us we could use |
diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c index 35bda49796fb..bfefd079a955 100644 --- a/drivers/md/dm-crypt.c +++ b/drivers/md/dm-crypt.c | |||
| @@ -60,6 +60,7 @@ struct dm_crypt_io { | |||
| 60 | }; | 60 | }; |
| 61 | 61 | ||
| 62 | struct dm_crypt_request { | 62 | struct dm_crypt_request { |
| 63 | struct convert_context *ctx; | ||
| 63 | struct scatterlist sg_in; | 64 | struct scatterlist sg_in; |
| 64 | struct scatterlist sg_out; | 65 | struct scatterlist sg_out; |
| 65 | }; | 66 | }; |
| @@ -335,6 +336,18 @@ static void crypt_convert_init(struct crypt_config *cc, | |||
| 335 | init_completion(&ctx->restart); | 336 | init_completion(&ctx->restart); |
| 336 | } | 337 | } |
| 337 | 338 | ||
| 339 | static struct dm_crypt_request *dmreq_of_req(struct crypt_config *cc, | ||
| 340 | struct ablkcipher_request *req) | ||
| 341 | { | ||
| 342 | return (struct dm_crypt_request *)((char *)req + cc->dmreq_start); | ||
| 343 | } | ||
| 344 | |||
| 345 | static struct ablkcipher_request *req_of_dmreq(struct crypt_config *cc, | ||
| 346 | struct dm_crypt_request *dmreq) | ||
| 347 | { | ||
| 348 | return (struct ablkcipher_request *)((char *)dmreq - cc->dmreq_start); | ||
| 349 | } | ||
| 350 | |||
| 338 | static int crypt_convert_block(struct crypt_config *cc, | 351 | static int crypt_convert_block(struct crypt_config *cc, |
| 339 | struct convert_context *ctx, | 352 | struct convert_context *ctx, |
| 340 | struct ablkcipher_request *req) | 353 | struct ablkcipher_request *req) |
| @@ -345,10 +358,11 @@ static int crypt_convert_block(struct crypt_config *cc, | |||
| 345 | u8 *iv; | 358 | u8 *iv; |
| 346 | int r = 0; | 359 | int r = 0; |
| 347 | 360 | ||
| 348 | dmreq = (struct dm_crypt_request *)((char *)req + cc->dmreq_start); | 361 | dmreq = dmreq_of_req(cc, req); |
| 349 | iv = (u8 *)ALIGN((unsigned long)(dmreq + 1), | 362 | iv = (u8 *)ALIGN((unsigned long)(dmreq + 1), |
| 350 | crypto_ablkcipher_alignmask(cc->tfm) + 1); | 363 | crypto_ablkcipher_alignmask(cc->tfm) + 1); |
| 351 | 364 | ||
| 365 | dmreq->ctx = ctx; | ||
| 352 | sg_init_table(&dmreq->sg_in, 1); | 366 | sg_init_table(&dmreq->sg_in, 1); |
| 353 | sg_set_page(&dmreq->sg_in, bv_in->bv_page, 1 << SECTOR_SHIFT, | 367 | sg_set_page(&dmreq->sg_in, bv_in->bv_page, 1 << SECTOR_SHIFT, |
| 354 | bv_in->bv_offset + ctx->offset_in); | 368 | bv_in->bv_offset + ctx->offset_in); |
| @@ -395,8 +409,9 @@ static void crypt_alloc_req(struct crypt_config *cc, | |||
| 395 | cc->req = mempool_alloc(cc->req_pool, GFP_NOIO); | 409 | cc->req = mempool_alloc(cc->req_pool, GFP_NOIO); |
| 396 | ablkcipher_request_set_tfm(cc->req, cc->tfm); | 410 | ablkcipher_request_set_tfm(cc->req, cc->tfm); |
| 397 | ablkcipher_request_set_callback(cc->req, CRYPTO_TFM_REQ_MAY_BACKLOG | | 411 | ablkcipher_request_set_callback(cc->req, CRYPTO_TFM_REQ_MAY_BACKLOG | |
| 398 | CRYPTO_TFM_REQ_MAY_SLEEP, | 412 | CRYPTO_TFM_REQ_MAY_SLEEP, |
| 399 | kcryptd_async_done, ctx); | 413 | kcryptd_async_done, |
| 414 | dmreq_of_req(cc, cc->req)); | ||
| 400 | } | 415 | } |
| 401 | 416 | ||
| 402 | /* | 417 | /* |
| @@ -553,19 +568,22 @@ static void crypt_inc_pending(struct dm_crypt_io *io) | |||
| 553 | static void crypt_dec_pending(struct dm_crypt_io *io) | 568 | static void crypt_dec_pending(struct dm_crypt_io *io) |
| 554 | { | 569 | { |
| 555 | struct crypt_config *cc = io->target->private; | 570 | struct crypt_config *cc = io->target->private; |
| 571 | struct bio *base_bio = io->base_bio; | ||
| 572 | struct dm_crypt_io *base_io = io->base_io; | ||
| 573 | int error = io->error; | ||
| 556 | 574 | ||
| 557 | if (!atomic_dec_and_test(&io->pending)) | 575 | if (!atomic_dec_and_test(&io->pending)) |
| 558 | return; | 576 | return; |
| 559 | 577 | ||
| 560 | if (likely(!io->base_io)) | 578 | mempool_free(io, cc->io_pool); |
| 561 | bio_endio(io->base_bio, io->error); | 579 | |
| 580 | if (likely(!base_io)) | ||
| 581 | bio_endio(base_bio, error); | ||
| 562 | else { | 582 | else { |
| 563 | if (io->error && !io->base_io->error) | 583 | if (error && !base_io->error) |
| 564 | io->base_io->error = io->error; | 584 | base_io->error = error; |
| 565 | crypt_dec_pending(io->base_io); | 585 | crypt_dec_pending(base_io); |
| 566 | } | 586 | } |
| 567 | |||
| 568 | mempool_free(io, cc->io_pool); | ||
| 569 | } | 587 | } |
| 570 | 588 | ||
| 571 | /* | 589 | /* |
| @@ -821,7 +839,8 @@ static void kcryptd_crypt_read_convert(struct dm_crypt_io *io) | |||
| 821 | static void kcryptd_async_done(struct crypto_async_request *async_req, | 839 | static void kcryptd_async_done(struct crypto_async_request *async_req, |
| 822 | int error) | 840 | int error) |
| 823 | { | 841 | { |
| 824 | struct convert_context *ctx = async_req->data; | 842 | struct dm_crypt_request *dmreq = async_req->data; |
| 843 | struct convert_context *ctx = dmreq->ctx; | ||
| 825 | struct dm_crypt_io *io = container_of(ctx, struct dm_crypt_io, ctx); | 844 | struct dm_crypt_io *io = container_of(ctx, struct dm_crypt_io, ctx); |
| 826 | struct crypt_config *cc = io->target->private; | 845 | struct crypt_config *cc = io->target->private; |
| 827 | 846 | ||
| @@ -830,7 +849,7 @@ static void kcryptd_async_done(struct crypto_async_request *async_req, | |||
| 830 | return; | 849 | return; |
| 831 | } | 850 | } |
| 832 | 851 | ||
| 833 | mempool_free(ablkcipher_request_cast(async_req), cc->req_pool); | 852 | mempool_free(req_of_dmreq(cc, dmreq), cc->req_pool); |
| 834 | 853 | ||
| 835 | if (!atomic_dec_and_test(&ctx->pending)) | 854 | if (!atomic_dec_and_test(&ctx->pending)) |
| 836 | return; | 855 | return; |
diff --git a/drivers/md/dm-io.c b/drivers/md/dm-io.c index f14813be4eff..36e2b5e46a6b 100644 --- a/drivers/md/dm-io.c +++ b/drivers/md/dm-io.c | |||
| @@ -292,6 +292,8 @@ static void do_region(int rw, unsigned region, struct dm_io_region *where, | |||
| 292 | (PAGE_SIZE >> SECTOR_SHIFT)); | 292 | (PAGE_SIZE >> SECTOR_SHIFT)); |
| 293 | num_bvecs = 1 + min_t(int, bio_get_nr_vecs(where->bdev), | 293 | num_bvecs = 1 + min_t(int, bio_get_nr_vecs(where->bdev), |
| 294 | num_bvecs); | 294 | num_bvecs); |
| 295 | if (unlikely(num_bvecs > BIO_MAX_PAGES)) | ||
| 296 | num_bvecs = BIO_MAX_PAGES; | ||
| 295 | bio = bio_alloc_bioset(GFP_NOIO, num_bvecs, io->client->bios); | 297 | bio = bio_alloc_bioset(GFP_NOIO, num_bvecs, io->client->bios); |
| 296 | bio->bi_sector = where->sector + (where->count - remaining); | 298 | bio->bi_sector = where->sector + (where->count - remaining); |
| 297 | bio->bi_bdev = where->bdev; | 299 | bio->bi_bdev = where->bdev; |
diff --git a/drivers/md/dm-ioctl.c b/drivers/md/dm-ioctl.c index 54d0588fc1f6..f01096549a93 100644 --- a/drivers/md/dm-ioctl.c +++ b/drivers/md/dm-ioctl.c | |||
| @@ -704,7 +704,8 @@ static int dev_rename(struct dm_ioctl *param, size_t param_size) | |||
| 704 | char *new_name = (char *) param + param->data_start; | 704 | char *new_name = (char *) param + param->data_start; |
| 705 | 705 | ||
| 706 | if (new_name < param->data || | 706 | if (new_name < param->data || |
| 707 | invalid_str(new_name, (void *) param + param_size)) { | 707 | invalid_str(new_name, (void *) param + param_size) || |
| 708 | strlen(new_name) > DM_NAME_LEN - 1) { | ||
| 708 | DMWARN("Invalid new logical volume name supplied."); | 709 | DMWARN("Invalid new logical volume name supplied."); |
| 709 | return -EINVAL; | 710 | return -EINVAL; |
| 710 | } | 711 | } |
| @@ -1063,7 +1064,7 @@ static int table_load(struct dm_ioctl *param, size_t param_size) | |||
| 1063 | 1064 | ||
| 1064 | r = populate_table(t, param, param_size); | 1065 | r = populate_table(t, param, param_size); |
| 1065 | if (r) { | 1066 | if (r) { |
| 1066 | dm_table_put(t); | 1067 | dm_table_destroy(t); |
| 1067 | goto out; | 1068 | goto out; |
| 1068 | } | 1069 | } |
| 1069 | 1070 | ||
| @@ -1071,7 +1072,7 @@ static int table_load(struct dm_ioctl *param, size_t param_size) | |||
| 1071 | hc = dm_get_mdptr(md); | 1072 | hc = dm_get_mdptr(md); |
| 1072 | if (!hc || hc->md != md) { | 1073 | if (!hc || hc->md != md) { |
| 1073 | DMWARN("device has been removed from the dev hash table."); | 1074 | DMWARN("device has been removed from the dev hash table."); |
| 1074 | dm_table_put(t); | 1075 | dm_table_destroy(t); |
| 1075 | up_write(&_hash_lock); | 1076 | up_write(&_hash_lock); |
| 1076 | r = -ENXIO; | 1077 | r = -ENXIO; |
| 1077 | goto out; | 1078 | goto out; |
diff --git a/drivers/md/dm.c b/drivers/md/dm.c index 51ba1db4b3e7..8d40f27cce89 100644 --- a/drivers/md/dm.c +++ b/drivers/md/dm.c | |||
| @@ -525,9 +525,12 @@ static int __noflush_suspending(struct mapped_device *md) | |||
| 525 | static void dec_pending(struct dm_io *io, int error) | 525 | static void dec_pending(struct dm_io *io, int error) |
| 526 | { | 526 | { |
| 527 | unsigned long flags; | 527 | unsigned long flags; |
| 528 | int io_error; | ||
| 529 | struct bio *bio; | ||
| 530 | struct mapped_device *md = io->md; | ||
| 528 | 531 | ||
| 529 | /* Push-back supersedes any I/O errors */ | 532 | /* Push-back supersedes any I/O errors */ |
| 530 | if (error && !(io->error > 0 && __noflush_suspending(io->md))) | 533 | if (error && !(io->error > 0 && __noflush_suspending(md))) |
| 531 | io->error = error; | 534 | io->error = error; |
| 532 | 535 | ||
| 533 | if (atomic_dec_and_test(&io->io_count)) { | 536 | if (atomic_dec_and_test(&io->io_count)) { |
| @@ -537,24 +540,27 @@ static void dec_pending(struct dm_io *io, int error) | |||
| 537 | * This must be handled before the sleeper on | 540 | * This must be handled before the sleeper on |
| 538 | * suspend queue merges the pushback list. | 541 | * suspend queue merges the pushback list. |
| 539 | */ | 542 | */ |
| 540 | spin_lock_irqsave(&io->md->pushback_lock, flags); | 543 | spin_lock_irqsave(&md->pushback_lock, flags); |
| 541 | if (__noflush_suspending(io->md)) | 544 | if (__noflush_suspending(md)) |
| 542 | bio_list_add(&io->md->pushback, io->bio); | 545 | bio_list_add(&md->pushback, io->bio); |
| 543 | else | 546 | else |
| 544 | /* noflush suspend was interrupted. */ | 547 | /* noflush suspend was interrupted. */ |
| 545 | io->error = -EIO; | 548 | io->error = -EIO; |
| 546 | spin_unlock_irqrestore(&io->md->pushback_lock, flags); | 549 | spin_unlock_irqrestore(&md->pushback_lock, flags); |
| 547 | } | 550 | } |
| 548 | 551 | ||
| 549 | end_io_acct(io); | 552 | end_io_acct(io); |
| 550 | 553 | ||
| 551 | if (io->error != DM_ENDIO_REQUEUE) { | 554 | io_error = io->error; |
| 552 | trace_block_bio_complete(io->md->queue, io->bio); | 555 | bio = io->bio; |
| 553 | 556 | ||
| 554 | bio_endio(io->bio, io->error); | 557 | free_io(md, io); |
| 555 | } | 558 | |
| 559 | if (io_error != DM_ENDIO_REQUEUE) { | ||
| 560 | trace_block_bio_complete(md->queue, bio); | ||
| 556 | 561 | ||
| 557 | free_io(io->md, io); | 562 | bio_endio(bio, io_error); |
| 563 | } | ||
| 558 | } | 564 | } |
| 559 | } | 565 | } |
| 560 | 566 | ||
| @@ -562,6 +568,7 @@ static void clone_endio(struct bio *bio, int error) | |||
| 562 | { | 568 | { |
| 563 | int r = 0; | 569 | int r = 0; |
| 564 | struct dm_target_io *tio = bio->bi_private; | 570 | struct dm_target_io *tio = bio->bi_private; |
| 571 | struct dm_io *io = tio->io; | ||
| 565 | struct mapped_device *md = tio->io->md; | 572 | struct mapped_device *md = tio->io->md; |
| 566 | dm_endio_fn endio = tio->ti->type->end_io; | 573 | dm_endio_fn endio = tio->ti->type->end_io; |
| 567 | 574 | ||
| @@ -585,15 +592,14 @@ static void clone_endio(struct bio *bio, int error) | |||
| 585 | } | 592 | } |
| 586 | } | 593 | } |
| 587 | 594 | ||
| 588 | dec_pending(tio->io, error); | ||
| 589 | |||
| 590 | /* | 595 | /* |
| 591 | * Store md for cleanup instead of tio which is about to get freed. | 596 | * Store md for cleanup instead of tio which is about to get freed. |
| 592 | */ | 597 | */ |
| 593 | bio->bi_private = md->bs; | 598 | bio->bi_private = md->bs; |
| 594 | 599 | ||
| 595 | bio_put(bio); | ||
| 596 | free_tio(md, tio); | 600 | free_tio(md, tio); |
| 601 | bio_put(bio); | ||
| 602 | dec_pending(io, error); | ||
| 597 | } | 603 | } |
| 598 | 604 | ||
| 599 | static sector_t max_io_len(struct mapped_device *md, | 605 | static sector_t max_io_len(struct mapped_device *md, |
diff --git a/drivers/md/md.c b/drivers/md/md.c index 03b4cd0a6344..a307f87eb90e 100644 --- a/drivers/md/md.c +++ b/drivers/md/md.c | |||
| @@ -214,12 +214,7 @@ static inline mddev_t *mddev_get(mddev_t *mddev) | |||
| 214 | return mddev; | 214 | return mddev; |
| 215 | } | 215 | } |
| 216 | 216 | ||
| 217 | static void mddev_delayed_delete(struct work_struct *ws) | 217 | static void mddev_delayed_delete(struct work_struct *ws); |
| 218 | { | ||
| 219 | mddev_t *mddev = container_of(ws, mddev_t, del_work); | ||
| 220 | kobject_del(&mddev->kobj); | ||
| 221 | kobject_put(&mddev->kobj); | ||
| 222 | } | ||
| 223 | 218 | ||
| 224 | static void mddev_put(mddev_t *mddev) | 219 | static void mddev_put(mddev_t *mddev) |
| 225 | { | 220 | { |
| @@ -3542,6 +3537,21 @@ static struct kobj_type md_ktype = { | |||
| 3542 | 3537 | ||
| 3543 | int mdp_major = 0; | 3538 | int mdp_major = 0; |
| 3544 | 3539 | ||
| 3540 | static void mddev_delayed_delete(struct work_struct *ws) | ||
| 3541 | { | ||
| 3542 | mddev_t *mddev = container_of(ws, mddev_t, del_work); | ||
| 3543 | |||
| 3544 | if (mddev->private == &md_redundancy_group) { | ||
| 3545 | sysfs_remove_group(&mddev->kobj, &md_redundancy_group); | ||
| 3546 | if (mddev->sysfs_action) | ||
| 3547 | sysfs_put(mddev->sysfs_action); | ||
| 3548 | mddev->sysfs_action = NULL; | ||
| 3549 | mddev->private = NULL; | ||
| 3550 | } | ||
| 3551 | kobject_del(&mddev->kobj); | ||
| 3552 | kobject_put(&mddev->kobj); | ||
| 3553 | } | ||
| 3554 | |||
| 3545 | static int md_alloc(dev_t dev, char *name) | 3555 | static int md_alloc(dev_t dev, char *name) |
| 3546 | { | 3556 | { |
| 3547 | static DEFINE_MUTEX(disks_mutex); | 3557 | static DEFINE_MUTEX(disks_mutex); |
| @@ -4033,13 +4043,9 @@ static int do_md_stop(mddev_t * mddev, int mode, int is_open) | |||
| 4033 | mddev->queue->merge_bvec_fn = NULL; | 4043 | mddev->queue->merge_bvec_fn = NULL; |
| 4034 | mddev->queue->unplug_fn = NULL; | 4044 | mddev->queue->unplug_fn = NULL; |
| 4035 | mddev->queue->backing_dev_info.congested_fn = NULL; | 4045 | mddev->queue->backing_dev_info.congested_fn = NULL; |
| 4036 | if (mddev->pers->sync_request) { | ||
| 4037 | sysfs_remove_group(&mddev->kobj, &md_redundancy_group); | ||
| 4038 | if (mddev->sysfs_action) | ||
| 4039 | sysfs_put(mddev->sysfs_action); | ||
| 4040 | mddev->sysfs_action = NULL; | ||
| 4041 | } | ||
| 4042 | module_put(mddev->pers->owner); | 4046 | module_put(mddev->pers->owner); |
| 4047 | if (mddev->pers->sync_request) | ||
| 4048 | mddev->private = &md_redundancy_group; | ||
| 4043 | mddev->pers = NULL; | 4049 | mddev->pers = NULL; |
| 4044 | /* tell userspace to handle 'inactive' */ | 4050 | /* tell userspace to handle 'inactive' */ |
| 4045 | sysfs_notify_dirent(mddev->sysfs_state); | 4051 | sysfs_notify_dirent(mddev->sysfs_state); |
diff --git a/drivers/media/dvb/bt8xx/dst.c b/drivers/media/dvb/bt8xx/dst.c index 29e8f1546ab6..fec1d77fa855 100644 --- a/drivers/media/dvb/bt8xx/dst.c +++ b/drivers/media/dvb/bt8xx/dst.c | |||
| @@ -1683,7 +1683,7 @@ static int dst_tune_frontend(struct dvb_frontend* fe, | |||
| 1683 | 1683 | ||
| 1684 | static int dst_get_tuning_algo(struct dvb_frontend *fe) | 1684 | static int dst_get_tuning_algo(struct dvb_frontend *fe) |
| 1685 | { | 1685 | { |
| 1686 | return dst_algo; | 1686 | return dst_algo ? DVBFE_ALGO_HW : DVBFE_ALGO_SW; |
| 1687 | } | 1687 | } |
| 1688 | 1688 | ||
| 1689 | static int dst_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) | 1689 | static int dst_get_frontend(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) |
diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c index 843407785083..8dcb3fbf7acd 100644 --- a/drivers/media/dvb/dvb-core/dvb_frontend.c +++ b/drivers/media/dvb/dvb-core/dvb_frontend.c | |||
| @@ -1290,9 +1290,6 @@ static int dtv_property_process_set(struct dvb_frontend *fe, | |||
| 1290 | dprintk("%s() Finalised property cache\n", __func__); | 1290 | dprintk("%s() Finalised property cache\n", __func__); |
| 1291 | dtv_property_cache_submit(fe); | 1291 | dtv_property_cache_submit(fe); |
| 1292 | 1292 | ||
| 1293 | /* Request the search algorithm to search */ | ||
| 1294 | fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN; | ||
| 1295 | |||
| 1296 | r |= dvb_frontend_ioctl_legacy(inode, file, FE_SET_FRONTEND, | 1293 | r |= dvb_frontend_ioctl_legacy(inode, file, FE_SET_FRONTEND, |
| 1297 | &fepriv->parameters); | 1294 | &fepriv->parameters); |
| 1298 | break; | 1295 | break; |
| @@ -1717,6 +1714,10 @@ static int dvb_frontend_ioctl_legacy(struct inode *inode, struct file *file, | |||
| 1717 | fepriv->min_delay = (dvb_override_tune_delay * HZ) / 1000; | 1714 | fepriv->min_delay = (dvb_override_tune_delay * HZ) / 1000; |
| 1718 | 1715 | ||
| 1719 | fepriv->state = FESTATE_RETUNE; | 1716 | fepriv->state = FESTATE_RETUNE; |
| 1717 | |||
| 1718 | /* Request the search algorithm to search */ | ||
| 1719 | fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN; | ||
| 1720 | |||
| 1720 | dvb_frontend_wakeup(fe); | 1721 | dvb_frontend_wakeup(fe); |
| 1721 | dvb_frontend_add_event(fe, 0); | 1722 | dvb_frontend_add_event(fe, 0); |
| 1722 | fepriv->status = 0; | 1723 | fepriv->status = 0; |
diff --git a/drivers/media/dvb/frontends/stb0899_algo.c b/drivers/media/dvb/frontends/stb0899_algo.c index a67d1775a43c..2da55ec20392 100644 --- a/drivers/media/dvb/frontends/stb0899_algo.c +++ b/drivers/media/dvb/frontends/stb0899_algo.c | |||
| @@ -156,7 +156,7 @@ static void stb0899_first_subrange(struct stb0899_state *state) | |||
| 156 | } | 156 | } |
| 157 | 157 | ||
| 158 | if (range > 0) | 158 | if (range > 0) |
| 159 | internal->sub_range = MIN(internal->srch_range, range); | 159 | internal->sub_range = min(internal->srch_range, range); |
| 160 | else | 160 | else |
| 161 | internal->sub_range = 0; | 161 | internal->sub_range = 0; |
| 162 | 162 | ||
| @@ -185,7 +185,7 @@ static enum stb0899_status stb0899_check_tmg(struct stb0899_state *state) | |||
| 185 | timing = stb0899_read_reg(state, STB0899_RTF); | 185 | timing = stb0899_read_reg(state, STB0899_RTF); |
| 186 | 186 | ||
| 187 | if (lock >= 42) { | 187 | if (lock >= 42) { |
| 188 | if ((lock > 48) && (ABS(timing) >= 110)) { | 188 | if ((lock > 48) && (abs(timing) >= 110)) { |
| 189 | internal->status = ANALOGCARRIER; | 189 | internal->status = ANALOGCARRIER; |
| 190 | dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !"); | 190 | dprintk(state->verbose, FE_DEBUG, 1, "-->ANALOG Carrier !"); |
| 191 | } else { | 191 | } else { |
| @@ -222,7 +222,7 @@ static enum stb0899_status stb0899_search_tmg(struct stb0899_state *state) | |||
| 222 | index++; | 222 | index++; |
| 223 | derot_freq += index * internal->direction * derot_step; /* next derot zig zag position */ | 223 | derot_freq += index * internal->direction * derot_step; /* next derot zig zag position */ |
| 224 | 224 | ||
| 225 | if (ABS(derot_freq) > derot_limit) | 225 | if (abs(derot_freq) > derot_limit) |
| 226 | next_loop--; | 226 | next_loop--; |
| 227 | 227 | ||
| 228 | if (next_loop) { | 228 | if (next_loop) { |
| @@ -298,7 +298,7 @@ static enum stb0899_status stb0899_search_carrier(struct stb0899_state *state) | |||
| 298 | last_derot_freq = derot_freq; | 298 | last_derot_freq = derot_freq; |
| 299 | derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */ | 299 | derot_freq += index * internal->direction * internal->derot_step; /* next zig zag derotator position */ |
| 300 | 300 | ||
| 301 | if(ABS(derot_freq) > derot_limit) | 301 | if(abs(derot_freq) > derot_limit) |
| 302 | next_loop--; | 302 | next_loop--; |
| 303 | 303 | ||
| 304 | if (next_loop) { | 304 | if (next_loop) { |
| @@ -400,7 +400,7 @@ static enum stb0899_status stb0899_search_data(struct stb0899_state *state) | |||
| 400 | if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) { | 400 | if ((internal->status != CARRIEROK) || (stb0899_check_data(state) != DATAOK)) { |
| 401 | 401 | ||
| 402 | derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */ | 402 | derot_freq += index * internal->direction * derot_step; /* next zig zag derotator position */ |
| 403 | if (ABS(derot_freq) > derot_limit) | 403 | if (abs(derot_freq) > derot_limit) |
| 404 | next_loop--; | 404 | next_loop--; |
| 405 | 405 | ||
| 406 | if (next_loop) { | 406 | if (next_loop) { |
| @@ -467,7 +467,7 @@ static void next_sub_range(struct stb0899_state *state) | |||
| 467 | 467 | ||
| 468 | if (internal->sub_dir > 0) { | 468 | if (internal->sub_dir > 0) { |
| 469 | old_sub_range = internal->sub_range; | 469 | old_sub_range = internal->sub_range; |
| 470 | internal->sub_range = MIN((internal->srch_range / 2) - | 470 | internal->sub_range = min((internal->srch_range / 2) - |
| 471 | (internal->tuner_offst + internal->sub_range / 2), | 471 | (internal->tuner_offst + internal->sub_range / 2), |
| 472 | internal->sub_range); | 472 | internal->sub_range); |
| 473 | 473 | ||
| @@ -771,7 +771,7 @@ static long Log2Int(int number) | |||
| 771 | int i; | 771 | int i; |
| 772 | 772 | ||
| 773 | i = 0; | 773 | i = 0; |
| 774 | while ((1 << i) <= ABS(number)) | 774 | while ((1 << i) <= abs(number)) |
| 775 | i++; | 775 | i++; |
| 776 | 776 | ||
| 777 | if (number == 0) | 777 | if (number == 0) |
diff --git a/drivers/media/dvb/frontends/stb0899_drv.c b/drivers/media/dvb/frontends/stb0899_drv.c index 10613acf18f5..a04c782fff8d 100644 --- a/drivers/media/dvb/frontends/stb0899_drv.c +++ b/drivers/media/dvb/frontends/stb0899_drv.c | |||
| @@ -794,7 +794,7 @@ static int stb0899_send_diseqc_burst(struct dvb_frontend *fe, fe_sec_mini_cmd_t | |||
| 794 | reg = stb0899_read_reg(state, STB0899_DISCNTRL1); | 794 | reg = stb0899_read_reg(state, STB0899_DISCNTRL1); |
| 795 | old_state = reg; | 795 | old_state = reg; |
| 796 | /* set to burst mode */ | 796 | /* set to burst mode */ |
| 797 | STB0899_SETFIELD_VAL(DISEQCMODE, reg, 0x02); | 797 | STB0899_SETFIELD_VAL(DISEQCMODE, reg, 0x03); |
| 798 | STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0x01); | 798 | STB0899_SETFIELD_VAL(DISPRECHARGE, reg, 0x01); |
| 799 | stb0899_write_reg(state, STB0899_DISCNTRL1, reg); | 799 | stb0899_write_reg(state, STB0899_DISCNTRL1, reg); |
| 800 | switch (burst) { | 800 | switch (burst) { |
diff --git a/drivers/media/dvb/frontends/stb0899_priv.h b/drivers/media/dvb/frontends/stb0899_priv.h index 24619e3689db..82395b912815 100644 --- a/drivers/media/dvb/frontends/stb0899_priv.h +++ b/drivers/media/dvb/frontends/stb0899_priv.h | |||
| @@ -59,10 +59,6 @@ | |||
| 59 | #define MAKEWORD32(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d)) | 59 | #define MAKEWORD32(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d)) |
| 60 | #define MAKEWORD16(a, b) (((a) << 8) | (b)) | 60 | #define MAKEWORD16(a, b) (((a) << 8) | (b)) |
| 61 | 61 | ||
| 62 | #define MIN(x, y) ((x) <= (y) ? (x) : (y)) | ||
| 63 | #define MAX(x, y) ((x) >= (y) ? (x) : (y)) | ||
| 64 | #define ABS(x) ((x) >= 0 ? (x) : -(x)) | ||
| 65 | |||
| 66 | #define LSB(x) ((x & 0xff)) | 62 | #define LSB(x) ((x & 0xff)) |
| 67 | #define MSB(y) ((y >> 8) & 0xff) | 63 | #define MSB(y) ((y >> 8) & 0xff) |
| 68 | 64 | ||
| @@ -168,10 +164,10 @@ struct stb0899_internal { | |||
| 168 | u32 freq; /* Demod internal Frequency */ | 164 | u32 freq; /* Demod internal Frequency */ |
| 169 | u32 srate; /* Demod internal Symbol rate */ | 165 | u32 srate; /* Demod internal Symbol rate */ |
| 170 | enum stb0899_fec fecrate; /* Demod internal FEC rate */ | 166 | enum stb0899_fec fecrate; /* Demod internal FEC rate */ |
| 171 | u32 srch_range; /* Demod internal Search Range */ | 167 | s32 srch_range; /* Demod internal Search Range */ |
| 172 | u32 sub_range; /* Demod current sub range (Hz) */ | 168 | s32 sub_range; /* Demod current sub range (Hz) */ |
| 173 | u32 tuner_step; /* Tuner step (Hz) */ | 169 | s32 tuner_step; /* Tuner step (Hz) */ |
| 174 | u32 tuner_offst; /* Relative offset to carrier (Hz) */ | 170 | s32 tuner_offst; /* Relative offset to carrier (Hz) */ |
| 175 | u32 tuner_bw; /* Current bandwidth of the tuner (Hz) */ | 171 | u32 tuner_bw; /* Current bandwidth of the tuner (Hz) */ |
| 176 | 172 | ||
| 177 | s32 mclk; /* Masterclock Divider factor (binary) */ | 173 | s32 mclk; /* Masterclock Divider factor (binary) */ |
diff --git a/drivers/media/dvb/frontends/stb6100.c b/drivers/media/dvb/frontends/stb6100.c index ff39275ab49c..1ed5a7db4c5e 100644 --- a/drivers/media/dvb/frontends/stb6100.c +++ b/drivers/media/dvb/frontends/stb6100.c | |||
| @@ -427,11 +427,11 @@ static int stb6100_init(struct dvb_frontend *fe) | |||
| 427 | status->refclock = 27000000; /* Hz */ | 427 | status->refclock = 27000000; /* Hz */ |
| 428 | status->iqsense = 1; | 428 | status->iqsense = 1; |
| 429 | status->bandwidth = 36000; /* kHz */ | 429 | status->bandwidth = 36000; /* kHz */ |
| 430 | state->bandwidth = status->bandwidth * 1000; /* MHz */ | 430 | state->bandwidth = status->bandwidth * 1000; /* Hz */ |
| 431 | state->reference = status->refclock / 1000; /* kHz */ | 431 | state->reference = status->refclock / 1000; /* kHz */ |
| 432 | 432 | ||
| 433 | /* Set default bandwidth. */ | 433 | /* Set default bandwidth. */ |
| 434 | return stb6100_set_bandwidth(fe, status->bandwidth); | 434 | return stb6100_set_bandwidth(fe, state->bandwidth); |
| 435 | } | 435 | } |
| 436 | 436 | ||
| 437 | static int stb6100_get_state(struct dvb_frontend *fe, | 437 | static int stb6100_get_state(struct dvb_frontend *fe, |
diff --git a/drivers/media/dvb/frontends/zl10353.c b/drivers/media/dvb/frontends/zl10353.c index 170720b02815..b150ed306696 100644 --- a/drivers/media/dvb/frontends/zl10353.c +++ b/drivers/media/dvb/frontends/zl10353.c | |||
| @@ -590,7 +590,7 @@ static int zl10353_i2c_gate_ctrl(struct dvb_frontend* fe, int enable) | |||
| 590 | struct zl10353_state *state = fe->demodulator_priv; | 590 | struct zl10353_state *state = fe->demodulator_priv; |
| 591 | u8 val = 0x0a; | 591 | u8 val = 0x0a; |
| 592 | 592 | ||
| 593 | if (state->config.no_tuner) { | 593 | if (state->config.disable_i2c_gate_ctrl) { |
| 594 | /* No tuner attached to the internal I2C bus */ | 594 | /* No tuner attached to the internal I2C bus */ |
| 595 | /* If set enable I2C bridge, the main I2C bus stopped hardly */ | 595 | /* If set enable I2C bridge, the main I2C bus stopped hardly */ |
| 596 | return 0; | 596 | return 0; |
diff --git a/drivers/media/dvb/frontends/zl10353.h b/drivers/media/dvb/frontends/zl10353.h index fdbb88ff75fe..2287bac46243 100644 --- a/drivers/media/dvb/frontends/zl10353.h +++ b/drivers/media/dvb/frontends/zl10353.h | |||
| @@ -38,6 +38,9 @@ struct zl10353_config | |||
| 38 | 38 | ||
| 39 | /* set if parallel ts output is required */ | 39 | /* set if parallel ts output is required */ |
| 40 | int parallel_ts; | 40 | int parallel_ts; |
| 41 | |||
| 42 | /* set if i2c_gate_ctrl disable is required */ | ||
| 43 | u8 disable_i2c_gate_ctrl:1; | ||
| 41 | }; | 44 | }; |
| 42 | 45 | ||
| 43 | #if defined(CONFIG_DVB_ZL10353) || (defined(CONFIG_DVB_ZL10353_MODULE) && defined(MODULE)) | 46 | #if defined(CONFIG_DVB_ZL10353) || (defined(CONFIG_DVB_ZL10353_MODULE) && defined(MODULE)) |
diff --git a/drivers/media/video/gspca/m5602/m5602_s5k4aa.c b/drivers/media/video/gspca/m5602/m5602_s5k4aa.c index e564a61a72d7..48892b5715d5 100644 --- a/drivers/media/video/gspca/m5602/m5602_s5k4aa.c +++ b/drivers/media/video/gspca/m5602/m5602_s5k4aa.c | |||
| @@ -102,7 +102,11 @@ int s5k4aa_probe(struct sd *sd) | |||
| 102 | } | 102 | } |
| 103 | 103 | ||
| 104 | /* Test some registers, but we don't know their exact meaning yet */ | 104 | /* Test some registers, but we don't know their exact meaning yet */ |
| 105 | if (m5602_read_sensor(sd, 0x00, prod_id, sizeof(prod_id))) | 105 | if (m5602_read_sensor(sd, 0x00, prod_id, 2)) |
| 106 | return -ENODEV; | ||
| 107 | if (m5602_read_sensor(sd, 0x02, prod_id+2, 2)) | ||
| 108 | return -ENODEV; | ||
| 109 | if (m5602_read_sensor(sd, 0x04, prod_id+4, 2)) | ||
| 106 | return -ENODEV; | 110 | return -ENODEV; |
| 107 | 111 | ||
| 108 | if (memcmp(prod_id, expected_prod_id, sizeof(prod_id))) | 112 | if (memcmp(prod_id, expected_prod_id, sizeof(prod_id))) |
diff --git a/drivers/media/video/omap24xxcam.c b/drivers/media/video/omap24xxcam.c index 73eb656acfe3..805faaea6449 100644 --- a/drivers/media/video/omap24xxcam.c +++ b/drivers/media/video/omap24xxcam.c | |||
| @@ -80,17 +80,17 @@ static int omap24xxcam_clock_get(struct omap24xxcam_device *cam) | |||
| 80 | { | 80 | { |
| 81 | int rval = 0; | 81 | int rval = 0; |
| 82 | 82 | ||
| 83 | cam->fck = clk_get(cam->dev, "cam_fck"); | 83 | cam->fck = clk_get(cam->dev, "fck"); |
| 84 | if (IS_ERR(cam->fck)) { | 84 | if (IS_ERR(cam->fck)) { |
| 85 | dev_err(cam->dev, "can't get cam_fck"); | 85 | dev_err(cam->dev, "can't get camera fck"); |
| 86 | rval = PTR_ERR(cam->fck); | 86 | rval = PTR_ERR(cam->fck); |
| 87 | omap24xxcam_clock_put(cam); | 87 | omap24xxcam_clock_put(cam); |
| 88 | return rval; | 88 | return rval; |
| 89 | } | 89 | } |
| 90 | 90 | ||
| 91 | cam->ick = clk_get(cam->dev, "cam_ick"); | 91 | cam->ick = clk_get(cam->dev, "ick"); |
| 92 | if (IS_ERR(cam->ick)) { | 92 | if (IS_ERR(cam->ick)) { |
| 93 | dev_err(cam->dev, "can't get cam_ick"); | 93 | dev_err(cam->dev, "can't get camera ick"); |
| 94 | rval = PTR_ERR(cam->ick); | 94 | rval = PTR_ERR(cam->ick); |
| 95 | omap24xxcam_clock_put(cam); | 95 | omap24xxcam_clock_put(cam); |
| 96 | } | 96 | } |
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c index 07c334f25aae..0c4ce58c53d5 100644 --- a/drivers/media/video/pxa_camera.c +++ b/drivers/media/video/pxa_camera.c | |||
| @@ -35,7 +35,6 @@ | |||
| 35 | #include <linux/videodev2.h> | 35 | #include <linux/videodev2.h> |
| 36 | 36 | ||
| 37 | #include <mach/dma.h> | 37 | #include <mach/dma.h> |
| 38 | #include <mach/pxa-regs.h> | ||
| 39 | #include <mach/camera.h> | 38 | #include <mach/camera.h> |
| 40 | 39 | ||
| 41 | #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) | 40 | #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) |
diff --git a/drivers/media/video/saa7134/saa7134-dvb.c b/drivers/media/video/saa7134/saa7134-dvb.c index 0776ecf56d27..b5370b3e1a3d 100644 --- a/drivers/media/video/saa7134/saa7134-dvb.c +++ b/drivers/media/video/saa7134/saa7134-dvb.c | |||
| @@ -860,6 +860,7 @@ static struct zl10353_config behold_h6_config = { | |||
| 860 | .demod_address = 0x1e>>1, | 860 | .demod_address = 0x1e>>1, |
| 861 | .no_tuner = 1, | 861 | .no_tuner = 1, |
| 862 | .parallel_ts = 1, | 862 | .parallel_ts = 1, |
| 863 | .disable_i2c_gate_ctrl = 1, | ||
| 863 | }; | 864 | }; |
| 864 | 865 | ||
| 865 | /* ================================================================== | 866 | /* ================================================================== |
diff --git a/drivers/media/video/tvaudio.c b/drivers/media/video/tvaudio.c index 5aeccb301cea..076ed5bf48b1 100644 --- a/drivers/media/video/tvaudio.c +++ b/drivers/media/video/tvaudio.c | |||
| @@ -54,7 +54,7 @@ MODULE_LICENSE("GPL"); | |||
| 54 | /* ---------------------------------------------------------------------- */ | 54 | /* ---------------------------------------------------------------------- */ |
| 55 | /* our structs */ | 55 | /* our structs */ |
| 56 | 56 | ||
| 57 | #define MAXREGS 64 | 57 | #define MAXREGS 256 |
| 58 | 58 | ||
| 59 | struct CHIPSTATE; | 59 | struct CHIPSTATE; |
| 60 | typedef int (*getvalue)(int); | 60 | typedef int (*getvalue)(int); |
diff --git a/drivers/media/video/zoran/Kconfig b/drivers/media/video/zoran/Kconfig index 4ea5fa71de89..8666e19f31a7 100644 --- a/drivers/media/video/zoran/Kconfig +++ b/drivers/media/video/zoran/Kconfig | |||
| @@ -68,6 +68,7 @@ config VIDEO_ZORAN_AVS6EYES | |||
| 68 | tristate "AverMedia 6 Eyes support (EXPERIMENTAL)" | 68 | tristate "AverMedia 6 Eyes support (EXPERIMENTAL)" |
| 69 | depends on VIDEO_ZORAN_ZR36060 && EXPERIMENTAL && VIDEO_V4L1 | 69 | depends on VIDEO_ZORAN_ZR36060 && EXPERIMENTAL && VIDEO_V4L1 |
| 70 | select VIDEO_BT856 if VIDEO_HELPER_CHIPS_AUTO | 70 | select VIDEO_BT856 if VIDEO_HELPER_CHIPS_AUTO |
| 71 | select VIDEO_BT866 if VIDEO_HELPER_CHIPS_AUTO | ||
| 71 | select VIDEO_KS0127 if VIDEO_HELPER_CHIPS_AUTO | 72 | select VIDEO_KS0127 if VIDEO_HELPER_CHIPS_AUTO |
| 72 | help | 73 | help |
| 73 | Support for the AverMedia 6 Eyes video surveillance card. | 74 | Support for the AverMedia 6 Eyes video surveillance card. |
diff --git a/drivers/mfd/wm8350-core.c b/drivers/mfd/wm8350-core.c index 84d5ea1ec171..b457a05b28d9 100644 --- a/drivers/mfd/wm8350-core.c +++ b/drivers/mfd/wm8350-core.c | |||
| @@ -1383,6 +1383,11 @@ int wm8350_device_init(struct wm8350 *wm8350, int irq, | |||
| 1383 | wm8350->power.rev_g_coeff = 1; | 1383 | wm8350->power.rev_g_coeff = 1; |
| 1384 | break; | 1384 | break; |
| 1385 | 1385 | ||
| 1386 | case 1: | ||
| 1387 | dev_info(wm8350->dev, "WM8351 Rev B\n"); | ||
| 1388 | wm8350->power.rev_g_coeff = 1; | ||
| 1389 | break; | ||
| 1390 | |||
| 1386 | default: | 1391 | default: |
| 1387 | dev_err(wm8350->dev, "Unknown WM8351 CHIP_REV\n"); | 1392 | dev_err(wm8350->dev, "Unknown WM8351 CHIP_REV\n"); |
| 1388 | ret = -ENODEV; | 1393 | ret = -ENODEV; |
diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c index 9c50e6f1c236..34ce2703d29a 100644 --- a/drivers/mmc/core/mmc_ops.c +++ b/drivers/mmc/core/mmc_ops.c | |||
| @@ -248,12 +248,15 @@ mmc_send_cxd_data(struct mmc_card *card, struct mmc_host *host, | |||
| 248 | 248 | ||
| 249 | sg_init_one(&sg, data_buf, len); | 249 | sg_init_one(&sg, data_buf, len); |
| 250 | 250 | ||
| 251 | /* | 251 | if (opcode == MMC_SEND_CSD || opcode == MMC_SEND_CID) { |
| 252 | * The spec states that CSR and CID accesses have a timeout | 252 | /* |
| 253 | * of 64 clock cycles. | 253 | * The spec states that CSR and CID accesses have a timeout |
| 254 | */ | 254 | * of 64 clock cycles. |
| 255 | data.timeout_ns = 0; | 255 | */ |
| 256 | data.timeout_clks = 64; | 256 | data.timeout_ns = 0; |
| 257 | data.timeout_clks = 64; | ||
| 258 | } else | ||
| 259 | mmc_set_data_timeout(&data, card); | ||
| 257 | 260 | ||
| 258 | mmc_wait_for_req(host, &mrq); | 261 | mmc_wait_for_req(host, &mrq); |
| 259 | 262 | ||
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 2909bbc8ad00..a663429b3d55 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c | |||
| @@ -490,7 +490,7 @@ static void mmci_check_status(unsigned long data) | |||
| 490 | mod_timer(&host->timer, jiffies + HZ); | 490 | mod_timer(&host->timer, jiffies + HZ); |
| 491 | } | 491 | } |
| 492 | 492 | ||
| 493 | static int mmci_probe(struct amba_device *dev, void *id) | 493 | static int __devinit mmci_probe(struct amba_device *dev, void *id) |
| 494 | { | 494 | { |
| 495 | struct mmc_platform_data *plat = dev->dev.platform_data; | 495 | struct mmc_platform_data *plat = dev->dev.platform_data; |
| 496 | struct mmci_host *host; | 496 | struct mmci_host *host; |
| @@ -633,7 +633,7 @@ static int mmci_probe(struct amba_device *dev, void *id) | |||
| 633 | return ret; | 633 | return ret; |
| 634 | } | 634 | } |
| 635 | 635 | ||
| 636 | static int mmci_remove(struct amba_device *dev) | 636 | static int __devexit mmci_remove(struct amba_device *dev) |
| 637 | { | 637 | { |
| 638 | struct mmc_host *mmc = amba_get_drvdata(dev); | 638 | struct mmc_host *mmc = amba_get_drvdata(dev); |
| 639 | 639 | ||
| @@ -730,7 +730,7 @@ static struct amba_driver mmci_driver = { | |||
| 730 | .name = DRIVER_NAME, | 730 | .name = DRIVER_NAME, |
| 731 | }, | 731 | }, |
| 732 | .probe = mmci_probe, | 732 | .probe = mmci_probe, |
| 733 | .remove = mmci_remove, | 733 | .remove = __devexit_p(mmci_remove), |
| 734 | .suspend = mmci_suspend, | 734 | .suspend = mmci_suspend, |
| 735 | .resume = mmci_resume, | 735 | .resume = mmci_resume, |
| 736 | .id_table = mmci_ids, | 736 | .id_table = mmci_ids, |
diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c index dda0be4e25dc..b4a615c55f28 100644 --- a/drivers/mmc/host/mxcmmc.c +++ b/drivers/mmc/host/mxcmmc.c | |||
| @@ -42,7 +42,7 @@ | |||
| 42 | #define HAS_DMA | 42 | #define HAS_DMA |
| 43 | #endif | 43 | #endif |
| 44 | 44 | ||
| 45 | #define DRIVER_NAME "imx-mmc" | 45 | #define DRIVER_NAME "mxc-mmc" |
| 46 | 46 | ||
| 47 | #define MMC_REG_STR_STP_CLK 0x00 | 47 | #define MMC_REG_STR_STP_CLK 0x00 |
| 48 | #define MMC_REG_STATUS 0x04 | 48 | #define MMC_REG_STATUS 0x04 |
| @@ -707,7 +707,7 @@ static int mxcmci_probe(struct platform_device *pdev) | |||
| 707 | host->res = r; | 707 | host->res = r; |
| 708 | host->irq = irq; | 708 | host->irq = irq; |
| 709 | 709 | ||
| 710 | host->clk = clk_get(&pdev->dev, "sdhc_clk"); | 710 | host->clk = clk_get(&pdev->dev, NULL); |
| 711 | if (IS_ERR(host->clk)) { | 711 | if (IS_ERR(host->clk)) { |
| 712 | ret = PTR_ERR(host->clk); | 712 | ret = PTR_ERR(host->clk); |
| 713 | goto out_iounmap; | 713 | goto out_iounmap; |
diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c index 67d7b7fef084..5570849188cc 100644 --- a/drivers/mmc/host/omap.c +++ b/drivers/mmc/host/omap.c | |||
| @@ -1460,18 +1460,12 @@ static int __init mmc_omap_probe(struct platform_device *pdev) | |||
| 1460 | if (!host->virt_base) | 1460 | if (!host->virt_base) |
| 1461 | goto err_ioremap; | 1461 | goto err_ioremap; |
| 1462 | 1462 | ||
| 1463 | if (cpu_is_omap24xx()) { | 1463 | host->iclk = clk_get(&pdev->dev, "ick"); |
| 1464 | host->iclk = clk_get(&pdev->dev, "mmc_ick"); | 1464 | if (IS_ERR(host->iclk)) |
| 1465 | if (IS_ERR(host->iclk)) | 1465 | goto err_free_mmc_host; |
| 1466 | goto err_free_mmc_host; | 1466 | clk_enable(host->iclk); |
| 1467 | clk_enable(host->iclk); | ||
| 1468 | } | ||
| 1469 | |||
| 1470 | if (!cpu_is_omap24xx()) | ||
| 1471 | host->fclk = clk_get(&pdev->dev, "mmc_ck"); | ||
| 1472 | else | ||
| 1473 | host->fclk = clk_get(&pdev->dev, "mmc_fck"); | ||
| 1474 | 1467 | ||
| 1468 | host->fclk = clk_get(&pdev->dev, "fck"); | ||
| 1475 | if (IS_ERR(host->fclk)) { | 1469 | if (IS_ERR(host->fclk)) { |
| 1476 | ret = PTR_ERR(host->fclk); | 1470 | ret = PTR_ERR(host->fclk); |
| 1477 | goto err_free_iclk; | 1471 | goto err_free_iclk; |
| @@ -1536,10 +1530,10 @@ static int mmc_omap_remove(struct platform_device *pdev) | |||
| 1536 | if (host->pdata->cleanup) | 1530 | if (host->pdata->cleanup) |
| 1537 | host->pdata->cleanup(&pdev->dev); | 1531 | host->pdata->cleanup(&pdev->dev); |
| 1538 | 1532 | ||
| 1539 | if (host->iclk && !IS_ERR(host->iclk)) | 1533 | mmc_omap_fclk_enable(host, 0); |
| 1540 | clk_put(host->iclk); | 1534 | clk_put(host->fclk); |
| 1541 | if (host->fclk && !IS_ERR(host->fclk)) | 1535 | clk_disable(host->iclk); |
| 1542 | clk_put(host->fclk); | 1536 | clk_put(host->iclk); |
| 1543 | 1537 | ||
| 1544 | iounmap(host->virt_base); | 1538 | iounmap(host->virt_base); |
| 1545 | release_mem_region(pdev->resource[0].start, | 1539 | release_mem_region(pdev->resource[0].start, |
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index a631c81dce12..3916a5618e28 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c | |||
| @@ -956,13 +956,13 @@ static int __init omap_mmc_probe(struct platform_device *pdev) | |||
| 956 | 956 | ||
| 957 | sema_init(&host->sem, 1); | 957 | sema_init(&host->sem, 1); |
| 958 | 958 | ||
| 959 | host->iclk = clk_get(&pdev->dev, "mmchs_ick"); | 959 | host->iclk = clk_get(&pdev->dev, "ick"); |
| 960 | if (IS_ERR(host->iclk)) { | 960 | if (IS_ERR(host->iclk)) { |
| 961 | ret = PTR_ERR(host->iclk); | 961 | ret = PTR_ERR(host->iclk); |
| 962 | host->iclk = NULL; | 962 | host->iclk = NULL; |
| 963 | goto err1; | 963 | goto err1; |
| 964 | } | 964 | } |
| 965 | host->fclk = clk_get(&pdev->dev, "mmchs_fck"); | 965 | host->fclk = clk_get(&pdev->dev, "fck"); |
| 966 | if (IS_ERR(host->fclk)) { | 966 | if (IS_ERR(host->fclk)) { |
| 967 | ret = PTR_ERR(host->fclk); | 967 | ret = PTR_ERR(host->fclk); |
| 968 | host->fclk = NULL; | 968 | host->fclk = NULL; |
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c index 9702ad3774cf..430095725f9f 100644 --- a/drivers/mmc/host/pxamci.c +++ b/drivers/mmc/host/pxamci.c | |||
| @@ -30,9 +30,8 @@ | |||
| 30 | 30 | ||
| 31 | #include <asm/sizes.h> | 31 | #include <asm/sizes.h> |
| 32 | 32 | ||
| 33 | #include <mach/dma.h> | ||
| 34 | #include <mach/hardware.h> | 33 | #include <mach/hardware.h> |
| 35 | #include <mach/pxa-regs.h> | 34 | #include <mach/dma.h> |
| 36 | #include <mach/mmc.h> | 35 | #include <mach/mmc.h> |
| 37 | 36 | ||
| 38 | #include "pxamci.h" | 37 | #include "pxamci.h" |
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c index f4a67c65d301..2db166b7096f 100644 --- a/drivers/mmc/host/s3cmci.c +++ b/drivers/mmc/host/s3cmci.c | |||
| @@ -793,8 +793,7 @@ static void s3cmci_dma_setup(struct s3cmci_host *host, | |||
| 793 | host->mem->start + host->sdidata); | 793 | host->mem->start + host->sdidata); |
| 794 | 794 | ||
| 795 | if (!setup_ok) { | 795 | if (!setup_ok) { |
| 796 | s3c2410_dma_config(host->dma, 4, | 796 | s3c2410_dma_config(host->dma, 4, 0); |
| 797 | (S3C2410_DCON_HWTRIG | S3C2410_DCON_CH0_SDI)); | ||
| 798 | s3c2410_dma_set_buffdone_fn(host->dma, | 797 | s3c2410_dma_set_buffdone_fn(host->dma, |
| 799 | s3cmci_dma_done_callback); | 798 | s3cmci_dma_done_callback); |
| 800 | s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART); | 799 | s3c2410_dma_setflags(host->dma, S3C2410_DMAF_AUTOSTART); |
diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig index bc33200535fc..6fde0a2e3567 100644 --- a/drivers/mtd/devices/Kconfig +++ b/drivers/mtd/devices/Kconfig | |||
| @@ -120,13 +120,6 @@ config MTD_PHRAM | |||
| 120 | doesn't have access to, memory beyond the mem=xxx limit, nvram, | 120 | doesn't have access to, memory beyond the mem=xxx limit, nvram, |
| 121 | memory on the video card, etc... | 121 | memory on the video card, etc... |
| 122 | 122 | ||
| 123 | config MTD_PS3VRAM | ||
| 124 | tristate "PS3 video RAM" | ||
| 125 | depends on FB_PS3 | ||
| 126 | help | ||
| 127 | This driver allows you to use excess PS3 video RAM as volatile | ||
| 128 | storage or system swap. | ||
| 129 | |||
| 130 | config MTD_LART | 123 | config MTD_LART |
| 131 | tristate "28F160xx flash driver for LART" | 124 | tristate "28F160xx flash driver for LART" |
| 132 | depends on SA1100_LART | 125 | depends on SA1100_LART |
diff --git a/drivers/mtd/devices/Makefile b/drivers/mtd/devices/Makefile index e51521df4e40..0993d5cf3923 100644 --- a/drivers/mtd/devices/Makefile +++ b/drivers/mtd/devices/Makefile | |||
| @@ -16,4 +16,3 @@ obj-$(CONFIG_MTD_LART) += lart.o | |||
| 16 | obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o | 16 | obj-$(CONFIG_MTD_BLOCK2MTD) += block2mtd.o |
| 17 | obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o | 17 | obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataflash.o |
| 18 | obj-$(CONFIG_MTD_M25P80) += m25p80.o | 18 | obj-$(CONFIG_MTD_M25P80) += m25p80.o |
| 19 | obj-$(CONFIG_MTD_PS3VRAM) += ps3vram.o | ||
diff --git a/drivers/mtd/devices/mtd_dataflash.c b/drivers/mtd/devices/mtd_dataflash.c index d44f741ae229..6d9f810565c8 100644 --- a/drivers/mtd/devices/mtd_dataflash.c +++ b/drivers/mtd/devices/mtd_dataflash.c | |||
| @@ -821,7 +821,8 @@ static struct flash_info *__devinit jedec_probe(struct spi_device *spi) | |||
| 821 | if (!(info->flags & IS_POW2PS)) | 821 | if (!(info->flags & IS_POW2PS)) |
| 822 | return info; | 822 | return info; |
| 823 | } | 823 | } |
| 824 | } | 824 | } else |
| 825 | return info; | ||
| 825 | } | 826 | } |
| 826 | } | 827 | } |
| 827 | 828 | ||
diff --git a/drivers/mtd/devices/ps3vram.c b/drivers/mtd/devices/ps3vram.c deleted file mode 100644 index d21e9beb7ed2..000000000000 --- a/drivers/mtd/devices/ps3vram.c +++ /dev/null | |||
| @@ -1,768 +0,0 @@ | |||
| 1 | /** | ||
| 2 | * ps3vram - Use extra PS3 video ram as MTD block device. | ||
| 3 | * | ||
| 4 | * Copyright (c) 2007-2008 Jim Paris <jim@jtan.com> | ||
| 5 | * Added support RSX DMA Vivien Chappelier <vivien.chappelier@free.fr> | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <linux/io.h> | ||
| 9 | #include <linux/mm.h> | ||
| 10 | #include <linux/init.h> | ||
| 11 | #include <linux/kernel.h> | ||
| 12 | #include <linux/list.h> | ||
| 13 | #include <linux/module.h> | ||
| 14 | #include <linux/moduleparam.h> | ||
| 15 | #include <linux/slab.h> | ||
| 16 | #include <linux/version.h> | ||
| 17 | #include <linux/gfp.h> | ||
| 18 | #include <linux/delay.h> | ||
| 19 | #include <linux/mtd/mtd.h> | ||
| 20 | |||
| 21 | #include <asm/lv1call.h> | ||
| 22 | #include <asm/ps3.h> | ||
| 23 | |||
| 24 | #define DEVICE_NAME "ps3vram" | ||
| 25 | |||
| 26 | #define XDR_BUF_SIZE (2 * 1024 * 1024) /* XDR buffer (must be 1MiB aligned) */ | ||
| 27 | #define XDR_IOIF 0x0c000000 | ||
| 28 | |||
| 29 | #define FIFO_BASE XDR_IOIF | ||
| 30 | #define FIFO_SIZE (64 * 1024) | ||
| 31 | |||
| 32 | #define DMA_PAGE_SIZE (4 * 1024) | ||
| 33 | |||
| 34 | #define CACHE_PAGE_SIZE (256 * 1024) | ||
| 35 | #define CACHE_PAGE_COUNT ((XDR_BUF_SIZE - FIFO_SIZE) / CACHE_PAGE_SIZE) | ||
| 36 | |||
| 37 | #define CACHE_OFFSET CACHE_PAGE_SIZE | ||
| 38 | #define FIFO_OFFSET 0 | ||
| 39 | |||
| 40 | #define CTRL_PUT 0x10 | ||
| 41 | #define CTRL_GET 0x11 | ||
| 42 | #define CTRL_TOP 0x15 | ||
| 43 | |||
| 44 | #define UPLOAD_SUBCH 1 | ||
| 45 | #define DOWNLOAD_SUBCH 2 | ||
| 46 | |||
| 47 | #define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c | ||
| 48 | #define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104 | ||
| 49 | |||
| 50 | #define L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT 0x601 | ||
| 51 | |||
| 52 | struct mtd_info ps3vram_mtd; | ||
| 53 | |||
| 54 | #define CACHE_PAGE_PRESENT 1 | ||
| 55 | #define CACHE_PAGE_DIRTY 2 | ||
| 56 | |||
| 57 | struct ps3vram_tag { | ||
| 58 | unsigned int address; | ||
| 59 | unsigned int flags; | ||
| 60 | }; | ||
| 61 | |||
| 62 | struct ps3vram_cache { | ||
| 63 | unsigned int page_count; | ||
| 64 | unsigned int page_size; | ||
| 65 | struct ps3vram_tag *tags; | ||
| 66 | }; | ||
| 67 | |||
| 68 | struct ps3vram_priv { | ||
| 69 | u64 memory_handle; | ||
| 70 | u64 context_handle; | ||
| 71 | u32 *ctrl; | ||
| 72 | u32 *reports; | ||
| 73 | u8 __iomem *ddr_base; | ||
| 74 | u8 *xdr_buf; | ||
| 75 | |||
| 76 | u32 *fifo_base; | ||
| 77 | u32 *fifo_ptr; | ||
| 78 | |||
| 79 | struct device *dev; | ||
| 80 | struct ps3vram_cache cache; | ||
| 81 | |||
| 82 | /* Used to serialize cache/DMA operations */ | ||
| 83 | struct mutex lock; | ||
| 84 | }; | ||
| 85 | |||
| 86 | #define DMA_NOTIFIER_HANDLE_BASE 0x66604200 /* first DMA notifier handle */ | ||
| 87 | #define DMA_NOTIFIER_OFFSET_BASE 0x1000 /* first DMA notifier offset */ | ||
| 88 | #define DMA_NOTIFIER_SIZE 0x40 | ||
| 89 | #define NOTIFIER 7 /* notifier used for completion report */ | ||
| 90 | |||
| 91 | /* A trailing '-' means to subtract off ps3fb_videomemory.size */ | ||
| 92 | char *size = "256M-"; | ||
| 93 | module_param(size, charp, 0); | ||
| 94 | MODULE_PARM_DESC(size, "memory size"); | ||
| 95 | |||
| 96 | static u32 *ps3vram_get_notifier(u32 *reports, int notifier) | ||
| 97 | { | ||
| 98 | return (void *) reports + | ||
| 99 | DMA_NOTIFIER_OFFSET_BASE + | ||
| 100 | DMA_NOTIFIER_SIZE * notifier; | ||
| 101 | } | ||
| 102 | |||
| 103 | static void ps3vram_notifier_reset(struct mtd_info *mtd) | ||
| 104 | { | ||
| 105 | int i; | ||
| 106 | |||
| 107 | struct ps3vram_priv *priv = mtd->priv; | ||
| 108 | u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER); | ||
| 109 | for (i = 0; i < 4; i++) | ||
| 110 | notify[i] = 0xffffffff; | ||
| 111 | } | ||
| 112 | |||
| 113 | static int ps3vram_notifier_wait(struct mtd_info *mtd, unsigned int timeout_ms) | ||
| 114 | { | ||
| 115 | struct ps3vram_priv *priv = mtd->priv; | ||
| 116 | u32 *notify = ps3vram_get_notifier(priv->reports, NOTIFIER); | ||
| 117 | unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); | ||
| 118 | |||
| 119 | do { | ||
| 120 | if (!notify[3]) | ||
| 121 | return 0; | ||
| 122 | msleep(1); | ||
| 123 | } while (time_before(jiffies, timeout)); | ||
| 124 | |||
| 125 | return -ETIMEDOUT; | ||
| 126 | } | ||
| 127 | |||
| 128 | static void ps3vram_init_ring(struct mtd_info *mtd) | ||
| 129 | { | ||
| 130 | struct ps3vram_priv *priv = mtd->priv; | ||
| 131 | |||
| 132 | priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET; | ||
| 133 | priv->ctrl[CTRL_GET] = FIFO_BASE + FIFO_OFFSET; | ||
| 134 | } | ||
| 135 | |||
| 136 | static int ps3vram_wait_ring(struct mtd_info *mtd, unsigned int timeout_ms) | ||
| 137 | { | ||
| 138 | struct ps3vram_priv *priv = mtd->priv; | ||
| 139 | unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms); | ||
| 140 | |||
| 141 | do { | ||
| 142 | if (priv->ctrl[CTRL_PUT] == priv->ctrl[CTRL_GET]) | ||
| 143 | return 0; | ||
| 144 | msleep(1); | ||
| 145 | } while (time_before(jiffies, timeout)); | ||
| 146 | |||
| 147 | dev_dbg(priv->dev, "%s:%d: FIFO timeout (%08x/%08x/%08x)\n", __func__, | ||
| 148 | __LINE__, priv->ctrl[CTRL_PUT], priv->ctrl[CTRL_GET], | ||
| 149 | priv->ctrl[CTRL_TOP]); | ||
| 150 | |||
| 151 | return -ETIMEDOUT; | ||
| 152 | } | ||
| 153 | |||
| 154 | static void ps3vram_out_ring(struct ps3vram_priv *priv, u32 data) | ||
| 155 | { | ||
| 156 | *(priv->fifo_ptr)++ = data; | ||
| 157 | } | ||
| 158 | |||
| 159 | static void ps3vram_begin_ring(struct ps3vram_priv *priv, u32 chan, | ||
| 160 | u32 tag, u32 size) | ||
| 161 | { | ||
| 162 | ps3vram_out_ring(priv, (size << 18) | (chan << 13) | tag); | ||
| 163 | } | ||
| 164 | |||
| 165 | static void ps3vram_rewind_ring(struct mtd_info *mtd) | ||
| 166 | { | ||
| 167 | struct ps3vram_priv *priv = mtd->priv; | ||
| 168 | u64 status; | ||
| 169 | |||
| 170 | ps3vram_out_ring(priv, 0x20000000 | (FIFO_BASE + FIFO_OFFSET)); | ||
| 171 | |||
| 172 | priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET; | ||
| 173 | |||
| 174 | /* asking the HV for a blit will kick the fifo */ | ||
| 175 | status = lv1_gpu_context_attribute(priv->context_handle, | ||
| 176 | L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT, | ||
| 177 | 0, 0, 0, 0); | ||
| 178 | if (status) | ||
| 179 | dev_err(priv->dev, "%s:%d: lv1_gpu_context_attribute failed\n", | ||
| 180 | __func__, __LINE__); | ||
| 181 | |||
| 182 | priv->fifo_ptr = priv->fifo_base; | ||
| 183 | } | ||
| 184 | |||
| 185 | static void ps3vram_fire_ring(struct mtd_info *mtd) | ||
| 186 | { | ||
| 187 | struct ps3vram_priv *priv = mtd->priv; | ||
| 188 | u64 status; | ||
| 189 | |||
| 190 | mutex_lock(&ps3_gpu_mutex); | ||
| 191 | |||
| 192 | priv->ctrl[CTRL_PUT] = FIFO_BASE + FIFO_OFFSET + | ||
| 193 | (priv->fifo_ptr - priv->fifo_base) * sizeof(u32); | ||
| 194 | |||
| 195 | /* asking the HV for a blit will kick the fifo */ | ||
| 196 | status = lv1_gpu_context_attribute(priv->context_handle, | ||
| 197 | L1GPU_CONTEXT_ATTRIBUTE_FB_BLIT, | ||
| 198 | 0, 0, 0, 0); | ||
| 199 | if (status) | ||
| 200 | dev_err(priv->dev, "%s:%d: lv1_gpu_context_attribute failed\n", | ||
| 201 | __func__, __LINE__); | ||
| 202 | |||
| 203 | if ((priv->fifo_ptr - priv->fifo_base) * sizeof(u32) > | ||
| 204 | FIFO_SIZE - 1024) { | ||
| 205 | dev_dbg(priv->dev, "%s:%d: fifo full, rewinding\n", __func__, | ||
| 206 | __LINE__); | ||
| 207 | ps3vram_wait_ring(mtd, 200); | ||
| 208 | ps3vram_rewind_ring(mtd); | ||
| 209 | } | ||
| 210 | |||
| 211 | mutex_unlock(&ps3_gpu_mutex); | ||
| 212 | } | ||
| 213 | |||
| 214 | static void ps3vram_bind(struct mtd_info *mtd) | ||
| 215 | { | ||
| 216 | struct ps3vram_priv *priv = mtd->priv; | ||
| 217 | |||
| 218 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0, 1); | ||
| 219 | ps3vram_out_ring(priv, 0x31337303); | ||
| 220 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x180, 3); | ||
| 221 | ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER); | ||
| 222 | ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */ | ||
| 223 | ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */ | ||
| 224 | |||
| 225 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0, 1); | ||
| 226 | ps3vram_out_ring(priv, 0x3137c0de); | ||
| 227 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x180, 3); | ||
| 228 | ps3vram_out_ring(priv, DMA_NOTIFIER_HANDLE_BASE + NOTIFIER); | ||
| 229 | ps3vram_out_ring(priv, 0xfeed0000); /* DMA video RAM instance */ | ||
| 230 | ps3vram_out_ring(priv, 0xfeed0001); /* DMA system RAM instance */ | ||
| 231 | |||
| 232 | ps3vram_fire_ring(mtd); | ||
| 233 | } | ||
| 234 | |||
| 235 | static int ps3vram_upload(struct mtd_info *mtd, unsigned int src_offset, | ||
| 236 | unsigned int dst_offset, int len, int count) | ||
| 237 | { | ||
| 238 | struct ps3vram_priv *priv = mtd->priv; | ||
| 239 | |||
| 240 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, | ||
| 241 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | ||
| 242 | ps3vram_out_ring(priv, XDR_IOIF + src_offset); | ||
| 243 | ps3vram_out_ring(priv, dst_offset); | ||
| 244 | ps3vram_out_ring(priv, len); | ||
| 245 | ps3vram_out_ring(priv, len); | ||
| 246 | ps3vram_out_ring(priv, len); | ||
| 247 | ps3vram_out_ring(priv, count); | ||
| 248 | ps3vram_out_ring(priv, (1 << 8) | 1); | ||
| 249 | ps3vram_out_ring(priv, 0); | ||
| 250 | |||
| 251 | ps3vram_notifier_reset(mtd); | ||
| 252 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, | ||
| 253 | NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1); | ||
| 254 | ps3vram_out_ring(priv, 0); | ||
| 255 | ps3vram_begin_ring(priv, UPLOAD_SUBCH, 0x100, 1); | ||
| 256 | ps3vram_out_ring(priv, 0); | ||
| 257 | ps3vram_fire_ring(mtd); | ||
| 258 | if (ps3vram_notifier_wait(mtd, 200) < 0) { | ||
| 259 | dev_dbg(priv->dev, "%s:%d: notifier timeout\n", __func__, | ||
| 260 | __LINE__); | ||
| 261 | return -1; | ||
| 262 | } | ||
| 263 | |||
| 264 | return 0; | ||
| 265 | } | ||
| 266 | |||
| 267 | static int ps3vram_download(struct mtd_info *mtd, unsigned int src_offset, | ||
| 268 | unsigned int dst_offset, int len, int count) | ||
| 269 | { | ||
| 270 | struct ps3vram_priv *priv = mtd->priv; | ||
| 271 | |||
| 272 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, | ||
| 273 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | ||
| 274 | ps3vram_out_ring(priv, src_offset); | ||
| 275 | ps3vram_out_ring(priv, XDR_IOIF + dst_offset); | ||
| 276 | ps3vram_out_ring(priv, len); | ||
| 277 | ps3vram_out_ring(priv, len); | ||
| 278 | ps3vram_out_ring(priv, len); | ||
| 279 | ps3vram_out_ring(priv, count); | ||
| 280 | ps3vram_out_ring(priv, (1 << 8) | 1); | ||
| 281 | ps3vram_out_ring(priv, 0); | ||
| 282 | |||
| 283 | ps3vram_notifier_reset(mtd); | ||
| 284 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, | ||
| 285 | NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY, 1); | ||
| 286 | ps3vram_out_ring(priv, 0); | ||
| 287 | ps3vram_begin_ring(priv, DOWNLOAD_SUBCH, 0x100, 1); | ||
| 288 | ps3vram_out_ring(priv, 0); | ||
| 289 | ps3vram_fire_ring(mtd); | ||
| 290 | if (ps3vram_notifier_wait(mtd, 200) < 0) { | ||
| 291 | dev_dbg(priv->dev, "%s:%d: notifier timeout\n", __func__, | ||
| 292 | __LINE__); | ||
| 293 | return -1; | ||
| 294 | } | ||
| 295 | |||
| 296 | return 0; | ||
| 297 | } | ||
| 298 | |||
| 299 | static void ps3vram_cache_evict(struct mtd_info *mtd, int entry) | ||
| 300 | { | ||
| 301 | struct ps3vram_priv *priv = mtd->priv; | ||
| 302 | struct ps3vram_cache *cache = &priv->cache; | ||
| 303 | |||
| 304 | if (cache->tags[entry].flags & CACHE_PAGE_DIRTY) { | ||
| 305 | dev_dbg(priv->dev, "%s:%d: flushing %d : 0x%08x\n", __func__, | ||
| 306 | __LINE__, entry, cache->tags[entry].address); | ||
| 307 | if (ps3vram_upload(mtd, | ||
| 308 | CACHE_OFFSET + entry * cache->page_size, | ||
| 309 | cache->tags[entry].address, | ||
| 310 | DMA_PAGE_SIZE, | ||
| 311 | cache->page_size / DMA_PAGE_SIZE) < 0) { | ||
| 312 | dev_dbg(priv->dev, "%s:%d: failed to upload from " | ||
| 313 | "0x%x to 0x%x size 0x%x\n", __func__, __LINE__, | ||
| 314 | entry * cache->page_size, | ||
| 315 | cache->tags[entry].address, cache->page_size); | ||
| 316 | } | ||
| 317 | cache->tags[entry].flags &= ~CACHE_PAGE_DIRTY; | ||
| 318 | } | ||
| 319 | } | ||
| 320 | |||
| 321 | static void ps3vram_cache_load(struct mtd_info *mtd, int entry, | ||
| 322 | unsigned int address) | ||
| 323 | { | ||
| 324 | struct ps3vram_priv *priv = mtd->priv; | ||
| 325 | struct ps3vram_cache *cache = &priv->cache; | ||
| 326 | |||
| 327 | dev_dbg(priv->dev, "%s:%d: fetching %d : 0x%08x\n", __func__, __LINE__, | ||
| 328 | entry, address); | ||
| 329 | if (ps3vram_download(mtd, | ||
| 330 | address, | ||
| 331 | CACHE_OFFSET + entry * cache->page_size, | ||
| 332 | DMA_PAGE_SIZE, | ||
| 333 | cache->page_size / DMA_PAGE_SIZE) < 0) { | ||
| 334 | dev_err(priv->dev, "%s:%d: failed to download from " | ||
| 335 | "0x%x to 0x%x size 0x%x\n", __func__, __LINE__, address, | ||
| 336 | entry * cache->page_size, cache->page_size); | ||
| 337 | } | ||
| 338 | |||
| 339 | cache->tags[entry].address = address; | ||
| 340 | cache->tags[entry].flags |= CACHE_PAGE_PRESENT; | ||
| 341 | } | ||
| 342 | |||
| 343 | |||
| 344 | static void ps3vram_cache_flush(struct mtd_info *mtd) | ||
| 345 | { | ||
| 346 | struct ps3vram_priv *priv = mtd->priv; | ||
| 347 | struct ps3vram_cache *cache = &priv->cache; | ||
| 348 | int i; | ||
| 349 | |||
| 350 | dev_dbg(priv->dev, "%s:%d: FLUSH\n", __func__, __LINE__); | ||
| 351 | for (i = 0; i < cache->page_count; i++) { | ||
| 352 | ps3vram_cache_evict(mtd, i); | ||
| 353 | cache->tags[i].flags = 0; | ||
| 354 | } | ||
| 355 | } | ||
| 356 | |||
| 357 | static unsigned int ps3vram_cache_match(struct mtd_info *mtd, loff_t address) | ||
| 358 | { | ||
| 359 | struct ps3vram_priv *priv = mtd->priv; | ||
| 360 | struct ps3vram_cache *cache = &priv->cache; | ||
| 361 | unsigned int base; | ||
| 362 | unsigned int offset; | ||
| 363 | int i; | ||
| 364 | static int counter; | ||
| 365 | |||
| 366 | offset = (unsigned int) (address & (cache->page_size - 1)); | ||
| 367 | base = (unsigned int) (address - offset); | ||
| 368 | |||
| 369 | /* fully associative check */ | ||
| 370 | for (i = 0; i < cache->page_count; i++) { | ||
| 371 | if ((cache->tags[i].flags & CACHE_PAGE_PRESENT) && | ||
| 372 | cache->tags[i].address == base) { | ||
| 373 | dev_dbg(priv->dev, "%s:%d: found entry %d : 0x%08x\n", | ||
| 374 | __func__, __LINE__, i, cache->tags[i].address); | ||
| 375 | return i; | ||
| 376 | } | ||
| 377 | } | ||
| 378 | |||
| 379 | /* choose a random entry */ | ||
| 380 | i = (jiffies + (counter++)) % cache->page_count; | ||
| 381 | dev_dbg(priv->dev, "%s:%d: using entry %d\n", __func__, __LINE__, i); | ||
| 382 | |||
| 383 | ps3vram_cache_evict(mtd, i); | ||
| 384 | ps3vram_cache_load(mtd, i, base); | ||
| 385 | |||
| 386 | return i; | ||
| 387 | } | ||
| 388 | |||
| 389 | static int ps3vram_cache_init(struct mtd_info *mtd) | ||
| 390 | { | ||
| 391 | struct ps3vram_priv *priv = mtd->priv; | ||
| 392 | |||
| 393 | priv->cache.page_count = CACHE_PAGE_COUNT; | ||
| 394 | priv->cache.page_size = CACHE_PAGE_SIZE; | ||
| 395 | priv->cache.tags = kzalloc(sizeof(struct ps3vram_tag) * | ||
| 396 | CACHE_PAGE_COUNT, GFP_KERNEL); | ||
| 397 | if (priv->cache.tags == NULL) { | ||
| 398 | dev_err(priv->dev, "%s:%d: could not allocate cache tags\n", | ||
| 399 | __func__, __LINE__); | ||
| 400 | return -ENOMEM; | ||
| 401 | } | ||
| 402 | |||
| 403 | dev_info(priv->dev, "created ram cache: %d entries, %d KiB each\n", | ||
| 404 | CACHE_PAGE_COUNT, CACHE_PAGE_SIZE / 1024); | ||
| 405 | |||
| 406 | return 0; | ||
| 407 | } | ||
| 408 | |||
| 409 | static void ps3vram_cache_cleanup(struct mtd_info *mtd) | ||
| 410 | { | ||
| 411 | struct ps3vram_priv *priv = mtd->priv; | ||
| 412 | |||
| 413 | ps3vram_cache_flush(mtd); | ||
| 414 | kfree(priv->cache.tags); | ||
| 415 | } | ||
| 416 | |||
| 417 | static int ps3vram_erase(struct mtd_info *mtd, struct erase_info *instr) | ||
| 418 | { | ||
| 419 | struct ps3vram_priv *priv = mtd->priv; | ||
| 420 | |||
| 421 | if (instr->addr + instr->len > mtd->size) | ||
| 422 | return -EINVAL; | ||
| 423 | |||
| 424 | mutex_lock(&priv->lock); | ||
| 425 | |||
| 426 | ps3vram_cache_flush(mtd); | ||
| 427 | |||
| 428 | /* Set bytes to 0xFF */ | ||
| 429 | memset_io(priv->ddr_base + instr->addr, 0xFF, instr->len); | ||
| 430 | |||
| 431 | mutex_unlock(&priv->lock); | ||
| 432 | |||
| 433 | instr->state = MTD_ERASE_DONE; | ||
| 434 | mtd_erase_callback(instr); | ||
| 435 | |||
| 436 | return 0; | ||
| 437 | } | ||
| 438 | |||
| 439 | static int ps3vram_read(struct mtd_info *mtd, loff_t from, size_t len, | ||
| 440 | size_t *retlen, u_char *buf) | ||
| 441 | { | ||
| 442 | struct ps3vram_priv *priv = mtd->priv; | ||
| 443 | unsigned int cached, count; | ||
| 444 | |||
| 445 | dev_dbg(priv->dev, "%s:%d: from=0x%08x len=0x%zx\n", __func__, __LINE__, | ||
| 446 | (unsigned int)from, len); | ||
| 447 | |||
| 448 | if (from >= mtd->size) | ||
| 449 | return -EINVAL; | ||
| 450 | |||
| 451 | if (len > mtd->size - from) | ||
| 452 | len = mtd->size - from; | ||
| 453 | |||
| 454 | /* Copy from vram to buf */ | ||
| 455 | count = len; | ||
| 456 | while (count) { | ||
| 457 | unsigned int offset, avail; | ||
| 458 | unsigned int entry; | ||
| 459 | |||
| 460 | offset = (unsigned int) (from & (priv->cache.page_size - 1)); | ||
| 461 | avail = priv->cache.page_size - offset; | ||
| 462 | |||
| 463 | mutex_lock(&priv->lock); | ||
| 464 | |||
| 465 | entry = ps3vram_cache_match(mtd, from); | ||
| 466 | cached = CACHE_OFFSET + entry * priv->cache.page_size + offset; | ||
| 467 | |||
| 468 | dev_dbg(priv->dev, "%s:%d: from=%08x cached=%08x offset=%08x " | ||
| 469 | "avail=%08x count=%08x\n", __func__, __LINE__, | ||
| 470 | (unsigned int)from, cached, offset, avail, count); | ||
| 471 | |||
| 472 | if (avail > count) | ||
| 473 | avail = count; | ||
| 474 | memcpy(buf, priv->xdr_buf + cached, avail); | ||
| 475 | |||
| 476 | mutex_unlock(&priv->lock); | ||
| 477 | |||
| 478 | buf += avail; | ||
| 479 | count -= avail; | ||
| 480 | from += avail; | ||
| 481 | } | ||
| 482 | |||
| 483 | *retlen = len; | ||
| 484 | return 0; | ||
| 485 | } | ||
| 486 | |||
| 487 | static int ps3vram_write(struct mtd_info *mtd, loff_t to, size_t len, | ||
| 488 | size_t *retlen, const u_char *buf) | ||
| 489 | { | ||
| 490 | struct ps3vram_priv *priv = mtd->priv; | ||
| 491 | unsigned int cached, count; | ||
| 492 | |||
| 493 | if (to >= mtd->size) | ||
| 494 | return -EINVAL; | ||
| 495 | |||
| 496 | if (len > mtd->size - to) | ||
| 497 | len = mtd->size - to; | ||
| 498 | |||
| 499 | /* Copy from buf to vram */ | ||
| 500 | count = len; | ||
| 501 | while (count) { | ||
| 502 | unsigned int offset, avail; | ||
| 503 | unsigned int entry; | ||
| 504 | |||
| 505 | offset = (unsigned int) (to & (priv->cache.page_size - 1)); | ||
| 506 | avail = priv->cache.page_size - offset; | ||
| 507 | |||
| 508 | mutex_lock(&priv->lock); | ||
| 509 | |||
| 510 | entry = ps3vram_cache_match(mtd, to); | ||
| 511 | cached = CACHE_OFFSET + entry * priv->cache.page_size + offset; | ||
| 512 | |||
| 513 | dev_dbg(priv->dev, "%s:%d: to=%08x cached=%08x offset=%08x " | ||
| 514 | "avail=%08x count=%08x\n", __func__, __LINE__, | ||
| 515 | (unsigned int)to, cached, offset, avail, count); | ||
| 516 | |||
| 517 | if (avail > count) | ||
| 518 | avail = count; | ||
| 519 | memcpy(priv->xdr_buf + cached, buf, avail); | ||
| 520 | |||
| 521 | priv->cache.tags[entry].flags |= CACHE_PAGE_DIRTY; | ||
| 522 | |||
| 523 | mutex_unlock(&priv->lock); | ||
| 524 | |||
| 525 | buf += avail; | ||
| 526 | count -= avail; | ||
| 527 | to += avail; | ||
| 528 | } | ||
| 529 | |||
| 530 | *retlen = len; | ||
| 531 | return 0; | ||
| 532 | } | ||
| 533 | |||
| 534 | static int __devinit ps3vram_probe(struct ps3_system_bus_device *dev) | ||
| 535 | { | ||
| 536 | struct ps3vram_priv *priv; | ||
| 537 | int status; | ||
| 538 | u64 ddr_lpar; | ||
| 539 | u64 ctrl_lpar; | ||
| 540 | u64 info_lpar; | ||
| 541 | u64 reports_lpar; | ||
| 542 | u64 ddr_size; | ||
| 543 | u64 reports_size; | ||
| 544 | int ret = -ENOMEM; | ||
| 545 | char *rest; | ||
| 546 | |||
| 547 | ret = -EIO; | ||
| 548 | ps3vram_mtd.priv = kzalloc(sizeof(struct ps3vram_priv), GFP_KERNEL); | ||
| 549 | if (!ps3vram_mtd.priv) | ||
| 550 | goto out; | ||
| 551 | priv = ps3vram_mtd.priv; | ||
| 552 | |||
| 553 | mutex_init(&priv->lock); | ||
| 554 | priv->dev = &dev->core; | ||
| 555 | |||
| 556 | /* Allocate XDR buffer (1MiB aligned) */ | ||
| 557 | priv->xdr_buf = (void *)__get_free_pages(GFP_KERNEL, | ||
| 558 | get_order(XDR_BUF_SIZE)); | ||
| 559 | if (priv->xdr_buf == NULL) { | ||
| 560 | dev_dbg(&dev->core, "%s:%d: could not allocate XDR buffer\n", | ||
| 561 | __func__, __LINE__); | ||
| 562 | ret = -ENOMEM; | ||
| 563 | goto out_free_priv; | ||
| 564 | } | ||
| 565 | |||
| 566 | /* Put FIFO at begginning of XDR buffer */ | ||
| 567 | priv->fifo_base = (u32 *) (priv->xdr_buf + FIFO_OFFSET); | ||
| 568 | priv->fifo_ptr = priv->fifo_base; | ||
| 569 | |||
| 570 | /* XXX: Need to open GPU, in case ps3fb or snd_ps3 aren't loaded */ | ||
| 571 | if (ps3_open_hv_device(dev)) { | ||
| 572 | dev_err(&dev->core, "%s:%d: ps3_open_hv_device failed\n", | ||
| 573 | __func__, __LINE__); | ||
| 574 | ret = -EAGAIN; | ||
| 575 | goto out_close_gpu; | ||
| 576 | } | ||
| 577 | |||
| 578 | /* Request memory */ | ||
| 579 | status = -1; | ||
| 580 | ddr_size = memparse(size, &rest); | ||
| 581 | if (*rest == '-') | ||
| 582 | ddr_size -= ps3fb_videomemory.size; | ||
| 583 | ddr_size = ALIGN(ddr_size, 1024*1024); | ||
| 584 | if (ddr_size <= 0) { | ||
| 585 | dev_err(&dev->core, "%s:%d: specified size is too small\n", | ||
| 586 | __func__, __LINE__); | ||
| 587 | ret = -EINVAL; | ||
| 588 | goto out_close_gpu; | ||
| 589 | } | ||
| 590 | |||
| 591 | while (ddr_size > 0) { | ||
| 592 | status = lv1_gpu_memory_allocate(ddr_size, 0, 0, 0, 0, | ||
| 593 | &priv->memory_handle, | ||
| 594 | &ddr_lpar); | ||
| 595 | if (!status) | ||
| 596 | break; | ||
| 597 | ddr_size -= 1024*1024; | ||
| 598 | } | ||
| 599 | if (status || ddr_size <= 0) { | ||
| 600 | dev_err(&dev->core, "%s:%d: lv1_gpu_memory_allocate failed\n", | ||
| 601 | __func__, __LINE__); | ||
| 602 | ret = -ENOMEM; | ||
| 603 | goto out_free_xdr_buf; | ||
| 604 | } | ||
| 605 | |||
| 606 | /* Request context */ | ||
| 607 | status = lv1_gpu_context_allocate(priv->memory_handle, | ||
| 608 | 0, | ||
| 609 | &priv->context_handle, | ||
| 610 | &ctrl_lpar, | ||
| 611 | &info_lpar, | ||
| 612 | &reports_lpar, | ||
| 613 | &reports_size); | ||
| 614 | if (status) { | ||
| 615 | dev_err(&dev->core, "%s:%d: lv1_gpu_context_allocate failed\n", | ||
| 616 | __func__, __LINE__); | ||
| 617 | ret = -ENOMEM; | ||
| 618 | goto out_free_memory; | ||
| 619 | } | ||
| 620 | |||
| 621 | /* Map XDR buffer to RSX */ | ||
| 622 | status = lv1_gpu_context_iomap(priv->context_handle, XDR_IOIF, | ||
| 623 | ps3_mm_phys_to_lpar(__pa(priv->xdr_buf)), | ||
| 624 | XDR_BUF_SIZE, 0); | ||
| 625 | if (status) { | ||
| 626 | dev_err(&dev->core, "%s:%d: lv1_gpu_context_iomap failed\n", | ||
| 627 | __func__, __LINE__); | ||
| 628 | ret = -ENOMEM; | ||
| 629 | goto out_free_context; | ||
| 630 | } | ||
| 631 | |||
| 632 | priv->ddr_base = ioremap_flags(ddr_lpar, ddr_size, _PAGE_NO_CACHE); | ||
| 633 | |||
| 634 | if (!priv->ddr_base) { | ||
| 635 | dev_err(&dev->core, "%s:%d: ioremap failed\n", __func__, | ||
| 636 | __LINE__); | ||
| 637 | ret = -ENOMEM; | ||
| 638 | goto out_free_context; | ||
| 639 | } | ||
| 640 | |||
| 641 | priv->ctrl = ioremap(ctrl_lpar, 64 * 1024); | ||
| 642 | if (!priv->ctrl) { | ||
| 643 | dev_err(&dev->core, "%s:%d: ioremap failed\n", __func__, | ||
| 644 | __LINE__); | ||
| 645 | ret = -ENOMEM; | ||
| 646 | goto out_unmap_vram; | ||
| 647 | } | ||
| 648 | |||
| 649 | priv->reports = ioremap(reports_lpar, reports_size); | ||
| 650 | if (!priv->reports) { | ||
| 651 | dev_err(&dev->core, "%s:%d: ioremap failed\n", __func__, | ||
| 652 | __LINE__); | ||
| 653 | ret = -ENOMEM; | ||
| 654 | goto out_unmap_ctrl; | ||
| 655 | } | ||
| 656 | |||
| 657 | mutex_lock(&ps3_gpu_mutex); | ||
| 658 | ps3vram_init_ring(&ps3vram_mtd); | ||
| 659 | mutex_unlock(&ps3_gpu_mutex); | ||
| 660 | |||
| 661 | ps3vram_mtd.name = "ps3vram"; | ||
| 662 | ps3vram_mtd.size = ddr_size; | ||
| 663 | ps3vram_mtd.flags = MTD_CAP_RAM; | ||
| 664 | ps3vram_mtd.erase = ps3vram_erase; | ||
| 665 | ps3vram_mtd.point = NULL; | ||
| 666 | ps3vram_mtd.unpoint = NULL; | ||
| 667 | ps3vram_mtd.read = ps3vram_read; | ||
| 668 | ps3vram_mtd.write = ps3vram_write; | ||
| 669 | ps3vram_mtd.owner = THIS_MODULE; | ||
| 670 | ps3vram_mtd.type = MTD_RAM; | ||
| 671 | ps3vram_mtd.erasesize = CACHE_PAGE_SIZE; | ||
| 672 | ps3vram_mtd.writesize = 1; | ||
| 673 | |||
| 674 | ps3vram_bind(&ps3vram_mtd); | ||
| 675 | |||
| 676 | mutex_lock(&ps3_gpu_mutex); | ||
| 677 | ret = ps3vram_wait_ring(&ps3vram_mtd, 100); | ||
| 678 | mutex_unlock(&ps3_gpu_mutex); | ||
| 679 | if (ret < 0) { | ||
| 680 | dev_err(&dev->core, "%s:%d: failed to initialize channels\n", | ||
| 681 | __func__, __LINE__); | ||
| 682 | ret = -ETIMEDOUT; | ||
| 683 | goto out_unmap_reports; | ||
| 684 | } | ||
| 685 | |||
| 686 | ps3vram_cache_init(&ps3vram_mtd); | ||
| 687 | |||
| 688 | if (add_mtd_device(&ps3vram_mtd)) { | ||
| 689 | dev_err(&dev->core, "%s:%d: add_mtd_device failed\n", | ||
| 690 | __func__, __LINE__); | ||
| 691 | ret = -EAGAIN; | ||
| 692 | goto out_cache_cleanup; | ||
| 693 | } | ||
| 694 | |||
| 695 | dev_info(&dev->core, "reserved %u MiB of gpu memory\n", | ||
| 696 | (unsigned int)(ddr_size / 1024 / 1024)); | ||
| 697 | |||
| 698 | return 0; | ||
| 699 | |||
| 700 | out_cache_cleanup: | ||
| 701 | ps3vram_cache_cleanup(&ps3vram_mtd); | ||
| 702 | out_unmap_reports: | ||
| 703 | iounmap(priv->reports); | ||
| 704 | out_unmap_ctrl: | ||
| 705 | iounmap(priv->ctrl); | ||
| 706 | out_unmap_vram: | ||
| 707 | iounmap(priv->ddr_base); | ||
| 708 | out_free_context: | ||
| 709 | lv1_gpu_context_free(priv->context_handle); | ||
| 710 | out_free_memory: | ||
| 711 | lv1_gpu_memory_free(priv->memory_handle); | ||
| 712 | out_close_gpu: | ||
| 713 | ps3_close_hv_device(dev); | ||
| 714 | out_free_xdr_buf: | ||
| 715 | free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE)); | ||
| 716 | out_free_priv: | ||
| 717 | kfree(ps3vram_mtd.priv); | ||
| 718 | ps3vram_mtd.priv = NULL; | ||
| 719 | out: | ||
| 720 | return ret; | ||
| 721 | } | ||
| 722 | |||
| 723 | static int ps3vram_shutdown(struct ps3_system_bus_device *dev) | ||
| 724 | { | ||
| 725 | struct ps3vram_priv *priv; | ||
| 726 | |||
| 727 | priv = ps3vram_mtd.priv; | ||
| 728 | |||
| 729 | del_mtd_device(&ps3vram_mtd); | ||
| 730 | ps3vram_cache_cleanup(&ps3vram_mtd); | ||
| 731 | iounmap(priv->reports); | ||
| 732 | iounmap(priv->ctrl); | ||
| 733 | iounmap(priv->ddr_base); | ||
| 734 | lv1_gpu_context_free(priv->context_handle); | ||
| 735 | lv1_gpu_memory_free(priv->memory_handle); | ||
| 736 | ps3_close_hv_device(dev); | ||
| 737 | free_pages((unsigned long) priv->xdr_buf, get_order(XDR_BUF_SIZE)); | ||
| 738 | kfree(priv); | ||
| 739 | return 0; | ||
| 740 | } | ||
| 741 | |||
| 742 | static struct ps3_system_bus_driver ps3vram_driver = { | ||
| 743 | .match_id = PS3_MATCH_ID_GPU, | ||
| 744 | .match_sub_id = PS3_MATCH_SUB_ID_GPU_RAMDISK, | ||
| 745 | .core.name = DEVICE_NAME, | ||
| 746 | .core.owner = THIS_MODULE, | ||
| 747 | .probe = ps3vram_probe, | ||
| 748 | .remove = ps3vram_shutdown, | ||
| 749 | .shutdown = ps3vram_shutdown, | ||
| 750 | }; | ||
| 751 | |||
| 752 | static int __init ps3vram_init(void) | ||
| 753 | { | ||
| 754 | return ps3_system_bus_driver_register(&ps3vram_driver); | ||
| 755 | } | ||
| 756 | |||
| 757 | static void __exit ps3vram_exit(void) | ||
| 758 | { | ||
| 759 | ps3_system_bus_driver_unregister(&ps3vram_driver); | ||
| 760 | } | ||
| 761 | |||
| 762 | module_init(ps3vram_init); | ||
| 763 | module_exit(ps3vram_exit); | ||
| 764 | |||
| 765 | MODULE_LICENSE("GPL"); | ||
| 766 | MODULE_AUTHOR("Jim Paris <jim@jtan.com>"); | ||
| 767 | MODULE_DESCRIPTION("MTD driver for PS3 video RAM"); | ||
| 768 | MODULE_ALIAS(PS3_MODULE_ALIAS_GPU_RAMDISK); | ||
diff --git a/drivers/mtd/maps/integrator-flash.c b/drivers/mtd/maps/integrator-flash.c index d2ec262666c7..c9681a339a59 100644 --- a/drivers/mtd/maps/integrator-flash.c +++ b/drivers/mtd/maps/integrator-flash.c | |||
| @@ -31,6 +31,7 @@ | |||
| 31 | #include <linux/ioport.h> | 31 | #include <linux/ioport.h> |
| 32 | #include <linux/platform_device.h> | 32 | #include <linux/platform_device.h> |
| 33 | #include <linux/init.h> | 33 | #include <linux/init.h> |
| 34 | #include <linux/io.h> | ||
| 34 | 35 | ||
| 35 | #include <linux/mtd/mtd.h> | 36 | #include <linux/mtd/mtd.h> |
| 36 | #include <linux/mtd/map.h> | 37 | #include <linux/mtd/map.h> |
| @@ -38,7 +39,6 @@ | |||
| 38 | 39 | ||
| 39 | #include <asm/mach/flash.h> | 40 | #include <asm/mach/flash.h> |
| 40 | #include <mach/hardware.h> | 41 | #include <mach/hardware.h> |
| 41 | #include <asm/io.h> | ||
| 42 | #include <asm/system.h> | 42 | #include <asm/system.h> |
| 43 | 43 | ||
| 44 | #ifdef CONFIG_ARCH_P720T | 44 | #ifdef CONFIG_ARCH_P720T |
diff --git a/drivers/mtd/maps/physmap.c b/drivers/mtd/maps/physmap.c index 4b122e7ab4b3..229718222db7 100644 --- a/drivers/mtd/maps/physmap.c +++ b/drivers/mtd/maps/physmap.c | |||
| @@ -46,16 +46,19 @@ static int physmap_flash_remove(struct platform_device *dev) | |||
| 46 | 46 | ||
| 47 | physmap_data = dev->dev.platform_data; | 47 | physmap_data = dev->dev.platform_data; |
| 48 | 48 | ||
| 49 | if (info->cmtd) { | ||
| 49 | #ifdef CONFIG_MTD_PARTITIONS | 50 | #ifdef CONFIG_MTD_PARTITIONS |
| 50 | if (info->nr_parts) { | 51 | if (info->nr_parts || physmap_data->nr_parts) |
| 51 | del_mtd_partitions(info->cmtd); | 52 | del_mtd_partitions(info->cmtd); |
| 52 | kfree(info->parts); | 53 | else |
| 53 | } else if (physmap_data->nr_parts) | 54 | del_mtd_device(info->cmtd); |
| 54 | del_mtd_partitions(info->cmtd); | ||
| 55 | else | ||
| 56 | del_mtd_device(info->cmtd); | ||
| 57 | #else | 55 | #else |
| 58 | del_mtd_device(info->cmtd); | 56 | del_mtd_device(info->cmtd); |
| 57 | #endif | ||
| 58 | } | ||
| 59 | #ifdef CONFIG_MTD_PARTITIONS | ||
| 60 | if (info->nr_parts) | ||
| 61 | kfree(info->parts); | ||
| 59 | #endif | 62 | #endif |
| 60 | 63 | ||
| 61 | #ifdef CONFIG_MTD_CONCAT | 64 | #ifdef CONFIG_MTD_CONCAT |
diff --git a/drivers/mtd/maps/sa1100-flash.c b/drivers/mtd/maps/sa1100-flash.c index 6f6a0f6dafd6..8f57b6f40aa2 100644 --- a/drivers/mtd/maps/sa1100-flash.c +++ b/drivers/mtd/maps/sa1100-flash.c | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | #include <linux/slab.h> | 12 | #include <linux/slab.h> |
| 13 | #include <linux/platform_device.h> | 13 | #include <linux/platform_device.h> |
| 14 | #include <linux/err.h> | 14 | #include <linux/err.h> |
| 15 | #include <linux/io.h> | ||
| 15 | 16 | ||
| 16 | #include <linux/mtd/mtd.h> | 17 | #include <linux/mtd/mtd.h> |
| 17 | #include <linux/mtd/map.h> | 18 | #include <linux/mtd/map.h> |
| @@ -19,7 +20,6 @@ | |||
| 19 | #include <linux/mtd/concat.h> | 20 | #include <linux/mtd/concat.h> |
| 20 | 21 | ||
| 21 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
| 22 | #include <asm/io.h> | ||
| 23 | #include <asm/sizes.h> | 23 | #include <asm/sizes.h> |
| 24 | #include <asm/mach/flash.h> | 24 | #include <asm/mach/flash.h> |
| 25 | 25 | ||
diff --git a/drivers/mtd/nand/cmx270_nand.c b/drivers/mtd/nand/cmx270_nand.c index fa129c09bca8..10081e656a6f 100644 --- a/drivers/mtd/nand/cmx270_nand.c +++ b/drivers/mtd/nand/cmx270_nand.c | |||
| @@ -26,8 +26,7 @@ | |||
| 26 | #include <asm/irq.h> | 26 | #include <asm/irq.h> |
| 27 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
| 28 | 28 | ||
| 29 | #include <mach/hardware.h> | 29 | #include <mach/pxa2xx-regs.h> |
| 30 | #include <mach/pxa-regs.h> | ||
| 31 | 30 | ||
| 32 | #define GPIO_NAND_CS (11) | 31 | #define GPIO_NAND_CS (11) |
| 33 | #define GPIO_NAND_RB (89) | 32 | #define GPIO_NAND_RB (89) |
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 21fd4f1c4806..bad048aca89a 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c | |||
| @@ -880,7 +880,7 @@ static int __init mxcnd_probe(struct platform_device *pdev) | |||
| 880 | this->read_buf = mxc_nand_read_buf; | 880 | this->read_buf = mxc_nand_read_buf; |
| 881 | this->verify_buf = mxc_nand_verify_buf; | 881 | this->verify_buf = mxc_nand_verify_buf; |
| 882 | 882 | ||
| 883 | host->clk = clk_get(&pdev->dev, "nfc_clk"); | 883 | host->clk = clk_get(&pdev->dev, "nfc"); |
| 884 | if (IS_ERR(host->clk)) | 884 | if (IS_ERR(host->clk)) |
| 885 | goto eclk; | 885 | goto eclk; |
| 886 | 886 | ||
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index cc55cbc2b308..61b69cc40009 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c | |||
| @@ -22,7 +22,6 @@ | |||
| 22 | #include <linux/irq.h> | 22 | #include <linux/irq.h> |
| 23 | 23 | ||
| 24 | #include <mach/dma.h> | 24 | #include <mach/dma.h> |
| 25 | #include <mach/pxa-regs.h> | ||
| 26 | #include <mach/pxa3xx_nand.h> | 25 | #include <mach/pxa3xx_nand.h> |
| 27 | 26 | ||
| 28 | #define CHIP_DELAY_TIMEOUT (2 * HZ/10) | 27 | #define CHIP_DELAY_TIMEOUT (2 * HZ/10) |
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index a2f185fd7072..62d732a886f1 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig | |||
| @@ -1040,6 +1040,17 @@ config NI65 | |||
| 1040 | To compile this driver as a module, choose M here. The module | 1040 | To compile this driver as a module, choose M here. The module |
| 1041 | will be called ni65. | 1041 | will be called ni65. |
| 1042 | 1042 | ||
| 1043 | config DNET | ||
| 1044 | tristate "Dave ethernet support (DNET)" | ||
| 1045 | depends on NET_ETHERNET && HAS_IOMEM | ||
| 1046 | select PHYLIB | ||
| 1047 | help | ||
| 1048 | The Dave ethernet interface (DNET) is found on Qong Board FPGA. | ||
| 1049 | Say Y to include support for the DNET chip. | ||
| 1050 | |||
| 1051 | To compile this driver as a module, choose M here: the module | ||
| 1052 | will be called dnet. | ||
| 1053 | |||
| 1043 | source "drivers/net/tulip/Kconfig" | 1054 | source "drivers/net/tulip/Kconfig" |
| 1044 | 1055 | ||
| 1045 | config AT1700 | 1056 | config AT1700 |
| @@ -2619,6 +2630,8 @@ config QLGE | |||
| 2619 | 2630 | ||
| 2620 | source "drivers/net/sfc/Kconfig" | 2631 | source "drivers/net/sfc/Kconfig" |
| 2621 | 2632 | ||
| 2633 | source "drivers/net/benet/Kconfig" | ||
| 2634 | |||
| 2622 | endif # NETDEV_10000 | 2635 | endif # NETDEV_10000 |
| 2623 | 2636 | ||
| 2624 | source "drivers/net/tokenring/Kconfig" | 2637 | source "drivers/net/tokenring/Kconfig" |
diff --git a/drivers/net/Makefile b/drivers/net/Makefile index aca8492db654..471baaff229f 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile | |||
| @@ -22,6 +22,7 @@ obj-$(CONFIG_GIANFAR) += gianfar_driver.o | |||
| 22 | obj-$(CONFIG_TEHUTI) += tehuti.o | 22 | obj-$(CONFIG_TEHUTI) += tehuti.o |
| 23 | obj-$(CONFIG_ENIC) += enic/ | 23 | obj-$(CONFIG_ENIC) += enic/ |
| 24 | obj-$(CONFIG_JME) += jme.o | 24 | obj-$(CONFIG_JME) += jme.o |
| 25 | obj-$(CONFIG_BE2NET) += benet/ | ||
| 25 | 26 | ||
| 26 | gianfar_driver-objs := gianfar.o \ | 27 | gianfar_driver-objs := gianfar.o \ |
| 27 | gianfar_ethtool.o \ | 28 | gianfar_ethtool.o \ |
| @@ -231,6 +232,7 @@ obj-$(CONFIG_ENC28J60) += enc28j60.o | |||
| 231 | 232 | ||
| 232 | obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o | 233 | obj-$(CONFIG_XTENSA_XT2000_SONIC) += xtsonic.o |
| 233 | 234 | ||
| 235 | obj-$(CONFIG_DNET) += dnet.o | ||
| 234 | obj-$(CONFIG_MACB) += macb.o | 236 | obj-$(CONFIG_MACB) += macb.o |
| 235 | 237 | ||
| 236 | obj-$(CONFIG_ARM) += arm/ | 238 | obj-$(CONFIG_ARM) += arm/ |
diff --git a/drivers/net/arm/am79c961a.c b/drivers/net/arm/am79c961a.c index c2d012fcc29b..4bc6901b3819 100644 --- a/drivers/net/arm/am79c961a.c +++ b/drivers/net/arm/am79c961a.c | |||
| @@ -27,9 +27,9 @@ | |||
| 27 | #include <linux/crc32.h> | 27 | #include <linux/crc32.h> |
| 28 | #include <linux/bitops.h> | 28 | #include <linux/bitops.h> |
| 29 | #include <linux/platform_device.h> | 29 | #include <linux/platform_device.h> |
| 30 | #include <linux/io.h> | ||
| 30 | 31 | ||
| 31 | #include <mach/hardware.h> | 32 | #include <mach/hardware.h> |
| 32 | #include <asm/io.h> | ||
| 33 | #include <asm/system.h> | 33 | #include <asm/system.h> |
| 34 | 34 | ||
| 35 | #define TX_BUFFERS 15 | 35 | #define TX_BUFFERS 15 |
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c index 5fce1d5c1a1a..9cc43476bfa6 100644 --- a/drivers/net/arm/ixp4xx_eth.c +++ b/drivers/net/arm/ixp4xx_eth.c | |||
| @@ -335,11 +335,20 @@ static int ixp4xx_mdio_register(void) | |||
| 335 | if (!(mdio_bus = mdiobus_alloc())) | 335 | if (!(mdio_bus = mdiobus_alloc())) |
| 336 | return -ENOMEM; | 336 | return -ENOMEM; |
| 337 | 337 | ||
| 338 | /* All MII PHY accesses use NPE-B Ethernet registers */ | 338 | if (cpu_is_ixp43x()) { |
| 339 | spin_lock_init(&mdio_lock); | 339 | /* IXP43x lacks NPE-B and uses NPE-C for MII PHY access */ |
| 340 | mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; | 340 | if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEC_ETH)) |
| 341 | __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); | 341 | return -ENOSYS; |
| 342 | mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthC_BASE_VIRT; | ||
| 343 | } else { | ||
| 344 | /* All MII PHY accesses use NPE-B Ethernet registers */ | ||
| 345 | if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0)) | ||
| 346 | return -ENOSYS; | ||
| 347 | mdio_regs = (struct eth_regs __iomem *)IXP4XX_EthB_BASE_VIRT; | ||
| 348 | } | ||
| 342 | 349 | ||
| 350 | __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); | ||
| 351 | spin_lock_init(&mdio_lock); | ||
| 343 | mdio_bus->name = "IXP4xx MII Bus"; | 352 | mdio_bus->name = "IXP4xx MII Bus"; |
| 344 | mdio_bus->read = &ixp4xx_mdio_read; | 353 | mdio_bus->read = &ixp4xx_mdio_read; |
| 345 | mdio_bus->write = &ixp4xx_mdio_write; | 354 | mdio_bus->write = &ixp4xx_mdio_write; |
| @@ -1250,9 +1259,6 @@ static struct platform_driver ixp4xx_eth_driver = { | |||
| 1250 | static int __init eth_init_module(void) | 1259 | static int __init eth_init_module(void) |
| 1251 | { | 1260 | { |
| 1252 | int err; | 1261 | int err; |
| 1253 | if (!(ixp4xx_read_feature_bits() & IXP4XX_FEATURE_NPEB_ETH0)) | ||
| 1254 | return -ENOSYS; | ||
| 1255 | |||
| 1256 | if ((err = ixp4xx_mdio_register())) | 1262 | if ((err = ixp4xx_mdio_register())) |
| 1257 | return err; | 1263 | return err; |
| 1258 | return platform_driver_register(&ixp4xx_eth_driver); | 1264 | return platform_driver_register(&ixp4xx_eth_driver); |
diff --git a/drivers/net/arm/ks8695net.c b/drivers/net/arm/ks8695net.c index 1cf2f949c0b4..f3a127434897 100644 --- a/drivers/net/arm/ks8695net.c +++ b/drivers/net/arm/ks8695net.c | |||
| @@ -560,7 +560,7 @@ ks8695_reset(struct ks8695_priv *ksp) | |||
| 560 | msleep(1); | 560 | msleep(1); |
| 561 | } | 561 | } |
| 562 | 562 | ||
| 563 | if (reset_timeout == 0) { | 563 | if (reset_timeout < 0) { |
| 564 | dev_crit(ksp->dev, | 564 | dev_crit(ksp->dev, |
| 565 | "Timeout waiting for DMA engines to reset\n"); | 565 | "Timeout waiting for DMA engines to reset\n"); |
| 566 | /* And blithely carry on */ | 566 | /* And blithely carry on */ |
diff --git a/drivers/net/benet/Kconfig b/drivers/net/benet/Kconfig new file mode 100644 index 000000000000..c6934f179c09 --- /dev/null +++ b/drivers/net/benet/Kconfig | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | config BE2NET | ||
| 2 | tristate "ServerEngines' 10Gbps NIC - BladeEngine 2" | ||
| 3 | depends on PCI && INET | ||
| 4 | select INET_LRO | ||
| 5 | help | ||
| 6 | This driver implements the NIC functionality for ServerEngines' | ||
| 7 | 10Gbps network adapter - BladeEngine 2. | ||
diff --git a/drivers/net/benet/Makefile b/drivers/net/benet/Makefile new file mode 100644 index 000000000000..a60cd8051135 --- /dev/null +++ b/drivers/net/benet/Makefile | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | # | ||
| 2 | # Makefile to build the network driver for ServerEngine's BladeEngine. | ||
| 3 | # | ||
| 4 | |||
| 5 | obj-$(CONFIG_BE2NET) += be2net.o | ||
| 6 | |||
| 7 | be2net-y := be_main.o be_cmds.o be_ethtool.o | ||
diff --git a/drivers/net/benet/be.h b/drivers/net/benet/be.h new file mode 100644 index 000000000000..f327be57ca96 --- /dev/null +++ b/drivers/net/benet/be.h | |||
| @@ -0,0 +1,328 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2009 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | |||
| 18 | #ifndef BE_H | ||
| 19 | #define BE_H | ||
| 20 | |||
| 21 | #include <linux/pci.h> | ||
| 22 | #include <linux/etherdevice.h> | ||
| 23 | #include <linux/version.h> | ||
| 24 | #include <linux/delay.h> | ||
| 25 | #include <net/tcp.h> | ||
| 26 | #include <net/ip.h> | ||
| 27 | #include <net/ipv6.h> | ||
| 28 | #include <linux/if_vlan.h> | ||
| 29 | #include <linux/workqueue.h> | ||
| 30 | #include <linux/interrupt.h> | ||
| 31 | #include <linux/inet_lro.h> | ||
| 32 | |||
| 33 | #include "be_hw.h" | ||
| 34 | |||
| 35 | #define DRV_VER "2.0.348" | ||
| 36 | #define DRV_NAME "be2net" | ||
| 37 | #define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC" | ||
| 38 | #define DRV_DESC BE_NAME "Driver" | ||
| 39 | |||
| 40 | /* Number of bytes of an RX frame that are copied to skb->data */ | ||
| 41 | #define BE_HDR_LEN 64 | ||
| 42 | #define BE_MAX_JUMBO_FRAME_SIZE 9018 | ||
| 43 | #define BE_MIN_MTU 256 | ||
| 44 | |||
| 45 | #define BE_NUM_VLANS_SUPPORTED 64 | ||
| 46 | #define BE_MAX_EQD 96 | ||
| 47 | #define BE_MAX_TX_FRAG_COUNT 30 | ||
| 48 | |||
| 49 | #define EVNT_Q_LEN 1024 | ||
| 50 | #define TX_Q_LEN 2048 | ||
| 51 | #define TX_CQ_LEN 1024 | ||
| 52 | #define RX_Q_LEN 1024 /* Does not support any other value */ | ||
| 53 | #define RX_CQ_LEN 1024 | ||
| 54 | #define MCC_Q_LEN 64 /* total size not to exceed 8 pages */ | ||
| 55 | #define MCC_CQ_LEN 256 | ||
| 56 | |||
| 57 | #define BE_NAPI_WEIGHT 64 | ||
| 58 | #define MAX_RX_POST BE_NAPI_WEIGHT /* Frags posted at a time */ | ||
| 59 | #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) | ||
| 60 | |||
| 61 | #define BE_MAX_LRO_DESCRIPTORS 16 | ||
| 62 | #define BE_MAX_FRAGS_PER_FRAME 16 | ||
| 63 | |||
| 64 | struct be_dma_mem { | ||
| 65 | void *va; | ||
| 66 | dma_addr_t dma; | ||
| 67 | u32 size; | ||
| 68 | }; | ||
| 69 | |||
| 70 | struct be_queue_info { | ||
| 71 | struct be_dma_mem dma_mem; | ||
| 72 | u16 len; | ||
| 73 | u16 entry_size; /* Size of an element in the queue */ | ||
| 74 | u16 id; | ||
| 75 | u16 tail, head; | ||
| 76 | bool created; | ||
| 77 | atomic_t used; /* Number of valid elements in the queue */ | ||
| 78 | }; | ||
| 79 | |||
| 80 | struct be_ctrl_info { | ||
| 81 | u8 __iomem *csr; | ||
| 82 | u8 __iomem *db; /* Door Bell */ | ||
| 83 | u8 __iomem *pcicfg; /* PCI config space */ | ||
| 84 | int pci_func; | ||
| 85 | |||
| 86 | /* Mbox used for cmd request/response */ | ||
| 87 | spinlock_t cmd_lock; /* For serializing cmds to BE card */ | ||
| 88 | struct be_dma_mem mbox_mem; | ||
| 89 | /* Mbox mem is adjusted to align to 16 bytes. The allocated addr | ||
| 90 | * is stored for freeing purpose */ | ||
| 91 | struct be_dma_mem mbox_mem_alloced; | ||
| 92 | }; | ||
| 93 | |||
| 94 | #include "be_cmds.h" | ||
| 95 | |||
| 96 | struct be_drvr_stats { | ||
| 97 | u32 be_tx_reqs; /* number of TX requests initiated */ | ||
| 98 | u32 be_tx_stops; /* number of times TX Q was stopped */ | ||
| 99 | u32 be_fwd_reqs; /* number of send reqs through forwarding i/f */ | ||
| 100 | u32 be_tx_wrbs; /* number of tx WRBs used */ | ||
| 101 | u32 be_tx_events; /* number of tx completion events */ | ||
| 102 | u32 be_tx_compl; /* number of tx completion entries processed */ | ||
| 103 | u64 be_tx_jiffies; | ||
| 104 | ulong be_tx_bytes; | ||
| 105 | ulong be_tx_bytes_prev; | ||
| 106 | u32 be_tx_rate; | ||
| 107 | |||
| 108 | u32 cache_barrier[16]; | ||
| 109 | |||
| 110 | u32 be_ethrx_post_fail;/* number of ethrx buffer alloc failures */ | ||
| 111 | u32 be_polls; /* number of times NAPI called poll function */ | ||
| 112 | u32 be_rx_events; /* number of ucast rx completion events */ | ||
| 113 | u32 be_rx_compl; /* number of rx completion entries processed */ | ||
| 114 | u32 be_lro_hgram_data[8]; /* histogram of LRO data packets */ | ||
| 115 | u32 be_lro_hgram_ack[8]; /* histogram of LRO ACKs */ | ||
| 116 | u64 be_rx_jiffies; | ||
| 117 | ulong be_rx_bytes; | ||
| 118 | ulong be_rx_bytes_prev; | ||
| 119 | u32 be_rx_rate; | ||
| 120 | /* number of non ether type II frames dropped where | ||
| 121 | * frame len > length field of Mac Hdr */ | ||
| 122 | u32 be_802_3_dropped_frames; | ||
| 123 | /* number of non ether type II frames malformed where | ||
| 124 | * in frame len < length field of Mac Hdr */ | ||
| 125 | u32 be_802_3_malformed_frames; | ||
| 126 | u32 be_rxcp_err; /* Num rx completion entries w/ err set. */ | ||
| 127 | ulong rx_fps_jiffies; /* jiffies at last FPS calc */ | ||
| 128 | u32 be_rx_frags; | ||
| 129 | u32 be_prev_rx_frags; | ||
| 130 | u32 be_rx_fps; /* Rx frags per second */ | ||
| 131 | }; | ||
| 132 | |||
| 133 | struct be_stats_obj { | ||
| 134 | struct be_drvr_stats drvr_stats; | ||
| 135 | struct net_device_stats net_stats; | ||
| 136 | struct be_dma_mem cmd; | ||
| 137 | }; | ||
| 138 | |||
| 139 | struct be_eq_obj { | ||
| 140 | struct be_queue_info q; | ||
| 141 | char desc[32]; | ||
| 142 | |||
| 143 | /* Adaptive interrupt coalescing (AIC) info */ | ||
| 144 | bool enable_aic; | ||
| 145 | u16 min_eqd; /* in usecs */ | ||
| 146 | u16 max_eqd; /* in usecs */ | ||
| 147 | u16 cur_eqd; /* in usecs */ | ||
| 148 | |||
| 149 | struct napi_struct napi; | ||
| 150 | }; | ||
| 151 | |||
| 152 | struct be_tx_obj { | ||
| 153 | struct be_queue_info q; | ||
| 154 | struct be_queue_info cq; | ||
| 155 | /* Remember the skbs that were transmitted */ | ||
| 156 | struct sk_buff *sent_skb_list[TX_Q_LEN]; | ||
| 157 | }; | ||
| 158 | |||
| 159 | /* Struct to remember the pages posted for rx frags */ | ||
| 160 | struct be_rx_page_info { | ||
| 161 | struct page *page; | ||
| 162 | dma_addr_t bus; | ||
| 163 | u16 page_offset; | ||
| 164 | bool last_page_user; | ||
| 165 | }; | ||
| 166 | |||
| 167 | struct be_rx_obj { | ||
| 168 | struct be_queue_info q; | ||
| 169 | struct be_queue_info cq; | ||
| 170 | struct be_rx_page_info page_info_tbl[RX_Q_LEN]; | ||
| 171 | struct net_lro_mgr lro_mgr; | ||
| 172 | struct net_lro_desc lro_desc[BE_MAX_LRO_DESCRIPTORS]; | ||
| 173 | }; | ||
| 174 | |||
| 175 | #define BE_NUM_MSIX_VECTORS 2 /* 1 each for Tx and Rx */ | ||
| 176 | struct be_adapter { | ||
| 177 | struct pci_dev *pdev; | ||
| 178 | struct net_device *netdev; | ||
| 179 | |||
| 180 | /* Mbox, pci config, csr address information */ | ||
| 181 | struct be_ctrl_info ctrl; | ||
| 182 | |||
| 183 | struct msix_entry msix_entries[BE_NUM_MSIX_VECTORS]; | ||
| 184 | bool msix_enabled; | ||
| 185 | bool isr_registered; | ||
| 186 | |||
| 187 | /* TX Rings */ | ||
| 188 | struct be_eq_obj tx_eq; | ||
| 189 | struct be_tx_obj tx_obj; | ||
| 190 | |||
| 191 | u32 cache_line_break[8]; | ||
| 192 | |||
| 193 | /* Rx rings */ | ||
| 194 | struct be_eq_obj rx_eq; | ||
| 195 | struct be_rx_obj rx_obj; | ||
| 196 | u32 big_page_size; /* Compounded page size shared by rx wrbs */ | ||
| 197 | bool rx_post_starved; /* Zero rx frags have been posted to BE */ | ||
| 198 | |||
| 199 | struct vlan_group *vlan_grp; | ||
| 200 | u16 num_vlans; | ||
| 201 | u8 vlan_tag[VLAN_GROUP_ARRAY_LEN]; | ||
| 202 | |||
| 203 | struct be_stats_obj stats; | ||
| 204 | /* Work queue used to perform periodic tasks like getting statistics */ | ||
| 205 | struct delayed_work work; | ||
| 206 | |||
| 207 | /* Ethtool knobs and info */ | ||
| 208 | bool rx_csum; /* BE card must perform rx-checksumming */ | ||
| 209 | u32 max_rx_coal; | ||
| 210 | char fw_ver[FW_VER_LEN]; | ||
| 211 | u32 if_handle; /* Used to configure filtering */ | ||
| 212 | u32 pmac_id; /* MAC addr handle used by BE card */ | ||
| 213 | |||
| 214 | struct be_link_info link; | ||
| 215 | u32 port_num; | ||
| 216 | }; | ||
| 217 | |||
| 218 | extern struct ethtool_ops be_ethtool_ops; | ||
| 219 | |||
| 220 | #define drvr_stats(adapter) (&adapter->stats.drvr_stats) | ||
| 221 | |||
| 222 | #define BE_SET_NETDEV_OPS(netdev, ops) (netdev->netdev_ops = ops) | ||
| 223 | |||
| 224 | static inline u32 MODULO(u16 val, u16 limit) | ||
| 225 | { | ||
| 226 | BUG_ON(limit & (limit - 1)); | ||
| 227 | return val & (limit - 1); | ||
| 228 | } | ||
| 229 | |||
| 230 | static inline void index_adv(u16 *index, u16 val, u16 limit) | ||
| 231 | { | ||
| 232 | *index = MODULO((*index + val), limit); | ||
| 233 | } | ||
| 234 | |||
| 235 | static inline void index_inc(u16 *index, u16 limit) | ||
| 236 | { | ||
| 237 | *index = MODULO((*index + 1), limit); | ||
| 238 | } | ||
| 239 | |||
| 240 | #define PAGE_SHIFT_4K 12 | ||
| 241 | #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) | ||
| 242 | |||
| 243 | /* Returns number of pages spanned by the data starting at the given addr */ | ||
| 244 | #define PAGES_4K_SPANNED(_address, size) \ | ||
| 245 | ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ | ||
| 246 | (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) | ||
| 247 | |||
| 248 | /* Byte offset into the page corresponding to given address */ | ||
| 249 | #define OFFSET_IN_PAGE(addr) \ | ||
| 250 | ((size_t)(addr) & (PAGE_SIZE_4K-1)) | ||
| 251 | |||
| 252 | /* Returns bit offset within a DWORD of a bitfield */ | ||
| 253 | #define AMAP_BIT_OFFSET(_struct, field) \ | ||
| 254 | (((size_t)&(((_struct *)0)->field))%32) | ||
| 255 | |||
| 256 | /* Returns the bit mask of the field that is NOT shifted into location. */ | ||
| 257 | static inline u32 amap_mask(u32 bitsize) | ||
| 258 | { | ||
| 259 | return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1); | ||
| 260 | } | ||
| 261 | |||
| 262 | static inline void | ||
| 263 | amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) | ||
| 264 | { | ||
| 265 | u32 *dw = (u32 *) ptr + dw_offset; | ||
| 266 | *dw &= ~(mask << offset); | ||
| 267 | *dw |= (mask & value) << offset; | ||
| 268 | } | ||
| 269 | |||
| 270 | #define AMAP_SET_BITS(_struct, field, ptr, val) \ | ||
| 271 | amap_set(ptr, \ | ||
| 272 | offsetof(_struct, field)/32, \ | ||
| 273 | amap_mask(sizeof(((_struct *)0)->field)), \ | ||
| 274 | AMAP_BIT_OFFSET(_struct, field), \ | ||
| 275 | val) | ||
| 276 | |||
| 277 | static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) | ||
| 278 | { | ||
| 279 | u32 *dw = (u32 *) ptr; | ||
| 280 | return mask & (*(dw + dw_offset) >> offset); | ||
| 281 | } | ||
| 282 | |||
| 283 | #define AMAP_GET_BITS(_struct, field, ptr) \ | ||
| 284 | amap_get(ptr, \ | ||
| 285 | offsetof(_struct, field)/32, \ | ||
| 286 | amap_mask(sizeof(((_struct *)0)->field)), \ | ||
| 287 | AMAP_BIT_OFFSET(_struct, field)) | ||
| 288 | |||
| 289 | #define be_dws_cpu_to_le(wrb, len) swap_dws(wrb, len) | ||
| 290 | #define be_dws_le_to_cpu(wrb, len) swap_dws(wrb, len) | ||
| 291 | static inline void swap_dws(void *wrb, int len) | ||
| 292 | { | ||
| 293 | #ifdef __BIG_ENDIAN | ||
| 294 | u32 *dw = wrb; | ||
| 295 | BUG_ON(len % 4); | ||
| 296 | do { | ||
| 297 | *dw = cpu_to_le32(*dw); | ||
| 298 | dw++; | ||
| 299 | len -= 4; | ||
| 300 | } while (len); | ||
| 301 | #endif /* __BIG_ENDIAN */ | ||
| 302 | } | ||
| 303 | |||
| 304 | static inline u8 is_tcp_pkt(struct sk_buff *skb) | ||
| 305 | { | ||
| 306 | u8 val = 0; | ||
| 307 | |||
| 308 | if (ip_hdr(skb)->version == 4) | ||
| 309 | val = (ip_hdr(skb)->protocol == IPPROTO_TCP); | ||
| 310 | else if (ip_hdr(skb)->version == 6) | ||
| 311 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP); | ||
| 312 | |||
| 313 | return val; | ||
| 314 | } | ||
| 315 | |||
| 316 | static inline u8 is_udp_pkt(struct sk_buff *skb) | ||
| 317 | { | ||
| 318 | u8 val = 0; | ||
| 319 | |||
| 320 | if (ip_hdr(skb)->version == 4) | ||
| 321 | val = (ip_hdr(skb)->protocol == IPPROTO_UDP); | ||
| 322 | else if (ip_hdr(skb)->version == 6) | ||
| 323 | val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP); | ||
| 324 | |||
| 325 | return val; | ||
| 326 | } | ||
| 327 | |||
| 328 | #endif /* BE_H */ | ||
diff --git a/drivers/net/benet/be_cmds.c b/drivers/net/benet/be_cmds.c new file mode 100644 index 000000000000..d444aed962bc --- /dev/null +++ b/drivers/net/benet/be_cmds.c | |||
| @@ -0,0 +1,861 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2009 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include "be.h" | ||
| 19 | |||
| 20 | static int be_mbox_db_ready_wait(void __iomem *db) | ||
| 21 | { | ||
| 22 | int cnt = 0, wait = 5; | ||
| 23 | u32 ready; | ||
| 24 | |||
| 25 | do { | ||
| 26 | ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK; | ||
| 27 | if (ready) | ||
| 28 | break; | ||
| 29 | |||
| 30 | if (cnt > 200000) { | ||
| 31 | printk(KERN_WARNING DRV_NAME | ||
| 32 | ": mbox_db poll timed out\n"); | ||
| 33 | return -1; | ||
| 34 | } | ||
| 35 | |||
| 36 | if (cnt > 50) | ||
| 37 | wait = 200; | ||
| 38 | cnt += wait; | ||
| 39 | udelay(wait); | ||
| 40 | } while (true); | ||
| 41 | |||
| 42 | return 0; | ||
| 43 | } | ||
| 44 | |||
| 45 | /* | ||
| 46 | * Insert the mailbox address into the doorbell in two steps | ||
| 47 | */ | ||
| 48 | static int be_mbox_db_ring(struct be_ctrl_info *ctrl) | ||
| 49 | { | ||
| 50 | int status; | ||
| 51 | u16 compl_status, extd_status; | ||
| 52 | u32 val = 0; | ||
| 53 | void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET; | ||
| 54 | struct be_dma_mem *mbox_mem = &ctrl->mbox_mem; | ||
| 55 | struct be_mcc_mailbox *mbox = mbox_mem->va; | ||
| 56 | struct be_mcc_cq_entry *cqe = &mbox->cqe; | ||
| 57 | |||
| 58 | memset(cqe, 0, sizeof(*cqe)); | ||
| 59 | |||
| 60 | val &= ~MPU_MAILBOX_DB_RDY_MASK; | ||
| 61 | val |= MPU_MAILBOX_DB_HI_MASK; | ||
| 62 | /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */ | ||
| 63 | val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2; | ||
| 64 | iowrite32(val, db); | ||
| 65 | |||
| 66 | /* wait for ready to be set */ | ||
| 67 | status = be_mbox_db_ready_wait(db); | ||
| 68 | if (status != 0) | ||
| 69 | return status; | ||
| 70 | |||
| 71 | val = 0; | ||
| 72 | val &= ~MPU_MAILBOX_DB_RDY_MASK; | ||
| 73 | val &= ~MPU_MAILBOX_DB_HI_MASK; | ||
| 74 | /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */ | ||
| 75 | val |= (u32)(mbox_mem->dma >> 4) << 2; | ||
| 76 | iowrite32(val, db); | ||
| 77 | |||
| 78 | status = be_mbox_db_ready_wait(db); | ||
| 79 | if (status != 0) | ||
| 80 | return status; | ||
| 81 | |||
| 82 | /* compl entry has been made now */ | ||
| 83 | be_dws_le_to_cpu(cqe, sizeof(*cqe)); | ||
| 84 | if (!(cqe->flags & CQE_FLAGS_VALID_MASK)) { | ||
| 85 | printk(KERN_WARNING DRV_NAME ": ERROR invalid mbox compl\n"); | ||
| 86 | return -1; | ||
| 87 | } | ||
| 88 | |||
| 89 | compl_status = (cqe->status >> CQE_STATUS_COMPL_SHIFT) & | ||
| 90 | CQE_STATUS_COMPL_MASK; | ||
| 91 | if (compl_status != MCC_STATUS_SUCCESS) { | ||
| 92 | extd_status = (cqe->status >> CQE_STATUS_EXTD_SHIFT) & | ||
| 93 | CQE_STATUS_EXTD_MASK; | ||
| 94 | printk(KERN_WARNING DRV_NAME | ||
| 95 | ": ERROR in cmd compl. status(compl/extd)=%d/%d\n", | ||
| 96 | compl_status, extd_status); | ||
| 97 | } | ||
| 98 | |||
| 99 | return compl_status; | ||
| 100 | } | ||
| 101 | |||
| 102 | static int be_POST_stage_get(struct be_ctrl_info *ctrl, u16 *stage) | ||
| 103 | { | ||
| 104 | u32 sem = ioread32(ctrl->csr + MPU_EP_SEMAPHORE_OFFSET); | ||
| 105 | |||
| 106 | *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK; | ||
| 107 | if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK) | ||
| 108 | return -1; | ||
| 109 | else | ||
| 110 | return 0; | ||
| 111 | } | ||
| 112 | |||
| 113 | static int be_POST_stage_poll(struct be_ctrl_info *ctrl, u16 poll_stage) | ||
| 114 | { | ||
| 115 | u16 stage, cnt, error; | ||
| 116 | for (cnt = 0; cnt < 5000; cnt++) { | ||
| 117 | error = be_POST_stage_get(ctrl, &stage); | ||
| 118 | if (error) | ||
| 119 | return -1; | ||
| 120 | |||
| 121 | if (stage == poll_stage) | ||
| 122 | break; | ||
| 123 | udelay(1000); | ||
| 124 | } | ||
| 125 | if (stage != poll_stage) | ||
| 126 | return -1; | ||
| 127 | return 0; | ||
| 128 | } | ||
| 129 | |||
| 130 | |||
| 131 | int be_cmd_POST(struct be_ctrl_info *ctrl) | ||
| 132 | { | ||
| 133 | u16 stage, error; | ||
| 134 | |||
| 135 | error = be_POST_stage_get(ctrl, &stage); | ||
| 136 | if (error) | ||
| 137 | goto err; | ||
| 138 | |||
| 139 | if (stage == POST_STAGE_ARMFW_RDY) | ||
| 140 | return 0; | ||
| 141 | |||
| 142 | if (stage != POST_STAGE_AWAITING_HOST_RDY) | ||
| 143 | goto err; | ||
| 144 | |||
| 145 | /* On awaiting host rdy, reset and again poll on awaiting host rdy */ | ||
| 146 | iowrite32(POST_STAGE_BE_RESET, ctrl->csr + MPU_EP_SEMAPHORE_OFFSET); | ||
| 147 | error = be_POST_stage_poll(ctrl, POST_STAGE_AWAITING_HOST_RDY); | ||
| 148 | if (error) | ||
| 149 | goto err; | ||
| 150 | |||
| 151 | /* Now kickoff POST and poll on armfw ready */ | ||
| 152 | iowrite32(POST_STAGE_HOST_RDY, ctrl->csr + MPU_EP_SEMAPHORE_OFFSET); | ||
| 153 | error = be_POST_stage_poll(ctrl, POST_STAGE_ARMFW_RDY); | ||
| 154 | if (error) | ||
| 155 | goto err; | ||
| 156 | |||
| 157 | return 0; | ||
| 158 | err: | ||
| 159 | printk(KERN_WARNING DRV_NAME ": ERROR, stage=%d\n", stage); | ||
| 160 | return -1; | ||
| 161 | } | ||
| 162 | |||
| 163 | static inline void *embedded_payload(struct be_mcc_wrb *wrb) | ||
| 164 | { | ||
| 165 | return wrb->payload.embedded_payload; | ||
| 166 | } | ||
| 167 | |||
| 168 | static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb) | ||
| 169 | { | ||
| 170 | return &wrb->payload.sgl[0]; | ||
| 171 | } | ||
| 172 | |||
| 173 | /* Don't touch the hdr after it's prepared */ | ||
| 174 | static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len, | ||
| 175 | bool embedded, u8 sge_cnt) | ||
| 176 | { | ||
| 177 | if (embedded) | ||
| 178 | wrb->embedded |= MCC_WRB_EMBEDDED_MASK; | ||
| 179 | else | ||
| 180 | wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) << | ||
| 181 | MCC_WRB_SGE_CNT_SHIFT; | ||
| 182 | wrb->payload_length = payload_len; | ||
| 183 | be_dws_cpu_to_le(wrb, 20); | ||
| 184 | } | ||
| 185 | |||
| 186 | /* Don't touch the hdr after it's prepared */ | ||
| 187 | static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, | ||
| 188 | u8 subsystem, u8 opcode, int cmd_len) | ||
| 189 | { | ||
| 190 | req_hdr->opcode = opcode; | ||
| 191 | req_hdr->subsystem = subsystem; | ||
| 192 | req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); | ||
| 193 | } | ||
| 194 | |||
| 195 | static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, | ||
| 196 | struct be_dma_mem *mem) | ||
| 197 | { | ||
| 198 | int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages); | ||
| 199 | u64 dma = (u64)mem->dma; | ||
| 200 | |||
| 201 | for (i = 0; i < buf_pages; i++) { | ||
| 202 | pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF); | ||
| 203 | pages[i].hi = cpu_to_le32(upper_32_bits(dma)); | ||
| 204 | dma += PAGE_SIZE_4K; | ||
| 205 | } | ||
| 206 | } | ||
| 207 | |||
| 208 | /* Converts interrupt delay in microseconds to multiplier value */ | ||
| 209 | static u32 eq_delay_to_mult(u32 usec_delay) | ||
| 210 | { | ||
| 211 | #define MAX_INTR_RATE 651042 | ||
| 212 | const u32 round = 10; | ||
| 213 | u32 multiplier; | ||
| 214 | |||
| 215 | if (usec_delay == 0) | ||
| 216 | multiplier = 0; | ||
| 217 | else { | ||
| 218 | u32 interrupt_rate = 1000000 / usec_delay; | ||
| 219 | /* Max delay, corresponding to the lowest interrupt rate */ | ||
| 220 | if (interrupt_rate == 0) | ||
| 221 | multiplier = 1023; | ||
| 222 | else { | ||
| 223 | multiplier = (MAX_INTR_RATE - interrupt_rate) * round; | ||
| 224 | multiplier /= interrupt_rate; | ||
| 225 | /* Round the multiplier to the closest value.*/ | ||
| 226 | multiplier = (multiplier + round/2) / round; | ||
| 227 | multiplier = min(multiplier, (u32)1023); | ||
| 228 | } | ||
| 229 | } | ||
| 230 | return multiplier; | ||
| 231 | } | ||
| 232 | |||
| 233 | static inline struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem) | ||
| 234 | { | ||
| 235 | return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb; | ||
| 236 | } | ||
| 237 | |||
| 238 | int be_cmd_eq_create(struct be_ctrl_info *ctrl, | ||
| 239 | struct be_queue_info *eq, int eq_delay) | ||
| 240 | { | ||
| 241 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 242 | struct be_cmd_req_eq_create *req = embedded_payload(wrb); | ||
| 243 | struct be_cmd_resp_eq_create *resp = embedded_payload(wrb); | ||
| 244 | struct be_dma_mem *q_mem = &eq->dma_mem; | ||
| 245 | int status; | ||
| 246 | |||
| 247 | spin_lock(&ctrl->cmd_lock); | ||
| 248 | memset(wrb, 0, sizeof(*wrb)); | ||
| 249 | |||
| 250 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 251 | |||
| 252 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 253 | OPCODE_COMMON_EQ_CREATE, sizeof(*req)); | ||
| 254 | |||
| 255 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | ||
| 256 | |||
| 257 | AMAP_SET_BITS(struct amap_eq_context, func, req->context, | ||
| 258 | ctrl->pci_func); | ||
| 259 | AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1); | ||
| 260 | /* 4byte eqe*/ | ||
| 261 | AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0); | ||
| 262 | AMAP_SET_BITS(struct amap_eq_context, count, req->context, | ||
| 263 | __ilog2_u32(eq->len/256)); | ||
| 264 | AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context, | ||
| 265 | eq_delay_to_mult(eq_delay)); | ||
| 266 | be_dws_cpu_to_le(req->context, sizeof(req->context)); | ||
| 267 | |||
| 268 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | ||
| 269 | |||
| 270 | status = be_mbox_db_ring(ctrl); | ||
| 271 | if (!status) { | ||
| 272 | eq->id = le16_to_cpu(resp->eq_id); | ||
| 273 | eq->created = true; | ||
| 274 | } | ||
| 275 | spin_unlock(&ctrl->cmd_lock); | ||
| 276 | return status; | ||
| 277 | } | ||
| 278 | |||
| 279 | int be_cmd_mac_addr_query(struct be_ctrl_info *ctrl, u8 *mac_addr, | ||
| 280 | u8 type, bool permanent, u32 if_handle) | ||
| 281 | { | ||
| 282 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 283 | struct be_cmd_req_mac_query *req = embedded_payload(wrb); | ||
| 284 | struct be_cmd_resp_mac_query *resp = embedded_payload(wrb); | ||
| 285 | int status; | ||
| 286 | |||
| 287 | spin_lock(&ctrl->cmd_lock); | ||
| 288 | memset(wrb, 0, sizeof(*wrb)); | ||
| 289 | |||
| 290 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 291 | |||
| 292 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 293 | OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req)); | ||
| 294 | |||
| 295 | req->type = type; | ||
| 296 | if (permanent) { | ||
| 297 | req->permanent = 1; | ||
| 298 | } else { | ||
| 299 | req->if_id = cpu_to_le16((u16)if_handle); | ||
| 300 | req->permanent = 0; | ||
| 301 | } | ||
| 302 | |||
| 303 | status = be_mbox_db_ring(ctrl); | ||
| 304 | if (!status) | ||
| 305 | memcpy(mac_addr, resp->mac.addr, ETH_ALEN); | ||
| 306 | |||
| 307 | spin_unlock(&ctrl->cmd_lock); | ||
| 308 | return status; | ||
| 309 | } | ||
| 310 | |||
| 311 | int be_cmd_pmac_add(struct be_ctrl_info *ctrl, u8 *mac_addr, | ||
| 312 | u32 if_id, u32 *pmac_id) | ||
| 313 | { | ||
| 314 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 315 | struct be_cmd_req_pmac_add *req = embedded_payload(wrb); | ||
| 316 | int status; | ||
| 317 | |||
| 318 | spin_lock(&ctrl->cmd_lock); | ||
| 319 | memset(wrb, 0, sizeof(*wrb)); | ||
| 320 | |||
| 321 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 322 | |||
| 323 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 324 | OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req)); | ||
| 325 | |||
| 326 | req->if_id = cpu_to_le32(if_id); | ||
| 327 | memcpy(req->mac_address, mac_addr, ETH_ALEN); | ||
| 328 | |||
| 329 | status = be_mbox_db_ring(ctrl); | ||
| 330 | if (!status) { | ||
| 331 | struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb); | ||
| 332 | *pmac_id = le32_to_cpu(resp->pmac_id); | ||
| 333 | } | ||
| 334 | |||
| 335 | spin_unlock(&ctrl->cmd_lock); | ||
| 336 | return status; | ||
| 337 | } | ||
| 338 | |||
| 339 | int be_cmd_pmac_del(struct be_ctrl_info *ctrl, u32 if_id, u32 pmac_id) | ||
| 340 | { | ||
| 341 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 342 | struct be_cmd_req_pmac_del *req = embedded_payload(wrb); | ||
| 343 | int status; | ||
| 344 | |||
| 345 | spin_lock(&ctrl->cmd_lock); | ||
| 346 | memset(wrb, 0, sizeof(*wrb)); | ||
| 347 | |||
| 348 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 349 | |||
| 350 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 351 | OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req)); | ||
| 352 | |||
| 353 | req->if_id = cpu_to_le32(if_id); | ||
| 354 | req->pmac_id = cpu_to_le32(pmac_id); | ||
| 355 | |||
| 356 | status = be_mbox_db_ring(ctrl); | ||
| 357 | spin_unlock(&ctrl->cmd_lock); | ||
| 358 | |||
| 359 | return status; | ||
| 360 | } | ||
| 361 | |||
| 362 | int be_cmd_cq_create(struct be_ctrl_info *ctrl, | ||
| 363 | struct be_queue_info *cq, struct be_queue_info *eq, | ||
| 364 | bool sol_evts, bool no_delay, int coalesce_wm) | ||
| 365 | { | ||
| 366 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 367 | struct be_cmd_req_cq_create *req = embedded_payload(wrb); | ||
| 368 | struct be_cmd_resp_cq_create *resp = embedded_payload(wrb); | ||
| 369 | struct be_dma_mem *q_mem = &cq->dma_mem; | ||
| 370 | void *ctxt = &req->context; | ||
| 371 | int status; | ||
| 372 | |||
| 373 | spin_lock(&ctrl->cmd_lock); | ||
| 374 | memset(wrb, 0, sizeof(*wrb)); | ||
| 375 | |||
| 376 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 377 | |||
| 378 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 379 | OPCODE_COMMON_CQ_CREATE, sizeof(*req)); | ||
| 380 | |||
| 381 | req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); | ||
| 382 | |||
| 383 | AMAP_SET_BITS(struct amap_cq_context, coalescwm, ctxt, coalesce_wm); | ||
| 384 | AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay); | ||
| 385 | AMAP_SET_BITS(struct amap_cq_context, count, ctxt, | ||
| 386 | __ilog2_u32(cq->len/256)); | ||
| 387 | AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1); | ||
| 388 | AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts); | ||
| 389 | AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1); | ||
| 390 | AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id); | ||
| 391 | AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 0); | ||
| 392 | AMAP_SET_BITS(struct amap_cq_context, func, ctxt, ctrl->pci_func); | ||
| 393 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | ||
| 394 | |||
| 395 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | ||
| 396 | |||
| 397 | status = be_mbox_db_ring(ctrl); | ||
| 398 | if (!status) { | ||
| 399 | cq->id = le16_to_cpu(resp->cq_id); | ||
| 400 | cq->created = true; | ||
| 401 | } | ||
| 402 | spin_unlock(&ctrl->cmd_lock); | ||
| 403 | |||
| 404 | return status; | ||
| 405 | } | ||
| 406 | |||
| 407 | int be_cmd_txq_create(struct be_ctrl_info *ctrl, | ||
| 408 | struct be_queue_info *txq, | ||
| 409 | struct be_queue_info *cq) | ||
| 410 | { | ||
| 411 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 412 | struct be_cmd_req_eth_tx_create *req = embedded_payload(wrb); | ||
| 413 | struct be_dma_mem *q_mem = &txq->dma_mem; | ||
| 414 | void *ctxt = &req->context; | ||
| 415 | int status; | ||
| 416 | u32 len_encoded; | ||
| 417 | |||
| 418 | spin_lock(&ctrl->cmd_lock); | ||
| 419 | memset(wrb, 0, sizeof(*wrb)); | ||
| 420 | |||
| 421 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 422 | |||
| 423 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE, | ||
| 424 | sizeof(*req)); | ||
| 425 | |||
| 426 | req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size); | ||
| 427 | req->ulp_num = BE_ULP1_NUM; | ||
| 428 | req->type = BE_ETH_TX_RING_TYPE_STANDARD; | ||
| 429 | |||
| 430 | len_encoded = fls(txq->len); /* log2(len) + 1 */ | ||
| 431 | if (len_encoded == 16) | ||
| 432 | len_encoded = 0; | ||
| 433 | AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt, len_encoded); | ||
| 434 | AMAP_SET_BITS(struct amap_tx_context, pci_func_id, ctxt, | ||
| 435 | ctrl->pci_func); | ||
| 436 | AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1); | ||
| 437 | AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id); | ||
| 438 | |||
| 439 | be_dws_cpu_to_le(ctxt, sizeof(req->context)); | ||
| 440 | |||
| 441 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | ||
| 442 | |||
| 443 | status = be_mbox_db_ring(ctrl); | ||
| 444 | if (!status) { | ||
| 445 | struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb); | ||
| 446 | txq->id = le16_to_cpu(resp->cid); | ||
| 447 | txq->created = true; | ||
| 448 | } | ||
| 449 | spin_unlock(&ctrl->cmd_lock); | ||
| 450 | |||
| 451 | return status; | ||
| 452 | } | ||
| 453 | |||
| 454 | int be_cmd_rxq_create(struct be_ctrl_info *ctrl, | ||
| 455 | struct be_queue_info *rxq, u16 cq_id, u16 frag_size, | ||
| 456 | u16 max_frame_size, u32 if_id, u32 rss) | ||
| 457 | { | ||
| 458 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 459 | struct be_cmd_req_eth_rx_create *req = embedded_payload(wrb); | ||
| 460 | struct be_dma_mem *q_mem = &rxq->dma_mem; | ||
| 461 | int status; | ||
| 462 | |||
| 463 | spin_lock(&ctrl->cmd_lock); | ||
| 464 | memset(wrb, 0, sizeof(*wrb)); | ||
| 465 | |||
| 466 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 467 | |||
| 468 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE, | ||
| 469 | sizeof(*req)); | ||
| 470 | |||
| 471 | req->cq_id = cpu_to_le16(cq_id); | ||
| 472 | req->frag_size = fls(frag_size) - 1; | ||
| 473 | req->num_pages = 2; | ||
| 474 | be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); | ||
| 475 | req->interface_id = cpu_to_le32(if_id); | ||
| 476 | req->max_frame_size = cpu_to_le16(max_frame_size); | ||
| 477 | req->rss_queue = cpu_to_le32(rss); | ||
| 478 | |||
| 479 | status = be_mbox_db_ring(ctrl); | ||
| 480 | if (!status) { | ||
| 481 | struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb); | ||
| 482 | rxq->id = le16_to_cpu(resp->id); | ||
| 483 | rxq->created = true; | ||
| 484 | } | ||
| 485 | spin_unlock(&ctrl->cmd_lock); | ||
| 486 | |||
| 487 | return status; | ||
| 488 | } | ||
| 489 | |||
| 490 | /* Generic destroyer function for all types of queues */ | ||
| 491 | int be_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, | ||
| 492 | int queue_type) | ||
| 493 | { | ||
| 494 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 495 | struct be_cmd_req_q_destroy *req = embedded_payload(wrb); | ||
| 496 | u8 subsys = 0, opcode = 0; | ||
| 497 | int status; | ||
| 498 | |||
| 499 | spin_lock(&ctrl->cmd_lock); | ||
| 500 | |||
| 501 | memset(wrb, 0, sizeof(*wrb)); | ||
| 502 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 503 | |||
| 504 | switch (queue_type) { | ||
| 505 | case QTYPE_EQ: | ||
| 506 | subsys = CMD_SUBSYSTEM_COMMON; | ||
| 507 | opcode = OPCODE_COMMON_EQ_DESTROY; | ||
| 508 | break; | ||
| 509 | case QTYPE_CQ: | ||
| 510 | subsys = CMD_SUBSYSTEM_COMMON; | ||
| 511 | opcode = OPCODE_COMMON_CQ_DESTROY; | ||
| 512 | break; | ||
| 513 | case QTYPE_TXQ: | ||
| 514 | subsys = CMD_SUBSYSTEM_ETH; | ||
| 515 | opcode = OPCODE_ETH_TX_DESTROY; | ||
| 516 | break; | ||
| 517 | case QTYPE_RXQ: | ||
| 518 | subsys = CMD_SUBSYSTEM_ETH; | ||
| 519 | opcode = OPCODE_ETH_RX_DESTROY; | ||
| 520 | break; | ||
| 521 | default: | ||
| 522 | printk(KERN_WARNING DRV_NAME ":bad Q type in Q destroy cmd\n"); | ||
| 523 | status = -1; | ||
| 524 | goto err; | ||
| 525 | } | ||
| 526 | be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req)); | ||
| 527 | req->id = cpu_to_le16(q->id); | ||
| 528 | |||
| 529 | status = be_mbox_db_ring(ctrl); | ||
| 530 | err: | ||
| 531 | spin_unlock(&ctrl->cmd_lock); | ||
| 532 | |||
| 533 | return status; | ||
| 534 | } | ||
| 535 | |||
| 536 | /* Create an rx filtering policy configuration on an i/f */ | ||
| 537 | int be_cmd_if_create(struct be_ctrl_info *ctrl, u32 flags, u8 *mac, | ||
| 538 | bool pmac_invalid, u32 *if_handle, u32 *pmac_id) | ||
| 539 | { | ||
| 540 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 541 | struct be_cmd_req_if_create *req = embedded_payload(wrb); | ||
| 542 | int status; | ||
| 543 | |||
| 544 | spin_lock(&ctrl->cmd_lock); | ||
| 545 | memset(wrb, 0, sizeof(*wrb)); | ||
| 546 | |||
| 547 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 548 | |||
| 549 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 550 | OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req)); | ||
| 551 | |||
| 552 | req->capability_flags = cpu_to_le32(flags); | ||
| 553 | req->enable_flags = cpu_to_le32(flags); | ||
| 554 | if (!pmac_invalid) | ||
| 555 | memcpy(req->mac_addr, mac, ETH_ALEN); | ||
| 556 | |||
| 557 | status = be_mbox_db_ring(ctrl); | ||
| 558 | if (!status) { | ||
| 559 | struct be_cmd_resp_if_create *resp = embedded_payload(wrb); | ||
| 560 | *if_handle = le32_to_cpu(resp->interface_id); | ||
| 561 | if (!pmac_invalid) | ||
| 562 | *pmac_id = le32_to_cpu(resp->pmac_id); | ||
| 563 | } | ||
| 564 | |||
| 565 | spin_unlock(&ctrl->cmd_lock); | ||
| 566 | return status; | ||
| 567 | } | ||
| 568 | |||
| 569 | int be_cmd_if_destroy(struct be_ctrl_info *ctrl, u32 interface_id) | ||
| 570 | { | ||
| 571 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 572 | struct be_cmd_req_if_destroy *req = embedded_payload(wrb); | ||
| 573 | int status; | ||
| 574 | |||
| 575 | spin_lock(&ctrl->cmd_lock); | ||
| 576 | memset(wrb, 0, sizeof(*wrb)); | ||
| 577 | |||
| 578 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 579 | |||
| 580 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 581 | OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req)); | ||
| 582 | |||
| 583 | req->interface_id = cpu_to_le32(interface_id); | ||
| 584 | status = be_mbox_db_ring(ctrl); | ||
| 585 | |||
| 586 | spin_unlock(&ctrl->cmd_lock); | ||
| 587 | |||
| 588 | return status; | ||
| 589 | } | ||
| 590 | |||
| 591 | /* Get stats is a non embedded command: the request is not embedded inside | ||
| 592 | * WRB but is a separate dma memory block | ||
| 593 | */ | ||
| 594 | int be_cmd_get_stats(struct be_ctrl_info *ctrl, struct be_dma_mem *nonemb_cmd) | ||
| 595 | { | ||
| 596 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 597 | struct be_cmd_req_get_stats *req = nonemb_cmd->va; | ||
| 598 | struct be_sge *sge = nonembedded_sgl(wrb); | ||
| 599 | int status; | ||
| 600 | |||
| 601 | spin_lock(&ctrl->cmd_lock); | ||
| 602 | memset(wrb, 0, sizeof(*wrb)); | ||
| 603 | |||
| 604 | memset(req, 0, sizeof(*req)); | ||
| 605 | |||
| 606 | be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1); | ||
| 607 | |||
| 608 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | ||
| 609 | OPCODE_ETH_GET_STATISTICS, sizeof(*req)); | ||
| 610 | sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma)); | ||
| 611 | sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF); | ||
| 612 | sge->len = cpu_to_le32(nonemb_cmd->size); | ||
| 613 | |||
| 614 | status = be_mbox_db_ring(ctrl); | ||
| 615 | if (!status) { | ||
| 616 | struct be_cmd_resp_get_stats *resp = nonemb_cmd->va; | ||
| 617 | be_dws_le_to_cpu(&resp->hw_stats, sizeof(resp->hw_stats)); | ||
| 618 | } | ||
| 619 | |||
| 620 | spin_unlock(&ctrl->cmd_lock); | ||
| 621 | return status; | ||
| 622 | } | ||
| 623 | |||
| 624 | int be_cmd_link_status_query(struct be_ctrl_info *ctrl, | ||
| 625 | struct be_link_info *link) | ||
| 626 | { | ||
| 627 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 628 | struct be_cmd_req_link_status *req = embedded_payload(wrb); | ||
| 629 | int status; | ||
| 630 | |||
| 631 | spin_lock(&ctrl->cmd_lock); | ||
| 632 | memset(wrb, 0, sizeof(*wrb)); | ||
| 633 | |||
| 634 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 635 | |||
| 636 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 637 | OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req)); | ||
| 638 | |||
| 639 | status = be_mbox_db_ring(ctrl); | ||
| 640 | if (!status) { | ||
| 641 | struct be_cmd_resp_link_status *resp = embedded_payload(wrb); | ||
| 642 | link->speed = resp->mac_speed; | ||
| 643 | link->duplex = resp->mac_duplex; | ||
| 644 | link->fault = resp->mac_fault; | ||
| 645 | } else { | ||
| 646 | link->speed = PHY_LINK_SPEED_ZERO; | ||
| 647 | } | ||
| 648 | |||
| 649 | spin_unlock(&ctrl->cmd_lock); | ||
| 650 | return status; | ||
| 651 | } | ||
| 652 | |||
| 653 | int be_cmd_get_fw_ver(struct be_ctrl_info *ctrl, char *fw_ver) | ||
| 654 | { | ||
| 655 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 656 | struct be_cmd_req_get_fw_version *req = embedded_payload(wrb); | ||
| 657 | int status; | ||
| 658 | |||
| 659 | spin_lock(&ctrl->cmd_lock); | ||
| 660 | memset(wrb, 0, sizeof(*wrb)); | ||
| 661 | |||
| 662 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 663 | |||
| 664 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 665 | OPCODE_COMMON_GET_FW_VERSION, sizeof(*req)); | ||
| 666 | |||
| 667 | status = be_mbox_db_ring(ctrl); | ||
| 668 | if (!status) { | ||
| 669 | struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); | ||
| 670 | strncpy(fw_ver, resp->firmware_version_string, FW_VER_LEN); | ||
| 671 | } | ||
| 672 | |||
| 673 | spin_unlock(&ctrl->cmd_lock); | ||
| 674 | return status; | ||
| 675 | } | ||
| 676 | |||
| 677 | /* set the EQ delay interval of an EQ to specified value */ | ||
| 678 | int be_cmd_modify_eqd(struct be_ctrl_info *ctrl, u32 eq_id, u32 eqd) | ||
| 679 | { | ||
| 680 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 681 | struct be_cmd_req_modify_eq_delay *req = embedded_payload(wrb); | ||
| 682 | int status; | ||
| 683 | |||
| 684 | spin_lock(&ctrl->cmd_lock); | ||
| 685 | memset(wrb, 0, sizeof(*wrb)); | ||
| 686 | |||
| 687 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 688 | |||
| 689 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 690 | OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req)); | ||
| 691 | |||
| 692 | req->num_eq = cpu_to_le32(1); | ||
| 693 | req->delay[0].eq_id = cpu_to_le32(eq_id); | ||
| 694 | req->delay[0].phase = 0; | ||
| 695 | req->delay[0].delay_multiplier = cpu_to_le32(eqd); | ||
| 696 | |||
| 697 | status = be_mbox_db_ring(ctrl); | ||
| 698 | |||
| 699 | spin_unlock(&ctrl->cmd_lock); | ||
| 700 | return status; | ||
| 701 | } | ||
| 702 | |||
| 703 | int be_cmd_vlan_config(struct be_ctrl_info *ctrl, u32 if_id, u16 *vtag_array, | ||
| 704 | u32 num, bool untagged, bool promiscuous) | ||
| 705 | { | ||
| 706 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 707 | struct be_cmd_req_vlan_config *req = embedded_payload(wrb); | ||
| 708 | int status; | ||
| 709 | |||
| 710 | spin_lock(&ctrl->cmd_lock); | ||
| 711 | memset(wrb, 0, sizeof(*wrb)); | ||
| 712 | |||
| 713 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 714 | |||
| 715 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 716 | OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req)); | ||
| 717 | |||
| 718 | req->interface_id = if_id; | ||
| 719 | req->promiscuous = promiscuous; | ||
| 720 | req->untagged = untagged; | ||
| 721 | req->num_vlan = num; | ||
| 722 | if (!promiscuous) { | ||
| 723 | memcpy(req->normal_vlan, vtag_array, | ||
| 724 | req->num_vlan * sizeof(vtag_array[0])); | ||
| 725 | } | ||
| 726 | |||
| 727 | status = be_mbox_db_ring(ctrl); | ||
| 728 | |||
| 729 | spin_unlock(&ctrl->cmd_lock); | ||
| 730 | return status; | ||
| 731 | } | ||
| 732 | |||
| 733 | int be_cmd_promiscuous_config(struct be_ctrl_info *ctrl, u8 port_num, bool en) | ||
| 734 | { | ||
| 735 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 736 | struct be_cmd_req_promiscuous_config *req = embedded_payload(wrb); | ||
| 737 | int status; | ||
| 738 | |||
| 739 | spin_lock(&ctrl->cmd_lock); | ||
| 740 | memset(wrb, 0, sizeof(*wrb)); | ||
| 741 | |||
| 742 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 743 | |||
| 744 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, | ||
| 745 | OPCODE_ETH_PROMISCUOUS, sizeof(*req)); | ||
| 746 | |||
| 747 | if (port_num) | ||
| 748 | req->port1_promiscuous = en; | ||
| 749 | else | ||
| 750 | req->port0_promiscuous = en; | ||
| 751 | |||
| 752 | status = be_mbox_db_ring(ctrl); | ||
| 753 | |||
| 754 | spin_unlock(&ctrl->cmd_lock); | ||
| 755 | return status; | ||
| 756 | } | ||
| 757 | |||
| 758 | int be_cmd_mcast_mac_set(struct be_ctrl_info *ctrl, u32 if_id, u8 *mac_table, | ||
| 759 | u32 num, bool promiscuous) | ||
| 760 | { | ||
| 761 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 762 | struct be_cmd_req_mcast_mac_config *req = embedded_payload(wrb); | ||
| 763 | int status; | ||
| 764 | |||
| 765 | spin_lock(&ctrl->cmd_lock); | ||
| 766 | memset(wrb, 0, sizeof(*wrb)); | ||
| 767 | |||
| 768 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 769 | |||
| 770 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 771 | OPCODE_COMMON_NTWK_MULTICAST_SET, sizeof(*req)); | ||
| 772 | |||
| 773 | req->interface_id = if_id; | ||
| 774 | req->promiscuous = promiscuous; | ||
| 775 | if (!promiscuous) { | ||
| 776 | req->num_mac = cpu_to_le16(num); | ||
| 777 | if (num) | ||
| 778 | memcpy(req->mac, mac_table, ETH_ALEN * num); | ||
| 779 | } | ||
| 780 | |||
| 781 | status = be_mbox_db_ring(ctrl); | ||
| 782 | |||
| 783 | spin_unlock(&ctrl->cmd_lock); | ||
| 784 | return status; | ||
| 785 | } | ||
| 786 | |||
| 787 | int be_cmd_set_flow_control(struct be_ctrl_info *ctrl, u32 tx_fc, u32 rx_fc) | ||
| 788 | { | ||
| 789 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 790 | struct be_cmd_req_set_flow_control *req = embedded_payload(wrb); | ||
| 791 | int status; | ||
| 792 | |||
| 793 | spin_lock(&ctrl->cmd_lock); | ||
| 794 | |||
| 795 | memset(wrb, 0, sizeof(*wrb)); | ||
| 796 | |||
| 797 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 798 | |||
| 799 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 800 | OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req)); | ||
| 801 | |||
| 802 | req->tx_flow_control = cpu_to_le16((u16)tx_fc); | ||
| 803 | req->rx_flow_control = cpu_to_le16((u16)rx_fc); | ||
| 804 | |||
| 805 | status = be_mbox_db_ring(ctrl); | ||
| 806 | |||
| 807 | spin_unlock(&ctrl->cmd_lock); | ||
| 808 | return status; | ||
| 809 | } | ||
| 810 | |||
| 811 | int be_cmd_get_flow_control(struct be_ctrl_info *ctrl, u32 *tx_fc, u32 *rx_fc) | ||
| 812 | { | ||
| 813 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 814 | struct be_cmd_req_get_flow_control *req = embedded_payload(wrb); | ||
| 815 | int status; | ||
| 816 | |||
| 817 | spin_lock(&ctrl->cmd_lock); | ||
| 818 | |||
| 819 | memset(wrb, 0, sizeof(*wrb)); | ||
| 820 | |||
| 821 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 822 | |||
| 823 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 824 | OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req)); | ||
| 825 | |||
| 826 | status = be_mbox_db_ring(ctrl); | ||
| 827 | if (!status) { | ||
| 828 | struct be_cmd_resp_get_flow_control *resp = | ||
| 829 | embedded_payload(wrb); | ||
| 830 | *tx_fc = le16_to_cpu(resp->tx_flow_control); | ||
| 831 | *rx_fc = le16_to_cpu(resp->rx_flow_control); | ||
| 832 | } | ||
| 833 | |||
| 834 | spin_unlock(&ctrl->cmd_lock); | ||
| 835 | return status; | ||
| 836 | } | ||
| 837 | |||
| 838 | int be_cmd_query_fw_cfg(struct be_ctrl_info *ctrl, u32 *port_num) | ||
| 839 | { | ||
| 840 | struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem); | ||
| 841 | struct be_cmd_req_query_fw_cfg *req = embedded_payload(wrb); | ||
| 842 | int status; | ||
| 843 | |||
| 844 | spin_lock(&ctrl->cmd_lock); | ||
| 845 | |||
| 846 | memset(wrb, 0, sizeof(*wrb)); | ||
| 847 | |||
| 848 | be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0); | ||
| 849 | |||
| 850 | be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, | ||
| 851 | OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req)); | ||
| 852 | |||
| 853 | status = be_mbox_db_ring(ctrl); | ||
| 854 | if (!status) { | ||
| 855 | struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb); | ||
| 856 | *port_num = le32_to_cpu(resp->phys_port); | ||
| 857 | } | ||
| 858 | |||
| 859 | spin_unlock(&ctrl->cmd_lock); | ||
| 860 | return status; | ||
| 861 | } | ||
diff --git a/drivers/net/benet/be_cmds.h b/drivers/net/benet/be_cmds.h new file mode 100644 index 000000000000..e499e2d5b8c3 --- /dev/null +++ b/drivers/net/benet/be_cmds.h | |||
| @@ -0,0 +1,688 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2009 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | |||
| 18 | /* | ||
| 19 | * The driver sends configuration and managements command requests to the | ||
| 20 | * firmware in the BE. These requests are communicated to the processor | ||
| 21 | * using Work Request Blocks (WRBs) submitted to the MCC-WRB ring or via one | ||
| 22 | * WRB inside a MAILBOX. | ||
| 23 | * The commands are serviced by the ARM processor in the BladeEngine's MPU. | ||
| 24 | */ | ||
| 25 | |||
| 26 | struct be_sge { | ||
| 27 | u32 pa_lo; | ||
| 28 | u32 pa_hi; | ||
| 29 | u32 len; | ||
| 30 | }; | ||
| 31 | |||
| 32 | #define MCC_WRB_EMBEDDED_MASK 1 /* bit 0 of dword 0*/ | ||
| 33 | #define MCC_WRB_SGE_CNT_SHIFT 3 /* bits 3 - 7 of dword 0 */ | ||
| 34 | #define MCC_WRB_SGE_CNT_MASK 0x1F /* bits 3 - 7 of dword 0 */ | ||
| 35 | struct be_mcc_wrb { | ||
| 36 | u32 embedded; /* dword 0 */ | ||
| 37 | u32 payload_length; /* dword 1 */ | ||
| 38 | u32 tag0; /* dword 2 */ | ||
| 39 | u32 tag1; /* dword 3 */ | ||
| 40 | u32 rsvd; /* dword 4 */ | ||
| 41 | union { | ||
| 42 | u8 embedded_payload[236]; /* used by embedded cmds */ | ||
| 43 | struct be_sge sgl[19]; /* used by non-embedded cmds */ | ||
| 44 | } payload; | ||
| 45 | }; | ||
| 46 | |||
| 47 | #define CQE_FLAGS_VALID_MASK (1 << 31) | ||
| 48 | #define CQE_FLAGS_ASYNC_MASK (1 << 30) | ||
| 49 | #define CQE_FLAGS_COMPLETED_MASK (1 << 28) | ||
| 50 | #define CQE_FLAGS_CONSUMED_MASK (1 << 27) | ||
| 51 | |||
| 52 | /* Completion Status */ | ||
| 53 | enum { | ||
| 54 | MCC_STATUS_SUCCESS = 0x0, | ||
| 55 | /* The client does not have sufficient privileges to execute the command */ | ||
| 56 | MCC_STATUS_INSUFFICIENT_PRIVILEGES = 0x1, | ||
| 57 | /* A parameter in the command was invalid. */ | ||
| 58 | MCC_STATUS_INVALID_PARAMETER = 0x2, | ||
| 59 | /* There are insufficient chip resources to execute the command */ | ||
| 60 | MCC_STATUS_INSUFFICIENT_RESOURCES = 0x3, | ||
| 61 | /* The command is completing because the queue was getting flushed */ | ||
| 62 | MCC_STATUS_QUEUE_FLUSHING = 0x4, | ||
| 63 | /* The command is completing with a DMA error */ | ||
| 64 | MCC_STATUS_DMA_FAILED = 0x5 | ||
| 65 | }; | ||
| 66 | |||
| 67 | #define CQE_STATUS_COMPL_MASK 0xFFFF | ||
| 68 | #define CQE_STATUS_COMPL_SHIFT 0 /* bits 0 - 15 */ | ||
| 69 | #define CQE_STATUS_EXTD_MASK 0xFFFF | ||
| 70 | #define CQE_STATUS_EXTD_SHIFT 0 /* bits 0 - 15 */ | ||
| 71 | |||
| 72 | struct be_mcc_cq_entry { | ||
| 73 | u32 status; /* dword 0 */ | ||
| 74 | u32 tag0; /* dword 1 */ | ||
| 75 | u32 tag1; /* dword 2 */ | ||
| 76 | u32 flags; /* dword 3 */ | ||
| 77 | }; | ||
| 78 | |||
| 79 | struct be_mcc_mailbox { | ||
| 80 | struct be_mcc_wrb wrb; | ||
| 81 | struct be_mcc_cq_entry cqe; | ||
| 82 | }; | ||
| 83 | |||
| 84 | #define CMD_SUBSYSTEM_COMMON 0x1 | ||
| 85 | #define CMD_SUBSYSTEM_ETH 0x3 | ||
| 86 | |||
| 87 | #define OPCODE_COMMON_NTWK_MAC_QUERY 1 | ||
| 88 | #define OPCODE_COMMON_NTWK_MAC_SET 2 | ||
| 89 | #define OPCODE_COMMON_NTWK_MULTICAST_SET 3 | ||
| 90 | #define OPCODE_COMMON_NTWK_VLAN_CONFIG 4 | ||
| 91 | #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY 5 | ||
| 92 | #define OPCODE_COMMON_CQ_CREATE 12 | ||
| 93 | #define OPCODE_COMMON_EQ_CREATE 13 | ||
| 94 | #define OPCODE_COMMON_MCC_CREATE 21 | ||
| 95 | #define OPCODE_COMMON_NTWK_RX_FILTER 34 | ||
| 96 | #define OPCODE_COMMON_GET_FW_VERSION 35 | ||
| 97 | #define OPCODE_COMMON_SET_FLOW_CONTROL 36 | ||
| 98 | #define OPCODE_COMMON_GET_FLOW_CONTROL 37 | ||
| 99 | #define OPCODE_COMMON_SET_FRAME_SIZE 39 | ||
| 100 | #define OPCODE_COMMON_MODIFY_EQ_DELAY 41 | ||
| 101 | #define OPCODE_COMMON_FIRMWARE_CONFIG 42 | ||
| 102 | #define OPCODE_COMMON_NTWK_INTERFACE_CREATE 50 | ||
| 103 | #define OPCODE_COMMON_NTWK_INTERFACE_DESTROY 51 | ||
| 104 | #define OPCODE_COMMON_CQ_DESTROY 54 | ||
| 105 | #define OPCODE_COMMON_EQ_DESTROY 55 | ||
| 106 | #define OPCODE_COMMON_QUERY_FIRMWARE_CONFIG 58 | ||
| 107 | #define OPCODE_COMMON_NTWK_PMAC_ADD 59 | ||
| 108 | #define OPCODE_COMMON_NTWK_PMAC_DEL 60 | ||
| 109 | |||
| 110 | #define OPCODE_ETH_ACPI_CONFIG 2 | ||
| 111 | #define OPCODE_ETH_PROMISCUOUS 3 | ||
| 112 | #define OPCODE_ETH_GET_STATISTICS 4 | ||
| 113 | #define OPCODE_ETH_TX_CREATE 7 | ||
| 114 | #define OPCODE_ETH_RX_CREATE 8 | ||
| 115 | #define OPCODE_ETH_TX_DESTROY 9 | ||
| 116 | #define OPCODE_ETH_RX_DESTROY 10 | ||
| 117 | |||
| 118 | struct be_cmd_req_hdr { | ||
| 119 | u8 opcode; /* dword 0 */ | ||
| 120 | u8 subsystem; /* dword 0 */ | ||
| 121 | u8 port_number; /* dword 0 */ | ||
| 122 | u8 domain; /* dword 0 */ | ||
| 123 | u32 timeout; /* dword 1 */ | ||
| 124 | u32 request_length; /* dword 2 */ | ||
| 125 | u32 rsvd; /* dword 3 */ | ||
| 126 | }; | ||
| 127 | |||
| 128 | #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */ | ||
| 129 | #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */ | ||
| 130 | struct be_cmd_resp_hdr { | ||
| 131 | u32 info; /* dword 0 */ | ||
| 132 | u32 status; /* dword 1 */ | ||
| 133 | u32 response_length; /* dword 2 */ | ||
| 134 | u32 actual_resp_len; /* dword 3 */ | ||
| 135 | }; | ||
| 136 | |||
| 137 | struct phys_addr { | ||
| 138 | u32 lo; | ||
| 139 | u32 hi; | ||
| 140 | }; | ||
| 141 | |||
| 142 | /************************** | ||
| 143 | * BE Command definitions * | ||
| 144 | **************************/ | ||
| 145 | |||
| 146 | /* Pseudo amap definition in which each bit of the actual structure is defined | ||
| 147 | * as a byte: used to calculate offset/shift/mask of each field */ | ||
| 148 | struct amap_eq_context { | ||
| 149 | u8 cidx[13]; /* dword 0*/ | ||
| 150 | u8 rsvd0[3]; /* dword 0*/ | ||
| 151 | u8 epidx[13]; /* dword 0*/ | ||
| 152 | u8 valid; /* dword 0*/ | ||
| 153 | u8 rsvd1; /* dword 0*/ | ||
| 154 | u8 size; /* dword 0*/ | ||
| 155 | u8 pidx[13]; /* dword 1*/ | ||
| 156 | u8 rsvd2[3]; /* dword 1*/ | ||
| 157 | u8 pd[10]; /* dword 1*/ | ||
| 158 | u8 count[3]; /* dword 1*/ | ||
| 159 | u8 solevent; /* dword 1*/ | ||
| 160 | u8 stalled; /* dword 1*/ | ||
| 161 | u8 armed; /* dword 1*/ | ||
| 162 | u8 rsvd3[4]; /* dword 2*/ | ||
| 163 | u8 func[8]; /* dword 2*/ | ||
| 164 | u8 rsvd4; /* dword 2*/ | ||
| 165 | u8 delaymult[10]; /* dword 2*/ | ||
| 166 | u8 rsvd5[2]; /* dword 2*/ | ||
| 167 | u8 phase[2]; /* dword 2*/ | ||
| 168 | u8 nodelay; /* dword 2*/ | ||
| 169 | u8 rsvd6[4]; /* dword 2*/ | ||
| 170 | u8 rsvd7[32]; /* dword 3*/ | ||
| 171 | } __packed; | ||
| 172 | |||
| 173 | struct be_cmd_req_eq_create { | ||
| 174 | struct be_cmd_req_hdr hdr; | ||
| 175 | u16 num_pages; /* sword */ | ||
| 176 | u16 rsvd0; /* sword */ | ||
| 177 | u8 context[sizeof(struct amap_eq_context) / 8]; | ||
| 178 | struct phys_addr pages[8]; | ||
| 179 | } __packed; | ||
| 180 | |||
| 181 | struct be_cmd_resp_eq_create { | ||
| 182 | struct be_cmd_resp_hdr resp_hdr; | ||
| 183 | u16 eq_id; /* sword */ | ||
| 184 | u16 rsvd0; /* sword */ | ||
| 185 | } __packed; | ||
| 186 | |||
| 187 | /******************** Mac query ***************************/ | ||
| 188 | enum { | ||
| 189 | MAC_ADDRESS_TYPE_STORAGE = 0x0, | ||
| 190 | MAC_ADDRESS_TYPE_NETWORK = 0x1, | ||
| 191 | MAC_ADDRESS_TYPE_PD = 0x2, | ||
| 192 | MAC_ADDRESS_TYPE_MANAGEMENT = 0x3 | ||
| 193 | }; | ||
| 194 | |||
| 195 | struct mac_addr { | ||
| 196 | u16 size_of_struct; | ||
| 197 | u8 addr[ETH_ALEN]; | ||
| 198 | } __packed; | ||
| 199 | |||
| 200 | struct be_cmd_req_mac_query { | ||
| 201 | struct be_cmd_req_hdr hdr; | ||
| 202 | u8 type; | ||
| 203 | u8 permanent; | ||
| 204 | u16 if_id; | ||
| 205 | } __packed; | ||
| 206 | |||
| 207 | struct be_cmd_resp_mac_query { | ||
| 208 | struct be_cmd_resp_hdr hdr; | ||
| 209 | struct mac_addr mac; | ||
| 210 | }; | ||
| 211 | |||
| 212 | /******************** PMac Add ***************************/ | ||
| 213 | struct be_cmd_req_pmac_add { | ||
| 214 | struct be_cmd_req_hdr hdr; | ||
| 215 | u32 if_id; | ||
| 216 | u8 mac_address[ETH_ALEN]; | ||
| 217 | u8 rsvd0[2]; | ||
| 218 | } __packed; | ||
| 219 | |||
| 220 | struct be_cmd_resp_pmac_add { | ||
| 221 | struct be_cmd_resp_hdr hdr; | ||
| 222 | u32 pmac_id; | ||
| 223 | }; | ||
| 224 | |||
| 225 | /******************** PMac Del ***************************/ | ||
| 226 | struct be_cmd_req_pmac_del { | ||
| 227 | struct be_cmd_req_hdr hdr; | ||
| 228 | u32 if_id; | ||
| 229 | u32 pmac_id; | ||
| 230 | }; | ||
| 231 | |||
| 232 | /******************** Create CQ ***************************/ | ||
| 233 | /* Pseudo amap definition in which each bit of the actual structure is defined | ||
| 234 | * as a byte: used to calculate offset/shift/mask of each field */ | ||
| 235 | struct amap_cq_context { | ||
| 236 | u8 cidx[11]; /* dword 0*/ | ||
| 237 | u8 rsvd0; /* dword 0*/ | ||
| 238 | u8 coalescwm[2]; /* dword 0*/ | ||
| 239 | u8 nodelay; /* dword 0*/ | ||
| 240 | u8 epidx[11]; /* dword 0*/ | ||
| 241 | u8 rsvd1; /* dword 0*/ | ||
| 242 | u8 count[2]; /* dword 0*/ | ||
| 243 | u8 valid; /* dword 0*/ | ||
| 244 | u8 solevent; /* dword 0*/ | ||
| 245 | u8 eventable; /* dword 0*/ | ||
| 246 | u8 pidx[11]; /* dword 1*/ | ||
| 247 | u8 rsvd2; /* dword 1*/ | ||
| 248 | u8 pd[10]; /* dword 1*/ | ||
| 249 | u8 eqid[8]; /* dword 1*/ | ||
| 250 | u8 stalled; /* dword 1*/ | ||
| 251 | u8 armed; /* dword 1*/ | ||
| 252 | u8 rsvd3[4]; /* dword 2*/ | ||
| 253 | u8 func[8]; /* dword 2*/ | ||
| 254 | u8 rsvd4[20]; /* dword 2*/ | ||
| 255 | u8 rsvd5[32]; /* dword 3*/ | ||
| 256 | } __packed; | ||
| 257 | |||
| 258 | struct be_cmd_req_cq_create { | ||
| 259 | struct be_cmd_req_hdr hdr; | ||
| 260 | u16 num_pages; | ||
| 261 | u16 rsvd0; | ||
| 262 | u8 context[sizeof(struct amap_cq_context) / 8]; | ||
| 263 | struct phys_addr pages[8]; | ||
| 264 | } __packed; | ||
| 265 | |||
| 266 | struct be_cmd_resp_cq_create { | ||
| 267 | struct be_cmd_resp_hdr hdr; | ||
| 268 | u16 cq_id; | ||
| 269 | u16 rsvd0; | ||
| 270 | } __packed; | ||
| 271 | |||
| 272 | /******************** Create TxQ ***************************/ | ||
| 273 | #define BE_ETH_TX_RING_TYPE_STANDARD 2 | ||
| 274 | #define BE_ULP1_NUM 1 | ||
| 275 | |||
| 276 | /* Pseudo amap definition in which each bit of the actual structure is defined | ||
| 277 | * as a byte: used to calculate offset/shift/mask of each field */ | ||
| 278 | struct amap_tx_context { | ||
| 279 | u8 rsvd0[16]; /* dword 0 */ | ||
| 280 | u8 tx_ring_size[4]; /* dword 0 */ | ||
| 281 | u8 rsvd1[26]; /* dword 0 */ | ||
| 282 | u8 pci_func_id[8]; /* dword 1 */ | ||
| 283 | u8 rsvd2[9]; /* dword 1 */ | ||
| 284 | u8 ctx_valid; /* dword 1 */ | ||
| 285 | u8 cq_id_send[16]; /* dword 2 */ | ||
| 286 | u8 rsvd3[16]; /* dword 2 */ | ||
| 287 | u8 rsvd4[32]; /* dword 3 */ | ||
| 288 | u8 rsvd5[32]; /* dword 4 */ | ||
| 289 | u8 rsvd6[32]; /* dword 5 */ | ||
| 290 | u8 rsvd7[32]; /* dword 6 */ | ||
| 291 | u8 rsvd8[32]; /* dword 7 */ | ||
| 292 | u8 rsvd9[32]; /* dword 8 */ | ||
| 293 | u8 rsvd10[32]; /* dword 9 */ | ||
| 294 | u8 rsvd11[32]; /* dword 10 */ | ||
| 295 | u8 rsvd12[32]; /* dword 11 */ | ||
| 296 | u8 rsvd13[32]; /* dword 12 */ | ||
| 297 | u8 rsvd14[32]; /* dword 13 */ | ||
| 298 | u8 rsvd15[32]; /* dword 14 */ | ||
| 299 | u8 rsvd16[32]; /* dword 15 */ | ||
| 300 | } __packed; | ||
| 301 | |||
| 302 | struct be_cmd_req_eth_tx_create { | ||
| 303 | struct be_cmd_req_hdr hdr; | ||
| 304 | u8 num_pages; | ||
| 305 | u8 ulp_num; | ||
| 306 | u8 type; | ||
| 307 | u8 bound_port; | ||
| 308 | u8 context[sizeof(struct amap_tx_context) / 8]; | ||
| 309 | struct phys_addr pages[8]; | ||
| 310 | } __packed; | ||
| 311 | |||
| 312 | struct be_cmd_resp_eth_tx_create { | ||
| 313 | struct be_cmd_resp_hdr hdr; | ||
| 314 | u16 cid; | ||
| 315 | u16 rsvd0; | ||
| 316 | } __packed; | ||
| 317 | |||
| 318 | /******************** Create RxQ ***************************/ | ||
| 319 | struct be_cmd_req_eth_rx_create { | ||
| 320 | struct be_cmd_req_hdr hdr; | ||
| 321 | u16 cq_id; | ||
| 322 | u8 frag_size; | ||
| 323 | u8 num_pages; | ||
| 324 | struct phys_addr pages[2]; | ||
| 325 | u32 interface_id; | ||
| 326 | u16 max_frame_size; | ||
| 327 | u16 rsvd0; | ||
| 328 | u32 rss_queue; | ||
| 329 | } __packed; | ||
| 330 | |||
| 331 | struct be_cmd_resp_eth_rx_create { | ||
| 332 | struct be_cmd_resp_hdr hdr; | ||
| 333 | u16 id; | ||
| 334 | u8 cpu_id; | ||
| 335 | u8 rsvd0; | ||
| 336 | } __packed; | ||
| 337 | |||
| 338 | /******************** Q Destroy ***************************/ | ||
| 339 | /* Type of Queue to be destroyed */ | ||
| 340 | enum { | ||
| 341 | QTYPE_EQ = 1, | ||
| 342 | QTYPE_CQ, | ||
| 343 | QTYPE_TXQ, | ||
| 344 | QTYPE_RXQ | ||
| 345 | }; | ||
| 346 | |||
| 347 | struct be_cmd_req_q_destroy { | ||
| 348 | struct be_cmd_req_hdr hdr; | ||
| 349 | u16 id; | ||
| 350 | u16 bypass_flush; /* valid only for rx q destroy */ | ||
| 351 | } __packed; | ||
| 352 | |||
| 353 | /************ I/f Create (it's actually I/f Config Create)**********/ | ||
| 354 | |||
| 355 | /* Capability flags for the i/f */ | ||
| 356 | enum be_if_flags { | ||
| 357 | BE_IF_FLAGS_RSS = 0x4, | ||
| 358 | BE_IF_FLAGS_PROMISCUOUS = 0x8, | ||
| 359 | BE_IF_FLAGS_BROADCAST = 0x10, | ||
| 360 | BE_IF_FLAGS_UNTAGGED = 0x20, | ||
| 361 | BE_IF_FLAGS_ULP = 0x40, | ||
| 362 | BE_IF_FLAGS_VLAN_PROMISCUOUS = 0x80, | ||
| 363 | BE_IF_FLAGS_VLAN = 0x100, | ||
| 364 | BE_IF_FLAGS_MCAST_PROMISCUOUS = 0x200, | ||
| 365 | BE_IF_FLAGS_PASS_L2_ERRORS = 0x400, | ||
| 366 | BE_IF_FLAGS_PASS_L3L4_ERRORS = 0x800 | ||
| 367 | }; | ||
| 368 | |||
| 369 | /* An RX interface is an object with one or more MAC addresses and | ||
| 370 | * filtering capabilities. */ | ||
| 371 | struct be_cmd_req_if_create { | ||
| 372 | struct be_cmd_req_hdr hdr; | ||
| 373 | u32 version; /* ignore currntly */ | ||
| 374 | u32 capability_flags; | ||
| 375 | u32 enable_flags; | ||
| 376 | u8 mac_addr[ETH_ALEN]; | ||
| 377 | u8 rsvd0; | ||
| 378 | u8 pmac_invalid; /* if set, don't attach the mac addr to the i/f */ | ||
| 379 | u32 vlan_tag; /* not used currently */ | ||
| 380 | } __packed; | ||
| 381 | |||
| 382 | struct be_cmd_resp_if_create { | ||
| 383 | struct be_cmd_resp_hdr hdr; | ||
| 384 | u32 interface_id; | ||
| 385 | u32 pmac_id; | ||
| 386 | }; | ||
| 387 | |||
| 388 | /****** I/f Destroy(it's actually I/f Config Destroy )**********/ | ||
| 389 | struct be_cmd_req_if_destroy { | ||
| 390 | struct be_cmd_req_hdr hdr; | ||
| 391 | u32 interface_id; | ||
| 392 | }; | ||
| 393 | |||
| 394 | /*************** HW Stats Get **********************************/ | ||
| 395 | struct be_port_rxf_stats { | ||
| 396 | u32 rx_bytes_lsd; /* dword 0*/ | ||
| 397 | u32 rx_bytes_msd; /* dword 1*/ | ||
| 398 | u32 rx_total_frames; /* dword 2*/ | ||
| 399 | u32 rx_unicast_frames; /* dword 3*/ | ||
| 400 | u32 rx_multicast_frames; /* dword 4*/ | ||
| 401 | u32 rx_broadcast_frames; /* dword 5*/ | ||
| 402 | u32 rx_crc_errors; /* dword 6*/ | ||
| 403 | u32 rx_alignment_symbol_errors; /* dword 7*/ | ||
| 404 | u32 rx_pause_frames; /* dword 8*/ | ||
| 405 | u32 rx_control_frames; /* dword 9*/ | ||
| 406 | u32 rx_in_range_errors; /* dword 10*/ | ||
| 407 | u32 rx_out_range_errors; /* dword 11*/ | ||
| 408 | u32 rx_frame_too_long; /* dword 12*/ | ||
| 409 | u32 rx_address_match_errors; /* dword 13*/ | ||
| 410 | u32 rx_vlan_mismatch; /* dword 14*/ | ||
| 411 | u32 rx_dropped_too_small; /* dword 15*/ | ||
| 412 | u32 rx_dropped_too_short; /* dword 16*/ | ||
| 413 | u32 rx_dropped_header_too_small; /* dword 17*/ | ||
| 414 | u32 rx_dropped_tcp_length; /* dword 18*/ | ||
| 415 | u32 rx_dropped_runt; /* dword 19*/ | ||
| 416 | u32 rx_64_byte_packets; /* dword 20*/ | ||
| 417 | u32 rx_65_127_byte_packets; /* dword 21*/ | ||
| 418 | u32 rx_128_256_byte_packets; /* dword 22*/ | ||
| 419 | u32 rx_256_511_byte_packets; /* dword 23*/ | ||
| 420 | u32 rx_512_1023_byte_packets; /* dword 24*/ | ||
| 421 | u32 rx_1024_1518_byte_packets; /* dword 25*/ | ||
| 422 | u32 rx_1519_2047_byte_packets; /* dword 26*/ | ||
| 423 | u32 rx_2048_4095_byte_packets; /* dword 27*/ | ||
| 424 | u32 rx_4096_8191_byte_packets; /* dword 28*/ | ||
| 425 | u32 rx_8192_9216_byte_packets; /* dword 29*/ | ||
| 426 | u32 rx_ip_checksum_errs; /* dword 30*/ | ||
| 427 | u32 rx_tcp_checksum_errs; /* dword 31*/ | ||
| 428 | u32 rx_udp_checksum_errs; /* dword 32*/ | ||
| 429 | u32 rx_non_rss_packets; /* dword 33*/ | ||
| 430 | u32 rx_ipv4_packets; /* dword 34*/ | ||
| 431 | u32 rx_ipv6_packets; /* dword 35*/ | ||
| 432 | u32 rx_ipv4_bytes_lsd; /* dword 36*/ | ||
| 433 | u32 rx_ipv4_bytes_msd; /* dword 37*/ | ||
| 434 | u32 rx_ipv6_bytes_lsd; /* dword 38*/ | ||
| 435 | u32 rx_ipv6_bytes_msd; /* dword 39*/ | ||
| 436 | u32 rx_chute1_packets; /* dword 40*/ | ||
| 437 | u32 rx_chute2_packets; /* dword 41*/ | ||
| 438 | u32 rx_chute3_packets; /* dword 42*/ | ||
| 439 | u32 rx_management_packets; /* dword 43*/ | ||
| 440 | u32 rx_switched_unicast_packets; /* dword 44*/ | ||
| 441 | u32 rx_switched_multicast_packets; /* dword 45*/ | ||
| 442 | u32 rx_switched_broadcast_packets; /* dword 46*/ | ||
| 443 | u32 tx_bytes_lsd; /* dword 47*/ | ||
| 444 | u32 tx_bytes_msd; /* dword 48*/ | ||
| 445 | u32 tx_unicastframes; /* dword 49*/ | ||
| 446 | u32 tx_multicastframes; /* dword 50*/ | ||
| 447 | u32 tx_broadcastframes; /* dword 51*/ | ||
| 448 | u32 tx_pauseframes; /* dword 52*/ | ||
| 449 | u32 tx_controlframes; /* dword 53*/ | ||
| 450 | u32 tx_64_byte_packets; /* dword 54*/ | ||
| 451 | u32 tx_65_127_byte_packets; /* dword 55*/ | ||
| 452 | u32 tx_128_256_byte_packets; /* dword 56*/ | ||
| 453 | u32 tx_256_511_byte_packets; /* dword 57*/ | ||
| 454 | u32 tx_512_1023_byte_packets; /* dword 58*/ | ||
| 455 | u32 tx_1024_1518_byte_packets; /* dword 59*/ | ||
| 456 | u32 tx_1519_2047_byte_packets; /* dword 60*/ | ||
| 457 | u32 tx_2048_4095_byte_packets; /* dword 61*/ | ||
| 458 | u32 tx_4096_8191_byte_packets; /* dword 62*/ | ||
| 459 | u32 tx_8192_9216_byte_packets; /* dword 63*/ | ||
| 460 | u32 rx_fifo_overflow; /* dword 64*/ | ||
| 461 | u32 rx_input_fifo_overflow; /* dword 65*/ | ||
| 462 | }; | ||
| 463 | |||
| 464 | struct be_rxf_stats { | ||
| 465 | struct be_port_rxf_stats port[2]; | ||
| 466 | u32 rx_drops_no_pbuf; /* dword 132*/ | ||
| 467 | u32 rx_drops_no_txpb; /* dword 133*/ | ||
| 468 | u32 rx_drops_no_erx_descr; /* dword 134*/ | ||
| 469 | u32 rx_drops_no_tpre_descr; /* dword 135*/ | ||
| 470 | u32 management_rx_port_packets; /* dword 136*/ | ||
| 471 | u32 management_rx_port_bytes; /* dword 137*/ | ||
| 472 | u32 management_rx_port_pause_frames; /* dword 138*/ | ||
| 473 | u32 management_rx_port_errors; /* dword 139*/ | ||
| 474 | u32 management_tx_port_packets; /* dword 140*/ | ||
| 475 | u32 management_tx_port_bytes; /* dword 141*/ | ||
| 476 | u32 management_tx_port_pause; /* dword 142*/ | ||
| 477 | u32 management_rx_port_rxfifo_overflow; /* dword 143*/ | ||
| 478 | u32 rx_drops_too_many_frags; /* dword 144*/ | ||
| 479 | u32 rx_drops_invalid_ring; /* dword 145*/ | ||
| 480 | u32 forwarded_packets; /* dword 146*/ | ||
| 481 | u32 rx_drops_mtu; /* dword 147*/ | ||
| 482 | u32 rsvd0[15]; | ||
| 483 | }; | ||
| 484 | |||
| 485 | struct be_erx_stats { | ||
| 486 | u32 rx_drops_no_fragments[44]; /* dwordS 0 to 43*/ | ||
| 487 | u32 debug_wdma_sent_hold; /* dword 44*/ | ||
| 488 | u32 debug_wdma_pbfree_sent_hold; /* dword 45*/ | ||
| 489 | u32 debug_wdma_zerobyte_pbfree_sent_hold; /* dword 46*/ | ||
| 490 | u32 debug_pmem_pbuf_dealloc; /* dword 47*/ | ||
| 491 | }; | ||
| 492 | |||
| 493 | struct be_hw_stats { | ||
| 494 | struct be_rxf_stats rxf; | ||
| 495 | u32 rsvd[48]; | ||
| 496 | struct be_erx_stats erx; | ||
| 497 | }; | ||
| 498 | |||
| 499 | struct be_cmd_req_get_stats { | ||
| 500 | struct be_cmd_req_hdr hdr; | ||
| 501 | u8 rsvd[sizeof(struct be_hw_stats)]; | ||
| 502 | }; | ||
| 503 | |||
| 504 | struct be_cmd_resp_get_stats { | ||
| 505 | struct be_cmd_resp_hdr hdr; | ||
| 506 | struct be_hw_stats hw_stats; | ||
| 507 | }; | ||
| 508 | |||
| 509 | struct be_cmd_req_vlan_config { | ||
| 510 | struct be_cmd_req_hdr hdr; | ||
| 511 | u8 interface_id; | ||
| 512 | u8 promiscuous; | ||
| 513 | u8 untagged; | ||
| 514 | u8 num_vlan; | ||
| 515 | u16 normal_vlan[64]; | ||
| 516 | } __packed; | ||
| 517 | |||
| 518 | struct be_cmd_req_promiscuous_config { | ||
| 519 | struct be_cmd_req_hdr hdr; | ||
| 520 | u8 port0_promiscuous; | ||
| 521 | u8 port1_promiscuous; | ||
| 522 | u16 rsvd0; | ||
| 523 | } __packed; | ||
| 524 | |||
| 525 | struct macaddr { | ||
| 526 | u8 byte[ETH_ALEN]; | ||
| 527 | }; | ||
| 528 | |||
| 529 | struct be_cmd_req_mcast_mac_config { | ||
| 530 | struct be_cmd_req_hdr hdr; | ||
| 531 | u16 num_mac; | ||
| 532 | u8 promiscuous; | ||
| 533 | u8 interface_id; | ||
| 534 | struct macaddr mac[32]; | ||
| 535 | } __packed; | ||
| 536 | |||
| 537 | static inline struct be_hw_stats * | ||
| 538 | hw_stats_from_cmd(struct be_cmd_resp_get_stats *cmd) | ||
| 539 | { | ||
| 540 | return &cmd->hw_stats; | ||
| 541 | } | ||
| 542 | |||
| 543 | /******************** Link Status Query *******************/ | ||
| 544 | struct be_cmd_req_link_status { | ||
| 545 | struct be_cmd_req_hdr hdr; | ||
| 546 | u32 rsvd; | ||
| 547 | }; | ||
| 548 | |||
| 549 | struct be_link_info { | ||
| 550 | u8 duplex; | ||
| 551 | u8 speed; | ||
| 552 | u8 fault; | ||
| 553 | }; | ||
| 554 | |||
| 555 | enum { | ||
| 556 | PHY_LINK_DUPLEX_NONE = 0x0, | ||
| 557 | PHY_LINK_DUPLEX_HALF = 0x1, | ||
| 558 | PHY_LINK_DUPLEX_FULL = 0x2 | ||
| 559 | }; | ||
| 560 | |||
| 561 | enum { | ||
| 562 | PHY_LINK_SPEED_ZERO = 0x0, /* => No link */ | ||
| 563 | PHY_LINK_SPEED_10MBPS = 0x1, | ||
| 564 | PHY_LINK_SPEED_100MBPS = 0x2, | ||
| 565 | PHY_LINK_SPEED_1GBPS = 0x3, | ||
| 566 | PHY_LINK_SPEED_10GBPS = 0x4 | ||
| 567 | }; | ||
| 568 | |||
| 569 | struct be_cmd_resp_link_status { | ||
| 570 | struct be_cmd_resp_hdr hdr; | ||
| 571 | u8 physical_port; | ||
| 572 | u8 mac_duplex; | ||
| 573 | u8 mac_speed; | ||
| 574 | u8 mac_fault; | ||
| 575 | u8 mgmt_mac_duplex; | ||
| 576 | u8 mgmt_mac_speed; | ||
| 577 | u16 rsvd0; | ||
| 578 | } __packed; | ||
| 579 | |||
| 580 | /******************** Get FW Version *******************/ | ||
| 581 | #define FW_VER_LEN 32 | ||
| 582 | struct be_cmd_req_get_fw_version { | ||
| 583 | struct be_cmd_req_hdr hdr; | ||
| 584 | u8 rsvd0[FW_VER_LEN]; | ||
| 585 | u8 rsvd1[FW_VER_LEN]; | ||
| 586 | } __packed; | ||
| 587 | |||
| 588 | struct be_cmd_resp_get_fw_version { | ||
| 589 | struct be_cmd_resp_hdr hdr; | ||
| 590 | u8 firmware_version_string[FW_VER_LEN]; | ||
| 591 | u8 fw_on_flash_version_string[FW_VER_LEN]; | ||
| 592 | } __packed; | ||
| 593 | |||
| 594 | /******************** Set Flow Contrl *******************/ | ||
| 595 | struct be_cmd_req_set_flow_control { | ||
| 596 | struct be_cmd_req_hdr hdr; | ||
| 597 | u16 tx_flow_control; | ||
| 598 | u16 rx_flow_control; | ||
| 599 | } __packed; | ||
| 600 | |||
| 601 | /******************** Get Flow Contrl *******************/ | ||
| 602 | struct be_cmd_req_get_flow_control { | ||
| 603 | struct be_cmd_req_hdr hdr; | ||
| 604 | u32 rsvd; | ||
| 605 | }; | ||
| 606 | |||
| 607 | struct be_cmd_resp_get_flow_control { | ||
| 608 | struct be_cmd_resp_hdr hdr; | ||
| 609 | u16 tx_flow_control; | ||
| 610 | u16 rx_flow_control; | ||
| 611 | } __packed; | ||
| 612 | |||
| 613 | /******************** Modify EQ Delay *******************/ | ||
| 614 | struct be_cmd_req_modify_eq_delay { | ||
| 615 | struct be_cmd_req_hdr hdr; | ||
| 616 | u32 num_eq; | ||
| 617 | struct { | ||
| 618 | u32 eq_id; | ||
| 619 | u32 phase; | ||
| 620 | u32 delay_multiplier; | ||
| 621 | } delay[8]; | ||
| 622 | } __packed; | ||
| 623 | |||
| 624 | struct be_cmd_resp_modify_eq_delay { | ||
| 625 | struct be_cmd_resp_hdr hdr; | ||
| 626 | u32 rsvd0; | ||
| 627 | } __packed; | ||
| 628 | |||
| 629 | /******************** Get FW Config *******************/ | ||
| 630 | struct be_cmd_req_query_fw_cfg { | ||
| 631 | struct be_cmd_req_hdr hdr; | ||
| 632 | u32 rsvd[30]; | ||
| 633 | }; | ||
| 634 | |||
| 635 | struct be_cmd_resp_query_fw_cfg { | ||
| 636 | struct be_cmd_resp_hdr hdr; | ||
| 637 | u32 be_config_number; | ||
| 638 | u32 asic_revision; | ||
| 639 | u32 phys_port; | ||
| 640 | u32 function_mode; | ||
| 641 | u32 rsvd[26]; | ||
| 642 | }; | ||
| 643 | |||
| 644 | extern int be_pci_fnum_get(struct be_ctrl_info *ctrl); | ||
| 645 | extern int be_cmd_POST(struct be_ctrl_info *ctrl); | ||
| 646 | extern int be_cmd_mac_addr_query(struct be_ctrl_info *ctrl, u8 *mac_addr, | ||
| 647 | u8 type, bool permanent, u32 if_handle); | ||
| 648 | extern int be_cmd_pmac_add(struct be_ctrl_info *ctrl, u8 *mac_addr, | ||
| 649 | u32 if_id, u32 *pmac_id); | ||
| 650 | extern int be_cmd_pmac_del(struct be_ctrl_info *ctrl, u32 if_id, u32 pmac_id); | ||
| 651 | extern int be_cmd_if_create(struct be_ctrl_info *ctrl, u32 if_flags, u8 *mac, | ||
| 652 | bool pmac_invalid, u32 *if_handle, u32 *pmac_id); | ||
| 653 | extern int be_cmd_if_destroy(struct be_ctrl_info *ctrl, u32 if_handle); | ||
| 654 | extern int be_cmd_eq_create(struct be_ctrl_info *ctrl, | ||
| 655 | struct be_queue_info *eq, int eq_delay); | ||
| 656 | extern int be_cmd_cq_create(struct be_ctrl_info *ctrl, | ||
| 657 | struct be_queue_info *cq, struct be_queue_info *eq, | ||
| 658 | bool sol_evts, bool no_delay, | ||
| 659 | int num_cqe_dma_coalesce); | ||
| 660 | extern int be_cmd_txq_create(struct be_ctrl_info *ctrl, | ||
| 661 | struct be_queue_info *txq, | ||
| 662 | struct be_queue_info *cq); | ||
| 663 | extern int be_cmd_rxq_create(struct be_ctrl_info *ctrl, | ||
| 664 | struct be_queue_info *rxq, u16 cq_id, | ||
| 665 | u16 frag_size, u16 max_frame_size, u32 if_id, | ||
| 666 | u32 rss); | ||
| 667 | extern int be_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q, | ||
| 668 | int type); | ||
| 669 | extern int be_cmd_link_status_query(struct be_ctrl_info *ctrl, | ||
| 670 | struct be_link_info *link); | ||
| 671 | extern int be_cmd_reset(struct be_ctrl_info *ctrl); | ||
| 672 | extern int be_cmd_get_stats(struct be_ctrl_info *ctrl, | ||
| 673 | struct be_dma_mem *nonemb_cmd); | ||
| 674 | extern int be_cmd_get_fw_ver(struct be_ctrl_info *ctrl, char *fw_ver); | ||
| 675 | |||
| 676 | extern int be_cmd_modify_eqd(struct be_ctrl_info *ctrl, u32 eq_id, u32 eqd); | ||
| 677 | extern int be_cmd_vlan_config(struct be_ctrl_info *ctrl, u32 if_id, | ||
| 678 | u16 *vtag_array, u32 num, bool untagged, | ||
| 679 | bool promiscuous); | ||
| 680 | extern int be_cmd_promiscuous_config(struct be_ctrl_info *ctrl, | ||
| 681 | u8 port_num, bool en); | ||
| 682 | extern int be_cmd_mcast_mac_set(struct be_ctrl_info *ctrl, u32 if_id, | ||
| 683 | u8 *mac_table, u32 num, bool promiscuous); | ||
| 684 | extern int be_cmd_set_flow_control(struct be_ctrl_info *ctrl, | ||
| 685 | u32 tx_fc, u32 rx_fc); | ||
| 686 | extern int be_cmd_get_flow_control(struct be_ctrl_info *ctrl, | ||
| 687 | u32 *tx_fc, u32 *rx_fc); | ||
| 688 | extern int be_cmd_query_fw_cfg(struct be_ctrl_info *ctrl, u32 *port_num); | ||
diff --git a/drivers/net/benet/be_ethtool.c b/drivers/net/benet/be_ethtool.c new file mode 100644 index 000000000000..04f4b73fa8d8 --- /dev/null +++ b/drivers/net/benet/be_ethtool.c | |||
| @@ -0,0 +1,362 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2009 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include "be.h" | ||
| 19 | #include <linux/ethtool.h> | ||
| 20 | |||
| 21 | struct be_ethtool_stat { | ||
| 22 | char desc[ETH_GSTRING_LEN]; | ||
| 23 | int type; | ||
| 24 | int size; | ||
| 25 | int offset; | ||
| 26 | }; | ||
| 27 | |||
| 28 | enum {NETSTAT, PORTSTAT, MISCSTAT, DRVSTAT, ERXSTAT}; | ||
| 29 | #define FIELDINFO(_struct, field) FIELD_SIZEOF(_struct, field), \ | ||
| 30 | offsetof(_struct, field) | ||
| 31 | #define NETSTAT_INFO(field) #field, NETSTAT,\ | ||
| 32 | FIELDINFO(struct net_device_stats,\ | ||
| 33 | field) | ||
| 34 | #define DRVSTAT_INFO(field) #field, DRVSTAT,\ | ||
| 35 | FIELDINFO(struct be_drvr_stats, field) | ||
| 36 | #define MISCSTAT_INFO(field) #field, MISCSTAT,\ | ||
| 37 | FIELDINFO(struct be_rxf_stats, field) | ||
| 38 | #define PORTSTAT_INFO(field) #field, PORTSTAT,\ | ||
| 39 | FIELDINFO(struct be_port_rxf_stats, \ | ||
| 40 | field) | ||
| 41 | #define ERXSTAT_INFO(field) #field, ERXSTAT,\ | ||
| 42 | FIELDINFO(struct be_erx_stats, field) | ||
| 43 | |||
| 44 | static const struct be_ethtool_stat et_stats[] = { | ||
| 45 | {NETSTAT_INFO(rx_packets)}, | ||
| 46 | {NETSTAT_INFO(tx_packets)}, | ||
| 47 | {NETSTAT_INFO(rx_bytes)}, | ||
| 48 | {NETSTAT_INFO(tx_bytes)}, | ||
| 49 | {NETSTAT_INFO(rx_errors)}, | ||
| 50 | {NETSTAT_INFO(tx_errors)}, | ||
| 51 | {NETSTAT_INFO(rx_dropped)}, | ||
| 52 | {NETSTAT_INFO(tx_dropped)}, | ||
| 53 | {DRVSTAT_INFO(be_tx_reqs)}, | ||
| 54 | {DRVSTAT_INFO(be_tx_stops)}, | ||
| 55 | {DRVSTAT_INFO(be_fwd_reqs)}, | ||
| 56 | {DRVSTAT_INFO(be_tx_wrbs)}, | ||
| 57 | {DRVSTAT_INFO(be_polls)}, | ||
| 58 | {DRVSTAT_INFO(be_tx_events)}, | ||
| 59 | {DRVSTAT_INFO(be_rx_events)}, | ||
| 60 | {DRVSTAT_INFO(be_tx_compl)}, | ||
| 61 | {DRVSTAT_INFO(be_rx_compl)}, | ||
| 62 | {DRVSTAT_INFO(be_ethrx_post_fail)}, | ||
| 63 | {DRVSTAT_INFO(be_802_3_dropped_frames)}, | ||
| 64 | {DRVSTAT_INFO(be_802_3_malformed_frames)}, | ||
| 65 | {DRVSTAT_INFO(be_tx_rate)}, | ||
| 66 | {DRVSTAT_INFO(be_rx_rate)}, | ||
| 67 | {PORTSTAT_INFO(rx_unicast_frames)}, | ||
| 68 | {PORTSTAT_INFO(rx_multicast_frames)}, | ||
| 69 | {PORTSTAT_INFO(rx_broadcast_frames)}, | ||
| 70 | {PORTSTAT_INFO(rx_crc_errors)}, | ||
| 71 | {PORTSTAT_INFO(rx_alignment_symbol_errors)}, | ||
| 72 | {PORTSTAT_INFO(rx_pause_frames)}, | ||
| 73 | {PORTSTAT_INFO(rx_control_frames)}, | ||
| 74 | {PORTSTAT_INFO(rx_in_range_errors)}, | ||
| 75 | {PORTSTAT_INFO(rx_out_range_errors)}, | ||
| 76 | {PORTSTAT_INFO(rx_frame_too_long)}, | ||
| 77 | {PORTSTAT_INFO(rx_address_match_errors)}, | ||
| 78 | {PORTSTAT_INFO(rx_vlan_mismatch)}, | ||
| 79 | {PORTSTAT_INFO(rx_dropped_too_small)}, | ||
| 80 | {PORTSTAT_INFO(rx_dropped_too_short)}, | ||
| 81 | {PORTSTAT_INFO(rx_dropped_header_too_small)}, | ||
| 82 | {PORTSTAT_INFO(rx_dropped_tcp_length)}, | ||
| 83 | {PORTSTAT_INFO(rx_dropped_runt)}, | ||
| 84 | {PORTSTAT_INFO(rx_fifo_overflow)}, | ||
| 85 | {PORTSTAT_INFO(rx_input_fifo_overflow)}, | ||
| 86 | {PORTSTAT_INFO(rx_ip_checksum_errs)}, | ||
| 87 | {PORTSTAT_INFO(rx_tcp_checksum_errs)}, | ||
| 88 | {PORTSTAT_INFO(rx_udp_checksum_errs)}, | ||
| 89 | {PORTSTAT_INFO(rx_non_rss_packets)}, | ||
| 90 | {PORTSTAT_INFO(rx_ipv4_packets)}, | ||
| 91 | {PORTSTAT_INFO(rx_ipv6_packets)}, | ||
| 92 | {PORTSTAT_INFO(tx_unicastframes)}, | ||
| 93 | {PORTSTAT_INFO(tx_multicastframes)}, | ||
| 94 | {PORTSTAT_INFO(tx_broadcastframes)}, | ||
| 95 | {PORTSTAT_INFO(tx_pauseframes)}, | ||
| 96 | {PORTSTAT_INFO(tx_controlframes)}, | ||
| 97 | {MISCSTAT_INFO(rx_drops_no_pbuf)}, | ||
| 98 | {MISCSTAT_INFO(rx_drops_no_txpb)}, | ||
| 99 | {MISCSTAT_INFO(rx_drops_no_erx_descr)}, | ||
| 100 | {MISCSTAT_INFO(rx_drops_no_tpre_descr)}, | ||
| 101 | {MISCSTAT_INFO(rx_drops_too_many_frags)}, | ||
| 102 | {MISCSTAT_INFO(rx_drops_invalid_ring)}, | ||
| 103 | {MISCSTAT_INFO(forwarded_packets)}, | ||
| 104 | {MISCSTAT_INFO(rx_drops_mtu)}, | ||
| 105 | {ERXSTAT_INFO(rx_drops_no_fragments)}, | ||
| 106 | }; | ||
| 107 | #define ETHTOOL_STATS_NUM ARRAY_SIZE(et_stats) | ||
| 108 | |||
| 109 | static void | ||
| 110 | be_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo) | ||
| 111 | { | ||
| 112 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 113 | |||
| 114 | strcpy(drvinfo->driver, DRV_NAME); | ||
| 115 | strcpy(drvinfo->version, DRV_VER); | ||
| 116 | strncpy(drvinfo->fw_version, adapter->fw_ver, FW_VER_LEN); | ||
| 117 | strcpy(drvinfo->bus_info, pci_name(adapter->pdev)); | ||
| 118 | drvinfo->testinfo_len = 0; | ||
| 119 | drvinfo->regdump_len = 0; | ||
| 120 | drvinfo->eedump_len = 0; | ||
| 121 | } | ||
| 122 | |||
| 123 | static int | ||
| 124 | be_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce) | ||
| 125 | { | ||
| 126 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 127 | struct be_eq_obj *rx_eq = &adapter->rx_eq; | ||
| 128 | struct be_eq_obj *tx_eq = &adapter->tx_eq; | ||
| 129 | |||
| 130 | coalesce->rx_max_coalesced_frames = adapter->max_rx_coal; | ||
| 131 | |||
| 132 | coalesce->rx_coalesce_usecs = rx_eq->cur_eqd; | ||
| 133 | coalesce->rx_coalesce_usecs_high = rx_eq->max_eqd; | ||
| 134 | coalesce->rx_coalesce_usecs_low = rx_eq->min_eqd; | ||
| 135 | |||
| 136 | coalesce->tx_coalesce_usecs = tx_eq->cur_eqd; | ||
| 137 | coalesce->tx_coalesce_usecs_high = tx_eq->max_eqd; | ||
| 138 | coalesce->tx_coalesce_usecs_low = tx_eq->min_eqd; | ||
| 139 | |||
| 140 | coalesce->use_adaptive_rx_coalesce = rx_eq->enable_aic; | ||
| 141 | coalesce->use_adaptive_tx_coalesce = tx_eq->enable_aic; | ||
| 142 | |||
| 143 | return 0; | ||
| 144 | } | ||
| 145 | |||
| 146 | /* | ||
| 147 | * This routine is used to set interrup coalescing delay *as well as* | ||
| 148 | * the number of pkts to coalesce for LRO. | ||
| 149 | */ | ||
| 150 | static int | ||
| 151 | be_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce) | ||
| 152 | { | ||
| 153 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 154 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 155 | struct be_eq_obj *rx_eq = &adapter->rx_eq; | ||
| 156 | struct be_eq_obj *tx_eq = &adapter->tx_eq; | ||
| 157 | u32 tx_max, tx_min, tx_cur; | ||
| 158 | u32 rx_max, rx_min, rx_cur; | ||
| 159 | int status = 0; | ||
| 160 | |||
| 161 | if (coalesce->use_adaptive_tx_coalesce == 1) | ||
| 162 | return -EINVAL; | ||
| 163 | |||
| 164 | adapter->max_rx_coal = coalesce->rx_max_coalesced_frames; | ||
| 165 | if (adapter->max_rx_coal > MAX_SKB_FRAGS) | ||
| 166 | adapter->max_rx_coal = MAX_SKB_FRAGS - 1; | ||
| 167 | |||
| 168 | /* if AIC is being turned on now, start with an EQD of 0 */ | ||
| 169 | if (rx_eq->enable_aic == 0 && | ||
| 170 | coalesce->use_adaptive_rx_coalesce == 1) { | ||
| 171 | rx_eq->cur_eqd = 0; | ||
| 172 | } | ||
| 173 | rx_eq->enable_aic = coalesce->use_adaptive_rx_coalesce; | ||
| 174 | |||
| 175 | rx_max = coalesce->rx_coalesce_usecs_high; | ||
| 176 | rx_min = coalesce->rx_coalesce_usecs_low; | ||
| 177 | rx_cur = coalesce->rx_coalesce_usecs; | ||
| 178 | |||
| 179 | tx_max = coalesce->tx_coalesce_usecs_high; | ||
| 180 | tx_min = coalesce->tx_coalesce_usecs_low; | ||
| 181 | tx_cur = coalesce->tx_coalesce_usecs; | ||
| 182 | |||
| 183 | if (tx_cur > BE_MAX_EQD) | ||
| 184 | tx_cur = BE_MAX_EQD; | ||
| 185 | if (tx_eq->cur_eqd != tx_cur) { | ||
| 186 | status = be_cmd_modify_eqd(ctrl, tx_eq->q.id, tx_cur); | ||
| 187 | if (!status) | ||
| 188 | tx_eq->cur_eqd = tx_cur; | ||
| 189 | } | ||
| 190 | |||
| 191 | if (rx_eq->enable_aic) { | ||
| 192 | if (rx_max > BE_MAX_EQD) | ||
| 193 | rx_max = BE_MAX_EQD; | ||
| 194 | if (rx_min > rx_max) | ||
| 195 | rx_min = rx_max; | ||
| 196 | rx_eq->max_eqd = rx_max; | ||
| 197 | rx_eq->min_eqd = rx_min; | ||
| 198 | if (rx_eq->cur_eqd > rx_max) | ||
| 199 | rx_eq->cur_eqd = rx_max; | ||
| 200 | if (rx_eq->cur_eqd < rx_min) | ||
| 201 | rx_eq->cur_eqd = rx_min; | ||
| 202 | } else { | ||
| 203 | if (rx_cur > BE_MAX_EQD) | ||
| 204 | rx_cur = BE_MAX_EQD; | ||
| 205 | if (rx_eq->cur_eqd != rx_cur) { | ||
| 206 | status = be_cmd_modify_eqd(ctrl, rx_eq->q.id, rx_cur); | ||
| 207 | if (!status) | ||
| 208 | rx_eq->cur_eqd = rx_cur; | ||
| 209 | } | ||
| 210 | } | ||
| 211 | return 0; | ||
| 212 | } | ||
| 213 | |||
| 214 | static u32 be_get_rx_csum(struct net_device *netdev) | ||
| 215 | { | ||
| 216 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 217 | |||
| 218 | return adapter->rx_csum; | ||
| 219 | } | ||
| 220 | |||
| 221 | static int be_set_rx_csum(struct net_device *netdev, uint32_t data) | ||
| 222 | { | ||
| 223 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 224 | |||
| 225 | if (data) | ||
| 226 | adapter->rx_csum = true; | ||
| 227 | else | ||
| 228 | adapter->rx_csum = false; | ||
| 229 | |||
| 230 | return 0; | ||
| 231 | } | ||
| 232 | |||
| 233 | static void | ||
| 234 | be_get_ethtool_stats(struct net_device *netdev, | ||
| 235 | struct ethtool_stats *stats, uint64_t *data) | ||
| 236 | { | ||
| 237 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 238 | struct be_drvr_stats *drvr_stats = &adapter->stats.drvr_stats; | ||
| 239 | struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va); | ||
| 240 | struct be_rxf_stats *rxf_stats = &hw_stats->rxf; | ||
| 241 | struct be_port_rxf_stats *port_stats = | ||
| 242 | &rxf_stats->port[adapter->port_num]; | ||
| 243 | struct net_device_stats *net_stats = &adapter->stats.net_stats; | ||
| 244 | struct be_erx_stats *erx_stats = &hw_stats->erx; | ||
| 245 | void *p = NULL; | ||
| 246 | int i; | ||
| 247 | |||
| 248 | for (i = 0; i < ETHTOOL_STATS_NUM; i++) { | ||
| 249 | switch (et_stats[i].type) { | ||
| 250 | case NETSTAT: | ||
| 251 | p = net_stats; | ||
| 252 | break; | ||
| 253 | case DRVSTAT: | ||
| 254 | p = drvr_stats; | ||
| 255 | break; | ||
| 256 | case PORTSTAT: | ||
| 257 | p = port_stats; | ||
| 258 | break; | ||
| 259 | case MISCSTAT: | ||
| 260 | p = rxf_stats; | ||
| 261 | break; | ||
| 262 | case ERXSTAT: /* Currently only one ERX stat is provided */ | ||
| 263 | p = (u32 *)erx_stats + adapter->rx_obj.q.id; | ||
| 264 | break; | ||
| 265 | } | ||
| 266 | |||
| 267 | p = (u8 *)p + et_stats[i].offset; | ||
| 268 | data[i] = (et_stats[i].size == sizeof(u64)) ? | ||
| 269 | *(u64 *)p: *(u32 *)p; | ||
| 270 | } | ||
| 271 | |||
| 272 | return; | ||
| 273 | } | ||
| 274 | |||
| 275 | static void | ||
| 276 | be_get_stat_strings(struct net_device *netdev, uint32_t stringset, | ||
| 277 | uint8_t *data) | ||
| 278 | { | ||
| 279 | int i; | ||
| 280 | switch (stringset) { | ||
| 281 | case ETH_SS_STATS: | ||
| 282 | for (i = 0; i < ETHTOOL_STATS_NUM; i++) { | ||
| 283 | memcpy(data, et_stats[i].desc, ETH_GSTRING_LEN); | ||
| 284 | data += ETH_GSTRING_LEN; | ||
| 285 | } | ||
| 286 | break; | ||
| 287 | } | ||
| 288 | } | ||
| 289 | |||
| 290 | static int be_get_stats_count(struct net_device *netdev) | ||
| 291 | { | ||
| 292 | return ETHTOOL_STATS_NUM; | ||
| 293 | } | ||
| 294 | |||
| 295 | static int be_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) | ||
| 296 | { | ||
| 297 | ecmd->speed = SPEED_10000; | ||
| 298 | ecmd->duplex = DUPLEX_FULL; | ||
| 299 | ecmd->autoneg = AUTONEG_DISABLE; | ||
| 300 | return 0; | ||
| 301 | } | ||
| 302 | |||
| 303 | static void | ||
| 304 | be_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring) | ||
| 305 | { | ||
| 306 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 307 | |||
| 308 | ring->rx_max_pending = adapter->rx_obj.q.len; | ||
| 309 | ring->tx_max_pending = adapter->tx_obj.q.len; | ||
| 310 | |||
| 311 | ring->rx_pending = atomic_read(&adapter->rx_obj.q.used); | ||
| 312 | ring->tx_pending = atomic_read(&adapter->tx_obj.q.used); | ||
| 313 | } | ||
| 314 | |||
| 315 | static void | ||
| 316 | be_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *ecmd) | ||
| 317 | { | ||
| 318 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 319 | |||
| 320 | be_cmd_get_flow_control(&adapter->ctrl, &ecmd->tx_pause, | ||
| 321 | &ecmd->rx_pause); | ||
| 322 | ecmd->autoneg = AUTONEG_ENABLE; | ||
| 323 | } | ||
| 324 | |||
| 325 | static int | ||
| 326 | be_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *ecmd) | ||
| 327 | { | ||
| 328 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 329 | int status; | ||
| 330 | |||
| 331 | if (ecmd->autoneg != AUTONEG_ENABLE) | ||
| 332 | return -EINVAL; | ||
| 333 | |||
| 334 | status = be_cmd_set_flow_control(&adapter->ctrl, ecmd->tx_pause, | ||
| 335 | ecmd->rx_pause); | ||
| 336 | if (!status) | ||
| 337 | dev_warn(&adapter->pdev->dev, "Pause param set failed.\n"); | ||
| 338 | |||
| 339 | return status; | ||
| 340 | } | ||
| 341 | |||
| 342 | struct ethtool_ops be_ethtool_ops = { | ||
| 343 | .get_settings = be_get_settings, | ||
| 344 | .get_drvinfo = be_get_drvinfo, | ||
| 345 | .get_link = ethtool_op_get_link, | ||
| 346 | .get_coalesce = be_get_coalesce, | ||
| 347 | .set_coalesce = be_set_coalesce, | ||
| 348 | .get_ringparam = be_get_ringparam, | ||
| 349 | .get_pauseparam = be_get_pauseparam, | ||
| 350 | .set_pauseparam = be_set_pauseparam, | ||
| 351 | .get_rx_csum = be_get_rx_csum, | ||
| 352 | .set_rx_csum = be_set_rx_csum, | ||
| 353 | .get_tx_csum = ethtool_op_get_tx_csum, | ||
| 354 | .set_tx_csum = ethtool_op_set_tx_csum, | ||
| 355 | .get_sg = ethtool_op_get_sg, | ||
| 356 | .set_sg = ethtool_op_set_sg, | ||
| 357 | .get_tso = ethtool_op_get_tso, | ||
| 358 | .set_tso = ethtool_op_set_tso, | ||
| 359 | .get_strings = be_get_stat_strings, | ||
| 360 | .get_stats_count = be_get_stats_count, | ||
| 361 | .get_ethtool_stats = be_get_ethtool_stats, | ||
| 362 | }; | ||
diff --git a/drivers/net/benet/be_hw.h b/drivers/net/benet/be_hw.h new file mode 100644 index 000000000000..b132aa4893ca --- /dev/null +++ b/drivers/net/benet/be_hw.h | |||
| @@ -0,0 +1,211 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2009 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | |||
| 18 | /********* Mailbox door bell *************/ | ||
| 19 | /* Used for driver communication with the FW. | ||
| 20 | * The software must write this register twice to post any command. First, | ||
| 21 | * it writes the register with hi=1 and the upper bits of the physical address | ||
| 22 | * for the MAILBOX structure. Software must poll the ready bit until this | ||
| 23 | * is acknowledged. Then, sotware writes the register with hi=0 with the lower | ||
| 24 | * bits in the address. It must poll the ready bit until the command is | ||
| 25 | * complete. Upon completion, the MAILBOX will contain a valid completion | ||
| 26 | * queue entry. | ||
| 27 | */ | ||
| 28 | #define MPU_MAILBOX_DB_OFFSET 0x160 | ||
| 29 | #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */ | ||
| 30 | #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */ | ||
| 31 | |||
| 32 | #define MPU_EP_CONTROL 0 | ||
| 33 | |||
| 34 | /********** MPU semphore ******************/ | ||
| 35 | #define MPU_EP_SEMAPHORE_OFFSET 0xac | ||
| 36 | #define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF | ||
| 37 | #define EP_SEMAPHORE_POST_ERR_MASK 0x1 | ||
| 38 | #define EP_SEMAPHORE_POST_ERR_SHIFT 31 | ||
| 39 | /* MPU semphore POST stage values */ | ||
| 40 | #define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */ | ||
| 41 | #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */ | ||
| 42 | #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */ | ||
| 43 | #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */ | ||
| 44 | |||
| 45 | /********* Memory BAR register ************/ | ||
| 46 | #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc | ||
| 47 | /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt | ||
| 48 | * Disable" may still globally block interrupts in addition to individual | ||
| 49 | * interrupt masks; a mechanism for the device driver to block all interrupts | ||
| 50 | * atomically without having to arbitrate for the PCI Interrupt Disable bit | ||
| 51 | * with the OS. | ||
| 52 | */ | ||
| 53 | #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */ | ||
| 54 | /* PCI physical function number */ | ||
| 55 | #define MEMBAR_CTRL_INT_CTRL_PFUNC_MASK 0x7 /* bits 26 - 28 */ | ||
| 56 | #define MEMBAR_CTRL_INT_CTRL_PFUNC_SHIFT 26 | ||
| 57 | |||
| 58 | /********* Event Q door bell *************/ | ||
| 59 | #define DB_EQ_OFFSET DB_CQ_OFFSET | ||
| 60 | #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */ | ||
| 61 | /* Clear the interrupt for this eq */ | ||
| 62 | #define DB_EQ_CLR_SHIFT (9) /* bit 9 */ | ||
| 63 | /* Must be 1 */ | ||
| 64 | #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */ | ||
| 65 | /* Number of event entries processed */ | ||
| 66 | #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ | ||
| 67 | /* Rearm bit */ | ||
| 68 | #define DB_EQ_REARM_SHIFT (29) /* bit 29 */ | ||
| 69 | |||
| 70 | /********* Compl Q door bell *************/ | ||
| 71 | #define DB_CQ_OFFSET 0x120 | ||
| 72 | #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ | ||
| 73 | /* Number of event entries processed */ | ||
| 74 | #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ | ||
| 75 | /* Rearm bit */ | ||
| 76 | #define DB_CQ_REARM_SHIFT (29) /* bit 29 */ | ||
| 77 | |||
| 78 | /********** TX ULP door bell *************/ | ||
| 79 | #define DB_TXULP1_OFFSET 0x60 | ||
| 80 | #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */ | ||
| 81 | /* Number of tx entries posted */ | ||
| 82 | #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */ | ||
| 83 | #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */ | ||
| 84 | |||
| 85 | /********** RQ(erx) door bell ************/ | ||
| 86 | #define DB_RQ_OFFSET 0x100 | ||
| 87 | #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ | ||
| 88 | /* Number of rx frags posted */ | ||
| 89 | #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */ | ||
| 90 | |||
| 91 | /* | ||
| 92 | * BE descriptors: host memory data structures whose formats | ||
| 93 | * are hardwired in BE silicon. | ||
| 94 | */ | ||
| 95 | /* Event Queue Descriptor */ | ||
| 96 | #define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */ | ||
| 97 | #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */ | ||
| 98 | #define EQ_ENTRY_RES_ID_SHIFT 16 | ||
| 99 | struct be_eq_entry { | ||
| 100 | u32 evt; | ||
| 101 | }; | ||
| 102 | |||
| 103 | /* TX Queue Descriptor */ | ||
| 104 | #define ETH_WRB_FRAG_LEN_MASK 0xFFFF | ||
| 105 | struct be_eth_wrb { | ||
| 106 | u32 frag_pa_hi; /* dword 0 */ | ||
| 107 | u32 frag_pa_lo; /* dword 1 */ | ||
| 108 | u32 rsvd0; /* dword 2 */ | ||
| 109 | u32 frag_len; /* dword 3: bits 0 - 15 */ | ||
| 110 | } __packed; | ||
| 111 | |||
| 112 | /* Pseudo amap definition for eth_hdr_wrb in which each bit of the | ||
| 113 | * actual structure is defined as a byte : used to calculate | ||
| 114 | * offset/shift/mask of each field */ | ||
| 115 | struct amap_eth_hdr_wrb { | ||
| 116 | u8 rsvd0[32]; /* dword 0 */ | ||
| 117 | u8 rsvd1[32]; /* dword 1 */ | ||
| 118 | u8 complete; /* dword 2 */ | ||
| 119 | u8 event; | ||
| 120 | u8 crc; | ||
| 121 | u8 forward; | ||
| 122 | u8 ipsec; | ||
| 123 | u8 mgmt; | ||
| 124 | u8 ipcs; | ||
| 125 | u8 udpcs; | ||
| 126 | u8 tcpcs; | ||
| 127 | u8 lso; | ||
| 128 | u8 vlan; | ||
| 129 | u8 gso[2]; | ||
| 130 | u8 num_wrb[5]; | ||
| 131 | u8 lso_mss[14]; | ||
| 132 | u8 len[16]; /* dword 3 */ | ||
| 133 | u8 vlan_tag[16]; | ||
| 134 | } __packed; | ||
| 135 | |||
| 136 | struct be_eth_hdr_wrb { | ||
| 137 | u32 dw[4]; | ||
| 138 | }; | ||
| 139 | |||
| 140 | /* TX Compl Queue Descriptor */ | ||
| 141 | |||
| 142 | /* Pseudo amap definition for eth_tx_compl in which each bit of the | ||
| 143 | * actual structure is defined as a byte: used to calculate | ||
| 144 | * offset/shift/mask of each field */ | ||
| 145 | struct amap_eth_tx_compl { | ||
| 146 | u8 wrb_index[16]; /* dword 0 */ | ||
| 147 | u8 ct[2]; /* dword 0 */ | ||
| 148 | u8 port[2]; /* dword 0 */ | ||
| 149 | u8 rsvd0[8]; /* dword 0 */ | ||
| 150 | u8 status[4]; /* dword 0 */ | ||
| 151 | u8 user_bytes[16]; /* dword 1 */ | ||
| 152 | u8 nwh_bytes[8]; /* dword 1 */ | ||
| 153 | u8 lso; /* dword 1 */ | ||
| 154 | u8 cast_enc[2]; /* dword 1 */ | ||
| 155 | u8 rsvd1[5]; /* dword 1 */ | ||
| 156 | u8 rsvd2[32]; /* dword 2 */ | ||
| 157 | u8 pkts[16]; /* dword 3 */ | ||
| 158 | u8 ringid[11]; /* dword 3 */ | ||
| 159 | u8 hash_val[4]; /* dword 3 */ | ||
| 160 | u8 valid; /* dword 3 */ | ||
| 161 | } __packed; | ||
| 162 | |||
| 163 | struct be_eth_tx_compl { | ||
| 164 | u32 dw[4]; | ||
| 165 | }; | ||
| 166 | |||
| 167 | /* RX Queue Descriptor */ | ||
| 168 | struct be_eth_rx_d { | ||
| 169 | u32 fragpa_hi; | ||
| 170 | u32 fragpa_lo; | ||
| 171 | }; | ||
| 172 | |||
| 173 | /* RX Compl Queue Descriptor */ | ||
| 174 | |||
| 175 | /* Pseudo amap definition for eth_rx_compl in which each bit of the | ||
| 176 | * actual structure is defined as a byte: used to calculate | ||
| 177 | * offset/shift/mask of each field */ | ||
| 178 | struct amap_eth_rx_compl { | ||
| 179 | u8 vlan_tag[16]; /* dword 0 */ | ||
| 180 | u8 pktsize[14]; /* dword 0 */ | ||
| 181 | u8 port; /* dword 0 */ | ||
| 182 | u8 ip_opt; /* dword 0 */ | ||
| 183 | u8 err; /* dword 1 */ | ||
| 184 | u8 rsshp; /* dword 1 */ | ||
| 185 | u8 ipf; /* dword 1 */ | ||
| 186 | u8 tcpf; /* dword 1 */ | ||
| 187 | u8 udpf; /* dword 1 */ | ||
| 188 | u8 ipcksm; /* dword 1 */ | ||
| 189 | u8 l4_cksm; /* dword 1 */ | ||
| 190 | u8 ip_version; /* dword 1 */ | ||
| 191 | u8 macdst[6]; /* dword 1 */ | ||
| 192 | u8 vtp; /* dword 1 */ | ||
| 193 | u8 rsvd0; /* dword 1 */ | ||
| 194 | u8 fragndx[10]; /* dword 1 */ | ||
| 195 | u8 ct[2]; /* dword 1 */ | ||
| 196 | u8 sw; /* dword 1 */ | ||
| 197 | u8 numfrags[3]; /* dword 1 */ | ||
| 198 | u8 rss_flush; /* dword 2 */ | ||
| 199 | u8 cast_enc[2]; /* dword 2 */ | ||
| 200 | u8 qnq; /* dword 2 */ | ||
| 201 | u8 rss_bank; /* dword 2 */ | ||
| 202 | u8 rsvd1[23]; /* dword 2 */ | ||
| 203 | u8 lro_pkt; /* dword 2 */ | ||
| 204 | u8 rsvd2[2]; /* dword 2 */ | ||
| 205 | u8 valid; /* dword 2 */ | ||
| 206 | u8 rsshash[32]; /* dword 3 */ | ||
| 207 | } __packed; | ||
| 208 | |||
| 209 | struct be_eth_rx_compl { | ||
| 210 | u32 dw[4]; | ||
| 211 | }; | ||
diff --git a/drivers/net/benet/be_main.c b/drivers/net/benet/be_main.c new file mode 100644 index 000000000000..0ecaffb70e58 --- /dev/null +++ b/drivers/net/benet/be_main.c | |||
| @@ -0,0 +1,1911 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2009 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | |||
| 18 | #include "be.h" | ||
| 19 | |||
| 20 | MODULE_VERSION(DRV_VER); | ||
| 21 | MODULE_DEVICE_TABLE(pci, be_dev_ids); | ||
| 22 | MODULE_DESCRIPTION(DRV_DESC " " DRV_VER); | ||
| 23 | MODULE_AUTHOR("ServerEngines Corporation"); | ||
| 24 | MODULE_LICENSE("GPL"); | ||
| 25 | |||
| 26 | static unsigned int rx_frag_size = 2048; | ||
| 27 | module_param(rx_frag_size, uint, S_IRUGO); | ||
| 28 | MODULE_PARM_DESC(rx_frag_size, "Size of a fragment that holds rcvd data."); | ||
| 29 | |||
| 30 | #define BE_VENDOR_ID 0x19a2 | ||
| 31 | #define BE2_DEVICE_ID_1 0x0211 | ||
| 32 | static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = { | ||
| 33 | { PCI_DEVICE(BE_VENDOR_ID, BE2_DEVICE_ID_1) }, | ||
| 34 | { 0 } | ||
| 35 | }; | ||
| 36 | MODULE_DEVICE_TABLE(pci, be_dev_ids); | ||
| 37 | |||
| 38 | static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q) | ||
| 39 | { | ||
| 40 | struct be_dma_mem *mem = &q->dma_mem; | ||
| 41 | if (mem->va) | ||
| 42 | pci_free_consistent(adapter->pdev, mem->size, | ||
| 43 | mem->va, mem->dma); | ||
| 44 | } | ||
| 45 | |||
| 46 | static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q, | ||
| 47 | u16 len, u16 entry_size) | ||
| 48 | { | ||
| 49 | struct be_dma_mem *mem = &q->dma_mem; | ||
| 50 | |||
| 51 | memset(q, 0, sizeof(*q)); | ||
| 52 | q->len = len; | ||
| 53 | q->entry_size = entry_size; | ||
| 54 | mem->size = len * entry_size; | ||
| 55 | mem->va = pci_alloc_consistent(adapter->pdev, mem->size, &mem->dma); | ||
| 56 | if (!mem->va) | ||
| 57 | return -1; | ||
| 58 | memset(mem->va, 0, mem->size); | ||
| 59 | return 0; | ||
| 60 | } | ||
| 61 | |||
| 62 | static inline void *queue_head_node(struct be_queue_info *q) | ||
| 63 | { | ||
| 64 | return q->dma_mem.va + q->head * q->entry_size; | ||
| 65 | } | ||
| 66 | |||
| 67 | static inline void *queue_tail_node(struct be_queue_info *q) | ||
| 68 | { | ||
| 69 | return q->dma_mem.va + q->tail * q->entry_size; | ||
| 70 | } | ||
| 71 | |||
| 72 | static inline void queue_head_inc(struct be_queue_info *q) | ||
| 73 | { | ||
| 74 | index_inc(&q->head, q->len); | ||
| 75 | } | ||
| 76 | |||
| 77 | static inline void queue_tail_inc(struct be_queue_info *q) | ||
| 78 | { | ||
| 79 | index_inc(&q->tail, q->len); | ||
| 80 | } | ||
| 81 | |||
| 82 | static void be_intr_set(struct be_ctrl_info *ctrl, bool enable) | ||
| 83 | { | ||
| 84 | u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET; | ||
| 85 | u32 reg = ioread32(addr); | ||
| 86 | u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; | ||
| 87 | if (!enabled && enable) { | ||
| 88 | reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; | ||
| 89 | } else if (enabled && !enable) { | ||
| 90 | reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; | ||
| 91 | } else { | ||
| 92 | printk(KERN_WARNING DRV_NAME | ||
| 93 | ": bad value in membar_int_ctrl reg=0x%x\n", reg); | ||
| 94 | return; | ||
| 95 | } | ||
| 96 | iowrite32(reg, addr); | ||
| 97 | } | ||
| 98 | |||
| 99 | static void be_rxq_notify(struct be_ctrl_info *ctrl, u16 qid, u16 posted) | ||
| 100 | { | ||
| 101 | u32 val = 0; | ||
| 102 | val |= qid & DB_RQ_RING_ID_MASK; | ||
| 103 | val |= posted << DB_RQ_NUM_POSTED_SHIFT; | ||
| 104 | iowrite32(val, ctrl->db + DB_RQ_OFFSET); | ||
| 105 | } | ||
| 106 | |||
| 107 | static void be_txq_notify(struct be_ctrl_info *ctrl, u16 qid, u16 posted) | ||
| 108 | { | ||
| 109 | u32 val = 0; | ||
| 110 | val |= qid & DB_TXULP_RING_ID_MASK; | ||
| 111 | val |= (posted & DB_TXULP_NUM_POSTED_MASK) << DB_TXULP_NUM_POSTED_SHIFT; | ||
| 112 | iowrite32(val, ctrl->db + DB_TXULP1_OFFSET); | ||
| 113 | } | ||
| 114 | |||
| 115 | static void be_eq_notify(struct be_ctrl_info *ctrl, u16 qid, | ||
| 116 | bool arm, bool clear_int, u16 num_popped) | ||
| 117 | { | ||
| 118 | u32 val = 0; | ||
| 119 | val |= qid & DB_EQ_RING_ID_MASK; | ||
| 120 | if (arm) | ||
| 121 | val |= 1 << DB_EQ_REARM_SHIFT; | ||
| 122 | if (clear_int) | ||
| 123 | val |= 1 << DB_EQ_CLR_SHIFT; | ||
| 124 | val |= 1 << DB_EQ_EVNT_SHIFT; | ||
| 125 | val |= num_popped << DB_EQ_NUM_POPPED_SHIFT; | ||
| 126 | iowrite32(val, ctrl->db + DB_EQ_OFFSET); | ||
| 127 | } | ||
| 128 | |||
| 129 | static void be_cq_notify(struct be_ctrl_info *ctrl, u16 qid, | ||
| 130 | bool arm, u16 num_popped) | ||
| 131 | { | ||
| 132 | u32 val = 0; | ||
| 133 | val |= qid & DB_CQ_RING_ID_MASK; | ||
| 134 | if (arm) | ||
| 135 | val |= 1 << DB_CQ_REARM_SHIFT; | ||
| 136 | val |= num_popped << DB_CQ_NUM_POPPED_SHIFT; | ||
| 137 | iowrite32(val, ctrl->db + DB_CQ_OFFSET); | ||
| 138 | } | ||
| 139 | |||
| 140 | |||
| 141 | static int be_mac_addr_set(struct net_device *netdev, void *p) | ||
| 142 | { | ||
| 143 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 144 | struct sockaddr *addr = p; | ||
| 145 | int status = 0; | ||
| 146 | |||
| 147 | if (netif_running(netdev)) { | ||
| 148 | status = be_cmd_pmac_del(&adapter->ctrl, adapter->if_handle, | ||
| 149 | adapter->pmac_id); | ||
| 150 | if (status) | ||
| 151 | return status; | ||
| 152 | |||
| 153 | status = be_cmd_pmac_add(&adapter->ctrl, (u8 *)addr->sa_data, | ||
| 154 | adapter->if_handle, &adapter->pmac_id); | ||
| 155 | } | ||
| 156 | |||
| 157 | if (!status) | ||
| 158 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | ||
| 159 | |||
| 160 | return status; | ||
| 161 | } | ||
| 162 | |||
| 163 | static void netdev_stats_update(struct be_adapter *adapter) | ||
| 164 | { | ||
| 165 | struct be_hw_stats *hw_stats = hw_stats_from_cmd(adapter->stats.cmd.va); | ||
| 166 | struct be_rxf_stats *rxf_stats = &hw_stats->rxf; | ||
| 167 | struct be_port_rxf_stats *port_stats = | ||
| 168 | &rxf_stats->port[adapter->port_num]; | ||
| 169 | struct net_device_stats *dev_stats = &adapter->stats.net_stats; | ||
| 170 | |||
| 171 | dev_stats->rx_packets = port_stats->rx_total_frames; | ||
| 172 | dev_stats->tx_packets = port_stats->tx_unicastframes + | ||
| 173 | port_stats->tx_multicastframes + port_stats->tx_broadcastframes; | ||
| 174 | dev_stats->rx_bytes = (u64) port_stats->rx_bytes_msd << 32 | | ||
| 175 | (u64) port_stats->rx_bytes_lsd; | ||
| 176 | dev_stats->tx_bytes = (u64) port_stats->tx_bytes_msd << 32 | | ||
| 177 | (u64) port_stats->tx_bytes_lsd; | ||
| 178 | |||
| 179 | /* bad pkts received */ | ||
| 180 | dev_stats->rx_errors = port_stats->rx_crc_errors + | ||
| 181 | port_stats->rx_alignment_symbol_errors + | ||
| 182 | port_stats->rx_in_range_errors + | ||
| 183 | port_stats->rx_out_range_errors + port_stats->rx_frame_too_long; | ||
| 184 | |||
| 185 | /* packet transmit problems */ | ||
| 186 | dev_stats->tx_errors = 0; | ||
| 187 | |||
| 188 | /* no space in linux buffers */ | ||
| 189 | dev_stats->rx_dropped = 0; | ||
| 190 | |||
| 191 | /* no space available in linux */ | ||
| 192 | dev_stats->tx_dropped = 0; | ||
| 193 | |||
| 194 | dev_stats->multicast = port_stats->tx_multicastframes; | ||
| 195 | dev_stats->collisions = 0; | ||
| 196 | |||
| 197 | /* detailed rx errors */ | ||
| 198 | dev_stats->rx_length_errors = port_stats->rx_in_range_errors + | ||
| 199 | port_stats->rx_out_range_errors + port_stats->rx_frame_too_long; | ||
| 200 | /* receive ring buffer overflow */ | ||
| 201 | dev_stats->rx_over_errors = 0; | ||
| 202 | dev_stats->rx_crc_errors = port_stats->rx_crc_errors; | ||
| 203 | |||
| 204 | /* frame alignment errors */ | ||
| 205 | dev_stats->rx_frame_errors = port_stats->rx_alignment_symbol_errors; | ||
| 206 | /* receiver fifo overrun */ | ||
| 207 | /* drops_no_pbuf is no per i/f, it's per BE card */ | ||
| 208 | dev_stats->rx_fifo_errors = port_stats->rx_fifo_overflow + | ||
| 209 | port_stats->rx_input_fifo_overflow + | ||
| 210 | rxf_stats->rx_drops_no_pbuf; | ||
| 211 | /* receiver missed packetd */ | ||
| 212 | dev_stats->rx_missed_errors = 0; | ||
| 213 | /* detailed tx_errors */ | ||
| 214 | dev_stats->tx_aborted_errors = 0; | ||
| 215 | dev_stats->tx_carrier_errors = 0; | ||
| 216 | dev_stats->tx_fifo_errors = 0; | ||
| 217 | dev_stats->tx_heartbeat_errors = 0; | ||
| 218 | dev_stats->tx_window_errors = 0; | ||
| 219 | } | ||
| 220 | |||
| 221 | static void be_link_status_update(struct be_adapter *adapter) | ||
| 222 | { | ||
| 223 | struct be_link_info *prev = &adapter->link; | ||
| 224 | struct be_link_info now = { 0 }; | ||
| 225 | struct net_device *netdev = adapter->netdev; | ||
| 226 | |||
| 227 | be_cmd_link_status_query(&adapter->ctrl, &now); | ||
| 228 | |||
| 229 | /* If link came up or went down */ | ||
| 230 | if (now.speed != prev->speed && (now.speed == PHY_LINK_SPEED_ZERO || | ||
| 231 | prev->speed == PHY_LINK_SPEED_ZERO)) { | ||
| 232 | if (now.speed == PHY_LINK_SPEED_ZERO) { | ||
| 233 | netif_stop_queue(netdev); | ||
| 234 | netif_carrier_off(netdev); | ||
| 235 | printk(KERN_INFO "%s: Link down\n", netdev->name); | ||
| 236 | } else { | ||
| 237 | netif_start_queue(netdev); | ||
| 238 | netif_carrier_on(netdev); | ||
| 239 | printk(KERN_INFO "%s: Link up\n", netdev->name); | ||
| 240 | } | ||
| 241 | } | ||
| 242 | *prev = now; | ||
| 243 | } | ||
| 244 | |||
| 245 | /* Update the EQ delay n BE based on the RX frags consumed / sec */ | ||
| 246 | static void be_rx_eqd_update(struct be_adapter *adapter) | ||
| 247 | { | ||
| 248 | u32 eqd; | ||
| 249 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 250 | struct be_eq_obj *rx_eq = &adapter->rx_eq; | ||
| 251 | struct be_drvr_stats *stats = &adapter->stats.drvr_stats; | ||
| 252 | |||
| 253 | /* Update once a second */ | ||
| 254 | if (((jiffies - stats->rx_fps_jiffies) < HZ) || rx_eq->enable_aic == 0) | ||
| 255 | return; | ||
| 256 | |||
| 257 | stats->be_rx_fps = (stats->be_rx_frags - stats->be_prev_rx_frags) / | ||
| 258 | ((jiffies - stats->rx_fps_jiffies) / HZ); | ||
| 259 | |||
| 260 | stats->rx_fps_jiffies = jiffies; | ||
| 261 | stats->be_prev_rx_frags = stats->be_rx_frags; | ||
| 262 | eqd = stats->be_rx_fps / 110000; | ||
| 263 | eqd = eqd << 3; | ||
| 264 | if (eqd > rx_eq->max_eqd) | ||
| 265 | eqd = rx_eq->max_eqd; | ||
| 266 | if (eqd < rx_eq->min_eqd) | ||
| 267 | eqd = rx_eq->min_eqd; | ||
| 268 | if (eqd < 10) | ||
| 269 | eqd = 0; | ||
| 270 | if (eqd != rx_eq->cur_eqd) | ||
| 271 | be_cmd_modify_eqd(ctrl, rx_eq->q.id, eqd); | ||
| 272 | |||
| 273 | rx_eq->cur_eqd = eqd; | ||
| 274 | } | ||
| 275 | |||
| 276 | static struct net_device_stats *be_get_stats(struct net_device *dev) | ||
| 277 | { | ||
| 278 | struct be_adapter *adapter = netdev_priv(dev); | ||
| 279 | |||
| 280 | return &adapter->stats.net_stats; | ||
| 281 | } | ||
| 282 | |||
| 283 | static void be_tx_stats_update(struct be_adapter *adapter, | ||
| 284 | u32 wrb_cnt, u32 copied, bool stopped) | ||
| 285 | { | ||
| 286 | struct be_drvr_stats *stats = &adapter->stats.drvr_stats; | ||
| 287 | stats->be_tx_reqs++; | ||
| 288 | stats->be_tx_wrbs += wrb_cnt; | ||
| 289 | stats->be_tx_bytes += copied; | ||
| 290 | if (stopped) | ||
| 291 | stats->be_tx_stops++; | ||
| 292 | |||
| 293 | /* Update tx rate once in two seconds */ | ||
| 294 | if ((jiffies - stats->be_tx_jiffies) > 2 * HZ) { | ||
| 295 | u32 r; | ||
| 296 | r = (stats->be_tx_bytes - stats->be_tx_bytes_prev) / | ||
| 297 | ((u32) (jiffies - stats->be_tx_jiffies) / HZ); | ||
| 298 | r = (r / 1000000); /* M bytes/s */ | ||
| 299 | stats->be_tx_rate = (r * 8); /* M bits/s */ | ||
| 300 | stats->be_tx_jiffies = jiffies; | ||
| 301 | stats->be_tx_bytes_prev = stats->be_tx_bytes; | ||
| 302 | } | ||
| 303 | } | ||
| 304 | |||
| 305 | /* Determine number of WRB entries needed to xmit data in an skb */ | ||
| 306 | static u32 wrb_cnt_for_skb(struct sk_buff *skb, bool *dummy) | ||
| 307 | { | ||
| 308 | int cnt = 0; | ||
| 309 | while (skb) { | ||
| 310 | if (skb->len > skb->data_len) | ||
| 311 | cnt++; | ||
| 312 | cnt += skb_shinfo(skb)->nr_frags; | ||
| 313 | skb = skb_shinfo(skb)->frag_list; | ||
| 314 | } | ||
| 315 | /* to account for hdr wrb */ | ||
| 316 | cnt++; | ||
| 317 | if (cnt & 1) { | ||
| 318 | /* add a dummy to make it an even num */ | ||
| 319 | cnt++; | ||
| 320 | *dummy = true; | ||
| 321 | } else | ||
| 322 | *dummy = false; | ||
| 323 | BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT); | ||
| 324 | return cnt; | ||
| 325 | } | ||
| 326 | |||
| 327 | static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len) | ||
| 328 | { | ||
| 329 | wrb->frag_pa_hi = upper_32_bits(addr); | ||
| 330 | wrb->frag_pa_lo = addr & 0xFFFFFFFF; | ||
| 331 | wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK; | ||
| 332 | } | ||
| 333 | |||
| 334 | static void wrb_fill_hdr(struct be_eth_hdr_wrb *hdr, struct sk_buff *skb, | ||
| 335 | bool vlan, u32 wrb_cnt, u32 len) | ||
| 336 | { | ||
| 337 | memset(hdr, 0, sizeof(*hdr)); | ||
| 338 | |||
| 339 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1); | ||
| 340 | |||
| 341 | if (skb_shinfo(skb)->gso_segs > 1 && skb_shinfo(skb)->gso_size) { | ||
| 342 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1); | ||
| 343 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss, | ||
| 344 | hdr, skb_shinfo(skb)->gso_size); | ||
| 345 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | ||
| 346 | if (is_tcp_pkt(skb)) | ||
| 347 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1); | ||
| 348 | else if (is_udp_pkt(skb)) | ||
| 349 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1); | ||
| 350 | } | ||
| 351 | |||
| 352 | if (vlan && vlan_tx_tag_present(skb)) { | ||
| 353 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1); | ||
| 354 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag, | ||
| 355 | hdr, vlan_tx_tag_get(skb)); | ||
| 356 | } | ||
| 357 | |||
| 358 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1); | ||
| 359 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, 1); | ||
| 360 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt); | ||
| 361 | AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len); | ||
| 362 | } | ||
| 363 | |||
| 364 | |||
| 365 | static int make_tx_wrbs(struct be_adapter *adapter, | ||
| 366 | struct sk_buff *skb, u32 wrb_cnt, bool dummy_wrb) | ||
| 367 | { | ||
| 368 | u64 busaddr; | ||
| 369 | u32 i, copied = 0; | ||
| 370 | struct pci_dev *pdev = adapter->pdev; | ||
| 371 | struct sk_buff *first_skb = skb; | ||
| 372 | struct be_queue_info *txq = &adapter->tx_obj.q; | ||
| 373 | struct be_eth_wrb *wrb; | ||
| 374 | struct be_eth_hdr_wrb *hdr; | ||
| 375 | |||
| 376 | atomic_add(wrb_cnt, &txq->used); | ||
| 377 | hdr = queue_head_node(txq); | ||
| 378 | queue_head_inc(txq); | ||
| 379 | |||
| 380 | while (skb) { | ||
| 381 | if (skb->len > skb->data_len) { | ||
| 382 | int len = skb->len - skb->data_len; | ||
| 383 | busaddr = pci_map_single(pdev, skb->data, len, | ||
| 384 | PCI_DMA_TODEVICE); | ||
| 385 | wrb = queue_head_node(txq); | ||
| 386 | wrb_fill(wrb, busaddr, len); | ||
| 387 | be_dws_cpu_to_le(wrb, sizeof(*wrb)); | ||
| 388 | queue_head_inc(txq); | ||
| 389 | copied += len; | ||
| 390 | } | ||
| 391 | |||
| 392 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | ||
| 393 | struct skb_frag_struct *frag = | ||
| 394 | &skb_shinfo(skb)->frags[i]; | ||
| 395 | busaddr = pci_map_page(pdev, frag->page, | ||
| 396 | frag->page_offset, | ||
| 397 | frag->size, PCI_DMA_TODEVICE); | ||
| 398 | wrb = queue_head_node(txq); | ||
| 399 | wrb_fill(wrb, busaddr, frag->size); | ||
| 400 | be_dws_cpu_to_le(wrb, sizeof(*wrb)); | ||
| 401 | queue_head_inc(txq); | ||
| 402 | copied += frag->size; | ||
| 403 | } | ||
| 404 | skb = skb_shinfo(skb)->frag_list; | ||
| 405 | } | ||
| 406 | |||
| 407 | if (dummy_wrb) { | ||
| 408 | wrb = queue_head_node(txq); | ||
| 409 | wrb_fill(wrb, 0, 0); | ||
| 410 | be_dws_cpu_to_le(wrb, sizeof(*wrb)); | ||
| 411 | queue_head_inc(txq); | ||
| 412 | } | ||
| 413 | |||
| 414 | wrb_fill_hdr(hdr, first_skb, adapter->vlan_grp ? true : false, | ||
| 415 | wrb_cnt, copied); | ||
| 416 | be_dws_cpu_to_le(hdr, sizeof(*hdr)); | ||
| 417 | |||
| 418 | return copied; | ||
| 419 | } | ||
| 420 | |||
| 421 | static int be_xmit(struct sk_buff *skb, struct net_device *netdev) | ||
| 422 | { | ||
| 423 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 424 | struct be_tx_obj *tx_obj = &adapter->tx_obj; | ||
| 425 | struct be_queue_info *txq = &tx_obj->q; | ||
| 426 | u32 wrb_cnt = 0, copied = 0; | ||
| 427 | u32 start = txq->head; | ||
| 428 | bool dummy_wrb, stopped = false; | ||
| 429 | |||
| 430 | wrb_cnt = wrb_cnt_for_skb(skb, &dummy_wrb); | ||
| 431 | |||
| 432 | copied = make_tx_wrbs(adapter, skb, wrb_cnt, dummy_wrb); | ||
| 433 | |||
| 434 | /* record the sent skb in the sent_skb table */ | ||
| 435 | BUG_ON(tx_obj->sent_skb_list[start]); | ||
| 436 | tx_obj->sent_skb_list[start] = skb; | ||
| 437 | |||
| 438 | /* Ensure that txq has space for the next skb; Else stop the queue | ||
| 439 | * *BEFORE* ringing the tx doorbell, so that we serialze the | ||
| 440 | * tx compls of the current transmit which'll wake up the queue | ||
| 441 | */ | ||
| 442 | if ((BE_MAX_TX_FRAG_COUNT + atomic_read(&txq->used)) >= txq->len) { | ||
| 443 | netif_stop_queue(netdev); | ||
| 444 | stopped = true; | ||
| 445 | } | ||
| 446 | |||
| 447 | be_txq_notify(&adapter->ctrl, txq->id, wrb_cnt); | ||
| 448 | |||
| 449 | netdev->trans_start = jiffies; | ||
| 450 | |||
| 451 | be_tx_stats_update(adapter, wrb_cnt, copied, stopped); | ||
| 452 | return NETDEV_TX_OK; | ||
| 453 | } | ||
| 454 | |||
| 455 | static int be_change_mtu(struct net_device *netdev, int new_mtu) | ||
| 456 | { | ||
| 457 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 458 | if (new_mtu < BE_MIN_MTU || | ||
| 459 | new_mtu > BE_MAX_JUMBO_FRAME_SIZE) { | ||
| 460 | dev_info(&adapter->pdev->dev, | ||
| 461 | "MTU must be between %d and %d bytes\n", | ||
| 462 | BE_MIN_MTU, BE_MAX_JUMBO_FRAME_SIZE); | ||
| 463 | return -EINVAL; | ||
| 464 | } | ||
| 465 | dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n", | ||
| 466 | netdev->mtu, new_mtu); | ||
| 467 | netdev->mtu = new_mtu; | ||
| 468 | return 0; | ||
| 469 | } | ||
| 470 | |||
| 471 | /* | ||
| 472 | * if there are BE_NUM_VLANS_SUPPORTED or lesser number of VLANS configured, | ||
| 473 | * program them in BE. If more than BE_NUM_VLANS_SUPPORTED are configured, | ||
| 474 | * set the BE in promiscuous VLAN mode. | ||
| 475 | */ | ||
| 476 | static void be_vid_config(struct net_device *netdev) | ||
| 477 | { | ||
| 478 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 479 | u16 vtag[BE_NUM_VLANS_SUPPORTED]; | ||
| 480 | u16 ntags = 0, i; | ||
| 481 | |||
| 482 | if (adapter->num_vlans <= BE_NUM_VLANS_SUPPORTED) { | ||
| 483 | /* Construct VLAN Table to give to HW */ | ||
| 484 | for (i = 0; i < VLAN_GROUP_ARRAY_LEN; i++) { | ||
| 485 | if (adapter->vlan_tag[i]) { | ||
| 486 | vtag[ntags] = cpu_to_le16(i); | ||
| 487 | ntags++; | ||
| 488 | } | ||
| 489 | } | ||
| 490 | be_cmd_vlan_config(&adapter->ctrl, adapter->if_handle, | ||
| 491 | vtag, ntags, 1, 0); | ||
| 492 | } else { | ||
| 493 | be_cmd_vlan_config(&adapter->ctrl, adapter->if_handle, | ||
| 494 | NULL, 0, 1, 1); | ||
| 495 | } | ||
| 496 | } | ||
| 497 | |||
| 498 | static void be_vlan_register(struct net_device *netdev, struct vlan_group *grp) | ||
| 499 | { | ||
| 500 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 501 | struct be_eq_obj *rx_eq = &adapter->rx_eq; | ||
| 502 | struct be_eq_obj *tx_eq = &adapter->tx_eq; | ||
| 503 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 504 | |||
| 505 | be_eq_notify(ctrl, rx_eq->q.id, false, false, 0); | ||
| 506 | be_eq_notify(ctrl, tx_eq->q.id, false, false, 0); | ||
| 507 | adapter->vlan_grp = grp; | ||
| 508 | be_eq_notify(ctrl, rx_eq->q.id, true, false, 0); | ||
| 509 | be_eq_notify(ctrl, tx_eq->q.id, true, false, 0); | ||
| 510 | } | ||
| 511 | |||
| 512 | static void be_vlan_add_vid(struct net_device *netdev, u16 vid) | ||
| 513 | { | ||
| 514 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 515 | |||
| 516 | adapter->num_vlans++; | ||
| 517 | adapter->vlan_tag[vid] = 1; | ||
| 518 | |||
| 519 | be_vid_config(netdev); | ||
| 520 | } | ||
| 521 | |||
| 522 | static void be_vlan_rem_vid(struct net_device *netdev, u16 vid) | ||
| 523 | { | ||
| 524 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 525 | |||
| 526 | adapter->num_vlans--; | ||
| 527 | adapter->vlan_tag[vid] = 0; | ||
| 528 | |||
| 529 | vlan_group_set_device(adapter->vlan_grp, vid, NULL); | ||
| 530 | be_vid_config(netdev); | ||
| 531 | } | ||
| 532 | |||
| 533 | static void be_set_multicast_filter(struct net_device *netdev) | ||
| 534 | { | ||
| 535 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 536 | struct dev_mc_list *mc_ptr; | ||
| 537 | u8 mac_addr[32][ETH_ALEN]; | ||
| 538 | int i = 0; | ||
| 539 | |||
| 540 | if (netdev->flags & IFF_ALLMULTI) { | ||
| 541 | /* set BE in Multicast promiscuous */ | ||
| 542 | be_cmd_mcast_mac_set(&adapter->ctrl, | ||
| 543 | adapter->if_handle, NULL, 0, true); | ||
| 544 | return; | ||
| 545 | } | ||
| 546 | |||
| 547 | for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) { | ||
| 548 | memcpy(&mac_addr[i][0], mc_ptr->dmi_addr, ETH_ALEN); | ||
| 549 | if (++i >= 32) { | ||
| 550 | be_cmd_mcast_mac_set(&adapter->ctrl, | ||
| 551 | adapter->if_handle, &mac_addr[0][0], i, false); | ||
| 552 | i = 0; | ||
| 553 | } | ||
| 554 | |||
| 555 | } | ||
| 556 | |||
| 557 | if (i) { | ||
| 558 | /* reset the promiscuous mode also. */ | ||
| 559 | be_cmd_mcast_mac_set(&adapter->ctrl, | ||
| 560 | adapter->if_handle, &mac_addr[0][0], i, false); | ||
| 561 | } | ||
| 562 | } | ||
| 563 | |||
| 564 | static void be_set_multicast_list(struct net_device *netdev) | ||
| 565 | { | ||
| 566 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 567 | |||
| 568 | if (netdev->flags & IFF_PROMISC) { | ||
| 569 | be_cmd_promiscuous_config(&adapter->ctrl, adapter->port_num, 1); | ||
| 570 | } else { | ||
| 571 | be_cmd_promiscuous_config(&adapter->ctrl, adapter->port_num, 0); | ||
| 572 | be_set_multicast_filter(netdev); | ||
| 573 | } | ||
| 574 | } | ||
| 575 | |||
| 576 | static void be_rx_rate_update(struct be_adapter *adapter, u32 pktsize, | ||
| 577 | u16 numfrags) | ||
| 578 | { | ||
| 579 | struct be_drvr_stats *stats = &adapter->stats.drvr_stats; | ||
| 580 | u32 rate; | ||
| 581 | |||
| 582 | stats->be_rx_compl++; | ||
| 583 | stats->be_rx_frags += numfrags; | ||
| 584 | stats->be_rx_bytes += pktsize; | ||
| 585 | |||
| 586 | /* Update the rate once in two seconds */ | ||
| 587 | if ((jiffies - stats->be_rx_jiffies) < 2 * HZ) | ||
| 588 | return; | ||
| 589 | |||
| 590 | rate = (stats->be_rx_bytes - stats->be_rx_bytes_prev) / | ||
| 591 | ((u32) (jiffies - stats->be_rx_jiffies) / HZ); | ||
| 592 | rate = (rate / 1000000); /* MB/Sec */ | ||
| 593 | stats->be_rx_rate = (rate * 8); /* Mega Bits/Sec */ | ||
| 594 | stats->be_rx_jiffies = jiffies; | ||
| 595 | stats->be_rx_bytes_prev = stats->be_rx_bytes; | ||
| 596 | } | ||
| 597 | |||
| 598 | static struct be_rx_page_info * | ||
| 599 | get_rx_page_info(struct be_adapter *adapter, u16 frag_idx) | ||
| 600 | { | ||
| 601 | struct be_rx_page_info *rx_page_info; | ||
| 602 | struct be_queue_info *rxq = &adapter->rx_obj.q; | ||
| 603 | |||
| 604 | rx_page_info = &adapter->rx_obj.page_info_tbl[frag_idx]; | ||
| 605 | BUG_ON(!rx_page_info->page); | ||
| 606 | |||
| 607 | if (rx_page_info->last_page_user) | ||
| 608 | pci_unmap_page(adapter->pdev, pci_unmap_addr(rx_page_info, bus), | ||
| 609 | adapter->big_page_size, PCI_DMA_FROMDEVICE); | ||
| 610 | |||
| 611 | atomic_dec(&rxq->used); | ||
| 612 | return rx_page_info; | ||
| 613 | } | ||
| 614 | |||
| 615 | /* Throwaway the data in the Rx completion */ | ||
| 616 | static void be_rx_compl_discard(struct be_adapter *adapter, | ||
| 617 | struct be_eth_rx_compl *rxcp) | ||
| 618 | { | ||
| 619 | struct be_queue_info *rxq = &adapter->rx_obj.q; | ||
| 620 | struct be_rx_page_info *page_info; | ||
| 621 | u16 rxq_idx, i, num_rcvd; | ||
| 622 | |||
| 623 | rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp); | ||
| 624 | num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp); | ||
| 625 | |||
| 626 | for (i = 0; i < num_rcvd; i++) { | ||
| 627 | page_info = get_rx_page_info(adapter, rxq_idx); | ||
| 628 | put_page(page_info->page); | ||
| 629 | memset(page_info, 0, sizeof(*page_info)); | ||
| 630 | index_inc(&rxq_idx, rxq->len); | ||
| 631 | } | ||
| 632 | } | ||
| 633 | |||
| 634 | /* | ||
| 635 | * skb_fill_rx_data forms a complete skb for an ether frame | ||
| 636 | * indicated by rxcp. | ||
| 637 | */ | ||
| 638 | static void skb_fill_rx_data(struct be_adapter *adapter, | ||
| 639 | struct sk_buff *skb, struct be_eth_rx_compl *rxcp) | ||
| 640 | { | ||
| 641 | struct be_queue_info *rxq = &adapter->rx_obj.q; | ||
| 642 | struct be_rx_page_info *page_info; | ||
| 643 | u16 rxq_idx, i, num_rcvd; | ||
| 644 | u32 pktsize, hdr_len, curr_frag_len; | ||
| 645 | u8 *start; | ||
| 646 | |||
| 647 | rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp); | ||
| 648 | pktsize = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp); | ||
| 649 | num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp); | ||
| 650 | |||
| 651 | page_info = get_rx_page_info(adapter, rxq_idx); | ||
| 652 | |||
| 653 | start = page_address(page_info->page) + page_info->page_offset; | ||
| 654 | prefetch(start); | ||
| 655 | |||
| 656 | /* Copy data in the first descriptor of this completion */ | ||
| 657 | curr_frag_len = min(pktsize, rx_frag_size); | ||
| 658 | |||
| 659 | /* Copy the header portion into skb_data */ | ||
| 660 | hdr_len = min((u32)BE_HDR_LEN, curr_frag_len); | ||
| 661 | memcpy(skb->data, start, hdr_len); | ||
| 662 | skb->len = curr_frag_len; | ||
| 663 | if (curr_frag_len <= BE_HDR_LEN) { /* tiny packet */ | ||
| 664 | /* Complete packet has now been moved to data */ | ||
| 665 | put_page(page_info->page); | ||
| 666 | skb->data_len = 0; | ||
| 667 | skb->tail += curr_frag_len; | ||
| 668 | } else { | ||
| 669 | skb_shinfo(skb)->nr_frags = 1; | ||
| 670 | skb_shinfo(skb)->frags[0].page = page_info->page; | ||
| 671 | skb_shinfo(skb)->frags[0].page_offset = | ||
| 672 | page_info->page_offset + hdr_len; | ||
| 673 | skb_shinfo(skb)->frags[0].size = curr_frag_len - hdr_len; | ||
| 674 | skb->data_len = curr_frag_len - hdr_len; | ||
| 675 | skb->tail += hdr_len; | ||
| 676 | } | ||
| 677 | memset(page_info, 0, sizeof(*page_info)); | ||
| 678 | |||
| 679 | if (pktsize <= rx_frag_size) { | ||
| 680 | BUG_ON(num_rcvd != 1); | ||
| 681 | return; | ||
| 682 | } | ||
| 683 | |||
| 684 | /* More frags present for this completion */ | ||
| 685 | pktsize -= curr_frag_len; /* account for above copied frag */ | ||
| 686 | for (i = 1; i < num_rcvd; i++) { | ||
| 687 | index_inc(&rxq_idx, rxq->len); | ||
| 688 | page_info = get_rx_page_info(adapter, rxq_idx); | ||
| 689 | |||
| 690 | curr_frag_len = min(pktsize, rx_frag_size); | ||
| 691 | |||
| 692 | skb_shinfo(skb)->frags[i].page = page_info->page; | ||
| 693 | skb_shinfo(skb)->frags[i].page_offset = page_info->page_offset; | ||
| 694 | skb_shinfo(skb)->frags[i].size = curr_frag_len; | ||
| 695 | skb->len += curr_frag_len; | ||
| 696 | skb->data_len += curr_frag_len; | ||
| 697 | skb_shinfo(skb)->nr_frags++; | ||
| 698 | pktsize -= curr_frag_len; | ||
| 699 | |||
| 700 | memset(page_info, 0, sizeof(*page_info)); | ||
| 701 | } | ||
| 702 | |||
| 703 | be_rx_rate_update(adapter, pktsize, num_rcvd); | ||
| 704 | return; | ||
| 705 | } | ||
| 706 | |||
| 707 | /* Process the RX completion indicated by rxcp when LRO is disabled */ | ||
| 708 | static void be_rx_compl_process(struct be_adapter *adapter, | ||
| 709 | struct be_eth_rx_compl *rxcp) | ||
| 710 | { | ||
| 711 | struct sk_buff *skb; | ||
| 712 | u32 vtp, vid; | ||
| 713 | int l4_cksm; | ||
| 714 | |||
| 715 | l4_cksm = AMAP_GET_BITS(struct amap_eth_rx_compl, l4_cksm, rxcp); | ||
| 716 | vtp = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp); | ||
| 717 | |||
| 718 | skb = netdev_alloc_skb(adapter->netdev, BE_HDR_LEN + NET_IP_ALIGN); | ||
| 719 | if (!skb) { | ||
| 720 | if (net_ratelimit()) | ||
| 721 | dev_warn(&adapter->pdev->dev, "skb alloc failed\n"); | ||
| 722 | be_rx_compl_discard(adapter, rxcp); | ||
| 723 | return; | ||
| 724 | } | ||
| 725 | |||
| 726 | skb_reserve(skb, NET_IP_ALIGN); | ||
| 727 | |||
| 728 | skb_fill_rx_data(adapter, skb, rxcp); | ||
| 729 | |||
| 730 | if (l4_cksm && adapter->rx_csum) | ||
| 731 | skb->ip_summed = CHECKSUM_UNNECESSARY; | ||
| 732 | else | ||
| 733 | skb->ip_summed = CHECKSUM_NONE; | ||
| 734 | |||
| 735 | skb->truesize = skb->len + sizeof(struct sk_buff); | ||
| 736 | skb->protocol = eth_type_trans(skb, adapter->netdev); | ||
| 737 | skb->dev = adapter->netdev; | ||
| 738 | |||
| 739 | if (vtp) { | ||
| 740 | if (!adapter->vlan_grp || adapter->num_vlans == 0) { | ||
| 741 | kfree_skb(skb); | ||
| 742 | return; | ||
| 743 | } | ||
| 744 | vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp); | ||
| 745 | vid = be16_to_cpu(vid); | ||
| 746 | vlan_hwaccel_receive_skb(skb, adapter->vlan_grp, vid); | ||
| 747 | } else { | ||
| 748 | netif_receive_skb(skb); | ||
| 749 | } | ||
| 750 | |||
| 751 | adapter->netdev->last_rx = jiffies; | ||
| 752 | |||
| 753 | return; | ||
| 754 | } | ||
| 755 | |||
| 756 | /* Process the RX completion indicated by rxcp when LRO is enabled */ | ||
| 757 | static void be_rx_compl_process_lro(struct be_adapter *adapter, | ||
| 758 | struct be_eth_rx_compl *rxcp) | ||
| 759 | { | ||
| 760 | struct be_rx_page_info *page_info; | ||
| 761 | struct skb_frag_struct rx_frags[BE_MAX_FRAGS_PER_FRAME]; | ||
| 762 | struct be_queue_info *rxq = &adapter->rx_obj.q; | ||
| 763 | u32 num_rcvd, pkt_size, remaining, vlanf, curr_frag_len; | ||
| 764 | u16 i, rxq_idx = 0, vid; | ||
| 765 | |||
| 766 | num_rcvd = AMAP_GET_BITS(struct amap_eth_rx_compl, numfrags, rxcp); | ||
| 767 | pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl, pktsize, rxcp); | ||
| 768 | vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl, vtp, rxcp); | ||
| 769 | rxq_idx = AMAP_GET_BITS(struct amap_eth_rx_compl, fragndx, rxcp); | ||
| 770 | |||
| 771 | remaining = pkt_size; | ||
| 772 | for (i = 0; i < num_rcvd; i++) { | ||
| 773 | page_info = get_rx_page_info(adapter, rxq_idx); | ||
| 774 | |||
| 775 | curr_frag_len = min(remaining, rx_frag_size); | ||
| 776 | |||
| 777 | rx_frags[i].page = page_info->page; | ||
| 778 | rx_frags[i].page_offset = page_info->page_offset; | ||
| 779 | rx_frags[i].size = curr_frag_len; | ||
| 780 | remaining -= curr_frag_len; | ||
| 781 | |||
| 782 | index_inc(&rxq_idx, rxq->len); | ||
| 783 | |||
| 784 | memset(page_info, 0, sizeof(*page_info)); | ||
| 785 | } | ||
| 786 | |||
| 787 | if (likely(!vlanf)) { | ||
| 788 | lro_receive_frags(&adapter->rx_obj.lro_mgr, rx_frags, pkt_size, | ||
| 789 | pkt_size, NULL, 0); | ||
| 790 | } else { | ||
| 791 | vid = AMAP_GET_BITS(struct amap_eth_rx_compl, vlan_tag, rxcp); | ||
| 792 | vid = be16_to_cpu(vid); | ||
| 793 | |||
| 794 | if (!adapter->vlan_grp || adapter->num_vlans == 0) | ||
| 795 | return; | ||
| 796 | |||
| 797 | lro_vlan_hwaccel_receive_frags(&adapter->rx_obj.lro_mgr, | ||
| 798 | rx_frags, pkt_size, pkt_size, adapter->vlan_grp, | ||
| 799 | vid, NULL, 0); | ||
| 800 | } | ||
| 801 | |||
| 802 | be_rx_rate_update(adapter, pkt_size, num_rcvd); | ||
| 803 | return; | ||
| 804 | } | ||
| 805 | |||
| 806 | static struct be_eth_rx_compl *be_rx_compl_get(struct be_adapter *adapter) | ||
| 807 | { | ||
| 808 | struct be_eth_rx_compl *rxcp = queue_tail_node(&adapter->rx_obj.cq); | ||
| 809 | |||
| 810 | if (rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] == 0) | ||
| 811 | return NULL; | ||
| 812 | |||
| 813 | be_dws_le_to_cpu(rxcp, sizeof(*rxcp)); | ||
| 814 | |||
| 815 | rxcp->dw[offsetof(struct amap_eth_rx_compl, valid) / 32] = 0; | ||
| 816 | |||
| 817 | queue_tail_inc(&adapter->rx_obj.cq); | ||
| 818 | return rxcp; | ||
| 819 | } | ||
| 820 | |||
| 821 | static inline struct page *be_alloc_pages(u32 size) | ||
| 822 | { | ||
| 823 | gfp_t alloc_flags = GFP_ATOMIC; | ||
| 824 | u32 order = get_order(size); | ||
| 825 | if (order > 0) | ||
| 826 | alloc_flags |= __GFP_COMP; | ||
| 827 | return alloc_pages(alloc_flags, order); | ||
| 828 | } | ||
| 829 | |||
| 830 | /* | ||
| 831 | * Allocate a page, split it to fragments of size rx_frag_size and post as | ||
| 832 | * receive buffers to BE | ||
| 833 | */ | ||
| 834 | static void be_post_rx_frags(struct be_adapter *adapter) | ||
| 835 | { | ||
| 836 | struct be_rx_page_info *page_info_tbl = adapter->rx_obj.page_info_tbl; | ||
| 837 | struct be_rx_page_info *page_info = NULL; | ||
| 838 | struct be_queue_info *rxq = &adapter->rx_obj.q; | ||
| 839 | struct page *pagep = NULL; | ||
| 840 | struct be_eth_rx_d *rxd; | ||
| 841 | u64 page_dmaaddr = 0, frag_dmaaddr; | ||
| 842 | u32 posted, page_offset = 0; | ||
| 843 | |||
| 844 | |||
| 845 | page_info = &page_info_tbl[rxq->head]; | ||
| 846 | for (posted = 0; posted < MAX_RX_POST && !page_info->page; posted++) { | ||
| 847 | if (!pagep) { | ||
| 848 | pagep = be_alloc_pages(adapter->big_page_size); | ||
| 849 | if (unlikely(!pagep)) { | ||
| 850 | drvr_stats(adapter)->be_ethrx_post_fail++; | ||
| 851 | break; | ||
| 852 | } | ||
| 853 | page_dmaaddr = pci_map_page(adapter->pdev, pagep, 0, | ||
| 854 | adapter->big_page_size, | ||
| 855 | PCI_DMA_FROMDEVICE); | ||
| 856 | page_info->page_offset = 0; | ||
| 857 | } else { | ||
| 858 | get_page(pagep); | ||
| 859 | page_info->page_offset = page_offset + rx_frag_size; | ||
| 860 | } | ||
| 861 | page_offset = page_info->page_offset; | ||
| 862 | page_info->page = pagep; | ||
| 863 | pci_unmap_addr_set(page_info, bus, page_dmaaddr); | ||
| 864 | frag_dmaaddr = page_dmaaddr + page_info->page_offset; | ||
| 865 | |||
| 866 | rxd = queue_head_node(rxq); | ||
| 867 | rxd->fragpa_lo = cpu_to_le32(frag_dmaaddr & 0xFFFFFFFF); | ||
| 868 | rxd->fragpa_hi = cpu_to_le32(upper_32_bits(frag_dmaaddr)); | ||
| 869 | queue_head_inc(rxq); | ||
| 870 | |||
| 871 | /* Any space left in the current big page for another frag? */ | ||
| 872 | if ((page_offset + rx_frag_size + rx_frag_size) > | ||
| 873 | adapter->big_page_size) { | ||
| 874 | pagep = NULL; | ||
| 875 | page_info->last_page_user = true; | ||
| 876 | } | ||
| 877 | page_info = &page_info_tbl[rxq->head]; | ||
| 878 | } | ||
| 879 | if (pagep) | ||
| 880 | page_info->last_page_user = true; | ||
| 881 | |||
| 882 | if (posted) { | ||
| 883 | atomic_add(posted, &rxq->used); | ||
| 884 | be_rxq_notify(&adapter->ctrl, rxq->id, posted); | ||
| 885 | } else if (atomic_read(&rxq->used) == 0) { | ||
| 886 | /* Let be_worker replenish when memory is available */ | ||
| 887 | adapter->rx_post_starved = true; | ||
| 888 | } | ||
| 889 | |||
| 890 | return; | ||
| 891 | } | ||
| 892 | |||
| 893 | static struct be_eth_tx_compl * | ||
| 894 | be_tx_compl_get(struct be_adapter *adapter) | ||
| 895 | { | ||
| 896 | struct be_queue_info *tx_cq = &adapter->tx_obj.cq; | ||
| 897 | struct be_eth_tx_compl *txcp = queue_tail_node(tx_cq); | ||
| 898 | |||
| 899 | if (txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] == 0) | ||
| 900 | return NULL; | ||
| 901 | |||
| 902 | be_dws_le_to_cpu(txcp, sizeof(*txcp)); | ||
| 903 | |||
| 904 | txcp->dw[offsetof(struct amap_eth_tx_compl, valid) / 32] = 0; | ||
| 905 | |||
| 906 | queue_tail_inc(tx_cq); | ||
| 907 | return txcp; | ||
| 908 | } | ||
| 909 | |||
| 910 | static void be_tx_compl_process(struct be_adapter *adapter, u16 last_index) | ||
| 911 | { | ||
| 912 | struct be_queue_info *txq = &adapter->tx_obj.q; | ||
| 913 | struct be_eth_wrb *wrb; | ||
| 914 | struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list; | ||
| 915 | struct sk_buff *sent_skb; | ||
| 916 | u64 busaddr; | ||
| 917 | u16 cur_index, num_wrbs = 0; | ||
| 918 | |||
| 919 | cur_index = txq->tail; | ||
| 920 | sent_skb = sent_skbs[cur_index]; | ||
| 921 | BUG_ON(!sent_skb); | ||
| 922 | sent_skbs[cur_index] = NULL; | ||
| 923 | |||
| 924 | do { | ||
| 925 | cur_index = txq->tail; | ||
| 926 | wrb = queue_tail_node(txq); | ||
| 927 | be_dws_le_to_cpu(wrb, sizeof(*wrb)); | ||
| 928 | busaddr = ((u64)wrb->frag_pa_hi << 32) | (u64)wrb->frag_pa_lo; | ||
| 929 | if (busaddr != 0) { | ||
| 930 | pci_unmap_single(adapter->pdev, busaddr, | ||
| 931 | wrb->frag_len, PCI_DMA_TODEVICE); | ||
| 932 | } | ||
| 933 | num_wrbs++; | ||
| 934 | queue_tail_inc(txq); | ||
| 935 | } while (cur_index != last_index); | ||
| 936 | |||
| 937 | atomic_sub(num_wrbs, &txq->used); | ||
| 938 | |||
| 939 | kfree_skb(sent_skb); | ||
| 940 | } | ||
| 941 | |||
| 942 | static void be_rx_q_clean(struct be_adapter *adapter) | ||
| 943 | { | ||
| 944 | struct be_rx_page_info *page_info; | ||
| 945 | struct be_queue_info *rxq = &adapter->rx_obj.q; | ||
| 946 | struct be_queue_info *rx_cq = &adapter->rx_obj.cq; | ||
| 947 | struct be_eth_rx_compl *rxcp; | ||
| 948 | u16 tail; | ||
| 949 | |||
| 950 | /* First cleanup pending rx completions */ | ||
| 951 | while ((rxcp = be_rx_compl_get(adapter)) != NULL) { | ||
| 952 | be_rx_compl_discard(adapter, rxcp); | ||
| 953 | be_cq_notify(&adapter->ctrl, rx_cq->id, true, 1); | ||
| 954 | } | ||
| 955 | |||
| 956 | /* Then free posted rx buffer that were not used */ | ||
| 957 | tail = (rxq->head + rxq->len - atomic_read(&rxq->used)) % rxq->len; | ||
| 958 | for (; tail != rxq->head; index_inc(&tail, rxq->len)) { | ||
| 959 | page_info = get_rx_page_info(adapter, tail); | ||
| 960 | put_page(page_info->page); | ||
| 961 | memset(page_info, 0, sizeof(*page_info)); | ||
| 962 | } | ||
| 963 | BUG_ON(atomic_read(&rxq->used)); | ||
| 964 | } | ||
| 965 | |||
| 966 | static void be_tx_q_clean(struct be_adapter *adapter) | ||
| 967 | { | ||
| 968 | struct sk_buff **sent_skbs = adapter->tx_obj.sent_skb_list; | ||
| 969 | struct sk_buff *sent_skb; | ||
| 970 | struct be_queue_info *txq = &adapter->tx_obj.q; | ||
| 971 | u16 last_index; | ||
| 972 | bool dummy_wrb; | ||
| 973 | |||
| 974 | while (atomic_read(&txq->used)) { | ||
| 975 | sent_skb = sent_skbs[txq->tail]; | ||
| 976 | last_index = txq->tail; | ||
| 977 | index_adv(&last_index, | ||
| 978 | wrb_cnt_for_skb(sent_skb, &dummy_wrb) - 1, txq->len); | ||
| 979 | be_tx_compl_process(adapter, last_index); | ||
| 980 | } | ||
| 981 | } | ||
| 982 | |||
| 983 | static void be_tx_queues_destroy(struct be_adapter *adapter) | ||
| 984 | { | ||
| 985 | struct be_queue_info *q; | ||
| 986 | |||
| 987 | q = &adapter->tx_obj.q; | ||
| 988 | if (q->created) | ||
| 989 | be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_TXQ); | ||
| 990 | be_queue_free(adapter, q); | ||
| 991 | |||
| 992 | q = &adapter->tx_obj.cq; | ||
| 993 | if (q->created) | ||
| 994 | be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_CQ); | ||
| 995 | be_queue_free(adapter, q); | ||
| 996 | |||
| 997 | /* No more tx completions can be rcvd now; clean up if there are | ||
| 998 | * any pending completions or pending tx requests */ | ||
| 999 | be_tx_q_clean(adapter); | ||
| 1000 | |||
| 1001 | q = &adapter->tx_eq.q; | ||
| 1002 | if (q->created) | ||
| 1003 | be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_EQ); | ||
| 1004 | be_queue_free(adapter, q); | ||
| 1005 | } | ||
| 1006 | |||
| 1007 | static int be_tx_queues_create(struct be_adapter *adapter) | ||
| 1008 | { | ||
| 1009 | struct be_queue_info *eq, *q, *cq; | ||
| 1010 | |||
| 1011 | adapter->tx_eq.max_eqd = 0; | ||
| 1012 | adapter->tx_eq.min_eqd = 0; | ||
| 1013 | adapter->tx_eq.cur_eqd = 96; | ||
| 1014 | adapter->tx_eq.enable_aic = false; | ||
| 1015 | /* Alloc Tx Event queue */ | ||
| 1016 | eq = &adapter->tx_eq.q; | ||
| 1017 | if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, sizeof(struct be_eq_entry))) | ||
| 1018 | return -1; | ||
| 1019 | |||
| 1020 | /* Ask BE to create Tx Event queue */ | ||
| 1021 | if (be_cmd_eq_create(&adapter->ctrl, eq, adapter->tx_eq.cur_eqd)) | ||
| 1022 | goto tx_eq_free; | ||
| 1023 | /* Alloc TX eth compl queue */ | ||
| 1024 | cq = &adapter->tx_obj.cq; | ||
| 1025 | if (be_queue_alloc(adapter, cq, TX_CQ_LEN, | ||
| 1026 | sizeof(struct be_eth_tx_compl))) | ||
| 1027 | goto tx_eq_destroy; | ||
| 1028 | |||
| 1029 | /* Ask BE to create Tx eth compl queue */ | ||
| 1030 | if (be_cmd_cq_create(&adapter->ctrl, cq, eq, false, false, 3)) | ||
| 1031 | goto tx_cq_free; | ||
| 1032 | |||
| 1033 | /* Alloc TX eth queue */ | ||
| 1034 | q = &adapter->tx_obj.q; | ||
| 1035 | if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb))) | ||
| 1036 | goto tx_cq_destroy; | ||
| 1037 | |||
| 1038 | /* Ask BE to create Tx eth queue */ | ||
| 1039 | if (be_cmd_txq_create(&adapter->ctrl, q, cq)) | ||
| 1040 | goto tx_q_free; | ||
| 1041 | return 0; | ||
| 1042 | |||
| 1043 | tx_q_free: | ||
| 1044 | be_queue_free(adapter, q); | ||
| 1045 | tx_cq_destroy: | ||
| 1046 | be_cmd_q_destroy(&adapter->ctrl, cq, QTYPE_CQ); | ||
| 1047 | tx_cq_free: | ||
| 1048 | be_queue_free(adapter, cq); | ||
| 1049 | tx_eq_destroy: | ||
| 1050 | be_cmd_q_destroy(&adapter->ctrl, eq, QTYPE_EQ); | ||
| 1051 | tx_eq_free: | ||
| 1052 | be_queue_free(adapter, eq); | ||
| 1053 | return -1; | ||
| 1054 | } | ||
| 1055 | |||
| 1056 | static void be_rx_queues_destroy(struct be_adapter *adapter) | ||
| 1057 | { | ||
| 1058 | struct be_queue_info *q; | ||
| 1059 | |||
| 1060 | q = &adapter->rx_obj.q; | ||
| 1061 | if (q->created) { | ||
| 1062 | be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_RXQ); | ||
| 1063 | be_rx_q_clean(adapter); | ||
| 1064 | } | ||
| 1065 | be_queue_free(adapter, q); | ||
| 1066 | |||
| 1067 | q = &adapter->rx_obj.cq; | ||
| 1068 | if (q->created) | ||
| 1069 | be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_CQ); | ||
| 1070 | be_queue_free(adapter, q); | ||
| 1071 | |||
| 1072 | q = &adapter->rx_eq.q; | ||
| 1073 | if (q->created) | ||
| 1074 | be_cmd_q_destroy(&adapter->ctrl, q, QTYPE_EQ); | ||
| 1075 | be_queue_free(adapter, q); | ||
| 1076 | } | ||
| 1077 | |||
| 1078 | static int be_rx_queues_create(struct be_adapter *adapter) | ||
| 1079 | { | ||
| 1080 | struct be_queue_info *eq, *q, *cq; | ||
| 1081 | int rc; | ||
| 1082 | |||
| 1083 | adapter->max_rx_coal = BE_MAX_FRAGS_PER_FRAME; | ||
| 1084 | adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE; | ||
| 1085 | adapter->rx_eq.max_eqd = BE_MAX_EQD; | ||
| 1086 | adapter->rx_eq.min_eqd = 0; | ||
| 1087 | adapter->rx_eq.cur_eqd = 0; | ||
| 1088 | adapter->rx_eq.enable_aic = true; | ||
| 1089 | |||
| 1090 | /* Alloc Rx Event queue */ | ||
| 1091 | eq = &adapter->rx_eq.q; | ||
| 1092 | rc = be_queue_alloc(adapter, eq, EVNT_Q_LEN, | ||
| 1093 | sizeof(struct be_eq_entry)); | ||
| 1094 | if (rc) | ||
| 1095 | return rc; | ||
| 1096 | |||
| 1097 | /* Ask BE to create Rx Event queue */ | ||
| 1098 | rc = be_cmd_eq_create(&adapter->ctrl, eq, adapter->rx_eq.cur_eqd); | ||
| 1099 | if (rc) | ||
| 1100 | goto rx_eq_free; | ||
| 1101 | |||
| 1102 | /* Alloc RX eth compl queue */ | ||
| 1103 | cq = &adapter->rx_obj.cq; | ||
| 1104 | rc = be_queue_alloc(adapter, cq, RX_CQ_LEN, | ||
| 1105 | sizeof(struct be_eth_rx_compl)); | ||
| 1106 | if (rc) | ||
| 1107 | goto rx_eq_destroy; | ||
| 1108 | |||
| 1109 | /* Ask BE to create Rx eth compl queue */ | ||
| 1110 | rc = be_cmd_cq_create(&adapter->ctrl, cq, eq, false, false, 3); | ||
| 1111 | if (rc) | ||
| 1112 | goto rx_cq_free; | ||
| 1113 | |||
| 1114 | /* Alloc RX eth queue */ | ||
| 1115 | q = &adapter->rx_obj.q; | ||
| 1116 | rc = be_queue_alloc(adapter, q, RX_Q_LEN, sizeof(struct be_eth_rx_d)); | ||
| 1117 | if (rc) | ||
| 1118 | goto rx_cq_destroy; | ||
| 1119 | |||
| 1120 | /* Ask BE to create Rx eth queue */ | ||
| 1121 | rc = be_cmd_rxq_create(&adapter->ctrl, q, cq->id, rx_frag_size, | ||
| 1122 | BE_MAX_JUMBO_FRAME_SIZE, adapter->if_handle, false); | ||
| 1123 | if (rc) | ||
| 1124 | goto rx_q_free; | ||
| 1125 | |||
| 1126 | return 0; | ||
| 1127 | rx_q_free: | ||
| 1128 | be_queue_free(adapter, q); | ||
| 1129 | rx_cq_destroy: | ||
| 1130 | be_cmd_q_destroy(&adapter->ctrl, cq, QTYPE_CQ); | ||
| 1131 | rx_cq_free: | ||
| 1132 | be_queue_free(adapter, cq); | ||
| 1133 | rx_eq_destroy: | ||
| 1134 | be_cmd_q_destroy(&adapter->ctrl, eq, QTYPE_EQ); | ||
| 1135 | rx_eq_free: | ||
| 1136 | be_queue_free(adapter, eq); | ||
| 1137 | return rc; | ||
| 1138 | } | ||
| 1139 | static bool event_get(struct be_eq_obj *eq_obj, u16 *rid) | ||
| 1140 | { | ||
| 1141 | struct be_eq_entry *entry = queue_tail_node(&eq_obj->q); | ||
| 1142 | u32 evt = entry->evt; | ||
| 1143 | |||
| 1144 | if (!evt) | ||
| 1145 | return false; | ||
| 1146 | |||
| 1147 | evt = le32_to_cpu(evt); | ||
| 1148 | *rid = (evt >> EQ_ENTRY_RES_ID_SHIFT) & EQ_ENTRY_RES_ID_MASK; | ||
| 1149 | entry->evt = 0; | ||
| 1150 | queue_tail_inc(&eq_obj->q); | ||
| 1151 | return true; | ||
| 1152 | } | ||
| 1153 | |||
| 1154 | static int event_handle(struct be_ctrl_info *ctrl, | ||
| 1155 | struct be_eq_obj *eq_obj) | ||
| 1156 | { | ||
| 1157 | u16 rid = 0, num = 0; | ||
| 1158 | |||
| 1159 | while (event_get(eq_obj, &rid)) | ||
| 1160 | num++; | ||
| 1161 | |||
| 1162 | /* We can see an interrupt and no event */ | ||
| 1163 | be_eq_notify(ctrl, eq_obj->q.id, true, true, num); | ||
| 1164 | if (num) | ||
| 1165 | napi_schedule(&eq_obj->napi); | ||
| 1166 | |||
| 1167 | return num; | ||
| 1168 | } | ||
| 1169 | |||
| 1170 | static irqreturn_t be_intx(int irq, void *dev) | ||
| 1171 | { | ||
| 1172 | struct be_adapter *adapter = dev; | ||
| 1173 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 1174 | int rx, tx; | ||
| 1175 | |||
| 1176 | tx = event_handle(ctrl, &adapter->tx_eq); | ||
| 1177 | rx = event_handle(ctrl, &adapter->rx_eq); | ||
| 1178 | |||
| 1179 | if (rx || tx) | ||
| 1180 | return IRQ_HANDLED; | ||
| 1181 | else | ||
| 1182 | return IRQ_NONE; | ||
| 1183 | } | ||
| 1184 | |||
| 1185 | static irqreturn_t be_msix_rx(int irq, void *dev) | ||
| 1186 | { | ||
| 1187 | struct be_adapter *adapter = dev; | ||
| 1188 | |||
| 1189 | event_handle(&adapter->ctrl, &adapter->rx_eq); | ||
| 1190 | |||
| 1191 | return IRQ_HANDLED; | ||
| 1192 | } | ||
| 1193 | |||
| 1194 | static irqreturn_t be_msix_tx(int irq, void *dev) | ||
| 1195 | { | ||
| 1196 | struct be_adapter *adapter = dev; | ||
| 1197 | |||
| 1198 | event_handle(&adapter->ctrl, &adapter->tx_eq); | ||
| 1199 | |||
| 1200 | return IRQ_HANDLED; | ||
| 1201 | } | ||
| 1202 | |||
| 1203 | static inline bool do_lro(struct be_adapter *adapter, | ||
| 1204 | struct be_eth_rx_compl *rxcp) | ||
| 1205 | { | ||
| 1206 | int err = AMAP_GET_BITS(struct amap_eth_rx_compl, err, rxcp); | ||
| 1207 | int tcp_frame = AMAP_GET_BITS(struct amap_eth_rx_compl, tcpf, rxcp); | ||
| 1208 | |||
| 1209 | if (err) | ||
| 1210 | drvr_stats(adapter)->be_rxcp_err++; | ||
| 1211 | |||
| 1212 | return (!tcp_frame || err || (adapter->max_rx_coal <= 1)) ? | ||
| 1213 | false : true; | ||
| 1214 | } | ||
| 1215 | |||
| 1216 | int be_poll_rx(struct napi_struct *napi, int budget) | ||
| 1217 | { | ||
| 1218 | struct be_eq_obj *rx_eq = container_of(napi, struct be_eq_obj, napi); | ||
| 1219 | struct be_adapter *adapter = | ||
| 1220 | container_of(rx_eq, struct be_adapter, rx_eq); | ||
| 1221 | struct be_queue_info *rx_cq = &adapter->rx_obj.cq; | ||
| 1222 | struct be_eth_rx_compl *rxcp; | ||
| 1223 | u32 work_done; | ||
| 1224 | |||
| 1225 | for (work_done = 0; work_done < budget; work_done++) { | ||
| 1226 | rxcp = be_rx_compl_get(adapter); | ||
| 1227 | if (!rxcp) | ||
| 1228 | break; | ||
| 1229 | |||
| 1230 | if (do_lro(adapter, rxcp)) | ||
| 1231 | be_rx_compl_process_lro(adapter, rxcp); | ||
| 1232 | else | ||
| 1233 | be_rx_compl_process(adapter, rxcp); | ||
| 1234 | } | ||
| 1235 | |||
| 1236 | lro_flush_all(&adapter->rx_obj.lro_mgr); | ||
| 1237 | |||
| 1238 | /* Refill the queue */ | ||
| 1239 | if (atomic_read(&adapter->rx_obj.q.used) < RX_FRAGS_REFILL_WM) | ||
| 1240 | be_post_rx_frags(adapter); | ||
| 1241 | |||
| 1242 | /* All consumed */ | ||
| 1243 | if (work_done < budget) { | ||
| 1244 | napi_complete(napi); | ||
| 1245 | be_cq_notify(&adapter->ctrl, rx_cq->id, true, work_done); | ||
| 1246 | } else { | ||
| 1247 | /* More to be consumed; continue with interrupts disabled */ | ||
| 1248 | be_cq_notify(&adapter->ctrl, rx_cq->id, false, work_done); | ||
| 1249 | } | ||
| 1250 | return work_done; | ||
| 1251 | } | ||
| 1252 | |||
| 1253 | /* For TX we don't honour budget; consume everything */ | ||
| 1254 | int be_poll_tx(struct napi_struct *napi, int budget) | ||
| 1255 | { | ||
| 1256 | struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi); | ||
| 1257 | struct be_adapter *adapter = | ||
| 1258 | container_of(tx_eq, struct be_adapter, tx_eq); | ||
| 1259 | struct be_tx_obj *tx_obj = &adapter->tx_obj; | ||
| 1260 | struct be_queue_info *tx_cq = &tx_obj->cq; | ||
| 1261 | struct be_queue_info *txq = &tx_obj->q; | ||
| 1262 | struct be_eth_tx_compl *txcp; | ||
| 1263 | u32 num_cmpl = 0; | ||
| 1264 | u16 end_idx; | ||
| 1265 | |||
| 1266 | while ((txcp = be_tx_compl_get(adapter))) { | ||
| 1267 | end_idx = AMAP_GET_BITS(struct amap_eth_tx_compl, | ||
| 1268 | wrb_index, txcp); | ||
| 1269 | be_tx_compl_process(adapter, end_idx); | ||
| 1270 | num_cmpl++; | ||
| 1271 | } | ||
| 1272 | |||
| 1273 | /* As Tx wrbs have been freed up, wake up netdev queue if | ||
| 1274 | * it was stopped due to lack of tx wrbs. | ||
| 1275 | */ | ||
| 1276 | if (netif_queue_stopped(adapter->netdev) && | ||
| 1277 | atomic_read(&txq->used) < txq->len / 2) { | ||
| 1278 | netif_wake_queue(adapter->netdev); | ||
| 1279 | } | ||
| 1280 | |||
| 1281 | napi_complete(napi); | ||
| 1282 | |||
| 1283 | be_cq_notify(&adapter->ctrl, tx_cq->id, true, num_cmpl); | ||
| 1284 | |||
| 1285 | drvr_stats(adapter)->be_tx_events++; | ||
| 1286 | drvr_stats(adapter)->be_tx_compl += num_cmpl; | ||
| 1287 | |||
| 1288 | return 1; | ||
| 1289 | } | ||
| 1290 | |||
| 1291 | static void be_worker(struct work_struct *work) | ||
| 1292 | { | ||
| 1293 | struct be_adapter *adapter = | ||
| 1294 | container_of(work, struct be_adapter, work.work); | ||
| 1295 | int status; | ||
| 1296 | |||
| 1297 | /* Check link */ | ||
| 1298 | be_link_status_update(adapter); | ||
| 1299 | |||
| 1300 | /* Get Stats */ | ||
| 1301 | status = be_cmd_get_stats(&adapter->ctrl, &adapter->stats.cmd); | ||
| 1302 | if (!status) | ||
| 1303 | netdev_stats_update(adapter); | ||
| 1304 | |||
| 1305 | /* Set EQ delay */ | ||
| 1306 | be_rx_eqd_update(adapter); | ||
| 1307 | |||
| 1308 | if (adapter->rx_post_starved) { | ||
| 1309 | adapter->rx_post_starved = false; | ||
| 1310 | be_post_rx_frags(adapter); | ||
| 1311 | } | ||
| 1312 | |||
| 1313 | schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000)); | ||
| 1314 | } | ||
| 1315 | |||
| 1316 | static void be_msix_enable(struct be_adapter *adapter) | ||
| 1317 | { | ||
| 1318 | int i, status; | ||
| 1319 | |||
| 1320 | for (i = 0; i < BE_NUM_MSIX_VECTORS; i++) | ||
| 1321 | adapter->msix_entries[i].entry = i; | ||
| 1322 | |||
| 1323 | status = pci_enable_msix(adapter->pdev, adapter->msix_entries, | ||
| 1324 | BE_NUM_MSIX_VECTORS); | ||
| 1325 | if (status == 0) | ||
| 1326 | adapter->msix_enabled = true; | ||
| 1327 | return; | ||
| 1328 | } | ||
| 1329 | |||
| 1330 | static inline int be_msix_vec_get(struct be_adapter *adapter, u32 eq_id) | ||
| 1331 | { | ||
| 1332 | return adapter->msix_entries[eq_id - | ||
| 1333 | 8 * adapter->ctrl.pci_func].vector; | ||
| 1334 | } | ||
| 1335 | |||
| 1336 | static int be_msix_register(struct be_adapter *adapter) | ||
| 1337 | { | ||
| 1338 | struct net_device *netdev = adapter->netdev; | ||
| 1339 | struct be_eq_obj *tx_eq = &adapter->tx_eq; | ||
| 1340 | struct be_eq_obj *rx_eq = &adapter->rx_eq; | ||
| 1341 | int status, vec; | ||
| 1342 | |||
| 1343 | sprintf(tx_eq->desc, "%s-tx", netdev->name); | ||
| 1344 | vec = be_msix_vec_get(adapter, tx_eq->q.id); | ||
| 1345 | status = request_irq(vec, be_msix_tx, 0, tx_eq->desc, adapter); | ||
| 1346 | if (status) | ||
| 1347 | goto err; | ||
| 1348 | |||
| 1349 | sprintf(rx_eq->desc, "%s-rx", netdev->name); | ||
| 1350 | vec = be_msix_vec_get(adapter, rx_eq->q.id); | ||
| 1351 | status = request_irq(vec, be_msix_rx, 0, rx_eq->desc, adapter); | ||
| 1352 | if (status) { /* Free TX IRQ */ | ||
| 1353 | vec = be_msix_vec_get(adapter, tx_eq->q.id); | ||
| 1354 | free_irq(vec, adapter); | ||
| 1355 | goto err; | ||
| 1356 | } | ||
| 1357 | return 0; | ||
| 1358 | err: | ||
| 1359 | dev_warn(&adapter->pdev->dev, | ||
| 1360 | "MSIX Request IRQ failed - err %d\n", status); | ||
| 1361 | pci_disable_msix(adapter->pdev); | ||
| 1362 | adapter->msix_enabled = false; | ||
| 1363 | return status; | ||
| 1364 | } | ||
| 1365 | |||
| 1366 | static int be_irq_register(struct be_adapter *adapter) | ||
| 1367 | { | ||
| 1368 | struct net_device *netdev = adapter->netdev; | ||
| 1369 | int status; | ||
| 1370 | |||
| 1371 | if (adapter->msix_enabled) { | ||
| 1372 | status = be_msix_register(adapter); | ||
| 1373 | if (status == 0) | ||
| 1374 | goto done; | ||
| 1375 | } | ||
| 1376 | |||
| 1377 | /* INTx */ | ||
| 1378 | netdev->irq = adapter->pdev->irq; | ||
| 1379 | status = request_irq(netdev->irq, be_intx, IRQF_SHARED, netdev->name, | ||
| 1380 | adapter); | ||
| 1381 | if (status) { | ||
| 1382 | dev_err(&adapter->pdev->dev, | ||
| 1383 | "INTx request IRQ failed - err %d\n", status); | ||
| 1384 | return status; | ||
| 1385 | } | ||
| 1386 | done: | ||
| 1387 | adapter->isr_registered = true; | ||
| 1388 | return 0; | ||
| 1389 | } | ||
| 1390 | |||
| 1391 | static void be_irq_unregister(struct be_adapter *adapter) | ||
| 1392 | { | ||
| 1393 | struct net_device *netdev = adapter->netdev; | ||
| 1394 | int vec; | ||
| 1395 | |||
| 1396 | if (!adapter->isr_registered) | ||
| 1397 | return; | ||
| 1398 | |||
| 1399 | /* INTx */ | ||
| 1400 | if (!adapter->msix_enabled) { | ||
| 1401 | free_irq(netdev->irq, adapter); | ||
| 1402 | goto done; | ||
| 1403 | } | ||
| 1404 | |||
| 1405 | /* MSIx */ | ||
| 1406 | vec = be_msix_vec_get(adapter, adapter->tx_eq.q.id); | ||
| 1407 | free_irq(vec, adapter); | ||
| 1408 | vec = be_msix_vec_get(adapter, adapter->rx_eq.q.id); | ||
| 1409 | free_irq(vec, adapter); | ||
| 1410 | done: | ||
| 1411 | adapter->isr_registered = false; | ||
| 1412 | return; | ||
| 1413 | } | ||
| 1414 | |||
| 1415 | static int be_open(struct net_device *netdev) | ||
| 1416 | { | ||
| 1417 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 1418 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 1419 | struct be_eq_obj *rx_eq = &adapter->rx_eq; | ||
| 1420 | struct be_eq_obj *tx_eq = &adapter->tx_eq; | ||
| 1421 | u32 if_flags; | ||
| 1422 | int status; | ||
| 1423 | |||
| 1424 | if_flags = BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_PROMISCUOUS | | ||
| 1425 | BE_IF_FLAGS_MCAST_PROMISCUOUS | BE_IF_FLAGS_UNTAGGED | | ||
| 1426 | BE_IF_FLAGS_PASS_L3L4_ERRORS; | ||
| 1427 | status = be_cmd_if_create(ctrl, if_flags, netdev->dev_addr, | ||
| 1428 | false/* pmac_invalid */, &adapter->if_handle, | ||
| 1429 | &adapter->pmac_id); | ||
| 1430 | if (status != 0) | ||
| 1431 | goto do_none; | ||
| 1432 | |||
| 1433 | be_vid_config(netdev); | ||
| 1434 | |||
| 1435 | status = be_cmd_set_flow_control(ctrl, true, true); | ||
| 1436 | if (status != 0) | ||
| 1437 | goto if_destroy; | ||
| 1438 | |||
| 1439 | status = be_tx_queues_create(adapter); | ||
| 1440 | if (status != 0) | ||
| 1441 | goto if_destroy; | ||
| 1442 | |||
| 1443 | status = be_rx_queues_create(adapter); | ||
| 1444 | if (status != 0) | ||
| 1445 | goto tx_qs_destroy; | ||
| 1446 | |||
| 1447 | /* First time posting */ | ||
| 1448 | be_post_rx_frags(adapter); | ||
| 1449 | |||
| 1450 | napi_enable(&rx_eq->napi); | ||
| 1451 | napi_enable(&tx_eq->napi); | ||
| 1452 | |||
| 1453 | be_irq_register(adapter); | ||
| 1454 | |||
| 1455 | be_intr_set(ctrl, true); | ||
| 1456 | |||
| 1457 | /* The evt queues are created in the unarmed state; arm them */ | ||
| 1458 | be_eq_notify(ctrl, rx_eq->q.id, true, false, 0); | ||
| 1459 | be_eq_notify(ctrl, tx_eq->q.id, true, false, 0); | ||
| 1460 | |||
| 1461 | /* The compl queues are created in the unarmed state; arm them */ | ||
| 1462 | be_cq_notify(ctrl, adapter->rx_obj.cq.id, true, 0); | ||
| 1463 | be_cq_notify(ctrl, adapter->tx_obj.cq.id, true, 0); | ||
| 1464 | |||
| 1465 | be_link_status_update(adapter); | ||
| 1466 | |||
| 1467 | schedule_delayed_work(&adapter->work, msecs_to_jiffies(100)); | ||
| 1468 | return 0; | ||
| 1469 | |||
| 1470 | tx_qs_destroy: | ||
| 1471 | be_tx_queues_destroy(adapter); | ||
| 1472 | if_destroy: | ||
| 1473 | be_cmd_if_destroy(ctrl, adapter->if_handle); | ||
| 1474 | do_none: | ||
| 1475 | return status; | ||
| 1476 | } | ||
| 1477 | |||
| 1478 | static int be_close(struct net_device *netdev) | ||
| 1479 | { | ||
| 1480 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 1481 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 1482 | struct be_eq_obj *rx_eq = &adapter->rx_eq; | ||
| 1483 | struct be_eq_obj *tx_eq = &adapter->tx_eq; | ||
| 1484 | int vec; | ||
| 1485 | |||
| 1486 | cancel_delayed_work(&adapter->work); | ||
| 1487 | |||
| 1488 | netif_stop_queue(netdev); | ||
| 1489 | netif_carrier_off(netdev); | ||
| 1490 | adapter->link.speed = PHY_LINK_SPEED_ZERO; | ||
| 1491 | |||
| 1492 | be_intr_set(ctrl, false); | ||
| 1493 | |||
| 1494 | if (adapter->msix_enabled) { | ||
| 1495 | vec = be_msix_vec_get(adapter, tx_eq->q.id); | ||
| 1496 | synchronize_irq(vec); | ||
| 1497 | vec = be_msix_vec_get(adapter, rx_eq->q.id); | ||
| 1498 | synchronize_irq(vec); | ||
| 1499 | } else { | ||
| 1500 | synchronize_irq(netdev->irq); | ||
| 1501 | } | ||
| 1502 | be_irq_unregister(adapter); | ||
| 1503 | |||
| 1504 | napi_disable(&rx_eq->napi); | ||
| 1505 | napi_disable(&tx_eq->napi); | ||
| 1506 | |||
| 1507 | be_rx_queues_destroy(adapter); | ||
| 1508 | be_tx_queues_destroy(adapter); | ||
| 1509 | |||
| 1510 | be_cmd_if_destroy(ctrl, adapter->if_handle); | ||
| 1511 | return 0; | ||
| 1512 | } | ||
| 1513 | |||
| 1514 | static int be_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr, | ||
| 1515 | void **ip_hdr, void **tcpudp_hdr, | ||
| 1516 | u64 *hdr_flags, void *priv) | ||
| 1517 | { | ||
| 1518 | struct ethhdr *eh; | ||
| 1519 | struct vlan_ethhdr *veh; | ||
| 1520 | struct iphdr *iph; | ||
| 1521 | u8 *va = page_address(frag->page) + frag->page_offset; | ||
| 1522 | unsigned long ll_hlen; | ||
| 1523 | |||
| 1524 | prefetch(va); | ||
| 1525 | eh = (struct ethhdr *)va; | ||
| 1526 | *mac_hdr = eh; | ||
| 1527 | ll_hlen = ETH_HLEN; | ||
| 1528 | if (eh->h_proto != htons(ETH_P_IP)) { | ||
| 1529 | if (eh->h_proto == htons(ETH_P_8021Q)) { | ||
| 1530 | veh = (struct vlan_ethhdr *)va; | ||
| 1531 | if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP)) | ||
| 1532 | return -1; | ||
| 1533 | |||
| 1534 | ll_hlen += VLAN_HLEN; | ||
| 1535 | } else { | ||
| 1536 | return -1; | ||
| 1537 | } | ||
| 1538 | } | ||
| 1539 | *hdr_flags = LRO_IPV4; | ||
| 1540 | iph = (struct iphdr *)(va + ll_hlen); | ||
| 1541 | *ip_hdr = iph; | ||
| 1542 | if (iph->protocol != IPPROTO_TCP) | ||
| 1543 | return -1; | ||
| 1544 | *hdr_flags |= LRO_TCP; | ||
| 1545 | *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2); | ||
| 1546 | |||
| 1547 | return 0; | ||
| 1548 | } | ||
| 1549 | |||
| 1550 | static void be_lro_init(struct be_adapter *adapter, struct net_device *netdev) | ||
| 1551 | { | ||
| 1552 | struct net_lro_mgr *lro_mgr; | ||
| 1553 | |||
| 1554 | lro_mgr = &adapter->rx_obj.lro_mgr; | ||
| 1555 | lro_mgr->dev = netdev; | ||
| 1556 | lro_mgr->features = LRO_F_NAPI; | ||
| 1557 | lro_mgr->ip_summed = CHECKSUM_UNNECESSARY; | ||
| 1558 | lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY; | ||
| 1559 | lro_mgr->max_desc = BE_MAX_LRO_DESCRIPTORS; | ||
| 1560 | lro_mgr->lro_arr = adapter->rx_obj.lro_desc; | ||
| 1561 | lro_mgr->get_frag_header = be_get_frag_header; | ||
| 1562 | lro_mgr->max_aggr = BE_MAX_FRAGS_PER_FRAME; | ||
| 1563 | } | ||
| 1564 | |||
| 1565 | static struct net_device_ops be_netdev_ops = { | ||
| 1566 | .ndo_open = be_open, | ||
| 1567 | .ndo_stop = be_close, | ||
| 1568 | .ndo_start_xmit = be_xmit, | ||
| 1569 | .ndo_get_stats = be_get_stats, | ||
| 1570 | .ndo_set_rx_mode = be_set_multicast_list, | ||
| 1571 | .ndo_set_mac_address = be_mac_addr_set, | ||
| 1572 | .ndo_change_mtu = be_change_mtu, | ||
| 1573 | .ndo_validate_addr = eth_validate_addr, | ||
| 1574 | .ndo_vlan_rx_register = be_vlan_register, | ||
| 1575 | .ndo_vlan_rx_add_vid = be_vlan_add_vid, | ||
| 1576 | .ndo_vlan_rx_kill_vid = be_vlan_rem_vid, | ||
| 1577 | }; | ||
| 1578 | |||
| 1579 | static void be_netdev_init(struct net_device *netdev) | ||
| 1580 | { | ||
| 1581 | struct be_adapter *adapter = netdev_priv(netdev); | ||
| 1582 | |||
| 1583 | netdev->features |= NETIF_F_SG | NETIF_F_HW_VLAN_RX | NETIF_F_TSO | | ||
| 1584 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_IP_CSUM | | ||
| 1585 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6; | ||
| 1586 | |||
| 1587 | netdev->flags |= IFF_MULTICAST; | ||
| 1588 | |||
| 1589 | BE_SET_NETDEV_OPS(netdev, &be_netdev_ops); | ||
| 1590 | |||
| 1591 | SET_ETHTOOL_OPS(netdev, &be_ethtool_ops); | ||
| 1592 | |||
| 1593 | be_lro_init(adapter, netdev); | ||
| 1594 | |||
| 1595 | netif_napi_add(netdev, &adapter->rx_eq.napi, be_poll_rx, | ||
| 1596 | BE_NAPI_WEIGHT); | ||
| 1597 | netif_napi_add(netdev, &adapter->tx_eq.napi, be_poll_tx, | ||
| 1598 | BE_NAPI_WEIGHT); | ||
| 1599 | |||
| 1600 | netif_carrier_off(netdev); | ||
| 1601 | netif_stop_queue(netdev); | ||
| 1602 | } | ||
| 1603 | |||
| 1604 | static void be_unmap_pci_bars(struct be_adapter *adapter) | ||
| 1605 | { | ||
| 1606 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 1607 | if (ctrl->csr) | ||
| 1608 | iounmap(ctrl->csr); | ||
| 1609 | if (ctrl->db) | ||
| 1610 | iounmap(ctrl->db); | ||
| 1611 | if (ctrl->pcicfg) | ||
| 1612 | iounmap(ctrl->pcicfg); | ||
| 1613 | } | ||
| 1614 | |||
| 1615 | static int be_map_pci_bars(struct be_adapter *adapter) | ||
| 1616 | { | ||
| 1617 | u8 __iomem *addr; | ||
| 1618 | |||
| 1619 | addr = ioremap_nocache(pci_resource_start(adapter->pdev, 2), | ||
| 1620 | pci_resource_len(adapter->pdev, 2)); | ||
| 1621 | if (addr == NULL) | ||
| 1622 | return -ENOMEM; | ||
| 1623 | adapter->ctrl.csr = addr; | ||
| 1624 | |||
| 1625 | addr = ioremap_nocache(pci_resource_start(adapter->pdev, 4), | ||
| 1626 | 128 * 1024); | ||
| 1627 | if (addr == NULL) | ||
| 1628 | goto pci_map_err; | ||
| 1629 | adapter->ctrl.db = addr; | ||
| 1630 | |||
| 1631 | addr = ioremap_nocache(pci_resource_start(adapter->pdev, 1), | ||
| 1632 | pci_resource_len(adapter->pdev, 1)); | ||
| 1633 | if (addr == NULL) | ||
| 1634 | goto pci_map_err; | ||
| 1635 | adapter->ctrl.pcicfg = addr; | ||
| 1636 | |||
| 1637 | return 0; | ||
| 1638 | pci_map_err: | ||
| 1639 | be_unmap_pci_bars(adapter); | ||
| 1640 | return -ENOMEM; | ||
| 1641 | } | ||
| 1642 | |||
| 1643 | |||
| 1644 | static void be_ctrl_cleanup(struct be_adapter *adapter) | ||
| 1645 | { | ||
| 1646 | struct be_dma_mem *mem = &adapter->ctrl.mbox_mem_alloced; | ||
| 1647 | |||
| 1648 | be_unmap_pci_bars(adapter); | ||
| 1649 | |||
| 1650 | if (mem->va) | ||
| 1651 | pci_free_consistent(adapter->pdev, mem->size, | ||
| 1652 | mem->va, mem->dma); | ||
| 1653 | } | ||
| 1654 | |||
| 1655 | /* Initialize the mbox required to send cmds to BE */ | ||
| 1656 | static int be_ctrl_init(struct be_adapter *adapter) | ||
| 1657 | { | ||
| 1658 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 1659 | struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced; | ||
| 1660 | struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem; | ||
| 1661 | int status; | ||
| 1662 | u32 val; | ||
| 1663 | |||
| 1664 | status = be_map_pci_bars(adapter); | ||
| 1665 | if (status) | ||
| 1666 | return status; | ||
| 1667 | |||
| 1668 | mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16; | ||
| 1669 | mbox_mem_alloc->va = pci_alloc_consistent(adapter->pdev, | ||
| 1670 | mbox_mem_alloc->size, &mbox_mem_alloc->dma); | ||
| 1671 | if (!mbox_mem_alloc->va) { | ||
| 1672 | be_unmap_pci_bars(adapter); | ||
| 1673 | return -1; | ||
| 1674 | } | ||
| 1675 | mbox_mem_align->size = sizeof(struct be_mcc_mailbox); | ||
| 1676 | mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16); | ||
| 1677 | mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16); | ||
| 1678 | memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox)); | ||
| 1679 | spin_lock_init(&ctrl->cmd_lock); | ||
| 1680 | |||
| 1681 | val = ioread32(ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET); | ||
| 1682 | ctrl->pci_func = (val >> MEMBAR_CTRL_INT_CTRL_PFUNC_SHIFT) & | ||
| 1683 | MEMBAR_CTRL_INT_CTRL_PFUNC_MASK; | ||
| 1684 | return 0; | ||
| 1685 | } | ||
| 1686 | |||
| 1687 | static void be_stats_cleanup(struct be_adapter *adapter) | ||
| 1688 | { | ||
| 1689 | struct be_stats_obj *stats = &adapter->stats; | ||
| 1690 | struct be_dma_mem *cmd = &stats->cmd; | ||
| 1691 | |||
| 1692 | if (cmd->va) | ||
| 1693 | pci_free_consistent(adapter->pdev, cmd->size, | ||
| 1694 | cmd->va, cmd->dma); | ||
| 1695 | } | ||
| 1696 | |||
| 1697 | static int be_stats_init(struct be_adapter *adapter) | ||
| 1698 | { | ||
| 1699 | struct be_stats_obj *stats = &adapter->stats; | ||
| 1700 | struct be_dma_mem *cmd = &stats->cmd; | ||
| 1701 | |||
| 1702 | cmd->size = sizeof(struct be_cmd_req_get_stats); | ||
| 1703 | cmd->va = pci_alloc_consistent(adapter->pdev, cmd->size, &cmd->dma); | ||
| 1704 | if (cmd->va == NULL) | ||
| 1705 | return -1; | ||
| 1706 | return 0; | ||
| 1707 | } | ||
| 1708 | |||
| 1709 | static void __devexit be_remove(struct pci_dev *pdev) | ||
| 1710 | { | ||
| 1711 | struct be_adapter *adapter = pci_get_drvdata(pdev); | ||
| 1712 | if (!adapter) | ||
| 1713 | return; | ||
| 1714 | |||
| 1715 | unregister_netdev(adapter->netdev); | ||
| 1716 | |||
| 1717 | be_stats_cleanup(adapter); | ||
| 1718 | |||
| 1719 | be_ctrl_cleanup(adapter); | ||
| 1720 | |||
| 1721 | if (adapter->msix_enabled) { | ||
| 1722 | pci_disable_msix(adapter->pdev); | ||
| 1723 | adapter->msix_enabled = false; | ||
| 1724 | } | ||
| 1725 | |||
| 1726 | pci_set_drvdata(pdev, NULL); | ||
| 1727 | pci_release_regions(pdev); | ||
| 1728 | pci_disable_device(pdev); | ||
| 1729 | |||
| 1730 | free_netdev(adapter->netdev); | ||
| 1731 | } | ||
| 1732 | |||
| 1733 | static int be_hw_up(struct be_adapter *adapter) | ||
| 1734 | { | ||
| 1735 | struct be_ctrl_info *ctrl = &adapter->ctrl; | ||
| 1736 | int status; | ||
| 1737 | |||
| 1738 | status = be_cmd_POST(ctrl); | ||
| 1739 | if (status) | ||
| 1740 | return status; | ||
| 1741 | |||
| 1742 | status = be_cmd_get_fw_ver(ctrl, adapter->fw_ver); | ||
| 1743 | if (status) | ||
| 1744 | return status; | ||
| 1745 | |||
| 1746 | status = be_cmd_query_fw_cfg(ctrl, &adapter->port_num); | ||
| 1747 | return status; | ||
| 1748 | } | ||
| 1749 | |||
| 1750 | static int __devinit be_probe(struct pci_dev *pdev, | ||
| 1751 | const struct pci_device_id *pdev_id) | ||
| 1752 | { | ||
| 1753 | int status = 0; | ||
| 1754 | struct be_adapter *adapter; | ||
| 1755 | struct net_device *netdev; | ||
| 1756 | struct be_ctrl_info *ctrl; | ||
| 1757 | u8 mac[ETH_ALEN]; | ||
| 1758 | |||
| 1759 | status = pci_enable_device(pdev); | ||
| 1760 | if (status) | ||
| 1761 | goto do_none; | ||
| 1762 | |||
| 1763 | status = pci_request_regions(pdev, DRV_NAME); | ||
| 1764 | if (status) | ||
| 1765 | goto disable_dev; | ||
| 1766 | pci_set_master(pdev); | ||
| 1767 | |||
| 1768 | netdev = alloc_etherdev(sizeof(struct be_adapter)); | ||
| 1769 | if (netdev == NULL) { | ||
| 1770 | status = -ENOMEM; | ||
| 1771 | goto rel_reg; | ||
| 1772 | } | ||
| 1773 | adapter = netdev_priv(netdev); | ||
| 1774 | adapter->pdev = pdev; | ||
| 1775 | pci_set_drvdata(pdev, adapter); | ||
| 1776 | adapter->netdev = netdev; | ||
| 1777 | |||
| 1778 | be_msix_enable(adapter); | ||
| 1779 | |||
| 1780 | status = pci_set_dma_mask(pdev, DMA_64BIT_MASK); | ||
| 1781 | if (!status) { | ||
| 1782 | netdev->features |= NETIF_F_HIGHDMA; | ||
| 1783 | } else { | ||
| 1784 | status = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | ||
| 1785 | if (status) { | ||
| 1786 | dev_err(&pdev->dev, "Could not set PCI DMA Mask\n"); | ||
| 1787 | goto free_netdev; | ||
| 1788 | } | ||
| 1789 | } | ||
| 1790 | |||
| 1791 | ctrl = &adapter->ctrl; | ||
| 1792 | status = be_ctrl_init(adapter); | ||
| 1793 | if (status) | ||
| 1794 | goto free_netdev; | ||
| 1795 | |||
| 1796 | status = be_stats_init(adapter); | ||
| 1797 | if (status) | ||
| 1798 | goto ctrl_clean; | ||
| 1799 | |||
| 1800 | status = be_hw_up(adapter); | ||
| 1801 | if (status) | ||
| 1802 | goto stats_clean; | ||
| 1803 | |||
| 1804 | status = be_cmd_mac_addr_query(ctrl, mac, MAC_ADDRESS_TYPE_NETWORK, | ||
| 1805 | true /* permanent */, 0); | ||
| 1806 | if (status) | ||
| 1807 | goto stats_clean; | ||
| 1808 | memcpy(netdev->dev_addr, mac, ETH_ALEN); | ||
| 1809 | |||
| 1810 | INIT_DELAYED_WORK(&adapter->work, be_worker); | ||
| 1811 | be_netdev_init(netdev); | ||
| 1812 | SET_NETDEV_DEV(netdev, &adapter->pdev->dev); | ||
| 1813 | |||
| 1814 | status = register_netdev(netdev); | ||
| 1815 | if (status != 0) | ||
| 1816 | goto stats_clean; | ||
| 1817 | |||
| 1818 | dev_info(&pdev->dev, BE_NAME " port %d\n", adapter->port_num); | ||
| 1819 | return 0; | ||
| 1820 | |||
| 1821 | stats_clean: | ||
| 1822 | be_stats_cleanup(adapter); | ||
| 1823 | ctrl_clean: | ||
| 1824 | be_ctrl_cleanup(adapter); | ||
| 1825 | free_netdev: | ||
| 1826 | free_netdev(adapter->netdev); | ||
| 1827 | rel_reg: | ||
| 1828 | pci_release_regions(pdev); | ||
| 1829 | disable_dev: | ||
| 1830 | pci_disable_device(pdev); | ||
| 1831 | do_none: | ||
| 1832 | dev_warn(&pdev->dev, BE_NAME " initialization failed\n"); | ||
| 1833 | return status; | ||
| 1834 | } | ||
| 1835 | |||
| 1836 | static int be_suspend(struct pci_dev *pdev, pm_message_t state) | ||
| 1837 | { | ||
| 1838 | struct be_adapter *adapter = pci_get_drvdata(pdev); | ||
| 1839 | struct net_device *netdev = adapter->netdev; | ||
| 1840 | |||
| 1841 | netif_device_detach(netdev); | ||
| 1842 | if (netif_running(netdev)) { | ||
| 1843 | rtnl_lock(); | ||
| 1844 | be_close(netdev); | ||
| 1845 | rtnl_unlock(); | ||
| 1846 | } | ||
| 1847 | |||
| 1848 | pci_save_state(pdev); | ||
| 1849 | pci_disable_device(pdev); | ||
| 1850 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | ||
| 1851 | return 0; | ||
| 1852 | } | ||
| 1853 | |||
| 1854 | static int be_resume(struct pci_dev *pdev) | ||
| 1855 | { | ||
| 1856 | int status = 0; | ||
| 1857 | struct be_adapter *adapter = pci_get_drvdata(pdev); | ||
| 1858 | struct net_device *netdev = adapter->netdev; | ||
| 1859 | |||
| 1860 | netif_device_detach(netdev); | ||
| 1861 | |||
| 1862 | status = pci_enable_device(pdev); | ||
| 1863 | if (status) | ||
| 1864 | return status; | ||
| 1865 | |||
| 1866 | pci_set_power_state(pdev, 0); | ||
| 1867 | pci_restore_state(pdev); | ||
| 1868 | |||
| 1869 | if (netif_running(netdev)) { | ||
| 1870 | rtnl_lock(); | ||
| 1871 | be_open(netdev); | ||
| 1872 | rtnl_unlock(); | ||
| 1873 | } | ||
| 1874 | netif_device_attach(netdev); | ||
| 1875 | return 0; | ||
| 1876 | } | ||
| 1877 | |||
| 1878 | static struct pci_driver be_driver = { | ||
| 1879 | .name = DRV_NAME, | ||
| 1880 | .id_table = be_dev_ids, | ||
| 1881 | .probe = be_probe, | ||
| 1882 | .remove = be_remove, | ||
| 1883 | .suspend = be_suspend, | ||
| 1884 | .resume = be_resume | ||
| 1885 | }; | ||
| 1886 | |||
| 1887 | static int __init be_init_module(void) | ||
| 1888 | { | ||
| 1889 | if (rx_frag_size != 8192 && rx_frag_size != 4096 | ||
| 1890 | && rx_frag_size != 2048) { | ||
| 1891 | printk(KERN_WARNING DRV_NAME | ||
| 1892 | " : Module param rx_frag_size must be 2048/4096/8192." | ||
| 1893 | " Using 2048\n"); | ||
| 1894 | rx_frag_size = 2048; | ||
| 1895 | } | ||
| 1896 | /* Ensure rx_frag_size is aligned to chache line */ | ||
| 1897 | if (SKB_DATA_ALIGN(rx_frag_size) != rx_frag_size) { | ||
| 1898 | printk(KERN_WARNING DRV_NAME | ||
| 1899 | " : Bad module param rx_frag_size. Using 2048\n"); | ||
| 1900 | rx_frag_size = 2048; | ||
| 1901 | } | ||
| 1902 | |||
| 1903 | return pci_register_driver(&be_driver); | ||
| 1904 | } | ||
| 1905 | module_init(be_init_module); | ||
| 1906 | |||
| 1907 | static void __exit be_exit_module(void) | ||
| 1908 | { | ||
| 1909 | pci_unregister_driver(&be_driver); | ||
| 1910 | } | ||
| 1911 | module_exit(be_exit_module); | ||
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c index 6500b7c4739f..6b6530ffdf19 100644 --- a/drivers/net/bnx2.c +++ b/drivers/net/bnx2.c | |||
| @@ -57,8 +57,8 @@ | |||
| 57 | 57 | ||
| 58 | #define DRV_MODULE_NAME "bnx2" | 58 | #define DRV_MODULE_NAME "bnx2" |
| 59 | #define PFX DRV_MODULE_NAME ": " | 59 | #define PFX DRV_MODULE_NAME ": " |
| 60 | #define DRV_MODULE_VERSION "1.9.2" | 60 | #define DRV_MODULE_VERSION "1.9.3" |
| 61 | #define DRV_MODULE_RELDATE "Feb 11, 2009" | 61 | #define DRV_MODULE_RELDATE "March 17, 2009" |
| 62 | 62 | ||
| 63 | #define RUN_AT(x) (jiffies + (x)) | 63 | #define RUN_AT(x) (jiffies + (x)) |
| 64 | 64 | ||
| @@ -5843,9 +5843,6 @@ bnx2_enable_msix(struct bnx2 *bp, int msix_vecs) | |||
| 5843 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { | 5843 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { |
| 5844 | msix_ent[i].entry = i; | 5844 | msix_ent[i].entry = i; |
| 5845 | msix_ent[i].vector = 0; | 5845 | msix_ent[i].vector = 0; |
| 5846 | |||
| 5847 | snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i); | ||
| 5848 | bp->irq_tbl[i].handler = bnx2_msi_1shot; | ||
| 5849 | } | 5846 | } |
| 5850 | 5847 | ||
| 5851 | rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC); | 5848 | rc = pci_enable_msix(bp->pdev, msix_ent, BNX2_MAX_MSIX_VEC); |
| @@ -5854,8 +5851,11 @@ bnx2_enable_msix(struct bnx2 *bp, int msix_vecs) | |||
| 5854 | 5851 | ||
| 5855 | bp->irq_nvecs = msix_vecs; | 5852 | bp->irq_nvecs = msix_vecs; |
| 5856 | bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI; | 5853 | bp->flags |= BNX2_FLAG_USING_MSIX | BNX2_FLAG_ONE_SHOT_MSI; |
| 5857 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) | 5854 | for (i = 0; i < BNX2_MAX_MSIX_VEC; i++) { |
| 5858 | bp->irq_tbl[i].vector = msix_ent[i].vector; | 5855 | bp->irq_tbl[i].vector = msix_ent[i].vector; |
| 5856 | snprintf(bp->irq_tbl[i].name, len, "%s-%d", dev->name, i); | ||
| 5857 | bp->irq_tbl[i].handler = bnx2_msi_1shot; | ||
| 5858 | } | ||
| 5859 | } | 5859 | } |
| 5860 | 5860 | ||
| 5861 | static void | 5861 | static void |
diff --git a/drivers/net/bnx2x.h b/drivers/net/bnx2x.h index 15a5cf0f676b..3cf2b92eef3b 100644 --- a/drivers/net/bnx2x.h +++ b/drivers/net/bnx2x.h | |||
| @@ -152,7 +152,7 @@ struct sw_rx_page { | |||
| 152 | #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) | 152 | #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) |
| 153 | #define SGE_PAGE_SIZE PAGE_SIZE | 153 | #define SGE_PAGE_SIZE PAGE_SIZE |
| 154 | #define SGE_PAGE_SHIFT PAGE_SHIFT | 154 | #define SGE_PAGE_SHIFT PAGE_SHIFT |
| 155 | #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN(addr) | 155 | #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))addr) |
| 156 | 156 | ||
| 157 | #define BCM_RX_ETH_PAYLOAD_ALIGN 64 | 157 | #define BCM_RX_ETH_PAYLOAD_ALIGN 64 |
| 158 | 158 | ||
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h index a6c0b3abba29..3b0c2499ef17 100644 --- a/drivers/net/bnx2x_init.h +++ b/drivers/net/bnx2x_init.h | |||
| @@ -150,7 +150,6 @@ static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr, const u32 *data, | |||
| 150 | 150 | ||
| 151 | static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len) | 151 | static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len) |
| 152 | { | 152 | { |
| 153 | #ifdef USE_DMAE | ||
| 154 | int offset = 0; | 153 | int offset = 0; |
| 155 | 154 | ||
| 156 | if (bp->dmae_ready) { | 155 | if (bp->dmae_ready) { |
| @@ -164,9 +163,6 @@ static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len) | |||
| 164 | addr + offset, len); | 163 | addr + offset, len); |
| 165 | } else | 164 | } else |
| 166 | bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len); | 165 | bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len); |
| 167 | #else | ||
| 168 | bnx2x_init_str_wr(bp, addr, bp->gunzip_buf, len); | ||
| 169 | #endif | ||
| 170 | } | 166 | } |
| 171 | 167 | ||
| 172 | static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) | 168 | static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill, u32 len) |
diff --git a/drivers/net/bnx2x_main.c b/drivers/net/bnx2x_main.c index d3e7775a9ccf..2e346a5e98cf 100644 --- a/drivers/net/bnx2x_main.c +++ b/drivers/net/bnx2x_main.c | |||
| @@ -57,7 +57,7 @@ | |||
| 57 | #include "bnx2x.h" | 57 | #include "bnx2x.h" |
| 58 | #include "bnx2x_init.h" | 58 | #include "bnx2x_init.h" |
| 59 | 59 | ||
| 60 | #define DRV_MODULE_VERSION "1.45.26" | 60 | #define DRV_MODULE_VERSION "1.45.27" |
| 61 | #define DRV_MODULE_RELDATE "2009/01/26" | 61 | #define DRV_MODULE_RELDATE "2009/01/26" |
| 62 | #define BNX2X_BC_VER 0x040200 | 62 | #define BNX2X_BC_VER 0x040200 |
| 63 | 63 | ||
| @@ -4035,10 +4035,10 @@ static void bnx2x_zero_sb(struct bnx2x *bp, int sb_id) | |||
| 4035 | { | 4035 | { |
| 4036 | int port = BP_PORT(bp); | 4036 | int port = BP_PORT(bp); |
| 4037 | 4037 | ||
| 4038 | bnx2x_init_fill(bp, BAR_USTRORM_INTMEM + | 4038 | bnx2x_init_fill(bp, USTORM_INTMEM_ADDR + |
| 4039 | USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, | 4039 | USTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, |
| 4040 | sizeof(struct ustorm_status_block)/4); | 4040 | sizeof(struct ustorm_status_block)/4); |
| 4041 | bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM + | 4041 | bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR + |
| 4042 | CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, | 4042 | CSTORM_SB_HOST_STATUS_BLOCK_OFFSET(port, sb_id), 0, |
| 4043 | sizeof(struct cstorm_status_block)/4); | 4043 | sizeof(struct cstorm_status_block)/4); |
| 4044 | } | 4044 | } |
| @@ -4092,18 +4092,18 @@ static void bnx2x_zero_def_sb(struct bnx2x *bp) | |||
| 4092 | { | 4092 | { |
| 4093 | int func = BP_FUNC(bp); | 4093 | int func = BP_FUNC(bp); |
| 4094 | 4094 | ||
| 4095 | bnx2x_init_fill(bp, BAR_USTRORM_INTMEM + | 4095 | bnx2x_init_fill(bp, TSTORM_INTMEM_ADDR + |
| 4096 | TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, | ||
| 4097 | sizeof(struct tstorm_def_status_block)/4); | ||
| 4098 | bnx2x_init_fill(bp, USTORM_INTMEM_ADDR + | ||
| 4096 | USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, | 4099 | USTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, |
| 4097 | sizeof(struct ustorm_def_status_block)/4); | 4100 | sizeof(struct ustorm_def_status_block)/4); |
| 4098 | bnx2x_init_fill(bp, BAR_CSTRORM_INTMEM + | 4101 | bnx2x_init_fill(bp, CSTORM_INTMEM_ADDR + |
| 4099 | CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, | 4102 | CSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, |
| 4100 | sizeof(struct cstorm_def_status_block)/4); | 4103 | sizeof(struct cstorm_def_status_block)/4); |
| 4101 | bnx2x_init_fill(bp, BAR_XSTRORM_INTMEM + | 4104 | bnx2x_init_fill(bp, XSTORM_INTMEM_ADDR + |
| 4102 | XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, | 4105 | XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, |
| 4103 | sizeof(struct xstorm_def_status_block)/4); | 4106 | sizeof(struct xstorm_def_status_block)/4); |
| 4104 | bnx2x_init_fill(bp, BAR_TSTRORM_INTMEM + | ||
| 4105 | TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0, | ||
| 4106 | sizeof(struct tstorm_def_status_block)/4); | ||
| 4107 | } | 4107 | } |
| 4108 | 4108 | ||
| 4109 | static void bnx2x_init_def_sb(struct bnx2x *bp, | 4109 | static void bnx2x_init_def_sb(struct bnx2x *bp, |
| @@ -4518,7 +4518,8 @@ static void bnx2x_init_context(struct bnx2x *bp) | |||
| 4518 | (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA | | 4518 | (USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA | |
| 4519 | USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING); | 4519 | USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_SGE_RING); |
| 4520 | context->ustorm_st_context.common.sge_buff_size = | 4520 | context->ustorm_st_context.common.sge_buff_size = |
| 4521 | (u16)(BCM_PAGE_SIZE*PAGES_PER_SGE); | 4521 | (u16)min((u32)SGE_PAGE_SIZE*PAGES_PER_SGE, |
| 4522 | (u32)0xffff); | ||
| 4522 | context->ustorm_st_context.common.sge_page_base_hi = | 4523 | context->ustorm_st_context.common.sge_page_base_hi = |
| 4523 | U64_HI(fp->rx_sge_mapping); | 4524 | U64_HI(fp->rx_sge_mapping); |
| 4524 | context->ustorm_st_context.common.sge_page_base_lo = | 4525 | context->ustorm_st_context.common.sge_page_base_lo = |
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c index 9fb388388fb7..3d76686dceca 100644 --- a/drivers/net/bonding/bond_main.c +++ b/drivers/net/bonding/bond_main.c | |||
| @@ -3537,11 +3537,26 @@ static int bond_slave_netdev_event(unsigned long event, struct net_device *slave | |||
| 3537 | } | 3537 | } |
| 3538 | break; | 3538 | break; |
| 3539 | case NETDEV_CHANGE: | 3539 | case NETDEV_CHANGE: |
| 3540 | /* | 3540 | if (bond->params.mode == BOND_MODE_8023AD || bond_is_lb(bond)) { |
| 3541 | * TODO: is this what we get if somebody | 3541 | struct slave *slave; |
| 3542 | * sets up a hierarchical bond, then rmmod's | 3542 | |
| 3543 | * one of the slave bonding devices? | 3543 | slave = bond_get_slave_by_dev(bond, slave_dev); |
| 3544 | */ | 3544 | if (slave) { |
| 3545 | u16 old_speed = slave->speed; | ||
| 3546 | u16 old_duplex = slave->duplex; | ||
| 3547 | |||
| 3548 | bond_update_speed_duplex(slave); | ||
| 3549 | |||
| 3550 | if (bond_is_lb(bond)) | ||
| 3551 | break; | ||
| 3552 | |||
| 3553 | if (old_speed != slave->speed) | ||
| 3554 | bond_3ad_adapter_speed_changed(slave); | ||
| 3555 | if (old_duplex != slave->duplex) | ||
| 3556 | bond_3ad_adapter_duplex_changed(slave); | ||
| 3557 | } | ||
| 3558 | } | ||
| 3559 | |||
| 3545 | break; | 3560 | break; |
| 3546 | case NETDEV_DOWN: | 3561 | case NETDEV_DOWN: |
| 3547 | /* | 3562 | /* |
| @@ -4113,7 +4128,7 @@ static int bond_neigh_setup(struct net_device *dev, struct neigh_parms *parms) | |||
| 4113 | const struct net_device_ops *slave_ops | 4128 | const struct net_device_ops *slave_ops |
| 4114 | = slave->dev->netdev_ops; | 4129 | = slave->dev->netdev_ops; |
| 4115 | if (slave_ops->ndo_neigh_setup) | 4130 | if (slave_ops->ndo_neigh_setup) |
| 4116 | return slave_ops->ndo_neigh_setup(dev, parms); | 4131 | return slave_ops->ndo_neigh_setup(slave->dev, parms); |
| 4117 | } | 4132 | } |
| 4118 | return 0; | 4133 | return 0; |
| 4119 | } | 4134 | } |
diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c index bcf92917bbf3..254ec62b5f58 100644 --- a/drivers/net/dm9000.c +++ b/drivers/net/dm9000.c | |||
| @@ -930,13 +930,15 @@ static irqreturn_t dm9000_interrupt(int irq, void *dev_id) | |||
| 930 | struct net_device *dev = dev_id; | 930 | struct net_device *dev = dev_id; |
| 931 | board_info_t *db = netdev_priv(dev); | 931 | board_info_t *db = netdev_priv(dev); |
| 932 | int int_status; | 932 | int int_status; |
| 933 | unsigned long flags; | ||
| 933 | u8 reg_save; | 934 | u8 reg_save; |
| 934 | 935 | ||
| 935 | dm9000_dbg(db, 3, "entering %s\n", __func__); | 936 | dm9000_dbg(db, 3, "entering %s\n", __func__); |
| 936 | 937 | ||
| 937 | /* A real interrupt coming */ | 938 | /* A real interrupt coming */ |
| 938 | 939 | ||
| 939 | spin_lock(&db->lock); | 940 | /* holders of db->lock must always block IRQs */ |
| 941 | spin_lock_irqsave(&db->lock, flags); | ||
| 940 | 942 | ||
| 941 | /* Save previous register address */ | 943 | /* Save previous register address */ |
| 942 | reg_save = readb(db->io_addr); | 944 | reg_save = readb(db->io_addr); |
| @@ -972,7 +974,7 @@ static irqreturn_t dm9000_interrupt(int irq, void *dev_id) | |||
| 972 | /* Restore previous register address */ | 974 | /* Restore previous register address */ |
| 973 | writeb(reg_save, db->io_addr); | 975 | writeb(reg_save, db->io_addr); |
| 974 | 976 | ||
| 975 | spin_unlock(&db->lock); | 977 | spin_unlock_irqrestore(&db->lock, flags); |
| 976 | 978 | ||
| 977 | return IRQ_HANDLED; | 979 | return IRQ_HANDLED; |
| 978 | } | 980 | } |
diff --git a/drivers/net/dnet.c b/drivers/net/dnet.c new file mode 100644 index 000000000000..1b4063222a82 --- /dev/null +++ b/drivers/net/dnet.c | |||
| @@ -0,0 +1,994 @@ | |||
| 1 | /* | ||
| 2 | * Dave DNET Ethernet Controller driver | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 Dave S.r.l. <www.dave.eu> | ||
| 5 | * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com> | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License version 2 as | ||
| 9 | * published by the Free Software Foundation. | ||
| 10 | */ | ||
| 11 | #include <linux/version.h> | ||
| 12 | #include <linux/module.h> | ||
| 13 | #include <linux/moduleparam.h> | ||
| 14 | #include <linux/kernel.h> | ||
| 15 | #include <linux/types.h> | ||
| 16 | #include <linux/slab.h> | ||
| 17 | #include <linux/delay.h> | ||
| 18 | #include <linux/init.h> | ||
| 19 | #include <linux/netdevice.h> | ||
| 20 | #include <linux/etherdevice.h> | ||
| 21 | #include <linux/dma-mapping.h> | ||
| 22 | #include <linux/platform_device.h> | ||
| 23 | #include <linux/phy.h> | ||
| 24 | #include <linux/platform_device.h> | ||
| 25 | |||
| 26 | #include "dnet.h" | ||
| 27 | |||
| 28 | #undef DEBUG | ||
| 29 | |||
| 30 | /* function for reading internal MAC register */ | ||
| 31 | u16 dnet_readw_mac(struct dnet *bp, u16 reg) | ||
| 32 | { | ||
| 33 | u16 data_read; | ||
| 34 | |||
| 35 | /* issue a read */ | ||
| 36 | dnet_writel(bp, reg, MACREG_ADDR); | ||
| 37 | |||
| 38 | /* since a read/write op to the MAC is very slow, | ||
| 39 | * we must wait before reading the data */ | ||
| 40 | ndelay(500); | ||
| 41 | |||
| 42 | /* read data read from the MAC register */ | ||
| 43 | data_read = dnet_readl(bp, MACREG_DATA); | ||
| 44 | |||
| 45 | /* all done */ | ||
| 46 | return data_read; | ||
| 47 | } | ||
| 48 | |||
| 49 | /* function for writing internal MAC register */ | ||
| 50 | void dnet_writew_mac(struct dnet *bp, u16 reg, u16 val) | ||
| 51 | { | ||
| 52 | /* load data to write */ | ||
| 53 | dnet_writel(bp, val, MACREG_DATA); | ||
| 54 | |||
| 55 | /* issue a write */ | ||
| 56 | dnet_writel(bp, reg | DNET_INTERNAL_WRITE, MACREG_ADDR); | ||
| 57 | |||
| 58 | /* since a read/write op to the MAC is very slow, | ||
| 59 | * we must wait before exiting */ | ||
| 60 | ndelay(500); | ||
| 61 | } | ||
| 62 | |||
| 63 | static void __dnet_set_hwaddr(struct dnet *bp) | ||
| 64 | { | ||
| 65 | u16 tmp; | ||
| 66 | |||
| 67 | tmp = cpu_to_be16(*((u16 *) bp->dev->dev_addr)); | ||
| 68 | dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG, tmp); | ||
| 69 | tmp = cpu_to_be16(*((u16 *) (bp->dev->dev_addr + 2))); | ||
| 70 | dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG, tmp); | ||
| 71 | tmp = cpu_to_be16(*((u16 *) (bp->dev->dev_addr + 4))); | ||
| 72 | dnet_writew_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG, tmp); | ||
| 73 | } | ||
| 74 | |||
| 75 | static void __devinit dnet_get_hwaddr(struct dnet *bp) | ||
| 76 | { | ||
| 77 | u16 tmp; | ||
| 78 | u8 addr[6]; | ||
| 79 | |||
| 80 | /* | ||
| 81 | * from MAC docs: | ||
| 82 | * "Note that the MAC address is stored in the registers in Hexadecimal | ||
| 83 | * form. For example, to set the MAC Address to: AC-DE-48-00-00-80 | ||
| 84 | * would require writing 0xAC (octet 0) to address 0x0B (high byte of | ||
| 85 | * Mac_addr[15:0]), 0xDE (octet 1) to address 0x0A (Low byte of | ||
| 86 | * Mac_addr[15:0]), 0x48 (octet 2) to address 0x0D (high byte of | ||
| 87 | * Mac_addr[15:0]), 0x00 (octet 3) to address 0x0C (Low byte of | ||
| 88 | * Mac_addr[15:0]), 0x00 (octet 4) to address 0x0F (high byte of | ||
| 89 | * Mac_addr[15:0]), and 0x80 (octet 5) to address * 0x0E (Low byte of | ||
| 90 | * Mac_addr[15:0]). | ||
| 91 | */ | ||
| 92 | tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_0_REG); | ||
| 93 | *((u16 *) addr) = be16_to_cpu(tmp); | ||
| 94 | tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_1_REG); | ||
| 95 | *((u16 *) (addr + 2)) = be16_to_cpu(tmp); | ||
| 96 | tmp = dnet_readw_mac(bp, DNET_INTERNAL_MAC_ADDR_2_REG); | ||
| 97 | *((u16 *) (addr + 4)) = be16_to_cpu(tmp); | ||
| 98 | |||
| 99 | if (is_valid_ether_addr(addr)) | ||
| 100 | memcpy(bp->dev->dev_addr, addr, sizeof(addr)); | ||
| 101 | } | ||
| 102 | |||
| 103 | static int dnet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) | ||
| 104 | { | ||
| 105 | struct dnet *bp = bus->priv; | ||
| 106 | u16 value; | ||
| 107 | |||
| 108 | while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) | ||
| 109 | & DNET_INTERNAL_GMII_MNG_CMD_FIN)) | ||
| 110 | cpu_relax(); | ||
| 111 | |||
| 112 | /* only 5 bits allowed for phy-addr and reg_offset */ | ||
| 113 | mii_id &= 0x1f; | ||
| 114 | regnum &= 0x1f; | ||
| 115 | |||
| 116 | /* prepare reg_value for a read */ | ||
| 117 | value = (mii_id << 8); | ||
| 118 | value |= regnum; | ||
| 119 | |||
| 120 | /* write control word */ | ||
| 121 | dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, value); | ||
| 122 | |||
| 123 | /* wait for end of transfer */ | ||
| 124 | while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) | ||
| 125 | & DNET_INTERNAL_GMII_MNG_CMD_FIN)) | ||
| 126 | cpu_relax(); | ||
| 127 | |||
| 128 | value = dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG); | ||
| 129 | |||
| 130 | pr_debug("mdio_read %02x:%02x <- %04x\n", mii_id, regnum, value); | ||
| 131 | |||
| 132 | return value; | ||
| 133 | } | ||
| 134 | |||
| 135 | static int dnet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, | ||
| 136 | u16 value) | ||
| 137 | { | ||
| 138 | struct dnet *bp = bus->priv; | ||
| 139 | u16 tmp; | ||
| 140 | |||
| 141 | pr_debug("mdio_write %02x:%02x <- %04x\n", mii_id, regnum, value); | ||
| 142 | |||
| 143 | while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) | ||
| 144 | & DNET_INTERNAL_GMII_MNG_CMD_FIN)) | ||
| 145 | cpu_relax(); | ||
| 146 | |||
| 147 | /* prepare for a write operation */ | ||
| 148 | tmp = (1 << 13); | ||
| 149 | |||
| 150 | /* only 5 bits allowed for phy-addr and reg_offset */ | ||
| 151 | mii_id &= 0x1f; | ||
| 152 | regnum &= 0x1f; | ||
| 153 | |||
| 154 | /* only 16 bits on data */ | ||
| 155 | value &= 0xffff; | ||
| 156 | |||
| 157 | /* prepare reg_value for a write */ | ||
| 158 | tmp |= (mii_id << 8); | ||
| 159 | tmp |= regnum; | ||
| 160 | |||
| 161 | /* write data to write first */ | ||
| 162 | dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_DAT_REG, value); | ||
| 163 | |||
| 164 | /* write control word */ | ||
| 165 | dnet_writew_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp); | ||
| 166 | |||
| 167 | while (!(dnet_readw_mac(bp, DNET_INTERNAL_GMII_MNG_CTL_REG) | ||
| 168 | & DNET_INTERNAL_GMII_MNG_CMD_FIN)) | ||
| 169 | cpu_relax(); | ||
| 170 | |||
| 171 | return 0; | ||
| 172 | } | ||
| 173 | |||
| 174 | static int dnet_mdio_reset(struct mii_bus *bus) | ||
| 175 | { | ||
| 176 | return 0; | ||
| 177 | } | ||
| 178 | |||
| 179 | static void dnet_handle_link_change(struct net_device *dev) | ||
| 180 | { | ||
| 181 | struct dnet *bp = netdev_priv(dev); | ||
| 182 | struct phy_device *phydev = bp->phy_dev; | ||
| 183 | unsigned long flags; | ||
| 184 | u32 mode_reg, ctl_reg; | ||
| 185 | |||
| 186 | int status_change = 0; | ||
| 187 | |||
| 188 | spin_lock_irqsave(&bp->lock, flags); | ||
| 189 | |||
| 190 | mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG); | ||
| 191 | ctl_reg = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG); | ||
| 192 | |||
| 193 | if (phydev->link) { | ||
| 194 | if (bp->duplex != phydev->duplex) { | ||
| 195 | if (phydev->duplex) | ||
| 196 | ctl_reg &= | ||
| 197 | ~(DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP); | ||
| 198 | else | ||
| 199 | ctl_reg |= | ||
| 200 | DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP; | ||
| 201 | |||
| 202 | bp->duplex = phydev->duplex; | ||
| 203 | status_change = 1; | ||
| 204 | } | ||
| 205 | |||
| 206 | if (bp->speed != phydev->speed) { | ||
| 207 | status_change = 1; | ||
| 208 | switch (phydev->speed) { | ||
| 209 | case 1000: | ||
| 210 | mode_reg |= DNET_INTERNAL_MODE_GBITEN; | ||
| 211 | break; | ||
| 212 | case 100: | ||
| 213 | case 10: | ||
| 214 | mode_reg &= ~DNET_INTERNAL_MODE_GBITEN; | ||
| 215 | break; | ||
| 216 | default: | ||
| 217 | printk(KERN_WARNING | ||
| 218 | "%s: Ack! Speed (%d) is not " | ||
| 219 | "10/100/1000!\n", dev->name, | ||
| 220 | phydev->speed); | ||
| 221 | break; | ||
| 222 | } | ||
| 223 | bp->speed = phydev->speed; | ||
| 224 | } | ||
| 225 | } | ||
| 226 | |||
| 227 | if (phydev->link != bp->link) { | ||
| 228 | if (phydev->link) { | ||
| 229 | mode_reg |= | ||
| 230 | (DNET_INTERNAL_MODE_RXEN | DNET_INTERNAL_MODE_TXEN); | ||
| 231 | } else { | ||
| 232 | mode_reg &= | ||
| 233 | ~(DNET_INTERNAL_MODE_RXEN | | ||
| 234 | DNET_INTERNAL_MODE_TXEN); | ||
| 235 | bp->speed = 0; | ||
| 236 | bp->duplex = -1; | ||
| 237 | } | ||
| 238 | bp->link = phydev->link; | ||
| 239 | |||
| 240 | status_change = 1; | ||
| 241 | } | ||
| 242 | |||
| 243 | if (status_change) { | ||
| 244 | dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, ctl_reg); | ||
| 245 | dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg); | ||
| 246 | } | ||
| 247 | |||
| 248 | spin_unlock_irqrestore(&bp->lock, flags); | ||
| 249 | |||
| 250 | if (status_change) { | ||
| 251 | if (phydev->link) | ||
| 252 | printk(KERN_INFO "%s: link up (%d/%s)\n", | ||
| 253 | dev->name, phydev->speed, | ||
| 254 | DUPLEX_FULL == phydev->duplex ? "Full" : "Half"); | ||
| 255 | else | ||
| 256 | printk(KERN_INFO "%s: link down\n", dev->name); | ||
| 257 | } | ||
| 258 | } | ||
| 259 | |||
| 260 | static int dnet_mii_probe(struct net_device *dev) | ||
| 261 | { | ||
| 262 | struct dnet *bp = netdev_priv(dev); | ||
| 263 | struct phy_device *phydev = NULL; | ||
| 264 | int phy_addr; | ||
| 265 | |||
| 266 | /* find the first phy */ | ||
| 267 | for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { | ||
| 268 | if (bp->mii_bus->phy_map[phy_addr]) { | ||
| 269 | phydev = bp->mii_bus->phy_map[phy_addr]; | ||
| 270 | break; | ||
| 271 | } | ||
| 272 | } | ||
| 273 | |||
| 274 | if (!phydev) { | ||
| 275 | printk(KERN_ERR "%s: no PHY found\n", dev->name); | ||
| 276 | return -ENODEV; | ||
| 277 | } | ||
| 278 | |||
| 279 | /* TODO : add pin_irq */ | ||
| 280 | |||
| 281 | /* attach the mac to the phy */ | ||
| 282 | if (bp->capabilities & DNET_HAS_RMII) { | ||
| 283 | phydev = phy_connect(dev, dev_name(&phydev->dev), | ||
| 284 | &dnet_handle_link_change, 0, | ||
| 285 | PHY_INTERFACE_MODE_RMII); | ||
| 286 | } else { | ||
| 287 | phydev = phy_connect(dev, dev_name(&phydev->dev), | ||
| 288 | &dnet_handle_link_change, 0, | ||
| 289 | PHY_INTERFACE_MODE_MII); | ||
| 290 | } | ||
| 291 | |||
| 292 | if (IS_ERR(phydev)) { | ||
| 293 | printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); | ||
| 294 | return PTR_ERR(phydev); | ||
| 295 | } | ||
| 296 | |||
| 297 | /* mask with MAC supported features */ | ||
| 298 | if (bp->capabilities & DNET_HAS_GIGABIT) | ||
| 299 | phydev->supported &= PHY_GBIT_FEATURES; | ||
| 300 | else | ||
| 301 | phydev->supported &= PHY_BASIC_FEATURES; | ||
| 302 | |||
| 303 | phydev->supported |= SUPPORTED_Asym_Pause | SUPPORTED_Pause; | ||
| 304 | |||
| 305 | phydev->advertising = phydev->supported; | ||
| 306 | |||
| 307 | bp->link = 0; | ||
| 308 | bp->speed = 0; | ||
| 309 | bp->duplex = -1; | ||
| 310 | bp->phy_dev = phydev; | ||
| 311 | |||
| 312 | return 0; | ||
| 313 | } | ||
| 314 | |||
| 315 | static int dnet_mii_init(struct dnet *bp) | ||
| 316 | { | ||
| 317 | int err, i; | ||
| 318 | |||
| 319 | bp->mii_bus = mdiobus_alloc(); | ||
| 320 | if (bp->mii_bus == NULL) | ||
| 321 | return -ENOMEM; | ||
| 322 | |||
| 323 | bp->mii_bus->name = "dnet_mii_bus"; | ||
| 324 | bp->mii_bus->read = &dnet_mdio_read; | ||
| 325 | bp->mii_bus->write = &dnet_mdio_write; | ||
| 326 | bp->mii_bus->reset = &dnet_mdio_reset; | ||
| 327 | |||
| 328 | snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); | ||
| 329 | |||
| 330 | bp->mii_bus->priv = bp; | ||
| 331 | |||
| 332 | bp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); | ||
| 333 | if (!bp->mii_bus->irq) { | ||
| 334 | err = -ENOMEM; | ||
| 335 | goto err_out; | ||
| 336 | } | ||
| 337 | |||
| 338 | for (i = 0; i < PHY_MAX_ADDR; i++) | ||
| 339 | bp->mii_bus->irq[i] = PHY_POLL; | ||
| 340 | |||
| 341 | platform_set_drvdata(bp->dev, bp->mii_bus); | ||
| 342 | |||
| 343 | if (mdiobus_register(bp->mii_bus)) { | ||
| 344 | err = -ENXIO; | ||
| 345 | goto err_out_free_mdio_irq; | ||
| 346 | } | ||
| 347 | |||
| 348 | if (dnet_mii_probe(bp->dev) != 0) { | ||
| 349 | err = -ENXIO; | ||
| 350 | goto err_out_unregister_bus; | ||
| 351 | } | ||
| 352 | |||
| 353 | return 0; | ||
| 354 | |||
| 355 | err_out_unregister_bus: | ||
| 356 | mdiobus_unregister(bp->mii_bus); | ||
| 357 | err_out_free_mdio_irq: | ||
| 358 | kfree(bp->mii_bus->irq); | ||
| 359 | err_out: | ||
| 360 | mdiobus_free(bp->mii_bus); | ||
| 361 | return err; | ||
| 362 | } | ||
| 363 | |||
| 364 | /* For Neptune board: LINK1000 as Link LED and TX as activity LED */ | ||
| 365 | int dnet_phy_marvell_fixup(struct phy_device *phydev) | ||
| 366 | { | ||
| 367 | return phy_write(phydev, 0x18, 0x4148); | ||
| 368 | } | ||
| 369 | |||
| 370 | static void dnet_update_stats(struct dnet *bp) | ||
| 371 | { | ||
| 372 | u32 __iomem *reg = bp->regs + DNET_RX_PKT_IGNR_CNT; | ||
| 373 | u32 *p = &bp->hw_stats.rx_pkt_ignr; | ||
| 374 | u32 *end = &bp->hw_stats.rx_byte + 1; | ||
| 375 | |||
| 376 | WARN_ON((unsigned long)(end - p - 1) != | ||
| 377 | (DNET_RX_BYTE_CNT - DNET_RX_PKT_IGNR_CNT) / 4); | ||
| 378 | |||
| 379 | for (; p < end; p++, reg++) | ||
| 380 | *p += readl(reg); | ||
| 381 | |||
| 382 | reg = bp->regs + DNET_TX_UNICAST_CNT; | ||
| 383 | p = &bp->hw_stats.tx_unicast; | ||
| 384 | end = &bp->hw_stats.tx_byte + 1; | ||
| 385 | |||
| 386 | WARN_ON((unsigned long)(end - p - 1) != | ||
| 387 | (DNET_TX_BYTE_CNT - DNET_TX_UNICAST_CNT) / 4); | ||
| 388 | |||
| 389 | for (; p < end; p++, reg++) | ||
| 390 | *p += readl(reg); | ||
| 391 | } | ||
| 392 | |||
| 393 | static int dnet_poll(struct napi_struct *napi, int budget) | ||
| 394 | { | ||
| 395 | struct dnet *bp = container_of(napi, struct dnet, napi); | ||
| 396 | struct net_device *dev = bp->dev; | ||
| 397 | int npackets = 0; | ||
| 398 | unsigned int pkt_len; | ||
| 399 | struct sk_buff *skb; | ||
| 400 | unsigned int *data_ptr; | ||
| 401 | u32 int_enable; | ||
| 402 | u32 cmd_word; | ||
| 403 | int i; | ||
| 404 | |||
| 405 | while (npackets < budget) { | ||
| 406 | /* | ||
| 407 | * break out of while loop if there are no more | ||
| 408 | * packets waiting | ||
| 409 | */ | ||
| 410 | if (!(dnet_readl(bp, RX_FIFO_WCNT) >> 16)) { | ||
| 411 | napi_complete(napi); | ||
| 412 | int_enable = dnet_readl(bp, INTR_ENB); | ||
| 413 | int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF; | ||
| 414 | dnet_writel(bp, int_enable, INTR_ENB); | ||
| 415 | return 0; | ||
| 416 | } | ||
| 417 | |||
| 418 | cmd_word = dnet_readl(bp, RX_LEN_FIFO); | ||
| 419 | pkt_len = cmd_word & 0xFFFF; | ||
| 420 | |||
| 421 | if (cmd_word & 0xDF180000) | ||
| 422 | printk(KERN_ERR "%s packet receive error %x\n", | ||
| 423 | __func__, cmd_word); | ||
| 424 | |||
| 425 | skb = dev_alloc_skb(pkt_len + 5); | ||
| 426 | if (skb != NULL) { | ||
| 427 | /* Align IP on 16 byte boundaries */ | ||
| 428 | skb_reserve(skb, 2); | ||
| 429 | /* | ||
| 430 | * 'skb_put()' points to the start of sk_buff | ||
| 431 | * data area. | ||
| 432 | */ | ||
| 433 | data_ptr = (unsigned int *)skb_put(skb, pkt_len); | ||
| 434 | for (i = 0; i < (pkt_len + 3) >> 2; i++) | ||
| 435 | *data_ptr++ = dnet_readl(bp, RX_DATA_FIFO); | ||
| 436 | skb->protocol = eth_type_trans(skb, dev); | ||
| 437 | netif_receive_skb(skb); | ||
| 438 | npackets++; | ||
| 439 | } else | ||
| 440 | printk(KERN_NOTICE | ||
| 441 | "%s: No memory to allocate a sk_buff of " | ||
| 442 | "size %u.\n", dev->name, pkt_len); | ||
| 443 | } | ||
| 444 | |||
| 445 | budget -= npackets; | ||
| 446 | |||
| 447 | if (npackets < budget) { | ||
| 448 | /* We processed all packets available. Tell NAPI it can | ||
| 449 | * stop polling then re-enable rx interrupts */ | ||
| 450 | napi_complete(napi); | ||
| 451 | int_enable = dnet_readl(bp, INTR_ENB); | ||
| 452 | int_enable |= DNET_INTR_SRC_RX_CMDFIFOAF; | ||
| 453 | dnet_writel(bp, int_enable, INTR_ENB); | ||
| 454 | return 0; | ||
| 455 | } | ||
| 456 | |||
| 457 | /* There are still packets waiting */ | ||
| 458 | return 1; | ||
| 459 | } | ||
| 460 | |||
| 461 | static irqreturn_t dnet_interrupt(int irq, void *dev_id) | ||
| 462 | { | ||
| 463 | struct net_device *dev = dev_id; | ||
| 464 | struct dnet *bp = netdev_priv(dev); | ||
| 465 | u32 int_src, int_enable, int_current; | ||
| 466 | unsigned long flags; | ||
| 467 | unsigned int handled = 0; | ||
| 468 | |||
| 469 | spin_lock_irqsave(&bp->lock, flags); | ||
| 470 | |||
| 471 | /* read and clear the DNET irq (clear on read) */ | ||
| 472 | int_src = dnet_readl(bp, INTR_SRC); | ||
| 473 | int_enable = dnet_readl(bp, INTR_ENB); | ||
| 474 | int_current = int_src & int_enable; | ||
| 475 | |||
| 476 | /* restart the queue if we had stopped it for TX fifo almost full */ | ||
| 477 | if (int_current & DNET_INTR_SRC_TX_FIFOAE) { | ||
| 478 | int_enable = dnet_readl(bp, INTR_ENB); | ||
| 479 | int_enable &= ~DNET_INTR_ENB_TX_FIFOAE; | ||
| 480 | dnet_writel(bp, int_enable, INTR_ENB); | ||
| 481 | netif_wake_queue(dev); | ||
| 482 | handled = 1; | ||
| 483 | } | ||
| 484 | |||
| 485 | /* RX FIFO error checking */ | ||
| 486 | if (int_current & | ||
| 487 | (DNET_INTR_SRC_RX_CMDFIFOFF | DNET_INTR_SRC_RX_DATAFIFOFF)) { | ||
| 488 | printk(KERN_ERR "%s: RX fifo error %x, irq %x\n", __func__, | ||
| 489 | dnet_readl(bp, RX_STATUS), int_current); | ||
| 490 | /* we can only flush the RX FIFOs */ | ||
| 491 | dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH, SYS_CTL); | ||
| 492 | ndelay(500); | ||
| 493 | dnet_writel(bp, 0, SYS_CTL); | ||
| 494 | handled = 1; | ||
| 495 | } | ||
| 496 | |||
| 497 | /* TX FIFO error checking */ | ||
| 498 | if (int_current & | ||
| 499 | (DNET_INTR_SRC_TX_FIFOFULL | DNET_INTR_SRC_TX_DISCFRM)) { | ||
| 500 | printk(KERN_ERR "%s: TX fifo error %x, irq %x\n", __func__, | ||
| 501 | dnet_readl(bp, TX_STATUS), int_current); | ||
| 502 | /* we can only flush the TX FIFOs */ | ||
| 503 | dnet_writel(bp, DNET_SYS_CTL_TXFIFOFLUSH, SYS_CTL); | ||
| 504 | ndelay(500); | ||
| 505 | dnet_writel(bp, 0, SYS_CTL); | ||
| 506 | handled = 1; | ||
| 507 | } | ||
| 508 | |||
| 509 | if (int_current & DNET_INTR_SRC_RX_CMDFIFOAF) { | ||
| 510 | if (napi_schedule_prep(&bp->napi)) { | ||
| 511 | /* | ||
| 512 | * There's no point taking any more interrupts | ||
| 513 | * until we have processed the buffers | ||
| 514 | */ | ||
| 515 | /* Disable Rx interrupts and schedule NAPI poll */ | ||
| 516 | int_enable = dnet_readl(bp, INTR_ENB); | ||
| 517 | int_enable &= ~DNET_INTR_SRC_RX_CMDFIFOAF; | ||
| 518 | dnet_writel(bp, int_enable, INTR_ENB); | ||
| 519 | __napi_schedule(&bp->napi); | ||
| 520 | } | ||
| 521 | handled = 1; | ||
| 522 | } | ||
| 523 | |||
| 524 | if (!handled) | ||
| 525 | pr_debug("%s: irq %x remains\n", __func__, int_current); | ||
| 526 | |||
| 527 | spin_unlock_irqrestore(&bp->lock, flags); | ||
| 528 | |||
| 529 | return IRQ_RETVAL(handled); | ||
| 530 | } | ||
| 531 | |||
| 532 | #ifdef DEBUG | ||
| 533 | static inline void dnet_print_skb(struct sk_buff *skb) | ||
| 534 | { | ||
| 535 | int k; | ||
| 536 | printk(KERN_DEBUG PFX "data:"); | ||
| 537 | for (k = 0; k < skb->len; k++) | ||
| 538 | printk(" %02x", (unsigned int)skb->data[k]); | ||
| 539 | printk("\n"); | ||
| 540 | } | ||
| 541 | #else | ||
| 542 | #define dnet_print_skb(skb) do {} while (0) | ||
| 543 | #endif | ||
| 544 | |||
| 545 | static int dnet_start_xmit(struct sk_buff *skb, struct net_device *dev) | ||
| 546 | { | ||
| 547 | |||
| 548 | struct dnet *bp = netdev_priv(dev); | ||
| 549 | u32 tx_status, irq_enable; | ||
| 550 | unsigned int len, i, tx_cmd, wrsz; | ||
| 551 | unsigned long flags; | ||
| 552 | unsigned int *bufp; | ||
| 553 | |||
| 554 | tx_status = dnet_readl(bp, TX_STATUS); | ||
| 555 | |||
| 556 | pr_debug("start_xmit: len %u head %p data %p\n", | ||
| 557 | skb->len, skb->head, skb->data); | ||
| 558 | dnet_print_skb(skb); | ||
| 559 | |||
| 560 | /* frame size (words) */ | ||
| 561 | len = (skb->len + 3) >> 2; | ||
| 562 | |||
| 563 | spin_lock_irqsave(&bp->lock, flags); | ||
| 564 | |||
| 565 | tx_status = dnet_readl(bp, TX_STATUS); | ||
| 566 | |||
| 567 | bufp = (unsigned int *)(((unsigned long) skb->data) & ~0x3UL); | ||
| 568 | wrsz = (u32) skb->len + 3; | ||
| 569 | wrsz += ((unsigned long) skb->data) & 0x3; | ||
| 570 | wrsz >>= 2; | ||
| 571 | tx_cmd = ((((unsigned long)(skb->data)) & 0x03) << 16) | (u32) skb->len; | ||
| 572 | |||
| 573 | /* check if there is enough room for the current frame */ | ||
| 574 | if (wrsz < (DNET_FIFO_SIZE - dnet_readl(bp, TX_FIFO_WCNT))) { | ||
| 575 | for (i = 0; i < wrsz; i++) | ||
| 576 | dnet_writel(bp, *bufp++, TX_DATA_FIFO); | ||
| 577 | |||
| 578 | /* | ||
| 579 | * inform MAC that a packet's written and ready to be | ||
| 580 | * shipped out | ||
| 581 | */ | ||
| 582 | dnet_writel(bp, tx_cmd, TX_LEN_FIFO); | ||
| 583 | } | ||
| 584 | |||
| 585 | if (dnet_readl(bp, TX_FIFO_WCNT) > DNET_FIFO_TX_DATA_AF_TH) { | ||
| 586 | netif_stop_queue(dev); | ||
| 587 | tx_status = dnet_readl(bp, INTR_SRC); | ||
| 588 | irq_enable = dnet_readl(bp, INTR_ENB); | ||
| 589 | irq_enable |= DNET_INTR_ENB_TX_FIFOAE; | ||
| 590 | dnet_writel(bp, irq_enable, INTR_ENB); | ||
| 591 | } | ||
| 592 | |||
| 593 | /* free the buffer */ | ||
| 594 | dev_kfree_skb(skb); | ||
| 595 | |||
| 596 | spin_unlock_irqrestore(&bp->lock, flags); | ||
| 597 | |||
| 598 | dev->trans_start = jiffies; | ||
| 599 | |||
| 600 | return 0; | ||
| 601 | } | ||
| 602 | |||
| 603 | static void dnet_reset_hw(struct dnet *bp) | ||
| 604 | { | ||
| 605 | /* put ts_mac in IDLE state i.e. disable rx/tx */ | ||
| 606 | dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, DNET_INTERNAL_MODE_FCEN); | ||
| 607 | |||
| 608 | /* | ||
| 609 | * RX FIFO almost full threshold: only cmd FIFO almost full is | ||
| 610 | * implemented for RX side | ||
| 611 | */ | ||
| 612 | dnet_writel(bp, DNET_FIFO_RX_CMD_AF_TH, RX_FIFO_TH); | ||
| 613 | /* | ||
| 614 | * TX FIFO almost empty threshold: only data FIFO almost empty | ||
| 615 | * is implemented for TX side | ||
| 616 | */ | ||
| 617 | dnet_writel(bp, DNET_FIFO_TX_DATA_AE_TH, TX_FIFO_TH); | ||
| 618 | |||
| 619 | /* flush rx/tx fifos */ | ||
| 620 | dnet_writel(bp, DNET_SYS_CTL_RXFIFOFLUSH | DNET_SYS_CTL_TXFIFOFLUSH, | ||
| 621 | SYS_CTL); | ||
| 622 | msleep(1); | ||
| 623 | dnet_writel(bp, 0, SYS_CTL); | ||
| 624 | } | ||
| 625 | |||
| 626 | static void dnet_init_hw(struct dnet *bp) | ||
| 627 | { | ||
| 628 | u32 config; | ||
| 629 | |||
| 630 | dnet_reset_hw(bp); | ||
| 631 | __dnet_set_hwaddr(bp); | ||
| 632 | |||
| 633 | config = dnet_readw_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG); | ||
| 634 | |||
| 635 | if (bp->dev->flags & IFF_PROMISC) | ||
| 636 | /* Copy All Frames */ | ||
| 637 | config |= DNET_INTERNAL_RXTX_CONTROL_ENPROMISC; | ||
| 638 | if (!(bp->dev->flags & IFF_BROADCAST)) | ||
| 639 | /* No BroadCast */ | ||
| 640 | config |= DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST; | ||
| 641 | |||
| 642 | config |= DNET_INTERNAL_RXTX_CONTROL_RXPAUSE | | ||
| 643 | DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST | | ||
| 644 | DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL | | ||
| 645 | DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS; | ||
| 646 | |||
| 647 | dnet_writew_mac(bp, DNET_INTERNAL_RXTX_CONTROL_REG, config); | ||
| 648 | |||
| 649 | /* clear irq before enabling them */ | ||
| 650 | config = dnet_readl(bp, INTR_SRC); | ||
| 651 | |||
| 652 | /* enable RX/TX interrupt, recv packet ready interrupt */ | ||
| 653 | dnet_writel(bp, DNET_INTR_ENB_GLOBAL_ENABLE | DNET_INTR_ENB_RX_SUMMARY | | ||
| 654 | DNET_INTR_ENB_TX_SUMMARY | DNET_INTR_ENB_RX_FIFOERR | | ||
| 655 | DNET_INTR_ENB_RX_ERROR | DNET_INTR_ENB_RX_FIFOFULL | | ||
| 656 | DNET_INTR_ENB_TX_FIFOFULL | DNET_INTR_ENB_TX_DISCFRM | | ||
| 657 | DNET_INTR_ENB_RX_PKTRDY, INTR_ENB); | ||
| 658 | } | ||
| 659 | |||
| 660 | static int dnet_open(struct net_device *dev) | ||
| 661 | { | ||
| 662 | struct dnet *bp = netdev_priv(dev); | ||
| 663 | |||
| 664 | /* if the phy is not yet register, retry later */ | ||
| 665 | if (!bp->phy_dev) | ||
| 666 | return -EAGAIN; | ||
| 667 | |||
| 668 | if (!is_valid_ether_addr(dev->dev_addr)) | ||
| 669 | return -EADDRNOTAVAIL; | ||
| 670 | |||
| 671 | napi_enable(&bp->napi); | ||
| 672 | dnet_init_hw(bp); | ||
| 673 | |||
| 674 | phy_start_aneg(bp->phy_dev); | ||
| 675 | |||
| 676 | /* schedule a link state check */ | ||
| 677 | phy_start(bp->phy_dev); | ||
| 678 | |||
| 679 | netif_start_queue(dev); | ||
| 680 | |||
| 681 | return 0; | ||
| 682 | } | ||
| 683 | |||
| 684 | static int dnet_close(struct net_device *dev) | ||
| 685 | { | ||
| 686 | struct dnet *bp = netdev_priv(dev); | ||
| 687 | |||
| 688 | netif_stop_queue(dev); | ||
| 689 | napi_disable(&bp->napi); | ||
| 690 | |||
| 691 | if (bp->phy_dev) | ||
| 692 | phy_stop(bp->phy_dev); | ||
| 693 | |||
| 694 | dnet_reset_hw(bp); | ||
| 695 | netif_carrier_off(dev); | ||
| 696 | |||
| 697 | return 0; | ||
| 698 | } | ||
| 699 | |||
| 700 | static inline void dnet_print_pretty_hwstats(struct dnet_stats *hwstat) | ||
| 701 | { | ||
| 702 | pr_debug("%s\n", __func__); | ||
| 703 | pr_debug("----------------------------- RX statistics " | ||
| 704 | "-------------------------------\n"); | ||
| 705 | pr_debug("RX_PKT_IGNR_CNT %-8x\n", hwstat->rx_pkt_ignr); | ||
| 706 | pr_debug("RX_LEN_CHK_ERR_CNT %-8x\n", hwstat->rx_len_chk_err); | ||
| 707 | pr_debug("RX_LNG_FRM_CNT %-8x\n", hwstat->rx_lng_frm); | ||
| 708 | pr_debug("RX_SHRT_FRM_CNT %-8x\n", hwstat->rx_shrt_frm); | ||
| 709 | pr_debug("RX_IPG_VIOL_CNT %-8x\n", hwstat->rx_ipg_viol); | ||
| 710 | pr_debug("RX_CRC_ERR_CNT %-8x\n", hwstat->rx_crc_err); | ||
| 711 | pr_debug("RX_OK_PKT_CNT %-8x\n", hwstat->rx_ok_pkt); | ||
| 712 | pr_debug("RX_CTL_FRM_CNT %-8x\n", hwstat->rx_ctl_frm); | ||
| 713 | pr_debug("RX_PAUSE_FRM_CNT %-8x\n", hwstat->rx_pause_frm); | ||
| 714 | pr_debug("RX_MULTICAST_CNT %-8x\n", hwstat->rx_multicast); | ||
| 715 | pr_debug("RX_BROADCAST_CNT %-8x\n", hwstat->rx_broadcast); | ||
| 716 | pr_debug("RX_VLAN_TAG_CNT %-8x\n", hwstat->rx_vlan_tag); | ||
| 717 | pr_debug("RX_PRE_SHRINK_CNT %-8x\n", hwstat->rx_pre_shrink); | ||
| 718 | pr_debug("RX_DRIB_NIB_CNT %-8x\n", hwstat->rx_drib_nib); | ||
| 719 | pr_debug("RX_UNSUP_OPCD_CNT %-8x\n", hwstat->rx_unsup_opcd); | ||
| 720 | pr_debug("RX_BYTE_CNT %-8x\n", hwstat->rx_byte); | ||
| 721 | pr_debug("----------------------------- TX statistics " | ||
| 722 | "-------------------------------\n"); | ||
| 723 | pr_debug("TX_UNICAST_CNT %-8x\n", hwstat->tx_unicast); | ||
| 724 | pr_debug("TX_PAUSE_FRM_CNT %-8x\n", hwstat->tx_pause_frm); | ||
| 725 | pr_debug("TX_MULTICAST_CNT %-8x\n", hwstat->tx_multicast); | ||
| 726 | pr_debug("TX_BRDCAST_CNT %-8x\n", hwstat->tx_brdcast); | ||
| 727 | pr_debug("TX_VLAN_TAG_CNT %-8x\n", hwstat->tx_vlan_tag); | ||
| 728 | pr_debug("TX_BAD_FCS_CNT %-8x\n", hwstat->tx_bad_fcs); | ||
| 729 | pr_debug("TX_JUMBO_CNT %-8x\n", hwstat->tx_jumbo); | ||
| 730 | pr_debug("TX_BYTE_CNT %-8x\n", hwstat->tx_byte); | ||
| 731 | } | ||
| 732 | |||
| 733 | static struct net_device_stats *dnet_get_stats(struct net_device *dev) | ||
| 734 | { | ||
| 735 | |||
| 736 | struct dnet *bp = netdev_priv(dev); | ||
| 737 | struct net_device_stats *nstat = &dev->stats; | ||
| 738 | struct dnet_stats *hwstat = &bp->hw_stats; | ||
| 739 | |||
| 740 | /* read stats from hardware */ | ||
| 741 | dnet_update_stats(bp); | ||
| 742 | |||
| 743 | /* Convert HW stats into netdevice stats */ | ||
| 744 | nstat->rx_errors = (hwstat->rx_len_chk_err + | ||
| 745 | hwstat->rx_lng_frm + hwstat->rx_shrt_frm + | ||
| 746 | /* ignore IGP violation error | ||
| 747 | hwstat->rx_ipg_viol + */ | ||
| 748 | hwstat->rx_crc_err + | ||
| 749 | hwstat->rx_pre_shrink + | ||
| 750 | hwstat->rx_drib_nib + hwstat->rx_unsup_opcd); | ||
| 751 | nstat->tx_errors = hwstat->tx_bad_fcs; | ||
| 752 | nstat->rx_length_errors = (hwstat->rx_len_chk_err + | ||
| 753 | hwstat->rx_lng_frm + | ||
| 754 | hwstat->rx_shrt_frm + hwstat->rx_pre_shrink); | ||
| 755 | nstat->rx_crc_errors = hwstat->rx_crc_err; | ||
| 756 | nstat->rx_frame_errors = hwstat->rx_pre_shrink + hwstat->rx_drib_nib; | ||
| 757 | nstat->rx_packets = hwstat->rx_ok_pkt; | ||
| 758 | nstat->tx_packets = (hwstat->tx_unicast + | ||
| 759 | hwstat->tx_multicast + hwstat->tx_brdcast); | ||
| 760 | nstat->rx_bytes = hwstat->rx_byte; | ||
| 761 | nstat->tx_bytes = hwstat->tx_byte; | ||
| 762 | nstat->multicast = hwstat->rx_multicast; | ||
| 763 | nstat->rx_missed_errors = hwstat->rx_pkt_ignr; | ||
| 764 | |||
| 765 | dnet_print_pretty_hwstats(hwstat); | ||
| 766 | |||
| 767 | return nstat; | ||
| 768 | } | ||
| 769 | |||
| 770 | static int dnet_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | ||
| 771 | { | ||
| 772 | struct dnet *bp = netdev_priv(dev); | ||
| 773 | struct phy_device *phydev = bp->phy_dev; | ||
| 774 | |||
| 775 | if (!phydev) | ||
| 776 | return -ENODEV; | ||
| 777 | |||
| 778 | return phy_ethtool_gset(phydev, cmd); | ||
| 779 | } | ||
| 780 | |||
| 781 | static int dnet_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | ||
| 782 | { | ||
| 783 | struct dnet *bp = netdev_priv(dev); | ||
| 784 | struct phy_device *phydev = bp->phy_dev; | ||
| 785 | |||
| 786 | if (!phydev) | ||
| 787 | return -ENODEV; | ||
| 788 | |||
| 789 | return phy_ethtool_sset(phydev, cmd); | ||
| 790 | } | ||
| 791 | |||
| 792 | static int dnet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | ||
| 793 | { | ||
| 794 | struct dnet *bp = netdev_priv(dev); | ||
| 795 | struct phy_device *phydev = bp->phy_dev; | ||
| 796 | |||
| 797 | if (!netif_running(dev)) | ||
| 798 | return -EINVAL; | ||
| 799 | |||
| 800 | if (!phydev) | ||
| 801 | return -ENODEV; | ||
| 802 | |||
| 803 | return phy_mii_ioctl(phydev, if_mii(rq), cmd); | ||
| 804 | } | ||
| 805 | |||
| 806 | static void dnet_get_drvinfo(struct net_device *dev, | ||
| 807 | struct ethtool_drvinfo *info) | ||
| 808 | { | ||
| 809 | strcpy(info->driver, DRV_NAME); | ||
| 810 | strcpy(info->version, DRV_VERSION); | ||
| 811 | strcpy(info->bus_info, "0"); | ||
| 812 | } | ||
| 813 | |||
| 814 | static const struct ethtool_ops dnet_ethtool_ops = { | ||
| 815 | .get_settings = dnet_get_settings, | ||
| 816 | .set_settings = dnet_set_settings, | ||
| 817 | .get_drvinfo = dnet_get_drvinfo, | ||
| 818 | .get_link = ethtool_op_get_link, | ||
| 819 | }; | ||
| 820 | |||
| 821 | static const struct net_device_ops dnet_netdev_ops = { | ||
| 822 | .ndo_open = dnet_open, | ||
| 823 | .ndo_stop = dnet_close, | ||
| 824 | .ndo_get_stats = dnet_get_stats, | ||
| 825 | .ndo_start_xmit = dnet_start_xmit, | ||
| 826 | .ndo_do_ioctl = dnet_ioctl, | ||
| 827 | .ndo_set_mac_address = eth_mac_addr, | ||
| 828 | .ndo_validate_addr = eth_validate_addr, | ||
| 829 | .ndo_change_mtu = eth_change_mtu, | ||
| 830 | }; | ||
| 831 | |||
| 832 | static int __devinit dnet_probe(struct platform_device *pdev) | ||
| 833 | { | ||
| 834 | struct resource *res; | ||
| 835 | struct net_device *dev; | ||
| 836 | struct dnet *bp; | ||
| 837 | struct phy_device *phydev; | ||
| 838 | int err = -ENXIO; | ||
| 839 | unsigned int mem_base, mem_size, irq; | ||
| 840 | |||
| 841 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
| 842 | if (!res) { | ||
| 843 | dev_err(&pdev->dev, "no mmio resource defined\n"); | ||
| 844 | goto err_out; | ||
| 845 | } | ||
| 846 | mem_base = res->start; | ||
| 847 | mem_size = resource_size(res); | ||
| 848 | irq = platform_get_irq(pdev, 0); | ||
| 849 | |||
| 850 | if (!request_mem_region(mem_base, mem_size, DRV_NAME)) { | ||
| 851 | dev_err(&pdev->dev, "no memory region available\n"); | ||
| 852 | err = -EBUSY; | ||
| 853 | goto err_out; | ||
| 854 | } | ||
| 855 | |||
| 856 | err = -ENOMEM; | ||
| 857 | dev = alloc_etherdev(sizeof(*bp)); | ||
| 858 | if (!dev) { | ||
| 859 | dev_err(&pdev->dev, "etherdev alloc failed, aborting.\n"); | ||
| 860 | goto err_out; | ||
| 861 | } | ||
| 862 | |||
| 863 | /* TODO: Actually, we have some interesting features... */ | ||
| 864 | dev->features |= 0; | ||
| 865 | |||
| 866 | bp = netdev_priv(dev); | ||
| 867 | bp->dev = dev; | ||
| 868 | |||
| 869 | SET_NETDEV_DEV(dev, &pdev->dev); | ||
| 870 | |||
| 871 | spin_lock_init(&bp->lock); | ||
| 872 | |||
| 873 | bp->regs = ioremap(mem_base, mem_size); | ||
| 874 | if (!bp->regs) { | ||
| 875 | dev_err(&pdev->dev, "failed to map registers, aborting.\n"); | ||
| 876 | err = -ENOMEM; | ||
| 877 | goto err_out_free_dev; | ||
| 878 | } | ||
| 879 | |||
| 880 | dev->irq = irq; | ||
| 881 | err = request_irq(dev->irq, dnet_interrupt, 0, DRV_NAME, dev); | ||
| 882 | if (err) { | ||
| 883 | dev_err(&pdev->dev, "Unable to request IRQ %d (error %d)\n", | ||
| 884 | irq, err); | ||
| 885 | goto err_out_iounmap; | ||
| 886 | } | ||
| 887 | |||
| 888 | dev->netdev_ops = &dnet_netdev_ops; | ||
| 889 | netif_napi_add(dev, &bp->napi, dnet_poll, 64); | ||
| 890 | dev->ethtool_ops = &dnet_ethtool_ops; | ||
| 891 | |||
| 892 | dev->base_addr = (unsigned long)bp->regs; | ||
| 893 | |||
| 894 | bp->capabilities = dnet_readl(bp, VERCAPS) & DNET_CAPS_MASK; | ||
| 895 | |||
| 896 | dnet_get_hwaddr(bp); | ||
| 897 | |||
| 898 | if (!is_valid_ether_addr(dev->dev_addr)) { | ||
| 899 | /* choose a random ethernet address */ | ||
| 900 | random_ether_addr(dev->dev_addr); | ||
| 901 | __dnet_set_hwaddr(bp); | ||
| 902 | } | ||
| 903 | |||
| 904 | err = register_netdev(dev); | ||
| 905 | if (err) { | ||
| 906 | dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); | ||
| 907 | goto err_out_free_irq; | ||
| 908 | } | ||
| 909 | |||
| 910 | /* register the PHY board fixup (for Marvell 88E1111) */ | ||
| 911 | err = phy_register_fixup_for_uid(0x01410cc0, 0xfffffff0, | ||
| 912 | dnet_phy_marvell_fixup); | ||
| 913 | /* we can live without it, so just issue a warning */ | ||
| 914 | if (err) | ||
| 915 | dev_warn(&pdev->dev, "Cannot register PHY board fixup.\n"); | ||
| 916 | |||
| 917 | if (dnet_mii_init(bp) != 0) | ||
| 918 | goto err_out_unregister_netdev; | ||
| 919 | |||
| 920 | dev_info(&pdev->dev, "Dave DNET at 0x%p (0x%08x) irq %d %pM\n", | ||
| 921 | bp->regs, mem_base, dev->irq, dev->dev_addr); | ||
| 922 | dev_info(&pdev->dev, "has %smdio, %sirq, %sgigabit, %sdma \n", | ||
| 923 | (bp->capabilities & DNET_HAS_MDIO) ? "" : "no ", | ||
| 924 | (bp->capabilities & DNET_HAS_IRQ) ? "" : "no ", | ||
| 925 | (bp->capabilities & DNET_HAS_GIGABIT) ? "" : "no ", | ||
| 926 | (bp->capabilities & DNET_HAS_DMA) ? "" : "no "); | ||
| 927 | phydev = bp->phy_dev; | ||
| 928 | dev_info(&pdev->dev, "attached PHY driver [%s] " | ||
| 929 | "(mii_bus:phy_addr=%s, irq=%d)\n", | ||
| 930 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq); | ||
| 931 | |||
| 932 | return 0; | ||
| 933 | |||
| 934 | err_out_unregister_netdev: | ||
| 935 | unregister_netdev(dev); | ||
| 936 | err_out_free_irq: | ||
| 937 | free_irq(dev->irq, dev); | ||
| 938 | err_out_iounmap: | ||
| 939 | iounmap(bp->regs); | ||
| 940 | err_out_free_dev: | ||
| 941 | free_netdev(dev); | ||
| 942 | err_out: | ||
| 943 | return err; | ||
| 944 | } | ||
| 945 | |||
| 946 | static int __devexit dnet_remove(struct platform_device *pdev) | ||
| 947 | { | ||
| 948 | |||
| 949 | struct net_device *dev; | ||
| 950 | struct dnet *bp; | ||
| 951 | |||
| 952 | dev = platform_get_drvdata(pdev); | ||
| 953 | |||
| 954 | if (dev) { | ||
| 955 | bp = netdev_priv(dev); | ||
| 956 | if (bp->phy_dev) | ||
| 957 | phy_disconnect(bp->phy_dev); | ||
| 958 | mdiobus_unregister(bp->mii_bus); | ||
| 959 | kfree(bp->mii_bus->irq); | ||
| 960 | mdiobus_free(bp->mii_bus); | ||
| 961 | unregister_netdev(dev); | ||
| 962 | free_irq(dev->irq, dev); | ||
| 963 | iounmap(bp->regs); | ||
| 964 | free_netdev(dev); | ||
| 965 | } | ||
| 966 | |||
| 967 | return 0; | ||
| 968 | } | ||
| 969 | |||
| 970 | static struct platform_driver dnet_driver = { | ||
| 971 | .probe = dnet_probe, | ||
| 972 | .remove = __devexit_p(dnet_remove), | ||
| 973 | .driver = { | ||
| 974 | .name = "dnet", | ||
| 975 | }, | ||
| 976 | }; | ||
| 977 | |||
| 978 | static int __init dnet_init(void) | ||
| 979 | { | ||
| 980 | return platform_driver_register(&dnet_driver); | ||
| 981 | } | ||
| 982 | |||
| 983 | static void __exit dnet_exit(void) | ||
| 984 | { | ||
| 985 | platform_driver_unregister(&dnet_driver); | ||
| 986 | } | ||
| 987 | |||
| 988 | module_init(dnet_init); | ||
| 989 | module_exit(dnet_exit); | ||
| 990 | |||
| 991 | MODULE_LICENSE("GPL"); | ||
| 992 | MODULE_DESCRIPTION("Dave DNET Ethernet driver"); | ||
| 993 | MODULE_AUTHOR("Ilya Yanok <yanok@emcraft.com>, " | ||
| 994 | "Matteo Vit <matteo.vit@dave.eu>"); | ||
diff --git a/drivers/net/dnet.h b/drivers/net/dnet.h new file mode 100644 index 000000000000..37f5b30fa78b --- /dev/null +++ b/drivers/net/dnet.h | |||
| @@ -0,0 +1,225 @@ | |||
| 1 | /* | ||
| 2 | * Dave DNET Ethernet Controller driver | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 Dave S.r.l. <www.dave.eu> | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | #ifndef _DNET_H | ||
| 11 | #define _DNET_H | ||
| 12 | |||
| 13 | #define DRV_NAME "dnet" | ||
| 14 | #define DRV_VERSION "0.9.1" | ||
| 15 | #define PFX DRV_NAME ": " | ||
| 16 | |||
| 17 | /* Register access macros */ | ||
| 18 | #define dnet_writel(port, value, reg) \ | ||
| 19 | writel((value), (port)->regs + DNET_##reg) | ||
| 20 | #define dnet_readl(port, reg) readl((port)->regs + DNET_##reg) | ||
| 21 | |||
| 22 | /* ALL DNET FIFO REGISTERS */ | ||
| 23 | #define DNET_RX_LEN_FIFO 0x000 /* RX_LEN_FIFO */ | ||
| 24 | #define DNET_RX_DATA_FIFO 0x004 /* RX_DATA_FIFO */ | ||
| 25 | #define DNET_TX_LEN_FIFO 0x008 /* TX_LEN_FIFO */ | ||
| 26 | #define DNET_TX_DATA_FIFO 0x00C /* TX_DATA_FIFO */ | ||
| 27 | |||
| 28 | /* ALL DNET CONTROL/STATUS REGISTERS OFFSETS */ | ||
| 29 | #define DNET_VERCAPS 0x100 /* VERCAPS */ | ||
| 30 | #define DNET_INTR_SRC 0x104 /* INTR_SRC */ | ||
| 31 | #define DNET_INTR_ENB 0x108 /* INTR_ENB */ | ||
| 32 | #define DNET_RX_STATUS 0x10C /* RX_STATUS */ | ||
| 33 | #define DNET_TX_STATUS 0x110 /* TX_STATUS */ | ||
| 34 | #define DNET_RX_FRAMES_CNT 0x114 /* RX_FRAMES_CNT */ | ||
| 35 | #define DNET_TX_FRAMES_CNT 0x118 /* TX_FRAMES_CNT */ | ||
| 36 | #define DNET_RX_FIFO_TH 0x11C /* RX_FIFO_TH */ | ||
| 37 | #define DNET_TX_FIFO_TH 0x120 /* TX_FIFO_TH */ | ||
| 38 | #define DNET_SYS_CTL 0x124 /* SYS_CTL */ | ||
| 39 | #define DNET_PAUSE_TMR 0x128 /* PAUSE_TMR */ | ||
| 40 | #define DNET_RX_FIFO_WCNT 0x12C /* RX_FIFO_WCNT */ | ||
| 41 | #define DNET_TX_FIFO_WCNT 0x130 /* TX_FIFO_WCNT */ | ||
| 42 | |||
| 43 | /* ALL DNET MAC REGISTERS */ | ||
| 44 | #define DNET_MACREG_DATA 0x200 /* Mac-Reg Data */ | ||
| 45 | #define DNET_MACREG_ADDR 0x204 /* Mac-Reg Addr */ | ||
| 46 | |||
| 47 | /* ALL DNET RX STATISTICS COUNTERS */ | ||
| 48 | #define DNET_RX_PKT_IGNR_CNT 0x300 | ||
| 49 | #define DNET_RX_LEN_CHK_ERR_CNT 0x304 | ||
| 50 | #define DNET_RX_LNG_FRM_CNT 0x308 | ||
| 51 | #define DNET_RX_SHRT_FRM_CNT 0x30C | ||
| 52 | #define DNET_RX_IPG_VIOL_CNT 0x310 | ||
| 53 | #define DNET_RX_CRC_ERR_CNT 0x314 | ||
| 54 | #define DNET_RX_OK_PKT_CNT 0x318 | ||
| 55 | #define DNET_RX_CTL_FRM_CNT 0x31C | ||
| 56 | #define DNET_RX_PAUSE_FRM_CNT 0x320 | ||
| 57 | #define DNET_RX_MULTICAST_CNT 0x324 | ||
| 58 | #define DNET_RX_BROADCAST_CNT 0x328 | ||
| 59 | #define DNET_RX_VLAN_TAG_CNT 0x32C | ||
| 60 | #define DNET_RX_PRE_SHRINK_CNT 0x330 | ||
| 61 | #define DNET_RX_DRIB_NIB_CNT 0x334 | ||
| 62 | #define DNET_RX_UNSUP_OPCD_CNT 0x338 | ||
| 63 | #define DNET_RX_BYTE_CNT 0x33C | ||
| 64 | |||
| 65 | /* DNET TX STATISTICS COUNTERS */ | ||
| 66 | #define DNET_TX_UNICAST_CNT 0x400 | ||
| 67 | #define DNET_TX_PAUSE_FRM_CNT 0x404 | ||
| 68 | #define DNET_TX_MULTICAST_CNT 0x408 | ||
| 69 | #define DNET_TX_BRDCAST_CNT 0x40C | ||
| 70 | #define DNET_TX_VLAN_TAG_CNT 0x410 | ||
| 71 | #define DNET_TX_BAD_FCS_CNT 0x414 | ||
| 72 | #define DNET_TX_JUMBO_CNT 0x418 | ||
| 73 | #define DNET_TX_BYTE_CNT 0x41C | ||
| 74 | |||
| 75 | /* SOME INTERNAL MAC-CORE REGISTER */ | ||
| 76 | #define DNET_INTERNAL_MODE_REG 0x0 | ||
| 77 | #define DNET_INTERNAL_RXTX_CONTROL_REG 0x2 | ||
| 78 | #define DNET_INTERNAL_MAX_PKT_SIZE_REG 0x4 | ||
| 79 | #define DNET_INTERNAL_IGP_REG 0x8 | ||
| 80 | #define DNET_INTERNAL_MAC_ADDR_0_REG 0xa | ||
| 81 | #define DNET_INTERNAL_MAC_ADDR_1_REG 0xc | ||
| 82 | #define DNET_INTERNAL_MAC_ADDR_2_REG 0xe | ||
| 83 | #define DNET_INTERNAL_TX_RX_STS_REG 0x12 | ||
| 84 | #define DNET_INTERNAL_GMII_MNG_CTL_REG 0x14 | ||
| 85 | #define DNET_INTERNAL_GMII_MNG_DAT_REG 0x16 | ||
| 86 | |||
| 87 | #define DNET_INTERNAL_GMII_MNG_CMD_FIN (1 << 14) | ||
| 88 | |||
| 89 | #define DNET_INTERNAL_WRITE (1 << 31) | ||
| 90 | |||
| 91 | /* MAC-CORE REGISTER FIELDS */ | ||
| 92 | |||
| 93 | /* MAC-CORE MODE REGISTER FIELDS */ | ||
| 94 | #define DNET_INTERNAL_MODE_GBITEN (1 << 0) | ||
| 95 | #define DNET_INTERNAL_MODE_FCEN (1 << 1) | ||
| 96 | #define DNET_INTERNAL_MODE_RXEN (1 << 2) | ||
| 97 | #define DNET_INTERNAL_MODE_TXEN (1 << 3) | ||
| 98 | |||
| 99 | /* MAC-CORE RXTX CONTROL REGISTER FIELDS */ | ||
| 100 | #define DNET_INTERNAL_RXTX_CONTROL_RXSHORTFRAME (1 << 8) | ||
| 101 | #define DNET_INTERNAL_RXTX_CONTROL_RXBROADCAST (1 << 7) | ||
| 102 | #define DNET_INTERNAL_RXTX_CONTROL_RXMULTICAST (1 << 4) | ||
| 103 | #define DNET_INTERNAL_RXTX_CONTROL_RXPAUSE (1 << 3) | ||
| 104 | #define DNET_INTERNAL_RXTX_CONTROL_DISTXFCS (1 << 2) | ||
| 105 | #define DNET_INTERNAL_RXTX_CONTROL_DISCFXFCS (1 << 1) | ||
| 106 | #define DNET_INTERNAL_RXTX_CONTROL_ENPROMISC (1 << 0) | ||
| 107 | #define DNET_INTERNAL_RXTX_CONTROL_DROPCONTROL (1 << 6) | ||
| 108 | #define DNET_INTERNAL_RXTX_CONTROL_ENABLEHALFDUP (1 << 5) | ||
| 109 | |||
| 110 | /* SYSTEM CONTROL REGISTER FIELDS */ | ||
| 111 | #define DNET_SYS_CTL_IGNORENEXTPKT (1 << 0) | ||
| 112 | #define DNET_SYS_CTL_SENDPAUSE (1 << 2) | ||
| 113 | #define DNET_SYS_CTL_RXFIFOFLUSH (1 << 3) | ||
| 114 | #define DNET_SYS_CTL_TXFIFOFLUSH (1 << 4) | ||
| 115 | |||
| 116 | /* TX STATUS REGISTER FIELDS */ | ||
| 117 | #define DNET_TX_STATUS_FIFO_ALMOST_EMPTY (1 << 2) | ||
| 118 | #define DNET_TX_STATUS_FIFO_ALMOST_FULL (1 << 1) | ||
| 119 | |||
| 120 | /* INTERRUPT SOURCE REGISTER FIELDS */ | ||
| 121 | #define DNET_INTR_SRC_TX_PKTSENT (1 << 0) | ||
| 122 | #define DNET_INTR_SRC_TX_FIFOAF (1 << 1) | ||
| 123 | #define DNET_INTR_SRC_TX_FIFOAE (1 << 2) | ||
| 124 | #define DNET_INTR_SRC_TX_DISCFRM (1 << 3) | ||
| 125 | #define DNET_INTR_SRC_TX_FIFOFULL (1 << 4) | ||
| 126 | #define DNET_INTR_SRC_RX_CMDFIFOAF (1 << 8) | ||
| 127 | #define DNET_INTR_SRC_RX_CMDFIFOFF (1 << 9) | ||
| 128 | #define DNET_INTR_SRC_RX_DATAFIFOFF (1 << 10) | ||
| 129 | #define DNET_INTR_SRC_TX_SUMMARY (1 << 16) | ||
| 130 | #define DNET_INTR_SRC_RX_SUMMARY (1 << 17) | ||
| 131 | #define DNET_INTR_SRC_PHY (1 << 19) | ||
| 132 | |||
| 133 | /* INTERRUPT ENABLE REGISTER FIELDS */ | ||
| 134 | #define DNET_INTR_ENB_TX_PKTSENT (1 << 0) | ||
| 135 | #define DNET_INTR_ENB_TX_FIFOAF (1 << 1) | ||
| 136 | #define DNET_INTR_ENB_TX_FIFOAE (1 << 2) | ||
| 137 | #define DNET_INTR_ENB_TX_DISCFRM (1 << 3) | ||
| 138 | #define DNET_INTR_ENB_TX_FIFOFULL (1 << 4) | ||
| 139 | #define DNET_INTR_ENB_RX_PKTRDY (1 << 8) | ||
| 140 | #define DNET_INTR_ENB_RX_FIFOAF (1 << 9) | ||
| 141 | #define DNET_INTR_ENB_RX_FIFOERR (1 << 10) | ||
| 142 | #define DNET_INTR_ENB_RX_ERROR (1 << 11) | ||
| 143 | #define DNET_INTR_ENB_RX_FIFOFULL (1 << 12) | ||
| 144 | #define DNET_INTR_ENB_RX_FIFOAE (1 << 13) | ||
| 145 | #define DNET_INTR_ENB_TX_SUMMARY (1 << 16) | ||
| 146 | #define DNET_INTR_ENB_RX_SUMMARY (1 << 17) | ||
| 147 | #define DNET_INTR_ENB_GLOBAL_ENABLE (1 << 18) | ||
| 148 | |||
| 149 | /* default values: | ||
| 150 | * almost empty = less than one full sized ethernet frame (no jumbo) inside | ||
| 151 | * the fifo almost full = can write less than one full sized ethernet frame | ||
| 152 | * (no jumbo) inside the fifo | ||
| 153 | */ | ||
| 154 | #define DNET_CFG_TX_FIFO_FULL_THRES 25 | ||
| 155 | #define DNET_CFG_RX_FIFO_FULL_THRES 20 | ||
| 156 | |||
| 157 | /* | ||
| 158 | * Capabilities. Used by the driver to know the capabilities that the ethernet | ||
| 159 | * controller inside the FPGA have. | ||
| 160 | */ | ||
| 161 | |||
| 162 | #define DNET_HAS_MDIO (1 << 0) | ||
| 163 | #define DNET_HAS_IRQ (1 << 1) | ||
| 164 | #define DNET_HAS_GIGABIT (1 << 2) | ||
| 165 | #define DNET_HAS_DMA (1 << 3) | ||
| 166 | |||
| 167 | #define DNET_HAS_MII (1 << 4) /* or GMII */ | ||
| 168 | #define DNET_HAS_RMII (1 << 5) /* or RGMII */ | ||
| 169 | |||
| 170 | #define DNET_CAPS_MASK 0xFFFF | ||
| 171 | |||
| 172 | #define DNET_FIFO_SIZE 1024 /* 1K x 32 bit */ | ||
| 173 | #define DNET_FIFO_TX_DATA_AF_TH (DNET_FIFO_SIZE - 384) /* 384 = 1536 / 4 */ | ||
| 174 | #define DNET_FIFO_TX_DATA_AE_TH 384 | ||
| 175 | |||
| 176 | #define DNET_FIFO_RX_CMD_AF_TH (1 << 16) /* just one frame inside the FIFO */ | ||
| 177 | |||
| 178 | /* | ||
| 179 | * Hardware-collected statistics. | ||
| 180 | */ | ||
| 181 | struct dnet_stats { | ||
| 182 | u32 rx_pkt_ignr; | ||
| 183 | u32 rx_len_chk_err; | ||
| 184 | u32 rx_lng_frm; | ||
| 185 | u32 rx_shrt_frm; | ||
| 186 | u32 rx_ipg_viol; | ||
| 187 | u32 rx_crc_err; | ||
| 188 | u32 rx_ok_pkt; | ||
| 189 | u32 rx_ctl_frm; | ||
| 190 | u32 rx_pause_frm; | ||
| 191 | u32 rx_multicast; | ||
| 192 | u32 rx_broadcast; | ||
| 193 | u32 rx_vlan_tag; | ||
| 194 | u32 rx_pre_shrink; | ||
| 195 | u32 rx_drib_nib; | ||
| 196 | u32 rx_unsup_opcd; | ||
| 197 | u32 rx_byte; | ||
| 198 | u32 tx_unicast; | ||
| 199 | u32 tx_pause_frm; | ||
| 200 | u32 tx_multicast; | ||
| 201 | u32 tx_brdcast; | ||
| 202 | u32 tx_vlan_tag; | ||
| 203 | u32 tx_bad_fcs; | ||
| 204 | u32 tx_jumbo; | ||
| 205 | u32 tx_byte; | ||
| 206 | }; | ||
| 207 | |||
| 208 | struct dnet { | ||
| 209 | void __iomem *regs; | ||
| 210 | spinlock_t lock; | ||
| 211 | struct platform_device *pdev; | ||
| 212 | struct net_device *dev; | ||
| 213 | struct dnet_stats hw_stats; | ||
| 214 | unsigned int capabilities; /* read from FPGA */ | ||
| 215 | struct napi_struct napi; | ||
| 216 | |||
| 217 | /* PHY stuff */ | ||
| 218 | struct mii_bus *mii_bus; | ||
| 219 | struct phy_device *phy_dev; | ||
| 220 | unsigned int link; | ||
| 221 | unsigned int speed; | ||
| 222 | unsigned int duplex; | ||
| 223 | }; | ||
| 224 | |||
| 225 | #endif /* _DNET_H */ | ||
diff --git a/drivers/net/ibm_newemac/core.c b/drivers/net/ibm_newemac/core.c index 87a706694fb3..6fd7aa61736e 100644 --- a/drivers/net/ibm_newemac/core.c +++ b/drivers/net/ibm_newemac/core.c | |||
| @@ -2594,6 +2594,9 @@ static int __devinit emac_init_config(struct emac_instance *dev) | |||
| 2594 | if (of_device_is_compatible(np, "ibm,emac-460ex") || | 2594 | if (of_device_is_compatible(np, "ibm,emac-460ex") || |
| 2595 | of_device_is_compatible(np, "ibm,emac-460gt")) | 2595 | of_device_is_compatible(np, "ibm,emac-460gt")) |
| 2596 | dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX; | 2596 | dev->features |= EMAC_FTR_460EX_PHY_CLK_FIX; |
| 2597 | if (of_device_is_compatible(np, "ibm,emac-405ex") || | ||
| 2598 | of_device_is_compatible(np, "ibm,emac-405exr")) | ||
| 2599 | dev->features |= EMAC_FTR_440EP_PHY_CLK_FIX; | ||
| 2597 | } else if (of_device_is_compatible(np, "ibm,emac4")) { | 2600 | } else if (of_device_is_compatible(np, "ibm,emac4")) { |
| 2598 | dev->features |= EMAC_FTR_EMAC4; | 2601 | dev->features |= EMAC_FTR_EMAC4; |
| 2599 | if (of_device_is_compatible(np, "ibm,emac-440gx")) | 2602 | if (of_device_is_compatible(np, "ibm,emac-440gx")) |
diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c index a50db5398fa5..9dd13ad12ce4 100644 --- a/drivers/net/igb/igb_main.c +++ b/drivers/net/igb/igb_main.c | |||
| @@ -1023,11 +1023,10 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
| 1023 | struct net_device *netdev; | 1023 | struct net_device *netdev; |
| 1024 | struct igb_adapter *adapter; | 1024 | struct igb_adapter *adapter; |
| 1025 | struct e1000_hw *hw; | 1025 | struct e1000_hw *hw; |
| 1026 | struct pci_dev *us_dev; | ||
| 1027 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; | 1026 | const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; |
| 1028 | unsigned long mmio_start, mmio_len; | 1027 | unsigned long mmio_start, mmio_len; |
| 1029 | int i, err, pci_using_dac, pos; | 1028 | int i, err, pci_using_dac; |
| 1030 | u16 eeprom_data = 0, state = 0; | 1029 | u16 eeprom_data = 0; |
| 1031 | u16 eeprom_apme_mask = IGB_EEPROM_APME; | 1030 | u16 eeprom_apme_mask = IGB_EEPROM_APME; |
| 1032 | u32 part_num; | 1031 | u32 part_num; |
| 1033 | int bars, need_ioport; | 1032 | int bars, need_ioport; |
| @@ -1062,27 +1061,6 @@ static int __devinit igb_probe(struct pci_dev *pdev, | |||
| 1062 | } | 1061 | } |
| 1063 | } | 1062 | } |
| 1064 | 1063 | ||
| 1065 | /* 82575 requires that the pci-e link partner disable the L0s state */ | ||
| 1066 | switch (pdev->device) { | ||
| 1067 | case E1000_DEV_ID_82575EB_COPPER: | ||
| 1068 | case E1000_DEV_ID_82575EB_FIBER_SERDES: | ||
| 1069 | case E1000_DEV_ID_82575GB_QUAD_COPPER: | ||
| 1070 | us_dev = pdev->bus->self; | ||
| 1071 | pos = pci_find_capability(us_dev, PCI_CAP_ID_EXP); | ||
| 1072 | if (pos) { | ||
| 1073 | pci_read_config_word(us_dev, pos + PCI_EXP_LNKCTL, | ||
| 1074 | &state); | ||
| 1075 | state &= ~PCIE_LINK_STATE_L0S; | ||
| 1076 | pci_write_config_word(us_dev, pos + PCI_EXP_LNKCTL, | ||
| 1077 | state); | ||
| 1078 | dev_info(&pdev->dev, | ||
| 1079 | "Disabling ASPM L0s upstream switch port %s\n", | ||
| 1080 | pci_name(us_dev)); | ||
| 1081 | } | ||
| 1082 | default: | ||
| 1083 | break; | ||
| 1084 | } | ||
| 1085 | |||
| 1086 | err = pci_request_selected_regions(pdev, bars, igb_driver_name); | 1064 | err = pci_request_selected_regions(pdev, bars, igb_driver_name); |
| 1087 | if (err) | 1065 | if (err) |
| 1088 | goto err_pci_reg; | 1066 | goto err_pci_reg; |
diff --git a/drivers/net/irda/pxaficp_ir.c b/drivers/net/irda/pxaficp_ir.c index 31794c2363ec..e775338b525f 100644 --- a/drivers/net/irda/pxaficp_ir.c +++ b/drivers/net/irda/pxaficp_ir.c | |||
| @@ -24,9 +24,8 @@ | |||
| 24 | 24 | ||
| 25 | #include <mach/dma.h> | 25 | #include <mach/dma.h> |
| 26 | #include <mach/irda.h> | 26 | #include <mach/irda.h> |
| 27 | #include <mach/hardware.h> | ||
| 28 | #include <mach/pxa-regs.h> | ||
| 29 | #include <mach/regs-uart.h> | 27 | #include <mach/regs-uart.h> |
| 28 | #include <mach/regs-ost.h> | ||
| 30 | 29 | ||
| 31 | #define FICP __REG(0x40800000) /* Start of FICP area */ | 30 | #define FICP __REG(0x40800000) /* Start of FICP area */ |
| 32 | #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ | 31 | #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ |
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c index d2f4d5f508b7..5d364a96e35d 100644 --- a/drivers/net/ixgbe/ixgbe_main.c +++ b/drivers/net/ixgbe/ixgbe_main.c | |||
| @@ -3973,6 +3973,7 @@ static const struct net_device_ops ixgbe_netdev_ops = { | |||
| 3973 | .ndo_stop = ixgbe_close, | 3973 | .ndo_stop = ixgbe_close, |
| 3974 | .ndo_start_xmit = ixgbe_xmit_frame, | 3974 | .ndo_start_xmit = ixgbe_xmit_frame, |
| 3975 | .ndo_get_stats = ixgbe_get_stats, | 3975 | .ndo_get_stats = ixgbe_get_stats, |
| 3976 | .ndo_set_rx_mode = ixgbe_set_rx_mode, | ||
| 3976 | .ndo_set_multicast_list = ixgbe_set_rx_mode, | 3977 | .ndo_set_multicast_list = ixgbe_set_rx_mode, |
| 3977 | .ndo_validate_addr = eth_validate_addr, | 3978 | .ndo_validate_addr = eth_validate_addr, |
| 3978 | .ndo_set_mac_address = ixgbe_set_mac, | 3979 | .ndo_set_mac_address = ixgbe_set_mac, |
diff --git a/drivers/net/jme.c b/drivers/net/jme.c index 08b34051c646..a6e1a35a13cb 100644 --- a/drivers/net/jme.c +++ b/drivers/net/jme.c | |||
| @@ -957,13 +957,14 @@ jme_process_receive(struct jme_adapter *jme, int limit) | |||
| 957 | goto out_inc; | 957 | goto out_inc; |
| 958 | 958 | ||
| 959 | i = atomic_read(&rxring->next_to_clean); | 959 | i = atomic_read(&rxring->next_to_clean); |
| 960 | while (limit-- > 0) { | 960 | while (limit > 0) { |
| 961 | rxdesc = rxring->desc; | 961 | rxdesc = rxring->desc; |
| 962 | rxdesc += i; | 962 | rxdesc += i; |
| 963 | 963 | ||
| 964 | if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) || | 964 | if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) || |
| 965 | !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL)) | 965 | !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL)) |
| 966 | goto out; | 966 | goto out; |
| 967 | --limit; | ||
| 967 | 968 | ||
| 968 | desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT; | 969 | desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT; |
| 969 | 970 | ||
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c index 13f11f402a99..b0bc3bc18e9c 100644 --- a/drivers/net/mv643xx_eth.c +++ b/drivers/net/mv643xx_eth.c | |||
| @@ -2030,11 +2030,6 @@ static void port_start(struct mv643xx_eth_private *mp) | |||
| 2030 | } | 2030 | } |
| 2031 | 2031 | ||
| 2032 | /* | 2032 | /* |
| 2033 | * Add configured unicast address to address filter table. | ||
| 2034 | */ | ||
| 2035 | mv643xx_eth_program_unicast_filter(mp->dev); | ||
| 2036 | |||
| 2037 | /* | ||
| 2038 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast | 2033 | * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast |
| 2039 | * frames to RX queue #0, and include the pseudo-header when | 2034 | * frames to RX queue #0, and include the pseudo-header when |
| 2040 | * calculating receive checksums. | 2035 | * calculating receive checksums. |
| @@ -2047,6 +2042,11 @@ static void port_start(struct mv643xx_eth_private *mp) | |||
| 2047 | wrlp(mp, PORT_CONFIG_EXT, 0x00000000); | 2042 | wrlp(mp, PORT_CONFIG_EXT, 0x00000000); |
| 2048 | 2043 | ||
| 2049 | /* | 2044 | /* |
| 2045 | * Add configured unicast addresses to address filter table. | ||
| 2046 | */ | ||
| 2047 | mv643xx_eth_program_unicast_filter(mp->dev); | ||
| 2048 | |||
| 2049 | /* | ||
| 2050 | * Enable the receive queues. | 2050 | * Enable the receive queues. |
| 2051 | */ | 2051 | */ |
| 2052 | for (i = 0; i < mp->rxq_count; i++) { | 2052 | for (i = 0; i < mp->rxq_count; i++) { |
diff --git a/drivers/net/netxen/netxen_nic.h b/drivers/net/netxen/netxen_nic.h index f4dd9acb6877..1ff066b2281a 100644 --- a/drivers/net/netxen/netxen_nic.h +++ b/drivers/net/netxen/netxen_nic.h | |||
| @@ -1595,7 +1595,6 @@ dma_watchdog_wakeup(struct netxen_adapter *adapter) | |||
| 1595 | } | 1595 | } |
| 1596 | 1596 | ||
| 1597 | 1597 | ||
| 1598 | int netxen_is_flash_supported(struct netxen_adapter *adapter); | ||
| 1599 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac); | 1598 | int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac); |
| 1600 | int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac); | 1599 | int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac); |
| 1601 | extern void netxen_change_ringparam(struct netxen_adapter *adapter); | 1600 | extern void netxen_change_ringparam(struct netxen_adapter *adapter); |
diff --git a/drivers/net/netxen/netxen_nic_hw.c b/drivers/net/netxen/netxen_nic_hw.c index 821cff68b3f3..7fea77088108 100644 --- a/drivers/net/netxen/netxen_nic_hw.c +++ b/drivers/net/netxen/netxen_nic_hw.c | |||
| @@ -706,28 +706,6 @@ int netxen_nic_change_mtu(struct net_device *netdev, int mtu) | |||
| 706 | return rc; | 706 | return rc; |
| 707 | } | 707 | } |
| 708 | 708 | ||
| 709 | int netxen_is_flash_supported(struct netxen_adapter *adapter) | ||
| 710 | { | ||
| 711 | const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 }; | ||
| 712 | int addr, val01, val02, i, j; | ||
| 713 | |||
| 714 | /* if the flash size less than 4Mb, make huge war cry and die */ | ||
| 715 | for (j = 1; j < 4; j++) { | ||
| 716 | addr = j * NETXEN_NIC_WINDOW_MARGIN; | ||
| 717 | for (i = 0; i < ARRAY_SIZE(locs); i++) { | ||
| 718 | if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0 | ||
| 719 | && netxen_rom_fast_read(adapter, (addr + locs[i]), | ||
| 720 | &val02) == 0) { | ||
| 721 | if (val01 == val02) | ||
| 722 | return -1; | ||
| 723 | } else | ||
| 724 | return -1; | ||
| 725 | } | ||
| 726 | } | ||
| 727 | |||
| 728 | return 0; | ||
| 729 | } | ||
| 730 | |||
| 731 | static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, | 709 | static int netxen_get_flash_block(struct netxen_adapter *adapter, int base, |
| 732 | int size, __le32 * buf) | 710 | int size, __le32 * buf) |
| 733 | { | 711 | { |
diff --git a/drivers/net/netxen/netxen_nic_main.c b/drivers/net/netxen/netxen_nic_main.c index 13087782ac40..c172b6e24a96 100644 --- a/drivers/net/netxen/netxen_nic_main.c +++ b/drivers/net/netxen/netxen_nic_main.c | |||
| @@ -405,9 +405,6 @@ netxen_read_mac_addr(struct netxen_adapter *adapter) | |||
| 405 | struct net_device *netdev = adapter->netdev; | 405 | struct net_device *netdev = adapter->netdev; |
| 406 | struct pci_dev *pdev = adapter->pdev; | 406 | struct pci_dev *pdev = adapter->pdev; |
| 407 | 407 | ||
| 408 | if (netxen_is_flash_supported(adapter) != 0) | ||
| 409 | return -EIO; | ||
| 410 | |||
| 411 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { | 408 | if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) { |
| 412 | if (netxen_p3_get_mac_addr(adapter, &mac_addr) != 0) | 409 | if (netxen_p3_get_mac_addr(adapter, &mac_addr) != 0) |
| 413 | return -EIO; | 410 | return -EIO; |
diff --git a/drivers/net/pcmcia/3c574_cs.c b/drivers/net/pcmcia/3c574_cs.c index e5cb6b1f0ebd..2404a838b1fe 100644 --- a/drivers/net/pcmcia/3c574_cs.c +++ b/drivers/net/pcmcia/3c574_cs.c | |||
| @@ -1035,7 +1035,8 @@ static int el3_rx(struct net_device *dev, int worklimit) | |||
| 1035 | DEBUG(3, "%s: in rx_packet(), status %4.4x, rx_status %4.4x.\n", | 1035 | DEBUG(3, "%s: in rx_packet(), status %4.4x, rx_status %4.4x.\n", |
| 1036 | dev->name, inw(ioaddr+EL3_STATUS), inw(ioaddr+RxStatus)); | 1036 | dev->name, inw(ioaddr+EL3_STATUS), inw(ioaddr+RxStatus)); |
| 1037 | while (!((rx_status = inw(ioaddr + RxStatus)) & 0x8000) && | 1037 | while (!((rx_status = inw(ioaddr + RxStatus)) & 0x8000) && |
| 1038 | (--worklimit >= 0)) { | 1038 | worklimit > 0) { |
| 1039 | worklimit--; | ||
| 1039 | if (rx_status & 0x4000) { /* Error, update stats. */ | 1040 | if (rx_status & 0x4000) { /* Error, update stats. */ |
| 1040 | short error = rx_status & 0x3800; | 1041 | short error = rx_status & 0x3800; |
| 1041 | dev->stats.rx_errors++; | 1042 | dev->stats.rx_errors++; |
diff --git a/drivers/net/pcmcia/3c589_cs.c b/drivers/net/pcmcia/3c589_cs.c index 73ecc657999d..1e01b8a6dbf3 100644 --- a/drivers/net/pcmcia/3c589_cs.c +++ b/drivers/net/pcmcia/3c589_cs.c | |||
| @@ -857,7 +857,8 @@ static int el3_rx(struct net_device *dev) | |||
| 857 | DEBUG(3, "%s: in rx_packet(), status %4.4x, rx_status %4.4x.\n", | 857 | DEBUG(3, "%s: in rx_packet(), status %4.4x, rx_status %4.4x.\n", |
| 858 | dev->name, inw(ioaddr+EL3_STATUS), inw(ioaddr+RX_STATUS)); | 858 | dev->name, inw(ioaddr+EL3_STATUS), inw(ioaddr+RX_STATUS)); |
| 859 | while (!((rx_status = inw(ioaddr + RX_STATUS)) & 0x8000) && | 859 | while (!((rx_status = inw(ioaddr + RX_STATUS)) & 0x8000) && |
| 860 | (--worklimit >= 0)) { | 860 | worklimit > 0) { |
| 861 | worklimit--; | ||
| 861 | if (rx_status & 0x4000) { /* Error, update stats. */ | 862 | if (rx_status & 0x4000) { /* Error, update stats. */ |
| 862 | short error = rx_status & 0x3800; | 863 | short error = rx_status & 0x3800; |
| 863 | dev->stats.rx_errors++; | 864 | dev->stats.rx_errors++; |
diff --git a/drivers/net/qlge/qlge.h b/drivers/net/qlge/qlge.h index e6fdce9206cc..aff9c5fec738 100644 --- a/drivers/net/qlge/qlge.h +++ b/drivers/net/qlge/qlge.h | |||
| @@ -927,6 +927,7 @@ struct ib_mac_iocb_rsp { | |||
| 927 | u8 flags1; | 927 | u8 flags1; |
| 928 | #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */ | 928 | #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */ |
| 929 | #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */ | 929 | #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */ |
| 930 | #define IB_MAC_CSUM_ERR_MASK 0x1c /* A mask to use for csum errs */ | ||
| 930 | #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */ | 931 | #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */ |
| 931 | #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */ | 932 | #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */ |
| 932 | #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */ | 933 | #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */ |
diff --git a/drivers/net/qlge/qlge_main.c b/drivers/net/qlge/qlge_main.c index 8ea72dc60f79..91191f761fba 100644 --- a/drivers/net/qlge/qlge_main.c +++ b/drivers/net/qlge/qlge_main.c | |||
| @@ -1436,18 +1436,32 @@ static void ql_process_mac_rx_intr(struct ql_adapter *qdev, | |||
| 1436 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) { | 1436 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) { |
| 1437 | QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n"); | 1437 | QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n"); |
| 1438 | } | 1438 | } |
| 1439 | if (ib_mac_rsp->flags1 & (IB_MAC_IOCB_RSP_IE | IB_MAC_IOCB_RSP_TE)) { | 1439 | |
| 1440 | QPRINTK(qdev, RX_STATUS, ERR, | 1440 | skb->protocol = eth_type_trans(skb, ndev); |
| 1441 | "Bad checksum for this %s packet.\n", | 1441 | skb->ip_summed = CHECKSUM_NONE; |
| 1442 | ((ib_mac_rsp-> | 1442 | |
| 1443 | flags2 & IB_MAC_IOCB_RSP_T) ? "TCP" : "UDP")); | 1443 | /* If rx checksum is on, and there are no |
| 1444 | skb->ip_summed = CHECKSUM_NONE; | 1444 | * csum or frame errors. |
| 1445 | } else if (qdev->rx_csum && | 1445 | */ |
| 1446 | ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) || | 1446 | if (qdev->rx_csum && |
| 1447 | ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) && | 1447 | !(ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) && |
| 1448 | !(ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU)))) { | 1448 | !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) { |
| 1449 | QPRINTK(qdev, RX_STATUS, DEBUG, "RX checksum done!\n"); | 1449 | /* TCP frame. */ |
| 1450 | skb->ip_summed = CHECKSUM_UNNECESSARY; | 1450 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) { |
| 1451 | QPRINTK(qdev, RX_STATUS, DEBUG, | ||
| 1452 | "TCP checksum done!\n"); | ||
| 1453 | skb->ip_summed = CHECKSUM_UNNECESSARY; | ||
| 1454 | } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) && | ||
| 1455 | (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) { | ||
| 1456 | /* Unfragmented ipv4 UDP frame. */ | ||
| 1457 | struct iphdr *iph = (struct iphdr *) skb->data; | ||
| 1458 | if (!(iph->frag_off & | ||
| 1459 | cpu_to_be16(IP_MF|IP_OFFSET))) { | ||
| 1460 | skb->ip_summed = CHECKSUM_UNNECESSARY; | ||
| 1461 | QPRINTK(qdev, RX_STATUS, DEBUG, | ||
| 1462 | "TCP checksum done!\n"); | ||
| 1463 | } | ||
| 1464 | } | ||
| 1451 | } | 1465 | } |
| 1452 | qdev->stats.rx_packets++; | 1466 | qdev->stats.rx_packets++; |
| 1453 | qdev->stats.rx_bytes += skb->len; | 1467 | qdev->stats.rx_bytes += skb->len; |
| @@ -1927,6 +1941,9 @@ static int qlge_send(struct sk_buff *skb, struct net_device *ndev) | |||
| 1927 | 1941 | ||
| 1928 | tx_ring = &qdev->tx_ring[tx_ring_idx]; | 1942 | tx_ring = &qdev->tx_ring[tx_ring_idx]; |
| 1929 | 1943 | ||
| 1944 | if (skb_padto(skb, ETH_ZLEN)) | ||
| 1945 | return NETDEV_TX_OK; | ||
| 1946 | |||
| 1930 | if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) { | 1947 | if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) { |
| 1931 | QPRINTK(qdev, TX_QUEUED, INFO, | 1948 | QPRINTK(qdev, TX_QUEUED, INFO, |
| 1932 | "%s: shutting down tx queue %d du to lack of resources.\n", | 1949 | "%s: shutting down tx queue %d du to lack of resources.\n", |
| @@ -2970,9 +2987,9 @@ static int ql_adapter_initialize(struct ql_adapter *qdev) | |||
| 2970 | mask = value << 16; | 2987 | mask = value << 16; |
| 2971 | ql_write32(qdev, SYS, mask | value); | 2988 | ql_write32(qdev, SYS, mask | value); |
| 2972 | 2989 | ||
| 2973 | /* Set the default queue. */ | 2990 | /* Set the default queue, and VLAN behavior. */ |
| 2974 | value = NIC_RCV_CFG_DFQ; | 2991 | value = NIC_RCV_CFG_DFQ | NIC_RCV_CFG_RV; |
| 2975 | mask = NIC_RCV_CFG_DFQ_MASK; | 2992 | mask = NIC_RCV_CFG_DFQ_MASK | (NIC_RCV_CFG_RV << 16); |
| 2976 | ql_write32(qdev, NIC_RCV_CFG, (mask | value)); | 2993 | ql_write32(qdev, NIC_RCV_CFG, (mask | value)); |
| 2977 | 2994 | ||
| 2978 | /* Set the MPI interrupt to enabled. */ | 2995 | /* Set the MPI interrupt to enabled. */ |
| @@ -3149,6 +3166,11 @@ static int ql_adapter_down(struct ql_adapter *qdev) | |||
| 3149 | 3166 | ||
| 3150 | ql_tx_ring_clean(qdev); | 3167 | ql_tx_ring_clean(qdev); |
| 3151 | 3168 | ||
| 3169 | /* Call netif_napi_del() from common point. | ||
| 3170 | */ | ||
| 3171 | for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) | ||
| 3172 | netif_napi_del(&qdev->rx_ring[i].napi); | ||
| 3173 | |||
| 3152 | spin_lock(&qdev->hw_lock); | 3174 | spin_lock(&qdev->hw_lock); |
| 3153 | status = ql_adapter_reset(qdev); | 3175 | status = ql_adapter_reset(qdev); |
| 3154 | if (status) | 3176 | if (status) |
| @@ -3853,7 +3875,7 @@ static int qlge_suspend(struct pci_dev *pdev, pm_message_t state) | |||
| 3853 | { | 3875 | { |
| 3854 | struct net_device *ndev = pci_get_drvdata(pdev); | 3876 | struct net_device *ndev = pci_get_drvdata(pdev); |
| 3855 | struct ql_adapter *qdev = netdev_priv(ndev); | 3877 | struct ql_adapter *qdev = netdev_priv(ndev); |
| 3856 | int err, i; | 3878 | int err; |
| 3857 | 3879 | ||
| 3858 | netif_device_detach(ndev); | 3880 | netif_device_detach(ndev); |
| 3859 | 3881 | ||
| @@ -3863,9 +3885,6 @@ static int qlge_suspend(struct pci_dev *pdev, pm_message_t state) | |||
| 3863 | return err; | 3885 | return err; |
| 3864 | } | 3886 | } |
| 3865 | 3887 | ||
| 3866 | for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) | ||
| 3867 | netif_napi_del(&qdev->rx_ring[i].napi); | ||
| 3868 | |||
| 3869 | err = pci_save_state(pdev); | 3888 | err = pci_save_state(pdev); |
| 3870 | if (err) | 3889 | if (err) |
| 3871 | return err; | 3890 | return err; |
diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c index b3473401c83a..43fedb9ecedb 100644 --- a/drivers/net/r8169.c +++ b/drivers/net/r8169.c | |||
| @@ -81,9 +81,9 @@ static const int multicast_filter_limit = 32; | |||
| 81 | #define RTL8169_TX_TIMEOUT (6*HZ) | 81 | #define RTL8169_TX_TIMEOUT (6*HZ) |
| 82 | #define RTL8169_PHY_TIMEOUT (10*HZ) | 82 | #define RTL8169_PHY_TIMEOUT (10*HZ) |
| 83 | 83 | ||
| 84 | #define RTL_EEPROM_SIG 0x8129 | 84 | #define RTL_EEPROM_SIG cpu_to_le32(0x8129) |
| 85 | #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) | ||
| 85 | #define RTL_EEPROM_SIG_ADDR 0x0000 | 86 | #define RTL_EEPROM_SIG_ADDR 0x0000 |
| 86 | #define RTL_EEPROM_MAC_ADDR 0x0007 | ||
| 87 | 87 | ||
| 88 | /* write/read MMIO register */ | 88 | /* write/read MMIO register */ |
| 89 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) | 89 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) |
| @@ -293,11 +293,6 @@ enum rtl_register_content { | |||
| 293 | /* Cfg9346Bits */ | 293 | /* Cfg9346Bits */ |
| 294 | Cfg9346_Lock = 0x00, | 294 | Cfg9346_Lock = 0x00, |
| 295 | Cfg9346_Unlock = 0xc0, | 295 | Cfg9346_Unlock = 0xc0, |
| 296 | Cfg9346_Program = 0x80, /* Programming mode */ | ||
| 297 | Cfg9346_EECS = 0x08, /* Chip select */ | ||
| 298 | Cfg9346_EESK = 0x04, /* Serial data clock */ | ||
| 299 | Cfg9346_EEDI = 0x02, /* Data input */ | ||
| 300 | Cfg9346_EEDO = 0x01, /* Data output */ | ||
| 301 | 296 | ||
| 302 | /* rx_mode_bits */ | 297 | /* rx_mode_bits */ |
| 303 | AcceptErr = 0x20, | 298 | AcceptErr = 0x20, |
| @@ -310,7 +305,6 @@ enum rtl_register_content { | |||
| 310 | /* RxConfigBits */ | 305 | /* RxConfigBits */ |
| 311 | RxCfgFIFOShift = 13, | 306 | RxCfgFIFOShift = 13, |
| 312 | RxCfgDMAShift = 8, | 307 | RxCfgDMAShift = 8, |
| 313 | RxCfg9356SEL = 6, /* EEPROM type: 0 = 9346, 1 = 9356 */ | ||
| 314 | 308 | ||
| 315 | /* TxConfigBits */ | 309 | /* TxConfigBits */ |
| 316 | TxInterFrameGapShift = 24, | 310 | TxInterFrameGapShift = 24, |
| @@ -1969,108 +1963,6 @@ static const struct net_device_ops rtl8169_netdev_ops = { | |||
| 1969 | 1963 | ||
| 1970 | }; | 1964 | }; |
| 1971 | 1965 | ||
| 1972 | /* Delay between EEPROM clock transitions. Force out buffered PCI writes. */ | ||
| 1973 | #define RTL_EEPROM_DELAY() RTL_R8(Cfg9346) | ||
| 1974 | #define RTL_EEPROM_READ_CMD 6 | ||
| 1975 | |||
| 1976 | /* read 16bit word stored in EEPROM. EEPROM is addressed by words. */ | ||
| 1977 | static u16 rtl_eeprom_read(void __iomem *ioaddr, int addr) | ||
| 1978 | { | ||
| 1979 | u16 result = 0; | ||
| 1980 | int cmd, cmd_len, i; | ||
| 1981 | |||
| 1982 | /* check for EEPROM address size (in bits) */ | ||
| 1983 | if (RTL_R32(RxConfig) & (1 << RxCfg9356SEL)) { | ||
| 1984 | /* EEPROM is 93C56 */ | ||
| 1985 | cmd_len = 3 + 8; /* 3 bits for command id and 8 for address */ | ||
| 1986 | cmd = (RTL_EEPROM_READ_CMD << 8) | (addr & 0xff); | ||
| 1987 | } else { | ||
| 1988 | /* EEPROM is 93C46 */ | ||
| 1989 | cmd_len = 3 + 6; /* 3 bits for command id and 6 for address */ | ||
| 1990 | cmd = (RTL_EEPROM_READ_CMD << 6) | (addr & 0x3f); | ||
| 1991 | } | ||
| 1992 | |||
| 1993 | /* enter programming mode */ | ||
| 1994 | RTL_W8(Cfg9346, Cfg9346_Program | Cfg9346_EECS); | ||
| 1995 | RTL_EEPROM_DELAY(); | ||
| 1996 | |||
| 1997 | /* write command and requested address */ | ||
| 1998 | while (cmd_len--) { | ||
| 1999 | u8 x = Cfg9346_Program | Cfg9346_EECS; | ||
| 2000 | |||
| 2001 | x |= (cmd & (1 << cmd_len)) ? Cfg9346_EEDI : 0; | ||
| 2002 | |||
| 2003 | /* write a bit */ | ||
| 2004 | RTL_W8(Cfg9346, x); | ||
| 2005 | RTL_EEPROM_DELAY(); | ||
| 2006 | |||
| 2007 | /* raise clock */ | ||
| 2008 | RTL_W8(Cfg9346, x | Cfg9346_EESK); | ||
| 2009 | RTL_EEPROM_DELAY(); | ||
| 2010 | } | ||
| 2011 | |||
| 2012 | /* lower clock */ | ||
| 2013 | RTL_W8(Cfg9346, Cfg9346_Program | Cfg9346_EECS); | ||
| 2014 | RTL_EEPROM_DELAY(); | ||
| 2015 | |||
| 2016 | /* read back 16bit value */ | ||
| 2017 | for (i = 16; i > 0; i--) { | ||
| 2018 | /* raise clock */ | ||
| 2019 | RTL_W8(Cfg9346, Cfg9346_Program | Cfg9346_EECS | Cfg9346_EESK); | ||
| 2020 | RTL_EEPROM_DELAY(); | ||
| 2021 | |||
| 2022 | result <<= 1; | ||
| 2023 | result |= (RTL_R8(Cfg9346) & Cfg9346_EEDO) ? 1 : 0; | ||
| 2024 | |||
| 2025 | /* lower clock */ | ||
| 2026 | RTL_W8(Cfg9346, Cfg9346_Program | Cfg9346_EECS); | ||
| 2027 | RTL_EEPROM_DELAY(); | ||
| 2028 | } | ||
| 2029 | |||
| 2030 | RTL_W8(Cfg9346, Cfg9346_Program); | ||
| 2031 | /* leave programming mode */ | ||
| 2032 | RTL_W8(Cfg9346, Cfg9346_Lock); | ||
| 2033 | |||
| 2034 | return result; | ||
| 2035 | } | ||
| 2036 | |||
| 2037 | static void rtl_init_mac_address(struct rtl8169_private *tp, | ||
| 2038 | void __iomem *ioaddr) | ||
| 2039 | { | ||
| 2040 | struct pci_dev *pdev = tp->pci_dev; | ||
| 2041 | u16 x; | ||
| 2042 | u8 mac[8]; | ||
| 2043 | |||
| 2044 | /* read EEPROM signature */ | ||
| 2045 | x = rtl_eeprom_read(ioaddr, RTL_EEPROM_SIG_ADDR); | ||
| 2046 | |||
| 2047 | if (x != RTL_EEPROM_SIG) { | ||
| 2048 | dev_info(&pdev->dev, "Missing EEPROM signature: %04x\n", x); | ||
| 2049 | return; | ||
| 2050 | } | ||
| 2051 | |||
| 2052 | /* read MAC address */ | ||
| 2053 | x = rtl_eeprom_read(ioaddr, RTL_EEPROM_MAC_ADDR); | ||
| 2054 | mac[0] = x & 0xff; | ||
| 2055 | mac[1] = x >> 8; | ||
| 2056 | x = rtl_eeprom_read(ioaddr, RTL_EEPROM_MAC_ADDR + 1); | ||
| 2057 | mac[2] = x & 0xff; | ||
| 2058 | mac[3] = x >> 8; | ||
| 2059 | x = rtl_eeprom_read(ioaddr, RTL_EEPROM_MAC_ADDR + 2); | ||
| 2060 | mac[4] = x & 0xff; | ||
| 2061 | mac[5] = x >> 8; | ||
| 2062 | |||
| 2063 | if (netif_msg_probe(tp)) { | ||
| 2064 | DECLARE_MAC_BUF(buf); | ||
| 2065 | |||
| 2066 | dev_info(&pdev->dev, "MAC address found in EEPROM: %s\n", | ||
| 2067 | print_mac(buf, mac)); | ||
| 2068 | } | ||
| 2069 | |||
| 2070 | if (is_valid_ether_addr(mac)) | ||
| 2071 | rtl_rar_set(tp, mac); | ||
| 2072 | } | ||
| 2073 | |||
| 2074 | static int __devinit | 1966 | static int __devinit |
| 2075 | rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | 1967 | rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
| 2076 | { | 1968 | { |
| @@ -2249,8 +2141,6 @@ rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
| 2249 | 2141 | ||
| 2250 | tp->mmio_addr = ioaddr; | 2142 | tp->mmio_addr = ioaddr; |
| 2251 | 2143 | ||
| 2252 | rtl_init_mac_address(tp, ioaddr); | ||
| 2253 | |||
| 2254 | /* Get MAC address */ | 2144 | /* Get MAC address */ |
| 2255 | for (i = 0; i < MAC_ADDR_LEN; i++) | 2145 | for (i = 0; i < MAC_ADDR_LEN; i++) |
| 2256 | dev->dev_addr[i] = RTL_R8(MAC0 + i); | 2146 | dev->dev_addr[i] = RTL_R8(MAC0 + i); |
| @@ -3363,13 +3253,6 @@ static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev) | |||
| 3363 | opts1 |= FirstFrag; | 3253 | opts1 |= FirstFrag; |
| 3364 | } else { | 3254 | } else { |
| 3365 | len = skb->len; | 3255 | len = skb->len; |
| 3366 | |||
| 3367 | if (unlikely(len < ETH_ZLEN)) { | ||
| 3368 | if (skb_padto(skb, ETH_ZLEN)) | ||
| 3369 | goto err_update_stats; | ||
| 3370 | len = ETH_ZLEN; | ||
| 3371 | } | ||
| 3372 | |||
| 3373 | opts1 |= FirstFrag | LastFrag; | 3256 | opts1 |= FirstFrag | LastFrag; |
| 3374 | tp->tx_skb[entry].skb = skb; | 3257 | tp->tx_skb[entry].skb = skb; |
| 3375 | } | 3258 | } |
| @@ -3407,7 +3290,6 @@ out: | |||
| 3407 | err_stop: | 3290 | err_stop: |
| 3408 | netif_stop_queue(dev); | 3291 | netif_stop_queue(dev); |
| 3409 | ret = NETDEV_TX_BUSY; | 3292 | ret = NETDEV_TX_BUSY; |
| 3410 | err_update_stats: | ||
| 3411 | dev->stats.tx_dropped++; | 3293 | dev->stats.tx_dropped++; |
| 3412 | goto out; | 3294 | goto out; |
| 3413 | } | 3295 | } |
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 7f8e514eb5e9..7b1882765a0c 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c | |||
| @@ -687,6 +687,7 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev) | |||
| 687 | { | 687 | { |
| 688 | struct net_device *ndev = netdev; | 688 | struct net_device *ndev = netdev; |
| 689 | struct sh_eth_private *mdp = netdev_priv(ndev); | 689 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 690 | irqreturn_t ret = IRQ_NONE; | ||
| 690 | u32 ioaddr, boguscnt = RX_RING_SIZE; | 691 | u32 ioaddr, boguscnt = RX_RING_SIZE; |
| 691 | u32 intr_status = 0; | 692 | u32 intr_status = 0; |
| 692 | 693 | ||
| @@ -696,7 +697,13 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev) | |||
| 696 | /* Get interrpt stat */ | 697 | /* Get interrpt stat */ |
| 697 | intr_status = ctrl_inl(ioaddr + EESR); | 698 | intr_status = ctrl_inl(ioaddr + EESR); |
| 698 | /* Clear interrupt */ | 699 | /* Clear interrupt */ |
| 699 | ctrl_outl(intr_status, ioaddr + EESR); | 700 | if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF | |
| 701 | EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF | | ||
| 702 | TX_CHECK | EESR_ERR_CHECK)) { | ||
| 703 | ctrl_outl(intr_status, ioaddr + EESR); | ||
| 704 | ret = IRQ_HANDLED; | ||
| 705 | } else | ||
| 706 | goto other_irq; | ||
| 700 | 707 | ||
| 701 | if (intr_status & (EESR_FRC | /* Frame recv*/ | 708 | if (intr_status & (EESR_FRC | /* Frame recv*/ |
| 702 | EESR_RMAF | /* Multi cast address recv*/ | 709 | EESR_RMAF | /* Multi cast address recv*/ |
| @@ -723,9 +730,10 @@ static irqreturn_t sh_eth_interrupt(int irq, void *netdev) | |||
| 723 | ndev->name, intr_status); | 730 | ndev->name, intr_status); |
| 724 | } | 731 | } |
| 725 | 732 | ||
| 733 | other_irq: | ||
| 726 | spin_unlock(&mdp->lock); | 734 | spin_unlock(&mdp->lock); |
| 727 | 735 | ||
| 728 | return IRQ_HANDLED; | 736 | return ret; |
| 729 | } | 737 | } |
| 730 | 738 | ||
| 731 | static void sh_eth_timer(unsigned long data) | 739 | static void sh_eth_timer(unsigned long data) |
| @@ -844,7 +852,13 @@ static int sh_eth_open(struct net_device *ndev) | |||
| 844 | int ret = 0; | 852 | int ret = 0; |
| 845 | struct sh_eth_private *mdp = netdev_priv(ndev); | 853 | struct sh_eth_private *mdp = netdev_priv(ndev); |
| 846 | 854 | ||
| 847 | ret = request_irq(ndev->irq, &sh_eth_interrupt, 0, ndev->name, ndev); | 855 | ret = request_irq(ndev->irq, &sh_eth_interrupt, |
| 856 | #if defined(CONFIG_CPU_SUBTYPE_SH7763) || defined(CONFIG_CPU_SUBTYPE_SH7764) | ||
| 857 | IRQF_SHARED, | ||
| 858 | #else | ||
| 859 | 0, | ||
| 860 | #endif | ||
| 861 | ndev->name, ndev); | ||
| 848 | if (ret) { | 862 | if (ret) { |
| 849 | printk(KERN_ERR "Can not assign IRQ number to %s\n", CARDNAME); | 863 | printk(KERN_ERR "Can not assign IRQ number to %s\n", CARDNAME); |
| 850 | return ret; | 864 | return ret; |
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 73bc7181cc18..1537e13e623d 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h | |||
| @@ -43,8 +43,8 @@ | |||
| 43 | 43 | ||
| 44 | #define SH7763_SKB_ALIGN 32 | 44 | #define SH7763_SKB_ALIGN 32 |
| 45 | /* Chip Base Address */ | 45 | /* Chip Base Address */ |
| 46 | # define SH_TSU_ADDR 0xFFE01800 | 46 | # define SH_TSU_ADDR 0xFEE01800 |
| 47 | # define ARSTR 0xFFE01800 | 47 | # define ARSTR SH_TSU_ADDR |
| 48 | 48 | ||
| 49 | /* Chip Registers */ | 49 | /* Chip Registers */ |
| 50 | /* E-DMAC */ | 50 | /* E-DMAC */ |
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h index 870b4c33f108..8140f7cb4d85 100644 --- a/drivers/net/smc911x.h +++ b/drivers/net/smc911x.h | |||
| @@ -42,6 +42,16 @@ | |||
| 42 | #define SMC_USE_16BIT 0 | 42 | #define SMC_USE_16BIT 0 |
| 43 | #define SMC_USE_32BIT 1 | 43 | #define SMC_USE_32BIT 1 |
| 44 | #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW | 44 | #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW |
| 45 | #elif defined(CONFIG_ARCH_OMAP34XX) | ||
| 46 | #define SMC_USE_16BIT 0 | ||
| 47 | #define SMC_USE_32BIT 1 | ||
| 48 | #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW | ||
| 49 | #define SMC_MEM_RESERVED 1 | ||
| 50 | #elif defined(CONFIG_ARCH_OMAP24XX) | ||
| 51 | #define SMC_USE_16BIT 0 | ||
| 52 | #define SMC_USE_32BIT 1 | ||
| 53 | #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW | ||
| 54 | #define SMC_MEM_RESERVED 1 | ||
| 45 | #else | 55 | #else |
| 46 | /* | 56 | /* |
| 47 | * Default configuration | 57 | * Default configuration |
| @@ -226,8 +236,7 @@ static inline void SMC_outsl(struct smc911x_local *lp, int reg, | |||
| 226 | * Use a DMA for RX and TX packets. | 236 | * Use a DMA for RX and TX packets. |
| 227 | */ | 237 | */ |
| 228 | #include <linux/dma-mapping.h> | 238 | #include <linux/dma-mapping.h> |
| 229 | #include <asm/dma.h> | 239 | #include <mach/dma.h> |
| 230 | #include <mach/pxa-regs.h> | ||
| 231 | 240 | ||
| 232 | static dma_addr_t rx_dmabuf, tx_dmabuf; | 241 | static dma_addr_t rx_dmabuf, tx_dmabuf; |
| 233 | static int rx_dmalen, tx_dmalen; | 242 | static int rx_dmalen, tx_dmalen; |
| @@ -675,6 +684,7 @@ smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr, | |||
| 675 | #define CHIP_9116 0x0116 | 684 | #define CHIP_9116 0x0116 |
| 676 | #define CHIP_9117 0x0117 | 685 | #define CHIP_9117 0x0117 |
| 677 | #define CHIP_9118 0x0118 | 686 | #define CHIP_9118 0x0118 |
| 687 | #define CHIP_9211 0x9211 | ||
| 678 | #define CHIP_9215 0x115A | 688 | #define CHIP_9215 0x115A |
| 679 | #define CHIP_9217 0x117A | 689 | #define CHIP_9217 0x117A |
| 680 | #define CHIP_9218 0x118A | 690 | #define CHIP_9218 0x118A |
| @@ -689,6 +699,7 @@ static const struct chip_id chip_ids[] = { | |||
| 689 | { CHIP_9116, "LAN9116" }, | 699 | { CHIP_9116, "LAN9116" }, |
| 690 | { CHIP_9117, "LAN9117" }, | 700 | { CHIP_9117, "LAN9117" }, |
| 691 | { CHIP_9118, "LAN9118" }, | 701 | { CHIP_9118, "LAN9118" }, |
| 702 | { CHIP_9211, "LAN9211" }, | ||
| 692 | { CHIP_9215, "LAN9215" }, | 703 | { CHIP_9215, "LAN9215" }, |
| 693 | { CHIP_9217, "LAN9217" }, | 704 | { CHIP_9217, "LAN9217" }, |
| 694 | { CHIP_9218, "LAN9218" }, | 705 | { CHIP_9218, "LAN9218" }, |
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h index c4ccd121bc9c..1083e2c5dec6 100644 --- a/drivers/net/smc91x.h +++ b/drivers/net/smc91x.h | |||
| @@ -44,6 +44,7 @@ | |||
| 44 | defined(CONFIG_MACH_MAINSTONE) ||\ | 44 | defined(CONFIG_MACH_MAINSTONE) ||\ |
| 45 | defined(CONFIG_MACH_ZYLONITE) ||\ | 45 | defined(CONFIG_MACH_ZYLONITE) ||\ |
| 46 | defined(CONFIG_MACH_LITTLETON) ||\ | 46 | defined(CONFIG_MACH_LITTLETON) ||\ |
| 47 | defined(CONFIG_MACH_ZYLONITE2) ||\ | ||
| 47 | defined(CONFIG_ARCH_VIPER) | 48 | defined(CONFIG_ARCH_VIPER) |
| 48 | 49 | ||
| 49 | #include <asm/mach-types.h> | 50 | #include <asm/mach-types.h> |
| @@ -494,8 +495,6 @@ struct smc_local { | |||
| 494 | */ | 495 | */ |
| 495 | #include <linux/dma-mapping.h> | 496 | #include <linux/dma-mapping.h> |
| 496 | #include <mach/dma.h> | 497 | #include <mach/dma.h> |
| 497 | #include <mach/hardware.h> | ||
| 498 | #include <mach/pxa-regs.h> | ||
| 499 | 498 | ||
| 500 | #ifdef SMC_insl | 499 | #ifdef SMC_insl |
| 501 | #undef SMC_insl | 500 | #undef SMC_insl |
diff --git a/drivers/net/smsc911x.c b/drivers/net/smsc911x.c index 9a78daec2fe9..d1590ac55e4b 100644 --- a/drivers/net/smsc911x.c +++ b/drivers/net/smsc911x.c | |||
| @@ -1225,6 +1225,10 @@ static int smsc911x_open(struct net_device *dev) | |||
| 1225 | dev_info(&dev->dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n", | 1225 | dev_info(&dev->dev, "SMSC911x/921x identified at %#08lx, IRQ: %d\n", |
| 1226 | (unsigned long)pdata->ioaddr, dev->irq); | 1226 | (unsigned long)pdata->ioaddr, dev->irq); |
| 1227 | 1227 | ||
| 1228 | /* Reset the last known duplex and carrier */ | ||
| 1229 | pdata->last_duplex = -1; | ||
| 1230 | pdata->last_carrier = -1; | ||
| 1231 | |||
| 1228 | /* Bring the PHY up */ | 1232 | /* Bring the PHY up */ |
| 1229 | phy_start(pdata->phy_dev); | 1233 | phy_start(pdata->phy_dev); |
| 1230 | 1234 | ||
diff --git a/drivers/net/sungem.c b/drivers/net/sungem.c index 8d64b1da0465..c9c7650826c0 100644 --- a/drivers/net/sungem.c +++ b/drivers/net/sungem.c | |||
| @@ -1229,7 +1229,7 @@ static void gem_reset(struct gem *gp) | |||
| 1229 | break; | 1229 | break; |
| 1230 | } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST)); | 1230 | } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST)); |
| 1231 | 1231 | ||
| 1232 | if (limit <= 0) | 1232 | if (limit < 0) |
| 1233 | printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name); | 1233 | printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name); |
| 1234 | 1234 | ||
| 1235 | if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes) | 1235 | if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes) |
| @@ -2998,8 +2998,11 @@ static const struct net_device_ops gem_netdev_ops = { | |||
| 2998 | .ndo_do_ioctl = gem_ioctl, | 2998 | .ndo_do_ioctl = gem_ioctl, |
| 2999 | .ndo_tx_timeout = gem_tx_timeout, | 2999 | .ndo_tx_timeout = gem_tx_timeout, |
| 3000 | .ndo_change_mtu = gem_change_mtu, | 3000 | .ndo_change_mtu = gem_change_mtu, |
| 3001 | .ndo_set_mac_address = eth_mac_addr, | ||
| 3002 | .ndo_validate_addr = eth_validate_addr, | 3001 | .ndo_validate_addr = eth_validate_addr, |
| 3002 | .ndo_set_mac_address = gem_set_mac_address, | ||
| 3003 | #ifdef CONFIG_NET_POLL_CONTROLLER | ||
| 3004 | .ndo_poll_controller = gem_poll_controller, | ||
| 3005 | #endif | ||
| 3003 | }; | 3006 | }; |
| 3004 | 3007 | ||
| 3005 | static int __devinit gem_init_one(struct pci_dev *pdev, | 3008 | static int __devinit gem_init_one(struct pci_dev *pdev, |
| @@ -3161,10 +3164,6 @@ static int __devinit gem_init_one(struct pci_dev *pdev, | |||
| 3161 | dev->watchdog_timeo = 5 * HZ; | 3164 | dev->watchdog_timeo = 5 * HZ; |
| 3162 | dev->irq = pdev->irq; | 3165 | dev->irq = pdev->irq; |
| 3163 | dev->dma = 0; | 3166 | dev->dma = 0; |
| 3164 | dev->set_mac_address = gem_set_mac_address; | ||
| 3165 | #ifdef CONFIG_NET_POLL_CONTROLLER | ||
| 3166 | dev->poll_controller = gem_poll_controller; | ||
| 3167 | #endif | ||
| 3168 | 3167 | ||
| 3169 | /* Set that now, in case PM kicks in now */ | 3168 | /* Set that now, in case PM kicks in now */ |
| 3170 | pci_set_drvdata(pdev, dev); | 3169 | pci_set_drvdata(pdev, dev); |
diff --git a/drivers/net/sunhme.c b/drivers/net/sunhme.c index d4fb4acdbebd..4e9bd380a5c2 100644 --- a/drivers/net/sunhme.c +++ b/drivers/net/sunhme.c | |||
| @@ -2649,8 +2649,6 @@ static int __devinit happy_meal_sbus_probe_one(struct of_device *op, int is_qfe) | |||
| 2649 | int err = -ENODEV; | 2649 | int err = -ENODEV; |
| 2650 | 2650 | ||
| 2651 | sbus_dp = to_of_device(op->dev.parent)->node; | 2651 | sbus_dp = to_of_device(op->dev.parent)->node; |
| 2652 | if (is_qfe) | ||
| 2653 | sbus_dp = to_of_device(op->dev.parent->parent)->node; | ||
| 2654 | 2652 | ||
| 2655 | /* We can match PCI devices too, do not accept those here. */ | 2653 | /* We can match PCI devices too, do not accept those here. */ |
| 2656 | if (strcmp(sbus_dp->name, "sbus")) | 2654 | if (strcmp(sbus_dp->name, "sbus")) |
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index b080f9493d83..dabdf59f8016 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
| @@ -1473,7 +1473,8 @@ static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) | |||
| 1473 | { | 1473 | { |
| 1474 | u32 reg; | 1474 | u32 reg; |
| 1475 | 1475 | ||
| 1476 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) | 1476 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
| 1477 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | ||
| 1477 | return; | 1478 | return; |
| 1478 | 1479 | ||
| 1479 | reg = MII_TG3_MISC_SHDW_WREN | | 1480 | reg = MII_TG3_MISC_SHDW_WREN | |
diff --git a/drivers/net/tokenring/tmspci.c b/drivers/net/tokenring/tmspci.c index 5f601773c260..e2150b3c83d9 100644 --- a/drivers/net/tokenring/tmspci.c +++ b/drivers/net/tokenring/tmspci.c | |||
| @@ -121,11 +121,6 @@ static int __devinit tms_pci_attach(struct pci_dev *pdev, const struct pci_devic | |||
| 121 | goto err_out_trdev; | 121 | goto err_out_trdev; |
| 122 | } | 122 | } |
| 123 | 123 | ||
| 124 | ret = request_irq(pdev->irq, tms380tr_interrupt, IRQF_SHARED, | ||
| 125 | dev->name, dev); | ||
| 126 | if (ret) | ||
| 127 | goto err_out_region; | ||
| 128 | |||
| 129 | dev->base_addr = pci_ioaddr; | 124 | dev->base_addr = pci_ioaddr; |
| 130 | dev->irq = pci_irq_line; | 125 | dev->irq = pci_irq_line; |
| 131 | dev->dma = 0; | 126 | dev->dma = 0; |
| @@ -142,7 +137,7 @@ static int __devinit tms_pci_attach(struct pci_dev *pdev, const struct pci_devic | |||
| 142 | ret = tmsdev_init(dev, &pdev->dev); | 137 | ret = tmsdev_init(dev, &pdev->dev); |
| 143 | if (ret) { | 138 | if (ret) { |
| 144 | printk("%s: unable to get memory for dev->priv.\n", dev->name); | 139 | printk("%s: unable to get memory for dev->priv.\n", dev->name); |
| 145 | goto err_out_irq; | 140 | goto err_out_region; |
| 146 | } | 141 | } |
| 147 | 142 | ||
| 148 | tp = netdev_priv(dev); | 143 | tp = netdev_priv(dev); |
| @@ -157,6 +152,11 @@ static int __devinit tms_pci_attach(struct pci_dev *pdev, const struct pci_devic | |||
| 157 | 152 | ||
| 158 | tp->tmspriv = cardinfo; | 153 | tp->tmspriv = cardinfo; |
| 159 | 154 | ||
| 155 | ret = request_irq(pdev->irq, tms380tr_interrupt, IRQF_SHARED, | ||
| 156 | dev->name, dev); | ||
| 157 | if (ret) | ||
| 158 | goto err_out_tmsdev; | ||
| 159 | |||
| 160 | dev->open = tms380tr_open; | 160 | dev->open = tms380tr_open; |
| 161 | dev->stop = tms380tr_close; | 161 | dev->stop = tms380tr_close; |
| 162 | pci_set_drvdata(pdev, dev); | 162 | pci_set_drvdata(pdev, dev); |
| @@ -164,15 +164,15 @@ static int __devinit tms_pci_attach(struct pci_dev *pdev, const struct pci_devic | |||
| 164 | 164 | ||
| 165 | ret = register_netdev(dev); | 165 | ret = register_netdev(dev); |
| 166 | if (ret) | 166 | if (ret) |
| 167 | goto err_out_tmsdev; | 167 | goto err_out_irq; |
| 168 | 168 | ||
| 169 | return 0; | 169 | return 0; |
| 170 | 170 | ||
| 171 | err_out_irq: | ||
| 172 | free_irq(pdev->irq, dev); | ||
| 171 | err_out_tmsdev: | 173 | err_out_tmsdev: |
| 172 | pci_set_drvdata(pdev, NULL); | 174 | pci_set_drvdata(pdev, NULL); |
| 173 | tmsdev_term(dev); | 175 | tmsdev_term(dev); |
| 174 | err_out_irq: | ||
| 175 | free_irq(pdev->irq, dev); | ||
| 176 | err_out_region: | 176 | err_out_region: |
| 177 | release_region(pci_ioaddr, TMS_PCI_IO_EXTENT); | 177 | release_region(pci_ioaddr, TMS_PCI_IO_EXTENT); |
| 178 | err_out_trdev: | 178 | err_out_trdev: |
diff --git a/drivers/net/tulip/tulip_core.c b/drivers/net/tulip/tulip_core.c index bee75fa87a9c..2abb5d3becc6 100644 --- a/drivers/net/tulip/tulip_core.c +++ b/drivers/net/tulip/tulip_core.c | |||
| @@ -255,6 +255,7 @@ const char tulip_media_cap[32] = | |||
| 255 | 255 | ||
| 256 | static void tulip_tx_timeout(struct net_device *dev); | 256 | static void tulip_tx_timeout(struct net_device *dev); |
| 257 | static void tulip_init_ring(struct net_device *dev); | 257 | static void tulip_init_ring(struct net_device *dev); |
| 258 | static void tulip_free_ring(struct net_device *dev); | ||
| 258 | static int tulip_start_xmit(struct sk_buff *skb, struct net_device *dev); | 259 | static int tulip_start_xmit(struct sk_buff *skb, struct net_device *dev); |
| 259 | static int tulip_open(struct net_device *dev); | 260 | static int tulip_open(struct net_device *dev); |
| 260 | static int tulip_close(struct net_device *dev); | 261 | static int tulip_close(struct net_device *dev); |
| @@ -502,16 +503,21 @@ tulip_open(struct net_device *dev) | |||
| 502 | { | 503 | { |
| 503 | int retval; | 504 | int retval; |
| 504 | 505 | ||
| 505 | if ((retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev))) | ||
| 506 | return retval; | ||
| 507 | |||
| 508 | tulip_init_ring (dev); | 506 | tulip_init_ring (dev); |
| 509 | 507 | ||
| 508 | retval = request_irq(dev->irq, &tulip_interrupt, IRQF_SHARED, dev->name, dev); | ||
| 509 | if (retval) | ||
| 510 | goto free_ring; | ||
| 511 | |||
| 510 | tulip_up (dev); | 512 | tulip_up (dev); |
| 511 | 513 | ||
| 512 | netif_start_queue (dev); | 514 | netif_start_queue (dev); |
| 513 | 515 | ||
| 514 | return 0; | 516 | return 0; |
| 517 | |||
| 518 | free_ring: | ||
| 519 | tulip_free_ring (dev); | ||
| 520 | return retval; | ||
| 515 | } | 521 | } |
| 516 | 522 | ||
| 517 | 523 | ||
| @@ -768,23 +774,11 @@ static void tulip_down (struct net_device *dev) | |||
| 768 | tulip_set_power_state (tp, 0, 1); | 774 | tulip_set_power_state (tp, 0, 1); |
| 769 | } | 775 | } |
| 770 | 776 | ||
| 771 | 777 | static void tulip_free_ring (struct net_device *dev) | |
| 772 | static int tulip_close (struct net_device *dev) | ||
| 773 | { | 778 | { |
| 774 | struct tulip_private *tp = netdev_priv(dev); | 779 | struct tulip_private *tp = netdev_priv(dev); |
| 775 | void __iomem *ioaddr = tp->base_addr; | ||
| 776 | int i; | 780 | int i; |
| 777 | 781 | ||
| 778 | netif_stop_queue (dev); | ||
| 779 | |||
| 780 | tulip_down (dev); | ||
| 781 | |||
| 782 | if (tulip_debug > 1) | ||
| 783 | printk (KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n", | ||
| 784 | dev->name, ioread32 (ioaddr + CSR5)); | ||
| 785 | |||
| 786 | free_irq (dev->irq, dev); | ||
| 787 | |||
| 788 | /* Free all the skbuffs in the Rx queue. */ | 782 | /* Free all the skbuffs in the Rx queue. */ |
| 789 | for (i = 0; i < RX_RING_SIZE; i++) { | 783 | for (i = 0; i < RX_RING_SIZE; i++) { |
| 790 | struct sk_buff *skb = tp->rx_buffers[i].skb; | 784 | struct sk_buff *skb = tp->rx_buffers[i].skb; |
| @@ -803,6 +797,7 @@ static int tulip_close (struct net_device *dev) | |||
| 803 | dev_kfree_skb (skb); | 797 | dev_kfree_skb (skb); |
| 804 | } | 798 | } |
| 805 | } | 799 | } |
| 800 | |||
| 806 | for (i = 0; i < TX_RING_SIZE; i++) { | 801 | for (i = 0; i < TX_RING_SIZE; i++) { |
| 807 | struct sk_buff *skb = tp->tx_buffers[i].skb; | 802 | struct sk_buff *skb = tp->tx_buffers[i].skb; |
| 808 | 803 | ||
| @@ -814,6 +809,24 @@ static int tulip_close (struct net_device *dev) | |||
| 814 | tp->tx_buffers[i].skb = NULL; | 809 | tp->tx_buffers[i].skb = NULL; |
| 815 | tp->tx_buffers[i].mapping = 0; | 810 | tp->tx_buffers[i].mapping = 0; |
| 816 | } | 811 | } |
| 812 | } | ||
| 813 | |||
| 814 | static int tulip_close (struct net_device *dev) | ||
| 815 | { | ||
| 816 | struct tulip_private *tp = netdev_priv(dev); | ||
| 817 | void __iomem *ioaddr = tp->base_addr; | ||
| 818 | |||
| 819 | netif_stop_queue (dev); | ||
| 820 | |||
| 821 | tulip_down (dev); | ||
| 822 | |||
| 823 | if (tulip_debug > 1) | ||
| 824 | printk (KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n", | ||
| 825 | dev->name, ioread32 (ioaddr + CSR5)); | ||
| 826 | |||
| 827 | free_irq (dev->irq, dev); | ||
| 828 | |||
| 829 | tulip_free_ring (dev); | ||
| 817 | 830 | ||
| 818 | return 0; | 831 | return 0; |
| 819 | } | 832 | } |
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c index e87986867ba5..1f61e42c641d 100644 --- a/drivers/net/ucc_geth.c +++ b/drivers/net/ucc_geth.c | |||
| @@ -1536,32 +1536,15 @@ static void adjust_link(struct net_device *dev) | |||
| 1536 | static int init_phy(struct net_device *dev) | 1536 | static int init_phy(struct net_device *dev) |
| 1537 | { | 1537 | { |
| 1538 | struct ucc_geth_private *priv = netdev_priv(dev); | 1538 | struct ucc_geth_private *priv = netdev_priv(dev); |
| 1539 | struct device_node *np = priv->node; | 1539 | struct ucc_geth_info *ug_info = priv->ug_info; |
| 1540 | struct device_node *phy, *mdio; | ||
| 1541 | const phandle *ph; | ||
| 1542 | char bus_name[MII_BUS_ID_SIZE]; | ||
| 1543 | const unsigned int *id; | ||
| 1544 | struct phy_device *phydev; | 1540 | struct phy_device *phydev; |
| 1545 | char phy_id[BUS_ID_SIZE]; | ||
| 1546 | 1541 | ||
| 1547 | priv->oldlink = 0; | 1542 | priv->oldlink = 0; |
| 1548 | priv->oldspeed = 0; | 1543 | priv->oldspeed = 0; |
| 1549 | priv->oldduplex = -1; | 1544 | priv->oldduplex = -1; |
| 1550 | 1545 | ||
| 1551 | ph = of_get_property(np, "phy-handle", NULL); | 1546 | phydev = phy_connect(dev, ug_info->phy_bus_id, &adjust_link, 0, |
| 1552 | phy = of_find_node_by_phandle(*ph); | 1547 | priv->phy_interface); |
| 1553 | mdio = of_get_parent(phy); | ||
| 1554 | |||
| 1555 | id = of_get_property(phy, "reg", NULL); | ||
| 1556 | |||
| 1557 | of_node_put(phy); | ||
| 1558 | of_node_put(mdio); | ||
| 1559 | |||
| 1560 | uec_mdio_bus_name(bus_name, mdio); | ||
| 1561 | snprintf(phy_id, sizeof(phy_id), "%s:%02x", | ||
| 1562 | bus_name, *id); | ||
| 1563 | |||
| 1564 | phydev = phy_connect(dev, phy_id, &adjust_link, 0, priv->phy_interface); | ||
| 1565 | 1548 | ||
| 1566 | if (IS_ERR(phydev)) { | 1549 | if (IS_ERR(phydev)) { |
| 1567 | printk("%s: Could not attach to PHY\n", dev->name); | 1550 | printk("%s: Could not attach to PHY\n", dev->name); |
| @@ -3629,10 +3612,12 @@ static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *ma | |||
| 3629 | ug_info->uf_info.irq = irq_of_parse_and_map(np, 0); | 3612 | ug_info->uf_info.irq = irq_of_parse_and_map(np, 0); |
| 3630 | fixed_link = of_get_property(np, "fixed-link", NULL); | 3613 | fixed_link = of_get_property(np, "fixed-link", NULL); |
| 3631 | if (fixed_link) { | 3614 | if (fixed_link) { |
| 3632 | snprintf(ug_info->mdio_bus, MII_BUS_ID_SIZE, "0"); | 3615 | snprintf(ug_info->phy_bus_id, sizeof(ug_info->phy_bus_id), |
| 3633 | ug_info->phy_address = fixed_link[0]; | 3616 | PHY_ID_FMT, "0", fixed_link[0]); |
| 3634 | phy = NULL; | 3617 | phy = NULL; |
| 3635 | } else { | 3618 | } else { |
| 3619 | char bus_name[MII_BUS_ID_SIZE]; | ||
| 3620 | |||
| 3636 | ph = of_get_property(np, "phy-handle", NULL); | 3621 | ph = of_get_property(np, "phy-handle", NULL); |
| 3637 | phy = of_find_node_by_phandle(*ph); | 3622 | phy = of_find_node_by_phandle(*ph); |
| 3638 | 3623 | ||
| @@ -3643,7 +3628,6 @@ static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *ma | |||
| 3643 | prop = of_get_property(phy, "reg", NULL); | 3628 | prop = of_get_property(phy, "reg", NULL); |
| 3644 | if (prop == NULL) | 3629 | if (prop == NULL) |
| 3645 | return -1; | 3630 | return -1; |
| 3646 | ug_info->phy_address = *prop; | ||
| 3647 | 3631 | ||
| 3648 | /* Set the bus id */ | 3632 | /* Set the bus id */ |
| 3649 | mdio = of_get_parent(phy); | 3633 | mdio = of_get_parent(phy); |
| @@ -3657,7 +3641,9 @@ static int ucc_geth_probe(struct of_device* ofdev, const struct of_device_id *ma | |||
| 3657 | if (err) | 3641 | if (err) |
| 3658 | return -1; | 3642 | return -1; |
| 3659 | 3643 | ||
| 3660 | snprintf(ug_info->mdio_bus, MII_BUS_ID_SIZE, "%x", res.start); | 3644 | uec_mdio_bus_name(bus_name, mdio); |
| 3645 | snprintf(ug_info->phy_bus_id, sizeof(ug_info->phy_bus_id), | ||
| 3646 | "%s:%02x", bus_name, *prop); | ||
| 3661 | } | 3647 | } |
| 3662 | 3648 | ||
| 3663 | /* get the phy interface type, or default to MII */ | 3649 | /* get the phy interface type, or default to MII */ |
diff --git a/drivers/net/ucc_geth.h b/drivers/net/ucc_geth.h index 16cbe42ba43c..611bdef2402b 100644 --- a/drivers/net/ucc_geth.h +++ b/drivers/net/ucc_geth.h | |||
| @@ -1091,8 +1091,7 @@ struct ucc_geth_info { | |||
| 1091 | u32 eventRegMask; | 1091 | u32 eventRegMask; |
| 1092 | u16 pausePeriod; | 1092 | u16 pausePeriod; |
| 1093 | u16 extensionField; | 1093 | u16 extensionField; |
| 1094 | u8 phy_address; | 1094 | char phy_bus_id[BUS_ID_SIZE]; |
| 1095 | char mdio_bus[MII_BUS_ID_SIZE]; | ||
| 1096 | u8 weightfactor[NUM_TX_QUEUES]; | 1095 | u8 weightfactor[NUM_TX_QUEUES]; |
| 1097 | u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES]; | 1096 | u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES]; |
| 1098 | u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX]; | 1097 | u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX]; |
diff --git a/drivers/net/ucc_geth_mii.c b/drivers/net/ucc_geth_mii.c index 54635911305c..0ada4edd56eb 100644 --- a/drivers/net/ucc_geth_mii.c +++ b/drivers/net/ucc_geth_mii.c | |||
| @@ -107,7 +107,7 @@ int uec_mdio_read(struct mii_bus *bus, int mii_id, int regnum) | |||
| 107 | static int uec_mdio_reset(struct mii_bus *bus) | 107 | static int uec_mdio_reset(struct mii_bus *bus) |
| 108 | { | 108 | { |
| 109 | struct ucc_mii_mng __iomem *regs = (void __iomem *)bus->priv; | 109 | struct ucc_mii_mng __iomem *regs = (void __iomem *)bus->priv; |
| 110 | unsigned int timeout = PHY_INIT_TIMEOUT; | 110 | int timeout = PHY_INIT_TIMEOUT; |
| 111 | 111 | ||
| 112 | mutex_lock(&bus->mdio_lock); | 112 | mutex_lock(&bus->mdio_lock); |
| 113 | 113 | ||
| @@ -123,7 +123,7 @@ static int uec_mdio_reset(struct mii_bus *bus) | |||
| 123 | 123 | ||
| 124 | mutex_unlock(&bus->mdio_lock); | 124 | mutex_unlock(&bus->mdio_lock); |
| 125 | 125 | ||
| 126 | if (timeout <= 0) { | 126 | if (timeout < 0) { |
| 127 | printk(KERN_ERR "%s: The MII Bus is stuck!\n", bus->name); | 127 | printk(KERN_ERR "%s: The MII Bus is stuck!\n", bus->name); |
| 128 | return -EBUSY; | 128 | return -EBUSY; |
| 129 | } | 129 | } |
diff --git a/drivers/net/usb/dm9601.c b/drivers/net/usb/dm9601.c index 5b67bbf1987e..81682c6defa0 100644 --- a/drivers/net/usb/dm9601.c +++ b/drivers/net/usb/dm9601.c | |||
| @@ -635,6 +635,10 @@ static const struct usb_device_id products[] = { | |||
| 635 | USB_DEVICE(0x0a47, 0x9601), /* Hirose USB-100 */ | 635 | USB_DEVICE(0x0a47, 0x9601), /* Hirose USB-100 */ |
| 636 | .driver_info = (unsigned long)&dm9601_info, | 636 | .driver_info = (unsigned long)&dm9601_info, |
| 637 | }, | 637 | }, |
| 638 | { | ||
| 639 | USB_DEVICE(0x0fe6, 0x8101), /* DM9601 USB to Fast Ethernet Adapter */ | ||
| 640 | .driver_info = (unsigned long)&dm9601_info, | ||
| 641 | }, | ||
| 638 | {}, // END | 642 | {}, // END |
| 639 | }; | 643 | }; |
| 640 | 644 | ||
diff --git a/drivers/net/via-velocity.c b/drivers/net/via-velocity.c index c5691fdb7079..fb53ef872df3 100644 --- a/drivers/net/via-velocity.c +++ b/drivers/net/via-velocity.c | |||
| @@ -1838,17 +1838,19 @@ static void velocity_free_tx_buf(struct velocity_info *vptr, struct velocity_td_ | |||
| 1838 | { | 1838 | { |
| 1839 | struct sk_buff *skb = tdinfo->skb; | 1839 | struct sk_buff *skb = tdinfo->skb; |
| 1840 | int i; | 1840 | int i; |
| 1841 | int pktlen; | ||
| 1841 | 1842 | ||
| 1842 | /* | 1843 | /* |
| 1843 | * Don't unmap the pre-allocated tx_bufs | 1844 | * Don't unmap the pre-allocated tx_bufs |
| 1844 | */ | 1845 | */ |
| 1845 | if (tdinfo->skb_dma) { | 1846 | if (tdinfo->skb_dma) { |
| 1846 | 1847 | ||
| 1848 | pktlen = (skb->len > ETH_ZLEN ? : ETH_ZLEN); | ||
| 1847 | for (i = 0; i < tdinfo->nskb_dma; i++) { | 1849 | for (i = 0; i < tdinfo->nskb_dma; i++) { |
| 1848 | #ifdef VELOCITY_ZERO_COPY_SUPPORT | 1850 | #ifdef VELOCITY_ZERO_COPY_SUPPORT |
| 1849 | pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], le16_to_cpu(td->tdesc1.len), PCI_DMA_TODEVICE); | 1851 | pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], le16_to_cpu(td->tdesc1.len), PCI_DMA_TODEVICE); |
| 1850 | #else | 1852 | #else |
| 1851 | pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], skb->len, PCI_DMA_TODEVICE); | 1853 | pci_unmap_single(vptr->pdev, tdinfo->skb_dma[i], pktlen, PCI_DMA_TODEVICE); |
| 1852 | #endif | 1854 | #endif |
| 1853 | tdinfo->skb_dma[i] = 0; | 1855 | tdinfo->skb_dma[i] = 0; |
| 1854 | } | 1856 | } |
| @@ -2080,17 +2082,14 @@ static int velocity_xmit(struct sk_buff *skb, struct net_device *dev) | |||
| 2080 | struct tx_desc *td_ptr; | 2082 | struct tx_desc *td_ptr; |
| 2081 | struct velocity_td_info *tdinfo; | 2083 | struct velocity_td_info *tdinfo; |
| 2082 | unsigned long flags; | 2084 | unsigned long flags; |
| 2083 | int pktlen = skb->len; | 2085 | int pktlen; |
| 2084 | __le16 len; | 2086 | __le16 len; |
| 2085 | int index; | 2087 | int index; |
| 2086 | 2088 | ||
| 2087 | 2089 | ||
| 2088 | 2090 | if (skb_padto(skb, ETH_ZLEN)) | |
| 2089 | if (skb->len < ETH_ZLEN) { | 2091 | goto out; |
| 2090 | if (skb_padto(skb, ETH_ZLEN)) | 2092 | pktlen = max_t(unsigned int, skb->len, ETH_ZLEN); |
| 2091 | goto out; | ||
| 2092 | pktlen = ETH_ZLEN; | ||
| 2093 | } | ||
| 2094 | 2093 | ||
| 2095 | len = cpu_to_le16(pktlen); | 2094 | len = cpu_to_le16(pktlen); |
| 2096 | 2095 | ||
diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c index c68808336c8c..e67d16c2e5f3 100644 --- a/drivers/net/virtio_net.c +++ b/drivers/net/virtio_net.c | |||
| @@ -612,6 +612,7 @@ static struct ethtool_ops virtnet_ethtool_ops = { | |||
| 612 | .set_tx_csum = virtnet_set_tx_csum, | 612 | .set_tx_csum = virtnet_set_tx_csum, |
| 613 | .set_sg = ethtool_op_set_sg, | 613 | .set_sg = ethtool_op_set_sg, |
| 614 | .set_tso = ethtool_op_set_tso, | 614 | .set_tso = ethtool_op_set_tso, |
| 615 | .get_link = ethtool_op_get_link, | ||
| 615 | }; | 616 | }; |
| 616 | 617 | ||
| 617 | #define MIN_MTU 68 | 618 | #define MIN_MTU 68 |
| @@ -739,6 +740,8 @@ static int virtnet_probe(struct virtio_device *vdev) | |||
| 739 | goto unregister; | 740 | goto unregister; |
| 740 | } | 741 | } |
| 741 | 742 | ||
| 743 | netif_carrier_on(dev); | ||
| 744 | |||
| 742 | pr_debug("virtnet: registered device %s\n", dev->name); | 745 | pr_debug("virtnet: registered device %s\n", dev->name); |
| 743 | return 0; | 746 | return 0; |
| 744 | 747 | ||
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h index d27813502953..6650f609ece4 100644 --- a/drivers/net/wireless/ath9k/ath9k.h +++ b/drivers/net/wireless/ath9k/ath9k.h | |||
| @@ -587,8 +587,8 @@ struct ath9k_country_entry { | |||
| 587 | u8 iso[3]; | 587 | u8 iso[3]; |
| 588 | }; | 588 | }; |
| 589 | 589 | ||
| 590 | #define REG_WRITE(_ah, _reg, _val) iowrite32(_val, _ah->ah_sh + _reg) | 590 | #define REG_WRITE(_ah, _reg, _val) ath9k_iowrite32((_ah), (_reg), (_val)) |
| 591 | #define REG_READ(_ah, _reg) ioread32(_ah->ah_sh + _reg) | 591 | #define REG_READ(_ah, _reg) ath9k_ioread32((_ah), (_reg)) |
| 592 | 592 | ||
| 593 | #define SM(_v, _f) (((_v) << _f##_S) & _f) | 593 | #define SM(_v, _f) (((_v) << _f##_S) & _f) |
| 594 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) | 594 | #define MS(_v, _f) (((_v) & _f) >> _f##_S) |
diff --git a/drivers/net/wireless/ath9k/core.h b/drivers/net/wireless/ath9k/core.h index 4ca2aed236e0..139566cbbf65 100644 --- a/drivers/net/wireless/ath9k/core.h +++ b/drivers/net/wireless/ath9k/core.h | |||
| @@ -701,6 +701,7 @@ struct ath_softc { | |||
| 701 | struct ath_hal *sc_ah; | 701 | struct ath_hal *sc_ah; |
| 702 | void __iomem *mem; | 702 | void __iomem *mem; |
| 703 | spinlock_t sc_resetlock; | 703 | spinlock_t sc_resetlock; |
| 704 | spinlock_t sc_serial_rw; | ||
| 704 | struct mutex mutex; | 705 | struct mutex mutex; |
| 705 | 706 | ||
| 706 | u8 sc_curbssid[ETH_ALEN]; | 707 | u8 sc_curbssid[ETH_ALEN]; |
| @@ -751,4 +752,36 @@ int ath_get_hal_qnum(u16 queue, struct ath_softc *sc); | |||
| 751 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); | 752 | int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc); |
| 752 | int ath_cabq_update(struct ath_softc *); | 753 | int ath_cabq_update(struct ath_softc *); |
| 753 | 754 | ||
| 755 | /* | ||
| 756 | * Read and write, they both share the same lock. We do this to serialize | ||
| 757 | * reads and writes on Atheros 802.11n PCI devices only. This is required | ||
| 758 | * as the FIFO on these devices can only accept sanely 2 requests. After | ||
| 759 | * that the device goes bananas. Serializing the reads/writes prevents this | ||
| 760 | * from happening. | ||
| 761 | */ | ||
| 762 | |||
| 763 | static inline void ath9k_iowrite32(struct ath_hal *ah, u32 reg_offset, u32 val) | ||
| 764 | { | ||
| 765 | if (ah->ah_config.serialize_regmode == SER_REG_MODE_ON) { | ||
| 766 | unsigned long flags; | ||
| 767 | spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags); | ||
| 768 | iowrite32(val, ah->ah_sc->mem + reg_offset); | ||
| 769 | spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags); | ||
| 770 | } else | ||
| 771 | iowrite32(val, ah->ah_sc->mem + reg_offset); | ||
| 772 | } | ||
| 773 | |||
| 774 | static inline unsigned int ath9k_ioread32(struct ath_hal *ah, u32 reg_offset) | ||
| 775 | { | ||
| 776 | u32 val; | ||
| 777 | if (ah->ah_config.serialize_regmode == SER_REG_MODE_ON) { | ||
| 778 | unsigned long flags; | ||
| 779 | spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags); | ||
| 780 | val = ioread32(ah->ah_sc->mem + reg_offset); | ||
| 781 | spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags); | ||
| 782 | } else | ||
| 783 | val = ioread32(ah->ah_sc->mem + reg_offset); | ||
| 784 | return val; | ||
| 785 | } | ||
| 786 | |||
| 754 | #endif /* CORE_H */ | 787 | #endif /* CORE_H */ |
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index 34474edefc97..c38a00bbce64 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c | |||
| @@ -437,6 +437,25 @@ static void ath9k_hw_set_defaults(struct ath_hal *ah) | |||
| 437 | } | 437 | } |
| 438 | 438 | ||
| 439 | ah->ah_config.intr_mitigation = 1; | 439 | ah->ah_config.intr_mitigation = 1; |
| 440 | |||
| 441 | /* | ||
| 442 | * We need this for PCI devices only (Cardbus, PCI, miniPCI) | ||
| 443 | * _and_ if on non-uniprocessor systems (Multiprocessor/HT). | ||
| 444 | * This means we use it for all AR5416 devices, and the few | ||
| 445 | * minor PCI AR9280 devices out there. | ||
| 446 | * | ||
| 447 | * Serialization is required because these devices do not handle | ||
| 448 | * well the case of two concurrent reads/writes due to the latency | ||
| 449 | * involved. During one read/write another read/write can be issued | ||
| 450 | * on another CPU while the previous read/write may still be working | ||
| 451 | * on our hardware, if we hit this case the hardware poops in a loop. | ||
| 452 | * We prevent this by serializing reads and writes. | ||
| 453 | * | ||
| 454 | * This issue is not present on PCI-Express devices or pre-AR5416 | ||
| 455 | * devices (legacy, 802.11abg). | ||
| 456 | */ | ||
| 457 | if (num_possible_cpus() > 1) | ||
| 458 | ah->ah_config.serialize_regmode = SER_REG_MODE_AUTO; | ||
| 440 | } | 459 | } |
| 441 | 460 | ||
| 442 | static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, | 461 | static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid, |
| @@ -668,7 +687,8 @@ static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc, | |||
| 668 | } | 687 | } |
| 669 | 688 | ||
| 670 | if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) { | 689 | if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) { |
| 671 | if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) { | 690 | if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI || |
| 691 | (AR_SREV_9280(ah) && !ah->ah_isPciExpress)) { | ||
| 672 | ah->ah_config.serialize_regmode = | 692 | ah->ah_config.serialize_regmode = |
| 673 | SER_REG_MODE_ON; | 693 | SER_REG_MODE_ON; |
| 674 | } else { | 694 | } else { |
diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c index 0e80990d8e84..3c04044a60bd 100644 --- a/drivers/net/wireless/ath9k/main.c +++ b/drivers/net/wireless/ath9k/main.c | |||
| @@ -1336,6 +1336,7 @@ static int ath_init(u16 devid, struct ath_softc *sc) | |||
| 1336 | printk(KERN_ERR "Unable to create debugfs files\n"); | 1336 | printk(KERN_ERR "Unable to create debugfs files\n"); |
| 1337 | 1337 | ||
| 1338 | spin_lock_init(&sc->sc_resetlock); | 1338 | spin_lock_init(&sc->sc_resetlock); |
| 1339 | spin_lock_init(&sc->sc_serial_rw); | ||
| 1339 | mutex_init(&sc->mutex); | 1340 | mutex_init(&sc->mutex); |
| 1340 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); | 1341 | tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc); |
| 1341 | tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, | 1342 | tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet, |
diff --git a/drivers/net/wireless/iwlwifi/iwl-agn.c b/drivers/net/wireless/iwlwifi/iwl-agn.c index 36bafeb353ce..129e2d330abb 100644 --- a/drivers/net/wireless/iwlwifi/iwl-agn.c +++ b/drivers/net/wireless/iwlwifi/iwl-agn.c | |||
| @@ -3868,7 +3868,7 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
| 3868 | } | 3868 | } |
| 3869 | err = iwl_eeprom_check_version(priv); | 3869 | err = iwl_eeprom_check_version(priv); |
| 3870 | if (err) | 3870 | if (err) |
| 3871 | goto out_iounmap; | 3871 | goto out_free_eeprom; |
| 3872 | 3872 | ||
| 3873 | /* extract MAC Address */ | 3873 | /* extract MAC Address */ |
| 3874 | iwl_eeprom_get_mac(priv, priv->mac_addr); | 3874 | iwl_eeprom_get_mac(priv, priv->mac_addr); |
| @@ -3945,6 +3945,8 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
| 3945 | return 0; | 3945 | return 0; |
| 3946 | 3946 | ||
| 3947 | out_remove_sysfs: | 3947 | out_remove_sysfs: |
| 3948 | destroy_workqueue(priv->workqueue); | ||
| 3949 | priv->workqueue = NULL; | ||
| 3948 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); | 3950 | sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group); |
| 3949 | out_uninit_drv: | 3951 | out_uninit_drv: |
| 3950 | iwl_uninit_drv(priv); | 3952 | iwl_uninit_drv(priv); |
| @@ -3953,8 +3955,8 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
| 3953 | out_iounmap: | 3955 | out_iounmap: |
| 3954 | pci_iounmap(pdev, priv->hw_base); | 3956 | pci_iounmap(pdev, priv->hw_base); |
| 3955 | out_pci_release_regions: | 3957 | out_pci_release_regions: |
| 3956 | pci_release_regions(pdev); | ||
| 3957 | pci_set_drvdata(pdev, NULL); | 3958 | pci_set_drvdata(pdev, NULL); |
| 3959 | pci_release_regions(pdev); | ||
| 3958 | out_pci_disable_device: | 3960 | out_pci_disable_device: |
| 3959 | pci_disable_device(pdev); | 3961 | pci_disable_device(pdev); |
| 3960 | out_ieee80211_free_hw: | 3962 | out_ieee80211_free_hw: |
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c index 93be74a1f139..57dd34e256d8 100644 --- a/drivers/net/wireless/iwlwifi/iwl3945-base.c +++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c | |||
| @@ -7911,7 +7911,7 @@ static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e | |||
| 7911 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); | 7911 | CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000); |
| 7912 | if (err < 0) { | 7912 | if (err < 0) { |
| 7913 | IWL_DEBUG_INFO("Failed to init the card\n"); | 7913 | IWL_DEBUG_INFO("Failed to init the card\n"); |
| 7914 | goto out_remove_sysfs; | 7914 | goto out_iounmap; |
| 7915 | } | 7915 | } |
| 7916 | 7916 | ||
| 7917 | /*********************** | 7917 | /*********************** |
| @@ -7921,7 +7921,7 @@ static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e | |||
| 7921 | err = iwl3945_eeprom_init(priv); | 7921 | err = iwl3945_eeprom_init(priv); |
| 7922 | if (err) { | 7922 | if (err) { |
| 7923 | IWL_ERROR("Unable to init EEPROM\n"); | 7923 | IWL_ERROR("Unable to init EEPROM\n"); |
| 7924 | goto out_remove_sysfs; | 7924 | goto out_iounmap; |
| 7925 | } | 7925 | } |
| 7926 | /* MAC Address location in EEPROM same for 3945/4965 */ | 7926 | /* MAC Address location in EEPROM same for 3945/4965 */ |
| 7927 | get_eeprom_mac(priv, priv->mac_addr); | 7927 | get_eeprom_mac(priv, priv->mac_addr); |
| @@ -7975,7 +7975,7 @@ static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e | |||
| 7975 | err = iwl3945_init_channel_map(priv); | 7975 | err = iwl3945_init_channel_map(priv); |
| 7976 | if (err) { | 7976 | if (err) { |
| 7977 | IWL_ERROR("initializing regulatory failed: %d\n", err); | 7977 | IWL_ERROR("initializing regulatory failed: %d\n", err); |
| 7978 | goto out_release_irq; | 7978 | goto out_unset_hw_setting; |
| 7979 | } | 7979 | } |
| 7980 | 7980 | ||
| 7981 | err = iwl3945_init_geos(priv); | 7981 | err = iwl3945_init_geos(priv); |
| @@ -8045,25 +8045,22 @@ static int iwl3945_pci_probe(struct pci_dev *pdev, const struct pci_device_id *e | |||
| 8045 | return 0; | 8045 | return 0; |
| 8046 | 8046 | ||
| 8047 | out_remove_sysfs: | 8047 | out_remove_sysfs: |
| 8048 | destroy_workqueue(priv->workqueue); | ||
| 8049 | priv->workqueue = NULL; | ||
| 8048 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); | 8050 | sysfs_remove_group(&pdev->dev.kobj, &iwl3945_attribute_group); |
| 8049 | out_free_geos: | 8051 | out_free_geos: |
| 8050 | iwl3945_free_geos(priv); | 8052 | iwl3945_free_geos(priv); |
| 8051 | out_free_channel_map: | 8053 | out_free_channel_map: |
| 8052 | iwl3945_free_channel_map(priv); | 8054 | iwl3945_free_channel_map(priv); |
| 8053 | 8055 | out_unset_hw_setting: | |
| 8054 | |||
| 8055 | out_release_irq: | ||
| 8056 | destroy_workqueue(priv->workqueue); | ||
| 8057 | priv->workqueue = NULL; | ||
| 8058 | iwl3945_unset_hw_setting(priv); | 8056 | iwl3945_unset_hw_setting(priv); |
| 8059 | |||
| 8060 | out_iounmap: | 8057 | out_iounmap: |
| 8061 | pci_iounmap(pdev, priv->hw_base); | 8058 | pci_iounmap(pdev, priv->hw_base); |
| 8062 | out_pci_release_regions: | 8059 | out_pci_release_regions: |
| 8063 | pci_release_regions(pdev); | 8060 | pci_release_regions(pdev); |
| 8064 | out_pci_disable_device: | 8061 | out_pci_disable_device: |
| 8065 | pci_disable_device(pdev); | ||
| 8066 | pci_set_drvdata(pdev, NULL); | 8062 | pci_set_drvdata(pdev, NULL); |
| 8063 | pci_disable_device(pdev); | ||
| 8067 | out_ieee80211_free_hw: | 8064 | out_ieee80211_free_hw: |
| 8068 | ieee80211_free_hw(priv->hw); | 8065 | ieee80211_free_hw(priv->hw); |
| 8069 | out: | 8066 | out: |
diff --git a/drivers/net/wireless/p54/p54common.c b/drivers/net/wireless/p54/p54common.c index 34561e6e816b..f170106bf0ae 100644 --- a/drivers/net/wireless/p54/p54common.c +++ b/drivers/net/wireless/p54/p54common.c | |||
| @@ -710,10 +710,11 @@ static struct sk_buff *p54_find_tx_entry(struct ieee80211_hw *dev, | |||
| 710 | __le32 req_id) | 710 | __le32 req_id) |
| 711 | { | 711 | { |
| 712 | struct p54_common *priv = dev->priv; | 712 | struct p54_common *priv = dev->priv; |
| 713 | struct sk_buff *entry = priv->tx_queue.next; | 713 | struct sk_buff *entry; |
| 714 | unsigned long flags; | 714 | unsigned long flags; |
| 715 | 715 | ||
| 716 | spin_lock_irqsave(&priv->tx_queue.lock, flags); | 716 | spin_lock_irqsave(&priv->tx_queue.lock, flags); |
| 717 | entry = priv->tx_queue.next; | ||
| 717 | while (entry != (struct sk_buff *)&priv->tx_queue) { | 718 | while (entry != (struct sk_buff *)&priv->tx_queue) { |
| 718 | struct p54_hdr *hdr = (struct p54_hdr *) entry->data; | 719 | struct p54_hdr *hdr = (struct p54_hdr *) entry->data; |
| 719 | 720 | ||
| @@ -732,7 +733,7 @@ static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb) | |||
| 732 | struct p54_common *priv = dev->priv; | 733 | struct p54_common *priv = dev->priv; |
| 733 | struct p54_hdr *hdr = (struct p54_hdr *) skb->data; | 734 | struct p54_hdr *hdr = (struct p54_hdr *) skb->data; |
| 734 | struct p54_frame_sent *payload = (struct p54_frame_sent *) hdr->data; | 735 | struct p54_frame_sent *payload = (struct p54_frame_sent *) hdr->data; |
| 735 | struct sk_buff *entry = (struct sk_buff *) priv->tx_queue.next; | 736 | struct sk_buff *entry; |
| 736 | u32 addr = le32_to_cpu(hdr->req_id) - priv->headroom; | 737 | u32 addr = le32_to_cpu(hdr->req_id) - priv->headroom; |
| 737 | struct memrecord *range = NULL; | 738 | struct memrecord *range = NULL; |
| 738 | u32 freed = 0; | 739 | u32 freed = 0; |
| @@ -741,6 +742,7 @@ static void p54_rx_frame_sent(struct ieee80211_hw *dev, struct sk_buff *skb) | |||
| 741 | int count, idx; | 742 | int count, idx; |
| 742 | 743 | ||
| 743 | spin_lock_irqsave(&priv->tx_queue.lock, flags); | 744 | spin_lock_irqsave(&priv->tx_queue.lock, flags); |
| 745 | entry = (struct sk_buff *) priv->tx_queue.next; | ||
| 744 | while (entry != (struct sk_buff *)&priv->tx_queue) { | 746 | while (entry != (struct sk_buff *)&priv->tx_queue) { |
| 745 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry); | 747 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(entry); |
| 746 | struct p54_hdr *entry_hdr; | 748 | struct p54_hdr *entry_hdr; |
| @@ -976,7 +978,7 @@ static int p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb, | |||
| 976 | struct p54_hdr *data, u32 len) | 978 | struct p54_hdr *data, u32 len) |
| 977 | { | 979 | { |
| 978 | struct p54_common *priv = dev->priv; | 980 | struct p54_common *priv = dev->priv; |
| 979 | struct sk_buff *entry = priv->tx_queue.next; | 981 | struct sk_buff *entry; |
| 980 | struct sk_buff *target_skb = NULL; | 982 | struct sk_buff *target_skb = NULL; |
| 981 | struct ieee80211_tx_info *info; | 983 | struct ieee80211_tx_info *info; |
| 982 | struct memrecord *range; | 984 | struct memrecord *range; |
| @@ -1014,6 +1016,7 @@ static int p54_assign_address(struct ieee80211_hw *dev, struct sk_buff *skb, | |||
| 1014 | } | 1016 | } |
| 1015 | } | 1017 | } |
| 1016 | 1018 | ||
| 1019 | entry = priv->tx_queue.next; | ||
| 1017 | while (left--) { | 1020 | while (left--) { |
| 1018 | u32 hole_size; | 1021 | u32 hole_size; |
| 1019 | info = IEEE80211_SKB_CB(entry); | 1022 | info = IEEE80211_SKB_CB(entry); |
diff --git a/drivers/net/wireless/rt2x00/rt2500usb.c b/drivers/net/wireless/rt2x00/rt2500usb.c index af6b5847be5c..3e2ac2bbb12f 100644 --- a/drivers/net/wireless/rt2x00/rt2500usb.c +++ b/drivers/net/wireless/rt2x00/rt2500usb.c | |||
| @@ -1952,6 +1952,8 @@ static struct usb_device_id rt2500usb_device_table[] = { | |||
| 1952 | { USB_DEVICE(0x13b1, 0x000d), USB_DEVICE_DATA(&rt2500usb_ops) }, | 1952 | { USB_DEVICE(0x13b1, 0x000d), USB_DEVICE_DATA(&rt2500usb_ops) }, |
| 1953 | { USB_DEVICE(0x13b1, 0x0011), USB_DEVICE_DATA(&rt2500usb_ops) }, | 1953 | { USB_DEVICE(0x13b1, 0x0011), USB_DEVICE_DATA(&rt2500usb_ops) }, |
| 1954 | { USB_DEVICE(0x13b1, 0x001a), USB_DEVICE_DATA(&rt2500usb_ops) }, | 1954 | { USB_DEVICE(0x13b1, 0x001a), USB_DEVICE_DATA(&rt2500usb_ops) }, |
| 1955 | /* CNet */ | ||
| 1956 | { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt2500usb_ops) }, | ||
| 1955 | /* Conceptronic */ | 1957 | /* Conceptronic */ |
| 1956 | { USB_DEVICE(0x14b2, 0x3c02), USB_DEVICE_DATA(&rt2500usb_ops) }, | 1958 | { USB_DEVICE(0x14b2, 0x3c02), USB_DEVICE_DATA(&rt2500usb_ops) }, |
| 1957 | /* D-LINK */ | 1959 | /* D-LINK */ |
| @@ -1976,14 +1978,20 @@ static struct usb_device_id rt2500usb_device_table[] = { | |||
| 1976 | { USB_DEVICE(0x148f, 0x2570), USB_DEVICE_DATA(&rt2500usb_ops) }, | 1978 | { USB_DEVICE(0x148f, 0x2570), USB_DEVICE_DATA(&rt2500usb_ops) }, |
| 1977 | { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt2500usb_ops) }, | 1979 | { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt2500usb_ops) }, |
| 1978 | { USB_DEVICE(0x148f, 0x9020), USB_DEVICE_DATA(&rt2500usb_ops) }, | 1980 | { USB_DEVICE(0x148f, 0x9020), USB_DEVICE_DATA(&rt2500usb_ops) }, |
| 1981 | /* Sagem */ | ||
| 1982 | { USB_DEVICE(0x079b, 0x004b), USB_DEVICE_DATA(&rt2500usb_ops) }, | ||
| 1979 | /* Siemens */ | 1983 | /* Siemens */ |
| 1980 | { USB_DEVICE(0x0681, 0x3c06), USB_DEVICE_DATA(&rt2500usb_ops) }, | 1984 | { USB_DEVICE(0x0681, 0x3c06), USB_DEVICE_DATA(&rt2500usb_ops) }, |
| 1981 | /* SMC */ | 1985 | /* SMC */ |
| 1982 | { USB_DEVICE(0x0707, 0xee13), USB_DEVICE_DATA(&rt2500usb_ops) }, | 1986 | { USB_DEVICE(0x0707, 0xee13), USB_DEVICE_DATA(&rt2500usb_ops) }, |
| 1983 | /* Spairon */ | 1987 | /* Spairon */ |
| 1984 | { USB_DEVICE(0x114b, 0x0110), USB_DEVICE_DATA(&rt2500usb_ops) }, | 1988 | { USB_DEVICE(0x114b, 0x0110), USB_DEVICE_DATA(&rt2500usb_ops) }, |
| 1989 | /* SURECOM */ | ||
| 1990 | { USB_DEVICE(0x0769, 0x11f3), USB_DEVICE_DATA(&rt2500usb_ops) }, | ||
| 1985 | /* Trust */ | 1991 | /* Trust */ |
| 1986 | { USB_DEVICE(0x0eb0, 0x9020), USB_DEVICE_DATA(&rt2500usb_ops) }, | 1992 | { USB_DEVICE(0x0eb0, 0x9020), USB_DEVICE_DATA(&rt2500usb_ops) }, |
| 1993 | /* VTech */ | ||
| 1994 | { USB_DEVICE(0x0f88, 0x3012), USB_DEVICE_DATA(&rt2500usb_ops) }, | ||
| 1987 | /* Zinwell */ | 1995 | /* Zinwell */ |
| 1988 | { USB_DEVICE(0x5a57, 0x0260), USB_DEVICE_DATA(&rt2500usb_ops) }, | 1996 | { USB_DEVICE(0x5a57, 0x0260), USB_DEVICE_DATA(&rt2500usb_ops) }, |
| 1989 | { 0, } | 1997 | { 0, } |
diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c index 96a8d69f8790..cefee1b26cd8 100644 --- a/drivers/net/wireless/rt2x00/rt73usb.c +++ b/drivers/net/wireless/rt2x00/rt73usb.c | |||
| @@ -2281,7 +2281,18 @@ static const struct rt2x00_ops rt73usb_ops = { | |||
| 2281 | */ | 2281 | */ |
| 2282 | static struct usb_device_id rt73usb_device_table[] = { | 2282 | static struct usb_device_id rt73usb_device_table[] = { |
| 2283 | /* AboCom */ | 2283 | /* AboCom */ |
| 2284 | { USB_DEVICE(0x07b8, 0xb21b), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2285 | { USB_DEVICE(0x07b8, 0xb21c), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2284 | { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) }, | 2286 | { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2287 | { USB_DEVICE(0x07b8, 0xb21e), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2288 | { USB_DEVICE(0x07b8, 0xb21f), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2289 | /* AL */ | ||
| 2290 | { USB_DEVICE(0x14b2, 0x3c10), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2291 | /* Amigo */ | ||
| 2292 | { USB_DEVICE(0x148f, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2293 | { USB_DEVICE(0x0eb0, 0x9021), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2294 | /* AMIT */ | ||
| 2295 | { USB_DEVICE(0x18c5, 0x0002), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2285 | /* Askey */ | 2296 | /* Askey */ |
| 2286 | { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) }, | 2297 | { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2287 | /* ASUS */ | 2298 | /* ASUS */ |
| @@ -2294,7 +2305,9 @@ static struct usb_device_id rt73usb_device_table[] = { | |||
| 2294 | { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) }, | 2305 | { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2295 | /* Billionton */ | 2306 | /* Billionton */ |
| 2296 | { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) }, | 2307 | { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2308 | { USB_DEVICE(0x08dd, 0x0120), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2297 | /* Buffalo */ | 2309 | /* Buffalo */ |
| 2310 | { USB_DEVICE(0x0411, 0x00d8), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2298 | { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) }, | 2311 | { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2299 | /* CNet */ | 2312 | /* CNet */ |
| 2300 | { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) }, | 2313 | { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) }, |
| @@ -2308,6 +2321,11 @@ static struct usb_device_id rt73usb_device_table[] = { | |||
| 2308 | { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) }, | 2321 | { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2309 | { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) }, | 2322 | { USB_DEVICE(0x07d1, 0x3c06), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2310 | { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) }, | 2323 | { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2324 | /* Edimax */ | ||
| 2325 | { USB_DEVICE(0x7392, 0x7318), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2326 | { USB_DEVICE(0x7392, 0x7618), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2327 | /* EnGenius */ | ||
| 2328 | { USB_DEVICE(0x1740, 0x3701), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2311 | /* Gemtek */ | 2329 | /* Gemtek */ |
| 2312 | { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) }, | 2330 | { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2313 | /* Gigabyte */ | 2331 | /* Gigabyte */ |
| @@ -2328,22 +2346,34 @@ static struct usb_device_id rt73usb_device_table[] = { | |||
| 2328 | { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) }, | 2346 | { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2329 | { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) }, | 2347 | { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2330 | /* Ralink */ | 2348 | /* Ralink */ |
| 2349 | { USB_DEVICE(0x04bb, 0x093d), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2331 | { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) }, | 2350 | { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2332 | { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) }, | 2351 | { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2333 | /* Qcom */ | 2352 | /* Qcom */ |
| 2334 | { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) }, | 2353 | { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2335 | { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) }, | 2354 | { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2336 | { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) }, | 2355 | { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2356 | /* Samsung */ | ||
| 2357 | { USB_DEVICE(0x04e8, 0x4471), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2337 | /* Senao */ | 2358 | /* Senao */ |
| 2338 | { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) }, | 2359 | { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2339 | /* Sitecom */ | 2360 | /* Sitecom */ |
| 2340 | { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) }, | 2361 | { USB_DEVICE(0x0df6, 0x0024), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2362 | { USB_DEVICE(0x0df6, 0x0027), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2363 | { USB_DEVICE(0x0df6, 0x002f), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2341 | { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) }, | 2364 | { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2365 | { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2342 | /* Surecom */ | 2366 | /* Surecom */ |
| 2343 | { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) }, | 2367 | { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2368 | /* Philips */ | ||
| 2369 | { USB_DEVICE(0x0471, 0x200a), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2344 | /* Planex */ | 2370 | /* Planex */ |
| 2345 | { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) }, | 2371 | { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2346 | { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) }, | 2372 | { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) }, |
| 2373 | /* Zcom */ | ||
| 2374 | { USB_DEVICE(0x0cde, 0x001c), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2375 | /* ZyXEL */ | ||
| 2376 | { USB_DEVICE(0x0586, 0x3415), USB_DEVICE_DATA(&rt73usb_ops) }, | ||
| 2347 | { 0, } | 2377 | { 0, } |
| 2348 | }; | 2378 | }; |
| 2349 | 2379 | ||
diff --git a/drivers/net/wireless/zd1211rw/zd_mac.c b/drivers/net/wireless/zd1211rw/zd_mac.c index a611ad857983..847057d682b1 100644 --- a/drivers/net/wireless/zd1211rw/zd_mac.c +++ b/drivers/net/wireless/zd1211rw/zd_mac.c | |||
| @@ -575,13 +575,17 @@ static int zd_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb) | |||
| 575 | 575 | ||
| 576 | r = fill_ctrlset(mac, skb); | 576 | r = fill_ctrlset(mac, skb); |
| 577 | if (r) | 577 | if (r) |
| 578 | return r; | 578 | goto fail; |
| 579 | 579 | ||
| 580 | info->rate_driver_data[0] = hw; | 580 | info->rate_driver_data[0] = hw; |
| 581 | 581 | ||
| 582 | r = zd_usb_tx(&mac->chip.usb, skb); | 582 | r = zd_usb_tx(&mac->chip.usb, skb); |
| 583 | if (r) | 583 | if (r) |
| 584 | return r; | 584 | goto fail; |
| 585 | return 0; | ||
| 586 | |||
| 587 | fail: | ||
| 588 | dev_kfree_skb(skb); | ||
| 585 | return 0; | 589 | return 0; |
| 586 | } | 590 | } |
| 587 | 591 | ||
diff --git a/drivers/parisc/dino.c b/drivers/parisc/dino.c index d539d9df88e7..bb5a1c9597cb 100644 --- a/drivers/parisc/dino.c +++ b/drivers/parisc/dino.c | |||
| @@ -479,7 +479,7 @@ dino_card_setup(struct pci_bus *bus, void __iomem *base_addr) | |||
| 479 | res = &dino_dev->hba.lmmio_space; | 479 | res = &dino_dev->hba.lmmio_space; |
| 480 | res->flags = IORESOURCE_MEM; | 480 | res->flags = IORESOURCE_MEM; |
| 481 | size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)", | 481 | size = scnprintf(name, sizeof(name), "Dino LMMIO (%s)", |
| 482 | bus->bridge->bus_id); | 482 | dev_name(bus->bridge)); |
| 483 | res->name = kmalloc(size+1, GFP_KERNEL); | 483 | res->name = kmalloc(size+1, GFP_KERNEL); |
| 484 | if(res->name) | 484 | if(res->name) |
| 485 | strcpy((char *)res->name, name); | 485 | strcpy((char *)res->name, name); |
| @@ -493,7 +493,7 @@ dino_card_setup(struct pci_bus *bus, void __iomem *base_addr) | |||
| 493 | struct list_head *ln, *tmp_ln; | 493 | struct list_head *ln, *tmp_ln; |
| 494 | 494 | ||
| 495 | printk(KERN_ERR "Dino: cannot attach bus %s\n", | 495 | printk(KERN_ERR "Dino: cannot attach bus %s\n", |
| 496 | bus->bridge->bus_id); | 496 | dev_name(bus->bridge)); |
| 497 | /* kill the bus, we can't do anything with it */ | 497 | /* kill the bus, we can't do anything with it */ |
| 498 | list_for_each_safe(ln, tmp_ln, &bus->devices) { | 498 | list_for_each_safe(ln, tmp_ln, &bus->devices) { |
| 499 | struct pci_dev *dev = pci_dev_b(ln); | 499 | struct pci_dev *dev = pci_dev_b(ln); |
| @@ -587,7 +587,7 @@ dino_fixup_bus(struct pci_bus *bus) | |||
| 587 | bus->resource[i+1] = &res[i]; | 587 | bus->resource[i+1] = &res[i]; |
| 588 | } | 588 | } |
| 589 | 589 | ||
| 590 | } else if(bus->self) { | 590 | } else if (bus->parent) { |
| 591 | int i; | 591 | int i; |
| 592 | 592 | ||
| 593 | pci_read_bridge_bases(bus); | 593 | pci_read_bridge_bases(bus); |
| @@ -611,12 +611,12 @@ dino_fixup_bus(struct pci_bus *bus) | |||
| 611 | } | 611 | } |
| 612 | 612 | ||
| 613 | DBG("DEBUG %s assigning %d [0x%lx,0x%lx]\n", | 613 | DBG("DEBUG %s assigning %d [0x%lx,0x%lx]\n", |
| 614 | bus->self->dev.bus_id, i, | 614 | dev_name(&bus->self->dev), i, |
| 615 | bus->self->resource[i].start, | 615 | bus->self->resource[i].start, |
| 616 | bus->self->resource[i].end); | 616 | bus->self->resource[i].end); |
| 617 | pci_assign_resource(bus->self, i); | 617 | pci_assign_resource(bus->self, i); |
| 618 | DBG("DEBUG %s after assign %d [0x%lx,0x%lx]\n", | 618 | DBG("DEBUG %s after assign %d [0x%lx,0x%lx]\n", |
| 619 | bus->self->dev.bus_id, i, | 619 | dev_name(&bus->self->dev), i, |
| 620 | bus->self->resource[i].start, | 620 | bus->self->resource[i].start, |
| 621 | bus->self->resource[i].end); | 621 | bus->self->resource[i].end); |
| 622 | } | 622 | } |
| @@ -1026,7 +1026,8 @@ static int __init dino_probe(struct parisc_device *dev) | |||
| 1026 | dino_current_bus = bus->subordinate + 1; | 1026 | dino_current_bus = bus->subordinate + 1; |
| 1027 | pci_bus_assign_resources(bus); | 1027 | pci_bus_assign_resources(bus); |
| 1028 | } else { | 1028 | } else { |
| 1029 | printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (probably duplicate bus number %d)\n", dev->dev.bus_id, dino_current_bus); | 1029 | printk(KERN_ERR "ERROR: failed to scan PCI bus on %s (probably duplicate bus number %d)\n", |
| 1030 | dev_name(&dev->dev), dino_current_bus); | ||
| 1030 | /* increment the bus number in case of duplicates */ | 1031 | /* increment the bus number in case of duplicates */ |
| 1031 | dino_current_bus++; | 1032 | dino_current_bus++; |
| 1032 | } | 1033 | } |
diff --git a/drivers/parisc/gsc.c b/drivers/parisc/gsc.c index e76db9e4d504..d33632917696 100644 --- a/drivers/parisc/gsc.c +++ b/drivers/parisc/gsc.c | |||
| @@ -186,29 +186,34 @@ void gsc_asic_assign_irq(struct gsc_asic *asic, int local_irq, int *irqp) | |||
| 186 | *irqp = irq; | 186 | *irqp = irq; |
| 187 | } | 187 | } |
| 188 | 188 | ||
| 189 | static struct device *next_device(struct klist_iter *i) | 189 | struct gsc_fixup_struct { |
| 190 | void (*choose_irq)(struct parisc_device *, void *); | ||
| 191 | void *ctrl; | ||
| 192 | }; | ||
| 193 | |||
| 194 | static int gsc_fixup_irqs_callback(struct device *dev, void *data) | ||
| 190 | { | 195 | { |
| 191 | struct klist_node * n = klist_next(i); | 196 | struct parisc_device *padev = to_parisc_device(dev); |
| 192 | return n ? container_of(n, struct device, knode_parent) : NULL; | 197 | struct gsc_fixup_struct *gf = data; |
| 198 | |||
| 199 | /* work-around for 715/64 and others which have parent | ||
| 200 | at path [5] and children at path [5/0/x] */ | ||
| 201 | if (padev->id.hw_type == HPHW_FAULTY) | ||
| 202 | gsc_fixup_irqs(padev, gf->ctrl, gf->choose_irq); | ||
| 203 | gf->choose_irq(padev, gf->ctrl); | ||
| 204 | |||
| 205 | return 0; | ||
| 193 | } | 206 | } |
| 194 | 207 | ||
| 195 | void gsc_fixup_irqs(struct parisc_device *parent, void *ctrl, | 208 | void gsc_fixup_irqs(struct parisc_device *parent, void *ctrl, |
| 196 | void (*choose_irq)(struct parisc_device *, void *)) | 209 | void (*choose_irq)(struct parisc_device *, void *)) |
| 197 | { | 210 | { |
| 198 | struct device *dev; | 211 | struct gsc_fixup_struct data = { |
| 199 | struct klist_iter i; | 212 | .choose_irq = choose_irq, |
| 200 | 213 | .ctrl = ctrl, | |
| 201 | klist_iter_init(&parent->dev.klist_children, &i); | 214 | }; |
| 202 | while ((dev = next_device(&i))) { | 215 | |
| 203 | struct parisc_device *padev = to_parisc_device(dev); | 216 | device_for_each_child(&parent->dev, &data, gsc_fixup_irqs_callback); |
| 204 | |||
| 205 | /* work-around for 715/64 and others which have parent | ||
| 206 | at path [5] and children at path [5/0/x] */ | ||
| 207 | if (padev->id.hw_type == HPHW_FAULTY) | ||
| 208 | return gsc_fixup_irqs(padev, ctrl, choose_irq); | ||
| 209 | choose_irq(padev, ctrl); | ||
| 210 | } | ||
| 211 | klist_iter_exit(&i); | ||
| 212 | } | 217 | } |
| 213 | 218 | ||
| 214 | int gsc_common_setup(struct parisc_device *parent, struct gsc_asic *gsc_asic) | 219 | int gsc_common_setup(struct parisc_device *parent, struct gsc_asic *gsc_asic) |
diff --git a/drivers/parisc/iosapic.c b/drivers/parisc/iosapic.c index 0797659ee016..501aaf1f253f 100644 --- a/drivers/parisc/iosapic.c +++ b/drivers/parisc/iosapic.c | |||
| @@ -487,7 +487,7 @@ iosapic_xlate_pin(struct iosapic_info *isi, struct pci_dev *pcidev) | |||
| 487 | } | 487 | } |
| 488 | 488 | ||
| 489 | /* Check if pcidev behind a PPB */ | 489 | /* Check if pcidev behind a PPB */ |
| 490 | if (NULL != pcidev->bus->self) { | 490 | if (pcidev->bus->parent) { |
| 491 | /* Convert pcidev INTR_PIN into something we | 491 | /* Convert pcidev INTR_PIN into something we |
| 492 | ** can lookup in the IRT. | 492 | ** can lookup in the IRT. |
| 493 | */ | 493 | */ |
| @@ -523,10 +523,9 @@ iosapic_xlate_pin(struct iosapic_info *isi, struct pci_dev *pcidev) | |||
| 523 | #endif /* PCI_BRIDGE_FUNCS */ | 523 | #endif /* PCI_BRIDGE_FUNCS */ |
| 524 | 524 | ||
| 525 | /* | 525 | /* |
| 526 | ** Locate the host slot the PPB nearest the Host bus | 526 | * Locate the host slot of the PPB. |
| 527 | ** adapter. | 527 | */ |
| 528 | */ | 528 | while (p->parent->parent) |
| 529 | while (NULL != p->parent->self) | ||
| 530 | p = p->parent; | 529 | p = p->parent; |
| 531 | 530 | ||
| 532 | intr_slot = PCI_SLOT(p->self->devfn); | 531 | intr_slot = PCI_SLOT(p->self->devfn); |
| @@ -709,11 +708,14 @@ static void iosapic_set_affinity_irq(unsigned int irq, | |||
| 709 | struct vector_info *vi = iosapic_get_vector(irq); | 708 | struct vector_info *vi = iosapic_get_vector(irq); |
| 710 | u32 d0, d1, dummy_d0; | 709 | u32 d0, d1, dummy_d0; |
| 711 | unsigned long flags; | 710 | unsigned long flags; |
| 711 | int dest_cpu; | ||
| 712 | 712 | ||
| 713 | if (cpu_check_affinity(irq, dest)) | 713 | dest_cpu = cpu_check_affinity(irq, dest); |
| 714 | if (dest_cpu < 0) | ||
| 714 | return; | 715 | return; |
| 715 | 716 | ||
| 716 | vi->txn_addr = txn_affinity_addr(irq, cpumask_first(dest)); | 717 | irq_desc[irq].affinity = cpumask_of_cpu(dest_cpu); |
| 718 | vi->txn_addr = txn_affinity_addr(irq, dest_cpu); | ||
| 717 | 719 | ||
| 718 | spin_lock_irqsave(&iosapic_lock, flags); | 720 | spin_lock_irqsave(&iosapic_lock, flags); |
| 719 | /* d1 contains the destination CPU, so only want to set that | 721 | /* d1 contains the destination CPU, so only want to set that |
diff --git a/drivers/parisc/lba_pci.c b/drivers/parisc/lba_pci.c index d8233de8c75d..59fbbf128365 100644 --- a/drivers/parisc/lba_pci.c +++ b/drivers/parisc/lba_pci.c | |||
| @@ -644,7 +644,7 @@ lba_fixup_bus(struct pci_bus *bus) | |||
| 644 | ** Properly Setup MMIO resources for this bus. | 644 | ** Properly Setup MMIO resources for this bus. |
| 645 | ** pci_alloc_primary_bus() mangles this. | 645 | ** pci_alloc_primary_bus() mangles this. |
| 646 | */ | 646 | */ |
| 647 | if (bus->self) { | 647 | if (bus->parent) { |
| 648 | int i; | 648 | int i; |
| 649 | /* PCI-PCI Bridge */ | 649 | /* PCI-PCI Bridge */ |
| 650 | pci_read_bridge_bases(bus); | 650 | pci_read_bridge_bases(bus); |
| @@ -802,7 +802,7 @@ lba_fixup_bus(struct pci_bus *bus) | |||
| 802 | ** Can't fixup here anyway....garr... | 802 | ** Can't fixup here anyway....garr... |
| 803 | */ | 803 | */ |
| 804 | if (fbb_enable) { | 804 | if (fbb_enable) { |
| 805 | if (bus->self) { | 805 | if (bus->parent) { |
| 806 | u8 control; | 806 | u8 control; |
| 807 | /* enable on PPB */ | 807 | /* enable on PPB */ |
| 808 | (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control); | 808 | (void) pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &control); |
diff --git a/drivers/parisc/sba_iommu.c b/drivers/parisc/sba_iommu.c index a70cf16ee1ad..e5999c4cedc8 100644 --- a/drivers/parisc/sba_iommu.c +++ b/drivers/parisc/sba_iommu.c | |||
| @@ -1206,30 +1206,48 @@ sba_alloc_pdir(unsigned int pdir_size) | |||
| 1206 | return (void *) pdir_base; | 1206 | return (void *) pdir_base; |
| 1207 | } | 1207 | } |
| 1208 | 1208 | ||
| 1209 | static struct device *next_device(struct klist_iter *i) | 1209 | struct ibase_data_struct { |
| 1210 | struct ioc *ioc; | ||
| 1211 | int ioc_num; | ||
| 1212 | }; | ||
| 1213 | |||
| 1214 | static int setup_ibase_imask_callback(struct device *dev, void *data) | ||
| 1210 | { | 1215 | { |
| 1211 | struct klist_node * n = klist_next(i); | 1216 | /* lba_set_iregs() is in drivers/parisc/lba_pci.c */ |
| 1212 | return n ? container_of(n, struct device, knode_parent) : NULL; | 1217 | extern void lba_set_iregs(struct parisc_device *, u32, u32); |
| 1218 | struct parisc_device *lba = to_parisc_device(dev); | ||
| 1219 | struct ibase_data_struct *ibd = data; | ||
| 1220 | int rope_num = (lba->hpa.start >> 13) & 0xf; | ||
| 1221 | if (rope_num >> 3 == ibd->ioc_num) | ||
| 1222 | lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask); | ||
| 1223 | return 0; | ||
| 1213 | } | 1224 | } |
| 1214 | 1225 | ||
| 1215 | /* setup Mercury or Elroy IBASE/IMASK registers. */ | 1226 | /* setup Mercury or Elroy IBASE/IMASK registers. */ |
| 1216 | static void | 1227 | static void |
| 1217 | setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num) | 1228 | setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num) |
| 1218 | { | 1229 | { |
| 1219 | /* lba_set_iregs() is in drivers/parisc/lba_pci.c */ | 1230 | struct ibase_data_struct ibase_data = { |
| 1220 | extern void lba_set_iregs(struct parisc_device *, u32, u32); | 1231 | .ioc = ioc, |
| 1221 | struct device *dev; | 1232 | .ioc_num = ioc_num, |
| 1222 | struct klist_iter i; | 1233 | }; |
| 1223 | 1234 | ||
| 1224 | klist_iter_init(&sba->dev.klist_children, &i); | 1235 | device_for_each_child(&sba->dev, &ibase_data, |
| 1225 | while ((dev = next_device(&i))) { | 1236 | setup_ibase_imask_callback); |
| 1226 | struct parisc_device *lba = to_parisc_device(dev); | 1237 | } |
| 1227 | int rope_num = (lba->hpa.start >> 13) & 0xf; | 1238 | |
| 1228 | if (rope_num >> 3 == ioc_num) | 1239 | #ifdef SBA_AGP_SUPPORT |
| 1229 | lba_set_iregs(lba, ioc->ibase, ioc->imask); | 1240 | static int |
| 1230 | } | 1241 | sba_ioc_find_quicksilver(struct device *dev, void *data) |
| 1231 | klist_iter_exit(&i); | 1242 | { |
| 1243 | int *agp_found = data; | ||
| 1244 | struct parisc_device *lba = to_parisc_device(dev); | ||
| 1245 | |||
| 1246 | if (IS_QUICKSILVER(lba)) | ||
| 1247 | *agp_found = 1; | ||
| 1248 | return 0; | ||
| 1232 | } | 1249 | } |
| 1250 | #endif | ||
| 1233 | 1251 | ||
| 1234 | static void | 1252 | static void |
| 1235 | sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num) | 1253 | sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num) |
| @@ -1332,9 +1350,6 @@ sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num) | |||
| 1332 | WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM); | 1350 | WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM); |
| 1333 | 1351 | ||
| 1334 | #ifdef SBA_AGP_SUPPORT | 1352 | #ifdef SBA_AGP_SUPPORT |
| 1335 | { | ||
| 1336 | struct klist_iter i; | ||
| 1337 | struct device *dev = NULL; | ||
| 1338 | 1353 | ||
| 1339 | /* | 1354 | /* |
| 1340 | ** If an AGP device is present, only use half of the IOV space | 1355 | ** If an AGP device is present, only use half of the IOV space |
| @@ -1344,13 +1359,7 @@ sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num) | |||
| 1344 | ** We program the next pdir index after we stop w/ a key for | 1359 | ** We program the next pdir index after we stop w/ a key for |
| 1345 | ** the GART code to handshake on. | 1360 | ** the GART code to handshake on. |
| 1346 | */ | 1361 | */ |
| 1347 | klist_iter_init(&sba->dev.klist_children, &i); | 1362 | device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver); |
| 1348 | while ((dev = next_device(&i))) { | ||
| 1349 | struct parisc_device *lba = to_parisc_device(dev); | ||
| 1350 | if (IS_QUICKSILVER(lba)) | ||
| 1351 | agp_found = 1; | ||
| 1352 | } | ||
| 1353 | klist_iter_exit(&i); | ||
| 1354 | 1363 | ||
| 1355 | if (agp_found && sba_reserve_agpgart) { | 1364 | if (agp_found && sba_reserve_agpgart) { |
| 1356 | printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n", | 1365 | printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n", |
| @@ -1358,9 +1367,7 @@ sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num) | |||
| 1358 | ioc->pdir_size /= 2; | 1367 | ioc->pdir_size /= 2; |
| 1359 | ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE; | 1368 | ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE; |
| 1360 | } | 1369 | } |
| 1361 | } | ||
| 1362 | #endif /*SBA_AGP_SUPPORT*/ | 1370 | #endif /*SBA_AGP_SUPPORT*/ |
| 1363 | |||
| 1364 | } | 1371 | } |
| 1365 | 1372 | ||
| 1366 | static void | 1373 | static void |
diff --git a/drivers/pci/hotplug/Kconfig b/drivers/pci/hotplug/Kconfig index eacfb13998bb..9aa4fe100a0d 100644 --- a/drivers/pci/hotplug/Kconfig +++ b/drivers/pci/hotplug/Kconfig | |||
| @@ -143,7 +143,7 @@ config HOTPLUG_PCI_SHPC | |||
| 143 | 143 | ||
| 144 | config HOTPLUG_PCI_RPA | 144 | config HOTPLUG_PCI_RPA |
| 145 | tristate "RPA PCI Hotplug driver" | 145 | tristate "RPA PCI Hotplug driver" |
| 146 | depends on PPC_PSERIES && PPC64 && !HOTPLUG_PCI_FAKE | 146 | depends on PPC_PSERIES && EEH && !HOTPLUG_PCI_FAKE |
| 147 | help | 147 | help |
| 148 | Say Y here if you have a RPA system that supports PCI Hotplug. | 148 | Say Y here if you have a RPA system that supports PCI Hotplug. |
| 149 | 149 | ||
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c index d0c973685868..382575007382 100644 --- a/drivers/pci/pcie/aer/aerdrv_core.c +++ b/drivers/pci/pcie/aer/aerdrv_core.c | |||
| @@ -133,6 +133,9 @@ static void set_downstream_devices_error_reporting(struct pci_dev *dev, | |||
| 133 | bool enable) | 133 | bool enable) |
| 134 | { | 134 | { |
| 135 | set_device_error_reporting(dev, &enable); | 135 | set_device_error_reporting(dev, &enable); |
| 136 | |||
| 137 | if (!dev->subordinate) | ||
| 138 | return; | ||
| 136 | pci_walk_bus(dev->subordinate, set_device_error_reporting, &enable); | 139 | pci_walk_bus(dev->subordinate, set_device_error_reporting, &enable); |
| 137 | } | 140 | } |
| 138 | 141 | ||
diff --git a/drivers/pci/pcie/portdrv_pci.c b/drivers/pci/pcie/portdrv_pci.c index 248b4db91552..5ea566e20b37 100644 --- a/drivers/pci/pcie/portdrv_pci.c +++ b/drivers/pci/pcie/portdrv_pci.c | |||
| @@ -103,6 +103,7 @@ static int __devinit pcie_portdrv_probe (struct pci_dev *dev, | |||
| 103 | static void pcie_portdrv_remove (struct pci_dev *dev) | 103 | static void pcie_portdrv_remove (struct pci_dev *dev) |
| 104 | { | 104 | { |
| 105 | pcie_port_device_remove(dev); | 105 | pcie_port_device_remove(dev); |
| 106 | pci_disable_device(dev); | ||
| 106 | kfree(pci_get_drvdata(dev)); | 107 | kfree(pci_get_drvdata(dev)); |
| 107 | } | 108 | } |
| 108 | 109 | ||
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index f20d55368edb..92b9efe9bcaf 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c | |||
| @@ -23,6 +23,7 @@ | |||
| 23 | #include <linux/acpi.h> | 23 | #include <linux/acpi.h> |
| 24 | #include <linux/kallsyms.h> | 24 | #include <linux/kallsyms.h> |
| 25 | #include <linux/dmi.h> | 25 | #include <linux/dmi.h> |
| 26 | #include <linux/pci-aspm.h> | ||
| 26 | #include "pci.h" | 27 | #include "pci.h" |
| 27 | 28 | ||
| 28 | int isa_dma_bridge_buggy; | 29 | int isa_dma_bridge_buggy; |
| @@ -1749,6 +1750,30 @@ static void __devinit quirk_e100_interrupt(struct pci_dev *dev) | |||
| 1749 | } | 1750 | } |
| 1750 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); | 1751 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt); |
| 1751 | 1752 | ||
| 1753 | /* | ||
| 1754 | * The 82575 and 82598 may experience data corruption issues when transitioning | ||
| 1755 | * out of L0S. To prevent this we need to disable L0S on the pci-e link | ||
| 1756 | */ | ||
| 1757 | static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev) | ||
| 1758 | { | ||
| 1759 | dev_info(&dev->dev, "Disabling L0s\n"); | ||
| 1760 | pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); | ||
| 1761 | } | ||
| 1762 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); | ||
| 1763 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); | ||
| 1764 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); | ||
| 1765 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); | ||
| 1766 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); | ||
| 1767 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); | ||
| 1768 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); | ||
| 1769 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); | ||
| 1770 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); | ||
| 1771 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); | ||
| 1772 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); | ||
| 1773 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); | ||
| 1774 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); | ||
| 1775 | DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); | ||
| 1776 | |||
| 1752 | static void __devinit fixup_rev1_53c810(struct pci_dev* dev) | 1777 | static void __devinit fixup_rev1_53c810(struct pci_dev* dev) |
| 1753 | { | 1778 | { |
| 1754 | /* rev 1 ncr53c810 chips don't set the class at all which means | 1779 | /* rev 1 ncr53c810 chips don't set the class at all which means |
| @@ -2097,7 +2122,7 @@ static void __devinit ht_disable_msi_mapping(struct pci_dev *dev) | |||
| 2097 | 2122 | ||
| 2098 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, | 2123 | if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, |
| 2099 | &flags) == 0) { | 2124 | &flags) == 0) { |
| 2100 | dev_info(&dev->dev, "Enabling HT MSI Mapping\n"); | 2125 | dev_info(&dev->dev, "Disabling HT MSI Mapping\n"); |
| 2101 | 2126 | ||
| 2102 | pci_write_config_byte(dev, pos + HT_MSI_FLAGS, | 2127 | pci_write_config_byte(dev, pos + HT_MSI_FLAGS, |
| 2103 | flags & ~HT_MSI_FLAGS_ENABLE); | 2128 | flags & ~HT_MSI_FLAGS_ENABLE); |
| @@ -2141,6 +2166,10 @@ static void __devinit nv_msi_ht_cap_quirk(struct pci_dev *dev) | |||
| 2141 | int pos; | 2166 | int pos; |
| 2142 | int found; | 2167 | int found; |
| 2143 | 2168 | ||
| 2169 | /* Enabling HT MSI mapping on this device breaks MCP51 */ | ||
| 2170 | if (dev->device == 0x270) | ||
| 2171 | return; | ||
| 2172 | |||
| 2144 | /* check if there is HT MSI cap or enabled on this device */ | 2173 | /* check if there is HT MSI cap or enabled on this device */ |
| 2145 | found = ht_check_msi_mapping(dev); | 2174 | found = ht_check_msi_mapping(dev); |
| 2146 | 2175 | ||
diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c index bb9ddb9532e3..16f84aab6ab3 100644 --- a/drivers/pcmcia/pxa2xx_base.c +++ b/drivers/pcmcia/pxa2xx_base.c | |||
| @@ -28,7 +28,6 @@ | |||
| 28 | #include <asm/io.h> | 28 | #include <asm/io.h> |
| 29 | #include <asm/irq.h> | 29 | #include <asm/irq.h> |
| 30 | #include <asm/system.h> | 30 | #include <asm/system.h> |
| 31 | #include <mach/pxa-regs.h> | ||
| 32 | #include <mach/pxa2xx-regs.h> | 31 | #include <mach/pxa2xx-regs.h> |
| 33 | #include <asm/mach-types.h> | 32 | #include <asm/mach-types.h> |
| 34 | 33 | ||
| @@ -39,6 +38,44 @@ | |||
| 39 | #include "soc_common.h" | 38 | #include "soc_common.h" |
| 40 | #include "pxa2xx_base.h" | 39 | #include "pxa2xx_base.h" |
| 41 | 40 | ||
| 41 | /* | ||
| 42 | * Personal Computer Memory Card International Association (PCMCIA) sockets | ||
| 43 | */ | ||
| 44 | |||
| 45 | #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */ | ||
| 46 | #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */ | ||
| 47 | #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */ | ||
| 48 | #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */ | ||
| 49 | #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */ | ||
| 50 | |||
| 51 | #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */ | ||
| 52 | #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */ | ||
| 53 | #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */ | ||
| 54 | #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */ | ||
| 55 | |||
| 56 | #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */ | ||
| 57 | #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */ | ||
| 58 | #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */ | ||
| 59 | #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */ | ||
| 60 | |||
| 61 | #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \ | ||
| 62 | (0x20000000 + (Nb) * PCMCIASp) | ||
| 63 | #define _PCMCIAIO(Nb) _PCMCIA(Nb) /* PCMCIA I/O [0..1] */ | ||
| 64 | #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \ | ||
| 65 | (_PCMCIA(Nb) + 2 * PCMCIAPrtSp) | ||
| 66 | #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \ | ||
| 67 | (_PCMCIA(Nb) + 3 * PCMCIAPrtSp) | ||
| 68 | |||
| 69 | #define _PCMCIA0 _PCMCIA(0) /* PCMCIA 0 */ | ||
| 70 | #define _PCMCIA0IO _PCMCIAIO(0) /* PCMCIA 0 I/O */ | ||
| 71 | #define _PCMCIA0Attr _PCMCIAAttr(0) /* PCMCIA 0 Attribute */ | ||
| 72 | #define _PCMCIA0Mem _PCMCIAMem(0) /* PCMCIA 0 Memory */ | ||
| 73 | |||
| 74 | #define _PCMCIA1 _PCMCIA(1) /* PCMCIA 1 */ | ||
| 75 | #define _PCMCIA1IO _PCMCIAIO(1) /* PCMCIA 1 I/O */ | ||
| 76 | #define _PCMCIA1Attr _PCMCIAAttr(1) /* PCMCIA 1 Attribute */ | ||
| 77 | #define _PCMCIA1Mem _PCMCIAMem(1) /* PCMCIA 1 Memory */ | ||
| 78 | |||
| 42 | 79 | ||
| 43 | #define MCXX_SETUP_MASK (0x7f) | 80 | #define MCXX_SETUP_MASK (0x7f) |
| 44 | #define MCXX_ASST_MASK (0x1f) | 81 | #define MCXX_ASST_MASK (0x1f) |
| @@ -183,23 +220,67 @@ static void pxa2xx_configure_sockets(struct device *dev) | |||
| 183 | MECR &= ~MECR_NOS; | 220 | MECR &= ~MECR_NOS; |
| 184 | } | 221 | } |
| 185 | 222 | ||
| 223 | static const char *skt_names[] = { | ||
| 224 | "PCMCIA socket 0", | ||
| 225 | "PCMCIA socket 1", | ||
| 226 | }; | ||
| 227 | |||
| 228 | #define SKT_DEV_INFO_SIZE(n) \ | ||
| 229 | (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket)) | ||
| 230 | |||
| 186 | int __pxa2xx_drv_pcmcia_probe(struct device *dev) | 231 | int __pxa2xx_drv_pcmcia_probe(struct device *dev) |
| 187 | { | 232 | { |
| 188 | int ret; | 233 | int i, ret; |
| 189 | struct pcmcia_low_level *ops; | 234 | struct pcmcia_low_level *ops; |
| 235 | struct skt_dev_info *sinfo; | ||
| 236 | struct soc_pcmcia_socket *skt; | ||
| 190 | 237 | ||
| 191 | if (!dev || !dev->platform_data) | 238 | if (!dev || !dev->platform_data) |
| 192 | return -ENODEV; | 239 | return -ENODEV; |
| 193 | 240 | ||
| 194 | ops = (struct pcmcia_low_level *)dev->platform_data; | 241 | ops = (struct pcmcia_low_level *)dev->platform_data; |
| 195 | 242 | ||
| 243 | sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL); | ||
| 244 | if (!sinfo) | ||
| 245 | return -ENOMEM; | ||
| 246 | |||
| 247 | sinfo->nskt = ops->nr; | ||
| 248 | |||
| 249 | /* Initialize processor specific parameters */ | ||
| 250 | for (i = 0; i < ops->nr; i++) { | ||
| 251 | skt = &sinfo->skt[i]; | ||
| 252 | |||
| 253 | skt->nr = i; | ||
| 254 | skt->irq = NO_IRQ; | ||
| 255 | |||
| 256 | skt->res_skt.start = _PCMCIA(skt->nr); | ||
| 257 | skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1; | ||
| 258 | skt->res_skt.name = skt_names[skt->nr]; | ||
| 259 | skt->res_skt.flags = IORESOURCE_MEM; | ||
| 260 | |||
| 261 | skt->res_io.start = _PCMCIAIO(skt->nr); | ||
| 262 | skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1; | ||
| 263 | skt->res_io.name = "io"; | ||
| 264 | skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY; | ||
| 265 | |||
| 266 | skt->res_mem.start = _PCMCIAMem(skt->nr); | ||
| 267 | skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1; | ||
| 268 | skt->res_mem.name = "memory"; | ||
| 269 | skt->res_mem.flags = IORESOURCE_MEM; | ||
| 270 | |||
| 271 | skt->res_attr.start = _PCMCIAAttr(skt->nr); | ||
| 272 | skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1; | ||
| 273 | skt->res_attr.name = "attribute"; | ||
| 274 | skt->res_attr.flags = IORESOURCE_MEM; | ||
| 275 | } | ||
| 276 | |||
| 196 | /* Provide our PXA2xx specific timing routines. */ | 277 | /* Provide our PXA2xx specific timing routines. */ |
| 197 | ops->set_timing = pxa2xx_pcmcia_set_timing; | 278 | ops->set_timing = pxa2xx_pcmcia_set_timing; |
| 198 | #ifdef CONFIG_CPU_FREQ | 279 | #ifdef CONFIG_CPU_FREQ |
| 199 | ops->frequency_change = pxa2xx_pcmcia_frequency_change; | 280 | ops->frequency_change = pxa2xx_pcmcia_frequency_change; |
| 200 | #endif | 281 | #endif |
| 201 | 282 | ||
| 202 | ret = soc_common_drv_pcmcia_probe(dev, ops, ops->first, ops->nr); | 283 | ret = soc_common_drv_pcmcia_probe(dev, ops, sinfo); |
| 203 | 284 | ||
| 204 | if (!ret) | 285 | if (!ret) |
| 205 | pxa2xx_configure_sockets(dev); | 286 | pxa2xx_configure_sockets(dev); |
diff --git a/drivers/pcmcia/pxa2xx_cm_x255.c b/drivers/pcmcia/pxa2xx_cm_x255.c index 7c8bcb476622..4ed64d8e95e7 100644 --- a/drivers/pcmcia/pxa2xx_cm_x255.c +++ b/drivers/pcmcia/pxa2xx_cm_x255.c | |||
| @@ -16,7 +16,6 @@ | |||
| 16 | #include <linux/gpio.h> | 16 | #include <linux/gpio.h> |
| 17 | 17 | ||
| 18 | #include <asm/mach-types.h> | 18 | #include <asm/mach-types.h> |
| 19 | #include <mach/pxa-regs.h> | ||
| 20 | 19 | ||
| 21 | #include "soc_common.h" | 20 | #include "soc_common.h" |
| 22 | 21 | ||
diff --git a/drivers/pcmcia/pxa2xx_cm_x270.c b/drivers/pcmcia/pxa2xx_cm_x270.c index 6c3aac377126..a7b943d01e34 100644 --- a/drivers/pcmcia/pxa2xx_cm_x270.c +++ b/drivers/pcmcia/pxa2xx_cm_x270.c | |||
| @@ -16,7 +16,6 @@ | |||
| 16 | #include <linux/gpio.h> | 16 | #include <linux/gpio.h> |
| 17 | 17 | ||
| 18 | #include <asm/mach-types.h> | 18 | #include <asm/mach-types.h> |
| 19 | #include <mach/pxa-regs.h> | ||
| 20 | 19 | ||
| 21 | #include "soc_common.h" | 20 | #include "soc_common.h" |
| 22 | 21 | ||
diff --git a/drivers/pcmcia/pxa2xx_e740.c b/drivers/pcmcia/pxa2xx_e740.c index f663a011bf4a..d09c0dc4a31a 100644 --- a/drivers/pcmcia/pxa2xx_e740.c +++ b/drivers/pcmcia/pxa2xx_e740.c | |||
| @@ -16,8 +16,6 @@ | |||
| 16 | #include <linux/interrupt.h> | 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
| 18 | 18 | ||
| 19 | #include <mach/hardware.h> | ||
| 20 | #include <mach/pxa-regs.h> | ||
| 21 | #include <mach/eseries-gpio.h> | 19 | #include <mach/eseries-gpio.h> |
| 22 | 20 | ||
| 23 | #include <asm/irq.h> | 21 | #include <asm/irq.h> |
diff --git a/drivers/pcmcia/pxa2xx_lubbock.c b/drivers/pcmcia/pxa2xx_lubbock.c index 37ec55df086e..6cbb1b1f7cfd 100644 --- a/drivers/pcmcia/pxa2xx_lubbock.c +++ b/drivers/pcmcia/pxa2xx_lubbock.c | |||
| @@ -24,7 +24,6 @@ | |||
| 24 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
| 25 | #include <asm/hardware/sa1111.h> | 25 | #include <asm/hardware/sa1111.h> |
| 26 | #include <asm/mach-types.h> | 26 | #include <asm/mach-types.h> |
| 27 | #include <mach/pxa-regs.h> | ||
| 28 | #include <mach/lubbock.h> | 27 | #include <mach/lubbock.h> |
| 29 | 28 | ||
| 30 | #include "sa1111_generic.h" | 29 | #include "sa1111_generic.h" |
diff --git a/drivers/pcmcia/pxa2xx_mainstone.c b/drivers/pcmcia/pxa2xx_mainstone.c index 877001db4916..1138551ba8f6 100644 --- a/drivers/pcmcia/pxa2xx_mainstone.c +++ b/drivers/pcmcia/pxa2xx_mainstone.c | |||
| @@ -21,11 +21,10 @@ | |||
| 21 | 21 | ||
| 22 | #include <pcmcia/ss.h> | 22 | #include <pcmcia/ss.h> |
| 23 | 23 | ||
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
| 26 | #include <asm/irq.h> | 25 | #include <asm/irq.h> |
| 27 | 26 | ||
| 28 | #include <mach/pxa-regs.h> | 27 | #include <mach/pxa2xx-regs.h> |
| 29 | #include <mach/mainstone.h> | 28 | #include <mach/mainstone.h> |
| 30 | 29 | ||
| 31 | #include "soc_common.h" | 30 | #include "soc_common.h" |
diff --git a/drivers/pcmcia/pxa2xx_trizeps4.c b/drivers/pcmcia/pxa2xx_trizeps4.c index 36c7a0b324d2..e0e5cb339b4a 100644 --- a/drivers/pcmcia/pxa2xx_trizeps4.c +++ b/drivers/pcmcia/pxa2xx_trizeps4.c | |||
| @@ -22,8 +22,7 @@ | |||
| 22 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
| 23 | #include <asm/irq.h> | 23 | #include <asm/irq.h> |
| 24 | 24 | ||
| 25 | #include <mach/hardware.h> | 25 | #include <mach/pxa2xx-regs.h> |
| 26 | #include <mach/pxa-regs.h> | ||
| 27 | #include <mach/trizeps4.h> | 26 | #include <mach/trizeps4.h> |
| 28 | 27 | ||
| 29 | #include "soc_common.h" | 28 | #include "soc_common.h" |
diff --git a/drivers/pcmcia/pxa2xx_viper.c b/drivers/pcmcia/pxa2xx_viper.c index dd10481be7bf..17871360fe99 100644 --- a/drivers/pcmcia/pxa2xx_viper.c +++ b/drivers/pcmcia/pxa2xx_viper.c | |||
| @@ -26,7 +26,6 @@ | |||
| 26 | 26 | ||
| 27 | #include <asm/irq.h> | 27 | #include <asm/irq.h> |
| 28 | 28 | ||
| 29 | #include <mach/pxa-regs.h> | ||
| 30 | #include <mach/viper.h> | 29 | #include <mach/viper.h> |
| 31 | #include <asm/mach-types.h> | 30 | #include <asm/mach-types.h> |
| 32 | 31 | ||
diff --git a/drivers/pcmcia/sa1100_h3600.c b/drivers/pcmcia/sa1100_h3600.c index 6de4e1b41d60..0cc3748f3758 100644 --- a/drivers/pcmcia/sa1100_h3600.c +++ b/drivers/pcmcia/sa1100_h3600.c | |||
| @@ -37,9 +37,9 @@ static void h3600_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt) | |||
| 37 | soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs)); | 37 | soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs)); |
| 38 | 38 | ||
| 39 | /* Disable CF bus: */ | 39 | /* Disable CF bus: */ |
| 40 | clr_h3600_egpio(IPAQ_EGPIO_OPT_NVRAM_ON); | 40 | assign_h3600_egpio(IPAQ_EGPIO_OPT_NVRAM_ON, 0); |
| 41 | clr_h3600_egpio(IPAQ_EGPIO_OPT_ON); | 41 | assign_h3600_egpio(IPAQ_EGPIO_OPT_ON, 0); |
| 42 | set_h3600_egpio(IPAQ_EGPIO_OPT_RESET); | 42 | assign_h3600_egpio(IPAQ_EGPIO_OPT_RESET, 1); |
| 43 | } | 43 | } |
| 44 | 44 | ||
| 45 | static void | 45 | static void |
| @@ -79,10 +79,7 @@ h3600_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_ | |||
| 79 | return -1; | 79 | return -1; |
| 80 | } | 80 | } |
| 81 | 81 | ||
| 82 | if (state->flags & SS_RESET) | 82 | assign_h3600_egpio(IPAQ_EGPIO_CARD_RESET, !!(state->flags & SS_RESET)); |
| 83 | set_h3600_egpio(IPAQ_EGPIO_CARD_RESET); | ||
| 84 | else | ||
| 85 | clr_h3600_egpio(IPAQ_EGPIO_CARD_RESET); | ||
| 86 | 83 | ||
| 87 | /* Silently ignore Vpp, output enable, speaker enable. */ | 84 | /* Silently ignore Vpp, output enable, speaker enable. */ |
| 88 | 85 | ||
| @@ -92,9 +89,9 @@ h3600_pcmcia_configure_socket(struct soc_pcmcia_socket *skt, const socket_state_ | |||
| 92 | static void h3600_pcmcia_socket_init(struct soc_pcmcia_socket *skt) | 89 | static void h3600_pcmcia_socket_init(struct soc_pcmcia_socket *skt) |
| 93 | { | 90 | { |
| 94 | /* Enable CF bus: */ | 91 | /* Enable CF bus: */ |
| 95 | set_h3600_egpio(IPAQ_EGPIO_OPT_NVRAM_ON); | 92 | assign_h3600_egpio(IPAQ_EGPIO_OPT_NVRAM_ON, 1); |
| 96 | set_h3600_egpio(IPAQ_EGPIO_OPT_ON); | 93 | assign_h3600_egpio(IPAQ_EGPIO_OPT_ON, 1); |
| 97 | clr_h3600_egpio(IPAQ_EGPIO_OPT_RESET); | 94 | assign_h3600_egpio(IPAQ_EGPIO_OPT_RESET, 0); |
| 98 | 95 | ||
| 99 | msleep(10); | 96 | msleep(10); |
| 100 | 97 | ||
| @@ -112,10 +109,10 @@ static void h3600_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt) | |||
| 112 | * socket 0 then socket 1. | 109 | * socket 0 then socket 1. |
| 113 | */ | 110 | */ |
| 114 | if (skt->nr == 1) { | 111 | if (skt->nr == 1) { |
| 115 | clr_h3600_egpio(IPAQ_EGPIO_OPT_ON); | 112 | assign_h3600_egpio(IPAQ_EGPIO_OPT_ON, 0); |
| 116 | clr_h3600_egpio(IPAQ_EGPIO_OPT_NVRAM_ON); | 113 | assign_h3600_egpio(IPAQ_EGPIO_OPT_NVRAM_ON, 0); |
| 117 | /* hmm, does this suck power? */ | 114 | /* hmm, does this suck power? */ |
| 118 | set_h3600_egpio(IPAQ_EGPIO_OPT_RESET); | 115 | assign_h3600_egpio(IPAQ_EGPIO_OPT_RESET, 1); |
| 119 | } | 116 | } |
| 120 | } | 117 | } |
| 121 | 118 | ||
diff --git a/drivers/pcmcia/sa1111_generic.c b/drivers/pcmcia/sa1111_generic.c index 6924d0ea8d32..401052a21ce8 100644 --- a/drivers/pcmcia/sa1111_generic.c +++ b/drivers/pcmcia/sa1111_generic.c | |||
| @@ -11,12 +11,12 @@ | |||
| 11 | #include <linux/device.h> | 11 | #include <linux/device.h> |
| 12 | #include <linux/interrupt.h> | 12 | #include <linux/interrupt.h> |
| 13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
| 14 | #include <linux/io.h> | ||
| 14 | 15 | ||
| 15 | #include <pcmcia/ss.h> | 16 | #include <pcmcia/ss.h> |
| 16 | 17 | ||
| 17 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
| 18 | #include <asm/hardware/sa1111.h> | 19 | #include <asm/hardware/sa1111.h> |
| 19 | #include <asm/io.h> | ||
| 20 | #include <asm/irq.h> | 20 | #include <asm/irq.h> |
| 21 | 21 | ||
| 22 | #include "sa1111_generic.h" | 22 | #include "sa1111_generic.h" |
diff --git a/drivers/pcmcia/sa11xx_base.c b/drivers/pcmcia/sa11xx_base.c index 7cb1273202cc..e15d59f2d8a9 100644 --- a/drivers/pcmcia/sa11xx_base.c +++ b/drivers/pcmcia/sa11xx_base.c | |||
| @@ -36,9 +36,9 @@ | |||
| 36 | #include <linux/ioport.h> | 36 | #include <linux/ioport.h> |
| 37 | #include <linux/kernel.h> | 37 | #include <linux/kernel.h> |
| 38 | #include <linux/spinlock.h> | 38 | #include <linux/spinlock.h> |
| 39 | #include <linux/io.h> | ||
| 39 | 40 | ||
| 40 | #include <mach/hardware.h> | 41 | #include <mach/hardware.h> |
| 41 | #include <asm/io.h> | ||
| 42 | #include <asm/irq.h> | 42 | #include <asm/irq.h> |
| 43 | #include <asm/system.h> | 43 | #include <asm/system.h> |
| 44 | 44 | ||
| @@ -163,9 +163,55 @@ sa1100_pcmcia_show_timing(struct soc_pcmcia_socket *skt, char *buf) | |||
| 163 | return p - buf; | 163 | return p - buf; |
| 164 | } | 164 | } |
| 165 | 165 | ||
| 166 | static const char *skt_names[] = { | ||
| 167 | "PCMCIA socket 0", | ||
| 168 | "PCMCIA socket 1", | ||
| 169 | }; | ||
| 170 | |||
| 171 | #define SKT_DEV_INFO_SIZE(n) \ | ||
| 172 | (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket)) | ||
| 173 | |||
| 166 | int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, | 174 | int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, |
| 167 | int first, int nr) | 175 | int first, int nr) |
| 168 | { | 176 | { |
| 177 | struct skt_dev_info *sinfo; | ||
| 178 | struct soc_pcmcia_socket *skt; | ||
| 179 | int i; | ||
| 180 | |||
| 181 | sinfo = kzalloc(SKT_DEV_INFO_SIZE(nr), GFP_KERNEL); | ||
| 182 | if (!sinfo) | ||
| 183 | return -ENOMEM; | ||
| 184 | |||
| 185 | sinfo->nskt = nr; | ||
| 186 | |||
| 187 | /* Initiliaze processor specific parameters */ | ||
| 188 | for (i = 0; i < nr; i++) { | ||
| 189 | skt = &sinfo->skt[i]; | ||
| 190 | |||
| 191 | skt->nr = first + i; | ||
| 192 | skt->irq = NO_IRQ; | ||
| 193 | |||
| 194 | skt->res_skt.start = _PCMCIA(skt->nr); | ||
| 195 | skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1; | ||
| 196 | skt->res_skt.name = skt_names[skt->nr]; | ||
| 197 | skt->res_skt.flags = IORESOURCE_MEM; | ||
| 198 | |||
| 199 | skt->res_io.start = _PCMCIAIO(skt->nr); | ||
| 200 | skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1; | ||
| 201 | skt->res_io.name = "io"; | ||
| 202 | skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY; | ||
| 203 | |||
| 204 | skt->res_mem.start = _PCMCIAMem(skt->nr); | ||
| 205 | skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1; | ||
| 206 | skt->res_mem.name = "memory"; | ||
| 207 | skt->res_mem.flags = IORESOURCE_MEM; | ||
| 208 | |||
| 209 | skt->res_attr.start = _PCMCIAAttr(skt->nr); | ||
| 210 | skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1; | ||
| 211 | skt->res_attr.name = "attribute"; | ||
| 212 | skt->res_attr.flags = IORESOURCE_MEM; | ||
| 213 | } | ||
| 214 | |||
| 169 | /* | 215 | /* |
| 170 | * set default MECR calculation if the board specific | 216 | * set default MECR calculation if the board specific |
| 171 | * code did not specify one... | 217 | * code did not specify one... |
| @@ -180,7 +226,7 @@ int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, | |||
| 180 | ops->frequency_change = sa1100_pcmcia_frequency_change; | 226 | ops->frequency_change = sa1100_pcmcia_frequency_change; |
| 181 | #endif | 227 | #endif |
| 182 | 228 | ||
| 183 | return soc_common_drv_pcmcia_probe(dev, ops, first, nr); | 229 | return soc_common_drv_pcmcia_probe(dev, ops, sinfo); |
| 184 | } | 230 | } |
| 185 | EXPORT_SYMBOL(sa11xx_drv_pcmcia_probe); | 231 | EXPORT_SYMBOL(sa11xx_drv_pcmcia_probe); |
| 186 | 232 | ||
diff --git a/drivers/pcmcia/soc_common.c b/drivers/pcmcia/soc_common.c index f49ac6666153..163cf98e2386 100644 --- a/drivers/pcmcia/soc_common.c +++ b/drivers/pcmcia/soc_common.c | |||
| @@ -49,11 +49,6 @@ | |||
| 49 | 49 | ||
| 50 | #include "soc_common.h" | 50 | #include "soc_common.h" |
| 51 | 51 | ||
| 52 | /* FIXME: platform dependent resource declaration has to move out of this file */ | ||
| 53 | #ifdef CONFIG_ARCH_PXA | ||
| 54 | #include <mach/pxa-regs.h> | ||
| 55 | #endif | ||
| 56 | |||
| 57 | #ifdef CONFIG_PCMCIA_DEBUG | 52 | #ifdef CONFIG_PCMCIA_DEBUG |
| 58 | 53 | ||
| 59 | static int pc_debug; | 54 | static int pc_debug; |
| @@ -581,19 +576,6 @@ EXPORT_SYMBOL(soc_pcmcia_enable_irqs); | |||
| 581 | LIST_HEAD(soc_pcmcia_sockets); | 576 | LIST_HEAD(soc_pcmcia_sockets); |
| 582 | static DEFINE_MUTEX(soc_pcmcia_sockets_lock); | 577 | static DEFINE_MUTEX(soc_pcmcia_sockets_lock); |
| 583 | 578 | ||
| 584 | static const char *skt_names[] = { | ||
| 585 | "PCMCIA socket 0", | ||
| 586 | "PCMCIA socket 1", | ||
| 587 | }; | ||
| 588 | |||
| 589 | struct skt_dev_info { | ||
| 590 | int nskt; | ||
| 591 | struct soc_pcmcia_socket skt[0]; | ||
| 592 | }; | ||
| 593 | |||
| 594 | #define SKT_DEV_INFO_SIZE(n) \ | ||
| 595 | (sizeof(struct skt_dev_info) + (n)*sizeof(struct soc_pcmcia_socket)) | ||
| 596 | |||
| 597 | #ifdef CONFIG_CPU_FREQ | 579 | #ifdef CONFIG_CPU_FREQ |
| 598 | static int | 580 | static int |
| 599 | soc_pcmcia_notifier(struct notifier_block *nb, unsigned long val, void *data) | 581 | soc_pcmcia_notifier(struct notifier_block *nb, unsigned long val, void *data) |
| @@ -637,26 +619,18 @@ static int soc_pcmcia_cpufreq_register(void) { return 0; } | |||
| 637 | static void soc_pcmcia_cpufreq_unregister(void) {} | 619 | static void soc_pcmcia_cpufreq_unregister(void) {} |
| 638 | #endif | 620 | #endif |
| 639 | 621 | ||
| 640 | int soc_common_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, int first, int nr) | 622 | int soc_common_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, |
| 623 | struct skt_dev_info *sinfo) | ||
| 641 | { | 624 | { |
| 642 | struct skt_dev_info *sinfo; | ||
| 643 | struct soc_pcmcia_socket *skt; | 625 | struct soc_pcmcia_socket *skt; |
| 644 | int ret, i; | 626 | int ret, i; |
| 645 | 627 | ||
| 646 | mutex_lock(&soc_pcmcia_sockets_lock); | 628 | mutex_lock(&soc_pcmcia_sockets_lock); |
| 647 | 629 | ||
| 648 | sinfo = kzalloc(SKT_DEV_INFO_SIZE(nr), GFP_KERNEL); | ||
| 649 | if (!sinfo) { | ||
| 650 | ret = -ENOMEM; | ||
| 651 | goto out; | ||
| 652 | } | ||
| 653 | |||
| 654 | sinfo->nskt = nr; | ||
| 655 | |||
| 656 | /* | 630 | /* |
| 657 | * Initialise the per-socket structure. | 631 | * Initialise the per-socket structure. |
| 658 | */ | 632 | */ |
| 659 | for (i = 0; i < nr; i++) { | 633 | for (i = 0; i < sinfo->nskt; i++) { |
| 660 | skt = &sinfo->skt[i]; | 634 | skt = &sinfo->skt[i]; |
| 661 | 635 | ||
| 662 | skt->socket.ops = &soc_common_pcmcia_operations; | 636 | skt->socket.ops = &soc_common_pcmcia_operations; |
| @@ -668,43 +642,21 @@ int soc_common_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops | |||
| 668 | skt->poll_timer.data = (unsigned long)skt; | 642 | skt->poll_timer.data = (unsigned long)skt; |
| 669 | skt->poll_timer.expires = jiffies + SOC_PCMCIA_POLL_PERIOD; | 643 | skt->poll_timer.expires = jiffies + SOC_PCMCIA_POLL_PERIOD; |
| 670 | 644 | ||
| 671 | skt->nr = first + i; | ||
| 672 | skt->irq = NO_IRQ; | ||
| 673 | skt->dev = dev; | 645 | skt->dev = dev; |
| 674 | skt->ops = ops; | 646 | skt->ops = ops; |
| 675 | 647 | ||
| 676 | skt->res_skt.start = _PCMCIA(skt->nr); | ||
| 677 | skt->res_skt.end = _PCMCIA(skt->nr) + PCMCIASp - 1; | ||
| 678 | skt->res_skt.name = skt_names[skt->nr]; | ||
| 679 | skt->res_skt.flags = IORESOURCE_MEM; | ||
| 680 | |||
| 681 | ret = request_resource(&iomem_resource, &skt->res_skt); | 648 | ret = request_resource(&iomem_resource, &skt->res_skt); |
| 682 | if (ret) | 649 | if (ret) |
| 683 | goto out_err_1; | 650 | goto out_err_1; |
| 684 | 651 | ||
| 685 | skt->res_io.start = _PCMCIAIO(skt->nr); | ||
| 686 | skt->res_io.end = _PCMCIAIO(skt->nr) + PCMCIAIOSp - 1; | ||
| 687 | skt->res_io.name = "io"; | ||
| 688 | skt->res_io.flags = IORESOURCE_MEM | IORESOURCE_BUSY; | ||
| 689 | |||
| 690 | ret = request_resource(&skt->res_skt, &skt->res_io); | 652 | ret = request_resource(&skt->res_skt, &skt->res_io); |
| 691 | if (ret) | 653 | if (ret) |
| 692 | goto out_err_2; | 654 | goto out_err_2; |
| 693 | 655 | ||
| 694 | skt->res_mem.start = _PCMCIAMem(skt->nr); | ||
| 695 | skt->res_mem.end = _PCMCIAMem(skt->nr) + PCMCIAMemSp - 1; | ||
| 696 | skt->res_mem.name = "memory"; | ||
| 697 | skt->res_mem.flags = IORESOURCE_MEM; | ||
| 698 | |||
| 699 | ret = request_resource(&skt->res_skt, &skt->res_mem); | 656 | ret = request_resource(&skt->res_skt, &skt->res_mem); |
| 700 | if (ret) | 657 | if (ret) |
| 701 | goto out_err_3; | 658 | goto out_err_3; |
| 702 | 659 | ||
| 703 | skt->res_attr.start = _PCMCIAAttr(skt->nr); | ||
| 704 | skt->res_attr.end = _PCMCIAAttr(skt->nr) + PCMCIAAttrSp - 1; | ||
| 705 | skt->res_attr.name = "attribute"; | ||
| 706 | skt->res_attr.flags = IORESOURCE_MEM; | ||
| 707 | |||
| 708 | ret = request_resource(&skt->res_skt, &skt->res_attr); | 660 | ret = request_resource(&skt->res_skt, &skt->res_attr); |
| 709 | if (ret) | 661 | if (ret) |
| 710 | goto out_err_4; | 662 | goto out_err_4; |
diff --git a/drivers/pcmcia/soc_common.h b/drivers/pcmcia/soc_common.h index 38c67375f363..290e143839ee 100644 --- a/drivers/pcmcia/soc_common.h +++ b/drivers/pcmcia/soc_common.h | |||
| @@ -58,6 +58,11 @@ struct soc_pcmcia_socket { | |||
| 58 | struct list_head node; | 58 | struct list_head node; |
| 59 | }; | 59 | }; |
| 60 | 60 | ||
| 61 | struct skt_dev_info { | ||
| 62 | int nskt; | ||
| 63 | struct soc_pcmcia_socket skt[0]; | ||
| 64 | }; | ||
| 65 | |||
| 61 | struct pcmcia_state { | 66 | struct pcmcia_state { |
| 62 | unsigned detect: 1, | 67 | unsigned detect: 1, |
| 63 | ready: 1, | 68 | ready: 1, |
| @@ -132,7 +137,7 @@ extern void soc_common_pcmcia_get_timing(struct soc_pcmcia_socket *, struct soc_ | |||
| 132 | 137 | ||
| 133 | extern struct list_head soc_pcmcia_sockets; | 138 | extern struct list_head soc_pcmcia_sockets; |
| 134 | 139 | ||
| 135 | extern int soc_common_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, int first, int nr); | 140 | extern int soc_common_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, struct skt_dev_info *sinfo); |
| 136 | extern int soc_common_drv_pcmcia_remove(struct device *dev); | 141 | extern int soc_common_drv_pcmcia_remove(struct device *dev); |
| 137 | 142 | ||
| 138 | 143 | ||
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig index b3866ad50227..3608081bc3e0 100644 --- a/drivers/platform/x86/Kconfig +++ b/drivers/platform/x86/Kconfig | |||
| @@ -15,8 +15,7 @@ menuconfig X86_PLATFORM_DEVICES | |||
| 15 | if X86_PLATFORM_DEVICES | 15 | if X86_PLATFORM_DEVICES |
| 16 | 16 | ||
| 17 | config ACER_WMI | 17 | config ACER_WMI |
| 18 | tristate "Acer WMI Laptop Extras (EXPERIMENTAL)" | 18 | tristate "Acer WMI Laptop Extras" |
| 19 | depends on EXPERIMENTAL | ||
| 20 | depends on ACPI | 19 | depends on ACPI |
| 21 | depends on LEDS_CLASS | 20 | depends on LEDS_CLASS |
| 22 | depends on NEW_LEDS | 21 | depends on NEW_LEDS |
| @@ -39,9 +38,9 @@ config ASUS_LAPTOP | |||
| 39 | tristate "Asus Laptop Extras (EXPERIMENTAL)" | 38 | tristate "Asus Laptop Extras (EXPERIMENTAL)" |
| 40 | depends on ACPI | 39 | depends on ACPI |
| 41 | depends on EXPERIMENTAL && !ACPI_ASUS | 40 | depends on EXPERIMENTAL && !ACPI_ASUS |
| 42 | depends on LEDS_CLASS | 41 | select LEDS_CLASS |
| 43 | depends on NEW_LEDS | 42 | select NEW_LEDS |
| 44 | depends on BACKLIGHT_CLASS_DEVICE | 43 | select BACKLIGHT_CLASS_DEVICE |
| 45 | depends on INPUT | 44 | depends on INPUT |
| 46 | ---help--- | 45 | ---help--- |
| 47 | This is the new Linux driver for Asus laptops. It may also support some | 46 | This is the new Linux driver for Asus laptops. It may also support some |
| @@ -185,11 +184,11 @@ config SONYPI_COMPAT | |||
| 185 | config THINKPAD_ACPI | 184 | config THINKPAD_ACPI |
| 186 | tristate "ThinkPad ACPI Laptop Extras" | 185 | tristate "ThinkPad ACPI Laptop Extras" |
| 187 | depends on ACPI | 186 | depends on ACPI |
| 187 | depends on INPUT | ||
| 188 | select BACKLIGHT_LCD_SUPPORT | 188 | select BACKLIGHT_LCD_SUPPORT |
| 189 | select BACKLIGHT_CLASS_DEVICE | 189 | select BACKLIGHT_CLASS_DEVICE |
| 190 | select HWMON | 190 | select HWMON |
| 191 | select NVRAM | 191 | select NVRAM |
| 192 | select INPUT | ||
| 193 | select NEW_LEDS | 192 | select NEW_LEDS |
| 194 | select LEDS_CLASS | 193 | select LEDS_CLASS |
| 195 | select NET | 194 | select NET |
| @@ -315,9 +314,8 @@ config EEEPC_LAPTOP | |||
| 315 | 314 | ||
| 316 | 315 | ||
| 317 | config ACPI_WMI | 316 | config ACPI_WMI |
| 318 | tristate "WMI (EXPERIMENTAL)" | 317 | tristate "WMI" |
| 319 | depends on ACPI | 318 | depends on ACPI |
| 320 | depends on EXPERIMENTAL | ||
| 321 | help | 319 | help |
| 322 | This driver adds support for the ACPI-WMI (Windows Management | 320 | This driver adds support for the ACPI-WMI (Windows Management |
| 323 | Instrumentation) mapper device (PNP0C14) found on some systems. | 321 | Instrumentation) mapper device (PNP0C14) found on some systems. |
diff --git a/drivers/platform/x86/acer-wmi.c b/drivers/platform/x86/acer-wmi.c index 94c9f911824e..a6a42e8c060b 100644 --- a/drivers/platform/x86/acer-wmi.c +++ b/drivers/platform/x86/acer-wmi.c | |||
| @@ -1026,7 +1026,7 @@ static void acer_rfkill_exit(void) | |||
| 1026 | kfree(wireless_rfkill->data); | 1026 | kfree(wireless_rfkill->data); |
| 1027 | rfkill_unregister(wireless_rfkill); | 1027 | rfkill_unregister(wireless_rfkill); |
| 1028 | if (has_cap(ACER_CAP_BLUETOOTH)) { | 1028 | if (has_cap(ACER_CAP_BLUETOOTH)) { |
| 1029 | kfree(wireless_rfkill->data); | 1029 | kfree(bluetooth_rfkill->data); |
| 1030 | rfkill_unregister(bluetooth_rfkill); | 1030 | rfkill_unregister(bluetooth_rfkill); |
| 1031 | } | 1031 | } |
| 1032 | return; | 1032 | return; |
| @@ -1297,7 +1297,7 @@ static int __init acer_wmi_init(void) | |||
| 1297 | 1297 | ||
| 1298 | set_quirks(); | 1298 | set_quirks(); |
| 1299 | 1299 | ||
| 1300 | if (!acpi_video_backlight_support() && has_cap(ACER_CAP_BRIGHTNESS)) { | 1300 | if (acpi_video_backlight_support() && has_cap(ACER_CAP_BRIGHTNESS)) { |
| 1301 | interface->capability &= ~ACER_CAP_BRIGHTNESS; | 1301 | interface->capability &= ~ACER_CAP_BRIGHTNESS; |
| 1302 | printk(ACER_INFO "Brightness must be controlled by " | 1302 | printk(ACER_INFO "Brightness must be controlled by " |
| 1303 | "generic video driver\n"); | 1303 | "generic video driver\n"); |
diff --git a/drivers/platform/x86/asus-laptop.c b/drivers/platform/x86/asus-laptop.c index 56af6cf385b0..eeafc6c0160d 100644 --- a/drivers/platform/x86/asus-laptop.c +++ b/drivers/platform/x86/asus-laptop.c | |||
| @@ -815,6 +815,7 @@ static int asus_setkeycode(struct input_dev *dev, int scancode, int keycode) | |||
| 815 | static void asus_hotk_notify(acpi_handle handle, u32 event, void *data) | 815 | static void asus_hotk_notify(acpi_handle handle, u32 event, void *data) |
| 816 | { | 816 | { |
| 817 | static struct key_entry *key; | 817 | static struct key_entry *key; |
| 818 | u16 count; | ||
| 818 | 819 | ||
| 819 | /* TODO Find a better way to handle events count. */ | 820 | /* TODO Find a better way to handle events count. */ |
| 820 | if (!hotk) | 821 | if (!hotk) |
| @@ -832,9 +833,11 @@ static void asus_hotk_notify(acpi_handle handle, u32 event, void *data) | |||
| 832 | lcd_blank(FB_BLANK_POWERDOWN); | 833 | lcd_blank(FB_BLANK_POWERDOWN); |
| 833 | } | 834 | } |
| 834 | 835 | ||
| 836 | count = hotk->event_count[event % 128]++; | ||
| 837 | acpi_bus_generate_proc_event(hotk->device, event, count); | ||
| 835 | acpi_bus_generate_netlink_event(hotk->device->pnp.device_class, | 838 | acpi_bus_generate_netlink_event(hotk->device->pnp.device_class, |
| 836 | dev_name(&hotk->device->dev), event, | 839 | dev_name(&hotk->device->dev), event, |
| 837 | hotk->event_count[event % 128]++); | 840 | count); |
| 838 | 841 | ||
| 839 | if (hotk->inputdev) { | 842 | if (hotk->inputdev) { |
| 840 | key = asus_get_entry_by_scancode(event); | 843 | key = asus_get_entry_by_scancode(event); |
diff --git a/drivers/platform/x86/eeepc-laptop.c b/drivers/platform/x86/eeepc-laptop.c index 786ed8661cb0..6f54fd1757cd 100644 --- a/drivers/platform/x86/eeepc-laptop.c +++ b/drivers/platform/x86/eeepc-laptop.c | |||
| @@ -557,13 +557,17 @@ static void eeepc_rfkill_notify(acpi_handle handle, u32 event, void *data) | |||
| 557 | static void eeepc_hotk_notify(acpi_handle handle, u32 event, void *data) | 557 | static void eeepc_hotk_notify(acpi_handle handle, u32 event, void *data) |
| 558 | { | 558 | { |
| 559 | static struct key_entry *key; | 559 | static struct key_entry *key; |
| 560 | u16 count; | ||
| 561 | |||
| 560 | if (!ehotk) | 562 | if (!ehotk) |
| 561 | return; | 563 | return; |
| 562 | if (event >= NOTIFY_BRN_MIN && event <= NOTIFY_BRN_MAX) | 564 | if (event >= NOTIFY_BRN_MIN && event <= NOTIFY_BRN_MAX) |
| 563 | notify_brn(); | 565 | notify_brn(); |
| 566 | count = ehotk->event_count[event % 128]++; | ||
| 567 | acpi_bus_generate_proc_event(ehotk->device, event, count); | ||
| 564 | acpi_bus_generate_netlink_event(ehotk->device->pnp.device_class, | 568 | acpi_bus_generate_netlink_event(ehotk->device->pnp.device_class, |
| 565 | dev_name(&ehotk->device->dev), event, | 569 | dev_name(&ehotk->device->dev), event, |
| 566 | ehotk->event_count[event % 128]++); | 570 | count); |
| 567 | if (ehotk->inputdev) { | 571 | if (ehotk->inputdev) { |
| 568 | key = eepc_get_entry_by_scancode(event); | 572 | key = eepc_get_entry_by_scancode(event); |
| 569 | if (key) { | 573 | if (key) { |
diff --git a/drivers/platform/x86/thinkpad_acpi.c b/drivers/platform/x86/thinkpad_acpi.c index bcbc05107ba8..d2433204a40c 100644 --- a/drivers/platform/x86/thinkpad_acpi.c +++ b/drivers/platform/x86/thinkpad_acpi.c | |||
| @@ -7532,7 +7532,7 @@ MODULE_ALIAS(TPACPI_DRVR_SHORTNAME); | |||
| 7532 | * if it is not there yet. | 7532 | * if it is not there yet. |
| 7533 | */ | 7533 | */ |
| 7534 | #define IBM_BIOS_MODULE_ALIAS(__type) \ | 7534 | #define IBM_BIOS_MODULE_ALIAS(__type) \ |
| 7535 | MODULE_ALIAS("dmi:bvnIBM:bvr" __type "ET??WW") | 7535 | MODULE_ALIAS("dmi:bvnIBM:bvr" __type "ET??WW*") |
| 7536 | 7536 | ||
| 7537 | /* Non-ancient thinkpads */ | 7537 | /* Non-ancient thinkpads */ |
| 7538 | MODULE_ALIAS("dmi:bvnIBM:*:svnIBM:*:pvrThinkPad*:rvnIBM:*"); | 7538 | MODULE_ALIAS("dmi:bvnIBM:*:svnIBM:*:pvrThinkPad*:rvnIBM:*"); |
| @@ -7541,9 +7541,9 @@ MODULE_ALIAS("dmi:bvnLENOVO:*:svnLENOVO:*:pvrThinkPad*:rvnLENOVO:*"); | |||
| 7541 | /* Ancient thinkpad BIOSes have to be identified by | 7541 | /* Ancient thinkpad BIOSes have to be identified by |
| 7542 | * BIOS type or model number, and there are far less | 7542 | * BIOS type or model number, and there are far less |
| 7543 | * BIOS types than model numbers... */ | 7543 | * BIOS types than model numbers... */ |
| 7544 | IBM_BIOS_MODULE_ALIAS("I[B,D,H,I,M,N,O,T,W,V,Y,Z]"); | 7544 | IBM_BIOS_MODULE_ALIAS("I[BDHIMNOTWVYZ]"); |
| 7545 | IBM_BIOS_MODULE_ALIAS("1[0,3,6,8,A-G,I,K,M-P,S,T]"); | 7545 | IBM_BIOS_MODULE_ALIAS("1[0368A-GIKM-PST]"); |
| 7546 | IBM_BIOS_MODULE_ALIAS("K[U,X-Z]"); | 7546 | IBM_BIOS_MODULE_ALIAS("K[UX-Z]"); |
| 7547 | 7547 | ||
| 7548 | MODULE_AUTHOR("Borislav Deianov, Henrique de Moraes Holschuh"); | 7548 | MODULE_AUTHOR("Borislav Deianov, Henrique de Moraes Holschuh"); |
| 7549 | MODULE_DESCRIPTION(TPACPI_DESC); | 7549 | MODULE_DESCRIPTION(TPACPI_DESC); |
diff --git a/drivers/platform/x86/wmi.c b/drivers/platform/x86/wmi.c index 8a8b377712c9..2f269e117b8f 100644 --- a/drivers/platform/x86/wmi.c +++ b/drivers/platform/x86/wmi.c | |||
| @@ -708,7 +708,7 @@ static int __init acpi_wmi_add(struct acpi_device *device) | |||
| 708 | 708 | ||
| 709 | static int __init acpi_wmi_init(void) | 709 | static int __init acpi_wmi_init(void) |
| 710 | { | 710 | { |
| 711 | acpi_status result; | 711 | int result; |
| 712 | 712 | ||
| 713 | INIT_LIST_HEAD(&wmi_blocks.list); | 713 | INIT_LIST_HEAD(&wmi_blocks.list); |
| 714 | 714 | ||
diff --git a/drivers/power/ds2760_battery.c b/drivers/power/ds2760_battery.c index 1d768928e0bb..a52d4a11652d 100644 --- a/drivers/power/ds2760_battery.c +++ b/drivers/power/ds2760_battery.c | |||
| @@ -180,10 +180,13 @@ static int ds2760_battery_read_status(struct ds2760_device_info *di) | |||
| 180 | di->empty_uAh = battery_interpolate(scale, di->temp_C / 10); | 180 | di->empty_uAh = battery_interpolate(scale, di->temp_C / 10); |
| 181 | di->empty_uAh *= 1000; /* convert to µAh */ | 181 | di->empty_uAh *= 1000; /* convert to µAh */ |
| 182 | 182 | ||
| 183 | /* From Maxim Application Note 131: remaining capacity = | 183 | if (di->full_active_uAh == di->empty_uAh) |
| 184 | * ((ICA - Empty Value) / (Full Value - Empty Value)) x 100% */ | 184 | di->rem_capacity = 0; |
| 185 | di->rem_capacity = ((di->accum_current_uAh - di->empty_uAh) * 100L) / | 185 | else |
| 186 | (di->full_active_uAh - di->empty_uAh); | 186 | /* From Maxim Application Note 131: remaining capacity = |
| 187 | * ((ICA - Empty Value) / (Full Value - Empty Value)) x 100% */ | ||
| 188 | di->rem_capacity = ((di->accum_current_uAh - di->empty_uAh) * 100L) / | ||
| 189 | (di->full_active_uAh - di->empty_uAh); | ||
| 187 | 190 | ||
| 188 | if (di->rem_capacity < 0) | 191 | if (di->rem_capacity < 0) |
| 189 | di->rem_capacity = 0; | 192 | di->rem_capacity = 0; |
diff --git a/drivers/rtc/rtc-mv.c b/drivers/rtc/rtc-mv.c index 45f12dcd3716..e0263d2005ee 100644 --- a/drivers/rtc/rtc-mv.c +++ b/drivers/rtc/rtc-mv.c | |||
| @@ -12,6 +12,7 @@ | |||
| 12 | #include <linux/bcd.h> | 12 | #include <linux/bcd.h> |
| 13 | #include <linux/io.h> | 13 | #include <linux/io.h> |
| 14 | #include <linux/platform_device.h> | 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/delay.h> | ||
| 15 | 16 | ||
| 16 | 17 | ||
| 17 | #define RTC_TIME_REG_OFFS 0 | 18 | #define RTC_TIME_REG_OFFS 0 |
| @@ -119,6 +120,16 @@ static int __init mv_rtc_probe(struct platform_device *pdev) | |||
| 119 | return -EINVAL; | 120 | return -EINVAL; |
| 120 | } | 121 | } |
| 121 | 122 | ||
| 123 | /* make sure it is actually functional */ | ||
| 124 | if (rtc_time == 0x01000000) { | ||
| 125 | ssleep(1); | ||
| 126 | rtc_time = readl(pdata->ioaddr + RTC_TIME_REG_OFFS); | ||
| 127 | if (rtc_time == 0x01000000) { | ||
| 128 | dev_err(&pdev->dev, "internal RTC not ticking\n"); | ||
| 129 | return -ENODEV; | ||
| 130 | } | ||
| 131 | } | ||
| 132 | |||
| 122 | platform_set_drvdata(pdev, pdata); | 133 | platform_set_drvdata(pdev, pdata); |
| 123 | pdata->rtc = rtc_device_register(pdev->name, &pdev->dev, | 134 | pdata->rtc = rtc_device_register(pdev->name, &pdev->dev, |
| 124 | &mv_rtc_ops, THIS_MODULE); | 135 | &mv_rtc_ops, THIS_MODULE); |
diff --git a/drivers/rtc/rtc-sa1100.c b/drivers/rtc/rtc-sa1100.c index d26a5f82aaba..4f247e4dd3f9 100644 --- a/drivers/rtc/rtc-sa1100.c +++ b/drivers/rtc/rtc-sa1100.c | |||
| @@ -35,7 +35,8 @@ | |||
| 35 | #include <asm/irq.h> | 35 | #include <asm/irq.h> |
| 36 | 36 | ||
| 37 | #ifdef CONFIG_ARCH_PXA | 37 | #ifdef CONFIG_ARCH_PXA |
| 38 | #include <mach/pxa-regs.h> | 38 | #include <mach/regs-rtc.h> |
| 39 | #include <mach/regs-ost.h> | ||
| 39 | #endif | 40 | #endif |
| 40 | 41 | ||
| 41 | #define RTC_DEF_DIVIDER 32768 - 1 | 42 | #define RTC_DEF_DIVIDER 32768 - 1 |
diff --git a/drivers/sbus/char/bbc_i2c.c b/drivers/sbus/char/bbc_i2c.c index f08e169ba1b5..7e30e5f6e032 100644 --- a/drivers/sbus/char/bbc_i2c.c +++ b/drivers/sbus/char/bbc_i2c.c | |||
| @@ -129,7 +129,7 @@ static int wait_for_pin(struct bbc_i2c_bus *bp, u8 *status) | |||
| 129 | bp->waiting = 1; | 129 | bp->waiting = 1; |
| 130 | add_wait_queue(&bp->wq, &wait); | 130 | add_wait_queue(&bp->wq, &wait); |
| 131 | while (limit-- > 0) { | 131 | while (limit-- > 0) { |
| 132 | unsigned long val; | 132 | long val; |
| 133 | 133 | ||
| 134 | val = wait_event_interruptible_timeout( | 134 | val = wait_event_interruptible_timeout( |
| 135 | bp->wq, | 135 | bp->wq, |
diff --git a/drivers/sbus/char/jsflash.c b/drivers/sbus/char/jsflash.c index a9a9893a5f95..e6d1fc8c54f1 100644 --- a/drivers/sbus/char/jsflash.c +++ b/drivers/sbus/char/jsflash.c | |||
| @@ -38,9 +38,6 @@ | |||
| 38 | #include <linux/string.h> | 38 | #include <linux/string.h> |
| 39 | #include <linux/genhd.h> | 39 | #include <linux/genhd.h> |
| 40 | #include <linux/blkdev.h> | 40 | #include <linux/blkdev.h> |
| 41 | |||
| 42 | #define MAJOR_NR JSFD_MAJOR | ||
| 43 | |||
| 44 | #include <asm/uaccess.h> | 41 | #include <asm/uaccess.h> |
| 45 | #include <asm/pgtable.h> | 42 | #include <asm/pgtable.h> |
| 46 | #include <asm/io.h> | 43 | #include <asm/io.h> |
diff --git a/drivers/sbus/char/openprom.c b/drivers/sbus/char/openprom.c index 29dc735e1a20..124f660a0383 100644 --- a/drivers/sbus/char/openprom.c +++ b/drivers/sbus/char/openprom.c | |||
| @@ -51,6 +51,7 @@ MODULE_AUTHOR("Thomas K. Dyas (tdyas@noc.rutgers.edu) and Eddie C. Dost (ecd@sk | |||
| 51 | MODULE_DESCRIPTION("OPENPROM Configuration Driver"); | 51 | MODULE_DESCRIPTION("OPENPROM Configuration Driver"); |
| 52 | MODULE_LICENSE("GPL"); | 52 | MODULE_LICENSE("GPL"); |
| 53 | MODULE_VERSION("1.0"); | 53 | MODULE_VERSION("1.0"); |
| 54 | MODULE_ALIAS_MISCDEV(SUN_OPENPROM_MINOR); | ||
| 54 | 55 | ||
| 55 | /* Private data kept by the driver for each descriptor. */ | 56 | /* Private data kept by the driver for each descriptor. */ |
| 56 | typedef struct openprom_private_data | 57 | typedef struct openprom_private_data |
diff --git a/drivers/scsi/arm/cumana_2.c b/drivers/scsi/arm/cumana_2.c index 68a64123af8f..8ee01b907332 100644 --- a/drivers/scsi/arm/cumana_2.c +++ b/drivers/scsi/arm/cumana_2.c | |||
| @@ -390,7 +390,8 @@ static struct scsi_host_template cumanascsi2_template = { | |||
| 390 | .eh_abort_handler = fas216_eh_abort, | 390 | .eh_abort_handler = fas216_eh_abort, |
| 391 | .can_queue = 1, | 391 | .can_queue = 1, |
| 392 | .this_id = 7, | 392 | .this_id = 7, |
| 393 | .sg_tablesize = SG_ALL, | 393 | .sg_tablesize = SCSI_MAX_SG_CHAIN_SEGMENTS, |
| 394 | .dma_boundary = IOMD_DMA_BOUNDARY, | ||
| 394 | .cmd_per_lun = 1, | 395 | .cmd_per_lun = 1, |
| 395 | .use_clustering = DISABLE_CLUSTERING, | 396 | .use_clustering = DISABLE_CLUSTERING, |
| 396 | .proc_name = "cumanascsi2", | 397 | .proc_name = "cumanascsi2", |
diff --git a/drivers/scsi/arm/eesox.c b/drivers/scsi/arm/eesox.c index bb2477b3fb0b..d8435132f461 100644 --- a/drivers/scsi/arm/eesox.c +++ b/drivers/scsi/arm/eesox.c | |||
| @@ -508,7 +508,8 @@ static struct scsi_host_template eesox_template = { | |||
| 508 | .eh_abort_handler = fas216_eh_abort, | 508 | .eh_abort_handler = fas216_eh_abort, |
| 509 | .can_queue = 1, | 509 | .can_queue = 1, |
| 510 | .this_id = 7, | 510 | .this_id = 7, |
| 511 | .sg_tablesize = SG_ALL, | 511 | .sg_tablesize = SCSI_MAX_SG_CHAIN_SEGMENTS, |
| 512 | .dma_boundary = IOMD_DMA_BOUNDARY, | ||
| 512 | .cmd_per_lun = 1, | 513 | .cmd_per_lun = 1, |
| 513 | .use_clustering = DISABLE_CLUSTERING, | 514 | .use_clustering = DISABLE_CLUSTERING, |
| 514 | .proc_name = "eesox", | 515 | .proc_name = "eesox", |
diff --git a/drivers/scsi/arm/powertec.c b/drivers/scsi/arm/powertec.c index d9a546d1917c..e2297b4c1b9e 100644 --- a/drivers/scsi/arm/powertec.c +++ b/drivers/scsi/arm/powertec.c | |||
| @@ -302,7 +302,8 @@ static struct scsi_host_template powertecscsi_template = { | |||
| 302 | 302 | ||
| 303 | .can_queue = 8, | 303 | .can_queue = 8, |
| 304 | .this_id = 7, | 304 | .this_id = 7, |
| 305 | .sg_tablesize = SG_ALL, | 305 | .sg_tablesize = SCSI_MAX_SG_CHAIN_SEGMENTS, |
| 306 | .dma_boundary = IOMD_DMA_BOUNDARY, | ||
| 306 | .cmd_per_lun = 2, | 307 | .cmd_per_lun = 2, |
| 307 | .use_clustering = ENABLE_CLUSTERING, | 308 | .use_clustering = ENABLE_CLUSTERING, |
| 308 | .proc_name = "powertec", | 309 | .proc_name = "powertec", |
diff --git a/drivers/scsi/fcoe/fc_transport_fcoe.c b/drivers/scsi/fcoe/fc_transport_fcoe.c index bf7fe6fc0820..8862758006c0 100644 --- a/drivers/scsi/fcoe/fc_transport_fcoe.c +++ b/drivers/scsi/fcoe/fc_transport_fcoe.c | |||
| @@ -33,19 +33,19 @@ static LIST_HEAD(fcoe_transports); | |||
| 33 | static DEFINE_MUTEX(fcoe_transports_lock); | 33 | static DEFINE_MUTEX(fcoe_transports_lock); |
| 34 | 34 | ||
| 35 | /** | 35 | /** |
| 36 | * fcoe_transport_default - returns ptr to the default transport fcoe_sw | 36 | * fcoe_transport_default() - Returns ptr to the default transport fcoe_sw |
| 37 | **/ | 37 | */ |
| 38 | struct fcoe_transport *fcoe_transport_default(void) | 38 | struct fcoe_transport *fcoe_transport_default(void) |
| 39 | { | 39 | { |
| 40 | return &fcoe_sw_transport; | 40 | return &fcoe_sw_transport; |
| 41 | } | 41 | } |
| 42 | 42 | ||
| 43 | /** | 43 | /** |
| 44 | * fcoe_transport_to_pcidev - get the pci dev from a netdev | 44 | * fcoe_transport_to_pcidev() - get the pci dev from a netdev |
| 45 | * @netdev: the netdev that pci dev will be retrived from | 45 | * @netdev: the netdev that pci dev will be retrived from |
| 46 | * | 46 | * |
| 47 | * Returns: NULL or the corrsponding pci_dev | 47 | * Returns: NULL or the corrsponding pci_dev |
| 48 | **/ | 48 | */ |
| 49 | struct pci_dev *fcoe_transport_pcidev(const struct net_device *netdev) | 49 | struct pci_dev *fcoe_transport_pcidev(const struct net_device *netdev) |
| 50 | { | 50 | { |
| 51 | if (!netdev->dev.parent) | 51 | if (!netdev->dev.parent) |
| @@ -54,18 +54,17 @@ struct pci_dev *fcoe_transport_pcidev(const struct net_device *netdev) | |||
| 54 | } | 54 | } |
| 55 | 55 | ||
| 56 | /** | 56 | /** |
| 57 | * fcoe_transport_device_lookup - find out netdev is managed by the | 57 | * fcoe_transport_device_lookup() - Lookup a transport |
| 58 | * transport | ||
| 59 | * assign a transport to a device | ||
| 60 | * @netdev: the netdev the transport to be attached to | 58 | * @netdev: the netdev the transport to be attached to |
| 61 | * | 59 | * |
| 62 | * This will look for existing offload driver, if not found, it falls back to | 60 | * This will look for existing offload driver, if not found, it falls back to |
| 63 | * the default sw hba (fcoe_sw) as its fcoe transport. | 61 | * the default sw hba (fcoe_sw) as its fcoe transport. |
| 64 | * | 62 | * |
| 65 | * Returns: 0 for success | 63 | * Returns: 0 for success |
| 66 | **/ | 64 | */ |
| 67 | static struct fcoe_transport_internal *fcoe_transport_device_lookup( | 65 | static struct fcoe_transport_internal * |
| 68 | struct fcoe_transport *t, struct net_device *netdev) | 66 | fcoe_transport_device_lookup(struct fcoe_transport *t, |
| 67 | struct net_device *netdev) | ||
| 69 | { | 68 | { |
| 70 | struct fcoe_transport_internal *ti; | 69 | struct fcoe_transport_internal *ti; |
| 71 | 70 | ||
| @@ -81,14 +80,14 @@ static struct fcoe_transport_internal *fcoe_transport_device_lookup( | |||
| 81 | return NULL; | 80 | return NULL; |
| 82 | } | 81 | } |
| 83 | /** | 82 | /** |
| 84 | * fcoe_transport_device_add - assign a transport to a device | 83 | * fcoe_transport_device_add() - Assign a transport to a device |
| 85 | * @netdev: the netdev the transport to be attached to | 84 | * @netdev: the netdev the transport to be attached to |
| 86 | * | 85 | * |
| 87 | * This will look for existing offload driver, if not found, it falls back to | 86 | * This will look for existing offload driver, if not found, it falls back to |
| 88 | * the default sw hba (fcoe_sw) as its fcoe transport. | 87 | * the default sw hba (fcoe_sw) as its fcoe transport. |
| 89 | * | 88 | * |
| 90 | * Returns: 0 for success | 89 | * Returns: 0 for success |
| 91 | **/ | 90 | */ |
| 92 | static int fcoe_transport_device_add(struct fcoe_transport *t, | 91 | static int fcoe_transport_device_add(struct fcoe_transport *t, |
| 93 | struct net_device *netdev) | 92 | struct net_device *netdev) |
| 94 | { | 93 | { |
| @@ -123,14 +122,14 @@ static int fcoe_transport_device_add(struct fcoe_transport *t, | |||
| 123 | } | 122 | } |
| 124 | 123 | ||
| 125 | /** | 124 | /** |
| 126 | * fcoe_transport_device_remove - remove a device from its transport | 125 | * fcoe_transport_device_remove() - Remove a device from its transport |
| 127 | * @netdev: the netdev the transport to be attached to | 126 | * @netdev: the netdev the transport to be attached to |
| 128 | * | 127 | * |
| 129 | * this removes the device from the transport so the given transport will | 128 | * This removes the device from the transport so the given transport will |
| 130 | * not manage this device any more | 129 | * not manage this device any more |
| 131 | * | 130 | * |
| 132 | * Returns: 0 for success | 131 | * Returns: 0 for success |
| 133 | **/ | 132 | */ |
| 134 | static int fcoe_transport_device_remove(struct fcoe_transport *t, | 133 | static int fcoe_transport_device_remove(struct fcoe_transport *t, |
| 135 | struct net_device *netdev) | 134 | struct net_device *netdev) |
| 136 | { | 135 | { |
| @@ -155,13 +154,13 @@ static int fcoe_transport_device_remove(struct fcoe_transport *t, | |||
| 155 | } | 154 | } |
| 156 | 155 | ||
| 157 | /** | 156 | /** |
| 158 | * fcoe_transport_device_remove_all - remove all from transport devlist | 157 | * fcoe_transport_device_remove_all() - Remove all from transport devlist |
| 159 | * | 158 | * |
| 160 | * this removes the device from the transport so the given transport will | 159 | * This removes the device from the transport so the given transport will |
| 161 | * not manage this device any more | 160 | * not manage this device any more |
| 162 | * | 161 | * |
| 163 | * Returns: 0 for success | 162 | * Returns: 0 for success |
| 164 | **/ | 163 | */ |
| 165 | static void fcoe_transport_device_remove_all(struct fcoe_transport *t) | 164 | static void fcoe_transport_device_remove_all(struct fcoe_transport *t) |
| 166 | { | 165 | { |
| 167 | struct fcoe_transport_internal *ti, *tmp; | 166 | struct fcoe_transport_internal *ti, *tmp; |
| @@ -175,18 +174,18 @@ static void fcoe_transport_device_remove_all(struct fcoe_transport *t) | |||
| 175 | } | 174 | } |
| 176 | 175 | ||
| 177 | /** | 176 | /** |
| 178 | * fcoe_transport_match - use the bus device match function to match the hw | 177 | * fcoe_transport_match() - Use the bus device match function to match the hw |
| 179 | * @t: the fcoe transport | 178 | * @t: The fcoe transport to check |
| 180 | * @netdev: | 179 | * @netdev: The netdev to match against |
| 181 | * | 180 | * |
| 182 | * This function is used to check if the givne transport wants to manage the | 181 | * This function is used to check if the given transport wants to manage the |
| 183 | * input netdev. if the transports implements the match function, it will be | 182 | * input netdev. if the transports implements the match function, it will be |
| 184 | * called, o.w. we just compare the pci vendor and device id. | 183 | * called, o.w. we just compare the pci vendor and device id. |
| 185 | * | 184 | * |
| 186 | * Returns: true for match up | 185 | * Returns: true for match up |
| 187 | **/ | 186 | */ |
| 188 | static bool fcoe_transport_match(struct fcoe_transport *t, | 187 | static bool fcoe_transport_match(struct fcoe_transport *t, |
| 189 | struct net_device *netdev) | 188 | struct net_device *netdev) |
| 190 | { | 189 | { |
| 191 | /* match transport by vendor and device id */ | 190 | /* match transport by vendor and device id */ |
| 192 | struct pci_dev *pci; | 191 | struct pci_dev *pci; |
| @@ -210,17 +209,17 @@ static bool fcoe_transport_match(struct fcoe_transport *t, | |||
| 210 | } | 209 | } |
| 211 | 210 | ||
| 212 | /** | 211 | /** |
| 213 | * fcoe_transport_lookup - check if the transport is already registered | 212 | * fcoe_transport_lookup() - Check if the transport is already registered |
| 214 | * @t: the transport to be looked up | 213 | * @t: the transport to be looked up |
| 215 | * | 214 | * |
| 216 | * This compares the parent device (pci) vendor and device id | 215 | * This compares the parent device (pci) vendor and device id |
| 217 | * | 216 | * |
| 218 | * Returns: NULL if not found | 217 | * Returns: NULL if not found |
| 219 | * | 218 | * |
| 220 | * TODO - return default sw transport if no other transport is found | 219 | * TODO: return default sw transport if no other transport is found |
| 221 | **/ | 220 | */ |
| 222 | static struct fcoe_transport *fcoe_transport_lookup( | 221 | static struct fcoe_transport * |
| 223 | struct net_device *netdev) | 222 | fcoe_transport_lookup(struct net_device *netdev) |
| 224 | { | 223 | { |
| 225 | struct fcoe_transport *t; | 224 | struct fcoe_transport *t; |
| 226 | 225 | ||
| @@ -239,11 +238,11 @@ static struct fcoe_transport *fcoe_transport_lookup( | |||
| 239 | } | 238 | } |
| 240 | 239 | ||
| 241 | /** | 240 | /** |
| 242 | * fcoe_transport_register - adds a fcoe transport to the fcoe transports list | 241 | * fcoe_transport_register() - Adds a fcoe transport to the fcoe transports list |
| 243 | * @t: ptr to the fcoe transport to be added | 242 | * @t: ptr to the fcoe transport to be added |
| 244 | * | 243 | * |
| 245 | * Returns: 0 for success | 244 | * Returns: 0 for success |
| 246 | **/ | 245 | */ |
| 247 | int fcoe_transport_register(struct fcoe_transport *t) | 246 | int fcoe_transport_register(struct fcoe_transport *t) |
| 248 | { | 247 | { |
| 249 | struct fcoe_transport *tt; | 248 | struct fcoe_transport *tt; |
| @@ -259,9 +258,6 @@ int fcoe_transport_register(struct fcoe_transport *t) | |||
| 259 | list_add_tail(&t->list, &fcoe_transports); | 258 | list_add_tail(&t->list, &fcoe_transports); |
| 260 | mutex_unlock(&fcoe_transports_lock); | 259 | mutex_unlock(&fcoe_transports_lock); |
| 261 | 260 | ||
| 262 | mutex_init(&t->devlock); | ||
| 263 | INIT_LIST_HEAD(&t->devlist); | ||
| 264 | |||
| 265 | printk(KERN_DEBUG "fcoe_transport_register:%s\n", t->name); | 261 | printk(KERN_DEBUG "fcoe_transport_register:%s\n", t->name); |
| 266 | 262 | ||
| 267 | return 0; | 263 | return 0; |
| @@ -269,11 +265,11 @@ int fcoe_transport_register(struct fcoe_transport *t) | |||
| 269 | EXPORT_SYMBOL_GPL(fcoe_transport_register); | 265 | EXPORT_SYMBOL_GPL(fcoe_transport_register); |
| 270 | 266 | ||
| 271 | /** | 267 | /** |
| 272 | * fcoe_transport_unregister - remove the tranport fro the fcoe transports list | 268 | * fcoe_transport_unregister() - Remove the tranport fro the fcoe transports list |
| 273 | * @t: ptr to the fcoe transport to be removed | 269 | * @t: ptr to the fcoe transport to be removed |
| 274 | * | 270 | * |
| 275 | * Returns: 0 for success | 271 | * Returns: 0 for success |
| 276 | **/ | 272 | */ |
| 277 | int fcoe_transport_unregister(struct fcoe_transport *t) | 273 | int fcoe_transport_unregister(struct fcoe_transport *t) |
| 278 | { | 274 | { |
| 279 | struct fcoe_transport *tt, *tmp; | 275 | struct fcoe_transport *tt, *tmp; |
| @@ -294,8 +290,8 @@ int fcoe_transport_unregister(struct fcoe_transport *t) | |||
| 294 | } | 290 | } |
| 295 | EXPORT_SYMBOL_GPL(fcoe_transport_unregister); | 291 | EXPORT_SYMBOL_GPL(fcoe_transport_unregister); |
| 296 | 292 | ||
| 297 | /* | 293 | /** |
| 298 | * fcoe_load_transport_driver - load an offload driver by alias name | 294 | * fcoe_load_transport_driver() - Load an offload driver by alias name |
| 299 | * @netdev: the target net device | 295 | * @netdev: the target net device |
| 300 | * | 296 | * |
| 301 | * Requests for an offload driver module as the fcoe transport, if fails, it | 297 | * Requests for an offload driver module as the fcoe transport, if fails, it |
| @@ -307,7 +303,7 @@ EXPORT_SYMBOL_GPL(fcoe_transport_unregister); | |||
| 307 | * 3. pure hw fcoe hba may not have netdev | 303 | * 3. pure hw fcoe hba may not have netdev |
| 308 | * | 304 | * |
| 309 | * Returns: 0 for success | 305 | * Returns: 0 for success |
| 310 | **/ | 306 | */ |
| 311 | int fcoe_load_transport_driver(struct net_device *netdev) | 307 | int fcoe_load_transport_driver(struct net_device *netdev) |
| 312 | { | 308 | { |
| 313 | struct pci_dev *pci; | 309 | struct pci_dev *pci; |
| @@ -335,14 +331,14 @@ int fcoe_load_transport_driver(struct net_device *netdev) | |||
| 335 | EXPORT_SYMBOL_GPL(fcoe_load_transport_driver); | 331 | EXPORT_SYMBOL_GPL(fcoe_load_transport_driver); |
| 336 | 332 | ||
| 337 | /** | 333 | /** |
| 338 | * fcoe_transport_attach - load transport to fcoe | 334 | * fcoe_transport_attach() - Load transport to fcoe |
| 339 | * @netdev: the netdev the transport to be attached to | 335 | * @netdev: the netdev the transport to be attached to |
| 340 | * | 336 | * |
| 341 | * This will look for existing offload driver, if not found, it falls back to | 337 | * This will look for existing offload driver, if not found, it falls back to |
| 342 | * the default sw hba (fcoe_sw) as its fcoe transport. | 338 | * the default sw hba (fcoe_sw) as its fcoe transport. |
| 343 | * | 339 | * |
| 344 | * Returns: 0 for success | 340 | * Returns: 0 for success |
| 345 | **/ | 341 | */ |
| 346 | int fcoe_transport_attach(struct net_device *netdev) | 342 | int fcoe_transport_attach(struct net_device *netdev) |
| 347 | { | 343 | { |
| 348 | struct fcoe_transport *t; | 344 | struct fcoe_transport *t; |
| @@ -373,11 +369,11 @@ int fcoe_transport_attach(struct net_device *netdev) | |||
| 373 | EXPORT_SYMBOL_GPL(fcoe_transport_attach); | 369 | EXPORT_SYMBOL_GPL(fcoe_transport_attach); |
| 374 | 370 | ||
| 375 | /** | 371 | /** |
| 376 | * fcoe_transport_release - unload transport from fcoe | 372 | * fcoe_transport_release() - Unload transport from fcoe |
| 377 | * @netdev: the net device on which fcoe is to be released | 373 | * @netdev: the net device on which fcoe is to be released |
| 378 | * | 374 | * |
| 379 | * Returns: 0 for success | 375 | * Returns: 0 for success |
| 380 | **/ | 376 | */ |
| 381 | int fcoe_transport_release(struct net_device *netdev) | 377 | int fcoe_transport_release(struct net_device *netdev) |
| 382 | { | 378 | { |
| 383 | struct fcoe_transport *t; | 379 | struct fcoe_transport *t; |
| @@ -410,12 +406,12 @@ int fcoe_transport_release(struct net_device *netdev) | |||
| 410 | EXPORT_SYMBOL_GPL(fcoe_transport_release); | 406 | EXPORT_SYMBOL_GPL(fcoe_transport_release); |
| 411 | 407 | ||
| 412 | /** | 408 | /** |
| 413 | * fcoe_transport_init - initializes fcoe transport layer | 409 | * fcoe_transport_init() - Initializes fcoe transport layer |
| 414 | * | 410 | * |
| 415 | * This prepares for the fcoe transport layer | 411 | * This prepares for the fcoe transport layer |
| 416 | * | 412 | * |
| 417 | * Returns: none | 413 | * Returns: none |
| 418 | **/ | 414 | */ |
| 419 | int __init fcoe_transport_init(void) | 415 | int __init fcoe_transport_init(void) |
| 420 | { | 416 | { |
| 421 | INIT_LIST_HEAD(&fcoe_transports); | 417 | INIT_LIST_HEAD(&fcoe_transports); |
| @@ -424,12 +420,13 @@ int __init fcoe_transport_init(void) | |||
| 424 | } | 420 | } |
| 425 | 421 | ||
| 426 | /** | 422 | /** |
| 427 | * fcoe_transport_exit - cleans up the fcoe transport layer | 423 | * fcoe_transport_exit() - Cleans up the fcoe transport layer |
| 424 | * | ||
| 428 | * This cleans up the fcoe transport layer. removing any transport on the list, | 425 | * This cleans up the fcoe transport layer. removing any transport on the list, |
| 429 | * note that the transport destroy func is not called here. | 426 | * note that the transport destroy func is not called here. |
| 430 | * | 427 | * |
| 431 | * Returns: none | 428 | * Returns: none |
| 432 | **/ | 429 | */ |
| 433 | int __exit fcoe_transport_exit(void) | 430 | int __exit fcoe_transport_exit(void) |
| 434 | { | 431 | { |
| 435 | struct fcoe_transport *t, *tmp; | 432 | struct fcoe_transport *t, *tmp; |
diff --git a/drivers/scsi/fcoe/fcoe_sw.c b/drivers/scsi/fcoe/fcoe_sw.c index dc4cd5e25760..da210eba1941 100644 --- a/drivers/scsi/fcoe/fcoe_sw.c +++ b/drivers/scsi/fcoe/fcoe_sw.c | |||
| @@ -104,19 +104,19 @@ static struct scsi_host_template fcoe_sw_shost_template = { | |||
| 104 | .max_sectors = 0xffff, | 104 | .max_sectors = 0xffff, |
| 105 | }; | 105 | }; |
| 106 | 106 | ||
| 107 | /* | 107 | /** |
| 108 | * fcoe_sw_lport_config - sets up the fc_lport | 108 | * fcoe_sw_lport_config() - sets up the fc_lport |
| 109 | * @lp: ptr to the fc_lport | 109 | * @lp: ptr to the fc_lport |
| 110 | * @shost: ptr to the parent scsi host | 110 | * @shost: ptr to the parent scsi host |
| 111 | * | 111 | * |
| 112 | * Returns: 0 for success | 112 | * Returns: 0 for success |
| 113 | * | ||
| 114 | */ | 113 | */ |
| 115 | static int fcoe_sw_lport_config(struct fc_lport *lp) | 114 | static int fcoe_sw_lport_config(struct fc_lport *lp) |
| 116 | { | 115 | { |
| 117 | int i = 0; | 116 | int i = 0; |
| 118 | 117 | ||
| 119 | lp->link_status = 0; | 118 | lp->link_up = 0; |
| 119 | lp->qfull = 0; | ||
| 120 | lp->max_retry_count = 3; | 120 | lp->max_retry_count = 3; |
| 121 | lp->e_d_tov = 2 * 1000; /* FC-FS default */ | 121 | lp->e_d_tov = 2 * 1000; /* FC-FS default */ |
| 122 | lp->r_a_tov = 2 * 2 * 1000; | 122 | lp->r_a_tov = 2 * 2 * 1000; |
| @@ -136,16 +136,14 @@ static int fcoe_sw_lport_config(struct fc_lport *lp) | |||
| 136 | return 0; | 136 | return 0; |
| 137 | } | 137 | } |
| 138 | 138 | ||
| 139 | /* | 139 | /** |
| 140 | * fcoe_sw_netdev_config - sets up fcoe_softc for lport and network | 140 | * fcoe_sw_netdev_config() - Set up netdev for SW FCoE |
| 141 | * related properties | ||
| 142 | * @lp : ptr to the fc_lport | 141 | * @lp : ptr to the fc_lport |
| 143 | * @netdev : ptr to the associated netdevice struct | 142 | * @netdev : ptr to the associated netdevice struct |
| 144 | * | 143 | * |
| 145 | * Must be called after fcoe_sw_lport_config() as it will use lport mutex | 144 | * Must be called after fcoe_sw_lport_config() as it will use lport mutex |
| 146 | * | 145 | * |
| 147 | * Returns : 0 for success | 146 | * Returns : 0 for success |
| 148 | * | ||
| 149 | */ | 147 | */ |
| 150 | static int fcoe_sw_netdev_config(struct fc_lport *lp, struct net_device *netdev) | 148 | static int fcoe_sw_netdev_config(struct fc_lport *lp, struct net_device *netdev) |
| 151 | { | 149 | { |
| @@ -181,9 +179,8 @@ static int fcoe_sw_netdev_config(struct fc_lport *lp, struct net_device *netdev) | |||
| 181 | if (fc_set_mfs(lp, mfs)) | 179 | if (fc_set_mfs(lp, mfs)) |
| 182 | return -EINVAL; | 180 | return -EINVAL; |
| 183 | 181 | ||
| 184 | lp->link_status = ~FC_PAUSE & ~FC_LINK_UP; | ||
| 185 | if (!fcoe_link_ok(lp)) | 182 | if (!fcoe_link_ok(lp)) |
| 186 | lp->link_status |= FC_LINK_UP; | 183 | lp->link_up = 1; |
| 187 | 184 | ||
| 188 | /* offload features support */ | 185 | /* offload features support */ |
| 189 | if (fc->real_dev->features & NETIF_F_SG) | 186 | if (fc->real_dev->features & NETIF_F_SG) |
| @@ -191,6 +188,7 @@ static int fcoe_sw_netdev_config(struct fc_lport *lp, struct net_device *netdev) | |||
| 191 | 188 | ||
| 192 | 189 | ||
| 193 | skb_queue_head_init(&fc->fcoe_pending_queue); | 190 | skb_queue_head_init(&fc->fcoe_pending_queue); |
| 191 | fc->fcoe_pending_queue_active = 0; | ||
| 194 | 192 | ||
| 195 | /* setup Source Mac Address */ | 193 | /* setup Source Mac Address */ |
| 196 | memcpy(fc->ctl_src_addr, fc->real_dev->dev_addr, | 194 | memcpy(fc->ctl_src_addr, fc->real_dev->dev_addr, |
| @@ -224,16 +222,15 @@ static int fcoe_sw_netdev_config(struct fc_lport *lp, struct net_device *netdev) | |||
| 224 | return 0; | 222 | return 0; |
| 225 | } | 223 | } |
| 226 | 224 | ||
| 227 | /* | 225 | /** |
| 228 | * fcoe_sw_shost_config - sets up fc_lport->host | 226 | * fcoe_sw_shost_config() - Sets up fc_lport->host |
| 229 | * @lp : ptr to the fc_lport | 227 | * @lp : ptr to the fc_lport |
| 230 | * @shost : ptr to the associated scsi host | 228 | * @shost : ptr to the associated scsi host |
| 231 | * @dev : device associated to scsi host | 229 | * @dev : device associated to scsi host |
| 232 | * | 230 | * |
| 233 | * Must be called after fcoe_sw_lport_config) and fcoe_sw_netdev_config() | 231 | * Must be called after fcoe_sw_lport_config() and fcoe_sw_netdev_config() |
| 234 | * | 232 | * |
| 235 | * Returns : 0 for success | 233 | * Returns : 0 for success |
| 236 | * | ||
| 237 | */ | 234 | */ |
| 238 | static int fcoe_sw_shost_config(struct fc_lport *lp, struct Scsi_Host *shost, | 235 | static int fcoe_sw_shost_config(struct fc_lport *lp, struct Scsi_Host *shost, |
| 239 | struct device *dev) | 236 | struct device *dev) |
| @@ -261,8 +258,8 @@ static int fcoe_sw_shost_config(struct fc_lport *lp, struct Scsi_Host *shost, | |||
| 261 | return 0; | 258 | return 0; |
| 262 | } | 259 | } |
| 263 | 260 | ||
| 264 | /* | 261 | /** |
| 265 | * fcoe_sw_em_config - allocates em for this lport | 262 | * fcoe_sw_em_config() - allocates em for this lport |
| 266 | * @lp: the port that em is to allocated for | 263 | * @lp: the port that em is to allocated for |
| 267 | * | 264 | * |
| 268 | * Returns : 0 on success | 265 | * Returns : 0 on success |
| @@ -279,8 +276,8 @@ static inline int fcoe_sw_em_config(struct fc_lport *lp) | |||
| 279 | return 0; | 276 | return 0; |
| 280 | } | 277 | } |
| 281 | 278 | ||
| 282 | /* | 279 | /** |
| 283 | * fcoe_sw_destroy - FCoE software HBA tear-down function | 280 | * fcoe_sw_destroy() - FCoE software HBA tear-down function |
| 284 | * @netdev: ptr to the associated net_device | 281 | * @netdev: ptr to the associated net_device |
| 285 | * | 282 | * |
| 286 | * Returns: 0 if link is OK for use by FCoE. | 283 | * Returns: 0 if link is OK for use by FCoE. |
| @@ -301,7 +298,7 @@ static int fcoe_sw_destroy(struct net_device *netdev) | |||
| 301 | if (!lp) | 298 | if (!lp) |
| 302 | return -ENODEV; | 299 | return -ENODEV; |
| 303 | 300 | ||
| 304 | fc = fcoe_softc(lp); | 301 | fc = lport_priv(lp); |
| 305 | 302 | ||
| 306 | /* Logout of the fabric */ | 303 | /* Logout of the fabric */ |
| 307 | fc_fabric_logoff(lp); | 304 | fc_fabric_logoff(lp); |
| @@ -353,8 +350,8 @@ static struct libfc_function_template fcoe_sw_libfc_fcn_templ = { | |||
| 353 | .frame_send = fcoe_xmit, | 350 | .frame_send = fcoe_xmit, |
| 354 | }; | 351 | }; |
| 355 | 352 | ||
| 356 | /* | 353 | /** |
| 357 | * fcoe_sw_create - this function creates the fcoe interface | 354 | * fcoe_sw_create() - this function creates the fcoe interface |
| 358 | * @netdev: pointer the associated netdevice | 355 | * @netdev: pointer the associated netdevice |
| 359 | * | 356 | * |
| 360 | * Creates fc_lport struct and scsi_host for lport, configures lport | 357 | * Creates fc_lport struct and scsi_host for lport, configures lport |
| @@ -440,8 +437,8 @@ out_host_put: | |||
| 440 | return rc; | 437 | return rc; |
| 441 | } | 438 | } |
| 442 | 439 | ||
| 443 | /* | 440 | /** |
| 444 | * fcoe_sw_match - the fcoe sw transport match function | 441 | * fcoe_sw_match() - The FCoE SW transport match function |
| 445 | * | 442 | * |
| 446 | * Returns : false always | 443 | * Returns : false always |
| 447 | */ | 444 | */ |
| @@ -461,8 +458,8 @@ struct fcoe_transport fcoe_sw_transport = { | |||
| 461 | .device = 0xffff, | 458 | .device = 0xffff, |
| 462 | }; | 459 | }; |
| 463 | 460 | ||
| 464 | /* | 461 | /** |
| 465 | * fcoe_sw_init - registers fcoe_sw_transport | 462 | * fcoe_sw_init() - Registers fcoe_sw_transport |
| 466 | * | 463 | * |
| 467 | * Returns : 0 on success | 464 | * Returns : 0 on success |
| 468 | */ | 465 | */ |
| @@ -471,17 +468,22 @@ int __init fcoe_sw_init(void) | |||
| 471 | /* attach to scsi transport */ | 468 | /* attach to scsi transport */ |
| 472 | scsi_transport_fcoe_sw = | 469 | scsi_transport_fcoe_sw = |
| 473 | fc_attach_transport(&fcoe_sw_transport_function); | 470 | fc_attach_transport(&fcoe_sw_transport_function); |
| 471 | |||
| 474 | if (!scsi_transport_fcoe_sw) { | 472 | if (!scsi_transport_fcoe_sw) { |
| 475 | printk(KERN_ERR "fcoe_sw_init:fc_attach_transport() failed\n"); | 473 | printk(KERN_ERR "fcoe_sw_init:fc_attach_transport() failed\n"); |
| 476 | return -ENODEV; | 474 | return -ENODEV; |
| 477 | } | 475 | } |
| 476 | |||
| 477 | mutex_init(&fcoe_sw_transport.devlock); | ||
| 478 | INIT_LIST_HEAD(&fcoe_sw_transport.devlist); | ||
| 479 | |||
| 478 | /* register sw transport */ | 480 | /* register sw transport */ |
| 479 | fcoe_transport_register(&fcoe_sw_transport); | 481 | fcoe_transport_register(&fcoe_sw_transport); |
| 480 | return 0; | 482 | return 0; |
| 481 | } | 483 | } |
| 482 | 484 | ||
| 483 | /* | 485 | /** |
| 484 | * fcoe_sw_exit - unregisters fcoe_sw_transport | 486 | * fcoe_sw_exit() - Unregisters fcoe_sw_transport |
| 485 | * | 487 | * |
| 486 | * Returns : 0 on success | 488 | * Returns : 0 on success |
| 487 | */ | 489 | */ |
diff --git a/drivers/scsi/fcoe/libfcoe.c b/drivers/scsi/fcoe/libfcoe.c index e419f486cdb3..5548bf3bb58b 100644 --- a/drivers/scsi/fcoe/libfcoe.c +++ b/drivers/scsi/fcoe/libfcoe.c | |||
| @@ -49,6 +49,7 @@ | |||
| 49 | static int debug_fcoe; | 49 | static int debug_fcoe; |
| 50 | 50 | ||
| 51 | #define FCOE_MAX_QUEUE_DEPTH 256 | 51 | #define FCOE_MAX_QUEUE_DEPTH 256 |
| 52 | #define FCOE_LOW_QUEUE_DEPTH 32 | ||
| 52 | 53 | ||
| 53 | /* destination address mode */ | 54 | /* destination address mode */ |
| 54 | #define FCOE_GW_ADDR_MODE 0x00 | 55 | #define FCOE_GW_ADDR_MODE 0x00 |
| @@ -69,8 +70,6 @@ struct fcoe_percpu_s *fcoe_percpu[NR_CPUS]; | |||
| 69 | 70 | ||
| 70 | /* Function Prototyes */ | 71 | /* Function Prototyes */ |
| 71 | static int fcoe_check_wait_queue(struct fc_lport *); | 72 | static int fcoe_check_wait_queue(struct fc_lport *); |
| 72 | static void fcoe_insert_wait_queue_head(struct fc_lport *, struct sk_buff *); | ||
| 73 | static void fcoe_insert_wait_queue(struct fc_lport *, struct sk_buff *); | ||
| 74 | static void fcoe_recv_flogi(struct fcoe_softc *, struct fc_frame *, u8 *); | 73 | static void fcoe_recv_flogi(struct fcoe_softc *, struct fc_frame *, u8 *); |
| 75 | #ifdef CONFIG_HOTPLUG_CPU | 74 | #ifdef CONFIG_HOTPLUG_CPU |
| 76 | static int fcoe_cpu_callback(struct notifier_block *, ulong, void *); | 75 | static int fcoe_cpu_callback(struct notifier_block *, ulong, void *); |
| @@ -91,13 +90,13 @@ static struct notifier_block fcoe_cpu_notifier = { | |||
| 91 | }; | 90 | }; |
| 92 | 91 | ||
| 93 | /** | 92 | /** |
| 94 | * fcoe_create_percpu_data - creates the associated cpu data | 93 | * fcoe_create_percpu_data() - creates the associated cpu data |
| 95 | * @cpu: index for the cpu where fcoe cpu data will be created | 94 | * @cpu: index for the cpu where fcoe cpu data will be created |
| 96 | * | 95 | * |
| 97 | * create percpu stats block, from cpu add notifier | 96 | * create percpu stats block, from cpu add notifier |
| 98 | * | 97 | * |
| 99 | * Returns: none | 98 | * Returns: none |
| 100 | **/ | 99 | */ |
| 101 | static void fcoe_create_percpu_data(int cpu) | 100 | static void fcoe_create_percpu_data(int cpu) |
| 102 | { | 101 | { |
| 103 | struct fc_lport *lp; | 102 | struct fc_lport *lp; |
| @@ -115,13 +114,13 @@ static void fcoe_create_percpu_data(int cpu) | |||
| 115 | } | 114 | } |
| 116 | 115 | ||
| 117 | /** | 116 | /** |
| 118 | * fcoe_destroy_percpu_data - destroys the associated cpu data | 117 | * fcoe_destroy_percpu_data() - destroys the associated cpu data |
| 119 | * @cpu: index for the cpu where fcoe cpu data will destroyed | 118 | * @cpu: index for the cpu where fcoe cpu data will destroyed |
| 120 | * | 119 | * |
| 121 | * destroy percpu stats block called by cpu add/remove notifier | 120 | * destroy percpu stats block called by cpu add/remove notifier |
| 122 | * | 121 | * |
| 123 | * Retuns: none | 122 | * Retuns: none |
| 124 | **/ | 123 | */ |
| 125 | static void fcoe_destroy_percpu_data(int cpu) | 124 | static void fcoe_destroy_percpu_data(int cpu) |
| 126 | { | 125 | { |
| 127 | struct fc_lport *lp; | 126 | struct fc_lport *lp; |
| @@ -137,7 +136,7 @@ static void fcoe_destroy_percpu_data(int cpu) | |||
| 137 | } | 136 | } |
| 138 | 137 | ||
| 139 | /** | 138 | /** |
| 140 | * fcoe_cpu_callback - fcoe cpu hotplug event callback | 139 | * fcoe_cpu_callback() - fcoe cpu hotplug event callback |
| 141 | * @nfb: callback data block | 140 | * @nfb: callback data block |
| 142 | * @action: event triggering the callback | 141 | * @action: event triggering the callback |
| 143 | * @hcpu: index for the cpu of this event | 142 | * @hcpu: index for the cpu of this event |
| @@ -145,7 +144,7 @@ static void fcoe_destroy_percpu_data(int cpu) | |||
| 145 | * this creates or destroys per cpu data for fcoe | 144 | * this creates or destroys per cpu data for fcoe |
| 146 | * | 145 | * |
| 147 | * Returns NOTIFY_OK always. | 146 | * Returns NOTIFY_OK always. |
| 148 | **/ | 147 | */ |
| 149 | static int fcoe_cpu_callback(struct notifier_block *nfb, unsigned long action, | 148 | static int fcoe_cpu_callback(struct notifier_block *nfb, unsigned long action, |
| 150 | void *hcpu) | 149 | void *hcpu) |
| 151 | { | 150 | { |
| @@ -166,7 +165,7 @@ static int fcoe_cpu_callback(struct notifier_block *nfb, unsigned long action, | |||
| 166 | #endif /* CONFIG_HOTPLUG_CPU */ | 165 | #endif /* CONFIG_HOTPLUG_CPU */ |
| 167 | 166 | ||
| 168 | /** | 167 | /** |
| 169 | * fcoe_rcv - this is the fcoe receive function called by NET_RX_SOFTIRQ | 168 | * fcoe_rcv() - this is the fcoe receive function called by NET_RX_SOFTIRQ |
| 170 | * @skb: the receive skb | 169 | * @skb: the receive skb |
| 171 | * @dev: associated net device | 170 | * @dev: associated net device |
| 172 | * @ptype: context | 171 | * @ptype: context |
| @@ -175,7 +174,7 @@ static int fcoe_cpu_callback(struct notifier_block *nfb, unsigned long action, | |||
| 175 | * this function will receive the packet and build fc frame and pass it up | 174 | * this function will receive the packet and build fc frame and pass it up |
| 176 | * | 175 | * |
| 177 | * Returns: 0 for success | 176 | * Returns: 0 for success |
| 178 | **/ | 177 | */ |
| 179 | int fcoe_rcv(struct sk_buff *skb, struct net_device *dev, | 178 | int fcoe_rcv(struct sk_buff *skb, struct net_device *dev, |
| 180 | struct packet_type *ptype, struct net_device *olddev) | 179 | struct packet_type *ptype, struct net_device *olddev) |
| 181 | { | 180 | { |
| @@ -265,11 +264,11 @@ err2: | |||
| 265 | EXPORT_SYMBOL_GPL(fcoe_rcv); | 264 | EXPORT_SYMBOL_GPL(fcoe_rcv); |
| 266 | 265 | ||
| 267 | /** | 266 | /** |
| 268 | * fcoe_start_io - pass to netdev to start xmit for fcoe | 267 | * fcoe_start_io() - pass to netdev to start xmit for fcoe |
| 269 | * @skb: the skb to be xmitted | 268 | * @skb: the skb to be xmitted |
| 270 | * | 269 | * |
| 271 | * Returns: 0 for success | 270 | * Returns: 0 for success |
| 272 | **/ | 271 | */ |
| 273 | static inline int fcoe_start_io(struct sk_buff *skb) | 272 | static inline int fcoe_start_io(struct sk_buff *skb) |
| 274 | { | 273 | { |
| 275 | int rc; | 274 | int rc; |
| @@ -283,12 +282,12 @@ static inline int fcoe_start_io(struct sk_buff *skb) | |||
| 283 | } | 282 | } |
| 284 | 283 | ||
| 285 | /** | 284 | /** |
| 286 | * fcoe_get_paged_crc_eof - in case we need alloc a page for crc_eof | 285 | * fcoe_get_paged_crc_eof() - in case we need alloc a page for crc_eof |
| 287 | * @skb: the skb to be xmitted | 286 | * @skb: the skb to be xmitted |
| 288 | * @tlen: total len | 287 | * @tlen: total len |
| 289 | * | 288 | * |
| 290 | * Returns: 0 for success | 289 | * Returns: 0 for success |
| 291 | **/ | 290 | */ |
| 292 | static int fcoe_get_paged_crc_eof(struct sk_buff *skb, int tlen) | 291 | static int fcoe_get_paged_crc_eof(struct sk_buff *skb, int tlen) |
| 293 | { | 292 | { |
| 294 | struct fcoe_percpu_s *fps; | 293 | struct fcoe_percpu_s *fps; |
| @@ -326,13 +325,12 @@ static int fcoe_get_paged_crc_eof(struct sk_buff *skb, int tlen) | |||
| 326 | } | 325 | } |
| 327 | 326 | ||
| 328 | /** | 327 | /** |
| 329 | * fcoe_fc_crc - calculates FC CRC in this fcoe skb | 328 | * fcoe_fc_crc() - calculates FC CRC in this fcoe skb |
| 330 | * @fp: the fc_frame containg data to be checksummed | 329 | * @fp: the fc_frame containg data to be checksummed |
| 331 | * | 330 | * |
| 332 | * This uses crc32() to calculate the crc for fc frame | 331 | * This uses crc32() to calculate the crc for fc frame |
| 333 | * Return : 32 bit crc | 332 | * Return : 32 bit crc |
| 334 | * | 333 | */ |
| 335 | **/ | ||
| 336 | u32 fcoe_fc_crc(struct fc_frame *fp) | 334 | u32 fcoe_fc_crc(struct fc_frame *fp) |
| 337 | { | 335 | { |
| 338 | struct sk_buff *skb = fp_skb(fp); | 336 | struct sk_buff *skb = fp_skb(fp); |
| @@ -363,13 +361,12 @@ u32 fcoe_fc_crc(struct fc_frame *fp) | |||
| 363 | EXPORT_SYMBOL_GPL(fcoe_fc_crc); | 361 | EXPORT_SYMBOL_GPL(fcoe_fc_crc); |
| 364 | 362 | ||
| 365 | /** | 363 | /** |
| 366 | * fcoe_xmit - FCoE frame transmit function | 364 | * fcoe_xmit() - FCoE frame transmit function |
| 367 | * @lp: the associated local port | 365 | * @lp: the associated local port |
| 368 | * @fp: the fc_frame to be transmitted | 366 | * @fp: the fc_frame to be transmitted |
| 369 | * | 367 | * |
| 370 | * Return : 0 for success | 368 | * Return : 0 for success |
| 371 | * | 369 | */ |
| 372 | **/ | ||
| 373 | int fcoe_xmit(struct fc_lport *lp, struct fc_frame *fp) | 370 | int fcoe_xmit(struct fc_lport *lp, struct fc_frame *fp) |
| 374 | { | 371 | { |
| 375 | int wlen, rc = 0; | 372 | int wlen, rc = 0; |
| @@ -389,7 +386,7 @@ int fcoe_xmit(struct fc_lport *lp, struct fc_frame *fp) | |||
| 389 | 386 | ||
| 390 | WARN_ON((fr_len(fp) % sizeof(u32)) != 0); | 387 | WARN_ON((fr_len(fp) % sizeof(u32)) != 0); |
| 391 | 388 | ||
| 392 | fc = fcoe_softc(lp); | 389 | fc = lport_priv(lp); |
| 393 | /* | 390 | /* |
| 394 | * if it is a flogi then we need to learn gw-addr | 391 | * if it is a flogi then we need to learn gw-addr |
| 395 | * and my own fcid | 392 | * and my own fcid |
| @@ -439,7 +436,7 @@ int fcoe_xmit(struct fc_lport *lp, struct fc_frame *fp) | |||
| 439 | if (skb_is_nonlinear(skb)) { | 436 | if (skb_is_nonlinear(skb)) { |
| 440 | skb_frag_t *frag; | 437 | skb_frag_t *frag; |
| 441 | if (fcoe_get_paged_crc_eof(skb, tlen)) { | 438 | if (fcoe_get_paged_crc_eof(skb, tlen)) { |
| 442 | kfree(skb); | 439 | kfree_skb(skb); |
| 443 | return -ENOMEM; | 440 | return -ENOMEM; |
| 444 | } | 441 | } |
| 445 | frag = &skb_shinfo(skb)->frags[skb_shinfo(skb)->nr_frags - 1]; | 442 | frag = &skb_shinfo(skb)->frags[skb_shinfo(skb)->nr_frags - 1]; |
| @@ -502,21 +499,22 @@ int fcoe_xmit(struct fc_lport *lp, struct fc_frame *fp) | |||
| 502 | rc = fcoe_start_io(skb); | 499 | rc = fcoe_start_io(skb); |
| 503 | 500 | ||
| 504 | if (rc) { | 501 | if (rc) { |
| 505 | fcoe_insert_wait_queue(lp, skb); | 502 | spin_lock_bh(&fc->fcoe_pending_queue.lock); |
| 503 | __skb_queue_tail(&fc->fcoe_pending_queue, skb); | ||
| 504 | spin_unlock_bh(&fc->fcoe_pending_queue.lock); | ||
| 506 | if (fc->fcoe_pending_queue.qlen > FCOE_MAX_QUEUE_DEPTH) | 505 | if (fc->fcoe_pending_queue.qlen > FCOE_MAX_QUEUE_DEPTH) |
| 507 | fc_pause(lp); | 506 | lp->qfull = 1; |
| 508 | } | 507 | } |
| 509 | 508 | ||
| 510 | return 0; | 509 | return 0; |
| 511 | } | 510 | } |
| 512 | EXPORT_SYMBOL_GPL(fcoe_xmit); | 511 | EXPORT_SYMBOL_GPL(fcoe_xmit); |
| 513 | 512 | ||
| 514 | /* | 513 | /** |
| 515 | * fcoe_percpu_receive_thread - recv thread per cpu | 514 | * fcoe_percpu_receive_thread() - recv thread per cpu |
| 516 | * @arg: ptr to the fcoe per cpu struct | 515 | * @arg: ptr to the fcoe per cpu struct |
| 517 | * | 516 | * |
| 518 | * Return: 0 for success | 517 | * Return: 0 for success |
| 519 | * | ||
| 520 | */ | 518 | */ |
| 521 | int fcoe_percpu_receive_thread(void *arg) | 519 | int fcoe_percpu_receive_thread(void *arg) |
| 522 | { | 520 | { |
| @@ -533,7 +531,7 @@ int fcoe_percpu_receive_thread(void *arg) | |||
| 533 | struct fcoe_softc *fc; | 531 | struct fcoe_softc *fc; |
| 534 | struct fcoe_hdr *hp; | 532 | struct fcoe_hdr *hp; |
| 535 | 533 | ||
| 536 | set_user_nice(current, 19); | 534 | set_user_nice(current, -20); |
| 537 | 535 | ||
| 538 | while (!kthread_should_stop()) { | 536 | while (!kthread_should_stop()) { |
| 539 | 537 | ||
| @@ -658,7 +656,7 @@ int fcoe_percpu_receive_thread(void *arg) | |||
| 658 | } | 656 | } |
| 659 | 657 | ||
| 660 | /** | 658 | /** |
| 661 | * fcoe_recv_flogi - flogi receive function | 659 | * fcoe_recv_flogi() - flogi receive function |
| 662 | * @fc: associated fcoe_softc | 660 | * @fc: associated fcoe_softc |
| 663 | * @fp: the recieved frame | 661 | * @fp: the recieved frame |
| 664 | * @sa: the source address of this flogi | 662 | * @sa: the source address of this flogi |
| @@ -667,7 +665,7 @@ int fcoe_percpu_receive_thread(void *arg) | |||
| 667 | * mac address for the initiator, eitehr OUI based or GW based. | 665 | * mac address for the initiator, eitehr OUI based or GW based. |
| 668 | * | 666 | * |
| 669 | * Returns: none | 667 | * Returns: none |
| 670 | **/ | 668 | */ |
| 671 | static void fcoe_recv_flogi(struct fcoe_softc *fc, struct fc_frame *fp, u8 *sa) | 669 | static void fcoe_recv_flogi(struct fcoe_softc *fc, struct fc_frame *fp, u8 *sa) |
| 672 | { | 670 | { |
| 673 | struct fc_frame_header *fh; | 671 | struct fc_frame_header *fh; |
| @@ -715,32 +713,23 @@ static void fcoe_recv_flogi(struct fcoe_softc *fc, struct fc_frame *fp, u8 *sa) | |||
| 715 | } | 713 | } |
| 716 | 714 | ||
| 717 | /** | 715 | /** |
| 718 | * fcoe_watchdog - fcoe timer callback | 716 | * fcoe_watchdog() - fcoe timer callback |
| 719 | * @vp: | 717 | * @vp: |
| 720 | * | 718 | * |
| 721 | * This checks the pending queue length for fcoe and put fcoe to be paused state | 719 | * This checks the pending queue length for fcoe and set lport qfull |
| 722 | * if the FCOE_MAX_QUEUE_DEPTH is reached. This is done for all fc_lport on the | 720 | * if the FCOE_MAX_QUEUE_DEPTH is reached. This is done for all fc_lport on the |
| 723 | * fcoe_hostlist. | 721 | * fcoe_hostlist. |
| 724 | * | 722 | * |
| 725 | * Returns: 0 for success | 723 | * Returns: 0 for success |
| 726 | **/ | 724 | */ |
| 727 | void fcoe_watchdog(ulong vp) | 725 | void fcoe_watchdog(ulong vp) |
| 728 | { | 726 | { |
| 729 | struct fc_lport *lp; | ||
| 730 | struct fcoe_softc *fc; | 727 | struct fcoe_softc *fc; |
| 731 | int paused = 0; | ||
| 732 | 728 | ||
| 733 | read_lock(&fcoe_hostlist_lock); | 729 | read_lock(&fcoe_hostlist_lock); |
| 734 | list_for_each_entry(fc, &fcoe_hostlist, list) { | 730 | list_for_each_entry(fc, &fcoe_hostlist, list) { |
| 735 | lp = fc->lp; | 731 | if (fc->lp) |
| 736 | if (lp) { | 732 | fcoe_check_wait_queue(fc->lp); |
| 737 | if (fc->fcoe_pending_queue.qlen > FCOE_MAX_QUEUE_DEPTH) | ||
| 738 | paused = 1; | ||
| 739 | if (fcoe_check_wait_queue(lp) < FCOE_MAX_QUEUE_DEPTH) { | ||
| 740 | if (paused) | ||
| 741 | fc_unpause(lp); | ||
| 742 | } | ||
| 743 | } | ||
| 744 | } | 733 | } |
| 745 | read_unlock(&fcoe_hostlist_lock); | 734 | read_unlock(&fcoe_hostlist_lock); |
| 746 | 735 | ||
| @@ -750,96 +739,64 @@ void fcoe_watchdog(ulong vp) | |||
| 750 | 739 | ||
| 751 | 740 | ||
| 752 | /** | 741 | /** |
| 753 | * fcoe_check_wait_queue - put the skb into fcoe pending xmit queue | 742 | * fcoe_check_wait_queue() - put the skb into fcoe pending xmit queue |
| 754 | * @lp: the fc_port for this skb | 743 | * @lp: the fc_port for this skb |
| 755 | * @skb: the associated skb to be xmitted | 744 | * @skb: the associated skb to be xmitted |
| 756 | * | 745 | * |
| 757 | * This empties the wait_queue, dequeue the head of the wait_queue queue | 746 | * This empties the wait_queue, dequeue the head of the wait_queue queue |
| 758 | * and calls fcoe_start_io() for each packet, if all skb have been | 747 | * and calls fcoe_start_io() for each packet, if all skb have been |
| 759 | * transmitted, return 0 if a error occurs, then restore wait_queue and | 748 | * transmitted, return qlen or -1 if a error occurs, then restore |
| 760 | * try again later. | 749 | * wait_queue and try again later. |
| 761 | * | 750 | * |
| 762 | * The wait_queue is used when the skb transmit fails. skb will go | 751 | * The wait_queue is used when the skb transmit fails. skb will go |
| 763 | * in the wait_queue which will be emptied by the time function OR | 752 | * in the wait_queue which will be emptied by the time function OR |
| 764 | * by the next skb transmit. | 753 | * by the next skb transmit. |
| 765 | * | 754 | * |
| 766 | * Returns: 0 for success | 755 | * Returns: 0 for success |
| 767 | **/ | 756 | */ |
| 768 | static int fcoe_check_wait_queue(struct fc_lport *lp) | 757 | static int fcoe_check_wait_queue(struct fc_lport *lp) |
| 769 | { | 758 | { |
| 770 | int rc, unpause = 0; | 759 | struct fcoe_softc *fc = lport_priv(lp); |
| 771 | int paused = 0; | ||
| 772 | struct sk_buff *skb; | 760 | struct sk_buff *skb; |
| 773 | struct fcoe_softc *fc; | 761 | int rc = -1; |
| 774 | 762 | ||
| 775 | fc = fcoe_softc(lp); | ||
| 776 | spin_lock_bh(&fc->fcoe_pending_queue.lock); | 763 | spin_lock_bh(&fc->fcoe_pending_queue.lock); |
| 764 | if (fc->fcoe_pending_queue_active) | ||
| 765 | goto out; | ||
| 766 | fc->fcoe_pending_queue_active = 1; | ||
| 777 | 767 | ||
| 778 | /* | 768 | while (fc->fcoe_pending_queue.qlen) { |
| 779 | * is this interface paused? | 769 | /* keep qlen > 0 until fcoe_start_io succeeds */ |
| 780 | */ | 770 | fc->fcoe_pending_queue.qlen++; |
| 781 | if (fc->fcoe_pending_queue.qlen > FCOE_MAX_QUEUE_DEPTH) | 771 | skb = __skb_dequeue(&fc->fcoe_pending_queue); |
| 782 | paused = 1; | ||
| 783 | if (fc->fcoe_pending_queue.qlen) { | ||
| 784 | while ((skb = __skb_dequeue(&fc->fcoe_pending_queue)) != NULL) { | ||
| 785 | spin_unlock_bh(&fc->fcoe_pending_queue.lock); | ||
| 786 | rc = fcoe_start_io(skb); | ||
| 787 | if (rc) { | ||
| 788 | fcoe_insert_wait_queue_head(lp, skb); | ||
| 789 | return rc; | ||
| 790 | } | ||
| 791 | spin_lock_bh(&fc->fcoe_pending_queue.lock); | ||
| 792 | } | ||
| 793 | if (fc->fcoe_pending_queue.qlen < FCOE_MAX_QUEUE_DEPTH) | ||
| 794 | unpause = 1; | ||
| 795 | } | ||
| 796 | spin_unlock_bh(&fc->fcoe_pending_queue.lock); | ||
| 797 | if ((unpause) && (paused)) | ||
| 798 | fc_unpause(lp); | ||
| 799 | return fc->fcoe_pending_queue.qlen; | ||
| 800 | } | ||
| 801 | |||
| 802 | /** | ||
| 803 | * fcoe_insert_wait_queue_head - puts skb to fcoe pending queue head | ||
| 804 | * @lp: the fc_port for this skb | ||
| 805 | * @skb: the associated skb to be xmitted | ||
| 806 | * | ||
| 807 | * Returns: none | ||
| 808 | **/ | ||
| 809 | static void fcoe_insert_wait_queue_head(struct fc_lport *lp, | ||
| 810 | struct sk_buff *skb) | ||
| 811 | { | ||
| 812 | struct fcoe_softc *fc; | ||
| 813 | 772 | ||
| 814 | fc = fcoe_softc(lp); | 773 | spin_unlock_bh(&fc->fcoe_pending_queue.lock); |
| 815 | spin_lock_bh(&fc->fcoe_pending_queue.lock); | 774 | rc = fcoe_start_io(skb); |
| 816 | __skb_queue_head(&fc->fcoe_pending_queue, skb); | 775 | spin_lock_bh(&fc->fcoe_pending_queue.lock); |
| 817 | spin_unlock_bh(&fc->fcoe_pending_queue.lock); | ||
| 818 | } | ||
| 819 | 776 | ||
| 820 | /** | 777 | if (rc) { |
| 821 | * fcoe_insert_wait_queue - put the skb into fcoe pending queue tail | 778 | __skb_queue_head(&fc->fcoe_pending_queue, skb); |
| 822 | * @lp: the fc_port for this skb | 779 | /* undo temporary increment above */ |
| 823 | * @skb: the associated skb to be xmitted | 780 | fc->fcoe_pending_queue.qlen--; |
| 824 | * | 781 | break; |
| 825 | * Returns: none | 782 | } |
| 826 | **/ | 783 | /* undo temporary increment above */ |
| 827 | static void fcoe_insert_wait_queue(struct fc_lport *lp, | 784 | fc->fcoe_pending_queue.qlen--; |
| 828 | struct sk_buff *skb) | 785 | } |
| 829 | { | ||
| 830 | struct fcoe_softc *fc; | ||
| 831 | 786 | ||
| 832 | fc = fcoe_softc(lp); | 787 | if (fc->fcoe_pending_queue.qlen < FCOE_LOW_QUEUE_DEPTH) |
| 833 | spin_lock_bh(&fc->fcoe_pending_queue.lock); | 788 | lp->qfull = 0; |
| 834 | __skb_queue_tail(&fc->fcoe_pending_queue, skb); | 789 | fc->fcoe_pending_queue_active = 0; |
| 790 | rc = fc->fcoe_pending_queue.qlen; | ||
| 791 | out: | ||
| 835 | spin_unlock_bh(&fc->fcoe_pending_queue.lock); | 792 | spin_unlock_bh(&fc->fcoe_pending_queue.lock); |
| 793 | return rc; | ||
| 836 | } | 794 | } |
| 837 | 795 | ||
| 838 | /** | 796 | /** |
| 839 | * fcoe_dev_setup - setup link change notification interface | 797 | * fcoe_dev_setup() - setup link change notification interface |
| 840 | * | 798 | */ |
| 841 | **/ | 799 | static void fcoe_dev_setup() |
| 842 | static void fcoe_dev_setup(void) | ||
| 843 | { | 800 | { |
| 844 | /* | 801 | /* |
| 845 | * here setup a interface specific wd time to | 802 | * here setup a interface specific wd time to |
| @@ -849,15 +806,15 @@ static void fcoe_dev_setup(void) | |||
| 849 | } | 806 | } |
| 850 | 807 | ||
| 851 | /** | 808 | /** |
| 852 | * fcoe_dev_setup - cleanup link change notification interface | 809 | * fcoe_dev_setup() - cleanup link change notification interface |
| 853 | **/ | 810 | */ |
| 854 | static void fcoe_dev_cleanup(void) | 811 | static void fcoe_dev_cleanup(void) |
| 855 | { | 812 | { |
| 856 | unregister_netdevice_notifier(&fcoe_notifier); | 813 | unregister_netdevice_notifier(&fcoe_notifier); |
| 857 | } | 814 | } |
| 858 | 815 | ||
| 859 | /** | 816 | /** |
| 860 | * fcoe_device_notification - netdev event notification callback | 817 | * fcoe_device_notification() - netdev event notification callback |
| 861 | * @notifier: context of the notification | 818 | * @notifier: context of the notification |
| 862 | * @event: type of event | 819 | * @event: type of event |
| 863 | * @ptr: fixed array for output parsed ifname | 820 | * @ptr: fixed array for output parsed ifname |
| @@ -865,7 +822,7 @@ static void fcoe_dev_cleanup(void) | |||
| 865 | * This function is called by the ethernet driver in case of link change event | 822 | * This function is called by the ethernet driver in case of link change event |
| 866 | * | 823 | * |
| 867 | * Returns: 0 for success | 824 | * Returns: 0 for success |
| 868 | **/ | 825 | */ |
| 869 | static int fcoe_device_notification(struct notifier_block *notifier, | 826 | static int fcoe_device_notification(struct notifier_block *notifier, |
| 870 | ulong event, void *ptr) | 827 | ulong event, void *ptr) |
| 871 | { | 828 | { |
| @@ -873,7 +830,7 @@ static int fcoe_device_notification(struct notifier_block *notifier, | |||
| 873 | struct net_device *real_dev = ptr; | 830 | struct net_device *real_dev = ptr; |
| 874 | struct fcoe_softc *fc; | 831 | struct fcoe_softc *fc; |
| 875 | struct fcoe_dev_stats *stats; | 832 | struct fcoe_dev_stats *stats; |
| 876 | u16 new_status; | 833 | u32 new_link_up; |
| 877 | u32 mfs; | 834 | u32 mfs; |
| 878 | int rc = NOTIFY_OK; | 835 | int rc = NOTIFY_OK; |
| 879 | 836 | ||
| @@ -890,17 +847,15 @@ static int fcoe_device_notification(struct notifier_block *notifier, | |||
| 890 | goto out; | 847 | goto out; |
| 891 | } | 848 | } |
| 892 | 849 | ||
| 893 | new_status = lp->link_status; | 850 | new_link_up = lp->link_up; |
| 894 | switch (event) { | 851 | switch (event) { |
| 895 | case NETDEV_DOWN: | 852 | case NETDEV_DOWN: |
| 896 | case NETDEV_GOING_DOWN: | 853 | case NETDEV_GOING_DOWN: |
| 897 | new_status &= ~FC_LINK_UP; | 854 | new_link_up = 0; |
| 898 | break; | 855 | break; |
| 899 | case NETDEV_UP: | 856 | case NETDEV_UP: |
| 900 | case NETDEV_CHANGE: | 857 | case NETDEV_CHANGE: |
| 901 | new_status &= ~FC_LINK_UP; | 858 | new_link_up = !fcoe_link_ok(lp); |
| 902 | if (!fcoe_link_ok(lp)) | ||
| 903 | new_status |= FC_LINK_UP; | ||
| 904 | break; | 859 | break; |
| 905 | case NETDEV_CHANGEMTU: | 860 | case NETDEV_CHANGEMTU: |
| 906 | mfs = fc->real_dev->mtu - | 861 | mfs = fc->real_dev->mtu - |
| @@ -908,17 +863,15 @@ static int fcoe_device_notification(struct notifier_block *notifier, | |||
| 908 | sizeof(struct fcoe_crc_eof)); | 863 | sizeof(struct fcoe_crc_eof)); |
| 909 | if (mfs >= FC_MIN_MAX_FRAME) | 864 | if (mfs >= FC_MIN_MAX_FRAME) |
| 910 | fc_set_mfs(lp, mfs); | 865 | fc_set_mfs(lp, mfs); |
| 911 | new_status &= ~FC_LINK_UP; | 866 | new_link_up = !fcoe_link_ok(lp); |
| 912 | if (!fcoe_link_ok(lp)) | ||
| 913 | new_status |= FC_LINK_UP; | ||
| 914 | break; | 867 | break; |
| 915 | case NETDEV_REGISTER: | 868 | case NETDEV_REGISTER: |
| 916 | break; | 869 | break; |
| 917 | default: | 870 | default: |
| 918 | FC_DBG("unknown event %ld call", event); | 871 | FC_DBG("unknown event %ld call", event); |
| 919 | } | 872 | } |
| 920 | if (lp->link_status != new_status) { | 873 | if (lp->link_up != new_link_up) { |
| 921 | if ((new_status & FC_LINK_UP) == FC_LINK_UP) | 874 | if (new_link_up) |
| 922 | fc_linkup(lp); | 875 | fc_linkup(lp); |
| 923 | else { | 876 | else { |
| 924 | stats = lp->dev_stats[smp_processor_id()]; | 877 | stats = lp->dev_stats[smp_processor_id()]; |
| @@ -933,12 +886,12 @@ out: | |||
| 933 | } | 886 | } |
| 934 | 887 | ||
| 935 | /** | 888 | /** |
| 936 | * fcoe_if_to_netdev - parse a name buffer to get netdev | 889 | * fcoe_if_to_netdev() - parse a name buffer to get netdev |
| 937 | * @ifname: fixed array for output parsed ifname | 890 | * @ifname: fixed array for output parsed ifname |
| 938 | * @buffer: incoming buffer to be copied | 891 | * @buffer: incoming buffer to be copied |
| 939 | * | 892 | * |
| 940 | * Returns: NULL or ptr to netdeive | 893 | * Returns: NULL or ptr to netdeive |
| 941 | **/ | 894 | */ |
| 942 | static struct net_device *fcoe_if_to_netdev(const char *buffer) | 895 | static struct net_device *fcoe_if_to_netdev(const char *buffer) |
| 943 | { | 896 | { |
| 944 | char *cp; | 897 | char *cp; |
| @@ -955,13 +908,13 @@ static struct net_device *fcoe_if_to_netdev(const char *buffer) | |||
| 955 | } | 908 | } |
| 956 | 909 | ||
| 957 | /** | 910 | /** |
| 958 | * fcoe_netdev_to_module_owner - finds out the nic drive moddule of the netdev | 911 | * fcoe_netdev_to_module_owner() - finds out the nic drive moddule of the netdev |
| 959 | * @netdev: the target netdev | 912 | * @netdev: the target netdev |
| 960 | * | 913 | * |
| 961 | * Returns: ptr to the struct module, NULL for failure | 914 | * Returns: ptr to the struct module, NULL for failure |
| 962 | **/ | 915 | */ |
| 963 | static struct module *fcoe_netdev_to_module_owner( | 916 | static struct module * |
| 964 | const struct net_device *netdev) | 917 | fcoe_netdev_to_module_owner(const struct net_device *netdev) |
| 965 | { | 918 | { |
| 966 | struct device *dev; | 919 | struct device *dev; |
| 967 | 920 | ||
| @@ -979,12 +932,14 @@ static struct module *fcoe_netdev_to_module_owner( | |||
| 979 | } | 932 | } |
| 980 | 933 | ||
| 981 | /** | 934 | /** |
| 982 | * fcoe_ethdrv_get - holds the nic driver module by try_module_get() for | 935 | * fcoe_ethdrv_get() - Hold the Ethernet driver |
| 983 | * the corresponding netdev. | ||
| 984 | * @netdev: the target netdev | 936 | * @netdev: the target netdev |
| 985 | * | 937 | * |
| 938 | * Holds the Ethernet driver module by try_module_get() for | ||
| 939 | * the corresponding netdev. | ||
| 940 | * | ||
| 986 | * Returns: 0 for succsss | 941 | * Returns: 0 for succsss |
| 987 | **/ | 942 | */ |
| 988 | static int fcoe_ethdrv_get(const struct net_device *netdev) | 943 | static int fcoe_ethdrv_get(const struct net_device *netdev) |
| 989 | { | 944 | { |
| 990 | struct module *owner; | 945 | struct module *owner; |
| @@ -999,12 +954,14 @@ static int fcoe_ethdrv_get(const struct net_device *netdev) | |||
| 999 | } | 954 | } |
| 1000 | 955 | ||
| 1001 | /** | 956 | /** |
| 1002 | * fcoe_ethdrv_get - releases the nic driver module by module_put for | 957 | * fcoe_ethdrv_put() - Release the Ethernet driver |
| 1003 | * the corresponding netdev. | ||
| 1004 | * @netdev: the target netdev | 958 | * @netdev: the target netdev |
| 1005 | * | 959 | * |
| 960 | * Releases the Ethernet driver module by module_put for | ||
| 961 | * the corresponding netdev. | ||
| 962 | * | ||
| 1006 | * Returns: 0 for succsss | 963 | * Returns: 0 for succsss |
| 1007 | **/ | 964 | */ |
| 1008 | static int fcoe_ethdrv_put(const struct net_device *netdev) | 965 | static int fcoe_ethdrv_put(const struct net_device *netdev) |
| 1009 | { | 966 | { |
| 1010 | struct module *owner; | 967 | struct module *owner; |
| @@ -1020,12 +977,12 @@ static int fcoe_ethdrv_put(const struct net_device *netdev) | |||
| 1020 | } | 977 | } |
| 1021 | 978 | ||
| 1022 | /** | 979 | /** |
| 1023 | * fcoe_destroy- handles the destroy from sysfs | 980 | * fcoe_destroy() - handles the destroy from sysfs |
| 1024 | * @buffer: expcted to be a eth if name | 981 | * @buffer: expcted to be a eth if name |
| 1025 | * @kp: associated kernel param | 982 | * @kp: associated kernel param |
| 1026 | * | 983 | * |
| 1027 | * Returns: 0 for success | 984 | * Returns: 0 for success |
| 1028 | **/ | 985 | */ |
| 1029 | static int fcoe_destroy(const char *buffer, struct kernel_param *kp) | 986 | static int fcoe_destroy(const char *buffer, struct kernel_param *kp) |
| 1030 | { | 987 | { |
| 1031 | int rc; | 988 | int rc; |
| @@ -1058,12 +1015,12 @@ out_nodev: | |||
| 1058 | } | 1015 | } |
| 1059 | 1016 | ||
| 1060 | /** | 1017 | /** |
| 1061 | * fcoe_create - handles the create call from sysfs | 1018 | * fcoe_create() - Handles the create call from sysfs |
| 1062 | * @buffer: expcted to be a eth if name | 1019 | * @buffer: expcted to be a eth if name |
| 1063 | * @kp: associated kernel param | 1020 | * @kp: associated kernel param |
| 1064 | * | 1021 | * |
| 1065 | * Returns: 0 for success | 1022 | * Returns: 0 for success |
| 1066 | **/ | 1023 | */ |
| 1067 | static int fcoe_create(const char *buffer, struct kernel_param *kp) | 1024 | static int fcoe_create(const char *buffer, struct kernel_param *kp) |
| 1068 | { | 1025 | { |
| 1069 | int rc; | 1026 | int rc; |
| @@ -1104,8 +1061,8 @@ module_param_call(destroy, fcoe_destroy, NULL, NULL, S_IWUSR); | |||
| 1104 | __MODULE_PARM_TYPE(destroy, "string"); | 1061 | __MODULE_PARM_TYPE(destroy, "string"); |
| 1105 | MODULE_PARM_DESC(destroy, "Destroy fcoe port"); | 1062 | MODULE_PARM_DESC(destroy, "Destroy fcoe port"); |
| 1106 | 1063 | ||
| 1107 | /* | 1064 | /** |
| 1108 | * fcoe_link_ok - check if link is ok for the fc_lport | 1065 | * fcoe_link_ok() - Check if link is ok for the fc_lport |
| 1109 | * @lp: ptr to the fc_lport | 1066 | * @lp: ptr to the fc_lport |
| 1110 | * | 1067 | * |
| 1111 | * Any permanently-disqualifying conditions have been previously checked. | 1068 | * Any permanently-disqualifying conditions have been previously checked. |
| @@ -1120,7 +1077,7 @@ MODULE_PARM_DESC(destroy, "Destroy fcoe port"); | |||
| 1120 | */ | 1077 | */ |
| 1121 | int fcoe_link_ok(struct fc_lport *lp) | 1078 | int fcoe_link_ok(struct fc_lport *lp) |
| 1122 | { | 1079 | { |
| 1123 | struct fcoe_softc *fc = fcoe_softc(lp); | 1080 | struct fcoe_softc *fc = lport_priv(lp); |
| 1124 | struct net_device *dev = fc->real_dev; | 1081 | struct net_device *dev = fc->real_dev; |
| 1125 | struct ethtool_cmd ecmd = { ETHTOOL_GSET }; | 1082 | struct ethtool_cmd ecmd = { ETHTOOL_GSET }; |
| 1126 | int rc = 0; | 1083 | int rc = 0; |
| @@ -1149,9 +1106,8 @@ int fcoe_link_ok(struct fc_lport *lp) | |||
| 1149 | } | 1106 | } |
| 1150 | EXPORT_SYMBOL_GPL(fcoe_link_ok); | 1107 | EXPORT_SYMBOL_GPL(fcoe_link_ok); |
| 1151 | 1108 | ||
| 1152 | /* | 1109 | /** |
| 1153 | * fcoe_percpu_clean - frees skb of the corresponding lport from the per | 1110 | * fcoe_percpu_clean() - Clear the pending skbs for an lport |
| 1154 | * cpu queue. | ||
| 1155 | * @lp: the fc_lport | 1111 | * @lp: the fc_lport |
| 1156 | */ | 1112 | */ |
| 1157 | void fcoe_percpu_clean(struct fc_lport *lp) | 1113 | void fcoe_percpu_clean(struct fc_lport *lp) |
| @@ -1185,11 +1141,11 @@ void fcoe_percpu_clean(struct fc_lport *lp) | |||
| 1185 | EXPORT_SYMBOL_GPL(fcoe_percpu_clean); | 1141 | EXPORT_SYMBOL_GPL(fcoe_percpu_clean); |
| 1186 | 1142 | ||
| 1187 | /** | 1143 | /** |
| 1188 | * fcoe_clean_pending_queue - dequeue skb and free it | 1144 | * fcoe_clean_pending_queue() - Dequeue a skb and free it |
| 1189 | * @lp: the corresponding fc_lport | 1145 | * @lp: the corresponding fc_lport |
| 1190 | * | 1146 | * |
| 1191 | * Returns: none | 1147 | * Returns: none |
| 1192 | **/ | 1148 | */ |
| 1193 | void fcoe_clean_pending_queue(struct fc_lport *lp) | 1149 | void fcoe_clean_pending_queue(struct fc_lport *lp) |
| 1194 | { | 1150 | { |
| 1195 | struct fcoe_softc *fc = lport_priv(lp); | 1151 | struct fcoe_softc *fc = lport_priv(lp); |
| @@ -1206,21 +1162,21 @@ void fcoe_clean_pending_queue(struct fc_lport *lp) | |||
| 1206 | EXPORT_SYMBOL_GPL(fcoe_clean_pending_queue); | 1162 | EXPORT_SYMBOL_GPL(fcoe_clean_pending_queue); |
| 1207 | 1163 | ||
| 1208 | /** | 1164 | /** |
| 1209 | * libfc_host_alloc - allocate a Scsi_Host with room for the fc_lport | 1165 | * libfc_host_alloc() - Allocate a Scsi_Host with room for the fc_lport |
| 1210 | * @sht: ptr to the scsi host templ | 1166 | * @sht: ptr to the scsi host templ |
| 1211 | * @priv_size: size of private data after fc_lport | 1167 | * @priv_size: size of private data after fc_lport |
| 1212 | * | 1168 | * |
| 1213 | * Returns: ptr to Scsi_Host | 1169 | * Returns: ptr to Scsi_Host |
| 1214 | * TODO - to libfc? | 1170 | * TODO: to libfc? |
| 1215 | */ | 1171 | */ |
| 1216 | static inline struct Scsi_Host *libfc_host_alloc( | 1172 | static inline struct Scsi_Host * |
| 1217 | struct scsi_host_template *sht, int priv_size) | 1173 | libfc_host_alloc(struct scsi_host_template *sht, int priv_size) |
| 1218 | { | 1174 | { |
| 1219 | return scsi_host_alloc(sht, sizeof(struct fc_lport) + priv_size); | 1175 | return scsi_host_alloc(sht, sizeof(struct fc_lport) + priv_size); |
| 1220 | } | 1176 | } |
| 1221 | 1177 | ||
| 1222 | /** | 1178 | /** |
| 1223 | * fcoe_host_alloc - allocate a Scsi_Host with room for the fcoe_softc | 1179 | * fcoe_host_alloc() - Allocate a Scsi_Host with room for the fcoe_softc |
| 1224 | * @sht: ptr to the scsi host templ | 1180 | * @sht: ptr to the scsi host templ |
| 1225 | * @priv_size: size of private data after fc_lport | 1181 | * @priv_size: size of private data after fc_lport |
| 1226 | * | 1182 | * |
| @@ -1232,8 +1188,8 @@ struct Scsi_Host *fcoe_host_alloc(struct scsi_host_template *sht, int priv_size) | |||
| 1232 | } | 1188 | } |
| 1233 | EXPORT_SYMBOL_GPL(fcoe_host_alloc); | 1189 | EXPORT_SYMBOL_GPL(fcoe_host_alloc); |
| 1234 | 1190 | ||
| 1235 | /* | 1191 | /** |
| 1236 | * fcoe_reset - resets the fcoe | 1192 | * fcoe_reset() - Resets the fcoe |
| 1237 | * @shost: shost the reset is from | 1193 | * @shost: shost the reset is from |
| 1238 | * | 1194 | * |
| 1239 | * Returns: always 0 | 1195 | * Returns: always 0 |
| @@ -1246,8 +1202,8 @@ int fcoe_reset(struct Scsi_Host *shost) | |||
| 1246 | } | 1202 | } |
| 1247 | EXPORT_SYMBOL_GPL(fcoe_reset); | 1203 | EXPORT_SYMBOL_GPL(fcoe_reset); |
| 1248 | 1204 | ||
| 1249 | /* | 1205 | /** |
| 1250 | * fcoe_wwn_from_mac - converts 48-bit IEEE MAC address to 64-bit FC WWN. | 1206 | * fcoe_wwn_from_mac() - Converts 48-bit IEEE MAC address to 64-bit FC WWN. |
| 1251 | * @mac: mac address | 1207 | * @mac: mac address |
| 1252 | * @scheme: check port | 1208 | * @scheme: check port |
| 1253 | * @port: port indicator for converting | 1209 | * @port: port indicator for converting |
| @@ -1286,14 +1242,15 @@ u64 fcoe_wwn_from_mac(unsigned char mac[MAX_ADDR_LEN], | |||
| 1286 | return wwn; | 1242 | return wwn; |
| 1287 | } | 1243 | } |
| 1288 | EXPORT_SYMBOL_GPL(fcoe_wwn_from_mac); | 1244 | EXPORT_SYMBOL_GPL(fcoe_wwn_from_mac); |
| 1289 | /* | 1245 | |
| 1290 | * fcoe_hostlist_lookup_softc - find the corresponding lport by a given device | 1246 | /** |
| 1247 | * fcoe_hostlist_lookup_softc() - find the corresponding lport by a given device | ||
| 1291 | * @device: this is currently ptr to net_device | 1248 | * @device: this is currently ptr to net_device |
| 1292 | * | 1249 | * |
| 1293 | * Returns: NULL or the located fcoe_softc | 1250 | * Returns: NULL or the located fcoe_softc |
| 1294 | */ | 1251 | */ |
| 1295 | static struct fcoe_softc *fcoe_hostlist_lookup_softc( | 1252 | static struct fcoe_softc * |
| 1296 | const struct net_device *dev) | 1253 | fcoe_hostlist_lookup_softc(const struct net_device *dev) |
| 1297 | { | 1254 | { |
| 1298 | struct fcoe_softc *fc; | 1255 | struct fcoe_softc *fc; |
| 1299 | 1256 | ||
| @@ -1308,8 +1265,8 @@ static struct fcoe_softc *fcoe_hostlist_lookup_softc( | |||
| 1308 | return NULL; | 1265 | return NULL; |
| 1309 | } | 1266 | } |
| 1310 | 1267 | ||
| 1311 | /* | 1268 | /** |
| 1312 | * fcoe_hostlist_lookup - find the corresponding lport by netdev | 1269 | * fcoe_hostlist_lookup() - Find the corresponding lport by netdev |
| 1313 | * @netdev: ptr to net_device | 1270 | * @netdev: ptr to net_device |
| 1314 | * | 1271 | * |
| 1315 | * Returns: 0 for success | 1272 | * Returns: 0 for success |
| @@ -1324,8 +1281,8 @@ struct fc_lport *fcoe_hostlist_lookup(const struct net_device *netdev) | |||
| 1324 | } | 1281 | } |
| 1325 | EXPORT_SYMBOL_GPL(fcoe_hostlist_lookup); | 1282 | EXPORT_SYMBOL_GPL(fcoe_hostlist_lookup); |
| 1326 | 1283 | ||
| 1327 | /* | 1284 | /** |
| 1328 | * fcoe_hostlist_add - add a lport to lports list | 1285 | * fcoe_hostlist_add() - Add a lport to lports list |
| 1329 | * @lp: ptr to the fc_lport to badded | 1286 | * @lp: ptr to the fc_lport to badded |
| 1330 | * | 1287 | * |
| 1331 | * Returns: 0 for success | 1288 | * Returns: 0 for success |
| @@ -1336,7 +1293,7 @@ int fcoe_hostlist_add(const struct fc_lport *lp) | |||
| 1336 | 1293 | ||
| 1337 | fc = fcoe_hostlist_lookup_softc(fcoe_netdev(lp)); | 1294 | fc = fcoe_hostlist_lookup_softc(fcoe_netdev(lp)); |
| 1338 | if (!fc) { | 1295 | if (!fc) { |
| 1339 | fc = fcoe_softc(lp); | 1296 | fc = lport_priv(lp); |
| 1340 | write_lock_bh(&fcoe_hostlist_lock); | 1297 | write_lock_bh(&fcoe_hostlist_lock); |
| 1341 | list_add_tail(&fc->list, &fcoe_hostlist); | 1298 | list_add_tail(&fc->list, &fcoe_hostlist); |
| 1342 | write_unlock_bh(&fcoe_hostlist_lock); | 1299 | write_unlock_bh(&fcoe_hostlist_lock); |
| @@ -1345,8 +1302,8 @@ int fcoe_hostlist_add(const struct fc_lport *lp) | |||
| 1345 | } | 1302 | } |
| 1346 | EXPORT_SYMBOL_GPL(fcoe_hostlist_add); | 1303 | EXPORT_SYMBOL_GPL(fcoe_hostlist_add); |
| 1347 | 1304 | ||
| 1348 | /* | 1305 | /** |
| 1349 | * fcoe_hostlist_remove - remove a lport from lports list | 1306 | * fcoe_hostlist_remove() - remove a lport from lports list |
| 1350 | * @lp: ptr to the fc_lport to badded | 1307 | * @lp: ptr to the fc_lport to badded |
| 1351 | * | 1308 | * |
| 1352 | * Returns: 0 for success | 1309 | * Returns: 0 for success |
| @@ -1366,12 +1323,12 @@ int fcoe_hostlist_remove(const struct fc_lport *lp) | |||
| 1366 | EXPORT_SYMBOL_GPL(fcoe_hostlist_remove); | 1323 | EXPORT_SYMBOL_GPL(fcoe_hostlist_remove); |
| 1367 | 1324 | ||
| 1368 | /** | 1325 | /** |
| 1369 | * fcoe_libfc_config - sets up libfc related properties for lport | 1326 | * fcoe_libfc_config() - sets up libfc related properties for lport |
| 1370 | * @lp: ptr to the fc_lport | 1327 | * @lp: ptr to the fc_lport |
| 1371 | * @tt: libfc function template | 1328 | * @tt: libfc function template |
| 1372 | * | 1329 | * |
| 1373 | * Returns : 0 for success | 1330 | * Returns : 0 for success |
| 1374 | **/ | 1331 | */ |
| 1375 | int fcoe_libfc_config(struct fc_lport *lp, struct libfc_function_template *tt) | 1332 | int fcoe_libfc_config(struct fc_lport *lp, struct libfc_function_template *tt) |
| 1376 | { | 1333 | { |
| 1377 | /* Set the function pointers set by the LLDD */ | 1334 | /* Set the function pointers set by the LLDD */ |
| @@ -1389,14 +1346,14 @@ int fcoe_libfc_config(struct fc_lport *lp, struct libfc_function_template *tt) | |||
| 1389 | EXPORT_SYMBOL_GPL(fcoe_libfc_config); | 1346 | EXPORT_SYMBOL_GPL(fcoe_libfc_config); |
| 1390 | 1347 | ||
| 1391 | /** | 1348 | /** |
| 1392 | * fcoe_init - fcoe module loading initialization | 1349 | * fcoe_init() - fcoe module loading initialization |
| 1393 | * | 1350 | * |
| 1394 | * Initialization routine | 1351 | * Initialization routine |
| 1395 | * 1. Will create fc transport software structure | 1352 | * 1. Will create fc transport software structure |
| 1396 | * 2. initialize the link list of port information structure | 1353 | * 2. initialize the link list of port information structure |
| 1397 | * | 1354 | * |
| 1398 | * Returns 0 on success, negative on failure | 1355 | * Returns 0 on success, negative on failure |
| 1399 | **/ | 1356 | */ |
| 1400 | static int __init fcoe_init(void) | 1357 | static int __init fcoe_init(void) |
| 1401 | { | 1358 | { |
| 1402 | int cpu; | 1359 | int cpu; |
| @@ -1433,7 +1390,6 @@ static int __init fcoe_init(void) | |||
| 1433 | } else { | 1390 | } else { |
| 1434 | fcoe_percpu[cpu] = NULL; | 1391 | fcoe_percpu[cpu] = NULL; |
| 1435 | kfree(p); | 1392 | kfree(p); |
| 1436 | |||
| 1437 | } | 1393 | } |
| 1438 | } | 1394 | } |
| 1439 | } | 1395 | } |
| @@ -1443,11 +1399,9 @@ static int __init fcoe_init(void) | |||
| 1443 | */ | 1399 | */ |
| 1444 | fcoe_dev_setup(); | 1400 | fcoe_dev_setup(); |
| 1445 | 1401 | ||
| 1446 | init_timer(&fcoe_timer); | 1402 | setup_timer(&fcoe_timer, fcoe_watchdog, 0); |
| 1447 | fcoe_timer.data = 0; | 1403 | |
| 1448 | fcoe_timer.function = fcoe_watchdog; | 1404 | mod_timer(&fcoe_timer, jiffies + (10 * HZ)); |
| 1449 | fcoe_timer.expires = (jiffies + (10 * HZ)); | ||
| 1450 | add_timer(&fcoe_timer); | ||
| 1451 | 1405 | ||
| 1452 | /* initiatlize the fcoe transport */ | 1406 | /* initiatlize the fcoe transport */ |
| 1453 | fcoe_transport_init(); | 1407 | fcoe_transport_init(); |
| @@ -1459,10 +1413,10 @@ static int __init fcoe_init(void) | |||
| 1459 | module_init(fcoe_init); | 1413 | module_init(fcoe_init); |
| 1460 | 1414 | ||
| 1461 | /** | 1415 | /** |
| 1462 | * fcoe_exit - fcoe module unloading cleanup | 1416 | * fcoe_exit() - fcoe module unloading cleanup |
| 1463 | * | 1417 | * |
| 1464 | * Returns 0 on success, negative on failure | 1418 | * Returns 0 on success, negative on failure |
| 1465 | **/ | 1419 | */ |
| 1466 | static void __exit fcoe_exit(void) | 1420 | static void __exit fcoe_exit(void) |
| 1467 | { | 1421 | { |
| 1468 | u32 idx; | 1422 | u32 idx; |
| @@ -1483,7 +1437,7 @@ static void __exit fcoe_exit(void) | |||
| 1483 | */ | 1437 | */ |
| 1484 | del_timer_sync(&fcoe_timer); | 1438 | del_timer_sync(&fcoe_timer); |
| 1485 | 1439 | ||
| 1486 | /* releases the assocaited fcoe transport for each lport */ | 1440 | /* releases the associated fcoe transport for each lport */ |
| 1487 | list_for_each_entry_safe(fc, tmp, &fcoe_hostlist, list) | 1441 | list_for_each_entry_safe(fc, tmp, &fcoe_hostlist, list) |
| 1488 | fcoe_transport_release(fc->real_dev); | 1442 | fcoe_transport_release(fc->real_dev); |
| 1489 | 1443 | ||
diff --git a/drivers/scsi/lasi700.c b/drivers/scsi/lasi700.c index 4a4e6954ec79..f23c4ca9a2ee 100644 --- a/drivers/scsi/lasi700.c +++ b/drivers/scsi/lasi700.c | |||
| @@ -103,7 +103,7 @@ lasi700_probe(struct parisc_device *dev) | |||
| 103 | 103 | ||
| 104 | hostdata = kzalloc(sizeof(*hostdata), GFP_KERNEL); | 104 | hostdata = kzalloc(sizeof(*hostdata), GFP_KERNEL); |
| 105 | if (!hostdata) { | 105 | if (!hostdata) { |
| 106 | dev_printk(KERN_ERR, dev, "Failed to allocate host data\n"); | 106 | dev_printk(KERN_ERR, &dev->dev, "Failed to allocate host data\n"); |
| 107 | return -ENOMEM; | 107 | return -ENOMEM; |
| 108 | } | 108 | } |
| 109 | 109 | ||
diff --git a/drivers/scsi/libfc/fc_disc.c b/drivers/scsi/libfc/fc_disc.c index dd1564c9e04a..e57556ea5b48 100644 --- a/drivers/scsi/libfc/fc_disc.c +++ b/drivers/scsi/libfc/fc_disc.c | |||
| @@ -64,7 +64,7 @@ static void fc_disc_single(struct fc_disc *, struct fc_disc_port *); | |||
| 64 | static void fc_disc_restart(struct fc_disc *); | 64 | static void fc_disc_restart(struct fc_disc *); |
| 65 | 65 | ||
| 66 | /** | 66 | /** |
| 67 | * fc_disc_lookup_rport - lookup a remote port by port_id | 67 | * fc_disc_lookup_rport() - lookup a remote port by port_id |
| 68 | * @lport: Fibre Channel host port instance | 68 | * @lport: Fibre Channel host port instance |
| 69 | * @port_id: remote port port_id to match | 69 | * @port_id: remote port port_id to match |
| 70 | */ | 70 | */ |
| @@ -92,7 +92,7 @@ struct fc_rport *fc_disc_lookup_rport(const struct fc_lport *lport, | |||
| 92 | } | 92 | } |
| 93 | 93 | ||
| 94 | /** | 94 | /** |
| 95 | * fc_disc_stop_rports - delete all the remote ports associated with the lport | 95 | * fc_disc_stop_rports() - delete all the remote ports associated with the lport |
| 96 | * @disc: The discovery job to stop rports on | 96 | * @disc: The discovery job to stop rports on |
| 97 | * | 97 | * |
| 98 | * Locking Note: This function expects that the lport mutex is locked before | 98 | * Locking Note: This function expects that the lport mutex is locked before |
| @@ -117,7 +117,7 @@ void fc_disc_stop_rports(struct fc_disc *disc) | |||
| 117 | } | 117 | } |
| 118 | 118 | ||
| 119 | /** | 119 | /** |
| 120 | * fc_disc_rport_callback - Event handler for rport events | 120 | * fc_disc_rport_callback() - Event handler for rport events |
| 121 | * @lport: The lport which is receiving the event | 121 | * @lport: The lport which is receiving the event |
| 122 | * @rport: The rport which the event has occured on | 122 | * @rport: The rport which the event has occured on |
| 123 | * @event: The event that occured | 123 | * @event: The event that occured |
| @@ -151,7 +151,7 @@ static void fc_disc_rport_callback(struct fc_lport *lport, | |||
| 151 | } | 151 | } |
| 152 | 152 | ||
| 153 | /** | 153 | /** |
| 154 | * fc_disc_recv_rscn_req - Handle Registered State Change Notification (RSCN) | 154 | * fc_disc_recv_rscn_req() - Handle Registered State Change Notification (RSCN) |
| 155 | * @sp: Current sequence of the RSCN exchange | 155 | * @sp: Current sequence of the RSCN exchange |
| 156 | * @fp: RSCN Frame | 156 | * @fp: RSCN Frame |
| 157 | * @lport: Fibre Channel host port instance | 157 | * @lport: Fibre Channel host port instance |
| @@ -246,7 +246,7 @@ static void fc_disc_recv_rscn_req(struct fc_seq *sp, struct fc_frame *fp, | |||
| 246 | list_del(&dp->peers); | 246 | list_del(&dp->peers); |
| 247 | rport = lport->tt.rport_lookup(lport, dp->ids.port_id); | 247 | rport = lport->tt.rport_lookup(lport, dp->ids.port_id); |
| 248 | if (rport) { | 248 | if (rport) { |
| 249 | rdata = RPORT_TO_PRIV(rport); | 249 | rdata = rport->dd_data; |
| 250 | list_del(&rdata->peers); | 250 | list_del(&rdata->peers); |
| 251 | lport->tt.rport_logoff(rport); | 251 | lport->tt.rport_logoff(rport); |
| 252 | } | 252 | } |
| @@ -265,7 +265,7 @@ reject: | |||
| 265 | } | 265 | } |
| 266 | 266 | ||
| 267 | /** | 267 | /** |
| 268 | * fc_disc_recv_req - Handle incoming requests | 268 | * fc_disc_recv_req() - Handle incoming requests |
| 269 | * @sp: Current sequence of the request exchange | 269 | * @sp: Current sequence of the request exchange |
| 270 | * @fp: The frame | 270 | * @fp: The frame |
| 271 | * @lport: The FC local port | 271 | * @lport: The FC local port |
| @@ -294,7 +294,7 @@ static void fc_disc_recv_req(struct fc_seq *sp, struct fc_frame *fp, | |||
| 294 | } | 294 | } |
| 295 | 295 | ||
| 296 | /** | 296 | /** |
| 297 | * fc_disc_restart - Restart discovery | 297 | * fc_disc_restart() - Restart discovery |
| 298 | * @lport: FC discovery context | 298 | * @lport: FC discovery context |
| 299 | * | 299 | * |
| 300 | * Locking Note: This function expects that the disc mutex | 300 | * Locking Note: This function expects that the disc mutex |
| @@ -322,7 +322,7 @@ static void fc_disc_restart(struct fc_disc *disc) | |||
| 322 | } | 322 | } |
| 323 | 323 | ||
| 324 | /** | 324 | /** |
| 325 | * fc_disc_start - Fibre Channel Target discovery | 325 | * fc_disc_start() - Fibre Channel Target discovery |
| 326 | * @lport: FC local port | 326 | * @lport: FC local port |
| 327 | * | 327 | * |
| 328 | * Returns non-zero if discovery cannot be started. | 328 | * Returns non-zero if discovery cannot be started. |
| @@ -383,7 +383,7 @@ static struct fc_rport_operations fc_disc_rport_ops = { | |||
| 383 | }; | 383 | }; |
| 384 | 384 | ||
| 385 | /** | 385 | /** |
| 386 | * fc_disc_new_target - Handle new target found by discovery | 386 | * fc_disc_new_target() - Handle new target found by discovery |
| 387 | * @lport: FC local port | 387 | * @lport: FC local port |
| 388 | * @rport: The previous FC remote port (NULL if new remote port) | 388 | * @rport: The previous FC remote port (NULL if new remote port) |
| 389 | * @ids: Identifiers for the new FC remote port | 389 | * @ids: Identifiers for the new FC remote port |
| @@ -396,7 +396,7 @@ static int fc_disc_new_target(struct fc_disc *disc, | |||
| 396 | struct fc_rport_identifiers *ids) | 396 | struct fc_rport_identifiers *ids) |
| 397 | { | 397 | { |
| 398 | struct fc_lport *lport = disc->lport; | 398 | struct fc_lport *lport = disc->lport; |
| 399 | struct fc_rport_libfc_priv *rp; | 399 | struct fc_rport_libfc_priv *rdata; |
| 400 | int error = 0; | 400 | int error = 0; |
| 401 | 401 | ||
| 402 | if (rport && ids->port_name) { | 402 | if (rport && ids->port_name) { |
| @@ -430,15 +430,15 @@ static int fc_disc_new_target(struct fc_disc *disc, | |||
| 430 | dp.ids.port_name = ids->port_name; | 430 | dp.ids.port_name = ids->port_name; |
| 431 | dp.ids.node_name = ids->node_name; | 431 | dp.ids.node_name = ids->node_name; |
| 432 | dp.ids.roles = ids->roles; | 432 | dp.ids.roles = ids->roles; |
| 433 | rport = fc_rport_rogue_create(&dp); | 433 | rport = lport->tt.rport_create(&dp); |
| 434 | } | 434 | } |
| 435 | if (!rport) | 435 | if (!rport) |
| 436 | error = -ENOMEM; | 436 | error = -ENOMEM; |
| 437 | } | 437 | } |
| 438 | if (rport) { | 438 | if (rport) { |
| 439 | rp = rport->dd_data; | 439 | rdata = rport->dd_data; |
| 440 | rp->ops = &fc_disc_rport_ops; | 440 | rdata->ops = &fc_disc_rport_ops; |
| 441 | rp->rp_state = RPORT_ST_INIT; | 441 | rdata->rp_state = RPORT_ST_INIT; |
| 442 | lport->tt.rport_login(rport); | 442 | lport->tt.rport_login(rport); |
| 443 | } | 443 | } |
| 444 | } | 444 | } |
| @@ -446,20 +446,20 @@ static int fc_disc_new_target(struct fc_disc *disc, | |||
| 446 | } | 446 | } |
| 447 | 447 | ||
| 448 | /** | 448 | /** |
| 449 | * fc_disc_del_target - Delete a target | 449 | * fc_disc_del_target() - Delete a target |
| 450 | * @disc: FC discovery context | 450 | * @disc: FC discovery context |
| 451 | * @rport: The remote port to be removed | 451 | * @rport: The remote port to be removed |
| 452 | */ | 452 | */ |
| 453 | static void fc_disc_del_target(struct fc_disc *disc, struct fc_rport *rport) | 453 | static void fc_disc_del_target(struct fc_disc *disc, struct fc_rport *rport) |
| 454 | { | 454 | { |
| 455 | struct fc_lport *lport = disc->lport; | 455 | struct fc_lport *lport = disc->lport; |
| 456 | struct fc_rport_libfc_priv *rdata = RPORT_TO_PRIV(rport); | 456 | struct fc_rport_libfc_priv *rdata = rport->dd_data; |
| 457 | list_del(&rdata->peers); | 457 | list_del(&rdata->peers); |
| 458 | lport->tt.rport_logoff(rport); | 458 | lport->tt.rport_logoff(rport); |
| 459 | } | 459 | } |
| 460 | 460 | ||
| 461 | /** | 461 | /** |
| 462 | * fc_disc_done - Discovery has been completed | 462 | * fc_disc_done() - Discovery has been completed |
| 463 | * @disc: FC discovery context | 463 | * @disc: FC discovery context |
| 464 | */ | 464 | */ |
| 465 | static void fc_disc_done(struct fc_disc *disc) | 465 | static void fc_disc_done(struct fc_disc *disc) |
| @@ -479,7 +479,7 @@ static void fc_disc_done(struct fc_disc *disc) | |||
| 479 | } | 479 | } |
| 480 | 480 | ||
| 481 | /** | 481 | /** |
| 482 | * fc_disc_error - Handle error on dNS request | 482 | * fc_disc_error() - Handle error on dNS request |
| 483 | * @disc: FC discovery context | 483 | * @disc: FC discovery context |
| 484 | * @fp: The frame pointer | 484 | * @fp: The frame pointer |
| 485 | */ | 485 | */ |
| @@ -519,7 +519,7 @@ static void fc_disc_error(struct fc_disc *disc, struct fc_frame *fp) | |||
| 519 | } | 519 | } |
| 520 | 520 | ||
| 521 | /** | 521 | /** |
| 522 | * fc_disc_gpn_ft_req - Send Get Port Names by FC-4 type (GPN_FT) request | 522 | * fc_disc_gpn_ft_req() - Send Get Port Names by FC-4 type (GPN_FT) request |
| 523 | * @lport: FC discovery context | 523 | * @lport: FC discovery context |
| 524 | * | 524 | * |
| 525 | * Locking Note: This function expects that the disc_mutex is locked | 525 | * Locking Note: This function expects that the disc_mutex is locked |
| @@ -553,7 +553,7 @@ err: | |||
| 553 | } | 553 | } |
| 554 | 554 | ||
| 555 | /** | 555 | /** |
| 556 | * fc_disc_gpn_ft_parse - Parse the list of IDs and names resulting from a request | 556 | * fc_disc_gpn_ft_parse() - Parse the list of IDs and names resulting from a request |
| 557 | * @lport: Fibre Channel host port instance | 557 | * @lport: Fibre Channel host port instance |
| 558 | * @buf: GPN_FT response buffer | 558 | * @buf: GPN_FT response buffer |
| 559 | * @len: size of response buffer | 559 | * @len: size of response buffer |
| @@ -617,7 +617,7 @@ static int fc_disc_gpn_ft_parse(struct fc_disc *disc, void *buf, size_t len) | |||
| 617 | 617 | ||
| 618 | if ((dp.ids.port_id != fc_host_port_id(lport->host)) && | 618 | if ((dp.ids.port_id != fc_host_port_id(lport->host)) && |
| 619 | (dp.ids.port_name != lport->wwpn)) { | 619 | (dp.ids.port_name != lport->wwpn)) { |
| 620 | rport = fc_rport_rogue_create(&dp); | 620 | rport = lport->tt.rport_create(&dp); |
| 621 | if (rport) { | 621 | if (rport) { |
| 622 | rdata = rport->dd_data; | 622 | rdata = rport->dd_data; |
| 623 | rdata->ops = &fc_disc_rport_ops; | 623 | rdata->ops = &fc_disc_rport_ops; |
| @@ -658,7 +658,10 @@ static int fc_disc_gpn_ft_parse(struct fc_disc *disc, void *buf, size_t len) | |||
| 658 | return error; | 658 | return error; |
| 659 | } | 659 | } |
| 660 | 660 | ||
| 661 | /* | 661 | /** |
| 662 | * fc_disc_timeout() - Retry handler for the disc component | ||
| 663 | * @work: Structure holding disc obj that needs retry discovery | ||
| 664 | * | ||
| 662 | * Handle retry of memory allocation for remote ports. | 665 | * Handle retry of memory allocation for remote ports. |
| 663 | */ | 666 | */ |
| 664 | static void fc_disc_timeout(struct work_struct *work) | 667 | static void fc_disc_timeout(struct work_struct *work) |
| @@ -673,7 +676,7 @@ static void fc_disc_timeout(struct work_struct *work) | |||
| 673 | } | 676 | } |
| 674 | 677 | ||
| 675 | /** | 678 | /** |
| 676 | * fc_disc_gpn_ft_resp - Handle a response frame from Get Port Names (GPN_FT) | 679 | * fc_disc_gpn_ft_resp() - Handle a response frame from Get Port Names (GPN_FT) |
| 677 | * @sp: Current sequence of GPN_FT exchange | 680 | * @sp: Current sequence of GPN_FT exchange |
| 678 | * @fp: response frame | 681 | * @fp: response frame |
| 679 | * @lp_arg: Fibre Channel host port instance | 682 | * @lp_arg: Fibre Channel host port instance |
| @@ -712,9 +715,7 @@ static void fc_disc_gpn_ft_resp(struct fc_seq *sp, struct fc_frame *fp, | |||
| 712 | fr_len(fp)); | 715 | fr_len(fp)); |
| 713 | } else if (ntohs(cp->ct_cmd) == FC_FS_ACC) { | 716 | } else if (ntohs(cp->ct_cmd) == FC_FS_ACC) { |
| 714 | 717 | ||
| 715 | /* | 718 | /* Accepted, parse the response. */ |
| 716 | * Accepted. Parse response. | ||
| 717 | */ | ||
| 718 | buf = cp + 1; | 719 | buf = cp + 1; |
| 719 | len -= sizeof(*cp); | 720 | len -= sizeof(*cp); |
| 720 | } else if (ntohs(cp->ct_cmd) == FC_FS_RJT) { | 721 | } else if (ntohs(cp->ct_cmd) == FC_FS_RJT) { |
| @@ -746,7 +747,7 @@ static void fc_disc_gpn_ft_resp(struct fc_seq *sp, struct fc_frame *fp, | |||
| 746 | } | 747 | } |
| 747 | 748 | ||
| 748 | /** | 749 | /** |
| 749 | * fc_disc_single - Discover the directory information for a single target | 750 | * fc_disc_single() - Discover the directory information for a single target |
| 750 | * @lport: FC local port | 751 | * @lport: FC local port |
| 751 | * @dp: The port to rediscover | 752 | * @dp: The port to rediscover |
| 752 | * | 753 | * |
| @@ -769,7 +770,7 @@ static void fc_disc_single(struct fc_disc *disc, struct fc_disc_port *dp) | |||
| 769 | if (rport) | 770 | if (rport) |
| 770 | fc_disc_del_target(disc, rport); | 771 | fc_disc_del_target(disc, rport); |
| 771 | 772 | ||
| 772 | new_rport = fc_rport_rogue_create(dp); | 773 | new_rport = lport->tt.rport_create(dp); |
| 773 | if (new_rport) { | 774 | if (new_rport) { |
| 774 | rdata = new_rport->dd_data; | 775 | rdata = new_rport->dd_data; |
| 775 | rdata->ops = &fc_disc_rport_ops; | 776 | rdata->ops = &fc_disc_rport_ops; |
| @@ -782,7 +783,7 @@ out: | |||
| 782 | } | 783 | } |
| 783 | 784 | ||
| 784 | /** | 785 | /** |
| 785 | * fc_disc_stop - Stop discovery for a given lport | 786 | * fc_disc_stop() - Stop discovery for a given lport |
| 786 | * @lport: The lport that discovery should stop for | 787 | * @lport: The lport that discovery should stop for |
| 787 | */ | 788 | */ |
| 788 | void fc_disc_stop(struct fc_lport *lport) | 789 | void fc_disc_stop(struct fc_lport *lport) |
| @@ -796,7 +797,7 @@ void fc_disc_stop(struct fc_lport *lport) | |||
| 796 | } | 797 | } |
| 797 | 798 | ||
| 798 | /** | 799 | /** |
| 799 | * fc_disc_stop_final - Stop discovery for a given lport | 800 | * fc_disc_stop_final() - Stop discovery for a given lport |
| 800 | * @lport: The lport that discovery should stop for | 801 | * @lport: The lport that discovery should stop for |
| 801 | * | 802 | * |
| 802 | * This function will block until discovery has been | 803 | * This function will block until discovery has been |
| @@ -809,7 +810,7 @@ void fc_disc_stop_final(struct fc_lport *lport) | |||
| 809 | } | 810 | } |
| 810 | 811 | ||
| 811 | /** | 812 | /** |
| 812 | * fc_disc_init - Initialize the discovery block | 813 | * fc_disc_init() - Initialize the discovery block |
| 813 | * @lport: FC local port | 814 | * @lport: FC local port |
| 814 | */ | 815 | */ |
| 815 | int fc_disc_init(struct fc_lport *lport) | 816 | int fc_disc_init(struct fc_lport *lport) |
diff --git a/drivers/scsi/libfc/fc_exch.c b/drivers/scsi/libfc/fc_exch.c index 66db08a5f27f..505825b6124d 100644 --- a/drivers/scsi/libfc/fc_exch.c +++ b/drivers/scsi/libfc/fc_exch.c | |||
| @@ -32,8 +32,6 @@ | |||
| 32 | #include <scsi/libfc.h> | 32 | #include <scsi/libfc.h> |
| 33 | #include <scsi/fc_encode.h> | 33 | #include <scsi/fc_encode.h> |
| 34 | 34 | ||
| 35 | #define FC_DEF_R_A_TOV (10 * 1000) /* resource allocation timeout */ | ||
| 36 | |||
| 37 | /* | 35 | /* |
| 38 | * fc_exch_debug can be set in debugger or at compile time to get more logs. | 36 | * fc_exch_debug can be set in debugger or at compile time to get more logs. |
| 39 | */ | 37 | */ |
| @@ -627,7 +625,6 @@ static struct fc_exch *fc_exch_resp(struct fc_exch_mgr *mp, struct fc_frame *fp) | |||
| 627 | { | 625 | { |
| 628 | struct fc_exch *ep; | 626 | struct fc_exch *ep; |
| 629 | struct fc_frame_header *fh; | 627 | struct fc_frame_header *fh; |
| 630 | u16 rxid; | ||
| 631 | 628 | ||
| 632 | ep = mp->lp->tt.exch_get(mp->lp, fp); | 629 | ep = mp->lp->tt.exch_get(mp->lp, fp); |
| 633 | if (ep) { | 630 | if (ep) { |
| @@ -654,18 +651,6 @@ static struct fc_exch *fc_exch_resp(struct fc_exch_mgr *mp, struct fc_frame *fp) | |||
| 654 | if ((ntoh24(fh->fh_f_ctl) & FC_FC_SEQ_INIT) == 0) | 651 | if ((ntoh24(fh->fh_f_ctl) & FC_FC_SEQ_INIT) == 0) |
| 655 | ep->esb_stat &= ~ESB_ST_SEQ_INIT; | 652 | ep->esb_stat &= ~ESB_ST_SEQ_INIT; |
| 656 | 653 | ||
| 657 | /* | ||
| 658 | * Set the responder ID in the frame header. | ||
| 659 | * The old one should've been 0xffff. | ||
| 660 | * If it isn't, don't assign one. | ||
| 661 | * Incoming basic link service frames may specify | ||
| 662 | * a referenced RX_ID. | ||
| 663 | */ | ||
| 664 | if (fh->fh_type != FC_TYPE_BLS) { | ||
| 665 | rxid = ntohs(fh->fh_rx_id); | ||
| 666 | WARN_ON(rxid != FC_XID_UNKNOWN); | ||
| 667 | fh->fh_rx_id = htons(ep->rxid); | ||
| 668 | } | ||
| 669 | fc_exch_hold(ep); /* hold for caller */ | 654 | fc_exch_hold(ep); /* hold for caller */ |
| 670 | spin_unlock_bh(&ep->ex_lock); /* lock from exch_get */ | 655 | spin_unlock_bh(&ep->ex_lock); /* lock from exch_get */ |
| 671 | } | 656 | } |
| @@ -677,8 +662,8 @@ static struct fc_exch *fc_exch_resp(struct fc_exch_mgr *mp, struct fc_frame *fp) | |||
| 677 | * If fc_pf_rjt_reason is FC_RJT_NONE then this function will have a hold | 662 | * If fc_pf_rjt_reason is FC_RJT_NONE then this function will have a hold |
| 678 | * on the ep that should be released by the caller. | 663 | * on the ep that should be released by the caller. |
| 679 | */ | 664 | */ |
| 680 | static enum fc_pf_rjt_reason | 665 | static enum fc_pf_rjt_reason fc_seq_lookup_recip(struct fc_exch_mgr *mp, |
| 681 | fc_seq_lookup_recip(struct fc_exch_mgr *mp, struct fc_frame *fp) | 666 | struct fc_frame *fp) |
| 682 | { | 667 | { |
| 683 | struct fc_frame_header *fh = fc_frame_header_get(fp); | 668 | struct fc_frame_header *fh = fc_frame_header_get(fp); |
| 684 | struct fc_exch *ep = NULL; | 669 | struct fc_exch *ep = NULL; |
| @@ -996,9 +981,9 @@ static void fc_seq_send_ack(struct fc_seq *sp, const struct fc_frame *rx_fp) | |||
| 996 | * Send BLS Reject. | 981 | * Send BLS Reject. |
| 997 | * This is for rejecting BA_ABTS only. | 982 | * This is for rejecting BA_ABTS only. |
| 998 | */ | 983 | */ |
| 999 | static void | 984 | static void fc_exch_send_ba_rjt(struct fc_frame *rx_fp, |
| 1000 | fc_exch_send_ba_rjt(struct fc_frame *rx_fp, enum fc_ba_rjt_reason reason, | 985 | enum fc_ba_rjt_reason reason, |
| 1001 | enum fc_ba_rjt_explan explan) | 986 | enum fc_ba_rjt_explan explan) |
| 1002 | { | 987 | { |
| 1003 | struct fc_frame *fp; | 988 | struct fc_frame *fp; |
| 1004 | struct fc_frame_header *rx_fh; | 989 | struct fc_frame_header *rx_fh; |
| @@ -1096,7 +1081,7 @@ static void fc_exch_recv_abts(struct fc_exch *ep, struct fc_frame *rx_fp) | |||
| 1096 | ap->ba_high_seq_cnt = fh->fh_seq_cnt; | 1081 | ap->ba_high_seq_cnt = fh->fh_seq_cnt; |
| 1097 | ap->ba_low_seq_cnt = htons(sp->cnt); | 1082 | ap->ba_low_seq_cnt = htons(sp->cnt); |
| 1098 | } | 1083 | } |
| 1099 | sp = fc_seq_start_next(sp); | 1084 | sp = fc_seq_start_next_locked(sp); |
| 1100 | spin_unlock_bh(&ep->ex_lock); | 1085 | spin_unlock_bh(&ep->ex_lock); |
| 1101 | fc_seq_send_last(sp, fp, FC_RCTL_BA_ACC, FC_TYPE_BLS); | 1086 | fc_seq_send_last(sp, fp, FC_RCTL_BA_ACC, FC_TYPE_BLS); |
| 1102 | fc_frame_free(rx_fp); | 1087 | fc_frame_free(rx_fp); |
| @@ -1480,10 +1465,11 @@ static void fc_exch_reset(struct fc_exch *ep) | |||
| 1480 | * If sid is non-zero, reset only exchanges we source from that FID. | 1465 | * If sid is non-zero, reset only exchanges we source from that FID. |
| 1481 | * If did is non-zero, reset only exchanges destined to that FID. | 1466 | * If did is non-zero, reset only exchanges destined to that FID. |
| 1482 | */ | 1467 | */ |
| 1483 | void fc_exch_mgr_reset(struct fc_exch_mgr *mp, u32 sid, u32 did) | 1468 | void fc_exch_mgr_reset(struct fc_lport *lp, u32 sid, u32 did) |
| 1484 | { | 1469 | { |
| 1485 | struct fc_exch *ep; | 1470 | struct fc_exch *ep; |
| 1486 | struct fc_exch *next; | 1471 | struct fc_exch *next; |
| 1472 | struct fc_exch_mgr *mp = lp->emp; | ||
| 1487 | 1473 | ||
| 1488 | spin_lock_bh(&mp->em_lock); | 1474 | spin_lock_bh(&mp->em_lock); |
| 1489 | restart: | 1475 | restart: |
| @@ -1607,7 +1593,7 @@ static void fc_exch_rrq_resp(struct fc_seq *sp, struct fc_frame *fp, void *arg) | |||
| 1607 | if (IS_ERR(fp)) { | 1593 | if (IS_ERR(fp)) { |
| 1608 | int err = PTR_ERR(fp); | 1594 | int err = PTR_ERR(fp); |
| 1609 | 1595 | ||
| 1610 | if (err == -FC_EX_CLOSED) | 1596 | if (err == -FC_EX_CLOSED || err == -FC_EX_TIMEOUT) |
| 1611 | goto cleanup; | 1597 | goto cleanup; |
| 1612 | FC_DBG("Cannot process RRQ, because of frame error %d\n", err); | 1598 | FC_DBG("Cannot process RRQ, because of frame error %d\n", err); |
| 1613 | return; | 1599 | return; |
diff --git a/drivers/scsi/libfc/fc_fcp.c b/drivers/scsi/libfc/fc_fcp.c index 404e63ff46b8..2a631d7dbcec 100644 --- a/drivers/scsi/libfc/fc_fcp.c +++ b/drivers/scsi/libfc/fc_fcp.c | |||
| @@ -161,7 +161,7 @@ static struct fc_fcp_pkt *fc_fcp_pkt_alloc(struct fc_lport *lp, gfp_t gfp) | |||
| 161 | } | 161 | } |
| 162 | 162 | ||
| 163 | /** | 163 | /** |
| 164 | * fc_fcp_pkt_release - release hold on scsi_pkt packet | 164 | * fc_fcp_pkt_release() - release hold on scsi_pkt packet |
| 165 | * @fsp: fcp packet struct | 165 | * @fsp: fcp packet struct |
| 166 | * | 166 | * |
| 167 | * This is used by upper layer scsi driver. | 167 | * This is used by upper layer scsi driver. |
| @@ -183,8 +183,7 @@ static void fc_fcp_pkt_hold(struct fc_fcp_pkt *fsp) | |||
| 183 | } | 183 | } |
| 184 | 184 | ||
| 185 | /** | 185 | /** |
| 186 | * fc_fcp_pkt_destory - release hold on scsi_pkt packet | 186 | * fc_fcp_pkt_destory() - release hold on scsi_pkt packet |
| 187 | * | ||
| 188 | * @seq: exchange sequence | 187 | * @seq: exchange sequence |
| 189 | * @fsp: fcp packet struct | 188 | * @fsp: fcp packet struct |
| 190 | * | 189 | * |
| @@ -199,7 +198,7 @@ static void fc_fcp_pkt_destroy(struct fc_seq *seq, void *fsp) | |||
| 199 | } | 198 | } |
| 200 | 199 | ||
| 201 | /** | 200 | /** |
| 202 | * fc_fcp_lock_pkt - lock a packet and get a ref to it. | 201 | * fc_fcp_lock_pkt() - lock a packet and get a ref to it. |
| 203 | * @fsp: fcp packet | 202 | * @fsp: fcp packet |
| 204 | * | 203 | * |
| 205 | * We should only return error if we return a command to scsi-ml before | 204 | * We should only return error if we return a command to scsi-ml before |
| @@ -291,9 +290,7 @@ static void fc_fcp_recv_data(struct fc_fcp_pkt *fsp, struct fc_frame *fp) | |||
| 291 | buf = fc_frame_payload_get(fp, 0); | 290 | buf = fc_frame_payload_get(fp, 0); |
| 292 | 291 | ||
| 293 | if (offset + len > fsp->data_len) { | 292 | if (offset + len > fsp->data_len) { |
| 294 | /* | 293 | /* this should never happen */ |
| 295 | * this should never happen | ||
| 296 | */ | ||
| 297 | if ((fr_flags(fp) & FCPHF_CRC_UNCHECKED) && | 294 | if ((fr_flags(fp) & FCPHF_CRC_UNCHECKED) && |
| 298 | fc_frame_crc_check(fp)) | 295 | fc_frame_crc_check(fp)) |
| 299 | goto crc_err; | 296 | goto crc_err; |
| @@ -387,8 +384,8 @@ crc_err: | |||
| 387 | fc_fcp_complete_locked(fsp); | 384 | fc_fcp_complete_locked(fsp); |
| 388 | } | 385 | } |
| 389 | 386 | ||
| 390 | /* | 387 | /** |
| 391 | * fc_fcp_send_data - Send SCSI data to target. | 388 | * fc_fcp_send_data() - Send SCSI data to target. |
| 392 | * @fsp: ptr to fc_fcp_pkt | 389 | * @fsp: ptr to fc_fcp_pkt |
| 393 | * @sp: ptr to this sequence | 390 | * @sp: ptr to this sequence |
| 394 | * @offset: starting offset for this data request | 391 | * @offset: starting offset for this data request |
| @@ -610,8 +607,8 @@ static void fc_fcp_abts_resp(struct fc_fcp_pkt *fsp, struct fc_frame *fp) | |||
| 610 | } | 607 | } |
| 611 | } | 608 | } |
| 612 | 609 | ||
| 613 | /* | 610 | /** |
| 614 | * fc_fcp_reduce_can_queue - drop can_queue | 611 | * fc_fcp_reduce_can_queue() - drop can_queue |
| 615 | * @lp: lport to drop queueing for | 612 | * @lp: lport to drop queueing for |
| 616 | * | 613 | * |
| 617 | * If we are getting memory allocation failures, then we may | 614 | * If we are getting memory allocation failures, then we may |
| @@ -642,9 +639,11 @@ done: | |||
| 642 | spin_unlock_irqrestore(lp->host->host_lock, flags); | 639 | spin_unlock_irqrestore(lp->host->host_lock, flags); |
| 643 | } | 640 | } |
| 644 | 641 | ||
| 645 | /* | 642 | /** |
| 646 | * exch mgr calls this routine to process scsi | 643 | * fc_fcp_recv() - Reveive FCP frames |
| 647 | * exchanges. | 644 | * @seq: The sequence the frame is on |
| 645 | * @fp: The FC frame | ||
| 646 | * @arg: The related FCP packet | ||
| 648 | * | 647 | * |
| 649 | * Return : None | 648 | * Return : None |
| 650 | * Context : called from Soft IRQ context | 649 | * Context : called from Soft IRQ context |
| @@ -832,7 +831,7 @@ err: | |||
| 832 | } | 831 | } |
| 833 | 832 | ||
| 834 | /** | 833 | /** |
| 835 | * fc_fcp_complete_locked - complete processing of a fcp packet | 834 | * fc_fcp_complete_locked() - complete processing of a fcp packet |
| 836 | * @fsp: fcp packet | 835 | * @fsp: fcp packet |
| 837 | * | 836 | * |
| 838 | * This function may sleep if a timer is pending. The packet lock must be | 837 | * This function may sleep if a timer is pending. The packet lock must be |
| @@ -900,7 +899,7 @@ static void fc_fcp_cleanup_cmd(struct fc_fcp_pkt *fsp, int error) | |||
| 900 | } | 899 | } |
| 901 | 900 | ||
| 902 | /** | 901 | /** |
| 903 | * fc_fcp_cleanup_each_cmd - run fn on each active command | 902 | * fc_fcp_cleanup_each_cmd() - Cleanup active commads |
| 904 | * @lp: logical port | 903 | * @lp: logical port |
| 905 | * @id: target id | 904 | * @id: target id |
| 906 | * @lun: lun | 905 | * @lun: lun |
| @@ -952,7 +951,7 @@ static void fc_fcp_abort_io(struct fc_lport *lp) | |||
| 952 | } | 951 | } |
| 953 | 952 | ||
| 954 | /** | 953 | /** |
| 955 | * fc_fcp_pkt_send - send a fcp packet to the lower level. | 954 | * fc_fcp_pkt_send() - send a fcp packet to the lower level. |
| 956 | * @lp: fc lport | 955 | * @lp: fc lport |
| 957 | * @fsp: fc packet. | 956 | * @fsp: fc packet. |
| 958 | * | 957 | * |
| @@ -1621,7 +1620,7 @@ out: | |||
| 1621 | static inline int fc_fcp_lport_queue_ready(struct fc_lport *lp) | 1620 | static inline int fc_fcp_lport_queue_ready(struct fc_lport *lp) |
| 1622 | { | 1621 | { |
| 1623 | /* lock ? */ | 1622 | /* lock ? */ |
| 1624 | return (lp->state == LPORT_ST_READY) && (lp->link_status & FC_LINK_UP); | 1623 | return (lp->state == LPORT_ST_READY) && lp->link_up && !lp->qfull; |
| 1625 | } | 1624 | } |
| 1626 | 1625 | ||
| 1627 | /** | 1626 | /** |
| @@ -1727,7 +1726,7 @@ out: | |||
| 1727 | EXPORT_SYMBOL(fc_queuecommand); | 1726 | EXPORT_SYMBOL(fc_queuecommand); |
| 1728 | 1727 | ||
| 1729 | /** | 1728 | /** |
| 1730 | * fc_io_compl - Handle responses for completed commands | 1729 | * fc_io_compl() - Handle responses for completed commands |
| 1731 | * @fsp: scsi packet | 1730 | * @fsp: scsi packet |
| 1732 | * | 1731 | * |
| 1733 | * Translates a error to a Linux SCSI error. | 1732 | * Translates a error to a Linux SCSI error. |
| @@ -1810,12 +1809,12 @@ static void fc_io_compl(struct fc_fcp_pkt *fsp) | |||
| 1810 | sc_cmd->result = DID_ERROR << 16; | 1809 | sc_cmd->result = DID_ERROR << 16; |
| 1811 | break; | 1810 | break; |
| 1812 | case FC_DATA_UNDRUN: | 1811 | case FC_DATA_UNDRUN: |
| 1813 | if (fsp->cdb_status == 0) { | 1812 | if ((fsp->cdb_status == 0) && !(fsp->req_flags & FC_SRB_READ)) { |
| 1814 | /* | 1813 | /* |
| 1815 | * scsi status is good but transport level | 1814 | * scsi status is good but transport level |
| 1816 | * underrun. for read it should be an error?? | 1815 | * underrun. |
| 1817 | */ | 1816 | */ |
| 1818 | sc_cmd->result = (DID_OK << 16) | fsp->cdb_status; | 1817 | sc_cmd->result = DID_OK << 16; |
| 1819 | } else { | 1818 | } else { |
| 1820 | /* | 1819 | /* |
| 1821 | * scsi got underrun, this is an error | 1820 | * scsi got underrun, this is an error |
| @@ -1857,7 +1856,7 @@ static void fc_io_compl(struct fc_fcp_pkt *fsp) | |||
| 1857 | } | 1856 | } |
| 1858 | 1857 | ||
| 1859 | /** | 1858 | /** |
| 1860 | * fc_fcp_complete - complete processing of a fcp packet | 1859 | * fc_fcp_complete() - complete processing of a fcp packet |
| 1861 | * @fsp: fcp packet | 1860 | * @fsp: fcp packet |
| 1862 | * | 1861 | * |
| 1863 | * This function may sleep if a fsp timer is pending. | 1862 | * This function may sleep if a fsp timer is pending. |
| @@ -1874,9 +1873,10 @@ void fc_fcp_complete(struct fc_fcp_pkt *fsp) | |||
| 1874 | EXPORT_SYMBOL(fc_fcp_complete); | 1873 | EXPORT_SYMBOL(fc_fcp_complete); |
| 1875 | 1874 | ||
| 1876 | /** | 1875 | /** |
| 1877 | * fc_eh_abort - Abort a command...from scsi host template | 1876 | * fc_eh_abort() - Abort a command |
| 1878 | * @sc_cmd: scsi command to abort | 1877 | * @sc_cmd: scsi command to abort |
| 1879 | * | 1878 | * |
| 1879 | * From scsi host template. | ||
| 1880 | * send ABTS to the target device and wait for the response | 1880 | * send ABTS to the target device and wait for the response |
| 1881 | * sc_cmd is the pointer to the command to be aborted. | 1881 | * sc_cmd is the pointer to the command to be aborted. |
| 1882 | */ | 1882 | */ |
| @@ -1890,7 +1890,7 @@ int fc_eh_abort(struct scsi_cmnd *sc_cmd) | |||
| 1890 | lp = shost_priv(sc_cmd->device->host); | 1890 | lp = shost_priv(sc_cmd->device->host); |
| 1891 | if (lp->state != LPORT_ST_READY) | 1891 | if (lp->state != LPORT_ST_READY) |
| 1892 | return rc; | 1892 | return rc; |
| 1893 | else if (!(lp->link_status & FC_LINK_UP)) | 1893 | else if (!lp->link_up) |
| 1894 | return rc; | 1894 | return rc; |
| 1895 | 1895 | ||
| 1896 | spin_lock_irqsave(lp->host->host_lock, flags); | 1896 | spin_lock_irqsave(lp->host->host_lock, flags); |
| @@ -1920,7 +1920,7 @@ release_pkt: | |||
| 1920 | EXPORT_SYMBOL(fc_eh_abort); | 1920 | EXPORT_SYMBOL(fc_eh_abort); |
| 1921 | 1921 | ||
| 1922 | /** | 1922 | /** |
| 1923 | * fc_eh_device_reset: Reset a single LUN | 1923 | * fc_eh_device_reset() Reset a single LUN |
| 1924 | * @sc_cmd: scsi command | 1924 | * @sc_cmd: scsi command |
| 1925 | * | 1925 | * |
| 1926 | * Set from scsi host template to send tm cmd to the target and wait for the | 1926 | * Set from scsi host template to send tm cmd to the target and wait for the |
| @@ -1973,7 +1973,7 @@ out: | |||
| 1973 | EXPORT_SYMBOL(fc_eh_device_reset); | 1973 | EXPORT_SYMBOL(fc_eh_device_reset); |
| 1974 | 1974 | ||
| 1975 | /** | 1975 | /** |
| 1976 | * fc_eh_host_reset - The reset function will reset the ports on the host. | 1976 | * fc_eh_host_reset() - The reset function will reset the ports on the host. |
| 1977 | * @sc_cmd: scsi command | 1977 | * @sc_cmd: scsi command |
| 1978 | */ | 1978 | */ |
| 1979 | int fc_eh_host_reset(struct scsi_cmnd *sc_cmd) | 1979 | int fc_eh_host_reset(struct scsi_cmnd *sc_cmd) |
| @@ -1999,7 +1999,7 @@ int fc_eh_host_reset(struct scsi_cmnd *sc_cmd) | |||
| 1999 | EXPORT_SYMBOL(fc_eh_host_reset); | 1999 | EXPORT_SYMBOL(fc_eh_host_reset); |
| 2000 | 2000 | ||
| 2001 | /** | 2001 | /** |
| 2002 | * fc_slave_alloc - configure queue depth | 2002 | * fc_slave_alloc() - configure queue depth |
| 2003 | * @sdev: scsi device | 2003 | * @sdev: scsi device |
| 2004 | * | 2004 | * |
| 2005 | * Configures queue depth based on host's cmd_per_len. If not set | 2005 | * Configures queue depth based on host's cmd_per_len. If not set |
diff --git a/drivers/scsi/libfc/fc_lport.c b/drivers/scsi/libfc/fc_lport.c index 0b9bdb1fb807..2ae50a1188e6 100644 --- a/drivers/scsi/libfc/fc_lport.c +++ b/drivers/scsi/libfc/fc_lport.c | |||
| @@ -139,7 +139,7 @@ static int fc_frame_drop(struct fc_lport *lport, struct fc_frame *fp) | |||
| 139 | } | 139 | } |
| 140 | 140 | ||
| 141 | /** | 141 | /** |
| 142 | * fc_lport_rport_callback - Event handler for rport events | 142 | * fc_lport_rport_callback() - Event handler for rport events |
| 143 | * @lport: The lport which is receiving the event | 143 | * @lport: The lport which is receiving the event |
| 144 | * @rport: The rport which the event has occured on | 144 | * @rport: The rport which the event has occured on |
| 145 | * @event: The event that occured | 145 | * @event: The event that occured |
| @@ -195,7 +195,7 @@ static void fc_lport_rport_callback(struct fc_lport *lport, | |||
| 195 | } | 195 | } |
| 196 | 196 | ||
| 197 | /** | 197 | /** |
| 198 | * fc_lport_state - Return a string which represents the lport's state | 198 | * fc_lport_state() - Return a string which represents the lport's state |
| 199 | * @lport: The lport whose state is to converted to a string | 199 | * @lport: The lport whose state is to converted to a string |
| 200 | */ | 200 | */ |
| 201 | static const char *fc_lport_state(struct fc_lport *lport) | 201 | static const char *fc_lport_state(struct fc_lport *lport) |
| @@ -209,7 +209,7 @@ static const char *fc_lport_state(struct fc_lport *lport) | |||
| 209 | } | 209 | } |
| 210 | 210 | ||
| 211 | /** | 211 | /** |
| 212 | * fc_lport_ptp_setup - Create an rport for point-to-point mode | 212 | * fc_lport_ptp_setup() - Create an rport for point-to-point mode |
| 213 | * @lport: The lport to attach the ptp rport to | 213 | * @lport: The lport to attach the ptp rport to |
| 214 | * @fid: The FID of the ptp rport | 214 | * @fid: The FID of the ptp rport |
| 215 | * @remote_wwpn: The WWPN of the ptp rport | 215 | * @remote_wwpn: The WWPN of the ptp rport |
| @@ -232,7 +232,7 @@ static void fc_lport_ptp_setup(struct fc_lport *lport, | |||
| 232 | lport->ptp_rp = NULL; | 232 | lport->ptp_rp = NULL; |
| 233 | } | 233 | } |
| 234 | 234 | ||
| 235 | lport->ptp_rp = fc_rport_rogue_create(&dp); | 235 | lport->ptp_rp = lport->tt.rport_create(&dp); |
| 236 | 236 | ||
| 237 | lport->tt.rport_login(lport->ptp_rp); | 237 | lport->tt.rport_login(lport->ptp_rp); |
| 238 | 238 | ||
| @@ -250,7 +250,7 @@ void fc_get_host_port_state(struct Scsi_Host *shost) | |||
| 250 | { | 250 | { |
| 251 | struct fc_lport *lp = shost_priv(shost); | 251 | struct fc_lport *lp = shost_priv(shost); |
| 252 | 252 | ||
| 253 | if ((lp->link_status & FC_LINK_UP) == FC_LINK_UP) | 253 | if (lp->link_up) |
| 254 | fc_host_port_state(shost) = FC_PORTSTATE_ONLINE; | 254 | fc_host_port_state(shost) = FC_PORTSTATE_ONLINE; |
| 255 | else | 255 | else |
| 256 | fc_host_port_state(shost) = FC_PORTSTATE_OFFLINE; | 256 | fc_host_port_state(shost) = FC_PORTSTATE_OFFLINE; |
| @@ -351,7 +351,7 @@ static void fc_lport_add_fc4_type(struct fc_lport *lport, enum fc_fh_type type) | |||
| 351 | } | 351 | } |
| 352 | 352 | ||
| 353 | /** | 353 | /** |
| 354 | * fc_lport_recv_rlir_req - Handle received Registered Link Incident Report. | 354 | * fc_lport_recv_rlir_req() - Handle received Registered Link Incident Report. |
| 355 | * @lport: Fibre Channel local port recieving the RLIR | 355 | * @lport: Fibre Channel local port recieving the RLIR |
| 356 | * @sp: current sequence in the RLIR exchange | 356 | * @sp: current sequence in the RLIR exchange |
| 357 | * @fp: RLIR request frame | 357 | * @fp: RLIR request frame |
| @@ -370,7 +370,7 @@ static void fc_lport_recv_rlir_req(struct fc_seq *sp, struct fc_frame *fp, | |||
| 370 | } | 370 | } |
| 371 | 371 | ||
| 372 | /** | 372 | /** |
| 373 | * fc_lport_recv_echo_req - Handle received ECHO request | 373 | * fc_lport_recv_echo_req() - Handle received ECHO request |
| 374 | * @lport: Fibre Channel local port recieving the ECHO | 374 | * @lport: Fibre Channel local port recieving the ECHO |
| 375 | * @sp: current sequence in the ECHO exchange | 375 | * @sp: current sequence in the ECHO exchange |
| 376 | * @fp: ECHO request frame | 376 | * @fp: ECHO request frame |
| @@ -412,7 +412,7 @@ static void fc_lport_recv_echo_req(struct fc_seq *sp, struct fc_frame *in_fp, | |||
| 412 | } | 412 | } |
| 413 | 413 | ||
| 414 | /** | 414 | /** |
| 415 | * fc_lport_recv_echo_req - Handle received Request Node ID data request | 415 | * fc_lport_recv_echo_req() - Handle received Request Node ID data request |
| 416 | * @lport: Fibre Channel local port recieving the RNID | 416 | * @lport: Fibre Channel local port recieving the RNID |
| 417 | * @sp: current sequence in the RNID exchange | 417 | * @sp: current sequence in the RNID exchange |
| 418 | * @fp: RNID request frame | 418 | * @fp: RNID request frame |
| @@ -479,7 +479,7 @@ static void fc_lport_recv_rnid_req(struct fc_seq *sp, struct fc_frame *in_fp, | |||
| 479 | } | 479 | } |
| 480 | 480 | ||
| 481 | /** | 481 | /** |
| 482 | * fc_lport_recv_adisc_req - Handle received Address Discovery Request | 482 | * fc_lport_recv_adisc_req() - Handle received Address Discovery Request |
| 483 | * @lport: Fibre Channel local port recieving the ADISC | 483 | * @lport: Fibre Channel local port recieving the ADISC |
| 484 | * @sp: current sequence in the ADISC exchange | 484 | * @sp: current sequence in the ADISC exchange |
| 485 | * @fp: ADISC request frame | 485 | * @fp: ADISC request frame |
| @@ -529,7 +529,7 @@ static void fc_lport_recv_adisc_req(struct fc_seq *sp, struct fc_frame *in_fp, | |||
| 529 | } | 529 | } |
| 530 | 530 | ||
| 531 | /** | 531 | /** |
| 532 | * fc_lport_recv_logo_req - Handle received fabric LOGO request | 532 | * fc_lport_recv_logo_req() - Handle received fabric LOGO request |
| 533 | * @lport: Fibre Channel local port recieving the LOGO | 533 | * @lport: Fibre Channel local port recieving the LOGO |
| 534 | * @sp: current sequence in the LOGO exchange | 534 | * @sp: current sequence in the LOGO exchange |
| 535 | * @fp: LOGO request frame | 535 | * @fp: LOGO request frame |
| @@ -546,7 +546,7 @@ static void fc_lport_recv_logo_req(struct fc_seq *sp, struct fc_frame *fp, | |||
| 546 | } | 546 | } |
| 547 | 547 | ||
| 548 | /** | 548 | /** |
| 549 | * fc_fabric_login - Start the lport state machine | 549 | * fc_fabric_login() - Start the lport state machine |
| 550 | * @lport: The lport that should log into the fabric | 550 | * @lport: The lport that should log into the fabric |
| 551 | * | 551 | * |
| 552 | * Locking Note: This function should not be called | 552 | * Locking Note: This function should not be called |
| @@ -568,7 +568,7 @@ int fc_fabric_login(struct fc_lport *lport) | |||
| 568 | EXPORT_SYMBOL(fc_fabric_login); | 568 | EXPORT_SYMBOL(fc_fabric_login); |
| 569 | 569 | ||
| 570 | /** | 570 | /** |
| 571 | * fc_linkup - Handler for transport linkup events | 571 | * fc_linkup() - Handler for transport linkup events |
| 572 | * @lport: The lport whose link is up | 572 | * @lport: The lport whose link is up |
| 573 | */ | 573 | */ |
| 574 | void fc_linkup(struct fc_lport *lport) | 574 | void fc_linkup(struct fc_lport *lport) |
| @@ -577,8 +577,8 @@ void fc_linkup(struct fc_lport *lport) | |||
| 577 | fc_host_port_id(lport->host)); | 577 | fc_host_port_id(lport->host)); |
| 578 | 578 | ||
| 579 | mutex_lock(&lport->lp_mutex); | 579 | mutex_lock(&lport->lp_mutex); |
| 580 | if ((lport->link_status & FC_LINK_UP) != FC_LINK_UP) { | 580 | if (!lport->link_up) { |
| 581 | lport->link_status |= FC_LINK_UP; | 581 | lport->link_up = 1; |
| 582 | 582 | ||
| 583 | if (lport->state == LPORT_ST_RESET) | 583 | if (lport->state == LPORT_ST_RESET) |
| 584 | fc_lport_enter_flogi(lport); | 584 | fc_lport_enter_flogi(lport); |
| @@ -588,7 +588,7 @@ void fc_linkup(struct fc_lport *lport) | |||
| 588 | EXPORT_SYMBOL(fc_linkup); | 588 | EXPORT_SYMBOL(fc_linkup); |
| 589 | 589 | ||
| 590 | /** | 590 | /** |
| 591 | * fc_linkdown - Handler for transport linkdown events | 591 | * fc_linkdown() - Handler for transport linkdown events |
| 592 | * @lport: The lport whose link is down | 592 | * @lport: The lport whose link is down |
| 593 | */ | 593 | */ |
| 594 | void fc_linkdown(struct fc_lport *lport) | 594 | void fc_linkdown(struct fc_lport *lport) |
| @@ -597,8 +597,8 @@ void fc_linkdown(struct fc_lport *lport) | |||
| 597 | FC_DEBUG_LPORT("Link is down for port (%6x)\n", | 597 | FC_DEBUG_LPORT("Link is down for port (%6x)\n", |
| 598 | fc_host_port_id(lport->host)); | 598 | fc_host_port_id(lport->host)); |
| 599 | 599 | ||
| 600 | if ((lport->link_status & FC_LINK_UP) == FC_LINK_UP) { | 600 | if (lport->link_up) { |
| 601 | lport->link_status &= ~(FC_LINK_UP); | 601 | lport->link_up = 0; |
| 602 | fc_lport_enter_reset(lport); | 602 | fc_lport_enter_reset(lport); |
| 603 | lport->tt.fcp_cleanup(lport); | 603 | lport->tt.fcp_cleanup(lport); |
| 604 | } | 604 | } |
| @@ -607,48 +607,25 @@ void fc_linkdown(struct fc_lport *lport) | |||
| 607 | EXPORT_SYMBOL(fc_linkdown); | 607 | EXPORT_SYMBOL(fc_linkdown); |
| 608 | 608 | ||
| 609 | /** | 609 | /** |
| 610 | * fc_pause - Pause the flow of frames | 610 | * fc_fabric_logoff() - Logout of the fabric |
| 611 | * @lport: The lport to be paused | ||
| 612 | */ | ||
| 613 | void fc_pause(struct fc_lport *lport) | ||
| 614 | { | ||
| 615 | mutex_lock(&lport->lp_mutex); | ||
| 616 | lport->link_status |= FC_PAUSE; | ||
| 617 | mutex_unlock(&lport->lp_mutex); | ||
| 618 | } | ||
| 619 | EXPORT_SYMBOL(fc_pause); | ||
| 620 | |||
| 621 | /** | ||
| 622 | * fc_unpause - Unpause the flow of frames | ||
| 623 | * @lport: The lport to be unpaused | ||
| 624 | */ | ||
| 625 | void fc_unpause(struct fc_lport *lport) | ||
| 626 | { | ||
| 627 | mutex_lock(&lport->lp_mutex); | ||
| 628 | lport->link_status &= ~(FC_PAUSE); | ||
| 629 | mutex_unlock(&lport->lp_mutex); | ||
| 630 | } | ||
| 631 | EXPORT_SYMBOL(fc_unpause); | ||
| 632 | |||
| 633 | /** | ||
| 634 | * fc_fabric_logoff - Logout of the fabric | ||
| 635 | * @lport: fc_lport pointer to logoff the fabric | 611 | * @lport: fc_lport pointer to logoff the fabric |
| 636 | * | 612 | * |
| 637 | * Return value: | 613 | * Return value: |
| 638 | * 0 for success, -1 for failure | 614 | * 0 for success, -1 for failure |
| 639 | **/ | 615 | */ |
| 640 | int fc_fabric_logoff(struct fc_lport *lport) | 616 | int fc_fabric_logoff(struct fc_lport *lport) |
| 641 | { | 617 | { |
| 642 | lport->tt.disc_stop_final(lport); | 618 | lport->tt.disc_stop_final(lport); |
| 643 | mutex_lock(&lport->lp_mutex); | 619 | mutex_lock(&lport->lp_mutex); |
| 644 | fc_lport_enter_logo(lport); | 620 | fc_lport_enter_logo(lport); |
| 645 | mutex_unlock(&lport->lp_mutex); | 621 | mutex_unlock(&lport->lp_mutex); |
| 622 | cancel_delayed_work_sync(&lport->retry_work); | ||
| 646 | return 0; | 623 | return 0; |
| 647 | } | 624 | } |
| 648 | EXPORT_SYMBOL(fc_fabric_logoff); | 625 | EXPORT_SYMBOL(fc_fabric_logoff); |
| 649 | 626 | ||
| 650 | /** | 627 | /** |
| 651 | * fc_lport_destroy - unregister a fc_lport | 628 | * fc_lport_destroy() - unregister a fc_lport |
| 652 | * @lport: fc_lport pointer to unregister | 629 | * @lport: fc_lport pointer to unregister |
| 653 | * | 630 | * |
| 654 | * Return value: | 631 | * Return value: |
| @@ -658,26 +635,25 @@ EXPORT_SYMBOL(fc_fabric_logoff); | |||
| 658 | * clean-up all the allocated memory | 635 | * clean-up all the allocated memory |
| 659 | * and free up other system resources. | 636 | * and free up other system resources. |
| 660 | * | 637 | * |
| 661 | **/ | 638 | */ |
| 662 | int fc_lport_destroy(struct fc_lport *lport) | 639 | int fc_lport_destroy(struct fc_lport *lport) |
| 663 | { | 640 | { |
| 664 | lport->tt.frame_send = fc_frame_drop; | 641 | lport->tt.frame_send = fc_frame_drop; |
| 665 | lport->tt.fcp_abort_io(lport); | 642 | lport->tt.fcp_abort_io(lport); |
| 666 | lport->tt.exch_mgr_reset(lport->emp, 0, 0); | 643 | lport->tt.exch_mgr_reset(lport, 0, 0); |
| 667 | return 0; | 644 | return 0; |
| 668 | } | 645 | } |
| 669 | EXPORT_SYMBOL(fc_lport_destroy); | 646 | EXPORT_SYMBOL(fc_lport_destroy); |
| 670 | 647 | ||
| 671 | /** | 648 | /** |
| 672 | * fc_set_mfs - sets up the mfs for the corresponding fc_lport | 649 | * fc_set_mfs() - sets up the mfs for the corresponding fc_lport |
| 673 | * @lport: fc_lport pointer to unregister | 650 | * @lport: fc_lport pointer to unregister |
| 674 | * @mfs: the new mfs for fc_lport | 651 | * @mfs: the new mfs for fc_lport |
| 675 | * | 652 | * |
| 676 | * Set mfs for the given fc_lport to the new mfs. | 653 | * Set mfs for the given fc_lport to the new mfs. |
| 677 | * | 654 | * |
| 678 | * Return: 0 for success | 655 | * Return: 0 for success |
| 679 | * | 656 | */ |
| 680 | **/ | ||
| 681 | int fc_set_mfs(struct fc_lport *lport, u32 mfs) | 657 | int fc_set_mfs(struct fc_lport *lport, u32 mfs) |
| 682 | { | 658 | { |
| 683 | unsigned int old_mfs; | 659 | unsigned int old_mfs; |
| @@ -706,7 +682,7 @@ int fc_set_mfs(struct fc_lport *lport, u32 mfs) | |||
| 706 | EXPORT_SYMBOL(fc_set_mfs); | 682 | EXPORT_SYMBOL(fc_set_mfs); |
| 707 | 683 | ||
| 708 | /** | 684 | /** |
| 709 | * fc_lport_disc_callback - Callback for discovery events | 685 | * fc_lport_disc_callback() - Callback for discovery events |
| 710 | * @lport: FC local port | 686 | * @lport: FC local port |
| 711 | * @event: The discovery event | 687 | * @event: The discovery event |
| 712 | */ | 688 | */ |
| @@ -731,7 +707,7 @@ void fc_lport_disc_callback(struct fc_lport *lport, enum fc_disc_event event) | |||
| 731 | } | 707 | } |
| 732 | 708 | ||
| 733 | /** | 709 | /** |
| 734 | * fc_rport_enter_ready - Enter the ready state and start discovery | 710 | * fc_rport_enter_ready() - Enter the ready state and start discovery |
| 735 | * @lport: Fibre Channel local port that is ready | 711 | * @lport: Fibre Channel local port that is ready |
| 736 | * | 712 | * |
| 737 | * Locking Note: The lport lock is expected to be held before calling | 713 | * Locking Note: The lport lock is expected to be held before calling |
| @@ -748,7 +724,7 @@ static void fc_lport_enter_ready(struct fc_lport *lport) | |||
| 748 | } | 724 | } |
| 749 | 725 | ||
| 750 | /** | 726 | /** |
| 751 | * fc_lport_recv_flogi_req - Receive a FLOGI request | 727 | * fc_lport_recv_flogi_req() - Receive a FLOGI request |
| 752 | * @sp_in: The sequence the FLOGI is on | 728 | * @sp_in: The sequence the FLOGI is on |
| 753 | * @rx_fp: The frame the FLOGI is in | 729 | * @rx_fp: The frame the FLOGI is in |
| 754 | * @lport: The lport that recieved the request | 730 | * @lport: The lport that recieved the request |
| @@ -838,7 +814,7 @@ out: | |||
| 838 | } | 814 | } |
| 839 | 815 | ||
| 840 | /** | 816 | /** |
| 841 | * fc_lport_recv_req - The generic lport request handler | 817 | * fc_lport_recv_req() - The generic lport request handler |
| 842 | * @lport: The lport that received the request | 818 | * @lport: The lport that received the request |
| 843 | * @sp: The sequence the request is on | 819 | * @sp: The sequence the request is on |
| 844 | * @fp: The frame the request is in | 820 | * @fp: The frame the request is in |
| @@ -934,7 +910,7 @@ static void fc_lport_recv_req(struct fc_lport *lport, struct fc_seq *sp, | |||
| 934 | } | 910 | } |
| 935 | 911 | ||
| 936 | /** | 912 | /** |
| 937 | * fc_lport_reset - Reset an lport | 913 | * fc_lport_reset() - Reset an lport |
| 938 | * @lport: The lport which should be reset | 914 | * @lport: The lport which should be reset |
| 939 | * | 915 | * |
| 940 | * Locking Note: This functions should not be called with the | 916 | * Locking Note: This functions should not be called with the |
| @@ -942,6 +918,7 @@ static void fc_lport_recv_req(struct fc_lport *lport, struct fc_seq *sp, | |||
| 942 | */ | 918 | */ |
| 943 | int fc_lport_reset(struct fc_lport *lport) | 919 | int fc_lport_reset(struct fc_lport *lport) |
| 944 | { | 920 | { |
| 921 | cancel_delayed_work_sync(&lport->retry_work); | ||
| 945 | mutex_lock(&lport->lp_mutex); | 922 | mutex_lock(&lport->lp_mutex); |
| 946 | fc_lport_enter_reset(lport); | 923 | fc_lport_enter_reset(lport); |
| 947 | mutex_unlock(&lport->lp_mutex); | 924 | mutex_unlock(&lport->lp_mutex); |
| @@ -950,7 +927,7 @@ int fc_lport_reset(struct fc_lport *lport) | |||
| 950 | EXPORT_SYMBOL(fc_lport_reset); | 927 | EXPORT_SYMBOL(fc_lport_reset); |
| 951 | 928 | ||
| 952 | /** | 929 | /** |
| 953 | * fc_rport_enter_reset - Reset the local port | 930 | * fc_rport_enter_reset() - Reset the local port |
| 954 | * @lport: Fibre Channel local port to be reset | 931 | * @lport: Fibre Channel local port to be reset |
| 955 | * | 932 | * |
| 956 | * Locking Note: The lport lock is expected to be held before calling | 933 | * Locking Note: The lport lock is expected to be held before calling |
| @@ -973,16 +950,16 @@ static void fc_lport_enter_reset(struct fc_lport *lport) | |||
| 973 | 950 | ||
| 974 | lport->tt.disc_stop(lport); | 951 | lport->tt.disc_stop(lport); |
| 975 | 952 | ||
| 976 | lport->tt.exch_mgr_reset(lport->emp, 0, 0); | 953 | lport->tt.exch_mgr_reset(lport, 0, 0); |
| 977 | fc_host_fabric_name(lport->host) = 0; | 954 | fc_host_fabric_name(lport->host) = 0; |
| 978 | fc_host_port_id(lport->host) = 0; | 955 | fc_host_port_id(lport->host) = 0; |
| 979 | 956 | ||
| 980 | if ((lport->link_status & FC_LINK_UP) == FC_LINK_UP) | 957 | if (lport->link_up) |
| 981 | fc_lport_enter_flogi(lport); | 958 | fc_lport_enter_flogi(lport); |
| 982 | } | 959 | } |
| 983 | 960 | ||
| 984 | /** | 961 | /** |
| 985 | * fc_lport_error - Handler for any errors | 962 | * fc_lport_error() - Handler for any errors |
| 986 | * @lport: The fc_lport object | 963 | * @lport: The fc_lport object |
| 987 | * @fp: The frame pointer | 964 | * @fp: The frame pointer |
| 988 | * | 965 | * |
| @@ -1029,8 +1006,8 @@ static void fc_lport_error(struct fc_lport *lport, struct fc_frame *fp) | |||
| 1029 | } | 1006 | } |
| 1030 | 1007 | ||
| 1031 | /** | 1008 | /** |
| 1032 | * fc_lport_rft_id_resp - Handle response to Register Fibre | 1009 | * fc_lport_rft_id_resp() - Handle response to Register Fibre |
| 1033 | * Channel Types by ID (RPN_ID) request | 1010 | * Channel Types by ID (RPN_ID) request |
| 1034 | * @sp: current sequence in RPN_ID exchange | 1011 | * @sp: current sequence in RPN_ID exchange |
| 1035 | * @fp: response frame | 1012 | * @fp: response frame |
| 1036 | * @lp_arg: Fibre Channel host port instance | 1013 | * @lp_arg: Fibre Channel host port instance |
| @@ -1053,17 +1030,17 @@ static void fc_lport_rft_id_resp(struct fc_seq *sp, struct fc_frame *fp, | |||
| 1053 | 1030 | ||
| 1054 | FC_DEBUG_LPORT("Received a RFT_ID response\n"); | 1031 | FC_DEBUG_LPORT("Received a RFT_ID response\n"); |
| 1055 | 1032 | ||
| 1033 | if (IS_ERR(fp)) { | ||
| 1034 | fc_lport_error(lport, fp); | ||
| 1035 | goto err; | ||
| 1036 | } | ||
| 1037 | |||
| 1056 | if (lport->state != LPORT_ST_RFT_ID) { | 1038 | if (lport->state != LPORT_ST_RFT_ID) { |
| 1057 | FC_DBG("Received a RFT_ID response, but in state %s\n", | 1039 | FC_DBG("Received a RFT_ID response, but in state %s\n", |
| 1058 | fc_lport_state(lport)); | 1040 | fc_lport_state(lport)); |
| 1059 | goto out; | 1041 | goto out; |
| 1060 | } | 1042 | } |
| 1061 | 1043 | ||
| 1062 | if (IS_ERR(fp)) { | ||
| 1063 | fc_lport_error(lport, fp); | ||
| 1064 | goto err; | ||
| 1065 | } | ||
| 1066 | |||
| 1067 | fh = fc_frame_header_get(fp); | 1044 | fh = fc_frame_header_get(fp); |
| 1068 | ct = fc_frame_payload_get(fp, sizeof(*ct)); | 1045 | ct = fc_frame_payload_get(fp, sizeof(*ct)); |
| 1069 | 1046 | ||
| @@ -1081,8 +1058,8 @@ err: | |||
| 1081 | } | 1058 | } |
| 1082 | 1059 | ||
| 1083 | /** | 1060 | /** |
| 1084 | * fc_lport_rpn_id_resp - Handle response to Register Port | 1061 | * fc_lport_rpn_id_resp() - Handle response to Register Port |
| 1085 | * Name by ID (RPN_ID) request | 1062 | * Name by ID (RPN_ID) request |
| 1086 | * @sp: current sequence in RPN_ID exchange | 1063 | * @sp: current sequence in RPN_ID exchange |
| 1087 | * @fp: response frame | 1064 | * @fp: response frame |
| 1088 | * @lp_arg: Fibre Channel host port instance | 1065 | * @lp_arg: Fibre Channel host port instance |
| @@ -1105,17 +1082,17 @@ static void fc_lport_rpn_id_resp(struct fc_seq *sp, struct fc_frame *fp, | |||
| 1105 | 1082 | ||
| 1106 | FC_DEBUG_LPORT("Received a RPN_ID response\n"); | 1083 | FC_DEBUG_LPORT("Received a RPN_ID response\n"); |
| 1107 | 1084 | ||
| 1085 | if (IS_ERR(fp)) { | ||
| 1086 | fc_lport_error(lport, fp); | ||
| 1087 | goto err; | ||
| 1088 | } | ||
| 1089 | |||
| 1108 | if (lport->state != LPORT_ST_RPN_ID) { | 1090 | if (lport->state != LPORT_ST_RPN_ID) { |
| 1109 | FC_DBG("Received a RPN_ID response, but in state %s\n", | 1091 | FC_DBG("Received a RPN_ID response, but in state %s\n", |
| 1110 | fc_lport_state(lport)); | 1092 | fc_lport_state(lport)); |
| 1111 | goto out; | 1093 | goto out; |
| 1112 | } | 1094 | } |
| 1113 | 1095 | ||
| 1114 | if (IS_ERR(fp)) { | ||
| 1115 | fc_lport_error(lport, fp); | ||
| 1116 | goto err; | ||
| 1117 | } | ||
| 1118 | |||
| 1119 | fh = fc_frame_header_get(fp); | 1096 | fh = fc_frame_header_get(fp); |
| 1120 | ct = fc_frame_payload_get(fp, sizeof(*ct)); | 1097 | ct = fc_frame_payload_get(fp, sizeof(*ct)); |
| 1121 | if (fh && ct && fh->fh_type == FC_TYPE_CT && | 1098 | if (fh && ct && fh->fh_type == FC_TYPE_CT && |
| @@ -1133,7 +1110,7 @@ err: | |||
| 1133 | } | 1110 | } |
| 1134 | 1111 | ||
| 1135 | /** | 1112 | /** |
| 1136 | * fc_lport_scr_resp - Handle response to State Change Register (SCR) request | 1113 | * fc_lport_scr_resp() - Handle response to State Change Register (SCR) request |
| 1137 | * @sp: current sequence in SCR exchange | 1114 | * @sp: current sequence in SCR exchange |
| 1138 | * @fp: response frame | 1115 | * @fp: response frame |
| 1139 | * @lp_arg: Fibre Channel lport port instance that sent the registration request | 1116 | * @lp_arg: Fibre Channel lport port instance that sent the registration request |
| @@ -1155,17 +1132,17 @@ static void fc_lport_scr_resp(struct fc_seq *sp, struct fc_frame *fp, | |||
| 1155 | 1132 | ||
| 1156 | FC_DEBUG_LPORT("Received a SCR response\n"); | 1133 | FC_DEBUG_LPORT("Received a SCR response\n"); |
| 1157 | 1134 | ||
| 1135 | if (IS_ERR(fp)) { | ||
| 1136 | fc_lport_error(lport, fp); | ||
| 1137 | goto err; | ||
| 1138 | } | ||
| 1139 | |||
| 1158 | if (lport->state != LPORT_ST_SCR) { | 1140 | if (lport->state != LPORT_ST_SCR) { |
| 1159 | FC_DBG("Received a SCR response, but in state %s\n", | 1141 | FC_DBG("Received a SCR response, but in state %s\n", |
| 1160 | fc_lport_state(lport)); | 1142 | fc_lport_state(lport)); |
| 1161 | goto out; | 1143 | goto out; |
| 1162 | } | 1144 | } |
| 1163 | 1145 | ||
| 1164 | if (IS_ERR(fp)) { | ||
| 1165 | fc_lport_error(lport, fp); | ||
| 1166 | goto err; | ||
| 1167 | } | ||
| 1168 | |||
| 1169 | op = fc_frame_payload_op(fp); | 1146 | op = fc_frame_payload_op(fp); |
| 1170 | if (op == ELS_LS_ACC) | 1147 | if (op == ELS_LS_ACC) |
| 1171 | fc_lport_enter_ready(lport); | 1148 | fc_lport_enter_ready(lport); |
| @@ -1179,7 +1156,7 @@ err: | |||
| 1179 | } | 1156 | } |
| 1180 | 1157 | ||
| 1181 | /** | 1158 | /** |
| 1182 | * fc_lport_enter_scr - Send a State Change Register (SCR) request | 1159 | * fc_lport_enter_scr() - Send a State Change Register (SCR) request |
| 1183 | * @lport: Fibre Channel local port to register for state changes | 1160 | * @lport: Fibre Channel local port to register for state changes |
| 1184 | * | 1161 | * |
| 1185 | * Locking Note: The lport lock is expected to be held before calling | 1162 | * Locking Note: The lport lock is expected to be held before calling |
| @@ -1206,7 +1183,7 @@ static void fc_lport_enter_scr(struct fc_lport *lport) | |||
| 1206 | } | 1183 | } |
| 1207 | 1184 | ||
| 1208 | /** | 1185 | /** |
| 1209 | * fc_lport_enter_rft_id - Register FC4-types with the name server | 1186 | * fc_lport_enter_rft_id() - Register FC4-types with the name server |
| 1210 | * @lport: Fibre Channel local port to register | 1187 | * @lport: Fibre Channel local port to register |
| 1211 | * | 1188 | * |
| 1212 | * Locking Note: The lport lock is expected to be held before calling | 1189 | * Locking Note: The lport lock is expected to be held before calling |
| @@ -1248,7 +1225,7 @@ static void fc_lport_enter_rft_id(struct fc_lport *lport) | |||
| 1248 | } | 1225 | } |
| 1249 | 1226 | ||
| 1250 | /** | 1227 | /** |
| 1251 | * fc_rport_enter_rft_id - Register port name with the name server | 1228 | * fc_rport_enter_rft_id() - Register port name with the name server |
| 1252 | * @lport: Fibre Channel local port to register | 1229 | * @lport: Fibre Channel local port to register |
| 1253 | * | 1230 | * |
| 1254 | * Locking Note: The lport lock is expected to be held before calling | 1231 | * Locking Note: The lport lock is expected to be held before calling |
| @@ -1281,7 +1258,7 @@ static struct fc_rport_operations fc_lport_rport_ops = { | |||
| 1281 | }; | 1258 | }; |
| 1282 | 1259 | ||
| 1283 | /** | 1260 | /** |
| 1284 | * fc_rport_enter_dns - Create a rport to the name server | 1261 | * fc_rport_enter_dns() - Create a rport to the name server |
| 1285 | * @lport: Fibre Channel local port requesting a rport for the name server | 1262 | * @lport: Fibre Channel local port requesting a rport for the name server |
| 1286 | * | 1263 | * |
| 1287 | * Locking Note: The lport lock is expected to be held before calling | 1264 | * Locking Note: The lport lock is expected to be held before calling |
| @@ -1304,7 +1281,7 @@ static void fc_lport_enter_dns(struct fc_lport *lport) | |||
| 1304 | 1281 | ||
| 1305 | fc_lport_state_enter(lport, LPORT_ST_DNS); | 1282 | fc_lport_state_enter(lport, LPORT_ST_DNS); |
| 1306 | 1283 | ||
| 1307 | rport = fc_rport_rogue_create(&dp); | 1284 | rport = lport->tt.rport_create(&dp); |
| 1308 | if (!rport) | 1285 | if (!rport) |
| 1309 | goto err; | 1286 | goto err; |
| 1310 | 1287 | ||
| @@ -1318,7 +1295,7 @@ err: | |||
| 1318 | } | 1295 | } |
| 1319 | 1296 | ||
| 1320 | /** | 1297 | /** |
| 1321 | * fc_lport_timeout - Handler for the retry_work timer. | 1298 | * fc_lport_timeout() - Handler for the retry_work timer. |
| 1322 | * @work: The work struct of the fc_lport | 1299 | * @work: The work struct of the fc_lport |
| 1323 | */ | 1300 | */ |
| 1324 | static void fc_lport_timeout(struct work_struct *work) | 1301 | static void fc_lport_timeout(struct work_struct *work) |
| @@ -1359,7 +1336,7 @@ static void fc_lport_timeout(struct work_struct *work) | |||
| 1359 | } | 1336 | } |
| 1360 | 1337 | ||
| 1361 | /** | 1338 | /** |
| 1362 | * fc_lport_logo_resp - Handle response to LOGO request | 1339 | * fc_lport_logo_resp() - Handle response to LOGO request |
| 1363 | * @sp: current sequence in LOGO exchange | 1340 | * @sp: current sequence in LOGO exchange |
| 1364 | * @fp: response frame | 1341 | * @fp: response frame |
| 1365 | * @lp_arg: Fibre Channel lport port instance that sent the LOGO request | 1342 | * @lp_arg: Fibre Channel lport port instance that sent the LOGO request |
| @@ -1381,17 +1358,17 @@ static void fc_lport_logo_resp(struct fc_seq *sp, struct fc_frame *fp, | |||
| 1381 | 1358 | ||
| 1382 | FC_DEBUG_LPORT("Received a LOGO response\n"); | 1359 | FC_DEBUG_LPORT("Received a LOGO response\n"); |
| 1383 | 1360 | ||
| 1361 | if (IS_ERR(fp)) { | ||
| 1362 | fc_lport_error(lport, fp); | ||
| 1363 | goto err; | ||
| 1364 | } | ||
| 1365 | |||
| 1384 | if (lport->state != LPORT_ST_LOGO) { | 1366 | if (lport->state != LPORT_ST_LOGO) { |
| 1385 | FC_DBG("Received a LOGO response, but in state %s\n", | 1367 | FC_DBG("Received a LOGO response, but in state %s\n", |
| 1386 | fc_lport_state(lport)); | 1368 | fc_lport_state(lport)); |
| 1387 | goto out; | 1369 | goto out; |
| 1388 | } | 1370 | } |
| 1389 | 1371 | ||
| 1390 | if (IS_ERR(fp)) { | ||
| 1391 | fc_lport_error(lport, fp); | ||
| 1392 | goto err; | ||
| 1393 | } | ||
| 1394 | |||
| 1395 | op = fc_frame_payload_op(fp); | 1372 | op = fc_frame_payload_op(fp); |
| 1396 | if (op == ELS_LS_ACC) | 1373 | if (op == ELS_LS_ACC) |
| 1397 | fc_lport_enter_reset(lport); | 1374 | fc_lport_enter_reset(lport); |
| @@ -1405,7 +1382,7 @@ err: | |||
| 1405 | } | 1382 | } |
| 1406 | 1383 | ||
| 1407 | /** | 1384 | /** |
| 1408 | * fc_rport_enter_logo - Logout of the fabric | 1385 | * fc_rport_enter_logo() - Logout of the fabric |
| 1409 | * @lport: Fibre Channel local port to be logged out | 1386 | * @lport: Fibre Channel local port to be logged out |
| 1410 | * | 1387 | * |
| 1411 | * Locking Note: The lport lock is expected to be held before calling | 1388 | * Locking Note: The lport lock is expected to be held before calling |
| @@ -1437,7 +1414,7 @@ static void fc_lport_enter_logo(struct fc_lport *lport) | |||
| 1437 | } | 1414 | } |
| 1438 | 1415 | ||
| 1439 | /** | 1416 | /** |
| 1440 | * fc_lport_flogi_resp - Handle response to FLOGI request | 1417 | * fc_lport_flogi_resp() - Handle response to FLOGI request |
| 1441 | * @sp: current sequence in FLOGI exchange | 1418 | * @sp: current sequence in FLOGI exchange |
| 1442 | * @fp: response frame | 1419 | * @fp: response frame |
| 1443 | * @lp_arg: Fibre Channel lport port instance that sent the FLOGI request | 1420 | * @lp_arg: Fibre Channel lport port instance that sent the FLOGI request |
| @@ -1465,17 +1442,17 @@ static void fc_lport_flogi_resp(struct fc_seq *sp, struct fc_frame *fp, | |||
| 1465 | 1442 | ||
| 1466 | FC_DEBUG_LPORT("Received a FLOGI response\n"); | 1443 | FC_DEBUG_LPORT("Received a FLOGI response\n"); |
| 1467 | 1444 | ||
| 1445 | if (IS_ERR(fp)) { | ||
| 1446 | fc_lport_error(lport, fp); | ||
| 1447 | goto err; | ||
| 1448 | } | ||
| 1449 | |||
| 1468 | if (lport->state != LPORT_ST_FLOGI) { | 1450 | if (lport->state != LPORT_ST_FLOGI) { |
| 1469 | FC_DBG("Received a FLOGI response, but in state %s\n", | 1451 | FC_DBG("Received a FLOGI response, but in state %s\n", |
| 1470 | fc_lport_state(lport)); | 1452 | fc_lport_state(lport)); |
| 1471 | goto out; | 1453 | goto out; |
| 1472 | } | 1454 | } |
| 1473 | 1455 | ||
| 1474 | if (IS_ERR(fp)) { | ||
| 1475 | fc_lport_error(lport, fp); | ||
| 1476 | goto err; | ||
| 1477 | } | ||
| 1478 | |||
| 1479 | fh = fc_frame_header_get(fp); | 1456 | fh = fc_frame_header_get(fp); |
| 1480 | did = ntoh24(fh->fh_d_id); | 1457 | did = ntoh24(fh->fh_d_id); |
| 1481 | if (fc_frame_payload_op(fp) == ELS_LS_ACC && did != 0) { | 1458 | if (fc_frame_payload_op(fp) == ELS_LS_ACC && did != 0) { |
| @@ -1532,7 +1509,7 @@ err: | |||
| 1532 | } | 1509 | } |
| 1533 | 1510 | ||
| 1534 | /** | 1511 | /** |
| 1535 | * fc_rport_enter_flogi - Send a FLOGI request to the fabric manager | 1512 | * fc_rport_enter_flogi() - Send a FLOGI request to the fabric manager |
| 1536 | * @lport: Fibre Channel local port to be logged in to the fabric | 1513 | * @lport: Fibre Channel local port to be logged in to the fabric |
| 1537 | * | 1514 | * |
| 1538 | * Locking Note: The lport lock is expected to be held before calling | 1515 | * Locking Note: The lport lock is expected to be held before calling |
diff --git a/drivers/scsi/libfc/fc_rport.c b/drivers/scsi/libfc/fc_rport.c index e780d8caf70e..dae65133a833 100644 --- a/drivers/scsi/libfc/fc_rport.c +++ b/drivers/scsi/libfc/fc_rport.c | |||
| @@ -81,6 +81,7 @@ static void fc_rport_recv_logo_req(struct fc_rport *, | |||
| 81 | struct fc_seq *, struct fc_frame *); | 81 | struct fc_seq *, struct fc_frame *); |
| 82 | static void fc_rport_timeout(struct work_struct *); | 82 | static void fc_rport_timeout(struct work_struct *); |
| 83 | static void fc_rport_error(struct fc_rport *, struct fc_frame *); | 83 | static void fc_rport_error(struct fc_rport *, struct fc_frame *); |
| 84 | static void fc_rport_error_retry(struct fc_rport *, struct fc_frame *); | ||
| 84 | static void fc_rport_work(struct work_struct *); | 85 | static void fc_rport_work(struct work_struct *); |
| 85 | 86 | ||
| 86 | static const char *fc_rport_state_names[] = { | 87 | static const char *fc_rport_state_names[] = { |
| @@ -145,7 +146,7 @@ struct fc_rport *fc_rport_rogue_create(struct fc_disc_port *dp) | |||
| 145 | } | 146 | } |
| 146 | 147 | ||
| 147 | /** | 148 | /** |
| 148 | * fc_rport_state - return a string for the state the rport is in | 149 | * fc_rport_state() - return a string for the state the rport is in |
| 149 | * @rport: The rport whose state we want to get a string for | 150 | * @rport: The rport whose state we want to get a string for |
| 150 | */ | 151 | */ |
| 151 | static const char *fc_rport_state(struct fc_rport *rport) | 152 | static const char *fc_rport_state(struct fc_rport *rport) |
| @@ -160,7 +161,7 @@ static const char *fc_rport_state(struct fc_rport *rport) | |||
| 160 | } | 161 | } |
| 161 | 162 | ||
| 162 | /** | 163 | /** |
| 163 | * fc_set_rport_loss_tmo - Set the remote port loss timeout in seconds. | 164 | * fc_set_rport_loss_tmo() - Set the remote port loss timeout in seconds. |
| 164 | * @rport: Pointer to Fibre Channel remote port structure | 165 | * @rport: Pointer to Fibre Channel remote port structure |
| 165 | * @timeout: timeout in seconds | 166 | * @timeout: timeout in seconds |
| 166 | */ | 167 | */ |
| @@ -174,12 +175,12 @@ void fc_set_rport_loss_tmo(struct fc_rport *rport, u32 timeout) | |||
| 174 | EXPORT_SYMBOL(fc_set_rport_loss_tmo); | 175 | EXPORT_SYMBOL(fc_set_rport_loss_tmo); |
| 175 | 176 | ||
| 176 | /** | 177 | /** |
| 177 | * fc_plogi_get_maxframe - Get max payload from the common service parameters | 178 | * fc_plogi_get_maxframe() - Get max payload from the common service parameters |
| 178 | * @flp: FLOGI payload structure | 179 | * @flp: FLOGI payload structure |
| 179 | * @maxval: upper limit, may be less than what is in the service parameters | 180 | * @maxval: upper limit, may be less than what is in the service parameters |
| 180 | */ | 181 | */ |
| 181 | static unsigned int | 182 | static unsigned int fc_plogi_get_maxframe(struct fc_els_flogi *flp, |
| 182 | fc_plogi_get_maxframe(struct fc_els_flogi *flp, unsigned int maxval) | 183 | unsigned int maxval) |
| 183 | { | 184 | { |
| 184 | unsigned int mfs; | 185 | unsigned int mfs; |
| 185 | 186 | ||
| @@ -197,7 +198,7 @@ fc_plogi_get_maxframe(struct fc_els_flogi *flp, unsigned int maxval) | |||
| 197 | } | 198 | } |
| 198 | 199 | ||
| 199 | /** | 200 | /** |
| 200 | * fc_rport_state_enter - Change the rport's state | 201 | * fc_rport_state_enter() - Change the rport's state |
| 201 | * @rport: The rport whose state should change | 202 | * @rport: The rport whose state should change |
| 202 | * @new: The new state of the rport | 203 | * @new: The new state of the rport |
| 203 | * | 204 | * |
| @@ -214,6 +215,7 @@ static void fc_rport_state_enter(struct fc_rport *rport, | |||
| 214 | 215 | ||
| 215 | static void fc_rport_work(struct work_struct *work) | 216 | static void fc_rport_work(struct work_struct *work) |
| 216 | { | 217 | { |
| 218 | u32 port_id; | ||
| 217 | struct fc_rport_libfc_priv *rdata = | 219 | struct fc_rport_libfc_priv *rdata = |
| 218 | container_of(work, struct fc_rport_libfc_priv, event_work); | 220 | container_of(work, struct fc_rport_libfc_priv, event_work); |
| 219 | enum fc_rport_event event; | 221 | enum fc_rport_event event; |
| @@ -279,14 +281,18 @@ static void fc_rport_work(struct work_struct *work) | |||
| 279 | rport_ops->event_callback(lport, rport, event); | 281 | rport_ops->event_callback(lport, rport, event); |
| 280 | if (trans_state == FC_PORTSTATE_ROGUE) | 282 | if (trans_state == FC_PORTSTATE_ROGUE) |
| 281 | put_device(&rport->dev); | 283 | put_device(&rport->dev); |
| 282 | else | 284 | else { |
| 285 | port_id = rport->port_id; | ||
| 283 | fc_remote_port_delete(rport); | 286 | fc_remote_port_delete(rport); |
| 287 | lport->tt.exch_mgr_reset(lport, 0, port_id); | ||
| 288 | lport->tt.exch_mgr_reset(lport, port_id, 0); | ||
| 289 | } | ||
| 284 | } else | 290 | } else |
| 285 | mutex_unlock(&rdata->rp_mutex); | 291 | mutex_unlock(&rdata->rp_mutex); |
| 286 | } | 292 | } |
| 287 | 293 | ||
| 288 | /** | 294 | /** |
| 289 | * fc_rport_login - Start the remote port login state machine | 295 | * fc_rport_login() - Start the remote port login state machine |
| 290 | * @rport: Fibre Channel remote port | 296 | * @rport: Fibre Channel remote port |
| 291 | * | 297 | * |
| 292 | * Locking Note: Called without the rport lock held. This | 298 | * Locking Note: Called without the rport lock held. This |
| @@ -309,7 +315,7 @@ int fc_rport_login(struct fc_rport *rport) | |||
| 309 | } | 315 | } |
| 310 | 316 | ||
| 311 | /** | 317 | /** |
| 312 | * fc_rport_logoff - Logoff and remove an rport | 318 | * fc_rport_logoff() - Logoff and remove an rport |
| 313 | * @rport: Fibre Channel remote port to be removed | 319 | * @rport: Fibre Channel remote port to be removed |
| 314 | * | 320 | * |
| 315 | * Locking Note: Called without the rport lock held. This | 321 | * Locking Note: Called without the rport lock held. This |
| @@ -347,7 +353,7 @@ int fc_rport_logoff(struct fc_rport *rport) | |||
| 347 | } | 353 | } |
| 348 | 354 | ||
| 349 | /** | 355 | /** |
| 350 | * fc_rport_enter_ready - The rport is ready | 356 | * fc_rport_enter_ready() - The rport is ready |
| 351 | * @rport: Fibre Channel remote port that is ready | 357 | * @rport: Fibre Channel remote port that is ready |
| 352 | * | 358 | * |
| 353 | * Locking Note: The rport lock is expected to be held before calling | 359 | * Locking Note: The rport lock is expected to be held before calling |
| @@ -366,7 +372,7 @@ static void fc_rport_enter_ready(struct fc_rport *rport) | |||
| 366 | } | 372 | } |
| 367 | 373 | ||
| 368 | /** | 374 | /** |
| 369 | * fc_rport_timeout - Handler for the retry_work timer. | 375 | * fc_rport_timeout() - Handler for the retry_work timer. |
| 370 | * @work: The work struct of the fc_rport_libfc_priv | 376 | * @work: The work struct of the fc_rport_libfc_priv |
| 371 | * | 377 | * |
| 372 | * Locking Note: Called without the rport lock held. This | 378 | * Locking Note: Called without the rport lock held. This |
| @@ -405,59 +411,75 @@ static void fc_rport_timeout(struct work_struct *work) | |||
| 405 | } | 411 | } |
| 406 | 412 | ||
| 407 | /** | 413 | /** |
| 408 | * fc_rport_error - Handler for any errors | 414 | * fc_rport_error() - Error handler, called once retries have been exhausted |
| 409 | * @rport: The fc_rport object | 415 | * @rport: The fc_rport object |
| 410 | * @fp: The frame pointer | 416 | * @fp: The frame pointer |
| 411 | * | 417 | * |
| 412 | * If the error was caused by a resource allocation failure | ||
| 413 | * then wait for half a second and retry, otherwise retry | ||
| 414 | * immediately. | ||
| 415 | * | ||
| 416 | * Locking Note: The rport lock is expected to be held before | 418 | * Locking Note: The rport lock is expected to be held before |
| 417 | * calling this routine | 419 | * calling this routine |
| 418 | */ | 420 | */ |
| 419 | static void fc_rport_error(struct fc_rport *rport, struct fc_frame *fp) | 421 | static void fc_rport_error(struct fc_rport *rport, struct fc_frame *fp) |
| 420 | { | 422 | { |
| 421 | struct fc_rport_libfc_priv *rdata = rport->dd_data; | 423 | struct fc_rport_libfc_priv *rdata = rport->dd_data; |
| 422 | unsigned long delay = 0; | ||
| 423 | 424 | ||
| 424 | FC_DEBUG_RPORT("Error %ld in state %s, retries %d\n", | 425 | FC_DEBUG_RPORT("Error %ld in state %s, retries %d\n", |
| 425 | PTR_ERR(fp), fc_rport_state(rport), rdata->retries); | 426 | PTR_ERR(fp), fc_rport_state(rport), rdata->retries); |
| 426 | 427 | ||
| 427 | if (!fp || PTR_ERR(fp) == -FC_EX_TIMEOUT) { | 428 | switch (rdata->rp_state) { |
| 428 | /* | 429 | case RPORT_ST_PLOGI: |
| 429 | * Memory allocation failure, or the exchange timed out. | 430 | case RPORT_ST_PRLI: |
| 430 | * Retry after delay | 431 | case RPORT_ST_LOGO: |
| 431 | */ | 432 | rdata->event = RPORT_EV_FAILED; |
| 432 | if (rdata->retries < rdata->local_port->max_retry_count) { | 433 | queue_work(rport_event_queue, |
| 433 | rdata->retries++; | 434 | &rdata->event_work); |
| 434 | if (!fp) | 435 | break; |
| 435 | delay = msecs_to_jiffies(500); | 436 | case RPORT_ST_RTV: |
| 436 | get_device(&rport->dev); | 437 | fc_rport_enter_ready(rport); |
| 437 | schedule_delayed_work(&rdata->retry_work, delay); | 438 | break; |
| 438 | } else { | 439 | case RPORT_ST_NONE: |
| 439 | switch (rdata->rp_state) { | 440 | case RPORT_ST_READY: |
| 440 | case RPORT_ST_PLOGI: | 441 | case RPORT_ST_INIT: |
| 441 | case RPORT_ST_PRLI: | 442 | break; |
| 442 | case RPORT_ST_LOGO: | ||
| 443 | rdata->event = RPORT_EV_FAILED; | ||
| 444 | queue_work(rport_event_queue, | ||
| 445 | &rdata->event_work); | ||
| 446 | break; | ||
| 447 | case RPORT_ST_RTV: | ||
| 448 | fc_rport_enter_ready(rport); | ||
| 449 | break; | ||
| 450 | case RPORT_ST_NONE: | ||
| 451 | case RPORT_ST_READY: | ||
| 452 | case RPORT_ST_INIT: | ||
| 453 | break; | ||
| 454 | } | ||
| 455 | } | ||
| 456 | } | 443 | } |
| 457 | } | 444 | } |
| 458 | 445 | ||
| 459 | /** | 446 | /** |
| 460 | * fc_rport_plogi_recv_resp - Handle incoming ELS PLOGI response | 447 | * fc_rport_error_retry() - Error handler when retries are desired |
| 448 | * @rport: The fc_rport object | ||
| 449 | * @fp: The frame pointer | ||
| 450 | * | ||
| 451 | * If the error was an exchange timeout retry immediately, | ||
| 452 | * otherwise wait for E_D_TOV. | ||
| 453 | * | ||
| 454 | * Locking Note: The rport lock is expected to be held before | ||
| 455 | * calling this routine | ||
| 456 | */ | ||
| 457 | static void fc_rport_error_retry(struct fc_rport *rport, struct fc_frame *fp) | ||
| 458 | { | ||
| 459 | struct fc_rport_libfc_priv *rdata = rport->dd_data; | ||
| 460 | unsigned long delay = FC_DEF_E_D_TOV; | ||
| 461 | |||
| 462 | /* make sure this isn't an FC_EX_CLOSED error, never retry those */ | ||
| 463 | if (PTR_ERR(fp) == -FC_EX_CLOSED) | ||
| 464 | return fc_rport_error(rport, fp); | ||
| 465 | |||
| 466 | if (rdata->retries < rdata->local_port->max_retry_count) { | ||
| 467 | FC_DEBUG_RPORT("Error %ld in state %s, retrying\n", | ||
| 468 | PTR_ERR(fp), fc_rport_state(rport)); | ||
| 469 | rdata->retries++; | ||
| 470 | /* no additional delay on exchange timeouts */ | ||
| 471 | if (PTR_ERR(fp) == -FC_EX_TIMEOUT) | ||
| 472 | delay = 0; | ||
| 473 | get_device(&rport->dev); | ||
| 474 | schedule_delayed_work(&rdata->retry_work, delay); | ||
| 475 | return; | ||
| 476 | } | ||
| 477 | |||
| 478 | return fc_rport_error(rport, fp); | ||
| 479 | } | ||
| 480 | |||
| 481 | /** | ||
| 482 | * fc_rport_plogi_recv_resp() - Handle incoming ELS PLOGI response | ||
| 461 | * @sp: current sequence in the PLOGI exchange | 483 | * @sp: current sequence in the PLOGI exchange |
| 462 | * @fp: response frame | 484 | * @fp: response frame |
| 463 | * @rp_arg: Fibre Channel remote port | 485 | * @rp_arg: Fibre Channel remote port |
| @@ -483,17 +505,17 @@ static void fc_rport_plogi_resp(struct fc_seq *sp, struct fc_frame *fp, | |||
| 483 | FC_DEBUG_RPORT("Received a PLOGI response from port (%6x)\n", | 505 | FC_DEBUG_RPORT("Received a PLOGI response from port (%6x)\n", |
| 484 | rport->port_id); | 506 | rport->port_id); |
| 485 | 507 | ||
| 508 | if (IS_ERR(fp)) { | ||
| 509 | fc_rport_error_retry(rport, fp); | ||
| 510 | goto err; | ||
| 511 | } | ||
| 512 | |||
| 486 | if (rdata->rp_state != RPORT_ST_PLOGI) { | 513 | if (rdata->rp_state != RPORT_ST_PLOGI) { |
| 487 | FC_DBG("Received a PLOGI response, but in state %s\n", | 514 | FC_DBG("Received a PLOGI response, but in state %s\n", |
| 488 | fc_rport_state(rport)); | 515 | fc_rport_state(rport)); |
| 489 | goto out; | 516 | goto out; |
| 490 | } | 517 | } |
| 491 | 518 | ||
| 492 | if (IS_ERR(fp)) { | ||
| 493 | fc_rport_error(rport, fp); | ||
| 494 | goto err; | ||
| 495 | } | ||
| 496 | |||
| 497 | op = fc_frame_payload_op(fp); | 519 | op = fc_frame_payload_op(fp); |
| 498 | if (op == ELS_LS_ACC && | 520 | if (op == ELS_LS_ACC && |
| 499 | (plp = fc_frame_payload_get(fp, sizeof(*plp))) != NULL) { | 521 | (plp = fc_frame_payload_get(fp, sizeof(*plp))) != NULL) { |
| @@ -522,7 +544,7 @@ static void fc_rport_plogi_resp(struct fc_seq *sp, struct fc_frame *fp, | |||
| 522 | else | 544 | else |
| 523 | fc_rport_enter_prli(rport); | 545 | fc_rport_enter_prli(rport); |
| 524 | } else | 546 | } else |
| 525 | fc_rport_error(rport, fp); | 547 | fc_rport_error_retry(rport, fp); |
| 526 | 548 | ||
| 527 | out: | 549 | out: |
| 528 | fc_frame_free(fp); | 550 | fc_frame_free(fp); |
| @@ -532,7 +554,7 @@ err: | |||
| 532 | } | 554 | } |
| 533 | 555 | ||
| 534 | /** | 556 | /** |
| 535 | * fc_rport_enter_plogi - Send Port Login (PLOGI) request to peer | 557 | * fc_rport_enter_plogi() - Send Port Login (PLOGI) request to peer |
| 536 | * @rport: Fibre Channel remote port to send PLOGI to | 558 | * @rport: Fibre Channel remote port to send PLOGI to |
| 537 | * | 559 | * |
| 538 | * Locking Note: The rport lock is expected to be held before calling | 560 | * Locking Note: The rport lock is expected to be held before calling |
| @@ -552,20 +574,20 @@ static void fc_rport_enter_plogi(struct fc_rport *rport) | |||
| 552 | rport->maxframe_size = FC_MIN_MAX_PAYLOAD; | 574 | rport->maxframe_size = FC_MIN_MAX_PAYLOAD; |
| 553 | fp = fc_frame_alloc(lport, sizeof(struct fc_els_flogi)); | 575 | fp = fc_frame_alloc(lport, sizeof(struct fc_els_flogi)); |
| 554 | if (!fp) { | 576 | if (!fp) { |
| 555 | fc_rport_error(rport, fp); | 577 | fc_rport_error_retry(rport, fp); |
| 556 | return; | 578 | return; |
| 557 | } | 579 | } |
| 558 | rdata->e_d_tov = lport->e_d_tov; | 580 | rdata->e_d_tov = lport->e_d_tov; |
| 559 | 581 | ||
| 560 | if (!lport->tt.elsct_send(lport, rport, fp, ELS_PLOGI, | 582 | if (!lport->tt.elsct_send(lport, rport, fp, ELS_PLOGI, |
| 561 | fc_rport_plogi_resp, rport, lport->e_d_tov)) | 583 | fc_rport_plogi_resp, rport, lport->e_d_tov)) |
| 562 | fc_rport_error(rport, fp); | 584 | fc_rport_error_retry(rport, fp); |
| 563 | else | 585 | else |
| 564 | get_device(&rport->dev); | 586 | get_device(&rport->dev); |
| 565 | } | 587 | } |
| 566 | 588 | ||
| 567 | /** | 589 | /** |
| 568 | * fc_rport_prli_resp - Process Login (PRLI) response handler | 590 | * fc_rport_prli_resp() - Process Login (PRLI) response handler |
| 569 | * @sp: current sequence in the PRLI exchange | 591 | * @sp: current sequence in the PRLI exchange |
| 570 | * @fp: response frame | 592 | * @fp: response frame |
| 571 | * @rp_arg: Fibre Channel remote port | 593 | * @rp_arg: Fibre Channel remote port |
| @@ -592,17 +614,17 @@ static void fc_rport_prli_resp(struct fc_seq *sp, struct fc_frame *fp, | |||
| 592 | FC_DEBUG_RPORT("Received a PRLI response from port (%6x)\n", | 614 | FC_DEBUG_RPORT("Received a PRLI response from port (%6x)\n", |
| 593 | rport->port_id); | 615 | rport->port_id); |
| 594 | 616 | ||
| 617 | if (IS_ERR(fp)) { | ||
| 618 | fc_rport_error_retry(rport, fp); | ||
| 619 | goto err; | ||
| 620 | } | ||
| 621 | |||
| 595 | if (rdata->rp_state != RPORT_ST_PRLI) { | 622 | if (rdata->rp_state != RPORT_ST_PRLI) { |
| 596 | FC_DBG("Received a PRLI response, but in state %s\n", | 623 | FC_DBG("Received a PRLI response, but in state %s\n", |
| 597 | fc_rport_state(rport)); | 624 | fc_rport_state(rport)); |
| 598 | goto out; | 625 | goto out; |
| 599 | } | 626 | } |
| 600 | 627 | ||
| 601 | if (IS_ERR(fp)) { | ||
| 602 | fc_rport_error(rport, fp); | ||
| 603 | goto err; | ||
| 604 | } | ||
| 605 | |||
| 606 | op = fc_frame_payload_op(fp); | 628 | op = fc_frame_payload_op(fp); |
| 607 | if (op == ELS_LS_ACC) { | 629 | if (op == ELS_LS_ACC) { |
| 608 | pp = fc_frame_payload_get(fp, sizeof(*pp)); | 630 | pp = fc_frame_payload_get(fp, sizeof(*pp)); |
| @@ -635,7 +657,7 @@ err: | |||
| 635 | } | 657 | } |
| 636 | 658 | ||
| 637 | /** | 659 | /** |
| 638 | * fc_rport_logo_resp - Logout (LOGO) response handler | 660 | * fc_rport_logo_resp() - Logout (LOGO) response handler |
| 639 | * @sp: current sequence in the LOGO exchange | 661 | * @sp: current sequence in the LOGO exchange |
| 640 | * @fp: response frame | 662 | * @fp: response frame |
| 641 | * @rp_arg: Fibre Channel remote port | 663 | * @rp_arg: Fibre Channel remote port |
| @@ -657,7 +679,7 @@ static void fc_rport_logo_resp(struct fc_seq *sp, struct fc_frame *fp, | |||
| 657 | rport->port_id); | 679 | rport->port_id); |
| 658 | 680 | ||
| 659 | if (IS_ERR(fp)) { | 681 | if (IS_ERR(fp)) { |
| 660 | fc_rport_error(rport, fp); | 682 | fc_rport_error_retry(rport, fp); |
| 661 | goto err; | 683 | goto err; |
| 662 | } | 684 | } |
| 663 | 685 | ||
| @@ -684,7 +706,7 @@ err: | |||
| 684 | } | 706 | } |
| 685 | 707 | ||
| 686 | /** | 708 | /** |
| 687 | * fc_rport_enter_prli - Send Process Login (PRLI) request to peer | 709 | * fc_rport_enter_prli() - Send Process Login (PRLI) request to peer |
| 688 | * @rport: Fibre Channel remote port to send PRLI to | 710 | * @rport: Fibre Channel remote port to send PRLI to |
| 689 | * | 711 | * |
| 690 | * Locking Note: The rport lock is expected to be held before calling | 712 | * Locking Note: The rport lock is expected to be held before calling |
| @@ -707,19 +729,19 @@ static void fc_rport_enter_prli(struct fc_rport *rport) | |||
| 707 | 729 | ||
| 708 | fp = fc_frame_alloc(lport, sizeof(*pp)); | 730 | fp = fc_frame_alloc(lport, sizeof(*pp)); |
| 709 | if (!fp) { | 731 | if (!fp) { |
| 710 | fc_rport_error(rport, fp); | 732 | fc_rport_error_retry(rport, fp); |
| 711 | return; | 733 | return; |
| 712 | } | 734 | } |
| 713 | 735 | ||
| 714 | if (!lport->tt.elsct_send(lport, rport, fp, ELS_PRLI, | 736 | if (!lport->tt.elsct_send(lport, rport, fp, ELS_PRLI, |
| 715 | fc_rport_prli_resp, rport, lport->e_d_tov)) | 737 | fc_rport_prli_resp, rport, lport->e_d_tov)) |
| 716 | fc_rport_error(rport, fp); | 738 | fc_rport_error_retry(rport, fp); |
| 717 | else | 739 | else |
| 718 | get_device(&rport->dev); | 740 | get_device(&rport->dev); |
| 719 | } | 741 | } |
| 720 | 742 | ||
| 721 | /** | 743 | /** |
| 722 | * fc_rport_els_rtv_resp - Request Timeout Value response handler | 744 | * fc_rport_els_rtv_resp() - Request Timeout Value response handler |
| 723 | * @sp: current sequence in the RTV exchange | 745 | * @sp: current sequence in the RTV exchange |
| 724 | * @fp: response frame | 746 | * @fp: response frame |
| 725 | * @rp_arg: Fibre Channel remote port | 747 | * @rp_arg: Fibre Channel remote port |
| @@ -742,17 +764,17 @@ static void fc_rport_rtv_resp(struct fc_seq *sp, struct fc_frame *fp, | |||
| 742 | FC_DEBUG_RPORT("Received a RTV response from port (%6x)\n", | 764 | FC_DEBUG_RPORT("Received a RTV response from port (%6x)\n", |
| 743 | rport->port_id); | 765 | rport->port_id); |
| 744 | 766 | ||
| 767 | if (IS_ERR(fp)) { | ||
| 768 | fc_rport_error(rport, fp); | ||
| 769 | goto err; | ||
| 770 | } | ||
| 771 | |||
| 745 | if (rdata->rp_state != RPORT_ST_RTV) { | 772 | if (rdata->rp_state != RPORT_ST_RTV) { |
| 746 | FC_DBG("Received a RTV response, but in state %s\n", | 773 | FC_DBG("Received a RTV response, but in state %s\n", |
| 747 | fc_rport_state(rport)); | 774 | fc_rport_state(rport)); |
| 748 | goto out; | 775 | goto out; |
| 749 | } | 776 | } |
| 750 | 777 | ||
| 751 | if (IS_ERR(fp)) { | ||
| 752 | fc_rport_error(rport, fp); | ||
| 753 | goto err; | ||
| 754 | } | ||
| 755 | |||
| 756 | op = fc_frame_payload_op(fp); | 778 | op = fc_frame_payload_op(fp); |
| 757 | if (op == ELS_LS_ACC) { | 779 | if (op == ELS_LS_ACC) { |
| 758 | struct fc_els_rtv_acc *rtv; | 780 | struct fc_els_rtv_acc *rtv; |
| @@ -785,7 +807,7 @@ err: | |||
| 785 | } | 807 | } |
| 786 | 808 | ||
| 787 | /** | 809 | /** |
| 788 | * fc_rport_enter_rtv - Send Request Timeout Value (RTV) request to peer | 810 | * fc_rport_enter_rtv() - Send Request Timeout Value (RTV) request to peer |
| 789 | * @rport: Fibre Channel remote port to send RTV to | 811 | * @rport: Fibre Channel remote port to send RTV to |
| 790 | * | 812 | * |
| 791 | * Locking Note: The rport lock is expected to be held before calling | 813 | * Locking Note: The rport lock is expected to be held before calling |
| @@ -804,19 +826,19 @@ static void fc_rport_enter_rtv(struct fc_rport *rport) | |||
| 804 | 826 | ||
| 805 | fp = fc_frame_alloc(lport, sizeof(struct fc_els_rtv)); | 827 | fp = fc_frame_alloc(lport, sizeof(struct fc_els_rtv)); |
| 806 | if (!fp) { | 828 | if (!fp) { |
| 807 | fc_rport_error(rport, fp); | 829 | fc_rport_error_retry(rport, fp); |
| 808 | return; | 830 | return; |
| 809 | } | 831 | } |
| 810 | 832 | ||
| 811 | if (!lport->tt.elsct_send(lport, rport, fp, ELS_RTV, | 833 | if (!lport->tt.elsct_send(lport, rport, fp, ELS_RTV, |
| 812 | fc_rport_rtv_resp, rport, lport->e_d_tov)) | 834 | fc_rport_rtv_resp, rport, lport->e_d_tov)) |
| 813 | fc_rport_error(rport, fp); | 835 | fc_rport_error_retry(rport, fp); |
| 814 | else | 836 | else |
| 815 | get_device(&rport->dev); | 837 | get_device(&rport->dev); |
| 816 | } | 838 | } |
| 817 | 839 | ||
| 818 | /** | 840 | /** |
| 819 | * fc_rport_enter_logo - Send Logout (LOGO) request to peer | 841 | * fc_rport_enter_logo() - Send Logout (LOGO) request to peer |
| 820 | * @rport: Fibre Channel remote port to send LOGO to | 842 | * @rport: Fibre Channel remote port to send LOGO to |
| 821 | * | 843 | * |
| 822 | * Locking Note: The rport lock is expected to be held before calling | 844 | * Locking Note: The rport lock is expected to be held before calling |
| @@ -835,20 +857,20 @@ static void fc_rport_enter_logo(struct fc_rport *rport) | |||
| 835 | 857 | ||
| 836 | fp = fc_frame_alloc(lport, sizeof(struct fc_els_logo)); | 858 | fp = fc_frame_alloc(lport, sizeof(struct fc_els_logo)); |
| 837 | if (!fp) { | 859 | if (!fp) { |
| 838 | fc_rport_error(rport, fp); | 860 | fc_rport_error_retry(rport, fp); |
| 839 | return; | 861 | return; |
| 840 | } | 862 | } |
| 841 | 863 | ||
| 842 | if (!lport->tt.elsct_send(lport, rport, fp, ELS_LOGO, | 864 | if (!lport->tt.elsct_send(lport, rport, fp, ELS_LOGO, |
| 843 | fc_rport_logo_resp, rport, lport->e_d_tov)) | 865 | fc_rport_logo_resp, rport, lport->e_d_tov)) |
| 844 | fc_rport_error(rport, fp); | 866 | fc_rport_error_retry(rport, fp); |
| 845 | else | 867 | else |
| 846 | get_device(&rport->dev); | 868 | get_device(&rport->dev); |
| 847 | } | 869 | } |
| 848 | 870 | ||
| 849 | 871 | ||
| 850 | /** | 872 | /** |
| 851 | * fc_rport_recv_req - Receive a request from a rport | 873 | * fc_rport_recv_req() - Receive a request from a rport |
| 852 | * @sp: current sequence in the PLOGI exchange | 874 | * @sp: current sequence in the PLOGI exchange |
| 853 | * @fp: response frame | 875 | * @fp: response frame |
| 854 | * @rp_arg: Fibre Channel remote port | 876 | * @rp_arg: Fibre Channel remote port |
| @@ -909,7 +931,7 @@ void fc_rport_recv_req(struct fc_seq *sp, struct fc_frame *fp, | |||
| 909 | } | 931 | } |
| 910 | 932 | ||
| 911 | /** | 933 | /** |
| 912 | * fc_rport_recv_plogi_req - Handle incoming Port Login (PLOGI) request | 934 | * fc_rport_recv_plogi_req() - Handle incoming Port Login (PLOGI) request |
| 913 | * @rport: Fibre Channel remote port that initiated PLOGI | 935 | * @rport: Fibre Channel remote port that initiated PLOGI |
| 914 | * @sp: current sequence in the PLOGI exchange | 936 | * @sp: current sequence in the PLOGI exchange |
| 915 | * @fp: PLOGI request frame | 937 | * @fp: PLOGI request frame |
| @@ -1031,7 +1053,7 @@ static void fc_rport_recv_plogi_req(struct fc_rport *rport, | |||
| 1031 | } | 1053 | } |
| 1032 | 1054 | ||
| 1033 | /** | 1055 | /** |
| 1034 | * fc_rport_recv_prli_req - Handle incoming Process Login (PRLI) request | 1056 | * fc_rport_recv_prli_req() - Handle incoming Process Login (PRLI) request |
| 1035 | * @rport: Fibre Channel remote port that initiated PRLI | 1057 | * @rport: Fibre Channel remote port that initiated PRLI |
| 1036 | * @sp: current sequence in the PRLI exchange | 1058 | * @sp: current sequence in the PRLI exchange |
| 1037 | * @fp: PRLI request frame | 1059 | * @fp: PRLI request frame |
| @@ -1182,7 +1204,7 @@ static void fc_rport_recv_prli_req(struct fc_rport *rport, | |||
| 1182 | } | 1204 | } |
| 1183 | 1205 | ||
| 1184 | /** | 1206 | /** |
| 1185 | * fc_rport_recv_prlo_req - Handle incoming Process Logout (PRLO) request | 1207 | * fc_rport_recv_prlo_req() - Handle incoming Process Logout (PRLO) request |
| 1186 | * @rport: Fibre Channel remote port that initiated PRLO | 1208 | * @rport: Fibre Channel remote port that initiated PRLO |
| 1187 | * @sp: current sequence in the PRLO exchange | 1209 | * @sp: current sequence in the PRLO exchange |
| 1188 | * @fp: PRLO request frame | 1210 | * @fp: PRLO request frame |
| @@ -1213,7 +1235,7 @@ static void fc_rport_recv_prlo_req(struct fc_rport *rport, struct fc_seq *sp, | |||
| 1213 | } | 1235 | } |
| 1214 | 1236 | ||
| 1215 | /** | 1237 | /** |
| 1216 | * fc_rport_recv_logo_req - Handle incoming Logout (LOGO) request | 1238 | * fc_rport_recv_logo_req() - Handle incoming Logout (LOGO) request |
| 1217 | * @rport: Fibre Channel remote port that initiated LOGO | 1239 | * @rport: Fibre Channel remote port that initiated LOGO |
| 1218 | * @sp: current sequence in the LOGO exchange | 1240 | * @sp: current sequence in the LOGO exchange |
| 1219 | * @fp: LOGO request frame | 1241 | * @fp: LOGO request frame |
| @@ -1249,6 +1271,9 @@ static void fc_rport_flush_queue(void) | |||
| 1249 | 1271 | ||
| 1250 | int fc_rport_init(struct fc_lport *lport) | 1272 | int fc_rport_init(struct fc_lport *lport) |
| 1251 | { | 1273 | { |
| 1274 | if (!lport->tt.rport_create) | ||
| 1275 | lport->tt.rport_create = fc_rport_rogue_create; | ||
| 1276 | |||
| 1252 | if (!lport->tt.rport_login) | 1277 | if (!lport->tt.rport_login) |
| 1253 | lport->tt.rport_login = fc_rport_login; | 1278 | lport->tt.rport_login = fc_rport_login; |
| 1254 | 1279 | ||
| @@ -1285,7 +1310,7 @@ void fc_rport_terminate_io(struct fc_rport *rport) | |||
| 1285 | struct fc_rport_libfc_priv *rdata = rport->dd_data; | 1310 | struct fc_rport_libfc_priv *rdata = rport->dd_data; |
| 1286 | struct fc_lport *lport = rdata->local_port; | 1311 | struct fc_lport *lport = rdata->local_port; |
| 1287 | 1312 | ||
| 1288 | lport->tt.exch_mgr_reset(lport->emp, 0, rport->port_id); | 1313 | lport->tt.exch_mgr_reset(lport, 0, rport->port_id); |
| 1289 | lport->tt.exch_mgr_reset(lport->emp, rport->port_id, 0); | 1314 | lport->tt.exch_mgr_reset(lport, rport->port_id, 0); |
| 1290 | } | 1315 | } |
| 1291 | EXPORT_SYMBOL(fc_rport_terminate_io); | 1316 | EXPORT_SYMBOL(fc_rport_terminate_io); |
diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c index f4c57227ec18..ee9d40152430 100644 --- a/drivers/scsi/qla2xxx/qla_attr.c +++ b/drivers/scsi/qla2xxx/qla_attr.c | |||
| @@ -244,12 +244,6 @@ qla2x00_sysfs_write_optrom_ctl(struct kobject *kobj, | |||
| 244 | if (ha->optrom_state != QLA_SWAITING) | 244 | if (ha->optrom_state != QLA_SWAITING) |
| 245 | break; | 245 | break; |
| 246 | 246 | ||
| 247 | if (start & 0xfff) { | ||
| 248 | qla_printk(KERN_WARNING, ha, | ||
| 249 | "Invalid start region 0x%x/0x%x.\n", start, size); | ||
| 250 | return -EINVAL; | ||
| 251 | } | ||
| 252 | |||
| 253 | ha->optrom_region_start = start; | 247 | ha->optrom_region_start = start; |
| 254 | ha->optrom_region_size = start + size > ha->optrom_size ? | 248 | ha->optrom_region_size = start + size > ha->optrom_size ? |
| 255 | ha->optrom_size - start : size; | 249 | ha->optrom_size - start : size; |
| @@ -303,8 +297,7 @@ qla2x00_sysfs_write_optrom_ctl(struct kobject *kobj, | |||
| 303 | else if (start == (ha->flt_region_boot * 4) || | 297 | else if (start == (ha->flt_region_boot * 4) || |
| 304 | start == (ha->flt_region_fw * 4)) | 298 | start == (ha->flt_region_fw * 4)) |
| 305 | valid = 1; | 299 | valid = 1; |
| 306 | else if ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && | 300 | else if (IS_QLA25XX(ha) || IS_QLA81XX(ha)) |
| 307 | start == (ha->flt_region_vpd_nvram * 4)) | ||
| 308 | valid = 1; | 301 | valid = 1; |
| 309 | if (!valid) { | 302 | if (!valid) { |
| 310 | qla_printk(KERN_WARNING, ha, | 303 | qla_printk(KERN_WARNING, ha, |
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c index 986501759ad4..87f9abc71460 100644 --- a/drivers/scsi/qla2xxx/qla_init.c +++ b/drivers/scsi/qla2xxx/qla_init.c | |||
| @@ -1308,8 +1308,12 @@ qla2x00_init_rings(scsi_qla_host_t *vha) | |||
| 1308 | 1308 | ||
| 1309 | DEBUG(printk("scsi(%ld): Issue init firmware.\n", vha->host_no)); | 1309 | DEBUG(printk("scsi(%ld): Issue init firmware.\n", vha->host_no)); |
| 1310 | 1310 | ||
| 1311 | if (ha->flags.npiv_supported) | 1311 | if (ha->flags.npiv_supported) { |
| 1312 | if (ha->operating_mode == LOOP) | ||
| 1313 | ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1; | ||
| 1312 | mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports); | 1314 | mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports); |
| 1315 | } | ||
| 1316 | |||
| 1313 | 1317 | ||
| 1314 | mid_init_cb->options = __constant_cpu_to_le16(BIT_1); | 1318 | mid_init_cb->options = __constant_cpu_to_le16(BIT_1); |
| 1315 | 1319 | ||
| @@ -2610,6 +2614,7 @@ qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha, | |||
| 2610 | port_id_t wrap, nxt_d_id; | 2614 | port_id_t wrap, nxt_d_id; |
| 2611 | struct qla_hw_data *ha = vha->hw; | 2615 | struct qla_hw_data *ha = vha->hw; |
| 2612 | struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev); | 2616 | struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev); |
| 2617 | struct scsi_qla_host *tvp; | ||
| 2613 | 2618 | ||
| 2614 | rval = QLA_SUCCESS; | 2619 | rval = QLA_SUCCESS; |
| 2615 | 2620 | ||
| @@ -2709,7 +2714,7 @@ qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha, | |||
| 2709 | /* Bypass virtual ports of the same host. */ | 2714 | /* Bypass virtual ports of the same host. */ |
| 2710 | found = 0; | 2715 | found = 0; |
| 2711 | if (ha->num_vhosts) { | 2716 | if (ha->num_vhosts) { |
| 2712 | list_for_each_entry(vp, &ha->vp_list, list) { | 2717 | list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { |
| 2713 | if (new_fcport->d_id.b24 == vp->d_id.b24) { | 2718 | if (new_fcport->d_id.b24 == vp->d_id.b24) { |
| 2714 | found = 1; | 2719 | found = 1; |
| 2715 | break; | 2720 | break; |
| @@ -2832,6 +2837,7 @@ qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev) | |||
| 2832 | uint16_t first_loop_id; | 2837 | uint16_t first_loop_id; |
| 2833 | struct qla_hw_data *ha = vha->hw; | 2838 | struct qla_hw_data *ha = vha->hw; |
| 2834 | struct scsi_qla_host *vp; | 2839 | struct scsi_qla_host *vp; |
| 2840 | struct scsi_qla_host *tvp; | ||
| 2835 | 2841 | ||
| 2836 | rval = QLA_SUCCESS; | 2842 | rval = QLA_SUCCESS; |
| 2837 | 2843 | ||
| @@ -2856,7 +2862,7 @@ qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev) | |||
| 2856 | /* Check for loop ID being already in use. */ | 2862 | /* Check for loop ID being already in use. */ |
| 2857 | found = 0; | 2863 | found = 0; |
| 2858 | fcport = NULL; | 2864 | fcport = NULL; |
| 2859 | list_for_each_entry(vp, &ha->vp_list, list) { | 2865 | list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { |
| 2860 | list_for_each_entry(fcport, &vp->vp_fcports, list) { | 2866 | list_for_each_entry(fcport, &vp->vp_fcports, list) { |
| 2861 | if (fcport->loop_id == dev->loop_id && | 2867 | if (fcport->loop_id == dev->loop_id && |
| 2862 | fcport != dev) { | 2868 | fcport != dev) { |
| @@ -3291,6 +3297,7 @@ qla2x00_abort_isp(scsi_qla_host_t *vha) | |||
| 3291 | uint8_t status = 0; | 3297 | uint8_t status = 0; |
| 3292 | struct qla_hw_data *ha = vha->hw; | 3298 | struct qla_hw_data *ha = vha->hw; |
| 3293 | struct scsi_qla_host *vp; | 3299 | struct scsi_qla_host *vp; |
| 3300 | struct scsi_qla_host *tvp; | ||
| 3294 | struct req_que *req = ha->req_q_map[0]; | 3301 | struct req_que *req = ha->req_q_map[0]; |
| 3295 | 3302 | ||
| 3296 | if (vha->flags.online) { | 3303 | if (vha->flags.online) { |
| @@ -3306,7 +3313,7 @@ qla2x00_abort_isp(scsi_qla_host_t *vha) | |||
| 3306 | if (atomic_read(&vha->loop_state) != LOOP_DOWN) { | 3313 | if (atomic_read(&vha->loop_state) != LOOP_DOWN) { |
| 3307 | atomic_set(&vha->loop_state, LOOP_DOWN); | 3314 | atomic_set(&vha->loop_state, LOOP_DOWN); |
| 3308 | qla2x00_mark_all_devices_lost(vha, 0); | 3315 | qla2x00_mark_all_devices_lost(vha, 0); |
| 3309 | list_for_each_entry(vp, &ha->vp_list, list) | 3316 | list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) |
| 3310 | qla2x00_mark_all_devices_lost(vp, 0); | 3317 | qla2x00_mark_all_devices_lost(vp, 0); |
| 3311 | } else { | 3318 | } else { |
| 3312 | if (!atomic_read(&vha->loop_down_timer)) | 3319 | if (!atomic_read(&vha->loop_down_timer)) |
| @@ -3403,7 +3410,7 @@ qla2x00_abort_isp(scsi_qla_host_t *vha) | |||
| 3403 | DEBUG(printk(KERN_INFO | 3410 | DEBUG(printk(KERN_INFO |
| 3404 | "qla2x00_abort_isp(%ld): succeeded.\n", | 3411 | "qla2x00_abort_isp(%ld): succeeded.\n", |
| 3405 | vha->host_no)); | 3412 | vha->host_no)); |
| 3406 | list_for_each_entry(vp, &ha->vp_list, list) { | 3413 | list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { |
| 3407 | if (vp->vp_idx) | 3414 | if (vp->vp_idx) |
| 3408 | qla2x00_vp_abort_isp(vp); | 3415 | qla2x00_vp_abort_isp(vp); |
| 3409 | } | 3416 | } |
| @@ -3428,7 +3435,7 @@ qla2x00_abort_isp(scsi_qla_host_t *vha) | |||
| 3428 | static int | 3435 | static int |
| 3429 | qla2x00_restart_isp(scsi_qla_host_t *vha) | 3436 | qla2x00_restart_isp(scsi_qla_host_t *vha) |
| 3430 | { | 3437 | { |
| 3431 | uint8_t status = 0; | 3438 | int status = 0; |
| 3432 | uint32_t wait_time; | 3439 | uint32_t wait_time; |
| 3433 | struct qla_hw_data *ha = vha->hw; | 3440 | struct qla_hw_data *ha = vha->hw; |
| 3434 | struct req_que *req = ha->req_q_map[0]; | 3441 | struct req_que *req = ha->req_q_map[0]; |
diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c index 4c7504cb3990..4aab7acf7525 100644 --- a/drivers/scsi/qla2xxx/qla_mbx.c +++ b/drivers/scsi/qla2xxx/qla_mbx.c | |||
| @@ -2685,6 +2685,7 @@ qla24xx_report_id_acquisition(scsi_qla_host_t *vha, | |||
| 2685 | uint16_t stat = le16_to_cpu(rptid_entry->vp_idx); | 2685 | uint16_t stat = le16_to_cpu(rptid_entry->vp_idx); |
| 2686 | struct qla_hw_data *ha = vha->hw; | 2686 | struct qla_hw_data *ha = vha->hw; |
| 2687 | scsi_qla_host_t *vp; | 2687 | scsi_qla_host_t *vp; |
| 2688 | scsi_qla_host_t *tvp; | ||
| 2688 | 2689 | ||
| 2689 | if (rptid_entry->entry_status != 0) | 2690 | if (rptid_entry->entry_status != 0) |
| 2690 | return; | 2691 | return; |
| @@ -2710,7 +2711,7 @@ qla24xx_report_id_acquisition(scsi_qla_host_t *vha, | |||
| 2710 | if (MSB(stat) == 1) | 2711 | if (MSB(stat) == 1) |
| 2711 | return; | 2712 | return; |
| 2712 | 2713 | ||
| 2713 | list_for_each_entry(vp, &ha->vp_list, list) | 2714 | list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) |
| 2714 | if (vp_idx == vp->vp_idx) | 2715 | if (vp_idx == vp->vp_idx) |
| 2715 | break; | 2716 | break; |
| 2716 | if (!vp) | 2717 | if (!vp) |
diff --git a/drivers/scsi/qla2xxx/qla_mid.c b/drivers/scsi/qla2xxx/qla_mid.c index 3f23932210c4..785c61279e6e 100644 --- a/drivers/scsi/qla2xxx/qla_mid.c +++ b/drivers/scsi/qla2xxx/qla_mid.c | |||
| @@ -69,9 +69,10 @@ static scsi_qla_host_t * | |||
| 69 | qla24xx_find_vhost_by_name(struct qla_hw_data *ha, uint8_t *port_name) | 69 | qla24xx_find_vhost_by_name(struct qla_hw_data *ha, uint8_t *port_name) |
| 70 | { | 70 | { |
| 71 | scsi_qla_host_t *vha; | 71 | scsi_qla_host_t *vha; |
| 72 | struct scsi_qla_host *tvha; | ||
| 72 | 73 | ||
| 73 | /* Locate matching device in database. */ | 74 | /* Locate matching device in database. */ |
| 74 | list_for_each_entry(vha, &ha->vp_list, list) { | 75 | list_for_each_entry_safe(vha, tvha, &ha->vp_list, list) { |
| 75 | if (!memcmp(port_name, vha->port_name, WWN_SIZE)) | 76 | if (!memcmp(port_name, vha->port_name, WWN_SIZE)) |
| 76 | return vha; | 77 | return vha; |
| 77 | } | 78 | } |
| @@ -194,11 +195,11 @@ qla24xx_configure_vp(scsi_qla_host_t *vha) | |||
| 194 | void | 195 | void |
| 195 | qla2x00_alert_all_vps(struct rsp_que *rsp, uint16_t *mb) | 196 | qla2x00_alert_all_vps(struct rsp_que *rsp, uint16_t *mb) |
| 196 | { | 197 | { |
| 197 | scsi_qla_host_t *vha; | 198 | scsi_qla_host_t *vha, *tvha; |
| 198 | struct qla_hw_data *ha = rsp->hw; | 199 | struct qla_hw_data *ha = rsp->hw; |
| 199 | int i = 0; | 200 | int i = 0; |
| 200 | 201 | ||
| 201 | list_for_each_entry(vha, &ha->vp_list, list) { | 202 | list_for_each_entry_safe(vha, tvha, &ha->vp_list, list) { |
| 202 | if (vha->vp_idx) { | 203 | if (vha->vp_idx) { |
| 203 | switch (mb[0]) { | 204 | switch (mb[0]) { |
| 204 | case MBA_LIP_OCCURRED: | 205 | case MBA_LIP_OCCURRED: |
| @@ -300,6 +301,7 @@ qla2x00_do_dpc_all_vps(scsi_qla_host_t *vha) | |||
| 300 | int ret; | 301 | int ret; |
| 301 | struct qla_hw_data *ha = vha->hw; | 302 | struct qla_hw_data *ha = vha->hw; |
| 302 | scsi_qla_host_t *vp; | 303 | scsi_qla_host_t *vp; |
| 304 | struct scsi_qla_host *tvp; | ||
| 303 | 305 | ||
| 304 | if (vha->vp_idx) | 306 | if (vha->vp_idx) |
| 305 | return; | 307 | return; |
| @@ -308,7 +310,7 @@ qla2x00_do_dpc_all_vps(scsi_qla_host_t *vha) | |||
| 308 | 310 | ||
| 309 | clear_bit(VP_DPC_NEEDED, &vha->dpc_flags); | 311 | clear_bit(VP_DPC_NEEDED, &vha->dpc_flags); |
| 310 | 312 | ||
| 311 | list_for_each_entry(vp, &ha->vp_list, list) { | 313 | list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { |
| 312 | if (vp->vp_idx) | 314 | if (vp->vp_idx) |
| 313 | ret = qla2x00_do_dpc_vp(vp); | 315 | ret = qla2x00_do_dpc_vp(vp); |
| 314 | } | 316 | } |
diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c index 2f5f72531e23..3ddfa889e949 100644 --- a/drivers/scsi/qla2xxx/qla_os.c +++ b/drivers/scsi/qla2xxx/qla_os.c | |||
| @@ -2222,10 +2222,6 @@ qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, | |||
| 2222 | { | 2222 | { |
| 2223 | char name[16]; | 2223 | char name[16]; |
| 2224 | 2224 | ||
| 2225 | ha->init_cb_size = sizeof(init_cb_t); | ||
| 2226 | if (IS_QLA2XXX_MIDTYPE(ha)) | ||
| 2227 | ha->init_cb_size = sizeof(struct mid_init_cb_24xx); | ||
| 2228 | |||
| 2229 | ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, | 2225 | ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, |
| 2230 | &ha->init_cb_dma, GFP_KERNEL); | 2226 | &ha->init_cb_dma, GFP_KERNEL); |
| 2231 | if (!ha->init_cb) | 2227 | if (!ha->init_cb) |
| @@ -2568,7 +2564,7 @@ qla2x00_do_work(struct scsi_qla_host *vha) | |||
| 2568 | void qla2x00_relogin(struct scsi_qla_host *vha) | 2564 | void qla2x00_relogin(struct scsi_qla_host *vha) |
| 2569 | { | 2565 | { |
| 2570 | fc_port_t *fcport; | 2566 | fc_port_t *fcport; |
| 2571 | uint8_t status; | 2567 | int status; |
| 2572 | uint16_t next_loopid = 0; | 2568 | uint16_t next_loopid = 0; |
| 2573 | struct qla_hw_data *ha = vha->hw; | 2569 | struct qla_hw_data *ha = vha->hw; |
| 2574 | 2570 | ||
diff --git a/drivers/scsi/qla2xxx/qla_version.h b/drivers/scsi/qla2xxx/qla_version.h index 79f7053da99b..a772eab2f0ea 100644 --- a/drivers/scsi/qla2xxx/qla_version.h +++ b/drivers/scsi/qla2xxx/qla_version.h | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | /* | 7 | /* |
| 8 | * Driver version | 8 | * Driver version |
| 9 | */ | 9 | */ |
| 10 | #define QLA2XXX_VERSION "8.03.00-k3" | 10 | #define QLA2XXX_VERSION "8.03.00-k4" |
| 11 | 11 | ||
| 12 | #define QLA_DRIVER_MAJOR_VER 8 | 12 | #define QLA_DRIVER_MAJOR_VER 8 |
| 13 | #define QLA_DRIVER_MINOR_VER 3 | 13 | #define QLA_DRIVER_MINOR_VER 3 |
diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c index 55310dbc10a6..4970ae4a62d6 100644 --- a/drivers/scsi/sd.c +++ b/drivers/scsi/sd.c | |||
| @@ -1167,23 +1167,19 @@ sd_spinup_disk(struct scsi_disk *sdkp) | |||
| 1167 | /* | 1167 | /* |
| 1168 | * The device does not want the automatic start to be issued. | 1168 | * The device does not want the automatic start to be issued. |
| 1169 | */ | 1169 | */ |
| 1170 | if (sdkp->device->no_start_on_add) { | 1170 | if (sdkp->device->no_start_on_add) |
| 1171 | break; | 1171 | break; |
| 1172 | } | ||
| 1173 | |||
| 1174 | /* | ||
| 1175 | * If manual intervention is required, or this is an | ||
| 1176 | * absent USB storage device, a spinup is meaningless. | ||
| 1177 | */ | ||
| 1178 | if (sense_valid && | ||
| 1179 | sshdr.sense_key == NOT_READY && | ||
| 1180 | sshdr.asc == 4 && sshdr.ascq == 3) { | ||
| 1181 | break; /* manual intervention required */ | ||
| 1182 | 1172 | ||
| 1183 | /* | 1173 | if (sense_valid && sshdr.sense_key == NOT_READY) { |
| 1184 | * Issue command to spin up drive when not ready | 1174 | if (sshdr.asc == 4 && sshdr.ascq == 3) |
| 1185 | */ | 1175 | break; /* manual intervention required */ |
| 1186 | } else if (sense_valid && sshdr.sense_key == NOT_READY) { | 1176 | if (sshdr.asc == 4 && sshdr.ascq == 0xb) |
| 1177 | break; /* standby */ | ||
| 1178 | if (sshdr.asc == 4 && sshdr.ascq == 0xc) | ||
| 1179 | break; /* unavailable */ | ||
| 1180 | /* | ||
| 1181 | * Issue command to spin up drive when not ready | ||
| 1182 | */ | ||
| 1187 | if (!spintime) { | 1183 | if (!spintime) { |
| 1188 | sd_printk(KERN_NOTICE, sdkp, "Spinning up disk..."); | 1184 | sd_printk(KERN_NOTICE, sdkp, "Spinning up disk..."); |
| 1189 | cmd[0] = START_STOP; | 1185 | cmd[0] = START_STOP; |
diff --git a/drivers/scsi/zalon.c b/drivers/scsi/zalon.c index a8d61a62522e..97f3158fa7b5 100644 --- a/drivers/scsi/zalon.c +++ b/drivers/scsi/zalon.c | |||
| @@ -137,7 +137,7 @@ zalon_probe(struct parisc_device *dev) | |||
| 137 | goto fail; | 137 | goto fail; |
| 138 | 138 | ||
| 139 | if (request_irq(dev->irq, ncr53c8xx_intr, IRQF_SHARED, "zalon", host)) { | 139 | if (request_irq(dev->irq, ncr53c8xx_intr, IRQF_SHARED, "zalon", host)) { |
| 140 | dev_printk(KERN_ERR, dev, "irq problem with %d, detaching\n ", | 140 | dev_printk(KERN_ERR, &dev->dev, "irq problem with %d, detaching\n ", |
| 141 | dev->irq); | 141 | dev->irq); |
| 142 | goto fail; | 142 | goto fail; |
| 143 | } | 143 | } |
diff --git a/drivers/serial/21285.c b/drivers/serial/21285.c index f31c6698419c..cb6d85d7ff43 100644 --- a/drivers/serial/21285.c +++ b/drivers/serial/21285.c | |||
| @@ -14,8 +14,8 @@ | |||
| 14 | #include <linux/tty_flip.h> | 14 | #include <linux/tty_flip.h> |
| 15 | #include <linux/serial_core.h> | 15 | #include <linux/serial_core.h> |
| 16 | #include <linux/serial.h> | 16 | #include <linux/serial.h> |
| 17 | #include <linux/io.h> | ||
| 17 | 18 | ||
| 18 | #include <asm/io.h> | ||
| 19 | #include <asm/irq.h> | 19 | #include <asm/irq.h> |
| 20 | #include <asm/mach-types.h> | 20 | #include <asm/mach-types.h> |
| 21 | #include <asm/hardware/dec21285.h> | 21 | #include <asm/hardware/dec21285.h> |
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 7d7f576da202..9be11b0963f2 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig | |||
| @@ -628,7 +628,7 @@ config SERIAL_MPSC_CONSOLE | |||
| 628 | 628 | ||
| 629 | config SERIAL_PXA | 629 | config SERIAL_PXA |
| 630 | bool "PXA serial port support" | 630 | bool "PXA serial port support" |
| 631 | depends on ARM && ARCH_PXA | 631 | depends on ARCH_PXA || ARCH_MMP |
| 632 | select SERIAL_CORE | 632 | select SERIAL_CORE |
| 633 | help | 633 | help |
| 634 | If you have a machine based on an Intel XScale PXA2xx CPU you | 634 | If you have a machine based on an Intel XScale PXA2xx CPU you |
diff --git a/drivers/serial/clps711x.c b/drivers/serial/clps711x.c index 459f3420a429..80e76426131d 100644 --- a/drivers/serial/clps711x.c +++ b/drivers/serial/clps711x.c | |||
| @@ -38,9 +38,9 @@ | |||
| 38 | #include <linux/tty_flip.h> | 38 | #include <linux/tty_flip.h> |
| 39 | #include <linux/serial_core.h> | 39 | #include <linux/serial_core.h> |
| 40 | #include <linux/serial.h> | 40 | #include <linux/serial.h> |
| 41 | #include <linux/io.h> | ||
| 41 | 42 | ||
| 42 | #include <mach/hardware.h> | 43 | #include <mach/hardware.h> |
| 43 | #include <asm/io.h> | ||
| 44 | #include <asm/irq.h> | 44 | #include <asm/irq.h> |
| 45 | #include <asm/hardware/clps7111.h> | 45 | #include <asm/hardware/clps7111.h> |
| 46 | 46 | ||
diff --git a/drivers/serial/imx.c b/drivers/serial/imx.c index a50954612b60..9f460b175c50 100644 --- a/drivers/serial/imx.c +++ b/drivers/serial/imx.c | |||
| @@ -1129,7 +1129,7 @@ static int serial_imx_probe(struct platform_device *pdev) | |||
| 1129 | sport->timer.function = imx_timeout; | 1129 | sport->timer.function = imx_timeout; |
| 1130 | sport->timer.data = (unsigned long)sport; | 1130 | sport->timer.data = (unsigned long)sport; |
| 1131 | 1131 | ||
| 1132 | sport->clk = clk_get(&pdev->dev, "uart_clk"); | 1132 | sport->clk = clk_get(&pdev->dev, "uart"); |
| 1133 | if (IS_ERR(sport->clk)) { | 1133 | if (IS_ERR(sport->clk)) { |
| 1134 | ret = PTR_ERR(sport->clk); | 1134 | ret = PTR_ERR(sport->clk); |
| 1135 | goto unmap; | 1135 | goto unmap; |
diff --git a/drivers/serial/pxa.c b/drivers/serial/pxa.c index f6e3b86bb0be..a48a8a13d87b 100644 --- a/drivers/serial/pxa.c +++ b/drivers/serial/pxa.c | |||
| @@ -43,13 +43,7 @@ | |||
| 43 | #include <linux/tty_flip.h> | 43 | #include <linux/tty_flip.h> |
| 44 | #include <linux/serial_core.h> | 44 | #include <linux/serial_core.h> |
| 45 | #include <linux/clk.h> | 45 | #include <linux/clk.h> |
| 46 | 46 | #include <linux/io.h> | |
| 47 | #include <asm/io.h> | ||
| 48 | #include <mach/hardware.h> | ||
| 49 | #include <asm/irq.h> | ||
| 50 | #include <mach/pxa-regs.h> | ||
| 51 | #include <mach/regs-uart.h> | ||
| 52 | |||
| 53 | 47 | ||
| 54 | struct uart_pxa_port { | 48 | struct uart_pxa_port { |
| 55 | struct uart_port port; | 49 | struct uart_port port; |
| @@ -491,7 +485,7 @@ serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios, | |||
| 491 | * Ensure the port will be enabled. | 485 | * Ensure the port will be enabled. |
| 492 | * This is required especially for serial console. | 486 | * This is required especially for serial console. |
| 493 | */ | 487 | */ |
| 494 | up->ier |= IER_UUE; | 488 | up->ier |= UART_IER_UUE; |
| 495 | 489 | ||
| 496 | /* | 490 | /* |
| 497 | * Update the per-port timeout. | 491 | * Update the per-port timeout. |
| @@ -784,19 +778,15 @@ static int serial_pxa_probe(struct platform_device *dev) | |||
| 784 | sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; | 778 | sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; |
| 785 | sport->port.uartclk = clk_get_rate(sport->clk); | 779 | sport->port.uartclk = clk_get_rate(sport->clk); |
| 786 | 780 | ||
| 787 | /* | 781 | switch (dev->id) { |
| 788 | * Is it worth keeping this? | 782 | case 0: sport->name = "FFUART"; break; |
| 789 | */ | 783 | case 1: sport->name = "BTUART"; break; |
| 790 | if (mmres->start == __PREG(FFUART)) | 784 | case 2: sport->name = "STUART"; break; |
| 791 | sport->name = "FFUART"; | 785 | case 3: sport->name = "HWUART"; break; |
| 792 | else if (mmres->start == __PREG(BTUART)) | 786 | default: |
| 793 | sport->name = "BTUART"; | ||
| 794 | else if (mmres->start == __PREG(STUART)) | ||
| 795 | sport->name = "STUART"; | ||
| 796 | else if (mmres->start == __PREG(HWUART)) | ||
| 797 | sport->name = "HWUART"; | ||
| 798 | else | ||
| 799 | sport->name = "???"; | 787 | sport->name = "???"; |
| 788 | break; | ||
| 789 | } | ||
| 800 | 790 | ||
| 801 | sport->port.membase = ioremap(mmres->start, mmres->end - mmres->start + 1); | 791 | sport->port.membase = ioremap(mmres->start, mmres->end - mmres->start + 1); |
| 802 | if (!sport->port.membase) { | 792 | if (!sport->port.membase) { |
diff --git a/drivers/serial/sa1100.c b/drivers/serial/sa1100.c index b24a25ea6bc5..94530f01521e 100644 --- a/drivers/serial/sa1100.c +++ b/drivers/serial/sa1100.c | |||
| @@ -36,8 +36,8 @@ | |||
| 36 | #include <linux/tty_flip.h> | 36 | #include <linux/tty_flip.h> |
| 37 | #include <linux/serial_core.h> | 37 | #include <linux/serial_core.h> |
| 38 | #include <linux/serial.h> | 38 | #include <linux/serial.h> |
| 39 | #include <linux/io.h> | ||
| 39 | 40 | ||
| 40 | #include <asm/io.h> | ||
| 41 | #include <asm/irq.h> | 41 | #include <asm/irq.h> |
| 42 | #include <mach/hardware.h> | 42 | #include <mach/hardware.h> |
| 43 | #include <asm/mach/serial_sa1100.h> | 43 | #include <asm/mach/serial_sa1100.h> |
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c index 454a2712e629..b91ee1ae975d 100644 --- a/drivers/spi/omap2_mcspi.c +++ b/drivers/spi/omap2_mcspi.c | |||
| @@ -1021,13 +1021,13 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev) | |||
| 1021 | spin_lock_init(&mcspi->lock); | 1021 | spin_lock_init(&mcspi->lock); |
| 1022 | INIT_LIST_HEAD(&mcspi->msg_queue); | 1022 | INIT_LIST_HEAD(&mcspi->msg_queue); |
| 1023 | 1023 | ||
| 1024 | mcspi->ick = clk_get(&pdev->dev, "mcspi_ick"); | 1024 | mcspi->ick = clk_get(&pdev->dev, "ick"); |
| 1025 | if (IS_ERR(mcspi->ick)) { | 1025 | if (IS_ERR(mcspi->ick)) { |
| 1026 | dev_dbg(&pdev->dev, "can't get mcspi_ick\n"); | 1026 | dev_dbg(&pdev->dev, "can't get mcspi_ick\n"); |
| 1027 | status = PTR_ERR(mcspi->ick); | 1027 | status = PTR_ERR(mcspi->ick); |
| 1028 | goto err1a; | 1028 | goto err1a; |
| 1029 | } | 1029 | } |
| 1030 | mcspi->fck = clk_get(&pdev->dev, "mcspi_fck"); | 1030 | mcspi->fck = clk_get(&pdev->dev, "fck"); |
| 1031 | if (IS_ERR(mcspi->fck)) { | 1031 | if (IS_ERR(mcspi->fck)) { |
| 1032 | dev_dbg(&pdev->dev, "can't get mcspi_fck\n"); | 1032 | dev_dbg(&pdev->dev, "can't get mcspi_fck\n"); |
| 1033 | status = PTR_ERR(mcspi->fck); | 1033 | status = PTR_ERR(mcspi->fck); |
diff --git a/drivers/spi/omap_uwire.c b/drivers/spi/omap_uwire.c index bab6ff061e91..394b616eafe3 100644 --- a/drivers/spi/omap_uwire.c +++ b/drivers/spi/omap_uwire.c | |||
| @@ -506,11 +506,12 @@ static int __init uwire_probe(struct platform_device *pdev) | |||
| 506 | 506 | ||
| 507 | dev_set_drvdata(&pdev->dev, uwire); | 507 | dev_set_drvdata(&pdev->dev, uwire); |
| 508 | 508 | ||
| 509 | uwire->ck = clk_get(&pdev->dev, "armxor_ck"); | 509 | uwire->ck = clk_get(&pdev->dev, "fck"); |
| 510 | if (!uwire->ck || IS_ERR(uwire->ck)) { | 510 | if (IS_ERR(uwire->ck)) { |
| 511 | dev_dbg(&pdev->dev, "no mpu_xor_clk ?\n"); | 511 | status = PTR_ERR(uwire->ck); |
| 512 | dev_dbg(&pdev->dev, "no functional clock?\n"); | ||
| 512 | spi_master_put(master); | 513 | spi_master_put(master); |
| 513 | return -ENODEV; | 514 | return status; |
| 514 | } | 515 | } |
| 515 | clk_enable(uwire->ck); | 516 | clk_enable(uwire->ck); |
| 516 | 517 | ||
diff --git a/drivers/spi/pxa2xx_spi.c b/drivers/spi/pxa2xx_spi.c index d0fc4ca2f656..d22fac27219a 100644 --- a/drivers/spi/pxa2xx_spi.c +++ b/drivers/spi/pxa2xx_spi.c | |||
| @@ -34,8 +34,6 @@ | |||
| 34 | #include <asm/delay.h> | 34 | #include <asm/delay.h> |
| 35 | 35 | ||
| 36 | #include <mach/dma.h> | 36 | #include <mach/dma.h> |
| 37 | #include <mach/hardware.h> | ||
| 38 | #include <mach/pxa-regs.h> | ||
| 39 | #include <mach/regs-ssp.h> | 37 | #include <mach/regs-ssp.h> |
| 40 | #include <mach/ssp.h> | 38 | #include <mach/ssp.h> |
| 41 | #include <mach/pxa2xx_spi.h> | 39 | #include <mach/pxa2xx_spi.h> |
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index ce6badded47a..211af86a6c55 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig | |||
| @@ -73,8 +73,6 @@ source "drivers/staging/rt2860/Kconfig" | |||
| 73 | 73 | ||
| 74 | source "drivers/staging/rt2870/Kconfig" | 74 | source "drivers/staging/rt2870/Kconfig" |
| 75 | 75 | ||
| 76 | source "drivers/staging/benet/Kconfig" | ||
| 77 | |||
| 78 | source "drivers/staging/comedi/Kconfig" | 76 | source "drivers/staging/comedi/Kconfig" |
| 79 | 77 | ||
| 80 | source "drivers/staging/asus_oled/Kconfig" | 78 | source "drivers/staging/asus_oled/Kconfig" |
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index 9ddcc2bb3365..47a56f5ffabc 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile | |||
| @@ -19,7 +19,6 @@ obj-$(CONFIG_AGNX) += agnx/ | |||
| 19 | obj-$(CONFIG_OTUS) += otus/ | 19 | obj-$(CONFIG_OTUS) += otus/ |
| 20 | obj-$(CONFIG_RT2860) += rt2860/ | 20 | obj-$(CONFIG_RT2860) += rt2860/ |
| 21 | obj-$(CONFIG_RT2870) += rt2870/ | 21 | obj-$(CONFIG_RT2870) += rt2870/ |
| 22 | obj-$(CONFIG_BENET) += benet/ | ||
| 23 | obj-$(CONFIG_COMEDI) += comedi/ | 22 | obj-$(CONFIG_COMEDI) += comedi/ |
| 24 | obj-$(CONFIG_ASUS_OLED) += asus_oled/ | 23 | obj-$(CONFIG_ASUS_OLED) += asus_oled/ |
| 25 | obj-$(CONFIG_PANEL) += panel/ | 24 | obj-$(CONFIG_PANEL) += panel/ |
diff --git a/drivers/staging/benet/Kconfig b/drivers/staging/benet/Kconfig deleted file mode 100644 index f6806074f998..000000000000 --- a/drivers/staging/benet/Kconfig +++ /dev/null | |||
| @@ -1,7 +0,0 @@ | |||
| 1 | config BENET | ||
| 2 | tristate "ServerEngines 10Gb NIC - BladeEngine" | ||
| 3 | depends on PCI && INET | ||
| 4 | select INET_LRO | ||
| 5 | help | ||
| 6 | This driver implements the NIC functionality for ServerEngines | ||
| 7 | 10Gb network adapter BladeEngine (EC 3210). | ||
diff --git a/drivers/staging/benet/MAINTAINERS b/drivers/staging/benet/MAINTAINERS deleted file mode 100644 index d5ce340218b3..000000000000 --- a/drivers/staging/benet/MAINTAINERS +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | SERVER ENGINES 10Gbe NIC - BLADE-ENGINE | ||
| 2 | P: Subbu Seetharaman | ||
| 3 | M: subbus@serverengines.com | ||
| 4 | L: netdev@vger.kernel.org | ||
| 5 | W: http://www.serverengines.com | ||
| 6 | S: Supported | ||
diff --git a/drivers/staging/benet/Makefile b/drivers/staging/benet/Makefile deleted file mode 100644 index 460b923b99bd..000000000000 --- a/drivers/staging/benet/Makefile +++ /dev/null | |||
| @@ -1,14 +0,0 @@ | |||
| 1 | # | ||
| 2 | # Makefile to build the network driver for ServerEngine's BladeEngine | ||
| 3 | # | ||
| 4 | obj-$(CONFIG_BENET) += benet.o | ||
| 5 | |||
| 6 | benet-y := be_init.o \ | ||
| 7 | be_int.o \ | ||
| 8 | be_netif.o \ | ||
| 9 | be_ethtool.o \ | ||
| 10 | funcobj.o \ | ||
| 11 | cq.o \ | ||
| 12 | eq.o \ | ||
| 13 | mpu.o \ | ||
| 14 | eth.o | ||
diff --git a/drivers/staging/benet/TODO b/drivers/staging/benet/TODO deleted file mode 100644 index a51dfb59a62f..000000000000 --- a/drivers/staging/benet/TODO +++ /dev/null | |||
| @@ -1,6 +0,0 @@ | |||
| 1 | TODO: | ||
| 2 | - remove wrappers around common iowrite functions | ||
| 3 | - full netdev audit of common problems/issues | ||
| 4 | |||
| 5 | Please send all patches and questions to Subbu Seetharaman | ||
| 6 | <subbus@serverengines.com> and Greg Kroah-Hartman <greg@kroah.com> | ||
diff --git a/drivers/staging/benet/asyncmesg.h b/drivers/staging/benet/asyncmesg.h deleted file mode 100644 index d1e779adb848..000000000000 --- a/drivers/staging/benet/asyncmesg.h +++ /dev/null | |||
| @@ -1,82 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __asyncmesg_amap_h__ | ||
| 21 | #define __asyncmesg_amap_h__ | ||
| 22 | #include "fwcmd_common.h" | ||
| 23 | |||
| 24 | /* --- ASYNC_EVENT_CODES --- */ | ||
| 25 | #define ASYNC_EVENT_CODE_LINK_STATE (1) | ||
| 26 | #define ASYNC_EVENT_CODE_ISCSI (2) | ||
| 27 | |||
| 28 | /* --- ASYNC_LINK_STATES --- */ | ||
| 29 | #define ASYNC_EVENT_LINK_DOWN (0) /* Link Down on a port */ | ||
| 30 | #define ASYNC_EVENT_LINK_UP (1) /* Link Up on a port */ | ||
| 31 | |||
| 32 | /* | ||
| 33 | * The last 4 bytes of the async events have this common format. It allows | ||
| 34 | * the driver to distinguish [link]MCC_CQ_ENTRY[/link] structs from | ||
| 35 | * asynchronous events. Both arrive on the same completion queue. This | ||
| 36 | * structure also contains the common fields used to decode the async event. | ||
| 37 | */ | ||
| 38 | struct BE_ASYNC_EVENT_TRAILER_AMAP { | ||
| 39 | u8 rsvd0[8]; /* DWORD 0 */ | ||
| 40 | u8 event_code[8]; /* DWORD 0 */ | ||
| 41 | u8 event_type[8]; /* DWORD 0 */ | ||
| 42 | u8 rsvd1[6]; /* DWORD 0 */ | ||
| 43 | u8 async_event; /* DWORD 0 */ | ||
| 44 | u8 valid; /* DWORD 0 */ | ||
| 45 | } __packed; | ||
| 46 | struct ASYNC_EVENT_TRAILER_AMAP { | ||
| 47 | u32 dw[1]; | ||
| 48 | }; | ||
| 49 | |||
| 50 | /* | ||
| 51 | * Applicable in Initiator, Target and NIC modes. | ||
| 52 | * A link state async event is seen by all device drivers as soon they | ||
| 53 | * create an MCC ring. Thereafter, anytime the link status changes the | ||
| 54 | * drivers will receive a link state async event. Notifications continue to | ||
| 55 | * be sent until a driver destroys its MCC ring. A link down event is | ||
| 56 | * reported when either port loses link. A link up event is reported | ||
| 57 | * when either port regains link. When BE's failover mechanism is enabled, a | ||
| 58 | * link down on the active port causes traffic to be diverted to the standby | ||
| 59 | * port by the BE's ARM firmware (assuming the standby port has link). In | ||
| 60 | * this case, the standy port assumes the active status. Note: when link is | ||
| 61 | * restored on the failed port, traffic continues on the currently active | ||
| 62 | * port. The ARM firmware does not attempt to 'fail back' traffic to | ||
| 63 | * the restored port. | ||
| 64 | */ | ||
| 65 | struct BE_ASYNC_EVENT_LINK_STATE_AMAP { | ||
| 66 | u8 port0_link_status[8]; | ||
| 67 | u8 port1_link_status[8]; | ||
| 68 | u8 active_port[8]; | ||
| 69 | u8 rsvd0[8]; /* DWORD 0 */ | ||
| 70 | u8 port0_duplex[8]; | ||
| 71 | u8 port0_speed[8]; | ||
| 72 | u8 port1_duplex[8]; | ||
| 73 | u8 port1_speed[8]; | ||
| 74 | u8 port0_fault[8]; | ||
| 75 | u8 port1_fault[8]; | ||
| 76 | u8 rsvd1[2][8]; /* DWORD 2 */ | ||
| 77 | struct BE_ASYNC_EVENT_TRAILER_AMAP trailer; | ||
| 78 | } __packed; | ||
| 79 | struct ASYNC_EVENT_LINK_STATE_AMAP { | ||
| 80 | u32 dw[4]; | ||
| 81 | }; | ||
| 82 | #endif /* __asyncmesg_amap_h__ */ | ||
diff --git a/drivers/staging/benet/be_cm.h b/drivers/staging/benet/be_cm.h deleted file mode 100644 index b7a1dfd20c36..000000000000 --- a/drivers/staging/benet/be_cm.h +++ /dev/null | |||
| @@ -1,134 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __be_cm_amap_h__ | ||
| 21 | #define __be_cm_amap_h__ | ||
| 22 | #include "be_common.h" | ||
| 23 | #include "etx_context.h" | ||
| 24 | #include "mpu_context.h" | ||
| 25 | |||
| 26 | /* | ||
| 27 | * --- CEV_WATERMARK_ENUM --- | ||
| 28 | * CQ/EQ Watermark Encodings. Encoded as number of free entries in | ||
| 29 | * Queue when Watermark is reached. | ||
| 30 | */ | ||
| 31 | #define CEV_WMARK_0 (0) /* Watermark when Queue full */ | ||
| 32 | #define CEV_WMARK_16 (1) /* Watermark at 16 free entries */ | ||
| 33 | #define CEV_WMARK_32 (2) /* Watermark at 32 free entries */ | ||
| 34 | #define CEV_WMARK_48 (3) /* Watermark at 48 free entries */ | ||
| 35 | #define CEV_WMARK_64 (4) /* Watermark at 64 free entries */ | ||
| 36 | #define CEV_WMARK_80 (5) /* Watermark at 80 free entries */ | ||
| 37 | #define CEV_WMARK_96 (6) /* Watermark at 96 free entries */ | ||
| 38 | #define CEV_WMARK_112 (7) /* Watermark at 112 free entries */ | ||
| 39 | #define CEV_WMARK_128 (8) /* Watermark at 128 free entries */ | ||
| 40 | #define CEV_WMARK_144 (9) /* Watermark at 144 free entries */ | ||
| 41 | #define CEV_WMARK_160 (10) /* Watermark at 160 free entries */ | ||
| 42 | #define CEV_WMARK_176 (11) /* Watermark at 176 free entries */ | ||
| 43 | #define CEV_WMARK_192 (12) /* Watermark at 192 free entries */ | ||
| 44 | #define CEV_WMARK_208 (13) /* Watermark at 208 free entries */ | ||
| 45 | #define CEV_WMARK_224 (14) /* Watermark at 224 free entries */ | ||
| 46 | #define CEV_WMARK_240 (15) /* Watermark at 240 free entries */ | ||
| 47 | |||
| 48 | /* | ||
| 49 | * --- CQ_CNT_ENUM --- | ||
| 50 | * Completion Queue Count Encodings. | ||
| 51 | */ | ||
| 52 | #define CEV_CQ_CNT_256 (0) /* CQ has 256 entries */ | ||
| 53 | #define CEV_CQ_CNT_512 (1) /* CQ has 512 entries */ | ||
| 54 | #define CEV_CQ_CNT_1024 (2) /* CQ has 1024 entries */ | ||
| 55 | |||
| 56 | /* | ||
| 57 | * --- EQ_CNT_ENUM --- | ||
| 58 | * Event Queue Count Encodings. | ||
| 59 | */ | ||
| 60 | #define CEV_EQ_CNT_256 (0) /* EQ has 256 entries (16-byte EQEs only) */ | ||
| 61 | #define CEV_EQ_CNT_512 (1) /* EQ has 512 entries (16-byte EQEs only) */ | ||
| 62 | #define CEV_EQ_CNT_1024 (2) /* EQ has 1024 entries (4-byte or */ | ||
| 63 | /* 16-byte EQEs only) */ | ||
| 64 | #define CEV_EQ_CNT_2048 (3) /* EQ has 2048 entries (4-byte or */ | ||
| 65 | /* 16-byte EQEs only) */ | ||
| 66 | #define CEV_EQ_CNT_4096 (4) /* EQ has 4096 entries (4-byte EQEs only) */ | ||
| 67 | |||
| 68 | /* | ||
| 69 | * --- EQ_SIZE_ENUM --- | ||
| 70 | * Event Queue Entry Size Encoding. | ||
| 71 | */ | ||
| 72 | #define CEV_EQ_SIZE_4 (0) /* EQE is 4 bytes */ | ||
| 73 | #define CEV_EQ_SIZE_16 (1) /* EQE is 16 bytes */ | ||
| 74 | |||
| 75 | /* | ||
| 76 | * Completion Queue Context Table Entry. Contains the state of a CQ. | ||
| 77 | * Located in RAM within the CEV block. | ||
| 78 | */ | ||
| 79 | struct BE_CQ_CONTEXT_AMAP { | ||
| 80 | u8 Cidx[11]; /* DWORD 0 */ | ||
| 81 | u8 Watermark[4]; /* DWORD 0 */ | ||
| 82 | u8 NoDelay; /* DWORD 0 */ | ||
| 83 | u8 EPIdx[11]; /* DWORD 0 */ | ||
| 84 | u8 Count[2]; /* DWORD 0 */ | ||
| 85 | u8 valid; /* DWORD 0 */ | ||
| 86 | u8 SolEvent; /* DWORD 0 */ | ||
| 87 | u8 Eventable; /* DWORD 0 */ | ||
| 88 | u8 Pidx[11]; /* DWORD 1 */ | ||
| 89 | u8 PD[10]; /* DWORD 1 */ | ||
| 90 | u8 EQID[7]; /* DWORD 1 */ | ||
| 91 | u8 Func; /* DWORD 1 */ | ||
| 92 | u8 WME; /* DWORD 1 */ | ||
| 93 | u8 Stalled; /* DWORD 1 */ | ||
| 94 | u8 Armed; /* DWORD 1 */ | ||
| 95 | } __packed; | ||
| 96 | struct CQ_CONTEXT_AMAP { | ||
| 97 | u32 dw[2]; | ||
| 98 | }; | ||
| 99 | |||
| 100 | /* | ||
| 101 | * Event Queue Context Table Entry. Contains the state of an EQ. | ||
| 102 | * Located in RAM in the CEV block. | ||
| 103 | */ | ||
| 104 | struct BE_EQ_CONTEXT_AMAP { | ||
| 105 | u8 Cidx[13]; /* DWORD 0 */ | ||
| 106 | u8 rsvd0[2]; /* DWORD 0 */ | ||
| 107 | u8 Func; /* DWORD 0 */ | ||
| 108 | u8 EPIdx[13]; /* DWORD 0 */ | ||
| 109 | u8 valid; /* DWORD 0 */ | ||
| 110 | u8 rsvd1; /* DWORD 0 */ | ||
| 111 | u8 Size; /* DWORD 0 */ | ||
| 112 | u8 Pidx[13]; /* DWORD 1 */ | ||
| 113 | u8 rsvd2[3]; /* DWORD 1 */ | ||
| 114 | u8 PD[10]; /* DWORD 1 */ | ||
| 115 | u8 Count[3]; /* DWORD 1 */ | ||
| 116 | u8 SolEvent; /* DWORD 1 */ | ||
| 117 | u8 Stalled; /* DWORD 1 */ | ||
| 118 | u8 Armed; /* DWORD 1 */ | ||
| 119 | u8 Watermark[4]; /* DWORD 2 */ | ||
| 120 | u8 WME; /* DWORD 2 */ | ||
| 121 | u8 rsvd3[3]; /* DWORD 2 */ | ||
| 122 | u8 EventVect[6]; /* DWORD 2 */ | ||
| 123 | u8 rsvd4[2]; /* DWORD 2 */ | ||
| 124 | u8 Delay[8]; /* DWORD 2 */ | ||
| 125 | u8 rsvd5[6]; /* DWORD 2 */ | ||
| 126 | u8 TMR; /* DWORD 2 */ | ||
| 127 | u8 rsvd6; /* DWORD 2 */ | ||
| 128 | u8 rsvd7[32]; /* DWORD 3 */ | ||
| 129 | } __packed; | ||
| 130 | struct EQ_CONTEXT_AMAP { | ||
| 131 | u32 dw[4]; | ||
| 132 | }; | ||
| 133 | |||
| 134 | #endif /* __be_cm_amap_h__ */ | ||
diff --git a/drivers/staging/benet/be_common.h b/drivers/staging/benet/be_common.h deleted file mode 100644 index 7e63dc5e3348..000000000000 --- a/drivers/staging/benet/be_common.h +++ /dev/null | |||
| @@ -1,53 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __be_common_amap_h__ | ||
| 21 | #define __be_common_amap_h__ | ||
| 22 | |||
| 23 | /* Physical Address. */ | ||
| 24 | struct BE_PHYS_ADDR_AMAP { | ||
| 25 | u8 lo[32]; /* DWORD 0 */ | ||
| 26 | u8 hi[32]; /* DWORD 1 */ | ||
| 27 | } __packed; | ||
| 28 | struct PHYS_ADDR_AMAP { | ||
| 29 | u32 dw[2]; | ||
| 30 | }; | ||
| 31 | |||
| 32 | /* Virtual Address. */ | ||
| 33 | struct BE_VIRT_ADDR_AMAP { | ||
| 34 | u8 lo[32]; /* DWORD 0 */ | ||
| 35 | u8 hi[32]; /* DWORD 1 */ | ||
| 36 | } __packed; | ||
| 37 | struct VIRT_ADDR_AMAP { | ||
| 38 | u32 dw[2]; | ||
| 39 | }; | ||
| 40 | |||
| 41 | /* Scatter gather element. */ | ||
| 42 | struct BE_SGE_AMAP { | ||
| 43 | u8 addr_hi[32]; /* DWORD 0 */ | ||
| 44 | u8 addr_lo[32]; /* DWORD 1 */ | ||
| 45 | u8 rsvd0[32]; /* DWORD 2 */ | ||
| 46 | u8 len[16]; /* DWORD 3 */ | ||
| 47 | u8 rsvd1[16]; /* DWORD 3 */ | ||
| 48 | } __packed; | ||
| 49 | struct SGE_AMAP { | ||
| 50 | u32 dw[4]; | ||
| 51 | }; | ||
| 52 | |||
| 53 | #endif /* __be_common_amap_h__ */ | ||
diff --git a/drivers/staging/benet/be_ethtool.c b/drivers/staging/benet/be_ethtool.c deleted file mode 100644 index 027af85707aa..000000000000 --- a/drivers/staging/benet/be_ethtool.c +++ /dev/null | |||
| @@ -1,348 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * be_ethtool.c | ||
| 19 | * | ||
| 20 | * This file contains various functions that ethtool can use | ||
| 21 | * to talk to the driver and the BE H/W. | ||
| 22 | */ | ||
| 23 | |||
| 24 | #include "benet.h" | ||
| 25 | |||
| 26 | #include <linux/ethtool.h> | ||
| 27 | |||
| 28 | static const char benet_gstrings_stats[][ETH_GSTRING_LEN] = { | ||
| 29 | /* net_device_stats */ | ||
| 30 | "rx_packets", | ||
| 31 | "tx_packets", | ||
| 32 | "rx_bytes", | ||
| 33 | "tx_bytes", | ||
| 34 | "rx_errors", | ||
| 35 | "tx_errors", | ||
| 36 | "rx_dropped", | ||
| 37 | "tx_dropped", | ||
| 38 | "multicast", | ||
| 39 | "collisions", | ||
| 40 | "rx_length_errors", | ||
| 41 | "rx_over_errors", | ||
| 42 | "rx_crc_errors", | ||
| 43 | "rx_frame_errors", | ||
| 44 | "rx_fifo_errors", | ||
| 45 | "rx_missed_errors", | ||
| 46 | "tx_aborted_errors", | ||
| 47 | "tx_carrier_errors", | ||
| 48 | "tx_fifo_errors", | ||
| 49 | "tx_heartbeat_errors", | ||
| 50 | "tx_window_errors", | ||
| 51 | "rx_compressed", | ||
| 52 | "tc_compressed", | ||
| 53 | /* BE driver Stats */ | ||
| 54 | "bes_tx_reqs", | ||
| 55 | "bes_tx_fails", | ||
| 56 | "bes_fwd_reqs", | ||
| 57 | "bes_tx_wrbs", | ||
| 58 | "bes_interrupts", | ||
| 59 | "bes_events", | ||
| 60 | "bes_tx_events", | ||
| 61 | "bes_rx_events", | ||
| 62 | "bes_tx_compl", | ||
| 63 | "bes_rx_compl", | ||
| 64 | "bes_ethrx_post_fail", | ||
| 65 | "bes_802_3_dropped_frames", | ||
| 66 | "bes_802_3_malformed_frames", | ||
| 67 | "bes_rx_misc_pkts", | ||
| 68 | "bes_eth_tx_rate", | ||
| 69 | "bes_eth_rx_rate", | ||
| 70 | "Num Packets collected", | ||
| 71 | "Num Times Flushed", | ||
| 72 | }; | ||
| 73 | |||
| 74 | #define NET_DEV_STATS_LEN \ | ||
| 75 | (sizeof(struct net_device_stats)/sizeof(unsigned long)) | ||
| 76 | |||
| 77 | #define BENET_STATS_LEN ARRAY_SIZE(benet_gstrings_stats) | ||
| 78 | |||
| 79 | static void | ||
| 80 | be_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *drvinfo) | ||
| 81 | { | ||
| 82 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 83 | struct be_adapter *adapter = pnob->adapter; | ||
| 84 | |||
| 85 | strncpy(drvinfo->driver, be_driver_name, 32); | ||
| 86 | strncpy(drvinfo->version, be_drvr_ver, 32); | ||
| 87 | strncpy(drvinfo->fw_version, be_fw_ver, 32); | ||
| 88 | strcpy(drvinfo->bus_info, pci_name(adapter->pdev)); | ||
| 89 | drvinfo->testinfo_len = 0; | ||
| 90 | drvinfo->regdump_len = 0; | ||
| 91 | drvinfo->eedump_len = 0; | ||
| 92 | } | ||
| 93 | |||
| 94 | static int | ||
| 95 | be_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce) | ||
| 96 | { | ||
| 97 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 98 | struct be_adapter *adapter = pnob->adapter; | ||
| 99 | |||
| 100 | coalesce->rx_max_coalesced_frames = adapter->max_rx_coal; | ||
| 101 | |||
| 102 | coalesce->rx_coalesce_usecs = adapter->cur_eqd; | ||
| 103 | coalesce->rx_coalesce_usecs_high = adapter->max_eqd; | ||
| 104 | coalesce->rx_coalesce_usecs_low = adapter->min_eqd; | ||
| 105 | |||
| 106 | coalesce->tx_coalesce_usecs = adapter->cur_eqd; | ||
| 107 | coalesce->tx_coalesce_usecs_high = adapter->max_eqd; | ||
| 108 | coalesce->tx_coalesce_usecs_low = adapter->min_eqd; | ||
| 109 | |||
| 110 | coalesce->use_adaptive_rx_coalesce = adapter->enable_aic; | ||
| 111 | coalesce->use_adaptive_tx_coalesce = adapter->enable_aic; | ||
| 112 | |||
| 113 | return 0; | ||
| 114 | } | ||
| 115 | |||
| 116 | /* | ||
| 117 | * This routine is used to set interrup coalescing delay *as well as* | ||
| 118 | * the number of pkts to coalesce for LRO. | ||
| 119 | */ | ||
| 120 | static int | ||
| 121 | be_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce) | ||
| 122 | { | ||
| 123 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 124 | struct be_adapter *adapter = pnob->adapter; | ||
| 125 | struct be_eq_object *eq_objectp; | ||
| 126 | u32 max, min, cur; | ||
| 127 | int status; | ||
| 128 | |||
| 129 | adapter->max_rx_coal = coalesce->rx_max_coalesced_frames; | ||
| 130 | if (adapter->max_rx_coal >= BE_LRO_MAX_PKTS) | ||
| 131 | adapter->max_rx_coal = BE_LRO_MAX_PKTS; | ||
| 132 | |||
| 133 | if (adapter->enable_aic == 0 && | ||
| 134 | coalesce->use_adaptive_rx_coalesce == 1) { | ||
| 135 | /* if AIC is being turned on now, start with an EQD of 0 */ | ||
| 136 | adapter->cur_eqd = 0; | ||
| 137 | } | ||
| 138 | adapter->enable_aic = coalesce->use_adaptive_rx_coalesce; | ||
| 139 | |||
| 140 | /* round off to nearest multiple of 8 */ | ||
| 141 | max = (((coalesce->rx_coalesce_usecs_high + 4) >> 3) << 3); | ||
| 142 | min = (((coalesce->rx_coalesce_usecs_low + 4) >> 3) << 3); | ||
| 143 | cur = (((coalesce->rx_coalesce_usecs + 4) >> 3) << 3); | ||
| 144 | |||
| 145 | if (adapter->enable_aic) { | ||
| 146 | /* accept low and high if AIC is enabled */ | ||
| 147 | if (max > MAX_EQD) | ||
| 148 | max = MAX_EQD; | ||
| 149 | if (min > max) | ||
| 150 | min = max; | ||
| 151 | adapter->max_eqd = max; | ||
| 152 | adapter->min_eqd = min; | ||
| 153 | if (adapter->cur_eqd > max) | ||
| 154 | adapter->cur_eqd = max; | ||
| 155 | if (adapter->cur_eqd < min) | ||
| 156 | adapter->cur_eqd = min; | ||
| 157 | } else { | ||
| 158 | /* accept specified coalesce_usecs only if AIC is disabled */ | ||
| 159 | if (cur > MAX_EQD) | ||
| 160 | cur = MAX_EQD; | ||
| 161 | eq_objectp = &pnob->event_q_obj; | ||
| 162 | status = | ||
| 163 | be_eq_modify_delay(&pnob->fn_obj, 1, &eq_objectp, &cur, | ||
| 164 | NULL, NULL, NULL); | ||
| 165 | if (status == BE_SUCCESS) | ||
| 166 | adapter->cur_eqd = cur; | ||
| 167 | } | ||
| 168 | return 0; | ||
| 169 | } | ||
| 170 | |||
| 171 | static u32 be_get_rx_csum(struct net_device *netdev) | ||
| 172 | { | ||
| 173 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 174 | struct be_adapter *adapter = pnob->adapter; | ||
| 175 | return adapter->rx_csum; | ||
| 176 | } | ||
| 177 | |||
| 178 | static int be_set_rx_csum(struct net_device *netdev, uint32_t data) | ||
| 179 | { | ||
| 180 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 181 | struct be_adapter *adapter = pnob->adapter; | ||
| 182 | |||
| 183 | if (data) | ||
| 184 | adapter->rx_csum = 1; | ||
| 185 | else | ||
| 186 | adapter->rx_csum = 0; | ||
| 187 | |||
| 188 | return 0; | ||
| 189 | } | ||
| 190 | |||
| 191 | static void | ||
| 192 | be_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data) | ||
| 193 | { | ||
| 194 | switch (stringset) { | ||
| 195 | case ETH_SS_STATS: | ||
| 196 | memcpy(data, *benet_gstrings_stats, | ||
| 197 | sizeof(benet_gstrings_stats)); | ||
| 198 | break; | ||
| 199 | } | ||
| 200 | } | ||
| 201 | |||
| 202 | static int be_get_stats_count(struct net_device *netdev) | ||
| 203 | { | ||
| 204 | return BENET_STATS_LEN; | ||
| 205 | } | ||
| 206 | |||
| 207 | static void | ||
| 208 | be_get_ethtool_stats(struct net_device *netdev, | ||
| 209 | struct ethtool_stats *stats, uint64_t *data) | ||
| 210 | { | ||
| 211 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 212 | struct be_adapter *adapter = pnob->adapter; | ||
| 213 | int i; | ||
| 214 | |||
| 215 | benet_get_stats(netdev); | ||
| 216 | |||
| 217 | for (i = 0; i <= NET_DEV_STATS_LEN; i++) | ||
| 218 | data[i] = ((unsigned long *)&adapter->benet_stats)[i]; | ||
| 219 | |||
| 220 | data[i] = adapter->be_stat.bes_tx_reqs; | ||
| 221 | data[i++] = adapter->be_stat.bes_tx_fails; | ||
| 222 | data[i++] = adapter->be_stat.bes_fwd_reqs; | ||
| 223 | data[i++] = adapter->be_stat.bes_tx_wrbs; | ||
| 224 | |||
| 225 | data[i++] = adapter->be_stat.bes_ints; | ||
| 226 | data[i++] = adapter->be_stat.bes_events; | ||
| 227 | data[i++] = adapter->be_stat.bes_tx_events; | ||
| 228 | data[i++] = adapter->be_stat.bes_rx_events; | ||
| 229 | data[i++] = adapter->be_stat.bes_tx_compl; | ||
| 230 | data[i++] = adapter->be_stat.bes_rx_compl; | ||
| 231 | data[i++] = adapter->be_stat.bes_ethrx_post_fail; | ||
| 232 | data[i++] = adapter->be_stat.bes_802_3_dropped_frames; | ||
| 233 | data[i++] = adapter->be_stat.bes_802_3_malformed_frames; | ||
| 234 | data[i++] = adapter->be_stat.bes_rx_misc_pkts; | ||
| 235 | data[i++] = adapter->be_stat.bes_eth_tx_rate; | ||
| 236 | data[i++] = adapter->be_stat.bes_eth_rx_rate; | ||
| 237 | data[i++] = adapter->be_stat.bes_rx_coal; | ||
| 238 | data[i++] = adapter->be_stat.bes_rx_flush; | ||
| 239 | |||
| 240 | } | ||
| 241 | |||
| 242 | static int be_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) | ||
| 243 | { | ||
| 244 | ecmd->speed = SPEED_10000; | ||
| 245 | ecmd->duplex = DUPLEX_FULL; | ||
| 246 | ecmd->autoneg = AUTONEG_DISABLE; | ||
| 247 | return 0; | ||
| 248 | } | ||
| 249 | |||
| 250 | /* Get the Ring parameters from the pnob */ | ||
| 251 | static void | ||
| 252 | be_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring) | ||
| 253 | { | ||
| 254 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 255 | |||
| 256 | /* Pre Set Maxims */ | ||
| 257 | ring->rx_max_pending = pnob->rx_q_len; | ||
| 258 | ring->rx_mini_max_pending = ring->rx_mini_max_pending; | ||
| 259 | ring->rx_jumbo_max_pending = ring->rx_jumbo_max_pending; | ||
| 260 | ring->tx_max_pending = pnob->tx_q_len; | ||
| 261 | |||
| 262 | /* Current hardware Settings */ | ||
| 263 | ring->rx_pending = atomic_read(&pnob->rx_q_posted); | ||
| 264 | ring->rx_mini_pending = ring->rx_mini_pending; | ||
| 265 | ring->rx_jumbo_pending = ring->rx_jumbo_pending; | ||
| 266 | ring->tx_pending = atomic_read(&pnob->tx_q_used); | ||
| 267 | |||
| 268 | } | ||
| 269 | |||
| 270 | static void | ||
| 271 | be_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *ecmd) | ||
| 272 | { | ||
| 273 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 274 | bool rxfc, txfc; | ||
| 275 | int status; | ||
| 276 | |||
| 277 | status = be_eth_get_flow_control(&pnob->fn_obj, &txfc, &rxfc); | ||
| 278 | if (status != BE_SUCCESS) { | ||
| 279 | dev_info(&netdev->dev, "Unable to get pause frame settings\n"); | ||
| 280 | /* return defaults */ | ||
| 281 | ecmd->rx_pause = 1; | ||
| 282 | ecmd->tx_pause = 0; | ||
| 283 | ecmd->autoneg = AUTONEG_ENABLE; | ||
| 284 | return; | ||
| 285 | } | ||
| 286 | |||
| 287 | if (txfc == true) | ||
| 288 | ecmd->tx_pause = 1; | ||
| 289 | else | ||
| 290 | ecmd->tx_pause = 0; | ||
| 291 | |||
| 292 | if (rxfc == true) | ||
| 293 | ecmd->rx_pause = 1; | ||
| 294 | else | ||
| 295 | ecmd->rx_pause = 0; | ||
| 296 | |||
| 297 | ecmd->autoneg = AUTONEG_ENABLE; | ||
| 298 | } | ||
| 299 | |||
| 300 | static int | ||
| 301 | be_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *ecmd) | ||
| 302 | { | ||
| 303 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 304 | bool txfc, rxfc; | ||
| 305 | int status; | ||
| 306 | |||
| 307 | if (ecmd->autoneg != AUTONEG_ENABLE) | ||
| 308 | return -EINVAL; | ||
| 309 | |||
| 310 | if (ecmd->tx_pause) | ||
| 311 | txfc = true; | ||
| 312 | else | ||
| 313 | txfc = false; | ||
| 314 | |||
| 315 | if (ecmd->rx_pause) | ||
| 316 | rxfc = true; | ||
| 317 | else | ||
| 318 | rxfc = false; | ||
| 319 | |||
| 320 | status = be_eth_set_flow_control(&pnob->fn_obj, txfc, rxfc); | ||
| 321 | if (status != BE_SUCCESS) { | ||
| 322 | dev_info(&netdev->dev, "Unable to set pause frame settings\n"); | ||
| 323 | return -1; | ||
| 324 | } | ||
| 325 | return 0; | ||
| 326 | } | ||
| 327 | |||
| 328 | struct ethtool_ops be_ethtool_ops = { | ||
| 329 | .get_settings = be_get_settings, | ||
| 330 | .get_drvinfo = be_get_drvinfo, | ||
| 331 | .get_link = ethtool_op_get_link, | ||
| 332 | .get_coalesce = be_get_coalesce, | ||
| 333 | .set_coalesce = be_set_coalesce, | ||
| 334 | .get_ringparam = be_get_ringparam, | ||
| 335 | .get_pauseparam = be_get_pauseparam, | ||
| 336 | .set_pauseparam = be_set_pauseparam, | ||
| 337 | .get_rx_csum = be_get_rx_csum, | ||
| 338 | .set_rx_csum = be_set_rx_csum, | ||
| 339 | .get_tx_csum = ethtool_op_get_tx_csum, | ||
| 340 | .set_tx_csum = ethtool_op_set_tx_csum, | ||
| 341 | .get_sg = ethtool_op_get_sg, | ||
| 342 | .set_sg = ethtool_op_set_sg, | ||
| 343 | .get_tso = ethtool_op_get_tso, | ||
| 344 | .set_tso = ethtool_op_set_tso, | ||
| 345 | .get_strings = be_get_strings, | ||
| 346 | .get_stats_count = be_get_stats_count, | ||
| 347 | .get_ethtool_stats = be_get_ethtool_stats, | ||
| 348 | }; | ||
diff --git a/drivers/staging/benet/be_init.c b/drivers/staging/benet/be_init.c deleted file mode 100644 index 12a026c3f9e1..000000000000 --- a/drivers/staging/benet/be_init.c +++ /dev/null | |||
| @@ -1,1382 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | #include <linux/etherdevice.h> | ||
| 18 | #include "benet.h" | ||
| 19 | |||
| 20 | #define DRVR_VERSION "1.0.728" | ||
| 21 | |||
| 22 | static const struct pci_device_id be_device_id_table[] = { | ||
| 23 | {PCI_DEVICE(0x19a2, 0x0201)}, | ||
| 24 | {0} | ||
| 25 | }; | ||
| 26 | |||
| 27 | MODULE_DEVICE_TABLE(pci, be_device_id_table); | ||
| 28 | |||
| 29 | MODULE_VERSION(DRVR_VERSION); | ||
| 30 | |||
| 31 | #define DRV_DESCRIPTION "ServerEngines BladeEngine Network Driver Version " | ||
| 32 | |||
| 33 | MODULE_DESCRIPTION(DRV_DESCRIPTION DRVR_VERSION); | ||
| 34 | MODULE_AUTHOR("ServerEngines"); | ||
| 35 | MODULE_LICENSE("GPL"); | ||
| 36 | |||
| 37 | static unsigned int msix = 1; | ||
| 38 | module_param(msix, uint, S_IRUGO); | ||
| 39 | MODULE_PARM_DESC(msix, "Use MSI-x interrupts"); | ||
| 40 | |||
| 41 | static unsigned int rxbuf_size = 2048; /* Default RX frag size */ | ||
| 42 | module_param(rxbuf_size, uint, S_IRUGO); | ||
| 43 | MODULE_PARM_DESC(rxbuf_size, "Size of buffers to hold Rx data"); | ||
| 44 | |||
| 45 | const char be_drvr_ver[] = DRVR_VERSION; | ||
| 46 | char be_fw_ver[32]; /* F/W version filled in by be_probe */ | ||
| 47 | char be_driver_name[] = "benet"; | ||
| 48 | |||
| 49 | /* | ||
| 50 | * Number of entries in each queue. | ||
| 51 | */ | ||
| 52 | #define EVENT_Q_LEN 1024 | ||
| 53 | #define ETH_TXQ_LEN 2048 | ||
| 54 | #define ETH_TXCQ_LEN 1024 | ||
| 55 | #define ETH_RXQ_LEN 1024 /* Does not support any other value */ | ||
| 56 | #define ETH_UC_RXCQ_LEN 1024 | ||
| 57 | #define ETH_BC_RXCQ_LEN 256 | ||
| 58 | #define MCC_Q_LEN 64 /* total size not to exceed 8 pages */ | ||
| 59 | #define MCC_CQ_LEN 256 | ||
| 60 | |||
| 61 | /* Bit mask describing events of interest to be traced */ | ||
| 62 | unsigned int trace_level; | ||
| 63 | |||
| 64 | static int | ||
| 65 | init_pci_be_function(struct be_adapter *adapter, struct pci_dev *pdev) | ||
| 66 | { | ||
| 67 | u64 pa; | ||
| 68 | |||
| 69 | /* CSR */ | ||
| 70 | pa = pci_resource_start(pdev, 2); | ||
| 71 | adapter->csr_va = ioremap_nocache(pa, pci_resource_len(pdev, 2)); | ||
| 72 | if (adapter->csr_va == NULL) | ||
| 73 | return -ENOMEM; | ||
| 74 | |||
| 75 | /* Door Bell */ | ||
| 76 | pa = pci_resource_start(pdev, 4); | ||
| 77 | adapter->db_va = ioremap_nocache(pa, (128 * 1024)); | ||
| 78 | if (adapter->db_va == NULL) { | ||
| 79 | iounmap(adapter->csr_va); | ||
| 80 | return -ENOMEM; | ||
| 81 | } | ||
| 82 | |||
| 83 | /* PCI */ | ||
| 84 | pa = pci_resource_start(pdev, 1); | ||
| 85 | adapter->pci_va = ioremap_nocache(pa, pci_resource_len(pdev, 1)); | ||
| 86 | if (adapter->pci_va == NULL) { | ||
| 87 | iounmap(adapter->csr_va); | ||
| 88 | iounmap(adapter->db_va); | ||
| 89 | return -ENOMEM; | ||
| 90 | } | ||
| 91 | return 0; | ||
| 92 | } | ||
| 93 | |||
| 94 | /* | ||
| 95 | This function enables the interrupt corresponding to the Event | ||
| 96 | queue ID for the given NetObject | ||
| 97 | */ | ||
| 98 | void be_enable_eq_intr(struct be_net_object *pnob) | ||
| 99 | { | ||
| 100 | struct CQ_DB_AMAP cqdb; | ||
| 101 | cqdb.dw[0] = 0; | ||
| 102 | AMAP_SET_BITS_PTR(CQ_DB, event, &cqdb, 1); | ||
| 103 | AMAP_SET_BITS_PTR(CQ_DB, rearm, &cqdb, 1); | ||
| 104 | AMAP_SET_BITS_PTR(CQ_DB, num_popped, &cqdb, 0); | ||
| 105 | AMAP_SET_BITS_PTR(CQ_DB, qid, &cqdb, pnob->event_q_id); | ||
| 106 | PD_WRITE(&pnob->fn_obj, cq_db, cqdb.dw[0]); | ||
| 107 | } | ||
| 108 | |||
| 109 | /* | ||
| 110 | This function disables the interrupt corresponding to the Event | ||
| 111 | queue ID for the given NetObject | ||
| 112 | */ | ||
| 113 | void be_disable_eq_intr(struct be_net_object *pnob) | ||
| 114 | { | ||
| 115 | struct CQ_DB_AMAP cqdb; | ||
| 116 | cqdb.dw[0] = 0; | ||
| 117 | AMAP_SET_BITS_PTR(CQ_DB, event, &cqdb, 1); | ||
| 118 | AMAP_SET_BITS_PTR(CQ_DB, rearm, &cqdb, 0); | ||
| 119 | AMAP_SET_BITS_PTR(CQ_DB, num_popped, &cqdb, 0); | ||
| 120 | AMAP_SET_BITS_PTR(CQ_DB, qid, &cqdb, pnob->event_q_id); | ||
| 121 | PD_WRITE(&pnob->fn_obj, cq_db, cqdb.dw[0]); | ||
| 122 | } | ||
| 123 | |||
| 124 | /* | ||
| 125 | This function enables the interrupt from the network function | ||
| 126 | of the BladeEngine. Use the function be_disable_eq_intr() | ||
| 127 | to enable the interrupt from the event queue of only one specific | ||
| 128 | NetObject | ||
| 129 | */ | ||
| 130 | void be_enable_intr(struct be_net_object *pnob) | ||
| 131 | { | ||
| 132 | struct PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP ctrl; | ||
| 133 | u32 host_intr; | ||
| 134 | |||
| 135 | ctrl.dw[0] = PCICFG1_READ(&pnob->fn_obj, host_timer_int_ctrl); | ||
| 136 | host_intr = AMAP_GET_BITS_PTR(PCICFG_HOST_TIMER_INT_CTRL_CSR, | ||
| 137 | hostintr, ctrl.dw); | ||
| 138 | if (!host_intr) { | ||
| 139 | AMAP_SET_BITS_PTR(PCICFG_HOST_TIMER_INT_CTRL_CSR, | ||
| 140 | hostintr, ctrl.dw, 1); | ||
| 141 | PCICFG1_WRITE(&pnob->fn_obj, host_timer_int_ctrl, | ||
| 142 | ctrl.dw[0]); | ||
| 143 | } | ||
| 144 | } | ||
| 145 | |||
| 146 | /* | ||
| 147 | This function disables the interrupt from the network function of | ||
| 148 | the BladeEngine. Use the function be_disable_eq_intr() to | ||
| 149 | disable the interrupt from the event queue of only one specific NetObject | ||
| 150 | */ | ||
| 151 | void be_disable_intr(struct be_net_object *pnob) | ||
| 152 | { | ||
| 153 | |||
| 154 | struct PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP ctrl; | ||
| 155 | u32 host_intr; | ||
| 156 | ctrl.dw[0] = PCICFG1_READ(&pnob->fn_obj, host_timer_int_ctrl); | ||
| 157 | host_intr = AMAP_GET_BITS_PTR(PCICFG_HOST_TIMER_INT_CTRL_CSR, | ||
| 158 | hostintr, ctrl.dw); | ||
| 159 | if (host_intr) { | ||
| 160 | AMAP_SET_BITS_PTR(PCICFG_HOST_TIMER_INT_CTRL_CSR, hostintr, | ||
| 161 | ctrl.dw, 0); | ||
| 162 | PCICFG1_WRITE(&pnob->fn_obj, host_timer_int_ctrl, | ||
| 163 | ctrl.dw[0]); | ||
| 164 | } | ||
| 165 | } | ||
| 166 | |||
| 167 | static int be_enable_msix(struct be_adapter *adapter) | ||
| 168 | { | ||
| 169 | int i, ret; | ||
| 170 | |||
| 171 | if (!msix) | ||
| 172 | return -1; | ||
| 173 | |||
| 174 | for (i = 0; i < BE_MAX_REQ_MSIX_VECTORS; i++) | ||
| 175 | adapter->msix_entries[i].entry = i; | ||
| 176 | |||
| 177 | ret = pci_enable_msix(adapter->pdev, adapter->msix_entries, | ||
| 178 | BE_MAX_REQ_MSIX_VECTORS); | ||
| 179 | |||
| 180 | if (ret == 0) | ||
| 181 | adapter->msix_enabled = 1; | ||
| 182 | return ret; | ||
| 183 | } | ||
| 184 | |||
| 185 | static int be_register_isr(struct be_adapter *adapter, | ||
| 186 | struct be_net_object *pnob) | ||
| 187 | { | ||
| 188 | struct net_device *netdev = pnob->netdev; | ||
| 189 | int intx = 0, r; | ||
| 190 | |||
| 191 | netdev->irq = adapter->pdev->irq; | ||
| 192 | r = be_enable_msix(adapter); | ||
| 193 | |||
| 194 | if (r == 0) { | ||
| 195 | r = request_irq(adapter->msix_entries[0].vector, | ||
| 196 | be_int, IRQF_SHARED, netdev->name, netdev); | ||
| 197 | if (r) { | ||
| 198 | printk(KERN_WARNING | ||
| 199 | "MSIX Request IRQ failed - Errno %d\n", r); | ||
| 200 | intx = 1; | ||
| 201 | pci_disable_msix(adapter->pdev); | ||
| 202 | adapter->msix_enabled = 0; | ||
| 203 | } | ||
| 204 | } else { | ||
| 205 | intx = 1; | ||
| 206 | } | ||
| 207 | |||
| 208 | if (intx) { | ||
| 209 | r = request_irq(netdev->irq, be_int, IRQF_SHARED, | ||
| 210 | netdev->name, netdev); | ||
| 211 | if (r) { | ||
| 212 | printk(KERN_WARNING | ||
| 213 | "INTx Request IRQ failed - Errno %d\n", r); | ||
| 214 | return -1; | ||
| 215 | } | ||
| 216 | } | ||
| 217 | adapter->isr_registered = 1; | ||
| 218 | return 0; | ||
| 219 | } | ||
| 220 | |||
| 221 | static void be_unregister_isr(struct be_adapter *adapter) | ||
| 222 | { | ||
| 223 | struct net_device *netdev = adapter->netdevp; | ||
| 224 | if (adapter->isr_registered) { | ||
| 225 | if (adapter->msix_enabled) { | ||
| 226 | free_irq(adapter->msix_entries[0].vector, netdev); | ||
| 227 | pci_disable_msix(adapter->pdev); | ||
| 228 | adapter->msix_enabled = 0; | ||
| 229 | } else { | ||
| 230 | free_irq(netdev->irq, netdev); | ||
| 231 | } | ||
| 232 | adapter->isr_registered = 0; | ||
| 233 | } | ||
| 234 | } | ||
| 235 | |||
| 236 | /* | ||
| 237 | This function processes the Flush Completions that are issued by the | ||
| 238 | ARM F/W, when a Recv Ring is destroyed. A flush completion is | ||
| 239 | identified when a Rx COmpl descriptor has the tcpcksum and udpcksum | ||
| 240 | set and the pktsize is 32. These completions are received on the | ||
| 241 | Rx Completion Queue. | ||
| 242 | */ | ||
| 243 | static u32 be_process_rx_flush_cmpl(struct be_net_object *pnob) | ||
| 244 | { | ||
| 245 | struct ETH_RX_COMPL_AMAP *rxcp; | ||
| 246 | unsigned int i = 0; | ||
| 247 | while ((rxcp = be_get_rx_cmpl(pnob)) != NULL) { | ||
| 248 | be_notify_cmpl(pnob, 1, pnob->rx_cq_id, 1); | ||
| 249 | i++; | ||
| 250 | } | ||
| 251 | return i; | ||
| 252 | } | ||
| 253 | |||
| 254 | static void be_tx_q_clean(struct be_net_object *pnob) | ||
| 255 | { | ||
| 256 | while (atomic_read(&pnob->tx_q_used)) | ||
| 257 | process_one_tx_compl(pnob, tx_compl_lastwrb_idx_get(pnob)); | ||
| 258 | } | ||
| 259 | |||
| 260 | static void be_rx_q_clean(struct be_net_object *pnob) | ||
| 261 | { | ||
| 262 | if (pnob->rx_ctxt) { | ||
| 263 | int i; | ||
| 264 | struct be_rx_page_info *rx_page_info; | ||
| 265 | for (i = 0; i < pnob->rx_q_len; i++) { | ||
| 266 | rx_page_info = &(pnob->rx_page_info[i]); | ||
| 267 | if (!pnob->rx_pg_shared || rx_page_info->page_offset) { | ||
| 268 | pci_unmap_page(pnob->adapter->pdev, | ||
| 269 | pci_unmap_addr(rx_page_info, bus), | ||
| 270 | pnob->rx_buf_size, | ||
| 271 | PCI_DMA_FROMDEVICE); | ||
| 272 | } | ||
| 273 | if (rx_page_info->page) | ||
| 274 | put_page(rx_page_info->page); | ||
| 275 | memset(rx_page_info, 0, sizeof(struct be_rx_page_info)); | ||
| 276 | } | ||
| 277 | pnob->rx_pg_info_hd = 0; | ||
| 278 | } | ||
| 279 | } | ||
| 280 | |||
| 281 | static void be_destroy_netobj(struct be_net_object *pnob) | ||
| 282 | { | ||
| 283 | int status; | ||
| 284 | |||
| 285 | if (pnob->tx_q_created) { | ||
| 286 | status = be_eth_sq_destroy(&pnob->tx_q_obj); | ||
| 287 | pnob->tx_q_created = 0; | ||
| 288 | } | ||
| 289 | |||
| 290 | if (pnob->rx_q_created) { | ||
| 291 | status = be_eth_rq_destroy(&pnob->rx_q_obj); | ||
| 292 | if (status != 0) { | ||
| 293 | status = be_eth_rq_destroy_options(&pnob->rx_q_obj, 0, | ||
| 294 | NULL, NULL); | ||
| 295 | BUG_ON(status); | ||
| 296 | } | ||
| 297 | pnob->rx_q_created = 0; | ||
| 298 | } | ||
| 299 | |||
| 300 | be_process_rx_flush_cmpl(pnob); | ||
| 301 | |||
| 302 | if (pnob->tx_cq_created) { | ||
| 303 | status = be_cq_destroy(&pnob->tx_cq_obj); | ||
| 304 | pnob->tx_cq_created = 0; | ||
| 305 | } | ||
| 306 | |||
| 307 | if (pnob->rx_cq_created) { | ||
| 308 | status = be_cq_destroy(&pnob->rx_cq_obj); | ||
| 309 | pnob->rx_cq_created = 0; | ||
| 310 | } | ||
| 311 | |||
| 312 | if (pnob->mcc_q_created) { | ||
| 313 | status = be_mcc_ring_destroy(&pnob->mcc_q_obj); | ||
| 314 | pnob->mcc_q_created = 0; | ||
| 315 | } | ||
| 316 | if (pnob->mcc_cq_created) { | ||
| 317 | status = be_cq_destroy(&pnob->mcc_cq_obj); | ||
| 318 | pnob->mcc_cq_created = 0; | ||
| 319 | } | ||
| 320 | |||
| 321 | if (pnob->event_q_created) { | ||
| 322 | status = be_eq_destroy(&pnob->event_q_obj); | ||
| 323 | pnob->event_q_created = 0; | ||
| 324 | } | ||
| 325 | be_function_cleanup(&pnob->fn_obj); | ||
| 326 | } | ||
| 327 | |||
| 328 | /* | ||
| 329 | * free all resources associated with a pnob | ||
| 330 | * Called at the time of module cleanup as well a any error during | ||
| 331 | * module init. Some resources may be partially allocated in a NetObj. | ||
| 332 | */ | ||
| 333 | static void netobject_cleanup(struct be_adapter *adapter, | ||
| 334 | struct be_net_object *pnob) | ||
| 335 | { | ||
| 336 | struct net_device *netdev = adapter->netdevp; | ||
| 337 | |||
| 338 | if (netif_running(netdev)) { | ||
| 339 | netif_stop_queue(netdev); | ||
| 340 | be_wait_nic_tx_cmplx_cmpl(pnob); | ||
| 341 | be_disable_eq_intr(pnob); | ||
| 342 | } | ||
| 343 | |||
| 344 | be_unregister_isr(adapter); | ||
| 345 | |||
| 346 | if (adapter->tasklet_started) { | ||
| 347 | tasklet_kill(&(adapter->sts_handler)); | ||
| 348 | adapter->tasklet_started = 0; | ||
| 349 | } | ||
| 350 | if (pnob->fn_obj_created) | ||
| 351 | be_disable_intr(pnob); | ||
| 352 | |||
| 353 | if (adapter->dev_state != BE_DEV_STATE_NONE) | ||
| 354 | unregister_netdev(netdev); | ||
| 355 | |||
| 356 | if (pnob->fn_obj_created) | ||
| 357 | be_destroy_netobj(pnob); | ||
| 358 | |||
| 359 | adapter->net_obj = NULL; | ||
| 360 | adapter->netdevp = NULL; | ||
| 361 | |||
| 362 | be_rx_q_clean(pnob); | ||
| 363 | if (pnob->rx_ctxt) { | ||
| 364 | kfree(pnob->rx_page_info); | ||
| 365 | kfree(pnob->rx_ctxt); | ||
| 366 | } | ||
| 367 | |||
| 368 | be_tx_q_clean(pnob); | ||
| 369 | kfree(pnob->tx_ctxt); | ||
| 370 | |||
| 371 | if (pnob->mcc_q) | ||
| 372 | pci_free_consistent(adapter->pdev, pnob->mcc_q_size, | ||
| 373 | pnob->mcc_q, pnob->mcc_q_bus); | ||
| 374 | |||
| 375 | if (pnob->mcc_wrb_ctxt) | ||
| 376 | free_pages((unsigned long)pnob->mcc_wrb_ctxt, | ||
| 377 | get_order(pnob->mcc_wrb_ctxt_size)); | ||
| 378 | |||
| 379 | if (pnob->mcc_cq) | ||
| 380 | pci_free_consistent(adapter->pdev, pnob->mcc_cq_size, | ||
| 381 | pnob->mcc_cq, pnob->mcc_cq_bus); | ||
| 382 | |||
| 383 | if (pnob->event_q) | ||
| 384 | pci_free_consistent(adapter->pdev, pnob->event_q_size, | ||
| 385 | pnob->event_q, pnob->event_q_bus); | ||
| 386 | |||
| 387 | if (pnob->tx_cq) | ||
| 388 | pci_free_consistent(adapter->pdev, pnob->tx_cq_size, | ||
| 389 | pnob->tx_cq, pnob->tx_cq_bus); | ||
| 390 | |||
| 391 | if (pnob->tx_q) | ||
| 392 | pci_free_consistent(adapter->pdev, pnob->tx_q_size, | ||
| 393 | pnob->tx_q, pnob->tx_q_bus); | ||
| 394 | |||
| 395 | if (pnob->rx_q) | ||
| 396 | pci_free_consistent(adapter->pdev, pnob->rx_q_size, | ||
| 397 | pnob->rx_q, pnob->rx_q_bus); | ||
| 398 | |||
| 399 | if (pnob->rx_cq) | ||
| 400 | pci_free_consistent(adapter->pdev, pnob->rx_cq_size, | ||
| 401 | pnob->rx_cq, pnob->rx_cq_bus); | ||
| 402 | |||
| 403 | |||
| 404 | if (pnob->mb_ptr) | ||
| 405 | pci_free_consistent(adapter->pdev, pnob->mb_size, pnob->mb_ptr, | ||
| 406 | pnob->mb_bus); | ||
| 407 | |||
| 408 | free_netdev(netdev); | ||
| 409 | } | ||
| 410 | |||
| 411 | |||
| 412 | static int be_nob_ring_alloc(struct be_adapter *adapter, | ||
| 413 | struct be_net_object *pnob) | ||
| 414 | { | ||
| 415 | u32 size; | ||
| 416 | |||
| 417 | /* Mail box rd; mailbox pointer needs to be 16 byte aligned */ | ||
| 418 | pnob->mb_size = sizeof(struct MCC_MAILBOX_AMAP) + 16; | ||
| 419 | pnob->mb_ptr = pci_alloc_consistent(adapter->pdev, pnob->mb_size, | ||
| 420 | &pnob->mb_bus); | ||
| 421 | if (!pnob->mb_bus) | ||
| 422 | return -1; | ||
| 423 | memset(pnob->mb_ptr, 0, pnob->mb_size); | ||
| 424 | pnob->mb_rd.va = PTR_ALIGN(pnob->mb_ptr, 16); | ||
| 425 | pnob->mb_rd.pa = PTR_ALIGN(pnob->mb_bus, 16); | ||
| 426 | pnob->mb_rd.length = sizeof(struct MCC_MAILBOX_AMAP); | ||
| 427 | /* | ||
| 428 | * Event queue | ||
| 429 | */ | ||
| 430 | pnob->event_q_len = EVENT_Q_LEN; | ||
| 431 | pnob->event_q_size = pnob->event_q_len * sizeof(struct EQ_ENTRY_AMAP); | ||
| 432 | pnob->event_q = pci_alloc_consistent(adapter->pdev, pnob->event_q_size, | ||
| 433 | &pnob->event_q_bus); | ||
| 434 | if (!pnob->event_q_bus) | ||
| 435 | return -1; | ||
| 436 | memset(pnob->event_q, 0, pnob->event_q_size); | ||
| 437 | /* | ||
| 438 | * Eth TX queue | ||
| 439 | */ | ||
| 440 | pnob->tx_q_len = ETH_TXQ_LEN; | ||
| 441 | pnob->tx_q_port = 0; | ||
| 442 | pnob->tx_q_size = pnob->tx_q_len * sizeof(struct ETH_WRB_AMAP); | ||
| 443 | pnob->tx_q = pci_alloc_consistent(adapter->pdev, pnob->tx_q_size, | ||
| 444 | &pnob->tx_q_bus); | ||
| 445 | if (!pnob->tx_q_bus) | ||
| 446 | return -1; | ||
| 447 | memset(pnob->tx_q, 0, pnob->tx_q_size); | ||
| 448 | /* | ||
| 449 | * Eth TX Compl queue | ||
| 450 | */ | ||
| 451 | pnob->txcq_len = ETH_TXCQ_LEN; | ||
| 452 | pnob->tx_cq_size = pnob->txcq_len * sizeof(struct ETH_TX_COMPL_AMAP); | ||
| 453 | pnob->tx_cq = pci_alloc_consistent(adapter->pdev, pnob->tx_cq_size, | ||
| 454 | &pnob->tx_cq_bus); | ||
| 455 | if (!pnob->tx_cq_bus) | ||
| 456 | return -1; | ||
| 457 | memset(pnob->tx_cq, 0, pnob->tx_cq_size); | ||
| 458 | /* | ||
| 459 | * Eth RX queue | ||
| 460 | */ | ||
| 461 | pnob->rx_q_len = ETH_RXQ_LEN; | ||
| 462 | pnob->rx_q_size = pnob->rx_q_len * sizeof(struct ETH_RX_D_AMAP); | ||
| 463 | pnob->rx_q = pci_alloc_consistent(adapter->pdev, pnob->rx_q_size, | ||
| 464 | &pnob->rx_q_bus); | ||
| 465 | if (!pnob->rx_q_bus) | ||
| 466 | return -1; | ||
| 467 | memset(pnob->rx_q, 0, pnob->rx_q_size); | ||
| 468 | /* | ||
| 469 | * Eth Unicast RX Compl queue | ||
| 470 | */ | ||
| 471 | pnob->rx_cq_len = ETH_UC_RXCQ_LEN; | ||
| 472 | pnob->rx_cq_size = pnob->rx_cq_len * | ||
| 473 | sizeof(struct ETH_RX_COMPL_AMAP); | ||
| 474 | pnob->rx_cq = pci_alloc_consistent(adapter->pdev, pnob->rx_cq_size, | ||
| 475 | &pnob->rx_cq_bus); | ||
| 476 | if (!pnob->rx_cq_bus) | ||
| 477 | return -1; | ||
| 478 | memset(pnob->rx_cq, 0, pnob->rx_cq_size); | ||
| 479 | |||
| 480 | /* TX resources */ | ||
| 481 | size = pnob->tx_q_len * sizeof(void **); | ||
| 482 | pnob->tx_ctxt = kzalloc(size, GFP_KERNEL); | ||
| 483 | if (pnob->tx_ctxt == NULL) | ||
| 484 | return -1; | ||
| 485 | |||
| 486 | /* RX resources */ | ||
| 487 | size = pnob->rx_q_len * sizeof(void *); | ||
| 488 | pnob->rx_ctxt = kzalloc(size, GFP_KERNEL); | ||
| 489 | if (pnob->rx_ctxt == NULL) | ||
| 490 | return -1; | ||
| 491 | |||
| 492 | size = (pnob->rx_q_len * sizeof(struct be_rx_page_info)); | ||
| 493 | pnob->rx_page_info = kzalloc(size, GFP_KERNEL); | ||
| 494 | if (pnob->rx_page_info == NULL) | ||
| 495 | return -1; | ||
| 496 | |||
| 497 | adapter->eth_statsp = kzalloc(sizeof(struct FWCMD_ETH_GET_STATISTICS), | ||
| 498 | GFP_KERNEL); | ||
| 499 | if (adapter->eth_statsp == NULL) | ||
| 500 | return -1; | ||
| 501 | pnob->rx_buf_size = rxbuf_size; | ||
| 502 | return 0; | ||
| 503 | } | ||
| 504 | |||
| 505 | /* | ||
| 506 | This function initializes the be_net_object for subsequent | ||
| 507 | network operations. | ||
| 508 | |||
| 509 | Before calling this function, the driver must have allocated | ||
| 510 | space for the NetObject structure, initialized the structure, | ||
| 511 | allocated DMAable memory for all the network queues that form | ||
| 512 | part of the NetObject and populated the start address (virtual) | ||
| 513 | and number of entries allocated for each queue in the NetObject structure. | ||
| 514 | |||
| 515 | The driver must also have allocated memory to hold the | ||
| 516 | mailbox structure (MCC_MAILBOX) and post the physical address, | ||
| 517 | virtual addresses and the size of the mailbox memory in the | ||
| 518 | NetObj.mb_rd. This structure is used by BECLIB for | ||
| 519 | initial communication with the embedded MCC processor. BECLIB | ||
| 520 | uses the mailbox until MCC rings are created for more efficient | ||
| 521 | communication with the MCC processor. | ||
| 522 | |||
| 523 | If the driver wants to create multiple network interface for more | ||
| 524 | than one protection domain, it can call be_create_netobj() | ||
| 525 | multiple times once for each protection domain. A Maximum of | ||
| 526 | 32 protection domains are supported. | ||
| 527 | |||
| 528 | */ | ||
| 529 | static int | ||
| 530 | be_create_netobj(struct be_net_object *pnob, u8 __iomem *csr_va, | ||
| 531 | u8 __iomem *db_va, u8 __iomem *pci_va) | ||
| 532 | { | ||
| 533 | int status = 0; | ||
| 534 | bool eventable = false, tx_no_delay = false, rx_no_delay = false; | ||
| 535 | struct be_eq_object *eq_objectp = NULL; | ||
| 536 | struct be_function_object *pfob = &pnob->fn_obj; | ||
| 537 | struct ring_desc rd; | ||
| 538 | u32 set_rxbuf_size; | ||
| 539 | u32 tx_cmpl_wm = CEV_WMARK_96; /* 0xffffffff to disable */ | ||
| 540 | u32 rx_cmpl_wm = CEV_WMARK_160; /* 0xffffffff to disable */ | ||
| 541 | u32 eq_delay = 0; /* delay in 8usec units. 0xffffffff to disable */ | ||
| 542 | |||
| 543 | memset(&rd, 0, sizeof(struct ring_desc)); | ||
| 544 | |||
| 545 | status = be_function_object_create(csr_va, db_va, pci_va, | ||
| 546 | BE_FUNCTION_TYPE_NETWORK, &pnob->mb_rd, pfob); | ||
| 547 | if (status != BE_SUCCESS) | ||
| 548 | return status; | ||
| 549 | pnob->fn_obj_created = true; | ||
| 550 | |||
| 551 | if (tx_cmpl_wm == 0xffffffff) | ||
| 552 | tx_no_delay = true; | ||
| 553 | if (rx_cmpl_wm == 0xffffffff) | ||
| 554 | rx_no_delay = true; | ||
| 555 | /* | ||
| 556 | * now create the necessary rings | ||
| 557 | * Event Queue first. | ||
| 558 | */ | ||
| 559 | if (pnob->event_q_len) { | ||
| 560 | rd.va = pnob->event_q; | ||
| 561 | rd.pa = pnob->event_q_bus; | ||
| 562 | rd.length = pnob->event_q_size; | ||
| 563 | |||
| 564 | status = be_eq_create(pfob, &rd, 4, pnob->event_q_len, | ||
| 565 | (u32) -1, /* CEV_WMARK_* or -1 */ | ||
| 566 | eq_delay, /* in 8us units, or -1 */ | ||
| 567 | &pnob->event_q_obj); | ||
| 568 | if (status != BE_SUCCESS) | ||
| 569 | goto error_ret; | ||
| 570 | pnob->event_q_id = pnob->event_q_obj.eq_id; | ||
| 571 | pnob->event_q_created = 1; | ||
| 572 | eventable = true; | ||
| 573 | eq_objectp = &pnob->event_q_obj; | ||
| 574 | } | ||
| 575 | /* | ||
| 576 | * Now Eth Tx Compl. queue. | ||
| 577 | */ | ||
| 578 | if (pnob->txcq_len) { | ||
| 579 | rd.va = pnob->tx_cq; | ||
| 580 | rd.pa = pnob->tx_cq_bus; | ||
| 581 | rd.length = pnob->tx_cq_size; | ||
| 582 | |||
| 583 | status = be_cq_create(pfob, &rd, | ||
| 584 | pnob->txcq_len * sizeof(struct ETH_TX_COMPL_AMAP), | ||
| 585 | false, /* solicted events, */ | ||
| 586 | tx_no_delay, /* nodelay */ | ||
| 587 | tx_cmpl_wm, /* Watermark encodings */ | ||
| 588 | eq_objectp, &pnob->tx_cq_obj); | ||
| 589 | if (status != BE_SUCCESS) | ||
| 590 | goto error_ret; | ||
| 591 | |||
| 592 | pnob->tx_cq_id = pnob->tx_cq_obj.cq_id; | ||
| 593 | pnob->tx_cq_created = 1; | ||
| 594 | } | ||
| 595 | /* | ||
| 596 | * Eth Tx queue | ||
| 597 | */ | ||
| 598 | if (pnob->tx_q_len) { | ||
| 599 | struct be_eth_sq_parameters ex_params = { 0 }; | ||
| 600 | u32 type; | ||
| 601 | |||
| 602 | if (pnob->tx_q_port) { | ||
| 603 | /* TXQ to be bound to a specific port */ | ||
| 604 | type = BE_ETH_TX_RING_TYPE_BOUND; | ||
| 605 | ex_params.port = pnob->tx_q_port - 1; | ||
| 606 | } else | ||
| 607 | type = BE_ETH_TX_RING_TYPE_STANDARD; | ||
| 608 | |||
| 609 | rd.va = pnob->tx_q; | ||
| 610 | rd.pa = pnob->tx_q_bus; | ||
| 611 | rd.length = pnob->tx_q_size; | ||
| 612 | |||
| 613 | status = be_eth_sq_create_ex(pfob, &rd, | ||
| 614 | pnob->tx_q_len * sizeof(struct ETH_WRB_AMAP), | ||
| 615 | type, 2, &pnob->tx_cq_obj, | ||
| 616 | &ex_params, &pnob->tx_q_obj); | ||
| 617 | |||
| 618 | if (status != BE_SUCCESS) | ||
| 619 | goto error_ret; | ||
| 620 | |||
| 621 | pnob->tx_q_id = pnob->tx_q_obj.bid; | ||
| 622 | pnob->tx_q_created = 1; | ||
| 623 | } | ||
| 624 | /* | ||
| 625 | * Now Eth Rx compl. queue. Always needed. | ||
| 626 | */ | ||
| 627 | rd.va = pnob->rx_cq; | ||
| 628 | rd.pa = pnob->rx_cq_bus; | ||
| 629 | rd.length = pnob->rx_cq_size; | ||
| 630 | |||
| 631 | status = be_cq_create(pfob, &rd, | ||
| 632 | pnob->rx_cq_len * sizeof(struct ETH_RX_COMPL_AMAP), | ||
| 633 | false, /* solicted events, */ | ||
| 634 | rx_no_delay, /* nodelay */ | ||
| 635 | rx_cmpl_wm, /* Watermark encodings */ | ||
| 636 | eq_objectp, &pnob->rx_cq_obj); | ||
| 637 | if (status != BE_SUCCESS) | ||
| 638 | goto error_ret; | ||
| 639 | |||
| 640 | pnob->rx_cq_id = pnob->rx_cq_obj.cq_id; | ||
| 641 | pnob->rx_cq_created = 1; | ||
| 642 | |||
| 643 | status = be_eth_rq_set_frag_size(pfob, pnob->rx_buf_size, | ||
| 644 | (u32 *) &set_rxbuf_size); | ||
| 645 | if (status != BE_SUCCESS) { | ||
| 646 | be_eth_rq_get_frag_size(pfob, (u32 *) &pnob->rx_buf_size); | ||
| 647 | if ((pnob->rx_buf_size != 2048) && (pnob->rx_buf_size != 4096) | ||
| 648 | && (pnob->rx_buf_size != 8192)) | ||
| 649 | goto error_ret; | ||
| 650 | } else { | ||
| 651 | if (pnob->rx_buf_size != set_rxbuf_size) | ||
| 652 | pnob->rx_buf_size = set_rxbuf_size; | ||
| 653 | } | ||
| 654 | /* | ||
| 655 | * Eth RX queue. be_eth_rq_create() always assumes 2 pages size | ||
| 656 | */ | ||
| 657 | rd.va = pnob->rx_q; | ||
| 658 | rd.pa = pnob->rx_q_bus; | ||
| 659 | rd.length = pnob->rx_q_size; | ||
| 660 | |||
| 661 | status = be_eth_rq_create(pfob, &rd, &pnob->rx_cq_obj, | ||
| 662 | &pnob->rx_cq_obj, &pnob->rx_q_obj); | ||
| 663 | |||
| 664 | if (status != BE_SUCCESS) | ||
| 665 | goto error_ret; | ||
| 666 | |||
| 667 | pnob->rx_q_id = pnob->rx_q_obj.rid; | ||
| 668 | pnob->rx_q_created = 1; | ||
| 669 | |||
| 670 | return BE_SUCCESS; /* All required queues created. */ | ||
| 671 | |||
| 672 | error_ret: | ||
| 673 | be_destroy_netobj(pnob); | ||
| 674 | return status; | ||
| 675 | } | ||
| 676 | |||
| 677 | static int be_nob_ring_init(struct be_adapter *adapter, | ||
| 678 | struct be_net_object *pnob) | ||
| 679 | { | ||
| 680 | int status; | ||
| 681 | |||
| 682 | pnob->event_q_tl = 0; | ||
| 683 | |||
| 684 | pnob->tx_q_hd = 0; | ||
| 685 | pnob->tx_q_tl = 0; | ||
| 686 | |||
| 687 | pnob->tx_cq_tl = 0; | ||
| 688 | |||
| 689 | pnob->rx_cq_tl = 0; | ||
| 690 | |||
| 691 | memset(pnob->event_q, 0, pnob->event_q_size); | ||
| 692 | memset(pnob->tx_cq, 0, pnob->tx_cq_size); | ||
| 693 | memset(pnob->tx_ctxt, 0, pnob->tx_q_len * sizeof(void **)); | ||
| 694 | memset(pnob->rx_ctxt, 0, pnob->rx_q_len * sizeof(void *)); | ||
| 695 | pnob->rx_pg_info_hd = 0; | ||
| 696 | pnob->rx_q_hd = 0; | ||
| 697 | atomic_set(&pnob->rx_q_posted, 0); | ||
| 698 | |||
| 699 | status = be_create_netobj(pnob, adapter->csr_va, adapter->db_va, | ||
| 700 | adapter->pci_va); | ||
| 701 | if (status != BE_SUCCESS) | ||
| 702 | return -1; | ||
| 703 | |||
| 704 | be_post_eth_rx_buffs(pnob); | ||
| 705 | return 0; | ||
| 706 | } | ||
| 707 | |||
| 708 | /* This function handles async callback for link status */ | ||
| 709 | static void | ||
| 710 | be_link_status_async_callback(void *context, u32 event_code, void *event) | ||
| 711 | { | ||
| 712 | struct ASYNC_EVENT_LINK_STATE_AMAP *link_status = event; | ||
| 713 | struct be_adapter *adapter = context; | ||
| 714 | bool link_enable = false; | ||
| 715 | struct be_net_object *pnob; | ||
| 716 | struct ASYNC_EVENT_TRAILER_AMAP *async_trailer; | ||
| 717 | struct net_device *netdev; | ||
| 718 | u32 async_event_code, async_event_type, active_port; | ||
| 719 | u32 port0_link_status, port1_link_status, port0_duplex, port1_duplex; | ||
| 720 | u32 port0_speed, port1_speed; | ||
| 721 | |||
| 722 | if (event_code != ASYNC_EVENT_CODE_LINK_STATE) { | ||
| 723 | /* Not our event to handle */ | ||
| 724 | return; | ||
| 725 | } | ||
| 726 | async_trailer = (struct ASYNC_EVENT_TRAILER_AMAP *) | ||
| 727 | ((u8 *) event + sizeof(struct MCC_CQ_ENTRY_AMAP) - | ||
| 728 | sizeof(struct ASYNC_EVENT_TRAILER_AMAP)); | ||
| 729 | |||
| 730 | async_event_code = AMAP_GET_BITS_PTR(ASYNC_EVENT_TRAILER, event_code, | ||
| 731 | async_trailer); | ||
| 732 | BUG_ON(async_event_code != ASYNC_EVENT_CODE_LINK_STATE); | ||
| 733 | |||
| 734 | pnob = adapter->net_obj; | ||
| 735 | netdev = pnob->netdev; | ||
| 736 | |||
| 737 | /* Determine if this event is a switch VLD or a physical link event */ | ||
| 738 | async_event_type = AMAP_GET_BITS_PTR(ASYNC_EVENT_TRAILER, event_type, | ||
| 739 | async_trailer); | ||
| 740 | active_port = AMAP_GET_BITS_PTR(ASYNC_EVENT_LINK_STATE, | ||
| 741 | active_port, link_status); | ||
| 742 | port0_link_status = AMAP_GET_BITS_PTR(ASYNC_EVENT_LINK_STATE, | ||
| 743 | port0_link_status, link_status); | ||
| 744 | port1_link_status = AMAP_GET_BITS_PTR(ASYNC_EVENT_LINK_STATE, | ||
| 745 | port1_link_status, link_status); | ||
| 746 | port0_duplex = AMAP_GET_BITS_PTR(ASYNC_EVENT_LINK_STATE, | ||
| 747 | port0_duplex, link_status); | ||
| 748 | port1_duplex = AMAP_GET_BITS_PTR(ASYNC_EVENT_LINK_STATE, | ||
| 749 | port1_duplex, link_status); | ||
| 750 | port0_speed = AMAP_GET_BITS_PTR(ASYNC_EVENT_LINK_STATE, | ||
| 751 | port0_speed, link_status); | ||
| 752 | port1_speed = AMAP_GET_BITS_PTR(ASYNC_EVENT_LINK_STATE, | ||
| 753 | port1_speed, link_status); | ||
| 754 | if (async_event_type == NTWK_LINK_TYPE_VIRTUAL) { | ||
| 755 | adapter->be_stat.bes_link_change_virtual++; | ||
| 756 | if (adapter->be_link_sts->active_port != active_port) { | ||
| 757 | dev_notice(&netdev->dev, | ||
| 758 | "Active port changed due to VLD on switch\n"); | ||
| 759 | } else { | ||
| 760 | dev_notice(&netdev->dev, "Link status update\n"); | ||
| 761 | } | ||
| 762 | |||
| 763 | } else { | ||
| 764 | adapter->be_stat.bes_link_change_physical++; | ||
| 765 | if (adapter->be_link_sts->active_port != active_port) { | ||
| 766 | dev_notice(&netdev->dev, | ||
| 767 | "Active port changed due to port link" | ||
| 768 | " status change\n"); | ||
| 769 | } else { | ||
| 770 | dev_notice(&netdev->dev, "Link status update\n"); | ||
| 771 | } | ||
| 772 | } | ||
| 773 | |||
| 774 | memset(adapter->be_link_sts, 0, sizeof(adapter->be_link_sts)); | ||
| 775 | |||
| 776 | if ((port0_link_status == ASYNC_EVENT_LINK_UP) || | ||
| 777 | (port1_link_status == ASYNC_EVENT_LINK_UP)) { | ||
| 778 | if ((adapter->port0_link_sts == BE_PORT_LINK_DOWN) && | ||
| 779 | (adapter->port1_link_sts == BE_PORT_LINK_DOWN)) { | ||
| 780 | /* Earlier both the ports are down So link is up */ | ||
| 781 | link_enable = true; | ||
| 782 | } | ||
| 783 | |||
| 784 | if (port0_link_status == ASYNC_EVENT_LINK_UP) { | ||
| 785 | adapter->port0_link_sts = BE_PORT_LINK_UP; | ||
| 786 | adapter->be_link_sts->mac0_duplex = port0_duplex; | ||
| 787 | adapter->be_link_sts->mac0_speed = port0_speed; | ||
| 788 | if (active_port == NTWK_PORT_A) | ||
| 789 | adapter->be_link_sts->active_port = 0; | ||
| 790 | } else | ||
| 791 | adapter->port0_link_sts = BE_PORT_LINK_DOWN; | ||
| 792 | |||
| 793 | if (port1_link_status == ASYNC_EVENT_LINK_UP) { | ||
| 794 | adapter->port1_link_sts = BE_PORT_LINK_UP; | ||
| 795 | adapter->be_link_sts->mac1_duplex = port1_duplex; | ||
| 796 | adapter->be_link_sts->mac1_speed = port1_speed; | ||
| 797 | if (active_port == NTWK_PORT_B) | ||
| 798 | adapter->be_link_sts->active_port = 1; | ||
| 799 | } else | ||
| 800 | adapter->port1_link_sts = BE_PORT_LINK_DOWN; | ||
| 801 | |||
| 802 | printk(KERN_INFO "Link Properties for %s:\n", netdev->name); | ||
| 803 | dev_info(&netdev->dev, "Link Properties:\n"); | ||
| 804 | be_print_link_info(adapter->be_link_sts); | ||
| 805 | |||
| 806 | if (!link_enable) | ||
| 807 | return; | ||
| 808 | /* | ||
| 809 | * Both ports were down previously, but atleast one of | ||
| 810 | * them has come up if this netdevice's carrier is not up, | ||
| 811 | * then indicate to stack | ||
| 812 | */ | ||
| 813 | if (!netif_carrier_ok(netdev)) { | ||
| 814 | netif_start_queue(netdev); | ||
| 815 | netif_carrier_on(netdev); | ||
| 816 | } | ||
| 817 | return; | ||
| 818 | } | ||
| 819 | |||
| 820 | /* Now both the ports are down. Tell the stack about it */ | ||
| 821 | dev_info(&netdev->dev, "Both ports are down\n"); | ||
| 822 | adapter->port0_link_sts = BE_PORT_LINK_DOWN; | ||
| 823 | adapter->port1_link_sts = BE_PORT_LINK_DOWN; | ||
| 824 | if (netif_carrier_ok(netdev)) { | ||
| 825 | netif_carrier_off(netdev); | ||
| 826 | netif_stop_queue(netdev); | ||
| 827 | } | ||
| 828 | return; | ||
| 829 | } | ||
| 830 | |||
| 831 | static int be_mcc_create(struct be_adapter *adapter) | ||
| 832 | { | ||
| 833 | struct be_net_object *pnob; | ||
| 834 | |||
| 835 | pnob = adapter->net_obj; | ||
| 836 | /* | ||
| 837 | * Create the MCC ring so that all further communication with | ||
| 838 | * MCC can go thru the ring. we do this at the end since | ||
| 839 | * we do not want to be dealing with interrupts until the | ||
| 840 | * initialization is complete. | ||
| 841 | */ | ||
| 842 | pnob->mcc_q_len = MCC_Q_LEN; | ||
| 843 | pnob->mcc_q_size = pnob->mcc_q_len * sizeof(struct MCC_WRB_AMAP); | ||
| 844 | pnob->mcc_q = pci_alloc_consistent(adapter->pdev, pnob->mcc_q_size, | ||
| 845 | &pnob->mcc_q_bus); | ||
| 846 | if (!pnob->mcc_q_bus) | ||
| 847 | return -1; | ||
| 848 | /* | ||
| 849 | * space for MCC WRB context | ||
| 850 | */ | ||
| 851 | pnob->mcc_wrb_ctxtLen = MCC_Q_LEN; | ||
| 852 | pnob->mcc_wrb_ctxt_size = pnob->mcc_wrb_ctxtLen * | ||
| 853 | sizeof(struct be_mcc_wrb_context); | ||
| 854 | pnob->mcc_wrb_ctxt = (void *)__get_free_pages(GFP_KERNEL, | ||
| 855 | get_order(pnob->mcc_wrb_ctxt_size)); | ||
| 856 | if (pnob->mcc_wrb_ctxt == NULL) | ||
| 857 | return -1; | ||
| 858 | /* | ||
| 859 | * Space for MCC compl. ring | ||
| 860 | */ | ||
| 861 | pnob->mcc_cq_len = MCC_CQ_LEN; | ||
| 862 | pnob->mcc_cq_size = pnob->mcc_cq_len * sizeof(struct MCC_CQ_ENTRY_AMAP); | ||
| 863 | pnob->mcc_cq = pci_alloc_consistent(adapter->pdev, pnob->mcc_cq_size, | ||
| 864 | &pnob->mcc_cq_bus); | ||
| 865 | if (!pnob->mcc_cq_bus) | ||
| 866 | return -1; | ||
| 867 | return 0; | ||
| 868 | } | ||
| 869 | |||
| 870 | /* | ||
| 871 | This function creates the MCC request and completion ring required | ||
| 872 | for communicating with the ARM processor. The caller must have | ||
| 873 | allocated required amount of memory for the MCC ring and MCC | ||
| 874 | completion ring and posted the virtual address and number of | ||
| 875 | entries in the corresponding members (mcc_q and mcc_cq) in the | ||
| 876 | NetObject struture. | ||
| 877 | |||
| 878 | When this call is completed, all further communication with | ||
| 879 | ARM will switch from mailbox to this ring. | ||
| 880 | |||
| 881 | pnob - Pointer to the NetObject structure. This NetObject should | ||
| 882 | have been created using a previous call to be_create_netobj() | ||
| 883 | */ | ||
| 884 | int be_create_mcc_rings(struct be_net_object *pnob) | ||
| 885 | { | ||
| 886 | int status = 0; | ||
| 887 | struct ring_desc rd; | ||
| 888 | struct be_function_object *pfob = &pnob->fn_obj; | ||
| 889 | |||
| 890 | memset(&rd, 0, sizeof(struct ring_desc)); | ||
| 891 | if (pnob->mcc_cq_len) { | ||
| 892 | rd.va = pnob->mcc_cq; | ||
| 893 | rd.pa = pnob->mcc_cq_bus; | ||
| 894 | rd.length = pnob->mcc_cq_size; | ||
| 895 | |||
| 896 | status = be_cq_create(pfob, &rd, | ||
| 897 | pnob->mcc_cq_len * sizeof(struct MCC_CQ_ENTRY_AMAP), | ||
| 898 | false, /* solicted events, */ | ||
| 899 | true, /* nodelay */ | ||
| 900 | 0, /* 0 Watermark since Nodelay is true */ | ||
| 901 | &pnob->event_q_obj, | ||
| 902 | &pnob->mcc_cq_obj); | ||
| 903 | |||
| 904 | if (status != BE_SUCCESS) | ||
| 905 | return status; | ||
| 906 | |||
| 907 | pnob->mcc_cq_id = pnob->mcc_cq_obj.cq_id; | ||
| 908 | pnob->mcc_cq_created = 1; | ||
| 909 | } | ||
| 910 | if (pnob->mcc_q_len) { | ||
| 911 | rd.va = pnob->mcc_q; | ||
| 912 | rd.pa = pnob->mcc_q_bus; | ||
| 913 | rd.length = pnob->mcc_q_size; | ||
| 914 | |||
| 915 | status = be_mcc_ring_create(pfob, &rd, | ||
| 916 | pnob->mcc_q_len * sizeof(struct MCC_WRB_AMAP), | ||
| 917 | pnob->mcc_wrb_ctxt, pnob->mcc_wrb_ctxtLen, | ||
| 918 | &pnob->mcc_cq_obj, &pnob->mcc_q_obj); | ||
| 919 | |||
| 920 | if (status != BE_SUCCESS) | ||
| 921 | return status; | ||
| 922 | |||
| 923 | pnob->mcc_q_created = 1; | ||
| 924 | } | ||
| 925 | return BE_SUCCESS; | ||
| 926 | } | ||
| 927 | |||
| 928 | static int be_mcc_init(struct be_adapter *adapter) | ||
| 929 | { | ||
| 930 | u32 r; | ||
| 931 | struct be_net_object *pnob; | ||
| 932 | |||
| 933 | pnob = adapter->net_obj; | ||
| 934 | memset(pnob->mcc_q, 0, pnob->mcc_q_size); | ||
| 935 | pnob->mcc_q_hd = 0; | ||
| 936 | |||
| 937 | memset(pnob->mcc_wrb_ctxt, 0, pnob->mcc_wrb_ctxt_size); | ||
| 938 | |||
| 939 | memset(pnob->mcc_cq, 0, pnob->mcc_cq_size); | ||
| 940 | pnob->mcc_cq_tl = 0; | ||
| 941 | |||
| 942 | r = be_create_mcc_rings(adapter->net_obj); | ||
| 943 | if (r != BE_SUCCESS) | ||
| 944 | return -1; | ||
| 945 | |||
| 946 | return 0; | ||
| 947 | } | ||
| 948 | |||
| 949 | static void be_remove(struct pci_dev *pdev) | ||
| 950 | { | ||
| 951 | struct be_net_object *pnob; | ||
| 952 | struct be_adapter *adapter; | ||
| 953 | |||
| 954 | adapter = pci_get_drvdata(pdev); | ||
| 955 | if (!adapter) | ||
| 956 | return; | ||
| 957 | |||
| 958 | pci_set_drvdata(pdev, NULL); | ||
| 959 | pnob = (struct be_net_object *)adapter->net_obj; | ||
| 960 | |||
| 961 | flush_scheduled_work(); | ||
| 962 | |||
| 963 | if (pnob) { | ||
| 964 | /* Unregister async callback function for link status updates */ | ||
| 965 | if (pnob->mcc_q_created) | ||
| 966 | be_mcc_add_async_event_callback(&pnob->mcc_q_obj, | ||
| 967 | NULL, NULL); | ||
| 968 | netobject_cleanup(adapter, pnob); | ||
| 969 | } | ||
| 970 | |||
| 971 | if (adapter->csr_va) | ||
| 972 | iounmap(adapter->csr_va); | ||
| 973 | if (adapter->db_va) | ||
| 974 | iounmap(adapter->db_va); | ||
| 975 | if (adapter->pci_va) | ||
| 976 | iounmap(adapter->pci_va); | ||
| 977 | |||
| 978 | pci_release_regions(adapter->pdev); | ||
| 979 | pci_disable_device(adapter->pdev); | ||
| 980 | |||
| 981 | kfree(adapter->be_link_sts); | ||
| 982 | kfree(adapter->eth_statsp); | ||
| 983 | |||
| 984 | if (adapter->timer_ctxt.get_stats_timer.function) | ||
| 985 | del_timer_sync(&adapter->timer_ctxt.get_stats_timer); | ||
| 986 | kfree(adapter); | ||
| 987 | } | ||
| 988 | |||
| 989 | /* | ||
| 990 | * This function is called by the PCI sub-system when it finds a PCI | ||
| 991 | * device with dev/vendor IDs that match with one of our devices. | ||
| 992 | * All of the driver initialization is done in this function. | ||
| 993 | */ | ||
| 994 | static int be_probe(struct pci_dev *pdev, const struct pci_device_id *pdev_id) | ||
| 995 | { | ||
| 996 | int status = 0; | ||
| 997 | struct be_adapter *adapter; | ||
| 998 | struct FWCMD_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD get_fwv; | ||
| 999 | struct be_net_object *pnob; | ||
| 1000 | struct net_device *netdev; | ||
| 1001 | |||
| 1002 | status = pci_enable_device(pdev); | ||
| 1003 | if (status) | ||
| 1004 | goto error; | ||
| 1005 | |||
| 1006 | status = pci_request_regions(pdev, be_driver_name); | ||
| 1007 | if (status) | ||
| 1008 | goto error_pci_req; | ||
| 1009 | |||
| 1010 | pci_set_master(pdev); | ||
| 1011 | adapter = kzalloc(sizeof(struct be_adapter), GFP_KERNEL); | ||
| 1012 | if (adapter == NULL) { | ||
| 1013 | status = -ENOMEM; | ||
| 1014 | goto error_adapter; | ||
| 1015 | } | ||
| 1016 | adapter->dev_state = BE_DEV_STATE_NONE; | ||
| 1017 | adapter->pdev = pdev; | ||
| 1018 | pci_set_drvdata(pdev, adapter); | ||
| 1019 | |||
| 1020 | adapter->enable_aic = 1; | ||
| 1021 | adapter->max_eqd = MAX_EQD; | ||
| 1022 | adapter->min_eqd = 0; | ||
| 1023 | adapter->cur_eqd = 0; | ||
| 1024 | |||
| 1025 | status = pci_set_dma_mask(pdev, DMA_64BIT_MASK); | ||
| 1026 | if (!status) { | ||
| 1027 | adapter->dma_64bit_cap = true; | ||
| 1028 | } else { | ||
| 1029 | adapter->dma_64bit_cap = false; | ||
| 1030 | status = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | ||
| 1031 | if (status != 0) { | ||
| 1032 | printk(KERN_ERR "Could not set PCI DMA Mask\n"); | ||
| 1033 | goto cleanup; | ||
| 1034 | } | ||
| 1035 | } | ||
| 1036 | |||
| 1037 | status = init_pci_be_function(adapter, pdev); | ||
| 1038 | if (status != 0) { | ||
| 1039 | printk(KERN_ERR "Failed to map PCI BARS\n"); | ||
| 1040 | status = -ENOMEM; | ||
| 1041 | goto cleanup; | ||
| 1042 | } | ||
| 1043 | |||
| 1044 | be_trace_set_level(DL_ALWAYS | DL_ERR); | ||
| 1045 | |||
| 1046 | adapter->be_link_sts = kmalloc(sizeof(struct BE_LINK_STATUS), | ||
| 1047 | GFP_KERNEL); | ||
| 1048 | if (adapter->be_link_sts == NULL) { | ||
| 1049 | printk(KERN_ERR "Memory allocation for link status " | ||
| 1050 | "buffer failed\n"); | ||
| 1051 | goto cleanup; | ||
| 1052 | } | ||
| 1053 | spin_lock_init(&adapter->txq_lock); | ||
| 1054 | |||
| 1055 | netdev = alloc_etherdev(sizeof(struct be_net_object)); | ||
| 1056 | if (netdev == NULL) { | ||
| 1057 | status = -ENOMEM; | ||
| 1058 | goto cleanup; | ||
| 1059 | } | ||
| 1060 | pnob = netdev_priv(netdev); | ||
| 1061 | adapter->net_obj = pnob; | ||
| 1062 | adapter->netdevp = netdev; | ||
| 1063 | pnob->adapter = adapter; | ||
| 1064 | pnob->netdev = netdev; | ||
| 1065 | |||
| 1066 | status = be_nob_ring_alloc(adapter, pnob); | ||
| 1067 | if (status != 0) | ||
| 1068 | goto cleanup; | ||
| 1069 | |||
| 1070 | status = be_nob_ring_init(adapter, pnob); | ||
| 1071 | if (status != 0) | ||
| 1072 | goto cleanup; | ||
| 1073 | |||
| 1074 | be_rxf_mac_address_read_write(&pnob->fn_obj, false, false, false, | ||
| 1075 | false, false, netdev->dev_addr, NULL, NULL); | ||
| 1076 | |||
| 1077 | netdev->init = &benet_init; | ||
| 1078 | netif_carrier_off(netdev); | ||
| 1079 | netif_stop_queue(netdev); | ||
| 1080 | |||
| 1081 | SET_NETDEV_DEV(netdev, &(adapter->pdev->dev)); | ||
| 1082 | |||
| 1083 | netif_napi_add(netdev, &pnob->napi, be_poll, 64); | ||
| 1084 | |||
| 1085 | /* if the rx_frag size if 2K, one page is shared as two RX frags */ | ||
| 1086 | pnob->rx_pg_shared = | ||
| 1087 | (pnob->rx_buf_size <= PAGE_SIZE / 2) ? true : false; | ||
| 1088 | if (pnob->rx_buf_size != rxbuf_size) { | ||
| 1089 | printk(KERN_WARNING | ||
| 1090 | "Could not set Rx buffer size to %d. Using %d\n", | ||
| 1091 | rxbuf_size, pnob->rx_buf_size); | ||
| 1092 | rxbuf_size = pnob->rx_buf_size; | ||
| 1093 | } | ||
| 1094 | |||
| 1095 | tasklet_init(&(adapter->sts_handler), be_process_intr, | ||
| 1096 | (unsigned long)adapter); | ||
| 1097 | adapter->tasklet_started = 1; | ||
| 1098 | spin_lock_init(&(adapter->int_lock)); | ||
| 1099 | |||
| 1100 | status = be_register_isr(adapter, pnob); | ||
| 1101 | if (status != 0) | ||
| 1102 | goto cleanup; | ||
| 1103 | |||
| 1104 | adapter->rx_csum = 1; | ||
| 1105 | adapter->max_rx_coal = BE_LRO_MAX_PKTS; | ||
| 1106 | |||
| 1107 | memset(&get_fwv, 0, | ||
| 1108 | sizeof(struct FWCMD_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD)); | ||
| 1109 | printk(KERN_INFO "BladeEngine Driver version:%s. " | ||
| 1110 | "Copyright ServerEngines, Corporation 2005 - 2008\n", | ||
| 1111 | be_drvr_ver); | ||
| 1112 | status = be_function_get_fw_version(&pnob->fn_obj, &get_fwv, NULL, | ||
| 1113 | NULL); | ||
| 1114 | if (status == BE_SUCCESS) { | ||
| 1115 | strncpy(be_fw_ver, get_fwv.firmware_version_string, 32); | ||
| 1116 | printk(KERN_INFO "BladeEngine Firmware Version:%s\n", | ||
| 1117 | get_fwv.firmware_version_string); | ||
| 1118 | } else { | ||
| 1119 | printk(KERN_WARNING "Unable to get BE Firmware Version\n"); | ||
| 1120 | } | ||
| 1121 | |||
| 1122 | sema_init(&adapter->get_eth_stat_sem, 0); | ||
| 1123 | init_timer(&adapter->timer_ctxt.get_stats_timer); | ||
| 1124 | atomic_set(&adapter->timer_ctxt.get_stat_flag, 0); | ||
| 1125 | adapter->timer_ctxt.get_stats_timer.function = | ||
| 1126 | &be_get_stats_timer_handler; | ||
| 1127 | |||
| 1128 | status = be_mcc_create(adapter); | ||
| 1129 | if (status < 0) | ||
| 1130 | goto cleanup; | ||
| 1131 | status = be_mcc_init(adapter); | ||
| 1132 | if (status < 0) | ||
| 1133 | goto cleanup; | ||
| 1134 | |||
| 1135 | |||
| 1136 | status = be_mcc_add_async_event_callback(&adapter->net_obj->mcc_q_obj, | ||
| 1137 | be_link_status_async_callback, (void *)adapter); | ||
| 1138 | if (status != BE_SUCCESS) { | ||
| 1139 | printk(KERN_WARNING "add_async_event_callback failed"); | ||
| 1140 | printk(KERN_WARNING | ||
| 1141 | "Link status changes may not be reflected\n"); | ||
| 1142 | } | ||
| 1143 | |||
| 1144 | status = register_netdev(netdev); | ||
| 1145 | if (status != 0) | ||
| 1146 | goto cleanup; | ||
| 1147 | be_update_link_status(adapter); | ||
| 1148 | adapter->dev_state = BE_DEV_STATE_INIT; | ||
| 1149 | return 0; | ||
| 1150 | |||
| 1151 | cleanup: | ||
| 1152 | be_remove(pdev); | ||
| 1153 | return status; | ||
| 1154 | error_adapter: | ||
| 1155 | pci_release_regions(pdev); | ||
| 1156 | error_pci_req: | ||
| 1157 | pci_disable_device(pdev); | ||
| 1158 | error: | ||
| 1159 | printk(KERN_ERR "BladeEngine initalization failed\n"); | ||
| 1160 | return status; | ||
| 1161 | } | ||
| 1162 | |||
| 1163 | /* | ||
| 1164 | * Get the current link status and print the status on console | ||
| 1165 | */ | ||
| 1166 | void be_update_link_status(struct be_adapter *adapter) | ||
| 1167 | { | ||
| 1168 | int status; | ||
| 1169 | struct be_net_object *pnob = adapter->net_obj; | ||
| 1170 | |||
| 1171 | status = be_rxf_link_status(&pnob->fn_obj, adapter->be_link_sts, NULL, | ||
| 1172 | NULL, NULL); | ||
| 1173 | if (status == BE_SUCCESS) { | ||
| 1174 | if (adapter->be_link_sts->mac0_speed && | ||
| 1175 | adapter->be_link_sts->mac0_duplex) | ||
| 1176 | adapter->port0_link_sts = BE_PORT_LINK_UP; | ||
| 1177 | else | ||
| 1178 | adapter->port0_link_sts = BE_PORT_LINK_DOWN; | ||
| 1179 | |||
| 1180 | if (adapter->be_link_sts->mac1_speed && | ||
| 1181 | adapter->be_link_sts->mac1_duplex) | ||
| 1182 | adapter->port1_link_sts = BE_PORT_LINK_UP; | ||
| 1183 | else | ||
| 1184 | adapter->port1_link_sts = BE_PORT_LINK_DOWN; | ||
| 1185 | |||
| 1186 | dev_info(&pnob->netdev->dev, "Link Properties:\n"); | ||
| 1187 | be_print_link_info(adapter->be_link_sts); | ||
| 1188 | return; | ||
| 1189 | } | ||
| 1190 | dev_info(&pnob->netdev->dev, "Could not get link status\n"); | ||
| 1191 | return; | ||
| 1192 | } | ||
| 1193 | |||
| 1194 | |||
| 1195 | #ifdef CONFIG_PM | ||
| 1196 | static void | ||
| 1197 | be_pm_cleanup(struct be_adapter *adapter, | ||
| 1198 | struct be_net_object *pnob, struct net_device *netdev) | ||
| 1199 | { | ||
| 1200 | netif_carrier_off(netdev); | ||
| 1201 | netif_stop_queue(netdev); | ||
| 1202 | |||
| 1203 | be_wait_nic_tx_cmplx_cmpl(pnob); | ||
| 1204 | be_disable_eq_intr(pnob); | ||
| 1205 | |||
| 1206 | if (adapter->tasklet_started) { | ||
| 1207 | tasklet_kill(&adapter->sts_handler); | ||
| 1208 | adapter->tasklet_started = 0; | ||
| 1209 | } | ||
| 1210 | |||
| 1211 | be_unregister_isr(adapter); | ||
| 1212 | be_disable_intr(pnob); | ||
| 1213 | |||
| 1214 | be_tx_q_clean(pnob); | ||
| 1215 | be_rx_q_clean(pnob); | ||
| 1216 | |||
| 1217 | be_destroy_netobj(pnob); | ||
| 1218 | } | ||
| 1219 | |||
| 1220 | static int be_suspend(struct pci_dev *pdev, pm_message_t state) | ||
| 1221 | { | ||
| 1222 | struct be_adapter *adapter = pci_get_drvdata(pdev); | ||
| 1223 | struct net_device *netdev = adapter->netdevp; | ||
| 1224 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 1225 | |||
| 1226 | adapter->dev_pm_state = adapter->dev_state; | ||
| 1227 | adapter->dev_state = BE_DEV_STATE_SUSPEND; | ||
| 1228 | |||
| 1229 | netif_device_detach(netdev); | ||
| 1230 | if (netif_running(netdev)) | ||
| 1231 | be_pm_cleanup(adapter, pnob, netdev); | ||
| 1232 | |||
| 1233 | pci_enable_wake(pdev, 3, 1); | ||
| 1234 | pci_enable_wake(pdev, 4, 1); /* D3 Cold = 4 */ | ||
| 1235 | pci_save_state(pdev); | ||
| 1236 | pci_disable_device(pdev); | ||
| 1237 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | ||
| 1238 | return 0; | ||
| 1239 | } | ||
| 1240 | |||
| 1241 | static void be_up(struct be_adapter *adapter) | ||
| 1242 | { | ||
| 1243 | struct be_net_object *pnob = adapter->net_obj; | ||
| 1244 | |||
| 1245 | if (pnob->num_vlans != 0) | ||
| 1246 | be_rxf_vlan_config(&pnob->fn_obj, false, pnob->num_vlans, | ||
| 1247 | pnob->vlan_tag, NULL, NULL, NULL); | ||
| 1248 | |||
| 1249 | } | ||
| 1250 | |||
| 1251 | static int be_resume(struct pci_dev *pdev) | ||
| 1252 | { | ||
| 1253 | int status = 0; | ||
| 1254 | struct be_adapter *adapter = pci_get_drvdata(pdev); | ||
| 1255 | struct net_device *netdev = adapter->netdevp; | ||
| 1256 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 1257 | |||
| 1258 | netif_device_detach(netdev); | ||
| 1259 | |||
| 1260 | status = pci_enable_device(pdev); | ||
| 1261 | if (status) | ||
| 1262 | return status; | ||
| 1263 | |||
| 1264 | pci_set_power_state(pdev, 0); | ||
| 1265 | pci_restore_state(pdev); | ||
| 1266 | pci_enable_wake(pdev, 3, 0); | ||
| 1267 | pci_enable_wake(pdev, 4, 0); /* 4 is D3 cold */ | ||
| 1268 | |||
| 1269 | netif_carrier_on(netdev); | ||
| 1270 | netif_start_queue(netdev); | ||
| 1271 | |||
| 1272 | if (netif_running(netdev)) { | ||
| 1273 | be_rxf_mac_address_read_write(&pnob->fn_obj, false, false, | ||
| 1274 | false, true, false, netdev->dev_addr, NULL, NULL); | ||
| 1275 | |||
| 1276 | status = be_nob_ring_init(adapter, pnob); | ||
| 1277 | if (status < 0) | ||
| 1278 | return status; | ||
| 1279 | |||
| 1280 | tasklet_init(&(adapter->sts_handler), be_process_intr, | ||
| 1281 | (unsigned long)adapter); | ||
| 1282 | adapter->tasklet_started = 1; | ||
| 1283 | |||
| 1284 | if (be_register_isr(adapter, pnob) != 0) { | ||
| 1285 | printk(KERN_ERR "be_register_isr failed\n"); | ||
| 1286 | return status; | ||
| 1287 | } | ||
| 1288 | |||
| 1289 | |||
| 1290 | status = be_mcc_init(adapter); | ||
| 1291 | if (status < 0) { | ||
| 1292 | printk(KERN_ERR "be_mcc_init failed\n"); | ||
| 1293 | return status; | ||
| 1294 | } | ||
| 1295 | be_update_link_status(adapter); | ||
| 1296 | /* | ||
| 1297 | * Register async call back function to handle link | ||
| 1298 | * status updates | ||
| 1299 | */ | ||
| 1300 | status = be_mcc_add_async_event_callback( | ||
| 1301 | &adapter->net_obj->mcc_q_obj, | ||
| 1302 | be_link_status_async_callback, (void *)adapter); | ||
| 1303 | if (status != BE_SUCCESS) { | ||
| 1304 | printk(KERN_WARNING "add_async_event_callback failed"); | ||
| 1305 | printk(KERN_WARNING | ||
| 1306 | "Link status changes may not be reflected\n"); | ||
| 1307 | } | ||
| 1308 | be_enable_intr(pnob); | ||
| 1309 | be_enable_eq_intr(pnob); | ||
| 1310 | be_up(adapter); | ||
| 1311 | } | ||
| 1312 | netif_device_attach(netdev); | ||
| 1313 | adapter->dev_state = adapter->dev_pm_state; | ||
| 1314 | return 0; | ||
| 1315 | |||
| 1316 | } | ||
| 1317 | |||
| 1318 | #endif | ||
| 1319 | |||
| 1320 | /* Wait until no more pending transmits */ | ||
| 1321 | void be_wait_nic_tx_cmplx_cmpl(struct be_net_object *pnob) | ||
| 1322 | { | ||
| 1323 | int i; | ||
| 1324 | |||
| 1325 | /* Wait for 20us * 50000 (= 1s) and no more */ | ||
| 1326 | i = 0; | ||
| 1327 | while ((pnob->tx_q_tl != pnob->tx_q_hd) && (i < 50000)) { | ||
| 1328 | ++i; | ||
| 1329 | udelay(20); | ||
| 1330 | } | ||
| 1331 | |||
| 1332 | /* Check for no more pending transmits */ | ||
| 1333 | if (i >= 50000) { | ||
| 1334 | printk(KERN_WARNING | ||
| 1335 | "Did not receive completions for all TX requests\n"); | ||
| 1336 | } | ||
| 1337 | } | ||
| 1338 | |||
| 1339 | static struct pci_driver be_driver = { | ||
| 1340 | .name = be_driver_name, | ||
| 1341 | .id_table = be_device_id_table, | ||
| 1342 | .probe = be_probe, | ||
| 1343 | #ifdef CONFIG_PM | ||
| 1344 | .suspend = be_suspend, | ||
| 1345 | .resume = be_resume, | ||
| 1346 | #endif | ||
| 1347 | .remove = be_remove | ||
| 1348 | }; | ||
| 1349 | |||
| 1350 | /* | ||
| 1351 | * Module init entry point. Registers our our device and return. | ||
| 1352 | * Our probe will be called if the device is found. | ||
| 1353 | */ | ||
| 1354 | static int __init be_init_module(void) | ||
| 1355 | { | ||
| 1356 | int ret; | ||
| 1357 | |||
| 1358 | if (rxbuf_size != 8192 && rxbuf_size != 4096 && rxbuf_size != 2048) { | ||
| 1359 | printk(KERN_WARNING | ||
| 1360 | "Unsupported receive buffer size (%d) requested\n", | ||
| 1361 | rxbuf_size); | ||
| 1362 | printk(KERN_WARNING | ||
| 1363 | "Must be 2048, 4096 or 8192. Defaulting to 2048\n"); | ||
| 1364 | rxbuf_size = 2048; | ||
| 1365 | } | ||
| 1366 | |||
| 1367 | ret = pci_register_driver(&be_driver); | ||
| 1368 | |||
| 1369 | return ret; | ||
| 1370 | } | ||
| 1371 | |||
| 1372 | module_init(be_init_module); | ||
| 1373 | |||
| 1374 | /* | ||
| 1375 | * be_exit_module - Driver Exit Cleanup Routine | ||
| 1376 | */ | ||
| 1377 | static void __exit be_exit_module(void) | ||
| 1378 | { | ||
| 1379 | pci_unregister_driver(&be_driver); | ||
| 1380 | } | ||
| 1381 | |||
| 1382 | module_exit(be_exit_module); | ||
diff --git a/drivers/staging/benet/be_int.c b/drivers/staging/benet/be_int.c deleted file mode 100644 index cba95d09a8b6..000000000000 --- a/drivers/staging/benet/be_int.c +++ /dev/null | |||
| @@ -1,863 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | #include <linux/if_vlan.h> | ||
| 18 | #include <linux/inet_lro.h> | ||
| 19 | |||
| 20 | #include "benet.h" | ||
| 21 | |||
| 22 | /* number of bytes of RX frame that are copied to skb->data */ | ||
| 23 | #define BE_HDR_LEN 64 | ||
| 24 | |||
| 25 | #define NETIF_RX(skb) netif_receive_skb(skb) | ||
| 26 | #define VLAN_ACCEL_RX(skb, pnob, vt) \ | ||
| 27 | vlan_hwaccel_rx(skb, pnob->vlan_grp, vt) | ||
| 28 | |||
| 29 | /* | ||
| 30 | This function notifies BladeEngine of the number of completion | ||
| 31 | entries processed from the specified completion queue by writing | ||
| 32 | the number of popped entries to the door bell. | ||
| 33 | |||
| 34 | pnob - Pointer to the NetObject structure | ||
| 35 | n - Number of completion entries processed | ||
| 36 | cq_id - Queue ID of the completion queue for which notification | ||
| 37 | is being done. | ||
| 38 | re_arm - 1 - rearm the completion ring to generate an event. | ||
| 39 | - 0 - dont rearm the completion ring to generate an event | ||
| 40 | */ | ||
| 41 | void be_notify_cmpl(struct be_net_object *pnob, int n, int cq_id, int re_arm) | ||
| 42 | { | ||
| 43 | struct CQ_DB_AMAP cqdb; | ||
| 44 | |||
| 45 | cqdb.dw[0] = 0; | ||
| 46 | AMAP_SET_BITS_PTR(CQ_DB, qid, &cqdb, cq_id); | ||
| 47 | AMAP_SET_BITS_PTR(CQ_DB, rearm, &cqdb, re_arm); | ||
| 48 | AMAP_SET_BITS_PTR(CQ_DB, num_popped, &cqdb, n); | ||
| 49 | PD_WRITE(&pnob->fn_obj, cq_db, cqdb.dw[0]); | ||
| 50 | } | ||
| 51 | |||
| 52 | /* | ||
| 53 | * adds additional receive frags indicated by BE starting from given | ||
| 54 | * frag index (fi) to specified skb's frag list | ||
| 55 | */ | ||
| 56 | static void | ||
| 57 | add_skb_frags(struct be_net_object *pnob, struct sk_buff *skb, | ||
| 58 | u32 nresid, u32 fi) | ||
| 59 | { | ||
| 60 | struct be_adapter *adapter = pnob->adapter; | ||
| 61 | u32 sk_frag_idx, n; | ||
| 62 | struct be_rx_page_info *rx_page_info; | ||
| 63 | u32 frag_sz = pnob->rx_buf_size; | ||
| 64 | |||
| 65 | sk_frag_idx = skb_shinfo(skb)->nr_frags; | ||
| 66 | while (nresid) { | ||
| 67 | index_inc(&fi, pnob->rx_q_len); | ||
| 68 | |||
| 69 | rx_page_info = (struct be_rx_page_info *)pnob->rx_ctxt[fi]; | ||
| 70 | pnob->rx_ctxt[fi] = NULL; | ||
| 71 | if ((rx_page_info->page_offset) || | ||
| 72 | (pnob->rx_pg_shared == false)) { | ||
| 73 | pci_unmap_page(adapter->pdev, | ||
| 74 | pci_unmap_addr(rx_page_info, bus), | ||
| 75 | frag_sz, PCI_DMA_FROMDEVICE); | ||
| 76 | } | ||
| 77 | |||
| 78 | n = min(nresid, frag_sz); | ||
| 79 | skb_shinfo(skb)->frags[sk_frag_idx].page = rx_page_info->page; | ||
| 80 | skb_shinfo(skb)->frags[sk_frag_idx].page_offset | ||
| 81 | = rx_page_info->page_offset; | ||
| 82 | skb_shinfo(skb)->frags[sk_frag_idx].size = n; | ||
| 83 | |||
| 84 | sk_frag_idx++; | ||
| 85 | skb->len += n; | ||
| 86 | skb->data_len += n; | ||
| 87 | skb_shinfo(skb)->nr_frags++; | ||
| 88 | nresid -= n; | ||
| 89 | |||
| 90 | memset(rx_page_info, 0, sizeof(struct be_rx_page_info)); | ||
| 91 | atomic_dec(&pnob->rx_q_posted); | ||
| 92 | } | ||
| 93 | } | ||
| 94 | |||
| 95 | /* | ||
| 96 | * This function processes incoming nic packets over various Rx queues. | ||
| 97 | * This function takes the adapter, the current Rx status descriptor | ||
| 98 | * entry and the Rx completion queue ID as argument. | ||
| 99 | */ | ||
| 100 | static inline int process_nic_rx_completion(struct be_net_object *pnob, | ||
| 101 | struct ETH_RX_COMPL_AMAP *rxcp) | ||
| 102 | { | ||
| 103 | struct be_adapter *adapter = pnob->adapter; | ||
| 104 | struct sk_buff *skb; | ||
| 105 | int udpcksm, tcpcksm; | ||
| 106 | int n; | ||
| 107 | u32 nresid, fi; | ||
| 108 | u32 frag_sz = pnob->rx_buf_size; | ||
| 109 | u8 *va; | ||
| 110 | struct be_rx_page_info *rx_page_info; | ||
| 111 | u32 numfrags, vtp, vtm, vlan_tag, pktsize; | ||
| 112 | |||
| 113 | fi = AMAP_GET_BITS_PTR(ETH_RX_COMPL, fragndx, rxcp); | ||
| 114 | BUG_ON(fi >= (int)pnob->rx_q_len); | ||
| 115 | BUG_ON(fi < 0); | ||
| 116 | |||
| 117 | rx_page_info = (struct be_rx_page_info *)pnob->rx_ctxt[fi]; | ||
| 118 | BUG_ON(!rx_page_info->page); | ||
| 119 | pnob->rx_ctxt[fi] = NULL; | ||
| 120 | |||
| 121 | /* | ||
| 122 | * If one page is used per fragment or if this is the second half of | ||
| 123 | * of the page, unmap the page here | ||
| 124 | */ | ||
| 125 | if ((rx_page_info->page_offset) || (pnob->rx_pg_shared == false)) { | ||
| 126 | pci_unmap_page(adapter->pdev, | ||
| 127 | pci_unmap_addr(rx_page_info, bus), frag_sz, | ||
| 128 | PCI_DMA_FROMDEVICE); | ||
| 129 | } | ||
| 130 | |||
| 131 | atomic_dec(&pnob->rx_q_posted); | ||
| 132 | udpcksm = AMAP_GET_BITS_PTR(ETH_RX_COMPL, udpcksm, rxcp); | ||
| 133 | tcpcksm = AMAP_GET_BITS_PTR(ETH_RX_COMPL, tcpcksm, rxcp); | ||
| 134 | pktsize = AMAP_GET_BITS_PTR(ETH_RX_COMPL, pktsize, rxcp); | ||
| 135 | /* | ||
| 136 | * get rid of RX flush completions first. | ||
| 137 | */ | ||
| 138 | if ((tcpcksm) && (udpcksm) && (pktsize == 32)) { | ||
| 139 | put_page(rx_page_info->page); | ||
| 140 | memset(rx_page_info, 0, sizeof(struct be_rx_page_info)); | ||
| 141 | return 0; | ||
| 142 | } | ||
| 143 | skb = netdev_alloc_skb(pnob->netdev, BE_HDR_LEN + NET_IP_ALIGN); | ||
| 144 | if (skb == NULL) { | ||
| 145 | dev_info(&pnob->netdev->dev, "alloc_skb() failed\n"); | ||
| 146 | put_page(rx_page_info->page); | ||
| 147 | memset(rx_page_info, 0, sizeof(struct be_rx_page_info)); | ||
| 148 | goto free_frags; | ||
| 149 | } | ||
| 150 | skb_reserve(skb, NET_IP_ALIGN); | ||
| 151 | |||
| 152 | skb->dev = pnob->netdev; | ||
| 153 | |||
| 154 | n = min(pktsize, frag_sz); | ||
| 155 | |||
| 156 | va = page_address(rx_page_info->page) + rx_page_info->page_offset; | ||
| 157 | prefetch(va); | ||
| 158 | |||
| 159 | skb->len = n; | ||
| 160 | skb->data_len = n; | ||
| 161 | if (n <= BE_HDR_LEN) { | ||
| 162 | memcpy(skb->data, va, n); | ||
| 163 | put_page(rx_page_info->page); | ||
| 164 | skb->data_len -= n; | ||
| 165 | skb->tail += n; | ||
| 166 | } else { | ||
| 167 | |||
| 168 | /* Setup the SKB with page buffer information */ | ||
| 169 | skb_shinfo(skb)->frags[0].page = rx_page_info->page; | ||
| 170 | skb_shinfo(skb)->nr_frags++; | ||
| 171 | |||
| 172 | /* Copy the header into the skb_data */ | ||
| 173 | memcpy(skb->data, va, BE_HDR_LEN); | ||
| 174 | skb_shinfo(skb)->frags[0].page_offset = | ||
| 175 | rx_page_info->page_offset + BE_HDR_LEN; | ||
| 176 | skb_shinfo(skb)->frags[0].size = n - BE_HDR_LEN; | ||
| 177 | skb->data_len -= BE_HDR_LEN; | ||
| 178 | skb->tail += BE_HDR_LEN; | ||
| 179 | } | ||
| 180 | memset(rx_page_info, 0, sizeof(struct be_rx_page_info)); | ||
| 181 | nresid = pktsize - n; | ||
| 182 | |||
| 183 | skb->protocol = eth_type_trans(skb, pnob->netdev); | ||
| 184 | |||
| 185 | if ((tcpcksm || udpcksm) && adapter->rx_csum) | ||
| 186 | skb->ip_summed = CHECKSUM_UNNECESSARY; | ||
| 187 | else | ||
| 188 | skb->ip_summed = CHECKSUM_NONE; | ||
| 189 | /* | ||
| 190 | * if we have more bytes left, the frame has been | ||
| 191 | * given to us in multiple fragments. This happens | ||
| 192 | * with Jumbo frames. Add the remaining fragments to | ||
| 193 | * skb->frags[] array. | ||
| 194 | */ | ||
| 195 | if (nresid) | ||
| 196 | add_skb_frags(pnob, skb, nresid, fi); | ||
| 197 | |||
| 198 | /* update the the true size of the skb. */ | ||
| 199 | skb->truesize = skb->len + sizeof(struct sk_buff); | ||
| 200 | |||
| 201 | /* | ||
| 202 | * If a 802.3 frame or 802.2 LLC frame | ||
| 203 | * (i.e) contains length field in MAC Hdr | ||
| 204 | * and frame len is greater than 64 bytes | ||
| 205 | */ | ||
| 206 | if (((skb->protocol == ntohs(ETH_P_802_2)) || | ||
| 207 | (skb->protocol == ntohs(ETH_P_802_3))) | ||
| 208 | && (pktsize > BE_HDR_LEN)) { | ||
| 209 | /* | ||
| 210 | * If the length given in Mac Hdr is less than frame size | ||
| 211 | * Erraneous frame, Drop it | ||
| 212 | */ | ||
| 213 | if ((ntohs(*(u16 *) (va + 12)) + ETH_HLEN) < pktsize) { | ||
| 214 | /* Increment Non Ether type II frames dropped */ | ||
| 215 | adapter->be_stat.bes_802_3_dropped_frames++; | ||
| 216 | |||
| 217 | kfree_skb(skb); | ||
| 218 | return 0; | ||
| 219 | } | ||
| 220 | /* | ||
| 221 | * else if the length given in Mac Hdr is greater than | ||
| 222 | * frame size, should not be seeing this sort of frames | ||
| 223 | * dump the pkt and pass to stack | ||
| 224 | */ | ||
| 225 | else if ((ntohs(*(u16 *) (va + 12)) + ETH_HLEN) > pktsize) { | ||
| 226 | /* Increment Non Ether type II frames malformed */ | ||
| 227 | adapter->be_stat.bes_802_3_malformed_frames++; | ||
| 228 | } | ||
| 229 | } | ||
| 230 | |||
| 231 | vtp = AMAP_GET_BITS_PTR(ETH_RX_COMPL, vtp, rxcp); | ||
| 232 | vtm = AMAP_GET_BITS_PTR(ETH_RX_COMPL, vtm, rxcp); | ||
| 233 | if (vtp && vtm) { | ||
| 234 | /* Vlan tag present in pkt and BE found | ||
| 235 | * that the tag matched an entry in VLAN table | ||
| 236 | */ | ||
| 237 | if (!pnob->vlan_grp || pnob->num_vlans == 0) { | ||
| 238 | /* But we have no VLANs configured. | ||
| 239 | * This should never happen. Drop the packet. | ||
| 240 | */ | ||
| 241 | dev_info(&pnob->netdev->dev, | ||
| 242 | "BladeEngine: Unexpected vlan tagged packet\n"); | ||
| 243 | kfree_skb(skb); | ||
| 244 | return 0; | ||
| 245 | } | ||
| 246 | /* pass the VLAN packet to stack */ | ||
| 247 | vlan_tag = AMAP_GET_BITS_PTR(ETH_RX_COMPL, vlan_tag, rxcp); | ||
| 248 | VLAN_ACCEL_RX(skb, pnob, be16_to_cpu(vlan_tag)); | ||
| 249 | |||
| 250 | } else { | ||
| 251 | NETIF_RX(skb); | ||
| 252 | } | ||
| 253 | return 0; | ||
| 254 | |||
| 255 | free_frags: | ||
| 256 | /* free all frags associated with the current rxcp */ | ||
| 257 | numfrags = AMAP_GET_BITS_PTR(ETH_RX_COMPL, numfrags, rxcp); | ||
| 258 | while (numfrags-- > 1) { | ||
| 259 | index_inc(&fi, pnob->rx_q_len); | ||
| 260 | |||
| 261 | rx_page_info = (struct be_rx_page_info *) | ||
| 262 | pnob->rx_ctxt[fi]; | ||
| 263 | pnob->rx_ctxt[fi] = (void *)NULL; | ||
| 264 | if (rx_page_info->page_offset || !pnob->rx_pg_shared) { | ||
| 265 | pci_unmap_page(adapter->pdev, | ||
| 266 | pci_unmap_addr(rx_page_info, bus), | ||
| 267 | frag_sz, PCI_DMA_FROMDEVICE); | ||
| 268 | } | ||
| 269 | |||
| 270 | put_page(rx_page_info->page); | ||
| 271 | memset(rx_page_info, 0, sizeof(struct be_rx_page_info)); | ||
| 272 | atomic_dec(&pnob->rx_q_posted); | ||
| 273 | } | ||
| 274 | return -ENOMEM; | ||
| 275 | } | ||
| 276 | |||
| 277 | static void process_nic_rx_completion_lro(struct be_net_object *pnob, | ||
| 278 | struct ETH_RX_COMPL_AMAP *rxcp) | ||
| 279 | { | ||
| 280 | struct be_adapter *adapter = pnob->adapter; | ||
| 281 | struct skb_frag_struct rx_frags[BE_MAX_FRAGS_PER_FRAME]; | ||
| 282 | unsigned int udpcksm, tcpcksm; | ||
| 283 | u32 numfrags, vlanf, vtm, vlan_tag, nresid; | ||
| 284 | u16 vlant; | ||
| 285 | unsigned int fi, idx, n; | ||
| 286 | struct be_rx_page_info *rx_page_info; | ||
| 287 | u32 frag_sz = pnob->rx_buf_size, pktsize; | ||
| 288 | bool rx_coal = (adapter->max_rx_coal <= 1) ? 0 : 1; | ||
| 289 | u8 err, *va; | ||
| 290 | __wsum csum = 0; | ||
| 291 | |||
| 292 | if (AMAP_GET_BITS_PTR(ETH_RX_COMPL, ipsec, rxcp)) { | ||
| 293 | /* Drop the pkt and move to the next completion. */ | ||
| 294 | adapter->be_stat.bes_rx_misc_pkts++; | ||
| 295 | return; | ||
| 296 | } | ||
| 297 | err = AMAP_GET_BITS_PTR(ETH_RX_COMPL, err, rxcp); | ||
| 298 | if (err || !rx_coal) { | ||
| 299 | /* We won't coalesce Rx pkts if the err bit set. | ||
| 300 | * take the path of normal completion processing */ | ||
| 301 | process_nic_rx_completion(pnob, rxcp); | ||
| 302 | return; | ||
| 303 | } | ||
| 304 | |||
| 305 | fi = AMAP_GET_BITS_PTR(ETH_RX_COMPL, fragndx, rxcp); | ||
| 306 | BUG_ON(fi >= (int)pnob->rx_q_len); | ||
| 307 | BUG_ON(fi < 0); | ||
| 308 | rx_page_info = (struct be_rx_page_info *)pnob->rx_ctxt[fi]; | ||
| 309 | BUG_ON(!rx_page_info->page); | ||
| 310 | pnob->rx_ctxt[fi] = (void *)NULL; | ||
| 311 | /* If one page is used per fragment or if this is the | ||
| 312 | * second half of the page, unmap the page here | ||
| 313 | */ | ||
| 314 | if (rx_page_info->page_offset || !pnob->rx_pg_shared) { | ||
| 315 | pci_unmap_page(adapter->pdev, | ||
| 316 | pci_unmap_addr(rx_page_info, bus), | ||
| 317 | frag_sz, PCI_DMA_FROMDEVICE); | ||
| 318 | } | ||
| 319 | |||
| 320 | numfrags = AMAP_GET_BITS_PTR(ETH_RX_COMPL, numfrags, rxcp); | ||
| 321 | udpcksm = AMAP_GET_BITS_PTR(ETH_RX_COMPL, udpcksm, rxcp); | ||
| 322 | tcpcksm = AMAP_GET_BITS_PTR(ETH_RX_COMPL, tcpcksm, rxcp); | ||
| 323 | vlan_tag = AMAP_GET_BITS_PTR(ETH_RX_COMPL, vlan_tag, rxcp); | ||
| 324 | vlant = be16_to_cpu(vlan_tag); | ||
| 325 | vlanf = AMAP_GET_BITS_PTR(ETH_RX_COMPL, vtp, rxcp); | ||
| 326 | vtm = AMAP_GET_BITS_PTR(ETH_RX_COMPL, vtm, rxcp); | ||
| 327 | pktsize = AMAP_GET_BITS_PTR(ETH_RX_COMPL, pktsize, rxcp); | ||
| 328 | |||
| 329 | atomic_dec(&pnob->rx_q_posted); | ||
| 330 | |||
| 331 | if (tcpcksm && udpcksm && pktsize == 32) { | ||
| 332 | /* flush completion entries */ | ||
| 333 | put_page(rx_page_info->page); | ||
| 334 | memset(rx_page_info, 0, sizeof(struct be_rx_page_info)); | ||
| 335 | return; | ||
| 336 | } | ||
| 337 | /* Only one of udpcksum and tcpcksum can be set */ | ||
| 338 | BUG_ON(udpcksm && tcpcksm); | ||
| 339 | |||
| 340 | /* jumbo frames could come in multiple fragments */ | ||
| 341 | BUG_ON(numfrags != ((pktsize + (frag_sz - 1)) / frag_sz)); | ||
| 342 | n = min(pktsize, frag_sz); | ||
| 343 | nresid = pktsize - n; /* will be useful for jumbo pkts */ | ||
| 344 | idx = 0; | ||
| 345 | |||
| 346 | va = page_address(rx_page_info->page) + rx_page_info->page_offset; | ||
| 347 | prefetch(va); | ||
| 348 | rx_frags[idx].page = rx_page_info->page; | ||
| 349 | rx_frags[idx].page_offset = (rx_page_info->page_offset); | ||
| 350 | rx_frags[idx].size = n; | ||
| 351 | memset(rx_page_info, 0, sizeof(struct be_rx_page_info)); | ||
| 352 | |||
| 353 | /* If we got multiple fragments, we have more data. */ | ||
| 354 | while (nresid) { | ||
| 355 | idx++; | ||
| 356 | index_inc(&fi, pnob->rx_q_len); | ||
| 357 | |||
| 358 | rx_page_info = (struct be_rx_page_info *)pnob->rx_ctxt[fi]; | ||
| 359 | pnob->rx_ctxt[fi] = (void *)NULL; | ||
| 360 | if (rx_page_info->page_offset || !pnob->rx_pg_shared) { | ||
| 361 | pci_unmap_page(adapter->pdev, | ||
| 362 | pci_unmap_addr(rx_page_info, bus), | ||
| 363 | frag_sz, PCI_DMA_FROMDEVICE); | ||
| 364 | } | ||
| 365 | |||
| 366 | n = min(nresid, frag_sz); | ||
| 367 | rx_frags[idx].page = rx_page_info->page; | ||
| 368 | rx_frags[idx].page_offset = (rx_page_info->page_offset); | ||
| 369 | rx_frags[idx].size = n; | ||
| 370 | |||
| 371 | nresid -= n; | ||
| 372 | memset(rx_page_info, 0, sizeof(struct be_rx_page_info)); | ||
| 373 | atomic_dec(&pnob->rx_q_posted); | ||
| 374 | } | ||
| 375 | |||
| 376 | if (likely(!(vlanf && vtm))) { | ||
| 377 | lro_receive_frags(&pnob->lro_mgr, rx_frags, | ||
| 378 | pktsize, pktsize, | ||
| 379 | (void *)(unsigned long)csum, csum); | ||
| 380 | } else { | ||
| 381 | /* Vlan tag present in pkt and BE found | ||
| 382 | * that the tag matched an entry in VLAN table | ||
| 383 | */ | ||
| 384 | if (unlikely(!pnob->vlan_grp || pnob->num_vlans == 0)) { | ||
| 385 | /* But we have no VLANs configured. | ||
| 386 | * This should never happen. Drop the packet. | ||
| 387 | */ | ||
| 388 | dev_info(&pnob->netdev->dev, | ||
| 389 | "BladeEngine: Unexpected vlan tagged packet\n"); | ||
| 390 | return; | ||
| 391 | } | ||
| 392 | /* pass the VLAN packet to stack */ | ||
| 393 | lro_vlan_hwaccel_receive_frags(&pnob->lro_mgr, | ||
| 394 | rx_frags, pktsize, pktsize, | ||
| 395 | pnob->vlan_grp, vlant, | ||
| 396 | (void *)(unsigned long)csum, | ||
| 397 | csum); | ||
| 398 | } | ||
| 399 | |||
| 400 | adapter->be_stat.bes_rx_coal++; | ||
| 401 | } | ||
| 402 | |||
| 403 | struct ETH_RX_COMPL_AMAP *be_get_rx_cmpl(struct be_net_object *pnob) | ||
| 404 | { | ||
| 405 | struct ETH_RX_COMPL_AMAP *rxcp = &pnob->rx_cq[pnob->rx_cq_tl]; | ||
| 406 | u32 valid, ct; | ||
| 407 | |||
| 408 | valid = AMAP_GET_BITS_PTR(ETH_RX_COMPL, valid, rxcp); | ||
| 409 | if (valid == 0) | ||
| 410 | return NULL; | ||
| 411 | |||
| 412 | ct = AMAP_GET_BITS_PTR(ETH_RX_COMPL, ct, rxcp); | ||
| 413 | if (ct != 0) { | ||
| 414 | /* Invalid chute #. treat as error */ | ||
| 415 | AMAP_SET_BITS_PTR(ETH_RX_COMPL, err, rxcp, 1); | ||
| 416 | } | ||
| 417 | |||
| 418 | be_adv_rxcq_tl(pnob); | ||
| 419 | AMAP_SET_BITS_PTR(ETH_RX_COMPL, valid, rxcp, 0); | ||
| 420 | return rxcp; | ||
| 421 | } | ||
| 422 | |||
| 423 | static void update_rx_rate(struct be_adapter *adapter) | ||
| 424 | { | ||
| 425 | /* update the rate once in two seconds */ | ||
| 426 | if ((jiffies - adapter->eth_rx_jiffies) > 2 * (HZ)) { | ||
| 427 | u32 r; | ||
| 428 | r = adapter->eth_rx_bytes / | ||
| 429 | ((jiffies - adapter->eth_rx_jiffies) / (HZ)); | ||
| 430 | r = (r / 1000000); /* MB/Sec */ | ||
| 431 | |||
| 432 | /* Mega Bits/Sec */ | ||
| 433 | adapter->be_stat.bes_eth_rx_rate = (r * 8); | ||
| 434 | adapter->eth_rx_jiffies = jiffies; | ||
| 435 | adapter->eth_rx_bytes = 0; | ||
| 436 | } | ||
| 437 | } | ||
| 438 | |||
| 439 | static int process_rx_completions(struct be_net_object *pnob, int max_work) | ||
| 440 | { | ||
| 441 | struct be_adapter *adapter = pnob->adapter; | ||
| 442 | struct ETH_RX_COMPL_AMAP *rxcp; | ||
| 443 | u32 nc = 0; | ||
| 444 | unsigned int pktsize; | ||
| 445 | |||
| 446 | while (max_work && (rxcp = be_get_rx_cmpl(pnob))) { | ||
| 447 | prefetch(rxcp); | ||
| 448 | pktsize = AMAP_GET_BITS_PTR(ETH_RX_COMPL, pktsize, rxcp); | ||
| 449 | process_nic_rx_completion_lro(pnob, rxcp); | ||
| 450 | adapter->eth_rx_bytes += pktsize; | ||
| 451 | update_rx_rate(adapter); | ||
| 452 | nc++; | ||
| 453 | max_work--; | ||
| 454 | adapter->be_stat.bes_rx_compl++; | ||
| 455 | } | ||
| 456 | if (likely(adapter->max_rx_coal > 1)) { | ||
| 457 | adapter->be_stat.bes_rx_flush++; | ||
| 458 | lro_flush_all(&pnob->lro_mgr); | ||
| 459 | } | ||
| 460 | |||
| 461 | /* Refill the queue */ | ||
| 462 | if (atomic_read(&pnob->rx_q_posted) < 900) | ||
| 463 | be_post_eth_rx_buffs(pnob); | ||
| 464 | |||
| 465 | return nc; | ||
| 466 | } | ||
| 467 | |||
| 468 | static struct ETH_TX_COMPL_AMAP *be_get_tx_cmpl(struct be_net_object *pnob) | ||
| 469 | { | ||
| 470 | struct ETH_TX_COMPL_AMAP *txcp = &pnob->tx_cq[pnob->tx_cq_tl]; | ||
| 471 | u32 valid; | ||
| 472 | |||
| 473 | valid = AMAP_GET_BITS_PTR(ETH_TX_COMPL, valid, txcp); | ||
| 474 | if (valid == 0) | ||
| 475 | return NULL; | ||
| 476 | |||
| 477 | AMAP_SET_BITS_PTR(ETH_TX_COMPL, valid, txcp, 0); | ||
| 478 | be_adv_txcq_tl(pnob); | ||
| 479 | return txcp; | ||
| 480 | |||
| 481 | } | ||
| 482 | |||
| 483 | void process_one_tx_compl(struct be_net_object *pnob, u32 end_idx) | ||
| 484 | { | ||
| 485 | struct be_adapter *adapter = pnob->adapter; | ||
| 486 | int cur_index, tx_wrbs_completed = 0; | ||
| 487 | struct sk_buff *skb; | ||
| 488 | u64 busaddr, pa, pa_lo, pa_hi; | ||
| 489 | struct ETH_WRB_AMAP *wrb; | ||
| 490 | u32 frag_len, last_index, j; | ||
| 491 | |||
| 492 | last_index = tx_compl_lastwrb_idx_get(pnob); | ||
| 493 | BUG_ON(last_index != end_idx); | ||
| 494 | pnob->tx_ctxt[pnob->tx_q_tl] = NULL; | ||
| 495 | do { | ||
| 496 | cur_index = pnob->tx_q_tl; | ||
| 497 | wrb = &pnob->tx_q[cur_index]; | ||
| 498 | pa_hi = AMAP_GET_BITS_PTR(ETH_WRB, frag_pa_hi, wrb); | ||
| 499 | pa_lo = AMAP_GET_BITS_PTR(ETH_WRB, frag_pa_lo, wrb); | ||
| 500 | frag_len = AMAP_GET_BITS_PTR(ETH_WRB, frag_len, wrb); | ||
| 501 | busaddr = (pa_hi << 32) | pa_lo; | ||
| 502 | if (busaddr != 0) { | ||
| 503 | pa = le64_to_cpu(busaddr); | ||
| 504 | pci_unmap_single(adapter->pdev, pa, | ||
| 505 | frag_len, PCI_DMA_TODEVICE); | ||
| 506 | } | ||
| 507 | if (cur_index == last_index) { | ||
| 508 | skb = (struct sk_buff *)pnob->tx_ctxt[cur_index]; | ||
| 509 | BUG_ON(!skb); | ||
| 510 | for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) { | ||
| 511 | struct skb_frag_struct *frag; | ||
| 512 | frag = &skb_shinfo(skb)->frags[j]; | ||
| 513 | pci_unmap_page(adapter->pdev, | ||
| 514 | (ulong) frag->page, frag->size, | ||
| 515 | PCI_DMA_TODEVICE); | ||
| 516 | } | ||
| 517 | kfree_skb(skb); | ||
| 518 | pnob->tx_ctxt[cur_index] = NULL; | ||
| 519 | } else { | ||
| 520 | BUG_ON(pnob->tx_ctxt[cur_index]); | ||
| 521 | } | ||
| 522 | tx_wrbs_completed++; | ||
| 523 | be_adv_txq_tl(pnob); | ||
| 524 | } while (cur_index != last_index); | ||
| 525 | atomic_sub(tx_wrbs_completed, &pnob->tx_q_used); | ||
| 526 | } | ||
| 527 | |||
| 528 | /* there is no need to take an SMP lock here since currently | ||
| 529 | * we have only one instance of the tasklet that does completion | ||
| 530 | * processing. | ||
| 531 | */ | ||
| 532 | static void process_nic_tx_completions(struct be_net_object *pnob) | ||
| 533 | { | ||
| 534 | struct be_adapter *adapter = pnob->adapter; | ||
| 535 | struct ETH_TX_COMPL_AMAP *txcp; | ||
| 536 | struct net_device *netdev = pnob->netdev; | ||
| 537 | u32 end_idx, num_processed = 0; | ||
| 538 | |||
| 539 | adapter->be_stat.bes_tx_events++; | ||
| 540 | |||
| 541 | while ((txcp = be_get_tx_cmpl(pnob))) { | ||
| 542 | end_idx = AMAP_GET_BITS_PTR(ETH_TX_COMPL, wrb_index, txcp); | ||
| 543 | process_one_tx_compl(pnob, end_idx); | ||
| 544 | num_processed++; | ||
| 545 | adapter->be_stat.bes_tx_compl++; | ||
| 546 | } | ||
| 547 | be_notify_cmpl(pnob, num_processed, pnob->tx_cq_id, 1); | ||
| 548 | /* | ||
| 549 | * We got Tx completions and have usable WRBs. | ||
| 550 | * If the netdev's queue has been stopped | ||
| 551 | * because we had run out of WRBs, wake it now. | ||
| 552 | */ | ||
| 553 | spin_lock(&adapter->txq_lock); | ||
| 554 | if (netif_queue_stopped(netdev) | ||
| 555 | && atomic_read(&pnob->tx_q_used) < pnob->tx_q_len / 2) { | ||
| 556 | netif_wake_queue(netdev); | ||
| 557 | } | ||
| 558 | spin_unlock(&adapter->txq_lock); | ||
| 559 | } | ||
| 560 | |||
| 561 | static u32 post_rx_buffs(struct be_net_object *pnob, struct list_head *rxbl) | ||
| 562 | { | ||
| 563 | u32 nposted = 0; | ||
| 564 | struct ETH_RX_D_AMAP *rxd = NULL; | ||
| 565 | struct be_recv_buffer *rxbp; | ||
| 566 | void **rx_ctxp; | ||
| 567 | struct RQ_DB_AMAP rqdb; | ||
| 568 | |||
| 569 | rx_ctxp = pnob->rx_ctxt; | ||
| 570 | |||
| 571 | while (!list_empty(rxbl) && | ||
| 572 | (rx_ctxp[pnob->rx_q_hd] == NULL) && nposted < 255) { | ||
| 573 | |||
| 574 | rxbp = list_first_entry(rxbl, struct be_recv_buffer, rxb_list); | ||
| 575 | list_del(&rxbp->rxb_list); | ||
| 576 | rxd = pnob->rx_q + pnob->rx_q_hd; | ||
| 577 | AMAP_SET_BITS_PTR(ETH_RX_D, fragpa_lo, rxd, rxbp->rxb_pa_lo); | ||
| 578 | AMAP_SET_BITS_PTR(ETH_RX_D, fragpa_hi, rxd, rxbp->rxb_pa_hi); | ||
| 579 | |||
| 580 | rx_ctxp[pnob->rx_q_hd] = rxbp->rxb_ctxt; | ||
| 581 | be_adv_rxq_hd(pnob); | ||
| 582 | nposted++; | ||
| 583 | } | ||
| 584 | |||
| 585 | if (nposted) { | ||
| 586 | /* Now press the door bell to notify BladeEngine. */ | ||
| 587 | rqdb.dw[0] = 0; | ||
| 588 | AMAP_SET_BITS_PTR(RQ_DB, numPosted, &rqdb, nposted); | ||
| 589 | AMAP_SET_BITS_PTR(RQ_DB, rq, &rqdb, pnob->rx_q_id); | ||
| 590 | PD_WRITE(&pnob->fn_obj, erx_rq_db, rqdb.dw[0]); | ||
| 591 | } | ||
| 592 | atomic_add(nposted, &pnob->rx_q_posted); | ||
| 593 | return nposted; | ||
| 594 | } | ||
| 595 | |||
| 596 | void be_post_eth_rx_buffs(struct be_net_object *pnob) | ||
| 597 | { | ||
| 598 | struct be_adapter *adapter = pnob->adapter; | ||
| 599 | u32 num_bufs, r; | ||
| 600 | u64 busaddr = 0, tmp_pa; | ||
| 601 | u32 max_bufs, pg_hd; | ||
| 602 | u32 frag_size; | ||
| 603 | struct be_recv_buffer *rxbp; | ||
| 604 | struct list_head rxbl; | ||
| 605 | struct be_rx_page_info *rx_page_info; | ||
| 606 | struct page *page = NULL; | ||
| 607 | u32 page_order = 0; | ||
| 608 | gfp_t alloc_flags = GFP_ATOMIC; | ||
| 609 | |||
| 610 | BUG_ON(!adapter); | ||
| 611 | |||
| 612 | max_bufs = 64; /* should be even # <= 255. */ | ||
| 613 | |||
| 614 | frag_size = pnob->rx_buf_size; | ||
| 615 | page_order = get_order(frag_size); | ||
| 616 | |||
| 617 | if (frag_size == 8192) | ||
| 618 | alloc_flags |= (gfp_t) __GFP_COMP; | ||
| 619 | /* | ||
| 620 | * Form a linked list of RECV_BUFFFER structure to be be posted. | ||
| 621 | * We will post even number of buffer so that pages can be | ||
| 622 | * shared. | ||
| 623 | */ | ||
| 624 | INIT_LIST_HEAD(&rxbl); | ||
| 625 | |||
| 626 | for (num_bufs = 0; num_bufs < max_bufs && | ||
| 627 | !pnob->rx_page_info[pnob->rx_pg_info_hd].page; ++num_bufs) { | ||
| 628 | |||
| 629 | rxbp = &pnob->eth_rx_bufs[num_bufs]; | ||
| 630 | pg_hd = pnob->rx_pg_info_hd; | ||
| 631 | rx_page_info = &pnob->rx_page_info[pg_hd]; | ||
| 632 | |||
| 633 | if (!page) { | ||
| 634 | page = alloc_pages(alloc_flags, page_order); | ||
| 635 | if (unlikely(page == NULL)) { | ||
| 636 | adapter->be_stat.bes_ethrx_post_fail++; | ||
| 637 | pnob->rxbuf_post_fail++; | ||
| 638 | break; | ||
| 639 | } | ||
| 640 | pnob->rxbuf_post_fail = 0; | ||
| 641 | busaddr = pci_map_page(adapter->pdev, page, 0, | ||
| 642 | frag_size, PCI_DMA_FROMDEVICE); | ||
| 643 | rx_page_info->page_offset = 0; | ||
| 644 | rx_page_info->page = page; | ||
| 645 | /* | ||
| 646 | * If we are sharing a page among two skbs, | ||
| 647 | * alloc a new one on the next iteration | ||
| 648 | */ | ||
| 649 | if (pnob->rx_pg_shared == false) | ||
| 650 | page = NULL; | ||
| 651 | } else { | ||
| 652 | get_page(page); | ||
| 653 | rx_page_info->page_offset += frag_size; | ||
| 654 | rx_page_info->page = page; | ||
| 655 | /* | ||
| 656 | * We are finished with the alloced page, | ||
| 657 | * Alloc a new one on the next iteration | ||
| 658 | */ | ||
| 659 | page = NULL; | ||
| 660 | } | ||
| 661 | rxbp->rxb_ctxt = (void *)rx_page_info; | ||
| 662 | index_inc(&pnob->rx_pg_info_hd, pnob->rx_q_len); | ||
| 663 | |||
| 664 | pci_unmap_addr_set(rx_page_info, bus, busaddr); | ||
| 665 | tmp_pa = busaddr + rx_page_info->page_offset; | ||
| 666 | rxbp->rxb_pa_lo = (tmp_pa & 0xFFFFFFFF); | ||
| 667 | rxbp->rxb_pa_hi = (tmp_pa >> 32); | ||
| 668 | rxbp->rxb_len = frag_size; | ||
| 669 | list_add_tail(&rxbp->rxb_list, &rxbl); | ||
| 670 | } /* End of for */ | ||
| 671 | |||
| 672 | r = post_rx_buffs(pnob, &rxbl); | ||
| 673 | BUG_ON(r != num_bufs); | ||
| 674 | return; | ||
| 675 | } | ||
| 676 | |||
| 677 | /* | ||
| 678 | * Interrupt service for network function. We just schedule the | ||
| 679 | * tasklet which does all completion processing. | ||
| 680 | */ | ||
| 681 | irqreturn_t be_int(int irq, void *dev) | ||
| 682 | { | ||
| 683 | struct net_device *netdev = dev; | ||
| 684 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 685 | struct be_adapter *adapter = pnob->adapter; | ||
| 686 | u32 isr; | ||
| 687 | |||
| 688 | isr = CSR_READ(&pnob->fn_obj, cev.isr1); | ||
| 689 | if (unlikely(!isr)) | ||
| 690 | return IRQ_NONE; | ||
| 691 | |||
| 692 | spin_lock(&adapter->int_lock); | ||
| 693 | adapter->isr |= isr; | ||
| 694 | spin_unlock(&adapter->int_lock); | ||
| 695 | |||
| 696 | adapter->be_stat.bes_ints++; | ||
| 697 | |||
| 698 | tasklet_schedule(&adapter->sts_handler); | ||
| 699 | return IRQ_HANDLED; | ||
| 700 | } | ||
| 701 | |||
| 702 | /* | ||
| 703 | * Poll function called by NAPI with a work budget. | ||
| 704 | * We process as many UC. BC and MC receive completions | ||
| 705 | * as the budget allows and return the actual number of | ||
| 706 | * RX ststutses processed. | ||
| 707 | */ | ||
| 708 | int be_poll(struct napi_struct *napi, int budget) | ||
| 709 | { | ||
| 710 | struct be_net_object *pnob = | ||
| 711 | container_of(napi, struct be_net_object, napi); | ||
| 712 | u32 work_done; | ||
| 713 | |||
| 714 | pnob->adapter->be_stat.bes_polls++; | ||
| 715 | work_done = process_rx_completions(pnob, budget); | ||
| 716 | BUG_ON(work_done > budget); | ||
| 717 | |||
| 718 | /* All consumed */ | ||
| 719 | if (work_done < budget) { | ||
| 720 | netif_rx_complete(napi); | ||
| 721 | /* enable intr */ | ||
| 722 | be_notify_cmpl(pnob, work_done, pnob->rx_cq_id, 1); | ||
| 723 | } else { | ||
| 724 | /* More to be consumed; continue with interrupts disabled */ | ||
| 725 | be_notify_cmpl(pnob, work_done, pnob->rx_cq_id, 0); | ||
| 726 | } | ||
| 727 | return work_done; | ||
| 728 | } | ||
| 729 | |||
| 730 | static struct EQ_ENTRY_AMAP *get_event(struct be_net_object *pnob) | ||
| 731 | { | ||
| 732 | struct EQ_ENTRY_AMAP *eqp = &(pnob->event_q[pnob->event_q_tl]); | ||
| 733 | if (!AMAP_GET_BITS_PTR(EQ_ENTRY, Valid, eqp)) | ||
| 734 | return NULL; | ||
| 735 | be_adv_eq_tl(pnob); | ||
| 736 | return eqp; | ||
| 737 | } | ||
| 738 | |||
| 739 | /* | ||
| 740 | * Processes all valid events in the event ring associated with given | ||
| 741 | * NetObject. Also, notifies BE the number of events processed. | ||
| 742 | */ | ||
| 743 | static inline u32 process_events(struct be_net_object *pnob) | ||
| 744 | { | ||
| 745 | struct be_adapter *adapter = pnob->adapter; | ||
| 746 | struct EQ_ENTRY_AMAP *eqp; | ||
| 747 | u32 rid, num_events = 0; | ||
| 748 | struct net_device *netdev = pnob->netdev; | ||
| 749 | |||
| 750 | while ((eqp = get_event(pnob)) != NULL) { | ||
| 751 | adapter->be_stat.bes_events++; | ||
| 752 | rid = AMAP_GET_BITS_PTR(EQ_ENTRY, ResourceID, eqp); | ||
| 753 | if (rid == pnob->rx_cq_id) { | ||
| 754 | adapter->be_stat.bes_rx_events++; | ||
| 755 | netif_rx_schedule(&pnob->napi); | ||
| 756 | } else if (rid == pnob->tx_cq_id) { | ||
| 757 | process_nic_tx_completions(pnob); | ||
| 758 | } else if (rid == pnob->mcc_cq_id) { | ||
| 759 | be_mcc_process_cq(&pnob->mcc_q_obj, 1); | ||
| 760 | } else { | ||
| 761 | dev_info(&netdev->dev, | ||
| 762 | "Invalid EQ ResourceID %d\n", rid); | ||
| 763 | } | ||
| 764 | AMAP_SET_BITS_PTR(EQ_ENTRY, Valid, eqp, 0); | ||
| 765 | AMAP_SET_BITS_PTR(EQ_ENTRY, ResourceID, eqp, 0); | ||
| 766 | num_events++; | ||
| 767 | } | ||
| 768 | return num_events; | ||
| 769 | } | ||
| 770 | |||
| 771 | static void update_eqd(struct be_adapter *adapter, struct be_net_object *pnob) | ||
| 772 | { | ||
| 773 | int status; | ||
| 774 | struct be_eq_object *eq_objectp; | ||
| 775 | |||
| 776 | /* update once a second */ | ||
| 777 | if ((jiffies - adapter->ips_jiffies) > 1 * (HZ)) { | ||
| 778 | /* One second elapsed since last update */ | ||
| 779 | u32 r, new_eqd = -1; | ||
| 780 | r = adapter->be_stat.bes_ints - adapter->be_stat.bes_prev_ints; | ||
| 781 | r = r / ((jiffies - adapter->ips_jiffies) / (HZ)); | ||
| 782 | adapter->be_stat.bes_ips = r; | ||
| 783 | adapter->ips_jiffies = jiffies; | ||
| 784 | adapter->be_stat.bes_prev_ints = adapter->be_stat.bes_ints; | ||
| 785 | if (r > IPS_HI_WM && adapter->cur_eqd < adapter->max_eqd) | ||
| 786 | new_eqd = (adapter->cur_eqd + 8); | ||
| 787 | if (r < IPS_LO_WM && adapter->cur_eqd > adapter->min_eqd) | ||
| 788 | new_eqd = (adapter->cur_eqd - 8); | ||
| 789 | if (adapter->enable_aic && new_eqd != -1) { | ||
| 790 | eq_objectp = &pnob->event_q_obj; | ||
| 791 | status = be_eq_modify_delay(&pnob->fn_obj, 1, | ||
| 792 | &eq_objectp, &new_eqd, NULL, | ||
| 793 | NULL, NULL); | ||
| 794 | if (status == BE_SUCCESS) | ||
| 795 | adapter->cur_eqd = new_eqd; | ||
| 796 | } | ||
| 797 | } | ||
| 798 | } | ||
| 799 | |||
| 800 | /* | ||
| 801 | This function notifies BladeEngine of how many events were processed | ||
| 802 | from the event queue by ringing the corresponding door bell and | ||
| 803 | optionally re-arms the event queue. | ||
| 804 | n - number of events processed | ||
| 805 | re_arm - 1 - re-arm the EQ, 0 - do not re-arm the EQ | ||
| 806 | |||
| 807 | */ | ||
| 808 | static void be_notify_event(struct be_net_object *pnob, int n, int re_arm) | ||
| 809 | { | ||
| 810 | struct CQ_DB_AMAP eqdb; | ||
| 811 | eqdb.dw[0] = 0; | ||
| 812 | |||
| 813 | AMAP_SET_BITS_PTR(CQ_DB, qid, &eqdb, pnob->event_q_id); | ||
| 814 | AMAP_SET_BITS_PTR(CQ_DB, rearm, &eqdb, re_arm); | ||
| 815 | AMAP_SET_BITS_PTR(CQ_DB, event, &eqdb, 1); | ||
| 816 | AMAP_SET_BITS_PTR(CQ_DB, num_popped, &eqdb, n); | ||
| 817 | /* | ||
| 818 | * Under some situations we see an interrupt and no valid | ||
| 819 | * EQ entry. To keep going, we need to ring the DB even if | ||
| 820 | * numPOsted is 0. | ||
| 821 | */ | ||
| 822 | PD_WRITE(&pnob->fn_obj, cq_db, eqdb.dw[0]); | ||
| 823 | return; | ||
| 824 | } | ||
| 825 | |||
| 826 | /* | ||
| 827 | * Called from the tasklet scheduled by ISR. All real interrupt processing | ||
| 828 | * is done here. | ||
| 829 | */ | ||
| 830 | void be_process_intr(unsigned long context) | ||
| 831 | { | ||
| 832 | struct be_adapter *adapter = (struct be_adapter *)context; | ||
| 833 | struct be_net_object *pnob = adapter->net_obj; | ||
| 834 | u32 isr, n; | ||
| 835 | ulong flags = 0; | ||
| 836 | |||
| 837 | isr = adapter->isr; | ||
| 838 | |||
| 839 | /* | ||
| 840 | * we create only one NIC event queue in Linux. Event is | ||
| 841 | * expected only in the first event queue | ||
| 842 | */ | ||
| 843 | BUG_ON(isr & 0xfffffffe); | ||
| 844 | if ((isr & 1) == 0) | ||
| 845 | return; /* not our interrupt */ | ||
| 846 | n = process_events(pnob); | ||
| 847 | /* | ||
| 848 | * Clear the event bit. adapter->isr is set by | ||
| 849 | * hard interrupt. Prevent race with lock. | ||
| 850 | */ | ||
| 851 | spin_lock_irqsave(&adapter->int_lock, flags); | ||
| 852 | adapter->isr &= ~1; | ||
| 853 | spin_unlock_irqrestore(&adapter->int_lock, flags); | ||
| 854 | be_notify_event(pnob, n, 1); | ||
| 855 | /* | ||
| 856 | * If previous allocation attempts had failed and | ||
| 857 | * BE has used up all posted buffers, post RX buffers here | ||
| 858 | */ | ||
| 859 | if (pnob->rxbuf_post_fail && atomic_read(&pnob->rx_q_posted) == 0) | ||
| 860 | be_post_eth_rx_buffs(pnob); | ||
| 861 | update_eqd(adapter, pnob); | ||
| 862 | return; | ||
| 863 | } | ||
diff --git a/drivers/staging/benet/be_netif.c b/drivers/staging/benet/be_netif.c deleted file mode 100644 index 2b8daf63dc7d..000000000000 --- a/drivers/staging/benet/be_netif.c +++ /dev/null | |||
| @@ -1,705 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * be_netif.c | ||
| 19 | * | ||
| 20 | * This file contains various entry points of drivers seen by tcp/ip stack. | ||
| 21 | */ | ||
| 22 | |||
| 23 | #include <linux/if_vlan.h> | ||
| 24 | #include <linux/in.h> | ||
| 25 | #include "benet.h" | ||
| 26 | #include <linux/ip.h> | ||
| 27 | #include <linux/inet_lro.h> | ||
| 28 | |||
| 29 | /* Strings to print Link properties */ | ||
| 30 | static const char *link_speed[] = { | ||
| 31 | "Invalid link Speed Value", | ||
| 32 | "10 Mbps", | ||
| 33 | "100 Mbps", | ||
| 34 | "1 Gbps", | ||
| 35 | "10 Gbps" | ||
| 36 | }; | ||
| 37 | |||
| 38 | static const char *link_duplex[] = { | ||
| 39 | "Invalid Duplex Value", | ||
| 40 | "Half Duplex", | ||
| 41 | "Full Duplex" | ||
| 42 | }; | ||
| 43 | |||
| 44 | static const char *link_state[] = { | ||
| 45 | "", | ||
| 46 | "(active)" | ||
| 47 | }; | ||
| 48 | |||
| 49 | void be_print_link_info(struct BE_LINK_STATUS *lnk_status) | ||
| 50 | { | ||
| 51 | u16 si, di, ai; | ||
| 52 | |||
| 53 | /* Port 0 */ | ||
| 54 | if (lnk_status->mac0_speed && lnk_status->mac0_duplex) { | ||
| 55 | /* Port is up and running */ | ||
| 56 | si = (lnk_status->mac0_speed < 5) ? lnk_status->mac0_speed : 0; | ||
| 57 | di = (lnk_status->mac0_duplex < 3) ? | ||
| 58 | lnk_status->mac0_duplex : 0; | ||
| 59 | ai = (lnk_status->active_port == 0) ? 1 : 0; | ||
| 60 | printk(KERN_INFO "PortNo. 0: Speed - %s %s %s\n", | ||
| 61 | link_speed[si], link_duplex[di], link_state[ai]); | ||
| 62 | } else | ||
| 63 | printk(KERN_INFO "PortNo. 0: Down\n"); | ||
| 64 | |||
| 65 | /* Port 1 */ | ||
| 66 | if (lnk_status->mac1_speed && lnk_status->mac1_duplex) { | ||
| 67 | /* Port is up and running */ | ||
| 68 | si = (lnk_status->mac1_speed < 5) ? lnk_status->mac1_speed : 0; | ||
| 69 | di = (lnk_status->mac1_duplex < 3) ? | ||
| 70 | lnk_status->mac1_duplex : 0; | ||
| 71 | ai = (lnk_status->active_port == 0) ? 1 : 0; | ||
| 72 | printk(KERN_INFO "PortNo. 1: Speed - %s %s %s\n", | ||
| 73 | link_speed[si], link_duplex[di], link_state[ai]); | ||
| 74 | } else | ||
| 75 | printk(KERN_INFO "PortNo. 1: Down\n"); | ||
| 76 | |||
| 77 | return; | ||
| 78 | } | ||
| 79 | |||
| 80 | static int | ||
| 81 | be_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr, | ||
| 82 | void **ip_hdr, void **tcpudp_hdr, | ||
| 83 | u64 *hdr_flags, void *priv) | ||
| 84 | { | ||
| 85 | struct ethhdr *eh; | ||
| 86 | struct vlan_ethhdr *veh; | ||
| 87 | struct iphdr *iph; | ||
| 88 | u8 *va = page_address(frag->page) + frag->page_offset; | ||
| 89 | unsigned long ll_hlen; | ||
| 90 | |||
| 91 | /* find the mac header, abort if not IPv4 */ | ||
| 92 | |||
| 93 | prefetch(va); | ||
| 94 | eh = (struct ethhdr *)va; | ||
| 95 | *mac_hdr = eh; | ||
| 96 | ll_hlen = ETH_HLEN; | ||
| 97 | if (eh->h_proto != htons(ETH_P_IP)) { | ||
| 98 | if (eh->h_proto == htons(ETH_P_8021Q)) { | ||
| 99 | veh = (struct vlan_ethhdr *)va; | ||
| 100 | if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP)) | ||
| 101 | return -1; | ||
| 102 | |||
| 103 | ll_hlen += VLAN_HLEN; | ||
| 104 | |||
| 105 | } else { | ||
| 106 | return -1; | ||
| 107 | } | ||
| 108 | } | ||
| 109 | *hdr_flags = LRO_IPV4; | ||
| 110 | |||
| 111 | iph = (struct iphdr *)(va + ll_hlen); | ||
| 112 | *ip_hdr = iph; | ||
| 113 | if (iph->protocol != IPPROTO_TCP) | ||
| 114 | return -1; | ||
| 115 | *hdr_flags |= LRO_TCP; | ||
| 116 | *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2); | ||
| 117 | |||
| 118 | return 0; | ||
| 119 | } | ||
| 120 | |||
| 121 | static int benet_open(struct net_device *netdev) | ||
| 122 | { | ||
| 123 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 124 | struct be_adapter *adapter = pnob->adapter; | ||
| 125 | struct net_lro_mgr *lro_mgr; | ||
| 126 | |||
| 127 | if (adapter->dev_state < BE_DEV_STATE_INIT) | ||
| 128 | return -EAGAIN; | ||
| 129 | |||
| 130 | lro_mgr = &pnob->lro_mgr; | ||
| 131 | lro_mgr->dev = netdev; | ||
| 132 | |||
| 133 | lro_mgr->features = LRO_F_NAPI; | ||
| 134 | lro_mgr->ip_summed = CHECKSUM_UNNECESSARY; | ||
| 135 | lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY; | ||
| 136 | lro_mgr->max_desc = BE_MAX_LRO_DESCRIPTORS; | ||
| 137 | lro_mgr->lro_arr = pnob->lro_desc; | ||
| 138 | lro_mgr->get_frag_header = be_get_frag_header; | ||
| 139 | lro_mgr->max_aggr = adapter->max_rx_coal; | ||
| 140 | lro_mgr->frag_align_pad = 2; | ||
| 141 | if (lro_mgr->max_aggr > MAX_SKB_FRAGS) | ||
| 142 | lro_mgr->max_aggr = MAX_SKB_FRAGS; | ||
| 143 | |||
| 144 | adapter->max_rx_coal = BE_LRO_MAX_PKTS; | ||
| 145 | |||
| 146 | be_update_link_status(adapter); | ||
| 147 | |||
| 148 | /* | ||
| 149 | * Set carrier on only if Physical Link up | ||
| 150 | * Either of the port link status up signifies this | ||
| 151 | */ | ||
| 152 | if ((adapter->port0_link_sts == BE_PORT_LINK_UP) || | ||
| 153 | (adapter->port1_link_sts == BE_PORT_LINK_UP)) { | ||
| 154 | netif_start_queue(netdev); | ||
| 155 | netif_carrier_on(netdev); | ||
| 156 | } | ||
| 157 | |||
| 158 | adapter->dev_state = BE_DEV_STATE_OPEN; | ||
| 159 | napi_enable(&pnob->napi); | ||
| 160 | be_enable_intr(pnob); | ||
| 161 | be_enable_eq_intr(pnob); | ||
| 162 | /* | ||
| 163 | * RX completion queue may be in dis-armed state. Arm it. | ||
| 164 | */ | ||
| 165 | be_notify_cmpl(pnob, 0, pnob->rx_cq_id, 1); | ||
| 166 | |||
| 167 | return 0; | ||
| 168 | } | ||
| 169 | |||
| 170 | static int benet_close(struct net_device *netdev) | ||
| 171 | { | ||
| 172 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 173 | struct be_adapter *adapter = pnob->adapter; | ||
| 174 | |||
| 175 | netif_stop_queue(netdev); | ||
| 176 | synchronize_irq(netdev->irq); | ||
| 177 | |||
| 178 | be_wait_nic_tx_cmplx_cmpl(pnob); | ||
| 179 | adapter->dev_state = BE_DEV_STATE_INIT; | ||
| 180 | netif_carrier_off(netdev); | ||
| 181 | |||
| 182 | adapter->port0_link_sts = BE_PORT_LINK_DOWN; | ||
| 183 | adapter->port1_link_sts = BE_PORT_LINK_DOWN; | ||
| 184 | be_disable_intr(pnob); | ||
| 185 | be_disable_eq_intr(pnob); | ||
| 186 | napi_disable(&pnob->napi); | ||
| 187 | |||
| 188 | return 0; | ||
| 189 | } | ||
| 190 | |||
| 191 | /* | ||
| 192 | * Setting a Mac Address for BE | ||
| 193 | * Takes netdev and a void pointer as arguments. | ||
| 194 | * The pointer holds the new addres to be used. | ||
| 195 | */ | ||
| 196 | static int benet_set_mac_addr(struct net_device *netdev, void *p) | ||
| 197 | { | ||
| 198 | struct sockaddr *addr = p; | ||
| 199 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 200 | |||
| 201 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | ||
| 202 | be_rxf_mac_address_read_write(&pnob->fn_obj, 0, 0, false, true, false, | ||
| 203 | netdev->dev_addr, NULL, NULL); | ||
| 204 | /* | ||
| 205 | * Since we are doing Active-Passive failover, both | ||
| 206 | * ports should have matching MAC addresses everytime. | ||
| 207 | */ | ||
| 208 | be_rxf_mac_address_read_write(&pnob->fn_obj, 1, 0, false, true, false, | ||
| 209 | netdev->dev_addr, NULL, NULL); | ||
| 210 | |||
| 211 | return 0; | ||
| 212 | } | ||
| 213 | |||
| 214 | void be_get_stats_timer_handler(unsigned long context) | ||
| 215 | { | ||
| 216 | struct be_timer_ctxt *ctxt = (struct be_timer_ctxt *)context; | ||
| 217 | |||
| 218 | if (atomic_read(&ctxt->get_stat_flag)) { | ||
| 219 | atomic_dec(&ctxt->get_stat_flag); | ||
| 220 | up((void *)ctxt->get_stat_sem_addr); | ||
| 221 | } | ||
| 222 | del_timer(&ctxt->get_stats_timer); | ||
| 223 | return; | ||
| 224 | } | ||
| 225 | |||
| 226 | void be_get_stat_cb(void *context, int status, | ||
| 227 | struct MCC_WRB_AMAP *optional_wrb) | ||
| 228 | { | ||
| 229 | struct be_timer_ctxt *ctxt = (struct be_timer_ctxt *)context; | ||
| 230 | /* | ||
| 231 | * just up the semaphore if the get_stat_flag | ||
| 232 | * reads 1. so that the waiter can continue. | ||
| 233 | * If it is 0, then it was handled by the timer handler. | ||
| 234 | */ | ||
| 235 | del_timer(&ctxt->get_stats_timer); | ||
| 236 | if (atomic_read(&ctxt->get_stat_flag)) { | ||
| 237 | atomic_dec(&ctxt->get_stat_flag); | ||
| 238 | up((void *)ctxt->get_stat_sem_addr); | ||
| 239 | } | ||
| 240 | } | ||
| 241 | |||
| 242 | struct net_device_stats *benet_get_stats(struct net_device *dev) | ||
| 243 | { | ||
| 244 | struct be_net_object *pnob = netdev_priv(dev); | ||
| 245 | struct be_adapter *adapter = pnob->adapter; | ||
| 246 | u64 pa; | ||
| 247 | struct be_timer_ctxt *ctxt = &adapter->timer_ctxt; | ||
| 248 | |||
| 249 | if (adapter->dev_state != BE_DEV_STATE_OPEN) { | ||
| 250 | /* Return previously read stats */ | ||
| 251 | return &(adapter->benet_stats); | ||
| 252 | } | ||
| 253 | /* Get Physical Addr */ | ||
| 254 | pa = pci_map_single(adapter->pdev, adapter->eth_statsp, | ||
| 255 | sizeof(struct FWCMD_ETH_GET_STATISTICS), | ||
| 256 | PCI_DMA_FROMDEVICE); | ||
| 257 | ctxt->get_stat_sem_addr = (unsigned long)&adapter->get_eth_stat_sem; | ||
| 258 | atomic_inc(&ctxt->get_stat_flag); | ||
| 259 | |||
| 260 | be_rxf_query_eth_statistics(&pnob->fn_obj, adapter->eth_statsp, | ||
| 261 | cpu_to_le64(pa), be_get_stat_cb, ctxt, | ||
| 262 | NULL); | ||
| 263 | |||
| 264 | ctxt->get_stats_timer.data = (unsigned long)ctxt; | ||
| 265 | mod_timer(&ctxt->get_stats_timer, (jiffies + (HZ * 2))); | ||
| 266 | down((void *)ctxt->get_stat_sem_addr); /* callback will unblock us */ | ||
| 267 | |||
| 268 | /* Adding port0 and port1 stats. */ | ||
| 269 | adapter->benet_stats.rx_packets = | ||
| 270 | adapter->eth_statsp->params.response.p0recvdtotalframes + | ||
| 271 | adapter->eth_statsp->params.response.p1recvdtotalframes; | ||
| 272 | adapter->benet_stats.tx_packets = | ||
| 273 | adapter->eth_statsp->params.response.p0xmitunicastframes + | ||
| 274 | adapter->eth_statsp->params.response.p1xmitunicastframes; | ||
| 275 | adapter->benet_stats.tx_bytes = | ||
| 276 | adapter->eth_statsp->params.response.p0xmitbyteslsd + | ||
| 277 | adapter->eth_statsp->params.response.p1xmitbyteslsd; | ||
| 278 | adapter->benet_stats.rx_errors = | ||
| 279 | adapter->eth_statsp->params.response.p0crcerrors + | ||
| 280 | adapter->eth_statsp->params.response.p1crcerrors; | ||
| 281 | adapter->benet_stats.rx_errors += | ||
| 282 | adapter->eth_statsp->params.response.p0alignmentsymerrs + | ||
| 283 | adapter->eth_statsp->params.response.p1alignmentsymerrs; | ||
| 284 | adapter->benet_stats.rx_errors += | ||
| 285 | adapter->eth_statsp->params.response.p0inrangelenerrors + | ||
| 286 | adapter->eth_statsp->params.response.p1inrangelenerrors; | ||
| 287 | adapter->benet_stats.rx_bytes = | ||
| 288 | adapter->eth_statsp->params.response.p0recvdtotalbytesLSD + | ||
| 289 | adapter->eth_statsp->params.response.p1recvdtotalbytesLSD; | ||
| 290 | adapter->benet_stats.rx_crc_errors = | ||
| 291 | adapter->eth_statsp->params.response.p0crcerrors + | ||
| 292 | adapter->eth_statsp->params.response.p1crcerrors; | ||
| 293 | |||
| 294 | adapter->benet_stats.tx_packets += | ||
| 295 | adapter->eth_statsp->params.response.p0xmitmulticastframes + | ||
| 296 | adapter->eth_statsp->params.response.p1xmitmulticastframes; | ||
| 297 | adapter->benet_stats.tx_packets += | ||
| 298 | adapter->eth_statsp->params.response.p0xmitbroadcastframes + | ||
| 299 | adapter->eth_statsp->params.response.p1xmitbroadcastframes; | ||
| 300 | adapter->benet_stats.tx_errors = 0; | ||
| 301 | |||
| 302 | adapter->benet_stats.multicast = | ||
| 303 | adapter->eth_statsp->params.response.p0xmitmulticastframes + | ||
| 304 | adapter->eth_statsp->params.response.p1xmitmulticastframes; | ||
| 305 | |||
| 306 | adapter->benet_stats.rx_fifo_errors = | ||
| 307 | adapter->eth_statsp->params.response.p0rxfifooverflowdropped + | ||
| 308 | adapter->eth_statsp->params.response.p1rxfifooverflowdropped; | ||
| 309 | adapter->benet_stats.rx_frame_errors = | ||
| 310 | adapter->eth_statsp->params.response.p0alignmentsymerrs + | ||
| 311 | adapter->eth_statsp->params.response.p1alignmentsymerrs; | ||
| 312 | adapter->benet_stats.rx_length_errors = | ||
| 313 | adapter->eth_statsp->params.response.p0inrangelenerrors + | ||
| 314 | adapter->eth_statsp->params.response.p1inrangelenerrors; | ||
| 315 | adapter->benet_stats.rx_length_errors += | ||
| 316 | adapter->eth_statsp->params.response.p0outrangeerrors + | ||
| 317 | adapter->eth_statsp->params.response.p1outrangeerrors; | ||
| 318 | adapter->benet_stats.rx_length_errors += | ||
| 319 | adapter->eth_statsp->params.response.p0frametoolongerrors + | ||
| 320 | adapter->eth_statsp->params.response.p1frametoolongerrors; | ||
| 321 | |||
| 322 | pci_unmap_single(adapter->pdev, (ulong) adapter->eth_statsp, | ||
| 323 | sizeof(struct FWCMD_ETH_GET_STATISTICS), | ||
| 324 | PCI_DMA_FROMDEVICE); | ||
| 325 | return &(adapter->benet_stats); | ||
| 326 | |||
| 327 | } | ||
| 328 | |||
| 329 | static void be_start_tx(struct be_net_object *pnob, u32 nposted) | ||
| 330 | { | ||
| 331 | #define CSR_ETH_MAX_SQPOSTS 255 | ||
| 332 | struct SQ_DB_AMAP sqdb; | ||
| 333 | |||
| 334 | sqdb.dw[0] = 0; | ||
| 335 | |||
| 336 | AMAP_SET_BITS_PTR(SQ_DB, cid, &sqdb, pnob->tx_q_id); | ||
| 337 | while (nposted) { | ||
| 338 | if (nposted > CSR_ETH_MAX_SQPOSTS) { | ||
| 339 | AMAP_SET_BITS_PTR(SQ_DB, numPosted, &sqdb, | ||
| 340 | CSR_ETH_MAX_SQPOSTS); | ||
| 341 | nposted -= CSR_ETH_MAX_SQPOSTS; | ||
| 342 | } else { | ||
| 343 | AMAP_SET_BITS_PTR(SQ_DB, numPosted, &sqdb, nposted); | ||
| 344 | nposted = 0; | ||
| 345 | } | ||
| 346 | PD_WRITE(&pnob->fn_obj, etx_sq_db, sqdb.dw[0]); | ||
| 347 | } | ||
| 348 | |||
| 349 | return; | ||
| 350 | } | ||
| 351 | |||
| 352 | static void update_tx_rate(struct be_adapter *adapter) | ||
| 353 | { | ||
| 354 | /* update the rate once in two seconds */ | ||
| 355 | if ((jiffies - adapter->eth_tx_jiffies) > 2 * (HZ)) { | ||
| 356 | u32 r; | ||
| 357 | r = adapter->eth_tx_bytes / | ||
| 358 | ((jiffies - adapter->eth_tx_jiffies) / (HZ)); | ||
| 359 | r = (r / 1000000); /* M bytes/s */ | ||
| 360 | adapter->be_stat.bes_eth_tx_rate = (r * 8); /* M bits/s */ | ||
| 361 | adapter->eth_tx_jiffies = jiffies; | ||
| 362 | adapter->eth_tx_bytes = 0; | ||
| 363 | } | ||
| 364 | } | ||
| 365 | |||
| 366 | static int wrb_cnt_in_skb(struct sk_buff *skb) | ||
| 367 | { | ||
| 368 | int cnt = 0; | ||
| 369 | while (skb) { | ||
| 370 | if (skb->len > skb->data_len) | ||
| 371 | cnt++; | ||
| 372 | cnt += skb_shinfo(skb)->nr_frags; | ||
| 373 | skb = skb_shinfo(skb)->frag_list; | ||
| 374 | } | ||
| 375 | BUG_ON(cnt > BE_MAX_TX_FRAG_COUNT); | ||
| 376 | return cnt; | ||
| 377 | } | ||
| 378 | |||
| 379 | static void wrb_fill(struct ETH_WRB_AMAP *wrb, u64 addr, int len) | ||
| 380 | { | ||
| 381 | AMAP_SET_BITS_PTR(ETH_WRB, frag_pa_hi, wrb, addr >> 32); | ||
| 382 | AMAP_SET_BITS_PTR(ETH_WRB, frag_pa_lo, wrb, addr & 0xFFFFFFFF); | ||
| 383 | AMAP_SET_BITS_PTR(ETH_WRB, frag_len, wrb, len); | ||
| 384 | } | ||
| 385 | |||
| 386 | static void wrb_fill_extra(struct ETH_WRB_AMAP *wrb, struct sk_buff *skb, | ||
| 387 | struct be_net_object *pnob) | ||
| 388 | { | ||
| 389 | wrb->dw[2] = 0; | ||
| 390 | wrb->dw[3] = 0; | ||
| 391 | AMAP_SET_BITS_PTR(ETH_WRB, crc, wrb, 1); | ||
| 392 | if (skb_shinfo(skb)->gso_segs > 1 && skb_shinfo(skb)->gso_size) { | ||
| 393 | AMAP_SET_BITS_PTR(ETH_WRB, lso, wrb, 1); | ||
| 394 | AMAP_SET_BITS_PTR(ETH_WRB, lso_mss, wrb, | ||
| 395 | skb_shinfo(skb)->gso_size); | ||
| 396 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | ||
| 397 | u8 proto = ((struct iphdr *)ip_hdr(skb))->protocol; | ||
| 398 | if (proto == IPPROTO_TCP) | ||
| 399 | AMAP_SET_BITS_PTR(ETH_WRB, tcpcs, wrb, 1); | ||
| 400 | else if (proto == IPPROTO_UDP) | ||
| 401 | AMAP_SET_BITS_PTR(ETH_WRB, udpcs, wrb, 1); | ||
| 402 | } | ||
| 403 | if (pnob->vlan_grp && vlan_tx_tag_present(skb)) { | ||
| 404 | AMAP_SET_BITS_PTR(ETH_WRB, vlan, wrb, 1); | ||
| 405 | AMAP_SET_BITS_PTR(ETH_WRB, vlan_tag, wrb, vlan_tx_tag_get(skb)); | ||
| 406 | } | ||
| 407 | } | ||
| 408 | |||
| 409 | static inline void wrb_copy_extra(struct ETH_WRB_AMAP *to, | ||
| 410 | struct ETH_WRB_AMAP *from) | ||
| 411 | { | ||
| 412 | |||
| 413 | to->dw[2] = from->dw[2]; | ||
| 414 | to->dw[3] = from->dw[3]; | ||
| 415 | } | ||
| 416 | |||
| 417 | /* Returns the actual count of wrbs used including a possible dummy */ | ||
| 418 | static int copy_skb_to_txq(struct be_net_object *pnob, struct sk_buff *skb, | ||
| 419 | u32 wrb_cnt, u32 *copied) | ||
| 420 | { | ||
| 421 | u64 busaddr; | ||
| 422 | struct ETH_WRB_AMAP *wrb = NULL, *first = NULL; | ||
| 423 | u32 i; | ||
| 424 | bool dummy = true; | ||
| 425 | struct pci_dev *pdev = pnob->adapter->pdev; | ||
| 426 | |||
| 427 | if (wrb_cnt & 1) | ||
| 428 | wrb_cnt++; | ||
| 429 | else | ||
| 430 | dummy = false; | ||
| 431 | |||
| 432 | atomic_add(wrb_cnt, &pnob->tx_q_used); | ||
| 433 | |||
| 434 | while (skb) { | ||
| 435 | if (skb->len > skb->data_len) { | ||
| 436 | int len = skb->len - skb->data_len; | ||
| 437 | busaddr = pci_map_single(pdev, skb->data, len, | ||
| 438 | PCI_DMA_TODEVICE); | ||
| 439 | busaddr = cpu_to_le64(busaddr); | ||
| 440 | wrb = &pnob->tx_q[pnob->tx_q_hd]; | ||
| 441 | if (first == NULL) { | ||
| 442 | wrb_fill_extra(wrb, skb, pnob); | ||
| 443 | first = wrb; | ||
| 444 | } else { | ||
| 445 | wrb_copy_extra(wrb, first); | ||
| 446 | } | ||
| 447 | wrb_fill(wrb, busaddr, len); | ||
| 448 | be_adv_txq_hd(pnob); | ||
| 449 | *copied += len; | ||
| 450 | } | ||
| 451 | |||
| 452 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | ||
| 453 | struct skb_frag_struct *frag = | ||
| 454 | &skb_shinfo(skb)->frags[i]; | ||
| 455 | busaddr = pci_map_page(pdev, frag->page, | ||
| 456 | frag->page_offset, frag->size, | ||
| 457 | PCI_DMA_TODEVICE); | ||
| 458 | busaddr = cpu_to_le64(busaddr); | ||
| 459 | wrb = &pnob->tx_q[pnob->tx_q_hd]; | ||
| 460 | if (first == NULL) { | ||
| 461 | wrb_fill_extra(wrb, skb, pnob); | ||
| 462 | first = wrb; | ||
| 463 | } else { | ||
| 464 | wrb_copy_extra(wrb, first); | ||
| 465 | } | ||
| 466 | wrb_fill(wrb, busaddr, frag->size); | ||
| 467 | be_adv_txq_hd(pnob); | ||
| 468 | *copied += frag->size; | ||
| 469 | } | ||
| 470 | skb = skb_shinfo(skb)->frag_list; | ||
| 471 | } | ||
| 472 | |||
| 473 | if (dummy) { | ||
| 474 | wrb = &pnob->tx_q[pnob->tx_q_hd]; | ||
| 475 | BUG_ON(first == NULL); | ||
| 476 | wrb_copy_extra(wrb, first); | ||
| 477 | wrb_fill(wrb, 0, 0); | ||
| 478 | be_adv_txq_hd(pnob); | ||
| 479 | } | ||
| 480 | AMAP_SET_BITS_PTR(ETH_WRB, complete, wrb, 1); | ||
| 481 | AMAP_SET_BITS_PTR(ETH_WRB, last, wrb, 1); | ||
| 482 | return wrb_cnt; | ||
| 483 | } | ||
| 484 | |||
| 485 | /* For each skb transmitted, tx_ctxt stores the num of wrbs in the | ||
| 486 | * start index and skb pointer in the end index | ||
| 487 | */ | ||
| 488 | static inline void be_tx_wrb_info_remember(struct be_net_object *pnob, | ||
| 489 | struct sk_buff *skb, int wrb_cnt, | ||
| 490 | u32 start) | ||
| 491 | { | ||
| 492 | *(u32 *) (&pnob->tx_ctxt[start]) = wrb_cnt; | ||
| 493 | index_adv(&start, wrb_cnt - 1, pnob->tx_q_len); | ||
| 494 | pnob->tx_ctxt[start] = skb; | ||
| 495 | } | ||
| 496 | |||
| 497 | static int benet_xmit(struct sk_buff *skb, struct net_device *netdev) | ||
| 498 | { | ||
| 499 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 500 | struct be_adapter *adapter = pnob->adapter; | ||
| 501 | u32 wrb_cnt, copied = 0; | ||
| 502 | u32 start = pnob->tx_q_hd; | ||
| 503 | |||
| 504 | adapter->be_stat.bes_tx_reqs++; | ||
| 505 | |||
| 506 | wrb_cnt = wrb_cnt_in_skb(skb); | ||
| 507 | spin_lock_bh(&adapter->txq_lock); | ||
| 508 | if ((pnob->tx_q_len - 2 - atomic_read(&pnob->tx_q_used)) <= wrb_cnt) { | ||
| 509 | netif_stop_queue(pnob->netdev); | ||
| 510 | spin_unlock_bh(&adapter->txq_lock); | ||
| 511 | adapter->be_stat.bes_tx_fails++; | ||
| 512 | return NETDEV_TX_BUSY; | ||
| 513 | } | ||
| 514 | spin_unlock_bh(&adapter->txq_lock); | ||
| 515 | |||
| 516 | wrb_cnt = copy_skb_to_txq(pnob, skb, wrb_cnt, &copied); | ||
| 517 | be_tx_wrb_info_remember(pnob, skb, wrb_cnt, start); | ||
| 518 | |||
| 519 | be_start_tx(pnob, wrb_cnt); | ||
| 520 | |||
| 521 | adapter->eth_tx_bytes += copied; | ||
| 522 | adapter->be_stat.bes_tx_wrbs += wrb_cnt; | ||
| 523 | update_tx_rate(adapter); | ||
| 524 | netdev->trans_start = jiffies; | ||
| 525 | |||
| 526 | return NETDEV_TX_OK; | ||
| 527 | } | ||
| 528 | |||
| 529 | /* | ||
| 530 | * This is the driver entry point to change the mtu of the device | ||
| 531 | * Returns 0 for success and errno for failure. | ||
| 532 | */ | ||
| 533 | static int benet_change_mtu(struct net_device *netdev, int new_mtu) | ||
| 534 | { | ||
| 535 | /* | ||
| 536 | * BE supports jumbo frame size upto 9000 bytes including the link layer | ||
| 537 | * header. Considering the different variants of frame formats possible | ||
| 538 | * like VLAN, SNAP/LLC, the maximum possible value for MTU is 8974 bytes | ||
| 539 | */ | ||
| 540 | |||
| 541 | if (new_mtu < (ETH_ZLEN + ETH_FCS_LEN) || (new_mtu > BE_MAX_MTU)) { | ||
| 542 | dev_info(&netdev->dev, "Invalid MTU requested. " | ||
| 543 | "Must be between %d and %d bytes\n", | ||
| 544 | (ETH_ZLEN + ETH_FCS_LEN), BE_MAX_MTU); | ||
| 545 | return -EINVAL; | ||
| 546 | } | ||
| 547 | dev_info(&netdev->dev, "MTU changed from %d to %d\n", | ||
| 548 | netdev->mtu, new_mtu); | ||
| 549 | netdev->mtu = new_mtu; | ||
| 550 | return 0; | ||
| 551 | } | ||
| 552 | |||
| 553 | /* | ||
| 554 | * This is the driver entry point to register a vlan with the device | ||
| 555 | */ | ||
| 556 | static void benet_vlan_register(struct net_device *netdev, | ||
| 557 | struct vlan_group *grp) | ||
| 558 | { | ||
| 559 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 560 | |||
| 561 | be_disable_eq_intr(pnob); | ||
| 562 | pnob->vlan_grp = grp; | ||
| 563 | pnob->num_vlans = 0; | ||
| 564 | be_enable_eq_intr(pnob); | ||
| 565 | } | ||
| 566 | |||
| 567 | /* | ||
| 568 | * This is the driver entry point to add a vlan vlan_id | ||
| 569 | * with the device netdev | ||
| 570 | */ | ||
| 571 | static void benet_vlan_add_vid(struct net_device *netdev, u16 vlan_id) | ||
| 572 | { | ||
| 573 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 574 | |||
| 575 | if (pnob->num_vlans == (BE_NUM_VLAN_SUPPORTED - 1)) { | ||
| 576 | /* no way to return an error */ | ||
| 577 | dev_info(&netdev->dev, | ||
| 578 | "BladeEngine: Cannot configure more than %d Vlans\n", | ||
| 579 | BE_NUM_VLAN_SUPPORTED); | ||
| 580 | return; | ||
| 581 | } | ||
| 582 | /* The new vlan tag will be in the slot indicated by num_vlans. */ | ||
| 583 | pnob->vlan_tag[pnob->num_vlans++] = vlan_id; | ||
| 584 | be_rxf_vlan_config(&pnob->fn_obj, false, pnob->num_vlans, | ||
| 585 | pnob->vlan_tag, NULL, NULL, NULL); | ||
| 586 | } | ||
| 587 | |||
| 588 | /* | ||
| 589 | * This is the driver entry point to remove a vlan vlan_id | ||
| 590 | * with the device netdev | ||
| 591 | */ | ||
| 592 | static void benet_vlan_rem_vid(struct net_device *netdev, u16 vlan_id) | ||
| 593 | { | ||
| 594 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 595 | |||
| 596 | u32 i, value; | ||
| 597 | |||
| 598 | /* | ||
| 599 | * In Blade Engine, we support 32 vlan tag filters across both ports. | ||
| 600 | * To program a vlan tag, the RXF_RTPR_CSR register is used. | ||
| 601 | * Each 32-bit value of RXF_RTDR_CSR can address 2 vlan tag entries. | ||
| 602 | * The Vlan table is of depth 16. thus we support 32 tags. | ||
| 603 | */ | ||
| 604 | |||
| 605 | value = vlan_id | VLAN_VALID_BIT; | ||
| 606 | for (i = 0; i < BE_NUM_VLAN_SUPPORTED; i++) { | ||
| 607 | if (pnob->vlan_tag[i] == vlan_id) | ||
| 608 | break; | ||
| 609 | } | ||
| 610 | |||
| 611 | if (i == BE_NUM_VLAN_SUPPORTED) | ||
| 612 | return; | ||
| 613 | /* Now compact the vlan tag array by removing hole created. */ | ||
| 614 | while ((i + 1) < BE_NUM_VLAN_SUPPORTED) { | ||
| 615 | pnob->vlan_tag[i] = pnob->vlan_tag[i + 1]; | ||
| 616 | i++; | ||
| 617 | } | ||
| 618 | if ((i + 1) == BE_NUM_VLAN_SUPPORTED) | ||
| 619 | pnob->vlan_tag[i] = (u16) 0x0; | ||
| 620 | pnob->num_vlans--; | ||
| 621 | be_rxf_vlan_config(&pnob->fn_obj, false, pnob->num_vlans, | ||
| 622 | pnob->vlan_tag, NULL, NULL, NULL); | ||
| 623 | } | ||
| 624 | |||
| 625 | /* | ||
| 626 | * This function is called to program multicast | ||
| 627 | * address in the multicast filter of the ASIC. | ||
| 628 | */ | ||
| 629 | static void be_set_multicast_filter(struct net_device *netdev) | ||
| 630 | { | ||
| 631 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 632 | struct dev_mc_list *mc_ptr; | ||
| 633 | u8 mac_addr[32][ETH_ALEN]; | ||
| 634 | int i; | ||
| 635 | |||
| 636 | if (netdev->flags & IFF_ALLMULTI) { | ||
| 637 | /* set BE in Multicast promiscuous */ | ||
| 638 | be_rxf_multicast_config(&pnob->fn_obj, true, 0, NULL, NULL, | ||
| 639 | NULL, NULL); | ||
| 640 | return; | ||
| 641 | } | ||
| 642 | |||
| 643 | for (mc_ptr = netdev->mc_list, i = 0; mc_ptr; | ||
| 644 | mc_ptr = mc_ptr->next, i++) { | ||
| 645 | memcpy(&mac_addr[i][0], mc_ptr->dmi_addr, ETH_ALEN); | ||
| 646 | } | ||
| 647 | |||
| 648 | /* reset the promiscuous mode also. */ | ||
| 649 | be_rxf_multicast_config(&pnob->fn_obj, false, i, | ||
| 650 | &mac_addr[0][0], NULL, NULL, NULL); | ||
| 651 | } | ||
| 652 | |||
| 653 | /* | ||
| 654 | * This is the driver entry point to set multicast list | ||
| 655 | * with the device netdev. This function will be used to | ||
| 656 | * set promiscuous mode or multicast promiscuous mode | ||
| 657 | * or multicast mode.... | ||
| 658 | */ | ||
| 659 | static void benet_set_multicast_list(struct net_device *netdev) | ||
| 660 | { | ||
| 661 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 662 | |||
| 663 | if (netdev->flags & IFF_PROMISC) { | ||
| 664 | be_rxf_promiscuous(&pnob->fn_obj, 1, 1, NULL, NULL, NULL); | ||
| 665 | } else { | ||
| 666 | be_rxf_promiscuous(&pnob->fn_obj, 0, 0, NULL, NULL, NULL); | ||
| 667 | be_set_multicast_filter(netdev); | ||
| 668 | } | ||
| 669 | } | ||
| 670 | |||
| 671 | int benet_init(struct net_device *netdev) | ||
| 672 | { | ||
| 673 | struct be_net_object *pnob = netdev_priv(netdev); | ||
| 674 | struct be_adapter *adapter = pnob->adapter; | ||
| 675 | |||
| 676 | ether_setup(netdev); | ||
| 677 | |||
| 678 | netdev->open = &benet_open; | ||
| 679 | netdev->stop = &benet_close; | ||
| 680 | netdev->hard_start_xmit = &benet_xmit; | ||
| 681 | |||
| 682 | netdev->get_stats = &benet_get_stats; | ||
| 683 | |||
| 684 | netdev->set_multicast_list = &benet_set_multicast_list; | ||
| 685 | |||
| 686 | netdev->change_mtu = &benet_change_mtu; | ||
| 687 | netdev->set_mac_address = &benet_set_mac_addr; | ||
| 688 | |||
| 689 | netdev->vlan_rx_register = benet_vlan_register; | ||
| 690 | netdev->vlan_rx_add_vid = benet_vlan_add_vid; | ||
| 691 | netdev->vlan_rx_kill_vid = benet_vlan_rem_vid; | ||
| 692 | |||
| 693 | netdev->features = | ||
| 694 | NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_HW_VLAN_RX | NETIF_F_TSO | | ||
| 695 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_FILTER | NETIF_F_IP_CSUM; | ||
| 696 | |||
| 697 | netdev->flags |= IFF_MULTICAST; | ||
| 698 | |||
| 699 | /* If device is DAC Capable, set the HIGHDMA flag for netdevice. */ | ||
| 700 | if (adapter->dma_64bit_cap) | ||
| 701 | netdev->features |= NETIF_F_HIGHDMA; | ||
| 702 | |||
| 703 | SET_ETHTOOL_OPS(netdev, &be_ethtool_ops); | ||
| 704 | return 0; | ||
| 705 | } | ||
diff --git a/drivers/staging/benet/benet.h b/drivers/staging/benet/benet.h deleted file mode 100644 index 09a1f0817722..000000000000 --- a/drivers/staging/benet/benet.h +++ /dev/null | |||
| @@ -1,429 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | #ifndef _BENET_H_ | ||
| 18 | #define _BENET_H_ | ||
| 19 | |||
| 20 | #include <linux/pci.h> | ||
| 21 | #include <linux/netdevice.h> | ||
| 22 | #include <linux/inet_lro.h> | ||
| 23 | #include "hwlib.h" | ||
| 24 | |||
| 25 | #define _SA_MODULE_NAME "net-driver" | ||
| 26 | |||
| 27 | #define VLAN_VALID_BIT 0x8000 | ||
| 28 | #define BE_NUM_VLAN_SUPPORTED 32 | ||
| 29 | #define BE_PORT_LINK_DOWN 0000 | ||
| 30 | #define BE_PORT_LINK_UP 0001 | ||
| 31 | #define BE_MAX_TX_FRAG_COUNT (30) | ||
| 32 | |||
| 33 | /* Flag bits for send operation */ | ||
| 34 | #define IPCS (1 << 0) /* Enable IP checksum offload */ | ||
| 35 | #define UDPCS (1 << 1) /* Enable UDP checksum offload */ | ||
| 36 | #define TCPCS (1 << 2) /* Enable TCP checksum offload */ | ||
| 37 | #define LSO (1 << 3) /* Enable Large Segment offload */ | ||
| 38 | #define ETHVLAN (1 << 4) /* Enable VLAN insert */ | ||
| 39 | #define ETHEVENT (1 << 5) /* Generate event on completion */ | ||
| 40 | #define ETHCOMPLETE (1 << 6) /* Generate completion when done */ | ||
| 41 | #define IPSEC (1 << 7) /* Enable IPSEC */ | ||
| 42 | #define FORWARD (1 << 8) /* Send the packet in forwarding path */ | ||
| 43 | #define FIN (1 << 9) /* Issue FIN segment */ | ||
| 44 | |||
| 45 | #define BE_MAX_MTU 8974 | ||
| 46 | |||
| 47 | #define BE_MAX_LRO_DESCRIPTORS 8 | ||
| 48 | #define BE_LRO_MAX_PKTS 64 | ||
| 49 | #define BE_MAX_FRAGS_PER_FRAME 6 | ||
| 50 | |||
| 51 | extern const char be_drvr_ver[]; | ||
| 52 | extern char be_fw_ver[]; | ||
| 53 | extern char be_driver_name[]; | ||
| 54 | |||
| 55 | extern struct ethtool_ops be_ethtool_ops; | ||
| 56 | |||
| 57 | #define BE_DEV_STATE_NONE 0 | ||
| 58 | #define BE_DEV_STATE_INIT 1 | ||
| 59 | #define BE_DEV_STATE_OPEN 2 | ||
| 60 | #define BE_DEV_STATE_SUSPEND 3 | ||
| 61 | |||
| 62 | /* This structure is used to describe physical fragments to use | ||
| 63 | * for DMAing data from NIC. | ||
| 64 | */ | ||
| 65 | struct be_recv_buffer { | ||
| 66 | struct list_head rxb_list; /* for maintaining a linked list */ | ||
| 67 | void *rxb_va; /* buffer virtual address */ | ||
| 68 | u32 rxb_pa_lo; /* low part of physical address */ | ||
| 69 | u32 rxb_pa_hi; /* high part of physical address */ | ||
| 70 | u32 rxb_len; /* length of recv buffer */ | ||
| 71 | void *rxb_ctxt; /* context for OSM driver to use */ | ||
| 72 | }; | ||
| 73 | |||
| 74 | /* | ||
| 75 | * fragment list to describe scattered data. | ||
| 76 | */ | ||
| 77 | struct be_tx_frag_list { | ||
| 78 | u32 txb_len; /* Size of this fragment */ | ||
| 79 | u32 txb_pa_lo; /* Lower 32 bits of 64 bit physical addr */ | ||
| 80 | u32 txb_pa_hi; /* Higher 32 bits of 64 bit physical addr */ | ||
| 81 | }; | ||
| 82 | |||
| 83 | struct be_rx_page_info { | ||
| 84 | struct page *page; | ||
| 85 | dma_addr_t bus; | ||
| 86 | u16 page_offset; | ||
| 87 | }; | ||
| 88 | |||
| 89 | /* | ||
| 90 | * This structure is the main tracking structure for a NIC interface. | ||
| 91 | */ | ||
| 92 | struct be_net_object { | ||
| 93 | /* MCC Ring - used to send fwcmds to embedded ARM processor */ | ||
| 94 | struct MCC_WRB_AMAP *mcc_q; /* VA of the start of the ring */ | ||
| 95 | u32 mcc_q_len; /* # of WRB entries in this ring */ | ||
| 96 | u32 mcc_q_size; | ||
| 97 | u32 mcc_q_hd; /* MCC ring head */ | ||
| 98 | u8 mcc_q_created; /* flag to help cleanup */ | ||
| 99 | struct be_mcc_object mcc_q_obj; /* BECLIB's MCC ring Object */ | ||
| 100 | dma_addr_t mcc_q_bus; /* DMA'ble bus address */ | ||
| 101 | |||
| 102 | /* MCC Completion Ring - FW responses to fwcmds sent from MCC ring */ | ||
| 103 | struct MCC_CQ_ENTRY_AMAP *mcc_cq; /* VA of the start of the ring */ | ||
| 104 | u32 mcc_cq_len; /* # of compl. entries in this ring */ | ||
| 105 | u32 mcc_cq_size; | ||
| 106 | u32 mcc_cq_tl; /* compl. ring tail */ | ||
| 107 | u8 mcc_cq_created; /* flag to help cleanup */ | ||
| 108 | struct be_cq_object mcc_cq_obj; /* BECLIB's MCC compl. ring object */ | ||
| 109 | u32 mcc_cq_id; /* MCC ring ID */ | ||
| 110 | dma_addr_t mcc_cq_bus; /* DMA'ble bus address */ | ||
| 111 | |||
| 112 | struct ring_desc mb_rd; /* RD for MCC_MAIL_BOX */ | ||
| 113 | void *mb_ptr; /* mailbox ptr to be freed */ | ||
| 114 | dma_addr_t mb_bus; /* DMA'ble bus address */ | ||
| 115 | u32 mb_size; | ||
| 116 | |||
| 117 | /* BEClib uses an array of context objects to track outstanding | ||
| 118 | * requests to the MCC. We need allocate the same number of | ||
| 119 | * conext entries as the number of entries in the MCC WRB ring | ||
| 120 | */ | ||
| 121 | u32 mcc_wrb_ctxt_size; | ||
| 122 | void *mcc_wrb_ctxt; /* pointer to the context area */ | ||
| 123 | u32 mcc_wrb_ctxtLen; /* Number of entries in the context */ | ||
| 124 | /* | ||
| 125 | * NIC send request ring - used for xmitting raw ether frames. | ||
| 126 | */ | ||
| 127 | struct ETH_WRB_AMAP *tx_q; /* VA of the start of the ring */ | ||
| 128 | u32 tx_q_len; /* # if entries in the send ring */ | ||
| 129 | u32 tx_q_size; | ||
| 130 | u32 tx_q_hd; /* Head index. Next req. goes here */ | ||
| 131 | u32 tx_q_tl; /* Tail indx. oldest outstanding req. */ | ||
| 132 | u8 tx_q_created; /* flag to help cleanup */ | ||
| 133 | struct be_ethsq_object tx_q_obj;/* BECLIB's send Q handle */ | ||
| 134 | dma_addr_t tx_q_bus; /* DMA'ble bus address */ | ||
| 135 | u32 tx_q_id; /* send queue ring ID */ | ||
| 136 | u32 tx_q_port; /* 0 no binding, 1 port A, 2 port B */ | ||
| 137 | atomic_t tx_q_used; /* # of WRBs used */ | ||
| 138 | /* ptr to an array in which we store context info for each send req. */ | ||
| 139 | void **tx_ctxt; | ||
| 140 | /* | ||
| 141 | * NIC Send compl. ring - completion status for all NIC frames xmitted. | ||
| 142 | */ | ||
| 143 | struct ETH_TX_COMPL_AMAP *tx_cq;/* VA of start of the ring */ | ||
| 144 | u32 txcq_len; /* # of entries in the ring */ | ||
| 145 | u32 tx_cq_size; | ||
| 146 | /* | ||
| 147 | * index into compl ring where the host expects next completion entry | ||
| 148 | */ | ||
| 149 | u32 tx_cq_tl; | ||
| 150 | u32 tx_cq_id; /* completion queue id */ | ||
| 151 | u8 tx_cq_created; /* flag to help cleanup */ | ||
| 152 | struct be_cq_object tx_cq_obj; | ||
| 153 | dma_addr_t tx_cq_bus; /* DMA'ble bus address */ | ||
| 154 | /* | ||
| 155 | * Event Queue - all completion entries post events here. | ||
| 156 | */ | ||
| 157 | struct EQ_ENTRY_AMAP *event_q; /* VA of start of event queue */ | ||
| 158 | u32 event_q_len; /* # of entries */ | ||
| 159 | u32 event_q_size; | ||
| 160 | u32 event_q_tl; /* Tail of the event queue */ | ||
| 161 | u32 event_q_id; /* Event queue ID */ | ||
| 162 | u8 event_q_created; /* flag to help cleanup */ | ||
| 163 | struct be_eq_object event_q_obj; /* Queue handle */ | ||
| 164 | dma_addr_t event_q_bus; /* DMA'ble bus address */ | ||
| 165 | /* | ||
| 166 | * NIC receive queue - Data buffers to be used for receiving unicast, | ||
| 167 | * broadcast and multi-cast frames are posted here. | ||
| 168 | */ | ||
| 169 | struct ETH_RX_D_AMAP *rx_q; /* VA of start of the queue */ | ||
| 170 | u32 rx_q_len; /* # of entries */ | ||
| 171 | u32 rx_q_size; | ||
| 172 | u32 rx_q_hd; /* Head of the queue */ | ||
| 173 | atomic_t rx_q_posted; /* number of posted buffers */ | ||
| 174 | u32 rx_q_id; /* queue ID */ | ||
| 175 | u8 rx_q_created; /* flag to help cleanup */ | ||
| 176 | struct be_ethrq_object rx_q_obj; /* NIC RX queue handle */ | ||
| 177 | dma_addr_t rx_q_bus; /* DMA'ble bus address */ | ||
| 178 | /* | ||
| 179 | * Pointer to an array of opaque context object for use by OSM driver | ||
| 180 | */ | ||
| 181 | void **rx_ctxt; | ||
| 182 | /* | ||
| 183 | * NIC unicast RX completion queue - all unicast ether frame completion | ||
| 184 | * statuses from BE come here. | ||
| 185 | */ | ||
| 186 | struct ETH_RX_COMPL_AMAP *rx_cq; /* VA of start of the queue */ | ||
| 187 | u32 rx_cq_len; /* # of entries */ | ||
| 188 | u32 rx_cq_size; | ||
| 189 | u32 rx_cq_tl; /* Tail of the queue */ | ||
| 190 | u32 rx_cq_id; /* queue ID */ | ||
| 191 | u8 rx_cq_created; /* flag to help cleanup */ | ||
| 192 | struct be_cq_object rx_cq_obj; /* queue handle */ | ||
| 193 | dma_addr_t rx_cq_bus; /* DMA'ble bus address */ | ||
| 194 | struct be_function_object fn_obj; /* function object */ | ||
| 195 | bool fn_obj_created; | ||
| 196 | u32 rx_buf_size; /* Size of the RX buffers */ | ||
| 197 | |||
| 198 | struct net_device *netdev; | ||
| 199 | struct be_recv_buffer eth_rx_bufs[256]; /* to pass Rx buffer | ||
| 200 | addresses */ | ||
| 201 | struct be_adapter *adapter; /* Pointer to OSM adapter */ | ||
| 202 | u32 devno; /* OSM, network dev no. */ | ||
| 203 | u32 use_port; /* Current active port */ | ||
| 204 | struct be_rx_page_info *rx_page_info; /* Array of Rx buf pages */ | ||
| 205 | u32 rx_pg_info_hd; /* Head of queue */ | ||
| 206 | int rxbuf_post_fail; /* RxBuff posting fail count */ | ||
| 207 | bool rx_pg_shared; /* Is an allocsted page shared as two frags ? */ | ||
| 208 | struct vlan_group *vlan_grp; | ||
| 209 | u32 num_vlans; /* Number of vlans in BE's filter */ | ||
| 210 | u16 vlan_tag[BE_NUM_VLAN_SUPPORTED]; /* vlans currently configured */ | ||
| 211 | struct napi_struct napi; | ||
| 212 | struct net_lro_mgr lro_mgr; | ||
| 213 | struct net_lro_desc lro_desc[BE_MAX_LRO_DESCRIPTORS]; | ||
| 214 | }; | ||
| 215 | |||
| 216 | #define NET_FH(np) (&(np)->fn_obj) | ||
| 217 | |||
| 218 | /* | ||
| 219 | * BE driver statistics. | ||
| 220 | */ | ||
| 221 | struct be_drvr_stat { | ||
| 222 | u32 bes_tx_reqs; /* number of TX requests initiated */ | ||
| 223 | u32 bes_tx_fails; /* number of TX requests that failed */ | ||
| 224 | u32 bes_fwd_reqs; /* number of send reqs through forwarding i/f */ | ||
| 225 | u32 bes_tx_wrbs; /* number of tx WRBs used */ | ||
| 226 | |||
| 227 | u32 bes_ints; /* number of interrupts */ | ||
| 228 | u32 bes_polls; /* number of times NAPI called poll function */ | ||
| 229 | u32 bes_events; /* total evet entries processed */ | ||
| 230 | u32 bes_tx_events; /* number of tx completion events */ | ||
| 231 | u32 bes_rx_events; /* number of ucast rx completion events */ | ||
| 232 | u32 bes_tx_compl; /* number of tx completion entries processed */ | ||
| 233 | u32 bes_rx_compl; /* number of rx completion entries | ||
| 234 | processed */ | ||
| 235 | u32 bes_ethrx_post_fail; /* number of ethrx buffer alloc | ||
| 236 | failures */ | ||
| 237 | /* | ||
| 238 | * number of non ether type II frames dropped where | ||
| 239 | * frame len > length field of Mac Hdr | ||
| 240 | */ | ||
| 241 | u32 bes_802_3_dropped_frames; | ||
| 242 | /* | ||
| 243 | * number of non ether type II frames malformed where | ||
| 244 | * in frame len < length field of Mac Hdr | ||
| 245 | */ | ||
| 246 | u32 bes_802_3_malformed_frames; | ||
| 247 | u32 bes_ips; /* interrupts / sec */ | ||
| 248 | u32 bes_prev_ints; /* bes_ints at last IPS calculation */ | ||
| 249 | u16 bes_eth_tx_rate; /* ETH TX rate - Mb/sec */ | ||
| 250 | u16 bes_eth_rx_rate; /* ETH RX rate - Mb/sec */ | ||
| 251 | u32 bes_rx_coal; /* Num pkts coalasced */ | ||
| 252 | u32 bes_rx_flush; /* Num times coalasced */ | ||
| 253 | u32 bes_link_change_physical; /*Num of times physical link changed */ | ||
| 254 | u32 bes_link_change_virtual; /*Num of times virtual link changed */ | ||
| 255 | u32 bes_rx_misc_pkts; /* Misc pkts received */ | ||
| 256 | }; | ||
| 257 | |||
| 258 | /* Maximum interrupt delay (in microseconds) allowed */ | ||
| 259 | #define MAX_EQD 120 | ||
| 260 | |||
| 261 | /* | ||
| 262 | * timer to prevent system shutdown hang for ever if h/w stops responding | ||
| 263 | */ | ||
| 264 | struct be_timer_ctxt { | ||
| 265 | atomic_t get_stat_flag; | ||
| 266 | struct timer_list get_stats_timer; | ||
| 267 | unsigned long get_stat_sem_addr; | ||
| 268 | } ; | ||
| 269 | |||
| 270 | /* This structure is the main BladeEngine driver context. */ | ||
| 271 | struct be_adapter { | ||
| 272 | struct net_device *netdevp; | ||
| 273 | struct be_drvr_stat be_stat; | ||
| 274 | struct net_device_stats benet_stats; | ||
| 275 | |||
| 276 | /* PCI BAR mapped addresses */ | ||
| 277 | u8 __iomem *csr_va; /* CSR */ | ||
| 278 | u8 __iomem *db_va; /* Door Bell */ | ||
| 279 | u8 __iomem *pci_va; /* PCI Config */ | ||
| 280 | |||
| 281 | struct tasklet_struct sts_handler; | ||
| 282 | struct timer_list cq_timer; | ||
| 283 | spinlock_t int_lock; /* to protect the isr field in adapter */ | ||
| 284 | |||
| 285 | struct FWCMD_ETH_GET_STATISTICS *eth_statsp; | ||
| 286 | /* | ||
| 287 | * This will enable the use of ethtool to enable or disable | ||
| 288 | * Checksum on Rx pkts to be obeyed or disobeyed. | ||
| 289 | * If this is true = 1, then whatever is the checksum on the | ||
| 290 | * Received pkt as per BE, it will be given to the stack. | ||
| 291 | * Else the stack will re calculate it. | ||
| 292 | */ | ||
| 293 | bool rx_csum; | ||
| 294 | /* | ||
| 295 | * This will enable the use of ethtool to enable or disable | ||
| 296 | * Coalese on Rx pkts to be obeyed or disobeyed. | ||
| 297 | * If this is grater than 0 and less than 16 then coalascing | ||
| 298 | * is enabled else it is disabled | ||
| 299 | */ | ||
| 300 | u32 max_rx_coal; | ||
| 301 | struct pci_dev *pdev; /* Pointer to OS's PCI dvice */ | ||
| 302 | |||
| 303 | spinlock_t txq_lock; /* to stop/wake queue based on tx_q_used */ | ||
| 304 | |||
| 305 | u32 isr; /* copy of Intr status reg. */ | ||
| 306 | |||
| 307 | u32 port0_link_sts; /* Port 0 link status */ | ||
| 308 | u32 port1_link_sts; /* port 1 list status */ | ||
| 309 | struct BE_LINK_STATUS *be_link_sts; | ||
| 310 | |||
| 311 | /* pointer to the first netobject of this adapter */ | ||
| 312 | struct be_net_object *net_obj; | ||
| 313 | |||
| 314 | /* Flags to indicate what to clean up */ | ||
| 315 | bool tasklet_started; | ||
| 316 | bool isr_registered; | ||
| 317 | /* | ||
| 318 | * adaptive interrupt coalescing (AIC) related | ||
| 319 | */ | ||
| 320 | bool enable_aic; /* 1 if AIC is enabled */ | ||
| 321 | u16 min_eqd; /* minimum EQ delay in usec */ | ||
| 322 | u16 max_eqd; /* minimum EQ delay in usec */ | ||
| 323 | u16 cur_eqd; /* current EQ delay in usec */ | ||
| 324 | /* | ||
| 325 | * book keeping for interrupt / sec and TX/RX rate calculation | ||
| 326 | */ | ||
| 327 | ulong ips_jiffies; /* jiffies at last IPS calc */ | ||
| 328 | u32 eth_tx_bytes; | ||
| 329 | ulong eth_tx_jiffies; | ||
| 330 | u32 eth_rx_bytes; | ||
| 331 | ulong eth_rx_jiffies; | ||
| 332 | |||
| 333 | struct semaphore get_eth_stat_sem; | ||
| 334 | |||
| 335 | /* timer ctxt to prevent shutdown hanging due to un-responsive BE */ | ||
| 336 | struct be_timer_ctxt timer_ctxt; | ||
| 337 | |||
| 338 | #define BE_MAX_MSIX_VECTORS 32 | ||
| 339 | #define BE_MAX_REQ_MSIX_VECTORS 1 /* only one EQ in Linux driver */ | ||
| 340 | struct msix_entry msix_entries[BE_MAX_MSIX_VECTORS]; | ||
| 341 | bool msix_enabled; | ||
| 342 | bool dma_64bit_cap; /* the Device DAC capable or not */ | ||
| 343 | u8 dev_state; /* The current state of the device */ | ||
| 344 | u8 dev_pm_state; /* The State of device before going to suspend */ | ||
| 345 | }; | ||
| 346 | |||
| 347 | /* | ||
| 348 | * Every second we look at the ints/sec and adjust eq_delay | ||
| 349 | * between adapter->min_eqd and adapter->max_eqd to keep the ints/sec between | ||
| 350 | * IPS_HI_WM and IPS_LO_WM. | ||
| 351 | */ | ||
| 352 | #define IPS_HI_WM 18000 | ||
| 353 | #define IPS_LO_WM 8000 | ||
| 354 | |||
| 355 | |||
| 356 | static inline void index_adv(u32 *index, u32 val, u32 limit) | ||
| 357 | { | ||
| 358 | BUG_ON(limit & (limit-1)); | ||
| 359 | *index = (*index + val) & (limit - 1); | ||
| 360 | } | ||
| 361 | |||
| 362 | static inline void index_inc(u32 *index, u32 limit) | ||
| 363 | { | ||
| 364 | BUG_ON(limit & (limit-1)); | ||
| 365 | *index = (*index + 1) & (limit - 1); | ||
| 366 | } | ||
| 367 | |||
| 368 | static inline void be_adv_eq_tl(struct be_net_object *pnob) | ||
| 369 | { | ||
| 370 | index_inc(&pnob->event_q_tl, pnob->event_q_len); | ||
| 371 | } | ||
| 372 | |||
| 373 | static inline void be_adv_txq_hd(struct be_net_object *pnob) | ||
| 374 | { | ||
| 375 | index_inc(&pnob->tx_q_hd, pnob->tx_q_len); | ||
| 376 | } | ||
| 377 | |||
| 378 | static inline void be_adv_txq_tl(struct be_net_object *pnob) | ||
| 379 | { | ||
| 380 | index_inc(&pnob->tx_q_tl, pnob->tx_q_len); | ||
| 381 | } | ||
| 382 | |||
| 383 | static inline void be_adv_txcq_tl(struct be_net_object *pnob) | ||
| 384 | { | ||
| 385 | index_inc(&pnob->tx_cq_tl, pnob->txcq_len); | ||
| 386 | } | ||
| 387 | |||
| 388 | static inline void be_adv_rxq_hd(struct be_net_object *pnob) | ||
| 389 | { | ||
| 390 | index_inc(&pnob->rx_q_hd, pnob->rx_q_len); | ||
| 391 | } | ||
| 392 | |||
| 393 | static inline void be_adv_rxcq_tl(struct be_net_object *pnob) | ||
| 394 | { | ||
| 395 | index_inc(&pnob->rx_cq_tl, pnob->rx_cq_len); | ||
| 396 | } | ||
| 397 | |||
| 398 | static inline u32 tx_compl_lastwrb_idx_get(struct be_net_object *pnob) | ||
| 399 | { | ||
| 400 | return (pnob->tx_q_tl + *(u32 *)&pnob->tx_ctxt[pnob->tx_q_tl] - 1) | ||
| 401 | & (pnob->tx_q_len - 1); | ||
| 402 | } | ||
| 403 | |||
| 404 | int benet_init(struct net_device *); | ||
| 405 | int be_ethtool_ioctl(struct net_device *, struct ifreq *); | ||
| 406 | struct net_device_stats *benet_get_stats(struct net_device *); | ||
| 407 | void be_process_intr(unsigned long context); | ||
| 408 | irqreturn_t be_int(int irq, void *dev); | ||
| 409 | void be_post_eth_rx_buffs(struct be_net_object *); | ||
| 410 | void be_get_stat_cb(void *, int, struct MCC_WRB_AMAP *); | ||
| 411 | void be_get_stats_timer_handler(unsigned long); | ||
| 412 | void be_wait_nic_tx_cmplx_cmpl(struct be_net_object *); | ||
| 413 | void be_print_link_info(struct BE_LINK_STATUS *); | ||
| 414 | void be_update_link_status(struct be_adapter *); | ||
| 415 | void be_init_procfs(struct be_adapter *); | ||
| 416 | void be_cleanup_procfs(struct be_adapter *); | ||
| 417 | int be_poll(struct napi_struct *, int); | ||
| 418 | struct ETH_RX_COMPL_AMAP *be_get_rx_cmpl(struct be_net_object *); | ||
| 419 | void be_notify_cmpl(struct be_net_object *, int, int, int); | ||
| 420 | void be_enable_intr(struct be_net_object *); | ||
| 421 | void be_enable_eq_intr(struct be_net_object *); | ||
| 422 | void be_disable_intr(struct be_net_object *); | ||
| 423 | void be_disable_eq_intr(struct be_net_object *); | ||
| 424 | int be_set_uc_mac_adr(struct be_net_object *, u8, u8, u8, | ||
| 425 | u8 *, mcc_wrb_cqe_callback, void *); | ||
| 426 | int be_get_flow_ctl(struct be_function_object *pFnObj, bool *, bool *); | ||
| 427 | void process_one_tx_compl(struct be_net_object *pnob, u32 end_idx); | ||
| 428 | |||
| 429 | #endif /* _BENET_H_ */ | ||
diff --git a/drivers/staging/benet/bestatus.h b/drivers/staging/benet/bestatus.h deleted file mode 100644 index 59c7a4b62223..000000000000 --- a/drivers/staging/benet/bestatus.h +++ /dev/null | |||
| @@ -1,103 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | #ifndef _BESTATUS_H_ | ||
| 18 | #define _BESTATUS_H_ | ||
| 19 | |||
| 20 | #define BE_SUCCESS (0x00000000L) | ||
| 21 | /* | ||
| 22 | * MessageId: BE_PENDING | ||
| 23 | * The BladeEngine Driver call succeeded, and pended operation. | ||
| 24 | */ | ||
| 25 | #define BE_PENDING (0x20070001L) | ||
| 26 | #define BE_STATUS_PENDING (BE_PENDING) | ||
| 27 | /* | ||
| 28 | * MessageId: BE_NOT_OK | ||
| 29 | * An error occurred. | ||
| 30 | */ | ||
| 31 | #define BE_NOT_OK (0xE0070002L) | ||
| 32 | /* | ||
| 33 | * MessageId: BE_STATUS_SYSTEM_RESOURCES | ||
| 34 | * Insufficient host system resources exist to complete the API. | ||
| 35 | */ | ||
| 36 | #define BE_STATUS_SYSTEM_RESOURCES (0xE0070003L) | ||
| 37 | /* | ||
| 38 | * MessageId: BE_STATUS_CHIP_RESOURCES | ||
| 39 | * Insufficient chip resources exist to complete the API. | ||
| 40 | */ | ||
| 41 | #define BE_STATUS_CHIP_RESOURCES (0xE0070004L) | ||
| 42 | /* | ||
| 43 | * MessageId: BE_STATUS_NO_RESOURCE | ||
| 44 | * Insufficient resources to complete request. | ||
| 45 | */ | ||
| 46 | #define BE_STATUS_NO_RESOURCE (0xE0070005L) | ||
| 47 | /* | ||
| 48 | * MessageId: BE_STATUS_BUSY | ||
| 49 | * Resource is currently busy. | ||
| 50 | */ | ||
| 51 | #define BE_STATUS_BUSY (0xE0070006L) | ||
| 52 | /* | ||
| 53 | * MessageId: BE_STATUS_INVALID_PARAMETER | ||
| 54 | * Invalid Parameter in request. | ||
| 55 | */ | ||
| 56 | #define BE_STATUS_INVALID_PARAMETER (0xE0000007L) | ||
| 57 | /* | ||
| 58 | * MessageId: BE_STATUS_NOT_SUPPORTED | ||
| 59 | * Requested operation is not supported. | ||
| 60 | */ | ||
| 61 | #define BE_STATUS_NOT_SUPPORTED (0xE000000DL) | ||
| 62 | |||
| 63 | /* | ||
| 64 | * *************************************************************************** | ||
| 65 | * E T H E R N E T S T A T U S | ||
| 66 | * *************************************************************************** | ||
| 67 | */ | ||
| 68 | |||
| 69 | /* | ||
| 70 | * MessageId: BE_ETH_TX_ERROR | ||
| 71 | * The Ethernet device driver failed to transmit a packet. | ||
| 72 | */ | ||
| 73 | #define BE_ETH_TX_ERROR (0xE0070101L) | ||
| 74 | |||
| 75 | /* | ||
| 76 | * *************************************************************************** | ||
| 77 | * S H A R E D S T A T U S | ||
| 78 | * *************************************************************************** | ||
| 79 | */ | ||
| 80 | |||
| 81 | /* | ||
| 82 | * MessageId: BE_STATUS_VBD_INVALID_VERSION | ||
| 83 | * The device driver is not compatible with this version of the VBD. | ||
| 84 | */ | ||
| 85 | #define BE_STATUS_INVALID_VERSION (0xE0070402L) | ||
| 86 | /* | ||
| 87 | * MessageId: BE_STATUS_DOMAIN_DENIED | ||
| 88 | * The operation failed to complete due to insufficient access | ||
| 89 | * rights for the requesting domain. | ||
| 90 | */ | ||
| 91 | #define BE_STATUS_DOMAIN_DENIED (0xE0070403L) | ||
| 92 | /* | ||
| 93 | * MessageId: BE_STATUS_TCP_NOT_STARTED | ||
| 94 | * The embedded TCP/IP stack has not been started. | ||
| 95 | */ | ||
| 96 | #define BE_STATUS_TCP_NOT_STARTED (0xE0070409L) | ||
| 97 | /* | ||
| 98 | * MessageId: BE_STATUS_NO_MCC_WRB | ||
| 99 | * No free MCC WRB are available for posting the request. | ||
| 100 | */ | ||
| 101 | #define BE_STATUS_NO_MCC_WRB (0xE0070414L) | ||
| 102 | |||
| 103 | #endif /* _BESTATUS_ */ | ||
diff --git a/drivers/staging/benet/cev.h b/drivers/staging/benet/cev.h deleted file mode 100644 index 30996920a544..000000000000 --- a/drivers/staging/benet/cev.h +++ /dev/null | |||
| @@ -1,243 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __cev_amap_h__ | ||
| 21 | #define __cev_amap_h__ | ||
| 22 | #include "ep.h" | ||
| 23 | |||
| 24 | /* | ||
| 25 | * Host Interrupt Status Register 0. The first of four application | ||
| 26 | * interrupt status registers. This register contains the interrupts | ||
| 27 | * for Event Queues EQ0 through EQ31. | ||
| 28 | */ | ||
| 29 | struct BE_CEV_ISR0_CSR_AMAP { | ||
| 30 | u8 interrupt0; /* DWORD 0 */ | ||
| 31 | u8 interrupt1; /* DWORD 0 */ | ||
| 32 | u8 interrupt2; /* DWORD 0 */ | ||
| 33 | u8 interrupt3; /* DWORD 0 */ | ||
| 34 | u8 interrupt4; /* DWORD 0 */ | ||
| 35 | u8 interrupt5; /* DWORD 0 */ | ||
| 36 | u8 interrupt6; /* DWORD 0 */ | ||
| 37 | u8 interrupt7; /* DWORD 0 */ | ||
| 38 | u8 interrupt8; /* DWORD 0 */ | ||
| 39 | u8 interrupt9; /* DWORD 0 */ | ||
| 40 | u8 interrupt10; /* DWORD 0 */ | ||
| 41 | u8 interrupt11; /* DWORD 0 */ | ||
| 42 | u8 interrupt12; /* DWORD 0 */ | ||
| 43 | u8 interrupt13; /* DWORD 0 */ | ||
| 44 | u8 interrupt14; /* DWORD 0 */ | ||
| 45 | u8 interrupt15; /* DWORD 0 */ | ||
| 46 | u8 interrupt16; /* DWORD 0 */ | ||
| 47 | u8 interrupt17; /* DWORD 0 */ | ||
| 48 | u8 interrupt18; /* DWORD 0 */ | ||
| 49 | u8 interrupt19; /* DWORD 0 */ | ||
| 50 | u8 interrupt20; /* DWORD 0 */ | ||
| 51 | u8 interrupt21; /* DWORD 0 */ | ||
| 52 | u8 interrupt22; /* DWORD 0 */ | ||
| 53 | u8 interrupt23; /* DWORD 0 */ | ||
| 54 | u8 interrupt24; /* DWORD 0 */ | ||
| 55 | u8 interrupt25; /* DWORD 0 */ | ||
| 56 | u8 interrupt26; /* DWORD 0 */ | ||
| 57 | u8 interrupt27; /* DWORD 0 */ | ||
| 58 | u8 interrupt28; /* DWORD 0 */ | ||
| 59 | u8 interrupt29; /* DWORD 0 */ | ||
| 60 | u8 interrupt30; /* DWORD 0 */ | ||
| 61 | u8 interrupt31; /* DWORD 0 */ | ||
| 62 | } __packed; | ||
| 63 | struct CEV_ISR0_CSR_AMAP { | ||
| 64 | u32 dw[1]; | ||
| 65 | }; | ||
| 66 | |||
| 67 | /* | ||
| 68 | * Host Interrupt Status Register 1. The second of four application | ||
| 69 | * interrupt status registers. This register contains the interrupts | ||
| 70 | * for Event Queues EQ32 through EQ63. | ||
| 71 | */ | ||
| 72 | struct BE_CEV_ISR1_CSR_AMAP { | ||
| 73 | u8 interrupt32; /* DWORD 0 */ | ||
| 74 | u8 interrupt33; /* DWORD 0 */ | ||
| 75 | u8 interrupt34; /* DWORD 0 */ | ||
| 76 | u8 interrupt35; /* DWORD 0 */ | ||
| 77 | u8 interrupt36; /* DWORD 0 */ | ||
| 78 | u8 interrupt37; /* DWORD 0 */ | ||
| 79 | u8 interrupt38; /* DWORD 0 */ | ||
| 80 | u8 interrupt39; /* DWORD 0 */ | ||
| 81 | u8 interrupt40; /* DWORD 0 */ | ||
| 82 | u8 interrupt41; /* DWORD 0 */ | ||
| 83 | u8 interrupt42; /* DWORD 0 */ | ||
| 84 | u8 interrupt43; /* DWORD 0 */ | ||
| 85 | u8 interrupt44; /* DWORD 0 */ | ||
| 86 | u8 interrupt45; /* DWORD 0 */ | ||
| 87 | u8 interrupt46; /* DWORD 0 */ | ||
| 88 | u8 interrupt47; /* DWORD 0 */ | ||
| 89 | u8 interrupt48; /* DWORD 0 */ | ||
| 90 | u8 interrupt49; /* DWORD 0 */ | ||
| 91 | u8 interrupt50; /* DWORD 0 */ | ||
| 92 | u8 interrupt51; /* DWORD 0 */ | ||
| 93 | u8 interrupt52; /* DWORD 0 */ | ||
| 94 | u8 interrupt53; /* DWORD 0 */ | ||
| 95 | u8 interrupt54; /* DWORD 0 */ | ||
| 96 | u8 interrupt55; /* DWORD 0 */ | ||
| 97 | u8 interrupt56; /* DWORD 0 */ | ||
| 98 | u8 interrupt57; /* DWORD 0 */ | ||
| 99 | u8 interrupt58; /* DWORD 0 */ | ||
| 100 | u8 interrupt59; /* DWORD 0 */ | ||
| 101 | u8 interrupt60; /* DWORD 0 */ | ||
| 102 | u8 interrupt61; /* DWORD 0 */ | ||
| 103 | u8 interrupt62; /* DWORD 0 */ | ||
| 104 | u8 interrupt63; /* DWORD 0 */ | ||
| 105 | } __packed; | ||
| 106 | struct CEV_ISR1_CSR_AMAP { | ||
| 107 | u32 dw[1]; | ||
| 108 | }; | ||
| 109 | /* | ||
| 110 | * Host Interrupt Status Register 2. The third of four application | ||
| 111 | * interrupt status registers. This register contains the interrupts | ||
| 112 | * for Event Queues EQ64 through EQ95. | ||
| 113 | */ | ||
| 114 | struct BE_CEV_ISR2_CSR_AMAP { | ||
| 115 | u8 interrupt64; /* DWORD 0 */ | ||
| 116 | u8 interrupt65; /* DWORD 0 */ | ||
| 117 | u8 interrupt66; /* DWORD 0 */ | ||
| 118 | u8 interrupt67; /* DWORD 0 */ | ||
| 119 | u8 interrupt68; /* DWORD 0 */ | ||
| 120 | u8 interrupt69; /* DWORD 0 */ | ||
| 121 | u8 interrupt70; /* DWORD 0 */ | ||
| 122 | u8 interrupt71; /* DWORD 0 */ | ||
| 123 | u8 interrupt72; /* DWORD 0 */ | ||
| 124 | u8 interrupt73; /* DWORD 0 */ | ||
| 125 | u8 interrupt74; /* DWORD 0 */ | ||
| 126 | u8 interrupt75; /* DWORD 0 */ | ||
| 127 | u8 interrupt76; /* DWORD 0 */ | ||
| 128 | u8 interrupt77; /* DWORD 0 */ | ||
| 129 | u8 interrupt78; /* DWORD 0 */ | ||
| 130 | u8 interrupt79; /* DWORD 0 */ | ||
| 131 | u8 interrupt80; /* DWORD 0 */ | ||
| 132 | u8 interrupt81; /* DWORD 0 */ | ||
| 133 | u8 interrupt82; /* DWORD 0 */ | ||
| 134 | u8 interrupt83; /* DWORD 0 */ | ||
| 135 | u8 interrupt84; /* DWORD 0 */ | ||
| 136 | u8 interrupt85; /* DWORD 0 */ | ||
| 137 | u8 interrupt86; /* DWORD 0 */ | ||
| 138 | u8 interrupt87; /* DWORD 0 */ | ||
| 139 | u8 interrupt88; /* DWORD 0 */ | ||
| 140 | u8 interrupt89; /* DWORD 0 */ | ||
| 141 | u8 interrupt90; /* DWORD 0 */ | ||
| 142 | u8 interrupt91; /* DWORD 0 */ | ||
| 143 | u8 interrupt92; /* DWORD 0 */ | ||
| 144 | u8 interrupt93; /* DWORD 0 */ | ||
| 145 | u8 interrupt94; /* DWORD 0 */ | ||
| 146 | u8 interrupt95; /* DWORD 0 */ | ||
| 147 | } __packed; | ||
| 148 | struct CEV_ISR2_CSR_AMAP { | ||
| 149 | u32 dw[1]; | ||
| 150 | }; | ||
| 151 | |||
| 152 | /* | ||
| 153 | * Host Interrupt Status Register 3. The fourth of four application | ||
| 154 | * interrupt status registers. This register contains the interrupts | ||
| 155 | * for Event Queues EQ96 through EQ127. | ||
| 156 | */ | ||
| 157 | struct BE_CEV_ISR3_CSR_AMAP { | ||
| 158 | u8 interrupt96; /* DWORD 0 */ | ||
| 159 | u8 interrupt97; /* DWORD 0 */ | ||
| 160 | u8 interrupt98; /* DWORD 0 */ | ||
| 161 | u8 interrupt99; /* DWORD 0 */ | ||
| 162 | u8 interrupt100; /* DWORD 0 */ | ||
| 163 | u8 interrupt101; /* DWORD 0 */ | ||
| 164 | u8 interrupt102; /* DWORD 0 */ | ||
| 165 | u8 interrupt103; /* DWORD 0 */ | ||
| 166 | u8 interrupt104; /* DWORD 0 */ | ||
| 167 | u8 interrupt105; /* DWORD 0 */ | ||
| 168 | u8 interrupt106; /* DWORD 0 */ | ||
| 169 | u8 interrupt107; /* DWORD 0 */ | ||
| 170 | u8 interrupt108; /* DWORD 0 */ | ||
| 171 | u8 interrupt109; /* DWORD 0 */ | ||
| 172 | u8 interrupt110; /* DWORD 0 */ | ||
| 173 | u8 interrupt111; /* DWORD 0 */ | ||
| 174 | u8 interrupt112; /* DWORD 0 */ | ||
| 175 | u8 interrupt113; /* DWORD 0 */ | ||
| 176 | u8 interrupt114; /* DWORD 0 */ | ||
| 177 | u8 interrupt115; /* DWORD 0 */ | ||
| 178 | u8 interrupt116; /* DWORD 0 */ | ||
| 179 | u8 interrupt117; /* DWORD 0 */ | ||
| 180 | u8 interrupt118; /* DWORD 0 */ | ||
| 181 | u8 interrupt119; /* DWORD 0 */ | ||
| 182 | u8 interrupt120; /* DWORD 0 */ | ||
| 183 | u8 interrupt121; /* DWORD 0 */ | ||
| 184 | u8 interrupt122; /* DWORD 0 */ | ||
| 185 | u8 interrupt123; /* DWORD 0 */ | ||
| 186 | u8 interrupt124; /* DWORD 0 */ | ||
| 187 | u8 interrupt125; /* DWORD 0 */ | ||
| 188 | u8 interrupt126; /* DWORD 0 */ | ||
| 189 | u8 interrupt127; /* DWORD 0 */ | ||
| 190 | } __packed; | ||
| 191 | struct CEV_ISR3_CSR_AMAP { | ||
| 192 | u32 dw[1]; | ||
| 193 | }; | ||
| 194 | |||
| 195 | /* Completions and Events block Registers. */ | ||
| 196 | struct BE_CEV_CSRMAP_AMAP { | ||
| 197 | u8 rsvd0[32]; /* DWORD 0 */ | ||
| 198 | u8 rsvd1[32]; /* DWORD 1 */ | ||
| 199 | u8 rsvd2[32]; /* DWORD 2 */ | ||
| 200 | u8 rsvd3[32]; /* DWORD 3 */ | ||
| 201 | struct BE_CEV_ISR0_CSR_AMAP isr0; | ||
| 202 | struct BE_CEV_ISR1_CSR_AMAP isr1; | ||
| 203 | struct BE_CEV_ISR2_CSR_AMAP isr2; | ||
| 204 | struct BE_CEV_ISR3_CSR_AMAP isr3; | ||
| 205 | u8 rsvd4[32]; /* DWORD 8 */ | ||
| 206 | u8 rsvd5[32]; /* DWORD 9 */ | ||
| 207 | u8 rsvd6[32]; /* DWORD 10 */ | ||
| 208 | u8 rsvd7[32]; /* DWORD 11 */ | ||
| 209 | u8 rsvd8[32]; /* DWORD 12 */ | ||
| 210 | u8 rsvd9[32]; /* DWORD 13 */ | ||
| 211 | u8 rsvd10[32]; /* DWORD 14 */ | ||
| 212 | u8 rsvd11[32]; /* DWORD 15 */ | ||
| 213 | u8 rsvd12[32]; /* DWORD 16 */ | ||
| 214 | u8 rsvd13[32]; /* DWORD 17 */ | ||
| 215 | u8 rsvd14[32]; /* DWORD 18 */ | ||
| 216 | u8 rsvd15[32]; /* DWORD 19 */ | ||
| 217 | u8 rsvd16[32]; /* DWORD 20 */ | ||
| 218 | u8 rsvd17[32]; /* DWORD 21 */ | ||
| 219 | u8 rsvd18[32]; /* DWORD 22 */ | ||
| 220 | u8 rsvd19[32]; /* DWORD 23 */ | ||
| 221 | u8 rsvd20[32]; /* DWORD 24 */ | ||
| 222 | u8 rsvd21[32]; /* DWORD 25 */ | ||
| 223 | u8 rsvd22[32]; /* DWORD 26 */ | ||
| 224 | u8 rsvd23[32]; /* DWORD 27 */ | ||
| 225 | u8 rsvd24[32]; /* DWORD 28 */ | ||
| 226 | u8 rsvd25[32]; /* DWORD 29 */ | ||
| 227 | u8 rsvd26[32]; /* DWORD 30 */ | ||
| 228 | u8 rsvd27[32]; /* DWORD 31 */ | ||
| 229 | u8 rsvd28[32]; /* DWORD 32 */ | ||
| 230 | u8 rsvd29[32]; /* DWORD 33 */ | ||
| 231 | u8 rsvd30[192]; /* DWORD 34 */ | ||
| 232 | u8 rsvd31[192]; /* DWORD 40 */ | ||
| 233 | u8 rsvd32[160]; /* DWORD 46 */ | ||
| 234 | u8 rsvd33[160]; /* DWORD 51 */ | ||
| 235 | u8 rsvd34[160]; /* DWORD 56 */ | ||
| 236 | u8 rsvd35[96]; /* DWORD 61 */ | ||
| 237 | u8 rsvd36[192][32]; /* DWORD 64 */ | ||
| 238 | } __packed; | ||
| 239 | struct CEV_CSRMAP_AMAP { | ||
| 240 | u32 dw[256]; | ||
| 241 | }; | ||
| 242 | |||
| 243 | #endif /* __cev_amap_h__ */ | ||
diff --git a/drivers/staging/benet/cq.c b/drivers/staging/benet/cq.c deleted file mode 100644 index 650458645433..000000000000 --- a/drivers/staging/benet/cq.c +++ /dev/null | |||
| @@ -1,211 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | #include "hwlib.h" | ||
| 18 | #include "bestatus.h" | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Completion Queue Objects | ||
| 22 | */ | ||
| 23 | /* | ||
| 24 | *============================================================================ | ||
| 25 | * P U B L I C R O U T I N E S | ||
| 26 | *============================================================================ | ||
| 27 | */ | ||
| 28 | |||
| 29 | /* | ||
| 30 | This routine creates a completion queue based on the client completion | ||
| 31 | queue configuration information. | ||
| 32 | |||
| 33 | |||
| 34 | FunctionObject - Handle to a function object | ||
| 35 | CqBaseVa - Base VA for a the CQ ring | ||
| 36 | NumEntries - CEV_CQ_CNT_* values | ||
| 37 | solEventEnable - 0 = All CQEs can generate Events if CQ is eventable | ||
| 38 | 1 = only CQEs with solicited bit set are eventable | ||
| 39 | eventable - Eventable CQ, generates interrupts. | ||
| 40 | nodelay - 1 = Force interrupt, relevent if CQ eventable. | ||
| 41 | Interrupt is asserted immediately after EQE | ||
| 42 | write is confirmed, regardless of EQ Timer | ||
| 43 | or watermark settings. | ||
| 44 | wme - Enable watermark based coalescing | ||
| 45 | wmThresh - High watermark(CQ fullness at which event | ||
| 46 | or interrupt should be asserted). These are the | ||
| 47 | CEV_WATERMARK encoded values. | ||
| 48 | EqObject - EQ Handle to assign to this CQ | ||
| 49 | ppCqObject - Internal CQ Handle returned. | ||
| 50 | |||
| 51 | Returns BE_SUCCESS if successfull, otherwise a useful error code is | ||
| 52 | returned. | ||
| 53 | |||
| 54 | IRQL < DISPATCH_LEVEL | ||
| 55 | |||
| 56 | */ | ||
| 57 | int be_cq_create(struct be_function_object *pfob, | ||
| 58 | struct ring_desc *rd, u32 length, bool solicited_eventable, | ||
| 59 | bool no_delay, u32 wm_thresh, | ||
| 60 | struct be_eq_object *eq_object, struct be_cq_object *cq_object) | ||
| 61 | { | ||
| 62 | int status = BE_SUCCESS; | ||
| 63 | u32 num_entries_encoding; | ||
| 64 | u32 num_entries = length / sizeof(struct MCC_CQ_ENTRY_AMAP); | ||
| 65 | struct FWCMD_COMMON_CQ_CREATE *fwcmd = NULL; | ||
| 66 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 67 | u32 n; | ||
| 68 | unsigned long irql; | ||
| 69 | |||
| 70 | ASSERT(rd); | ||
| 71 | ASSERT(cq_object); | ||
| 72 | ASSERT(length % sizeof(struct MCC_CQ_ENTRY_AMAP) == 0); | ||
| 73 | |||
| 74 | switch (num_entries) { | ||
| 75 | case 256: | ||
| 76 | num_entries_encoding = CEV_CQ_CNT_256; | ||
| 77 | break; | ||
| 78 | case 512: | ||
| 79 | num_entries_encoding = CEV_CQ_CNT_512; | ||
| 80 | break; | ||
| 81 | case 1024: | ||
| 82 | num_entries_encoding = CEV_CQ_CNT_1024; | ||
| 83 | break; | ||
| 84 | default: | ||
| 85 | ASSERT(0); | ||
| 86 | return BE_STATUS_INVALID_PARAMETER; | ||
| 87 | } | ||
| 88 | |||
| 89 | /* | ||
| 90 | * All cq entries all the same size. Use iSCSI version | ||
| 91 | * as a test for the proper rd length. | ||
| 92 | */ | ||
| 93 | memset(cq_object, 0, sizeof(*cq_object)); | ||
| 94 | |||
| 95 | atomic_set(&cq_object->ref_count, 0); | ||
| 96 | cq_object->parent_function = pfob; | ||
| 97 | cq_object->eq_object = eq_object; | ||
| 98 | cq_object->num_entries = num_entries; | ||
| 99 | /* save for MCC cq processing */ | ||
| 100 | cq_object->va = rd->va; | ||
| 101 | |||
| 102 | /* map into UT. */ | ||
| 103 | length = num_entries * sizeof(struct MCC_CQ_ENTRY_AMAP); | ||
| 104 | |||
| 105 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 106 | |||
| 107 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 108 | if (!wrb) { | ||
| 109 | ASSERT(wrb); | ||
| 110 | TRACE(DL_ERR, "No free MCC WRBs in create EQ."); | ||
| 111 | status = BE_STATUS_NO_MCC_WRB; | ||
| 112 | goto Error; | ||
| 113 | } | ||
| 114 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 115 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_CQ_CREATE); | ||
| 116 | |||
| 117 | fwcmd->params.request.num_pages = PAGES_SPANNED(OFFSET_IN_PAGE(rd->va), | ||
| 118 | length); | ||
| 119 | |||
| 120 | AMAP_SET_BITS_PTR(CQ_CONTEXT, valid, &fwcmd->params.request.context, 1); | ||
| 121 | n = pfob->pci_function_number; | ||
| 122 | AMAP_SET_BITS_PTR(CQ_CONTEXT, Func, &fwcmd->params.request.context, n); | ||
| 123 | |||
| 124 | n = (eq_object != NULL); | ||
| 125 | AMAP_SET_BITS_PTR(CQ_CONTEXT, Eventable, | ||
| 126 | &fwcmd->params.request.context, n); | ||
| 127 | AMAP_SET_BITS_PTR(CQ_CONTEXT, Armed, &fwcmd->params.request.context, 1); | ||
| 128 | |||
| 129 | n = eq_object ? eq_object->eq_id : 0; | ||
| 130 | AMAP_SET_BITS_PTR(CQ_CONTEXT, EQID, &fwcmd->params.request.context, n); | ||
| 131 | AMAP_SET_BITS_PTR(CQ_CONTEXT, Count, | ||
| 132 | &fwcmd->params.request.context, num_entries_encoding); | ||
| 133 | |||
| 134 | n = 0; /* Protection Domain is always 0 in Linux driver */ | ||
| 135 | AMAP_SET_BITS_PTR(CQ_CONTEXT, PD, &fwcmd->params.request.context, n); | ||
| 136 | AMAP_SET_BITS_PTR(CQ_CONTEXT, NoDelay, | ||
| 137 | &fwcmd->params.request.context, no_delay); | ||
| 138 | AMAP_SET_BITS_PTR(CQ_CONTEXT, SolEvent, | ||
| 139 | &fwcmd->params.request.context, solicited_eventable); | ||
| 140 | |||
| 141 | n = (wm_thresh != 0xFFFFFFFF); | ||
| 142 | AMAP_SET_BITS_PTR(CQ_CONTEXT, WME, &fwcmd->params.request.context, n); | ||
| 143 | |||
| 144 | n = (n ? wm_thresh : 0); | ||
| 145 | AMAP_SET_BITS_PTR(CQ_CONTEXT, Watermark, | ||
| 146 | &fwcmd->params.request.context, n); | ||
| 147 | /* Create a page list for the FWCMD. */ | ||
| 148 | be_rd_to_pa_list(rd, fwcmd->params.request.pages, | ||
| 149 | ARRAY_SIZE(fwcmd->params.request.pages)); | ||
| 150 | |||
| 151 | /* Post the f/w command */ | ||
| 152 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, NULL, NULL, | ||
| 153 | NULL, NULL, fwcmd, NULL); | ||
| 154 | if (status != BE_SUCCESS) { | ||
| 155 | TRACE(DL_ERR, "MCC to create CQ failed."); | ||
| 156 | goto Error; | ||
| 157 | } | ||
| 158 | /* Remember the CQ id. */ | ||
| 159 | cq_object->cq_id = fwcmd->params.response.cq_id; | ||
| 160 | |||
| 161 | /* insert this cq into eq_object reference */ | ||
| 162 | if (eq_object) { | ||
| 163 | atomic_inc(&eq_object->ref_count); | ||
| 164 | list_add_tail(&cq_object->cqlist_for_eq, | ||
| 165 | &eq_object->cq_list_head); | ||
| 166 | } | ||
| 167 | |||
| 168 | Error: | ||
| 169 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 170 | |||
| 171 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 172 | pfob->pend_queue_driving = 0; | ||
| 173 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 174 | } | ||
| 175 | return status; | ||
| 176 | } | ||
| 177 | |||
| 178 | /* | ||
| 179 | |||
| 180 | Deferences the given object. Once the object's reference count drops to | ||
| 181 | zero, the object is destroyed and all resources that are held by this object | ||
| 182 | are released. The on-chip context is also destroyed along with the queue | ||
| 183 | ID, and any mappings made into the UT. | ||
| 184 | |||
| 185 | cq_object - CQ handle returned from cq_object_create. | ||
| 186 | |||
| 187 | returns the current reference count on the object | ||
| 188 | |||
| 189 | IRQL: IRQL < DISPATCH_LEVEL | ||
| 190 | */ | ||
| 191 | int be_cq_destroy(struct be_cq_object *cq_object) | ||
| 192 | { | ||
| 193 | int status = 0; | ||
| 194 | |||
| 195 | /* Nothing should reference this CQ at this point. */ | ||
| 196 | ASSERT(atomic_read(&cq_object->ref_count) == 0); | ||
| 197 | |||
| 198 | /* Send fwcmd to destroy the CQ. */ | ||
| 199 | status = be_function_ring_destroy(cq_object->parent_function, | ||
| 200 | cq_object->cq_id, FWCMD_RING_TYPE_CQ, | ||
| 201 | NULL, NULL, NULL, NULL); | ||
| 202 | ASSERT(status == 0); | ||
| 203 | |||
| 204 | /* Remove reference if this is an eventable CQ. */ | ||
| 205 | if (cq_object->eq_object) { | ||
| 206 | atomic_dec(&cq_object->eq_object->ref_count); | ||
| 207 | list_del(&cq_object->cqlist_for_eq); | ||
| 208 | } | ||
| 209 | return BE_SUCCESS; | ||
| 210 | } | ||
| 211 | |||
diff --git a/drivers/staging/benet/descriptors.h b/drivers/staging/benet/descriptors.h deleted file mode 100644 index 8da438c407d2..000000000000 --- a/drivers/staging/benet/descriptors.h +++ /dev/null | |||
| @@ -1,71 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __descriptors_amap_h__ | ||
| 21 | #define __descriptors_amap_h__ | ||
| 22 | |||
| 23 | /* | ||
| 24 | * --- IPC_NODE_ID_ENUM --- | ||
| 25 | * IPC processor id values | ||
| 26 | */ | ||
| 27 | #define TPOST_NODE_ID (0) /* TPOST ID */ | ||
| 28 | #define TPRE_NODE_ID (1) /* TPRE ID */ | ||
| 29 | #define TXULP0_NODE_ID (2) /* TXULP0 ID */ | ||
| 30 | #define TXULP1_NODE_ID (3) /* TXULP1 ID */ | ||
| 31 | #define TXULP2_NODE_ID (4) /* TXULP2 ID */ | ||
| 32 | #define RXULP0_NODE_ID (5) /* RXULP0 ID */ | ||
| 33 | #define RXULP1_NODE_ID (6) /* RXULP1 ID */ | ||
| 34 | #define RXULP2_NODE_ID (7) /* RXULP2 ID */ | ||
| 35 | #define MPU_NODE_ID (15) /* MPU ID */ | ||
| 36 | |||
| 37 | /* | ||
| 38 | * --- MAC_ID_ENUM --- | ||
| 39 | * Meaning of the mac_id field in rxpp_eth_d | ||
| 40 | */ | ||
| 41 | #define PORT0_HOST_MAC0 (0) /* PD 0, Port 0, host networking, MAC 0. */ | ||
| 42 | #define PORT0_HOST_MAC1 (1) /* PD 0, Port 0, host networking, MAC 1. */ | ||
| 43 | #define PORT0_STORAGE_MAC0 (2) /* PD 0, Port 0, host storage, MAC 0. */ | ||
| 44 | #define PORT0_STORAGE_MAC1 (3) /* PD 0, Port 0, host storage, MAC 1. */ | ||
| 45 | #define PORT1_HOST_MAC0 (4) /* PD 0, Port 1 host networking, MAC 0. */ | ||
| 46 | #define PORT1_HOST_MAC1 (5) /* PD 0, Port 1 host networking, MAC 1. */ | ||
| 47 | #define PORT1_STORAGE_MAC0 (6) /* PD 0, Port 1 host storage, MAC 0. */ | ||
| 48 | #define PORT1_STORAGE_MAC1 (7) /* PD 0, Port 1 host storage, MAC 1. */ | ||
| 49 | #define FIRST_VM_MAC (8) /* PD 1 MAC. Protection domains have IDs */ | ||
| 50 | /* from 0x8-0x26, one per PD. */ | ||
| 51 | #define LAST_VM_MAC (38) /* PD 31 MAC. */ | ||
| 52 | #define MGMT_MAC (39) /* Management port MAC. */ | ||
| 53 | #define MARBLE_MAC0 (59) /* Used for flushing function 0 receive */ | ||
| 54 | /* | ||
| 55 | * queues before re-using a torn-down | ||
| 56 | * receive ring. the DA = | ||
| 57 | * 00-00-00-00-00-00, and the MSB of the | ||
| 58 | * SA = 00 | ||
| 59 | */ | ||
| 60 | #define MARBLE_MAC1 (60) /* Used for flushing function 1 receive */ | ||
| 61 | /* | ||
| 62 | * queues before re-using a torn-down | ||
| 63 | * receive ring. the DA = | ||
| 64 | * 00-00-00-00-00-00, and the MSB of the | ||
| 65 | * SA != 00 | ||
| 66 | */ | ||
| 67 | #define NULL_MAC (61) /* Promiscuous mode, indicates no match */ | ||
| 68 | #define MCAST_MAC (62) /* Multicast match. */ | ||
| 69 | #define BCAST_MATCH (63) /* Broadcast match. */ | ||
| 70 | |||
| 71 | #endif /* __descriptors_amap_h__ */ | ||
diff --git a/drivers/staging/benet/doorbells.h b/drivers/staging/benet/doorbells.h deleted file mode 100644 index 550cc4d5d6f7..000000000000 --- a/drivers/staging/benet/doorbells.h +++ /dev/null | |||
| @@ -1,179 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __doorbells_amap_h__ | ||
| 21 | #define __doorbells_amap_h__ | ||
| 22 | |||
| 23 | /* The TX/RDMA send queue doorbell. */ | ||
| 24 | struct BE_SQ_DB_AMAP { | ||
| 25 | u8 cid[11]; /* DWORD 0 */ | ||
| 26 | u8 rsvd0[5]; /* DWORD 0 */ | ||
| 27 | u8 numPosted[14]; /* DWORD 0 */ | ||
| 28 | u8 rsvd1[2]; /* DWORD 0 */ | ||
| 29 | } __packed; | ||
| 30 | struct SQ_DB_AMAP { | ||
| 31 | u32 dw[1]; | ||
| 32 | }; | ||
| 33 | |||
| 34 | /* The receive queue doorbell. */ | ||
| 35 | struct BE_RQ_DB_AMAP { | ||
| 36 | u8 rq[10]; /* DWORD 0 */ | ||
| 37 | u8 rsvd0[13]; /* DWORD 0 */ | ||
| 38 | u8 Invalidate; /* DWORD 0 */ | ||
| 39 | u8 numPosted[8]; /* DWORD 0 */ | ||
| 40 | } __packed; | ||
| 41 | struct RQ_DB_AMAP { | ||
| 42 | u32 dw[1]; | ||
| 43 | }; | ||
| 44 | |||
| 45 | /* | ||
| 46 | * The CQ/EQ doorbell. Software MUST set reserved fields in this | ||
| 47 | * descriptor to zero, otherwise (CEV) hardware will not execute the | ||
| 48 | * doorbell (flagging a bad_db_qid error instead). | ||
| 49 | */ | ||
| 50 | struct BE_CQ_DB_AMAP { | ||
| 51 | u8 qid[10]; /* DWORD 0 */ | ||
| 52 | u8 rsvd0[4]; /* DWORD 0 */ | ||
| 53 | u8 rearm; /* DWORD 0 */ | ||
| 54 | u8 event; /* DWORD 0 */ | ||
| 55 | u8 num_popped[13]; /* DWORD 0 */ | ||
| 56 | u8 rsvd1[3]; /* DWORD 0 */ | ||
| 57 | } __packed; | ||
| 58 | struct CQ_DB_AMAP { | ||
| 59 | u32 dw[1]; | ||
| 60 | }; | ||
| 61 | |||
| 62 | struct BE_TPM_RQ_DB_AMAP { | ||
| 63 | u8 qid[10]; /* DWORD 0 */ | ||
| 64 | u8 rsvd0[6]; /* DWORD 0 */ | ||
| 65 | u8 numPosted[11]; /* DWORD 0 */ | ||
| 66 | u8 mss_cnt[5]; /* DWORD 0 */ | ||
| 67 | } __packed; | ||
| 68 | struct TPM_RQ_DB_AMAP { | ||
| 69 | u32 dw[1]; | ||
| 70 | }; | ||
| 71 | |||
| 72 | /* | ||
| 73 | * Post WRB Queue Doorbell Register used by the host Storage stack | ||
| 74 | * to notify the controller of a posted Work Request Block | ||
| 75 | */ | ||
| 76 | struct BE_WRB_POST_DB_AMAP { | ||
| 77 | u8 wrb_cid[10]; /* DWORD 0 */ | ||
| 78 | u8 rsvd0[6]; /* DWORD 0 */ | ||
| 79 | u8 wrb_index[8]; /* DWORD 0 */ | ||
| 80 | u8 numberPosted[8]; /* DWORD 0 */ | ||
| 81 | } __packed; | ||
| 82 | struct WRB_POST_DB_AMAP { | ||
| 83 | u32 dw[1]; | ||
| 84 | }; | ||
| 85 | |||
| 86 | /* | ||
| 87 | * Update Default PDU Queue Doorbell Register used to communicate | ||
| 88 | * to the controller that the driver has stopped processing the queue | ||
| 89 | * and where in the queue it stopped, this is | ||
| 90 | * a CQ Entry Type. Used by storage driver. | ||
| 91 | */ | ||
| 92 | struct BE_DEFAULT_PDU_DB_AMAP { | ||
| 93 | u8 qid[10]; /* DWORD 0 */ | ||
| 94 | u8 rsvd0[4]; /* DWORD 0 */ | ||
| 95 | u8 rearm; /* DWORD 0 */ | ||
| 96 | u8 event; /* DWORD 0 */ | ||
| 97 | u8 cqproc[14]; /* DWORD 0 */ | ||
| 98 | u8 rsvd1[2]; /* DWORD 0 */ | ||
| 99 | } __packed; | ||
| 100 | struct DEFAULT_PDU_DB_AMAP { | ||
| 101 | u32 dw[1]; | ||
| 102 | }; | ||
| 103 | |||
| 104 | /* Management Command and Controller default fragment ring */ | ||
| 105 | struct BE_MCC_DB_AMAP { | ||
| 106 | u8 rid[11]; /* DWORD 0 */ | ||
| 107 | u8 rsvd0[5]; /* DWORD 0 */ | ||
| 108 | u8 numPosted[14]; /* DWORD 0 */ | ||
| 109 | u8 rsvd1[2]; /* DWORD 0 */ | ||
| 110 | } __packed; | ||
| 111 | struct MCC_DB_AMAP { | ||
| 112 | u32 dw[1]; | ||
| 113 | }; | ||
| 114 | |||
| 115 | /* | ||
| 116 | * Used for bootstrapping the Host interface. This register is | ||
| 117 | * used for driver communication with the MPU when no MCC Rings exist. | ||
| 118 | * The software must write this register twice to post any MCC | ||
| 119 | * command. First, it writes the register with hi=1 and the upper bits of | ||
| 120 | * the physical address for the MCC_MAILBOX structure. Software must poll | ||
| 121 | * the ready bit until this is acknowledged. Then, sotware writes the | ||
| 122 | * register with hi=0 with the lower bits in the address. It must | ||
| 123 | * poll the ready bit until the MCC command is complete. Upon completion, | ||
| 124 | * the MCC_MAILBOX will contain a valid completion queue entry. | ||
| 125 | */ | ||
| 126 | struct BE_MPU_MAILBOX_DB_AMAP { | ||
| 127 | u8 ready; /* DWORD 0 */ | ||
| 128 | u8 hi; /* DWORD 0 */ | ||
| 129 | u8 address[30]; /* DWORD 0 */ | ||
| 130 | } __packed; | ||
| 131 | struct MPU_MAILBOX_DB_AMAP { | ||
| 132 | u32 dw[1]; | ||
| 133 | }; | ||
| 134 | |||
| 135 | /* | ||
| 136 | * This is the protection domain doorbell register map. Note that | ||
| 137 | * while this map shows doorbells for all Blade Engine supported | ||
| 138 | * protocols, not all of these may be valid in a given function or | ||
| 139 | * protection domain. It is the responsibility of the application | ||
| 140 | * accessing the doorbells to know which are valid. Each doorbell | ||
| 141 | * occupies 32 bytes of space, but unless otherwise specified, | ||
| 142 | * only the first 4 bytes should be written. There are 32 instances | ||
| 143 | * of these doorbells for the host and 31 virtual machines respectively. | ||
| 144 | * The host and VMs will only map the doorbell pages belonging to its | ||
| 145 | * protection domain. It will not be able to touch the doorbells for | ||
| 146 | * another VM. The doorbells are the only registers directly accessible | ||
| 147 | * by a virtual machine. Similarly, there are 511 additional | ||
| 148 | * doorbells for RDMA protection domains. PD 0 for RDMA shares | ||
| 149 | * the same physical protection domain doorbell page as ETH/iSCSI. | ||
| 150 | * | ||
| 151 | */ | ||
| 152 | struct BE_PROTECTION_DOMAIN_DBMAP_AMAP { | ||
| 153 | u8 rsvd0[512]; /* DWORD 0 */ | ||
| 154 | struct BE_SQ_DB_AMAP rdma_sq_db; | ||
| 155 | u8 rsvd1[7][32]; /* DWORD 17 */ | ||
| 156 | struct BE_WRB_POST_DB_AMAP iscsi_wrb_post_db; | ||
| 157 | u8 rsvd2[7][32]; /* DWORD 25 */ | ||
| 158 | struct BE_SQ_DB_AMAP etx_sq_db; | ||
| 159 | u8 rsvd3[7][32]; /* DWORD 33 */ | ||
| 160 | struct BE_RQ_DB_AMAP rdma_rq_db; | ||
| 161 | u8 rsvd4[7][32]; /* DWORD 41 */ | ||
| 162 | struct BE_DEFAULT_PDU_DB_AMAP iscsi_default_pdu_db; | ||
| 163 | u8 rsvd5[7][32]; /* DWORD 49 */ | ||
| 164 | struct BE_TPM_RQ_DB_AMAP tpm_rq_db; | ||
| 165 | u8 rsvd6[7][32]; /* DWORD 57 */ | ||
| 166 | struct BE_RQ_DB_AMAP erx_rq_db; | ||
| 167 | u8 rsvd7[7][32]; /* DWORD 65 */ | ||
| 168 | struct BE_CQ_DB_AMAP cq_db; | ||
| 169 | u8 rsvd8[7][32]; /* DWORD 73 */ | ||
| 170 | struct BE_MCC_DB_AMAP mpu_mcc_db; | ||
| 171 | u8 rsvd9[7][32]; /* DWORD 81 */ | ||
| 172 | struct BE_MPU_MAILBOX_DB_AMAP mcc_bootstrap_db; | ||
| 173 | u8 rsvd10[935][32]; /* DWORD 89 */ | ||
| 174 | } __packed; | ||
| 175 | struct PROTECTION_DOMAIN_DBMAP_AMAP { | ||
| 176 | u32 dw[1024]; | ||
| 177 | }; | ||
| 178 | |||
| 179 | #endif /* __doorbells_amap_h__ */ | ||
diff --git a/drivers/staging/benet/ep.h b/drivers/staging/benet/ep.h deleted file mode 100644 index 72fcf64a9ffb..000000000000 --- a/drivers/staging/benet/ep.h +++ /dev/null | |||
| @@ -1,66 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __ep_amap_h__ | ||
| 21 | #define __ep_amap_h__ | ||
| 22 | |||
| 23 | /* General Control and Status Register. */ | ||
| 24 | struct BE_EP_CONTROL_CSR_AMAP { | ||
| 25 | u8 m0_RxPbuf; /* DWORD 0 */ | ||
| 26 | u8 m1_RxPbuf; /* DWORD 0 */ | ||
| 27 | u8 m2_RxPbuf; /* DWORD 0 */ | ||
| 28 | u8 ff_en; /* DWORD 0 */ | ||
| 29 | u8 rsvd0[27]; /* DWORD 0 */ | ||
| 30 | u8 CPU_reset; /* DWORD 0 */ | ||
| 31 | } __packed; | ||
| 32 | struct EP_CONTROL_CSR_AMAP { | ||
| 33 | u32 dw[1]; | ||
| 34 | }; | ||
| 35 | |||
| 36 | /* Semaphore Register. */ | ||
| 37 | struct BE_EP_SEMAPHORE_CSR_AMAP { | ||
| 38 | u8 value[32]; /* DWORD 0 */ | ||
| 39 | } __packed; | ||
| 40 | struct EP_SEMAPHORE_CSR_AMAP { | ||
| 41 | u32 dw[1]; | ||
| 42 | }; | ||
| 43 | |||
| 44 | /* Embedded Processor Specific Registers. */ | ||
| 45 | struct BE_EP_CSRMAP_AMAP { | ||
| 46 | struct BE_EP_CONTROL_CSR_AMAP ep_control; | ||
| 47 | u8 rsvd0[32]; /* DWORD 1 */ | ||
| 48 | u8 rsvd1[32]; /* DWORD 2 */ | ||
| 49 | u8 rsvd2[32]; /* DWORD 3 */ | ||
| 50 | u8 rsvd3[32]; /* DWORD 4 */ | ||
| 51 | u8 rsvd4[32]; /* DWORD 5 */ | ||
| 52 | u8 rsvd5[8][128]; /* DWORD 6 */ | ||
| 53 | u8 rsvd6[32]; /* DWORD 38 */ | ||
| 54 | u8 rsvd7[32]; /* DWORD 39 */ | ||
| 55 | u8 rsvd8[32]; /* DWORD 40 */ | ||
| 56 | u8 rsvd9[32]; /* DWORD 41 */ | ||
| 57 | u8 rsvd10[32]; /* DWORD 42 */ | ||
| 58 | struct BE_EP_SEMAPHORE_CSR_AMAP ep_semaphore; | ||
| 59 | u8 rsvd11[32]; /* DWORD 44 */ | ||
| 60 | u8 rsvd12[19][32]; /* DWORD 45 */ | ||
| 61 | } __packed; | ||
| 62 | struct EP_CSRMAP_AMAP { | ||
| 63 | u32 dw[64]; | ||
| 64 | }; | ||
| 65 | |||
| 66 | #endif /* __ep_amap_h__ */ | ||
diff --git a/drivers/staging/benet/eq.c b/drivers/staging/benet/eq.c deleted file mode 100644 index db92ccd8fed8..000000000000 --- a/drivers/staging/benet/eq.c +++ /dev/null | |||
| @@ -1,299 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | #include "hwlib.h" | ||
| 18 | #include "bestatus.h" | ||
| 19 | /* | ||
| 20 | This routine creates an event queue based on the client completion | ||
| 21 | queue configuration information. | ||
| 22 | |||
| 23 | FunctionObject - Handle to a function object | ||
| 24 | EqBaseVa - Base VA for a the EQ ring | ||
| 25 | SizeEncoding - The encoded size for the EQ entries. This value is | ||
| 26 | either CEV_EQ_SIZE_4 or CEV_EQ_SIZE_16 | ||
| 27 | NumEntries - CEV_CQ_CNT_* values. | ||
| 28 | Watermark - Enables watermark based coalescing. This parameter | ||
| 29 | must be of the type CEV_WMARK_* if watermarks | ||
| 30 | are enabled. If watermarks to to be disabled | ||
| 31 | this value should be-1. | ||
| 32 | TimerDelay - If a timer delay is enabled this value should be the | ||
| 33 | time of the delay in 8 microsecond units. If | ||
| 34 | delays are not used this parameter should be | ||
| 35 | set to -1. | ||
| 36 | ppEqObject - Internal EQ Handle returned. | ||
| 37 | |||
| 38 | Returns BE_SUCCESS if successfull,, otherwise a useful error code | ||
| 39 | is returned. | ||
| 40 | |||
| 41 | IRQL < DISPATCH_LEVEL | ||
| 42 | */ | ||
| 43 | int | ||
| 44 | be_eq_create(struct be_function_object *pfob, | ||
| 45 | struct ring_desc *rd, u32 eqe_size, u32 num_entries, | ||
| 46 | u32 watermark, /* CEV_WMARK_* or -1 */ | ||
| 47 | u32 timer_delay, /* in 8us units, or -1 */ | ||
| 48 | struct be_eq_object *eq_object) | ||
| 49 | { | ||
| 50 | int status = BE_SUCCESS; | ||
| 51 | u32 num_entries_encoding, eqe_size_encoding, length; | ||
| 52 | struct FWCMD_COMMON_EQ_CREATE *fwcmd = NULL; | ||
| 53 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 54 | u32 n; | ||
| 55 | unsigned long irql; | ||
| 56 | |||
| 57 | ASSERT(rd); | ||
| 58 | ASSERT(eq_object); | ||
| 59 | |||
| 60 | switch (num_entries) { | ||
| 61 | case 256: | ||
| 62 | num_entries_encoding = CEV_EQ_CNT_256; | ||
| 63 | break; | ||
| 64 | case 512: | ||
| 65 | num_entries_encoding = CEV_EQ_CNT_512; | ||
| 66 | break; | ||
| 67 | case 1024: | ||
| 68 | num_entries_encoding = CEV_EQ_CNT_1024; | ||
| 69 | break; | ||
| 70 | case 2048: | ||
| 71 | num_entries_encoding = CEV_EQ_CNT_2048; | ||
| 72 | break; | ||
| 73 | case 4096: | ||
| 74 | num_entries_encoding = CEV_EQ_CNT_4096; | ||
| 75 | break; | ||
| 76 | default: | ||
| 77 | ASSERT(0); | ||
| 78 | return BE_STATUS_INVALID_PARAMETER; | ||
| 79 | } | ||
| 80 | |||
| 81 | switch (eqe_size) { | ||
| 82 | case 4: | ||
| 83 | eqe_size_encoding = CEV_EQ_SIZE_4; | ||
| 84 | break; | ||
| 85 | case 16: | ||
| 86 | eqe_size_encoding = CEV_EQ_SIZE_16; | ||
| 87 | break; | ||
| 88 | default: | ||
| 89 | ASSERT(0); | ||
| 90 | return BE_STATUS_INVALID_PARAMETER; | ||
| 91 | } | ||
| 92 | |||
| 93 | if ((eqe_size == 4 && num_entries < 1024) || | ||
| 94 | (eqe_size == 16 && num_entries == 4096)) { | ||
| 95 | TRACE(DL_ERR, "Bad EQ size. eqe_size:%d num_entries:%d", | ||
| 96 | eqe_size, num_entries); | ||
| 97 | ASSERT(0); | ||
| 98 | return BE_STATUS_INVALID_PARAMETER; | ||
| 99 | } | ||
| 100 | |||
| 101 | memset(eq_object, 0, sizeof(*eq_object)); | ||
| 102 | |||
| 103 | atomic_set(&eq_object->ref_count, 0); | ||
| 104 | eq_object->parent_function = pfob; | ||
| 105 | eq_object->eq_id = 0xFFFFFFFF; | ||
| 106 | |||
| 107 | INIT_LIST_HEAD(&eq_object->cq_list_head); | ||
| 108 | |||
| 109 | length = num_entries * eqe_size; | ||
| 110 | |||
| 111 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 112 | |||
| 113 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 114 | if (!wrb) { | ||
| 115 | ASSERT(wrb); | ||
| 116 | TRACE(DL_ERR, "No free MCC WRBs in create EQ."); | ||
| 117 | status = BE_STATUS_NO_MCC_WRB; | ||
| 118 | goto Error; | ||
| 119 | } | ||
| 120 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 121 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_EQ_CREATE); | ||
| 122 | |||
| 123 | fwcmd->params.request.num_pages = PAGES_SPANNED(OFFSET_IN_PAGE(rd->va), | ||
| 124 | length); | ||
| 125 | n = pfob->pci_function_number; | ||
| 126 | AMAP_SET_BITS_PTR(EQ_CONTEXT, Func, &fwcmd->params.request.context, n); | ||
| 127 | |||
| 128 | AMAP_SET_BITS_PTR(EQ_CONTEXT, valid, &fwcmd->params.request.context, 1); | ||
| 129 | |||
| 130 | AMAP_SET_BITS_PTR(EQ_CONTEXT, Size, | ||
| 131 | &fwcmd->params.request.context, eqe_size_encoding); | ||
| 132 | |||
| 133 | n = 0; /* Protection Domain is always 0 in Linux driver */ | ||
| 134 | AMAP_SET_BITS_PTR(EQ_CONTEXT, PD, &fwcmd->params.request.context, n); | ||
| 135 | |||
| 136 | /* Let the caller ARM the EQ with the doorbell. */ | ||
| 137 | AMAP_SET_BITS_PTR(EQ_CONTEXT, Armed, &fwcmd->params.request.context, 0); | ||
| 138 | |||
| 139 | AMAP_SET_BITS_PTR(EQ_CONTEXT, Count, &fwcmd->params.request.context, | ||
| 140 | num_entries_encoding); | ||
| 141 | |||
| 142 | n = pfob->pci_function_number * 32; | ||
| 143 | AMAP_SET_BITS_PTR(EQ_CONTEXT, EventVect, | ||
| 144 | &fwcmd->params.request.context, n); | ||
| 145 | if (watermark != -1) { | ||
| 146 | AMAP_SET_BITS_PTR(EQ_CONTEXT, WME, | ||
| 147 | &fwcmd->params.request.context, 1); | ||
| 148 | AMAP_SET_BITS_PTR(EQ_CONTEXT, Watermark, | ||
| 149 | &fwcmd->params.request.context, watermark); | ||
| 150 | ASSERT(watermark <= CEV_WMARK_240); | ||
| 151 | } else | ||
| 152 | AMAP_SET_BITS_PTR(EQ_CONTEXT, WME, | ||
| 153 | &fwcmd->params.request.context, 0); | ||
| 154 | if (timer_delay != -1) { | ||
| 155 | AMAP_SET_BITS_PTR(EQ_CONTEXT, TMR, | ||
| 156 | &fwcmd->params.request.context, 1); | ||
| 157 | |||
| 158 | ASSERT(timer_delay <= 250); /* max value according to EAS */ | ||
| 159 | timer_delay = min(timer_delay, (u32)250); | ||
| 160 | |||
| 161 | AMAP_SET_BITS_PTR(EQ_CONTEXT, Delay, | ||
| 162 | &fwcmd->params.request.context, timer_delay); | ||
| 163 | } else { | ||
| 164 | AMAP_SET_BITS_PTR(EQ_CONTEXT, TMR, | ||
| 165 | &fwcmd->params.request.context, 0); | ||
| 166 | } | ||
| 167 | /* Create a page list for the FWCMD. */ | ||
| 168 | be_rd_to_pa_list(rd, fwcmd->params.request.pages, | ||
| 169 | ARRAY_SIZE(fwcmd->params.request.pages)); | ||
| 170 | |||
| 171 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, NULL, NULL, | ||
| 172 | NULL, NULL, fwcmd, NULL); | ||
| 173 | if (status != BE_SUCCESS) { | ||
| 174 | TRACE(DL_ERR, "MCC to create EQ failed."); | ||
| 175 | goto Error; | ||
| 176 | } | ||
| 177 | /* Get the EQ id. The MPU allocates the IDs. */ | ||
| 178 | eq_object->eq_id = fwcmd->params.response.eq_id; | ||
| 179 | |||
| 180 | Error: | ||
| 181 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 182 | |||
| 183 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 184 | pfob->pend_queue_driving = 0; | ||
| 185 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 186 | } | ||
| 187 | return status; | ||
| 188 | } | ||
| 189 | |||
| 190 | /* | ||
| 191 | Deferences the given object. Once the object's reference count drops to | ||
| 192 | zero, the object is destroyed and all resources that are held by this | ||
| 193 | object are released. The on-chip context is also destroyed along with | ||
| 194 | the queue ID, and any mappings made into the UT. | ||
| 195 | |||
| 196 | eq_object - EQ handle returned from eq_object_create. | ||
| 197 | |||
| 198 | Returns BE_SUCCESS if successfull, otherwise a useful error code | ||
| 199 | is returned. | ||
| 200 | |||
| 201 | IRQL: IRQL < DISPATCH_LEVEL | ||
| 202 | */ | ||
| 203 | int be_eq_destroy(struct be_eq_object *eq_object) | ||
| 204 | { | ||
| 205 | int status = 0; | ||
| 206 | |||
| 207 | ASSERT(atomic_read(&eq_object->ref_count) == 0); | ||
| 208 | /* no CQs should reference this EQ now */ | ||
| 209 | ASSERT(list_empty(&eq_object->cq_list_head)); | ||
| 210 | |||
| 211 | /* Send fwcmd to destroy the EQ. */ | ||
| 212 | status = be_function_ring_destroy(eq_object->parent_function, | ||
| 213 | eq_object->eq_id, FWCMD_RING_TYPE_EQ, | ||
| 214 | NULL, NULL, NULL, NULL); | ||
| 215 | ASSERT(status == 0); | ||
| 216 | |||
| 217 | return BE_SUCCESS; | ||
| 218 | } | ||
| 219 | /* | ||
| 220 | *--------------------------------------------------------------------------- | ||
| 221 | * Function: be_eq_modify_delay | ||
| 222 | * Changes the EQ delay for a group of EQs. | ||
| 223 | * num_eq - The number of EQs in the eq_array to adjust. | ||
| 224 | * This also is the number of delay values in | ||
| 225 | * the eq_delay_array. | ||
| 226 | * eq_array - Array of struct be_eq_object pointers to adjust. | ||
| 227 | * eq_delay_array - Array of "num_eq" timer delays in units | ||
| 228 | * of microseconds. The be_eq_query_delay_range | ||
| 229 | * fwcmd returns the resolution and range of | ||
| 230 | * legal EQ delays. | ||
| 231 | * cb - | ||
| 232 | * cb_context - | ||
| 233 | * q_ctxt - Optional. Pointer to a previously allocated | ||
| 234 | * struct. If the MCC WRB ring is full, this | ||
| 235 | * structure is used to queue the operation. It | ||
| 236 | * will be posted to the MCC ring when space | ||
| 237 | * becomes available. All queued commands will | ||
| 238 | * be posted to the ring in the order they are | ||
| 239 | * received. It is always valid to pass a pointer to | ||
| 240 | * a generic be_generic_q_cntxt. However, | ||
| 241 | * the specific context structs | ||
| 242 | * are generally smaller than the generic struct. | ||
| 243 | * return pend_status - BE_SUCCESS (0) on success. | ||
| 244 | * BE_PENDING (postive value) if the FWCMD | ||
| 245 | * completion is pending. Negative error code on failure. | ||
| 246 | *------------------------------------------------------------------------- | ||
| 247 | */ | ||
| 248 | int | ||
| 249 | be_eq_modify_delay(struct be_function_object *pfob, | ||
| 250 | u32 num_eq, struct be_eq_object **eq_array, | ||
| 251 | u32 *eq_delay_array, mcc_wrb_cqe_callback cb, | ||
| 252 | void *cb_context, struct be_eq_modify_delay_q_ctxt *q_ctxt) | ||
| 253 | { | ||
| 254 | struct FWCMD_COMMON_MODIFY_EQ_DELAY *fwcmd = NULL; | ||
| 255 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 256 | int status = 0; | ||
| 257 | struct be_generic_q_ctxt *gen_ctxt = NULL; | ||
| 258 | u32 i; | ||
| 259 | unsigned long irql; | ||
| 260 | |||
| 261 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 262 | |||
| 263 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 264 | if (!wrb) { | ||
| 265 | if (q_ctxt && cb) { | ||
| 266 | wrb = (struct MCC_WRB_AMAP *) &q_ctxt->wrb_header; | ||
| 267 | gen_ctxt = (struct be_generic_q_ctxt *) q_ctxt; | ||
| 268 | gen_ctxt->context.bytes = sizeof(*q_ctxt); | ||
| 269 | } else { | ||
| 270 | status = BE_STATUS_NO_MCC_WRB; | ||
| 271 | goto Error; | ||
| 272 | } | ||
| 273 | } | ||
| 274 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 275 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_MODIFY_EQ_DELAY); | ||
| 276 | |||
| 277 | ASSERT(num_eq > 0); | ||
| 278 | ASSERT(num_eq <= ARRAY_SIZE(fwcmd->params.request.delay)); | ||
| 279 | fwcmd->params.request.num_eq = num_eq; | ||
| 280 | for (i = 0; i < num_eq; i++) { | ||
| 281 | fwcmd->params.request.delay[i].eq_id = eq_array[i]->eq_id; | ||
| 282 | fwcmd->params.request.delay[i].delay_in_microseconds = | ||
| 283 | eq_delay_array[i]; | ||
| 284 | } | ||
| 285 | |||
| 286 | /* Post the f/w command */ | ||
| 287 | status = be_function_post_mcc_wrb(pfob, wrb, gen_ctxt, | ||
| 288 | cb, cb_context, NULL, NULL, fwcmd, NULL); | ||
| 289 | |||
| 290 | Error: | ||
| 291 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 292 | |||
| 293 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 294 | pfob->pend_queue_driving = 0; | ||
| 295 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 296 | } | ||
| 297 | return status; | ||
| 298 | } | ||
| 299 | |||
diff --git a/drivers/staging/benet/eth.c b/drivers/staging/benet/eth.c deleted file mode 100644 index f641b6260d07..000000000000 --- a/drivers/staging/benet/eth.c +++ /dev/null | |||
| @@ -1,1273 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | #include <linux/if_ether.h> | ||
| 18 | #include "hwlib.h" | ||
| 19 | #include "bestatus.h" | ||
| 20 | |||
| 21 | /* | ||
| 22 | *--------------------------------------------------------- | ||
| 23 | * Function: be_eth_sq_create_ex | ||
| 24 | * Creates an ethernet send ring - extended version with | ||
| 25 | * additional parameters. | ||
| 26 | * pfob - | ||
| 27 | * rd - ring address | ||
| 28 | * length_in_bytes - | ||
| 29 | * type - The type of ring to create. | ||
| 30 | * ulp - The requested ULP number for the ring. | ||
| 31 | * This should be zero based, i.e. 0,1,2. This must | ||
| 32 | * be valid NIC ULP based on the firmware config. | ||
| 33 | * All doorbells for this ring must be sent to | ||
| 34 | * this ULP. The first network ring allocated for | ||
| 35 | * each ULP are higher performance than subsequent rings. | ||
| 36 | * cq_object - cq object for completions | ||
| 37 | * ex_parameters - Additional parameters (that may increase in | ||
| 38 | * future revisions). These parameters are only used | ||
| 39 | * for certain ring types -- see | ||
| 40 | * struct be_eth_sq_parameters for details. | ||
| 41 | * eth_sq - | ||
| 42 | * return status - BE_SUCCESS (0) on success. Negative error code on failure. | ||
| 43 | *--------------------------------------------------------- | ||
| 44 | */ | ||
| 45 | int | ||
| 46 | be_eth_sq_create_ex(struct be_function_object *pfob, struct ring_desc *rd, | ||
| 47 | u32 length, u32 type, u32 ulp, struct be_cq_object *cq_object, | ||
| 48 | struct be_eth_sq_parameters *ex_parameters, | ||
| 49 | struct be_ethsq_object *eth_sq) | ||
| 50 | { | ||
| 51 | struct FWCMD_COMMON_ETH_TX_CREATE *fwcmd = NULL; | ||
| 52 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 53 | int status = 0; | ||
| 54 | u32 n; | ||
| 55 | unsigned long irql; | ||
| 56 | |||
| 57 | ASSERT(rd); | ||
| 58 | ASSERT(eth_sq); | ||
| 59 | ASSERT(ex_parameters); | ||
| 60 | |||
| 61 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 62 | |||
| 63 | memset(eth_sq, 0, sizeof(*eth_sq)); | ||
| 64 | |||
| 65 | eth_sq->parent_function = pfob; | ||
| 66 | eth_sq->bid = 0xFFFFFFFF; | ||
| 67 | eth_sq->cq_object = cq_object; | ||
| 68 | |||
| 69 | /* Translate hwlib interface to arm interface. */ | ||
| 70 | switch (type) { | ||
| 71 | case BE_ETH_TX_RING_TYPE_FORWARDING: | ||
| 72 | type = ETH_TX_RING_TYPE_FORWARDING; | ||
| 73 | break; | ||
| 74 | case BE_ETH_TX_RING_TYPE_STANDARD: | ||
| 75 | type = ETH_TX_RING_TYPE_STANDARD; | ||
| 76 | break; | ||
| 77 | case BE_ETH_TX_RING_TYPE_BOUND: | ||
| 78 | ASSERT(ex_parameters->port < 2); | ||
| 79 | type = ETH_TX_RING_TYPE_BOUND; | ||
| 80 | break; | ||
| 81 | default: | ||
| 82 | TRACE(DL_ERR, "Invalid eth tx ring type:%d", type); | ||
| 83 | return BE_NOT_OK; | ||
| 84 | break; | ||
| 85 | } | ||
| 86 | |||
| 87 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 88 | if (!wrb) { | ||
| 89 | ASSERT(wrb); | ||
| 90 | TRACE(DL_ERR, "No free MCC WRBs in create EQ."); | ||
| 91 | status = BE_STATUS_NO_MCC_WRB; | ||
| 92 | goto Error; | ||
| 93 | } | ||
| 94 | /* NIC must be supported by the current config. */ | ||
| 95 | ASSERT(pfob->fw_config.nic_ulp_mask); | ||
| 96 | |||
| 97 | /* | ||
| 98 | * The ulp parameter must select a valid NIC ULP | ||
| 99 | * for the current config. | ||
| 100 | */ | ||
| 101 | ASSERT((1 << ulp) & pfob->fw_config.nic_ulp_mask); | ||
| 102 | |||
| 103 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 104 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_ETH_TX_CREATE); | ||
| 105 | fwcmd->header.request.port_number = ex_parameters->port; | ||
| 106 | |||
| 107 | AMAP_SET_BITS_PTR(ETX_CONTEXT, pd_id, | ||
| 108 | &fwcmd->params.request.context, 0); | ||
| 109 | |||
| 110 | n = be_ring_length_to_encoding(length, sizeof(struct ETH_WRB_AMAP)); | ||
| 111 | AMAP_SET_BITS_PTR(ETX_CONTEXT, tx_ring_size, | ||
| 112 | &fwcmd->params.request.context, n); | ||
| 113 | |||
| 114 | AMAP_SET_BITS_PTR(ETX_CONTEXT, cq_id_send, | ||
| 115 | &fwcmd->params.request.context, cq_object->cq_id); | ||
| 116 | |||
| 117 | n = pfob->pci_function_number; | ||
| 118 | AMAP_SET_BITS_PTR(ETX_CONTEXT, func, &fwcmd->params.request.context, n); | ||
| 119 | |||
| 120 | fwcmd->params.request.type = type; | ||
| 121 | fwcmd->params.request.ulp_num = (1 << ulp); | ||
| 122 | fwcmd->params.request.num_pages = DIV_ROUND_UP(length, PAGE_SIZE); | ||
| 123 | ASSERT(PAGES_SPANNED(rd->va, rd->length) >= | ||
| 124 | fwcmd->params.request.num_pages); | ||
| 125 | |||
| 126 | /* Create a page list for the FWCMD. */ | ||
| 127 | be_rd_to_pa_list(rd, fwcmd->params.request.pages, | ||
| 128 | ARRAY_SIZE(fwcmd->params.request.pages)); | ||
| 129 | |||
| 130 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, NULL, NULL, | ||
| 131 | NULL, NULL, fwcmd, NULL); | ||
| 132 | if (status != BE_SUCCESS) { | ||
| 133 | TRACE(DL_ERR, "MCC to create etx queue failed."); | ||
| 134 | goto Error; | ||
| 135 | } | ||
| 136 | /* save the butler ID */ | ||
| 137 | eth_sq->bid = fwcmd->params.response.cid; | ||
| 138 | |||
| 139 | /* add a reference to the corresponding CQ */ | ||
| 140 | atomic_inc(&cq_object->ref_count); | ||
| 141 | |||
| 142 | Error: | ||
| 143 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 144 | |||
| 145 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 146 | pfob->pend_queue_driving = 0; | ||
| 147 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 148 | } | ||
| 149 | return status; | ||
| 150 | } | ||
| 151 | |||
| 152 | |||
| 153 | /* | ||
| 154 | This routine destroys an ethernet send queue | ||
| 155 | |||
| 156 | EthSq - EthSq Handle returned from EthSqCreate | ||
| 157 | |||
| 158 | This function always return BE_SUCCESS. | ||
| 159 | |||
| 160 | This function frees memory allocated by EthSqCreate for the EthSq Object. | ||
| 161 | |||
| 162 | */ | ||
| 163 | int be_eth_sq_destroy(struct be_ethsq_object *eth_sq) | ||
| 164 | { | ||
| 165 | int status = 0; | ||
| 166 | |||
| 167 | /* Send fwcmd to destroy the queue. */ | ||
| 168 | status = be_function_ring_destroy(eth_sq->parent_function, eth_sq->bid, | ||
| 169 | FWCMD_RING_TYPE_ETH_TX, NULL, NULL, NULL, NULL); | ||
| 170 | ASSERT(status == 0); | ||
| 171 | |||
| 172 | /* Derefence any associated CQs. */ | ||
| 173 | atomic_dec(ð_sq->cq_object->ref_count); | ||
| 174 | return status; | ||
| 175 | } | ||
| 176 | /* | ||
| 177 | This routine attempts to set the transmit flow control parameters. | ||
| 178 | |||
| 179 | FunctionObject - Handle to a function object | ||
| 180 | |||
| 181 | txfc_enable - transmit flow control enable - true for | ||
| 182 | enable, false for disable | ||
| 183 | |||
| 184 | rxfc_enable - receive flow control enable - true for | ||
| 185 | enable, false for disable | ||
| 186 | |||
| 187 | Returns BE_SUCCESS if successfull, otherwise a useful int error | ||
| 188 | code is returned. | ||
| 189 | |||
| 190 | IRQL: < DISPATCH_LEVEL | ||
| 191 | |||
| 192 | This function always fails in non-privileged machine context. | ||
| 193 | */ | ||
| 194 | int | ||
| 195 | be_eth_set_flow_control(struct be_function_object *pfob, | ||
| 196 | bool txfc_enable, bool rxfc_enable) | ||
| 197 | { | ||
| 198 | struct FWCMD_COMMON_SET_FLOW_CONTROL *fwcmd = NULL; | ||
| 199 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 200 | int status = 0; | ||
| 201 | unsigned long irql; | ||
| 202 | |||
| 203 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 204 | |||
| 205 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 206 | if (!wrb) { | ||
| 207 | TRACE(DL_ERR, "MCC wrb peek failed."); | ||
| 208 | status = BE_STATUS_NO_MCC_WRB; | ||
| 209 | goto error; | ||
| 210 | } | ||
| 211 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 212 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_SET_FLOW_CONTROL); | ||
| 213 | |||
| 214 | fwcmd->params.request.rx_flow_control = rxfc_enable; | ||
| 215 | fwcmd->params.request.tx_flow_control = txfc_enable; | ||
| 216 | |||
| 217 | /* Post the f/w command */ | ||
| 218 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, NULL, NULL, | ||
| 219 | NULL, NULL, fwcmd, NULL); | ||
| 220 | |||
| 221 | if (status != 0) { | ||
| 222 | TRACE(DL_ERR, "set flow control fwcmd failed."); | ||
| 223 | goto error; | ||
| 224 | } | ||
| 225 | |||
| 226 | error: | ||
| 227 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 228 | |||
| 229 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 230 | pfob->pend_queue_driving = 0; | ||
| 231 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 232 | } | ||
| 233 | return status; | ||
| 234 | } | ||
| 235 | |||
| 236 | /* | ||
| 237 | This routine attempts to get the transmit flow control parameters. | ||
| 238 | |||
| 239 | pfob - Handle to a function object | ||
| 240 | |||
| 241 | txfc_enable - transmit flow control enable - true for | ||
| 242 | enable, false for disable | ||
| 243 | |||
| 244 | rxfc_enable - receive flow control enable - true for enable, | ||
| 245 | false for disable | ||
| 246 | |||
| 247 | Returns BE_SUCCESS if successfull, otherwise a useful int error code | ||
| 248 | is returned. | ||
| 249 | |||
| 250 | IRQL: < DISPATCH_LEVEL | ||
| 251 | |||
| 252 | This function always fails in non-privileged machine context. | ||
| 253 | */ | ||
| 254 | int | ||
| 255 | be_eth_get_flow_control(struct be_function_object *pfob, | ||
| 256 | bool *txfc_enable, bool *rxfc_enable) | ||
| 257 | { | ||
| 258 | struct FWCMD_COMMON_GET_FLOW_CONTROL *fwcmd = NULL; | ||
| 259 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 260 | int status = 0; | ||
| 261 | unsigned long irql; | ||
| 262 | |||
| 263 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 264 | |||
| 265 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 266 | if (!wrb) { | ||
| 267 | TRACE(DL_ERR, "MCC wrb peek failed."); | ||
| 268 | status = BE_STATUS_NO_MCC_WRB; | ||
| 269 | goto error; | ||
| 270 | } | ||
| 271 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 272 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_GET_FLOW_CONTROL); | ||
| 273 | |||
| 274 | /* Post the f/w command */ | ||
| 275 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, NULL, NULL, | ||
| 276 | NULL, NULL, fwcmd, NULL); | ||
| 277 | |||
| 278 | if (status != 0) { | ||
| 279 | TRACE(DL_ERR, "get flow control fwcmd failed."); | ||
| 280 | goto error; | ||
| 281 | } | ||
| 282 | |||
| 283 | *txfc_enable = fwcmd->params.response.tx_flow_control; | ||
| 284 | *rxfc_enable = fwcmd->params.response.rx_flow_control; | ||
| 285 | |||
| 286 | error: | ||
| 287 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 288 | |||
| 289 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 290 | pfob->pend_queue_driving = 0; | ||
| 291 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 292 | } | ||
| 293 | return status; | ||
| 294 | } | ||
| 295 | |||
| 296 | /* | ||
| 297 | *--------------------------------------------------------- | ||
| 298 | * Function: be_eth_set_qos | ||
| 299 | * This function sets the ethernet transmit Quality of Service (QoS) | ||
| 300 | * characteristics of BladeEngine for the domain. All ethernet | ||
| 301 | * transmit rings of the domain will evenly share the bandwidth. | ||
| 302 | * The exeception to sharing is the host primary (super) ethernet | ||
| 303 | * transmit ring as well as the host ethernet forwarding ring | ||
| 304 | * for missed offload data. | ||
| 305 | * pfob - | ||
| 306 | * max_bps - the maximum bits per second in units of | ||
| 307 | * 10 Mbps (valid 0-100) | ||
| 308 | * max_pps - the maximum packets per second in units | ||
| 309 | * of 1 Kpps (0 indicates no limit) | ||
| 310 | * return status - BE_SUCCESS (0) on success. Negative error code on failure. | ||
| 311 | *--------------------------------------------------------- | ||
| 312 | */ | ||
| 313 | int | ||
| 314 | be_eth_set_qos(struct be_function_object *pfob, u32 max_bps, u32 max_pps) | ||
| 315 | { | ||
| 316 | struct FWCMD_COMMON_SET_QOS *fwcmd = NULL; | ||
| 317 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 318 | int status = 0; | ||
| 319 | unsigned long irql; | ||
| 320 | |||
| 321 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 322 | |||
| 323 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 324 | if (!wrb) { | ||
| 325 | TRACE(DL_ERR, "MCC wrb peek failed."); | ||
| 326 | status = BE_STATUS_NO_MCC_WRB; | ||
| 327 | goto error; | ||
| 328 | } | ||
| 329 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 330 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_SET_QOS); | ||
| 331 | |||
| 332 | /* Set fields in fwcmd */ | ||
| 333 | fwcmd->params.request.max_bits_per_second_NIC = max_bps; | ||
| 334 | fwcmd->params.request.max_packets_per_second_NIC = max_pps; | ||
| 335 | fwcmd->params.request.valid_flags = QOS_BITS_NIC | QOS_PKTS_NIC; | ||
| 336 | |||
| 337 | /* Post the f/w command */ | ||
| 338 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, NULL, NULL, | ||
| 339 | NULL, NULL, fwcmd, NULL); | ||
| 340 | |||
| 341 | if (status != 0) | ||
| 342 | TRACE(DL_ERR, "network set qos fwcmd failed."); | ||
| 343 | |||
| 344 | error: | ||
| 345 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 346 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 347 | pfob->pend_queue_driving = 0; | ||
| 348 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 349 | } | ||
| 350 | return status; | ||
| 351 | } | ||
| 352 | |||
| 353 | /* | ||
| 354 | *--------------------------------------------------------- | ||
| 355 | * Function: be_eth_get_qos | ||
| 356 | * This function retrieves the ethernet transmit Quality of Service (QoS) | ||
| 357 | * characteristics for the domain. | ||
| 358 | * max_bps - the maximum bits per second in units of | ||
| 359 | * 10 Mbps (valid 0-100) | ||
| 360 | * max_pps - the maximum packets per second in units of | ||
| 361 | * 1 Kpps (0 indicates no limit) | ||
| 362 | * return status - BE_SUCCESS (0) on success. Negative error code on failure. | ||
| 363 | *--------------------------------------------------------- | ||
| 364 | */ | ||
| 365 | int | ||
| 366 | be_eth_get_qos(struct be_function_object *pfob, u32 *max_bps, u32 *max_pps) | ||
| 367 | { | ||
| 368 | struct FWCMD_COMMON_GET_QOS *fwcmd = NULL; | ||
| 369 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 370 | int status = 0; | ||
| 371 | unsigned long irql; | ||
| 372 | |||
| 373 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 374 | |||
| 375 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 376 | if (!wrb) { | ||
| 377 | TRACE(DL_ERR, "MCC wrb peek failed."); | ||
| 378 | status = BE_STATUS_NO_MCC_WRB; | ||
| 379 | goto error; | ||
| 380 | } | ||
| 381 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 382 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_GET_QOS); | ||
| 383 | |||
| 384 | /* Post the f/w command */ | ||
| 385 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, NULL, NULL, | ||
| 386 | NULL, NULL, fwcmd, NULL); | ||
| 387 | |||
| 388 | if (status != 0) { | ||
| 389 | TRACE(DL_ERR, "network get qos fwcmd failed."); | ||
| 390 | goto error; | ||
| 391 | } | ||
| 392 | |||
| 393 | *max_bps = fwcmd->params.response.max_bits_per_second_NIC; | ||
| 394 | *max_pps = fwcmd->params.response.max_packets_per_second_NIC; | ||
| 395 | |||
| 396 | error: | ||
| 397 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 398 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 399 | pfob->pend_queue_driving = 0; | ||
| 400 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 401 | } | ||
| 402 | return status; | ||
| 403 | } | ||
| 404 | |||
| 405 | /* | ||
| 406 | *--------------------------------------------------------- | ||
| 407 | * Function: be_eth_set_frame_size | ||
| 408 | * This function sets the ethernet maximum frame size. The previous | ||
| 409 | * values are returned. | ||
| 410 | * pfob - | ||
| 411 | * tx_frame_size - maximum transmit frame size in bytes | ||
| 412 | * rx_frame_size - maximum receive frame size in bytes | ||
| 413 | * return status - BE_SUCCESS (0) on success. Negative error code on failure. | ||
| 414 | *--------------------------------------------------------- | ||
| 415 | */ | ||
| 416 | int | ||
| 417 | be_eth_set_frame_size(struct be_function_object *pfob, | ||
| 418 | u32 *tx_frame_size, u32 *rx_frame_size) | ||
| 419 | { | ||
| 420 | struct FWCMD_COMMON_SET_FRAME_SIZE *fwcmd = NULL; | ||
| 421 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 422 | int status = 0; | ||
| 423 | unsigned long irql; | ||
| 424 | |||
| 425 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 426 | |||
| 427 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 428 | if (!wrb) { | ||
| 429 | TRACE(DL_ERR, "MCC wrb peek failed."); | ||
| 430 | status = BE_STATUS_NO_MCC_WRB; | ||
| 431 | goto error; | ||
| 432 | } | ||
| 433 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 434 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_SET_FRAME_SIZE); | ||
| 435 | fwcmd->params.request.max_tx_frame_size = *tx_frame_size; | ||
| 436 | fwcmd->params.request.max_rx_frame_size = *rx_frame_size; | ||
| 437 | |||
| 438 | /* Post the f/w command */ | ||
| 439 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, NULL, NULL, | ||
| 440 | NULL, NULL, fwcmd, NULL); | ||
| 441 | |||
| 442 | if (status != 0) { | ||
| 443 | TRACE(DL_ERR, "network set frame size fwcmd failed."); | ||
| 444 | goto error; | ||
| 445 | } | ||
| 446 | |||
| 447 | *tx_frame_size = fwcmd->params.response.chip_max_tx_frame_size; | ||
| 448 | *rx_frame_size = fwcmd->params.response.chip_max_rx_frame_size; | ||
| 449 | |||
| 450 | error: | ||
| 451 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 452 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 453 | pfob->pend_queue_driving = 0; | ||
| 454 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 455 | } | ||
| 456 | return status; | ||
| 457 | } | ||
| 458 | |||
| 459 | |||
| 460 | /* | ||
| 461 | This routine creates a Ethernet receive ring. | ||
| 462 | |||
| 463 | pfob - handle to a function object | ||
| 464 | rq_base_va - base VA for the default receive ring. this must be | ||
| 465 | exactly 8K in length and continguous physical memory. | ||
| 466 | cq_object - handle to a previously created CQ to be associated | ||
| 467 | with the RQ. | ||
| 468 | pp_eth_rq - pointer to an opqaue handle where an eth | ||
| 469 | receive object is returned. | ||
| 470 | Returns BE_SUCCESS if successfull, , otherwise a useful | ||
| 471 | int error code is returned. | ||
| 472 | |||
| 473 | IRQL: < DISPATCH_LEVEL | ||
| 474 | this function allocates a struct be_ethrq_object *object. | ||
| 475 | there must be no more than 1 of these per function object, unless the | ||
| 476 | function object supports RSS (is networking and on the host). | ||
| 477 | the rq_base_va must point to a buffer of exactly 8K. | ||
| 478 | the erx::host_cqid (or host_stor_cqid) register and erx::ring_page registers | ||
| 479 | will be updated as appropriate on return | ||
| 480 | */ | ||
| 481 | int | ||
| 482 | be_eth_rq_create(struct be_function_object *pfob, | ||
| 483 | struct ring_desc *rd, struct be_cq_object *cq_object, | ||
| 484 | struct be_cq_object *bcmc_cq_object, | ||
| 485 | struct be_ethrq_object *eth_rq) | ||
| 486 | { | ||
| 487 | int status = 0; | ||
| 488 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 489 | struct FWCMD_COMMON_ETH_RX_CREATE *fwcmd = NULL; | ||
| 490 | unsigned long irql; | ||
| 491 | |||
| 492 | /* MPU will set the */ | ||
| 493 | ASSERT(rd); | ||
| 494 | ASSERT(eth_rq); | ||
| 495 | |||
| 496 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 497 | |||
| 498 | eth_rq->parent_function = pfob; | ||
| 499 | eth_rq->cq_object = cq_object; | ||
| 500 | |||
| 501 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 502 | if (!wrb) { | ||
| 503 | TRACE(DL_ERR, "MCC wrb peek failed."); | ||
| 504 | status = BE_STATUS_NO_MCC_WRB; | ||
| 505 | goto Error; | ||
| 506 | } | ||
| 507 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 508 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_ETH_RX_CREATE); | ||
| 509 | |||
| 510 | fwcmd->params.request.num_pages = 2; /* required length */ | ||
| 511 | fwcmd->params.request.cq_id = cq_object->cq_id; | ||
| 512 | |||
| 513 | if (bcmc_cq_object) | ||
| 514 | fwcmd->params.request.bcmc_cq_id = bcmc_cq_object->cq_id; | ||
| 515 | else | ||
| 516 | fwcmd->params.request.bcmc_cq_id = 0xFFFF; | ||
| 517 | |||
| 518 | /* Create a page list for the FWCMD. */ | ||
| 519 | be_rd_to_pa_list(rd, fwcmd->params.request.pages, | ||
| 520 | ARRAY_SIZE(fwcmd->params.request.pages)); | ||
| 521 | |||
| 522 | /* Post the f/w command */ | ||
| 523 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, NULL, NULL, | ||
| 524 | NULL, NULL, fwcmd, NULL); | ||
| 525 | if (status != BE_SUCCESS) { | ||
| 526 | TRACE(DL_ERR, "fwcmd to map eth rxq frags failed."); | ||
| 527 | goto Error; | ||
| 528 | } | ||
| 529 | /* Save the ring ID for cleanup. */ | ||
| 530 | eth_rq->rid = fwcmd->params.response.id; | ||
| 531 | |||
| 532 | atomic_inc(&cq_object->ref_count); | ||
| 533 | |||
| 534 | Error: | ||
| 535 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 536 | |||
| 537 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 538 | pfob->pend_queue_driving = 0; | ||
| 539 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 540 | } | ||
| 541 | return status; | ||
| 542 | } | ||
| 543 | |||
| 544 | /* | ||
| 545 | This routine destroys an Ethernet receive queue | ||
| 546 | |||
| 547 | eth_rq - ethernet receive queue handle returned from eth_rq_create | ||
| 548 | |||
| 549 | Returns BE_SUCCESS on success and an appropriate int on failure. | ||
| 550 | |||
| 551 | This function frees resourcs allocated by EthRqCreate. | ||
| 552 | The erx::host_cqid (or host_stor_cqid) register and erx::ring_page | ||
| 553 | registers will be updated as appropriate on return | ||
| 554 | IRQL: < DISPATCH_LEVEL | ||
| 555 | */ | ||
| 556 | |||
| 557 | static void be_eth_rq_destroy_internal_cb(void *context, int status, | ||
| 558 | struct MCC_WRB_AMAP *wrb) | ||
| 559 | { | ||
| 560 | struct be_ethrq_object *eth_rq = (struct be_ethrq_object *) context; | ||
| 561 | |||
| 562 | if (status != BE_SUCCESS) { | ||
| 563 | TRACE(DL_ERR, "Destroy eth rq failed in internal callback.\n"); | ||
| 564 | } else { | ||
| 565 | /* Dereference any CQs associated with this queue. */ | ||
| 566 | atomic_dec(ð_rq->cq_object->ref_count); | ||
| 567 | } | ||
| 568 | |||
| 569 | return; | ||
| 570 | } | ||
| 571 | |||
| 572 | int be_eth_rq_destroy(struct be_ethrq_object *eth_rq) | ||
| 573 | { | ||
| 574 | int status = BE_SUCCESS; | ||
| 575 | |||
| 576 | /* Send fwcmd to destroy the RQ. */ | ||
| 577 | status = be_function_ring_destroy(eth_rq->parent_function, | ||
| 578 | eth_rq->rid, FWCMD_RING_TYPE_ETH_RX, NULL, NULL, | ||
| 579 | be_eth_rq_destroy_internal_cb, eth_rq); | ||
| 580 | |||
| 581 | return status; | ||
| 582 | } | ||
| 583 | |||
| 584 | /* | ||
| 585 | *--------------------------------------------------------------------------- | ||
| 586 | * Function: be_eth_rq_destroy_options | ||
| 587 | * Destroys an ethernet receive ring with finer granularity options | ||
| 588 | * than the standard be_eth_rq_destroy() API function. | ||
| 589 | * eth_rq - | ||
| 590 | * flush - Set to 1 to flush the ring, set to 0 to bypass the flush | ||
| 591 | * cb - Callback function on completion | ||
| 592 | * cb_context - Callback context | ||
| 593 | * return status - BE_SUCCESS (0) on success. Negative error code on failure. | ||
| 594 | *---------------------------------------------------------------------------- | ||
| 595 | */ | ||
| 596 | int | ||
| 597 | be_eth_rq_destroy_options(struct be_ethrq_object *eth_rq, bool flush, | ||
| 598 | mcc_wrb_cqe_callback cb, void *cb_context) | ||
| 599 | { | ||
| 600 | struct FWCMD_COMMON_RING_DESTROY *fwcmd = NULL; | ||
| 601 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 602 | int status = BE_SUCCESS; | ||
| 603 | struct be_function_object *pfob = NULL; | ||
| 604 | unsigned long irql; | ||
| 605 | |||
| 606 | pfob = eth_rq->parent_function; | ||
| 607 | |||
| 608 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 609 | |||
| 610 | TRACE(DL_INFO, "Destroy eth_rq ring id:%d, flush:%d", eth_rq->rid, | ||
| 611 | flush); | ||
| 612 | |||
| 613 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 614 | if (!wrb) { | ||
| 615 | ASSERT(wrb); | ||
| 616 | TRACE(DL_ERR, "No free MCC WRBs in destroy eth_rq ring."); | ||
| 617 | status = BE_STATUS_NO_MCC_WRB; | ||
| 618 | goto Error; | ||
| 619 | } | ||
| 620 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 621 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_RING_DESTROY); | ||
| 622 | |||
| 623 | fwcmd->params.request.id = eth_rq->rid; | ||
| 624 | fwcmd->params.request.ring_type = FWCMD_RING_TYPE_ETH_RX; | ||
| 625 | fwcmd->params.request.bypass_flush = ((0 == flush) ? 1 : 0); | ||
| 626 | |||
| 627 | /* Post the f/w command */ | ||
| 628 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, cb, cb_context, | ||
| 629 | be_eth_rq_destroy_internal_cb, eth_rq, fwcmd, NULL); | ||
| 630 | |||
| 631 | if (status != BE_SUCCESS && status != BE_PENDING) { | ||
| 632 | TRACE(DL_ERR, "eth_rq ring destroy failed. id:%d, flush:%d", | ||
| 633 | eth_rq->rid, flush); | ||
| 634 | goto Error; | ||
| 635 | } | ||
| 636 | |||
| 637 | Error: | ||
| 638 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 639 | |||
| 640 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 641 | pfob->pend_queue_driving = 0; | ||
| 642 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 643 | } | ||
| 644 | return status; | ||
| 645 | } | ||
| 646 | |||
| 647 | /* | ||
| 648 | This routine queries the frag size for erx. | ||
| 649 | |||
| 650 | pfob - handle to a function object | ||
| 651 | |||
| 652 | frag_size_bytes - erx frag size in bytes that is/was set. | ||
| 653 | |||
| 654 | Returns BE_SUCCESS if successfull, otherwise a useful int error | ||
| 655 | code is returned. | ||
| 656 | |||
| 657 | IRQL: < DISPATCH_LEVEL | ||
| 658 | |||
| 659 | */ | ||
| 660 | int | ||
| 661 | be_eth_rq_get_frag_size(struct be_function_object *pfob, u32 *frag_size_bytes) | ||
| 662 | { | ||
| 663 | struct FWCMD_ETH_GET_RX_FRAG_SIZE *fwcmd = NULL; | ||
| 664 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 665 | int status = 0; | ||
| 666 | unsigned long irql; | ||
| 667 | |||
| 668 | ASSERT(frag_size_bytes); | ||
| 669 | |||
| 670 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 671 | |||
| 672 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 673 | if (!wrb) { | ||
| 674 | TRACE(DL_ERR, "MCC wrb peek failed."); | ||
| 675 | return BE_STATUS_NO_MCC_WRB; | ||
| 676 | } | ||
| 677 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 678 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, ETH_GET_RX_FRAG_SIZE); | ||
| 679 | |||
| 680 | /* Post the f/w command */ | ||
| 681 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, NULL, NULL, | ||
| 682 | NULL, NULL, fwcmd, NULL); | ||
| 683 | |||
| 684 | if (status != 0) { | ||
| 685 | TRACE(DL_ERR, "get frag size fwcmd failed."); | ||
| 686 | goto error; | ||
| 687 | } | ||
| 688 | |||
| 689 | *frag_size_bytes = 1 << fwcmd->params.response.actual_fragsize_log2; | ||
| 690 | |||
| 691 | error: | ||
| 692 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 693 | |||
| 694 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 695 | pfob->pend_queue_driving = 0; | ||
| 696 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 697 | } | ||
| 698 | return status; | ||
| 699 | } | ||
| 700 | |||
| 701 | /* | ||
| 702 | This routine attempts to set the frag size for erx. If the frag size is | ||
| 703 | already set, the attempt fails and the current frag size is returned. | ||
| 704 | |||
| 705 | pfob - Handle to a function object | ||
| 706 | |||
| 707 | frag_size - Erx frag size in bytes that is/was set. | ||
| 708 | |||
| 709 | current_frag_size_bytes - Pointer to location where currrent frag | ||
| 710 | is to be rturned | ||
| 711 | |||
| 712 | Returns BE_SUCCESS if successfull, otherwise a useful int error | ||
| 713 | code is returned. | ||
| 714 | |||
| 715 | IRQL: < DISPATCH_LEVEL | ||
| 716 | |||
| 717 | This function always fails in non-privileged machine context. | ||
| 718 | */ | ||
| 719 | int | ||
| 720 | be_eth_rq_set_frag_size(struct be_function_object *pfob, | ||
| 721 | u32 frag_size, u32 *frag_size_bytes) | ||
| 722 | { | ||
| 723 | struct FWCMD_ETH_SET_RX_FRAG_SIZE *fwcmd = NULL; | ||
| 724 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 725 | int status = 0; | ||
| 726 | unsigned long irql; | ||
| 727 | |||
| 728 | ASSERT(frag_size_bytes); | ||
| 729 | |||
| 730 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 731 | |||
| 732 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 733 | if (!wrb) { | ||
| 734 | TRACE(DL_ERR, "MCC wrb peek failed."); | ||
| 735 | status = BE_STATUS_NO_MCC_WRB; | ||
| 736 | goto error; | ||
| 737 | } | ||
| 738 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 739 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, ETH_SET_RX_FRAG_SIZE); | ||
| 740 | |||
| 741 | ASSERT(frag_size >= 128 && frag_size <= 16 * 1024); | ||
| 742 | |||
| 743 | /* This is the log2 of the fragsize. This is not the exact | ||
| 744 | * ERX encoding. */ | ||
| 745 | fwcmd->params.request.new_fragsize_log2 = __ilog2_u32(frag_size); | ||
| 746 | |||
| 747 | /* Post the f/w command */ | ||
| 748 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, NULL, NULL, | ||
| 749 | NULL, NULL, fwcmd, NULL); | ||
| 750 | |||
| 751 | if (status != 0) { | ||
| 752 | TRACE(DL_ERR, "set frag size fwcmd failed."); | ||
| 753 | goto error; | ||
| 754 | } | ||
| 755 | |||
| 756 | *frag_size_bytes = 1 << fwcmd->params.response.actual_fragsize_log2; | ||
| 757 | error: | ||
| 758 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 759 | |||
| 760 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 761 | pfob->pend_queue_driving = 0; | ||
| 762 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 763 | } | ||
| 764 | return status; | ||
| 765 | } | ||
| 766 | |||
| 767 | |||
| 768 | /* | ||
| 769 | This routine gets or sets a mac address for a domain | ||
| 770 | given the port and mac. | ||
| 771 | |||
| 772 | FunctionObject - Function object handle. | ||
| 773 | port1 - Set to TRUE if this function will set/get the Port 1 | ||
| 774 | address. Only the host may set this to TRUE. | ||
| 775 | mac1 - Set to TRUE if this function will set/get the | ||
| 776 | MAC 1 address. Only the host may set this to TRUE. | ||
| 777 | write - Set to TRUE if this function should write the mac address. | ||
| 778 | mac_address - Buffer of the mac address to read or write. | ||
| 779 | |||
| 780 | Returns BE_SUCCESS if successfull, otherwise a useful int is returned. | ||
| 781 | |||
| 782 | IRQL: < DISPATCH_LEVEL | ||
| 783 | */ | ||
| 784 | int be_rxf_mac_address_read_write(struct be_function_object *pfob, | ||
| 785 | bool port1, /* VM must always set to false */ | ||
| 786 | bool mac1, /* VM must always set to false */ | ||
| 787 | bool mgmt, bool write, | ||
| 788 | bool permanent, u8 *mac_address, | ||
| 789 | mcc_wrb_cqe_callback cb, /* optional */ | ||
| 790 | void *cb_context) /* optional */ | ||
| 791 | { | ||
| 792 | int status = BE_SUCCESS; | ||
| 793 | union { | ||
| 794 | struct FWCMD_COMMON_NTWK_MAC_QUERY *query; | ||
| 795 | struct FWCMD_COMMON_NTWK_MAC_SET *set; | ||
| 796 | } fwcmd = {NULL}; | ||
| 797 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 798 | u32 type = 0; | ||
| 799 | unsigned long irql; | ||
| 800 | struct be_mcc_wrb_response_copy rc; | ||
| 801 | |||
| 802 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 803 | |||
| 804 | ASSERT(mac_address); | ||
| 805 | |||
| 806 | ASSERT(port1 == false); | ||
| 807 | ASSERT(mac1 == false); | ||
| 808 | |||
| 809 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 810 | if (!wrb) { | ||
| 811 | TRACE(DL_ERR, "MCC wrb peek failed."); | ||
| 812 | status = BE_STATUS_NO_MCC_WRB; | ||
| 813 | goto Error; | ||
| 814 | } | ||
| 815 | |||
| 816 | if (mgmt) { | ||
| 817 | type = MAC_ADDRESS_TYPE_MANAGEMENT; | ||
| 818 | } else { | ||
| 819 | if (pfob->type == BE_FUNCTION_TYPE_NETWORK) | ||
| 820 | type = MAC_ADDRESS_TYPE_NETWORK; | ||
| 821 | else | ||
| 822 | type = MAC_ADDRESS_TYPE_STORAGE; | ||
| 823 | } | ||
| 824 | |||
| 825 | if (write) { | ||
| 826 | /* Prepares an embedded fwcmd, including | ||
| 827 | * request/response sizes. | ||
| 828 | */ | ||
| 829 | fwcmd.set = BE_PREPARE_EMBEDDED_FWCMD(pfob, | ||
| 830 | wrb, COMMON_NTWK_MAC_SET); | ||
| 831 | |||
| 832 | fwcmd.set->params.request.invalidate = 0; | ||
| 833 | fwcmd.set->params.request.mac1 = (mac1 ? 1 : 0); | ||
| 834 | fwcmd.set->params.request.port = (port1 ? 1 : 0); | ||
| 835 | fwcmd.set->params.request.type = type; | ||
| 836 | |||
| 837 | /* Copy the mac address to set. */ | ||
| 838 | fwcmd.set->params.request.mac.SizeOfStructure = | ||
| 839 | sizeof(fwcmd.set->params.request.mac); | ||
| 840 | memcpy(fwcmd.set->params.request.mac.MACAddress, | ||
| 841 | mac_address, ETH_ALEN); | ||
| 842 | |||
| 843 | /* Post the f/w command */ | ||
| 844 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, | ||
| 845 | cb, cb_context, NULL, NULL, fwcmd.set, NULL); | ||
| 846 | |||
| 847 | } else { | ||
| 848 | |||
| 849 | /* | ||
| 850 | * Prepares an embedded fwcmd, including | ||
| 851 | * request/response sizes. | ||
| 852 | */ | ||
| 853 | fwcmd.query = BE_PREPARE_EMBEDDED_FWCMD(pfob, | ||
| 854 | wrb, COMMON_NTWK_MAC_QUERY); | ||
| 855 | |||
| 856 | fwcmd.query->params.request.mac1 = (mac1 ? 1 : 0); | ||
| 857 | fwcmd.query->params.request.port = (port1 ? 1 : 0); | ||
| 858 | fwcmd.query->params.request.type = type; | ||
| 859 | fwcmd.query->params.request.permanent = permanent; | ||
| 860 | |||
| 861 | rc.length = FIELD_SIZEOF(struct FWCMD_COMMON_NTWK_MAC_QUERY, | ||
| 862 | params.response.mac.MACAddress); | ||
| 863 | rc.fwcmd_offset = offsetof(struct FWCMD_COMMON_NTWK_MAC_QUERY, | ||
| 864 | params.response.mac.MACAddress); | ||
| 865 | rc.va = mac_address; | ||
| 866 | /* Post the f/w command (with a copy for the response) */ | ||
| 867 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, cb, | ||
| 868 | cb_context, NULL, NULL, fwcmd.query, &rc); | ||
| 869 | } | ||
| 870 | |||
| 871 | if (status < 0) { | ||
| 872 | TRACE(DL_ERR, "mac set/query failed."); | ||
| 873 | goto Error; | ||
| 874 | } | ||
| 875 | |||
| 876 | Error: | ||
| 877 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 878 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 879 | pfob->pend_queue_driving = 0; | ||
| 880 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 881 | } | ||
| 882 | return status; | ||
| 883 | } | ||
| 884 | |||
| 885 | /* | ||
| 886 | This routine writes data to context memory. | ||
| 887 | |||
| 888 | pfob - Function object handle. | ||
| 889 | mac_table - Set to the 128-bit multicast address hash table. | ||
| 890 | |||
| 891 | Returns BE_SUCCESS if successfull, otherwise a useful int is returned. | ||
| 892 | |||
| 893 | IRQL: < DISPATCH_LEVEL | ||
| 894 | */ | ||
| 895 | |||
| 896 | int be_rxf_multicast_config(struct be_function_object *pfob, | ||
| 897 | bool promiscuous, u32 num, u8 *mac_table, | ||
| 898 | mcc_wrb_cqe_callback cb, /* optional */ | ||
| 899 | void *cb_context, | ||
| 900 | struct be_multicast_q_ctxt *q_ctxt) | ||
| 901 | { | ||
| 902 | int status = BE_SUCCESS; | ||
| 903 | struct FWCMD_COMMON_NTWK_MULTICAST_SET *fwcmd = NULL; | ||
| 904 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 905 | struct be_generic_q_ctxt *generic_ctxt = NULL; | ||
| 906 | unsigned long irql; | ||
| 907 | |||
| 908 | ASSERT(num <= ARRAY_SIZE(fwcmd->params.request.mac)); | ||
| 909 | |||
| 910 | if (num > ARRAY_SIZE(fwcmd->params.request.mac)) { | ||
| 911 | TRACE(DL_ERR, "Too many multicast addresses. BE supports %d.", | ||
| 912 | (int) ARRAY_SIZE(fwcmd->params.request.mac)); | ||
| 913 | return BE_NOT_OK; | ||
| 914 | } | ||
| 915 | |||
| 916 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 917 | |||
| 918 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 919 | if (!wrb) { | ||
| 920 | if (q_ctxt && cb) { | ||
| 921 | wrb = (struct MCC_WRB_AMAP *) &q_ctxt->wrb_header; | ||
| 922 | generic_ctxt = (struct be_generic_q_ctxt *) q_ctxt; | ||
| 923 | generic_ctxt->context.bytes = sizeof(*q_ctxt); | ||
| 924 | } else { | ||
| 925 | status = BE_STATUS_NO_MCC_WRB; | ||
| 926 | goto Error; | ||
| 927 | } | ||
| 928 | } | ||
| 929 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 930 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_NTWK_MULTICAST_SET); | ||
| 931 | |||
| 932 | fwcmd->params.request.promiscuous = promiscuous; | ||
| 933 | if (!promiscuous) { | ||
| 934 | fwcmd->params.request.num_mac = num; | ||
| 935 | if (num > 0) { | ||
| 936 | ASSERT(mac_table); | ||
| 937 | memcpy(fwcmd->params.request.mac, | ||
| 938 | mac_table, ETH_ALEN * num); | ||
| 939 | } | ||
| 940 | } | ||
| 941 | |||
| 942 | /* Post the f/w command */ | ||
| 943 | status = be_function_post_mcc_wrb(pfob, wrb, generic_ctxt, | ||
| 944 | cb, cb_context, NULL, NULL, fwcmd, NULL); | ||
| 945 | if (status < 0) { | ||
| 946 | TRACE(DL_ERR, "multicast fwcmd failed."); | ||
| 947 | goto Error; | ||
| 948 | } | ||
| 949 | |||
| 950 | Error: | ||
| 951 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 952 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 953 | pfob->pend_queue_driving = 0; | ||
| 954 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 955 | } | ||
| 956 | return status; | ||
| 957 | } | ||
| 958 | |||
| 959 | /* | ||
| 960 | This routine adds or removes a vlan tag from the rxf table. | ||
| 961 | |||
| 962 | FunctionObject - Function object handle. | ||
| 963 | VLanTag - VLan tag to add or remove. | ||
| 964 | Add - Set to TRUE if this will add a vlan tag | ||
| 965 | |||
| 966 | Returns BE_SUCCESS if successfull, otherwise a useful int is returned. | ||
| 967 | |||
| 968 | IRQL: < DISPATCH_LEVEL | ||
| 969 | */ | ||
| 970 | int be_rxf_vlan_config(struct be_function_object *pfob, | ||
| 971 | bool promiscuous, u32 num, u16 *vlan_tag_array, | ||
| 972 | mcc_wrb_cqe_callback cb, /* optional */ | ||
| 973 | void *cb_context, | ||
| 974 | struct be_vlan_q_ctxt *q_ctxt) /* optional */ | ||
| 975 | { | ||
| 976 | int status = BE_SUCCESS; | ||
| 977 | struct FWCMD_COMMON_NTWK_VLAN_CONFIG *fwcmd = NULL; | ||
| 978 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 979 | struct be_generic_q_ctxt *generic_ctxt = NULL; | ||
| 980 | unsigned long irql; | ||
| 981 | |||
| 982 | if (num > ARRAY_SIZE(fwcmd->params.request.vlan_tag)) { | ||
| 983 | TRACE(DL_ERR, "Too many VLAN tags."); | ||
| 984 | return BE_NOT_OK; | ||
| 985 | } | ||
| 986 | |||
| 987 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 988 | |||
| 989 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 990 | if (!wrb) { | ||
| 991 | if (q_ctxt && cb) { | ||
| 992 | wrb = (struct MCC_WRB_AMAP *) &q_ctxt->wrb_header; | ||
| 993 | generic_ctxt = (struct be_generic_q_ctxt *) q_ctxt; | ||
| 994 | generic_ctxt->context.bytes = sizeof(*q_ctxt); | ||
| 995 | } else { | ||
| 996 | status = BE_STATUS_NO_MCC_WRB; | ||
| 997 | goto Error; | ||
| 998 | } | ||
| 999 | } | ||
| 1000 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 1001 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_NTWK_VLAN_CONFIG); | ||
| 1002 | |||
| 1003 | fwcmd->params.request.promiscuous = promiscuous; | ||
| 1004 | if (!promiscuous) { | ||
| 1005 | fwcmd->params.request.num_vlan = num; | ||
| 1006 | |||
| 1007 | if (num > 0) { | ||
| 1008 | ASSERT(vlan_tag_array); | ||
| 1009 | memcpy(fwcmd->params.request.vlan_tag, vlan_tag_array, | ||
| 1010 | num * sizeof(vlan_tag_array[0])); | ||
| 1011 | } | ||
| 1012 | } | ||
| 1013 | |||
| 1014 | /* Post the commadn */ | ||
| 1015 | status = be_function_post_mcc_wrb(pfob, wrb, generic_ctxt, | ||
| 1016 | cb, cb_context, NULL, NULL, fwcmd, NULL); | ||
| 1017 | if (status < 0) { | ||
| 1018 | TRACE(DL_ERR, "vlan fwcmd failed."); | ||
| 1019 | goto Error; | ||
| 1020 | } | ||
| 1021 | |||
| 1022 | Error: | ||
| 1023 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 1024 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 1025 | pfob->pend_queue_driving = 0; | ||
| 1026 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 1027 | } | ||
| 1028 | return status; | ||
| 1029 | } | ||
| 1030 | |||
| 1031 | |||
| 1032 | int be_rxf_link_status(struct be_function_object *pfob, | ||
| 1033 | struct BE_LINK_STATUS *link_status, | ||
| 1034 | mcc_wrb_cqe_callback cb, | ||
| 1035 | void *cb_context, | ||
| 1036 | struct be_link_status_q_ctxt *q_ctxt) | ||
| 1037 | { | ||
| 1038 | struct FWCMD_COMMON_NTWK_LINK_STATUS_QUERY *fwcmd = NULL; | ||
| 1039 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 1040 | int status = 0; | ||
| 1041 | struct be_generic_q_ctxt *generic_ctxt = NULL; | ||
| 1042 | unsigned long irql; | ||
| 1043 | struct be_mcc_wrb_response_copy rc; | ||
| 1044 | |||
| 1045 | ASSERT(link_status); | ||
| 1046 | |||
| 1047 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 1048 | |||
| 1049 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 1050 | |||
| 1051 | if (!wrb) { | ||
| 1052 | if (q_ctxt && cb) { | ||
| 1053 | wrb = (struct MCC_WRB_AMAP *) &q_ctxt->wrb_header; | ||
| 1054 | generic_ctxt = (struct be_generic_q_ctxt *) q_ctxt; | ||
| 1055 | generic_ctxt->context.bytes = sizeof(*q_ctxt); | ||
| 1056 | } else { | ||
| 1057 | status = BE_STATUS_NO_MCC_WRB; | ||
| 1058 | goto Error; | ||
| 1059 | } | ||
| 1060 | } | ||
| 1061 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 1062 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, | ||
| 1063 | COMMON_NTWK_LINK_STATUS_QUERY); | ||
| 1064 | |||
| 1065 | rc.length = FIELD_SIZEOF(struct FWCMD_COMMON_NTWK_LINK_STATUS_QUERY, | ||
| 1066 | params.response); | ||
| 1067 | rc.fwcmd_offset = offsetof(struct FWCMD_COMMON_NTWK_LINK_STATUS_QUERY, | ||
| 1068 | params.response); | ||
| 1069 | rc.va = link_status; | ||
| 1070 | /* Post or queue the f/w command */ | ||
| 1071 | status = be_function_post_mcc_wrb(pfob, wrb, generic_ctxt, | ||
| 1072 | cb, cb_context, NULL, NULL, fwcmd, &rc); | ||
| 1073 | |||
| 1074 | if (status < 0) { | ||
| 1075 | TRACE(DL_ERR, "link status fwcmd failed."); | ||
| 1076 | goto Error; | ||
| 1077 | } | ||
| 1078 | |||
| 1079 | Error: | ||
| 1080 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 1081 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 1082 | pfob->pend_queue_driving = 0; | ||
| 1083 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 1084 | } | ||
| 1085 | return status; | ||
| 1086 | } | ||
| 1087 | |||
| 1088 | int | ||
| 1089 | be_rxf_query_eth_statistics(struct be_function_object *pfob, | ||
| 1090 | struct FWCMD_ETH_GET_STATISTICS *va_for_fwcmd, | ||
| 1091 | u64 pa_for_fwcmd, mcc_wrb_cqe_callback cb, | ||
| 1092 | void *cb_context, | ||
| 1093 | struct be_nonembedded_q_ctxt *q_ctxt) | ||
| 1094 | { | ||
| 1095 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 1096 | int status = 0; | ||
| 1097 | struct be_generic_q_ctxt *generic_ctxt = NULL; | ||
| 1098 | unsigned long irql; | ||
| 1099 | |||
| 1100 | ASSERT(va_for_fwcmd); | ||
| 1101 | ASSERT(pa_for_fwcmd); | ||
| 1102 | |||
| 1103 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 1104 | |||
| 1105 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 1106 | |||
| 1107 | if (!wrb) { | ||
| 1108 | if (q_ctxt && cb) { | ||
| 1109 | wrb = (struct MCC_WRB_AMAP *) &q_ctxt->wrb_header; | ||
| 1110 | generic_ctxt = (struct be_generic_q_ctxt *) q_ctxt; | ||
| 1111 | generic_ctxt->context.bytes = sizeof(*q_ctxt); | ||
| 1112 | } else { | ||
| 1113 | status = BE_STATUS_NO_MCC_WRB; | ||
| 1114 | goto Error; | ||
| 1115 | } | ||
| 1116 | } | ||
| 1117 | |||
| 1118 | TRACE(DL_INFO, "Query eth stats. fwcmd va:%p pa:0x%08x_%08x", | ||
| 1119 | va_for_fwcmd, upper_32_bits(pa_for_fwcmd), (u32)pa_for_fwcmd); | ||
| 1120 | |||
| 1121 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 1122 | va_for_fwcmd = BE_PREPARE_NONEMBEDDED_FWCMD(pfob, wrb, | ||
| 1123 | va_for_fwcmd, pa_for_fwcmd, ETH_GET_STATISTICS); | ||
| 1124 | |||
| 1125 | /* Post the f/w command */ | ||
| 1126 | status = be_function_post_mcc_wrb(pfob, wrb, generic_ctxt, | ||
| 1127 | cb, cb_context, NULL, NULL, va_for_fwcmd, NULL); | ||
| 1128 | if (status < 0) { | ||
| 1129 | TRACE(DL_ERR, "eth stats fwcmd failed."); | ||
| 1130 | goto Error; | ||
| 1131 | } | ||
| 1132 | |||
| 1133 | Error: | ||
| 1134 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 1135 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 1136 | pfob->pend_queue_driving = 0; | ||
| 1137 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 1138 | } | ||
| 1139 | return status; | ||
| 1140 | } | ||
| 1141 | |||
| 1142 | int | ||
| 1143 | be_rxf_promiscuous(struct be_function_object *pfob, | ||
| 1144 | bool enable_port0, bool enable_port1, | ||
| 1145 | mcc_wrb_cqe_callback cb, void *cb_context, | ||
| 1146 | struct be_promiscuous_q_ctxt *q_ctxt) | ||
| 1147 | { | ||
| 1148 | struct FWCMD_ETH_PROMISCUOUS *fwcmd = NULL; | ||
| 1149 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 1150 | int status = 0; | ||
| 1151 | struct be_generic_q_ctxt *generic_ctxt = NULL; | ||
| 1152 | unsigned long irql; | ||
| 1153 | |||
| 1154 | |||
| 1155 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 1156 | |||
| 1157 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 1158 | |||
| 1159 | if (!wrb) { | ||
| 1160 | if (q_ctxt && cb) { | ||
| 1161 | wrb = (struct MCC_WRB_AMAP *) &q_ctxt->wrb_header; | ||
| 1162 | generic_ctxt = (struct be_generic_q_ctxt *) q_ctxt; | ||
| 1163 | generic_ctxt->context.bytes = sizeof(*q_ctxt); | ||
| 1164 | } else { | ||
| 1165 | status = BE_STATUS_NO_MCC_WRB; | ||
| 1166 | goto Error; | ||
| 1167 | } | ||
| 1168 | } | ||
| 1169 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 1170 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, ETH_PROMISCUOUS); | ||
| 1171 | |||
| 1172 | fwcmd->params.request.port0_promiscuous = enable_port0; | ||
| 1173 | fwcmd->params.request.port1_promiscuous = enable_port1; | ||
| 1174 | |||
| 1175 | /* Post the f/w command */ | ||
| 1176 | status = be_function_post_mcc_wrb(pfob, wrb, generic_ctxt, | ||
| 1177 | cb, cb_context, NULL, NULL, fwcmd, NULL); | ||
| 1178 | |||
| 1179 | if (status < 0) { | ||
| 1180 | TRACE(DL_ERR, "promiscuous fwcmd failed."); | ||
| 1181 | goto Error; | ||
| 1182 | } | ||
| 1183 | |||
| 1184 | Error: | ||
| 1185 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 1186 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 1187 | pfob->pend_queue_driving = 0; | ||
| 1188 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 1189 | } | ||
| 1190 | return status; | ||
| 1191 | } | ||
| 1192 | |||
| 1193 | |||
| 1194 | /* | ||
| 1195 | *------------------------------------------------------------------------- | ||
| 1196 | * Function: be_rxf_filter_config | ||
| 1197 | * Configures BladeEngine ethernet receive filter settings. | ||
| 1198 | * pfob - | ||
| 1199 | * settings - Pointer to the requested filter settings. | ||
| 1200 | * The response from BladeEngine will be placed back | ||
| 1201 | * in this structure. | ||
| 1202 | * cb - optional | ||
| 1203 | * cb_context - optional | ||
| 1204 | * q_ctxt - Optional. Pointer to a previously allocated struct. | ||
| 1205 | * If the MCC WRB ring is full, this structure is | ||
| 1206 | * used to queue the operation. It will be posted | ||
| 1207 | * to the MCC ring when space becomes available. All | ||
| 1208 | * queued commands will be posted to the ring in | ||
| 1209 | * the order they are received. It is always valid | ||
| 1210 | * to pass a pointer to a generic | ||
| 1211 | * be_generic_q_ctxt. However, the specific | ||
| 1212 | * context structs are generally smaller than | ||
| 1213 | * the generic struct. | ||
| 1214 | * return pend_status - BE_SUCCESS (0) on success. | ||
| 1215 | * BE_PENDING (postive value) if the FWCMD | ||
| 1216 | * completion is pending. Negative error code on failure. | ||
| 1217 | *--------------------------------------------------------------------------- | ||
| 1218 | */ | ||
| 1219 | int | ||
| 1220 | be_rxf_filter_config(struct be_function_object *pfob, | ||
| 1221 | struct NTWK_RX_FILTER_SETTINGS *settings, | ||
| 1222 | mcc_wrb_cqe_callback cb, void *cb_context, | ||
| 1223 | struct be_rxf_filter_q_ctxt *q_ctxt) | ||
| 1224 | { | ||
| 1225 | struct FWCMD_COMMON_NTWK_RX_FILTER *fwcmd = NULL; | ||
| 1226 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 1227 | int status = 0; | ||
| 1228 | struct be_generic_q_ctxt *generic_ctxt = NULL; | ||
| 1229 | unsigned long irql; | ||
| 1230 | struct be_mcc_wrb_response_copy rc; | ||
| 1231 | |||
| 1232 | ASSERT(settings); | ||
| 1233 | |||
| 1234 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 1235 | |||
| 1236 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 1237 | |||
| 1238 | if (!wrb) { | ||
| 1239 | if (q_ctxt && cb) { | ||
| 1240 | wrb = (struct MCC_WRB_AMAP *) &q_ctxt->wrb_header; | ||
| 1241 | generic_ctxt = (struct be_generic_q_ctxt *) q_ctxt; | ||
| 1242 | generic_ctxt->context.bytes = sizeof(*q_ctxt); | ||
| 1243 | } else { | ||
| 1244 | status = BE_STATUS_NO_MCC_WRB; | ||
| 1245 | goto Error; | ||
| 1246 | } | ||
| 1247 | } | ||
| 1248 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 1249 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_NTWK_RX_FILTER); | ||
| 1250 | memcpy(&fwcmd->params.request, settings, sizeof(*settings)); | ||
| 1251 | |||
| 1252 | rc.length = FIELD_SIZEOF(struct FWCMD_COMMON_NTWK_RX_FILTER, | ||
| 1253 | params.response); | ||
| 1254 | rc.fwcmd_offset = offsetof(struct FWCMD_COMMON_NTWK_RX_FILTER, | ||
| 1255 | params.response); | ||
| 1256 | rc.va = settings; | ||
| 1257 | /* Post or queue the f/w command */ | ||
| 1258 | status = be_function_post_mcc_wrb(pfob, wrb, generic_ctxt, | ||
| 1259 | cb, cb_context, NULL, NULL, fwcmd, &rc); | ||
| 1260 | |||
| 1261 | if (status < 0) { | ||
| 1262 | TRACE(DL_ERR, "RXF/ERX filter config fwcmd failed."); | ||
| 1263 | goto Error; | ||
| 1264 | } | ||
| 1265 | |||
| 1266 | Error: | ||
| 1267 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 1268 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 1269 | pfob->pend_queue_driving = 0; | ||
| 1270 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 1271 | } | ||
| 1272 | return status; | ||
| 1273 | } | ||
diff --git a/drivers/staging/benet/etx_context.h b/drivers/staging/benet/etx_context.h deleted file mode 100644 index 554fbe5d127b..000000000000 --- a/drivers/staging/benet/etx_context.h +++ /dev/null | |||
| @@ -1,55 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __etx_context_amap_h__ | ||
| 21 | #define __etx_context_amap_h__ | ||
| 22 | |||
| 23 | /* ETX ring context structure. */ | ||
| 24 | struct BE_ETX_CONTEXT_AMAP { | ||
| 25 | u8 tx_cidx[11]; /* DWORD 0 */ | ||
| 26 | u8 rsvd0[5]; /* DWORD 0 */ | ||
| 27 | u8 rsvd1[16]; /* DWORD 0 */ | ||
| 28 | u8 tx_pidx[11]; /* DWORD 1 */ | ||
| 29 | u8 rsvd2; /* DWORD 1 */ | ||
| 30 | u8 tx_ring_size[4]; /* DWORD 1 */ | ||
| 31 | u8 pd_id[5]; /* DWORD 1 */ | ||
| 32 | u8 pd_id_not_valid; /* DWORD 1 */ | ||
| 33 | u8 cq_id_send[10]; /* DWORD 1 */ | ||
| 34 | u8 rsvd3[32]; /* DWORD 2 */ | ||
| 35 | u8 rsvd4[32]; /* DWORD 3 */ | ||
| 36 | u8 cur_bytes[32]; /* DWORD 4 */ | ||
| 37 | u8 max_bytes[32]; /* DWORD 5 */ | ||
| 38 | u8 time_stamp[32]; /* DWORD 6 */ | ||
| 39 | u8 rsvd5[11]; /* DWORD 7 */ | ||
| 40 | u8 func; /* DWORD 7 */ | ||
| 41 | u8 rsvd6[20]; /* DWORD 7 */ | ||
| 42 | u8 cur_txd_count[32]; /* DWORD 8 */ | ||
| 43 | u8 max_txd_count[32]; /* DWORD 9 */ | ||
| 44 | u8 rsvd7[32]; /* DWORD 10 */ | ||
| 45 | u8 rsvd8[32]; /* DWORD 11 */ | ||
| 46 | u8 rsvd9[32]; /* DWORD 12 */ | ||
| 47 | u8 rsvd10[32]; /* DWORD 13 */ | ||
| 48 | u8 rsvd11[32]; /* DWORD 14 */ | ||
| 49 | u8 rsvd12[32]; /* DWORD 15 */ | ||
| 50 | } __packed; | ||
| 51 | struct ETX_CONTEXT_AMAP { | ||
| 52 | u32 dw[16]; | ||
| 53 | }; | ||
| 54 | |||
| 55 | #endif /* __etx_context_amap_h__ */ | ||
diff --git a/drivers/staging/benet/funcobj.c b/drivers/staging/benet/funcobj.c deleted file mode 100644 index 0f57eb58daef..000000000000 --- a/drivers/staging/benet/funcobj.c +++ /dev/null | |||
| @@ -1,565 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | #include "hwlib.h" | ||
| 18 | #include "bestatus.h" | ||
| 19 | |||
| 20 | |||
| 21 | int | ||
| 22 | be_function_internal_query_firmware_config(struct be_function_object *pfob, | ||
| 23 | struct BE_FIRMWARE_CONFIG *config) | ||
| 24 | { | ||
| 25 | struct FWCMD_COMMON_FIRMWARE_CONFIG *fwcmd = NULL; | ||
| 26 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 27 | int status = 0; | ||
| 28 | unsigned long irql; | ||
| 29 | struct be_mcc_wrb_response_copy rc; | ||
| 30 | |||
| 31 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 32 | |||
| 33 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 34 | if (!wrb) { | ||
| 35 | TRACE(DL_ERR, "MCC wrb peek failed."); | ||
| 36 | status = BE_STATUS_NO_MCC_WRB; | ||
| 37 | goto error; | ||
| 38 | } | ||
| 39 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 40 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_FIRMWARE_CONFIG); | ||
| 41 | |||
| 42 | rc.length = FIELD_SIZEOF(struct FWCMD_COMMON_FIRMWARE_CONFIG, | ||
| 43 | params.response); | ||
| 44 | rc.fwcmd_offset = offsetof(struct FWCMD_COMMON_FIRMWARE_CONFIG, | ||
| 45 | params.response); | ||
| 46 | rc.va = config; | ||
| 47 | |||
| 48 | /* Post the f/w command */ | ||
| 49 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, NULL, | ||
| 50 | NULL, NULL, NULL, fwcmd, &rc); | ||
| 51 | error: | ||
| 52 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 53 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 54 | pfob->pend_queue_driving = 0; | ||
| 55 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 56 | } | ||
| 57 | return status; | ||
| 58 | } | ||
| 59 | |||
| 60 | /* | ||
| 61 | This allocates and initializes a function object based on the information | ||
| 62 | provided by upper layer drivers. | ||
| 63 | |||
| 64 | Returns BE_SUCCESS on success and an appropriate int on failure. | ||
| 65 | |||
| 66 | A function object represents a single BladeEngine (logical) PCI function. | ||
| 67 | That is a function object either represents | ||
| 68 | the networking side of BladeEngine or the iSCSI side of BladeEngine. | ||
| 69 | |||
| 70 | This routine will also detect and create an appropriate PD object for the | ||
| 71 | PCI function as needed. | ||
| 72 | */ | ||
| 73 | int | ||
| 74 | be_function_object_create(u8 __iomem *csr_va, u8 __iomem *db_va, | ||
| 75 | u8 __iomem *pci_va, u32 function_type, | ||
| 76 | struct ring_desc *mailbox, struct be_function_object *pfob) | ||
| 77 | { | ||
| 78 | int status; | ||
| 79 | |||
| 80 | ASSERT(pfob); /* not a magic assert */ | ||
| 81 | ASSERT(function_type <= 2); | ||
| 82 | |||
| 83 | TRACE(DL_INFO, "Create function object. type:%s object:0x%p", | ||
| 84 | (function_type == BE_FUNCTION_TYPE_ISCSI ? "iSCSI" : | ||
| 85 | (function_type == BE_FUNCTION_TYPE_NETWORK ? "Network" : | ||
| 86 | "Arm")), pfob); | ||
| 87 | |||
| 88 | memset(pfob, 0, sizeof(*pfob)); | ||
| 89 | |||
| 90 | pfob->type = function_type; | ||
| 91 | pfob->csr_va = csr_va; | ||
| 92 | pfob->db_va = db_va; | ||
| 93 | pfob->pci_va = pci_va; | ||
| 94 | |||
| 95 | spin_lock_init(&pfob->cq_lock); | ||
| 96 | spin_lock_init(&pfob->post_lock); | ||
| 97 | spin_lock_init(&pfob->mcc_context_lock); | ||
| 98 | |||
| 99 | |||
| 100 | pfob->pci_function_number = 1; | ||
| 101 | |||
| 102 | |||
| 103 | pfob->emulate = false; | ||
| 104 | TRACE(DL_NOTE, "Non-emulation mode"); | ||
| 105 | status = be_drive_POST(pfob); | ||
| 106 | if (status != BE_SUCCESS) { | ||
| 107 | TRACE(DL_ERR, "BladeEngine POST failed."); | ||
| 108 | goto error; | ||
| 109 | } | ||
| 110 | |||
| 111 | /* Initialize the mailbox */ | ||
| 112 | status = be_mpu_init_mailbox(pfob, mailbox); | ||
| 113 | if (status != BE_SUCCESS) { | ||
| 114 | TRACE(DL_ERR, "Failed to initialize mailbox."); | ||
| 115 | goto error; | ||
| 116 | } | ||
| 117 | /* | ||
| 118 | * Cache the firmware config for ASSERTs in hwclib and later | ||
| 119 | * driver queries. | ||
| 120 | */ | ||
| 121 | status = be_function_internal_query_firmware_config(pfob, | ||
| 122 | &pfob->fw_config); | ||
| 123 | if (status != BE_SUCCESS) { | ||
| 124 | TRACE(DL_ERR, "Failed to query firmware config."); | ||
| 125 | goto error; | ||
| 126 | } | ||
| 127 | |||
| 128 | error: | ||
| 129 | if (status != BE_SUCCESS) { | ||
| 130 | /* No cleanup necessary */ | ||
| 131 | TRACE(DL_ERR, "Failed to create function."); | ||
| 132 | memset(pfob, 0, sizeof(*pfob)); | ||
| 133 | } | ||
| 134 | return status; | ||
| 135 | } | ||
| 136 | |||
| 137 | /* | ||
| 138 | This routine drops the reference count on a given function object. Once | ||
| 139 | the reference count falls to zero, the function object is destroyed and all | ||
| 140 | resources held are freed. | ||
| 141 | |||
| 142 | FunctionObject - The function object to drop the reference to. | ||
| 143 | */ | ||
| 144 | int be_function_object_destroy(struct be_function_object *pfob) | ||
| 145 | { | ||
| 146 | TRACE(DL_INFO, "Destroy pfob. Object:0x%p", | ||
| 147 | pfob); | ||
| 148 | |||
| 149 | |||
| 150 | ASSERT(pfob->mcc == NULL); | ||
| 151 | |||
| 152 | return BE_SUCCESS; | ||
| 153 | } | ||
| 154 | |||
| 155 | int be_function_cleanup(struct be_function_object *pfob) | ||
| 156 | { | ||
| 157 | int status = 0; | ||
| 158 | u32 isr; | ||
| 159 | u32 host_intr; | ||
| 160 | struct PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP ctrl; | ||
| 161 | |||
| 162 | |||
| 163 | if (pfob->type == BE_FUNCTION_TYPE_NETWORK) { | ||
| 164 | status = be_rxf_multicast_config(pfob, false, 0, | ||
| 165 | NULL, NULL, NULL, NULL); | ||
| 166 | ASSERT(status == BE_SUCCESS); | ||
| 167 | } | ||
| 168 | /* VLAN */ | ||
| 169 | status = be_rxf_vlan_config(pfob, false, 0, NULL, NULL, NULL, NULL); | ||
| 170 | ASSERT(status == BE_SUCCESS); | ||
| 171 | /* | ||
| 172 | * MCC Queue -- Switches to mailbox mode. May want to destroy | ||
| 173 | * all but the MCC CQ before this call if polling CQ is much better | ||
| 174 | * performance than polling mailbox register. | ||
| 175 | */ | ||
| 176 | if (pfob->mcc) | ||
| 177 | status = be_mcc_ring_destroy(pfob->mcc); | ||
| 178 | /* | ||
| 179 | * If interrupts are disabled, clear any CEV interrupt assertions that | ||
| 180 | * fired after we stopped processing EQs. | ||
| 181 | */ | ||
| 182 | ctrl.dw[0] = PCICFG1_READ(pfob, host_timer_int_ctrl); | ||
| 183 | host_intr = AMAP_GET_BITS_PTR(PCICFG_HOST_TIMER_INT_CTRL_CSR, | ||
| 184 | hostintr, ctrl.dw); | ||
| 185 | if (!host_intr) | ||
| 186 | if (pfob->type == BE_FUNCTION_TYPE_NETWORK) | ||
| 187 | isr = CSR_READ(pfob, cev.isr1); | ||
| 188 | else | ||
| 189 | isr = CSR_READ(pfob, cev.isr0); | ||
| 190 | else | ||
| 191 | /* This should never happen... */ | ||
| 192 | TRACE(DL_ERR, "function_cleanup called with interrupt enabled"); | ||
| 193 | /* Function object destroy */ | ||
| 194 | status = be_function_object_destroy(pfob); | ||
| 195 | ASSERT(status == BE_SUCCESS); | ||
| 196 | |||
| 197 | return status; | ||
| 198 | } | ||
| 199 | |||
| 200 | |||
| 201 | void * | ||
| 202 | be_function_prepare_embedded_fwcmd(struct be_function_object *pfob, | ||
| 203 | struct MCC_WRB_AMAP *wrb, u32 payld_len, u32 request_length, | ||
| 204 | u32 response_length, u32 opcode, u32 subsystem) | ||
| 205 | { | ||
| 206 | struct FWCMD_REQUEST_HEADER *header = NULL; | ||
| 207 | u32 n; | ||
| 208 | |||
| 209 | ASSERT(wrb); | ||
| 210 | |||
| 211 | n = offsetof(struct BE_MCC_WRB_AMAP, payload)/8; | ||
| 212 | AMAP_SET_BITS_PTR(MCC_WRB, embedded, wrb, 1); | ||
| 213 | AMAP_SET_BITS_PTR(MCC_WRB, payload_length, wrb, min(payld_len, n)); | ||
| 214 | header = (struct FWCMD_REQUEST_HEADER *)((u8 *)wrb + n); | ||
| 215 | |||
| 216 | header->timeout = 0; | ||
| 217 | header->domain = 0; | ||
| 218 | header->request_length = max(request_length, response_length); | ||
| 219 | header->opcode = opcode; | ||
| 220 | header->subsystem = subsystem; | ||
| 221 | |||
| 222 | return header; | ||
| 223 | } | ||
| 224 | |||
| 225 | void * | ||
| 226 | be_function_prepare_nonembedded_fwcmd(struct be_function_object *pfob, | ||
| 227 | struct MCC_WRB_AMAP *wrb, | ||
| 228 | void *fwcmd_va, u64 fwcmd_pa, | ||
| 229 | u32 payld_len, | ||
| 230 | u32 request_length, | ||
| 231 | u32 response_length, | ||
| 232 | u32 opcode, u32 subsystem) | ||
| 233 | { | ||
| 234 | struct FWCMD_REQUEST_HEADER *header = NULL; | ||
| 235 | u32 n; | ||
| 236 | struct MCC_WRB_PAYLOAD_AMAP *plp; | ||
| 237 | |||
| 238 | ASSERT(wrb); | ||
| 239 | ASSERT(fwcmd_va); | ||
| 240 | |||
| 241 | header = (struct FWCMD_REQUEST_HEADER *) fwcmd_va; | ||
| 242 | |||
| 243 | AMAP_SET_BITS_PTR(MCC_WRB, embedded, wrb, 0); | ||
| 244 | AMAP_SET_BITS_PTR(MCC_WRB, payload_length, wrb, payld_len); | ||
| 245 | |||
| 246 | /* | ||
| 247 | * Assume one fragment. The caller may override the SGL by | ||
| 248 | * rewriting the 0th length and adding more entries. They | ||
| 249 | * will also need to update the sge_count. | ||
| 250 | */ | ||
| 251 | AMAP_SET_BITS_PTR(MCC_WRB, sge_count, wrb, 1); | ||
| 252 | |||
| 253 | n = offsetof(struct BE_MCC_WRB_AMAP, payload)/8; | ||
| 254 | plp = (struct MCC_WRB_PAYLOAD_AMAP *)((u8 *)wrb + n); | ||
| 255 | AMAP_SET_BITS_PTR(MCC_WRB_PAYLOAD, sgl[0].length, plp, payld_len); | ||
| 256 | AMAP_SET_BITS_PTR(MCC_WRB_PAYLOAD, sgl[0].pa_lo, plp, (u32)fwcmd_pa); | ||
| 257 | AMAP_SET_BITS_PTR(MCC_WRB_PAYLOAD, sgl[0].pa_hi, plp, | ||
| 258 | upper_32_bits(fwcmd_pa)); | ||
| 259 | |||
| 260 | header->timeout = 0; | ||
| 261 | header->domain = 0; | ||
| 262 | header->request_length = max(request_length, response_length); | ||
| 263 | header->opcode = opcode; | ||
| 264 | header->subsystem = subsystem; | ||
| 265 | |||
| 266 | return header; | ||
| 267 | } | ||
| 268 | |||
| 269 | struct MCC_WRB_AMAP * | ||
| 270 | be_function_peek_mcc_wrb(struct be_function_object *pfob) | ||
| 271 | { | ||
| 272 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 273 | u32 offset; | ||
| 274 | |||
| 275 | if (pfob->mcc) | ||
| 276 | wrb = _be_mpu_peek_ring_wrb(pfob->mcc, false); | ||
| 277 | else { | ||
| 278 | offset = offsetof(struct BE_MCC_MAILBOX_AMAP, wrb)/8; | ||
| 279 | wrb = (struct MCC_WRB_AMAP *) ((u8 *) pfob->mailbox.va + | ||
| 280 | offset); | ||
| 281 | } | ||
| 282 | |||
| 283 | if (wrb) | ||
| 284 | memset(wrb, 0, sizeof(struct MCC_WRB_AMAP)); | ||
| 285 | |||
| 286 | return wrb; | ||
| 287 | } | ||
| 288 | |||
| 289 | #if defined(BE_DEBUG) | ||
| 290 | void be_function_debug_print_wrb(struct be_function_object *pfob, | ||
| 291 | struct MCC_WRB_AMAP *wrb, void *optional_fwcmd_va, | ||
| 292 | struct be_mcc_wrb_context *wrb_context) | ||
| 293 | { | ||
| 294 | |||
| 295 | struct FWCMD_REQUEST_HEADER *header = NULL; | ||
| 296 | u8 embedded; | ||
| 297 | u32 n; | ||
| 298 | |||
| 299 | embedded = AMAP_GET_BITS_PTR(MCC_WRB, embedded, wrb); | ||
| 300 | |||
| 301 | if (embedded) { | ||
| 302 | n = offsetof(struct BE_MCC_WRB_AMAP, payload)/8; | ||
| 303 | header = (struct FWCMD_REQUEST_HEADER *)((u8 *)wrb + n); | ||
| 304 | } else { | ||
| 305 | header = (struct FWCMD_REQUEST_HEADER *) optional_fwcmd_va; | ||
| 306 | } | ||
| 307 | |||
| 308 | /* Save the completed count before posting for a debug assert. */ | ||
| 309 | |||
| 310 | if (header) { | ||
| 311 | wrb_context->opcode = header->opcode; | ||
| 312 | wrb_context->subsystem = header->subsystem; | ||
| 313 | |||
| 314 | } else { | ||
| 315 | wrb_context->opcode = 0; | ||
| 316 | wrb_context->subsystem = 0; | ||
| 317 | } | ||
| 318 | } | ||
| 319 | #else | ||
| 320 | #define be_function_debug_print_wrb(a_, b_, c_, d_) | ||
| 321 | #endif | ||
| 322 | |||
| 323 | int | ||
| 324 | be_function_post_mcc_wrb(struct be_function_object *pfob, | ||
| 325 | struct MCC_WRB_AMAP *wrb, | ||
| 326 | struct be_generic_q_ctxt *q_ctxt, | ||
| 327 | mcc_wrb_cqe_callback cb, void *cb_context, | ||
| 328 | mcc_wrb_cqe_callback internal_cb, | ||
| 329 | void *internal_cb_context, void *optional_fwcmd_va, | ||
| 330 | struct be_mcc_wrb_response_copy *rc) | ||
| 331 | { | ||
| 332 | int status; | ||
| 333 | struct be_mcc_wrb_context *wrb_context = NULL; | ||
| 334 | u64 *p; | ||
| 335 | |||
| 336 | if (q_ctxt) { | ||
| 337 | /* Initialize context. */ | ||
| 338 | q_ctxt->context.internal_cb = internal_cb; | ||
| 339 | q_ctxt->context.internal_cb_context = internal_cb_context; | ||
| 340 | q_ctxt->context.cb = cb; | ||
| 341 | q_ctxt->context.cb_context = cb_context; | ||
| 342 | if (rc) { | ||
| 343 | q_ctxt->context.copy.length = rc->length; | ||
| 344 | q_ctxt->context.copy.fwcmd_offset = rc->fwcmd_offset; | ||
| 345 | q_ctxt->context.copy.va = rc->va; | ||
| 346 | } else | ||
| 347 | q_ctxt->context.copy.length = 0; | ||
| 348 | |||
| 349 | q_ctxt->context.optional_fwcmd_va = optional_fwcmd_va; | ||
| 350 | |||
| 351 | /* Queue this request */ | ||
| 352 | status = be_function_queue_mcc_wrb(pfob, q_ctxt); | ||
| 353 | |||
| 354 | goto Error; | ||
| 355 | } | ||
| 356 | /* | ||
| 357 | * Allocate a WRB context struct to hold the callback pointers, | ||
| 358 | * status, etc. This is required if commands complete out of order. | ||
| 359 | */ | ||
| 360 | wrb_context = _be_mcc_allocate_wrb_context(pfob); | ||
| 361 | if (!wrb_context) { | ||
| 362 | TRACE(DL_WARN, "Failed to allocate MCC WRB context."); | ||
| 363 | status = BE_STATUS_SYSTEM_RESOURCES; | ||
| 364 | goto Error; | ||
| 365 | } | ||
| 366 | /* Initialize context. */ | ||
| 367 | memset(wrb_context, 0, sizeof(*wrb_context)); | ||
| 368 | wrb_context->internal_cb = internal_cb; | ||
| 369 | wrb_context->internal_cb_context = internal_cb_context; | ||
| 370 | wrb_context->cb = cb; | ||
| 371 | wrb_context->cb_context = cb_context; | ||
| 372 | if (rc) { | ||
| 373 | wrb_context->copy.length = rc->length; | ||
| 374 | wrb_context->copy.fwcmd_offset = rc->fwcmd_offset; | ||
| 375 | wrb_context->copy.va = rc->va; | ||
| 376 | } else | ||
| 377 | wrb_context->copy.length = 0; | ||
| 378 | wrb_context->wrb = wrb; | ||
| 379 | |||
| 380 | /* | ||
| 381 | * Copy the context pointer into the WRB opaque tag field. | ||
| 382 | * Verify assumption of 64-bit tag with a compile time assert. | ||
| 383 | */ | ||
| 384 | p = (u64 *) ((u8 *)wrb + offsetof(struct BE_MCC_WRB_AMAP, tag)/8); | ||
| 385 | *p = (u64)(size_t)wrb_context; | ||
| 386 | |||
| 387 | /* Print info about this FWCMD for debug builds. */ | ||
| 388 | be_function_debug_print_wrb(pfob, wrb, optional_fwcmd_va, wrb_context); | ||
| 389 | |||
| 390 | /* | ||
| 391 | * issue the WRB to the MPU as appropriate | ||
| 392 | */ | ||
| 393 | if (pfob->mcc) { | ||
| 394 | /* | ||
| 395 | * we're in WRB mode, pass to the mcc layer | ||
| 396 | */ | ||
| 397 | status = _be_mpu_post_wrb_ring(pfob->mcc, wrb, wrb_context); | ||
| 398 | } else { | ||
| 399 | /* | ||
| 400 | * we're in mailbox mode | ||
| 401 | */ | ||
| 402 | status = _be_mpu_post_wrb_mailbox(pfob, wrb, wrb_context); | ||
| 403 | |||
| 404 | /* mailbox mode always completes synchronously */ | ||
| 405 | ASSERT(status != BE_STATUS_PENDING); | ||
| 406 | } | ||
| 407 | |||
| 408 | Error: | ||
| 409 | |||
| 410 | return status; | ||
| 411 | } | ||
| 412 | |||
| 413 | int | ||
| 414 | be_function_ring_destroy(struct be_function_object *pfob, | ||
| 415 | u32 id, u32 ring_type, mcc_wrb_cqe_callback cb, | ||
| 416 | void *cb_context, mcc_wrb_cqe_callback internal_cb, | ||
| 417 | void *internal_cb_context) | ||
| 418 | { | ||
| 419 | |||
| 420 | struct FWCMD_COMMON_RING_DESTROY *fwcmd = NULL; | ||
| 421 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 422 | int status = 0; | ||
| 423 | unsigned long irql; | ||
| 424 | |||
| 425 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 426 | |||
| 427 | TRACE(DL_INFO, "Destroy ring id:%d type:%d", id, ring_type); | ||
| 428 | |||
| 429 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 430 | if (!wrb) { | ||
| 431 | ASSERT(wrb); | ||
| 432 | TRACE(DL_ERR, "No free MCC WRBs in destroy ring."); | ||
| 433 | status = BE_STATUS_NO_MCC_WRB; | ||
| 434 | goto Error; | ||
| 435 | } | ||
| 436 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 437 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_RING_DESTROY); | ||
| 438 | |||
| 439 | fwcmd->params.request.id = id; | ||
| 440 | fwcmd->params.request.ring_type = ring_type; | ||
| 441 | |||
| 442 | /* Post the f/w command */ | ||
| 443 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, cb, cb_context, | ||
| 444 | internal_cb, internal_cb_context, fwcmd, NULL); | ||
| 445 | if (status != BE_SUCCESS && status != BE_PENDING) { | ||
| 446 | TRACE(DL_ERR, "Ring destroy fwcmd failed. id:%d ring_type:%d", | ||
| 447 | id, ring_type); | ||
| 448 | goto Error; | ||
| 449 | } | ||
| 450 | |||
| 451 | Error: | ||
| 452 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 453 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 454 | pfob->pend_queue_driving = 0; | ||
| 455 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 456 | } | ||
| 457 | return status; | ||
| 458 | } | ||
| 459 | |||
| 460 | void | ||
| 461 | be_rd_to_pa_list(struct ring_desc *rd, struct PHYS_ADDR *pa_list, u32 max_num) | ||
| 462 | { | ||
| 463 | u32 num_pages = PAGES_SPANNED(rd->va, rd->length); | ||
| 464 | u32 i = 0; | ||
| 465 | u64 pa = rd->pa; | ||
| 466 | __le64 lepa; | ||
| 467 | |||
| 468 | ASSERT(pa_list); | ||
| 469 | ASSERT(pa); | ||
| 470 | |||
| 471 | for (i = 0; i < min(num_pages, max_num); i++) { | ||
| 472 | lepa = cpu_to_le64(pa); | ||
| 473 | pa_list[i].lo = (u32)lepa; | ||
| 474 | pa_list[i].hi = upper_32_bits(lepa); | ||
| 475 | pa += PAGE_SIZE; | ||
| 476 | } | ||
| 477 | } | ||
| 478 | |||
| 479 | |||
| 480 | |||
| 481 | /*----------------------------------------------------------------------------- | ||
| 482 | * Function: be_function_get_fw_version | ||
| 483 | * Retrieves the firmware version on the adpater. If the callback is | ||
| 484 | * NULL this call executes synchronously. If the callback is not NULL, | ||
| 485 | * the returned status will be BE_PENDING if the command was issued | ||
| 486 | * successfully. | ||
| 487 | * pfob - | ||
| 488 | * fwv - Pointer to response buffer if callback is NULL. | ||
| 489 | * cb - Callback function invoked when the FWCMD completes. | ||
| 490 | * cb_context - Passed to the callback function. | ||
| 491 | * return pend_status - BE_SUCCESS (0) on success. | ||
| 492 | * BE_PENDING (postive value) if the FWCMD | ||
| 493 | * completion is pending. Negative error code on failure. | ||
| 494 | *--------------------------------------------------------------------------- | ||
| 495 | */ | ||
| 496 | int | ||
| 497 | be_function_get_fw_version(struct be_function_object *pfob, | ||
| 498 | struct FWCMD_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD *fwv, | ||
| 499 | mcc_wrb_cqe_callback cb, void *cb_context) | ||
| 500 | { | ||
| 501 | int status = BE_SUCCESS; | ||
| 502 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 503 | struct FWCMD_COMMON_GET_FW_VERSION *fwcmd = NULL; | ||
| 504 | unsigned long irql; | ||
| 505 | struct be_mcc_wrb_response_copy rc; | ||
| 506 | |||
| 507 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 508 | |||
| 509 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 510 | if (!wrb) { | ||
| 511 | TRACE(DL_ERR, "MCC wrb peek failed."); | ||
| 512 | status = BE_STATUS_NO_MCC_WRB; | ||
| 513 | goto Error; | ||
| 514 | } | ||
| 515 | |||
| 516 | if (!cb && !fwv) { | ||
| 517 | TRACE(DL_ERR, "callback and response buffer NULL!"); | ||
| 518 | status = BE_NOT_OK; | ||
| 519 | goto Error; | ||
| 520 | } | ||
| 521 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 522 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_GET_FW_VERSION); | ||
| 523 | |||
| 524 | rc.length = FIELD_SIZEOF(struct FWCMD_COMMON_GET_FW_VERSION, | ||
| 525 | params.response); | ||
| 526 | rc.fwcmd_offset = offsetof(struct FWCMD_COMMON_GET_FW_VERSION, | ||
| 527 | params.response); | ||
| 528 | rc.va = fwv; | ||
| 529 | |||
| 530 | /* Post the f/w command */ | ||
| 531 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, cb, | ||
| 532 | cb_context, NULL, NULL, fwcmd, &rc); | ||
| 533 | |||
| 534 | Error: | ||
| 535 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 536 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 537 | pfob->pend_queue_driving = 0; | ||
| 538 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 539 | } | ||
| 540 | return status; | ||
| 541 | } | ||
| 542 | |||
| 543 | int | ||
| 544 | be_function_queue_mcc_wrb(struct be_function_object *pfob, | ||
| 545 | struct be_generic_q_ctxt *q_ctxt) | ||
| 546 | { | ||
| 547 | int status; | ||
| 548 | |||
| 549 | ASSERT(q_ctxt); | ||
| 550 | |||
| 551 | /* | ||
| 552 | * issue the WRB to the MPU as appropriate | ||
| 553 | */ | ||
| 554 | if (pfob->mcc) { | ||
| 555 | |||
| 556 | /* We're in ring mode. Queue this item. */ | ||
| 557 | pfob->mcc->backlog_length++; | ||
| 558 | list_add_tail(&q_ctxt->context.list, &pfob->mcc->backlog); | ||
| 559 | status = BE_PENDING; | ||
| 560 | } else { | ||
| 561 | status = BE_NOT_OK; | ||
| 562 | } | ||
| 563 | return status; | ||
| 564 | } | ||
| 565 | |||
diff --git a/drivers/staging/benet/fwcmd_common.h b/drivers/staging/benet/fwcmd_common.h deleted file mode 100644 index 406e0d6fa985..000000000000 --- a/drivers/staging/benet/fwcmd_common.h +++ /dev/null | |||
| @@ -1,222 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __fwcmd_common_amap_h__ | ||
| 21 | #define __fwcmd_common_amap_h__ | ||
| 22 | #include "host_struct.h" | ||
| 23 | |||
| 24 | /* --- PHY_LINK_DUPLEX_ENUM --- */ | ||
| 25 | #define PHY_LINK_DUPLEX_NONE (0) | ||
| 26 | #define PHY_LINK_DUPLEX_HALF (1) | ||
| 27 | #define PHY_LINK_DUPLEX_FULL (2) | ||
| 28 | |||
| 29 | /* --- PHY_LINK_SPEED_ENUM --- */ | ||
| 30 | #define PHY_LINK_SPEED_ZERO (0) /* No link. */ | ||
| 31 | #define PHY_LINK_SPEED_10MBPS (1) /* 10 Mbps */ | ||
| 32 | #define PHY_LINK_SPEED_100MBPS (2) /* 100 Mbps */ | ||
| 33 | #define PHY_LINK_SPEED_1GBPS (3) /* 1 Gbps */ | ||
| 34 | #define PHY_LINK_SPEED_10GBPS (4) /* 10 Gbps */ | ||
| 35 | |||
| 36 | /* --- PHY_LINK_FAULT_ENUM --- */ | ||
| 37 | #define PHY_LINK_FAULT_NONE (0) /* No fault status | ||
| 38 | available or detected */ | ||
| 39 | #define PHY_LINK_FAULT_LOCAL (1) /* Local fault detected */ | ||
| 40 | #define PHY_LINK_FAULT_REMOTE (2) /* Remote fault detected */ | ||
| 41 | |||
| 42 | /* --- BE_ULP_MASK --- */ | ||
| 43 | #define BE_ULP0_MASK (1) | ||
| 44 | #define BE_ULP1_MASK (2) | ||
| 45 | #define BE_ULP2_MASK (4) | ||
| 46 | |||
| 47 | /* --- NTWK_ACTIVE_PORT --- */ | ||
| 48 | #define NTWK_PORT_A (0) /* Port A is currently active */ | ||
| 49 | #define NTWK_PORT_B (1) /* Port B is currently active */ | ||
| 50 | #define NTWK_NO_ACTIVE_PORT (15) /* Both ports have lost link */ | ||
| 51 | |||
| 52 | /* --- NTWK_LINK_TYPE --- */ | ||
| 53 | #define NTWK_LINK_TYPE_PHYSICAL (0) /* link up/down event | ||
| 54 | applies to BladeEngine's | ||
| 55 | Physical Ports | ||
| 56 | */ | ||
| 57 | #define NTWK_LINK_TYPE_VIRTUAL (1) /* Virtual link up/down event | ||
| 58 | reported by BladeExchange. | ||
| 59 | This applies only when the | ||
| 60 | VLD feature is enabled | ||
| 61 | */ | ||
| 62 | |||
| 63 | /* | ||
| 64 | * --- FWCMD_MAC_TYPE_ENUM --- | ||
| 65 | * This enum defines the types of MAC addresses in the RXF MAC Address Table. | ||
| 66 | */ | ||
| 67 | #define MAC_ADDRESS_TYPE_STORAGE (0) /* Storage MAC Address */ | ||
| 68 | #define MAC_ADDRESS_TYPE_NETWORK (1) /* Network MAC Address */ | ||
| 69 | #define MAC_ADDRESS_TYPE_PD (2) /* Protection Domain MAC Addr */ | ||
| 70 | #define MAC_ADDRESS_TYPE_MANAGEMENT (3) /* Managment MAC Address */ | ||
| 71 | |||
| 72 | |||
| 73 | /* --- FWCMD_RING_TYPE_ENUM --- */ | ||
| 74 | #define FWCMD_RING_TYPE_ETH_RX (1) /* Ring created with */ | ||
| 75 | /* FWCMD_COMMON_ETH_RX_CREATE. */ | ||
| 76 | #define FWCMD_RING_TYPE_ETH_TX (2) /* Ring created with */ | ||
| 77 | /* FWCMD_COMMON_ETH_TX_CREATE. */ | ||
| 78 | #define FWCMD_RING_TYPE_ISCSI_WRBQ (3) /* Ring created with */ | ||
| 79 | /* FWCMD_COMMON_ISCSI_WRBQ_CREATE. */ | ||
| 80 | #define FWCMD_RING_TYPE_ISCSI_DEFQ (4) /* Ring created with */ | ||
| 81 | /* FWCMD_COMMON_ISCSI_DEFQ_CREATE. */ | ||
| 82 | #define FWCMD_RING_TYPE_TPM_WRBQ (5) /* Ring created with */ | ||
| 83 | /* FWCMD_COMMON_TPM_WRBQ_CREATE. */ | ||
| 84 | #define FWCMD_RING_TYPE_TPM_DEFQ (6) /* Ring created with */ | ||
| 85 | /* FWCMD_COMMONTPM_TDEFQ_CREATE. */ | ||
| 86 | #define FWCMD_RING_TYPE_TPM_RQ (7) /* Ring created with */ | ||
| 87 | /* FWCMD_COMMON_TPM_RQ_CREATE. */ | ||
| 88 | #define FWCMD_RING_TYPE_MCC (8) /* Ring created with */ | ||
| 89 | /* FWCMD_COMMON_MCC_CREATE. */ | ||
| 90 | #define FWCMD_RING_TYPE_CQ (9) /* Ring created with */ | ||
| 91 | /* FWCMD_COMMON_CQ_CREATE. */ | ||
| 92 | #define FWCMD_RING_TYPE_EQ (10) /* Ring created with */ | ||
| 93 | /* FWCMD_COMMON_EQ_CREATE. */ | ||
| 94 | #define FWCMD_RING_TYPE_QP (11) /* Ring created with */ | ||
| 95 | /* FWCMD_RDMA_QP_CREATE. */ | ||
| 96 | |||
| 97 | |||
| 98 | /* --- ETH_TX_RING_TYPE_ENUM --- */ | ||
| 99 | #define ETH_TX_RING_TYPE_FORWARDING (1) /* Ethernet ring for | ||
| 100 | forwarding packets */ | ||
| 101 | #define ETH_TX_RING_TYPE_STANDARD (2) /* Ethernet ring for sending | ||
| 102 | network packets. */ | ||
| 103 | #define ETH_TX_RING_TYPE_BOUND (3) /* Ethernet ring bound to the | ||
| 104 | port specified in the command | ||
| 105 | header.port_number field. | ||
| 106 | Rings of this type are | ||
| 107 | NOT subject to the | ||
| 108 | failover logic implemented | ||
| 109 | in the BladeEngine. | ||
| 110 | */ | ||
| 111 | |||
| 112 | /* --- FWCMD_COMMON_QOS_TYPE_ENUM --- */ | ||
| 113 | #define QOS_BITS_NIC (1) /* max_bits_per_second_NIC */ | ||
| 114 | /* field is valid. */ | ||
| 115 | #define QOS_PKTS_NIC (2) /* max_packets_per_second_NIC */ | ||
| 116 | /* field is valid. */ | ||
| 117 | #define QOS_IOPS_ISCSI (4) /* max_ios_per_second_iSCSI */ | ||
| 118 | /*field is valid. */ | ||
| 119 | #define QOS_VLAN_TAG (8) /* domain_VLAN_tag field | ||
| 120 | is valid. */ | ||
| 121 | #define QOS_FABRIC_ID (16) /* fabric_domain_ID field | ||
| 122 | is valid. */ | ||
| 123 | #define QOS_OEM_PARAMS (32) /* qos_params_oem field | ||
| 124 | is valid. */ | ||
| 125 | #define QOS_TPUT_ISCSI (64) /* max_bytes_per_second_iSCSI | ||
| 126 | field is valid. */ | ||
| 127 | |||
| 128 | |||
| 129 | /* | ||
| 130 | * --- FAILOVER_CONFIG_ENUM --- | ||
| 131 | * Failover configuration setting used in FWCMD_COMMON_FORCE_FAILOVER | ||
| 132 | */ | ||
| 133 | #define FAILOVER_CONFIG_NO_CHANGE (0) /* No change to automatic */ | ||
| 134 | /* port failover setting. */ | ||
| 135 | #define FAILOVER_CONFIG_ON (1) /* Automatic port failover | ||
| 136 | on link down is enabled. */ | ||
| 137 | #define FAILOVER_CONFIG_OFF (2) /* Automatic port failover | ||
| 138 | on link down is disabled. */ | ||
| 139 | |||
| 140 | /* | ||
| 141 | * --- FAILOVER_PORT_ENUM --- | ||
| 142 | * Failover port setting used in FWCMD_COMMON_FORCE_FAILOVER | ||
| 143 | */ | ||
| 144 | #define FAILOVER_PORT_A (0) /* Selects port A. */ | ||
| 145 | #define FAILOVER_PORT_B (1) /* Selects port B. */ | ||
| 146 | #define FAILOVER_PORT_NONE (15) /* No port change requested. */ | ||
| 147 | |||
| 148 | |||
| 149 | /* | ||
| 150 | * --- MGMT_FLASHROM_OPCODE --- | ||
| 151 | * Flash ROM operation code | ||
| 152 | */ | ||
| 153 | #define MGMT_FLASHROM_OPCODE_FLASH (1) /* Commit downloaded data | ||
| 154 | to Flash ROM */ | ||
| 155 | #define MGMT_FLASHROM_OPCODE_SAVE (2) /* Save downloaded data to | ||
| 156 | ARM's DDR - do not flash */ | ||
| 157 | #define MGMT_FLASHROM_OPCODE_CLEAR (3) /* Erase specified component | ||
| 158 | from FlashROM */ | ||
| 159 | #define MGMT_FLASHROM_OPCODE_REPORT (4) /* Read specified component | ||
| 160 | from Flash ROM */ | ||
| 161 | #define MGMT_FLASHROM_OPCODE_IMAGE_INFO (5) /* Returns size of a | ||
| 162 | component */ | ||
| 163 | |||
| 164 | /* | ||
| 165 | * --- MGMT_FLASHROM_OPTYPE --- | ||
| 166 | * Flash ROM operation type | ||
| 167 | */ | ||
| 168 | #define MGMT_FLASHROM_OPTYPE_CODE_FIRMWARE (0) /* Includes ARM firmware, | ||
| 169 | IPSec (optional) and EP | ||
| 170 | firmware */ | ||
| 171 | #define MGMT_FLASHROM_OPTYPE_CODE_REDBOOT (1) | ||
| 172 | #define MGMT_FLASHROM_OPTYPE_CODE_BIOS (2) | ||
| 173 | #define MGMT_FLASHROM_OPTYPE_CODE_PXE_BIOS (3) | ||
| 174 | #define MGMT_FLASHROM_OPTYPE_CODE_CTRLS (4) | ||
| 175 | #define MGMT_FLASHROM_OPTYPE_CFG_IPSEC (5) | ||
| 176 | #define MGMT_FLASHROM_OPTYPE_CFG_INI (6) | ||
| 177 | #define MGMT_FLASHROM_OPTYPE_ROM_OFFSET_SPECIFIED (7) | ||
| 178 | |||
| 179 | /* | ||
| 180 | * --- FLASHROM_TYPE --- | ||
| 181 | * Flash ROM manufacturers supported in the f/w | ||
| 182 | */ | ||
| 183 | #define INTEL (0) | ||
| 184 | #define SPANSION (1) | ||
| 185 | #define MICRON (2) | ||
| 186 | |||
| 187 | /* --- DDR_CAS_TYPE --- */ | ||
| 188 | #define CAS_3 (0) | ||
| 189 | #define CAS_4 (1) | ||
| 190 | #define CAS_5 (2) | ||
| 191 | |||
| 192 | /* --- DDR_SIZE_TYPE --- */ | ||
| 193 | #define SIZE_256MB (0) | ||
| 194 | #define SIZE_512MB (1) | ||
| 195 | |||
| 196 | /* --- DDR_MODE_TYPE --- */ | ||
| 197 | #define DDR_NO_ECC (0) | ||
| 198 | #define DDR_ECC (1) | ||
| 199 | |||
| 200 | /* --- INTERFACE_10GB_TYPE --- */ | ||
| 201 | #define CX4_TYPE (0) | ||
| 202 | #define XFP_TYPE (1) | ||
| 203 | |||
| 204 | /* --- BE_CHIP_MAX_MTU --- */ | ||
| 205 | #define CHIP_MAX_MTU (9000) | ||
| 206 | |||
| 207 | /* --- XAUI_STATE_ENUM --- */ | ||
| 208 | #define XAUI_STATE_ENABLE (0) /* This MUST be the default | ||
| 209 | value for all requests | ||
| 210 | which set/change | ||
| 211 | equalization parameter. */ | ||
| 212 | #define XAUI_STATE_DISABLE (255) /* The XAUI for both ports | ||
| 213 | may be disabled for EMI | ||
| 214 | tests. There is no | ||
| 215 | provision for turning off | ||
| 216 | individual ports. | ||
| 217 | */ | ||
| 218 | /* --- BE_ASIC_REVISION --- */ | ||
| 219 | #define BE_ASIC_REV_A0 (1) | ||
| 220 | #define BE_ASIC_REV_A1 (2) | ||
| 221 | |||
| 222 | #endif /* __fwcmd_common_amap_h__ */ | ||
diff --git a/drivers/staging/benet/fwcmd_common_bmap.h b/drivers/staging/benet/fwcmd_common_bmap.h deleted file mode 100644 index a007cf276500..000000000000 --- a/drivers/staging/benet/fwcmd_common_bmap.h +++ /dev/null | |||
| @@ -1,717 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __fwcmd_common_bmap_h__ | ||
| 21 | #define __fwcmd_common_bmap_h__ | ||
| 22 | #include "fwcmd_types_bmap.h" | ||
| 23 | #include "fwcmd_hdr_bmap.h" | ||
| 24 | |||
| 25 | #if defined(__BIG_ENDIAN) | ||
| 26 | /* Physical Address. */ | ||
| 27 | struct PHYS_ADDR { | ||
| 28 | union { | ||
| 29 | struct { | ||
| 30 | u32 lo; /* DWORD 0 */ | ||
| 31 | u32 hi; /* DWORD 1 */ | ||
| 32 | } __packed; /* unnamed struct */ | ||
| 33 | u32 dw[2]; /* dword union */ | ||
| 34 | }; /* unnamed union */ | ||
| 35 | } __packed ; | ||
| 36 | |||
| 37 | |||
| 38 | #else | ||
| 39 | /* Physical Address. */ | ||
| 40 | struct PHYS_ADDR { | ||
| 41 | union { | ||
| 42 | struct { | ||
| 43 | u32 lo; /* DWORD 0 */ | ||
| 44 | u32 hi; /* DWORD 1 */ | ||
| 45 | } __packed; /* unnamed struct */ | ||
| 46 | u32 dw[2]; /* dword union */ | ||
| 47 | }; /* unnamed union */ | ||
| 48 | } __packed ; | ||
| 49 | |||
| 50 | struct BE_LINK_STATUS { | ||
| 51 | u8 mac0_duplex; | ||
| 52 | u8 mac0_speed; | ||
| 53 | u8 mac1_duplex; | ||
| 54 | u8 mac1_speed; | ||
| 55 | u8 mgmt_mac_duplex; | ||
| 56 | u8 mgmt_mac_speed; | ||
| 57 | u8 active_port; | ||
| 58 | u8 rsvd0; | ||
| 59 | u8 mac0_fault; | ||
| 60 | u8 mac1_fault; | ||
| 61 | u16 rsvd1; | ||
| 62 | } __packed; | ||
| 63 | #endif | ||
| 64 | |||
| 65 | struct FWCMD_COMMON_ANON_170_REQUEST { | ||
| 66 | u32 rsvd0; | ||
| 67 | } __packed; | ||
| 68 | |||
| 69 | union LINK_STATUS_QUERY_PARAMS { | ||
| 70 | struct BE_LINK_STATUS response; | ||
| 71 | struct FWCMD_COMMON_ANON_170_REQUEST request; | ||
| 72 | } __packed; | ||
| 73 | |||
| 74 | /* | ||
| 75 | * Queries the the link status for all ports. The valid values below | ||
| 76 | * DO NOT indicate that a particular duplex or speed is supported by | ||
| 77 | * BladeEngine. These enumerations simply list all possible duplexes | ||
| 78 | * and speeds for any port. Consult BladeEngine product documentation | ||
| 79 | * for the supported parameters. | ||
| 80 | */ | ||
| 81 | struct FWCMD_COMMON_NTWK_LINK_STATUS_QUERY { | ||
| 82 | union FWCMD_HEADER header; | ||
| 83 | union LINK_STATUS_QUERY_PARAMS params; | ||
| 84 | } __packed; | ||
| 85 | |||
| 86 | struct FWCMD_COMMON_ANON_171_REQUEST { | ||
| 87 | u8 type; | ||
| 88 | u8 port; | ||
| 89 | u8 mac1; | ||
| 90 | u8 permanent; | ||
| 91 | } __packed; | ||
| 92 | |||
| 93 | struct FWCMD_COMMON_ANON_172_RESPONSE { | ||
| 94 | struct MAC_ADDRESS_FORMAT mac; | ||
| 95 | } __packed; | ||
| 96 | |||
| 97 | union NTWK_MAC_QUERY_PARAMS { | ||
| 98 | struct FWCMD_COMMON_ANON_171_REQUEST request; | ||
| 99 | struct FWCMD_COMMON_ANON_172_RESPONSE response; | ||
| 100 | } __packed; | ||
| 101 | |||
| 102 | /* Queries one MAC address. */ | ||
| 103 | struct FWCMD_COMMON_NTWK_MAC_QUERY { | ||
| 104 | union FWCMD_HEADER header; | ||
| 105 | union NTWK_MAC_QUERY_PARAMS params; | ||
| 106 | } __packed; | ||
| 107 | |||
| 108 | struct MAC_SET_PARAMS_IN { | ||
| 109 | u8 type; | ||
| 110 | u8 port; | ||
| 111 | u8 mac1; | ||
| 112 | u8 invalidate; | ||
| 113 | struct MAC_ADDRESS_FORMAT mac; | ||
| 114 | } __packed; | ||
| 115 | |||
| 116 | struct MAC_SET_PARAMS_OUT { | ||
| 117 | u32 rsvd0; | ||
| 118 | } __packed; | ||
| 119 | |||
| 120 | union MAC_SET_PARAMS { | ||
| 121 | struct MAC_SET_PARAMS_IN request; | ||
| 122 | struct MAC_SET_PARAMS_OUT response; | ||
| 123 | } __packed; | ||
| 124 | |||
| 125 | /* Sets a MAC address. */ | ||
| 126 | struct FWCMD_COMMON_NTWK_MAC_SET { | ||
| 127 | union FWCMD_HEADER header; | ||
| 128 | union MAC_SET_PARAMS params; | ||
| 129 | } __packed; | ||
| 130 | |||
| 131 | /* MAC address list. */ | ||
| 132 | struct NTWK_MULTICAST_MAC_LIST { | ||
| 133 | u8 byte[6]; | ||
| 134 | } __packed; | ||
| 135 | |||
| 136 | struct FWCMD_COMMON_NTWK_MULTICAST_SET_REQUEST_PAYLOAD { | ||
| 137 | u16 num_mac; | ||
| 138 | u8 promiscuous; | ||
| 139 | u8 rsvd0; | ||
| 140 | struct NTWK_MULTICAST_MAC_LIST mac[32]; | ||
| 141 | } __packed; | ||
| 142 | |||
| 143 | struct FWCMD_COMMON_ANON_174_RESPONSE { | ||
| 144 | u32 rsvd0; | ||
| 145 | } __packed; | ||
| 146 | |||
| 147 | union FWCMD_COMMON_ANON_173_PARAMS { | ||
| 148 | struct FWCMD_COMMON_NTWK_MULTICAST_SET_REQUEST_PAYLOAD request; | ||
| 149 | struct FWCMD_COMMON_ANON_174_RESPONSE response; | ||
| 150 | } __packed; | ||
| 151 | |||
| 152 | /* | ||
| 153 | * Sets multicast address hash. The MPU will merge the MAC address lists | ||
| 154 | * from all clients, including the networking and storage functions. | ||
| 155 | * This command may fail if the final merged list of MAC addresses exceeds | ||
| 156 | * 32 entries. | ||
| 157 | */ | ||
| 158 | struct FWCMD_COMMON_NTWK_MULTICAST_SET { | ||
| 159 | union FWCMD_HEADER header; | ||
| 160 | union FWCMD_COMMON_ANON_173_PARAMS params; | ||
| 161 | } __packed; | ||
| 162 | |||
| 163 | struct FWCMD_COMMON_NTWK_VLAN_CONFIG_REQUEST_PAYLOAD { | ||
| 164 | u16 num_vlan; | ||
| 165 | u8 promiscuous; | ||
| 166 | u8 rsvd0; | ||
| 167 | u16 vlan_tag[32]; | ||
| 168 | } __packed; | ||
| 169 | |||
| 170 | struct FWCMD_COMMON_ANON_176_RESPONSE { | ||
| 171 | u32 rsvd0; | ||
| 172 | } __packed; | ||
| 173 | |||
| 174 | union FWCMD_COMMON_ANON_175_PARAMS { | ||
| 175 | struct FWCMD_COMMON_NTWK_VLAN_CONFIG_REQUEST_PAYLOAD request; | ||
| 176 | struct FWCMD_COMMON_ANON_176_RESPONSE response; | ||
| 177 | } __packed; | ||
| 178 | |||
| 179 | /* | ||
| 180 | * Sets VLAN tag filter. The MPU will merge the VLAN tag list from all | ||
| 181 | * clients, including the networking and storage functions. This command | ||
| 182 | * may fail if the final vlan_tag array (from all functions) is longer | ||
| 183 | * than 32 entries. | ||
| 184 | */ | ||
| 185 | struct FWCMD_COMMON_NTWK_VLAN_CONFIG { | ||
| 186 | union FWCMD_HEADER header; | ||
| 187 | union FWCMD_COMMON_ANON_175_PARAMS params; | ||
| 188 | } __packed; | ||
| 189 | |||
| 190 | struct RING_DESTROY_REQUEST { | ||
| 191 | u16 ring_type; | ||
| 192 | u16 id; | ||
| 193 | u8 bypass_flush; | ||
| 194 | u8 rsvd0; | ||
| 195 | u16 rsvd1; | ||
| 196 | } __packed; | ||
| 197 | |||
| 198 | struct FWCMD_COMMON_ANON_190_RESPONSE { | ||
| 199 | u32 rsvd0; | ||
| 200 | } __packed; | ||
| 201 | |||
| 202 | union FWCMD_COMMON_ANON_189_PARAMS { | ||
| 203 | struct RING_DESTROY_REQUEST request; | ||
| 204 | struct FWCMD_COMMON_ANON_190_RESPONSE response; | ||
| 205 | } __packed; | ||
| 206 | /* | ||
| 207 | * Command for destroying any ring. The connection(s) using the ring should | ||
| 208 | * be quiesced before destroying the ring. | ||
| 209 | */ | ||
| 210 | struct FWCMD_COMMON_RING_DESTROY { | ||
| 211 | union FWCMD_HEADER header; | ||
| 212 | union FWCMD_COMMON_ANON_189_PARAMS params; | ||
| 213 | } __packed; | ||
| 214 | |||
| 215 | struct FWCMD_COMMON_ANON_192_REQUEST { | ||
| 216 | u16 num_pages; | ||
| 217 | u16 rsvd0; | ||
| 218 | struct CQ_CONTEXT_AMAP context; | ||
| 219 | struct PHYS_ADDR pages[4]; | ||
| 220 | } __packed ; | ||
| 221 | |||
| 222 | struct FWCMD_COMMON_ANON_193_RESPONSE { | ||
| 223 | u16 cq_id; | ||
| 224 | } __packed ; | ||
| 225 | |||
| 226 | union FWCMD_COMMON_ANON_191_PARAMS { | ||
| 227 | struct FWCMD_COMMON_ANON_192_REQUEST request; | ||
| 228 | struct FWCMD_COMMON_ANON_193_RESPONSE response; | ||
| 229 | } __packed ; | ||
| 230 | |||
| 231 | /* | ||
| 232 | * Command for creating a completion queue. A Completion Queue must span | ||
| 233 | * at least 1 page and at most 4 pages. Each completion queue entry | ||
| 234 | * is 16 bytes regardless of CQ entry format. Thus the ring must be | ||
| 235 | * at least 256 entries deep (corresponding to 1 page) and can be at | ||
| 236 | * most 1024 entries deep (corresponding to 4 pages). The number of | ||
| 237 | * pages posted must contain the CQ ring size as encoded in the context. | ||
| 238 | * | ||
| 239 | */ | ||
| 240 | struct FWCMD_COMMON_CQ_CREATE { | ||
| 241 | union FWCMD_HEADER header; | ||
| 242 | union FWCMD_COMMON_ANON_191_PARAMS params; | ||
| 243 | } __packed ; | ||
| 244 | |||
| 245 | struct FWCMD_COMMON_ANON_198_REQUEST { | ||
| 246 | u16 num_pages; | ||
| 247 | u16 rsvd0; | ||
| 248 | struct EQ_CONTEXT_AMAP context; | ||
| 249 | struct PHYS_ADDR pages[8]; | ||
| 250 | } __packed ; | ||
| 251 | |||
| 252 | struct FWCMD_COMMON_ANON_199_RESPONSE { | ||
| 253 | u16 eq_id; | ||
| 254 | } __packed ; | ||
| 255 | |||
| 256 | union FWCMD_COMMON_ANON_197_PARAMS { | ||
| 257 | struct FWCMD_COMMON_ANON_198_REQUEST request; | ||
| 258 | struct FWCMD_COMMON_ANON_199_RESPONSE response; | ||
| 259 | } __packed ; | ||
| 260 | |||
| 261 | /* | ||
| 262 | * Command for creating a event queue. An Event Queue must span at least | ||
| 263 | * 1 page and at most 8 pages. The number of pages posted must contain | ||
| 264 | * the EQ ring. The ring is defined by the size of the EQ entries (encoded | ||
| 265 | * in the context) and the number of EQ entries (also encoded in the | ||
| 266 | * context). | ||
| 267 | */ | ||
| 268 | struct FWCMD_COMMON_EQ_CREATE { | ||
| 269 | union FWCMD_HEADER header; | ||
| 270 | union FWCMD_COMMON_ANON_197_PARAMS params; | ||
| 271 | } __packed ; | ||
| 272 | |||
| 273 | struct FWCMD_COMMON_ANON_201_REQUEST { | ||
| 274 | u16 cq_id; | ||
| 275 | u16 bcmc_cq_id; | ||
| 276 | u16 num_pages; | ||
| 277 | u16 rsvd0; | ||
| 278 | struct PHYS_ADDR pages[2]; | ||
| 279 | } __packed; | ||
| 280 | |||
| 281 | struct FWCMD_COMMON_ANON_202_RESPONSE { | ||
| 282 | u16 id; | ||
| 283 | } __packed; | ||
| 284 | |||
| 285 | union FWCMD_COMMON_ANON_200_PARAMS { | ||
| 286 | struct FWCMD_COMMON_ANON_201_REQUEST request; | ||
| 287 | struct FWCMD_COMMON_ANON_202_RESPONSE response; | ||
| 288 | } __packed; | ||
| 289 | |||
| 290 | /* | ||
| 291 | * Command for creating Ethernet receive ring. An ERX ring contains ETH_RX_D | ||
| 292 | * entries (8 bytes each). An ERX ring must be 1024 entries deep | ||
| 293 | * (corresponding to 2 pages). | ||
| 294 | */ | ||
| 295 | struct FWCMD_COMMON_ETH_RX_CREATE { | ||
| 296 | union FWCMD_HEADER header; | ||
| 297 | union FWCMD_COMMON_ANON_200_PARAMS params; | ||
| 298 | } __packed; | ||
| 299 | |||
| 300 | struct FWCMD_COMMON_ANON_204_REQUEST { | ||
| 301 | u16 num_pages; | ||
| 302 | u8 ulp_num; | ||
| 303 | u8 type; | ||
| 304 | struct ETX_CONTEXT_AMAP context; | ||
| 305 | struct PHYS_ADDR pages[8]; | ||
| 306 | } __packed ; | ||
| 307 | |||
| 308 | struct FWCMD_COMMON_ANON_205_RESPONSE { | ||
| 309 | u16 cid; | ||
| 310 | u8 ulp_num; | ||
| 311 | u8 rsvd0; | ||
| 312 | } __packed ; | ||
| 313 | |||
| 314 | union FWCMD_COMMON_ANON_203_PARAMS { | ||
| 315 | struct FWCMD_COMMON_ANON_204_REQUEST request; | ||
| 316 | struct FWCMD_COMMON_ANON_205_RESPONSE response; | ||
| 317 | } __packed ; | ||
| 318 | |||
| 319 | /* | ||
| 320 | * Command for creating an Ethernet transmit ring. An ETX ring contains | ||
| 321 | * ETH_WRB entries (16 bytes each). An ETX ring must be at least 256 | ||
| 322 | * entries deep (corresponding to 1 page) and at most 2k entries deep | ||
| 323 | * (corresponding to 8 pages). | ||
| 324 | */ | ||
| 325 | struct FWCMD_COMMON_ETH_TX_CREATE { | ||
| 326 | union FWCMD_HEADER header; | ||
| 327 | union FWCMD_COMMON_ANON_203_PARAMS params; | ||
| 328 | } __packed ; | ||
| 329 | |||
| 330 | struct FWCMD_COMMON_ANON_222_REQUEST { | ||
| 331 | u16 num_pages; | ||
| 332 | u16 rsvd0; | ||
| 333 | struct MCC_RING_CONTEXT_AMAP context; | ||
| 334 | struct PHYS_ADDR pages[8]; | ||
| 335 | } __packed ; | ||
| 336 | |||
| 337 | struct FWCMD_COMMON_ANON_223_RESPONSE { | ||
| 338 | u16 id; | ||
| 339 | } __packed ; | ||
| 340 | |||
| 341 | union FWCMD_COMMON_ANON_221_PARAMS { | ||
| 342 | struct FWCMD_COMMON_ANON_222_REQUEST request; | ||
| 343 | struct FWCMD_COMMON_ANON_223_RESPONSE response; | ||
| 344 | } __packed ; | ||
| 345 | |||
| 346 | /* | ||
| 347 | * Command for creating the MCC ring. An MCC ring must be at least 16 | ||
| 348 | * entries deep (corresponding to 1 page) and at most 128 entries deep | ||
| 349 | * (corresponding to 8 pages). | ||
| 350 | */ | ||
| 351 | struct FWCMD_COMMON_MCC_CREATE { | ||
| 352 | union FWCMD_HEADER header; | ||
| 353 | union FWCMD_COMMON_ANON_221_PARAMS params; | ||
| 354 | } __packed ; | ||
| 355 | |||
| 356 | struct GET_QOS_IN { | ||
| 357 | u32 qos_params_rsvd; | ||
| 358 | } __packed; | ||
| 359 | |||
| 360 | struct GET_QOS_OUT { | ||
| 361 | u32 max_bits_per_second_NIC; | ||
| 362 | u32 max_packets_per_second_NIC; | ||
| 363 | u32 max_ios_per_second_iSCSI; | ||
| 364 | u32 max_bytes_per_second_iSCSI; | ||
| 365 | u16 domain_VLAN_tag; | ||
| 366 | u16 fabric_domain_ID; | ||
| 367 | u32 qos_params_oem[4]; | ||
| 368 | } __packed; | ||
| 369 | |||
| 370 | union GET_QOS_PARAMS { | ||
| 371 | struct GET_QOS_IN request; | ||
| 372 | struct GET_QOS_OUT response; | ||
| 373 | } __packed; | ||
| 374 | |||
| 375 | /* QOS/Bandwidth settings per domain. Applicable only in VMs. */ | ||
| 376 | struct FWCMD_COMMON_GET_QOS { | ||
| 377 | union FWCMD_HEADER header; | ||
| 378 | union GET_QOS_PARAMS params; | ||
| 379 | } __packed; | ||
| 380 | |||
| 381 | struct SET_QOS_IN { | ||
| 382 | u32 valid_flags; | ||
| 383 | u32 max_bits_per_second_NIC; | ||
| 384 | u32 max_packets_per_second_NIC; | ||
| 385 | u32 max_ios_per_second_iSCSI; | ||
| 386 | u32 max_bytes_per_second_iSCSI; | ||
| 387 | u16 domain_VLAN_tag; | ||
| 388 | u16 fabric_domain_ID; | ||
| 389 | u32 qos_params_oem[4]; | ||
| 390 | } __packed; | ||
| 391 | |||
| 392 | struct SET_QOS_OUT { | ||
| 393 | u32 qos_params_rsvd; | ||
| 394 | } __packed; | ||
| 395 | |||
| 396 | union SET_QOS_PARAMS { | ||
| 397 | struct SET_QOS_IN request; | ||
| 398 | struct SET_QOS_OUT response; | ||
| 399 | } __packed; | ||
| 400 | |||
| 401 | /* QOS/Bandwidth settings per domain. Applicable only in VMs. */ | ||
| 402 | struct FWCMD_COMMON_SET_QOS { | ||
| 403 | union FWCMD_HEADER header; | ||
| 404 | union SET_QOS_PARAMS params; | ||
| 405 | } __packed; | ||
| 406 | |||
| 407 | struct SET_FRAME_SIZE_IN { | ||
| 408 | u32 max_tx_frame_size; | ||
| 409 | u32 max_rx_frame_size; | ||
| 410 | } __packed; | ||
| 411 | |||
| 412 | struct SET_FRAME_SIZE_OUT { | ||
| 413 | u32 chip_max_tx_frame_size; | ||
| 414 | u32 chip_max_rx_frame_size; | ||
| 415 | } __packed; | ||
| 416 | |||
| 417 | union SET_FRAME_SIZE_PARAMS { | ||
| 418 | struct SET_FRAME_SIZE_IN request; | ||
| 419 | struct SET_FRAME_SIZE_OUT response; | ||
| 420 | } __packed; | ||
| 421 | |||
| 422 | /* Set frame size command. Only host domain may issue this command. */ | ||
| 423 | struct FWCMD_COMMON_SET_FRAME_SIZE { | ||
| 424 | union FWCMD_HEADER header; | ||
| 425 | union SET_FRAME_SIZE_PARAMS params; | ||
| 426 | } __packed; | ||
| 427 | |||
| 428 | struct FORCE_FAILOVER_IN { | ||
| 429 | u32 move_to_port; | ||
| 430 | u32 failover_config; | ||
| 431 | } __packed; | ||
| 432 | |||
| 433 | struct FWCMD_COMMON_ANON_231_RESPONSE { | ||
| 434 | u32 rsvd0; | ||
| 435 | } __packed; | ||
| 436 | |||
| 437 | union FWCMD_COMMON_ANON_230_PARAMS { | ||
| 438 | struct FORCE_FAILOVER_IN request; | ||
| 439 | struct FWCMD_COMMON_ANON_231_RESPONSE response; | ||
| 440 | } __packed; | ||
| 441 | |||
| 442 | /* | ||
| 443 | * Use this command to control failover in BladeEngine. It may be used | ||
| 444 | * to failback to a restored port or to forcibly move traffic from | ||
| 445 | * one port to another. It may also be used to enable or disable the | ||
| 446 | * automatic failover feature. This command can only be issued by domain | ||
| 447 | * 0. | ||
| 448 | */ | ||
| 449 | struct FWCMD_COMMON_FORCE_FAILOVER { | ||
| 450 | union FWCMD_HEADER header; | ||
| 451 | union FWCMD_COMMON_ANON_230_PARAMS params; | ||
| 452 | } __packed; | ||
| 453 | |||
| 454 | struct FWCMD_COMMON_ANON_240_REQUEST { | ||
| 455 | u64 context; | ||
| 456 | } __packed; | ||
| 457 | |||
| 458 | struct FWCMD_COMMON_ANON_241_RESPONSE { | ||
| 459 | u64 context; | ||
| 460 | } __packed; | ||
| 461 | |||
| 462 | union FWCMD_COMMON_ANON_239_PARAMS { | ||
| 463 | struct FWCMD_COMMON_ANON_240_REQUEST request; | ||
| 464 | struct FWCMD_COMMON_ANON_241_RESPONSE response; | ||
| 465 | } __packed; | ||
| 466 | |||
| 467 | /* | ||
| 468 | * This command can be used by clients as a no-operation request. Typical | ||
| 469 | * uses for drivers are as a heartbeat mechanism, or deferred processing | ||
| 470 | * catalyst. The ARM will always complete this command with a good completion. | ||
| 471 | * The 64-bit parameter is not touched by the ARM processor. | ||
| 472 | */ | ||
| 473 | struct FWCMD_COMMON_NOP { | ||
| 474 | union FWCMD_HEADER header; | ||
| 475 | union FWCMD_COMMON_ANON_239_PARAMS params; | ||
| 476 | } __packed; | ||
| 477 | |||
| 478 | struct NTWK_RX_FILTER_SETTINGS { | ||
| 479 | u8 promiscuous; | ||
| 480 | u8 ip_cksum; | ||
| 481 | u8 tcp_cksum; | ||
| 482 | u8 udp_cksum; | ||
| 483 | u8 pass_err; | ||
| 484 | u8 pass_ckerr; | ||
| 485 | u8 strip_crc; | ||
| 486 | u8 mcast_en; | ||
| 487 | u8 bcast_en; | ||
| 488 | u8 mcast_promiscuous_en; | ||
| 489 | u8 unicast_en; | ||
| 490 | u8 vlan_promiscuous; | ||
| 491 | } __packed; | ||
| 492 | |||
| 493 | union FWCMD_COMMON_ANON_242_PARAMS { | ||
| 494 | struct NTWK_RX_FILTER_SETTINGS request; | ||
| 495 | struct NTWK_RX_FILTER_SETTINGS response; | ||
| 496 | } __packed; | ||
| 497 | |||
| 498 | /* | ||
| 499 | * This command is used to modify the ethernet receive filter configuration. | ||
| 500 | * Only domain 0 network function drivers may issue this command. The | ||
| 501 | * applied configuration is returned in the response payload. Note: | ||
| 502 | * Some receive packet filter settings are global on BladeEngine and | ||
| 503 | * can affect both the storage and network function clients that the | ||
| 504 | * BladeEngine hardware and firmware serve. Additionaly, depending | ||
| 505 | * on the revision of BladeEngine, some ethernet receive filter settings | ||
| 506 | * are dependent on others. If a dependency exists between settings | ||
| 507 | * for the BladeEngine revision, and the command request settings do | ||
| 508 | * not meet the dependency requirement, the invalid settings will not | ||
| 509 | * be applied despite the comand succeeding. For example: a driver may | ||
| 510 | * request to enable broadcast packets, but not enable multicast packets. | ||
| 511 | * On early revisions of BladeEngine, there may be no distinction between | ||
| 512 | * broadcast and multicast filters, so broadcast could not be enabled | ||
| 513 | * without enabling multicast. In this scenario, the comand would still | ||
| 514 | * succeed, but the response payload would indicate the previously | ||
| 515 | * configured broadcast and multicast setting. | ||
| 516 | */ | ||
| 517 | struct FWCMD_COMMON_NTWK_RX_FILTER { | ||
| 518 | union FWCMD_HEADER header; | ||
| 519 | union FWCMD_COMMON_ANON_242_PARAMS params; | ||
| 520 | } __packed; | ||
| 521 | |||
| 522 | |||
| 523 | struct FWCMD_COMMON_ANON_244_REQUEST { | ||
| 524 | u32 rsvd0; | ||
| 525 | } __packed; | ||
| 526 | |||
| 527 | struct FWCMD_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD { | ||
| 528 | u8 firmware_version_string[32]; | ||
| 529 | u8 fw_on_flash_version_string[32]; | ||
| 530 | } __packed; | ||
| 531 | |||
| 532 | union FWCMD_COMMON_ANON_243_PARAMS { | ||
| 533 | struct FWCMD_COMMON_ANON_244_REQUEST request; | ||
| 534 | struct FWCMD_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD response; | ||
| 535 | } __packed; | ||
| 536 | |||
| 537 | /* This comand retrieves the firmware version. */ | ||
| 538 | struct FWCMD_COMMON_GET_FW_VERSION { | ||
| 539 | union FWCMD_HEADER header; | ||
| 540 | union FWCMD_COMMON_ANON_243_PARAMS params; | ||
| 541 | } __packed; | ||
| 542 | |||
| 543 | struct FWCMD_COMMON_ANON_246_REQUEST { | ||
| 544 | u16 tx_flow_control; | ||
| 545 | u16 rx_flow_control; | ||
| 546 | } __packed; | ||
| 547 | |||
| 548 | struct FWCMD_COMMON_ANON_247_RESPONSE { | ||
| 549 | u32 rsvd0; | ||
| 550 | } __packed; | ||
| 551 | |||
| 552 | union FWCMD_COMMON_ANON_245_PARAMS { | ||
| 553 | struct FWCMD_COMMON_ANON_246_REQUEST request; | ||
| 554 | struct FWCMD_COMMON_ANON_247_RESPONSE response; | ||
| 555 | } __packed; | ||
| 556 | |||
| 557 | /* | ||
| 558 | * This comand is used to program BladeEngine flow control behavior. | ||
| 559 | * Only the host networking driver is allowed to use this comand. | ||
| 560 | */ | ||
| 561 | struct FWCMD_COMMON_SET_FLOW_CONTROL { | ||
| 562 | union FWCMD_HEADER header; | ||
| 563 | union FWCMD_COMMON_ANON_245_PARAMS params; | ||
| 564 | } __packed; | ||
| 565 | |||
| 566 | struct FWCMD_COMMON_ANON_249_REQUEST { | ||
| 567 | u32 rsvd0; | ||
| 568 | } __packed; | ||
| 569 | |||
| 570 | struct FWCMD_COMMON_ANON_250_RESPONSE { | ||
| 571 | u16 tx_flow_control; | ||
| 572 | u16 rx_flow_control; | ||
| 573 | } __packed; | ||
| 574 | |||
| 575 | union FWCMD_COMMON_ANON_248_PARAMS { | ||
| 576 | struct FWCMD_COMMON_ANON_249_REQUEST request; | ||
| 577 | struct FWCMD_COMMON_ANON_250_RESPONSE response; | ||
| 578 | } __packed; | ||
| 579 | |||
| 580 | /* This comand is used to read BladeEngine flow control settings. */ | ||
| 581 | struct FWCMD_COMMON_GET_FLOW_CONTROL { | ||
| 582 | union FWCMD_HEADER header; | ||
| 583 | union FWCMD_COMMON_ANON_248_PARAMS params; | ||
| 584 | } __packed; | ||
| 585 | |||
| 586 | struct EQ_DELAY_PARAMS { | ||
| 587 | u32 eq_id; | ||
| 588 | u32 delay_in_microseconds; | ||
| 589 | } __packed; | ||
| 590 | |||
| 591 | struct FWCMD_COMMON_ANON_257_REQUEST { | ||
| 592 | u32 num_eq; | ||
| 593 | u32 rsvd0; | ||
| 594 | struct EQ_DELAY_PARAMS delay[16]; | ||
| 595 | } __packed; | ||
| 596 | |||
| 597 | struct FWCMD_COMMON_ANON_258_RESPONSE { | ||
| 598 | u32 delay_resolution_in_microseconds; | ||
| 599 | u32 delay_max_in_microseconds; | ||
| 600 | } __packed; | ||
| 601 | |||
| 602 | union MODIFY_EQ_DELAY_PARAMS { | ||
| 603 | struct FWCMD_COMMON_ANON_257_REQUEST request; | ||
| 604 | struct FWCMD_COMMON_ANON_258_RESPONSE response; | ||
| 605 | } __packed; | ||
| 606 | |||
| 607 | /* This comand changes the EQ delay for a given set of EQs. */ | ||
| 608 | struct FWCMD_COMMON_MODIFY_EQ_DELAY { | ||
| 609 | union FWCMD_HEADER header; | ||
| 610 | union MODIFY_EQ_DELAY_PARAMS params; | ||
| 611 | } __packed; | ||
| 612 | |||
| 613 | struct FWCMD_COMMON_ANON_260_REQUEST { | ||
| 614 | u32 rsvd0; | ||
| 615 | } __packed; | ||
| 616 | |||
| 617 | struct BE_FIRMWARE_CONFIG { | ||
| 618 | u16 be_config_number; | ||
| 619 | u16 asic_revision; | ||
| 620 | u32 nic_ulp_mask; | ||
| 621 | u32 tulp_mask; | ||
| 622 | u32 iscsi_ulp_mask; | ||
| 623 | u32 rdma_ulp_mask; | ||
| 624 | u32 rsvd0[4]; | ||
| 625 | u32 eth_tx_id_start; | ||
| 626 | u32 eth_tx_id_count; | ||
| 627 | u32 eth_rx_id_start; | ||
| 628 | u32 eth_rx_id_count; | ||
| 629 | u32 tpm_wrbq_id_start; | ||
| 630 | u32 tpm_wrbq_id_count; | ||
| 631 | u32 tpm_defq_id_start; | ||
| 632 | u32 tpm_defq_id_count; | ||
| 633 | u32 iscsi_wrbq_id_start; | ||
| 634 | u32 iscsi_wrbq_id_count; | ||
| 635 | u32 iscsi_defq_id_start; | ||
| 636 | u32 iscsi_defq_id_count; | ||
| 637 | u32 rdma_qp_id_start; | ||
| 638 | u32 rdma_qp_id_count; | ||
| 639 | u32 rsvd1[8]; | ||
| 640 | } __packed; | ||
| 641 | |||
| 642 | union FWCMD_COMMON_ANON_259_PARAMS { | ||
| 643 | struct FWCMD_COMMON_ANON_260_REQUEST request; | ||
| 644 | struct BE_FIRMWARE_CONFIG response; | ||
| 645 | } __packed; | ||
| 646 | |||
| 647 | /* | ||
| 648 | * This comand queries the current firmware configuration parameters. | ||
| 649 | * The static configuration type is defined by be_config_number. This | ||
| 650 | * differentiates different BladeEngine builds, such as iSCSI Initiator | ||
| 651 | * versus iSCSI Target. For a given static configuration, the Upper | ||
| 652 | * Layer Protocol (ULP) processors may be reconfigured to support different | ||
| 653 | * protocols. Each ULP processor supports one or more protocols. The | ||
| 654 | * masks indicate which processors are configured for each protocol. | ||
| 655 | * For a given static configuration, the number of TCP connections | ||
| 656 | * supported for each protocol may vary. The *_id_start and *_id_count | ||
| 657 | * variables define a linear range of IDs that are available for each | ||
| 658 | * supported protocol. The *_id_count may be used by the driver to allocate | ||
| 659 | * the appropriate number of connection resources. The *_id_start may | ||
| 660 | * be used to map the arbitrary range of IDs to a zero-based range | ||
| 661 | * of indices. | ||
| 662 | */ | ||
| 663 | struct FWCMD_COMMON_FIRMWARE_CONFIG { | ||
| 664 | union FWCMD_HEADER header; | ||
| 665 | union FWCMD_COMMON_ANON_259_PARAMS params; | ||
| 666 | } __packed; | ||
| 667 | |||
| 668 | struct FWCMD_COMMON_PORT_EQUALIZATION_PARAMS { | ||
| 669 | u32 emph_lev_sel_port0; | ||
| 670 | u32 emph_lev_sel_port1; | ||
| 671 | u8 xaui_vo_sel; | ||
| 672 | u8 xaui_state; | ||
| 673 | u16 rsvd0; | ||
| 674 | u32 xaui_eq_vector; | ||
| 675 | } __packed; | ||
| 676 | |||
| 677 | struct FWCMD_COMMON_ANON_262_REQUEST { | ||
| 678 | u32 rsvd0; | ||
| 679 | } __packed; | ||
| 680 | |||
| 681 | union FWCMD_COMMON_ANON_261_PARAMS { | ||
| 682 | struct FWCMD_COMMON_ANON_262_REQUEST request; | ||
| 683 | struct FWCMD_COMMON_PORT_EQUALIZATION_PARAMS response; | ||
| 684 | } __packed; | ||
| 685 | |||
| 686 | /* | ||
| 687 | * This comand can be used to read XAUI equalization parameters. The | ||
| 688 | * ARM firmware applies default equalization parameters during initialization. | ||
| 689 | * These parameters may be customer-specific when derived from the | ||
| 690 | * SEEPROM. See SEEPROM_DATA for equalization specific fields. | ||
| 691 | */ | ||
| 692 | struct FWCMD_COMMON_GET_PORT_EQUALIZATION { | ||
| 693 | union FWCMD_HEADER header; | ||
| 694 | union FWCMD_COMMON_ANON_261_PARAMS params; | ||
| 695 | } __packed; | ||
| 696 | |||
| 697 | struct FWCMD_COMMON_ANON_264_RESPONSE { | ||
| 698 | u32 rsvd0; | ||
| 699 | } __packed; | ||
| 700 | |||
| 701 | union FWCMD_COMMON_ANON_263_PARAMS { | ||
| 702 | struct FWCMD_COMMON_PORT_EQUALIZATION_PARAMS request; | ||
| 703 | struct FWCMD_COMMON_ANON_264_RESPONSE response; | ||
| 704 | } __packed; | ||
| 705 | |||
| 706 | /* | ||
| 707 | * This comand can be used to set XAUI equalization parameters. The ARM | ||
| 708 | * firmware applies default equalization parameters during initialization. | ||
| 709 | * These parameters may be customer-specific when derived from the | ||
| 710 | * SEEPROM. See SEEPROM_DATA for equalization specific fields. | ||
| 711 | */ | ||
| 712 | struct FWCMD_COMMON_SET_PORT_EQUALIZATION { | ||
| 713 | union FWCMD_HEADER header; | ||
| 714 | union FWCMD_COMMON_ANON_263_PARAMS params; | ||
| 715 | } __packed; | ||
| 716 | |||
| 717 | #endif /* __fwcmd_common_bmap_h__ */ | ||
diff --git a/drivers/staging/benet/fwcmd_eth_bmap.h b/drivers/staging/benet/fwcmd_eth_bmap.h deleted file mode 100644 index 234b179eace6..000000000000 --- a/drivers/staging/benet/fwcmd_eth_bmap.h +++ /dev/null | |||
| @@ -1,280 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __fwcmd_eth_bmap_h__ | ||
| 21 | #define __fwcmd_eth_bmap_h__ | ||
| 22 | #include "fwcmd_hdr_bmap.h" | ||
| 23 | #include "fwcmd_types_bmap.h" | ||
| 24 | |||
| 25 | struct MIB_ETH_STATISTICS_PARAMS_IN { | ||
| 26 | u32 rsvd0; | ||
| 27 | } __packed; | ||
| 28 | |||
| 29 | struct BE_RXF_STATS { | ||
| 30 | u32 p0recvdtotalbytesLSD; /* DWORD 0 */ | ||
| 31 | u32 p0recvdtotalbytesMSD; /* DWORD 1 */ | ||
| 32 | u32 p0recvdtotalframes; /* DWORD 2 */ | ||
| 33 | u32 p0recvdunicastframes; /* DWORD 3 */ | ||
| 34 | u32 p0recvdmulticastframes; /* DWORD 4 */ | ||
| 35 | u32 p0recvdbroadcastframes; /* DWORD 5 */ | ||
| 36 | u32 p0crcerrors; /* DWORD 6 */ | ||
| 37 | u32 p0alignmentsymerrs; /* DWORD 7 */ | ||
| 38 | u32 p0pauseframesrecvd; /* DWORD 8 */ | ||
| 39 | u32 p0controlframesrecvd; /* DWORD 9 */ | ||
| 40 | u32 p0inrangelenerrors; /* DWORD 10 */ | ||
| 41 | u32 p0outrangeerrors; /* DWORD 11 */ | ||
| 42 | u32 p0frametoolongerrors; /* DWORD 12 */ | ||
| 43 | u32 p0droppedaddressmatch; /* DWORD 13 */ | ||
| 44 | u32 p0droppedvlanmismatch; /* DWORD 14 */ | ||
| 45 | u32 p0ipdroppedtoosmall; /* DWORD 15 */ | ||
| 46 | u32 p0ipdroppedtooshort; /* DWORD 16 */ | ||
| 47 | u32 p0ipdroppedhdrtoosmall; /* DWORD 17 */ | ||
| 48 | u32 p0tcpdroppedlen; /* DWORD 18 */ | ||
| 49 | u32 p0droppedrunt; /* DWORD 19 */ | ||
| 50 | u32 p0recvd64; /* DWORD 20 */ | ||
| 51 | u32 p0recvd65_127; /* DWORD 21 */ | ||
| 52 | u32 p0recvd128_256; /* DWORD 22 */ | ||
| 53 | u32 p0recvd256_511; /* DWORD 23 */ | ||
| 54 | u32 p0recvd512_1023; /* DWORD 24 */ | ||
| 55 | u32 p0recvd1518_1522; /* DWORD 25 */ | ||
| 56 | u32 p0recvd1522_2047; /* DWORD 26 */ | ||
| 57 | u32 p0recvd2048_4095; /* DWORD 27 */ | ||
| 58 | u32 p0recvd4096_8191; /* DWORD 28 */ | ||
| 59 | u32 p0recvd8192_9216; /* DWORD 29 */ | ||
| 60 | u32 p0rcvdipcksmerrs; /* DWORD 30 */ | ||
| 61 | u32 p0recvdtcpcksmerrs; /* DWORD 31 */ | ||
| 62 | u32 p0recvdudpcksmerrs; /* DWORD 32 */ | ||
| 63 | u32 p0recvdnonrsspackets; /* DWORD 33 */ | ||
| 64 | u32 p0recvdippackets; /* DWORD 34 */ | ||
| 65 | u32 p0recvdchute1packets; /* DWORD 35 */ | ||
| 66 | u32 p0recvdchute2packets; /* DWORD 36 */ | ||
| 67 | u32 p0recvdchute3packets; /* DWORD 37 */ | ||
| 68 | u32 p0recvdipsecpackets; /* DWORD 38 */ | ||
| 69 | u32 p0recvdmanagementpackets; /* DWORD 39 */ | ||
| 70 | u32 p0xmitbyteslsd; /* DWORD 40 */ | ||
| 71 | u32 p0xmitbytesmsd; /* DWORD 41 */ | ||
| 72 | u32 p0xmitunicastframes; /* DWORD 42 */ | ||
| 73 | u32 p0xmitmulticastframes; /* DWORD 43 */ | ||
| 74 | u32 p0xmitbroadcastframes; /* DWORD 44 */ | ||
| 75 | u32 p0xmitpauseframes; /* DWORD 45 */ | ||
| 76 | u32 p0xmitcontrolframes; /* DWORD 46 */ | ||
| 77 | u32 p0xmit64; /* DWORD 47 */ | ||
| 78 | u32 p0xmit65_127; /* DWORD 48 */ | ||
| 79 | u32 p0xmit128_256; /* DWORD 49 */ | ||
| 80 | u32 p0xmit256_511; /* DWORD 50 */ | ||
| 81 | u32 p0xmit512_1023; /* DWORD 51 */ | ||
| 82 | u32 p0xmit1518_1522; /* DWORD 52 */ | ||
| 83 | u32 p0xmit1522_2047; /* DWORD 53 */ | ||
| 84 | u32 p0xmit2048_4095; /* DWORD 54 */ | ||
| 85 | u32 p0xmit4096_8191; /* DWORD 55 */ | ||
| 86 | u32 p0xmit8192_9216; /* DWORD 56 */ | ||
| 87 | u32 p0rxfifooverflowdropped; /* DWORD 57 */ | ||
| 88 | u32 p0ipseclookupfaileddropped; /* DWORD 58 */ | ||
| 89 | u32 p1recvdtotalbytesLSD; /* DWORD 59 */ | ||
| 90 | u32 p1recvdtotalbytesMSD; /* DWORD 60 */ | ||
| 91 | u32 p1recvdtotalframes; /* DWORD 61 */ | ||
| 92 | u32 p1recvdunicastframes; /* DWORD 62 */ | ||
| 93 | u32 p1recvdmulticastframes; /* DWORD 63 */ | ||
| 94 | u32 p1recvdbroadcastframes; /* DWORD 64 */ | ||
| 95 | u32 p1crcerrors; /* DWORD 65 */ | ||
| 96 | u32 p1alignmentsymerrs; /* DWORD 66 */ | ||
| 97 | u32 p1pauseframesrecvd; /* DWORD 67 */ | ||
| 98 | u32 p1controlframesrecvd; /* DWORD 68 */ | ||
| 99 | u32 p1inrangelenerrors; /* DWORD 69 */ | ||
| 100 | u32 p1outrangeerrors; /* DWORD 70 */ | ||
| 101 | u32 p1frametoolongerrors; /* DWORD 71 */ | ||
| 102 | u32 p1droppedaddressmatch; /* DWORD 72 */ | ||
| 103 | u32 p1droppedvlanmismatch; /* DWORD 73 */ | ||
| 104 | u32 p1ipdroppedtoosmall; /* DWORD 74 */ | ||
| 105 | u32 p1ipdroppedtooshort; /* DWORD 75 */ | ||
| 106 | u32 p1ipdroppedhdrtoosmall; /* DWORD 76 */ | ||
| 107 | u32 p1tcpdroppedlen; /* DWORD 77 */ | ||
| 108 | u32 p1droppedrunt; /* DWORD 78 */ | ||
| 109 | u32 p1recvd64; /* DWORD 79 */ | ||
| 110 | u32 p1recvd65_127; /* DWORD 80 */ | ||
| 111 | u32 p1recvd128_256; /* DWORD 81 */ | ||
| 112 | u32 p1recvd256_511; /* DWORD 82 */ | ||
| 113 | u32 p1recvd512_1023; /* DWORD 83 */ | ||
| 114 | u32 p1recvd1518_1522; /* DWORD 84 */ | ||
| 115 | u32 p1recvd1522_2047; /* DWORD 85 */ | ||
| 116 | u32 p1recvd2048_4095; /* DWORD 86 */ | ||
| 117 | u32 p1recvd4096_8191; /* DWORD 87 */ | ||
| 118 | u32 p1recvd8192_9216; /* DWORD 88 */ | ||
| 119 | u32 p1rcvdipcksmerrs; /* DWORD 89 */ | ||
| 120 | u32 p1recvdtcpcksmerrs; /* DWORD 90 */ | ||
| 121 | u32 p1recvdudpcksmerrs; /* DWORD 91 */ | ||
| 122 | u32 p1recvdnonrsspackets; /* DWORD 92 */ | ||
| 123 | u32 p1recvdippackets; /* DWORD 93 */ | ||
| 124 | u32 p1recvdchute1packets; /* DWORD 94 */ | ||
| 125 | u32 p1recvdchute2packets; /* DWORD 95 */ | ||
| 126 | u32 p1recvdchute3packets; /* DWORD 96 */ | ||
| 127 | u32 p1recvdipsecpackets; /* DWORD 97 */ | ||
| 128 | u32 p1recvdmanagementpackets; /* DWORD 98 */ | ||
| 129 | u32 p1xmitbyteslsd; /* DWORD 99 */ | ||
| 130 | u32 p1xmitbytesmsd; /* DWORD 100 */ | ||
| 131 | u32 p1xmitunicastframes; /* DWORD 101 */ | ||
| 132 | u32 p1xmitmulticastframes; /* DWORD 102 */ | ||
| 133 | u32 p1xmitbroadcastframes; /* DWORD 103 */ | ||
| 134 | u32 p1xmitpauseframes; /* DWORD 104 */ | ||
| 135 | u32 p1xmitcontrolframes; /* DWORD 105 */ | ||
| 136 | u32 p1xmit64; /* DWORD 106 */ | ||
| 137 | u32 p1xmit65_127; /* DWORD 107 */ | ||
| 138 | u32 p1xmit128_256; /* DWORD 108 */ | ||
| 139 | u32 p1xmit256_511; /* DWORD 109 */ | ||
| 140 | u32 p1xmit512_1023; /* DWORD 110 */ | ||
| 141 | u32 p1xmit1518_1522; /* DWORD 111 */ | ||
| 142 | u32 p1xmit1522_2047; /* DWORD 112 */ | ||
| 143 | u32 p1xmit2048_4095; /* DWORD 113 */ | ||
| 144 | u32 p1xmit4096_8191; /* DWORD 114 */ | ||
| 145 | u32 p1xmit8192_9216; /* DWORD 115 */ | ||
| 146 | u32 p1rxfifooverflowdropped; /* DWORD 116 */ | ||
| 147 | u32 p1ipseclookupfaileddropped; /* DWORD 117 */ | ||
| 148 | u32 pxdroppednopbuf; /* DWORD 118 */ | ||
| 149 | u32 pxdroppednotxpb; /* DWORD 119 */ | ||
| 150 | u32 pxdroppednoipsecbuf; /* DWORD 120 */ | ||
| 151 | u32 pxdroppednoerxdescr; /* DWORD 121 */ | ||
| 152 | u32 pxdroppednotpredescr; /* DWORD 122 */ | ||
| 153 | u32 pxrecvdmanagementportpackets; /* DWORD 123 */ | ||
| 154 | u32 pxrecvdmanagementportbytes; /* DWORD 124 */ | ||
| 155 | u32 pxrecvdmanagementportpauseframes; /* DWORD 125 */ | ||
| 156 | u32 pxrecvdmanagementporterrors; /* DWORD 126 */ | ||
| 157 | u32 pxxmitmanagementportpackets; /* DWORD 127 */ | ||
| 158 | u32 pxxmitmanagementportbytes; /* DWORD 128 */ | ||
| 159 | u32 pxxmitmanagementportpause; /* DWORD 129 */ | ||
| 160 | u32 pxxmitmanagementportrxfifooverflow; /* DWORD 130 */ | ||
| 161 | u32 pxrecvdipsecipcksmerrs; /* DWORD 131 */ | ||
| 162 | u32 pxrecvdtcpsecipcksmerrs; /* DWORD 132 */ | ||
| 163 | u32 pxrecvdudpsecipcksmerrs; /* DWORD 133 */ | ||
| 164 | u32 pxipsecrunt; /* DWORD 134 */ | ||
| 165 | u32 pxipsecaddressmismatchdropped; /* DWORD 135 */ | ||
| 166 | u32 pxipsecrxfifooverflowdropped; /* DWORD 136 */ | ||
| 167 | u32 pxipsecframestoolong; /* DWORD 137 */ | ||
| 168 | u32 pxipsectotalipframes; /* DWORD 138 */ | ||
| 169 | u32 pxipseciptoosmall; /* DWORD 139 */ | ||
| 170 | u32 pxipseciptooshort; /* DWORD 140 */ | ||
| 171 | u32 pxipseciphdrtoosmall; /* DWORD 141 */ | ||
| 172 | u32 pxipsectcphdrbad; /* DWORD 142 */ | ||
| 173 | u32 pxrecvdipsecchute1; /* DWORD 143 */ | ||
| 174 | u32 pxrecvdipsecchute2; /* DWORD 144 */ | ||
| 175 | u32 pxrecvdipsecchute3; /* DWORD 145 */ | ||
| 176 | u32 pxdropped7frags; /* DWORD 146 */ | ||
| 177 | u32 pxdroppedfrags; /* DWORD 147 */ | ||
| 178 | u32 pxdroppedinvalidfragring; /* DWORD 148 */ | ||
| 179 | u32 pxnumforwardedpackets; /* DWORD 149 */ | ||
| 180 | } __packed; | ||
| 181 | |||
| 182 | union MIB_ETH_STATISTICS_PARAMS { | ||
| 183 | struct MIB_ETH_STATISTICS_PARAMS_IN request; | ||
| 184 | struct BE_RXF_STATS response; | ||
| 185 | } __packed; | ||
| 186 | |||
| 187 | /* | ||
| 188 | * Query ethernet statistics. All domains may issue this command. The | ||
| 189 | * host domain drivers may optionally reset internal statistic counters | ||
| 190 | * with a query. | ||
| 191 | */ | ||
| 192 | struct FWCMD_ETH_GET_STATISTICS { | ||
| 193 | union FWCMD_HEADER header; | ||
| 194 | union MIB_ETH_STATISTICS_PARAMS params; | ||
| 195 | } __packed; | ||
| 196 | |||
| 197 | |||
| 198 | struct FWCMD_ETH_ANON_175_REQUEST { | ||
| 199 | u8 port0_promiscuous; | ||
| 200 | u8 port1_promiscuous; | ||
| 201 | u16 rsvd0; | ||
| 202 | } __packed; | ||
| 203 | |||
| 204 | struct FWCMD_ETH_ANON_176_RESPONSE { | ||
| 205 | u32 rsvd0; | ||
| 206 | } __packed; | ||
| 207 | |||
| 208 | union FWCMD_ETH_ANON_174_PARAMS { | ||
| 209 | struct FWCMD_ETH_ANON_175_REQUEST request; | ||
| 210 | struct FWCMD_ETH_ANON_176_RESPONSE response; | ||
| 211 | } __packed; | ||
| 212 | |||
| 213 | /* Enables/Disables promiscuous ethernet receive mode. */ | ||
| 214 | struct FWCMD_ETH_PROMISCUOUS { | ||
| 215 | union FWCMD_HEADER header; | ||
| 216 | union FWCMD_ETH_ANON_174_PARAMS params; | ||
| 217 | } __packed; | ||
| 218 | |||
| 219 | struct FWCMD_ETH_ANON_178_REQUEST { | ||
| 220 | u32 new_fragsize_log2; | ||
| 221 | } __packed; | ||
| 222 | |||
| 223 | struct FWCMD_ETH_ANON_179_RESPONSE { | ||
| 224 | u32 actual_fragsize_log2; | ||
| 225 | } __packed; | ||
| 226 | |||
| 227 | union FWCMD_ETH_ANON_177_PARAMS { | ||
| 228 | struct FWCMD_ETH_ANON_178_REQUEST request; | ||
| 229 | struct FWCMD_ETH_ANON_179_RESPONSE response; | ||
| 230 | } __packed; | ||
| 231 | |||
| 232 | /* | ||
| 233 | * Sets the Ethernet RX fragment size. Only host (domain 0) networking | ||
| 234 | * drivers may issue this command. This call will fail for non-host | ||
| 235 | * protection domains. In this situation the MCC CQ status will indicate | ||
| 236 | * a failure due to insufficient priviledges. The response should be | ||
| 237 | * ignored, and the driver should use the FWCMD_ETH_GET_FRAG_SIZE to | ||
| 238 | * query the existing ethernet receive fragment size. It must use this | ||
| 239 | * fragment size for all fragments in the ethernet receive ring. If | ||
| 240 | * the command succeeds, the driver must use the frag size indicated | ||
| 241 | * in the command response since the requested frag size may not be applied | ||
| 242 | * until the next reboot. When the requested fragsize matches the response | ||
| 243 | * fragsize, this indicates the request was applied immediately. | ||
| 244 | */ | ||
| 245 | struct FWCMD_ETH_SET_RX_FRAG_SIZE { | ||
| 246 | union FWCMD_HEADER header; | ||
| 247 | union FWCMD_ETH_ANON_177_PARAMS params; | ||
| 248 | } __packed; | ||
| 249 | |||
| 250 | struct FWCMD_ETH_ANON_181_REQUEST { | ||
| 251 | u32 rsvd0; | ||
| 252 | } __packed; | ||
| 253 | |||
| 254 | struct FWCMD_ETH_ANON_182_RESPONSE { | ||
| 255 | u32 actual_fragsize_log2; | ||
| 256 | } __packed; | ||
| 257 | |||
| 258 | union FWCMD_ETH_ANON_180_PARAMS { | ||
| 259 | struct FWCMD_ETH_ANON_181_REQUEST request; | ||
| 260 | struct FWCMD_ETH_ANON_182_RESPONSE response; | ||
| 261 | } __packed; | ||
| 262 | |||
| 263 | /* | ||
| 264 | * Queries the Ethernet RX fragment size. All domains may issue this | ||
| 265 | * command. The driver should call this command to determine the minimum | ||
| 266 | * required fragment size for the ethernet RX ring buffers. Drivers | ||
| 267 | * may choose to use a larger size for each fragment buffer, but BladeEngine | ||
| 268 | * will use up to the configured minimum required fragsize in each ethernet | ||
| 269 | * receive fragment buffer. For example, if the ethernet receive fragment | ||
| 270 | * size is configured to 4kB, and a driver uses 8kB fragments, a 6kB | ||
| 271 | * ethernet packet received by BladeEngine will be split accross two | ||
| 272 | * of the driver's receive framgents (4kB in one fragment buffer, and | ||
| 273 | * 2kB in the subsequent fragment buffer). | ||
| 274 | */ | ||
| 275 | struct FWCMD_ETH_GET_RX_FRAG_SIZE { | ||
| 276 | union FWCMD_HEADER header; | ||
| 277 | union FWCMD_ETH_ANON_180_PARAMS params; | ||
| 278 | } __packed; | ||
| 279 | |||
| 280 | #endif /* __fwcmd_eth_bmap_h__ */ | ||
diff --git a/drivers/staging/benet/fwcmd_hdr_bmap.h b/drivers/staging/benet/fwcmd_hdr_bmap.h deleted file mode 100644 index 28b45328fe7b..000000000000 --- a/drivers/staging/benet/fwcmd_hdr_bmap.h +++ /dev/null | |||
| @@ -1,54 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __fwcmd_hdr_bmap_h__ | ||
| 21 | #define __fwcmd_hdr_bmap_h__ | ||
| 22 | |||
| 23 | struct FWCMD_REQUEST_HEADER { | ||
| 24 | u8 opcode; | ||
| 25 | u8 subsystem; | ||
| 26 | u8 port_number; | ||
| 27 | u8 domain; | ||
| 28 | u32 timeout; | ||
| 29 | u32 request_length; | ||
| 30 | u32 rsvd0; | ||
| 31 | } __packed; | ||
| 32 | |||
| 33 | struct FWCMD_RESPONSE_HEADER { | ||
| 34 | u8 opcode; | ||
| 35 | u8 subsystem; | ||
| 36 | u8 rsvd0; | ||
| 37 | u8 domain; | ||
| 38 | u8 status; | ||
| 39 | u8 additional_status; | ||
| 40 | u16 rsvd1; | ||
| 41 | u32 response_length; | ||
| 42 | u32 actual_response_length; | ||
| 43 | } __packed; | ||
| 44 | |||
| 45 | /* | ||
| 46 | * The firmware/driver overwrites the input FWCMD_REQUEST_HEADER with | ||
| 47 | * the output FWCMD_RESPONSE_HEADER. | ||
| 48 | */ | ||
| 49 | union FWCMD_HEADER { | ||
| 50 | struct FWCMD_REQUEST_HEADER request; | ||
| 51 | struct FWCMD_RESPONSE_HEADER response; | ||
| 52 | } __packed; | ||
| 53 | |||
| 54 | #endif /* __fwcmd_hdr_bmap_h__ */ | ||
diff --git a/drivers/staging/benet/fwcmd_mcc.h b/drivers/staging/benet/fwcmd_mcc.h deleted file mode 100644 index 9eeca878c1fb..000000000000 --- a/drivers/staging/benet/fwcmd_mcc.h +++ /dev/null | |||
| @@ -1,94 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __fwcmd_mcc_amap_h__ | ||
| 21 | #define __fwcmd_mcc_amap_h__ | ||
| 22 | #include "fwcmd_opcodes.h" | ||
| 23 | /* | ||
| 24 | * Where applicable, a WRB, may contain a list of Scatter-gather elements. | ||
| 25 | * Each element supports a 64 bit address and a 32bit length field. | ||
| 26 | */ | ||
| 27 | struct BE_MCC_SGE_AMAP { | ||
| 28 | u8 pa_lo[32]; /* DWORD 0 */ | ||
| 29 | u8 pa_hi[32]; /* DWORD 1 */ | ||
| 30 | u8 length[32]; /* DWORD 2 */ | ||
| 31 | } __packed; | ||
| 32 | struct MCC_SGE_AMAP { | ||
| 33 | u32 dw[3]; | ||
| 34 | }; | ||
| 35 | /* | ||
| 36 | * The design of an MCC_SGE allows up to 19 elements to be embedded | ||
| 37 | * in a WRB, supporting 64KB data transfers (assuming a 4KB page size). | ||
| 38 | */ | ||
| 39 | struct BE_MCC_WRB_PAYLOAD_AMAP { | ||
| 40 | union { | ||
| 41 | struct BE_MCC_SGE_AMAP sgl[19]; | ||
| 42 | u8 embedded[59][32]; /* DWORD 0 */ | ||
| 43 | }; | ||
| 44 | } __packed; | ||
| 45 | struct MCC_WRB_PAYLOAD_AMAP { | ||
| 46 | u32 dw[59]; | ||
| 47 | }; | ||
| 48 | |||
| 49 | /* | ||
| 50 | * This is the structure of the MCC Command WRB for commands | ||
| 51 | * sent to the Management Processing Unit (MPU). See section | ||
| 52 | * for usage in embedded and non-embedded modes. | ||
| 53 | */ | ||
| 54 | struct BE_MCC_WRB_AMAP { | ||
| 55 | u8 embedded; /* DWORD 0 */ | ||
| 56 | u8 rsvd0[2]; /* DWORD 0 */ | ||
| 57 | u8 sge_count[5]; /* DWORD 0 */ | ||
| 58 | u8 rsvd1[16]; /* DWORD 0 */ | ||
| 59 | u8 special[8]; /* DWORD 0 */ | ||
| 60 | u8 payload_length[32]; /* DWORD 1 */ | ||
| 61 | u8 tag[2][32]; /* DWORD 2 */ | ||
| 62 | u8 rsvd2[32]; /* DWORD 4 */ | ||
| 63 | struct BE_MCC_WRB_PAYLOAD_AMAP payload; | ||
| 64 | } __packed; | ||
| 65 | struct MCC_WRB_AMAP { | ||
| 66 | u32 dw[64]; | ||
| 67 | }; | ||
| 68 | |||
| 69 | /* This is the structure of the MCC Completion queue entry */ | ||
| 70 | struct BE_MCC_CQ_ENTRY_AMAP { | ||
| 71 | u8 completion_status[16]; /* DWORD 0 */ | ||
| 72 | u8 extended_status[16]; /* DWORD 0 */ | ||
| 73 | u8 mcc_tag[2][32]; /* DWORD 1 */ | ||
| 74 | u8 rsvd0[27]; /* DWORD 3 */ | ||
| 75 | u8 consumed; /* DWORD 3 */ | ||
| 76 | u8 completed; /* DWORD 3 */ | ||
| 77 | u8 hpi_buffer_completion; /* DWORD 3 */ | ||
| 78 | u8 async_event; /* DWORD 3 */ | ||
| 79 | u8 valid; /* DWORD 3 */ | ||
| 80 | } __packed; | ||
| 81 | struct MCC_CQ_ENTRY_AMAP { | ||
| 82 | u32 dw[4]; | ||
| 83 | }; | ||
| 84 | |||
| 85 | /* Mailbox structures used by the MPU during bootstrap */ | ||
| 86 | struct BE_MCC_MAILBOX_AMAP { | ||
| 87 | struct BE_MCC_WRB_AMAP wrb; | ||
| 88 | struct BE_MCC_CQ_ENTRY_AMAP cq; | ||
| 89 | } __packed; | ||
| 90 | struct MCC_MAILBOX_AMAP { | ||
| 91 | u32 dw[68]; | ||
| 92 | }; | ||
| 93 | |||
| 94 | #endif /* __fwcmd_mcc_amap_h__ */ | ||
diff --git a/drivers/staging/benet/fwcmd_opcodes.h b/drivers/staging/benet/fwcmd_opcodes.h deleted file mode 100644 index 23d569386b46..000000000000 --- a/drivers/staging/benet/fwcmd_opcodes.h +++ /dev/null | |||
| @@ -1,244 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __fwcmd_opcodes_amap_h__ | ||
| 21 | #define __fwcmd_opcodes_amap_h__ | ||
| 22 | |||
| 23 | /* | ||
| 24 | * --- FWCMD_SUBSYSTEMS --- | ||
| 25 | * The commands are grouped into the following subsystems. The subsystem | ||
| 26 | * code along with the opcode uniquely identify a particular fwcmd. | ||
| 27 | */ | ||
| 28 | #define FWCMD_SUBSYSTEM_RSVD (0) /* This subsystem is reserved. It is */ | ||
| 29 | /* never used. */ | ||
| 30 | #define FWCMD_SUBSYSTEM_COMMON (1) /* CMDs in this group are common to | ||
| 31 | * all subsystems. See | ||
| 32 | * COMMON_SUBSYSTEM_OPCODES for opcodes | ||
| 33 | * and Common Host Configuration CMDs | ||
| 34 | * for the FWCMD descriptions. | ||
| 35 | */ | ||
| 36 | #define FWCMD_SUBSYSTEM_COMMON_ISCSI (2) /* CMDs in this group are */ | ||
| 37 | /* | ||
| 38 | * common to Initiator and Target. See | ||
| 39 | * COMMON_ISCSI_SUBSYSTEM_OPCODES and | ||
| 40 | * Common iSCSI Initiator and Target | ||
| 41 | * CMDs for the command descriptions. | ||
| 42 | */ | ||
| 43 | #define FWCMD_SUBSYSTEM_ETH (3) /* This subsystem is used to | ||
| 44 | execute Ethernet commands. */ | ||
| 45 | |||
| 46 | #define FWCMD_SUBSYSTEM_TPM (4) /* This subsystem is used | ||
| 47 | to execute TPM commands. */ | ||
| 48 | #define FWCMD_SUBSYSTEM_PXE_UNDI (5) /* This subsystem is used | ||
| 49 | * to execute PXE | ||
| 50 | * and UNDI specific commands. | ||
| 51 | */ | ||
| 52 | |||
| 53 | #define FWCMD_SUBSYSTEM_ISCSI_INI (6) /* This subsystem is used to | ||
| 54 | execute ISCSI Initiator | ||
| 55 | specific commands. | ||
| 56 | */ | ||
| 57 | #define FWCMD_SUBSYSTEM_ISCSI_TGT (7) /* This subsystem is used | ||
| 58 | to execute iSCSI Target | ||
| 59 | specific commands.between | ||
| 60 | PTL and ARM firmware. | ||
| 61 | */ | ||
| 62 | #define FWCMD_SUBSYSTEM_MILI_PTL (8) /* This subsystem is used to | ||
| 63 | execute iSCSI Target specific | ||
| 64 | commands.between MILI | ||
| 65 | and PTL. */ | ||
| 66 | #define FWCMD_SUBSYSTEM_MILI_TMD (9) /* This subsystem is used to | ||
| 67 | execute iSCSI Target specific | ||
| 68 | commands between MILI | ||
| 69 | and TMD. */ | ||
| 70 | #define FWCMD_SUBSYSTEM_PROXY (11) /* This subsystem is used | ||
| 71 | to execute proxied commands | ||
| 72 | within the host at the | ||
| 73 | explicit request of a | ||
| 74 | non priviledged domain. | ||
| 75 | This 'subsystem' is entirely | ||
| 76 | virtual from the controller | ||
| 77 | and firmware perspective as | ||
| 78 | it is implemented in host | ||
| 79 | drivers. | ||
| 80 | */ | ||
| 81 | |||
| 82 | /* | ||
| 83 | * --- COMMON_SUBSYSTEM_OPCODES --- | ||
| 84 | * These opcodes are common to both networking and storage PCI | ||
| 85 | * functions. They are used to reserve resources and configure | ||
| 86 | * BladeEngine. These opcodes all use the FWCMD_SUBSYSTEM_COMMON | ||
| 87 | * subsystem code. | ||
| 88 | */ | ||
| 89 | #define OPCODE_COMMON_NTWK_MAC_QUERY (1) | ||
| 90 | #define SUBSYSTEM_COMMON_NTWK_MAC_QUERY (1) | ||
| 91 | #define SUBSYSTEM_COMMON_NTWK_MAC_SET (1) | ||
| 92 | #define SUBSYSTEM_COMMON_NTWK_MULTICAST_SET (1) | ||
| 93 | #define SUBSYSTEM_COMMON_NTWK_VLAN_CONFIG (1) | ||
| 94 | #define SUBSYSTEM_COMMON_NTWK_LINK_STATUS_QUERY (1) | ||
| 95 | #define SUBSYSTEM_COMMON_READ_FLASHROM (1) | ||
| 96 | #define SUBSYSTEM_COMMON_WRITE_FLASHROM (1) | ||
| 97 | #define SUBSYSTEM_COMMON_QUERY_MAX_FWCMD_BUFFER_SIZE (1) | ||
| 98 | #define SUBSYSTEM_COMMON_ADD_PAGE_TABLES (1) | ||
| 99 | #define SUBSYSTEM_COMMON_REMOVE_PAGE_TABLES (1) | ||
| 100 | #define SUBSYSTEM_COMMON_RING_DESTROY (1) | ||
| 101 | #define SUBSYSTEM_COMMON_CQ_CREATE (1) | ||
| 102 | #define SUBSYSTEM_COMMON_EQ_CREATE (1) | ||
| 103 | #define SUBSYSTEM_COMMON_ETH_RX_CREATE (1) | ||
| 104 | #define SUBSYSTEM_COMMON_ETH_TX_CREATE (1) | ||
| 105 | #define SUBSYSTEM_COMMON_ISCSI_DEFQ_CREATE (1) | ||
| 106 | #define SUBSYSTEM_COMMON_ISCSI_WRBQ_CREATE (1) | ||
| 107 | #define SUBSYSTEM_COMMON_MCC_CREATE (1) | ||
| 108 | #define SUBSYSTEM_COMMON_JELL_CONFIG (1) | ||
| 109 | #define SUBSYSTEM_COMMON_FORCE_FAILOVER (1) | ||
| 110 | #define SUBSYSTEM_COMMON_ADD_TEMPLATE_HEADER_BUFFERS (1) | ||
| 111 | #define SUBSYSTEM_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS (1) | ||
| 112 | #define SUBSYSTEM_COMMON_POST_ZERO_BUFFER (1) | ||
| 113 | #define SUBSYSTEM_COMMON_GET_QOS (1) | ||
| 114 | #define SUBSYSTEM_COMMON_SET_QOS (1) | ||
| 115 | #define SUBSYSTEM_COMMON_TCP_GET_STATISTICS (1) | ||
| 116 | #define SUBSYSTEM_COMMON_SEEPROM_READ (1) | ||
| 117 | #define SUBSYSTEM_COMMON_TCP_STATE_QUERY (1) | ||
| 118 | #define SUBSYSTEM_COMMON_GET_CNTL_ATTRIBUTES (1) | ||
| 119 | #define SUBSYSTEM_COMMON_NOP (1) | ||
| 120 | #define SUBSYSTEM_COMMON_NTWK_RX_FILTER (1) | ||
| 121 | #define SUBSYSTEM_COMMON_GET_FW_VERSION (1) | ||
| 122 | #define SUBSYSTEM_COMMON_SET_FLOW_CONTROL (1) | ||
| 123 | #define SUBSYSTEM_COMMON_GET_FLOW_CONTROL (1) | ||
| 124 | #define SUBSYSTEM_COMMON_SET_TCP_PARAMETERS (1) | ||
| 125 | #define SUBSYSTEM_COMMON_SET_FRAME_SIZE (1) | ||
| 126 | #define SUBSYSTEM_COMMON_GET_FAT (1) | ||
| 127 | #define SUBSYSTEM_COMMON_MODIFY_EQ_DELAY (1) | ||
| 128 | #define SUBSYSTEM_COMMON_FIRMWARE_CONFIG (1) | ||
| 129 | #define SUBSYSTEM_COMMON_ENABLE_DISABLE_DOMAINS (1) | ||
| 130 | #define SUBSYSTEM_COMMON_GET_DOMAIN_CONFIG (1) | ||
| 131 | #define SUBSYSTEM_COMMON_SET_VLD_CONFIG (1) | ||
| 132 | #define SUBSYSTEM_COMMON_GET_VLD_CONFIG (1) | ||
| 133 | #define SUBSYSTEM_COMMON_GET_PORT_EQUALIZATION (1) | ||
| 134 | #define SUBSYSTEM_COMMON_SET_PORT_EQUALIZATION (1) | ||
| 135 | #define SUBSYSTEM_COMMON_RED_CONFIG (1) | ||
| 136 | #define OPCODE_COMMON_NTWK_MAC_SET (2) | ||
| 137 | #define OPCODE_COMMON_NTWK_MULTICAST_SET (3) | ||
| 138 | #define OPCODE_COMMON_NTWK_VLAN_CONFIG (4) | ||
| 139 | #define OPCODE_COMMON_NTWK_LINK_STATUS_QUERY (5) | ||
| 140 | #define OPCODE_COMMON_READ_FLASHROM (6) | ||
| 141 | #define OPCODE_COMMON_WRITE_FLASHROM (7) | ||
| 142 | #define OPCODE_COMMON_QUERY_MAX_FWCMD_BUFFER_SIZE (8) | ||
| 143 | #define OPCODE_COMMON_ADD_PAGE_TABLES (9) | ||
| 144 | #define OPCODE_COMMON_REMOVE_PAGE_TABLES (10) | ||
| 145 | #define OPCODE_COMMON_RING_DESTROY (11) | ||
| 146 | #define OPCODE_COMMON_CQ_CREATE (12) | ||
| 147 | #define OPCODE_COMMON_EQ_CREATE (13) | ||
| 148 | #define OPCODE_COMMON_ETH_RX_CREATE (14) | ||
| 149 | #define OPCODE_COMMON_ETH_TX_CREATE (15) | ||
| 150 | #define OPCODE_COMMON_NET_RESERVED0 (16) /* Reserved */ | ||
| 151 | #define OPCODE_COMMON_NET_RESERVED1 (17) /* Reserved */ | ||
| 152 | #define OPCODE_COMMON_NET_RESERVED2 (18) /* Reserved */ | ||
| 153 | #define OPCODE_COMMON_ISCSI_DEFQ_CREATE (19) | ||
| 154 | #define OPCODE_COMMON_ISCSI_WRBQ_CREATE (20) | ||
| 155 | #define OPCODE_COMMON_MCC_CREATE (21) | ||
| 156 | #define OPCODE_COMMON_JELL_CONFIG (22) | ||
| 157 | #define OPCODE_COMMON_FORCE_FAILOVER (23) | ||
| 158 | #define OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS (24) | ||
| 159 | #define OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS (25) | ||
| 160 | #define OPCODE_COMMON_POST_ZERO_BUFFER (26) | ||
| 161 | #define OPCODE_COMMON_GET_QOS (27) | ||
| 162 | #define OPCODE_COMMON_SET_QOS (28) | ||
| 163 | #define OPCODE_COMMON_TCP_GET_STATISTICS (29) | ||
| 164 | #define OPCODE_COMMON_SEEPROM_READ (30) | ||
| 165 | #define OPCODE_COMMON_TCP_STATE_QUERY (31) | ||
| 166 | #define OPCODE_COMMON_GET_CNTL_ATTRIBUTES (32) | ||
| 167 | #define OPCODE_COMMON_NOP (33) | ||
| 168 | #define OPCODE_COMMON_NTWK_RX_FILTER (34) | ||
| 169 | #define OPCODE_COMMON_GET_FW_VERSION (35) | ||
| 170 | #define OPCODE_COMMON_SET_FLOW_CONTROL (36) | ||
| 171 | #define OPCODE_COMMON_GET_FLOW_CONTROL (37) | ||
| 172 | #define OPCODE_COMMON_SET_TCP_PARAMETERS (38) | ||
| 173 | #define OPCODE_COMMON_SET_FRAME_SIZE (39) | ||
| 174 | #define OPCODE_COMMON_GET_FAT (40) | ||
| 175 | #define OPCODE_COMMON_MODIFY_EQ_DELAY (41) | ||
| 176 | #define OPCODE_COMMON_FIRMWARE_CONFIG (42) | ||
| 177 | #define OPCODE_COMMON_ENABLE_DISABLE_DOMAINS (43) | ||
| 178 | #define OPCODE_COMMON_GET_DOMAIN_CONFIG (44) | ||
| 179 | #define OPCODE_COMMON_SET_VLD_CONFIG (45) | ||
| 180 | #define OPCODE_COMMON_GET_VLD_CONFIG (46) | ||
| 181 | #define OPCODE_COMMON_GET_PORT_EQUALIZATION (47) | ||
| 182 | #define OPCODE_COMMON_SET_PORT_EQUALIZATION (48) | ||
| 183 | #define OPCODE_COMMON_RED_CONFIG (49) | ||
| 184 | |||
| 185 | |||
| 186 | |||
| 187 | /* | ||
| 188 | * --- ETH_SUBSYSTEM_OPCODES --- | ||
| 189 | * These opcodes are used for configuring the Ethernet interfaces. These | ||
| 190 | * opcodes all use the FWCMD_SUBSYSTEM_ETH subsystem code. | ||
| 191 | */ | ||
| 192 | #define OPCODE_ETH_RSS_CONFIG (1) | ||
| 193 | #define OPCODE_ETH_ACPI_CONFIG (2) | ||
| 194 | #define SUBSYSTEM_ETH_RSS_CONFIG (3) | ||
| 195 | #define SUBSYSTEM_ETH_ACPI_CONFIG (3) | ||
| 196 | #define OPCODE_ETH_PROMISCUOUS (3) | ||
| 197 | #define SUBSYSTEM_ETH_PROMISCUOUS (3) | ||
| 198 | #define SUBSYSTEM_ETH_GET_STATISTICS (3) | ||
| 199 | #define SUBSYSTEM_ETH_GET_RX_FRAG_SIZE (3) | ||
| 200 | #define SUBSYSTEM_ETH_SET_RX_FRAG_SIZE (3) | ||
| 201 | #define OPCODE_ETH_GET_STATISTICS (4) | ||
| 202 | #define OPCODE_ETH_GET_RX_FRAG_SIZE (5) | ||
| 203 | #define OPCODE_ETH_SET_RX_FRAG_SIZE (6) | ||
| 204 | |||
| 205 | |||
| 206 | |||
| 207 | |||
| 208 | |||
| 209 | /* | ||
| 210 | * --- MCC_STATUS_CODE --- | ||
| 211 | * These are the global status codes used by all subsystems | ||
| 212 | */ | ||
| 213 | #define MCC_STATUS_SUCCESS (0) /* Indicates a successful | ||
| 214 | completion of the command */ | ||
| 215 | #define MCC_STATUS_INSUFFICIENT_PRIVILEGES (1) /* The client does not have | ||
| 216 | sufficient privileges to | ||
| 217 | execute the command */ | ||
| 218 | #define MCC_STATUS_INVALID_PARAMETER (2) /* A parameter in the command | ||
| 219 | was invalid. The extended | ||
| 220 | status contains the index | ||
| 221 | of the parameter */ | ||
| 222 | #define MCC_STATUS_INSUFFICIENT_RESOURCES (3) /* There are insufficient | ||
| 223 | chip resources to execute | ||
| 224 | the command */ | ||
| 225 | #define MCC_STATUS_QUEUE_FLUSHING (4) /* The command is completing | ||
| 226 | because the queue was | ||
| 227 | getting flushed */ | ||
| 228 | #define MCC_STATUS_DMA_FAILED (5) /* The command is completing | ||
| 229 | with a DMA error */ | ||
| 230 | |||
| 231 | /* | ||
| 232 | * --- MGMT_ERROR_CODES --- | ||
| 233 | * Error Codes returned in the status field of the FWCMD response header | ||
| 234 | */ | ||
| 235 | #define MGMT_STATUS_SUCCESS (0) /* The FWCMD completed | ||
| 236 | without errors */ | ||
| 237 | #define MGMT_STATUS_FAILED (1) /* Error status in the Status | ||
| 238 | field of the | ||
| 239 | struct FWCMD_RESPONSE_HEADER */ | ||
| 240 | #define MGMT_STATUS_ILLEGAL_REQUEST (2) /* Invalid FWCMD opcode */ | ||
| 241 | #define MGMT_STATUS_ILLEGAL_FIELD (3) /* Invalid parameter in | ||
| 242 | the FWCMD payload */ | ||
| 243 | |||
| 244 | #endif /* __fwcmd_opcodes_amap_h__ */ | ||
diff --git a/drivers/staging/benet/fwcmd_types_bmap.h b/drivers/staging/benet/fwcmd_types_bmap.h deleted file mode 100644 index 92217aff3a16..000000000000 --- a/drivers/staging/benet/fwcmd_types_bmap.h +++ /dev/null | |||
| @@ -1,29 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __fwcmd_types_bmap_h__ | ||
| 21 | #define __fwcmd_types_bmap_h__ | ||
| 22 | |||
| 23 | /* MAC address format */ | ||
| 24 | struct MAC_ADDRESS_FORMAT { | ||
| 25 | u16 SizeOfStructure; | ||
| 26 | u8 MACAddress[6]; | ||
| 27 | } __packed; | ||
| 28 | |||
| 29 | #endif /* __fwcmd_types_bmap_h__ */ | ||
diff --git a/drivers/staging/benet/host_struct.h b/drivers/staging/benet/host_struct.h deleted file mode 100644 index 3de6722b980f..000000000000 --- a/drivers/staging/benet/host_struct.h +++ /dev/null | |||
| @@ -1,182 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __host_struct_amap_h__ | ||
| 21 | #define __host_struct_amap_h__ | ||
| 22 | #include "be_cm.h" | ||
| 23 | #include "be_common.h" | ||
| 24 | #include "descriptors.h" | ||
| 25 | |||
| 26 | /* --- EQ_COMPLETION_MAJOR_CODE_ENUM --- */ | ||
| 27 | #define EQ_MAJOR_CODE_COMPLETION (0) /* Completion event on a */ | ||
| 28 | /* qcompletion ueue. */ | ||
| 29 | #define EQ_MAJOR_CODE_ETH (1) /* Affiliated Ethernet Event. */ | ||
| 30 | #define EQ_MAJOR_CODE_RESERVED (2) /* Reserved */ | ||
| 31 | #define EQ_MAJOR_CODE_RDMA (3) /* Affiliated RDMA Event. */ | ||
| 32 | #define EQ_MAJOR_CODE_ISCSI (4) /* Affiliated ISCSI Event */ | ||
| 33 | #define EQ_MAJOR_CODE_UNAFFILIATED (5) /* Unaffiliated Event */ | ||
| 34 | |||
| 35 | /* --- EQ_COMPLETION_MINOR_CODE_ENUM --- */ | ||
| 36 | #define EQ_MINOR_CODE_COMPLETION (0) /* Completion event on a */ | ||
| 37 | /* completion queue. */ | ||
| 38 | #define EQ_MINOR_CODE_OTHER (1) /* Other Event (TBD). */ | ||
| 39 | |||
| 40 | /* Queue Entry Definition for all 4 byte event queue types. */ | ||
| 41 | struct BE_EQ_ENTRY_AMAP { | ||
| 42 | u8 Valid; /* DWORD 0 */ | ||
| 43 | u8 MajorCode[3]; /* DWORD 0 */ | ||
| 44 | u8 MinorCode[12]; /* DWORD 0 */ | ||
| 45 | u8 ResourceID[16]; /* DWORD 0 */ | ||
| 46 | } __packed; | ||
| 47 | struct EQ_ENTRY_AMAP { | ||
| 48 | u32 dw[1]; | ||
| 49 | }; | ||
| 50 | |||
| 51 | /* | ||
| 52 | * --- ETH_EVENT_CODE --- | ||
| 53 | * These codes are returned by the MPU when one of these events has occurred, | ||
| 54 | * and the event is configured to report to an Event Queue when an event | ||
| 55 | * is detected. | ||
| 56 | */ | ||
| 57 | #define ETH_EQ_LINK_STATUS (0) /* Link status change event */ | ||
| 58 | /* detected. */ | ||
| 59 | #define ETH_EQ_WATERMARK (1) /* watermark event detected. */ | ||
| 60 | #define ETH_EQ_MAGIC_PKT (2) /* magic pkt event detected. */ | ||
| 61 | #define ETH_EQ_ACPI_PKT0 (3) /* ACPI interesting packet */ | ||
| 62 | /* detected. */ | ||
| 63 | #define ETH_EQ_ACPI_PKT1 (3) /* ACPI interesting packet */ | ||
| 64 | /* detected. */ | ||
| 65 | #define ETH_EQ_ACPI_PKT2 (3) /* ACPI interesting packet */ | ||
| 66 | /* detected. */ | ||
| 67 | #define ETH_EQ_ACPI_PKT3 (3) /* ACPI interesting packet */ | ||
| 68 | /* detected. */ | ||
| 69 | |||
| 70 | /* | ||
| 71 | * --- ETH_TX_COMPL_STATUS_ENUM --- | ||
| 72 | * Status codes contained in Ethernet TX completion descriptors. | ||
| 73 | */ | ||
| 74 | #define ETH_COMP_VALID (0) | ||
| 75 | #define ETH_COMP_ERROR (1) | ||
| 76 | #define ETH_COMP_INVALID (15) | ||
| 77 | |||
| 78 | /* | ||
| 79 | * --- ETH_TX_COMPL_PORT_ENUM --- | ||
| 80 | * Port indicator contained in Ethernet TX completion descriptors. | ||
| 81 | */ | ||
| 82 | #define ETH_COMP_PORT0 (0) | ||
| 83 | #define ETH_COMP_PORT1 (1) | ||
| 84 | #define ETH_COMP_MGMT (2) | ||
| 85 | |||
| 86 | /* | ||
| 87 | * --- ETH_TX_COMPL_CT_ENUM --- | ||
| 88 | * Completion type indicator contained in Ethernet TX completion descriptors. | ||
| 89 | */ | ||
| 90 | #define ETH_COMP_ETH (0) | ||
| 91 | |||
| 92 | /* | ||
| 93 | * Work request block that the driver issues to the chip for | ||
| 94 | * Ethernet transmissions. All control fields must be valid in each WRB for | ||
| 95 | * a message. The controller, as specified by the flags, optionally writes | ||
| 96 | * an entry to the Completion Ring and generate an event. | ||
| 97 | */ | ||
| 98 | struct BE_ETH_WRB_AMAP { | ||
| 99 | u8 frag_pa_hi[32]; /* DWORD 0 */ | ||
| 100 | u8 frag_pa_lo[32]; /* DWORD 1 */ | ||
| 101 | u8 complete; /* DWORD 2 */ | ||
| 102 | u8 event; /* DWORD 2 */ | ||
| 103 | u8 crc; /* DWORD 2 */ | ||
| 104 | u8 forward; /* DWORD 2 */ | ||
| 105 | u8 ipsec; /* DWORD 2 */ | ||
| 106 | u8 mgmt; /* DWORD 2 */ | ||
| 107 | u8 ipcs; /* DWORD 2 */ | ||
| 108 | u8 udpcs; /* DWORD 2 */ | ||
| 109 | u8 tcpcs; /* DWORD 2 */ | ||
| 110 | u8 lso; /* DWORD 2 */ | ||
| 111 | u8 last; /* DWORD 2 */ | ||
| 112 | u8 vlan; /* DWORD 2 */ | ||
| 113 | u8 dbg[3]; /* DWORD 2 */ | ||
| 114 | u8 hash_val[3]; /* DWORD 2 */ | ||
| 115 | u8 lso_mss[14]; /* DWORD 2 */ | ||
| 116 | u8 frag_len[16]; /* DWORD 3 */ | ||
| 117 | u8 vlan_tag[16]; /* DWORD 3 */ | ||
| 118 | } __packed; | ||
| 119 | struct ETH_WRB_AMAP { | ||
| 120 | u32 dw[4]; | ||
| 121 | }; | ||
| 122 | |||
| 123 | /* This is an Ethernet transmit completion descriptor */ | ||
| 124 | struct BE_ETH_TX_COMPL_AMAP { | ||
| 125 | u8 user_bytes[16]; /* DWORD 0 */ | ||
| 126 | u8 nwh_bytes[8]; /* DWORD 0 */ | ||
| 127 | u8 lso; /* DWORD 0 */ | ||
| 128 | u8 rsvd0[7]; /* DWORD 0 */ | ||
| 129 | u8 wrb_index[16]; /* DWORD 1 */ | ||
| 130 | u8 ct[2]; /* DWORD 1 */ | ||
| 131 | u8 port[2]; /* DWORD 1 */ | ||
| 132 | u8 rsvd1[8]; /* DWORD 1 */ | ||
| 133 | u8 status[4]; /* DWORD 1 */ | ||
| 134 | u8 rsvd2[16]; /* DWORD 2 */ | ||
| 135 | u8 ringid[11]; /* DWORD 2 */ | ||
| 136 | u8 hash_val[4]; /* DWORD 2 */ | ||
| 137 | u8 valid; /* DWORD 2 */ | ||
| 138 | u8 rsvd3[32]; /* DWORD 3 */ | ||
| 139 | } __packed; | ||
| 140 | struct ETH_TX_COMPL_AMAP { | ||
| 141 | u32 dw[4]; | ||
| 142 | }; | ||
| 143 | |||
| 144 | /* Ethernet Receive Buffer descriptor */ | ||
| 145 | struct BE_ETH_RX_D_AMAP { | ||
| 146 | u8 fragpa_hi[32]; /* DWORD 0 */ | ||
| 147 | u8 fragpa_lo[32]; /* DWORD 1 */ | ||
| 148 | } __packed; | ||
| 149 | struct ETH_RX_D_AMAP { | ||
| 150 | u32 dw[2]; | ||
| 151 | }; | ||
| 152 | |||
| 153 | /* This is an Ethernet Receive Completion Descriptor */ | ||
| 154 | struct BE_ETH_RX_COMPL_AMAP { | ||
| 155 | u8 vlan_tag[16]; /* DWORD 0 */ | ||
| 156 | u8 pktsize[14]; /* DWORD 0 */ | ||
| 157 | u8 port; /* DWORD 0 */ | ||
| 158 | u8 rsvd0; /* DWORD 0 */ | ||
| 159 | u8 err; /* DWORD 1 */ | ||
| 160 | u8 rsshp; /* DWORD 1 */ | ||
| 161 | u8 ipf; /* DWORD 1 */ | ||
| 162 | u8 tcpf; /* DWORD 1 */ | ||
| 163 | u8 udpf; /* DWORD 1 */ | ||
| 164 | u8 ipcksm; /* DWORD 1 */ | ||
| 165 | u8 tcpcksm; /* DWORD 1 */ | ||
| 166 | u8 udpcksm; /* DWORD 1 */ | ||
| 167 | u8 macdst[6]; /* DWORD 1 */ | ||
| 168 | u8 vtp; /* DWORD 1 */ | ||
| 169 | u8 vtm; /* DWORD 1 */ | ||
| 170 | u8 fragndx[10]; /* DWORD 1 */ | ||
| 171 | u8 ct[2]; /* DWORD 1 */ | ||
| 172 | u8 ipsec; /* DWORD 1 */ | ||
| 173 | u8 numfrags[3]; /* DWORD 1 */ | ||
| 174 | u8 rsvd1[31]; /* DWORD 2 */ | ||
| 175 | u8 valid; /* DWORD 2 */ | ||
| 176 | u8 rsshash[32]; /* DWORD 3 */ | ||
| 177 | } __packed; | ||
| 178 | struct ETH_RX_COMPL_AMAP { | ||
| 179 | u32 dw[4]; | ||
| 180 | }; | ||
| 181 | |||
| 182 | #endif /* __host_struct_amap_h__ */ | ||
diff --git a/drivers/staging/benet/hwlib.h b/drivers/staging/benet/hwlib.h deleted file mode 100644 index afedf4dc5903..000000000000 --- a/drivers/staging/benet/hwlib.h +++ /dev/null | |||
| @@ -1,830 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | #ifndef __hwlib_h__ | ||
| 18 | #define __hwlib_h__ | ||
| 19 | |||
| 20 | #include <linux/module.h> | ||
| 21 | #include <linux/io.h> | ||
| 22 | #include <linux/list.h> | ||
| 23 | #include <linux/spinlock.h> | ||
| 24 | |||
| 25 | #include "regmap.h" /* srcgen array map output */ | ||
| 26 | |||
| 27 | #include "asyncmesg.h" | ||
| 28 | #include "fwcmd_opcodes.h" | ||
| 29 | #include "post_codes.h" | ||
| 30 | #include "fwcmd_mcc.h" | ||
| 31 | |||
| 32 | #include "fwcmd_types_bmap.h" | ||
| 33 | #include "fwcmd_common_bmap.h" | ||
| 34 | #include "fwcmd_eth_bmap.h" | ||
| 35 | #include "bestatus.h" | ||
| 36 | /* | ||
| 37 | * | ||
| 38 | * Macros for reading/writing a protection domain or CSR registers | ||
| 39 | * in BladeEngine. | ||
| 40 | */ | ||
| 41 | #define PD_READ(fo, field) ioread32((fo)->db_va + \ | ||
| 42 | offsetof(struct BE_PROTECTION_DOMAIN_DBMAP_AMAP, field)/8) | ||
| 43 | |||
| 44 | #define PD_WRITE(fo, field, val) iowrite32(val, (fo)->db_va + \ | ||
| 45 | offsetof(struct BE_PROTECTION_DOMAIN_DBMAP_AMAP, field)/8) | ||
| 46 | |||
| 47 | #define CSR_READ(fo, field) ioread32((fo)->csr_va + \ | ||
| 48 | offsetof(struct BE_BLADE_ENGINE_CSRMAP_AMAP, field)/8) | ||
| 49 | |||
| 50 | #define CSR_WRITE(fo, field, val) iowrite32(val, (fo)->csr_va + \ | ||
| 51 | offsetof(struct BE_BLADE_ENGINE_CSRMAP_AMAP, field)/8) | ||
| 52 | |||
| 53 | #define PCICFG0_READ(fo, field) ioread32((fo)->pci_va + \ | ||
| 54 | offsetof(struct BE_PCICFG0_CSRMAP_AMAP, field)/8) | ||
| 55 | |||
| 56 | #define PCICFG0_WRITE(fo, field, val) iowrite32(val, (fo)->pci_va + \ | ||
| 57 | offsetof(struct BE_PCICFG0_CSRMAP_AMAP, field)/8) | ||
| 58 | |||
| 59 | #define PCICFG1_READ(fo, field) ioread32((fo)->pci_va + \ | ||
| 60 | offsetof(struct BE_PCICFG1_CSRMAP_AMAP, field)/8) | ||
| 61 | |||
| 62 | #define PCICFG1_WRITE(fo, field, val) iowrite32(val, (fo)->pci_va + \ | ||
| 63 | offsetof(struct BE_PCICFG1_CSRMAP_AMAP, field)/8) | ||
| 64 | |||
| 65 | #ifdef BE_DEBUG | ||
| 66 | #define ASSERT(c) BUG_ON(!(c)); | ||
| 67 | #else | ||
| 68 | #define ASSERT(c) | ||
| 69 | #endif | ||
| 70 | |||
| 71 | /* debug levels */ | ||
| 72 | enum BE_DEBUG_LEVELS { | ||
| 73 | DL_ALWAYS = 0, /* cannot be masked */ | ||
| 74 | DL_ERR = 0x1, /* errors that should never happen */ | ||
| 75 | DL_WARN = 0x2, /* something questionable. | ||
| 76 | recoverable errors */ | ||
| 77 | DL_NOTE = 0x4, /* infrequent, important debug info */ | ||
| 78 | DL_INFO = 0x8, /* debug information */ | ||
| 79 | DL_VERBOSE = 0x10, /* detailed info, such as buffer traces */ | ||
| 80 | BE_DL_MIN_VALUE = 0x1, /* this is the min value used */ | ||
| 81 | BE_DL_MAX_VALUE = 0x80 /* this is the higheset value used */ | ||
| 82 | } ; | ||
| 83 | |||
| 84 | extern unsigned int trace_level; | ||
| 85 | |||
| 86 | #define TRACE(lm, fmt, args...) { \ | ||
| 87 | if (trace_level & lm) { \ | ||
| 88 | printk(KERN_NOTICE "BE: %s:%d \n" fmt, \ | ||
| 89 | __FILE__ , __LINE__ , ## args); \ | ||
| 90 | } \ | ||
| 91 | } | ||
| 92 | |||
| 93 | static inline unsigned int be_trace_set_level(unsigned int level) | ||
| 94 | { | ||
| 95 | unsigned int old_level = trace_level; | ||
| 96 | trace_level = level; | ||
| 97 | return old_level; | ||
| 98 | } | ||
| 99 | |||
| 100 | #define be_trace_get_level() trace_level | ||
| 101 | /* | ||
| 102 | * Returns number of pages spanned by the size of data | ||
| 103 | * starting at the given address. | ||
| 104 | */ | ||
| 105 | #define PAGES_SPANNED(_address, _size) \ | ||
| 106 | ((u32)((((size_t)(_address) & (PAGE_SIZE - 1)) + \ | ||
| 107 | (_size) + (PAGE_SIZE - 1)) >> PAGE_SHIFT)) | ||
| 108 | /* Byte offset into the page corresponding to given address */ | ||
| 109 | #define OFFSET_IN_PAGE(_addr_) ((size_t)(_addr_) & (PAGE_SIZE-1)) | ||
| 110 | |||
| 111 | /* | ||
| 112 | * circular subtract. | ||
| 113 | * Returns a - b assuming a circular number system, where a and b are | ||
| 114 | * in range (0, maxValue-1). If a==b, zero is returned so the | ||
| 115 | * highest value possible with this subtraction is maxValue-1. | ||
| 116 | */ | ||
| 117 | static inline u32 be_subc(u32 a, u32 b, u32 max) | ||
| 118 | { | ||
| 119 | ASSERT(a <= max && b <= max); | ||
| 120 | ASSERT(max > 0); | ||
| 121 | return a >= b ? (a - b) : (max - b + a); | ||
| 122 | } | ||
| 123 | |||
| 124 | static inline u32 be_addc(u32 a, u32 b, u32 max) | ||
| 125 | { | ||
| 126 | ASSERT(a < max); | ||
| 127 | ASSERT(max > 0); | ||
| 128 | return (max - a > b) ? (a + b) : (b + a - max); | ||
| 129 | } | ||
| 130 | |||
| 131 | /* descriptor for a physically contiguous memory used for ring */ | ||
| 132 | struct ring_desc { | ||
| 133 | u32 length; /* length in bytes */ | ||
| 134 | void *va; /* virtual address */ | ||
| 135 | u64 pa; /* bus address */ | ||
| 136 | } ; | ||
| 137 | |||
| 138 | /* | ||
| 139 | * This structure stores information about a ring shared between hardware | ||
| 140 | * and software. Each ring is allocated by the driver in the uncached | ||
| 141 | * extension and mapped into BladeEngine's unified table. | ||
| 142 | */ | ||
| 143 | struct mp_ring { | ||
| 144 | u32 pages; /* queue size in pages */ | ||
| 145 | u32 id; /* queue id assigned by beklib */ | ||
| 146 | u32 num; /* number of elements in queue */ | ||
| 147 | u32 cidx; /* consumer index */ | ||
| 148 | u32 pidx; /* producer index -- not used by most rings */ | ||
| 149 | u32 itemSize; /* size in bytes of one object */ | ||
| 150 | |||
| 151 | void *va; /* The virtual address of the ring. | ||
| 152 | This should be last to allow 32 & 64 | ||
| 153 | bit debugger extensions to work. */ | ||
| 154 | } ; | ||
| 155 | |||
| 156 | /*----------- amap bit filed get / set macros and functions -----*/ | ||
| 157 | /* | ||
| 158 | * Structures defined in the map header files (under fw/amap/) with names | ||
| 159 | * in the format BE_<name>_AMAP are pseudo structures with members | ||
| 160 | * of type u8. These structures are templates that are used in | ||
| 161 | * conjuntion with the structures with names in the format | ||
| 162 | * <name>_AMAP to calculate the bit masks and bit offsets to get or set | ||
| 163 | * bit fields in structures. The structures <name>_AMAP are arrays | ||
| 164 | * of 32 bits words and have the correct size. The following macros | ||
| 165 | * provide convenient ways to get and set the various members | ||
| 166 | * in the structures without using strucctures with bit fields. | ||
| 167 | * Always use the macros AMAP_GET_BITS_PTR and AMAP_SET_BITS_PTR | ||
| 168 | * macros to extract and set various members. | ||
| 169 | */ | ||
| 170 | |||
| 171 | /* | ||
| 172 | * Returns the a bit mask for the register that is NOT shifted into location. | ||
| 173 | * That means return values always look like: 0x1, 0xFF, 0x7FF, etc... | ||
| 174 | */ | ||
| 175 | static inline u32 amap_mask(u32 bit_size) | ||
| 176 | { | ||
| 177 | return bit_size == 32 ? 0xFFFFFFFF : (1 << bit_size) - 1; | ||
| 178 | } | ||
| 179 | |||
| 180 | #define AMAP_BIT_MASK(_struct_, field) \ | ||
| 181 | amap_mask(AMAP_BIT_SIZE(_struct_, field)) | ||
| 182 | |||
| 183 | /* | ||
| 184 | * non-optimized set bits function. First clears the bits and then assigns them. | ||
| 185 | * This does not require knowledge of the particular DWORD you are setting. | ||
| 186 | * e.g. AMAP_SET_BITS_PTR (struct, field1, &contextMemory, 123); | ||
| 187 | */ | ||
| 188 | static inline void | ||
| 189 | amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value) | ||
| 190 | { | ||
| 191 | u32 *dw = (u32 *)ptr; | ||
| 192 | *(dw + dw_offset) &= ~(mask << offset); | ||
| 193 | *(dw + dw_offset) |= (mask & value) << offset; | ||
| 194 | } | ||
| 195 | |||
| 196 | #define AMAP_SET_BITS_PTR(_struct_, field, _structPtr_, val) \ | ||
| 197 | amap_set(_structPtr_, AMAP_WORD_OFFSET(_struct_, field),\ | ||
| 198 | AMAP_BIT_MASK(_struct_, field), \ | ||
| 199 | AMAP_BIT_OFFSET(_struct_, field), val) | ||
| 200 | /* | ||
| 201 | * Non-optimized routine that gets the bits without knowing the correct DWORD. | ||
| 202 | * e.g. fieldValue = AMAP_GET_BITS_PTR (struct, field1, &contextMemory); | ||
| 203 | */ | ||
| 204 | static inline u32 | ||
| 205 | amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset) | ||
| 206 | { | ||
| 207 | u32 *dw = (u32 *)ptr; | ||
| 208 | return mask & (*(dw + dw_offset) >> offset); | ||
| 209 | } | ||
| 210 | #define AMAP_GET_BITS_PTR(_struct_, field, _structPtr_) \ | ||
| 211 | amap_get(_structPtr_, AMAP_WORD_OFFSET(_struct_, field), \ | ||
| 212 | AMAP_BIT_MASK(_struct_, field), \ | ||
| 213 | AMAP_BIT_OFFSET(_struct_, field)) | ||
| 214 | |||
| 215 | /* Returns 0-31 representing bit offset within a DWORD of a bitfield. */ | ||
| 216 | #define AMAP_BIT_OFFSET(_struct_, field) \ | ||
| 217 | (offsetof(struct BE_ ## _struct_ ## _AMAP, field) % 32) | ||
| 218 | |||
| 219 | /* Returns 0-n representing DWORD offset of bitfield within the structure. */ | ||
| 220 | #define AMAP_WORD_OFFSET(_struct_, field) \ | ||
| 221 | (offsetof(struct BE_ ## _struct_ ## _AMAP, field)/32) | ||
| 222 | |||
| 223 | /* Returns size of bitfield in bits. */ | ||
| 224 | #define AMAP_BIT_SIZE(_struct_, field) \ | ||
| 225 | sizeof(((struct BE_ ## _struct_ ## _AMAP*)0)->field) | ||
| 226 | |||
| 227 | struct be_mcc_wrb_response_copy { | ||
| 228 | u16 length; /* bytes in response */ | ||
| 229 | u16 fwcmd_offset; /* offset within the wrb of the response */ | ||
| 230 | void *va; /* user's va to copy response into */ | ||
| 231 | |||
| 232 | } ; | ||
| 233 | typedef void (*mcc_wrb_cqe_callback) (void *context, int status, | ||
| 234 | struct MCC_WRB_AMAP *optional_wrb); | ||
| 235 | struct be_mcc_wrb_context { | ||
| 236 | |||
| 237 | mcc_wrb_cqe_callback internal_cb; /* Function to call on | ||
| 238 | completion */ | ||
| 239 | void *internal_cb_context; /* Parameter to pass | ||
| 240 | to completion function */ | ||
| 241 | |||
| 242 | mcc_wrb_cqe_callback cb; /* Function to call on completion */ | ||
| 243 | void *cb_context; /* Parameter to pass to completion function */ | ||
| 244 | |||
| 245 | int *users_final_status; /* pointer to a local | ||
| 246 | variable for synchronous | ||
| 247 | commands */ | ||
| 248 | struct MCC_WRB_AMAP *wrb; /* pointer to original wrb for embedded | ||
| 249 | commands only */ | ||
| 250 | struct list_head next; /* links context structs together in | ||
| 251 | free list */ | ||
| 252 | |||
| 253 | struct be_mcc_wrb_response_copy copy; /* Optional parameters to copy | ||
| 254 | embedded response to user's va */ | ||
| 255 | |||
| 256 | #if defined(BE_DEBUG) | ||
| 257 | u16 subsystem, opcode; /* Track this FWCMD for debug builds. */ | ||
| 258 | struct MCC_WRB_AMAP *ring_wrb; | ||
| 259 | u32 consumed_count; | ||
| 260 | #endif | ||
| 261 | } ; | ||
| 262 | |||
| 263 | /* | ||
| 264 | Represents a function object for network or storage. This | ||
| 265 | is used to manage per-function resources like MCC CQs, etc. | ||
| 266 | */ | ||
| 267 | struct be_function_object { | ||
| 268 | |||
| 269 | u32 magic; /*!< magic for detecting memory corruption. */ | ||
| 270 | |||
| 271 | /* PCI BAR mapped addresses */ | ||
| 272 | u8 __iomem *csr_va; /* CSR */ | ||
| 273 | u8 __iomem *db_va; /* Door Bell */ | ||
| 274 | u8 __iomem *pci_va; /* PCI config space */ | ||
| 275 | u32 emulate; /* if set, MPU is not available. | ||
| 276 | Emulate everything. */ | ||
| 277 | u32 pend_queue_driving; /* if set, drive the queued WRBs | ||
| 278 | after releasing the WRB lock */ | ||
| 279 | |||
| 280 | spinlock_t post_lock; /* lock for verifying one thread posting wrbs */ | ||
| 281 | spinlock_t cq_lock; /* lock for verifying one thread | ||
| 282 | processing cq */ | ||
| 283 | spinlock_t mcc_context_lock; /* lock for protecting mcc | ||
| 284 | context free list */ | ||
| 285 | unsigned long post_irq; | ||
| 286 | unsigned long cq_irq; | ||
| 287 | |||
| 288 | u32 type; | ||
| 289 | u32 pci_function_number; | ||
| 290 | |||
| 291 | struct be_mcc_object *mcc; /* mcc rings. */ | ||
| 292 | |||
| 293 | struct { | ||
| 294 | struct MCC_MAILBOX_AMAP *va; /* VA to the mailbox */ | ||
| 295 | u64 pa; /* PA to the mailbox */ | ||
| 296 | u32 length; /* byte length of mailbox */ | ||
| 297 | |||
| 298 | /* One default context struct used for posting at | ||
| 299 | * least one MCC_WRB | ||
| 300 | */ | ||
| 301 | struct be_mcc_wrb_context default_context; | ||
| 302 | bool default_context_allocated; | ||
| 303 | } mailbox; | ||
| 304 | |||
| 305 | struct { | ||
| 306 | |||
| 307 | /* Wake on lans configured. */ | ||
| 308 | u32 wol_bitmask; /* bits 0,1,2,3 are set if | ||
| 309 | corresponding index is enabled */ | ||
| 310 | } config; | ||
| 311 | |||
| 312 | |||
| 313 | struct BE_FIRMWARE_CONFIG fw_config; | ||
| 314 | } ; | ||
| 315 | |||
| 316 | /* | ||
| 317 | Represents an Event Queue | ||
| 318 | */ | ||
| 319 | struct be_eq_object { | ||
| 320 | u32 magic; | ||
| 321 | atomic_t ref_count; | ||
| 322 | |||
| 323 | struct be_function_object *parent_function; | ||
| 324 | |||
| 325 | struct list_head eq_list; | ||
| 326 | struct list_head cq_list_head; | ||
| 327 | |||
| 328 | u32 eq_id; | ||
| 329 | void *cb_context; | ||
| 330 | |||
| 331 | } ; | ||
| 332 | |||
| 333 | /* | ||
| 334 | Manages a completion queue | ||
| 335 | */ | ||
| 336 | struct be_cq_object { | ||
| 337 | u32 magic; | ||
| 338 | atomic_t ref_count; | ||
| 339 | |||
| 340 | struct be_function_object *parent_function; | ||
| 341 | struct be_eq_object *eq_object; | ||
| 342 | |||
| 343 | struct list_head cq_list; | ||
| 344 | struct list_head cqlist_for_eq; | ||
| 345 | |||
| 346 | void *va; | ||
| 347 | u32 num_entries; | ||
| 348 | |||
| 349 | void *cb_context; | ||
| 350 | |||
| 351 | u32 cq_id; | ||
| 352 | |||
| 353 | } ; | ||
| 354 | |||
| 355 | /* | ||
| 356 | Manages an ethernet send queue | ||
| 357 | */ | ||
| 358 | struct be_ethsq_object { | ||
| 359 | u32 magic; | ||
| 360 | |||
| 361 | struct list_head list; | ||
| 362 | |||
| 363 | struct be_function_object *parent_function; | ||
| 364 | struct be_cq_object *cq_object; | ||
| 365 | u32 bid; | ||
| 366 | |||
| 367 | } ; | ||
| 368 | |||
| 369 | /* | ||
| 370 | @brief | ||
| 371 | Manages an ethernet receive queue | ||
| 372 | */ | ||
| 373 | struct be_ethrq_object { | ||
| 374 | u32 magic; | ||
| 375 | struct list_head list; | ||
| 376 | struct be_function_object *parent_function; | ||
| 377 | u32 rid; | ||
| 378 | struct be_cq_object *cq_object; | ||
| 379 | struct be_cq_object *rss_cq_object[4]; | ||
| 380 | |||
| 381 | } ; | ||
| 382 | |||
| 383 | /* | ||
| 384 | Manages an MCC | ||
| 385 | */ | ||
| 386 | typedef void (*mcc_async_event_callback) (void *context, u32 event_code, | ||
| 387 | void *event); | ||
| 388 | struct be_mcc_object { | ||
| 389 | u32 magic; | ||
| 390 | |||
| 391 | struct be_function_object *parent_function; | ||
| 392 | struct list_head mcc_list; | ||
| 393 | |||
| 394 | struct be_cq_object *cq_object; | ||
| 395 | |||
| 396 | /* Async event callback for MCC CQ. */ | ||
| 397 | mcc_async_event_callback async_cb; | ||
| 398 | void *async_context; | ||
| 399 | |||
| 400 | struct { | ||
| 401 | struct be_mcc_wrb_context *base; | ||
| 402 | u32 num; | ||
| 403 | struct list_head list_head; | ||
| 404 | } wrb_context; | ||
| 405 | |||
| 406 | struct { | ||
| 407 | struct ring_desc *rd; | ||
| 408 | struct mp_ring ring; | ||
| 409 | } sq; | ||
| 410 | |||
| 411 | struct { | ||
| 412 | struct mp_ring ring; | ||
| 413 | } cq; | ||
| 414 | |||
| 415 | u32 processing; /* flag indicating that one thread | ||
| 416 | is processing CQ */ | ||
| 417 | u32 rearm; /* doorbell rearm setting to make | ||
| 418 | sure the active processing thread */ | ||
| 419 | /* rearms the CQ if any of the threads requested it. */ | ||
| 420 | |||
| 421 | struct list_head backlog; | ||
| 422 | u32 backlog_length; | ||
| 423 | u32 driving_backlog; | ||
| 424 | u32 consumed_index; | ||
| 425 | |||
| 426 | } ; | ||
| 427 | |||
| 428 | |||
| 429 | /* Queue context header -- the required software information for | ||
| 430 | * queueing a WRB. | ||
| 431 | */ | ||
| 432 | struct be_queue_driver_context { | ||
| 433 | mcc_wrb_cqe_callback internal_cb; /* Function to call on | ||
| 434 | completion */ | ||
| 435 | void *internal_cb_context; /* Parameter to pass | ||
| 436 | to completion function */ | ||
| 437 | |||
| 438 | mcc_wrb_cqe_callback cb; /* Function to call on completion */ | ||
| 439 | void *cb_context; /* Parameter to pass to completion function */ | ||
| 440 | |||
| 441 | struct be_mcc_wrb_response_copy copy; /* Optional parameters to copy | ||
| 442 | embedded response to user's va */ | ||
| 443 | void *optional_fwcmd_va; | ||
| 444 | struct list_head list; | ||
| 445 | u32 bytes; | ||
| 446 | } ; | ||
| 447 | |||
| 448 | /* | ||
| 449 | * Common MCC WRB header that all commands require. | ||
| 450 | */ | ||
| 451 | struct be_mcc_wrb_header { | ||
| 452 | u8 rsvd[offsetof(struct BE_MCC_WRB_AMAP, payload)/8]; | ||
| 453 | } ; | ||
| 454 | |||
| 455 | /* | ||
| 456 | * All non embedded commands supported by hwlib functions only allow | ||
| 457 | * 1 SGE. This queue context handles them all. | ||
| 458 | */ | ||
| 459 | struct be_nonembedded_q_ctxt { | ||
| 460 | struct be_queue_driver_context context; | ||
| 461 | struct be_mcc_wrb_header wrb_header; | ||
| 462 | struct MCC_SGE_AMAP sge[1]; | ||
| 463 | } ; | ||
| 464 | |||
| 465 | /* | ||
| 466 | * ------------------------------------------------------------------------ | ||
| 467 | * This section contains the specific queue struct for each command. | ||
| 468 | * The user could always provide a be_generic_q_ctxt but this is a | ||
| 469 | * rather large struct. By using the specific struct, memory consumption | ||
| 470 | * can be reduced. | ||
| 471 | * ------------------------------------------------------------------------ | ||
| 472 | */ | ||
| 473 | |||
| 474 | struct be_link_status_q_ctxt { | ||
| 475 | struct be_queue_driver_context context; | ||
| 476 | struct be_mcc_wrb_header wrb_header; | ||
| 477 | struct FWCMD_COMMON_NTWK_LINK_STATUS_QUERY fwcmd; | ||
| 478 | } ; | ||
| 479 | |||
| 480 | struct be_multicast_q_ctxt { | ||
| 481 | struct be_queue_driver_context context; | ||
| 482 | struct be_mcc_wrb_header wrb_header; | ||
| 483 | struct FWCMD_COMMON_NTWK_MULTICAST_SET fwcmd; | ||
| 484 | } ; | ||
| 485 | |||
| 486 | |||
| 487 | struct be_vlan_q_ctxt { | ||
| 488 | struct be_queue_driver_context context; | ||
| 489 | struct be_mcc_wrb_header wrb_header; | ||
| 490 | struct FWCMD_COMMON_NTWK_VLAN_CONFIG fwcmd; | ||
| 491 | } ; | ||
| 492 | |||
| 493 | struct be_promiscuous_q_ctxt { | ||
| 494 | struct be_queue_driver_context context; | ||
| 495 | struct be_mcc_wrb_header wrb_header; | ||
| 496 | struct FWCMD_ETH_PROMISCUOUS fwcmd; | ||
| 497 | } ; | ||
| 498 | |||
| 499 | struct be_force_failover_q_ctxt { | ||
| 500 | struct be_queue_driver_context context; | ||
| 501 | struct be_mcc_wrb_header wrb_header; | ||
| 502 | struct FWCMD_COMMON_FORCE_FAILOVER fwcmd; | ||
| 503 | } ; | ||
| 504 | |||
| 505 | |||
| 506 | struct be_rxf_filter_q_ctxt { | ||
| 507 | struct be_queue_driver_context context; | ||
| 508 | struct be_mcc_wrb_header wrb_header; | ||
| 509 | struct FWCMD_COMMON_NTWK_RX_FILTER fwcmd; | ||
| 510 | } ; | ||
| 511 | |||
| 512 | struct be_eq_modify_delay_q_ctxt { | ||
| 513 | struct be_queue_driver_context context; | ||
| 514 | struct be_mcc_wrb_header wrb_header; | ||
| 515 | struct FWCMD_COMMON_MODIFY_EQ_DELAY fwcmd; | ||
| 516 | } ; | ||
| 517 | |||
| 518 | /* | ||
| 519 | * The generic context is the largest size that would be required. | ||
| 520 | * It is the software context plus an entire WRB. | ||
| 521 | */ | ||
| 522 | struct be_generic_q_ctxt { | ||
| 523 | struct be_queue_driver_context context; | ||
| 524 | struct be_mcc_wrb_header wrb_header; | ||
| 525 | struct MCC_WRB_PAYLOAD_AMAP payload; | ||
| 526 | } ; | ||
| 527 | |||
| 528 | /* | ||
| 529 | * Types for the BE_QUEUE_CONTEXT object. | ||
| 530 | */ | ||
| 531 | #define BE_QUEUE_INVALID (0) | ||
| 532 | #define BE_QUEUE_LINK_STATUS (0xA006) | ||
| 533 | #define BE_QUEUE_ETH_STATS (0xA007) | ||
| 534 | #define BE_QUEUE_TPM_STATS (0xA008) | ||
| 535 | #define BE_QUEUE_TCP_STATS (0xA009) | ||
| 536 | #define BE_QUEUE_MULTICAST (0xA00A) | ||
| 537 | #define BE_QUEUE_VLAN (0xA00B) | ||
| 538 | #define BE_QUEUE_RSS (0xA00C) | ||
| 539 | #define BE_QUEUE_FORCE_FAILOVER (0xA00D) | ||
| 540 | #define BE_QUEUE_PROMISCUOUS (0xA00E) | ||
| 541 | #define BE_QUEUE_WAKE_ON_LAN (0xA00F) | ||
| 542 | #define BE_QUEUE_NOP (0xA010) | ||
| 543 | |||
| 544 | /* --- BE_FUNCTION_ENUM --- */ | ||
| 545 | #define BE_FUNCTION_TYPE_ISCSI (0) | ||
| 546 | #define BE_FUNCTION_TYPE_NETWORK (1) | ||
| 547 | #define BE_FUNCTION_TYPE_ARM (2) | ||
| 548 | |||
| 549 | /* --- BE_ETH_TX_RING_TYPE_ENUM --- */ | ||
| 550 | #define BE_ETH_TX_RING_TYPE_FORWARDING (1) /* Ether ring for forwarding */ | ||
| 551 | #define BE_ETH_TX_RING_TYPE_STANDARD (2) /* Ether ring for sending */ | ||
| 552 | /* network packets. */ | ||
| 553 | #define BE_ETH_TX_RING_TYPE_BOUND (3) /* Ethernet ring for sending */ | ||
| 554 | /* network packets, bound */ | ||
| 555 | /* to a physical port. */ | ||
| 556 | /* | ||
| 557 | * ---------------------------------------------------------------------- | ||
| 558 | * API MACROS | ||
| 559 | * ---------------------------------------------------------------------- | ||
| 560 | */ | ||
| 561 | #define BE_FWCMD_NAME(_short_name_) struct FWCMD_##_short_name_ | ||
| 562 | #define BE_OPCODE_NAME(_short_name_) OPCODE_##_short_name_ | ||
| 563 | #define BE_SUBSYSTEM_NAME(_short_name_) SUBSYSTEM_##_short_name_ | ||
| 564 | |||
| 565 | |||
| 566 | #define BE_PREPARE_EMBEDDED_FWCMD(_pfob_, _wrb_, _short_name_) \ | ||
| 567 | ((BE_FWCMD_NAME(_short_name_) *) \ | ||
| 568 | be_function_prepare_embedded_fwcmd(_pfob_, _wrb_, \ | ||
| 569 | sizeof(BE_FWCMD_NAME(_short_name_)), \ | ||
| 570 | FIELD_SIZEOF(BE_FWCMD_NAME(_short_name_), params.request), \ | ||
| 571 | FIELD_SIZEOF(BE_FWCMD_NAME(_short_name_), params.response), \ | ||
| 572 | BE_OPCODE_NAME(_short_name_), \ | ||
| 573 | BE_SUBSYSTEM_NAME(_short_name_))); | ||
| 574 | |||
| 575 | #define BE_PREPARE_NONEMBEDDED_FWCMD(_pfob_, _wrb_, _iva_, _ipa_, _short_name_)\ | ||
| 576 | ((BE_FWCMD_NAME(_short_name_) *) \ | ||
| 577 | be_function_prepare_nonembedded_fwcmd(_pfob_, _wrb_, (_iva_), (_ipa_), \ | ||
| 578 | sizeof(BE_FWCMD_NAME(_short_name_)), \ | ||
| 579 | FIELD_SIZEOF(BE_FWCMD_NAME(_short_name_), params.request), \ | ||
| 580 | FIELD_SIZEOF(BE_FWCMD_NAME(_short_name_), params.response), \ | ||
| 581 | BE_OPCODE_NAME(_short_name_), \ | ||
| 582 | BE_SUBSYSTEM_NAME(_short_name_))); | ||
| 583 | |||
| 584 | int be_function_object_create(u8 __iomem *csr_va, u8 __iomem *db_va, | ||
| 585 | u8 __iomem *pci_va, u32 function_type, struct ring_desc *mailbox_rd, | ||
| 586 | struct be_function_object *pfob); | ||
| 587 | |||
| 588 | int be_function_object_destroy(struct be_function_object *pfob); | ||
| 589 | int be_function_cleanup(struct be_function_object *pfob); | ||
| 590 | |||
| 591 | |||
| 592 | int be_function_get_fw_version(struct be_function_object *pfob, | ||
| 593 | struct FWCMD_COMMON_GET_FW_VERSION_RESPONSE_PAYLOAD *fw_version, | ||
| 594 | mcc_wrb_cqe_callback cb, void *cb_context); | ||
| 595 | |||
| 596 | |||
| 597 | int be_eq_modify_delay(struct be_function_object *pfob, | ||
| 598 | u32 num_eq, struct be_eq_object **eq_array, | ||
| 599 | u32 *eq_delay_array, mcc_wrb_cqe_callback cb, | ||
| 600 | void *cb_context, | ||
| 601 | struct be_eq_modify_delay_q_ctxt *q_ctxt); | ||
| 602 | |||
| 603 | |||
| 604 | |||
| 605 | int be_eq_create(struct be_function_object *pfob, | ||
| 606 | struct ring_desc *rd, u32 eqe_size, u32 num_entries, | ||
| 607 | u32 watermark, u32 timer_delay, struct be_eq_object *eq_object); | ||
| 608 | |||
| 609 | int be_eq_destroy(struct be_eq_object *eq); | ||
| 610 | |||
| 611 | int be_cq_create(struct be_function_object *pfob, | ||
| 612 | struct ring_desc *rd, u32 length, | ||
| 613 | bool solicited_eventable, bool no_delay, | ||
| 614 | u32 wm_thresh, struct be_eq_object *eq_object, | ||
| 615 | struct be_cq_object *cq_object); | ||
| 616 | |||
| 617 | int be_cq_destroy(struct be_cq_object *cq); | ||
| 618 | |||
| 619 | int be_mcc_ring_create(struct be_function_object *pfob, | ||
| 620 | struct ring_desc *rd, u32 length, | ||
| 621 | struct be_mcc_wrb_context *context_array, | ||
| 622 | u32 num_context_entries, | ||
| 623 | struct be_cq_object *cq, struct be_mcc_object *mcc); | ||
| 624 | int be_mcc_ring_destroy(struct be_mcc_object *mcc_object); | ||
| 625 | |||
| 626 | int be_mcc_process_cq(struct be_mcc_object *mcc_object, bool rearm); | ||
| 627 | |||
| 628 | int be_mcc_add_async_event_callback(struct be_mcc_object *mcc_object, | ||
| 629 | mcc_async_event_callback cb, void *cb_context); | ||
| 630 | |||
| 631 | int be_pci_soft_reset(struct be_function_object *pfob); | ||
| 632 | |||
| 633 | |||
| 634 | int be_drive_POST(struct be_function_object *pfob); | ||
| 635 | |||
| 636 | |||
| 637 | int be_eth_sq_create(struct be_function_object *pfob, | ||
| 638 | struct ring_desc *rd, u32 length_in_bytes, | ||
| 639 | u32 type, u32 ulp, struct be_cq_object *cq_object, | ||
| 640 | struct be_ethsq_object *eth_sq); | ||
| 641 | |||
| 642 | struct be_eth_sq_parameters { | ||
| 643 | u32 port; | ||
| 644 | u32 rsvd0[2]; | ||
| 645 | } ; | ||
| 646 | |||
| 647 | int be_eth_sq_create_ex(struct be_function_object *pfob, | ||
| 648 | struct ring_desc *rd, u32 length_in_bytes, | ||
| 649 | u32 type, u32 ulp, struct be_cq_object *cq_object, | ||
| 650 | struct be_eth_sq_parameters *ex_parameters, | ||
| 651 | struct be_ethsq_object *eth_sq); | ||
| 652 | int be_eth_sq_destroy(struct be_ethsq_object *eth_sq); | ||
| 653 | |||
| 654 | int be_eth_set_flow_control(struct be_function_object *pfob, | ||
| 655 | bool txfc_enable, bool rxfc_enable); | ||
| 656 | |||
| 657 | int be_eth_get_flow_control(struct be_function_object *pfob, | ||
| 658 | bool *txfc_enable, bool *rxfc_enable); | ||
| 659 | int be_eth_set_qos(struct be_function_object *pfob, u32 max_bps, u32 max_pps); | ||
| 660 | |||
| 661 | int be_eth_get_qos(struct be_function_object *pfob, u32 *max_bps, u32 *max_pps); | ||
| 662 | |||
| 663 | int be_eth_set_frame_size(struct be_function_object *pfob, | ||
| 664 | u32 *tx_frame_size, u32 *rx_frame_size); | ||
| 665 | |||
| 666 | int be_eth_rq_create(struct be_function_object *pfob, | ||
| 667 | struct ring_desc *rd, struct be_cq_object *cq_object, | ||
| 668 | struct be_cq_object *bcmc_cq_object, | ||
| 669 | struct be_ethrq_object *eth_rq); | ||
| 670 | |||
| 671 | int be_eth_rq_destroy(struct be_ethrq_object *eth_rq); | ||
| 672 | |||
| 673 | int be_eth_rq_destroy_options(struct be_ethrq_object *eth_rq, bool flush, | ||
| 674 | mcc_wrb_cqe_callback cb, void *cb_context); | ||
| 675 | int be_eth_rq_set_frag_size(struct be_function_object *pfob, | ||
| 676 | u32 new_frag_size_bytes, u32 *actual_frag_size_bytes); | ||
| 677 | int be_eth_rq_get_frag_size(struct be_function_object *pfob, | ||
| 678 | u32 *frag_size_bytes); | ||
| 679 | |||
| 680 | void *be_function_prepare_embedded_fwcmd(struct be_function_object *pfob, | ||
| 681 | struct MCC_WRB_AMAP *wrb, | ||
| 682 | u32 payload_length, u32 request_length, | ||
| 683 | u32 response_length, u32 opcode, u32 subsystem); | ||
| 684 | void *be_function_prepare_nonembedded_fwcmd(struct be_function_object *pfob, | ||
| 685 | struct MCC_WRB_AMAP *wrb, void *fwcmd_header_va, u64 fwcmd_header_pa, | ||
| 686 | u32 payload_length, u32 request_length, u32 response_length, | ||
| 687 | u32 opcode, u32 subsystem); | ||
| 688 | |||
| 689 | |||
| 690 | struct MCC_WRB_AMAP * | ||
| 691 | be_function_peek_mcc_wrb(struct be_function_object *pfob); | ||
| 692 | |||
| 693 | int be_rxf_mac_address_read_write(struct be_function_object *pfob, | ||
| 694 | bool port1, bool mac1, bool mgmt, | ||
| 695 | bool write, bool permanent, u8 *mac_address, | ||
| 696 | mcc_wrb_cqe_callback cb, | ||
| 697 | void *cb_context); | ||
| 698 | |||
| 699 | int be_rxf_multicast_config(struct be_function_object *pfob, | ||
| 700 | bool promiscuous, u32 num, u8 *mac_table, | ||
| 701 | mcc_wrb_cqe_callback cb, | ||
| 702 | void *cb_context, | ||
| 703 | struct be_multicast_q_ctxt *q_ctxt); | ||
| 704 | |||
| 705 | int be_rxf_vlan_config(struct be_function_object *pfob, | ||
| 706 | bool promiscuous, u32 num, u16 *vlan_tag_array, | ||
| 707 | mcc_wrb_cqe_callback cb, void *cb_context, | ||
| 708 | struct be_vlan_q_ctxt *q_ctxt); | ||
| 709 | |||
| 710 | |||
| 711 | int be_rxf_link_status(struct be_function_object *pfob, | ||
| 712 | struct BE_LINK_STATUS *link_status, | ||
| 713 | mcc_wrb_cqe_callback cb, | ||
| 714 | void *cb_context, | ||
| 715 | struct be_link_status_q_ctxt *q_ctxt); | ||
| 716 | |||
| 717 | |||
| 718 | int be_rxf_query_eth_statistics(struct be_function_object *pfob, | ||
| 719 | struct FWCMD_ETH_GET_STATISTICS *va_for_fwcmd, | ||
| 720 | u64 pa_for_fwcmd, mcc_wrb_cqe_callback cb, | ||
| 721 | void *cb_context, | ||
| 722 | struct be_nonembedded_q_ctxt *q_ctxt); | ||
| 723 | |||
| 724 | int be_rxf_promiscuous(struct be_function_object *pfob, | ||
| 725 | bool enable_port0, bool enable_port1, | ||
| 726 | mcc_wrb_cqe_callback cb, void *cb_context, | ||
| 727 | struct be_promiscuous_q_ctxt *q_ctxt); | ||
| 728 | |||
| 729 | |||
| 730 | int be_rxf_filter_config(struct be_function_object *pfob, | ||
| 731 | struct NTWK_RX_FILTER_SETTINGS *settings, | ||
| 732 | mcc_wrb_cqe_callback cb, | ||
| 733 | void *cb_context, | ||
| 734 | struct be_rxf_filter_q_ctxt *q_ctxt); | ||
| 735 | |||
| 736 | /* | ||
| 737 | * ------------------------------------------------------ | ||
| 738 | * internal functions used by hwlib | ||
| 739 | * ------------------------------------------------------ | ||
| 740 | */ | ||
| 741 | |||
| 742 | |||
| 743 | int be_function_ring_destroy(struct be_function_object *pfob, | ||
| 744 | u32 id, u32 ring_type, mcc_wrb_cqe_callback cb, | ||
| 745 | void *cb_context, | ||
| 746 | mcc_wrb_cqe_callback internal_cb, | ||
| 747 | void *internal_callback_context); | ||
| 748 | |||
| 749 | int be_function_post_mcc_wrb(struct be_function_object *pfob, | ||
| 750 | struct MCC_WRB_AMAP *wrb, | ||
| 751 | struct be_generic_q_ctxt *q_ctxt, | ||
| 752 | mcc_wrb_cqe_callback cb, void *cb_context, | ||
| 753 | mcc_wrb_cqe_callback internal_cb, | ||
| 754 | void *internal_cb_context, void *optional_fwcmd_va, | ||
| 755 | struct be_mcc_wrb_response_copy *response_copy); | ||
| 756 | |||
| 757 | int be_function_queue_mcc_wrb(struct be_function_object *pfob, | ||
| 758 | struct be_generic_q_ctxt *q_ctxt); | ||
| 759 | |||
| 760 | /* | ||
| 761 | * ------------------------------------------------------ | ||
| 762 | * MCC QUEUE | ||
| 763 | * ------------------------------------------------------ | ||
| 764 | */ | ||
| 765 | |||
| 766 | int be_mpu_init_mailbox(struct be_function_object *pfob, struct ring_desc *rd); | ||
| 767 | |||
| 768 | |||
| 769 | struct MCC_WRB_AMAP * | ||
| 770 | _be_mpu_peek_ring_wrb(struct be_mcc_object *mcc, bool driving_queue); | ||
| 771 | |||
| 772 | struct be_mcc_wrb_context * | ||
| 773 | _be_mcc_allocate_wrb_context(struct be_function_object *pfob); | ||
| 774 | |||
| 775 | void _be_mcc_free_wrb_context(struct be_function_object *pfob, | ||
| 776 | struct be_mcc_wrb_context *context); | ||
| 777 | |||
| 778 | int _be_mpu_post_wrb_mailbox(struct be_function_object *pfob, | ||
| 779 | struct MCC_WRB_AMAP *wrb, struct be_mcc_wrb_context *wrb_context); | ||
| 780 | |||
| 781 | int _be_mpu_post_wrb_ring(struct be_mcc_object *mcc, | ||
| 782 | struct MCC_WRB_AMAP *wrb, struct be_mcc_wrb_context *wrb_context); | ||
| 783 | |||
| 784 | void be_drive_mcc_wrb_queue(struct be_mcc_object *mcc); | ||
| 785 | |||
| 786 | |||
| 787 | /* | ||
| 788 | * ------------------------------------------------------ | ||
| 789 | * Ring Sizes | ||
| 790 | * ------------------------------------------------------ | ||
| 791 | */ | ||
| 792 | static inline u32 be_ring_encoding_to_length(u32 encoding, u32 object_size) | ||
| 793 | { | ||
| 794 | |||
| 795 | ASSERT(encoding != 1); /* 1 is rsvd */ | ||
| 796 | ASSERT(encoding < 16); | ||
| 797 | ASSERT(object_size > 0); | ||
| 798 | |||
| 799 | if (encoding == 0) /* 32k deep */ | ||
| 800 | encoding = 16; | ||
| 801 | |||
| 802 | return (1 << (encoding - 1)) * object_size; | ||
| 803 | } | ||
| 804 | |||
| 805 | static inline | ||
| 806 | u32 be_ring_length_to_encoding(u32 length_in_bytes, u32 object_size) | ||
| 807 | { | ||
| 808 | |||
| 809 | u32 count, encoding; | ||
| 810 | |||
| 811 | ASSERT(object_size > 0); | ||
| 812 | ASSERT(length_in_bytes % object_size == 0); | ||
| 813 | |||
| 814 | count = length_in_bytes / object_size; | ||
| 815 | |||
| 816 | ASSERT(count > 1); | ||
| 817 | ASSERT(count <= 32 * 1024); | ||
| 818 | ASSERT(length_in_bytes <= 8 * PAGE_SIZE); /* max ring size in UT */ | ||
| 819 | |||
| 820 | encoding = __ilog2_u32(count) + 1; | ||
| 821 | |||
| 822 | if (encoding == 16) | ||
| 823 | encoding = 0; /* 32k deep */ | ||
| 824 | |||
| 825 | return encoding; | ||
| 826 | } | ||
| 827 | |||
| 828 | void be_rd_to_pa_list(struct ring_desc *rd, struct PHYS_ADDR *pa_list, | ||
| 829 | u32 max_num); | ||
| 830 | #endif /* __hwlib_h__ */ | ||
diff --git a/drivers/staging/benet/mpu.c b/drivers/staging/benet/mpu.c deleted file mode 100644 index 269cc11d3055..000000000000 --- a/drivers/staging/benet/mpu.c +++ /dev/null | |||
| @@ -1,1364 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | #include <linux/delay.h> | ||
| 18 | #include "hwlib.h" | ||
| 19 | #include "bestatus.h" | ||
| 20 | |||
| 21 | static | ||
| 22 | inline void mp_ring_create(struct mp_ring *ring, u32 num, u32 size, void *va) | ||
| 23 | { | ||
| 24 | ASSERT(ring); | ||
| 25 | memset(ring, 0, sizeof(struct mp_ring)); | ||
| 26 | ring->num = num; | ||
| 27 | ring->pages = DIV_ROUND_UP(num * size, PAGE_SIZE); | ||
| 28 | ring->itemSize = size; | ||
| 29 | ring->va = va; | ||
| 30 | } | ||
| 31 | |||
| 32 | /* | ||
| 33 | * ----------------------------------------------------------------------- | ||
| 34 | * Interface for 2 index rings. i.e. consumer/producer rings | ||
| 35 | * -------------------------------------------------------------------------- | ||
| 36 | */ | ||
| 37 | |||
| 38 | /* Returns number items pending on ring. */ | ||
| 39 | static inline u32 mp_ring_num_pending(struct mp_ring *ring) | ||
| 40 | { | ||
| 41 | ASSERT(ring); | ||
| 42 | if (ring->num == 0) | ||
| 43 | return 0; | ||
| 44 | return be_subc(ring->pidx, ring->cidx, ring->num); | ||
| 45 | } | ||
| 46 | |||
| 47 | /* Returns number items free on ring. */ | ||
| 48 | static inline u32 mp_ring_num_empty(struct mp_ring *ring) | ||
| 49 | { | ||
| 50 | ASSERT(ring); | ||
| 51 | return ring->num - 1 - mp_ring_num_pending(ring); | ||
| 52 | } | ||
| 53 | |||
| 54 | /* Consume 1 item */ | ||
| 55 | static inline void mp_ring_consume(struct mp_ring *ring) | ||
| 56 | { | ||
| 57 | ASSERT(ring); | ||
| 58 | ASSERT(ring->pidx != ring->cidx); | ||
| 59 | |||
| 60 | ring->cidx = be_addc(ring->cidx, 1, ring->num); | ||
| 61 | } | ||
| 62 | |||
| 63 | /* Produce 1 item */ | ||
| 64 | static inline void mp_ring_produce(struct mp_ring *ring) | ||
| 65 | { | ||
| 66 | ASSERT(ring); | ||
| 67 | ring->pidx = be_addc(ring->pidx, 1, ring->num); | ||
| 68 | } | ||
| 69 | |||
| 70 | /* Consume count items */ | ||
| 71 | static inline void mp_ring_consume_multiple(struct mp_ring *ring, u32 count) | ||
| 72 | { | ||
| 73 | ASSERT(ring); | ||
| 74 | ASSERT(mp_ring_num_pending(ring) >= count); | ||
| 75 | ring->cidx = be_addc(ring->cidx, count, ring->num); | ||
| 76 | } | ||
| 77 | |||
| 78 | static inline void *mp_ring_item(struct mp_ring *ring, u32 index) | ||
| 79 | { | ||
| 80 | ASSERT(ring); | ||
| 81 | ASSERT(index < ring->num); | ||
| 82 | ASSERT(ring->itemSize > 0); | ||
| 83 | return (u8 *) ring->va + index * ring->itemSize; | ||
| 84 | } | ||
| 85 | |||
| 86 | /* Ptr to produce item */ | ||
| 87 | static inline void *mp_ring_producer_ptr(struct mp_ring *ring) | ||
| 88 | { | ||
| 89 | ASSERT(ring); | ||
| 90 | return mp_ring_item(ring, ring->pidx); | ||
| 91 | } | ||
| 92 | |||
| 93 | /* | ||
| 94 | * Returns a pointer to the current location in the ring. | ||
| 95 | * This is used for rings with 1 index. | ||
| 96 | */ | ||
| 97 | static inline void *mp_ring_current(struct mp_ring *ring) | ||
| 98 | { | ||
| 99 | ASSERT(ring); | ||
| 100 | ASSERT(ring->pidx == 0); /* not used */ | ||
| 101 | |||
| 102 | return mp_ring_item(ring, ring->cidx); | ||
| 103 | } | ||
| 104 | |||
| 105 | /* | ||
| 106 | * Increment index for rings with only 1 index. | ||
| 107 | * This is used for rings with 1 index. | ||
| 108 | */ | ||
| 109 | static inline void *mp_ring_next(struct mp_ring *ring) | ||
| 110 | { | ||
| 111 | ASSERT(ring); | ||
| 112 | ASSERT(ring->num > 0); | ||
| 113 | ASSERT(ring->pidx == 0); /* not used */ | ||
| 114 | |||
| 115 | ring->cidx = be_addc(ring->cidx, 1, ring->num); | ||
| 116 | return mp_ring_current(ring); | ||
| 117 | } | ||
| 118 | |||
| 119 | /* | ||
| 120 | This routine waits for a previously posted mailbox WRB to be completed. | ||
| 121 | Specifically it waits for the mailbox to say that it's ready to accept | ||
| 122 | more data by setting the LSB of the mailbox pd register to 1. | ||
| 123 | |||
| 124 | pcontroller - The function object to post this data to | ||
| 125 | |||
| 126 | IRQL < DISPATCH_LEVEL | ||
| 127 | */ | ||
| 128 | static void be_mcc_mailbox_wait(struct be_function_object *pfob) | ||
| 129 | { | ||
| 130 | struct MPU_MAILBOX_DB_AMAP mailbox_db; | ||
| 131 | u32 i = 0; | ||
| 132 | u32 ready; | ||
| 133 | |||
| 134 | if (pfob->emulate) { | ||
| 135 | /* No waiting for mailbox in emulated mode. */ | ||
| 136 | return; | ||
| 137 | } | ||
| 138 | |||
| 139 | mailbox_db.dw[0] = PD_READ(pfob, mcc_bootstrap_db); | ||
| 140 | ready = AMAP_GET_BITS_PTR(MPU_MAILBOX_DB, ready, &mailbox_db); | ||
| 141 | |||
| 142 | while (ready == false) { | ||
| 143 | if ((++i & 0x3FFFF) == 0) { | ||
| 144 | TRACE(DL_WARN, "Waiting for mailbox ready - %dk polls", | ||
| 145 | i / 1000); | ||
| 146 | } | ||
| 147 | udelay(1); | ||
| 148 | mailbox_db.dw[0] = PD_READ(pfob, mcc_bootstrap_db); | ||
| 149 | ready = AMAP_GET_BITS_PTR(MPU_MAILBOX_DB, ready, &mailbox_db); | ||
| 150 | } | ||
| 151 | } | ||
| 152 | |||
| 153 | /* | ||
| 154 | This routine tells the MCC mailbox that there is data to processed | ||
| 155 | in the mailbox. It does this by setting the physical address for the | ||
| 156 | mailbox location and clearing the LSB. This routine returns immediately | ||
| 157 | and does not wait for the WRB to be processed. | ||
| 158 | |||
| 159 | pcontroller - The function object to post this data to | ||
| 160 | |||
| 161 | IRQL < DISPATCH_LEVEL | ||
| 162 | |||
| 163 | */ | ||
| 164 | static void be_mcc_mailbox_notify(struct be_function_object *pfob) | ||
| 165 | { | ||
| 166 | struct MPU_MAILBOX_DB_AMAP mailbox_db; | ||
| 167 | u32 pa; | ||
| 168 | |||
| 169 | ASSERT(pfob->mailbox.pa); | ||
| 170 | ASSERT(pfob->mailbox.va); | ||
| 171 | |||
| 172 | /* If emulated, do not ring the mailbox */ | ||
| 173 | if (pfob->emulate) { | ||
| 174 | TRACE(DL_WARN, "MPU disabled. Skipping mailbox notify."); | ||
| 175 | return; | ||
| 176 | } | ||
| 177 | |||
| 178 | /* form the higher bits in the address */ | ||
| 179 | mailbox_db.dw[0] = 0; /* init */ | ||
| 180 | AMAP_SET_BITS_PTR(MPU_MAILBOX_DB, hi, &mailbox_db, 1); | ||
| 181 | AMAP_SET_BITS_PTR(MPU_MAILBOX_DB, ready, &mailbox_db, 0); | ||
| 182 | |||
| 183 | /* bits 34 to 63 */ | ||
| 184 | pa = (u32) (pfob->mailbox.pa >> 34); | ||
| 185 | AMAP_SET_BITS_PTR(MPU_MAILBOX_DB, address, &mailbox_db, pa); | ||
| 186 | |||
| 187 | /* Wait for the MPU to be ready */ | ||
| 188 | be_mcc_mailbox_wait(pfob); | ||
| 189 | |||
| 190 | /* Ring doorbell 1st time */ | ||
| 191 | PD_WRITE(pfob, mcc_bootstrap_db, mailbox_db.dw[0]); | ||
| 192 | |||
| 193 | /* Wait for 1st write to be acknowledged. */ | ||
| 194 | be_mcc_mailbox_wait(pfob); | ||
| 195 | |||
| 196 | /* lower bits 30 bits from 4th bit (bits 4 to 33)*/ | ||
| 197 | pa = (u32) (pfob->mailbox.pa >> 4) & 0x3FFFFFFF; | ||
| 198 | |||
| 199 | AMAP_SET_BITS_PTR(MPU_MAILBOX_DB, hi, &mailbox_db, 0); | ||
| 200 | AMAP_SET_BITS_PTR(MPU_MAILBOX_DB, ready, &mailbox_db, 0); | ||
| 201 | AMAP_SET_BITS_PTR(MPU_MAILBOX_DB, address, &mailbox_db, pa); | ||
| 202 | |||
| 203 | /* Ring doorbell 2nd time */ | ||
| 204 | PD_WRITE(pfob, mcc_bootstrap_db, mailbox_db.dw[0]); | ||
| 205 | } | ||
| 206 | |||
| 207 | /* | ||
| 208 | This routine tells the MCC mailbox that there is data to processed | ||
| 209 | in the mailbox. It does this by setting the physical address for the | ||
| 210 | mailbox location and clearing the LSB. This routine spins until the | ||
| 211 | MPU writes a 1 into the LSB indicating that the data has been received | ||
| 212 | and is ready to be processed. | ||
| 213 | |||
| 214 | pcontroller - The function object to post this data to | ||
| 215 | |||
| 216 | IRQL < DISPATCH_LEVEL | ||
| 217 | */ | ||
| 218 | static void | ||
| 219 | be_mcc_mailbox_notify_and_wait(struct be_function_object *pfob) | ||
| 220 | { | ||
| 221 | /* | ||
| 222 | * Notify it | ||
| 223 | */ | ||
| 224 | be_mcc_mailbox_notify(pfob); | ||
| 225 | /* | ||
| 226 | * Now wait for completion of WRB | ||
| 227 | */ | ||
| 228 | be_mcc_mailbox_wait(pfob); | ||
| 229 | } | ||
| 230 | |||
| 231 | void | ||
| 232 | be_mcc_process_cqe(struct be_function_object *pfob, | ||
| 233 | struct MCC_CQ_ENTRY_AMAP *cqe) | ||
| 234 | { | ||
| 235 | struct be_mcc_wrb_context *wrb_context = NULL; | ||
| 236 | u32 offset, status; | ||
| 237 | u8 *p; | ||
| 238 | |||
| 239 | ASSERT(cqe); | ||
| 240 | /* | ||
| 241 | * A command completed. Commands complete out-of-order. | ||
| 242 | * Determine which command completed from the TAG. | ||
| 243 | */ | ||
| 244 | offset = offsetof(struct BE_MCC_CQ_ENTRY_AMAP, mcc_tag)/8; | ||
| 245 | p = (u8 *) cqe + offset; | ||
| 246 | wrb_context = (struct be_mcc_wrb_context *)(void *)(size_t)(*(u64 *)p); | ||
| 247 | ASSERT(wrb_context); | ||
| 248 | |||
| 249 | /* | ||
| 250 | * Perform a response copy if requested. | ||
| 251 | * Only copy data if the FWCMD is successful. | ||
| 252 | */ | ||
| 253 | status = AMAP_GET_BITS_PTR(MCC_CQ_ENTRY, completion_status, cqe); | ||
| 254 | if (status == MGMT_STATUS_SUCCESS && wrb_context->copy.length > 0) { | ||
| 255 | ASSERT(wrb_context->wrb); | ||
| 256 | ASSERT(wrb_context->copy.va); | ||
| 257 | p = (u8 *)wrb_context->wrb + | ||
| 258 | offsetof(struct BE_MCC_WRB_AMAP, payload)/8; | ||
| 259 | memcpy(wrb_context->copy.va, | ||
| 260 | (u8 *)p + wrb_context->copy.fwcmd_offset, | ||
| 261 | wrb_context->copy.length); | ||
| 262 | } | ||
| 263 | |||
| 264 | if (status) | ||
| 265 | status = BE_NOT_OK; | ||
| 266 | /* internal callback */ | ||
| 267 | if (wrb_context->internal_cb) { | ||
| 268 | wrb_context->internal_cb(wrb_context->internal_cb_context, | ||
| 269 | status, wrb_context->wrb); | ||
| 270 | } | ||
| 271 | |||
| 272 | /* callback */ | ||
| 273 | if (wrb_context->cb) { | ||
| 274 | wrb_context->cb(wrb_context->cb_context, | ||
| 275 | status, wrb_context->wrb); | ||
| 276 | } | ||
| 277 | /* Free the context structure */ | ||
| 278 | _be_mcc_free_wrb_context(pfob, wrb_context); | ||
| 279 | } | ||
| 280 | |||
| 281 | void be_drive_mcc_wrb_queue(struct be_mcc_object *mcc) | ||
| 282 | { | ||
| 283 | struct be_function_object *pfob = NULL; | ||
| 284 | int status = BE_PENDING; | ||
| 285 | struct be_generic_q_ctxt *q_ctxt; | ||
| 286 | struct MCC_WRB_AMAP *wrb; | ||
| 287 | struct MCC_WRB_AMAP *queue_wrb; | ||
| 288 | u32 length, payload_length, sge_count, embedded; | ||
| 289 | unsigned long irql; | ||
| 290 | |||
| 291 | BUILD_BUG_ON((sizeof(struct be_generic_q_ctxt) < | ||
| 292 | sizeof(struct be_queue_driver_context) + | ||
| 293 | sizeof(struct MCC_WRB_AMAP))); | ||
| 294 | pfob = mcc->parent_function; | ||
| 295 | |||
| 296 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 297 | |||
| 298 | if (mcc->driving_backlog) { | ||
| 299 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 300 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 301 | pfob->pend_queue_driving = 0; | ||
| 302 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 303 | } | ||
| 304 | return; | ||
| 305 | } | ||
| 306 | /* Acquire the flag to limit 1 thread to redrive posts. */ | ||
| 307 | mcc->driving_backlog = 1; | ||
| 308 | |||
| 309 | while (!list_empty(&mcc->backlog)) { | ||
| 310 | wrb = _be_mpu_peek_ring_wrb(mcc, true); /* Driving the queue */ | ||
| 311 | if (!wrb) | ||
| 312 | break; /* No space in the ring yet. */ | ||
| 313 | /* Get the next queued entry to process. */ | ||
| 314 | q_ctxt = list_first_entry(&mcc->backlog, | ||
| 315 | struct be_generic_q_ctxt, context.list); | ||
| 316 | list_del(&q_ctxt->context.list); | ||
| 317 | pfob->mcc->backlog_length--; | ||
| 318 | /* | ||
| 319 | * Compute the required length of the WRB. | ||
| 320 | * Since the queue element may be smaller than | ||
| 321 | * the complete WRB, copy only the required number of bytes. | ||
| 322 | */ | ||
| 323 | queue_wrb = (struct MCC_WRB_AMAP *) &q_ctxt->wrb_header; | ||
| 324 | embedded = AMAP_GET_BITS_PTR(MCC_WRB, embedded, queue_wrb); | ||
| 325 | if (embedded) { | ||
| 326 | payload_length = AMAP_GET_BITS_PTR(MCC_WRB, | ||
| 327 | payload_length, queue_wrb); | ||
| 328 | length = sizeof(struct be_mcc_wrb_header) + | ||
| 329 | payload_length; | ||
| 330 | } else { | ||
| 331 | sge_count = AMAP_GET_BITS_PTR(MCC_WRB, sge_count, | ||
| 332 | queue_wrb); | ||
| 333 | ASSERT(sge_count == 1); /* only 1 frag. */ | ||
| 334 | length = sizeof(struct be_mcc_wrb_header) + | ||
| 335 | sge_count * sizeof(struct MCC_SGE_AMAP); | ||
| 336 | } | ||
| 337 | |||
| 338 | /* | ||
| 339 | * Truncate the length based on the size of the | ||
| 340 | * queue element. Some elements that have output parameters | ||
| 341 | * can be smaller than the payload_length field would | ||
| 342 | * indicate. We really only need to copy the request | ||
| 343 | * parameters, not the response. | ||
| 344 | */ | ||
| 345 | length = min(length, (u32) (q_ctxt->context.bytes - | ||
| 346 | offsetof(struct be_generic_q_ctxt, wrb_header))); | ||
| 347 | |||
| 348 | /* Copy the queue element WRB into the ring. */ | ||
| 349 | memcpy(wrb, &q_ctxt->wrb_header, length); | ||
| 350 | |||
| 351 | /* Post the wrb. This should not fail assuming we have | ||
| 352 | * enough context structs. */ | ||
| 353 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, | ||
| 354 | q_ctxt->context.cb, q_ctxt->context.cb_context, | ||
| 355 | q_ctxt->context.internal_cb, | ||
| 356 | q_ctxt->context.internal_cb_context, | ||
| 357 | q_ctxt->context.optional_fwcmd_va, | ||
| 358 | &q_ctxt->context.copy); | ||
| 359 | |||
| 360 | if (status == BE_SUCCESS) { | ||
| 361 | /* | ||
| 362 | * Synchronous completion. Since it was queued, | ||
| 363 | * we will invoke the callback. | ||
| 364 | * To the user, this is an asynchronous request. | ||
| 365 | */ | ||
| 366 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 367 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 368 | pfob->pend_queue_driving = 0; | ||
| 369 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 370 | } | ||
| 371 | |||
| 372 | ASSERT(q_ctxt->context.cb); | ||
| 373 | |||
| 374 | q_ctxt->context.cb( | ||
| 375 | q_ctxt->context.cb_context, | ||
| 376 | BE_SUCCESS, NULL); | ||
| 377 | |||
| 378 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 379 | |||
| 380 | } else if (status != BE_PENDING) { | ||
| 381 | /* | ||
| 382 | * Another resource failed. Should never happen | ||
| 383 | * if we have sufficient MCC_WRB_CONTEXT structs. | ||
| 384 | * Return to head of the queue. | ||
| 385 | */ | ||
| 386 | TRACE(DL_WARN, "Failed to post a queued WRB. 0x%x", | ||
| 387 | status); | ||
| 388 | list_add(&q_ctxt->context.list, &mcc->backlog); | ||
| 389 | pfob->mcc->backlog_length++; | ||
| 390 | break; | ||
| 391 | } | ||
| 392 | } | ||
| 393 | |||
| 394 | /* Free the flag to limit 1 thread to redrive posts. */ | ||
| 395 | mcc->driving_backlog = 0; | ||
| 396 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 397 | } | ||
| 398 | |||
| 399 | /* This function asserts that the WRB was consumed in order. */ | ||
| 400 | #ifdef BE_DEBUG | ||
| 401 | u32 be_mcc_wrb_consumed_in_order(struct be_mcc_object *mcc, | ||
| 402 | struct MCC_CQ_ENTRY_AMAP *cqe) | ||
| 403 | { | ||
| 404 | struct be_mcc_wrb_context *wrb_context = NULL; | ||
| 405 | u32 wrb_index; | ||
| 406 | u32 wrb_consumed_in_order; | ||
| 407 | u32 offset; | ||
| 408 | u8 *p; | ||
| 409 | |||
| 410 | ASSERT(cqe); | ||
| 411 | /* | ||
| 412 | * A command completed. Commands complete out-of-order. | ||
| 413 | * Determine which command completed from the TAG. | ||
| 414 | */ | ||
| 415 | offset = offsetof(struct BE_MCC_CQ_ENTRY_AMAP, mcc_tag)/8; | ||
| 416 | p = (u8 *) cqe + offset; | ||
| 417 | wrb_context = (struct be_mcc_wrb_context *)(void *)(size_t)(*(u64 *)p); | ||
| 418 | |||
| 419 | ASSERT(wrb_context); | ||
| 420 | |||
| 421 | wrb_index = (u32) (((u64)(size_t)wrb_context->ring_wrb - | ||
| 422 | (u64)(size_t)mcc->sq.ring.va) / sizeof(struct MCC_WRB_AMAP)); | ||
| 423 | |||
| 424 | ASSERT(wrb_index < mcc->sq.ring.num); | ||
| 425 | |||
| 426 | wrb_consumed_in_order = (u32) (wrb_index == mcc->consumed_index); | ||
| 427 | mcc->consumed_index = be_addc(mcc->consumed_index, 1, mcc->sq.ring.num); | ||
| 428 | return wrb_consumed_in_order; | ||
| 429 | } | ||
| 430 | #endif | ||
| 431 | |||
| 432 | int be_mcc_process_cq(struct be_mcc_object *mcc, bool rearm) | ||
| 433 | { | ||
| 434 | struct be_function_object *pfob = NULL; | ||
| 435 | struct MCC_CQ_ENTRY_AMAP *cqe; | ||
| 436 | struct CQ_DB_AMAP db; | ||
| 437 | struct mp_ring *cq_ring = &mcc->cq.ring; | ||
| 438 | struct mp_ring *mp_ring = &mcc->sq.ring; | ||
| 439 | u32 num_processed = 0; | ||
| 440 | u32 consumed = 0, valid, completed, cqe_consumed, async_event; | ||
| 441 | |||
| 442 | pfob = mcc->parent_function; | ||
| 443 | |||
| 444 | spin_lock_irqsave(&pfob->cq_lock, pfob->cq_irq); | ||
| 445 | |||
| 446 | /* | ||
| 447 | * Verify that only one thread is processing the CQ at once. | ||
| 448 | * We cannot hold the lock while processing the CQ due to | ||
| 449 | * the callbacks into the OS. Therefore, this flag is used | ||
| 450 | * to control it. If any of the threads want to | ||
| 451 | * rearm the CQ, we need to honor that. | ||
| 452 | */ | ||
| 453 | if (mcc->processing != 0) { | ||
| 454 | mcc->rearm = mcc->rearm || rearm; | ||
| 455 | goto Error; | ||
| 456 | } else { | ||
| 457 | mcc->processing = 1; /* lock processing for this thread. */ | ||
| 458 | mcc->rearm = rearm; /* set our rearm setting */ | ||
| 459 | } | ||
| 460 | |||
| 461 | spin_unlock_irqrestore(&pfob->cq_lock, pfob->cq_irq); | ||
| 462 | |||
| 463 | cqe = mp_ring_current(cq_ring); | ||
| 464 | valid = AMAP_GET_BITS_PTR(MCC_CQ_ENTRY, valid, cqe); | ||
| 465 | while (valid) { | ||
| 466 | |||
| 467 | if (num_processed >= 8) { | ||
| 468 | /* coalesce doorbells, but free space in cq | ||
| 469 | * ring while processing. */ | ||
| 470 | db.dw[0] = 0; /* clear */ | ||
| 471 | AMAP_SET_BITS_PTR(CQ_DB, qid, &db, cq_ring->id); | ||
| 472 | AMAP_SET_BITS_PTR(CQ_DB, rearm, &db, false); | ||
| 473 | AMAP_SET_BITS_PTR(CQ_DB, event, &db, false); | ||
| 474 | AMAP_SET_BITS_PTR(CQ_DB, num_popped, &db, | ||
| 475 | num_processed); | ||
| 476 | num_processed = 0; | ||
| 477 | |||
| 478 | PD_WRITE(pfob, cq_db, db.dw[0]); | ||
| 479 | } | ||
| 480 | |||
| 481 | async_event = AMAP_GET_BITS_PTR(MCC_CQ_ENTRY, async_event, cqe); | ||
| 482 | if (async_event) { | ||
| 483 | /* This is an asynchronous event. */ | ||
| 484 | struct ASYNC_EVENT_TRAILER_AMAP *async_trailer = | ||
| 485 | (struct ASYNC_EVENT_TRAILER_AMAP *) | ||
| 486 | ((u8 *) cqe + sizeof(struct MCC_CQ_ENTRY_AMAP) - | ||
| 487 | sizeof(struct ASYNC_EVENT_TRAILER_AMAP)); | ||
| 488 | u32 event_code; | ||
| 489 | async_event = AMAP_GET_BITS_PTR(ASYNC_EVENT_TRAILER, | ||
| 490 | async_event, async_trailer); | ||
| 491 | ASSERT(async_event == 1); | ||
| 492 | |||
| 493 | |||
| 494 | valid = AMAP_GET_BITS_PTR(ASYNC_EVENT_TRAILER, | ||
| 495 | valid, async_trailer); | ||
| 496 | ASSERT(valid == 1); | ||
| 497 | |||
| 498 | /* Call the async event handler if it is installed. */ | ||
| 499 | if (mcc->async_cb) { | ||
| 500 | event_code = | ||
| 501 | AMAP_GET_BITS_PTR(ASYNC_EVENT_TRAILER, | ||
| 502 | event_code, async_trailer); | ||
| 503 | mcc->async_cb(mcc->async_context, | ||
| 504 | (u32) event_code, (void *) cqe); | ||
| 505 | } | ||
| 506 | |||
| 507 | } else { | ||
| 508 | /* This is a completion entry. */ | ||
| 509 | |||
| 510 | /* No vm forwarding in this driver. */ | ||
| 511 | |||
| 512 | cqe_consumed = AMAP_GET_BITS_PTR(MCC_CQ_ENTRY, | ||
| 513 | consumed, cqe); | ||
| 514 | if (cqe_consumed) { | ||
| 515 | /* | ||
| 516 | * A command on the MCC ring was consumed. | ||
| 517 | * Update the consumer index. | ||
| 518 | * These occur in order. | ||
| 519 | */ | ||
| 520 | ASSERT(be_mcc_wrb_consumed_in_order(mcc, cqe)); | ||
| 521 | consumed++; | ||
| 522 | } | ||
| 523 | |||
| 524 | completed = AMAP_GET_BITS_PTR(MCC_CQ_ENTRY, | ||
| 525 | completed, cqe); | ||
| 526 | if (completed) { | ||
| 527 | /* A command completed. Use tag to | ||
| 528 | * determine which command. */ | ||
| 529 | be_mcc_process_cqe(pfob, cqe); | ||
| 530 | } | ||
| 531 | } | ||
| 532 | |||
| 533 | /* Reset the CQE */ | ||
| 534 | AMAP_SET_BITS_PTR(MCC_CQ_ENTRY, valid, cqe, false); | ||
| 535 | num_processed++; | ||
| 536 | |||
| 537 | /* Update our tracking for the CQ ring. */ | ||
| 538 | cqe = mp_ring_next(cq_ring); | ||
| 539 | valid = AMAP_GET_BITS_PTR(MCC_CQ_ENTRY, valid, cqe); | ||
| 540 | } | ||
| 541 | |||
| 542 | TRACE(DL_INFO, "num_processed:0x%x, and consumed:0x%x", | ||
| 543 | num_processed, consumed); | ||
| 544 | /* | ||
| 545 | * Grab the CQ lock to synchronize the "rearm" setting for | ||
| 546 | * the doorbell, and for clearing the "processing" flag. | ||
| 547 | */ | ||
| 548 | spin_lock_irqsave(&pfob->cq_lock, pfob->cq_irq); | ||
| 549 | |||
| 550 | /* | ||
| 551 | * Rearm the cq. This is done based on the global mcc->rearm | ||
| 552 | * flag which combines the rearm parameter from the current | ||
| 553 | * call to process_cq and any other threads | ||
| 554 | * that tried to process the CQ while this one was active. | ||
| 555 | * This handles the situation where a sync. fwcmd was processing | ||
| 556 | * the CQ while the interrupt/dpc tries to process it. | ||
| 557 | * The sync process gets to continue -- but it is now | ||
| 558 | * responsible for the rearming. | ||
| 559 | */ | ||
| 560 | if (num_processed > 0 || mcc->rearm == true) { | ||
| 561 | db.dw[0] = 0; /* clear */ | ||
| 562 | AMAP_SET_BITS_PTR(CQ_DB, qid, &db, cq_ring->id); | ||
| 563 | AMAP_SET_BITS_PTR(CQ_DB, rearm, &db, mcc->rearm); | ||
| 564 | AMAP_SET_BITS_PTR(CQ_DB, event, &db, false); | ||
| 565 | AMAP_SET_BITS_PTR(CQ_DB, num_popped, &db, num_processed); | ||
| 566 | |||
| 567 | PD_WRITE(pfob, cq_db, db.dw[0]); | ||
| 568 | } | ||
| 569 | /* | ||
| 570 | * Update the consumer index after ringing the CQ doorbell. | ||
| 571 | * We don't want another thread to post more WRBs before we | ||
| 572 | * have CQ space available. | ||
| 573 | */ | ||
| 574 | mp_ring_consume_multiple(mp_ring, consumed); | ||
| 575 | |||
| 576 | /* Clear the processing flag. */ | ||
| 577 | mcc->processing = 0; | ||
| 578 | |||
| 579 | Error: | ||
| 580 | spin_unlock_irqrestore(&pfob->cq_lock, pfob->cq_irq); | ||
| 581 | /* | ||
| 582 | * Use the local variable to detect if the current thread | ||
| 583 | * holds the WRB post lock. If rearm is false, this is | ||
| 584 | * either a synchronous command, or the upper layer driver is polling | ||
| 585 | * from a thread. We do not drive the queue from that | ||
| 586 | * context since the driver may hold the | ||
| 587 | * wrb post lock already. | ||
| 588 | */ | ||
| 589 | if (rearm) | ||
| 590 | be_drive_mcc_wrb_queue(mcc); | ||
| 591 | else | ||
| 592 | pfob->pend_queue_driving = 1; | ||
| 593 | |||
| 594 | return BE_SUCCESS; | ||
| 595 | } | ||
| 596 | |||
| 597 | /* | ||
| 598 | *============================================================================ | ||
| 599 | * P U B L I C R O U T I N E S | ||
| 600 | *============================================================================ | ||
| 601 | */ | ||
| 602 | |||
| 603 | /* | ||
| 604 | This routine creates an MCC object. This object contains an MCC send queue | ||
| 605 | and a CQ private to the MCC. | ||
| 606 | |||
| 607 | pcontroller - Handle to a function object | ||
| 608 | |||
| 609 | EqObject - EQ object that will be used to dispatch this MCC | ||
| 610 | |||
| 611 | ppMccObject - Pointer to an internal Mcc Object returned. | ||
| 612 | |||
| 613 | Returns BE_SUCCESS if successfull,, otherwise a useful error code | ||
| 614 | is returned. | ||
| 615 | |||
| 616 | IRQL < DISPATCH_LEVEL | ||
| 617 | |||
| 618 | */ | ||
| 619 | int | ||
| 620 | be_mcc_ring_create(struct be_function_object *pfob, | ||
| 621 | struct ring_desc *rd, u32 length, | ||
| 622 | struct be_mcc_wrb_context *context_array, | ||
| 623 | u32 num_context_entries, | ||
| 624 | struct be_cq_object *cq, struct be_mcc_object *mcc) | ||
| 625 | { | ||
| 626 | int status = 0; | ||
| 627 | |||
| 628 | struct FWCMD_COMMON_MCC_CREATE *fwcmd = NULL; | ||
| 629 | struct MCC_WRB_AMAP *wrb = NULL; | ||
| 630 | u32 num_entries_encoded, n, i; | ||
| 631 | void *va = NULL; | ||
| 632 | unsigned long irql; | ||
| 633 | |||
| 634 | if (length < sizeof(struct MCC_WRB_AMAP) * 2) { | ||
| 635 | TRACE(DL_ERR, "Invalid MCC ring length:%d", length); | ||
| 636 | return BE_NOT_OK; | ||
| 637 | } | ||
| 638 | /* | ||
| 639 | * Reduce the actual ring size to be less than the number | ||
| 640 | * of context entries. This ensures that we run out of | ||
| 641 | * ring WRBs first so the queuing works correctly. We never | ||
| 642 | * queue based on context structs. | ||
| 643 | */ | ||
| 644 | if (num_context_entries + 1 < | ||
| 645 | length / sizeof(struct MCC_WRB_AMAP) - 1) { | ||
| 646 | |||
| 647 | u32 max_length = | ||
| 648 | (num_context_entries + 2) * sizeof(struct MCC_WRB_AMAP); | ||
| 649 | |||
| 650 | if (is_power_of_2(max_length)) | ||
| 651 | length = __roundup_pow_of_two(max_length+1) / 2; | ||
| 652 | else | ||
| 653 | length = __roundup_pow_of_two(max_length) / 2; | ||
| 654 | |||
| 655 | ASSERT(length <= max_length); | ||
| 656 | |||
| 657 | TRACE(DL_WARN, | ||
| 658 | "MCC ring length reduced based on context entries." | ||
| 659 | " length:%d wrbs:%d context_entries:%d", length, | ||
| 660 | (int) (length / sizeof(struct MCC_WRB_AMAP)), | ||
| 661 | num_context_entries); | ||
| 662 | } | ||
| 663 | |||
| 664 | spin_lock_irqsave(&pfob->post_lock, irql); | ||
| 665 | |||
| 666 | num_entries_encoded = | ||
| 667 | be_ring_length_to_encoding(length, sizeof(struct MCC_WRB_AMAP)); | ||
| 668 | |||
| 669 | /* Init MCC object. */ | ||
| 670 | memset(mcc, 0, sizeof(*mcc)); | ||
| 671 | mcc->parent_function = pfob; | ||
| 672 | mcc->cq_object = cq; | ||
| 673 | |||
| 674 | INIT_LIST_HEAD(&mcc->backlog); | ||
| 675 | |||
| 676 | wrb = be_function_peek_mcc_wrb(pfob); | ||
| 677 | if (!wrb) { | ||
| 678 | ASSERT(wrb); | ||
| 679 | TRACE(DL_ERR, "No free MCC WRBs in create EQ."); | ||
| 680 | status = BE_STATUS_NO_MCC_WRB; | ||
| 681 | goto error; | ||
| 682 | } | ||
| 683 | /* Prepares an embedded fwcmd, including request/response sizes. */ | ||
| 684 | fwcmd = BE_PREPARE_EMBEDDED_FWCMD(pfob, wrb, COMMON_MCC_CREATE); | ||
| 685 | |||
| 686 | fwcmd->params.request.num_pages = DIV_ROUND_UP(length, PAGE_SIZE); | ||
| 687 | /* | ||
| 688 | * Program MCC ring context | ||
| 689 | */ | ||
| 690 | AMAP_SET_BITS_PTR(MCC_RING_CONTEXT, pdid, | ||
| 691 | &fwcmd->params.request.context, 0); | ||
| 692 | AMAP_SET_BITS_PTR(MCC_RING_CONTEXT, invalid, | ||
| 693 | &fwcmd->params.request.context, false); | ||
| 694 | AMAP_SET_BITS_PTR(MCC_RING_CONTEXT, ring_size, | ||
| 695 | &fwcmd->params.request.context, num_entries_encoded); | ||
| 696 | |||
| 697 | n = cq->cq_id; | ||
| 698 | AMAP_SET_BITS_PTR(MCC_RING_CONTEXT, | ||
| 699 | cq_id, &fwcmd->params.request.context, n); | ||
| 700 | be_rd_to_pa_list(rd, fwcmd->params.request.pages, | ||
| 701 | ARRAY_SIZE(fwcmd->params.request.pages)); | ||
| 702 | /* Post the f/w command */ | ||
| 703 | status = be_function_post_mcc_wrb(pfob, wrb, NULL, NULL, NULL, | ||
| 704 | NULL, NULL, fwcmd, NULL); | ||
| 705 | if (status != BE_SUCCESS) { | ||
| 706 | TRACE(DL_ERR, "MCC to create CQ failed."); | ||
| 707 | goto error; | ||
| 708 | } | ||
| 709 | /* | ||
| 710 | * Create a linked list of context structures | ||
| 711 | */ | ||
| 712 | mcc->wrb_context.base = context_array; | ||
| 713 | mcc->wrb_context.num = num_context_entries; | ||
| 714 | INIT_LIST_HEAD(&mcc->wrb_context.list_head); | ||
| 715 | memset(context_array, 0, | ||
| 716 | sizeof(struct be_mcc_wrb_context) * num_context_entries); | ||
| 717 | for (i = 0; i < mcc->wrb_context.num; i++) { | ||
| 718 | list_add_tail(&context_array[i].next, | ||
| 719 | &mcc->wrb_context.list_head); | ||
| 720 | } | ||
| 721 | |||
| 722 | /* | ||
| 723 | * | ||
| 724 | * Create an mcc_ring for tracking WRB hw ring | ||
| 725 | */ | ||
| 726 | va = rd->va; | ||
| 727 | ASSERT(va); | ||
| 728 | mp_ring_create(&mcc->sq.ring, length / sizeof(struct MCC_WRB_AMAP), | ||
| 729 | sizeof(struct MCC_WRB_AMAP), va); | ||
| 730 | mcc->sq.ring.id = fwcmd->params.response.id; | ||
| 731 | /* | ||
| 732 | * Init a mcc_ring for tracking the MCC CQ. | ||
| 733 | */ | ||
| 734 | ASSERT(cq->va); | ||
| 735 | mp_ring_create(&mcc->cq.ring, cq->num_entries, | ||
| 736 | sizeof(struct MCC_CQ_ENTRY_AMAP), cq->va); | ||
| 737 | mcc->cq.ring.id = cq->cq_id; | ||
| 738 | |||
| 739 | /* Force zeroing of CQ. */ | ||
| 740 | memset(cq->va, 0, cq->num_entries * sizeof(struct MCC_CQ_ENTRY_AMAP)); | ||
| 741 | |||
| 742 | /* Initialize debug index. */ | ||
| 743 | mcc->consumed_index = 0; | ||
| 744 | |||
| 745 | atomic_inc(&cq->ref_count); | ||
| 746 | pfob->mcc = mcc; | ||
| 747 | |||
| 748 | TRACE(DL_INFO, "MCC ring created. id:%d bytes:%d cq_id:%d cq_entries:%d" | ||
| 749 | " num_context:%d", mcc->sq.ring.id, length, | ||
| 750 | cq->cq_id, cq->num_entries, num_context_entries); | ||
| 751 | |||
| 752 | error: | ||
| 753 | spin_unlock_irqrestore(&pfob->post_lock, irql); | ||
| 754 | if (pfob->pend_queue_driving && pfob->mcc) { | ||
| 755 | pfob->pend_queue_driving = 0; | ||
| 756 | be_drive_mcc_wrb_queue(pfob->mcc); | ||
| 757 | } | ||
| 758 | return status; | ||
| 759 | } | ||
| 760 | |||
| 761 | /* | ||
| 762 | This routine destroys an MCC send queue | ||
| 763 | |||
| 764 | MccObject - Internal Mcc Object to be destroyed. | ||
| 765 | |||
| 766 | Returns BE_SUCCESS if successfull, otherwise an error code is returned. | ||
| 767 | |||
| 768 | IRQL < DISPATCH_LEVEL | ||
| 769 | |||
| 770 | The caller of this routine must ensure that no other WRB may be posted | ||
| 771 | until this routine returns. | ||
| 772 | |||
| 773 | */ | ||
| 774 | int be_mcc_ring_destroy(struct be_mcc_object *mcc) | ||
| 775 | { | ||
| 776 | int status = 0; | ||
| 777 | struct be_function_object *pfob = mcc->parent_function; | ||
| 778 | |||
| 779 | |||
| 780 | ASSERT(mcc->processing == 0); | ||
| 781 | |||
| 782 | /* | ||
| 783 | * Remove the ring from the function object. | ||
| 784 | * This transitions back to mailbox mode. | ||
| 785 | */ | ||
| 786 | pfob->mcc = NULL; | ||
| 787 | |||
| 788 | /* Send fwcmd to destroy the queue. (Using the mailbox.) */ | ||
| 789 | status = be_function_ring_destroy(mcc->parent_function, mcc->sq.ring.id, | ||
| 790 | FWCMD_RING_TYPE_MCC, NULL, NULL, NULL, NULL); | ||
| 791 | ASSERT(status == 0); | ||
| 792 | |||
| 793 | /* Release the SQ reference to the CQ */ | ||
| 794 | atomic_dec(&mcc->cq_object->ref_count); | ||
| 795 | |||
| 796 | return status; | ||
| 797 | } | ||
| 798 | |||
| 799 | static void | ||
| 800 | mcc_wrb_sync_cb(void *context, int staus, struct MCC_WRB_AMAP *wrb) | ||
| 801 | { | ||
| 802 | struct be_mcc_wrb_context *wrb_context = | ||
| 803 | (struct be_mcc_wrb_context *) context; | ||
| 804 | ASSERT(wrb_context); | ||
| 805 | *wrb_context->users_final_status = staus; | ||
| 806 | } | ||
| 807 | |||
| 808 | /* | ||
| 809 | This routine posts a command to the MCC send queue | ||
| 810 | |||
| 811 | mcc - Internal Mcc Object to be destroyed. | ||
| 812 | |||
| 813 | wrb - wrb to post. | ||
| 814 | |||
| 815 | Returns BE_SUCCESS if successfull, otherwise an error code is returned. | ||
| 816 | |||
| 817 | IRQL < DISPATCH_LEVEL if CompletionCallback is not NULL | ||
| 818 | IRQL <=DISPATCH_LEVEL if CompletionCallback is NULL | ||
| 819 | |||
| 820 | If this routine is called with CompletionCallback != NULL the | ||
| 821 | call is considered to be asynchronous and will return as soon | ||
| 822 | as the WRB is posted to the MCC with BE_PENDING. | ||
| 823 | |||
| 824 | If CompletionCallback is NULL, then this routine will not return until | ||
| 825 | a completion for this MCC command has been processed. | ||
| 826 | If called at DISPATCH_LEVEL the CompletionCallback must be NULL. | ||
| 827 | |||
| 828 | This routine should only be called if the MPU has been boostraped past | ||
| 829 | mailbox mode. | ||
| 830 | |||
| 831 | |||
| 832 | */ | ||
| 833 | int | ||
| 834 | _be_mpu_post_wrb_ring(struct be_mcc_object *mcc, struct MCC_WRB_AMAP *wrb, | ||
| 835 | struct be_mcc_wrb_context *wrb_context) | ||
| 836 | { | ||
| 837 | |||
| 838 | struct MCC_WRB_AMAP *ring_wrb = NULL; | ||
| 839 | int status = BE_PENDING; | ||
| 840 | int final_status = BE_PENDING; | ||
| 841 | mcc_wrb_cqe_callback cb = NULL; | ||
| 842 | struct MCC_DB_AMAP mcc_db; | ||
| 843 | u32 embedded; | ||
| 844 | |||
| 845 | ASSERT(mp_ring_num_empty(&mcc->sq.ring) > 0); | ||
| 846 | /* | ||
| 847 | * Input wrb is most likely the next wrb in the ring, since the client | ||
| 848 | * can peek at the address. | ||
| 849 | */ | ||
| 850 | ring_wrb = mp_ring_producer_ptr(&mcc->sq.ring); | ||
| 851 | if (wrb != ring_wrb) { | ||
| 852 | /* If not equal, copy it into the ring. */ | ||
| 853 | memcpy(ring_wrb, wrb, sizeof(struct MCC_WRB_AMAP)); | ||
| 854 | } | ||
| 855 | #ifdef BE_DEBUG | ||
| 856 | wrb_context->ring_wrb = ring_wrb; | ||
| 857 | #endif | ||
| 858 | embedded = AMAP_GET_BITS_PTR(MCC_WRB, embedded, ring_wrb); | ||
| 859 | if (embedded) { | ||
| 860 | /* embedded commands will have the response within the WRB. */ | ||
| 861 | wrb_context->wrb = ring_wrb; | ||
| 862 | } else { | ||
| 863 | /* | ||
| 864 | * non-embedded commands will not have the response | ||
| 865 | * within the WRB, and they may complete out-of-order. | ||
| 866 | * The WRB will not be valid to inspect | ||
| 867 | * during the completion. | ||
| 868 | */ | ||
| 869 | wrb_context->wrb = NULL; | ||
| 870 | } | ||
| 871 | cb = wrb_context->cb; | ||
| 872 | |||
| 873 | if (cb == NULL) { | ||
| 874 | /* Assign our internal callback if this is a | ||
| 875 | * synchronous call. */ | ||
| 876 | wrb_context->cb = mcc_wrb_sync_cb; | ||
| 877 | wrb_context->cb_context = wrb_context; | ||
| 878 | wrb_context->users_final_status = &final_status; | ||
| 879 | } | ||
| 880 | /* Increment producer index */ | ||
| 881 | |||
| 882 | mcc_db.dw[0] = 0; /* initialize */ | ||
| 883 | AMAP_SET_BITS_PTR(MCC_DB, rid, &mcc_db, mcc->sq.ring.id); | ||
| 884 | AMAP_SET_BITS_PTR(MCC_DB, numPosted, &mcc_db, 1); | ||
| 885 | |||
| 886 | mp_ring_produce(&mcc->sq.ring); | ||
| 887 | PD_WRITE(mcc->parent_function, mpu_mcc_db, mcc_db.dw[0]); | ||
| 888 | TRACE(DL_INFO, "pidx: %x and cidx: %x.", mcc->sq.ring.pidx, | ||
| 889 | mcc->sq.ring.cidx); | ||
| 890 | |||
| 891 | if (cb == NULL) { | ||
| 892 | int polls = 0; /* At >= 1 us per poll */ | ||
| 893 | /* Wait until this command completes, polling the CQ. */ | ||
| 894 | do { | ||
| 895 | TRACE(DL_INFO, "FWCMD submitted in the poll mode."); | ||
| 896 | /* Do not rearm CQ in this context. */ | ||
| 897 | be_mcc_process_cq(mcc, false); | ||
| 898 | |||
| 899 | if (final_status == BE_PENDING) { | ||
| 900 | if ((++polls & 0x7FFFF) == 0) { | ||
| 901 | TRACE(DL_WARN, | ||
| 902 | "Warning : polling MCC CQ for %d" | ||
| 903 | "ms.", polls / 1000); | ||
| 904 | } | ||
| 905 | |||
| 906 | udelay(1); | ||
| 907 | } | ||
| 908 | |||
| 909 | /* final_status changed when the command completes */ | ||
| 910 | } while (final_status == BE_PENDING); | ||
| 911 | |||
| 912 | status = final_status; | ||
| 913 | } | ||
| 914 | |||
| 915 | return status; | ||
| 916 | } | ||
| 917 | |||
| 918 | struct MCC_WRB_AMAP * | ||
| 919 | _be_mpu_peek_ring_wrb(struct be_mcc_object *mcc, bool driving_queue) | ||
| 920 | { | ||
| 921 | /* If we have queued items, do not allow a post to bypass the queue. */ | ||
| 922 | if (!driving_queue && !list_empty(&mcc->backlog)) | ||
| 923 | return NULL; | ||
| 924 | |||
| 925 | if (mp_ring_num_empty(&mcc->sq.ring) <= 0) | ||
| 926 | return NULL; | ||
| 927 | return (struct MCC_WRB_AMAP *) mp_ring_producer_ptr(&mcc->sq.ring); | ||
| 928 | } | ||
| 929 | |||
| 930 | int | ||
| 931 | be_mpu_init_mailbox(struct be_function_object *pfob, struct ring_desc *mailbox) | ||
| 932 | { | ||
| 933 | ASSERT(mailbox); | ||
| 934 | pfob->mailbox.va = mailbox->va; | ||
| 935 | pfob->mailbox.pa = cpu_to_le64(mailbox->pa); | ||
| 936 | pfob->mailbox.length = mailbox->length; | ||
| 937 | |||
| 938 | ASSERT(((u32)(size_t)pfob->mailbox.va & 0xf) == 0); | ||
| 939 | ASSERT(((u32)(size_t)pfob->mailbox.pa & 0xf) == 0); | ||
| 940 | /* | ||
| 941 | * Issue the WRB to set MPU endianness | ||
| 942 | */ | ||
| 943 | { | ||
| 944 | u64 *endian_check = (u64 *) (pfob->mailbox.va + | ||
| 945 | offsetof(struct BE_MCC_MAILBOX_AMAP, wrb)/8); | ||
| 946 | *endian_check = 0xFF1234FFFF5678FFULL; | ||
| 947 | } | ||
| 948 | |||
| 949 | be_mcc_mailbox_notify_and_wait(pfob); | ||
| 950 | |||
| 951 | return BE_SUCCESS; | ||
| 952 | } | ||
| 953 | |||
| 954 | |||
| 955 | /* | ||
| 956 | This routine posts a command to the MCC mailbox. | ||
| 957 | |||
| 958 | FuncObj - Function Object to post the WRB on behalf of. | ||
| 959 | wrb - wrb to post. | ||
| 960 | CompletionCallback - Address of a callback routine to invoke once the WRB | ||
| 961 | is completed. | ||
| 962 | CompletionCallbackContext - Opaque context to be passed during the call to | ||
| 963 | the CompletionCallback. | ||
| 964 | Returns BE_SUCCESS if successfull, otherwise an error code is returned. | ||
| 965 | |||
| 966 | IRQL <=DISPATCH_LEVEL if CompletionCallback is NULL | ||
| 967 | |||
| 968 | This routine will block until a completion for this MCC command has been | ||
| 969 | processed. If called at DISPATCH_LEVEL the CompletionCallback must be NULL. | ||
| 970 | |||
| 971 | This routine should only be called if the MPU has not been boostraped past | ||
| 972 | mailbox mode. | ||
| 973 | */ | ||
| 974 | int | ||
| 975 | _be_mpu_post_wrb_mailbox(struct be_function_object *pfob, | ||
| 976 | struct MCC_WRB_AMAP *wrb, struct be_mcc_wrb_context *wrb_context) | ||
| 977 | { | ||
| 978 | struct MCC_MAILBOX_AMAP *mailbox = NULL; | ||
| 979 | struct MCC_WRB_AMAP *mb_wrb; | ||
| 980 | struct MCC_CQ_ENTRY_AMAP *mb_cq; | ||
| 981 | u32 offset, status; | ||
| 982 | |||
| 983 | ASSERT(pfob->mcc == NULL); | ||
| 984 | mailbox = pfob->mailbox.va; | ||
| 985 | ASSERT(mailbox); | ||
| 986 | |||
| 987 | offset = offsetof(struct BE_MCC_MAILBOX_AMAP, wrb)/8; | ||
| 988 | mb_wrb = (struct MCC_WRB_AMAP *) (u8 *)mailbox + offset; | ||
| 989 | if (mb_wrb != wrb) { | ||
| 990 | memset(mailbox, 0, sizeof(*mailbox)); | ||
| 991 | memcpy(mb_wrb, wrb, sizeof(struct MCC_WRB_AMAP)); | ||
| 992 | } | ||
| 993 | /* The callback can inspect the final WRB to get output parameters. */ | ||
| 994 | wrb_context->wrb = mb_wrb; | ||
| 995 | |||
| 996 | be_mcc_mailbox_notify_and_wait(pfob); | ||
| 997 | |||
| 998 | /* A command completed. Use tag to determine which command. */ | ||
| 999 | offset = offsetof(struct BE_MCC_MAILBOX_AMAP, cq)/8; | ||
| 1000 | mb_cq = (struct MCC_CQ_ENTRY_AMAP *) ((u8 *)mailbox + offset); | ||
| 1001 | be_mcc_process_cqe(pfob, mb_cq); | ||
| 1002 | |||
| 1003 | status = AMAP_GET_BITS_PTR(MCC_CQ_ENTRY, completion_status, mb_cq); | ||
| 1004 | if (status) | ||
| 1005 | status = BE_NOT_OK; | ||
| 1006 | return status; | ||
| 1007 | } | ||
| 1008 | |||
| 1009 | struct be_mcc_wrb_context * | ||
| 1010 | _be_mcc_allocate_wrb_context(struct be_function_object *pfob) | ||
| 1011 | { | ||
| 1012 | struct be_mcc_wrb_context *context = NULL; | ||
| 1013 | unsigned long irq; | ||
| 1014 | |||
| 1015 | spin_lock_irqsave(&pfob->mcc_context_lock, irq); | ||
| 1016 | |||
| 1017 | if (!pfob->mailbox.default_context_allocated) { | ||
| 1018 | /* Use the single default context that we | ||
| 1019 | * always have allocated. */ | ||
| 1020 | pfob->mailbox.default_context_allocated = true; | ||
| 1021 | context = &pfob->mailbox.default_context; | ||
| 1022 | } else if (pfob->mcc) { | ||
| 1023 | /* Get a context from the free list. If any are available. */ | ||
| 1024 | if (!list_empty(&pfob->mcc->wrb_context.list_head)) { | ||
| 1025 | context = list_first_entry( | ||
| 1026 | &pfob->mcc->wrb_context.list_head, | ||
| 1027 | struct be_mcc_wrb_context, next); | ||
| 1028 | } | ||
| 1029 | } | ||
| 1030 | |||
| 1031 | spin_unlock_irqrestore(&pfob->mcc_context_lock, irq); | ||
| 1032 | |||
| 1033 | return context; | ||
| 1034 | } | ||
| 1035 | |||
| 1036 | void | ||
| 1037 | _be_mcc_free_wrb_context(struct be_function_object *pfob, | ||
| 1038 | struct be_mcc_wrb_context *context) | ||
| 1039 | { | ||
| 1040 | unsigned long irq; | ||
| 1041 | |||
| 1042 | ASSERT(context); | ||
| 1043 | /* | ||
| 1044 | * Zero during free to try and catch any bugs where the context | ||
| 1045 | * is accessed after a free. | ||
| 1046 | */ | ||
| 1047 | memset(context, 0, sizeof(context)); | ||
| 1048 | |||
| 1049 | spin_lock_irqsave(&pfob->mcc_context_lock, irq); | ||
| 1050 | |||
| 1051 | if (context == &pfob->mailbox.default_context) { | ||
| 1052 | /* Free the default context. */ | ||
| 1053 | ASSERT(pfob->mailbox.default_context_allocated); | ||
| 1054 | pfob->mailbox.default_context_allocated = false; | ||
| 1055 | } else { | ||
| 1056 | /* Add to free list. */ | ||
| 1057 | ASSERT(pfob->mcc); | ||
| 1058 | list_add_tail(&context->next, | ||
| 1059 | &pfob->mcc->wrb_context.list_head); | ||
| 1060 | } | ||
| 1061 | |||
| 1062 | spin_unlock_irqrestore(&pfob->mcc_context_lock, irq); | ||
| 1063 | } | ||
| 1064 | |||
| 1065 | int | ||
| 1066 | be_mcc_add_async_event_callback(struct be_mcc_object *mcc_object, | ||
| 1067 | mcc_async_event_callback cb, void *cb_context) | ||
| 1068 | { | ||
| 1069 | /* Lock against anyone trying to change the callback/context pointers | ||
| 1070 | * while being used. */ | ||
| 1071 | spin_lock_irqsave(&mcc_object->parent_function->cq_lock, | ||
| 1072 | mcc_object->parent_function->cq_irq); | ||
| 1073 | |||
| 1074 | /* Assign the async callback. */ | ||
| 1075 | mcc_object->async_context = cb_context; | ||
| 1076 | mcc_object->async_cb = cb; | ||
| 1077 | |||
| 1078 | spin_unlock_irqrestore(&mcc_object->parent_function->cq_lock, | ||
| 1079 | mcc_object->parent_function->cq_irq); | ||
| 1080 | |||
| 1081 | return BE_SUCCESS; | ||
| 1082 | } | ||
| 1083 | |||
| 1084 | #define MPU_EP_CONTROL 0 | ||
| 1085 | #define MPU_EP_SEMAPHORE 0xac | ||
| 1086 | |||
| 1087 | /* | ||
| 1088 | *------------------------------------------------------------------- | ||
| 1089 | * Function: be_wait_for_POST_complete | ||
| 1090 | * Waits until the BladeEngine POST completes (either in error or success). | ||
| 1091 | * pfob - | ||
| 1092 | * return status - BE_SUCCESS (0) on success. Negative error code on failure. | ||
| 1093 | *------------------------------------------------------------------- | ||
| 1094 | */ | ||
| 1095 | static int be_wait_for_POST_complete(struct be_function_object *pfob) | ||
| 1096 | { | ||
| 1097 | struct MGMT_HBA_POST_STATUS_STRUCT_AMAP status; | ||
| 1098 | int s; | ||
| 1099 | u32 post_error, post_stage; | ||
| 1100 | |||
| 1101 | const u32 us_per_loop = 1000; /* 1000us */ | ||
| 1102 | const u32 print_frequency_loops = 1000000 / us_per_loop; | ||
| 1103 | const u32 max_loops = 60 * print_frequency_loops; | ||
| 1104 | u32 loops = 0; | ||
| 1105 | |||
| 1106 | /* | ||
| 1107 | * Wait for arm fw indicating it is done or a fatal error happened. | ||
| 1108 | * Note: POST can take some time to complete depending on configuration | ||
| 1109 | * settings (consider ARM attempts to acquire an IP address | ||
| 1110 | * over DHCP!!!). | ||
| 1111 | * | ||
| 1112 | */ | ||
| 1113 | do { | ||
| 1114 | status.dw[0] = ioread32(pfob->csr_va + MPU_EP_SEMAPHORE); | ||
| 1115 | post_error = AMAP_GET_BITS_PTR(MGMT_HBA_POST_STATUS_STRUCT, | ||
| 1116 | error, &status); | ||
| 1117 | post_stage = AMAP_GET_BITS_PTR(MGMT_HBA_POST_STATUS_STRUCT, | ||
| 1118 | stage, &status); | ||
| 1119 | if (0 == (loops % print_frequency_loops)) { | ||
| 1120 | /* Print current status */ | ||
| 1121 | TRACE(DL_INFO, "POST status = 0x%x (stage = 0x%x)", | ||
| 1122 | status.dw[0], post_stage); | ||
| 1123 | } | ||
| 1124 | udelay(us_per_loop); | ||
| 1125 | } while ((post_error != 1) && | ||
| 1126 | (post_stage != POST_STAGE_ARMFW_READY) && | ||
| 1127 | (++loops < max_loops)); | ||
| 1128 | |||
| 1129 | if (post_error == 1) { | ||
| 1130 | TRACE(DL_ERR, "POST error! Status = 0x%x (stage = 0x%x)", | ||
| 1131 | status.dw[0], post_stage); | ||
| 1132 | s = BE_NOT_OK; | ||
| 1133 | } else if (post_stage != POST_STAGE_ARMFW_READY) { | ||
| 1134 | TRACE(DL_ERR, "POST time-out! Status = 0x%x (stage = 0x%x)", | ||
| 1135 | status.dw[0], post_stage); | ||
| 1136 | s = BE_NOT_OK; | ||
| 1137 | } else { | ||
| 1138 | s = BE_SUCCESS; | ||
| 1139 | } | ||
| 1140 | return s; | ||
| 1141 | } | ||
| 1142 | |||
| 1143 | /* | ||
| 1144 | *------------------------------------------------------------------- | ||
| 1145 | * Function: be_kickoff_and_wait_for_POST | ||
| 1146 | * Interacts with the BladeEngine management processor to initiate POST, and | ||
| 1147 | * subsequently waits until POST completes (either in error or success). | ||
| 1148 | * The caller must acquire the reset semaphore before initiating POST | ||
| 1149 | * to prevent multiple drivers interacting with the management processor. | ||
| 1150 | * Once POST is complete the caller must release the reset semaphore. | ||
| 1151 | * Callers who only want to wait for POST complete may call | ||
| 1152 | * be_wait_for_POST_complete. | ||
| 1153 | * pfob - | ||
| 1154 | * return status - BE_SUCCESS (0) on success. Negative error code on failure. | ||
| 1155 | *------------------------------------------------------------------- | ||
| 1156 | */ | ||
| 1157 | static int | ||
| 1158 | be_kickoff_and_wait_for_POST(struct be_function_object *pfob) | ||
| 1159 | { | ||
| 1160 | struct MGMT_HBA_POST_STATUS_STRUCT_AMAP status; | ||
| 1161 | int s; | ||
| 1162 | |||
| 1163 | const u32 us_per_loop = 1000; /* 1000us */ | ||
| 1164 | const u32 print_frequency_loops = 1000000 / us_per_loop; | ||
| 1165 | const u32 max_loops = 5 * print_frequency_loops; | ||
| 1166 | u32 loops = 0; | ||
| 1167 | u32 post_error, post_stage; | ||
| 1168 | |||
| 1169 | /* Wait for arm fw awaiting host ready or a fatal error happened. */ | ||
| 1170 | TRACE(DL_INFO, "Wait for BladeEngine ready to POST"); | ||
| 1171 | do { | ||
| 1172 | status.dw[0] = ioread32(pfob->csr_va + MPU_EP_SEMAPHORE); | ||
| 1173 | post_error = AMAP_GET_BITS_PTR(MGMT_HBA_POST_STATUS_STRUCT, | ||
| 1174 | error, &status); | ||
| 1175 | post_stage = AMAP_GET_BITS_PTR(MGMT_HBA_POST_STATUS_STRUCT, | ||
| 1176 | stage, &status); | ||
| 1177 | if (0 == (loops % print_frequency_loops)) { | ||
| 1178 | /* Print current status */ | ||
| 1179 | TRACE(DL_INFO, "POST status = 0x%x (stage = 0x%x)", | ||
| 1180 | status.dw[0], post_stage); | ||
| 1181 | } | ||
| 1182 | udelay(us_per_loop); | ||
| 1183 | } while ((post_error != 1) && | ||
| 1184 | (post_stage < POST_STAGE_AWAITING_HOST_RDY) && | ||
| 1185 | (++loops < max_loops)); | ||
| 1186 | |||
| 1187 | if (post_error == 1) { | ||
| 1188 | TRACE(DL_ERR, "Pre-POST error! Status = 0x%x (stage = 0x%x)", | ||
| 1189 | status.dw[0], post_stage); | ||
| 1190 | s = BE_NOT_OK; | ||
| 1191 | } else if (post_stage == POST_STAGE_AWAITING_HOST_RDY) { | ||
| 1192 | iowrite32(POST_STAGE_HOST_RDY, pfob->csr_va + MPU_EP_SEMAPHORE); | ||
| 1193 | |||
| 1194 | /* Wait for POST to complete */ | ||
| 1195 | s = be_wait_for_POST_complete(pfob); | ||
| 1196 | } else { | ||
| 1197 | /* | ||
| 1198 | * Either a timeout waiting for host ready signal or POST has | ||
| 1199 | * moved ahead without requiring a host ready signal. | ||
| 1200 | * Might as well give POST a chance to complete | ||
| 1201 | * (or timeout again). | ||
| 1202 | */ | ||
| 1203 | s = be_wait_for_POST_complete(pfob); | ||
| 1204 | } | ||
| 1205 | return s; | ||
| 1206 | } | ||
| 1207 | |||
| 1208 | /* | ||
| 1209 | *------------------------------------------------------------------- | ||
| 1210 | * Function: be_pci_soft_reset | ||
| 1211 | * This function is called to issue a BladeEngine soft reset. | ||
| 1212 | * Callers should acquire the soft reset semaphore before calling this | ||
| 1213 | * function. Additionaly, callers should ensure they cannot be pre-empted | ||
| 1214 | * while the routine executes. Upon completion of this routine, callers | ||
| 1215 | * should release the reset semaphore. This routine implicitly waits | ||
| 1216 | * for BladeEngine POST to complete. | ||
| 1217 | * pfob - | ||
| 1218 | * return status - BE_SUCCESS (0) on success. Negative error code on failure. | ||
| 1219 | *------------------------------------------------------------------- | ||
| 1220 | */ | ||
| 1221 | int be_pci_soft_reset(struct be_function_object *pfob) | ||
| 1222 | { | ||
| 1223 | struct PCICFG_SOFT_RESET_CSR_AMAP soft_reset; | ||
| 1224 | struct PCICFG_ONLINE0_CSR_AMAP pciOnline0; | ||
| 1225 | struct PCICFG_ONLINE1_CSR_AMAP pciOnline1; | ||
| 1226 | struct EP_CONTROL_CSR_AMAP epControlCsr; | ||
| 1227 | int status = BE_SUCCESS; | ||
| 1228 | u32 i, soft_reset_bit; | ||
| 1229 | |||
| 1230 | TRACE(DL_NOTE, "PCI reset..."); | ||
| 1231 | |||
| 1232 | /* Issue soft reset #1 to get BladeEngine into a known state. */ | ||
| 1233 | soft_reset.dw[0] = PCICFG0_READ(pfob, soft_reset); | ||
| 1234 | AMAP_SET_BITS_PTR(PCICFG_SOFT_RESET_CSR, softreset, soft_reset.dw, 1); | ||
| 1235 | PCICFG0_WRITE(pfob, host_timer_int_ctrl, soft_reset.dw[0]); | ||
| 1236 | /* | ||
| 1237 | * wait til soft reset is deasserted - hardware | ||
| 1238 | * deasserts after some time. | ||
| 1239 | */ | ||
| 1240 | i = 0; | ||
| 1241 | do { | ||
| 1242 | udelay(50); | ||
| 1243 | soft_reset.dw[0] = PCICFG0_READ(pfob, soft_reset); | ||
| 1244 | soft_reset_bit = AMAP_GET_BITS_PTR(PCICFG_SOFT_RESET_CSR, | ||
| 1245 | softreset, soft_reset.dw); | ||
| 1246 | } while (soft_reset_bit && (i++ < 1024)); | ||
| 1247 | if (soft_reset_bit != 0) { | ||
| 1248 | TRACE(DL_ERR, "Soft-reset #1 did not deassert as expected."); | ||
| 1249 | status = BE_NOT_OK; | ||
| 1250 | goto Error_label; | ||
| 1251 | } | ||
| 1252 | /* Mask everything */ | ||
| 1253 | PCICFG0_WRITE(pfob, ue_status_low_mask, 0xFFFFFFFF); | ||
| 1254 | PCICFG0_WRITE(pfob, ue_status_hi_mask, 0xFFFFFFFF); | ||
| 1255 | /* | ||
| 1256 | * Set everything offline except MPU IRAM (it is offline with | ||
| 1257 | * the soft-reset, but soft-reset does not reset the PCICFG registers!) | ||
| 1258 | */ | ||
| 1259 | pciOnline0.dw[0] = 0; | ||
| 1260 | pciOnline1.dw[0] = 0; | ||
| 1261 | AMAP_SET_BITS_PTR(PCICFG_ONLINE1_CSR, mpu_iram_online, | ||
| 1262 | pciOnline1.dw, 1); | ||
| 1263 | PCICFG0_WRITE(pfob, online0, pciOnline0.dw[0]); | ||
| 1264 | PCICFG0_WRITE(pfob, online1, pciOnline1.dw[0]); | ||
| 1265 | |||
| 1266 | udelay(20000); | ||
| 1267 | |||
| 1268 | /* Issue soft reset #2. */ | ||
| 1269 | AMAP_SET_BITS_PTR(PCICFG_SOFT_RESET_CSR, softreset, soft_reset.dw, 1); | ||
| 1270 | PCICFG0_WRITE(pfob, host_timer_int_ctrl, soft_reset.dw[0]); | ||
| 1271 | /* | ||
| 1272 | * wait til soft reset is deasserted - hardware | ||
| 1273 | * deasserts after some time. | ||
| 1274 | */ | ||
| 1275 | i = 0; | ||
| 1276 | do { | ||
| 1277 | udelay(50); | ||
| 1278 | soft_reset.dw[0] = PCICFG0_READ(pfob, soft_reset); | ||
| 1279 | soft_reset_bit = AMAP_GET_BITS_PTR(PCICFG_SOFT_RESET_CSR, | ||
| 1280 | softreset, soft_reset.dw); | ||
| 1281 | } while (soft_reset_bit && (i++ < 1024)); | ||
| 1282 | if (soft_reset_bit != 0) { | ||
| 1283 | TRACE(DL_ERR, "Soft-reset #1 did not deassert as expected."); | ||
| 1284 | status = BE_NOT_OK; | ||
| 1285 | goto Error_label; | ||
| 1286 | } | ||
| 1287 | |||
| 1288 | |||
| 1289 | udelay(20000); | ||
| 1290 | |||
| 1291 | /* Take MPU out of reset. */ | ||
| 1292 | |||
| 1293 | epControlCsr.dw[0] = ioread32(pfob->csr_va + MPU_EP_CONTROL); | ||
| 1294 | AMAP_SET_BITS_PTR(EP_CONTROL_CSR, CPU_reset, &epControlCsr, 0); | ||
| 1295 | iowrite32((u32)epControlCsr.dw[0], pfob->csr_va + MPU_EP_CONTROL); | ||
| 1296 | |||
| 1297 | /* Kickoff BE POST and wait for completion */ | ||
| 1298 | status = be_kickoff_and_wait_for_POST(pfob); | ||
| 1299 | |||
| 1300 | Error_label: | ||
| 1301 | return status; | ||
| 1302 | } | ||
| 1303 | |||
| 1304 | |||
| 1305 | /* | ||
| 1306 | *------------------------------------------------------------------- | ||
| 1307 | * Function: be_pci_reset_required | ||
| 1308 | * This private function is called to detect if a host entity is | ||
| 1309 | * required to issue a PCI soft reset and subsequently drive | ||
| 1310 | * BladeEngine POST. Scenarios where this is required: | ||
| 1311 | * 1) BIOS-less configuration | ||
| 1312 | * 2) Hot-swap/plug/power-on | ||
| 1313 | * pfob - | ||
| 1314 | * return true if a reset is required, false otherwise | ||
| 1315 | *------------------------------------------------------------------- | ||
| 1316 | */ | ||
| 1317 | static bool be_pci_reset_required(struct be_function_object *pfob) | ||
| 1318 | { | ||
| 1319 | struct MGMT_HBA_POST_STATUS_STRUCT_AMAP status; | ||
| 1320 | bool do_reset = false; | ||
| 1321 | u32 post_error, post_stage; | ||
| 1322 | |||
| 1323 | /* | ||
| 1324 | * Read the POST status register | ||
| 1325 | */ | ||
| 1326 | status.dw[0] = ioread32(pfob->csr_va + MPU_EP_SEMAPHORE); | ||
| 1327 | post_error = AMAP_GET_BITS_PTR(MGMT_HBA_POST_STATUS_STRUCT, error, | ||
| 1328 | &status); | ||
| 1329 | post_stage = AMAP_GET_BITS_PTR(MGMT_HBA_POST_STATUS_STRUCT, stage, | ||
| 1330 | &status); | ||
| 1331 | if (post_stage <= POST_STAGE_AWAITING_HOST_RDY) { | ||
| 1332 | /* | ||
| 1333 | * If BladeEngine is waiting for host ready indication, | ||
| 1334 | * we want to do a PCI reset. | ||
| 1335 | */ | ||
| 1336 | do_reset = true; | ||
| 1337 | } | ||
| 1338 | |||
| 1339 | return do_reset; | ||
| 1340 | } | ||
| 1341 | |||
| 1342 | /* | ||
| 1343 | *------------------------------------------------------------------- | ||
| 1344 | * Function: be_drive_POST | ||
| 1345 | * This function is called to drive BladeEngine POST. The | ||
| 1346 | * caller should ensure they cannot be pre-empted while this routine executes. | ||
| 1347 | * pfob - | ||
| 1348 | * return status - BE_SUCCESS (0) on success. Negative error code on failure. | ||
| 1349 | *------------------------------------------------------------------- | ||
| 1350 | */ | ||
| 1351 | int be_drive_POST(struct be_function_object *pfob) | ||
| 1352 | { | ||
| 1353 | int status; | ||
| 1354 | |||
| 1355 | if (false != be_pci_reset_required(pfob)) { | ||
| 1356 | /* PCI reset is needed (implicitly starts and waits for POST) */ | ||
| 1357 | status = be_pci_soft_reset(pfob); | ||
| 1358 | } else { | ||
| 1359 | /* No PCI reset is needed, start POST */ | ||
| 1360 | status = be_kickoff_and_wait_for_POST(pfob); | ||
| 1361 | } | ||
| 1362 | |||
| 1363 | return status; | ||
| 1364 | } | ||
diff --git a/drivers/staging/benet/mpu.h b/drivers/staging/benet/mpu.h deleted file mode 100644 index 41f3f87516e5..000000000000 --- a/drivers/staging/benet/mpu.h +++ /dev/null | |||
| @@ -1,74 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __mpu_amap_h__ | ||
| 21 | #define __mpu_amap_h__ | ||
| 22 | #include "ep.h" | ||
| 23 | |||
| 24 | /* Provide control parameters for the Managment Processor Unit. */ | ||
| 25 | struct BE_MPU_CSRMAP_AMAP { | ||
| 26 | struct BE_EP_CSRMAP_AMAP ep; | ||
| 27 | u8 rsvd0[128]; /* DWORD 64 */ | ||
| 28 | u8 rsvd1[32]; /* DWORD 68 */ | ||
| 29 | u8 rsvd2[192]; /* DWORD 69 */ | ||
| 30 | u8 rsvd3[192]; /* DWORD 75 */ | ||
| 31 | u8 rsvd4[32]; /* DWORD 81 */ | ||
| 32 | u8 rsvd5[32]; /* DWORD 82 */ | ||
| 33 | u8 rsvd6[32]; /* DWORD 83 */ | ||
| 34 | u8 rsvd7[32]; /* DWORD 84 */ | ||
| 35 | u8 rsvd8[32]; /* DWORD 85 */ | ||
| 36 | u8 rsvd9[32]; /* DWORD 86 */ | ||
| 37 | u8 rsvd10[32]; /* DWORD 87 */ | ||
| 38 | u8 rsvd11[32]; /* DWORD 88 */ | ||
| 39 | u8 rsvd12[32]; /* DWORD 89 */ | ||
| 40 | u8 rsvd13[32]; /* DWORD 90 */ | ||
| 41 | u8 rsvd14[32]; /* DWORD 91 */ | ||
| 42 | u8 rsvd15[32]; /* DWORD 92 */ | ||
| 43 | u8 rsvd16[32]; /* DWORD 93 */ | ||
| 44 | u8 rsvd17[32]; /* DWORD 94 */ | ||
| 45 | u8 rsvd18[32]; /* DWORD 95 */ | ||
| 46 | u8 rsvd19[32]; /* DWORD 96 */ | ||
| 47 | u8 rsvd20[32]; /* DWORD 97 */ | ||
| 48 | u8 rsvd21[32]; /* DWORD 98 */ | ||
| 49 | u8 rsvd22[32]; /* DWORD 99 */ | ||
| 50 | u8 rsvd23[32]; /* DWORD 100 */ | ||
| 51 | u8 rsvd24[32]; /* DWORD 101 */ | ||
| 52 | u8 rsvd25[32]; /* DWORD 102 */ | ||
| 53 | u8 rsvd26[32]; /* DWORD 103 */ | ||
| 54 | u8 rsvd27[32]; /* DWORD 104 */ | ||
| 55 | u8 rsvd28[96]; /* DWORD 105 */ | ||
| 56 | u8 rsvd29[32]; /* DWORD 108 */ | ||
| 57 | u8 rsvd30[32]; /* DWORD 109 */ | ||
| 58 | u8 rsvd31[32]; /* DWORD 110 */ | ||
| 59 | u8 rsvd32[32]; /* DWORD 111 */ | ||
| 60 | u8 rsvd33[32]; /* DWORD 112 */ | ||
| 61 | u8 rsvd34[96]; /* DWORD 113 */ | ||
| 62 | u8 rsvd35[32]; /* DWORD 116 */ | ||
| 63 | u8 rsvd36[32]; /* DWORD 117 */ | ||
| 64 | u8 rsvd37[32]; /* DWORD 118 */ | ||
| 65 | u8 rsvd38[32]; /* DWORD 119 */ | ||
| 66 | u8 rsvd39[32]; /* DWORD 120 */ | ||
| 67 | u8 rsvd40[32]; /* DWORD 121 */ | ||
| 68 | u8 rsvd41[134][32]; /* DWORD 122 */ | ||
| 69 | } __packed; | ||
| 70 | struct MPU_CSRMAP_AMAP { | ||
| 71 | u32 dw[256]; | ||
| 72 | }; | ||
| 73 | |||
| 74 | #endif /* __mpu_amap_h__ */ | ||
diff --git a/drivers/staging/benet/mpu_context.h b/drivers/staging/benet/mpu_context.h deleted file mode 100644 index 8ce90f9c46c2..000000000000 --- a/drivers/staging/benet/mpu_context.h +++ /dev/null | |||
| @@ -1,46 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __mpu_context_amap_h__ | ||
| 21 | #define __mpu_context_amap_h__ | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Management command and control ring context. The MPUs BTLR_CTRL1 CSR | ||
| 25 | * controls the writeback behavior of the producer and consumer index values. | ||
| 26 | */ | ||
| 27 | struct BE_MCC_RING_CONTEXT_AMAP { | ||
| 28 | u8 con_index[16]; /* DWORD 0 */ | ||
| 29 | u8 ring_size[4]; /* DWORD 0 */ | ||
| 30 | u8 cq_id[11]; /* DWORD 0 */ | ||
| 31 | u8 rsvd0; /* DWORD 0 */ | ||
| 32 | u8 prod_index[16]; /* DWORD 1 */ | ||
| 33 | u8 pdid[15]; /* DWORD 1 */ | ||
| 34 | u8 invalid; /* DWORD 1 */ | ||
| 35 | u8 cmd_pending_current[7]; /* DWORD 2 */ | ||
| 36 | u8 rsvd1[25]; /* DWORD 2 */ | ||
| 37 | u8 hpi_port_cq_id[11]; /* DWORD 3 */ | ||
| 38 | u8 rsvd2[5]; /* DWORD 3 */ | ||
| 39 | u8 cmd_pending_max[7]; /* DWORD 3 */ | ||
| 40 | u8 rsvd3[9]; /* DWORD 3 */ | ||
| 41 | } __packed; | ||
| 42 | struct MCC_RING_CONTEXT_AMAP { | ||
| 43 | u32 dw[4]; | ||
| 44 | }; | ||
| 45 | |||
| 46 | #endif /* __mpu_context_amap_h__ */ | ||
diff --git a/drivers/staging/benet/pcicfg.h b/drivers/staging/benet/pcicfg.h deleted file mode 100644 index 7c15684adf4a..000000000000 --- a/drivers/staging/benet/pcicfg.h +++ /dev/null | |||
| @@ -1,825 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __pcicfg_amap_h__ | ||
| 21 | #define __pcicfg_amap_h__ | ||
| 22 | |||
| 23 | /* Vendor and Device ID Register. */ | ||
| 24 | struct BE_PCICFG_ID_CSR_AMAP { | ||
| 25 | u8 vendorid[16]; /* DWORD 0 */ | ||
| 26 | u8 deviceid[16]; /* DWORD 0 */ | ||
| 27 | } __packed; | ||
| 28 | struct PCICFG_ID_CSR_AMAP { | ||
| 29 | u32 dw[1]; | ||
| 30 | }; | ||
| 31 | |||
| 32 | /* IO Bar Register. */ | ||
| 33 | struct BE_PCICFG_IOBAR_CSR_AMAP { | ||
| 34 | u8 iospace; /* DWORD 0 */ | ||
| 35 | u8 rsvd0[7]; /* DWORD 0 */ | ||
| 36 | u8 iobar[24]; /* DWORD 0 */ | ||
| 37 | } __packed; | ||
| 38 | struct PCICFG_IOBAR_CSR_AMAP { | ||
| 39 | u32 dw[1]; | ||
| 40 | }; | ||
| 41 | |||
| 42 | /* Memory BAR 0 Register. */ | ||
| 43 | struct BE_PCICFG_MEMBAR0_CSR_AMAP { | ||
| 44 | u8 memspace; /* DWORD 0 */ | ||
| 45 | u8 type[2]; /* DWORD 0 */ | ||
| 46 | u8 pf; /* DWORD 0 */ | ||
| 47 | u8 rsvd0[10]; /* DWORD 0 */ | ||
| 48 | u8 membar0[18]; /* DWORD 0 */ | ||
| 49 | } __packed; | ||
| 50 | struct PCICFG_MEMBAR0_CSR_AMAP { | ||
| 51 | u32 dw[1]; | ||
| 52 | }; | ||
| 53 | |||
| 54 | /* Memory BAR 1 - Low Address Register. */ | ||
| 55 | struct BE_PCICFG_MEMBAR1_LO_CSR_AMAP { | ||
| 56 | u8 memspace; /* DWORD 0 */ | ||
| 57 | u8 type[2]; /* DWORD 0 */ | ||
| 58 | u8 pf; /* DWORD 0 */ | ||
| 59 | u8 rsvd0[13]; /* DWORD 0 */ | ||
| 60 | u8 membar1lo[15]; /* DWORD 0 */ | ||
| 61 | } __packed; | ||
| 62 | struct PCICFG_MEMBAR1_LO_CSR_AMAP { | ||
| 63 | u32 dw[1]; | ||
| 64 | }; | ||
| 65 | |||
| 66 | /* Memory BAR 1 - High Address Register. */ | ||
| 67 | struct BE_PCICFG_MEMBAR1_HI_CSR_AMAP { | ||
| 68 | u8 membar1hi[32]; /* DWORD 0 */ | ||
| 69 | } __packed; | ||
| 70 | struct PCICFG_MEMBAR1_HI_CSR_AMAP { | ||
| 71 | u32 dw[1]; | ||
| 72 | }; | ||
| 73 | |||
| 74 | /* Memory BAR 2 - Low Address Register. */ | ||
| 75 | struct BE_PCICFG_MEMBAR2_LO_CSR_AMAP { | ||
| 76 | u8 memspace; /* DWORD 0 */ | ||
| 77 | u8 type[2]; /* DWORD 0 */ | ||
| 78 | u8 pf; /* DWORD 0 */ | ||
| 79 | u8 rsvd0[17]; /* DWORD 0 */ | ||
| 80 | u8 membar2lo[11]; /* DWORD 0 */ | ||
| 81 | } __packed; | ||
| 82 | struct PCICFG_MEMBAR2_LO_CSR_AMAP { | ||
| 83 | u32 dw[1]; | ||
| 84 | }; | ||
| 85 | |||
| 86 | /* Memory BAR 2 - High Address Register. */ | ||
| 87 | struct BE_PCICFG_MEMBAR2_HI_CSR_AMAP { | ||
| 88 | u8 membar2hi[32]; /* DWORD 0 */ | ||
| 89 | } __packed; | ||
| 90 | struct PCICFG_MEMBAR2_HI_CSR_AMAP { | ||
| 91 | u32 dw[1]; | ||
| 92 | }; | ||
| 93 | |||
| 94 | /* Subsystem Vendor and ID (Function 0) Register. */ | ||
| 95 | struct BE_PCICFG_SUBSYSTEM_ID_F0_CSR_AMAP { | ||
| 96 | u8 subsys_vendor_id[16]; /* DWORD 0 */ | ||
| 97 | u8 subsys_id[16]; /* DWORD 0 */ | ||
| 98 | } __packed; | ||
| 99 | struct PCICFG_SUBSYSTEM_ID_F0_CSR_AMAP { | ||
| 100 | u32 dw[1]; | ||
| 101 | }; | ||
| 102 | |||
| 103 | /* Subsystem Vendor and ID (Function 1) Register. */ | ||
| 104 | struct BE_PCICFG_SUBSYSTEM_ID_F1_CSR_AMAP { | ||
| 105 | u8 subsys_vendor_id[16]; /* DWORD 0 */ | ||
| 106 | u8 subsys_id[16]; /* DWORD 0 */ | ||
| 107 | } __packed; | ||
| 108 | struct PCICFG_SUBSYSTEM_ID_F1_CSR_AMAP { | ||
| 109 | u32 dw[1]; | ||
| 110 | }; | ||
| 111 | |||
| 112 | /* Semaphore Register. */ | ||
| 113 | struct BE_PCICFG_SEMAPHORE_CSR_AMAP { | ||
| 114 | u8 locked; /* DWORD 0 */ | ||
| 115 | u8 rsvd0[31]; /* DWORD 0 */ | ||
| 116 | } __packed; | ||
| 117 | struct PCICFG_SEMAPHORE_CSR_AMAP { | ||
| 118 | u32 dw[1]; | ||
| 119 | }; | ||
| 120 | |||
| 121 | /* Soft Reset Register. */ | ||
| 122 | struct BE_PCICFG_SOFT_RESET_CSR_AMAP { | ||
| 123 | u8 rsvd0[7]; /* DWORD 0 */ | ||
| 124 | u8 softreset; /* DWORD 0 */ | ||
| 125 | u8 rsvd1[16]; /* DWORD 0 */ | ||
| 126 | u8 nec_ll_rcvdetect_i[8]; /* DWORD 0 */ | ||
| 127 | } __packed; | ||
| 128 | struct PCICFG_SOFT_RESET_CSR_AMAP { | ||
| 129 | u32 dw[1]; | ||
| 130 | }; | ||
| 131 | |||
| 132 | /* Unrecoverable Error Status (Low) Register. Each bit corresponds to | ||
| 133 | * an internal Unrecoverable Error. These are set by hardware and may be | ||
| 134 | * cleared by writing a one to the respective bit(s) to be cleared. Any | ||
| 135 | * bit being set that is also unmasked will result in Unrecoverable Error | ||
| 136 | * interrupt notification to the host CPU and/or Server Management chip | ||
| 137 | * and the transitioning of BladeEngine to an Offline state. | ||
| 138 | */ | ||
| 139 | struct BE_PCICFG_UE_STATUS_LOW_CSR_AMAP { | ||
| 140 | u8 cev_ue_status; /* DWORD 0 */ | ||
| 141 | u8 ctx_ue_status; /* DWORD 0 */ | ||
| 142 | u8 dbuf_ue_status; /* DWORD 0 */ | ||
| 143 | u8 erx_ue_status; /* DWORD 0 */ | ||
| 144 | u8 host_ue_status; /* DWORD 0 */ | ||
| 145 | u8 mpu_ue_status; /* DWORD 0 */ | ||
| 146 | u8 ndma_ue_status; /* DWORD 0 */ | ||
| 147 | u8 ptc_ue_status; /* DWORD 0 */ | ||
| 148 | u8 rdma_ue_status; /* DWORD 0 */ | ||
| 149 | u8 rxf_ue_status; /* DWORD 0 */ | ||
| 150 | u8 rxips_ue_status; /* DWORD 0 */ | ||
| 151 | u8 rxulp0_ue_status; /* DWORD 0 */ | ||
| 152 | u8 rxulp1_ue_status; /* DWORD 0 */ | ||
| 153 | u8 rxulp2_ue_status; /* DWORD 0 */ | ||
| 154 | u8 tim_ue_status; /* DWORD 0 */ | ||
| 155 | u8 tpost_ue_status; /* DWORD 0 */ | ||
| 156 | u8 tpre_ue_status; /* DWORD 0 */ | ||
| 157 | u8 txips_ue_status; /* DWORD 0 */ | ||
| 158 | u8 txulp0_ue_status; /* DWORD 0 */ | ||
| 159 | u8 txulp1_ue_status; /* DWORD 0 */ | ||
| 160 | u8 uc_ue_status; /* DWORD 0 */ | ||
| 161 | u8 wdma_ue_status; /* DWORD 0 */ | ||
| 162 | u8 txulp2_ue_status; /* DWORD 0 */ | ||
| 163 | u8 host1_ue_status; /* DWORD 0 */ | ||
| 164 | u8 p0_ob_link_ue_status; /* DWORD 0 */ | ||
| 165 | u8 p1_ob_link_ue_status; /* DWORD 0 */ | ||
| 166 | u8 host_gpio_ue_status; /* DWORD 0 */ | ||
| 167 | u8 mbox_netw_ue_status; /* DWORD 0 */ | ||
| 168 | u8 mbox_stor_ue_status; /* DWORD 0 */ | ||
| 169 | u8 axgmac0_ue_status; /* DWORD 0 */ | ||
| 170 | u8 axgmac1_ue_status; /* DWORD 0 */ | ||
| 171 | u8 mpu_intpend_ue_status; /* DWORD 0 */ | ||
| 172 | } __packed; | ||
| 173 | struct PCICFG_UE_STATUS_LOW_CSR_AMAP { | ||
| 174 | u32 dw[1]; | ||
| 175 | }; | ||
| 176 | |||
| 177 | /* Unrecoverable Error Status (High) Register. Each bit corresponds to | ||
| 178 | * an internal Unrecoverable Error. These are set by hardware and may be | ||
| 179 | * cleared by writing a one to the respective bit(s) to be cleared. Any | ||
| 180 | * bit being set that is also unmasked will result in Unrecoverable Error | ||
| 181 | * interrupt notification to the host CPU and/or Server Management chip; | ||
| 182 | * and the transitioning of BladeEngine to an Offline state. | ||
| 183 | */ | ||
| 184 | struct BE_PCICFG_UE_STATUS_HI_CSR_AMAP { | ||
| 185 | u8 jtag_ue_status; /* DWORD 0 */ | ||
| 186 | u8 lpcmemhost_ue_status; /* DWORD 0 */ | ||
| 187 | u8 mgmt_mac_ue_status; /* DWORD 0 */ | ||
| 188 | u8 mpu_iram_ue_status; /* DWORD 0 */ | ||
| 189 | u8 pcs0online_ue_status; /* DWORD 0 */ | ||
| 190 | u8 pcs1online_ue_status; /* DWORD 0 */ | ||
| 191 | u8 pctl0_ue_status; /* DWORD 0 */ | ||
| 192 | u8 pctl1_ue_status; /* DWORD 0 */ | ||
| 193 | u8 pmem_ue_status; /* DWORD 0 */ | ||
| 194 | u8 rr_ue_status; /* DWORD 0 */ | ||
| 195 | u8 rxpp_ue_status; /* DWORD 0 */ | ||
| 196 | u8 txpb_ue_status; /* DWORD 0 */ | ||
| 197 | u8 txp_ue_status; /* DWORD 0 */ | ||
| 198 | u8 xaui_ue_status; /* DWORD 0 */ | ||
| 199 | u8 arm_ue_status; /* DWORD 0 */ | ||
| 200 | u8 ipc_ue_status; /* DWORD 0 */ | ||
| 201 | u8 rsvd0[16]; /* DWORD 0 */ | ||
| 202 | } __packed; | ||
| 203 | struct PCICFG_UE_STATUS_HI_CSR_AMAP { | ||
| 204 | u32 dw[1]; | ||
| 205 | }; | ||
| 206 | |||
| 207 | /* Unrecoverable Error Mask (Low) Register. Each bit, when set to one, | ||
| 208 | * will mask the associated Unrecoverable Error status bit from notification | ||
| 209 | * of Unrecoverable Error to the host CPU and/or Server Managment chip and the | ||
| 210 | * transitioning of all BladeEngine units to an Offline state. | ||
| 211 | */ | ||
| 212 | struct BE_PCICFG_UE_STATUS_LOW_MASK_CSR_AMAP { | ||
| 213 | u8 cev_ue_mask; /* DWORD 0 */ | ||
| 214 | u8 ctx_ue_mask; /* DWORD 0 */ | ||
| 215 | u8 dbuf_ue_mask; /* DWORD 0 */ | ||
| 216 | u8 erx_ue_mask; /* DWORD 0 */ | ||
| 217 | u8 host_ue_mask; /* DWORD 0 */ | ||
| 218 | u8 mpu_ue_mask; /* DWORD 0 */ | ||
| 219 | u8 ndma_ue_mask; /* DWORD 0 */ | ||
| 220 | u8 ptc_ue_mask; /* DWORD 0 */ | ||
| 221 | u8 rdma_ue_mask; /* DWORD 0 */ | ||
| 222 | u8 rxf_ue_mask; /* DWORD 0 */ | ||
| 223 | u8 rxips_ue_mask; /* DWORD 0 */ | ||
| 224 | u8 rxulp0_ue_mask; /* DWORD 0 */ | ||
| 225 | u8 rxulp1_ue_mask; /* DWORD 0 */ | ||
| 226 | u8 rxulp2_ue_mask; /* DWORD 0 */ | ||
| 227 | u8 tim_ue_mask; /* DWORD 0 */ | ||
| 228 | u8 tpost_ue_mask; /* DWORD 0 */ | ||
| 229 | u8 tpre_ue_mask; /* DWORD 0 */ | ||
| 230 | u8 txips_ue_mask; /* DWORD 0 */ | ||
| 231 | u8 txulp0_ue_mask; /* DWORD 0 */ | ||
| 232 | u8 txulp1_ue_mask; /* DWORD 0 */ | ||
| 233 | u8 uc_ue_mask; /* DWORD 0 */ | ||
| 234 | u8 wdma_ue_mask; /* DWORD 0 */ | ||
| 235 | u8 txulp2_ue_mask; /* DWORD 0 */ | ||
| 236 | u8 host1_ue_mask; /* DWORD 0 */ | ||
| 237 | u8 p0_ob_link_ue_mask; /* DWORD 0 */ | ||
| 238 | u8 p1_ob_link_ue_mask; /* DWORD 0 */ | ||
| 239 | u8 host_gpio_ue_mask; /* DWORD 0 */ | ||
| 240 | u8 mbox_netw_ue_mask; /* DWORD 0 */ | ||
| 241 | u8 mbox_stor_ue_mask; /* DWORD 0 */ | ||
| 242 | u8 axgmac0_ue_mask; /* DWORD 0 */ | ||
| 243 | u8 axgmac1_ue_mask; /* DWORD 0 */ | ||
| 244 | u8 mpu_intpend_ue_mask; /* DWORD 0 */ | ||
| 245 | } __packed; | ||
| 246 | struct PCICFG_UE_STATUS_LOW_MASK_CSR_AMAP { | ||
| 247 | u32 dw[1]; | ||
| 248 | }; | ||
| 249 | |||
| 250 | /* Unrecoverable Error Mask (High) Register. Each bit, when set to one, | ||
| 251 | * will mask the associated Unrecoverable Error status bit from notification | ||
| 252 | * of Unrecoverable Error to the host CPU and/or Server Managment chip and the | ||
| 253 | * transitioning of all BladeEngine units to an Offline state. | ||
| 254 | */ | ||
| 255 | struct BE_PCICFG_UE_STATUS_HI_MASK_CSR_AMAP { | ||
| 256 | u8 jtag_ue_mask; /* DWORD 0 */ | ||
| 257 | u8 lpcmemhost_ue_mask; /* DWORD 0 */ | ||
| 258 | u8 mgmt_mac_ue_mask; /* DWORD 0 */ | ||
| 259 | u8 mpu_iram_ue_mask; /* DWORD 0 */ | ||
| 260 | u8 pcs0online_ue_mask; /* DWORD 0 */ | ||
| 261 | u8 pcs1online_ue_mask; /* DWORD 0 */ | ||
| 262 | u8 pctl0_ue_mask; /* DWORD 0 */ | ||
| 263 | u8 pctl1_ue_mask; /* DWORD 0 */ | ||
| 264 | u8 pmem_ue_mask; /* DWORD 0 */ | ||
| 265 | u8 rr_ue_mask; /* DWORD 0 */ | ||
| 266 | u8 rxpp_ue_mask; /* DWORD 0 */ | ||
| 267 | u8 txpb_ue_mask; /* DWORD 0 */ | ||
| 268 | u8 txp_ue_mask; /* DWORD 0 */ | ||
| 269 | u8 xaui_ue_mask; /* DWORD 0 */ | ||
| 270 | u8 arm_ue_mask; /* DWORD 0 */ | ||
| 271 | u8 ipc_ue_mask; /* DWORD 0 */ | ||
| 272 | u8 rsvd0[16]; /* DWORD 0 */ | ||
| 273 | } __packed; | ||
| 274 | struct PCICFG_UE_STATUS_HI_MASK_CSR_AMAP { | ||
| 275 | u32 dw[1]; | ||
| 276 | }; | ||
| 277 | |||
| 278 | /* Online Control Register 0. This register controls various units within | ||
| 279 | * BladeEngine being in an Online or Offline state. | ||
| 280 | */ | ||
| 281 | struct BE_PCICFG_ONLINE0_CSR_AMAP { | ||
| 282 | u8 cev_online; /* DWORD 0 */ | ||
| 283 | u8 ctx_online; /* DWORD 0 */ | ||
| 284 | u8 dbuf_online; /* DWORD 0 */ | ||
| 285 | u8 erx_online; /* DWORD 0 */ | ||
| 286 | u8 host_online; /* DWORD 0 */ | ||
| 287 | u8 mpu_online; /* DWORD 0 */ | ||
| 288 | u8 ndma_online; /* DWORD 0 */ | ||
| 289 | u8 ptc_online; /* DWORD 0 */ | ||
| 290 | u8 rdma_online; /* DWORD 0 */ | ||
| 291 | u8 rxf_online; /* DWORD 0 */ | ||
| 292 | u8 rxips_online; /* DWORD 0 */ | ||
| 293 | u8 rxulp0_online; /* DWORD 0 */ | ||
| 294 | u8 rxulp1_online; /* DWORD 0 */ | ||
| 295 | u8 rxulp2_online; /* DWORD 0 */ | ||
| 296 | u8 tim_online; /* DWORD 0 */ | ||
| 297 | u8 tpost_online; /* DWORD 0 */ | ||
| 298 | u8 tpre_online; /* DWORD 0 */ | ||
| 299 | u8 txips_online; /* DWORD 0 */ | ||
| 300 | u8 txulp0_online; /* DWORD 0 */ | ||
| 301 | u8 txulp1_online; /* DWORD 0 */ | ||
| 302 | u8 uc_online; /* DWORD 0 */ | ||
| 303 | u8 wdma_online; /* DWORD 0 */ | ||
| 304 | u8 txulp2_online; /* DWORD 0 */ | ||
| 305 | u8 host1_online; /* DWORD 0 */ | ||
| 306 | u8 p0_ob_link_online; /* DWORD 0 */ | ||
| 307 | u8 p1_ob_link_online; /* DWORD 0 */ | ||
| 308 | u8 host_gpio_online; /* DWORD 0 */ | ||
| 309 | u8 mbox_netw_online; /* DWORD 0 */ | ||
| 310 | u8 mbox_stor_online; /* DWORD 0 */ | ||
| 311 | u8 axgmac0_online; /* DWORD 0 */ | ||
| 312 | u8 axgmac1_online; /* DWORD 0 */ | ||
| 313 | u8 mpu_intpend_online; /* DWORD 0 */ | ||
| 314 | } __packed; | ||
| 315 | struct PCICFG_ONLINE0_CSR_AMAP { | ||
| 316 | u32 dw[1]; | ||
| 317 | }; | ||
| 318 | |||
| 319 | /* Online Control Register 1. This register controls various units within | ||
| 320 | * BladeEngine being in an Online or Offline state. | ||
| 321 | */ | ||
| 322 | struct BE_PCICFG_ONLINE1_CSR_AMAP { | ||
| 323 | u8 jtag_online; /* DWORD 0 */ | ||
| 324 | u8 lpcmemhost_online; /* DWORD 0 */ | ||
| 325 | u8 mgmt_mac_online; /* DWORD 0 */ | ||
| 326 | u8 mpu_iram_online; /* DWORD 0 */ | ||
| 327 | u8 pcs0online_online; /* DWORD 0 */ | ||
| 328 | u8 pcs1online_online; /* DWORD 0 */ | ||
| 329 | u8 pctl0_online; /* DWORD 0 */ | ||
| 330 | u8 pctl1_online; /* DWORD 0 */ | ||
| 331 | u8 pmem_online; /* DWORD 0 */ | ||
| 332 | u8 rr_online; /* DWORD 0 */ | ||
| 333 | u8 rxpp_online; /* DWORD 0 */ | ||
| 334 | u8 txpb_online; /* DWORD 0 */ | ||
| 335 | u8 txp_online; /* DWORD 0 */ | ||
| 336 | u8 xaui_online; /* DWORD 0 */ | ||
| 337 | u8 arm_online; /* DWORD 0 */ | ||
| 338 | u8 ipc_online; /* DWORD 0 */ | ||
| 339 | u8 rsvd0[16]; /* DWORD 0 */ | ||
| 340 | } __packed; | ||
| 341 | struct PCICFG_ONLINE1_CSR_AMAP { | ||
| 342 | u32 dw[1]; | ||
| 343 | }; | ||
| 344 | |||
| 345 | /* Host Timer Register. */ | ||
| 346 | struct BE_PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP { | ||
| 347 | u8 hosttimer[24]; /* DWORD 0 */ | ||
| 348 | u8 hostintr; /* DWORD 0 */ | ||
| 349 | u8 rsvd0[7]; /* DWORD 0 */ | ||
| 350 | } __packed; | ||
| 351 | struct PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP { | ||
| 352 | u32 dw[1]; | ||
| 353 | }; | ||
| 354 | |||
| 355 | /* Scratchpad Register (for software use). */ | ||
| 356 | struct BE_PCICFG_SCRATCHPAD_CSR_AMAP { | ||
| 357 | u8 scratchpad[32]; /* DWORD 0 */ | ||
| 358 | } __packed; | ||
| 359 | struct PCICFG_SCRATCHPAD_CSR_AMAP { | ||
| 360 | u32 dw[1]; | ||
| 361 | }; | ||
| 362 | |||
| 363 | /* PCI Express Capabilities Register. */ | ||
| 364 | struct BE_PCICFG_PCIE_CAP_CSR_AMAP { | ||
| 365 | u8 capid[8]; /* DWORD 0 */ | ||
| 366 | u8 nextcap[8]; /* DWORD 0 */ | ||
| 367 | u8 capver[4]; /* DWORD 0 */ | ||
| 368 | u8 devport[4]; /* DWORD 0 */ | ||
| 369 | u8 rsvd0[6]; /* DWORD 0 */ | ||
| 370 | u8 rsvd1[2]; /* DWORD 0 */ | ||
| 371 | } __packed; | ||
| 372 | struct PCICFG_PCIE_CAP_CSR_AMAP { | ||
| 373 | u32 dw[1]; | ||
| 374 | }; | ||
| 375 | |||
| 376 | /* PCI Express Device Capabilities Register. */ | ||
| 377 | struct BE_PCICFG_PCIE_DEVCAP_CSR_AMAP { | ||
| 378 | u8 payload[3]; /* DWORD 0 */ | ||
| 379 | u8 rsvd0[3]; /* DWORD 0 */ | ||
| 380 | u8 lo_lat[3]; /* DWORD 0 */ | ||
| 381 | u8 l1_lat[3]; /* DWORD 0 */ | ||
| 382 | u8 rsvd1[3]; /* DWORD 0 */ | ||
| 383 | u8 rsvd2[3]; /* DWORD 0 */ | ||
| 384 | u8 pwr_value[8]; /* DWORD 0 */ | ||
| 385 | u8 pwr_scale[2]; /* DWORD 0 */ | ||
| 386 | u8 rsvd3[4]; /* DWORD 0 */ | ||
| 387 | } __packed; | ||
| 388 | struct PCICFG_PCIE_DEVCAP_CSR_AMAP { | ||
| 389 | u32 dw[1]; | ||
| 390 | }; | ||
| 391 | |||
| 392 | /* PCI Express Device Control/Status Registers. */ | ||
| 393 | struct BE_PCICFG_PCIE_CONTROL_STATUS_CSR_AMAP { | ||
| 394 | u8 CorrErrReportEn; /* DWORD 0 */ | ||
| 395 | u8 NonFatalErrReportEn; /* DWORD 0 */ | ||
| 396 | u8 FatalErrReportEn; /* DWORD 0 */ | ||
| 397 | u8 UnsuppReqReportEn; /* DWORD 0 */ | ||
| 398 | u8 EnableRelaxOrder; /* DWORD 0 */ | ||
| 399 | u8 Max_Payload_Size[3]; /* DWORD 0 */ | ||
| 400 | u8 ExtendTagFieldEnable; /* DWORD 0 */ | ||
| 401 | u8 PhantomFnEnable; /* DWORD 0 */ | ||
| 402 | u8 AuxPwrPMEnable; /* DWORD 0 */ | ||
| 403 | u8 EnableNoSnoop; /* DWORD 0 */ | ||
| 404 | u8 Max_Read_Req_Size[3]; /* DWORD 0 */ | ||
| 405 | u8 rsvd0; /* DWORD 0 */ | ||
| 406 | u8 CorrErrDetect; /* DWORD 0 */ | ||
| 407 | u8 NonFatalErrDetect; /* DWORD 0 */ | ||
| 408 | u8 FatalErrDetect; /* DWORD 0 */ | ||
| 409 | u8 UnsuppReqDetect; /* DWORD 0 */ | ||
| 410 | u8 AuxPwrDetect; /* DWORD 0 */ | ||
| 411 | u8 TransPending; /* DWORD 0 */ | ||
| 412 | u8 rsvd1[10]; /* DWORD 0 */ | ||
| 413 | } __packed; | ||
| 414 | struct PCICFG_PCIE_CONTROL_STATUS_CSR_AMAP { | ||
| 415 | u32 dw[1]; | ||
| 416 | }; | ||
| 417 | |||
| 418 | /* PCI Express Link Capabilities Register. */ | ||
| 419 | struct BE_PCICFG_PCIE_LINK_CAP_CSR_AMAP { | ||
| 420 | u8 MaxLinkSpeed[4]; /* DWORD 0 */ | ||
| 421 | u8 MaxLinkWidth[6]; /* DWORD 0 */ | ||
| 422 | u8 ASPMSupport[2]; /* DWORD 0 */ | ||
| 423 | u8 L0sExitLat[3]; /* DWORD 0 */ | ||
| 424 | u8 L1ExitLat[3]; /* DWORD 0 */ | ||
| 425 | u8 rsvd0[6]; /* DWORD 0 */ | ||
| 426 | u8 PortNum[8]; /* DWORD 0 */ | ||
| 427 | } __packed; | ||
| 428 | struct PCICFG_PCIE_LINK_CAP_CSR_AMAP { | ||
| 429 | u32 dw[1]; | ||
| 430 | }; | ||
| 431 | |||
| 432 | /* PCI Express Link Status Register. */ | ||
| 433 | struct BE_PCICFG_PCIE_LINK_STATUS_CSR_AMAP { | ||
| 434 | u8 ASPMCtl[2]; /* DWORD 0 */ | ||
| 435 | u8 rsvd0; /* DWORD 0 */ | ||
| 436 | u8 ReadCmplBndry; /* DWORD 0 */ | ||
| 437 | u8 LinkDisable; /* DWORD 0 */ | ||
| 438 | u8 RetrainLink; /* DWORD 0 */ | ||
| 439 | u8 CommonClkConfig; /* DWORD 0 */ | ||
| 440 | u8 ExtendSync; /* DWORD 0 */ | ||
| 441 | u8 rsvd1[8]; /* DWORD 0 */ | ||
| 442 | u8 LinkSpeed[4]; /* DWORD 0 */ | ||
| 443 | u8 NegLinkWidth[6]; /* DWORD 0 */ | ||
| 444 | u8 LinkTrainErr; /* DWORD 0 */ | ||
| 445 | u8 LinkTrain; /* DWORD 0 */ | ||
| 446 | u8 SlotClkConfig; /* DWORD 0 */ | ||
| 447 | u8 rsvd2[3]; /* DWORD 0 */ | ||
| 448 | } __packed; | ||
| 449 | struct PCICFG_PCIE_LINK_STATUS_CSR_AMAP { | ||
| 450 | u32 dw[1]; | ||
| 451 | }; | ||
| 452 | |||
| 453 | /* PCI Express MSI Configuration Register. */ | ||
| 454 | struct BE_PCICFG_MSI_CSR_AMAP { | ||
| 455 | u8 capid[8]; /* DWORD 0 */ | ||
| 456 | u8 nextptr[8]; /* DWORD 0 */ | ||
| 457 | u8 tablesize[11]; /* DWORD 0 */ | ||
| 458 | u8 rsvd0[3]; /* DWORD 0 */ | ||
| 459 | u8 funcmask; /* DWORD 0 */ | ||
| 460 | u8 en; /* DWORD 0 */ | ||
| 461 | } __packed; | ||
| 462 | struct PCICFG_MSI_CSR_AMAP { | ||
| 463 | u32 dw[1]; | ||
| 464 | }; | ||
| 465 | |||
| 466 | /* MSI-X Table Offset Register. */ | ||
| 467 | struct BE_PCICFG_MSIX_TABLE_CSR_AMAP { | ||
| 468 | u8 tablebir[3]; /* DWORD 0 */ | ||
| 469 | u8 offset[29]; /* DWORD 0 */ | ||
| 470 | } __packed; | ||
| 471 | struct PCICFG_MSIX_TABLE_CSR_AMAP { | ||
| 472 | u32 dw[1]; | ||
| 473 | }; | ||
| 474 | |||
| 475 | /* MSI-X PBA Offset Register. */ | ||
| 476 | struct BE_PCICFG_MSIX_PBA_CSR_AMAP { | ||
| 477 | u8 pbabir[3]; /* DWORD 0 */ | ||
| 478 | u8 offset[29]; /* DWORD 0 */ | ||
| 479 | } __packed; | ||
| 480 | struct PCICFG_MSIX_PBA_CSR_AMAP { | ||
| 481 | u32 dw[1]; | ||
| 482 | }; | ||
| 483 | |||
| 484 | /* PCI Express MSI-X Message Vector Control Register. */ | ||
| 485 | struct BE_PCICFG_MSIX_VECTOR_CONTROL_CSR_AMAP { | ||
| 486 | u8 vector_control; /* DWORD 0 */ | ||
| 487 | u8 rsvd0[31]; /* DWORD 0 */ | ||
| 488 | } __packed; | ||
| 489 | struct PCICFG_MSIX_VECTOR_CONTROL_CSR_AMAP { | ||
| 490 | u32 dw[1]; | ||
| 491 | }; | ||
| 492 | |||
| 493 | /* PCI Express MSI-X Message Data Register. */ | ||
| 494 | struct BE_PCICFG_MSIX_MSG_DATA_CSR_AMAP { | ||
| 495 | u8 data[16]; /* DWORD 0 */ | ||
| 496 | u8 rsvd0[16]; /* DWORD 0 */ | ||
| 497 | } __packed; | ||
| 498 | struct PCICFG_MSIX_MSG_DATA_CSR_AMAP { | ||
| 499 | u32 dw[1]; | ||
| 500 | }; | ||
| 501 | |||
| 502 | /* PCI Express MSI-X Message Address Register - High Part. */ | ||
| 503 | struct BE_PCICFG_MSIX_MSG_ADDR_HI_CSR_AMAP { | ||
| 504 | u8 addr[32]; /* DWORD 0 */ | ||
| 505 | } __packed; | ||
| 506 | struct PCICFG_MSIX_MSG_ADDR_HI_CSR_AMAP { | ||
| 507 | u32 dw[1]; | ||
| 508 | }; | ||
| 509 | |||
| 510 | /* PCI Express MSI-X Message Address Register - Low Part. */ | ||
| 511 | struct BE_PCICFG_MSIX_MSG_ADDR_LO_CSR_AMAP { | ||
| 512 | u8 rsvd0[2]; /* DWORD 0 */ | ||
| 513 | u8 addr[30]; /* DWORD 0 */ | ||
| 514 | } __packed; | ||
| 515 | struct PCICFG_MSIX_MSG_ADDR_LO_CSR_AMAP { | ||
| 516 | u32 dw[1]; | ||
| 517 | }; | ||
| 518 | |||
| 519 | struct BE_PCICFG_ANON_18_RSVD_AMAP { | ||
| 520 | u8 rsvd0[32]; /* DWORD 0 */ | ||
| 521 | } __packed; | ||
| 522 | struct PCICFG_ANON_18_RSVD_AMAP { | ||
| 523 | u32 dw[1]; | ||
| 524 | }; | ||
| 525 | |||
| 526 | struct BE_PCICFG_ANON_19_RSVD_AMAP { | ||
| 527 | u8 rsvd0[32]; /* DWORD 0 */ | ||
| 528 | } __packed; | ||
| 529 | struct PCICFG_ANON_19_RSVD_AMAP { | ||
| 530 | u32 dw[1]; | ||
| 531 | }; | ||
| 532 | |||
| 533 | struct BE_PCICFG_ANON_20_RSVD_AMAP { | ||
| 534 | u8 rsvd0[32]; /* DWORD 0 */ | ||
| 535 | u8 rsvd1[25][32]; /* DWORD 1 */ | ||
| 536 | } __packed; | ||
| 537 | struct PCICFG_ANON_20_RSVD_AMAP { | ||
| 538 | u32 dw[26]; | ||
| 539 | }; | ||
| 540 | |||
| 541 | struct BE_PCICFG_ANON_21_RSVD_AMAP { | ||
| 542 | u8 rsvd0[32]; /* DWORD 0 */ | ||
| 543 | u8 rsvd1[1919][32]; /* DWORD 1 */ | ||
| 544 | } __packed; | ||
| 545 | struct PCICFG_ANON_21_RSVD_AMAP { | ||
| 546 | u32 dw[1920]; | ||
| 547 | }; | ||
| 548 | |||
| 549 | struct BE_PCICFG_ANON_22_MESSAGE_AMAP { | ||
| 550 | struct BE_PCICFG_MSIX_VECTOR_CONTROL_CSR_AMAP vec_ctrl; | ||
| 551 | struct BE_PCICFG_MSIX_MSG_DATA_CSR_AMAP msg_data; | ||
| 552 | struct BE_PCICFG_MSIX_MSG_ADDR_HI_CSR_AMAP addr_hi; | ||
| 553 | struct BE_PCICFG_MSIX_MSG_ADDR_LO_CSR_AMAP addr_low; | ||
| 554 | } __packed; | ||
| 555 | struct PCICFG_ANON_22_MESSAGE_AMAP { | ||
| 556 | u32 dw[4]; | ||
| 557 | }; | ||
| 558 | |||
| 559 | struct BE_PCICFG_ANON_23_RSVD_AMAP { | ||
| 560 | u8 rsvd0[32]; /* DWORD 0 */ | ||
| 561 | u8 rsvd1[895][32]; /* DWORD 1 */ | ||
| 562 | } __packed; | ||
| 563 | struct PCICFG_ANON_23_RSVD_AMAP { | ||
| 564 | u32 dw[896]; | ||
| 565 | }; | ||
| 566 | |||
| 567 | /* These PCI Configuration Space registers are for the Storage Function of | ||
| 568 | * BladeEngine (Function 0). In the memory map of the registers below their | ||
| 569 | * table, | ||
| 570 | */ | ||
| 571 | struct BE_PCICFG0_CSRMAP_AMAP { | ||
| 572 | struct BE_PCICFG_ID_CSR_AMAP id; | ||
| 573 | u8 rsvd0[32]; /* DWORD 1 */ | ||
| 574 | u8 rsvd1[32]; /* DWORD 2 */ | ||
| 575 | u8 rsvd2[32]; /* DWORD 3 */ | ||
| 576 | struct BE_PCICFG_IOBAR_CSR_AMAP iobar; | ||
| 577 | struct BE_PCICFG_MEMBAR0_CSR_AMAP membar0; | ||
| 578 | struct BE_PCICFG_MEMBAR1_LO_CSR_AMAP membar1_lo; | ||
| 579 | struct BE_PCICFG_MEMBAR1_HI_CSR_AMAP membar1_hi; | ||
| 580 | struct BE_PCICFG_MEMBAR2_LO_CSR_AMAP membar2_lo; | ||
| 581 | struct BE_PCICFG_MEMBAR2_HI_CSR_AMAP membar2_hi; | ||
| 582 | u8 rsvd3[32]; /* DWORD 10 */ | ||
| 583 | struct BE_PCICFG_SUBSYSTEM_ID_F0_CSR_AMAP subsystem_id; | ||
| 584 | u8 rsvd4[32]; /* DWORD 12 */ | ||
| 585 | u8 rsvd5[32]; /* DWORD 13 */ | ||
| 586 | u8 rsvd6[32]; /* DWORD 14 */ | ||
| 587 | u8 rsvd7[32]; /* DWORD 15 */ | ||
| 588 | struct BE_PCICFG_SEMAPHORE_CSR_AMAP semaphore[4]; | ||
| 589 | struct BE_PCICFG_SOFT_RESET_CSR_AMAP soft_reset; | ||
| 590 | u8 rsvd8[32]; /* DWORD 21 */ | ||
| 591 | struct BE_PCICFG_SCRATCHPAD_CSR_AMAP scratchpad; | ||
| 592 | u8 rsvd9[32]; /* DWORD 23 */ | ||
| 593 | u8 rsvd10[32]; /* DWORD 24 */ | ||
| 594 | u8 rsvd11[32]; /* DWORD 25 */ | ||
| 595 | u8 rsvd12[32]; /* DWORD 26 */ | ||
| 596 | u8 rsvd13[32]; /* DWORD 27 */ | ||
| 597 | u8 rsvd14[2][32]; /* DWORD 28 */ | ||
| 598 | u8 rsvd15[32]; /* DWORD 30 */ | ||
| 599 | u8 rsvd16[32]; /* DWORD 31 */ | ||
| 600 | u8 rsvd17[8][32]; /* DWORD 32 */ | ||
| 601 | struct BE_PCICFG_UE_STATUS_LOW_CSR_AMAP ue_status_low; | ||
| 602 | struct BE_PCICFG_UE_STATUS_HI_CSR_AMAP ue_status_hi; | ||
| 603 | struct BE_PCICFG_UE_STATUS_LOW_MASK_CSR_AMAP ue_status_low_mask; | ||
| 604 | struct BE_PCICFG_UE_STATUS_HI_MASK_CSR_AMAP ue_status_hi_mask; | ||
| 605 | struct BE_PCICFG_ONLINE0_CSR_AMAP online0; | ||
| 606 | struct BE_PCICFG_ONLINE1_CSR_AMAP online1; | ||
| 607 | u8 rsvd18[32]; /* DWORD 46 */ | ||
| 608 | u8 rsvd19[32]; /* DWORD 47 */ | ||
| 609 | u8 rsvd20[32]; /* DWORD 48 */ | ||
| 610 | u8 rsvd21[32]; /* DWORD 49 */ | ||
| 611 | struct BE_PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP host_timer_int_ctrl; | ||
| 612 | u8 rsvd22[32]; /* DWORD 51 */ | ||
| 613 | struct BE_PCICFG_PCIE_CAP_CSR_AMAP pcie_cap; | ||
| 614 | struct BE_PCICFG_PCIE_DEVCAP_CSR_AMAP pcie_devcap; | ||
| 615 | struct BE_PCICFG_PCIE_CONTROL_STATUS_CSR_AMAP pcie_control_status; | ||
| 616 | struct BE_PCICFG_PCIE_LINK_CAP_CSR_AMAP pcie_link_cap; | ||
| 617 | struct BE_PCICFG_PCIE_LINK_STATUS_CSR_AMAP pcie_link_status; | ||
| 618 | struct BE_PCICFG_MSI_CSR_AMAP msi; | ||
| 619 | struct BE_PCICFG_MSIX_TABLE_CSR_AMAP msix_table_offset; | ||
| 620 | struct BE_PCICFG_MSIX_PBA_CSR_AMAP msix_pba_offset; | ||
| 621 | u8 rsvd23[32]; /* DWORD 60 */ | ||
| 622 | u8 rsvd24[32]; /* DWORD 61 */ | ||
| 623 | u8 rsvd25[32]; /* DWORD 62 */ | ||
| 624 | u8 rsvd26[32]; /* DWORD 63 */ | ||
| 625 | u8 rsvd27[32]; /* DWORD 64 */ | ||
| 626 | u8 rsvd28[32]; /* DWORD 65 */ | ||
| 627 | u8 rsvd29[32]; /* DWORD 66 */ | ||
| 628 | u8 rsvd30[32]; /* DWORD 67 */ | ||
| 629 | u8 rsvd31[32]; /* DWORD 68 */ | ||
| 630 | u8 rsvd32[32]; /* DWORD 69 */ | ||
| 631 | u8 rsvd33[32]; /* DWORD 70 */ | ||
| 632 | u8 rsvd34[32]; /* DWORD 71 */ | ||
| 633 | u8 rsvd35[32]; /* DWORD 72 */ | ||
| 634 | u8 rsvd36[32]; /* DWORD 73 */ | ||
| 635 | u8 rsvd37[32]; /* DWORD 74 */ | ||
| 636 | u8 rsvd38[32]; /* DWORD 75 */ | ||
| 637 | u8 rsvd39[32]; /* DWORD 76 */ | ||
| 638 | u8 rsvd40[32]; /* DWORD 77 */ | ||
| 639 | u8 rsvd41[32]; /* DWORD 78 */ | ||
| 640 | u8 rsvd42[32]; /* DWORD 79 */ | ||
| 641 | u8 rsvd43[32]; /* DWORD 80 */ | ||
| 642 | u8 rsvd44[32]; /* DWORD 81 */ | ||
| 643 | u8 rsvd45[32]; /* DWORD 82 */ | ||
| 644 | u8 rsvd46[32]; /* DWORD 83 */ | ||
| 645 | u8 rsvd47[32]; /* DWORD 84 */ | ||
| 646 | u8 rsvd48[32]; /* DWORD 85 */ | ||
| 647 | u8 rsvd49[32]; /* DWORD 86 */ | ||
| 648 | u8 rsvd50[32]; /* DWORD 87 */ | ||
| 649 | u8 rsvd51[32]; /* DWORD 88 */ | ||
| 650 | u8 rsvd52[32]; /* DWORD 89 */ | ||
| 651 | u8 rsvd53[32]; /* DWORD 90 */ | ||
| 652 | u8 rsvd54[32]; /* DWORD 91 */ | ||
| 653 | u8 rsvd55[32]; /* DWORD 92 */ | ||
| 654 | u8 rsvd56[832]; /* DWORD 93 */ | ||
| 655 | u8 rsvd57[32]; /* DWORD 119 */ | ||
| 656 | u8 rsvd58[32]; /* DWORD 120 */ | ||
| 657 | u8 rsvd59[32]; /* DWORD 121 */ | ||
| 658 | u8 rsvd60[32]; /* DWORD 122 */ | ||
| 659 | u8 rsvd61[32]; /* DWORD 123 */ | ||
| 660 | u8 rsvd62[32]; /* DWORD 124 */ | ||
| 661 | u8 rsvd63[32]; /* DWORD 125 */ | ||
| 662 | u8 rsvd64[32]; /* DWORD 126 */ | ||
| 663 | u8 rsvd65[32]; /* DWORD 127 */ | ||
| 664 | u8 rsvd66[61440]; /* DWORD 128 */ | ||
| 665 | struct BE_PCICFG_ANON_22_MESSAGE_AMAP message[32]; | ||
| 666 | u8 rsvd67[28672]; /* DWORD 2176 */ | ||
| 667 | u8 rsvd68[32]; /* DWORD 3072 */ | ||
| 668 | u8 rsvd69[1023][32]; /* DWORD 3073 */ | ||
| 669 | } __packed; | ||
| 670 | struct PCICFG0_CSRMAP_AMAP { | ||
| 671 | u32 dw[4096]; | ||
| 672 | }; | ||
| 673 | |||
| 674 | struct BE_PCICFG_ANON_24_RSVD_AMAP { | ||
| 675 | u8 rsvd0[32]; /* DWORD 0 */ | ||
| 676 | } __packed; | ||
| 677 | struct PCICFG_ANON_24_RSVD_AMAP { | ||
| 678 | u32 dw[1]; | ||
| 679 | }; | ||
| 680 | |||
| 681 | struct BE_PCICFG_ANON_25_RSVD_AMAP { | ||
| 682 | u8 rsvd0[32]; /* DWORD 0 */ | ||
| 683 | } __packed; | ||
| 684 | struct PCICFG_ANON_25_RSVD_AMAP { | ||
| 685 | u32 dw[1]; | ||
| 686 | }; | ||
| 687 | |||
| 688 | struct BE_PCICFG_ANON_26_RSVD_AMAP { | ||
| 689 | u8 rsvd0[32]; /* DWORD 0 */ | ||
| 690 | } __packed; | ||
| 691 | struct PCICFG_ANON_26_RSVD_AMAP { | ||
| 692 | u32 dw[1]; | ||
| 693 | }; | ||
| 694 | |||
| 695 | struct BE_PCICFG_ANON_27_RSVD_AMAP { | ||
| 696 | u8 rsvd0[32]; /* DWORD 0 */ | ||
| 697 | u8 rsvd1[32]; /* DWORD 1 */ | ||
| 698 | } __packed; | ||
| 699 | struct PCICFG_ANON_27_RSVD_AMAP { | ||
| 700 | u32 dw[2]; | ||
| 701 | }; | ||
| 702 | |||
| 703 | struct BE_PCICFG_ANON_28_RSVD_AMAP { | ||
| 704 | u8 rsvd0[32]; /* DWORD 0 */ | ||
| 705 | u8 rsvd1[3][32]; /* DWORD 1 */ | ||
| 706 | } __packed; | ||
| 707 | struct PCICFG_ANON_28_RSVD_AMAP { | ||
| 708 | u32 dw[4]; | ||
| 709 | }; | ||
| 710 | |||
| 711 | struct BE_PCICFG_ANON_29_RSVD_AMAP { | ||
| 712 | u8 rsvd0[32]; /* DWORD 0 */ | ||
| 713 | u8 rsvd1[36][32]; /* DWORD 1 */ | ||
| 714 | } __packed; | ||
| 715 | struct PCICFG_ANON_29_RSVD_AMAP { | ||
| 716 | u32 dw[37]; | ||
| 717 | }; | ||
| 718 | |||
| 719 | struct BE_PCICFG_ANON_30_RSVD_AMAP { | ||
| 720 | u8 rsvd0[32]; /* DWORD 0 */ | ||
| 721 | u8 rsvd1[1930][32]; /* DWORD 1 */ | ||
| 722 | } __packed; | ||
| 723 | struct PCICFG_ANON_30_RSVD_AMAP { | ||
| 724 | u32 dw[1931]; | ||
| 725 | }; | ||
| 726 | |||
| 727 | struct BE_PCICFG_ANON_31_MESSAGE_AMAP { | ||
| 728 | struct BE_PCICFG_MSIX_VECTOR_CONTROL_CSR_AMAP vec_ctrl; | ||
| 729 | struct BE_PCICFG_MSIX_MSG_DATA_CSR_AMAP msg_data; | ||
| 730 | struct BE_PCICFG_MSIX_MSG_ADDR_HI_CSR_AMAP addr_hi; | ||
| 731 | struct BE_PCICFG_MSIX_MSG_ADDR_LO_CSR_AMAP addr_low; | ||
| 732 | } __packed; | ||
| 733 | struct PCICFG_ANON_31_MESSAGE_AMAP { | ||
| 734 | u32 dw[4]; | ||
| 735 | }; | ||
| 736 | |||
| 737 | struct BE_PCICFG_ANON_32_RSVD_AMAP { | ||
| 738 | u8 rsvd0[32]; /* DWORD 0 */ | ||
| 739 | u8 rsvd1[895][32]; /* DWORD 1 */ | ||
| 740 | } __packed; | ||
| 741 | struct PCICFG_ANON_32_RSVD_AMAP { | ||
| 742 | u32 dw[896]; | ||
| 743 | }; | ||
| 744 | |||
| 745 | /* This PCI configuration space register map is for the Networking Function of | ||
| 746 | * BladeEngine (Function 1). | ||
| 747 | */ | ||
| 748 | struct BE_PCICFG1_CSRMAP_AMAP { | ||
| 749 | struct BE_PCICFG_ID_CSR_AMAP id; | ||
| 750 | u8 rsvd0[32]; /* DWORD 1 */ | ||
| 751 | u8 rsvd1[32]; /* DWORD 2 */ | ||
| 752 | u8 rsvd2[32]; /* DWORD 3 */ | ||
| 753 | struct BE_PCICFG_IOBAR_CSR_AMAP iobar; | ||
| 754 | struct BE_PCICFG_MEMBAR0_CSR_AMAP membar0; | ||
| 755 | struct BE_PCICFG_MEMBAR1_LO_CSR_AMAP membar1_lo; | ||
| 756 | struct BE_PCICFG_MEMBAR1_HI_CSR_AMAP membar1_hi; | ||
| 757 | struct BE_PCICFG_MEMBAR2_LO_CSR_AMAP membar2_lo; | ||
| 758 | struct BE_PCICFG_MEMBAR2_HI_CSR_AMAP membar2_hi; | ||
| 759 | u8 rsvd3[32]; /* DWORD 10 */ | ||
| 760 | struct BE_PCICFG_SUBSYSTEM_ID_F1_CSR_AMAP subsystem_id; | ||
| 761 | u8 rsvd4[32]; /* DWORD 12 */ | ||
| 762 | u8 rsvd5[32]; /* DWORD 13 */ | ||
| 763 | u8 rsvd6[32]; /* DWORD 14 */ | ||
| 764 | u8 rsvd7[32]; /* DWORD 15 */ | ||
| 765 | struct BE_PCICFG_SEMAPHORE_CSR_AMAP semaphore[4]; | ||
| 766 | struct BE_PCICFG_SOFT_RESET_CSR_AMAP soft_reset; | ||
| 767 | u8 rsvd8[32]; /* DWORD 21 */ | ||
| 768 | struct BE_PCICFG_SCRATCHPAD_CSR_AMAP scratchpad; | ||
| 769 | u8 rsvd9[32]; /* DWORD 23 */ | ||
| 770 | u8 rsvd10[32]; /* DWORD 24 */ | ||
| 771 | u8 rsvd11[32]; /* DWORD 25 */ | ||
| 772 | u8 rsvd12[32]; /* DWORD 26 */ | ||
| 773 | u8 rsvd13[32]; /* DWORD 27 */ | ||
| 774 | u8 rsvd14[2][32]; /* DWORD 28 */ | ||
| 775 | u8 rsvd15[32]; /* DWORD 30 */ | ||
| 776 | u8 rsvd16[32]; /* DWORD 31 */ | ||
| 777 | u8 rsvd17[8][32]; /* DWORD 32 */ | ||
| 778 | struct BE_PCICFG_UE_STATUS_LOW_CSR_AMAP ue_status_low; | ||
| 779 | struct BE_PCICFG_UE_STATUS_HI_CSR_AMAP ue_status_hi; | ||
| 780 | struct BE_PCICFG_UE_STATUS_LOW_MASK_CSR_AMAP ue_status_low_mask; | ||
| 781 | struct BE_PCICFG_UE_STATUS_HI_MASK_CSR_AMAP ue_status_hi_mask; | ||
| 782 | struct BE_PCICFG_ONLINE0_CSR_AMAP online0; | ||
| 783 | struct BE_PCICFG_ONLINE1_CSR_AMAP online1; | ||
| 784 | u8 rsvd18[32]; /* DWORD 46 */ | ||
| 785 | u8 rsvd19[32]; /* DWORD 47 */ | ||
| 786 | u8 rsvd20[32]; /* DWORD 48 */ | ||
| 787 | u8 rsvd21[32]; /* DWORD 49 */ | ||
| 788 | struct BE_PCICFG_HOST_TIMER_INT_CTRL_CSR_AMAP host_timer_int_ctrl; | ||
| 789 | u8 rsvd22[32]; /* DWORD 51 */ | ||
| 790 | struct BE_PCICFG_PCIE_CAP_CSR_AMAP pcie_cap; | ||
| 791 | struct BE_PCICFG_PCIE_DEVCAP_CSR_AMAP pcie_devcap; | ||
| 792 | struct BE_PCICFG_PCIE_CONTROL_STATUS_CSR_AMAP pcie_control_status; | ||
| 793 | struct BE_PCICFG_PCIE_LINK_CAP_CSR_AMAP pcie_link_cap; | ||
| 794 | struct BE_PCICFG_PCIE_LINK_STATUS_CSR_AMAP pcie_link_status; | ||
| 795 | struct BE_PCICFG_MSI_CSR_AMAP msi; | ||
| 796 | struct BE_PCICFG_MSIX_TABLE_CSR_AMAP msix_table_offset; | ||
| 797 | struct BE_PCICFG_MSIX_PBA_CSR_AMAP msix_pba_offset; | ||
| 798 | u8 rsvd23[64]; /* DWORD 60 */ | ||
| 799 | u8 rsvd24[32]; /* DWORD 62 */ | ||
| 800 | u8 rsvd25[32]; /* DWORD 63 */ | ||
| 801 | u8 rsvd26[32]; /* DWORD 64 */ | ||
| 802 | u8 rsvd27[32]; /* DWORD 65 */ | ||
| 803 | u8 rsvd28[32]; /* DWORD 66 */ | ||
| 804 | u8 rsvd29[32]; /* DWORD 67 */ | ||
| 805 | u8 rsvd30[32]; /* DWORD 68 */ | ||
| 806 | u8 rsvd31[32]; /* DWORD 69 */ | ||
| 807 | u8 rsvd32[32]; /* DWORD 70 */ | ||
| 808 | u8 rsvd33[32]; /* DWORD 71 */ | ||
| 809 | u8 rsvd34[32]; /* DWORD 72 */ | ||
| 810 | u8 rsvd35[32]; /* DWORD 73 */ | ||
| 811 | u8 rsvd36[32]; /* DWORD 74 */ | ||
| 812 | u8 rsvd37[128]; /* DWORD 75 */ | ||
| 813 | u8 rsvd38[32]; /* DWORD 79 */ | ||
| 814 | u8 rsvd39[1184]; /* DWORD 80 */ | ||
| 815 | u8 rsvd40[61792]; /* DWORD 117 */ | ||
| 816 | struct BE_PCICFG_ANON_31_MESSAGE_AMAP message[32]; | ||
| 817 | u8 rsvd41[28672]; /* DWORD 2176 */ | ||
| 818 | u8 rsvd42[32]; /* DWORD 3072 */ | ||
| 819 | u8 rsvd43[1023][32]; /* DWORD 3073 */ | ||
| 820 | } __packed; | ||
| 821 | struct PCICFG1_CSRMAP_AMAP { | ||
| 822 | u32 dw[4096]; | ||
| 823 | }; | ||
| 824 | |||
| 825 | #endif /* __pcicfg_amap_h__ */ | ||
diff --git a/drivers/staging/benet/post_codes.h b/drivers/staging/benet/post_codes.h deleted file mode 100644 index 6d1621f5f5fb..000000000000 --- a/drivers/staging/benet/post_codes.h +++ /dev/null | |||
| @@ -1,111 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __post_codes_amap_h__ | ||
| 21 | #define __post_codes_amap_h__ | ||
| 22 | |||
| 23 | /* --- MGMT_HBA_POST_STAGE_ENUM --- */ | ||
| 24 | #define POST_STAGE_POWER_ON_RESET (0) /* State after a cold or warm boot. */ | ||
| 25 | #define POST_STAGE_AWAITING_HOST_RDY (1) /* ARM boot code awaiting a | ||
| 26 | go-ahed from the host. */ | ||
| 27 | #define POST_STAGE_HOST_RDY (2) /* Host has given go-ahed to ARM. */ | ||
| 28 | #define POST_STAGE_BE_RESET (3) /* Host wants to reset chip, this is a chip | ||
| 29 | workaround */ | ||
| 30 | #define POST_STAGE_SEEPROM_CS_START (256) /* SEEPROM checksum | ||
| 31 | test start. */ | ||
| 32 | #define POST_STAGE_SEEPROM_CS_DONE (257) /* SEEPROM checksum test | ||
| 33 | done. */ | ||
| 34 | #define POST_STAGE_DDR_CONFIG_START (512) /* DDR configuration start. */ | ||
| 35 | #define POST_STAGE_DDR_CONFIG_DONE (513) /* DDR configuration done. */ | ||
| 36 | #define POST_STAGE_DDR_CALIBRATE_START (768) /* DDR calibration start. */ | ||
| 37 | #define POST_STAGE_DDR_CALIBRATE_DONE (769) /* DDR calibration done. */ | ||
| 38 | #define POST_STAGE_DDR_TEST_START (1024) /* DDR memory test start. */ | ||
| 39 | #define POST_STAGE_DDR_TEST_DONE (1025) /* DDR memory test done. */ | ||
| 40 | #define POST_STAGE_REDBOOT_INIT_START (1536) /* Redboot starts execution. */ | ||
| 41 | #define POST_STAGE_REDBOOT_INIT_DONE (1537) /* Redboot done execution. */ | ||
| 42 | #define POST_STAGE_FW_IMAGE_LOAD_START (1792) /* Firmware image load to | ||
| 43 | DDR start. */ | ||
| 44 | #define POST_STAGE_FW_IMAGE_LOAD_DONE (1793) /* Firmware image load | ||
| 45 | to DDR done. */ | ||
| 46 | #define POST_STAGE_ARMFW_START (2048) /* ARMfw runtime code | ||
| 47 | starts execution. */ | ||
| 48 | #define POST_STAGE_DHCP_QUERY_START (2304) /* DHCP server query start. */ | ||
| 49 | #define POST_STAGE_DHCP_QUERY_DONE (2305) /* DHCP server query done. */ | ||
| 50 | #define POST_STAGE_BOOT_TARGET_DISCOVERY_START (2560) /* Boot Target | ||
| 51 | Discovery Start. */ | ||
| 52 | #define POST_STAGE_BOOT_TARGET_DISCOVERY_DONE (2561) /* Boot Target | ||
| 53 | Discovery Done. */ | ||
| 54 | #define POST_STAGE_RC_OPTION_SET (2816) /* Remote configuration | ||
| 55 | option is set in SEEPROM */ | ||
| 56 | #define POST_STAGE_SWITCH_LINK (2817) /* Wait for link up on switch */ | ||
| 57 | #define POST_STAGE_SEND_ICDS_MESSAGE (2818) /* Send the ICDS message | ||
| 58 | to switch */ | ||
| 59 | #define POST_STAGE_PERFROM_TFTP (2819) /* Download xml using TFTP */ | ||
| 60 | #define POST_STAGE_PARSE_XML (2820) /* Parse XML file */ | ||
| 61 | #define POST_STAGE_DOWNLOAD_IMAGE (2821) /* Download IMAGE from | ||
| 62 | TFTP server */ | ||
| 63 | #define POST_STAGE_FLASH_IMAGE (2822) /* Flash the IMAGE */ | ||
| 64 | #define POST_STAGE_RC_DONE (2823) /* Remote configuration | ||
| 65 | complete */ | ||
| 66 | #define POST_STAGE_REBOOT_SYSTEM (2824) /* Upgrade IMAGE done, | ||
| 67 | reboot required */ | ||
| 68 | #define POST_STAGE_MAC_ADDRESS (3072) /* MAC Address Check */ | ||
| 69 | #define POST_STAGE_ARMFW_READY (49152) /* ARMfw is done with POST | ||
| 70 | and ready. */ | ||
| 71 | #define POST_STAGE_ARMFW_UE (61440) /* ARMfw has asserted an | ||
| 72 | unrecoverable error. The | ||
| 73 | lower 3 hex digits of the | ||
| 74 | stage code identify the | ||
| 75 | unique error code. | ||
| 76 | */ | ||
| 77 | |||
| 78 | /* This structure defines the format of the MPU semaphore | ||
| 79 | * register when used for POST. | ||
| 80 | */ | ||
| 81 | struct BE_MGMT_HBA_POST_STATUS_STRUCT_AMAP { | ||
| 82 | u8 stage[16]; /* DWORD 0 */ | ||
| 83 | u8 rsvd0[10]; /* DWORD 0 */ | ||
| 84 | u8 iscsi_driver_loaded; /* DWORD 0 */ | ||
| 85 | u8 option_rom_installed; /* DWORD 0 */ | ||
| 86 | u8 iscsi_ip_conflict; /* DWORD 0 */ | ||
| 87 | u8 iscsi_no_ip; /* DWORD 0 */ | ||
| 88 | u8 backup_fw; /* DWORD 0 */ | ||
| 89 | u8 error; /* DWORD 0 */ | ||
| 90 | } __packed; | ||
| 91 | struct MGMT_HBA_POST_STATUS_STRUCT_AMAP { | ||
| 92 | u32 dw[1]; | ||
| 93 | }; | ||
| 94 | |||
| 95 | /* --- MGMT_HBA_POST_DUMMY_BITS_ENUM --- */ | ||
| 96 | #define POST_BIT_ISCSI_LOADED (26) | ||
| 97 | #define POST_BIT_OPTROM_INST (27) | ||
| 98 | #define POST_BIT_BAD_IP_ADDR (28) | ||
| 99 | #define POST_BIT_NO_IP_ADDR (29) | ||
| 100 | #define POST_BIT_BACKUP_FW (30) | ||
| 101 | #define POST_BIT_ERROR (31) | ||
| 102 | |||
| 103 | /* --- MGMT_HBA_POST_DUMMY_VALUES_ENUM --- */ | ||
| 104 | #define POST_ISCSI_DRIVER_LOADED (67108864) | ||
| 105 | #define POST_OPTROM_INSTALLED (134217728) | ||
| 106 | #define POST_ISCSI_IP_ADDRESS_CONFLICT (268435456) | ||
| 107 | #define POST_ISCSI_NO_IP_ADDRESS (536870912) | ||
| 108 | #define POST_BACKUP_FW_LOADED (1073741824) | ||
| 109 | #define POST_FATAL_ERROR (2147483648) | ||
| 110 | |||
| 111 | #endif /* __post_codes_amap_h__ */ | ||
diff --git a/drivers/staging/benet/regmap.h b/drivers/staging/benet/regmap.h deleted file mode 100644 index e816ba210e83..000000000000 --- a/drivers/staging/benet/regmap.h +++ /dev/null | |||
| @@ -1,68 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Copyright (C) 2005 - 2008 ServerEngines | ||
| 3 | * All rights reserved. | ||
| 4 | * | ||
| 5 | * This program is free software; you can redistribute it and/or | ||
| 6 | * modify it under the terms of the GNU General Public License version 2 | ||
| 7 | * as published by the Free Software Foundation. The full GNU General | ||
| 8 | * Public License is included in this distribution in the file called COPYING. | ||
| 9 | * | ||
| 10 | * Contact Information: | ||
| 11 | * linux-drivers@serverengines.com | ||
| 12 | * | ||
| 13 | * ServerEngines | ||
| 14 | * 209 N. Fair Oaks Ave | ||
| 15 | * Sunnyvale, CA 94085 | ||
| 16 | */ | ||
| 17 | /* | ||
| 18 | * Autogenerated by srcgen version: 0127 | ||
| 19 | */ | ||
| 20 | #ifndef __regmap_amap_h__ | ||
| 21 | #define __regmap_amap_h__ | ||
| 22 | #include "pcicfg.h" | ||
| 23 | #include "ep.h" | ||
| 24 | #include "cev.h" | ||
| 25 | #include "mpu.h" | ||
| 26 | #include "doorbells.h" | ||
| 27 | |||
| 28 | /* | ||
| 29 | * This is the control and status register map for BladeEngine, showing | ||
| 30 | * the relative size and offset of each sub-module. The CSR registers | ||
| 31 | * are identical for the network and storage PCI functions. The | ||
| 32 | * CSR map is shown below, followed by details of each block, | ||
| 33 | * in sub-sections. The sub-sections begin with a description | ||
| 34 | * of CSRs that are instantiated in multiple blocks. | ||
| 35 | */ | ||
| 36 | struct BE_BLADE_ENGINE_CSRMAP_AMAP { | ||
| 37 | struct BE_MPU_CSRMAP_AMAP mpu; | ||
| 38 | u8 rsvd0[8192]; /* DWORD 256 */ | ||
| 39 | u8 rsvd1[8192]; /* DWORD 512 */ | ||
| 40 | struct BE_CEV_CSRMAP_AMAP cev; | ||
| 41 | u8 rsvd2[8192]; /* DWORD 1024 */ | ||
| 42 | u8 rsvd3[8192]; /* DWORD 1280 */ | ||
| 43 | u8 rsvd4[8192]; /* DWORD 1536 */ | ||
| 44 | u8 rsvd5[8192]; /* DWORD 1792 */ | ||
| 45 | u8 rsvd6[8192]; /* DWORD 2048 */ | ||
| 46 | u8 rsvd7[8192]; /* DWORD 2304 */ | ||
| 47 | u8 rsvd8[8192]; /* DWORD 2560 */ | ||
| 48 | u8 rsvd9[8192]; /* DWORD 2816 */ | ||
| 49 | u8 rsvd10[8192]; /* DWORD 3072 */ | ||
| 50 | u8 rsvd11[8192]; /* DWORD 3328 */ | ||
| 51 | u8 rsvd12[8192]; /* DWORD 3584 */ | ||
| 52 | u8 rsvd13[8192]; /* DWORD 3840 */ | ||
| 53 | u8 rsvd14[8192]; /* DWORD 4096 */ | ||
| 54 | u8 rsvd15[8192]; /* DWORD 4352 */ | ||
| 55 | u8 rsvd16[8192]; /* DWORD 4608 */ | ||
| 56 | u8 rsvd17[8192]; /* DWORD 4864 */ | ||
| 57 | u8 rsvd18[8192]; /* DWORD 5120 */ | ||
| 58 | u8 rsvd19[8192]; /* DWORD 5376 */ | ||
| 59 | u8 rsvd20[8192]; /* DWORD 5632 */ | ||
| 60 | u8 rsvd21[8192]; /* DWORD 5888 */ | ||
| 61 | u8 rsvd22[8192]; /* DWORD 6144 */ | ||
| 62 | u8 rsvd23[17152][32]; /* DWORD 6400 */ | ||
| 63 | } __packed; | ||
| 64 | struct BLADE_ENGINE_CSRMAP_AMAP { | ||
| 65 | u32 dw[23552]; | ||
| 66 | }; | ||
| 67 | |||
| 68 | #endif /* __regmap_amap_h__ */ | ||
diff --git a/drivers/usb/atm/cxacru.c b/drivers/usb/atm/cxacru.c index 5ed4ae07bac1..6789089e2461 100644 --- a/drivers/usb/atm/cxacru.c +++ b/drivers/usb/atm/cxacru.c | |||
| @@ -485,7 +485,7 @@ static int cxacru_cm(struct cxacru_data *instance, enum cxacru_cm_request cm, | |||
| 485 | usb_err(instance->usbatm, "requested transfer size too large (%d, %d)\n", | 485 | usb_err(instance->usbatm, "requested transfer size too large (%d, %d)\n", |
| 486 | wbuflen, rbuflen); | 486 | wbuflen, rbuflen); |
| 487 | ret = -ENOMEM; | 487 | ret = -ENOMEM; |
| 488 | goto fail; | 488 | goto err; |
| 489 | } | 489 | } |
| 490 | 490 | ||
| 491 | mutex_lock(&instance->cm_serialize); | 491 | mutex_lock(&instance->cm_serialize); |
| @@ -565,6 +565,7 @@ static int cxacru_cm(struct cxacru_data *instance, enum cxacru_cm_request cm, | |||
| 565 | dbg("cm %#x", cm); | 565 | dbg("cm %#x", cm); |
| 566 | fail: | 566 | fail: |
| 567 | mutex_unlock(&instance->cm_serialize); | 567 | mutex_unlock(&instance->cm_serialize); |
| 568 | err: | ||
| 568 | return ret; | 569 | return ret; |
| 569 | } | 570 | } |
| 570 | 571 | ||
diff --git a/drivers/usb/class/usbtmc.c b/drivers/usb/class/usbtmc.c index 0f5c05f6f9df..c40a9b284cc9 100644 --- a/drivers/usb/class/usbtmc.c +++ b/drivers/usb/class/usbtmc.c | |||
| @@ -50,6 +50,7 @@ | |||
| 50 | 50 | ||
| 51 | static struct usb_device_id usbtmc_devices[] = { | 51 | static struct usb_device_id usbtmc_devices[] = { |
| 52 | { USB_INTERFACE_INFO(USB_CLASS_APP_SPEC, 3, 0), }, | 52 | { USB_INTERFACE_INFO(USB_CLASS_APP_SPEC, 3, 0), }, |
| 53 | { USB_INTERFACE_INFO(USB_CLASS_APP_SPEC, 3, 1), }, | ||
| 53 | { 0, } /* terminating entry */ | 54 | { 0, } /* terminating entry */ |
| 54 | }; | 55 | }; |
| 55 | MODULE_DEVICE_TABLE(usb, usbtmc_devices); | 56 | MODULE_DEVICE_TABLE(usb, usbtmc_devices); |
| @@ -106,12 +107,13 @@ static int usbtmc_open(struct inode *inode, struct file *filp) | |||
| 106 | { | 107 | { |
| 107 | struct usb_interface *intf; | 108 | struct usb_interface *intf; |
| 108 | struct usbtmc_device_data *data; | 109 | struct usbtmc_device_data *data; |
| 109 | int retval = -ENODEV; | 110 | int retval = 0; |
| 110 | 111 | ||
| 111 | intf = usb_find_interface(&usbtmc_driver, iminor(inode)); | 112 | intf = usb_find_interface(&usbtmc_driver, iminor(inode)); |
| 112 | if (!intf) { | 113 | if (!intf) { |
| 113 | printk(KERN_ERR KBUILD_MODNAME | 114 | printk(KERN_ERR KBUILD_MODNAME |
| 114 | ": can not find device for minor %d", iminor(inode)); | 115 | ": can not find device for minor %d", iminor(inode)); |
| 116 | retval = -ENODEV; | ||
| 115 | goto exit; | 117 | goto exit; |
| 116 | } | 118 | } |
| 117 | 119 | ||
diff --git a/drivers/usb/core/devio.c b/drivers/usb/core/devio.c index 7513bb083c15..6585f527e381 100644 --- a/drivers/usb/core/devio.c +++ b/drivers/usb/core/devio.c | |||
| @@ -359,11 +359,6 @@ static void destroy_async(struct dev_state *ps, struct list_head *list) | |||
| 359 | spin_lock_irqsave(&ps->lock, flags); | 359 | spin_lock_irqsave(&ps->lock, flags); |
| 360 | } | 360 | } |
| 361 | spin_unlock_irqrestore(&ps->lock, flags); | 361 | spin_unlock_irqrestore(&ps->lock, flags); |
| 362 | as = async_getcompleted(ps); | ||
| 363 | while (as) { | ||
| 364 | free_async(as); | ||
| 365 | as = async_getcompleted(ps); | ||
| 366 | } | ||
| 367 | } | 362 | } |
| 368 | 363 | ||
| 369 | static void destroy_async_on_interface(struct dev_state *ps, | 364 | static void destroy_async_on_interface(struct dev_state *ps, |
| @@ -643,6 +638,7 @@ static int usbdev_release(struct inode *inode, struct file *file) | |||
| 643 | struct dev_state *ps = file->private_data; | 638 | struct dev_state *ps = file->private_data; |
| 644 | struct usb_device *dev = ps->dev; | 639 | struct usb_device *dev = ps->dev; |
| 645 | unsigned int ifnum; | 640 | unsigned int ifnum; |
| 641 | struct async *as; | ||
| 646 | 642 | ||
| 647 | usb_lock_device(dev); | 643 | usb_lock_device(dev); |
| 648 | 644 | ||
| @@ -661,6 +657,12 @@ static int usbdev_release(struct inode *inode, struct file *file) | |||
| 661 | usb_unlock_device(dev); | 657 | usb_unlock_device(dev); |
| 662 | usb_put_dev(dev); | 658 | usb_put_dev(dev); |
| 663 | put_pid(ps->disc_pid); | 659 | put_pid(ps->disc_pid); |
| 660 | |||
| 661 | as = async_getcompleted(ps); | ||
| 662 | while (as) { | ||
| 663 | free_async(as); | ||
| 664 | as = async_getcompleted(ps); | ||
| 665 | } | ||
| 664 | kfree(ps); | 666 | kfree(ps); |
| 665 | return 0; | 667 | return 0; |
| 666 | } | 668 | } |
diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c index 3712b925b315..ecc9b66c03cd 100644 --- a/drivers/usb/host/ehci-q.c +++ b/drivers/usb/host/ehci-q.c | |||
| @@ -1095,7 +1095,8 @@ static void start_unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) | |||
| 1095 | prev->qh_next = qh->qh_next; | 1095 | prev->qh_next = qh->qh_next; |
| 1096 | wmb (); | 1096 | wmb (); |
| 1097 | 1097 | ||
| 1098 | if (unlikely (ehci_to_hcd(ehci)->state == HC_STATE_HALT)) { | 1098 | /* If the controller isn't running, we don't have to wait for it */ |
| 1099 | if (unlikely(!HC_IS_RUNNING(ehci_to_hcd(ehci)->state))) { | ||
| 1099 | /* if (unlikely (qh->reclaim != 0)) | 1100 | /* if (unlikely (qh->reclaim != 0)) |
| 1100 | * this will recurse, probably not much | 1101 | * this will recurse, probably not much |
| 1101 | */ | 1102 | */ |
diff --git a/drivers/usb/host/ehci-sched.c b/drivers/usb/host/ehci-sched.c index 07bcb931021b..1d0b49e3f192 100644 --- a/drivers/usb/host/ehci-sched.c +++ b/drivers/usb/host/ehci-sched.c | |||
| @@ -1536,7 +1536,7 @@ itd_link_urb ( | |||
| 1536 | struct ehci_itd, itd_list); | 1536 | struct ehci_itd, itd_list); |
| 1537 | list_move_tail (&itd->itd_list, &stream->td_list); | 1537 | list_move_tail (&itd->itd_list, &stream->td_list); |
| 1538 | itd->stream = iso_stream_get (stream); | 1538 | itd->stream = iso_stream_get (stream); |
| 1539 | itd->urb = usb_get_urb (urb); | 1539 | itd->urb = urb; |
| 1540 | itd_init (ehci, stream, itd); | 1540 | itd_init (ehci, stream, itd); |
| 1541 | } | 1541 | } |
| 1542 | 1542 | ||
| @@ -1645,7 +1645,7 @@ itd_complete ( | |||
| 1645 | (void) disable_periodic(ehci); | 1645 | (void) disable_periodic(ehci); |
| 1646 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; | 1646 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; |
| 1647 | 1647 | ||
| 1648 | if (unlikely (list_empty (&stream->td_list))) { | 1648 | if (unlikely(list_is_singular(&stream->td_list))) { |
| 1649 | ehci_to_hcd(ehci)->self.bandwidth_allocated | 1649 | ehci_to_hcd(ehci)->self.bandwidth_allocated |
| 1650 | -= stream->bandwidth; | 1650 | -= stream->bandwidth; |
| 1651 | ehci_vdbg (ehci, | 1651 | ehci_vdbg (ehci, |
| @@ -1656,7 +1656,6 @@ itd_complete ( | |||
| 1656 | iso_stream_put (ehci, stream); | 1656 | iso_stream_put (ehci, stream); |
| 1657 | 1657 | ||
| 1658 | done: | 1658 | done: |
| 1659 | usb_put_urb(urb); | ||
| 1660 | itd->urb = NULL; | 1659 | itd->urb = NULL; |
| 1661 | if (ehci->clock_frame != itd->frame || itd->index[7] != -1) { | 1660 | if (ehci->clock_frame != itd->frame || itd->index[7] != -1) { |
| 1662 | /* OK to recycle this ITD now. */ | 1661 | /* OK to recycle this ITD now. */ |
| @@ -1949,7 +1948,7 @@ sitd_link_urb ( | |||
| 1949 | struct ehci_sitd, sitd_list); | 1948 | struct ehci_sitd, sitd_list); |
| 1950 | list_move_tail (&sitd->sitd_list, &stream->td_list); | 1949 | list_move_tail (&sitd->sitd_list, &stream->td_list); |
| 1951 | sitd->stream = iso_stream_get (stream); | 1950 | sitd->stream = iso_stream_get (stream); |
| 1952 | sitd->urb = usb_get_urb (urb); | 1951 | sitd->urb = urb; |
| 1953 | 1952 | ||
| 1954 | sitd_patch(ehci, stream, sitd, sched, packet); | 1953 | sitd_patch(ehci, stream, sitd, sched, packet); |
| 1955 | sitd_link (ehci, (next_uframe >> 3) % ehci->periodic_size, | 1954 | sitd_link (ehci, (next_uframe >> 3) % ehci->periodic_size, |
| @@ -2034,7 +2033,7 @@ sitd_complete ( | |||
| 2034 | (void) disable_periodic(ehci); | 2033 | (void) disable_periodic(ehci); |
| 2035 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; | 2034 | ehci_to_hcd(ehci)->self.bandwidth_isoc_reqs--; |
| 2036 | 2035 | ||
| 2037 | if (list_empty (&stream->td_list)) { | 2036 | if (list_is_singular(&stream->td_list)) { |
| 2038 | ehci_to_hcd(ehci)->self.bandwidth_allocated | 2037 | ehci_to_hcd(ehci)->self.bandwidth_allocated |
| 2039 | -= stream->bandwidth; | 2038 | -= stream->bandwidth; |
| 2040 | ehci_vdbg (ehci, | 2039 | ehci_vdbg (ehci, |
| @@ -2045,7 +2044,6 @@ sitd_complete ( | |||
| 2045 | iso_stream_put (ehci, stream); | 2044 | iso_stream_put (ehci, stream); |
| 2046 | /* OK to recycle this SITD now that its completion callback ran. */ | 2045 | /* OK to recycle this SITD now that its completion callback ran. */ |
| 2047 | done: | 2046 | done: |
| 2048 | usb_put_urb(urb); | ||
| 2049 | sitd->urb = NULL; | 2047 | sitd->urb = NULL; |
| 2050 | sitd->stream = NULL; | 2048 | sitd->stream = NULL; |
| 2051 | list_move(&sitd->sitd_list, &stream->free_list); | 2049 | list_move(&sitd->sitd_list, &stream->free_list); |
diff --git a/drivers/usb/host/ohci-ep93xx.c b/drivers/usb/host/ohci-ep93xx.c index fb3055f084b5..7cf74f8c2db1 100644 --- a/drivers/usb/host/ohci-ep93xx.c +++ b/drivers/usb/host/ohci-ep93xx.c | |||
| @@ -28,8 +28,6 @@ | |||
| 28 | #include <linux/signal.h> | 28 | #include <linux/signal.h> |
| 29 | #include <linux/platform_device.h> | 29 | #include <linux/platform_device.h> |
| 30 | 30 | ||
| 31 | #include <mach/hardware.h> | ||
| 32 | |||
| 33 | static struct clk *usb_host_clock; | 31 | static struct clk *usb_host_clock; |
| 34 | 32 | ||
| 35 | static void ep93xx_start_hc(struct device *dev) | 33 | static void ep93xx_start_hc(struct device *dev) |
diff --git a/drivers/usb/image/mdc800.c b/drivers/usb/image/mdc800.c index 878c77ca086e..972f20b3406c 100644 --- a/drivers/usb/image/mdc800.c +++ b/drivers/usb/image/mdc800.c | |||
| @@ -499,6 +499,7 @@ static int mdc800_usb_probe (struct usb_interface *intf, | |||
| 499 | retval = usb_register_dev(intf, &mdc800_class); | 499 | retval = usb_register_dev(intf, &mdc800_class); |
| 500 | if (retval) { | 500 | if (retval) { |
| 501 | dev_err(&intf->dev, "Not able to get a minor for this device.\n"); | 501 | dev_err(&intf->dev, "Not able to get a minor for this device.\n"); |
| 502 | mutex_unlock(&mdc800->io_lock); | ||
| 502 | return -ENODEV; | 503 | return -ENODEV; |
| 503 | } | 504 | } |
| 504 | 505 | ||
diff --git a/drivers/usb/misc/adutux.c b/drivers/usb/misc/adutux.c index 7b6922e08ed1..203526542013 100644 --- a/drivers/usb/misc/adutux.c +++ b/drivers/usb/misc/adutux.c | |||
| @@ -376,7 +376,7 @@ static int adu_release(struct inode *inode, struct file *file) | |||
| 376 | if (dev->open_count <= 0) { | 376 | if (dev->open_count <= 0) { |
| 377 | dbg(1," %s : device not opened", __func__); | 377 | dbg(1," %s : device not opened", __func__); |
| 378 | retval = -ENODEV; | 378 | retval = -ENODEV; |
| 379 | goto exit; | 379 | goto unlock; |
| 380 | } | 380 | } |
| 381 | 381 | ||
| 382 | adu_release_internal(dev); | 382 | adu_release_internal(dev); |
| @@ -385,9 +385,9 @@ static int adu_release(struct inode *inode, struct file *file) | |||
| 385 | if (!dev->open_count) /* ... and we're the last user */ | 385 | if (!dev->open_count) /* ... and we're the last user */ |
| 386 | adu_delete(dev); | 386 | adu_delete(dev); |
| 387 | } | 387 | } |
| 388 | 388 | unlock: | |
| 389 | exit: | ||
| 390 | mutex_unlock(&adutux_mutex); | 389 | mutex_unlock(&adutux_mutex); |
| 390 | exit: | ||
| 391 | dbg(2," %s : leave, return value %d", __func__, retval); | 391 | dbg(2," %s : leave, return value %d", __func__, retval); |
| 392 | return retval; | 392 | return retval; |
| 393 | } | 393 | } |
diff --git a/drivers/usb/misc/vstusb.c b/drivers/usb/misc/vstusb.c index 63dff9ba73c5..f26ea8dc1577 100644 --- a/drivers/usb/misc/vstusb.c +++ b/drivers/usb/misc/vstusb.c | |||
| @@ -401,6 +401,7 @@ static ssize_t vstusb_write(struct file *file, const char __user *buffer, | |||
| 401 | } | 401 | } |
| 402 | 402 | ||
| 403 | if (copy_from_user(buf, buffer, count)) { | 403 | if (copy_from_user(buf, buffer, count)) { |
| 404 | mutex_unlock(&vstdev->lock); | ||
| 404 | dev_err(&dev->dev, "%s: can't copy_from_user\n", __func__); | 405 | dev_err(&dev->dev, "%s: can't copy_from_user\n", __func__); |
| 405 | retval = -EFAULT; | 406 | retval = -EFAULT; |
| 406 | goto exit; | 407 | goto exit; |
diff --git a/drivers/usb/serial/cp2101.c b/drivers/usb/serial/cp2101.c index 027f4b7dde86..9b4082b58c5b 100644 --- a/drivers/usb/serial/cp2101.c +++ b/drivers/usb/serial/cp2101.c | |||
| @@ -79,6 +79,7 @@ static struct usb_device_id id_table [] = { | |||
| 79 | { USB_DEVICE(0x10C4, 0x814A) }, /* West Mountain Radio RIGblaster P&P */ | 79 | { USB_DEVICE(0x10C4, 0x814A) }, /* West Mountain Radio RIGblaster P&P */ |
| 80 | { USB_DEVICE(0x10C4, 0x814B) }, /* West Mountain Radio RIGtalk */ | 80 | { USB_DEVICE(0x10C4, 0x814B) }, /* West Mountain Radio RIGtalk */ |
| 81 | { USB_DEVICE(0x10C4, 0x815E) }, /* Helicomm IP-Link 1220-DVM */ | 81 | { USB_DEVICE(0x10C4, 0x815E) }, /* Helicomm IP-Link 1220-DVM */ |
| 82 | { USB_DEVICE(0x10C4, 0x819F) }, /* MJS USB Toslink Switcher */ | ||
| 82 | { USB_DEVICE(0x10C4, 0x81A6) }, /* ThinkOptics WavIt */ | 83 | { USB_DEVICE(0x10C4, 0x81A6) }, /* ThinkOptics WavIt */ |
| 83 | { USB_DEVICE(0x10C4, 0x81AC) }, /* MSD Dash Hawk */ | 84 | { USB_DEVICE(0x10C4, 0x81AC) }, /* MSD Dash Hawk */ |
| 84 | { USB_DEVICE(0x10C4, 0x81C8) }, /* Lipowsky Industrie Elektronik GmbH, Baby-JTAG */ | 85 | { USB_DEVICE(0x10C4, 0x81C8) }, /* Lipowsky Industrie Elektronik GmbH, Baby-JTAG */ |
diff --git a/drivers/usb/serial/ftdi_sio.c b/drivers/usb/serial/ftdi_sio.c index f92f4d773374..ae84c326a540 100644 --- a/drivers/usb/serial/ftdi_sio.c +++ b/drivers/usb/serial/ftdi_sio.c | |||
| @@ -663,6 +663,11 @@ static struct usb_device_id id_table_combined [] = { | |||
| 663 | { USB_DEVICE(ALTI2_VID, ALTI2_N3_PID) }, | 663 | { USB_DEVICE(ALTI2_VID, ALTI2_N3_PID) }, |
| 664 | { USB_DEVICE(FTDI_VID, DIEBOLD_BCS_SE923_PID) }, | 664 | { USB_DEVICE(FTDI_VID, DIEBOLD_BCS_SE923_PID) }, |
| 665 | { USB_DEVICE(FTDI_VID, FTDI_NDI_HUC_PID) }, | 665 | { USB_DEVICE(FTDI_VID, FTDI_NDI_HUC_PID) }, |
| 666 | { USB_DEVICE(ATMEL_VID, STK541_PID) }, | ||
| 667 | { USB_DEVICE(DE_VID, STB_PID) }, | ||
| 668 | { USB_DEVICE(DE_VID, WHT_PID) }, | ||
| 669 | { USB_DEVICE(ADI_VID, ADI_GNICE_PID), | ||
| 670 | .driver_info = (kernel_ulong_t)&ftdi_jtag_quirk }, | ||
| 666 | { }, /* Optional parameter entry */ | 671 | { }, /* Optional parameter entry */ |
| 667 | { } /* Terminating entry */ | 672 | { } /* Terminating entry */ |
| 668 | }; | 673 | }; |
diff --git a/drivers/usb/serial/ftdi_sio.h b/drivers/usb/serial/ftdi_sio.h index e300c840f8ca..daaf63db0b50 100644 --- a/drivers/usb/serial/ftdi_sio.h +++ b/drivers/usb/serial/ftdi_sio.h | |||
| @@ -893,6 +893,26 @@ | |||
| 893 | #define DIEBOLD_BCS_SE923_PID 0xfb99 | 893 | #define DIEBOLD_BCS_SE923_PID 0xfb99 |
| 894 | 894 | ||
| 895 | /* | 895 | /* |
| 896 | * Atmel STK541 | ||
| 897 | */ | ||
| 898 | #define ATMEL_VID 0x03eb /* Vendor ID */ | ||
| 899 | #define STK541_PID 0x2109 /* Zigbee Controller */ | ||
| 900 | |||
| 901 | /* | ||
| 902 | * Dresden Elektronic Sensor Terminal Board | ||
| 903 | */ | ||
| 904 | #define DE_VID 0x1cf1 /* Vendor ID */ | ||
| 905 | #define STB_PID 0x0001 /* Sensor Terminal Board */ | ||
| 906 | #define WHT_PID 0x0004 /* Wireless Handheld Terminal */ | ||
| 907 | |||
| 908 | /* | ||
| 909 | * Blackfin gnICE JTAG | ||
| 910 | * http://docs.blackfin.uclinux.org/doku.php?id=hw:jtag:gnice | ||
| 911 | */ | ||
| 912 | #define ADI_VID 0x0456 | ||
| 913 | #define ADI_GNICE_PID 0xF000 | ||
| 914 | |||
| 915 | /* | ||
| 896 | * BmRequestType: 1100 0000b | 916 | * BmRequestType: 1100 0000b |
| 897 | * bRequest: FTDI_E2_READ | 917 | * bRequest: FTDI_E2_READ |
| 898 | * wValue: 0 | 918 | * wValue: 0 |
diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c index b7c132bded7f..61ebddc48497 100644 --- a/drivers/usb/serial/option.c +++ b/drivers/usb/serial/option.c | |||
| @@ -89,6 +89,7 @@ static int option_send_setup(struct tty_struct *tty, struct usb_serial_port *po | |||
| 89 | #define OPTION_PRODUCT_ETNA_MODEM_GT 0x7041 | 89 | #define OPTION_PRODUCT_ETNA_MODEM_GT 0x7041 |
| 90 | #define OPTION_PRODUCT_ETNA_MODEM_EX 0x7061 | 90 | #define OPTION_PRODUCT_ETNA_MODEM_EX 0x7061 |
| 91 | #define OPTION_PRODUCT_ETNA_KOI_MODEM 0x7100 | 91 | #define OPTION_PRODUCT_ETNA_KOI_MODEM 0x7100 |
| 92 | #define OPTION_PRODUCT_GTM380_MODEM 0x7201 | ||
| 92 | 93 | ||
| 93 | #define HUAWEI_VENDOR_ID 0x12D1 | 94 | #define HUAWEI_VENDOR_ID 0x12D1 |
| 94 | #define HUAWEI_PRODUCT_E600 0x1001 | 95 | #define HUAWEI_PRODUCT_E600 0x1001 |
| @@ -197,6 +198,7 @@ static int option_send_setup(struct tty_struct *tty, struct usb_serial_port *po | |||
| 197 | /* OVATION PRODUCTS */ | 198 | /* OVATION PRODUCTS */ |
| 198 | #define NOVATELWIRELESS_PRODUCT_MC727 0x4100 | 199 | #define NOVATELWIRELESS_PRODUCT_MC727 0x4100 |
| 199 | #define NOVATELWIRELESS_PRODUCT_MC950D 0x4400 | 200 | #define NOVATELWIRELESS_PRODUCT_MC950D 0x4400 |
| 201 | #define NOVATELWIRELESS_PRODUCT_U727 0x5010 | ||
| 200 | 202 | ||
| 201 | /* FUTURE NOVATEL PRODUCTS */ | 203 | /* FUTURE NOVATEL PRODUCTS */ |
| 202 | #define NOVATELWIRELESS_PRODUCT_EVDO_FULLSPEED 0X6000 | 204 | #define NOVATELWIRELESS_PRODUCT_EVDO_FULLSPEED 0X6000 |
| @@ -288,15 +290,11 @@ static int option_send_setup(struct tty_struct *tty, struct usb_serial_port *po | |||
| 288 | 290 | ||
| 289 | /* ZTE PRODUCTS */ | 291 | /* ZTE PRODUCTS */ |
| 290 | #define ZTE_VENDOR_ID 0x19d2 | 292 | #define ZTE_VENDOR_ID 0x19d2 |
| 293 | #define ZTE_PRODUCT_MF622 0x0001 | ||
| 291 | #define ZTE_PRODUCT_MF628 0x0015 | 294 | #define ZTE_PRODUCT_MF628 0x0015 |
| 292 | #define ZTE_PRODUCT_MF626 0x0031 | 295 | #define ZTE_PRODUCT_MF626 0x0031 |
| 293 | #define ZTE_PRODUCT_CDMA_TECH 0xfffe | 296 | #define ZTE_PRODUCT_CDMA_TECH 0xfffe |
| 294 | 297 | ||
| 295 | /* Ericsson products */ | ||
| 296 | #define ERICSSON_VENDOR_ID 0x0bdb | ||
| 297 | #define ERICSSON_PRODUCT_F3507G_1 0x1900 | ||
| 298 | #define ERICSSON_PRODUCT_F3507G_2 0x1902 | ||
| 299 | |||
| 300 | #define BENQ_VENDOR_ID 0x04a5 | 298 | #define BENQ_VENDOR_ID 0x04a5 |
| 301 | #define BENQ_PRODUCT_H10 0x4068 | 299 | #define BENQ_PRODUCT_H10 0x4068 |
| 302 | 300 | ||
| @@ -325,6 +323,7 @@ static struct usb_device_id option_ids[] = { | |||
| 325 | { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_ETNA_MODEM_GT) }, | 323 | { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_ETNA_MODEM_GT) }, |
| 326 | { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_ETNA_MODEM_EX) }, | 324 | { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_ETNA_MODEM_EX) }, |
| 327 | { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_ETNA_KOI_MODEM) }, | 325 | { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_ETNA_KOI_MODEM) }, |
| 326 | { USB_DEVICE(OPTION_VENDOR_ID, OPTION_PRODUCT_GTM380_MODEM) }, | ||
| 328 | { USB_DEVICE(QUANTA_VENDOR_ID, QUANTA_PRODUCT_Q101) }, | 327 | { USB_DEVICE(QUANTA_VENDOR_ID, QUANTA_PRODUCT_Q101) }, |
| 329 | { USB_DEVICE(QUANTA_VENDOR_ID, QUANTA_PRODUCT_Q111) }, | 328 | { USB_DEVICE(QUANTA_VENDOR_ID, QUANTA_PRODUCT_Q111) }, |
| 330 | { USB_DEVICE(QUANTA_VENDOR_ID, QUANTA_PRODUCT_GLX) }, | 329 | { USB_DEVICE(QUANTA_VENDOR_ID, QUANTA_PRODUCT_GLX) }, |
| @@ -415,6 +414,7 @@ static struct usb_device_id option_ids[] = { | |||
| 415 | { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_EU870D) }, /* Novatel EU850D/EU860D/EU870D */ | 414 | { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_EU870D) }, /* Novatel EU850D/EU860D/EU870D */ |
| 416 | { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_MC950D) }, /* Novatel MC930D/MC950D */ | 415 | { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_MC950D) }, /* Novatel MC930D/MC950D */ |
| 417 | { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_MC727) }, /* Novatel MC727/U727/USB727 */ | 416 | { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_MC727) }, /* Novatel MC727/U727/USB727 */ |
| 417 | { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_U727) }, /* Novatel MC727/U727/USB727 */ | ||
| 418 | { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_EVDO_FULLSPEED) }, /* Novatel EVDO product */ | 418 | { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_EVDO_FULLSPEED) }, /* Novatel EVDO product */ |
| 419 | { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_HSPA_FULLSPEED) }, /* Novatel HSPA product */ | 419 | { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_HSPA_FULLSPEED) }, /* Novatel HSPA product */ |
| 420 | { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_EVDO_EMBEDDED_FULLSPEED) }, /* Novatel EVDO Embedded product */ | 420 | { USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_EVDO_EMBEDDED_FULLSPEED) }, /* Novatel EVDO Embedded product */ |
| @@ -442,7 +442,6 @@ static struct usb_device_id option_ids[] = { | |||
| 442 | { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5520_MINICARD_CINGULAR) }, /* Dell Wireless HSDPA 5520 == Novatel Expedite EU860D */ | 442 | { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5520_MINICARD_CINGULAR) }, /* Dell Wireless HSDPA 5520 == Novatel Expedite EU860D */ |
| 443 | { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5520_MINICARD_GENERIC_L) }, /* Dell Wireless HSDPA 5520 */ | 443 | { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5520_MINICARD_GENERIC_L) }, /* Dell Wireless HSDPA 5520 */ |
| 444 | { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5520_MINICARD_GENERIC_I) }, /* Dell Wireless 5520 Voda I Mobile Broadband (3G HSDPA) Minicard */ | 444 | { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5520_MINICARD_GENERIC_I) }, /* Dell Wireless 5520 Voda I Mobile Broadband (3G HSDPA) Minicard */ |
| 445 | { USB_DEVICE(DELL_VENDOR_ID, 0x8147) }, /* Dell Wireless 5530 Mobile Broadband (3G HSPA) Mini-Card */ | ||
| 446 | { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5730_MINICARD_SPRINT) }, /* Dell Wireless 5730 Mobile Broadband EVDO/HSPA Mini-Card */ | 445 | { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5730_MINICARD_SPRINT) }, /* Dell Wireless 5730 Mobile Broadband EVDO/HSPA Mini-Card */ |
| 447 | { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5730_MINICARD_TELUS) }, /* Dell Wireless 5730 Mobile Broadband EVDO/HSPA Mini-Card */ | 446 | { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5730_MINICARD_TELUS) }, /* Dell Wireless 5730 Mobile Broadband EVDO/HSPA Mini-Card */ |
| 448 | { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5730_MINICARD_VZW) }, /* Dell Wireless 5730 Mobile Broadband EVDO/HSPA Mini-Card */ | 447 | { USB_DEVICE(DELL_VENDOR_ID, DELL_PRODUCT_5730_MINICARD_VZW) }, /* Dell Wireless 5730 Mobile Broadband EVDO/HSPA Mini-Card */ |
| @@ -510,11 +509,10 @@ static struct usb_device_id option_ids[] = { | |||
| 510 | { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x6613)}, /* Onda H600/ZTE MF330 */ | 509 | { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x6613)}, /* Onda H600/ZTE MF330 */ |
| 511 | { USB_DEVICE(MAXON_VENDOR_ID, 0x6280) }, /* BP3-USB & BP3-EXT HSDPA */ | 510 | { USB_DEVICE(MAXON_VENDOR_ID, 0x6280) }, /* BP3-USB & BP3-EXT HSDPA */ |
| 512 | { USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_UC864E) }, | 511 | { USB_DEVICE(TELIT_VENDOR_ID, TELIT_PRODUCT_UC864E) }, |
| 512 | { USB_DEVICE(ZTE_VENDOR_ID, ZTE_PRODUCT_MF622) }, | ||
| 513 | { USB_DEVICE(ZTE_VENDOR_ID, ZTE_PRODUCT_MF626) }, | 513 | { USB_DEVICE(ZTE_VENDOR_ID, ZTE_PRODUCT_MF626) }, |
| 514 | { USB_DEVICE(ZTE_VENDOR_ID, ZTE_PRODUCT_MF628) }, | 514 | { USB_DEVICE(ZTE_VENDOR_ID, ZTE_PRODUCT_MF628) }, |
| 515 | { USB_DEVICE(ZTE_VENDOR_ID, ZTE_PRODUCT_CDMA_TECH) }, | 515 | { USB_DEVICE(ZTE_VENDOR_ID, ZTE_PRODUCT_CDMA_TECH) }, |
| 516 | { USB_DEVICE(ERICSSON_VENDOR_ID, ERICSSON_PRODUCT_F3507G_1) }, | ||
| 517 | { USB_DEVICE(ERICSSON_VENDOR_ID, ERICSSON_PRODUCT_F3507G_2) }, | ||
| 518 | { USB_DEVICE(BENQ_VENDOR_ID, BENQ_PRODUCT_H10) }, | 516 | { USB_DEVICE(BENQ_VENDOR_ID, BENQ_PRODUCT_H10) }, |
| 519 | { USB_DEVICE(0x1da5, 0x4515) }, /* BenQ H20 */ | 517 | { USB_DEVICE(0x1da5, 0x4515) }, /* BenQ H20 */ |
| 520 | { } /* Terminating entry */ | 518 | { } /* Terminating entry */ |
diff --git a/drivers/usb/storage/unusual_devs.h b/drivers/usb/storage/unusual_devs.h index 6f59c8e510ea..cfde74a6faa3 100644 --- a/drivers/usb/storage/unusual_devs.h +++ b/drivers/usb/storage/unusual_devs.h | |||
| @@ -226,7 +226,7 @@ UNUSUAL_DEV( 0x0421, 0x047c, 0x0370, 0x0610, | |||
| 226 | US_FL_MAX_SECTORS_64 ), | 226 | US_FL_MAX_SECTORS_64 ), |
| 227 | 227 | ||
| 228 | /* Reported by Manuel Osdoba <manuel.osdoba@tu-ilmenau.de> */ | 228 | /* Reported by Manuel Osdoba <manuel.osdoba@tu-ilmenau.de> */ |
| 229 | UNUSUAL_DEV( 0x0421, 0x0492, 0x0452, 0x0452, | 229 | UNUSUAL_DEV( 0x0421, 0x0492, 0x0452, 0x9999, |
| 230 | "Nokia", | 230 | "Nokia", |
| 231 | "Nokia 6233", | 231 | "Nokia 6233", |
| 232 | US_SC_DEVICE, US_PR_DEVICE, NULL, | 232 | US_SC_DEVICE, US_PR_DEVICE, NULL, |
| @@ -951,7 +951,9 @@ UNUSUAL_DEV( 0x066f, 0x8000, 0x0001, 0x0001, | |||
| 951 | US_FL_FIX_CAPACITY ), | 951 | US_FL_FIX_CAPACITY ), |
| 952 | 952 | ||
| 953 | /* Reported by Richard -=[]=- <micro_flyer@hotmail.com> */ | 953 | /* Reported by Richard -=[]=- <micro_flyer@hotmail.com> */ |
| 954 | UNUSUAL_DEV( 0x067b, 0x2507, 0x0100, 0x0100, | 954 | /* Change to bcdDeviceMin (0x0100 to 0x0001) reported by |
| 955 | * Thomas Bartosik <tbartdev@gmx-topmail.de> */ | ||
| 956 | UNUSUAL_DEV( 0x067b, 0x2507, 0x0001, 0x0100, | ||
| 955 | "Prolific Technology Inc.", | 957 | "Prolific Technology Inc.", |
| 956 | "Mass Storage Device", | 958 | "Mass Storage Device", |
| 957 | US_SC_DEVICE, US_PR_DEVICE, NULL, | 959 | US_SC_DEVICE, US_PR_DEVICE, NULL, |
| @@ -1390,6 +1392,16 @@ UNUSUAL_DEV( 0x0af0, 0x7401, 0x0000, 0x0000, | |||
| 1390 | US_SC_DEVICE, US_PR_DEVICE, NULL, | 1392 | US_SC_DEVICE, US_PR_DEVICE, NULL, |
| 1391 | 0 ), | 1393 | 0 ), |
| 1392 | 1394 | ||
| 1395 | /* Reported by Jan Dumon <j.dumon@option.com> | ||
| 1396 | * This device (wrongly) has a vendor-specific device descriptor. | ||
| 1397 | * The entry is needed so usb-storage can bind to it's mass-storage | ||
| 1398 | * interface as an interface driver */ | ||
| 1399 | UNUSUAL_DEV( 0x0af0, 0x7501, 0x0000, 0x0000, | ||
| 1400 | "Option", | ||
| 1401 | "GI 0431 SD-Card", | ||
| 1402 | US_SC_DEVICE, US_PR_DEVICE, NULL, | ||
| 1403 | 0 ), | ||
| 1404 | |||
| 1393 | /* Reported by Ben Efros <ben@pc-doctor.com> */ | 1405 | /* Reported by Ben Efros <ben@pc-doctor.com> */ |
| 1394 | UNUSUAL_DEV( 0x0bc2, 0x3010, 0x0000, 0x0000, | 1406 | UNUSUAL_DEV( 0x0bc2, 0x3010, 0x0000, 0x0000, |
| 1395 | "Seagate", | 1407 | "Seagate", |
diff --git a/drivers/usb/wusbcore/wa-xfer.c b/drivers/usb/wusbcore/wa-xfer.c index 238a96aee3a1..613a5fc490d3 100644 --- a/drivers/usb/wusbcore/wa-xfer.c +++ b/drivers/usb/wusbcore/wa-xfer.c | |||
| @@ -921,8 +921,10 @@ static void wa_urb_enqueue_b(struct wa_xfer *xfer) | |||
| 921 | result = -ENODEV; | 921 | result = -ENODEV; |
| 922 | /* FIXME: segmentation broken -- kills DWA */ | 922 | /* FIXME: segmentation broken -- kills DWA */ |
| 923 | mutex_lock(&wusbhc->mutex); /* get a WUSB dev */ | 923 | mutex_lock(&wusbhc->mutex); /* get a WUSB dev */ |
| 924 | if (urb->dev == NULL) | 924 | if (urb->dev == NULL) { |
| 925 | mutex_unlock(&wusbhc->mutex); | ||
| 925 | goto error_dev_gone; | 926 | goto error_dev_gone; |
| 927 | } | ||
| 926 | wusb_dev = __wusb_dev_get_by_usb_dev(wusbhc, urb->dev); | 928 | wusb_dev = __wusb_dev_get_by_usb_dev(wusbhc, urb->dev); |
| 927 | if (wusb_dev == NULL) { | 929 | if (wusb_dev == NULL) { |
| 928 | mutex_unlock(&wusbhc->mutex); | 930 | mutex_unlock(&wusbhc->mutex); |
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index fb19803060cf..41c27a44bd82 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig | |||
| @@ -397,7 +397,7 @@ config FB_SA1100 | |||
| 397 | 397 | ||
| 398 | config FB_IMX | 398 | config FB_IMX |
| 399 | tristate "Motorola i.MX LCD support" | 399 | tristate "Motorola i.MX LCD support" |
| 400 | depends on FB && ARM && ARCH_IMX | 400 | depends on FB && (ARCH_IMX || ARCH_MX2) |
| 401 | select FB_CFB_FILLRECT | 401 | select FB_CFB_FILLRECT |
| 402 | select FB_CFB_COPYAREA | 402 | select FB_CFB_COPYAREA |
| 403 | select FB_CFB_IMAGEBLIT | 403 | select FB_CFB_IMAGEBLIT |
| @@ -2120,16 +2120,30 @@ config FB_PRE_INIT_FB | |||
| 2120 | the bootloader. | 2120 | the bootloader. |
| 2121 | 2121 | ||
| 2122 | config FB_MX3 | 2122 | config FB_MX3 |
| 2123 | tristate "MX3 Framebuffer support" | 2123 | tristate "MX3 Framebuffer support" |
| 2124 | depends on FB && MX3_IPU | 2124 | depends on FB && MX3_IPU |
| 2125 | select FB_CFB_FILLRECT | 2125 | select FB_CFB_FILLRECT |
| 2126 | select FB_CFB_COPYAREA | 2126 | select FB_CFB_COPYAREA |
| 2127 | select FB_CFB_IMAGEBLIT | 2127 | select FB_CFB_IMAGEBLIT |
| 2128 | default y | 2128 | default y |
| 2129 | help | 2129 | help |
| 2130 | This is a framebuffer device for the i.MX31 LCD Controller. So | 2130 | This is a framebuffer device for the i.MX31 LCD Controller. So |
| 2131 | far only synchronous displays are supported. If you plan to use | 2131 | far only synchronous displays are supported. If you plan to use |
| 2132 | an LCD display with your i.MX31 system, say Y here. | 2132 | an LCD display with your i.MX31 system, say Y here. |
| 2133 | |||
| 2134 | config FB_BROADSHEET | ||
| 2135 | tristate "E-Ink Broadsheet/Epson S1D13521 controller support" | ||
| 2136 | depends on FB | ||
| 2137 | select FB_SYS_FILLRECT | ||
| 2138 | select FB_SYS_COPYAREA | ||
| 2139 | select FB_SYS_IMAGEBLIT | ||
| 2140 | select FB_SYS_FOPS | ||
| 2141 | select FB_DEFERRED_IO | ||
| 2142 | help | ||
| 2143 | This driver implements support for the E-Ink Broadsheet | ||
| 2144 | controller. The release name for this device was Epson S1D13521 | ||
| 2145 | and could also have been called by other names when coupled with | ||
| 2146 | a bridge adapter. | ||
| 2133 | 2147 | ||
| 2134 | source "drivers/video/omap/Kconfig" | 2148 | source "drivers/video/omap/Kconfig" |
| 2135 | 2149 | ||
diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 2a998ca6181d..bb265eca7d57 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile | |||
| @@ -106,6 +106,7 @@ obj-$(CONFIG_FB_PMAG_BA) += pmag-ba-fb.o | |||
| 106 | obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o | 106 | obj-$(CONFIG_FB_PMAGB_B) += pmagb-b-fb.o |
| 107 | obj-$(CONFIG_FB_MAXINE) += maxinefb.o | 107 | obj-$(CONFIG_FB_MAXINE) += maxinefb.o |
| 108 | obj-$(CONFIG_FB_METRONOME) += metronomefb.o | 108 | obj-$(CONFIG_FB_METRONOME) += metronomefb.o |
| 109 | obj-$(CONFIG_FB_BROADSHEET) += broadsheetfb.o | ||
| 109 | obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o | 110 | obj-$(CONFIG_FB_S1D13XXX) += s1d13xxxfb.o |
| 110 | obj-$(CONFIG_FB_SH7760) += sh7760fb.o | 111 | obj-$(CONFIG_FB_SH7760) += sh7760fb.o |
| 111 | obj-$(CONFIG_FB_IMX) += imxfb.o | 112 | obj-$(CONFIG_FB_IMX) += imxfb.o |
| @@ -132,7 +133,7 @@ obj-$(CONFIG_FB_VGA16) += vga16fb.o | |||
| 132 | obj-$(CONFIG_FB_OF) += offb.o | 133 | obj-$(CONFIG_FB_OF) += offb.o |
| 133 | obj-$(CONFIG_FB_BF54X_LQ043) += bf54x-lq043fb.o | 134 | obj-$(CONFIG_FB_BF54X_LQ043) += bf54x-lq043fb.o |
| 134 | obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o | 135 | obj-$(CONFIG_FB_BFIN_T350MCQB) += bfin-t350mcqb-fb.o |
| 135 | obj-$(CONFIG_FB_MX3) += mx3fb.o | 136 | obj-$(CONFIG_FB_MX3) += mx3fb.o |
| 136 | 137 | ||
| 137 | # the test framebuffer is last | 138 | # the test framebuffer is last |
| 138 | obj-$(CONFIG_FB_VIRTUAL) += vfb.o | 139 | obj-$(CONFIG_FB_VIRTUAL) += vfb.o |
diff --git a/drivers/video/acornfb.c b/drivers/video/acornfb.c index 61c3d3f40fd1..6995fe1e86d4 100644 --- a/drivers/video/acornfb.c +++ b/drivers/video/acornfb.c | |||
| @@ -28,9 +28,9 @@ | |||
| 28 | #include <linux/fb.h> | 28 | #include <linux/fb.h> |
| 29 | #include <linux/platform_device.h> | 29 | #include <linux/platform_device.h> |
| 30 | #include <linux/dma-mapping.h> | 30 | #include <linux/dma-mapping.h> |
| 31 | #include <linux/io.h> | ||
| 31 | 32 | ||
| 32 | #include <mach/hardware.h> | 33 | #include <mach/hardware.h> |
| 33 | #include <asm/io.h> | ||
| 34 | #include <asm/irq.h> | 34 | #include <asm/irq.h> |
| 35 | #include <asm/mach-types.h> | 35 | #include <asm/mach-types.h> |
| 36 | #include <asm/pgtable.h> | 36 | #include <asm/pgtable.h> |
diff --git a/drivers/video/aty/aty128fb.c b/drivers/video/aty/aty128fb.c index 2181ce4d7ebd..35e8eb02b9e9 100644 --- a/drivers/video/aty/aty128fb.c +++ b/drivers/video/aty/aty128fb.c | |||
| @@ -1853,13 +1853,14 @@ static void aty128_bl_exit(struct backlight_device *bd) | |||
| 1853 | * Initialisation | 1853 | * Initialisation |
| 1854 | */ | 1854 | */ |
| 1855 | 1855 | ||
| 1856 | #ifdef CONFIG_PPC_PMAC | 1856 | #ifdef CONFIG_PPC_PMAC__disabled |
| 1857 | static void aty128_early_resume(void *data) | 1857 | static void aty128_early_resume(void *data) |
| 1858 | { | 1858 | { |
| 1859 | struct aty128fb_par *par = data; | 1859 | struct aty128fb_par *par = data; |
| 1860 | 1860 | ||
| 1861 | if (try_acquire_console_sem()) | 1861 | if (try_acquire_console_sem()) |
| 1862 | return; | 1862 | return; |
| 1863 | pci_restore_state(par->pdev); | ||
| 1863 | aty128_do_resume(par->pdev); | 1864 | aty128_do_resume(par->pdev); |
| 1864 | release_console_sem(); | 1865 | release_console_sem(); |
| 1865 | } | 1866 | } |
| @@ -1907,7 +1908,14 @@ static int __devinit aty128_init(struct pci_dev *pdev, const struct pci_device_i | |||
| 1907 | /* Indicate sleep capability */ | 1908 | /* Indicate sleep capability */ |
| 1908 | if (par->chip_gen == rage_M3) { | 1909 | if (par->chip_gen == rage_M3) { |
| 1909 | pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1); | 1910 | pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1); |
| 1911 | #if 0 /* Disable the early video resume hack for now as it's causing problems, among | ||
| 1912 | * others we now rely on the PCI core restoring the config space for us, which | ||
| 1913 | * isn't the case with that hack, and that code path causes various things to | ||
| 1914 | * be called with interrupts off while they shouldn't. I'm leaving the code in | ||
| 1915 | * as it can be useful for debugging purposes | ||
| 1916 | */ | ||
| 1910 | pmac_set_early_video_resume(aty128_early_resume, par); | 1917 | pmac_set_early_video_resume(aty128_early_resume, par); |
| 1918 | #endif | ||
| 1911 | } | 1919 | } |
| 1912 | 1920 | ||
| 1913 | /* Find default mode */ | 1921 | /* Find default mode */ |
diff --git a/drivers/video/aty/radeon_pm.c b/drivers/video/aty/radeon_pm.c index ca5f0dc28546..c6d7cc76516f 100644 --- a/drivers/video/aty/radeon_pm.c +++ b/drivers/video/aty/radeon_pm.c | |||
| @@ -2507,6 +2507,25 @@ static void radeon_reinitialize_QW(struct radeonfb_info *rinfo) | |||
| 2507 | 2507 | ||
| 2508 | #endif /* CONFIG_PPC_OF */ | 2508 | #endif /* CONFIG_PPC_OF */ |
| 2509 | 2509 | ||
| 2510 | static void radeonfb_whack_power_state(struct radeonfb_info *rinfo, pci_power_t state) | ||
| 2511 | { | ||
| 2512 | u16 pwr_cmd; | ||
| 2513 | |||
| 2514 | for (;;) { | ||
| 2515 | pci_read_config_word(rinfo->pdev, | ||
| 2516 | rinfo->pm_reg+PCI_PM_CTRL, | ||
| 2517 | &pwr_cmd); | ||
| 2518 | if (pwr_cmd & 2) | ||
| 2519 | break; | ||
| 2520 | pwr_cmd = (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2; | ||
| 2521 | pci_write_config_word(rinfo->pdev, | ||
| 2522 | rinfo->pm_reg+PCI_PM_CTRL, | ||
| 2523 | pwr_cmd); | ||
| 2524 | msleep(500); | ||
| 2525 | } | ||
| 2526 | rinfo->pdev->current_state = state; | ||
| 2527 | } | ||
| 2528 | |||
| 2510 | static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend) | 2529 | static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend) |
| 2511 | { | 2530 | { |
| 2512 | u32 tmp; | 2531 | u32 tmp; |
| @@ -2558,6 +2577,11 @@ static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend) | |||
| 2558 | /* Switch PCI power management to D2. */ | 2577 | /* Switch PCI power management to D2. */ |
| 2559 | pci_disable_device(rinfo->pdev); | 2578 | pci_disable_device(rinfo->pdev); |
| 2560 | pci_save_state(rinfo->pdev); | 2579 | pci_save_state(rinfo->pdev); |
| 2580 | /* The chip seems to need us to whack the PM register | ||
| 2581 | * repeatedly until it sticks. We do that -prior- to | ||
| 2582 | * calling pci_set_power_state() | ||
| 2583 | */ | ||
| 2584 | radeonfb_whack_power_state(rinfo, PCI_D2); | ||
| 2561 | pci_set_power_state(rinfo->pdev, PCI_D2); | 2585 | pci_set_power_state(rinfo->pdev, PCI_D2); |
| 2562 | } else { | 2586 | } else { |
| 2563 | printk(KERN_DEBUG "radeonfb (%s): switching to D0 state...\n", | 2587 | printk(KERN_DEBUG "radeonfb (%s): switching to D0 state...\n", |
| @@ -2762,12 +2786,13 @@ int radeonfb_pci_resume(struct pci_dev *pdev) | |||
| 2762 | return rc; | 2786 | return rc; |
| 2763 | } | 2787 | } |
| 2764 | 2788 | ||
| 2765 | #ifdef CONFIG_PPC_OF | 2789 | #ifdef CONFIG_PPC_OF__disabled |
| 2766 | static void radeonfb_early_resume(void *data) | 2790 | static void radeonfb_early_resume(void *data) |
| 2767 | { | 2791 | { |
| 2768 | struct radeonfb_info *rinfo = data; | 2792 | struct radeonfb_info *rinfo = data; |
| 2769 | 2793 | ||
| 2770 | rinfo->no_schedule = 1; | 2794 | rinfo->no_schedule = 1; |
| 2795 | pci_restore_state(rinfo->pdev); | ||
| 2771 | radeonfb_pci_resume(rinfo->pdev); | 2796 | radeonfb_pci_resume(rinfo->pdev); |
| 2772 | rinfo->no_schedule = 0; | 2797 | rinfo->no_schedule = 0; |
| 2773 | } | 2798 | } |
| @@ -2834,7 +2859,14 @@ void radeonfb_pm_init(struct radeonfb_info *rinfo, int dynclk, int ignore_devlis | |||
| 2834 | */ | 2859 | */ |
| 2835 | if (rinfo->pm_mode != radeon_pm_none) { | 2860 | if (rinfo->pm_mode != radeon_pm_none) { |
| 2836 | pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1); | 2861 | pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, rinfo->of_node, 0, 1); |
| 2862 | #if 0 /* Disable the early video resume hack for now as it's causing problems, among | ||
| 2863 | * others we now rely on the PCI core restoring the config space for us, which | ||
| 2864 | * isn't the case with that hack, and that code path causes various things to | ||
| 2865 | * be called with interrupts off while they shouldn't. I'm leaving the code in | ||
| 2866 | * as it can be useful for debugging purposes | ||
| 2867 | */ | ||
| 2837 | pmac_set_early_video_resume(radeonfb_early_resume, rinfo); | 2868 | pmac_set_early_video_resume(radeonfb_early_resume, rinfo); |
| 2869 | #endif | ||
| 2838 | } | 2870 | } |
| 2839 | 2871 | ||
| 2840 | #if 0 | 2872 | #if 0 |
diff --git a/drivers/video/broadsheetfb.c b/drivers/video/broadsheetfb.c new file mode 100644 index 000000000000..509cb92e8731 --- /dev/null +++ b/drivers/video/broadsheetfb.c | |||
| @@ -0,0 +1,568 @@ | |||
| 1 | /* | ||
| 2 | * broadsheetfb.c -- FB driver for E-Ink Broadsheet controller | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008, Jaya Kumar | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file COPYING in the main directory of this archive for | ||
| 8 | * more details. | ||
| 9 | * | ||
| 10 | * Layout is based on skeletonfb.c by James Simmons and Geert Uytterhoeven. | ||
| 11 | * | ||
| 12 | * This driver is written to be used with the Broadsheet display controller. | ||
| 13 | * | ||
| 14 | * It is intended to be architecture independent. A board specific driver | ||
| 15 | * must be used to perform all the physical IO interactions. | ||
| 16 | * | ||
| 17 | */ | ||
| 18 | |||
| 19 | #include <linux/module.h> | ||
| 20 | #include <linux/kernel.h> | ||
| 21 | #include <linux/errno.h> | ||
| 22 | #include <linux/string.h> | ||
| 23 | #include <linux/mm.h> | ||
| 24 | #include <linux/slab.h> | ||
| 25 | #include <linux/vmalloc.h> | ||
| 26 | #include <linux/delay.h> | ||
| 27 | #include <linux/interrupt.h> | ||
| 28 | #include <linux/fb.h> | ||
| 29 | #include <linux/init.h> | ||
| 30 | #include <linux/platform_device.h> | ||
| 31 | #include <linux/list.h> | ||
| 32 | #include <linux/uaccess.h> | ||
| 33 | |||
| 34 | #include <video/broadsheetfb.h> | ||
| 35 | |||
| 36 | /* Display specific information */ | ||
| 37 | #define DPY_W 800 | ||
| 38 | #define DPY_H 600 | ||
| 39 | |||
| 40 | static struct fb_fix_screeninfo broadsheetfb_fix __devinitdata = { | ||
| 41 | .id = "broadsheetfb", | ||
| 42 | .type = FB_TYPE_PACKED_PIXELS, | ||
| 43 | .visual = FB_VISUAL_STATIC_PSEUDOCOLOR, | ||
| 44 | .xpanstep = 0, | ||
| 45 | .ypanstep = 0, | ||
| 46 | .ywrapstep = 0, | ||
| 47 | .line_length = DPY_W, | ||
| 48 | .accel = FB_ACCEL_NONE, | ||
| 49 | }; | ||
| 50 | |||
| 51 | static struct fb_var_screeninfo broadsheetfb_var __devinitdata = { | ||
| 52 | .xres = DPY_W, | ||
| 53 | .yres = DPY_H, | ||
| 54 | .xres_virtual = DPY_W, | ||
| 55 | .yres_virtual = DPY_H, | ||
| 56 | .bits_per_pixel = 8, | ||
| 57 | .grayscale = 1, | ||
| 58 | .red = { 0, 4, 0 }, | ||
| 59 | .green = { 0, 4, 0 }, | ||
| 60 | .blue = { 0, 4, 0 }, | ||
| 61 | .transp = { 0, 0, 0 }, | ||
| 62 | }; | ||
| 63 | |||
| 64 | /* main broadsheetfb functions */ | ||
| 65 | static void broadsheet_issue_data(struct broadsheetfb_par *par, u16 data) | ||
| 66 | { | ||
| 67 | par->board->set_ctl(par, BS_WR, 0); | ||
| 68 | par->board->set_hdb(par, data); | ||
| 69 | par->board->set_ctl(par, BS_WR, 1); | ||
| 70 | } | ||
| 71 | |||
| 72 | static void broadsheet_issue_cmd(struct broadsheetfb_par *par, u16 data) | ||
| 73 | { | ||
| 74 | par->board->set_ctl(par, BS_DC, 0); | ||
| 75 | broadsheet_issue_data(par, data); | ||
| 76 | } | ||
| 77 | |||
| 78 | static void broadsheet_send_command(struct broadsheetfb_par *par, u16 data) | ||
| 79 | { | ||
| 80 | par->board->wait_for_rdy(par); | ||
| 81 | |||
| 82 | par->board->set_ctl(par, BS_CS, 0); | ||
| 83 | broadsheet_issue_cmd(par, data); | ||
| 84 | par->board->set_ctl(par, BS_DC, 1); | ||
| 85 | par->board->set_ctl(par, BS_CS, 1); | ||
| 86 | } | ||
| 87 | |||
| 88 | static void broadsheet_send_cmdargs(struct broadsheetfb_par *par, u16 cmd, | ||
| 89 | int argc, u16 *argv) | ||
| 90 | { | ||
| 91 | int i; | ||
| 92 | |||
| 93 | par->board->wait_for_rdy(par); | ||
| 94 | |||
| 95 | par->board->set_ctl(par, BS_CS, 0); | ||
| 96 | broadsheet_issue_cmd(par, cmd); | ||
| 97 | par->board->set_ctl(par, BS_DC, 1); | ||
| 98 | |||
| 99 | for (i = 0; i < argc; i++) | ||
| 100 | broadsheet_issue_data(par, argv[i]); | ||
| 101 | par->board->set_ctl(par, BS_CS, 1); | ||
| 102 | } | ||
| 103 | |||
| 104 | static void broadsheet_burst_write(struct broadsheetfb_par *par, int size, | ||
| 105 | u16 *data) | ||
| 106 | { | ||
| 107 | int i; | ||
| 108 | u16 tmp; | ||
| 109 | |||
| 110 | par->board->set_ctl(par, BS_CS, 0); | ||
| 111 | par->board->set_ctl(par, BS_DC, 1); | ||
| 112 | |||
| 113 | for (i = 0; i < size; i++) { | ||
| 114 | par->board->set_ctl(par, BS_WR, 0); | ||
| 115 | tmp = (data[i] & 0x0F) << 4; | ||
| 116 | tmp |= (data[i] & 0x0F00) << 4; | ||
| 117 | par->board->set_hdb(par, tmp); | ||
| 118 | par->board->set_ctl(par, BS_WR, 1); | ||
| 119 | } | ||
| 120 | |||
| 121 | par->board->set_ctl(par, BS_CS, 1); | ||
| 122 | } | ||
| 123 | |||
| 124 | static u16 broadsheet_get_data(struct broadsheetfb_par *par) | ||
| 125 | { | ||
| 126 | u16 res; | ||
| 127 | /* wait for ready to go hi. (lo is busy) */ | ||
| 128 | par->board->wait_for_rdy(par); | ||
| 129 | |||
| 130 | /* cs lo, dc lo for cmd, we lo for each data, db as usual */ | ||
| 131 | par->board->set_ctl(par, BS_DC, 1); | ||
| 132 | par->board->set_ctl(par, BS_CS, 0); | ||
| 133 | par->board->set_ctl(par, BS_WR, 0); | ||
| 134 | |||
| 135 | res = par->board->get_hdb(par); | ||
| 136 | |||
| 137 | /* strobe wr */ | ||
| 138 | par->board->set_ctl(par, BS_WR, 1); | ||
| 139 | par->board->set_ctl(par, BS_CS, 1); | ||
| 140 | |||
| 141 | return res; | ||
| 142 | } | ||
| 143 | |||
| 144 | static void broadsheet_write_reg(struct broadsheetfb_par *par, u16 reg, | ||
| 145 | u16 data) | ||
| 146 | { | ||
| 147 | /* wait for ready to go hi. (lo is busy) */ | ||
| 148 | par->board->wait_for_rdy(par); | ||
| 149 | |||
| 150 | /* cs lo, dc lo for cmd, we lo for each data, db as usual */ | ||
| 151 | par->board->set_ctl(par, BS_CS, 0); | ||
| 152 | |||
| 153 | broadsheet_issue_cmd(par, BS_CMD_WR_REG); | ||
| 154 | |||
| 155 | par->board->set_ctl(par, BS_DC, 1); | ||
| 156 | |||
| 157 | broadsheet_issue_data(par, reg); | ||
| 158 | broadsheet_issue_data(par, data); | ||
| 159 | |||
| 160 | par->board->set_ctl(par, BS_CS, 1); | ||
| 161 | } | ||
| 162 | |||
| 163 | static u16 broadsheet_read_reg(struct broadsheetfb_par *par, u16 reg) | ||
| 164 | { | ||
| 165 | broadsheet_send_command(par, reg); | ||
| 166 | msleep(100); | ||
| 167 | return broadsheet_get_data(par); | ||
| 168 | } | ||
| 169 | |||
| 170 | static void __devinit broadsheet_init_display(struct broadsheetfb_par *par) | ||
| 171 | { | ||
| 172 | u16 args[5]; | ||
| 173 | |||
| 174 | args[0] = DPY_W; | ||
| 175 | args[1] = DPY_H; | ||
| 176 | args[2] = (100 | (1 << 8) | (1 << 9)); /* sdcfg */ | ||
| 177 | args[3] = 2; /* gdrv cfg */ | ||
| 178 | args[4] = (4 | (1 << 7)); /* lut index format */ | ||
| 179 | broadsheet_send_cmdargs(par, BS_CMD_INIT_DSPE_CFG, 5, args); | ||
| 180 | |||
| 181 | /* did the controller really set it? */ | ||
| 182 | broadsheet_send_cmdargs(par, BS_CMD_INIT_DSPE_CFG, 5, args); | ||
| 183 | |||
| 184 | args[0] = 4; /* fsync len */ | ||
| 185 | args[1] = (10 << 8) | 4; /* fend/fbegin len */ | ||
| 186 | args[2] = 10; /* line sync len */ | ||
| 187 | args[3] = (100 << 8) | 4; /* line end/begin len */ | ||
| 188 | args[4] = 6; /* pixel clock cfg */ | ||
| 189 | broadsheet_send_cmdargs(par, BS_CMD_INIT_DSPE_TMG, 5, args); | ||
| 190 | |||
| 191 | /* setup waveform */ | ||
| 192 | args[0] = 0x886; | ||
| 193 | args[1] = 0; | ||
| 194 | broadsheet_send_cmdargs(par, BS_CMD_RD_WFM_INFO, 2, args); | ||
| 195 | |||
| 196 | broadsheet_send_command(par, BS_CMD_UPD_GDRV_CLR); | ||
| 197 | |||
| 198 | broadsheet_send_command(par, BS_CMD_WAIT_DSPE_TRG); | ||
| 199 | |||
| 200 | broadsheet_write_reg(par, 0x330, 0x84); | ||
| 201 | |||
| 202 | broadsheet_send_command(par, BS_CMD_WAIT_DSPE_TRG); | ||
| 203 | |||
| 204 | args[0] = (0x3 << 4); | ||
| 205 | broadsheet_send_cmdargs(par, BS_CMD_LD_IMG, 1, args); | ||
| 206 | |||
| 207 | args[0] = 0x154; | ||
| 208 | broadsheet_send_cmdargs(par, BS_CMD_WR_REG, 1, args); | ||
| 209 | |||
| 210 | broadsheet_burst_write(par, DPY_W*DPY_H/2, | ||
| 211 | (u16 *) par->info->screen_base); | ||
| 212 | |||
| 213 | broadsheet_send_command(par, BS_CMD_LD_IMG_END); | ||
| 214 | |||
| 215 | args[0] = 0x4300; | ||
| 216 | broadsheet_send_cmdargs(par, BS_CMD_UPD_FULL, 1, args); | ||
| 217 | |||
| 218 | broadsheet_send_command(par, BS_CMD_WAIT_DSPE_TRG); | ||
| 219 | |||
| 220 | broadsheet_send_command(par, BS_CMD_WAIT_DSPE_FREND); | ||
| 221 | |||
| 222 | par->board->wait_for_rdy(par); | ||
| 223 | } | ||
| 224 | |||
| 225 | static void __devinit broadsheet_init(struct broadsheetfb_par *par) | ||
| 226 | { | ||
| 227 | broadsheet_send_command(par, BS_CMD_INIT_SYS_RUN); | ||
| 228 | /* the controller needs a second */ | ||
| 229 | msleep(1000); | ||
| 230 | broadsheet_init_display(par); | ||
| 231 | } | ||
| 232 | |||
| 233 | static void broadsheetfb_dpy_update_pages(struct broadsheetfb_par *par, | ||
| 234 | u16 y1, u16 y2) | ||
| 235 | { | ||
| 236 | u16 args[5]; | ||
| 237 | unsigned char *buf = (unsigned char *)par->info->screen_base; | ||
| 238 | |||
| 239 | /* y1 must be a multiple of 4 so drop the lower bits */ | ||
| 240 | y1 &= 0xFFFC; | ||
| 241 | /* y2 must be a multiple of 4 , but - 1 so up the lower bits */ | ||
| 242 | y2 |= 0x0003; | ||
| 243 | |||
| 244 | args[0] = 0x3 << 4; | ||
| 245 | args[1] = 0; | ||
| 246 | args[2] = y1; | ||
| 247 | args[3] = cpu_to_le16(par->info->var.xres); | ||
| 248 | args[4] = y2; | ||
| 249 | broadsheet_send_cmdargs(par, BS_CMD_LD_IMG_AREA, 5, args); | ||
| 250 | |||
| 251 | args[0] = 0x154; | ||
| 252 | broadsheet_send_cmdargs(par, BS_CMD_WR_REG, 1, args); | ||
| 253 | |||
| 254 | buf += y1 * par->info->var.xres; | ||
| 255 | broadsheet_burst_write(par, ((1 + y2 - y1) * par->info->var.xres)/2, | ||
| 256 | (u16 *) buf); | ||
| 257 | |||
| 258 | broadsheet_send_command(par, BS_CMD_LD_IMG_END); | ||
| 259 | |||
| 260 | args[0] = 0x4300; | ||
| 261 | broadsheet_send_cmdargs(par, BS_CMD_UPD_FULL, 1, args); | ||
| 262 | |||
| 263 | broadsheet_send_command(par, BS_CMD_WAIT_DSPE_TRG); | ||
| 264 | |||
| 265 | broadsheet_send_command(par, BS_CMD_WAIT_DSPE_FREND); | ||
| 266 | |||
| 267 | par->board->wait_for_rdy(par); | ||
| 268 | |||
| 269 | } | ||
| 270 | |||
| 271 | static void broadsheetfb_dpy_update(struct broadsheetfb_par *par) | ||
| 272 | { | ||
| 273 | u16 args[5]; | ||
| 274 | |||
| 275 | args[0] = 0x3 << 4; | ||
| 276 | broadsheet_send_cmdargs(par, BS_CMD_LD_IMG, 1, args); | ||
| 277 | |||
| 278 | args[0] = 0x154; | ||
| 279 | broadsheet_send_cmdargs(par, BS_CMD_WR_REG, 1, args); | ||
| 280 | broadsheet_burst_write(par, DPY_W*DPY_H/2, | ||
| 281 | (u16 *) par->info->screen_base); | ||
| 282 | |||
| 283 | broadsheet_send_command(par, BS_CMD_LD_IMG_END); | ||
| 284 | |||
| 285 | args[0] = 0x4300; | ||
| 286 | broadsheet_send_cmdargs(par, BS_CMD_UPD_FULL, 1, args); | ||
| 287 | |||
| 288 | broadsheet_send_command(par, BS_CMD_WAIT_DSPE_TRG); | ||
| 289 | |||
| 290 | broadsheet_send_command(par, BS_CMD_WAIT_DSPE_FREND); | ||
| 291 | |||
| 292 | par->board->wait_for_rdy(par); | ||
| 293 | |||
| 294 | } | ||
| 295 | |||
| 296 | /* this is called back from the deferred io workqueue */ | ||
| 297 | static void broadsheetfb_dpy_deferred_io(struct fb_info *info, | ||
| 298 | struct list_head *pagelist) | ||
| 299 | { | ||
| 300 | u16 y1 = 0, h = 0; | ||
| 301 | int prev_index = -1; | ||
| 302 | struct page *cur; | ||
| 303 | struct fb_deferred_io *fbdefio = info->fbdefio; | ||
| 304 | int h_inc; | ||
| 305 | u16 yres = info->var.yres; | ||
| 306 | u16 xres = info->var.xres; | ||
| 307 | |||
| 308 | /* height increment is fixed per page */ | ||
| 309 | h_inc = DIV_ROUND_UP(PAGE_SIZE , xres); | ||
| 310 | |||
| 311 | /* walk the written page list and swizzle the data */ | ||
| 312 | list_for_each_entry(cur, &fbdefio->pagelist, lru) { | ||
| 313 | if (prev_index < 0) { | ||
| 314 | /* just starting so assign first page */ | ||
| 315 | y1 = (cur->index << PAGE_SHIFT) / xres; | ||
| 316 | h = h_inc; | ||
| 317 | } else if ((prev_index + 1) == cur->index) { | ||
| 318 | /* this page is consecutive so increase our height */ | ||
| 319 | h += h_inc; | ||
| 320 | } else { | ||
| 321 | /* page not consecutive, issue previous update first */ | ||
| 322 | broadsheetfb_dpy_update_pages(info->par, y1, y1 + h); | ||
| 323 | /* start over with our non consecutive page */ | ||
| 324 | y1 = (cur->index << PAGE_SHIFT) / xres; | ||
| 325 | h = h_inc; | ||
| 326 | } | ||
| 327 | prev_index = cur->index; | ||
| 328 | } | ||
| 329 | |||
| 330 | /* if we still have any pages to update we do so now */ | ||
| 331 | if (h >= yres) { | ||
| 332 | /* its a full screen update, just do it */ | ||
| 333 | broadsheetfb_dpy_update(info->par); | ||
| 334 | } else { | ||
| 335 | broadsheetfb_dpy_update_pages(info->par, y1, | ||
| 336 | min((u16) (y1 + h), yres)); | ||
| 337 | } | ||
| 338 | } | ||
| 339 | |||
| 340 | static void broadsheetfb_fillrect(struct fb_info *info, | ||
| 341 | const struct fb_fillrect *rect) | ||
| 342 | { | ||
| 343 | struct broadsheetfb_par *par = info->par; | ||
| 344 | |||
| 345 | sys_fillrect(info, rect); | ||
| 346 | |||
| 347 | broadsheetfb_dpy_update(par); | ||
| 348 | } | ||
| 349 | |||
| 350 | static void broadsheetfb_copyarea(struct fb_info *info, | ||
| 351 | const struct fb_copyarea *area) | ||
| 352 | { | ||
| 353 | struct broadsheetfb_par *par = info->par; | ||
| 354 | |||
| 355 | sys_copyarea(info, area); | ||
| 356 | |||
| 357 | broadsheetfb_dpy_update(par); | ||
| 358 | } | ||
| 359 | |||
| 360 | static void broadsheetfb_imageblit(struct fb_info *info, | ||
| 361 | const struct fb_image *image) | ||
| 362 | { | ||
| 363 | struct broadsheetfb_par *par = info->par; | ||
| 364 | |||
| 365 | sys_imageblit(info, image); | ||
| 366 | |||
| 367 | broadsheetfb_dpy_update(par); | ||
| 368 | } | ||
| 369 | |||
| 370 | /* | ||
| 371 | * this is the slow path from userspace. they can seek and write to | ||
| 372 | * the fb. it's inefficient to do anything less than a full screen draw | ||
| 373 | */ | ||
| 374 | static ssize_t broadsheetfb_write(struct fb_info *info, const char __user *buf, | ||
| 375 | size_t count, loff_t *ppos) | ||
| 376 | { | ||
| 377 | struct broadsheetfb_par *par = info->par; | ||
| 378 | unsigned long p = *ppos; | ||
| 379 | void *dst; | ||
| 380 | int err = 0; | ||
| 381 | unsigned long total_size; | ||
| 382 | |||
| 383 | if (info->state != FBINFO_STATE_RUNNING) | ||
| 384 | return -EPERM; | ||
| 385 | |||
| 386 | total_size = info->fix.smem_len; | ||
| 387 | |||
| 388 | if (p > total_size) | ||
| 389 | return -EFBIG; | ||
| 390 | |||
| 391 | if (count > total_size) { | ||
| 392 | err = -EFBIG; | ||
| 393 | count = total_size; | ||
| 394 | } | ||
| 395 | |||
| 396 | if (count + p > total_size) { | ||
| 397 | if (!err) | ||
| 398 | err = -ENOSPC; | ||
| 399 | |||
| 400 | count = total_size - p; | ||
| 401 | } | ||
| 402 | |||
| 403 | dst = (void *)(info->screen_base + p); | ||
| 404 | |||
| 405 | if (copy_from_user(dst, buf, count)) | ||
| 406 | err = -EFAULT; | ||
| 407 | |||
| 408 | if (!err) | ||
| 409 | *ppos += count; | ||
| 410 | |||
| 411 | broadsheetfb_dpy_update(par); | ||
| 412 | |||
| 413 | return (err) ? err : count; | ||
| 414 | } | ||
| 415 | |||
| 416 | static struct fb_ops broadsheetfb_ops = { | ||
| 417 | .owner = THIS_MODULE, | ||
| 418 | .fb_read = fb_sys_read, | ||
| 419 | .fb_write = broadsheetfb_write, | ||
| 420 | .fb_fillrect = broadsheetfb_fillrect, | ||
| 421 | .fb_copyarea = broadsheetfb_copyarea, | ||
| 422 | .fb_imageblit = broadsheetfb_imageblit, | ||
| 423 | }; | ||
| 424 | |||
| 425 | static struct fb_deferred_io broadsheetfb_defio = { | ||
| 426 | .delay = HZ/4, | ||
| 427 | .deferred_io = broadsheetfb_dpy_deferred_io, | ||
| 428 | }; | ||
| 429 | |||
| 430 | static int __devinit broadsheetfb_probe(struct platform_device *dev) | ||
| 431 | { | ||
| 432 | struct fb_info *info; | ||
| 433 | struct broadsheet_board *board; | ||
| 434 | int retval = -ENOMEM; | ||
| 435 | int videomemorysize; | ||
| 436 | unsigned char *videomemory; | ||
| 437 | struct broadsheetfb_par *par; | ||
| 438 | int i; | ||
| 439 | |||
| 440 | /* pick up board specific routines */ | ||
| 441 | board = dev->dev.platform_data; | ||
| 442 | if (!board) | ||
| 443 | return -EINVAL; | ||
| 444 | |||
| 445 | /* try to count device specific driver, if can't, platform recalls */ | ||
| 446 | if (!try_module_get(board->owner)) | ||
| 447 | return -ENODEV; | ||
| 448 | |||
| 449 | info = framebuffer_alloc(sizeof(struct broadsheetfb_par), &dev->dev); | ||
| 450 | if (!info) | ||
| 451 | goto err; | ||
| 452 | |||
| 453 | videomemorysize = (DPY_W*DPY_H); | ||
| 454 | videomemory = vmalloc(videomemorysize); | ||
| 455 | if (!videomemory) | ||
| 456 | goto err_fb_rel; | ||
| 457 | |||
| 458 | memset(videomemory, 0, videomemorysize); | ||
| 459 | |||
| 460 | info->screen_base = (char *)videomemory; | ||
| 461 | info->fbops = &broadsheetfb_ops; | ||
| 462 | |||
| 463 | info->var = broadsheetfb_var; | ||
| 464 | info->fix = broadsheetfb_fix; | ||
| 465 | info->fix.smem_len = videomemorysize; | ||
| 466 | par = info->par; | ||
| 467 | par->info = info; | ||
| 468 | par->board = board; | ||
| 469 | par->write_reg = broadsheet_write_reg; | ||
| 470 | par->read_reg = broadsheet_read_reg; | ||
| 471 | init_waitqueue_head(&par->waitq); | ||
| 472 | |||
| 473 | info->flags = FBINFO_FLAG_DEFAULT; | ||
| 474 | |||
| 475 | info->fbdefio = &broadsheetfb_defio; | ||
| 476 | fb_deferred_io_init(info); | ||
| 477 | |||
| 478 | retval = fb_alloc_cmap(&info->cmap, 16, 0); | ||
| 479 | if (retval < 0) { | ||
| 480 | dev_err(&dev->dev, "Failed to allocate colormap\n"); | ||
| 481 | goto err_vfree; | ||
| 482 | } | ||
| 483 | |||
| 484 | /* set cmap */ | ||
| 485 | for (i = 0; i < 16; i++) | ||
| 486 | info->cmap.red[i] = (((2*i)+1)*(0xFFFF))/32; | ||
| 487 | memcpy(info->cmap.green, info->cmap.red, sizeof(u16)*16); | ||
| 488 | memcpy(info->cmap.blue, info->cmap.red, sizeof(u16)*16); | ||
| 489 | |||
| 490 | retval = par->board->setup_irq(info); | ||
| 491 | if (retval < 0) | ||
| 492 | goto err_cmap; | ||
| 493 | |||
| 494 | /* this inits the dpy */ | ||
| 495 | retval = board->init(par); | ||
| 496 | if (retval < 0) | ||
| 497 | goto err_free_irq; | ||
| 498 | |||
| 499 | broadsheet_init(par); | ||
| 500 | |||
| 501 | retval = register_framebuffer(info); | ||
| 502 | if (retval < 0) | ||
| 503 | goto err_free_irq; | ||
| 504 | platform_set_drvdata(dev, info); | ||
| 505 | |||
| 506 | printk(KERN_INFO | ||
| 507 | "fb%d: Broadsheet frame buffer, using %dK of video memory\n", | ||
| 508 | info->node, videomemorysize >> 10); | ||
| 509 | |||
| 510 | |||
| 511 | return 0; | ||
| 512 | |||
| 513 | err_free_irq: | ||
| 514 | board->cleanup(par); | ||
| 515 | err_cmap: | ||
| 516 | fb_dealloc_cmap(&info->cmap); | ||
| 517 | err_vfree: | ||
| 518 | vfree(videomemory); | ||
| 519 | err_fb_rel: | ||
| 520 | framebuffer_release(info); | ||
| 521 | err: | ||
| 522 | module_put(board->owner); | ||
| 523 | return retval; | ||
| 524 | |||
| 525 | } | ||
| 526 | |||
| 527 | static int __devexit broadsheetfb_remove(struct platform_device *dev) | ||
| 528 | { | ||
| 529 | struct fb_info *info = platform_get_drvdata(dev); | ||
| 530 | |||
| 531 | if (info) { | ||
| 532 | struct broadsheetfb_par *par = info->par; | ||
| 533 | unregister_framebuffer(info); | ||
| 534 | fb_deferred_io_cleanup(info); | ||
| 535 | par->board->cleanup(par); | ||
| 536 | fb_dealloc_cmap(&info->cmap); | ||
| 537 | vfree((void *)info->screen_base); | ||
| 538 | module_put(par->board->owner); | ||
| 539 | framebuffer_release(info); | ||
| 540 | } | ||
| 541 | return 0; | ||
| 542 | } | ||
| 543 | |||
| 544 | static struct platform_driver broadsheetfb_driver = { | ||
| 545 | .probe = broadsheetfb_probe, | ||
| 546 | .remove = broadsheetfb_remove, | ||
| 547 | .driver = { | ||
| 548 | .owner = THIS_MODULE, | ||
| 549 | .name = "broadsheetfb", | ||
| 550 | }, | ||
| 551 | }; | ||
| 552 | |||
| 553 | static int __init broadsheetfb_init(void) | ||
| 554 | { | ||
| 555 | return platform_driver_register(&broadsheetfb_driver); | ||
| 556 | } | ||
| 557 | |||
| 558 | static void __exit broadsheetfb_exit(void) | ||
| 559 | { | ||
| 560 | platform_driver_unregister(&broadsheetfb_driver); | ||
| 561 | } | ||
| 562 | |||
| 563 | module_init(broadsheetfb_init); | ||
| 564 | module_exit(broadsheetfb_exit); | ||
| 565 | |||
| 566 | MODULE_DESCRIPTION("fbdev driver for Broadsheet controller"); | ||
| 567 | MODULE_AUTHOR("Jaya Kumar"); | ||
| 568 | MODULE_LICENSE("GPL"); | ||
diff --git a/drivers/video/cyber2000fb.c b/drivers/video/cyber2000fb.c index 7a9e42e3a9a9..83c5cefc266c 100644 --- a/drivers/video/cyber2000fb.c +++ b/drivers/video/cyber2000fb.c | |||
| @@ -46,8 +46,8 @@ | |||
| 46 | #include <linux/fb.h> | 46 | #include <linux/fb.h> |
| 47 | #include <linux/pci.h> | 47 | #include <linux/pci.h> |
| 48 | #include <linux/init.h> | 48 | #include <linux/init.h> |
| 49 | #include <linux/io.h> | ||
| 49 | 50 | ||
| 50 | #include <asm/io.h> | ||
| 51 | #include <asm/pgtable.h> | 51 | #include <asm/pgtable.h> |
| 52 | #include <asm/system.h> | 52 | #include <asm/system.h> |
| 53 | 53 | ||
| @@ -1425,7 +1425,7 @@ static void cyberpro_common_resume(struct cfb_info *cfb) | |||
| 1425 | 1425 | ||
| 1426 | #ifdef CONFIG_ARCH_SHARK | 1426 | #ifdef CONFIG_ARCH_SHARK |
| 1427 | 1427 | ||
| 1428 | #include <mach/hardware.h> | 1428 | #include <mach/framebuffer.h> |
| 1429 | 1429 | ||
| 1430 | static int __devinit cyberpro_vl_probe(void) | 1430 | static int __devinit cyberpro_vl_probe(void) |
| 1431 | { | 1431 | { |
diff --git a/drivers/video/i810/i810_main.c b/drivers/video/i810/i810_main.c index a24e680d2b9c..2e940199fc89 100644 --- a/drivers/video/i810/i810_main.c +++ b/drivers/video/i810/i810_main.c | |||
| @@ -993,6 +993,7 @@ static int i810_check_params(struct fb_var_screeninfo *var, | |||
| 993 | struct i810fb_par *par = info->par; | 993 | struct i810fb_par *par = info->par; |
| 994 | int line_length, vidmem, mode_valid = 0, retval = 0; | 994 | int line_length, vidmem, mode_valid = 0, retval = 0; |
| 995 | u32 vyres = var->yres_virtual, vxres = var->xres_virtual; | 995 | u32 vyres = var->yres_virtual, vxres = var->xres_virtual; |
| 996 | |||
| 996 | /* | 997 | /* |
| 997 | * Memory limit | 998 | * Memory limit |
| 998 | */ | 999 | */ |
| @@ -1002,12 +1003,12 @@ static int i810_check_params(struct fb_var_screeninfo *var, | |||
| 1002 | if (vidmem > par->fb.size) { | 1003 | if (vidmem > par->fb.size) { |
| 1003 | vyres = par->fb.size/line_length; | 1004 | vyres = par->fb.size/line_length; |
| 1004 | if (vyres < var->yres) { | 1005 | if (vyres < var->yres) { |
| 1005 | vyres = yres; | 1006 | vyres = info->var.yres; |
| 1006 | vxres = par->fb.size/vyres; | 1007 | vxres = par->fb.size/vyres; |
| 1007 | vxres /= var->bits_per_pixel >> 3; | 1008 | vxres /= var->bits_per_pixel >> 3; |
| 1008 | line_length = get_line_length(par, vxres, | 1009 | line_length = get_line_length(par, vxres, |
| 1009 | var->bits_per_pixel); | 1010 | var->bits_per_pixel); |
| 1010 | vidmem = line_length * yres; | 1011 | vidmem = line_length * info->var.yres; |
| 1011 | if (vxres < var->xres) { | 1012 | if (vxres < var->xres) { |
| 1012 | printk("i810fb: required video memory, " | 1013 | printk("i810fb: required video memory, " |
| 1013 | "%d bytes, for %dx%d-%d (virtual) " | 1014 | "%d bytes, for %dx%d-%d (virtual) " |
diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c index d58c68cd456e..bd1cb75cd14b 100644 --- a/drivers/video/imxfb.c +++ b/drivers/video/imxfb.c | |||
| @@ -14,7 +14,6 @@ | |||
| 14 | * linux-arm-kernel@lists.arm.linux.org.uk | 14 | * linux-arm-kernel@lists.arm.linux.org.uk |
| 15 | */ | 15 | */ |
| 16 | 16 | ||
| 17 | |||
| 18 | #include <linux/module.h> | 17 | #include <linux/module.h> |
| 19 | #include <linux/kernel.h> | 18 | #include <linux/kernel.h> |
| 20 | #include <linux/errno.h> | 19 | #include <linux/errno.h> |
| @@ -44,7 +43,12 @@ | |||
| 44 | 43 | ||
| 45 | #define LCDC_SIZE 0x04 | 44 | #define LCDC_SIZE 0x04 |
| 46 | #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) | 45 | #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) |
| 46 | |||
| 47 | #ifdef CONFIG_ARCH_MX1 | ||
| 47 | #define SIZE_YMAX(y) ((y) & 0x1ff) | 48 | #define SIZE_YMAX(y) ((y) & 0x1ff) |
| 49 | #else | ||
| 50 | #define SIZE_YMAX(y) ((y) & 0x3ff) | ||
| 51 | #endif | ||
| 48 | 52 | ||
| 49 | #define LCDC_VPW 0x08 | 53 | #define LCDC_VPW 0x08 |
| 50 | #define VPW_VPW(x) ((x) & 0x3ff) | 54 | #define VPW_VPW(x) ((x) & 0x3ff) |
| @@ -54,7 +58,12 @@ | |||
| 54 | #define CPOS_CC0 (1<<30) | 58 | #define CPOS_CC0 (1<<30) |
| 55 | #define CPOS_OP (1<<28) | 59 | #define CPOS_OP (1<<28) |
| 56 | #define CPOS_CXP(x) (((x) & 3ff) << 16) | 60 | #define CPOS_CXP(x) (((x) & 3ff) << 16) |
| 61 | |||
| 62 | #ifdef CONFIG_ARCH_MX1 | ||
| 57 | #define CPOS_CYP(y) ((y) & 0x1ff) | 63 | #define CPOS_CYP(y) ((y) & 0x1ff) |
| 64 | #else | ||
| 65 | #define CPOS_CYP(y) ((y) & 0x3ff) | ||
| 66 | #endif | ||
| 58 | 67 | ||
| 59 | #define LCDC_LCWHB 0x10 | 68 | #define LCDC_LCWHB 0x10 |
| 60 | #define LCWHB_BK_EN (1<<31) | 69 | #define LCWHB_BK_EN (1<<31) |
| @@ -63,9 +72,16 @@ | |||
| 63 | #define LCWHB_BD(x) ((x) & 0xff) | 72 | #define LCWHB_BD(x) ((x) & 0xff) |
| 64 | 73 | ||
| 65 | #define LCDC_LCHCC 0x14 | 74 | #define LCDC_LCHCC 0x14 |
| 75 | |||
| 76 | #ifdef CONFIG_ARCH_MX1 | ||
| 66 | #define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) | 77 | #define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) |
| 67 | #define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) | 78 | #define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) |
| 68 | #define LCHCC_CUR_COL_B(b) ((b) & 0x1f) | 79 | #define LCHCC_CUR_COL_B(b) ((b) & 0x1f) |
| 80 | #else | ||
| 81 | #define LCHCC_CUR_COL_R(r) (((r) & 0x3f) << 12) | ||
| 82 | #define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 6) | ||
| 83 | #define LCHCC_CUR_COL_B(b) ((b) & 0x3f) | ||
| 84 | #endif | ||
| 69 | 85 | ||
| 70 | #define LCDC_PCR 0x18 | 86 | #define LCDC_PCR 0x18 |
| 71 | 87 | ||
| @@ -92,7 +108,13 @@ | |||
| 92 | /* bit fields in imxfb.h */ | 108 | /* bit fields in imxfb.h */ |
| 93 | 109 | ||
| 94 | #define LCDC_RMCR 0x34 | 110 | #define LCDC_RMCR 0x34 |
| 111 | |||
| 112 | #ifdef CONFIG_ARCH_MX1 | ||
| 95 | #define RMCR_LCDC_EN (1<<1) | 113 | #define RMCR_LCDC_EN (1<<1) |
| 114 | #else | ||
| 115 | #define RMCR_LCDC_EN 0 | ||
| 116 | #endif | ||
| 117 | |||
| 96 | #define RMCR_SELF_REF (1<<0) | 118 | #define RMCR_SELF_REF (1<<0) |
| 97 | 119 | ||
| 98 | #define LCDC_LCDICR 0x38 | 120 | #define LCDC_LCDICR 0x38 |
| @@ -159,6 +181,17 @@ struct imxfb_info { | |||
| 159 | #define MIN_XRES 64 | 181 | #define MIN_XRES 64 |
| 160 | #define MIN_YRES 64 | 182 | #define MIN_YRES 64 |
| 161 | 183 | ||
| 184 | /* Actually this really is 18bit support, the lowest 2 bits of each colour | ||
| 185 | * are unused in hardware. We claim to have 24bit support to make software | ||
| 186 | * like X work, which does not support 18bit. | ||
| 187 | */ | ||
| 188 | static struct imxfb_rgb def_rgb_18 = { | ||
| 189 | .red = {.offset = 16, .length = 8,}, | ||
| 190 | .green = {.offset = 8, .length = 8,}, | ||
| 191 | .blue = {.offset = 0, .length = 8,}, | ||
| 192 | .transp = {.offset = 0, .length = 0,}, | ||
| 193 | }; | ||
| 194 | |||
| 162 | static struct imxfb_rgb def_rgb_16_tft = { | 195 | static struct imxfb_rgb def_rgb_16_tft = { |
| 163 | .red = {.offset = 11, .length = 5,}, | 196 | .red = {.offset = 11, .length = 5,}, |
| 164 | .green = {.offset = 5, .length = 6,}, | 197 | .green = {.offset = 5, .length = 6,}, |
| @@ -286,6 +319,9 @@ static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |||
| 286 | 319 | ||
| 287 | pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel); | 320 | pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel); |
| 288 | switch (var->bits_per_pixel) { | 321 | switch (var->bits_per_pixel) { |
| 322 | case 32: | ||
| 323 | rgb = &def_rgb_18; | ||
| 324 | break; | ||
| 289 | case 16: | 325 | case 16: |
| 290 | default: | 326 | default: |
| 291 | if (readl(fbi->regs + LCDC_PCR) & PCR_TFT) | 327 | if (readl(fbi->regs + LCDC_PCR) & PCR_TFT) |
| @@ -327,9 +363,7 @@ static int imxfb_set_par(struct fb_info *info) | |||
| 327 | struct imxfb_info *fbi = info->par; | 363 | struct imxfb_info *fbi = info->par; |
| 328 | struct fb_var_screeninfo *var = &info->var; | 364 | struct fb_var_screeninfo *var = &info->var; |
| 329 | 365 | ||
| 330 | pr_debug("set_par\n"); | 366 | if (var->bits_per_pixel == 16 || var->bits_per_pixel == 32) |
| 331 | |||
| 332 | if (var->bits_per_pixel == 16) | ||
| 333 | info->fix.visual = FB_VISUAL_TRUECOLOR; | 367 | info->fix.visual = FB_VISUAL_TRUECOLOR; |
| 334 | else if (!fbi->cmap_static) | 368 | else if (!fbi->cmap_static) |
| 335 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; | 369 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; |
| @@ -354,10 +388,6 @@ static void imxfb_enable_controller(struct imxfb_info *fbi) | |||
| 354 | { | 388 | { |
| 355 | pr_debug("Enabling LCD controller\n"); | 389 | pr_debug("Enabling LCD controller\n"); |
| 356 | 390 | ||
| 357 | /* initialize LCDC */ | ||
| 358 | writel(readl(fbi->regs + LCDC_RMCR) & ~RMCR_LCDC_EN, | ||
| 359 | fbi->regs + LCDC_RMCR); /* just to be safe... */ | ||
| 360 | |||
| 361 | writel(fbi->screen_dma, fbi->regs + LCDC_SSA); | 391 | writel(fbi->screen_dma, fbi->regs + LCDC_SSA); |
| 362 | 392 | ||
| 363 | /* physical screen start address */ | 393 | /* physical screen start address */ |
| @@ -465,9 +495,9 @@ static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *inf | |||
| 465 | info->fix.id, var->lower_margin); | 495 | info->fix.id, var->lower_margin); |
| 466 | #endif | 496 | #endif |
| 467 | 497 | ||
| 468 | writel(HCR_H_WIDTH(var->hsync_len) | | 498 | writel(HCR_H_WIDTH(var->hsync_len - 1) | |
| 469 | HCR_H_WAIT_1(var->right_margin) | | 499 | HCR_H_WAIT_1(var->right_margin - 1) | |
| 470 | HCR_H_WAIT_2(var->left_margin), | 500 | HCR_H_WAIT_2(var->left_margin - 3), |
| 471 | fbi->regs + LCDC_HCR); | 501 | fbi->regs + LCDC_HCR); |
| 472 | 502 | ||
| 473 | writel(VCR_V_WIDTH(var->vsync_len) | | 503 | writel(VCR_V_WIDTH(var->vsync_len) | |
| @@ -650,6 +680,12 @@ static int __init imxfb_probe(struct platform_device *pdev) | |||
| 650 | info->fix.smem_start = fbi->screen_dma; | 680 | info->fix.smem_start = fbi->screen_dma; |
| 651 | } | 681 | } |
| 652 | 682 | ||
| 683 | if (pdata->init) { | ||
| 684 | ret = pdata->init(fbi->pdev); | ||
| 685 | if (ret) | ||
| 686 | goto failed_platform_init; | ||
| 687 | } | ||
| 688 | |||
| 653 | /* | 689 | /* |
| 654 | * This makes sure that our colour bitfield | 690 | * This makes sure that our colour bitfield |
| 655 | * descriptors are correctly initialised. | 691 | * descriptors are correctly initialised. |
| @@ -674,6 +710,9 @@ static int __init imxfb_probe(struct platform_device *pdev) | |||
| 674 | failed_register: | 710 | failed_register: |
| 675 | fb_dealloc_cmap(&info->cmap); | 711 | fb_dealloc_cmap(&info->cmap); |
| 676 | failed_cmap: | 712 | failed_cmap: |
| 713 | if (pdata->exit) | ||
| 714 | pdata->exit(fbi->pdev); | ||
| 715 | failed_platform_init: | ||
| 677 | if (!pdata->fixed_screen_cpu) | 716 | if (!pdata->fixed_screen_cpu) |
| 678 | dma_free_writecombine(&pdev->dev,fbi->map_size,fbi->map_cpu, | 717 | dma_free_writecombine(&pdev->dev,fbi->map_size,fbi->map_cpu, |
| 679 | fbi->map_dma); | 718 | fbi->map_dma); |
| @@ -691,6 +730,7 @@ failed_init: | |||
| 691 | 730 | ||
| 692 | static int __devexit imxfb_remove(struct platform_device *pdev) | 731 | static int __devexit imxfb_remove(struct platform_device *pdev) |
| 693 | { | 732 | { |
| 733 | struct imx_fb_platform_data *pdata; | ||
| 694 | struct fb_info *info = platform_get_drvdata(pdev); | 734 | struct fb_info *info = platform_get_drvdata(pdev); |
| 695 | struct imxfb_info *fbi = info->par; | 735 | struct imxfb_info *fbi = info->par; |
| 696 | struct resource *res; | 736 | struct resource *res; |
| @@ -701,6 +741,10 @@ static int __devexit imxfb_remove(struct platform_device *pdev) | |||
| 701 | 741 | ||
| 702 | unregister_framebuffer(info); | 742 | unregister_framebuffer(info); |
| 703 | 743 | ||
| 744 | pdata = pdev->dev.platform_data; | ||
| 745 | if (pdata->exit) | ||
| 746 | pdata->exit(fbi->pdev); | ||
| 747 | |||
| 704 | fb_dealloc_cmap(&info->cmap); | 748 | fb_dealloc_cmap(&info->cmap); |
| 705 | kfree(info->pseudo_palette); | 749 | kfree(info->pseudo_palette); |
| 706 | framebuffer_release(info); | 750 | framebuffer_release(info); |
diff --git a/drivers/video/logo/logo_linux_clut224.ppm b/drivers/video/logo/logo_linux_clut224.ppm index 3c14e43b82fe..de93ff3fc1ad 100644 --- a/drivers/video/logo/logo_linux_clut224.ppm +++ b/drivers/video/logo/logo_linux_clut224.ppm | |||
| @@ -1,1604 +1,2828 @@ | |||
| 1 | P3 | 1 | P3 |
| 2 | # Standard 224-color Linux logo | 2 | 145 113 |
| 3 | 80 80 | ||
| 4 | 255 | 3 | 255 |
| 5 | 0 0 0 0 0 0 0 0 0 0 0 0 | 4 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 6 | 0 0 0 0 0 0 0 0 0 0 0 0 | 5 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 7 | 0 0 0 0 0 0 0 0 0 0 0 0 | 6 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 8 | 0 0 0 0 0 0 0 0 0 0 0 0 | 7 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 9 | 0 0 0 0 0 0 0 0 0 0 0 0 | 8 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 10 | 0 0 0 0 0 0 0 0 0 0 0 0 | 9 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 11 | 0 0 0 0 0 0 0 0 0 0 0 0 | 10 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 12 | 0 0 0 0 0 0 0 0 0 0 0 0 | 11 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 13 | 0 0 0 0 0 0 0 0 0 0 0 0 | 12 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 14 | 6 6 6 6 6 6 10 10 10 10 10 10 | 13 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 15 | 10 10 10 6 6 6 6 6 6 6 6 6 | 14 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 16 | 0 0 0 0 0 0 0 0 0 0 0 0 | 15 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 17 | 0 0 0 0 0 0 0 0 0 0 0 0 | 16 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 18 | 0 0 0 0 0 0 0 0 0 0 0 0 | 17 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 19 | 0 0 0 0 0 0 0 0 0 0 0 0 | 18 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 20 | 0 0 0 0 0 0 0 0 0 0 0 0 | 19 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 21 | 0 0 0 0 0 0 0 0 0 0 0 0 | 20 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 22 | 0 0 0 0 0 0 0 0 0 0 0 0 | 21 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 23 | 0 0 0 0 0 0 0 0 0 0 0 0 | 22 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 24 | 0 0 0 0 0 0 0 0 0 0 0 0 | 23 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 25 | 0 0 0 0 0 0 0 0 0 0 0 0 | 24 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 26 | 0 0 0 0 0 0 0 0 0 0 0 0 | 25 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 27 | 0 0 0 0 0 0 0 0 0 0 0 0 | 26 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 28 | 0 0 0 0 0 0 0 0 0 0 0 0 | 27 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 29 | 0 0 0 0 0 0 0 0 0 0 0 0 | 28 | 0 0 0 |
| 30 | 0 0 0 0 0 0 0 0 0 0 0 0 | 29 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 31 | 0 0 0 0 0 0 0 0 0 0 0 0 | 30 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 32 | 0 0 0 0 0 0 0 0 0 0 0 0 | 31 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 33 | 0 0 0 6 6 6 10 10 10 14 14 14 | 32 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 34 | 22 22 22 26 26 26 30 30 30 34 34 34 | 33 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 35 | 30 30 30 30 30 30 26 26 26 18 18 18 | 34 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 36 | 14 14 14 10 10 10 6 6 6 0 0 0 | 35 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 37 | 0 0 0 0 0 0 0 0 0 0 0 0 | 36 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 38 | 0 0 0 0 0 0 0 0 0 0 0 0 | 37 | 0 0 0 0 0 0 0 0 0 0 0 0 3 4 4 6 7 7 |
| 39 | 0 0 0 0 0 0 0 0 0 0 0 0 | 38 | 8 10 10 8 10 10 6 8 8 6 7 7 3 4 4 2 2 2 |
| 40 | 0 0 0 0 0 0 0 0 0 0 0 0 | 39 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 41 | 0 0 0 0 0 0 0 0 0 0 0 0 | 40 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 42 | 0 0 0 0 0 0 0 0 0 0 0 0 | 41 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 43 | 0 0 0 0 0 0 0 0 0 0 0 0 | 42 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 44 | 0 0 0 0 0 0 0 0 0 0 0 0 | 43 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 45 | 0 0 0 0 0 0 0 0 0 0 0 0 | 44 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 46 | 0 0 0 0 0 1 0 0 1 0 0 0 | 45 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 47 | 0 0 0 0 0 0 0 0 0 0 0 0 | 46 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 48 | 0 0 0 0 0 0 0 0 0 0 0 0 | 47 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 49 | 0 0 0 0 0 0 0 0 0 0 0 0 | 48 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 50 | 0 0 0 0 0 0 0 0 0 0 0 0 | 49 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 51 | 0 0 0 0 0 0 0 0 0 0 0 0 | 50 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 52 | 0 0 0 0 0 0 0 0 0 0 0 0 | 51 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 53 | 6 6 6 14 14 14 26 26 26 42 42 42 | 52 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 54 | 54 54 54 66 66 66 78 78 78 78 78 78 | 53 | 0 0 0 |
| 55 | 78 78 78 74 74 74 66 66 66 54 54 54 | 54 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 56 | 42 42 42 26 26 26 18 18 18 10 10 10 | 55 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 57 | 6 6 6 0 0 0 0 0 0 0 0 0 | 56 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 58 | 0 0 0 0 0 0 0 0 0 0 0 0 | 57 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 59 | 0 0 0 0 0 0 0 0 0 0 0 0 | 58 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 60 | 0 0 0 0 0 0 0 0 0 0 0 0 | 59 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 61 | 0 0 0 0 0 0 0 0 0 0 0 0 | 60 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 62 | 0 0 0 0 0 0 0 0 0 0 0 0 | 61 | 0 0 0 0 0 0 0 0 0 0 0 0 4 5 5 17 18 17 |
| 63 | 0 0 0 0 0 0 0 0 0 0 0 0 | 62 | 27 29 28 35 37 36 40 43 41 43 45 43 40 43 41 37 39 37 |
| 64 | 0 0 0 0 0 0 0 0 0 0 0 0 | 63 | 32 34 33 27 30 29 23 25 24 17 21 21 15 18 18 12 15 15 |
| 65 | 0 0 0 0 0 0 0 0 0 0 0 0 | 64 | 11 13 13 8 10 10 6 7 7 3 4 4 1 1 1 0 0 0 |
| 66 | 0 0 1 0 0 0 0 0 0 0 0 0 | 65 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 67 | 0 0 0 0 0 0 0 0 0 0 0 0 | 66 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 68 | 0 0 0 0 0 0 0 0 0 0 0 0 | 67 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 69 | 0 0 0 0 0 0 0 0 0 0 0 0 | 68 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 70 | 0 0 0 0 0 0 0 0 0 0 0 0 | 69 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 71 | 0 0 0 0 0 0 0 0 0 0 0 0 | 70 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 72 | 0 0 0 0 0 0 0 0 0 10 10 10 | 71 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 73 | 22 22 22 42 42 42 66 66 66 86 86 86 | 72 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 74 | 66 66 66 38 38 38 38 38 38 22 22 22 | 73 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 75 | 26 26 26 34 34 34 54 54 54 66 66 66 | 74 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 76 | 86 86 86 70 70 70 46 46 46 26 26 26 | 75 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 77 | 14 14 14 6 6 6 0 0 0 0 0 0 | 76 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 78 | 0 0 0 0 0 0 0 0 0 0 0 0 | 77 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 79 | 0 0 0 0 0 0 0 0 0 0 0 0 | 78 | 0 0 0 |
| 80 | 0 0 0 0 0 0 0 0 0 0 0 0 | 79 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 81 | 0 0 0 0 0 0 0 0 0 0 0 0 | 80 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 82 | 0 0 0 0 0 0 0 0 0 0 0 0 | 81 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 83 | 0 0 0 0 0 0 0 0 0 0 0 0 | 82 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 84 | 0 0 0 0 0 0 0 0 0 0 0 0 | 83 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 85 | 0 0 0 0 0 0 0 0 0 0 0 0 | 84 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 86 | 0 0 1 0 0 1 0 0 1 0 0 0 | 85 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 87 | 0 0 0 0 0 0 0 0 0 0 0 0 | 86 | 0 0 0 13 13 13 32 34 33 49 51 48 60 60 56 58 59 55 |
| 88 | 0 0 0 0 0 0 0 0 0 0 0 0 | 87 | 55 57 54 55 56 53 49 51 48 43 45 43 39 40 39 33 37 35 |
| 89 | 0 0 0 0 0 0 0 0 0 0 0 0 | 88 | 28 31 30 23 27 26 20 23 23 17 20 20 14 17 17 13 16 16 |
| 90 | 0 0 0 0 0 0 0 0 0 0 0 0 | 89 | 11 14 14 10 13 13 10 12 12 9 11 11 8 10 10 6 7 7 |
| 91 | 0 0 0 0 0 0 0 0 0 0 0 0 | 90 | 2 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 92 | 0 0 0 0 0 0 10 10 10 26 26 26 | 91 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 93 | 50 50 50 82 82 82 58 58 58 6 6 6 | 92 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 94 | 2 2 6 2 2 6 2 2 6 2 2 6 | 93 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 95 | 2 2 6 2 2 6 2 2 6 2 2 6 | 94 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 96 | 6 6 6 54 54 54 86 86 86 66 66 66 | 95 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 97 | 38 38 38 18 18 18 6 6 6 0 0 0 | 96 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 98 | 0 0 0 0 0 0 0 0 0 0 0 0 | 97 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 99 | 0 0 0 0 0 0 0 0 0 0 0 0 | 98 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 100 | 0 0 0 0 0 0 0 0 0 0 0 0 | 99 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 101 | 0 0 0 0 0 0 0 0 0 0 0 0 | 100 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 102 | 0 0 0 0 0 0 0 0 0 0 0 0 | 101 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 103 | 0 0 0 0 0 0 0 0 0 0 0 0 | 102 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 104 | 0 0 0 0 0 0 0 0 0 0 0 0 | 103 | 0 0 0 |
| 105 | 0 0 0 0 0 0 0 0 0 0 0 0 | 104 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 106 | 0 0 0 0 0 0 0 0 0 0 0 0 | 105 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 107 | 0 0 0 0 0 0 0 0 0 0 0 0 | 106 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 108 | 0 0 0 0 0 0 0 0 0 0 0 0 | 107 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 109 | 0 0 0 0 0 0 0 0 0 0 0 0 | 108 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 110 | 0 0 0 0 0 0 0 0 0 0 0 0 | 109 | 0 0 0 0 0 0 0 0 0 0 0 0 6 7 7 12 15 15 |
| 111 | 0 0 0 0 0 0 0 0 0 0 0 0 | 110 | 12 15 15 8 9 9 2 3 3 0 0 0 1 1 1 25 27 26 |
| 112 | 0 0 0 6 6 6 22 22 22 50 50 50 | 111 | 55 56 53 68 70 65 65 66 61 65 66 61 63 64 60 63 64 60 |
| 113 | 78 78 78 34 34 34 2 2 6 2 2 6 | 112 | 58 59 55 51 52 50 47 48 46 41 42 42 35 37 36 30 32 31 |
| 114 | 2 2 6 2 2 6 2 2 6 2 2 6 | 113 | 26 28 27 20 24 24 18 22 22 16 19 19 14 17 17 13 16 16 |
| 115 | 2 2 6 2 2 6 2 2 6 2 2 6 | 114 | 12 15 15 11 14 14 10 13 13 10 12 12 9 11 11 8 10 10 |
| 116 | 2 2 6 2 2 6 6 6 6 70 70 70 | 115 | 8 9 9 6 8 8 3 3 3 0 0 0 0 0 0 0 0 0 |
| 117 | 78 78 78 46 46 46 22 22 22 6 6 6 | 116 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 118 | 0 0 0 0 0 0 0 0 0 0 0 0 | 117 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 119 | 0 0 0 0 0 0 0 0 0 0 0 0 | 118 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 120 | 0 0 0 0 0 0 0 0 0 0 0 0 | 119 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 121 | 0 0 0 0 0 0 0 0 0 0 0 0 | 120 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 122 | 0 0 0 0 0 0 0 0 0 0 0 0 | 121 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 123 | 0 0 0 0 0 0 0 0 0 0 0 0 | 122 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 124 | 0 0 0 0 0 0 0 0 0 0 0 0 | 123 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 125 | 0 0 0 0 0 0 0 0 0 0 0 0 | 124 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 126 | 0 0 1 0 0 1 0 0 1 0 0 0 | 125 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 127 | 0 0 0 0 0 0 0 0 0 0 0 0 | 126 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 128 | 0 0 0 0 0 0 0 0 0 0 0 0 | 127 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 129 | 0 0 0 0 0 0 0 0 0 0 0 0 | 128 | 0 0 0 |
| 130 | 0 0 0 0 0 0 0 0 0 0 0 0 | 129 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 131 | 0 0 0 0 0 0 0 0 0 0 0 0 | 130 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 132 | 6 6 6 18 18 18 42 42 42 82 82 82 | 131 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 133 | 26 26 26 2 2 6 2 2 6 2 2 6 | 132 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 134 | 2 2 6 2 2 6 2 2 6 2 2 6 | 133 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 135 | 2 2 6 2 2 6 2 2 6 14 14 14 | 134 | 0 0 0 0 0 0 0 0 0 6 7 7 20 24 24 23 27 26 |
| 136 | 46 46 46 34 34 34 6 6 6 2 2 6 | 135 | 23 27 26 18 22 22 11 13 13 23 24 24 61 63 57 72 73 67 |
| 137 | 42 42 42 78 78 78 42 42 42 18 18 18 | 136 | 72 73 67 68 70 65 68 70 65 68 70 65 63 64 60 58 59 55 |
| 138 | 6 6 6 0 0 0 0 0 0 0 0 0 | 137 | 55 56 53 47 48 46 41 42 42 35 37 36 30 32 31 26 28 27 |
| 139 | 0 0 0 0 0 0 0 0 0 0 0 0 | 138 | 20 24 24 18 22 22 16 20 20 15 19 19 14 17 17 13 16 16 |
| 140 | 0 0 0 0 0 0 0 0 0 0 0 0 | 139 | 12 15 15 12 15 15 11 14 14 10 13 13 10 12 12 9 11 11 |
| 141 | 0 0 0 0 0 0 0 0 0 0 0 0 | 140 | 8 10 10 8 9 9 7 9 9 6 7 7 1 2 2 0 0 0 |
| 142 | 0 0 0 0 0 0 0 0 0 0 0 0 | 141 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 143 | 0 0 0 0 0 0 0 0 0 0 0 0 | 142 | 0 0 0 0 0 0 1 1 1 4 5 5 5 6 5 4 5 5 |
| 144 | 0 0 0 0 0 0 0 0 0 0 0 0 | 143 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 145 | 0 0 0 0 0 0 0 0 0 0 0 0 | 144 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 146 | 0 0 1 0 0 0 0 0 1 0 0 0 | 145 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 147 | 0 0 0 0 0 0 0 0 0 0 0 0 | 146 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 148 | 0 0 0 0 0 0 0 0 0 0 0 0 | 147 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 149 | 0 0 0 0 0 0 0 0 0 0 0 0 | 148 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 150 | 0 0 0 0 0 0 0 0 0 0 0 0 | 149 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 151 | 0 0 0 0 0 0 0 0 0 0 0 0 | 150 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 152 | 10 10 10 30 30 30 66 66 66 58 58 58 | 151 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 153 | 2 2 6 2 2 6 2 2 6 2 2 6 | 152 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 154 | 2 2 6 2 2 6 2 2 6 2 2 6 | 153 | 0 0 0 |
| 155 | 2 2 6 2 2 6 2 2 6 26 26 26 | 154 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 156 | 86 86 86 101 101 101 46 46 46 10 10 10 | 155 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 157 | 2 2 6 58 58 58 70 70 70 34 34 34 | 156 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 158 | 10 10 10 0 0 0 0 0 0 0 0 0 | 157 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 159 | 0 0 0 0 0 0 0 0 0 0 0 0 | 158 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 160 | 0 0 0 0 0 0 0 0 0 0 0 0 | 159 | 0 0 0 0 0 0 0 0 0 15 19 19 40 41 39 53 55 47 |
| 161 | 0 0 0 0 0 0 0 0 0 0 0 0 | 160 | 33 36 34 27 30 29 51 52 50 72 73 67 72 73 67 72 73 67 |
| 162 | 0 0 0 0 0 0 0 0 0 0 0 0 | 161 | 72 73 67 68 70 65 68 70 65 63 64 60 58 59 55 51 52 50 |
| 163 | 0 0 0 0 0 0 0 0 0 0 0 0 | 162 | 47 48 46 40 43 41 33 37 35 30 32 31 26 28 27 20 24 24 |
| 164 | 0 0 0 0 0 0 0 0 0 0 0 0 | 163 | 18 22 22 17 21 21 16 19 19 14 18 18 14 17 17 13 17 17 |
| 165 | 0 0 0 0 0 0 0 0 0 0 0 0 | 164 | 13 16 16 12 15 15 12 15 15 11 14 14 10 13 13 10 12 12 |
| 166 | 0 0 1 0 0 1 0 0 1 0 0 0 | 165 | 9 11 11 8 10 10 8 9 9 7 9 9 6 8 8 3 4 4 |
| 167 | 0 0 0 0 0 0 0 0 0 0 0 0 | 166 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 168 | 0 0 0 0 0 0 0 0 0 0 0 0 | 167 | 2 2 2 6 8 8 10 12 12 10 12 12 10 12 12 10 12 12 |
| 169 | 0 0 0 0 0 0 0 0 0 0 0 0 | 168 | 6 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 170 | 0 0 0 0 0 0 0 0 0 0 0 0 | 169 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 171 | 0 0 0 0 0 0 0 0 0 0 0 0 | 170 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 172 | 14 14 14 42 42 42 86 86 86 10 10 10 | 171 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 173 | 2 2 6 2 2 6 2 2 6 2 2 6 | 172 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 174 | 2 2 6 2 2 6 2 2 6 2 2 6 | 173 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 175 | 2 2 6 2 2 6 2 2 6 30 30 30 | 174 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 176 | 94 94 94 94 94 94 58 58 58 26 26 26 | 175 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 177 | 2 2 6 6 6 6 78 78 78 54 54 54 | 176 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 178 | 22 22 22 6 6 6 0 0 0 0 0 0 | 177 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 179 | 0 0 0 0 0 0 0 0 0 0 0 0 | 178 | 0 0 0 |
| 180 | 0 0 0 0 0 0 0 0 0 0 0 0 | 179 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 181 | 0 0 0 0 0 0 0 0 0 0 0 0 | 180 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 182 | 0 0 0 0 0 0 0 0 0 0 0 0 | 181 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 183 | 0 0 0 0 0 0 0 0 0 0 0 0 | 182 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 184 | 0 0 0 0 0 0 0 0 0 0 0 0 | 183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 185 | 0 0 0 0 0 0 0 0 0 0 0 0 | 184 | 0 0 0 0 0 0 0 0 0 20 23 23 71 71 57 131 127 93 |
| 186 | 0 0 0 0 0 0 0 0 0 0 0 0 | 185 | 115 113 82 63 64 60 72 73 67 72 73 67 72 73 67 72 73 67 |
| 187 | 0 0 0 0 0 0 0 0 0 0 0 0 | 186 | 68 70 65 65 66 61 61 63 57 55 57 54 49 51 48 43 45 43 |
| 188 | 0 0 0 0 0 0 0 0 0 0 0 0 | 187 | 39 40 39 33 36 34 28 31 30 23 27 26 20 24 24 20 23 23 |
| 189 | 0 0 0 0 0 0 0 0 0 0 0 0 | 188 | 17 21 21 16 20 20 15 19 19 15 18 18 14 18 18 14 17 17 |
| 190 | 0 0 0 0 0 0 0 0 0 0 0 0 | 189 | 13 17 17 13 16 16 12 15 15 12 15 15 11 14 14 10 13 13 |
| 191 | 0 0 0 0 0 0 0 0 0 6 6 6 | 190 | 10 12 12 9 11 11 8 10 10 7 9 9 7 9 9 6 8 8 |
| 192 | 22 22 22 62 62 62 62 62 62 2 2 6 | 191 | 4 5 5 0 0 0 0 0 0 0 0 0 1 1 1 6 7 7 |
| 193 | 2 2 6 2 2 6 2 2 6 2 2 6 | 192 | 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 |
| 194 | 2 2 6 2 2 6 2 2 6 2 2 6 | 193 | 10 12 12 3 4 4 0 0 0 0 0 0 0 0 0 0 0 0 |
| 195 | 2 2 6 2 2 6 2 2 6 26 26 26 | 194 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 196 | 54 54 54 38 38 38 18 18 18 10 10 10 | 195 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 197 | 2 2 6 2 2 6 34 34 34 82 82 82 | 196 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 198 | 38 38 38 14 14 14 0 0 0 0 0 0 | 197 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 199 | 0 0 0 0 0 0 0 0 0 0 0 0 | 198 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 200 | 0 0 0 0 0 0 0 0 0 0 0 0 | 199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 201 | 0 0 0 0 0 0 0 0 0 0 0 0 | 200 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 202 | 0 0 0 0 0 0 0 0 0 0 0 0 | 201 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 203 | 0 0 0 0 0 0 0 0 0 0 0 0 | 202 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 204 | 0 0 0 0 0 0 0 0 0 0 0 0 | 203 | 0 0 0 |
| 205 | 0 0 0 0 0 0 0 0 0 0 0 0 | 204 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 206 | 0 0 0 0 0 1 0 0 1 0 0 0 | 205 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 207 | 0 0 0 0 0 0 0 0 0 0 0 0 | 206 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 208 | 0 0 0 0 0 0 0 0 0 0 0 0 | 207 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 209 | 0 0 0 0 0 0 0 0 0 0 0 0 | 208 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 210 | 0 0 0 0 0 0 0 0 0 0 0 0 | 209 | 0 0 0 0 0 0 0 0 0 18 22 22 71 71 57 144 139 99 |
| 211 | 0 0 0 0 0 0 0 0 0 6 6 6 | 210 | 84 83 72 68 70 65 72 73 67 72 73 67 68 70 65 65 66 61 |
| 212 | 30 30 30 78 78 78 30 30 30 2 2 6 | 211 | 63 64 60 55 57 54 51 52 50 47 48 46 40 43 41 35 37 36 |
| 213 | 2 2 6 2 2 6 2 2 6 2 2 6 | 212 | 30 32 31 27 29 28 23 27 26 20 24 24 18 22 22 17 21 21 |
| 214 | 2 2 6 2 2 6 2 2 6 2 2 6 | 213 | 16 20 20 15 19 19 15 19 19 15 19 19 15 18 18 14 18 18 |
| 215 | 2 2 6 2 2 6 2 2 6 10 10 10 | 214 | 14 17 17 13 17 17 13 16 16 12 15 15 12 15 15 11 14 14 |
| 216 | 10 10 10 2 2 6 2 2 6 2 2 6 | 215 | 10 13 13 9 12 12 9 11 11 8 10 10 7 9 9 6 8 8 |
| 217 | 2 2 6 2 2 6 2 2 6 78 78 78 | 216 | 6 8 8 3 4 4 0 0 0 2 2 2 8 10 10 10 12 12 |
| 218 | 50 50 50 18 18 18 6 6 6 0 0 0 | 217 | 10 12 12 10 12 12 11 13 13 36 38 35 61 61 53 48 49 45 |
| 219 | 0 0 0 0 0 0 0 0 0 0 0 0 | 218 | 10 12 12 7 9 9 0 0 0 0 0 0 0 0 0 0 0 0 |
| 220 | 0 0 0 0 0 0 0 0 0 0 0 0 | 219 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 221 | 0 0 0 0 0 0 0 0 0 0 0 0 | 220 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 222 | 0 0 0 0 0 0 0 0 0 0 0 0 | 221 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 223 | 0 0 0 0 0 0 0 0 0 0 0 0 | 222 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 224 | 0 0 0 0 0 0 0 0 0 0 0 0 | 223 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 225 | 0 0 0 0 0 0 0 0 0 0 0 0 | 224 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 226 | 0 0 1 0 0 0 0 0 0 0 0 0 | 225 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 227 | 0 0 0 0 0 0 0 0 0 0 0 0 | 226 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 228 | 0 0 0 0 0 0 0 0 0 0 0 0 | 227 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 229 | 0 0 0 0 0 0 0 0 0 0 0 0 | 228 | 0 0 0 |
| 230 | 0 0 0 0 0 0 0 0 0 0 0 0 | 229 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 231 | 0 0 0 0 0 0 0 0 0 10 10 10 | 230 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 232 | 38 38 38 86 86 86 14 14 14 2 2 6 | 231 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 233 | 2 2 6 2 2 6 2 2 6 2 2 6 | 232 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 234 | 2 2 6 2 2 6 2 2 6 2 2 6 | 233 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 235 | 2 2 6 2 2 6 2 2 6 2 2 6 | 234 | 0 0 0 0 0 0 0 0 0 15 19 19 61 61 53 84 83 72 |
| 236 | 2 2 6 2 2 6 2 2 6 2 2 6 | 235 | 68 70 65 72 73 67 68 70 65 68 70 65 63 64 60 58 59 55 |
| 237 | 2 2 6 2 2 6 2 2 6 54 54 54 | 236 | 51 52 50 47 48 46 41 42 42 37 39 37 32 35 33 28 31 30 |
| 238 | 66 66 66 26 26 26 6 6 6 0 0 0 | 237 | 23 27 26 20 24 24 20 23 23 18 22 22 17 21 21 17 21 21 |
| 239 | 0 0 0 0 0 0 0 0 0 0 0 0 | 238 | 17 21 21 17 21 21 17 20 20 16 20 20 16 20 20 16 19 19 |
| 240 | 0 0 0 0 0 0 0 0 0 0 0 0 | 239 | 15 18 18 14 18 18 13 17 17 13 16 16 12 15 15 12 15 15 |
| 241 | 0 0 0 0 0 0 0 0 0 0 0 0 | 240 | 11 14 14 10 13 13 9 12 12 9 11 11 8 10 10 7 9 9 |
| 242 | 0 0 0 0 0 0 0 0 0 0 0 0 | 241 | 6 8 8 6 8 8 5 6 5 9 11 11 10 12 12 10 12 12 |
| 243 | 0 0 0 0 0 0 0 0 0 0 0 0 | 242 | 19 20 18 82 81 62 149 145 103 160 154 106 142 137 94 96 95 69 |
| 244 | 0 0 0 0 0 0 0 0 0 0 0 0 | 243 | 10 12 12 10 12 12 1 1 1 0 0 0 0 0 0 0 0 0 |
| 245 | 0 0 0 0 0 0 0 0 0 0 0 0 | 244 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 246 | 0 0 0 0 0 1 0 0 1 0 0 0 | 245 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 247 | 0 0 0 0 0 0 0 0 0 0 0 0 | 246 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 248 | 0 0 0 0 0 0 0 0 0 0 0 0 | 247 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 249 | 0 0 0 0 0 0 0 0 0 0 0 0 | 248 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 250 | 0 0 0 0 0 0 0 0 0 0 0 0 | 249 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 251 | 0 0 0 0 0 0 0 0 0 14 14 14 | 250 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 252 | 42 42 42 82 82 82 2 2 6 2 2 6 | 251 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 253 | 2 2 6 6 6 6 10 10 10 2 2 6 | 252 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 254 | 2 2 6 2 2 6 2 2 6 2 2 6 | 253 | 0 0 0 |
| 255 | 2 2 6 2 2 6 2 2 6 6 6 6 | 254 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 256 | 14 14 14 10 10 10 2 2 6 2 2 6 | 255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 257 | 2 2 6 2 2 6 2 2 6 18 18 18 | 256 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 258 | 82 82 82 34 34 34 10 10 10 0 0 0 | 257 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 259 | 0 0 0 0 0 0 0 0 0 0 0 0 | 258 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 260 | 0 0 0 0 0 0 0 0 0 0 0 0 | 259 | 0 0 0 0 0 0 0 0 0 10 12 12 44 46 43 68 70 65 |
| 261 | 0 0 0 0 0 0 0 0 0 0 0 0 | 260 | 72 73 67 68 70 65 68 70 65 63 64 60 55 57 54 49 51 48 |
| 262 | 0 0 0 0 0 0 0 0 0 0 0 0 | 261 | 43 45 43 39 40 39 33 37 35 30 32 31 26 28 27 23 27 26 |
| 263 | 0 0 0 0 0 0 0 0 0 0 0 0 | 262 | 20 24 24 18 22 22 18 22 22 18 22 22 18 22 22 20 23 23 |
| 264 | 0 0 0 0 0 0 0 0 0 0 0 0 | 263 | 20 24 24 23 25 24 23 25 24 22 24 23 20 23 23 18 22 22 |
| 265 | 0 0 0 0 0 0 0 0 0 0 0 0 | 264 | 17 20 20 15 19 19 15 18 18 14 17 17 13 16 16 12 15 15 |
| 266 | 0 0 1 0 0 0 0 0 0 0 0 0 | 265 | 11 14 14 11 13 13 10 12 12 9 11 11 8 10 10 8 9 9 |
| 267 | 0 0 0 0 0 0 0 0 0 0 0 0 | 266 | 7 9 9 7 9 9 10 12 12 10 12 12 10 12 12 71 71 57 |
| 268 | 0 0 0 0 0 0 0 0 0 0 0 0 | 267 | 164 159 111 186 182 128 186 182 128 171 165 117 151 147 98 96 95 69 |
| 269 | 0 0 0 0 0 0 0 0 0 0 0 0 | 268 | 10 12 12 10 12 12 3 3 3 0 0 0 0 0 0 0 0 0 |
| 270 | 0 0 0 0 0 0 0 0 0 0 0 0 | 269 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 271 | 0 0 0 0 0 0 0 0 0 14 14 14 | 270 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 272 | 46 46 46 86 86 86 2 2 6 2 2 6 | 271 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 273 | 6 6 6 6 6 6 22 22 22 34 34 34 | 272 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 274 | 6 6 6 2 2 6 2 2 6 2 2 6 | 273 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 275 | 2 2 6 2 2 6 18 18 18 34 34 34 | 274 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 276 | 10 10 10 50 50 50 22 22 22 2 2 6 | 275 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 277 | 2 2 6 2 2 6 2 2 6 10 10 10 | 276 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 278 | 86 86 86 42 42 42 14 14 14 0 0 0 | 277 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 279 | 0 0 0 0 0 0 0 0 0 0 0 0 | 278 | 0 0 0 |
| 280 | 0 0 0 0 0 0 0 0 0 0 0 0 | 279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 281 | 0 0 0 0 0 0 0 0 0 0 0 0 | 280 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 282 | 0 0 0 0 0 0 0 0 0 0 0 0 | 281 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 283 | 0 0 0 0 0 0 0 0 0 0 0 0 | 282 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 284 | 0 0 0 0 0 0 0 0 0 0 0 0 | 283 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 285 | 0 0 0 0 0 0 0 0 0 0 0 0 | 284 | 0 0 0 0 0 0 0 0 0 8 10 10 63 64 60 68 70 65 |
| 286 | 0 0 1 0 0 1 0 0 1 0 0 0 | 285 | 72 73 67 68 70 65 63 64 60 55 57 54 47 48 46 40 43 41 |
| 287 | 0 0 0 0 0 0 0 0 0 0 0 0 | 286 | 33 37 35 30 32 31 27 29 28 23 27 26 20 24 24 20 23 23 |
| 288 | 0 0 0 0 0 0 0 0 0 0 0 0 | 287 | 18 22 22 18 22 22 20 23 22 21 25 23 23 27 26 27 29 28 |
| 289 | 0 0 0 0 0 0 0 0 0 0 0 0 | 288 | 28 31 30 31 33 31 31 33 31 31 33 31 28 31 30 26 28 27 |
| 290 | 0 0 0 0 0 0 0 0 0 0 0 0 | 289 | 23 25 24 20 23 22 16 20 20 15 18 18 14 17 17 13 16 16 |
| 291 | 0 0 0 0 0 0 0 0 0 14 14 14 | 290 | 12 15 15 11 14 14 10 13 13 10 12 12 9 11 11 8 10 10 |
| 292 | 46 46 46 86 86 86 2 2 6 2 2 6 | 291 | 10 12 12 10 13 13 10 12 12 12 14 14 96 95 69 165 161 109 |
| 293 | 38 38 38 116 116 116 94 94 94 22 22 22 | 292 | 186 182 128 192 187 134 192 187 134 176 171 126 160 154 106 103 101 77 |
| 294 | 22 22 22 2 2 6 2 2 6 2 2 6 | 293 | 10 12 12 10 12 12 5 6 5 0 0 0 0 0 0 0 0 0 |
| 295 | 14 14 14 86 86 86 138 138 138 162 162 162 | 294 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 296 | 154 154 154 38 38 38 26 26 26 6 6 6 | 295 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 297 | 2 2 6 2 2 6 2 2 6 2 2 6 | 296 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 298 | 86 86 86 46 46 46 14 14 14 0 0 0 | 297 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 299 | 0 0 0 0 0 0 0 0 0 0 0 0 | 298 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 300 | 0 0 0 0 0 0 0 0 0 0 0 0 | 299 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 301 | 0 0 0 0 0 0 0 0 0 0 0 0 | 300 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 302 | 0 0 0 0 0 0 0 0 0 0 0 0 | 301 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 303 | 0 0 0 0 0 0 0 0 0 0 0 0 | 302 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 304 | 0 0 0 0 0 0 0 0 0 0 0 0 | 303 | 0 0 0 |
| 305 | 0 0 0 0 0 0 0 0 0 0 0 0 | 304 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 306 | 0 0 0 0 0 0 0 0 0 0 0 0 | 305 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 307 | 0 0 0 0 0 0 0 0 0 0 0 0 | 306 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 308 | 0 0 0 0 0 0 0 0 0 0 0 0 | 307 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 309 | 0 0 0 0 0 0 0 0 0 0 0 0 | 308 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 310 | 0 0 0 0 0 0 0 0 0 0 0 0 | 309 | 0 0 0 0 0 0 0 0 0 35 37 36 68 70 65 72 73 67 |
| 311 | 0 0 0 0 0 0 0 0 0 14 14 14 | 310 | 68 70 65 65 66 61 58 59 55 49 51 48 40 43 41 33 37 35 |
| 312 | 46 46 46 86 86 86 2 2 6 14 14 14 | 311 | 28 31 30 23 27 26 20 24 24 20 23 23 18 22 22 18 22 22 |
| 313 | 134 134 134 198 198 198 195 195 195 116 116 116 | 312 | 18 22 22 20 23 23 23 27 26 27 30 29 32 35 33 37 39 37 |
| 314 | 10 10 10 2 2 6 2 2 6 6 6 6 | 313 | 40 43 41 44 46 43 46 47 43 44 46 43 40 43 41 36 38 35 |
| 315 | 101 98 89 187 187 187 210 210 210 218 218 218 | 314 | 31 33 31 27 29 28 22 24 23 17 21 21 15 18 18 14 17 17 |
| 316 | 214 214 214 134 134 134 14 14 14 6 6 6 | 315 | 13 16 16 12 15 15 11 14 14 11 14 14 11 13 13 13 16 16 |
| 317 | 2 2 6 2 2 6 2 2 6 2 2 6 | 316 | 13 16 16 11 14 14 10 12 12 79 78 62 142 137 94 164 159 111 |
| 318 | 86 86 86 50 50 50 18 18 18 6 6 6 | 317 | 178 174 128 192 187 134 192 187 134 176 171 126 160 154 106 96 95 69 |
| 319 | 0 0 0 0 0 0 0 0 0 0 0 0 | 318 | 10 12 12 10 12 12 6 7 7 0 0 0 0 0 0 0 0 0 |
| 320 | 0 0 0 0 0 0 0 0 0 0 0 0 | 319 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 321 | 0 0 0 0 0 0 0 0 0 0 0 0 | 320 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 322 | 0 0 0 0 0 0 0 0 0 0 0 0 | 321 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 323 | 0 0 0 0 0 0 0 0 0 0 0 0 | 322 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 324 | 0 0 0 0 0 0 0 0 0 0 0 0 | 323 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 325 | 0 0 0 0 0 0 0 0 1 0 0 0 | 324 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 326 | 0 0 1 0 0 1 0 0 1 0 0 0 | 325 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 327 | 0 0 0 0 0 0 0 0 0 0 0 0 | 326 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 328 | 0 0 0 0 0 0 0 0 0 0 0 0 | 327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 329 | 0 0 0 0 0 0 0 0 0 0 0 0 | 328 | 0 0 0 |
| 330 | 0 0 0 0 0 0 0 0 0 0 0 0 | 329 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 331 | 0 0 0 0 0 0 0 0 0 14 14 14 | 330 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 332 | 46 46 46 86 86 86 2 2 6 54 54 54 | 331 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 333 | 218 218 218 195 195 195 226 226 226 246 246 246 | 332 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 334 | 58 58 58 2 2 6 2 2 6 30 30 30 | 333 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 335 | 210 210 210 253 253 253 174 174 174 123 123 123 | 334 | 0 0 0 0 0 0 0 0 0 55 57 54 68 70 65 72 73 67 |
| 336 | 221 221 221 234 234 234 74 74 74 2 2 6 | 335 | 68 70 65 63 64 60 55 56 53 43 45 43 35 37 36 28 31 30 |
| 337 | 2 2 6 2 2 6 2 2 6 2 2 6 | 336 | 23 27 26 20 24 24 18 22 22 17 21 21 17 21 21 17 21 21 |
| 338 | 70 70 70 58 58 58 22 22 22 6 6 6 | 337 | 20 24 24 25 27 26 31 33 31 38 39 37 46 47 43 53 55 47 |
| 339 | 0 0 0 0 0 0 0 0 0 0 0 0 | 338 | 61 61 53 66 65 55 66 65 55 66 65 55 61 61 53 53 55 47 |
| 340 | 0 0 0 0 0 0 0 0 0 0 0 0 | 339 | 46 47 43 37 39 37 30 33 30 24 26 24 17 21 21 15 18 18 |
| 341 | 0 0 0 0 0 0 0 0 0 0 0 0 | 340 | 13 17 17 12 15 15 12 15 15 13 16 16 14 18 18 14 18 18 |
| 342 | 0 0 0 0 0 0 0 0 0 0 0 0 | 341 | 14 17 17 12 15 15 30 31 28 118 116 76 134 131 96 160 154 106 |
| 343 | 0 0 0 0 0 0 0 0 0 0 0 0 | 342 | 174 170 121 178 174 128 178 174 128 171 165 117 151 147 98 96 95 69 |
| 344 | 0 0 0 0 0 0 0 0 0 0 0 0 | 343 | 10 12 12 10 12 12 6 8 8 0 0 0 0 0 0 0 0 0 |
| 345 | 0 0 0 0 0 0 0 0 0 0 0 0 | 344 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 346 | 0 0 0 0 0 0 0 0 0 0 0 0 | 345 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 347 | 0 0 0 0 0 0 0 0 0 0 0 0 | 346 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 348 | 0 0 0 0 0 0 0 0 0 0 0 0 | 347 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 349 | 0 0 0 0 0 0 0 0 0 0 0 0 | 348 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 350 | 0 0 0 0 0 0 0 0 0 0 0 0 | 349 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 351 | 0 0 0 0 0 0 0 0 0 14 14 14 | 350 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 352 | 46 46 46 82 82 82 2 2 6 106 106 106 | 351 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 353 | 170 170 170 26 26 26 86 86 86 226 226 226 | 352 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 354 | 123 123 123 10 10 10 14 14 14 46 46 46 | 353 | 0 0 0 |
| 355 | 231 231 231 190 190 190 6 6 6 70 70 70 | 354 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 356 | 90 90 90 238 238 238 158 158 158 2 2 6 | 355 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 357 | 2 2 6 2 2 6 2 2 6 2 2 6 | 356 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 358 | 70 70 70 58 58 58 22 22 22 6 6 6 | 357 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 359 | 0 0 0 0 0 0 0 0 0 0 0 0 | 358 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 360 | 0 0 0 0 0 0 0 0 0 0 0 0 | 359 | 0 0 0 0 0 0 0 0 0 63 64 60 68 70 65 68 70 65 |
| 361 | 0 0 0 0 0 0 0 0 0 0 0 0 | 360 | 65 66 61 58 59 55 49 51 48 39 40 39 30 32 31 23 27 26 |
| 362 | 0 0 0 0 0 0 0 0 0 0 0 0 | 361 | 20 24 24 18 22 22 17 21 21 16 20 20 17 21 21 20 23 23 |
| 363 | 0 0 0 0 0 0 0 0 0 0 0 0 | 362 | 25 27 26 32 35 33 43 44 41 53 55 47 66 65 55 75 75 61 |
| 364 | 0 0 0 0 0 0 0 0 0 0 0 0 | 363 | 82 81 62 84 83 72 87 86 72 87 86 72 82 81 62 75 75 61 |
| 365 | 0 0 0 0 0 0 0 0 1 0 0 0 | 364 | 66 65 55 53 55 47 40 41 39 31 33 31 23 25 24 17 20 20 |
| 366 | 0 0 1 0 0 1 0 0 1 0 0 0 | 365 | 14 18 18 13 16 16 12 15 15 12 15 15 13 17 17 14 18 18 |
| 367 | 0 0 0 0 0 0 0 0 0 0 0 0 | 366 | 14 18 18 13 16 16 46 47 43 96 95 69 125 122 87 142 137 94 |
| 368 | 0 0 0 0 0 0 0 0 0 0 0 0 | 367 | 160 154 106 165 161 109 164 159 111 155 149 109 142 137 94 75 75 61 |
| 369 | 0 0 0 0 0 0 0 0 0 0 0 0 | 368 | 10 12 12 10 12 12 6 8 8 0 0 0 0 0 0 0 0 0 |
| 370 | 0 0 0 0 0 0 0 0 0 0 0 0 | 369 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 371 | 0 0 0 0 0 0 0 0 0 14 14 14 | 370 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 372 | 42 42 42 86 86 86 6 6 6 116 116 116 | 371 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 373 | 106 106 106 6 6 6 70 70 70 149 149 149 | 372 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 374 | 128 128 128 18 18 18 38 38 38 54 54 54 | 373 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 375 | 221 221 221 106 106 106 2 2 6 14 14 14 | 374 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 376 | 46 46 46 190 190 190 198 198 198 2 2 6 | 375 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 377 | 2 2 6 2 2 6 2 2 6 2 2 6 | 376 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 378 | 74 74 74 62 62 62 22 22 22 6 6 6 | 377 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 379 | 0 0 0 0 0 0 0 0 0 0 0 0 | 378 | 0 0 0 |
| 380 | 0 0 0 0 0 0 0 0 0 0 0 0 | 379 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 381 | 0 0 0 0 0 0 0 0 0 0 0 0 | 380 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 382 | 0 0 0 0 0 0 0 0 0 0 0 0 | 381 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 383 | 0 0 0 0 0 0 0 0 0 0 0 0 | 382 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 384 | 0 0 0 0 0 0 0 0 0 0 0 0 | 383 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 385 | 0 0 0 0 0 0 0 0 1 0 0 0 | 384 | 0 0 0 0 0 0 0 0 0 60 60 56 68 70 65 68 70 65 |
| 386 | 0 0 1 0 0 0 0 0 1 0 0 0 | 385 | 63 64 60 55 57 54 46 47 45 35 37 36 27 30 29 23 25 24 |
| 387 | 0 0 0 0 0 0 0 0 0 0 0 0 | 386 | 18 22 22 17 21 21 16 20 20 17 21 21 18 22 22 23 27 26 |
| 388 | 0 0 0 0 0 0 0 0 0 0 0 0 | 387 | 31 33 31 43 44 41 55 56 53 71 71 57 84 83 72 92 91 72 |
| 389 | 0 0 0 0 0 0 0 0 0 0 0 0 | 388 | 103 101 77 92 91 72 82 81 62 82 81 62 87 86 72 92 91 72 |
| 390 | 0 0 0 0 0 0 0 0 0 0 0 0 | 389 | 84 83 72 71 71 57 55 56 53 43 44 41 30 33 30 22 24 23 |
| 391 | 0 0 0 0 0 0 0 0 0 14 14 14 | 390 | 16 19 19 14 17 17 12 15 15 12 15 15 13 16 16 14 18 18 |
| 392 | 42 42 42 94 94 94 14 14 14 101 101 101 | 391 | 14 18 18 14 17 17 43 44 41 82 81 62 118 116 76 125 122 87 |
| 393 | 128 128 128 2 2 6 18 18 18 116 116 116 | 392 | 142 137 94 144 139 99 144 139 99 134 131 96 118 116 76 53 55 47 |
| 394 | 118 98 46 121 92 8 121 92 8 98 78 10 | 393 | 10 12 12 10 12 12 6 8 8 0 0 0 0 0 0 0 0 0 |
| 395 | 162 162 162 106 106 106 2 2 6 2 2 6 | 394 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 396 | 2 2 6 195 195 195 195 195 195 6 6 6 | 395 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 397 | 2 2 6 2 2 6 2 2 6 2 2 6 | 396 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 398 | 74 74 74 62 62 62 22 22 22 6 6 6 | 397 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 399 | 0 0 0 0 0 0 0 0 0 0 0 0 | 398 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 400 | 0 0 0 0 0 0 0 0 0 0 0 0 | 399 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 401 | 0 0 0 0 0 0 0 0 0 0 0 0 | 400 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 402 | 0 0 0 0 0 0 0 0 0 0 0 0 | 401 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 403 | 0 0 0 0 0 0 0 0 0 0 0 0 | 402 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 404 | 0 0 0 0 0 0 0 0 0 0 0 0 | 403 | 0 0 0 |
| 405 | 0 0 0 0 0 0 0 0 1 0 0 1 | 404 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 406 | 0 0 1 0 0 0 0 0 1 0 0 0 | 405 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 407 | 0 0 0 0 0 0 0 0 0 0 0 0 | 406 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 408 | 0 0 0 0 0 0 0 0 0 0 0 0 | 407 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 409 | 0 0 0 0 0 0 0 0 0 0 0 0 | 408 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 410 | 0 0 0 0 0 0 0 0 0 0 0 0 | 409 | 0 0 0 0 0 0 0 0 0 47 48 46 63 64 60 63 64 60 |
| 411 | 0 0 0 0 0 0 0 0 0 10 10 10 | 410 | 55 57 54 49 51 48 40 43 41 32 34 33 26 28 27 20 24 24 |
| 412 | 38 38 38 90 90 90 14 14 14 58 58 58 | 411 | 18 22 22 16 20 20 16 20 20 17 21 21 20 24 24 28 31 30 |
| 413 | 210 210 210 26 26 26 54 38 6 154 114 10 | 412 | 40 41 39 53 55 47 75 75 61 90 89 73 87 86 72 48 49 45 |
| 414 | 226 170 11 236 186 11 225 175 15 184 144 12 | 413 | 14 14 13 2 2 2 1 2 2 1 1 1 1 1 1 2 2 2 |
| 415 | 215 174 15 175 146 61 37 26 9 2 2 6 | 414 | 19 20 18 43 44 41 66 65 55 53 55 47 38 39 37 26 28 27 |
| 416 | 70 70 70 246 246 246 138 138 138 2 2 6 | 415 | 18 22 22 14 18 18 13 16 16 12 15 15 12 15 15 13 17 17 |
| 417 | 2 2 6 2 2 6 2 2 6 2 2 6 | 416 | 14 18 18 14 18 18 30 31 28 66 65 55 96 95 69 103 101 77 |
| 418 | 70 70 70 66 66 66 26 26 26 6 6 6 | 417 | 118 116 76 118 116 76 118 116 76 118 116 76 103 101 77 36 38 35 |
| 419 | 0 0 0 0 0 0 0 0 0 0 0 0 | 418 | 10 12 12 10 12 12 6 7 7 0 0 0 0 0 0 0 0 0 |
| 420 | 0 0 0 0 0 0 0 0 0 0 0 0 | 419 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 421 | 0 0 0 0 0 0 0 0 0 0 0 0 | 420 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 422 | 0 0 0 0 0 0 0 0 0 0 0 0 | 421 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 423 | 0 0 0 0 0 0 0 0 0 0 0 0 | 422 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 424 | 0 0 0 0 0 0 0 0 0 0 0 0 | 423 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 425 | 0 0 0 0 0 0 0 0 0 0 0 0 | 424 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 426 | 0 0 0 0 0 0 0 0 0 0 0 0 | 425 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 427 | 0 0 0 0 0 0 0 0 0 0 0 0 | 426 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 428 | 0 0 0 0 0 0 0 0 0 0 0 0 | 427 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 429 | 0 0 0 0 0 0 0 0 0 0 0 0 | 428 | 0 0 0 |
| 430 | 0 0 0 0 0 0 0 0 0 0 0 0 | 429 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 431 | 0 0 0 0 0 0 0 0 0 10 10 10 | 430 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 432 | 38 38 38 86 86 86 14 14 14 10 10 10 | 431 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 433 | 195 195 195 188 164 115 192 133 9 225 175 15 | 432 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 434 | 239 182 13 234 190 10 232 195 16 232 200 30 | 433 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 435 | 245 207 45 241 208 19 232 195 16 184 144 12 | 434 | 0 0 0 0 0 0 0 0 0 28 31 30 55 57 54 51 52 50 |
| 436 | 218 194 134 211 206 186 42 42 42 2 2 6 | 435 | 49 51 48 41 42 42 35 37 36 28 31 30 23 27 26 20 23 23 |
| 437 | 2 2 6 2 2 6 2 2 6 2 2 6 | 436 | 17 21 21 16 20 20 16 20 20 18 22 22 23 27 26 33 36 34 |
| 438 | 50 50 50 74 74 74 30 30 30 6 6 6 | 437 | 48 49 45 71 71 57 82 81 62 43 44 41 8 9 9 6 7 7 |
| 439 | 0 0 0 0 0 0 0 0 0 0 0 0 | 438 | 6 7 7 6 7 7 6 7 7 5 6 5 4 5 5 3 4 4 |
| 440 | 0 0 0 0 0 0 0 0 0 0 0 0 | 439 | 2 3 3 1 2 2 4 5 4 36 38 35 48 49 45 32 35 33 |
| 441 | 0 0 0 0 0 0 0 0 0 0 0 0 | 440 | 21 25 23 16 19 19 13 17 17 12 15 15 12 15 15 13 16 16 |
| 442 | 0 0 0 0 0 0 0 0 0 0 0 0 | 441 | 14 18 18 14 18 18 16 18 16 36 38 35 61 61 53 82 81 62 |
| 443 | 0 0 0 0 0 0 0 0 0 0 0 0 | 442 | 96 95 69 96 95 69 96 95 69 96 95 69 79 78 62 19 20 18 |
| 444 | 0 0 0 0 0 0 0 0 0 0 0 0 | 443 | 10 12 12 10 12 12 4 5 5 0 0 0 0 0 0 0 0 0 |
| 445 | 0 0 0 0 0 0 0 0 0 0 0 0 | 444 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 446 | 0 0 0 0 0 0 0 0 0 0 0 0 | 445 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 447 | 0 0 0 0 0 0 0 0 0 0 0 0 | 446 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 448 | 0 0 0 0 0 0 0 0 0 0 0 0 | 447 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 449 | 0 0 0 0 0 0 0 0 0 0 0 0 | 448 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 450 | 0 0 0 0 0 0 0 0 0 0 0 0 | 449 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 451 | 0 0 0 0 0 0 0 0 0 10 10 10 | 450 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 452 | 34 34 34 86 86 86 14 14 14 2 2 6 | 451 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 453 | 121 87 25 192 133 9 219 162 10 239 182 13 | 452 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 454 | 236 186 11 232 195 16 241 208 19 244 214 54 | 453 | 0 0 0 |
| 455 | 246 218 60 246 218 38 246 215 20 241 208 19 | 454 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 456 | 241 208 19 226 184 13 121 87 25 2 2 6 | 455 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 457 | 2 2 6 2 2 6 2 2 6 2 2 6 | 456 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 458 | 50 50 50 82 82 82 34 34 34 10 10 10 | 457 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 459 | 0 0 0 0 0 0 0 0 0 0 0 0 | 458 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 460 | 0 0 0 0 0 0 0 0 0 0 0 0 | 459 | 0 0 0 0 0 0 0 0 0 13 13 13 46 47 45 43 45 43 |
| 461 | 0 0 0 0 0 0 0 0 0 0 0 0 | 460 | 40 43 41 35 37 36 30 32 31 23 27 26 20 24 24 18 22 22 |
| 462 | 0 0 0 0 0 0 0 0 0 0 0 0 | 461 | 17 21 21 16 20 20 17 21 21 20 23 23 27 30 29 40 41 39 |
| 463 | 0 0 0 0 0 0 0 0 0 0 0 0 | 462 | 61 61 53 53 55 47 16 17 16 9 11 11 10 12 12 10 12 12 |
| 464 | 0 0 0 0 0 0 0 0 0 0 0 0 | 463 | 10 12 12 10 12 12 10 12 12 9 11 11 8 10 10 8 9 9 |
| 465 | 0 0 0 0 0 0 0 0 0 0 0 0 | 464 | 6 8 8 5 6 5 4 5 5 2 3 3 19 20 18 38 39 37 |
| 466 | 0 0 0 0 0 0 0 0 0 0 0 0 | 465 | 26 28 27 17 21 21 14 17 17 13 16 16 12 15 15 12 15 15 |
| 467 | 0 0 0 0 0 0 0 0 0 0 0 0 | 466 | 13 17 17 14 18 18 12 15 15 13 12 7 30 31 28 46 47 43 |
| 468 | 0 0 0 0 0 0 0 0 0 0 0 0 | 467 | 53 55 47 66 65 55 66 65 55 53 55 47 36 38 35 10 12 12 |
| 469 | 0 0 0 0 0 0 0 0 0 0 0 0 | 468 | 10 12 12 10 12 12 2 3 3 0 0 0 0 0 0 0 0 0 |
| 470 | 0 0 0 0 0 0 0 0 0 0 0 0 | 469 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 471 | 0 0 0 0 0 0 0 0 0 10 10 10 | 470 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 472 | 34 34 34 82 82 82 30 30 30 61 42 6 | 471 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 473 | 180 123 7 206 145 10 230 174 11 239 182 13 | 472 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 474 | 234 190 10 238 202 15 241 208 19 246 218 74 | 473 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 475 | 246 218 38 246 215 20 246 215 20 246 215 20 | 474 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 476 | 226 184 13 215 174 15 184 144 12 6 6 6 | 475 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 477 | 2 2 6 2 2 6 2 2 6 2 2 6 | 476 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 478 | 26 26 26 94 94 94 42 42 42 14 14 14 | 477 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 479 | 0 0 0 0 0 0 0 0 0 0 0 0 | 478 | 0 0 0 |
| 480 | 0 0 0 0 0 0 0 0 0 0 0 0 | 479 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 481 | 0 0 0 0 0 0 0 0 0 0 0 0 | 480 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 482 | 0 0 0 0 0 0 0 0 0 0 0 0 | 481 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 483 | 0 0 0 0 0 0 0 0 0 0 0 0 | 482 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 484 | 0 0 0 0 0 0 0 0 0 0 0 0 | 483 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 485 | 0 0 0 0 0 0 0 0 0 0 0 0 | 484 | 0 0 0 0 0 0 0 0 0 1 1 1 33 37 35 35 37 36 |
| 486 | 0 0 0 0 0 0 0 0 0 0 0 0 | 485 | 32 35 33 28 31 30 23 27 26 20 24 24 18 22 22 17 21 21 |
| 487 | 0 0 0 0 0 0 0 0 0 0 0 0 | 486 | 16 20 20 16 20 20 17 21 21 21 25 23 31 33 31 44 46 43 |
| 488 | 0 0 0 0 0 0 0 0 0 0 0 0 | 487 | 31 33 31 11 13 13 12 14 14 12 15 15 13 16 16 14 17 17 |
| 489 | 0 0 0 0 0 0 0 0 0 0 0 0 | 488 | 14 17 17 14 17 17 14 17 17 13 16 16 12 15 15 12 14 14 |
| 490 | 0 0 0 0 0 0 0 0 0 0 0 0 | 489 | 11 13 13 9 11 11 8 10 10 6 8 8 4 5 5 17 18 17 |
| 491 | 0 0 0 0 0 0 0 0 0 10 10 10 | 490 | 30 33 30 20 23 22 15 18 18 13 16 16 12 15 15 12 14 14 |
| 492 | 30 30 30 78 78 78 50 50 50 104 69 6 | 491 | 13 16 16 14 17 17 14 18 18 11 12 11 7 7 5 16 17 12 |
| 493 | 192 133 9 216 158 10 236 178 12 236 186 11 | 492 | 21 22 20 30 31 28 25 27 25 21 22 20 14 14 13 10 12 12 |
| 494 | 232 195 16 241 208 19 244 214 54 245 215 43 | 493 | 10 12 12 9 11 11 0 0 0 0 0 0 0 0 0 0 0 0 |
| 495 | 246 215 20 246 215 20 241 208 19 198 155 10 | 494 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 496 | 200 144 11 216 158 10 156 118 10 2 2 6 | 495 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 497 | 2 2 6 2 2 6 2 2 6 2 2 6 | 496 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 498 | 6 6 6 90 90 90 54 54 54 18 18 18 | 497 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 499 | 6 6 6 0 0 0 0 0 0 0 0 0 | 498 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 500 | 0 0 0 0 0 0 0 0 0 0 0 0 | 499 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 501 | 0 0 0 0 0 0 0 0 0 0 0 0 | 500 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 502 | 0 0 0 0 0 0 0 0 0 0 0 0 | 501 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 503 | 0 0 0 0 0 0 0 0 0 0 0 0 | 502 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 504 | 0 0 0 0 0 0 0 0 0 0 0 0 | 503 | 0 0 0 |
| 505 | 0 0 0 0 0 0 0 0 0 0 0 0 | 504 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 506 | 0 0 0 0 0 0 0 0 0 0 0 0 | 505 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 507 | 0 0 0 0 0 0 0 0 0 0 0 0 | 506 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 508 | 0 0 0 0 0 0 0 0 0 0 0 0 | 507 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 509 | 0 0 0 0 0 0 0 0 0 0 0 0 | 508 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 510 | 0 0 0 0 0 0 0 0 0 0 0 0 | 509 | 0 0 0 0 0 0 0 0 0 0 0 0 18 22 22 27 30 29 |
| 511 | 0 0 0 0 0 0 0 0 0 10 10 10 | 510 | 27 29 28 40 41 39 53 55 47 53 55 47 53 55 47 46 47 43 |
| 512 | 30 30 30 78 78 78 46 46 46 22 22 22 | 511 | 25 27 25 16 20 20 17 21 21 23 25 24 31 33 31 20 20 20 |
| 513 | 137 92 6 210 162 10 239 182 13 238 190 10 | 512 | 12 15 15 14 17 17 15 19 19 16 20 20 17 21 21 18 22 22 |
| 514 | 238 202 15 241 208 19 246 215 20 246 215 20 | 513 | 18 22 22 18 22 22 18 22 22 17 21 21 17 21 21 16 19 19 |
| 515 | 241 208 19 203 166 17 185 133 11 210 150 10 | 514 | 15 18 18 13 16 16 12 15 15 10 12 12 8 10 10 6 8 8 |
| 516 | 216 158 10 210 150 10 102 78 10 2 2 6 | 515 | 21 22 21 22 24 23 15 19 19 13 17 17 13 16 16 12 15 15 |
| 517 | 6 6 6 54 54 54 14 14 14 2 2 6 | 516 | 12 15 15 13 17 17 14 18 18 14 18 18 13 15 14 10 9 6 |
| 518 | 2 2 6 62 62 62 74 74 74 30 30 30 | 517 | 7 7 5 7 7 5 7 7 5 9 11 11 10 12 12 10 12 12 |
| 519 | 10 10 10 0 0 0 0 0 0 0 0 0 | 518 | 10 12 12 6 7 7 0 0 0 0 0 0 0 0 0 0 0 0 |
| 520 | 0 0 0 0 0 0 0 0 0 0 0 0 | 519 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 521 | 0 0 0 0 0 0 0 0 0 0 0 0 | 520 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 522 | 0 0 0 0 0 0 0 0 0 0 0 0 | 521 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 523 | 0 0 0 0 0 0 0 0 0 0 0 0 | 522 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 524 | 0 0 0 0 0 0 0 0 0 0 0 0 | 523 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 525 | 0 0 0 0 0 0 0 0 0 0 0 0 | 524 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 526 | 0 0 0 0 0 0 0 0 0 0 0 0 | 525 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 527 | 0 0 0 0 0 0 0 0 0 0 0 0 | 526 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 528 | 0 0 0 0 0 0 0 0 0 0 0 0 | 527 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 529 | 0 0 0 0 0 0 0 0 0 0 0 0 | 528 | 0 0 0 |
| 530 | 0 0 0 0 0 0 0 0 0 0 0 0 | 529 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 531 | 0 0 0 0 0 0 0 0 0 10 10 10 | 530 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 532 | 34 34 34 78 78 78 50 50 50 6 6 6 | 531 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 533 | 94 70 30 139 102 15 190 146 13 226 184 13 | 532 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 534 | 232 200 30 232 195 16 215 174 15 190 146 13 | 533 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 535 | 168 122 10 192 133 9 210 150 10 213 154 11 | 534 | 0 0 0 0 0 0 0 0 0 0 0 0 16 17 12 82 81 62 |
| 536 | 202 150 34 182 157 106 101 98 89 2 2 6 | 535 | 118 116 76 118 116 76 161 156 96 161 156 96 161 156 96 118 116 76 |
| 537 | 2 2 6 78 78 78 116 116 116 58 58 58 | 536 | 118 116 76 96 95 69 53 55 47 22 24 23 14 17 17 13 16 16 |
| 538 | 2 2 6 22 22 22 90 90 90 46 46 46 | 537 | 15 19 19 17 21 21 18 22 22 20 24 24 20 24 24 23 27 26 |
| 539 | 18 18 18 6 6 6 0 0 0 0 0 0 | 538 | 23 27 26 23 27 26 23 27 26 23 27 26 23 27 26 20 24 24 |
| 540 | 0 0 0 0 0 0 0 0 0 0 0 0 | 539 | 20 23 23 17 21 21 16 19 19 14 17 17 12 15 15 10 12 12 |
| 541 | 0 0 0 0 0 0 0 0 0 0 0 0 | 540 | 9 11 11 20 23 22 16 19 19 14 17 17 13 16 16 12 15 15 |
| 542 | 0 0 0 0 0 0 0 0 0 0 0 0 | 541 | 11 14 14 13 16 16 14 17 17 14 18 18 14 17 17 12 15 15 |
| 543 | 0 0 0 0 0 0 0 0 0 0 0 0 | 542 | 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 |
| 544 | 0 0 0 0 0 0 0 0 0 0 0 0 | 543 | 9 11 11 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 |
| 545 | 0 0 0 0 0 0 0 0 0 0 0 0 | 544 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 546 | 0 0 0 0 0 0 0 0 0 0 0 0 | 545 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 547 | 0 0 0 0 0 0 0 0 0 0 0 0 | 546 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 548 | 0 0 0 0 0 0 0 0 0 0 0 0 | 547 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 549 | 0 0 0 0 0 0 0 0 0 0 0 0 | 548 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 550 | 0 0 0 0 0 0 0 0 0 0 0 0 | 549 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 551 | 0 0 0 0 0 0 0 0 0 10 10 10 | 550 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 552 | 38 38 38 86 86 86 50 50 50 6 6 6 | 551 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 553 | 128 128 128 174 154 114 156 107 11 168 122 10 | 552 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 554 | 198 155 10 184 144 12 197 138 11 200 144 11 | 553 | 0 0 0 |
| 555 | 206 145 10 206 145 10 197 138 11 188 164 115 | 554 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 556 | 195 195 195 198 198 198 174 174 174 14 14 14 | 555 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 557 | 2 2 6 22 22 22 116 116 116 116 116 116 | 556 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 558 | 22 22 22 2 2 6 74 74 74 70 70 70 | 557 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 559 | 30 30 30 10 10 10 0 0 0 0 0 0 | 558 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 560 | 0 0 0 0 0 0 0 0 0 0 0 0 | 559 | 0 0 0 0 0 0 0 0 0 0 0 0 53 55 47 161 156 96 |
| 561 | 0 0 0 0 0 0 0 0 0 0 0 0 | 560 | 161 156 96 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 562 | 0 0 0 0 0 0 0 0 0 0 0 0 | 561 | 230 229 82 161 156 96 118 116 76 96 95 69 21 22 20 16 19 19 |
| 563 | 0 0 0 0 0 0 0 0 0 0 0 0 | 562 | 18 22 22 20 24 24 23 27 26 23 27 26 26 28 27 27 30 29 |
| 564 | 0 0 0 0 0 0 0 0 0 0 0 0 | 563 | 27 30 29 18 22 22 12 14 14 8 10 10 9 11 11 17 21 21 |
| 565 | 0 0 0 0 0 0 0 0 0 0 0 0 | 564 | 23 27 26 23 27 26 20 24 24 18 22 22 16 20 20 14 17 17 |
| 566 | 0 0 0 0 0 0 0 0 0 0 0 0 | 565 | 12 14 14 14 17 17 16 20 20 14 17 17 13 17 17 13 16 16 |
| 567 | 0 0 0 0 0 0 0 0 0 0 0 0 | 566 | 12 15 15 12 15 15 13 17 17 14 18 18 14 17 17 13 16 16 |
| 568 | 0 0 0 0 0 0 0 0 0 0 0 0 | 567 | 11 13 13 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 |
| 569 | 0 0 0 0 0 0 0 0 0 0 0 0 | 568 | 4 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 570 | 0 0 0 0 0 0 0 0 0 0 0 0 | 569 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 571 | 0 0 0 0 0 0 6 6 6 18 18 18 | 570 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 572 | 50 50 50 101 101 101 26 26 26 10 10 10 | 571 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 573 | 138 138 138 190 190 190 174 154 114 156 107 11 | 572 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 574 | 197 138 11 200 144 11 197 138 11 192 133 9 | 573 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 575 | 180 123 7 190 142 34 190 178 144 187 187 187 | 574 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 576 | 202 202 202 221 221 221 214 214 214 66 66 66 | 575 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 577 | 2 2 6 2 2 6 50 50 50 62 62 62 | 576 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 578 | 6 6 6 2 2 6 10 10 10 90 90 90 | 577 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 579 | 50 50 50 18 18 18 6 6 6 0 0 0 | 578 | 0 0 0 |
| 580 | 0 0 0 0 0 0 0 0 0 0 0 0 | 579 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 581 | 0 0 0 0 0 0 0 0 0 0 0 0 | 580 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 582 | 0 0 0 0 0 0 0 0 0 0 0 0 | 581 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 583 | 0 0 0 0 0 0 0 0 0 0 0 0 | 582 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 584 | 0 0 0 0 0 0 0 0 0 0 0 0 | 583 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 585 | 0 0 0 0 0 0 0 0 0 0 0 0 | 584 | 0 0 0 0 0 0 0 0 0 13 12 7 118 116 76 230 229 82 |
| 586 | 0 0 0 0 0 0 0 0 0 0 0 0 | 585 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 587 | 0 0 0 0 0 0 0 0 0 0 0 0 | 586 | 230 229 82 230 229 82 230 229 82 161 156 96 118 116 76 30 31 28 |
| 588 | 0 0 0 0 0 0 0 0 0 0 0 0 | 587 | 20 24 24 23 27 26 27 30 29 28 31 30 30 32 31 23 27 26 |
| 589 | 0 0 0 0 0 0 0 0 0 0 0 0 | 588 | 16 19 19 17 21 21 12 15 15 9 11 11 10 12 12 9 11 11 |
| 590 | 0 0 0 0 0 0 0 0 0 0 0 0 | 589 | 20 24 24 28 31 30 26 28 27 23 27 26 20 24 24 17 21 21 |
| 591 | 0 0 0 0 0 0 10 10 10 34 34 34 | 590 | 15 19 19 13 16 16 16 19 19 14 18 18 14 17 17 13 16 16 |
| 592 | 74 74 74 74 74 74 2 2 6 6 6 6 | 591 | 12 15 15 11 14 14 13 16 16 14 17 17 14 18 18 14 17 17 |
| 593 | 144 144 144 198 198 198 190 190 190 178 166 146 | 592 | 12 15 15 10 12 12 10 12 12 10 12 12 10 12 12 8 9 9 |
| 594 | 154 121 60 156 107 11 156 107 11 168 124 44 | 593 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 595 | 174 154 114 187 187 187 190 190 190 210 210 210 | 594 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 596 | 246 246 246 253 253 253 253 253 253 182 182 182 | 595 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 597 | 6 6 6 2 2 6 2 2 6 2 2 6 | 596 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 598 | 2 2 6 2 2 6 2 2 6 62 62 62 | 597 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 599 | 74 74 74 34 34 34 14 14 14 0 0 0 | 598 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 600 | 0 0 0 0 0 0 0 0 0 0 0 0 | 599 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 601 | 0 0 0 0 0 0 0 0 0 0 0 0 | 600 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 602 | 0 0 0 0 0 0 0 0 0 0 0 0 | 601 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 603 | 0 0 0 0 0 0 0 0 0 0 0 0 | 602 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 604 | 0 0 0 0 0 0 0 0 0 0 0 0 | 603 | 0 0 0 |
| 605 | 0 0 0 0 0 0 0 0 0 0 0 0 | 604 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 606 | 0 0 0 0 0 0 0 0 0 0 0 0 | 605 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 607 | 0 0 0 0 0 0 0 0 0 0 0 0 | 606 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 608 | 0 0 0 0 0 0 0 0 0 0 0 0 | 607 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 609 | 0 0 0 0 0 0 0 0 0 0 0 0 | 608 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 610 | 0 0 0 0 0 0 0 0 0 0 0 0 | 609 | 0 0 0 0 0 0 0 0 0 82 81 62 161 156 96 230 229 82 |
| 611 | 0 0 0 10 10 10 22 22 22 54 54 54 | 610 | 230 229 82 233 233 100 230 229 82 230 229 82 230 229 82 230 229 82 |
| 612 | 94 94 94 18 18 18 2 2 6 46 46 46 | 611 | 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 118 116 76 |
| 613 | 234 234 234 221 221 221 190 190 190 190 190 190 | 612 | 27 29 28 27 30 29 30 32 31 30 32 31 23 27 26 20 24 24 |
| 614 | 190 190 190 187 187 187 187 187 187 190 190 190 | 613 | 26 28 27 17 21 21 6 7 7 72 73 67 145 141 105 15 15 15 |
| 615 | 190 190 190 195 195 195 214 214 214 242 242 242 | 614 | 14 17 17 33 37 35 30 32 31 28 31 30 26 28 27 23 27 26 |
| 616 | 253 253 253 253 253 253 253 253 253 253 253 253 | 615 | 20 23 23 16 20 20 15 19 19 14 18 18 14 17 17 13 16 16 |
| 617 | 82 82 82 2 2 6 2 2 6 2 2 6 | 616 | 12 15 15 11 14 14 12 15 15 13 17 17 14 18 18 14 17 17 |
| 618 | 2 2 6 2 2 6 2 2 6 14 14 14 | 617 | 13 16 16 11 13 13 10 12 12 10 12 12 9 11 11 1 1 1 |
| 619 | 86 86 86 54 54 54 22 22 22 6 6 6 | 618 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 620 | 0 0 0 0 0 0 0 0 0 0 0 0 | 619 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 621 | 0 0 0 0 0 0 0 0 0 0 0 0 | 620 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 622 | 0 0 0 0 0 0 0 0 0 0 0 0 | 621 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 623 | 0 0 0 0 0 0 0 0 0 0 0 0 | 622 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 624 | 0 0 0 0 0 0 0 0 0 0 0 0 | 623 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 625 | 0 0 0 0 0 0 0 0 0 0 0 0 | 624 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 626 | 0 0 0 0 0 0 0 0 0 0 0 0 | 625 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 627 | 0 0 0 0 0 0 0 0 0 0 0 0 | 626 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 628 | 0 0 0 0 0 0 0 0 0 0 0 0 | 627 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 629 | 0 0 0 0 0 0 0 0 0 0 0 0 | 628 | 0 0 0 |
| 630 | 0 0 0 0 0 0 0 0 0 0 0 0 | 629 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 631 | 6 6 6 18 18 18 46 46 46 90 90 90 | 630 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 632 | 46 46 46 18 18 18 6 6 6 182 182 182 | 631 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 633 | 253 253 253 246 246 246 206 206 206 190 190 190 | 632 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 634 | 190 190 190 190 190 190 190 190 190 190 190 190 | 633 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 635 | 206 206 206 231 231 231 250 250 250 253 253 253 | 634 | 0 0 0 0 0 0 16 17 12 161 156 96 230 229 82 230 229 82 |
| 636 | 253 253 253 253 253 253 253 253 253 253 253 253 | 635 | 243 242 120 235 234 117 230 229 82 230 229 82 230 229 82 230 229 82 |
| 637 | 202 202 202 14 14 14 2 2 6 2 2 6 | 636 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 |
| 638 | 2 2 6 2 2 6 2 2 6 2 2 6 | 637 | 82 81 62 28 31 30 28 31 30 27 30 29 28 31 30 30 32 31 |
| 639 | 42 42 42 86 86 86 42 42 42 18 18 18 | 638 | 33 37 35 13 16 16 3 3 3 105 104 92 210 208 158 12 14 14 |
| 640 | 6 6 6 0 0 0 0 0 0 0 0 0 | 639 | 17 21 21 33 37 35 33 37 35 32 35 33 30 32 31 27 30 29 |
| 641 | 0 0 0 0 0 0 0 0 0 0 0 0 | 640 | 23 27 26 20 23 23 17 20 20 15 18 18 14 18 18 13 17 17 |
| 642 | 0 0 0 0 0 0 0 0 0 0 0 0 | 641 | 13 16 16 12 15 15 11 14 14 13 16 16 14 17 17 14 18 18 |
| 643 | 0 0 0 0 0 0 0 0 0 0 0 0 | 642 | 13 17 17 12 15 15 10 12 12 10 12 12 3 4 4 0 0 0 |
| 644 | 0 0 0 0 0 0 0 0 0 0 0 0 | 643 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 645 | 0 0 0 0 0 0 0 0 0 0 0 0 | 644 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 646 | 0 0 0 0 0 0 0 0 0 0 0 0 | 645 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 647 | 0 0 0 0 0 0 0 0 0 0 0 0 | 646 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 648 | 0 0 0 0 0 0 0 0 0 0 0 0 | 647 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 649 | 0 0 0 0 0 0 0 0 0 0 0 0 | 648 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 650 | 0 0 0 0 0 0 0 0 0 6 6 6 | 649 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 651 | 14 14 14 38 38 38 74 74 74 66 66 66 | 650 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 652 | 2 2 6 6 6 6 90 90 90 250 250 250 | 651 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 653 | 253 253 253 253 253 253 238 238 238 198 198 198 | 652 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 654 | 190 190 190 190 190 190 195 195 195 221 221 221 | 653 | 0 0 0 |
| 655 | 246 246 246 253 253 253 253 253 253 253 253 253 | 654 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 656 | 253 253 253 253 253 253 253 253 253 253 253 253 | 655 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 657 | 253 253 253 82 82 82 2 2 6 2 2 6 | 656 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 658 | 2 2 6 2 2 6 2 2 6 2 2 6 | 657 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 659 | 2 2 6 78 78 78 70 70 70 34 34 34 | 658 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 660 | 14 14 14 6 6 6 0 0 0 0 0 0 | 659 | 0 0 0 0 0 0 96 95 69 230 229 82 230 229 82 244 244 132 |
| 661 | 0 0 0 0 0 0 0 0 0 0 0 0 | 660 | 241 241 143 243 242 120 230 229 82 230 229 82 230 229 82 230 229 82 |
| 662 | 0 0 0 0 0 0 0 0 0 0 0 0 | 661 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 663 | 0 0 0 0 0 0 0 0 0 0 0 0 | 662 | 161 156 96 46 47 43 32 35 33 33 37 35 33 37 35 33 37 35 |
| 664 | 0 0 0 0 0 0 0 0 0 0 0 0 | 663 | 40 43 41 23 27 26 1 1 1 2 2 2 24 26 24 14 17 17 |
| 665 | 0 0 0 0 0 0 0 0 0 0 0 0 | 664 | 23 27 26 33 37 35 33 37 35 33 37 35 33 37 35 30 32 31 |
| 666 | 0 0 0 0 0 0 0 0 0 0 0 0 | 665 | 27 30 29 23 27 26 20 23 23 15 18 18 14 18 18 14 17 17 |
| 667 | 0 0 0 0 0 0 0 0 0 0 0 0 | 666 | 13 16 16 12 15 15 11 14 14 12 15 15 13 17 17 14 17 17 |
| 668 | 0 0 0 0 0 0 0 0 0 0 0 0 | 667 | 14 17 17 13 16 16 11 13 13 6 8 8 0 0 0 0 0 0 |
| 669 | 0 0 0 0 0 0 0 0 0 0 0 0 | 668 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 670 | 0 0 0 0 0 0 0 0 0 14 14 14 | 669 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 671 | 34 34 34 66 66 66 78 78 78 6 6 6 | 670 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 672 | 2 2 6 18 18 18 218 218 218 253 253 253 | 671 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 673 | 253 253 253 253 253 253 253 253 253 246 246 246 | 672 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 674 | 226 226 226 231 231 231 246 246 246 253 253 253 | 673 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 675 | 253 253 253 253 253 253 253 253 253 253 253 253 | 674 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 676 | 253 253 253 253 253 253 253 253 253 253 253 253 | 675 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 677 | 253 253 253 178 178 178 2 2 6 2 2 6 | 676 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 678 | 2 2 6 2 2 6 2 2 6 2 2 6 | 677 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 679 | 2 2 6 18 18 18 90 90 90 62 62 62 | 678 | 0 0 0 |
| 680 | 30 30 30 10 10 10 0 0 0 0 0 0 | 679 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 681 | 0 0 0 0 0 0 0 0 0 0 0 0 | 680 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 682 | 0 0 0 0 0 0 0 0 0 0 0 0 | 681 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 683 | 0 0 0 0 0 0 0 0 0 0 0 0 | 682 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 684 | 0 0 0 0 0 0 0 0 0 0 0 0 | 683 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 685 | 0 0 0 0 0 0 0 0 0 0 0 0 | 684 | 0 0 0 16 17 12 161 156 96 230 229 82 235 234 117 239 239 170 |
| 686 | 0 0 0 0 0 0 0 0 0 0 0 0 | 685 | 239 239 170 236 236 101 230 229 82 230 229 82 230 229 82 230 229 82 |
| 687 | 0 0 0 0 0 0 0 0 0 0 0 0 | 686 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 688 | 0 0 0 0 0 0 0 0 0 0 0 0 | 687 | 230 229 82 118 116 76 33 37 35 33 37 35 37 39 37 37 39 37 |
| 689 | 0 0 0 0 0 0 0 0 0 0 0 0 | 688 | 43 45 43 49 51 48 20 24 24 8 10 10 17 20 20 35 37 36 |
| 690 | 0 0 0 0 0 0 10 10 10 26 26 26 | 689 | 33 37 35 40 43 41 37 39 37 35 37 36 33 37 35 33 37 35 |
| 691 | 58 58 58 90 90 90 18 18 18 2 2 6 | 690 | 30 32 31 27 30 29 23 27 26 15 19 19 14 18 18 14 17 17 |
| 692 | 2 2 6 110 110 110 253 253 253 253 253 253 | 691 | 13 17 17 13 16 16 12 15 15 11 14 14 13 16 16 14 17 17 |
| 693 | 253 253 253 253 253 253 253 253 253 253 253 253 | 692 | 14 17 17 13 17 17 11 14 14 4 5 5 0 0 0 0 0 0 |
| 694 | 250 250 250 253 253 253 253 253 253 253 253 253 | 693 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 695 | 253 253 253 253 253 253 253 253 253 253 253 253 | 694 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 696 | 253 253 253 253 253 253 253 253 253 253 253 253 | 695 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 697 | 253 253 253 231 231 231 18 18 18 2 2 6 | 696 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 698 | 2 2 6 2 2 6 2 2 6 2 2 6 | 697 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 699 | 2 2 6 2 2 6 18 18 18 94 94 94 | 698 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 700 | 54 54 54 26 26 26 10 10 10 0 0 0 | 699 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 701 | 0 0 0 0 0 0 0 0 0 0 0 0 | 700 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 702 | 0 0 0 0 0 0 0 0 0 0 0 0 | 701 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 703 | 0 0 0 0 0 0 0 0 0 0 0 0 | 702 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 704 | 0 0 0 0 0 0 0 0 0 0 0 0 | 703 | 0 0 0 |
| 705 | 0 0 0 0 0 0 0 0 0 0 0 0 | 704 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 706 | 0 0 0 0 0 0 0 0 0 0 0 0 | 705 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 707 | 0 0 0 0 0 0 0 0 0 0 0 0 | 706 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 708 | 0 0 0 0 0 0 0 0 0 0 0 0 | 707 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 709 | 0 0 0 0 0 0 0 0 0 0 0 0 | 708 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 710 | 0 0 0 6 6 6 22 22 22 50 50 50 | 709 | 0 0 0 96 95 69 230 229 82 230 229 82 239 239 170 251 251 187 |
| 711 | 90 90 90 26 26 26 2 2 6 2 2 6 | 710 | 241 241 143 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 712 | 14 14 14 195 195 195 250 250 250 253 253 253 | 711 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 713 | 253 253 253 253 253 253 253 253 253 253 253 253 | 712 | 230 229 82 161 156 96 36 38 35 33 37 35 33 37 35 33 37 35 |
| 714 | 253 253 253 253 253 253 253 253 253 253 253 253 | 713 | 37 39 37 47 48 46 55 57 54 55 57 54 49 51 48 43 45 43 |
| 715 | 253 253 253 253 253 253 253 253 253 253 253 253 | 714 | 43 45 43 43 45 43 40 43 41 40 43 41 37 39 37 33 37 35 |
| 716 | 253 253 253 253 253 253 253 253 253 253 253 253 | 715 | 33 37 35 28 31 30 26 28 27 16 20 20 15 18 18 14 18 18 |
| 717 | 250 250 250 242 242 242 54 54 54 2 2 6 | 716 | 14 17 17 13 16 16 12 15 15 11 14 14 12 15 15 13 17 17 |
| 718 | 2 2 6 2 2 6 2 2 6 2 2 6 | 717 | 14 17 17 14 17 17 8 10 10 5 7 7 0 0 0 0 0 0 |
| 719 | 2 2 6 2 2 6 2 2 6 38 38 38 | 718 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 720 | 86 86 86 50 50 50 22 22 22 6 6 6 | 719 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 721 | 0 0 0 0 0 0 0 0 0 0 0 0 | 720 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 722 | 0 0 0 0 0 0 0 0 0 0 0 0 | 721 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 723 | 0 0 0 0 0 0 0 0 0 0 0 0 | 722 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 724 | 0 0 0 0 0 0 0 0 0 0 0 0 | 723 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 725 | 0 0 0 0 0 0 0 0 0 0 0 0 | 724 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 726 | 0 0 0 0 0 0 0 0 0 0 0 0 | 725 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 727 | 0 0 0 0 0 0 0 0 0 0 0 0 | 726 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 728 | 0 0 0 0 0 0 0 0 0 0 0 0 | 727 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 729 | 0 0 0 0 0 0 0 0 0 0 0 0 | 728 | 0 0 0 |
| 730 | 6 6 6 14 14 14 38 38 38 82 82 82 | 729 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 731 | 34 34 34 2 2 6 2 2 6 2 2 6 | 730 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 732 | 42 42 42 195 195 195 246 246 246 253 253 253 | 731 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 733 | 253 253 253 253 253 253 253 253 253 250 250 250 | 732 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 734 | 242 242 242 242 242 242 250 250 250 253 253 253 | 733 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 735 | 253 253 253 253 253 253 253 253 253 253 253 253 | 734 | 16 17 12 230 229 82 230 229 82 243 242 120 251 251 187 251 251 187 |
| 736 | 253 253 253 250 250 250 246 246 246 238 238 238 | 735 | 246 246 123 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 737 | 226 226 226 231 231 231 101 101 101 6 6 6 | 736 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 738 | 2 2 6 2 2 6 2 2 6 2 2 6 | 737 | 230 229 82 230 229 82 66 65 55 30 32 31 32 35 33 33 37 35 |
| 739 | 2 2 6 2 2 6 2 2 6 2 2 6 | 738 | 33 37 35 37 39 37 40 43 41 47 48 46 49 51 48 51 52 50 |
| 740 | 38 38 38 82 82 82 42 42 42 14 14 14 | 739 | 55 57 54 55 57 54 51 52 50 47 48 46 43 45 43 39 40 39 |
| 741 | 6 6 6 0 0 0 0 0 0 0 0 0 | 740 | 33 37 35 30 32 31 26 28 27 17 21 21 15 19 19 14 18 18 |
| 742 | 0 0 0 0 0 0 0 0 0 0 0 0 | 741 | 14 17 17 13 16 16 12 15 15 12 14 14 11 14 14 13 16 16 |
| 743 | 0 0 0 0 0 0 0 0 0 0 0 0 | 742 | 14 17 17 12 15 15 7 9 9 6 8 8 1 1 1 0 0 0 |
| 744 | 0 0 0 0 0 0 0 0 0 0 0 0 | 743 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 745 | 0 0 0 0 0 0 0 0 0 0 0 0 | 744 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 746 | 0 0 0 0 0 0 0 0 0 0 0 0 | 745 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 747 | 0 0 0 0 0 0 0 0 0 0 0 0 | 746 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 748 | 0 0 0 0 0 0 0 0 0 0 0 0 | 747 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 749 | 0 0 0 0 0 0 0 0 0 0 0 0 | 748 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 750 | 10 10 10 26 26 26 62 62 62 66 66 66 | 749 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 751 | 2 2 6 2 2 6 2 2 6 6 6 6 | 750 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 752 | 70 70 70 170 170 170 206 206 206 234 234 234 | 751 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 753 | 246 246 246 250 250 250 250 250 250 238 238 238 | 752 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 754 | 226 226 226 231 231 231 238 238 238 250 250 250 | 753 | 0 0 0 |
| 755 | 250 250 250 250 250 250 246 246 246 231 231 231 | 754 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 756 | 214 214 214 206 206 206 202 202 202 202 202 202 | 755 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 757 | 198 198 198 202 202 202 182 182 182 18 18 18 | 756 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 758 | 2 2 6 2 2 6 2 2 6 2 2 6 | 757 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 759 | 2 2 6 2 2 6 2 2 6 2 2 6 | 758 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 760 | 2 2 6 62 62 62 66 66 66 30 30 30 | 759 | 96 95 69 230 229 82 230 229 82 239 239 170 251 251 187 239 239 170 |
| 761 | 10 10 10 0 0 0 0 0 0 0 0 0 | 760 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 762 | 0 0 0 0 0 0 0 0 0 0 0 0 | 761 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 763 | 0 0 0 0 0 0 0 0 0 0 0 0 | 762 | 230 229 82 230 229 82 96 95 69 27 30 29 28 31 30 30 32 31 |
| 764 | 0 0 0 0 0 0 0 0 0 0 0 0 | 763 | 33 37 35 40 43 41 46 47 45 55 57 54 63 64 60 72 73 67 |
| 765 | 0 0 0 0 0 0 0 0 0 0 0 0 | 764 | 72 73 67 72 73 67 72 73 67 65 66 61 55 57 54 47 48 46 |
| 766 | 0 0 0 0 0 0 0 0 0 0 0 0 | 765 | 39 40 39 32 35 33 27 30 29 17 21 21 15 19 19 15 18 18 |
| 767 | 0 0 0 0 0 0 0 0 0 0 0 0 | 766 | 14 18 18 13 17 17 13 16 16 12 15 15 11 14 14 12 14 14 |
| 768 | 0 0 0 0 0 0 0 0 0 0 0 0 | 767 | 13 16 16 9 11 11 7 9 9 9 11 11 66 65 55 115 113 82 |
| 769 | 0 0 0 0 0 0 0 0 0 0 0 0 | 768 | 21 22 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 770 | 14 14 14 42 42 42 82 82 82 18 18 18 | 769 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 771 | 2 2 6 2 2 6 2 2 6 10 10 10 | 770 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 772 | 94 94 94 182 182 182 218 218 218 242 242 242 | 771 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 773 | 250 250 250 253 253 253 253 253 253 250 250 250 | 772 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 774 | 234 234 234 253 253 253 253 253 253 253 253 253 | 773 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 775 | 253 253 253 253 253 253 253 253 253 246 246 246 | 774 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 776 | 238 238 238 226 226 226 210 210 210 202 202 202 | 775 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 777 | 195 195 195 195 195 195 210 210 210 158 158 158 | 776 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 778 | 6 6 6 14 14 14 50 50 50 14 14 14 | 777 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 779 | 2 2 6 2 2 6 2 2 6 2 2 6 | 778 | 0 0 0 |
| 780 | 2 2 6 6 6 6 86 86 86 46 46 46 | 779 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 781 | 18 18 18 6 6 6 0 0 0 0 0 0 | 780 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 782 | 0 0 0 0 0 0 0 0 0 0 0 0 | 781 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 783 | 0 0 0 0 0 0 0 0 0 0 0 0 | 782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 784 | 0 0 0 0 0 0 0 0 0 0 0 0 | 783 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 12 7 |
| 785 | 0 0 0 0 0 0 0 0 0 0 0 0 | 784 | 230 229 82 230 229 82 236 236 101 251 251 187 251 251 187 246 246 123 |
| 786 | 0 0 0 0 0 0 0 0 0 0 0 0 | 785 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 787 | 0 0 0 0 0 0 0 0 0 0 0 0 | 786 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 788 | 0 0 0 0 0 0 0 0 0 0 0 0 | 787 | 230 229 82 230 229 82 118 116 76 23 27 26 26 28 27 32 35 33 |
| 789 | 0 0 0 0 0 0 0 0 0 6 6 6 | 788 | 51 52 50 90 89 73 110 109 94 145 141 105 168 163 120 177 172 135 |
| 790 | 22 22 22 54 54 54 70 70 70 2 2 6 | 789 | 177 172 135 188 184 146 188 184 146 181 176 137 194 191 148 188 184 146 |
| 791 | 2 2 6 10 10 10 2 2 6 22 22 22 | 790 | 184 179 149 188 184 146 188 184 146 156 151 111 177 172 135 181 176 137 |
| 792 | 166 166 166 231 231 231 250 250 250 253 253 253 | 791 | 177 172 135 168 163 120 168 163 120 158 153 112 156 151 111 158 153 112 |
| 793 | 253 253 253 253 253 253 253 253 253 250 250 250 | 792 | 156 151 111 158 153 112 177 172 135 188 184 146 188 184 146 194 189 146 |
| 794 | 242 242 242 253 253 253 253 253 253 253 253 253 | 793 | 36 38 35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 795 | 253 253 253 253 253 253 253 253 253 253 253 253 | 794 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 796 | 253 253 253 253 253 253 253 253 253 246 246 246 | 795 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 797 | 231 231 231 206 206 206 198 198 198 226 226 226 | 796 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 798 | 94 94 94 2 2 6 6 6 6 38 38 38 | 797 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 799 | 30 30 30 2 2 6 2 2 6 2 2 6 | 798 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 800 | 2 2 6 2 2 6 62 62 62 66 66 66 | 799 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 801 | 26 26 26 10 10 10 0 0 0 0 0 0 | 800 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 802 | 0 0 0 0 0 0 0 0 0 0 0 0 | 801 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 803 | 0 0 0 0 0 0 0 0 0 0 0 0 | 802 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 804 | 0 0 0 0 0 0 0 0 0 0 0 0 | 803 | 0 0 0 |
| 805 | 0 0 0 0 0 0 0 0 0 0 0 0 | 804 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 806 | 0 0 0 0 0 0 0 0 0 0 0 0 | 805 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 807 | 0 0 0 0 0 0 0 0 0 0 0 0 | 806 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 808 | 0 0 0 0 0 0 0 0 0 0 0 0 | 807 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 809 | 0 0 0 0 0 0 0 0 0 10 10 10 | 808 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82 81 62 |
| 810 | 30 30 30 74 74 74 50 50 50 2 2 6 | 809 | 230 229 82 230 229 82 244 244 132 251 251 187 244 244 132 230 229 82 |
| 811 | 26 26 26 26 26 26 2 2 6 106 106 106 | 810 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 812 | 238 238 238 253 253 253 253 253 253 253 253 253 | 811 | 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 82 81 62 |
| 813 | 253 253 253 253 253 253 253 253 253 253 253 253 | 812 | 96 95 69 230 229 82 181 178 103 110 109 94 156 151 111 188 184 146 |
| 814 | 253 253 253 253 253 253 253 253 253 253 253 253 | 813 | 188 184 146 197 193 154 188 184 146 184 181 136 188 184 146 168 163 120 |
| 815 | 253 253 253 253 253 253 253 253 253 253 253 253 | 814 | 168 163 120 178 174 128 156 151 111 158 153 112 174 170 121 156 151 111 |
| 816 | 253 253 253 253 253 253 253 253 253 253 253 253 | 815 | 156 151 111 158 153 112 156 151 111 168 163 120 178 174 128 181 176 137 |
| 817 | 253 253 253 246 246 246 218 218 218 202 202 202 | 816 | 176 171 126 178 174 128 184 181 136 176 171 126 178 174 128 184 181 136 |
| 818 | 210 210 210 14 14 14 2 2 6 2 2 6 | 817 | 176 171 126 178 174 128 184 181 136 164 159 111 155 149 109 96 95 69 |
| 819 | 30 30 30 22 22 22 2 2 6 2 2 6 | 818 | 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 820 | 2 2 6 2 2 6 18 18 18 86 86 86 | 819 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 821 | 42 42 42 14 14 14 0 0 0 0 0 0 | 820 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 822 | 0 0 0 0 0 0 0 0 0 0 0 0 | 821 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 823 | 0 0 0 0 0 0 0 0 0 0 0 0 | 822 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 824 | 0 0 0 0 0 0 0 0 0 0 0 0 | 823 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 825 | 0 0 0 0 0 0 0 0 0 0 0 0 | 824 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 826 | 0 0 0 0 0 0 0 0 0 0 0 0 | 825 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 827 | 0 0 0 0 0 0 0 0 0 0 0 0 | 826 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 828 | 0 0 0 0 0 0 0 0 0 0 0 0 | 827 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 829 | 0 0 0 0 0 0 0 0 0 14 14 14 | 828 | 0 0 0 |
| 830 | 42 42 42 90 90 90 22 22 22 2 2 6 | 829 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 831 | 42 42 42 2 2 6 18 18 18 218 218 218 | 830 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 832 | 253 253 253 253 253 253 253 253 253 253 253 253 | 831 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 833 | 253 253 253 253 253 253 253 253 253 253 253 253 | 832 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 834 | 253 253 253 253 253 253 253 253 253 253 253 253 | 833 | 0 0 0 0 0 0 0 0 0 0 0 0 2 2 1 161 156 96 |
| 835 | 253 253 253 253 253 253 253 253 253 253 253 253 | 834 | 230 229 82 230 229 82 244 244 132 244 244 132 236 236 101 230 229 82 |
| 836 | 253 253 253 253 253 253 253 253 253 253 253 253 | 835 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 837 | 253 253 253 253 253 253 250 250 250 221 221 221 | 836 | 230 229 82 230 229 82 230 229 82 230 229 82 46 47 43 82 81 62 |
| 838 | 218 218 218 101 101 101 2 2 6 14 14 14 | 837 | 158 153 112 197 193 154 194 189 146 184 181 136 188 184 146 168 163 120 |
| 839 | 18 18 18 38 38 38 10 10 10 2 2 6 | 838 | 156 151 111 137 133 100 131 127 93 137 133 100 137 133 100 158 153 112 |
| 840 | 2 2 6 2 2 6 2 2 6 78 78 78 | 839 | 121 119 87 137 133 100 156 151 111 145 141 105 99 98 80 84 83 72 |
| 841 | 58 58 58 22 22 22 6 6 6 0 0 0 | 840 | 63 64 60 52 53 49 40 43 41 33 36 34 36 38 35 36 38 35 |
| 842 | 0 0 0 0 0 0 0 0 0 0 0 0 | 841 | 38 39 37 43 44 41 43 44 41 46 47 43 48 49 45 48 49 45 |
| 843 | 0 0 0 0 0 0 0 0 0 0 0 0 | 842 | 46 47 43 36 38 35 30 31 28 19 20 18 6 7 7 0 0 0 |
| 844 | 0 0 0 0 0 0 0 0 0 0 0 0 | 843 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 845 | 0 0 0 0 0 0 0 0 0 0 0 0 | 844 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 846 | 0 0 0 0 0 0 0 0 0 0 0 0 | 845 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 847 | 0 0 0 0 0 0 0 0 0 0 0 0 | 846 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 848 | 0 0 0 0 0 0 0 0 0 0 0 0 | 847 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 849 | 0 0 0 0 0 0 6 6 6 18 18 18 | 848 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 850 | 54 54 54 82 82 82 2 2 6 26 26 26 | 849 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 851 | 22 22 22 2 2 6 123 123 123 253 253 253 | 850 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 852 | 253 253 253 253 253 253 253 253 253 253 253 253 | 851 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 853 | 253 253 253 253 253 253 253 253 253 253 253 253 | 852 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 854 | 253 253 253 253 253 253 253 253 253 253 253 253 | 853 | 0 0 0 |
| 855 | 253 253 253 253 253 253 253 253 253 253 253 253 | 854 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 856 | 253 253 253 253 253 253 253 253 253 253 253 253 | 855 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 857 | 253 253 253 253 253 253 253 253 253 250 250 250 | 856 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 858 | 238 238 238 198 198 198 6 6 6 38 38 38 | 857 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 859 | 58 58 58 26 26 26 38 38 38 2 2 6 | 858 | 0 0 0 0 0 0 0 0 0 0 0 0 36 38 35 230 229 82 |
| 860 | 2 2 6 2 2 6 2 2 6 46 46 46 | 859 | 230 229 82 230 229 82 246 246 123 236 236 101 230 229 82 230 229 82 |
| 861 | 78 78 78 30 30 30 10 10 10 0 0 0 | 860 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 862 | 0 0 0 0 0 0 0 0 0 0 0 0 | 861 | 230 229 82 230 229 82 230 229 82 230 229 82 53 55 47 121 119 87 |
| 863 | 0 0 0 0 0 0 0 0 0 0 0 0 | 862 | 176 171 126 171 165 117 161 156 96 82 81 62 53 55 47 33 37 35 |
| 864 | 0 0 0 0 0 0 0 0 0 0 0 0 | 863 | 39 40 39 63 64 60 99 98 80 121 119 87 137 133 100 177 172 135 |
| 865 | 0 0 0 0 0 0 0 0 0 0 0 0 | 864 | 176 171 126 184 181 136 131 127 93 131 127 93 110 109 94 84 83 72 |
| 866 | 0 0 0 0 0 0 0 0 0 0 0 0 | 865 | 51 52 50 39 40 39 27 29 28 18 22 22 16 19 19 15 19 19 |
| 867 | 0 0 0 0 0 0 0 0 0 0 0 0 | 866 | 15 19 19 14 18 18 14 17 17 13 16 16 12 15 15 11 14 14 |
| 868 | 0 0 0 0 0 0 0 0 0 0 0 0 | 867 | 10 13 13 9 12 12 9 11 11 8 9 9 7 9 9 1 1 1 |
| 869 | 0 0 0 0 0 0 10 10 10 30 30 30 | 868 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 870 | 74 74 74 58 58 58 2 2 6 42 42 42 | 869 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 871 | 2 2 6 22 22 22 231 231 231 253 253 253 | 870 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 872 | 253 253 253 253 253 253 253 253 253 253 253 253 | 871 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 873 | 253 253 253 253 253 253 253 253 253 250 250 250 | 872 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 874 | 253 253 253 253 253 253 253 253 253 253 253 253 | 873 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 875 | 253 253 253 253 253 253 253 253 253 253 253 253 | 874 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 876 | 253 253 253 253 253 253 253 253 253 253 253 253 | 875 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 877 | 253 253 253 253 253 253 253 253 253 253 253 253 | 876 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 878 | 253 253 253 246 246 246 46 46 46 38 38 38 | 877 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 879 | 42 42 42 14 14 14 38 38 38 14 14 14 | 878 | 0 0 0 |
| 880 | 2 2 6 2 2 6 2 2 6 6 6 6 | 879 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 881 | 86 86 86 46 46 46 14 14 14 0 0 0 | 880 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 882 | 0 0 0 0 0 0 0 0 0 0 0 0 | 881 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 883 | 0 0 0 0 0 0 0 0 0 0 0 0 | 882 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 884 | 0 0 0 0 0 0 0 0 0 0 0 0 | 883 | 0 0 0 0 0 0 0 0 0 0 0 0 118 116 76 230 229 82 |
| 885 | 0 0 0 0 0 0 0 0 0 0 0 0 | 884 | 230 229 82 230 229 82 236 236 101 230 229 82 230 229 82 230 229 82 |
| 886 | 0 0 0 0 0 0 0 0 0 0 0 0 | 885 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 887 | 0 0 0 0 0 0 0 0 0 0 0 0 | 886 | 230 229 82 230 229 82 230 229 82 230 229 82 96 95 69 71 71 57 |
| 888 | 0 0 0 0 0 0 0 0 0 0 0 0 | 887 | 36 38 35 118 116 76 118 116 76 12 15 15 15 18 18 20 24 24 |
| 889 | 0 0 0 6 6 6 14 14 14 42 42 42 | 888 | 33 37 35 55 56 53 84 83 72 110 109 94 145 141 105 110 109 94 |
| 890 | 90 90 90 18 18 18 18 18 18 26 26 26 | 889 | 168 163 120 121 119 87 156 151 111 131 127 93 87 86 72 61 63 57 |
| 891 | 2 2 6 116 116 116 253 253 253 253 253 253 | 890 | 47 48 46 28 31 30 18 22 22 15 19 19 15 18 18 15 19 19 |
| 892 | 253 253 253 253 253 253 253 253 253 253 253 253 | 891 | 15 19 19 14 18 18 14 17 17 13 17 17 13 16 16 12 15 15 |
| 893 | 253 253 253 253 253 253 250 250 250 238 238 238 | 892 | 11 13 13 10 12 12 9 11 11 8 10 10 7 9 9 3 3 3 |
| 894 | 253 253 253 253 253 253 253 253 253 253 253 253 | 893 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 895 | 253 253 253 253 253 253 253 253 253 253 253 253 | 894 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 896 | 253 253 253 253 253 253 253 253 253 253 253 253 | 895 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 897 | 253 253 253 253 253 253 253 253 253 253 253 253 | 896 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 898 | 253 253 253 253 253 253 94 94 94 6 6 6 | 897 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 899 | 2 2 6 2 2 6 10 10 10 34 34 34 | 898 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 900 | 2 2 6 2 2 6 2 2 6 2 2 6 | 899 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 901 | 74 74 74 58 58 58 22 22 22 6 6 6 | 900 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 902 | 0 0 0 0 0 0 0 0 0 0 0 0 | 901 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 903 | 0 0 0 0 0 0 0 0 0 0 0 0 | 902 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 904 | 0 0 0 0 0 0 0 0 0 0 0 0 | 903 | 0 0 0 |
| 905 | 0 0 0 0 0 0 0 0 0 0 0 0 | 904 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 906 | 0 0 0 0 0 0 0 0 0 0 0 0 | 905 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 907 | 0 0 0 0 0 0 0 0 0 0 0 0 | 906 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 908 | 0 0 0 0 0 0 0 0 0 0 0 0 | 907 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 909 | 0 0 0 10 10 10 26 26 26 66 66 66 | 908 | 0 0 0 0 0 0 0 0 0 1 1 0 230 229 82 230 229 82 |
| 910 | 82 82 82 2 2 6 38 38 38 6 6 6 | 909 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 911 | 14 14 14 210 210 210 253 253 253 253 253 253 | 910 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 912 | 253 253 253 253 253 253 253 253 253 253 253 253 | 911 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 |
| 913 | 253 253 253 253 253 253 246 246 246 242 242 242 | 912 | 161 156 96 230 229 82 118 116 76 11 14 14 14 17 17 18 22 22 |
| 914 | 253 253 253 253 253 253 253 253 253 253 253 253 | 913 | 27 30 29 40 43 41 60 60 56 84 83 72 105 104 92 110 109 94 |
| 915 | 253 253 253 253 253 253 253 253 253 253 253 253 | 914 | 110 109 94 110 109 94 99 98 80 90 89 73 68 70 65 47 48 46 |
| 916 | 253 253 253 253 253 253 253 253 253 253 253 253 | 915 | 32 34 33 23 25 24 20 23 23 17 21 21 15 19 19 14 17 17 |
| 917 | 253 253 253 253 253 253 253 253 253 253 253 253 | 916 | 15 19 19 15 18 18 14 18 18 13 17 17 13 16 16 12 15 15 |
| 918 | 253 253 253 253 253 253 144 144 144 2 2 6 | 917 | 11 14 14 10 12 12 9 11 11 8 10 10 7 9 9 4 5 5 |
| 919 | 2 2 6 2 2 6 2 2 6 46 46 46 | 918 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 920 | 2 2 6 2 2 6 2 2 6 2 2 6 | 919 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 921 | 42 42 42 74 74 74 30 30 30 10 10 10 | 920 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 922 | 0 0 0 0 0 0 0 0 0 0 0 0 | 921 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 923 | 0 0 0 0 0 0 0 0 0 0 0 0 | 922 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 924 | 0 0 0 0 0 0 0 0 0 0 0 0 | 923 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 925 | 0 0 0 0 0 0 0 0 0 0 0 0 | 924 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 926 | 0 0 0 0 0 0 0 0 0 0 0 0 | 925 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 927 | 0 0 0 0 0 0 0 0 0 0 0 0 | 926 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 928 | 0 0 0 0 0 0 0 0 0 0 0 0 | 927 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 929 | 6 6 6 14 14 14 42 42 42 90 90 90 | 928 | 0 0 0 |
| 930 | 26 26 26 6 6 6 42 42 42 2 2 6 | 929 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 931 | 74 74 74 250 250 250 253 253 253 253 253 253 | 930 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 932 | 253 253 253 253 253 253 253 253 253 253 253 253 | 931 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 933 | 253 253 253 253 253 253 242 242 242 242 242 242 | 932 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 934 | 253 253 253 253 253 253 253 253 253 253 253 253 | 933 | 0 0 0 0 0 0 0 0 0 16 17 12 230 229 82 230 229 82 |
| 935 | 253 253 253 253 253 253 253 253 253 253 253 253 | 934 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 936 | 253 253 253 253 253 253 253 253 253 253 253 253 | 935 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 937 | 253 253 253 253 253 253 253 253 253 253 253 253 | 936 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 938 | 253 253 253 253 253 253 182 182 182 2 2 6 | 937 | 230 229 82 161 156 96 118 116 76 11 13 13 13 16 16 15 19 19 |
| 939 | 2 2 6 2 2 6 2 2 6 46 46 46 | 938 | 20 24 24 30 32 31 40 43 41 51 52 50 63 64 60 72 73 67 |
| 940 | 2 2 6 2 2 6 2 2 6 2 2 6 | 939 | 65 66 61 65 66 61 65 66 61 55 57 54 46 47 45 33 37 35 |
| 941 | 10 10 10 86 86 86 38 38 38 10 10 10 | 940 | 27 29 28 20 24 24 17 21 21 16 20 20 16 20 20 15 19 19 |
| 942 | 0 0 0 0 0 0 0 0 0 0 0 0 | 941 | 15 19 19 15 19 19 14 18 18 14 17 17 13 16 16 12 15 15 |
| 943 | 0 0 0 0 0 0 0 0 0 0 0 0 | 942 | 11 14 14 10 13 13 9 12 12 8 10 10 7 9 9 6 7 7 |
| 944 | 0 0 0 0 0 0 0 0 0 0 0 0 | 943 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 945 | 0 0 0 0 0 0 0 0 0 0 0 0 | 944 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 946 | 0 0 0 0 0 0 0 0 0 0 0 0 | 945 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 947 | 0 0 0 0 0 0 0 0 0 0 0 0 | 946 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 948 | 0 0 0 0 0 0 0 0 0 0 0 0 | 947 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 949 | 10 10 10 26 26 26 66 66 66 82 82 82 | 948 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 950 | 2 2 6 22 22 22 18 18 18 2 2 6 | 949 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 951 | 149 149 149 253 253 253 253 253 253 253 253 253 | 950 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 952 | 253 253 253 253 253 253 253 253 253 253 253 253 | 951 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 953 | 253 253 253 253 253 253 234 234 234 242 242 242 | 952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 954 | 253 253 253 253 253 253 253 253 253 253 253 253 | 953 | 0 0 0 |
| 955 | 253 253 253 253 253 253 253 253 253 253 253 253 | 954 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 956 | 253 253 253 253 253 253 253 253 253 253 253 253 | 955 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 957 | 253 253 253 253 253 253 253 253 253 253 253 253 | 956 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 958 | 253 253 253 253 253 253 206 206 206 2 2 6 | 957 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 959 | 2 2 6 2 2 6 2 2 6 38 38 38 | 958 | 0 0 0 0 0 0 0 0 0 53 55 47 230 229 82 230 229 82 |
| 960 | 2 2 6 2 2 6 2 2 6 2 2 6 | 959 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 961 | 6 6 6 86 86 86 46 46 46 14 14 14 | 960 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 962 | 0 0 0 0 0 0 0 0 0 0 0 0 | 961 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 963 | 0 0 0 0 0 0 0 0 0 0 0 0 | 962 | 161 156 96 118 116 76 53 55 47 10 13 13 12 15 15 14 17 17 |
| 964 | 0 0 0 0 0 0 0 0 0 0 0 0 | 963 | 17 20 20 20 24 24 27 29 28 32 34 33 37 39 37 40 43 41 |
| 965 | 0 0 0 0 0 0 0 0 0 0 0 0 | 964 | 43 45 43 41 42 42 35 37 36 30 32 31 28 31 30 23 27 26 |
| 966 | 0 0 0 0 0 0 0 0 0 0 0 0 | 965 | 20 23 23 17 21 21 16 20 20 16 20 20 16 20 20 16 19 19 |
| 967 | 0 0 0 0 0 0 0 0 0 0 0 0 | 966 | 15 19 19 15 19 19 14 18 18 14 17 17 13 16 16 12 15 15 |
| 968 | 0 0 0 0 0 0 0 0 0 6 6 6 | 967 | 11 14 14 10 13 13 9 12 12 9 11 11 8 10 10 10 12 12 |
| 969 | 18 18 18 46 46 46 86 86 86 18 18 18 | 968 | 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 970 | 2 2 6 34 34 34 10 10 10 6 6 6 | 969 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 971 | 210 210 210 253 253 253 253 253 253 253 253 253 | 970 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 972 | 253 253 253 253 253 253 253 253 253 253 253 253 | 971 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 973 | 253 253 253 253 253 253 234 234 234 242 242 242 | 972 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 974 | 253 253 253 253 253 253 253 253 253 253 253 253 | 973 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 975 | 253 253 253 253 253 253 253 253 253 253 253 253 | 974 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 976 | 253 253 253 253 253 253 253 253 253 253 253 253 | 975 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 977 | 253 253 253 253 253 253 253 253 253 253 253 253 | 976 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 978 | 253 253 253 253 253 253 221 221 221 6 6 6 | 977 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 979 | 2 2 6 2 2 6 6 6 6 30 30 30 | 978 | 0 0 0 |
| 980 | 2 2 6 2 2 6 2 2 6 2 2 6 | 979 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 981 | 2 2 6 82 82 82 54 54 54 18 18 18 | 980 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 982 | 6 6 6 0 0 0 0 0 0 0 0 0 | 981 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 983 | 0 0 0 0 0 0 0 0 0 0 0 0 | 982 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 984 | 0 0 0 0 0 0 0 0 0 0 0 0 | 983 | 0 0 0 0 0 0 0 0 0 82 81 62 230 229 82 230 229 82 |
| 985 | 0 0 0 0 0 0 0 0 0 0 0 0 | 984 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 986 | 0 0 0 0 0 0 0 0 0 0 0 0 | 985 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 987 | 0 0 0 0 0 0 0 0 0 0 0 0 | 986 | 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 161 156 96 |
| 988 | 0 0 0 0 0 0 0 0 0 10 10 10 | 987 | 118 116 76 82 81 62 13 14 12 10 13 13 12 15 15 13 17 17 |
| 989 | 26 26 26 66 66 66 62 62 62 2 2 6 | 988 | 15 19 19 16 20 20 20 23 23 20 24 24 23 27 26 26 28 27 |
| 990 | 2 2 6 38 38 38 10 10 10 26 26 26 | 989 | 26 28 27 26 28 27 23 27 26 18 22 22 20 23 23 17 21 21 |
| 991 | 238 238 238 253 253 253 253 253 253 253 253 253 | 990 | 17 21 21 16 20 20 16 20 20 16 20 20 16 20 20 16 19 19 |
| 992 | 253 253 253 253 253 253 253 253 253 253 253 253 | 991 | 15 19 19 15 19 19 15 18 18 14 17 17 13 17 17 13 16 16 |
| 993 | 253 253 253 253 253 253 231 231 231 238 238 238 | 992 | 12 15 15 12 14 14 12 14 14 12 14 14 12 14 14 23 24 24 |
| 994 | 253 253 253 253 253 253 253 253 253 253 253 253 | 993 | 6 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 995 | 253 253 253 253 253 253 253 253 253 253 253 253 | 994 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 996 | 253 253 253 253 253 253 253 253 253 253 253 253 | 995 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 997 | 253 253 253 253 253 253 253 253 253 253 253 253 | 996 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 998 | 253 253 253 253 253 253 231 231 231 6 6 6 | 997 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 999 | 2 2 6 2 2 6 10 10 10 30 30 30 | 998 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1000 | 2 2 6 2 2 6 2 2 6 2 2 6 | 999 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1001 | 2 2 6 66 66 66 58 58 58 22 22 22 | 1000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1002 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1001 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1003 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1002 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1004 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1003 | 0 0 0 |
| 1005 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1004 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1006 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1005 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1007 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1006 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1008 | 0 0 0 0 0 0 0 0 0 10 10 10 | 1007 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1009 | 38 38 38 78 78 78 6 6 6 2 2 6 | 1008 | 0 0 0 0 0 0 0 0 0 118 116 76 230 229 82 230 229 82 |
| 1010 | 2 2 6 46 46 46 14 14 14 42 42 42 | 1009 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 1011 | 246 246 246 253 253 253 253 253 253 253 253 253 | 1010 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 1012 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1011 | 230 229 82 230 229 82 230 229 82 161 156 96 161 156 96 118 116 76 |
| 1013 | 253 253 253 253 253 253 231 231 231 242 242 242 | 1012 | 71 71 57 13 14 12 9 12 12 10 13 13 12 15 15 13 17 17 |
| 1014 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1013 | 15 18 18 15 19 19 16 20 20 17 21 21 17 21 21 18 22 22 |
| 1015 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1014 | 18 22 22 18 22 22 17 21 21 16 19 19 15 18 18 14 18 18 |
| 1016 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1015 | 16 19 19 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1017 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1016 | 15 19 19 15 19 19 15 18 18 14 18 18 16 20 20 23 25 24 |
| 1018 | 253 253 253 253 253 253 234 234 234 10 10 10 | 1017 | 17 21 21 25 27 26 47 48 46 47 48 46 51 52 50 72 73 67 |
| 1019 | 2 2 6 2 2 6 22 22 22 14 14 14 | 1018 | 33 36 34 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1020 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1019 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1021 | 2 2 6 66 66 66 62 62 62 22 22 22 | 1020 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1022 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1021 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1023 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1022 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1024 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1023 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1025 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1024 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1026 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1025 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1027 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1026 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1028 | 0 0 0 0 0 0 6 6 6 18 18 18 | 1027 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1029 | 50 50 50 74 74 74 2 2 6 2 2 6 | 1028 | 0 0 0 |
| 1030 | 14 14 14 70 70 70 34 34 34 62 62 62 | 1029 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1031 | 250 250 250 253 253 253 253 253 253 253 253 253 | 1030 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1032 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1031 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1033 | 253 253 253 253 253 253 231 231 231 246 246 246 | 1032 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1034 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1033 | 0 0 0 0 0 0 0 0 0 118 116 76 230 229 82 230 229 82 |
| 1035 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1034 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 1036 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1035 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 1037 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1036 | 230 229 82 230 229 82 161 156 96 118 116 76 118 116 76 46 47 43 |
| 1038 | 253 253 253 253 253 253 234 234 234 14 14 14 | 1037 | 9 11 11 9 11 11 10 12 12 11 13 13 12 15 15 14 17 17 |
| 1039 | 2 2 6 2 2 6 30 30 30 2 2 6 | 1038 | 15 18 18 15 19 19 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1040 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1039 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1041 | 2 2 6 66 66 66 62 62 62 22 22 22 | 1040 | 15 19 19 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1042 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1041 | 15 19 19 16 20 20 20 24 24 55 56 53 32 34 33 84 83 72 |
| 1043 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1042 | 90 89 73 110 109 94 110 109 94 105 104 92 110 109 94 110 109 94 |
| 1044 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1043 | 72 73 67 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1045 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1044 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1046 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1045 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1047 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1046 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1048 | 0 0 0 0 0 0 6 6 6 18 18 18 | 1047 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1049 | 54 54 54 62 62 62 2 2 6 2 2 6 | 1048 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1050 | 2 2 6 30 30 30 46 46 46 70 70 70 | 1049 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1051 | 250 250 250 253 253 253 253 253 253 253 253 253 | 1050 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1052 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1051 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1053 | 253 253 253 253 253 253 231 231 231 246 246 246 | 1052 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1054 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1053 | 0 0 0 |
| 1055 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1054 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1056 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1055 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1057 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1056 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1058 | 253 253 253 253 253 253 226 226 226 10 10 10 | 1057 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1059 | 2 2 6 6 6 6 30 30 30 2 2 6 | 1058 | 0 0 0 0 0 0 0 0 0 96 95 69 230 229 82 230 229 82 |
| 1060 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1059 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 1061 | 2 2 6 66 66 66 58 58 58 22 22 22 | 1060 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 1062 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1061 | 230 229 82 161 156 96 118 116 76 82 81 62 16 17 12 9 11 11 |
| 1063 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1062 | 9 11 11 9 12 12 10 13 13 12 14 14 13 16 16 14 18 18 |
| 1064 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1063 | 15 19 19 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1065 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1064 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1066 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1065 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1067 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1066 | 16 19 19 33 36 34 99 98 80 156 151 111 145 141 105 184 179 149 |
| 1068 | 0 0 0 0 0 0 6 6 6 22 22 22 | 1067 | 168 163 120 184 179 149 177 172 135 156 151 111 145 141 105 110 109 94 |
| 1069 | 58 58 58 62 62 62 2 2 6 2 2 6 | 1068 | 90 89 73 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1070 | 2 2 6 2 2 6 30 30 30 78 78 78 | 1069 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1071 | 250 250 250 253 253 253 253 253 253 253 253 253 | 1070 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1072 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1071 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1073 | 253 253 253 253 253 253 231 231 231 246 246 246 | 1072 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1074 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1073 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1075 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1074 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1076 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1075 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1077 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1076 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1078 | 253 253 253 253 253 253 206 206 206 2 2 6 | 1077 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1079 | 22 22 22 34 34 34 18 14 6 22 22 22 | 1078 | 0 0 0 |
| 1080 | 26 26 26 18 18 18 6 6 6 2 2 6 | 1079 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1081 | 2 2 6 82 82 82 54 54 54 18 18 18 | 1080 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1082 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1081 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1083 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1082 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1084 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1083 | 0 0 0 0 0 0 0 0 0 71 71 57 230 229 82 230 229 82 |
| 1085 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1084 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 |
| 1086 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1085 | 230 229 82 161 156 96 230 229 82 230 229 82 230 229 82 161 156 96 |
| 1087 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1086 | 118 116 76 82 81 62 30 31 28 9 11 11 9 11 11 9 11 11 |
| 1088 | 0 0 0 0 0 0 6 6 6 26 26 26 | 1087 | 10 12 12 10 13 13 11 14 14 13 16 16 14 17 17 15 18 18 |
| 1089 | 62 62 62 106 106 106 74 54 14 185 133 11 | 1088 | 15 19 19 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1090 | 210 162 10 121 92 8 6 6 6 62 62 62 | 1089 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1091 | 238 238 238 253 253 253 253 253 253 253 253 253 | 1090 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1092 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1091 | 18 22 22 58 59 55 137 133 100 197 193 154 214 212 158 210 208 158 |
| 1093 | 253 253 253 253 253 253 231 231 231 246 246 246 | 1092 | 197 193 154 184 179 149 184 179 149 137 133 100 110 109 94 99 98 80 |
| 1094 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1093 | 84 83 72 10 10 9 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1095 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1094 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1096 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1095 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1097 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1096 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1098 | 253 253 253 253 253 253 158 158 158 18 18 18 | 1097 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1099 | 14 14 14 2 2 6 2 2 6 2 2 6 | 1098 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1100 | 6 6 6 18 18 18 66 66 66 38 38 38 | 1099 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1101 | 6 6 6 94 94 94 50 50 50 18 18 18 | 1100 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1102 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1101 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1103 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1102 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1104 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1103 | 0 0 0 |
| 1105 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1104 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1106 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1105 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1107 | 0 0 0 0 0 0 0 0 0 6 6 6 | 1106 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1108 | 10 10 10 10 10 10 18 18 18 38 38 38 | 1107 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1109 | 78 78 78 142 134 106 216 158 10 242 186 14 | 1108 | 0 0 0 0 0 0 0 0 0 16 17 12 230 229 82 230 229 82 |
| 1110 | 246 190 14 246 190 14 156 118 10 10 10 10 | 1109 | 230 229 82 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 |
| 1111 | 90 90 90 238 238 238 253 253 253 253 253 253 | 1110 | 161 156 96 161 156 96 161 156 96 161 156 96 118 116 76 71 71 57 |
| 1112 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1111 | 21 22 20 12 14 14 11 13 13 10 12 12 10 12 12 10 13 13 |
| 1113 | 253 253 253 253 253 253 231 231 231 250 250 250 | 1112 | 11 13 13 12 15 15 13 16 16 14 17 17 14 18 18 15 19 19 |
| 1114 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1113 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1115 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1114 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1116 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1115 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 17 21 21 |
| 1117 | 253 253 253 253 253 253 253 253 253 246 230 190 | 1116 | 23 27 26 84 83 72 184 179 149 251 251 187 210 208 158 184 179 149 |
| 1118 | 238 204 91 238 204 91 181 142 44 37 26 9 | 1117 | 184 179 149 156 151 111 110 109 94 84 83 72 63 64 60 51 52 50 |
| 1119 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1118 | 18 22 22 6 8 8 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1120 | 2 2 6 2 2 6 38 38 38 46 46 46 | 1119 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1121 | 26 26 26 106 106 106 54 54 54 18 18 18 | 1120 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1122 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1121 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1123 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1122 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1124 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1123 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1125 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1124 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1126 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1125 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1127 | 0 0 0 6 6 6 14 14 14 22 22 22 | 1126 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1128 | 30 30 30 38 38 38 50 50 50 70 70 70 | 1127 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1129 | 106 106 106 190 142 34 226 170 11 242 186 14 | 1128 | 0 0 0 |
| 1130 | 246 190 14 246 190 14 246 190 14 154 114 10 | 1129 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1131 | 6 6 6 74 74 74 226 226 226 253 253 253 | 1130 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1132 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1131 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1133 | 253 253 253 253 253 253 231 231 231 250 250 250 | 1132 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1134 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1133 | 0 0 0 0 0 0 0 0 0 0 0 0 118 116 76 230 229 82 |
| 1135 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1134 | 230 229 82 230 229 82 230 229 82 230 229 82 161 156 96 161 156 96 |
| 1136 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1135 | 161 156 96 161 156 96 118 116 76 53 55 47 20 23 22 16 19 19 |
| 1137 | 253 253 253 253 253 253 253 253 253 228 184 62 | 1136 | 13 16 16 12 15 15 12 14 14 11 14 14 11 14 14 11 14 14 |
| 1138 | 241 196 14 241 208 19 232 195 16 38 30 10 | 1137 | 12 15 15 13 16 16 14 17 17 15 19 19 16 20 20 17 21 21 |
| 1139 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1138 | 23 27 26 18 22 22 20 24 24 23 27 26 30 32 31 17 21 21 |
| 1140 | 2 2 6 6 6 6 30 30 30 26 26 26 | 1139 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1141 | 203 166 17 154 142 90 66 66 66 26 26 26 | 1140 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1142 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1141 | 23 27 26 33 37 35 137 133 100 156 151 111 158 153 112 105 104 92 |
| 1143 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1142 | 105 104 92 68 70 65 39 40 39 18 22 22 12 14 14 12 15 15 |
| 1144 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1143 | 9 11 11 4 5 5 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1145 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1144 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1146 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1145 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1147 | 6 6 6 18 18 18 38 38 38 58 58 58 | 1146 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1148 | 78 78 78 86 86 86 101 101 101 123 123 123 | 1147 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1149 | 175 146 61 210 150 10 234 174 13 246 186 14 | 1148 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1150 | 246 190 14 246 190 14 246 190 14 238 190 10 | 1149 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1151 | 102 78 10 2 2 6 46 46 46 198 198 198 | 1150 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1152 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1151 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1153 | 253 253 253 253 253 253 234 234 234 242 242 242 | 1152 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1154 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1153 | 0 0 0 |
| 1155 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1154 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1156 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1155 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1157 | 253 253 253 253 253 253 253 253 253 224 178 62 | 1156 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1158 | 242 186 14 241 196 14 210 166 10 22 18 6 | 1157 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1159 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1158 | 0 0 0 0 0 0 0 0 0 0 0 0 16 17 12 230 229 82 |
| 1160 | 2 2 6 2 2 6 6 6 6 121 92 8 | 1159 | 230 229 82 230 229 82 230 229 82 161 156 96 118 116 76 118 116 76 |
| 1161 | 238 202 15 232 195 16 82 82 82 34 34 34 | 1160 | 118 116 76 66 65 55 43 45 43 32 34 33 25 27 26 20 23 22 |
| 1162 | 10 10 10 0 0 0 0 0 0 0 0 0 | 1161 | 17 20 20 15 18 18 14 17 17 15 18 18 13 16 16 14 17 17 |
| 1163 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1162 | 14 18 18 16 20 20 32 34 33 55 57 54 58 59 55 72 73 67 |
| 1164 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1163 | 105 104 92 55 57 54 65 66 61 63 64 60 40 43 41 33 37 35 |
| 1165 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1164 | 41 42 42 20 24 24 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1166 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1165 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1167 | 14 14 14 38 38 38 70 70 70 154 122 46 | 1166 | 17 21 21 26 28 27 30 32 31 35 37 36 68 70 65 39 40 39 |
| 1168 | 190 142 34 200 144 11 197 138 11 197 138 11 | 1167 | 23 27 26 15 18 18 13 16 16 11 14 14 9 12 12 8 10 10 |
| 1169 | 213 154 11 226 170 11 242 186 14 246 190 14 | 1168 | 7 9 9 6 7 7 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1170 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1169 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1171 | 225 175 15 46 32 6 2 2 6 22 22 22 | 1170 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1172 | 158 158 158 250 250 250 253 253 253 253 253 253 | 1171 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1173 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1172 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1174 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1173 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1175 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1174 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1176 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1175 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1177 | 253 253 253 250 250 250 242 242 242 224 178 62 | 1176 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1178 | 239 182 13 236 186 11 213 154 11 46 32 6 | 1177 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1179 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1178 | 0 0 0 |
| 1180 | 2 2 6 2 2 6 61 42 6 225 175 15 | 1179 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1181 | 238 190 10 236 186 11 112 100 78 42 42 42 | 1180 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1182 | 14 14 14 0 0 0 0 0 0 0 0 0 | 1181 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1183 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1182 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1184 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 38 35 |
| 1185 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1184 | 230 229 82 230 229 82 230 229 82 96 95 69 30 31 28 49 51 48 |
| 1186 | 0 0 0 0 0 0 0 0 0 6 6 6 | 1185 | 90 89 73 68 70 65 55 57 54 47 48 46 47 48 46 43 45 43 |
| 1187 | 22 22 22 54 54 54 154 122 46 213 154 11 | 1186 | 32 34 33 43 45 43 43 45 43 23 27 26 25 27 26 40 43 41 |
| 1188 | 226 170 11 230 174 11 226 170 11 226 170 11 | 1187 | 40 43 41 90 89 73 110 109 94 145 141 105 156 151 111 156 151 111 |
| 1189 | 236 178 12 242 186 14 246 190 14 246 190 14 | 1188 | 184 179 149 184 179 149 177 172 135 184 179 149 137 133 100 84 83 72 |
| 1190 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1189 | 105 104 92 63 64 60 49 51 48 47 48 46 28 31 30 18 22 22 |
| 1191 | 241 196 14 184 144 12 10 10 10 2 2 6 | 1190 | 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1192 | 6 6 6 116 116 116 242 242 242 253 253 253 | 1191 | 16 20 20 15 19 19 15 19 19 15 19 19 18 22 22 15 19 19 |
| 1193 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1192 | 13 16 16 12 15 15 11 14 14 10 13 13 9 12 12 9 11 11 |
| 1194 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1193 | 8 10 10 6 8 8 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1195 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1194 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1196 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1195 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1197 | 253 253 253 231 231 231 198 198 198 214 170 54 | 1196 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1198 | 236 178 12 236 178 12 210 150 10 137 92 6 | 1197 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1199 | 18 14 6 2 2 6 2 2 6 2 2 6 | 1198 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1200 | 6 6 6 70 47 6 200 144 11 236 178 12 | 1199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1201 | 239 182 13 239 182 13 124 112 88 58 58 58 | 1200 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1202 | 22 22 22 6 6 6 0 0 0 0 0 0 | 1201 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1203 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1202 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1204 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1203 | 0 0 0 |
| 1205 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1204 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1206 | 0 0 0 0 0 0 0 0 0 10 10 10 | 1205 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1207 | 30 30 30 70 70 70 180 133 36 226 170 11 | 1206 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1208 | 239 182 13 242 186 14 242 186 14 246 186 14 | 1207 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1209 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1208 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1210 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1209 | 30 31 28 230 229 82 71 71 57 2 2 1 0 0 0 58 59 55 |
| 1211 | 246 190 14 232 195 16 98 70 6 2 2 6 | 1210 | 105 104 92 84 83 72 65 66 61 84 83 72 110 109 94 110 109 94 |
| 1212 | 2 2 6 2 2 6 66 66 66 221 221 221 | 1211 | 145 141 105 105 104 92 110 109 94 110 109 94 84 83 72 110 109 94 |
| 1213 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1212 | 158 153 112 197 193 154 197 193 154 239 239 170 251 251 187 251 251 187 |
| 1214 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1213 | 251 251 187 251 251 187 251 251 187 251 251 187 210 208 158 197 193 154 |
| 1215 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1214 | 197 193 154 184 179 149 145 141 105 137 133 100 105 104 92 47 48 46 |
| 1216 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1215 | 20 23 23 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1217 | 253 253 253 206 206 206 198 198 198 214 166 58 | 1216 | 16 20 20 16 19 19 15 19 19 15 19 19 14 18 18 14 17 17 |
| 1218 | 230 174 11 230 174 11 216 158 10 192 133 9 | 1217 | 13 17 17 13 16 16 12 14 14 12 14 14 13 13 13 13 13 13 |
| 1219 | 163 110 8 116 81 8 102 78 10 116 81 8 | 1218 | 13 13 13 12 12 12 10 10 9 6 7 7 2 2 2 0 0 0 |
| 1220 | 167 114 7 197 138 11 226 170 11 239 182 13 | 1219 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1221 | 242 186 14 242 186 14 162 146 94 78 78 78 | 1220 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1222 | 34 34 34 14 14 14 6 6 6 0 0 0 | 1221 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1223 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1222 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1224 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1223 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1225 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1224 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1226 | 0 0 0 0 0 0 0 0 0 6 6 6 | 1225 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1227 | 30 30 30 78 78 78 190 142 34 226 170 11 | 1226 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1228 | 239 182 13 246 190 14 246 190 14 246 190 14 | 1227 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1229 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1228 | 0 0 0 |
| 1230 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1229 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1231 | 246 190 14 241 196 14 203 166 17 22 18 6 | 1230 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1232 | 2 2 6 2 2 6 2 2 6 38 38 38 | 1231 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1233 | 218 218 218 253 253 253 253 253 253 253 253 253 | 1232 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1234 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1233 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1235 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1234 | 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 65 66 61 |
| 1236 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1235 | 105 104 92 84 83 72 84 83 72 110 109 94 184 179 149 210 208 158 |
| 1237 | 250 250 250 206 206 206 198 198 198 202 162 69 | 1236 | 210 208 158 210 208 158 214 212 158 197 193 154 214 212 158 210 208 158 |
| 1238 | 226 170 11 236 178 12 224 166 10 210 150 10 | 1237 | 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 |
| 1239 | 200 144 11 197 138 11 192 133 9 197 138 11 | 1238 | 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 |
| 1240 | 210 150 10 226 170 11 242 186 14 246 190 14 | 1239 | 251 251 187 251 251 187 239 239 170 251 251 187 184 179 149 84 83 72 |
| 1241 | 246 190 14 246 186 14 225 175 15 124 112 88 | 1240 | 26 28 27 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1242 | 62 62 62 30 30 30 14 14 14 6 6 6 | 1241 | 16 20 20 16 20 20 15 19 19 15 19 19 15 18 18 14 18 18 |
| 1243 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1242 | 13 17 17 13 16 16 15 15 15 14 14 13 14 14 13 14 14 13 |
| 1244 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1243 | 13 13 13 13 13 13 12 12 12 12 12 12 12 12 12 3 4 4 |
| 1245 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1244 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1246 | 0 0 0 0 0 0 0 0 0 10 10 10 | 1245 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1247 | 30 30 30 78 78 78 174 135 50 224 166 10 | 1246 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1248 | 239 182 13 246 190 14 246 190 14 246 190 14 | 1247 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1249 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1248 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1250 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1249 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1251 | 246 190 14 246 190 14 241 196 14 139 102 15 | 1250 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1252 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1251 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1253 | 78 78 78 250 250 250 253 253 253 253 253 253 | 1252 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1254 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1253 | 0 0 0 |
| 1255 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1254 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1256 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1257 | 250 250 250 214 214 214 198 198 198 190 150 46 | 1256 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1258 | 219 162 10 236 178 12 234 174 13 224 166 10 | 1257 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1259 | 216 158 10 213 154 11 213 154 11 216 158 10 | 1258 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1260 | 226 170 11 239 182 13 246 190 14 246 190 14 | 1259 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 72 73 67 |
| 1261 | 246 190 14 246 190 14 242 186 14 206 162 42 | 1260 | 105 104 92 99 98 80 84 83 72 99 98 80 177 172 135 197 193 154 |
| 1262 | 101 101 101 58 58 58 30 30 30 14 14 14 | 1261 | 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 |
| 1263 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1262 | 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 |
| 1264 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1263 | 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 |
| 1265 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1264 | 251 251 187 251 251 187 251 251 187 214 212 158 197 193 154 99 98 80 |
| 1266 | 0 0 0 0 0 0 0 0 0 10 10 10 | 1265 | 23 27 26 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1267 | 30 30 30 74 74 74 174 135 50 216 158 10 | 1266 | 16 20 20 16 20 20 15 19 19 15 19 19 15 18 18 14 18 18 |
| 1268 | 236 178 12 246 190 14 246 190 14 246 190 14 | 1267 | 14 17 17 16 16 16 16 16 16 16 16 16 15 15 15 14 14 13 |
| 1269 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1268 | 14 14 13 13 13 13 13 13 13 12 12 12 12 12 12 12 12 12 |
| 1270 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1269 | 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1271 | 246 190 14 246 190 14 241 196 14 226 184 13 | 1270 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1272 | 61 42 6 2 2 6 2 2 6 2 2 6 | 1271 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1273 | 22 22 22 238 238 238 253 253 253 253 253 253 | 1272 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1274 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1273 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1275 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1274 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1276 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1275 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1277 | 253 253 253 226 226 226 187 187 187 180 133 36 | 1276 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1278 | 216 158 10 236 178 12 239 182 13 236 178 12 | 1277 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1279 | 230 174 11 226 170 11 226 170 11 230 174 11 | 1278 | 0 0 0 |
| 1280 | 236 178 12 242 186 14 246 190 14 246 190 14 | 1279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1281 | 246 190 14 246 190 14 246 186 14 239 182 13 | 1280 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1282 | 206 162 42 106 106 106 66 66 66 34 34 34 | 1281 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1283 | 14 14 14 6 6 6 0 0 0 0 0 0 | 1282 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1284 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1283 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1285 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1284 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 84 83 72 |
| 1286 | 0 0 0 0 0 0 0 0 0 6 6 6 | 1285 | 110 109 94 99 98 80 72 73 67 63 64 60 99 98 80 177 172 135 |
| 1287 | 26 26 26 70 70 70 163 133 67 213 154 11 | 1286 | 184 179 149 210 208 158 251 251 187 251 251 187 251 251 187 251 251 187 |
| 1288 | 236 178 12 246 190 14 246 190 14 246 190 14 | 1287 | 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 |
| 1289 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1288 | 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 |
| 1290 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1289 | 251 251 187 210 208 158 184 179 149 177 172 135 110 109 94 33 37 35 |
| 1291 | 246 190 14 246 190 14 246 190 14 241 196 14 | 1290 | 17 21 21 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1292 | 190 146 13 18 14 6 2 2 6 2 2 6 | 1291 | 16 20 20 16 20 20 15 19 19 15 19 19 15 19 19 14 18 18 |
| 1293 | 46 46 46 246 246 246 253 253 253 253 253 253 | 1292 | 15 18 18 18 19 18 18 19 18 17 17 17 16 16 16 15 15 15 |
| 1294 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1293 | 14 14 13 13 13 13 13 13 13 12 12 12 12 12 12 12 12 12 |
| 1295 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1294 | 10 10 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1296 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1295 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1297 | 253 253 253 221 221 221 86 86 86 156 107 11 | 1296 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1298 | 216 158 10 236 178 12 242 186 14 246 186 14 | 1297 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1299 | 242 186 14 239 182 13 239 182 13 242 186 14 | 1298 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1300 | 242 186 14 246 186 14 246 190 14 246 190 14 | 1299 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1301 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1300 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1302 | 242 186 14 225 175 15 142 122 72 66 66 66 | 1301 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1303 | 30 30 30 10 10 10 0 0 0 0 0 0 | 1302 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1304 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1303 | 0 0 0 |
| 1305 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1304 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1306 | 0 0 0 0 0 0 0 0 0 6 6 6 | 1305 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1307 | 26 26 26 70 70 70 163 133 67 210 150 10 | 1306 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1308 | 236 178 12 246 190 14 246 190 14 246 190 14 | 1307 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1309 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1308 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1310 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1309 | 0 0 0 0 0 0 0 0 0 0 0 0 2 2 2 105 104 92 |
| 1311 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1310 | 108 107 93 99 98 80 72 73 67 63 64 60 51 52 50 87 86 72 |
| 1312 | 232 195 16 121 92 8 34 34 34 106 106 106 | 1311 | 105 104 92 110 109 94 108 107 93 156 151 111 184 179 149 184 179 149 |
| 1313 | 221 221 221 253 253 253 253 253 253 253 253 253 | 1312 | 197 193 154 197 193 154 197 193 154 184 179 149 184 179 149 177 172 135 |
| 1314 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1313 | 197 193 154 156 151 111 177 172 135 184 179 149 168 163 120 137 133 100 |
| 1315 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1314 | 145 141 105 110 109 94 99 98 80 47 48 46 55 57 54 15 19 19 |
| 1316 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1315 | 16 19 19 16 20 20 16 20 20 16 20 20 16 20 20 16 20 20 |
| 1317 | 242 242 242 82 82 82 18 14 6 163 110 8 | 1316 | 17 20 20 17 21 21 16 20 20 16 19 19 15 19 19 16 19 19 |
| 1318 | 216 158 10 236 178 12 242 186 14 246 190 14 | 1317 | 20 20 20 21 22 21 20 20 20 19 20 19 18 19 18 16 16 16 |
| 1319 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1318 | 15 15 15 14 14 13 13 13 13 13 13 13 12 12 12 12 12 12 |
| 1320 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1319 | 12 12 12 4 5 5 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1321 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1320 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1322 | 246 190 14 246 190 14 242 186 14 163 133 67 | 1321 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1323 | 46 46 46 18 18 18 6 6 6 0 0 0 | 1322 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1324 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1323 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1325 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1324 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1326 | 0 0 0 0 0 0 0 0 0 10 10 10 | 1325 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1327 | 30 30 30 78 78 78 163 133 67 210 150 10 | 1326 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1328 | 236 178 12 246 186 14 246 190 14 246 190 14 | 1327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1329 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1328 | 0 0 0 |
| 1330 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1329 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1331 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1330 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1332 | 241 196 14 215 174 15 190 178 144 253 253 253 | 1331 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1333 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1332 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1334 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1333 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1335 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1334 | 0 0 0 0 0 0 0 0 0 0 0 0 58 59 55 110 109 94 |
| 1336 | 253 253 253 253 253 253 253 253 253 218 218 218 | 1335 | 105 104 92 90 89 73 72 73 67 55 57 54 43 45 43 39 40 39 |
| 1337 | 58 58 58 2 2 6 22 18 6 167 114 7 | 1336 | 43 45 43 46 47 45 43 45 43 68 70 65 65 66 61 63 64 60 |
| 1338 | 216 158 10 236 178 12 246 186 14 246 190 14 | 1337 | 108 107 93 72 73 67 105 104 92 90 89 73 72 73 67 40 43 41 |
| 1339 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1338 | 72 73 67 68 70 65 68 70 65 58 59 55 63 64 60 49 51 48 |
| 1340 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1339 | 43 45 43 33 36 34 27 30 29 20 24 24 16 20 20 15 19 19 |
| 1341 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1340 | 15 19 19 15 19 19 15 19 19 16 19 19 16 20 20 16 20 20 |
| 1342 | 246 190 14 246 186 14 242 186 14 190 150 46 | 1341 | 17 21 21 20 24 24 20 23 22 17 21 21 17 20 20 20 20 20 |
| 1343 | 54 54 54 22 22 22 6 6 6 0 0 0 | 1342 | 21 22 21 21 22 21 21 22 21 21 22 21 20 20 20 18 19 18 |
| 1344 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1343 | 16 16 16 15 15 15 13 13 13 13 13 13 12 12 12 12 12 12 |
| 1345 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1344 | 12 12 12 10 10 9 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1346 | 0 0 0 0 0 0 0 0 0 14 14 14 | 1345 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1347 | 38 38 38 86 86 86 180 133 36 213 154 11 | 1346 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1348 | 236 178 12 246 186 14 246 190 14 246 190 14 | 1347 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1349 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1348 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1350 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1349 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1351 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1350 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1352 | 246 190 14 232 195 16 190 146 13 214 214 214 | 1351 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1353 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1352 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1354 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1353 | 0 0 0 |
| 1355 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1354 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1356 | 253 253 253 250 250 250 170 170 170 26 26 26 | 1355 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1357 | 2 2 6 2 2 6 37 26 9 163 110 8 | 1356 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1358 | 219 162 10 239 182 13 246 186 14 246 190 14 | 1357 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1359 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1358 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1360 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1359 | 0 0 0 0 0 0 0 0 0 21 22 21 110 109 94 110 109 94 |
| 1361 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1360 | 105 104 92 84 83 72 68 70 65 51 52 50 41 42 42 33 37 35 |
| 1362 | 246 186 14 236 178 12 224 166 10 142 122 72 | 1361 | 28 31 30 23 27 26 20 23 23 18 22 22 17 20 20 25 27 26 |
| 1363 | 46 46 46 18 18 18 6 6 6 0 0 0 | 1362 | 26 28 27 27 30 29 25 27 26 20 23 23 23 27 26 30 32 31 |
| 1364 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1363 | 20 24 24 17 21 21 18 22 22 15 19 19 26 28 27 20 23 23 |
| 1365 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1364 | 14 18 18 15 19 19 15 18 18 15 19 19 15 19 19 15 19 19 |
| 1366 | 0 0 0 0 0 0 6 6 6 18 18 18 | 1365 | 15 19 19 15 19 19 15 19 19 15 19 19 15 19 19 16 19 19 |
| 1367 | 50 50 50 109 106 95 192 133 9 224 166 10 | 1366 | 16 20 20 22 24 23 24 26 24 22 24 23 20 23 22 22 24 23 |
| 1368 | 242 186 14 246 190 14 246 190 14 246 190 14 | 1367 | 24 26 24 24 26 24 23 24 24 22 24 23 21 22 21 19 20 19 |
| 1369 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1368 | 17 17 17 15 15 15 14 14 13 13 13 13 12 12 12 12 12 12 |
| 1370 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1369 | 12 12 12 12 12 12 2 2 2 0 0 0 0 0 0 0 0 0 |
| 1371 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1370 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1372 | 242 186 14 226 184 13 210 162 10 142 110 46 | 1371 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1373 | 226 226 226 253 253 253 253 253 253 253 253 253 | 1372 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1374 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1373 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1375 | 253 253 253 253 253 253 253 253 253 253 253 253 | 1374 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1376 | 198 198 198 66 66 66 2 2 6 2 2 6 | 1375 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1377 | 2 2 6 2 2 6 50 34 6 156 107 11 | 1376 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1378 | 219 162 10 239 182 13 246 186 14 246 190 14 | 1377 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1379 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1378 | 0 0 0 |
| 1380 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1379 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1381 | 246 190 14 246 190 14 246 190 14 242 186 14 | 1380 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1382 | 234 174 13 213 154 11 154 122 46 66 66 66 | 1381 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1383 | 30 30 30 10 10 10 0 0 0 0 0 0 | 1382 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1384 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1383 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1385 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1384 | 0 0 0 0 0 0 2 2 2 99 98 80 110 109 94 108 107 93 |
| 1386 | 0 0 0 0 0 0 6 6 6 22 22 22 | 1385 | 105 104 92 84 83 72 63 64 60 49 51 48 39 40 39 32 34 33 |
| 1387 | 58 58 58 154 121 60 206 145 10 234 174 13 | 1386 | 27 30 29 23 25 24 20 23 23 17 20 20 15 19 19 14 18 18 |
| 1388 | 242 186 14 246 186 14 246 190 14 246 190 14 | 1387 | 14 17 17 13 17 17 13 17 17 13 17 17 13 17 17 13 17 17 |
| 1389 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1388 | 14 17 17 14 17 17 14 17 17 14 17 17 14 17 17 14 17 17 |
| 1390 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1389 | 14 18 18 14 18 18 14 18 18 14 18 18 15 18 18 15 19 19 |
| 1391 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1390 | 15 19 19 15 19 19 15 19 19 15 19 19 15 19 19 15 19 19 |
| 1392 | 246 186 14 236 178 12 210 162 10 163 110 8 | 1391 | 15 19 19 17 21 21 27 29 28 26 28 27 25 27 26 25 27 26 |
| 1393 | 61 42 6 138 138 138 218 218 218 250 250 250 | 1392 | 27 29 28 27 29 28 26 28 27 24 26 24 21 22 21 20 20 20 |
| 1394 | 253 253 253 253 253 253 253 253 253 250 250 250 | 1393 | 18 19 18 16 16 16 14 14 13 13 13 13 12 12 12 12 12 12 |
| 1395 | 242 242 242 210 210 210 144 144 144 66 66 66 | 1394 | 12 12 12 12 12 12 4 5 5 0 0 0 0 0 0 0 0 0 |
| 1396 | 6 6 6 2 2 6 2 2 6 2 2 6 | 1395 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1397 | 2 2 6 2 2 6 61 42 6 163 110 8 | 1396 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1398 | 216 158 10 236 178 12 246 190 14 246 190 14 | 1397 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1399 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1398 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1400 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1399 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1401 | 246 190 14 239 182 13 230 174 11 216 158 10 | 1400 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1402 | 190 142 34 124 112 88 70 70 70 38 38 38 | 1401 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1403 | 18 18 18 6 6 6 0 0 0 0 0 0 | 1402 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1404 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1403 | 0 0 0 |
| 1405 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1404 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1406 | 0 0 0 0 0 0 6 6 6 22 22 22 | 1405 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1407 | 62 62 62 168 124 44 206 145 10 224 166 10 | 1406 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1408 | 236 178 12 239 182 13 242 186 14 242 186 14 | 1407 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1409 | 246 186 14 246 190 14 246 190 14 246 190 14 | 1408 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1410 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1409 | 0 0 0 0 0 0 51 52 50 110 109 94 110 109 94 105 104 92 |
| 1411 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1410 | 90 89 73 72 73 67 55 57 54 43 45 43 35 37 36 30 32 31 |
| 1412 | 246 190 14 236 178 12 216 158 10 175 118 6 | 1411 | 26 28 27 20 24 24 17 21 21 16 19 19 15 18 18 14 17 17 |
| 1413 | 80 54 7 2 2 6 6 6 6 30 30 30 | 1412 | 13 16 16 13 16 16 13 16 16 13 16 16 13 16 16 13 16 16 |
| 1414 | 54 54 54 62 62 62 50 50 50 38 38 38 | 1413 | 13 16 16 13 16 16 13 16 16 13 17 17 13 17 17 14 17 17 |
| 1415 | 14 14 14 2 2 6 2 2 6 2 2 6 | 1414 | 14 17 17 14 17 17 14 17 17 14 18 18 14 18 18 14 18 18 |
| 1416 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1415 | 15 18 18 15 18 18 15 19 19 15 19 19 15 19 19 15 19 19 |
| 1417 | 2 2 6 6 6 6 80 54 7 167 114 7 | 1416 | 15 19 19 15 19 19 27 29 28 32 34 33 28 31 30 27 29 28 |
| 1418 | 213 154 11 236 178 12 246 190 14 246 190 14 | 1417 | 30 32 31 30 32 31 30 31 28 26 28 27 23 24 24 21 22 21 |
| 1419 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1418 | 19 20 19 16 16 16 14 14 13 13 13 13 12 12 12 12 12 12 |
| 1420 | 246 190 14 242 186 14 239 182 13 239 182 13 | 1419 | 12 12 12 12 12 12 6 7 7 0 0 0 0 0 0 0 0 0 |
| 1421 | 230 174 11 210 150 10 174 135 50 124 112 88 | 1420 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1422 | 82 82 82 54 54 54 34 34 34 18 18 18 | 1421 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1423 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1422 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1424 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1423 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1425 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1424 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1426 | 0 0 0 0 0 0 6 6 6 18 18 18 | 1425 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1427 | 50 50 50 158 118 36 192 133 9 200 144 11 | 1426 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1428 | 216 158 10 219 162 10 224 166 10 226 170 11 | 1427 | 0 0 0 0 0 0 0 0 0 3 3 3 0 0 0 0 0 0 |
| 1429 | 230 174 11 236 178 12 239 182 13 239 182 13 | 1428 | 0 0 0 |
| 1430 | 242 186 14 246 186 14 246 190 14 246 190 14 | 1429 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1431 | 246 190 14 246 190 14 246 190 14 246 190 14 | 1430 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1432 | 246 186 14 230 174 11 210 150 10 163 110 8 | 1431 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1433 | 104 69 6 10 10 10 2 2 6 2 2 6 | 1432 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1434 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1433 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1435 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1434 | 0 0 0 10 10 9 108 107 93 110 109 94 108 107 93 99 98 80 |
| 1436 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1435 | 84 83 72 63 64 60 49 51 48 40 43 41 33 36 34 27 30 29 |
| 1437 | 2 2 6 6 6 6 91 60 6 167 114 7 | 1436 | 23 27 26 18 22 22 17 20 20 15 18 18 14 17 17 13 16 16 |
| 1438 | 206 145 10 230 174 11 242 186 14 246 190 14 | 1437 | 13 16 16 13 16 16 12 15 15 12 15 15 12 15 15 12 15 15 |
| 1439 | 246 190 14 246 190 14 246 186 14 242 186 14 | 1438 | 13 16 16 13 16 16 13 16 16 13 16 16 13 16 16 13 16 16 |
| 1440 | 239 182 13 230 174 11 224 166 10 213 154 11 | 1439 | 13 17 17 13 17 17 14 17 17 14 17 17 14 17 17 14 18 18 |
| 1441 | 180 133 36 124 112 88 86 86 86 58 58 58 | 1440 | 14 18 18 14 18 18 15 18 18 15 18 18 15 19 19 15 19 19 |
| 1442 | 38 38 38 22 22 22 10 10 10 6 6 6 | 1441 | 15 19 19 15 19 19 17 21 21 33 36 34 32 34 33 31 33 31 |
| 1443 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1442 | 33 36 34 33 36 34 31 33 31 27 29 28 25 27 26 21 22 21 |
| 1444 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1443 | 19 20 19 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12 |
| 1445 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1444 | 12 12 12 12 12 12 8 8 7 0 0 0 0 0 0 0 0 0 |
| 1446 | 0 0 0 0 0 0 0 0 0 14 14 14 | 1445 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1447 | 34 34 34 70 70 70 138 110 50 158 118 36 | 1446 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1448 | 167 114 7 180 123 7 192 133 9 197 138 11 | 1447 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1449 | 200 144 11 206 145 10 213 154 11 219 162 10 | 1448 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1450 | 224 166 10 230 174 11 239 182 13 242 186 14 | 1449 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1451 | 246 186 14 246 186 14 246 186 14 246 186 14 | 1450 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1452 | 239 182 13 216 158 10 185 133 11 152 99 6 | 1451 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1453 | 104 69 6 18 14 6 2 2 6 2 2 6 | 1452 | 0 0 0 0 0 0 63 64 60 137 133 100 43 45 43 0 0 0 |
| 1454 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1453 | 0 0 0 |
| 1455 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1454 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1456 | 2 2 6 2 2 6 2 2 6 2 2 6 | 1455 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1457 | 2 2 6 6 6 6 80 54 7 152 99 6 | 1456 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1458 | 192 133 9 219 162 10 236 178 12 239 182 13 | 1457 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1459 | 246 186 14 242 186 14 239 182 13 236 178 12 | 1458 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1460 | 224 166 10 206 145 10 192 133 9 154 121 60 | 1459 | 0 0 0 68 70 65 110 109 94 110 109 94 105 104 92 84 83 72 |
| 1461 | 94 94 94 62 62 62 42 42 42 22 22 22 | 1460 | 68 70 65 55 57 54 43 45 43 35 37 36 30 32 31 26 28 27 |
| 1462 | 14 14 14 6 6 6 0 0 0 0 0 0 | 1461 | 20 24 24 17 21 21 16 19 19 14 17 17 13 16 16 12 15 15 |
| 1463 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1462 | 12 15 15 12 15 15 12 15 15 12 15 15 12 15 15 12 15 15 |
| 1464 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1463 | 12 15 15 12 15 15 12 15 15 12 15 15 12 15 15 13 16 16 |
| 1465 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1464 | 13 16 16 13 16 16 13 16 16 13 17 17 13 17 17 14 17 17 |
| 1466 | 0 0 0 0 0 0 0 0 0 6 6 6 | 1465 | 14 17 17 14 17 17 14 18 18 14 18 18 14 18 18 15 18 18 |
| 1467 | 18 18 18 34 34 34 58 58 58 78 78 78 | 1466 | 15 19 19 15 19 19 15 19 19 20 24 24 32 34 33 35 37 36 |
| 1468 | 101 98 89 124 112 88 142 110 46 156 107 11 | 1467 | 37 39 37 35 37 36 33 36 34 30 32 31 26 28 27 22 24 23 |
| 1469 | 163 110 8 167 114 7 175 118 6 180 123 7 | 1468 | 20 20 20 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12 |
| 1470 | 185 133 11 197 138 11 210 150 10 219 162 10 | 1469 | 12 12 12 12 12 12 8 8 7 0 0 0 0 0 0 0 0 0 |
| 1471 | 226 170 11 236 178 12 236 178 12 234 174 13 | 1470 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1472 | 219 162 10 197 138 11 163 110 8 130 83 6 | 1471 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1473 | 91 60 6 10 10 10 2 2 6 2 2 6 | 1472 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1474 | 18 18 18 38 38 38 38 38 38 38 38 38 | 1473 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1475 | 38 38 38 38 38 38 38 38 38 38 38 38 | 1474 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1476 | 38 38 38 38 38 38 26 26 26 2 2 6 | 1475 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1477 | 2 2 6 6 6 6 70 47 6 137 92 6 | 1476 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1478 | 175 118 6 200 144 11 219 162 10 230 174 11 | 1477 | 1 1 1 99 98 80 184 179 149 184 179 149 68 70 65 0 0 0 |
| 1479 | 234 174 13 230 174 11 219 162 10 210 150 10 | 1478 | 0 0 0 |
| 1480 | 192 133 9 163 110 8 124 112 88 82 82 82 | 1479 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1481 | 50 50 50 30 30 30 14 14 14 6 6 6 | 1480 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1482 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1481 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1483 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1482 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1484 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1483 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1485 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1484 | 15 15 15 110 109 94 110 109 94 108 107 93 99 98 80 72 73 67 |
| 1486 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1485 | 61 63 57 49 51 48 39 40 39 33 36 34 27 30 29 23 25 24 |
| 1487 | 6 6 6 14 14 14 22 22 22 34 34 34 | 1486 | 18 22 22 16 19 19 14 17 17 13 16 16 12 15 15 12 15 15 |
| 1488 | 42 42 42 58 58 58 74 74 74 86 86 86 | 1487 | 11 14 14 11 14 14 11 14 14 11 14 14 11 14 14 11 14 14 |
| 1489 | 101 98 89 122 102 70 130 98 46 121 87 25 | 1488 | 11 14 14 11 14 14 12 14 14 12 15 15 12 15 15 12 15 15 |
| 1490 | 137 92 6 152 99 6 163 110 8 180 123 7 | 1489 | 12 15 15 13 16 16 13 16 16 13 16 16 13 16 16 13 16 16 |
| 1491 | 185 133 11 197 138 11 206 145 10 200 144 11 | 1490 | 13 17 17 14 17 17 14 17 17 14 17 17 14 18 18 14 18 18 |
| 1492 | 180 123 7 156 107 11 130 83 6 104 69 6 | 1491 | 14 18 18 15 18 18 15 19 19 15 19 19 30 32 31 38 39 37 |
| 1493 | 50 34 6 54 54 54 110 110 110 101 98 89 | 1492 | 39 40 39 39 40 39 35 37 36 31 33 31 27 29 28 22 24 23 |
| 1494 | 86 86 86 82 82 82 78 78 78 78 78 78 | 1493 | 20 20 20 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12 |
| 1495 | 78 78 78 78 78 78 78 78 78 78 78 78 | 1494 | 12 12 12 12 12 12 8 8 7 0 0 0 0 0 0 0 0 0 |
| 1496 | 78 78 78 82 82 82 86 86 86 94 94 94 | 1495 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1497 | 106 106 106 101 101 101 86 66 34 124 80 6 | 1496 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1498 | 156 107 11 180 123 7 192 133 9 200 144 11 | 1497 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1499 | 206 145 10 200 144 11 192 133 9 175 118 6 | 1498 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1500 | 139 102 15 109 106 95 70 70 70 42 42 42 | 1499 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1501 | 22 22 22 10 10 10 0 0 0 0 0 0 | 1500 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1502 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1501 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 3 3 |
| 1503 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1502 | 110 109 94 197 193 154 210 208 158 184 179 149 68 70 65 0 0 0 |
| 1504 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1503 | 0 0 0 |
| 1505 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1504 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1506 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1505 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1507 | 0 0 0 0 0 0 6 6 6 10 10 10 | 1506 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1508 | 14 14 14 22 22 22 30 30 30 38 38 38 | 1507 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1509 | 50 50 50 62 62 62 74 74 74 90 90 90 | 1508 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1510 | 101 98 89 112 100 78 121 87 25 124 80 6 | 1509 | 68 70 65 110 109 94 110 109 94 105 104 92 84 83 72 65 66 61 |
| 1511 | 137 92 6 152 99 6 152 99 6 152 99 6 | 1510 | 51 52 50 43 45 43 35 37 36 30 32 31 25 27 26 20 23 23 |
| 1512 | 138 86 6 124 80 6 98 70 6 86 66 30 | 1511 | 17 20 20 15 18 18 13 16 16 12 15 15 12 15 15 11 14 14 |
| 1513 | 101 98 89 82 82 82 58 58 58 46 46 46 | 1512 | 11 14 14 11 14 14 11 13 13 11 13 13 11 13 13 11 13 13 |
| 1514 | 38 38 38 34 34 34 34 34 34 34 34 34 | 1513 | 11 14 14 11 14 14 11 14 14 11 14 14 11 14 14 11 14 14 |
| 1515 | 34 34 34 34 34 34 34 34 34 34 34 34 | 1514 | 12 15 15 12 15 15 12 15 15 12 15 15 13 16 16 13 16 16 |
| 1516 | 34 34 34 34 34 34 38 38 38 42 42 42 | 1515 | 13 16 16 13 16 16 13 17 17 13 17 17 14 17 17 14 17 17 |
| 1517 | 54 54 54 82 82 82 94 86 76 91 60 6 | 1516 | 14 18 18 14 18 18 14 18 18 16 19 19 37 39 37 41 42 42 |
| 1518 | 134 86 6 156 107 11 167 114 7 175 118 6 | 1517 | 41 42 42 41 42 42 38 39 37 32 34 33 27 29 28 23 24 24 |
| 1519 | 175 118 6 167 114 7 152 99 6 121 87 25 | 1518 | 21 22 21 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12 |
| 1520 | 101 98 89 62 62 62 34 34 34 18 18 18 | 1519 | 12 12 12 12 12 12 8 8 7 0 0 0 0 0 0 0 0 0 |
| 1521 | 6 6 6 0 0 0 0 0 0 0 0 0 | 1520 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1522 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1521 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1523 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1522 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1524 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1523 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1525 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1524 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1526 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1525 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1527 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1526 | 0 0 0 0 0 0 0 0 0 0 0 0 11 11 11 137 133 100 |
| 1528 | 0 0 0 6 6 6 6 6 6 10 10 10 | 1527 | 197 193 154 251 251 187 239 239 170 184 179 149 31 33 31 0 0 0 |
| 1529 | 18 18 18 22 22 22 30 30 30 42 42 42 | 1528 | 0 0 0 |
| 1530 | 50 50 50 66 66 66 86 86 86 101 98 89 | 1529 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1531 | 106 86 58 98 70 6 104 69 6 104 69 6 | 1530 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1532 | 104 69 6 91 60 6 82 62 34 90 90 90 | 1531 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1533 | 62 62 62 38 38 38 22 22 22 14 14 14 | 1532 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1534 | 10 10 10 10 10 10 10 10 10 10 10 10 | 1533 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 12 12 |
| 1535 | 10 10 10 10 10 10 6 6 6 10 10 10 | 1534 | 110 109 94 110 109 94 105 104 92 90 89 73 72 73 67 58 59 55 |
| 1536 | 10 10 10 10 10 10 10 10 10 14 14 14 | 1535 | 46 47 45 37 39 37 31 33 31 26 28 27 20 24 24 17 21 21 |
| 1537 | 22 22 22 42 42 42 70 70 70 89 81 66 | 1536 | 15 18 18 13 16 16 12 15 15 12 14 14 11 13 13 11 13 13 |
| 1538 | 80 54 7 104 69 6 124 80 6 137 92 6 | 1537 | 10 13 13 10 13 13 10 13 13 10 13 13 10 13 13 10 13 13 |
| 1539 | 134 86 6 116 81 8 100 82 52 86 86 86 | 1538 | 10 13 13 10 13 13 11 13 13 11 13 13 11 14 14 11 14 14 |
| 1540 | 58 58 58 30 30 30 14 14 14 6 6 6 | 1539 | 11 14 14 11 14 14 12 14 14 12 15 15 12 15 15 12 15 15 |
| 1541 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1540 | 13 16 16 13 16 16 13 16 16 13 16 16 13 17 17 13 17 17 |
| 1542 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1541 | 14 17 17 14 17 17 14 18 18 23 27 26 41 42 42 41 42 42 |
| 1543 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1542 | 43 45 43 41 42 42 39 40 39 33 36 34 27 29 28 23 24 24 |
| 1544 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1543 | 21 22 21 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12 |
| 1545 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1544 | 12 12 12 12 12 12 6 7 7 0 0 0 0 0 0 0 0 0 |
| 1546 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1545 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1547 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1546 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1548 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1547 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1549 | 0 0 0 6 6 6 10 10 10 14 14 14 | 1548 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1550 | 18 18 18 26 26 26 38 38 38 54 54 54 | 1549 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1551 | 70 70 70 86 86 86 94 86 76 89 81 66 | 1550 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1552 | 89 81 66 86 86 86 74 74 74 50 50 50 | 1551 | 0 0 0 0 0 0 0 0 0 27 29 28 168 163 120 210 208 158 |
| 1553 | 30 30 30 14 14 14 6 6 6 0 0 0 | 1552 | 251 251 187 251 251 187 210 208 158 137 133 100 1 1 1 0 0 0 |
| 1554 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1553 | 0 0 0 |
| 1555 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1554 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1556 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1555 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1557 | 6 6 6 18 18 18 34 34 34 58 58 58 | 1556 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1558 | 82 82 82 89 81 66 89 81 66 89 81 66 | 1557 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1559 | 94 86 66 94 86 76 74 74 74 50 50 50 | 1558 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 60 60 56 |
| 1560 | 26 26 26 14 14 14 6 6 6 0 0 0 | 1559 | 110 109 94 105 104 92 105 104 92 84 83 72 65 66 61 51 52 50 |
| 1561 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1560 | 40 43 41 33 36 34 27 30 29 23 25 24 18 22 22 16 19 19 |
| 1562 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1561 | 14 17 17 12 15 15 11 14 14 11 14 14 10 13 13 10 13 13 |
| 1563 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1562 | 10 13 13 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 |
| 1564 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1563 | 10 12 12 10 12 12 10 13 13 10 13 13 10 13 13 11 13 13 |
| 1565 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1564 | 11 13 13 11 14 14 11 14 14 11 14 14 11 14 14 12 15 15 |
| 1566 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1565 | 12 15 15 12 15 15 12 15 15 13 16 16 13 16 16 13 16 16 |
| 1567 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1566 | 13 17 17 13 17 17 14 17 17 32 34 33 43 45 43 43 45 43 |
| 1568 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1567 | 43 45 43 43 45 43 39 40 39 33 36 34 27 29 28 23 24 24 |
| 1569 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1568 | 21 22 21 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12 |
| 1570 | 6 6 6 6 6 6 14 14 14 18 18 18 | 1569 | 12 12 12 12 12 12 6 7 7 0 0 0 0 0 0 0 0 0 |
| 1571 | 30 30 30 38 38 38 46 46 46 54 54 54 | 1570 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1572 | 50 50 50 42 42 42 30 30 30 18 18 18 | 1571 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1573 | 10 10 10 0 0 0 0 0 0 0 0 0 | 1572 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1574 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1573 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1575 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1574 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1576 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1575 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1577 | 0 0 0 6 6 6 14 14 14 26 26 26 | 1576 | 0 0 0 1 1 1 68 70 65 184 179 149 210 208 158 251 251 187 |
| 1578 | 38 38 38 50 50 50 58 58 58 58 58 58 | 1577 | 251 251 187 214 212 158 184 179 149 37 39 37 0 0 0 0 0 0 |
| 1579 | 54 54 54 42 42 42 30 30 30 18 18 18 | 1578 | 0 0 0 |
| 1580 | 10 10 10 0 0 0 0 0 0 0 0 0 | 1579 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1581 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1580 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1582 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1581 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1583 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1582 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1584 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1583 | 0 0 0 0 0 0 0 0 0 0 0 0 6 7 7 105 104 92 |
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| 1587 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1586 | 12 15 15 12 14 14 11 13 13 10 13 13 10 12 12 10 12 12 |
| 1588 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1587 | 10 12 12 10 12 12 9 12 12 9 12 12 9 12 12 9 12 12 |
| 1589 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1588 | 10 12 12 10 12 12 10 12 12 10 12 12 10 12 12 10 13 13 |
| 1590 | 0 0 0 0 0 0 0 0 0 6 6 6 | 1589 | 10 13 13 10 13 13 11 13 13 11 13 13 11 14 14 11 14 14 |
| 1591 | 6 6 6 10 10 10 14 14 14 18 18 18 | 1590 | 11 14 14 12 15 15 12 15 15 12 15 15 12 15 15 13 16 16 |
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| 1593 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1592 | 46 47 45 43 45 43 40 41 39 33 36 34 27 29 28 23 24 24 |
| 1594 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1593 | 20 20 20 17 17 17 15 15 15 13 13 13 12 12 12 12 12 12 |
| 1595 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1594 | 12 12 12 12 12 12 4 5 5 0 0 0 0 0 0 0 0 0 |
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| 1597 | 0 0 0 0 0 0 0 0 0 6 6 6 | 1596 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
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| 1688 | 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 | ||
| 1689 | 9 11 11 9 11 11 9 11 11 9 12 12 9 12 12 9 12 12 | ||
| 1690 | 10 12 12 10 12 12 10 12 12 10 13 13 10 13 13 11 13 13 | ||
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| 1717 | 49 51 48 43 45 43 38 39 37 31 33 31 25 27 26 22 24 23 | ||
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| 1738 | 8 10 10 8 10 10 8 10 10 8 10 10 9 11 11 9 11 11 | ||
| 1739 | 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 | ||
| 1740 | 9 11 11 9 11 11 9 12 12 9 12 12 10 12 12 17 20 20 | ||
| 1741 | 46 47 45 72 73 67 210 208 158 251 251 187 210 208 158 63 64 60 | ||
| 1742 | 49 51 48 43 45 43 37 39 37 30 32 31 24 26 24 105 104 92 | ||
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| 1761 | 9 11 11 9 11 11 9 11 11 8 10 10 8 10 10 8 10 10 | ||
| 1762 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1763 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1764 | 8 10 10 9 11 11 9 11 11 9 11 11 9 11 11 9 11 11 | ||
| 1765 | 9 11 11 9 11 11 9 11 11 9 12 12 13 16 16 41 42 42 | ||
| 1766 | 49 51 48 110 109 94 251 251 187 251 251 187 251 251 187 105 104 92 | ||
| 1767 | 49 51 48 43 45 43 35 37 36 30 31 28 47 48 46 197 193 154 | ||
| 1768 | 251 251 187 197 193 154 31 33 31 12 12 12 12 12 12 12 12 12 | ||
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| 1775 | 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 214 212 158 | ||
| 1776 | 184 179 149 110 109 94 13 13 13 0 0 0 0 0 0 0 0 0 | ||
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| 1783 | 0 0 0 26 28 27 99 98 80 84 83 72 60 60 56 43 45 43 | ||
| 1784 | 72 73 67 65 66 61 49 51 48 35 37 36 27 29 28 20 24 24 | ||
| 1785 | 17 20 20 14 17 17 12 15 15 11 13 13 10 12 12 9 11 11 | ||
| 1786 | 9 11 11 9 11 11 8 10 10 8 10 10 8 10 10 8 10 10 | ||
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| 1788 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1789 | 8 10 10 8 10 10 8 10 10 8 10 10 9 11 11 9 11 11 | ||
| 1790 | 9 11 11 9 11 11 9 11 11 11 13 13 37 39 37 47 48 46 | ||
| 1791 | 51 52 50 184 179 149 251 251 187 251 251 187 251 251 187 145 141 105 | ||
| 1792 | 47 48 46 41 42 42 35 37 36 27 29 28 137 133 100 251 251 187 | ||
| 1793 | 251 251 187 197 193 154 19 20 19 12 12 12 12 12 12 12 12 12 | ||
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| 1806 | 30 32 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 1808 | 0 0 0 60 60 56 84 83 72 68 70 65 51 52 50 38 39 37 | ||
| 1809 | 84 83 72 63 64 60 43 45 43 33 36 34 25 27 26 20 23 22 | ||
| 1810 | 15 18 18 13 16 16 12 14 14 10 13 13 9 12 12 9 11 11 | ||
| 1811 | 9 11 11 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1812 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1813 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1814 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1815 | 9 11 11 9 11 11 10 12 12 33 36 34 46 47 45 51 52 50 | ||
| 1816 | 72 73 67 210 208 158 251 251 187 251 251 187 251 251 187 177 172 135 | ||
| 1817 | 47 48 46 41 42 42 35 37 36 37 39 37 184 179 149 251 251 187 | ||
| 1818 | 251 251 187 197 193 154 13 13 13 12 12 12 12 12 12 12 12 12 | ||
| 1819 | 110 109 94 251 251 187 251 251 187 37 39 37 0 0 0 0 0 0 | ||
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| 1824 | 46 47 45 55 56 53 60 60 56 65 66 61 68 70 65 105 104 92 | ||
| 1825 | 110 109 94 197 193 154 210 208 158 197 193 154 184 179 149 84 83 72 | ||
| 1826 | 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 1828 | 0 0 0 | ||
| 1829 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1830 | 0 0 0 0 0 0 0 0 0 13 13 13 184 179 149 251 251 187 | ||
| 1831 | 197 193 154 43 44 41 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1832 | 145 141 105 251 251 187 251 251 187 251 251 187 214 212 158 43 45 43 | ||
| 1833 | 2 2 2 84 83 72 72 73 67 58 59 55 41 42 42 38 39 37 | ||
| 1834 | 72 73 67 58 59 55 41 42 42 31 33 31 25 27 26 18 22 22 | ||
| 1835 | 14 17 17 12 15 15 12 14 14 10 12 12 9 12 12 9 11 11 | ||
| 1836 | 9 11 11 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1837 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1838 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1839 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1840 | 8 10 10 9 12 12 31 33 31 43 45 43 49 51 48 55 56 53 | ||
| 1841 | 110 109 94 251 251 187 251 251 187 251 251 187 251 251 187 168 163 120 | ||
| 1842 | 47 48 46 41 42 42 33 36 34 63 64 60 197 193 154 251 251 187 | ||
| 1843 | 251 251 187 184 179 149 13 13 13 12 12 12 12 12 12 16 16 16 | ||
| 1844 | 197 193 154 251 251 187 239 239 170 20 20 20 0 0 0 2 2 1 | ||
| 1845 | 108 107 93 110 109 94 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1846 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1847 | 0 0 0 0 0 0 1 1 1 4 5 5 11 11 11 18 19 18 | ||
| 1848 | 22 24 23 26 28 27 32 34 33 39 40 39 46 47 45 51 52 50 | ||
| 1849 | 55 57 54 60 60 56 63 64 60 63 64 60 63 64 60 58 59 55 | ||
| 1850 | 63 64 60 99 98 80 145 141 105 137 133 100 43 45 43 0 0 0 | ||
| 1851 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1852 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1853 | 0 0 0 | ||
| 1854 | 0 0 0 0 0 0 0 0 0 3 4 3 0 0 0 0 0 0 | ||
| 1855 | 0 0 0 0 0 0 0 0 0 0 0 0 110 109 94 251 251 187 | ||
| 1856 | 251 251 187 184 179 149 25 27 26 0 0 0 0 0 0 0 0 0 | ||
| 1857 | 99 98 80 251 251 187 251 251 187 251 251 187 251 251 187 156 151 111 | ||
| 1858 | 25 27 26 84 83 72 65 66 61 47 48 46 32 34 33 39 40 39 | ||
| 1859 | 72 73 67 55 57 54 40 41 39 30 32 31 23 25 24 18 22 22 | ||
| 1860 | 14 17 17 12 15 15 11 13 13 10 12 12 9 11 11 9 11 11 | ||
| 1861 | 9 11 11 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1862 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1863 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1864 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1865 | 9 11 11 28 31 30 41 42 42 47 48 46 55 56 53 58 59 55 | ||
| 1866 | 137 133 100 251 251 187 251 251 187 251 251 187 210 208 158 137 133 100 | ||
| 1867 | 47 48 46 40 41 39 32 34 33 75 75 61 184 179 149 239 239 170 | ||
| 1868 | 251 251 187 177 172 135 13 13 13 12 12 12 12 12 12 43 44 41 | ||
| 1869 | 197 193 154 251 251 187 210 208 158 10 10 9 0 0 0 84 83 72 | ||
| 1870 | 251 251 187 84 83 72 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1871 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 | ||
| 1872 | 6 7 7 11 11 11 17 17 17 20 20 20 23 24 24 27 29 28 | ||
| 1873 | 32 34 33 38 39 37 43 45 43 47 48 46 51 52 50 55 56 53 | ||
| 1874 | 58 59 55 58 59 55 55 57 54 55 56 53 47 48 46 41 42 42 | ||
| 1875 | 35 37 36 31 33 31 47 48 46 14 14 13 0 0 0 0 0 0 | ||
| 1876 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1877 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1878 | 0 0 0 | ||
| 1879 | 0 0 0 0 0 0 0 0 0 66 65 55 99 98 80 20 20 20 | ||
| 1880 | 0 0 0 0 0 0 0 0 0 0 0 0 43 45 43 214 212 158 | ||
| 1881 | 251 251 187 251 251 187 145 141 105 3 3 3 0 0 0 0 0 0 | ||
| 1882 | 48 49 45 184 179 149 239 239 170 251 251 187 239 239 170 177 172 135 | ||
| 1883 | 84 83 72 72 73 67 55 56 53 39 40 39 26 28 27 39 40 39 | ||
| 1884 | 68 70 65 51 52 50 39 40 39 28 31 30 22 24 23 17 20 20 | ||
| 1885 | 14 17 17 12 14 14 10 13 13 9 11 11 9 11 11 9 11 11 | ||
| 1886 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1887 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1888 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1889 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1890 | 27 29 28 40 41 39 46 47 45 51 52 50 55 57 54 63 64 60 | ||
| 1891 | 131 127 93 197 193 154 210 208 158 197 193 154 168 163 120 96 95 69 | ||
| 1892 | 47 48 46 40 41 39 32 34 33 71 71 57 145 141 105 184 179 149 | ||
| 1893 | 184 179 149 131 127 93 13 13 13 12 12 12 12 12 12 48 49 45 | ||
| 1894 | 168 163 120 184 179 149 156 151 111 6 7 7 14 14 13 177 172 135 | ||
| 1895 | 239 239 170 40 41 39 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1896 | 0 0 0 0 0 0 3 3 3 6 7 7 11 11 11 16 16 16 | ||
| 1897 | 18 19 18 21 22 21 23 24 24 27 29 28 32 34 33 37 39 37 | ||
| 1898 | 41 42 42 43 45 43 47 48 46 51 52 50 51 52 50 51 52 50 | ||
| 1899 | 51 52 50 49 51 48 46 47 45 40 41 39 32 34 33 25 27 26 | ||
| 1900 | 20 20 20 14 14 13 2 2 2 0 0 0 0 0 0 0 0 0 | ||
| 1901 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1902 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1903 | 0 0 0 | ||
| 1904 | 0 0 0 0 0 0 0 0 0 33 36 34 197 193 154 184 179 149 | ||
| 1905 | 41 42 42 0 0 0 0 0 0 0 0 0 3 3 3 184 179 149 | ||
| 1906 | 251 251 187 251 251 187 184 179 149 48 49 45 0 0 0 0 0 0 | ||
| 1907 | 16 17 12 121 119 87 177 172 135 194 189 146 188 184 146 145 141 105 | ||
| 1908 | 82 81 62 63 64 60 46 47 45 31 33 31 21 22 21 35 37 36 | ||
| 1909 | 68 70 65 51 52 50 37 39 37 27 30 29 22 24 23 17 20 20 | ||
| 1910 | 13 16 16 12 14 14 10 13 13 9 11 11 8 10 10 8 10 10 | ||
| 1911 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1912 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1913 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1914 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 25 27 26 | ||
| 1915 | 38 39 37 43 45 43 51 52 50 55 56 53 60 60 56 63 64 60 | ||
| 1916 | 92 91 72 158 153 112 176 171 126 171 165 117 149 143 98 82 81 62 | ||
| 1917 | 44 46 43 38 39 37 30 32 31 71 71 57 131 127 93 160 154 106 | ||
| 1918 | 149 143 98 82 81 62 13 13 13 12 12 12 12 12 12 46 47 43 | ||
| 1919 | 121 119 87 134 131 96 96 95 69 7 7 6 38 39 37 131 127 93 | ||
| 1920 | 145 141 105 12 13 12 0 0 0 1 1 1 3 3 3 6 7 7 | ||
| 1921 | 10 10 9 12 12 12 14 14 13 16 16 16 18 19 18 21 22 21 | ||
| 1922 | 22 24 23 26 28 27 30 31 28 33 36 34 37 39 37 40 41 39 | ||
| 1923 | 41 42 42 43 45 43 46 47 45 46 47 45 46 47 45 43 45 43 | ||
| 1924 | 41 42 42 37 39 37 31 33 31 26 28 27 21 22 21 16 16 16 | ||
| 1925 | 6 7 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1926 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1927 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1928 | 0 0 0 | ||
| 1929 | 0 0 0 0 0 0 0 0 0 0 0 0 177 172 135 251 251 187 | ||
| 1930 | 197 193 154 27 29 28 0 0 0 0 0 0 0 0 0 110 109 94 | ||
| 1931 | 239 239 170 239 239 170 184 179 149 87 86 72 2 2 1 0 0 0 | ||
| 1932 | 1 1 1 82 81 62 142 137 94 165 161 109 165 161 109 131 127 93 | ||
| 1933 | 75 75 61 55 56 53 37 39 37 25 27 26 19 20 19 32 34 33 | ||
| 1934 | 65 66 61 49 51 48 35 37 36 27 29 28 20 23 23 16 19 19 | ||
| 1935 | 13 16 16 13 13 13 10 12 12 9 11 11 8 10 10 8 10 10 | ||
| 1936 | 8 9 9 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1937 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1938 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1939 | 8 10 10 8 10 10 8 10 10 8 10 10 22 24 23 35 37 36 | ||
| 1940 | 41 42 42 47 48 46 55 56 53 58 59 55 63 64 60 65 66 61 | ||
| 1941 | 71 71 57 131 127 93 160 154 106 160 154 106 142 137 94 82 81 62 | ||
| 1942 | 46 47 43 40 41 39 33 36 34 66 65 55 125 122 87 149 143 98 | ||
| 1943 | 142 137 94 82 81 62 17 17 17 18 19 17 14 14 13 46 47 43 | ||
| 1944 | 118 116 76 125 122 87 96 95 69 16 17 12 71 71 57 103 101 77 | ||
| 1945 | 82 81 62 11 11 11 11 11 11 13 13 13 14 14 13 14 14 13 | ||
| 1946 | 15 15 15 16 16 16 17 17 17 19 20 19 21 22 21 23 24 24 | ||
| 1947 | 26 28 27 27 29 28 31 33 31 33 36 34 35 37 36 38 39 37 | ||
| 1948 | 39 40 39 39 40 39 38 39 37 37 39 37 35 37 36 31 33 31 | ||
| 1949 | 27 29 28 24 26 24 21 22 21 17 17 17 12 12 12 2 2 2 | ||
| 1950 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1951 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1952 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1953 | 0 0 0 | ||
| 1954 | 0 0 0 0 0 0 0 0 0 0 0 0 68 70 65 251 251 187 | ||
| 1955 | 251 251 187 156 151 111 2 2 1 0 0 0 0 0 0 43 44 41 | ||
| 1956 | 177 172 135 184 179 149 158 153 112 103 101 77 19 20 18 0 0 0 | ||
| 1957 | 0 0 0 46 47 43 131 127 93 160 154 106 160 154 106 131 127 93 | ||
| 1958 | 71 71 57 43 45 43 30 32 31 21 22 21 16 16 16 26 28 27 | ||
| 1959 | 63 64 60 47 48 46 35 37 36 26 28 27 20 23 23 16 19 19 | ||
| 1960 | 13 16 16 13 13 13 10 12 12 9 11 11 8 10 10 8 10 10 | ||
| 1961 | 7 9 9 7 9 9 8 9 9 8 10 10 8 10 10 8 10 10 | ||
| 1962 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1963 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1964 | 8 10 10 8 10 10 8 10 10 20 20 20 33 36 34 40 41 39 | ||
| 1965 | 46 47 45 51 52 50 55 57 54 60 60 56 63 64 60 65 66 61 | ||
| 1966 | 66 65 55 118 116 76 151 147 98 165 161 109 151 147 98 121 119 87 | ||
| 1967 | 96 95 69 96 95 69 96 95 69 103 101 77 142 137 94 151 147 98 | ||
| 1968 | 142 137 94 103 101 77 82 81 62 82 81 62 82 81 62 96 95 69 | ||
| 1969 | 131 127 93 142 137 94 103 101 77 46 47 43 96 95 69 118 116 76 | ||
| 1970 | 71 71 57 14 14 13 14 14 13 15 15 15 15 15 15 16 16 16 | ||
| 1971 | 16 16 16 17 17 17 18 19 18 20 20 20 21 22 21 23 24 24 | ||
| 1972 | 25 27 26 27 29 28 30 31 28 30 32 31 31 33 31 31 33 31 | ||
| 1973 | 31 33 31 31 33 31 30 31 28 27 29 28 25 27 26 22 24 23 | ||
| 1974 | 20 20 20 16 16 16 13 13 13 6 7 7 0 0 0 0 0 0 | ||
| 1975 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1976 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1977 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1978 | 0 0 0 | ||
| 1979 | 58 59 55 68 70 65 8 8 7 0 0 0 10 10 9 210 208 158 | ||
| 1980 | 251 251 187 184 179 149 38 39 37 0 0 0 0 0 0 8 8 7 | ||
| 1981 | 103 101 77 149 143 98 149 143 98 118 116 76 40 41 39 25 27 25 | ||
| 1982 | 53 55 47 82 81 62 144 139 99 165 161 109 165 161 109 142 137 94 | ||
| 1983 | 71 71 57 35 37 36 24 26 24 18 19 18 15 15 15 22 24 23 | ||
| 1984 | 63 64 60 46 47 45 33 36 34 26 28 27 20 23 22 17 18 17 | ||
| 1985 | 12 15 15 11 13 13 10 12 12 9 11 11 8 10 10 8 10 10 | ||
| 1986 | 7 9 9 7 9 9 7 9 9 7 9 9 8 9 9 8 10 10 | ||
| 1987 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1988 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 1989 | 8 10 10 8 10 10 16 16 16 30 31 28 35 37 36 41 42 42 | ||
| 1990 | 47 48 46 55 56 53 58 59 55 63 64 60 65 66 61 65 66 61 | ||
| 1991 | 61 61 53 103 101 77 151 147 98 171 165 117 171 165 117 168 163 120 | ||
| 1992 | 158 153 112 158 153 112 155 149 109 151 147 98 151 147 98 160 154 106 | ||
| 1993 | 151 147 98 149 143 98 142 137 94 149 143 98 149 143 98 149 143 98 | ||
| 1994 | 155 149 109 151 147 98 131 127 93 103 101 77 125 122 87 118 116 76 | ||
| 1995 | 71 71 57 16 16 16 16 16 16 16 16 16 17 17 17 17 17 17 | ||
| 1996 | 17 17 17 17 17 17 18 19 18 19 20 19 20 20 20 21 22 21 | ||
| 1997 | 23 24 24 24 26 24 25 27 26 26 28 27 26 28 27 26 28 27 | ||
| 1998 | 25 27 26 24 26 24 22 24 23 21 22 21 19 20 19 16 16 16 | ||
| 1999 | 14 14 13 8 8 7 1 1 1 0 0 0 0 0 0 0 0 0 | ||
| 2000 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2001 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2002 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2003 | 0 0 0 | ||
| 2004 | 20 20 20 184 179 149 168 163 120 21 22 21 0 0 0 105 104 92 | ||
| 2005 | 177 172 135 145 141 105 71 71 57 0 0 0 0 0 0 0 0 0 | ||
| 2006 | 66 65 55 131 127 93 151 147 98 142 137 94 118 116 76 121 119 87 | ||
| 2007 | 145 141 105 158 153 112 176 171 126 178 174 128 176 171 126 149 145 103 | ||
| 2008 | 96 95 69 31 33 31 21 22 21 16 16 16 14 14 13 18 19 18 | ||
| 2009 | 60 60 56 46 47 45 33 36 34 25 27 26 21 22 21 15 18 18 | ||
| 2010 | 12 15 15 11 13 13 9 11 11 8 10 10 8 10 10 8 9 9 | ||
| 2011 | 7 9 9 7 9 9 7 9 9 7 9 9 7 9 9 8 9 9 | ||
| 2012 | 8 9 9 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 2013 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 2014 | 8 10 10 10 12 12 26 28 27 31 33 31 38 39 37 43 45 43 | ||
| 2015 | 51 52 50 55 56 53 60 60 56 63 64 60 65 66 61 68 70 65 | ||
| 2016 | 63 64 60 96 95 69 158 153 112 178 174 128 188 184 146 194 189 146 | ||
| 2017 | 194 189 146 188 184 146 184 181 136 176 171 126 171 165 117 173 167 111 | ||
| 2018 | 173 167 111 165 161 109 171 165 117 174 170 121 176 171 126 178 174 128 | ||
| 2019 | 178 174 128 174 170 121 160 154 106 149 143 98 149 143 98 125 122 87 | ||
| 2020 | 71 71 57 16 16 16 16 16 16 17 17 17 17 17 17 17 17 17 | ||
| 2021 | 17 17 17 17 17 17 17 17 17 18 19 18 19 20 19 20 20 20 | ||
| 2022 | 21 22 21 21 22 21 21 22 21 22 24 23 21 22 21 21 22 21 | ||
| 2023 | 21 22 21 19 20 19 18 19 18 16 16 16 14 14 13 11 11 11 | ||
| 2024 | 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2025 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2026 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2027 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2028 | 0 0 0 | ||
| 2029 | 0 0 0 105 104 92 197 193 154 110 109 94 9 9 8 36 38 35 | ||
| 2030 | 121 119 87 131 127 93 96 95 69 18 19 17 30 31 28 66 65 55 | ||
| 2031 | 96 95 69 142 137 94 160 154 106 160 154 106 160 154 106 168 163 120 | ||
| 2032 | 184 181 136 194 191 148 197 193 154 197 193 154 194 189 146 168 163 120 | ||
| 2033 | 125 122 87 46 47 43 18 19 18 15 15 15 13 13 13 14 14 13 | ||
| 2034 | 55 57 54 43 45 43 32 34 33 25 27 26 18 22 22 17 17 17 | ||
| 2035 | 12 14 14 10 12 12 9 11 11 8 10 10 8 9 9 7 9 9 | ||
| 2036 | 6 8 8 7 9 9 7 9 9 7 9 9 7 9 9 7 9 9 | ||
| 2037 | 7 9 9 8 9 9 8 9 9 8 10 10 8 10 10 8 10 10 | ||
| 2038 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 2039 | 8 10 10 32 34 33 41 42 42 35 37 36 39 40 39 37 39 37 | ||
| 2040 | 35 37 36 55 57 54 60 60 56 63 64 60 65 66 61 65 66 61 | ||
| 2041 | 61 63 57 115 113 82 168 163 120 194 191 148 204 201 155 210 208 158 | ||
| 2042 | 210 208 158 210 208 158 197 193 154 194 189 146 186 182 128 176 171 126 | ||
| 2043 | 174 170 121 176 171 126 186 182 128 190 186 136 194 191 148 197 193 154 | ||
| 2044 | 197 193 154 188 184 146 181 176 137 174 170 121 165 161 109 142 137 94 | ||
| 2045 | 82 81 62 24 26 24 16 16 16 16 16 16 16 16 16 16 16 16 | ||
| 2046 | 17 17 17 17 17 17 17 17 17 17 17 17 18 19 18 19 20 19 | ||
| 2047 | 19 20 19 19 20 19 20 20 20 19 20 19 19 20 19 18 19 18 | ||
| 2048 | 17 17 17 15 15 15 13 13 13 12 12 12 6 7 7 0 0 0 | ||
| 2049 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 2053 | 0 0 0 | ||
| 2054 | 0 0 0 17 18 17 137 133 100 115 113 82 53 55 47 19 20 18 | ||
| 2055 | 103 101 77 144 139 99 137 133 100 115 113 82 137 133 100 156 151 111 | ||
| 2056 | 158 153 112 164 159 111 171 165 117 174 170 121 178 174 128 194 189 146 | ||
| 2057 | 204 201 155 214 212 158 214 212 158 214 212 158 210 208 158 188 184 146 | ||
| 2058 | 158 153 112 87 86 72 17 17 17 13 13 13 13 13 13 15 15 15 | ||
| 2059 | 55 56 53 43 45 43 32 34 33 24 26 24 17 20 20 16 16 16 | ||
| 2060 | 12 14 14 10 12 12 8 10 10 8 10 10 7 9 9 6 8 8 | ||
| 2061 | 6 8 8 6 8 8 6 8 8 7 9 9 7 9 9 7 9 9 | ||
| 2062 | 7 9 9 7 9 9 7 9 9 7 9 9 8 9 9 8 10 10 | ||
| 2063 | 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 8 10 10 | ||
| 2064 | 8 10 10 110 109 94 84 83 72 49 51 48 26 28 27 8 10 10 | ||
| 2065 | 8 9 9 51 52 50 58 59 55 63 64 60 63 64 60 63 64 60 | ||
| 2066 | 66 65 55 134 131 96 181 176 137 210 208 158 214 212 158 239 239 170 | ||
| 2067 | 239 239 170 224 223 159 210 208 158 204 201 155 194 189 146 186 182 128 | ||
| 2068 | 186 182 128 184 181 136 194 189 146 204 201 155 210 208 158 210 208 158 | ||
| 2069 | 210 208 158 210 208 158 197 193 154 190 186 136 176 171 126 155 149 109 | ||
| 2070 | 118 116 76 36 38 35 15 15 15 16 16 16 16 16 16 16 16 16 | ||
| 2071 | 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 17 17 17 | ||
| 2072 | 17 17 17 17 17 17 17 17 17 16 16 16 16 16 16 15 15 15 | ||
| 2073 | 13 13 13 12 12 12 8 8 7 2 2 2 0 0 0 0 0 0 | ||
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| 2080 | 103 101 77 158 153 112 177 172 135 184 179 149 188 184 146 197 193 154 | ||
| 2081 | 194 189 146 190 186 136 184 181 136 184 181 136 194 189 146 210 208 158 | ||
| 2082 | 214 212 158 239 239 170 251 251 187 251 251 187 224 223 159 204 201 155 | ||
| 2083 | 177 172 135 121 119 87 30 31 28 13 13 13 12 12 12 39 40 39 | ||
| 2084 | 60 60 56 43 45 43 32 34 33 23 25 24 18 19 18 13 16 16 | ||
| 2085 | 13 13 13 9 11 11 8 10 10 8 9 9 6 8 8 6 8 8 | ||
| 2086 | 6 8 8 6 8 8 6 8 8 6 8 8 6 8 8 7 9 9 | ||
| 2087 | 7 9 9 7 9 9 7 9 9 7 9 9 7 9 9 7 9 9 | ||
| 2088 | 7 9 9 8 9 9 8 9 9 8 10 10 8 10 10 8 10 10 | ||
| 2089 | 14 17 17 197 193 154 158 153 112 55 57 54 7 9 9 7 9 9 | ||
| 2090 | 8 10 10 51 52 50 58 59 55 60 60 56 63 64 60 63 64 60 | ||
| 2091 | 71 71 57 155 149 109 194 191 148 214 212 158 251 251 187 251 251 187 | ||
| 2092 | 251 251 187 251 251 187 239 239 170 210 208 158 197 193 154 190 186 136 | ||
| 2093 | 190 186 136 194 189 146 204 201 155 210 208 158 224 223 159 239 239 170 | ||
| 2094 | 239 239 170 224 223 159 210 208 158 204 201 155 190 186 136 164 159 111 | ||
| 2095 | 125 122 87 40 41 39 15 15 15 15 15 15 15 15 15 15 15 15 | ||
| 2096 | 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 | ||
| 2097 | 16 16 16 16 16 16 15 15 15 14 14 13 13 13 13 12 12 12 | ||
| 2098 | 8 9 9 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 2105 | 144 139 99 177 172 135 197 193 154 210 208 158 214 212 158 214 212 158 | ||
| 2106 | 210 208 158 204 201 155 194 191 148 194 189 146 204 201 155 214 212 158 | ||
| 2107 | 239 239 170 251 251 187 251 251 187 251 251 187 251 251 187 214 212 158 | ||
| 2108 | 188 184 146 145 141 105 53 55 47 12 12 12 15 15 15 63 64 60 | ||
| 2109 | 63 64 60 41 42 42 31 33 31 23 24 24 17 18 17 12 15 15 | ||
| 2110 | 11 13 13 9 11 11 8 9 9 7 9 9 6 8 8 6 8 8 | ||
| 2111 | 6 7 7 6 7 7 6 8 8 6 8 8 6 8 8 6 8 8 | ||
| 2112 | 6 8 8 7 9 9 7 9 9 7 9 9 7 9 9 7 9 9 | ||
| 2113 | 7 9 9 7 9 9 7 9 9 7 9 9 7 9 9 8 8 7 | ||
| 2114 | 43 45 43 251 251 187 156 151 111 8 10 10 7 9 9 7 9 9 | ||
| 2115 | 21 22 21 51 52 50 55 56 53 55 57 54 58 59 55 58 59 55 | ||
| 2116 | 75 75 61 158 153 112 197 193 154 224 223 159 251 251 187 251 251 187 | ||
| 2117 | 251 251 187 251 251 187 251 251 187 214 212 158 204 201 155 194 189 146 | ||
| 2118 | 190 186 136 197 193 154 210 208 158 224 223 159 251 251 187 251 251 187 | ||
| 2119 | 251 251 187 251 251 187 239 239 170 210 208 158 197 193 154 176 171 126 | ||
| 2120 | 125 122 87 36 38 35 14 14 13 14 14 13 15 15 15 15 15 15 | ||
| 2121 | 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 15 | ||
| 2122 | 15 15 15 14 14 13 13 13 13 12 12 12 10 10 9 3 4 4 | ||
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| 2131 | 238 237 168 210 208 158 204 201 155 197 193 154 204 201 155 214 212 158 | ||
| 2132 | 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 214 212 158 | ||
| 2133 | 197 193 154 156 151 111 66 65 55 12 12 12 37 39 37 58 59 55 | ||
| 2134 | 58 59 55 41 42 42 31 33 31 22 24 23 17 17 17 12 14 14 | ||
| 2135 | 10 12 12 8 10 10 6 8 8 6 8 8 6 7 7 6 7 7 | ||
| 2136 | 6 7 7 5 7 7 6 7 7 6 7 7 6 8 8 6 8 8 | ||
| 2137 | 6 8 8 6 8 8 6 8 8 7 9 9 7 9 9 7 9 9 | ||
| 2138 | 7 9 9 6 8 8 6 8 8 6 8 8 6 8 8 6 8 8 | ||
| 2139 | 61 63 57 197 193 154 16 19 19 6 8 8 6 8 8 8 9 9 | ||
| 2140 | 41 42 42 47 48 46 51 52 50 51 52 50 55 56 53 55 56 53 | ||
| 2141 | 71 71 57 158 153 112 197 193 154 224 223 159 251 251 187 251 251 187 | ||
| 2142 | 251 251 187 251 251 187 239 239 170 214 212 158 204 201 155 194 189 146 | ||
| 2143 | 190 186 136 197 193 154 210 208 158 239 239 170 251 251 187 251 251 187 | ||
| 2144 | 251 251 187 251 251 187 251 251 187 224 223 159 204 201 155 177 172 135 | ||
| 2145 | 121 119 87 30 31 28 13 13 13 14 14 13 14 14 13 14 14 13 | ||
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| 2163 | 6 7 7 6 8 8 6 8 8 6 8 8 6 8 8 6 8 8 | ||
| 2164 | 55 56 53 43 45 43 6 8 8 6 8 8 6 8 8 47 48 46 | ||
| 2165 | 60 60 56 47 48 46 46 47 45 47 48 46 38 39 37 10 12 12 | ||
| 2166 | 66 65 55 145 141 105 197 193 154 214 212 158 251 251 187 251 251 187 | ||
| 2167 | 251 251 187 251 251 187 224 223 159 210 208 158 194 191 148 184 181 136 | ||
| 2168 | 184 181 136 194 189 146 204 201 155 224 223 159 251 251 187 251 251 187 | ||
| 2169 | 251 251 187 251 251 187 251 251 187 239 239 170 210 208 158 181 176 137 | ||
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| 2180 | 204 201 155 214 212 158 251 251 187 251 251 187 251 251 187 251 251 187 | ||
| 2181 | 251 251 187 214 212 158 204 201 155 194 191 148 197 193 154 204 201 155 | ||
| 2182 | 214 212 158 239 239 170 239 239 170 239 239 170 214 212 158 210 208 158 | ||
| 2183 | 184 181 136 149 145 103 66 65 55 41 42 42 47 48 46 46 47 45 | ||
| 2184 | 43 45 43 39 40 39 28 31 30 21 22 21 16 16 16 10 12 12 | ||
| 2185 | 8 10 10 6 8 8 6 7 7 6 7 7 5 6 5 5 6 5 | ||
| 2186 | 5 6 5 5 6 5 5 6 5 5 6 5 5 7 7 5 7 7 | ||
| 2187 | 6 7 7 6 7 7 6 7 7 5 7 7 5 7 7 5 7 7 | ||
| 2188 | 5 7 7 6 7 7 6 7 7 6 7 7 6 7 7 6 8 8 | ||
| 2189 | 6 8 8 6 8 8 6 7 7 6 7 7 46 47 45 156 151 111 | ||
| 2190 | 105 104 92 58 59 55 43 45 43 32 34 33 6 8 8 6 8 8 | ||
| 2191 | 49 51 48 125 122 87 181 176 137 204 201 155 214 212 158 239 239 170 | ||
| 2192 | 239 239 170 214 212 158 210 208 158 197 193 154 181 176 137 176 171 126 | ||
| 2193 | 176 171 126 184 181 136 197 193 154 210 208 158 239 239 170 251 251 187 | ||
| 2194 | 251 251 187 251 251 187 251 251 187 251 251 187 210 208 158 177 172 135 | ||
| 2195 | 99 98 80 13 13 13 12 12 12 12 12 12 13 13 13 12 12 12 | ||
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| 2205 | 204 201 155 224 223 159 251 251 187 251 251 187 251 251 187 251 251 187 | ||
| 2206 | 251 251 187 214 212 158 197 193 154 190 186 136 184 181 136 188 184 146 | ||
| 2207 | 197 193 154 204 201 155 210 208 158 210 208 158 204 201 155 194 189 146 | ||
| 2208 | 176 171 126 134 131 96 66 65 55 43 45 43 41 42 42 39 40 39 | ||
| 2209 | 35 37 36 33 36 34 27 29 28 20 20 20 15 15 15 9 11 11 | ||
| 2210 | 8 9 9 6 7 7 5 6 5 5 6 5 4 5 5 4 5 5 | ||
| 2211 | 4 5 5 4 5 5 4 5 5 4 5 5 5 6 5 4 5 5 | ||
| 2212 | 4 5 5 5 6 5 4 5 5 5 6 5 5 6 5 5 6 5 | ||
| 2213 | 5 7 7 5 7 7 5 7 7 5 7 7 5 7 7 5 7 7 | ||
| 2214 | 6 7 7 6 7 7 6 7 7 28 31 30 184 179 149 184 179 149 | ||
| 2215 | 145 141 105 84 83 72 27 29 28 5 7 7 5 6 5 16 16 16 | ||
| 2216 | 43 44 41 96 95 69 158 153 112 188 184 146 204 201 155 210 208 158 | ||
| 2217 | 204 201 155 197 193 154 184 179 149 177 172 135 168 163 120 164 159 111 | ||
| 2218 | 164 159 111 174 170 121 184 181 136 197 193 154 214 212 158 251 251 187 | ||
| 2219 | 251 251 187 251 251 187 251 251 187 251 251 187 210 208 158 177 172 135 | ||
| 2220 | 71 71 57 11 11 11 12 12 12 11 11 11 11 11 11 11 11 11 | ||
| 2221 | 10 10 9 10 10 9 8 8 7 3 4 4 0 0 0 0 0 0 | ||
| 2222 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2223 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2224 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2225 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2226 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2227 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2228 | 0 0 0 | ||
| 2229 | 0 0 0 0 0 0 0 0 0 31 33 31 121 119 87 176 171 126 | ||
| 2230 | 197 193 154 214 212 158 251 251 187 251 251 187 251 251 187 251 251 187 | ||
| 2231 | 239 239 170 210 208 158 194 189 146 178 174 128 174 170 121 176 171 126 | ||
| 2232 | 177 172 135 181 176 137 184 179 149 184 179 149 181 176 137 178 174 128 | ||
| 2233 | 158 153 112 121 119 87 53 55 47 37 39 37 33 36 34 30 32 31 | ||
| 2234 | 27 29 28 25 27 26 24 26 24 19 20 19 13 13 13 8 10 10 | ||
| 2235 | 6 8 8 6 7 7 5 6 5 4 5 5 4 5 5 4 5 5 | ||
| 2236 | 4 5 5 4 5 5 4 5 5 3 4 4 3 4 4 4 5 5 | ||
| 2237 | 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 | ||
| 2238 | 5 6 5 5 6 5 5 6 5 5 6 5 5 6 5 5 6 5 | ||
| 2239 | 5 6 5 5 6 5 12 14 14 145 141 105 184 179 149 177 172 135 | ||
| 2240 | 90 89 73 21 22 21 5 6 5 5 6 5 4 5 5 37 39 37 | ||
| 2241 | 38 39 37 61 61 53 134 131 96 168 163 120 184 181 136 188 184 146 | ||
| 2242 | 184 179 149 177 172 135 168 163 120 164 159 111 155 149 109 151 147 98 | ||
| 2243 | 151 147 98 164 159 111 176 171 126 184 179 149 210 208 158 239 239 170 | ||
| 2244 | 251 251 187 251 251 187 251 251 187 239 239 170 210 208 158 158 153 112 | ||
| 2245 | 46 47 43 10 10 9 10 10 9 10 10 9 8 9 9 8 9 9 | ||
| 2246 | 6 7 7 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2247 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2248 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2249 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2250 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2251 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2252 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2253 | 0 0 0 | ||
| 2254 | 0 0 0 0 0 0 0 0 0 13 12 7 82 81 62 158 153 112 | ||
| 2255 | 188 184 146 210 208 158 239 239 170 251 251 187 251 251 187 251 251 187 | ||
| 2256 | 224 223 159 204 201 155 184 181 136 171 165 117 164 159 111 160 154 106 | ||
| 2257 | 158 153 112 164 159 111 168 163 120 168 163 120 168 163 120 164 159 111 | ||
| 2258 | 142 137 94 96 95 69 43 44 41 27 29 28 26 28 27 23 24 24 | ||
| 2259 | 21 22 21 18 19 18 17 17 17 18 19 18 13 13 13 8 8 7 | ||
| 2260 | 6 7 7 5 6 5 4 5 5 3 4 4 3 4 4 3 4 4 | ||
| 2261 | 3 4 4 3 4 4 3 3 3 3 3 3 3 4 4 3 4 4 | ||
| 2262 | 3 4 4 3 4 4 4 5 5 4 5 5 4 5 5 4 5 5 | ||
| 2263 | 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 | ||
| 2264 | 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 | ||
| 2265 | 4 5 5 4 5 5 4 5 5 4 5 5 31 33 31 65 66 61 | ||
| 2266 | 37 39 37 38 39 37 96 95 69 144 139 99 168 163 120 174 170 121 | ||
| 2267 | 168 163 120 164 159 111 155 149 109 149 145 103 149 143 98 142 137 94 | ||
| 2268 | 149 143 98 151 147 98 164 159 111 177 172 135 197 193 154 210 208 158 | ||
| 2269 | 251 251 187 251 251 187 251 251 187 239 239 170 197 193 154 137 133 100 | ||
| 2270 | 24 26 24 8 9 9 8 9 9 8 8 7 6 7 7 2 2 2 | ||
| 2271 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2272 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2273 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2274 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2275 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2276 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2277 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2278 | 0 0 0 | ||
| 2279 | 0 0 0 0 0 0 0 0 0 0 0 0 46 47 43 125 122 87 | ||
| 2280 | 176 171 126 197 193 154 210 208 158 239 239 170 251 251 187 239 239 170 | ||
| 2281 | 214 212 158 197 193 154 181 176 137 164 159 111 151 147 98 149 143 98 | ||
| 2282 | 149 143 98 149 143 98 149 145 103 155 149 109 160 154 106 149 143 98 | ||
| 2283 | 118 116 76 82 81 62 30 31 28 21 22 21 19 20 19 17 17 17 | ||
| 2284 | 14 14 13 12 12 12 10 10 9 12 12 12 10 12 12 6 8 8 | ||
| 2285 | 4 5 5 3 4 4 3 4 4 3 4 4 3 3 3 3 3 3 | ||
| 2286 | 3 3 3 3 3 3 3 3 3 3 3 3 2 3 3 2 3 3 | ||
| 2287 | 3 4 4 3 4 4 3 4 4 3 4 4 3 4 4 4 5 5 | ||
| 2288 | 4 5 5 3 4 4 3 4 4 3 4 4 3 4 4 3 4 4 | ||
| 2289 | 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 4 5 5 | ||
| 2290 | 4 5 5 3 4 4 3 4 4 23 24 24 110 109 94 72 73 67 | ||
| 2291 | 39 40 39 22 24 23 46 47 43 103 101 77 142 137 94 155 149 109 | ||
| 2292 | 160 154 106 155 149 109 149 143 98 142 137 94 142 137 94 142 137 94 | ||
| 2293 | 142 137 94 149 143 98 155 149 109 176 171 126 184 179 149 210 208 158 | ||
| 2294 | 239 239 170 251 251 187 251 251 187 214 212 158 184 179 149 105 104 92 | ||
| 2295 | 10 10 9 6 7 7 3 4 4 1 1 1 0 0 0 0 0 0 | ||
| 2296 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2297 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2298 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2299 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2300 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2301 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2302 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2303 | 0 0 0 | ||
| 2304 | 0 0 0 0 0 0 0 0 0 0 0 0 12 12 9 82 81 62 | ||
| 2305 | 149 145 103 181 176 137 197 193 154 210 208 158 214 212 158 214 212 158 | ||
| 2306 | 210 208 158 197 193 154 177 172 135 158 153 112 149 143 98 142 137 94 | ||
| 2307 | 142 137 94 142 137 94 149 143 98 151 147 98 151 147 98 131 127 93 | ||
| 2308 | 103 101 77 71 71 57 22 24 23 15 15 15 13 13 13 11 11 11 | ||
| 2309 | 8 9 9 6 7 7 6 7 7 4 5 5 8 9 9 6 7 7 | ||
| 2310 | 4 5 5 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 | ||
| 2311 | 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 | ||
| 2312 | 2 3 3 2 3 3 2 3 3 3 4 4 3 4 4 3 4 4 | ||
| 2313 | 3 4 4 3 4 4 3 3 3 3 4 4 3 4 4 3 4 4 | ||
| 2314 | 3 4 4 3 4 4 3 4 4 3 4 4 3 4 4 3 4 4 | ||
| 2315 | 3 4 4 3 4 4 21 22 21 145 141 105 145 141 105 72 73 67 | ||
| 2316 | 17 18 17 3 4 4 21 22 20 66 65 55 118 116 76 142 137 94 | ||
| 2317 | 149 143 98 151 147 98 149 143 98 142 137 94 142 137 94 142 137 94 | ||
| 2318 | 142 137 94 149 143 98 155 149 109 168 163 120 184 179 149 210 208 158 | ||
| 2319 | 239 239 170 251 251 187 251 251 187 210 208 158 177 172 135 71 71 57 | ||
| 2320 | 3 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2321 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2322 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2323 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2324 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2325 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2326 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2327 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2328 | 0 0 0 | ||
| 2329 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36 38 35 | ||
| 2330 | 115 113 82 158 153 112 181 176 137 197 193 154 204 201 155 210 208 158 | ||
| 2331 | 204 201 155 188 184 146 177 172 135 164 159 111 149 145 103 142 137 94 | ||
| 2332 | 142 137 94 142 137 94 149 143 98 151 147 98 149 143 98 125 122 87 | ||
| 2333 | 96 95 69 61 61 53 16 17 12 8 9 9 8 8 7 6 7 7 | ||
| 2334 | 4 5 5 3 4 4 3 3 3 3 3 3 3 3 3 5 6 5 | ||
| 2335 | 3 4 4 2 3 3 2 2 2 2 2 2 2 2 2 2 2 2 | ||
| 2336 | 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 | ||
| 2337 | 2 2 2 2 2 2 2 3 3 2 3 3 2 3 3 2 3 3 | ||
| 2338 | 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 | ||
| 2339 | 3 3 3 2 3 3 2 3 3 3 4 4 3 4 4 3 4 4 | ||
| 2340 | 3 4 4 3 4 4 3 4 4 8 9 9 8 8 7 3 3 3 | ||
| 2341 | 3 3 3 3 3 3 9 9 8 36 38 35 82 81 62 118 116 76 | ||
| 2342 | 142 137 94 151 147 98 151 147 98 151 147 98 149 143 98 149 143 98 | ||
| 2343 | 149 143 98 151 147 98 160 154 106 176 171 126 188 184 146 210 208 158 | ||
| 2344 | 239 239 170 251 251 187 239 239 170 210 208 158 156 151 111 31 33 31 | ||
| 2345 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2346 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2347 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2348 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2349 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2350 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2351 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2352 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2353 | 0 0 0 | ||
| 2354 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 7 5 | ||
| 2355 | 66 65 55 125 122 87 158 153 112 181 176 137 194 189 146 197 193 154 | ||
| 2356 | 197 193 154 184 179 149 177 172 135 168 163 120 156 151 111 151 147 98 | ||
| 2357 | 151 147 98 151 147 98 151 147 98 161 156 96 149 143 98 118 116 76 | ||
| 2358 | 82 81 62 53 55 47 12 12 9 4 5 5 3 4 4 3 3 3 | ||
| 2359 | 3 3 3 3 3 3 2 2 2 2 2 2 1 1 1 1 2 2 | ||
| 2360 | 3 3 3 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 | ||
| 2361 | 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 2 | ||
| 2362 | 1 2 2 1 2 2 1 2 2 2 2 2 2 2 2 2 3 3 | ||
| 2363 | 2 3 3 2 3 3 2 3 3 2 3 3 2 2 2 2 2 2 | ||
| 2364 | 2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 | ||
| 2365 | 2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 3 3 3 | ||
| 2366 | 3 3 3 3 3 3 72 73 67 61 61 53 53 55 47 96 95 69 | ||
| 2367 | 131 127 93 151 147 98 161 156 96 161 156 96 151 147 98 151 147 98 | ||
| 2368 | 161 156 96 160 154 106 164 159 111 177 172 135 197 193 154 210 208 158 | ||
| 2369 | 239 239 170 251 251 187 224 223 159 197 193 154 131 127 93 9 9 8 | ||
| 2370 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2371 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2372 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2373 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2374 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2375 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2376 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2377 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2378 | 0 0 0 | ||
| 2379 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2380 | 24 26 24 82 81 62 131 127 93 164 159 111 178 174 128 188 184 146 | ||
| 2381 | 188 184 146 188 184 146 181 176 137 176 171 126 168 163 120 164 159 111 | ||
| 2382 | 160 154 106 160 154 106 160 154 106 160 154 106 151 147 98 125 122 87 | ||
| 2383 | 82 81 62 61 61 53 12 12 9 3 3 3 3 3 3 2 2 2 | ||
| 2384 | 2 2 2 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 | ||
| 2385 | 0 0 0 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2386 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2387 | 1 1 1 1 1 1 1 2 2 1 2 2 1 2 2 1 2 2 | ||
| 2388 | 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 | ||
| 2389 | 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 | ||
| 2390 | 2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 2 3 3 | ||
| 2391 | 2 3 3 30 32 31 72 73 67 31 33 31 36 38 35 82 81 62 | ||
| 2392 | 118 116 76 149 143 98 161 156 96 161 156 96 161 156 96 160 154 106 | ||
| 2393 | 165 161 109 165 161 109 176 171 126 188 184 146 204 201 155 214 212 158 | ||
| 2394 | 239 239 170 239 239 170 214 212 158 184 179 149 82 81 62 0 0 0 | ||
| 2395 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2396 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2397 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2398 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2399 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2400 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2401 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2402 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2403 | 0 0 0 | ||
| 2404 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2405 | 2 2 2 43 44 41 96 95 69 131 127 93 160 154 106 176 171 126 | ||
| 2406 | 184 181 136 184 181 136 184 181 136 181 176 137 178 174 128 174 170 121 | ||
| 2407 | 171 165 117 173 167 111 173 167 111 173 167 111 160 154 106 131 127 93 | ||
| 2408 | 96 95 69 66 65 55 16 17 12 2 2 2 1 1 1 1 1 1 | ||
| 2409 | 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2410 | 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2411 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2412 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2413 | 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 2 | ||
| 2414 | 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 | ||
| 2415 | 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 | ||
| 2416 | 2 2 2 2 2 2 2 2 2 10 9 6 30 31 28 71 71 57 | ||
| 2417 | 118 116 76 149 143 98 165 161 109 165 161 109 165 161 109 173 167 111 | ||
| 2418 | 173 167 111 176 171 126 184 181 136 197 193 154 210 208 158 224 223 159 | ||
| 2419 | 251 251 187 239 239 170 210 208 158 168 163 120 40 41 39 0 0 0 | ||
| 2420 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2421 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2422 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2423 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2424 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2425 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2426 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2427 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2428 | 0 0 0 | ||
| 2429 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2430 | 0 0 0 13 12 7 61 61 53 96 95 69 131 127 93 160 154 106 | ||
| 2431 | 176 171 126 184 181 136 184 181 136 188 184 146 184 181 136 184 181 136 | ||
| 2432 | 184 181 136 186 182 128 186 182 128 178 174 128 174 170 121 149 145 103 | ||
| 2433 | 118 116 76 82 81 62 21 22 20 1 1 1 1 1 1 0 0 0 | ||
| 2434 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2435 | 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 | ||
| 2436 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2437 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2438 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 | ||
| 2439 | 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 2 | ||
| 2440 | 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 | ||
| 2441 | 2 2 2 2 2 2 2 2 2 3 3 3 30 31 28 66 65 55 | ||
| 2442 | 118 116 76 149 143 98 165 161 109 173 167 111 173 167 111 174 170 121 | ||
| 2443 | 186 182 128 190 186 136 197 193 154 210 208 158 224 223 159 251 251 187 | ||
| 2444 | 251 251 187 239 239 170 197 193 154 137 133 100 12 12 9 0 0 0 | ||
| 2445 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2446 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2447 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2448 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2449 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2450 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2451 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2452 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2453 | 0 0 0 | ||
| 2454 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2455 | 0 0 0 0 0 0 30 31 28 71 71 57 103 101 77 134 131 96 | ||
| 2456 | 164 159 111 176 171 126 184 181 136 188 184 146 194 189 146 197 193 154 | ||
| 2457 | 197 193 154 197 193 154 194 191 148 194 189 146 190 186 136 176 171 126 | ||
| 2458 | 145 141 105 103 101 77 40 41 39 0 0 0 0 0 0 0 0 0 | ||
| 2459 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2460 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2461 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2462 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2463 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2464 | 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 2 | ||
| 2465 | 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 | ||
| 2466 | 1 2 2 1 2 2 1 2 2 1 2 2 30 31 28 71 71 57 | ||
| 2467 | 118 116 76 160 154 106 173 167 111 178 174 128 186 182 128 190 186 136 | ||
| 2468 | 194 191 148 204 201 155 210 208 158 224 223 159 251 251 187 251 251 187 | ||
| 2469 | 251 251 187 214 212 158 184 179 149 84 83 72 0 0 0 0 0 0 | ||
| 2470 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2471 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2472 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2473 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2474 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2475 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2476 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2477 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2478 | 0 0 0 | ||
| 2479 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2480 | 0 0 0 0 0 0 5 5 3 43 44 41 82 81 62 103 101 77 | ||
| 2481 | 142 137 94 165 161 109 178 174 128 190 186 136 197 193 154 204 201 155 | ||
| 2482 | 210 208 158 210 208 158 210 208 158 210 208 158 210 208 158 197 193 154 | ||
| 2483 | 177 172 135 145 141 105 79 78 62 5 4 3 0 0 0 0 0 0 | ||
| 2484 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2485 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2486 | 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2487 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2488 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2489 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2490 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2491 | 1 1 1 1 1 1 1 2 2 1 2 2 30 31 28 82 81 62 | ||
| 2492 | 142 137 94 165 161 109 178 174 128 190 186 136 194 191 148 204 201 155 | ||
| 2493 | 210 208 158 214 212 158 239 239 170 251 251 187 251 251 187 251 251 187 | ||
| 2494 | 251 251 187 210 208 158 168 163 120 36 38 35 0 0 0 0 0 0 | ||
| 2495 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2496 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2497 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2498 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2499 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2500 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2501 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2502 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2503 | 0 0 0 | ||
| 2504 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2505 | 0 0 0 0 0 0 0 0 0 16 17 12 53 55 47 82 81 62 | ||
| 2506 | 118 116 76 151 147 98 171 165 117 184 181 136 194 191 148 210 208 158 | ||
| 2507 | 214 212 158 224 223 159 239 239 170 239 239 170 224 223 159 214 212 158 | ||
| 2508 | 197 193 154 176 171 126 115 113 82 24 26 24 0 0 0 0 0 0 | ||
| 2509 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2510 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2511 | 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 | ||
| 2512 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2513 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2514 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2515 | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | ||
| 2516 | 1 1 1 1 1 1 1 1 1 1 1 1 40 41 39 103 101 77 | ||
| 2517 | 151 147 98 176 171 126 190 186 136 197 193 154 210 208 158 214 212 158 | ||
| 2518 | 239 239 170 251 251 187 251 251 187 251 251 187 251 251 187 251 251 187 | ||
| 2519 | 239 239 170 197 193 154 110 109 94 3 4 3 0 0 0 0 0 0 | ||
| 2520 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2521 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2522 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2523 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2524 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2525 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2526 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2527 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2528 | 0 0 0 | ||
| 2529 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2530 | 0 0 0 0 0 0 0 0 0 0 0 0 30 31 28 66 65 55 | ||
| 2531 | 96 95 69 125 122 87 160 154 106 178 174 128 194 189 146 204 201 155 | ||
| 2532 | 214 212 158 239 239 170 251 251 187 251 251 187 251 251 187 239 239 170 | ||
| 2533 | 210 208 158 188 184 146 149 145 103 61 61 53 0 0 0 0 0 0 | ||
| 2534 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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diff --git a/drivers/video/logo/logo_linux_vga16.ppm b/drivers/video/logo/logo_linux_vga16.ppm index 1850c15e6feb..12ac3a5454c0 100644 --- a/drivers/video/logo/logo_linux_vga16.ppm +++ b/drivers/video/logo/logo_linux_vga16.ppm | |||
| @@ -1,1604 +1,2739 @@ | |||
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| 1441 | 170 85 0 0 0 0 0 0 0 0 0 0 | 1440 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1442 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1441 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1443 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1442 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1444 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1443 | 0 0 0 85 85 85 170 170 170 170 170 170 |
| 1445 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1444 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1446 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1445 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1447 | 0 0 0 0 0 0 255 255 85 170 85 0 | 1446 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1448 | 255 255 85 170 85 0 255 255 85 170 85 0 | 1447 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1449 | 255 255 85 170 85 0 255 255 85 170 85 0 | 1448 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1450 | 255 255 85 170 85 0 255 255 85 170 85 0 | 1449 | 0 0 0 85 85 85 170 170 170 85 85 85 85 85 85 85 85 85 |
| 1451 | 255 255 85 170 85 0 255 255 85 170 85 0 | 1450 | 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 |
| 1452 | 255 255 85 170 85 0 255 255 85 170 85 0 | 1451 | 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 |
| 1453 | 170 85 0 0 0 0 0 0 0 0 0 0 | 1452 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1454 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1453 | 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 |
| 1455 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1454 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 |
| 1456 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1455 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1457 | 0 0 0 0 0 0 85 85 85 170 85 0 | 1456 | 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 85 85 85 |
| 1458 | 170 85 0 255 255 85 170 85 0 255 255 85 | 1457 | 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 |
| 1459 | 170 85 0 255 255 85 170 85 0 255 255 85 | 1458 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1460 | 170 85 0 170 85 0 170 85 0 170 85 0 | 1459 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1461 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1460 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1462 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1461 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1463 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1462 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1464 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1463 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1465 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1464 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1466 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1465 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1467 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1466 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1468 | 0 0 0 0 0 0 170 85 0 170 85 0 | 1467 | 85 85 85 170 170 170 255 255 255 170 170 170 |
| 1469 | 170 85 0 170 85 0 170 85 0 170 85 0 | 1468 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1470 | 170 85 0 255 255 85 170 85 0 255 255 85 | 1469 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1471 | 170 85 0 255 255 85 170 85 0 255 255 85 | 1470 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1472 | 170 85 0 255 255 85 170 85 0 170 85 0 | 1471 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1473 | 170 85 0 0 0 0 0 0 0 0 0 0 | 1472 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1474 | 85 85 85 85 85 85 85 85 85 85 85 85 | 1473 | 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 |
| 1475 | 85 85 85 85 85 85 85 85 85 85 85 85 | 1474 | 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 |
| 1476 | 85 85 85 85 85 85 85 85 85 0 0 0 | 1475 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 |
| 1477 | 0 0 0 0 0 0 0 0 0 170 85 0 | 1476 | 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 |
| 1478 | 170 85 0 170 85 0 255 255 85 170 85 0 | 1477 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 |
| 1479 | 255 255 85 170 85 0 255 255 85 170 85 0 | 1478 | 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 |
| 1480 | 170 85 0 170 85 0 0 0 0 0 0 0 | 1479 | 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 |
| 1481 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1480 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1482 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1481 | 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 |
| 1483 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1482 | 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 |
| 1484 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1483 | 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1485 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1484 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1486 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1485 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1487 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1486 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1488 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1487 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1489 | 0 0 0 0 0 0 170 85 0 170 85 0 | 1488 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1490 | 170 85 0 170 85 0 170 85 0 170 85 0 | 1489 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1491 | 170 85 0 170 85 0 255 255 85 170 85 0 | 1490 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 |
| 1492 | 255 255 85 170 85 0 170 85 0 170 85 0 | 1491 | 170 170 170 255 255 255 170 170 170 170 170 170 |
| 1493 | 85 85 85 85 85 85 85 85 85 85 85 85 | 1492 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1494 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1493 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1495 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1494 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1496 | 0 0 0 0 0 0 0 0 0 85 85 85 | 1495 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1497 | 85 85 85 85 85 85 85 85 85 170 85 0 | 1496 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1498 | 170 85 0 170 85 0 170 85 0 255 255 85 | 1497 | 85 85 85 170 170 170 85 85 85 85 85 85 85 85 85 0 0 0 |
| 1499 | 170 85 0 255 255 85 170 85 0 170 85 0 | 1498 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1500 | 170 85 0 0 0 0 0 0 0 0 0 0 | 1499 | 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 |
| 1501 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1500 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1502 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1501 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1503 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1502 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1504 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1503 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1505 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1504 | 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 85 85 85 |
| 1506 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1505 | 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 |
| 1507 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1506 | 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1508 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1507 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1509 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1508 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1510 | 0 0 0 0 0 0 0 0 0 170 85 0 | 1509 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1511 | 170 85 0 170 85 0 170 85 0 170 85 0 | 1510 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1512 | 170 85 0 170 85 0 170 85 0 170 85 0 | 1511 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1513 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1512 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1514 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1513 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1515 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1514 | 0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 170 170 170 |
| 1516 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1515 | 255 255 255 255 255 255 170 170 170 170 170 170 |
| 1517 | 0 0 0 0 0 0 0 0 0 170 85 0 | 1516 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1518 | 170 85 0 170 85 0 170 85 0 170 85 0 | 1517 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1519 | 170 85 0 170 85 0 170 85 0 170 85 0 | 1518 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1520 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1519 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1521 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1520 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 |
| 1522 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1521 | 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 0 0 0 |
| 1523 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1522 | 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 |
| 1524 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1523 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1525 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1524 | 85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 |
| 1526 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1525 | 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 |
| 1527 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1526 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 |
| 1528 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1527 | 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 |
| 1529 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1528 | 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 |
| 1530 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1529 | 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 |
| 1531 | 0 0 0 170 85 0 170 85 0 170 85 0 | 1530 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1532 | 170 85 0 170 85 0 170 85 0 0 0 0 | 1531 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1533 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1532 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1534 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1533 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1535 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1534 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
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| 1537 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1536 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1538 | 170 85 0 170 85 0 170 85 0 170 85 0 | 1537 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1539 | 170 85 0 170 85 0 170 85 0 0 0 0 | 1538 | 0 0 0 0 0 0 85 85 85 170 170 170 170 170 170 255 255 255 |
| 1540 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1539 | 255 255 255 170 170 170 170 170 170 0 0 0 |
| 1541 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1540 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
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| 1545 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1544 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 |
| 1546 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1545 | 170 170 170 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 |
| 1547 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1546 | 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 |
| 1548 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1547 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
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| 1550 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1549 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 |
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| 1554 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1553 | 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 |
| 1555 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1554 | 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 |
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| 1563 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1562 | 0 0 0 85 85 85 170 170 170 255 255 255 255 255 255 255 255 255 |
| 1564 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1563 | 170 170 170 170 170 170 85 85 85 0 0 0 |
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| 1570 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1569 | 85 85 85 85 85 85 85 85 85 85 85 85 0 0 0 85 85 85 |
| 1571 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1570 | 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 |
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| 1587 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1586 | 170 170 170 170 170 170 255 255 255 255 255 255 255 255 255 170 170 170 |
| 1588 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1587 | 170 170 170 170 170 170 0 0 0 0 0 0 |
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| 1594 | 0 0 0 0 0 0 0 0 0 0 0 0 | 1593 | 85 85 85 85 85 85 85 85 85 85 85 85 0 0 0 85 85 85 |
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| 1604 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 1610 | 170 170 170 255 255 255 255 255 255 255 255 255 170 170 170 170 170 170 | ||
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| 1634 | 255 255 255 255 255 255 255 255 255 255 255 255 170 170 170 170 170 170 | ||
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| 1641 | 85 85 85 85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 | ||
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| 1977 | 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 | ||
| 1978 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1979 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1980 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1981 | 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 | ||
| 1982 | 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 | ||
| 1983 | 85 85 85 85 85 85 0 0 0 85 85 85 85 85 85 85 85 85 | ||
| 1984 | 85 85 85 85 85 85 170 170 170 255 255 85 170 170 170 170 170 170 | ||
| 1985 | 170 170 170 255 255 85 170 170 170 170 170 170 170 170 170 170 85 0 | ||
| 1986 | 170 170 170 255 255 85 170 170 170 255 255 85 170 170 170 255 255 85 | ||
| 1987 | 170 170 170 255 255 85 170 170 170 170 170 170 85 255 85 170 85 0 | ||
| 1988 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1989 | 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 | ||
| 1990 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 | ||
| 1991 | 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 | ||
| 1992 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1993 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1994 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1995 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 1996 | 0 0 0 0 0 0 170 170 170 85 85 85 85 85 85 0 0 0 | ||
| 1997 | 85 85 85 85 85 85 170 170 170 85 85 85 170 170 170 170 85 0 | ||
| 1998 | 170 170 170 85 255 85 170 170 170 170 85 0 170 170 170 170 170 170 | ||
| 1999 | 255 255 85 170 170 170 170 170 170 255 255 255 255 255 85 170 170 170 | ||
| 2000 | 255 255 85 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2001 | 85 85 85 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 | ||
| 2002 | 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 | ||
| 2003 | 0 0 0 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 | ||
| 2004 | 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 | ||
| 2005 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2006 | 0 0 0 85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 | ||
| 2007 | 0 0 0 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 | ||
| 2008 | 85 85 85 170 85 0 170 170 170 170 170 170 170 170 170 255 255 255 | ||
| 2009 | 170 170 170 255 255 255 255 255 85 170 170 170 255 255 85 170 170 170 | ||
| 2010 | 255 255 85 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 | ||
| 2011 | 170 170 170 170 170 170 170 170 170 255 85 85 170 170 170 170 170 170 | ||
| 2012 | 85 85 85 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 | ||
| 2013 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2014 | 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 | ||
| 2015 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2016 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2017 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2018 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2019 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2020 | 0 0 0 0 0 0 85 85 85 85 85 85 170 85 0 85 85 85 | ||
| 2021 | 85 85 85 255 255 85 170 170 170 170 170 170 170 170 170 170 170 170 | ||
| 2022 | 255 255 85 170 170 170 170 170 170 255 255 85 170 170 170 170 170 170 | ||
| 2023 | 170 170 170 255 255 255 255 255 255 170 170 170 255 255 255 170 170 170 | ||
| 2024 | 170 170 170 85 85 85 85 85 85 0 0 0 0 0 0 85 85 85 | ||
| 2025 | 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 | ||
| 2026 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2027 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2028 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2029 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2030 | 85 85 85 170 170 170 170 170 170 85 85 85 0 0 0 0 0 0 | ||
| 2031 | 0 0 0 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 | ||
| 2032 | 85 85 85 85 255 85 170 170 170 255 255 85 255 255 255 255 255 255 | ||
| 2033 | 255 255 255 170 170 170 255 255 255 170 170 170 170 170 170 170 170 170 | ||
| 2034 | 170 170 170 170 170 170 255 255 85 170 170 170 255 255 85 255 255 255 | ||
| 2035 | 255 255 85 255 255 255 255 255 85 170 170 170 170 170 170 170 85 0 | ||
| 2036 | 170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2037 | 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 | ||
| 2038 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2039 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2040 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2041 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2042 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2043 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2044 | 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85 | ||
| 2045 | 85 85 85 170 170 170 255 255 85 170 170 170 255 255 85 170 170 170 | ||
| 2046 | 170 170 170 255 255 85 170 170 170 170 170 170 170 170 170 255 255 85 | ||
| 2047 | 255 255 255 255 255 255 255 255 85 255 255 255 255 255 255 170 170 170 | ||
| 2048 | 255 255 85 85 85 85 85 85 85 0 0 0 0 0 0 85 85 85 | ||
| 2049 | 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2050 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 | ||
| 2051 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2052 | 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2053 | 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 | ||
| 2054 | 85 85 85 170 170 170 170 170 170 0 0 0 0 0 0 0 0 0 | ||
| 2055 | 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 | ||
| 2056 | 85 85 85 170 170 170 170 170 170 170 170 170 255 255 255 170 170 170 | ||
| 2057 | 255 255 255 255 255 255 255 255 255 170 170 170 170 170 170 255 255 85 | ||
| 2058 | 170 170 170 255 255 85 170 170 170 255 255 255 170 170 170 255 255 255 | ||
| 2059 | 255 255 255 255 255 255 170 170 170 255 255 85 170 170 170 255 255 85 | ||
| 2060 | 85 85 85 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 | ||
| 2061 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 | ||
| 2062 | 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2063 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2064 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2065 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2066 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2067 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2068 | 0 0 0 0 0 0 0 0 0 85 85 85 170 85 0 170 170 170 | ||
| 2069 | 255 255 85 170 170 170 170 170 170 255 255 255 255 255 255 255 255 255 | ||
| 2070 | 170 170 170 170 170 170 170 170 170 255 255 85 170 170 170 170 170 170 | ||
| 2071 | 255 255 255 170 170 170 255 255 255 255 255 255 170 170 170 255 255 255 | ||
| 2072 | 170 170 170 170 170 170 85 85 85 0 0 0 85 85 85 0 0 0 | ||
| 2073 | 85 85 85 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 | ||
| 2074 | 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2075 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2076 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 | ||
| 2077 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2078 | 85 85 85 170 170 170 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2079 | 0 0 0 85 85 85 0 0 0 85 85 85 85 85 85 0 0 0 | ||
| 2080 | 85 85 85 170 85 0 255 255 255 170 170 170 255 255 255 255 255 255 | ||
| 2081 | 255 255 85 255 255 255 170 170 170 255 255 85 170 170 170 170 170 170 | ||
| 2082 | 170 170 170 170 170 170 170 170 170 255 255 85 255 255 255 255 255 255 | ||
| 2083 | 170 170 170 255 255 255 255 255 255 170 170 170 170 170 170 170 170 170 | ||
| 2084 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2085 | 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2086 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2087 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2088 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2089 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2090 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2091 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2092 | 0 0 0 0 0 0 0 0 0 85 85 85 85 255 85 170 170 170 | ||
| 2093 | 170 170 170 255 255 85 170 170 170 255 255 255 170 170 170 255 255 255 | ||
| 2094 | 255 255 255 255 255 255 255 255 85 170 170 170 170 170 170 255 255 255 | ||
| 2095 | 170 170 170 255 255 255 255 255 255 170 170 170 255 255 255 255 255 85 | ||
| 2096 | 170 170 170 170 85 0 85 85 85 0 0 0 0 0 0 85 85 85 | ||
| 2097 | 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2098 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2099 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 | ||
| 2100 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2101 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2102 | 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 | ||
| 2103 | 85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 | ||
| 2104 | 85 85 85 170 170 170 170 170 170 255 255 85 170 170 170 255 255 255 | ||
| 2105 | 255 255 255 170 170 170 255 255 255 170 170 170 170 170 170 255 255 85 | ||
| 2106 | 170 170 170 255 255 85 170 170 170 255 255 255 170 170 170 255 255 255 | ||
| 2107 | 255 255 255 255 255 255 255 255 255 255 255 255 170 170 170 255 255 85 | ||
| 2108 | 85 85 85 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 | ||
| 2109 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 | ||
| 2110 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2111 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2112 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2113 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2114 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2115 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2116 | 0 0 0 0 0 0 0 0 0 85 85 85 170 85 0 170 170 170 | ||
| 2117 | 170 170 170 255 255 255 255 255 255 255 255 255 255 255 255 255 255 255 | ||
| 2118 | 170 170 170 170 170 170 170 170 170 170 170 170 255 255 85 170 170 170 | ||
| 2119 | 255 255 85 255 255 255 170 170 170 255 255 255 170 170 170 170 170 170 | ||
| 2120 | 170 170 170 170 170 170 85 85 85 0 0 0 85 85 85 85 85 85 | ||
| 2121 | 0 0 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 | ||
| 2122 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2123 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2124 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2125 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2126 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 | ||
| 2127 | 85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 | ||
| 2128 | 85 85 85 85 85 85 170 170 170 170 170 170 255 255 255 170 170 170 | ||
| 2129 | 255 255 255 170 170 170 255 255 85 170 170 170 170 170 170 170 170 170 | ||
| 2130 | 255 85 85 170 170 170 170 170 170 170 170 170 255 255 255 255 255 255 | ||
| 2131 | 170 170 170 255 255 255 255 255 255 170 170 170 255 255 255 170 170 170 | ||
| 2132 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2133 | 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2134 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2135 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2136 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2137 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2138 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2139 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2140 | 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 170 170 170 | ||
| 2141 | 255 255 85 170 170 170 255 255 255 170 170 170 255 255 255 255 255 255 | ||
| 2142 | 255 255 85 255 255 255 170 170 170 255 255 85 170 170 170 170 170 170 | ||
| 2143 | 170 170 170 170 170 170 255 255 85 170 170 170 170 170 170 255 255 85 | ||
| 2144 | 170 170 170 170 85 0 85 85 85 0 0 0 85 85 85 0 0 0 | ||
| 2145 | 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2146 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2147 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2148 | 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 | ||
| 2149 | 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 | ||
| 2150 | 0 0 0 0 0 0 0 0 0 0 0 0 170 170 170 170 170 170 | ||
| 2151 | 170 170 170 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2152 | 0 0 0 85 85 85 170 170 170 255 255 85 170 170 170 170 170 170 | ||
| 2153 | 255 255 85 170 170 170 170 170 170 170 170 170 170 170 170 255 85 85 | ||
| 2154 | 85 255 85 170 170 170 170 170 170 170 170 170 255 255 85 170 170 170 | ||
| 2155 | 255 255 255 255 255 255 255 255 255 255 255 85 170 170 170 170 170 170 | ||
| 2156 | 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 | ||
| 2157 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2158 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2159 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2160 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2161 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2162 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2163 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2164 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 255 255 85 | ||
| 2165 | 170 170 170 170 170 170 255 255 255 255 255 255 255 255 255 170 170 170 | ||
| 2166 | 255 255 255 170 170 170 170 170 170 170 170 170 170 170 170 255 85 85 | ||
| 2167 | 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 | ||
| 2168 | 170 170 170 85 85 85 85 85 85 0 0 0 85 85 85 0 0 0 | ||
| 2169 | 85 85 85 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 | ||
| 2170 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2171 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2172 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2173 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2174 | 0 0 0 0 0 0 0 0 0 170 170 170 170 170 170 170 170 170 | ||
| 2175 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 | ||
| 2176 | 0 0 0 85 85 85 170 85 0 170 170 170 170 170 170 170 170 170 | ||
| 2177 | 170 170 170 170 170 170 170 170 170 170 85 0 170 170 170 85 255 85 | ||
| 2178 | 255 85 85 170 170 170 255 255 85 170 170 170 170 170 170 255 255 255 | ||
| 2179 | 255 255 255 170 170 170 255 255 255 255 255 255 170 170 170 170 170 170 | ||
| 2180 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2181 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2182 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2184 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2185 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2186 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2187 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2188 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 | ||
| 2189 | 170 170 170 255 255 85 170 170 170 255 255 85 255 255 255 255 255 255 | ||
| 2190 | 170 170 170 170 170 170 255 255 85 170 170 170 255 85 85 85 255 85 | ||
| 2191 | 170 170 170 170 85 0 170 170 170 170 170 170 255 255 85 170 170 170 | ||
| 2192 | 170 85 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 | ||
| 2193 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2194 | 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 | ||
| 2195 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2196 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2197 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2198 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2199 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 | ||
| 2200 | 0 0 0 85 85 85 85 85 85 85 85 85 170 170 170 255 255 85 | ||
| 2201 | 170 170 170 170 85 0 170 170 170 170 170 170 170 85 0 85 85 85 | ||
| 2202 | 170 170 170 170 85 0 85 85 85 170 170 170 170 170 170 170 170 170 | ||
| 2203 | 170 170 170 255 255 255 255 255 255 255 255 85 170 170 170 170 170 170 | ||
| 2204 | 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2205 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2206 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2207 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2208 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2209 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2210 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2211 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2212 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 170 85 0 | ||
| 2213 | 170 170 170 170 170 170 255 255 255 170 170 170 255 255 255 170 170 170 | ||
| 2214 | 255 255 255 170 170 170 170 170 170 170 85 0 170 170 170 85 85 85 | ||
| 2215 | 170 170 170 170 170 170 170 85 0 170 170 170 170 85 0 85 85 85 | ||
| 2216 | 85 255 85 85 85 85 0 0 0 0 0 0 0 0 0 85 85 85 | ||
| 2217 | 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 | ||
| 2218 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2219 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2220 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2221 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2222 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2223 | 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85 | ||
| 2224 | 85 85 85 0 0 0 85 85 85 170 85 0 85 85 85 170 170 170 | ||
| 2225 | 170 85 0 170 170 170 85 255 85 170 85 0 170 170 170 85 85 85 | ||
| 2226 | 170 85 0 170 170 170 170 170 170 255 255 85 170 170 170 255 255 255 | ||
| 2227 | 255 255 85 255 255 255 170 170 170 170 170 170 170 170 170 170 85 0 | ||
| 2228 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2229 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2230 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2231 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2232 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2233 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2234 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2235 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2236 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 | ||
| 2237 | 170 170 170 170 170 170 170 170 170 170 170 170 170 170 170 255 255 85 | ||
| 2238 | 170 170 170 255 255 85 170 170 170 170 170 170 85 255 85 170 170 170 | ||
| 2239 | 170 85 0 170 85 0 170 170 170 85 255 85 85 85 85 170 170 170 | ||
| 2240 | 170 85 0 85 85 85 0 0 0 85 85 85 0 0 0 0 0 0 | ||
| 2241 | 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 0 0 0 | ||
| 2242 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2243 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2244 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2245 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2246 | 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2247 | 0 0 0 0 0 0 0 0 0 85 85 85 170 170 170 85 85 85 | ||
| 2248 | 0 0 0 0 0 0 0 0 0 85 85 85 170 85 0 85 85 85 | ||
| 2249 | 170 170 170 170 85 0 170 170 170 85 85 85 170 170 170 170 85 0 | ||
| 2250 | 170 170 170 85 255 85 170 85 0 170 170 170 170 170 170 170 170 170 | ||
| 2251 | 255 255 255 170 170 170 255 255 255 255 255 255 170 170 170 85 85 85 | ||
| 2252 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2253 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2254 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2255 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2256 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2257 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2258 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2259 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2260 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2261 | 170 85 0 170 170 170 255 255 85 170 170 170 255 255 255 170 170 170 | ||
| 2262 | 170 170 170 170 170 170 170 170 170 170 85 0 170 170 170 170 85 0 | ||
| 2263 | 170 170 170 85 255 85 170 85 0 170 170 170 170 85 0 85 85 85 | ||
| 2264 | 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2265 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2266 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2267 | 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 | ||
| 2268 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2269 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2270 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2271 | 0 0 0 0 0 0 85 85 85 0 0 0 0 0 0 0 0 0 | ||
| 2272 | 0 0 0 0 0 0 0 0 0 85 85 85 85 85 85 85 85 85 | ||
| 2273 | 85 255 85 170 170 170 170 85 0 170 170 170 170 85 0 85 255 85 | ||
| 2274 | 170 170 170 170 85 0 170 170 170 170 170 170 170 170 170 255 255 85 | ||
| 2275 | 170 170 170 255 255 255 170 170 170 170 170 170 170 170 170 0 0 0 | ||
| 2276 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2277 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2278 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2279 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2280 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2281 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2282 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2283 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2284 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2285 | 85 85 85 170 85 0 85 85 85 170 170 170 255 255 85 170 170 170 | ||
| 2286 | 170 170 170 255 255 85 170 170 170 170 170 170 170 170 170 170 85 0 | ||
| 2287 | 170 170 170 85 85 85 170 170 170 170 85 0 170 170 170 85 85 85 | ||
| 2288 | 170 85 0 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2289 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2290 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2291 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2292 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2293 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
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| 2612 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2613 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2614 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2615 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2616 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2617 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2618 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2619 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2620 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2621 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2622 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2623 | 85 85 85 85 85 85 85 85 85 170 85 0 85 85 85 170 85 0 | ||
| 2624 | 85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 | ||
| 2625 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2626 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2627 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2628 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2629 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2630 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2631 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2632 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 170 85 0 | ||
| 2633 | 85 85 85 170 85 0 170 170 170 170 170 170 170 170 170 255 255 85 | ||
| 2634 | 170 170 170 170 170 170 170 85 0 85 85 85 0 0 0 0 0 0 | ||
| 2635 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2636 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2637 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2638 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2639 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2640 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2641 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2642 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2643 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2644 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2645 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2646 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2647 | 0 0 0 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 | ||
| 2648 | 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2649 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2650 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2651 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2652 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2653 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2654 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2655 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2656 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 85 85 85 | ||
| 2657 | 85 85 85 85 255 85 170 85 0 170 170 170 170 85 0 170 170 170 | ||
| 2658 | 85 85 85 85 85 85 85 85 85 0 0 0 0 0 0 0 0 0 | ||
| 2659 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2660 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2661 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2662 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2663 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2664 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2665 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2666 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2667 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2668 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2669 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2670 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2671 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2672 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2673 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2674 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2675 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2676 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2677 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2678 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2679 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2680 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2681 | 0 0 0 85 85 85 85 85 85 85 85 85 85 85 85 85 85 85 | ||
| 2682 | 85 85 85 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2683 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2684 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2685 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2686 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2687 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2688 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2689 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2690 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2691 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2692 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2693 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2694 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2695 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2696 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2697 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2698 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2699 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2700 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2701 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2702 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2703 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2704 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2705 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2706 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2707 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2708 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2709 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2710 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2711 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2712 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2713 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2714 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2715 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2716 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2717 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2718 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2719 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2720 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2721 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2722 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2723 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2724 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2725 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2726 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2727 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2728 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2729 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2730 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2731 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2732 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2733 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2734 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2735 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2736 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2737 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2738 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | ||
| 2739 | 0 0 0 0 0 0 0 0 0 0 0 0 | ||
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c index 8a75d05f4334..fa1a512ce030 100644 --- a/drivers/video/mx3fb.c +++ b/drivers/video/mx3fb.c | |||
| @@ -34,240 +34,240 @@ | |||
| 34 | #include <asm/io.h> | 34 | #include <asm/io.h> |
| 35 | #include <asm/uaccess.h> | 35 | #include <asm/uaccess.h> |
| 36 | 36 | ||
| 37 | #define MX3FB_NAME "mx3_sdc_fb" | 37 | #define MX3FB_NAME "mx3_sdc_fb" |
| 38 | 38 | ||
| 39 | #define MX3FB_REG_OFFSET 0xB4 | 39 | #define MX3FB_REG_OFFSET 0xB4 |
| 40 | 40 | ||
| 41 | /* SDC Registers */ | 41 | /* SDC Registers */ |
| 42 | #define SDC_COM_CONF (0xB4 - MX3FB_REG_OFFSET) | 42 | #define SDC_COM_CONF (0xB4 - MX3FB_REG_OFFSET) |
| 43 | #define SDC_GW_CTRL (0xB8 - MX3FB_REG_OFFSET) | 43 | #define SDC_GW_CTRL (0xB8 - MX3FB_REG_OFFSET) |
| 44 | #define SDC_FG_POS (0xBC - MX3FB_REG_OFFSET) | 44 | #define SDC_FG_POS (0xBC - MX3FB_REG_OFFSET) |
| 45 | #define SDC_BG_POS (0xC0 - MX3FB_REG_OFFSET) | 45 | #define SDC_BG_POS (0xC0 - MX3FB_REG_OFFSET) |
| 46 | #define SDC_CUR_POS (0xC4 - MX3FB_REG_OFFSET) | 46 | #define SDC_CUR_POS (0xC4 - MX3FB_REG_OFFSET) |
| 47 | #define SDC_PWM_CTRL (0xC8 - MX3FB_REG_OFFSET) | 47 | #define SDC_PWM_CTRL (0xC8 - MX3FB_REG_OFFSET) |
| 48 | #define SDC_CUR_MAP (0xCC - MX3FB_REG_OFFSET) | 48 | #define SDC_CUR_MAP (0xCC - MX3FB_REG_OFFSET) |
| 49 | #define SDC_HOR_CONF (0xD0 - MX3FB_REG_OFFSET) | 49 | #define SDC_HOR_CONF (0xD0 - MX3FB_REG_OFFSET) |
| 50 | #define SDC_VER_CONF (0xD4 - MX3FB_REG_OFFSET) | 50 | #define SDC_VER_CONF (0xD4 - MX3FB_REG_OFFSET) |
| 51 | #define SDC_SHARP_CONF_1 (0xD8 - MX3FB_REG_OFFSET) | 51 | #define SDC_SHARP_CONF_1 (0xD8 - MX3FB_REG_OFFSET) |
| 52 | #define SDC_SHARP_CONF_2 (0xDC - MX3FB_REG_OFFSET) | 52 | #define SDC_SHARP_CONF_2 (0xDC - MX3FB_REG_OFFSET) |
| 53 | 53 | ||
| 54 | /* Register bits */ | 54 | /* Register bits */ |
| 55 | #define SDC_COM_TFT_COLOR 0x00000001UL | 55 | #define SDC_COM_TFT_COLOR 0x00000001UL |
| 56 | #define SDC_COM_FG_EN 0x00000010UL | 56 | #define SDC_COM_FG_EN 0x00000010UL |
| 57 | #define SDC_COM_GWSEL 0x00000020UL | 57 | #define SDC_COM_GWSEL 0x00000020UL |
| 58 | #define SDC_COM_GLB_A 0x00000040UL | 58 | #define SDC_COM_GLB_A 0x00000040UL |
| 59 | #define SDC_COM_KEY_COLOR_G 0x00000080UL | 59 | #define SDC_COM_KEY_COLOR_G 0x00000080UL |
| 60 | #define SDC_COM_BG_EN 0x00000200UL | 60 | #define SDC_COM_BG_EN 0x00000200UL |
| 61 | #define SDC_COM_SHARP 0x00001000UL | 61 | #define SDC_COM_SHARP 0x00001000UL |
| 62 | 62 | ||
| 63 | #define SDC_V_SYNC_WIDTH_L 0x00000001UL | 63 | #define SDC_V_SYNC_WIDTH_L 0x00000001UL |
| 64 | 64 | ||
| 65 | /* Display Interface registers */ | 65 | /* Display Interface registers */ |
| 66 | #define DI_DISP_IF_CONF (0x0124 - MX3FB_REG_OFFSET) | 66 | #define DI_DISP_IF_CONF (0x0124 - MX3FB_REG_OFFSET) |
| 67 | #define DI_DISP_SIG_POL (0x0128 - MX3FB_REG_OFFSET) | 67 | #define DI_DISP_SIG_POL (0x0128 - MX3FB_REG_OFFSET) |
| 68 | #define DI_SER_DISP1_CONF (0x012C - MX3FB_REG_OFFSET) | 68 | #define DI_SER_DISP1_CONF (0x012C - MX3FB_REG_OFFSET) |
| 69 | #define DI_SER_DISP2_CONF (0x0130 - MX3FB_REG_OFFSET) | 69 | #define DI_SER_DISP2_CONF (0x0130 - MX3FB_REG_OFFSET) |
| 70 | #define DI_HSP_CLK_PER (0x0134 - MX3FB_REG_OFFSET) | 70 | #define DI_HSP_CLK_PER (0x0134 - MX3FB_REG_OFFSET) |
| 71 | #define DI_DISP0_TIME_CONF_1 (0x0138 - MX3FB_REG_OFFSET) | 71 | #define DI_DISP0_TIME_CONF_1 (0x0138 - MX3FB_REG_OFFSET) |
| 72 | #define DI_DISP0_TIME_CONF_2 (0x013C - MX3FB_REG_OFFSET) | 72 | #define DI_DISP0_TIME_CONF_2 (0x013C - MX3FB_REG_OFFSET) |
| 73 | #define DI_DISP0_TIME_CONF_3 (0x0140 - MX3FB_REG_OFFSET) | 73 | #define DI_DISP0_TIME_CONF_3 (0x0140 - MX3FB_REG_OFFSET) |
| 74 | #define DI_DISP1_TIME_CONF_1 (0x0144 - MX3FB_REG_OFFSET) | 74 | #define DI_DISP1_TIME_CONF_1 (0x0144 - MX3FB_REG_OFFSET) |
| 75 | #define DI_DISP1_TIME_CONF_2 (0x0148 - MX3FB_REG_OFFSET) | 75 | #define DI_DISP1_TIME_CONF_2 (0x0148 - MX3FB_REG_OFFSET) |
| 76 | #define DI_DISP1_TIME_CONF_3 (0x014C - MX3FB_REG_OFFSET) | 76 | #define DI_DISP1_TIME_CONF_3 (0x014C - MX3FB_REG_OFFSET) |
| 77 | #define DI_DISP2_TIME_CONF_1 (0x0150 - MX3FB_REG_OFFSET) | 77 | #define DI_DISP2_TIME_CONF_1 (0x0150 - MX3FB_REG_OFFSET) |
| 78 | #define DI_DISP2_TIME_CONF_2 (0x0154 - MX3FB_REG_OFFSET) | 78 | #define DI_DISP2_TIME_CONF_2 (0x0154 - MX3FB_REG_OFFSET) |
| 79 | #define DI_DISP2_TIME_CONF_3 (0x0158 - MX3FB_REG_OFFSET) | 79 | #define DI_DISP2_TIME_CONF_3 (0x0158 - MX3FB_REG_OFFSET) |
| 80 | #define DI_DISP3_TIME_CONF (0x015C - MX3FB_REG_OFFSET) | 80 | #define DI_DISP3_TIME_CONF (0x015C - MX3FB_REG_OFFSET) |
| 81 | #define DI_DISP0_DB0_MAP (0x0160 - MX3FB_REG_OFFSET) | 81 | #define DI_DISP0_DB0_MAP (0x0160 - MX3FB_REG_OFFSET) |
| 82 | #define DI_DISP0_DB1_MAP (0x0164 - MX3FB_REG_OFFSET) | 82 | #define DI_DISP0_DB1_MAP (0x0164 - MX3FB_REG_OFFSET) |
| 83 | #define DI_DISP0_DB2_MAP (0x0168 - MX3FB_REG_OFFSET) | 83 | #define DI_DISP0_DB2_MAP (0x0168 - MX3FB_REG_OFFSET) |
| 84 | #define DI_DISP0_CB0_MAP (0x016C - MX3FB_REG_OFFSET) | 84 | #define DI_DISP0_CB0_MAP (0x016C - MX3FB_REG_OFFSET) |
| 85 | #define DI_DISP0_CB1_MAP (0x0170 - MX3FB_REG_OFFSET) | 85 | #define DI_DISP0_CB1_MAP (0x0170 - MX3FB_REG_OFFSET) |
| 86 | #define DI_DISP0_CB2_MAP (0x0174 - MX3FB_REG_OFFSET) | 86 | #define DI_DISP0_CB2_MAP (0x0174 - MX3FB_REG_OFFSET) |
| 87 | #define DI_DISP1_DB0_MAP (0x0178 - MX3FB_REG_OFFSET) | 87 | #define DI_DISP1_DB0_MAP (0x0178 - MX3FB_REG_OFFSET) |
| 88 | #define DI_DISP1_DB1_MAP (0x017C - MX3FB_REG_OFFSET) | 88 | #define DI_DISP1_DB1_MAP (0x017C - MX3FB_REG_OFFSET) |
| 89 | #define DI_DISP1_DB2_MAP (0x0180 - MX3FB_REG_OFFSET) | 89 | #define DI_DISP1_DB2_MAP (0x0180 - MX3FB_REG_OFFSET) |
| 90 | #define DI_DISP1_CB0_MAP (0x0184 - MX3FB_REG_OFFSET) | 90 | #define DI_DISP1_CB0_MAP (0x0184 - MX3FB_REG_OFFSET) |
| 91 | #define DI_DISP1_CB1_MAP (0x0188 - MX3FB_REG_OFFSET) | 91 | #define DI_DISP1_CB1_MAP (0x0188 - MX3FB_REG_OFFSET) |
| 92 | #define DI_DISP1_CB2_MAP (0x018C - MX3FB_REG_OFFSET) | 92 | #define DI_DISP1_CB2_MAP (0x018C - MX3FB_REG_OFFSET) |
| 93 | #define DI_DISP2_DB0_MAP (0x0190 - MX3FB_REG_OFFSET) | 93 | #define DI_DISP2_DB0_MAP (0x0190 - MX3FB_REG_OFFSET) |
| 94 | #define DI_DISP2_DB1_MAP (0x0194 - MX3FB_REG_OFFSET) | 94 | #define DI_DISP2_DB1_MAP (0x0194 - MX3FB_REG_OFFSET) |
| 95 | #define DI_DISP2_DB2_MAP (0x0198 - MX3FB_REG_OFFSET) | 95 | #define DI_DISP2_DB2_MAP (0x0198 - MX3FB_REG_OFFSET) |
| 96 | #define DI_DISP2_CB0_MAP (0x019C - MX3FB_REG_OFFSET) | 96 | #define DI_DISP2_CB0_MAP (0x019C - MX3FB_REG_OFFSET) |
| 97 | #define DI_DISP2_CB1_MAP (0x01A0 - MX3FB_REG_OFFSET) | 97 | #define DI_DISP2_CB1_MAP (0x01A0 - MX3FB_REG_OFFSET) |
| 98 | #define DI_DISP2_CB2_MAP (0x01A4 - MX3FB_REG_OFFSET) | 98 | #define DI_DISP2_CB2_MAP (0x01A4 - MX3FB_REG_OFFSET) |
| 99 | #define DI_DISP3_B0_MAP (0x01A8 - MX3FB_REG_OFFSET) | 99 | #define DI_DISP3_B0_MAP (0x01A8 - MX3FB_REG_OFFSET) |
| 100 | #define DI_DISP3_B1_MAP (0x01AC - MX3FB_REG_OFFSET) | 100 | #define DI_DISP3_B1_MAP (0x01AC - MX3FB_REG_OFFSET) |
| 101 | #define DI_DISP3_B2_MAP (0x01B0 - MX3FB_REG_OFFSET) | 101 | #define DI_DISP3_B2_MAP (0x01B0 - MX3FB_REG_OFFSET) |
| 102 | #define DI_DISP_ACC_CC (0x01B4 - MX3FB_REG_OFFSET) | 102 | #define DI_DISP_ACC_CC (0x01B4 - MX3FB_REG_OFFSET) |
| 103 | #define DI_DISP_LLA_CONF (0x01B8 - MX3FB_REG_OFFSET) | 103 | #define DI_DISP_LLA_CONF (0x01B8 - MX3FB_REG_OFFSET) |
| 104 | #define DI_DISP_LLA_DATA (0x01BC - MX3FB_REG_OFFSET) | 104 | #define DI_DISP_LLA_DATA (0x01BC - MX3FB_REG_OFFSET) |
| 105 | 105 | ||
| 106 | /* DI_DISP_SIG_POL bits */ | 106 | /* DI_DISP_SIG_POL bits */ |
| 107 | #define DI_D3_VSYNC_POL_SHIFT 28 | 107 | #define DI_D3_VSYNC_POL_SHIFT 28 |
| 108 | #define DI_D3_HSYNC_POL_SHIFT 27 | 108 | #define DI_D3_HSYNC_POL_SHIFT 27 |
| 109 | #define DI_D3_DRDY_SHARP_POL_SHIFT 26 | 109 | #define DI_D3_DRDY_SHARP_POL_SHIFT 26 |
| 110 | #define DI_D3_CLK_POL_SHIFT 25 | 110 | #define DI_D3_CLK_POL_SHIFT 25 |
| 111 | #define DI_D3_DATA_POL_SHIFT 24 | 111 | #define DI_D3_DATA_POL_SHIFT 24 |
| 112 | 112 | ||
| 113 | /* DI_DISP_IF_CONF bits */ | 113 | /* DI_DISP_IF_CONF bits */ |
| 114 | #define DI_D3_CLK_IDLE_SHIFT 26 | 114 | #define DI_D3_CLK_IDLE_SHIFT 26 |
| 115 | #define DI_D3_CLK_SEL_SHIFT 25 | 115 | #define DI_D3_CLK_SEL_SHIFT 25 |
| 116 | #define DI_D3_DATAMSK_SHIFT 24 | 116 | #define DI_D3_DATAMSK_SHIFT 24 |
| 117 | 117 | ||
| 118 | enum ipu_panel { | 118 | enum ipu_panel { |
| 119 | IPU_PANEL_SHARP_TFT, | 119 | IPU_PANEL_SHARP_TFT, |
| 120 | IPU_PANEL_TFT, | 120 | IPU_PANEL_TFT, |
| 121 | }; | 121 | }; |
| 122 | 122 | ||
| 123 | struct ipu_di_signal_cfg { | 123 | struct ipu_di_signal_cfg { |
| 124 | unsigned datamask_en:1; | 124 | unsigned datamask_en:1; |
| 125 | unsigned clksel_en:1; | 125 | unsigned clksel_en:1; |
| 126 | unsigned clkidle_en:1; | 126 | unsigned clkidle_en:1; |
| 127 | unsigned data_pol:1; /* true = inverted */ | 127 | unsigned data_pol:1; /* true = inverted */ |
| 128 | unsigned clk_pol:1; /* true = rising edge */ | 128 | unsigned clk_pol:1; /* true = rising edge */ |
| 129 | unsigned enable_pol:1; | 129 | unsigned enable_pol:1; |
| 130 | unsigned Hsync_pol:1; /* true = active high */ | 130 | unsigned Hsync_pol:1; /* true = active high */ |
| 131 | unsigned Vsync_pol:1; | 131 | unsigned Vsync_pol:1; |
| 132 | }; | 132 | }; |
| 133 | 133 | ||
| 134 | static const struct fb_videomode mx3fb_modedb[] = { | 134 | static const struct fb_videomode mx3fb_modedb[] = { |
| 135 | { | 135 | { |
| 136 | /* 240x320 @ 60 Hz */ | 136 | /* 240x320 @ 60 Hz */ |
| 137 | .name = "Sharp-QVGA", | 137 | .name = "Sharp-QVGA", |
| 138 | .refresh = 60, | 138 | .refresh = 60, |
| 139 | .xres = 240, | 139 | .xres = 240, |
| 140 | .yres = 320, | 140 | .yres = 320, |
| 141 | .pixclock = 185925, | 141 | .pixclock = 185925, |
| 142 | .left_margin = 9, | 142 | .left_margin = 9, |
| 143 | .right_margin = 16, | 143 | .right_margin = 16, |
| 144 | .upper_margin = 7, | 144 | .upper_margin = 7, |
| 145 | .lower_margin = 9, | 145 | .lower_margin = 9, |
| 146 | .hsync_len = 1, | 146 | .hsync_len = 1, |
| 147 | .vsync_len = 1, | 147 | .vsync_len = 1, |
| 148 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | | 148 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | |
| 149 | FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT | | 149 | FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT | |
| 150 | FB_SYNC_CLK_IDLE_EN, | 150 | FB_SYNC_CLK_IDLE_EN, |
| 151 | .vmode = FB_VMODE_NONINTERLACED, | 151 | .vmode = FB_VMODE_NONINTERLACED, |
| 152 | .flag = 0, | 152 | .flag = 0, |
| 153 | }, { | 153 | }, { |
| 154 | /* 240x33 @ 60 Hz */ | 154 | /* 240x33 @ 60 Hz */ |
| 155 | .name = "Sharp-CLI", | 155 | .name = "Sharp-CLI", |
| 156 | .refresh = 60, | 156 | .refresh = 60, |
| 157 | .xres = 240, | 157 | .xres = 240, |
| 158 | .yres = 33, | 158 | .yres = 33, |
| 159 | .pixclock = 185925, | 159 | .pixclock = 185925, |
| 160 | .left_margin = 9, | 160 | .left_margin = 9, |
| 161 | .right_margin = 16, | 161 | .right_margin = 16, |
| 162 | .upper_margin = 7, | 162 | .upper_margin = 7, |
| 163 | .lower_margin = 9 + 287, | 163 | .lower_margin = 9 + 287, |
| 164 | .hsync_len = 1, | 164 | .hsync_len = 1, |
| 165 | .vsync_len = 1, | 165 | .vsync_len = 1, |
| 166 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | | 166 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | |
| 167 | FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT | | 167 | FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT | |
| 168 | FB_SYNC_CLK_IDLE_EN, | 168 | FB_SYNC_CLK_IDLE_EN, |
| 169 | .vmode = FB_VMODE_NONINTERLACED, | 169 | .vmode = FB_VMODE_NONINTERLACED, |
| 170 | .flag = 0, | 170 | .flag = 0, |
| 171 | }, { | 171 | }, { |
| 172 | /* 640x480 @ 60 Hz */ | 172 | /* 640x480 @ 60 Hz */ |
| 173 | .name = "NEC-VGA", | 173 | .name = "NEC-VGA", |
| 174 | .refresh = 60, | 174 | .refresh = 60, |
| 175 | .xres = 640, | 175 | .xres = 640, |
| 176 | .yres = 480, | 176 | .yres = 480, |
| 177 | .pixclock = 38255, | 177 | .pixclock = 38255, |
| 178 | .left_margin = 144, | 178 | .left_margin = 144, |
| 179 | .right_margin = 0, | 179 | .right_margin = 0, |
| 180 | .upper_margin = 34, | 180 | .upper_margin = 34, |
| 181 | .lower_margin = 40, | 181 | .lower_margin = 40, |
| 182 | .hsync_len = 1, | 182 | .hsync_len = 1, |
| 183 | .vsync_len = 1, | 183 | .vsync_len = 1, |
| 184 | .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, | 184 | .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, |
| 185 | .vmode = FB_VMODE_NONINTERLACED, | 185 | .vmode = FB_VMODE_NONINTERLACED, |
| 186 | .flag = 0, | 186 | .flag = 0, |
| 187 | }, { | 187 | }, { |
| 188 | /* NTSC TV output */ | 188 | /* NTSC TV output */ |
| 189 | .name = "TV-NTSC", | 189 | .name = "TV-NTSC", |
| 190 | .refresh = 60, | 190 | .refresh = 60, |
| 191 | .xres = 640, | 191 | .xres = 640, |
| 192 | .yres = 480, | 192 | .yres = 480, |
| 193 | .pixclock = 37538, | 193 | .pixclock = 37538, |
| 194 | .left_margin = 38, | 194 | .left_margin = 38, |
| 195 | .right_margin = 858 - 640 - 38 - 3, | 195 | .right_margin = 858 - 640 - 38 - 3, |
| 196 | .upper_margin = 36, | 196 | .upper_margin = 36, |
| 197 | .lower_margin = 518 - 480 - 36 - 1, | 197 | .lower_margin = 518 - 480 - 36 - 1, |
| 198 | .hsync_len = 3, | 198 | .hsync_len = 3, |
| 199 | .vsync_len = 1, | 199 | .vsync_len = 1, |
| 200 | .sync = 0, | 200 | .sync = 0, |
| 201 | .vmode = FB_VMODE_NONINTERLACED, | 201 | .vmode = FB_VMODE_NONINTERLACED, |
| 202 | .flag = 0, | 202 | .flag = 0, |
| 203 | }, { | 203 | }, { |
| 204 | /* PAL TV output */ | 204 | /* PAL TV output */ |
| 205 | .name = "TV-PAL", | 205 | .name = "TV-PAL", |
| 206 | .refresh = 50, | 206 | .refresh = 50, |
| 207 | .xres = 640, | 207 | .xres = 640, |
| 208 | .yres = 480, | 208 | .yres = 480, |
| 209 | .pixclock = 37538, | 209 | .pixclock = 37538, |
| 210 | .left_margin = 38, | 210 | .left_margin = 38, |
| 211 | .right_margin = 960 - 640 - 38 - 32, | 211 | .right_margin = 960 - 640 - 38 - 32, |
| 212 | .upper_margin = 32, | 212 | .upper_margin = 32, |
| 213 | .lower_margin = 555 - 480 - 32 - 3, | 213 | .lower_margin = 555 - 480 - 32 - 3, |
| 214 | .hsync_len = 32, | 214 | .hsync_len = 32, |
| 215 | .vsync_len = 3, | 215 | .vsync_len = 3, |
| 216 | .sync = 0, | 216 | .sync = 0, |
| 217 | .vmode = FB_VMODE_NONINTERLACED, | 217 | .vmode = FB_VMODE_NONINTERLACED, |
| 218 | .flag = 0, | 218 | .flag = 0, |
| 219 | }, { | 219 | }, { |
| 220 | /* TV output VGA mode, 640x480 @ 65 Hz */ | 220 | /* TV output VGA mode, 640x480 @ 65 Hz */ |
| 221 | .name = "TV-VGA", | 221 | .name = "TV-VGA", |
| 222 | .refresh = 60, | 222 | .refresh = 60, |
| 223 | .xres = 640, | 223 | .xres = 640, |
| 224 | .yres = 480, | 224 | .yres = 480, |
| 225 | .pixclock = 40574, | 225 | .pixclock = 40574, |
| 226 | .left_margin = 35, | 226 | .left_margin = 35, |
| 227 | .right_margin = 45, | 227 | .right_margin = 45, |
| 228 | .upper_margin = 9, | 228 | .upper_margin = 9, |
| 229 | .lower_margin = 1, | 229 | .lower_margin = 1, |
| 230 | .hsync_len = 46, | 230 | .hsync_len = 46, |
| 231 | .vsync_len = 5, | 231 | .vsync_len = 5, |
| 232 | .sync = 0, | 232 | .sync = 0, |
| 233 | .vmode = FB_VMODE_NONINTERLACED, | 233 | .vmode = FB_VMODE_NONINTERLACED, |
| 234 | .flag = 0, | 234 | .flag = 0, |
| 235 | }, | 235 | }, |
| 236 | }; | 236 | }; |
| 237 | 237 | ||
| 238 | struct mx3fb_data { | 238 | struct mx3fb_data { |
| 239 | struct fb_info *fbi; | 239 | struct fb_info *fbi; |
| 240 | int backlight_level; | 240 | int backlight_level; |
| 241 | void __iomem *reg_base; | 241 | void __iomem *reg_base; |
| 242 | spinlock_t lock; | 242 | spinlock_t lock; |
| 243 | struct device *dev; | 243 | struct device *dev; |
| 244 | 244 | ||
| 245 | uint32_t h_start_width; | 245 | uint32_t h_start_width; |
| 246 | uint32_t v_start_width; | 246 | uint32_t v_start_width; |
| 247 | }; | 247 | }; |
| 248 | 248 | ||
| 249 | struct dma_chan_request { | 249 | struct dma_chan_request { |
| 250 | struct mx3fb_data *mx3fb; | 250 | struct mx3fb_data *mx3fb; |
| 251 | enum ipu_channel id; | 251 | enum ipu_channel id; |
| 252 | }; | 252 | }; |
| 253 | 253 | ||
| 254 | /* MX3 specific framebuffer information. */ | 254 | /* MX3 specific framebuffer information. */ |
| 255 | struct mx3fb_info { | 255 | struct mx3fb_info { |
| 256 | int blank; | 256 | int blank; |
| 257 | enum ipu_channel ipu_ch; | 257 | enum ipu_channel ipu_ch; |
| 258 | uint32_t cur_ipu_buf; | 258 | uint32_t cur_ipu_buf; |
| 259 | 259 | ||
| 260 | u32 pseudo_palette[16]; | 260 | u32 pseudo_palette[16]; |
| 261 | 261 | ||
| 262 | struct completion flip_cmpl; | 262 | struct completion flip_cmpl; |
| 263 | struct mutex mutex; /* Protects fb-ops */ | 263 | struct mutex mutex; /* Protects fb-ops */ |
| 264 | struct mx3fb_data *mx3fb; | 264 | struct mx3fb_data *mx3fb; |
| 265 | struct idmac_channel *idmac_channel; | 265 | struct idmac_channel *idmac_channel; |
| 266 | struct dma_async_tx_descriptor *txd; | 266 | struct dma_async_tx_descriptor *txd; |
| 267 | dma_cookie_t cookie; | 267 | dma_cookie_t cookie; |
| 268 | struct scatterlist sg[2]; | 268 | struct scatterlist sg[2]; |
| 269 | 269 | ||
| 270 | u32 sync; /* preserve var->sync flags */ | 270 | u32 sync; /* preserve var->sync flags */ |
| 271 | }; | 271 | }; |
| 272 | 272 | ||
| 273 | static void mx3fb_dma_done(void *); | 273 | static void mx3fb_dma_done(void *); |
| @@ -278,389 +278,389 @@ static unsigned long default_bpp = 16; | |||
| 278 | 278 | ||
| 279 | static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg) | 279 | static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg) |
| 280 | { | 280 | { |
| 281 | return __raw_readl(mx3fb->reg_base + reg); | 281 | return __raw_readl(mx3fb->reg_base + reg); |
| 282 | } | 282 | } |
| 283 | 283 | ||
| 284 | static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg) | 284 | static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg) |
| 285 | { | 285 | { |
| 286 | __raw_writel(value, mx3fb->reg_base + reg); | 286 | __raw_writel(value, mx3fb->reg_base + reg); |
| 287 | } | 287 | } |
| 288 | 288 | ||
| 289 | static const uint32_t di_mappings[] = { | 289 | static const uint32_t di_mappings[] = { |
| 290 | 0x1600AAAA, 0x00E05555, 0x00070000, 3, /* RGB888 */ | 290 | 0x1600AAAA, 0x00E05555, 0x00070000, 3, /* RGB888 */ |
| 291 | 0x0005000F, 0x000B000F, 0x0011000F, 1, /* RGB666 */ | 291 | 0x0005000F, 0x000B000F, 0x0011000F, 1, /* RGB666 */ |
| 292 | 0x0011000F, 0x000B000F, 0x0005000F, 1, /* BGR666 */ | 292 | 0x0011000F, 0x000B000F, 0x0005000F, 1, /* BGR666 */ |
| 293 | 0x0004003F, 0x000A000F, 0x000F003F, 1 /* RGB565 */ | 293 | 0x0004003F, 0x000A000F, 0x000F003F, 1 /* RGB565 */ |
| 294 | }; | 294 | }; |
| 295 | 295 | ||
| 296 | static void sdc_fb_init(struct mx3fb_info *fbi) | 296 | static void sdc_fb_init(struct mx3fb_info *fbi) |
| 297 | { | 297 | { |
| 298 | struct mx3fb_data *mx3fb = fbi->mx3fb; | 298 | struct mx3fb_data *mx3fb = fbi->mx3fb; |
| 299 | uint32_t reg; | 299 | uint32_t reg; |
| 300 | 300 | ||
| 301 | reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); | 301 | reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); |
| 302 | 302 | ||
| 303 | mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF); | 303 | mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF); |
| 304 | } | 304 | } |
| 305 | 305 | ||
| 306 | /* Returns enabled flag before uninit */ | 306 | /* Returns enabled flag before uninit */ |
| 307 | static uint32_t sdc_fb_uninit(struct mx3fb_info *fbi) | 307 | static uint32_t sdc_fb_uninit(struct mx3fb_info *fbi) |
| 308 | { | 308 | { |
| 309 | struct mx3fb_data *mx3fb = fbi->mx3fb; | 309 | struct mx3fb_data *mx3fb = fbi->mx3fb; |
| 310 | uint32_t reg; | 310 | uint32_t reg; |
| 311 | 311 | ||
| 312 | reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); | 312 | reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); |
| 313 | 313 | ||
| 314 | mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF); | 314 | mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF); |
| 315 | 315 | ||
| 316 | return reg & SDC_COM_BG_EN; | 316 | return reg & SDC_COM_BG_EN; |
| 317 | } | 317 | } |
| 318 | 318 | ||
| 319 | static void sdc_enable_channel(struct mx3fb_info *mx3_fbi) | 319 | static void sdc_enable_channel(struct mx3fb_info *mx3_fbi) |
| 320 | { | 320 | { |
| 321 | struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; | 321 | struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; |
| 322 | struct idmac_channel *ichan = mx3_fbi->idmac_channel; | 322 | struct idmac_channel *ichan = mx3_fbi->idmac_channel; |
| 323 | struct dma_chan *dma_chan = &ichan->dma_chan; | 323 | struct dma_chan *dma_chan = &ichan->dma_chan; |
| 324 | unsigned long flags; | 324 | unsigned long flags; |
| 325 | dma_cookie_t cookie; | 325 | dma_cookie_t cookie; |
| 326 | 326 | ||
| 327 | dev_dbg(mx3fb->dev, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi, | 327 | dev_dbg(mx3fb->dev, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi, |
| 328 | to_tx_desc(mx3_fbi->txd), to_tx_desc(mx3_fbi->txd)->sg); | 328 | to_tx_desc(mx3_fbi->txd), to_tx_desc(mx3_fbi->txd)->sg); |
| 329 | 329 | ||
| 330 | /* This enables the channel */ | 330 | /* This enables the channel */ |
| 331 | if (mx3_fbi->cookie < 0) { | 331 | if (mx3_fbi->cookie < 0) { |
| 332 | mx3_fbi->txd = dma_chan->device->device_prep_slave_sg(dma_chan, | 332 | mx3_fbi->txd = dma_chan->device->device_prep_slave_sg(dma_chan, |
| 333 | &mx3_fbi->sg[0], 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT); | 333 | &mx3_fbi->sg[0], 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT); |
| 334 | if (!mx3_fbi->txd) { | 334 | if (!mx3_fbi->txd) { |
| 335 | dev_err(mx3fb->dev, "Cannot allocate descriptor on %d\n", | 335 | dev_err(mx3fb->dev, "Cannot allocate descriptor on %d\n", |
| 336 | dma_chan->chan_id); | 336 | dma_chan->chan_id); |
| 337 | return; | 337 | return; |
| 338 | } | 338 | } |
| 339 | 339 | ||
| 340 | mx3_fbi->txd->callback_param = mx3_fbi->txd; | 340 | mx3_fbi->txd->callback_param = mx3_fbi->txd; |
| 341 | mx3_fbi->txd->callback = mx3fb_dma_done; | 341 | mx3_fbi->txd->callback = mx3fb_dma_done; |
| 342 | 342 | ||
| 343 | cookie = mx3_fbi->txd->tx_submit(mx3_fbi->txd); | 343 | cookie = mx3_fbi->txd->tx_submit(mx3_fbi->txd); |
| 344 | dev_dbg(mx3fb->dev, "%d: Submit %p #%d [%c]\n", __LINE__, | 344 | dev_dbg(mx3fb->dev, "%d: Submit %p #%d [%c]\n", __LINE__, |
| 345 | mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+'); | 345 | mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+'); |
| 346 | } else { | 346 | } else { |
| 347 | if (!mx3_fbi->txd || !mx3_fbi->txd->tx_submit) { | 347 | if (!mx3_fbi->txd || !mx3_fbi->txd->tx_submit) { |
| 348 | dev_err(mx3fb->dev, "Cannot enable channel %d\n", | 348 | dev_err(mx3fb->dev, "Cannot enable channel %d\n", |
| 349 | dma_chan->chan_id); | 349 | dma_chan->chan_id); |
| 350 | return; | 350 | return; |
| 351 | } | 351 | } |
| 352 | 352 | ||
| 353 | /* Just re-activate the same buffer */ | 353 | /* Just re-activate the same buffer */ |
| 354 | dma_async_issue_pending(dma_chan); | 354 | dma_async_issue_pending(dma_chan); |
| 355 | cookie = mx3_fbi->cookie; | 355 | cookie = mx3_fbi->cookie; |
| 356 | dev_dbg(mx3fb->dev, "%d: Re-submit %p #%d [%c]\n", __LINE__, | 356 | dev_dbg(mx3fb->dev, "%d: Re-submit %p #%d [%c]\n", __LINE__, |
| 357 | mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+'); | 357 | mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+'); |
| 358 | } | 358 | } |
| 359 | 359 | ||
| 360 | if (cookie >= 0) { | 360 | if (cookie >= 0) { |
| 361 | spin_lock_irqsave(&mx3fb->lock, flags); | 361 | spin_lock_irqsave(&mx3fb->lock, flags); |
| 362 | sdc_fb_init(mx3_fbi); | 362 | sdc_fb_init(mx3_fbi); |
| 363 | mx3_fbi->cookie = cookie; | 363 | mx3_fbi->cookie = cookie; |
| 364 | spin_unlock_irqrestore(&mx3fb->lock, flags); | 364 | spin_unlock_irqrestore(&mx3fb->lock, flags); |
| 365 | } | 365 | } |
| 366 | 366 | ||
| 367 | /* | 367 | /* |
| 368 | * Attention! Without this msleep the channel keeps generating | 368 | * Attention! Without this msleep the channel keeps generating |
| 369 | * interrupts. Next sdc_set_brightness() is going to be called | 369 | * interrupts. Next sdc_set_brightness() is going to be called |
| 370 | * from mx3fb_blank(). | 370 | * from mx3fb_blank(). |
| 371 | */ | 371 | */ |
| 372 | msleep(2); | 372 | msleep(2); |
| 373 | } | 373 | } |
| 374 | 374 | ||
| 375 | static void sdc_disable_channel(struct mx3fb_info *mx3_fbi) | 375 | static void sdc_disable_channel(struct mx3fb_info *mx3_fbi) |
| 376 | { | 376 | { |
| 377 | struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; | 377 | struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; |
| 378 | uint32_t enabled; | 378 | uint32_t enabled; |
| 379 | unsigned long flags; | 379 | unsigned long flags; |
| 380 | 380 | ||
| 381 | spin_lock_irqsave(&mx3fb->lock, flags); | 381 | spin_lock_irqsave(&mx3fb->lock, flags); |
| 382 | 382 | ||
| 383 | enabled = sdc_fb_uninit(mx3_fbi); | 383 | enabled = sdc_fb_uninit(mx3_fbi); |
| 384 | 384 | ||
| 385 | spin_unlock_irqrestore(&mx3fb->lock, flags); | 385 | spin_unlock_irqrestore(&mx3fb->lock, flags); |
| 386 | 386 | ||
| 387 | mx3_fbi->txd->chan->device->device_terminate_all(mx3_fbi->txd->chan); | 387 | mx3_fbi->txd->chan->device->device_terminate_all(mx3_fbi->txd->chan); |
| 388 | mx3_fbi->txd = NULL; | 388 | mx3_fbi->txd = NULL; |
| 389 | mx3_fbi->cookie = -EINVAL; | 389 | mx3_fbi->cookie = -EINVAL; |
| 390 | } | 390 | } |
| 391 | 391 | ||
| 392 | /** | 392 | /** |
| 393 | * sdc_set_window_pos() - set window position of the respective plane. | 393 | * sdc_set_window_pos() - set window position of the respective plane. |
| 394 | * @mx3fb: mx3fb context. | 394 | * @mx3fb: mx3fb context. |
| 395 | * @channel: IPU DMAC channel ID. | 395 | * @channel: IPU DMAC channel ID. |
| 396 | * @x_pos: X coordinate relative to the top left corner to place window at. | 396 | * @x_pos: X coordinate relative to the top left corner to place window at. |
| 397 | * @y_pos: Y coordinate relative to the top left corner to place window at. | 397 | * @y_pos: Y coordinate relative to the top left corner to place window at. |
| 398 | * @return: 0 on success or negative error code on failure. | 398 | * @return: 0 on success or negative error code on failure. |
| 399 | */ | 399 | */ |
| 400 | static int sdc_set_window_pos(struct mx3fb_data *mx3fb, enum ipu_channel channel, | 400 | static int sdc_set_window_pos(struct mx3fb_data *mx3fb, enum ipu_channel channel, |
| 401 | int16_t x_pos, int16_t y_pos) | 401 | int16_t x_pos, int16_t y_pos) |
| 402 | { | 402 | { |
| 403 | x_pos += mx3fb->h_start_width; | 403 | x_pos += mx3fb->h_start_width; |
| 404 | y_pos += mx3fb->v_start_width; | 404 | y_pos += mx3fb->v_start_width; |
| 405 | 405 | ||
| 406 | if (channel != IDMAC_SDC_0) | 406 | if (channel != IDMAC_SDC_0) |
| 407 | return -EINVAL; | 407 | return -EINVAL; |
| 408 | 408 | ||
| 409 | mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS); | 409 | mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS); |
| 410 | return 0; | 410 | return 0; |
| 411 | } | 411 | } |
| 412 | 412 | ||
| 413 | /** | 413 | /** |
| 414 | * sdc_init_panel() - initialize a synchronous LCD panel. | 414 | * sdc_init_panel() - initialize a synchronous LCD panel. |
| 415 | * @mx3fb: mx3fb context. | 415 | * @mx3fb: mx3fb context. |
| 416 | * @panel: panel type. | 416 | * @panel: panel type. |
| 417 | * @pixel_clk: desired pixel clock frequency in Hz. | 417 | * @pixel_clk: desired pixel clock frequency in Hz. |
| 418 | * @width: width of panel in pixels. | 418 | * @width: width of panel in pixels. |
| 419 | * @height: height of panel in pixels. | 419 | * @height: height of panel in pixels. |
| 420 | * @pixel_fmt: pixel format of buffer as FOURCC ASCII code. | 420 | * @pixel_fmt: pixel format of buffer as FOURCC ASCII code. |
| 421 | * @h_start_width: number of pixel clocks between the HSYNC signal pulse | 421 | * @h_start_width: number of pixel clocks between the HSYNC signal pulse |
| 422 | * and the start of valid data. | 422 | * and the start of valid data. |
| 423 | * @h_sync_width: width of the HSYNC signal in units of pixel clocks. | 423 | * @h_sync_width: width of the HSYNC signal in units of pixel clocks. |
| 424 | * @h_end_width: number of pixel clocks between the end of valid data | 424 | * @h_end_width: number of pixel clocks between the end of valid data |
| 425 | * and the HSYNC signal for next line. | 425 | * and the HSYNC signal for next line. |
| 426 | * @v_start_width: number of lines between the VSYNC signal pulse and the | 426 | * @v_start_width: number of lines between the VSYNC signal pulse and the |
| 427 | * start of valid data. | 427 | * start of valid data. |
| 428 | * @v_sync_width: width of the VSYNC signal in units of lines | 428 | * @v_sync_width: width of the VSYNC signal in units of lines |
| 429 | * @v_end_width: number of lines between the end of valid data and the | 429 | * @v_end_width: number of lines between the end of valid data and the |
| 430 | * VSYNC signal for next frame. | 430 | * VSYNC signal for next frame. |
| 431 | * @sig: bitfield of signal polarities for LCD interface. | 431 | * @sig: bitfield of signal polarities for LCD interface. |
| 432 | * @return: 0 on success or negative error code on failure. | 432 | * @return: 0 on success or negative error code on failure. |
| 433 | */ | 433 | */ |
| 434 | static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel, | 434 | static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel, |
| 435 | uint32_t pixel_clk, | 435 | uint32_t pixel_clk, |
| 436 | uint16_t width, uint16_t height, | 436 | uint16_t width, uint16_t height, |
| 437 | enum pixel_fmt pixel_fmt, | 437 | enum pixel_fmt pixel_fmt, |
| 438 | uint16_t h_start_width, uint16_t h_sync_width, | 438 | uint16_t h_start_width, uint16_t h_sync_width, |
| 439 | uint16_t h_end_width, uint16_t v_start_width, | 439 | uint16_t h_end_width, uint16_t v_start_width, |
| 440 | uint16_t v_sync_width, uint16_t v_end_width, | 440 | uint16_t v_sync_width, uint16_t v_end_width, |
| 441 | struct ipu_di_signal_cfg sig) | 441 | struct ipu_di_signal_cfg sig) |
| 442 | { | 442 | { |
| 443 | unsigned long lock_flags; | 443 | unsigned long lock_flags; |
| 444 | uint32_t reg; | 444 | uint32_t reg; |
| 445 | uint32_t old_conf; | 445 | uint32_t old_conf; |
| 446 | uint32_t div; | 446 | uint32_t div; |
| 447 | struct clk *ipu_clk; | 447 | struct clk *ipu_clk; |
| 448 | 448 | ||
| 449 | dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height); | 449 | dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height); |
| 450 | 450 | ||
| 451 | if (v_sync_width == 0 || h_sync_width == 0) | 451 | if (v_sync_width == 0 || h_sync_width == 0) |
| 452 | return -EINVAL; | 452 | return -EINVAL; |
| 453 | 453 | ||
| 454 | /* Init panel size and blanking periods */ | 454 | /* Init panel size and blanking periods */ |
| 455 | reg = ((uint32_t) (h_sync_width - 1) << 26) | | 455 | reg = ((uint32_t) (h_sync_width - 1) << 26) | |
| 456 | ((uint32_t) (width + h_start_width + h_end_width - 1) << 16); | 456 | ((uint32_t) (width + h_start_width + h_end_width - 1) << 16); |
| 457 | mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF); | 457 | mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF); |
| 458 | 458 | ||
| 459 | #ifdef DEBUG | 459 | #ifdef DEBUG |
| 460 | printk(KERN_CONT " hor_conf %x,", reg); | 460 | printk(KERN_CONT " hor_conf %x,", reg); |
| 461 | #endif | 461 | #endif |
| 462 | 462 | ||
| 463 | reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L | | 463 | reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L | |
| 464 | ((uint32_t) (height + v_start_width + v_end_width - 1) << 16); | 464 | ((uint32_t) (height + v_start_width + v_end_width - 1) << 16); |
| 465 | mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF); | 465 | mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF); |
| 466 | 466 | ||
| 467 | #ifdef DEBUG | 467 | #ifdef DEBUG |
| 468 | printk(KERN_CONT " ver_conf %x\n", reg); | 468 | printk(KERN_CONT " ver_conf %x\n", reg); |
| 469 | #endif | 469 | #endif |
| 470 | 470 | ||
| 471 | mx3fb->h_start_width = h_start_width; | 471 | mx3fb->h_start_width = h_start_width; |
| 472 | mx3fb->v_start_width = v_start_width; | 472 | mx3fb->v_start_width = v_start_width; |
| 473 | 473 | ||
| 474 | switch (panel) { | 474 | switch (panel) { |
| 475 | case IPU_PANEL_SHARP_TFT: | 475 | case IPU_PANEL_SHARP_TFT: |
| 476 | mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1); | 476 | mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1); |
| 477 | mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2); | 477 | mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2); |
| 478 | mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF); | 478 | mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF); |
| 479 | break; | 479 | break; |
| 480 | case IPU_PANEL_TFT: | 480 | case IPU_PANEL_TFT: |
| 481 | mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF); | 481 | mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF); |
| 482 | break; | 482 | break; |
| 483 | default: | 483 | default: |
| 484 | return -EINVAL; | 484 | return -EINVAL; |
| 485 | } | 485 | } |
| 486 | 486 | ||
| 487 | /* Init clocking */ | 487 | /* Init clocking */ |
| 488 | 488 | ||
| 489 | /* | 489 | /* |
| 490 | * Calculate divider: fractional part is 4 bits so simply multiple by | 490 | * Calculate divider: fractional part is 4 bits so simply multiple by |
| 491 | * 24 to get fractional part, as long as we stay under ~250MHz and on | 491 | * 2^4 to get fractional part, as long as we stay under ~250MHz and on |
| 492 | * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz | 492 | * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz |
| 493 | */ | 493 | */ |
| 494 | dev_dbg(mx3fb->dev, "pixel clk = %d\n", pixel_clk); | 494 | dev_dbg(mx3fb->dev, "pixel clk = %d\n", pixel_clk); |
| 495 | 495 | ||
| 496 | ipu_clk = clk_get(mx3fb->dev, "ipu_clk"); | 496 | ipu_clk = clk_get(mx3fb->dev, NULL); |
| 497 | div = clk_get_rate(ipu_clk) * 16 / pixel_clk; | 497 | div = clk_get_rate(ipu_clk) * 16 / pixel_clk; |
| 498 | clk_put(ipu_clk); | 498 | clk_put(ipu_clk); |
| 499 | 499 | ||
| 500 | if (div < 0x40) { /* Divider less than 4 */ | 500 | if (div < 0x40) { /* Divider less than 4 */ |
| 501 | dev_dbg(mx3fb->dev, | 501 | dev_dbg(mx3fb->dev, |
| 502 | "InitPanel() - Pixel clock divider less than 4\n"); | 502 | "InitPanel() - Pixel clock divider less than 4\n"); |
| 503 | div = 0x40; | 503 | div = 0x40; |
| 504 | } | 504 | } |
| 505 | 505 | ||
| 506 | spin_lock_irqsave(&mx3fb->lock, lock_flags); | 506 | spin_lock_irqsave(&mx3fb->lock, lock_flags); |
| 507 | 507 | ||
| 508 | /* | 508 | /* |
| 509 | * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits | 509 | * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits |
| 510 | * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing | 510 | * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing |
| 511 | * debug. DISP3_IF_CLK_UP_WR is 0 | 511 | * debug. DISP3_IF_CLK_UP_WR is 0 |
| 512 | */ | 512 | */ |
| 513 | mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF); | 513 | mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF); |
| 514 | 514 | ||
| 515 | /* DI settings */ | 515 | /* DI settings */ |
| 516 | old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF; | 516 | old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF; |
| 517 | old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT | | 517 | old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT | |
| 518 | sig.clksel_en << DI_D3_CLK_SEL_SHIFT | | 518 | sig.clksel_en << DI_D3_CLK_SEL_SHIFT | |
| 519 | sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT; | 519 | sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT; |
| 520 | mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF); | 520 | mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF); |
| 521 | 521 | ||
| 522 | old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF; | 522 | old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF; |
| 523 | old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT | | 523 | old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT | |
| 524 | sig.clk_pol << DI_D3_CLK_POL_SHIFT | | 524 | sig.clk_pol << DI_D3_CLK_POL_SHIFT | |
| 525 | sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT | | 525 | sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT | |
| 526 | sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT | | 526 | sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT | |
| 527 | sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT; | 527 | sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT; |
| 528 | mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL); | 528 | mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL); |
| 529 | 529 | ||
| 530 | switch (pixel_fmt) { | 530 | switch (pixel_fmt) { |
| 531 | case IPU_PIX_FMT_RGB24: | 531 | case IPU_PIX_FMT_RGB24: |
| 532 | mx3fb_write_reg(mx3fb, di_mappings[0], DI_DISP3_B0_MAP); | 532 | mx3fb_write_reg(mx3fb, di_mappings[0], DI_DISP3_B0_MAP); |
| 533 | mx3fb_write_reg(mx3fb, di_mappings[1], DI_DISP3_B1_MAP); | 533 | mx3fb_write_reg(mx3fb, di_mappings[1], DI_DISP3_B1_MAP); |
| 534 | mx3fb_write_reg(mx3fb, di_mappings[2], DI_DISP3_B2_MAP); | 534 | mx3fb_write_reg(mx3fb, di_mappings[2], DI_DISP3_B2_MAP); |
| 535 | mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | | 535 | mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | |
| 536 | ((di_mappings[3] - 1) << 12), DI_DISP_ACC_CC); | 536 | ((di_mappings[3] - 1) << 12), DI_DISP_ACC_CC); |
| 537 | break; | 537 | break; |
| 538 | case IPU_PIX_FMT_RGB666: | 538 | case IPU_PIX_FMT_RGB666: |
| 539 | mx3fb_write_reg(mx3fb, di_mappings[4], DI_DISP3_B0_MAP); | 539 | mx3fb_write_reg(mx3fb, di_mappings[4], DI_DISP3_B0_MAP); |
| 540 | mx3fb_write_reg(mx3fb, di_mappings[5], DI_DISP3_B1_MAP); | 540 | mx3fb_write_reg(mx3fb, di_mappings[5], DI_DISP3_B1_MAP); |
| 541 | mx3fb_write_reg(mx3fb, di_mappings[6], DI_DISP3_B2_MAP); | 541 | mx3fb_write_reg(mx3fb, di_mappings[6], DI_DISP3_B2_MAP); |
| 542 | mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | | 542 | mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | |
| 543 | ((di_mappings[7] - 1) << 12), DI_DISP_ACC_CC); | 543 | ((di_mappings[7] - 1) << 12), DI_DISP_ACC_CC); |
| 544 | break; | 544 | break; |
| 545 | case IPU_PIX_FMT_BGR666: | 545 | case IPU_PIX_FMT_BGR666: |
| 546 | mx3fb_write_reg(mx3fb, di_mappings[8], DI_DISP3_B0_MAP); | 546 | mx3fb_write_reg(mx3fb, di_mappings[8], DI_DISP3_B0_MAP); |
| 547 | mx3fb_write_reg(mx3fb, di_mappings[9], DI_DISP3_B1_MAP); | 547 | mx3fb_write_reg(mx3fb, di_mappings[9], DI_DISP3_B1_MAP); |
| 548 | mx3fb_write_reg(mx3fb, di_mappings[10], DI_DISP3_B2_MAP); | 548 | mx3fb_write_reg(mx3fb, di_mappings[10], DI_DISP3_B2_MAP); |
| 549 | mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | | 549 | mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | |
| 550 | ((di_mappings[11] - 1) << 12), DI_DISP_ACC_CC); | 550 | ((di_mappings[11] - 1) << 12), DI_DISP_ACC_CC); |
| 551 | break; | 551 | break; |
| 552 | default: | 552 | default: |
| 553 | mx3fb_write_reg(mx3fb, di_mappings[12], DI_DISP3_B0_MAP); | 553 | mx3fb_write_reg(mx3fb, di_mappings[12], DI_DISP3_B0_MAP); |
| 554 | mx3fb_write_reg(mx3fb, di_mappings[13], DI_DISP3_B1_MAP); | 554 | mx3fb_write_reg(mx3fb, di_mappings[13], DI_DISP3_B1_MAP); |
| 555 | mx3fb_write_reg(mx3fb, di_mappings[14], DI_DISP3_B2_MAP); | 555 | mx3fb_write_reg(mx3fb, di_mappings[14], DI_DISP3_B2_MAP); |
| 556 | mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | | 556 | mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) | |
| 557 | ((di_mappings[15] - 1) << 12), DI_DISP_ACC_CC); | 557 | ((di_mappings[15] - 1) << 12), DI_DISP_ACC_CC); |
| 558 | break; | 558 | break; |
| 559 | } | 559 | } |
| 560 | 560 | ||
| 561 | spin_unlock_irqrestore(&mx3fb->lock, lock_flags); | 561 | spin_unlock_irqrestore(&mx3fb->lock, lock_flags); |
| 562 | 562 | ||
| 563 | dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n", | 563 | dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n", |
| 564 | mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF)); | 564 | mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF)); |
| 565 | dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n", | 565 | dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n", |
| 566 | mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL)); | 566 | mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL)); |
| 567 | dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n", | 567 | dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n", |
| 568 | mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF)); | 568 | mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF)); |
| 569 | 569 | ||
| 570 | return 0; | 570 | return 0; |
| 571 | } | 571 | } |
| 572 | 572 | ||
| 573 | /** | 573 | /** |
| 574 | * sdc_set_color_key() - set the transparent color key for SDC graphic plane. | 574 | * sdc_set_color_key() - set the transparent color key for SDC graphic plane. |
| 575 | * @mx3fb: mx3fb context. | 575 | * @mx3fb: mx3fb context. |
| 576 | * @channel: IPU DMAC channel ID. | 576 | * @channel: IPU DMAC channel ID. |
| 577 | * @enable: boolean to enable or disable color keyl. | 577 | * @enable: boolean to enable or disable color keyl. |
| 578 | * @color_key: 24-bit RGB color to use as transparent color key. | 578 | * @color_key: 24-bit RGB color to use as transparent color key. |
| 579 | * @return: 0 on success or negative error code on failure. | 579 | * @return: 0 on success or negative error code on failure. |
| 580 | */ | 580 | */ |
| 581 | static int sdc_set_color_key(struct mx3fb_data *mx3fb, enum ipu_channel channel, | 581 | static int sdc_set_color_key(struct mx3fb_data *mx3fb, enum ipu_channel channel, |
| 582 | bool enable, uint32_t color_key) | 582 | bool enable, uint32_t color_key) |
| 583 | { | 583 | { |
| 584 | uint32_t reg, sdc_conf; | 584 | uint32_t reg, sdc_conf; |
| 585 | unsigned long lock_flags; | 585 | unsigned long lock_flags; |
| 586 | 586 | ||
| 587 | spin_lock_irqsave(&mx3fb->lock, lock_flags); | 587 | spin_lock_irqsave(&mx3fb->lock, lock_flags); |
| 588 | 588 | ||
| 589 | sdc_conf = mx3fb_read_reg(mx3fb, SDC_COM_CONF); | 589 | sdc_conf = mx3fb_read_reg(mx3fb, SDC_COM_CONF); |
| 590 | if (channel == IDMAC_SDC_0) | 590 | if (channel == IDMAC_SDC_0) |
| 591 | sdc_conf &= ~SDC_COM_GWSEL; | 591 | sdc_conf &= ~SDC_COM_GWSEL; |
| 592 | else | 592 | else |
| 593 | sdc_conf |= SDC_COM_GWSEL; | 593 | sdc_conf |= SDC_COM_GWSEL; |
| 594 | 594 | ||
| 595 | if (enable) { | 595 | if (enable) { |
| 596 | reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L; | 596 | reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L; |
| 597 | mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL), | 597 | mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL), |
| 598 | SDC_GW_CTRL); | 598 | SDC_GW_CTRL); |
| 599 | 599 | ||
| 600 | sdc_conf |= SDC_COM_KEY_COLOR_G; | 600 | sdc_conf |= SDC_COM_KEY_COLOR_G; |
| 601 | } else { | 601 | } else { |
| 602 | sdc_conf &= ~SDC_COM_KEY_COLOR_G; | 602 | sdc_conf &= ~SDC_COM_KEY_COLOR_G; |
| 603 | } | 603 | } |
| 604 | mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF); | 604 | mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF); |
| 605 | 605 | ||
| 606 | spin_unlock_irqrestore(&mx3fb->lock, lock_flags); | 606 | spin_unlock_irqrestore(&mx3fb->lock, lock_flags); |
| 607 | 607 | ||
| 608 | return 0; | 608 | return 0; |
| 609 | } | 609 | } |
| 610 | 610 | ||
| 611 | /** | 611 | /** |
| 612 | * sdc_set_global_alpha() - set global alpha blending modes. | 612 | * sdc_set_global_alpha() - set global alpha blending modes. |
| 613 | * @mx3fb: mx3fb context. | 613 | * @mx3fb: mx3fb context. |
| 614 | * @enable: boolean to enable or disable global alpha blending. If disabled, | 614 | * @enable: boolean to enable or disable global alpha blending. If disabled, |
| 615 | * per pixel blending is used. | 615 | * per pixel blending is used. |
| 616 | * @alpha: global alpha value. | 616 | * @alpha: global alpha value. |
| 617 | * @return: 0 on success or negative error code on failure. | 617 | * @return: 0 on success or negative error code on failure. |
| 618 | */ | 618 | */ |
| 619 | static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t alpha) | 619 | static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t alpha) |
| 620 | { | 620 | { |
| 621 | uint32_t reg; | 621 | uint32_t reg; |
| 622 | unsigned long lock_flags; | 622 | unsigned long lock_flags; |
| 623 | 623 | ||
| 624 | spin_lock_irqsave(&mx3fb->lock, lock_flags); | 624 | spin_lock_irqsave(&mx3fb->lock, lock_flags); |
| 625 | 625 | ||
| 626 | if (enable) { | 626 | if (enable) { |
| 627 | reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL; | 627 | reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL; |
| 628 | mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL); | 628 | mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL); |
| 629 | 629 | ||
| 630 | reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); | 630 | reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); |
| 631 | mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF); | 631 | mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF); |
| 632 | } else { | 632 | } else { |
| 633 | reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); | 633 | reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF); |
| 634 | mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF); | 634 | mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF); |
| 635 | } | 635 | } |
| 636 | 636 | ||
| 637 | spin_unlock_irqrestore(&mx3fb->lock, lock_flags); | 637 | spin_unlock_irqrestore(&mx3fb->lock, lock_flags); |
| 638 | 638 | ||
| 639 | return 0; | 639 | return 0; |
| 640 | } | 640 | } |
| 641 | 641 | ||
| 642 | static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value) | 642 | static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value) |
| 643 | { | 643 | { |
| 644 | /* This might be board-specific */ | 644 | /* This might be board-specific */ |
| 645 | mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL); | 645 | mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL); |
| 646 | return; | 646 | return; |
| 647 | } | 647 | } |
| 648 | 648 | ||
| 649 | static uint32_t bpp_to_pixfmt(int bpp) | 649 | static uint32_t bpp_to_pixfmt(int bpp) |
| 650 | { | 650 | { |
| 651 | uint32_t pixfmt = 0; | 651 | uint32_t pixfmt = 0; |
| 652 | switch (bpp) { | 652 | switch (bpp) { |
| 653 | case 24: | 653 | case 24: |
| 654 | pixfmt = IPU_PIX_FMT_BGR24; | 654 | pixfmt = IPU_PIX_FMT_BGR24; |
| 655 | break; | 655 | break; |
| 656 | case 32: | 656 | case 32: |
| 657 | pixfmt = IPU_PIX_FMT_BGR32; | 657 | pixfmt = IPU_PIX_FMT_BGR32; |
| 658 | break; | 658 | break; |
| 659 | case 16: | 659 | case 16: |
| 660 | pixfmt = IPU_PIX_FMT_RGB565; | 660 | pixfmt = IPU_PIX_FMT_RGB565; |
| 661 | break; | 661 | break; |
| 662 | } | 662 | } |
| 663 | return pixfmt; | 663 | return pixfmt; |
| 664 | } | 664 | } |
| 665 | 665 | ||
| 666 | static int mx3fb_blank(int blank, struct fb_info *fbi); | 666 | static int mx3fb_blank(int blank, struct fb_info *fbi); |
| @@ -669,300 +669,300 @@ static int mx3fb_unmap_video_memory(struct fb_info *fbi); | |||
| 669 | 669 | ||
| 670 | /** | 670 | /** |
| 671 | * mx3fb_set_fix() - set fixed framebuffer parameters from variable settings. | 671 | * mx3fb_set_fix() - set fixed framebuffer parameters from variable settings. |
| 672 | * @info: framebuffer information pointer | 672 | * @info: framebuffer information pointer |
| 673 | * @return: 0 on success or negative error code on failure. | 673 | * @return: 0 on success or negative error code on failure. |
| 674 | */ | 674 | */ |
| 675 | static int mx3fb_set_fix(struct fb_info *fbi) | 675 | static int mx3fb_set_fix(struct fb_info *fbi) |
| 676 | { | 676 | { |
| 677 | struct fb_fix_screeninfo *fix = &fbi->fix; | 677 | struct fb_fix_screeninfo *fix = &fbi->fix; |
| 678 | struct fb_var_screeninfo *var = &fbi->var; | 678 | struct fb_var_screeninfo *var = &fbi->var; |
| 679 | 679 | ||
| 680 | strncpy(fix->id, "DISP3 BG", 8); | 680 | strncpy(fix->id, "DISP3 BG", 8); |
| 681 | 681 | ||
| 682 | fix->line_length = var->xres_virtual * var->bits_per_pixel / 8; | 682 | fix->line_length = var->xres_virtual * var->bits_per_pixel / 8; |
| 683 | 683 | ||
| 684 | fix->type = FB_TYPE_PACKED_PIXELS; | 684 | fix->type = FB_TYPE_PACKED_PIXELS; |
| 685 | fix->accel = FB_ACCEL_NONE; | 685 | fix->accel = FB_ACCEL_NONE; |
| 686 | fix->visual = FB_VISUAL_TRUECOLOR; | 686 | fix->visual = FB_VISUAL_TRUECOLOR; |
| 687 | fix->xpanstep = 1; | 687 | fix->xpanstep = 1; |
| 688 | fix->ypanstep = 1; | 688 | fix->ypanstep = 1; |
| 689 | 689 | ||
| 690 | return 0; | 690 | return 0; |
| 691 | } | 691 | } |
| 692 | 692 | ||
| 693 | static void mx3fb_dma_done(void *arg) | 693 | static void mx3fb_dma_done(void *arg) |
| 694 | { | 694 | { |
| 695 | struct idmac_tx_desc *tx_desc = to_tx_desc(arg); | 695 | struct idmac_tx_desc *tx_desc = to_tx_desc(arg); |
| 696 | struct dma_chan *chan = tx_desc->txd.chan; | 696 | struct dma_chan *chan = tx_desc->txd.chan; |
| 697 | struct idmac_channel *ichannel = to_idmac_chan(chan); | 697 | struct idmac_channel *ichannel = to_idmac_chan(chan); |
| 698 | struct mx3fb_data *mx3fb = ichannel->client; | 698 | struct mx3fb_data *mx3fb = ichannel->client; |
| 699 | struct mx3fb_info *mx3_fbi = mx3fb->fbi->par; | 699 | struct mx3fb_info *mx3_fbi = mx3fb->fbi->par; |
| 700 | 700 | ||
| 701 | dev_dbg(mx3fb->dev, "irq %d callback\n", ichannel->eof_irq); | 701 | dev_dbg(mx3fb->dev, "irq %d callback\n", ichannel->eof_irq); |
| 702 | 702 | ||
| 703 | /* We only need one interrupt, it will be re-enabled as needed */ | 703 | /* We only need one interrupt, it will be re-enabled as needed */ |
| 704 | disable_irq(ichannel->eof_irq); | 704 | disable_irq(ichannel->eof_irq); |
| 705 | 705 | ||
| 706 | complete(&mx3_fbi->flip_cmpl); | 706 | complete(&mx3_fbi->flip_cmpl); |
| 707 | } | 707 | } |
| 708 | 708 | ||
| 709 | /** | 709 | /** |
| 710 | * mx3fb_set_par() - set framebuffer parameters and change the operating mode. | 710 | * mx3fb_set_par() - set framebuffer parameters and change the operating mode. |
| 711 | * @fbi: framebuffer information pointer. | 711 | * @fbi: framebuffer information pointer. |
| 712 | * @return: 0 on success or negative error code on failure. | 712 | * @return: 0 on success or negative error code on failure. |
| 713 | */ | 713 | */ |
| 714 | static int mx3fb_set_par(struct fb_info *fbi) | 714 | static int mx3fb_set_par(struct fb_info *fbi) |
| 715 | { | 715 | { |
| 716 | u32 mem_len; | 716 | u32 mem_len; |
| 717 | struct ipu_di_signal_cfg sig_cfg; | 717 | struct ipu_di_signal_cfg sig_cfg; |
| 718 | enum ipu_panel mode = IPU_PANEL_TFT; | 718 | enum ipu_panel mode = IPU_PANEL_TFT; |
| 719 | struct mx3fb_info *mx3_fbi = fbi->par; | 719 | struct mx3fb_info *mx3_fbi = fbi->par; |
| 720 | struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; | 720 | struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; |
| 721 | struct idmac_channel *ichan = mx3_fbi->idmac_channel; | 721 | struct idmac_channel *ichan = mx3_fbi->idmac_channel; |
| 722 | struct idmac_video_param *video = &ichan->params.video; | 722 | struct idmac_video_param *video = &ichan->params.video; |
| 723 | struct scatterlist *sg = mx3_fbi->sg; | 723 | struct scatterlist *sg = mx3_fbi->sg; |
| 724 | size_t screen_size; | 724 | size_t screen_size; |
| 725 | 725 | ||
| 726 | dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+'); | 726 | dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+'); |
| 727 | 727 | ||
| 728 | mutex_lock(&mx3_fbi->mutex); | 728 | mutex_lock(&mx3_fbi->mutex); |
| 729 | 729 | ||
| 730 | /* Total cleanup */ | 730 | /* Total cleanup */ |
| 731 | if (mx3_fbi->txd) | 731 | if (mx3_fbi->txd) |
| 732 | sdc_disable_channel(mx3_fbi); | 732 | sdc_disable_channel(mx3_fbi); |
| 733 | 733 | ||
| 734 | mx3fb_set_fix(fbi); | 734 | mx3fb_set_fix(fbi); |
| 735 | 735 | ||
| 736 | mem_len = fbi->var.yres_virtual * fbi->fix.line_length; | 736 | mem_len = fbi->var.yres_virtual * fbi->fix.line_length; |
| 737 | if (mem_len > fbi->fix.smem_len) { | 737 | if (mem_len > fbi->fix.smem_len) { |
| 738 | if (fbi->fix.smem_start) | 738 | if (fbi->fix.smem_start) |
| 739 | mx3fb_unmap_video_memory(fbi); | 739 | mx3fb_unmap_video_memory(fbi); |
| 740 | 740 | ||
| 741 | fbi->fix.smem_len = mem_len; | 741 | fbi->fix.smem_len = mem_len; |
| 742 | if (mx3fb_map_video_memory(fbi) < 0) { | 742 | if (mx3fb_map_video_memory(fbi) < 0) { |
| 743 | mutex_unlock(&mx3_fbi->mutex); | 743 | mutex_unlock(&mx3_fbi->mutex); |
| 744 | return -ENOMEM; | 744 | return -ENOMEM; |
| 745 | } | 745 | } |
| 746 | } | 746 | } |
| 747 | 747 | ||
| 748 | screen_size = fbi->fix.line_length * fbi->var.yres; | 748 | screen_size = fbi->fix.line_length * fbi->var.yres; |
| 749 | 749 | ||
| 750 | sg_init_table(&sg[0], 1); | 750 | sg_init_table(&sg[0], 1); |
| 751 | sg_init_table(&sg[1], 1); | 751 | sg_init_table(&sg[1], 1); |
| 752 | 752 | ||
| 753 | sg_dma_address(&sg[0]) = fbi->fix.smem_start; | 753 | sg_dma_address(&sg[0]) = fbi->fix.smem_start; |
| 754 | sg_set_page(&sg[0], virt_to_page(fbi->screen_base), | 754 | sg_set_page(&sg[0], virt_to_page(fbi->screen_base), |
| 755 | fbi->fix.smem_len, | 755 | fbi->fix.smem_len, |
| 756 | offset_in_page(fbi->screen_base)); | 756 | offset_in_page(fbi->screen_base)); |
| 757 | 757 | ||
| 758 | if (mx3_fbi->ipu_ch == IDMAC_SDC_0) { | 758 | if (mx3_fbi->ipu_ch == IDMAC_SDC_0) { |
| 759 | memset(&sig_cfg, 0, sizeof(sig_cfg)); | 759 | memset(&sig_cfg, 0, sizeof(sig_cfg)); |
| 760 | if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT) | 760 | if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT) |
| 761 | sig_cfg.Hsync_pol = true; | 761 | sig_cfg.Hsync_pol = true; |
| 762 | if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT) | 762 | if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT) |
| 763 | sig_cfg.Vsync_pol = true; | 763 | sig_cfg.Vsync_pol = true; |
| 764 | if (fbi->var.sync & FB_SYNC_CLK_INVERT) | 764 | if (fbi->var.sync & FB_SYNC_CLK_INVERT) |
| 765 | sig_cfg.clk_pol = true; | 765 | sig_cfg.clk_pol = true; |
| 766 | if (fbi->var.sync & FB_SYNC_DATA_INVERT) | 766 | if (fbi->var.sync & FB_SYNC_DATA_INVERT) |
| 767 | sig_cfg.data_pol = true; | 767 | sig_cfg.data_pol = true; |
| 768 | if (fbi->var.sync & FB_SYNC_OE_ACT_HIGH) | 768 | if (fbi->var.sync & FB_SYNC_OE_ACT_HIGH) |
| 769 | sig_cfg.enable_pol = true; | 769 | sig_cfg.enable_pol = true; |
| 770 | if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN) | 770 | if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN) |
| 771 | sig_cfg.clkidle_en = true; | 771 | sig_cfg.clkidle_en = true; |
| 772 | if (fbi->var.sync & FB_SYNC_CLK_SEL_EN) | 772 | if (fbi->var.sync & FB_SYNC_CLK_SEL_EN) |
| 773 | sig_cfg.clksel_en = true; | 773 | sig_cfg.clksel_en = true; |
| 774 | if (fbi->var.sync & FB_SYNC_SHARP_MODE) | 774 | if (fbi->var.sync & FB_SYNC_SHARP_MODE) |
| 775 | mode = IPU_PANEL_SHARP_TFT; | 775 | mode = IPU_PANEL_SHARP_TFT; |
| 776 | 776 | ||
| 777 | dev_dbg(fbi->device, "pixclock = %ul Hz\n", | 777 | dev_dbg(fbi->device, "pixclock = %ul Hz\n", |
| 778 | (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL)); | 778 | (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL)); |
| 779 | 779 | ||
| 780 | if (sdc_init_panel(mx3fb, mode, | 780 | if (sdc_init_panel(mx3fb, mode, |
| 781 | (PICOS2KHZ(fbi->var.pixclock)) * 1000UL, | 781 | (PICOS2KHZ(fbi->var.pixclock)) * 1000UL, |
| 782 | fbi->var.xres, fbi->var.yres, | 782 | fbi->var.xres, fbi->var.yres, |
| 783 | (fbi->var.sync & FB_SYNC_SWAP_RGB) ? | 783 | (fbi->var.sync & FB_SYNC_SWAP_RGB) ? |
| 784 | IPU_PIX_FMT_BGR666 : IPU_PIX_FMT_RGB666, | 784 | IPU_PIX_FMT_BGR666 : IPU_PIX_FMT_RGB666, |
| 785 | fbi->var.left_margin, | 785 | fbi->var.left_margin, |
| 786 | fbi->var.hsync_len, | 786 | fbi->var.hsync_len, |
| 787 | fbi->var.right_margin + | 787 | fbi->var.right_margin + |
| 788 | fbi->var.hsync_len, | 788 | fbi->var.hsync_len, |
| 789 | fbi->var.upper_margin, | 789 | fbi->var.upper_margin, |
| 790 | fbi->var.vsync_len, | 790 | fbi->var.vsync_len, |
| 791 | fbi->var.lower_margin + | 791 | fbi->var.lower_margin + |
| 792 | fbi->var.vsync_len, sig_cfg) != 0) { | 792 | fbi->var.vsync_len, sig_cfg) != 0) { |
| 793 | mutex_unlock(&mx3_fbi->mutex); | 793 | mutex_unlock(&mx3_fbi->mutex); |
| 794 | dev_err(fbi->device, | 794 | dev_err(fbi->device, |
| 795 | "mx3fb: Error initializing panel.\n"); | 795 | "mx3fb: Error initializing panel.\n"); |
| 796 | return -EINVAL; | 796 | return -EINVAL; |
| 797 | } | 797 | } |
| 798 | } | 798 | } |
| 799 | 799 | ||
| 800 | sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0); | 800 | sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0); |
| 801 | 801 | ||
| 802 | mx3_fbi->cur_ipu_buf = 0; | 802 | mx3_fbi->cur_ipu_buf = 0; |
| 803 | 803 | ||
| 804 | video->out_pixel_fmt = bpp_to_pixfmt(fbi->var.bits_per_pixel); | 804 | video->out_pixel_fmt = bpp_to_pixfmt(fbi->var.bits_per_pixel); |
| 805 | video->out_width = fbi->var.xres; | 805 | video->out_width = fbi->var.xres; |
| 806 | video->out_height = fbi->var.yres; | 806 | video->out_height = fbi->var.yres; |
| 807 | video->out_stride = fbi->var.xres_virtual; | 807 | video->out_stride = fbi->var.xres_virtual; |
| 808 | 808 | ||
| 809 | if (mx3_fbi->blank == FB_BLANK_UNBLANK) | 809 | if (mx3_fbi->blank == FB_BLANK_UNBLANK) |
| 810 | sdc_enable_channel(mx3_fbi); | 810 | sdc_enable_channel(mx3_fbi); |
| 811 | 811 | ||
| 812 | mutex_unlock(&mx3_fbi->mutex); | 812 | mutex_unlock(&mx3_fbi->mutex); |
| 813 | 813 | ||
| 814 | return 0; | 814 | return 0; |
| 815 | } | 815 | } |
| 816 | 816 | ||
| 817 | /** | 817 | /** |
| 818 | * mx3fb_check_var() - check and adjust framebuffer variable parameters. | 818 | * mx3fb_check_var() - check and adjust framebuffer variable parameters. |
| 819 | * @var: framebuffer variable parameters | 819 | * @var: framebuffer variable parameters |
| 820 | * @fbi: framebuffer information pointer | 820 | * @fbi: framebuffer information pointer |
| 821 | */ | 821 | */ |
| 822 | static int mx3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi) | 822 | static int mx3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi) |
| 823 | { | 823 | { |
| 824 | struct mx3fb_info *mx3_fbi = fbi->par; | 824 | struct mx3fb_info *mx3_fbi = fbi->par; |
| 825 | u32 vtotal; | 825 | u32 vtotal; |
| 826 | u32 htotal; | 826 | u32 htotal; |
| 827 | 827 | ||
| 828 | dev_dbg(fbi->device, "%s\n", __func__); | 828 | dev_dbg(fbi->device, "%s\n", __func__); |
| 829 | 829 | ||
| 830 | if (var->xres_virtual < var->xres) | 830 | if (var->xres_virtual < var->xres) |
| 831 | var->xres_virtual = var->xres; | 831 | var->xres_virtual = var->xres; |
| 832 | if (var->yres_virtual < var->yres) | 832 | if (var->yres_virtual < var->yres) |
| 833 | var->yres_virtual = var->yres; | 833 | var->yres_virtual = var->yres; |
| 834 | 834 | ||
| 835 | if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) && | 835 | if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) && |
| 836 | (var->bits_per_pixel != 16)) | 836 | (var->bits_per_pixel != 16)) |
| 837 | var->bits_per_pixel = default_bpp; | 837 | var->bits_per_pixel = default_bpp; |
| 838 | 838 | ||
| 839 | switch (var->bits_per_pixel) { | 839 | switch (var->bits_per_pixel) { |
| 840 | case 16: | 840 | case 16: |
| 841 | var->red.length = 5; | 841 | var->red.length = 5; |
| 842 | var->red.offset = 11; | 842 | var->red.offset = 11; |
| 843 | var->red.msb_right = 0; | 843 | var->red.msb_right = 0; |
| 844 | 844 | ||
| 845 | var->green.length = 6; | 845 | var->green.length = 6; |
| 846 | var->green.offset = 5; | 846 | var->green.offset = 5; |
| 847 | var->green.msb_right = 0; | 847 | var->green.msb_right = 0; |
| 848 | 848 | ||
| 849 | var->blue.length = 5; | 849 | var->blue.length = 5; |
| 850 | var->blue.offset = 0; | 850 | var->blue.offset = 0; |
| 851 | var->blue.msb_right = 0; | 851 | var->blue.msb_right = 0; |
| 852 | 852 | ||
| 853 | var->transp.length = 0; | 853 | var->transp.length = 0; |
| 854 | var->transp.offset = 0; | 854 | var->transp.offset = 0; |
| 855 | var->transp.msb_right = 0; | 855 | var->transp.msb_right = 0; |
| 856 | break; | 856 | break; |
| 857 | case 24: | 857 | case 24: |
| 858 | var->red.length = 8; | 858 | var->red.length = 8; |
| 859 | var->red.offset = 16; | 859 | var->red.offset = 16; |
| 860 | var->red.msb_right = 0; | 860 | var->red.msb_right = 0; |
| 861 | 861 | ||
| 862 | var->green.length = 8; | 862 | var->green.length = 8; |
| 863 | var->green.offset = 8; | 863 | var->green.offset = 8; |
| 864 | var->green.msb_right = 0; | 864 | var->green.msb_right = 0; |
| 865 | 865 | ||
| 866 | var->blue.length = 8; | 866 | var->blue.length = 8; |
| 867 | var->blue.offset = 0; | 867 | var->blue.offset = 0; |
| 868 | var->blue.msb_right = 0; | 868 | var->blue.msb_right = 0; |
| 869 | 869 | ||
| 870 | var->transp.length = 0; | 870 | var->transp.length = 0; |
| 871 | var->transp.offset = 0; | 871 | var->transp.offset = 0; |
| 872 | var->transp.msb_right = 0; | 872 | var->transp.msb_right = 0; |
| 873 | break; | 873 | break; |
| 874 | case 32: | 874 | case 32: |
| 875 | var->red.length = 8; | 875 | var->red.length = 8; |
| 876 | var->red.offset = 16; | 876 | var->red.offset = 16; |
| 877 | var->red.msb_right = 0; | 877 | var->red.msb_right = 0; |
| 878 | 878 | ||
| 879 | var->green.length = 8; | 879 | var->green.length = 8; |
| 880 | var->green.offset = 8; | 880 | var->green.offset = 8; |
| 881 | var->green.msb_right = 0; | 881 | var->green.msb_right = 0; |
| 882 | 882 | ||
| 883 | var->blue.length = 8; | 883 | var->blue.length = 8; |
| 884 | var->blue.offset = 0; | 884 | var->blue.offset = 0; |
| 885 | var->blue.msb_right = 0; | 885 | var->blue.msb_right = 0; |
| 886 | 886 | ||
| 887 | var->transp.length = 8; | 887 | var->transp.length = 8; |
| 888 | var->transp.offset = 24; | 888 | var->transp.offset = 24; |
| 889 | var->transp.msb_right = 0; | 889 | var->transp.msb_right = 0; |
| 890 | break; | 890 | break; |
| 891 | } | 891 | } |
| 892 | 892 | ||
| 893 | if (var->pixclock < 1000) { | 893 | if (var->pixclock < 1000) { |
| 894 | htotal = var->xres + var->right_margin + var->hsync_len + | 894 | htotal = var->xres + var->right_margin + var->hsync_len + |
| 895 | var->left_margin; | 895 | var->left_margin; |
| 896 | vtotal = var->yres + var->lower_margin + var->vsync_len + | 896 | vtotal = var->yres + var->lower_margin + var->vsync_len + |
| 897 | var->upper_margin; | 897 | var->upper_margin; |
| 898 | var->pixclock = (vtotal * htotal * 6UL) / 100UL; | 898 | var->pixclock = (vtotal * htotal * 6UL) / 100UL; |
| 899 | var->pixclock = KHZ2PICOS(var->pixclock); | 899 | var->pixclock = KHZ2PICOS(var->pixclock); |
| 900 | dev_dbg(fbi->device, "pixclock set for 60Hz refresh = %u ps\n", | 900 | dev_dbg(fbi->device, "pixclock set for 60Hz refresh = %u ps\n", |
| 901 | var->pixclock); | 901 | var->pixclock); |
| 902 | } | 902 | } |
| 903 | 903 | ||
| 904 | var->height = -1; | 904 | var->height = -1; |
| 905 | var->width = -1; | 905 | var->width = -1; |
| 906 | var->grayscale = 0; | 906 | var->grayscale = 0; |
| 907 | 907 | ||
| 908 | /* Preserve sync flags */ | 908 | /* Preserve sync flags */ |
| 909 | var->sync |= mx3_fbi->sync; | 909 | var->sync |= mx3_fbi->sync; |
| 910 | mx3_fbi->sync |= var->sync; | 910 | mx3_fbi->sync |= var->sync; |
| 911 | 911 | ||
| 912 | return 0; | 912 | return 0; |
| 913 | } | 913 | } |
| 914 | 914 | ||
| 915 | static u32 chan_to_field(unsigned int chan, struct fb_bitfield *bf) | 915 | static u32 chan_to_field(unsigned int chan, struct fb_bitfield *bf) |
| 916 | { | 916 | { |
| 917 | chan &= 0xffff; | 917 | chan &= 0xffff; |
| 918 | chan >>= 16 - bf->length; | 918 | chan >>= 16 - bf->length; |
| 919 | return chan << bf->offset; | 919 | return chan << bf->offset; |
| 920 | } | 920 | } |
| 921 | 921 | ||
| 922 | static int mx3fb_setcolreg(unsigned int regno, unsigned int red, | 922 | static int mx3fb_setcolreg(unsigned int regno, unsigned int red, |
| 923 | unsigned int green, unsigned int blue, | 923 | unsigned int green, unsigned int blue, |
| 924 | unsigned int trans, struct fb_info *fbi) | 924 | unsigned int trans, struct fb_info *fbi) |
| 925 | { | 925 | { |
| 926 | struct mx3fb_info *mx3_fbi = fbi->par; | 926 | struct mx3fb_info *mx3_fbi = fbi->par; |
| 927 | u32 val; | 927 | u32 val; |
| 928 | int ret = 1; | 928 | int ret = 1; |
| 929 | 929 | ||
| 930 | dev_dbg(fbi->device, "%s\n", __func__); | 930 | dev_dbg(fbi->device, "%s\n", __func__); |
| 931 | 931 | ||
| 932 | mutex_lock(&mx3_fbi->mutex); | 932 | mutex_lock(&mx3_fbi->mutex); |
| 933 | /* | 933 | /* |
| 934 | * If greyscale is true, then we convert the RGB value | 934 | * If greyscale is true, then we convert the RGB value |
| 935 | * to greyscale no matter what visual we are using. | 935 | * to greyscale no matter what visual we are using. |
| 936 | */ | 936 | */ |
| 937 | if (fbi->var.grayscale) | 937 | if (fbi->var.grayscale) |
| 938 | red = green = blue = (19595 * red + 38470 * green + | 938 | red = green = blue = (19595 * red + 38470 * green + |
| 939 | 7471 * blue) >> 16; | 939 | 7471 * blue) >> 16; |
| 940 | switch (fbi->fix.visual) { | 940 | switch (fbi->fix.visual) { |
| 941 | case FB_VISUAL_TRUECOLOR: | 941 | case FB_VISUAL_TRUECOLOR: |
| 942 | /* | 942 | /* |
| 943 | * 16-bit True Colour. We encode the RGB value | 943 | * 16-bit True Colour. We encode the RGB value |
| 944 | * according to the RGB bitfield information. | 944 | * according to the RGB bitfield information. |
| 945 | */ | 945 | */ |
| 946 | if (regno < 16) { | 946 | if (regno < 16) { |
| 947 | u32 *pal = fbi->pseudo_palette; | 947 | u32 *pal = fbi->pseudo_palette; |
| 948 | 948 | ||
| 949 | val = chan_to_field(red, &fbi->var.red); | 949 | val = chan_to_field(red, &fbi->var.red); |
| 950 | val |= chan_to_field(green, &fbi->var.green); | 950 | val |= chan_to_field(green, &fbi->var.green); |
| 951 | val |= chan_to_field(blue, &fbi->var.blue); | 951 | val |= chan_to_field(blue, &fbi->var.blue); |
| 952 | 952 | ||
| 953 | pal[regno] = val; | 953 | pal[regno] = val; |
| 954 | 954 | ||
| 955 | ret = 0; | 955 | ret = 0; |
| 956 | } | 956 | } |
| 957 | break; | 957 | break; |
| 958 | 958 | ||
| 959 | case FB_VISUAL_STATIC_PSEUDOCOLOR: | 959 | case FB_VISUAL_STATIC_PSEUDOCOLOR: |
| 960 | case FB_VISUAL_PSEUDOCOLOR: | 960 | case FB_VISUAL_PSEUDOCOLOR: |
| 961 | break; | 961 | break; |
| 962 | } | 962 | } |
| 963 | mutex_unlock(&mx3_fbi->mutex); | 963 | mutex_unlock(&mx3_fbi->mutex); |
| 964 | 964 | ||
| 965 | return ret; | 965 | return ret; |
| 966 | } | 966 | } |
| 967 | 967 | ||
| 968 | /** | 968 | /** |
| @@ -970,152 +970,152 @@ static int mx3fb_setcolreg(unsigned int regno, unsigned int red, | |||
| 970 | */ | 970 | */ |
| 971 | static int mx3fb_blank(int blank, struct fb_info *fbi) | 971 | static int mx3fb_blank(int blank, struct fb_info *fbi) |
| 972 | { | 972 | { |
| 973 | struct mx3fb_info *mx3_fbi = fbi->par; | 973 | struct mx3fb_info *mx3_fbi = fbi->par; |
| 974 | struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; | 974 | struct mx3fb_data *mx3fb = mx3_fbi->mx3fb; |
| 975 | 975 | ||
| 976 | dev_dbg(fbi->device, "%s\n", __func__); | 976 | dev_dbg(fbi->device, "%s\n", __func__); |
| 977 | 977 | ||
| 978 | dev_dbg(fbi->device, "blank = %d\n", blank); | 978 | dev_dbg(fbi->device, "blank = %d\n", blank); |
| 979 | 979 | ||
| 980 | if (mx3_fbi->blank == blank) | 980 | if (mx3_fbi->blank == blank) |
| 981 | return 0; | 981 | return 0; |
| 982 | 982 | ||
| 983 | mutex_lock(&mx3_fbi->mutex); | 983 | mutex_lock(&mx3_fbi->mutex); |
| 984 | mx3_fbi->blank = blank; | 984 | mx3_fbi->blank = blank; |
| 985 | 985 | ||
| 986 | switch (blank) { | 986 | switch (blank) { |
| 987 | case FB_BLANK_POWERDOWN: | 987 | case FB_BLANK_POWERDOWN: |
| 988 | case FB_BLANK_VSYNC_SUSPEND: | 988 | case FB_BLANK_VSYNC_SUSPEND: |
| 989 | case FB_BLANK_HSYNC_SUSPEND: | 989 | case FB_BLANK_HSYNC_SUSPEND: |
| 990 | case FB_BLANK_NORMAL: | 990 | case FB_BLANK_NORMAL: |
| 991 | sdc_disable_channel(mx3_fbi); | 991 | sdc_disable_channel(mx3_fbi); |
| 992 | sdc_set_brightness(mx3fb, 0); | 992 | sdc_set_brightness(mx3fb, 0); |
| 993 | break; | 993 | break; |
| 994 | case FB_BLANK_UNBLANK: | 994 | case FB_BLANK_UNBLANK: |
| 995 | sdc_enable_channel(mx3_fbi); | 995 | sdc_enable_channel(mx3_fbi); |
| 996 | sdc_set_brightness(mx3fb, mx3fb->backlight_level); | 996 | sdc_set_brightness(mx3fb, mx3fb->backlight_level); |
| 997 | break; | 997 | break; |
| 998 | } | 998 | } |
| 999 | mutex_unlock(&mx3_fbi->mutex); | 999 | mutex_unlock(&mx3_fbi->mutex); |
| 1000 | 1000 | ||
| 1001 | return 0; | 1001 | return 0; |
| 1002 | } | 1002 | } |
| 1003 | 1003 | ||
| 1004 | /** | 1004 | /** |
| 1005 | * mx3fb_pan_display() - pan or wrap the display | 1005 | * mx3fb_pan_display() - pan or wrap the display |
| 1006 | * @var: variable screen buffer information. | 1006 | * @var: variable screen buffer information. |
| 1007 | * @info: framebuffer information pointer. | 1007 | * @info: framebuffer information pointer. |
| 1008 | * | 1008 | * |
| 1009 | * We look only at xoffset, yoffset and the FB_VMODE_YWRAP flag | 1009 | * We look only at xoffset, yoffset and the FB_VMODE_YWRAP flag |
| 1010 | */ | 1010 | */ |
| 1011 | static int mx3fb_pan_display(struct fb_var_screeninfo *var, | 1011 | static int mx3fb_pan_display(struct fb_var_screeninfo *var, |
| 1012 | struct fb_info *fbi) | 1012 | struct fb_info *fbi) |
| 1013 | { | 1013 | { |
| 1014 | struct mx3fb_info *mx3_fbi = fbi->par; | 1014 | struct mx3fb_info *mx3_fbi = fbi->par; |
| 1015 | u32 y_bottom; | 1015 | u32 y_bottom; |
| 1016 | unsigned long base; | 1016 | unsigned long base; |
| 1017 | off_t offset; | 1017 | off_t offset; |
| 1018 | dma_cookie_t cookie; | 1018 | dma_cookie_t cookie; |
| 1019 | struct scatterlist *sg = mx3_fbi->sg; | 1019 | struct scatterlist *sg = mx3_fbi->sg; |
| 1020 | struct dma_chan *dma_chan = &mx3_fbi->idmac_channel->dma_chan; | 1020 | struct dma_chan *dma_chan = &mx3_fbi->idmac_channel->dma_chan; |
| 1021 | struct dma_async_tx_descriptor *txd; | 1021 | struct dma_async_tx_descriptor *txd; |
| 1022 | int ret; | 1022 | int ret; |
| 1023 | 1023 | ||
| 1024 | dev_dbg(fbi->device, "%s [%c]\n", __func__, | 1024 | dev_dbg(fbi->device, "%s [%c]\n", __func__, |
| 1025 | list_empty(&mx3_fbi->idmac_channel->queue) ? '-' : '+'); | 1025 | list_empty(&mx3_fbi->idmac_channel->queue) ? '-' : '+'); |
| 1026 | 1026 | ||
| 1027 | if (var->xoffset > 0) { | 1027 | if (var->xoffset > 0) { |
| 1028 | dev_dbg(fbi->device, "x panning not supported\n"); | 1028 | dev_dbg(fbi->device, "x panning not supported\n"); |
| 1029 | return -EINVAL; | 1029 | return -EINVAL; |
| 1030 | } | 1030 | } |
| 1031 | 1031 | ||
| 1032 | if (fbi->var.xoffset == var->xoffset && | 1032 | if (fbi->var.xoffset == var->xoffset && |
| 1033 | fbi->var.yoffset == var->yoffset) | 1033 | fbi->var.yoffset == var->yoffset) |
| 1034 | return 0; /* No change, do nothing */ | 1034 | return 0; /* No change, do nothing */ |
| 1035 | 1035 | ||
| 1036 | y_bottom = var->yoffset; | 1036 | y_bottom = var->yoffset; |
| 1037 | 1037 | ||
| 1038 | if (!(var->vmode & FB_VMODE_YWRAP)) | 1038 | if (!(var->vmode & FB_VMODE_YWRAP)) |
| 1039 | y_bottom += var->yres; | 1039 | y_bottom += var->yres; |
| 1040 | 1040 | ||
| 1041 | if (y_bottom > fbi->var.yres_virtual) | 1041 | if (y_bottom > fbi->var.yres_virtual) |
| 1042 | return -EINVAL; | 1042 | return -EINVAL; |
| 1043 | 1043 | ||
| 1044 | mutex_lock(&mx3_fbi->mutex); | 1044 | mutex_lock(&mx3_fbi->mutex); |
| 1045 | 1045 | ||
| 1046 | offset = (var->yoffset * var->xres_virtual + var->xoffset) * | 1046 | offset = (var->yoffset * var->xres_virtual + var->xoffset) * |
| 1047 | (var->bits_per_pixel / 8); | 1047 | (var->bits_per_pixel / 8); |
| 1048 | base = fbi->fix.smem_start + offset; | 1048 | base = fbi->fix.smem_start + offset; |
| 1049 | 1049 | ||
| 1050 | dev_dbg(fbi->device, "Updating SDC BG buf %d address=0x%08lX\n", | 1050 | dev_dbg(fbi->device, "Updating SDC BG buf %d address=0x%08lX\n", |
| 1051 | mx3_fbi->cur_ipu_buf, base); | 1051 | mx3_fbi->cur_ipu_buf, base); |
| 1052 | 1052 | ||
| 1053 | /* | 1053 | /* |
| 1054 | * We enable the End of Frame interrupt, which will free a tx-descriptor, | 1054 | * We enable the End of Frame interrupt, which will free a tx-descriptor, |
| 1055 | * which we will need for the next device_prep_slave_sg(). The | 1055 | * which we will need for the next device_prep_slave_sg(). The |
| 1056 | * IRQ-handler will disable the IRQ again. | 1056 | * IRQ-handler will disable the IRQ again. |
| 1057 | */ | 1057 | */ |
| 1058 | init_completion(&mx3_fbi->flip_cmpl); | 1058 | init_completion(&mx3_fbi->flip_cmpl); |
| 1059 | enable_irq(mx3_fbi->idmac_channel->eof_irq); | 1059 | enable_irq(mx3_fbi->idmac_channel->eof_irq); |
| 1060 | 1060 | ||
| 1061 | ret = wait_for_completion_timeout(&mx3_fbi->flip_cmpl, HZ / 10); | 1061 | ret = wait_for_completion_timeout(&mx3_fbi->flip_cmpl, HZ / 10); |
| 1062 | if (ret <= 0) { | 1062 | if (ret <= 0) { |
| 1063 | mutex_unlock(&mx3_fbi->mutex); | 1063 | mutex_unlock(&mx3_fbi->mutex); |
| 1064 | dev_info(fbi->device, "Panning failed due to %s\n", ret < 0 ? | 1064 | dev_info(fbi->device, "Panning failed due to %s\n", ret < 0 ? |
| 1065 | "user interrupt" : "timeout"); | 1065 | "user interrupt" : "timeout"); |
| 1066 | return ret ? : -ETIMEDOUT; | 1066 | return ret ? : -ETIMEDOUT; |
| 1067 | } | 1067 | } |
| 1068 | 1068 | ||
| 1069 | mx3_fbi->cur_ipu_buf = !mx3_fbi->cur_ipu_buf; | 1069 | mx3_fbi->cur_ipu_buf = !mx3_fbi->cur_ipu_buf; |
| 1070 | 1070 | ||
| 1071 | sg_dma_address(&sg[mx3_fbi->cur_ipu_buf]) = base; | 1071 | sg_dma_address(&sg[mx3_fbi->cur_ipu_buf]) = base; |
| 1072 | sg_set_page(&sg[mx3_fbi->cur_ipu_buf], | 1072 | sg_set_page(&sg[mx3_fbi->cur_ipu_buf], |
| 1073 | virt_to_page(fbi->screen_base + offset), fbi->fix.smem_len, | 1073 | virt_to_page(fbi->screen_base + offset), fbi->fix.smem_len, |
| 1074 | offset_in_page(fbi->screen_base + offset)); | 1074 | offset_in_page(fbi->screen_base + offset)); |
| 1075 | 1075 | ||
| 1076 | txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg + | 1076 | txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg + |
| 1077 | mx3_fbi->cur_ipu_buf, 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT); | 1077 | mx3_fbi->cur_ipu_buf, 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT); |
| 1078 | if (!txd) { | 1078 | if (!txd) { |
| 1079 | dev_err(fbi->device, | 1079 | dev_err(fbi->device, |
| 1080 | "Error preparing a DMA transaction descriptor.\n"); | 1080 | "Error preparing a DMA transaction descriptor.\n"); |
| 1081 | mutex_unlock(&mx3_fbi->mutex); | 1081 | mutex_unlock(&mx3_fbi->mutex); |
| 1082 | return -EIO; | 1082 | return -EIO; |
| 1083 | } | 1083 | } |
| 1084 | 1084 | ||
| 1085 | txd->callback_param = txd; | 1085 | txd->callback_param = txd; |
| 1086 | txd->callback = mx3fb_dma_done; | 1086 | txd->callback = mx3fb_dma_done; |
| 1087 | 1087 | ||
| 1088 | /* | 1088 | /* |
| 1089 | * Emulate original mx3fb behaviour: each new call to idmac_tx_submit() | 1089 | * Emulate original mx3fb behaviour: each new call to idmac_tx_submit() |
| 1090 | * should switch to another buffer | 1090 | * should switch to another buffer |
| 1091 | */ | 1091 | */ |
| 1092 | cookie = txd->tx_submit(txd); | 1092 | cookie = txd->tx_submit(txd); |
| 1093 | dev_dbg(fbi->device, "%d: Submit %p #%d\n", __LINE__, txd, cookie); | 1093 | dev_dbg(fbi->device, "%d: Submit %p #%d\n", __LINE__, txd, cookie); |
| 1094 | if (cookie < 0) { | 1094 | if (cookie < 0) { |
| 1095 | dev_err(fbi->device, | 1095 | dev_err(fbi->device, |
| 1096 | "Error updating SDC buf %d to address=0x%08lX\n", | 1096 | "Error updating SDC buf %d to address=0x%08lX\n", |
| 1097 | mx3_fbi->cur_ipu_buf, base); | 1097 | mx3_fbi->cur_ipu_buf, base); |
| 1098 | mutex_unlock(&mx3_fbi->mutex); | 1098 | mutex_unlock(&mx3_fbi->mutex); |
| 1099 | return -EIO; | 1099 | return -EIO; |
| 1100 | } | 1100 | } |
| 1101 | 1101 | ||
| 1102 | if (mx3_fbi->txd) | 1102 | if (mx3_fbi->txd) |
| 1103 | async_tx_ack(mx3_fbi->txd); | 1103 | async_tx_ack(mx3_fbi->txd); |
| 1104 | mx3_fbi->txd = txd; | 1104 | mx3_fbi->txd = txd; |
| 1105 | 1105 | ||
| 1106 | fbi->var.xoffset = var->xoffset; | 1106 | fbi->var.xoffset = var->xoffset; |
| 1107 | fbi->var.yoffset = var->yoffset; | 1107 | fbi->var.yoffset = var->yoffset; |
| 1108 | 1108 | ||
| 1109 | if (var->vmode & FB_VMODE_YWRAP) | 1109 | if (var->vmode & FB_VMODE_YWRAP) |
| 1110 | fbi->var.vmode |= FB_VMODE_YWRAP; | 1110 | fbi->var.vmode |= FB_VMODE_YWRAP; |
| 1111 | else | 1111 | else |
| 1112 | fbi->var.vmode &= ~FB_VMODE_YWRAP; | 1112 | fbi->var.vmode &= ~FB_VMODE_YWRAP; |
| 1113 | 1113 | ||
| 1114 | mutex_unlock(&mx3_fbi->mutex); | 1114 | mutex_unlock(&mx3_fbi->mutex); |
| 1115 | 1115 | ||
| 1116 | dev_dbg(fbi->device, "Update complete\n"); | 1116 | dev_dbg(fbi->device, "Update complete\n"); |
| 1117 | 1117 | ||
| 1118 | return 0; | 1118 | return 0; |
| 1119 | } | 1119 | } |
| 1120 | 1120 | ||
| 1121 | /* | 1121 | /* |
| @@ -1124,15 +1124,15 @@ static int mx3fb_pan_display(struct fb_var_screeninfo *var, | |||
| 1124 | * blitting, rectangle filling, copy regions and cursor definition. | 1124 | * blitting, rectangle filling, copy regions and cursor definition. |
| 1125 | */ | 1125 | */ |
| 1126 | static struct fb_ops mx3fb_ops = { | 1126 | static struct fb_ops mx3fb_ops = { |
| 1127 | .owner = THIS_MODULE, | 1127 | .owner = THIS_MODULE, |
| 1128 | .fb_set_par = mx3fb_set_par, | 1128 | .fb_set_par = mx3fb_set_par, |
| 1129 | .fb_check_var = mx3fb_check_var, | 1129 | .fb_check_var = mx3fb_check_var, |
| 1130 | .fb_setcolreg = mx3fb_setcolreg, | 1130 | .fb_setcolreg = mx3fb_setcolreg, |
| 1131 | .fb_pan_display = mx3fb_pan_display, | 1131 | .fb_pan_display = mx3fb_pan_display, |
| 1132 | .fb_fillrect = cfb_fillrect, | 1132 | .fb_fillrect = cfb_fillrect, |
| 1133 | .fb_copyarea = cfb_copyarea, | 1133 | .fb_copyarea = cfb_copyarea, |
| 1134 | .fb_imageblit = cfb_imageblit, | 1134 | .fb_imageblit = cfb_imageblit, |
| 1135 | .fb_blank = mx3fb_blank, | 1135 | .fb_blank = mx3fb_blank, |
| 1136 | }; | 1136 | }; |
| 1137 | 1137 | ||
| 1138 | #ifdef CONFIG_PM | 1138 | #ifdef CONFIG_PM |
| @@ -1146,19 +1146,19 @@ static struct fb_ops mx3fb_ops = { | |||
| 1146 | */ | 1146 | */ |
| 1147 | static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state) | 1147 | static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state) |
| 1148 | { | 1148 | { |
| 1149 | struct mx3fb_data *drv_data = platform_get_drvdata(pdev); | 1149 | struct mx3fb_data *drv_data = platform_get_drvdata(pdev); |
| 1150 | struct mx3fb_info *mx3_fbi = drv_data->fbi->par; | 1150 | struct mx3fb_info *mx3_fbi = drv_data->fbi->par; |
| 1151 | 1151 | ||
| 1152 | acquire_console_sem(); | 1152 | acquire_console_sem(); |
| 1153 | fb_set_suspend(drv_data->fbi, 1); | 1153 | fb_set_suspend(drv_data->fbi, 1); |
| 1154 | release_console_sem(); | 1154 | release_console_sem(); |
| 1155 | 1155 | ||
| 1156 | if (mx3_fbi->blank == FB_BLANK_UNBLANK) { | 1156 | if (mx3_fbi->blank == FB_BLANK_UNBLANK) { |
| 1157 | sdc_disable_channel(mx3_fbi); | 1157 | sdc_disable_channel(mx3_fbi); |
| 1158 | sdc_set_brightness(mx3fb, 0); | 1158 | sdc_set_brightness(mx3fb, 0); |
| 1159 | 1159 | ||
| 1160 | } | 1160 | } |
| 1161 | return 0; | 1161 | return 0; |
| 1162 | } | 1162 | } |
| 1163 | 1163 | ||
| 1164 | /* | 1164 | /* |
| @@ -1166,19 +1166,19 @@ static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state) | |||
| 1166 | */ | 1166 | */ |
| 1167 | static int mx3fb_resume(struct platform_device *pdev) | 1167 | static int mx3fb_resume(struct platform_device *pdev) |
| 1168 | { | 1168 | { |
| 1169 | struct mx3fb_data *drv_data = platform_get_drvdata(pdev); | 1169 | struct mx3fb_data *drv_data = platform_get_drvdata(pdev); |
| 1170 | struct mx3fb_info *mx3_fbi = drv_data->fbi->par; | 1170 | struct mx3fb_info *mx3_fbi = drv_data->fbi->par; |
| 1171 | 1171 | ||
| 1172 | if (mx3_fbi->blank == FB_BLANK_UNBLANK) { | 1172 | if (mx3_fbi->blank == FB_BLANK_UNBLANK) { |
| 1173 | sdc_enable_channel(mx3_fbi); | 1173 | sdc_enable_channel(mx3_fbi); |
| 1174 | sdc_set_brightness(mx3fb, drv_data->backlight_level); | 1174 | sdc_set_brightness(mx3fb, drv_data->backlight_level); |
| 1175 | } | 1175 | } |
| 1176 | 1176 | ||
| 1177 | acquire_console_sem(); | 1177 | acquire_console_sem(); |
| 1178 | fb_set_suspend(drv_data->fbi, 0); | 1178 | fb_set_suspend(drv_data->fbi, 0); |
| 1179 | release_console_sem(); | 1179 | release_console_sem(); |
| 1180 | 1180 | ||
| 1181 | return 0; | 1181 | return 0; |
| 1182 | } | 1182 | } |
| 1183 | #else | 1183 | #else |
| 1184 | #define mx3fb_suspend NULL | 1184 | #define mx3fb_suspend NULL |
| @@ -1191,8 +1191,8 @@ static int mx3fb_resume(struct platform_device *pdev) | |||
| 1191 | 1191 | ||
| 1192 | /** | 1192 | /** |
| 1193 | * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer. | 1193 | * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer. |
| 1194 | * @fbi: framebuffer information pointer | 1194 | * @fbi: framebuffer information pointer |
| 1195 | * @return: Error code indicating success or failure | 1195 | * @return: Error code indicating success or failure |
| 1196 | * | 1196 | * |
| 1197 | * This buffer is remapped into a non-cached, non-buffered, memory region to | 1197 | * This buffer is remapped into a non-cached, non-buffered, memory region to |
| 1198 | * allow palette and pixel writes to occur without flushing the cache. Once this | 1198 | * allow palette and pixel writes to occur without flushing the cache. Once this |
| @@ -1201,349 +1201,349 @@ static int mx3fb_resume(struct platform_device *pdev) | |||
| 1201 | */ | 1201 | */ |
| 1202 | static int mx3fb_map_video_memory(struct fb_info *fbi) | 1202 | static int mx3fb_map_video_memory(struct fb_info *fbi) |
| 1203 | { | 1203 | { |
| 1204 | int retval = 0; | 1204 | int retval = 0; |
| 1205 | dma_addr_t addr; | 1205 | dma_addr_t addr; |
| 1206 | 1206 | ||
| 1207 | fbi->screen_base = dma_alloc_writecombine(fbi->device, | 1207 | fbi->screen_base = dma_alloc_writecombine(fbi->device, |
| 1208 | fbi->fix.smem_len, | 1208 | fbi->fix.smem_len, |
| 1209 | &addr, GFP_DMA); | 1209 | &addr, GFP_DMA); |
| 1210 | 1210 | ||
| 1211 | if (!fbi->screen_base) { | 1211 | if (!fbi->screen_base) { |
| 1212 | dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n", | 1212 | dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n", |
| 1213 | fbi->fix.smem_len); | 1213 | fbi->fix.smem_len); |
| 1214 | retval = -EBUSY; | 1214 | retval = -EBUSY; |
| 1215 | goto err0; | 1215 | goto err0; |
| 1216 | } | 1216 | } |
| 1217 | 1217 | ||
| 1218 | fbi->fix.smem_start = addr; | 1218 | fbi->fix.smem_start = addr; |
| 1219 | 1219 | ||
| 1220 | dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n", | 1220 | dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n", |
| 1221 | (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len); | 1221 | (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len); |
| 1222 | 1222 | ||
| 1223 | fbi->screen_size = fbi->fix.smem_len; | 1223 | fbi->screen_size = fbi->fix.smem_len; |
| 1224 | 1224 | ||
| 1225 | /* Clear the screen */ | 1225 | /* Clear the screen */ |
| 1226 | memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); | 1226 | memset((char *)fbi->screen_base, 0, fbi->fix.smem_len); |
| 1227 | 1227 | ||
| 1228 | return 0; | 1228 | return 0; |
| 1229 | 1229 | ||
| 1230 | err0: | 1230 | err0: |
| 1231 | fbi->fix.smem_len = 0; | 1231 | fbi->fix.smem_len = 0; |
| 1232 | fbi->fix.smem_start = 0; | 1232 | fbi->fix.smem_start = 0; |
| 1233 | fbi->screen_base = NULL; | 1233 | fbi->screen_base = NULL; |
| 1234 | return retval; | 1234 | return retval; |
| 1235 | } | 1235 | } |
| 1236 | 1236 | ||
| 1237 | /** | 1237 | /** |
| 1238 | * mx3fb_unmap_video_memory() - de-allocate frame buffer memory. | 1238 | * mx3fb_unmap_video_memory() - de-allocate frame buffer memory. |
| 1239 | * @fbi: framebuffer information pointer | 1239 | * @fbi: framebuffer information pointer |
| 1240 | * @return: error code indicating success or failure | 1240 | * @return: error code indicating success or failure |
| 1241 | */ | 1241 | */ |
| 1242 | static int mx3fb_unmap_video_memory(struct fb_info *fbi) | 1242 | static int mx3fb_unmap_video_memory(struct fb_info *fbi) |
| 1243 | { | 1243 | { |
| 1244 | dma_free_writecombine(fbi->device, fbi->fix.smem_len, | 1244 | dma_free_writecombine(fbi->device, fbi->fix.smem_len, |
| 1245 | fbi->screen_base, fbi->fix.smem_start); | 1245 | fbi->screen_base, fbi->fix.smem_start); |
| 1246 | 1246 | ||
| 1247 | fbi->screen_base = 0; | 1247 | fbi->screen_base = 0; |
| 1248 | fbi->fix.smem_start = 0; | 1248 | fbi->fix.smem_start = 0; |
| 1249 | fbi->fix.smem_len = 0; | 1249 | fbi->fix.smem_len = 0; |
| 1250 | return 0; | 1250 | return 0; |
| 1251 | } | 1251 | } |
| 1252 | 1252 | ||
| 1253 | /** | 1253 | /** |
| 1254 | * mx3fb_init_fbinfo() - initialize framebuffer information object. | 1254 | * mx3fb_init_fbinfo() - initialize framebuffer information object. |
| 1255 | * @return: initialized framebuffer structure. | 1255 | * @return: initialized framebuffer structure. |
| 1256 | */ | 1256 | */ |
| 1257 | static struct fb_info *mx3fb_init_fbinfo(struct device *dev, struct fb_ops *ops) | 1257 | static struct fb_info *mx3fb_init_fbinfo(struct device *dev, struct fb_ops *ops) |
| 1258 | { | 1258 | { |
| 1259 | struct fb_info *fbi; | 1259 | struct fb_info *fbi; |
| 1260 | struct mx3fb_info *mx3fbi; | 1260 | struct mx3fb_info *mx3fbi; |
| 1261 | int ret; | 1261 | int ret; |
| 1262 | 1262 | ||
| 1263 | /* Allocate sufficient memory for the fb structure */ | 1263 | /* Allocate sufficient memory for the fb structure */ |
| 1264 | fbi = framebuffer_alloc(sizeof(struct mx3fb_info), dev); | 1264 | fbi = framebuffer_alloc(sizeof(struct mx3fb_info), dev); |
| 1265 | if (!fbi) | 1265 | if (!fbi) |
| 1266 | return NULL; | 1266 | return NULL; |
| 1267 | 1267 | ||
| 1268 | mx3fbi = fbi->par; | 1268 | mx3fbi = fbi->par; |
| 1269 | mx3fbi->cookie = -EINVAL; | 1269 | mx3fbi->cookie = -EINVAL; |
| 1270 | mx3fbi->cur_ipu_buf = 0; | 1270 | mx3fbi->cur_ipu_buf = 0; |
| 1271 | 1271 | ||
| 1272 | fbi->var.activate = FB_ACTIVATE_NOW; | 1272 | fbi->var.activate = FB_ACTIVATE_NOW; |
| 1273 | 1273 | ||
| 1274 | fbi->fbops = ops; | 1274 | fbi->fbops = ops; |
| 1275 | fbi->flags = FBINFO_FLAG_DEFAULT; | 1275 | fbi->flags = FBINFO_FLAG_DEFAULT; |
| 1276 | fbi->pseudo_palette = mx3fbi->pseudo_palette; | 1276 | fbi->pseudo_palette = mx3fbi->pseudo_palette; |
| 1277 | 1277 | ||
| 1278 | mutex_init(&mx3fbi->mutex); | 1278 | mutex_init(&mx3fbi->mutex); |
| 1279 | 1279 | ||
| 1280 | /* Allocate colormap */ | 1280 | /* Allocate colormap */ |
| 1281 | ret = fb_alloc_cmap(&fbi->cmap, 16, 0); | 1281 | ret = fb_alloc_cmap(&fbi->cmap, 16, 0); |
| 1282 | if (ret < 0) { | 1282 | if (ret < 0) { |
| 1283 | framebuffer_release(fbi); | 1283 | framebuffer_release(fbi); |
| 1284 | return NULL; | 1284 | return NULL; |
| 1285 | } | 1285 | } |
| 1286 | 1286 | ||
| 1287 | return fbi; | 1287 | return fbi; |
| 1288 | } | 1288 | } |
| 1289 | 1289 | ||
| 1290 | static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan) | 1290 | static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan) |
| 1291 | { | 1291 | { |
| 1292 | struct device *dev = mx3fb->dev; | 1292 | struct device *dev = mx3fb->dev; |
| 1293 | struct mx3fb_platform_data *mx3fb_pdata = dev->platform_data; | 1293 | struct mx3fb_platform_data *mx3fb_pdata = dev->platform_data; |
| 1294 | const char *name = mx3fb_pdata->name; | 1294 | const char *name = mx3fb_pdata->name; |
| 1295 | unsigned int irq; | 1295 | unsigned int irq; |
| 1296 | struct fb_info *fbi; | 1296 | struct fb_info *fbi; |
| 1297 | struct mx3fb_info *mx3fbi; | 1297 | struct mx3fb_info *mx3fbi; |
| 1298 | const struct fb_videomode *mode; | 1298 | const struct fb_videomode *mode; |
| 1299 | int ret, num_modes; | 1299 | int ret, num_modes; |
| 1300 | 1300 | ||
| 1301 | ichan->client = mx3fb; | 1301 | ichan->client = mx3fb; |
| 1302 | irq = ichan->eof_irq; | 1302 | irq = ichan->eof_irq; |
| 1303 | 1303 | ||
| 1304 | if (ichan->dma_chan.chan_id != IDMAC_SDC_0) | 1304 | if (ichan->dma_chan.chan_id != IDMAC_SDC_0) |
| 1305 | return -EINVAL; | 1305 | return -EINVAL; |
| 1306 | 1306 | ||
| 1307 | fbi = mx3fb_init_fbinfo(dev, &mx3fb_ops); | 1307 | fbi = mx3fb_init_fbinfo(dev, &mx3fb_ops); |
| 1308 | if (!fbi) | 1308 | if (!fbi) |
| 1309 | return -ENOMEM; | 1309 | return -ENOMEM; |
| 1310 | 1310 | ||
| 1311 | if (!fb_mode) | 1311 | if (!fb_mode) |
| 1312 | fb_mode = name; | 1312 | fb_mode = name; |
| 1313 | 1313 | ||
| 1314 | if (!fb_mode) { | 1314 | if (!fb_mode) { |
| 1315 | ret = -EINVAL; | 1315 | ret = -EINVAL; |
| 1316 | goto emode; | 1316 | goto emode; |
| 1317 | } | 1317 | } |
| 1318 | 1318 | ||
| 1319 | if (mx3fb_pdata->mode && mx3fb_pdata->num_modes) { | 1319 | if (mx3fb_pdata->mode && mx3fb_pdata->num_modes) { |
| 1320 | mode = mx3fb_pdata->mode; | 1320 | mode = mx3fb_pdata->mode; |
| 1321 | num_modes = mx3fb_pdata->num_modes; | 1321 | num_modes = mx3fb_pdata->num_modes; |
| 1322 | } else { | 1322 | } else { |
| 1323 | mode = mx3fb_modedb; | 1323 | mode = mx3fb_modedb; |
| 1324 | num_modes = ARRAY_SIZE(mx3fb_modedb); | 1324 | num_modes = ARRAY_SIZE(mx3fb_modedb); |
| 1325 | } | 1325 | } |
| 1326 | 1326 | ||
| 1327 | if (!fb_find_mode(&fbi->var, fbi, fb_mode, mode, | 1327 | if (!fb_find_mode(&fbi->var, fbi, fb_mode, mode, |
| 1328 | num_modes, NULL, default_bpp)) { | 1328 | num_modes, NULL, default_bpp)) { |
| 1329 | ret = -EBUSY; | 1329 | ret = -EBUSY; |
| 1330 | goto emode; | 1330 | goto emode; |
| 1331 | } | 1331 | } |
| 1332 | 1332 | ||
| 1333 | fb_videomode_to_modelist(mode, num_modes, &fbi->modelist); | 1333 | fb_videomode_to_modelist(mode, num_modes, &fbi->modelist); |
| 1334 | 1334 | ||
| 1335 | /* Default Y virtual size is 2x panel size */ | 1335 | /* Default Y virtual size is 2x panel size */ |
| 1336 | fbi->var.yres_virtual = fbi->var.yres * 2; | 1336 | fbi->var.yres_virtual = fbi->var.yres * 2; |
| 1337 | 1337 | ||
| 1338 | mx3fb->fbi = fbi; | 1338 | mx3fb->fbi = fbi; |
| 1339 | 1339 | ||
| 1340 | /* set Display Interface clock period */ | 1340 | /* set Display Interface clock period */ |
| 1341 | mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER); | 1341 | mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER); |
| 1342 | /* Might need to trigger HSP clock change - see 44.3.3.8.5 */ | 1342 | /* Might need to trigger HSP clock change - see 44.3.3.8.5 */ |
| 1343 | 1343 | ||
| 1344 | sdc_set_brightness(mx3fb, 255); | 1344 | sdc_set_brightness(mx3fb, 255); |
| 1345 | sdc_set_global_alpha(mx3fb, true, 0xFF); | 1345 | sdc_set_global_alpha(mx3fb, true, 0xFF); |
| 1346 | sdc_set_color_key(mx3fb, IDMAC_SDC_0, false, 0); | 1346 | sdc_set_color_key(mx3fb, IDMAC_SDC_0, false, 0); |
| 1347 | 1347 | ||
| 1348 | mx3fbi = fbi->par; | 1348 | mx3fbi = fbi->par; |
| 1349 | mx3fbi->idmac_channel = ichan; | 1349 | mx3fbi->idmac_channel = ichan; |
| 1350 | mx3fbi->ipu_ch = ichan->dma_chan.chan_id; | 1350 | mx3fbi->ipu_ch = ichan->dma_chan.chan_id; |
| 1351 | mx3fbi->mx3fb = mx3fb; | 1351 | mx3fbi->mx3fb = mx3fb; |
| 1352 | mx3fbi->blank = FB_BLANK_NORMAL; | 1352 | mx3fbi->blank = FB_BLANK_NORMAL; |
| 1353 | 1353 | ||
| 1354 | init_completion(&mx3fbi->flip_cmpl); | 1354 | init_completion(&mx3fbi->flip_cmpl); |
| 1355 | disable_irq(ichan->eof_irq); | 1355 | disable_irq(ichan->eof_irq); |
| 1356 | dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq); | 1356 | dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq); |
| 1357 | ret = mx3fb_set_par(fbi); | 1357 | ret = mx3fb_set_par(fbi); |
| 1358 | if (ret < 0) | 1358 | if (ret < 0) |
| 1359 | goto esetpar; | 1359 | goto esetpar; |
| 1360 | 1360 | ||
| 1361 | mx3fb_blank(FB_BLANK_UNBLANK, fbi); | 1361 | mx3fb_blank(FB_BLANK_UNBLANK, fbi); |
| 1362 | 1362 | ||
| 1363 | dev_info(dev, "mx3fb: fb registered, using mode %s\n", fb_mode); | 1363 | dev_info(dev, "mx3fb: fb registered, using mode %s\n", fb_mode); |
| 1364 | 1364 | ||
| 1365 | ret = register_framebuffer(fbi); | 1365 | ret = register_framebuffer(fbi); |
| 1366 | if (ret < 0) | 1366 | if (ret < 0) |
| 1367 | goto erfb; | 1367 | goto erfb; |
| 1368 | 1368 | ||
| 1369 | return 0; | 1369 | return 0; |
| 1370 | 1370 | ||
| 1371 | erfb: | 1371 | erfb: |
| 1372 | esetpar: | 1372 | esetpar: |
| 1373 | emode: | 1373 | emode: |
| 1374 | fb_dealloc_cmap(&fbi->cmap); | 1374 | fb_dealloc_cmap(&fbi->cmap); |
| 1375 | framebuffer_release(fbi); | 1375 | framebuffer_release(fbi); |
| 1376 | 1376 | ||
| 1377 | return ret; | 1377 | return ret; |
| 1378 | } | 1378 | } |
| 1379 | 1379 | ||
| 1380 | static bool chan_filter(struct dma_chan *chan, void *arg) | 1380 | static bool chan_filter(struct dma_chan *chan, void *arg) |
| 1381 | { | 1381 | { |
| 1382 | struct dma_chan_request *rq = arg; | 1382 | struct dma_chan_request *rq = arg; |
| 1383 | struct device *dev; | 1383 | struct device *dev; |
| 1384 | struct mx3fb_platform_data *mx3fb_pdata; | 1384 | struct mx3fb_platform_data *mx3fb_pdata; |
| 1385 | 1385 | ||
| 1386 | if (!rq) | 1386 | if (!rq) |
| 1387 | return false; | 1387 | return false; |
| 1388 | 1388 | ||
| 1389 | dev = rq->mx3fb->dev; | 1389 | dev = rq->mx3fb->dev; |
| 1390 | mx3fb_pdata = dev->platform_data; | 1390 | mx3fb_pdata = dev->platform_data; |
| 1391 | 1391 | ||
| 1392 | return rq->id == chan->chan_id && | 1392 | return rq->id == chan->chan_id && |
| 1393 | mx3fb_pdata->dma_dev == chan->device->dev; | 1393 | mx3fb_pdata->dma_dev == chan->device->dev; |
| 1394 | } | 1394 | } |
| 1395 | 1395 | ||
| 1396 | static void release_fbi(struct fb_info *fbi) | 1396 | static void release_fbi(struct fb_info *fbi) |
| 1397 | { | 1397 | { |
| 1398 | mx3fb_unmap_video_memory(fbi); | 1398 | mx3fb_unmap_video_memory(fbi); |
| 1399 | 1399 | ||
| 1400 | fb_dealloc_cmap(&fbi->cmap); | 1400 | fb_dealloc_cmap(&fbi->cmap); |
| 1401 | 1401 | ||
| 1402 | unregister_framebuffer(fbi); | 1402 | unregister_framebuffer(fbi); |
| 1403 | framebuffer_release(fbi); | 1403 | framebuffer_release(fbi); |
| 1404 | } | 1404 | } |
| 1405 | 1405 | ||
| 1406 | static int mx3fb_probe(struct platform_device *pdev) | 1406 | static int mx3fb_probe(struct platform_device *pdev) |
| 1407 | { | 1407 | { |
| 1408 | struct device *dev = &pdev->dev; | 1408 | struct device *dev = &pdev->dev; |
| 1409 | int ret; | 1409 | int ret; |
| 1410 | struct resource *sdc_reg; | 1410 | struct resource *sdc_reg; |
| 1411 | struct mx3fb_data *mx3fb; | 1411 | struct mx3fb_data *mx3fb; |
| 1412 | dma_cap_mask_t mask; | 1412 | dma_cap_mask_t mask; |
| 1413 | struct dma_chan *chan; | 1413 | struct dma_chan *chan; |
| 1414 | struct dma_chan_request rq; | 1414 | struct dma_chan_request rq; |
| 1415 | 1415 | ||
| 1416 | /* | 1416 | /* |
| 1417 | * Display Interface (DI) and Synchronous Display Controller (SDC) | 1417 | * Display Interface (DI) and Synchronous Display Controller (SDC) |
| 1418 | * registers | 1418 | * registers |
| 1419 | */ | 1419 | */ |
| 1420 | sdc_reg = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1420 | sdc_reg = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 1421 | if (!sdc_reg) | 1421 | if (!sdc_reg) |
| 1422 | return -EINVAL; | 1422 | return -EINVAL; |
| 1423 | 1423 | ||
| 1424 | mx3fb = kzalloc(sizeof(*mx3fb), GFP_KERNEL); | 1424 | mx3fb = kzalloc(sizeof(*mx3fb), GFP_KERNEL); |
| 1425 | if (!mx3fb) | 1425 | if (!mx3fb) |
| 1426 | return -ENOMEM; | 1426 | return -ENOMEM; |
| 1427 | 1427 | ||
| 1428 | spin_lock_init(&mx3fb->lock); | 1428 | spin_lock_init(&mx3fb->lock); |
| 1429 | 1429 | ||
| 1430 | mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg)); | 1430 | mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg)); |
| 1431 | if (!mx3fb->reg_base) { | 1431 | if (!mx3fb->reg_base) { |
| 1432 | ret = -ENOMEM; | 1432 | ret = -ENOMEM; |
| 1433 | goto eremap; | 1433 | goto eremap; |
| 1434 | } | 1434 | } |
| 1435 | 1435 | ||
| 1436 | pr_debug("Remapped %x to %x at %p\n", sdc_reg->start, sdc_reg->end, | 1436 | pr_debug("Remapped %x to %x at %p\n", sdc_reg->start, sdc_reg->end, |
| 1437 | mx3fb->reg_base); | 1437 | mx3fb->reg_base); |
| 1438 | 1438 | ||
| 1439 | /* IDMAC interface */ | 1439 | /* IDMAC interface */ |
| 1440 | dmaengine_get(); | 1440 | dmaengine_get(); |
| 1441 | 1441 | ||
| 1442 | mx3fb->dev = dev; | 1442 | mx3fb->dev = dev; |
| 1443 | platform_set_drvdata(pdev, mx3fb); | 1443 | platform_set_drvdata(pdev, mx3fb); |
| 1444 | 1444 | ||
| 1445 | rq.mx3fb = mx3fb; | 1445 | rq.mx3fb = mx3fb; |
| 1446 | 1446 | ||
| 1447 | dma_cap_zero(mask); | 1447 | dma_cap_zero(mask); |
| 1448 | dma_cap_set(DMA_SLAVE, mask); | 1448 | dma_cap_set(DMA_SLAVE, mask); |
| 1449 | dma_cap_set(DMA_PRIVATE, mask); | 1449 | dma_cap_set(DMA_PRIVATE, mask); |
| 1450 | rq.id = IDMAC_SDC_0; | 1450 | rq.id = IDMAC_SDC_0; |
| 1451 | chan = dma_request_channel(mask, chan_filter, &rq); | 1451 | chan = dma_request_channel(mask, chan_filter, &rq); |
| 1452 | if (!chan) { | 1452 | if (!chan) { |
| 1453 | ret = -EBUSY; | 1453 | ret = -EBUSY; |
| 1454 | goto ersdc0; | 1454 | goto ersdc0; |
| 1455 | } | 1455 | } |
| 1456 | 1456 | ||
| 1457 | ret = init_fb_chan(mx3fb, to_idmac_chan(chan)); | 1457 | ret = init_fb_chan(mx3fb, to_idmac_chan(chan)); |
| 1458 | if (ret < 0) | 1458 | if (ret < 0) |
| 1459 | goto eisdc0; | 1459 | goto eisdc0; |
| 1460 | 1460 | ||
| 1461 | mx3fb->backlight_level = 255; | 1461 | mx3fb->backlight_level = 255; |
| 1462 | 1462 | ||
| 1463 | return 0; | 1463 | return 0; |
| 1464 | 1464 | ||
| 1465 | eisdc0: | 1465 | eisdc0: |
| 1466 | dma_release_channel(chan); | 1466 | dma_release_channel(chan); |
| 1467 | ersdc0: | 1467 | ersdc0: |
| 1468 | dmaengine_put(); | 1468 | dmaengine_put(); |
| 1469 | iounmap(mx3fb->reg_base); | 1469 | iounmap(mx3fb->reg_base); |
| 1470 | eremap: | 1470 | eremap: |
| 1471 | kfree(mx3fb); | 1471 | kfree(mx3fb); |
| 1472 | dev_err(dev, "mx3fb: failed to register fb\n"); | 1472 | dev_err(dev, "mx3fb: failed to register fb\n"); |
| 1473 | return ret; | 1473 | return ret; |
| 1474 | } | 1474 | } |
| 1475 | 1475 | ||
| 1476 | static int mx3fb_remove(struct platform_device *dev) | 1476 | static int mx3fb_remove(struct platform_device *dev) |
| 1477 | { | 1477 | { |
| 1478 | struct mx3fb_data *mx3fb = platform_get_drvdata(dev); | 1478 | struct mx3fb_data *mx3fb = platform_get_drvdata(dev); |
| 1479 | struct fb_info *fbi = mx3fb->fbi; | 1479 | struct fb_info *fbi = mx3fb->fbi; |
| 1480 | struct mx3fb_info *mx3_fbi = fbi->par; | 1480 | struct mx3fb_info *mx3_fbi = fbi->par; |
| 1481 | struct dma_chan *chan; | 1481 | struct dma_chan *chan; |
| 1482 | 1482 | ||
| 1483 | chan = &mx3_fbi->idmac_channel->dma_chan; | 1483 | chan = &mx3_fbi->idmac_channel->dma_chan; |
| 1484 | release_fbi(fbi); | 1484 | release_fbi(fbi); |
| 1485 | 1485 | ||
| 1486 | dma_release_channel(chan); | 1486 | dma_release_channel(chan); |
| 1487 | dmaengine_put(); | 1487 | dmaengine_put(); |
| 1488 | 1488 | ||
| 1489 | iounmap(mx3fb->reg_base); | 1489 | iounmap(mx3fb->reg_base); |
| 1490 | kfree(mx3fb); | 1490 | kfree(mx3fb); |
| 1491 | return 0; | 1491 | return 0; |
| 1492 | } | 1492 | } |
| 1493 | 1493 | ||
| 1494 | static struct platform_driver mx3fb_driver = { | 1494 | static struct platform_driver mx3fb_driver = { |
| 1495 | .driver = { | 1495 | .driver = { |
| 1496 | .name = MX3FB_NAME, | 1496 | .name = MX3FB_NAME, |
| 1497 | }, | 1497 | }, |
| 1498 | .probe = mx3fb_probe, | 1498 | .probe = mx3fb_probe, |
| 1499 | .remove = mx3fb_remove, | 1499 | .remove = mx3fb_remove, |
| 1500 | .suspend = mx3fb_suspend, | 1500 | .suspend = mx3fb_suspend, |
| 1501 | .resume = mx3fb_resume, | 1501 | .resume = mx3fb_resume, |
| 1502 | }; | 1502 | }; |
| 1503 | 1503 | ||
| 1504 | /* | 1504 | /* |
| 1505 | * Parse user specified options (`video=mx3fb:') | 1505 | * Parse user specified options (`video=mx3fb:') |
| 1506 | * example: | 1506 | * example: |
| 1507 | * video=mx3fb:bpp=16 | 1507 | * video=mx3fb:bpp=16 |
| 1508 | */ | 1508 | */ |
| 1509 | static int mx3fb_setup(void) | 1509 | static int mx3fb_setup(void) |
| 1510 | { | 1510 | { |
| 1511 | #ifndef MODULE | 1511 | #ifndef MODULE |
| 1512 | char *opt, *options = NULL; | 1512 | char *opt, *options = NULL; |
| 1513 | 1513 | ||
| 1514 | if (fb_get_options("mx3fb", &options)) | 1514 | if (fb_get_options("mx3fb", &options)) |
| 1515 | return -ENODEV; | 1515 | return -ENODEV; |
| 1516 | 1516 | ||
| 1517 | if (!options || !*options) | 1517 | if (!options || !*options) |
| 1518 | return 0; | 1518 | return 0; |
| 1519 | 1519 | ||
| 1520 | while ((opt = strsep(&options, ",")) != NULL) { | 1520 | while ((opt = strsep(&options, ",")) != NULL) { |
| 1521 | if (!*opt) | 1521 | if (!*opt) |
| 1522 | continue; | 1522 | continue; |
| 1523 | if (!strncmp(opt, "bpp=", 4)) | 1523 | if (!strncmp(opt, "bpp=", 4)) |
| 1524 | default_bpp = simple_strtoul(opt + 4, NULL, 0); | 1524 | default_bpp = simple_strtoul(opt + 4, NULL, 0); |
| 1525 | else | 1525 | else |
| 1526 | fb_mode = opt; | 1526 | fb_mode = opt; |
| 1527 | } | 1527 | } |
| 1528 | #endif | 1528 | #endif |
| 1529 | 1529 | ||
| 1530 | return 0; | 1530 | return 0; |
| 1531 | } | 1531 | } |
| 1532 | 1532 | ||
| 1533 | static int __init mx3fb_init(void) | 1533 | static int __init mx3fb_init(void) |
| 1534 | { | 1534 | { |
| 1535 | int ret = mx3fb_setup(); | 1535 | int ret = mx3fb_setup(); |
| 1536 | 1536 | ||
| 1537 | if (ret < 0) | 1537 | if (ret < 0) |
| 1538 | return ret; | 1538 | return ret; |
| 1539 | 1539 | ||
| 1540 | ret = platform_driver_register(&mx3fb_driver); | 1540 | ret = platform_driver_register(&mx3fb_driver); |
| 1541 | return ret; | 1541 | return ret; |
| 1542 | } | 1542 | } |
| 1543 | 1543 | ||
| 1544 | static void __exit mx3fb_exit(void) | 1544 | static void __exit mx3fb_exit(void) |
| 1545 | { | 1545 | { |
| 1546 | platform_driver_unregister(&mx3fb_driver); | 1546 | platform_driver_unregister(&mx3fb_driver); |
| 1547 | } | 1547 | } |
| 1548 | 1548 | ||
| 1549 | module_init(mx3fb_init); | 1549 | module_init(mx3fb_init); |
diff --git a/drivers/video/pxafb.c b/drivers/video/pxafb.c index 2552b9f325ee..84f63205c46d 100644 --- a/drivers/video/pxafb.c +++ b/drivers/video/pxafb.c | |||
| @@ -59,7 +59,6 @@ | |||
| 59 | #include <asm/io.h> | 59 | #include <asm/io.h> |
| 60 | #include <asm/irq.h> | 60 | #include <asm/irq.h> |
| 61 | #include <asm/div64.h> | 61 | #include <asm/div64.h> |
| 62 | #include <mach/pxa-regs.h> | ||
| 63 | #include <mach/bitfield.h> | 62 | #include <mach/bitfield.h> |
| 64 | #include <mach/pxafb.h> | 63 | #include <mach/pxafb.h> |
| 65 | 64 | ||
| @@ -883,10 +882,21 @@ static void __devinit init_pxafb_overlay(struct pxafb_info *fbi, | |||
| 883 | init_completion(&ofb->branch_done); | 882 | init_completion(&ofb->branch_done); |
| 884 | } | 883 | } |
| 885 | 884 | ||
| 885 | static inline int pxafb_overlay_supported(void) | ||
| 886 | { | ||
| 887 | if (cpu_is_pxa27x() || cpu_is_pxa3xx()) | ||
| 888 | return 1; | ||
| 889 | |||
| 890 | return 0; | ||
| 891 | } | ||
| 892 | |||
| 886 | static int __devinit pxafb_overlay_init(struct pxafb_info *fbi) | 893 | static int __devinit pxafb_overlay_init(struct pxafb_info *fbi) |
| 887 | { | 894 | { |
| 888 | int i, ret; | 895 | int i, ret; |
| 889 | 896 | ||
| 897 | if (!pxafb_overlay_supported()) | ||
| 898 | return 0; | ||
| 899 | |||
| 890 | for (i = 0; i < 2; i++) { | 900 | for (i = 0; i < 2; i++) { |
| 891 | init_pxafb_overlay(fbi, &fbi->overlay[i], i); | 901 | init_pxafb_overlay(fbi, &fbi->overlay[i], i); |
| 892 | ret = register_framebuffer(&fbi->overlay[i].fb); | 902 | ret = register_framebuffer(&fbi->overlay[i].fb); |
| @@ -909,6 +919,9 @@ static void __devexit pxafb_overlay_exit(struct pxafb_info *fbi) | |||
| 909 | { | 919 | { |
| 910 | int i; | 920 | int i; |
| 911 | 921 | ||
| 922 | if (!pxafb_overlay_supported()) | ||
| 923 | return; | ||
| 924 | |||
| 912 | for (i = 0; i < 2; i++) | 925 | for (i = 0; i < 2; i++) |
| 913 | unregister_framebuffer(&fbi->overlay[i].fb); | 926 | unregister_framebuffer(&fbi->overlay[i].fb); |
| 914 | } | 927 | } |
diff --git a/drivers/video/s3c2410fb.c b/drivers/video/s3c2410fb.c index 79cf0b1976aa..b0b4513ba537 100644 --- a/drivers/video/s3c2410fb.c +++ b/drivers/video/s3c2410fb.c | |||
| @@ -1017,6 +1017,10 @@ static int s3c2410fb_resume(struct platform_device *dev) | |||
| 1017 | 1017 | ||
| 1018 | s3c2410fb_init_registers(fbinfo); | 1018 | s3c2410fb_init_registers(fbinfo); |
| 1019 | 1019 | ||
| 1020 | /* re-activate our display after resume */ | ||
| 1021 | s3c2410fb_activate_var(fbinfo); | ||
| 1022 | s3c2410fb_blank(FB_BLANK_UNBLANK, fbinfo); | ||
| 1023 | |||
| 1020 | return 0; | 1024 | return 0; |
| 1021 | } | 1025 | } |
| 1022 | 1026 | ||
diff --git a/drivers/video/sa1100fb.c b/drivers/video/sa1100fb.c index 076f946fa0f5..fad58cf9ef73 100644 --- a/drivers/video/sa1100fb.c +++ b/drivers/video/sa1100fb.c | |||
| @@ -176,9 +176,9 @@ | |||
| 176 | #include <linux/platform_device.h> | 176 | #include <linux/platform_device.h> |
| 177 | #include <linux/dma-mapping.h> | 177 | #include <linux/dma-mapping.h> |
| 178 | #include <linux/mutex.h> | 178 | #include <linux/mutex.h> |
| 179 | #include <linux/io.h> | ||
| 179 | 180 | ||
| 180 | #include <mach/hardware.h> | 181 | #include <mach/hardware.h> |
| 181 | #include <asm/io.h> | ||
| 182 | #include <asm/mach-types.h> | 182 | #include <asm/mach-types.h> |
| 183 | #include <mach/assabet.h> | 183 | #include <mach/assabet.h> |
| 184 | #include <mach/shannon.h> | 184 | #include <mach/shannon.h> |
| @@ -251,22 +251,6 @@ static struct sa1100fb_mach_info pal_info __initdata = { | |||
| 251 | #endif | 251 | #endif |
| 252 | #endif | 252 | #endif |
| 253 | 253 | ||
| 254 | #ifdef CONFIG_SA1100_H3800 | ||
| 255 | static struct sa1100fb_mach_info h3800_info __initdata = { | ||
| 256 | .pixclock = 174757, .bpp = 16, | ||
| 257 | .xres = 320, .yres = 240, | ||
| 258 | |||
| 259 | .hsync_len = 3, .vsync_len = 3, | ||
| 260 | .left_margin = 12, .upper_margin = 10, | ||
| 261 | .right_margin = 17, .lower_margin = 1, | ||
| 262 | |||
| 263 | .cmap_static = 1, | ||
| 264 | |||
| 265 | .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act, | ||
| 266 | .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2), | ||
| 267 | }; | ||
| 268 | #endif | ||
| 269 | |||
| 270 | #ifdef CONFIG_SA1100_H3600 | 254 | #ifdef CONFIG_SA1100_H3600 |
| 271 | static struct sa1100fb_mach_info h3600_info __initdata = { | 255 | static struct sa1100fb_mach_info h3600_info __initdata = { |
| 272 | .pixclock = 174757, .bpp = 16, | 256 | .pixclock = 174757, .bpp = 16, |
| @@ -432,11 +416,6 @@ sa1100fb_get_machine_info(struct sa1100fb_info *fbi) | |||
| 432 | fbi->rgb[RGB_16] = &h3600_rgb_16; | 416 | fbi->rgb[RGB_16] = &h3600_rgb_16; |
| 433 | } | 417 | } |
| 434 | #endif | 418 | #endif |
| 435 | #ifdef CONFIG_SA1100_H3800 | ||
| 436 | if (machine_is_h3800()) { | ||
| 437 | inf = &h3800_info; | ||
| 438 | } | ||
| 439 | #endif | ||
| 440 | #ifdef CONFIG_SA1100_COLLIE | 419 | #ifdef CONFIG_SA1100_COLLIE |
| 441 | if (machine_is_collie()) { | 420 | if (machine_is_collie()) { |
| 442 | inf = &collie_info; | 421 | inf = &collie_info; |
diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c index 0e2b8fd24df1..2c5d069e5f06 100644 --- a/drivers/video/sh_mobile_lcdcfb.c +++ b/drivers/video/sh_mobile_lcdcfb.c | |||
| @@ -446,7 +446,6 @@ static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv) | |||
| 446 | { | 446 | { |
| 447 | struct sh_mobile_lcdc_chan *ch; | 447 | struct sh_mobile_lcdc_chan *ch; |
| 448 | struct sh_mobile_lcdc_board_cfg *board_cfg; | 448 | struct sh_mobile_lcdc_board_cfg *board_cfg; |
| 449 | unsigned long tmp; | ||
| 450 | int k; | 449 | int k; |
| 451 | 450 | ||
| 452 | /* tell the board code to disable the panel */ | 451 | /* tell the board code to disable the panel */ |
| @@ -456,9 +455,8 @@ static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv) | |||
| 456 | if (board_cfg->display_off) | 455 | if (board_cfg->display_off) |
| 457 | board_cfg->display_off(board_cfg->board_data); | 456 | board_cfg->display_off(board_cfg->board_data); |
| 458 | 457 | ||
| 459 | /* cleanup deferred io if SYS bus */ | 458 | /* cleanup deferred io if enabled */ |
| 460 | tmp = ch->cfg.sys_bus_cfg.deferred_io_msec; | 459 | if (ch->info.fbdefio) { |
| 461 | if (ch->ldmt1r_value & (1 << 12) && tmp) { | ||
| 462 | fb_deferred_io_cleanup(&ch->info); | 460 | fb_deferred_io_cleanup(&ch->info); |
| 463 | ch->info.fbdefio = NULL; | 461 | ch->info.fbdefio = NULL; |
| 464 | } | 462 | } |
diff --git a/drivers/w1/masters/mxc_w1.c b/drivers/w1/masters/mxc_w1.c index b9d74d0b353e..65244c02551b 100644 --- a/drivers/w1/masters/mxc_w1.c +++ b/drivers/w1/masters/mxc_w1.c | |||
| @@ -116,7 +116,7 @@ static int __init mxc_w1_probe(struct platform_device *pdev) | |||
| 116 | if (!mdev) | 116 | if (!mdev) |
| 117 | return -ENOMEM; | 117 | return -ENOMEM; |
| 118 | 118 | ||
| 119 | mdev->clk = clk_get(&pdev->dev, "owire_clk"); | 119 | mdev->clk = clk_get(&pdev->dev, "owire"); |
| 120 | if (!mdev->clk) { | 120 | if (!mdev->clk) { |
| 121 | err = -ENODEV; | 121 | err = -ENODEV; |
| 122 | goto failed_clk; | 122 | goto failed_clk; |
diff --git a/drivers/w1/masters/omap_hdq.c b/drivers/w1/masters/omap_hdq.c index c973889110c8..a7e3b706b9d3 100644 --- a/drivers/w1/masters/omap_hdq.c +++ b/drivers/w1/masters/omap_hdq.c | |||
| @@ -590,8 +590,8 @@ static int __init omap_hdq_probe(struct platform_device *pdev) | |||
| 590 | } | 590 | } |
| 591 | 591 | ||
| 592 | /* get interface & functional clock objects */ | 592 | /* get interface & functional clock objects */ |
| 593 | hdq_data->hdq_ick = clk_get(&pdev->dev, "hdq_ick"); | 593 | hdq_data->hdq_ick = clk_get(&pdev->dev, "ick"); |
| 594 | hdq_data->hdq_fck = clk_get(&pdev->dev, "hdq_fck"); | 594 | hdq_data->hdq_fck = clk_get(&pdev->dev, "fck"); |
| 595 | 595 | ||
| 596 | if (IS_ERR(hdq_data->hdq_ick) || IS_ERR(hdq_data->hdq_fck)) { | 596 | if (IS_ERR(hdq_data->hdq_ick) || IS_ERR(hdq_data->hdq_fck)) { |
| 597 | dev_dbg(&pdev->dev, "Can't get HDQ clock objects\n"); | 597 | dev_dbg(&pdev->dev, "Can't get HDQ clock objects\n"); |
diff --git a/drivers/w1/masters/w1-gpio.c b/drivers/w1/masters/w1-gpio.c index 9e1138a75e8b..a411702413d6 100644 --- a/drivers/w1/masters/w1-gpio.c +++ b/drivers/w1/masters/w1-gpio.c | |||
| @@ -39,7 +39,7 @@ static u8 w1_gpio_read_bit(void *data) | |||
| 39 | { | 39 | { |
| 40 | struct w1_gpio_platform_data *pdata = data; | 40 | struct w1_gpio_platform_data *pdata = data; |
| 41 | 41 | ||
| 42 | return gpio_get_value(pdata->pin); | 42 | return gpio_get_value(pdata->pin) ? 1 : 0; |
| 43 | } | 43 | } |
| 44 | 44 | ||
| 45 | static int __init w1_gpio_probe(struct platform_device *pdev) | 45 | static int __init w1_gpio_probe(struct platform_device *pdev) |
diff --git a/drivers/watchdog/gef_wdt.c b/drivers/watchdog/gef_wdt.c index f0c2b7a1a175..734d9806a872 100644 --- a/drivers/watchdog/gef_wdt.c +++ b/drivers/watchdog/gef_wdt.c | |||
| @@ -269,7 +269,7 @@ static int __devinit gef_wdt_probe(struct of_device *dev, | |||
| 269 | bus_clk = 133; /* in MHz */ | 269 | bus_clk = 133; /* in MHz */ |
| 270 | 270 | ||
| 271 | freq = fsl_get_sys_freq(); | 271 | freq = fsl_get_sys_freq(); |
| 272 | if (freq > 0) | 272 | if (freq != -1) |
| 273 | bus_clk = freq; | 273 | bus_clk = freq; |
| 274 | 274 | ||
| 275 | /* Map devices registers into memory */ | 275 | /* Map devices registers into memory */ |
diff --git a/drivers/watchdog/ks8695_wdt.c b/drivers/watchdog/ks8695_wdt.c index 0b798fdaa378..74c92d384112 100644 --- a/drivers/watchdog/ks8695_wdt.c +++ b/drivers/watchdog/ks8695_wdt.c | |||
| @@ -21,6 +21,7 @@ | |||
| 21 | #include <linux/watchdog.h> | 21 | #include <linux/watchdog.h> |
| 22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
| 23 | #include <linux/uaccess.h> | 23 | #include <linux/uaccess.h> |
| 24 | #include <mach/timex.h> | ||
| 24 | #include <mach/regs-timer.h> | 25 | #include <mach/regs-timer.h> |
| 25 | 26 | ||
| 26 | #define WDT_DEFAULT_TIME 5 /* seconds */ | 27 | #define WDT_DEFAULT_TIME 5 /* seconds */ |
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 2f2ce7429f5b..aa5ad6e33f02 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c | |||
| @@ -60,9 +60,8 @@ struct omap_wdt_dev { | |||
| 60 | void __iomem *base; /* physical */ | 60 | void __iomem *base; /* physical */ |
| 61 | struct device *dev; | 61 | struct device *dev; |
| 62 | int omap_wdt_users; | 62 | int omap_wdt_users; |
| 63 | struct clk *armwdt_ck; | 63 | struct clk *ick; |
| 64 | struct clk *mpu_wdt_ick; | 64 | struct clk *fck; |
| 65 | struct clk *mpu_wdt_fck; | ||
| 66 | struct resource *mem; | 65 | struct resource *mem; |
| 67 | struct miscdevice omap_wdt_miscdev; | 66 | struct miscdevice omap_wdt_miscdev; |
| 68 | }; | 67 | }; |
| @@ -146,13 +145,8 @@ static int omap_wdt_open(struct inode *inode, struct file *file) | |||
| 146 | if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users))) | 145 | if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users))) |
| 147 | return -EBUSY; | 146 | return -EBUSY; |
| 148 | 147 | ||
| 149 | if (cpu_is_omap16xx()) | 148 | clk_enable(wdev->ick); /* Enable the interface clock */ |
| 150 | clk_enable(wdev->armwdt_ck); /* Enable the clock */ | 149 | clk_enable(wdev->fck); /* Enable the functional clock */ |
| 151 | |||
| 152 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | ||
| 153 | clk_enable(wdev->mpu_wdt_ick); /* Enable the interface clock */ | ||
| 154 | clk_enable(wdev->mpu_wdt_fck); /* Enable the functional clock */ | ||
| 155 | } | ||
| 156 | 150 | ||
| 157 | /* initialize prescaler */ | 151 | /* initialize prescaler */ |
| 158 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) | 152 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) |
| @@ -181,13 +175,8 @@ static int omap_wdt_release(struct inode *inode, struct file *file) | |||
| 181 | 175 | ||
| 182 | omap_wdt_disable(wdev); | 176 | omap_wdt_disable(wdev); |
| 183 | 177 | ||
| 184 | if (cpu_is_omap16xx()) | 178 | clk_disable(wdev->ick); |
| 185 | clk_disable(wdev->armwdt_ck); /* Disable the clock */ | 179 | clk_disable(wdev->fck); |
| 186 | |||
| 187 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | ||
| 188 | clk_disable(wdev->mpu_wdt_ick); /* Disable the clock */ | ||
| 189 | clk_disable(wdev->mpu_wdt_fck); /* Disable the clock */ | ||
| 190 | } | ||
| 191 | #else | 180 | #else |
| 192 | printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n"); | 181 | printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n"); |
| 193 | #endif | 182 | #endif |
| @@ -303,44 +292,19 @@ static int __init omap_wdt_probe(struct platform_device *pdev) | |||
| 303 | wdev->omap_wdt_users = 0; | 292 | wdev->omap_wdt_users = 0; |
| 304 | wdev->mem = mem; | 293 | wdev->mem = mem; |
| 305 | 294 | ||
| 306 | if (cpu_is_omap16xx()) { | 295 | wdev->ick = clk_get(&pdev->dev, "ick"); |
| 307 | wdev->armwdt_ck = clk_get(&pdev->dev, "armwdt_ck"); | 296 | if (IS_ERR(wdev->ick)) { |
| 308 | if (IS_ERR(wdev->armwdt_ck)) { | 297 | ret = PTR_ERR(wdev->ick); |
| 309 | ret = PTR_ERR(wdev->armwdt_ck); | 298 | wdev->ick = NULL; |
| 310 | wdev->armwdt_ck = NULL; | 299 | goto err_clk; |
| 311 | goto err_clk; | ||
| 312 | } | ||
| 313 | } | 300 | } |
| 314 | 301 | wdev->fck = clk_get(&pdev->dev, "fck"); | |
| 315 | if (cpu_is_omap24xx()) { | 302 | if (IS_ERR(wdev->fck)) { |
| 316 | wdev->mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick"); | 303 | ret = PTR_ERR(wdev->fck); |
| 317 | if (IS_ERR(wdev->mpu_wdt_ick)) { | 304 | wdev->fck = NULL; |
| 318 | ret = PTR_ERR(wdev->mpu_wdt_ick); | 305 | goto err_clk; |
| 319 | wdev->mpu_wdt_ick = NULL; | ||
| 320 | goto err_clk; | ||
| 321 | } | ||
| 322 | wdev->mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck"); | ||
| 323 | if (IS_ERR(wdev->mpu_wdt_fck)) { | ||
| 324 | ret = PTR_ERR(wdev->mpu_wdt_fck); | ||
| 325 | wdev->mpu_wdt_fck = NULL; | ||
| 326 | goto err_clk; | ||
| 327 | } | ||
| 328 | } | 306 | } |
| 329 | 307 | ||
| 330 | if (cpu_is_omap34xx()) { | ||
| 331 | wdev->mpu_wdt_ick = clk_get(&pdev->dev, "wdt2_ick"); | ||
| 332 | if (IS_ERR(wdev->mpu_wdt_ick)) { | ||
| 333 | ret = PTR_ERR(wdev->mpu_wdt_ick); | ||
| 334 | wdev->mpu_wdt_ick = NULL; | ||
| 335 | goto err_clk; | ||
| 336 | } | ||
| 337 | wdev->mpu_wdt_fck = clk_get(&pdev->dev, "wdt2_fck"); | ||
| 338 | if (IS_ERR(wdev->mpu_wdt_fck)) { | ||
| 339 | ret = PTR_ERR(wdev->mpu_wdt_fck); | ||
| 340 | wdev->mpu_wdt_fck = NULL; | ||
| 341 | goto err_clk; | ||
| 342 | } | ||
| 343 | } | ||
| 344 | wdev->base = ioremap(res->start, res->end - res->start + 1); | 308 | wdev->base = ioremap(res->start, res->end - res->start + 1); |
| 345 | if (!wdev->base) { | 309 | if (!wdev->base) { |
| 346 | ret = -ENOMEM; | 310 | ret = -ENOMEM; |
| @@ -380,12 +344,10 @@ err_ioremap: | |||
| 380 | wdev->base = NULL; | 344 | wdev->base = NULL; |
| 381 | 345 | ||
| 382 | err_clk: | 346 | err_clk: |
| 383 | if (wdev->armwdt_ck) | 347 | if (wdev->ick) |
| 384 | clk_put(wdev->armwdt_ck); | 348 | clk_put(wdev->ick); |
| 385 | if (wdev->mpu_wdt_ick) | 349 | if (wdev->fck) |
| 386 | clk_put(wdev->mpu_wdt_ick); | 350 | clk_put(wdev->fck); |
| 387 | if (wdev->mpu_wdt_fck) | ||
| 388 | clk_put(wdev->mpu_wdt_fck); | ||
| 389 | kfree(wdev); | 351 | kfree(wdev); |
| 390 | 352 | ||
| 391 | err_kzalloc: | 353 | err_kzalloc: |
| @@ -417,20 +379,8 @@ static int omap_wdt_remove(struct platform_device *pdev) | |||
| 417 | release_mem_region(res->start, res->end - res->start + 1); | 379 | release_mem_region(res->start, res->end - res->start + 1); |
| 418 | platform_set_drvdata(pdev, NULL); | 380 | platform_set_drvdata(pdev, NULL); |
| 419 | 381 | ||
| 420 | if (wdev->armwdt_ck) { | 382 | clk_put(wdev->ick); |
| 421 | clk_put(wdev->armwdt_ck); | 383 | clk_put(wdev->fck); |
| 422 | wdev->armwdt_ck = NULL; | ||
| 423 | } | ||
| 424 | |||
| 425 | if (wdev->mpu_wdt_ick) { | ||
| 426 | clk_put(wdev->mpu_wdt_ick); | ||
| 427 | wdev->mpu_wdt_ick = NULL; | ||
| 428 | } | ||
| 429 | |||
| 430 | if (wdev->mpu_wdt_fck) { | ||
| 431 | clk_put(wdev->mpu_wdt_fck); | ||
| 432 | wdev->mpu_wdt_fck = NULL; | ||
| 433 | } | ||
| 434 | iounmap(wdev->base); | 384 | iounmap(wdev->base); |
| 435 | 385 | ||
| 436 | kfree(wdev); | 386 | kfree(wdev); |
diff --git a/drivers/watchdog/orion5x_wdt.c b/drivers/watchdog/orion5x_wdt.c index 14a339f58b6a..b64ae1a17832 100644 --- a/drivers/watchdog/orion5x_wdt.c +++ b/drivers/watchdog/orion5x_wdt.c | |||
| @@ -29,6 +29,7 @@ | |||
| 29 | #define WDT_EN 0x0010 | 29 | #define WDT_EN 0x0010 |
| 30 | #define WDT_VAL (TIMER_VIRT_BASE + 0x0024) | 30 | #define WDT_VAL (TIMER_VIRT_BASE + 0x0024) |
| 31 | 31 | ||
| 32 | #define ORION5X_TCLK 166666667 | ||
| 32 | #define WDT_MAX_DURATION (0xffffffff / ORION5X_TCLK) | 33 | #define WDT_MAX_DURATION (0xffffffff / ORION5X_TCLK) |
| 33 | #define WDT_IN_USE 0 | 34 | #define WDT_IN_USE 0 |
| 34 | #define WDT_OK_TO_CLOSE 1 | 35 | #define WDT_OK_TO_CLOSE 1 |
diff --git a/drivers/watchdog/rc32434_wdt.c b/drivers/watchdog/rc32434_wdt.c index 57027f4653ce..f3553fa40b17 100644 --- a/drivers/watchdog/rc32434_wdt.c +++ b/drivers/watchdog/rc32434_wdt.c | |||
| @@ -34,104 +34,89 @@ | |||
| 34 | #include <asm/time.h> | 34 | #include <asm/time.h> |
| 35 | #include <asm/mach-rc32434/integ.h> | 35 | #include <asm/mach-rc32434/integ.h> |
| 36 | 36 | ||
| 37 | #define MAX_TIMEOUT 20 | 37 | #define VERSION "0.4" |
| 38 | #define RC32434_WDT_INTERVAL (15 * HZ) | ||
| 39 | |||
| 40 | #define VERSION "0.2" | ||
| 41 | 38 | ||
| 42 | static struct { | 39 | static struct { |
| 43 | struct completion stop; | ||
| 44 | int running; | ||
| 45 | struct timer_list timer; | ||
| 46 | int queue; | ||
| 47 | int default_ticks; | ||
| 48 | unsigned long inuse; | 40 | unsigned long inuse; |
| 49 | } rc32434_wdt_device; | 41 | } rc32434_wdt_device; |
| 50 | 42 | ||
| 51 | static struct integ __iomem *wdt_reg; | 43 | static struct integ __iomem *wdt_reg; |
| 52 | static int ticks = 100 * HZ; | ||
| 53 | 44 | ||
| 54 | static int expect_close; | 45 | static int expect_close; |
| 55 | static int timeout; | 46 | |
| 47 | /* Board internal clock speed in Hz, | ||
| 48 | * the watchdog timer ticks at. */ | ||
| 49 | extern unsigned int idt_cpu_freq; | ||
| 50 | |||
| 51 | /* translate wtcompare value to seconds and vice versa */ | ||
| 52 | #define WTCOMP2SEC(x) (x / idt_cpu_freq) | ||
| 53 | #define SEC2WTCOMP(x) (x * idt_cpu_freq) | ||
| 54 | |||
| 55 | /* Use a default timeout of 20s. This should be | ||
| 56 | * safe for CPU clock speeds up to 400MHz, as | ||
| 57 | * ((2 ^ 32) - 1) / (400MHz / 2) = 21s. */ | ||
| 58 | #define WATCHDOG_TIMEOUT 20 | ||
| 59 | |||
| 60 | static int timeout = WATCHDOG_TIMEOUT; | ||
| 56 | 61 | ||
| 57 | static int nowayout = WATCHDOG_NOWAYOUT; | 62 | static int nowayout = WATCHDOG_NOWAYOUT; |
| 58 | module_param(nowayout, int, 0); | 63 | module_param(nowayout, int, 0); |
| 59 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | 64 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" |
| 60 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | 65 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); |
| 61 | 66 | ||
| 67 | /* apply or and nand masks to data read from addr and write back */ | ||
| 68 | #define SET_BITS(addr, or, nand) \ | ||
| 69 | writel((readl(&addr) | or) & ~nand, &addr) | ||
| 62 | 70 | ||
| 63 | static void rc32434_wdt_start(void) | 71 | static void rc32434_wdt_start(void) |
| 64 | { | 72 | { |
| 65 | u32 val; | 73 | u32 or, nand; |
| 66 | |||
| 67 | if (!rc32434_wdt_device.inuse) { | ||
| 68 | writel(0, &wdt_reg->wtcount); | ||
| 69 | 74 | ||
| 70 | val = RC32434_ERR_WRE; | 75 | /* zero the counter before enabling */ |
| 71 | writel(readl(&wdt_reg->errcs) | val, &wdt_reg->errcs); | 76 | writel(0, &wdt_reg->wtcount); |
| 72 | 77 | ||
| 73 | val = RC32434_WTC_EN; | 78 | /* don't generate a non-maskable interrupt, |
| 74 | writel(readl(&wdt_reg->wtc) | val, &wdt_reg->wtc); | 79 | * do a warm reset instead */ |
| 75 | } | 80 | nand = 1 << RC32434_ERR_WNE; |
| 76 | rc32434_wdt_device.running++; | 81 | or = 1 << RC32434_ERR_WRE; |
| 77 | } | ||
| 78 | 82 | ||
| 79 | static void rc32434_wdt_stop(void) | 83 | /* reset the ERRCS timeout bit in case it's set */ |
| 80 | { | 84 | nand |= 1 << RC32434_ERR_WTO; |
| 81 | u32 val; | ||
| 82 | 85 | ||
| 83 | if (rc32434_wdt_device.running) { | 86 | SET_BITS(wdt_reg->errcs, or, nand); |
| 84 | 87 | ||
| 85 | val = ~RC32434_WTC_EN; | 88 | /* reset WTC timeout bit and enable WDT */ |
| 86 | writel(readl(&wdt_reg->wtc) & val, &wdt_reg->wtc); | 89 | nand = 1 << RC32434_WTC_TO; |
| 90 | or = 1 << RC32434_WTC_EN; | ||
| 87 | 91 | ||
| 88 | val = ~RC32434_ERR_WRE; | 92 | SET_BITS(wdt_reg->wtc, or, nand); |
| 89 | writel(readl(&wdt_reg->errcs) & val, &wdt_reg->errcs); | 93 | } |
| 90 | 94 | ||
| 91 | rc32434_wdt_device.running = 0; | 95 | static void rc32434_wdt_stop(void) |
| 92 | } | 96 | { |
| 97 | /* Disable WDT */ | ||
| 98 | SET_BITS(wdt_reg->wtc, 0, 1 << RC32434_WTC_EN); | ||
| 93 | } | 99 | } |
| 94 | 100 | ||
| 95 | static void rc32434_wdt_set(int new_timeout) | 101 | static int rc32434_wdt_set(int new_timeout) |
| 96 | { | 102 | { |
| 97 | u32 cmp = new_timeout * HZ; | 103 | int max_to = WTCOMP2SEC((u32)-1); |
| 98 | u32 state, val; | ||
| 99 | 104 | ||
| 105 | if (new_timeout < 0 || new_timeout > max_to) { | ||
| 106 | printk(KERN_ERR KBUILD_MODNAME | ||
| 107 | ": timeout value must be between 0 and %d", | ||
| 108 | max_to); | ||
| 109 | return -EINVAL; | ||
| 110 | } | ||
| 100 | timeout = new_timeout; | 111 | timeout = new_timeout; |
| 101 | /* | 112 | writel(SEC2WTCOMP(timeout), &wdt_reg->wtcompare); |
| 102 | * store and disable WTC | ||
| 103 | */ | ||
| 104 | state = (u32)(readl(&wdt_reg->wtc) & RC32434_WTC_EN); | ||
| 105 | val = ~RC32434_WTC_EN; | ||
| 106 | writel(readl(&wdt_reg->wtc) & val, &wdt_reg->wtc); | ||
| 107 | |||
| 108 | writel(0, &wdt_reg->wtcount); | ||
| 109 | writel(cmp, &wdt_reg->wtcompare); | ||
| 110 | |||
| 111 | /* | ||
| 112 | * restore WTC | ||
| 113 | */ | ||
| 114 | |||
| 115 | writel(readl(&wdt_reg->wtc) | state, &wdt_reg); | ||
| 116 | } | ||
| 117 | 113 | ||
| 118 | static void rc32434_wdt_reset(void) | 114 | return 0; |
| 119 | { | ||
| 120 | ticks = rc32434_wdt_device.default_ticks; | ||
| 121 | } | 115 | } |
| 122 | 116 | ||
| 123 | static void rc32434_wdt_update(unsigned long unused) | 117 | static void rc32434_wdt_ping(void) |
| 124 | { | 118 | { |
| 125 | if (rc32434_wdt_device.running) | ||
| 126 | ticks--; | ||
| 127 | |||
| 128 | writel(0, &wdt_reg->wtcount); | 119 | writel(0, &wdt_reg->wtcount); |
| 129 | |||
| 130 | if (rc32434_wdt_device.queue && ticks) | ||
| 131 | mod_timer(&rc32434_wdt_device.timer, | ||
| 132 | jiffies + RC32434_WDT_INTERVAL); | ||
| 133 | else | ||
| 134 | complete(&rc32434_wdt_device.stop); | ||
| 135 | } | 120 | } |
| 136 | 121 | ||
| 137 | static int rc32434_wdt_open(struct inode *inode, struct file *file) | 122 | static int rc32434_wdt_open(struct inode *inode, struct file *file) |
| @@ -142,19 +127,23 @@ static int rc32434_wdt_open(struct inode *inode, struct file *file) | |||
| 142 | if (nowayout) | 127 | if (nowayout) |
| 143 | __module_get(THIS_MODULE); | 128 | __module_get(THIS_MODULE); |
| 144 | 129 | ||
| 130 | rc32434_wdt_start(); | ||
| 131 | rc32434_wdt_ping(); | ||
| 132 | |||
| 145 | return nonseekable_open(inode, file); | 133 | return nonseekable_open(inode, file); |
| 146 | } | 134 | } |
| 147 | 135 | ||
| 148 | static int rc32434_wdt_release(struct inode *inode, struct file *file) | 136 | static int rc32434_wdt_release(struct inode *inode, struct file *file) |
| 149 | { | 137 | { |
| 150 | if (expect_close && nowayout == 0) { | 138 | if (expect_close == 42) { |
| 151 | rc32434_wdt_stop(); | 139 | rc32434_wdt_stop(); |
| 152 | printk(KERN_INFO KBUILD_MODNAME ": disabling watchdog timer\n"); | 140 | printk(KERN_INFO KBUILD_MODNAME ": disabling watchdog timer\n"); |
| 153 | module_put(THIS_MODULE); | 141 | module_put(THIS_MODULE); |
| 154 | } else | 142 | } else { |
| 155 | printk(KERN_CRIT KBUILD_MODNAME | 143 | printk(KERN_CRIT KBUILD_MODNAME |
| 156 | ": device closed unexpectedly. WDT will not stop !\n"); | 144 | ": device closed unexpectedly. WDT will not stop !\n"); |
| 157 | 145 | rc32434_wdt_ping(); | |
| 146 | } | ||
| 158 | clear_bit(0, &rc32434_wdt_device.inuse); | 147 | clear_bit(0, &rc32434_wdt_device.inuse); |
| 159 | return 0; | 148 | return 0; |
| 160 | } | 149 | } |
| @@ -174,10 +163,10 @@ static ssize_t rc32434_wdt_write(struct file *file, const char *data, | |||
| 174 | if (get_user(c, data + i)) | 163 | if (get_user(c, data + i)) |
| 175 | return -EFAULT; | 164 | return -EFAULT; |
| 176 | if (c == 'V') | 165 | if (c == 'V') |
| 177 | expect_close = 1; | 166 | expect_close = 42; |
| 178 | } | 167 | } |
| 179 | } | 168 | } |
| 180 | rc32434_wdt_update(0); | 169 | rc32434_wdt_ping(); |
| 181 | return len; | 170 | return len; |
| 182 | } | 171 | } |
| 183 | return 0; | 172 | return 0; |
| @@ -197,11 +186,11 @@ static long rc32434_wdt_ioctl(struct file *file, unsigned int cmd, | |||
| 197 | }; | 186 | }; |
| 198 | switch (cmd) { | 187 | switch (cmd) { |
| 199 | case WDIOC_KEEPALIVE: | 188 | case WDIOC_KEEPALIVE: |
| 200 | rc32434_wdt_reset(); | 189 | rc32434_wdt_ping(); |
| 201 | break; | 190 | break; |
| 202 | case WDIOC_GETSTATUS: | 191 | case WDIOC_GETSTATUS: |
| 203 | case WDIOC_GETBOOTSTATUS: | 192 | case WDIOC_GETBOOTSTATUS: |
| 204 | value = readl(&wdt_reg->wtcount); | 193 | value = 0; |
| 205 | if (copy_to_user(argp, &value, sizeof(int))) | 194 | if (copy_to_user(argp, &value, sizeof(int))) |
| 206 | return -EFAULT; | 195 | return -EFAULT; |
| 207 | break; | 196 | break; |
| @@ -218,6 +207,7 @@ static long rc32434_wdt_ioctl(struct file *file, unsigned int cmd, | |||
| 218 | break; | 207 | break; |
| 219 | case WDIOS_DISABLECARD: | 208 | case WDIOS_DISABLECARD: |
| 220 | rc32434_wdt_stop(); | 209 | rc32434_wdt_stop(); |
| 210 | break; | ||
| 221 | default: | 211 | default: |
| 222 | return -EINVAL; | 212 | return -EINVAL; |
| 223 | } | 213 | } |
| @@ -225,11 +215,9 @@ static long rc32434_wdt_ioctl(struct file *file, unsigned int cmd, | |||
| 225 | case WDIOC_SETTIMEOUT: | 215 | case WDIOC_SETTIMEOUT: |
| 226 | if (copy_from_user(&new_timeout, argp, sizeof(int))) | 216 | if (copy_from_user(&new_timeout, argp, sizeof(int))) |
| 227 | return -EFAULT; | 217 | return -EFAULT; |
| 228 | if (new_timeout < 1) | 218 | if (rc32434_wdt_set(new_timeout)) |
| 229 | return -EINVAL; | 219 | return -EINVAL; |
| 230 | if (new_timeout > MAX_TIMEOUT) | 220 | /* Fall through */ |
| 231 | return -EINVAL; | ||
| 232 | rc32434_wdt_set(new_timeout); | ||
| 233 | case WDIOC_GETTIMEOUT: | 221 | case WDIOC_GETTIMEOUT: |
| 234 | return copy_to_user(argp, &timeout, sizeof(int)); | 222 | return copy_to_user(argp, &timeout, sizeof(int)); |
| 235 | default: | 223 | default: |
| @@ -254,15 +242,15 @@ static struct miscdevice rc32434_wdt_miscdev = { | |||
| 254 | .fops = &rc32434_wdt_fops, | 242 | .fops = &rc32434_wdt_fops, |
| 255 | }; | 243 | }; |
| 256 | 244 | ||
| 257 | static char banner[] = KERN_INFO KBUILD_MODNAME | 245 | static char banner[] __devinitdata = KERN_INFO KBUILD_MODNAME |
| 258 | ": Watchdog Timer version " VERSION ", timer margin: %d sec\n"; | 246 | ": Watchdog Timer version " VERSION ", timer margin: %d sec\n"; |
| 259 | 247 | ||
| 260 | static int rc32434_wdt_probe(struct platform_device *pdev) | 248 | static int __devinit rc32434_wdt_probe(struct platform_device *pdev) |
| 261 | { | 249 | { |
| 262 | int ret; | 250 | int ret; |
| 263 | struct resource *r; | 251 | struct resource *r; |
| 264 | 252 | ||
| 265 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rb500_wdt_res"); | 253 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rb532_wdt_res"); |
| 266 | if (!r) { | 254 | if (!r) { |
| 267 | printk(KERN_ERR KBUILD_MODNAME | 255 | printk(KERN_ERR KBUILD_MODNAME |
| 268 | "failed to retrieve resources\n"); | 256 | "failed to retrieve resources\n"); |
| @@ -277,24 +265,12 @@ static int rc32434_wdt_probe(struct platform_device *pdev) | |||
| 277 | } | 265 | } |
| 278 | 266 | ||
| 279 | ret = misc_register(&rc32434_wdt_miscdev); | 267 | ret = misc_register(&rc32434_wdt_miscdev); |
| 280 | |||
| 281 | if (ret < 0) { | 268 | if (ret < 0) { |
| 282 | printk(KERN_ERR KBUILD_MODNAME | 269 | printk(KERN_ERR KBUILD_MODNAME |
| 283 | "failed to register watchdog device\n"); | 270 | "failed to register watchdog device\n"); |
| 284 | goto unmap; | 271 | goto unmap; |
| 285 | } | 272 | } |
| 286 | 273 | ||
| 287 | init_completion(&rc32434_wdt_device.stop); | ||
| 288 | rc32434_wdt_device.queue = 0; | ||
| 289 | |||
| 290 | clear_bit(0, &rc32434_wdt_device.inuse); | ||
| 291 | |||
| 292 | setup_timer(&rc32434_wdt_device.timer, rc32434_wdt_update, 0L); | ||
| 293 | |||
| 294 | rc32434_wdt_device.default_ticks = ticks; | ||
| 295 | |||
| 296 | rc32434_wdt_start(); | ||
| 297 | |||
| 298 | printk(banner, timeout); | 274 | printk(banner, timeout); |
| 299 | 275 | ||
| 300 | return 0; | 276 | return 0; |
| @@ -304,23 +280,17 @@ unmap: | |||
| 304 | return ret; | 280 | return ret; |
| 305 | } | 281 | } |
| 306 | 282 | ||
| 307 | static int rc32434_wdt_remove(struct platform_device *pdev) | 283 | static int __devexit rc32434_wdt_remove(struct platform_device *pdev) |
| 308 | { | 284 | { |
| 309 | if (rc32434_wdt_device.queue) { | ||
| 310 | rc32434_wdt_device.queue = 0; | ||
| 311 | wait_for_completion(&rc32434_wdt_device.stop); | ||
| 312 | } | ||
| 313 | misc_deregister(&rc32434_wdt_miscdev); | 285 | misc_deregister(&rc32434_wdt_miscdev); |
| 314 | |||
| 315 | iounmap(wdt_reg); | 286 | iounmap(wdt_reg); |
| 316 | |||
| 317 | return 0; | 287 | return 0; |
| 318 | } | 288 | } |
| 319 | 289 | ||
| 320 | static struct platform_driver rc32434_wdt = { | 290 | static struct platform_driver rc32434_wdt = { |
| 321 | .probe = rc32434_wdt_probe, | 291 | .probe = rc32434_wdt_probe, |
| 322 | .remove = rc32434_wdt_remove, | 292 | .remove = __devexit_p(rc32434_wdt_remove), |
| 323 | .driver = { | 293 | .driver = { |
| 324 | .name = "rc32434_wdt", | 294 | .name = "rc32434_wdt", |
| 325 | } | 295 | } |
| 326 | }; | 296 | }; |
diff --git a/drivers/watchdog/sa1100_wdt.c b/drivers/watchdog/sa1100_wdt.c index e19b45794717..4b84f296d30c 100644 --- a/drivers/watchdog/sa1100_wdt.c +++ b/drivers/watchdog/sa1100_wdt.c | |||
| @@ -30,7 +30,7 @@ | |||
| 30 | #include <linux/timex.h> | 30 | #include <linux/timex.h> |
| 31 | 31 | ||
| 32 | #ifdef CONFIG_ARCH_PXA | 32 | #ifdef CONFIG_ARCH_PXA |
| 33 | #include <mach/pxa-regs.h> | 33 | #include <mach/regs-ost.h> |
| 34 | #endif | 34 | #endif |
| 35 | 35 | ||
| 36 | #include <mach/reset.h> | 36 | #include <mach/reset.h> |
| @@ -443,7 +443,7 @@ static struct kiocb *__aio_get_req(struct kioctx *ctx) | |||
| 443 | req->private = NULL; | 443 | req->private = NULL; |
| 444 | req->ki_iovec = NULL; | 444 | req->ki_iovec = NULL; |
| 445 | INIT_LIST_HEAD(&req->ki_run_list); | 445 | INIT_LIST_HEAD(&req->ki_run_list); |
| 446 | req->ki_eventfd = ERR_PTR(-EINVAL); | 446 | req->ki_eventfd = NULL; |
| 447 | 447 | ||
| 448 | /* Check if the completion queue has enough free space to | 448 | /* Check if the completion queue has enough free space to |
| 449 | * accept an event from this io. | 449 | * accept an event from this io. |
| @@ -485,8 +485,6 @@ static inline void really_put_req(struct kioctx *ctx, struct kiocb *req) | |||
| 485 | { | 485 | { |
| 486 | assert_spin_locked(&ctx->ctx_lock); | 486 | assert_spin_locked(&ctx->ctx_lock); |
| 487 | 487 | ||
| 488 | if (!IS_ERR(req->ki_eventfd)) | ||
| 489 | fput(req->ki_eventfd); | ||
| 490 | if (req->ki_dtor) | 488 | if (req->ki_dtor) |
| 491 | req->ki_dtor(req); | 489 | req->ki_dtor(req); |
| 492 | if (req->ki_iovec != &req->ki_inline_vec) | 490 | if (req->ki_iovec != &req->ki_inline_vec) |
| @@ -508,8 +506,11 @@ static void aio_fput_routine(struct work_struct *data) | |||
| 508 | list_del(&req->ki_list); | 506 | list_del(&req->ki_list); |
| 509 | spin_unlock_irq(&fput_lock); | 507 | spin_unlock_irq(&fput_lock); |
| 510 | 508 | ||
| 511 | /* Complete the fput */ | 509 | /* Complete the fput(s) */ |
| 512 | __fput(req->ki_filp); | 510 | if (req->ki_filp != NULL) |
| 511 | __fput(req->ki_filp); | ||
| 512 | if (req->ki_eventfd != NULL) | ||
| 513 | __fput(req->ki_eventfd); | ||
| 513 | 514 | ||
| 514 | /* Link the iocb into the context's free list */ | 515 | /* Link the iocb into the context's free list */ |
| 515 | spin_lock_irq(&ctx->ctx_lock); | 516 | spin_lock_irq(&ctx->ctx_lock); |
| @@ -527,12 +528,14 @@ static void aio_fput_routine(struct work_struct *data) | |||
| 527 | */ | 528 | */ |
| 528 | static int __aio_put_req(struct kioctx *ctx, struct kiocb *req) | 529 | static int __aio_put_req(struct kioctx *ctx, struct kiocb *req) |
| 529 | { | 530 | { |
| 531 | int schedule_putreq = 0; | ||
| 532 | |||
| 530 | dprintk(KERN_DEBUG "aio_put(%p): f_count=%ld\n", | 533 | dprintk(KERN_DEBUG "aio_put(%p): f_count=%ld\n", |
| 531 | req, atomic_long_read(&req->ki_filp->f_count)); | 534 | req, atomic_long_read(&req->ki_filp->f_count)); |
| 532 | 535 | ||
| 533 | assert_spin_locked(&ctx->ctx_lock); | 536 | assert_spin_locked(&ctx->ctx_lock); |
| 534 | 537 | ||
| 535 | req->ki_users --; | 538 | req->ki_users--; |
| 536 | BUG_ON(req->ki_users < 0); | 539 | BUG_ON(req->ki_users < 0); |
| 537 | if (likely(req->ki_users)) | 540 | if (likely(req->ki_users)) |
| 538 | return 0; | 541 | return 0; |
| @@ -540,10 +543,23 @@ static int __aio_put_req(struct kioctx *ctx, struct kiocb *req) | |||
| 540 | req->ki_cancel = NULL; | 543 | req->ki_cancel = NULL; |
| 541 | req->ki_retry = NULL; | 544 | req->ki_retry = NULL; |
| 542 | 545 | ||
| 543 | /* Must be done under the lock to serialise against cancellation. | 546 | /* |
| 544 | * Call this aio_fput as it duplicates fput via the fput_work. | 547 | * Try to optimize the aio and eventfd file* puts, by avoiding to |
| 548 | * schedule work in case it is not __fput() time. In normal cases, | ||
| 549 | * we would not be holding the last reference to the file*, so | ||
| 550 | * this function will be executed w/out any aio kthread wakeup. | ||
| 545 | */ | 551 | */ |
| 546 | if (unlikely(atomic_long_dec_and_test(&req->ki_filp->f_count))) { | 552 | if (unlikely(atomic_long_dec_and_test(&req->ki_filp->f_count))) |
| 553 | schedule_putreq++; | ||
| 554 | else | ||
| 555 | req->ki_filp = NULL; | ||
| 556 | if (req->ki_eventfd != NULL) { | ||
| 557 | if (unlikely(atomic_long_dec_and_test(&req->ki_eventfd->f_count))) | ||
| 558 | schedule_putreq++; | ||
| 559 | else | ||
| 560 | req->ki_eventfd = NULL; | ||
| 561 | } | ||
| 562 | if (unlikely(schedule_putreq)) { | ||
| 547 | get_ioctx(ctx); | 563 | get_ioctx(ctx); |
| 548 | spin_lock(&fput_lock); | 564 | spin_lock(&fput_lock); |
| 549 | list_add(&req->ki_list, &fput_head); | 565 | list_add(&req->ki_list, &fput_head); |
| @@ -571,7 +587,7 @@ int aio_put_req(struct kiocb *req) | |||
| 571 | static struct kioctx *lookup_ioctx(unsigned long ctx_id) | 587 | static struct kioctx *lookup_ioctx(unsigned long ctx_id) |
| 572 | { | 588 | { |
| 573 | struct mm_struct *mm = current->mm; | 589 | struct mm_struct *mm = current->mm; |
| 574 | struct kioctx *ctx = NULL; | 590 | struct kioctx *ctx, *ret = NULL; |
| 575 | struct hlist_node *n; | 591 | struct hlist_node *n; |
| 576 | 592 | ||
| 577 | rcu_read_lock(); | 593 | rcu_read_lock(); |
| @@ -579,12 +595,13 @@ static struct kioctx *lookup_ioctx(unsigned long ctx_id) | |||
| 579 | hlist_for_each_entry_rcu(ctx, n, &mm->ioctx_list, list) { | 595 | hlist_for_each_entry_rcu(ctx, n, &mm->ioctx_list, list) { |
| 580 | if (ctx->user_id == ctx_id && !ctx->dead) { | 596 | if (ctx->user_id == ctx_id && !ctx->dead) { |
| 581 | get_ioctx(ctx); | 597 | get_ioctx(ctx); |
| 598 | ret = ctx; | ||
| 582 | break; | 599 | break; |
| 583 | } | 600 | } |
| 584 | } | 601 | } |
| 585 | 602 | ||
| 586 | rcu_read_unlock(); | 603 | rcu_read_unlock(); |
| 587 | return ctx; | 604 | return ret; |
| 588 | } | 605 | } |
| 589 | 606 | ||
| 590 | /* | 607 | /* |
| @@ -1009,7 +1026,7 @@ int aio_complete(struct kiocb *iocb, long res, long res2) | |||
| 1009 | * eventfd. The eventfd_signal() function is safe to be called | 1026 | * eventfd. The eventfd_signal() function is safe to be called |
| 1010 | * from IRQ context. | 1027 | * from IRQ context. |
| 1011 | */ | 1028 | */ |
| 1012 | if (!IS_ERR(iocb->ki_eventfd)) | 1029 | if (iocb->ki_eventfd != NULL) |
| 1013 | eventfd_signal(iocb->ki_eventfd, 1); | 1030 | eventfd_signal(iocb->ki_eventfd, 1); |
| 1014 | 1031 | ||
| 1015 | put_rq: | 1032 | put_rq: |
| @@ -1608,6 +1625,7 @@ static int io_submit_one(struct kioctx *ctx, struct iocb __user *user_iocb, | |||
| 1608 | req->ki_eventfd = eventfd_fget((int) iocb->aio_resfd); | 1625 | req->ki_eventfd = eventfd_fget((int) iocb->aio_resfd); |
| 1609 | if (IS_ERR(req->ki_eventfd)) { | 1626 | if (IS_ERR(req->ki_eventfd)) { |
| 1610 | ret = PTR_ERR(req->ki_eventfd); | 1627 | ret = PTR_ERR(req->ki_eventfd); |
| 1628 | req->ki_eventfd = NULL; | ||
| 1611 | goto out_put_req; | 1629 | goto out_put_req; |
| 1612 | } | 1630 | } |
| 1613 | } | 1631 | } |
diff --git a/fs/bio-integrity.c b/fs/bio-integrity.c index 549b0144da11..fe2b1aa2464e 100644 --- a/fs/bio-integrity.c +++ b/fs/bio-integrity.c | |||
| @@ -685,19 +685,20 @@ EXPORT_SYMBOL(bio_integrity_split); | |||
| 685 | * bio_integrity_clone - Callback for cloning bios with integrity metadata | 685 | * bio_integrity_clone - Callback for cloning bios with integrity metadata |
| 686 | * @bio: New bio | 686 | * @bio: New bio |
| 687 | * @bio_src: Original bio | 687 | * @bio_src: Original bio |
| 688 | * @gfp_mask: Memory allocation mask | ||
| 688 | * @bs: bio_set to allocate bip from | 689 | * @bs: bio_set to allocate bip from |
| 689 | * | 690 | * |
| 690 | * Description: Called to allocate a bip when cloning a bio | 691 | * Description: Called to allocate a bip when cloning a bio |
| 691 | */ | 692 | */ |
| 692 | int bio_integrity_clone(struct bio *bio, struct bio *bio_src, | 693 | int bio_integrity_clone(struct bio *bio, struct bio *bio_src, |
| 693 | struct bio_set *bs) | 694 | gfp_t gfp_mask, struct bio_set *bs) |
| 694 | { | 695 | { |
| 695 | struct bio_integrity_payload *bip_src = bio_src->bi_integrity; | 696 | struct bio_integrity_payload *bip_src = bio_src->bi_integrity; |
| 696 | struct bio_integrity_payload *bip; | 697 | struct bio_integrity_payload *bip; |
| 697 | 698 | ||
| 698 | BUG_ON(bip_src == NULL); | 699 | BUG_ON(bip_src == NULL); |
| 699 | 700 | ||
| 700 | bip = bio_integrity_alloc_bioset(bio, GFP_NOIO, bip_src->bip_vcnt, bs); | 701 | bip = bio_integrity_alloc_bioset(bio, gfp_mask, bip_src->bip_vcnt, bs); |
| 701 | 702 | ||
| 702 | if (bip == NULL) | 703 | if (bip == NULL) |
| 703 | return -EIO; | 704 | return -EIO; |
| @@ -463,10 +463,12 @@ struct bio *bio_clone(struct bio *bio, gfp_t gfp_mask) | |||
| 463 | if (bio_integrity(bio)) { | 463 | if (bio_integrity(bio)) { |
| 464 | int ret; | 464 | int ret; |
| 465 | 465 | ||
| 466 | ret = bio_integrity_clone(b, bio, fs_bio_set); | 466 | ret = bio_integrity_clone(b, bio, gfp_mask, fs_bio_set); |
| 467 | 467 | ||
| 468 | if (ret < 0) | 468 | if (ret < 0) { |
| 469 | bio_put(b); | ||
| 469 | return NULL; | 470 | return NULL; |
| 471 | } | ||
| 470 | } | 472 | } |
| 471 | 473 | ||
| 472 | return b; | 474 | return b; |
diff --git a/fs/btrfs/ctree.c b/fs/btrfs/ctree.c index 42491d728e99..37f31b5529aa 100644 --- a/fs/btrfs/ctree.c +++ b/fs/btrfs/ctree.c | |||
| @@ -277,7 +277,7 @@ static noinline int __btrfs_cow_block(struct btrfs_trans_handle *trans, | |||
| 277 | if (*cow_ret == buf) | 277 | if (*cow_ret == buf) |
| 278 | unlock_orig = 1; | 278 | unlock_orig = 1; |
| 279 | 279 | ||
| 280 | WARN_ON(!btrfs_tree_locked(buf)); | 280 | btrfs_assert_tree_locked(buf); |
| 281 | 281 | ||
| 282 | if (parent) | 282 | if (parent) |
| 283 | parent_start = parent->start; | 283 | parent_start = parent->start; |
| @@ -2365,7 +2365,7 @@ static int push_leaf_right(struct btrfs_trans_handle *trans, struct btrfs_root | |||
| 2365 | if (slot >= btrfs_header_nritems(upper) - 1) | 2365 | if (slot >= btrfs_header_nritems(upper) - 1) |
| 2366 | return 1; | 2366 | return 1; |
| 2367 | 2367 | ||
| 2368 | WARN_ON(!btrfs_tree_locked(path->nodes[1])); | 2368 | btrfs_assert_tree_locked(path->nodes[1]); |
| 2369 | 2369 | ||
| 2370 | right = read_node_slot(root, upper, slot + 1); | 2370 | right = read_node_slot(root, upper, slot + 1); |
| 2371 | btrfs_tree_lock(right); | 2371 | btrfs_tree_lock(right); |
| @@ -2562,7 +2562,7 @@ static int push_leaf_left(struct btrfs_trans_handle *trans, struct btrfs_root | |||
| 2562 | if (right_nritems == 0) | 2562 | if (right_nritems == 0) |
| 2563 | return 1; | 2563 | return 1; |
| 2564 | 2564 | ||
| 2565 | WARN_ON(!btrfs_tree_locked(path->nodes[1])); | 2565 | btrfs_assert_tree_locked(path->nodes[1]); |
| 2566 | 2566 | ||
| 2567 | left = read_node_slot(root, path->nodes[1], slot - 1); | 2567 | left = read_node_slot(root, path->nodes[1], slot - 1); |
| 2568 | btrfs_tree_lock(left); | 2568 | btrfs_tree_lock(left); |
| @@ -4101,7 +4101,7 @@ int btrfs_next_leaf(struct btrfs_root *root, struct btrfs_path *path) | |||
| 4101 | 4101 | ||
| 4102 | next = read_node_slot(root, c, slot); | 4102 | next = read_node_slot(root, c, slot); |
| 4103 | if (!path->skip_locking) { | 4103 | if (!path->skip_locking) { |
| 4104 | WARN_ON(!btrfs_tree_locked(c)); | 4104 | btrfs_assert_tree_locked(c); |
| 4105 | btrfs_tree_lock(next); | 4105 | btrfs_tree_lock(next); |
| 4106 | btrfs_set_lock_blocking(next); | 4106 | btrfs_set_lock_blocking(next); |
| 4107 | } | 4107 | } |
| @@ -4126,7 +4126,7 @@ int btrfs_next_leaf(struct btrfs_root *root, struct btrfs_path *path) | |||
| 4126 | reada_for_search(root, path, level, slot, 0); | 4126 | reada_for_search(root, path, level, slot, 0); |
| 4127 | next = read_node_slot(root, next, 0); | 4127 | next = read_node_slot(root, next, 0); |
| 4128 | if (!path->skip_locking) { | 4128 | if (!path->skip_locking) { |
| 4129 | WARN_ON(!btrfs_tree_locked(path->nodes[level])); | 4129 | btrfs_assert_tree_locked(path->nodes[level]); |
| 4130 | btrfs_tree_lock(next); | 4130 | btrfs_tree_lock(next); |
| 4131 | btrfs_set_lock_blocking(next); | 4131 | btrfs_set_lock_blocking(next); |
| 4132 | } | 4132 | } |
diff --git a/fs/btrfs/ctree.h b/fs/btrfs/ctree.h index 82491ba8fa40..5e1d4e30e9d8 100644 --- a/fs/btrfs/ctree.h +++ b/fs/btrfs/ctree.h | |||
| @@ -784,7 +784,14 @@ struct btrfs_fs_info { | |||
| 784 | struct list_head dirty_cowonly_roots; | 784 | struct list_head dirty_cowonly_roots; |
| 785 | 785 | ||
| 786 | struct btrfs_fs_devices *fs_devices; | 786 | struct btrfs_fs_devices *fs_devices; |
| 787 | |||
| 788 | /* | ||
| 789 | * the space_info list is almost entirely read only. It only changes | ||
| 790 | * when we add a new raid type to the FS, and that happens | ||
| 791 | * very rarely. RCU is used to protect it. | ||
| 792 | */ | ||
| 787 | struct list_head space_info; | 793 | struct list_head space_info; |
| 794 | |||
| 788 | spinlock_t delalloc_lock; | 795 | spinlock_t delalloc_lock; |
| 789 | spinlock_t new_trans_lock; | 796 | spinlock_t new_trans_lock; |
| 790 | u64 delalloc_bytes; | 797 | u64 delalloc_bytes; |
| @@ -1797,6 +1804,8 @@ int btrfs_cleanup_reloc_trees(struct btrfs_root *root); | |||
| 1797 | int btrfs_reloc_clone_csums(struct inode *inode, u64 file_pos, u64 len); | 1804 | int btrfs_reloc_clone_csums(struct inode *inode, u64 file_pos, u64 len); |
| 1798 | u64 btrfs_reduce_alloc_profile(struct btrfs_root *root, u64 flags); | 1805 | u64 btrfs_reduce_alloc_profile(struct btrfs_root *root, u64 flags); |
| 1799 | void btrfs_set_inode_space_info(struct btrfs_root *root, struct inode *ionde); | 1806 | void btrfs_set_inode_space_info(struct btrfs_root *root, struct inode *ionde); |
| 1807 | void btrfs_clear_space_info_full(struct btrfs_fs_info *info); | ||
| 1808 | |||
| 1800 | int btrfs_check_metadata_free_space(struct btrfs_root *root); | 1809 | int btrfs_check_metadata_free_space(struct btrfs_root *root); |
| 1801 | int btrfs_check_data_free_space(struct btrfs_root *root, struct inode *inode, | 1810 | int btrfs_check_data_free_space(struct btrfs_root *root, struct inode *inode, |
| 1802 | u64 bytes); | 1811 | u64 bytes); |
diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c index adda739a0215..3e18175248e0 100644 --- a/fs/btrfs/disk-io.c +++ b/fs/btrfs/disk-io.c | |||
| @@ -857,7 +857,7 @@ int clean_tree_block(struct btrfs_trans_handle *trans, struct btrfs_root *root, | |||
| 857 | struct inode *btree_inode = root->fs_info->btree_inode; | 857 | struct inode *btree_inode = root->fs_info->btree_inode; |
| 858 | if (btrfs_header_generation(buf) == | 858 | if (btrfs_header_generation(buf) == |
| 859 | root->fs_info->running_transaction->transid) { | 859 | root->fs_info->running_transaction->transid) { |
| 860 | WARN_ON(!btrfs_tree_locked(buf)); | 860 | btrfs_assert_tree_locked(buf); |
| 861 | 861 | ||
| 862 | /* ugh, clear_extent_buffer_dirty can be expensive */ | 862 | /* ugh, clear_extent_buffer_dirty can be expensive */ |
| 863 | btrfs_set_lock_blocking(buf); | 863 | btrfs_set_lock_blocking(buf); |
| @@ -2361,7 +2361,7 @@ void btrfs_mark_buffer_dirty(struct extent_buffer *buf) | |||
| 2361 | 2361 | ||
| 2362 | btrfs_set_lock_blocking(buf); | 2362 | btrfs_set_lock_blocking(buf); |
| 2363 | 2363 | ||
| 2364 | WARN_ON(!btrfs_tree_locked(buf)); | 2364 | btrfs_assert_tree_locked(buf); |
| 2365 | if (transid != root->fs_info->generation) { | 2365 | if (transid != root->fs_info->generation) { |
| 2366 | printk(KERN_CRIT "btrfs transid mismatch buffer %llu, " | 2366 | printk(KERN_CRIT "btrfs transid mismatch buffer %llu, " |
| 2367 | "found %llu running %llu\n", | 2367 | "found %llu running %llu\n", |
diff --git a/fs/btrfs/extent-tree.c b/fs/btrfs/extent-tree.c index 6b5966aacf44..fefe83ad2059 100644 --- a/fs/btrfs/extent-tree.c +++ b/fs/btrfs/extent-tree.c | |||
| @@ -20,6 +20,7 @@ | |||
| 20 | #include <linux/writeback.h> | 20 | #include <linux/writeback.h> |
| 21 | #include <linux/blkdev.h> | 21 | #include <linux/blkdev.h> |
| 22 | #include <linux/sort.h> | 22 | #include <linux/sort.h> |
| 23 | #include <linux/rcupdate.h> | ||
| 23 | #include "compat.h" | 24 | #include "compat.h" |
| 24 | #include "hash.h" | 25 | #include "hash.h" |
| 25 | #include "crc32c.h" | 26 | #include "crc32c.h" |
| @@ -330,13 +331,33 @@ static struct btrfs_space_info *__find_space_info(struct btrfs_fs_info *info, | |||
| 330 | { | 331 | { |
| 331 | struct list_head *head = &info->space_info; | 332 | struct list_head *head = &info->space_info; |
| 332 | struct btrfs_space_info *found; | 333 | struct btrfs_space_info *found; |
| 333 | list_for_each_entry(found, head, list) { | 334 | |
| 334 | if (found->flags == flags) | 335 | rcu_read_lock(); |
| 336 | list_for_each_entry_rcu(found, head, list) { | ||
| 337 | if (found->flags == flags) { | ||
| 338 | rcu_read_unlock(); | ||
| 335 | return found; | 339 | return found; |
| 340 | } | ||
| 336 | } | 341 | } |
| 342 | rcu_read_unlock(); | ||
| 337 | return NULL; | 343 | return NULL; |
| 338 | } | 344 | } |
| 339 | 345 | ||
| 346 | /* | ||
| 347 | * after adding space to the filesystem, we need to clear the full flags | ||
| 348 | * on all the space infos. | ||
| 349 | */ | ||
| 350 | void btrfs_clear_space_info_full(struct btrfs_fs_info *info) | ||
| 351 | { | ||
| 352 | struct list_head *head = &info->space_info; | ||
| 353 | struct btrfs_space_info *found; | ||
| 354 | |||
| 355 | rcu_read_lock(); | ||
| 356 | list_for_each_entry_rcu(found, head, list) | ||
| 357 | found->full = 0; | ||
| 358 | rcu_read_unlock(); | ||
| 359 | } | ||
| 360 | |||
| 340 | static u64 div_factor(u64 num, int factor) | 361 | static u64 div_factor(u64 num, int factor) |
| 341 | { | 362 | { |
| 342 | if (factor == 10) | 363 | if (factor == 10) |
| @@ -1903,7 +1924,6 @@ static int update_space_info(struct btrfs_fs_info *info, u64 flags, | |||
| 1903 | if (!found) | 1924 | if (!found) |
| 1904 | return -ENOMEM; | 1925 | return -ENOMEM; |
| 1905 | 1926 | ||
| 1906 | list_add(&found->list, &info->space_info); | ||
| 1907 | INIT_LIST_HEAD(&found->block_groups); | 1927 | INIT_LIST_HEAD(&found->block_groups); |
| 1908 | init_rwsem(&found->groups_sem); | 1928 | init_rwsem(&found->groups_sem); |
| 1909 | spin_lock_init(&found->lock); | 1929 | spin_lock_init(&found->lock); |
| @@ -1917,6 +1937,7 @@ static int update_space_info(struct btrfs_fs_info *info, u64 flags, | |||
| 1917 | found->full = 0; | 1937 | found->full = 0; |
| 1918 | found->force_alloc = 0; | 1938 | found->force_alloc = 0; |
| 1919 | *space_info = found; | 1939 | *space_info = found; |
| 1940 | list_add_rcu(&found->list, &info->space_info); | ||
| 1920 | return 0; | 1941 | return 0; |
| 1921 | } | 1942 | } |
| 1922 | 1943 | ||
| @@ -4418,13 +4439,13 @@ int btrfs_drop_subtree(struct btrfs_trans_handle *trans, | |||
| 4418 | path = btrfs_alloc_path(); | 4439 | path = btrfs_alloc_path(); |
| 4419 | BUG_ON(!path); | 4440 | BUG_ON(!path); |
| 4420 | 4441 | ||
| 4421 | BUG_ON(!btrfs_tree_locked(parent)); | 4442 | btrfs_assert_tree_locked(parent); |
| 4422 | parent_level = btrfs_header_level(parent); | 4443 | parent_level = btrfs_header_level(parent); |
| 4423 | extent_buffer_get(parent); | 4444 | extent_buffer_get(parent); |
| 4424 | path->nodes[parent_level] = parent; | 4445 | path->nodes[parent_level] = parent; |
| 4425 | path->slots[parent_level] = btrfs_header_nritems(parent); | 4446 | path->slots[parent_level] = btrfs_header_nritems(parent); |
| 4426 | 4447 | ||
| 4427 | BUG_ON(!btrfs_tree_locked(node)); | 4448 | btrfs_assert_tree_locked(node); |
| 4428 | level = btrfs_header_level(node); | 4449 | level = btrfs_header_level(node); |
| 4429 | extent_buffer_get(node); | 4450 | extent_buffer_get(node); |
| 4430 | path->nodes[level] = node; | 4451 | path->nodes[level] = node; |
| @@ -6320,6 +6341,7 @@ out: | |||
| 6320 | int btrfs_free_block_groups(struct btrfs_fs_info *info) | 6341 | int btrfs_free_block_groups(struct btrfs_fs_info *info) |
| 6321 | { | 6342 | { |
| 6322 | struct btrfs_block_group_cache *block_group; | 6343 | struct btrfs_block_group_cache *block_group; |
| 6344 | struct btrfs_space_info *space_info; | ||
| 6323 | struct rb_node *n; | 6345 | struct rb_node *n; |
| 6324 | 6346 | ||
| 6325 | spin_lock(&info->block_group_cache_lock); | 6347 | spin_lock(&info->block_group_cache_lock); |
| @@ -6341,6 +6363,23 @@ int btrfs_free_block_groups(struct btrfs_fs_info *info) | |||
| 6341 | spin_lock(&info->block_group_cache_lock); | 6363 | spin_lock(&info->block_group_cache_lock); |
| 6342 | } | 6364 | } |
| 6343 | spin_unlock(&info->block_group_cache_lock); | 6365 | spin_unlock(&info->block_group_cache_lock); |
| 6366 | |||
| 6367 | /* now that all the block groups are freed, go through and | ||
| 6368 | * free all the space_info structs. This is only called during | ||
| 6369 | * the final stages of unmount, and so we know nobody is | ||
| 6370 | * using them. We call synchronize_rcu() once before we start, | ||
| 6371 | * just to be on the safe side. | ||
| 6372 | */ | ||
| 6373 | synchronize_rcu(); | ||
| 6374 | |||
| 6375 | while(!list_empty(&info->space_info)) { | ||
| 6376 | space_info = list_entry(info->space_info.next, | ||
| 6377 | struct btrfs_space_info, | ||
| 6378 | list); | ||
| 6379 | |||
| 6380 | list_del(&space_info->list); | ||
| 6381 | kfree(space_info); | ||
| 6382 | } | ||
| 6344 | return 0; | 6383 | return 0; |
| 6345 | } | 6384 | } |
| 6346 | 6385 | ||
diff --git a/fs/btrfs/locking.c b/fs/btrfs/locking.c index 85506c4a3af7..47b0a88c12a2 100644 --- a/fs/btrfs/locking.c +++ b/fs/btrfs/locking.c | |||
| @@ -220,8 +220,8 @@ int btrfs_tree_unlock(struct extent_buffer *eb) | |||
| 220 | return 0; | 220 | return 0; |
| 221 | } | 221 | } |
| 222 | 222 | ||
| 223 | int btrfs_tree_locked(struct extent_buffer *eb) | 223 | void btrfs_assert_tree_locked(struct extent_buffer *eb) |
| 224 | { | 224 | { |
| 225 | return test_bit(EXTENT_BUFFER_BLOCKING, &eb->bflags) || | 225 | if (!test_bit(EXTENT_BUFFER_BLOCKING, &eb->bflags)) |
| 226 | spin_is_locked(&eb->lock); | 226 | assert_spin_locked(&eb->lock); |
| 227 | } | 227 | } |
diff --git a/fs/btrfs/locking.h b/fs/btrfs/locking.h index 6bb0afbff928..6c4ce457168c 100644 --- a/fs/btrfs/locking.h +++ b/fs/btrfs/locking.h | |||
| @@ -21,11 +21,11 @@ | |||
| 21 | 21 | ||
| 22 | int btrfs_tree_lock(struct extent_buffer *eb); | 22 | int btrfs_tree_lock(struct extent_buffer *eb); |
| 23 | int btrfs_tree_unlock(struct extent_buffer *eb); | 23 | int btrfs_tree_unlock(struct extent_buffer *eb); |
| 24 | int btrfs_tree_locked(struct extent_buffer *eb); | ||
| 25 | 24 | ||
| 26 | int btrfs_try_tree_lock(struct extent_buffer *eb); | 25 | int btrfs_try_tree_lock(struct extent_buffer *eb); |
| 27 | int btrfs_try_spin_lock(struct extent_buffer *eb); | 26 | int btrfs_try_spin_lock(struct extent_buffer *eb); |
| 28 | 27 | ||
| 29 | void btrfs_set_lock_blocking(struct extent_buffer *eb); | 28 | void btrfs_set_lock_blocking(struct extent_buffer *eb); |
| 30 | void btrfs_clear_lock_blocking(struct extent_buffer *eb); | 29 | void btrfs_clear_lock_blocking(struct extent_buffer *eb); |
| 30 | void btrfs_assert_tree_locked(struct extent_buffer *eb); | ||
| 31 | #endif | 31 | #endif |
diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c index 1316139bf9e8..dd06e18e5aac 100644 --- a/fs/btrfs/volumes.c +++ b/fs/btrfs/volumes.c | |||
| @@ -1374,6 +1374,12 @@ int btrfs_init_new_device(struct btrfs_root *root, char *device_path) | |||
| 1374 | ret = btrfs_add_device(trans, root, device); | 1374 | ret = btrfs_add_device(trans, root, device); |
| 1375 | } | 1375 | } |
| 1376 | 1376 | ||
| 1377 | /* | ||
| 1378 | * we've got more storage, clear any full flags on the space | ||
| 1379 | * infos | ||
| 1380 | */ | ||
| 1381 | btrfs_clear_space_info_full(root->fs_info); | ||
| 1382 | |||
| 1377 | unlock_chunks(root); | 1383 | unlock_chunks(root); |
| 1378 | btrfs_commit_transaction(trans, root); | 1384 | btrfs_commit_transaction(trans, root); |
| 1379 | 1385 | ||
| @@ -1459,6 +1465,8 @@ static int __btrfs_grow_device(struct btrfs_trans_handle *trans, | |||
| 1459 | device->fs_devices->total_rw_bytes += diff; | 1465 | device->fs_devices->total_rw_bytes += diff; |
| 1460 | 1466 | ||
| 1461 | device->total_bytes = new_size; | 1467 | device->total_bytes = new_size; |
| 1468 | btrfs_clear_space_info_full(device->dev_root->fs_info); | ||
| 1469 | |||
| 1462 | return btrfs_update_device(trans, device); | 1470 | return btrfs_update_device(trans, device); |
| 1463 | } | 1471 | } |
| 1464 | 1472 | ||
diff --git a/fs/buffer.c b/fs/buffer.c index 9f697419ed8e..891e1c78e4f1 100644 --- a/fs/buffer.c +++ b/fs/buffer.c | |||
| @@ -760,15 +760,9 @@ EXPORT_SYMBOL(mark_buffer_dirty_inode); | |||
| 760 | * If warn is true, then emit a warning if the page is not uptodate and has | 760 | * If warn is true, then emit a warning if the page is not uptodate and has |
| 761 | * not been truncated. | 761 | * not been truncated. |
| 762 | */ | 762 | */ |
| 763 | static int __set_page_dirty(struct page *page, | 763 | static void __set_page_dirty(struct page *page, |
| 764 | struct address_space *mapping, int warn) | 764 | struct address_space *mapping, int warn) |
| 765 | { | 765 | { |
| 766 | if (unlikely(!mapping)) | ||
| 767 | return !TestSetPageDirty(page); | ||
| 768 | |||
| 769 | if (TestSetPageDirty(page)) | ||
| 770 | return 0; | ||
| 771 | |||
| 772 | spin_lock_irq(&mapping->tree_lock); | 766 | spin_lock_irq(&mapping->tree_lock); |
| 773 | if (page->mapping) { /* Race with truncate? */ | 767 | if (page->mapping) { /* Race with truncate? */ |
| 774 | WARN_ON_ONCE(warn && !PageUptodate(page)); | 768 | WARN_ON_ONCE(warn && !PageUptodate(page)); |
| @@ -785,8 +779,6 @@ static int __set_page_dirty(struct page *page, | |||
| 785 | } | 779 | } |
| 786 | spin_unlock_irq(&mapping->tree_lock); | 780 | spin_unlock_irq(&mapping->tree_lock); |
| 787 | __mark_inode_dirty(mapping->host, I_DIRTY_PAGES); | 781 | __mark_inode_dirty(mapping->host, I_DIRTY_PAGES); |
| 788 | |||
| 789 | return 1; | ||
| 790 | } | 782 | } |
| 791 | 783 | ||
| 792 | /* | 784 | /* |
| @@ -816,6 +808,7 @@ static int __set_page_dirty(struct page *page, | |||
| 816 | */ | 808 | */ |
| 817 | int __set_page_dirty_buffers(struct page *page) | 809 | int __set_page_dirty_buffers(struct page *page) |
| 818 | { | 810 | { |
| 811 | int newly_dirty; | ||
| 819 | struct address_space *mapping = page_mapping(page); | 812 | struct address_space *mapping = page_mapping(page); |
| 820 | 813 | ||
| 821 | if (unlikely(!mapping)) | 814 | if (unlikely(!mapping)) |
| @@ -831,9 +824,12 @@ int __set_page_dirty_buffers(struct page *page) | |||
| 831 | bh = bh->b_this_page; | 824 | bh = bh->b_this_page; |
| 832 | } while (bh != head); | 825 | } while (bh != head); |
| 833 | } | 826 | } |
| 827 | newly_dirty = !TestSetPageDirty(page); | ||
| 834 | spin_unlock(&mapping->private_lock); | 828 | spin_unlock(&mapping->private_lock); |
| 835 | 829 | ||
| 836 | return __set_page_dirty(page, mapping, 1); | 830 | if (newly_dirty) |
| 831 | __set_page_dirty(page, mapping, 1); | ||
| 832 | return newly_dirty; | ||
| 837 | } | 833 | } |
| 838 | EXPORT_SYMBOL(__set_page_dirty_buffers); | 834 | EXPORT_SYMBOL(__set_page_dirty_buffers); |
| 839 | 835 | ||
| @@ -1262,8 +1258,11 @@ void mark_buffer_dirty(struct buffer_head *bh) | |||
| 1262 | return; | 1258 | return; |
| 1263 | } | 1259 | } |
| 1264 | 1260 | ||
| 1265 | if (!test_set_buffer_dirty(bh)) | 1261 | if (!test_set_buffer_dirty(bh)) { |
| 1266 | __set_page_dirty(bh->b_page, page_mapping(bh->b_page), 0); | 1262 | struct page *page = bh->b_page; |
| 1263 | if (!TestSetPageDirty(page)) | ||
| 1264 | __set_page_dirty(page, page_mapping(page), 0); | ||
| 1265 | } | ||
| 1267 | } | 1266 | } |
| 1268 | 1267 | ||
| 1269 | /* | 1268 | /* |
diff --git a/fs/devpts/inode.c b/fs/devpts/inode.c index 5f3231b9633f..bff4052b05e7 100644 --- a/fs/devpts/inode.c +++ b/fs/devpts/inode.c | |||
| @@ -198,9 +198,6 @@ static int mknod_ptmx(struct super_block *sb) | |||
| 198 | 198 | ||
| 199 | fsi->ptmx_dentry = dentry; | 199 | fsi->ptmx_dentry = dentry; |
| 200 | rc = 0; | 200 | rc = 0; |
| 201 | |||
| 202 | printk(KERN_DEBUG "Created ptmx node in devpts ino %lu\n", | ||
| 203 | inode->i_ino); | ||
| 204 | out: | 201 | out: |
| 205 | mutex_unlock(&root->d_inode->i_mutex); | 202 | mutex_unlock(&root->d_inode->i_mutex); |
| 206 | return rc; | 203 | return rc; |
| @@ -369,8 +366,6 @@ static int new_pts_mount(struct file_system_type *fs_type, int flags, | |||
| 369 | struct pts_fs_info *fsi; | 366 | struct pts_fs_info *fsi; |
| 370 | struct pts_mount_opts *opts; | 367 | struct pts_mount_opts *opts; |
| 371 | 368 | ||
| 372 | printk(KERN_NOTICE "devpts: newinstance mount\n"); | ||
| 373 | |||
| 374 | err = get_sb_nodev(fs_type, flags, data, devpts_fill_super, mnt); | 369 | err = get_sb_nodev(fs_type, flags, data, devpts_fill_super, mnt); |
| 375 | if (err) | 370 | if (err) |
| 376 | return err; | 371 | return err; |
diff --git a/fs/ecryptfs/crypto.c b/fs/ecryptfs/crypto.c index f6caeb1d1106..8b65f289ee00 100644 --- a/fs/ecryptfs/crypto.c +++ b/fs/ecryptfs/crypto.c | |||
| @@ -946,6 +946,8 @@ static int ecryptfs_copy_mount_wide_sigs_to_inode_sigs( | |||
| 946 | list_for_each_entry(global_auth_tok, | 946 | list_for_each_entry(global_auth_tok, |
| 947 | &mount_crypt_stat->global_auth_tok_list, | 947 | &mount_crypt_stat->global_auth_tok_list, |
| 948 | mount_crypt_stat_list) { | 948 | mount_crypt_stat_list) { |
| 949 | if (global_auth_tok->flags & ECRYPTFS_AUTH_TOK_FNEK) | ||
| 950 | continue; | ||
| 949 | rc = ecryptfs_add_keysig(crypt_stat, global_auth_tok->sig); | 951 | rc = ecryptfs_add_keysig(crypt_stat, global_auth_tok->sig); |
| 950 | if (rc) { | 952 | if (rc) { |
| 951 | printk(KERN_ERR "Error adding keysig; rc = [%d]\n", rc); | 953 | printk(KERN_ERR "Error adding keysig; rc = [%d]\n", rc); |
| @@ -1322,14 +1324,13 @@ static int ecryptfs_write_headers_virt(char *page_virt, size_t max, | |||
| 1322 | } | 1324 | } |
| 1323 | 1325 | ||
| 1324 | static int | 1326 | static int |
| 1325 | ecryptfs_write_metadata_to_contents(struct ecryptfs_crypt_stat *crypt_stat, | 1327 | ecryptfs_write_metadata_to_contents(struct dentry *ecryptfs_dentry, |
| 1326 | struct dentry *ecryptfs_dentry, | 1328 | char *virt, size_t virt_len) |
| 1327 | char *virt) | ||
| 1328 | { | 1329 | { |
| 1329 | int rc; | 1330 | int rc; |
| 1330 | 1331 | ||
| 1331 | rc = ecryptfs_write_lower(ecryptfs_dentry->d_inode, virt, | 1332 | rc = ecryptfs_write_lower(ecryptfs_dentry->d_inode, virt, |
| 1332 | 0, crypt_stat->num_header_bytes_at_front); | 1333 | 0, virt_len); |
| 1333 | if (rc) | 1334 | if (rc) |
| 1334 | printk(KERN_ERR "%s: Error attempting to write header " | 1335 | printk(KERN_ERR "%s: Error attempting to write header " |
| 1335 | "information to lower file; rc = [%d]\n", __func__, | 1336 | "information to lower file; rc = [%d]\n", __func__, |
| @@ -1339,7 +1340,6 @@ ecryptfs_write_metadata_to_contents(struct ecryptfs_crypt_stat *crypt_stat, | |||
| 1339 | 1340 | ||
| 1340 | static int | 1341 | static int |
| 1341 | ecryptfs_write_metadata_to_xattr(struct dentry *ecryptfs_dentry, | 1342 | ecryptfs_write_metadata_to_xattr(struct dentry *ecryptfs_dentry, |
| 1342 | struct ecryptfs_crypt_stat *crypt_stat, | ||
| 1343 | char *page_virt, size_t size) | 1343 | char *page_virt, size_t size) |
| 1344 | { | 1344 | { |
| 1345 | int rc; | 1345 | int rc; |
| @@ -1349,6 +1349,17 @@ ecryptfs_write_metadata_to_xattr(struct dentry *ecryptfs_dentry, | |||
| 1349 | return rc; | 1349 | return rc; |
| 1350 | } | 1350 | } |
| 1351 | 1351 | ||
| 1352 | static unsigned long ecryptfs_get_zeroed_pages(gfp_t gfp_mask, | ||
| 1353 | unsigned int order) | ||
| 1354 | { | ||
| 1355 | struct page *page; | ||
| 1356 | |||
| 1357 | page = alloc_pages(gfp_mask | __GFP_ZERO, order); | ||
| 1358 | if (page) | ||
| 1359 | return (unsigned long) page_address(page); | ||
| 1360 | return 0; | ||
| 1361 | } | ||
| 1362 | |||
| 1352 | /** | 1363 | /** |
| 1353 | * ecryptfs_write_metadata | 1364 | * ecryptfs_write_metadata |
| 1354 | * @ecryptfs_dentry: The eCryptfs dentry | 1365 | * @ecryptfs_dentry: The eCryptfs dentry |
| @@ -1365,7 +1376,9 @@ int ecryptfs_write_metadata(struct dentry *ecryptfs_dentry) | |||
| 1365 | { | 1376 | { |
| 1366 | struct ecryptfs_crypt_stat *crypt_stat = | 1377 | struct ecryptfs_crypt_stat *crypt_stat = |
| 1367 | &ecryptfs_inode_to_private(ecryptfs_dentry->d_inode)->crypt_stat; | 1378 | &ecryptfs_inode_to_private(ecryptfs_dentry->d_inode)->crypt_stat; |
| 1379 | unsigned int order; | ||
| 1368 | char *virt; | 1380 | char *virt; |
| 1381 | size_t virt_len; | ||
| 1369 | size_t size = 0; | 1382 | size_t size = 0; |
| 1370 | int rc = 0; | 1383 | int rc = 0; |
| 1371 | 1384 | ||
| @@ -1381,33 +1394,35 @@ int ecryptfs_write_metadata(struct dentry *ecryptfs_dentry) | |||
| 1381 | rc = -EINVAL; | 1394 | rc = -EINVAL; |
| 1382 | goto out; | 1395 | goto out; |
| 1383 | } | 1396 | } |
| 1397 | virt_len = crypt_stat->num_header_bytes_at_front; | ||
| 1398 | order = get_order(virt_len); | ||
| 1384 | /* Released in this function */ | 1399 | /* Released in this function */ |
| 1385 | virt = (char *)get_zeroed_page(GFP_KERNEL); | 1400 | virt = (char *)ecryptfs_get_zeroed_pages(GFP_KERNEL, order); |
| 1386 | if (!virt) { | 1401 | if (!virt) { |
| 1387 | printk(KERN_ERR "%s: Out of memory\n", __func__); | 1402 | printk(KERN_ERR "%s: Out of memory\n", __func__); |
| 1388 | rc = -ENOMEM; | 1403 | rc = -ENOMEM; |
| 1389 | goto out; | 1404 | goto out; |
| 1390 | } | 1405 | } |
| 1391 | rc = ecryptfs_write_headers_virt(virt, PAGE_CACHE_SIZE, &size, | 1406 | rc = ecryptfs_write_headers_virt(virt, virt_len, &size, crypt_stat, |
| 1392 | crypt_stat, ecryptfs_dentry); | 1407 | ecryptfs_dentry); |
| 1393 | if (unlikely(rc)) { | 1408 | if (unlikely(rc)) { |
| 1394 | printk(KERN_ERR "%s: Error whilst writing headers; rc = [%d]\n", | 1409 | printk(KERN_ERR "%s: Error whilst writing headers; rc = [%d]\n", |
| 1395 | __func__, rc); | 1410 | __func__, rc); |
| 1396 | goto out_free; | 1411 | goto out_free; |
| 1397 | } | 1412 | } |
| 1398 | if (crypt_stat->flags & ECRYPTFS_METADATA_IN_XATTR) | 1413 | if (crypt_stat->flags & ECRYPTFS_METADATA_IN_XATTR) |
| 1399 | rc = ecryptfs_write_metadata_to_xattr(ecryptfs_dentry, | 1414 | rc = ecryptfs_write_metadata_to_xattr(ecryptfs_dentry, virt, |
| 1400 | crypt_stat, virt, size); | 1415 | size); |
| 1401 | else | 1416 | else |
| 1402 | rc = ecryptfs_write_metadata_to_contents(crypt_stat, | 1417 | rc = ecryptfs_write_metadata_to_contents(ecryptfs_dentry, virt, |
| 1403 | ecryptfs_dentry, virt); | 1418 | virt_len); |
| 1404 | if (rc) { | 1419 | if (rc) { |
| 1405 | printk(KERN_ERR "%s: Error writing metadata out to lower file; " | 1420 | printk(KERN_ERR "%s: Error writing metadata out to lower file; " |
| 1406 | "rc = [%d]\n", __func__, rc); | 1421 | "rc = [%d]\n", __func__, rc); |
| 1407 | goto out_free; | 1422 | goto out_free; |
| 1408 | } | 1423 | } |
| 1409 | out_free: | 1424 | out_free: |
| 1410 | free_page((unsigned long)virt); | 1425 | free_pages((unsigned long)virt, order); |
| 1411 | out: | 1426 | out: |
| 1412 | return rc; | 1427 | return rc; |
| 1413 | } | 1428 | } |
| @@ -2206,17 +2221,19 @@ int ecryptfs_decode_and_decrypt_filename(char **plaintext_name, | |||
| 2206 | struct dentry *ecryptfs_dir_dentry, | 2221 | struct dentry *ecryptfs_dir_dentry, |
| 2207 | const char *name, size_t name_size) | 2222 | const char *name, size_t name_size) |
| 2208 | { | 2223 | { |
| 2224 | struct ecryptfs_mount_crypt_stat *mount_crypt_stat = | ||
| 2225 | &ecryptfs_superblock_to_private( | ||
| 2226 | ecryptfs_dir_dentry->d_sb)->mount_crypt_stat; | ||
| 2209 | char *decoded_name; | 2227 | char *decoded_name; |
| 2210 | size_t decoded_name_size; | 2228 | size_t decoded_name_size; |
| 2211 | size_t packet_size; | 2229 | size_t packet_size; |
| 2212 | int rc = 0; | 2230 | int rc = 0; |
| 2213 | 2231 | ||
| 2214 | if ((name_size > ECRYPTFS_FNEK_ENCRYPTED_FILENAME_PREFIX_SIZE) | 2232 | if ((mount_crypt_stat->flags & ECRYPTFS_GLOBAL_ENCRYPT_FILENAMES) |
| 2233 | && !(mount_crypt_stat->flags & ECRYPTFS_ENCRYPTED_VIEW_ENABLED) | ||
| 2234 | && (name_size > ECRYPTFS_FNEK_ENCRYPTED_FILENAME_PREFIX_SIZE) | ||
| 2215 | && (strncmp(name, ECRYPTFS_FNEK_ENCRYPTED_FILENAME_PREFIX, | 2235 | && (strncmp(name, ECRYPTFS_FNEK_ENCRYPTED_FILENAME_PREFIX, |
| 2216 | ECRYPTFS_FNEK_ENCRYPTED_FILENAME_PREFIX_SIZE) == 0)) { | 2236 | ECRYPTFS_FNEK_ENCRYPTED_FILENAME_PREFIX_SIZE) == 0)) { |
| 2217 | struct ecryptfs_mount_crypt_stat *mount_crypt_stat = | ||
| 2218 | &ecryptfs_superblock_to_private( | ||
| 2219 | ecryptfs_dir_dentry->d_sb)->mount_crypt_stat; | ||
| 2220 | const char *orig_name = name; | 2237 | const char *orig_name = name; |
| 2221 | size_t orig_name_size = name_size; | 2238 | size_t orig_name_size = name_size; |
| 2222 | 2239 | ||
diff --git a/fs/ecryptfs/ecryptfs_kernel.h b/fs/ecryptfs/ecryptfs_kernel.h index c11fc95714ab..ac749d4d644f 100644 --- a/fs/ecryptfs/ecryptfs_kernel.h +++ b/fs/ecryptfs/ecryptfs_kernel.h | |||
| @@ -328,6 +328,7 @@ struct ecryptfs_dentry_info { | |||
| 328 | */ | 328 | */ |
| 329 | struct ecryptfs_global_auth_tok { | 329 | struct ecryptfs_global_auth_tok { |
| 330 | #define ECRYPTFS_AUTH_TOK_INVALID 0x00000001 | 330 | #define ECRYPTFS_AUTH_TOK_INVALID 0x00000001 |
| 331 | #define ECRYPTFS_AUTH_TOK_FNEK 0x00000002 | ||
| 331 | u32 flags; | 332 | u32 flags; |
| 332 | struct list_head mount_crypt_stat_list; | 333 | struct list_head mount_crypt_stat_list; |
| 333 | struct key *global_auth_tok_key; | 334 | struct key *global_auth_tok_key; |
| @@ -619,7 +620,6 @@ int ecryptfs_interpose(struct dentry *hidden_dentry, | |||
| 619 | u32 flags); | 620 | u32 flags); |
| 620 | int ecryptfs_lookup_and_interpose_lower(struct dentry *ecryptfs_dentry, | 621 | int ecryptfs_lookup_and_interpose_lower(struct dentry *ecryptfs_dentry, |
| 621 | struct dentry *lower_dentry, | 622 | struct dentry *lower_dentry, |
| 622 | struct ecryptfs_crypt_stat *crypt_stat, | ||
| 623 | struct inode *ecryptfs_dir_inode, | 623 | struct inode *ecryptfs_dir_inode, |
| 624 | struct nameidata *ecryptfs_nd); | 624 | struct nameidata *ecryptfs_nd); |
| 625 | int ecryptfs_decode_and_decrypt_filename(char **decrypted_name, | 625 | int ecryptfs_decode_and_decrypt_filename(char **decrypted_name, |
| @@ -696,7 +696,7 @@ ecryptfs_write_header_metadata(char *virt, | |||
| 696 | int ecryptfs_add_keysig(struct ecryptfs_crypt_stat *crypt_stat, char *sig); | 696 | int ecryptfs_add_keysig(struct ecryptfs_crypt_stat *crypt_stat, char *sig); |
| 697 | int | 697 | int |
| 698 | ecryptfs_add_global_auth_tok(struct ecryptfs_mount_crypt_stat *mount_crypt_stat, | 698 | ecryptfs_add_global_auth_tok(struct ecryptfs_mount_crypt_stat *mount_crypt_stat, |
| 699 | char *sig); | 699 | char *sig, u32 global_auth_tok_flags); |
| 700 | int ecryptfs_get_global_auth_tok_for_sig( | 700 | int ecryptfs_get_global_auth_tok_for_sig( |
| 701 | struct ecryptfs_global_auth_tok **global_auth_tok, | 701 | struct ecryptfs_global_auth_tok **global_auth_tok, |
| 702 | struct ecryptfs_mount_crypt_stat *mount_crypt_stat, char *sig); | 702 | struct ecryptfs_mount_crypt_stat *mount_crypt_stat, char *sig); |
diff --git a/fs/ecryptfs/inode.c b/fs/ecryptfs/inode.c index 5697899a168d..55b3145b8072 100644 --- a/fs/ecryptfs/inode.c +++ b/fs/ecryptfs/inode.c | |||
| @@ -246,7 +246,6 @@ out: | |||
| 246 | */ | 246 | */ |
| 247 | int ecryptfs_lookup_and_interpose_lower(struct dentry *ecryptfs_dentry, | 247 | int ecryptfs_lookup_and_interpose_lower(struct dentry *ecryptfs_dentry, |
| 248 | struct dentry *lower_dentry, | 248 | struct dentry *lower_dentry, |
| 249 | struct ecryptfs_crypt_stat *crypt_stat, | ||
| 250 | struct inode *ecryptfs_dir_inode, | 249 | struct inode *ecryptfs_dir_inode, |
| 251 | struct nameidata *ecryptfs_nd) | 250 | struct nameidata *ecryptfs_nd) |
| 252 | { | 251 | { |
| @@ -254,6 +253,7 @@ int ecryptfs_lookup_and_interpose_lower(struct dentry *ecryptfs_dentry, | |||
| 254 | struct vfsmount *lower_mnt; | 253 | struct vfsmount *lower_mnt; |
| 255 | struct inode *lower_inode; | 254 | struct inode *lower_inode; |
| 256 | struct ecryptfs_mount_crypt_stat *mount_crypt_stat; | 255 | struct ecryptfs_mount_crypt_stat *mount_crypt_stat; |
| 256 | struct ecryptfs_crypt_stat *crypt_stat; | ||
| 257 | char *page_virt = NULL; | 257 | char *page_virt = NULL; |
| 258 | u64 file_size; | 258 | u64 file_size; |
| 259 | int rc = 0; | 259 | int rc = 0; |
| @@ -314,6 +314,11 @@ int ecryptfs_lookup_and_interpose_lower(struct dentry *ecryptfs_dentry, | |||
| 314 | goto out_free_kmem; | 314 | goto out_free_kmem; |
| 315 | } | 315 | } |
| 316 | } | 316 | } |
| 317 | crypt_stat = &ecryptfs_inode_to_private( | ||
| 318 | ecryptfs_dentry->d_inode)->crypt_stat; | ||
| 319 | /* TODO: lock for crypt_stat comparison */ | ||
| 320 | if (!(crypt_stat->flags & ECRYPTFS_POLICY_APPLIED)) | ||
| 321 | ecryptfs_set_default_sizes(crypt_stat); | ||
| 317 | rc = ecryptfs_read_and_validate_header_region(page_virt, | 322 | rc = ecryptfs_read_and_validate_header_region(page_virt, |
| 318 | ecryptfs_dentry->d_inode); | 323 | ecryptfs_dentry->d_inode); |
| 319 | if (rc) { | 324 | if (rc) { |
| @@ -362,9 +367,7 @@ static struct dentry *ecryptfs_lookup(struct inode *ecryptfs_dir_inode, | |||
| 362 | { | 367 | { |
| 363 | char *encrypted_and_encoded_name = NULL; | 368 | char *encrypted_and_encoded_name = NULL; |
| 364 | size_t encrypted_and_encoded_name_size; | 369 | size_t encrypted_and_encoded_name_size; |
| 365 | struct ecryptfs_crypt_stat *crypt_stat = NULL; | ||
| 366 | struct ecryptfs_mount_crypt_stat *mount_crypt_stat = NULL; | 370 | struct ecryptfs_mount_crypt_stat *mount_crypt_stat = NULL; |
| 367 | struct ecryptfs_inode_info *inode_info; | ||
| 368 | struct dentry *lower_dir_dentry, *lower_dentry; | 371 | struct dentry *lower_dir_dentry, *lower_dentry; |
| 369 | int rc = 0; | 372 | int rc = 0; |
| 370 | 373 | ||
| @@ -388,26 +391,15 @@ static struct dentry *ecryptfs_lookup(struct inode *ecryptfs_dir_inode, | |||
| 388 | } | 391 | } |
| 389 | if (lower_dentry->d_inode) | 392 | if (lower_dentry->d_inode) |
| 390 | goto lookup_and_interpose; | 393 | goto lookup_and_interpose; |
| 391 | inode_info = ecryptfs_inode_to_private(ecryptfs_dentry->d_inode); | 394 | mount_crypt_stat = &ecryptfs_superblock_to_private( |
| 392 | if (inode_info) { | 395 | ecryptfs_dentry->d_sb)->mount_crypt_stat; |
| 393 | crypt_stat = &inode_info->crypt_stat; | 396 | if (!(mount_crypt_stat |
| 394 | /* TODO: lock for crypt_stat comparison */ | 397 | && (mount_crypt_stat->flags & ECRYPTFS_GLOBAL_ENCRYPT_FILENAMES))) |
| 395 | if (!(crypt_stat->flags & ECRYPTFS_POLICY_APPLIED)) | ||
| 396 | ecryptfs_set_default_sizes(crypt_stat); | ||
| 397 | } | ||
| 398 | if (crypt_stat) | ||
| 399 | mount_crypt_stat = crypt_stat->mount_crypt_stat; | ||
| 400 | else | ||
| 401 | mount_crypt_stat = &ecryptfs_superblock_to_private( | ||
| 402 | ecryptfs_dentry->d_sb)->mount_crypt_stat; | ||
| 403 | if (!(crypt_stat && (crypt_stat->flags & ECRYPTFS_ENCRYPT_FILENAMES)) | ||
| 404 | && !(mount_crypt_stat && (mount_crypt_stat->flags | ||
| 405 | & ECRYPTFS_GLOBAL_ENCRYPT_FILENAMES))) | ||
| 406 | goto lookup_and_interpose; | 398 | goto lookup_and_interpose; |
| 407 | dput(lower_dentry); | 399 | dput(lower_dentry); |
| 408 | rc = ecryptfs_encrypt_and_encode_filename( | 400 | rc = ecryptfs_encrypt_and_encode_filename( |
| 409 | &encrypted_and_encoded_name, &encrypted_and_encoded_name_size, | 401 | &encrypted_and_encoded_name, &encrypted_and_encoded_name_size, |
| 410 | crypt_stat, mount_crypt_stat, ecryptfs_dentry->d_name.name, | 402 | NULL, mount_crypt_stat, ecryptfs_dentry->d_name.name, |
| 411 | ecryptfs_dentry->d_name.len); | 403 | ecryptfs_dentry->d_name.len); |
| 412 | if (rc) { | 404 | if (rc) { |
| 413 | printk(KERN_ERR "%s: Error attempting to encrypt and encode " | 405 | printk(KERN_ERR "%s: Error attempting to encrypt and encode " |
| @@ -426,7 +418,7 @@ static struct dentry *ecryptfs_lookup(struct inode *ecryptfs_dir_inode, | |||
| 426 | } | 418 | } |
| 427 | lookup_and_interpose: | 419 | lookup_and_interpose: |
| 428 | rc = ecryptfs_lookup_and_interpose_lower(ecryptfs_dentry, lower_dentry, | 420 | rc = ecryptfs_lookup_and_interpose_lower(ecryptfs_dentry, lower_dentry, |
| 429 | crypt_stat, ecryptfs_dir_inode, | 421 | ecryptfs_dir_inode, |
| 430 | ecryptfs_nd); | 422 | ecryptfs_nd); |
| 431 | goto out; | 423 | goto out; |
| 432 | out_d_drop: | 424 | out_d_drop: |
diff --git a/fs/ecryptfs/keystore.c b/fs/ecryptfs/keystore.c index ff539420cc6f..e4a6223c3145 100644 --- a/fs/ecryptfs/keystore.c +++ b/fs/ecryptfs/keystore.c | |||
| @@ -2375,7 +2375,7 @@ struct kmem_cache *ecryptfs_global_auth_tok_cache; | |||
| 2375 | 2375 | ||
| 2376 | int | 2376 | int |
| 2377 | ecryptfs_add_global_auth_tok(struct ecryptfs_mount_crypt_stat *mount_crypt_stat, | 2377 | ecryptfs_add_global_auth_tok(struct ecryptfs_mount_crypt_stat *mount_crypt_stat, |
| 2378 | char *sig) | 2378 | char *sig, u32 global_auth_tok_flags) |
| 2379 | { | 2379 | { |
| 2380 | struct ecryptfs_global_auth_tok *new_auth_tok; | 2380 | struct ecryptfs_global_auth_tok *new_auth_tok; |
| 2381 | int rc = 0; | 2381 | int rc = 0; |
| @@ -2389,6 +2389,7 @@ ecryptfs_add_global_auth_tok(struct ecryptfs_mount_crypt_stat *mount_crypt_stat, | |||
| 2389 | goto out; | 2389 | goto out; |
| 2390 | } | 2390 | } |
| 2391 | memcpy(new_auth_tok->sig, sig, ECRYPTFS_SIG_SIZE_HEX); | 2391 | memcpy(new_auth_tok->sig, sig, ECRYPTFS_SIG_SIZE_HEX); |
| 2392 | new_auth_tok->flags = global_auth_tok_flags; | ||
| 2392 | new_auth_tok->sig[ECRYPTFS_SIG_SIZE_HEX] = '\0'; | 2393 | new_auth_tok->sig[ECRYPTFS_SIG_SIZE_HEX] = '\0'; |
| 2393 | mutex_lock(&mount_crypt_stat->global_auth_tok_list_mutex); | 2394 | mutex_lock(&mount_crypt_stat->global_auth_tok_list_mutex); |
| 2394 | list_add(&new_auth_tok->mount_crypt_stat_list, | 2395 | list_add(&new_auth_tok->mount_crypt_stat_list, |
diff --git a/fs/ecryptfs/main.c b/fs/ecryptfs/main.c index 789cf2e1be1e..aed56c25539b 100644 --- a/fs/ecryptfs/main.c +++ b/fs/ecryptfs/main.c | |||
| @@ -319,7 +319,7 @@ static int ecryptfs_parse_options(struct super_block *sb, char *options) | |||
| 319 | case ecryptfs_opt_ecryptfs_sig: | 319 | case ecryptfs_opt_ecryptfs_sig: |
| 320 | sig_src = args[0].from; | 320 | sig_src = args[0].from; |
| 321 | rc = ecryptfs_add_global_auth_tok(mount_crypt_stat, | 321 | rc = ecryptfs_add_global_auth_tok(mount_crypt_stat, |
| 322 | sig_src); | 322 | sig_src, 0); |
| 323 | if (rc) { | 323 | if (rc) { |
| 324 | printk(KERN_ERR "Error attempting to register " | 324 | printk(KERN_ERR "Error attempting to register " |
| 325 | "global sig; rc = [%d]\n", rc); | 325 | "global sig; rc = [%d]\n", rc); |
| @@ -370,7 +370,8 @@ static int ecryptfs_parse_options(struct super_block *sb, char *options) | |||
| 370 | ECRYPTFS_SIG_SIZE_HEX] = '\0'; | 370 | ECRYPTFS_SIG_SIZE_HEX] = '\0'; |
| 371 | rc = ecryptfs_add_global_auth_tok( | 371 | rc = ecryptfs_add_global_auth_tok( |
| 372 | mount_crypt_stat, | 372 | mount_crypt_stat, |
| 373 | mount_crypt_stat->global_default_fnek_sig); | 373 | mount_crypt_stat->global_default_fnek_sig, |
| 374 | ECRYPTFS_AUTH_TOK_FNEK); | ||
| 374 | if (rc) { | 375 | if (rc) { |
| 375 | printk(KERN_ERR "Error attempting to register " | 376 | printk(KERN_ERR "Error attempting to register " |
| 376 | "global fnek sig [%s]; rc = [%d]\n", | 377 | "global fnek sig [%s]; rc = [%d]\n", |
diff --git a/fs/ext4/extents.c b/fs/ext4/extents.c index e2eab196875f..e0aa4fe4f596 100644 --- a/fs/ext4/extents.c +++ b/fs/ext4/extents.c | |||
| @@ -1122,7 +1122,8 @@ ext4_ext_search_right(struct inode *inode, struct ext4_ext_path *path, | |||
| 1122 | struct ext4_extent_idx *ix; | 1122 | struct ext4_extent_idx *ix; |
| 1123 | struct ext4_extent *ex; | 1123 | struct ext4_extent *ex; |
| 1124 | ext4_fsblk_t block; | 1124 | ext4_fsblk_t block; |
| 1125 | int depth, ee_len; | 1125 | int depth; /* Note, NOT eh_depth; depth from top of tree */ |
| 1126 | int ee_len; | ||
| 1126 | 1127 | ||
| 1127 | BUG_ON(path == NULL); | 1128 | BUG_ON(path == NULL); |
| 1128 | depth = path->p_depth; | 1129 | depth = path->p_depth; |
| @@ -1179,7 +1180,8 @@ got_index: | |||
| 1179 | if (bh == NULL) | 1180 | if (bh == NULL) |
| 1180 | return -EIO; | 1181 | return -EIO; |
| 1181 | eh = ext_block_hdr(bh); | 1182 | eh = ext_block_hdr(bh); |
| 1182 | if (ext4_ext_check_header(inode, eh, depth)) { | 1183 | /* subtract from p_depth to get proper eh_depth */ |
| 1184 | if (ext4_ext_check_header(inode, eh, path->p_depth - depth)) { | ||
| 1183 | put_bh(bh); | 1185 | put_bh(bh); |
| 1184 | return -EIO; | 1186 | return -EIO; |
| 1185 | } | 1187 | } |
diff --git a/fs/ext4/ialloc.c b/fs/ext4/ialloc.c index f18a919be70b..2d2b3585ee91 100644 --- a/fs/ext4/ialloc.c +++ b/fs/ext4/ialloc.c | |||
| @@ -188,7 +188,7 @@ void ext4_free_inode(handle_t *handle, struct inode *inode) | |||
| 188 | struct ext4_group_desc *gdp; | 188 | struct ext4_group_desc *gdp; |
| 189 | struct ext4_super_block *es; | 189 | struct ext4_super_block *es; |
| 190 | struct ext4_sb_info *sbi; | 190 | struct ext4_sb_info *sbi; |
| 191 | int fatal = 0, err, count; | 191 | int fatal = 0, err, count, cleared; |
| 192 | ext4_group_t flex_group; | 192 | ext4_group_t flex_group; |
| 193 | 193 | ||
| 194 | if (atomic_read(&inode->i_count) > 1) { | 194 | if (atomic_read(&inode->i_count) > 1) { |
| @@ -248,8 +248,10 @@ void ext4_free_inode(handle_t *handle, struct inode *inode) | |||
| 248 | goto error_return; | 248 | goto error_return; |
| 249 | 249 | ||
| 250 | /* Ok, now we can actually update the inode bitmaps.. */ | 250 | /* Ok, now we can actually update the inode bitmaps.. */ |
| 251 | if (!ext4_clear_bit_atomic(sb_bgl_lock(sbi, block_group), | 251 | spin_lock(sb_bgl_lock(sbi, block_group)); |
| 252 | bit, bitmap_bh->b_data)) | 252 | cleared = ext4_clear_bit(bit, bitmap_bh->b_data); |
| 253 | spin_unlock(sb_bgl_lock(sbi, block_group)); | ||
| 254 | if (!cleared) | ||
| 253 | ext4_error(sb, "ext4_free_inode", | 255 | ext4_error(sb, "ext4_free_inode", |
| 254 | "bit already cleared for inode %lu", ino); | 256 | "bit already cleared for inode %lu", ino); |
| 255 | else { | 257 | else { |
| @@ -696,6 +698,7 @@ struct inode *ext4_new_inode(handle_t *handle, struct inode *dir, int mode) | |||
| 696 | struct inode *ret; | 698 | struct inode *ret; |
| 697 | ext4_group_t i; | 699 | ext4_group_t i; |
| 698 | int free = 0; | 700 | int free = 0; |
| 701 | static int once = 1; | ||
| 699 | ext4_group_t flex_group; | 702 | ext4_group_t flex_group; |
| 700 | 703 | ||
| 701 | /* Cannot create files in a deleted directory */ | 704 | /* Cannot create files in a deleted directory */ |
| @@ -717,7 +720,8 @@ struct inode *ext4_new_inode(handle_t *handle, struct inode *dir, int mode) | |||
| 717 | ret2 = find_group_flex(sb, dir, &group); | 720 | ret2 = find_group_flex(sb, dir, &group); |
| 718 | if (ret2 == -1) { | 721 | if (ret2 == -1) { |
| 719 | ret2 = find_group_other(sb, dir, &group); | 722 | ret2 = find_group_other(sb, dir, &group); |
| 720 | if (ret2 == 0 && printk_ratelimit()) | 723 | if (ret2 == 0 && once) |
| 724 | once = 0; | ||
| 721 | printk(KERN_NOTICE "ext4: find_group_flex " | 725 | printk(KERN_NOTICE "ext4: find_group_flex " |
| 722 | "failed, fallback succeeded dir %lu\n", | 726 | "failed, fallback succeeded dir %lu\n", |
| 723 | dir->i_ino); | 727 | dir->i_ino); |
diff --git a/fs/ext4/mballoc.c b/fs/ext4/mballoc.c index 4415beeb0b62..9f61e62f435f 100644 --- a/fs/ext4/mballoc.c +++ b/fs/ext4/mballoc.c | |||
| @@ -1447,7 +1447,7 @@ static void ext4_mb_measure_extent(struct ext4_allocation_context *ac, | |||
| 1447 | struct ext4_free_extent *gex = &ac->ac_g_ex; | 1447 | struct ext4_free_extent *gex = &ac->ac_g_ex; |
| 1448 | 1448 | ||
| 1449 | BUG_ON(ex->fe_len <= 0); | 1449 | BUG_ON(ex->fe_len <= 0); |
| 1450 | BUG_ON(ex->fe_len >= EXT4_BLOCKS_PER_GROUP(ac->ac_sb)); | 1450 | BUG_ON(ex->fe_len > EXT4_BLOCKS_PER_GROUP(ac->ac_sb)); |
| 1451 | BUG_ON(ex->fe_start >= EXT4_BLOCKS_PER_GROUP(ac->ac_sb)); | 1451 | BUG_ON(ex->fe_start >= EXT4_BLOCKS_PER_GROUP(ac->ac_sb)); |
| 1452 | BUG_ON(ac->ac_status != AC_STATUS_CONTINUE); | 1452 | BUG_ON(ac->ac_status != AC_STATUS_CONTINUE); |
| 1453 | 1453 | ||
| @@ -3292,7 +3292,7 @@ ext4_mb_normalize_request(struct ext4_allocation_context *ac, | |||
| 3292 | } | 3292 | } |
| 3293 | BUG_ON(start + size <= ac->ac_o_ex.fe_logical && | 3293 | BUG_ON(start + size <= ac->ac_o_ex.fe_logical && |
| 3294 | start > ac->ac_o_ex.fe_logical); | 3294 | start > ac->ac_o_ex.fe_logical); |
| 3295 | BUG_ON(size <= 0 || size >= EXT4_BLOCKS_PER_GROUP(ac->ac_sb)); | 3295 | BUG_ON(size <= 0 || size > EXT4_BLOCKS_PER_GROUP(ac->ac_sb)); |
| 3296 | 3296 | ||
| 3297 | /* now prepare goal request */ | 3297 | /* now prepare goal request */ |
| 3298 | 3298 | ||
| @@ -3589,6 +3589,7 @@ static void ext4_mb_put_pa(struct ext4_allocation_context *ac, | |||
| 3589 | struct super_block *sb, struct ext4_prealloc_space *pa) | 3589 | struct super_block *sb, struct ext4_prealloc_space *pa) |
| 3590 | { | 3590 | { |
| 3591 | ext4_group_t grp; | 3591 | ext4_group_t grp; |
| 3592 | ext4_fsblk_t grp_blk; | ||
| 3592 | 3593 | ||
| 3593 | if (!atomic_dec_and_test(&pa->pa_count) || pa->pa_free != 0) | 3594 | if (!atomic_dec_and_test(&pa->pa_count) || pa->pa_free != 0) |
| 3594 | return; | 3595 | return; |
| @@ -3603,8 +3604,12 @@ static void ext4_mb_put_pa(struct ext4_allocation_context *ac, | |||
| 3603 | pa->pa_deleted = 1; | 3604 | pa->pa_deleted = 1; |
| 3604 | spin_unlock(&pa->pa_lock); | 3605 | spin_unlock(&pa->pa_lock); |
| 3605 | 3606 | ||
| 3606 | /* -1 is to protect from crossing allocation group */ | 3607 | grp_blk = pa->pa_pstart; |
| 3607 | ext4_get_group_no_and_offset(sb, pa->pa_pstart - 1, &grp, NULL); | 3608 | /* If linear, pa_pstart may be in the next group when pa is used up */ |
| 3609 | if (pa->pa_linear) | ||
| 3610 | grp_blk--; | ||
| 3611 | |||
| 3612 | ext4_get_group_no_and_offset(sb, grp_blk, &grp, NULL); | ||
| 3608 | 3613 | ||
| 3609 | /* | 3614 | /* |
| 3610 | * possible race: | 3615 | * possible race: |
diff --git a/fs/fat/inode.c b/fs/fat/inode.c index 6b74d09adbe5..de0004fe6e00 100644 --- a/fs/fat/inode.c +++ b/fs/fat/inode.c | |||
| @@ -202,9 +202,9 @@ static sector_t _fat_bmap(struct address_space *mapping, sector_t block) | |||
| 202 | sector_t blocknr; | 202 | sector_t blocknr; |
| 203 | 203 | ||
| 204 | /* fat_get_cluster() assumes the requested blocknr isn't truncated. */ | 204 | /* fat_get_cluster() assumes the requested blocknr isn't truncated. */ |
| 205 | mutex_lock(&mapping->host->i_mutex); | 205 | down_read(&mapping->host->i_alloc_sem); |
| 206 | blocknr = generic_block_bmap(mapping, block, fat_get_block); | 206 | blocknr = generic_block_bmap(mapping, block, fat_get_block); |
| 207 | mutex_unlock(&mapping->host->i_mutex); | 207 | up_read(&mapping->host->i_alloc_sem); |
| 208 | 208 | ||
| 209 | return blocknr; | 209 | return blocknr; |
| 210 | } | 210 | } |
diff --git a/fs/fs-writeback.c b/fs/fs-writeback.c index e5eaa62fd17f..e3fe9918faaf 100644 --- a/fs/fs-writeback.c +++ b/fs/fs-writeback.c | |||
| @@ -274,6 +274,7 @@ __sync_single_inode(struct inode *inode, struct writeback_control *wbc) | |||
| 274 | int ret; | 274 | int ret; |
| 275 | 275 | ||
| 276 | BUG_ON(inode->i_state & I_SYNC); | 276 | BUG_ON(inode->i_state & I_SYNC); |
| 277 | WARN_ON(inode->i_state & I_NEW); | ||
| 277 | 278 | ||
| 278 | /* Set I_SYNC, reset I_DIRTY */ | 279 | /* Set I_SYNC, reset I_DIRTY */ |
| 279 | dirty = inode->i_state & I_DIRTY; | 280 | dirty = inode->i_state & I_DIRTY; |
| @@ -298,6 +299,7 @@ __sync_single_inode(struct inode *inode, struct writeback_control *wbc) | |||
| 298 | } | 299 | } |
| 299 | 300 | ||
| 300 | spin_lock(&inode_lock); | 301 | spin_lock(&inode_lock); |
| 302 | WARN_ON(inode->i_state & I_NEW); | ||
| 301 | inode->i_state &= ~I_SYNC; | 303 | inode->i_state &= ~I_SYNC; |
| 302 | if (!(inode->i_state & I_FREEING)) { | 304 | if (!(inode->i_state & I_FREEING)) { |
| 303 | if (!(inode->i_state & I_DIRTY) && | 305 | if (!(inode->i_state & I_DIRTY) && |
| @@ -470,6 +472,11 @@ void generic_sync_sb_inodes(struct super_block *sb, | |||
| 470 | break; | 472 | break; |
| 471 | } | 473 | } |
| 472 | 474 | ||
| 475 | if (inode->i_state & I_NEW) { | ||
| 476 | requeue_io(inode); | ||
| 477 | continue; | ||
| 478 | } | ||
| 479 | |||
| 473 | if (wbc->nonblocking && bdi_write_congested(bdi)) { | 480 | if (wbc->nonblocking && bdi_write_congested(bdi)) { |
| 474 | wbc->encountered_congestion = 1; | 481 | wbc->encountered_congestion = 1; |
| 475 | if (!sb_is_blkdev_sb(sb)) | 482 | if (!sb_is_blkdev_sb(sb)) |
| @@ -531,7 +538,7 @@ void generic_sync_sb_inodes(struct super_block *sb, | |||
| 531 | list_for_each_entry(inode, &sb->s_inodes, i_sb_list) { | 538 | list_for_each_entry(inode, &sb->s_inodes, i_sb_list) { |
| 532 | struct address_space *mapping; | 539 | struct address_space *mapping; |
| 533 | 540 | ||
| 534 | if (inode->i_state & (I_FREEING|I_WILL_FREE)) | 541 | if (inode->i_state & (I_FREEING|I_WILL_FREE|I_NEW)) |
| 535 | continue; | 542 | continue; |
| 536 | mapping = inode->i_mapping; | 543 | mapping = inode->i_mapping; |
| 537 | if (mapping->nrpages == 0) | 544 | if (mapping->nrpages == 0) |
diff --git a/fs/inode.c b/fs/inode.c index 913ab2d9a5d1..826fb0b9d1c3 100644 --- a/fs/inode.c +++ b/fs/inode.c | |||
| @@ -359,6 +359,7 @@ static int invalidate_list(struct list_head *head, struct list_head *dispose) | |||
| 359 | invalidate_inode_buffers(inode); | 359 | invalidate_inode_buffers(inode); |
| 360 | if (!atomic_read(&inode->i_count)) { | 360 | if (!atomic_read(&inode->i_count)) { |
| 361 | list_move(&inode->i_list, dispose); | 361 | list_move(&inode->i_list, dispose); |
| 362 | WARN_ON(inode->i_state & I_NEW); | ||
| 362 | inode->i_state |= I_FREEING; | 363 | inode->i_state |= I_FREEING; |
| 363 | count++; | 364 | count++; |
| 364 | continue; | 365 | continue; |
| @@ -460,6 +461,7 @@ static void prune_icache(int nr_to_scan) | |||
| 460 | continue; | 461 | continue; |
| 461 | } | 462 | } |
| 462 | list_move(&inode->i_list, &freeable); | 463 | list_move(&inode->i_list, &freeable); |
| 464 | WARN_ON(inode->i_state & I_NEW); | ||
| 463 | inode->i_state |= I_FREEING; | 465 | inode->i_state |= I_FREEING; |
| 464 | nr_pruned++; | 466 | nr_pruned++; |
| 465 | } | 467 | } |
| @@ -656,6 +658,7 @@ void unlock_new_inode(struct inode *inode) | |||
| 656 | * just created it (so there can be no old holders | 658 | * just created it (so there can be no old holders |
| 657 | * that haven't tested I_LOCK). | 659 | * that haven't tested I_LOCK). |
| 658 | */ | 660 | */ |
| 661 | WARN_ON((inode->i_state & (I_LOCK|I_NEW)) != (I_LOCK|I_NEW)); | ||
| 659 | inode->i_state &= ~(I_LOCK|I_NEW); | 662 | inode->i_state &= ~(I_LOCK|I_NEW); |
| 660 | wake_up_inode(inode); | 663 | wake_up_inode(inode); |
| 661 | } | 664 | } |
| @@ -1145,6 +1148,7 @@ void generic_delete_inode(struct inode *inode) | |||
| 1145 | 1148 | ||
| 1146 | list_del_init(&inode->i_list); | 1149 | list_del_init(&inode->i_list); |
| 1147 | list_del_init(&inode->i_sb_list); | 1150 | list_del_init(&inode->i_sb_list); |
| 1151 | WARN_ON(inode->i_state & I_NEW); | ||
| 1148 | inode->i_state |= I_FREEING; | 1152 | inode->i_state |= I_FREEING; |
| 1149 | inodes_stat.nr_inodes--; | 1153 | inodes_stat.nr_inodes--; |
| 1150 | spin_unlock(&inode_lock); | 1154 | spin_unlock(&inode_lock); |
| @@ -1186,16 +1190,19 @@ static void generic_forget_inode(struct inode *inode) | |||
| 1186 | spin_unlock(&inode_lock); | 1190 | spin_unlock(&inode_lock); |
| 1187 | return; | 1191 | return; |
| 1188 | } | 1192 | } |
| 1193 | WARN_ON(inode->i_state & I_NEW); | ||
| 1189 | inode->i_state |= I_WILL_FREE; | 1194 | inode->i_state |= I_WILL_FREE; |
| 1190 | spin_unlock(&inode_lock); | 1195 | spin_unlock(&inode_lock); |
| 1191 | write_inode_now(inode, 1); | 1196 | write_inode_now(inode, 1); |
| 1192 | spin_lock(&inode_lock); | 1197 | spin_lock(&inode_lock); |
| 1198 | WARN_ON(inode->i_state & I_NEW); | ||
| 1193 | inode->i_state &= ~I_WILL_FREE; | 1199 | inode->i_state &= ~I_WILL_FREE; |
| 1194 | inodes_stat.nr_unused--; | 1200 | inodes_stat.nr_unused--; |
| 1195 | hlist_del_init(&inode->i_hash); | 1201 | hlist_del_init(&inode->i_hash); |
| 1196 | } | 1202 | } |
| 1197 | list_del_init(&inode->i_list); | 1203 | list_del_init(&inode->i_list); |
| 1198 | list_del_init(&inode->i_sb_list); | 1204 | list_del_init(&inode->i_sb_list); |
| 1205 | WARN_ON(inode->i_state & I_NEW); | ||
| 1199 | inode->i_state |= I_FREEING; | 1206 | inode->i_state |= I_FREEING; |
| 1200 | inodes_stat.nr_inodes--; | 1207 | inodes_stat.nr_inodes--; |
| 1201 | spin_unlock(&inode_lock); | 1208 | spin_unlock(&inode_lock); |
diff --git a/fs/lockd/clntlock.c b/fs/lockd/clntlock.c index 1f3b0fc0d351..aedc47a264c1 100644 --- a/fs/lockd/clntlock.c +++ b/fs/lockd/clntlock.c | |||
| @@ -139,6 +139,55 @@ int nlmclnt_block(struct nlm_wait *block, struct nlm_rqst *req, long timeout) | |||
| 139 | return 0; | 139 | return 0; |
| 140 | } | 140 | } |
| 141 | 141 | ||
| 142 | #if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) | ||
| 143 | static const struct in6_addr *nlmclnt_map_v4addr(const struct sockaddr *sap, | ||
| 144 | struct in6_addr *addr_mapped) | ||
| 145 | { | ||
| 146 | const struct sockaddr_in *sin = (const struct sockaddr_in *)sap; | ||
| 147 | |||
| 148 | switch (sap->sa_family) { | ||
| 149 | case AF_INET6: | ||
| 150 | return &((const struct sockaddr_in6 *)sap)->sin6_addr; | ||
| 151 | case AF_INET: | ||
| 152 | ipv6_addr_set_v4mapped(sin->sin_addr.s_addr, addr_mapped); | ||
| 153 | return addr_mapped; | ||
| 154 | } | ||
| 155 | |||
| 156 | return NULL; | ||
| 157 | } | ||
| 158 | |||
| 159 | /* | ||
| 160 | * If lockd is using a PF_INET6 listener, all incoming requests appear | ||
| 161 | * to come from AF_INET6 remotes. The address of AF_INET remotes are | ||
| 162 | * mapped to AF_INET6 automatically by the network layer. In case the | ||
| 163 | * user passed an AF_INET server address at mount time, ensure both | ||
| 164 | * addresses are AF_INET6 before comparing them. | ||
| 165 | */ | ||
| 166 | static int nlmclnt_cmp_addr(const struct nlm_host *host, | ||
| 167 | const struct sockaddr *sap) | ||
| 168 | { | ||
| 169 | const struct in6_addr *addr1; | ||
| 170 | const struct in6_addr *addr2; | ||
| 171 | struct in6_addr addr1_mapped; | ||
| 172 | struct in6_addr addr2_mapped; | ||
| 173 | |||
| 174 | addr1 = nlmclnt_map_v4addr(nlm_addr(host), &addr1_mapped); | ||
| 175 | if (likely(addr1 != NULL)) { | ||
| 176 | addr2 = nlmclnt_map_v4addr(sap, &addr2_mapped); | ||
| 177 | if (likely(addr2 != NULL)) | ||
| 178 | return ipv6_addr_equal(addr1, addr2); | ||
| 179 | } | ||
| 180 | |||
| 181 | return 0; | ||
| 182 | } | ||
| 183 | #else /* !(CONFIG_IPV6 || CONFIG_IPV6_MODULE) */ | ||
| 184 | static int nlmclnt_cmp_addr(const struct nlm_host *host, | ||
| 185 | const struct sockaddr *sap) | ||
| 186 | { | ||
| 187 | return nlm_cmp_addr(nlm_addr(host), sap); | ||
| 188 | } | ||
| 189 | #endif /* !(CONFIG_IPV6 || CONFIG_IPV6_MODULE) */ | ||
| 190 | |||
| 142 | /* | 191 | /* |
| 143 | * The server lockd has called us back to tell us the lock was granted | 192 | * The server lockd has called us back to tell us the lock was granted |
| 144 | */ | 193 | */ |
| @@ -166,7 +215,7 @@ __be32 nlmclnt_grant(const struct sockaddr *addr, const struct nlm_lock *lock) | |||
| 166 | */ | 215 | */ |
| 167 | if (fl_blocked->fl_u.nfs_fl.owner->pid != lock->svid) | 216 | if (fl_blocked->fl_u.nfs_fl.owner->pid != lock->svid) |
| 168 | continue; | 217 | continue; |
| 169 | if (!nlm_cmp_addr(nlm_addr(block->b_host), addr)) | 218 | if (!nlmclnt_cmp_addr(block->b_host, addr)) |
| 170 | continue; | 219 | continue; |
| 171 | if (nfs_compare_fh(NFS_FH(fl_blocked->fl_file->f_path.dentry->d_inode) ,fh) != 0) | 220 | if (nfs_compare_fh(NFS_FH(fl_blocked->fl_file->f_path.dentry->d_inode) ,fh) != 0) |
| 172 | continue; | 221 | continue; |
diff --git a/fs/minix/inode.c b/fs/minix/inode.c index d1d1eb84679d..618865b3128b 100644 --- a/fs/minix/inode.c +++ b/fs/minix/inode.c | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | * | 3 | * |
| 4 | * Copyright (C) 1991, 1992 Linus Torvalds | 4 | * Copyright (C) 1991, 1992 Linus Torvalds |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 1996 Gertjan van Wingerde (gertjan@cs.vu.nl) | 6 | * Copyright (C) 1996 Gertjan van Wingerde |
| 7 | * Minix V2 fs support. | 7 | * Minix V2 fs support. |
| 8 | * | 8 | * |
| 9 | * Modified for 680x0 by Andreas Schwab | 9 | * Modified for 680x0 by Andreas Schwab |
diff --git a/fs/nfs/client.c b/fs/nfs/client.c index 9b728f3565a1..574158ae2398 100644 --- a/fs/nfs/client.c +++ b/fs/nfs/client.c | |||
| @@ -255,6 +255,32 @@ static int nfs_sockaddr_match_ipaddr(const struct sockaddr *sa1, | |||
| 255 | } | 255 | } |
| 256 | return 0; | 256 | return 0; |
| 257 | } | 257 | } |
| 258 | |||
| 259 | /* | ||
| 260 | * Test if two ip6 socket addresses refer to the same socket by | ||
| 261 | * comparing relevant fields. The padding bytes specifically, are not | ||
| 262 | * compared. sin6_flowinfo is not compared because it only affects QoS | ||
| 263 | * and sin6_scope_id is only compared if the address is "link local" | ||
| 264 | * because "link local" addresses need only be unique to a specific | ||
| 265 | * link. Conversely, ordinary unicast addresses might have different | ||
| 266 | * sin6_scope_id. | ||
| 267 | * | ||
| 268 | * The caller should ensure both socket addresses are AF_INET6. | ||
| 269 | */ | ||
| 270 | static int nfs_sockaddr_cmp_ip6(const struct sockaddr *sa1, | ||
| 271 | const struct sockaddr *sa2) | ||
| 272 | { | ||
| 273 | const struct sockaddr_in6 *saddr1 = (const struct sockaddr_in6 *)sa1; | ||
| 274 | const struct sockaddr_in6 *saddr2 = (const struct sockaddr_in6 *)sa2; | ||
| 275 | |||
| 276 | if (!ipv6_addr_equal(&saddr1->sin6_addr, | ||
| 277 | &saddr1->sin6_addr)) | ||
| 278 | return 0; | ||
| 279 | if (ipv6_addr_scope(&saddr1->sin6_addr) == IPV6_ADDR_SCOPE_LINKLOCAL && | ||
| 280 | saddr1->sin6_scope_id != saddr2->sin6_scope_id) | ||
| 281 | return 0; | ||
| 282 | return saddr1->sin6_port == saddr2->sin6_port; | ||
| 283 | } | ||
| 258 | #else | 284 | #else |
| 259 | static int nfs_sockaddr_match_ipaddr4(const struct sockaddr_in *sa1, | 285 | static int nfs_sockaddr_match_ipaddr4(const struct sockaddr_in *sa1, |
| 260 | const struct sockaddr_in *sa2) | 286 | const struct sockaddr_in *sa2) |
| @@ -270,9 +296,52 @@ static int nfs_sockaddr_match_ipaddr(const struct sockaddr *sa1, | |||
| 270 | return nfs_sockaddr_match_ipaddr4((const struct sockaddr_in *)sa1, | 296 | return nfs_sockaddr_match_ipaddr4((const struct sockaddr_in *)sa1, |
| 271 | (const struct sockaddr_in *)sa2); | 297 | (const struct sockaddr_in *)sa2); |
| 272 | } | 298 | } |
| 299 | |||
| 300 | static int nfs_sockaddr_cmp_ip6(const struct sockaddr * sa1, | ||
| 301 | const struct sockaddr * sa2) | ||
| 302 | { | ||
| 303 | return 0; | ||
| 304 | } | ||
| 273 | #endif | 305 | #endif |
| 274 | 306 | ||
| 275 | /* | 307 | /* |
| 308 | * Test if two ip4 socket addresses refer to the same socket, by | ||
| 309 | * comparing relevant fields. The padding bytes specifically, are | ||
| 310 | * not compared. | ||
| 311 | * | ||
| 312 | * The caller should ensure both socket addresses are AF_INET. | ||
| 313 | */ | ||
| 314 | static int nfs_sockaddr_cmp_ip4(const struct sockaddr *sa1, | ||
| 315 | const struct sockaddr *sa2) | ||
| 316 | { | ||
| 317 | const struct sockaddr_in *saddr1 = (const struct sockaddr_in *)sa1; | ||
| 318 | const struct sockaddr_in *saddr2 = (const struct sockaddr_in *)sa2; | ||
| 319 | |||
| 320 | if (saddr1->sin_addr.s_addr != saddr2->sin_addr.s_addr) | ||
| 321 | return 0; | ||
| 322 | return saddr1->sin_port == saddr2->sin_port; | ||
| 323 | } | ||
| 324 | |||
| 325 | /* | ||
| 326 | * Test if two socket addresses represent the same actual socket, | ||
| 327 | * by comparing (only) relevant fields. | ||
| 328 | */ | ||
| 329 | static int nfs_sockaddr_cmp(const struct sockaddr *sa1, | ||
| 330 | const struct sockaddr *sa2) | ||
| 331 | { | ||
| 332 | if (sa1->sa_family != sa2->sa_family) | ||
| 333 | return 0; | ||
| 334 | |||
| 335 | switch (sa1->sa_family) { | ||
| 336 | case AF_INET: | ||
| 337 | return nfs_sockaddr_cmp_ip4(sa1, sa2); | ||
| 338 | case AF_INET6: | ||
| 339 | return nfs_sockaddr_cmp_ip6(sa1, sa2); | ||
| 340 | } | ||
| 341 | return 0; | ||
| 342 | } | ||
| 343 | |||
| 344 | /* | ||
| 276 | * Find a client by IP address and protocol version | 345 | * Find a client by IP address and protocol version |
| 277 | * - returns NULL if no such client | 346 | * - returns NULL if no such client |
| 278 | */ | 347 | */ |
| @@ -344,8 +413,10 @@ struct nfs_client *nfs_find_client_next(struct nfs_client *clp) | |||
| 344 | static struct nfs_client *nfs_match_client(const struct nfs_client_initdata *data) | 413 | static struct nfs_client *nfs_match_client(const struct nfs_client_initdata *data) |
| 345 | { | 414 | { |
| 346 | struct nfs_client *clp; | 415 | struct nfs_client *clp; |
| 416 | const struct sockaddr *sap = data->addr; | ||
| 347 | 417 | ||
| 348 | list_for_each_entry(clp, &nfs_client_list, cl_share_link) { | 418 | list_for_each_entry(clp, &nfs_client_list, cl_share_link) { |
| 419 | const struct sockaddr *clap = (struct sockaddr *)&clp->cl_addr; | ||
| 349 | /* Don't match clients that failed to initialise properly */ | 420 | /* Don't match clients that failed to initialise properly */ |
| 350 | if (clp->cl_cons_state < 0) | 421 | if (clp->cl_cons_state < 0) |
| 351 | continue; | 422 | continue; |
| @@ -358,7 +429,7 @@ static struct nfs_client *nfs_match_client(const struct nfs_client_initdata *dat | |||
| 358 | continue; | 429 | continue; |
| 359 | 430 | ||
| 360 | /* Match the full socket address */ | 431 | /* Match the full socket address */ |
| 361 | if (memcmp(&clp->cl_addr, data->addr, sizeof(clp->cl_addr)) != 0) | 432 | if (!nfs_sockaddr_cmp(sap, clap)) |
| 362 | continue; | 433 | continue; |
| 363 | 434 | ||
| 364 | atomic_inc(&clp->cl_count); | 435 | atomic_inc(&clp->cl_count); |
diff --git a/fs/nfs/dir.c b/fs/nfs/dir.c index e35c8199f82f..672368f865ca 100644 --- a/fs/nfs/dir.c +++ b/fs/nfs/dir.c | |||
| @@ -1892,8 +1892,14 @@ static int nfs_do_access(struct inode *inode, struct rpc_cred *cred, int mask) | |||
| 1892 | cache.cred = cred; | 1892 | cache.cred = cred; |
| 1893 | cache.jiffies = jiffies; | 1893 | cache.jiffies = jiffies; |
| 1894 | status = NFS_PROTO(inode)->access(inode, &cache); | 1894 | status = NFS_PROTO(inode)->access(inode, &cache); |
| 1895 | if (status != 0) | 1895 | if (status != 0) { |
| 1896 | if (status == -ESTALE) { | ||
| 1897 | nfs_zap_caches(inode); | ||
| 1898 | if (!S_ISDIR(inode->i_mode)) | ||
| 1899 | set_bit(NFS_INO_STALE, &NFS_I(inode)->flags); | ||
| 1900 | } | ||
| 1896 | return status; | 1901 | return status; |
| 1902 | } | ||
| 1897 | nfs_access_add_cache(inode, &cache); | 1903 | nfs_access_add_cache(inode, &cache); |
| 1898 | out: | 1904 | out: |
| 1899 | if ((mask & ~cache.mask & (MAY_READ | MAY_WRITE | MAY_EXEC)) == 0) | 1905 | if ((mask & ~cache.mask & (MAY_READ | MAY_WRITE | MAY_EXEC)) == 0) |
diff --git a/fs/nfs/nfs3acl.c b/fs/nfs/nfs3acl.c index cef62557c87d..6bbf0e6daad2 100644 --- a/fs/nfs/nfs3acl.c +++ b/fs/nfs/nfs3acl.c | |||
| @@ -292,7 +292,7 @@ static int nfs3_proc_setacls(struct inode *inode, struct posix_acl *acl, | |||
| 292 | { | 292 | { |
| 293 | struct nfs_server *server = NFS_SERVER(inode); | 293 | struct nfs_server *server = NFS_SERVER(inode); |
| 294 | struct nfs_fattr fattr; | 294 | struct nfs_fattr fattr; |
| 295 | struct page *pages[NFSACL_MAXPAGES] = { }; | 295 | struct page *pages[NFSACL_MAXPAGES]; |
| 296 | struct nfs3_setaclargs args = { | 296 | struct nfs3_setaclargs args = { |
| 297 | .inode = inode, | 297 | .inode = inode, |
| 298 | .mask = NFS_ACL, | 298 | .mask = NFS_ACL, |
| @@ -303,7 +303,7 @@ static int nfs3_proc_setacls(struct inode *inode, struct posix_acl *acl, | |||
| 303 | .rpc_argp = &args, | 303 | .rpc_argp = &args, |
| 304 | .rpc_resp = &fattr, | 304 | .rpc_resp = &fattr, |
| 305 | }; | 305 | }; |
| 306 | int status, count; | 306 | int status; |
| 307 | 307 | ||
| 308 | status = -EOPNOTSUPP; | 308 | status = -EOPNOTSUPP; |
| 309 | if (!nfs_server_capable(inode, NFS_CAP_ACLS)) | 309 | if (!nfs_server_capable(inode, NFS_CAP_ACLS)) |
| @@ -319,6 +319,20 @@ static int nfs3_proc_setacls(struct inode *inode, struct posix_acl *acl, | |||
| 319 | if (S_ISDIR(inode->i_mode)) { | 319 | if (S_ISDIR(inode->i_mode)) { |
| 320 | args.mask |= NFS_DFACL; | 320 | args.mask |= NFS_DFACL; |
| 321 | args.acl_default = dfacl; | 321 | args.acl_default = dfacl; |
| 322 | args.len = nfsacl_size(acl, dfacl); | ||
| 323 | } else | ||
| 324 | args.len = nfsacl_size(acl, NULL); | ||
| 325 | |||
| 326 | if (args.len > NFS_ACL_INLINE_BUFSIZE) { | ||
| 327 | unsigned int npages = 1 + ((args.len - 1) >> PAGE_SHIFT); | ||
| 328 | |||
| 329 | status = -ENOMEM; | ||
| 330 | do { | ||
| 331 | args.pages[args.npages] = alloc_page(GFP_KERNEL); | ||
| 332 | if (args.pages[args.npages] == NULL) | ||
| 333 | goto out_freepages; | ||
| 334 | args.npages++; | ||
| 335 | } while (args.npages < npages); | ||
| 322 | } | 336 | } |
| 323 | 337 | ||
| 324 | dprintk("NFS call setacl\n"); | 338 | dprintk("NFS call setacl\n"); |
| @@ -329,10 +343,6 @@ static int nfs3_proc_setacls(struct inode *inode, struct posix_acl *acl, | |||
| 329 | nfs_zap_acl_cache(inode); | 343 | nfs_zap_acl_cache(inode); |
| 330 | dprintk("NFS reply setacl: %d\n", status); | 344 | dprintk("NFS reply setacl: %d\n", status); |
| 331 | 345 | ||
| 332 | /* pages may have been allocated at the xdr layer. */ | ||
| 333 | for (count = 0; count < NFSACL_MAXPAGES && args.pages[count]; count++) | ||
| 334 | __free_page(args.pages[count]); | ||
| 335 | |||
| 336 | switch (status) { | 346 | switch (status) { |
| 337 | case 0: | 347 | case 0: |
| 338 | status = nfs_refresh_inode(inode, &fattr); | 348 | status = nfs_refresh_inode(inode, &fattr); |
| @@ -346,6 +356,11 @@ static int nfs3_proc_setacls(struct inode *inode, struct posix_acl *acl, | |||
| 346 | case -ENOTSUPP: | 356 | case -ENOTSUPP: |
| 347 | status = -EOPNOTSUPP; | 357 | status = -EOPNOTSUPP; |
| 348 | } | 358 | } |
| 359 | out_freepages: | ||
| 360 | while (args.npages != 0) { | ||
| 361 | args.npages--; | ||
| 362 | __free_page(args.pages[args.npages]); | ||
| 363 | } | ||
| 349 | out: | 364 | out: |
| 350 | return status; | 365 | return status; |
| 351 | } | 366 | } |
diff --git a/fs/nfs/nfs3xdr.c b/fs/nfs/nfs3xdr.c index 11cdddec1432..6cdeacffde46 100644 --- a/fs/nfs/nfs3xdr.c +++ b/fs/nfs/nfs3xdr.c | |||
| @@ -82,8 +82,10 @@ | |||
| 82 | #define NFS3_commitres_sz (1+NFS3_wcc_data_sz+2) | 82 | #define NFS3_commitres_sz (1+NFS3_wcc_data_sz+2) |
| 83 | 83 | ||
| 84 | #define ACL3_getaclargs_sz (NFS3_fh_sz+1) | 84 | #define ACL3_getaclargs_sz (NFS3_fh_sz+1) |
| 85 | #define ACL3_setaclargs_sz (NFS3_fh_sz+1+2*(2+5*3)) | 85 | #define ACL3_setaclargs_sz (NFS3_fh_sz+1+ \ |
| 86 | #define ACL3_getaclres_sz (1+NFS3_post_op_attr_sz+1+2*(2+5*3)) | 86 | XDR_QUADLEN(NFS_ACL_INLINE_BUFSIZE)) |
| 87 | #define ACL3_getaclres_sz (1+NFS3_post_op_attr_sz+1+ \ | ||
| 88 | XDR_QUADLEN(NFS_ACL_INLINE_BUFSIZE)) | ||
| 87 | #define ACL3_setaclres_sz (1+NFS3_post_op_attr_sz) | 89 | #define ACL3_setaclres_sz (1+NFS3_post_op_attr_sz) |
| 88 | 90 | ||
| 89 | /* | 91 | /* |
| @@ -703,28 +705,18 @@ nfs3_xdr_setaclargs(struct rpc_rqst *req, __be32 *p, | |||
| 703 | struct nfs3_setaclargs *args) | 705 | struct nfs3_setaclargs *args) |
| 704 | { | 706 | { |
| 705 | struct xdr_buf *buf = &req->rq_snd_buf; | 707 | struct xdr_buf *buf = &req->rq_snd_buf; |
| 706 | unsigned int base, len_in_head, len = nfsacl_size( | 708 | unsigned int base; |
| 707 | (args->mask & NFS_ACL) ? args->acl_access : NULL, | 709 | int err; |
| 708 | (args->mask & NFS_DFACL) ? args->acl_default : NULL); | ||
| 709 | int count, err; | ||
| 710 | 710 | ||
| 711 | p = xdr_encode_fhandle(p, NFS_FH(args->inode)); | 711 | p = xdr_encode_fhandle(p, NFS_FH(args->inode)); |
| 712 | *p++ = htonl(args->mask); | 712 | *p++ = htonl(args->mask); |
| 713 | base = (char *)p - (char *)buf->head->iov_base; | 713 | req->rq_slen = xdr_adjust_iovec(req->rq_svec, p); |
| 714 | /* put as much of the acls into head as possible. */ | 714 | base = req->rq_slen; |
| 715 | len_in_head = min_t(unsigned int, buf->head->iov_len - base, len); | 715 | |
| 716 | len -= len_in_head; | 716 | if (args->npages != 0) |
| 717 | req->rq_slen = xdr_adjust_iovec(req->rq_svec, p + (len_in_head >> 2)); | 717 | xdr_encode_pages(buf, args->pages, 0, args->len); |
| 718 | 718 | else | |
| 719 | for (count = 0; (count << PAGE_SHIFT) < len; count++) { | 719 | req->rq_slen += args->len; |
| 720 | args->pages[count] = alloc_page(GFP_KERNEL); | ||
| 721 | if (!args->pages[count]) { | ||
| 722 | while (count) | ||
| 723 | __free_page(args->pages[--count]); | ||
| 724 | return -ENOMEM; | ||
| 725 | } | ||
| 726 | } | ||
| 727 | xdr_encode_pages(buf, args->pages, 0, len); | ||
| 728 | 720 | ||
| 729 | err = nfsacl_encode(buf, base, args->inode, | 721 | err = nfsacl_encode(buf, base, args->inode, |
| 730 | (args->mask & NFS_ACL) ? | 722 | (args->mask & NFS_ACL) ? |
diff --git a/fs/nfs/nfs4namespace.c b/fs/nfs/nfs4namespace.c index 30befc39b3c6..2a2a0a7143ad 100644 --- a/fs/nfs/nfs4namespace.c +++ b/fs/nfs/nfs4namespace.c | |||
| @@ -21,7 +21,9 @@ | |||
| 21 | #define NFSDBG_FACILITY NFSDBG_VFS | 21 | #define NFSDBG_FACILITY NFSDBG_VFS |
| 22 | 22 | ||
| 23 | /* | 23 | /* |
| 24 | * Check if fs_root is valid | 24 | * Convert the NFSv4 pathname components into a standard posix path. |
| 25 | * | ||
| 26 | * Note that the resulting string will be placed at the end of the buffer | ||
| 25 | */ | 27 | */ |
| 26 | static inline char *nfs4_pathname_string(const struct nfs4_pathname *pathname, | 28 | static inline char *nfs4_pathname_string(const struct nfs4_pathname *pathname, |
| 27 | char *buffer, ssize_t buflen) | 29 | char *buffer, ssize_t buflen) |
| @@ -99,21 +101,20 @@ static struct vfsmount *try_location(struct nfs_clone_mount *mountdata, | |||
| 99 | { | 101 | { |
| 100 | struct vfsmount *mnt = ERR_PTR(-ENOENT); | 102 | struct vfsmount *mnt = ERR_PTR(-ENOENT); |
| 101 | char *mnt_path; | 103 | char *mnt_path; |
| 102 | int page2len; | 104 | unsigned int maxbuflen; |
| 103 | unsigned int s; | 105 | unsigned int s; |
| 104 | 106 | ||
| 105 | mnt_path = nfs4_pathname_string(&location->rootpath, page2, PAGE_SIZE); | 107 | mnt_path = nfs4_pathname_string(&location->rootpath, page2, PAGE_SIZE); |
| 106 | if (IS_ERR(mnt_path)) | 108 | if (IS_ERR(mnt_path)) |
| 107 | return mnt; | 109 | return mnt; |
| 108 | mountdata->mnt_path = mnt_path; | 110 | mountdata->mnt_path = mnt_path; |
| 109 | page2 += strlen(mnt_path) + 1; | 111 | maxbuflen = mnt_path - 1 - page2; |
| 110 | page2len = PAGE_SIZE - strlen(mnt_path) - 1; | ||
| 111 | 112 | ||
| 112 | for (s = 0; s < location->nservers; s++) { | 113 | for (s = 0; s < location->nservers; s++) { |
| 113 | const struct nfs4_string *buf = &location->servers[s]; | 114 | const struct nfs4_string *buf = &location->servers[s]; |
| 114 | struct sockaddr_storage addr; | 115 | struct sockaddr_storage addr; |
| 115 | 116 | ||
| 116 | if (buf->len <= 0 || buf->len >= PAGE_SIZE) | 117 | if (buf->len <= 0 || buf->len >= maxbuflen) |
| 117 | continue; | 118 | continue; |
| 118 | 119 | ||
| 119 | mountdata->addr = (struct sockaddr *)&addr; | 120 | mountdata->addr = (struct sockaddr *)&addr; |
| @@ -126,8 +127,8 @@ static struct vfsmount *try_location(struct nfs_clone_mount *mountdata, | |||
| 126 | continue; | 127 | continue; |
| 127 | nfs_set_port(mountdata->addr, NFS_PORT); | 128 | nfs_set_port(mountdata->addr, NFS_PORT); |
| 128 | 129 | ||
| 129 | strncpy(page2, buf->data, page2len); | 130 | memcpy(page2, buf->data, buf->len); |
| 130 | page2[page2len] = '\0'; | 131 | page2[buf->len] = '\0'; |
| 131 | mountdata->hostname = page2; | 132 | mountdata->hostname = page2; |
| 132 | 133 | ||
| 133 | snprintf(page, PAGE_SIZE, "%s:%s", | 134 | snprintf(page, PAGE_SIZE, "%s:%s", |
diff --git a/fs/nfsd/nfs4xdr.c b/fs/nfsd/nfs4xdr.c index f65953be39c0..9250067943d8 100644 --- a/fs/nfsd/nfs4xdr.c +++ b/fs/nfsd/nfs4xdr.c | |||
| @@ -2596,6 +2596,7 @@ static nfsd4_enc nfsd4_enc_ops[] = { | |||
| 2596 | [OP_LOOKUPP] = (nfsd4_enc)nfsd4_encode_noop, | 2596 | [OP_LOOKUPP] = (nfsd4_enc)nfsd4_encode_noop, |
| 2597 | [OP_NVERIFY] = (nfsd4_enc)nfsd4_encode_noop, | 2597 | [OP_NVERIFY] = (nfsd4_enc)nfsd4_encode_noop, |
| 2598 | [OP_OPEN] = (nfsd4_enc)nfsd4_encode_open, | 2598 | [OP_OPEN] = (nfsd4_enc)nfsd4_encode_open, |
| 2599 | [OP_OPENATTR] = (nfsd4_enc)nfsd4_encode_noop, | ||
| 2599 | [OP_OPEN_CONFIRM] = (nfsd4_enc)nfsd4_encode_open_confirm, | 2600 | [OP_OPEN_CONFIRM] = (nfsd4_enc)nfsd4_encode_open_confirm, |
| 2600 | [OP_OPEN_DOWNGRADE] = (nfsd4_enc)nfsd4_encode_open_downgrade, | 2601 | [OP_OPEN_DOWNGRADE] = (nfsd4_enc)nfsd4_encode_open_downgrade, |
| 2601 | [OP_PUTFH] = (nfsd4_enc)nfsd4_encode_noop, | 2602 | [OP_PUTFH] = (nfsd4_enc)nfsd4_encode_noop, |
diff --git a/fs/ocfs2/alloc.c b/fs/ocfs2/alloc.c index 3a9e5deed74d..19e3a96aa02c 100644 --- a/fs/ocfs2/alloc.c +++ b/fs/ocfs2/alloc.c | |||
| @@ -176,7 +176,8 @@ static int ocfs2_dinode_insert_check(struct inode *inode, | |||
| 176 | 176 | ||
| 177 | BUG_ON(OCFS2_I(inode)->ip_dyn_features & OCFS2_INLINE_DATA_FL); | 177 | BUG_ON(OCFS2_I(inode)->ip_dyn_features & OCFS2_INLINE_DATA_FL); |
| 178 | mlog_bug_on_msg(!ocfs2_sparse_alloc(osb) && | 178 | mlog_bug_on_msg(!ocfs2_sparse_alloc(osb) && |
| 179 | (OCFS2_I(inode)->ip_clusters != rec->e_cpos), | 179 | (OCFS2_I(inode)->ip_clusters != |
| 180 | le32_to_cpu(rec->e_cpos)), | ||
| 180 | "Device %s, asking for sparse allocation: inode %llu, " | 181 | "Device %s, asking for sparse allocation: inode %llu, " |
| 181 | "cpos %u, clusters %u\n", | 182 | "cpos %u, clusters %u\n", |
| 182 | osb->dev_str, | 183 | osb->dev_str, |
diff --git a/fs/ocfs2/aops.c b/fs/ocfs2/aops.c index a067a6cffb01..8e1709a679b7 100644 --- a/fs/ocfs2/aops.c +++ b/fs/ocfs2/aops.c | |||
| @@ -227,7 +227,7 @@ int ocfs2_read_inline_data(struct inode *inode, struct page *page, | |||
| 227 | size = i_size_read(inode); | 227 | size = i_size_read(inode); |
| 228 | 228 | ||
| 229 | if (size > PAGE_CACHE_SIZE || | 229 | if (size > PAGE_CACHE_SIZE || |
| 230 | size > ocfs2_max_inline_data(inode->i_sb)) { | 230 | size > ocfs2_max_inline_data_with_xattr(inode->i_sb, di)) { |
| 231 | ocfs2_error(inode->i_sb, | 231 | ocfs2_error(inode->i_sb, |
| 232 | "Inode %llu has with inline data has bad size: %Lu", | 232 | "Inode %llu has with inline data has bad size: %Lu", |
| 233 | (unsigned long long)OCFS2_I(inode)->ip_blkno, | 233 | (unsigned long long)OCFS2_I(inode)->ip_blkno, |
| @@ -1555,6 +1555,7 @@ static int ocfs2_try_to_write_inline_data(struct address_space *mapping, | |||
| 1555 | int ret, written = 0; | 1555 | int ret, written = 0; |
| 1556 | loff_t end = pos + len; | 1556 | loff_t end = pos + len; |
| 1557 | struct ocfs2_inode_info *oi = OCFS2_I(inode); | 1557 | struct ocfs2_inode_info *oi = OCFS2_I(inode); |
| 1558 | struct ocfs2_dinode *di = NULL; | ||
| 1558 | 1559 | ||
| 1559 | mlog(0, "Inode %llu, write of %u bytes at off %llu. features: 0x%x\n", | 1560 | mlog(0, "Inode %llu, write of %u bytes at off %llu. features: 0x%x\n", |
| 1560 | (unsigned long long)oi->ip_blkno, len, (unsigned long long)pos, | 1561 | (unsigned long long)oi->ip_blkno, len, (unsigned long long)pos, |
| @@ -1587,7 +1588,9 @@ static int ocfs2_try_to_write_inline_data(struct address_space *mapping, | |||
| 1587 | /* | 1588 | /* |
| 1588 | * Check whether the write can fit. | 1589 | * Check whether the write can fit. |
| 1589 | */ | 1590 | */ |
| 1590 | if (mmap_page || end > ocfs2_max_inline_data(inode->i_sb)) | 1591 | di = (struct ocfs2_dinode *)wc->w_di_bh->b_data; |
| 1592 | if (mmap_page || | ||
| 1593 | end > ocfs2_max_inline_data_with_xattr(inode->i_sb, di)) | ||
| 1591 | return 0; | 1594 | return 0; |
| 1592 | 1595 | ||
| 1593 | do_inline_write: | 1596 | do_inline_write: |
diff --git a/fs/ocfs2/namei.c b/fs/ocfs2/namei.c index 084aba86c3b2..4b11762f249e 100644 --- a/fs/ocfs2/namei.c +++ b/fs/ocfs2/namei.c | |||
| @@ -532,7 +532,8 @@ static int ocfs2_mknod_locked(struct ocfs2_super *osb, | |||
| 532 | 532 | ||
| 533 | fe->i_dyn_features = cpu_to_le16(feat | OCFS2_INLINE_DATA_FL); | 533 | fe->i_dyn_features = cpu_to_le16(feat | OCFS2_INLINE_DATA_FL); |
| 534 | 534 | ||
| 535 | fe->id2.i_data.id_count = cpu_to_le16(ocfs2_max_inline_data(osb->sb)); | 535 | fe->id2.i_data.id_count = cpu_to_le16( |
| 536 | ocfs2_max_inline_data_with_xattr(osb->sb, fe)); | ||
| 536 | } else { | 537 | } else { |
| 537 | fel = &fe->id2.i_list; | 538 | fel = &fe->id2.i_list; |
| 538 | fel->l_tree_depth = 0; | 539 | fel->l_tree_depth = 0; |
diff --git a/fs/ocfs2/ocfs2_fs.h b/fs/ocfs2/ocfs2_fs.h index c7ae45aaa36c..2332ef740f4f 100644 --- a/fs/ocfs2/ocfs2_fs.h +++ b/fs/ocfs2/ocfs2_fs.h | |||
| @@ -1070,12 +1070,6 @@ static inline int ocfs2_fast_symlink_chars(struct super_block *sb) | |||
| 1070 | offsetof(struct ocfs2_dinode, id2.i_symlink); | 1070 | offsetof(struct ocfs2_dinode, id2.i_symlink); |
| 1071 | } | 1071 | } |
| 1072 | 1072 | ||
| 1073 | static inline int ocfs2_max_inline_data(struct super_block *sb) | ||
| 1074 | { | ||
| 1075 | return sb->s_blocksize - | ||
| 1076 | offsetof(struct ocfs2_dinode, id2.i_data.id_data); | ||
| 1077 | } | ||
| 1078 | |||
| 1079 | static inline int ocfs2_max_inline_data_with_xattr(struct super_block *sb, | 1073 | static inline int ocfs2_max_inline_data_with_xattr(struct super_block *sb, |
| 1080 | struct ocfs2_dinode *di) | 1074 | struct ocfs2_dinode *di) |
| 1081 | { | 1075 | { |
diff --git a/fs/ocfs2/xattr.c b/fs/ocfs2/xattr.c index 4ddd788add67..2563df89fc2a 100644 --- a/fs/ocfs2/xattr.c +++ b/fs/ocfs2/xattr.c | |||
| @@ -547,8 +547,12 @@ int ocfs2_calc_xattr_init(struct inode *dir, | |||
| 547 | * when blocksize = 512, may reserve one more cluser for | 547 | * when blocksize = 512, may reserve one more cluser for |
| 548 | * xattr bucket, otherwise reserve one metadata block | 548 | * xattr bucket, otherwise reserve one metadata block |
| 549 | * for them is ok. | 549 | * for them is ok. |
| 550 | * If this is a new directory with inline data, | ||
| 551 | * we choose to reserve the entire inline area for | ||
| 552 | * directory contents and force an external xattr block. | ||
| 550 | */ | 553 | */ |
| 551 | if (dir->i_sb->s_blocksize == OCFS2_MIN_BLOCKSIZE || | 554 | if (dir->i_sb->s_blocksize == OCFS2_MIN_BLOCKSIZE || |
| 555 | (S_ISDIR(mode) && ocfs2_supports_inline_data(osb)) || | ||
| 552 | (s_size + a_size) > OCFS2_XATTR_FREE_IN_IBODY) { | 556 | (s_size + a_size) > OCFS2_XATTR_FREE_IN_IBODY) { |
| 553 | ret = ocfs2_reserve_new_metadata_blocks(osb, 1, xattr_ac); | 557 | ret = ocfs2_reserve_new_metadata_blocks(osb, 1, xattr_ac); |
| 554 | if (ret) { | 558 | if (ret) { |
| @@ -4791,19 +4795,33 @@ static int ocfs2_xattr_bucket_set_value_outside(struct inode *inode, | |||
| 4791 | char *val, | 4795 | char *val, |
| 4792 | int value_len) | 4796 | int value_len) |
| 4793 | { | 4797 | { |
| 4794 | int offset; | 4798 | int ret, offset, block_off; |
| 4795 | struct ocfs2_xattr_value_root *xv; | 4799 | struct ocfs2_xattr_value_root *xv; |
| 4796 | struct ocfs2_xattr_entry *xe = xs->here; | 4800 | struct ocfs2_xattr_entry *xe = xs->here; |
| 4801 | struct ocfs2_xattr_header *xh = bucket_xh(xs->bucket); | ||
| 4802 | void *base; | ||
| 4797 | 4803 | ||
| 4798 | BUG_ON(!xs->base || !xe || ocfs2_xattr_is_local(xe)); | 4804 | BUG_ON(!xs->base || !xe || ocfs2_xattr_is_local(xe)); |
| 4799 | 4805 | ||
| 4800 | offset = le16_to_cpu(xe->xe_name_offset) + | 4806 | ret = ocfs2_xattr_bucket_get_name_value(inode, xh, |
| 4801 | OCFS2_XATTR_SIZE(xe->xe_name_len); | 4807 | xe - xh->xh_entries, |
| 4808 | &block_off, | ||
| 4809 | &offset); | ||
| 4810 | if (ret) { | ||
| 4811 | mlog_errno(ret); | ||
| 4812 | goto out; | ||
| 4813 | } | ||
| 4802 | 4814 | ||
| 4803 | xv = (struct ocfs2_xattr_value_root *)(xs->base + offset); | 4815 | base = bucket_block(xs->bucket, block_off); |
| 4816 | xv = (struct ocfs2_xattr_value_root *)(base + offset + | ||
| 4817 | OCFS2_XATTR_SIZE(xe->xe_name_len)); | ||
| 4804 | 4818 | ||
| 4805 | return __ocfs2_xattr_set_value_outside(inode, handle, | 4819 | ret = __ocfs2_xattr_set_value_outside(inode, handle, |
| 4806 | xv, val, value_len); | 4820 | xv, val, value_len); |
| 4821 | if (ret) | ||
| 4822 | mlog_errno(ret); | ||
| 4823 | out: | ||
| 4824 | return ret; | ||
| 4807 | } | 4825 | } |
| 4808 | 4826 | ||
| 4809 | static int ocfs2_rm_xattr_cluster(struct inode *inode, | 4827 | static int ocfs2_rm_xattr_cluster(struct inode *inode, |
| @@ -699,12 +699,12 @@ pipe_rdwr_fasync(int fd, struct file *filp, int on) | |||
| 699 | int retval; | 699 | int retval; |
| 700 | 700 | ||
| 701 | mutex_lock(&inode->i_mutex); | 701 | mutex_lock(&inode->i_mutex); |
| 702 | |||
| 703 | retval = fasync_helper(fd, filp, on, &pipe->fasync_readers); | 702 | retval = fasync_helper(fd, filp, on, &pipe->fasync_readers); |
| 704 | 703 | if (retval >= 0) { | |
| 705 | if (retval >= 0) | ||
| 706 | retval = fasync_helper(fd, filp, on, &pipe->fasync_writers); | 704 | retval = fasync_helper(fd, filp, on, &pipe->fasync_writers); |
| 707 | 705 | if (retval < 0) /* this can happen only if on == T */ | |
| 706 | fasync_helper(-1, filp, 0, &pipe->fasync_readers); | ||
| 707 | } | ||
| 708 | mutex_unlock(&inode->i_mutex); | 708 | mutex_unlock(&inode->i_mutex); |
| 709 | 709 | ||
| 710 | if (retval < 0) | 710 | if (retval < 0) |
diff --git a/fs/proc/base.c b/fs/proc/base.c index 0c9de19a1633..beaa0ce3b82e 100644 --- a/fs/proc/base.c +++ b/fs/proc/base.c | |||
| @@ -3066,7 +3066,6 @@ static int proc_task_readdir(struct file * filp, void * dirent, filldir_t filldi | |||
| 3066 | int retval = -ENOENT; | 3066 | int retval = -ENOENT; |
| 3067 | ino_t ino; | 3067 | ino_t ino; |
| 3068 | int tid; | 3068 | int tid; |
| 3069 | unsigned long pos = filp->f_pos; /* avoiding "long long" filp->f_pos */ | ||
| 3070 | struct pid_namespace *ns; | 3069 | struct pid_namespace *ns; |
| 3071 | 3070 | ||
| 3072 | task = get_proc_task(inode); | 3071 | task = get_proc_task(inode); |
| @@ -3083,18 +3082,18 @@ static int proc_task_readdir(struct file * filp, void * dirent, filldir_t filldi | |||
| 3083 | goto out_no_task; | 3082 | goto out_no_task; |
| 3084 | retval = 0; | 3083 | retval = 0; |
| 3085 | 3084 | ||
| 3086 | switch (pos) { | 3085 | switch ((unsigned long)filp->f_pos) { |
| 3087 | case 0: | 3086 | case 0: |
| 3088 | ino = inode->i_ino; | 3087 | ino = inode->i_ino; |
| 3089 | if (filldir(dirent, ".", 1, pos, ino, DT_DIR) < 0) | 3088 | if (filldir(dirent, ".", 1, filp->f_pos, ino, DT_DIR) < 0) |
| 3090 | goto out; | 3089 | goto out; |
| 3091 | pos++; | 3090 | filp->f_pos++; |
| 3092 | /* fall through */ | 3091 | /* fall through */ |
| 3093 | case 1: | 3092 | case 1: |
| 3094 | ino = parent_ino(dentry); | 3093 | ino = parent_ino(dentry); |
| 3095 | if (filldir(dirent, "..", 2, pos, ino, DT_DIR) < 0) | 3094 | if (filldir(dirent, "..", 2, filp->f_pos, ino, DT_DIR) < 0) |
| 3096 | goto out; | 3095 | goto out; |
| 3097 | pos++; | 3096 | filp->f_pos++; |
| 3098 | /* fall through */ | 3097 | /* fall through */ |
| 3099 | } | 3098 | } |
| 3100 | 3099 | ||
| @@ -3104,9 +3103,9 @@ static int proc_task_readdir(struct file * filp, void * dirent, filldir_t filldi | |||
| 3104 | ns = filp->f_dentry->d_sb->s_fs_info; | 3103 | ns = filp->f_dentry->d_sb->s_fs_info; |
| 3105 | tid = (int)filp->f_version; | 3104 | tid = (int)filp->f_version; |
| 3106 | filp->f_version = 0; | 3105 | filp->f_version = 0; |
| 3107 | for (task = first_tid(leader, tid, pos - 2, ns); | 3106 | for (task = first_tid(leader, tid, filp->f_pos - 2, ns); |
| 3108 | task; | 3107 | task; |
| 3109 | task = next_tid(task), pos++) { | 3108 | task = next_tid(task), filp->f_pos++) { |
| 3110 | tid = task_pid_nr_ns(task, ns); | 3109 | tid = task_pid_nr_ns(task, ns); |
| 3111 | if (proc_task_fill_cache(filp, dirent, filldir, task, tid) < 0) { | 3110 | if (proc_task_fill_cache(filp, dirent, filldir, task, tid) < 0) { |
| 3112 | /* returning this tgid failed, save it as the first | 3111 | /* returning this tgid failed, save it as the first |
| @@ -3117,7 +3116,6 @@ static int proc_task_readdir(struct file * filp, void * dirent, filldir_t filldi | |||
| 3117 | } | 3116 | } |
| 3118 | } | 3117 | } |
| 3119 | out: | 3118 | out: |
| 3120 | filp->f_pos = pos; | ||
| 3121 | put_task_struct(leader); | 3119 | put_task_struct(leader); |
| 3122 | out_no_task: | 3120 | out_no_task: |
| 3123 | return retval; | 3121 | return retval; |
diff --git a/fs/proc/page.c b/fs/proc/page.c index 2d1345112a42..e9983837d08d 100644 --- a/fs/proc/page.c +++ b/fs/proc/page.c | |||
| @@ -80,7 +80,7 @@ static const struct file_operations proc_kpagecount_operations = { | |||
| 80 | #define KPF_RECLAIM 9 | 80 | #define KPF_RECLAIM 9 |
| 81 | #define KPF_BUDDY 10 | 81 | #define KPF_BUDDY 10 |
| 82 | 82 | ||
| 83 | #define kpf_copy_bit(flags, srcpos, dstpos) (((flags >> srcpos) & 1) << dstpos) | 83 | #define kpf_copy_bit(flags, dstpos, srcpos) (((flags >> srcpos) & 1) << dstpos) |
| 84 | 84 | ||
| 85 | static ssize_t kpageflags_read(struct file *file, char __user *buf, | 85 | static ssize_t kpageflags_read(struct file *file, char __user *buf, |
| 86 | size_t count, loff_t *ppos) | 86 | size_t count, loff_t *ppos) |
diff --git a/fs/ramfs/file-nommu.c b/fs/ramfs/file-nommu.c index b9b567a28376..5d7c7ececa64 100644 --- a/fs/ramfs/file-nommu.c +++ b/fs/ramfs/file-nommu.c | |||
| @@ -114,6 +114,9 @@ int ramfs_nommu_expand_for_mapping(struct inode *inode, size_t newsize) | |||
| 114 | if (!pagevec_add(&lru_pvec, page)) | 114 | if (!pagevec_add(&lru_pvec, page)) |
| 115 | __pagevec_lru_add_file(&lru_pvec); | 115 | __pagevec_lru_add_file(&lru_pvec); |
| 116 | 116 | ||
| 117 | /* prevent the page from being discarded on memory pressure */ | ||
| 118 | SetPageDirty(page); | ||
| 119 | |||
| 117 | unlock_page(page); | 120 | unlock_page(page); |
| 118 | } | 121 | } |
| 119 | 122 | ||
| @@ -126,6 +129,7 @@ int ramfs_nommu_expand_for_mapping(struct inode *inode, size_t newsize) | |||
| 126 | return -EFBIG; | 129 | return -EFBIG; |
| 127 | 130 | ||
| 128 | add_error: | 131 | add_error: |
| 132 | pagevec_lru_add_file(&lru_pvec); | ||
| 129 | page_cache_release(pages + loop); | 133 | page_cache_release(pages + loop); |
| 130 | for (loop++; loop < npages; loop++) | 134 | for (loop++; loop < npages; loop++) |
| 131 | __free_page(pages + loop); | 135 | __free_page(pages + loop); |
diff --git a/fs/squashfs/block.c b/fs/squashfs/block.c index c837dfc2b3c6..2a7960310349 100644 --- a/fs/squashfs/block.c +++ b/fs/squashfs/block.c | |||
| @@ -80,7 +80,7 @@ static struct buffer_head *get_block_length(struct super_block *sb, | |||
| 80 | * generated a larger block - this does occasionally happen with zlib). | 80 | * generated a larger block - this does occasionally happen with zlib). |
| 81 | */ | 81 | */ |
| 82 | int squashfs_read_data(struct super_block *sb, void **buffer, u64 index, | 82 | int squashfs_read_data(struct super_block *sb, void **buffer, u64 index, |
| 83 | int length, u64 *next_index, int srclength) | 83 | int length, u64 *next_index, int srclength, int pages) |
| 84 | { | 84 | { |
| 85 | struct squashfs_sb_info *msblk = sb->s_fs_info; | 85 | struct squashfs_sb_info *msblk = sb->s_fs_info; |
| 86 | struct buffer_head **bh; | 86 | struct buffer_head **bh; |
| @@ -184,7 +184,7 @@ int squashfs_read_data(struct super_block *sb, void **buffer, u64 index, | |||
| 184 | offset = 0; | 184 | offset = 0; |
| 185 | } | 185 | } |
| 186 | 186 | ||
| 187 | if (msblk->stream.avail_out == 0) { | 187 | if (msblk->stream.avail_out == 0 && page < pages) { |
| 188 | msblk->stream.next_out = buffer[page++]; | 188 | msblk->stream.next_out = buffer[page++]; |
| 189 | msblk->stream.avail_out = PAGE_CACHE_SIZE; | 189 | msblk->stream.avail_out = PAGE_CACHE_SIZE; |
| 190 | } | 190 | } |
| @@ -201,25 +201,20 @@ int squashfs_read_data(struct super_block *sb, void **buffer, u64 index, | |||
| 201 | zlib_init = 1; | 201 | zlib_init = 1; |
| 202 | } | 202 | } |
| 203 | 203 | ||
| 204 | zlib_err = zlib_inflate(&msblk->stream, Z_NO_FLUSH); | 204 | zlib_err = zlib_inflate(&msblk->stream, Z_SYNC_FLUSH); |
| 205 | 205 | ||
| 206 | if (msblk->stream.avail_in == 0 && k < b) | 206 | if (msblk->stream.avail_in == 0 && k < b) |
| 207 | put_bh(bh[k++]); | 207 | put_bh(bh[k++]); |
| 208 | } while (zlib_err == Z_OK); | 208 | } while (zlib_err == Z_OK); |
| 209 | 209 | ||
| 210 | if (zlib_err != Z_STREAM_END) { | 210 | if (zlib_err != Z_STREAM_END) { |
| 211 | ERROR("zlib_inflate returned unexpected result" | 211 | ERROR("zlib_inflate error, data probably corrupt\n"); |
| 212 | " 0x%x, srclength %d, avail_in %d," | ||
| 213 | " avail_out %d\n", zlib_err, srclength, | ||
| 214 | msblk->stream.avail_in, | ||
| 215 | msblk->stream.avail_out); | ||
| 216 | goto release_mutex; | 212 | goto release_mutex; |
| 217 | } | 213 | } |
| 218 | 214 | ||
| 219 | zlib_err = zlib_inflateEnd(&msblk->stream); | 215 | zlib_err = zlib_inflateEnd(&msblk->stream); |
| 220 | if (zlib_err != Z_OK) { | 216 | if (zlib_err != Z_OK) { |
| 221 | ERROR("zlib_inflateEnd returned unexpected result 0x%x," | 217 | ERROR("zlib_inflate error, data probably corrupt\n"); |
| 222 | " srclength %d\n", zlib_err, srclength); | ||
| 223 | goto release_mutex; | 218 | goto release_mutex; |
| 224 | } | 219 | } |
| 225 | length = msblk->stream.total_out; | 220 | length = msblk->stream.total_out; |
| @@ -268,7 +263,8 @@ block_release: | |||
| 268 | put_bh(bh[k]); | 263 | put_bh(bh[k]); |
| 269 | 264 | ||
| 270 | read_failure: | 265 | read_failure: |
| 271 | ERROR("sb_bread failed reading block 0x%llx\n", cur_index); | 266 | ERROR("squashfs_read_data failed to read block 0x%llx\n", |
| 267 | (unsigned long long) index); | ||
| 272 | kfree(bh); | 268 | kfree(bh); |
| 273 | return -EIO; | 269 | return -EIO; |
| 274 | } | 270 | } |
diff --git a/fs/squashfs/cache.c b/fs/squashfs/cache.c index f29eda16d25e..1c4739e33af6 100644 --- a/fs/squashfs/cache.c +++ b/fs/squashfs/cache.c | |||
| @@ -119,7 +119,7 @@ struct squashfs_cache_entry *squashfs_cache_get(struct super_block *sb, | |||
| 119 | 119 | ||
| 120 | entry->length = squashfs_read_data(sb, entry->data, | 120 | entry->length = squashfs_read_data(sb, entry->data, |
| 121 | block, length, &entry->next_index, | 121 | block, length, &entry->next_index, |
| 122 | cache->block_size); | 122 | cache->block_size, cache->pages); |
| 123 | 123 | ||
| 124 | spin_lock(&cache->lock); | 124 | spin_lock(&cache->lock); |
| 125 | 125 | ||
| @@ -406,7 +406,7 @@ int squashfs_read_table(struct super_block *sb, void *buffer, u64 block, | |||
| 406 | for (i = 0; i < pages; i++, buffer += PAGE_CACHE_SIZE) | 406 | for (i = 0; i < pages; i++, buffer += PAGE_CACHE_SIZE) |
| 407 | data[i] = buffer; | 407 | data[i] = buffer; |
| 408 | res = squashfs_read_data(sb, data, block, length | | 408 | res = squashfs_read_data(sb, data, block, length | |
| 409 | SQUASHFS_COMPRESSED_BIT_BLOCK, NULL, length); | 409 | SQUASHFS_COMPRESSED_BIT_BLOCK, NULL, length, pages); |
| 410 | kfree(data); | 410 | kfree(data); |
| 411 | return res; | 411 | return res; |
| 412 | } | 412 | } |
diff --git a/fs/squashfs/inode.c b/fs/squashfs/inode.c index 7a63398bb855..9101dbde39ec 100644 --- a/fs/squashfs/inode.c +++ b/fs/squashfs/inode.c | |||
| @@ -133,7 +133,8 @@ int squashfs_read_inode(struct inode *inode, long long ino) | |||
| 133 | type = le16_to_cpu(sqshb_ino->inode_type); | 133 | type = le16_to_cpu(sqshb_ino->inode_type); |
| 134 | switch (type) { | 134 | switch (type) { |
| 135 | case SQUASHFS_REG_TYPE: { | 135 | case SQUASHFS_REG_TYPE: { |
| 136 | unsigned int frag_offset, frag_size, frag; | 136 | unsigned int frag_offset, frag; |
| 137 | int frag_size; | ||
| 137 | u64 frag_blk; | 138 | u64 frag_blk; |
| 138 | struct squashfs_reg_inode *sqsh_ino = &squashfs_ino.reg; | 139 | struct squashfs_reg_inode *sqsh_ino = &squashfs_ino.reg; |
| 139 | 140 | ||
| @@ -175,7 +176,8 @@ int squashfs_read_inode(struct inode *inode, long long ino) | |||
| 175 | break; | 176 | break; |
| 176 | } | 177 | } |
| 177 | case SQUASHFS_LREG_TYPE: { | 178 | case SQUASHFS_LREG_TYPE: { |
| 178 | unsigned int frag_offset, frag_size, frag; | 179 | unsigned int frag_offset, frag; |
| 180 | int frag_size; | ||
| 179 | u64 frag_blk; | 181 | u64 frag_blk; |
| 180 | struct squashfs_lreg_inode *sqsh_ino = &squashfs_ino.lreg; | 182 | struct squashfs_lreg_inode *sqsh_ino = &squashfs_ino.lreg; |
| 181 | 183 | ||
diff --git a/fs/squashfs/squashfs.h b/fs/squashfs/squashfs.h index 6b2515d027d5..0e9feb6adf7e 100644 --- a/fs/squashfs/squashfs.h +++ b/fs/squashfs/squashfs.h | |||
| @@ -34,7 +34,7 @@ static inline struct squashfs_inode_info *squashfs_i(struct inode *inode) | |||
| 34 | 34 | ||
| 35 | /* block.c */ | 35 | /* block.c */ |
| 36 | extern int squashfs_read_data(struct super_block *, void **, u64, int, u64 *, | 36 | extern int squashfs_read_data(struct super_block *, void **, u64, int, u64 *, |
| 37 | int); | 37 | int, int); |
| 38 | 38 | ||
| 39 | /* cache.c */ | 39 | /* cache.c */ |
| 40 | extern struct squashfs_cache *squashfs_cache_init(char *, int, int); | 40 | extern struct squashfs_cache *squashfs_cache_init(char *, int, int); |
diff --git a/fs/squashfs/super.c b/fs/squashfs/super.c index 071df5b5b491..681ec0d83799 100644 --- a/fs/squashfs/super.c +++ b/fs/squashfs/super.c | |||
| @@ -389,7 +389,7 @@ static int __init init_squashfs_fs(void) | |||
| 389 | return err; | 389 | return err; |
| 390 | } | 390 | } |
| 391 | 391 | ||
| 392 | printk(KERN_INFO "squashfs: version 4.0 (2009/01/03) " | 392 | printk(KERN_INFO "squashfs: version 4.0 (2009/01/31) " |
| 393 | "Phillip Lougher\n"); | 393 | "Phillip Lougher\n"); |
| 394 | 394 | ||
| 395 | return 0; | 395 | return 0; |
diff --git a/fs/super.c b/fs/super.c index 8349ed6b1412..6ce501447ada 100644 --- a/fs/super.c +++ b/fs/super.c | |||
| @@ -371,8 +371,10 @@ retry: | |||
| 371 | continue; | 371 | continue; |
| 372 | if (!grab_super(old)) | 372 | if (!grab_super(old)) |
| 373 | goto retry; | 373 | goto retry; |
| 374 | if (s) | 374 | if (s) { |
| 375 | up_write(&s->s_umount); | ||
| 375 | destroy_super(s); | 376 | destroy_super(s); |
| 377 | } | ||
| 376 | return old; | 378 | return old; |
| 377 | } | 379 | } |
| 378 | } | 380 | } |
| @@ -387,6 +389,7 @@ retry: | |||
| 387 | err = set(s, data); | 389 | err = set(s, data); |
| 388 | if (err) { | 390 | if (err) { |
| 389 | spin_unlock(&sb_lock); | 391 | spin_unlock(&sb_lock); |
| 392 | up_write(&s->s_umount); | ||
| 390 | destroy_super(s); | 393 | destroy_super(s); |
| 391 | return ERR_PTR(err); | 394 | return ERR_PTR(err); |
| 392 | } | 395 | } |
diff --git a/fs/ufs/super.c b/fs/ufs/super.c index e65212dfb60e..261a1c2f22dd 100644 --- a/fs/ufs/super.c +++ b/fs/ufs/super.c | |||
| @@ -41,7 +41,7 @@ | |||
| 41 | * Stefan Reinauer <stepan@home.culture.mipt.ru> | 41 | * Stefan Reinauer <stepan@home.culture.mipt.ru> |
| 42 | * | 42 | * |
| 43 | * Module usage counts added on 96/04/29 by | 43 | * Module usage counts added on 96/04/29 by |
| 44 | * Gertjan van Wingerde <gertjan@cs.vu.nl> | 44 | * Gertjan van Wingerde <gwingerde@gmail.com> |
| 45 | * | 45 | * |
| 46 | * Clean swab support on 19970406 by | 46 | * Clean swab support on 19970406 by |
| 47 | * Francois-Rene Rideau <fare@tunes.org> | 47 | * Francois-Rene Rideau <fare@tunes.org> |
diff --git a/fs/xfs/linux-2.6/xfs_buf.c b/fs/xfs/linux-2.6/xfs_buf.c index cb329edc925b..aa1016bb9134 100644 --- a/fs/xfs/linux-2.6/xfs_buf.c +++ b/fs/xfs/linux-2.6/xfs_buf.c | |||
| @@ -34,6 +34,12 @@ | |||
| 34 | #include <linux/backing-dev.h> | 34 | #include <linux/backing-dev.h> |
| 35 | #include <linux/freezer.h> | 35 | #include <linux/freezer.h> |
| 36 | 36 | ||
| 37 | #include "xfs_sb.h" | ||
| 38 | #include "xfs_inum.h" | ||
| 39 | #include "xfs_ag.h" | ||
| 40 | #include "xfs_dmapi.h" | ||
| 41 | #include "xfs_mount.h" | ||
| 42 | |||
| 37 | static kmem_zone_t *xfs_buf_zone; | 43 | static kmem_zone_t *xfs_buf_zone; |
| 38 | STATIC int xfsbufd(void *); | 44 | STATIC int xfsbufd(void *); |
| 39 | STATIC int xfsbufd_wakeup(int, gfp_t); | 45 | STATIC int xfsbufd_wakeup(int, gfp_t); |
| @@ -1435,10 +1441,12 @@ xfs_unregister_buftarg( | |||
| 1435 | 1441 | ||
| 1436 | void | 1442 | void |
| 1437 | xfs_free_buftarg( | 1443 | xfs_free_buftarg( |
| 1438 | xfs_buftarg_t *btp) | 1444 | struct xfs_mount *mp, |
| 1445 | struct xfs_buftarg *btp) | ||
| 1439 | { | 1446 | { |
| 1440 | xfs_flush_buftarg(btp, 1); | 1447 | xfs_flush_buftarg(btp, 1); |
| 1441 | xfs_blkdev_issue_flush(btp); | 1448 | if (mp->m_flags & XFS_MOUNT_BARRIER) |
| 1449 | xfs_blkdev_issue_flush(btp); | ||
| 1442 | xfs_free_bufhash(btp); | 1450 | xfs_free_bufhash(btp); |
| 1443 | iput(btp->bt_mapping->host); | 1451 | iput(btp->bt_mapping->host); |
| 1444 | 1452 | ||
diff --git a/fs/xfs/linux-2.6/xfs_buf.h b/fs/xfs/linux-2.6/xfs_buf.h index 288ae7c4c800..9b4d666ad31f 100644 --- a/fs/xfs/linux-2.6/xfs_buf.h +++ b/fs/xfs/linux-2.6/xfs_buf.h | |||
| @@ -413,7 +413,7 @@ static inline int XFS_bwrite(xfs_buf_t *bp) | |||
| 413 | * Handling of buftargs. | 413 | * Handling of buftargs. |
| 414 | */ | 414 | */ |
| 415 | extern xfs_buftarg_t *xfs_alloc_buftarg(struct block_device *, int); | 415 | extern xfs_buftarg_t *xfs_alloc_buftarg(struct block_device *, int); |
| 416 | extern void xfs_free_buftarg(xfs_buftarg_t *); | 416 | extern void xfs_free_buftarg(struct xfs_mount *, struct xfs_buftarg *); |
| 417 | extern void xfs_wait_buftarg(xfs_buftarg_t *); | 417 | extern void xfs_wait_buftarg(xfs_buftarg_t *); |
| 418 | extern int xfs_setsize_buftarg(xfs_buftarg_t *, unsigned int, unsigned int); | 418 | extern int xfs_setsize_buftarg(xfs_buftarg_t *, unsigned int, unsigned int); |
| 419 | extern int xfs_flush_buftarg(xfs_buftarg_t *, int); | 419 | extern int xfs_flush_buftarg(xfs_buftarg_t *, int); |
diff --git a/fs/xfs/linux-2.6/xfs_super.c b/fs/xfs/linux-2.6/xfs_super.c index c71e226da7f5..32ae5028e96b 100644 --- a/fs/xfs/linux-2.6/xfs_super.c +++ b/fs/xfs/linux-2.6/xfs_super.c | |||
| @@ -734,15 +734,15 @@ xfs_close_devices( | |||
| 734 | { | 734 | { |
| 735 | if (mp->m_logdev_targp && mp->m_logdev_targp != mp->m_ddev_targp) { | 735 | if (mp->m_logdev_targp && mp->m_logdev_targp != mp->m_ddev_targp) { |
| 736 | struct block_device *logdev = mp->m_logdev_targp->bt_bdev; | 736 | struct block_device *logdev = mp->m_logdev_targp->bt_bdev; |
| 737 | xfs_free_buftarg(mp->m_logdev_targp); | 737 | xfs_free_buftarg(mp, mp->m_logdev_targp); |
| 738 | xfs_blkdev_put(logdev); | 738 | xfs_blkdev_put(logdev); |
| 739 | } | 739 | } |
| 740 | if (mp->m_rtdev_targp) { | 740 | if (mp->m_rtdev_targp) { |
| 741 | struct block_device *rtdev = mp->m_rtdev_targp->bt_bdev; | 741 | struct block_device *rtdev = mp->m_rtdev_targp->bt_bdev; |
| 742 | xfs_free_buftarg(mp->m_rtdev_targp); | 742 | xfs_free_buftarg(mp, mp->m_rtdev_targp); |
| 743 | xfs_blkdev_put(rtdev); | 743 | xfs_blkdev_put(rtdev); |
| 744 | } | 744 | } |
| 745 | xfs_free_buftarg(mp->m_ddev_targp); | 745 | xfs_free_buftarg(mp, mp->m_ddev_targp); |
| 746 | } | 746 | } |
| 747 | 747 | ||
| 748 | /* | 748 | /* |
| @@ -811,9 +811,9 @@ xfs_open_devices( | |||
| 811 | 811 | ||
| 812 | out_free_rtdev_targ: | 812 | out_free_rtdev_targ: |
| 813 | if (mp->m_rtdev_targp) | 813 | if (mp->m_rtdev_targp) |
| 814 | xfs_free_buftarg(mp->m_rtdev_targp); | 814 | xfs_free_buftarg(mp, mp->m_rtdev_targp); |
| 815 | out_free_ddev_targ: | 815 | out_free_ddev_targ: |
| 816 | xfs_free_buftarg(mp->m_ddev_targp); | 816 | xfs_free_buftarg(mp, mp->m_ddev_targp); |
| 817 | out_close_rtdev: | 817 | out_close_rtdev: |
| 818 | if (rtdev) | 818 | if (rtdev) |
| 819 | xfs_blkdev_put(rtdev); | 819 | xfs_blkdev_put(rtdev); |
diff --git a/fs/xfs/xfs_iget.c b/fs/xfs/xfs_iget.c index e2fb6210d4c5..478e587087fe 100644 --- a/fs/xfs/xfs_iget.c +++ b/fs/xfs/xfs_iget.c | |||
| @@ -246,9 +246,6 @@ xfs_iget_cache_miss( | |||
| 246 | goto out_destroy; | 246 | goto out_destroy; |
| 247 | } | 247 | } |
| 248 | 248 | ||
| 249 | if (lock_flags) | ||
| 250 | xfs_ilock(ip, lock_flags); | ||
| 251 | |||
| 252 | /* | 249 | /* |
| 253 | * Preload the radix tree so we can insert safely under the | 250 | * Preload the radix tree so we can insert safely under the |
| 254 | * write spinlock. Note that we cannot sleep inside the preload | 251 | * write spinlock. Note that we cannot sleep inside the preload |
| @@ -256,7 +253,16 @@ xfs_iget_cache_miss( | |||
| 256 | */ | 253 | */ |
| 257 | if (radix_tree_preload(GFP_KERNEL)) { | 254 | if (radix_tree_preload(GFP_KERNEL)) { |
| 258 | error = EAGAIN; | 255 | error = EAGAIN; |
| 259 | goto out_unlock; | 256 | goto out_destroy; |
| 257 | } | ||
| 258 | |||
| 259 | /* | ||
| 260 | * Because the inode hasn't been added to the radix-tree yet it can't | ||
| 261 | * be found by another thread, so we can do the non-sleeping lock here. | ||
| 262 | */ | ||
| 263 | if (lock_flags) { | ||
| 264 | if (!xfs_ilock_nowait(ip, lock_flags)) | ||
| 265 | BUG(); | ||
| 260 | } | 266 | } |
| 261 | 267 | ||
| 262 | mask = ~(((XFS_INODE_CLUSTER_SIZE(mp) >> mp->m_sb.sb_inodelog)) - 1); | 268 | mask = ~(((XFS_INODE_CLUSTER_SIZE(mp) >> mp->m_sb.sb_inodelog)) - 1); |
| @@ -284,7 +290,6 @@ xfs_iget_cache_miss( | |||
| 284 | out_preload_end: | 290 | out_preload_end: |
| 285 | write_unlock(&pag->pag_ici_lock); | 291 | write_unlock(&pag->pag_ici_lock); |
| 286 | radix_tree_preload_end(); | 292 | radix_tree_preload_end(); |
| 287 | out_unlock: | ||
| 288 | if (lock_flags) | 293 | if (lock_flags) |
| 289 | xfs_iunlock(ip, lock_flags); | 294 | xfs_iunlock(ip, lock_flags); |
| 290 | out_destroy: | 295 | out_destroy: |
diff --git a/fs/xfs/xfs_log_recover.c b/fs/xfs/xfs_log_recover.c index b1047de2fffd..61af610d79b3 100644 --- a/fs/xfs/xfs_log_recover.c +++ b/fs/xfs/xfs_log_recover.c | |||
| @@ -1455,10 +1455,19 @@ xlog_recover_add_to_trans( | |||
| 1455 | item = item->ri_prev; | 1455 | item = item->ri_prev; |
| 1456 | 1456 | ||
| 1457 | if (item->ri_total == 0) { /* first region to be added */ | 1457 | if (item->ri_total == 0) { /* first region to be added */ |
| 1458 | item->ri_total = in_f->ilf_size; | 1458 | if (in_f->ilf_size == 0 || |
| 1459 | ASSERT(item->ri_total <= XLOG_MAX_REGIONS_IN_ITEM); | 1459 | in_f->ilf_size > XLOG_MAX_REGIONS_IN_ITEM) { |
| 1460 | item->ri_buf = kmem_zalloc((item->ri_total * | 1460 | xlog_warn( |
| 1461 | sizeof(xfs_log_iovec_t)), KM_SLEEP); | 1461 | "XFS: bad number of regions (%d) in inode log format", |
| 1462 | in_f->ilf_size); | ||
| 1463 | ASSERT(0); | ||
| 1464 | return XFS_ERROR(EIO); | ||
| 1465 | } | ||
| 1466 | |||
| 1467 | item->ri_total = in_f->ilf_size; | ||
| 1468 | item->ri_buf = | ||
| 1469 | kmem_zalloc(item->ri_total * sizeof(xfs_log_iovec_t), | ||
| 1470 | KM_SLEEP); | ||
| 1462 | } | 1471 | } |
| 1463 | ASSERT(item->ri_total > item->ri_cnt); | 1472 | ASSERT(item->ri_total > item->ri_cnt); |
| 1464 | /* Description region is ri_buf[0] */ | 1473 | /* Description region is ri_buf[0] */ |
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h index ff8d27af4786..a11cc9d32591 100644 --- a/include/drm/drm_edid.h +++ b/include/drm/drm_edid.h | |||
| @@ -69,8 +69,8 @@ struct detailed_pixel_timing { | |||
| 69 | u8 hborder; | 69 | u8 hborder; |
| 70 | u8 vborder; | 70 | u8 vborder; |
| 71 | u8 unknown0:1; | 71 | u8 unknown0:1; |
| 72 | u8 vsync_positive:1; | ||
| 73 | u8 hsync_positive:1; | 72 | u8 hsync_positive:1; |
| 73 | u8 vsync_positive:1; | ||
| 74 | u8 separate_sync:2; | 74 | u8 separate_sync:2; |
| 75 | u8 stereo:1; | 75 | u8 stereo:1; |
| 76 | u8 unknown6:1; | 76 | u8 unknown6:1; |
diff --git a/include/linux/ata.h b/include/linux/ata.h index 08a86d5cdf1b..9a061accd8b8 100644 --- a/include/linux/ata.h +++ b/include/linux/ata.h | |||
| @@ -89,6 +89,8 @@ enum { | |||
| 89 | ATA_ID_DLF = 128, | 89 | ATA_ID_DLF = 128, |
| 90 | ATA_ID_CSFO = 129, | 90 | ATA_ID_CSFO = 129, |
| 91 | ATA_ID_CFA_POWER = 160, | 91 | ATA_ID_CFA_POWER = 160, |
| 92 | ATA_ID_CFA_KEY_MGMT = 162, | ||
| 93 | ATA_ID_CFA_MODES = 163, | ||
| 92 | ATA_ID_ROT_SPEED = 217, | 94 | ATA_ID_ROT_SPEED = 217, |
| 93 | ATA_ID_PIO4 = (1 << 1), | 95 | ATA_ID_PIO4 = (1 << 1), |
| 94 | 96 | ||
diff --git a/include/linux/bio.h b/include/linux/bio.h index 1b16108a5417..d8bd43bfdcf5 100644 --- a/include/linux/bio.h +++ b/include/linux/bio.h | |||
| @@ -531,7 +531,7 @@ extern void bio_integrity_endio(struct bio *, int); | |||
| 531 | extern void bio_integrity_advance(struct bio *, unsigned int); | 531 | extern void bio_integrity_advance(struct bio *, unsigned int); |
| 532 | extern void bio_integrity_trim(struct bio *, unsigned int, unsigned int); | 532 | extern void bio_integrity_trim(struct bio *, unsigned int, unsigned int); |
| 533 | extern void bio_integrity_split(struct bio *, struct bio_pair *, int); | 533 | extern void bio_integrity_split(struct bio *, struct bio_pair *, int); |
| 534 | extern int bio_integrity_clone(struct bio *, struct bio *, struct bio_set *); | 534 | extern int bio_integrity_clone(struct bio *, struct bio *, gfp_t, struct bio_set *); |
| 535 | extern int bioset_integrity_create(struct bio_set *, int); | 535 | extern int bioset_integrity_create(struct bio_set *, int); |
| 536 | extern void bioset_integrity_free(struct bio_set *); | 536 | extern void bioset_integrity_free(struct bio_set *); |
| 537 | extern void bio_integrity_init_slab(void); | 537 | extern void bio_integrity_init_slab(void); |
| @@ -542,7 +542,7 @@ extern void bio_integrity_init_slab(void); | |||
| 542 | #define bioset_integrity_create(a, b) (0) | 542 | #define bioset_integrity_create(a, b) (0) |
| 543 | #define bio_integrity_prep(a) (0) | 543 | #define bio_integrity_prep(a) (0) |
| 544 | #define bio_integrity_enabled(a) (0) | 544 | #define bio_integrity_enabled(a) (0) |
| 545 | #define bio_integrity_clone(a, b, c) (0) | 545 | #define bio_integrity_clone(a, b, c,d ) (0) |
| 546 | #define bioset_integrity_free(a) do { } while (0) | 546 | #define bioset_integrity_free(a) do { } while (0) |
| 547 | #define bio_integrity_free(a, b) do { } while (0) | 547 | #define bio_integrity_free(a, b) do { } while (0) |
| 548 | #define bio_integrity_endio(a, b) do { } while (0) | 548 | #define bio_integrity_endio(a, b) do { } while (0) |
diff --git a/include/linux/capability.h b/include/linux/capability.h index 1b9872556131..4864a43b2b45 100644 --- a/include/linux/capability.h +++ b/include/linux/capability.h | |||
| @@ -393,8 +393,10 @@ struct cpu_vfs_cap_data { | |||
| 393 | # define CAP_FULL_SET ((kernel_cap_t){{ ~0, ~0 }}) | 393 | # define CAP_FULL_SET ((kernel_cap_t){{ ~0, ~0 }}) |
| 394 | # define CAP_INIT_EFF_SET ((kernel_cap_t){{ ~CAP_TO_MASK(CAP_SETPCAP), ~0 }}) | 394 | # define CAP_INIT_EFF_SET ((kernel_cap_t){{ ~CAP_TO_MASK(CAP_SETPCAP), ~0 }}) |
| 395 | # define CAP_FS_SET ((kernel_cap_t){{ CAP_FS_MASK_B0, CAP_FS_MASK_B1 } }) | 395 | # define CAP_FS_SET ((kernel_cap_t){{ CAP_FS_MASK_B0, CAP_FS_MASK_B1 } }) |
| 396 | # define CAP_NFSD_SET ((kernel_cap_t){{ CAP_FS_MASK_B0|CAP_TO_MASK(CAP_SYS_RESOURCE), \ | 396 | # define CAP_NFSD_SET ((kernel_cap_t){{ CAP_FS_MASK_B0 \ |
| 397 | CAP_FS_MASK_B1 } }) | 397 | | CAP_TO_MASK(CAP_SYS_RESOURCE) \ |
| 398 | | CAP_TO_MASK(CAP_MKNOD), \ | ||
| 399 | CAP_FS_MASK_B1 } }) | ||
| 398 | 400 | ||
| 399 | #endif /* _KERNEL_CAPABILITY_U32S != 2 */ | 401 | #endif /* _KERNEL_CAPABILITY_U32S != 2 */ |
| 400 | 402 | ||
diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h index 1514d534deeb..a3ed7cb8ca34 100644 --- a/include/linux/compiler-gcc.h +++ b/include/linux/compiler-gcc.h | |||
| @@ -52,7 +52,15 @@ | |||
| 52 | #define __deprecated __attribute__((deprecated)) | 52 | #define __deprecated __attribute__((deprecated)) |
| 53 | #define __packed __attribute__((packed)) | 53 | #define __packed __attribute__((packed)) |
| 54 | #define __weak __attribute__((weak)) | 54 | #define __weak __attribute__((weak)) |
| 55 | #define __naked __attribute__((naked)) | 55 | |
| 56 | /* | ||
| 57 | * it doesn't make sense on ARM (currently the only user of __naked) to trace | ||
| 58 | * naked functions because then mcount is called without stack and frame pointer | ||
| 59 | * being set up and there is no chance to restore the lr register to the value | ||
| 60 | * before mcount was called. | ||
| 61 | */ | ||
| 62 | #define __naked __attribute__((naked)) notrace | ||
| 63 | |||
| 56 | #define __noreturn __attribute__((noreturn)) | 64 | #define __noreturn __attribute__((noreturn)) |
| 57 | 65 | ||
| 58 | /* | 66 | /* |
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 384b38d3e8e2..161042746afc 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h | |||
| @@ -234,7 +234,6 @@ struct cpufreq_driver { | |||
| 234 | int (*suspend) (struct cpufreq_policy *policy, pm_message_t pmsg); | 234 | int (*suspend) (struct cpufreq_policy *policy, pm_message_t pmsg); |
| 235 | int (*resume) (struct cpufreq_policy *policy); | 235 | int (*resume) (struct cpufreq_policy *policy); |
| 236 | struct freq_attr **attr; | 236 | struct freq_attr **attr; |
| 237 | bool hide_interface; | ||
| 238 | }; | 237 | }; |
| 239 | 238 | ||
| 240 | /* flags */ | 239 | /* flags */ |
diff --git a/include/linux/dca.h b/include/linux/dca.h index b00a753eda53..9c20c7e87d0a 100644 --- a/include/linux/dca.h +++ b/include/linux/dca.h | |||
| @@ -1,3 +1,23 @@ | |||
| 1 | /* | ||
| 2 | * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved. | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify it | ||
| 5 | * under the terms of the GNU General Public License as published by the Free | ||
| 6 | * Software Foundation; either version 2 of the License, or (at your option) | ||
| 7 | * any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT | ||
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
| 12 | * more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License along with | ||
| 15 | * this program; if not, write to the Free Software Foundation, Inc., 59 | ||
| 16 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. | ||
| 17 | * | ||
| 18 | * The full GNU General Public License is included in this distribution in the | ||
| 19 | * file called COPYING. | ||
| 20 | */ | ||
| 1 | #ifndef DCA_H | 21 | #ifndef DCA_H |
| 2 | #define DCA_H | 22 | #define DCA_H |
| 3 | /* DCA Provider API */ | 23 | /* DCA Provider API */ |
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index f0413845f20e..1956c8d46d32 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h | |||
| @@ -97,7 +97,6 @@ typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t; | |||
| 97 | 97 | ||
| 98 | /** | 98 | /** |
| 99 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan | 99 | * struct dma_chan_percpu - the per-CPU part of struct dma_chan |
| 100 | * @refcount: local_t used for open-coded "bigref" counting | ||
| 101 | * @memcpy_count: transaction counter | 100 | * @memcpy_count: transaction counter |
| 102 | * @bytes_transferred: byte counter | 101 | * @bytes_transferred: byte counter |
| 103 | */ | 102 | */ |
| @@ -114,9 +113,6 @@ struct dma_chan_percpu { | |||
| 114 | * @cookie: last cookie value returned to client | 113 | * @cookie: last cookie value returned to client |
| 115 | * @chan_id: channel ID for sysfs | 114 | * @chan_id: channel ID for sysfs |
| 116 | * @dev: class device for sysfs | 115 | * @dev: class device for sysfs |
| 117 | * @refcount: kref, used in "bigref" slow-mode | ||
| 118 | * @slow_ref: indicates that the DMA channel is free | ||
| 119 | * @rcu: the DMA channel's RCU head | ||
| 120 | * @device_node: used to add this to the device chan list | 116 | * @device_node: used to add this to the device chan list |
| 121 | * @local: per-cpu pointer to a struct dma_chan_percpu | 117 | * @local: per-cpu pointer to a struct dma_chan_percpu |
| 122 | * @client-count: how many clients are using this channel | 118 | * @client-count: how many clients are using this channel |
| @@ -213,8 +209,6 @@ struct dma_async_tx_descriptor { | |||
| 213 | * @global_node: list_head for global dma_device_list | 209 | * @global_node: list_head for global dma_device_list |
| 214 | * @cap_mask: one or more dma_capability flags | 210 | * @cap_mask: one or more dma_capability flags |
| 215 | * @max_xor: maximum number of xor sources, 0 if no capability | 211 | * @max_xor: maximum number of xor sources, 0 if no capability |
| 216 | * @refcount: reference count | ||
| 217 | * @done: IO completion struct | ||
| 218 | * @dev_id: unique device ID | 212 | * @dev_id: unique device ID |
| 219 | * @dev: struct device reference for dma mapping api | 213 | * @dev: struct device reference for dma mapping api |
| 220 | * @device_alloc_chan_resources: allocate resources and return the | 214 | * @device_alloc_chan_resources: allocate resources and return the |
| @@ -227,6 +221,7 @@ struct dma_async_tx_descriptor { | |||
| 227 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation | 221 | * @device_prep_dma_interrupt: prepares an end of chain interrupt operation |
| 228 | * @device_prep_slave_sg: prepares a slave dma operation | 222 | * @device_prep_slave_sg: prepares a slave dma operation |
| 229 | * @device_terminate_all: terminate all pending operations | 223 | * @device_terminate_all: terminate all pending operations |
| 224 | * @device_is_tx_complete: poll for transaction completion | ||
| 230 | * @device_issue_pending: push pending transactions to hardware | 225 | * @device_issue_pending: push pending transactions to hardware |
| 231 | */ | 226 | */ |
| 232 | struct dma_device { | 227 | struct dma_device { |
diff --git a/include/linux/hdreg.h b/include/linux/hdreg.h index c37e9241fae7..ed21bd3dbd25 100644 --- a/include/linux/hdreg.h +++ b/include/linux/hdreg.h | |||
| @@ -511,7 +511,6 @@ struct hd_driveid { | |||
| 511 | unsigned short words69_70[2]; /* reserved words 69-70 | 511 | unsigned short words69_70[2]; /* reserved words 69-70 |
| 512 | * future command overlap and queuing | 512 | * future command overlap and queuing |
| 513 | */ | 513 | */ |
| 514 | /* HDIO_GET_IDENTITY currently returns only words 0 through 70 */ | ||
| 515 | unsigned short words71_74[4]; /* reserved words 71-74 | 514 | unsigned short words71_74[4]; /* reserved words 71-74 |
| 516 | * for IDENTIFY PACKET DEVICE command | 515 | * for IDENTIFY PACKET DEVICE command |
| 517 | */ | 516 | */ |
diff --git a/include/linux/ide.h b/include/linux/ide.h index fe235b65207e..25087aead657 100644 --- a/include/linux/ide.h +++ b/include/linux/ide.h | |||
| @@ -797,6 +797,7 @@ typedef struct hwif_s { | |||
| 797 | struct scatterlist *sg_table; | 797 | struct scatterlist *sg_table; |
| 798 | int sg_max_nents; /* Maximum number of entries in it */ | 798 | int sg_max_nents; /* Maximum number of entries in it */ |
| 799 | int sg_nents; /* Current number of entries in it */ | 799 | int sg_nents; /* Current number of entries in it */ |
| 800 | int orig_sg_nents; | ||
| 800 | int sg_dma_direction; /* dma transfer direction */ | 801 | int sg_dma_direction; /* dma transfer direction */ |
| 801 | 802 | ||
| 802 | /* data phase of the active command (currently only valid for PIO/DMA) */ | 803 | /* data phase of the active command (currently only valid for PIO/DMA) */ |
| @@ -866,6 +867,7 @@ struct ide_host { | |||
| 866 | unsigned int n_ports; | 867 | unsigned int n_ports; |
| 867 | struct device *dev[2]; | 868 | struct device *dev[2]; |
| 868 | unsigned int (*init_chipset)(struct pci_dev *); | 869 | unsigned int (*init_chipset)(struct pci_dev *); |
| 870 | irq_handler_t irq_handler; | ||
| 869 | unsigned long host_flags; | 871 | unsigned long host_flags; |
| 870 | void *host_priv; | 872 | void *host_priv; |
| 871 | ide_hwif_t *cur_port; /* for hosts requiring serialization */ | 873 | ide_hwif_t *cur_port; /* for hosts requiring serialization */ |
diff --git a/include/linux/libata.h b/include/linux/libata.h index 5d87bc09a1f5..dc18b87ed722 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h | |||
| @@ -275,7 +275,7 @@ enum { | |||
| 275 | * advised to wait only for the following duration before | 275 | * advised to wait only for the following duration before |
| 276 | * doing SRST. | 276 | * doing SRST. |
| 277 | */ | 277 | */ |
| 278 | ATA_TMOUT_PMP_SRST_WAIT = 1000, | 278 | ATA_TMOUT_PMP_SRST_WAIT = 5000, |
| 279 | 279 | ||
| 280 | /* ATA bus states */ | 280 | /* ATA bus states */ |
| 281 | BUS_UNKNOWN = 0, | 281 | BUS_UNKNOWN = 0, |
| @@ -530,6 +530,7 @@ struct ata_queued_cmd { | |||
| 530 | unsigned long flags; /* ATA_QCFLAG_xxx */ | 530 | unsigned long flags; /* ATA_QCFLAG_xxx */ |
| 531 | unsigned int tag; | 531 | unsigned int tag; |
| 532 | unsigned int n_elem; | 532 | unsigned int n_elem; |
| 533 | unsigned int orig_n_elem; | ||
| 533 | 534 | ||
| 534 | int dma_dir; | 535 | int dma_dir; |
| 535 | 536 | ||
| @@ -750,7 +751,8 @@ struct ata_port { | |||
| 750 | acpi_handle acpi_handle; | 751 | acpi_handle acpi_handle; |
| 751 | struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */ | 752 | struct ata_acpi_gtm __acpi_init_gtm; /* use ata_acpi_init_gtm() */ |
| 752 | #endif | 753 | #endif |
| 753 | u8 sector_buf[ATA_SECT_SIZE]; /* owned by EH */ | 754 | /* owned by EH */ |
| 755 | u8 sector_buf[ATA_SECT_SIZE] ____cacheline_aligned; | ||
| 754 | }; | 756 | }; |
| 755 | 757 | ||
| 756 | /* The following initializer overrides a method to NULL whether one of | 758 | /* The following initializer overrides a method to NULL whether one of |
diff --git a/include/linux/lockd/lockd.h b/include/linux/lockd/lockd.h index aa6fe7026de7..51855dfd8adb 100644 --- a/include/linux/lockd/lockd.h +++ b/include/linux/lockd/lockd.h | |||
| @@ -346,6 +346,7 @@ static inline int __nlm_cmp_addr4(const struct sockaddr *sap1, | |||
| 346 | return sin1->sin_addr.s_addr == sin2->sin_addr.s_addr; | 346 | return sin1->sin_addr.s_addr == sin2->sin_addr.s_addr; |
| 347 | } | 347 | } |
| 348 | 348 | ||
| 349 | #if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) | ||
| 349 | static inline int __nlm_cmp_addr6(const struct sockaddr *sap1, | 350 | static inline int __nlm_cmp_addr6(const struct sockaddr *sap1, |
| 350 | const struct sockaddr *sap2) | 351 | const struct sockaddr *sap2) |
| 351 | { | 352 | { |
| @@ -353,6 +354,13 @@ static inline int __nlm_cmp_addr6(const struct sockaddr *sap1, | |||
| 353 | const struct sockaddr_in6 *sin2 = (const struct sockaddr_in6 *)sap2; | 354 | const struct sockaddr_in6 *sin2 = (const struct sockaddr_in6 *)sap2; |
| 354 | return ipv6_addr_equal(&sin1->sin6_addr, &sin2->sin6_addr); | 355 | return ipv6_addr_equal(&sin1->sin6_addr, &sin2->sin6_addr); |
| 355 | } | 356 | } |
| 357 | #else /* !(CONFIG_IPV6 || CONFIG_IPV6_MODULE) */ | ||
| 358 | static inline int __nlm_cmp_addr6(const struct sockaddr *sap1, | ||
| 359 | const struct sockaddr *sap2) | ||
| 360 | { | ||
| 361 | return 0; | ||
| 362 | } | ||
| 363 | #endif /* !(CONFIG_IPV6 || CONFIG_IPV6_MODULE) */ | ||
| 356 | 364 | ||
| 357 | /* | 365 | /* |
| 358 | * Compare two host addresses | 366 | * Compare two host addresses |
diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h index 92915e81443f..d84feb7bdbf0 100644 --- a/include/linux/mm_types.h +++ b/include/linux/mm_types.h | |||
| @@ -276,4 +276,7 @@ struct mm_struct { | |||
| 276 | #endif | 276 | #endif |
| 277 | }; | 277 | }; |
| 278 | 278 | ||
| 279 | /* Future-safe accessor for struct mm_struct's cpu_vm_mask. */ | ||
| 280 | #define mm_cpumask(mm) (&(mm)->cpu_vm_mask) | ||
| 281 | |||
| 279 | #endif /* _LINUX_MM_TYPES_H */ | 282 | #endif /* _LINUX_MM_TYPES_H */ |
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h index ec54785d34f9..659366734f3f 100644 --- a/include/linux/netdevice.h +++ b/include/linux/netdevice.h | |||
| @@ -1079,6 +1079,7 @@ extern void synchronize_net(void); | |||
| 1079 | extern int register_netdevice_notifier(struct notifier_block *nb); | 1079 | extern int register_netdevice_notifier(struct notifier_block *nb); |
| 1080 | extern int unregister_netdevice_notifier(struct notifier_block *nb); | 1080 | extern int unregister_netdevice_notifier(struct notifier_block *nb); |
| 1081 | extern int init_dummy_netdev(struct net_device *dev); | 1081 | extern int init_dummy_netdev(struct net_device *dev); |
| 1082 | extern void netdev_resync_ops(struct net_device *dev); | ||
| 1082 | 1083 | ||
| 1083 | extern int call_netdevice_notifiers(unsigned long val, struct net_device *dev); | 1084 | extern int call_netdevice_notifiers(unsigned long val, struct net_device *dev); |
| 1084 | extern struct net_device *dev_get_by_index(struct net *net, int ifindex); | 1085 | extern struct net_device *dev_get_by_index(struct net *net, int ifindex); |
diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h index a550b528319f..2e5f00066afd 100644 --- a/include/linux/nfs_xdr.h +++ b/include/linux/nfs_xdr.h | |||
| @@ -406,6 +406,8 @@ struct nfs3_setaclargs { | |||
| 406 | int mask; | 406 | int mask; |
| 407 | struct posix_acl * acl_access; | 407 | struct posix_acl * acl_access; |
| 408 | struct posix_acl * acl_default; | 408 | struct posix_acl * acl_default; |
| 409 | size_t len; | ||
| 410 | unsigned int npages; | ||
| 409 | struct page ** pages; | 411 | struct page ** pages; |
| 410 | }; | 412 | }; |
| 411 | 413 | ||
diff --git a/include/linux/nfsacl.h b/include/linux/nfsacl.h index 54487a99beb8..43011b69297c 100644 --- a/include/linux/nfsacl.h +++ b/include/linux/nfsacl.h | |||
| @@ -37,6 +37,9 @@ | |||
| 37 | #define NFSACL_MAXPAGES ((2*(8+12*NFS_ACL_MAX_ENTRIES) + PAGE_SIZE-1) \ | 37 | #define NFSACL_MAXPAGES ((2*(8+12*NFS_ACL_MAX_ENTRIES) + PAGE_SIZE-1) \ |
| 38 | >> PAGE_SHIFT) | 38 | >> PAGE_SHIFT) |
| 39 | 39 | ||
| 40 | #define NFS_ACL_MAX_ENTRIES_INLINE (5) | ||
| 41 | #define NFS_ACL_INLINE_BUFSIZE ((2*(2+3*NFS_ACL_MAX_ENTRIES_INLINE)) << 2) | ||
| 42 | |||
| 40 | static inline unsigned int | 43 | static inline unsigned int |
| 41 | nfsacl_size(struct posix_acl *acl_access, struct posix_acl *acl_default) | 44 | nfsacl_size(struct posix_acl *acl_access, struct posix_acl *acl_default) |
| 42 | { | 45 | { |
diff --git a/include/linux/sched.h b/include/linux/sched.h index 8c216e057c94..011db2f4c94c 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h | |||
| @@ -1419,6 +1419,9 @@ struct task_struct { | |||
| 1419 | #endif | 1419 | #endif |
| 1420 | }; | 1420 | }; |
| 1421 | 1421 | ||
| 1422 | /* Future-safe accessor for struct task_struct's cpus_allowed. */ | ||
| 1423 | #define tsk_cpumask(tsk) (&(tsk)->cpus_allowed) | ||
| 1424 | |||
| 1422 | /* | 1425 | /* |
| 1423 | * Priority of a process goes from 0..MAX_PRIO-1, valid RT | 1426 | * Priority of a process goes from 0..MAX_PRIO-1, valid RT |
| 1424 | * priority is 0..MAX_RT_PRIO-1, and SCHED_NORMAL/SCHED_BATCH | 1427 | * priority is 0..MAX_RT_PRIO-1, and SCHED_NORMAL/SCHED_BATCH |
diff --git a/include/linux/serio.h b/include/linux/serio.h index 1bcb357a01a1..e0417e4d3f15 100644 --- a/include/linux/serio.h +++ b/include/linux/serio.h | |||
| @@ -212,7 +212,7 @@ static inline void serio_unpin_driver(struct serio *serio) | |||
| 212 | #define SERIO_FUJITSU 0x35 | 212 | #define SERIO_FUJITSU 0x35 |
| 213 | #define SERIO_ZHENHUA 0x36 | 213 | #define SERIO_ZHENHUA 0x36 |
| 214 | #define SERIO_INEXIO 0x37 | 214 | #define SERIO_INEXIO 0x37 |
| 215 | #define SERIO_TOUCHIT213 0x37 | 215 | #define SERIO_TOUCHIT213 0x38 |
| 216 | #define SERIO_W8001 0x39 | 216 | #define SERIO_W8001 0x39 |
| 217 | 217 | ||
| 218 | #endif | 218 | #endif |
diff --git a/include/net/net_namespace.h b/include/net/net_namespace.h index 6fc13d905c5f..ded434b032a4 100644 --- a/include/net/net_namespace.h +++ b/include/net/net_namespace.h | |||
| @@ -109,11 +109,6 @@ extern struct list_head net_namespace_list; | |||
| 109 | #ifdef CONFIG_NET_NS | 109 | #ifdef CONFIG_NET_NS |
| 110 | extern void __put_net(struct net *net); | 110 | extern void __put_net(struct net *net); |
| 111 | 111 | ||
| 112 | static inline int net_alive(struct net *net) | ||
| 113 | { | ||
| 114 | return net && atomic_read(&net->count); | ||
| 115 | } | ||
| 116 | |||
| 117 | static inline struct net *get_net(struct net *net) | 112 | static inline struct net *get_net(struct net *net) |
| 118 | { | 113 | { |
| 119 | atomic_inc(&net->count); | 114 | atomic_inc(&net->count); |
| @@ -145,11 +140,6 @@ int net_eq(const struct net *net1, const struct net *net2) | |||
| 145 | } | 140 | } |
| 146 | #else | 141 | #else |
| 147 | 142 | ||
| 148 | static inline int net_alive(struct net *net) | ||
| 149 | { | ||
| 150 | return 1; | ||
| 151 | } | ||
| 152 | |||
| 153 | static inline struct net *get_net(struct net *net) | 143 | static inline struct net *get_net(struct net *net) |
| 154 | { | 144 | { |
| 155 | return net; | 145 | return net; |
| @@ -234,6 +224,23 @@ struct pernet_operations { | |||
| 234 | void (*exit)(struct net *net); | 224 | void (*exit)(struct net *net); |
| 235 | }; | 225 | }; |
| 236 | 226 | ||
| 227 | /* | ||
| 228 | * Use these carefully. If you implement a network device and it | ||
| 229 | * needs per network namespace operations use device pernet operations, | ||
| 230 | * otherwise use pernet subsys operations. | ||
| 231 | * | ||
| 232 | * This is critically important. Most of the network code cleanup | ||
| 233 | * runs with the assumption that dev_remove_pack has been called so no | ||
| 234 | * new packets will arrive during and after the cleanup functions have | ||
| 235 | * been called. dev_remove_pack is not per namespace so instead the | ||
| 236 | * guarantee of no more packets arriving in a network namespace is | ||
| 237 | * provided by ensuring that all network devices and all sockets have | ||
| 238 | * left the network namespace before the cleanup methods are called. | ||
| 239 | * | ||
| 240 | * For the longest time the ipv4 icmp code was registered as a pernet | ||
| 241 | * device which caused kernel oops, and panics during network | ||
| 242 | * namespace cleanup. So please don't get this wrong. | ||
| 243 | */ | ||
| 237 | extern int register_pernet_subsys(struct pernet_operations *); | 244 | extern int register_pernet_subsys(struct pernet_operations *); |
| 238 | extern void unregister_pernet_subsys(struct pernet_operations *); | 245 | extern void unregister_pernet_subsys(struct pernet_operations *); |
| 239 | extern int register_pernet_gen_subsys(int *id, struct pernet_operations *); | 246 | extern int register_pernet_gen_subsys(int *id, struct pernet_operations *); |
diff --git a/include/net/netfilter/nf_conntrack_core.h b/include/net/netfilter/nf_conntrack_core.h index c25068e38516..5a449b44ba33 100644 --- a/include/net/netfilter/nf_conntrack_core.h +++ b/include/net/netfilter/nf_conntrack_core.h | |||
| @@ -62,7 +62,8 @@ static inline int nf_conntrack_confirm(struct sk_buff *skb) | |||
| 62 | if (ct && ct != &nf_conntrack_untracked) { | 62 | if (ct && ct != &nf_conntrack_untracked) { |
| 63 | if (!nf_ct_is_confirmed(ct) && !nf_ct_is_dying(ct)) | 63 | if (!nf_ct_is_confirmed(ct) && !nf_ct_is_dying(ct)) |
| 64 | ret = __nf_conntrack_confirm(skb); | 64 | ret = __nf_conntrack_confirm(skb); |
| 65 | nf_ct_deliver_cached_events(ct); | 65 | if (likely(ret == NF_ACCEPT)) |
| 66 | nf_ct_deliver_cached_events(ct); | ||
| 66 | } | 67 | } |
| 67 | return ret; | 68 | return ret; |
| 68 | } | 69 | } |
diff --git a/include/scsi/fc/fc_fcoe.h b/include/scsi/fc/fc_fcoe.h index 57aaa8f0d613..f271d9cc0fc2 100644 --- a/include/scsi/fc/fc_fcoe.h +++ b/include/scsi/fc/fc_fcoe.h | |||
| @@ -31,10 +31,6 @@ | |||
| 31 | #define ETH_P_FCOE 0x8906 /* FCOE ether type */ | 31 | #define ETH_P_FCOE 0x8906 /* FCOE ether type */ |
| 32 | #endif | 32 | #endif |
| 33 | 33 | ||
| 34 | #ifndef ETH_P_8021Q | ||
| 35 | #define ETH_P_8021Q 0x8100 | ||
| 36 | #endif | ||
| 37 | |||
| 38 | /* | 34 | /* |
| 39 | * FC_FCOE_OUI hasn't been standardized yet. XXX TBD. | 35 | * FC_FCOE_OUI hasn't been standardized yet. XXX TBD. |
| 40 | */ | 36 | */ |
diff --git a/include/scsi/fc/fc_fs.h b/include/scsi/fc/fc_fs.h index 3e4801d2bdbb..1b7af3a64c7c 100644 --- a/include/scsi/fc/fc_fs.h +++ b/include/scsi/fc/fc_fs.h | |||
| @@ -337,4 +337,9 @@ enum fc_pf_rjt_reason { | |||
| 337 | FC_RJT_VENDOR = 0xff, /* vendor specific reject */ | 337 | FC_RJT_VENDOR = 0xff, /* vendor specific reject */ |
| 338 | }; | 338 | }; |
| 339 | 339 | ||
| 340 | /* default timeout values */ | ||
| 341 | |||
| 342 | #define FC_DEF_E_D_TOV 2000UL | ||
| 343 | #define FC_DEF_R_A_TOV 10000UL | ||
| 344 | |||
| 340 | #endif /* _FC_FS_H_ */ | 345 | #endif /* _FC_FS_H_ */ |
diff --git a/include/scsi/libfc.h b/include/scsi/libfc.h index 9f2876397dda..a2e126b86e3e 100644 --- a/include/scsi/libfc.h +++ b/include/scsi/libfc.h | |||
| @@ -68,9 +68,6 @@ | |||
| 68 | /* | 68 | /* |
| 69 | * FC HBA status | 69 | * FC HBA status |
| 70 | */ | 70 | */ |
| 71 | #define FC_PAUSE (1 << 1) | ||
| 72 | #define FC_LINK_UP (1 << 0) | ||
| 73 | |||
| 74 | enum fc_lport_state { | 71 | enum fc_lport_state { |
| 75 | LPORT_ST_NONE = 0, | 72 | LPORT_ST_NONE = 0, |
| 76 | LPORT_ST_FLOGI, | 73 | LPORT_ST_FLOGI, |
| @@ -339,31 +336,17 @@ struct fc_exch { | |||
| 339 | 336 | ||
| 340 | struct libfc_function_template { | 337 | struct libfc_function_template { |
| 341 | 338 | ||
| 342 | /** | ||
| 343 | * Mandatory Fields | ||
| 344 | * | ||
| 345 | * These handlers must be implemented by the LLD. | ||
| 346 | */ | ||
| 347 | |||
| 348 | /* | 339 | /* |
| 349 | * Interface to send a FC frame | 340 | * Interface to send a FC frame |
| 350 | */ | ||
| 351 | int (*frame_send)(struct fc_lport *lp, struct fc_frame *fp); | ||
| 352 | |||
| 353 | /** | ||
| 354 | * Optional Fields | ||
| 355 | * | 341 | * |
| 356 | * The LLD may choose to implement any of the following handlers. | 342 | * STATUS: REQUIRED |
| 357 | * If LLD doesn't specify hander and leaves its pointer NULL then | ||
| 358 | * the default libfc function will be used for that handler. | ||
| 359 | */ | ||
| 360 | |||
| 361 | /** | ||
| 362 | * ELS/CT interfaces | ||
| 363 | */ | 343 | */ |
| 344 | int (*frame_send)(struct fc_lport *lp, struct fc_frame *fp); | ||
| 364 | 345 | ||
| 365 | /* | 346 | /* |
| 366 | * elsct_send - sends ELS/CT frame | 347 | * Interface to send ELS/CT frames |
| 348 | * | ||
| 349 | * STATUS: OPTIONAL | ||
| 367 | */ | 350 | */ |
| 368 | struct fc_seq *(*elsct_send)(struct fc_lport *lport, | 351 | struct fc_seq *(*elsct_send)(struct fc_lport *lport, |
| 369 | struct fc_rport *rport, | 352 | struct fc_rport *rport, |
| @@ -373,9 +356,6 @@ struct libfc_function_template { | |||
| 373 | struct fc_frame *fp, | 356 | struct fc_frame *fp, |
| 374 | void *arg), | 357 | void *arg), |
| 375 | void *arg, u32 timer_msec); | 358 | void *arg, u32 timer_msec); |
| 376 | /** | ||
| 377 | * Exhance Manager interfaces | ||
| 378 | */ | ||
| 379 | 359 | ||
| 380 | /* | 360 | /* |
| 381 | * Send the FC frame payload using a new exchange and sequence. | 361 | * Send the FC frame payload using a new exchange and sequence. |
| @@ -407,6 +387,8 @@ struct libfc_function_template { | |||
| 407 | * timer_msec argument is specified. The timer is canceled when | 387 | * timer_msec argument is specified. The timer is canceled when |
| 408 | * it fires or when the exchange is done. The exchange timeout handler | 388 | * it fires or when the exchange is done. The exchange timeout handler |
| 409 | * is registered by EM layer. | 389 | * is registered by EM layer. |
| 390 | * | ||
| 391 | * STATUS: OPTIONAL | ||
| 410 | */ | 392 | */ |
| 411 | struct fc_seq *(*exch_seq_send)(struct fc_lport *lp, | 393 | struct fc_seq *(*exch_seq_send)(struct fc_lport *lp, |
| 412 | struct fc_frame *fp, | 394 | struct fc_frame *fp, |
| @@ -418,14 +400,18 @@ struct libfc_function_template { | |||
| 418 | void *arg, unsigned int timer_msec); | 400 | void *arg, unsigned int timer_msec); |
| 419 | 401 | ||
| 420 | /* | 402 | /* |
| 421 | * send a frame using existing sequence and exchange. | 403 | * Send a frame using an existing sequence and exchange. |
| 404 | * | ||
| 405 | * STATUS: OPTIONAL | ||
| 422 | */ | 406 | */ |
| 423 | int (*seq_send)(struct fc_lport *lp, struct fc_seq *sp, | 407 | int (*seq_send)(struct fc_lport *lp, struct fc_seq *sp, |
| 424 | struct fc_frame *fp); | 408 | struct fc_frame *fp); |
| 425 | 409 | ||
| 426 | /* | 410 | /* |
| 427 | * Send ELS response using mainly infomation | 411 | * Send an ELS response using infomation from a previous |
| 428 | * in exchange and sequence in EM layer. | 412 | * exchange and sequence. |
| 413 | * | ||
| 414 | * STATUS: OPTIONAL | ||
| 429 | */ | 415 | */ |
| 430 | void (*seq_els_rsp_send)(struct fc_seq *sp, enum fc_els_cmd els_cmd, | 416 | void (*seq_els_rsp_send)(struct fc_seq *sp, enum fc_els_cmd els_cmd, |
| 431 | struct fc_seq_els_data *els_data); | 417 | struct fc_seq_els_data *els_data); |
| @@ -437,6 +423,8 @@ struct libfc_function_template { | |||
| 437 | * A timer_msec can be specified for abort timeout, if non-zero | 423 | * A timer_msec can be specified for abort timeout, if non-zero |
| 438 | * timer_msec value is specified then exchange resp handler | 424 | * timer_msec value is specified then exchange resp handler |
| 439 | * will be called with timeout error if no response to abort. | 425 | * will be called with timeout error if no response to abort. |
| 426 | * | ||
| 427 | * STATUS: OPTIONAL | ||
| 440 | */ | 428 | */ |
| 441 | int (*seq_exch_abort)(const struct fc_seq *req_sp, | 429 | int (*seq_exch_abort)(const struct fc_seq *req_sp, |
| 442 | unsigned int timer_msec); | 430 | unsigned int timer_msec); |
| @@ -444,6 +432,8 @@ struct libfc_function_template { | |||
| 444 | /* | 432 | /* |
| 445 | * Indicate that an exchange/sequence tuple is complete and the memory | 433 | * Indicate that an exchange/sequence tuple is complete and the memory |
| 446 | * allocated for the related objects may be freed. | 434 | * allocated for the related objects may be freed. |
| 435 | * | ||
| 436 | * STATUS: OPTIONAL | ||
| 447 | */ | 437 | */ |
| 448 | void (*exch_done)(struct fc_seq *sp); | 438 | void (*exch_done)(struct fc_seq *sp); |
| 449 | 439 | ||
| @@ -451,6 +441,8 @@ struct libfc_function_template { | |||
| 451 | * Assigns a EM and a free XID for an new exchange and then | 441 | * Assigns a EM and a free XID for an new exchange and then |
| 452 | * allocates a new exchange and sequence pair. | 442 | * allocates a new exchange and sequence pair. |
| 453 | * The fp can be used to determine free XID. | 443 | * The fp can be used to determine free XID. |
| 444 | * | ||
| 445 | * STATUS: OPTIONAL | ||
| 454 | */ | 446 | */ |
| 455 | struct fc_exch *(*exch_get)(struct fc_lport *lp, struct fc_frame *fp); | 447 | struct fc_exch *(*exch_get)(struct fc_lport *lp, struct fc_frame *fp); |
| 456 | 448 | ||
| @@ -458,12 +450,16 @@ struct libfc_function_template { | |||
| 458 | * Release previously assigned XID by exch_get API. | 450 | * Release previously assigned XID by exch_get API. |
| 459 | * The LLD may implement this if XID is assigned by LLD | 451 | * The LLD may implement this if XID is assigned by LLD |
| 460 | * in exch_get(). | 452 | * in exch_get(). |
| 453 | * | ||
| 454 | * STATUS: OPTIONAL | ||
| 461 | */ | 455 | */ |
| 462 | void (*exch_put)(struct fc_lport *lp, struct fc_exch_mgr *mp, | 456 | void (*exch_put)(struct fc_lport *lp, struct fc_exch_mgr *mp, |
| 463 | u16 ex_id); | 457 | u16 ex_id); |
| 464 | 458 | ||
| 465 | /* | 459 | /* |
| 466 | * Start a new sequence on the same exchange/sequence tuple. | 460 | * Start a new sequence on the same exchange/sequence tuple. |
| 461 | * | ||
| 462 | * STATUS: OPTIONAL | ||
| 467 | */ | 463 | */ |
| 468 | struct fc_seq *(*seq_start_next)(struct fc_seq *sp); | 464 | struct fc_seq *(*seq_start_next)(struct fc_seq *sp); |
| 469 | 465 | ||
| @@ -471,26 +467,38 @@ struct libfc_function_template { | |||
| 471 | * Reset an exchange manager, completing all sequences and exchanges. | 467 | * Reset an exchange manager, completing all sequences and exchanges. |
| 472 | * If s_id is non-zero, reset only exchanges originating from that FID. | 468 | * If s_id is non-zero, reset only exchanges originating from that FID. |
| 473 | * If d_id is non-zero, reset only exchanges sending to that FID. | 469 | * If d_id is non-zero, reset only exchanges sending to that FID. |
| 470 | * | ||
| 471 | * STATUS: OPTIONAL | ||
| 474 | */ | 472 | */ |
| 475 | void (*exch_mgr_reset)(struct fc_exch_mgr *, | 473 | void (*exch_mgr_reset)(struct fc_lport *, |
| 476 | u32 s_id, u32 d_id); | 474 | u32 s_id, u32 d_id); |
| 477 | 475 | ||
| 478 | void (*rport_flush_queue)(void); | 476 | /* |
| 479 | /** | 477 | * Flush the rport work queue. Generally used before shutdown. |
| 480 | * Local Port interfaces | 478 | * |
| 479 | * STATUS: OPTIONAL | ||
| 481 | */ | 480 | */ |
| 481 | void (*rport_flush_queue)(void); | ||
| 482 | 482 | ||
| 483 | /* | 483 | /* |
| 484 | * Receive a frame to a local port. | 484 | * Receive a frame for a local port. |
| 485 | * | ||
| 486 | * STATUS: OPTIONAL | ||
| 485 | */ | 487 | */ |
| 486 | void (*lport_recv)(struct fc_lport *lp, struct fc_seq *sp, | 488 | void (*lport_recv)(struct fc_lport *lp, struct fc_seq *sp, |
| 487 | struct fc_frame *fp); | 489 | struct fc_frame *fp); |
| 488 | 490 | ||
| 491 | /* | ||
| 492 | * Reset the local port. | ||
| 493 | * | ||
| 494 | * STATUS: OPTIONAL | ||
| 495 | */ | ||
| 489 | int (*lport_reset)(struct fc_lport *); | 496 | int (*lport_reset)(struct fc_lport *); |
| 490 | 497 | ||
| 491 | /** | 498 | /* |
| 492 | * Remote Port interfaces | 499 | * Create a remote port |
| 493 | */ | 500 | */ |
| 501 | struct fc_rport *(*rport_create)(struct fc_disc_port *); | ||
| 494 | 502 | ||
| 495 | /* | 503 | /* |
| 496 | * Initiates the RP state machine. It is called from the LP module. | 504 | * Initiates the RP state machine. It is called from the LP module. |
| @@ -500,26 +508,33 @@ struct libfc_function_template { | |||
| 500 | * - PLOGI | 508 | * - PLOGI |
| 501 | * - PRLI | 509 | * - PRLI |
| 502 | * - RTV | 510 | * - RTV |
| 511 | * | ||
| 512 | * STATUS: OPTIONAL | ||
| 503 | */ | 513 | */ |
| 504 | int (*rport_login)(struct fc_rport *rport); | 514 | int (*rport_login)(struct fc_rport *rport); |
| 505 | 515 | ||
| 506 | /* | 516 | /* |
| 507 | * Logoff, and remove the rport from the transport if | 517 | * Logoff, and remove the rport from the transport if |
| 508 | * it had been added. This will send a LOGO to the target. | 518 | * it had been added. This will send a LOGO to the target. |
| 519 | * | ||
| 520 | * STATUS: OPTIONAL | ||
| 509 | */ | 521 | */ |
| 510 | int (*rport_logoff)(struct fc_rport *rport); | 522 | int (*rport_logoff)(struct fc_rport *rport); |
| 511 | 523 | ||
| 512 | /* | 524 | /* |
| 513 | * Recieve a request from a remote port. | 525 | * Recieve a request from a remote port. |
| 526 | * | ||
| 527 | * STATUS: OPTIONAL | ||
| 514 | */ | 528 | */ |
| 515 | void (*rport_recv_req)(struct fc_seq *, struct fc_frame *, | 529 | void (*rport_recv_req)(struct fc_seq *, struct fc_frame *, |
| 516 | struct fc_rport *); | 530 | struct fc_rport *); |
| 517 | 531 | ||
| 518 | struct fc_rport *(*rport_lookup)(const struct fc_lport *, u32); | 532 | /* |
| 519 | 533 | * lookup an rport by it's port ID. | |
| 520 | /** | 534 | * |
| 521 | * FCP interfaces | 535 | * STATUS: OPTIONAL |
| 522 | */ | 536 | */ |
| 537 | struct fc_rport *(*rport_lookup)(const struct fc_lport *, u32); | ||
| 523 | 538 | ||
| 524 | /* | 539 | /* |
| 525 | * Send a fcp cmd from fsp pkt. | 540 | * Send a fcp cmd from fsp pkt. |
| @@ -527,30 +542,38 @@ struct libfc_function_template { | |||
| 527 | * | 542 | * |
| 528 | * The resp handler is called when FCP_RSP received. | 543 | * The resp handler is called when FCP_RSP received. |
| 529 | * | 544 | * |
| 545 | * STATUS: OPTIONAL | ||
| 530 | */ | 546 | */ |
| 531 | int (*fcp_cmd_send)(struct fc_lport *lp, struct fc_fcp_pkt *fsp, | 547 | int (*fcp_cmd_send)(struct fc_lport *lp, struct fc_fcp_pkt *fsp, |
| 532 | void (*resp)(struct fc_seq *, struct fc_frame *fp, | 548 | void (*resp)(struct fc_seq *, struct fc_frame *fp, |
| 533 | void *arg)); | 549 | void *arg)); |
| 534 | 550 | ||
| 535 | /* | 551 | /* |
| 536 | * Used at least durring linkdown and reset | 552 | * Cleanup the FCP layer, used durring link down and reset |
| 553 | * | ||
| 554 | * STATUS: OPTIONAL | ||
| 537 | */ | 555 | */ |
| 538 | void (*fcp_cleanup)(struct fc_lport *lp); | 556 | void (*fcp_cleanup)(struct fc_lport *lp); |
| 539 | 557 | ||
| 540 | /* | 558 | /* |
| 541 | * Abort all I/O on a local port | 559 | * Abort all I/O on a local port |
| 560 | * | ||
| 561 | * STATUS: OPTIONAL | ||
| 542 | */ | 562 | */ |
| 543 | void (*fcp_abort_io)(struct fc_lport *lp); | 563 | void (*fcp_abort_io)(struct fc_lport *lp); |
| 544 | 564 | ||
| 545 | /** | 565 | /* |
| 546 | * Discovery interfaces | 566 | * Receive a request for the discovery layer. |
| 567 | * | ||
| 568 | * STATUS: OPTIONAL | ||
| 547 | */ | 569 | */ |
| 548 | |||
| 549 | void (*disc_recv_req)(struct fc_seq *, | 570 | void (*disc_recv_req)(struct fc_seq *, |
| 550 | struct fc_frame *, struct fc_lport *); | 571 | struct fc_frame *, struct fc_lport *); |
| 551 | 572 | ||
| 552 | /* | 573 | /* |
| 553 | * Start discovery for a local port. | 574 | * Start discovery for a local port. |
| 575 | * | ||
| 576 | * STATUS: OPTIONAL | ||
| 554 | */ | 577 | */ |
| 555 | void (*disc_start)(void (*disc_callback)(struct fc_lport *, | 578 | void (*disc_start)(void (*disc_callback)(struct fc_lport *, |
| 556 | enum fc_disc_event), | 579 | enum fc_disc_event), |
| @@ -559,6 +582,8 @@ struct libfc_function_template { | |||
| 559 | /* | 582 | /* |
| 560 | * Stop discovery for a given lport. This will remove | 583 | * Stop discovery for a given lport. This will remove |
| 561 | * all discovered rports | 584 | * all discovered rports |
| 585 | * | ||
| 586 | * STATUS: OPTIONAL | ||
| 562 | */ | 587 | */ |
| 563 | void (*disc_stop) (struct fc_lport *); | 588 | void (*disc_stop) (struct fc_lport *); |
| 564 | 589 | ||
| @@ -566,6 +591,8 @@ struct libfc_function_template { | |||
| 566 | * Stop discovery for a given lport. This will block | 591 | * Stop discovery for a given lport. This will block |
| 567 | * until all discovered rports are deleted from the | 592 | * until all discovered rports are deleted from the |
| 568 | * FC transport class | 593 | * FC transport class |
| 594 | * | ||
| 595 | * STATUS: OPTIONAL | ||
| 569 | */ | 596 | */ |
| 570 | void (*disc_stop_final) (struct fc_lport *); | 597 | void (*disc_stop_final) (struct fc_lport *); |
| 571 | }; | 598 | }; |
| @@ -603,7 +630,8 @@ struct fc_lport { | |||
| 603 | 630 | ||
| 604 | /* Operational Information */ | 631 | /* Operational Information */ |
| 605 | struct libfc_function_template tt; | 632 | struct libfc_function_template tt; |
| 606 | u16 link_status; | 633 | u8 link_up; |
| 634 | u8 qfull; | ||
| 607 | enum fc_lport_state state; | 635 | enum fc_lport_state state; |
| 608 | unsigned long boot_time; | 636 | unsigned long boot_time; |
| 609 | 637 | ||
| @@ -637,7 +665,7 @@ struct fc_lport { | |||
| 637 | struct delayed_work disc_work; | 665 | struct delayed_work disc_work; |
| 638 | }; | 666 | }; |
| 639 | 667 | ||
| 640 | /** | 668 | /* |
| 641 | * FC_LPORT HELPER FUNCTIONS | 669 | * FC_LPORT HELPER FUNCTIONS |
| 642 | *****************************/ | 670 | *****************************/ |
| 643 | static inline void *lport_priv(const struct fc_lport *lp) | 671 | static inline void *lport_priv(const struct fc_lport *lp) |
| @@ -669,7 +697,7 @@ static inline void fc_lport_state_enter(struct fc_lport *lp, | |||
| 669 | } | 697 | } |
| 670 | 698 | ||
| 671 | 699 | ||
| 672 | /** | 700 | /* |
| 673 | * LOCAL PORT LAYER | 701 | * LOCAL PORT LAYER |
| 674 | *****************************/ | 702 | *****************************/ |
| 675 | int fc_lport_init(struct fc_lport *lp); | 703 | int fc_lport_init(struct fc_lport *lp); |
| @@ -704,12 +732,6 @@ void fc_linkup(struct fc_lport *); | |||
| 704 | void fc_linkdown(struct fc_lport *); | 732 | void fc_linkdown(struct fc_lport *); |
| 705 | 733 | ||
| 706 | /* | 734 | /* |
| 707 | * Pause and unpause traffic. | ||
| 708 | */ | ||
| 709 | void fc_pause(struct fc_lport *); | ||
| 710 | void fc_unpause(struct fc_lport *); | ||
| 711 | |||
| 712 | /* | ||
| 713 | * Configure the local port. | 735 | * Configure the local port. |
| 714 | */ | 736 | */ |
| 715 | int fc_lport_config(struct fc_lport *); | 737 | int fc_lport_config(struct fc_lport *); |
| @@ -725,19 +747,19 @@ int fc_lport_reset(struct fc_lport *); | |||
| 725 | int fc_set_mfs(struct fc_lport *lp, u32 mfs); | 747 | int fc_set_mfs(struct fc_lport *lp, u32 mfs); |
| 726 | 748 | ||
| 727 | 749 | ||
| 728 | /** | 750 | /* |
| 729 | * REMOTE PORT LAYER | 751 | * REMOTE PORT LAYER |
| 730 | *****************************/ | 752 | *****************************/ |
| 731 | int fc_rport_init(struct fc_lport *lp); | 753 | int fc_rport_init(struct fc_lport *lp); |
| 732 | void fc_rport_terminate_io(struct fc_rport *rp); | 754 | void fc_rport_terminate_io(struct fc_rport *rp); |
| 733 | 755 | ||
| 734 | /** | 756 | /* |
| 735 | * DISCOVERY LAYER | 757 | * DISCOVERY LAYER |
| 736 | *****************************/ | 758 | *****************************/ |
| 737 | int fc_disc_init(struct fc_lport *lp); | 759 | int fc_disc_init(struct fc_lport *lp); |
| 738 | 760 | ||
| 739 | 761 | ||
| 740 | /** | 762 | /* |
| 741 | * SCSI LAYER | 763 | * SCSI LAYER |
| 742 | *****************************/ | 764 | *****************************/ |
| 743 | /* | 765 | /* |
| @@ -798,7 +820,7 @@ int fc_change_queue_type(struct scsi_device *sdev, int tag_type); | |||
| 798 | */ | 820 | */ |
| 799 | void fc_fcp_destroy(struct fc_lport *); | 821 | void fc_fcp_destroy(struct fc_lport *); |
| 800 | 822 | ||
| 801 | /** | 823 | /* |
| 802 | * ELS/CT interface | 824 | * ELS/CT interface |
| 803 | *****************************/ | 825 | *****************************/ |
| 804 | /* | 826 | /* |
| @@ -807,7 +829,7 @@ void fc_fcp_destroy(struct fc_lport *); | |||
| 807 | int fc_elsct_init(struct fc_lport *lp); | 829 | int fc_elsct_init(struct fc_lport *lp); |
| 808 | 830 | ||
| 809 | 831 | ||
| 810 | /** | 832 | /* |
| 811 | * EXCHANGE MANAGER LAYER | 833 | * EXCHANGE MANAGER LAYER |
| 812 | *****************************/ | 834 | *****************************/ |
| 813 | /* | 835 | /* |
| @@ -916,7 +938,7 @@ struct fc_seq *fc_seq_start_next(struct fc_seq *sp); | |||
| 916 | * If s_id is non-zero, reset only exchanges originating from that FID. | 938 | * If s_id is non-zero, reset only exchanges originating from that FID. |
| 917 | * If d_id is non-zero, reset only exchanges sending to that FID. | 939 | * If d_id is non-zero, reset only exchanges sending to that FID. |
| 918 | */ | 940 | */ |
| 919 | void fc_exch_mgr_reset(struct fc_exch_mgr *, u32 s_id, u32 d_id); | 941 | void fc_exch_mgr_reset(struct fc_lport *, u32 s_id, u32 d_id); |
| 920 | 942 | ||
| 921 | /* | 943 | /* |
| 922 | * Functions for fc_functions_template | 944 | * Functions for fc_functions_template |
diff --git a/include/scsi/libfcoe.h b/include/scsi/libfcoe.h index 89fdbb9a6a1b..941818f29f59 100644 --- a/include/scsi/libfcoe.h +++ b/include/scsi/libfcoe.h | |||
| @@ -46,6 +46,7 @@ struct fcoe_softc { | |||
| 46 | struct net_device *phys_dev; /* device with ethtool_ops */ | 46 | struct net_device *phys_dev; /* device with ethtool_ops */ |
| 47 | struct packet_type fcoe_packet_type; | 47 | struct packet_type fcoe_packet_type; |
| 48 | struct sk_buff_head fcoe_pending_queue; | 48 | struct sk_buff_head fcoe_pending_queue; |
| 49 | u8 fcoe_pending_queue_active; | ||
| 49 | 50 | ||
| 50 | u8 dest_addr[ETH_ALEN]; | 51 | u8 dest_addr[ETH_ALEN]; |
| 51 | u8 ctl_src_addr[ETH_ALEN]; | 52 | u8 ctl_src_addr[ETH_ALEN]; |
| @@ -58,16 +59,10 @@ struct fcoe_softc { | |||
| 58 | u8 address_mode; | 59 | u8 address_mode; |
| 59 | }; | 60 | }; |
| 60 | 61 | ||
| 61 | static inline struct fcoe_softc *fcoe_softc( | ||
| 62 | const struct fc_lport *lp) | ||
| 63 | { | ||
| 64 | return (struct fcoe_softc *)lport_priv(lp); | ||
| 65 | } | ||
| 66 | |||
| 67 | static inline struct net_device *fcoe_netdev( | 62 | static inline struct net_device *fcoe_netdev( |
| 68 | const struct fc_lport *lp) | 63 | const struct fc_lport *lp) |
| 69 | { | 64 | { |
| 70 | return fcoe_softc(lp)->real_dev; | 65 | return ((struct fcoe_softc *)lport_priv(lp))->real_dev; |
| 71 | } | 66 | } |
| 72 | 67 | ||
| 73 | static inline struct fcoe_hdr *skb_fcoe_header(const struct sk_buff *skb) | 68 | static inline struct fcoe_hdr *skb_fcoe_header(const struct sk_buff *skb) |
diff --git a/include/video/broadsheetfb.h b/include/video/broadsheetfb.h new file mode 100644 index 000000000000..a758534c0272 --- /dev/null +++ b/include/video/broadsheetfb.h | |||
| @@ -0,0 +1,59 @@ | |||
| 1 | /* | ||
| 2 | * broadsheetfb.h - definitions for the broadsheet framebuffer driver | ||
| 3 | * | ||
| 4 | * Copyright (C) 2008 by Jaya Kumar | ||
| 5 | * | ||
| 6 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 7 | * License. See the file COPYING in the main directory of this archive for | ||
| 8 | * more details. | ||
| 9 | * | ||
| 10 | */ | ||
| 11 | |||
| 12 | #ifndef _LINUX_BROADSHEETFB_H_ | ||
| 13 | #define _LINUX_BROADSHEETFB_H_ | ||
| 14 | |||
| 15 | /* Broadsheet command defines */ | ||
| 16 | #define BS_CMD_INIT_SYS_RUN 0x06 | ||
| 17 | #define BS_CMD_INIT_DSPE_CFG 0x09 | ||
| 18 | #define BS_CMD_INIT_DSPE_TMG 0x0A | ||
| 19 | #define BS_CMD_INIT_ROTMODE 0x0B | ||
| 20 | #define BS_CMD_RD_REG 0x10 | ||
| 21 | #define BS_CMD_WR_REG 0x11 | ||
| 22 | #define BS_CMD_LD_IMG 0x20 | ||
| 23 | #define BS_CMD_LD_IMG_AREA 0x22 | ||
| 24 | #define BS_CMD_LD_IMG_END 0x23 | ||
| 25 | #define BS_CMD_WAIT_DSPE_TRG 0x28 | ||
| 26 | #define BS_CMD_WAIT_DSPE_FREND 0x29 | ||
| 27 | #define BS_CMD_RD_WFM_INFO 0x30 | ||
| 28 | #define BS_CMD_UPD_INIT 0x32 | ||
| 29 | #define BS_CMD_UPD_FULL 0x33 | ||
| 30 | #define BS_CMD_UPD_GDRV_CLR 0x37 | ||
| 31 | |||
| 32 | /* Broadsheet pin interface specific defines */ | ||
| 33 | #define BS_CS 0x01 | ||
| 34 | #define BS_DC 0x02 | ||
| 35 | #define BS_WR 0x03 | ||
| 36 | |||
| 37 | /* struct used by broadsheet. board specific stuff comes from *board */ | ||
| 38 | struct broadsheetfb_par { | ||
| 39 | struct fb_info *info; | ||
| 40 | struct broadsheet_board *board; | ||
| 41 | void (*write_reg)(struct broadsheetfb_par *, u16 reg, u16 val); | ||
| 42 | u16 (*read_reg)(struct broadsheetfb_par *, u16 reg); | ||
| 43 | wait_queue_head_t waitq; | ||
| 44 | }; | ||
| 45 | |||
| 46 | /* board specific routines */ | ||
| 47 | struct broadsheet_board { | ||
| 48 | struct module *owner; | ||
| 49 | int (*init)(struct broadsheetfb_par *); | ||
| 50 | int (*wait_for_rdy)(struct broadsheetfb_par *); | ||
| 51 | void (*set_ctl)(struct broadsheetfb_par *, unsigned char, u8); | ||
| 52 | void (*set_hdb)(struct broadsheetfb_par *, u16); | ||
| 53 | u16 (*get_hdb)(struct broadsheetfb_par *); | ||
| 54 | void (*cleanup)(struct broadsheetfb_par *); | ||
| 55 | int (*get_panel_type)(void); | ||
| 56 | int (*setup_irq)(struct fb_info *); | ||
| 57 | }; | ||
| 58 | |||
| 59 | #endif | ||
diff --git a/init/Kconfig b/init/Kconfig index f068071fcc5d..6a5c5fed66c9 100644 --- a/init/Kconfig +++ b/init/Kconfig | |||
| @@ -675,6 +675,9 @@ config CC_OPTIMIZE_FOR_SIZE | |||
| 675 | config SYSCTL | 675 | config SYSCTL |
| 676 | bool | 676 | bool |
| 677 | 677 | ||
| 678 | config ANON_INODES | ||
| 679 | bool | ||
| 680 | |||
| 678 | menuconfig EMBEDDED | 681 | menuconfig EMBEDDED |
| 679 | bool "Configure standard kernel features (for small systems)" | 682 | bool "Configure standard kernel features (for small systems)" |
| 680 | help | 683 | help |
| @@ -780,18 +783,6 @@ config PCSPKR_PLATFORM | |||
| 780 | This option allows to disable the internal PC-Speaker | 783 | This option allows to disable the internal PC-Speaker |
| 781 | support, saving some memory. | 784 | support, saving some memory. |
| 782 | 785 | ||
| 783 | config COMPAT_BRK | ||
| 784 | bool "Disable heap randomization" | ||
| 785 | default y | ||
| 786 | help | ||
| 787 | Randomizing heap placement makes heap exploits harder, but it | ||
| 788 | also breaks ancient binaries (including anything libc5 based). | ||
| 789 | This option changes the bootup default to heap randomization | ||
| 790 | disabled, and can be overriden runtime by setting | ||
| 791 | /proc/sys/kernel/randomize_va_space to 2. | ||
| 792 | |||
| 793 | On non-ancient distros (post-2000 ones) N is usually a safe choice. | ||
| 794 | |||
| 795 | config BASE_FULL | 786 | config BASE_FULL |
| 796 | default y | 787 | default y |
| 797 | bool "Enable full-sized data structures for core" if EMBEDDED | 788 | bool "Enable full-sized data structures for core" if EMBEDDED |
| @@ -809,9 +800,6 @@ config FUTEX | |||
| 809 | support for "fast userspace mutexes". The resulting kernel may not | 800 | support for "fast userspace mutexes". The resulting kernel may not |
| 810 | run glibc-based applications correctly. | 801 | run glibc-based applications correctly. |
| 811 | 802 | ||
| 812 | config ANON_INODES | ||
| 813 | bool | ||
| 814 | |||
| 815 | config EPOLL | 803 | config EPOLL |
| 816 | bool "Enable eventpoll support" if EMBEDDED | 804 | bool "Enable eventpoll support" if EMBEDDED |
| 817 | default y | 805 | default y |
| @@ -897,6 +885,18 @@ config SLUB_DEBUG | |||
| 897 | SLUB sysfs support. /sys/slab will not exist and there will be | 885 | SLUB sysfs support. /sys/slab will not exist and there will be |
| 898 | no support for cache validation etc. | 886 | no support for cache validation etc. |
| 899 | 887 | ||
| 888 | config COMPAT_BRK | ||
| 889 | bool "Disable heap randomization" | ||
| 890 | default y | ||
| 891 | help | ||
| 892 | Randomizing heap placement makes heap exploits harder, but it | ||
| 893 | also breaks ancient binaries (including anything libc5 based). | ||
| 894 | This option changes the bootup default to heap randomization | ||
| 895 | disabled, and can be overriden runtime by setting | ||
| 896 | /proc/sys/kernel/randomize_va_space to 2. | ||
| 897 | |||
| 898 | On non-ancient distros (post-2000 ones) N is usually a safe choice. | ||
| 899 | |||
| 900 | choice | 900 | choice |
| 901 | prompt "Choose SLAB allocator" | 901 | prompt "Choose SLAB allocator" |
| 902 | default SLUB | 902 | default SLUB |
diff --git a/kernel/fork.c b/kernel/fork.c index a66fbde20715..4854c2c4a82e 100644 --- a/kernel/fork.c +++ b/kernel/fork.c | |||
| @@ -1179,10 +1179,6 @@ static struct task_struct *copy_process(unsigned long clone_flags, | |||
| 1179 | #endif | 1179 | #endif |
| 1180 | clear_all_latency_tracing(p); | 1180 | clear_all_latency_tracing(p); |
| 1181 | 1181 | ||
| 1182 | /* Our parent execution domain becomes current domain | ||
| 1183 | These must match for thread signalling to apply */ | ||
| 1184 | p->parent_exec_id = p->self_exec_id; | ||
| 1185 | |||
| 1186 | /* ok, now we should be set up.. */ | 1182 | /* ok, now we should be set up.. */ |
| 1187 | p->exit_signal = (clone_flags & CLONE_THREAD) ? -1 : (clone_flags & CSIGNAL); | 1183 | p->exit_signal = (clone_flags & CLONE_THREAD) ? -1 : (clone_flags & CSIGNAL); |
| 1188 | p->pdeath_signal = 0; | 1184 | p->pdeath_signal = 0; |
| @@ -1220,10 +1216,13 @@ static struct task_struct *copy_process(unsigned long clone_flags, | |||
| 1220 | set_task_cpu(p, smp_processor_id()); | 1216 | set_task_cpu(p, smp_processor_id()); |
| 1221 | 1217 | ||
| 1222 | /* CLONE_PARENT re-uses the old parent */ | 1218 | /* CLONE_PARENT re-uses the old parent */ |
| 1223 | if (clone_flags & (CLONE_PARENT|CLONE_THREAD)) | 1219 | if (clone_flags & (CLONE_PARENT|CLONE_THREAD)) { |
| 1224 | p->real_parent = current->real_parent; | 1220 | p->real_parent = current->real_parent; |
| 1225 | else | 1221 | p->parent_exec_id = current->parent_exec_id; |
| 1222 | } else { | ||
| 1226 | p->real_parent = current; | 1223 | p->real_parent = current; |
| 1224 | p->parent_exec_id = current->self_exec_id; | ||
| 1225 | } | ||
| 1227 | 1226 | ||
| 1228 | spin_lock(¤t->sighand->siglock); | 1227 | spin_lock(¤t->sighand->siglock); |
| 1229 | 1228 | ||
diff --git a/kernel/module.c b/kernel/module.c index ba22484a987e..1196f5d11700 100644 --- a/kernel/module.c +++ b/kernel/module.c | |||
| @@ -2015,14 +2015,6 @@ static noinline struct module *load_module(void __user *umod, | |||
| 2015 | if (err < 0) | 2015 | if (err < 0) |
| 2016 | goto free_mod; | 2016 | goto free_mod; |
| 2017 | 2017 | ||
| 2018 | #if defined(CONFIG_MODULE_UNLOAD) && defined(CONFIG_SMP) | ||
| 2019 | mod->refptr = percpu_modalloc(sizeof(local_t), __alignof__(local_t), | ||
| 2020 | mod->name); | ||
| 2021 | if (!mod->refptr) { | ||
| 2022 | err = -ENOMEM; | ||
| 2023 | goto free_mod; | ||
| 2024 | } | ||
| 2025 | #endif | ||
| 2026 | if (pcpuindex) { | 2018 | if (pcpuindex) { |
| 2027 | /* We have a special allocation for this section. */ | 2019 | /* We have a special allocation for this section. */ |
| 2028 | percpu = percpu_modalloc(sechdrs[pcpuindex].sh_size, | 2020 | percpu = percpu_modalloc(sechdrs[pcpuindex].sh_size, |
| @@ -2030,7 +2022,7 @@ static noinline struct module *load_module(void __user *umod, | |||
| 2030 | mod->name); | 2022 | mod->name); |
| 2031 | if (!percpu) { | 2023 | if (!percpu) { |
| 2032 | err = -ENOMEM; | 2024 | err = -ENOMEM; |
| 2033 | goto free_percpu; | 2025 | goto free_mod; |
| 2034 | } | 2026 | } |
| 2035 | sechdrs[pcpuindex].sh_flags &= ~(unsigned long)SHF_ALLOC; | 2027 | sechdrs[pcpuindex].sh_flags &= ~(unsigned long)SHF_ALLOC; |
| 2036 | mod->percpu = percpu; | 2028 | mod->percpu = percpu; |
| @@ -2082,6 +2074,14 @@ static noinline struct module *load_module(void __user *umod, | |||
| 2082 | /* Module has been moved. */ | 2074 | /* Module has been moved. */ |
| 2083 | mod = (void *)sechdrs[modindex].sh_addr; | 2075 | mod = (void *)sechdrs[modindex].sh_addr; |
| 2084 | 2076 | ||
| 2077 | #if defined(CONFIG_MODULE_UNLOAD) && defined(CONFIG_SMP) | ||
| 2078 | mod->refptr = percpu_modalloc(sizeof(local_t), __alignof__(local_t), | ||
| 2079 | mod->name); | ||
| 2080 | if (!mod->refptr) { | ||
| 2081 | err = -ENOMEM; | ||
| 2082 | goto free_init; | ||
| 2083 | } | ||
| 2084 | #endif | ||
| 2085 | /* Now we've moved module, initialize linked lists, etc. */ | 2085 | /* Now we've moved module, initialize linked lists, etc. */ |
| 2086 | module_unload_init(mod); | 2086 | module_unload_init(mod); |
| 2087 | 2087 | ||
| @@ -2288,15 +2288,17 @@ static noinline struct module *load_module(void __user *umod, | |||
| 2288 | ftrace_release(mod->module_core, mod->core_size); | 2288 | ftrace_release(mod->module_core, mod->core_size); |
| 2289 | free_unload: | 2289 | free_unload: |
| 2290 | module_unload_free(mod); | 2290 | module_unload_free(mod); |
| 2291 | free_init: | ||
| 2292 | #if defined(CONFIG_MODULE_UNLOAD) && defined(CONFIG_SMP) | ||
| 2293 | percpu_modfree(mod->refptr); | ||
| 2294 | #endif | ||
| 2291 | module_free(mod, mod->module_init); | 2295 | module_free(mod, mod->module_init); |
| 2292 | free_core: | 2296 | free_core: |
| 2293 | module_free(mod, mod->module_core); | 2297 | module_free(mod, mod->module_core); |
| 2298 | /* mod will be freed with core. Don't access it beyond this line! */ | ||
| 2294 | free_percpu: | 2299 | free_percpu: |
| 2295 | if (percpu) | 2300 | if (percpu) |
| 2296 | percpu_modfree(percpu); | 2301 | percpu_modfree(percpu); |
| 2297 | #if defined(CONFIG_MODULE_UNLOAD) && defined(CONFIG_SMP) | ||
| 2298 | percpu_modfree(mod->refptr); | ||
| 2299 | #endif | ||
| 2300 | free_mod: | 2302 | free_mod: |
| 2301 | kfree(args); | 2303 | kfree(args); |
| 2302 | free_hdr: | 2304 | free_hdr: |
diff --git a/kernel/signal.c b/kernel/signal.c index 2a74fe87c0dd..1c8814481a11 100644 --- a/kernel/signal.c +++ b/kernel/signal.c | |||
| @@ -1575,7 +1575,15 @@ static void ptrace_stop(int exit_code, int clear_code, siginfo_t *info) | |||
| 1575 | read_lock(&tasklist_lock); | 1575 | read_lock(&tasklist_lock); |
| 1576 | if (may_ptrace_stop()) { | 1576 | if (may_ptrace_stop()) { |
| 1577 | do_notify_parent_cldstop(current, CLD_TRAPPED); | 1577 | do_notify_parent_cldstop(current, CLD_TRAPPED); |
| 1578 | /* | ||
| 1579 | * Don't want to allow preemption here, because | ||
| 1580 | * sys_ptrace() needs this task to be inactive. | ||
| 1581 | * | ||
| 1582 | * XXX: implement read_unlock_no_resched(). | ||
| 1583 | */ | ||
| 1584 | preempt_disable(); | ||
| 1578 | read_unlock(&tasklist_lock); | 1585 | read_unlock(&tasklist_lock); |
| 1586 | preempt_enable_no_resched(); | ||
| 1579 | schedule(); | 1587 | schedule(); |
| 1580 | } else { | 1588 | } else { |
| 1581 | /* | 1589 | /* |
diff --git a/kernel/softirq.c b/kernel/softirq.c index bdbe9de9cd8d..9041ea7948fe 100644 --- a/kernel/softirq.c +++ b/kernel/softirq.c | |||
| @@ -626,6 +626,7 @@ static int ksoftirqd(void * __bind_cpu) | |||
| 626 | preempt_enable_no_resched(); | 626 | preempt_enable_no_resched(); |
| 627 | cond_resched(); | 627 | cond_resched(); |
| 628 | preempt_disable(); | 628 | preempt_disable(); |
| 629 | rcu_qsctr_inc((long)__bind_cpu); | ||
| 629 | } | 630 | } |
| 630 | preempt_enable(); | 631 | preempt_enable(); |
| 631 | set_current_state(TASK_INTERRUPTIBLE); | 632 | set_current_state(TASK_INTERRUPTIBLE); |
diff --git a/kernel/tsacct.c b/kernel/tsacct.c index 43f891b05a4b..00d59d048edf 100644 --- a/kernel/tsacct.c +++ b/kernel/tsacct.c | |||
| @@ -122,8 +122,10 @@ void acct_update_integrals(struct task_struct *tsk) | |||
| 122 | if (likely(tsk->mm)) { | 122 | if (likely(tsk->mm)) { |
| 123 | cputime_t time, dtime; | 123 | cputime_t time, dtime; |
| 124 | struct timeval value; | 124 | struct timeval value; |
| 125 | unsigned long flags; | ||
| 125 | u64 delta; | 126 | u64 delta; |
| 126 | 127 | ||
| 128 | local_irq_save(flags); | ||
| 127 | time = tsk->stime + tsk->utime; | 129 | time = tsk->stime + tsk->utime; |
| 128 | dtime = cputime_sub(time, tsk->acct_timexpd); | 130 | dtime = cputime_sub(time, tsk->acct_timexpd); |
| 129 | jiffies_to_timeval(cputime_to_jiffies(dtime), &value); | 131 | jiffies_to_timeval(cputime_to_jiffies(dtime), &value); |
| @@ -131,10 +133,12 @@ void acct_update_integrals(struct task_struct *tsk) | |||
| 131 | delta = delta * USEC_PER_SEC + value.tv_usec; | 133 | delta = delta * USEC_PER_SEC + value.tv_usec; |
| 132 | 134 | ||
| 133 | if (delta == 0) | 135 | if (delta == 0) |
| 134 | return; | 136 | goto out; |
| 135 | tsk->acct_timexpd = time; | 137 | tsk->acct_timexpd = time; |
| 136 | tsk->acct_rss_mem1 += delta * get_mm_rss(tsk->mm); | 138 | tsk->acct_rss_mem1 += delta * get_mm_rss(tsk->mm); |
| 137 | tsk->acct_vm_mem1 += delta * tsk->mm->total_vm; | 139 | tsk->acct_vm_mem1 += delta * tsk->mm->total_vm; |
| 140 | out: | ||
| 141 | local_irq_restore(flags); | ||
| 138 | } | 142 | } |
| 139 | } | 143 | } |
| 140 | 144 | ||
diff --git a/kernel/user.c b/kernel/user.c index 6a9b696128c8..fbb300e6191f 100644 --- a/kernel/user.c +++ b/kernel/user.c | |||
| @@ -286,14 +286,12 @@ int __init uids_sysfs_init(void) | |||
| 286 | /* work function to remove sysfs directory for a user and free up | 286 | /* work function to remove sysfs directory for a user and free up |
| 287 | * corresponding structures. | 287 | * corresponding structures. |
| 288 | */ | 288 | */ |
| 289 | static void remove_user_sysfs_dir(struct work_struct *w) | 289 | static void cleanup_user_struct(struct work_struct *w) |
| 290 | { | 290 | { |
| 291 | struct user_struct *up = container_of(w, struct user_struct, work); | 291 | struct user_struct *up = container_of(w, struct user_struct, work); |
| 292 | unsigned long flags; | 292 | unsigned long flags; |
| 293 | int remove_user = 0; | 293 | int remove_user = 0; |
| 294 | 294 | ||
| 295 | if (up->user_ns != &init_user_ns) | ||
| 296 | return; | ||
| 297 | /* Make uid_hash_remove() + sysfs_remove_file() + kobject_del() | 295 | /* Make uid_hash_remove() + sysfs_remove_file() + kobject_del() |
| 298 | * atomic. | 296 | * atomic. |
| 299 | */ | 297 | */ |
| @@ -312,9 +310,11 @@ static void remove_user_sysfs_dir(struct work_struct *w) | |||
| 312 | if (!remove_user) | 310 | if (!remove_user) |
| 313 | goto done; | 311 | goto done; |
| 314 | 312 | ||
| 315 | kobject_uevent(&up->kobj, KOBJ_REMOVE); | 313 | if (up->user_ns == &init_user_ns) { |
| 316 | kobject_del(&up->kobj); | 314 | kobject_uevent(&up->kobj, KOBJ_REMOVE); |
| 317 | kobject_put(&up->kobj); | 315 | kobject_del(&up->kobj); |
| 316 | kobject_put(&up->kobj); | ||
| 317 | } | ||
| 318 | 318 | ||
| 319 | sched_destroy_user(up); | 319 | sched_destroy_user(up); |
| 320 | key_put(up->uid_keyring); | 320 | key_put(up->uid_keyring); |
| @@ -335,7 +335,7 @@ static void free_user(struct user_struct *up, unsigned long flags) | |||
| 335 | atomic_inc(&up->__count); | 335 | atomic_inc(&up->__count); |
| 336 | spin_unlock_irqrestore(&uidhash_lock, flags); | 336 | spin_unlock_irqrestore(&uidhash_lock, flags); |
| 337 | 337 | ||
| 338 | INIT_WORK(&up->work, remove_user_sysfs_dir); | 338 | INIT_WORK(&up->work, cleanup_user_struct); |
| 339 | schedule_work(&up->work); | 339 | schedule_work(&up->work); |
| 340 | } | 340 | } |
| 341 | 341 | ||
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug index 1bcf9cd4baa0..c536b37a11cc 100644 --- a/lib/Kconfig.debug +++ b/lib/Kconfig.debug | |||
| @@ -402,7 +402,7 @@ config LOCKDEP | |||
| 402 | bool | 402 | bool |
| 403 | depends on DEBUG_KERNEL && TRACE_IRQFLAGS_SUPPORT && STACKTRACE_SUPPORT && LOCKDEP_SUPPORT | 403 | depends on DEBUG_KERNEL && TRACE_IRQFLAGS_SUPPORT && STACKTRACE_SUPPORT && LOCKDEP_SUPPORT |
| 404 | select STACKTRACE | 404 | select STACKTRACE |
| 405 | select FRAME_POINTER if !X86 && !MIPS && !PPC | 405 | select FRAME_POINTER if !X86 && !MIPS && !PPC && !ARM_UNWIND |
| 406 | select KALLSYMS | 406 | select KALLSYMS |
| 407 | select KALLSYMS_ALL | 407 | select KALLSYMS_ALL |
| 408 | 408 | ||
diff --git a/lib/bitmap.c b/lib/bitmap.c index 1338469ac849..35a1f7ff4149 100644 --- a/lib/bitmap.c +++ b/lib/bitmap.c | |||
| @@ -948,15 +948,15 @@ done: | |||
| 948 | */ | 948 | */ |
| 949 | int bitmap_find_free_region(unsigned long *bitmap, int bits, int order) | 949 | int bitmap_find_free_region(unsigned long *bitmap, int bits, int order) |
| 950 | { | 950 | { |
| 951 | int pos; /* scans bitmap by regions of size order */ | 951 | int pos, end; /* scans bitmap by regions of size order */ |
| 952 | 952 | ||
| 953 | for (pos = 0; pos < bits; pos += (1 << order)) | 953 | for (pos = 0 ; (end = pos + (1 << order)) <= bits; pos = end) { |
| 954 | if (__reg_op(bitmap, pos, order, REG_OP_ISFREE)) | 954 | if (!__reg_op(bitmap, pos, order, REG_OP_ISFREE)) |
| 955 | break; | 955 | continue; |
| 956 | if (pos == bits) | 956 | __reg_op(bitmap, pos, order, REG_OP_ALLOC); |
| 957 | return -ENOMEM; | 957 | return pos; |
| 958 | __reg_op(bitmap, pos, order, REG_OP_ALLOC); | 958 | } |
| 959 | return pos; | 959 | return -ENOMEM; |
| 960 | } | 960 | } |
| 961 | EXPORT_SYMBOL(bitmap_find_free_region); | 961 | EXPORT_SYMBOL(bitmap_find_free_region); |
| 962 | 962 | ||
| @@ -449,6 +449,7 @@ void idr_remove_all(struct idr *idp) | |||
| 449 | 449 | ||
| 450 | n = idp->layers * IDR_BITS; | 450 | n = idp->layers * IDR_BITS; |
| 451 | p = idp->top; | 451 | p = idp->top; |
| 452 | rcu_assign_pointer(idp->top, NULL); | ||
| 452 | max = 1 << n; | 453 | max = 1 << n; |
| 453 | 454 | ||
| 454 | id = 0; | 455 | id = 0; |
| @@ -467,7 +468,6 @@ void idr_remove_all(struct idr *idp) | |||
| 467 | p = *--paa; | 468 | p = *--paa; |
| 468 | } | 469 | } |
| 469 | } | 470 | } |
| 470 | rcu_assign_pointer(idp->top, NULL); | ||
| 471 | idp->layers = 0; | 471 | idp->layers = 0; |
| 472 | } | 472 | } |
| 473 | EXPORT_SYMBOL(idr_remove_all); | 473 | EXPORT_SYMBOL(idr_remove_all); |
diff --git a/mm/highmem.c b/mm/highmem.c index b36b83b920ff..910198037bf5 100644 --- a/mm/highmem.c +++ b/mm/highmem.c | |||
| @@ -67,6 +67,25 @@ pte_t * pkmap_page_table; | |||
| 67 | 67 | ||
| 68 | static DECLARE_WAIT_QUEUE_HEAD(pkmap_map_wait); | 68 | static DECLARE_WAIT_QUEUE_HEAD(pkmap_map_wait); |
| 69 | 69 | ||
| 70 | /* | ||
| 71 | * Most architectures have no use for kmap_high_get(), so let's abstract | ||
| 72 | * the disabling of IRQ out of the locking in that case to save on a | ||
| 73 | * potential useless overhead. | ||
| 74 | */ | ||
| 75 | #ifdef ARCH_NEEDS_KMAP_HIGH_GET | ||
| 76 | #define lock_kmap() spin_lock_irq(&kmap_lock) | ||
| 77 | #define unlock_kmap() spin_unlock_irq(&kmap_lock) | ||
| 78 | #define lock_kmap_any(flags) spin_lock_irqsave(&kmap_lock, flags) | ||
| 79 | #define unlock_kmap_any(flags) spin_unlock_irqrestore(&kmap_lock, flags) | ||
| 80 | #else | ||
| 81 | #define lock_kmap() spin_lock(&kmap_lock) | ||
| 82 | #define unlock_kmap() spin_unlock(&kmap_lock) | ||
| 83 | #define lock_kmap_any(flags) \ | ||
| 84 | do { spin_lock(&kmap_lock); (void)(flags); } while (0) | ||
| 85 | #define unlock_kmap_any(flags) \ | ||
| 86 | do { spin_unlock(&kmap_lock); (void)(flags); } while (0) | ||
| 87 | #endif | ||
| 88 | |||
| 70 | static void flush_all_zero_pkmaps(void) | 89 | static void flush_all_zero_pkmaps(void) |
| 71 | { | 90 | { |
| 72 | int i; | 91 | int i; |
| @@ -113,9 +132,9 @@ static void flush_all_zero_pkmaps(void) | |||
| 113 | */ | 132 | */ |
| 114 | void kmap_flush_unused(void) | 133 | void kmap_flush_unused(void) |
| 115 | { | 134 | { |
| 116 | spin_lock(&kmap_lock); | 135 | lock_kmap(); |
| 117 | flush_all_zero_pkmaps(); | 136 | flush_all_zero_pkmaps(); |
| 118 | spin_unlock(&kmap_lock); | 137 | unlock_kmap(); |
| 119 | } | 138 | } |
| 120 | 139 | ||
| 121 | static inline unsigned long map_new_virtual(struct page *page) | 140 | static inline unsigned long map_new_virtual(struct page *page) |
| @@ -145,10 +164,10 @@ start: | |||
| 145 | 164 | ||
| 146 | __set_current_state(TASK_UNINTERRUPTIBLE); | 165 | __set_current_state(TASK_UNINTERRUPTIBLE); |
| 147 | add_wait_queue(&pkmap_map_wait, &wait); | 166 | add_wait_queue(&pkmap_map_wait, &wait); |
| 148 | spin_unlock(&kmap_lock); | 167 | unlock_kmap(); |
| 149 | schedule(); | 168 | schedule(); |
| 150 | remove_wait_queue(&pkmap_map_wait, &wait); | 169 | remove_wait_queue(&pkmap_map_wait, &wait); |
| 151 | spin_lock(&kmap_lock); | 170 | lock_kmap(); |
| 152 | 171 | ||
| 153 | /* Somebody else might have mapped it while we slept */ | 172 | /* Somebody else might have mapped it while we slept */ |
| 154 | if (page_address(page)) | 173 | if (page_address(page)) |
| @@ -184,29 +203,59 @@ void *kmap_high(struct page *page) | |||
| 184 | * For highmem pages, we can't trust "virtual" until | 203 | * For highmem pages, we can't trust "virtual" until |
| 185 | * after we have the lock. | 204 | * after we have the lock. |
| 186 | */ | 205 | */ |
| 187 | spin_lock(&kmap_lock); | 206 | lock_kmap(); |
| 188 | vaddr = (unsigned long)page_address(page); | 207 | vaddr = (unsigned long)page_address(page); |
| 189 | if (!vaddr) | 208 | if (!vaddr) |
| 190 | vaddr = map_new_virtual(page); | 209 | vaddr = map_new_virtual(page); |
| 191 | pkmap_count[PKMAP_NR(vaddr)]++; | 210 | pkmap_count[PKMAP_NR(vaddr)]++; |
| 192 | BUG_ON(pkmap_count[PKMAP_NR(vaddr)] < 2); | 211 | BUG_ON(pkmap_count[PKMAP_NR(vaddr)] < 2); |
| 193 | spin_unlock(&kmap_lock); | 212 | unlock_kmap(); |
| 194 | return (void*) vaddr; | 213 | return (void*) vaddr; |
| 195 | } | 214 | } |
| 196 | 215 | ||
| 197 | EXPORT_SYMBOL(kmap_high); | 216 | EXPORT_SYMBOL(kmap_high); |
| 198 | 217 | ||
| 218 | #ifdef ARCH_NEEDS_KMAP_HIGH_GET | ||
| 219 | /** | ||
| 220 | * kmap_high_get - pin a highmem page into memory | ||
| 221 | * @page: &struct page to pin | ||
| 222 | * | ||
| 223 | * Returns the page's current virtual memory address, or NULL if no mapping | ||
| 224 | * exists. When and only when a non null address is returned then a | ||
| 225 | * matching call to kunmap_high() is necessary. | ||
| 226 | * | ||
| 227 | * This can be called from any context. | ||
| 228 | */ | ||
| 229 | void *kmap_high_get(struct page *page) | ||
| 230 | { | ||
| 231 | unsigned long vaddr, flags; | ||
| 232 | |||
| 233 | lock_kmap_any(flags); | ||
| 234 | vaddr = (unsigned long)page_address(page); | ||
| 235 | if (vaddr) { | ||
| 236 | BUG_ON(pkmap_count[PKMAP_NR(vaddr)] < 1); | ||
| 237 | pkmap_count[PKMAP_NR(vaddr)]++; | ||
| 238 | } | ||
| 239 | unlock_kmap_any(flags); | ||
| 240 | return (void*) vaddr; | ||
| 241 | } | ||
| 242 | #endif | ||
| 243 | |||
| 199 | /** | 244 | /** |
| 200 | * kunmap_high - map a highmem page into memory | 245 | * kunmap_high - map a highmem page into memory |
| 201 | * @page: &struct page to unmap | 246 | * @page: &struct page to unmap |
| 247 | * | ||
| 248 | * If ARCH_NEEDS_KMAP_HIGH_GET is not defined then this may be called | ||
| 249 | * only from user context. | ||
| 202 | */ | 250 | */ |
| 203 | void kunmap_high(struct page *page) | 251 | void kunmap_high(struct page *page) |
| 204 | { | 252 | { |
| 205 | unsigned long vaddr; | 253 | unsigned long vaddr; |
| 206 | unsigned long nr; | 254 | unsigned long nr; |
| 255 | unsigned long flags; | ||
| 207 | int need_wakeup; | 256 | int need_wakeup; |
| 208 | 257 | ||
| 209 | spin_lock(&kmap_lock); | 258 | lock_kmap_any(flags); |
| 210 | vaddr = (unsigned long)page_address(page); | 259 | vaddr = (unsigned long)page_address(page); |
| 211 | BUG_ON(!vaddr); | 260 | BUG_ON(!vaddr); |
| 212 | nr = PKMAP_NR(vaddr); | 261 | nr = PKMAP_NR(vaddr); |
| @@ -232,7 +281,7 @@ void kunmap_high(struct page *page) | |||
| 232 | */ | 281 | */ |
| 233 | need_wakeup = waitqueue_active(&pkmap_map_wait); | 282 | need_wakeup = waitqueue_active(&pkmap_map_wait); |
| 234 | } | 283 | } |
| 235 | spin_unlock(&kmap_lock); | 284 | unlock_kmap_any(flags); |
| 236 | 285 | ||
| 237 | /* do wake-up, if needed, race-free outside of the spin lock */ | 286 | /* do wake-up, if needed, race-free outside of the spin lock */ |
| 238 | if (need_wakeup) | 287 | if (need_wakeup) |
diff --git a/mm/vmscan.c b/mm/vmscan.c index 6177e3bcd66b..56ddf41149eb 100644 --- a/mm/vmscan.c +++ b/mm/vmscan.c | |||
| @@ -1262,7 +1262,6 @@ static void shrink_active_list(unsigned long nr_pages, struct zone *zone, | |||
| 1262 | * Move the pages to the [file or anon] inactive list. | 1262 | * Move the pages to the [file or anon] inactive list. |
| 1263 | */ | 1263 | */ |
| 1264 | pagevec_init(&pvec, 1); | 1264 | pagevec_init(&pvec, 1); |
| 1265 | pgmoved = 0; | ||
| 1266 | lru = LRU_BASE + file * LRU_FILE; | 1265 | lru = LRU_BASE + file * LRU_FILE; |
| 1267 | 1266 | ||
| 1268 | spin_lock_irq(&zone->lru_lock); | 1267 | spin_lock_irq(&zone->lru_lock); |
| @@ -1274,6 +1273,7 @@ static void shrink_active_list(unsigned long nr_pages, struct zone *zone, | |||
| 1274 | */ | 1273 | */ |
| 1275 | reclaim_stat->recent_rotated[!!file] += pgmoved; | 1274 | reclaim_stat->recent_rotated[!!file] += pgmoved; |
| 1276 | 1275 | ||
| 1276 | pgmoved = 0; | ||
| 1277 | while (!list_empty(&l_inactive)) { | 1277 | while (!list_empty(&l_inactive)) { |
| 1278 | page = lru_to_page(&l_inactive); | 1278 | page = lru_to_page(&l_inactive); |
| 1279 | prefetchw_prev_lru_page(page, &l_inactive, flags); | 1279 | prefetchw_prev_lru_page(page, &l_inactive, flags); |
| @@ -1469,7 +1469,7 @@ static void shrink_zone(int priority, struct zone *zone, | |||
| 1469 | int file = is_file_lru(l); | 1469 | int file = is_file_lru(l); |
| 1470 | int scan; | 1470 | int scan; |
| 1471 | 1471 | ||
| 1472 | scan = zone_page_state(zone, NR_LRU_BASE + l); | 1472 | scan = zone_nr_pages(zone, sc, l); |
| 1473 | if (priority) { | 1473 | if (priority) { |
| 1474 | scan >>= priority; | 1474 | scan >>= priority; |
| 1475 | scan = (scan * percent[file]) / 100; | 1475 | scan = (scan * percent[file]) / 100; |
diff --git a/net/802/tr.c b/net/802/tr.c index 158150fee462..f47ae289d83b 100644 --- a/net/802/tr.c +++ b/net/802/tr.c | |||
| @@ -668,3 +668,5 @@ module_init(rif_init); | |||
| 668 | 668 | ||
| 669 | EXPORT_SYMBOL(tr_type_trans); | 669 | EXPORT_SYMBOL(tr_type_trans); |
| 670 | EXPORT_SYMBOL(alloc_trdev); | 670 | EXPORT_SYMBOL(alloc_trdev); |
| 671 | |||
| 672 | MODULE_LICENSE("GPL"); | ||
diff --git a/net/8021q/vlan_dev.c b/net/8021q/vlan_dev.c index 4a19acd3a32b..1b34135cf990 100644 --- a/net/8021q/vlan_dev.c +++ b/net/8021q/vlan_dev.c | |||
| @@ -553,7 +553,7 @@ static int vlan_dev_neigh_setup(struct net_device *dev, struct neigh_parms *pa) | |||
| 553 | int err = 0; | 553 | int err = 0; |
| 554 | 554 | ||
| 555 | if (netif_device_present(real_dev) && ops->ndo_neigh_setup) | 555 | if (netif_device_present(real_dev) && ops->ndo_neigh_setup) |
| 556 | err = ops->ndo_neigh_setup(dev, pa); | 556 | err = ops->ndo_neigh_setup(real_dev, pa); |
| 557 | 557 | ||
| 558 | return err; | 558 | return err; |
| 559 | } | 559 | } |
| @@ -639,6 +639,7 @@ static int vlan_dev_init(struct net_device *dev) | |||
| 639 | dev->hard_header_len = real_dev->hard_header_len + VLAN_HLEN; | 639 | dev->hard_header_len = real_dev->hard_header_len + VLAN_HLEN; |
| 640 | dev->netdev_ops = &vlan_netdev_ops; | 640 | dev->netdev_ops = &vlan_netdev_ops; |
| 641 | } | 641 | } |
| 642 | netdev_resync_ops(dev); | ||
| 642 | 643 | ||
| 643 | if (is_vlan_dev(real_dev)) | 644 | if (is_vlan_dev(real_dev)) |
| 644 | subclass = 1; | 645 | subclass = 1; |
diff --git a/net/core/dev.c b/net/core/dev.c index 72b0d26fd46d..e3fe5c705606 100644 --- a/net/core/dev.c +++ b/net/core/dev.c | |||
| @@ -2267,12 +2267,6 @@ int netif_receive_skb(struct sk_buff *skb) | |||
| 2267 | 2267 | ||
| 2268 | rcu_read_lock(); | 2268 | rcu_read_lock(); |
| 2269 | 2269 | ||
| 2270 | /* Don't receive packets in an exiting network namespace */ | ||
| 2271 | if (!net_alive(dev_net(skb->dev))) { | ||
| 2272 | kfree_skb(skb); | ||
| 2273 | goto out; | ||
| 2274 | } | ||
| 2275 | |||
| 2276 | #ifdef CONFIG_NET_CLS_ACT | 2270 | #ifdef CONFIG_NET_CLS_ACT |
| 2277 | if (skb->tc_verd & TC_NCLS) { | 2271 | if (skb->tc_verd & TC_NCLS) { |
| 2278 | skb->tc_verd = CLR_TC_NCLS(skb->tc_verd); | 2272 | skb->tc_verd = CLR_TC_NCLS(skb->tc_verd); |
| @@ -2594,9 +2588,9 @@ static int process_backlog(struct napi_struct *napi, int quota) | |||
| 2594 | local_irq_disable(); | 2588 | local_irq_disable(); |
| 2595 | skb = __skb_dequeue(&queue->input_pkt_queue); | 2589 | skb = __skb_dequeue(&queue->input_pkt_queue); |
| 2596 | if (!skb) { | 2590 | if (!skb) { |
| 2597 | __napi_complete(napi); | ||
| 2598 | local_irq_enable(); | 2591 | local_irq_enable(); |
| 2599 | break; | 2592 | napi_complete(napi); |
| 2593 | goto out; | ||
| 2600 | } | 2594 | } |
| 2601 | local_irq_enable(); | 2595 | local_irq_enable(); |
| 2602 | 2596 | ||
| @@ -2605,6 +2599,7 @@ static int process_backlog(struct napi_struct *napi, int quota) | |||
| 2605 | 2599 | ||
| 2606 | napi_gro_flush(napi); | 2600 | napi_gro_flush(napi); |
| 2607 | 2601 | ||
| 2602 | out: | ||
| 2608 | return work; | 2603 | return work; |
| 2609 | } | 2604 | } |
| 2610 | 2605 | ||
| @@ -2677,7 +2672,7 @@ void netif_napi_del(struct napi_struct *napi) | |||
| 2677 | struct sk_buff *skb, *next; | 2672 | struct sk_buff *skb, *next; |
| 2678 | 2673 | ||
| 2679 | list_del_init(&napi->dev_list); | 2674 | list_del_init(&napi->dev_list); |
| 2680 | kfree(napi->skb); | 2675 | kfree_skb(napi->skb); |
| 2681 | 2676 | ||
| 2682 | for (skb = napi->gro_list; skb; skb = next) { | 2677 | for (skb = napi->gro_list; skb; skb = next) { |
| 2683 | next = skb->next; | 2678 | next = skb->next; |
| @@ -4288,6 +4283,39 @@ unsigned long netdev_fix_features(unsigned long features, const char *name) | |||
| 4288 | } | 4283 | } |
| 4289 | EXPORT_SYMBOL(netdev_fix_features); | 4284 | EXPORT_SYMBOL(netdev_fix_features); |
| 4290 | 4285 | ||
| 4286 | /* Some devices need to (re-)set their netdev_ops inside | ||
| 4287 | * ->init() or similar. If that happens, we have to setup | ||
| 4288 | * the compat pointers again. | ||
| 4289 | */ | ||
| 4290 | void netdev_resync_ops(struct net_device *dev) | ||
| 4291 | { | ||
| 4292 | #ifdef CONFIG_COMPAT_NET_DEV_OPS | ||
| 4293 | const struct net_device_ops *ops = dev->netdev_ops; | ||
| 4294 | |||
| 4295 | dev->init = ops->ndo_init; | ||
| 4296 | dev->uninit = ops->ndo_uninit; | ||
| 4297 | dev->open = ops->ndo_open; | ||
| 4298 | dev->change_rx_flags = ops->ndo_change_rx_flags; | ||
| 4299 | dev->set_rx_mode = ops->ndo_set_rx_mode; | ||
| 4300 | dev->set_multicast_list = ops->ndo_set_multicast_list; | ||
| 4301 | dev->set_mac_address = ops->ndo_set_mac_address; | ||
| 4302 | dev->validate_addr = ops->ndo_validate_addr; | ||
| 4303 | dev->do_ioctl = ops->ndo_do_ioctl; | ||
| 4304 | dev->set_config = ops->ndo_set_config; | ||
| 4305 | dev->change_mtu = ops->ndo_change_mtu; | ||
| 4306 | dev->neigh_setup = ops->ndo_neigh_setup; | ||
| 4307 | dev->tx_timeout = ops->ndo_tx_timeout; | ||
| 4308 | dev->get_stats = ops->ndo_get_stats; | ||
| 4309 | dev->vlan_rx_register = ops->ndo_vlan_rx_register; | ||
| 4310 | dev->vlan_rx_add_vid = ops->ndo_vlan_rx_add_vid; | ||
| 4311 | dev->vlan_rx_kill_vid = ops->ndo_vlan_rx_kill_vid; | ||
| 4312 | #ifdef CONFIG_NET_POLL_CONTROLLER | ||
| 4313 | dev->poll_controller = ops->ndo_poll_controller; | ||
| 4314 | #endif | ||
| 4315 | #endif | ||
| 4316 | } | ||
| 4317 | EXPORT_SYMBOL(netdev_resync_ops); | ||
| 4318 | |||
| 4291 | /** | 4319 | /** |
| 4292 | * register_netdevice - register a network device | 4320 | * register_netdevice - register a network device |
| 4293 | * @dev: device to register | 4321 | * @dev: device to register |
| @@ -4332,27 +4360,7 @@ int register_netdevice(struct net_device *dev) | |||
| 4332 | * This is temporary until all network devices are converted. | 4360 | * This is temporary until all network devices are converted. |
| 4333 | */ | 4361 | */ |
| 4334 | if (dev->netdev_ops) { | 4362 | if (dev->netdev_ops) { |
| 4335 | const struct net_device_ops *ops = dev->netdev_ops; | 4363 | netdev_resync_ops(dev); |
| 4336 | |||
| 4337 | dev->init = ops->ndo_init; | ||
| 4338 | dev->uninit = ops->ndo_uninit; | ||
| 4339 | dev->open = ops->ndo_open; | ||
| 4340 | dev->change_rx_flags = ops->ndo_change_rx_flags; | ||
| 4341 | dev->set_rx_mode = ops->ndo_set_rx_mode; | ||
| 4342 | dev->set_multicast_list = ops->ndo_set_multicast_list; | ||
| 4343 | dev->set_mac_address = ops->ndo_set_mac_address; | ||
| 4344 | dev->validate_addr = ops->ndo_validate_addr; | ||
| 4345 | dev->do_ioctl = ops->ndo_do_ioctl; | ||
| 4346 | dev->set_config = ops->ndo_set_config; | ||
| 4347 | dev->change_mtu = ops->ndo_change_mtu; | ||
| 4348 | dev->tx_timeout = ops->ndo_tx_timeout; | ||
| 4349 | dev->get_stats = ops->ndo_get_stats; | ||
| 4350 | dev->vlan_rx_register = ops->ndo_vlan_rx_register; | ||
| 4351 | dev->vlan_rx_add_vid = ops->ndo_vlan_rx_add_vid; | ||
| 4352 | dev->vlan_rx_kill_vid = ops->ndo_vlan_rx_kill_vid; | ||
| 4353 | #ifdef CONFIG_NET_POLL_CONTROLLER | ||
| 4354 | dev->poll_controller = ops->ndo_poll_controller; | ||
| 4355 | #endif | ||
| 4356 | } else { | 4364 | } else { |
| 4357 | char drivername[64]; | 4365 | char drivername[64]; |
| 4358 | pr_info("%s (%s): not using net_device_ops yet\n", | 4366 | pr_info("%s (%s): not using net_device_ops yet\n", |
diff --git a/net/core/net-sysfs.c b/net/core/net-sysfs.c index 6ac29a46e23e..484f58750eba 100644 --- a/net/core/net-sysfs.c +++ b/net/core/net-sysfs.c | |||
| @@ -77,7 +77,9 @@ static ssize_t netdev_store(struct device *dev, struct device_attribute *attr, | |||
| 77 | if (endp == buf) | 77 | if (endp == buf) |
| 78 | goto err; | 78 | goto err; |
| 79 | 79 | ||
| 80 | rtnl_lock(); | 80 | if (!rtnl_trylock()) |
| 81 | return -ERESTARTSYS; | ||
| 82 | |||
| 81 | if (dev_isalive(net)) { | 83 | if (dev_isalive(net)) { |
| 82 | if ((ret = (*set)(net, new)) == 0) | 84 | if ((ret = (*set)(net, new)) == 0) |
| 83 | ret = len; | 85 | ret = len; |
diff --git a/net/core/net_namespace.c b/net/core/net_namespace.c index 2adb1a7d361f..e3bebd36f053 100644 --- a/net/core/net_namespace.c +++ b/net/core/net_namespace.c | |||
| @@ -157,9 +157,6 @@ static void cleanup_net(struct work_struct *work) | |||
| 157 | struct pernet_operations *ops; | 157 | struct pernet_operations *ops; |
| 158 | struct net *net; | 158 | struct net *net; |
| 159 | 159 | ||
| 160 | /* Be very certain incoming network packets will not find us */ | ||
| 161 | rcu_barrier(); | ||
| 162 | |||
| 163 | net = container_of(work, struct net, work); | 160 | net = container_of(work, struct net, work); |
| 164 | 161 | ||
| 165 | mutex_lock(&net_mutex); | 162 | mutex_lock(&net_mutex); |
diff --git a/net/ipv4/icmp.c b/net/ipv4/icmp.c index 705b33b184a3..fc562d29cc46 100644 --- a/net/ipv4/icmp.c +++ b/net/ipv4/icmp.c | |||
| @@ -1205,7 +1205,7 @@ static struct pernet_operations __net_initdata icmp_sk_ops = { | |||
| 1205 | 1205 | ||
| 1206 | int __init icmp_init(void) | 1206 | int __init icmp_init(void) |
| 1207 | { | 1207 | { |
| 1208 | return register_pernet_device(&icmp_sk_ops); | 1208 | return register_pernet_subsys(&icmp_sk_ops); |
| 1209 | } | 1209 | } |
| 1210 | 1210 | ||
| 1211 | EXPORT_SYMBOL(icmp_err_convert); | 1211 | EXPORT_SYMBOL(icmp_err_convert); |
diff --git a/net/ipv4/ip_fragment.c b/net/ipv4/ip_fragment.c index 6659ac000eeb..7985346653bd 100644 --- a/net/ipv4/ip_fragment.c +++ b/net/ipv4/ip_fragment.c | |||
| @@ -463,6 +463,7 @@ err: | |||
| 463 | static int ip_frag_reasm(struct ipq *qp, struct sk_buff *prev, | 463 | static int ip_frag_reasm(struct ipq *qp, struct sk_buff *prev, |
| 464 | struct net_device *dev) | 464 | struct net_device *dev) |
| 465 | { | 465 | { |
| 466 | struct net *net = container_of(qp->q.net, struct net, ipv4.frags); | ||
| 466 | struct iphdr *iph; | 467 | struct iphdr *iph; |
| 467 | struct sk_buff *fp, *head = qp->q.fragments; | 468 | struct sk_buff *fp, *head = qp->q.fragments; |
| 468 | int len; | 469 | int len; |
| @@ -548,7 +549,7 @@ static int ip_frag_reasm(struct ipq *qp, struct sk_buff *prev, | |||
| 548 | iph = ip_hdr(head); | 549 | iph = ip_hdr(head); |
| 549 | iph->frag_off = 0; | 550 | iph->frag_off = 0; |
| 550 | iph->tot_len = htons(len); | 551 | iph->tot_len = htons(len); |
| 551 | IP_INC_STATS_BH(dev_net(dev), IPSTATS_MIB_REASMOKS); | 552 | IP_INC_STATS_BH(net, IPSTATS_MIB_REASMOKS); |
| 552 | qp->q.fragments = NULL; | 553 | qp->q.fragments = NULL; |
| 553 | return 0; | 554 | return 0; |
| 554 | 555 | ||
diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c index 19d7b429a262..cf74c416831a 100644 --- a/net/ipv4/tcp_ipv4.c +++ b/net/ipv4/tcp_ipv4.c | |||
| @@ -2443,7 +2443,7 @@ static struct pernet_operations __net_initdata tcp_sk_ops = { | |||
| 2443 | void __init tcp_v4_init(void) | 2443 | void __init tcp_v4_init(void) |
| 2444 | { | 2444 | { |
| 2445 | inet_hashinfo_init(&tcp_hashinfo); | 2445 | inet_hashinfo_init(&tcp_hashinfo); |
| 2446 | if (register_pernet_device(&tcp_sk_ops)) | 2446 | if (register_pernet_subsys(&tcp_sk_ops)) |
| 2447 | panic("Failed to create the TCP control socket.\n"); | 2447 | panic("Failed to create the TCP control socket.\n"); |
| 2448 | } | 2448 | } |
| 2449 | 2449 | ||
diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c index f9afb452249c..1220e2c7831e 100644 --- a/net/ipv6/addrconf.c +++ b/net/ipv6/addrconf.c | |||
| @@ -493,15 +493,17 @@ static void addrconf_forward_change(struct net *net, __s32 newf) | |||
| 493 | read_unlock(&dev_base_lock); | 493 | read_unlock(&dev_base_lock); |
| 494 | } | 494 | } |
| 495 | 495 | ||
| 496 | static void addrconf_fixup_forwarding(struct ctl_table *table, int *p, int old) | 496 | static int addrconf_fixup_forwarding(struct ctl_table *table, int *p, int old) |
| 497 | { | 497 | { |
| 498 | struct net *net; | 498 | struct net *net; |
| 499 | 499 | ||
| 500 | net = (struct net *)table->extra2; | 500 | net = (struct net *)table->extra2; |
| 501 | if (p == &net->ipv6.devconf_dflt->forwarding) | 501 | if (p == &net->ipv6.devconf_dflt->forwarding) |
| 502 | return; | 502 | return 0; |
| 503 | |||
| 504 | if (!rtnl_trylock()) | ||
| 505 | return -ERESTARTSYS; | ||
| 503 | 506 | ||
| 504 | rtnl_lock(); | ||
| 505 | if (p == &net->ipv6.devconf_all->forwarding) { | 507 | if (p == &net->ipv6.devconf_all->forwarding) { |
| 506 | __s32 newf = net->ipv6.devconf_all->forwarding; | 508 | __s32 newf = net->ipv6.devconf_all->forwarding; |
| 507 | net->ipv6.devconf_dflt->forwarding = newf; | 509 | net->ipv6.devconf_dflt->forwarding = newf; |
| @@ -512,6 +514,7 @@ static void addrconf_fixup_forwarding(struct ctl_table *table, int *p, int old) | |||
| 512 | 514 | ||
| 513 | if (*p) | 515 | if (*p) |
| 514 | rt6_purge_dflt_routers(net); | 516 | rt6_purge_dflt_routers(net); |
| 517 | return 1; | ||
| 515 | } | 518 | } |
| 516 | #endif | 519 | #endif |
| 517 | 520 | ||
| @@ -2608,9 +2611,6 @@ static int addrconf_ifdown(struct net_device *dev, int how) | |||
| 2608 | 2611 | ||
| 2609 | ASSERT_RTNL(); | 2612 | ASSERT_RTNL(); |
| 2610 | 2613 | ||
| 2611 | if ((dev->flags & IFF_LOOPBACK) && how == 1) | ||
| 2612 | how = 0; | ||
| 2613 | |||
| 2614 | rt6_ifdown(net, dev); | 2614 | rt6_ifdown(net, dev); |
| 2615 | neigh_ifdown(&nd_tbl, dev); | 2615 | neigh_ifdown(&nd_tbl, dev); |
| 2616 | 2616 | ||
| @@ -3983,7 +3983,7 @@ int addrconf_sysctl_forward(ctl_table *ctl, int write, struct file * filp, | |||
| 3983 | ret = proc_dointvec(ctl, write, filp, buffer, lenp, ppos); | 3983 | ret = proc_dointvec(ctl, write, filp, buffer, lenp, ppos); |
| 3984 | 3984 | ||
| 3985 | if (write) | 3985 | if (write) |
| 3986 | addrconf_fixup_forwarding(ctl, valp, val); | 3986 | ret = addrconf_fixup_forwarding(ctl, valp, val); |
| 3987 | return ret; | 3987 | return ret; |
| 3988 | } | 3988 | } |
| 3989 | 3989 | ||
| @@ -4019,8 +4019,7 @@ static int addrconf_sysctl_forward_strategy(ctl_table *table, | |||
| 4019 | } | 4019 | } |
| 4020 | 4020 | ||
| 4021 | *valp = new; | 4021 | *valp = new; |
| 4022 | addrconf_fixup_forwarding(table, valp, val); | 4022 | return addrconf_fixup_forwarding(table, valp, val); |
| 4023 | return 1; | ||
| 4024 | } | 4023 | } |
| 4025 | 4024 | ||
| 4026 | static struct addrconf_sysctl_table | 4025 | static struct addrconf_sysctl_table |
| @@ -4446,25 +4445,6 @@ int unregister_inet6addr_notifier(struct notifier_block *nb) | |||
| 4446 | 4445 | ||
| 4447 | EXPORT_SYMBOL(unregister_inet6addr_notifier); | 4446 | EXPORT_SYMBOL(unregister_inet6addr_notifier); |
| 4448 | 4447 | ||
| 4449 | static void addrconf_net_exit(struct net *net) | ||
| 4450 | { | ||
| 4451 | struct net_device *dev; | ||
| 4452 | |||
| 4453 | rtnl_lock(); | ||
| 4454 | /* clean dev list */ | ||
| 4455 | for_each_netdev(net, dev) { | ||
| 4456 | if (__in6_dev_get(dev) == NULL) | ||
| 4457 | continue; | ||
| 4458 | addrconf_ifdown(dev, 1); | ||
| 4459 | } | ||
| 4460 | addrconf_ifdown(net->loopback_dev, 2); | ||
| 4461 | rtnl_unlock(); | ||
| 4462 | } | ||
| 4463 | |||
| 4464 | static struct pernet_operations addrconf_net_ops = { | ||
| 4465 | .exit = addrconf_net_exit, | ||
| 4466 | }; | ||
| 4467 | |||
| 4468 | /* | 4448 | /* |
| 4469 | * Init / cleanup code | 4449 | * Init / cleanup code |
| 4470 | */ | 4450 | */ |
| @@ -4506,10 +4486,6 @@ int __init addrconf_init(void) | |||
| 4506 | if (err) | 4486 | if (err) |
| 4507 | goto errlo; | 4487 | goto errlo; |
| 4508 | 4488 | ||
| 4509 | err = register_pernet_device(&addrconf_net_ops); | ||
| 4510 | if (err) | ||
| 4511 | return err; | ||
| 4512 | |||
| 4513 | register_netdevice_notifier(&ipv6_dev_notf); | 4489 | register_netdevice_notifier(&ipv6_dev_notf); |
| 4514 | 4490 | ||
| 4515 | addrconf_verify(0); | 4491 | addrconf_verify(0); |
| @@ -4539,15 +4515,22 @@ errlo: | |||
| 4539 | void addrconf_cleanup(void) | 4515 | void addrconf_cleanup(void) |
| 4540 | { | 4516 | { |
| 4541 | struct inet6_ifaddr *ifa; | 4517 | struct inet6_ifaddr *ifa; |
| 4518 | struct net_device *dev; | ||
| 4542 | int i; | 4519 | int i; |
| 4543 | 4520 | ||
| 4544 | unregister_netdevice_notifier(&ipv6_dev_notf); | 4521 | unregister_netdevice_notifier(&ipv6_dev_notf); |
| 4545 | unregister_pernet_device(&addrconf_net_ops); | ||
| 4546 | |||
| 4547 | unregister_pernet_subsys(&addrconf_ops); | 4522 | unregister_pernet_subsys(&addrconf_ops); |
| 4548 | 4523 | ||
| 4549 | rtnl_lock(); | 4524 | rtnl_lock(); |
| 4550 | 4525 | ||
| 4526 | /* clean dev list */ | ||
| 4527 | for_each_netdev(&init_net, dev) { | ||
| 4528 | if (__in6_dev_get(dev) == NULL) | ||
| 4529 | continue; | ||
| 4530 | addrconf_ifdown(dev, 1); | ||
| 4531 | } | ||
| 4532 | addrconf_ifdown(init_net.loopback_dev, 2); | ||
| 4533 | |||
| 4551 | /* | 4534 | /* |
| 4552 | * Check hash table. | 4535 | * Check hash table. |
| 4553 | */ | 4536 | */ |
| @@ -4568,6 +4551,4 @@ void addrconf_cleanup(void) | |||
| 4568 | 4551 | ||
| 4569 | del_timer(&addr_chk_timer); | 4552 | del_timer(&addr_chk_timer); |
| 4570 | rtnl_unlock(); | 4553 | rtnl_unlock(); |
| 4571 | |||
| 4572 | unregister_pernet_subsys(&addrconf_net_ops); | ||
| 4573 | } | 4554 | } |
diff --git a/net/ipv6/af_inet6.c b/net/ipv6/af_inet6.c index c802bc1658a8..9c8309ed35cf 100644 --- a/net/ipv6/af_inet6.c +++ b/net/ipv6/af_inet6.c | |||
| @@ -72,6 +72,10 @@ MODULE_LICENSE("GPL"); | |||
| 72 | static struct list_head inetsw6[SOCK_MAX]; | 72 | static struct list_head inetsw6[SOCK_MAX]; |
| 73 | static DEFINE_SPINLOCK(inetsw6_lock); | 73 | static DEFINE_SPINLOCK(inetsw6_lock); |
| 74 | 74 | ||
| 75 | static int disable_ipv6 = 0; | ||
| 76 | module_param_named(disable, disable_ipv6, int, 0); | ||
| 77 | MODULE_PARM_DESC(disable, "Disable IPv6 such that it is non-functional"); | ||
| 78 | |||
| 75 | static __inline__ struct ipv6_pinfo *inet6_sk_generic(struct sock *sk) | 79 | static __inline__ struct ipv6_pinfo *inet6_sk_generic(struct sock *sk) |
| 76 | { | 80 | { |
| 77 | const int offset = sk->sk_prot->obj_size - sizeof(struct ipv6_pinfo); | 81 | const int offset = sk->sk_prot->obj_size - sizeof(struct ipv6_pinfo); |
| @@ -991,10 +995,21 @@ static int __init inet6_init(void) | |||
| 991 | { | 995 | { |
| 992 | struct sk_buff *dummy_skb; | 996 | struct sk_buff *dummy_skb; |
| 993 | struct list_head *r; | 997 | struct list_head *r; |
| 994 | int err; | 998 | int err = 0; |
| 995 | 999 | ||
| 996 | BUILD_BUG_ON(sizeof(struct inet6_skb_parm) > sizeof(dummy_skb->cb)); | 1000 | BUILD_BUG_ON(sizeof(struct inet6_skb_parm) > sizeof(dummy_skb->cb)); |
| 997 | 1001 | ||
| 1002 | /* Register the socket-side information for inet6_create. */ | ||
| 1003 | for(r = &inetsw6[0]; r < &inetsw6[SOCK_MAX]; ++r) | ||
| 1004 | INIT_LIST_HEAD(r); | ||
| 1005 | |||
| 1006 | if (disable_ipv6) { | ||
| 1007 | printk(KERN_INFO | ||
| 1008 | "IPv6: Loaded, but administratively disabled, " | ||
| 1009 | "reboot required to enable\n"); | ||
| 1010 | goto out; | ||
| 1011 | } | ||
| 1012 | |||
| 998 | err = proto_register(&tcpv6_prot, 1); | 1013 | err = proto_register(&tcpv6_prot, 1); |
| 999 | if (err) | 1014 | if (err) |
| 1000 | goto out; | 1015 | goto out; |
| @@ -1012,10 +1027,6 @@ static int __init inet6_init(void) | |||
| 1012 | goto out_unregister_udplite_proto; | 1027 | goto out_unregister_udplite_proto; |
| 1013 | 1028 | ||
| 1014 | 1029 | ||
| 1015 | /* Register the socket-side information for inet6_create. */ | ||
| 1016 | for(r = &inetsw6[0]; r < &inetsw6[SOCK_MAX]; ++r) | ||
| 1017 | INIT_LIST_HEAD(r); | ||
| 1018 | |||
| 1019 | /* We MUST register RAW sockets before we create the ICMP6, | 1030 | /* We MUST register RAW sockets before we create the ICMP6, |
| 1020 | * IGMP6, or NDISC control sockets. | 1031 | * IGMP6, or NDISC control sockets. |
| 1021 | */ | 1032 | */ |
| @@ -1181,6 +1192,9 @@ module_init(inet6_init); | |||
| 1181 | 1192 | ||
| 1182 | static void __exit inet6_exit(void) | 1193 | static void __exit inet6_exit(void) |
| 1183 | { | 1194 | { |
| 1195 | if (disable_ipv6) | ||
| 1196 | return; | ||
| 1197 | |||
| 1184 | /* First of all disallow new sockets creation. */ | 1198 | /* First of all disallow new sockets creation. */ |
| 1185 | sock_unregister(PF_INET6); | 1199 | sock_unregister(PF_INET6); |
| 1186 | /* Disallow any further netlink messages */ | 1200 | /* Disallow any further netlink messages */ |
diff --git a/net/ipv6/netfilter/nf_conntrack_reasm.c b/net/ipv6/netfilter/nf_conntrack_reasm.c index ed4d79a9e4a6..058a5e4a60c3 100644 --- a/net/ipv6/netfilter/nf_conntrack_reasm.c +++ b/net/ipv6/netfilter/nf_conntrack_reasm.c | |||
| @@ -528,14 +528,14 @@ find_prev_fhdr(struct sk_buff *skb, u8 *prevhdrp, int *prevhoff, int *fhoff) | |||
| 528 | if (!ipv6_ext_hdr(nexthdr)) { | 528 | if (!ipv6_ext_hdr(nexthdr)) { |
| 529 | return -1; | 529 | return -1; |
| 530 | } | 530 | } |
| 531 | if (len < (int)sizeof(struct ipv6_opt_hdr)) { | ||
| 532 | pr_debug("too short\n"); | ||
| 533 | return -1; | ||
| 534 | } | ||
| 535 | if (nexthdr == NEXTHDR_NONE) { | 531 | if (nexthdr == NEXTHDR_NONE) { |
| 536 | pr_debug("next header is none\n"); | 532 | pr_debug("next header is none\n"); |
| 537 | return -1; | 533 | return -1; |
| 538 | } | 534 | } |
| 535 | if (len < (int)sizeof(struct ipv6_opt_hdr)) { | ||
| 536 | pr_debug("too short\n"); | ||
| 537 | return -1; | ||
| 538 | } | ||
| 539 | if (skb_copy_bits(skb, start, &hdr, sizeof(hdr))) | 539 | if (skb_copy_bits(skb, start, &hdr, sizeof(hdr))) |
| 540 | BUG(); | 540 | BUG(); |
| 541 | if (nexthdr == NEXTHDR_AUTH) | 541 | if (nexthdr == NEXTHDR_AUTH) |
diff --git a/net/ipv6/reassembly.c b/net/ipv6/reassembly.c index 3c575118fca5..e9ac7a12f595 100644 --- a/net/ipv6/reassembly.c +++ b/net/ipv6/reassembly.c | |||
| @@ -452,6 +452,7 @@ err: | |||
| 452 | static int ip6_frag_reasm(struct frag_queue *fq, struct sk_buff *prev, | 452 | static int ip6_frag_reasm(struct frag_queue *fq, struct sk_buff *prev, |
| 453 | struct net_device *dev) | 453 | struct net_device *dev) |
| 454 | { | 454 | { |
| 455 | struct net *net = container_of(fq->q.net, struct net, ipv6.frags); | ||
| 455 | struct sk_buff *fp, *head = fq->q.fragments; | 456 | struct sk_buff *fp, *head = fq->q.fragments; |
| 456 | int payload_len; | 457 | int payload_len; |
| 457 | unsigned int nhoff; | 458 | unsigned int nhoff; |
| @@ -551,8 +552,7 @@ static int ip6_frag_reasm(struct frag_queue *fq, struct sk_buff *prev, | |||
| 551 | head->csum); | 552 | head->csum); |
| 552 | 553 | ||
| 553 | rcu_read_lock(); | 554 | rcu_read_lock(); |
| 554 | IP6_INC_STATS_BH(dev_net(dev), | 555 | IP6_INC_STATS_BH(net, __in6_dev_get(dev), IPSTATS_MIB_REASMOKS); |
| 555 | __in6_dev_get(dev), IPSTATS_MIB_REASMOKS); | ||
| 556 | rcu_read_unlock(); | 556 | rcu_read_unlock(); |
| 557 | fq->q.fragments = NULL; | 557 | fq->q.fragments = NULL; |
| 558 | return 1; | 558 | return 1; |
| @@ -566,8 +566,7 @@ out_oom: | |||
| 566 | printk(KERN_DEBUG "ip6_frag_reasm: no memory for reassembly\n"); | 566 | printk(KERN_DEBUG "ip6_frag_reasm: no memory for reassembly\n"); |
| 567 | out_fail: | 567 | out_fail: |
| 568 | rcu_read_lock(); | 568 | rcu_read_lock(); |
| 569 | IP6_INC_STATS_BH(dev_net(dev), | 569 | IP6_INC_STATS_BH(net, __in6_dev_get(dev), IPSTATS_MIB_REASMFAILS); |
| 570 | __in6_dev_get(dev), IPSTATS_MIB_REASMFAILS); | ||
| 571 | rcu_read_unlock(); | 570 | rcu_read_unlock(); |
| 572 | return -1; | 571 | return -1; |
| 573 | } | 572 | } |
diff --git a/net/ipv6/sit.c b/net/ipv6/sit.c index d3467e563f02..5cee2bcbcece 100644 --- a/net/ipv6/sit.c +++ b/net/ipv6/sit.c | |||
| @@ -188,9 +188,9 @@ static struct ip_tunnel * ipip6_tunnel_locate(struct net *net, | |||
| 188 | } | 188 | } |
| 189 | 189 | ||
| 190 | nt = netdev_priv(dev); | 190 | nt = netdev_priv(dev); |
| 191 | ipip6_tunnel_init(dev); | ||
| 192 | 191 | ||
| 193 | nt->parms = *parms; | 192 | nt->parms = *parms; |
| 193 | ipip6_tunnel_init(dev); | ||
| 194 | 194 | ||
| 195 | if (parms->i_flags & SIT_ISATAP) | 195 | if (parms->i_flags & SIT_ISATAP) |
| 196 | dev->priv_flags |= IFF_ISATAP; | 196 | dev->priv_flags |= IFF_ISATAP; |
diff --git a/net/mac80211/tx.c b/net/mac80211/tx.c index 94de5033f0b6..37e3d5ef7e3f 100644 --- a/net/mac80211/tx.c +++ b/net/mac80211/tx.c | |||
| @@ -752,6 +752,8 @@ ieee80211_tx_h_fragment(struct ieee80211_tx_data *tx) | |||
| 752 | skb_copy_queue_mapping(frag, first); | 752 | skb_copy_queue_mapping(frag, first); |
| 753 | 753 | ||
| 754 | frag->do_not_encrypt = first->do_not_encrypt; | 754 | frag->do_not_encrypt = first->do_not_encrypt; |
| 755 | frag->dev = first->dev; | ||
| 756 | frag->iif = first->iif; | ||
| 755 | 757 | ||
| 756 | pos += copylen; | 758 | pos += copylen; |
| 757 | left -= copylen; | 759 | left -= copylen; |
diff --git a/net/netfilter/nf_conntrack_core.c b/net/netfilter/nf_conntrack_core.c index 90ce9ddb9451..f4935e344b61 100644 --- a/net/netfilter/nf_conntrack_core.c +++ b/net/netfilter/nf_conntrack_core.c | |||
| @@ -726,7 +726,7 @@ nf_conntrack_in(struct net *net, u_int8_t pf, unsigned int hooknum, | |||
| 726 | NF_CT_ASSERT(skb->nfct); | 726 | NF_CT_ASSERT(skb->nfct); |
| 727 | 727 | ||
| 728 | ret = l4proto->packet(ct, skb, dataoff, ctinfo, pf, hooknum); | 728 | ret = l4proto->packet(ct, skb, dataoff, ctinfo, pf, hooknum); |
| 729 | if (ret < 0) { | 729 | if (ret <= 0) { |
| 730 | /* Invalid: inverse of the return code tells | 730 | /* Invalid: inverse of the return code tells |
| 731 | * the netfilter core what to do */ | 731 | * the netfilter core what to do */ |
| 732 | pr_debug("nf_conntrack_in: Can't track with proto module\n"); | 732 | pr_debug("nf_conntrack_in: Can't track with proto module\n"); |
diff --git a/net/netfilter/nf_conntrack_netlink.c b/net/netfilter/nf_conntrack_netlink.c index cb78aa00399e..ed6d873ad384 100644 --- a/net/netfilter/nf_conntrack_netlink.c +++ b/net/netfilter/nf_conntrack_netlink.c | |||
| @@ -1780,6 +1780,7 @@ ctnetlink_create_expect(struct nlattr *cda[], u_int8_t u3, u32 pid, int report) | |||
| 1780 | goto out; | 1780 | goto out; |
| 1781 | } | 1781 | } |
| 1782 | 1782 | ||
| 1783 | exp->class = 0; | ||
| 1783 | exp->expectfn = NULL; | 1784 | exp->expectfn = NULL; |
| 1784 | exp->flags = 0; | 1785 | exp->flags = 0; |
| 1785 | exp->master = ct; | 1786 | exp->master = ct; |
diff --git a/net/netfilter/nf_conntrack_proto_tcp.c b/net/netfilter/nf_conntrack_proto_tcp.c index a1edb9c1adee..f3fd154d1ddd 100644 --- a/net/netfilter/nf_conntrack_proto_tcp.c +++ b/net/netfilter/nf_conntrack_proto_tcp.c | |||
| @@ -859,7 +859,7 @@ static int tcp_packet(struct nf_conn *ct, | |||
| 859 | */ | 859 | */ |
| 860 | if (nf_ct_kill(ct)) | 860 | if (nf_ct_kill(ct)) |
| 861 | return -NF_REPEAT; | 861 | return -NF_REPEAT; |
| 862 | return -NF_DROP; | 862 | return NF_DROP; |
| 863 | } | 863 | } |
| 864 | /* Fall through */ | 864 | /* Fall through */ |
| 865 | case TCP_CONNTRACK_IGNORE: | 865 | case TCP_CONNTRACK_IGNORE: |
| @@ -892,7 +892,7 @@ static int tcp_packet(struct nf_conn *ct, | |||
| 892 | nf_log_packet(pf, 0, skb, NULL, NULL, NULL, | 892 | nf_log_packet(pf, 0, skb, NULL, NULL, NULL, |
| 893 | "nf_ct_tcp: killing out of sync session "); | 893 | "nf_ct_tcp: killing out of sync session "); |
| 894 | nf_ct_kill(ct); | 894 | nf_ct_kill(ct); |
| 895 | return -NF_DROP; | 895 | return NF_DROP; |
| 896 | } | 896 | } |
| 897 | ct->proto.tcp.last_index = index; | 897 | ct->proto.tcp.last_index = index; |
| 898 | ct->proto.tcp.last_dir = dir; | 898 | ct->proto.tcp.last_dir = dir; |
diff --git a/net/netlink/af_netlink.c b/net/netlink/af_netlink.c index 9eb895c7a2a9..3ae3cb816563 100644 --- a/net/netlink/af_netlink.c +++ b/net/netlink/af_netlink.c | |||
| @@ -1084,6 +1084,13 @@ out: | |||
| 1084 | return 0; | 1084 | return 0; |
| 1085 | } | 1085 | } |
| 1086 | 1086 | ||
| 1087 | /** | ||
| 1088 | * netlink_set_err - report error to broadcast listeners | ||
| 1089 | * @ssk: the kernel netlink socket, as returned by netlink_kernel_create() | ||
| 1090 | * @pid: the PID of a process that we want to skip (if any) | ||
| 1091 | * @groups: the broadcast group that will notice the error | ||
| 1092 | * @code: error code, must be negative (as usual in kernelspace) | ||
| 1093 | */ | ||
| 1087 | void netlink_set_err(struct sock *ssk, u32 pid, u32 group, int code) | 1094 | void netlink_set_err(struct sock *ssk, u32 pid, u32 group, int code) |
| 1088 | { | 1095 | { |
| 1089 | struct netlink_set_err_data info; | 1096 | struct netlink_set_err_data info; |
| @@ -1093,7 +1100,8 @@ void netlink_set_err(struct sock *ssk, u32 pid, u32 group, int code) | |||
| 1093 | info.exclude_sk = ssk; | 1100 | info.exclude_sk = ssk; |
| 1094 | info.pid = pid; | 1101 | info.pid = pid; |
| 1095 | info.group = group; | 1102 | info.group = group; |
| 1096 | info.code = code; | 1103 | /* sk->sk_err wants a positive error value */ |
| 1104 | info.code = -code; | ||
| 1097 | 1105 | ||
| 1098 | read_lock(&nl_table_lock); | 1106 | read_lock(&nl_table_lock); |
| 1099 | 1107 | ||
diff --git a/net/sched/act_police.c b/net/sched/act_police.c index 5c72a116b1a4..f8f047b61245 100644 --- a/net/sched/act_police.c +++ b/net/sched/act_police.c | |||
| @@ -183,13 +183,6 @@ override: | |||
| 183 | if (R_tab == NULL) | 183 | if (R_tab == NULL) |
| 184 | goto failure; | 184 | goto failure; |
| 185 | 185 | ||
| 186 | if (!est && (ret == ACT_P_CREATED || | ||
| 187 | !gen_estimator_active(&police->tcf_bstats, | ||
| 188 | &police->tcf_rate_est))) { | ||
| 189 | err = -EINVAL; | ||
| 190 | goto failure; | ||
| 191 | } | ||
| 192 | |||
| 193 | if (parm->peakrate.rate) { | 186 | if (parm->peakrate.rate) { |
| 194 | P_tab = qdisc_get_rtab(&parm->peakrate, | 187 | P_tab = qdisc_get_rtab(&parm->peakrate, |
| 195 | tb[TCA_POLICE_PEAKRATE]); | 188 | tb[TCA_POLICE_PEAKRATE]); |
| @@ -205,6 +198,12 @@ override: | |||
| 205 | &police->tcf_lock, est); | 198 | &police->tcf_lock, est); |
| 206 | if (err) | 199 | if (err) |
| 207 | goto failure_unlock; | 200 | goto failure_unlock; |
| 201 | } else if (tb[TCA_POLICE_AVRATE] && | ||
| 202 | (ret == ACT_P_CREATED || | ||
| 203 | !gen_estimator_active(&police->tcf_bstats, | ||
| 204 | &police->tcf_rate_est))) { | ||
| 205 | err = -EINVAL; | ||
| 206 | goto failure_unlock; | ||
| 208 | } | 207 | } |
| 209 | 208 | ||
| 210 | /* No failure allowed after this point */ | 209 | /* No failure allowed after this point */ |
diff --git a/net/sctp/endpointola.c b/net/sctp/endpointola.c index 4c8d9f45ce09..905fda582b92 100644 --- a/net/sctp/endpointola.c +++ b/net/sctp/endpointola.c | |||
| @@ -111,7 +111,8 @@ static struct sctp_endpoint *sctp_endpoint_init(struct sctp_endpoint *ep, | |||
| 111 | if (sctp_addip_enable) { | 111 | if (sctp_addip_enable) { |
| 112 | auth_chunks->chunks[0] = SCTP_CID_ASCONF; | 112 | auth_chunks->chunks[0] = SCTP_CID_ASCONF; |
| 113 | auth_chunks->chunks[1] = SCTP_CID_ASCONF_ACK; | 113 | auth_chunks->chunks[1] = SCTP_CID_ASCONF_ACK; |
| 114 | auth_chunks->param_hdr.length += htons(2); | 114 | auth_chunks->param_hdr.length = |
| 115 | htons(sizeof(sctp_paramhdr_t) + 2); | ||
| 115 | } | 116 | } |
| 116 | } | 117 | } |
| 117 | 118 | ||
diff --git a/net/sctp/protocol.c b/net/sctp/protocol.c index b78e3be69013..c4986d0f7419 100644 --- a/net/sctp/protocol.c +++ b/net/sctp/protocol.c | |||
| @@ -717,15 +717,20 @@ static int sctp_inetaddr_event(struct notifier_block *this, unsigned long ev, | |||
| 717 | static int sctp_ctl_sock_init(void) | 717 | static int sctp_ctl_sock_init(void) |
| 718 | { | 718 | { |
| 719 | int err; | 719 | int err; |
| 720 | sa_family_t family; | 720 | sa_family_t family = PF_INET; |
| 721 | 721 | ||
| 722 | if (sctp_get_pf_specific(PF_INET6)) | 722 | if (sctp_get_pf_specific(PF_INET6)) |
| 723 | family = PF_INET6; | 723 | family = PF_INET6; |
| 724 | else | ||
| 725 | family = PF_INET; | ||
| 726 | 724 | ||
| 727 | err = inet_ctl_sock_create(&sctp_ctl_sock, family, | 725 | err = inet_ctl_sock_create(&sctp_ctl_sock, family, |
| 728 | SOCK_SEQPACKET, IPPROTO_SCTP, &init_net); | 726 | SOCK_SEQPACKET, IPPROTO_SCTP, &init_net); |
| 727 | |||
| 728 | /* If IPv6 socket could not be created, try the IPv4 socket */ | ||
| 729 | if (err < 0 && family == PF_INET6) | ||
| 730 | err = inet_ctl_sock_create(&sctp_ctl_sock, AF_INET, | ||
| 731 | SOCK_SEQPACKET, IPPROTO_SCTP, | ||
| 732 | &init_net); | ||
| 733 | |||
| 729 | if (err < 0) { | 734 | if (err < 0) { |
| 730 | printk(KERN_ERR | 735 | printk(KERN_ERR |
| 731 | "SCTP: Failed to create the SCTP control socket.\n"); | 736 | "SCTP: Failed to create the SCTP control socket.\n"); |
| @@ -1322,9 +1327,8 @@ SCTP_STATIC __init int sctp_init(void) | |||
| 1322 | out: | 1327 | out: |
| 1323 | return status; | 1328 | return status; |
| 1324 | err_v6_add_protocol: | 1329 | err_v6_add_protocol: |
| 1325 | sctp_v6_del_protocol(); | ||
| 1326 | err_add_protocol: | ||
| 1327 | sctp_v4_del_protocol(); | 1330 | sctp_v4_del_protocol(); |
| 1331 | err_add_protocol: | ||
| 1328 | inet_ctl_sock_destroy(sctp_ctl_sock); | 1332 | inet_ctl_sock_destroy(sctp_ctl_sock); |
| 1329 | err_ctl_sock_init: | 1333 | err_ctl_sock_init: |
| 1330 | sctp_v6_protosw_exit(); | 1334 | sctp_v6_protosw_exit(); |
| @@ -1335,7 +1339,6 @@ err_protosw_init: | |||
| 1335 | sctp_v4_pf_exit(); | 1339 | sctp_v4_pf_exit(); |
| 1336 | sctp_v6_pf_exit(); | 1340 | sctp_v6_pf_exit(); |
| 1337 | sctp_sysctl_unregister(); | 1341 | sctp_sysctl_unregister(); |
| 1338 | list_del(&sctp_af_inet.list); | ||
| 1339 | free_pages((unsigned long)sctp_port_hashtable, | 1342 | free_pages((unsigned long)sctp_port_hashtable, |
| 1340 | get_order(sctp_port_hashsize * | 1343 | get_order(sctp_port_hashsize * |
| 1341 | sizeof(struct sctp_bind_hashbucket))); | 1344 | sizeof(struct sctp_bind_hashbucket))); |
| @@ -1383,7 +1386,6 @@ SCTP_STATIC __exit void sctp_exit(void) | |||
| 1383 | sctp_v4_pf_exit(); | 1386 | sctp_v4_pf_exit(); |
| 1384 | 1387 | ||
| 1385 | sctp_sysctl_unregister(); | 1388 | sctp_sysctl_unregister(); |
| 1386 | list_del(&sctp_af_inet.list); | ||
| 1387 | 1389 | ||
| 1388 | free_pages((unsigned long)sctp_assoc_hashtable, | 1390 | free_pages((unsigned long)sctp_assoc_hashtable, |
| 1389 | get_order(sctp_assoc_hashsize * | 1391 | get_order(sctp_assoc_hashsize * |
diff --git a/net/sctp/sm_sideeffect.c b/net/sctp/sm_sideeffect.c index e1d6076b4f59..b5495aecab60 100644 --- a/net/sctp/sm_sideeffect.c +++ b/net/sctp/sm_sideeffect.c | |||
| @@ -787,36 +787,48 @@ static void sctp_cmd_process_operr(sctp_cmd_seq_t *cmds, | |||
| 787 | struct sctp_association *asoc, | 787 | struct sctp_association *asoc, |
| 788 | struct sctp_chunk *chunk) | 788 | struct sctp_chunk *chunk) |
| 789 | { | 789 | { |
| 790 | struct sctp_operr_chunk *operr_chunk; | ||
| 791 | struct sctp_errhdr *err_hdr; | 790 | struct sctp_errhdr *err_hdr; |
| 791 | struct sctp_ulpevent *ev; | ||
| 792 | 792 | ||
| 793 | operr_chunk = (struct sctp_operr_chunk *)chunk->chunk_hdr; | 793 | while (chunk->chunk_end > chunk->skb->data) { |
| 794 | err_hdr = &operr_chunk->err_hdr; | 794 | err_hdr = (struct sctp_errhdr *)(chunk->skb->data); |
| 795 | 795 | ||
| 796 | switch (err_hdr->cause) { | 796 | ev = sctp_ulpevent_make_remote_error(asoc, chunk, 0, |
| 797 | case SCTP_ERROR_UNKNOWN_CHUNK: | 797 | GFP_ATOMIC); |
| 798 | { | 798 | if (!ev) |
| 799 | struct sctp_chunkhdr *unk_chunk_hdr; | 799 | return; |
| 800 | 800 | ||
| 801 | unk_chunk_hdr = (struct sctp_chunkhdr *)err_hdr->variable; | 801 | sctp_ulpq_tail_event(&asoc->ulpq, ev); |
| 802 | switch (unk_chunk_hdr->type) { | 802 | |
| 803 | /* ADDIP 4.1 A9) If the peer responds to an ASCONF with an | 803 | switch (err_hdr->cause) { |
| 804 | * ERROR chunk reporting that it did not recognized the ASCONF | 804 | case SCTP_ERROR_UNKNOWN_CHUNK: |
| 805 | * chunk type, the sender of the ASCONF MUST NOT send any | 805 | { |
| 806 | * further ASCONF chunks and MUST stop its T-4 timer. | 806 | sctp_chunkhdr_t *unk_chunk_hdr; |
| 807 | */ | 807 | |
| 808 | case SCTP_CID_ASCONF: | 808 | unk_chunk_hdr = (sctp_chunkhdr_t *)err_hdr->variable; |
| 809 | asoc->peer.asconf_capable = 0; | 809 | switch (unk_chunk_hdr->type) { |
| 810 | sctp_add_cmd_sf(cmds, SCTP_CMD_TIMER_STOP, | 810 | /* ADDIP 4.1 A9) If the peer responds to an ASCONF with |
| 811 | * an ERROR chunk reporting that it did not recognized | ||
| 812 | * the ASCONF chunk type, the sender of the ASCONF MUST | ||
| 813 | * NOT send any further ASCONF chunks and MUST stop its | ||
| 814 | * T-4 timer. | ||
| 815 | */ | ||
| 816 | case SCTP_CID_ASCONF: | ||
| 817 | if (asoc->peer.asconf_capable == 0) | ||
| 818 | break; | ||
| 819 | |||
| 820 | asoc->peer.asconf_capable = 0; | ||
| 821 | sctp_add_cmd_sf(cmds, SCTP_CMD_TIMER_STOP, | ||
| 811 | SCTP_TO(SCTP_EVENT_TIMEOUT_T4_RTO)); | 822 | SCTP_TO(SCTP_EVENT_TIMEOUT_T4_RTO)); |
| 823 | break; | ||
| 824 | default: | ||
| 825 | break; | ||
| 826 | } | ||
| 812 | break; | 827 | break; |
| 828 | } | ||
| 813 | default: | 829 | default: |
| 814 | break; | 830 | break; |
| 815 | } | 831 | } |
| 816 | break; | ||
| 817 | } | ||
| 818 | default: | ||
| 819 | break; | ||
| 820 | } | 832 | } |
| 821 | } | 833 | } |
| 822 | 834 | ||
diff --git a/net/sctp/sm_statefuns.c b/net/sctp/sm_statefuns.c index 3a0cd075914f..f88dfded0e3a 100644 --- a/net/sctp/sm_statefuns.c +++ b/net/sctp/sm_statefuns.c | |||
| @@ -3163,7 +3163,6 @@ sctp_disposition_t sctp_sf_operr_notify(const struct sctp_endpoint *ep, | |||
| 3163 | sctp_cmd_seq_t *commands) | 3163 | sctp_cmd_seq_t *commands) |
| 3164 | { | 3164 | { |
| 3165 | struct sctp_chunk *chunk = arg; | 3165 | struct sctp_chunk *chunk = arg; |
| 3166 | struct sctp_ulpevent *ev; | ||
| 3167 | 3166 | ||
| 3168 | if (!sctp_vtag_verify(chunk, asoc)) | 3167 | if (!sctp_vtag_verify(chunk, asoc)) |
| 3169 | return sctp_sf_pdiscard(ep, asoc, type, arg, commands); | 3168 | return sctp_sf_pdiscard(ep, asoc, type, arg, commands); |
| @@ -3173,21 +3172,10 @@ sctp_disposition_t sctp_sf_operr_notify(const struct sctp_endpoint *ep, | |||
| 3173 | return sctp_sf_violation_chunklen(ep, asoc, type, arg, | 3172 | return sctp_sf_violation_chunklen(ep, asoc, type, arg, |
| 3174 | commands); | 3173 | commands); |
| 3175 | 3174 | ||
| 3176 | while (chunk->chunk_end > chunk->skb->data) { | 3175 | sctp_add_cmd_sf(commands, SCTP_CMD_PROCESS_OPERR, |
| 3177 | ev = sctp_ulpevent_make_remote_error(asoc, chunk, 0, | 3176 | SCTP_CHUNK(chunk)); |
| 3178 | GFP_ATOMIC); | ||
| 3179 | if (!ev) | ||
| 3180 | goto nomem; | ||
| 3181 | 3177 | ||
| 3182 | sctp_add_cmd_sf(commands, SCTP_CMD_EVENT_ULP, | ||
| 3183 | SCTP_ULPEVENT(ev)); | ||
| 3184 | sctp_add_cmd_sf(commands, SCTP_CMD_PROCESS_OPERR, | ||
| 3185 | SCTP_CHUNK(chunk)); | ||
| 3186 | } | ||
| 3187 | return SCTP_DISPOSITION_CONSUME; | 3178 | return SCTP_DISPOSITION_CONSUME; |
| 3188 | |||
| 3189 | nomem: | ||
| 3190 | return SCTP_DISPOSITION_NOMEM; | ||
| 3191 | } | 3179 | } |
| 3192 | 3180 | ||
| 3193 | /* | 3181 | /* |
diff --git a/net/sunrpc/sched.c b/net/sunrpc/sched.c index 385f427bedad..ff50a0546865 100644 --- a/net/sunrpc/sched.c +++ b/net/sunrpc/sched.c | |||
| @@ -293,11 +293,6 @@ static void rpc_make_runnable(struct rpc_task *task) | |||
| 293 | rpc_clear_queued(task); | 293 | rpc_clear_queued(task); |
| 294 | if (rpc_test_and_set_running(task)) | 294 | if (rpc_test_and_set_running(task)) |
| 295 | return; | 295 | return; |
| 296 | /* We might have raced */ | ||
| 297 | if (RPC_IS_QUEUED(task)) { | ||
| 298 | rpc_clear_running(task); | ||
| 299 | return; | ||
| 300 | } | ||
| 301 | if (RPC_IS_ASYNC(task)) { | 296 | if (RPC_IS_ASYNC(task)) { |
| 302 | int status; | 297 | int status; |
| 303 | 298 | ||
| @@ -607,7 +602,9 @@ void rpc_release_calldata(const struct rpc_call_ops *ops, void *calldata) | |||
| 607 | */ | 602 | */ |
| 608 | static void __rpc_execute(struct rpc_task *task) | 603 | static void __rpc_execute(struct rpc_task *task) |
| 609 | { | 604 | { |
| 610 | int status = 0; | 605 | struct rpc_wait_queue *queue; |
| 606 | int task_is_async = RPC_IS_ASYNC(task); | ||
| 607 | int status = 0; | ||
| 611 | 608 | ||
| 612 | dprintk("RPC: %5u __rpc_execute flags=0x%x\n", | 609 | dprintk("RPC: %5u __rpc_execute flags=0x%x\n", |
| 613 | task->tk_pid, task->tk_flags); | 610 | task->tk_pid, task->tk_flags); |
| @@ -647,15 +644,25 @@ static void __rpc_execute(struct rpc_task *task) | |||
| 647 | */ | 644 | */ |
| 648 | if (!RPC_IS_QUEUED(task)) | 645 | if (!RPC_IS_QUEUED(task)) |
| 649 | continue; | 646 | continue; |
| 650 | rpc_clear_running(task); | 647 | /* |
| 651 | if (RPC_IS_ASYNC(task)) { | 648 | * The queue->lock protects against races with |
| 652 | /* Careful! we may have raced... */ | 649 | * rpc_make_runnable(). |
| 653 | if (RPC_IS_QUEUED(task)) | 650 | * |
| 654 | return; | 651 | * Note that once we clear RPC_TASK_RUNNING on an asynchronous |
| 655 | if (rpc_test_and_set_running(task)) | 652 | * rpc_task, rpc_make_runnable() can assign it to a |
| 656 | return; | 653 | * different workqueue. We therefore cannot assume that the |
| 654 | * rpc_task pointer may still be dereferenced. | ||
| 655 | */ | ||
| 656 | queue = task->tk_waitqueue; | ||
| 657 | spin_lock_bh(&queue->lock); | ||
| 658 | if (!RPC_IS_QUEUED(task)) { | ||
| 659 | spin_unlock_bh(&queue->lock); | ||
| 657 | continue; | 660 | continue; |
| 658 | } | 661 | } |
| 662 | rpc_clear_running(task); | ||
| 663 | spin_unlock_bh(&queue->lock); | ||
| 664 | if (task_is_async) | ||
| 665 | return; | ||
| 659 | 666 | ||
| 660 | /* sync task: sleep here */ | 667 | /* sync task: sleep here */ |
| 661 | dprintk("RPC: %5u sync task going to sleep\n", task->tk_pid); | 668 | dprintk("RPC: %5u sync task going to sleep\n", task->tk_pid); |
diff --git a/net/sunrpc/xprt.c b/net/sunrpc/xprt.c index 29e401bb612e..62098d101a1f 100644 --- a/net/sunrpc/xprt.c +++ b/net/sunrpc/xprt.c | |||
| @@ -663,7 +663,7 @@ void xprt_connect(struct rpc_task *task) | |||
| 663 | xprt, (xprt_connected(xprt) ? "is" : "is not")); | 663 | xprt, (xprt_connected(xprt) ? "is" : "is not")); |
| 664 | 664 | ||
| 665 | if (!xprt_bound(xprt)) { | 665 | if (!xprt_bound(xprt)) { |
| 666 | task->tk_status = -EIO; | 666 | task->tk_status = -EAGAIN; |
| 667 | return; | 667 | return; |
| 668 | } | 668 | } |
| 669 | if (!xprt_lock_write(xprt, task)) | 669 | if (!xprt_lock_write(xprt, task)) |
diff --git a/net/sunrpc/xprtsock.c b/net/sunrpc/xprtsock.c index 5cbb404c4cdf..29c71e645b27 100644 --- a/net/sunrpc/xprtsock.c +++ b/net/sunrpc/xprtsock.c | |||
| @@ -467,7 +467,7 @@ static int xs_sendpages(struct socket *sock, struct sockaddr *addr, int addrlen, | |||
| 467 | int err, sent = 0; | 467 | int err, sent = 0; |
| 468 | 468 | ||
| 469 | if (unlikely(!sock)) | 469 | if (unlikely(!sock)) |
| 470 | return -ENOTCONN; | 470 | return -ENOTSOCK; |
| 471 | 471 | ||
| 472 | clear_bit(SOCK_ASYNC_NOSPACE, &sock->flags); | 472 | clear_bit(SOCK_ASYNC_NOSPACE, &sock->flags); |
| 473 | if (base != 0) { | 473 | if (base != 0) { |
| @@ -577,6 +577,8 @@ static int xs_udp_send_request(struct rpc_task *task) | |||
| 577 | req->rq_svec->iov_base, | 577 | req->rq_svec->iov_base, |
| 578 | req->rq_svec->iov_len); | 578 | req->rq_svec->iov_len); |
| 579 | 579 | ||
| 580 | if (!xprt_bound(xprt)) | ||
| 581 | return -ENOTCONN; | ||
| 580 | status = xs_sendpages(transport->sock, | 582 | status = xs_sendpages(transport->sock, |
| 581 | xs_addr(xprt), | 583 | xs_addr(xprt), |
| 582 | xprt->addrlen, xdr, | 584 | xprt->addrlen, xdr, |
| @@ -594,6 +596,10 @@ static int xs_udp_send_request(struct rpc_task *task) | |||
| 594 | } | 596 | } |
| 595 | 597 | ||
| 596 | switch (status) { | 598 | switch (status) { |
| 599 | case -ENOTSOCK: | ||
| 600 | status = -ENOTCONN; | ||
| 601 | /* Should we call xs_close() here? */ | ||
| 602 | break; | ||
| 597 | case -EAGAIN: | 603 | case -EAGAIN: |
| 598 | xs_nospace(task); | 604 | xs_nospace(task); |
| 599 | break; | 605 | break; |
| @@ -693,6 +699,10 @@ static int xs_tcp_send_request(struct rpc_task *task) | |||
| 693 | } | 699 | } |
| 694 | 700 | ||
| 695 | switch (status) { | 701 | switch (status) { |
| 702 | case -ENOTSOCK: | ||
| 703 | status = -ENOTCONN; | ||
| 704 | /* Should we call xs_close() here? */ | ||
| 705 | break; | ||
| 696 | case -EAGAIN: | 706 | case -EAGAIN: |
| 697 | xs_nospace(task); | 707 | xs_nospace(task); |
| 698 | break; | 708 | break; |
| @@ -1523,7 +1533,7 @@ static void xs_udp_connect_worker4(struct work_struct *work) | |||
| 1523 | struct socket *sock = transport->sock; | 1533 | struct socket *sock = transport->sock; |
| 1524 | int err, status = -EIO; | 1534 | int err, status = -EIO; |
| 1525 | 1535 | ||
| 1526 | if (xprt->shutdown || !xprt_bound(xprt)) | 1536 | if (xprt->shutdown) |
| 1527 | goto out; | 1537 | goto out; |
| 1528 | 1538 | ||
| 1529 | /* Start by resetting any existing state */ | 1539 | /* Start by resetting any existing state */ |
| @@ -1564,7 +1574,7 @@ static void xs_udp_connect_worker6(struct work_struct *work) | |||
| 1564 | struct socket *sock = transport->sock; | 1574 | struct socket *sock = transport->sock; |
| 1565 | int err, status = -EIO; | 1575 | int err, status = -EIO; |
| 1566 | 1576 | ||
| 1567 | if (xprt->shutdown || !xprt_bound(xprt)) | 1577 | if (xprt->shutdown) |
| 1568 | goto out; | 1578 | goto out; |
| 1569 | 1579 | ||
| 1570 | /* Start by resetting any existing state */ | 1580 | /* Start by resetting any existing state */ |
| @@ -1648,6 +1658,9 @@ static int xs_tcp_finish_connecting(struct rpc_xprt *xprt, struct socket *sock) | |||
| 1648 | write_unlock_bh(&sk->sk_callback_lock); | 1658 | write_unlock_bh(&sk->sk_callback_lock); |
| 1649 | } | 1659 | } |
| 1650 | 1660 | ||
| 1661 | if (!xprt_bound(xprt)) | ||
| 1662 | return -ENOTCONN; | ||
| 1663 | |||
| 1651 | /* Tell the socket layer to start connecting... */ | 1664 | /* Tell the socket layer to start connecting... */ |
| 1652 | xprt->stat.connect_count++; | 1665 | xprt->stat.connect_count++; |
| 1653 | xprt->stat.connect_start = jiffies; | 1666 | xprt->stat.connect_start = jiffies; |
| @@ -1668,7 +1681,7 @@ static void xs_tcp_connect_worker4(struct work_struct *work) | |||
| 1668 | struct socket *sock = transport->sock; | 1681 | struct socket *sock = transport->sock; |
| 1669 | int err, status = -EIO; | 1682 | int err, status = -EIO; |
| 1670 | 1683 | ||
| 1671 | if (xprt->shutdown || !xprt_bound(xprt)) | 1684 | if (xprt->shutdown) |
| 1672 | goto out; | 1685 | goto out; |
| 1673 | 1686 | ||
| 1674 | if (!sock) { | 1687 | if (!sock) { |
| @@ -1728,7 +1741,7 @@ static void xs_tcp_connect_worker6(struct work_struct *work) | |||
| 1728 | struct socket *sock = transport->sock; | 1741 | struct socket *sock = transport->sock; |
| 1729 | int err, status = -EIO; | 1742 | int err, status = -EIO; |
| 1730 | 1743 | ||
| 1731 | if (xprt->shutdown || !xprt_bound(xprt)) | 1744 | if (xprt->shutdown) |
| 1732 | goto out; | 1745 | goto out; |
| 1733 | 1746 | ||
| 1734 | if (!sock) { | 1747 | if (!sock) { |
diff --git a/net/wireless/Kconfig b/net/wireless/Kconfig index e28e2b8fa436..092ae6faccca 100644 --- a/net/wireless/Kconfig +++ b/net/wireless/Kconfig | |||
| @@ -102,3 +102,13 @@ config LIB80211_CRYPT_CCMP | |||
| 102 | 102 | ||
| 103 | config LIB80211_CRYPT_TKIP | 103 | config LIB80211_CRYPT_TKIP |
| 104 | tristate | 104 | tristate |
| 105 | |||
| 106 | config LIB80211_DEBUG | ||
| 107 | bool "lib80211 debugging messages" | ||
| 108 | depends on LIB80211 | ||
| 109 | default n | ||
| 110 | ---help--- | ||
| 111 | You can enable this if you want verbose debugging messages | ||
| 112 | from lib80211. | ||
| 113 | |||
| 114 | If unsure, say N. | ||
diff --git a/net/wireless/lib80211_crypt_ccmp.c b/net/wireless/lib80211_crypt_ccmp.c index db428194c16a..2301dc1edc4c 100644 --- a/net/wireless/lib80211_crypt_ccmp.c +++ b/net/wireless/lib80211_crypt_ccmp.c | |||
| @@ -337,6 +337,7 @@ static int lib80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) | |||
| 337 | pos += 8; | 337 | pos += 8; |
| 338 | 338 | ||
| 339 | if (ccmp_replay_check(pn, key->rx_pn)) { | 339 | if (ccmp_replay_check(pn, key->rx_pn)) { |
| 340 | #ifdef CONFIG_LIB80211_DEBUG | ||
| 340 | if (net_ratelimit()) { | 341 | if (net_ratelimit()) { |
| 341 | printk(KERN_DEBUG "CCMP: replay detected: STA=%pM " | 342 | printk(KERN_DEBUG "CCMP: replay detected: STA=%pM " |
| 342 | "previous PN %02x%02x%02x%02x%02x%02x " | 343 | "previous PN %02x%02x%02x%02x%02x%02x " |
| @@ -346,6 +347,7 @@ static int lib80211_ccmp_decrypt(struct sk_buff *skb, int hdr_len, void *priv) | |||
| 346 | key->rx_pn[3], key->rx_pn[4], key->rx_pn[5], | 347 | key->rx_pn[3], key->rx_pn[4], key->rx_pn[5], |
| 347 | pn[0], pn[1], pn[2], pn[3], pn[4], pn[5]); | 348 | pn[0], pn[1], pn[2], pn[3], pn[4], pn[5]); |
| 348 | } | 349 | } |
| 350 | #endif | ||
| 349 | key->dot11RSNAStatsCCMPReplays++; | 351 | key->dot11RSNAStatsCCMPReplays++; |
| 350 | return -4; | 352 | return -4; |
| 351 | } | 353 | } |
diff --git a/net/wireless/lib80211_crypt_tkip.c b/net/wireless/lib80211_crypt_tkip.c index 7e8e22bfed90..c36287399d7e 100644 --- a/net/wireless/lib80211_crypt_tkip.c +++ b/net/wireless/lib80211_crypt_tkip.c | |||
| @@ -465,12 +465,14 @@ static int lib80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) | |||
| 465 | pos += 8; | 465 | pos += 8; |
| 466 | 466 | ||
| 467 | if (tkip_replay_check(iv32, iv16, tkey->rx_iv32, tkey->rx_iv16)) { | 467 | if (tkip_replay_check(iv32, iv16, tkey->rx_iv32, tkey->rx_iv16)) { |
| 468 | #ifdef CONFIG_LIB80211_DEBUG | ||
| 468 | if (net_ratelimit()) { | 469 | if (net_ratelimit()) { |
| 469 | printk(KERN_DEBUG "TKIP: replay detected: STA=%pM" | 470 | printk(KERN_DEBUG "TKIP: replay detected: STA=%pM" |
| 470 | " previous TSC %08x%04x received TSC " | 471 | " previous TSC %08x%04x received TSC " |
| 471 | "%08x%04x\n", hdr->addr2, | 472 | "%08x%04x\n", hdr->addr2, |
| 472 | tkey->rx_iv32, tkey->rx_iv16, iv32, iv16); | 473 | tkey->rx_iv32, tkey->rx_iv16, iv32, iv16); |
| 473 | } | 474 | } |
| 475 | #endif | ||
| 474 | tkey->dot11RSNAStatsTKIPReplays++; | 476 | tkey->dot11RSNAStatsTKIPReplays++; |
| 475 | return -4; | 477 | return -4; |
| 476 | } | 478 | } |
| @@ -505,10 +507,12 @@ static int lib80211_tkip_decrypt(struct sk_buff *skb, int hdr_len, void *priv) | |||
| 505 | * it needs to be recalculated for the next packet. */ | 507 | * it needs to be recalculated for the next packet. */ |
| 506 | tkey->rx_phase1_done = 0; | 508 | tkey->rx_phase1_done = 0; |
| 507 | } | 509 | } |
| 510 | #ifdef CONFIG_LIB80211_DEBUG | ||
| 508 | if (net_ratelimit()) { | 511 | if (net_ratelimit()) { |
| 509 | printk(KERN_DEBUG "TKIP: ICV error detected: STA=" | 512 | printk(KERN_DEBUG "TKIP: ICV error detected: STA=" |
| 510 | "%pM\n", hdr->addr2); | 513 | "%pM\n", hdr->addr2); |
| 511 | } | 514 | } |
| 515 | #endif | ||
| 512 | tkey->dot11RSNAStatsTKIPICVErrors++; | 516 | tkey->dot11RSNAStatsTKIPICVErrors++; |
| 513 | return -5; | 517 | return -5; |
| 514 | } | 518 | } |
diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c index 1e728fff474e..31b807af3235 100644 --- a/net/wireless/nl80211.c +++ b/net/wireless/nl80211.c | |||
| @@ -1908,6 +1908,11 @@ static int nl80211_get_mesh_params(struct sk_buff *skb, | |||
| 1908 | if (err) | 1908 | if (err) |
| 1909 | return err; | 1909 | return err; |
| 1910 | 1910 | ||
| 1911 | if (!drv->ops->get_mesh_params) { | ||
| 1912 | err = -EOPNOTSUPP; | ||
| 1913 | goto out; | ||
| 1914 | } | ||
| 1915 | |||
| 1911 | /* Get the mesh params */ | 1916 | /* Get the mesh params */ |
| 1912 | rtnl_lock(); | 1917 | rtnl_lock(); |
| 1913 | err = drv->ops->get_mesh_params(&drv->wiphy, dev, &cur_params); | 1918 | err = drv->ops->get_mesh_params(&drv->wiphy, dev, &cur_params); |
| @@ -2017,6 +2022,11 @@ static int nl80211_set_mesh_params(struct sk_buff *skb, struct genl_info *info) | |||
| 2017 | if (err) | 2022 | if (err) |
| 2018 | return err; | 2023 | return err; |
| 2019 | 2024 | ||
| 2025 | if (!drv->ops->set_mesh_params) { | ||
| 2026 | err = -EOPNOTSUPP; | ||
| 2027 | goto out; | ||
| 2028 | } | ||
| 2029 | |||
| 2020 | /* This makes sure that there aren't more than 32 mesh config | 2030 | /* This makes sure that there aren't more than 32 mesh config |
| 2021 | * parameters (otherwise our bitfield scheme would not work.) */ | 2031 | * parameters (otherwise our bitfield scheme would not work.) */ |
| 2022 | BUILD_BUG_ON(NL80211_MESHCONF_ATTR_MAX > 32); | 2032 | BUILD_BUG_ON(NL80211_MESHCONF_ATTR_MAX > 32); |
| @@ -2061,6 +2071,7 @@ static int nl80211_set_mesh_params(struct sk_buff *skb, struct genl_info *info) | |||
| 2061 | err = drv->ops->set_mesh_params(&drv->wiphy, dev, &cfg, mask); | 2071 | err = drv->ops->set_mesh_params(&drv->wiphy, dev, &cfg, mask); |
| 2062 | rtnl_unlock(); | 2072 | rtnl_unlock(); |
| 2063 | 2073 | ||
| 2074 | out: | ||
| 2064 | /* cleanup */ | 2075 | /* cleanup */ |
| 2065 | cfg80211_put_dev(drv); | 2076 | cfg80211_put_dev(drv); |
| 2066 | dev_put(dev); | 2077 | dev_put(dev); |
diff --git a/net/wireless/reg.c b/net/wireless/reg.c index 85c9034c59b2..bd0a16c3de5e 100644 --- a/net/wireless/reg.c +++ b/net/wireless/reg.c | |||
| @@ -380,7 +380,8 @@ static bool is_valid_reg_rule(const struct ieee80211_reg_rule *rule) | |||
| 380 | 380 | ||
| 381 | freq_diff = freq_range->end_freq_khz - freq_range->start_freq_khz; | 381 | freq_diff = freq_range->end_freq_khz - freq_range->start_freq_khz; |
| 382 | 382 | ||
| 383 | if (freq_diff <= 0 || freq_range->max_bandwidth_khz > freq_diff) | 383 | if (freq_range->end_freq_khz <= freq_range->start_freq_khz || |
| 384 | freq_range->max_bandwidth_khz > freq_diff) | ||
| 384 | return false; | 385 | return false; |
| 385 | 386 | ||
| 386 | return true; | 387 | return true; |
diff --git a/net/xfrm/xfrm_state.c b/net/xfrm/xfrm_state.c index e25ff62ab2a6..62a5425cc6aa 100644 --- a/net/xfrm/xfrm_state.c +++ b/net/xfrm/xfrm_state.c | |||
| @@ -748,12 +748,51 @@ static void xfrm_hash_grow_check(struct net *net, int have_hash_collision) | |||
| 748 | schedule_work(&net->xfrm.state_hash_work); | 748 | schedule_work(&net->xfrm.state_hash_work); |
| 749 | } | 749 | } |
| 750 | 750 | ||
| 751 | static void xfrm_state_look_at(struct xfrm_policy *pol, struct xfrm_state *x, | ||
| 752 | struct flowi *fl, unsigned short family, | ||
| 753 | xfrm_address_t *daddr, xfrm_address_t *saddr, | ||
| 754 | struct xfrm_state **best, int *acq_in_progress, | ||
| 755 | int *error) | ||
| 756 | { | ||
| 757 | /* Resolution logic: | ||
| 758 | * 1. There is a valid state with matching selector. Done. | ||
| 759 | * 2. Valid state with inappropriate selector. Skip. | ||
| 760 | * | ||
| 761 | * Entering area of "sysdeps". | ||
| 762 | * | ||
| 763 | * 3. If state is not valid, selector is temporary, it selects | ||
| 764 | * only session which triggered previous resolution. Key | ||
| 765 | * manager will do something to install a state with proper | ||
| 766 | * selector. | ||
| 767 | */ | ||
| 768 | if (x->km.state == XFRM_STATE_VALID) { | ||
| 769 | if ((x->sel.family && | ||
| 770 | !xfrm_selector_match(&x->sel, fl, x->sel.family)) || | ||
| 771 | !security_xfrm_state_pol_flow_match(x, pol, fl)) | ||
| 772 | return; | ||
| 773 | |||
| 774 | if (!*best || | ||
| 775 | (*best)->km.dying > x->km.dying || | ||
| 776 | ((*best)->km.dying == x->km.dying && | ||
| 777 | (*best)->curlft.add_time < x->curlft.add_time)) | ||
| 778 | *best = x; | ||
| 779 | } else if (x->km.state == XFRM_STATE_ACQ) { | ||
| 780 | *acq_in_progress = 1; | ||
| 781 | } else if (x->km.state == XFRM_STATE_ERROR || | ||
| 782 | x->km.state == XFRM_STATE_EXPIRED) { | ||
| 783 | if (xfrm_selector_match(&x->sel, fl, x->sel.family) && | ||
| 784 | security_xfrm_state_pol_flow_match(x, pol, fl)) | ||
| 785 | *error = -ESRCH; | ||
| 786 | } | ||
| 787 | } | ||
| 788 | |||
| 751 | struct xfrm_state * | 789 | struct xfrm_state * |
| 752 | xfrm_state_find(xfrm_address_t *daddr, xfrm_address_t *saddr, | 790 | xfrm_state_find(xfrm_address_t *daddr, xfrm_address_t *saddr, |
| 753 | struct flowi *fl, struct xfrm_tmpl *tmpl, | 791 | struct flowi *fl, struct xfrm_tmpl *tmpl, |
| 754 | struct xfrm_policy *pol, int *err, | 792 | struct xfrm_policy *pol, int *err, |
| 755 | unsigned short family) | 793 | unsigned short family) |
| 756 | { | 794 | { |
| 795 | static xfrm_address_t saddr_wildcard = { }; | ||
| 757 | struct net *net = xp_net(pol); | 796 | struct net *net = xp_net(pol); |
| 758 | unsigned int h; | 797 | unsigned int h; |
| 759 | struct hlist_node *entry; | 798 | struct hlist_node *entry; |
| @@ -773,40 +812,27 @@ xfrm_state_find(xfrm_address_t *daddr, xfrm_address_t *saddr, | |||
| 773 | xfrm_state_addr_check(x, daddr, saddr, family) && | 812 | xfrm_state_addr_check(x, daddr, saddr, family) && |
| 774 | tmpl->mode == x->props.mode && | 813 | tmpl->mode == x->props.mode && |
| 775 | tmpl->id.proto == x->id.proto && | 814 | tmpl->id.proto == x->id.proto && |
| 776 | (tmpl->id.spi == x->id.spi || !tmpl->id.spi)) { | 815 | (tmpl->id.spi == x->id.spi || !tmpl->id.spi)) |
| 777 | /* Resolution logic: | 816 | xfrm_state_look_at(pol, x, fl, family, daddr, saddr, |
| 778 | 1. There is a valid state with matching selector. | 817 | &best, &acquire_in_progress, &error); |
| 779 | Done. | 818 | } |
| 780 | 2. Valid state with inappropriate selector. Skip. | 819 | if (best) |
| 781 | 820 | goto found; | |
| 782 | Entering area of "sysdeps". | 821 | |
| 783 | 822 | h = xfrm_dst_hash(net, daddr, &saddr_wildcard, tmpl->reqid, family); | |
| 784 | 3. If state is not valid, selector is temporary, | 823 | hlist_for_each_entry(x, entry, net->xfrm.state_bydst+h, bydst) { |
| 785 | it selects only session which triggered | 824 | if (x->props.family == family && |
| 786 | previous resolution. Key manager will do | 825 | x->props.reqid == tmpl->reqid && |
| 787 | something to install a state with proper | 826 | !(x->props.flags & XFRM_STATE_WILDRECV) && |
| 788 | selector. | 827 | xfrm_state_addr_check(x, daddr, saddr, family) && |
| 789 | */ | 828 | tmpl->mode == x->props.mode && |
| 790 | if (x->km.state == XFRM_STATE_VALID) { | 829 | tmpl->id.proto == x->id.proto && |
| 791 | if ((x->sel.family && !xfrm_selector_match(&x->sel, fl, x->sel.family)) || | 830 | (tmpl->id.spi == x->id.spi || !tmpl->id.spi)) |
| 792 | !security_xfrm_state_pol_flow_match(x, pol, fl)) | 831 | xfrm_state_look_at(pol, x, fl, family, daddr, saddr, |
| 793 | continue; | 832 | &best, &acquire_in_progress, &error); |
| 794 | if (!best || | ||
| 795 | best->km.dying > x->km.dying || | ||
| 796 | (best->km.dying == x->km.dying && | ||
| 797 | best->curlft.add_time < x->curlft.add_time)) | ||
| 798 | best = x; | ||
| 799 | } else if (x->km.state == XFRM_STATE_ACQ) { | ||
| 800 | acquire_in_progress = 1; | ||
| 801 | } else if (x->km.state == XFRM_STATE_ERROR || | ||
| 802 | x->km.state == XFRM_STATE_EXPIRED) { | ||
| 803 | if (xfrm_selector_match(&x->sel, fl, x->sel.family) && | ||
| 804 | security_xfrm_state_pol_flow_match(x, pol, fl)) | ||
| 805 | error = -ESRCH; | ||
| 806 | } | ||
| 807 | } | ||
| 808 | } | 833 | } |
| 809 | 834 | ||
| 835 | found: | ||
| 810 | x = best; | 836 | x = best; |
| 811 | if (!x && !error && !acquire_in_progress) { | 837 | if (!x && !error && !acquire_in_progress) { |
| 812 | if (tmpl->id.spi && | 838 | if (tmpl->id.spi && |
diff --git a/scripts/kconfig/conf.c b/scripts/kconfig/conf.c index 3e1057f885c6..d190092c3b6e 100644 --- a/scripts/kconfig/conf.c +++ b/scripts/kconfig/conf.c | |||
| @@ -11,6 +11,7 @@ | |||
| 11 | #include <time.h> | 11 | #include <time.h> |
| 12 | #include <unistd.h> | 12 | #include <unistd.h> |
| 13 | #include <sys/stat.h> | 13 | #include <sys/stat.h> |
| 14 | #include <sys/time.h> | ||
| 14 | 15 | ||
| 15 | #define LKC_DIRECT_LINK | 16 | #define LKC_DIRECT_LINK |
| 16 | #include "lkc.h" | 17 | #include "lkc.h" |
| @@ -464,9 +465,22 @@ int main(int ac, char **av) | |||
| 464 | input_mode = set_yes; | 465 | input_mode = set_yes; |
| 465 | break; | 466 | break; |
| 466 | case 'r': | 467 | case 'r': |
| 468 | { | ||
| 469 | struct timeval now; | ||
| 470 | unsigned int seed; | ||
| 471 | |||
| 472 | /* | ||
| 473 | * Use microseconds derived seed, | ||
| 474 | * compensate for systems where it may be zero | ||
| 475 | */ | ||
| 476 | gettimeofday(&now, NULL); | ||
| 477 | |||
| 478 | seed = (unsigned int)((now.tv_sec + 1) * (now.tv_usec + 1)); | ||
| 479 | srand(seed); | ||
| 480 | |||
| 467 | input_mode = set_random; | 481 | input_mode = set_random; |
| 468 | srand(time(NULL)); | ||
| 469 | break; | 482 | break; |
| 483 | } | ||
| 470 | case 'h': | 484 | case 'h': |
| 471 | printf(_("See README for usage info\n")); | 485 | printf(_("See README for usage info\n")); |
| 472 | exit(0); | 486 | exit(0); |
diff --git a/scripts/kconfig/confdata.c b/scripts/kconfig/confdata.c index 830d9eae11f9..273d73888f9d 100644 --- a/scripts/kconfig/confdata.c +++ b/scripts/kconfig/confdata.c | |||
| @@ -843,7 +843,7 @@ void conf_set_all_new_symbols(enum conf_def_mode mode) | |||
| 843 | default: | 843 | default: |
| 844 | continue; | 844 | continue; |
| 845 | } | 845 | } |
| 846 | if (!sym_is_choice(sym) || mode != def_random) | 846 | if (!(sym_is_choice(sym) && mode == def_random)) |
| 847 | sym->flags |= SYMBOL_DEF_USER; | 847 | sym->flags |= SYMBOL_DEF_USER; |
| 848 | break; | 848 | break; |
| 849 | default: | 849 | default: |
| @@ -856,28 +856,49 @@ void conf_set_all_new_symbols(enum conf_def_mode mode) | |||
| 856 | 856 | ||
| 857 | if (mode != def_random) | 857 | if (mode != def_random) |
| 858 | return; | 858 | return; |
| 859 | 859 | /* | |
| 860 | * We have different type of choice blocks. | ||
| 861 | * If curr.tri equal to mod then we can select several | ||
| 862 | * choice symbols in one block. | ||
| 863 | * In this case we do nothing. | ||
| 864 | * If curr.tri equal yes then only one symbol can be | ||
| 865 | * selected in a choice block and we set it to yes, | ||
| 866 | * and the rest to no. | ||
| 867 | */ | ||
| 860 | for_all_symbols(i, csym) { | 868 | for_all_symbols(i, csym) { |
| 861 | if (sym_has_value(csym) || !sym_is_choice(csym)) | 869 | if (sym_has_value(csym) || !sym_is_choice(csym)) |
| 862 | continue; | 870 | continue; |
| 863 | 871 | ||
| 864 | sym_calc_value(csym); | 872 | sym_calc_value(csym); |
| 873 | |||
| 874 | if (csym->curr.tri != yes) | ||
| 875 | continue; | ||
| 876 | |||
| 865 | prop = sym_get_choice_prop(csym); | 877 | prop = sym_get_choice_prop(csym); |
| 866 | def = -1; | 878 | |
| 867 | while (1) { | 879 | /* count entries in choice block */ |
| 868 | cnt = 0; | 880 | cnt = 0; |
| 869 | expr_list_for_each_sym(prop->expr, e, sym) { | 881 | expr_list_for_each_sym(prop->expr, e, sym) |
| 870 | if (sym->visible == no) | 882 | cnt++; |
| 871 | continue; | 883 | |
| 872 | if (def == cnt++) { | 884 | /* |
| 873 | csym->def[S_DEF_USER].val = sym; | 885 | * find a random value and set it to yes, |
| 874 | break; | 886 | * set the rest to no so we have only one set |
| 875 | } | 887 | */ |
| 888 | def = (rand() % cnt); | ||
| 889 | |||
| 890 | cnt = 0; | ||
| 891 | expr_list_for_each_sym(prop->expr, e, sym) { | ||
| 892 | if (def == cnt++) { | ||
| 893 | sym->def[S_DEF_USER].tri = yes; | ||
| 894 | csym->def[S_DEF_USER].val = sym; | ||
| 895 | } | ||
| 896 | else { | ||
| 897 | sym->def[S_DEF_USER].tri = no; | ||
| 876 | } | 898 | } |
| 877 | if (def >= 0 || cnt < 2) | ||
| 878 | break; | ||
| 879 | def = (rand() % cnt) + 1; | ||
| 880 | } | 899 | } |
| 881 | csym->flags |= SYMBOL_DEF_USER; | 900 | csym->flags |= SYMBOL_DEF_USER; |
| 901 | /* clear VALID to get value calculated */ | ||
| 902 | csym->flags &= ~(SYMBOL_VALID); | ||
| 882 | } | 903 | } |
| 883 | } | 904 | } |
diff --git a/scripts/package/Makefile b/scripts/package/Makefile index 8c6b7b09606a..fa4a0a17b7e0 100644 --- a/scripts/package/Makefile +++ b/scripts/package/Makefile | |||
| @@ -35,9 +35,10 @@ $(objtree)/kernel.spec: $(MKSPEC) $(srctree)/Makefile | |||
| 35 | rpm-pkg rpm: $(objtree)/kernel.spec FORCE | 35 | rpm-pkg rpm: $(objtree)/kernel.spec FORCE |
| 36 | $(MAKE) clean | 36 | $(MAKE) clean |
| 37 | $(PREV) ln -sf $(srctree) $(KERNELPATH) | 37 | $(PREV) ln -sf $(srctree) $(KERNELPATH) |
| 38 | $(CONFIG_SHELL) $(srctree)/scripts/setlocalversion > $(objtree)/.scmversion | ||
| 38 | $(PREV) tar -cz $(RCS_TAR_IGNORE) -f $(KERNELPATH).tar.gz $(KERNELPATH)/. | 39 | $(PREV) tar -cz $(RCS_TAR_IGNORE) -f $(KERNELPATH).tar.gz $(KERNELPATH)/. |
| 39 | $(PREV) rm $(KERNELPATH) | 40 | $(PREV) rm $(KERNELPATH) |
| 40 | 41 | rm -f $(objtree)/.scmversion | |
| 41 | set -e; \ | 42 | set -e; \ |
| 42 | $(CONFIG_SHELL) $(srctree)/scripts/mkversion > $(objtree)/.tmp_version | 43 | $(CONFIG_SHELL) $(srctree)/scripts/mkversion > $(objtree)/.tmp_version |
| 43 | set -e; \ | 44 | set -e; \ |
diff --git a/scripts/package/mkspec b/scripts/package/mkspec index ee448cdc6a2b..3d93f8c81252 100755 --- a/scripts/package/mkspec +++ b/scripts/package/mkspec | |||
| @@ -96,7 +96,7 @@ echo "%endif" | |||
| 96 | 96 | ||
| 97 | echo "" | 97 | echo "" |
| 98 | echo "%clean" | 98 | echo "%clean" |
| 99 | echo '#echo -rf $RPM_BUILD_ROOT' | 99 | echo 'rm -rf $RPM_BUILD_ROOT' |
| 100 | echo "" | 100 | echo "" |
| 101 | echo "%files" | 101 | echo "%files" |
| 102 | echo '%defattr (-, root, root)' | 102 | echo '%defattr (-, root, root)' |
diff --git a/scripts/unifdef.c b/scripts/unifdef.c index 552025e72acb..05a31a6c7e1b 100644 --- a/scripts/unifdef.c +++ b/scripts/unifdef.c | |||
| @@ -206,7 +206,7 @@ static void done(void); | |||
| 206 | static void error(const char *); | 206 | static void error(const char *); |
| 207 | static int findsym(const char *); | 207 | static int findsym(const char *); |
| 208 | static void flushline(bool); | 208 | static void flushline(bool); |
| 209 | static Linetype getline(void); | 209 | static Linetype get_line(void); |
| 210 | static Linetype ifeval(const char **); | 210 | static Linetype ifeval(const char **); |
| 211 | static void ignoreoff(void); | 211 | static void ignoreoff(void); |
| 212 | static void ignoreon(void); | 212 | static void ignoreon(void); |
| @@ -512,7 +512,7 @@ process(void) | |||
| 512 | 512 | ||
| 513 | for (;;) { | 513 | for (;;) { |
| 514 | linenum++; | 514 | linenum++; |
| 515 | lineval = getline(); | 515 | lineval = get_line(); |
| 516 | trans_table[ifstate[depth]][lineval](); | 516 | trans_table[ifstate[depth]][lineval](); |
| 517 | debug("process %s -> %s depth %d", | 517 | debug("process %s -> %s depth %d", |
| 518 | linetype_name[lineval], | 518 | linetype_name[lineval], |
| @@ -526,7 +526,7 @@ process(void) | |||
| 526 | * help from skipcomment(). | 526 | * help from skipcomment(). |
| 527 | */ | 527 | */ |
| 528 | static Linetype | 528 | static Linetype |
| 529 | getline(void) | 529 | get_line(void) |
| 530 | { | 530 | { |
| 531 | const char *cp; | 531 | const char *cp; |
| 532 | int cursym; | 532 | int cursym; |
diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c index 0278bc083044..e7ded1326b0f 100644 --- a/security/smack/smack_lsm.c +++ b/security/smack/smack_lsm.c | |||
| @@ -1498,58 +1498,31 @@ static int smack_socket_post_create(struct socket *sock, int family, | |||
| 1498 | * looks for host based access restrictions | 1498 | * looks for host based access restrictions |
| 1499 | * | 1499 | * |
| 1500 | * This version will only be appropriate for really small | 1500 | * This version will only be appropriate for really small |
| 1501 | * sets of single label hosts. Because of the masking | 1501 | * sets of single label hosts. |
| 1502 | * it cannot shortcut out on the first match. There are | ||
| 1503 | * numerious ways to address the problem, but none of them | ||
| 1504 | * have been applied here. | ||
| 1505 | * | 1502 | * |
| 1506 | * Returns the label of the far end or NULL if it's not special. | 1503 | * Returns the label of the far end or NULL if it's not special. |
| 1507 | */ | 1504 | */ |
| 1508 | static char *smack_host_label(struct sockaddr_in *sip) | 1505 | static char *smack_host_label(struct sockaddr_in *sip) |
| 1509 | { | 1506 | { |
| 1510 | struct smk_netlbladdr *snp; | 1507 | struct smk_netlbladdr *snp; |
| 1511 | char *bestlabel = NULL; | ||
| 1512 | struct in_addr *siap = &sip->sin_addr; | 1508 | struct in_addr *siap = &sip->sin_addr; |
| 1513 | struct in_addr *liap; | ||
| 1514 | struct in_addr *miap; | ||
| 1515 | struct in_addr bestmask; | ||
| 1516 | 1509 | ||
| 1517 | if (siap->s_addr == 0) | 1510 | if (siap->s_addr == 0) |
| 1518 | return NULL; | 1511 | return NULL; |
| 1519 | 1512 | ||
| 1520 | bestmask.s_addr = 0; | ||
| 1521 | |||
| 1522 | for (snp = smack_netlbladdrs; snp != NULL; snp = snp->smk_next) { | 1513 | for (snp = smack_netlbladdrs; snp != NULL; snp = snp->smk_next) { |
| 1523 | liap = &snp->smk_host.sin_addr; | ||
| 1524 | miap = &snp->smk_mask; | ||
| 1525 | /* | ||
| 1526 | * If the addresses match after applying the list entry mask | ||
| 1527 | * the entry matches the address. If it doesn't move along to | ||
| 1528 | * the next entry. | ||
| 1529 | */ | ||
| 1530 | if ((liap->s_addr & miap->s_addr) != | ||
| 1531 | (siap->s_addr & miap->s_addr)) | ||
| 1532 | continue; | ||
| 1533 | /* | 1514 | /* |
| 1534 | * If the list entry mask identifies a single address | 1515 | * we break after finding the first match because |
| 1535 | * it can't get any more specific. | 1516 | * the list is sorted from longest to shortest mask |
| 1517 | * so we have found the most specific match | ||
| 1536 | */ | 1518 | */ |
| 1537 | if (miap->s_addr == 0xffffffff) | 1519 | if ((&snp->smk_host.sin_addr)->s_addr == |
| 1520 | (siap->s_addr & (&snp->smk_mask)->s_addr)) { | ||
| 1538 | return snp->smk_label; | 1521 | return snp->smk_label; |
| 1539 | /* | 1522 | } |
| 1540 | * If the list entry mask is less specific than the best | ||
| 1541 | * already found this entry is uninteresting. | ||
| 1542 | */ | ||
| 1543 | if ((miap->s_addr | bestmask.s_addr) == bestmask.s_addr) | ||
| 1544 | continue; | ||
| 1545 | /* | ||
| 1546 | * This is better than any entry found so far. | ||
| 1547 | */ | ||
| 1548 | bestmask.s_addr = miap->s_addr; | ||
| 1549 | bestlabel = snp->smk_label; | ||
| 1550 | } | 1523 | } |
| 1551 | 1524 | ||
| 1552 | return bestlabel; | 1525 | return NULL; |
| 1553 | } | 1526 | } |
| 1554 | 1527 | ||
| 1555 | /** | 1528 | /** |
diff --git a/security/smack/smackfs.c b/security/smack/smackfs.c index 8e42800878f4..51f0efc50dab 100644 --- a/security/smack/smackfs.c +++ b/security/smack/smackfs.c | |||
| @@ -650,10 +650,6 @@ static void *netlbladdr_seq_next(struct seq_file *s, void *v, loff_t *pos) | |||
| 650 | 650 | ||
| 651 | return skp; | 651 | return skp; |
| 652 | } | 652 | } |
| 653 | /* | ||
| 654 | #define BEMASK 0x80000000 | ||
| 655 | */ | ||
| 656 | #define BEMASK 0x00000001 | ||
| 657 | #define BEBITS (sizeof(__be32) * 8) | 653 | #define BEBITS (sizeof(__be32) * 8) |
| 658 | 654 | ||
| 659 | /* | 655 | /* |
| @@ -663,12 +659,10 @@ static int netlbladdr_seq_show(struct seq_file *s, void *v) | |||
| 663 | { | 659 | { |
| 664 | struct smk_netlbladdr *skp = (struct smk_netlbladdr *) v; | 660 | struct smk_netlbladdr *skp = (struct smk_netlbladdr *) v; |
| 665 | unsigned char *hp = (char *) &skp->smk_host.sin_addr.s_addr; | 661 | unsigned char *hp = (char *) &skp->smk_host.sin_addr.s_addr; |
| 666 | __be32 bebits; | 662 | int maskn; |
| 667 | int maskn = 0; | 663 | u32 temp_mask = be32_to_cpu(skp->smk_mask.s_addr); |
| 668 | 664 | ||
| 669 | for (bebits = BEMASK; bebits != 0; maskn++, bebits <<= 1) | 665 | for (maskn = 0; temp_mask; temp_mask <<= 1, maskn++); |
| 670 | if ((skp->smk_mask.s_addr & bebits) == 0) | ||
| 671 | break; | ||
| 672 | 666 | ||
| 673 | seq_printf(s, "%u.%u.%u.%u/%d %s\n", | 667 | seq_printf(s, "%u.%u.%u.%u/%d %s\n", |
| 674 | hp[0], hp[1], hp[2], hp[3], maskn, skp->smk_label); | 668 | hp[0], hp[1], hp[2], hp[3], maskn, skp->smk_label); |
| @@ -702,6 +696,42 @@ static int smk_open_netlbladdr(struct inode *inode, struct file *file) | |||
| 702 | } | 696 | } |
| 703 | 697 | ||
| 704 | /** | 698 | /** |
| 699 | * smk_netlbladdr_insert | ||
| 700 | * @new : netlabel to insert | ||
| 701 | * | ||
| 702 | * This helper insert netlabel in the smack_netlbladdrs list | ||
| 703 | * sorted by netmask length (longest to smallest) | ||
| 704 | */ | ||
| 705 | static void smk_netlbladdr_insert(struct smk_netlbladdr *new) | ||
| 706 | { | ||
| 707 | struct smk_netlbladdr *m; | ||
| 708 | |||
| 709 | if (smack_netlbladdrs == NULL) { | ||
| 710 | smack_netlbladdrs = new; | ||
| 711 | return; | ||
| 712 | } | ||
| 713 | |||
| 714 | /* the comparison '>' is a bit hacky, but works */ | ||
| 715 | if (new->smk_mask.s_addr > smack_netlbladdrs->smk_mask.s_addr) { | ||
| 716 | new->smk_next = smack_netlbladdrs; | ||
| 717 | smack_netlbladdrs = new; | ||
| 718 | return; | ||
| 719 | } | ||
| 720 | for (m = smack_netlbladdrs; m != NULL; m = m->smk_next) { | ||
| 721 | if (m->smk_next == NULL) { | ||
| 722 | m->smk_next = new; | ||
| 723 | return; | ||
| 724 | } | ||
| 725 | if (new->smk_mask.s_addr > m->smk_next->smk_mask.s_addr) { | ||
| 726 | new->smk_next = m->smk_next; | ||
| 727 | m->smk_next = new; | ||
| 728 | return; | ||
| 729 | } | ||
| 730 | } | ||
| 731 | } | ||
| 732 | |||
| 733 | |||
| 734 | /** | ||
| 705 | * smk_write_netlbladdr - write() for /smack/netlabel | 735 | * smk_write_netlbladdr - write() for /smack/netlabel |
| 706 | * @filp: file pointer, not actually used | 736 | * @filp: file pointer, not actually used |
| 707 | * @buf: where to get the data from | 737 | * @buf: where to get the data from |
| @@ -724,8 +754,9 @@ static ssize_t smk_write_netlbladdr(struct file *file, const char __user *buf, | |||
| 724 | struct netlbl_audit audit_info; | 754 | struct netlbl_audit audit_info; |
| 725 | struct in_addr mask; | 755 | struct in_addr mask; |
| 726 | unsigned int m; | 756 | unsigned int m; |
| 727 | __be32 bebits = BEMASK; | 757 | u32 mask_bits = (1<<31); |
| 728 | __be32 nsa; | 758 | __be32 nsa; |
| 759 | u32 temp_mask; | ||
| 729 | 760 | ||
| 730 | /* | 761 | /* |
| 731 | * Must have privilege. | 762 | * Must have privilege. |
| @@ -761,10 +792,13 @@ static ssize_t smk_write_netlbladdr(struct file *file, const char __user *buf, | |||
| 761 | if (sp == NULL) | 792 | if (sp == NULL) |
| 762 | return -EINVAL; | 793 | return -EINVAL; |
| 763 | 794 | ||
| 764 | for (mask.s_addr = 0; m > 0; m--) { | 795 | for (temp_mask = 0; m > 0; m--) { |
| 765 | mask.s_addr |= bebits; | 796 | temp_mask |= mask_bits; |
| 766 | bebits <<= 1; | 797 | mask_bits >>= 1; |
| 767 | } | 798 | } |
| 799 | mask.s_addr = cpu_to_be32(temp_mask); | ||
| 800 | |||
| 801 | newname.sin_addr.s_addr &= mask.s_addr; | ||
| 768 | /* | 802 | /* |
| 769 | * Only allow one writer at a time. Writes should be | 803 | * Only allow one writer at a time. Writes should be |
| 770 | * quite rare and small in any case. | 804 | * quite rare and small in any case. |
| @@ -772,6 +806,7 @@ static ssize_t smk_write_netlbladdr(struct file *file, const char __user *buf, | |||
| 772 | mutex_lock(&smk_netlbladdr_lock); | 806 | mutex_lock(&smk_netlbladdr_lock); |
| 773 | 807 | ||
| 774 | nsa = newname.sin_addr.s_addr; | 808 | nsa = newname.sin_addr.s_addr; |
| 809 | /* try to find if the prefix is already in the list */ | ||
| 775 | for (skp = smack_netlbladdrs; skp != NULL; skp = skp->smk_next) | 810 | for (skp = smack_netlbladdrs; skp != NULL; skp = skp->smk_next) |
| 776 | if (skp->smk_host.sin_addr.s_addr == nsa && | 811 | if (skp->smk_host.sin_addr.s_addr == nsa && |
| 777 | skp->smk_mask.s_addr == mask.s_addr) | 812 | skp->smk_mask.s_addr == mask.s_addr) |
| @@ -787,9 +822,8 @@ static ssize_t smk_write_netlbladdr(struct file *file, const char __user *buf, | |||
| 787 | rc = 0; | 822 | rc = 0; |
| 788 | skp->smk_host.sin_addr.s_addr = newname.sin_addr.s_addr; | 823 | skp->smk_host.sin_addr.s_addr = newname.sin_addr.s_addr; |
| 789 | skp->smk_mask.s_addr = mask.s_addr; | 824 | skp->smk_mask.s_addr = mask.s_addr; |
| 790 | skp->smk_next = smack_netlbladdrs; | ||
| 791 | skp->smk_label = sp; | 825 | skp->smk_label = sp; |
| 792 | smack_netlbladdrs = skp; | 826 | smk_netlbladdr_insert(skp); |
| 793 | } | 827 | } |
| 794 | } else { | 828 | } else { |
| 795 | rc = netlbl_cfg_unlbl_static_del(&init_net, NULL, | 829 | rc = netlbl_cfg_unlbl_static_del(&init_net, NULL, |
diff --git a/sound/arm/pxa2xx-ac97-lib.c b/sound/arm/pxa2xx-ac97-lib.c index 35afd0c33be5..718d06640dd4 100644 --- a/sound/arm/pxa2xx-ac97-lib.c +++ b/sound/arm/pxa2xx-ac97-lib.c | |||
| @@ -21,7 +21,6 @@ | |||
| 21 | #include <sound/pxa2xx-lib.h> | 21 | #include <sound/pxa2xx-lib.h> |
| 22 | 22 | ||
| 23 | #include <asm/irq.h> | 23 | #include <asm/irq.h> |
| 24 | #include <mach/hardware.h> | ||
| 25 | #include <mach/regs-ac97.h> | 24 | #include <mach/regs-ac97.h> |
| 26 | #include <mach/pxa2xx-gpio.h> | 25 | #include <mach/pxa2xx-gpio.h> |
| 27 | #include <mach/audio.h> | 26 | #include <mach/audio.h> |
diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c index 85cf591d4e11..ccec48fc8e3f 100644 --- a/sound/arm/pxa2xx-ac97.c +++ b/sound/arm/pxa2xx-ac97.c | |||
| @@ -20,8 +20,6 @@ | |||
| 20 | #include <sound/initval.h> | 20 | #include <sound/initval.h> |
| 21 | #include <sound/pxa2xx-lib.h> | 21 | #include <sound/pxa2xx-lib.h> |
| 22 | 22 | ||
| 23 | #include <mach/hardware.h> | ||
| 24 | #include <mach/pxa-regs.h> | ||
| 25 | #include <mach/regs-ac97.h> | 23 | #include <mach/regs-ac97.h> |
| 26 | #include <mach/audio.h> | 24 | #include <mach/audio.h> |
| 27 | 25 | ||
diff --git a/sound/arm/pxa2xx-pcm-lib.c b/sound/arm/pxa2xx-pcm-lib.c index 75a0d746fb60..108b643229ba 100644 --- a/sound/arm/pxa2xx-pcm-lib.c +++ b/sound/arm/pxa2xx-pcm-lib.c | |||
| @@ -12,8 +12,7 @@ | |||
| 12 | #include <sound/pcm_params.h> | 12 | #include <sound/pcm_params.h> |
| 13 | #include <sound/pxa2xx-lib.h> | 13 | #include <sound/pxa2xx-lib.h> |
| 14 | 14 | ||
| 15 | #include <asm/dma.h> | 15 | #include <mach/dma.h> |
| 16 | #include <mach/pxa-regs.h> | ||
| 17 | 16 | ||
| 18 | #include "pxa2xx-pcm.h" | 17 | #include "pxa2xx-pcm.h" |
| 19 | 18 | ||
diff --git a/sound/core/oss/mixer_oss.c b/sound/core/oss/mixer_oss.c index 4690b8b5681f..e570649184e2 100644 --- a/sound/core/oss/mixer_oss.c +++ b/sound/core/oss/mixer_oss.c | |||
| @@ -692,6 +692,9 @@ static int snd_mixer_oss_put_volume1(struct snd_mixer_oss_file *fmixer, | |||
| 692 | snd_mixer_oss_put_volume1_vol(fmixer, pslot, slot->numid[SNDRV_MIXER_OSS_ITEM_PVOLUME], left, right); | 692 | snd_mixer_oss_put_volume1_vol(fmixer, pslot, slot->numid[SNDRV_MIXER_OSS_ITEM_PVOLUME], left, right); |
| 693 | if (slot->present & SNDRV_MIXER_OSS_PRESENT_CVOLUME) | 693 | if (slot->present & SNDRV_MIXER_OSS_PRESENT_CVOLUME) |
| 694 | snd_mixer_oss_put_volume1_vol(fmixer, pslot, slot->numid[SNDRV_MIXER_OSS_ITEM_CVOLUME], left, right); | 694 | snd_mixer_oss_put_volume1_vol(fmixer, pslot, slot->numid[SNDRV_MIXER_OSS_ITEM_CVOLUME], left, right); |
| 695 | } else if (slot->present & SNDRV_MIXER_OSS_PRESENT_CVOLUME) { | ||
| 696 | snd_mixer_oss_put_volume1_vol(fmixer, pslot, | ||
| 697 | slot->numid[SNDRV_MIXER_OSS_ITEM_CVOLUME], left, right); | ||
| 695 | } else if (slot->present & SNDRV_MIXER_OSS_PRESENT_GVOLUME) { | 698 | } else if (slot->present & SNDRV_MIXER_OSS_PRESENT_GVOLUME) { |
| 696 | snd_mixer_oss_put_volume1_vol(fmixer, pslot, slot->numid[SNDRV_MIXER_OSS_ITEM_GVOLUME], left, right); | 699 | snd_mixer_oss_put_volume1_vol(fmixer, pslot, slot->numid[SNDRV_MIXER_OSS_ITEM_GVOLUME], left, right); |
| 697 | } else if (slot->present & SNDRV_MIXER_OSS_PRESENT_GLOBAL) { | 700 | } else if (slot->present & SNDRV_MIXER_OSS_PRESENT_GLOBAL) { |
diff --git a/sound/core/oss/pcm_oss.c b/sound/core/oss/pcm_oss.c index 0a1798eafb0b..699d2890535c 100644 --- a/sound/core/oss/pcm_oss.c +++ b/sound/core/oss/pcm_oss.c | |||
| @@ -2872,7 +2872,7 @@ static void snd_pcm_oss_proc_write(struct snd_info_entry *entry, | |||
| 2872 | setup = kmalloc(sizeof(*setup), GFP_KERNEL); | 2872 | setup = kmalloc(sizeof(*setup), GFP_KERNEL); |
| 2873 | if (! setup) { | 2873 | if (! setup) { |
| 2874 | buffer->error = -ENOMEM; | 2874 | buffer->error = -ENOMEM; |
| 2875 | mutex_lock(&pstr->oss.setup_mutex); | 2875 | mutex_unlock(&pstr->oss.setup_mutex); |
| 2876 | return; | 2876 | return; |
| 2877 | } | 2877 | } |
| 2878 | if (pstr->oss.setup_list == NULL) | 2878 | if (pstr->oss.setup_list == NULL) |
| @@ -2886,7 +2886,7 @@ static void snd_pcm_oss_proc_write(struct snd_info_entry *entry, | |||
| 2886 | if (! template.task_name) { | 2886 | if (! template.task_name) { |
| 2887 | kfree(setup); | 2887 | kfree(setup); |
| 2888 | buffer->error = -ENOMEM; | 2888 | buffer->error = -ENOMEM; |
| 2889 | mutex_lock(&pstr->oss.setup_mutex); | 2889 | mutex_unlock(&pstr->oss.setup_mutex); |
| 2890 | return; | 2890 | return; |
| 2891 | } | 2891 | } |
| 2892 | } | 2892 | } |
diff --git a/sound/core/sgbuf.c b/sound/core/sgbuf.c index d4564edd61d7..4e7ec2b49873 100644 --- a/sound/core/sgbuf.c +++ b/sound/core/sgbuf.c | |||
| @@ -38,6 +38,10 @@ int snd_free_sgbuf_pages(struct snd_dma_buffer *dmab) | |||
| 38 | if (! sgbuf) | 38 | if (! sgbuf) |
| 39 | return -EINVAL; | 39 | return -EINVAL; |
| 40 | 40 | ||
| 41 | if (dmab->area) | ||
| 42 | vunmap(dmab->area); | ||
| 43 | dmab->area = NULL; | ||
| 44 | |||
| 41 | tmpb.dev.type = SNDRV_DMA_TYPE_DEV; | 45 | tmpb.dev.type = SNDRV_DMA_TYPE_DEV; |
| 42 | tmpb.dev.dev = sgbuf->dev; | 46 | tmpb.dev.dev = sgbuf->dev; |
| 43 | for (i = 0; i < sgbuf->pages; i++) { | 47 | for (i = 0; i < sgbuf->pages; i++) { |
| @@ -48,9 +52,6 @@ int snd_free_sgbuf_pages(struct snd_dma_buffer *dmab) | |||
| 48 | tmpb.bytes = (sgbuf->table[i].addr & ~PAGE_MASK) << PAGE_SHIFT; | 52 | tmpb.bytes = (sgbuf->table[i].addr & ~PAGE_MASK) << PAGE_SHIFT; |
| 49 | snd_dma_free_pages(&tmpb); | 53 | snd_dma_free_pages(&tmpb); |
| 50 | } | 54 | } |
| 51 | if (dmab->area) | ||
| 52 | vunmap(dmab->area); | ||
| 53 | dmab->area = NULL; | ||
| 54 | 55 | ||
| 55 | kfree(sgbuf->table); | 56 | kfree(sgbuf->table); |
| 56 | kfree(sgbuf->page_table); | 57 | kfree(sgbuf->page_table); |
diff --git a/sound/isa/opl3sa2.c b/sound/isa/opl3sa2.c index 58c972b2af03..b848d1001864 100644 --- a/sound/isa/opl3sa2.c +++ b/sound/isa/opl3sa2.c | |||
| @@ -550,21 +550,27 @@ static int __devinit snd_opl3sa2_mixer(struct snd_card *card) | |||
| 550 | #ifdef CONFIG_PM | 550 | #ifdef CONFIG_PM |
| 551 | static int snd_opl3sa2_suspend(struct snd_card *card, pm_message_t state) | 551 | static int snd_opl3sa2_suspend(struct snd_card *card, pm_message_t state) |
| 552 | { | 552 | { |
| 553 | struct snd_opl3sa2 *chip = card->private_data; | 553 | if (card) { |
| 554 | struct snd_opl3sa2 *chip = card->private_data; | ||
| 554 | 555 | ||
| 555 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); | 556 | snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); |
| 556 | chip->wss->suspend(chip->wss); | 557 | chip->wss->suspend(chip->wss); |
| 557 | /* power down */ | 558 | /* power down */ |
| 558 | snd_opl3sa2_write(chip, OPL3SA2_PM_CTRL, OPL3SA2_PM_D3); | 559 | snd_opl3sa2_write(chip, OPL3SA2_PM_CTRL, OPL3SA2_PM_D3); |
| 560 | } | ||
| 559 | 561 | ||
| 560 | return 0; | 562 | return 0; |
| 561 | } | 563 | } |
| 562 | 564 | ||
| 563 | static int snd_opl3sa2_resume(struct snd_card *card) | 565 | static int snd_opl3sa2_resume(struct snd_card *card) |
| 564 | { | 566 | { |
| 565 | struct snd_opl3sa2 *chip = card->private_data; | 567 | struct snd_opl3sa2 *chip; |
| 566 | int i; | 568 | int i; |
| 567 | 569 | ||
| 570 | if (!card) | ||
| 571 | return 0; | ||
| 572 | |||
| 573 | chip = card->private_data; | ||
| 568 | /* power up */ | 574 | /* power up */ |
| 569 | snd_opl3sa2_write(chip, OPL3SA2_PM_CTRL, OPL3SA2_PM_D0); | 575 | snd_opl3sa2_write(chip, OPL3SA2_PM_CTRL, OPL3SA2_PM_D0); |
| 570 | 576 | ||
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c index 5e909e0da04b..f3b5723c2859 100644 --- a/sound/pci/hda/hda_intel.c +++ b/sound/pci/hda/hda_intel.c | |||
| @@ -2059,26 +2059,31 @@ static int __devinit check_position_fix(struct azx *chip, int fix) | |||
| 2059 | { | 2059 | { |
| 2060 | const struct snd_pci_quirk *q; | 2060 | const struct snd_pci_quirk *q; |
| 2061 | 2061 | ||
| 2062 | /* Check VIA HD Audio Controller exist */ | 2062 | switch (fix) { |
| 2063 | if (chip->pci->vendor == PCI_VENDOR_ID_VIA && | 2063 | case POS_FIX_LPIB: |
| 2064 | chip->pci->device == VIA_HDAC_DEVICE_ID) { | 2064 | case POS_FIX_POSBUF: |
| 2065 | return fix; | ||
| 2066 | } | ||
| 2067 | |||
| 2068 | /* Check VIA/ATI HD Audio Controller exist */ | ||
| 2069 | switch (chip->driver_type) { | ||
| 2070 | case AZX_DRIVER_VIA: | ||
| 2071 | case AZX_DRIVER_ATI: | ||
| 2065 | chip->via_dmapos_patch = 1; | 2072 | chip->via_dmapos_patch = 1; |
| 2066 | /* Use link position directly, avoid any transfer problem. */ | 2073 | /* Use link position directly, avoid any transfer problem. */ |
| 2067 | return POS_FIX_LPIB; | 2074 | return POS_FIX_LPIB; |
| 2068 | } | 2075 | } |
| 2069 | chip->via_dmapos_patch = 0; | 2076 | chip->via_dmapos_patch = 0; |
| 2070 | 2077 | ||
| 2071 | if (fix == POS_FIX_AUTO) { | 2078 | q = snd_pci_quirk_lookup(chip->pci, position_fix_list); |
| 2072 | q = snd_pci_quirk_lookup(chip->pci, position_fix_list); | 2079 | if (q) { |
| 2073 | if (q) { | 2080 | printk(KERN_INFO |
| 2074 | printk(KERN_INFO | 2081 | "hda_intel: position_fix set to %d " |
| 2075 | "hda_intel: position_fix set to %d " | 2082 | "for device %04x:%04x\n", |
| 2076 | "for device %04x:%04x\n", | 2083 | q->value, q->subvendor, q->subdevice); |
| 2077 | q->value, q->subvendor, q->subdevice); | 2084 | return q->value; |
| 2078 | return q->value; | ||
| 2079 | } | ||
| 2080 | } | 2085 | } |
| 2081 | return fix; | 2086 | return POS_FIX_AUTO; |
| 2082 | } | 2087 | } |
| 2083 | 2088 | ||
| 2084 | /* | 2089 | /* |
| @@ -2210,9 +2215,17 @@ static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci, | |||
| 2210 | gcap = azx_readw(chip, GCAP); | 2215 | gcap = azx_readw(chip, GCAP); |
| 2211 | snd_printdd("chipset global capabilities = 0x%x\n", gcap); | 2216 | snd_printdd("chipset global capabilities = 0x%x\n", gcap); |
| 2212 | 2217 | ||
| 2218 | /* ATI chips seems buggy about 64bit DMA addresses */ | ||
| 2219 | if (chip->driver_type == AZX_DRIVER_ATI) | ||
| 2220 | gcap &= ~0x01; | ||
| 2221 | |||
| 2213 | /* allow 64bit DMA address if supported by H/W */ | 2222 | /* allow 64bit DMA address if supported by H/W */ |
| 2214 | if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK)) | 2223 | if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK)) |
| 2215 | pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK); | 2224 | pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK); |
| 2225 | else { | ||
| 2226 | pci_set_dma_mask(pci, DMA_32BIT_MASK); | ||
| 2227 | pci_set_consistent_dma_mask(pci, DMA_32BIT_MASK); | ||
| 2228 | } | ||
| 2216 | 2229 | ||
| 2217 | /* read number of streams from GCAP register instead of using | 2230 | /* read number of streams from GCAP register instead of using |
| 2218 | * hardcoded value | 2231 | * hardcoded value |
diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c index 3bc427645da8..6094344fb223 100644 --- a/sound/pci/hda/patch_sigmatel.c +++ b/sound/pci/hda/patch_sigmatel.c | |||
| @@ -1207,7 +1207,7 @@ static const char *slave_vols[] = { | |||
| 1207 | "LFE Playback Volume", | 1207 | "LFE Playback Volume", |
| 1208 | "Side Playback Volume", | 1208 | "Side Playback Volume", |
| 1209 | "Headphone Playback Volume", | 1209 | "Headphone Playback Volume", |
| 1210 | "Headphone Playback Volume", | 1210 | "Headphone2 Playback Volume", |
| 1211 | "Speaker Playback Volume", | 1211 | "Speaker Playback Volume", |
| 1212 | "External Speaker Playback Volume", | 1212 | "External Speaker Playback Volume", |
| 1213 | "Speaker2 Playback Volume", | 1213 | "Speaker2 Playback Volume", |
| @@ -1221,7 +1221,7 @@ static const char *slave_sws[] = { | |||
| 1221 | "LFE Playback Switch", | 1221 | "LFE Playback Switch", |
| 1222 | "Side Playback Switch", | 1222 | "Side Playback Switch", |
| 1223 | "Headphone Playback Switch", | 1223 | "Headphone Playback Switch", |
| 1224 | "Headphone Playback Switch", | 1224 | "Headphone2 Playback Switch", |
| 1225 | "Speaker Playback Switch", | 1225 | "Speaker Playback Switch", |
| 1226 | "External Speaker Playback Switch", | 1226 | "External Speaker Playback Switch", |
| 1227 | "Speaker2 Playback Switch", | 1227 | "Speaker2 Playback Switch", |
| @@ -3516,6 +3516,7 @@ static int stac92xx_parse_auto_config(struct hda_codec *codec, hda_nid_t dig_out | |||
| 3516 | if (! spec->autocfg.line_outs) | 3516 | if (! spec->autocfg.line_outs) |
| 3517 | return 0; /* can't find valid pin config */ | 3517 | return 0; /* can't find valid pin config */ |
| 3518 | 3518 | ||
| 3519 | #if 0 /* FIXME: temporarily disabled */ | ||
| 3519 | /* If we have no real line-out pin and multiple hp-outs, HPs should | 3520 | /* If we have no real line-out pin and multiple hp-outs, HPs should |
| 3520 | * be set up as multi-channel outputs. | 3521 | * be set up as multi-channel outputs. |
| 3521 | */ | 3522 | */ |
| @@ -3535,6 +3536,7 @@ static int stac92xx_parse_auto_config(struct hda_codec *codec, hda_nid_t dig_out | |||
| 3535 | spec->autocfg.line_out_type = AUTO_PIN_HP_OUT; | 3536 | spec->autocfg.line_out_type = AUTO_PIN_HP_OUT; |
| 3536 | spec->autocfg.hp_outs = 0; | 3537 | spec->autocfg.hp_outs = 0; |
| 3537 | } | 3538 | } |
| 3539 | #endif /* FIXME: temporarily disabled */ | ||
| 3538 | if (spec->autocfg.mono_out_pin) { | 3540 | if (spec->autocfg.mono_out_pin) { |
| 3539 | int dir = get_wcaps(codec, spec->autocfg.mono_out_pin) & | 3541 | int dir = get_wcaps(codec, spec->autocfg.mono_out_pin) & |
| 3540 | (AC_WCAP_OUT_AMP | AC_WCAP_IN_AMP); | 3542 | (AC_WCAP_OUT_AMP | AC_WCAP_IN_AMP); |
diff --git a/sound/pci/mixart/mixart.c b/sound/pci/mixart/mixart.c index f23a73577c22..bb162507fe6c 100644 --- a/sound/pci/mixart/mixart.c +++ b/sound/pci/mixart/mixart.c | |||
| @@ -607,6 +607,7 @@ static int snd_mixart_hw_params(struct snd_pcm_substream *subs, | |||
| 607 | /* set the format to the board */ | 607 | /* set the format to the board */ |
| 608 | err = mixart_set_format(stream, format); | 608 | err = mixart_set_format(stream, format); |
| 609 | if(err < 0) { | 609 | if(err < 0) { |
| 610 | mutex_unlock(&mgr->setup_mutex); | ||
| 610 | return err; | 611 | return err; |
| 611 | } | 612 | } |
| 612 | 613 | ||
diff --git a/sound/soc/pxa/corgi.c b/sound/soc/pxa/corgi.c index 1ba25a559524..ec930667feff 100644 --- a/sound/soc/pxa/corgi.c +++ b/sound/soc/pxa/corgi.c | |||
| @@ -25,8 +25,6 @@ | |||
| 25 | #include <sound/soc-dapm.h> | 25 | #include <sound/soc-dapm.h> |
| 26 | 26 | ||
| 27 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
| 28 | #include <mach/pxa-regs.h> | ||
| 29 | #include <mach/hardware.h> | ||
| 30 | #include <mach/corgi.h> | 28 | #include <mach/corgi.h> |
| 31 | #include <mach/audio.h> | 29 | #include <mach/audio.h> |
| 32 | 30 | ||
diff --git a/sound/soc/pxa/e800_wm9712.c b/sound/soc/pxa/e800_wm9712.c index 2e3386dfa0f0..ac294c797b7d 100644 --- a/sound/soc/pxa/e800_wm9712.c +++ b/sound/soc/pxa/e800_wm9712.c | |||
| @@ -21,8 +21,6 @@ | |||
| 21 | #include <sound/soc-dapm.h> | 21 | #include <sound/soc-dapm.h> |
| 22 | 22 | ||
| 23 | #include <asm/mach-types.h> | 23 | #include <asm/mach-types.h> |
| 24 | #include <mach/pxa-regs.h> | ||
| 25 | #include <mach/hardware.h> | ||
| 26 | #include <mach/audio.h> | 24 | #include <mach/audio.h> |
| 27 | 25 | ||
| 28 | #include "../codecs/wm9712.h" | 26 | #include "../codecs/wm9712.h" |
diff --git a/sound/soc/pxa/em-x270.c b/sound/soc/pxa/em-x270.c index fe4a729ea648..949be9c2a01b 100644 --- a/sound/soc/pxa/em-x270.c +++ b/sound/soc/pxa/em-x270.c | |||
| @@ -29,8 +29,6 @@ | |||
| 29 | #include <sound/soc-dapm.h> | 29 | #include <sound/soc-dapm.h> |
| 30 | 30 | ||
| 31 | #include <asm/mach-types.h> | 31 | #include <asm/mach-types.h> |
| 32 | #include <mach/pxa-regs.h> | ||
| 33 | #include <mach/hardware.h> | ||
| 34 | #include <mach/audio.h> | 32 | #include <mach/audio.h> |
| 35 | 33 | ||
| 36 | #include "../codecs/wm9712.h" | 34 | #include "../codecs/wm9712.h" |
diff --git a/sound/soc/pxa/poodle.c b/sound/soc/pxa/poodle.c index 6e9827189fff..cad2c4c0ac95 100644 --- a/sound/soc/pxa/poodle.c +++ b/sound/soc/pxa/poodle.c | |||
| @@ -26,8 +26,6 @@ | |||
| 26 | 26 | ||
| 27 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
| 28 | #include <asm/hardware/locomo.h> | 28 | #include <asm/hardware/locomo.h> |
| 29 | #include <mach/pxa-regs.h> | ||
| 30 | #include <mach/hardware.h> | ||
| 31 | #include <mach/poodle.h> | 29 | #include <mach/poodle.h> |
| 32 | #include <mach/audio.h> | 30 | #include <mach/audio.h> |
| 33 | 31 | ||
diff --git a/sound/soc/pxa/pxa-ssp.c b/sound/soc/pxa/pxa-ssp.c index 73cb6b4c2f2d..1dfdf66fb1f3 100644 --- a/sound/soc/pxa/pxa-ssp.c +++ b/sound/soc/pxa/pxa-ssp.c | |||
| @@ -29,7 +29,7 @@ | |||
| 29 | #include <sound/pxa2xx-lib.h> | 29 | #include <sound/pxa2xx-lib.h> |
| 30 | 30 | ||
| 31 | #include <mach/hardware.h> | 31 | #include <mach/hardware.h> |
| 32 | #include <mach/pxa-regs.h> | 32 | #include <mach/dma.h> |
| 33 | #include <mach/regs-ssp.h> | 33 | #include <mach/regs-ssp.h> |
| 34 | #include <mach/audio.h> | 34 | #include <mach/audio.h> |
| 35 | #include <mach/ssp.h> | 35 | #include <mach/ssp.h> |
diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c index 812c2b4d3e07..a4a655f7e304 100644 --- a/sound/soc/pxa/pxa2xx-ac97.c +++ b/sound/soc/pxa/pxa2xx-ac97.c | |||
| @@ -20,8 +20,8 @@ | |||
| 20 | #include <sound/pxa2xx-lib.h> | 20 | #include <sound/pxa2xx-lib.h> |
| 21 | 21 | ||
| 22 | #include <mach/hardware.h> | 22 | #include <mach/hardware.h> |
| 23 | #include <mach/pxa-regs.h> | ||
| 24 | #include <mach/regs-ac97.h> | 23 | #include <mach/regs-ac97.h> |
| 24 | #include <mach/dma.h> | ||
| 25 | 25 | ||
| 26 | #include "pxa2xx-pcm.h" | 26 | #include "pxa2xx-pcm.h" |
| 27 | #include "pxa2xx-ac97.h" | 27 | #include "pxa2xx-ac97.h" |
diff --git a/sound/soc/pxa/pxa2xx-i2s.c b/sound/soc/pxa/pxa2xx-i2s.c index 517991fb1099..223de890259e 100644 --- a/sound/soc/pxa/pxa2xx-i2s.c +++ b/sound/soc/pxa/pxa2xx-i2s.c | |||
| @@ -24,7 +24,7 @@ | |||
| 24 | #include <sound/pxa2xx-lib.h> | 24 | #include <sound/pxa2xx-lib.h> |
| 25 | 25 | ||
| 26 | #include <mach/hardware.h> | 26 | #include <mach/hardware.h> |
| 27 | #include <mach/pxa-regs.h> | 27 | #include <mach/dma.h> |
| 28 | #include <mach/pxa2xx-gpio.h> | 28 | #include <mach/pxa2xx-gpio.h> |
| 29 | #include <mach/audio.h> | 29 | #include <mach/audio.h> |
| 30 | 30 | ||
diff --git a/sound/soc/pxa/spitz.c b/sound/soc/pxa/spitz.c index a3b9e6bdf979..de8778fa8729 100644 --- a/sound/soc/pxa/spitz.c +++ b/sound/soc/pxa/spitz.c | |||
| @@ -26,8 +26,6 @@ | |||
| 26 | #include <sound/soc-dapm.h> | 26 | #include <sound/soc-dapm.h> |
| 27 | 27 | ||
| 28 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
| 29 | #include <mach/pxa-regs.h> | ||
| 30 | #include <mach/hardware.h> | ||
| 31 | #include <mach/spitz.h> | 29 | #include <mach/spitz.h> |
| 32 | #include "../codecs/wm8750.h" | 30 | #include "../codecs/wm8750.h" |
| 33 | #include "pxa2xx-pcm.h" | 31 | #include "pxa2xx-pcm.h" |
diff --git a/sound/soc/pxa/tosa.c b/sound/soc/pxa/tosa.c index c77194f74c9b..050223d04e54 100644 --- a/sound/soc/pxa/tosa.c +++ b/sound/soc/pxa/tosa.c | |||
| @@ -30,8 +30,6 @@ | |||
| 30 | 30 | ||
| 31 | #include <asm/mach-types.h> | 31 | #include <asm/mach-types.h> |
| 32 | #include <mach/tosa.h> | 32 | #include <mach/tosa.h> |
| 33 | #include <mach/pxa-regs.h> | ||
| 34 | #include <mach/hardware.h> | ||
| 35 | #include <mach/audio.h> | 33 | #include <mach/audio.h> |
| 36 | 34 | ||
| 37 | #include "../codecs/wm9712.h" | 35 | #include "../codecs/wm9712.h" |
