diff options
-rw-r--r-- | drivers/scsi/qla2xxx/Makefile | 3 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_attr.c | 35 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_dbg.c | 3 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_def.h | 54 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_gbl.h | 85 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_gs.c | 2 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_init.c | 233 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_inline.h | 5 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_iocb.c | 74 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_isr.c | 42 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_mbx.c | 158 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_nx.c | 3635 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_nx.h | 888 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_os.c | 346 | ||||
-rw-r--r-- | drivers/scsi/qla2xxx/qla_sup.c | 80 |
15 files changed, 5518 insertions, 125 deletions
diff --git a/drivers/scsi/qla2xxx/Makefile b/drivers/scsi/qla2xxx/Makefile index 1014db6f9928..5df782f4a097 100644 --- a/drivers/scsi/qla2xxx/Makefile +++ b/drivers/scsi/qla2xxx/Makefile | |||
@@ -1,4 +1,5 @@ | |||
1 | qla2xxx-y := qla_os.o qla_init.o qla_mbx.o qla_iocb.o qla_isr.o qla_gs.o \ | 1 | qla2xxx-y := qla_os.o qla_init.o qla_mbx.o qla_iocb.o qla_isr.o qla_gs.o \ |
2 | qla_dbg.o qla_sup.o qla_attr.o qla_mid.o qla_dfs.o qla_bsg.o | 2 | qla_dbg.o qla_sup.o qla_attr.o qla_mid.o qla_dfs.o qla_bsg.o \ |
3 | qla_nx.o | ||
3 | 4 | ||
4 | obj-$(CONFIG_SCSI_QLA_FC) += qla2xxx.o | 5 | obj-$(CONFIG_SCSI_QLA_FC) += qla2xxx.o |
diff --git a/drivers/scsi/qla2xxx/qla_attr.c b/drivers/scsi/qla2xxx/qla_attr.c index 0710e3c8760f..c272af4a76e4 100644 --- a/drivers/scsi/qla2xxx/qla_attr.c +++ b/drivers/scsi/qla2xxx/qla_attr.c | |||
@@ -41,6 +41,12 @@ qla2x00_sysfs_write_fw_dump(struct kobject *kobj, | |||
41 | struct qla_hw_data *ha = vha->hw; | 41 | struct qla_hw_data *ha = vha->hw; |
42 | int reading; | 42 | int reading; |
43 | 43 | ||
44 | if (IS_QLA82XX(ha)) { | ||
45 | DEBUG2(qla_printk(KERN_INFO, ha, | ||
46 | "Firmware dump not supported for ISP82xx\n")); | ||
47 | return count; | ||
48 | } | ||
49 | |||
44 | if (off != 0) | 50 | if (off != 0) |
45 | return (0); | 51 | return (0); |
46 | 52 | ||
@@ -313,8 +319,8 @@ qla2x00_sysfs_write_optrom_ctl(struct kobject *kobj, | |||
313 | else if (start == (ha->flt_region_boot * 4) || | 319 | else if (start == (ha->flt_region_boot * 4) || |
314 | start == (ha->flt_region_fw * 4)) | 320 | start == (ha->flt_region_fw * 4)) |
315 | valid = 1; | 321 | valid = 1; |
316 | else if (IS_QLA25XX(ha) || IS_QLA81XX(ha)) | 322 | else if (IS_QLA25XX(ha) || IS_QLA8XXX_TYPE(ha)) |
317 | valid = 1; | 323 | valid = 1; |
318 | if (!valid) { | 324 | if (!valid) { |
319 | qla_printk(KERN_WARNING, ha, | 325 | qla_printk(KERN_WARNING, ha, |
320 | "Invalid start region 0x%x/0x%x.\n", start, size); | 326 | "Invalid start region 0x%x/0x%x.\n", start, size); |
@@ -517,6 +523,7 @@ qla2x00_sysfs_write_reset(struct kobject *kobj, | |||
517 | struct scsi_qla_host *vha = shost_priv(dev_to_shost(container_of(kobj, | 523 | struct scsi_qla_host *vha = shost_priv(dev_to_shost(container_of(kobj, |
518 | struct device, kobj))); | 524 | struct device, kobj))); |
519 | struct qla_hw_data *ha = vha->hw; | 525 | struct qla_hw_data *ha = vha->hw; |
526 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | ||
520 | int type; | 527 | int type; |
521 | 528 | ||
522 | if (off != 0) | 529 | if (off != 0) |
@@ -551,6 +558,20 @@ qla2x00_sysfs_write_reset(struct kobject *kobj, | |||
551 | "MPI reset failed on (%ld).\n", vha->host_no); | 558 | "MPI reset failed on (%ld).\n", vha->host_no); |
552 | scsi_unblock_requests(vha->host); | 559 | scsi_unblock_requests(vha->host); |
553 | break; | 560 | break; |
561 | case 0x2025e: | ||
562 | if (!IS_QLA82XX(ha) || vha != base_vha) { | ||
563 | qla_printk(KERN_INFO, ha, | ||
564 | "FCoE ctx reset not supported for host%ld.\n", | ||
565 | vha->host_no); | ||
566 | return count; | ||
567 | } | ||
568 | |||
569 | qla_printk(KERN_INFO, ha, | ||
570 | "Issuing FCoE CTX reset on host%ld.\n", vha->host_no); | ||
571 | set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags); | ||
572 | qla2xxx_wake_dpc(vha); | ||
573 | qla2x00_wait_for_fcoe_ctx_reset(vha); | ||
574 | break; | ||
554 | } | 575 | } |
555 | return count; | 576 | return count; |
556 | } | 577 | } |
@@ -836,7 +857,7 @@ qla2x00_alloc_sysfs_attr(scsi_qla_host_t *vha) | |||
836 | continue; | 857 | continue; |
837 | if (iter->is4GBp_only == 2 && !IS_QLA25XX(vha->hw)) | 858 | if (iter->is4GBp_only == 2 && !IS_QLA25XX(vha->hw)) |
838 | continue; | 859 | continue; |
839 | if (iter->is4GBp_only == 3 && !IS_QLA81XX(vha->hw)) | 860 | if (iter->is4GBp_only == 3 && !(IS_QLA8XXX_TYPE(vha->hw))) |
840 | continue; | 861 | continue; |
841 | 862 | ||
842 | ret = sysfs_create_bin_file(&host->shost_gendev.kobj, | 863 | ret = sysfs_create_bin_file(&host->shost_gendev.kobj, |
@@ -860,7 +881,7 @@ qla2x00_free_sysfs_attr(scsi_qla_host_t *vha) | |||
860 | continue; | 881 | continue; |
861 | if (iter->is4GBp_only == 2 && !IS_QLA25XX(ha)) | 882 | if (iter->is4GBp_only == 2 && !IS_QLA25XX(ha)) |
862 | continue; | 883 | continue; |
863 | if (iter->is4GBp_only == 3 && !IS_QLA81XX(ha)) | 884 | if (iter->is4GBp_only == 3 && !!(IS_QLA8XXX_TYPE(vha->hw))) |
864 | continue; | 885 | continue; |
865 | 886 | ||
866 | sysfs_remove_bin_file(&host->shost_gendev.kobj, | 887 | sysfs_remove_bin_file(&host->shost_gendev.kobj, |
@@ -1233,7 +1254,7 @@ qla2x00_vlan_id_show(struct device *dev, struct device_attribute *attr, | |||
1233 | { | 1254 | { |
1234 | scsi_qla_host_t *vha = shost_priv(class_to_shost(dev)); | 1255 | scsi_qla_host_t *vha = shost_priv(class_to_shost(dev)); |
1235 | 1256 | ||
1236 | if (!IS_QLA81XX(vha->hw)) | 1257 | if (!IS_QLA8XXX_TYPE(vha->hw)) |
1237 | return snprintf(buf, PAGE_SIZE, "\n"); | 1258 | return snprintf(buf, PAGE_SIZE, "\n"); |
1238 | 1259 | ||
1239 | return snprintf(buf, PAGE_SIZE, "%d\n", vha->fcoe_vlan_id); | 1260 | return snprintf(buf, PAGE_SIZE, "%d\n", vha->fcoe_vlan_id); |
@@ -1245,7 +1266,7 @@ qla2x00_vn_port_mac_address_show(struct device *dev, | |||
1245 | { | 1266 | { |
1246 | scsi_qla_host_t *vha = shost_priv(class_to_shost(dev)); | 1267 | scsi_qla_host_t *vha = shost_priv(class_to_shost(dev)); |
1247 | 1268 | ||
1248 | if (!IS_QLA81XX(vha->hw)) | 1269 | if (!IS_QLA8XXX_TYPE(vha->hw)) |
1249 | return snprintf(buf, PAGE_SIZE, "\n"); | 1270 | return snprintf(buf, PAGE_SIZE, "\n"); |
1250 | 1271 | ||
1251 | return snprintf(buf, PAGE_SIZE, "%02x:%02x:%02x:%02x:%02x:%02x\n", | 1272 | return snprintf(buf, PAGE_SIZE, "%02x:%02x:%02x:%02x:%02x:%02x\n", |
@@ -1922,7 +1943,7 @@ qla2x00_init_host_attr(scsi_qla_host_t *vha) | |||
1922 | fc_host_max_npiv_vports(vha->host) = ha->max_npiv_vports; | 1943 | fc_host_max_npiv_vports(vha->host) = ha->max_npiv_vports; |
1923 | fc_host_npiv_vports_inuse(vha->host) = ha->cur_vport_count; | 1944 | fc_host_npiv_vports_inuse(vha->host) = ha->cur_vport_count; |
1924 | 1945 | ||
1925 | if (IS_QLA81XX(ha)) | 1946 | if (IS_QLA8XXX_TYPE(ha)) |
1926 | speed = FC_PORTSPEED_10GBIT; | 1947 | speed = FC_PORTSPEED_10GBIT; |
1927 | else if (IS_QLA25XX(ha)) | 1948 | else if (IS_QLA25XX(ha)) |
1928 | speed = FC_PORTSPEED_8GBIT | FC_PORTSPEED_4GBIT | | 1949 | speed = FC_PORTSPEED_8GBIT | FC_PORTSPEED_4GBIT | |
diff --git a/drivers/scsi/qla2xxx/qla_dbg.c b/drivers/scsi/qla2xxx/qla_dbg.c index cb2eca4c26d8..89bfc119010b 100644 --- a/drivers/scsi/qla2xxx/qla_dbg.c +++ b/drivers/scsi/qla2xxx/qla_dbg.c | |||
@@ -769,6 +769,9 @@ qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) | |||
769 | void *nxt; | 769 | void *nxt; |
770 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); | 770 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
771 | 771 | ||
772 | if (IS_QLA82XX(ha)) | ||
773 | return; | ||
774 | |||
772 | risc_address = ext_mem_cnt = 0; | 775 | risc_address = ext_mem_cnt = 0; |
773 | flags = 0; | 776 | flags = 0; |
774 | 777 | ||
diff --git a/drivers/scsi/qla2xxx/qla_def.h b/drivers/scsi/qla2xxx/qla_def.h index c51bd4e5fb44..edb7a704ed77 100644 --- a/drivers/scsi/qla2xxx/qla_def.h +++ b/drivers/scsi/qla2xxx/qla_def.h | |||
@@ -34,6 +34,7 @@ | |||
34 | #include <scsi/scsi_bsg_fc.h> | 34 | #include <scsi/scsi_bsg_fc.h> |
35 | 35 | ||
36 | #include "qla_bsg.h" | 36 | #include "qla_bsg.h" |
37 | #include "qla_nx.h" | ||
37 | #define QLA2XXX_DRIVER_NAME "qla2xxx" | 38 | #define QLA2XXX_DRIVER_NAME "qla2xxx" |
38 | 39 | ||
39 | /* | 40 | /* |
@@ -207,6 +208,7 @@ typedef struct srb { | |||
207 | * SRB flag definitions | 208 | * SRB flag definitions |
208 | */ | 209 | */ |
209 | #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ | 210 | #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ |
211 | #define SRB_FCP_CMND_DMA_VALID BIT_12 /* FCP command in IOCB */ | ||
210 | 212 | ||
211 | /* | 213 | /* |
212 | * SRB extensions. | 214 | * SRB extensions. |
@@ -417,6 +419,7 @@ typedef union { | |||
417 | struct device_reg_2xxx isp; | 419 | struct device_reg_2xxx isp; |
418 | struct device_reg_24xx isp24; | 420 | struct device_reg_24xx isp24; |
419 | struct device_reg_25xxmq isp25mq; | 421 | struct device_reg_25xxmq isp25mq; |
422 | struct device_reg_82xx isp82; | ||
420 | } device_reg_t; | 423 | } device_reg_t; |
421 | 424 | ||
422 | #define ISP_REQ_Q_IN(ha, reg) \ | 425 | #define ISP_REQ_Q_IN(ha, reg) \ |
@@ -2112,6 +2115,7 @@ struct isp_operations { | |||
2112 | 2115 | ||
2113 | int (*get_flash_version) (struct scsi_qla_host *, void *); | 2116 | int (*get_flash_version) (struct scsi_qla_host *, void *); |
2114 | int (*start_scsi) (srb_t *); | 2117 | int (*start_scsi) (srb_t *); |
2118 | int (*abort_isp) (struct scsi_qla_host *); | ||
2115 | }; | 2119 | }; |
2116 | 2120 | ||
2117 | /* MSI-X Support *************************************************************/ | 2121 | /* MSI-X Support *************************************************************/ |
@@ -2386,7 +2390,8 @@ struct qla_hw_data { | |||
2386 | #define DT_ISP2532 BIT_11 | 2390 | #define DT_ISP2532 BIT_11 |
2387 | #define DT_ISP8432 BIT_12 | 2391 | #define DT_ISP8432 BIT_12 |
2388 | #define DT_ISP8001 BIT_13 | 2392 | #define DT_ISP8001 BIT_13 |
2389 | #define DT_ISP_LAST (DT_ISP8001 << 1) | 2393 | #define DT_ISP8021 BIT_14 |
2394 | #define DT_ISP_LAST (DT_ISP8021 << 1) | ||
2390 | 2395 | ||
2391 | #define DT_IIDMA BIT_26 | 2396 | #define DT_IIDMA BIT_26 |
2392 | #define DT_FWI2 BIT_27 | 2397 | #define DT_FWI2 BIT_27 |
@@ -2409,6 +2414,7 @@ struct qla_hw_data { | |||
2409 | #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) | 2414 | #define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532) |
2410 | #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) | 2415 | #define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432) |
2411 | #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) | 2416 | #define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001) |
2417 | #define IS_QLA82XX(ha) (DT_MASK(ha) & DT_ISP8021) | ||
2412 | 2418 | ||
2413 | #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ | 2419 | #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \ |
2414 | IS_QLA6312(ha) || IS_QLA6322(ha)) | 2420 | IS_QLA6312(ha) || IS_QLA6322(ha)) |
@@ -2419,8 +2425,10 @@ struct qla_hw_data { | |||
2419 | #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ | 2425 | #define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \ |
2420 | IS_QLA84XX(ha)) | 2426 | IS_QLA84XX(ha)) |
2421 | #define IS_QLA81XX(ha) (IS_QLA8001(ha)) | 2427 | #define IS_QLA81XX(ha) (IS_QLA8001(ha)) |
2428 | #define IS_QLA8XXX_TYPE(ha) (IS_QLA81XX(ha) || IS_QLA82XX(ha)) | ||
2422 | #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ | 2429 | #define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \ |
2423 | IS_QLA25XX(ha) || IS_QLA81XX(ha)) | 2430 | IS_QLA25XX(ha) || IS_QLA81XX(ha) || \ |
2431 | IS_QLA82XX(ha)) | ||
2424 | #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha)) | 2432 | #define IS_MSIX_NACK_CAPABLE(ha) (IS_QLA81XX(ha)) |
2425 | #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \ | 2433 | #define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \ |
2426 | (ha)->flags.msix_enabled) | 2434 | (ha)->flags.msix_enabled) |
@@ -2603,6 +2611,7 @@ struct qla_hw_data { | |||
2603 | uint32_t flt_region_npiv_conf; | 2611 | uint32_t flt_region_npiv_conf; |
2604 | uint32_t flt_region_gold_fw; | 2612 | uint32_t flt_region_gold_fw; |
2605 | uint32_t flt_region_fcp_prio; | 2613 | uint32_t flt_region_fcp_prio; |
2614 | uint32_t flt_region_bootload; | ||
2606 | 2615 | ||
2607 | /* Needed for BEACON */ | 2616 | /* Needed for BEACON */ |
2608 | uint16_t beacon_blink_led; | 2617 | uint16_t beacon_blink_led; |
@@ -2634,6 +2643,38 @@ struct qla_hw_data { | |||
2634 | 2643 | ||
2635 | /* FCP_CMND priority support */ | 2644 | /* FCP_CMND priority support */ |
2636 | struct qla_fcp_prio_cfg *fcp_prio_cfg; | 2645 | struct qla_fcp_prio_cfg *fcp_prio_cfg; |
2646 | |||
2647 | struct dma_pool *dl_dma_pool; | ||
2648 | #define DSD_LIST_DMA_POOL_SIZE 512 | ||
2649 | |||
2650 | struct dma_pool *fcp_cmnd_dma_pool; | ||
2651 | mempool_t *ctx_mempool; | ||
2652 | #define FCP_CMND_DMA_POOL_SIZE 512 | ||
2653 | |||
2654 | unsigned long nx_pcibase; /* Base I/O address */ | ||
2655 | uint8_t *nxdb_rd_ptr; /* Doorbell read pointer */ | ||
2656 | unsigned long nxdb_wr_ptr; /* Door bell write pointer */ | ||
2657 | unsigned long first_page_group_start; | ||
2658 | unsigned long first_page_group_end; | ||
2659 | |||
2660 | uint32_t crb_win; | ||
2661 | uint32_t curr_window; | ||
2662 | uint32_t ddr_mn_window; | ||
2663 | unsigned long mn_win_crb; | ||
2664 | unsigned long ms_win_crb; | ||
2665 | int qdr_sn_window; | ||
2666 | uint32_t nx_dev_init_timeout; | ||
2667 | uint32_t nx_reset_timeout; | ||
2668 | rwlock_t hw_lock; | ||
2669 | uint16_t portnum; /* port number */ | ||
2670 | int link_width; | ||
2671 | struct fw_blob *hablob; | ||
2672 | struct qla82xx_legacy_intr_set nx_legacy_intr; | ||
2673 | |||
2674 | uint16_t gbl_dsd_inuse; | ||
2675 | uint16_t gbl_dsd_avail; | ||
2676 | struct list_head gbl_dsd_list; | ||
2677 | #define NUM_DSD_CHAIN 4096 | ||
2637 | }; | 2678 | }; |
2638 | 2679 | ||
2639 | /* | 2680 | /* |
@@ -2686,10 +2727,13 @@ typedef struct scsi_qla_host { | |||
2686 | #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ | 2727 | #define VP_DPC_NEEDED 14 /* wake up for VP dpc handling */ |
2687 | #define UNLOADING 15 | 2728 | #define UNLOADING 15 |
2688 | #define NPIV_CONFIG_NEEDED 16 | 2729 | #define NPIV_CONFIG_NEEDED 16 |
2730 | #define ISP_UNRECOVERABLE 17 | ||
2731 | #define FCOE_CTX_RESET_NEEDED 18 /* Initiate FCoE context reset */ | ||
2689 | 2732 | ||
2690 | uint32_t device_flags; | 2733 | uint32_t device_flags; |
2691 | #define SWITCH_FOUND BIT_0 | 2734 | #define SWITCH_FOUND BIT_0 |
2692 | #define DFLG_NO_CABLE BIT_1 | 2735 | #define DFLG_NO_CABLE BIT_1 |
2736 | #define DFLG_DEV_FAILED BIT_5 | ||
2693 | 2737 | ||
2694 | /* ISP configuration data. */ | 2738 | /* ISP configuration data. */ |
2695 | uint16_t loop_id; /* Host adapter loop id */ | 2739 | uint16_t loop_id; /* Host adapter loop id */ |
@@ -2747,6 +2791,8 @@ typedef struct scsi_qla_host { | |||
2747 | #define VP_ERR_ADAP_NORESOURCES 5 | 2791 | #define VP_ERR_ADAP_NORESOURCES 5 |
2748 | struct qla_hw_data *hw; | 2792 | struct qla_hw_data *hw; |
2749 | struct req_que *req; | 2793 | struct req_que *req; |
2794 | int fw_heartbeat_counter; | ||
2795 | int seconds_since_last_heartbeat; | ||
2750 | } scsi_qla_host_t; | 2796 | } scsi_qla_host_t; |
2751 | 2797 | ||
2752 | /* | 2798 | /* |
@@ -2799,6 +2845,10 @@ typedef struct scsi_qla_host { | |||
2799 | #define OPTROM_SIZE_24XX 0x100000 | 2845 | #define OPTROM_SIZE_24XX 0x100000 |
2800 | #define OPTROM_SIZE_25XX 0x200000 | 2846 | #define OPTROM_SIZE_25XX 0x200000 |
2801 | #define OPTROM_SIZE_81XX 0x400000 | 2847 | #define OPTROM_SIZE_81XX 0x400000 |
2848 | #define OPTROM_SIZE_82XX 0x800000 | ||
2849 | |||
2850 | #define OPTROM_BURST_SIZE 0x1000 | ||
2851 | #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) | ||
2802 | 2852 | ||
2803 | #include "qla_gbl.h" | 2853 | #include "qla_gbl.h" |
2804 | #include "qla_dbg.h" | 2854 | #include "qla_dbg.h" |
diff --git a/drivers/scsi/qla2xxx/qla_gbl.h b/drivers/scsi/qla2xxx/qla_gbl.h index 5efd4c05c79b..cff5a4ae7626 100644 --- a/drivers/scsi/qla2xxx/qla_gbl.h +++ b/drivers/scsi/qla2xxx/qla_gbl.h | |||
@@ -44,6 +44,7 @@ extern int qla2x00_local_device_login(scsi_qla_host_t *, fc_port_t *); | |||
44 | extern void qla2x00_update_fcports(scsi_qla_host_t *); | 44 | extern void qla2x00_update_fcports(scsi_qla_host_t *); |
45 | 45 | ||
46 | extern int qla2x00_abort_isp(scsi_qla_host_t *); | 46 | extern int qla2x00_abort_isp(scsi_qla_host_t *); |
47 | extern void qla2x00_abort_isp_cleanup(scsi_qla_host_t *); | ||
47 | 48 | ||
48 | extern void qla2x00_update_fcport(scsi_qla_host_t *, fc_port_t *); | 49 | extern void qla2x00_update_fcport(scsi_qla_host_t *, fc_port_t *); |
49 | 50 | ||
@@ -79,6 +80,9 @@ extern int ql2xmaxqueues; | |||
79 | extern int ql2xmultique_tag; | 80 | extern int ql2xmultique_tag; |
80 | extern int ql2xfwloadbin; | 81 | extern int ql2xfwloadbin; |
81 | extern int ql2xetsenable; | 82 | extern int ql2xetsenable; |
83 | extern int ql2xshiftctondsd; | ||
84 | extern int ql2xdbwr; | ||
85 | extern int ql2xdontresethba; | ||
82 | 86 | ||
83 | extern int qla2x00_loop_reset(scsi_qla_host_t *); | 87 | extern int qla2x00_loop_reset(scsi_qla_host_t *); |
84 | extern void qla2x00_abort_all_cmds(scsi_qla_host_t *, int); | 88 | extern void qla2x00_abort_all_cmds(scsi_qla_host_t *, int); |
@@ -135,6 +139,7 @@ extern struct fw_blob *qla2x00_request_firmware(scsi_qla_host_t *); | |||
135 | 139 | ||
136 | extern int qla2x00_wait_for_hba_online(scsi_qla_host_t *); | 140 | extern int qla2x00_wait_for_hba_online(scsi_qla_host_t *); |
137 | extern int qla2x00_wait_for_chip_reset(scsi_qla_host_t *); | 141 | extern int qla2x00_wait_for_chip_reset(scsi_qla_host_t *); |
142 | extern int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *); | ||
138 | 143 | ||
139 | extern void qla2xxx_wake_dpc(struct scsi_qla_host *); | 144 | extern void qla2xxx_wake_dpc(struct scsi_qla_host *); |
140 | extern void qla2x00_alert_all_vps(struct rsp_que *, uint16_t *); | 145 | extern void qla2x00_alert_all_vps(struct rsp_que *, uint16_t *); |
@@ -157,6 +162,9 @@ int __qla2x00_marker(struct scsi_qla_host *, struct req_que *, struct rsp_que *, | |||
157 | uint16_t, uint16_t, uint8_t); | 162 | uint16_t, uint16_t, uint8_t); |
158 | extern int qla2x00_start_sp(srb_t *); | 163 | extern int qla2x00_start_sp(srb_t *); |
159 | extern void qla2x00_ctx_sp_free(srb_t *); | 164 | extern void qla2x00_ctx_sp_free(srb_t *); |
165 | extern uint16_t qla24xx_calc_iocbs(uint16_t); | ||
166 | extern void qla24xx_build_scsi_iocbs(srb_t *, struct cmd_type_7 *, uint16_t); | ||
167 | |||
160 | 168 | ||
161 | /* | 169 | /* |
162 | * Global Function Prototypes in qla_mbx.c source file. | 170 | * Global Function Prototypes in qla_mbx.c source file. |
@@ -343,6 +351,7 @@ qla24xx_process_response_queue(struct scsi_qla_host *, struct rsp_que *); | |||
343 | extern int qla2x00_request_irqs(struct qla_hw_data *, struct rsp_que *); | 351 | extern int qla2x00_request_irqs(struct qla_hw_data *, struct rsp_que *); |
344 | extern void qla2x00_free_irqs(scsi_qla_host_t *); | 352 | extern void qla2x00_free_irqs(scsi_qla_host_t *); |
345 | 353 | ||
354 | extern int qla2x00_get_data_rate(scsi_qla_host_t *); | ||
346 | /* | 355 | /* |
347 | * Global Function Prototypes in qla_sup.c source file. | 356 | * Global Function Prototypes in qla_sup.c source file. |
348 | */ | 357 | */ |
@@ -466,6 +475,82 @@ extern void qla25xx_wrt_req_reg(struct qla_hw_data *, uint16_t, uint16_t); | |||
466 | extern void qla25xx_wrt_rsp_reg(struct qla_hw_data *, uint16_t, uint16_t); | 475 | extern void qla25xx_wrt_rsp_reg(struct qla_hw_data *, uint16_t, uint16_t); |
467 | extern void qla24xx_wrt_rsp_reg(struct qla_hw_data *, uint16_t, uint16_t); | 476 | extern void qla24xx_wrt_rsp_reg(struct qla_hw_data *, uint16_t, uint16_t); |
468 | 477 | ||
478 | /* qla82xx related functions */ | ||
479 | |||
480 | /* PCI related functions */ | ||
481 | extern int qla82xx_pci_config(struct scsi_qla_host *); | ||
482 | extern int qla82xx_pci_mem_read_2M(struct qla_hw_data *, u64, void *, int); | ||
483 | extern int qla82xx_pci_mem_write_2M(struct qla_hw_data *, u64, void *, int); | ||
484 | extern char *qla82xx_pci_info_str(struct scsi_qla_host *, char *); | ||
485 | extern int qla82xx_pci_region_offset(struct pci_dev *, int); | ||
486 | extern int qla82xx_pci_region_len(struct pci_dev *, int); | ||
487 | extern int qla82xx_iospace_config(struct qla_hw_data *); | ||
488 | |||
489 | /* Initialization related functions */ | ||
490 | extern void qla82xx_reset_chip(struct scsi_qla_host *); | ||
491 | extern void qla82xx_config_rings(struct scsi_qla_host *); | ||
492 | extern int qla82xx_nvram_config(struct scsi_qla_host *); | ||
493 | extern int qla82xx_pinit_from_rom(scsi_qla_host_t *); | ||
494 | extern int qla82xx_load_firmware(scsi_qla_host_t *); | ||
495 | extern int qla82xx_reset_hw(scsi_qla_host_t *); | ||
496 | extern int qla82xx_load_risc_blob(scsi_qla_host_t *, uint32_t *); | ||
497 | extern void qla82xx_watchdog(scsi_qla_host_t *); | ||
498 | |||
499 | /* Firmware and flash related functions */ | ||
500 | extern int qla82xx_load_risc(scsi_qla_host_t *, uint32_t *); | ||
501 | extern uint8_t *qla82xx_read_optrom_data(struct scsi_qla_host *, uint8_t *, | ||
502 | uint32_t, uint32_t); | ||
503 | extern int qla82xx_write_optrom_data(struct scsi_qla_host *, uint8_t *, | ||
504 | uint32_t, uint32_t); | ||
505 | |||
506 | /* Mailbox related functions */ | ||
507 | extern int qla82xx_abort_isp(scsi_qla_host_t *); | ||
508 | extern int qla82xx_restart_isp(scsi_qla_host_t *); | ||
509 | |||
510 | /* IOCB related functions */ | ||
511 | extern int qla82xx_start_scsi(srb_t *); | ||
512 | |||
513 | /* Interrupt related */ | ||
514 | extern irqreturn_t qla82xx_intr_handler(int, void *); | ||
515 | extern irqreturn_t qla82xx_msi_handler(int, void *); | ||
516 | extern irqreturn_t qla82xx_msix_default(int, void *); | ||
517 | extern irqreturn_t qla82xx_msix_rsp_q(int, void *); | ||
518 | extern void qla82xx_enable_intrs(struct qla_hw_data *); | ||
519 | extern void qla82xx_disable_intrs(struct qla_hw_data *); | ||
520 | extern void qla82xx_mbx_completion(scsi_qla_host_t *, uint16_t); | ||
521 | extern void qla82xx_poll(int, void *); | ||
522 | extern void qla82xx_init_flags(struct qla_hw_data *); | ||
523 | |||
524 | /* ISP 8021 hardware related */ | ||
525 | extern int qla82xx_crb_win_lock(struct qla_hw_data *); | ||
526 | extern void qla82xx_crb_win_unlock(struct qla_hw_data *); | ||
527 | extern int qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *, ulong *); | ||
528 | extern int qla82xx_wr_32(struct qla_hw_data *, ulong, u32); | ||
529 | extern int qla82xx_rd_32(struct qla_hw_data *, ulong); | ||
530 | extern int qla82xx_rdmem(struct qla_hw_data *, u64, void *, int); | ||
531 | extern int qla82xx_wrmem(struct qla_hw_data *, u64, void *, int); | ||
532 | extern int qla82xx_check_for_bad_spd(struct qla_hw_data *); | ||
533 | extern int qla82xx_load_fw(scsi_qla_host_t *); | ||
534 | extern int qla82xx_rom_lock(struct qla_hw_data *); | ||
535 | extern void qla82xx_rom_unlock(struct qla_hw_data *); | ||
536 | extern int qla82xx_rom_fast_read(struct qla_hw_data *, int , int *); | ||
537 | extern int qla82xx_do_rom_fast_read(struct qla_hw_data *, int, int *); | ||
538 | extern unsigned long qla82xx_decode_crb_addr(unsigned long); | ||
539 | |||
540 | /* ISP 8021 IDC */ | ||
541 | extern void qla82xx_clear_drv_active(struct qla_hw_data *); | ||
542 | extern int qla82xx_idc_lock(struct qla_hw_data *); | ||
543 | extern void qla82xx_idc_unlock(struct qla_hw_data *); | ||
544 | extern int qla82xx_device_state_handler(scsi_qla_host_t *); | ||
545 | |||
546 | extern void qla2x00_set_model_info(scsi_qla_host_t *, uint8_t *, | ||
547 | size_t, char *); | ||
548 | extern int qla82xx_mbx_intr_enable(scsi_qla_host_t *); | ||
549 | extern int qla82xx_mbx_intr_disable(scsi_qla_host_t *); | ||
550 | extern void qla82xx_start_iocbs(srb_t *); | ||
551 | extern int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *); | ||
552 | extern void qla82xx_wait_for_pending_commands(scsi_qla_host_t *); | ||
553 | |||
469 | /* BSG related functions */ | 554 | /* BSG related functions */ |
470 | extern int qla24xx_bsg_request(struct fc_bsg_job *); | 555 | extern int qla24xx_bsg_request(struct fc_bsg_job *); |
471 | extern int qla24xx_bsg_timeout(struct fc_bsg_job *); | 556 | extern int qla24xx_bsg_timeout(struct fc_bsg_job *); |
diff --git a/drivers/scsi/qla2xxx/qla_gs.c b/drivers/scsi/qla2xxx/qla_gs.c index 4647015eba63..872c55f049a5 100644 --- a/drivers/scsi/qla2xxx/qla_gs.c +++ b/drivers/scsi/qla2xxx/qla_gs.c | |||
@@ -1535,7 +1535,7 @@ qla2x00_fdmi_rpa(scsi_qla_host_t *vha) | |||
1535 | eiter = (struct ct_fdmi_port_attr *) (entries + size); | 1535 | eiter = (struct ct_fdmi_port_attr *) (entries + size); |
1536 | eiter->type = __constant_cpu_to_be16(FDMI_PORT_SUPPORT_SPEED); | 1536 | eiter->type = __constant_cpu_to_be16(FDMI_PORT_SUPPORT_SPEED); |
1537 | eiter->len = __constant_cpu_to_be16(4 + 4); | 1537 | eiter->len = __constant_cpu_to_be16(4 + 4); |
1538 | if (IS_QLA81XX(ha)) | 1538 | if (IS_QLA8XXX_TYPE(ha)) |
1539 | eiter->a.sup_speed = __constant_cpu_to_be32( | 1539 | eiter->a.sup_speed = __constant_cpu_to_be32( |
1540 | FDMI_PORT_SPEED_10GB); | 1540 | FDMI_PORT_SPEED_10GB); |
1541 | else if (IS_QLA25XX(ha)) | 1541 | else if (IS_QLA25XX(ha)) |
diff --git a/drivers/scsi/qla2xxx/qla_init.c b/drivers/scsi/qla2xxx/qla_init.c index 8517aa49744a..55540d2d4e38 100644 --- a/drivers/scsi/qla2xxx/qla_init.c +++ b/drivers/scsi/qla2xxx/qla_init.c | |||
@@ -328,6 +328,7 @@ qla2x00_initialize_adapter(scsi_qla_host_t *vha) | |||
328 | if (rval) | 328 | if (rval) |
329 | return (rval); | 329 | return (rval); |
330 | } | 330 | } |
331 | |||
331 | if (IS_QLA84XX(ha)) { | 332 | if (IS_QLA84XX(ha)) { |
332 | ha->cs84xx = qla84xx_get_chip(vha); | 333 | ha->cs84xx = qla84xx_get_chip(vha); |
333 | if (!ha->cs84xx) { | 334 | if (!ha->cs84xx) { |
@@ -961,6 +962,9 @@ qla24xx_chip_diag(scsi_qla_host_t *vha) | |||
961 | struct qla_hw_data *ha = vha->hw; | 962 | struct qla_hw_data *ha = vha->hw; |
962 | struct req_que *req = ha->req_q_map[0]; | 963 | struct req_que *req = ha->req_q_map[0]; |
963 | 964 | ||
965 | if (IS_QLA82XX(ha)) | ||
966 | return QLA_SUCCESS; | ||
967 | |||
964 | ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length; | 968 | ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length; |
965 | 969 | ||
966 | rval = qla2x00_mbx_reg_test(vha); | 970 | rval = qla2x00_mbx_reg_test(vha); |
@@ -1183,6 +1187,12 @@ qla2x00_setup_chip(scsi_qla_host_t *vha) | |||
1183 | unsigned long flags; | 1187 | unsigned long flags; |
1184 | uint16_t fw_major_version; | 1188 | uint16_t fw_major_version; |
1185 | 1189 | ||
1190 | if (IS_QLA82XX(ha)) { | ||
1191 | rval = ha->isp_ops->load_risc(vha, &srisc_address); | ||
1192 | if (rval == QLA_SUCCESS) | ||
1193 | goto enable_82xx_npiv; | ||
1194 | } | ||
1195 | |||
1186 | if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { | 1196 | if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { |
1187 | /* Disable SRAM, Instruction RAM and GP RAM parity. */ | 1197 | /* Disable SRAM, Instruction RAM and GP RAM parity. */ |
1188 | spin_lock_irqsave(&ha->hardware_lock, flags); | 1198 | spin_lock_irqsave(&ha->hardware_lock, flags); |
@@ -1208,6 +1218,7 @@ qla2x00_setup_chip(scsi_qla_host_t *vha) | |||
1208 | rval = qla2x00_execute_fw(vha, srisc_address); | 1218 | rval = qla2x00_execute_fw(vha, srisc_address); |
1209 | /* Retrieve firmware information. */ | 1219 | /* Retrieve firmware information. */ |
1210 | if (rval == QLA_SUCCESS) { | 1220 | if (rval == QLA_SUCCESS) { |
1221 | enable_82xx_npiv: | ||
1211 | fw_major_version = ha->fw_major_version; | 1222 | fw_major_version = ha->fw_major_version; |
1212 | rval = qla2x00_get_fw_version(vha, | 1223 | rval = qla2x00_get_fw_version(vha, |
1213 | &ha->fw_major_version, | 1224 | &ha->fw_major_version, |
@@ -1232,8 +1243,10 @@ qla2x00_setup_chip(scsi_qla_host_t *vha) | |||
1232 | &ha->fw_xcb_count, NULL, NULL, | 1243 | &ha->fw_xcb_count, NULL, NULL, |
1233 | &ha->max_npiv_vports, NULL); | 1244 | &ha->max_npiv_vports, NULL); |
1234 | 1245 | ||
1235 | if (!fw_major_version && ql2xallocfwdump) | 1246 | if (!fw_major_version && ql2xallocfwdump) { |
1236 | qla2x00_alloc_fw_dump(vha); | 1247 | if (!IS_QLA82XX(ha)) |
1248 | qla2x00_alloc_fw_dump(vha); | ||
1249 | } | ||
1237 | } | 1250 | } |
1238 | } else { | 1251 | } else { |
1239 | DEBUG2(printk(KERN_INFO | 1252 | DEBUG2(printk(KERN_INFO |
@@ -1390,6 +1403,9 @@ qla24xx_update_fw_options(scsi_qla_host_t *vha) | |||
1390 | int rval; | 1403 | int rval; |
1391 | struct qla_hw_data *ha = vha->hw; | 1404 | struct qla_hw_data *ha = vha->hw; |
1392 | 1405 | ||
1406 | if (IS_QLA82XX(ha)) | ||
1407 | return; | ||
1408 | |||
1393 | /* Update Serial Link options. */ | 1409 | /* Update Serial Link options. */ |
1394 | if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) | 1410 | if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) |
1395 | return; | 1411 | return; |
@@ -1824,7 +1840,7 @@ qla2x00_configure_hba(scsi_qla_host_t *vha) | |||
1824 | return(rval); | 1840 | return(rval); |
1825 | } | 1841 | } |
1826 | 1842 | ||
1827 | static inline void | 1843 | inline void |
1828 | qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len, | 1844 | qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len, |
1829 | char *def) | 1845 | char *def) |
1830 | { | 1846 | { |
@@ -1832,7 +1848,7 @@ qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len, | |||
1832 | uint16_t index; | 1848 | uint16_t index; |
1833 | struct qla_hw_data *ha = vha->hw; | 1849 | struct qla_hw_data *ha = vha->hw; |
1834 | int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && | 1850 | int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && |
1835 | !IS_QLA81XX(ha); | 1851 | !IS_QLA8XXX_TYPE(ha); |
1836 | 1852 | ||
1837 | if (memcmp(model, BINZERO, len) != 0) { | 1853 | if (memcmp(model, BINZERO, len) != 0) { |
1838 | strncpy(ha->model_number, model, len); | 1854 | strncpy(ha->model_number, model, len); |
@@ -3552,6 +3568,45 @@ qla2x00_update_fcports(scsi_qla_host_t *base_vha) | |||
3552 | qla2x00_rport_del(fcport); | 3568 | qla2x00_rport_del(fcport); |
3553 | } | 3569 | } |
3554 | 3570 | ||
3571 | void | ||
3572 | qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha) | ||
3573 | { | ||
3574 | struct qla_hw_data *ha = vha->hw; | ||
3575 | struct scsi_qla_host *vp, *base_vha = pci_get_drvdata(ha->pdev); | ||
3576 | struct scsi_qla_host *tvp; | ||
3577 | |||
3578 | vha->flags.online = 0; | ||
3579 | ha->flags.chip_reset_done = 0; | ||
3580 | clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | ||
3581 | ha->qla_stats.total_isp_aborts++; | ||
3582 | |||
3583 | qla_printk(KERN_INFO, ha, | ||
3584 | "Performing ISP error recovery - ha= %p.\n", ha); | ||
3585 | |||
3586 | /* Chip reset does not apply to 82XX */ | ||
3587 | if (!IS_QLA82XX(ha)) | ||
3588 | ha->isp_ops->reset_chip(vha); | ||
3589 | |||
3590 | atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); | ||
3591 | if (atomic_read(&vha->loop_state) != LOOP_DOWN) { | ||
3592 | atomic_set(&vha->loop_state, LOOP_DOWN); | ||
3593 | qla2x00_mark_all_devices_lost(vha, 0); | ||
3594 | list_for_each_entry_safe(vp, tvp, &base_vha->hw->vp_list, list) | ||
3595 | qla2x00_mark_all_devices_lost(vp, 0); | ||
3596 | } else { | ||
3597 | if (!atomic_read(&vha->loop_down_timer)) | ||
3598 | atomic_set(&vha->loop_down_timer, | ||
3599 | LOOP_DOWN_TIME); | ||
3600 | } | ||
3601 | |||
3602 | /* Make sure for ISP 82XX IO DMA is complete */ | ||
3603 | if (IS_QLA82XX(ha)) | ||
3604 | qla82xx_wait_for_pending_commands(vha); | ||
3605 | |||
3606 | /* Requeue all commands in outstanding command list. */ | ||
3607 | qla2x00_abort_all_cmds(vha, DID_RESET << 16); | ||
3608 | } | ||
3609 | |||
3555 | /* | 3610 | /* |
3556 | * qla2x00_abort_isp | 3611 | * qla2x00_abort_isp |
3557 | * Resets ISP and aborts all outstanding commands. | 3612 | * Resets ISP and aborts all outstanding commands. |
@@ -3573,27 +3628,7 @@ qla2x00_abort_isp(scsi_qla_host_t *vha) | |||
3573 | struct req_que *req = ha->req_q_map[0]; | 3628 | struct req_que *req = ha->req_q_map[0]; |
3574 | 3629 | ||
3575 | if (vha->flags.online) { | 3630 | if (vha->flags.online) { |
3576 | vha->flags.online = 0; | 3631 | qla2x00_abort_isp_cleanup(vha); |
3577 | ha->flags.chip_reset_done = 0; | ||
3578 | clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | ||
3579 | ha->qla_stats.total_isp_aborts++; | ||
3580 | |||
3581 | qla_printk(KERN_INFO, ha, | ||
3582 | "Performing ISP error recovery - ha= %p.\n", ha); | ||
3583 | ha->isp_ops->reset_chip(vha); | ||
3584 | |||
3585 | atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); | ||
3586 | if (atomic_read(&vha->loop_state) != LOOP_DOWN) { | ||
3587 | atomic_set(&vha->loop_state, LOOP_DOWN); | ||
3588 | qla2x00_mark_all_devices_lost(vha, 0); | ||
3589 | } else { | ||
3590 | if (!atomic_read(&vha->loop_down_timer)) | ||
3591 | atomic_set(&vha->loop_down_timer, | ||
3592 | LOOP_DOWN_TIME); | ||
3593 | } | ||
3594 | |||
3595 | /* Requeue all commands in outstanding command list. */ | ||
3596 | qla2x00_abort_all_cmds(vha, DID_RESET << 16); | ||
3597 | 3632 | ||
3598 | if (unlikely(pci_channel_offline(ha->pdev) && | 3633 | if (unlikely(pci_channel_offline(ha->pdev) && |
3599 | ha->flags.pci_channel_io_perm_failure)) { | 3634 | ha->flags.pci_channel_io_perm_failure)) { |
@@ -3849,6 +3884,9 @@ qla24xx_reset_adapter(scsi_qla_host_t *vha) | |||
3849 | struct qla_hw_data *ha = vha->hw; | 3884 | struct qla_hw_data *ha = vha->hw; |
3850 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | 3885 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
3851 | 3886 | ||
3887 | if (IS_QLA82XX(ha)) | ||
3888 | return; | ||
3889 | |||
3852 | vha->flags.online = 0; | 3890 | vha->flags.online = 0; |
3853 | ha->isp_ops->disable_intrs(ha); | 3891 | ha->isp_ops->disable_intrs(ha); |
3854 | 3892 | ||
@@ -3912,6 +3950,8 @@ qla24xx_nvram_config(scsi_qla_host_t *vha) | |||
3912 | } | 3950 | } |
3913 | ha->nvram_size = sizeof(struct nvram_24xx); | 3951 | ha->nvram_size = sizeof(struct nvram_24xx); |
3914 | ha->vpd_size = FA_NVRAM_VPD_SIZE; | 3952 | ha->vpd_size = FA_NVRAM_VPD_SIZE; |
3953 | if (IS_QLA82XX(ha)) | ||
3954 | ha->vpd_size = FA_VPD_SIZE_82XX; | ||
3915 | 3955 | ||
3916 | /* Get VPD data into cache */ | 3956 | /* Get VPD data into cache */ |
3917 | ha->vpd = ha->nvram + VPD_OFFSET; | 3957 | ha->vpd = ha->nvram + VPD_OFFSET; |
@@ -4775,7 +4815,7 @@ qla81xx_nvram_config(scsi_qla_host_t *vha) | |||
4775 | * Setup driver NVRAM options. | 4815 | * Setup driver NVRAM options. |
4776 | */ | 4816 | */ |
4777 | qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), | 4817 | qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), |
4778 | "QLE81XX"); | 4818 | "QLE8XXX"); |
4779 | 4819 | ||
4780 | /* Use alternate WWN? */ | 4820 | /* Use alternate WWN? */ |
4781 | if (nv->host_p & __constant_cpu_to_le32(BIT_15)) { | 4821 | if (nv->host_p & __constant_cpu_to_le32(BIT_15)) { |
@@ -4898,6 +4938,147 @@ qla81xx_nvram_config(scsi_qla_host_t *vha) | |||
4898 | return (rval); | 4938 | return (rval); |
4899 | } | 4939 | } |
4900 | 4940 | ||
4941 | int | ||
4942 | qla82xx_restart_isp(scsi_qla_host_t *vha) | ||
4943 | { | ||
4944 | int status, rval; | ||
4945 | uint32_t wait_time; | ||
4946 | struct qla_hw_data *ha = vha->hw; | ||
4947 | struct req_que *req = ha->req_q_map[0]; | ||
4948 | struct rsp_que *rsp = ha->rsp_q_map[0]; | ||
4949 | struct scsi_qla_host *vp; | ||
4950 | struct scsi_qla_host *tvp; | ||
4951 | |||
4952 | status = qla2x00_init_rings(vha); | ||
4953 | if (!status) { | ||
4954 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); | ||
4955 | ha->flags.chip_reset_done = 1; | ||
4956 | |||
4957 | status = qla2x00_fw_ready(vha); | ||
4958 | if (!status) { | ||
4959 | qla_printk(KERN_INFO, ha, | ||
4960 | "%s(): Start configure loop, " | ||
4961 | "status = %d\n", __func__, status); | ||
4962 | |||
4963 | /* Issue a marker after FW becomes ready. */ | ||
4964 | qla2x00_marker(vha, req, rsp, 0, 0, MK_SYNC_ALL); | ||
4965 | |||
4966 | vha->flags.online = 1; | ||
4967 | /* Wait at most MAX_TARGET RSCNs for a stable link. */ | ||
4968 | wait_time = 256; | ||
4969 | do { | ||
4970 | clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); | ||
4971 | qla2x00_configure_loop(vha); | ||
4972 | wait_time--; | ||
4973 | } while (!atomic_read(&vha->loop_down_timer) && | ||
4974 | !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) && | ||
4975 | wait_time && | ||
4976 | (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))); | ||
4977 | } | ||
4978 | |||
4979 | /* if no cable then assume it's good */ | ||
4980 | if ((vha->device_flags & DFLG_NO_CABLE)) | ||
4981 | status = 0; | ||
4982 | |||
4983 | qla_printk(KERN_INFO, ha, | ||
4984 | "%s(): Configure loop done, status = 0x%x\n", | ||
4985 | __func__, status); | ||
4986 | } | ||
4987 | |||
4988 | if (!status) { | ||
4989 | clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); | ||
4990 | |||
4991 | if (!atomic_read(&vha->loop_down_timer)) { | ||
4992 | /* | ||
4993 | * Issue marker command only when we are going | ||
4994 | * to start the I/O . | ||
4995 | */ | ||
4996 | vha->marker_needed = 1; | ||
4997 | } | ||
4998 | |||
4999 | vha->flags.online = 1; | ||
5000 | |||
5001 | ha->isp_ops->enable_intrs(ha); | ||
5002 | |||
5003 | ha->isp_abort_cnt = 0; | ||
5004 | clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); | ||
5005 | |||
5006 | if (ha->fce) { | ||
5007 | ha->flags.fce_enabled = 1; | ||
5008 | memset(ha->fce, 0, | ||
5009 | fce_calc_size(ha->fce_bufs)); | ||
5010 | rval = qla2x00_enable_fce_trace(vha, | ||
5011 | ha->fce_dma, ha->fce_bufs, ha->fce_mb, | ||
5012 | &ha->fce_bufs); | ||
5013 | if (rval) { | ||
5014 | qla_printk(KERN_WARNING, ha, | ||
5015 | "Unable to reinitialize FCE " | ||
5016 | "(%d).\n", rval); | ||
5017 | ha->flags.fce_enabled = 0; | ||
5018 | } | ||
5019 | } | ||
5020 | |||
5021 | if (ha->eft) { | ||
5022 | memset(ha->eft, 0, EFT_SIZE); | ||
5023 | rval = qla2x00_enable_eft_trace(vha, | ||
5024 | ha->eft_dma, EFT_NUM_BUFFERS); | ||
5025 | if (rval) { | ||
5026 | qla_printk(KERN_WARNING, ha, | ||
5027 | "Unable to reinitialize EFT " | ||
5028 | "(%d).\n", rval); | ||
5029 | } | ||
5030 | } | ||
5031 | } else { /* failed the ISP abort */ | ||
5032 | vha->flags.online = 1; | ||
5033 | if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { | ||
5034 | if (ha->isp_abort_cnt == 0) { | ||
5035 | qla_printk(KERN_WARNING, ha, | ||
5036 | "ISP error recovery failed - " | ||
5037 | "board disabled\n"); | ||
5038 | /* | ||
5039 | * The next call disables the board | ||
5040 | * completely. | ||
5041 | */ | ||
5042 | ha->isp_ops->reset_adapter(vha); | ||
5043 | vha->flags.online = 0; | ||
5044 | clear_bit(ISP_ABORT_RETRY, | ||
5045 | &vha->dpc_flags); | ||
5046 | status = 0; | ||
5047 | } else { /* schedule another ISP abort */ | ||
5048 | ha->isp_abort_cnt--; | ||
5049 | qla_printk(KERN_INFO, ha, | ||
5050 | "qla%ld: ISP abort - " | ||
5051 | "retry remaining %d\n", | ||
5052 | vha->host_no, ha->isp_abort_cnt); | ||
5053 | status = 1; | ||
5054 | } | ||
5055 | } else { | ||
5056 | ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; | ||
5057 | qla_printk(KERN_INFO, ha, | ||
5058 | "(%ld): ISP error recovery " | ||
5059 | "- retrying (%d) more times\n", | ||
5060 | vha->host_no, ha->isp_abort_cnt); | ||
5061 | set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); | ||
5062 | status = 1; | ||
5063 | } | ||
5064 | } | ||
5065 | |||
5066 | if (!status) { | ||
5067 | DEBUG(printk(KERN_INFO | ||
5068 | "qla82xx_restart_isp(%ld): succeeded.\n", | ||
5069 | vha->host_no)); | ||
5070 | list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { | ||
5071 | if (vp->vp_idx) | ||
5072 | qla2x00_vp_abort_isp(vp); | ||
5073 | } | ||
5074 | } else { | ||
5075 | qla_printk(KERN_INFO, ha, | ||
5076 | "qla82xx_restart_isp: **** FAILED ****\n"); | ||
5077 | } | ||
5078 | |||
5079 | return status; | ||
5080 | } | ||
5081 | |||
4901 | void | 5082 | void |
4902 | qla81xx_update_fw_options(scsi_qla_host_t *vha) | 5083 | qla81xx_update_fw_options(scsi_qla_host_t *vha) |
4903 | { | 5084 | { |
diff --git a/drivers/scsi/qla2xxx/qla_inline.h b/drivers/scsi/qla2xxx/qla_inline.h index 5e0a7095c9f2..ad53c6455556 100644 --- a/drivers/scsi/qla2xxx/qla_inline.h +++ b/drivers/scsi/qla2xxx/qla_inline.h | |||
@@ -37,7 +37,10 @@ qla2x00_poll(struct rsp_que *rsp) | |||
37 | unsigned long flags; | 37 | unsigned long flags; |
38 | struct qla_hw_data *ha = rsp->hw; | 38 | struct qla_hw_data *ha = rsp->hw; |
39 | local_irq_save(flags); | 39 | local_irq_save(flags); |
40 | ha->isp_ops->intr_handler(0, rsp); | 40 | if (IS_QLA82XX(ha)) |
41 | qla82xx_poll(0, rsp); | ||
42 | else | ||
43 | ha->isp_ops->intr_handler(0, rsp); | ||
41 | local_irq_restore(flags); | 44 | local_irq_restore(flags); |
42 | } | 45 | } |
43 | 46 | ||
diff --git a/drivers/scsi/qla2xxx/qla_iocb.c b/drivers/scsi/qla2xxx/qla_iocb.c index 8299a9891bfe..d792ae32ed69 100644 --- a/drivers/scsi/qla2xxx/qla_iocb.c +++ b/drivers/scsi/qla2xxx/qla_iocb.c | |||
@@ -506,7 +506,10 @@ qla2x00_req_pkt(struct scsi_qla_host *vha, struct req_que *req, | |||
506 | cnt = (uint16_t) | 506 | cnt = (uint16_t) |
507 | RD_REG_DWORD(®->isp25mq.req_q_out); | 507 | RD_REG_DWORD(®->isp25mq.req_q_out); |
508 | else { | 508 | else { |
509 | if (IS_FWI2_CAPABLE(ha)) | 509 | if (IS_QLA82XX(ha)) |
510 | cnt = (uint16_t)RD_REG_DWORD( | ||
511 | ®->isp82.req_q_out); | ||
512 | else if (IS_FWI2_CAPABLE(ha)) | ||
510 | cnt = (uint16_t)RD_REG_DWORD( | 513 | cnt = (uint16_t)RD_REG_DWORD( |
511 | ®->isp24.req_q_out); | 514 | ®->isp24.req_q_out); |
512 | else | 515 | else |
@@ -579,11 +582,29 @@ qla2x00_isp_cmd(struct scsi_qla_host *vha, struct req_que *req) | |||
579 | req->ring_ptr++; | 582 | req->ring_ptr++; |
580 | 583 | ||
581 | /* Set chip new ring index. */ | 584 | /* Set chip new ring index. */ |
582 | if (ha->mqenable) { | 585 | if (IS_QLA82XX(ha)) { |
586 | uint32_t dbval = 0x04 | (ha->portnum << 5); | ||
587 | |||
588 | /* write, read and verify logic */ | ||
589 | dbval = dbval | (req->id << 8) | (req->ring_index << 16); | ||
590 | if (ql2xdbwr) | ||
591 | qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); | ||
592 | else { | ||
593 | WRT_REG_DWORD( | ||
594 | (unsigned long __iomem *)ha->nxdb_wr_ptr, | ||
595 | dbval); | ||
596 | wmb(); | ||
597 | while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { | ||
598 | WRT_REG_DWORD((unsigned long __iomem *) | ||
599 | ha->nxdb_wr_ptr, dbval); | ||
600 | wmb(); | ||
601 | } | ||
602 | } | ||
603 | } else if (ha->mqenable) { | ||
604 | /* Set chip new ring index. */ | ||
583 | WRT_REG_DWORD(®->isp25mq.req_q_in, req->ring_index); | 605 | WRT_REG_DWORD(®->isp25mq.req_q_in, req->ring_index); |
584 | RD_REG_DWORD(&ioreg->hccr); | 606 | RD_REG_DWORD(&ioreg->hccr); |
585 | } | 607 | } else { |
586 | else { | ||
587 | if (IS_FWI2_CAPABLE(ha)) { | 608 | if (IS_FWI2_CAPABLE(ha)) { |
588 | WRT_REG_DWORD(®->isp24.req_q_in, req->ring_index); | 609 | WRT_REG_DWORD(®->isp24.req_q_in, req->ring_index); |
589 | RD_REG_DWORD_RELAXED(®->isp24.req_q_in); | 610 | RD_REG_DWORD_RELAXED(®->isp24.req_q_in); |
@@ -604,7 +625,7 @@ qla2x00_isp_cmd(struct scsi_qla_host *vha, struct req_que *req) | |||
604 | * | 625 | * |
605 | * Returns the number of IOCB entries needed to store @dsds. | 626 | * Returns the number of IOCB entries needed to store @dsds. |
606 | */ | 627 | */ |
607 | static inline uint16_t | 628 | inline uint16_t |
608 | qla24xx_calc_iocbs(uint16_t dsds) | 629 | qla24xx_calc_iocbs(uint16_t dsds) |
609 | { | 630 | { |
610 | uint16_t iocbs; | 631 | uint16_t iocbs; |
@@ -626,7 +647,7 @@ qla24xx_calc_iocbs(uint16_t dsds) | |||
626 | * @cmd_pkt: Command type 3 IOCB | 647 | * @cmd_pkt: Command type 3 IOCB |
627 | * @tot_dsds: Total number of segments to transfer | 648 | * @tot_dsds: Total number of segments to transfer |
628 | */ | 649 | */ |
629 | static inline void | 650 | inline void |
630 | qla24xx_build_scsi_iocbs(srb_t *sp, struct cmd_type_7 *cmd_pkt, | 651 | qla24xx_build_scsi_iocbs(srb_t *sp, struct cmd_type_7 *cmd_pkt, |
631 | uint16_t tot_dsds) | 652 | uint16_t tot_dsds) |
632 | { | 653 | { |
@@ -931,24 +952,31 @@ qla2x00_start_iocbs(srb_t *sp) | |||
931 | device_reg_t __iomem *reg = ISP_QUE_REG(ha, req->id); | 952 | device_reg_t __iomem *reg = ISP_QUE_REG(ha, req->id); |
932 | struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp; | 953 | struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp; |
933 | 954 | ||
934 | /* Adjust ring index. */ | 955 | if (IS_QLA82XX(ha)) { |
935 | req->ring_index++; | 956 | qla82xx_start_iocbs(sp); |
936 | if (req->ring_index == req->length) { | ||
937 | req->ring_index = 0; | ||
938 | req->ring_ptr = req->ring; | ||
939 | } else | ||
940 | req->ring_ptr++; | ||
941 | |||
942 | /* Set chip new ring index. */ | ||
943 | if (ha->mqenable) { | ||
944 | WRT_REG_DWORD(®->isp25mq.req_q_in, req->ring_index); | ||
945 | RD_REG_DWORD(&ioreg->hccr); | ||
946 | } else if (IS_FWI2_CAPABLE(ha)) { | ||
947 | WRT_REG_DWORD(®->isp24.req_q_in, req->ring_index); | ||
948 | RD_REG_DWORD_RELAXED(®->isp24.req_q_in); | ||
949 | } else { | 957 | } else { |
950 | WRT_REG_WORD(ISP_REQ_Q_IN(ha, ®->isp), req->ring_index); | 958 | /* Adjust ring index. */ |
951 | RD_REG_WORD_RELAXED(ISP_REQ_Q_IN(ha, ®->isp)); | 959 | req->ring_index++; |
960 | if (req->ring_index == req->length) { | ||
961 | req->ring_index = 0; | ||
962 | req->ring_ptr = req->ring; | ||
963 | } else | ||
964 | req->ring_ptr++; | ||
965 | |||
966 | /* Set chip new ring index. */ | ||
967 | if (ha->mqenable) { | ||
968 | WRT_REG_DWORD(®->isp25mq.req_q_in, req->ring_index); | ||
969 | RD_REG_DWORD(&ioreg->hccr); | ||
970 | } else if (IS_QLA82XX(ha)) { | ||
971 | qla82xx_start_iocbs(sp); | ||
972 | } else if (IS_FWI2_CAPABLE(ha)) { | ||
973 | WRT_REG_DWORD(®->isp24.req_q_in, req->ring_index); | ||
974 | RD_REG_DWORD_RELAXED(®->isp24.req_q_in); | ||
975 | } else { | ||
976 | WRT_REG_WORD(ISP_REQ_Q_IN(ha, ®->isp), | ||
977 | req->ring_index); | ||
978 | RD_REG_WORD_RELAXED(ISP_REQ_Q_IN(ha, ®->isp)); | ||
979 | } | ||
952 | } | 980 | } |
953 | } | 981 | } |
954 | 982 | ||
diff --git a/drivers/scsi/qla2xxx/qla_isr.c b/drivers/scsi/qla2xxx/qla_isr.c index db539b0c3dae..f1ac62d505d1 100644 --- a/drivers/scsi/qla2xxx/qla_isr.c +++ b/drivers/scsi/qla2xxx/qla_isr.c | |||
@@ -326,7 +326,7 @@ qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb) | |||
326 | 326 | ||
327 | /* Setup to process RIO completion. */ | 327 | /* Setup to process RIO completion. */ |
328 | handle_cnt = 0; | 328 | handle_cnt = 0; |
329 | if (IS_QLA81XX(ha)) | 329 | if (IS_QLA8XXX_TYPE(ha)) |
330 | goto skip_rio; | 330 | goto skip_rio; |
331 | switch (mb[0]) { | 331 | switch (mb[0]) { |
332 | case MBA_SCSI_COMPLETION: | 332 | case MBA_SCSI_COMPLETION: |
@@ -544,7 +544,7 @@ skip_rio: | |||
544 | if (IS_QLA2100(ha)) | 544 | if (IS_QLA2100(ha)) |
545 | break; | 545 | break; |
546 | 546 | ||
547 | if (IS_QLA81XX(ha)) | 547 | if (IS_QLA8XXX_TYPE(ha)) |
548 | DEBUG2(printk("scsi(%ld): DCBX Completed -- %04x %04x " | 548 | DEBUG2(printk("scsi(%ld): DCBX Completed -- %04x %04x " |
549 | "%04x\n", vha->host_no, mb[1], mb[2], mb[3])); | 549 | "%04x\n", vha->host_no, mb[1], mb[2], mb[3])); |
550 | else | 550 | else |
@@ -845,7 +845,7 @@ qla2x00_process_completed_request(struct scsi_qla_host *vha, | |||
845 | qla2x00_sp_compl(ha, sp); | 845 | qla2x00_sp_compl(ha, sp); |
846 | } else { | 846 | } else { |
847 | DEBUG2(printk("scsi(%ld) Req:%d: Invalid ISP SCSI completion" | 847 | DEBUG2(printk("scsi(%ld) Req:%d: Invalid ISP SCSI completion" |
848 | " handle(%d)\n", vha->host_no, req->id, index)); | 848 | " handle(0x%x)\n", vha->host_no, req->id, index)); |
849 | qla_printk(KERN_WARNING, ha, | 849 | qla_printk(KERN_WARNING, ha, |
850 | "Invalid ISP SCSI completion handle\n"); | 850 | "Invalid ISP SCSI completion handle\n"); |
851 | 851 | ||
@@ -1337,6 +1337,7 @@ qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt) | |||
1337 | handle = (uint32_t) LSW(sts->handle); | 1337 | handle = (uint32_t) LSW(sts->handle); |
1338 | que = MSW(sts->handle); | 1338 | que = MSW(sts->handle); |
1339 | req = ha->req_q_map[que]; | 1339 | req = ha->req_q_map[que]; |
1340 | |||
1340 | /* Fast path completion. */ | 1341 | /* Fast path completion. */ |
1341 | if (comp_status == CS_COMPLETE && scsi_status == 0) { | 1342 | if (comp_status == CS_COMPLETE && scsi_status == 0) { |
1342 | qla2x00_process_completed_request(vha, req, handle); | 1343 | qla2x00_process_completed_request(vha, req, handle); |
@@ -1806,6 +1807,7 @@ void qla24xx_process_response_queue(struct scsi_qla_host *vha, | |||
1806 | struct rsp_que *rsp) | 1807 | struct rsp_que *rsp) |
1807 | { | 1808 | { |
1808 | struct sts_entry_24xx *pkt; | 1809 | struct sts_entry_24xx *pkt; |
1810 | struct qla_hw_data *ha = vha->hw; | ||
1809 | 1811 | ||
1810 | if (!vha->flags.online) | 1812 | if (!vha->flags.online) |
1811 | return; | 1813 | return; |
@@ -1866,7 +1868,11 @@ void qla24xx_process_response_queue(struct scsi_qla_host *vha, | |||
1866 | } | 1868 | } |
1867 | 1869 | ||
1868 | /* Adjust ring index */ | 1870 | /* Adjust ring index */ |
1869 | WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index); | 1871 | if (IS_QLA82XX(ha)) { |
1872 | struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; | ||
1873 | WRT_REG_DWORD(®->rsp_q_out[0], rsp->ring_index); | ||
1874 | } else | ||
1875 | WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index); | ||
1870 | } | 1876 | } |
1871 | 1877 | ||
1872 | static void | 1878 | static void |
@@ -2169,6 +2175,11 @@ static struct qla_init_msix_entry msix_entries[3] = { | |||
2169 | { "qla2xxx (multiq)", qla25xx_msix_rsp_q }, | 2175 | { "qla2xxx (multiq)", qla25xx_msix_rsp_q }, |
2170 | }; | 2176 | }; |
2171 | 2177 | ||
2178 | static struct qla_init_msix_entry qla82xx_msix_entries[2] = { | ||
2179 | { "qla2xxx (default)", qla82xx_msix_default }, | ||
2180 | { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q }, | ||
2181 | }; | ||
2182 | |||
2172 | static void | 2183 | static void |
2173 | qla24xx_disable_msix(struct qla_hw_data *ha) | 2184 | qla24xx_disable_msix(struct qla_hw_data *ha) |
2174 | { | 2185 | { |
@@ -2195,7 +2206,7 @@ qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp) | |||
2195 | struct qla_msix_entry *qentry; | 2206 | struct qla_msix_entry *qentry; |
2196 | 2207 | ||
2197 | entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count, | 2208 | entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count, |
2198 | GFP_KERNEL); | 2209 | GFP_KERNEL); |
2199 | if (!entries) | 2210 | if (!entries) |
2200 | return -ENOMEM; | 2211 | return -ENOMEM; |
2201 | 2212 | ||
@@ -2240,8 +2251,15 @@ msix_failed: | |||
2240 | /* Enable MSI-X vectors for the base queue */ | 2251 | /* Enable MSI-X vectors for the base queue */ |
2241 | for (i = 0; i < 2; i++) { | 2252 | for (i = 0; i < 2; i++) { |
2242 | qentry = &ha->msix_entries[i]; | 2253 | qentry = &ha->msix_entries[i]; |
2243 | ret = request_irq(qentry->vector, msix_entries[i].handler, | 2254 | if (IS_QLA82XX(ha)) { |
2244 | 0, msix_entries[i].name, rsp); | 2255 | ret = request_irq(qentry->vector, |
2256 | qla82xx_msix_entries[i].handler, | ||
2257 | 0, qla82xx_msix_entries[i].name, rsp); | ||
2258 | } else { | ||
2259 | ret = request_irq(qentry->vector, | ||
2260 | msix_entries[i].handler, | ||
2261 | 0, msix_entries[i].name, rsp); | ||
2262 | } | ||
2245 | if (ret) { | 2263 | if (ret) { |
2246 | qla_printk(KERN_WARNING, ha, | 2264 | qla_printk(KERN_WARNING, ha, |
2247 | "MSI-X: Unable to register handler -- %x/%d.\n", | 2265 | "MSI-X: Unable to register handler -- %x/%d.\n", |
@@ -2272,7 +2290,7 @@ qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp) | |||
2272 | 2290 | ||
2273 | /* If possible, enable MSI-X. */ | 2291 | /* If possible, enable MSI-X. */ |
2274 | if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && | 2292 | if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && |
2275 | !IS_QLA8432(ha) && !IS_QLA8001(ha)) | 2293 | !IS_QLA8432(ha) && !IS_QLA8XXX_TYPE(ha)) |
2276 | goto skip_msi; | 2294 | goto skip_msi; |
2277 | 2295 | ||
2278 | if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP && | 2296 | if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP && |
@@ -2302,7 +2320,7 @@ qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp) | |||
2302 | goto clear_risc_ints; | 2320 | goto clear_risc_ints; |
2303 | } | 2321 | } |
2304 | qla_printk(KERN_WARNING, ha, | 2322 | qla_printk(KERN_WARNING, ha, |
2305 | "MSI-X: Falling back-to INTa mode -- %d.\n", ret); | 2323 | "MSI-X: Falling back-to MSI mode -- %d.\n", ret); |
2306 | skip_msix: | 2324 | skip_msix: |
2307 | 2325 | ||
2308 | if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) && | 2326 | if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) && |
@@ -2313,7 +2331,9 @@ skip_msix: | |||
2313 | if (!ret) { | 2331 | if (!ret) { |
2314 | DEBUG2(qla_printk(KERN_INFO, ha, "MSI: Enabled.\n")); | 2332 | DEBUG2(qla_printk(KERN_INFO, ha, "MSI: Enabled.\n")); |
2315 | ha->flags.msi_enabled = 1; | 2333 | ha->flags.msi_enabled = 1; |
2316 | } | 2334 | } else |
2335 | qla_printk(KERN_WARNING, ha, | ||
2336 | "MSI-X: Falling back-to INTa mode -- %d.\n", ret); | ||
2317 | skip_msi: | 2337 | skip_msi: |
2318 | 2338 | ||
2319 | ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler, | 2339 | ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler, |
@@ -2331,7 +2351,7 @@ clear_risc_ints: | |||
2331 | * FIXME: Noted that 8014s were being dropped during NK testing. | 2351 | * FIXME: Noted that 8014s were being dropped during NK testing. |
2332 | * Timing deltas during MSI-X/INTa transitions? | 2352 | * Timing deltas during MSI-X/INTa transitions? |
2333 | */ | 2353 | */ |
2334 | if (IS_QLA81XX(ha)) | 2354 | if (IS_QLA81XX(ha) || IS_QLA82XX(ha)) |
2335 | goto fail; | 2355 | goto fail; |
2336 | spin_lock_irq(&ha->hardware_lock); | 2356 | spin_lock_irq(&ha->hardware_lock); |
2337 | if (IS_FWI2_CAPABLE(ha)) { | 2357 | if (IS_FWI2_CAPABLE(ha)) { |
diff --git a/drivers/scsi/qla2xxx/qla_mbx.c b/drivers/scsi/qla2xxx/qla_mbx.c index bce6cd47e3c3..2f3033228061 100644 --- a/drivers/scsi/qla2xxx/qla_mbx.c +++ b/drivers/scsi/qla2xxx/qla_mbx.c | |||
@@ -49,6 +49,14 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp) | |||
49 | if (ha->pdev->error_state > pci_channel_io_frozen) | 49 | if (ha->pdev->error_state > pci_channel_io_frozen) |
50 | return QLA_FUNCTION_TIMEOUT; | 50 | return QLA_FUNCTION_TIMEOUT; |
51 | 51 | ||
52 | if (vha->device_flags & DFLG_DEV_FAILED) { | ||
53 | DEBUG2_3_11(qla_printk(KERN_WARNING, ha, | ||
54 | "%s(%ld): Device in failed state, " | ||
55 | "timeout MBX Exiting.\n", | ||
56 | __func__, base_vha->host_no)); | ||
57 | return QLA_FUNCTION_TIMEOUT; | ||
58 | } | ||
59 | |||
52 | reg = ha->iobase; | 60 | reg = ha->iobase; |
53 | io_lock_on = base_vha->flags.init_done; | 61 | io_lock_on = base_vha->flags.init_done; |
54 | 62 | ||
@@ -85,7 +93,9 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp) | |||
85 | spin_lock_irqsave(&ha->hardware_lock, flags); | 93 | spin_lock_irqsave(&ha->hardware_lock, flags); |
86 | 94 | ||
87 | /* Load mailbox registers. */ | 95 | /* Load mailbox registers. */ |
88 | if (IS_FWI2_CAPABLE(ha)) | 96 | if (IS_QLA82XX(ha)) |
97 | optr = (uint16_t __iomem *)®->isp82.mailbox_in[0]; | ||
98 | else if (IS_FWI2_CAPABLE(ha) && !IS_QLA82XX(ha)) | ||
89 | optr = (uint16_t __iomem *)®->isp24.mailbox0; | 99 | optr = (uint16_t __iomem *)®->isp24.mailbox0; |
90 | else | 100 | else |
91 | optr = (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 0); | 101 | optr = (uint16_t __iomem *)MAILBOX_REG(ha, ®->isp, 0); |
@@ -133,7 +143,18 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp) | |||
133 | if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) { | 143 | if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) { |
134 | set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); | 144 | set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); |
135 | 145 | ||
136 | if (IS_FWI2_CAPABLE(ha)) | 146 | if (IS_QLA82XX(ha)) { |
147 | if (RD_REG_DWORD(®->isp82.hint) & | ||
148 | HINT_MBX_INT_PENDING) { | ||
149 | spin_unlock_irqrestore(&ha->hardware_lock, | ||
150 | flags); | ||
151 | DEBUG2_3_11(printk(KERN_INFO | ||
152 | "%s(%ld): Pending Mailbox timeout. " | ||
153 | "Exiting.\n", __func__, base_vha->host_no)); | ||
154 | return QLA_FUNCTION_TIMEOUT; | ||
155 | } | ||
156 | WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); | ||
157 | } else if (IS_FWI2_CAPABLE(ha)) | ||
137 | WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); | 158 | WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); |
138 | else | 159 | else |
139 | WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); | 160 | WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); |
@@ -147,7 +168,18 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp) | |||
147 | DEBUG3_11(printk("%s(%ld): cmd=%x POLLING MODE.\n", __func__, | 168 | DEBUG3_11(printk("%s(%ld): cmd=%x POLLING MODE.\n", __func__, |
148 | base_vha->host_no, command)); | 169 | base_vha->host_no, command)); |
149 | 170 | ||
150 | if (IS_FWI2_CAPABLE(ha)) | 171 | if (IS_QLA82XX(ha)) { |
172 | if (RD_REG_DWORD(®->isp82.hint) & | ||
173 | HINT_MBX_INT_PENDING) { | ||
174 | spin_unlock_irqrestore(&ha->hardware_lock, | ||
175 | flags); | ||
176 | DEBUG2_3_11(printk(KERN_INFO | ||
177 | "%s(%ld): Pending Mailbox timeout. " | ||
178 | "Exiting.\n", __func__, base_vha->host_no)); | ||
179 | return QLA_FUNCTION_TIMEOUT; | ||
180 | } | ||
181 | WRT_REG_DWORD(®->isp82.hint, HINT_MBX_INT_PENDING); | ||
182 | } else if (IS_FWI2_CAPABLE(ha)) | ||
151 | WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); | 183 | WRT_REG_DWORD(®->isp24.hccr, HCCRX_SET_HOST_INT); |
152 | else | 184 | else |
153 | WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); | 185 | WRT_REG_WORD(®->isp.hccr, HCCR_SET_HOST_INT); |
@@ -264,7 +296,7 @@ qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp) | |||
264 | 296 | ||
265 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | 297 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
266 | clear_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); | 298 | clear_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); |
267 | if (qla2x00_abort_isp(base_vha)) { | 299 | if (ha->isp_ops->abort_isp(base_vha)) { |
268 | /* Failed. retry later. */ | 300 | /* Failed. retry later. */ |
269 | set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); | 301 | set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); |
270 | } | 302 | } |
@@ -952,7 +984,7 @@ qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa, | |||
952 | mcp->mb[9] = vha->vp_idx; | 984 | mcp->mb[9] = vha->vp_idx; |
953 | mcp->out_mb = MBX_9|MBX_0; | 985 | mcp->out_mb = MBX_9|MBX_0; |
954 | mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; | 986 | mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0; |
955 | if (IS_QLA81XX(vha->hw)) | 987 | if (IS_QLA8XXX_TYPE(vha->hw)) |
956 | mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10; | 988 | mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10; |
957 | mcp->tov = MBX_TOV_SECONDS; | 989 | mcp->tov = MBX_TOV_SECONDS; |
958 | mcp->flags = 0; | 990 | mcp->flags = 0; |
@@ -978,7 +1010,7 @@ qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa, | |||
978 | DEBUG11(printk("qla2x00_get_adapter_id(%ld): done.\n", | 1010 | DEBUG11(printk("qla2x00_get_adapter_id(%ld): done.\n", |
979 | vha->host_no)); | 1011 | vha->host_no)); |
980 | 1012 | ||
981 | if (IS_QLA81XX(vha->hw)) { | 1013 | if (IS_QLA8XXX_TYPE(vha->hw)) { |
982 | vha->fcoe_vlan_id = mcp->mb[9] & 0xfff; | 1014 | vha->fcoe_vlan_id = mcp->mb[9] & 0xfff; |
983 | vha->fcoe_fcf_idx = mcp->mb[10]; | 1015 | vha->fcoe_fcf_idx = mcp->mb[10]; |
984 | vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8; | 1016 | vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8; |
@@ -1076,6 +1108,10 @@ qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size) | |||
1076 | DEBUG11(printk("qla2x00_init_firmware(%ld): entered.\n", | 1108 | DEBUG11(printk("qla2x00_init_firmware(%ld): entered.\n", |
1077 | vha->host_no)); | 1109 | vha->host_no)); |
1078 | 1110 | ||
1111 | if (IS_QLA82XX(ha) && ql2xdbwr) | ||
1112 | qla82xx_wr_32(ha, ha->nxdb_wr_ptr, | ||
1113 | (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16))); | ||
1114 | |||
1079 | if (ha->flags.npiv_supported) | 1115 | if (ha->flags.npiv_supported) |
1080 | mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE; | 1116 | mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE; |
1081 | else | 1117 | else |
@@ -1408,7 +1444,7 @@ qla2x00_lip_reset(scsi_qla_host_t *vha) | |||
1408 | 1444 | ||
1409 | DEBUG11(printk("%s(%ld): entered.\n", __func__, vha->host_no)); | 1445 | DEBUG11(printk("%s(%ld): entered.\n", __func__, vha->host_no)); |
1410 | 1446 | ||
1411 | if (IS_QLA81XX(vha->hw)) { | 1447 | if (IS_QLA8XXX_TYPE(vha->hw)) { |
1412 | /* Logout across all FCFs. */ | 1448 | /* Logout across all FCFs. */ |
1413 | mcp->mb[0] = MBC_LIP_FULL_LOGIN; | 1449 | mcp->mb[0] = MBC_LIP_FULL_LOGIN; |
1414 | mcp->mb[1] = BIT_1; | 1450 | mcp->mb[1] = BIT_1; |
@@ -2797,7 +2833,7 @@ qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id, | |||
2797 | mcp->mb[0] = MBC_PORT_PARAMS; | 2833 | mcp->mb[0] = MBC_PORT_PARAMS; |
2798 | mcp->mb[1] = loop_id; | 2834 | mcp->mb[1] = loop_id; |
2799 | mcp->mb[2] = BIT_0; | 2835 | mcp->mb[2] = BIT_0; |
2800 | if (IS_QLA81XX(vha->hw)) | 2836 | if (IS_QLA8XXX_TYPE(vha->hw)) |
2801 | mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0); | 2837 | mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0); |
2802 | else | 2838 | else |
2803 | mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0); | 2839 | mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0); |
@@ -3586,7 +3622,7 @@ qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma, | |||
3586 | mbx_cmd_t mc; | 3622 | mbx_cmd_t mc; |
3587 | mbx_cmd_t *mcp = &mc; | 3623 | mbx_cmd_t *mcp = &mc; |
3588 | 3624 | ||
3589 | if (!IS_QLA81XX(vha->hw)) | 3625 | if (!IS_QLA8XXX_TYPE(vha->hw)) |
3590 | return QLA_FUNCTION_FAILED; | 3626 | return QLA_FUNCTION_FAILED; |
3591 | 3627 | ||
3592 | DEBUG11(printk("%s(%ld): entered.\n", __func__, vha->host_no)); | 3628 | DEBUG11(printk("%s(%ld): entered.\n", __func__, vha->host_no)); |
@@ -3624,7 +3660,7 @@ qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma, | |||
3624 | mbx_cmd_t mc; | 3660 | mbx_cmd_t mc; |
3625 | mbx_cmd_t *mcp = &mc; | 3661 | mbx_cmd_t *mcp = &mc; |
3626 | 3662 | ||
3627 | if (!IS_QLA81XX(vha->hw)) | 3663 | if (!IS_QLA8XXX_TYPE(vha->hw)) |
3628 | return QLA_FUNCTION_FAILED; | 3664 | return QLA_FUNCTION_FAILED; |
3629 | 3665 | ||
3630 | DEBUG11(printk("%s(%ld): entered.\n", __func__, vha->host_no)); | 3666 | DEBUG11(printk("%s(%ld): entered.\n", __func__, vha->host_no)); |
@@ -3685,7 +3721,8 @@ qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data) | |||
3685 | } | 3721 | } |
3686 | 3722 | ||
3687 | int | 3723 | int |
3688 | qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, uint16_t *mresp) | 3724 | qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, |
3725 | uint16_t *mresp) | ||
3689 | { | 3726 | { |
3690 | int rval; | 3727 | int rval; |
3691 | mbx_cmd_t mc; | 3728 | mbx_cmd_t mc; |
@@ -3720,7 +3757,7 @@ qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, uint16_t * | |||
3720 | 3757 | ||
3721 | mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15| | 3758 | mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15| |
3722 | MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; | 3759 | MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; |
3723 | if (IS_QLA81XX(vha->hw)) | 3760 | if (IS_QLA8XXX_TYPE(vha->hw)) |
3724 | mcp->out_mb |= MBX_2; | 3761 | mcp->out_mb |= MBX_2; |
3725 | mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0; | 3762 | mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0; |
3726 | 3763 | ||
@@ -3732,9 +3769,11 @@ qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, uint16_t * | |||
3732 | 3769 | ||
3733 | if (rval != QLA_SUCCESS) { | 3770 | if (rval != QLA_SUCCESS) { |
3734 | DEBUG2(printk(KERN_WARNING | 3771 | DEBUG2(printk(KERN_WARNING |
3735 | "(%ld): failed=%x mb[0]=0x%x " | 3772 | "(%ld): failed=%x mb[0]=0x%x " |
3736 | "mb[1]=0x%x mb[2]=0x%x mb[3]=0x%x mb[18]=0x%x mb[19]=0x%x. \n", vha->host_no, rval, | 3773 | "mb[1]=0x%x mb[2]=0x%x mb[3]=0x%x mb[18]=0x%x " |
3737 | mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], mcp->mb[18], mcp->mb[19])); | 3774 | "mb[19]=0x%x.\n", |
3775 | vha->host_no, rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], | ||
3776 | mcp->mb[3], mcp->mb[18], mcp->mb[19])); | ||
3738 | } else { | 3777 | } else { |
3739 | DEBUG2(printk(KERN_WARNING | 3778 | DEBUG2(printk(KERN_WARNING |
3740 | "scsi(%ld): done.\n", vha->host_no)); | 3779 | "scsi(%ld): done.\n", vha->host_no)); |
@@ -3748,7 +3787,8 @@ qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, uint16_t * | |||
3748 | } | 3787 | } |
3749 | 3788 | ||
3750 | int | 3789 | int |
3751 | qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, uint16_t *mresp) | 3790 | qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, |
3791 | uint16_t *mresp) | ||
3752 | { | 3792 | { |
3753 | int rval; | 3793 | int rval; |
3754 | mbx_cmd_t mc; | 3794 | mbx_cmd_t mc; |
@@ -3760,9 +3800,10 @@ qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, uint16_t *mres | |||
3760 | memset(mcp->mb, 0 , sizeof(mcp->mb)); | 3800 | memset(mcp->mb, 0 , sizeof(mcp->mb)); |
3761 | mcp->mb[0] = MBC_DIAGNOSTIC_ECHO; | 3801 | mcp->mb[0] = MBC_DIAGNOSTIC_ECHO; |
3762 | mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */ | 3802 | mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */ |
3763 | if (IS_QLA81XX(ha)) | 3803 | if (IS_QLA8XXX_TYPE(ha)) { |
3764 | mcp->mb[1] |= BIT_15; | 3804 | mcp->mb[1] |= BIT_15; |
3765 | mcp->mb[2] = IS_QLA81XX(ha) ? vha->fcoe_fcf_idx : 0; | 3805 | mcp->mb[2] = vha->fcoe_fcf_idx; |
3806 | } | ||
3766 | mcp->mb[16] = LSW(mreq->rcv_dma); | 3807 | mcp->mb[16] = LSW(mreq->rcv_dma); |
3767 | mcp->mb[17] = MSW(mreq->rcv_dma); | 3808 | mcp->mb[17] = MSW(mreq->rcv_dma); |
3768 | mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); | 3809 | mcp->mb[6] = LSW(MSD(mreq->rcv_dma)); |
@@ -3777,13 +3818,13 @@ qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq, uint16_t *mres | |||
3777 | 3818 | ||
3778 | mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15| | 3819 | mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15| |
3779 | MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; | 3820 | MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0; |
3780 | if (IS_QLA81XX(ha)) | 3821 | if (IS_QLA8XXX_TYPE(ha)) |
3781 | mcp->out_mb |= MBX_2; | 3822 | mcp->out_mb |= MBX_2; |
3782 | 3823 | ||
3783 | mcp->in_mb = MBX_0; | 3824 | mcp->in_mb = MBX_0; |
3784 | if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha)) | 3825 | if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) || IS_QLA8XXX_TYPE(ha)) |
3785 | mcp->in_mb |= MBX_1; | 3826 | mcp->in_mb |= MBX_1; |
3786 | if (IS_QLA81XX(ha)) | 3827 | if (IS_QLA8XXX_TYPE(ha)) |
3787 | mcp->in_mb |= MBX_3; | 3828 | mcp->in_mb |= MBX_3; |
3788 | 3829 | ||
3789 | mcp->tov = MBX_TOV_SECONDS; | 3830 | mcp->tov = MBX_TOV_SECONDS; |
@@ -3875,7 +3916,8 @@ qla2x00_get_data_rate(scsi_qla_host_t *vha) | |||
3875 | if (!IS_FWI2_CAPABLE(ha)) | 3916 | if (!IS_FWI2_CAPABLE(ha)) |
3876 | return QLA_FUNCTION_FAILED; | 3917 | return QLA_FUNCTION_FAILED; |
3877 | 3918 | ||
3878 | DEBUG11(printk(KERN_INFO "%s(%ld): entered.\n", __func__, vha->host_no)); | 3919 | DEBUG11(qla_printk(KERN_INFO, ha, |
3920 | "%s(%ld): entered.\n", __func__, vha->host_no)); | ||
3879 | 3921 | ||
3880 | mcp->mb[0] = MBC_DATA_RATE; | 3922 | mcp->mb[0] = MBC_DATA_RATE; |
3881 | mcp->mb[1] = 0; | 3923 | mcp->mb[1] = 0; |
@@ -3943,3 +3985,75 @@ qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority, | |||
3943 | 3985 | ||
3944 | return rval; | 3986 | return rval; |
3945 | } | 3987 | } |
3988 | |||
3989 | int | ||
3990 | qla82xx_mbx_intr_enable(scsi_qla_host_t *vha) | ||
3991 | { | ||
3992 | int rval; | ||
3993 | struct qla_hw_data *ha = vha->hw; | ||
3994 | mbx_cmd_t mc; | ||
3995 | mbx_cmd_t *mcp = &mc; | ||
3996 | |||
3997 | if (!IS_FWI2_CAPABLE(ha)) | ||
3998 | return QLA_FUNCTION_FAILED; | ||
3999 | |||
4000 | DEBUG11(qla_printk(KERN_INFO, ha, | ||
4001 | "%s(%ld): entered.\n", __func__, vha->host_no)); | ||
4002 | |||
4003 | memset(mcp, 0, sizeof(mbx_cmd_t)); | ||
4004 | mcp->mb[0] = MBC_TOGGLE_INTR; | ||
4005 | mcp->mb[1] = 1; | ||
4006 | |||
4007 | mcp->out_mb = MBX_1|MBX_0; | ||
4008 | mcp->in_mb = MBX_0; | ||
4009 | mcp->tov = 30; | ||
4010 | mcp->flags = 0; | ||
4011 | |||
4012 | rval = qla2x00_mailbox_command(vha, mcp); | ||
4013 | if (rval != QLA_SUCCESS) { | ||
4014 | DEBUG2_3_11(qla_printk(KERN_WARNING, ha, | ||
4015 | "%s(%ld): failed=%x mb[0]=%x.\n", __func__, | ||
4016 | vha->host_no, rval, mcp->mb[0])); | ||
4017 | } else { | ||
4018 | DEBUG11(qla_printk(KERN_INFO, ha, | ||
4019 | "%s(%ld): done.\n", __func__, vha->host_no)); | ||
4020 | } | ||
4021 | |||
4022 | return rval; | ||
4023 | } | ||
4024 | |||
4025 | int | ||
4026 | qla82xx_mbx_intr_disable(scsi_qla_host_t *vha) | ||
4027 | { | ||
4028 | int rval; | ||
4029 | struct qla_hw_data *ha = vha->hw; | ||
4030 | mbx_cmd_t mc; | ||
4031 | mbx_cmd_t *mcp = &mc; | ||
4032 | |||
4033 | if (!IS_QLA82XX(ha)) | ||
4034 | return QLA_FUNCTION_FAILED; | ||
4035 | |||
4036 | DEBUG11(qla_printk(KERN_INFO, ha, | ||
4037 | "%s(%ld): entered.\n", __func__, vha->host_no)); | ||
4038 | |||
4039 | memset(mcp, 0, sizeof(mbx_cmd_t)); | ||
4040 | mcp->mb[0] = MBC_TOGGLE_INTR; | ||
4041 | mcp->mb[1] = 0; | ||
4042 | |||
4043 | mcp->out_mb = MBX_1|MBX_0; | ||
4044 | mcp->in_mb = MBX_0; | ||
4045 | mcp->tov = 30; | ||
4046 | mcp->flags = 0; | ||
4047 | |||
4048 | rval = qla2x00_mailbox_command(vha, mcp); | ||
4049 | if (rval != QLA_SUCCESS) { | ||
4050 | DEBUG2_3_11(qla_printk(KERN_WARNING, ha, | ||
4051 | "%s(%ld): failed=%x mb[0]=%x.\n", __func__, | ||
4052 | vha->host_no, rval, mcp->mb[0])); | ||
4053 | } else { | ||
4054 | DEBUG11(qla_printk(KERN_INFO, ha, | ||
4055 | "%s(%ld): done.\n", __func__, vha->host_no)); | ||
4056 | } | ||
4057 | |||
4058 | return rval; | ||
4059 | } | ||
diff --git a/drivers/scsi/qla2xxx/qla_nx.c b/drivers/scsi/qla2xxx/qla_nx.c new file mode 100644 index 000000000000..495ff1ade36e --- /dev/null +++ b/drivers/scsi/qla2xxx/qla_nx.c | |||
@@ -0,0 +1,3635 @@ | |||
1 | /* | ||
2 | * QLogic Fibre Channel HBA Driver | ||
3 | * Copyright (c) 2003-2008 QLogic Corporation | ||
4 | * | ||
5 | * See LICENSE.qla2xxx for copyright and licensing details. | ||
6 | */ | ||
7 | #include "qla_def.h" | ||
8 | #include <linux/delay.h> | ||
9 | #include <linux/pci.h> | ||
10 | |||
11 | #define MASK(n) ((1ULL<<(n))-1) | ||
12 | #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \ | ||
13 | ((addr >> 25) & 0x3ff)) | ||
14 | #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \ | ||
15 | ((addr >> 25) & 0x3ff)) | ||
16 | #define MS_WIN(addr) (addr & 0x0ffc0000) | ||
17 | #define QLA82XX_PCI_MN_2M (0) | ||
18 | #define QLA82XX_PCI_MS_2M (0x80000) | ||
19 | #define QLA82XX_PCI_OCM0_2M (0xc0000) | ||
20 | #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800) | ||
21 | #define GET_MEM_OFFS_2M(addr) (addr & MASK(18)) | ||
22 | |||
23 | /* CRB window related */ | ||
24 | #define CRB_BLK(off) ((off >> 20) & 0x3f) | ||
25 | #define CRB_SUBBLK(off) ((off >> 16) & 0xf) | ||
26 | #define CRB_WINDOW_2M (0x130060) | ||
27 | #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL) | ||
28 | #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \ | ||
29 | ((off) & 0xf0000)) | ||
30 | #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL) | ||
31 | #define CRB_INDIRECT_2M (0x1e0000UL) | ||
32 | |||
33 | static inline void *qla82xx_pci_base_offsetfset(struct qla_hw_data *ha, | ||
34 | unsigned long off) | ||
35 | { | ||
36 | if ((off < ha->first_page_group_end) && | ||
37 | (off >= ha->first_page_group_start)) | ||
38 | return (void *)(ha->nx_pcibase + off); | ||
39 | |||
40 | return NULL; | ||
41 | } | ||
42 | |||
43 | #define MAX_CRB_XFORM 60 | ||
44 | static unsigned long crb_addr_xform[MAX_CRB_XFORM]; | ||
45 | int qla82xx_crb_table_initialized; | ||
46 | |||
47 | #define qla82xx_crb_addr_transform(name) \ | ||
48 | (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \ | ||
49 | QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20) | ||
50 | |||
51 | static void qla82xx_crb_addr_transform_setup(void) | ||
52 | { | ||
53 | qla82xx_crb_addr_transform(XDMA); | ||
54 | qla82xx_crb_addr_transform(TIMR); | ||
55 | qla82xx_crb_addr_transform(SRE); | ||
56 | qla82xx_crb_addr_transform(SQN3); | ||
57 | qla82xx_crb_addr_transform(SQN2); | ||
58 | qla82xx_crb_addr_transform(SQN1); | ||
59 | qla82xx_crb_addr_transform(SQN0); | ||
60 | qla82xx_crb_addr_transform(SQS3); | ||
61 | qla82xx_crb_addr_transform(SQS2); | ||
62 | qla82xx_crb_addr_transform(SQS1); | ||
63 | qla82xx_crb_addr_transform(SQS0); | ||
64 | qla82xx_crb_addr_transform(RPMX7); | ||
65 | qla82xx_crb_addr_transform(RPMX6); | ||
66 | qla82xx_crb_addr_transform(RPMX5); | ||
67 | qla82xx_crb_addr_transform(RPMX4); | ||
68 | qla82xx_crb_addr_transform(RPMX3); | ||
69 | qla82xx_crb_addr_transform(RPMX2); | ||
70 | qla82xx_crb_addr_transform(RPMX1); | ||
71 | qla82xx_crb_addr_transform(RPMX0); | ||
72 | qla82xx_crb_addr_transform(ROMUSB); | ||
73 | qla82xx_crb_addr_transform(SN); | ||
74 | qla82xx_crb_addr_transform(QMN); | ||
75 | qla82xx_crb_addr_transform(QMS); | ||
76 | qla82xx_crb_addr_transform(PGNI); | ||
77 | qla82xx_crb_addr_transform(PGND); | ||
78 | qla82xx_crb_addr_transform(PGN3); | ||
79 | qla82xx_crb_addr_transform(PGN2); | ||
80 | qla82xx_crb_addr_transform(PGN1); | ||
81 | qla82xx_crb_addr_transform(PGN0); | ||
82 | qla82xx_crb_addr_transform(PGSI); | ||
83 | qla82xx_crb_addr_transform(PGSD); | ||
84 | qla82xx_crb_addr_transform(PGS3); | ||
85 | qla82xx_crb_addr_transform(PGS2); | ||
86 | qla82xx_crb_addr_transform(PGS1); | ||
87 | qla82xx_crb_addr_transform(PGS0); | ||
88 | qla82xx_crb_addr_transform(PS); | ||
89 | qla82xx_crb_addr_transform(PH); | ||
90 | qla82xx_crb_addr_transform(NIU); | ||
91 | qla82xx_crb_addr_transform(I2Q); | ||
92 | qla82xx_crb_addr_transform(EG); | ||
93 | qla82xx_crb_addr_transform(MN); | ||
94 | qla82xx_crb_addr_transform(MS); | ||
95 | qla82xx_crb_addr_transform(CAS2); | ||
96 | qla82xx_crb_addr_transform(CAS1); | ||
97 | qla82xx_crb_addr_transform(CAS0); | ||
98 | qla82xx_crb_addr_transform(CAM); | ||
99 | qla82xx_crb_addr_transform(C2C1); | ||
100 | qla82xx_crb_addr_transform(C2C0); | ||
101 | qla82xx_crb_addr_transform(SMB); | ||
102 | qla82xx_crb_addr_transform(OCM0); | ||
103 | /* | ||
104 | * Used only in P3 just define it for P2 also. | ||
105 | */ | ||
106 | qla82xx_crb_addr_transform(I2C0); | ||
107 | |||
108 | qla82xx_crb_table_initialized = 1; | ||
109 | } | ||
110 | |||
111 | struct crb_128M_2M_block_map crb_128M_2M_map[64] = { | ||
112 | {{{0, 0, 0, 0} } }, | ||
113 | {{{1, 0x0100000, 0x0102000, 0x120000}, | ||
114 | {1, 0x0110000, 0x0120000, 0x130000}, | ||
115 | {1, 0x0120000, 0x0122000, 0x124000}, | ||
116 | {1, 0x0130000, 0x0132000, 0x126000}, | ||
117 | {1, 0x0140000, 0x0142000, 0x128000}, | ||
118 | {1, 0x0150000, 0x0152000, 0x12a000}, | ||
119 | {1, 0x0160000, 0x0170000, 0x110000}, | ||
120 | {1, 0x0170000, 0x0172000, 0x12e000}, | ||
121 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
122 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
123 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
124 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
125 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
126 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
127 | {1, 0x01e0000, 0x01e0800, 0x122000}, | ||
128 | {0, 0x0000000, 0x0000000, 0x000000} } } , | ||
129 | {{{1, 0x0200000, 0x0210000, 0x180000} } }, | ||
130 | {{{0, 0, 0, 0} } }, | ||
131 | {{{1, 0x0400000, 0x0401000, 0x169000} } }, | ||
132 | {{{1, 0x0500000, 0x0510000, 0x140000} } }, | ||
133 | {{{1, 0x0600000, 0x0610000, 0x1c0000} } }, | ||
134 | {{{1, 0x0700000, 0x0704000, 0x1b8000} } }, | ||
135 | {{{1, 0x0800000, 0x0802000, 0x170000}, | ||
136 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
137 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
138 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
139 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
140 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
141 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
142 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
143 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
144 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
145 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
146 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
147 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
148 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
149 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
150 | {1, 0x08f0000, 0x08f2000, 0x172000} } }, | ||
151 | {{{1, 0x0900000, 0x0902000, 0x174000}, | ||
152 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
153 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
154 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
155 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
156 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
157 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
158 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
159 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
160 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
161 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
162 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
163 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
164 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
165 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
166 | {1, 0x09f0000, 0x09f2000, 0x176000} } }, | ||
167 | {{{0, 0x0a00000, 0x0a02000, 0x178000}, | ||
168 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
169 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
170 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
171 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
172 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
173 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
174 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
175 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
176 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
177 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
178 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
179 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
180 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
181 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
182 | {1, 0x0af0000, 0x0af2000, 0x17a000} } }, | ||
183 | {{{0, 0x0b00000, 0x0b02000, 0x17c000}, | ||
184 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
185 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
186 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
187 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
188 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
189 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
190 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
191 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
192 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
193 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
194 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
195 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
196 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
197 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
198 | {1, 0x0bf0000, 0x0bf2000, 0x17e000} } }, | ||
199 | {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } }, | ||
200 | {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } }, | ||
201 | {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } }, | ||
202 | {{{1, 0x0f00000, 0x0f01000, 0x164000} } }, | ||
203 | {{{0, 0x1000000, 0x1004000, 0x1a8000} } }, | ||
204 | {{{1, 0x1100000, 0x1101000, 0x160000} } }, | ||
205 | {{{1, 0x1200000, 0x1201000, 0x161000} } }, | ||
206 | {{{1, 0x1300000, 0x1301000, 0x162000} } }, | ||
207 | {{{1, 0x1400000, 0x1401000, 0x163000} } }, | ||
208 | {{{1, 0x1500000, 0x1501000, 0x165000} } }, | ||
209 | {{{1, 0x1600000, 0x1601000, 0x166000} } }, | ||
210 | {{{0, 0, 0, 0} } }, | ||
211 | {{{0, 0, 0, 0} } }, | ||
212 | {{{0, 0, 0, 0} } }, | ||
213 | {{{0, 0, 0, 0} } }, | ||
214 | {{{0, 0, 0, 0} } }, | ||
215 | {{{0, 0, 0, 0} } }, | ||
216 | {{{1, 0x1d00000, 0x1d10000, 0x190000} } }, | ||
217 | {{{1, 0x1e00000, 0x1e01000, 0x16a000} } }, | ||
218 | {{{1, 0x1f00000, 0x1f10000, 0x150000} } }, | ||
219 | {{{0} } }, | ||
220 | {{{1, 0x2100000, 0x2102000, 0x120000}, | ||
221 | {1, 0x2110000, 0x2120000, 0x130000}, | ||
222 | {1, 0x2120000, 0x2122000, 0x124000}, | ||
223 | {1, 0x2130000, 0x2132000, 0x126000}, | ||
224 | {1, 0x2140000, 0x2142000, 0x128000}, | ||
225 | {1, 0x2150000, 0x2152000, 0x12a000}, | ||
226 | {1, 0x2160000, 0x2170000, 0x110000}, | ||
227 | {1, 0x2170000, 0x2172000, 0x12e000}, | ||
228 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
229 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
230 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
231 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
232 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
233 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
234 | {0, 0x0000000, 0x0000000, 0x000000}, | ||
235 | {0, 0x0000000, 0x0000000, 0x000000} } }, | ||
236 | {{{1, 0x2200000, 0x2204000, 0x1b0000} } }, | ||
237 | {{{0} } }, | ||
238 | {{{0} } }, | ||
239 | {{{0} } }, | ||
240 | {{{0} } }, | ||
241 | {{{0} } }, | ||
242 | {{{1, 0x2800000, 0x2804000, 0x1a4000} } }, | ||
243 | {{{1, 0x2900000, 0x2901000, 0x16b000} } }, | ||
244 | {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } }, | ||
245 | {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } }, | ||
246 | {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } }, | ||
247 | {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } }, | ||
248 | {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } }, | ||
249 | {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } }, | ||
250 | {{{1, 0x3000000, 0x3000400, 0x1adc00} } }, | ||
251 | {{{0, 0x3100000, 0x3104000, 0x1a8000} } }, | ||
252 | {{{1, 0x3200000, 0x3204000, 0x1d4000} } }, | ||
253 | {{{1, 0x3300000, 0x3304000, 0x1a0000} } }, | ||
254 | {{{0} } }, | ||
255 | {{{1, 0x3500000, 0x3500400, 0x1ac000} } }, | ||
256 | {{{1, 0x3600000, 0x3600400, 0x1ae000} } }, | ||
257 | {{{1, 0x3700000, 0x3700400, 0x1ae400} } }, | ||
258 | {{{1, 0x3800000, 0x3804000, 0x1d0000} } }, | ||
259 | {{{1, 0x3900000, 0x3904000, 0x1b4000} } }, | ||
260 | {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } }, | ||
261 | {{{0} } }, | ||
262 | {{{0} } }, | ||
263 | {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } }, | ||
264 | {{{1, 0x3e00000, 0x3e01000, 0x167000} } }, | ||
265 | {{{1, 0x3f00000, 0x3f01000, 0x168000} } } | ||
266 | }; | ||
267 | |||
268 | /* | ||
269 | * top 12 bits of crb internal address (hub, agent) | ||
270 | */ | ||
271 | unsigned qla82xx_crb_hub_agt[64] = { | ||
272 | 0, | ||
273 | QLA82XX_HW_CRB_HUB_AGT_ADR_PS, | ||
274 | QLA82XX_HW_CRB_HUB_AGT_ADR_MN, | ||
275 | QLA82XX_HW_CRB_HUB_AGT_ADR_MS, | ||
276 | 0, | ||
277 | QLA82XX_HW_CRB_HUB_AGT_ADR_SRE, | ||
278 | QLA82XX_HW_CRB_HUB_AGT_ADR_NIU, | ||
279 | QLA82XX_HW_CRB_HUB_AGT_ADR_QMN, | ||
280 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0, | ||
281 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1, | ||
282 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2, | ||
283 | QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3, | ||
284 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, | ||
285 | QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, | ||
286 | QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, | ||
287 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4, | ||
288 | QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, | ||
289 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0, | ||
290 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1, | ||
291 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2, | ||
292 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3, | ||
293 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGND, | ||
294 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI, | ||
295 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0, | ||
296 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1, | ||
297 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2, | ||
298 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3, | ||
299 | 0, | ||
300 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI, | ||
301 | QLA82XX_HW_CRB_HUB_AGT_ADR_SN, | ||
302 | 0, | ||
303 | QLA82XX_HW_CRB_HUB_AGT_ADR_EG, | ||
304 | 0, | ||
305 | QLA82XX_HW_CRB_HUB_AGT_ADR_PS, | ||
306 | QLA82XX_HW_CRB_HUB_AGT_ADR_CAM, | ||
307 | 0, | ||
308 | 0, | ||
309 | 0, | ||
310 | 0, | ||
311 | 0, | ||
312 | QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR, | ||
313 | 0, | ||
314 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1, | ||
315 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2, | ||
316 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3, | ||
317 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4, | ||
318 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5, | ||
319 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6, | ||
320 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7, | ||
321 | QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA, | ||
322 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q, | ||
323 | QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB, | ||
324 | 0, | ||
325 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0, | ||
326 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8, | ||
327 | QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9, | ||
328 | QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0, | ||
329 | 0, | ||
330 | QLA82XX_HW_CRB_HUB_AGT_ADR_SMB, | ||
331 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0, | ||
332 | QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1, | ||
333 | 0, | ||
334 | QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC, | ||
335 | 0, | ||
336 | }; | ||
337 | |||
338 | /* | ||
339 | * In: 'off' is offset from CRB space in 128M pci map | ||
340 | * Out: 'off' is 2M pci map addr | ||
341 | * side effect: lock crb window | ||
342 | */ | ||
343 | static void | ||
344 | qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong *off) | ||
345 | { | ||
346 | u32 win_read; | ||
347 | |||
348 | ha->crb_win = CRB_HI(*off); | ||
349 | writel(ha->crb_win, | ||
350 | (void *)(CRB_WINDOW_2M + ha->nx_pcibase)); | ||
351 | |||
352 | /* Read back value to make sure write has gone through before trying | ||
353 | * to use it. | ||
354 | */ | ||
355 | win_read = RD_REG_DWORD((void *)(CRB_WINDOW_2M + ha->nx_pcibase)); | ||
356 | if (win_read != ha->crb_win) { | ||
357 | DEBUG2(qla_printk(KERN_INFO, ha, | ||
358 | "%s: Written crbwin (0x%x) != Read crbwin (0x%x), " | ||
359 | "off=0x%lx\n", __func__, ha->crb_win, win_read, *off)); | ||
360 | } | ||
361 | *off = (*off & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase; | ||
362 | } | ||
363 | |||
364 | static inline unsigned long | ||
365 | qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off) | ||
366 | { | ||
367 | /* See if we are currently pointing to the region we want to use next */ | ||
368 | if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) { | ||
369 | /* No need to change window. PCIX and PCIEregs are in both | ||
370 | * regs are in both windows. | ||
371 | */ | ||
372 | return off; | ||
373 | } | ||
374 | |||
375 | if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) { | ||
376 | /* We are in first CRB window */ | ||
377 | if (ha->curr_window != 0) | ||
378 | WARN_ON(1); | ||
379 | return off; | ||
380 | } | ||
381 | |||
382 | if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) { | ||
383 | /* We are in second CRB window */ | ||
384 | off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST; | ||
385 | |||
386 | if (ha->curr_window != 1) | ||
387 | return off; | ||
388 | |||
389 | /* We are in the QM or direct access | ||
390 | * register region - do nothing | ||
391 | */ | ||
392 | if ((off >= QLA82XX_PCI_DIRECT_CRB) && | ||
393 | (off < QLA82XX_PCI_CAMQM_MAX)) | ||
394 | return off; | ||
395 | } | ||
396 | /* strange address given */ | ||
397 | qla_printk(KERN_WARNING, ha, | ||
398 | "%s: Warning: unm_nic_pci_set_crbwindow called with" | ||
399 | " an unknown address(%llx)\n", QLA2XXX_DRIVER_NAME, off); | ||
400 | return off; | ||
401 | } | ||
402 | |||
403 | int | ||
404 | qla82xx_wr_32(struct qla_hw_data *ha, ulong off, u32 data) | ||
405 | { | ||
406 | unsigned long flags = 0; | ||
407 | int rv; | ||
408 | |||
409 | rv = qla82xx_pci_get_crb_addr_2M(ha, &off); | ||
410 | |||
411 | BUG_ON(rv == -1); | ||
412 | |||
413 | if (rv == 1) { | ||
414 | write_lock_irqsave(&ha->hw_lock, flags); | ||
415 | qla82xx_crb_win_lock(ha); | ||
416 | qla82xx_pci_set_crbwindow_2M(ha, &off); | ||
417 | } | ||
418 | |||
419 | writel(data, (void __iomem *)off); | ||
420 | |||
421 | if (rv == 1) { | ||
422 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); | ||
423 | write_unlock_irqrestore(&ha->hw_lock, flags); | ||
424 | } | ||
425 | return 0; | ||
426 | } | ||
427 | |||
428 | int | ||
429 | qla82xx_rd_32(struct qla_hw_data *ha, ulong off) | ||
430 | { | ||
431 | unsigned long flags = 0; | ||
432 | int rv; | ||
433 | u32 data; | ||
434 | |||
435 | rv = qla82xx_pci_get_crb_addr_2M(ha, &off); | ||
436 | |||
437 | BUG_ON(rv == -1); | ||
438 | |||
439 | if (rv == 1) { | ||
440 | write_lock_irqsave(&ha->hw_lock, flags); | ||
441 | qla82xx_crb_win_lock(ha); | ||
442 | qla82xx_pci_set_crbwindow_2M(ha, &off); | ||
443 | } | ||
444 | data = RD_REG_DWORD((void __iomem *)off); | ||
445 | |||
446 | if (rv == 1) { | ||
447 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK)); | ||
448 | write_unlock_irqrestore(&ha->hw_lock, flags); | ||
449 | } | ||
450 | return data; | ||
451 | } | ||
452 | |||
453 | #define CRB_WIN_LOCK_TIMEOUT 100000000 | ||
454 | int qla82xx_crb_win_lock(struct qla_hw_data *ha) | ||
455 | { | ||
456 | int done = 0, timeout = 0; | ||
457 | |||
458 | while (!done) { | ||
459 | /* acquire semaphore3 from PCI HW block */ | ||
460 | done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK)); | ||
461 | if (done == 1) | ||
462 | break; | ||
463 | if (timeout >= CRB_WIN_LOCK_TIMEOUT) | ||
464 | return -1; | ||
465 | timeout++; | ||
466 | } | ||
467 | qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum); | ||
468 | return 0; | ||
469 | } | ||
470 | |||
471 | #define IDC_LOCK_TIMEOUT 100000000 | ||
472 | int qla82xx_idc_lock(struct qla_hw_data *ha) | ||
473 | { | ||
474 | int i; | ||
475 | int done = 0, timeout = 0; | ||
476 | |||
477 | while (!done) { | ||
478 | /* acquire semaphore5 from PCI HW block */ | ||
479 | done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK)); | ||
480 | if (done == 1) | ||
481 | break; | ||
482 | if (timeout >= IDC_LOCK_TIMEOUT) | ||
483 | return -1; | ||
484 | |||
485 | timeout++; | ||
486 | |||
487 | /* Yield CPU */ | ||
488 | if (!in_interrupt()) | ||
489 | schedule(); | ||
490 | else { | ||
491 | for (i = 0; i < 20; i++) | ||
492 | cpu_relax(); | ||
493 | } | ||
494 | } | ||
495 | |||
496 | return 0; | ||
497 | } | ||
498 | |||
499 | void qla82xx_idc_unlock(struct qla_hw_data *ha) | ||
500 | { | ||
501 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK)); | ||
502 | } | ||
503 | |||
504 | int | ||
505 | qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong *off) | ||
506 | { | ||
507 | struct crb_128M_2M_sub_block_map *m; | ||
508 | |||
509 | if (*off >= QLA82XX_CRB_MAX) | ||
510 | return -1; | ||
511 | |||
512 | if (*off >= QLA82XX_PCI_CAMQM && (*off < QLA82XX_PCI_CAMQM_2M_END)) { | ||
513 | *off = (*off - QLA82XX_PCI_CAMQM) + | ||
514 | QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase; | ||
515 | return 0; | ||
516 | } | ||
517 | |||
518 | if (*off < QLA82XX_PCI_CRBSPACE) | ||
519 | return -1; | ||
520 | |||
521 | *off -= QLA82XX_PCI_CRBSPACE; | ||
522 | |||
523 | /* Try direct map */ | ||
524 | m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)]; | ||
525 | |||
526 | if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) { | ||
527 | *off = *off + m->start_2M - m->start_128M + ha->nx_pcibase; | ||
528 | return 0; | ||
529 | } | ||
530 | /* Not in direct map, use crb window */ | ||
531 | return 1; | ||
532 | } | ||
533 | |||
534 | /* PCI Windowing for DDR regions. */ | ||
535 | #define QLA82XX_ADDR_IN_RANGE(addr, low, high) \ | ||
536 | (((addr) <= (high)) && ((addr) >= (low))) | ||
537 | /* | ||
538 | * check memory access boundary. | ||
539 | * used by test agent. support ddr access only for now | ||
540 | */ | ||
541 | static unsigned long | ||
542 | qla82xx_pci_mem_bound_check(struct qla_hw_data *ha, | ||
543 | unsigned long long addr, int size) | ||
544 | { | ||
545 | if (!QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, | ||
546 | QLA82XX_ADDR_DDR_NET_MAX) || | ||
547 | !QLA82XX_ADDR_IN_RANGE(addr + size - 1, QLA82XX_ADDR_DDR_NET, | ||
548 | QLA82XX_ADDR_DDR_NET_MAX) || | ||
549 | ((size != 1) && (size != 2) && (size != 4) && (size != 8))) | ||
550 | return 0; | ||
551 | else | ||
552 | return 1; | ||
553 | } | ||
554 | |||
555 | int qla82xx_pci_set_window_warning_count; | ||
556 | |||
557 | unsigned long | ||
558 | qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr) | ||
559 | { | ||
560 | int window; | ||
561 | u32 win_read; | ||
562 | |||
563 | if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, | ||
564 | QLA82XX_ADDR_DDR_NET_MAX)) { | ||
565 | /* DDR network side */ | ||
566 | window = MN_WIN(addr); | ||
567 | ha->ddr_mn_window = window; | ||
568 | qla82xx_wr_32(ha, | ||
569 | ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); | ||
570 | win_read = qla82xx_rd_32(ha, | ||
571 | ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); | ||
572 | if ((win_read << 17) != window) { | ||
573 | qla_printk(KERN_WARNING, ha, | ||
574 | "%s: Written MNwin (0x%x) != Read MNwin (0x%x)\n", | ||
575 | __func__, window, win_read); | ||
576 | } | ||
577 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET; | ||
578 | } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, | ||
579 | QLA82XX_ADDR_OCM0_MAX)) { | ||
580 | unsigned int temp1; | ||
581 | if ((addr & 0x00ff800) == 0xff800) { | ||
582 | qla_printk(KERN_WARNING, ha, | ||
583 | "%s: QM access not handled.\n", __func__); | ||
584 | addr = -1UL; | ||
585 | } | ||
586 | window = OCM_WIN(addr); | ||
587 | ha->ddr_mn_window = window; | ||
588 | qla82xx_wr_32(ha, | ||
589 | ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window); | ||
590 | win_read = qla82xx_rd_32(ha, | ||
591 | ha->mn_win_crb | QLA82XX_PCI_CRBSPACE); | ||
592 | temp1 = ((window & 0x1FF) << 7) | | ||
593 | ((window & 0x0FFFE0000) >> 17); | ||
594 | if (win_read != temp1) { | ||
595 | qla_printk(KERN_WARNING, ha, | ||
596 | "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x)\n", | ||
597 | __func__, temp1, win_read); | ||
598 | } | ||
599 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M; | ||
600 | |||
601 | } else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, | ||
602 | QLA82XX_P3_ADDR_QDR_NET_MAX)) { | ||
603 | /* QDR network side */ | ||
604 | window = MS_WIN(addr); | ||
605 | ha->qdr_sn_window = window; | ||
606 | qla82xx_wr_32(ha, | ||
607 | ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window); | ||
608 | win_read = qla82xx_rd_32(ha, | ||
609 | ha->ms_win_crb | QLA82XX_PCI_CRBSPACE); | ||
610 | if (win_read != window) { | ||
611 | qla_printk(KERN_WARNING, ha, | ||
612 | "%s: Written MSwin (0x%x) != Read MSwin (0x%x)\n", | ||
613 | __func__, window, win_read); | ||
614 | } | ||
615 | addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET; | ||
616 | } else { | ||
617 | /* | ||
618 | * peg gdb frequently accesses memory that doesn't exist, | ||
619 | * this limits the chit chat so debugging isn't slowed down. | ||
620 | */ | ||
621 | if ((qla82xx_pci_set_window_warning_count++ < 8) || | ||
622 | (qla82xx_pci_set_window_warning_count%64 == 0)) { | ||
623 | qla_printk(KERN_WARNING, ha, | ||
624 | "%s: Warning:%s Unknown address range!\n", __func__, | ||
625 | QLA2XXX_DRIVER_NAME); | ||
626 | } | ||
627 | addr = -1UL; | ||
628 | } | ||
629 | return addr; | ||
630 | } | ||
631 | |||
632 | /* check if address is in the same windows as the previous access */ | ||
633 | static int qla82xx_pci_is_same_window(struct qla_hw_data *ha, | ||
634 | unsigned long long addr) | ||
635 | { | ||
636 | int window; | ||
637 | unsigned long long qdr_max; | ||
638 | |||
639 | qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX; | ||
640 | |||
641 | /* DDR network side */ | ||
642 | if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_DDR_NET, | ||
643 | QLA82XX_ADDR_DDR_NET_MAX)) | ||
644 | BUG(); | ||
645 | else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM0, | ||
646 | QLA82XX_ADDR_OCM0_MAX)) | ||
647 | return 1; | ||
648 | else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_OCM1, | ||
649 | QLA82XX_ADDR_OCM1_MAX)) | ||
650 | return 1; | ||
651 | else if (QLA82XX_ADDR_IN_RANGE(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) { | ||
652 | /* QDR network side */ | ||
653 | window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f; | ||
654 | if (ha->qdr_sn_window == window) | ||
655 | return 1; | ||
656 | } | ||
657 | return 0; | ||
658 | } | ||
659 | |||
660 | static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha, | ||
661 | u64 off, void *data, int size) | ||
662 | { | ||
663 | unsigned long flags; | ||
664 | void *addr; | ||
665 | int ret = 0; | ||
666 | u64 start; | ||
667 | uint8_t *mem_ptr = NULL; | ||
668 | unsigned long mem_base; | ||
669 | unsigned long mem_page; | ||
670 | |||
671 | write_lock_irqsave(&ha->hw_lock, flags); | ||
672 | |||
673 | /* | ||
674 | * If attempting to access unknown address or straddle hw windows, | ||
675 | * do not access. | ||
676 | */ | ||
677 | start = qla82xx_pci_set_window(ha, off); | ||
678 | if ((start == -1UL) || | ||
679 | (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { | ||
680 | write_unlock_irqrestore(&ha->hw_lock, flags); | ||
681 | qla_printk(KERN_ERR, ha, | ||
682 | "%s out of bound pci memory access. " | ||
683 | "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME, off); | ||
684 | return -1; | ||
685 | } | ||
686 | |||
687 | addr = qla82xx_pci_base_offsetfset(ha, start); | ||
688 | if (!addr) { | ||
689 | write_unlock_irqrestore(&ha->hw_lock, flags); | ||
690 | mem_base = pci_resource_start(ha->pdev, 0); | ||
691 | mem_page = start & PAGE_MASK; | ||
692 | /* Map two pages whenever user tries to access addresses in two | ||
693 | * consecutive pages. | ||
694 | */ | ||
695 | if (mem_page != ((start + size - 1) & PAGE_MASK)) | ||
696 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2); | ||
697 | else | ||
698 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); | ||
699 | if (mem_ptr == 0UL) { | ||
700 | *(u8 *)data = 0; | ||
701 | return -1; | ||
702 | } | ||
703 | addr = mem_ptr; | ||
704 | addr += start & (PAGE_SIZE - 1); | ||
705 | write_lock_irqsave(&ha->hw_lock, flags); | ||
706 | } | ||
707 | |||
708 | switch (size) { | ||
709 | case 1: | ||
710 | *(u8 *)data = readb(addr); | ||
711 | break; | ||
712 | case 2: | ||
713 | *(u16 *)data = readw(addr); | ||
714 | break; | ||
715 | case 4: | ||
716 | *(u32 *)data = readl(addr); | ||
717 | break; | ||
718 | case 8: | ||
719 | *(u64 *)data = readq(addr); | ||
720 | break; | ||
721 | default: | ||
722 | ret = -1; | ||
723 | break; | ||
724 | } | ||
725 | write_unlock_irqrestore(&ha->hw_lock, flags); | ||
726 | |||
727 | if (mem_ptr) | ||
728 | iounmap(mem_ptr); | ||
729 | return ret; | ||
730 | } | ||
731 | |||
732 | static int | ||
733 | qla82xx_pci_mem_write_direct(struct qla_hw_data *ha, | ||
734 | u64 off, void *data, int size) | ||
735 | { | ||
736 | unsigned long flags; | ||
737 | void *addr; | ||
738 | int ret = 0; | ||
739 | u64 start; | ||
740 | uint8_t *mem_ptr = NULL; | ||
741 | unsigned long mem_base; | ||
742 | unsigned long mem_page; | ||
743 | |||
744 | write_lock_irqsave(&ha->hw_lock, flags); | ||
745 | |||
746 | /* | ||
747 | * If attempting to access unknown address or straddle hw windows, | ||
748 | * do not access. | ||
749 | */ | ||
750 | start = qla82xx_pci_set_window(ha, off); | ||
751 | if ((start == -1UL) || | ||
752 | (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) { | ||
753 | write_unlock_irqrestore(&ha->hw_lock, flags); | ||
754 | qla_printk(KERN_ERR, ha, | ||
755 | "%s out of bound pci memory access. " | ||
756 | "offset is 0x%llx\n", QLA2XXX_DRIVER_NAME, off); | ||
757 | return -1; | ||
758 | } | ||
759 | |||
760 | addr = qla82xx_pci_base_offsetfset(ha, start); | ||
761 | if (!addr) { | ||
762 | write_unlock_irqrestore(&ha->hw_lock, flags); | ||
763 | mem_base = pci_resource_start(ha->pdev, 0); | ||
764 | mem_page = start & PAGE_MASK; | ||
765 | /* Map two pages whenever user tries to access addresses in two | ||
766 | * consecutive pages. | ||
767 | */ | ||
768 | if (mem_page != ((start + size - 1) & PAGE_MASK)) | ||
769 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2); | ||
770 | else | ||
771 | mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE); | ||
772 | if (mem_ptr == 0UL) | ||
773 | return -1; | ||
774 | |||
775 | addr = mem_ptr; | ||
776 | addr += start & (PAGE_SIZE - 1); | ||
777 | write_lock_irqsave(&ha->hw_lock, flags); | ||
778 | } | ||
779 | |||
780 | switch (size) { | ||
781 | case 1: | ||
782 | writeb(*(u8 *)data, addr); | ||
783 | break; | ||
784 | case 2: | ||
785 | writew(*(u16 *)data, addr); | ||
786 | break; | ||
787 | case 4: | ||
788 | writel(*(u32 *)data, addr); | ||
789 | break; | ||
790 | case 8: | ||
791 | writeq(*(u64 *)data, addr); | ||
792 | break; | ||
793 | default: | ||
794 | ret = -1; | ||
795 | break; | ||
796 | } | ||
797 | write_unlock_irqrestore(&ha->hw_lock, flags); | ||
798 | if (mem_ptr) | ||
799 | iounmap(mem_ptr); | ||
800 | return ret; | ||
801 | } | ||
802 | |||
803 | int | ||
804 | qla82xx_wrmem(struct qla_hw_data *ha, u64 off, void *data, int size) | ||
805 | { | ||
806 | int i, j, ret = 0, loop, sz[2], off0; | ||
807 | u32 temp; | ||
808 | u64 off8, mem_crb, tmpw, word[2] = {0, 0}; | ||
809 | #define MAX_CTL_CHECK 1000 | ||
810 | /* | ||
811 | * If not MN, go check for MS or invalid. | ||
812 | */ | ||
813 | if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) { | ||
814 | mem_crb = QLA82XX_CRB_QDR_NET; | ||
815 | } else { | ||
816 | mem_crb = QLA82XX_CRB_DDR_NET; | ||
817 | if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) | ||
818 | return qla82xx_pci_mem_write_direct(ha, off, | ||
819 | data, size); | ||
820 | } | ||
821 | |||
822 | off8 = off & 0xfffffff8; | ||
823 | off0 = off & 0x7; | ||
824 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); | ||
825 | sz[1] = size - sz[0]; | ||
826 | loop = ((off0 + size - 1) >> 3) + 1; | ||
827 | |||
828 | if ((size != 8) || (off0 != 0)) { | ||
829 | for (i = 0; i < loop; i++) { | ||
830 | if (qla82xx_rdmem(ha, off8 + (i << 3), &word[i], 8)) | ||
831 | return -1; | ||
832 | } | ||
833 | } | ||
834 | |||
835 | switch (size) { | ||
836 | case 1: | ||
837 | tmpw = *((u8 *)data); | ||
838 | break; | ||
839 | case 2: | ||
840 | tmpw = *((u16 *)data); | ||
841 | break; | ||
842 | case 4: | ||
843 | tmpw = *((u32 *)data); | ||
844 | break; | ||
845 | case 8: | ||
846 | default: | ||
847 | tmpw = *((u64 *)data); | ||
848 | break; | ||
849 | } | ||
850 | |||
851 | word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); | ||
852 | word[0] |= tmpw << (off0 * 8); | ||
853 | |||
854 | if (loop == 2) { | ||
855 | word[1] &= ~(~0ULL << (sz[1] * 8)); | ||
856 | word[1] |= tmpw >> (sz[0] * 8); | ||
857 | } | ||
858 | |||
859 | for (i = 0; i < loop; i++) { | ||
860 | temp = off8 + (i << 3); | ||
861 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); | ||
862 | temp = 0; | ||
863 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); | ||
864 | temp = word[i] & 0xffffffff; | ||
865 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); | ||
866 | temp = (word[i] >> 32) & 0xffffffff; | ||
867 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); | ||
868 | temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; | ||
869 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); | ||
870 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; | ||
871 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_CTRL, temp); | ||
872 | |||
873 | for (j = 0; j < MAX_CTL_CHECK; j++) { | ||
874 | temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); | ||
875 | if ((temp & MIU_TA_CTL_BUSY) == 0) | ||
876 | break; | ||
877 | } | ||
878 | |||
879 | if (j >= MAX_CTL_CHECK) { | ||
880 | qla_printk(KERN_WARNING, ha, | ||
881 | "%s: Fail to write through agent\n", | ||
882 | QLA2XXX_DRIVER_NAME); | ||
883 | ret = -1; | ||
884 | break; | ||
885 | } | ||
886 | } | ||
887 | return ret; | ||
888 | } | ||
889 | |||
890 | int | ||
891 | qla82xx_rdmem(struct qla_hw_data *ha, u64 off, void *data, int size) | ||
892 | { | ||
893 | int i, j = 0, k, start, end, loop, sz[2], off0[2]; | ||
894 | u32 temp; | ||
895 | u64 off8, val, mem_crb, word[2] = {0, 0}; | ||
896 | #define MAX_CTL_CHECK 1000 | ||
897 | |||
898 | /* | ||
899 | * If not MN, go check for MS or invalid. | ||
900 | */ | ||
901 | if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) | ||
902 | mem_crb = QLA82XX_CRB_QDR_NET; | ||
903 | else { | ||
904 | mem_crb = QLA82XX_CRB_DDR_NET; | ||
905 | if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) | ||
906 | return qla82xx_pci_mem_read_direct(ha, off, | ||
907 | data, size); | ||
908 | } | ||
909 | |||
910 | off8 = off & 0xfffffff8; | ||
911 | off0[0] = off & 0x7; | ||
912 | off0[1] = 0; | ||
913 | sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); | ||
914 | sz[1] = size - sz[0]; | ||
915 | loop = ((off0[0] + size - 1) >> 3) + 1; | ||
916 | |||
917 | for (i = 0; i < loop; i++) { | ||
918 | temp = off8 + (i << 3); | ||
919 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); | ||
920 | temp = 0; | ||
921 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); | ||
922 | temp = MIU_TA_CTL_ENABLE; | ||
923 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); | ||
924 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; | ||
925 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); | ||
926 | |||
927 | for (j = 0; j < MAX_CTL_CHECK; j++) { | ||
928 | temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); | ||
929 | if ((temp & MIU_TA_CTL_BUSY) == 0) | ||
930 | break; | ||
931 | } | ||
932 | |||
933 | if (j >= MAX_CTL_CHECK) { | ||
934 | qla_printk(KERN_INFO, ha, | ||
935 | "%s: Fail to read through agent\n", | ||
936 | QLA2XXX_DRIVER_NAME); | ||
937 | break; | ||
938 | } | ||
939 | |||
940 | start = off0[i] >> 2; | ||
941 | end = (off0[i] + sz[i] - 1) >> 2; | ||
942 | for (k = start; k <= end; k++) { | ||
943 | temp = qla82xx_rd_32(ha, | ||
944 | mem_crb + MIU_TEST_AGT_RDDATA(k)); | ||
945 | word[i] |= ((u64)temp << (32 * k)); | ||
946 | } | ||
947 | } | ||
948 | |||
949 | if (j >= MAX_CTL_CHECK) | ||
950 | return -1; | ||
951 | |||
952 | if (sz[0] == 8) { | ||
953 | val = word[0]; | ||
954 | } else { | ||
955 | val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | | ||
956 | ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); | ||
957 | } | ||
958 | |||
959 | switch (size) { | ||
960 | case 1: | ||
961 | *(u8 *)data = val; | ||
962 | break; | ||
963 | case 2: | ||
964 | *(u16 *)data = val; | ||
965 | break; | ||
966 | case 4: | ||
967 | *(u32 *)data = val; | ||
968 | break; | ||
969 | case 8: | ||
970 | *(u64 *)data = val; | ||
971 | break; | ||
972 | } | ||
973 | return 0; | ||
974 | } | ||
975 | |||
976 | #define MTU_FUDGE_FACTOR 100 | ||
977 | unsigned long qla82xx_decode_crb_addr(unsigned long addr) | ||
978 | { | ||
979 | int i; | ||
980 | unsigned long base_addr, offset, pci_base; | ||
981 | |||
982 | if (!qla82xx_crb_table_initialized) | ||
983 | qla82xx_crb_addr_transform_setup(); | ||
984 | |||
985 | pci_base = ADDR_ERROR; | ||
986 | base_addr = addr & 0xfff00000; | ||
987 | offset = addr & 0x000fffff; | ||
988 | |||
989 | for (i = 0; i < MAX_CRB_XFORM; i++) { | ||
990 | if (crb_addr_xform[i] == base_addr) { | ||
991 | pci_base = i << 20; | ||
992 | break; | ||
993 | } | ||
994 | } | ||
995 | if (pci_base == ADDR_ERROR) | ||
996 | return pci_base; | ||
997 | return pci_base + offset; | ||
998 | } | ||
999 | |||
1000 | static long rom_max_timeout = 100; | ||
1001 | static long qla82xx_rom_lock_timeout = 100; | ||
1002 | |||
1003 | int | ||
1004 | qla82xx_rom_lock(struct qla_hw_data *ha) | ||
1005 | { | ||
1006 | int done = 0, timeout = 0; | ||
1007 | |||
1008 | while (!done) { | ||
1009 | /* acquire semaphore2 from PCI HW block */ | ||
1010 | done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK)); | ||
1011 | if (done == 1) | ||
1012 | break; | ||
1013 | if (timeout >= qla82xx_rom_lock_timeout) | ||
1014 | return -1; | ||
1015 | timeout++; | ||
1016 | } | ||
1017 | qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ROM_LOCK_DRIVER); | ||
1018 | return 0; | ||
1019 | } | ||
1020 | |||
1021 | int | ||
1022 | qla82xx_wait_rom_busy(struct qla_hw_data *ha) | ||
1023 | { | ||
1024 | long timeout = 0; | ||
1025 | long done = 0 ; | ||
1026 | |||
1027 | while (done == 0) { | ||
1028 | done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); | ||
1029 | done &= 4; | ||
1030 | timeout++; | ||
1031 | if (timeout >= rom_max_timeout) { | ||
1032 | DEBUG(qla_printk(KERN_INFO, ha, | ||
1033 | "%s: Timeout reached waiting for rom busy", | ||
1034 | QLA2XXX_DRIVER_NAME)); | ||
1035 | return -1; | ||
1036 | } | ||
1037 | } | ||
1038 | return 0; | ||
1039 | } | ||
1040 | |||
1041 | int | ||
1042 | qla82xx_wait_rom_done(struct qla_hw_data *ha) | ||
1043 | { | ||
1044 | long timeout = 0; | ||
1045 | long done = 0 ; | ||
1046 | |||
1047 | while (done == 0) { | ||
1048 | done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS); | ||
1049 | done &= 2; | ||
1050 | timeout++; | ||
1051 | if (timeout >= rom_max_timeout) { | ||
1052 | DEBUG(qla_printk(KERN_INFO, ha, | ||
1053 | "%s: Timeout reached waiting for rom done", | ||
1054 | QLA2XXX_DRIVER_NAME)); | ||
1055 | return -1; | ||
1056 | } | ||
1057 | } | ||
1058 | return 0; | ||
1059 | } | ||
1060 | |||
1061 | int | ||
1062 | qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) | ||
1063 | { | ||
1064 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); | ||
1065 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); | ||
1066 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); | ||
1067 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0xb); | ||
1068 | qla82xx_wait_rom_busy(ha); | ||
1069 | if (qla82xx_wait_rom_done(ha)) { | ||
1070 | qla_printk(KERN_WARNING, ha, | ||
1071 | "%s: Error waiting for rom done\n", | ||
1072 | QLA2XXX_DRIVER_NAME); | ||
1073 | return -1; | ||
1074 | } | ||
1075 | /* Reset abyte_cnt and dummy_byte_cnt */ | ||
1076 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT, 0); | ||
1077 | udelay(10); | ||
1078 | cond_resched(); | ||
1079 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); | ||
1080 | *valp = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); | ||
1081 | return 0; | ||
1082 | } | ||
1083 | |||
1084 | int | ||
1085 | qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp) | ||
1086 | { | ||
1087 | int ret, loops = 0; | ||
1088 | |||
1089 | while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { | ||
1090 | udelay(100); | ||
1091 | schedule(); | ||
1092 | loops++; | ||
1093 | } | ||
1094 | if (loops >= 50000) { | ||
1095 | qla_printk(KERN_INFO, ha, | ||
1096 | "%s: qla82xx_rom_lock failed\n", | ||
1097 | QLA2XXX_DRIVER_NAME); | ||
1098 | return -1; | ||
1099 | } | ||
1100 | ret = qla82xx_do_rom_fast_read(ha, addr, valp); | ||
1101 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); | ||
1102 | return ret; | ||
1103 | } | ||
1104 | |||
1105 | int | ||
1106 | qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val) | ||
1107 | { | ||
1108 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR); | ||
1109 | qla82xx_wait_rom_busy(ha); | ||
1110 | if (qla82xx_wait_rom_done(ha)) { | ||
1111 | qla_printk(KERN_WARNING, ha, | ||
1112 | "Error waiting for rom done\n"); | ||
1113 | return -1; | ||
1114 | } | ||
1115 | *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA); | ||
1116 | return 0; | ||
1117 | } | ||
1118 | |||
1119 | int | ||
1120 | qla82xx_flash_wait_write_finish(struct qla_hw_data *ha) | ||
1121 | { | ||
1122 | long timeout = 0; | ||
1123 | uint32_t done = 1 ; | ||
1124 | uint32_t val; | ||
1125 | int ret = 0; | ||
1126 | |||
1127 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); | ||
1128 | while ((done != 0) && (ret == 0)) { | ||
1129 | ret = qla82xx_read_status_reg(ha, &val); | ||
1130 | done = val & 1; | ||
1131 | timeout++; | ||
1132 | udelay(10); | ||
1133 | cond_resched(); | ||
1134 | if (timeout >= 50000) { | ||
1135 | qla_printk(KERN_WARNING, ha, | ||
1136 | "Timeout reached waiting for write finish"); | ||
1137 | return -1; | ||
1138 | } | ||
1139 | } | ||
1140 | return ret; | ||
1141 | } | ||
1142 | |||
1143 | int | ||
1144 | qla82xx_flash_set_write_enable(struct qla_hw_data *ha) | ||
1145 | { | ||
1146 | uint32_t val; | ||
1147 | qla82xx_wait_rom_busy(ha); | ||
1148 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0); | ||
1149 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN); | ||
1150 | qla82xx_wait_rom_busy(ha); | ||
1151 | if (qla82xx_wait_rom_done(ha)) | ||
1152 | return -1; | ||
1153 | if (qla82xx_read_status_reg(ha, &val) != 0) | ||
1154 | return -1; | ||
1155 | if ((val & 2) != 2) | ||
1156 | return -1; | ||
1157 | return 0; | ||
1158 | } | ||
1159 | |||
1160 | int | ||
1161 | qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val) | ||
1162 | { | ||
1163 | if (qla82xx_flash_set_write_enable(ha)) | ||
1164 | return -1; | ||
1165 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val); | ||
1166 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1); | ||
1167 | if (qla82xx_wait_rom_done(ha)) { | ||
1168 | qla_printk(KERN_WARNING, ha, | ||
1169 | "Error waiting for rom done\n"); | ||
1170 | return -1; | ||
1171 | } | ||
1172 | return qla82xx_flash_wait_write_finish(ha); | ||
1173 | } | ||
1174 | |||
1175 | int | ||
1176 | qla82xx_write_disable_flash(struct qla_hw_data *ha) | ||
1177 | { | ||
1178 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI); | ||
1179 | if (qla82xx_wait_rom_done(ha)) { | ||
1180 | qla_printk(KERN_WARNING, ha, | ||
1181 | "Error waiting for rom done\n"); | ||
1182 | return -1; | ||
1183 | } | ||
1184 | return 0; | ||
1185 | } | ||
1186 | |||
1187 | int | ||
1188 | ql82xx_rom_lock_d(struct qla_hw_data *ha) | ||
1189 | { | ||
1190 | int loops = 0; | ||
1191 | while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) { | ||
1192 | udelay(100); | ||
1193 | cond_resched(); | ||
1194 | loops++; | ||
1195 | } | ||
1196 | if (loops >= 50000) { | ||
1197 | qla_printk(KERN_WARNING, ha, "ROM lock failed\n"); | ||
1198 | return -1; | ||
1199 | } | ||
1200 | return 0;; | ||
1201 | } | ||
1202 | |||
1203 | int | ||
1204 | qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr, | ||
1205 | uint32_t data) | ||
1206 | { | ||
1207 | int ret = 0; | ||
1208 | |||
1209 | ret = ql82xx_rom_lock_d(ha); | ||
1210 | if (ret < 0) { | ||
1211 | qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); | ||
1212 | return ret; | ||
1213 | } | ||
1214 | |||
1215 | if (qla82xx_flash_set_write_enable(ha)) | ||
1216 | goto done_write; | ||
1217 | |||
1218 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data); | ||
1219 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr); | ||
1220 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); | ||
1221 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP); | ||
1222 | qla82xx_wait_rom_busy(ha); | ||
1223 | if (qla82xx_wait_rom_done(ha)) { | ||
1224 | qla_printk(KERN_WARNING, ha, | ||
1225 | "Error waiting for rom done\n"); | ||
1226 | ret = -1; | ||
1227 | goto done_write; | ||
1228 | } | ||
1229 | |||
1230 | ret = qla82xx_flash_wait_write_finish(ha); | ||
1231 | |||
1232 | done_write: | ||
1233 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); | ||
1234 | return ret; | ||
1235 | } | ||
1236 | |||
1237 | /* This routine does CRB initialize sequence | ||
1238 | * to put the ISP into operational state | ||
1239 | */ | ||
1240 | int qla82xx_pinit_from_rom(scsi_qla_host_t *vha) | ||
1241 | { | ||
1242 | int addr, val; | ||
1243 | int i ; | ||
1244 | struct crb_addr_pair *buf; | ||
1245 | unsigned long off; | ||
1246 | unsigned offset, n; | ||
1247 | struct qla_hw_data *ha = vha->hw; | ||
1248 | |||
1249 | struct crb_addr_pair { | ||
1250 | long addr; | ||
1251 | long data; | ||
1252 | }; | ||
1253 | |||
1254 | /* Halt all the indiviual PEGs and other blocks of the ISP */ | ||
1255 | qla82xx_rom_lock(ha); | ||
1256 | if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) | ||
1257 | /* don't reset CAM block on reset */ | ||
1258 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff); | ||
1259 | else | ||
1260 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff); | ||
1261 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); | ||
1262 | |||
1263 | /* Read the signature value from the flash. | ||
1264 | * Offset 0: Contain signature (0xcafecafe) | ||
1265 | * Offset 4: Offset and number of addr/value pairs | ||
1266 | * that present in CRB initialize sequence | ||
1267 | */ | ||
1268 | if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL || | ||
1269 | qla82xx_rom_fast_read(ha, 4, &n) != 0) { | ||
1270 | qla_printk(KERN_WARNING, ha, | ||
1271 | "[ERROR] Reading crb_init area: n: %08x\n", n); | ||
1272 | return -1; | ||
1273 | } | ||
1274 | |||
1275 | /* Offset in flash = lower 16 bits | ||
1276 | * Number of enteries = upper 16 bits | ||
1277 | */ | ||
1278 | offset = n & 0xffffU; | ||
1279 | n = (n >> 16) & 0xffffU; | ||
1280 | |||
1281 | /* number of addr/value pair should not exceed 1024 enteries */ | ||
1282 | if (n >= 1024) { | ||
1283 | qla_printk(KERN_WARNING, ha, | ||
1284 | "%s: %s:n=0x%x [ERROR] Card flash not initialized.\n", | ||
1285 | QLA2XXX_DRIVER_NAME, __func__, n); | ||
1286 | return -1; | ||
1287 | } | ||
1288 | |||
1289 | qla_printk(KERN_INFO, ha, | ||
1290 | "%s: %d CRB init values found in ROM.\n", QLA2XXX_DRIVER_NAME, n); | ||
1291 | |||
1292 | buf = kmalloc(n * sizeof(struct crb_addr_pair), GFP_KERNEL); | ||
1293 | if (buf == NULL) { | ||
1294 | qla_printk(KERN_WARNING, ha, | ||
1295 | "%s: [ERROR] Unable to malloc memory.\n", | ||
1296 | QLA2XXX_DRIVER_NAME); | ||
1297 | return -1; | ||
1298 | } | ||
1299 | |||
1300 | for (i = 0; i < n; i++) { | ||
1301 | if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 || | ||
1302 | qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) { | ||
1303 | kfree(buf); | ||
1304 | return -1; | ||
1305 | } | ||
1306 | |||
1307 | buf[i].addr = addr; | ||
1308 | buf[i].data = val; | ||
1309 | } | ||
1310 | |||
1311 | for (i = 0; i < n; i++) { | ||
1312 | /* Translate internal CRB initialization | ||
1313 | * address to PCI bus address | ||
1314 | */ | ||
1315 | off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) + | ||
1316 | QLA82XX_PCI_CRBSPACE; | ||
1317 | /* Not all CRB addr/value pair to be written, | ||
1318 | * some of them are skipped | ||
1319 | */ | ||
1320 | |||
1321 | /* skipping cold reboot MAGIC */ | ||
1322 | if (off == QLA82XX_CAM_RAM(0x1fc)) | ||
1323 | continue; | ||
1324 | |||
1325 | /* do not reset PCI */ | ||
1326 | if (off == (ROMUSB_GLB + 0xbc)) | ||
1327 | continue; | ||
1328 | |||
1329 | /* skip core clock, so that firmware can increase the clock */ | ||
1330 | if (off == (ROMUSB_GLB + 0xc8)) | ||
1331 | continue; | ||
1332 | |||
1333 | /* skip the function enable register */ | ||
1334 | if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION)) | ||
1335 | continue; | ||
1336 | |||
1337 | if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2)) | ||
1338 | continue; | ||
1339 | |||
1340 | if ((off & 0x0ff00000) == QLA82XX_CRB_SMB) | ||
1341 | continue; | ||
1342 | |||
1343 | if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET) | ||
1344 | continue; | ||
1345 | |||
1346 | if (off == ADDR_ERROR) { | ||
1347 | qla_printk(KERN_WARNING, ha, | ||
1348 | "%s: [ERROR] Unknown addr: 0x%08lx\n", | ||
1349 | QLA2XXX_DRIVER_NAME, buf[i].addr); | ||
1350 | continue; | ||
1351 | } | ||
1352 | |||
1353 | if (off == (QLA82XX_CRB_PEG_NET_1 + 0x18)) { | ||
1354 | if (!QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) | ||
1355 | buf[i].data = 0x1020; | ||
1356 | } | ||
1357 | |||
1358 | qla82xx_wr_32(ha, off, buf[i].data); | ||
1359 | |||
1360 | /* ISP requires much bigger delay to settle down, | ||
1361 | * else crb_window returns 0xffffffff | ||
1362 | */ | ||
1363 | if (off == QLA82XX_ROMUSB_GLB_SW_RESET) | ||
1364 | msleep(1000); | ||
1365 | |||
1366 | /* ISP requires millisec delay between | ||
1367 | * successive CRB register updation | ||
1368 | */ | ||
1369 | msleep(1); | ||
1370 | } | ||
1371 | |||
1372 | kfree(buf); | ||
1373 | |||
1374 | /* Resetting the data and instruction cache */ | ||
1375 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e); | ||
1376 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8); | ||
1377 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8); | ||
1378 | |||
1379 | /* Clear all protocol processing engines */ | ||
1380 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0); | ||
1381 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0); | ||
1382 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0); | ||
1383 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0); | ||
1384 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0); | ||
1385 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0); | ||
1386 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0); | ||
1387 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0); | ||
1388 | return 0; | ||
1389 | } | ||
1390 | |||
1391 | int qla82xx_check_for_bad_spd(struct qla_hw_data *ha) | ||
1392 | { | ||
1393 | u32 val = 0; | ||
1394 | val = qla82xx_rd_32(ha, BOOT_LOADER_DIMM_STATUS); | ||
1395 | val &= QLA82XX_BOOT_LOADER_MN_ISSUE; | ||
1396 | if (val & QLA82XX_PEG_TUNE_MN_SPD_ZEROED) { | ||
1397 | qla_printk(KERN_INFO, ha, | ||
1398 | "Memory DIMM SPD not programmed. " | ||
1399 | " Assumed valid.\n"); | ||
1400 | return 1; | ||
1401 | } else if (val) { | ||
1402 | qla_printk(KERN_INFO, ha, | ||
1403 | "Memory DIMM type incorrect.Info:%08X.\n", val); | ||
1404 | return 2; | ||
1405 | } | ||
1406 | return 0; | ||
1407 | } | ||
1408 | |||
1409 | int | ||
1410 | qla82xx_fw_load_from_flash(struct qla_hw_data *ha) | ||
1411 | { | ||
1412 | int i; | ||
1413 | long size = 0; | ||
1414 | long flashaddr = BOOTLD_START, memaddr = BOOTLD_START; | ||
1415 | u64 data; | ||
1416 | u32 high, low; | ||
1417 | size = (IMAGE_START - BOOTLD_START) / 8; | ||
1418 | |||
1419 | for (i = 0; i < size; i++) { | ||
1420 | if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) || | ||
1421 | (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) { | ||
1422 | return -1; | ||
1423 | } | ||
1424 | data = ((u64)high << 32) | low ; | ||
1425 | qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8); | ||
1426 | flashaddr += 8; | ||
1427 | memaddr += 8; | ||
1428 | |||
1429 | if (i % 0x1000 == 0) | ||
1430 | msleep(1); | ||
1431 | } | ||
1432 | udelay(100); | ||
1433 | read_lock(&ha->hw_lock); | ||
1434 | if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { | ||
1435 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); | ||
1436 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); | ||
1437 | } else { | ||
1438 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001d); | ||
1439 | } | ||
1440 | read_unlock(&ha->hw_lock); | ||
1441 | return 0; | ||
1442 | } | ||
1443 | |||
1444 | int | ||
1445 | qla82xx_pci_mem_read_2M(struct qla_hw_data *ha, | ||
1446 | u64 off, void *data, int size) | ||
1447 | { | ||
1448 | int i, j = 0, k, start, end, loop, sz[2], off0[2]; | ||
1449 | int shift_amount; | ||
1450 | uint32_t temp; | ||
1451 | uint64_t off8, val, mem_crb, word[2] = {0, 0}; | ||
1452 | |||
1453 | /* | ||
1454 | * If not MN, go check for MS or invalid. | ||
1455 | */ | ||
1456 | |||
1457 | if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) | ||
1458 | mem_crb = QLA82XX_CRB_QDR_NET; | ||
1459 | else { | ||
1460 | mem_crb = QLA82XX_CRB_DDR_NET; | ||
1461 | if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) | ||
1462 | return qla82xx_pci_mem_read_direct(ha, | ||
1463 | off, data, size); | ||
1464 | } | ||
1465 | |||
1466 | if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { | ||
1467 | off8 = off & 0xfffffff0; | ||
1468 | off0[0] = off & 0xf; | ||
1469 | sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]); | ||
1470 | shift_amount = 4; | ||
1471 | } else { | ||
1472 | off8 = off & 0xfffffff8; | ||
1473 | off0[0] = off & 0x7; | ||
1474 | sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]); | ||
1475 | shift_amount = 4; | ||
1476 | } | ||
1477 | loop = ((off0[0] + size - 1) >> shift_amount) + 1; | ||
1478 | off0[1] = 0; | ||
1479 | sz[1] = size - sz[0]; | ||
1480 | |||
1481 | /* | ||
1482 | * don't lock here - write_wx gets the lock if each time | ||
1483 | * write_lock_irqsave(&adapter->adapter_lock, flags); | ||
1484 | * netxen_nic_pci_change_crbwindow_128M(adapter, 0); | ||
1485 | */ | ||
1486 | |||
1487 | for (i = 0; i < loop; i++) { | ||
1488 | temp = off8 + (i << shift_amount); | ||
1489 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp); | ||
1490 | temp = 0; | ||
1491 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp); | ||
1492 | temp = MIU_TA_CTL_ENABLE; | ||
1493 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); | ||
1494 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE; | ||
1495 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); | ||
1496 | |||
1497 | for (j = 0; j < MAX_CTL_CHECK; j++) { | ||
1498 | temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); | ||
1499 | if ((temp & MIU_TA_CTL_BUSY) == 0) | ||
1500 | break; | ||
1501 | } | ||
1502 | |||
1503 | if (j >= MAX_CTL_CHECK) { | ||
1504 | if (printk_ratelimit()) | ||
1505 | dev_err(&ha->pdev->dev, | ||
1506 | "failed to read through agent\n"); | ||
1507 | break; | ||
1508 | } | ||
1509 | |||
1510 | start = off0[i] >> 2; | ||
1511 | end = (off0[i] + sz[i] - 1) >> 2; | ||
1512 | for (k = start; k <= end; k++) { | ||
1513 | temp = qla82xx_rd_32(ha, | ||
1514 | mem_crb + MIU_TEST_AGT_RDDATA(k)); | ||
1515 | word[i] |= ((uint64_t)temp << (32 * (k & 1))); | ||
1516 | } | ||
1517 | } | ||
1518 | |||
1519 | /* | ||
1520 | * netxen_nic_pci_change_crbwindow_128M(adapter, 1); | ||
1521 | * write_unlock_irqrestore(&adapter->adapter_lock, flags); | ||
1522 | */ | ||
1523 | |||
1524 | if (j >= MAX_CTL_CHECK) | ||
1525 | return -1; | ||
1526 | |||
1527 | if ((off0[0] & 7) == 0) { | ||
1528 | val = word[0]; | ||
1529 | } else { | ||
1530 | val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) | | ||
1531 | ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8)); | ||
1532 | } | ||
1533 | |||
1534 | switch (size) { | ||
1535 | case 1: | ||
1536 | *(uint8_t *)data = val; | ||
1537 | break; | ||
1538 | case 2: | ||
1539 | *(uint16_t *)data = val; | ||
1540 | break; | ||
1541 | case 4: | ||
1542 | *(uint32_t *)data = val; | ||
1543 | break; | ||
1544 | case 8: | ||
1545 | *(uint64_t *)data = val; | ||
1546 | break; | ||
1547 | } | ||
1548 | return 0; | ||
1549 | } | ||
1550 | |||
1551 | int | ||
1552 | qla82xx_pci_mem_write_2M(struct qla_hw_data *ha, | ||
1553 | u64 off, void *data, int size) | ||
1554 | { | ||
1555 | int i, j, ret = 0, loop, sz[2], off0; | ||
1556 | int scale, shift_amount, p3p, startword; | ||
1557 | uint32_t temp; | ||
1558 | uint64_t off8, mem_crb, tmpw, word[2] = {0, 0}; | ||
1559 | |||
1560 | /* | ||
1561 | * If not MN, go check for MS or invalid. | ||
1562 | */ | ||
1563 | if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX) | ||
1564 | mem_crb = QLA82XX_CRB_QDR_NET; | ||
1565 | else { | ||
1566 | mem_crb = QLA82XX_CRB_DDR_NET; | ||
1567 | if (qla82xx_pci_mem_bound_check(ha, off, size) == 0) | ||
1568 | return qla82xx_pci_mem_write_direct(ha, | ||
1569 | off, data, size); | ||
1570 | } | ||
1571 | |||
1572 | off0 = off & 0x7; | ||
1573 | sz[0] = (size < (8 - off0)) ? size : (8 - off0); | ||
1574 | sz[1] = size - sz[0]; | ||
1575 | |||
1576 | if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { | ||
1577 | off8 = off & 0xfffffff0; | ||
1578 | loop = (((off & 0xf) + size - 1) >> 4) + 1; | ||
1579 | shift_amount = 4; | ||
1580 | scale = 2; | ||
1581 | p3p = 1; | ||
1582 | startword = (off & 0xf)/8; | ||
1583 | } else { | ||
1584 | off8 = off & 0xfffffff8; | ||
1585 | loop = ((off0 + size - 1) >> 3) + 1; | ||
1586 | shift_amount = 3; | ||
1587 | scale = 1; | ||
1588 | p3p = 0; | ||
1589 | startword = 0; | ||
1590 | } | ||
1591 | |||
1592 | if (p3p || (size != 8) || (off0 != 0)) { | ||
1593 | for (i = 0; i < loop; i++) { | ||
1594 | if (qla82xx_pci_mem_read_2M(ha, off8 + | ||
1595 | (i << shift_amount), &word[i * scale], 8)) | ||
1596 | return -1; | ||
1597 | } | ||
1598 | } | ||
1599 | |||
1600 | switch (size) { | ||
1601 | case 1: | ||
1602 | tmpw = *((uint8_t *)data); | ||
1603 | break; | ||
1604 | case 2: | ||
1605 | tmpw = *((uint16_t *)data); | ||
1606 | break; | ||
1607 | case 4: | ||
1608 | tmpw = *((uint32_t *)data); | ||
1609 | break; | ||
1610 | case 8: | ||
1611 | default: | ||
1612 | tmpw = *((uint64_t *)data); | ||
1613 | break; | ||
1614 | } | ||
1615 | |||
1616 | if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { | ||
1617 | if (sz[0] == 8) { | ||
1618 | word[startword] = tmpw; | ||
1619 | } else { | ||
1620 | word[startword] &= | ||
1621 | ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); | ||
1622 | word[startword] |= tmpw << (off0 * 8); | ||
1623 | } | ||
1624 | if (sz[1] != 0) { | ||
1625 | word[startword+1] &= ~(~0ULL << (sz[1] * 8)); | ||
1626 | word[startword+1] |= tmpw >> (sz[0] * 8); | ||
1627 | } | ||
1628 | } else { | ||
1629 | word[startword] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8)); | ||
1630 | word[startword] |= tmpw << (off0 * 8); | ||
1631 | |||
1632 | if (loop == 2) { | ||
1633 | word[1] &= ~(~0ULL << (sz[1] * 8)); | ||
1634 | word[1] |= tmpw >> (sz[0] * 8); | ||
1635 | } | ||
1636 | } | ||
1637 | |||
1638 | /* | ||
1639 | * don't lock here - write_wx gets the lock if each time | ||
1640 | * write_lock_irqsave(&adapter->adapter_lock, flags); | ||
1641 | * netxen_nic_pci_change_crbwindow_128M(adapter, 0); | ||
1642 | */ | ||
1643 | for (i = 0; i < loop; i++) { | ||
1644 | temp = off8 + (i << shift_amount); | ||
1645 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp); | ||
1646 | temp = 0; | ||
1647 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp); | ||
1648 | temp = word[i * scale] & 0xffffffff; | ||
1649 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp); | ||
1650 | temp = (word[i * scale] >> 32) & 0xffffffff; | ||
1651 | qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp); | ||
1652 | if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { | ||
1653 | temp = word[i*scale + 1] & 0xffffffff; | ||
1654 | qla82xx_wr_32(ha, mem_crb + | ||
1655 | MIU_TEST_AGT_WRDATA_UPPER_LO, temp); | ||
1656 | temp = (word[i*scale + 1] >> 32) & 0xffffffff; | ||
1657 | qla82xx_wr_32(ha, mem_crb + | ||
1658 | MIU_TEST_AGT_WRDATA_UPPER_HI, temp); | ||
1659 | } | ||
1660 | |||
1661 | temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; | ||
1662 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); | ||
1663 | temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE; | ||
1664 | qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp); | ||
1665 | |||
1666 | for (j = 0; j < MAX_CTL_CHECK; j++) { | ||
1667 | temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL); | ||
1668 | if ((temp & MIU_TA_CTL_BUSY) == 0) | ||
1669 | break; | ||
1670 | } | ||
1671 | |||
1672 | if (j >= MAX_CTL_CHECK) { | ||
1673 | if (printk_ratelimit()) | ||
1674 | dev_err(&ha->pdev->dev, | ||
1675 | "failed to write through agent\n"); | ||
1676 | ret = -1; | ||
1677 | break; | ||
1678 | } | ||
1679 | } | ||
1680 | |||
1681 | return ret; | ||
1682 | } | ||
1683 | |||
1684 | /* PCI related functions */ | ||
1685 | char * | ||
1686 | qla82xx_pci_info_str(struct scsi_qla_host *vha, char *str) | ||
1687 | { | ||
1688 | int pcie_reg; | ||
1689 | struct qla_hw_data *ha = vha->hw; | ||
1690 | char lwstr[6]; | ||
1691 | uint16_t lnk; | ||
1692 | |||
1693 | pcie_reg = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); | ||
1694 | pci_read_config_word(ha->pdev, pcie_reg + PCI_EXP_LNKSTA, &lnk); | ||
1695 | ha->link_width = (lnk >> 4) & 0x3f; | ||
1696 | |||
1697 | strcpy(str, "PCIe ("); | ||
1698 | strcat(str, "2.5Gb/s "); | ||
1699 | snprintf(lwstr, sizeof(lwstr), "x%d)", ha->link_width); | ||
1700 | strcat(str, lwstr); | ||
1701 | return str; | ||
1702 | } | ||
1703 | |||
1704 | int qla82xx_pci_region_offset(struct pci_dev *pdev, int region) | ||
1705 | { | ||
1706 | unsigned long val = 0; | ||
1707 | u32 control; | ||
1708 | |||
1709 | switch (region) { | ||
1710 | case 0: | ||
1711 | val = 0; | ||
1712 | break; | ||
1713 | case 1: | ||
1714 | pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); | ||
1715 | val = control + QLA82XX_MSIX_TBL_SPACE; | ||
1716 | break; | ||
1717 | } | ||
1718 | return val; | ||
1719 | } | ||
1720 | |||
1721 | int qla82xx_pci_region_len(struct pci_dev *pdev, int region) | ||
1722 | { | ||
1723 | unsigned long val = 0; | ||
1724 | u32 control; | ||
1725 | switch (region) { | ||
1726 | case 0: | ||
1727 | pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control); | ||
1728 | val = control; | ||
1729 | break; | ||
1730 | case 1: | ||
1731 | val = pci_resource_len(pdev, 0) - | ||
1732 | qla82xx_pci_region_offset(pdev, 1); | ||
1733 | break; | ||
1734 | } | ||
1735 | return val; | ||
1736 | } | ||
1737 | |||
1738 | int | ||
1739 | qla82xx_iospace_config(struct qla_hw_data *ha) | ||
1740 | { | ||
1741 | uint32_t len = 0; | ||
1742 | |||
1743 | if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) { | ||
1744 | qla_printk(KERN_WARNING, ha, | ||
1745 | "Failed to reserve selected regions (%s)\n", | ||
1746 | pci_name(ha->pdev)); | ||
1747 | goto iospace_error_exit; | ||
1748 | } | ||
1749 | |||
1750 | /* Use MMIO operations for all accesses. */ | ||
1751 | if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { | ||
1752 | qla_printk(KERN_ERR, ha, | ||
1753 | "region #0 not an MMIO resource (%s), aborting\n", | ||
1754 | pci_name(ha->pdev)); | ||
1755 | goto iospace_error_exit; | ||
1756 | } | ||
1757 | |||
1758 | len = pci_resource_len(ha->pdev, 0); | ||
1759 | ha->nx_pcibase = | ||
1760 | (unsigned long)ioremap(pci_resource_start(ha->pdev, 0), len); | ||
1761 | if (!ha->nx_pcibase) { | ||
1762 | qla_printk(KERN_ERR, ha, | ||
1763 | "cannot remap pcibase MMIO (%s), aborting\n", | ||
1764 | pci_name(ha->pdev)); | ||
1765 | pci_release_regions(ha->pdev); | ||
1766 | goto iospace_error_exit; | ||
1767 | } | ||
1768 | |||
1769 | /* Mapping of IO base pointer */ | ||
1770 | ha->iobase = (device_reg_t __iomem *)((uint8_t *)ha->nx_pcibase + | ||
1771 | 0xbc000 + (ha->pdev->devfn << 11)); | ||
1772 | |||
1773 | if (!ql2xdbwr) { | ||
1774 | ha->nxdb_wr_ptr = | ||
1775 | (unsigned long)ioremap((pci_resource_start(ha->pdev, 4) + | ||
1776 | (ha->pdev->devfn << 12)), 4); | ||
1777 | if (!ha->nxdb_wr_ptr) { | ||
1778 | qla_printk(KERN_ERR, ha, | ||
1779 | "cannot remap MMIO (%s), aborting\n", | ||
1780 | pci_name(ha->pdev)); | ||
1781 | pci_release_regions(ha->pdev); | ||
1782 | goto iospace_error_exit; | ||
1783 | } | ||
1784 | |||
1785 | /* Mapping of IO base pointer, | ||
1786 | * door bell read and write pointer | ||
1787 | */ | ||
1788 | ha->nxdb_rd_ptr = (uint8_t *) ha->nx_pcibase + (512 * 1024) + | ||
1789 | (ha->pdev->devfn * 8); | ||
1790 | } else { | ||
1791 | ha->nxdb_wr_ptr = (ha->pdev->devfn == 6 ? | ||
1792 | QLA82XX_CAMRAM_DB1 : | ||
1793 | QLA82XX_CAMRAM_DB2); | ||
1794 | } | ||
1795 | |||
1796 | ha->max_req_queues = ha->max_rsp_queues = 1; | ||
1797 | ha->msix_count = ha->max_rsp_queues + 1; | ||
1798 | return 0; | ||
1799 | |||
1800 | iospace_error_exit: | ||
1801 | return -ENOMEM; | ||
1802 | } | ||
1803 | |||
1804 | /* GS related functions */ | ||
1805 | |||
1806 | /* Initialization related functions */ | ||
1807 | |||
1808 | /** | ||
1809 | * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers. | ||
1810 | * @ha: HA context | ||
1811 | * | ||
1812 | * Returns 0 on success. | ||
1813 | */ | ||
1814 | int | ||
1815 | qla82xx_pci_config(scsi_qla_host_t *vha) | ||
1816 | { | ||
1817 | struct qla_hw_data *ha = vha->hw; | ||
1818 | int ret; | ||
1819 | |||
1820 | pci_set_master(ha->pdev); | ||
1821 | ret = pci_set_mwi(ha->pdev); | ||
1822 | ha->chip_revision = ha->pdev->revision; | ||
1823 | return 0; | ||
1824 | } | ||
1825 | |||
1826 | /** | ||
1827 | * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers. | ||
1828 | * @ha: HA context | ||
1829 | * | ||
1830 | * Returns 0 on success. | ||
1831 | */ | ||
1832 | void | ||
1833 | qla82xx_reset_chip(scsi_qla_host_t *vha) | ||
1834 | { | ||
1835 | struct qla_hw_data *ha = vha->hw; | ||
1836 | ha->isp_ops->disable_intrs(ha); | ||
1837 | } | ||
1838 | |||
1839 | void qla82xx_config_rings(struct scsi_qla_host *vha) | ||
1840 | { | ||
1841 | struct qla_hw_data *ha = vha->hw; | ||
1842 | struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; | ||
1843 | struct init_cb_81xx *icb; | ||
1844 | struct req_que *req = ha->req_q_map[0]; | ||
1845 | struct rsp_que *rsp = ha->rsp_q_map[0]; | ||
1846 | |||
1847 | /* Setup ring parameters in initialization control block. */ | ||
1848 | icb = (struct init_cb_81xx *)ha->init_cb; | ||
1849 | icb->request_q_outpointer = __constant_cpu_to_le16(0); | ||
1850 | icb->response_q_inpointer = __constant_cpu_to_le16(0); | ||
1851 | icb->request_q_length = cpu_to_le16(req->length); | ||
1852 | icb->response_q_length = cpu_to_le16(rsp->length); | ||
1853 | icb->request_q_address[0] = cpu_to_le32(LSD(req->dma)); | ||
1854 | icb->request_q_address[1] = cpu_to_le32(MSD(req->dma)); | ||
1855 | icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma)); | ||
1856 | icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma)); | ||
1857 | |||
1858 | icb->version = 1; | ||
1859 | icb->frame_payload_size = 2112; | ||
1860 | icb->execution_throttle = 8; | ||
1861 | icb->exchange_count = 128; | ||
1862 | icb->login_retry_count = 8; | ||
1863 | |||
1864 | WRT_REG_DWORD((unsigned long __iomem *)®->req_q_out[0], 0); | ||
1865 | WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_in[0], 0); | ||
1866 | WRT_REG_DWORD((unsigned long __iomem *)®->rsp_q_out[0], 0); | ||
1867 | } | ||
1868 | |||
1869 | int qla82xx_fw_load_from_blob(struct qla_hw_data *ha) | ||
1870 | { | ||
1871 | u64 *ptr64; | ||
1872 | u32 i, flashaddr, size; | ||
1873 | __le64 data; | ||
1874 | |||
1875 | size = (IMAGE_START - BOOTLD_START) / 8; | ||
1876 | |||
1877 | ptr64 = (u64 *)&ha->hablob->fw->data[BOOTLD_START]; | ||
1878 | flashaddr = BOOTLD_START; | ||
1879 | |||
1880 | for (i = 0; i < size; i++) { | ||
1881 | data = cpu_to_le64(ptr64[i]); | ||
1882 | qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8); | ||
1883 | flashaddr += 8; | ||
1884 | } | ||
1885 | |||
1886 | size = *(u32 *)&ha->hablob->fw->data[FW_SIZE_OFFSET]; | ||
1887 | size = (__force u32)cpu_to_le32(size) / 8; | ||
1888 | ptr64 = (u64 *)&ha->hablob->fw->data[IMAGE_START]; | ||
1889 | flashaddr = FLASH_ADDR_START; | ||
1890 | |||
1891 | for (i = 0; i < size; i++) { | ||
1892 | data = cpu_to_le64(ptr64[i]); | ||
1893 | |||
1894 | if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8)) | ||
1895 | return -EIO; | ||
1896 | flashaddr += 8; | ||
1897 | } | ||
1898 | |||
1899 | /* Write a magic value to CAMRAM register | ||
1900 | * at a specified offset to indicate | ||
1901 | * that all data is written and | ||
1902 | * ready for firmware to initialize. | ||
1903 | */ | ||
1904 | qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), 0x12345678); | ||
1905 | |||
1906 | if (QLA82XX_IS_REVISION_P3PLUS(ha->chip_revision)) { | ||
1907 | qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020); | ||
1908 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e); | ||
1909 | } else | ||
1910 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001d); | ||
1911 | return 0; | ||
1912 | } | ||
1913 | |||
1914 | int qla82xx_check_cmdpeg_state(struct qla_hw_data *ha) | ||
1915 | { | ||
1916 | u32 val = 0; | ||
1917 | int retries = 60; | ||
1918 | |||
1919 | do { | ||
1920 | read_lock(&ha->hw_lock); | ||
1921 | val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE); | ||
1922 | read_unlock(&ha->hw_lock); | ||
1923 | |||
1924 | switch (val) { | ||
1925 | case PHAN_INITIALIZE_COMPLETE: | ||
1926 | case PHAN_INITIALIZE_ACK: | ||
1927 | return QLA_SUCCESS; | ||
1928 | case PHAN_INITIALIZE_FAILED: | ||
1929 | break; | ||
1930 | default: | ||
1931 | break; | ||
1932 | } | ||
1933 | qla_printk(KERN_WARNING, ha, | ||
1934 | "CRB_CMDPEG_STATE: 0x%x and retries: 0x%x\n", | ||
1935 | val, retries); | ||
1936 | |||
1937 | msleep(500); | ||
1938 | |||
1939 | } while (--retries); | ||
1940 | |||
1941 | qla_printk(KERN_INFO, ha, | ||
1942 | "Cmd Peg initialization failed: 0x%x.\n", val); | ||
1943 | |||
1944 | qla82xx_check_for_bad_spd(ha); | ||
1945 | val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE); | ||
1946 | read_lock(&ha->hw_lock); | ||
1947 | qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED); | ||
1948 | read_unlock(&ha->hw_lock); | ||
1949 | return QLA_FUNCTION_FAILED; | ||
1950 | } | ||
1951 | |||
1952 | int qla82xx_check_rcvpeg_state(struct qla_hw_data *ha) | ||
1953 | { | ||
1954 | u32 val = 0; | ||
1955 | int retries = 60; | ||
1956 | |||
1957 | do { | ||
1958 | read_lock(&ha->hw_lock); | ||
1959 | val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE); | ||
1960 | read_unlock(&ha->hw_lock); | ||
1961 | |||
1962 | switch (val) { | ||
1963 | case PHAN_INITIALIZE_COMPLETE: | ||
1964 | case PHAN_INITIALIZE_ACK: | ||
1965 | return QLA_SUCCESS; | ||
1966 | case PHAN_INITIALIZE_FAILED: | ||
1967 | break; | ||
1968 | default: | ||
1969 | break; | ||
1970 | } | ||
1971 | |||
1972 | qla_printk(KERN_WARNING, ha, | ||
1973 | "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x\n", | ||
1974 | val, retries); | ||
1975 | |||
1976 | msleep(500); | ||
1977 | |||
1978 | } while (--retries); | ||
1979 | |||
1980 | qla_printk(KERN_INFO, ha, | ||
1981 | "Rcv Peg initialization failed: 0x%x.\n", val); | ||
1982 | read_lock(&ha->hw_lock); | ||
1983 | qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED); | ||
1984 | read_unlock(&ha->hw_lock); | ||
1985 | return QLA_FUNCTION_FAILED; | ||
1986 | } | ||
1987 | |||
1988 | /* ISR related functions */ | ||
1989 | uint32_t qla82xx_isr_int_target_mask_enable[8] = { | ||
1990 | ISR_INT_TARGET_MASK, ISR_INT_TARGET_MASK_F1, | ||
1991 | ISR_INT_TARGET_MASK_F2, ISR_INT_TARGET_MASK_F3, | ||
1992 | ISR_INT_TARGET_MASK_F4, ISR_INT_TARGET_MASK_F5, | ||
1993 | ISR_INT_TARGET_MASK_F7, ISR_INT_TARGET_MASK_F7 | ||
1994 | }; | ||
1995 | |||
1996 | uint32_t qla82xx_isr_int_target_status[8] = { | ||
1997 | ISR_INT_TARGET_STATUS, ISR_INT_TARGET_STATUS_F1, | ||
1998 | ISR_INT_TARGET_STATUS_F2, ISR_INT_TARGET_STATUS_F3, | ||
1999 | ISR_INT_TARGET_STATUS_F4, ISR_INT_TARGET_STATUS_F5, | ||
2000 | ISR_INT_TARGET_STATUS_F7, ISR_INT_TARGET_STATUS_F7 | ||
2001 | }; | ||
2002 | |||
2003 | static struct qla82xx_legacy_intr_set legacy_intr[] = \ | ||
2004 | QLA82XX_LEGACY_INTR_CONFIG; | ||
2005 | |||
2006 | /* | ||
2007 | * qla82xx_mbx_completion() - Process mailbox command completions. | ||
2008 | * @ha: SCSI driver HA context | ||
2009 | * @mb0: Mailbox0 register | ||
2010 | */ | ||
2011 | void | ||
2012 | qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0) | ||
2013 | { | ||
2014 | uint16_t cnt; | ||
2015 | uint16_t __iomem *wptr; | ||
2016 | struct qla_hw_data *ha = vha->hw; | ||
2017 | struct device_reg_82xx __iomem *reg = &ha->iobase->isp82; | ||
2018 | wptr = (uint16_t __iomem *)®->mailbox_out[1]; | ||
2019 | |||
2020 | /* Load return mailbox registers. */ | ||
2021 | ha->flags.mbox_int = 1; | ||
2022 | ha->mailbox_out[0] = mb0; | ||
2023 | |||
2024 | for (cnt = 1; cnt < ha->mbx_count; cnt++) { | ||
2025 | ha->mailbox_out[cnt] = RD_REG_WORD(wptr); | ||
2026 | wptr++; | ||
2027 | } | ||
2028 | |||
2029 | if (ha->mcp) { | ||
2030 | DEBUG3_11(printk(KERN_INFO "%s(%ld): " | ||
2031 | "Got mailbox completion. cmd=%x.\n", | ||
2032 | __func__, vha->host_no, ha->mcp->mb[0])); | ||
2033 | } else { | ||
2034 | qla_printk(KERN_INFO, ha, | ||
2035 | "%s(%ld): MBX pointer ERROR!\n", | ||
2036 | __func__, vha->host_no); | ||
2037 | } | ||
2038 | } | ||
2039 | |||
2040 | /* | ||
2041 | * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx. | ||
2042 | * @irq: | ||
2043 | * @dev_id: SCSI driver HA context | ||
2044 | * @regs: | ||
2045 | * | ||
2046 | * Called by system whenever the host adapter generates an interrupt. | ||
2047 | * | ||
2048 | * Returns handled flag. | ||
2049 | */ | ||
2050 | irqreturn_t | ||
2051 | qla82xx_intr_handler(int irq, void *dev_id) | ||
2052 | { | ||
2053 | scsi_qla_host_t *vha; | ||
2054 | struct qla_hw_data *ha; | ||
2055 | struct rsp_que *rsp; | ||
2056 | struct device_reg_82xx __iomem *reg; | ||
2057 | int status = 0, status1 = 0; | ||
2058 | unsigned long flags; | ||
2059 | unsigned long iter; | ||
2060 | uint32_t stat; | ||
2061 | uint16_t mb[4]; | ||
2062 | |||
2063 | rsp = (struct rsp_que *) dev_id; | ||
2064 | if (!rsp) { | ||
2065 | printk(KERN_INFO | ||
2066 | "%s(): NULL response queue pointer\n", __func__); | ||
2067 | return IRQ_NONE; | ||
2068 | } | ||
2069 | ha = rsp->hw; | ||
2070 | |||
2071 | if (!ha->flags.msi_enabled) { | ||
2072 | status = qla82xx_rd_32(ha, ISR_INT_VECTOR); | ||
2073 | if (!(status & ha->nx_legacy_intr.int_vec_bit)) | ||
2074 | return IRQ_NONE; | ||
2075 | |||
2076 | status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG); | ||
2077 | if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1)) | ||
2078 | return IRQ_NONE; | ||
2079 | } | ||
2080 | |||
2081 | /* clear the interrupt */ | ||
2082 | qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff); | ||
2083 | |||
2084 | /* read twice to ensure write is flushed */ | ||
2085 | qla82xx_rd_32(ha, ISR_INT_VECTOR); | ||
2086 | qla82xx_rd_32(ha, ISR_INT_VECTOR); | ||
2087 | |||
2088 | reg = &ha->iobase->isp82; | ||
2089 | |||
2090 | spin_lock_irqsave(&ha->hardware_lock, flags); | ||
2091 | vha = pci_get_drvdata(ha->pdev); | ||
2092 | for (iter = 1; iter--; ) { | ||
2093 | |||
2094 | if (RD_REG_DWORD(®->host_int)) { | ||
2095 | stat = RD_REG_DWORD(®->host_status); | ||
2096 | if (stat & HSRX_RISC_PAUSED) { | ||
2097 | if (pci_channel_offline(ha->pdev)) | ||
2098 | break; | ||
2099 | |||
2100 | qla_printk(KERN_INFO, ha, "RISC paused\n"); | ||
2101 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | ||
2102 | qla2xxx_wake_dpc(vha); | ||
2103 | break; | ||
2104 | } else if ((stat & HSRX_RISC_INT) == 0) | ||
2105 | break; | ||
2106 | |||
2107 | switch (stat & 0xff) { | ||
2108 | case 0x1: | ||
2109 | case 0x2: | ||
2110 | case 0x10: | ||
2111 | case 0x11: | ||
2112 | qla82xx_mbx_completion(vha, MSW(stat)); | ||
2113 | status |= MBX_INTERRUPT; | ||
2114 | break; | ||
2115 | case 0x12: | ||
2116 | mb[0] = MSW(stat); | ||
2117 | mb[1] = RD_REG_WORD(®->mailbox_out[1]); | ||
2118 | mb[2] = RD_REG_WORD(®->mailbox_out[2]); | ||
2119 | mb[3] = RD_REG_WORD(®->mailbox_out[3]); | ||
2120 | qla2x00_async_event(vha, rsp, mb); | ||
2121 | break; | ||
2122 | case 0x13: | ||
2123 | qla24xx_process_response_queue(vha, rsp); | ||
2124 | break; | ||
2125 | default: | ||
2126 | DEBUG2(printk("scsi(%ld): " | ||
2127 | " Unrecognized interrupt type (%d).\n", | ||
2128 | vha->host_no, stat & 0xff)); | ||
2129 | break; | ||
2130 | } | ||
2131 | } | ||
2132 | WRT_REG_DWORD(®->host_int, 0); | ||
2133 | } | ||
2134 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | ||
2135 | if (!ha->flags.msi_enabled) | ||
2136 | qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); | ||
2137 | |||
2138 | #ifdef QL_DEBUG_LEVEL_17 | ||
2139 | if (!irq && ha->flags.eeh_busy) | ||
2140 | qla_printk(KERN_WARNING, ha, | ||
2141 | "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n", | ||
2142 | status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); | ||
2143 | #endif | ||
2144 | |||
2145 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && | ||
2146 | (status & MBX_INTERRUPT) && ha->flags.mbox_int) { | ||
2147 | set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | ||
2148 | complete(&ha->mbx_intr_comp); | ||
2149 | } | ||
2150 | return IRQ_HANDLED; | ||
2151 | } | ||
2152 | |||
2153 | irqreturn_t | ||
2154 | qla82xx_msix_default(int irq, void *dev_id) | ||
2155 | { | ||
2156 | scsi_qla_host_t *vha; | ||
2157 | struct qla_hw_data *ha; | ||
2158 | struct rsp_que *rsp; | ||
2159 | struct device_reg_82xx __iomem *reg; | ||
2160 | int status = 0; | ||
2161 | unsigned long flags; | ||
2162 | uint32_t stat; | ||
2163 | uint16_t mb[4]; | ||
2164 | |||
2165 | rsp = (struct rsp_que *) dev_id; | ||
2166 | if (!rsp) { | ||
2167 | printk(KERN_INFO | ||
2168 | "%s(): NULL response queue pointer\n", __func__); | ||
2169 | return IRQ_NONE; | ||
2170 | } | ||
2171 | ha = rsp->hw; | ||
2172 | |||
2173 | reg = &ha->iobase->isp82; | ||
2174 | |||
2175 | spin_lock_irqsave(&ha->hardware_lock, flags); | ||
2176 | vha = pci_get_drvdata(ha->pdev); | ||
2177 | do { | ||
2178 | if (RD_REG_DWORD(®->host_int)) { | ||
2179 | stat = RD_REG_DWORD(®->host_status); | ||
2180 | if (stat & HSRX_RISC_PAUSED) { | ||
2181 | if (pci_channel_offline(ha->pdev)) | ||
2182 | break; | ||
2183 | |||
2184 | qla_printk(KERN_INFO, ha, "RISC paused\n"); | ||
2185 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | ||
2186 | qla2xxx_wake_dpc(vha); | ||
2187 | break; | ||
2188 | } else if ((stat & HSRX_RISC_INT) == 0) | ||
2189 | break; | ||
2190 | |||
2191 | switch (stat & 0xff) { | ||
2192 | case 0x1: | ||
2193 | case 0x2: | ||
2194 | case 0x10: | ||
2195 | case 0x11: | ||
2196 | qla82xx_mbx_completion(vha, MSW(stat)); | ||
2197 | status |= MBX_INTERRUPT; | ||
2198 | break; | ||
2199 | case 0x12: | ||
2200 | mb[0] = MSW(stat); | ||
2201 | mb[1] = RD_REG_WORD(®->mailbox_out[1]); | ||
2202 | mb[2] = RD_REG_WORD(®->mailbox_out[2]); | ||
2203 | mb[3] = RD_REG_WORD(®->mailbox_out[3]); | ||
2204 | qla2x00_async_event(vha, rsp, mb); | ||
2205 | break; | ||
2206 | case 0x13: | ||
2207 | qla24xx_process_response_queue(vha, rsp); | ||
2208 | break; | ||
2209 | default: | ||
2210 | DEBUG2(printk("scsi(%ld): " | ||
2211 | " Unrecognized interrupt type (%d).\n", | ||
2212 | vha->host_no, stat & 0xff)); | ||
2213 | break; | ||
2214 | } | ||
2215 | } | ||
2216 | WRT_REG_DWORD(®->host_int, 0); | ||
2217 | } while (0); | ||
2218 | |||
2219 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | ||
2220 | |||
2221 | #ifdef QL_DEBUG_LEVEL_17 | ||
2222 | if (!irq && ha->flags.eeh_busy) | ||
2223 | qla_printk(KERN_WARNING, ha, | ||
2224 | "isr: status %x, cmd_flags %lx, mbox_int %x, stat %x\n", | ||
2225 | status, ha->mbx_cmd_flags, ha->flags.mbox_int, stat); | ||
2226 | #endif | ||
2227 | |||
2228 | if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags) && | ||
2229 | (status & MBX_INTERRUPT) && ha->flags.mbox_int) { | ||
2230 | set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); | ||
2231 | complete(&ha->mbx_intr_comp); | ||
2232 | } | ||
2233 | return IRQ_HANDLED; | ||
2234 | } | ||
2235 | |||
2236 | irqreturn_t | ||
2237 | qla82xx_msix_rsp_q(int irq, void *dev_id) | ||
2238 | { | ||
2239 | scsi_qla_host_t *vha; | ||
2240 | struct qla_hw_data *ha; | ||
2241 | struct rsp_que *rsp; | ||
2242 | struct device_reg_82xx __iomem *reg; | ||
2243 | |||
2244 | rsp = (struct rsp_que *) dev_id; | ||
2245 | if (!rsp) { | ||
2246 | printk(KERN_INFO | ||
2247 | "%s(): NULL response queue pointer\n", __func__); | ||
2248 | return IRQ_NONE; | ||
2249 | } | ||
2250 | |||
2251 | ha = rsp->hw; | ||
2252 | reg = &ha->iobase->isp82; | ||
2253 | spin_lock_irq(&ha->hardware_lock); | ||
2254 | vha = pci_get_drvdata(ha->pdev); | ||
2255 | qla24xx_process_response_queue(vha, rsp); | ||
2256 | WRT_REG_DWORD(®->host_int, 0); | ||
2257 | spin_unlock_irq(&ha->hardware_lock); | ||
2258 | return IRQ_HANDLED; | ||
2259 | } | ||
2260 | |||
2261 | void | ||
2262 | qla82xx_poll(int irq, void *dev_id) | ||
2263 | { | ||
2264 | scsi_qla_host_t *vha; | ||
2265 | struct qla_hw_data *ha; | ||
2266 | struct rsp_que *rsp; | ||
2267 | struct device_reg_82xx __iomem *reg; | ||
2268 | int status = 0; | ||
2269 | uint32_t stat; | ||
2270 | uint16_t mb[4]; | ||
2271 | unsigned long flags; | ||
2272 | |||
2273 | rsp = (struct rsp_que *) dev_id; | ||
2274 | if (!rsp) { | ||
2275 | printk(KERN_INFO | ||
2276 | "%s(): NULL response queue pointer\n", __func__); | ||
2277 | return; | ||
2278 | } | ||
2279 | ha = rsp->hw; | ||
2280 | |||
2281 | reg = &ha->iobase->isp82; | ||
2282 | spin_lock_irqsave(&ha->hardware_lock, flags); | ||
2283 | vha = pci_get_drvdata(ha->pdev); | ||
2284 | |||
2285 | if (RD_REG_DWORD(®->host_int)) { | ||
2286 | stat = RD_REG_DWORD(®->host_status); | ||
2287 | switch (stat & 0xff) { | ||
2288 | case 0x1: | ||
2289 | case 0x2: | ||
2290 | case 0x10: | ||
2291 | case 0x11: | ||
2292 | qla82xx_mbx_completion(vha, MSW(stat)); | ||
2293 | status |= MBX_INTERRUPT; | ||
2294 | break; | ||
2295 | case 0x12: | ||
2296 | mb[0] = MSW(stat); | ||
2297 | mb[1] = RD_REG_WORD(®->mailbox_out[1]); | ||
2298 | mb[2] = RD_REG_WORD(®->mailbox_out[2]); | ||
2299 | mb[3] = RD_REG_WORD(®->mailbox_out[3]); | ||
2300 | qla2x00_async_event(vha, rsp, mb); | ||
2301 | break; | ||
2302 | case 0x13: | ||
2303 | qla24xx_process_response_queue(vha, rsp); | ||
2304 | break; | ||
2305 | default: | ||
2306 | DEBUG2(printk("scsi(%ld): Unrecognized interrupt type " | ||
2307 | "(%d).\n", | ||
2308 | vha->host_no, stat & 0xff)); | ||
2309 | break; | ||
2310 | } | ||
2311 | } | ||
2312 | WRT_REG_DWORD(®->host_int, 0); | ||
2313 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | ||
2314 | } | ||
2315 | |||
2316 | void | ||
2317 | qla82xx_enable_intrs(struct qla_hw_data *ha) | ||
2318 | { | ||
2319 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); | ||
2320 | qla82xx_mbx_intr_enable(vha); | ||
2321 | spin_lock_irq(&ha->hardware_lock); | ||
2322 | qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff); | ||
2323 | spin_unlock_irq(&ha->hardware_lock); | ||
2324 | ha->interrupts_on = 1; | ||
2325 | } | ||
2326 | |||
2327 | void | ||
2328 | qla82xx_disable_intrs(struct qla_hw_data *ha) | ||
2329 | { | ||
2330 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); | ||
2331 | qla82xx_mbx_intr_disable(vha); | ||
2332 | spin_lock_irq(&ha->hardware_lock); | ||
2333 | qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400); | ||
2334 | spin_unlock_irq(&ha->hardware_lock); | ||
2335 | ha->interrupts_on = 0; | ||
2336 | } | ||
2337 | |||
2338 | void qla82xx_init_flags(struct qla_hw_data *ha) | ||
2339 | { | ||
2340 | struct qla82xx_legacy_intr_set *nx_legacy_intr; | ||
2341 | |||
2342 | /* ISP 8021 initializations */ | ||
2343 | rwlock_init(&ha->hw_lock); | ||
2344 | ha->qdr_sn_window = -1; | ||
2345 | ha->ddr_mn_window = -1; | ||
2346 | ha->curr_window = 255; | ||
2347 | ha->portnum = PCI_FUNC(ha->pdev->devfn); | ||
2348 | nx_legacy_intr = &legacy_intr[ha->portnum]; | ||
2349 | ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit; | ||
2350 | ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg; | ||
2351 | ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg; | ||
2352 | ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg; | ||
2353 | } | ||
2354 | |||
2355 | static inline void | ||
2356 | qla82xx_set_drv_active(scsi_qla_host_t *vha) | ||
2357 | { | ||
2358 | uint32_t drv_active; | ||
2359 | struct qla_hw_data *ha = vha->hw; | ||
2360 | |||
2361 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | ||
2362 | |||
2363 | /* If reset value is all FF's, initialize DRV_ACTIVE */ | ||
2364 | if (drv_active == 0xffffffff) { | ||
2365 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, 0); | ||
2366 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | ||
2367 | } | ||
2368 | drv_active |= (1 << (ha->portnum * 4)); | ||
2369 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); | ||
2370 | } | ||
2371 | |||
2372 | inline void | ||
2373 | qla82xx_clear_drv_active(struct qla_hw_data *ha) | ||
2374 | { | ||
2375 | uint32_t drv_active; | ||
2376 | |||
2377 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | ||
2378 | drv_active &= ~(1 << (ha->portnum * 4)); | ||
2379 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active); | ||
2380 | } | ||
2381 | |||
2382 | static inline int | ||
2383 | qla82xx_need_reset(struct qla_hw_data *ha) | ||
2384 | { | ||
2385 | uint32_t drv_state; | ||
2386 | int rval; | ||
2387 | |||
2388 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | ||
2389 | rval = drv_state & (1 << (ha->portnum * 4)); | ||
2390 | return rval; | ||
2391 | } | ||
2392 | |||
2393 | static inline void | ||
2394 | qla82xx_set_rst_ready(struct qla_hw_data *ha) | ||
2395 | { | ||
2396 | uint32_t drv_state; | ||
2397 | scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); | ||
2398 | |||
2399 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | ||
2400 | |||
2401 | /* If reset value is all FF's, initialize DRV_STATE */ | ||
2402 | if (drv_state == 0xffffffff) { | ||
2403 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0); | ||
2404 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | ||
2405 | } | ||
2406 | drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); | ||
2407 | qla_printk(KERN_INFO, ha, | ||
2408 | "%s(%ld):drv_state = 0x%x\n", | ||
2409 | __func__, vha->host_no, drv_state); | ||
2410 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); | ||
2411 | } | ||
2412 | |||
2413 | static inline void | ||
2414 | qla82xx_clear_rst_ready(struct qla_hw_data *ha) | ||
2415 | { | ||
2416 | uint32_t drv_state; | ||
2417 | |||
2418 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | ||
2419 | drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4)); | ||
2420 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state); | ||
2421 | } | ||
2422 | |||
2423 | static inline void | ||
2424 | qla82xx_set_qsnt_ready(struct qla_hw_data *ha) | ||
2425 | { | ||
2426 | uint32_t qsnt_state; | ||
2427 | |||
2428 | qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | ||
2429 | qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4)); | ||
2430 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state); | ||
2431 | } | ||
2432 | |||
2433 | int qla82xx_load_fw(scsi_qla_host_t *vha) | ||
2434 | { | ||
2435 | int rst; | ||
2436 | struct fw_blob *blob; | ||
2437 | struct qla_hw_data *ha = vha->hw; | ||
2438 | |||
2439 | /* Put both the PEG CMD and RCV PEG to default state | ||
2440 | * of 0 before resetting the hardware | ||
2441 | */ | ||
2442 | qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0); | ||
2443 | qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0); | ||
2444 | |||
2445 | if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) { | ||
2446 | qla_printk(KERN_ERR, ha, | ||
2447 | "%s: Error during CRB Initialization\n", __func__); | ||
2448 | return QLA_FUNCTION_FAILED; | ||
2449 | } | ||
2450 | udelay(500); | ||
2451 | |||
2452 | /* Bring QM and CAMRAM out of reset */ | ||
2453 | rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET); | ||
2454 | rst &= ~((1 << 28) | (1 << 24)); | ||
2455 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst); | ||
2456 | |||
2457 | /* | ||
2458 | * FW Load priority: | ||
2459 | * 1) Operational firmware residing in flash. | ||
2460 | * 2) Firmware via request-firmware interface (.bin file). | ||
2461 | */ | ||
2462 | if (ql2xfwloadbin == 2) | ||
2463 | goto try_blob_fw; | ||
2464 | |||
2465 | qla_printk(KERN_INFO, ha, | ||
2466 | "Attempting to load firmware from flash\n"); | ||
2467 | |||
2468 | if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) { | ||
2469 | qla_printk(KERN_ERR, ha, | ||
2470 | "Firmware loaded successfully from flash\n"); | ||
2471 | return QLA_SUCCESS; | ||
2472 | } | ||
2473 | try_blob_fw: | ||
2474 | qla_printk(KERN_INFO, ha, | ||
2475 | "Attempting to load firmware from blob\n"); | ||
2476 | |||
2477 | /* Load firmware blob. */ | ||
2478 | blob = ha->hablob = qla2x00_request_firmware(vha); | ||
2479 | if (!blob) { | ||
2480 | qla_printk(KERN_ERR, ha, | ||
2481 | "Firmware image not present.\n"); | ||
2482 | goto fw_load_failed; | ||
2483 | } | ||
2484 | |||
2485 | if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) { | ||
2486 | qla_printk(KERN_ERR, ha, | ||
2487 | "%s: Firmware loaded successfully " | ||
2488 | " from binary blob\n", __func__); | ||
2489 | return QLA_SUCCESS; | ||
2490 | } else { | ||
2491 | qla_printk(KERN_ERR, ha, | ||
2492 | "Firmware load failed from binary blob\n"); | ||
2493 | blob->fw = NULL; | ||
2494 | blob = NULL; | ||
2495 | goto fw_load_failed; | ||
2496 | } | ||
2497 | return QLA_SUCCESS; | ||
2498 | |||
2499 | fw_load_failed: | ||
2500 | return QLA_FUNCTION_FAILED; | ||
2501 | } | ||
2502 | |||
2503 | static int | ||
2504 | qla82xx_start_firmware(scsi_qla_host_t *vha) | ||
2505 | { | ||
2506 | int pcie_cap; | ||
2507 | uint16_t lnk; | ||
2508 | struct qla_hw_data *ha = vha->hw; | ||
2509 | |||
2510 | /* scrub dma mask expansion register */ | ||
2511 | qla82xx_wr_32(ha, CRB_DMA_SHIFT, 0x55555555); | ||
2512 | |||
2513 | /* Overwrite stale initialization register values */ | ||
2514 | qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0); | ||
2515 | qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0); | ||
2516 | |||
2517 | if (qla82xx_load_fw(vha) != QLA_SUCCESS) { | ||
2518 | qla_printk(KERN_INFO, ha, | ||
2519 | "%s: Error trying to start fw!\n", __func__); | ||
2520 | return QLA_FUNCTION_FAILED; | ||
2521 | } | ||
2522 | |||
2523 | /* Handshake with the card before we register the devices. */ | ||
2524 | if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) { | ||
2525 | qla_printk(KERN_INFO, ha, | ||
2526 | "%s: Error during card handshake!\n", __func__); | ||
2527 | return QLA_FUNCTION_FAILED; | ||
2528 | } | ||
2529 | |||
2530 | /* Negotiated Link width */ | ||
2531 | pcie_cap = pci_find_capability(ha->pdev, PCI_CAP_ID_EXP); | ||
2532 | pci_read_config_word(ha->pdev, pcie_cap + PCI_EXP_LNKSTA, &lnk); | ||
2533 | ha->link_width = (lnk >> 4) & 0x3f; | ||
2534 | |||
2535 | /* Synchronize with Receive peg */ | ||
2536 | return qla82xx_check_rcvpeg_state(ha); | ||
2537 | } | ||
2538 | |||
2539 | static inline int | ||
2540 | qla2xx_build_scsi_type_6_iocbs(srb_t *sp, struct cmd_type_6 *cmd_pkt, | ||
2541 | uint16_t tot_dsds) | ||
2542 | { | ||
2543 | uint32_t *cur_dsd = NULL; | ||
2544 | scsi_qla_host_t *vha; | ||
2545 | struct qla_hw_data *ha; | ||
2546 | struct scsi_cmnd *cmd; | ||
2547 | struct scatterlist *cur_seg; | ||
2548 | uint32_t *dsd_seg; | ||
2549 | void *next_dsd; | ||
2550 | uint8_t avail_dsds; | ||
2551 | uint8_t first_iocb = 1; | ||
2552 | uint32_t dsd_list_len; | ||
2553 | struct dsd_dma *dsd_ptr; | ||
2554 | struct ct6_dsd *ctx; | ||
2555 | |||
2556 | cmd = sp->cmd; | ||
2557 | |||
2558 | /* Update entry type to indicate Command Type 3 IOCB */ | ||
2559 | *((uint32_t *)(&cmd_pkt->entry_type)) = | ||
2560 | __constant_cpu_to_le32(COMMAND_TYPE_6); | ||
2561 | |||
2562 | /* No data transfer */ | ||
2563 | if (!scsi_bufflen(cmd) || cmd->sc_data_direction == DMA_NONE) { | ||
2564 | cmd_pkt->byte_count = __constant_cpu_to_le32(0); | ||
2565 | return 0; | ||
2566 | } | ||
2567 | |||
2568 | vha = sp->fcport->vha; | ||
2569 | ha = vha->hw; | ||
2570 | |||
2571 | /* Set transfer direction */ | ||
2572 | if (cmd->sc_data_direction == DMA_TO_DEVICE) { | ||
2573 | cmd_pkt->control_flags = | ||
2574 | __constant_cpu_to_le16(CF_WRITE_DATA); | ||
2575 | ha->qla_stats.output_bytes += scsi_bufflen(cmd); | ||
2576 | } else if (cmd->sc_data_direction == DMA_FROM_DEVICE) { | ||
2577 | cmd_pkt->control_flags = | ||
2578 | __constant_cpu_to_le16(CF_READ_DATA); | ||
2579 | ha->qla_stats.input_bytes += scsi_bufflen(cmd); | ||
2580 | } | ||
2581 | |||
2582 | cur_seg = scsi_sglist(cmd); | ||
2583 | ctx = sp->ctx; | ||
2584 | |||
2585 | while (tot_dsds) { | ||
2586 | avail_dsds = (tot_dsds > QLA_DSDS_PER_IOCB) ? | ||
2587 | QLA_DSDS_PER_IOCB : tot_dsds; | ||
2588 | tot_dsds -= avail_dsds; | ||
2589 | dsd_list_len = (avail_dsds + 1) * QLA_DSD_SIZE; | ||
2590 | |||
2591 | dsd_ptr = list_first_entry(&ha->gbl_dsd_list, | ||
2592 | struct dsd_dma, list); | ||
2593 | next_dsd = dsd_ptr->dsd_addr; | ||
2594 | list_del(&dsd_ptr->list); | ||
2595 | ha->gbl_dsd_avail--; | ||
2596 | list_add_tail(&dsd_ptr->list, &ctx->dsd_list); | ||
2597 | ctx->dsd_use_cnt++; | ||
2598 | ha->gbl_dsd_inuse++; | ||
2599 | |||
2600 | if (first_iocb) { | ||
2601 | first_iocb = 0; | ||
2602 | dsd_seg = (uint32_t *)&cmd_pkt->fcp_data_dseg_address; | ||
2603 | *dsd_seg++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); | ||
2604 | *dsd_seg++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); | ||
2605 | *dsd_seg++ = dsd_list_len; | ||
2606 | } else { | ||
2607 | *cur_dsd++ = cpu_to_le32(LSD(dsd_ptr->dsd_list_dma)); | ||
2608 | *cur_dsd++ = cpu_to_le32(MSD(dsd_ptr->dsd_list_dma)); | ||
2609 | *cur_dsd++ = dsd_list_len; | ||
2610 | } | ||
2611 | cur_dsd = (uint32_t *)next_dsd; | ||
2612 | while (avail_dsds) { | ||
2613 | dma_addr_t sle_dma; | ||
2614 | |||
2615 | sle_dma = sg_dma_address(cur_seg); | ||
2616 | *cur_dsd++ = cpu_to_le32(LSD(sle_dma)); | ||
2617 | *cur_dsd++ = cpu_to_le32(MSD(sle_dma)); | ||
2618 | *cur_dsd++ = cpu_to_le32(sg_dma_len(cur_seg)); | ||
2619 | cur_seg++; | ||
2620 | avail_dsds--; | ||
2621 | } | ||
2622 | } | ||
2623 | |||
2624 | /* Null termination */ | ||
2625 | *cur_dsd++ = 0; | ||
2626 | *cur_dsd++ = 0; | ||
2627 | *cur_dsd++ = 0; | ||
2628 | cmd_pkt->control_flags |= CF_DATA_SEG_DESCR_ENABLE; | ||
2629 | return 0; | ||
2630 | } | ||
2631 | |||
2632 | /* | ||
2633 | * qla82xx_calc_dsd_lists() - Determine number of DSD list required | ||
2634 | * for Command Type 6. | ||
2635 | * | ||
2636 | * @dsds: number of data segment decriptors needed | ||
2637 | * | ||
2638 | * Returns the number of dsd list needed to store @dsds. | ||
2639 | */ | ||
2640 | inline uint16_t | ||
2641 | qla82xx_calc_dsd_lists(uint16_t dsds) | ||
2642 | { | ||
2643 | uint16_t dsd_lists = 0; | ||
2644 | |||
2645 | dsd_lists = (dsds/QLA_DSDS_PER_IOCB); | ||
2646 | if (dsds % QLA_DSDS_PER_IOCB) | ||
2647 | dsd_lists++; | ||
2648 | return dsd_lists; | ||
2649 | } | ||
2650 | |||
2651 | /* | ||
2652 | * qla82xx_start_scsi() - Send a SCSI command to the ISP | ||
2653 | * @sp: command to send to the ISP | ||
2654 | * | ||
2655 | * Returns non-zero if a failure occured, else zero. | ||
2656 | */ | ||
2657 | int | ||
2658 | qla82xx_start_scsi(srb_t *sp) | ||
2659 | { | ||
2660 | int ret, nseg; | ||
2661 | unsigned long flags; | ||
2662 | struct scsi_cmnd *cmd; | ||
2663 | uint32_t *clr_ptr; | ||
2664 | uint32_t index; | ||
2665 | uint32_t handle; | ||
2666 | uint16_t cnt; | ||
2667 | uint16_t req_cnt; | ||
2668 | uint16_t tot_dsds; | ||
2669 | struct device_reg_82xx __iomem *reg; | ||
2670 | uint32_t dbval; | ||
2671 | uint32_t *fcp_dl; | ||
2672 | uint8_t additional_cdb_len; | ||
2673 | struct ct6_dsd *ctx; | ||
2674 | struct scsi_qla_host *vha = sp->fcport->vha; | ||
2675 | struct qla_hw_data *ha = vha->hw; | ||
2676 | struct req_que *req = NULL; | ||
2677 | struct rsp_que *rsp = NULL; | ||
2678 | |||
2679 | /* Setup device pointers. */ | ||
2680 | ret = 0; | ||
2681 | reg = &ha->iobase->isp82; | ||
2682 | cmd = sp->cmd; | ||
2683 | req = vha->req; | ||
2684 | rsp = ha->rsp_q_map[0]; | ||
2685 | |||
2686 | /* So we know we haven't pci_map'ed anything yet */ | ||
2687 | tot_dsds = 0; | ||
2688 | |||
2689 | dbval = 0x04 | (ha->portnum << 5); | ||
2690 | |||
2691 | /* Send marker if required */ | ||
2692 | if (vha->marker_needed != 0) { | ||
2693 | if (qla2x00_marker(vha, req, | ||
2694 | rsp, 0, 0, MK_SYNC_ALL) != QLA_SUCCESS) | ||
2695 | return QLA_FUNCTION_FAILED; | ||
2696 | vha->marker_needed = 0; | ||
2697 | } | ||
2698 | |||
2699 | /* Acquire ring specific lock */ | ||
2700 | spin_lock_irqsave(&ha->hardware_lock, flags); | ||
2701 | |||
2702 | /* Check for room in outstanding command list. */ | ||
2703 | handle = req->current_outstanding_cmd; | ||
2704 | for (index = 1; index < MAX_OUTSTANDING_COMMANDS; index++) { | ||
2705 | handle++; | ||
2706 | if (handle == MAX_OUTSTANDING_COMMANDS) | ||
2707 | handle = 1; | ||
2708 | if (!req->outstanding_cmds[handle]) | ||
2709 | break; | ||
2710 | } | ||
2711 | if (index == MAX_OUTSTANDING_COMMANDS) | ||
2712 | goto queuing_error; | ||
2713 | |||
2714 | /* Map the sg table so we have an accurate count of sg entries needed */ | ||
2715 | if (scsi_sg_count(cmd)) { | ||
2716 | nseg = dma_map_sg(&ha->pdev->dev, scsi_sglist(cmd), | ||
2717 | scsi_sg_count(cmd), cmd->sc_data_direction); | ||
2718 | if (unlikely(!nseg)) | ||
2719 | goto queuing_error; | ||
2720 | } else | ||
2721 | nseg = 0; | ||
2722 | |||
2723 | tot_dsds = nseg; | ||
2724 | |||
2725 | if (tot_dsds > ql2xshiftctondsd) { | ||
2726 | struct cmd_type_6 *cmd_pkt; | ||
2727 | uint16_t more_dsd_lists = 0; | ||
2728 | struct dsd_dma *dsd_ptr; | ||
2729 | uint16_t i; | ||
2730 | |||
2731 | more_dsd_lists = qla82xx_calc_dsd_lists(tot_dsds); | ||
2732 | if ((more_dsd_lists + ha->gbl_dsd_inuse) >= NUM_DSD_CHAIN) | ||
2733 | goto queuing_error; | ||
2734 | |||
2735 | if (more_dsd_lists <= ha->gbl_dsd_avail) | ||
2736 | goto sufficient_dsds; | ||
2737 | else | ||
2738 | more_dsd_lists -= ha->gbl_dsd_avail; | ||
2739 | |||
2740 | for (i = 0; i < more_dsd_lists; i++) { | ||
2741 | dsd_ptr = kzalloc(sizeof(struct dsd_dma), GFP_ATOMIC); | ||
2742 | if (!dsd_ptr) | ||
2743 | goto queuing_error; | ||
2744 | |||
2745 | dsd_ptr->dsd_addr = dma_pool_alloc(ha->dl_dma_pool, | ||
2746 | GFP_ATOMIC, &dsd_ptr->dsd_list_dma); | ||
2747 | if (!dsd_ptr->dsd_addr) { | ||
2748 | kfree(dsd_ptr); | ||
2749 | goto queuing_error; | ||
2750 | } | ||
2751 | list_add_tail(&dsd_ptr->list, &ha->gbl_dsd_list); | ||
2752 | ha->gbl_dsd_avail++; | ||
2753 | } | ||
2754 | |||
2755 | sufficient_dsds: | ||
2756 | req_cnt = 1; | ||
2757 | |||
2758 | ctx = sp->ctx = mempool_alloc(ha->ctx_mempool, GFP_ATOMIC); | ||
2759 | if (!sp->ctx) { | ||
2760 | DEBUG(printk(KERN_INFO | ||
2761 | "%s(%ld): failed to allocate" | ||
2762 | " ctx.\n", __func__, vha->host_no)); | ||
2763 | goto queuing_error; | ||
2764 | } | ||
2765 | memset(ctx, 0, sizeof(struct ct6_dsd)); | ||
2766 | ctx->fcp_cmnd = dma_pool_alloc(ha->fcp_cmnd_dma_pool, | ||
2767 | GFP_ATOMIC, &ctx->fcp_cmnd_dma); | ||
2768 | if (!ctx->fcp_cmnd) { | ||
2769 | DEBUG2_3(printk("%s(%ld): failed to allocate" | ||
2770 | " fcp_cmnd.\n", __func__, vha->host_no)); | ||
2771 | goto queuing_error_fcp_cmnd; | ||
2772 | } | ||
2773 | |||
2774 | /* Initialize the DSD list and dma handle */ | ||
2775 | INIT_LIST_HEAD(&ctx->dsd_list); | ||
2776 | ctx->dsd_use_cnt = 0; | ||
2777 | |||
2778 | if (cmd->cmd_len > 16) { | ||
2779 | additional_cdb_len = cmd->cmd_len - 16; | ||
2780 | if ((cmd->cmd_len % 4) != 0) { | ||
2781 | /* SCSI command bigger than 16 bytes must be | ||
2782 | * multiple of 4 | ||
2783 | */ | ||
2784 | goto queuing_error_fcp_cmnd; | ||
2785 | } | ||
2786 | ctx->fcp_cmnd_len = 12 + cmd->cmd_len + 4; | ||
2787 | } else { | ||
2788 | additional_cdb_len = 0; | ||
2789 | ctx->fcp_cmnd_len = 12 + 16 + 4; | ||
2790 | } | ||
2791 | |||
2792 | cmd_pkt = (struct cmd_type_6 *)req->ring_ptr; | ||
2793 | cmd_pkt->handle = MAKE_HANDLE(req->id, handle); | ||
2794 | |||
2795 | /* Zero out remaining portion of packet. */ | ||
2796 | /* tagged queuing modifier -- default is TSK_SIMPLE (0). */ | ||
2797 | clr_ptr = (uint32_t *)cmd_pkt + 2; | ||
2798 | memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); | ||
2799 | cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); | ||
2800 | |||
2801 | /* Set NPORT-ID and LUN number*/ | ||
2802 | cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); | ||
2803 | cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; | ||
2804 | cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; | ||
2805 | cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; | ||
2806 | cmd_pkt->vp_index = sp->fcport->vp_idx; | ||
2807 | |||
2808 | /* Build IOCB segments */ | ||
2809 | if (qla2xx_build_scsi_type_6_iocbs(sp, cmd_pkt, tot_dsds)) | ||
2810 | goto queuing_error_fcp_cmnd; | ||
2811 | |||
2812 | int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); | ||
2813 | |||
2814 | /* build FCP_CMND IU */ | ||
2815 | memset(ctx->fcp_cmnd, 0, sizeof(struct fcp_cmnd)); | ||
2816 | int_to_scsilun(sp->cmd->device->lun, &ctx->fcp_cmnd->lun); | ||
2817 | ctx->fcp_cmnd->additional_cdb_len = additional_cdb_len; | ||
2818 | |||
2819 | if (cmd->sc_data_direction == DMA_TO_DEVICE) | ||
2820 | ctx->fcp_cmnd->additional_cdb_len |= 1; | ||
2821 | else if (cmd->sc_data_direction == DMA_FROM_DEVICE) | ||
2822 | ctx->fcp_cmnd->additional_cdb_len |= 2; | ||
2823 | |||
2824 | memcpy(ctx->fcp_cmnd->cdb, cmd->cmnd, cmd->cmd_len); | ||
2825 | |||
2826 | fcp_dl = (uint32_t *)(ctx->fcp_cmnd->cdb + 16 + | ||
2827 | additional_cdb_len); | ||
2828 | *fcp_dl = htonl((uint32_t)scsi_bufflen(cmd)); | ||
2829 | |||
2830 | cmd_pkt->fcp_cmnd_dseg_len = cpu_to_le16(ctx->fcp_cmnd_len); | ||
2831 | cmd_pkt->fcp_cmnd_dseg_address[0] = | ||
2832 | cpu_to_le32(LSD(ctx->fcp_cmnd_dma)); | ||
2833 | cmd_pkt->fcp_cmnd_dseg_address[1] = | ||
2834 | cpu_to_le32(MSD(ctx->fcp_cmnd_dma)); | ||
2835 | |||
2836 | sp->flags |= SRB_FCP_CMND_DMA_VALID; | ||
2837 | cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); | ||
2838 | /* Set total data segment count. */ | ||
2839 | cmd_pkt->entry_count = (uint8_t)req_cnt; | ||
2840 | /* Specify response queue number where | ||
2841 | * completion should happen | ||
2842 | */ | ||
2843 | cmd_pkt->entry_status = (uint8_t) rsp->id; | ||
2844 | } else { | ||
2845 | struct cmd_type_7 *cmd_pkt; | ||
2846 | req_cnt = qla24xx_calc_iocbs(tot_dsds); | ||
2847 | if (req->cnt < (req_cnt + 2)) { | ||
2848 | cnt = (uint16_t)RD_REG_DWORD_RELAXED( | ||
2849 | ®->req_q_out[0]); | ||
2850 | if (req->ring_index < cnt) | ||
2851 | req->cnt = cnt - req->ring_index; | ||
2852 | else | ||
2853 | req->cnt = req->length - | ||
2854 | (req->ring_index - cnt); | ||
2855 | } | ||
2856 | if (req->cnt < (req_cnt + 2)) | ||
2857 | goto queuing_error; | ||
2858 | |||
2859 | cmd_pkt = (struct cmd_type_7 *)req->ring_ptr; | ||
2860 | cmd_pkt->handle = MAKE_HANDLE(req->id, handle); | ||
2861 | |||
2862 | /* Zero out remaining portion of packet. */ | ||
2863 | /* tagged queuing modifier -- default is TSK_SIMPLE (0).*/ | ||
2864 | clr_ptr = (uint32_t *)cmd_pkt + 2; | ||
2865 | memset(clr_ptr, 0, REQUEST_ENTRY_SIZE - 8); | ||
2866 | cmd_pkt->dseg_count = cpu_to_le16(tot_dsds); | ||
2867 | |||
2868 | /* Set NPORT-ID and LUN number*/ | ||
2869 | cmd_pkt->nport_handle = cpu_to_le16(sp->fcport->loop_id); | ||
2870 | cmd_pkt->port_id[0] = sp->fcport->d_id.b.al_pa; | ||
2871 | cmd_pkt->port_id[1] = sp->fcport->d_id.b.area; | ||
2872 | cmd_pkt->port_id[2] = sp->fcport->d_id.b.domain; | ||
2873 | cmd_pkt->vp_index = sp->fcport->vp_idx; | ||
2874 | |||
2875 | int_to_scsilun(sp->cmd->device->lun, &cmd_pkt->lun); | ||
2876 | host_to_fcp_swap((uint8_t *)&cmd_pkt->lun, | ||
2877 | sizeof(cmd_pkt->lun)); | ||
2878 | |||
2879 | /* Load SCSI command packet. */ | ||
2880 | memcpy(cmd_pkt->fcp_cdb, cmd->cmnd, cmd->cmd_len); | ||
2881 | host_to_fcp_swap(cmd_pkt->fcp_cdb, sizeof(cmd_pkt->fcp_cdb)); | ||
2882 | |||
2883 | cmd_pkt->byte_count = cpu_to_le32((uint32_t)scsi_bufflen(cmd)); | ||
2884 | |||
2885 | /* Build IOCB segments */ | ||
2886 | qla24xx_build_scsi_iocbs(sp, cmd_pkt, tot_dsds); | ||
2887 | |||
2888 | /* Set total data segment count. */ | ||
2889 | cmd_pkt->entry_count = (uint8_t)req_cnt; | ||
2890 | /* Specify response queue number where | ||
2891 | * completion should happen. | ||
2892 | */ | ||
2893 | cmd_pkt->entry_status = (uint8_t) rsp->id; | ||
2894 | |||
2895 | } | ||
2896 | /* Build command packet. */ | ||
2897 | req->current_outstanding_cmd = handle; | ||
2898 | req->outstanding_cmds[handle] = sp; | ||
2899 | sp->handle = handle; | ||
2900 | sp->cmd->host_scribble = (unsigned char *)(unsigned long)handle; | ||
2901 | req->cnt -= req_cnt; | ||
2902 | wmb(); | ||
2903 | |||
2904 | /* Adjust ring index. */ | ||
2905 | req->ring_index++; | ||
2906 | if (req->ring_index == req->length) { | ||
2907 | req->ring_index = 0; | ||
2908 | req->ring_ptr = req->ring; | ||
2909 | } else | ||
2910 | req->ring_ptr++; | ||
2911 | |||
2912 | sp->flags |= SRB_DMA_VALID; | ||
2913 | |||
2914 | /* Set chip new ring index. */ | ||
2915 | /* write, read and verify logic */ | ||
2916 | dbval = dbval | (req->id << 8) | (req->ring_index << 16); | ||
2917 | if (ql2xdbwr) | ||
2918 | qla82xx_wr_32(ha, ha->nxdb_wr_ptr, dbval); | ||
2919 | else { | ||
2920 | WRT_REG_DWORD( | ||
2921 | (unsigned long __iomem *)ha->nxdb_wr_ptr, | ||
2922 | dbval); | ||
2923 | wmb(); | ||
2924 | while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { | ||
2925 | WRT_REG_DWORD( | ||
2926 | (unsigned long __iomem *)ha->nxdb_wr_ptr, | ||
2927 | dbval); | ||
2928 | wmb(); | ||
2929 | } | ||
2930 | } | ||
2931 | |||
2932 | /* Manage unprocessed RIO/ZIO commands in response queue. */ | ||
2933 | if (vha->flags.process_response_queue && | ||
2934 | rsp->ring_ptr->signature != RESPONSE_PROCESSED) | ||
2935 | qla24xx_process_response_queue(vha, rsp); | ||
2936 | |||
2937 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | ||
2938 | return QLA_SUCCESS; | ||
2939 | |||
2940 | queuing_error_fcp_cmnd: | ||
2941 | dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd, ctx->fcp_cmnd_dma); | ||
2942 | queuing_error: | ||
2943 | if (tot_dsds) | ||
2944 | scsi_dma_unmap(cmd); | ||
2945 | |||
2946 | if (sp->ctx) { | ||
2947 | mempool_free(sp->ctx, ha->ctx_mempool); | ||
2948 | sp->ctx = NULL; | ||
2949 | } | ||
2950 | spin_unlock_irqrestore(&ha->hardware_lock, flags); | ||
2951 | |||
2952 | return QLA_FUNCTION_FAILED; | ||
2953 | } | ||
2954 | |||
2955 | uint32_t * | ||
2956 | qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, | ||
2957 | uint32_t length) | ||
2958 | { | ||
2959 | uint32_t i; | ||
2960 | uint32_t val; | ||
2961 | struct qla_hw_data *ha = vha->hw; | ||
2962 | |||
2963 | /* Dword reads to flash. */ | ||
2964 | for (i = 0; i < length/4; i++, faddr += 4) { | ||
2965 | if (qla82xx_rom_fast_read(ha, faddr, &val)) { | ||
2966 | qla_printk(KERN_WARNING, ha, | ||
2967 | "Do ROM fast read failed\n"); | ||
2968 | goto done_read; | ||
2969 | } | ||
2970 | dwptr[i] = __constant_cpu_to_le32(val); | ||
2971 | } | ||
2972 | done_read: | ||
2973 | return dwptr; | ||
2974 | } | ||
2975 | |||
2976 | int | ||
2977 | qla82xx_unprotect_flash(struct qla_hw_data *ha) | ||
2978 | { | ||
2979 | int ret; | ||
2980 | uint32_t val; | ||
2981 | |||
2982 | ret = ql82xx_rom_lock_d(ha); | ||
2983 | if (ret < 0) { | ||
2984 | qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); | ||
2985 | return ret; | ||
2986 | } | ||
2987 | |||
2988 | ret = qla82xx_read_status_reg(ha, &val); | ||
2989 | if (ret < 0) | ||
2990 | goto done_unprotect; | ||
2991 | |||
2992 | val &= ~(0x7 << 2); | ||
2993 | ret = qla82xx_write_status_reg(ha, val); | ||
2994 | if (ret < 0) { | ||
2995 | val |= (0x7 << 2); | ||
2996 | qla82xx_write_status_reg(ha, val); | ||
2997 | } | ||
2998 | |||
2999 | if (qla82xx_write_disable_flash(ha) != 0) | ||
3000 | qla_printk(KERN_WARNING, ha, "Write disable failed\n"); | ||
3001 | |||
3002 | done_unprotect: | ||
3003 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); | ||
3004 | return ret; | ||
3005 | } | ||
3006 | |||
3007 | int | ||
3008 | qla82xx_protect_flash(struct qla_hw_data *ha) | ||
3009 | { | ||
3010 | int ret; | ||
3011 | uint32_t val; | ||
3012 | |||
3013 | ret = ql82xx_rom_lock_d(ha); | ||
3014 | if (ret < 0) { | ||
3015 | qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); | ||
3016 | return ret; | ||
3017 | } | ||
3018 | |||
3019 | ret = qla82xx_read_status_reg(ha, &val); | ||
3020 | if (ret < 0) | ||
3021 | goto done_protect; | ||
3022 | |||
3023 | val |= (0x7 << 2); | ||
3024 | /* LOCK all sectors */ | ||
3025 | ret = qla82xx_write_status_reg(ha, val); | ||
3026 | if (ret < 0) | ||
3027 | qla_printk(KERN_WARNING, ha, "Write status register failed\n"); | ||
3028 | |||
3029 | if (qla82xx_write_disable_flash(ha) != 0) | ||
3030 | qla_printk(KERN_WARNING, ha, "Write disable failed\n"); | ||
3031 | done_protect: | ||
3032 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); | ||
3033 | return ret; | ||
3034 | } | ||
3035 | |||
3036 | int | ||
3037 | qla82xx_erase_sector(struct qla_hw_data *ha, int addr) | ||
3038 | { | ||
3039 | int ret = 0; | ||
3040 | |||
3041 | ret = ql82xx_rom_lock_d(ha); | ||
3042 | if (ret < 0) { | ||
3043 | qla_printk(KERN_WARNING, ha, "ROM Lock failed\n"); | ||
3044 | return ret; | ||
3045 | } | ||
3046 | |||
3047 | qla82xx_flash_set_write_enable(ha); | ||
3048 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr); | ||
3049 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3); | ||
3050 | qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE); | ||
3051 | |||
3052 | if (qla82xx_wait_rom_done(ha)) { | ||
3053 | qla_printk(KERN_WARNING, ha, | ||
3054 | "Error waiting for rom done\n"); | ||
3055 | ret = -1; | ||
3056 | goto done; | ||
3057 | } | ||
3058 | ret = qla82xx_flash_wait_write_finish(ha); | ||
3059 | done: | ||
3060 | qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK)); | ||
3061 | return ret; | ||
3062 | } | ||
3063 | |||
3064 | /* | ||
3065 | * Address and length are byte address | ||
3066 | */ | ||
3067 | uint8_t * | ||
3068 | qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, | ||
3069 | uint32_t offset, uint32_t length) | ||
3070 | { | ||
3071 | scsi_block_requests(vha->host); | ||
3072 | qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length); | ||
3073 | scsi_unblock_requests(vha->host); | ||
3074 | return buf; | ||
3075 | } | ||
3076 | |||
3077 | static int | ||
3078 | qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr, | ||
3079 | uint32_t faddr, uint32_t dwords) | ||
3080 | { | ||
3081 | int ret; | ||
3082 | uint32_t liter; | ||
3083 | uint32_t sec_mask, rest_addr; | ||
3084 | dma_addr_t optrom_dma; | ||
3085 | void *optrom = NULL; | ||
3086 | int page_mode = 0; | ||
3087 | struct qla_hw_data *ha = vha->hw; | ||
3088 | |||
3089 | ret = -1; | ||
3090 | |||
3091 | /* Prepare burst-capable write on supported ISPs. */ | ||
3092 | if (page_mode && !(faddr & 0xfff) && | ||
3093 | dwords > OPTROM_BURST_DWORDS) { | ||
3094 | optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, | ||
3095 | &optrom_dma, GFP_KERNEL); | ||
3096 | if (!optrom) { | ||
3097 | qla_printk(KERN_DEBUG, ha, | ||
3098 | "Unable to allocate memory for optrom " | ||
3099 | "burst write (%x KB).\n", | ||
3100 | OPTROM_BURST_SIZE / 1024); | ||
3101 | } | ||
3102 | } | ||
3103 | |||
3104 | rest_addr = ha->fdt_block_size - 1; | ||
3105 | sec_mask = ~rest_addr; | ||
3106 | |||
3107 | ret = qla82xx_unprotect_flash(ha); | ||
3108 | if (ret) { | ||
3109 | qla_printk(KERN_WARNING, ha, | ||
3110 | "Unable to unprotect flash for update.\n"); | ||
3111 | goto write_done; | ||
3112 | } | ||
3113 | |||
3114 | for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { | ||
3115 | /* Are we at the beginning of a sector? */ | ||
3116 | if ((faddr & rest_addr) == 0) { | ||
3117 | |||
3118 | ret = qla82xx_erase_sector(ha, faddr); | ||
3119 | if (ret) { | ||
3120 | DEBUG9(qla_printk(KERN_ERR, ha, | ||
3121 | "Unable to erase sector: " | ||
3122 | "address=%x.\n", faddr)); | ||
3123 | break; | ||
3124 | } | ||
3125 | } | ||
3126 | |||
3127 | /* Go with burst-write. */ | ||
3128 | if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) { | ||
3129 | /* Copy data to DMA'ble buffer. */ | ||
3130 | memcpy(optrom, dwptr, OPTROM_BURST_SIZE); | ||
3131 | |||
3132 | ret = qla2x00_load_ram(vha, optrom_dma, | ||
3133 | (ha->flash_data_off | faddr), | ||
3134 | OPTROM_BURST_DWORDS); | ||
3135 | if (ret != QLA_SUCCESS) { | ||
3136 | qla_printk(KERN_WARNING, ha, | ||
3137 | "Unable to burst-write optrom segment " | ||
3138 | "(%x/%x/%llx).\n", ret, | ||
3139 | (ha->flash_data_off | faddr), | ||
3140 | (unsigned long long)optrom_dma); | ||
3141 | qla_printk(KERN_WARNING, ha, | ||
3142 | "Reverting to slow-write.\n"); | ||
3143 | |||
3144 | dma_free_coherent(&ha->pdev->dev, | ||
3145 | OPTROM_BURST_SIZE, optrom, optrom_dma); | ||
3146 | optrom = NULL; | ||
3147 | } else { | ||
3148 | liter += OPTROM_BURST_DWORDS - 1; | ||
3149 | faddr += OPTROM_BURST_DWORDS - 1; | ||
3150 | dwptr += OPTROM_BURST_DWORDS - 1; | ||
3151 | continue; | ||
3152 | } | ||
3153 | } | ||
3154 | |||
3155 | ret = qla82xx_write_flash_dword(ha, faddr, | ||
3156 | cpu_to_le32(*dwptr)); | ||
3157 | if (ret) { | ||
3158 | DEBUG9(printk(KERN_DEBUG "%s(%ld) Unable to program" | ||
3159 | "flash address=%x data=%x.\n", __func__, | ||
3160 | ha->host_no, faddr, *dwptr)); | ||
3161 | break; | ||
3162 | } | ||
3163 | } | ||
3164 | |||
3165 | ret = qla82xx_protect_flash(ha); | ||
3166 | if (ret) | ||
3167 | qla_printk(KERN_WARNING, ha, | ||
3168 | "Unable to protect flash after update.\n"); | ||
3169 | write_done: | ||
3170 | if (optrom) | ||
3171 | dma_free_coherent(&ha->pdev->dev, | ||
3172 | OPTROM_BURST_SIZE, optrom, optrom_dma); | ||
3173 | return ret; | ||
3174 | } | ||
3175 | |||
3176 | int | ||
3177 | qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, | ||
3178 | uint32_t offset, uint32_t length) | ||
3179 | { | ||
3180 | int rval; | ||
3181 | |||
3182 | /* Suspend HBA. */ | ||
3183 | scsi_block_requests(vha->host); | ||
3184 | rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset, | ||
3185 | length >> 2); | ||
3186 | scsi_unblock_requests(vha->host); | ||
3187 | |||
3188 | /* Convert return ISP82xx to generic */ | ||
3189 | if (rval) | ||
3190 | rval = QLA_FUNCTION_FAILED; | ||
3191 | else | ||
3192 | rval = QLA_SUCCESS; | ||
3193 | return rval; | ||
3194 | } | ||
3195 | |||
3196 | void | ||
3197 | qla82xx_start_iocbs(srb_t *sp) | ||
3198 | { | ||
3199 | struct qla_hw_data *ha = sp->fcport->vha->hw; | ||
3200 | struct req_que *req = ha->req_q_map[0]; | ||
3201 | struct device_reg_82xx __iomem *reg; | ||
3202 | uint32_t dbval; | ||
3203 | |||
3204 | /* Adjust ring index. */ | ||
3205 | req->ring_index++; | ||
3206 | if (req->ring_index == req->length) { | ||
3207 | req->ring_index = 0; | ||
3208 | req->ring_ptr = req->ring; | ||
3209 | } else | ||
3210 | req->ring_ptr++; | ||
3211 | |||
3212 | reg = &ha->iobase->isp82; | ||
3213 | dbval = 0x04 | (ha->portnum << 5); | ||
3214 | |||
3215 | dbval = dbval | (req->id << 8) | (req->ring_index << 16); | ||
3216 | WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); | ||
3217 | wmb(); | ||
3218 | while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) { | ||
3219 | WRT_REG_DWORD((unsigned long __iomem *)ha->nxdb_wr_ptr, dbval); | ||
3220 | wmb(); | ||
3221 | } | ||
3222 | } | ||
3223 | |||
3224 | /* | ||
3225 | * qla82xx_device_bootstrap | ||
3226 | * Initialize device, set DEV_READY, start fw | ||
3227 | * | ||
3228 | * Note: | ||
3229 | * IDC lock must be held upon entry | ||
3230 | * | ||
3231 | * Return: | ||
3232 | * Success : 0 | ||
3233 | * Failed : 1 | ||
3234 | */ | ||
3235 | static int | ||
3236 | qla82xx_device_bootstrap(scsi_qla_host_t *vha) | ||
3237 | { | ||
3238 | int rval, i, timeout; | ||
3239 | uint32_t old_count, count; | ||
3240 | struct qla_hw_data *ha = vha->hw; | ||
3241 | |||
3242 | if (qla82xx_need_reset(ha)) | ||
3243 | goto dev_initialize; | ||
3244 | |||
3245 | old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); | ||
3246 | |||
3247 | for (i = 0; i < 10; i++) { | ||
3248 | timeout = msleep_interruptible(200); | ||
3249 | if (timeout) { | ||
3250 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | ||
3251 | QLA82XX_DEV_FAILED); | ||
3252 | return QLA_FUNCTION_FAILED; | ||
3253 | } | ||
3254 | |||
3255 | count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); | ||
3256 | if (count != old_count) | ||
3257 | goto dev_ready; | ||
3258 | } | ||
3259 | |||
3260 | dev_initialize: | ||
3261 | /* set to DEV_INITIALIZING */ | ||
3262 | qla_printk(KERN_INFO, ha, "HW State: INITIALIZING\n"); | ||
3263 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_INITIALIZING); | ||
3264 | |||
3265 | /* Driver that sets device state to initializating sets IDC version */ | ||
3266 | qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION, QLA82XX_IDC_VERSION); | ||
3267 | |||
3268 | qla82xx_idc_unlock(ha); | ||
3269 | rval = qla82xx_start_firmware(vha); | ||
3270 | qla82xx_idc_lock(ha); | ||
3271 | |||
3272 | if (rval != QLA_SUCCESS) { | ||
3273 | qla_printk(KERN_INFO, ha, "HW State: FAILED\n"); | ||
3274 | qla82xx_clear_drv_active(ha); | ||
3275 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_FAILED); | ||
3276 | return rval; | ||
3277 | } | ||
3278 | |||
3279 | dev_ready: | ||
3280 | qla_printk(KERN_INFO, ha, "HW State: READY\n"); | ||
3281 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_READY); | ||
3282 | |||
3283 | return QLA_SUCCESS; | ||
3284 | } | ||
3285 | |||
3286 | static void | ||
3287 | qla82xx_dev_failed_handler(scsi_qla_host_t *vha) | ||
3288 | { | ||
3289 | struct qla_hw_data *ha = vha->hw; | ||
3290 | |||
3291 | /* Disable the board */ | ||
3292 | qla_printk(KERN_INFO, ha, "Disabling the board\n"); | ||
3293 | |||
3294 | /* Set DEV_FAILED flag to disable timer */ | ||
3295 | vha->device_flags |= DFLG_DEV_FAILED; | ||
3296 | qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); | ||
3297 | qla2x00_mark_all_devices_lost(vha, 0); | ||
3298 | vha->flags.online = 0; | ||
3299 | vha->flags.init_done = 0; | ||
3300 | } | ||
3301 | |||
3302 | /* | ||
3303 | * qla82xx_need_reset_handler | ||
3304 | * Code to start reset sequence | ||
3305 | * | ||
3306 | * Note: | ||
3307 | * IDC lock must be held upon entry | ||
3308 | * | ||
3309 | * Return: | ||
3310 | * Success : 0 | ||
3311 | * Failed : 1 | ||
3312 | */ | ||
3313 | static void | ||
3314 | qla82xx_need_reset_handler(scsi_qla_host_t *vha) | ||
3315 | { | ||
3316 | uint32_t dev_state, drv_state, drv_active; | ||
3317 | unsigned long reset_timeout; | ||
3318 | struct qla_hw_data *ha = vha->hw; | ||
3319 | struct req_que *req = ha->req_q_map[0]; | ||
3320 | |||
3321 | if (vha->flags.online) { | ||
3322 | qla82xx_idc_unlock(ha); | ||
3323 | qla2x00_abort_isp_cleanup(vha); | ||
3324 | ha->isp_ops->get_flash_version(vha, req->ring); | ||
3325 | ha->isp_ops->nvram_config(vha); | ||
3326 | qla82xx_idc_lock(ha); | ||
3327 | } | ||
3328 | |||
3329 | qla82xx_set_rst_ready(ha); | ||
3330 | |||
3331 | /* wait for 10 seconds for reset ack from all functions */ | ||
3332 | reset_timeout = jiffies + (ha->nx_reset_timeout * HZ); | ||
3333 | |||
3334 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | ||
3335 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | ||
3336 | |||
3337 | while (drv_state != drv_active) { | ||
3338 | if (time_after_eq(jiffies, reset_timeout)) { | ||
3339 | qla_printk(KERN_INFO, ha, | ||
3340 | "%s: RESET TIMEOUT!\n", QLA2XXX_DRIVER_NAME); | ||
3341 | break; | ||
3342 | } | ||
3343 | qla82xx_idc_unlock(ha); | ||
3344 | msleep(1000); | ||
3345 | qla82xx_idc_lock(ha); | ||
3346 | drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE); | ||
3347 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | ||
3348 | } | ||
3349 | |||
3350 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | ||
3351 | /* Force to DEV_COLD unless someone else is starting a reset */ | ||
3352 | if (dev_state != QLA82XX_DEV_INITIALIZING) { | ||
3353 | qla_printk(KERN_INFO, ha, "HW State: COLD/RE-INIT\n"); | ||
3354 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA82XX_DEV_COLD); | ||
3355 | } | ||
3356 | } | ||
3357 | |||
3358 | static void | ||
3359 | qla82xx_check_fw_alive(scsi_qla_host_t *vha) | ||
3360 | { | ||
3361 | uint32_t fw_heartbeat_counter, halt_status; | ||
3362 | struct qla_hw_data *ha = vha->hw; | ||
3363 | |||
3364 | fw_heartbeat_counter = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER); | ||
3365 | if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { | ||
3366 | vha->seconds_since_last_heartbeat++; | ||
3367 | /* FW not alive after 2 seconds */ | ||
3368 | if (vha->seconds_since_last_heartbeat == 2) { | ||
3369 | vha->seconds_since_last_heartbeat = 0; | ||
3370 | halt_status = qla82xx_rd_32(ha, | ||
3371 | QLA82XX_PEG_HALT_STATUS1); | ||
3372 | if (halt_status & HALT_STATUS_UNRECOVERABLE) { | ||
3373 | set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); | ||
3374 | } else { | ||
3375 | qla_printk(KERN_INFO, ha, | ||
3376 | "scsi(%ld): %s - detect abort needed\n", | ||
3377 | vha->host_no, __func__); | ||
3378 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | ||
3379 | } | ||
3380 | qla2xxx_wake_dpc(vha); | ||
3381 | } | ||
3382 | } | ||
3383 | vha->fw_heartbeat_counter = fw_heartbeat_counter; | ||
3384 | } | ||
3385 | |||
3386 | /* | ||
3387 | * qla82xx_device_state_handler | ||
3388 | * Main state handler | ||
3389 | * | ||
3390 | * Note: | ||
3391 | * IDC lock must be held upon entry | ||
3392 | * | ||
3393 | * Return: | ||
3394 | * Success : 0 | ||
3395 | * Failed : 1 | ||
3396 | */ | ||
3397 | int | ||
3398 | qla82xx_device_state_handler(scsi_qla_host_t *vha) | ||
3399 | { | ||
3400 | uint32_t dev_state; | ||
3401 | uint32_t drv_active; | ||
3402 | int rval = QLA_SUCCESS; | ||
3403 | unsigned long dev_init_timeout; | ||
3404 | struct qla_hw_data *ha = vha->hw; | ||
3405 | |||
3406 | qla82xx_idc_lock(ha); | ||
3407 | if (!vha->flags.init_done) | ||
3408 | qla82xx_set_drv_active(vha); | ||
3409 | |||
3410 | /* Set cold state*/ | ||
3411 | if (!PCI_FUNC(ha->pdev->devfn & 1)) { | ||
3412 | |||
3413 | /* Check if other functions alive, else set dev state | ||
3414 | * to cold | ||
3415 | */ | ||
3416 | drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE); | ||
3417 | drv_active &= ~(1 << (ha->portnum * 4)); | ||
3418 | drv_active &= ~(1 << ((ha->portnum + 1) * 4)); | ||
3419 | |||
3420 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | ||
3421 | if (!drv_active) { | ||
3422 | |||
3423 | switch (dev_state) { | ||
3424 | case QLA82XX_DEV_COLD: | ||
3425 | case QLA82XX_DEV_READY: | ||
3426 | case QLA82XX_DEV_INITIALIZING: | ||
3427 | case QLA82XX_DEV_NEED_RESET: | ||
3428 | case QLA82XX_DEV_NEED_QUIESCENT: | ||
3429 | case QLA82XX_DEV_QUIESCENT: | ||
3430 | case QLA82XX_DEV_FAILED: | ||
3431 | break; | ||
3432 | default: | ||
3433 | qla_printk(KERN_INFO, ha, | ||
3434 | "No other function exist," | ||
3435 | " resetting dev state to COLD\n"); | ||
3436 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | ||
3437 | QLA82XX_DEV_COLD); | ||
3438 | break; | ||
3439 | } | ||
3440 | } | ||
3441 | } | ||
3442 | |||
3443 | /* wait for 30 seconds for device to go ready */ | ||
3444 | dev_init_timeout = jiffies + (ha->nx_dev_init_timeout * HZ); | ||
3445 | |||
3446 | while (1) { | ||
3447 | |||
3448 | if (time_after_eq(jiffies, dev_init_timeout)) { | ||
3449 | DEBUG(qla_printk(KERN_INFO, ha, | ||
3450 | "%s: device init failed!\n", | ||
3451 | QLA2XXX_DRIVER_NAME)); | ||
3452 | rval = QLA_FUNCTION_FAILED; | ||
3453 | break; | ||
3454 | } | ||
3455 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | ||
3456 | switch (dev_state) { | ||
3457 | case QLA82XX_DEV_READY: | ||
3458 | goto exit; | ||
3459 | case QLA82XX_DEV_COLD: | ||
3460 | rval = qla82xx_device_bootstrap(vha); | ||
3461 | goto exit; | ||
3462 | case QLA82XX_DEV_INITIALIZING: | ||
3463 | qla82xx_idc_unlock(ha); | ||
3464 | msleep(1000); | ||
3465 | qla82xx_idc_lock(ha); | ||
3466 | break; | ||
3467 | case QLA82XX_DEV_NEED_RESET: | ||
3468 | if (!ql2xdontresethba) | ||
3469 | qla82xx_need_reset_handler(vha); | ||
3470 | break; | ||
3471 | case QLA82XX_DEV_NEED_QUIESCENT: | ||
3472 | qla82xx_set_qsnt_ready(ha); | ||
3473 | case QLA82XX_DEV_QUIESCENT: | ||
3474 | qla82xx_idc_unlock(ha); | ||
3475 | msleep(1000); | ||
3476 | qla82xx_idc_lock(ha); | ||
3477 | break; | ||
3478 | case QLA82XX_DEV_FAILED: | ||
3479 | qla82xx_dev_failed_handler(vha); | ||
3480 | rval = QLA_FUNCTION_FAILED; | ||
3481 | goto exit; | ||
3482 | default: | ||
3483 | qla82xx_idc_unlock(ha); | ||
3484 | msleep(1000); | ||
3485 | qla82xx_idc_lock(ha); | ||
3486 | } | ||
3487 | } | ||
3488 | exit: | ||
3489 | qla82xx_idc_unlock(ha); | ||
3490 | return rval; | ||
3491 | } | ||
3492 | |||
3493 | void qla82xx_watchdog(scsi_qla_host_t *vha) | ||
3494 | { | ||
3495 | uint32_t dev_state; | ||
3496 | struct qla_hw_data *ha = vha->hw; | ||
3497 | |||
3498 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | ||
3499 | |||
3500 | /* don't poll if reset is going on */ | ||
3501 | if (!(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || | ||
3502 | test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) || | ||
3503 | test_bit(ISP_ABORT_RETRY, &vha->dpc_flags))) { | ||
3504 | if (dev_state == QLA82XX_DEV_NEED_RESET) { | ||
3505 | qla_printk(KERN_WARNING, ha, | ||
3506 | "%s(): Adapter reset needed!\n", __func__); | ||
3507 | set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); | ||
3508 | qla2xxx_wake_dpc(vha); | ||
3509 | } else { | ||
3510 | qla82xx_check_fw_alive(vha); | ||
3511 | } | ||
3512 | } | ||
3513 | } | ||
3514 | |||
3515 | int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) | ||
3516 | { | ||
3517 | int rval; | ||
3518 | rval = qla82xx_device_state_handler(vha); | ||
3519 | return rval; | ||
3520 | } | ||
3521 | |||
3522 | /* | ||
3523 | * qla82xx_abort_isp | ||
3524 | * Resets ISP and aborts all outstanding commands. | ||
3525 | * | ||
3526 | * Input: | ||
3527 | * ha = adapter block pointer. | ||
3528 | * | ||
3529 | * Returns: | ||
3530 | * 0 = success | ||
3531 | */ | ||
3532 | int | ||
3533 | qla82xx_abort_isp(scsi_qla_host_t *vha) | ||
3534 | { | ||
3535 | int rval; | ||
3536 | struct qla_hw_data *ha = vha->hw; | ||
3537 | uint32_t dev_state; | ||
3538 | |||
3539 | if (vha->device_flags & DFLG_DEV_FAILED) { | ||
3540 | qla_printk(KERN_WARNING, ha, | ||
3541 | "%s(%ld): Device in failed state, " | ||
3542 | "Exiting.\n", __func__, vha->host_no); | ||
3543 | return QLA_SUCCESS; | ||
3544 | } | ||
3545 | |||
3546 | qla82xx_idc_lock(ha); | ||
3547 | dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE); | ||
3548 | if (dev_state != QLA82XX_DEV_INITIALIZING) { | ||
3549 | qla_printk(KERN_INFO, ha, "HW State: NEED RESET\n"); | ||
3550 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | ||
3551 | QLA82XX_DEV_NEED_RESET); | ||
3552 | } else | ||
3553 | qla_printk(KERN_INFO, ha, "HW State: DEVICE INITIALIZING\n"); | ||
3554 | qla82xx_idc_unlock(ha); | ||
3555 | |||
3556 | rval = qla82xx_device_state_handler(vha); | ||
3557 | |||
3558 | qla82xx_idc_lock(ha); | ||
3559 | qla82xx_clear_rst_ready(ha); | ||
3560 | qla82xx_idc_unlock(ha); | ||
3561 | |||
3562 | if (rval == QLA_SUCCESS) | ||
3563 | qla82xx_restart_isp(vha); | ||
3564 | return rval; | ||
3565 | } | ||
3566 | |||
3567 | /* | ||
3568 | * qla82xx_fcoe_ctx_reset | ||
3569 | * Perform a quick reset and aborts all outstanding commands. | ||
3570 | * This will only perform an FCoE context reset and avoids a full blown | ||
3571 | * chip reset. | ||
3572 | * | ||
3573 | * Input: | ||
3574 | * ha = adapter block pointer. | ||
3575 | * is_reset_path = flag for identifying the reset path. | ||
3576 | * | ||
3577 | * Returns: | ||
3578 | * 0 = success | ||
3579 | */ | ||
3580 | int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha) | ||
3581 | { | ||
3582 | int rval = QLA_FUNCTION_FAILED; | ||
3583 | |||
3584 | if (vha->flags.online) { | ||
3585 | /* Abort all outstanding commands, so as to be requeued later */ | ||
3586 | qla2x00_abort_isp_cleanup(vha); | ||
3587 | } | ||
3588 | |||
3589 | /* Stop currently executing firmware. | ||
3590 | * This will destroy existing FCoE context at the F/W end. | ||
3591 | */ | ||
3592 | qla2x00_try_to_stop_firmware(vha); | ||
3593 | |||
3594 | /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */ | ||
3595 | rval = qla82xx_restart_isp(vha); | ||
3596 | |||
3597 | return rval; | ||
3598 | } | ||
3599 | |||
3600 | /* | ||
3601 | * qla2x00_wait_for_fcoe_ctx_reset | ||
3602 | * Wait till the FCoE context is reset. | ||
3603 | * | ||
3604 | * Note: | ||
3605 | * Does context switching here. | ||
3606 | * Release SPIN_LOCK (if any) before calling this routine. | ||
3607 | * | ||
3608 | * Return: | ||
3609 | * Success (fcoe_ctx reset is done) : 0 | ||
3610 | * Failed (fcoe_ctx reset not completed within max loop timout ) : 1 | ||
3611 | */ | ||
3612 | int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha) | ||
3613 | { | ||
3614 | int status = QLA_FUNCTION_FAILED; | ||
3615 | unsigned long wait_reset; | ||
3616 | |||
3617 | wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); | ||
3618 | while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || | ||
3619 | test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) | ||
3620 | && time_before(jiffies, wait_reset)) { | ||
3621 | |||
3622 | set_current_state(TASK_UNINTERRUPTIBLE); | ||
3623 | schedule_timeout(HZ); | ||
3624 | |||
3625 | if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) && | ||
3626 | !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) { | ||
3627 | status = QLA_SUCCESS; | ||
3628 | break; | ||
3629 | } | ||
3630 | } | ||
3631 | DEBUG2(printk(KERN_INFO | ||
3632 | "%s status=%d\n", __func__, status)); | ||
3633 | |||
3634 | return status; | ||
3635 | } | ||
diff --git a/drivers/scsi/qla2xxx/qla_nx.h b/drivers/scsi/qla2xxx/qla_nx.h new file mode 100644 index 000000000000..7804bbbb3db3 --- /dev/null +++ b/drivers/scsi/qla2xxx/qla_nx.h | |||
@@ -0,0 +1,888 @@ | |||
1 | /* | ||
2 | * QLogic Fibre Channel HBA Driver | ||
3 | * Copyright (c) 2003-2008 QLogic Corporation | ||
4 | * | ||
5 | * See LICENSE.qla2xxx for copyright and licensing details. | ||
6 | */ | ||
7 | #ifndef __QLA_NX_H | ||
8 | #define __QLA_NX_H | ||
9 | |||
10 | /* | ||
11 | * Following are the states of the Phantom. Phantom will set them and | ||
12 | * Host will read to check if the fields are correct. | ||
13 | */ | ||
14 | #define PHAN_INITIALIZE_FAILED 0xffff | ||
15 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | ||
16 | |||
17 | /* Host writes the following to notify that it has done the init-handshake */ | ||
18 | #define PHAN_INITIALIZE_ACK 0xf00f | ||
19 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | ||
20 | |||
21 | /*CRB_RELATED*/ | ||
22 | #define QLA82XX_CRB_BASE QLA82XX_CAM_RAM(0x200) | ||
23 | #define QLA82XX_REG(X) (QLA82XX_CRB_BASE+(X)) | ||
24 | |||
25 | #define CRB_CMDPEG_STATE QLA82XX_REG(0x50) | ||
26 | #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c) | ||
27 | #define BOOT_LOADER_DIMM_STATUS QLA82XX_REG(0x54) | ||
28 | #define CRB_DMA_SHIFT QLA82XX_REG(0xcc) | ||
29 | |||
30 | #define QLA82XX_HW_H0_CH_HUB_ADR 0x05 | ||
31 | #define QLA82XX_HW_H1_CH_HUB_ADR 0x0E | ||
32 | #define QLA82XX_HW_H2_CH_HUB_ADR 0x03 | ||
33 | #define QLA82XX_HW_H3_CH_HUB_ADR 0x01 | ||
34 | #define QLA82XX_HW_H4_CH_HUB_ADR 0x06 | ||
35 | #define QLA82XX_HW_H5_CH_HUB_ADR 0x07 | ||
36 | #define QLA82XX_HW_H6_CH_HUB_ADR 0x08 | ||
37 | |||
38 | /* Hub 0 */ | ||
39 | #define QLA82XX_HW_MN_CRB_AGT_ADR 0x15 | ||
40 | #define QLA82XX_HW_MS_CRB_AGT_ADR 0x25 | ||
41 | |||
42 | /* Hub 1 */ | ||
43 | #define QLA82XX_HW_PS_CRB_AGT_ADR 0x73 | ||
44 | #define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00 | ||
45 | #define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b | ||
46 | #define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01 | ||
47 | #define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02 | ||
48 | #define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03 | ||
49 | #define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04 | ||
50 | #define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58 | ||
51 | #define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59 | ||
52 | #define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a | ||
53 | #define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a | ||
54 | #define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c | ||
55 | #define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f | ||
56 | #define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12 | ||
57 | #define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18 | ||
58 | |||
59 | /* Hub 2 */ | ||
60 | #define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31 | ||
61 | #define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19 | ||
62 | #define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29 | ||
63 | |||
64 | #define QLA82XX_HW_SN_CRB_AGT_ADR 0x10 | ||
65 | #define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20 | ||
66 | #define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22 | ||
67 | #define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21 | ||
68 | #define QLA82XX_HW_QM_CRB_AGT_ADR 0x66 | ||
69 | #define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60 | ||
70 | #define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61 | ||
71 | #define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62 | ||
72 | #define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63 | ||
73 | #define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09 | ||
74 | #define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d | ||
75 | #define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e | ||
76 | #define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11 | ||
77 | |||
78 | /* Hub 3 */ | ||
79 | #define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A | ||
80 | #define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50 | ||
81 | #define QLA82XX_HW_EG_CRB_AGT_ADR 0x51 | ||
82 | #define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08 | ||
83 | |||
84 | /* Hub 4 */ | ||
85 | #define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40 | ||
86 | #define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41 | ||
87 | #define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42 | ||
88 | #define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43 | ||
89 | #define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44 | ||
90 | #define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45 | ||
91 | #define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46 | ||
92 | #define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47 | ||
93 | #define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48 | ||
94 | #define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49 | ||
95 | #define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a | ||
96 | #define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b | ||
97 | |||
98 | /* Hub 5 */ | ||
99 | #define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40 | ||
100 | #define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41 | ||
101 | #define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42 | ||
102 | #define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43 | ||
103 | #define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44 | ||
104 | #define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45 | ||
105 | #define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46 | ||
106 | |||
107 | /* Hub 6 */ | ||
108 | #define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46 | ||
109 | #define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47 | ||
110 | #define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48 | ||
111 | #define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49 | ||
112 | #define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16 | ||
113 | #define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17 | ||
114 | #define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05 | ||
115 | #define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06 | ||
116 | #define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07 | ||
117 | |||
118 | /* This field defines PCI/X adr [25:20] of agents on the CRB */ | ||
119 | /* */ | ||
120 | #define QLA82XX_HW_PX_MAP_CRB_PH 0 | ||
121 | #define QLA82XX_HW_PX_MAP_CRB_PS 1 | ||
122 | #define QLA82XX_HW_PX_MAP_CRB_MN 2 | ||
123 | #define QLA82XX_HW_PX_MAP_CRB_MS 3 | ||
124 | #define QLA82XX_HW_PX_MAP_CRB_SRE 5 | ||
125 | #define QLA82XX_HW_PX_MAP_CRB_NIU 6 | ||
126 | #define QLA82XX_HW_PX_MAP_CRB_QMN 7 | ||
127 | #define QLA82XX_HW_PX_MAP_CRB_SQN0 8 | ||
128 | #define QLA82XX_HW_PX_MAP_CRB_SQN1 9 | ||
129 | #define QLA82XX_HW_PX_MAP_CRB_SQN2 10 | ||
130 | #define QLA82XX_HW_PX_MAP_CRB_SQN3 11 | ||
131 | #define QLA82XX_HW_PX_MAP_CRB_QMS 12 | ||
132 | #define QLA82XX_HW_PX_MAP_CRB_SQS0 13 | ||
133 | #define QLA82XX_HW_PX_MAP_CRB_SQS1 14 | ||
134 | #define QLA82XX_HW_PX_MAP_CRB_SQS2 15 | ||
135 | #define QLA82XX_HW_PX_MAP_CRB_SQS3 16 | ||
136 | #define QLA82XX_HW_PX_MAP_CRB_PGN0 17 | ||
137 | #define QLA82XX_HW_PX_MAP_CRB_PGN1 18 | ||
138 | #define QLA82XX_HW_PX_MAP_CRB_PGN2 19 | ||
139 | #define QLA82XX_HW_PX_MAP_CRB_PGN3 20 | ||
140 | #define QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2 | ||
141 | #define QLA82XX_HW_PX_MAP_CRB_PGND 21 | ||
142 | #define QLA82XX_HW_PX_MAP_CRB_PGNI 22 | ||
143 | #define QLA82XX_HW_PX_MAP_CRB_PGS0 23 | ||
144 | #define QLA82XX_HW_PX_MAP_CRB_PGS1 24 | ||
145 | #define QLA82XX_HW_PX_MAP_CRB_PGS2 25 | ||
146 | #define QLA82XX_HW_PX_MAP_CRB_PGS3 26 | ||
147 | #define QLA82XX_HW_PX_MAP_CRB_PGSD 27 | ||
148 | #define QLA82XX_HW_PX_MAP_CRB_PGSI 28 | ||
149 | #define QLA82XX_HW_PX_MAP_CRB_SN 29 | ||
150 | #define QLA82XX_HW_PX_MAP_CRB_EG 31 | ||
151 | #define QLA82XX_HW_PX_MAP_CRB_PH2 32 | ||
152 | #define QLA82XX_HW_PX_MAP_CRB_PS2 33 | ||
153 | #define QLA82XX_HW_PX_MAP_CRB_CAM 34 | ||
154 | #define QLA82XX_HW_PX_MAP_CRB_CAS0 35 | ||
155 | #define QLA82XX_HW_PX_MAP_CRB_CAS1 36 | ||
156 | #define QLA82XX_HW_PX_MAP_CRB_CAS2 37 | ||
157 | #define QLA82XX_HW_PX_MAP_CRB_C2C0 38 | ||
158 | #define QLA82XX_HW_PX_MAP_CRB_C2C1 39 | ||
159 | #define QLA82XX_HW_PX_MAP_CRB_TIMR 40 | ||
160 | #define QLA82XX_HW_PX_MAP_CRB_RPMX1 42 | ||
161 | #define QLA82XX_HW_PX_MAP_CRB_RPMX2 43 | ||
162 | #define QLA82XX_HW_PX_MAP_CRB_RPMX3 44 | ||
163 | #define QLA82XX_HW_PX_MAP_CRB_RPMX4 45 | ||
164 | #define QLA82XX_HW_PX_MAP_CRB_RPMX5 46 | ||
165 | #define QLA82XX_HW_PX_MAP_CRB_RPMX6 47 | ||
166 | #define QLA82XX_HW_PX_MAP_CRB_RPMX7 48 | ||
167 | #define QLA82XX_HW_PX_MAP_CRB_XDMA 49 | ||
168 | #define QLA82XX_HW_PX_MAP_CRB_I2Q 50 | ||
169 | #define QLA82XX_HW_PX_MAP_CRB_ROMUSB 51 | ||
170 | #define QLA82XX_HW_PX_MAP_CRB_CAS3 52 | ||
171 | #define QLA82XX_HW_PX_MAP_CRB_RPMX0 53 | ||
172 | #define QLA82XX_HW_PX_MAP_CRB_RPMX8 54 | ||
173 | #define QLA82XX_HW_PX_MAP_CRB_RPMX9 55 | ||
174 | #define QLA82XX_HW_PX_MAP_CRB_OCM0 56 | ||
175 | #define QLA82XX_HW_PX_MAP_CRB_OCM1 57 | ||
176 | #define QLA82XX_HW_PX_MAP_CRB_SMB 58 | ||
177 | #define QLA82XX_HW_PX_MAP_CRB_I2C0 59 | ||
178 | #define QLA82XX_HW_PX_MAP_CRB_I2C1 60 | ||
179 | #define QLA82XX_HW_PX_MAP_CRB_LPC 61 | ||
180 | #define QLA82XX_HW_PX_MAP_CRB_PGNC 62 | ||
181 | #define QLA82XX_HW_PX_MAP_CRB_PGR0 63 | ||
182 | #define QLA82XX_HW_PX_MAP_CRB_PGR1 4 | ||
183 | #define QLA82XX_HW_PX_MAP_CRB_PGR2 30 | ||
184 | #define QLA82XX_HW_PX_MAP_CRB_PGR3 41 | ||
185 | |||
186 | /* This field defines CRB adr [31:20] of the agents */ | ||
187 | /* */ | ||
188 | |||
189 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_MN ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \ | ||
190 | QLA82XX_HW_MN_CRB_AGT_ADR) | ||
191 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PH ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \ | ||
192 | QLA82XX_HW_PH_CRB_AGT_ADR) | ||
193 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_MS ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \ | ||
194 | QLA82XX_HW_MS_CRB_AGT_ADR) | ||
195 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ | ||
196 | QLA82XX_HW_PS_CRB_AGT_ADR) | ||
197 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_SS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ | ||
198 | QLA82XX_HW_SS_CRB_AGT_ADR) | ||
199 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ | ||
200 | QLA82XX_HW_RPMX3_CRB_AGT_ADR) | ||
201 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ | ||
202 | QLA82XX_HW_QMS_CRB_AGT_ADR) | ||
203 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ | ||
204 | QLA82XX_HW_SQGS0_CRB_AGT_ADR) | ||
205 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ | ||
206 | QLA82XX_HW_SQGS1_CRB_AGT_ADR) | ||
207 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ | ||
208 | QLA82XX_HW_SQGS2_CRB_AGT_ADR) | ||
209 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ | ||
210 | QLA82XX_HW_SQGS3_CRB_AGT_ADR) | ||
211 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ | ||
212 | QLA82XX_HW_C2C0_CRB_AGT_ADR) | ||
213 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ | ||
214 | QLA82XX_HW_C2C1_CRB_AGT_ADR) | ||
215 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ | ||
216 | QLA82XX_HW_RPMX2_CRB_AGT_ADR) | ||
217 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ | ||
218 | QLA82XX_HW_RPMX4_CRB_AGT_ADR) | ||
219 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ | ||
220 | QLA82XX_HW_RPMX7_CRB_AGT_ADR) | ||
221 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ | ||
222 | QLA82XX_HW_RPMX9_CRB_AGT_ADR) | ||
223 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_SMB ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \ | ||
224 | QLA82XX_HW_SMB_CRB_AGT_ADR) | ||
225 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_NIU ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \ | ||
226 | QLA82XX_HW_NIU_CRB_AGT_ADR) | ||
227 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \ | ||
228 | QLA82XX_HW_I2C0_CRB_AGT_ADR) | ||
229 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \ | ||
230 | QLA82XX_HW_I2C1_CRB_AGT_ADR) | ||
231 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_SRE ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ | ||
232 | QLA82XX_HW_SRE_CRB_AGT_ADR) | ||
233 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_EG ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ | ||
234 | QLA82XX_HW_EG_CRB_AGT_ADR) | ||
235 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ | ||
236 | QLA82XX_HW_RPMX0_CRB_AGT_ADR) | ||
237 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMN ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ | ||
238 | QLA82XX_HW_QM_CRB_AGT_ADR) | ||
239 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ | ||
240 | QLA82XX_HW_SQG0_CRB_AGT_ADR) | ||
241 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ | ||
242 | QLA82XX_HW_SQG1_CRB_AGT_ADR) | ||
243 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ | ||
244 | QLA82XX_HW_SQG2_CRB_AGT_ADR) | ||
245 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ | ||
246 | QLA82XX_HW_SQG3_CRB_AGT_ADR) | ||
247 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ | ||
248 | QLA82XX_HW_RPMX1_CRB_AGT_ADR) | ||
249 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ | ||
250 | QLA82XX_HW_RPMX5_CRB_AGT_ADR) | ||
251 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ | ||
252 | QLA82XX_HW_RPMX6_CRB_AGT_ADR) | ||
253 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ | ||
254 | QLA82XX_HW_RPMX8_CRB_AGT_ADR) | ||
255 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ | ||
256 | QLA82XX_HW_CAS0_CRB_AGT_ADR) | ||
257 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ | ||
258 | QLA82XX_HW_CAS1_CRB_AGT_ADR) | ||
259 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ | ||
260 | QLA82XX_HW_CAS2_CRB_AGT_ADR) | ||
261 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \ | ||
262 | QLA82XX_HW_CAS3_CRB_AGT_ADR) | ||
263 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ | ||
264 | QLA82XX_HW_PEGNI_CRB_AGT_ADR) | ||
265 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGND ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ | ||
266 | QLA82XX_HW_PEGND_CRB_AGT_ADR) | ||
267 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ | ||
268 | QLA82XX_HW_PEGN0_CRB_AGT_ADR) | ||
269 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ | ||
270 | QLA82XX_HW_PEGN1_CRB_AGT_ADR) | ||
271 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ | ||
272 | QLA82XX_HW_PEGN2_CRB_AGT_ADR) | ||
273 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ | ||
274 | QLA82XX_HW_PEGN3_CRB_AGT_ADR) | ||
275 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ | ||
276 | QLA82XX_HW_PEGN4_CRB_AGT_ADR) | ||
277 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ | ||
278 | QLA82XX_HW_PEGNC_CRB_AGT_ADR) | ||
279 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ | ||
280 | QLA82XX_HW_PEGR0_CRB_AGT_ADR) | ||
281 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ | ||
282 | QLA82XX_HW_PEGR1_CRB_AGT_ADR) | ||
283 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ | ||
284 | QLA82XX_HW_PEGR2_CRB_AGT_ADR) | ||
285 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \ | ||
286 | QLA82XX_HW_PEGR3_CRB_AGT_ADR) | ||
287 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ | ||
288 | QLA82XX_HW_PEGSI_CRB_AGT_ADR) | ||
289 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ | ||
290 | QLA82XX_HW_PEGSD_CRB_AGT_ADR) | ||
291 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ | ||
292 | QLA82XX_HW_PEGS0_CRB_AGT_ADR) | ||
293 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ | ||
294 | QLA82XX_HW_PEGS1_CRB_AGT_ADR) | ||
295 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ | ||
296 | QLA82XX_HW_PEGS2_CRB_AGT_ADR) | ||
297 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ | ||
298 | QLA82XX_HW_PEGS3_CRB_AGT_ADR) | ||
299 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \ | ||
300 | QLA82XX_HW_PEGSC_CRB_AGT_ADR) | ||
301 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAM ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ | ||
302 | QLA82XX_HW_NCM_CRB_AGT_ADR) | ||
303 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ | ||
304 | QLA82XX_HW_TMR_CRB_AGT_ADR) | ||
305 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ | ||
306 | QLA82XX_HW_XDMA_CRB_AGT_ADR) | ||
307 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_SN ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ | ||
308 | QLA82XX_HW_SN_CRB_AGT_ADR) | ||
309 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ | ||
310 | QLA82XX_HW_I2Q_CRB_AGT_ADR) | ||
311 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ | ||
312 | QLA82XX_HW_ROMUSB_CRB_AGT_ADR) | ||
313 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ | ||
314 | QLA82XX_HW_OCM0_CRB_AGT_ADR) | ||
315 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ | ||
316 | QLA82XX_HW_OCM1_CRB_AGT_ADR) | ||
317 | #define QLA82XX_HW_CRB_HUB_AGT_ADR_LPC ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \ | ||
318 | QLA82XX_HW_LPC_CRB_AGT_ADR) | ||
319 | |||
320 | #define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000) | ||
321 | #define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c) | ||
322 | #define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004) | ||
323 | #define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008) | ||
324 | #define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008) | ||
325 | #define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c) | ||
326 | #define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010) | ||
327 | #define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014) | ||
328 | #define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018) | ||
329 | |||
330 | #define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000) | ||
331 | #define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004) | ||
332 | #define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038) | ||
333 | |||
334 | /* Lock IDs for ROM lock */ | ||
335 | #define ROM_LOCK_DRIVER 0x0d417340 | ||
336 | |||
337 | #define QLA82XX_PCI_CRB_WINDOWSIZE 0x00100000 /* all are 1MB windows */ | ||
338 | #define QLA82XX_PCI_CRB_WINDOW(A) \ | ||
339 | (QLA82XX_PCI_CRBSPACE + (A)*QLA82XX_PCI_CRB_WINDOWSIZE) | ||
340 | #define QLA82XX_CRB_C2C_0 \ | ||
341 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0) | ||
342 | #define QLA82XX_CRB_C2C_1 \ | ||
343 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1) | ||
344 | #define QLA82XX_CRB_C2C_2 \ | ||
345 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2) | ||
346 | #define QLA82XX_CRB_CAM \ | ||
347 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM) | ||
348 | #define QLA82XX_CRB_CASPER \ | ||
349 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS) | ||
350 | #define QLA82XX_CRB_CASPER_0 \ | ||
351 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0) | ||
352 | #define QLA82XX_CRB_CASPER_1 \ | ||
353 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1) | ||
354 | #define QLA82XX_CRB_CASPER_2 \ | ||
355 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2) | ||
356 | #define QLA82XX_CRB_DDR_MD \ | ||
357 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS) | ||
358 | #define QLA82XX_CRB_DDR_NET \ | ||
359 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN) | ||
360 | #define QLA82XX_CRB_EPG \ | ||
361 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG) | ||
362 | #define QLA82XX_CRB_I2Q \ | ||
363 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q) | ||
364 | #define QLA82XX_CRB_NIU \ | ||
365 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU) | ||
366 | |||
367 | #define QLA82XX_CRB_PCIX_HOST \ | ||
368 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH) | ||
369 | #define QLA82XX_CRB_PCIX_HOST2 \ | ||
370 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2) | ||
371 | #define QLA82XX_CRB_PCIX_MD \ | ||
372 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS) | ||
373 | #define QLA82XX_CRB_PCIE \ | ||
374 | QLA82XX_CRB_PCIX_MD | ||
375 | |||
376 | /* window 1 pcie slot */ | ||
377 | #define QLA82XX_CRB_PCIE2 \ | ||
378 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2) | ||
379 | #define QLA82XX_CRB_PEG_MD_0 \ | ||
380 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0) | ||
381 | #define QLA82XX_CRB_PEG_MD_1 \ | ||
382 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1) | ||
383 | #define QLA82XX_CRB_PEG_MD_2 \ | ||
384 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2) | ||
385 | #define QLA82XX_CRB_PEG_MD_3 \ | ||
386 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3) | ||
387 | #define QLA82XX_CRB_PEG_MD_3 \ | ||
388 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3) | ||
389 | #define QLA82XX_CRB_PEG_MD_D \ | ||
390 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD) | ||
391 | #define QLA82XX_CRB_PEG_MD_I \ | ||
392 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI) | ||
393 | #define QLA82XX_CRB_PEG_NET_0 \ | ||
394 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0) | ||
395 | #define QLA82XX_CRB_PEG_NET_1 \ | ||
396 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1) | ||
397 | #define QLA82XX_CRB_PEG_NET_2 \ | ||
398 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2) | ||
399 | #define QLA82XX_CRB_PEG_NET_3 \ | ||
400 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3) | ||
401 | #define QLA82XX_CRB_PEG_NET_4 \ | ||
402 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4) | ||
403 | #define QLA82XX_CRB_PEG_NET_D \ | ||
404 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND) | ||
405 | #define QLA82XX_CRB_PEG_NET_I \ | ||
406 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI) | ||
407 | #define QLA82XX_CRB_PQM_MD \ | ||
408 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS) | ||
409 | #define QLA82XX_CRB_PQM_NET \ | ||
410 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN) | ||
411 | #define QLA82XX_CRB_QDR_MD \ | ||
412 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS) | ||
413 | #define QLA82XX_CRB_QDR_NET \ | ||
414 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN) | ||
415 | #define QLA82XX_CRB_ROMUSB \ | ||
416 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB) | ||
417 | #define QLA82XX_CRB_RPMX_0 \ | ||
418 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0) | ||
419 | #define QLA82XX_CRB_RPMX_1 \ | ||
420 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1) | ||
421 | #define QLA82XX_CRB_RPMX_2 \ | ||
422 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2) | ||
423 | #define QLA82XX_CRB_RPMX_3 \ | ||
424 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3) | ||
425 | #define QLA82XX_CRB_RPMX_4 \ | ||
426 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4) | ||
427 | #define QLA82XX_CRB_RPMX_5 \ | ||
428 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5) | ||
429 | #define QLA82XX_CRB_RPMX_6 \ | ||
430 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6) | ||
431 | #define QLA82XX_CRB_RPMX_7 \ | ||
432 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7) | ||
433 | #define QLA82XX_CRB_SQM_MD_0 \ | ||
434 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0) | ||
435 | #define QLA82XX_CRB_SQM_MD_1 \ | ||
436 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1) | ||
437 | #define QLA82XX_CRB_SQM_MD_2 \ | ||
438 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2) | ||
439 | #define QLA82XX_CRB_SQM_MD_3 \ | ||
440 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3) | ||
441 | #define QLA82XX_CRB_SQM_NET_0 \ | ||
442 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0) | ||
443 | #define QLA82XX_CRB_SQM_NET_1 \ | ||
444 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1) | ||
445 | #define QLA82XX_CRB_SQM_NET_2 \ | ||
446 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2) | ||
447 | #define QLA82XX_CRB_SQM_NET_3 \ | ||
448 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3) | ||
449 | #define QLA82XX_CRB_SRE \ | ||
450 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE) | ||
451 | #define QLA82XX_CRB_TIMER \ | ||
452 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR) | ||
453 | #define QLA82XX_CRB_XDMA \ | ||
454 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA) | ||
455 | #define QLA82XX_CRB_I2C0 \ | ||
456 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0) | ||
457 | #define QLA82XX_CRB_I2C1 \ | ||
458 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1) | ||
459 | #define QLA82XX_CRB_OCM0 \ | ||
460 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0) | ||
461 | #define QLA82XX_CRB_SMB \ | ||
462 | QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB) | ||
463 | #define QLA82XX_CRB_MAX \ | ||
464 | QLA82XX_PCI_CRB_WINDOW(64) | ||
465 | |||
466 | /* | ||
467 | * ====================== BASE ADDRESSES ON-CHIP ====================== | ||
468 | * Base addresses of major components on-chip. | ||
469 | * ====================== BASE ADDRESSES ON-CHIP ====================== | ||
470 | */ | ||
471 | #define QLA82XX_ADDR_DDR_NET (0x0000000000000000ULL) | ||
472 | #define QLA82XX_ADDR_DDR_NET_MAX (0x000000000fffffffULL) | ||
473 | |||
474 | /* Imbus address bit used to indicate a host address. This bit is | ||
475 | * eliminated by the pcie bar and bar select before presentation | ||
476 | * over pcie. */ | ||
477 | /* host memory via IMBUS */ | ||
478 | #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL) | ||
479 | #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL) | ||
480 | #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL) | ||
481 | #define QLA82XX_ADDR_OCM0 (0x0000000200000000ULL) | ||
482 | #define QLA82XX_ADDR_OCM0_MAX (0x00000002000fffffULL) | ||
483 | #define QLA82XX_ADDR_OCM1 (0x0000000200400000ULL) | ||
484 | #define QLA82XX_ADDR_OCM1_MAX (0x00000002004fffffULL) | ||
485 | #define QLA82XX_ADDR_QDR_NET (0x0000000300000000ULL) | ||
486 | |||
487 | #define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL) | ||
488 | #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL) | ||
489 | |||
490 | #define QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000 | ||
491 | #define QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000 | ||
492 | #define QLA82XX_PCI_CAMQM (unsigned long)0x04800000 | ||
493 | #define QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff | ||
494 | #define QLA82XX_PCI_DDR_NET (unsigned long)0x00000000 | ||
495 | #define QLA82XX_PCI_QDR_NET (unsigned long)0x04000000 | ||
496 | #define QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff | ||
497 | |||
498 | /* | ||
499 | * Register offsets for MN | ||
500 | */ | ||
501 | #define MIU_CONTROL (0x000) | ||
502 | #define MIU_TAG (0x004) | ||
503 | #define MIU_TEST_AGT_CTRL (0x090) | ||
504 | #define MIU_TEST_AGT_ADDR_LO (0x094) | ||
505 | #define MIU_TEST_AGT_ADDR_HI (0x098) | ||
506 | #define MIU_TEST_AGT_WRDATA_LO (0x0a0) | ||
507 | #define MIU_TEST_AGT_WRDATA_HI (0x0a4) | ||
508 | #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i))) | ||
509 | #define MIU_TEST_AGT_RDDATA_LO (0x0a8) | ||
510 | #define MIU_TEST_AGT_RDDATA_HI (0x0ac) | ||
511 | #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i))) | ||
512 | #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8 | ||
513 | #define MIU_TEST_AGT_UPPER_ADDR(off) (0) | ||
514 | |||
515 | /* MIU_TEST_AGT_CTRL flags. work for SIU as well */ | ||
516 | #define MIU_TA_CTL_START 1 | ||
517 | #define MIU_TA_CTL_ENABLE 2 | ||
518 | #define MIU_TA_CTL_WRITE 4 | ||
519 | #define MIU_TA_CTL_BUSY 8 | ||
520 | |||
521 | /*CAM RAM */ | ||
522 | # define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000) | ||
523 | # define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg)) | ||
524 | |||
525 | #define QLA82XX_PEG_TUNE_MN_SPD_ZEROED 0x80000000 | ||
526 | #define QLA82XX_BOOT_LOADER_MN_ISSUE 0xff00ffff | ||
527 | #define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24)) | ||
528 | #define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8)) | ||
529 | #define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac)) | ||
530 | #define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0)) | ||
531 | |||
532 | #define QLA82XX_CAMRAM_DB1 (QLA82XX_CAM_RAM(0x1b8)) | ||
533 | #define QLA82XX_CAMRAM_DB2 (QLA82XX_CAM_RAM(0x1bc)) | ||
534 | |||
535 | #define HALT_STATUS_UNRECOVERABLE 0x80000000 | ||
536 | #define HALT_STATUS_RECOVERABLE 0x40000000 | ||
537 | |||
538 | /* Driver Coexistence Defines */ | ||
539 | #define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138)) | ||
540 | #define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140)) | ||
541 | #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c)) | ||
542 | #define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174)) | ||
543 | #define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144)) | ||
544 | #define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148)) | ||
545 | #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c)) | ||
546 | |||
547 | /* Every driver should use these Device State */ | ||
548 | #define QLA82XX_DEV_COLD 1 | ||
549 | #define QLA82XX_DEV_INITIALIZING 2 | ||
550 | #define QLA82XX_DEV_READY 3 | ||
551 | #define QLA82XX_DEV_NEED_RESET 4 | ||
552 | #define QLA82XX_DEV_NEED_QUIESCENT 5 | ||
553 | #define QLA82XX_DEV_FAILED 6 | ||
554 | #define QLA82XX_DEV_QUIESCENT 7 | ||
555 | |||
556 | #define QLA82XX_IDC_VERSION 1 | ||
557 | #define QLA82XX_ROM_DEV_INIT_TIMEOUT 30 | ||
558 | #define QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT 10 | ||
559 | |||
560 | #define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100)) | ||
561 | #define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124)) | ||
562 | #define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150)) | ||
563 | #define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154)) | ||
564 | #define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158)) | ||
565 | #define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg)) | ||
566 | |||
567 | #define PCIE_CHICKEN3 (0x120c8) | ||
568 | #define PCIE_SETUP_FUNCTION (0x12040) | ||
569 | #define PCIE_SETUP_FUNCTION2 (0x12048) | ||
570 | |||
571 | #define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg)) | ||
572 | #define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg)) | ||
573 | |||
574 | #define PCIE_SEM2_LOCK (0x1c010) /* Flash lock */ | ||
575 | #define PCIE_SEM2_UNLOCK (0x1c014) /* Flash unlock */ | ||
576 | #define PCIE_SEM5_LOCK (0x1c028) /* Coexistence lock */ | ||
577 | #define PCIE_SEM5_UNLOCK (0x1c02c) /* Coexistence unlock */ | ||
578 | #define PCIE_SEM7_LOCK (0x1c038) /* crb win lock */ | ||
579 | #define PCIE_SEM7_UNLOCK (0x1c03c) /* crbwin unlock*/ | ||
580 | |||
581 | /* Different drive state */ | ||
582 | #define QLA82XX_DRVST_NOT_RDY 0 | ||
583 | #define QLA82XX_DRVST_RST_RDY 1 | ||
584 | #define QLA82XX_DRVST_QSNT_RDY 2 | ||
585 | |||
586 | /* | ||
587 | * The PCI VendorID and DeviceID for our board. | ||
588 | */ | ||
589 | #define PCI_DEVICE_ID_QLOGIC_ISP8021 0x8021 | ||
590 | |||
591 | #define QLA82XX_MSIX_TBL_SPACE 8192 | ||
592 | #define QLA82XX_PCI_REG_MSIX_TBL 0x44 | ||
593 | #define QLA82XX_PCI_MSIX_CONTROL 0x40 | ||
594 | |||
595 | struct crb_128M_2M_sub_block_map { | ||
596 | unsigned valid; | ||
597 | unsigned start_128M; | ||
598 | unsigned end_128M; | ||
599 | unsigned start_2M; | ||
600 | }; | ||
601 | |||
602 | struct crb_128M_2M_block_map { | ||
603 | struct crb_128M_2M_sub_block_map sub_block[16]; | ||
604 | }; | ||
605 | |||
606 | struct crb_addr_pair { | ||
607 | long addr; | ||
608 | long data; | ||
609 | }; | ||
610 | |||
611 | #define ADDR_ERROR ((unsigned long) 0xffffffff) | ||
612 | #define MAX_CTL_CHECK 1000 | ||
613 | |||
614 | /*************************************************************************** | ||
615 | * PCI related defines. | ||
616 | **************************************************************************/ | ||
617 | |||
618 | /* | ||
619 | * Interrupt related defines. | ||
620 | */ | ||
621 | #define PCIX_TARGET_STATUS (0x10118) | ||
622 | #define PCIX_TARGET_STATUS_F1 (0x10160) | ||
623 | #define PCIX_TARGET_STATUS_F2 (0x10164) | ||
624 | #define PCIX_TARGET_STATUS_F3 (0x10168) | ||
625 | #define PCIX_TARGET_STATUS_F4 (0x10360) | ||
626 | #define PCIX_TARGET_STATUS_F5 (0x10364) | ||
627 | #define PCIX_TARGET_STATUS_F6 (0x10368) | ||
628 | #define PCIX_TARGET_STATUS_F7 (0x1036c) | ||
629 | |||
630 | #define PCIX_TARGET_MASK (0x10128) | ||
631 | #define PCIX_TARGET_MASK_F1 (0x10170) | ||
632 | #define PCIX_TARGET_MASK_F2 (0x10174) | ||
633 | #define PCIX_TARGET_MASK_F3 (0x10178) | ||
634 | #define PCIX_TARGET_MASK_F4 (0x10370) | ||
635 | #define PCIX_TARGET_MASK_F5 (0x10374) | ||
636 | #define PCIX_TARGET_MASK_F6 (0x10378) | ||
637 | #define PCIX_TARGET_MASK_F7 (0x1037c) | ||
638 | |||
639 | /* | ||
640 | * Message Signaled Interrupts | ||
641 | */ | ||
642 | #define PCIX_MSI_F0 (0x13000) | ||
643 | #define PCIX_MSI_F1 (0x13004) | ||
644 | #define PCIX_MSI_F2 (0x13008) | ||
645 | #define PCIX_MSI_F3 (0x1300c) | ||
646 | #define PCIX_MSI_F4 (0x13010) | ||
647 | #define PCIX_MSI_F5 (0x13014) | ||
648 | #define PCIX_MSI_F6 (0x13018) | ||
649 | #define PCIX_MSI_F7 (0x1301c) | ||
650 | #define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4)) | ||
651 | #define PCIX_INT_VECTOR (0x10100) | ||
652 | #define PCIX_INT_MASK (0x10104) | ||
653 | |||
654 | /* | ||
655 | * Interrupt state machine and other bits. | ||
656 | */ | ||
657 | #define PCIE_MISCCFG_RC (0x1206c) | ||
658 | |||
659 | #define ISR_INT_TARGET_STATUS \ | ||
660 | (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS)) | ||
661 | #define ISR_INT_TARGET_STATUS_F1 \ | ||
662 | (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1)) | ||
663 | #define ISR_INT_TARGET_STATUS_F2 \ | ||
664 | (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2)) | ||
665 | #define ISR_INT_TARGET_STATUS_F3 \ | ||
666 | (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3)) | ||
667 | #define ISR_INT_TARGET_STATUS_F4 \ | ||
668 | (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4)) | ||
669 | #define ISR_INT_TARGET_STATUS_F5 \ | ||
670 | (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5)) | ||
671 | #define ISR_INT_TARGET_STATUS_F6 \ | ||
672 | (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6)) | ||
673 | #define ISR_INT_TARGET_STATUS_F7 \ | ||
674 | (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7)) | ||
675 | |||
676 | #define ISR_INT_TARGET_MASK \ | ||
677 | (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK)) | ||
678 | #define ISR_INT_TARGET_MASK_F1 \ | ||
679 | (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1)) | ||
680 | #define ISR_INT_TARGET_MASK_F2 \ | ||
681 | (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2)) | ||
682 | #define ISR_INT_TARGET_MASK_F3 \ | ||
683 | (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3)) | ||
684 | #define ISR_INT_TARGET_MASK_F4 \ | ||
685 | (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4)) | ||
686 | #define ISR_INT_TARGET_MASK_F5 \ | ||
687 | (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5)) | ||
688 | #define ISR_INT_TARGET_MASK_F6 \ | ||
689 | (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6)) | ||
690 | #define ISR_INT_TARGET_MASK_F7 \ | ||
691 | (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7)) | ||
692 | |||
693 | #define ISR_INT_VECTOR \ | ||
694 | (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR)) | ||
695 | #define ISR_INT_MASK \ | ||
696 | (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK)) | ||
697 | #define ISR_INT_STATE_REG \ | ||
698 | (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC)) | ||
699 | |||
700 | #define ISR_MSI_INT_TRIGGER(FUNC) \ | ||
701 | (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC))) | ||
702 | |||
703 | #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0) | ||
704 | #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) | ||
705 | |||
706 | /* | ||
707 | * PCI Interrupt Vector Values. | ||
708 | */ | ||
709 | #define PCIX_INT_VECTOR_BIT_F0 0x0080 | ||
710 | #define PCIX_INT_VECTOR_BIT_F1 0x0100 | ||
711 | #define PCIX_INT_VECTOR_BIT_F2 0x0200 | ||
712 | #define PCIX_INT_VECTOR_BIT_F3 0x0400 | ||
713 | #define PCIX_INT_VECTOR_BIT_F4 0x0800 | ||
714 | #define PCIX_INT_VECTOR_BIT_F5 0x1000 | ||
715 | #define PCIX_INT_VECTOR_BIT_F6 0x2000 | ||
716 | #define PCIX_INT_VECTOR_BIT_F7 0x4000 | ||
717 | |||
718 | struct qla82xx_legacy_intr_set { | ||
719 | uint32_t int_vec_bit; | ||
720 | uint32_t tgt_status_reg; | ||
721 | uint32_t tgt_mask_reg; | ||
722 | uint32_t pci_int_reg; | ||
723 | }; | ||
724 | |||
725 | #define QLA82XX_LEGACY_INTR_CONFIG \ | ||
726 | { \ | ||
727 | { \ | ||
728 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \ | ||
729 | .tgt_status_reg = ISR_INT_TARGET_STATUS, \ | ||
730 | .tgt_mask_reg = ISR_INT_TARGET_MASK, \ | ||
731 | .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \ | ||
732 | \ | ||
733 | { \ | ||
734 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \ | ||
735 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \ | ||
736 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \ | ||
737 | .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \ | ||
738 | \ | ||
739 | { \ | ||
740 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \ | ||
741 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \ | ||
742 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \ | ||
743 | .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \ | ||
744 | \ | ||
745 | { \ | ||
746 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \ | ||
747 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \ | ||
748 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \ | ||
749 | .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \ | ||
750 | \ | ||
751 | { \ | ||
752 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \ | ||
753 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \ | ||
754 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \ | ||
755 | .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \ | ||
756 | \ | ||
757 | { \ | ||
758 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \ | ||
759 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \ | ||
760 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \ | ||
761 | .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \ | ||
762 | \ | ||
763 | { \ | ||
764 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \ | ||
765 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \ | ||
766 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \ | ||
767 | .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \ | ||
768 | \ | ||
769 | { \ | ||
770 | .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \ | ||
771 | .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \ | ||
772 | .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \ | ||
773 | .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \ | ||
774 | } | ||
775 | |||
776 | #define BOOTLD_START 0x10000 | ||
777 | #define IMAGE_START 0x100000 | ||
778 | #define FLASH_ADDR_START 0x43000 | ||
779 | |||
780 | /* Magic number to let user know flash is programmed */ | ||
781 | #define QLA82XX_BDINFO_MAGIC 0x12345678 | ||
782 | #define FW_SIZE_OFFSET (0x3e840c) | ||
783 | |||
784 | #define QLA82XX_IS_REVISION_P3PLUS(_rev_) ((_rev_) >= 0x50) | ||
785 | #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0) | ||
786 | #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4) | ||
787 | |||
788 | #ifndef readq | ||
789 | static inline u64 readq(void __iomem *addr) | ||
790 | { | ||
791 | return readl(addr) | (((u64) readl(addr + 4)) << 32LL); | ||
792 | } | ||
793 | #endif | ||
794 | |||
795 | #ifndef writeq | ||
796 | static inline void writeq(u64 val, void __iomem *addr) | ||
797 | { | ||
798 | writel(((u32) (val)), (addr)); | ||
799 | writel(((u32) (val >> 32)), (addr + 4)); | ||
800 | } | ||
801 | #endif | ||
802 | |||
803 | /* Request and response queue size */ | ||
804 | #define REQUEST_ENTRY_CNT_82XX 128 /* Number of request entries. */ | ||
805 | #define RESPONSE_ENTRY_CNT_82XX 128 /* Number of response entries.*/ | ||
806 | |||
807 | /* | ||
808 | * ISP 8021 I/O Register Set structure definitions. | ||
809 | */ | ||
810 | struct device_reg_82xx { | ||
811 | uint32_t req_q_out[64]; /* Request Queue out-Pointer (64 * 4) */ | ||
812 | uint32_t rsp_q_in[64]; /* Response Queue In-Pointer. */ | ||
813 | uint32_t rsp_q_out[64]; /* Response Queue Out-Pointer. */ | ||
814 | |||
815 | uint16_t mailbox_in[32]; /* Mail box In registers */ | ||
816 | uint16_t unused_1[32]; | ||
817 | uint32_t hint; /* Host interrupt register */ | ||
818 | #define HINT_MBX_INT_PENDING BIT_0 | ||
819 | uint16_t unused_2[62]; | ||
820 | uint16_t mailbox_out[32]; /* Mail box Out registers */ | ||
821 | uint32_t unused_3[48]; | ||
822 | |||
823 | uint32_t host_status; /* host status */ | ||
824 | #define HSRX_RISC_INT BIT_15 /* RISC to Host interrupt. */ | ||
825 | #define HSRX_RISC_PAUSED BIT_8 /* RISC Paused. */ | ||
826 | uint32_t host_int; /* Interrupt status. */ | ||
827 | #define ISRX_NX_RISC_INT BIT_0 /* RISC interrupt. */ | ||
828 | }; | ||
829 | |||
830 | struct fcp_cmnd { | ||
831 | struct scsi_lun lun; | ||
832 | uint8_t crn; | ||
833 | uint8_t task_attribute; | ||
834 | uint8_t task_managment; | ||
835 | uint8_t additional_cdb_len; | ||
836 | uint8_t cdb[260]; /* 256 for CDB len and 4 for FCP_DL */ | ||
837 | }; | ||
838 | |||
839 | struct dsd_dma { | ||
840 | struct list_head list; | ||
841 | dma_addr_t dsd_list_dma; | ||
842 | void *dsd_addr; | ||
843 | }; | ||
844 | |||
845 | #define QLA_DSDS_PER_IOCB 37 | ||
846 | #define QLA_DSD_SIZE 12 | ||
847 | struct ct6_dsd { | ||
848 | uint16_t fcp_cmnd_len; | ||
849 | dma_addr_t fcp_cmnd_dma; | ||
850 | struct fcp_cmnd *fcp_cmnd; | ||
851 | int dsd_use_cnt; | ||
852 | struct list_head dsd_list; | ||
853 | }; | ||
854 | |||
855 | #define MBC_TOGGLE_INTR 0x10 | ||
856 | |||
857 | /* Flash offset */ | ||
858 | #define FLT_REG_BOOTLOAD_82XX 0x72 | ||
859 | #define FLT_REG_BOOT_CODE_82XX 0x78 | ||
860 | #define FLT_REG_FW_82XX 0x74 | ||
861 | #define FLT_REG_GOLD_FW_82XX 0x75 | ||
862 | #define FLT_REG_VPD_82XX 0x81 | ||
863 | |||
864 | #define FA_VPD_SIZE_82XX 0x400 | ||
865 | |||
866 | #define FA_FLASH_LAYOUT_ADDR_82 0xFC400 | ||
867 | |||
868 | /****************************************************************************** | ||
869 | * | ||
870 | * Definitions specific to M25P flash | ||
871 | * | ||
872 | ******************************************************************************* | ||
873 | * Instructions | ||
874 | */ | ||
875 | #define M25P_INSTR_WREN 0x06 | ||
876 | #define M25P_INSTR_WRDI 0x04 | ||
877 | #define M25P_INSTR_RDID 0x9f | ||
878 | #define M25P_INSTR_RDSR 0x05 | ||
879 | #define M25P_INSTR_WRSR 0x01 | ||
880 | #define M25P_INSTR_READ 0x03 | ||
881 | #define M25P_INSTR_FAST_READ 0x0b | ||
882 | #define M25P_INSTR_PP 0x02 | ||
883 | #define M25P_INSTR_SE 0xd8 | ||
884 | #define M25P_INSTR_BE 0xc7 | ||
885 | #define M25P_INSTR_DP 0xb9 | ||
886 | #define M25P_INSTR_RES 0xab | ||
887 | |||
888 | #endif | ||
diff --git a/drivers/scsi/qla2xxx/qla_os.c b/drivers/scsi/qla2xxx/qla_os.c index f31820691dc2..b1adeb71a8b0 100644 --- a/drivers/scsi/qla2xxx/qla_os.c +++ b/drivers/scsi/qla2xxx/qla_os.c | |||
@@ -29,6 +29,11 @@ char qla2x00_version_str[40]; | |||
29 | */ | 29 | */ |
30 | static struct kmem_cache *srb_cachep; | 30 | static struct kmem_cache *srb_cachep; |
31 | 31 | ||
32 | /* | ||
33 | * CT6 CTX allocation cache | ||
34 | */ | ||
35 | static struct kmem_cache *ctx_cachep; | ||
36 | |||
32 | int ql2xlogintimeout = 20; | 37 | int ql2xlogintimeout = 20; |
33 | module_param(ql2xlogintimeout, int, S_IRUGO|S_IRUSR); | 38 | module_param(ql2xlogintimeout, int, S_IRUGO|S_IRUSR); |
34 | MODULE_PARM_DESC(ql2xlogintimeout, | 39 | MODULE_PARM_DESC(ql2xlogintimeout, |
@@ -65,6 +70,12 @@ MODULE_PARM_DESC(ql2xextended_error_logging, | |||
65 | "Option to enable extended error logging, " | 70 | "Option to enable extended error logging, " |
66 | "Default is 0 - no logging. 1 - log errors."); | 71 | "Default is 0 - no logging. 1 - log errors."); |
67 | 72 | ||
73 | int ql2xshiftctondsd = 6; | ||
74 | module_param(ql2xshiftctondsd, int, S_IRUGO|S_IRUSR); | ||
75 | MODULE_PARM_DESC(ql2xshiftctondsd, | ||
76 | "Set to control shifting of command type processing " | ||
77 | "based on total number of SG elements."); | ||
78 | |||
68 | static void qla2x00_free_device(scsi_qla_host_t *); | 79 | static void qla2x00_free_device(scsi_qla_host_t *); |
69 | 80 | ||
70 | int ql2xfdmienable=1; | 81 | int ql2xfdmienable=1; |
@@ -114,6 +125,21 @@ MODULE_PARM_DESC(ql2xetsenable, | |||
114 | "Enables firmware ETS burst." | 125 | "Enables firmware ETS burst." |
115 | "Default is 0 - skip ETS enablement."); | 126 | "Default is 0 - skip ETS enablement."); |
116 | 127 | ||
128 | int ql2xdbwr; | ||
129 | module_param(ql2xdbwr, int, S_IRUGO|S_IRUSR); | ||
130 | MODULE_PARM_DESC(ql2xdbwr, | ||
131 | "Option to specify scheme for request queue posting\n" | ||
132 | " 0 -- Regular doorbell.\n" | ||
133 | " 1 -- CAMRAM doorbell (faster).\n"); | ||
134 | |||
135 | int ql2xdontresethba; | ||
136 | module_param(ql2xdontresethba, int, S_IRUGO|S_IRUSR); | ||
137 | MODULE_PARM_DESC(ql2xdontresethba, | ||
138 | "Option to specify reset behaviour\n" | ||
139 | " 0 (Default) -- Reset on failure.\n" | ||
140 | " 1 -- Do not reset on failure.\n"); | ||
141 | |||
142 | |||
117 | /* | 143 | /* |
118 | * SCSI host template entry points | 144 | * SCSI host template entry points |
119 | */ | 145 | */ |
@@ -183,6 +209,10 @@ qla2x00_start_timer(scsi_qla_host_t *vha, void *func, unsigned long interval) | |||
183 | static inline void | 209 | static inline void |
184 | qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) | 210 | qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) |
185 | { | 211 | { |
212 | /* Currently used for 82XX only. */ | ||
213 | if (vha->device_flags & DFLG_DEV_FAILED) | ||
214 | return; | ||
215 | |||
186 | mod_timer(&vha->timer, jiffies + interval * HZ); | 216 | mod_timer(&vha->timer, jiffies + interval * HZ); |
187 | } | 217 | } |
188 | 218 | ||
@@ -739,7 +769,7 @@ qla2xxx_eh_abort(struct scsi_cmnd *cmd) | |||
739 | 769 | ||
740 | if (sp == NULL) | 770 | if (sp == NULL) |
741 | continue; | 771 | continue; |
742 | if (sp->ctx) | 772 | if ((sp->ctx) && !(sp->flags & SRB_FCP_CMND_DMA_VALID)) |
743 | continue; | 773 | continue; |
744 | if (sp->cmd != cmd) | 774 | if (sp->cmd != cmd) |
745 | continue; | 775 | continue; |
@@ -834,6 +864,24 @@ qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, | |||
834 | return status; | 864 | return status; |
835 | } | 865 | } |
836 | 866 | ||
867 | void qla82xx_wait_for_pending_commands(scsi_qla_host_t *vha) | ||
868 | { | ||
869 | int cnt; | ||
870 | srb_t *sp; | ||
871 | struct req_que *req = vha->req; | ||
872 | |||
873 | DEBUG2(qla_printk(KERN_INFO, vha->hw, | ||
874 | "Waiting for pending commands\n")); | ||
875 | for (cnt = 1; cnt < MAX_OUTSTANDING_COMMANDS; cnt++) { | ||
876 | sp = req->outstanding_cmds[cnt]; | ||
877 | if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, | ||
878 | sp, WAIT_HOST) == QLA_SUCCESS) { | ||
879 | DEBUG2(qla_printk(KERN_INFO, vha->hw, | ||
880 | "Done wait for pending commands\n")); | ||
881 | } | ||
882 | } | ||
883 | } | ||
884 | |||
837 | static char *reset_errors[] = { | 885 | static char *reset_errors[] = { |
838 | "HBA not online", | 886 | "HBA not online", |
839 | "HBA not ready", | 887 | "HBA not ready", |
@@ -1020,11 +1068,19 @@ qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) | |||
1020 | if (qla2x00_vp_abort_isp(vha)) | 1068 | if (qla2x00_vp_abort_isp(vha)) |
1021 | goto eh_host_reset_lock; | 1069 | goto eh_host_reset_lock; |
1022 | } else { | 1070 | } else { |
1071 | if (IS_QLA82XX(vha->hw)) { | ||
1072 | if (!qla82xx_fcoe_ctx_reset(vha)) { | ||
1073 | /* Ctx reset success */ | ||
1074 | ret = SUCCESS; | ||
1075 | goto eh_host_reset_lock; | ||
1076 | } | ||
1077 | /* fall thru if ctx reset failed */ | ||
1078 | } | ||
1023 | if (ha->wq) | 1079 | if (ha->wq) |
1024 | flush_workqueue(ha->wq); | 1080 | flush_workqueue(ha->wq); |
1025 | 1081 | ||
1026 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | 1082 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
1027 | if (qla2x00_abort_isp(base_vha)) { | 1083 | if (ha->isp_ops->abort_isp(base_vha)) { |
1028 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | 1084 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
1029 | /* failed. schedule dpc to try */ | 1085 | /* failed. schedule dpc to try */ |
1030 | set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); | 1086 | set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); |
@@ -1078,7 +1134,7 @@ qla2x00_loop_reset(scsi_qla_host_t *vha) | |||
1078 | } | 1134 | } |
1079 | } | 1135 | } |
1080 | 1136 | ||
1081 | if (ha->flags.enable_lip_full_login && !IS_QLA81XX(ha)) { | 1137 | if (ha->flags.enable_lip_full_login && !IS_QLA8XXX_TYPE(ha)) { |
1082 | ret = qla2x00_full_login_lip(vha); | 1138 | ret = qla2x00_full_login_lip(vha); |
1083 | if (ret != QLA_SUCCESS) { | 1139 | if (ret != QLA_SUCCESS) { |
1084 | DEBUG2_3(printk("%s(%ld): failed: " | 1140 | DEBUG2_3(printk("%s(%ld): failed: " |
@@ -1125,7 +1181,8 @@ qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) | |||
1125 | sp = req->outstanding_cmds[cnt]; | 1181 | sp = req->outstanding_cmds[cnt]; |
1126 | if (sp) { | 1182 | if (sp) { |
1127 | req->outstanding_cmds[cnt] = NULL; | 1183 | req->outstanding_cmds[cnt] = NULL; |
1128 | if (!sp->ctx) { | 1184 | if (!sp->ctx || |
1185 | (sp->flags & SRB_FCP_CMND_DMA_VALID)) { | ||
1129 | sp->cmd->result = res; | 1186 | sp->cmd->result = res; |
1130 | qla2x00_sp_compl(ha, sp); | 1187 | qla2x00_sp_compl(ha, sp); |
1131 | } else { | 1188 | } else { |
@@ -1387,6 +1444,7 @@ static struct isp_operations qla2100_isp_ops = { | |||
1387 | .write_optrom = qla2x00_write_optrom_data, | 1444 | .write_optrom = qla2x00_write_optrom_data, |
1388 | .get_flash_version = qla2x00_get_flash_version, | 1445 | .get_flash_version = qla2x00_get_flash_version, |
1389 | .start_scsi = qla2x00_start_scsi, | 1446 | .start_scsi = qla2x00_start_scsi, |
1447 | .abort_isp = qla2x00_abort_isp, | ||
1390 | }; | 1448 | }; |
1391 | 1449 | ||
1392 | static struct isp_operations qla2300_isp_ops = { | 1450 | static struct isp_operations qla2300_isp_ops = { |
@@ -1422,6 +1480,7 @@ static struct isp_operations qla2300_isp_ops = { | |||
1422 | .write_optrom = qla2x00_write_optrom_data, | 1480 | .write_optrom = qla2x00_write_optrom_data, |
1423 | .get_flash_version = qla2x00_get_flash_version, | 1481 | .get_flash_version = qla2x00_get_flash_version, |
1424 | .start_scsi = qla2x00_start_scsi, | 1482 | .start_scsi = qla2x00_start_scsi, |
1483 | .abort_isp = qla2x00_abort_isp, | ||
1425 | }; | 1484 | }; |
1426 | 1485 | ||
1427 | static struct isp_operations qla24xx_isp_ops = { | 1486 | static struct isp_operations qla24xx_isp_ops = { |
@@ -1457,6 +1516,7 @@ static struct isp_operations qla24xx_isp_ops = { | |||
1457 | .write_optrom = qla24xx_write_optrom_data, | 1516 | .write_optrom = qla24xx_write_optrom_data, |
1458 | .get_flash_version = qla24xx_get_flash_version, | 1517 | .get_flash_version = qla24xx_get_flash_version, |
1459 | .start_scsi = qla24xx_start_scsi, | 1518 | .start_scsi = qla24xx_start_scsi, |
1519 | .abort_isp = qla2x00_abort_isp, | ||
1460 | }; | 1520 | }; |
1461 | 1521 | ||
1462 | static struct isp_operations qla25xx_isp_ops = { | 1522 | static struct isp_operations qla25xx_isp_ops = { |
@@ -1492,6 +1552,7 @@ static struct isp_operations qla25xx_isp_ops = { | |||
1492 | .write_optrom = qla24xx_write_optrom_data, | 1552 | .write_optrom = qla24xx_write_optrom_data, |
1493 | .get_flash_version = qla24xx_get_flash_version, | 1553 | .get_flash_version = qla24xx_get_flash_version, |
1494 | .start_scsi = qla24xx_start_scsi, | 1554 | .start_scsi = qla24xx_start_scsi, |
1555 | .abort_isp = qla2x00_abort_isp, | ||
1495 | }; | 1556 | }; |
1496 | 1557 | ||
1497 | static struct isp_operations qla81xx_isp_ops = { | 1558 | static struct isp_operations qla81xx_isp_ops = { |
@@ -1527,6 +1588,43 @@ static struct isp_operations qla81xx_isp_ops = { | |||
1527 | .write_optrom = qla24xx_write_optrom_data, | 1588 | .write_optrom = qla24xx_write_optrom_data, |
1528 | .get_flash_version = qla24xx_get_flash_version, | 1589 | .get_flash_version = qla24xx_get_flash_version, |
1529 | .start_scsi = qla24xx_start_scsi, | 1590 | .start_scsi = qla24xx_start_scsi, |
1591 | .abort_isp = qla2x00_abort_isp, | ||
1592 | }; | ||
1593 | |||
1594 | static struct isp_operations qla82xx_isp_ops = { | ||
1595 | .pci_config = qla82xx_pci_config, | ||
1596 | .reset_chip = qla82xx_reset_chip, | ||
1597 | .chip_diag = qla24xx_chip_diag, | ||
1598 | .config_rings = qla82xx_config_rings, | ||
1599 | .reset_adapter = qla24xx_reset_adapter, | ||
1600 | .nvram_config = qla81xx_nvram_config, | ||
1601 | .update_fw_options = qla24xx_update_fw_options, | ||
1602 | .load_risc = qla82xx_load_risc, | ||
1603 | .pci_info_str = qla82xx_pci_info_str, | ||
1604 | .fw_version_str = qla24xx_fw_version_str, | ||
1605 | .intr_handler = qla82xx_intr_handler, | ||
1606 | .enable_intrs = qla82xx_enable_intrs, | ||
1607 | .disable_intrs = qla82xx_disable_intrs, | ||
1608 | .abort_command = qla24xx_abort_command, | ||
1609 | .target_reset = qla24xx_abort_target, | ||
1610 | .lun_reset = qla24xx_lun_reset, | ||
1611 | .fabric_login = qla24xx_login_fabric, | ||
1612 | .fabric_logout = qla24xx_fabric_logout, | ||
1613 | .calc_req_entries = NULL, | ||
1614 | .build_iocbs = NULL, | ||
1615 | .prep_ms_iocb = qla24xx_prep_ms_iocb, | ||
1616 | .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, | ||
1617 | .read_nvram = qla24xx_read_nvram_data, | ||
1618 | .write_nvram = qla24xx_write_nvram_data, | ||
1619 | .fw_dump = qla24xx_fw_dump, | ||
1620 | .beacon_on = qla24xx_beacon_on, | ||
1621 | .beacon_off = qla24xx_beacon_off, | ||
1622 | .beacon_blink = qla24xx_beacon_blink, | ||
1623 | .read_optrom = qla82xx_read_optrom_data, | ||
1624 | .write_optrom = qla82xx_write_optrom_data, | ||
1625 | .get_flash_version = qla24xx_get_flash_version, | ||
1626 | .start_scsi = qla82xx_start_scsi, | ||
1627 | .abort_isp = qla82xx_abort_isp, | ||
1530 | }; | 1628 | }; |
1531 | 1629 | ||
1532 | static inline void | 1630 | static inline void |
@@ -1615,10 +1713,22 @@ qla2x00_set_isp_flags(struct qla_hw_data *ha) | |||
1615 | ha->device_type |= DT_IIDMA; | 1713 | ha->device_type |= DT_IIDMA; |
1616 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | 1714 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; |
1617 | break; | 1715 | break; |
1716 | case PCI_DEVICE_ID_QLOGIC_ISP8021: | ||
1717 | ha->device_type |= DT_ISP8021; | ||
1718 | ha->device_type |= DT_ZIO_SUPPORTED; | ||
1719 | ha->device_type |= DT_FWI2; | ||
1720 | ha->fw_srisc_address = RISC_START_ADDRESS_2400; | ||
1721 | /* Initialize 82XX ISP flags */ | ||
1722 | qla82xx_init_flags(ha); | ||
1723 | break; | ||
1618 | } | 1724 | } |
1619 | 1725 | ||
1620 | /* Get adapter physical port no from interrupt pin register. */ | 1726 | if (IS_QLA82XX(ha)) |
1621 | pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); | 1727 | ha->port_no = !(ha->portnum & 1); |
1728 | else | ||
1729 | /* Get adapter physical port no from interrupt pin register. */ | ||
1730 | pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); | ||
1731 | |||
1622 | if (ha->port_no & 1) | 1732 | if (ha->port_no & 1) |
1623 | ha->flags.port0 = 1; | 1733 | ha->flags.port0 = 1; |
1624 | else | 1734 | else |
@@ -1632,6 +1742,9 @@ qla2x00_iospace_config(struct qla_hw_data *ha) | |||
1632 | uint16_t msix; | 1742 | uint16_t msix; |
1633 | int cpus; | 1743 | int cpus; |
1634 | 1744 | ||
1745 | if (IS_QLA82XX(ha)) | ||
1746 | return qla82xx_iospace_config(ha); | ||
1747 | |||
1635 | if (pci_request_selected_regions(ha->pdev, ha->bars, | 1748 | if (pci_request_selected_regions(ha->pdev, ha->bars, |
1636 | QLA2XXX_DRIVER_NAME)) { | 1749 | QLA2XXX_DRIVER_NAME)) { |
1637 | qla_printk(KERN_WARNING, ha, | 1750 | qla_printk(KERN_WARNING, ha, |
@@ -1775,7 +1888,8 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) | |||
1775 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || | 1888 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || |
1776 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || | 1889 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || |
1777 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || | 1890 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || |
1778 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001) { | 1891 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || |
1892 | pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021) { | ||
1779 | bars = pci_select_bars(pdev, IORESOURCE_MEM); | 1893 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
1780 | mem_only = 1; | 1894 | mem_only = 1; |
1781 | } | 1895 | } |
@@ -1905,6 +2019,19 @@ qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) | |||
1905 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; | 2019 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; |
1906 | ha->nvram_conf_off = ~0; | 2020 | ha->nvram_conf_off = ~0; |
1907 | ha->nvram_data_off = ~0; | 2021 | ha->nvram_data_off = ~0; |
2022 | } else if (IS_QLA82XX(ha)) { | ||
2023 | ha->mbx_count = MAILBOX_REGISTER_COUNT; | ||
2024 | req_length = REQUEST_ENTRY_CNT_82XX; | ||
2025 | rsp_length = RESPONSE_ENTRY_CNT_82XX; | ||
2026 | ha->max_loop_id = SNS_LAST_LOOP_ID_2300; | ||
2027 | ha->init_cb_size = sizeof(struct mid_init_cb_81xx); | ||
2028 | ha->gid_list_info_size = 8; | ||
2029 | ha->optrom_size = OPTROM_SIZE_82XX; | ||
2030 | ha->isp_ops = &qla82xx_isp_ops; | ||
2031 | ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; | ||
2032 | ha->flash_data_off = FARX_ACCESS_FLASH_DATA; | ||
2033 | ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; | ||
2034 | ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; | ||
1908 | } | 2035 | } |
1909 | 2036 | ||
1910 | mutex_init(&ha->vport_lock); | 2037 | mutex_init(&ha->vport_lock); |
@@ -1977,6 +2104,7 @@ que_init: | |||
1977 | " pointers\n"); | 2104 | " pointers\n"); |
1978 | goto probe_init_failed; | 2105 | goto probe_init_failed; |
1979 | } | 2106 | } |
2107 | |||
1980 | ha->rsp_q_map[0] = rsp; | 2108 | ha->rsp_q_map[0] = rsp; |
1981 | ha->req_q_map[0] = req; | 2109 | ha->req_q_map[0] = req; |
1982 | rsp->req = req; | 2110 | rsp->req = req; |
@@ -1995,6 +2123,12 @@ que_init: | |||
1995 | rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; | 2123 | rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; |
1996 | } | 2124 | } |
1997 | 2125 | ||
2126 | if (IS_QLA82XX(ha)) { | ||
2127 | req->req_q_out = &ha->iobase->isp82.req_q_out[0]; | ||
2128 | rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; | ||
2129 | rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; | ||
2130 | } | ||
2131 | |||
1998 | if (qla2x00_initialize_adapter(base_vha)) { | 2132 | if (qla2x00_initialize_adapter(base_vha)) { |
1999 | qla_printk(KERN_WARNING, ha, | 2133 | qla_printk(KERN_WARNING, ha, |
2000 | "Failed to initialize adapter\n"); | 2134 | "Failed to initialize adapter\n"); |
@@ -2003,6 +2137,14 @@ que_init: | |||
2003 | "Adapter flags %x.\n", | 2137 | "Adapter flags %x.\n", |
2004 | base_vha->host_no, base_vha->device_flags)); | 2138 | base_vha->host_no, base_vha->device_flags)); |
2005 | 2139 | ||
2140 | if (IS_QLA82XX(ha)) { | ||
2141 | qla82xx_idc_lock(ha); | ||
2142 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | ||
2143 | QLA82XX_DEV_FAILED); | ||
2144 | qla82xx_idc_unlock(ha); | ||
2145 | qla_printk(KERN_INFO, ha, "HW State: FAILED\n"); | ||
2146 | } | ||
2147 | |||
2006 | ret = -ENODEV; | 2148 | ret = -ENODEV; |
2007 | goto probe_failed; | 2149 | goto probe_failed; |
2008 | } | 2150 | } |
@@ -2041,6 +2183,8 @@ skip_dpc: | |||
2041 | DEBUG2(printk("DEBUG: detect hba %ld at address = %p\n", | 2183 | DEBUG2(printk("DEBUG: detect hba %ld at address = %p\n", |
2042 | base_vha->host_no, ha)); | 2184 | base_vha->host_no, ha)); |
2043 | 2185 | ||
2186 | ha->isp_ops->enable_intrs(ha); | ||
2187 | |||
2044 | ret = scsi_add_host(host, &pdev->dev); | 2188 | ret = scsi_add_host(host, &pdev->dev); |
2045 | if (ret) | 2189 | if (ret) |
2046 | goto probe_failed; | 2190 | goto probe_failed; |
@@ -2048,8 +2192,6 @@ skip_dpc: | |||
2048 | base_vha->flags.init_done = 1; | 2192 | base_vha->flags.init_done = 1; |
2049 | base_vha->flags.online = 1; | 2193 | base_vha->flags.online = 1; |
2050 | 2194 | ||
2051 | ha->isp_ops->enable_intrs(ha); | ||
2052 | |||
2053 | scsi_scan_host(host); | 2195 | scsi_scan_host(host); |
2054 | 2196 | ||
2055 | qla2x00_alloc_sysfs_attr(base_vha); | 2197 | qla2x00_alloc_sysfs_attr(base_vha); |
@@ -2091,9 +2233,17 @@ probe_failed: | |||
2091 | scsi_host_put(base_vha->host); | 2233 | scsi_host_put(base_vha->host); |
2092 | 2234 | ||
2093 | probe_hw_failed: | 2235 | probe_hw_failed: |
2094 | if (ha->iobase) | 2236 | if (IS_QLA82XX(ha)) { |
2095 | iounmap(ha->iobase); | 2237 | qla82xx_idc_lock(ha); |
2096 | 2238 | qla82xx_clear_drv_active(ha); | |
2239 | qla82xx_idc_unlock(ha); | ||
2240 | iounmap((device_reg_t __iomem *)ha->nx_pcibase); | ||
2241 | if (!ql2xdbwr) | ||
2242 | iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); | ||
2243 | } else { | ||
2244 | if (ha->iobase) | ||
2245 | iounmap(ha->iobase); | ||
2246 | } | ||
2097 | pci_release_selected_regions(ha->pdev, ha->bars); | 2247 | pci_release_selected_regions(ha->pdev, ha->bars); |
2098 | kfree(ha); | 2248 | kfree(ha); |
2099 | ha = NULL; | 2249 | ha = NULL; |
@@ -2160,11 +2310,17 @@ qla2x00_remove_one(struct pci_dev *pdev) | |||
2160 | 2310 | ||
2161 | scsi_host_put(base_vha->host); | 2311 | scsi_host_put(base_vha->host); |
2162 | 2312 | ||
2163 | if (ha->iobase) | 2313 | if (IS_QLA82XX(ha)) { |
2164 | iounmap(ha->iobase); | 2314 | iounmap((device_reg_t __iomem *)ha->nx_pcibase); |
2315 | if (!ql2xdbwr) | ||
2316 | iounmap((device_reg_t __iomem *)ha->nxdb_wr_ptr); | ||
2317 | } else { | ||
2318 | if (ha->iobase) | ||
2319 | iounmap(ha->iobase); | ||
2165 | 2320 | ||
2166 | if (ha->mqiobase) | 2321 | if (ha->mqiobase) |
2167 | iounmap(ha->mqiobase); | 2322 | iounmap(ha->mqiobase); |
2323 | } | ||
2168 | 2324 | ||
2169 | pci_release_selected_regions(ha->pdev, ha->bars); | 2325 | pci_release_selected_regions(ha->pdev, ha->bars); |
2170 | kfree(ha); | 2326 | kfree(ha); |
@@ -2213,8 +2369,10 @@ qla2x00_free_device(scsi_qla_host_t *vha) | |||
2213 | vha->flags.online = 0; | 2369 | vha->flags.online = 0; |
2214 | 2370 | ||
2215 | /* turn-off interrupts on the card */ | 2371 | /* turn-off interrupts on the card */ |
2216 | if (ha->interrupts_on) | 2372 | if (ha->interrupts_on) { |
2373 | vha->flags.init_done = 0; | ||
2217 | ha->isp_ops->disable_intrs(ha); | 2374 | ha->isp_ops->disable_intrs(ha); |
2375 | } | ||
2218 | 2376 | ||
2219 | qla2x00_free_irqs(vha); | 2377 | qla2x00_free_irqs(vha); |
2220 | 2378 | ||
@@ -2359,10 +2517,25 @@ qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, | |||
2359 | if (!ha->srb_mempool) | 2517 | if (!ha->srb_mempool) |
2360 | goto fail_free_gid_list; | 2518 | goto fail_free_gid_list; |
2361 | 2519 | ||
2520 | if (IS_QLA82XX(ha)) { | ||
2521 | /* Allocate cache for CT6 Ctx. */ | ||
2522 | if (!ctx_cachep) { | ||
2523 | ctx_cachep = kmem_cache_create("qla2xxx_ctx", | ||
2524 | sizeof(struct ct6_dsd), 0, | ||
2525 | SLAB_HWCACHE_ALIGN, NULL); | ||
2526 | if (!ctx_cachep) | ||
2527 | goto fail_free_gid_list; | ||
2528 | } | ||
2529 | ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, | ||
2530 | ctx_cachep); | ||
2531 | if (!ha->ctx_mempool) | ||
2532 | goto fail_free_srb_mempool; | ||
2533 | } | ||
2534 | |||
2362 | /* Get memory for cached NVRAM */ | 2535 | /* Get memory for cached NVRAM */ |
2363 | ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); | 2536 | ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); |
2364 | if (!ha->nvram) | 2537 | if (!ha->nvram) |
2365 | goto fail_free_srb_mempool; | 2538 | goto fail_free_ctx_mempool; |
2366 | 2539 | ||
2367 | snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, | 2540 | snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, |
2368 | ha->pdev->device); | 2541 | ha->pdev->device); |
@@ -2371,6 +2544,24 @@ qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, | |||
2371 | if (!ha->s_dma_pool) | 2544 | if (!ha->s_dma_pool) |
2372 | goto fail_free_nvram; | 2545 | goto fail_free_nvram; |
2373 | 2546 | ||
2547 | if (IS_QLA82XX(ha)) { | ||
2548 | ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, | ||
2549 | DSD_LIST_DMA_POOL_SIZE, 8, 0); | ||
2550 | if (!ha->dl_dma_pool) { | ||
2551 | qla_printk(KERN_WARNING, ha, | ||
2552 | "Memory Allocation failed - dl_dma_pool\n"); | ||
2553 | goto fail_s_dma_pool; | ||
2554 | } | ||
2555 | |||
2556 | ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, | ||
2557 | FCP_CMND_DMA_POOL_SIZE, 8, 0); | ||
2558 | if (!ha->fcp_cmnd_dma_pool) { | ||
2559 | qla_printk(KERN_WARNING, ha, | ||
2560 | "Memory Allocation failed - fcp_cmnd_dma_pool\n"); | ||
2561 | goto fail_dl_dma_pool; | ||
2562 | } | ||
2563 | } | ||
2564 | |||
2374 | /* Allocate memory for SNS commands */ | 2565 | /* Allocate memory for SNS commands */ |
2375 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) { | 2566 | if (IS_QLA2100(ha) || IS_QLA2200(ha)) { |
2376 | /* Get consistent memory allocated for SNS commands */ | 2567 | /* Get consistent memory allocated for SNS commands */ |
@@ -2437,13 +2628,15 @@ qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, | |||
2437 | ha->npiv_info = NULL; | 2628 | ha->npiv_info = NULL; |
2438 | 2629 | ||
2439 | /* Get consistent memory allocated for EX-INIT-CB. */ | 2630 | /* Get consistent memory allocated for EX-INIT-CB. */ |
2440 | if (IS_QLA81XX(ha)) { | 2631 | if (IS_QLA8XXX_TYPE(ha)) { |
2441 | ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, | 2632 | ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, |
2442 | &ha->ex_init_cb_dma); | 2633 | &ha->ex_init_cb_dma); |
2443 | if (!ha->ex_init_cb) | 2634 | if (!ha->ex_init_cb) |
2444 | goto fail_ex_init_cb; | 2635 | goto fail_ex_init_cb; |
2445 | } | 2636 | } |
2446 | 2637 | ||
2638 | INIT_LIST_HEAD(&ha->gbl_dsd_list); | ||
2639 | |||
2447 | INIT_LIST_HEAD(&ha->vp_list); | 2640 | INIT_LIST_HEAD(&ha->vp_list); |
2448 | return 1; | 2641 | return 1; |
2449 | 2642 | ||
@@ -2473,11 +2666,24 @@ fail_free_ms_iocb: | |||
2473 | ha->ms_iocb = NULL; | 2666 | ha->ms_iocb = NULL; |
2474 | ha->ms_iocb_dma = 0; | 2667 | ha->ms_iocb_dma = 0; |
2475 | fail_dma_pool: | 2668 | fail_dma_pool: |
2669 | if (IS_QLA82XX(ha)) { | ||
2670 | dma_pool_destroy(ha->fcp_cmnd_dma_pool); | ||
2671 | ha->fcp_cmnd_dma_pool = NULL; | ||
2672 | } | ||
2673 | fail_dl_dma_pool: | ||
2674 | if (IS_QLA82XX(ha)) { | ||
2675 | dma_pool_destroy(ha->dl_dma_pool); | ||
2676 | ha->dl_dma_pool = NULL; | ||
2677 | } | ||
2678 | fail_s_dma_pool: | ||
2476 | dma_pool_destroy(ha->s_dma_pool); | 2679 | dma_pool_destroy(ha->s_dma_pool); |
2477 | ha->s_dma_pool = NULL; | 2680 | ha->s_dma_pool = NULL; |
2478 | fail_free_nvram: | 2681 | fail_free_nvram: |
2479 | kfree(ha->nvram); | 2682 | kfree(ha->nvram); |
2480 | ha->nvram = NULL; | 2683 | ha->nvram = NULL; |
2684 | fail_free_ctx_mempool: | ||
2685 | mempool_destroy(ha->ctx_mempool); | ||
2686 | ha->ctx_mempool = NULL; | ||
2481 | fail_free_srb_mempool: | 2687 | fail_free_srb_mempool: |
2482 | mempool_destroy(ha->srb_mempool); | 2688 | mempool_destroy(ha->srb_mempool); |
2483 | ha->srb_mempool = NULL; | 2689 | ha->srb_mempool = NULL; |
@@ -2546,7 +2752,8 @@ qla2x00_mem_free(struct qla_hw_data *ha) | |||
2546 | dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); | 2752 | dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); |
2547 | 2753 | ||
2548 | if (ha->ex_init_cb) | 2754 | if (ha->ex_init_cb) |
2549 | dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); | 2755 | dma_pool_free(ha->s_dma_pool, |
2756 | ha->ex_init_cb, ha->ex_init_cb_dma); | ||
2550 | 2757 | ||
2551 | if (ha->s_dma_pool) | 2758 | if (ha->s_dma_pool) |
2552 | dma_pool_destroy(ha->s_dma_pool); | 2759 | dma_pool_destroy(ha->s_dma_pool); |
@@ -2555,14 +2762,39 @@ qla2x00_mem_free(struct qla_hw_data *ha) | |||
2555 | dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list, | 2762 | dma_free_coherent(&ha->pdev->dev, GID_LIST_SIZE, ha->gid_list, |
2556 | ha->gid_list_dma); | 2763 | ha->gid_list_dma); |
2557 | 2764 | ||
2765 | if (IS_QLA82XX(ha)) { | ||
2766 | if (!list_empty(&ha->gbl_dsd_list)) { | ||
2767 | struct dsd_dma *dsd_ptr, *tdsd_ptr; | ||
2768 | |||
2769 | /* clean up allocated prev pool */ | ||
2770 | list_for_each_entry_safe(dsd_ptr, | ||
2771 | tdsd_ptr, &ha->gbl_dsd_list, list) { | ||
2772 | dma_pool_free(ha->dl_dma_pool, | ||
2773 | dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma); | ||
2774 | list_del(&dsd_ptr->list); | ||
2775 | kfree(dsd_ptr); | ||
2776 | } | ||
2777 | } | ||
2778 | } | ||
2779 | |||
2780 | if (ha->dl_dma_pool) | ||
2781 | dma_pool_destroy(ha->dl_dma_pool); | ||
2782 | |||
2783 | if (ha->fcp_cmnd_dma_pool) | ||
2784 | dma_pool_destroy(ha->fcp_cmnd_dma_pool); | ||
2785 | |||
2786 | if (ha->ctx_mempool) | ||
2787 | mempool_destroy(ha->ctx_mempool); | ||
2788 | |||
2558 | if (ha->init_cb) | 2789 | if (ha->init_cb) |
2559 | dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, | 2790 | dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, |
2560 | ha->init_cb, ha->init_cb_dma); | 2791 | ha->init_cb, ha->init_cb_dma); |
2561 | vfree(ha->optrom_buffer); | 2792 | vfree(ha->optrom_buffer); |
2562 | kfree(ha->nvram); | 2793 | kfree(ha->nvram); |
2563 | kfree(ha->npiv_info); | 2794 | kfree(ha->npiv_info); |
2564 | 2795 | ||
2565 | ha->srb_mempool = NULL; | 2796 | ha->srb_mempool = NULL; |
2797 | ha->ctx_mempool = NULL; | ||
2566 | ha->eft = NULL; | 2798 | ha->eft = NULL; |
2567 | ha->eft_dma = 0; | 2799 | ha->eft_dma = 0; |
2568 | ha->sns_cmd = NULL; | 2800 | ha->sns_cmd = NULL; |
@@ -2577,6 +2809,8 @@ qla2x00_mem_free(struct qla_hw_data *ha) | |||
2577 | ha->ex_init_cb_dma = 0; | 2809 | ha->ex_init_cb_dma = 0; |
2578 | 2810 | ||
2579 | ha->s_dma_pool = NULL; | 2811 | ha->s_dma_pool = NULL; |
2812 | ha->dl_dma_pool = NULL; | ||
2813 | ha->fcp_cmnd_dma_pool = NULL; | ||
2580 | 2814 | ||
2581 | ha->gid_list = NULL; | 2815 | ha->gid_list = NULL; |
2582 | ha->gid_list_dma = 0; | 2816 | ha->gid_list_dma = 0; |
@@ -2904,6 +3138,45 @@ qla2x00_do_dpc(void *data) | |||
2904 | 3138 | ||
2905 | qla2x00_do_work(base_vha); | 3139 | qla2x00_do_work(base_vha); |
2906 | 3140 | ||
3141 | if (IS_QLA82XX(ha)) { | ||
3142 | if (test_and_clear_bit(ISP_UNRECOVERABLE, | ||
3143 | &base_vha->dpc_flags)) { | ||
3144 | qla82xx_idc_lock(ha); | ||
3145 | qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, | ||
3146 | QLA82XX_DEV_FAILED); | ||
3147 | qla82xx_idc_unlock(ha); | ||
3148 | qla_printk(KERN_INFO, ha, | ||
3149 | "HW State: FAILED\n"); | ||
3150 | qla82xx_device_state_handler(base_vha); | ||
3151 | continue; | ||
3152 | } | ||
3153 | |||
3154 | if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, | ||
3155 | &base_vha->dpc_flags)) { | ||
3156 | |||
3157 | DEBUG(printk(KERN_INFO | ||
3158 | "scsi(%ld): dpc: sched " | ||
3159 | "qla82xx_fcoe_ctx_reset ha = %p\n", | ||
3160 | base_vha->host_no, ha)); | ||
3161 | if (!(test_and_set_bit(ABORT_ISP_ACTIVE, | ||
3162 | &base_vha->dpc_flags))) { | ||
3163 | if (qla82xx_fcoe_ctx_reset(base_vha)) { | ||
3164 | /* FCoE-ctx reset failed. | ||
3165 | * Escalate to chip-reset | ||
3166 | */ | ||
3167 | set_bit(ISP_ABORT_NEEDED, | ||
3168 | &base_vha->dpc_flags); | ||
3169 | } | ||
3170 | clear_bit(ABORT_ISP_ACTIVE, | ||
3171 | &base_vha->dpc_flags); | ||
3172 | } | ||
3173 | |||
3174 | DEBUG(printk("scsi(%ld): dpc:" | ||
3175 | " qla82xx_fcoe_ctx_reset end\n", | ||
3176 | base_vha->host_no)); | ||
3177 | } | ||
3178 | } | ||
3179 | |||
2907 | if (test_and_clear_bit(ISP_ABORT_NEEDED, | 3180 | if (test_and_clear_bit(ISP_ABORT_NEEDED, |
2908 | &base_vha->dpc_flags)) { | 3181 | &base_vha->dpc_flags)) { |
2909 | 3182 | ||
@@ -2913,7 +3186,7 @@ qla2x00_do_dpc(void *data) | |||
2913 | if (!(test_and_set_bit(ABORT_ISP_ACTIVE, | 3186 | if (!(test_and_set_bit(ABORT_ISP_ACTIVE, |
2914 | &base_vha->dpc_flags))) { | 3187 | &base_vha->dpc_flags))) { |
2915 | 3188 | ||
2916 | if (qla2x00_abort_isp(base_vha)) { | 3189 | if (ha->isp_ops->abort_isp(base_vha)) { |
2917 | /* failed. retry later */ | 3190 | /* failed. retry later */ |
2918 | set_bit(ISP_ABORT_NEEDED, | 3191 | set_bit(ISP_ABORT_NEEDED, |
2919 | &base_vha->dpc_flags); | 3192 | &base_vha->dpc_flags); |
@@ -3061,8 +3334,18 @@ qla2x00_sp_compl(struct qla_hw_data *ha, srb_t *sp) | |||
3061 | 3334 | ||
3062 | qla2x00_sp_free_dma(sp); | 3335 | qla2x00_sp_free_dma(sp); |
3063 | 3336 | ||
3064 | mempool_free(sp, ha->srb_mempool); | 3337 | if (sp->flags & SRB_FCP_CMND_DMA_VALID) { |
3338 | struct ct6_dsd *ctx = sp->ctx; | ||
3339 | dma_pool_free(ha->fcp_cmnd_dma_pool, ctx->fcp_cmnd, | ||
3340 | ctx->fcp_cmnd_dma); | ||
3341 | list_splice(&ctx->dsd_list, &ha->gbl_dsd_list); | ||
3342 | ha->gbl_dsd_inuse -= ctx->dsd_use_cnt; | ||
3343 | ha->gbl_dsd_avail += ctx->dsd_use_cnt; | ||
3344 | mempool_free(sp->ctx, ha->ctx_mempool); | ||
3345 | sp->ctx = NULL; | ||
3346 | } | ||
3065 | 3347 | ||
3348 | mempool_free(sp, ha->srb_mempool); | ||
3066 | cmd->scsi_done(cmd); | 3349 | cmd->scsi_done(cmd); |
3067 | } | 3350 | } |
3068 | 3351 | ||
@@ -3087,6 +3370,9 @@ qla2x00_timer(scsi_qla_host_t *vha) | |||
3087 | struct qla_hw_data *ha = vha->hw; | 3370 | struct qla_hw_data *ha = vha->hw; |
3088 | struct req_que *req; | 3371 | struct req_que *req; |
3089 | 3372 | ||
3373 | if (IS_QLA82XX(ha)) | ||
3374 | qla82xx_watchdog(vha); | ||
3375 | |||
3090 | /* Hardware read to raise pending EEH errors during mailbox waits. */ | 3376 | /* Hardware read to raise pending EEH errors during mailbox waits. */ |
3091 | if (!pci_channel_offline(ha->pdev)) | 3377 | if (!pci_channel_offline(ha->pdev)) |
3092 | pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); | 3378 | pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); |
@@ -3201,6 +3487,8 @@ qla2x00_timer(scsi_qla_host_t *vha) | |||
3201 | start_dpc || | 3487 | start_dpc || |
3202 | test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || | 3488 | test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || |
3203 | test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || | 3489 | test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || |
3490 | test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || | ||
3491 | test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || | ||
3204 | test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || | 3492 | test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || |
3205 | test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) | 3493 | test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) |
3206 | qla2xxx_wake_dpc(vha); | 3494 | qla2xxx_wake_dpc(vha); |
@@ -3210,7 +3498,7 @@ qla2x00_timer(scsi_qla_host_t *vha) | |||
3210 | 3498 | ||
3211 | /* Firmware interface routines. */ | 3499 | /* Firmware interface routines. */ |
3212 | 3500 | ||
3213 | #define FW_BLOBS 7 | 3501 | #define FW_BLOBS 8 |
3214 | #define FW_ISP21XX 0 | 3502 | #define FW_ISP21XX 0 |
3215 | #define FW_ISP22XX 1 | 3503 | #define FW_ISP22XX 1 |
3216 | #define FW_ISP2300 2 | 3504 | #define FW_ISP2300 2 |
@@ -3218,6 +3506,7 @@ qla2x00_timer(scsi_qla_host_t *vha) | |||
3218 | #define FW_ISP24XX 4 | 3506 | #define FW_ISP24XX 4 |
3219 | #define FW_ISP25XX 5 | 3507 | #define FW_ISP25XX 5 |
3220 | #define FW_ISP81XX 6 | 3508 | #define FW_ISP81XX 6 |
3509 | #define FW_ISP82XX 7 | ||
3221 | 3510 | ||
3222 | #define FW_FILE_ISP21XX "ql2100_fw.bin" | 3511 | #define FW_FILE_ISP21XX "ql2100_fw.bin" |
3223 | #define FW_FILE_ISP22XX "ql2200_fw.bin" | 3512 | #define FW_FILE_ISP22XX "ql2200_fw.bin" |
@@ -3226,6 +3515,7 @@ qla2x00_timer(scsi_qla_host_t *vha) | |||
3226 | #define FW_FILE_ISP24XX "ql2400_fw.bin" | 3515 | #define FW_FILE_ISP24XX "ql2400_fw.bin" |
3227 | #define FW_FILE_ISP25XX "ql2500_fw.bin" | 3516 | #define FW_FILE_ISP25XX "ql2500_fw.bin" |
3228 | #define FW_FILE_ISP81XX "ql8100_fw.bin" | 3517 | #define FW_FILE_ISP81XX "ql8100_fw.bin" |
3518 | #define FW_FILE_ISP82XX "ql8200_fw.bin" | ||
3229 | 3519 | ||
3230 | static DEFINE_MUTEX(qla_fw_lock); | 3520 | static DEFINE_MUTEX(qla_fw_lock); |
3231 | 3521 | ||
@@ -3237,6 +3527,7 @@ static struct fw_blob qla_fw_blobs[FW_BLOBS] = { | |||
3237 | { .name = FW_FILE_ISP24XX, }, | 3527 | { .name = FW_FILE_ISP24XX, }, |
3238 | { .name = FW_FILE_ISP25XX, }, | 3528 | { .name = FW_FILE_ISP25XX, }, |
3239 | { .name = FW_FILE_ISP81XX, }, | 3529 | { .name = FW_FILE_ISP81XX, }, |
3530 | { .name = FW_FILE_ISP82XX, }, | ||
3240 | }; | 3531 | }; |
3241 | 3532 | ||
3242 | struct fw_blob * | 3533 | struct fw_blob * |
@@ -3260,6 +3551,8 @@ qla2x00_request_firmware(scsi_qla_host_t *vha) | |||
3260 | blob = &qla_fw_blobs[FW_ISP25XX]; | 3551 | blob = &qla_fw_blobs[FW_ISP25XX]; |
3261 | } else if (IS_QLA81XX(ha)) { | 3552 | } else if (IS_QLA81XX(ha)) { |
3262 | blob = &qla_fw_blobs[FW_ISP81XX]; | 3553 | blob = &qla_fw_blobs[FW_ISP81XX]; |
3554 | } else if (IS_QLA82XX(ha)) { | ||
3555 | blob = &qla_fw_blobs[FW_ISP82XX]; | ||
3263 | } | 3556 | } |
3264 | 3557 | ||
3265 | mutex_lock(&qla_fw_lock); | 3558 | mutex_lock(&qla_fw_lock); |
@@ -3400,7 +3693,7 @@ qla2xxx_pci_slot_reset(struct pci_dev *pdev) | |||
3400 | msleep(1000); | 3693 | msleep(1000); |
3401 | 3694 | ||
3402 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | 3695 | set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
3403 | if (qla2x00_abort_isp(base_vha) == QLA_SUCCESS) | 3696 | if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS) |
3404 | ret = PCI_ERS_RESULT_RECOVERED; | 3697 | ret = PCI_ERS_RESULT_RECOVERED; |
3405 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); | 3698 | clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); |
3406 | 3699 | ||
@@ -3453,6 +3746,7 @@ static struct pci_device_id qla2xxx_pci_tbl[] = { | |||
3453 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, | 3746 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, |
3454 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, | 3747 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, |
3455 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, | 3748 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, |
3749 | { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, | ||
3456 | { 0 }, | 3750 | { 0 }, |
3457 | }; | 3751 | }; |
3458 | MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); | 3752 | MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); |
@@ -3524,6 +3818,8 @@ qla2x00_module_exit(void) | |||
3524 | pci_unregister_driver(&qla2xxx_pci_driver); | 3818 | pci_unregister_driver(&qla2xxx_pci_driver); |
3525 | qla2x00_release_firmware(); | 3819 | qla2x00_release_firmware(); |
3526 | kmem_cache_destroy(srb_cachep); | 3820 | kmem_cache_destroy(srb_cachep); |
3821 | if (ctx_cachep) | ||
3822 | kmem_cache_destroy(ctx_cachep); | ||
3527 | fc_release_transport(qla2xxx_transport_template); | 3823 | fc_release_transport(qla2xxx_transport_template); |
3528 | fc_release_transport(qla2xxx_transport_vport_template); | 3824 | fc_release_transport(qla2xxx_transport_vport_template); |
3529 | } | 3825 | } |
diff --git a/drivers/scsi/qla2xxx/qla_sup.c b/drivers/scsi/qla2xxx/qla_sup.c index e74552c8c5e1..de92504d7585 100644 --- a/drivers/scsi/qla2xxx/qla_sup.c +++ b/drivers/scsi/qla2xxx/qla_sup.c | |||
@@ -423,9 +423,6 @@ qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat) | |||
423 | /* Flash Manipulation Routines */ | 423 | /* Flash Manipulation Routines */ |
424 | /*****************************************************************************/ | 424 | /*****************************************************************************/ |
425 | 425 | ||
426 | #define OPTROM_BURST_SIZE 0x1000 | ||
427 | #define OPTROM_BURST_DWORDS (OPTROM_BURST_SIZE / 4) | ||
428 | |||
429 | static inline uint32_t | 426 | static inline uint32_t |
430 | flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr) | 427 | flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr) |
431 | { | 428 | { |
@@ -565,6 +562,10 @@ qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start) | |||
565 | *start = FA_FLASH_LAYOUT_ADDR; | 562 | *start = FA_FLASH_LAYOUT_ADDR; |
566 | else if (IS_QLA81XX(ha)) | 563 | else if (IS_QLA81XX(ha)) |
567 | *start = FA_FLASH_LAYOUT_ADDR_81; | 564 | *start = FA_FLASH_LAYOUT_ADDR_81; |
565 | else if (IS_QLA82XX(ha)) { | ||
566 | *start = FA_FLASH_LAYOUT_ADDR_82; | ||
567 | goto end; | ||
568 | } | ||
568 | /* Begin with first PCI expansion ROM header. */ | 569 | /* Begin with first PCI expansion ROM header. */ |
569 | buf = (uint8_t *)req->ring; | 570 | buf = (uint8_t *)req->ring; |
570 | dcode = (uint32_t *)req->ring; | 571 | dcode = (uint32_t *)req->ring; |
@@ -709,10 +710,14 @@ qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr) | |||
709 | break; | 710 | break; |
710 | case FLT_REG_VPD_0: | 711 | case FLT_REG_VPD_0: |
711 | ha->flt_region_vpd_nvram = start; | 712 | ha->flt_region_vpd_nvram = start; |
713 | if (IS_QLA82XX(ha)) | ||
714 | break; | ||
712 | if (ha->flags.port0) | 715 | if (ha->flags.port0) |
713 | ha->flt_region_vpd = start; | 716 | ha->flt_region_vpd = start; |
714 | break; | 717 | break; |
715 | case FLT_REG_VPD_1: | 718 | case FLT_REG_VPD_1: |
719 | if (IS_QLA82XX(ha)) | ||
720 | break; | ||
716 | if (!ha->flags.port0) | 721 | if (!ha->flags.port0) |
717 | ha->flt_region_vpd = start; | 722 | ha->flt_region_vpd = start; |
718 | break; | 723 | break; |
@@ -746,6 +751,21 @@ qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr) | |||
746 | if (!ha->flags.port0) | 751 | if (!ha->flags.port0) |
747 | ha->flt_region_fcp_prio = start; | 752 | ha->flt_region_fcp_prio = start; |
748 | break; | 753 | break; |
754 | case FLT_REG_BOOT_CODE_82XX: | ||
755 | ha->flt_region_boot = start; | ||
756 | break; | ||
757 | case FLT_REG_FW_82XX: | ||
758 | ha->flt_region_fw = start; | ||
759 | break; | ||
760 | case FLT_REG_GOLD_FW_82XX: | ||
761 | ha->flt_region_gold_fw = start; | ||
762 | break; | ||
763 | case FLT_REG_BOOTLOAD_82XX: | ||
764 | ha->flt_region_bootload = start; | ||
765 | break; | ||
766 | case FLT_REG_VPD_82XX: | ||
767 | ha->flt_region_vpd = start; | ||
768 | break; | ||
749 | } | 769 | } |
750 | } | 770 | } |
751 | goto done; | 771 | goto done; |
@@ -791,7 +811,7 @@ qla2xxx_get_fdt_info(scsi_qla_host_t *vha) | |||
791 | uint16_t *wptr; | 811 | uint16_t *wptr; |
792 | struct qla_fdt_layout *fdt; | 812 | struct qla_fdt_layout *fdt; |
793 | uint8_t man_id, flash_id; | 813 | uint8_t man_id, flash_id; |
794 | uint16_t mid, fid; | 814 | uint16_t mid = 0, fid = 0; |
795 | struct qla_hw_data *ha = vha->hw; | 815 | struct qla_hw_data *ha = vha->hw; |
796 | struct req_que *req = ha->req_q_map[0]; | 816 | struct req_que *req = ha->req_q_map[0]; |
797 | 817 | ||
@@ -832,6 +852,10 @@ qla2xxx_get_fdt_info(scsi_qla_host_t *vha) | |||
832 | goto done; | 852 | goto done; |
833 | no_flash_data: | 853 | no_flash_data: |
834 | loc = locations[0]; | 854 | loc = locations[0]; |
855 | if (IS_QLA82XX(ha)) { | ||
856 | ha->fdt_block_size = FLASH_BLK_SIZE_64K; | ||
857 | goto done; | ||
858 | } | ||
835 | qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); | 859 | qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); |
836 | mid = man_id; | 860 | mid = man_id; |
837 | fid = flash_id; | 861 | fid = flash_id; |
@@ -869,6 +893,31 @@ done: | |||
869 | ha->fdt_block_size)); | 893 | ha->fdt_block_size)); |
870 | } | 894 | } |
871 | 895 | ||
896 | static void | ||
897 | qla2xxx_get_idc_param(scsi_qla_host_t *vha) | ||
898 | { | ||
899 | #define QLA82XX_IDC_PARAM_ADDR 0x003e885c | ||
900 | uint32_t *wptr; | ||
901 | struct qla_hw_data *ha = vha->hw; | ||
902 | struct req_que *req = ha->req_q_map[0]; | ||
903 | |||
904 | if (!IS_QLA82XX(ha)) | ||
905 | return; | ||
906 | |||
907 | wptr = (uint32_t *)req->ring; | ||
908 | ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring, | ||
909 | QLA82XX_IDC_PARAM_ADDR , 8); | ||
910 | |||
911 | if (*wptr == __constant_cpu_to_le32(0xffffffff)) { | ||
912 | ha->nx_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT; | ||
913 | ha->nx_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT; | ||
914 | } else { | ||
915 | ha->nx_dev_init_timeout = le32_to_cpu(*wptr++); | ||
916 | ha->nx_reset_timeout = le32_to_cpu(*wptr); | ||
917 | } | ||
918 | return; | ||
919 | } | ||
920 | |||
872 | int | 921 | int |
873 | qla2xxx_get_flash_info(scsi_qla_host_t *vha) | 922 | qla2xxx_get_flash_info(scsi_qla_host_t *vha) |
874 | { | 923 | { |
@@ -876,7 +925,7 @@ qla2xxx_get_flash_info(scsi_qla_host_t *vha) | |||
876 | uint32_t flt_addr; | 925 | uint32_t flt_addr; |
877 | struct qla_hw_data *ha = vha->hw; | 926 | struct qla_hw_data *ha = vha->hw; |
878 | 927 | ||
879 | if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha)) | 928 | if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA8XXX_TYPE(ha)) |
880 | return QLA_SUCCESS; | 929 | return QLA_SUCCESS; |
881 | 930 | ||
882 | ret = qla2xxx_find_flt_start(vha, &flt_addr); | 931 | ret = qla2xxx_find_flt_start(vha, &flt_addr); |
@@ -885,6 +934,7 @@ qla2xxx_get_flash_info(scsi_qla_host_t *vha) | |||
885 | 934 | ||
886 | qla2xxx_get_flt_info(vha, flt_addr); | 935 | qla2xxx_get_flt_info(vha, flt_addr); |
887 | qla2xxx_get_fdt_info(vha); | 936 | qla2xxx_get_fdt_info(vha); |
937 | qla2xxx_get_idc_param(vha); | ||
888 | 938 | ||
889 | return QLA_SUCCESS; | 939 | return QLA_SUCCESS; |
890 | } | 940 | } |
@@ -901,7 +951,7 @@ qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha) | |||
901 | struct qla_npiv_entry *entry; | 951 | struct qla_npiv_entry *entry; |
902 | struct qla_hw_data *ha = vha->hw; | 952 | struct qla_hw_data *ha = vha->hw; |
903 | 953 | ||
904 | if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA81XX(ha)) | 954 | if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && !IS_QLA8XXX_TYPE(ha)) |
905 | return; | 955 | return; |
906 | 956 | ||
907 | ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr, | 957 | ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr, |
@@ -1194,6 +1244,9 @@ qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, | |||
1194 | uint32_t *dwptr; | 1244 | uint32_t *dwptr; |
1195 | struct qla_hw_data *ha = vha->hw; | 1245 | struct qla_hw_data *ha = vha->hw; |
1196 | 1246 | ||
1247 | if (IS_QLA82XX(ha)) | ||
1248 | return buf; | ||
1249 | |||
1197 | /* Dword reads to flash. */ | 1250 | /* Dword reads to flash. */ |
1198 | dwptr = (uint32_t *)buf; | 1251 | dwptr = (uint32_t *)buf; |
1199 | for (i = 0; i < bytes >> 2; i++, naddr++) | 1252 | for (i = 0; i < bytes >> 2; i++, naddr++) |
@@ -1249,6 +1302,9 @@ qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr, | |||
1249 | 1302 | ||
1250 | ret = QLA_SUCCESS; | 1303 | ret = QLA_SUCCESS; |
1251 | 1304 | ||
1305 | if (IS_QLA82XX(ha)) | ||
1306 | return ret; | ||
1307 | |||
1252 | /* Enable flash write. */ | 1308 | /* Enable flash write. */ |
1253 | WRT_REG_DWORD(®->ctrl_status, | 1309 | WRT_REG_DWORD(®->ctrl_status, |
1254 | RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); | 1310 | RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE); |
@@ -1360,6 +1416,9 @@ qla2x00_beacon_blink(struct scsi_qla_host *vha) | |||
1360 | struct qla_hw_data *ha = vha->hw; | 1416 | struct qla_hw_data *ha = vha->hw; |
1361 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; | 1417 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
1362 | 1418 | ||
1419 | if (IS_QLA82XX(ha)) | ||
1420 | return; | ||
1421 | |||
1363 | spin_lock_irqsave(&ha->hardware_lock, flags); | 1422 | spin_lock_irqsave(&ha->hardware_lock, flags); |
1364 | 1423 | ||
1365 | /* Save the Original GPIOE. */ | 1424 | /* Save the Original GPIOE. */ |
@@ -1541,6 +1600,9 @@ qla24xx_beacon_on(struct scsi_qla_host *vha) | |||
1541 | struct qla_hw_data *ha = vha->hw; | 1600 | struct qla_hw_data *ha = vha->hw; |
1542 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | 1601 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
1543 | 1602 | ||
1603 | if (IS_QLA82XX(ha)) | ||
1604 | return QLA_SUCCESS; | ||
1605 | |||
1544 | if (ha->beacon_blink_led == 0) { | 1606 | if (ha->beacon_blink_led == 0) { |
1545 | /* Enable firmware for update */ | 1607 | /* Enable firmware for update */ |
1546 | ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; | 1608 | ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; |
@@ -1583,6 +1645,9 @@ qla24xx_beacon_off(struct scsi_qla_host *vha) | |||
1583 | struct qla_hw_data *ha = vha->hw; | 1645 | struct qla_hw_data *ha = vha->hw; |
1584 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; | 1646 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
1585 | 1647 | ||
1648 | if (IS_QLA82XX(ha)) | ||
1649 | return QLA_SUCCESS; | ||
1650 | |||
1586 | ha->beacon_blink_led = 0; | 1651 | ha->beacon_blink_led = 0; |
1587 | ha->beacon_color_state = QLA_LED_ALL_ON; | 1652 | ha->beacon_color_state = QLA_LED_ALL_ON; |
1588 | 1653 | ||
@@ -2592,6 +2657,9 @@ qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) | |||
2592 | int i; | 2657 | int i; |
2593 | struct qla_hw_data *ha = vha->hw; | 2658 | struct qla_hw_data *ha = vha->hw; |
2594 | 2659 | ||
2660 | if (IS_QLA82XX(ha)) | ||
2661 | return ret; | ||
2662 | |||
2595 | if (!mbuf) | 2663 | if (!mbuf) |
2596 | return QLA_FUNCTION_FAILED; | 2664 | return QLA_FUNCTION_FAILED; |
2597 | 2665 | ||