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-rw-r--r--arch/sh/Kconfig126
-rw-r--r--arch/sh/Kconfig.cpu8
-rw-r--r--arch/sh/Kconfig.debug23
-rw-r--r--arch/sh/Makefile73
-rw-r--r--arch/sh/boards/Kconfig15
-rw-r--r--arch/sh/boards/board-ap325rxa.c12
-rw-r--r--arch/sh/boards/board-sh7785lcr.c44
-rw-r--r--arch/sh/boards/mach-cayman/Makefile2
-rw-r--r--arch/sh/boards/mach-cayman/irq.c17
-rw-r--r--arch/sh/boards/mach-cayman/panic.c49
-rw-r--r--arch/sh/boards/mach-cayman/setup.c2
-rw-r--r--arch/sh/boards/mach-dreamcast/setup.c6
-rw-r--r--arch/sh/boards/mach-migor/setup.c19
-rw-r--r--arch/sh/boards/mach-r2d/setup.c50
-rw-r--r--arch/sh/boards/mach-se/7724/Makefile10
-rw-r--r--arch/sh/boards/mach-se/7724/irq.c139
-rw-r--r--arch/sh/boards/mach-se/7724/setup.c448
-rw-r--r--arch/sh/boards/mach-se/7751/Makefile2
-rw-r--r--arch/sh/boards/mach-se/7751/io.c16
-rw-r--r--arch/sh/boards/mach-se/7751/pci.c147
-rw-r--r--arch/sh/boards/mach-se/7780/irq.c27
-rw-r--r--arch/sh/boards/mach-se/Makefile1
-rw-r--r--arch/sh/boards/mach-sh03/rtc.c10
-rw-r--r--arch/sh/boards/mach-snapgear/io.c16
-rw-r--r--arch/sh/boards/mach-systemh/io.c16
-rw-r--r--arch/sh/boards/mach-titan/io.c20
-rw-r--r--arch/sh/boot/Makefile6
-rw-r--r--arch/sh/boot/compressed/Makefile50
-rw-r--r--arch/sh/boot/compressed/Makefile_3246
-rw-r--r--arch/sh/boot/compressed/Makefile_6443
-rw-r--r--arch/sh/boot/compressed/head_64.S5
-rw-r--r--arch/sh/boot/compressed/vmlinux_64.lds64
-rw-r--r--arch/sh/cchips/Kconfig5
-rw-r--r--arch/sh/cchips/hd6446x/hd64461.c2
-rw-r--r--arch/sh/configs/ap325rxa_defconfig37
-rw-r--r--arch/sh/configs/cayman_defconfig71
-rw-r--r--arch/sh/configs/dreamcast_defconfig39
-rw-r--r--arch/sh/configs/edosk7705_defconfig29
-rw-r--r--arch/sh/configs/edosk7760_defconfig32
-rw-r--r--arch/sh/configs/espt_defconfig39
-rw-r--r--arch/sh/configs/hp6xx_defconfig35
-rw-r--r--arch/sh/configs/landisk_defconfig48
-rw-r--r--arch/sh/configs/lboxre2_defconfig44
-rw-r--r--arch/sh/configs/magicpanelr2_defconfig30
-rw-r--r--arch/sh/configs/microdev_defconfig36
-rw-r--r--arch/sh/configs/migor_defconfig36
-rw-r--r--arch/sh/configs/polaris_defconfig30
-rw-r--r--arch/sh/configs/r7780mp_defconfig38
-rw-r--r--arch/sh/configs/r7785rp_defconfig38
-rw-r--r--arch/sh/configs/rsk7201_defconfig37
-rw-r--r--arch/sh/configs/rsk7203_defconfig40
-rw-r--r--arch/sh/configs/rts7751r2d1_defconfig43
-rw-r--r--arch/sh/configs/rts7751r2dplus_defconfig130
-rw-r--r--arch/sh/configs/sdk7780_defconfig38
-rw-r--r--arch/sh/configs/se7206_defconfig35
-rw-r--r--arch/sh/configs/se7343_defconfig42
-rw-r--r--arch/sh/configs/se7619_defconfig35
-rw-r--r--arch/sh/configs/se7705_defconfig34
-rw-r--r--arch/sh/configs/se7712_defconfig30
-rw-r--r--arch/sh/configs/se7721_defconfig33
-rw-r--r--arch/sh/configs/se7722_defconfig38
-rw-r--r--arch/sh/configs/se7724_defconfig1552
-rw-r--r--arch/sh/configs/se7750_defconfig34
-rw-r--r--arch/sh/configs/se7751_defconfig34
-rw-r--r--arch/sh/configs/se7780_defconfig38
-rw-r--r--arch/sh/configs/sh03_defconfig43
-rw-r--r--arch/sh/configs/sh7710voipgw_defconfig35
-rw-r--r--arch/sh/configs/sh7724_generic_defconfig707
-rw-r--r--arch/sh/configs/sh7763rdp_defconfig35
-rw-r--r--arch/sh/configs/sh7770_generic_defconfig700
-rw-r--r--arch/sh/configs/sh7785lcr_32bit_defconfig37
-rw-r--r--arch/sh/configs/sh7785lcr_defconfig6
-rw-r--r--arch/sh/configs/shmin_defconfig31
-rw-r--r--arch/sh/configs/shx3_defconfig32
-rw-r--r--arch/sh/configs/snapgear_defconfig40
-rw-r--r--arch/sh/configs/systemh_defconfig39
-rw-r--r--arch/sh/configs/titan_defconfig40
-rw-r--r--arch/sh/configs/ul2_defconfig37
-rw-r--r--arch/sh/configs/urquell_defconfig39
-rw-r--r--arch/sh/drivers/dma/Kconfig3
-rw-r--r--arch/sh/drivers/pci/Kconfig18
-rw-r--r--arch/sh/drivers/pci/Makefile28
-rw-r--r--arch/sh/drivers/pci/fixups-cayman.c (renamed from arch/sh/drivers/pci/ops-cayman.c)12
-rw-r--r--arch/sh/drivers/pci/fixups-dreamcast.c9
-rw-r--r--arch/sh/drivers/pci/fixups-landisk.c (renamed from arch/sh/drivers/pci/ops-landisk.c)33
-rw-r--r--arch/sh/drivers/pci/fixups-lboxre2.c41
-rw-r--r--arch/sh/drivers/pci/fixups-r7780rp.c41
-rw-r--r--arch/sh/drivers/pci/fixups-rts7751r2d.c48
-rw-r--r--arch/sh/drivers/pci/fixups-sdk7780.c63
-rw-r--r--arch/sh/drivers/pci/fixups-se7751.c111
-rw-r--r--arch/sh/drivers/pci/fixups-se7780.c60
-rw-r--r--arch/sh/drivers/pci/fixups-sh7785lcr.c46
-rw-r--r--arch/sh/drivers/pci/fixups-snapgear.c38
-rw-r--r--arch/sh/drivers/pci/fixups-titan.c (renamed from arch/sh/drivers/pci/ops-titan.c)39
-rw-r--r--arch/sh/drivers/pci/ops-dreamcast.c107
-rw-r--r--arch/sh/drivers/pci/ops-lboxre2.c63
-rw-r--r--arch/sh/drivers/pci/ops-r7780rp.c68
-rw-r--r--arch/sh/drivers/pci/ops-rts7751r2d.c74
-rw-r--r--arch/sh/drivers/pci/ops-sdk7780.c73
-rw-r--r--arch/sh/drivers/pci/ops-se7780.c96
-rw-r--r--arch/sh/drivers/pci/ops-sh03.c45
-rw-r--r--arch/sh/drivers/pci/ops-sh4.c79
-rw-r--r--arch/sh/drivers/pci/ops-sh5.c25
-rw-r--r--arch/sh/drivers/pci/ops-sh7785lcr.c66
-rw-r--r--arch/sh/drivers/pci/ops-snapgear.c94
-rw-r--r--arch/sh/drivers/pci/pci-auto.c545
-rw-r--r--arch/sh/drivers/pci/pci-dreamcast.c102
-rw-r--r--arch/sh/drivers/pci/pci-sh4.h19
-rw-r--r--arch/sh/drivers/pci/pci-sh5.c55
-rw-r--r--arch/sh/drivers/pci/pci-sh5.h3
-rw-r--r--arch/sh/drivers/pci/pci-sh7751.c215
-rw-r--r--arch/sh/drivers/pci/pci-sh7751.h12
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.c224
-rw-r--r--arch/sh/drivers/pci/pci-sh7780.h16
-rw-r--r--arch/sh/drivers/pci/pci.c279
-rw-r--r--arch/sh/include/asm/atomic-llsc.h27
-rw-r--r--arch/sh/include/asm/atomic.h4
-rw-r--r--arch/sh/include/asm/cacheflush.h2
-rw-r--r--arch/sh/include/asm/clock.h113
-rw-r--r--arch/sh/include/asm/cmpxchg-llsc.h2
-rw-r--r--arch/sh/include/asm/device.h2
-rw-r--r--arch/sh/include/asm/hd64461.h148
-rw-r--r--arch/sh/include/asm/io.h22
-rw-r--r--arch/sh/include/asm/irq.h3
-rw-r--r--arch/sh/include/asm/kprobes.h2
-rw-r--r--arch/sh/include/asm/machvec.h3
-rw-r--r--arch/sh/include/asm/pci.h118
-rw-r--r--arch/sh/include/asm/pgtable.h4
-rw-r--r--arch/sh/include/asm/processor.h23
-rw-r--r--arch/sh/include/asm/ptrace.h5
-rw-r--r--arch/sh/include/asm/rtc.h11
-rw-r--r--arch/sh/include/asm/spinlock.h2
-rw-r--r--arch/sh/include/asm/swab.h12
-rw-r--r--arch/sh/include/asm/system_32.h2
-rw-r--r--arch/sh/include/asm/timer.h44
-rw-r--r--arch/sh/include/asm/types.h4
-rw-r--r--arch/sh/include/asm/ubc.h11
-rw-r--r--arch/sh/include/asm/unaligned-sh4a.h10
-rw-r--r--arch/sh/include/asm/unistd_32.h3
-rw-r--r--arch/sh/include/asm/unistd_64.h3
-rw-r--r--arch/sh/include/cpu-sh2a/cpu/ubc.h29
-rw-r--r--arch/sh/include/cpu-sh3/cpu/timer.h67
-rw-r--r--arch/sh/include/cpu-sh4/cpu/cache.h2
-rw-r--r--arch/sh/include/cpu-sh4/cpu/freq.h18
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7722.h14
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7723.h14
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7724.h269
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7785.h25
-rw-r--r--arch/sh/include/cpu-sh4/cpu/timer.h60
-rw-r--r--arch/sh/include/cpu-sh5/cpu/irq.h1
-rw-r--r--arch/sh/include/mach-common/mach/sh7785lcr.h10
-rw-r--r--arch/sh/include/mach-dreamcast/mach/pci.h2
-rw-r--r--arch/sh/include/mach-se/mach/se7724.h67
-rw-r--r--arch/sh/kernel/Makefile_326
-rw-r--r--arch/sh/kernel/Makefile_649
-rw-r--r--arch/sh/kernel/cpu/Makefile1
-rw-r--r--arch/sh/kernel/cpu/clock-cpg.c256
-rw-r--r--arch/sh/kernel/cpu/clock.c606
-rw-r--r--arch/sh/kernel/cpu/init.c7
-rw-r--r--arch/sh/kernel/cpu/irq/imask.c68
-rw-r--r--arch/sh/kernel/cpu/irq/intc-sh5.c36
-rw-r--r--arch/sh/kernel/cpu/irq/ipr.c9
-rw-r--r--arch/sh/kernel/cpu/sh2/clock-sh7619.c16
-rw-r--r--arch/sh/kernel/cpu/sh2/setup-sh7619.c84
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7201.c14
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7203.c15
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7206.c12
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-mxg.c111
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7201.c115
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7203.c154
-rw-r--r--arch/sh/kernel/cpu/sh2a/setup-sh7206.c187
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh3.c12
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7705.c12
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7706.c12
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7709.c12
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7710.c12
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7712.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c108
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c108
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7710.c108
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c270
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh4-202.c43
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh4.c12
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c130
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh4-202.c164
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c187
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c140
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile9
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7343.c211
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7366.c211
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7722.c923
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7723.c222
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7724.c242
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7763.c46
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7770.c12
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7780.c43
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7785.c208
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7786.c47
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-shx3.c41
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c2230
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7343.c122
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c119
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c123
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c231
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c786
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c204
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c546
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c204
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c210
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c393
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-shx3.c209
-rw-r--r--arch/sh/kernel/cpu/sh5/Makefile3
-rw-r--r--arch/sh/kernel/cpu/sh5/clock-sh5.c14
-rw-r--r--arch/sh/kernel/cpu/sh5/entry.S65
-rw-r--r--arch/sh/kernel/cpu/sh5/setup-sh5.c195
-rw-r--r--arch/sh/kernel/io.c1
-rw-r--r--arch/sh/kernel/io_trapped.c2
-rw-r--r--arch/sh/kernel/irq.c77
-rw-r--r--arch/sh/kernel/kgdb.c4
-rw-r--r--arch/sh/kernel/localtimer.c (renamed from arch/sh/kernel/timers/timer-broadcast.c)0
-rw-r--r--arch/sh/kernel/machvec.c1
-rw-r--r--arch/sh/kernel/module.c2
-rw-r--r--arch/sh/kernel/process_32.c4
-rw-r--r--arch/sh/kernel/ptrace_32.c8
-rw-r--r--arch/sh/kernel/setup.c26
-rw-r--r--arch/sh/kernel/sh_ksyms_32.c9
-rw-r--r--arch/sh/kernel/sh_ksyms_64.c2
-rw-r--r--arch/sh/kernel/syscalls_32.S3
-rw-r--r--arch/sh/kernel/syscalls_64.S1
-rw-r--r--arch/sh/kernel/time.c125
-rw-r--r--arch/sh/kernel/time_32.c240
-rw-r--r--arch/sh/kernel/time_64.c363
-rw-r--r--arch/sh/kernel/timers/Makefile11
-rw-r--r--arch/sh/kernel/timers/timer-cmt.c188
-rw-r--r--arch/sh/kernel/timers/timer-mtu2.c202
-rw-r--r--arch/sh/kernel/timers/timer-tmu.c297
-rw-r--r--arch/sh/kernel/timers/timer.c55
-rw-r--r--arch/sh/kernel/traps.c6
-rw-r--r--arch/sh/kernel/traps_32.c15
-rw-r--r--arch/sh/kernel/traps_64.c35
-rw-r--r--arch/sh/kernel/vmlinux.lds.S179
-rw-r--r--arch/sh/kernel/vmlinux_32.lds.S154
-rw-r--r--arch/sh/kernel/vmlinux_64.lds.S163
-rw-r--r--arch/sh/lib64/.gitignore1
-rw-r--r--arch/sh/lib64/dbg.c182
-rw-r--r--arch/sh/lib64/panic.c43
-rw-r--r--arch/sh/lib64/sdivsi3.S6
-rw-r--r--arch/sh/lib64/udelay.c2
-rw-r--r--arch/sh/mm/Kconfig31
-rw-r--r--arch/sh/mm/cache-sh5.c8
-rw-r--r--arch/sh/mm/init.c3
-rw-r--r--arch/sh/mm/ioremap_32.c14
-rw-r--r--arch/sh/mm/ioremap_64.c266
-rw-r--r--arch/sh/mm/mmap.c136
-rw-r--r--arch/sh/oprofile/common.c1
-rw-r--r--arch/sh/tools/mach-types1
-rw-r--r--drivers/clocksource/Makefile2
-rw-r--r--drivers/clocksource/sh_cmt.c116
-rw-r--r--drivers/clocksource/sh_mtu2.c357
-rw-r--r--drivers/clocksource/sh_tmu.c461
-rw-r--r--drivers/i2c/busses/i2c-sh7760.c2
-rw-r--r--drivers/rtc/Kconfig2
-rw-r--r--drivers/serial/sh-sci.c388
-rw-r--r--drivers/serial/sh-sci.h42
-rw-r--r--drivers/sh/intc.c11
-rw-r--r--drivers/video/hitfb.c4
-rw-r--r--include/linux/clocksource.h10
-rw-r--r--include/linux/serial_sci.h3
-rw-r--r--include/linux/sh_cmt.h13
-rw-r--r--include/linux/sh_timer.h13
-rw-r--r--include/linux/time.h15
-rw-r--r--kernel/time/clocksource.c3
-rw-r--r--kernel/time/timekeeping.c7
-rw-r--r--sound/oss/Kconfig2
-rw-r--r--sound/oss/sh_dac_audio.c85
275 files changed, 18185 insertions, 7254 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index e7390dd0283d..586cd045e2db 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -15,6 +15,7 @@ config SUPERH
15 select HAVE_IOREMAP_PROT if MMU 15 select HAVE_IOREMAP_PROT if MMU
16 select HAVE_ARCH_TRACEHOOK 16 select HAVE_ARCH_TRACEHOOK
17 select HAVE_DMA_API_DEBUG 17 select HAVE_DMA_API_DEBUG
18 select RTC_LIB
18 help 19 help
19 The SuperH is a RISC processor targeted for use in embedded systems 20 The SuperH is a RISC processor targeted for use in embedded systems
20 and consumer electronics; it was also used in the Sega Dreamcast 21 and consumer electronics; it was also used in the Sega Dreamcast
@@ -74,14 +75,18 @@ config GENERIC_IOMAP
74 bool 75 bool
75 76
76config GENERIC_TIME 77config GENERIC_TIME
77 def_bool n 78 def_bool y
78 79
79config GENERIC_CLOCKEVENTS 80config GENERIC_CLOCKEVENTS
80 def_bool n 81 def_bool y
81 82
82config GENERIC_CLOCKEVENTS_BROADCAST 83config GENERIC_CLOCKEVENTS_BROADCAST
83 bool 84 bool
84 85
86config GENERIC_CMOS_UPDATE
87 def_bool y
88 depends on SH_SH03 || SH_DREAMCAST
89
85config GENERIC_LOCKBREAK 90config GENERIC_LOCKBREAK
86 def_bool y 91 def_bool y
87 depends on SMP && PREEMPT 92 depends on SMP && PREEMPT
@@ -112,6 +117,12 @@ config SYS_SUPPORTS_PCI
112config SYS_SUPPORTS_CMT 117config SYS_SUPPORTS_CMT
113 bool 118 bool
114 119
120config SYS_SUPPORTS_MTU2
121 bool
122
123config SYS_SUPPORTS_TMU
124 bool
125
115config STACKTRACE_SUPPORT 126config STACKTRACE_SUPPORT
116 def_bool y 127 def_bool y
117 128
@@ -157,13 +168,14 @@ config CPU_SH3
157 bool 168 bool
158 select CPU_HAS_INTEVT 169 select CPU_HAS_INTEVT
159 select CPU_HAS_SR_RB 170 select CPU_HAS_SR_RB
171 select SYS_SUPPORTS_TMU
160 172
161config CPU_SH4 173config CPU_SH4
162 bool 174 bool
163 select CPU_HAS_INTEVT 175 select CPU_HAS_INTEVT
164 select CPU_HAS_SR_RB 176 select CPU_HAS_SR_RB
165 select CPU_HAS_PTEA if !CPU_SH4A || CPU_SHX2
166 select CPU_HAS_FPU if !CPU_SH4AL_DSP 177 select CPU_HAS_FPU if !CPU_SH4AL_DSP
178 select SYS_SUPPORTS_TMU
167 179
168config CPU_SH4A 180config CPU_SH4A
169 bool 181 bool
@@ -177,6 +189,7 @@ config CPU_SH4AL_DSP
177config CPU_SH5 189config CPU_SH5
178 bool 190 bool
179 select CPU_HAS_FPU 191 select CPU_HAS_FPU
192 select SYS_SUPPORTS_TMU
180 193
181config CPU_SHX2 194config CPU_SHX2
182 bool 195 bool
@@ -210,27 +223,32 @@ config CPU_SUBTYPE_SH7201
210 bool "Support SH7201 processor" 223 bool "Support SH7201 processor"
211 select CPU_SH2A 224 select CPU_SH2A
212 select CPU_HAS_FPU 225 select CPU_HAS_FPU
226 select SYS_SUPPORTS_MTU2
213 227
214config CPU_SUBTYPE_SH7203 228config CPU_SUBTYPE_SH7203
215 bool "Support SH7203 processor" 229 bool "Support SH7203 processor"
216 select CPU_SH2A 230 select CPU_SH2A
217 select CPU_HAS_FPU 231 select CPU_HAS_FPU
218 select SYS_SUPPORTS_CMT 232 select SYS_SUPPORTS_CMT
233 select SYS_SUPPORTS_MTU2
219 234
220config CPU_SUBTYPE_SH7206 235config CPU_SUBTYPE_SH7206
221 bool "Support SH7206 processor" 236 bool "Support SH7206 processor"
222 select CPU_SH2A 237 select CPU_SH2A
223 select SYS_SUPPORTS_CMT 238 select SYS_SUPPORTS_CMT
239 select SYS_SUPPORTS_MTU2
224 240
225config CPU_SUBTYPE_SH7263 241config CPU_SUBTYPE_SH7263
226 bool "Support SH7263 processor" 242 bool "Support SH7263 processor"
227 select CPU_SH2A 243 select CPU_SH2A
228 select CPU_HAS_FPU 244 select CPU_HAS_FPU
229 select SYS_SUPPORTS_CMT 245 select SYS_SUPPORTS_CMT
246 select SYS_SUPPORTS_MTU2
230 247
231config CPU_SUBTYPE_MXG 248config CPU_SUBTYPE_MXG
232 bool "Support MX-G processor" 249 bool "Support MX-G processor"
233 select CPU_SH2A 250 select CPU_SH2A
251 select SYS_SUPPORTS_MTU2
234 help 252 help
235 Select MX-G if running on an R8A03022BG part. 253 Select MX-G if running on an R8A03022BG part.
236 254
@@ -283,6 +301,7 @@ config CPU_SUBTYPE_SH7720
283 bool "Support SH7720 processor" 301 bool "Support SH7720 processor"
284 select CPU_SH3 302 select CPU_SH3
285 select CPU_HAS_DSP 303 select CPU_HAS_DSP
304 select SYS_SUPPORTS_CMT
286 help 305 help
287 Select SH7720 if you have a SH3-DSP SH7720 CPU. 306 Select SH7720 if you have a SH3-DSP SH7720 CPU.
288 307
@@ -290,6 +309,7 @@ config CPU_SUBTYPE_SH7721
290 bool "Support SH7721 processor" 309 bool "Support SH7721 processor"
291 select CPU_SH3 310 select CPU_SH3
292 select CPU_HAS_DSP 311 select CPU_HAS_DSP
312 select SYS_SUPPORTS_CMT
293 help 313 help
294 Select SH7721 if you have a SH3-DSP SH7721 CPU. 314 Select SH7721 if you have a SH3-DSP SH7721 CPU.
295 315
@@ -347,6 +367,16 @@ config CPU_SUBTYPE_SH7723
347 help 367 help
348 Select SH7723 if you have an SH-MobileR2 CPU. 368 Select SH7723 if you have an SH-MobileR2 CPU.
349 369
370config CPU_SUBTYPE_SH7724
371 bool "Support SH7724 processor"
372 select CPU_SH4A
373 select CPU_SHX2
374 select ARCH_SHMOBILE
375 select ARCH_SPARSEMEM_ENABLE
376 select SYS_SUPPORTS_CMT
377 help
378 Select SH7724 if you have an SH-MobileR2R CPU.
379
350config CPU_SUBTYPE_SH7763 380config CPU_SUBTYPE_SH7763
351 bool "Support SH7763 processor" 381 bool "Support SH7763 processor"
352 select CPU_SH4A 382 select CPU_SH4A
@@ -442,48 +472,26 @@ source "arch/sh/boards/Kconfig"
442 472
443menu "Timer and clock configuration" 473menu "Timer and clock configuration"
444 474
445config SH_TMU 475config SH_TIMER_TMU
446 bool "TMU timer support" 476 bool "TMU timer driver"
447 depends on CPU_SH3 || CPU_SH4 477 depends on SYS_SUPPORTS_TMU
448 default y 478 default y
449 select GENERIC_TIME
450 select GENERIC_CLOCKEVENTS
451 help 479 help
452 This enables the use of the TMU as the system timer. 480 This enables the build of the TMU timer driver.
453 481
454config SH_CMT 482config SH_TIMER_CMT
455 bool "CMT timer support" 483 bool "CMT timer driver"
456 depends on SYS_SUPPORTS_CMT && CPU_SH2 484 depends on SYS_SUPPORTS_CMT
457 default y 485 default y
458 help 486 help
459 This enables the use of the CMT as the system timer. 487 This enables build of the CMT timer driver.
460 488
461# 489config SH_TIMER_MTU2
462# Support for the new-style CMT driver. This will replace SH_CMT 490 bool "MTU2 timer driver"
463# once its other dependencies are merged. 491 depends on SYS_SUPPORTS_MTU2
464#
465config SH_TIMER_CMT
466 bool "CMT clockevents driver"
467 depends on SYS_SUPPORTS_CMT && !SH_CMT
468 select GENERIC_CLOCKEVENTS
469
470config SH_MTU2
471 bool "MTU2 timer support"
472 depends on CPU_SH2A
473 default y 492 default y
474 help 493 help
475 This enables the use of the MTU2 as the system timer. 494 This enables build of the MTU2 timer driver.
476
477config SH_TIMER_IRQ
478 int
479 default "28" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || \
480 CPU_SUBTYPE_SH7763
481 default "86" if CPU_SUBTYPE_SH7619
482 default "140" if CPU_SUBTYPE_SH7206
483 default "142" if CPU_SUBTYPE_SH7203 && SH_CMT
484 default "153" if CPU_SUBTYPE_SH7203 && SH_MTU2
485 default "238" if CPU_SUBTYPE_MXG
486 default "16"
487 495
488config SH_PCLK_FREQ 496config SH_PCLK_FREQ
489 int "Peripheral clock frequency (in Hz)" 497 int "Peripheral clock frequency (in Hz)"
@@ -494,7 +502,7 @@ config SH_PCLK_FREQ
494 CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \ 502 CPU_SUBTYPE_SH7760 || CPU_SUBTYPE_SH7705 || \
495 CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \ 503 CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7206 || \
496 CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG || \ 504 CPU_SUBTYPE_SH7263 || CPU_SUBTYPE_MXG || \
497 CPU_SUBTYPE_SH7786 505 CPU_SUBTYPE_SH7786 || CPU_SUBTYPE_SH7724
498 default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R 506 default "60000000" if CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7751R
499 default "66000000" if CPU_SUBTYPE_SH4_202 507 default "66000000" if CPU_SUBTYPE_SH4_202
500 default "50000000" 508 default "50000000"
@@ -503,6 +511,13 @@ config SH_PCLK_FREQ
503 This is necessary for determining the reference clock value on 511 This is necessary for determining the reference clock value on
504 platforms lacking an RTC. 512 platforms lacking an RTC.
505 513
514config SH_CLK_CPG
515 def_bool y
516
517config SH_CLK_CPG_LEGACY
518 depends on SH_CLK_CPG
519 def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE
520
506config SH_CLK_MD 521config SH_CLK_MD
507 int "CPU Mode Pin Setting" 522 int "CPU Mode Pin Setting"
508 depends on CPU_SH2 523 depends on CPU_SH2
@@ -663,27 +678,54 @@ config GUSA_RB
663 LLSC, this should be more efficient than the other alternative of 678 LLSC, this should be more efficient than the other alternative of
664 disabling interrupts around the atomic sequence. 679 disabling interrupts around the atomic sequence.
665 680
681config SPARSE_IRQ
682 bool "Support sparse irq numbering"
683 depends on EXPERIMENTAL
684 help
685 This enables support for sparse irqs. This is useful in general
686 as most CPUs have a fairly sparse array of IRQ vectors, which
687 the irq_desc then maps directly on to. Systems with a high
688 number of off-chip IRQs will want to treat this as
689 experimental until they have been independently verified.
690
691 If you don't know what to do here, say N.
692
666endmenu 693endmenu
667 694
668menu "Boot options" 695menu "Boot options"
669 696
670config ZERO_PAGE_OFFSET 697config ZERO_PAGE_OFFSET
671 hex "Zero page offset" 698 hex
672 default "0x00004000" if SH_SH03 699 default "0x00010000" if PAGE_SIZE_64KB || SH_RTS7751R2D || \
673 default "0x00010000" if PAGE_SIZE_64KB 700 SH_7751_SOLUTION_ENGINE
701 default "0x00004000" if PAGE_SIZE_16KB || SH_SH03
674 default "0x00002000" if PAGE_SIZE_8KB 702 default "0x00002000" if PAGE_SIZE_8KB
675 default "0x00001000" 703 default "0x00001000"
676 help 704 help
677 This sets the default offset of zero page. 705 This sets the default offset of zero page.
678 706
679config BOOT_LINK_OFFSET 707config BOOT_LINK_OFFSET
680 hex "Link address offset for booting" 708 hex
709 default "0x00210000" if SH_SHMIN
710 default "0x00400000" if SH_CAYMAN
711 default "0x00810000" if SH_7780_SOLUTION_ENGINE
712 default "0x009e0000" if SH_TITAN
713 default "0x01800000" if SH_SDK7780
714 default "0x02000000" if SH_EDOSK7760
681 default "0x00800000" 715 default "0x00800000"
682 help 716 help
683 This option allows you to set the link address offset of the zImage. 717 This option allows you to set the link address offset of the zImage.
684 This can be useful if you are on a board which has a small amount of 718 This can be useful if you are on a board which has a small amount of
685 memory. 719 memory.
686 720
721config ENTRY_OFFSET
722 hex
723 default "0x00001000" if PAGE_SIZE_4KB
724 default "0x00002000" if PAGE_SIZE_8KB
725 default "0x00004000" if PAGE_SIZE_16KB
726 default "0x00010000" if PAGE_SIZE_64KB
727 default "0x00000000"
728
687config UBC_WAKEUP 729config UBC_WAKEUP
688 bool "Wakeup UBC on startup" 730 bool "Wakeup UBC on startup"
689 depends on CPU_SH4 && !CPU_SH4A 731 depends on CPU_SH4 && !CPU_SH4A
diff --git a/arch/sh/Kconfig.cpu b/arch/sh/Kconfig.cpu
index c7d704381a6d..cd6e3ea598d5 100644
--- a/arch/sh/Kconfig.cpu
+++ b/arch/sh/Kconfig.cpu
@@ -76,11 +76,6 @@ config SPECULATIVE_EXECUTION
76 76
77 If unsure, say N. 77 If unsure, say N.
78 78
79config SH64_USER_MISALIGNED_FIXUP
80 def_bool y
81 prompt "Fixup misaligned loads/stores occurring in user mode"
82 depends on SUPERH64
83
84config SH64_ID2815_WORKAROUND 79config SH64_ID2815_WORKAROUND
85 bool "Include workaround for SH5-101 cut2 silicon defect ID2815" 80 bool "Include workaround for SH5-101 cut2 silicon defect ID2815"
86 depends on CPU_SUBTYPE_SH5_101 81 depends on CPU_SUBTYPE_SH5_101
@@ -101,9 +96,6 @@ config CPU_HAS_SR_RB
101 See <file:Documentation/sh/register-banks.txt> for further 96 See <file:Documentation/sh/register-banks.txt> for further
102 information on SR.RB and register banking in the kernel in general. 97 information on SR.RB and register banking in the kernel in general.
103 98
104config CPU_HAS_PTEA
105 bool
106
107config CPU_HAS_PTEAEX 99config CPU_HAS_PTEAEX
108 bool 100 bool
109 101
diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug
index 0d62681f72a0..8179cc9be9a4 100644
--- a/arch/sh/Kconfig.debug
+++ b/arch/sh/Kconfig.debug
@@ -38,10 +38,10 @@ config EARLY_SCIF_CONSOLE_PORT
38 default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \ 38 default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \
39 CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366 || \ 39 CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366 || \
40 CPU_SUBTYPE_SH7343 40 CPU_SUBTYPE_SH7343
41 default "0xffe80000" if CPU_SH4
42 default "0xffea0000" if CPU_SUBTYPE_SH7785 41 default "0xffea0000" if CPU_SUBTYPE_SH7785
43 default "0xfffe8000" if CPU_SUBTYPE_SH7203 42 default "0xfffe8000" if CPU_SUBTYPE_SH7203
44 default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263 43 default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
44 default "0xffe80000" if CPU_SH4
45 default "0x00000000" 45 default "0x00000000"
46 46
47config EARLY_PRINTK 47config EARLY_PRINTK
@@ -92,7 +92,7 @@ config 4KSTACKS
92 92
93config IRQSTACKS 93config IRQSTACKS
94 bool "Use separate kernel stacks when processing interrupts" 94 bool "Use separate kernel stacks when processing interrupts"
95 depends on DEBUG_KERNEL && SUPERH32 95 depends on DEBUG_KERNEL && SUPERH32 && BROKEN
96 help 96 help
97 If you say Y here the kernel will use separate kernel stacks 97 If you say Y here the kernel will use separate kernel stacks
98 for handling hard and soft interrupts. This can help avoid 98 for handling hard and soft interrupts. This can help avoid
@@ -122,27 +122,8 @@ config SH_NO_BSS_INIT
122 For all other cases, say N. If this option seems perplexing, or 122 For all other cases, say N. If this option seems perplexing, or
123 you aren't sure, say N. 123 you aren't sure, say N.
124 124
125config MORE_COMPILE_OPTIONS
126 bool "Add any additional compile options"
127 help
128 If you want to add additional CFLAGS to the kernel build, enable this
129 option and then enter what you would like to add in the next question.
130 Note however that -g is already appended with the selection of KGDB.
131
132config COMPILE_OPTIONS
133 string "Additional compile arguments"
134 depends on MORE_COMPILE_OPTIONS
135
136config SH64_SR_WATCH 125config SH64_SR_WATCH
137 bool "Debug: set SR.WATCH to enable hardware watchpoints and trace" 126 bool "Debug: set SR.WATCH to enable hardware watchpoints and trace"
138 depends on SUPERH64 127 depends on SUPERH64
139 128
140config POOR_MANS_STRACE
141 bool "Debug: enable rudimentary strace facility"
142 depends on SUPERH64
143 help
144 This option allows system calls to be traced to the console. It also
145 aids in detecting kernel stack underflow. It is useful for debugging
146 early-userland problems (e.g. init incurring fatal exceptions.)
147
148endmenu 129endmenu
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index bece1f7535f2..75d049b03f7e 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -70,9 +70,6 @@ cflags-$(CONFIG_CPU_LITTLE_ENDIAN) += -ml
70cflags-y += $(call cc-option,-mno-fdpic) 70cflags-y += $(call cc-option,-mno-fdpic)
71cflags-y += $(isaflags-y) -ffreestanding 71cflags-y += $(isaflags-y) -ffreestanding
72 72
73cflags-$(CONFIG_MORE_COMPILE_OPTIONS) += \
74 $(shell echo $(CONFIG_COMPILE_OPTIONS) | sed -e 's/"//g')
75
76OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment \ 73OBJCOPYFLAGS := -O binary -R .note -R .note.gnu.build-id -R .comment \
77 -R .stab -R .stabstr -S 74 -R .stab -R .stabstr -S
78 75
@@ -85,7 +82,6 @@ defaultimage-$(CONFIG_SH_7206_SOLUTION_ENGINE) := vmlinux
85defaultimage-$(CONFIG_SH_7619_SOLUTION_ENGINE) := vmlinux 82defaultimage-$(CONFIG_SH_7619_SOLUTION_ENGINE) := vmlinux
86 83
87# Set some sensible Kbuild defaults 84# Set some sensible Kbuild defaults
88KBUILD_DEFCONFIG := shx3_defconfig
89KBUILD_IMAGE := $(defaultimage-y) 85KBUILD_IMAGE := $(defaultimage-y)
90 86
91# 87#
@@ -93,26 +89,38 @@ KBUILD_IMAGE := $(defaultimage-y)
93# error messages during linking. 89# error messages during linking.
94# 90#
95ifdef CONFIG_SUPERH32 91ifdef CONFIG_SUPERH32
96UTS_MACHINE := sh 92UTS_MACHINE := sh
97LDFLAGS_vmlinux += -e _stext 93BITS := 32
94LDFLAGS_vmlinux += -e _stext
95KBUILD_DEFCONFIG := shx3_defconfig
98else 96else
99UTS_MACHINE := sh64 97UTS_MACHINE := sh64
100LDFLAGS_vmlinux += --defsym phys_stext=_stext-$(CONFIG_PAGE_OFFSET) \ 98BITS := 64
101 --defsym phys_stext_shmedia=phys_stext+1 \ 99LDFLAGS_vmlinux += --defsym phys_stext=_stext-$(CONFIG_PAGE_OFFSET) \
102 -e phys_stext_shmedia 100 --defsym phys_stext_shmedia=phys_stext+1 \
101 -e phys_stext_shmedia
102KBUILD_DEFCONFIG := cayman_defconfig
103endif
104
105ifneq ($(SUBARCH),$(ARCH))
106 ifeq ($(CROSS_COMPILE),)
107 CROSS_COMPILE := $(call cc-cross-prefix, $(UTS_MACHINE)-linux- $(UTS_MACHINE)-linux-gnu- $(UTS_MACHINE)-unknown-linux-gnu-)
108 endif
103endif 109endif
104 110
105ifdef CONFIG_CPU_LITTLE_ENDIAN 111ifdef CONFIG_CPU_LITTLE_ENDIAN
106LDFLAGS_vmlinux += --defsym 'jiffies=jiffies_64' 112ld-bfd := elf32-$(UTS_MACHINE)-linux
113LDFLAGS_vmlinux += --defsym 'jiffies=jiffies_64' --oformat $(ld-bfd)
107LDFLAGS += -EL 114LDFLAGS += -EL
108else 115else
109LDFLAGS_vmlinux += --defsym 'jiffies=jiffies_64+4' 116ld-bfd := elf32-$(UTS_MACHINE)big-linux
117LDFLAGS_vmlinux += --defsym 'jiffies=jiffies_64+4' --oformat $(ld-bfd)
110LDFLAGS += -EB 118LDFLAGS += -EB
111endif 119endif
112 120
113head-y := arch/sh/kernel/init_task.o 121export ld-bfd BITS
114head-$(CONFIG_SUPERH32) += arch/sh/kernel/head_32.o 122
115head-$(CONFIG_SUPERH64) += arch/sh/kernel/head_64.o 123head-y := arch/sh/kernel/init_task.o arch/sh/kernel/head_$(BITS).o
116 124
117core-y += arch/sh/kernel/ arch/sh/mm/ arch/sh/boards/ 125core-y += arch/sh/kernel/ arch/sh/mm/ arch/sh/boards/
118core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/ 126core-$(CONFIG_SH_FPU_EMU) += arch/sh/math-emu/
@@ -193,10 +201,11 @@ zImage uImage uImage.srec vmlinux.srec: vmlinux
193 201
194compressed: zImage 202compressed: zImage
195 203
196archprepare: maketools arch/sh/lib64/syscalltab.h 204archprepare: maketools
197 205
198archclean: 206archclean:
199 $(Q)$(MAKE) $(clean)=$(boot) 207 $(Q)$(MAKE) $(clean)=$(boot)
208 $(Q)$(MAKE) $(clean)=arch/sh/kernel/vsyscall
200 209
201define archhelp 210define archhelp
202 @echo '* zImage - Compressed kernel image' 211 @echo '* zImage - Compressed kernel image'
@@ -205,34 +214,4 @@ define archhelp
205 @echo ' uImage.srec - Create an S-record for U-Boot' 214 @echo ' uImage.srec - Create an S-record for U-Boot'
206endef 215endef
207 216
208define filechk_gen-syscalltab 217CLEAN_FILES += include/asm-sh/machtypes.h
209 (set -e; \
210 echo "/*"; \
211 echo " * DO NOT MODIFY."; \
212 echo " *"; \
213 echo " * This file was generated by arch/sh/Makefile"; \
214 echo " * Any changes will be reverted at build time."; \
215 echo " */"; \
216 echo ""; \
217 echo "#ifndef __SYSCALLTAB_H"; \
218 echo "#define __SYSCALLTAB_H"; \
219 echo ""; \
220 echo "#include <linux/kernel.h>"; \
221 echo ""; \
222 echo "struct syscall_info {"; \
223 echo " const char *name;"; \
224 echo "} syscall_info_table[] = {"; \
225 sed -e '/^.*\.long /!d;s// { "/;s/\(\([^/]*\)\/\)\{1\}.*/\2/; \
226 s/[ \t]*$$//g;s/$$/" },/;s/\("\)sys_/\1/g'; \
227 echo "};"; \
228 echo ""; \
229 echo "#define NUM_SYSCALL_INFO_ENTRIES ARRAY_SIZE(syscall_info_table)";\
230 echo ""; \
231 echo "#endif /* __SYSCALLTAB_H */" )
232endef
233
234arch/sh/lib64/syscalltab.h: arch/sh/kernel/syscalls_64.S
235 $(call filechk,gen-syscalltab)
236
237CLEAN_FILES += arch/sh/lib64/syscalltab.h \
238 include/asm-sh/machtypes.h
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index dcc1af8a2cfe..1c91b1f565d5 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -46,6 +46,15 @@ config SH_7722_SOLUTION_ENGINE
46 Select 7722 SolutionEngine if configuring for a Hitachi SH772 46 Select 7722 SolutionEngine if configuring for a Hitachi SH772
47 evaluation board. 47 evaluation board.
48 48
49config SH_7724_SOLUTION_ENGINE
50 bool "SolutionEngine7724"
51 select SOLUTION_ENGINE
52 depends on CPU_SUBTYPE_SH7724
53 select ARCH_REQUIRE_GPIOLIB
54 help
55 Select 7724 SolutionEngine if configuring for a Hitachi SH7724
56 evaluation board.
57
49config SH_7751_SOLUTION_ENGINE 58config SH_7751_SOLUTION_ENGINE
50 bool "SolutionEngine7751" 59 bool "SolutionEngine7751"
51 select SOLUTION_ENGINE 60 select SOLUTION_ENGINE
@@ -121,7 +130,7 @@ config SH_RTS7751R2D
121 bool "RTS7751R2D" 130 bool "RTS7751R2D"
122 depends on CPU_SUBTYPE_SH7751R 131 depends on CPU_SUBTYPE_SH7751R
123 select SYS_SUPPORTS_PCI 132 select SYS_SUPPORTS_PCI
124 select IO_TRAPPED 133 select IO_TRAPPED if MMU
125 help 134 help
126 Select RTS7751R2D if configuring for a Renesas Technology 135 Select RTS7751R2D if configuring for a Renesas Technology
127 Sales SH-Graphics board. 136 Sales SH-Graphics board.
@@ -145,13 +154,13 @@ config SH_HIGHLANDER
145 bool "Highlander" 154 bool "Highlander"
146 depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 155 depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
147 select SYS_SUPPORTS_PCI 156 select SYS_SUPPORTS_PCI
148 select IO_TRAPPED 157 select IO_TRAPPED if MMU
149 158
150config SH_SH7785LCR 159config SH_SH7785LCR
151 bool "SH7785LCR" 160 bool "SH7785LCR"
152 depends on CPU_SUBTYPE_SH7785 161 depends on CPU_SUBTYPE_SH7785
153 select SYS_SUPPORTS_PCI 162 select SYS_SUPPORTS_PCI
154 select IO_TRAPPED 163 select IO_TRAPPED if MMU
155 164
156config SH_SH7785LCR_29BIT_PHYSMAPS 165config SH_SH7785LCR_29BIT_PHYSMAPS
157 bool "SH7785LCR 29bit physmaps" 166 bool "SH7785LCR 29bit physmaps"
diff --git a/arch/sh/boards/board-ap325rxa.c b/arch/sh/boards/board-ap325rxa.c
index f2a29641b6a3..1c4d83ef2a47 100644
--- a/arch/sh/boards/board-ap325rxa.c
+++ b/arch/sh/boards/board-ap325rxa.c
@@ -535,6 +535,18 @@ static int __init ap325rxa_devices_setup(void)
535} 535}
536device_initcall(ap325rxa_devices_setup); 536device_initcall(ap325rxa_devices_setup);
537 537
538/* Return the board specific boot mode pin configuration */
539static int ap325rxa_mode_pins(void)
540{
541 /* MD0=0, MD1=0, MD2=0: Clock Mode 0
542 * MD3=0: 16-bit Area0 Bus Width
543 * MD5=1: Little Endian
544 * TSTMD=1, MD8=1: Test Mode Disabled
545 */
546 return MODE_PIN5 | MODE_PIN8;
547}
548
538static struct sh_machine_vector mv_ap325rxa __initmv = { 549static struct sh_machine_vector mv_ap325rxa __initmv = {
539 .mv_name = "AP-325RXA", 550 .mv_name = "AP-325RXA",
551 .mv_mode_pins = ap325rxa_mode_pins,
540}; 552};
diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c
index 6f94f17adc46..7be56fb06c1f 100644
--- a/arch/sh/boards/board-sh7785lcr.c
+++ b/arch/sh/boards/board-sh7785lcr.c
@@ -2,12 +2,12 @@
2 * Renesas Technology Corp. R0P7785LC0011RL Support. 2 * Renesas Technology Corp. R0P7785LC0011RL Support.
3 * 3 *
4 * Copyright (C) 2008 Yoshihiro Shimoda 4 * Copyright (C) 2008 Yoshihiro Shimoda
5 * Copyright (C) 2009 Paul Mundt
5 * 6 *
6 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
8 * for more details. 9 * for more details.
9 */ 10 */
10
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/platform_device.h> 12#include <linux/platform_device.h>
13#include <linux/sm501.h> 13#include <linux/sm501.h>
@@ -19,8 +19,12 @@
19#include <linux/i2c-pca-platform.h> 19#include <linux/i2c-pca-platform.h>
20#include <linux/i2c-algo-pca.h> 20#include <linux/i2c-algo-pca.h>
21#include <linux/irq.h> 21#include <linux/irq.h>
22#include <asm/heartbeat.h> 22#include <linux/clk.h>
23#include <linux/errno.h>
23#include <mach/sh7785lcr.h> 24#include <mach/sh7785lcr.h>
25#include <asm/heartbeat.h>
26#include <asm/clock.h>
27#include <cpu/sh7785.h>
24 28
25/* 29/*
26 * NOTE: This board has 2 physical memory maps. 30 * NOTE: This board has 2 physical memory maps.
@@ -273,6 +277,20 @@ void __init init_sh7785lcr_IRQ(void)
273 plat_irq_setup_pins(IRQ_MODE_IRQ3210); 277 plat_irq_setup_pins(IRQ_MODE_IRQ3210);
274} 278}
275 279
280static int sh7785lcr_clk_init(void)
281{
282 struct clk *clk;
283 int ret;
284
285 clk = clk_get(NULL, "extal");
286 if (!clk || IS_ERR(clk))
287 return PTR_ERR(clk);
288 ret = clk_set_rate(clk, 33333333);
289 clk_put(clk);
290
291 return ret;
292}
293
276static void sh7785lcr_power_off(void) 294static void sh7785lcr_power_off(void)
277{ 295{
278 unsigned char *p; 296 unsigned char *p;
@@ -303,12 +321,34 @@ static void __init sh7785lcr_setup(char **cmdline_p)
303 writel(0x000307c2, sm501_reg); 321 writel(0x000307c2, sm501_reg);
304} 322}
305 323
324/* Return the board specific boot mode pin configuration */
325static int sh7785lcr_mode_pins(void)
326{
327 int value = 0;
328
329 /* These are the factory default settings of S1 and S2.
330 * If you change these dip switches then you will need to
331 * adjust the values below as well.
332 */
333 value |= MODE_PIN4; /* Clock Mode 16 */
334 value |= MODE_PIN5; /* 32-bit Area0 bus width */
335 value |= MODE_PIN6; /* 32-bit Area0 bus width */
336 value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */
337 value |= MODE_PIN8; /* Little Endian */
338 value |= MODE_PIN9; /* Master Mode */
339 value |= MODE_PIN14; /* No PLL step-up */
340
341 return value;
342}
343
306/* 344/*
307 * The Machine Vector 345 * The Machine Vector
308 */ 346 */
309static struct sh_machine_vector mv_sh7785lcr __initmv = { 347static struct sh_machine_vector mv_sh7785lcr __initmv = {
310 .mv_name = "SH7785LCR", 348 .mv_name = "SH7785LCR",
311 .mv_setup = sh7785lcr_setup, 349 .mv_setup = sh7785lcr_setup,
350 .mv_clk_init = sh7785lcr_clk_init,
312 .mv_init_irq = init_sh7785lcr_IRQ, 351 .mv_init_irq = init_sh7785lcr_IRQ,
352 .mv_mode_pins = sh7785lcr_mode_pins,
313}; 353};
314 354
diff --git a/arch/sh/boards/mach-cayman/Makefile b/arch/sh/boards/mach-cayman/Makefile
index cafe1ac3b29c..00fa3eaecb1b 100644
--- a/arch/sh/boards/mach-cayman/Makefile
+++ b/arch/sh/boards/mach-cayman/Makefile
@@ -1,4 +1,4 @@
1# 1#
2# Makefile for the Hitachi Cayman specific parts of the kernel 2# Makefile for the Hitachi Cayman specific parts of the kernel
3# 3#
4obj-y := setup.o irq.o 4obj-y := setup.o irq.o panic.o
diff --git a/arch/sh/boards/mach-cayman/irq.c b/arch/sh/boards/mach-cayman/irq.c
index da62ad516994..33f770856319 100644
--- a/arch/sh/boards/mach-cayman/irq.c
+++ b/arch/sh/boards/mach-cayman/irq.c
@@ -142,26 +142,11 @@ int cayman_irq_demux(int evt)
142 return irq; 142 return irq;
143} 143}
144 144
145#if defined(CONFIG_PROC_FS) && defined(CONFIG_SYSCTL)
146int cayman_irq_describe(char* p, int irq)
147{
148 if (irq < NR_INTC_IRQS) {
149 return intc_irq_describe(p, irq);
150 } else if (irq < NR_INTC_IRQS + 8) {
151 return sprintf(p, "(SMSC %d)", irq - NR_INTC_IRQS);
152 } else if ((irq >= NR_INTC_IRQS + 24) && (irq < NR_INTC_IRQS + 32)) {
153 return sprintf(p, "(PCI2 %d)", irq - (NR_INTC_IRQS + 24));
154 }
155
156 return 0;
157}
158#endif
159
160void init_cayman_irq(void) 145void init_cayman_irq(void)
161{ 146{
162 int i; 147 int i;
163 148
164 epld_virt = onchip_remap(EPLD_BASE, 1024, "EPLD"); 149 epld_virt = (unsigned long)ioremap_nocache(EPLD_BASE, 1024);
165 if (!epld_virt) { 150 if (!epld_virt) {
166 printk(KERN_ERR "Cayman IRQ: Unable to remap EPLD\n"); 151 printk(KERN_ERR "Cayman IRQ: Unable to remap EPLD\n");
167 return; 152 return;
diff --git a/arch/sh/boards/mach-cayman/panic.c b/arch/sh/boards/mach-cayman/panic.c
new file mode 100644
index 000000000000..d1e67306d07c
--- /dev/null
+++ b/arch/sh/boards/mach-cayman/panic.c
@@ -0,0 +1,49 @@
1/*
2 * Copyright (C) 2003 Richard Curnow, SuperH UK Limited
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 */
8
9#include <linux/kernel.h>
10#include <linux/io.h>
11#include <cpu/registers.h>
12
13/* THIS IS A PHYSICAL ADDRESS */
14#define HDSP2534_ADDR (0x04002100)
15
16static void poor_mans_delay(void)
17{
18 int i;
19
20 for (i = 0; i < 2500000; i++)
21 cpu_relax();
22}
23
24static void show_value(unsigned long x)
25{
26 int i;
27 unsigned nibble;
28 for (i = 0; i < 8; i++) {
29 nibble = ((x >> (i * 4)) & 0xf);
30
31 __raw_writeb(nibble + ((nibble > 9) ? 55 : 48),
32 HDSP2534_ADDR + 0xe0 + ((7 - i) << 2));
33 }
34}
35
36void
37panic_handler(unsigned long panicPC, unsigned long panicSSR,
38 unsigned long panicEXPEVT)
39{
40 while (1) {
41 /* This piece of code displays the PC on the LED display */
42 show_value(panicPC);
43 poor_mans_delay();
44 show_value(panicSSR);
45 poor_mans_delay();
46 show_value(panicEXPEVT);
47 poor_mans_delay();
48 }
49}
diff --git a/arch/sh/boards/mach-cayman/setup.c b/arch/sh/boards/mach-cayman/setup.c
index e7f9cc5f2ff1..7e8216ac31bd 100644
--- a/arch/sh/boards/mach-cayman/setup.c
+++ b/arch/sh/boards/mach-cayman/setup.c
@@ -102,7 +102,7 @@ static int __init smsc_superio_setup(void)
102{ 102{
103 unsigned char devid, devrev; 103 unsigned char devid, devrev;
104 104
105 smsc_superio_virt = onchip_remap(SMSC_SUPERIO_BASE, 1024, "SMSC SuperIO"); 105 smsc_superio_virt = (unsigned long)ioremap_nocache(SMSC_SUPERIO_BASE, 1024);
106 if (!smsc_superio_virt) { 106 if (!smsc_superio_virt) {
107 panic("Unable to remap SMSC SuperIO\n"); 107 panic("Unable to remap SMSC SuperIO\n");
108 } 108 }
diff --git a/arch/sh/boards/mach-dreamcast/setup.c b/arch/sh/boards/mach-dreamcast/setup.c
index d1bee4884cd6..ebe99227d4e6 100644
--- a/arch/sh/boards/mach-dreamcast/setup.c
+++ b/arch/sh/boards/mach-dreamcast/setup.c
@@ -30,7 +30,6 @@
30 30
31extern struct irq_chip systemasic_int; 31extern struct irq_chip systemasic_int;
32extern void aica_time_init(void); 32extern void aica_time_init(void);
33extern int gapspci_init(void);
34extern int systemasic_irq_demux(int); 33extern int systemasic_irq_demux(int);
35 34
36static void __init dreamcast_setup(char **cmdline_p) 35static void __init dreamcast_setup(char **cmdline_p)
@@ -51,11 +50,6 @@ static void __init dreamcast_setup(char **cmdline_p)
51 handle_level_irq); 50 handle_level_irq);
52 51
53 board_time_init = aica_time_init; 52 board_time_init = aica_time_init;
54
55#ifdef CONFIG_PCI
56 if (gapspci_init() < 0)
57 printk(KERN_WARNING "GAPSPCI was not detected.\n");
58#endif
59} 53}
60 54
61static struct sh_machine_vector mv_dreamcast __initmv = { 55static struct sh_machine_vector mv_dreamcast __initmv = {
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index 1ee1de0bc1c3..6ed401cd3156 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -584,3 +584,22 @@ static int __init migor_devices_setup(void)
584 return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices)); 584 return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
585} 585}
586__initcall(migor_devices_setup); 586__initcall(migor_devices_setup);
587
588/* Return the board specific boot mode pin configuration */
589static int migor_mode_pins(void)
590{
591 /* MD0=1, MD1=1, MD2=0: Clock Mode 3
592 * MD3=0: 16-bit Area0 Bus Width
593 * MD5=1: Little Endian
594 * TSTMD=1, MD8=0: Test Mode Disabled
595 */
596 return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
597}
598
599/*
600 * The Machine Vector
601 */
602static struct sh_machine_vector mv_migor __initmv = {
603 .mv_name = "Migo-R",
604 .mv_mode_pins = migor_mode_pins,
605};
diff --git a/arch/sh/boards/mach-r2d/setup.c b/arch/sh/boards/mach-r2d/setup.c
index c585be00956e..a625ecb93e47 100644
--- a/arch/sh/boards/mach-r2d/setup.c
+++ b/arch/sh/boards/mach-r2d/setup.c
@@ -10,6 +10,9 @@
10 */ 10 */
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/platform_device.h> 12#include <linux/platform_device.h>
13#include <linux/mtd/mtd.h>
14#include <linux/mtd/partitions.h>
15#include <linux/mtd/physmap.h>
13#include <linux/ata_platform.h> 16#include <linux/ata_platform.h>
14#include <linux/sm501.h> 17#include <linux/sm501.h>
15#include <linux/sm501-regs.h> 18#include <linux/sm501-regs.h>
@@ -181,6 +184,50 @@ static struct platform_device sm501_device = {
181 .resource = sm501_resources, 184 .resource = sm501_resources,
182}; 185};
183 186
187static struct mtd_partition r2d_partitions[] = {
188 {
189 .name = "U-Boot",
190 .offset = 0x00000000,
191 .size = 0x00040000,
192 .mask_flags = MTD_WRITEABLE,
193 }, {
194 .name = "Environment",
195 .offset = MTDPART_OFS_NXTBLK,
196 .size = 0x00040000,
197 .mask_flags = MTD_WRITEABLE,
198 }, {
199 .name = "Kernel",
200 .offset = MTDPART_OFS_NXTBLK,
201 .size = 0x001c0000,
202 }, {
203 .name = "Flash_FS",
204 .offset = MTDPART_OFS_NXTBLK,
205 .size = MTDPART_SIZ_FULL,
206 }
207};
208
209static struct physmap_flash_data flash_data = {
210 .width = 2,
211 .nr_parts = ARRAY_SIZE(r2d_partitions),
212 .parts = r2d_partitions,
213};
214
215static struct resource flash_resource = {
216 .start = 0x00000000,
217 .end = 0x02000000,
218 .flags = IORESOURCE_MEM,
219};
220
221static struct platform_device flash_device = {
222 .name = "physmap-flash",
223 .id = -1,
224 .resource = &flash_resource,
225 .num_resources = 1,
226 .dev = {
227 .platform_data = &flash_data,
228 },
229};
230
184static struct platform_device *rts7751r2d_devices[] __initdata = { 231static struct platform_device *rts7751r2d_devices[] __initdata = {
185 &sm501_device, 232 &sm501_device,
186 &heartbeat_device, 233 &heartbeat_device,
@@ -203,6 +250,9 @@ static int __init rts7751r2d_devices_setup(void)
203 if (register_trapped_io(&cf_trapped_io) == 0) 250 if (register_trapped_io(&cf_trapped_io) == 0)
204 platform_device_register(&cf_ide_device); 251 platform_device_register(&cf_ide_device);
205 252
253 if (mach_is_r2d_plus())
254 platform_device_register(&flash_device);
255
206 spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus)); 256 spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus));
207 257
208 return platform_add_devices(rts7751r2d_devices, 258 return platform_add_devices(rts7751r2d_devices,
diff --git a/arch/sh/boards/mach-se/7724/Makefile b/arch/sh/boards/mach-se/7724/Makefile
new file mode 100644
index 000000000000..349cbd6ce82d
--- /dev/null
+++ b/arch/sh/boards/mach-se/7724/Makefile
@@ -0,0 +1,10 @@
1#
2# Makefile for the HITACHI UL SolutionEngine 7724 specific parts of the kernel
3#
4# This file is subject to the terms and conditions of the GNU General Public
5# License. See the file "COPYING" in the main directory of this archive
6# for more details.
7#
8#
9
10obj-y := setup.o irq.o \ No newline at end of file
diff --git a/arch/sh/boards/mach-se/7724/irq.c b/arch/sh/boards/mach-se/7724/irq.c
new file mode 100644
index 000000000000..f76cf3b49f23
--- /dev/null
+++ b/arch/sh/boards/mach-se/7724/irq.c
@@ -0,0 +1,139 @@
1/*
2 * linux/arch/sh/boards/se/7724/irq.c
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 *
8 * Based on linux/arch/sh/boards/se/7722/irq.c
9 * Copyright (C) 2007 Nobuhiro Iwamatsu
10 *
11 * Hitachi UL SolutionEngine 7724 Support.
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
15 * for more details.
16 */
17#include <linux/init.h>
18#include <linux/irq.h>
19#include <linux/interrupt.h>
20#include <asm/irq.h>
21#include <asm/io.h>
22#include <mach-se/mach/se7724.h>
23
24struct fpga_irq {
25 unsigned long sraddr;
26 unsigned long mraddr;
27 unsigned short mask;
28 unsigned int base;
29};
30
31static unsigned int fpga2irq(unsigned int irq)
32{
33 if (irq >= IRQ0_BASE &&
34 irq <= IRQ0_END)
35 return IRQ0_IRQ;
36 else if (irq >= IRQ1_BASE &&
37 irq <= IRQ1_END)
38 return IRQ1_IRQ;
39 else
40 return IRQ2_IRQ;
41}
42
43static struct fpga_irq get_fpga_irq(unsigned int irq)
44{
45 struct fpga_irq set;
46
47 switch (irq) {
48 case IRQ0_IRQ:
49 set.sraddr = IRQ0_SR;
50 set.mraddr = IRQ0_MR;
51 set.mask = IRQ0_MASK;
52 set.base = IRQ0_BASE;
53 break;
54 case IRQ1_IRQ:
55 set.sraddr = IRQ1_SR;
56 set.mraddr = IRQ1_MR;
57 set.mask = IRQ1_MASK;
58 set.base = IRQ1_BASE;
59 break;
60 default:
61 set.sraddr = IRQ2_SR;
62 set.mraddr = IRQ2_MR;
63 set.mask = IRQ2_MASK;
64 set.base = IRQ2_BASE;
65 break;
66 }
67
68 return set;
69}
70
71static void disable_se7724_irq(unsigned int irq)
72{
73 struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
74 unsigned int bit = irq - set.base;
75 ctrl_outw(ctrl_inw(set.mraddr) | 0x0001 << bit, set.mraddr);
76}
77
78static void enable_se7724_irq(unsigned int irq)
79{
80 struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
81 unsigned int bit = irq - set.base;
82 ctrl_outw(ctrl_inw(set.mraddr) & ~(0x0001 << bit), set.mraddr);
83}
84
85static struct irq_chip se7724_irq_chip __read_mostly = {
86 .name = "SE7724-FPGA",
87 .mask = disable_se7724_irq,
88 .unmask = enable_se7724_irq,
89 .mask_ack = disable_se7724_irq,
90};
91
92static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc)
93{
94 struct fpga_irq set = get_fpga_irq(irq);
95 unsigned short intv = ctrl_inw(set.sraddr);
96 struct irq_desc *ext_desc;
97 unsigned int ext_irq = set.base;
98
99 intv &= set.mask;
100
101 while (intv) {
102 if (intv & 0x0001) {
103 ext_desc = irq_desc + ext_irq;
104 handle_level_irq(ext_irq, ext_desc);
105 }
106 intv >>= 1;
107 ext_irq++;
108 }
109}
110
111/*
112 * Initialize IRQ setting
113 */
114void __init init_se7724_IRQ(void)
115{
116 int i;
117
118 ctrl_outw(0xffff, IRQ0_MR); /* mask all */
119 ctrl_outw(0xffff, IRQ1_MR); /* mask all */
120 ctrl_outw(0xffff, IRQ2_MR); /* mask all */
121 ctrl_outw(0x0000, IRQ0_SR); /* clear irq */
122 ctrl_outw(0x0000, IRQ1_SR); /* clear irq */
123 ctrl_outw(0x0000, IRQ2_SR); /* clear irq */
124 ctrl_outw(0x002a, IRQ_MODE); /* set irq type */
125
126 for (i = 0; i < SE7724_FPGA_IRQ_NR; i++)
127 set_irq_chip_and_handler_name(SE7724_FPGA_IRQ_BASE + i,
128 &se7724_irq_chip,
129 handle_level_irq, "level");
130
131 set_irq_chained_handler(IRQ0_IRQ, se7724_irq_demux);
132 set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
133
134 set_irq_chained_handler(IRQ1_IRQ, se7724_irq_demux);
135 set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
136
137 set_irq_chained_handler(IRQ2_IRQ, se7724_irq_demux);
138 set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW);
139}
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
new file mode 100644
index 000000000000..9cd04bd558b8
--- /dev/null
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -0,0 +1,448 @@
1/*
2 * linux/arch/sh/boards/se/7724/setup.c
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13#include <linux/init.h>
14#include <linux/device.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/mtd/physmap.h>
18#include <linux/delay.h>
19#include <linux/smc91x.h>
20#include <linux/gpio.h>
21#include <linux/input.h>
22#include <video/sh_mobile_lcdc.h>
23#include <media/sh_mobile_ceu.h>
24#include <asm/io.h>
25#include <asm/heartbeat.h>
26#include <asm/sh_keysc.h>
27#include <cpu/sh7724.h>
28#include <mach-se/mach/se7724.h>
29
30/*
31 * SWx 1234 5678
32 * ------------------------------------
33 * SW31 : 1001 1100 : default
34 * SW32 : 0111 1111 : use on board flash
35 *
36 * SW41 : abxx xxxx -> a = 0 : Analog monitor
37 * 1 : Digital monitor
38 * b = 0 : VGA
39 * 1 : SVGA
40 */
41
42/* Heartbeat */
43static struct heartbeat_data heartbeat_data = {
44 .regsize = 16,
45};
46
47static struct resource heartbeat_resources[] = {
48 [0] = {
49 .start = PA_LED,
50 .end = PA_LED,
51 .flags = IORESOURCE_MEM,
52 },
53};
54
55static struct platform_device heartbeat_device = {
56 .name = "heartbeat",
57 .id = -1,
58 .dev = {
59 .platform_data = &heartbeat_data,
60 },
61 .num_resources = ARRAY_SIZE(heartbeat_resources),
62 .resource = heartbeat_resources,
63};
64
65/* LAN91C111 */
66static struct smc91x_platdata smc91x_info = {
67 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
68};
69
70static struct resource smc91x_eth_resources[] = {
71 [0] = {
72 .name = "SMC91C111" ,
73 .start = 0x1a300300,
74 .end = 0x1a30030f,
75 .flags = IORESOURCE_MEM,
76 },
77 [1] = {
78 .start = IRQ0_SMC,
79 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
80 },
81};
82
83static struct platform_device smc91x_eth_device = {
84 .name = "smc91x",
85 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
86 .resource = smc91x_eth_resources,
87 .dev = {
88 .platform_data = &smc91x_info,
89 },
90};
91
92/* MTD */
93static struct mtd_partition nor_flash_partitions[] = {
94 {
95 .name = "uboot",
96 .offset = 0,
97 .size = (1 * 1024 * 1024),
98 .mask_flags = MTD_WRITEABLE, /* Read-only */
99 }, {
100 .name = "kernel",
101 .offset = MTDPART_OFS_APPEND,
102 .size = (2 * 1024 * 1024),
103 }, {
104 .name = "free-area",
105 .offset = MTDPART_OFS_APPEND,
106 .size = MTDPART_SIZ_FULL,
107 },
108};
109
110static struct physmap_flash_data nor_flash_data = {
111 .width = 2,
112 .parts = nor_flash_partitions,
113 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
114};
115
116static struct resource nor_flash_resources[] = {
117 [0] = {
118 .name = "NOR Flash",
119 .start = 0x00000000,
120 .end = 0x01ffffff,
121 .flags = IORESOURCE_MEM,
122 }
123};
124
125static struct platform_device nor_flash_device = {
126 .name = "physmap-flash",
127 .resource = nor_flash_resources,
128 .num_resources = ARRAY_SIZE(nor_flash_resources),
129 .dev = {
130 .platform_data = &nor_flash_data,
131 },
132};
133
134/* LCDC */
135static struct sh_mobile_lcdc_info lcdc_info = {
136 .clock_source = LCDC_CLK_EXTERNAL,
137 .ch[0] = {
138 .chan = LCDC_CHAN_MAINLCD,
139 .bpp = 16,
140 .clock_divider = 1,
141 .lcd_cfg = {
142 .name = "LB070WV1",
143 .sync = 0, /* hsync and vsync are active low */
144 },
145 .lcd_size_cfg = { /* 7.0 inch */
146 .width = 152,
147 .height = 91,
148 },
149 .board_cfg = {
150 },
151 }
152};
153
154static struct resource lcdc_resources[] = {
155 [0] = {
156 .name = "LCDC",
157 .start = 0xfe940000,
158 .end = 0xfe941fff,
159 .flags = IORESOURCE_MEM,
160 },
161 [1] = {
162 .start = 106,
163 .flags = IORESOURCE_IRQ,
164 },
165};
166
167static struct platform_device lcdc_device = {
168 .name = "sh_mobile_lcdc_fb",
169 .num_resources = ARRAY_SIZE(lcdc_resources),
170 .resource = lcdc_resources,
171 .dev = {
172 .platform_data = &lcdc_info,
173 },
174};
175
176/* CEU0 */
177static struct sh_mobile_ceu_info sh_mobile_ceu0_info = {
178 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
179};
180
181static struct resource ceu0_resources[] = {
182 [0] = {
183 .name = "CEU0",
184 .start = 0xfe910000,
185 .end = 0xfe91009f,
186 .flags = IORESOURCE_MEM,
187 },
188 [1] = {
189 .start = 52,
190 .flags = IORESOURCE_IRQ,
191 },
192 [2] = {
193 /* place holder for contiguous memory */
194 },
195};
196
197static struct platform_device ceu0_device = {
198 .name = "sh_mobile_ceu",
199 .id = 0, /* "ceu0" clock */
200 .num_resources = ARRAY_SIZE(ceu0_resources),
201 .resource = ceu0_resources,
202 .dev = {
203 .platform_data = &sh_mobile_ceu0_info,
204 },
205};
206
207/* CEU1 */
208static struct sh_mobile_ceu_info sh_mobile_ceu1_info = {
209 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
210};
211
212static struct resource ceu1_resources[] = {
213 [0] = {
214 .name = "CEU1",
215 .start = 0xfe914000,
216 .end = 0xfe91409f,
217 .flags = IORESOURCE_MEM,
218 },
219 [1] = {
220 .start = 63,
221 .flags = IORESOURCE_IRQ,
222 },
223 [2] = {
224 /* place holder for contiguous memory */
225 },
226};
227
228static struct platform_device ceu1_device = {
229 .name = "sh_mobile_ceu",
230 .id = 1, /* "ceu1" clock */
231 .num_resources = ARRAY_SIZE(ceu1_resources),
232 .resource = ceu1_resources,
233 .dev = {
234 .platform_data = &sh_mobile_ceu1_info,
235 },
236};
237
238/* KEYSC */
239static struct sh_keysc_info keysc_info = {
240 .mode = SH_KEYSC_MODE_1,
241 .scan_timing = 10,
242 .delay = 50,
243 .keycodes = {
244 KEY_1, KEY_2, KEY_3, KEY_4, KEY_5,
245 KEY_6, KEY_7, KEY_8, KEY_9, KEY_A,
246 KEY_B, KEY_C, KEY_D, KEY_E, KEY_F,
247 KEY_G, KEY_H, KEY_I, KEY_K, KEY_L,
248 KEY_M, KEY_N, KEY_O, KEY_P, KEY_Q,
249 KEY_R, KEY_S, KEY_T, KEY_U, KEY_V,
250 },
251};
252
253static struct resource keysc_resources[] = {
254 [0] = {
255 .start = 0x1a204000,
256 .end = 0x1a20400f,
257 .flags = IORESOURCE_MEM,
258 },
259 [1] = {
260 .start = IRQ0_KEY,
261 .flags = IORESOURCE_IRQ,
262 },
263};
264
265static struct platform_device keysc_device = {
266 .name = "sh_keysc",
267 .id = 0, /* "keysc0" clock */
268 .num_resources = ARRAY_SIZE(keysc_resources),
269 .resource = keysc_resources,
270 .dev = {
271 .platform_data = &keysc_info,
272 },
273};
274
275static struct platform_device *ms7724se_devices[] __initdata = {
276 &heartbeat_device,
277 &smc91x_eth_device,
278 &lcdc_device,
279 &nor_flash_device,
280 &ceu0_device,
281 &ceu1_device,
282 &keysc_device,
283};
284
285#define SW4140 0xBA201000
286#define FPGA_OUT 0xBA200400
287#define PORT_HIZA 0xA4050158
288
289#define SW41_A 0x0100
290#define SW41_B 0x0200
291#define SW41_C 0x0400
292#define SW41_D 0x0800
293#define SW41_E 0x1000
294#define SW41_F 0x2000
295#define SW41_G 0x4000
296#define SW41_H 0x8000
297static int __init devices_setup(void)
298{
299 u16 sw = ctrl_inw(SW4140); /* select camera, monitor */
300
301 /* Reset Release */
302 ctrl_outw(ctrl_inw(FPGA_OUT) &
303 ~((1 << 1) | /* LAN */
304 (1 << 6) | /* VIDEO DAC */
305 (1 << 12)), /* USB0 */
306 FPGA_OUT);
307
308 /* enable IRQ 0,1,2 */
309 gpio_request(GPIO_FN_INTC_IRQ0, NULL);
310 gpio_request(GPIO_FN_INTC_IRQ1, NULL);
311 gpio_request(GPIO_FN_INTC_IRQ2, NULL);
312
313 /* enable SCIFA3 */
314 gpio_request(GPIO_FN_SCIF3_I_SCK, NULL);
315 gpio_request(GPIO_FN_SCIF3_I_RXD, NULL);
316 gpio_request(GPIO_FN_SCIF3_I_TXD, NULL);
317 gpio_request(GPIO_FN_SCIF3_I_CTS, NULL);
318 gpio_request(GPIO_FN_SCIF3_I_RTS, NULL);
319
320 /* enable LCDC */
321 gpio_request(GPIO_FN_LCDD23, NULL);
322 gpio_request(GPIO_FN_LCDD22, NULL);
323 gpio_request(GPIO_FN_LCDD21, NULL);
324 gpio_request(GPIO_FN_LCDD20, NULL);
325 gpio_request(GPIO_FN_LCDD19, NULL);
326 gpio_request(GPIO_FN_LCDD18, NULL);
327 gpio_request(GPIO_FN_LCDD17, NULL);
328 gpio_request(GPIO_FN_LCDD16, NULL);
329 gpio_request(GPIO_FN_LCDD15, NULL);
330 gpio_request(GPIO_FN_LCDD14, NULL);
331 gpio_request(GPIO_FN_LCDD13, NULL);
332 gpio_request(GPIO_FN_LCDD12, NULL);
333 gpio_request(GPIO_FN_LCDD11, NULL);
334 gpio_request(GPIO_FN_LCDD10, NULL);
335 gpio_request(GPIO_FN_LCDD9, NULL);
336 gpio_request(GPIO_FN_LCDD8, NULL);
337 gpio_request(GPIO_FN_LCDD7, NULL);
338 gpio_request(GPIO_FN_LCDD6, NULL);
339 gpio_request(GPIO_FN_LCDD5, NULL);
340 gpio_request(GPIO_FN_LCDD4, NULL);
341 gpio_request(GPIO_FN_LCDD3, NULL);
342 gpio_request(GPIO_FN_LCDD2, NULL);
343 gpio_request(GPIO_FN_LCDD1, NULL);
344 gpio_request(GPIO_FN_LCDD0, NULL);
345 gpio_request(GPIO_FN_LCDDISP, NULL);
346 gpio_request(GPIO_FN_LCDHSYN, NULL);
347 gpio_request(GPIO_FN_LCDDCK, NULL);
348 gpio_request(GPIO_FN_LCDVSYN, NULL);
349 gpio_request(GPIO_FN_LCDDON, NULL);
350 gpio_request(GPIO_FN_LCDVEPWC, NULL);
351 gpio_request(GPIO_FN_LCDVCPWC, NULL);
352 gpio_request(GPIO_FN_LCDRD, NULL);
353 gpio_request(GPIO_FN_LCDLCLK, NULL);
354 ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA);
355
356 /* enable CEU0 */
357 gpio_request(GPIO_FN_VIO0_D15, NULL);
358 gpio_request(GPIO_FN_VIO0_D14, NULL);
359 gpio_request(GPIO_FN_VIO0_D13, NULL);
360 gpio_request(GPIO_FN_VIO0_D12, NULL);
361 gpio_request(GPIO_FN_VIO0_D11, NULL);
362 gpio_request(GPIO_FN_VIO0_D10, NULL);
363 gpio_request(GPIO_FN_VIO0_D9, NULL);
364 gpio_request(GPIO_FN_VIO0_D8, NULL);
365 gpio_request(GPIO_FN_VIO0_D7, NULL);
366 gpio_request(GPIO_FN_VIO0_D6, NULL);
367 gpio_request(GPIO_FN_VIO0_D5, NULL);
368 gpio_request(GPIO_FN_VIO0_D4, NULL);
369 gpio_request(GPIO_FN_VIO0_D3, NULL);
370 gpio_request(GPIO_FN_VIO0_D2, NULL);
371 gpio_request(GPIO_FN_VIO0_D1, NULL);
372 gpio_request(GPIO_FN_VIO0_D0, NULL);
373 gpio_request(GPIO_FN_VIO0_VD, NULL);
374 gpio_request(GPIO_FN_VIO0_CLK, NULL);
375 gpio_request(GPIO_FN_VIO0_FLD, NULL);
376 gpio_request(GPIO_FN_VIO0_HD, NULL);
377 platform_resource_setup_memory(&ceu0_device, "ceu", 4 << 20);
378
379 /* enable CEU1 */
380 gpio_request(GPIO_FN_VIO1_D7, NULL);
381 gpio_request(GPIO_FN_VIO1_D6, NULL);
382 gpio_request(GPIO_FN_VIO1_D5, NULL);
383 gpio_request(GPIO_FN_VIO1_D4, NULL);
384 gpio_request(GPIO_FN_VIO1_D3, NULL);
385 gpio_request(GPIO_FN_VIO1_D2, NULL);
386 gpio_request(GPIO_FN_VIO1_D1, NULL);
387 gpio_request(GPIO_FN_VIO1_D0, NULL);
388 gpio_request(GPIO_FN_VIO1_FLD, NULL);
389 gpio_request(GPIO_FN_VIO1_HD, NULL);
390 gpio_request(GPIO_FN_VIO1_VD, NULL);
391 gpio_request(GPIO_FN_VIO1_CLK, NULL);
392 platform_resource_setup_memory(&ceu1_device, "ceu", 4 << 20);
393
394 /* KEYSC */
395 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
396 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
397 gpio_request(GPIO_FN_KEYIN4, NULL);
398 gpio_request(GPIO_FN_KEYIN3, NULL);
399 gpio_request(GPIO_FN_KEYIN2, NULL);
400 gpio_request(GPIO_FN_KEYIN1, NULL);
401 gpio_request(GPIO_FN_KEYIN0, NULL);
402 gpio_request(GPIO_FN_KEYOUT3, NULL);
403 gpio_request(GPIO_FN_KEYOUT2, NULL);
404 gpio_request(GPIO_FN_KEYOUT1, NULL);
405 gpio_request(GPIO_FN_KEYOUT0, NULL);
406
407 if (sw & SW41_B) {
408 /* SVGA */
409 lcdc_info.ch[0].lcd_cfg.xres = 800;
410 lcdc_info.ch[0].lcd_cfg.yres = 600;
411 lcdc_info.ch[0].lcd_cfg.left_margin = 142;
412 lcdc_info.ch[0].lcd_cfg.right_margin = 52;
413 lcdc_info.ch[0].lcd_cfg.hsync_len = 96;
414 lcdc_info.ch[0].lcd_cfg.upper_margin = 24;
415 lcdc_info.ch[0].lcd_cfg.lower_margin = 2;
416 lcdc_info.ch[0].lcd_cfg.vsync_len = 2;
417 } else {
418 /* VGA */
419 lcdc_info.ch[0].lcd_cfg.xres = 640;
420 lcdc_info.ch[0].lcd_cfg.yres = 480;
421 lcdc_info.ch[0].lcd_cfg.left_margin = 105;
422 lcdc_info.ch[0].lcd_cfg.right_margin = 50;
423 lcdc_info.ch[0].lcd_cfg.hsync_len = 96;
424 lcdc_info.ch[0].lcd_cfg.upper_margin = 33;
425 lcdc_info.ch[0].lcd_cfg.lower_margin = 10;
426 lcdc_info.ch[0].lcd_cfg.vsync_len = 2;
427 }
428
429 if (sw & SW41_A) {
430 /* Digital monitor */
431 lcdc_info.ch[0].interface_type = RGB18;
432 lcdc_info.ch[0].flags = 0;
433 } else {
434 /* Analog monitor */
435 lcdc_info.ch[0].interface_type = RGB24;
436 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
437 }
438
439 return platform_add_devices(ms7724se_devices,
440 ARRAY_SIZE(ms7724se_devices));
441}
442device_initcall(devices_setup);
443
444static struct sh_machine_vector mv_ms7724se __initmv = {
445 .mv_name = "ms7724se",
446 .mv_init_irq = init_se7724_IRQ,
447 .mv_nr_irqs = SE7724_FPGA_IRQ_BASE + SE7724_FPGA_IRQ_NR,
448};
diff --git a/arch/sh/boards/mach-se/7751/Makefile b/arch/sh/boards/mach-se/7751/Makefile
index dbc29f3a9de5..e6f4341bfe6e 100644
--- a/arch/sh/boards/mach-se/7751/Makefile
+++ b/arch/sh/boards/mach-se/7751/Makefile
@@ -3,5 +3,3 @@
3# 3#
4 4
5obj-y := setup.o io.o irq.o 5obj-y := setup.o io.o irq.o
6
7obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/sh/boards/mach-se/7751/io.c b/arch/sh/boards/mach-se/7751/io.c
index 6287ae570319..6e75bd4459e5 100644
--- a/arch/sh/boards/mach-se/7751/io.c
+++ b/arch/sh/boards/mach-se/7751/io.c
@@ -34,8 +34,6 @@ unsigned char sh7751se_inb(unsigned long port)
34{ 34{
35 if (PXSEG(port)) 35 if (PXSEG(port))
36 return *(volatile unsigned char *)port; 36 return *(volatile unsigned char *)port;
37 else if (is_pci_ioaddr(port))
38 return *(volatile unsigned char *)pci_ioaddr(port);
39 else 37 else
40 return (*port2adr(port)) & 0xff; 38 return (*port2adr(port)) & 0xff;
41} 39}
@@ -46,8 +44,6 @@ unsigned char sh7751se_inb_p(unsigned long port)
46 44
47 if (PXSEG(port)) 45 if (PXSEG(port))
48 v = *(volatile unsigned char *)port; 46 v = *(volatile unsigned char *)port;
49 else if (is_pci_ioaddr(port))
50 v = *(volatile unsigned char *)pci_ioaddr(port);
51 else 47 else
52 v = (*port2adr(port)) & 0xff; 48 v = (*port2adr(port)) & 0xff;
53 ctrl_delay(); 49 ctrl_delay();
@@ -58,8 +54,6 @@ unsigned short sh7751se_inw(unsigned long port)
58{ 54{
59 if (PXSEG(port)) 55 if (PXSEG(port))
60 return *(volatile unsigned short *)port; 56 return *(volatile unsigned short *)port;
61 else if (is_pci_ioaddr(port))
62 return *(volatile unsigned short *)pci_ioaddr(port);
63 else if (port >= 0x2000) 57 else if (port >= 0x2000)
64 return *port2adr(port); 58 return *port2adr(port);
65 else 59 else
@@ -71,8 +65,6 @@ unsigned int sh7751se_inl(unsigned long port)
71{ 65{
72 if (PXSEG(port)) 66 if (PXSEG(port))
73 return *(volatile unsigned long *)port; 67 return *(volatile unsigned long *)port;
74 else if (is_pci_ioaddr(port))
75 return *(volatile unsigned int *)pci_ioaddr(port);
76 else if (port >= 0x2000) 68 else if (port >= 0x2000)
77 return *port2adr(port); 69 return *port2adr(port);
78 else 70 else
@@ -85,8 +77,6 @@ void sh7751se_outb(unsigned char value, unsigned long port)
85 77
86 if (PXSEG(port)) 78 if (PXSEG(port))
87 *(volatile unsigned char *)port = value; 79 *(volatile unsigned char *)port = value;
88 else if (is_pci_ioaddr(port))
89 *((unsigned char*)pci_ioaddr(port)) = value;
90 else 80 else
91 *(port2adr(port)) = value; 81 *(port2adr(port)) = value;
92} 82}
@@ -95,8 +85,6 @@ void sh7751se_outb_p(unsigned char value, unsigned long port)
95{ 85{
96 if (PXSEG(port)) 86 if (PXSEG(port))
97 *(volatile unsigned char *)port = value; 87 *(volatile unsigned char *)port = value;
98 else if (is_pci_ioaddr(port))
99 *((unsigned char*)pci_ioaddr(port)) = value;
100 else 88 else
101 *(port2adr(port)) = value; 89 *(port2adr(port)) = value;
102 ctrl_delay(); 90 ctrl_delay();
@@ -106,8 +94,6 @@ void sh7751se_outw(unsigned short value, unsigned long port)
106{ 94{
107 if (PXSEG(port)) 95 if (PXSEG(port))
108 *(volatile unsigned short *)port = value; 96 *(volatile unsigned short *)port = value;
109 else if (is_pci_ioaddr(port))
110 *((unsigned short *)pci_ioaddr(port)) = value;
111 else if (port >= 0x2000) 97 else if (port >= 0x2000)
112 *port2adr(port) = value; 98 *port2adr(port) = value;
113 else 99 else
@@ -118,8 +104,6 @@ void sh7751se_outl(unsigned int value, unsigned long port)
118{ 104{
119 if (PXSEG(port)) 105 if (PXSEG(port))
120 *(volatile unsigned long *)port = value; 106 *(volatile unsigned long *)port = value;
121 else if (is_pci_ioaddr(port))
122 *((unsigned long*)pci_ioaddr(port)) = value;
123 else 107 else
124 maybebadio(port); 108 maybebadio(port);
125} 109}
diff --git a/arch/sh/boards/mach-se/7751/pci.c b/arch/sh/boards/mach-se/7751/pci.c
deleted file mode 100644
index 203b2923fe7f..000000000000
--- a/arch/sh/boards/mach-se/7751/pci.c
+++ /dev/null
@@ -1,147 +0,0 @@
1/*
2 * linux/arch/sh/boards/se/7751/pci.c
3 *
4 * Author: Ian DaSilva (idasilva@mvista.com)
5 *
6 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 *
11 * PCI initialization for the Hitachi SH7751 Solution Engine board (MS7751SE01)
12 */
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pci.h>
19
20#include <asm/io.h>
21#include "../../../drivers/pci/pci-sh7751.h"
22
23#define PCIMCR_MRSET_OFF 0xBFFFFFFF
24#define PCIMCR_RFSH_OFF 0xFFFFFFFB
25
26/*
27 * Only long word accesses of the PCIC's internal local registers and the
28 * configuration registers from the CPU is supported.
29 */
30#define PCIC_WRITE(x,v) writel((v), PCI_REG(x))
31#define PCIC_READ(x) readl(PCI_REG(x))
32
33/*
34 * Description: This function sets up and initializes the pcic, sets
35 * up the BARS, maps the DRAM into the address space etc, etc.
36 */
37int __init pcibios_init_platform(void)
38{
39 unsigned long bcr1, wcr1, wcr2, wcr3, mcr;
40 unsigned short bcr2;
41
42 /*
43 * Initialize the slave bus controller on the pcic. The values used
44 * here should not be hardcoded, but they should be taken from the bsc
45 * on the processor, to make this function as generic as possible.
46 * (i.e. Another sbc may usr different SDRAM timing settings -- in order
47 * for the pcic to work, its settings need to be exactly the same.)
48 */
49 bcr1 = (*(volatile unsigned long*)(SH7751_BCR1));
50 bcr2 = (*(volatile unsigned short*)(SH7751_BCR2));
51 wcr1 = (*(volatile unsigned long*)(SH7751_WCR1));
52 wcr2 = (*(volatile unsigned long*)(SH7751_WCR2));
53 wcr3 = (*(volatile unsigned long*)(SH7751_WCR3));
54 mcr = (*(volatile unsigned long*)(SH7751_MCR));
55
56 bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */
57 (*(volatile unsigned long*)(SH7751_BCR1)) = bcr1;
58
59 bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
60 PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */
61 PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */
62 PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */
63 PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */
64 PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */
65 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
66 PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */
67
68
69 /* Enable all interrupts, so we know what to fix */
70 PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);
71 PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);
72
73 /* Set up standard PCI config registers */
74 PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */
75 PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */
76 PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */
77 PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */
78 PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */
79 PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */
80 PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */
81 PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */
82 PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */
83 PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */
84
85 /* Now turn it on... */
86 PCIC_WRITE(SH7751_PCICR, 0xa5000001);
87
88 /*
89 * Set PCIMBR and PCIIOBR here, assuming a single window
90 * (16M MEM, 256K IO) is enough. If a larger space is
91 * needed, the readx/writex and inx/outx functions will
92 * have to do more (e.g. setting registers for each call).
93 */
94
95 /*
96 * Set the MBR so PCI address is one-to-one with window,
97 * meaning all calls go straight through... use BUG_ON to
98 * catch erroneous assumption.
99 */
100 BUG_ON(PCIBIOS_MIN_MEM != SH7751_PCI_MEMORY_BASE);
101
102 PCIC_WRITE(SH7751_PCIMBR, PCIBIOS_MIN_MEM);
103
104 /* Set IOBR for window containing area specified in pci.h */
105 PCIC_WRITE(SH7751_PCIIOBR, (PCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK));
106
107 /* All done, may as well say so... */
108 printk("SH7751 PCI: Finished initialization of the PCI controller\n");
109
110 return 1;
111}
112
113int __init pcibios_map_platform_irq(u8 slot, u8 pin)
114{
115 switch (slot) {
116 case 0: return 13;
117 case 1: return 13; /* AMD Ethernet controller */
118 case 2: return -1;
119 case 3: return -1;
120 case 4: return -1;
121 default:
122 printk("PCI: Bad IRQ mapping request for slot %d\n", slot);
123 return -1;
124 }
125}
126
127static struct resource sh7751_io_resource = {
128 .name = "SH7751 IO",
129 .start = SH7751_PCI_IO_BASE,
130 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
131 .flags = IORESOURCE_IO
132};
133
134static struct resource sh7751_mem_resource = {
135 .name = "SH7751 mem",
136 .start = SH7751_PCI_MEMORY_BASE,
137 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
138 .flags = IORESOURCE_MEM
139};
140
141extern struct pci_ops sh7751_pci_ops;
142
143struct pci_channel board_pci_channels[] = {
144 { &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
145 { NULL, NULL, NULL, 0, 0 },
146};
147
diff --git a/arch/sh/boards/mach-se/7780/irq.c b/arch/sh/boards/mach-se/7780/irq.c
index 66ad292c9fc3..b8d43b638fcf 100644
--- a/arch/sh/boards/mach-se/7780/irq.c
+++ b/arch/sh/boards/mach-se/7780/irq.c
@@ -12,10 +12,13 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <asm/irq.h> 15#include <linux/irq.h>
16#include <asm/io.h> 16#include <linux/io.h>
17#include <mach-se/mach/se7780.h> 17#include <mach-se/mach/se7780.h>
18 18
19#define INTC_BASE 0xffd00000
20#define INTC_ICR1 (INTC_BASE+0x1c)
21
19/* 22/*
20 * Initialize IRQ setting 23 * Initialize IRQ setting
21 */ 24 */
@@ -43,4 +46,24 @@ void __init init_se7780_IRQ(void)
43 ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3); 46 ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
44 47
45 plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */ 48 plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */
49
50 /* ICR1: detect low level(for 2ndcut) */
51 ctrl_outl(0xAAAA0000, INTC_ICR1);
52
53 /*
54 * FPGA PCISEL register initialize
55 *
56 * CPU || SLOT1 | SLOT2 | S-ATA | USB
57 * -------------------------------------
58 * INTA || INTA | INTD | -- | INTB
59 * -------------------------------------
60 * INTB || INTB | INTA | -- | INTC
61 * -------------------------------------
62 * INTC || INTC | INTB | INTA | --
63 * -------------------------------------
64 * INTD || INTD | INTC | -- | INTA
65 * -------------------------------------
66 */
67 ctrl_outw(0x0013, FPGA_PCI_INTSEL1);
68 ctrl_outw(0xE402, FPGA_PCI_INTSEL2);
46} 69}
diff --git a/arch/sh/boards/mach-se/Makefile b/arch/sh/boards/mach-se/Makefile
index 2de42bae4b4f..b537e238c6bc 100644
--- a/arch/sh/boards/mach-se/Makefile
+++ b/arch/sh/boards/mach-se/Makefile
@@ -7,3 +7,4 @@ obj-$(CONFIG_SH_7751_SOLUTION_ENGINE) += 7751/
7obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += 7780/ 7obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += 7780/
8obj-$(CONFIG_SH_7343_SOLUTION_ENGINE) += 7343/ 8obj-$(CONFIG_SH_7343_SOLUTION_ENGINE) += 7343/
9obj-$(CONFIG_SH_7721_SOLUTION_ENGINE) += 7721/ 9obj-$(CONFIG_SH_7721_SOLUTION_ENGINE) += 7721/
10obj-$(CONFIG_SH_7724_SOLUTION_ENGINE) += 7724/
diff --git a/arch/sh/boards/mach-sh03/rtc.c b/arch/sh/boards/mach-sh03/rtc.c
index 0a9266bb51c5..a8b9f844ab5b 100644
--- a/arch/sh/boards/mach-sh03/rtc.c
+++ b/arch/sh/boards/mach-sh03/rtc.c
@@ -35,13 +35,13 @@
35#define RTC_BUSY 1 35#define RTC_BUSY 1
36#define RTC_STOP 2 36#define RTC_STOP 2
37 37
38extern spinlock_t rtc_lock; 38static DEFINE_SPINLOCK(sh03_rtc_lock);
39 39
40unsigned long get_cmos_time(void) 40unsigned long get_cmos_time(void)
41{ 41{
42 unsigned int year, mon, day, hour, min, sec; 42 unsigned int year, mon, day, hour, min, sec;
43 43
44 spin_lock(&rtc_lock); 44 spin_lock(&sh03_rtc_lock);
45 again: 45 again:
46 do { 46 do {
47 sec = (ctrl_inb(RTC_SEC1) & 0xf) + (ctrl_inb(RTC_SEC10) & 0x7) * 10; 47 sec = (ctrl_inb(RTC_SEC1) & 0xf) + (ctrl_inb(RTC_SEC10) & 0x7) * 10;
@@ -73,7 +73,7 @@ unsigned long get_cmos_time(void)
73 goto again; 73 goto again;
74 } 74 }
75 75
76 spin_unlock(&rtc_lock); 76 spin_unlock(&sh03_rtc_lock);
77 return mktime(year, mon, day, hour, min, sec); 77 return mktime(year, mon, day, hour, min, sec);
78} 78}
79 79
@@ -91,7 +91,7 @@ static int set_rtc_mmss(unsigned long nowtime)
91 int i; 91 int i;
92 92
93 /* gets recalled with irq locally disabled */ 93 /* gets recalled with irq locally disabled */
94 spin_lock(&rtc_lock); 94 spin_lock(&sh03_rtc_lock);
95 for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */ 95 for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */
96 if (!(ctrl_inb(RTC_CTL) & RTC_BUSY)) 96 if (!(ctrl_inb(RTC_CTL) & RTC_BUSY))
97 break; 97 break;
@@ -113,7 +113,7 @@ static int set_rtc_mmss(unsigned long nowtime)
113 cmos_minutes, real_minutes); 113 cmos_minutes, real_minutes);
114 retval = -1; 114 retval = -1;
115 } 115 }
116 spin_unlock(&rtc_lock); 116 spin_unlock(&sh03_rtc_lock);
117 117
118 return retval; 118 return retval;
119} 119}
diff --git a/arch/sh/boards/mach-snapgear/io.c b/arch/sh/boards/mach-snapgear/io.c
index 0f4824264557..476650e42dbc 100644
--- a/arch/sh/boards/mach-snapgear/io.c
+++ b/arch/sh/boards/mach-snapgear/io.c
@@ -36,8 +36,6 @@ unsigned char snapgear_inb(unsigned long port)
36{ 36{
37 if (PXSEG(port)) 37 if (PXSEG(port))
38 return *(volatile unsigned char *)port; 38 return *(volatile unsigned char *)port;
39 else if (is_pci_ioaddr(port))
40 return *(volatile unsigned char *)pci_ioaddr(port);
41 else 39 else
42 return (*port2adr(port)) & 0xff; 40 return (*port2adr(port)) & 0xff;
43} 41}
@@ -48,8 +46,6 @@ unsigned char snapgear_inb_p(unsigned long port)
48 46
49 if (PXSEG(port)) 47 if (PXSEG(port))
50 v = *(volatile unsigned char *)port; 48 v = *(volatile unsigned char *)port;
51 else if (is_pci_ioaddr(port))
52 v = *(volatile unsigned char *)pci_ioaddr(port);
53 else 49 else
54 v = (*port2adr(port))&0xff; 50 v = (*port2adr(port))&0xff;
55 ctrl_delay(); 51 ctrl_delay();
@@ -60,8 +56,6 @@ unsigned short snapgear_inw(unsigned long port)
60{ 56{
61 if (PXSEG(port)) 57 if (PXSEG(port))
62 return *(volatile unsigned short *)port; 58 return *(volatile unsigned short *)port;
63 else if (is_pci_ioaddr(port))
64 return *(volatile unsigned short *)pci_ioaddr(port);
65 else if (port >= 0x2000) 59 else if (port >= 0x2000)
66 return *port2adr(port); 60 return *port2adr(port);
67 else 61 else
@@ -73,8 +67,6 @@ unsigned int snapgear_inl(unsigned long port)
73{ 67{
74 if (PXSEG(port)) 68 if (PXSEG(port))
75 return *(volatile unsigned long *)port; 69 return *(volatile unsigned long *)port;
76 else if (is_pci_ioaddr(port))
77 return *(volatile unsigned int *)pci_ioaddr(port);
78 else if (port >= 0x2000) 70 else if (port >= 0x2000)
79 return *port2adr(port); 71 return *port2adr(port);
80 else 72 else
@@ -87,8 +79,6 @@ void snapgear_outb(unsigned char value, unsigned long port)
87 79
88 if (PXSEG(port)) 80 if (PXSEG(port))
89 *(volatile unsigned char *)port = value; 81 *(volatile unsigned char *)port = value;
90 else if (is_pci_ioaddr(port))
91 *((unsigned char*)pci_ioaddr(port)) = value;
92 else 82 else
93 *(port2adr(port)) = value; 83 *(port2adr(port)) = value;
94} 84}
@@ -97,8 +87,6 @@ void snapgear_outb_p(unsigned char value, unsigned long port)
97{ 87{
98 if (PXSEG(port)) 88 if (PXSEG(port))
99 *(volatile unsigned char *)port = value; 89 *(volatile unsigned char *)port = value;
100 else if (is_pci_ioaddr(port))
101 *((unsigned char*)pci_ioaddr(port)) = value;
102 else 90 else
103 *(port2adr(port)) = value; 91 *(port2adr(port)) = value;
104 ctrl_delay(); 92 ctrl_delay();
@@ -108,8 +96,6 @@ void snapgear_outw(unsigned short value, unsigned long port)
108{ 96{
109 if (PXSEG(port)) 97 if (PXSEG(port))
110 *(volatile unsigned short *)port = value; 98 *(volatile unsigned short *)port = value;
111 else if (is_pci_ioaddr(port))
112 *((unsigned short *)pci_ioaddr(port)) = value;
113 else if (port >= 0x2000) 99 else if (port >= 0x2000)
114 *port2adr(port) = value; 100 *port2adr(port) = value;
115 else 101 else
@@ -120,8 +106,6 @@ void snapgear_outl(unsigned int value, unsigned long port)
120{ 106{
121 if (PXSEG(port)) 107 if (PXSEG(port))
122 *(volatile unsigned long *)port = value; 108 *(volatile unsigned long *)port = value;
123 else if (is_pci_ioaddr(port))
124 *((unsigned long*)pci_ioaddr(port)) = value;
125 else 109 else
126 maybebadio(port); 110 maybebadio(port);
127} 111}
diff --git a/arch/sh/boards/mach-systemh/io.c b/arch/sh/boards/mach-systemh/io.c
index dec3db0ee933..15577ff1f715 100644
--- a/arch/sh/boards/mach-systemh/io.c
+++ b/arch/sh/boards/mach-systemh/io.c
@@ -35,8 +35,6 @@ unsigned char sh7751systemh_inb(unsigned long port)
35{ 35{
36 if (PXSEG(port)) 36 if (PXSEG(port))
37 return *(volatile unsigned char *)port; 37 return *(volatile unsigned char *)port;
38 else if (is_pci_ioaddr(port))
39 return *(volatile unsigned char *)pci_ioaddr(port);
40 else if (port <= 0x3F1) 38 else if (port <= 0x3F1)
41 return *(volatile unsigned char *)ETHER_IOMAP(port); 39 return *(volatile unsigned char *)ETHER_IOMAP(port);
42 else 40 else
@@ -49,8 +47,6 @@ unsigned char sh7751systemh_inb_p(unsigned long port)
49 47
50 if (PXSEG(port)) 48 if (PXSEG(port))
51 v = *(volatile unsigned char *)port; 49 v = *(volatile unsigned char *)port;
52 else if (is_pci_ioaddr(port))
53 v = *(volatile unsigned char *)pci_ioaddr(port);
54 else if (port <= 0x3F1) 50 else if (port <= 0x3F1)
55 v = *(volatile unsigned char *)ETHER_IOMAP(port); 51 v = *(volatile unsigned char *)ETHER_IOMAP(port);
56 else 52 else
@@ -63,8 +59,6 @@ unsigned short sh7751systemh_inw(unsigned long port)
63{ 59{
64 if (PXSEG(port)) 60 if (PXSEG(port))
65 return *(volatile unsigned short *)port; 61 return *(volatile unsigned short *)port;
66 else if (is_pci_ioaddr(port))
67 return *(volatile unsigned short *)pci_ioaddr(port);
68 else if (port >= 0x2000) 62 else if (port >= 0x2000)
69 return *port2adr(port); 63 return *port2adr(port);
70 else if (port <= 0x3F1) 64 else if (port <= 0x3F1)
@@ -78,8 +72,6 @@ unsigned int sh7751systemh_inl(unsigned long port)
78{ 72{
79 if (PXSEG(port)) 73 if (PXSEG(port))
80 return *(volatile unsigned long *)port; 74 return *(volatile unsigned long *)port;
81 else if (is_pci_ioaddr(port))
82 return *(volatile unsigned int *)pci_ioaddr(port);
83 else if (port >= 0x2000) 75 else if (port >= 0x2000)
84 return *port2adr(port); 76 return *port2adr(port);
85 else if (port <= 0x3F1) 77 else if (port <= 0x3F1)
@@ -94,8 +86,6 @@ void sh7751systemh_outb(unsigned char value, unsigned long port)
94 86
95 if (PXSEG(port)) 87 if (PXSEG(port))
96 *(volatile unsigned char *)port = value; 88 *(volatile unsigned char *)port = value;
97 else if (is_pci_ioaddr(port))
98 *((unsigned char*)pci_ioaddr(port)) = value;
99 else if (port <= 0x3F1) 89 else if (port <= 0x3F1)
100 *(volatile unsigned char *)ETHER_IOMAP(port) = value; 90 *(volatile unsigned char *)ETHER_IOMAP(port) = value;
101 else 91 else
@@ -106,8 +96,6 @@ void sh7751systemh_outb_p(unsigned char value, unsigned long port)
106{ 96{
107 if (PXSEG(port)) 97 if (PXSEG(port))
108 *(volatile unsigned char *)port = value; 98 *(volatile unsigned char *)port = value;
109 else if (is_pci_ioaddr(port))
110 *((unsigned char*)pci_ioaddr(port)) = value;
111 else if (port <= 0x3F1) 99 else if (port <= 0x3F1)
112 *(volatile unsigned char *)ETHER_IOMAP(port) = value; 100 *(volatile unsigned char *)ETHER_IOMAP(port) = value;
113 else 101 else
@@ -119,8 +107,6 @@ void sh7751systemh_outw(unsigned short value, unsigned long port)
119{ 107{
120 if (PXSEG(port)) 108 if (PXSEG(port))
121 *(volatile unsigned short *)port = value; 109 *(volatile unsigned short *)port = value;
122 else if (is_pci_ioaddr(port))
123 *((unsigned short *)pci_ioaddr(port)) = value;
124 else if (port >= 0x2000) 110 else if (port >= 0x2000)
125 *port2adr(port) = value; 111 *port2adr(port) = value;
126 else if (port <= 0x3F1) 112 else if (port <= 0x3F1)
@@ -133,8 +119,6 @@ void sh7751systemh_outl(unsigned int value, unsigned long port)
133{ 119{
134 if (PXSEG(port)) 120 if (PXSEG(port))
135 *(volatile unsigned long *)port = value; 121 *(volatile unsigned long *)port = value;
136 else if (is_pci_ioaddr(port))
137 *((unsigned long*)pci_ioaddr(port)) = value;
138 else 122 else
139 maybebadio(port); 123 maybebadio(port);
140} 124}
diff --git a/arch/sh/boards/mach-titan/io.c b/arch/sh/boards/mach-titan/io.c
index 4badad4c6f30..0130e9826aca 100644
--- a/arch/sh/boards/mach-titan/io.c
+++ b/arch/sh/boards/mach-titan/io.c
@@ -17,8 +17,6 @@ u8 titan_inb(unsigned long port)
17{ 17{
18 if (PXSEG(port)) 18 if (PXSEG(port))
19 return ctrl_inb(port); 19 return ctrl_inb(port);
20 else if (is_pci_ioaddr(port))
21 return ctrl_inb(pci_ioaddr(port));
22 return ctrl_inw(port2adr(port)) & 0xff; 20 return ctrl_inw(port2adr(port)) & 0xff;
23} 21}
24 22
@@ -28,8 +26,6 @@ u8 titan_inb_p(unsigned long port)
28 26
29 if (PXSEG(port)) 27 if (PXSEG(port))
30 v = ctrl_inb(port); 28 v = ctrl_inb(port);
31 else if (is_pci_ioaddr(port))
32 v = ctrl_inb(pci_ioaddr(port));
33 else 29 else
34 v = ctrl_inw(port2adr(port)) & 0xff; 30 v = ctrl_inw(port2adr(port)) & 0xff;
35 ctrl_delay(); 31 ctrl_delay();
@@ -40,8 +36,6 @@ u16 titan_inw(unsigned long port)
40{ 36{
41 if (PXSEG(port)) 37 if (PXSEG(port))
42 return ctrl_inw(port); 38 return ctrl_inw(port);
43 else if (is_pci_ioaddr(port))
44 return ctrl_inw(pci_ioaddr(port));
45 else if (port >= 0x2000) 39 else if (port >= 0x2000)
46 return ctrl_inw(port2adr(port)); 40 return ctrl_inw(port2adr(port));
47 else 41 else
@@ -53,8 +47,6 @@ u32 titan_inl(unsigned long port)
53{ 47{
54 if (PXSEG(port)) 48 if (PXSEG(port))
55 return ctrl_inl(port); 49 return ctrl_inl(port);
56 else if (is_pci_ioaddr(port))
57 return ctrl_inl(pci_ioaddr(port));
58 else if (port >= 0x2000) 50 else if (port >= 0x2000)
59 return ctrl_inw(port2adr(port)); 51 return ctrl_inw(port2adr(port));
60 else 52 else
@@ -66,8 +58,6 @@ void titan_outb(u8 value, unsigned long port)
66{ 58{
67 if (PXSEG(port)) 59 if (PXSEG(port))
68 ctrl_outb(value, port); 60 ctrl_outb(value, port);
69 else if (is_pci_ioaddr(port))
70 ctrl_outb(value, pci_ioaddr(port));
71 else 61 else
72 ctrl_outw(value, port2adr(port)); 62 ctrl_outw(value, port2adr(port));
73} 63}
@@ -76,8 +66,6 @@ void titan_outb_p(u8 value, unsigned long port)
76{ 66{
77 if (PXSEG(port)) 67 if (PXSEG(port))
78 ctrl_outb(value, port); 68 ctrl_outb(value, port);
79 else if (is_pci_ioaddr(port))
80 ctrl_outb(value, pci_ioaddr(port));
81 else 69 else
82 ctrl_outw(value, port2adr(port)); 70 ctrl_outw(value, port2adr(port));
83 ctrl_delay(); 71 ctrl_delay();
@@ -87,8 +75,6 @@ void titan_outw(u16 value, unsigned long port)
87{ 75{
88 if (PXSEG(port)) 76 if (PXSEG(port))
89 ctrl_outw(value, port); 77 ctrl_outw(value, port);
90 else if (is_pci_ioaddr(port))
91 ctrl_outw(value, pci_ioaddr(port));
92 else if (port >= 0x2000) 78 else if (port >= 0x2000)
93 ctrl_outw(value, port2adr(port)); 79 ctrl_outw(value, port2adr(port));
94 else 80 else
@@ -99,8 +85,6 @@ void titan_outl(u32 value, unsigned long port)
99{ 85{
100 if (PXSEG(port)) 86 if (PXSEG(port))
101 ctrl_outl(value, port); 87 ctrl_outl(value, port);
102 else if (is_pci_ioaddr(port))
103 ctrl_outl(value, pci_ioaddr(port));
104 else 88 else
105 maybebadio(port); 89 maybebadio(port);
106} 90}
@@ -117,10 +101,8 @@ void titan_outsl(unsigned long port, const void *src, unsigned long count)
117 101
118void __iomem *titan_ioport_map(unsigned long port, unsigned int size) 102void __iomem *titan_ioport_map(unsigned long port, unsigned int size)
119{ 103{
120 if (PXSEG(port) || is_pci_memaddr(port)) 104 if (PXSEG(port))
121 return (void __iomem *)port; 105 return (void __iomem *)port;
122 else if (is_pci_ioaddr(port))
123 return (void __iomem *)pci_ioaddr(port);
124 106
125 return (void __iomem *)port2adr(port); 107 return (void __iomem *)port2adr(port);
126} 108}
diff --git a/arch/sh/boot/Makefile b/arch/sh/boot/Makefile
index 95483d161258..78efb04c28f3 100644
--- a/arch/sh/boot/Makefile
+++ b/arch/sh/boot/Makefile
@@ -20,9 +20,6 @@ CONFIG_BOOT_LINK_OFFSET ?= 0x00800000
20CONFIG_ZERO_PAGE_OFFSET ?= 0x00001000 20CONFIG_ZERO_PAGE_OFFSET ?= 0x00001000
21CONFIG_ENTRY_OFFSET ?= 0x00001000 21CONFIG_ENTRY_OFFSET ?= 0x00001000
22 22
23export CONFIG_PAGE_OFFSET CONFIG_MEMORY_START CONFIG_BOOT_LINK_OFFSET \
24 CONFIG_ZERO_PAGE_OFFSET CONFIG_ENTRY_OFFSET
25
26targets := zImage vmlinux.srec uImage uImage.srec 23targets := zImage vmlinux.srec uImage uImage.srec
27subdir- := compressed 24subdir- := compressed
28 25
@@ -43,6 +40,9 @@ KERNEL_MEMORY := $(shell /bin/bash -c 'printf "0x%08x" \
43 $$[$(CONFIG_MEMORY_START)]') 40 $$[$(CONFIG_MEMORY_START)]')
44endif 41endif
45 42
43export CONFIG_PAGE_OFFSET CONFIG_MEMORY_START CONFIG_BOOT_LINK_OFFSET \
44 CONFIG_ZERO_PAGE_OFFSET CONFIG_ENTRY_OFFSET KERNEL_MEMORY
45
46KERNEL_LOAD := $(shell /bin/bash -c 'printf "0x%08x" \ 46KERNEL_LOAD := $(shell /bin/bash -c 'printf "0x%08x" \
47 $$[$(CONFIG_PAGE_OFFSET) + \ 47 $$[$(CONFIG_PAGE_OFFSET) + \
48 $(KERNEL_MEMORY) + \ 48 $(KERNEL_MEMORY) + \
diff --git a/arch/sh/boot/compressed/Makefile b/arch/sh/boot/compressed/Makefile
index efb01dc3c8c3..9531bf1b7c2f 100644
--- a/arch/sh/boot/compressed/Makefile
+++ b/arch/sh/boot/compressed/Makefile
@@ -1,5 +1,47 @@
1ifeq ($(CONFIG_SUPERH32),y) 1#
2include ${srctree}/arch/sh/boot/compressed/Makefile_32 2# linux/arch/sh/boot/compressed/Makefile
3else 3#
4include ${srctree}/arch/sh/boot/compressed/Makefile_64 4# create a compressed vmlinux image from the original vmlinux
5#
6
7targets := vmlinux vmlinux.bin vmlinux.bin.gz \
8 head_$(BITS).o misc_$(BITS).o piggy.o
9
10OBJECTS = $(obj)/head_$(BITS).o $(obj)/misc_$(BITS).o $(obj)/cache.o
11
12ifdef CONFIG_SH_STANDARD_BIOS
13OBJECTS += $(obj)/../../kernel/sh_bios.o
5endif 14endif
15
16#
17# IMAGE_OFFSET is the load offset of the compression loader
18#
19IMAGE_OFFSET := $(shell /bin/bash -c 'printf "0x%08x" \
20 $$[$(CONFIG_PAGE_OFFSET) + \
21 $(KERNEL_MEMORY) + \
22 $(CONFIG_BOOT_LINK_OFFSET)]')
23
24LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
25
26ifeq ($(CONFIG_FUNCTION_TRACER),y)
27ORIG_CFLAGS := $(KBUILD_CFLAGS)
28KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
29endif
30
31LDFLAGS_vmlinux := --oformat $(ld-bfd) -Ttext $(IMAGE_OFFSET) -e startup \
32 -T $(obj)/../../kernel/vmlinux.lds
33
34$(obj)/vmlinux: $(OBJECTS) $(obj)/piggy.o $(LIBGCC) FORCE
35 $(call if_changed,ld)
36 @:
37
38$(obj)/vmlinux.bin: vmlinux FORCE
39 $(call if_changed,objcopy)
40
41$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
42 $(call if_changed,gzip)
43
44OBJCOPYFLAGS += -R .empty_zero_page
45
46$(obj)/piggy.o: $(obj)/piggy.S $(obj)/vmlinux.bin.gz FORCE
47 $(call if_changed,as_o_S)
diff --git a/arch/sh/boot/compressed/Makefile_32 b/arch/sh/boot/compressed/Makefile_32
deleted file mode 100644
index b96a055b053e..000000000000
--- a/arch/sh/boot/compressed/Makefile_32
+++ /dev/null
@@ -1,46 +0,0 @@
1#
2# linux/arch/sh/boot/compressed/Makefile
3#
4# create a compressed vmlinux image from the original vmlinux
5#
6
7targets := vmlinux vmlinux.bin vmlinux.bin.gz \
8 head_32.o misc_32.o piggy.o
9
10OBJECTS = $(obj)/head_32.o $(obj)/misc_32.o
11
12ifdef CONFIG_SH_STANDARD_BIOS
13OBJECTS += $(obj)/../../kernel/sh_bios.o
14endif
15
16#
17# IMAGE_OFFSET is the load offset of the compression loader
18#
19IMAGE_OFFSET := $(shell /bin/bash -c 'printf "0x%08x" \
20 $$[$(CONFIG_PAGE_OFFSET) + \
21 $(CONFIG_MEMORY_START) + \
22 $(CONFIG_BOOT_LINK_OFFSET)]')
23
24LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
25
26ifeq ($(CONFIG_FUNCTION_TRACER),y)
27ORIG_CFLAGS := $(KBUILD_CFLAGS)
28KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
29endif
30
31LDFLAGS_vmlinux := -Ttext $(IMAGE_OFFSET) -e startup -T $(obj)/../../kernel/vmlinux.lds
32
33$(obj)/vmlinux: $(OBJECTS) $(obj)/piggy.o $(LIBGCC) FORCE
34 $(call if_changed,ld)
35 @:
36
37$(obj)/vmlinux.bin: vmlinux FORCE
38 $(call if_changed,objcopy)
39
40$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
41 $(call if_changed,gzip)
42
43OBJCOPYFLAGS += -R .empty_zero_page
44
45$(obj)/piggy.o: $(obj)/piggy.S $(obj)/vmlinux.bin.gz FORCE
46 $(call if_changed,as_o_S)
diff --git a/arch/sh/boot/compressed/Makefile_64 b/arch/sh/boot/compressed/Makefile_64
deleted file mode 100644
index 658d4f915556..000000000000
--- a/arch/sh/boot/compressed/Makefile_64
+++ /dev/null
@@ -1,43 +0,0 @@
1#
2# arch/sh/boot/compressed/Makefile_64
3#
4# create a compressed vmlinux image from the original vmlinux
5#
6# Copyright (C) 2002 Stuart Menefy
7# Copyright (C) 2004 Paul Mundt
8#
9# This file is subject to the terms and conditions of the GNU General Public
10# License. See the file "COPYING" in the main directory of this archive
11# for more details.
12#
13
14targets := vmlinux vmlinux.bin vmlinux.bin.gz \
15 head_64.o misc_64.o cache.o piggy.o
16
17OBJECTS := $(obj)/vmlinux_64.lds $(obj)/head_64.o $(obj)/misc_64.o \
18 $(obj)/cache.o
19
20#
21# ZIMAGE_OFFSET is the load offset of the compression loader
22# (4M for the kernel plus 64K for this loader)
23#
24ZIMAGE_OFFSET := $(shell /bin/bash -c 'printf "0x%08x" \
25 $$[$(CONFIG_PAGE_OFFSET)+0x400000+0x10000]')
26
27LDFLAGS_vmlinux := -Ttext $(ZIMAGE_OFFSET) -e startup \
28 -T $(obj)/../../kernel/vmlinux.lds
29
30$(obj)/vmlinux: $(OBJECTS) $(obj)/piggy.o FORCE
31 $(call if_changed,ld)
32 @:
33
34$(obj)/vmlinux.bin: vmlinux FORCE
35 $(call if_changed,objcopy)
36
37$(obj)/vmlinux.bin.gz: $(obj)/vmlinux.bin FORCE
38 $(call if_changed,gzip)
39
40OBJCOPYFLAGS += -R .empty_zero_page
41
42$(obj)/piggy.o: $(obj)/piggy.S $(obj)/vmlinux.bin.gz FORCE
43 $(call if_changed,as_o_S)
diff --git a/arch/sh/boot/compressed/head_64.S b/arch/sh/boot/compressed/head_64.S
index 622eac3cf556..9993113c6713 100644
--- a/arch/sh/boot/compressed/head_64.S
+++ b/arch/sh/boot/compressed/head_64.S
@@ -14,6 +14,7 @@
14 * Copyright (C) 2002 Stuart Menefy (stuart.menefy@st.com) 14 * Copyright (C) 2002 Stuart Menefy (stuart.menefy@st.com)
15 */ 15 */
16#include <asm/cache.h> 16#include <asm/cache.h>
17#include <asm/tlb.h>
17#include <cpu/mmu_context.h> 18#include <cpu/mmu_context.h>
18#include <cpu/registers.h> 19#include <cpu/registers.h>
19 20
@@ -33,11 +34,7 @@
33#define ICCR0_INIT_VAL ICCR0_ON | ICCR0_ICI /* ICE + ICI */ 34#define ICCR0_INIT_VAL ICCR0_ON | ICCR0_ICI /* ICE + ICI */
34#define ICCR1_INIT_VAL ICCR1_NOLOCK /* No locking */ 35#define ICCR1_INIT_VAL ICCR1_NOLOCK /* No locking */
35 36
36#if 1
37#define OCCR0_INIT_VAL OCCR0_ON | OCCR0_OCI | OCCR0_WB /* OCE + OCI + WB */ 37#define OCCR0_INIT_VAL OCCR0_ON | OCCR0_OCI | OCCR0_WB /* OCE + OCI + WB */
38#else
39#define OCCR0_INIT_VAL OCCR0_OFF
40#endif
41#define OCCR1_INIT_VAL OCCR1_NOLOCK /* No locking */ 38#define OCCR1_INIT_VAL OCCR1_NOLOCK /* No locking */
42 39
43 .text 40 .text
diff --git a/arch/sh/boot/compressed/vmlinux_64.lds b/arch/sh/boot/compressed/vmlinux_64.lds
deleted file mode 100644
index 59c2ef4aeda5..000000000000
--- a/arch/sh/boot/compressed/vmlinux_64.lds
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * ld script to make compressed SuperH/shmedia Linux kernel+decompression
3 * bootstrap
4 * Modified by Stuart Menefy from arch/sh/vmlinux.lds.S written by Niibe Yutaka
5 */
6
7
8#ifdef CONFIG_LITTLE_ENDIAN
9/* OUTPUT_FORMAT("elf32-sh64l-linux", "elf32-sh64l-linux", "elf32-sh64l-linux") */
10#define NOP 0x6ff0fff0
11#else
12/* OUTPUT_FORMAT("elf32-sh64", "elf32-sh64", "elf32-sh64") */
13#define NOP 0xf0fff06f
14#endif
15
16OUTPUT_FORMAT("elf32-sh64-linux")
17OUTPUT_ARCH(sh)
18ENTRY(_start)
19
20#define ALIGNED_GAP(section, align) (((ADDR(section)+SIZEOF(section)+(align)-1) & ~((align)-1))-ADDR(section))
21#define FOLLOWING(section, align) AT (LOADADDR(section) + ALIGNED_GAP(section,align))
22
23SECTIONS
24{
25 _text = .; /* Text and read-only data */
26
27 .text : {
28 *(.text)
29 *(.text64)
30 *(.text..SHmedia32)
31 *(.fixup)
32 *(.gnu.warning)
33 } = NOP
34 . = ALIGN(4);
35 .rodata : { *(.rodata) }
36
37 /* There is no 'real' reason for eight byte alignment, four would work
38 * as well, but gdb downloads much (*4) faster with this.
39 */
40 . = ALIGN(8);
41 .image : { *(.image) }
42 . = ALIGN(4);
43 _etext = .; /* End of text section */
44
45 .data : /* Data */
46 FOLLOWING(.image, 4)
47 {
48 _data = .;
49 *(.data)
50 }
51 _data_image = LOADADDR(.data);/* Address of data section in ROM */
52
53 _edata = .; /* End of data section */
54
55 .stack : { stack = .; _stack = .; }
56
57 . = ALIGN(4);
58 __bss_start = .; /* BSS */
59 .bss : {
60 *(.bss)
61 }
62 . = ALIGN(4);
63 _end = . ;
64}
diff --git a/arch/sh/cchips/Kconfig b/arch/sh/cchips/Kconfig
index f43d18373f22..a5ab2eccdaa6 100644
--- a/arch/sh/cchips/Kconfig
+++ b/arch/sh/cchips/Kconfig
@@ -34,11 +34,6 @@ config HD64461_IRQ
34 34
35 Do not change this unless you know what you are doing. 35 Do not change this unless you know what you are doing.
36 36
37config HD64461_IOBASE
38 hex "HD64461 start address"
39 depends on HD64461
40 default "0xb0000000"
41
42config HD64461_ENABLER 37config HD64461_ENABLER
43 bool "HD64461 PCMCIA enabler" 38 bool "HD64461 PCMCIA enabler"
44 depends on HD64461 39 depends on HD64461
diff --git a/arch/sh/cchips/hd6446x/hd64461.c b/arch/sh/cchips/hd6446x/hd64461.c
index 25ef91061521..50aa0c1f76ea 100644
--- a/arch/sh/cchips/hd6446x/hd64461.c
+++ b/arch/sh/cchips/hd6446x/hd64461.c
@@ -80,7 +80,7 @@ int __init setup_hd64461(void)
80 80
81 printk(KERN_INFO 81 printk(KERN_INFO
82 "HD64461 configured at 0x%x on irq %d(mapped into %d to %d)\n", 82 "HD64461 configured at 0x%x on irq %d(mapped into %d to %d)\n",
83 CONFIG_HD64461_IOBASE, CONFIG_HD64461_IRQ, HD64461_IRQBASE, 83 HD64461_IOBASE, CONFIG_HD64461_IRQ, HD64461_IRQBASE,
84 HD64461_IRQBASE + 15); 84 HD64461_IRQBASE + 15);
85 85
86/* Should be at processor specific part.. */ 86/* Should be at processor specific part.. */
diff --git a/arch/sh/configs/ap325rxa_defconfig b/arch/sh/configs/ap325rxa_defconfig
index c8d982a8a2e6..022f70e0ea03 100644
--- a/arch/sh/configs/ap325rxa_defconfig
+++ b/arch/sh/configs/ap325rxa_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 17:46:53 2009 4# Mon Apr 27 12:42:06 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -74,6 +75,7 @@ CONFIG_EMBEDDED=y
74CONFIG_UID16=y 75CONFIG_UID16=y
75CONFIG_SYSCTL_SYSCALL=y 76CONFIG_SYSCTL_SYSCALL=y
76# CONFIG_KALLSYMS is not set 77# CONFIG_KALLSYMS is not set
78# CONFIG_STRIP_ASM_SYMS is not set
77CONFIG_HOTPLUG=y 79CONFIG_HOTPLUG=y
78CONFIG_PRINTK=y 80CONFIG_PRINTK=y
79CONFIG_BUG=y 81CONFIG_BUG=y
@@ -92,12 +94,15 @@ CONFIG_SLAB=y
92# CONFIG_SLUB is not set 94# CONFIG_SLUB is not set
93# CONFIG_SLOB is not set 95# CONFIG_SLOB is not set
94# CONFIG_PROFILING is not set 96# CONFIG_PROFILING is not set
97# CONFIG_MARKERS is not set
95CONFIG_HAVE_OPROFILE=y 98CONFIG_HAVE_OPROFILE=y
96CONFIG_HAVE_IOREMAP_PROT=y 99CONFIG_HAVE_IOREMAP_PROT=y
97CONFIG_HAVE_KPROBES=y 100CONFIG_HAVE_KPROBES=y
98CONFIG_HAVE_KRETPROBES=y 101CONFIG_HAVE_KRETPROBES=y
99CONFIG_HAVE_ARCH_TRACEHOOK=y 102CONFIG_HAVE_ARCH_TRACEHOOK=y
100CONFIG_HAVE_CLK=y 103CONFIG_HAVE_CLK=y
104CONFIG_HAVE_DMA_API_DEBUG=y
105# CONFIG_SLOW_WORK is not set
101CONFIG_HAVE_GENERIC_DMA_COHERENT=y 106CONFIG_HAVE_GENERIC_DMA_COHERENT=y
102CONFIG_SLABINFO=y 107CONFIG_SLABINFO=y
103CONFIG_RT_MUTEXES=y 108CONFIG_RT_MUTEXES=y
@@ -110,7 +115,6 @@ CONFIG_MODULE_UNLOAD=y
110# CONFIG_MODULE_SRCVERSION_ALL is not set 115# CONFIG_MODULE_SRCVERSION_ALL is not set
111CONFIG_BLOCK=y 116CONFIG_BLOCK=y
112# CONFIG_LBD is not set 117# CONFIG_LBD is not set
113# CONFIG_BLK_DEV_IO_TRACE is not set
114# CONFIG_BLK_DEV_BSG is not set 118# CONFIG_BLK_DEV_BSG is not set
115# CONFIG_BLK_DEV_INTEGRITY is not set 119# CONFIG_BLK_DEV_INTEGRITY is not set
116 120
@@ -159,6 +163,7 @@ CONFIG_ARCH_SHMOBILE=y
159# CONFIG_CPU_SUBTYPE_SH7760 is not set 163# CONFIG_CPU_SUBTYPE_SH7760 is not set
160# CONFIG_CPU_SUBTYPE_SH4_202 is not set 164# CONFIG_CPU_SUBTYPE_SH4_202 is not set
161CONFIG_CPU_SUBTYPE_SH7723=y 165CONFIG_CPU_SUBTYPE_SH7723=y
166# CONFIG_CPU_SUBTYPE_SH7724 is not set
162# CONFIG_CPU_SUBTYPE_SH7763 is not set 167# CONFIG_CPU_SUBTYPE_SH7763 is not set
163# CONFIG_CPU_SUBTYPE_SH7770 is not set 168# CONFIG_CPU_SUBTYPE_SH7770 is not set
164# CONFIG_CPU_SUBTYPE_SH7780 is not set 169# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -168,8 +173,6 @@ CONFIG_CPU_SUBTYPE_SH7723=y
168# CONFIG_CPU_SUBTYPE_SH7343 is not set 173# CONFIG_CPU_SUBTYPE_SH7343 is not set
169# CONFIG_CPU_SUBTYPE_SH7722 is not set 174# CONFIG_CPU_SUBTYPE_SH7722 is not set
170# CONFIG_CPU_SUBTYPE_SH7366 is not set 175# CONFIG_CPU_SUBTYPE_SH7366 is not set
171# CONFIG_CPU_SUBTYPE_SH5_101 is not set
172# CONFIG_CPU_SUBTYPE_SH5_103 is not set
173 176
174# 177#
175# Memory management options 178# Memory management options
@@ -573,6 +576,7 @@ CONFIG_SCSI_WAIT_SCAN=m
573CONFIG_SCSI_LOWLEVEL=y 576CONFIG_SCSI_LOWLEVEL=y
574# CONFIG_ISCSI_TCP is not set 577# CONFIG_ISCSI_TCP is not set
575# CONFIG_LIBFC is not set 578# CONFIG_LIBFC is not set
579# CONFIG_LIBFCOE is not set
576# CONFIG_SCSI_DEBUG is not set 580# CONFIG_SCSI_DEBUG is not set
577# CONFIG_SCSI_DH is not set 581# CONFIG_SCSI_DH is not set
578# CONFIG_SCSI_OSD_INITIATOR is not set 582# CONFIG_SCSI_OSD_INITIATOR is not set
@@ -695,6 +699,7 @@ CONFIG_DEVKMEM=y
695# 699#
696# Non-8250 serial port support 700# Non-8250 serial port support
697# 701#
702# CONFIG_SERIAL_MAX3100 is not set
698CONFIG_SERIAL_SH_SCI=y 703CONFIG_SERIAL_SH_SCI=y
699CONFIG_SERIAL_SH_SCI_NR_UARTS=6 704CONFIG_SERIAL_SH_SCI_NR_UARTS=6
700CONFIG_SERIAL_SH_SCI_CONSOLE=y 705CONFIG_SERIAL_SH_SCI_CONSOLE=y
@@ -1030,6 +1035,7 @@ CONFIG_EXT2_FS_POSIX_ACL=y
1030CONFIG_EXT2_FS_SECURITY=y 1035CONFIG_EXT2_FS_SECURITY=y
1031# CONFIG_EXT2_FS_XIP is not set 1036# CONFIG_EXT2_FS_XIP is not set
1032CONFIG_EXT3_FS=y 1037CONFIG_EXT3_FS=y
1038# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1033CONFIG_EXT3_FS_XATTR=y 1039CONFIG_EXT3_FS_XATTR=y
1034CONFIG_EXT3_FS_POSIX_ACL=y 1040CONFIG_EXT3_FS_POSIX_ACL=y
1035CONFIG_EXT3_FS_SECURITY=y 1041CONFIG_EXT3_FS_SECURITY=y
@@ -1052,6 +1058,11 @@ CONFIG_INOTIFY_USER=y
1052# CONFIG_FUSE_FS is not set 1058# CONFIG_FUSE_FS is not set
1053 1059
1054# 1060#
1061# Caches
1062#
1063# CONFIG_FSCACHE is not set
1064
1065#
1055# CD-ROM/DVD Filesystems 1066# CD-ROM/DVD Filesystems
1056# 1067#
1057# CONFIG_ISO9660_FS is not set 1068# CONFIG_ISO9660_FS is not set
@@ -1100,6 +1111,7 @@ CONFIG_MISC_FILESYSTEMS=y
1100# CONFIG_ROMFS_FS is not set 1111# CONFIG_ROMFS_FS is not set
1101# CONFIG_SYSV_FS is not set 1112# CONFIG_SYSV_FS is not set
1102# CONFIG_UFS_FS is not set 1113# CONFIG_UFS_FS is not set
1114# CONFIG_NILFS2_FS is not set
1103CONFIG_NETWORK_FILESYSTEMS=y 1115CONFIG_NETWORK_FILESYSTEMS=y
1104CONFIG_NFS_FS=y 1116CONFIG_NFS_FS=y
1105CONFIG_NFS_V3=y 1117CONFIG_NFS_V3=y
@@ -1191,10 +1203,24 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
1191CONFIG_HAVE_FUNCTION_TRACER=y 1203CONFIG_HAVE_FUNCTION_TRACER=y
1192CONFIG_HAVE_DYNAMIC_FTRACE=y 1204CONFIG_HAVE_DYNAMIC_FTRACE=y
1193CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1205CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1206CONFIG_TRACING_SUPPORT=y
1194 1207
1195# 1208#
1196# Tracers 1209# Tracers
1197# 1210#
1211# CONFIG_FUNCTION_TRACER is not set
1212# CONFIG_IRQSOFF_TRACER is not set
1213# CONFIG_PREEMPT_TRACER is not set
1214# CONFIG_SCHED_TRACER is not set
1215# CONFIG_CONTEXT_SWITCH_TRACER is not set
1216# CONFIG_EVENT_TRACER is not set
1217# CONFIG_BOOT_TRACER is not set
1218# CONFIG_TRACE_BRANCH_PROFILING is not set
1219# CONFIG_STACK_TRACER is not set
1220# CONFIG_KMEMTRACE is not set
1221# CONFIG_WORKQUEUE_TRACER is not set
1222# CONFIG_BLK_DEV_IO_TRACE is not set
1223# CONFIG_DMA_API_DEBUG is not set
1198# CONFIG_SAMPLES is not set 1224# CONFIG_SAMPLES is not set
1199CONFIG_HAVE_ARCH_KGDB=y 1225CONFIG_HAVE_ARCH_KGDB=y
1200# CONFIG_SH_STANDARD_BIOS is not set 1226# CONFIG_SH_STANDARD_BIOS is not set
@@ -1303,6 +1329,7 @@ CONFIG_CRYPTO_CBC=y
1303# 1329#
1304# CONFIG_CRYPTO_ANSI_CPRNG is not set 1330# CONFIG_CRYPTO_ANSI_CPRNG is not set
1305CONFIG_CRYPTO_HW=y 1331CONFIG_CRYPTO_HW=y
1332# CONFIG_BINARY_PRINTF is not set
1306 1333
1307# 1334#
1308# Library routines 1335# Library routines
diff --git a/arch/sh/configs/cayman_defconfig b/arch/sh/configs/cayman_defconfig
index fa5fc1e1e980..40301f86a45c 100644
--- a/arch/sh/configs/cayman_defconfig
+++ b/arch/sh/configs/cayman_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 17:49:14 2009 4# Mon Apr 27 13:42:53 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7# CONFIG_SUPERH32 is not set 7# CONFIG_SUPERH32 is not set
@@ -40,6 +40,7 @@ CONFIG_LOCALVERSION_AUTO=y
40CONFIG_SWAP=y 40CONFIG_SWAP=y
41# CONFIG_SYSVIPC is not set 41# CONFIG_SYSVIPC is not set
42CONFIG_POSIX_MQUEUE=y 42CONFIG_POSIX_MQUEUE=y
43CONFIG_POSIX_MQUEUE_SYSCTL=y
43# CONFIG_BSD_PROCESS_ACCT is not set 44# CONFIG_BSD_PROCESS_ACCT is not set
44# CONFIG_TASKSTATS is not set 45# CONFIG_TASKSTATS is not set
45# CONFIG_AUDIT is not set 46# CONFIG_AUDIT is not set
@@ -70,6 +71,7 @@ CONFIG_SYSCTL_SYSCALL=y
70CONFIG_KALLSYMS=y 71CONFIG_KALLSYMS=y
71# CONFIG_KALLSYMS_ALL is not set 72# CONFIG_KALLSYMS_ALL is not set
72# CONFIG_KALLSYMS_EXTRA_PASS is not set 73# CONFIG_KALLSYMS_EXTRA_PASS is not set
74# CONFIG_STRIP_ASM_SYMS is not set
73CONFIG_HOTPLUG=y 75CONFIG_HOTPLUG=y
74CONFIG_PRINTK=y 76CONFIG_PRINTK=y
75CONFIG_BUG=y 77CONFIG_BUG=y
@@ -89,10 +91,13 @@ CONFIG_SLAB=y
89# CONFIG_SLUB is not set 91# CONFIG_SLUB is not set
90# CONFIG_SLOB is not set 92# CONFIG_SLOB is not set
91# CONFIG_PROFILING is not set 93# CONFIG_PROFILING is not set
94# CONFIG_MARKERS is not set
92CONFIG_HAVE_OPROFILE=y 95CONFIG_HAVE_OPROFILE=y
93CONFIG_HAVE_IOREMAP_PROT=y 96CONFIG_HAVE_IOREMAP_PROT=y
94CONFIG_HAVE_ARCH_TRACEHOOK=y 97CONFIG_HAVE_ARCH_TRACEHOOK=y
95CONFIG_HAVE_CLK=y 98CONFIG_HAVE_CLK=y
99CONFIG_HAVE_DMA_API_DEBUG=y
100# CONFIG_SLOW_WORK is not set
96CONFIG_HAVE_GENERIC_DMA_COHERENT=y 101CONFIG_HAVE_GENERIC_DMA_COHERENT=y
97CONFIG_SLABINFO=y 102CONFIG_SLABINFO=y
98CONFIG_RT_MUTEXES=y 103CONFIG_RT_MUTEXES=y
@@ -105,7 +110,6 @@ CONFIG_MODULE_UNLOAD=y
105# CONFIG_MODULE_SRCVERSION_ALL is not set 110# CONFIG_MODULE_SRCVERSION_ALL is not set
106CONFIG_BLOCK=y 111CONFIG_BLOCK=y
107# CONFIG_LBD is not set 112# CONFIG_LBD is not set
108# CONFIG_BLK_DEV_IO_TRACE is not set
109# CONFIG_BLK_DEV_BSG is not set 113# CONFIG_BLK_DEV_BSG is not set
110# CONFIG_BLK_DEV_INTEGRITY is not set 114# CONFIG_BLK_DEV_INTEGRITY is not set
111 115
@@ -127,39 +131,6 @@ CONFIG_DEFAULT_IOSCHED="cfq"
127# System type 131# System type
128# 132#
129CONFIG_CPU_SH5=y 133CONFIG_CPU_SH5=y
130# CONFIG_CPU_SUBTYPE_SH7619 is not set
131# CONFIG_CPU_SUBTYPE_SH7201 is not set
132# CONFIG_CPU_SUBTYPE_SH7203 is not set
133# CONFIG_CPU_SUBTYPE_SH7206 is not set
134# CONFIG_CPU_SUBTYPE_SH7263 is not set
135# CONFIG_CPU_SUBTYPE_MXG is not set
136# CONFIG_CPU_SUBTYPE_SH7705 is not set
137# CONFIG_CPU_SUBTYPE_SH7706 is not set
138# CONFIG_CPU_SUBTYPE_SH7707 is not set
139# CONFIG_CPU_SUBTYPE_SH7708 is not set
140# CONFIG_CPU_SUBTYPE_SH7709 is not set
141# CONFIG_CPU_SUBTYPE_SH7710 is not set
142# CONFIG_CPU_SUBTYPE_SH7712 is not set
143# CONFIG_CPU_SUBTYPE_SH7720 is not set
144# CONFIG_CPU_SUBTYPE_SH7721 is not set
145# CONFIG_CPU_SUBTYPE_SH7750 is not set
146# CONFIG_CPU_SUBTYPE_SH7091 is not set
147# CONFIG_CPU_SUBTYPE_SH7750R is not set
148# CONFIG_CPU_SUBTYPE_SH7750S is not set
149# CONFIG_CPU_SUBTYPE_SH7751 is not set
150# CONFIG_CPU_SUBTYPE_SH7751R is not set
151# CONFIG_CPU_SUBTYPE_SH7760 is not set
152# CONFIG_CPU_SUBTYPE_SH4_202 is not set
153# CONFIG_CPU_SUBTYPE_SH7723 is not set
154# CONFIG_CPU_SUBTYPE_SH7763 is not set
155# CONFIG_CPU_SUBTYPE_SH7770 is not set
156# CONFIG_CPU_SUBTYPE_SH7780 is not set
157# CONFIG_CPU_SUBTYPE_SH7785 is not set
158# CONFIG_CPU_SUBTYPE_SH7786 is not set
159# CONFIG_CPU_SUBTYPE_SHX3 is not set
160# CONFIG_CPU_SUBTYPE_SH7343 is not set
161# CONFIG_CPU_SUBTYPE_SH7722 is not set
162# CONFIG_CPU_SUBTYPE_SH7366 is not set
163CONFIG_CPU_SUBTYPE_SH5_101=y 134CONFIG_CPU_SUBTYPE_SH5_101=y
164# CONFIG_CPU_SUBTYPE_SH5_103 is not set 135# CONFIG_CPU_SUBTYPE_SH5_103 is not set
165 136
@@ -279,8 +250,6 @@ CONFIG_BOOT_LINK_OFFSET=0x00800000
279# 250#
280CONFIG_PCI=y 251CONFIG_PCI=y
281CONFIG_SH_PCIDMA_NONCOHERENT=y 252CONFIG_SH_PCIDMA_NONCOHERENT=y
282CONFIG_PCI_AUTO=y
283CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
284# CONFIG_PCIEPORTBUS is not set 253# CONFIG_PCIEPORTBUS is not set
285# CONFIG_ARCH_SUPPORTS_MSI is not set 254# CONFIG_ARCH_SUPPORTS_MSI is not set
286CONFIG_PCI_LEGACY=y 255CONFIG_PCI_LEGACY=y
@@ -492,6 +461,7 @@ CONFIG_SCSI_LOWLEVEL=y
492# CONFIG_SCSI_MPT2SAS is not set 461# CONFIG_SCSI_MPT2SAS is not set
493# CONFIG_SCSI_HPTIOP is not set 462# CONFIG_SCSI_HPTIOP is not set
494# CONFIG_LIBFC is not set 463# CONFIG_LIBFC is not set
464# CONFIG_LIBFCOE is not set
495# CONFIG_FCOE is not set 465# CONFIG_FCOE is not set
496# CONFIG_SCSI_DMX3191D is not set 466# CONFIG_SCSI_DMX3191D is not set
497# CONFIG_SCSI_FUTURE_DOMAIN is not set 467# CONFIG_SCSI_FUTURE_DOMAIN is not set
@@ -568,6 +538,7 @@ CONFIG_NETDEV_1000=y
568# CONFIG_E1000E is not set 538# CONFIG_E1000E is not set
569# CONFIG_IP1000 is not set 539# CONFIG_IP1000 is not set
570# CONFIG_IGB is not set 540# CONFIG_IGB is not set
541# CONFIG_IGBVF is not set
571# CONFIG_NS83820 is not set 542# CONFIG_NS83820 is not set
572# CONFIG_HAMACHI is not set 543# CONFIG_HAMACHI is not set
573# CONFIG_YELLOWFIN is not set 544# CONFIG_YELLOWFIN is not set
@@ -591,6 +562,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
591# CONFIG_IXGBE is not set 562# CONFIG_IXGBE is not set
592# CONFIG_IXGB is not set 563# CONFIG_IXGB is not set
593# CONFIG_S2IO is not set 564# CONFIG_S2IO is not set
565# CONFIG_VXGE is not set
594# CONFIG_MYRI10GE is not set 566# CONFIG_MYRI10GE is not set
595# CONFIG_NETXEN_NIC is not set 567# CONFIG_NETXEN_NIC is not set
596# CONFIG_NIU is not set 568# CONFIG_NIU is not set
@@ -779,6 +751,7 @@ CONFIG_HWMON=y
779# CONFIG_SENSORS_F71805F is not set 751# CONFIG_SENSORS_F71805F is not set
780# CONFIG_SENSORS_F71882FG is not set 752# CONFIG_SENSORS_F71882FG is not set
781# CONFIG_SENSORS_F75375S is not set 753# CONFIG_SENSORS_F75375S is not set
754# CONFIG_SENSORS_G760A is not set
782# CONFIG_SENSORS_GL518SM is not set 755# CONFIG_SENSORS_GL518SM is not set
783# CONFIG_SENSORS_GL520SM is not set 756# CONFIG_SENSORS_GL520SM is not set
784# CONFIG_SENSORS_IT87 is not set 757# CONFIG_SENSORS_IT87 is not set
@@ -1042,7 +1015,6 @@ CONFIG_HID=y
1042# 1015#
1043# Special HID drivers 1016# Special HID drivers
1044# 1017#
1045CONFIG_HID_COMPAT=y
1046CONFIG_USB_SUPPORT=y 1018CONFIG_USB_SUPPORT=y
1047CONFIG_USB_ARCH_HAS_HCD=y 1019CONFIG_USB_ARCH_HAS_HCD=y
1048CONFIG_USB_ARCH_HAS_OHCI=y 1020CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1082,6 +1054,7 @@ CONFIG_EXT2_FS=y
1082# CONFIG_EXT2_FS_XATTR is not set 1054# CONFIG_EXT2_FS_XATTR is not set
1083# CONFIG_EXT2_FS_XIP is not set 1055# CONFIG_EXT2_FS_XIP is not set
1084CONFIG_EXT3_FS=y 1056CONFIG_EXT3_FS=y
1057# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1085CONFIG_EXT3_FS_XATTR=y 1058CONFIG_EXT3_FS_XATTR=y
1086# CONFIG_EXT3_FS_POSIX_ACL is not set 1059# CONFIG_EXT3_FS_POSIX_ACL is not set
1087# CONFIG_EXT3_FS_SECURITY is not set 1060# CONFIG_EXT3_FS_SECURITY is not set
@@ -1105,6 +1078,11 @@ CONFIG_INOTIFY_USER=y
1105# CONFIG_FUSE_FS is not set 1078# CONFIG_FUSE_FS is not set
1106 1079
1107# 1080#
1081# Caches
1082#
1083# CONFIG_FSCACHE is not set
1084
1085#
1108# CD-ROM/DVD Filesystems 1086# CD-ROM/DVD Filesystems
1109# 1087#
1110# CONFIG_ISO9660_FS is not set 1088# CONFIG_ISO9660_FS is not set
@@ -1146,8 +1124,13 @@ CONFIG_MINIX_FS=y
1146# CONFIG_HPFS_FS is not set 1124# CONFIG_HPFS_FS is not set
1147# CONFIG_QNX4FS_FS is not set 1125# CONFIG_QNX4FS_FS is not set
1148CONFIG_ROMFS_FS=y 1126CONFIG_ROMFS_FS=y
1127CONFIG_ROMFS_BACKED_BY_BLOCK=y
1128# CONFIG_ROMFS_BACKED_BY_MTD is not set
1129# CONFIG_ROMFS_BACKED_BY_BOTH is not set
1130CONFIG_ROMFS_ON_BLOCK=y
1149# CONFIG_SYSV_FS is not set 1131# CONFIG_SYSV_FS is not set
1150# CONFIG_UFS_FS is not set 1132# CONFIG_UFS_FS is not set
1133# CONFIG_NILFS2_FS is not set
1151CONFIG_NETWORK_FILESYSTEMS=y 1134CONFIG_NETWORK_FILESYSTEMS=y
1152CONFIG_NFS_FS=y 1135CONFIG_NFS_FS=y
1153CONFIG_NFS_V3=y 1136CONFIG_NFS_V3=y
@@ -1208,6 +1191,9 @@ CONFIG_DEBUG_KERNEL=y
1208CONFIG_DETECT_SOFTLOCKUP=y 1191CONFIG_DETECT_SOFTLOCKUP=y
1209# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set 1192# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1210CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 1193CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1194CONFIG_DETECT_HUNG_TASK=y
1195# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1196CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1211CONFIG_SCHED_DEBUG=y 1197CONFIG_SCHED_DEBUG=y
1212CONFIG_SCHEDSTATS=y 1198CONFIG_SCHEDSTATS=y
1213# CONFIG_TIMER_STATS is not set 1199# CONFIG_TIMER_STATS is not set
@@ -1241,15 +1227,21 @@ CONFIG_FRAME_POINTER=y
1241# CONFIG_LATENCYTOP is not set 1227# CONFIG_LATENCYTOP is not set
1242# CONFIG_SYSCTL_SYSCALL_CHECK is not set 1228# CONFIG_SYSCTL_SYSCALL_CHECK is not set
1243# CONFIG_PAGE_POISONING is not set 1229# CONFIG_PAGE_POISONING is not set
1230CONFIG_TRACING_SUPPORT=y
1244 1231
1245# 1232#
1246# Tracers 1233# Tracers
1247# 1234#
1248# CONFIG_SCHED_TRACER is not set 1235# CONFIG_SCHED_TRACER is not set
1249# CONFIG_CONTEXT_SWITCH_TRACER is not set 1236# CONFIG_CONTEXT_SWITCH_TRACER is not set
1237# CONFIG_EVENT_TRACER is not set
1250# CONFIG_BOOT_TRACER is not set 1238# CONFIG_BOOT_TRACER is not set
1251# CONFIG_TRACE_BRANCH_PROFILING is not set 1239# CONFIG_TRACE_BRANCH_PROFILING is not set
1240# CONFIG_KMEMTRACE is not set
1241# CONFIG_WORKQUEUE_TRACER is not set
1242# CONFIG_BLK_DEV_IO_TRACE is not set
1252# CONFIG_DYNAMIC_DEBUG is not set 1243# CONFIG_DYNAMIC_DEBUG is not set
1244# CONFIG_DMA_API_DEBUG is not set
1253# CONFIG_SAMPLES is not set 1245# CONFIG_SAMPLES is not set
1254# CONFIG_EARLY_SCIF_CONSOLE is not set 1246# CONFIG_EARLY_SCIF_CONSOLE is not set
1255# CONFIG_DEBUG_BOOTMEM is not set 1247# CONFIG_DEBUG_BOOTMEM is not set
@@ -1354,6 +1346,7 @@ CONFIG_CRYPTO=y
1354# CONFIG_CRYPTO_ANSI_CPRNG is not set 1346# CONFIG_CRYPTO_ANSI_CPRNG is not set
1355CONFIG_CRYPTO_HW=y 1347CONFIG_CRYPTO_HW=y
1356# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1348# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1349# CONFIG_BINARY_PRINTF is not set
1357 1350
1358# 1351#
1359# Library routines 1352# Library routines
diff --git a/arch/sh/configs/dreamcast_defconfig b/arch/sh/configs/dreamcast_defconfig
index 5c1123640142..1f3cc98330bf 100644
--- a/arch/sh/configs/dreamcast_defconfig
+++ b/arch/sh/configs/dreamcast_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 17:51:48 2009 4# Mon Apr 27 12:44:27 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -71,6 +72,7 @@ CONFIG_UID16=y
71# CONFIG_SYSCTL_SYSCALL is not set 72# CONFIG_SYSCTL_SYSCALL is not set
72CONFIG_KALLSYMS=y 73CONFIG_KALLSYMS=y
73# CONFIG_KALLSYMS_EXTRA_PASS is not set 74# CONFIG_KALLSYMS_EXTRA_PASS is not set
75# CONFIG_STRIP_ASM_SYMS is not set
74CONFIG_HOTPLUG=y 76CONFIG_HOTPLUG=y
75CONFIG_PRINTK=y 77CONFIG_PRINTK=y
76CONFIG_BUG=y 78CONFIG_BUG=y
@@ -90,6 +92,7 @@ CONFIG_SLAB=y
90# CONFIG_SLUB is not set 92# CONFIG_SLUB is not set
91# CONFIG_SLOB is not set 93# CONFIG_SLOB is not set
92CONFIG_PROFILING=y 94CONFIG_PROFILING=y
95# CONFIG_MARKERS is not set
93# CONFIG_OPROFILE is not set 96# CONFIG_OPROFILE is not set
94CONFIG_HAVE_OPROFILE=y 97CONFIG_HAVE_OPROFILE=y
95# CONFIG_KPROBES is not set 98# CONFIG_KPROBES is not set
@@ -98,6 +101,8 @@ CONFIG_HAVE_KPROBES=y
98CONFIG_HAVE_KRETPROBES=y 101CONFIG_HAVE_KRETPROBES=y
99CONFIG_HAVE_ARCH_TRACEHOOK=y 102CONFIG_HAVE_ARCH_TRACEHOOK=y
100CONFIG_HAVE_CLK=y 103CONFIG_HAVE_CLK=y
104CONFIG_HAVE_DMA_API_DEBUG=y
105# CONFIG_SLOW_WORK is not set
101CONFIG_HAVE_GENERIC_DMA_COHERENT=y 106CONFIG_HAVE_GENERIC_DMA_COHERENT=y
102CONFIG_SLABINFO=y 107CONFIG_SLABINFO=y
103CONFIG_RT_MUTEXES=y 108CONFIG_RT_MUTEXES=y
@@ -110,7 +115,6 @@ CONFIG_MODULE_UNLOAD=y
110# CONFIG_MODULE_SRCVERSION_ALL is not set 115# CONFIG_MODULE_SRCVERSION_ALL is not set
111CONFIG_BLOCK=y 116CONFIG_BLOCK=y
112# CONFIG_LBD is not set 117# CONFIG_LBD is not set
113# CONFIG_BLK_DEV_IO_TRACE is not set
114# CONFIG_BLK_DEV_BSG is not set 118# CONFIG_BLK_DEV_BSG is not set
115# CONFIG_BLK_DEV_INTEGRITY is not set 119# CONFIG_BLK_DEV_INTEGRITY is not set
116 120
@@ -156,6 +160,7 @@ CONFIG_CPU_SUBTYPE_SH7091=y
156# CONFIG_CPU_SUBTYPE_SH7760 is not set 160# CONFIG_CPU_SUBTYPE_SH7760 is not set
157# CONFIG_CPU_SUBTYPE_SH4_202 is not set 161# CONFIG_CPU_SUBTYPE_SH4_202 is not set
158# CONFIG_CPU_SUBTYPE_SH7723 is not set 162# CONFIG_CPU_SUBTYPE_SH7723 is not set
163# CONFIG_CPU_SUBTYPE_SH7724 is not set
159# CONFIG_CPU_SUBTYPE_SH7763 is not set 164# CONFIG_CPU_SUBTYPE_SH7763 is not set
160# CONFIG_CPU_SUBTYPE_SH7770 is not set 165# CONFIG_CPU_SUBTYPE_SH7770 is not set
161# CONFIG_CPU_SUBTYPE_SH7780 is not set 166# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -165,8 +170,6 @@ CONFIG_CPU_SUBTYPE_SH7091=y
165# CONFIG_CPU_SUBTYPE_SH7343 is not set 170# CONFIG_CPU_SUBTYPE_SH7343 is not set
166# CONFIG_CPU_SUBTYPE_SH7722 is not set 171# CONFIG_CPU_SUBTYPE_SH7722 is not set
167# CONFIG_CPU_SUBTYPE_SH7366 is not set 172# CONFIG_CPU_SUBTYPE_SH7366 is not set
168# CONFIG_CPU_SUBTYPE_SH5_101 is not set
169# CONFIG_CPU_SUBTYPE_SH5_103 is not set
170 173
171# 174#
172# Memory management options 175# Memory management options
@@ -271,7 +274,7 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=y
271CONFIG_SH_DMA_API=y 274CONFIG_SH_DMA_API=y
272CONFIG_SH_DMA=y 275CONFIG_SH_DMA=y
273CONFIG_SH_DMA_IRQ_MULTI=y 276CONFIG_SH_DMA_IRQ_MULTI=y
274CONFIG_NR_ONCHIP_DMA_CHANNELS=6 277CONFIG_NR_ONCHIP_DMA_CHANNELS=4
275CONFIG_NR_DMA_CHANNELS_BOOL=y 278CONFIG_NR_DMA_CHANNELS_BOOL=y
276CONFIG_NR_DMA_CHANNELS=9 279CONFIG_NR_DMA_CHANNELS=9
277# CONFIG_PVR2_DMA is not set 280# CONFIG_PVR2_DMA is not set
@@ -320,7 +323,6 @@ CONFIG_CMDLINE="console=ttySC1,115200 panic=3"
320CONFIG_MAPLE=y 323CONFIG_MAPLE=y
321CONFIG_PCI=y 324CONFIG_PCI=y
322CONFIG_SH_PCIDMA_NONCOHERENT=y 325CONFIG_SH_PCIDMA_NONCOHERENT=y
323CONFIG_PCI_AUTO=y
324# CONFIG_PCIEPORTBUS is not set 326# CONFIG_PCIEPORTBUS is not set
325# CONFIG_ARCH_SUPPORTS_MSI is not set 327# CONFIG_ARCH_SUPPORTS_MSI is not set
326CONFIG_PCI_LEGACY=y 328CONFIG_PCI_LEGACY=y
@@ -602,6 +604,7 @@ CONFIG_INPUT_MOUSE=y
602# CONFIG_MOUSE_APPLETOUCH is not set 604# CONFIG_MOUSE_APPLETOUCH is not set
603# CONFIG_MOUSE_BCM5974 is not set 605# CONFIG_MOUSE_BCM5974 is not set
604# CONFIG_MOUSE_VSXXXAA is not set 606# CONFIG_MOUSE_VSXXXAA is not set
607# CONFIG_MOUSE_MAPLE is not set
605# CONFIG_INPUT_JOYSTICK is not set 608# CONFIG_INPUT_JOYSTICK is not set
606# CONFIG_INPUT_TABLET is not set 609# CONFIG_INPUT_TABLET is not set
607# CONFIG_INPUT_TOUCHSCREEN is not set 610# CONFIG_INPUT_TOUCHSCREEN is not set
@@ -812,7 +815,6 @@ CONFIG_HID=y
812# 815#
813# Special HID drivers 816# Special HID drivers
814# 817#
815CONFIG_HID_COMPAT=y
816CONFIG_USB_SUPPORT=y 818CONFIG_USB_SUPPORT=y
817CONFIG_USB_ARCH_HAS_HCD=y 819CONFIG_USB_ARCH_HAS_HCD=y
818CONFIG_USB_ARCH_HAS_OHCI=y 820CONFIG_USB_ARCH_HAS_OHCI=y
@@ -867,6 +869,11 @@ CONFIG_INOTIFY_USER=y
867# CONFIG_FUSE_FS is not set 869# CONFIG_FUSE_FS is not set
868 870
869# 871#
872# Caches
873#
874# CONFIG_FSCACHE is not set
875
876#
870# CD-ROM/DVD Filesystems 877# CD-ROM/DVD Filesystems
871# 878#
872# CONFIG_ISO9660_FS is not set 879# CONFIG_ISO9660_FS is not set
@@ -910,6 +917,7 @@ CONFIG_MISC_FILESYSTEMS=y
910# CONFIG_ROMFS_FS is not set 917# CONFIG_ROMFS_FS is not set
911# CONFIG_SYSV_FS is not set 918# CONFIG_SYSV_FS is not set
912# CONFIG_UFS_FS is not set 919# CONFIG_UFS_FS is not set
920# CONFIG_NILFS2_FS is not set
913CONFIG_NETWORK_FILESYSTEMS=y 921CONFIG_NETWORK_FILESYSTEMS=y
914# CONFIG_NFS_FS is not set 922# CONFIG_NFS_FS is not set
915# CONFIG_NFSD is not set 923# CONFIG_NFSD is not set
@@ -947,10 +955,24 @@ CONFIG_FRAME_WARN=1024
947CONFIG_HAVE_FUNCTION_TRACER=y 955CONFIG_HAVE_FUNCTION_TRACER=y
948CONFIG_HAVE_DYNAMIC_FTRACE=y 956CONFIG_HAVE_DYNAMIC_FTRACE=y
949CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 957CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
958CONFIG_TRACING_SUPPORT=y
950 959
951# 960#
952# Tracers 961# Tracers
953# 962#
963# CONFIG_FUNCTION_TRACER is not set
964# CONFIG_IRQSOFF_TRACER is not set
965# CONFIG_PREEMPT_TRACER is not set
966# CONFIG_SCHED_TRACER is not set
967# CONFIG_CONTEXT_SWITCH_TRACER is not set
968# CONFIG_EVENT_TRACER is not set
969# CONFIG_BOOT_TRACER is not set
970# CONFIG_TRACE_BRANCH_PROFILING is not set
971# CONFIG_STACK_TRACER is not set
972# CONFIG_KMEMTRACE is not set
973# CONFIG_WORKQUEUE_TRACER is not set
974# CONFIG_BLK_DEV_IO_TRACE is not set
975# CONFIG_DMA_API_DEBUG is not set
954# CONFIG_SAMPLES is not set 976# CONFIG_SAMPLES is not set
955CONFIG_HAVE_ARCH_KGDB=y 977CONFIG_HAVE_ARCH_KGDB=y
956# CONFIG_SH_STANDARD_BIOS is not set 978# CONFIG_SH_STANDARD_BIOS is not set
@@ -1051,6 +1073,7 @@ CONFIG_CRYPTO=y
1051# CONFIG_CRYPTO_ANSI_CPRNG is not set 1073# CONFIG_CRYPTO_ANSI_CPRNG is not set
1052CONFIG_CRYPTO_HW=y 1074CONFIG_CRYPTO_HW=y
1053# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1075# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1076# CONFIG_BINARY_PRINTF is not set
1054 1077
1055# 1078#
1056# Library routines 1079# Library routines
diff --git a/arch/sh/configs/edosk7705_defconfig b/arch/sh/configs/edosk7705_defconfig
index f4c34b039312..d7092457ddc7 100644
--- a/arch/sh/configs/edosk7705_defconfig
+++ b/arch/sh/configs/edosk7705_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 17:54:02 2009 4# Mon Apr 27 12:45:04 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_FIND_NEXT_BIT=y 11CONFIG_GENERIC_FIND_NEXT_BIT=y
@@ -56,6 +57,7 @@ CONFIG_EMBEDDED=y
56# CONFIG_UID16 is not set 57# CONFIG_UID16 is not set
57# CONFIG_SYSCTL_SYSCALL is not set 58# CONFIG_SYSCTL_SYSCALL is not set
58# CONFIG_KALLSYMS is not set 59# CONFIG_KALLSYMS is not set
60# CONFIG_STRIP_ASM_SYMS is not set
59# CONFIG_HOTPLUG is not set 61# CONFIG_HOTPLUG is not set
60# CONFIG_PRINTK is not set 62# CONFIG_PRINTK is not set
61# CONFIG_BUG is not set 63# CONFIG_BUG is not set
@@ -74,12 +76,15 @@ CONFIG_SHMEM=y
74CONFIG_SLUB=y 76CONFIG_SLUB=y
75# CONFIG_SLOB is not set 77# CONFIG_SLOB is not set
76# CONFIG_PROFILING is not set 78# CONFIG_PROFILING is not set
79# CONFIG_MARKERS is not set
77CONFIG_HAVE_OPROFILE=y 80CONFIG_HAVE_OPROFILE=y
78CONFIG_HAVE_IOREMAP_PROT=y 81CONFIG_HAVE_IOREMAP_PROT=y
79CONFIG_HAVE_KPROBES=y 82CONFIG_HAVE_KPROBES=y
80CONFIG_HAVE_KRETPROBES=y 83CONFIG_HAVE_KRETPROBES=y
81CONFIG_HAVE_ARCH_TRACEHOOK=y 84CONFIG_HAVE_ARCH_TRACEHOOK=y
82CONFIG_HAVE_CLK=y 85CONFIG_HAVE_CLK=y
86CONFIG_HAVE_DMA_API_DEBUG=y
87# CONFIG_SLOW_WORK is not set
83CONFIG_HAVE_GENERIC_DMA_COHERENT=y 88CONFIG_HAVE_GENERIC_DMA_COHERENT=y
84CONFIG_BASE_SMALL=1 89CONFIG_BASE_SMALL=1
85# CONFIG_MODULES is not set 90# CONFIG_MODULES is not set
@@ -114,6 +119,7 @@ CONFIG_CPU_SUBTYPE_SH7705=y
114# CONFIG_CPU_SUBTYPE_SH7760 is not set 119# CONFIG_CPU_SUBTYPE_SH7760 is not set
115# CONFIG_CPU_SUBTYPE_SH4_202 is not set 120# CONFIG_CPU_SUBTYPE_SH4_202 is not set
116# CONFIG_CPU_SUBTYPE_SH7723 is not set 121# CONFIG_CPU_SUBTYPE_SH7723 is not set
122# CONFIG_CPU_SUBTYPE_SH7724 is not set
117# CONFIG_CPU_SUBTYPE_SH7763 is not set 123# CONFIG_CPU_SUBTYPE_SH7763 is not set
118# CONFIG_CPU_SUBTYPE_SH7770 is not set 124# CONFIG_CPU_SUBTYPE_SH7770 is not set
119# CONFIG_CPU_SUBTYPE_SH7780 is not set 125# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -123,8 +129,6 @@ CONFIG_CPU_SUBTYPE_SH7705=y
123# CONFIG_CPU_SUBTYPE_SH7343 is not set 129# CONFIG_CPU_SUBTYPE_SH7343 is not set
124# CONFIG_CPU_SUBTYPE_SH7722 is not set 130# CONFIG_CPU_SUBTYPE_SH7722 is not set
125# CONFIG_CPU_SUBTYPE_SH7366 is not set 131# CONFIG_CPU_SUBTYPE_SH7366 is not set
126# CONFIG_CPU_SUBTYPE_SH5_101 is not set
127# CONFIG_CPU_SUBTYPE_SH5_103 is not set
128 132
129# 133#
130# Memory management options 134# Memory management options
@@ -382,6 +386,10 @@ CONFIG_SSB_POSSIBLE=y
382# CONFIG_FUSE_FS is not set 386# CONFIG_FUSE_FS is not set
383 387
384# 388#
389# Caches
390#
391
392#
385# Pseudo filesystems 393# Pseudo filesystems
386# 394#
387# CONFIG_PROC_FS is not set 395# CONFIG_PROC_FS is not set
@@ -409,10 +417,22 @@ CONFIG_FRAME_WARN=1024
409CONFIG_HAVE_FUNCTION_TRACER=y 417CONFIG_HAVE_FUNCTION_TRACER=y
410CONFIG_HAVE_DYNAMIC_FTRACE=y 418CONFIG_HAVE_DYNAMIC_FTRACE=y
411CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 419CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
420CONFIG_TRACING_SUPPORT=y
412 421
413# 422#
414# Tracers 423# Tracers
415# 424#
425# CONFIG_FUNCTION_TRACER is not set
426# CONFIG_IRQSOFF_TRACER is not set
427# CONFIG_SCHED_TRACER is not set
428# CONFIG_CONTEXT_SWITCH_TRACER is not set
429# CONFIG_EVENT_TRACER is not set
430# CONFIG_BOOT_TRACER is not set
431# CONFIG_TRACE_BRANCH_PROFILING is not set
432# CONFIG_STACK_TRACER is not set
433# CONFIG_KMEMTRACE is not set
434# CONFIG_WORKQUEUE_TRACER is not set
435# CONFIG_DMA_API_DEBUG is not set
416# CONFIG_SAMPLES is not set 436# CONFIG_SAMPLES is not set
417CONFIG_HAVE_ARCH_KGDB=y 437CONFIG_HAVE_ARCH_KGDB=y
418# CONFIG_SH_STANDARD_BIOS is not set 438# CONFIG_SH_STANDARD_BIOS is not set
@@ -426,6 +446,7 @@ CONFIG_HAVE_ARCH_KGDB=y
426# CONFIG_SECURITYFS is not set 446# CONFIG_SECURITYFS is not set
427# CONFIG_SECURITY_FILE_CAPABILITIES is not set 447# CONFIG_SECURITY_FILE_CAPABILITIES is not set
428# CONFIG_CRYPTO is not set 448# CONFIG_CRYPTO is not set
449# CONFIG_BINARY_PRINTF is not set
429 450
430# 451#
431# Library routines 452# Library routines
diff --git a/arch/sh/configs/edosk7760_defconfig b/arch/sh/configs/edosk7760_defconfig
index 7825c2699f18..a822b1d8c116 100644
--- a/arch/sh/configs/edosk7760_defconfig
+++ b/arch/sh/configs/edosk7760_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 17:54:57 2009 4# Mon Apr 27 12:45:25 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -40,6 +41,7 @@ CONFIG_SWAP=y
40CONFIG_SYSVIPC=y 41CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y 42CONFIG_SYSVIPC_SYSCTL=y
42CONFIG_POSIX_MQUEUE=y 43CONFIG_POSIX_MQUEUE=y
44CONFIG_POSIX_MQUEUE_SYSCTL=y
43CONFIG_BSD_PROCESS_ACCT=y 45CONFIG_BSD_PROCESS_ACCT=y
44# CONFIG_BSD_PROCESS_ACCT_V3 is not set 46# CONFIG_BSD_PROCESS_ACCT_V3 is not set
45# CONFIG_TASKSTATS is not set 47# CONFIG_TASKSTATS is not set
@@ -67,7 +69,6 @@ CONFIG_INITRAMFS_SOURCE=""
67CONFIG_RD_GZIP=y 69CONFIG_RD_GZIP=y
68# CONFIG_RD_BZIP2 is not set 70# CONFIG_RD_BZIP2 is not set
69# CONFIG_RD_LZMA is not set 71# CONFIG_RD_LZMA is not set
70CONFIG_INITRAMFS_COMPRESSION_NONE=y
71CONFIG_CC_OPTIMIZE_FOR_SIZE=y 72CONFIG_CC_OPTIMIZE_FOR_SIZE=y
72CONFIG_SYSCTL=y 73CONFIG_SYSCTL=y
73CONFIG_ANON_INODES=y 74CONFIG_ANON_INODES=y
@@ -77,6 +78,7 @@ CONFIG_SYSCTL_SYSCALL=y
77CONFIG_KALLSYMS=y 78CONFIG_KALLSYMS=y
78CONFIG_KALLSYMS_ALL=y 79CONFIG_KALLSYMS_ALL=y
79# CONFIG_KALLSYMS_EXTRA_PASS is not set 80# CONFIG_KALLSYMS_EXTRA_PASS is not set
81# CONFIG_STRIP_ASM_SYMS is not set
80CONFIG_HOTPLUG=y 82CONFIG_HOTPLUG=y
81CONFIG_PRINTK=y 83CONFIG_PRINTK=y
82CONFIG_BUG=y 84CONFIG_BUG=y
@@ -96,6 +98,7 @@ CONFIG_COMPAT_BRK=y
96CONFIG_SLUB=y 98CONFIG_SLUB=y
97# CONFIG_SLOB is not set 99# CONFIG_SLOB is not set
98# CONFIG_PROFILING is not set 100# CONFIG_PROFILING is not set
101# CONFIG_MARKERS is not set
99CONFIG_HAVE_OPROFILE=y 102CONFIG_HAVE_OPROFILE=y
100# CONFIG_KPROBES is not set 103# CONFIG_KPROBES is not set
101CONFIG_HAVE_IOREMAP_PROT=y 104CONFIG_HAVE_IOREMAP_PROT=y
@@ -103,6 +106,8 @@ CONFIG_HAVE_KPROBES=y
103CONFIG_HAVE_KRETPROBES=y 106CONFIG_HAVE_KRETPROBES=y
104CONFIG_HAVE_ARCH_TRACEHOOK=y 107CONFIG_HAVE_ARCH_TRACEHOOK=y
105CONFIG_HAVE_CLK=y 108CONFIG_HAVE_CLK=y
109CONFIG_HAVE_DMA_API_DEBUG=y
110# CONFIG_SLOW_WORK is not set
106CONFIG_HAVE_GENERIC_DMA_COHERENT=y 111CONFIG_HAVE_GENERIC_DMA_COHERENT=y
107CONFIG_SLABINFO=y 112CONFIG_SLABINFO=y
108CONFIG_RT_MUTEXES=y 113CONFIG_RT_MUTEXES=y
@@ -115,7 +120,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y
115# CONFIG_MODULE_SRCVERSION_ALL is not set 120# CONFIG_MODULE_SRCVERSION_ALL is not set
116CONFIG_BLOCK=y 121CONFIG_BLOCK=y
117# CONFIG_LBD is not set 122# CONFIG_LBD is not set
118# CONFIG_BLK_DEV_IO_TRACE is not set
119# CONFIG_BLK_DEV_BSG is not set 123# CONFIG_BLK_DEV_BSG is not set
120# CONFIG_BLK_DEV_INTEGRITY is not set 124# CONFIG_BLK_DEV_INTEGRITY is not set
121 125
@@ -161,6 +165,7 @@ CONFIG_CPU_SH4=y
161CONFIG_CPU_SUBTYPE_SH7760=y 165CONFIG_CPU_SUBTYPE_SH7760=y
162# CONFIG_CPU_SUBTYPE_SH4_202 is not set 166# CONFIG_CPU_SUBTYPE_SH4_202 is not set
163# CONFIG_CPU_SUBTYPE_SH7723 is not set 167# CONFIG_CPU_SUBTYPE_SH7723 is not set
168# CONFIG_CPU_SUBTYPE_SH7724 is not set
164# CONFIG_CPU_SUBTYPE_SH7763 is not set 169# CONFIG_CPU_SUBTYPE_SH7763 is not set
165# CONFIG_CPU_SUBTYPE_SH7770 is not set 170# CONFIG_CPU_SUBTYPE_SH7770 is not set
166# CONFIG_CPU_SUBTYPE_SH7780 is not set 171# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -170,8 +175,6 @@ CONFIG_CPU_SUBTYPE_SH7760=y
170# CONFIG_CPU_SUBTYPE_SH7343 is not set 175# CONFIG_CPU_SUBTYPE_SH7343 is not set
171# CONFIG_CPU_SUBTYPE_SH7722 is not set 176# CONFIG_CPU_SUBTYPE_SH7722 is not set
172# CONFIG_CPU_SUBTYPE_SH7366 is not set 177# CONFIG_CPU_SUBTYPE_SH7366 is not set
173# CONFIG_CPU_SUBTYPE_SH5_101 is not set
174# CONFIG_CPU_SUBTYPE_SH5_103 is not set
175 178
176# 179#
177# Memory management options 180# Memory management options
@@ -815,6 +818,7 @@ CONFIG_EXT2_FS_XATTR=y
815# CONFIG_EXT2_FS_SECURITY is not set 818# CONFIG_EXT2_FS_SECURITY is not set
816CONFIG_EXT2_FS_XIP=y 819CONFIG_EXT2_FS_XIP=y
817CONFIG_EXT3_FS=y 820CONFIG_EXT3_FS=y
821# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
818CONFIG_EXT3_FS_XATTR=y 822CONFIG_EXT3_FS_XATTR=y
819# CONFIG_EXT3_FS_POSIX_ACL is not set 823# CONFIG_EXT3_FS_POSIX_ACL is not set
820# CONFIG_EXT3_FS_SECURITY is not set 824# CONFIG_EXT3_FS_SECURITY is not set
@@ -839,6 +843,11 @@ CONFIG_INOTIFY_USER=y
839CONFIG_GENERIC_ACL=y 843CONFIG_GENERIC_ACL=y
840 844
841# 845#
846# Caches
847#
848# CONFIG_FSCACHE is not set
849
850#
842# CD-ROM/DVD Filesystems 851# CD-ROM/DVD Filesystems
843# 852#
844# CONFIG_ISO9660_FS is not set 853# CONFIG_ISO9660_FS is not set
@@ -883,6 +892,7 @@ CONFIG_MISC_FILESYSTEMS=y
883# CONFIG_ROMFS_FS is not set 892# CONFIG_ROMFS_FS is not set
884# CONFIG_SYSV_FS is not set 893# CONFIG_SYSV_FS is not set
885# CONFIG_UFS_FS is not set 894# CONFIG_UFS_FS is not set
895# CONFIG_NILFS2_FS is not set
886CONFIG_NETWORK_FILESYSTEMS=y 896CONFIG_NETWORK_FILESYSTEMS=y
887CONFIG_NFS_FS=y 897CONFIG_NFS_FS=y
888# CONFIG_NFS_V3 is not set 898# CONFIG_NFS_V3 is not set
@@ -964,6 +974,9 @@ CONFIG_DEBUG_SHIRQ=y
964CONFIG_DETECT_SOFTLOCKUP=y 974CONFIG_DETECT_SOFTLOCKUP=y
965# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set 975# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
966CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 976CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
977CONFIG_DETECT_HUNG_TASK=y
978# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
979CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
967# CONFIG_SCHED_DEBUG is not set 980# CONFIG_SCHED_DEBUG is not set
968# CONFIG_SCHEDSTATS is not set 981# CONFIG_SCHEDSTATS is not set
969CONFIG_TIMER_STATS=y 982CONFIG_TIMER_STATS=y
@@ -1001,6 +1014,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
1001CONFIG_HAVE_FUNCTION_TRACER=y 1014CONFIG_HAVE_FUNCTION_TRACER=y
1002CONFIG_HAVE_DYNAMIC_FTRACE=y 1015CONFIG_HAVE_DYNAMIC_FTRACE=y
1003CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1016CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1017CONFIG_TRACING_SUPPORT=y
1004 1018
1005# 1019#
1006# Tracers 1020# Tracers
@@ -1010,9 +1024,14 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1010# CONFIG_PREEMPT_TRACER is not set 1024# CONFIG_PREEMPT_TRACER is not set
1011# CONFIG_SCHED_TRACER is not set 1025# CONFIG_SCHED_TRACER is not set
1012# CONFIG_CONTEXT_SWITCH_TRACER is not set 1026# CONFIG_CONTEXT_SWITCH_TRACER is not set
1027# CONFIG_EVENT_TRACER is not set
1013# CONFIG_BOOT_TRACER is not set 1028# CONFIG_BOOT_TRACER is not set
1014# CONFIG_TRACE_BRANCH_PROFILING is not set 1029# CONFIG_TRACE_BRANCH_PROFILING is not set
1015# CONFIG_STACK_TRACER is not set 1030# CONFIG_STACK_TRACER is not set
1031# CONFIG_KMEMTRACE is not set
1032# CONFIG_WORKQUEUE_TRACER is not set
1033# CONFIG_BLK_DEV_IO_TRACE is not set
1034# CONFIG_DMA_API_DEBUG is not set
1016# CONFIG_SAMPLES is not set 1035# CONFIG_SAMPLES is not set
1017CONFIG_HAVE_ARCH_KGDB=y 1036CONFIG_HAVE_ARCH_KGDB=y
1018# CONFIG_KGDB is not set 1037# CONFIG_KGDB is not set
@@ -1126,6 +1145,7 @@ CONFIG_CRYPTO_DES=y
1126# 1145#
1127# CONFIG_CRYPTO_ANSI_CPRNG is not set 1146# CONFIG_CRYPTO_ANSI_CPRNG is not set
1128CONFIG_CRYPTO_HW=y 1147CONFIG_CRYPTO_HW=y
1148# CONFIG_BINARY_PRINTF is not set
1129 1149
1130# 1150#
1131# Library routines 1151# Library routines
diff --git a/arch/sh/configs/espt_defconfig b/arch/sh/configs/espt_defconfig
index ebb4c37abaa6..c5b50077913d 100644
--- a/arch/sh/configs/espt_defconfig
+++ b/arch/sh/configs/espt_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 17:58:18 2009 4# Mon Apr 27 12:46:26 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -78,6 +79,7 @@ CONFIG_UID16=y
78# CONFIG_SYSCTL_SYSCALL is not set 79# CONFIG_SYSCTL_SYSCALL is not set
79CONFIG_KALLSYMS=y 80CONFIG_KALLSYMS=y
80# CONFIG_KALLSYMS_EXTRA_PASS is not set 81# CONFIG_KALLSYMS_EXTRA_PASS is not set
82# CONFIG_STRIP_ASM_SYMS is not set
81CONFIG_HOTPLUG=y 83CONFIG_HOTPLUG=y
82CONFIG_PRINTK=y 84CONFIG_PRINTK=y
83CONFIG_BUG=y 85CONFIG_BUG=y
@@ -106,6 +108,8 @@ CONFIG_HAVE_KPROBES=y
106CONFIG_HAVE_KRETPROBES=y 108CONFIG_HAVE_KRETPROBES=y
107CONFIG_HAVE_ARCH_TRACEHOOK=y 109CONFIG_HAVE_ARCH_TRACEHOOK=y
108CONFIG_HAVE_CLK=y 110CONFIG_HAVE_CLK=y
111CONFIG_HAVE_DMA_API_DEBUG=y
112# CONFIG_SLOW_WORK is not set
109CONFIG_HAVE_GENERIC_DMA_COHERENT=y 113CONFIG_HAVE_GENERIC_DMA_COHERENT=y
110CONFIG_SLABINFO=y 114CONFIG_SLABINFO=y
111CONFIG_RT_MUTEXES=y 115CONFIG_RT_MUTEXES=y
@@ -117,7 +121,6 @@ CONFIG_MODULES=y
117# CONFIG_MODULE_SRCVERSION_ALL is not set 121# CONFIG_MODULE_SRCVERSION_ALL is not set
118CONFIG_BLOCK=y 122CONFIG_BLOCK=y
119# CONFIG_LBD is not set 123# CONFIG_LBD is not set
120# CONFIG_BLK_DEV_IO_TRACE is not set
121# CONFIG_BLK_DEV_BSG is not set 124# CONFIG_BLK_DEV_BSG is not set
122# CONFIG_BLK_DEV_INTEGRITY is not set 125# CONFIG_BLK_DEV_INTEGRITY is not set
123 126
@@ -164,6 +167,7 @@ CONFIG_CPU_SH4A=y
164# CONFIG_CPU_SUBTYPE_SH7760 is not set 167# CONFIG_CPU_SUBTYPE_SH7760 is not set
165# CONFIG_CPU_SUBTYPE_SH4_202 is not set 168# CONFIG_CPU_SUBTYPE_SH4_202 is not set
166# CONFIG_CPU_SUBTYPE_SH7723 is not set 169# CONFIG_CPU_SUBTYPE_SH7723 is not set
170# CONFIG_CPU_SUBTYPE_SH7724 is not set
167CONFIG_CPU_SUBTYPE_SH7763=y 171CONFIG_CPU_SUBTYPE_SH7763=y
168# CONFIG_CPU_SUBTYPE_SH7770 is not set 172# CONFIG_CPU_SUBTYPE_SH7770 is not set
169# CONFIG_CPU_SUBTYPE_SH7780 is not set 173# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -173,8 +177,6 @@ CONFIG_CPU_SUBTYPE_SH7763=y
173# CONFIG_CPU_SUBTYPE_SH7343 is not set 177# CONFIG_CPU_SUBTYPE_SH7343 is not set
174# CONFIG_CPU_SUBTYPE_SH7722 is not set 178# CONFIG_CPU_SUBTYPE_SH7722 is not set
175# CONFIG_CPU_SUBTYPE_SH7366 is not set 179# CONFIG_CPU_SUBTYPE_SH7366 is not set
176# CONFIG_CPU_SUBTYPE_SH5_101 is not set
177# CONFIG_CPU_SUBTYPE_SH5_103 is not set
178 180
179# 181#
180# Memory management options 182# Memory management options
@@ -548,6 +550,7 @@ CONFIG_SCSI_WAIT_SCAN=m
548CONFIG_SCSI_LOWLEVEL=y 550CONFIG_SCSI_LOWLEVEL=y
549# CONFIG_ISCSI_TCP is not set 551# CONFIG_ISCSI_TCP is not set
550# CONFIG_LIBFC is not set 552# CONFIG_LIBFC is not set
553# CONFIG_LIBFCOE is not set
551# CONFIG_SCSI_DEBUG is not set 554# CONFIG_SCSI_DEBUG is not set
552# CONFIG_SCSI_DH is not set 555# CONFIG_SCSI_DH is not set
553# CONFIG_SCSI_OSD_INITIATOR is not set 556# CONFIG_SCSI_OSD_INITIATOR is not set
@@ -919,6 +922,7 @@ CONFIG_EXT2_FS=y
919# CONFIG_EXT2_FS_XATTR is not set 922# CONFIG_EXT2_FS_XATTR is not set
920# CONFIG_EXT2_FS_XIP is not set 923# CONFIG_EXT2_FS_XIP is not set
921CONFIG_EXT3_FS=y 924CONFIG_EXT3_FS=y
925# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
922CONFIG_EXT3_FS_XATTR=y 926CONFIG_EXT3_FS_XATTR=y
923# CONFIG_EXT3_FS_POSIX_ACL is not set 927# CONFIG_EXT3_FS_POSIX_ACL is not set
924# CONFIG_EXT3_FS_SECURITY is not set 928# CONFIG_EXT3_FS_SECURITY is not set
@@ -943,6 +947,11 @@ CONFIG_AUTOFS4_FS=y
943CONFIG_GENERIC_ACL=y 947CONFIG_GENERIC_ACL=y
944 948
945# 949#
950# Caches
951#
952# CONFIG_FSCACHE is not set
953
954#
946# CD-ROM/DVD Filesystems 955# CD-ROM/DVD Filesystems
947# 956#
948# CONFIG_ISO9660_FS is not set 957# CONFIG_ISO9660_FS is not set
@@ -985,8 +994,13 @@ CONFIG_CRAMFS=y
985# CONFIG_HPFS_FS is not set 994# CONFIG_HPFS_FS is not set
986# CONFIG_QNX4FS_FS is not set 995# CONFIG_QNX4FS_FS is not set
987CONFIG_ROMFS_FS=y 996CONFIG_ROMFS_FS=y
997CONFIG_ROMFS_BACKED_BY_BLOCK=y
998# CONFIG_ROMFS_BACKED_BY_MTD is not set
999# CONFIG_ROMFS_BACKED_BY_BOTH is not set
1000CONFIG_ROMFS_ON_BLOCK=y
988# CONFIG_SYSV_FS is not set 1001# CONFIG_SYSV_FS is not set
989# CONFIG_UFS_FS is not set 1002# CONFIG_UFS_FS is not set
1003# CONFIG_NILFS2_FS is not set
990CONFIG_NETWORK_FILESYSTEMS=y 1004CONFIG_NETWORK_FILESYSTEMS=y
991CONFIG_NFS_FS=y 1005CONFIG_NFS_FS=y
992# CONFIG_NFS_V3 is not set 1006# CONFIG_NFS_V3 is not set
@@ -1075,11 +1089,25 @@ CONFIG_HAVE_DYNAMIC_FTRACE=y
1075CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1089CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1076CONFIG_RING_BUFFER=y 1090CONFIG_RING_BUFFER=y
1077CONFIG_TRACING=y 1091CONFIG_TRACING=y
1092CONFIG_TRACING_SUPPORT=y
1078 1093
1079# 1094#
1080# Tracers 1095# Tracers
1081# 1096#
1097# CONFIG_FUNCTION_TRACER is not set
1098# CONFIG_IRQSOFF_TRACER is not set
1099# CONFIG_SCHED_TRACER is not set
1100# CONFIG_CONTEXT_SWITCH_TRACER is not set
1101# CONFIG_EVENT_TRACER is not set
1102# CONFIG_BOOT_TRACER is not set
1103# CONFIG_TRACE_BRANCH_PROFILING is not set
1104# CONFIG_STACK_TRACER is not set
1105# CONFIG_KMEMTRACE is not set
1106# CONFIG_WORKQUEUE_TRACER is not set
1107# CONFIG_BLK_DEV_IO_TRACE is not set
1108# CONFIG_FTRACE_STARTUP_TEST is not set
1082# CONFIG_DYNAMIC_DEBUG is not set 1109# CONFIG_DYNAMIC_DEBUG is not set
1110# CONFIG_DMA_API_DEBUG is not set
1083# CONFIG_SAMPLES is not set 1111# CONFIG_SAMPLES is not set
1084CONFIG_HAVE_ARCH_KGDB=y 1112CONFIG_HAVE_ARCH_KGDB=y
1085# CONFIG_SH_STANDARD_BIOS is not set 1113# CONFIG_SH_STANDARD_BIOS is not set
@@ -1179,6 +1207,7 @@ CONFIG_CRYPTO=y
1179# 1207#
1180# CONFIG_CRYPTO_ANSI_CPRNG is not set 1208# CONFIG_CRYPTO_ANSI_CPRNG is not set
1181CONFIG_CRYPTO_HW=y 1209CONFIG_CRYPTO_HW=y
1210CONFIG_BINARY_PRINTF=y
1182 1211
1183# 1212#
1184# Library routines 1213# Library routines
diff --git a/arch/sh/configs/hp6xx_defconfig b/arch/sh/configs/hp6xx_defconfig
index 82b113af08d3..8e13027eecc3 100644
--- a/arch/sh/configs/hp6xx_defconfig
+++ b/arch/sh/configs/hp6xx_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:01:05 2009 4# Mon Apr 27 12:47:15 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -67,6 +68,7 @@ CONFIG_UID16=y
67# CONFIG_SYSCTL_SYSCALL is not set 68# CONFIG_SYSCTL_SYSCALL is not set
68CONFIG_KALLSYMS=y 69CONFIG_KALLSYMS=y
69# CONFIG_KALLSYMS_EXTRA_PASS is not set 70# CONFIG_KALLSYMS_EXTRA_PASS is not set
71# CONFIG_STRIP_ASM_SYMS is not set
70CONFIG_HOTPLUG=y 72CONFIG_HOTPLUG=y
71CONFIG_PRINTK=y 73CONFIG_PRINTK=y
72CONFIG_BUG=y 74CONFIG_BUG=y
@@ -85,12 +87,15 @@ CONFIG_SLAB=y
85# CONFIG_SLUB is not set 87# CONFIG_SLUB is not set
86# CONFIG_SLOB is not set 88# CONFIG_SLOB is not set
87# CONFIG_PROFILING is not set 89# CONFIG_PROFILING is not set
90# CONFIG_MARKERS is not set
88CONFIG_HAVE_OPROFILE=y 91CONFIG_HAVE_OPROFILE=y
89CONFIG_HAVE_IOREMAP_PROT=y 92CONFIG_HAVE_IOREMAP_PROT=y
90CONFIG_HAVE_KPROBES=y 93CONFIG_HAVE_KPROBES=y
91CONFIG_HAVE_KRETPROBES=y 94CONFIG_HAVE_KRETPROBES=y
92CONFIG_HAVE_ARCH_TRACEHOOK=y 95CONFIG_HAVE_ARCH_TRACEHOOK=y
93CONFIG_HAVE_CLK=y 96CONFIG_HAVE_CLK=y
97CONFIG_HAVE_DMA_API_DEBUG=y
98# CONFIG_SLOW_WORK is not set
94CONFIG_HAVE_GENERIC_DMA_COHERENT=y 99CONFIG_HAVE_GENERIC_DMA_COHERENT=y
95CONFIG_SLABINFO=y 100CONFIG_SLABINFO=y
96CONFIG_RT_MUTEXES=y 101CONFIG_RT_MUTEXES=y
@@ -98,7 +103,6 @@ CONFIG_BASE_SMALL=0
98# CONFIG_MODULES is not set 103# CONFIG_MODULES is not set
99CONFIG_BLOCK=y 104CONFIG_BLOCK=y
100# CONFIG_LBD is not set 105# CONFIG_LBD is not set
101# CONFIG_BLK_DEV_IO_TRACE is not set
102# CONFIG_BLK_DEV_BSG is not set 106# CONFIG_BLK_DEV_BSG is not set
103# CONFIG_BLK_DEV_INTEGRITY is not set 107# CONFIG_BLK_DEV_INTEGRITY is not set
104 108
@@ -144,6 +148,7 @@ CONFIG_CPU_SUBTYPE_SH7709=y
144# CONFIG_CPU_SUBTYPE_SH7760 is not set 148# CONFIG_CPU_SUBTYPE_SH7760 is not set
145# CONFIG_CPU_SUBTYPE_SH4_202 is not set 149# CONFIG_CPU_SUBTYPE_SH4_202 is not set
146# CONFIG_CPU_SUBTYPE_SH7723 is not set 150# CONFIG_CPU_SUBTYPE_SH7723 is not set
151# CONFIG_CPU_SUBTYPE_SH7724 is not set
147# CONFIG_CPU_SUBTYPE_SH7763 is not set 152# CONFIG_CPU_SUBTYPE_SH7763 is not set
148# CONFIG_CPU_SUBTYPE_SH7770 is not set 153# CONFIG_CPU_SUBTYPE_SH7770 is not set
149# CONFIG_CPU_SUBTYPE_SH7780 is not set 154# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -153,8 +158,6 @@ CONFIG_CPU_SUBTYPE_SH7709=y
153# CONFIG_CPU_SUBTYPE_SH7343 is not set 158# CONFIG_CPU_SUBTYPE_SH7343 is not set
154# CONFIG_CPU_SUBTYPE_SH7722 is not set 159# CONFIG_CPU_SUBTYPE_SH7722 is not set
155# CONFIG_CPU_SUBTYPE_SH7366 is not set 160# CONFIG_CPU_SUBTYPE_SH7366 is not set
156# CONFIG_CPU_SUBTYPE_SH5_101 is not set
157# CONFIG_CPU_SUBTYPE_SH5_103 is not set
158 161
159# 162#
160# Memory management options 163# Memory management options
@@ -385,6 +388,7 @@ CONFIG_BLK_DEV_SD=y
385# CONFIG_SCSI_SRP_ATTRS is not set 388# CONFIG_SCSI_SRP_ATTRS is not set
386CONFIG_SCSI_LOWLEVEL=y 389CONFIG_SCSI_LOWLEVEL=y
387# CONFIG_LIBFC is not set 390# CONFIG_LIBFC is not set
391# CONFIG_LIBFCOE is not set
388# CONFIG_SCSI_DEBUG is not set 392# CONFIG_SCSI_DEBUG is not set
389# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set 393# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
390# CONFIG_SCSI_DH is not set 394# CONFIG_SCSI_DH is not set
@@ -431,6 +435,7 @@ CONFIG_KEYBOARD_HP6XX=y
431# CONFIG_INPUT_JOYSTICK is not set 435# CONFIG_INPUT_JOYSTICK is not set
432# CONFIG_INPUT_TABLET is not set 436# CONFIG_INPUT_TABLET is not set
433CONFIG_INPUT_TOUCHSCREEN=y 437CONFIG_INPUT_TOUCHSCREEN=y
438# CONFIG_TOUCHSCREEN_AD7879 is not set
434# CONFIG_TOUCHSCREEN_FUJITSU is not set 439# CONFIG_TOUCHSCREEN_FUJITSU is not set
435# CONFIG_TOUCHSCREEN_GUNZE is not set 440# CONFIG_TOUCHSCREEN_GUNZE is not set
436# CONFIG_TOUCHSCREEN_ELO is not set 441# CONFIG_TOUCHSCREEN_ELO is not set
@@ -674,6 +679,11 @@ CONFIG_INOTIFY_USER=y
674# CONFIG_FUSE_FS is not set 679# CONFIG_FUSE_FS is not set
675 680
676# 681#
682# Caches
683#
684# CONFIG_FSCACHE is not set
685
686#
677# CD-ROM/DVD Filesystems 687# CD-ROM/DVD Filesystems
678# 688#
679# CONFIG_ISO9660_FS is not set 689# CONFIG_ISO9660_FS is not set
@@ -719,6 +729,7 @@ CONFIG_MISC_FILESYSTEMS=y
719# CONFIG_ROMFS_FS is not set 729# CONFIG_ROMFS_FS is not set
720# CONFIG_SYSV_FS is not set 730# CONFIG_SYSV_FS is not set
721# CONFIG_UFS_FS is not set 731# CONFIG_UFS_FS is not set
732# CONFIG_NILFS2_FS is not set
722 733
723# 734#
724# Partition Types 735# Partition Types
@@ -786,10 +797,23 @@ CONFIG_FRAME_WARN=1024
786CONFIG_HAVE_FUNCTION_TRACER=y 797CONFIG_HAVE_FUNCTION_TRACER=y
787CONFIG_HAVE_DYNAMIC_FTRACE=y 798CONFIG_HAVE_DYNAMIC_FTRACE=y
788CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 799CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
800CONFIG_TRACING_SUPPORT=y
789 801
790# 802#
791# Tracers 803# Tracers
792# 804#
805# CONFIG_FUNCTION_TRACER is not set
806# CONFIG_IRQSOFF_TRACER is not set
807# CONFIG_SCHED_TRACER is not set
808# CONFIG_CONTEXT_SWITCH_TRACER is not set
809# CONFIG_EVENT_TRACER is not set
810# CONFIG_BOOT_TRACER is not set
811# CONFIG_TRACE_BRANCH_PROFILING is not set
812# CONFIG_STACK_TRACER is not set
813# CONFIG_KMEMTRACE is not set
814# CONFIG_WORKQUEUE_TRACER is not set
815# CONFIG_BLK_DEV_IO_TRACE is not set
816# CONFIG_DMA_API_DEBUG is not set
793# CONFIG_SAMPLES is not set 817# CONFIG_SAMPLES is not set
794CONFIG_HAVE_ARCH_KGDB=y 818CONFIG_HAVE_ARCH_KGDB=y
795# CONFIG_SH_STANDARD_BIOS is not set 819# CONFIG_SH_STANDARD_BIOS is not set
@@ -898,6 +922,7 @@ CONFIG_CRYPTO_MD5=y
898# 922#
899# CONFIG_CRYPTO_ANSI_CPRNG is not set 923# CONFIG_CRYPTO_ANSI_CPRNG is not set
900# CONFIG_CRYPTO_HW is not set 924# CONFIG_CRYPTO_HW is not set
925# CONFIG_BINARY_PRINTF is not set
901 926
902# 927#
903# Library routines 928# Library routines
diff --git a/arch/sh/configs/landisk_defconfig b/arch/sh/configs/landisk_defconfig
index b6fa4a7599d0..7f549aef0dfd 100644
--- a/arch/sh/configs/landisk_defconfig
+++ b/arch/sh/configs/landisk_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:02:54 2009 4# Mon Apr 27 12:47:48 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -69,6 +70,7 @@ CONFIG_UID16=y
69# CONFIG_SYSCTL_SYSCALL is not set 70# CONFIG_SYSCTL_SYSCALL is not set
70CONFIG_KALLSYMS=y 71CONFIG_KALLSYMS=y
71CONFIG_KALLSYMS_EXTRA_PASS=y 72CONFIG_KALLSYMS_EXTRA_PASS=y
73# CONFIG_STRIP_ASM_SYMS is not set
72CONFIG_HOTPLUG=y 74CONFIG_HOTPLUG=y
73CONFIG_PRINTK=y 75CONFIG_PRINTK=y
74CONFIG_BUG=y 76CONFIG_BUG=y
@@ -88,6 +90,7 @@ CONFIG_SLAB=y
88# CONFIG_SLUB is not set 90# CONFIG_SLUB is not set
89# CONFIG_SLOB is not set 91# CONFIG_SLOB is not set
90# CONFIG_PROFILING is not set 92# CONFIG_PROFILING is not set
93# CONFIG_MARKERS is not set
91CONFIG_HAVE_OPROFILE=y 94CONFIG_HAVE_OPROFILE=y
92# CONFIG_KPROBES is not set 95# CONFIG_KPROBES is not set
93CONFIG_HAVE_IOREMAP_PROT=y 96CONFIG_HAVE_IOREMAP_PROT=y
@@ -95,6 +98,8 @@ CONFIG_HAVE_KPROBES=y
95CONFIG_HAVE_KRETPROBES=y 98CONFIG_HAVE_KRETPROBES=y
96CONFIG_HAVE_ARCH_TRACEHOOK=y 99CONFIG_HAVE_ARCH_TRACEHOOK=y
97CONFIG_HAVE_CLK=y 100CONFIG_HAVE_CLK=y
101CONFIG_HAVE_DMA_API_DEBUG=y
102# CONFIG_SLOW_WORK is not set
98CONFIG_HAVE_GENERIC_DMA_COHERENT=y 103CONFIG_HAVE_GENERIC_DMA_COHERENT=y
99CONFIG_SLABINFO=y 104CONFIG_SLABINFO=y
100CONFIG_RT_MUTEXES=y 105CONFIG_RT_MUTEXES=y
@@ -107,7 +112,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y
107# CONFIG_MODULE_SRCVERSION_ALL is not set 112# CONFIG_MODULE_SRCVERSION_ALL is not set
108CONFIG_BLOCK=y 113CONFIG_BLOCK=y
109# CONFIG_LBD is not set 114# CONFIG_LBD is not set
110# CONFIG_BLK_DEV_IO_TRACE is not set
111# CONFIG_BLK_DEV_BSG is not set 115# CONFIG_BLK_DEV_BSG is not set
112# CONFIG_BLK_DEV_INTEGRITY is not set 116# CONFIG_BLK_DEV_INTEGRITY is not set
113 117
@@ -153,6 +157,7 @@ CONFIG_CPU_SUBTYPE_SH7751R=y
153# CONFIG_CPU_SUBTYPE_SH7760 is not set 157# CONFIG_CPU_SUBTYPE_SH7760 is not set
154# CONFIG_CPU_SUBTYPE_SH4_202 is not set 158# CONFIG_CPU_SUBTYPE_SH4_202 is not set
155# CONFIG_CPU_SUBTYPE_SH7723 is not set 159# CONFIG_CPU_SUBTYPE_SH7723 is not set
160# CONFIG_CPU_SUBTYPE_SH7724 is not set
156# CONFIG_CPU_SUBTYPE_SH7763 is not set 161# CONFIG_CPU_SUBTYPE_SH7763 is not set
157# CONFIG_CPU_SUBTYPE_SH7770 is not set 162# CONFIG_CPU_SUBTYPE_SH7770 is not set
158# CONFIG_CPU_SUBTYPE_SH7780 is not set 163# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -162,8 +167,6 @@ CONFIG_CPU_SUBTYPE_SH7751R=y
162# CONFIG_CPU_SUBTYPE_SH7343 is not set 167# CONFIG_CPU_SUBTYPE_SH7343 is not set
163# CONFIG_CPU_SUBTYPE_SH7722 is not set 168# CONFIG_CPU_SUBTYPE_SH7722 is not set
164# CONFIG_CPU_SUBTYPE_SH7366 is not set 169# CONFIG_CPU_SUBTYPE_SH7366 is not set
165# CONFIG_CPU_SUBTYPE_SH5_101 is not set
166# CONFIG_CPU_SUBTYPE_SH5_103 is not set
167 170
168# 171#
169# Memory management options 172# Memory management options
@@ -292,8 +295,6 @@ CONFIG_BOOT_LINK_OFFSET=0x00800000
292# 295#
293CONFIG_PCI=y 296CONFIG_PCI=y
294CONFIG_SH_PCIDMA_NONCOHERENT=y 297CONFIG_SH_PCIDMA_NONCOHERENT=y
295CONFIG_PCI_AUTO=y
296CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
297# CONFIG_PCIEPORTBUS is not set 298# CONFIG_PCIEPORTBUS is not set
298# CONFIG_ARCH_SUPPORTS_MSI is not set 299# CONFIG_ARCH_SUPPORTS_MSI is not set
299CONFIG_PCI_LEGACY=y 300CONFIG_PCI_LEGACY=y
@@ -602,6 +603,7 @@ CONFIG_SCSI_LOWLEVEL=y
602# CONFIG_SCSI_MPT2SAS is not set 603# CONFIG_SCSI_MPT2SAS is not set
603# CONFIG_SCSI_HPTIOP is not set 604# CONFIG_SCSI_HPTIOP is not set
604# CONFIG_LIBFC is not set 605# CONFIG_LIBFC is not set
606# CONFIG_LIBFCOE is not set
605# CONFIG_FCOE is not set 607# CONFIG_FCOE is not set
606# CONFIG_SCSI_DMX3191D is not set 608# CONFIG_SCSI_DMX3191D is not set
607# CONFIG_SCSI_FUTURE_DOMAIN is not set 609# CONFIG_SCSI_FUTURE_DOMAIN is not set
@@ -706,6 +708,7 @@ CONFIG_NETDEV_1000=y
706# CONFIG_E1000E is not set 708# CONFIG_E1000E is not set
707# CONFIG_IP1000 is not set 709# CONFIG_IP1000 is not set
708# CONFIG_IGB is not set 710# CONFIG_IGB is not set
711# CONFIG_IGBVF is not set
709# CONFIG_NS83820 is not set 712# CONFIG_NS83820 is not set
710# CONFIG_HAMACHI is not set 713# CONFIG_HAMACHI is not set
711# CONFIG_YELLOWFIN is not set 714# CONFIG_YELLOWFIN is not set
@@ -729,6 +732,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
729# CONFIG_IXGBE is not set 732# CONFIG_IXGBE is not set
730# CONFIG_IXGB is not set 733# CONFIG_IXGB is not set
731# CONFIG_S2IO is not set 734# CONFIG_S2IO is not set
735# CONFIG_VXGE is not set
732# CONFIG_MYRI10GE is not set 736# CONFIG_MYRI10GE is not set
733# CONFIG_NETXEN_NIC is not set 737# CONFIG_NETXEN_NIC is not set
734# CONFIG_NIU is not set 738# CONFIG_NIU is not set
@@ -922,6 +926,7 @@ CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
922# CONFIG_SOC_CAMERA is not set 926# CONFIG_SOC_CAMERA is not set
923CONFIG_V4L_USB_DRIVERS=y 927CONFIG_V4L_USB_DRIVERS=y
924# CONFIG_USB_VIDEO_CLASS is not set 928# CONFIG_USB_VIDEO_CLASS is not set
929CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
925# CONFIG_USB_GSPCA is not set 930# CONFIG_USB_GSPCA is not set
926# CONFIG_VIDEO_HDPVR is not set 931# CONFIG_VIDEO_HDPVR is not set
927CONFIG_VIDEO_USBVIDEO=m 932CONFIG_VIDEO_USBVIDEO=m
@@ -994,15 +999,17 @@ CONFIG_USB_HID=m
994# 999#
995# Special HID drivers 1000# Special HID drivers
996# 1001#
997CONFIG_HID_COMPAT=y
998CONFIG_HID_A4TECH=m 1002CONFIG_HID_A4TECH=m
999CONFIG_HID_APPLE=m 1003CONFIG_HID_APPLE=m
1000CONFIG_HID_BELKIN=m 1004CONFIG_HID_BELKIN=m
1001CONFIG_HID_CHERRY=m 1005CONFIG_HID_CHERRY=m
1002CONFIG_HID_CHICONY=m 1006CONFIG_HID_CHICONY=m
1003CONFIG_HID_CYPRESS=m 1007CONFIG_HID_CYPRESS=m
1008# CONFIG_DRAGONRISE_FF is not set
1004CONFIG_HID_EZKEY=m 1009CONFIG_HID_EZKEY=m
1010# CONFIG_HID_KYE is not set
1005CONFIG_HID_GYRATION=m 1011CONFIG_HID_GYRATION=m
1012# CONFIG_HID_KENSINGTON is not set
1006CONFIG_HID_LOGITECH=m 1013CONFIG_HID_LOGITECH=m
1007# CONFIG_LOGITECH_FF is not set 1014# CONFIG_LOGITECH_FF is not set
1008# CONFIG_LOGIRUMBLEPAD2_FF is not set 1015# CONFIG_LOGIRUMBLEPAD2_FF is not set
@@ -1197,6 +1204,7 @@ CONFIG_EXT2_FS=y
1197# CONFIG_EXT2_FS_XATTR is not set 1204# CONFIG_EXT2_FS_XATTR is not set
1198# CONFIG_EXT2_FS_XIP is not set 1205# CONFIG_EXT2_FS_XIP is not set
1199CONFIG_EXT3_FS=y 1206CONFIG_EXT3_FS=y
1207# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1200CONFIG_EXT3_FS_XATTR=y 1208CONFIG_EXT3_FS_XATTR=y
1201# CONFIG_EXT3_FS_POSIX_ACL is not set 1209# CONFIG_EXT3_FS_POSIX_ACL is not set
1202# CONFIG_EXT3_FS_SECURITY is not set 1210# CONFIG_EXT3_FS_SECURITY is not set
@@ -1222,6 +1230,11 @@ CONFIG_INOTIFY_USER=y
1222# CONFIG_FUSE_FS is not set 1230# CONFIG_FUSE_FS is not set
1223 1231
1224# 1232#
1233# Caches
1234#
1235# CONFIG_FSCACHE is not set
1236
1237#
1225# CD-ROM/DVD Filesystems 1238# CD-ROM/DVD Filesystems
1226# 1239#
1227CONFIG_ISO9660_FS=m 1240CONFIG_ISO9660_FS=m
@@ -1270,10 +1283,15 @@ CONFIG_MISC_FILESYSTEMS=y
1270# CONFIG_HPFS_FS is not set 1283# CONFIG_HPFS_FS is not set
1271# CONFIG_QNX4FS_FS is not set 1284# CONFIG_QNX4FS_FS is not set
1272CONFIG_ROMFS_FS=y 1285CONFIG_ROMFS_FS=y
1286CONFIG_ROMFS_BACKED_BY_BLOCK=y
1287# CONFIG_ROMFS_BACKED_BY_MTD is not set
1288# CONFIG_ROMFS_BACKED_BY_BOTH is not set
1289CONFIG_ROMFS_ON_BLOCK=y
1273# CONFIG_SYSV_FS is not set 1290# CONFIG_SYSV_FS is not set
1274CONFIG_UFS_FS=m 1291CONFIG_UFS_FS=m
1275# CONFIG_UFS_FS_WRITE is not set 1292# CONFIG_UFS_FS_WRITE is not set
1276# CONFIG_UFS_DEBUG is not set 1293# CONFIG_UFS_DEBUG is not set
1294# CONFIG_NILFS2_FS is not set
1277CONFIG_NETWORK_FILESYSTEMS=y 1295CONFIG_NETWORK_FILESYSTEMS=y
1278CONFIG_NFS_FS=m 1296CONFIG_NFS_FS=m
1279CONFIG_NFS_V3=y 1297CONFIG_NFS_V3=y
@@ -1364,10 +1382,23 @@ CONFIG_FRAME_WARN=1024
1364CONFIG_HAVE_FUNCTION_TRACER=y 1382CONFIG_HAVE_FUNCTION_TRACER=y
1365CONFIG_HAVE_DYNAMIC_FTRACE=y 1383CONFIG_HAVE_DYNAMIC_FTRACE=y
1366CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1384CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1385CONFIG_TRACING_SUPPORT=y
1367 1386
1368# 1387#
1369# Tracers 1388# Tracers
1370# 1389#
1390# CONFIG_FUNCTION_TRACER is not set
1391# CONFIG_IRQSOFF_TRACER is not set
1392# CONFIG_SCHED_TRACER is not set
1393# CONFIG_CONTEXT_SWITCH_TRACER is not set
1394# CONFIG_EVENT_TRACER is not set
1395# CONFIG_BOOT_TRACER is not set
1396# CONFIG_TRACE_BRANCH_PROFILING is not set
1397# CONFIG_STACK_TRACER is not set
1398# CONFIG_KMEMTRACE is not set
1399# CONFIG_WORKQUEUE_TRACER is not set
1400# CONFIG_BLK_DEV_IO_TRACE is not set
1401# CONFIG_DMA_API_DEBUG is not set
1371# CONFIG_SAMPLES is not set 1402# CONFIG_SAMPLES is not set
1372CONFIG_HAVE_ARCH_KGDB=y 1403CONFIG_HAVE_ARCH_KGDB=y
1373CONFIG_SH_STANDARD_BIOS=y 1404CONFIG_SH_STANDARD_BIOS=y
@@ -1469,6 +1500,7 @@ CONFIG_CRYPTO=y
1469# CONFIG_CRYPTO_ANSI_CPRNG is not set 1500# CONFIG_CRYPTO_ANSI_CPRNG is not set
1470CONFIG_CRYPTO_HW=y 1501CONFIG_CRYPTO_HW=y
1471# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1502# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1503# CONFIG_BINARY_PRINTF is not set
1472 1504
1473# 1505#
1474# Library routines 1506# Library routines
diff --git a/arch/sh/configs/lboxre2_defconfig b/arch/sh/configs/lboxre2_defconfig
index 92c515c4199f..a7db539f2800 100644
--- a/arch/sh/configs/lboxre2_defconfig
+++ b/arch/sh/configs/lboxre2_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:06:51 2009 4# Mon Apr 27 12:48:54 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -69,6 +70,7 @@ CONFIG_UID16=y
69# CONFIG_SYSCTL_SYSCALL is not set 70# CONFIG_SYSCTL_SYSCALL is not set
70CONFIG_KALLSYMS=y 71CONFIG_KALLSYMS=y
71CONFIG_KALLSYMS_EXTRA_PASS=y 72CONFIG_KALLSYMS_EXTRA_PASS=y
73# CONFIG_STRIP_ASM_SYMS is not set
72CONFIG_HOTPLUG=y 74CONFIG_HOTPLUG=y
73CONFIG_PRINTK=y 75CONFIG_PRINTK=y
74CONFIG_BUG=y 76CONFIG_BUG=y
@@ -88,6 +90,7 @@ CONFIG_SLAB=y
88# CONFIG_SLUB is not set 90# CONFIG_SLUB is not set
89# CONFIG_SLOB is not set 91# CONFIG_SLOB is not set
90# CONFIG_PROFILING is not set 92# CONFIG_PROFILING is not set
93# CONFIG_MARKERS is not set
91CONFIG_HAVE_OPROFILE=y 94CONFIG_HAVE_OPROFILE=y
92# CONFIG_KPROBES is not set 95# CONFIG_KPROBES is not set
93CONFIG_HAVE_IOREMAP_PROT=y 96CONFIG_HAVE_IOREMAP_PROT=y
@@ -95,6 +98,8 @@ CONFIG_HAVE_KPROBES=y
95CONFIG_HAVE_KRETPROBES=y 98CONFIG_HAVE_KRETPROBES=y
96CONFIG_HAVE_ARCH_TRACEHOOK=y 99CONFIG_HAVE_ARCH_TRACEHOOK=y
97CONFIG_HAVE_CLK=y 100CONFIG_HAVE_CLK=y
101CONFIG_HAVE_DMA_API_DEBUG=y
102# CONFIG_SLOW_WORK is not set
98CONFIG_HAVE_GENERIC_DMA_COHERENT=y 103CONFIG_HAVE_GENERIC_DMA_COHERENT=y
99CONFIG_SLABINFO=y 104CONFIG_SLABINFO=y
100CONFIG_RT_MUTEXES=y 105CONFIG_RT_MUTEXES=y
@@ -107,7 +112,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y
107# CONFIG_MODULE_SRCVERSION_ALL is not set 112# CONFIG_MODULE_SRCVERSION_ALL is not set
108CONFIG_BLOCK=y 113CONFIG_BLOCK=y
109# CONFIG_LBD is not set 114# CONFIG_LBD is not set
110# CONFIG_BLK_DEV_IO_TRACE is not set
111# CONFIG_BLK_DEV_BSG is not set 115# CONFIG_BLK_DEV_BSG is not set
112# CONFIG_BLK_DEV_INTEGRITY is not set 116# CONFIG_BLK_DEV_INTEGRITY is not set
113 117
@@ -153,6 +157,7 @@ CONFIG_CPU_SUBTYPE_SH7751R=y
153# CONFIG_CPU_SUBTYPE_SH7760 is not set 157# CONFIG_CPU_SUBTYPE_SH7760 is not set
154# CONFIG_CPU_SUBTYPE_SH4_202 is not set 158# CONFIG_CPU_SUBTYPE_SH4_202 is not set
155# CONFIG_CPU_SUBTYPE_SH7723 is not set 159# CONFIG_CPU_SUBTYPE_SH7723 is not set
160# CONFIG_CPU_SUBTYPE_SH7724 is not set
156# CONFIG_CPU_SUBTYPE_SH7763 is not set 161# CONFIG_CPU_SUBTYPE_SH7763 is not set
157# CONFIG_CPU_SUBTYPE_SH7770 is not set 162# CONFIG_CPU_SUBTYPE_SH7770 is not set
158# CONFIG_CPU_SUBTYPE_SH7780 is not set 163# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -162,8 +167,6 @@ CONFIG_CPU_SUBTYPE_SH7751R=y
162# CONFIG_CPU_SUBTYPE_SH7343 is not set 167# CONFIG_CPU_SUBTYPE_SH7343 is not set
163# CONFIG_CPU_SUBTYPE_SH7722 is not set 168# CONFIG_CPU_SUBTYPE_SH7722 is not set
164# CONFIG_CPU_SUBTYPE_SH7366 is not set 169# CONFIG_CPU_SUBTYPE_SH7366 is not set
165# CONFIG_CPU_SUBTYPE_SH5_101 is not set
166# CONFIG_CPU_SUBTYPE_SH5_103 is not set
167 170
168# 171#
169# Memory management options 172# Memory management options
@@ -293,8 +296,6 @@ CONFIG_CMDLINE="console=ttySC1,115200 root=/dev/sda1"
293# 296#
294CONFIG_PCI=y 297CONFIG_PCI=y
295CONFIG_SH_PCIDMA_NONCOHERENT=y 298CONFIG_SH_PCIDMA_NONCOHERENT=y
296CONFIG_PCI_AUTO=y
297CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
298# CONFIG_PCIEPORTBUS is not set 299# CONFIG_PCIEPORTBUS is not set
299# CONFIG_ARCH_SUPPORTS_MSI is not set 300# CONFIG_ARCH_SUPPORTS_MSI is not set
300CONFIG_PCI_LEGACY=y 301CONFIG_PCI_LEGACY=y
@@ -542,6 +543,7 @@ CONFIG_SCSI_LOWLEVEL=y
542# CONFIG_SCSI_MPT2SAS is not set 543# CONFIG_SCSI_MPT2SAS is not set
543# CONFIG_SCSI_HPTIOP is not set 544# CONFIG_SCSI_HPTIOP is not set
544# CONFIG_LIBFC is not set 545# CONFIG_LIBFC is not set
546# CONFIG_LIBFCOE is not set
545# CONFIG_FCOE is not set 547# CONFIG_FCOE is not set
546# CONFIG_SCSI_DMX3191D is not set 548# CONFIG_SCSI_DMX3191D is not set
547# CONFIG_SCSI_FUTURE_DOMAIN is not set 549# CONFIG_SCSI_FUTURE_DOMAIN is not set
@@ -702,6 +704,7 @@ CONFIG_NETDEV_1000=y
702# CONFIG_E1000E is not set 704# CONFIG_E1000E is not set
703# CONFIG_IP1000 is not set 705# CONFIG_IP1000 is not set
704# CONFIG_IGB is not set 706# CONFIG_IGB is not set
707# CONFIG_IGBVF is not set
705# CONFIG_NS83820 is not set 708# CONFIG_NS83820 is not set
706# CONFIG_HAMACHI is not set 709# CONFIG_HAMACHI is not set
707# CONFIG_YELLOWFIN is not set 710# CONFIG_YELLOWFIN is not set
@@ -725,6 +728,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
725# CONFIG_IXGBE is not set 728# CONFIG_IXGBE is not set
726# CONFIG_IXGB is not set 729# CONFIG_IXGB is not set
727# CONFIG_S2IO is not set 730# CONFIG_S2IO is not set
731# CONFIG_VXGE is not set
728# CONFIG_MYRI10GE is not set 732# CONFIG_MYRI10GE is not set
729# CONFIG_NETXEN_NIC is not set 733# CONFIG_NETXEN_NIC is not set
730# CONFIG_NIU is not set 734# CONFIG_NIU is not set
@@ -931,7 +935,6 @@ CONFIG_HID=y
931# 935#
932# Special HID drivers 936# Special HID drivers
933# 937#
934CONFIG_HID_COMPAT=y
935CONFIG_USB_SUPPORT=y 938CONFIG_USB_SUPPORT=y
936CONFIG_USB_ARCH_HAS_HCD=y 939CONFIG_USB_ARCH_HAS_HCD=y
937CONFIG_USB_ARCH_HAS_OHCI=y 940CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1007,6 +1010,7 @@ CONFIG_EXT2_FS=y
1007# CONFIG_EXT2_FS_XATTR is not set 1010# CONFIG_EXT2_FS_XATTR is not set
1008# CONFIG_EXT2_FS_XIP is not set 1011# CONFIG_EXT2_FS_XIP is not set
1009CONFIG_EXT3_FS=y 1012CONFIG_EXT3_FS=y
1013# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1010CONFIG_EXT3_FS_XATTR=y 1014CONFIG_EXT3_FS_XATTR=y
1011# CONFIG_EXT3_FS_POSIX_ACL is not set 1015# CONFIG_EXT3_FS_POSIX_ACL is not set
1012# CONFIG_EXT3_FS_SECURITY is not set 1016# CONFIG_EXT3_FS_SECURITY is not set
@@ -1029,6 +1033,11 @@ CONFIG_INOTIFY_USER=y
1029# CONFIG_FUSE_FS is not set 1033# CONFIG_FUSE_FS is not set
1030 1034
1031# 1035#
1036# Caches
1037#
1038# CONFIG_FSCACHE is not set
1039
1040#
1032# CD-ROM/DVD Filesystems 1041# CD-ROM/DVD Filesystems
1033# 1042#
1034# CONFIG_ISO9660_FS is not set 1043# CONFIG_ISO9660_FS is not set
@@ -1073,8 +1082,13 @@ CONFIG_MISC_FILESYSTEMS=y
1073# CONFIG_HPFS_FS is not set 1082# CONFIG_HPFS_FS is not set
1074# CONFIG_QNX4FS_FS is not set 1083# CONFIG_QNX4FS_FS is not set
1075CONFIG_ROMFS_FS=y 1084CONFIG_ROMFS_FS=y
1085CONFIG_ROMFS_BACKED_BY_BLOCK=y
1086# CONFIG_ROMFS_BACKED_BY_MTD is not set
1087# CONFIG_ROMFS_BACKED_BY_BOTH is not set
1088CONFIG_ROMFS_ON_BLOCK=y
1076# CONFIG_SYSV_FS is not set 1089# CONFIG_SYSV_FS is not set
1077# CONFIG_UFS_FS is not set 1090# CONFIG_UFS_FS is not set
1091# CONFIG_NILFS2_FS is not set
1078CONFIG_NETWORK_FILESYSTEMS=y 1092CONFIG_NETWORK_FILESYSTEMS=y
1079# CONFIG_NFS_FS is not set 1093# CONFIG_NFS_FS is not set
1080# CONFIG_NFSD is not set 1094# CONFIG_NFSD is not set
@@ -1151,10 +1165,23 @@ CONFIG_FRAME_WARN=1024
1151CONFIG_HAVE_FUNCTION_TRACER=y 1165CONFIG_HAVE_FUNCTION_TRACER=y
1152CONFIG_HAVE_DYNAMIC_FTRACE=y 1166CONFIG_HAVE_DYNAMIC_FTRACE=y
1153CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1167CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1168CONFIG_TRACING_SUPPORT=y
1154 1169
1155# 1170#
1156# Tracers 1171# Tracers
1157# 1172#
1173# CONFIG_FUNCTION_TRACER is not set
1174# CONFIG_IRQSOFF_TRACER is not set
1175# CONFIG_SCHED_TRACER is not set
1176# CONFIG_CONTEXT_SWITCH_TRACER is not set
1177# CONFIG_EVENT_TRACER is not set
1178# CONFIG_BOOT_TRACER is not set
1179# CONFIG_TRACE_BRANCH_PROFILING is not set
1180# CONFIG_STACK_TRACER is not set
1181# CONFIG_KMEMTRACE is not set
1182# CONFIG_WORKQUEUE_TRACER is not set
1183# CONFIG_BLK_DEV_IO_TRACE is not set
1184# CONFIG_DMA_API_DEBUG is not set
1158# CONFIG_SAMPLES is not set 1185# CONFIG_SAMPLES is not set
1159CONFIG_HAVE_ARCH_KGDB=y 1186CONFIG_HAVE_ARCH_KGDB=y
1160CONFIG_SH_STANDARD_BIOS=y 1187CONFIG_SH_STANDARD_BIOS=y
@@ -1256,6 +1283,7 @@ CONFIG_CRYPTO=y
1256# CONFIG_CRYPTO_ANSI_CPRNG is not set 1283# CONFIG_CRYPTO_ANSI_CPRNG is not set
1257CONFIG_CRYPTO_HW=y 1284CONFIG_CRYPTO_HW=y
1258# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1285# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1286# CONFIG_BINARY_PRINTF is not set
1259 1287
1260# 1288#
1261# Library routines 1289# Library routines
diff --git a/arch/sh/configs/magicpanelr2_defconfig b/arch/sh/configs/magicpanelr2_defconfig
index 26586c2d64ca..58bec61506fa 100644
--- a/arch/sh/configs/magicpanelr2_defconfig
+++ b/arch/sh/configs/magicpanelr2_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:07:39 2009 4# Mon Apr 27 12:49:32 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -39,6 +40,7 @@ CONFIG_SWAP=y
39CONFIG_SYSVIPC=y 40CONFIG_SYSVIPC=y
40CONFIG_SYSVIPC_SYSCTL=y 41CONFIG_SYSVIPC_SYSCTL=y
41CONFIG_POSIX_MQUEUE=y 42CONFIG_POSIX_MQUEUE=y
43CONFIG_POSIX_MQUEUE_SYSCTL=y
42CONFIG_BSD_PROCESS_ACCT=y 44CONFIG_BSD_PROCESS_ACCT=y
43CONFIG_BSD_PROCESS_ACCT_V3=y 45CONFIG_BSD_PROCESS_ACCT_V3=y
44# CONFIG_TASKSTATS is not set 46# CONFIG_TASKSTATS is not set
@@ -66,7 +68,6 @@ CONFIG_INITRAMFS_SOURCE=""
66CONFIG_RD_GZIP=y 68CONFIG_RD_GZIP=y
67# CONFIG_RD_BZIP2 is not set 69# CONFIG_RD_BZIP2 is not set
68# CONFIG_RD_LZMA is not set 70# CONFIG_RD_LZMA is not set
69CONFIG_INITRAMFS_COMPRESSION_NONE=y
70# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 71# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
71CONFIG_SYSCTL=y 72CONFIG_SYSCTL=y
72CONFIG_ANON_INODES=y 73CONFIG_ANON_INODES=y
@@ -76,6 +77,7 @@ CONFIG_SYSCTL_SYSCALL=y
76CONFIG_KALLSYMS=y 77CONFIG_KALLSYMS=y
77CONFIG_KALLSYMS_ALL=y 78CONFIG_KALLSYMS_ALL=y
78# CONFIG_KALLSYMS_EXTRA_PASS is not set 79# CONFIG_KALLSYMS_EXTRA_PASS is not set
80# CONFIG_STRIP_ASM_SYMS is not set
79CONFIG_HOTPLUG=y 81CONFIG_HOTPLUG=y
80CONFIG_PRINTK=y 82CONFIG_PRINTK=y
81CONFIG_BUG=y 83CONFIG_BUG=y
@@ -94,6 +96,7 @@ CONFIG_SLAB=y
94# CONFIG_SLUB is not set 96# CONFIG_SLUB is not set
95# CONFIG_SLOB is not set 97# CONFIG_SLOB is not set
96# CONFIG_PROFILING is not set 98# CONFIG_PROFILING is not set
99# CONFIG_MARKERS is not set
97CONFIG_HAVE_OPROFILE=y 100CONFIG_HAVE_OPROFILE=y
98# CONFIG_KPROBES is not set 101# CONFIG_KPROBES is not set
99CONFIG_HAVE_IOREMAP_PROT=y 102CONFIG_HAVE_IOREMAP_PROT=y
@@ -101,6 +104,8 @@ CONFIG_HAVE_KPROBES=y
101CONFIG_HAVE_KRETPROBES=y 104CONFIG_HAVE_KRETPROBES=y
102CONFIG_HAVE_ARCH_TRACEHOOK=y 105CONFIG_HAVE_ARCH_TRACEHOOK=y
103CONFIG_HAVE_CLK=y 106CONFIG_HAVE_CLK=y
107CONFIG_HAVE_DMA_API_DEBUG=y
108# CONFIG_SLOW_WORK is not set
104CONFIG_HAVE_GENERIC_DMA_COHERENT=y 109CONFIG_HAVE_GENERIC_DMA_COHERENT=y
105CONFIG_SLABINFO=y 110CONFIG_SLABINFO=y
106CONFIG_RT_MUTEXES=y 111CONFIG_RT_MUTEXES=y
@@ -113,7 +118,6 @@ CONFIG_MODVERSIONS=y
113CONFIG_MODULE_SRCVERSION_ALL=y 118CONFIG_MODULE_SRCVERSION_ALL=y
114CONFIG_BLOCK=y 119CONFIG_BLOCK=y
115# CONFIG_LBD is not set 120# CONFIG_LBD is not set
116# CONFIG_BLK_DEV_IO_TRACE is not set
117# CONFIG_BLK_DEV_BSG is not set 121# CONFIG_BLK_DEV_BSG is not set
118# CONFIG_BLK_DEV_INTEGRITY is not set 122# CONFIG_BLK_DEV_INTEGRITY is not set
119 123
@@ -159,6 +163,7 @@ CONFIG_CPU_SUBTYPE_SH7720=y
159# CONFIG_CPU_SUBTYPE_SH7760 is not set 163# CONFIG_CPU_SUBTYPE_SH7760 is not set
160# CONFIG_CPU_SUBTYPE_SH4_202 is not set 164# CONFIG_CPU_SUBTYPE_SH4_202 is not set
161# CONFIG_CPU_SUBTYPE_SH7723 is not set 165# CONFIG_CPU_SUBTYPE_SH7723 is not set
166# CONFIG_CPU_SUBTYPE_SH7724 is not set
162# CONFIG_CPU_SUBTYPE_SH7763 is not set 167# CONFIG_CPU_SUBTYPE_SH7763 is not set
163# CONFIG_CPU_SUBTYPE_SH7770 is not set 168# CONFIG_CPU_SUBTYPE_SH7770 is not set
164# CONFIG_CPU_SUBTYPE_SH7780 is not set 169# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -168,8 +173,6 @@ CONFIG_CPU_SUBTYPE_SH7720=y
168# CONFIG_CPU_SUBTYPE_SH7343 is not set 173# CONFIG_CPU_SUBTYPE_SH7343 is not set
169# CONFIG_CPU_SUBTYPE_SH7722 is not set 174# CONFIG_CPU_SUBTYPE_SH7722 is not set
170# CONFIG_CPU_SUBTYPE_SH7366 is not set 175# CONFIG_CPU_SUBTYPE_SH7366 is not set
171# CONFIG_CPU_SUBTYPE_SH5_101 is not set
172# CONFIG_CPU_SUBTYPE_SH5_103 is not set
173 176
174# 177#
175# Memory management options 178# Memory management options
@@ -813,6 +816,7 @@ CONFIG_EXT2_FS=y
813# CONFIG_EXT2_FS_XATTR is not set 816# CONFIG_EXT2_FS_XATTR is not set
814# CONFIG_EXT2_FS_XIP is not set 817# CONFIG_EXT2_FS_XIP is not set
815CONFIG_EXT3_FS=y 818CONFIG_EXT3_FS=y
819# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
816# CONFIG_EXT3_FS_XATTR is not set 820# CONFIG_EXT3_FS_XATTR is not set
817# CONFIG_EXT4_FS is not set 821# CONFIG_EXT4_FS is not set
818CONFIG_JBD=y 822CONFIG_JBD=y
@@ -831,6 +835,11 @@ CONFIG_FILE_LOCKING=y
831# CONFIG_FUSE_FS is not set 835# CONFIG_FUSE_FS is not set
832 836
833# 837#
838# Caches
839#
840# CONFIG_FSCACHE is not set
841
842#
834# CD-ROM/DVD Filesystems 843# CD-ROM/DVD Filesystems
835# 844#
836# CONFIG_ISO9660_FS is not set 845# CONFIG_ISO9660_FS is not set
@@ -884,6 +893,7 @@ CONFIG_JFFS2_RTIME=y
884# CONFIG_ROMFS_FS is not set 893# CONFIG_ROMFS_FS is not set
885# CONFIG_SYSV_FS is not set 894# CONFIG_SYSV_FS is not set
886# CONFIG_UFS_FS is not set 895# CONFIG_UFS_FS is not set
896# CONFIG_NILFS2_FS is not set
887CONFIG_NETWORK_FILESYSTEMS=y 897CONFIG_NETWORK_FILESYSTEMS=y
888CONFIG_NFS_FS=y 898CONFIG_NFS_FS=y
889CONFIG_NFS_V3=y 899CONFIG_NFS_V3=y
@@ -965,6 +975,7 @@ CONFIG_MAGIC_SYSRQ=y
965CONFIG_DEBUG_KERNEL=y 975CONFIG_DEBUG_KERNEL=y
966# CONFIG_DEBUG_SHIRQ is not set 976# CONFIG_DEBUG_SHIRQ is not set
967# CONFIG_DETECT_SOFTLOCKUP is not set 977# CONFIG_DETECT_SOFTLOCKUP is not set
978# CONFIG_DETECT_HUNG_TASK is not set
968# CONFIG_SCHED_DEBUG is not set 979# CONFIG_SCHED_DEBUG is not set
969# CONFIG_SCHEDSTATS is not set 980# CONFIG_SCHEDSTATS is not set
970# CONFIG_TIMER_STATS is not set 981# CONFIG_TIMER_STATS is not set
@@ -1000,6 +1011,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
1000CONFIG_HAVE_FUNCTION_TRACER=y 1011CONFIG_HAVE_FUNCTION_TRACER=y
1001CONFIG_HAVE_DYNAMIC_FTRACE=y 1012CONFIG_HAVE_DYNAMIC_FTRACE=y
1002CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1013CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1014CONFIG_TRACING_SUPPORT=y
1003 1015
1004# 1016#
1005# Tracers 1017# Tracers
@@ -1008,9 +1020,14 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1008# CONFIG_IRQSOFF_TRACER is not set 1020# CONFIG_IRQSOFF_TRACER is not set
1009# CONFIG_SCHED_TRACER is not set 1021# CONFIG_SCHED_TRACER is not set
1010# CONFIG_CONTEXT_SWITCH_TRACER is not set 1022# CONFIG_CONTEXT_SWITCH_TRACER is not set
1023# CONFIG_EVENT_TRACER is not set
1011# CONFIG_BOOT_TRACER is not set 1024# CONFIG_BOOT_TRACER is not set
1012# CONFIG_TRACE_BRANCH_PROFILING is not set 1025# CONFIG_TRACE_BRANCH_PROFILING is not set
1013# CONFIG_STACK_TRACER is not set 1026# CONFIG_STACK_TRACER is not set
1027# CONFIG_KMEMTRACE is not set
1028# CONFIG_WORKQUEUE_TRACER is not set
1029# CONFIG_BLK_DEV_IO_TRACE is not set
1030# CONFIG_DMA_API_DEBUG is not set
1014# CONFIG_SAMPLES is not set 1031# CONFIG_SAMPLES is not set
1015CONFIG_HAVE_ARCH_KGDB=y 1032CONFIG_HAVE_ARCH_KGDB=y
1016# CONFIG_KGDB is not set 1033# CONFIG_KGDB is not set
@@ -1035,6 +1052,7 @@ CONFIG_DUMP_CODE=y
1035# CONFIG_SECURITYFS is not set 1052# CONFIG_SECURITYFS is not set
1036# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1053# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1037# CONFIG_CRYPTO is not set 1054# CONFIG_CRYPTO is not set
1055# CONFIG_BINARY_PRINTF is not set
1038 1056
1039# 1057#
1040# Library routines 1058# Library routines
diff --git a/arch/sh/configs/microdev_defconfig b/arch/sh/configs/microdev_defconfig
index 75178355d69a..2886fc84bc1c 100644
--- a/arch/sh/configs/microdev_defconfig
+++ b/arch/sh/configs/microdev_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:11:13 2009 4# Mon Apr 27 12:50:51 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -65,7 +66,6 @@ CONFIG_INITRAMFS_SOURCE=""
65CONFIG_RD_GZIP=y 66CONFIG_RD_GZIP=y
66# CONFIG_RD_BZIP2 is not set 67# CONFIG_RD_BZIP2 is not set
67# CONFIG_RD_LZMA is not set 68# CONFIG_RD_LZMA is not set
68CONFIG_INITRAMFS_COMPRESSION_NONE=y
69# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 69# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
70CONFIG_SYSCTL=y 70CONFIG_SYSCTL=y
71CONFIG_ANON_INODES=y 71CONFIG_ANON_INODES=y
@@ -74,6 +74,7 @@ CONFIG_UID16=y
74# CONFIG_SYSCTL_SYSCALL is not set 74# CONFIG_SYSCTL_SYSCALL is not set
75CONFIG_KALLSYMS=y 75CONFIG_KALLSYMS=y
76# CONFIG_KALLSYMS_EXTRA_PASS is not set 76# CONFIG_KALLSYMS_EXTRA_PASS is not set
77# CONFIG_STRIP_ASM_SYMS is not set
77CONFIG_HOTPLUG=y 78CONFIG_HOTPLUG=y
78CONFIG_PRINTK=y 79CONFIG_PRINTK=y
79CONFIG_BUG=y 80CONFIG_BUG=y
@@ -92,12 +93,15 @@ CONFIG_SLAB=y
92# CONFIG_SLUB is not set 93# CONFIG_SLUB is not set
93# CONFIG_SLOB is not set 94# CONFIG_SLOB is not set
94# CONFIG_PROFILING is not set 95# CONFIG_PROFILING is not set
96# CONFIG_MARKERS is not set
95CONFIG_HAVE_OPROFILE=y 97CONFIG_HAVE_OPROFILE=y
96CONFIG_HAVE_IOREMAP_PROT=y 98CONFIG_HAVE_IOREMAP_PROT=y
97CONFIG_HAVE_KPROBES=y 99CONFIG_HAVE_KPROBES=y
98CONFIG_HAVE_KRETPROBES=y 100CONFIG_HAVE_KRETPROBES=y
99CONFIG_HAVE_ARCH_TRACEHOOK=y 101CONFIG_HAVE_ARCH_TRACEHOOK=y
100CONFIG_HAVE_CLK=y 102CONFIG_HAVE_CLK=y
103CONFIG_HAVE_DMA_API_DEBUG=y
104# CONFIG_SLOW_WORK is not set
101CONFIG_HAVE_GENERIC_DMA_COHERENT=y 105CONFIG_HAVE_GENERIC_DMA_COHERENT=y
102CONFIG_SLABINFO=y 106CONFIG_SLABINFO=y
103CONFIG_RT_MUTEXES=y 107CONFIG_RT_MUTEXES=y
@@ -105,7 +109,6 @@ CONFIG_BASE_SMALL=0
105# CONFIG_MODULES is not set 109# CONFIG_MODULES is not set
106CONFIG_BLOCK=y 110CONFIG_BLOCK=y
107# CONFIG_LBD is not set 111# CONFIG_LBD is not set
108# CONFIG_BLK_DEV_IO_TRACE is not set
109# CONFIG_BLK_DEV_BSG is not set 112# CONFIG_BLK_DEV_BSG is not set
110# CONFIG_BLK_DEV_INTEGRITY is not set 113# CONFIG_BLK_DEV_INTEGRITY is not set
111 114
@@ -151,6 +154,7 @@ CONFIG_CPU_SH4=y
151# CONFIG_CPU_SUBTYPE_SH7760 is not set 154# CONFIG_CPU_SUBTYPE_SH7760 is not set
152CONFIG_CPU_SUBTYPE_SH4_202=y 155CONFIG_CPU_SUBTYPE_SH4_202=y
153# CONFIG_CPU_SUBTYPE_SH7723 is not set 156# CONFIG_CPU_SUBTYPE_SH7723 is not set
157# CONFIG_CPU_SUBTYPE_SH7724 is not set
154# CONFIG_CPU_SUBTYPE_SH7763 is not set 158# CONFIG_CPU_SUBTYPE_SH7763 is not set
155# CONFIG_CPU_SUBTYPE_SH7770 is not set 159# CONFIG_CPU_SUBTYPE_SH7770 is not set
156# CONFIG_CPU_SUBTYPE_SH7780 is not set 160# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -160,8 +164,6 @@ CONFIG_CPU_SUBTYPE_SH4_202=y
160# CONFIG_CPU_SUBTYPE_SH7343 is not set 164# CONFIG_CPU_SUBTYPE_SH7343 is not set
161# CONFIG_CPU_SUBTYPE_SH7722 is not set 165# CONFIG_CPU_SUBTYPE_SH7722 is not set
162# CONFIG_CPU_SUBTYPE_SH7366 is not set 166# CONFIG_CPU_SUBTYPE_SH7366 is not set
163# CONFIG_CPU_SUBTYPE_SH5_101 is not set
164# CONFIG_CPU_SUBTYPE_SH5_103 is not set
165 167
166# 168#
167# Memory management options 169# Memory management options
@@ -647,6 +649,7 @@ CONFIG_EXT2_FS=y
647# CONFIG_EXT2_FS_XATTR is not set 649# CONFIG_EXT2_FS_XATTR is not set
648# CONFIG_EXT2_FS_XIP is not set 650# CONFIG_EXT2_FS_XIP is not set
649CONFIG_EXT3_FS=y 651CONFIG_EXT3_FS=y
652# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
650CONFIG_EXT3_FS_XATTR=y 653CONFIG_EXT3_FS_XATTR=y
651# CONFIG_EXT3_FS_POSIX_ACL is not set 654# CONFIG_EXT3_FS_POSIX_ACL is not set
652# CONFIG_EXT3_FS_SECURITY is not set 655# CONFIG_EXT3_FS_SECURITY is not set
@@ -669,6 +672,11 @@ CONFIG_INOTIFY_USER=y
669# CONFIG_FUSE_FS is not set 672# CONFIG_FUSE_FS is not set
670 673
671# 674#
675# Caches
676#
677# CONFIG_FSCACHE is not set
678
679#
672# CD-ROM/DVD Filesystems 680# CD-ROM/DVD Filesystems
673# 681#
674# CONFIG_ISO9660_FS is not set 682# CONFIG_ISO9660_FS is not set
@@ -715,6 +723,7 @@ CONFIG_MISC_FILESYSTEMS=y
715# CONFIG_ROMFS_FS is not set 723# CONFIG_ROMFS_FS is not set
716# CONFIG_SYSV_FS is not set 724# CONFIG_SYSV_FS is not set
717# CONFIG_UFS_FS is not set 725# CONFIG_UFS_FS is not set
726# CONFIG_NILFS2_FS is not set
718CONFIG_NETWORK_FILESYSTEMS=y 727CONFIG_NETWORK_FILESYSTEMS=y
719CONFIG_NFS_FS=y 728CONFIG_NFS_FS=y
720CONFIG_NFS_V3=y 729CONFIG_NFS_V3=y
@@ -802,10 +811,24 @@ CONFIG_FRAME_WARN=1024
802CONFIG_HAVE_FUNCTION_TRACER=y 811CONFIG_HAVE_FUNCTION_TRACER=y
803CONFIG_HAVE_DYNAMIC_FTRACE=y 812CONFIG_HAVE_DYNAMIC_FTRACE=y
804CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 813CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
814CONFIG_TRACING_SUPPORT=y
805 815
806# 816#
807# Tracers 817# Tracers
808# 818#
819# CONFIG_FUNCTION_TRACER is not set
820# CONFIG_IRQSOFF_TRACER is not set
821# CONFIG_PREEMPT_TRACER is not set
822# CONFIG_SCHED_TRACER is not set
823# CONFIG_CONTEXT_SWITCH_TRACER is not set
824# CONFIG_EVENT_TRACER is not set
825# CONFIG_BOOT_TRACER is not set
826# CONFIG_TRACE_BRANCH_PROFILING is not set
827# CONFIG_STACK_TRACER is not set
828# CONFIG_KMEMTRACE is not set
829# CONFIG_WORKQUEUE_TRACER is not set
830# CONFIG_BLK_DEV_IO_TRACE is not set
831# CONFIG_DMA_API_DEBUG is not set
809# CONFIG_SAMPLES is not set 832# CONFIG_SAMPLES is not set
810CONFIG_HAVE_ARCH_KGDB=y 833CONFIG_HAVE_ARCH_KGDB=y
811# CONFIG_SH_STANDARD_BIOS is not set 834# CONFIG_SH_STANDARD_BIOS is not set
@@ -914,6 +937,7 @@ CONFIG_CRYPTO_DES=y
914# 937#
915# CONFIG_CRYPTO_ANSI_CPRNG is not set 938# CONFIG_CRYPTO_ANSI_CPRNG is not set
916CONFIG_CRYPTO_HW=y 939CONFIG_CRYPTO_HW=y
940# CONFIG_BINARY_PRINTF is not set
917 941
918# 942#
919# Library routines 943# Library routines
diff --git a/arch/sh/configs/migor_defconfig b/arch/sh/configs/migor_defconfig
index a8720f9c6047..8ecceb4bf27e 100644
--- a/arch/sh/configs/migor_defconfig
+++ b/arch/sh/configs/migor_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:14:03 2009 4# Mon Apr 27 12:51:34 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -67,7 +68,6 @@ CONFIG_INITRAMFS_SOURCE=""
67CONFIG_RD_GZIP=y 68CONFIG_RD_GZIP=y
68# CONFIG_RD_BZIP2 is not set 69# CONFIG_RD_BZIP2 is not set
69# CONFIG_RD_LZMA is not set 70# CONFIG_RD_LZMA is not set
70CONFIG_INITRAMFS_COMPRESSION_NONE=y
71# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 71# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
72CONFIG_SYSCTL=y 72CONFIG_SYSCTL=y
73CONFIG_ANON_INODES=y 73CONFIG_ANON_INODES=y
@@ -76,6 +76,7 @@ CONFIG_UID16=y
76# CONFIG_SYSCTL_SYSCALL is not set 76# CONFIG_SYSCTL_SYSCALL is not set
77CONFIG_KALLSYMS=y 77CONFIG_KALLSYMS=y
78# CONFIG_KALLSYMS_EXTRA_PASS is not set 78# CONFIG_KALLSYMS_EXTRA_PASS is not set
79# CONFIG_STRIP_ASM_SYMS is not set
79CONFIG_HOTPLUG=y 80CONFIG_HOTPLUG=y
80CONFIG_PRINTK=y 81CONFIG_PRINTK=y
81CONFIG_BUG=y 82CONFIG_BUG=y
@@ -104,6 +105,8 @@ CONFIG_HAVE_KPROBES=y
104CONFIG_HAVE_KRETPROBES=y 105CONFIG_HAVE_KRETPROBES=y
105CONFIG_HAVE_ARCH_TRACEHOOK=y 106CONFIG_HAVE_ARCH_TRACEHOOK=y
106CONFIG_HAVE_CLK=y 107CONFIG_HAVE_CLK=y
108CONFIG_HAVE_DMA_API_DEBUG=y
109# CONFIG_SLOW_WORK is not set
107CONFIG_HAVE_GENERIC_DMA_COHERENT=y 110CONFIG_HAVE_GENERIC_DMA_COHERENT=y
108CONFIG_SLABINFO=y 111CONFIG_SLABINFO=y
109CONFIG_RT_MUTEXES=y 112CONFIG_RT_MUTEXES=y
@@ -115,7 +118,6 @@ CONFIG_MODULES=y
115# CONFIG_MODULE_SRCVERSION_ALL is not set 118# CONFIG_MODULE_SRCVERSION_ALL is not set
116CONFIG_BLOCK=y 119CONFIG_BLOCK=y
117# CONFIG_LBD is not set 120# CONFIG_LBD is not set
118# CONFIG_BLK_DEV_IO_TRACE is not set
119# CONFIG_BLK_DEV_BSG is not set 121# CONFIG_BLK_DEV_BSG is not set
120# CONFIG_BLK_DEV_INTEGRITY is not set 122# CONFIG_BLK_DEV_INTEGRITY is not set
121 123
@@ -165,6 +167,7 @@ CONFIG_ARCH_SHMOBILE=y
165# CONFIG_CPU_SUBTYPE_SH7760 is not set 167# CONFIG_CPU_SUBTYPE_SH7760 is not set
166# CONFIG_CPU_SUBTYPE_SH4_202 is not set 168# CONFIG_CPU_SUBTYPE_SH4_202 is not set
167# CONFIG_CPU_SUBTYPE_SH7723 is not set 169# CONFIG_CPU_SUBTYPE_SH7723 is not set
170# CONFIG_CPU_SUBTYPE_SH7724 is not set
168# CONFIG_CPU_SUBTYPE_SH7763 is not set 171# CONFIG_CPU_SUBTYPE_SH7763 is not set
169# CONFIG_CPU_SUBTYPE_SH7770 is not set 172# CONFIG_CPU_SUBTYPE_SH7770 is not set
170# CONFIG_CPU_SUBTYPE_SH7780 is not set 173# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -174,8 +177,6 @@ CONFIG_ARCH_SHMOBILE=y
174# CONFIG_CPU_SUBTYPE_SH7343 is not set 177# CONFIG_CPU_SUBTYPE_SH7343 is not set
175CONFIG_CPU_SUBTYPE_SH7722=y 178CONFIG_CPU_SUBTYPE_SH7722=y
176# CONFIG_CPU_SUBTYPE_SH7366 is not set 179# CONFIG_CPU_SUBTYPE_SH7366 is not set
177# CONFIG_CPU_SUBTYPE_SH5_101 is not set
178# CONFIG_CPU_SUBTYPE_SH5_103 is not set
179 180
180# 181#
181# Memory management options 182# Memory management options
@@ -577,6 +578,7 @@ CONFIG_SCSI_WAIT_SCAN=m
577CONFIG_SCSI_LOWLEVEL=y 578CONFIG_SCSI_LOWLEVEL=y
578# CONFIG_ISCSI_TCP is not set 579# CONFIG_ISCSI_TCP is not set
579# CONFIG_LIBFC is not set 580# CONFIG_LIBFC is not set
581# CONFIG_LIBFCOE is not set
580# CONFIG_SCSI_DEBUG is not set 582# CONFIG_SCSI_DEBUG is not set
581# CONFIG_SCSI_DH is not set 583# CONFIG_SCSI_DH is not set
582# CONFIG_SCSI_OSD_INITIATOR is not set 584# CONFIG_SCSI_OSD_INITIATOR is not set
@@ -873,7 +875,6 @@ CONFIG_HID=y
873# 875#
874# Special HID drivers 876# Special HID drivers
875# 877#
876CONFIG_HID_COMPAT=y
877CONFIG_USB_SUPPORT=y 878CONFIG_USB_SUPPORT=y
878CONFIG_USB_ARCH_HAS_HCD=y 879CONFIG_USB_ARCH_HAS_HCD=y
879# CONFIG_USB_ARCH_HAS_OHCI is not set 880# CONFIG_USB_ARCH_HAS_OHCI is not set
@@ -1012,6 +1013,11 @@ CONFIG_FILE_LOCKING=y
1012# CONFIG_FUSE_FS is not set 1013# CONFIG_FUSE_FS is not set
1013 1014
1014# 1015#
1016# Caches
1017#
1018# CONFIG_FSCACHE is not set
1019
1020#
1015# CD-ROM/DVD Filesystems 1021# CD-ROM/DVD Filesystems
1016# 1022#
1017# CONFIG_ISO9660_FS is not set 1023# CONFIG_ISO9660_FS is not set
@@ -1056,6 +1062,7 @@ CONFIG_MISC_FILESYSTEMS=y
1056# CONFIG_ROMFS_FS is not set 1062# CONFIG_ROMFS_FS is not set
1057# CONFIG_SYSV_FS is not set 1063# CONFIG_SYSV_FS is not set
1058# CONFIG_UFS_FS is not set 1064# CONFIG_UFS_FS is not set
1065# CONFIG_NILFS2_FS is not set
1059CONFIG_NETWORK_FILESYSTEMS=y 1066CONFIG_NETWORK_FILESYSTEMS=y
1060CONFIG_NFS_FS=y 1067CONFIG_NFS_FS=y
1061# CONFIG_NFS_V3 is not set 1068# CONFIG_NFS_V3 is not set
@@ -1105,11 +1112,25 @@ CONFIG_HAVE_DYNAMIC_FTRACE=y
1105CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1112CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1106CONFIG_RING_BUFFER=y 1113CONFIG_RING_BUFFER=y
1107CONFIG_TRACING=y 1114CONFIG_TRACING=y
1115CONFIG_TRACING_SUPPORT=y
1108 1116
1109# 1117#
1110# Tracers 1118# Tracers
1111# 1119#
1120# CONFIG_FUNCTION_TRACER is not set
1121# CONFIG_IRQSOFF_TRACER is not set
1122# CONFIG_SCHED_TRACER is not set
1123# CONFIG_CONTEXT_SWITCH_TRACER is not set
1124# CONFIG_EVENT_TRACER is not set
1125# CONFIG_BOOT_TRACER is not set
1126# CONFIG_TRACE_BRANCH_PROFILING is not set
1127# CONFIG_STACK_TRACER is not set
1128# CONFIG_KMEMTRACE is not set
1129# CONFIG_WORKQUEUE_TRACER is not set
1130# CONFIG_BLK_DEV_IO_TRACE is not set
1131# CONFIG_FTRACE_STARTUP_TEST is not set
1112# CONFIG_DYNAMIC_DEBUG is not set 1132# CONFIG_DYNAMIC_DEBUG is not set
1133# CONFIG_DMA_API_DEBUG is not set
1113# CONFIG_SAMPLES is not set 1134# CONFIG_SAMPLES is not set
1114CONFIG_HAVE_ARCH_KGDB=y 1135CONFIG_HAVE_ARCH_KGDB=y
1115# CONFIG_SH_STANDARD_BIOS is not set 1136# CONFIG_SH_STANDARD_BIOS is not set
@@ -1218,6 +1239,7 @@ CONFIG_CRYPTO_WORKQUEUE=y
1218# 1239#
1219# CONFIG_CRYPTO_ANSI_CPRNG is not set 1240# CONFIG_CRYPTO_ANSI_CPRNG is not set
1220# CONFIG_CRYPTO_HW is not set 1241# CONFIG_CRYPTO_HW is not set
1242CONFIG_BINARY_PRINTF=y
1221 1243
1222# 1244#
1223# Library routines 1245# Library routines
diff --git a/arch/sh/configs/polaris_defconfig b/arch/sh/configs/polaris_defconfig
index df2d177d5346..2b9507286182 100644
--- a/arch/sh/configs/polaris_defconfig
+++ b/arch/sh/configs/polaris_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:16:48 2009 4# Mon Apr 27 12:52:19 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -40,6 +41,7 @@ CONFIG_LOCALVERSION=""
40CONFIG_SYSVIPC=y 41CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y 42CONFIG_SYSVIPC_SYSCTL=y
42CONFIG_POSIX_MQUEUE=y 43CONFIG_POSIX_MQUEUE=y
44CONFIG_POSIX_MQUEUE_SYSCTL=y
43CONFIG_BSD_PROCESS_ACCT=y 45CONFIG_BSD_PROCESS_ACCT=y
44CONFIG_BSD_PROCESS_ACCT_V3=y 46CONFIG_BSD_PROCESS_ACCT_V3=y
45# CONFIG_TASKSTATS is not set 47# CONFIG_TASKSTATS is not set
@@ -76,6 +78,7 @@ CONFIG_SYSCTL_SYSCALL=y
76CONFIG_KALLSYMS=y 78CONFIG_KALLSYMS=y
77CONFIG_KALLSYMS_ALL=y 79CONFIG_KALLSYMS_ALL=y
78# CONFIG_KALLSYMS_EXTRA_PASS is not set 80# CONFIG_KALLSYMS_EXTRA_PASS is not set
81# CONFIG_STRIP_ASM_SYMS is not set
79CONFIG_HOTPLUG=y 82CONFIG_HOTPLUG=y
80CONFIG_PRINTK=y 83CONFIG_PRINTK=y
81CONFIG_BUG=y 84CONFIG_BUG=y
@@ -94,6 +97,7 @@ CONFIG_SLAB=y
94# CONFIG_SLUB is not set 97# CONFIG_SLUB is not set
95# CONFIG_SLOB is not set 98# CONFIG_SLOB is not set
96# CONFIG_PROFILING is not set 99# CONFIG_PROFILING is not set
100# CONFIG_MARKERS is not set
97CONFIG_HAVE_OPROFILE=y 101CONFIG_HAVE_OPROFILE=y
98# CONFIG_KPROBES is not set 102# CONFIG_KPROBES is not set
99CONFIG_HAVE_IOREMAP_PROT=y 103CONFIG_HAVE_IOREMAP_PROT=y
@@ -101,6 +105,8 @@ CONFIG_HAVE_KPROBES=y
101CONFIG_HAVE_KRETPROBES=y 105CONFIG_HAVE_KRETPROBES=y
102CONFIG_HAVE_ARCH_TRACEHOOK=y 106CONFIG_HAVE_ARCH_TRACEHOOK=y
103CONFIG_HAVE_CLK=y 107CONFIG_HAVE_CLK=y
108CONFIG_HAVE_DMA_API_DEBUG=y
109# CONFIG_SLOW_WORK is not set
104CONFIG_HAVE_GENERIC_DMA_COHERENT=y 110CONFIG_HAVE_GENERIC_DMA_COHERENT=y
105CONFIG_SLABINFO=y 111CONFIG_SLABINFO=y
106CONFIG_RT_MUTEXES=y 112CONFIG_RT_MUTEXES=y
@@ -113,7 +119,6 @@ CONFIG_MODVERSIONS=y
113# CONFIG_MODULE_SRCVERSION_ALL is not set 119# CONFIG_MODULE_SRCVERSION_ALL is not set
114CONFIG_BLOCK=y 120CONFIG_BLOCK=y
115# CONFIG_LBD is not set 121# CONFIG_LBD is not set
116# CONFIG_BLK_DEV_IO_TRACE is not set
117# CONFIG_BLK_DEV_BSG is not set 122# CONFIG_BLK_DEV_BSG is not set
118# CONFIG_BLK_DEV_INTEGRITY is not set 123# CONFIG_BLK_DEV_INTEGRITY is not set
119 124
@@ -159,6 +164,7 @@ CONFIG_CPU_SUBTYPE_SH7709=y
159# CONFIG_CPU_SUBTYPE_SH7760 is not set 164# CONFIG_CPU_SUBTYPE_SH7760 is not set
160# CONFIG_CPU_SUBTYPE_SH4_202 is not set 165# CONFIG_CPU_SUBTYPE_SH4_202 is not set
161# CONFIG_CPU_SUBTYPE_SH7723 is not set 166# CONFIG_CPU_SUBTYPE_SH7723 is not set
167# CONFIG_CPU_SUBTYPE_SH7724 is not set
162# CONFIG_CPU_SUBTYPE_SH7763 is not set 168# CONFIG_CPU_SUBTYPE_SH7763 is not set
163# CONFIG_CPU_SUBTYPE_SH7770 is not set 169# CONFIG_CPU_SUBTYPE_SH7770 is not set
164# CONFIG_CPU_SUBTYPE_SH7780 is not set 170# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -168,8 +174,6 @@ CONFIG_CPU_SUBTYPE_SH7709=y
168# CONFIG_CPU_SUBTYPE_SH7343 is not set 174# CONFIG_CPU_SUBTYPE_SH7343 is not set
169# CONFIG_CPU_SUBTYPE_SH7722 is not set 175# CONFIG_CPU_SUBTYPE_SH7722 is not set
170# CONFIG_CPU_SUBTYPE_SH7366 is not set 176# CONFIG_CPU_SUBTYPE_SH7366 is not set
171# CONFIG_CPU_SUBTYPE_SH5_101 is not set
172# CONFIG_CPU_SUBTYPE_SH5_103 is not set
173 177
174# 178#
175# Memory management options 179# Memory management options
@@ -778,6 +782,11 @@ CONFIG_FILE_LOCKING=y
778# CONFIG_FUSE_FS is not set 782# CONFIG_FUSE_FS is not set
779 783
780# 784#
785# Caches
786#
787# CONFIG_FSCACHE is not set
788
789#
781# CD-ROM/DVD Filesystems 790# CD-ROM/DVD Filesystems
782# 791#
783# CONFIG_ISO9660_FS is not set 792# CONFIG_ISO9660_FS is not set
@@ -831,6 +840,7 @@ CONFIG_JFFS2_RTIME=y
831# CONFIG_ROMFS_FS is not set 840# CONFIG_ROMFS_FS is not set
832# CONFIG_SYSV_FS is not set 841# CONFIG_SYSV_FS is not set
833# CONFIG_UFS_FS is not set 842# CONFIG_UFS_FS is not set
843# CONFIG_NILFS2_FS is not set
834CONFIG_NETWORK_FILESYSTEMS=y 844CONFIG_NETWORK_FILESYSTEMS=y
835CONFIG_NFS_FS=y 845CONFIG_NFS_FS=y
836CONFIG_NFS_V3=y 846CONFIG_NFS_V3=y
@@ -874,6 +884,9 @@ CONFIG_DEBUG_SHIRQ=y
874CONFIG_DETECT_SOFTLOCKUP=y 884CONFIG_DETECT_SOFTLOCKUP=y
875# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set 885# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
876CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 886CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
887CONFIG_DETECT_HUNG_TASK=y
888# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
889CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
877# CONFIG_SCHED_DEBUG is not set 890# CONFIG_SCHED_DEBUG is not set
878# CONFIG_SCHEDSTATS is not set 891# CONFIG_SCHEDSTATS is not set
879# CONFIG_TIMER_STATS is not set 892# CONFIG_TIMER_STATS is not set
@@ -914,6 +927,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
914CONFIG_HAVE_FUNCTION_TRACER=y 927CONFIG_HAVE_FUNCTION_TRACER=y
915CONFIG_HAVE_DYNAMIC_FTRACE=y 928CONFIG_HAVE_DYNAMIC_FTRACE=y
916CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 929CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
930CONFIG_TRACING_SUPPORT=y
917 931
918# 932#
919# Tracers 933# Tracers
@@ -923,9 +937,14 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
923# CONFIG_PREEMPT_TRACER is not set 937# CONFIG_PREEMPT_TRACER is not set
924# CONFIG_SCHED_TRACER is not set 938# CONFIG_SCHED_TRACER is not set
925# CONFIG_CONTEXT_SWITCH_TRACER is not set 939# CONFIG_CONTEXT_SWITCH_TRACER is not set
940# CONFIG_EVENT_TRACER is not set
926# CONFIG_BOOT_TRACER is not set 941# CONFIG_BOOT_TRACER is not set
927# CONFIG_TRACE_BRANCH_PROFILING is not set 942# CONFIG_TRACE_BRANCH_PROFILING is not set
928# CONFIG_STACK_TRACER is not set 943# CONFIG_STACK_TRACER is not set
944# CONFIG_KMEMTRACE is not set
945# CONFIG_WORKQUEUE_TRACER is not set
946# CONFIG_BLK_DEV_IO_TRACE is not set
947# CONFIG_DMA_API_DEBUG is not set
929# CONFIG_SAMPLES is not set 948# CONFIG_SAMPLES is not set
930CONFIG_HAVE_ARCH_KGDB=y 949CONFIG_HAVE_ARCH_KGDB=y
931# CONFIG_KGDB is not set 950# CONFIG_KGDB is not set
@@ -950,6 +969,7 @@ CONFIG_DUMP_CODE=y
950# CONFIG_SECURITYFS is not set 969# CONFIG_SECURITYFS is not set
951# CONFIG_SECURITY_FILE_CAPABILITIES is not set 970# CONFIG_SECURITY_FILE_CAPABILITIES is not set
952# CONFIG_CRYPTO is not set 971# CONFIG_CRYPTO is not set
972# CONFIG_BINARY_PRINTF is not set
953 973
954# 974#
955# Library routines 975# Library routines
diff --git a/arch/sh/configs/r7780mp_defconfig b/arch/sh/configs/r7780mp_defconfig
index 7def4df46ddb..943da63a3852 100644
--- a/arch/sh/configs/r7780mp_defconfig
+++ b/arch/sh/configs/r7780mp_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:20:17 2009 4# Mon Apr 27 12:53:28 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -78,6 +79,7 @@ CONFIG_UID16=y
78CONFIG_KALLSYMS=y 79CONFIG_KALLSYMS=y
79# CONFIG_KALLSYMS_ALL is not set 80# CONFIG_KALLSYMS_ALL is not set
80# CONFIG_KALLSYMS_EXTRA_PASS is not set 81# CONFIG_KALLSYMS_EXTRA_PASS is not set
82# CONFIG_STRIP_ASM_SYMS is not set
81CONFIG_HOTPLUG=y 83CONFIG_HOTPLUG=y
82CONFIG_PRINTK=y 84CONFIG_PRINTK=y
83CONFIG_BUG=y 85CONFIG_BUG=y
@@ -107,6 +109,8 @@ CONFIG_HAVE_KPROBES=y
107CONFIG_HAVE_KRETPROBES=y 109CONFIG_HAVE_KRETPROBES=y
108CONFIG_HAVE_ARCH_TRACEHOOK=y 110CONFIG_HAVE_ARCH_TRACEHOOK=y
109CONFIG_HAVE_CLK=y 111CONFIG_HAVE_CLK=y
112CONFIG_HAVE_DMA_API_DEBUG=y
113# CONFIG_SLOW_WORK is not set
110CONFIG_HAVE_GENERIC_DMA_COHERENT=y 114CONFIG_HAVE_GENERIC_DMA_COHERENT=y
111CONFIG_SLABINFO=y 115CONFIG_SLABINFO=y
112CONFIG_BASE_SMALL=0 116CONFIG_BASE_SMALL=0
@@ -118,7 +122,6 @@ CONFIG_MODULE_UNLOAD=y
118# CONFIG_MODULE_SRCVERSION_ALL is not set 122# CONFIG_MODULE_SRCVERSION_ALL is not set
119CONFIG_BLOCK=y 123CONFIG_BLOCK=y
120# CONFIG_LBD is not set 124# CONFIG_LBD is not set
121# CONFIG_BLK_DEV_IO_TRACE is not set
122# CONFIG_BLK_DEV_BSG is not set 125# CONFIG_BLK_DEV_BSG is not set
123# CONFIG_BLK_DEV_INTEGRITY is not set 126# CONFIG_BLK_DEV_INTEGRITY is not set
124 127
@@ -165,6 +168,7 @@ CONFIG_CPU_SH4A=y
165# CONFIG_CPU_SUBTYPE_SH7760 is not set 168# CONFIG_CPU_SUBTYPE_SH7760 is not set
166# CONFIG_CPU_SUBTYPE_SH4_202 is not set 169# CONFIG_CPU_SUBTYPE_SH4_202 is not set
167# CONFIG_CPU_SUBTYPE_SH7723 is not set 170# CONFIG_CPU_SUBTYPE_SH7723 is not set
171# CONFIG_CPU_SUBTYPE_SH7724 is not set
168# CONFIG_CPU_SUBTYPE_SH7763 is not set 172# CONFIG_CPU_SUBTYPE_SH7763 is not set
169# CONFIG_CPU_SUBTYPE_SH7770 is not set 173# CONFIG_CPU_SUBTYPE_SH7770 is not set
170CONFIG_CPU_SUBTYPE_SH7780=y 174CONFIG_CPU_SUBTYPE_SH7780=y
@@ -174,8 +178,6 @@ CONFIG_CPU_SUBTYPE_SH7780=y
174# CONFIG_CPU_SUBTYPE_SH7343 is not set 178# CONFIG_CPU_SUBTYPE_SH7343 is not set
175# CONFIG_CPU_SUBTYPE_SH7722 is not set 179# CONFIG_CPU_SUBTYPE_SH7722 is not set
176# CONFIG_CPU_SUBTYPE_SH7366 is not set 180# CONFIG_CPU_SUBTYPE_SH7366 is not set
177# CONFIG_CPU_SUBTYPE_SH5_101 is not set
178# CONFIG_CPU_SUBTYPE_SH5_103 is not set
179 181
180# 182#
181# Memory management options 183# Memory management options
@@ -258,7 +260,7 @@ CONFIG_SH_R7780MP=y
258# 260#
259CONFIG_SH_TMU=y 261CONFIG_SH_TMU=y
260CONFIG_SH_TIMER_IRQ=28 262CONFIG_SH_TIMER_IRQ=28
261CONFIG_SH_PCLK_FREQ=32000000 263CONFIG_SH_PCLK_FREQ=33333333
262# CONFIG_NO_HZ is not set 264# CONFIG_NO_HZ is not set
263# CONFIG_HIGH_RES_TIMERS is not set 265# CONFIG_HIGH_RES_TIMERS is not set
264CONFIG_GENERIC_CLOCKEVENTS_BUILD=y 266CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
@@ -313,8 +315,6 @@ CONFIG_CMDLINE="console=ttySC0,115200 root=/dev/sda1"
313# 315#
314CONFIG_PCI=y 316CONFIG_PCI=y
315CONFIG_SH_PCIDMA_NONCOHERENT=y 317CONFIG_SH_PCIDMA_NONCOHERENT=y
316CONFIG_PCI_AUTO=y
317CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
318# CONFIG_PCIEPORTBUS is not set 318# CONFIG_PCIEPORTBUS is not set
319# CONFIG_ARCH_SUPPORTS_MSI is not set 319# CONFIG_ARCH_SUPPORTS_MSI is not set
320CONFIG_PCI_LEGACY=y 320CONFIG_PCI_LEGACY=y
@@ -536,6 +536,7 @@ CONFIG_SCSI_LOWLEVEL=y
536# CONFIG_SCSI_MPT2SAS is not set 536# CONFIG_SCSI_MPT2SAS is not set
537# CONFIG_SCSI_HPTIOP is not set 537# CONFIG_SCSI_HPTIOP is not set
538# CONFIG_LIBFC is not set 538# CONFIG_LIBFC is not set
539# CONFIG_LIBFCOE is not set
539# CONFIG_FCOE is not set 540# CONFIG_FCOE is not set
540# CONFIG_SCSI_DMX3191D is not set 541# CONFIG_SCSI_DMX3191D is not set
541# CONFIG_SCSI_FUTURE_DOMAIN is not set 542# CONFIG_SCSI_FUTURE_DOMAIN is not set
@@ -696,6 +697,7 @@ CONFIG_E1000=m
696# CONFIG_E1000E is not set 697# CONFIG_E1000E is not set
697# CONFIG_IP1000 is not set 698# CONFIG_IP1000 is not set
698# CONFIG_IGB is not set 699# CONFIG_IGB is not set
700# CONFIG_IGBVF is not set
699# CONFIG_NS83820 is not set 701# CONFIG_NS83820 is not set
700# CONFIG_HAMACHI is not set 702# CONFIG_HAMACHI is not set
701# CONFIG_YELLOWFIN is not set 703# CONFIG_YELLOWFIN is not set
@@ -719,6 +721,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
719# CONFIG_IXGBE is not set 721# CONFIG_IXGBE is not set
720# CONFIG_IXGB is not set 722# CONFIG_IXGB is not set
721# CONFIG_S2IO is not set 723# CONFIG_S2IO is not set
724# CONFIG_VXGE is not set
722# CONFIG_MYRI10GE is not set 725# CONFIG_MYRI10GE is not set
723# CONFIG_NETXEN_NIC is not set 726# CONFIG_NETXEN_NIC is not set
724# CONFIG_NIU is not set 727# CONFIG_NIU is not set
@@ -920,6 +923,7 @@ CONFIG_HWMON=y
920# CONFIG_SENSORS_F71805F is not set 923# CONFIG_SENSORS_F71805F is not set
921# CONFIG_SENSORS_F71882FG is not set 924# CONFIG_SENSORS_F71882FG is not set
922# CONFIG_SENSORS_F75375S is not set 925# CONFIG_SENSORS_F75375S is not set
926# CONFIG_SENSORS_G760A is not set
923# CONFIG_SENSORS_GL518SM is not set 927# CONFIG_SENSORS_GL518SM is not set
924# CONFIG_SENSORS_GL520SM is not set 928# CONFIG_SENSORS_GL520SM is not set
925# CONFIG_SENSORS_IT87 is not set 929# CONFIG_SENSORS_IT87 is not set
@@ -1027,7 +1031,6 @@ CONFIG_HID=y
1027# 1031#
1028# Special HID drivers 1032# Special HID drivers
1029# 1033#
1030CONFIG_HID_COMPAT=y
1031CONFIG_USB_SUPPORT=y 1034CONFIG_USB_SUPPORT=y
1032CONFIG_USB_ARCH_HAS_HCD=y 1035CONFIG_USB_ARCH_HAS_HCD=y
1033CONFIG_USB_ARCH_HAS_OHCI=y 1036CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1120,6 +1123,7 @@ CONFIG_EXT2_FS=y
1120# CONFIG_EXT2_FS_XATTR is not set 1123# CONFIG_EXT2_FS_XATTR is not set
1121# CONFIG_EXT2_FS_XIP is not set 1124# CONFIG_EXT2_FS_XIP is not set
1122CONFIG_EXT3_FS=y 1125CONFIG_EXT3_FS=y
1126# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1123CONFIG_EXT3_FS_XATTR=y 1127CONFIG_EXT3_FS_XATTR=y
1124# CONFIG_EXT3_FS_POSIX_ACL is not set 1128# CONFIG_EXT3_FS_POSIX_ACL is not set
1125# CONFIG_EXT3_FS_SECURITY is not set 1129# CONFIG_EXT3_FS_SECURITY is not set
@@ -1143,6 +1147,11 @@ CONFIG_INOTIFY_USER=y
1143CONFIG_FUSE_FS=m 1147CONFIG_FUSE_FS=m
1144 1148
1145# 1149#
1150# Caches
1151#
1152# CONFIG_FSCACHE is not set
1153
1154#
1146# CD-ROM/DVD Filesystems 1155# CD-ROM/DVD Filesystems
1147# 1156#
1148# CONFIG_ISO9660_FS is not set 1157# CONFIG_ISO9660_FS is not set
@@ -1191,6 +1200,7 @@ CONFIG_MINIX_FS=y
1191# CONFIG_ROMFS_FS is not set 1200# CONFIG_ROMFS_FS is not set
1192# CONFIG_SYSV_FS is not set 1201# CONFIG_SYSV_FS is not set
1193# CONFIG_UFS_FS is not set 1202# CONFIG_UFS_FS is not set
1203# CONFIG_NILFS2_FS is not set
1194CONFIG_NETWORK_FILESYSTEMS=y 1204CONFIG_NETWORK_FILESYSTEMS=y
1195CONFIG_NFS_FS=y 1205CONFIG_NFS_FS=y
1196CONFIG_NFS_V3=y 1206CONFIG_NFS_V3=y
@@ -1279,6 +1289,9 @@ CONFIG_DEBUG_KERNEL=y
1279CONFIG_DETECT_SOFTLOCKUP=y 1289CONFIG_DETECT_SOFTLOCKUP=y
1280# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set 1290# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1281CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 1291CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1292CONFIG_DETECT_HUNG_TASK=y
1293# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1294CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1282CONFIG_SCHED_DEBUG=y 1295CONFIG_SCHED_DEBUG=y
1283# CONFIG_SCHEDSTATS is not set 1296# CONFIG_SCHEDSTATS is not set
1284# CONFIG_TIMER_STATS is not set 1297# CONFIG_TIMER_STATS is not set
@@ -1316,6 +1329,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE=y
1316CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1329CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1317CONFIG_RING_BUFFER=y 1330CONFIG_RING_BUFFER=y
1318CONFIG_TRACING=y 1331CONFIG_TRACING=y
1332CONFIG_TRACING_SUPPORT=y
1319 1333
1320# 1334#
1321# Tracers 1335# Tracers
@@ -1325,11 +1339,16 @@ CONFIG_TRACING=y
1325# CONFIG_PREEMPT_TRACER is not set 1339# CONFIG_PREEMPT_TRACER is not set
1326# CONFIG_SCHED_TRACER is not set 1340# CONFIG_SCHED_TRACER is not set
1327# CONFIG_CONTEXT_SWITCH_TRACER is not set 1341# CONFIG_CONTEXT_SWITCH_TRACER is not set
1342# CONFIG_EVENT_TRACER is not set
1328# CONFIG_BOOT_TRACER is not set 1343# CONFIG_BOOT_TRACER is not set
1329# CONFIG_TRACE_BRANCH_PROFILING is not set 1344# CONFIG_TRACE_BRANCH_PROFILING is not set
1330# CONFIG_STACK_TRACER is not set 1345# CONFIG_STACK_TRACER is not set
1346# CONFIG_KMEMTRACE is not set
1347# CONFIG_WORKQUEUE_TRACER is not set
1348# CONFIG_BLK_DEV_IO_TRACE is not set
1331# CONFIG_FTRACE_STARTUP_TEST is not set 1349# CONFIG_FTRACE_STARTUP_TEST is not set
1332# CONFIG_DYNAMIC_DEBUG is not set 1350# CONFIG_DYNAMIC_DEBUG is not set
1351# CONFIG_DMA_API_DEBUG is not set
1333# CONFIG_SAMPLES is not set 1352# CONFIG_SAMPLES is not set
1334CONFIG_HAVE_ARCH_KGDB=y 1353CONFIG_HAVE_ARCH_KGDB=y
1335# CONFIG_KGDB is not set 1354# CONFIG_KGDB is not set
@@ -1449,6 +1468,7 @@ CONFIG_CRYPTO_DES=y
1449# CONFIG_CRYPTO_ANSI_CPRNG is not set 1468# CONFIG_CRYPTO_ANSI_CPRNG is not set
1450CONFIG_CRYPTO_HW=y 1469CONFIG_CRYPTO_HW=y
1451# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1470# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1471CONFIG_BINARY_PRINTF=y
1452 1472
1453# 1473#
1454# Library routines 1474# Library routines
diff --git a/arch/sh/configs/r7785rp_defconfig b/arch/sh/configs/r7785rp_defconfig
index cb134ffc2118..82658f672398 100644
--- a/arch/sh/configs/r7785rp_defconfig
+++ b/arch/sh/configs/r7785rp_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:24:35 2009 4# Mon Apr 27 12:55:10 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -43,6 +44,7 @@ CONFIG_SWAP=y
43CONFIG_SYSVIPC=y 44CONFIG_SYSVIPC=y
44CONFIG_SYSVIPC_SYSCTL=y 45CONFIG_SYSVIPC_SYSCTL=y
45CONFIG_POSIX_MQUEUE=y 46CONFIG_POSIX_MQUEUE=y
47CONFIG_POSIX_MQUEUE_SYSCTL=y
46CONFIG_BSD_PROCESS_ACCT=y 48CONFIG_BSD_PROCESS_ACCT=y
47# CONFIG_BSD_PROCESS_ACCT_V3 is not set 49# CONFIG_BSD_PROCESS_ACCT_V3 is not set
48# CONFIG_TASKSTATS is not set 50# CONFIG_TASKSTATS is not set
@@ -78,6 +80,7 @@ CONFIG_UID16=y
78CONFIG_KALLSYMS=y 80CONFIG_KALLSYMS=y
79CONFIG_KALLSYMS_ALL=y 81CONFIG_KALLSYMS_ALL=y
80# CONFIG_KALLSYMS_EXTRA_PASS is not set 82# CONFIG_KALLSYMS_EXTRA_PASS is not set
83# CONFIG_STRIP_ASM_SYMS is not set
81CONFIG_HOTPLUG=y 84CONFIG_HOTPLUG=y
82CONFIG_PRINTK=y 85CONFIG_PRINTK=y
83CONFIG_BUG=y 86CONFIG_BUG=y
@@ -108,6 +111,8 @@ CONFIG_HAVE_KPROBES=y
108CONFIG_HAVE_KRETPROBES=y 111CONFIG_HAVE_KRETPROBES=y
109CONFIG_HAVE_ARCH_TRACEHOOK=y 112CONFIG_HAVE_ARCH_TRACEHOOK=y
110CONFIG_HAVE_CLK=y 113CONFIG_HAVE_CLK=y
114CONFIG_HAVE_DMA_API_DEBUG=y
115# CONFIG_SLOW_WORK is not set
111CONFIG_HAVE_GENERIC_DMA_COHERENT=y 116CONFIG_HAVE_GENERIC_DMA_COHERENT=y
112CONFIG_SLABINFO=y 117CONFIG_SLABINFO=y
113CONFIG_RT_MUTEXES=y 118CONFIG_RT_MUTEXES=y
@@ -120,7 +125,6 @@ CONFIG_MODULE_UNLOAD=y
120# CONFIG_MODULE_SRCVERSION_ALL is not set 125# CONFIG_MODULE_SRCVERSION_ALL is not set
121CONFIG_BLOCK=y 126CONFIG_BLOCK=y
122# CONFIG_LBD is not set 127# CONFIG_LBD is not set
123# CONFIG_BLK_DEV_IO_TRACE is not set
124# CONFIG_BLK_DEV_BSG is not set 128# CONFIG_BLK_DEV_BSG is not set
125# CONFIG_BLK_DEV_INTEGRITY is not set 129# CONFIG_BLK_DEV_INTEGRITY is not set
126 130
@@ -168,6 +172,7 @@ CONFIG_CPU_SHX2=y
168# CONFIG_CPU_SUBTYPE_SH7760 is not set 172# CONFIG_CPU_SUBTYPE_SH7760 is not set
169# CONFIG_CPU_SUBTYPE_SH4_202 is not set 173# CONFIG_CPU_SUBTYPE_SH4_202 is not set
170# CONFIG_CPU_SUBTYPE_SH7723 is not set 174# CONFIG_CPU_SUBTYPE_SH7723 is not set
175# CONFIG_CPU_SUBTYPE_SH7724 is not set
171# CONFIG_CPU_SUBTYPE_SH7763 is not set 176# CONFIG_CPU_SUBTYPE_SH7763 is not set
172# CONFIG_CPU_SUBTYPE_SH7770 is not set 177# CONFIG_CPU_SUBTYPE_SH7770 is not set
173# CONFIG_CPU_SUBTYPE_SH7780 is not set 178# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -177,8 +182,6 @@ CONFIG_CPU_SUBTYPE_SH7785=y
177# CONFIG_CPU_SUBTYPE_SH7343 is not set 182# CONFIG_CPU_SUBTYPE_SH7343 is not set
178# CONFIG_CPU_SUBTYPE_SH7722 is not set 183# CONFIG_CPU_SUBTYPE_SH7722 is not set
179# CONFIG_CPU_SUBTYPE_SH7366 is not set 184# CONFIG_CPU_SUBTYPE_SH7366 is not set
180# CONFIG_CPU_SUBTYPE_SH5_101 is not set
181# CONFIG_CPU_SUBTYPE_SH5_103 is not set
182 185
183# 186#
184# Memory management options 187# Memory management options
@@ -266,7 +269,7 @@ CONFIG_SH_R7785RP=y
266# 269#
267CONFIG_SH_TMU=y 270CONFIG_SH_TMU=y
268CONFIG_SH_TIMER_IRQ=28 271CONFIG_SH_TIMER_IRQ=28
269CONFIG_SH_PCLK_FREQ=50000000 272CONFIG_SH_PCLK_FREQ=33333333
270CONFIG_TICK_ONESHOT=y 273CONFIG_TICK_ONESHOT=y
271CONFIG_NO_HZ=y 274CONFIG_NO_HZ=y
272CONFIG_HIGH_RES_TIMERS=y 275CONFIG_HIGH_RES_TIMERS=y
@@ -337,8 +340,6 @@ CONFIG_CMDLINE="console=ttySC0,115200 root=/dev/sda1"
337# 340#
338CONFIG_PCI=y 341CONFIG_PCI=y
339CONFIG_SH_PCIDMA_NONCOHERENT=y 342CONFIG_SH_PCIDMA_NONCOHERENT=y
340CONFIG_PCI_AUTO=y
341CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
342# CONFIG_PCIEPORTBUS is not set 343# CONFIG_PCIEPORTBUS is not set
343# CONFIG_ARCH_SUPPORTS_MSI is not set 344# CONFIG_ARCH_SUPPORTS_MSI is not set
344# CONFIG_PCI_LEGACY is not set 345# CONFIG_PCI_LEGACY is not set
@@ -561,6 +562,7 @@ CONFIG_SCSI_LOWLEVEL=y
561# CONFIG_SCSI_MPT2SAS is not set 562# CONFIG_SCSI_MPT2SAS is not set
562# CONFIG_SCSI_HPTIOP is not set 563# CONFIG_SCSI_HPTIOP is not set
563# CONFIG_LIBFC is not set 564# CONFIG_LIBFC is not set
565# CONFIG_LIBFCOE is not set
564# CONFIG_FCOE is not set 566# CONFIG_FCOE is not set
565# CONFIG_SCSI_DMX3191D is not set 567# CONFIG_SCSI_DMX3191D is not set
566# CONFIG_SCSI_FUTURE_DOMAIN is not set 568# CONFIG_SCSI_FUTURE_DOMAIN is not set
@@ -698,6 +700,7 @@ CONFIG_NETDEV_1000=y
698# CONFIG_E1000E is not set 700# CONFIG_E1000E is not set
699# CONFIG_IP1000 is not set 701# CONFIG_IP1000 is not set
700# CONFIG_IGB is not set 702# CONFIG_IGB is not set
703# CONFIG_IGBVF is not set
701# CONFIG_NS83820 is not set 704# CONFIG_NS83820 is not set
702# CONFIG_HAMACHI is not set 705# CONFIG_HAMACHI is not set
703# CONFIG_YELLOWFIN is not set 706# CONFIG_YELLOWFIN is not set
@@ -721,6 +724,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
721# CONFIG_IXGBE is not set 724# CONFIG_IXGBE is not set
722# CONFIG_IXGB is not set 725# CONFIG_IXGB is not set
723# CONFIG_S2IO is not set 726# CONFIG_S2IO is not set
727# CONFIG_VXGE is not set
724# CONFIG_MYRI10GE is not set 728# CONFIG_MYRI10GE is not set
725# CONFIG_NETXEN_NIC is not set 729# CONFIG_NETXEN_NIC is not set
726# CONFIG_NIU is not set 730# CONFIG_NIU is not set
@@ -948,6 +952,7 @@ CONFIG_HWMON=y
948# CONFIG_SENSORS_F71805F is not set 952# CONFIG_SENSORS_F71805F is not set
949# CONFIG_SENSORS_F71882FG is not set 953# CONFIG_SENSORS_F71882FG is not set
950# CONFIG_SENSORS_F75375S is not set 954# CONFIG_SENSORS_F75375S is not set
955# CONFIG_SENSORS_G760A is not set
951# CONFIG_SENSORS_GL518SM is not set 956# CONFIG_SENSORS_GL518SM is not set
952# CONFIG_SENSORS_GL520SM is not set 957# CONFIG_SENSORS_GL520SM is not set
953# CONFIG_SENSORS_IT87 is not set 958# CONFIG_SENSORS_IT87 is not set
@@ -970,6 +975,7 @@ CONFIG_HWMON=y
970# CONFIG_SENSORS_PC87360 is not set 975# CONFIG_SENSORS_PC87360 is not set
971# CONFIG_SENSORS_PC87427 is not set 976# CONFIG_SENSORS_PC87427 is not set
972# CONFIG_SENSORS_PCF8591 is not set 977# CONFIG_SENSORS_PCF8591 is not set
978# CONFIG_SENSORS_SHT15 is not set
973# CONFIG_SENSORS_SIS5595 is not set 979# CONFIG_SENSORS_SIS5595 is not set
974# CONFIG_SENSORS_DME1737 is not set 980# CONFIG_SENSORS_DME1737 is not set
975# CONFIG_SENSORS_SMSC47M1 is not set 981# CONFIG_SENSORS_SMSC47M1 is not set
@@ -1109,7 +1115,6 @@ CONFIG_HID=y
1109# 1115#
1110# Special HID drivers 1116# Special HID drivers
1111# 1117#
1112CONFIG_HID_COMPAT=y
1113CONFIG_USB_SUPPORT=y 1118CONFIG_USB_SUPPORT=y
1114CONFIG_USB_ARCH_HAS_HCD=y 1119CONFIG_USB_ARCH_HAS_HCD=y
1115CONFIG_USB_ARCH_HAS_OHCI=y 1120CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1202,6 +1207,7 @@ CONFIG_EXT2_FS=y
1202# CONFIG_EXT2_FS_XATTR is not set 1207# CONFIG_EXT2_FS_XATTR is not set
1203# CONFIG_EXT2_FS_XIP is not set 1208# CONFIG_EXT2_FS_XIP is not set
1204CONFIG_EXT3_FS=y 1209CONFIG_EXT3_FS=y
1210# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1205CONFIG_EXT3_FS_XATTR=y 1211CONFIG_EXT3_FS_XATTR=y
1206# CONFIG_EXT3_FS_POSIX_ACL is not set 1212# CONFIG_EXT3_FS_POSIX_ACL is not set
1207# CONFIG_EXT3_FS_SECURITY is not set 1213# CONFIG_EXT3_FS_SECURITY is not set
@@ -1225,6 +1231,11 @@ CONFIG_INOTIFY_USER=y
1225CONFIG_FUSE_FS=m 1231CONFIG_FUSE_FS=m
1226 1232
1227# 1233#
1234# Caches
1235#
1236# CONFIG_FSCACHE is not set
1237
1238#
1228# CD-ROM/DVD Filesystems 1239# CD-ROM/DVD Filesystems
1229# 1240#
1230# CONFIG_ISO9660_FS is not set 1241# CONFIG_ISO9660_FS is not set
@@ -1273,6 +1284,7 @@ CONFIG_MINIX_FS=y
1273# CONFIG_ROMFS_FS is not set 1284# CONFIG_ROMFS_FS is not set
1274# CONFIG_SYSV_FS is not set 1285# CONFIG_SYSV_FS is not set
1275# CONFIG_UFS_FS is not set 1286# CONFIG_UFS_FS is not set
1287# CONFIG_NILFS2_FS is not set
1276CONFIG_NETWORK_FILESYSTEMS=y 1288CONFIG_NETWORK_FILESYSTEMS=y
1277CONFIG_NFS_FS=y 1289CONFIG_NFS_FS=y
1278CONFIG_NFS_V3=y 1290CONFIG_NFS_V3=y
@@ -1359,6 +1371,7 @@ CONFIG_DEBUG_FS=y
1359CONFIG_DEBUG_KERNEL=y 1371CONFIG_DEBUG_KERNEL=y
1360# CONFIG_DEBUG_SHIRQ is not set 1372# CONFIG_DEBUG_SHIRQ is not set
1361# CONFIG_DETECT_SOFTLOCKUP is not set 1373# CONFIG_DETECT_SOFTLOCKUP is not set
1374# CONFIG_DETECT_HUNG_TASK is not set
1362CONFIG_SCHED_DEBUG=y 1375CONFIG_SCHED_DEBUG=y
1363# CONFIG_SCHEDSTATS is not set 1376# CONFIG_SCHEDSTATS is not set
1364# CONFIG_TIMER_STATS is not set 1377# CONFIG_TIMER_STATS is not set
@@ -1401,6 +1414,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE=y
1401CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1414CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1402CONFIG_RING_BUFFER=y 1415CONFIG_RING_BUFFER=y
1403CONFIG_TRACING=y 1416CONFIG_TRACING=y
1417CONFIG_TRACING_SUPPORT=y
1404 1418
1405# 1419#
1406# Tracers 1420# Tracers
@@ -1410,11 +1424,16 @@ CONFIG_TRACING=y
1410# CONFIG_PREEMPT_TRACER is not set 1424# CONFIG_PREEMPT_TRACER is not set
1411# CONFIG_SCHED_TRACER is not set 1425# CONFIG_SCHED_TRACER is not set
1412# CONFIG_CONTEXT_SWITCH_TRACER is not set 1426# CONFIG_CONTEXT_SWITCH_TRACER is not set
1427# CONFIG_EVENT_TRACER is not set
1413# CONFIG_BOOT_TRACER is not set 1428# CONFIG_BOOT_TRACER is not set
1414# CONFIG_TRACE_BRANCH_PROFILING is not set 1429# CONFIG_TRACE_BRANCH_PROFILING is not set
1415# CONFIG_STACK_TRACER is not set 1430# CONFIG_STACK_TRACER is not set
1431# CONFIG_KMEMTRACE is not set
1432# CONFIG_WORKQUEUE_TRACER is not set
1433# CONFIG_BLK_DEV_IO_TRACE is not set
1416# CONFIG_FTRACE_STARTUP_TEST is not set 1434# CONFIG_FTRACE_STARTUP_TEST is not set
1417# CONFIG_DYNAMIC_DEBUG is not set 1435# CONFIG_DYNAMIC_DEBUG is not set
1436# CONFIG_DMA_API_DEBUG is not set
1418# CONFIG_SAMPLES is not set 1437# CONFIG_SAMPLES is not set
1419CONFIG_HAVE_ARCH_KGDB=y 1438CONFIG_HAVE_ARCH_KGDB=y
1420# CONFIG_KGDB is not set 1439# CONFIG_KGDB is not set
@@ -1534,6 +1553,7 @@ CONFIG_CRYPTO_DES=y
1534# CONFIG_CRYPTO_ANSI_CPRNG is not set 1553# CONFIG_CRYPTO_ANSI_CPRNG is not set
1535CONFIG_CRYPTO_HW=y 1554CONFIG_CRYPTO_HW=y
1536# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1555# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1556CONFIG_BINARY_PRINTF=y
1537 1557
1538# 1558#
1539# Library routines 1559# Library routines
diff --git a/arch/sh/configs/rsk7201_defconfig b/arch/sh/configs/rsk7201_defconfig
index a037c744b798..fa4395768d19 100644
--- a/arch/sh/configs/rsk7201_defconfig
+++ b/arch/sh/configs/rsk7201_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:29:08 2009 4# Mon Apr 27 12:56:29 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -65,7 +66,6 @@ CONFIG_INITRAMFS_SOURCE=""
65CONFIG_RD_GZIP=y 66CONFIG_RD_GZIP=y
66# CONFIG_RD_BZIP2 is not set 67# CONFIG_RD_BZIP2 is not set
67# CONFIG_RD_LZMA is not set 68# CONFIG_RD_LZMA is not set
68CONFIG_INITRAMFS_COMPRESSION_NONE=y
69CONFIG_CC_OPTIMIZE_FOR_SIZE=y 69CONFIG_CC_OPTIMIZE_FOR_SIZE=y
70CONFIG_SYSCTL=y 70CONFIG_SYSCTL=y
71CONFIG_ANON_INODES=y 71CONFIG_ANON_INODES=y
@@ -74,6 +74,7 @@ CONFIG_UID16=y
74CONFIG_SYSCTL_SYSCALL=y 74CONFIG_SYSCTL_SYSCALL=y
75CONFIG_KALLSYMS=y 75CONFIG_KALLSYMS=y
76# CONFIG_KALLSYMS_EXTRA_PASS is not set 76# CONFIG_KALLSYMS_EXTRA_PASS is not set
77# CONFIG_STRIP_ASM_SYMS is not set
77CONFIG_HOTPLUG=y 78CONFIG_HOTPLUG=y
78CONFIG_PRINTK=y 79CONFIG_PRINTK=y
79CONFIG_BUG=y 80CONFIG_BUG=y
@@ -100,6 +101,8 @@ CONFIG_HAVE_KPROBES=y
100CONFIG_HAVE_KRETPROBES=y 101CONFIG_HAVE_KRETPROBES=y
101CONFIG_HAVE_ARCH_TRACEHOOK=y 102CONFIG_HAVE_ARCH_TRACEHOOK=y
102CONFIG_HAVE_CLK=y 103CONFIG_HAVE_CLK=y
104CONFIG_HAVE_DMA_API_DEBUG=y
105# CONFIG_SLOW_WORK is not set
103CONFIG_HAVE_GENERIC_DMA_COHERENT=y 106CONFIG_HAVE_GENERIC_DMA_COHERENT=y
104CONFIG_RT_MUTEXES=y 107CONFIG_RT_MUTEXES=y
105CONFIG_BASE_SMALL=0 108CONFIG_BASE_SMALL=0
@@ -110,7 +113,6 @@ CONFIG_MODULES=y
110# CONFIG_MODULE_SRCVERSION_ALL is not set 113# CONFIG_MODULE_SRCVERSION_ALL is not set
111CONFIG_BLOCK=y 114CONFIG_BLOCK=y
112# CONFIG_LBD is not set 115# CONFIG_LBD is not set
113# CONFIG_BLK_DEV_IO_TRACE is not set
114# CONFIG_BLK_DEV_BSG is not set 116# CONFIG_BLK_DEV_BSG is not set
115# CONFIG_BLK_DEV_INTEGRITY is not set 117# CONFIG_BLK_DEV_INTEGRITY is not set
116 118
@@ -157,6 +159,7 @@ CONFIG_CPU_SUBTYPE_SH7201=y
157# CONFIG_CPU_SUBTYPE_SH7760 is not set 159# CONFIG_CPU_SUBTYPE_SH7760 is not set
158# CONFIG_CPU_SUBTYPE_SH4_202 is not set 160# CONFIG_CPU_SUBTYPE_SH4_202 is not set
159# CONFIG_CPU_SUBTYPE_SH7723 is not set 161# CONFIG_CPU_SUBTYPE_SH7723 is not set
162# CONFIG_CPU_SUBTYPE_SH7724 is not set
160# CONFIG_CPU_SUBTYPE_SH7763 is not set 163# CONFIG_CPU_SUBTYPE_SH7763 is not set
161# CONFIG_CPU_SUBTYPE_SH7770 is not set 164# CONFIG_CPU_SUBTYPE_SH7770 is not set
162# CONFIG_CPU_SUBTYPE_SH7780 is not set 165# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -166,8 +169,6 @@ CONFIG_CPU_SUBTYPE_SH7201=y
166# CONFIG_CPU_SUBTYPE_SH7343 is not set 169# CONFIG_CPU_SUBTYPE_SH7343 is not set
167# CONFIG_CPU_SUBTYPE_SH7722 is not set 170# CONFIG_CPU_SUBTYPE_SH7722 is not set
168# CONFIG_CPU_SUBTYPE_SH7366 is not set 171# CONFIG_CPU_SUBTYPE_SH7366 is not set
169# CONFIG_CPU_SUBTYPE_SH5_101 is not set
170# CONFIG_CPU_SUBTYPE_SH5_103 is not set
171 172
172# 173#
173# Memory management options 174# Memory management options
@@ -603,6 +604,11 @@ CONFIG_EXT2_FS=y
603# CONFIG_FUSE_FS is not set 604# CONFIG_FUSE_FS is not set
604 605
605# 606#
607# Caches
608#
609# CONFIG_FSCACHE is not set
610
611#
606# CD-ROM/DVD Filesystems 612# CD-ROM/DVD Filesystems
607# 613#
608# CONFIG_ISO9660_FS is not set 614# CONFIG_ISO9660_FS is not set
@@ -651,8 +657,13 @@ CONFIG_JFFS2_RTIME=y
651# CONFIG_HPFS_FS is not set 657# CONFIG_HPFS_FS is not set
652# CONFIG_QNX4FS_FS is not set 658# CONFIG_QNX4FS_FS is not set
653CONFIG_ROMFS_FS=y 659CONFIG_ROMFS_FS=y
660CONFIG_ROMFS_BACKED_BY_BLOCK=y
661# CONFIG_ROMFS_BACKED_BY_MTD is not set
662# CONFIG_ROMFS_BACKED_BY_BOTH is not set
663CONFIG_ROMFS_ON_BLOCK=y
654# CONFIG_SYSV_FS is not set 664# CONFIG_SYSV_FS is not set
655# CONFIG_UFS_FS is not set 665# CONFIG_UFS_FS is not set
666# CONFIG_NILFS2_FS is not set
656 667
657# 668#
658# Partition Types 669# Partition Types
@@ -686,11 +697,24 @@ CONFIG_HAVE_DYNAMIC_FTRACE=y
686CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 697CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
687CONFIG_RING_BUFFER=y 698CONFIG_RING_BUFFER=y
688CONFIG_TRACING=y 699CONFIG_TRACING=y
700CONFIG_TRACING_SUPPORT=y
689 701
690# 702#
691# Tracers 703# Tracers
692# 704#
705# CONFIG_FUNCTION_TRACER is not set
706# CONFIG_SCHED_TRACER is not set
707# CONFIG_CONTEXT_SWITCH_TRACER is not set
708# CONFIG_EVENT_TRACER is not set
709# CONFIG_BOOT_TRACER is not set
710# CONFIG_TRACE_BRANCH_PROFILING is not set
711# CONFIG_STACK_TRACER is not set
712# CONFIG_KMEMTRACE is not set
713# CONFIG_WORKQUEUE_TRACER is not set
714# CONFIG_BLK_DEV_IO_TRACE is not set
715# CONFIG_FTRACE_STARTUP_TEST is not set
693# CONFIG_DYNAMIC_DEBUG is not set 716# CONFIG_DYNAMIC_DEBUG is not set
717# CONFIG_DMA_API_DEBUG is not set
694# CONFIG_SAMPLES is not set 718# CONFIG_SAMPLES is not set
695CONFIG_HAVE_ARCH_KGDB=y 719CONFIG_HAVE_ARCH_KGDB=y
696# CONFIG_SH_STANDARD_BIOS is not set 720# CONFIG_SH_STANDARD_BIOS is not set
@@ -705,6 +729,7 @@ CONFIG_HAVE_ARCH_KGDB=y
705# CONFIG_SECURITYFS is not set 729# CONFIG_SECURITYFS is not set
706# CONFIG_SECURITY_FILE_CAPABILITIES is not set 730# CONFIG_SECURITY_FILE_CAPABILITIES is not set
707# CONFIG_CRYPTO is not set 731# CONFIG_CRYPTO is not set
732CONFIG_BINARY_PRINTF=y
708 733
709# 734#
710# Library routines 735# Library routines
diff --git a/arch/sh/configs/rsk7203_defconfig b/arch/sh/configs/rsk7203_defconfig
index 9ae28e88426c..e3a65f819f0a 100644
--- a/arch/sh/configs/rsk7203_defconfig
+++ b/arch/sh/configs/rsk7203_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:30:34 2009 4# Mon Apr 27 12:57:06 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -39,6 +40,7 @@ CONFIG_LOCALVERSION=""
39CONFIG_SYSVIPC=y 40CONFIG_SYSVIPC=y
40CONFIG_SYSVIPC_SYSCTL=y 41CONFIG_SYSVIPC_SYSCTL=y
41CONFIG_POSIX_MQUEUE=y 42CONFIG_POSIX_MQUEUE=y
43CONFIG_POSIX_MQUEUE_SYSCTL=y
42CONFIG_BSD_PROCESS_ACCT=y 44CONFIG_BSD_PROCESS_ACCT=y
43# CONFIG_BSD_PROCESS_ACCT_V3 is not set 45# CONFIG_BSD_PROCESS_ACCT_V3 is not set
44# CONFIG_TASKSTATS is not set 46# CONFIG_TASKSTATS is not set
@@ -70,7 +72,6 @@ CONFIG_INITRAMFS_SOURCE=""
70CONFIG_RD_GZIP=y 72CONFIG_RD_GZIP=y
71# CONFIG_RD_BZIP2 is not set 73# CONFIG_RD_BZIP2 is not set
72# CONFIG_RD_LZMA is not set 74# CONFIG_RD_LZMA is not set
73CONFIG_INITRAMFS_COMPRESSION_NONE=y
74CONFIG_CC_OPTIMIZE_FOR_SIZE=y 75CONFIG_CC_OPTIMIZE_FOR_SIZE=y
75CONFIG_SYSCTL=y 76CONFIG_SYSCTL=y
76CONFIG_ANON_INODES=y 77CONFIG_ANON_INODES=y
@@ -80,6 +81,7 @@ CONFIG_SYSCTL_SYSCALL=y
80CONFIG_KALLSYMS=y 81CONFIG_KALLSYMS=y
81CONFIG_KALLSYMS_ALL=y 82CONFIG_KALLSYMS_ALL=y
82# CONFIG_KALLSYMS_EXTRA_PASS is not set 83# CONFIG_KALLSYMS_EXTRA_PASS is not set
84# CONFIG_STRIP_ASM_SYMS is not set
83CONFIG_HOTPLUG=y 85CONFIG_HOTPLUG=y
84CONFIG_PRINTK=y 86CONFIG_PRINTK=y
85CONFIG_BUG=y 87CONFIG_BUG=y
@@ -106,6 +108,8 @@ CONFIG_HAVE_KPROBES=y
106CONFIG_HAVE_KRETPROBES=y 108CONFIG_HAVE_KRETPROBES=y
107CONFIG_HAVE_ARCH_TRACEHOOK=y 109CONFIG_HAVE_ARCH_TRACEHOOK=y
108CONFIG_HAVE_CLK=y 110CONFIG_HAVE_CLK=y
111CONFIG_HAVE_DMA_API_DEBUG=y
112# CONFIG_SLOW_WORK is not set
109CONFIG_HAVE_GENERIC_DMA_COHERENT=y 113CONFIG_HAVE_GENERIC_DMA_COHERENT=y
110CONFIG_RT_MUTEXES=y 114CONFIG_RT_MUTEXES=y
111CONFIG_BASE_SMALL=0 115CONFIG_BASE_SMALL=0
@@ -116,7 +120,6 @@ CONFIG_MODULES=y
116# CONFIG_MODULE_SRCVERSION_ALL is not set 120# CONFIG_MODULE_SRCVERSION_ALL is not set
117CONFIG_BLOCK=y 121CONFIG_BLOCK=y
118# CONFIG_LBD is not set 122# CONFIG_LBD is not set
119# CONFIG_BLK_DEV_IO_TRACE is not set
120# CONFIG_BLK_DEV_BSG is not set 123# CONFIG_BLK_DEV_BSG is not set
121# CONFIG_BLK_DEV_INTEGRITY is not set 124# CONFIG_BLK_DEV_INTEGRITY is not set
122 125
@@ -163,6 +166,7 @@ CONFIG_CPU_SUBTYPE_SH7203=y
163# CONFIG_CPU_SUBTYPE_SH7760 is not set 166# CONFIG_CPU_SUBTYPE_SH7760 is not set
164# CONFIG_CPU_SUBTYPE_SH4_202 is not set 167# CONFIG_CPU_SUBTYPE_SH4_202 is not set
165# CONFIG_CPU_SUBTYPE_SH7723 is not set 168# CONFIG_CPU_SUBTYPE_SH7723 is not set
169# CONFIG_CPU_SUBTYPE_SH7724 is not set
166# CONFIG_CPU_SUBTYPE_SH7763 is not set 170# CONFIG_CPU_SUBTYPE_SH7763 is not set
167# CONFIG_CPU_SUBTYPE_SH7770 is not set 171# CONFIG_CPU_SUBTYPE_SH7770 is not set
168# CONFIG_CPU_SUBTYPE_SH7780 is not set 172# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -172,8 +176,6 @@ CONFIG_CPU_SUBTYPE_SH7203=y
172# CONFIG_CPU_SUBTYPE_SH7343 is not set 176# CONFIG_CPU_SUBTYPE_SH7343 is not set
173# CONFIG_CPU_SUBTYPE_SH7722 is not set 177# CONFIG_CPU_SUBTYPE_SH7722 is not set
174# CONFIG_CPU_SUBTYPE_SH7366 is not set 178# CONFIG_CPU_SUBTYPE_SH7366 is not set
175# CONFIG_CPU_SUBTYPE_SH5_101 is not set
176# CONFIG_CPU_SUBTYPE_SH5_103 is not set
177 179
178# 180#
179# Memory management options 181# Memory management options
@@ -750,15 +752,17 @@ CONFIG_USB_HID=y
750# 752#
751# Special HID drivers 753# Special HID drivers
752# 754#
753CONFIG_HID_COMPAT=y
754CONFIG_HID_A4TECH=y 755CONFIG_HID_A4TECH=y
755CONFIG_HID_APPLE=y 756CONFIG_HID_APPLE=y
756CONFIG_HID_BELKIN=y 757CONFIG_HID_BELKIN=y
757CONFIG_HID_CHERRY=y 758CONFIG_HID_CHERRY=y
758CONFIG_HID_CHICONY=y 759CONFIG_HID_CHICONY=y
759CONFIG_HID_CYPRESS=y 760CONFIG_HID_CYPRESS=y
761# CONFIG_DRAGONRISE_FF is not set
760CONFIG_HID_EZKEY=y 762CONFIG_HID_EZKEY=y
763# CONFIG_HID_KYE is not set
761CONFIG_HID_GYRATION=y 764CONFIG_HID_GYRATION=y
765# CONFIG_HID_KENSINGTON is not set
762CONFIG_HID_LOGITECH=y 766CONFIG_HID_LOGITECH=y
763# CONFIG_LOGITECH_FF is not set 767# CONFIG_LOGITECH_FF is not set
764# CONFIG_LOGIRUMBLEPAD2_FF is not set 768# CONFIG_LOGIRUMBLEPAD2_FF is not set
@@ -874,6 +878,7 @@ CONFIG_LEDS_CLASS=y
874# LED drivers 878# LED drivers
875# 879#
876CONFIG_LEDS_GPIO=y 880CONFIG_LEDS_GPIO=y
881CONFIG_LEDS_GPIO_PLATFORM=y
877 882
878# 883#
879# LED Triggers 884# LED Triggers
@@ -882,6 +887,7 @@ CONFIG_LEDS_TRIGGERS=y
882CONFIG_LEDS_TRIGGER_TIMER=y 887CONFIG_LEDS_TRIGGER_TIMER=y
883CONFIG_LEDS_TRIGGER_HEARTBEAT=y 888CONFIG_LEDS_TRIGGER_HEARTBEAT=y
884CONFIG_LEDS_TRIGGER_BACKLIGHT=y 889CONFIG_LEDS_TRIGGER_BACKLIGHT=y
890# CONFIG_LEDS_TRIGGER_GPIO is not set
885CONFIG_LEDS_TRIGGER_DEFAULT_ON=y 891CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
886 892
887# 893#
@@ -951,6 +957,11 @@ CONFIG_FILE_LOCKING=y
951# CONFIG_FUSE_FS is not set 957# CONFIG_FUSE_FS is not set
952 958
953# 959#
960# Caches
961#
962# CONFIG_FSCACHE is not set
963
964#
954# CD-ROM/DVD Filesystems 965# CD-ROM/DVD Filesystems
955# 966#
956# CONFIG_ISO9660_FS is not set 967# CONFIG_ISO9660_FS is not set
@@ -989,8 +1000,13 @@ CONFIG_MISC_FILESYSTEMS=y
989# CONFIG_HPFS_FS is not set 1000# CONFIG_HPFS_FS is not set
990# CONFIG_QNX4FS_FS is not set 1001# CONFIG_QNX4FS_FS is not set
991CONFIG_ROMFS_FS=y 1002CONFIG_ROMFS_FS=y
1003CONFIG_ROMFS_BACKED_BY_BLOCK=y
1004# CONFIG_ROMFS_BACKED_BY_MTD is not set
1005# CONFIG_ROMFS_BACKED_BY_BOTH is not set
1006CONFIG_ROMFS_ON_BLOCK=y
992# CONFIG_SYSV_FS is not set 1007# CONFIG_SYSV_FS is not set
993# CONFIG_UFS_FS is not set 1008# CONFIG_UFS_FS is not set
1009# CONFIG_NILFS2_FS is not set
994CONFIG_NETWORK_FILESYSTEMS=y 1010CONFIG_NETWORK_FILESYSTEMS=y
995CONFIG_NFS_FS=y 1011CONFIG_NFS_FS=y
996# CONFIG_NFS_V3 is not set 1012# CONFIG_NFS_V3 is not set
@@ -1033,6 +1049,9 @@ CONFIG_DEBUG_SHIRQ=y
1033CONFIG_DETECT_SOFTLOCKUP=y 1049CONFIG_DETECT_SOFTLOCKUP=y
1034# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set 1050# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1035CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 1051CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1052CONFIG_DETECT_HUNG_TASK=y
1053# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1054CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1036CONFIG_SCHED_DEBUG=y 1055CONFIG_SCHED_DEBUG=y
1037# CONFIG_SCHEDSTATS is not set 1056# CONFIG_SCHEDSTATS is not set
1038# CONFIG_TIMER_STATS is not set 1057# CONFIG_TIMER_STATS is not set
@@ -1076,6 +1095,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE=y
1076CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1095CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1077CONFIG_RING_BUFFER=y 1096CONFIG_RING_BUFFER=y
1078CONFIG_TRACING=y 1097CONFIG_TRACING=y
1098CONFIG_TRACING_SUPPORT=y
1079 1099
1080# 1100#
1081# Tracers 1101# Tracers
@@ -1083,11 +1103,16 @@ CONFIG_TRACING=y
1083# CONFIG_FUNCTION_TRACER is not set 1103# CONFIG_FUNCTION_TRACER is not set
1084# CONFIG_SCHED_TRACER is not set 1104# CONFIG_SCHED_TRACER is not set
1085# CONFIG_CONTEXT_SWITCH_TRACER is not set 1105# CONFIG_CONTEXT_SWITCH_TRACER is not set
1106# CONFIG_EVENT_TRACER is not set
1086# CONFIG_BOOT_TRACER is not set 1107# CONFIG_BOOT_TRACER is not set
1087# CONFIG_TRACE_BRANCH_PROFILING is not set 1108# CONFIG_TRACE_BRANCH_PROFILING is not set
1088# CONFIG_STACK_TRACER is not set 1109# CONFIG_STACK_TRACER is not set
1110# CONFIG_KMEMTRACE is not set
1111# CONFIG_WORKQUEUE_TRACER is not set
1112# CONFIG_BLK_DEV_IO_TRACE is not set
1089# CONFIG_FTRACE_STARTUP_TEST is not set 1113# CONFIG_FTRACE_STARTUP_TEST is not set
1090# CONFIG_DYNAMIC_DEBUG is not set 1114# CONFIG_DYNAMIC_DEBUG is not set
1115# CONFIG_DMA_API_DEBUG is not set
1091# CONFIG_SAMPLES is not set 1116# CONFIG_SAMPLES is not set
1092CONFIG_HAVE_ARCH_KGDB=y 1117CONFIG_HAVE_ARCH_KGDB=y
1093# CONFIG_KGDB is not set 1118# CONFIG_KGDB is not set
@@ -1111,6 +1136,7 @@ CONFIG_DUMP_CODE=y
1111# CONFIG_SECURITYFS is not set 1136# CONFIG_SECURITYFS is not set
1112# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1137# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1113# CONFIG_CRYPTO is not set 1138# CONFIG_CRYPTO is not set
1139CONFIG_BINARY_PRINTF=y
1114 1140
1115# 1141#
1116# Library routines 1142# Library routines
diff --git a/arch/sh/configs/rts7751r2d1_defconfig b/arch/sh/configs/rts7751r2d1_defconfig
index c0f741af6da8..a4a59f6205ab 100644
--- a/arch/sh/configs/rts7751r2d1_defconfig
+++ b/arch/sh/configs/rts7751r2d1_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:33:25 2009 4# Mon Apr 27 12:58:13 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -70,6 +71,7 @@ CONFIG_UID16=y
70# CONFIG_SYSCTL_SYSCALL is not set 71# CONFIG_SYSCTL_SYSCALL is not set
71CONFIG_KALLSYMS=y 72CONFIG_KALLSYMS=y
72# CONFIG_KALLSYMS_EXTRA_PASS is not set 73# CONFIG_KALLSYMS_EXTRA_PASS is not set
74# CONFIG_STRIP_ASM_SYMS is not set
73CONFIG_HOTPLUG=y 75CONFIG_HOTPLUG=y
74CONFIG_PRINTK=y 76CONFIG_PRINTK=y
75CONFIG_BUG=y 77CONFIG_BUG=y
@@ -99,6 +101,8 @@ CONFIG_HAVE_KPROBES=y
99CONFIG_HAVE_KRETPROBES=y 101CONFIG_HAVE_KRETPROBES=y
100CONFIG_HAVE_ARCH_TRACEHOOK=y 102CONFIG_HAVE_ARCH_TRACEHOOK=y
101CONFIG_HAVE_CLK=y 103CONFIG_HAVE_CLK=y
104CONFIG_HAVE_DMA_API_DEBUG=y
105# CONFIG_SLOW_WORK is not set
102CONFIG_HAVE_GENERIC_DMA_COHERENT=y 106CONFIG_HAVE_GENERIC_DMA_COHERENT=y
103CONFIG_SLABINFO=y 107CONFIG_SLABINFO=y
104CONFIG_RT_MUTEXES=y 108CONFIG_RT_MUTEXES=y
@@ -110,7 +114,6 @@ CONFIG_MODULES=y
110# CONFIG_MODULE_SRCVERSION_ALL is not set 114# CONFIG_MODULE_SRCVERSION_ALL is not set
111CONFIG_BLOCK=y 115CONFIG_BLOCK=y
112# CONFIG_LBD is not set 116# CONFIG_LBD is not set
113# CONFIG_BLK_DEV_IO_TRACE is not set
114# CONFIG_BLK_DEV_BSG is not set 117# CONFIG_BLK_DEV_BSG is not set
115# CONFIG_BLK_DEV_INTEGRITY is not set 118# CONFIG_BLK_DEV_INTEGRITY is not set
116 119
@@ -156,6 +159,7 @@ CONFIG_CPU_SUBTYPE_SH7751R=y
156# CONFIG_CPU_SUBTYPE_SH7760 is not set 159# CONFIG_CPU_SUBTYPE_SH7760 is not set
157# CONFIG_CPU_SUBTYPE_SH4_202 is not set 160# CONFIG_CPU_SUBTYPE_SH4_202 is not set
158# CONFIG_CPU_SUBTYPE_SH7723 is not set 161# CONFIG_CPU_SUBTYPE_SH7723 is not set
162# CONFIG_CPU_SUBTYPE_SH7724 is not set
159# CONFIG_CPU_SUBTYPE_SH7763 is not set 163# CONFIG_CPU_SUBTYPE_SH7763 is not set
160# CONFIG_CPU_SUBTYPE_SH7770 is not set 164# CONFIG_CPU_SUBTYPE_SH7770 is not set
161# CONFIG_CPU_SUBTYPE_SH7780 is not set 165# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -165,8 +169,6 @@ CONFIG_CPU_SUBTYPE_SH7751R=y
165# CONFIG_CPU_SUBTYPE_SH7343 is not set 169# CONFIG_CPU_SUBTYPE_SH7343 is not set
166# CONFIG_CPU_SUBTYPE_SH7722 is not set 170# CONFIG_CPU_SUBTYPE_SH7722 is not set
167# CONFIG_CPU_SUBTYPE_SH7366 is not set 171# CONFIG_CPU_SUBTYPE_SH7366 is not set
168# CONFIG_CPU_SUBTYPE_SH5_101 is not set
169# CONFIG_CPU_SUBTYPE_SH5_103 is not set
170 172
171# 173#
172# Memory management options 174# Memory management options
@@ -302,8 +304,6 @@ CONFIG_CMDLINE="console=tty0 console=ttySC0,115200 root=/dev/sda1 earlyprintk=se
302# 304#
303CONFIG_PCI=y 305CONFIG_PCI=y
304CONFIG_SH_PCIDMA_NONCOHERENT=y 306CONFIG_SH_PCIDMA_NONCOHERENT=y
305CONFIG_PCI_AUTO=y
306CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
307# CONFIG_PCIEPORTBUS is not set 307# CONFIG_PCIEPORTBUS is not set
308# CONFIG_ARCH_SUPPORTS_MSI is not set 308# CONFIG_ARCH_SUPPORTS_MSI is not set
309CONFIG_PCI_LEGACY=y 309CONFIG_PCI_LEGACY=y
@@ -513,6 +513,7 @@ CONFIG_SCSI_LOWLEVEL=y
513# CONFIG_SCSI_MPT2SAS is not set 513# CONFIG_SCSI_MPT2SAS is not set
514# CONFIG_SCSI_HPTIOP is not set 514# CONFIG_SCSI_HPTIOP is not set
515# CONFIG_LIBFC is not set 515# CONFIG_LIBFC is not set
516# CONFIG_LIBFCOE is not set
516# CONFIG_FCOE is not set 517# CONFIG_FCOE is not set
517# CONFIG_SCSI_DMX3191D is not set 518# CONFIG_SCSI_DMX3191D is not set
518# CONFIG_SCSI_FUTURE_DOMAIN is not set 519# CONFIG_SCSI_FUTURE_DOMAIN is not set
@@ -672,6 +673,7 @@ CONFIG_NETDEV_1000=y
672# CONFIG_E1000E is not set 673# CONFIG_E1000E is not set
673# CONFIG_IP1000 is not set 674# CONFIG_IP1000 is not set
674# CONFIG_IGB is not set 675# CONFIG_IGB is not set
676# CONFIG_IGBVF is not set
675# CONFIG_NS83820 is not set 677# CONFIG_NS83820 is not set
676# CONFIG_HAMACHI is not set 678# CONFIG_HAMACHI is not set
677# CONFIG_YELLOWFIN is not set 679# CONFIG_YELLOWFIN is not set
@@ -695,6 +697,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
695# CONFIG_IXGBE is not set 697# CONFIG_IXGBE is not set
696# CONFIG_IXGB is not set 698# CONFIG_IXGB is not set
697# CONFIG_S2IO is not set 699# CONFIG_S2IO is not set
700# CONFIG_VXGE is not set
698# CONFIG_MYRI10GE is not set 701# CONFIG_MYRI10GE is not set
699# CONFIG_NETXEN_NIC is not set 702# CONFIG_NETXEN_NIC is not set
700# CONFIG_NIU is not set 703# CONFIG_NIU is not set
@@ -793,6 +796,7 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
793# 796#
794# Non-8250 serial port support 797# Non-8250 serial port support
795# 798#
799# CONFIG_SERIAL_MAX3100 is not set
796CONFIG_SERIAL_SH_SCI=y 800CONFIG_SERIAL_SH_SCI=y
797CONFIG_SERIAL_SH_SCI_NR_UARTS=1 801CONFIG_SERIAL_SH_SCI_NR_UARTS=1
798CONFIG_SERIAL_SH_SCI_CONSOLE=y 802CONFIG_SERIAL_SH_SCI_CONSOLE=y
@@ -1079,15 +1083,17 @@ CONFIG_USB_HID=y
1079# 1083#
1080# Special HID drivers 1084# Special HID drivers
1081# 1085#
1082CONFIG_HID_COMPAT=y
1083CONFIG_HID_A4TECH=y 1086CONFIG_HID_A4TECH=y
1084CONFIG_HID_APPLE=y 1087CONFIG_HID_APPLE=y
1085CONFIG_HID_BELKIN=y 1088CONFIG_HID_BELKIN=y
1086CONFIG_HID_CHERRY=y 1089CONFIG_HID_CHERRY=y
1087CONFIG_HID_CHICONY=y 1090CONFIG_HID_CHICONY=y
1088CONFIG_HID_CYPRESS=y 1091CONFIG_HID_CYPRESS=y
1092# CONFIG_DRAGONRISE_FF is not set
1089CONFIG_HID_EZKEY=y 1093CONFIG_HID_EZKEY=y
1094# CONFIG_HID_KYE is not set
1090CONFIG_HID_GYRATION=y 1095CONFIG_HID_GYRATION=y
1096# CONFIG_HID_KENSINGTON is not set
1091CONFIG_HID_LOGITECH=y 1097CONFIG_HID_LOGITECH=y
1092# CONFIG_LOGITECH_FF is not set 1098# CONFIG_LOGITECH_FF is not set
1093# CONFIG_LOGIRUMBLEPAD2_FF is not set 1099# CONFIG_LOGIRUMBLEPAD2_FF is not set
@@ -1291,6 +1297,11 @@ CONFIG_INOTIFY_USER=y
1291# CONFIG_FUSE_FS is not set 1297# CONFIG_FUSE_FS is not set
1292 1298
1293# 1299#
1300# Caches
1301#
1302# CONFIG_FSCACHE is not set
1303
1304#
1294# CD-ROM/DVD Filesystems 1305# CD-ROM/DVD Filesystems
1295# 1306#
1296# CONFIG_ISO9660_FS is not set 1307# CONFIG_ISO9660_FS is not set
@@ -1337,6 +1348,7 @@ CONFIG_MINIX_FS=y
1337# CONFIG_ROMFS_FS is not set 1348# CONFIG_ROMFS_FS is not set
1338# CONFIG_SYSV_FS is not set 1349# CONFIG_SYSV_FS is not set
1339# CONFIG_UFS_FS is not set 1350# CONFIG_UFS_FS is not set
1351# CONFIG_NILFS2_FS is not set
1340CONFIG_NETWORK_FILESYSTEMS=y 1352CONFIG_NETWORK_FILESYSTEMS=y
1341# CONFIG_NFS_FS is not set 1353# CONFIG_NFS_FS is not set
1342# CONFIG_NFSD is not set 1354# CONFIG_NFSD is not set
@@ -1417,11 +1429,25 @@ CONFIG_HAVE_DYNAMIC_FTRACE=y
1417CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1429CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1418CONFIG_RING_BUFFER=y 1430CONFIG_RING_BUFFER=y
1419CONFIG_TRACING=y 1431CONFIG_TRACING=y
1432CONFIG_TRACING_SUPPORT=y
1420 1433
1421# 1434#
1422# Tracers 1435# Tracers
1423# 1436#
1437# CONFIG_FUNCTION_TRACER is not set
1438# CONFIG_IRQSOFF_TRACER is not set
1439# CONFIG_SCHED_TRACER is not set
1440# CONFIG_CONTEXT_SWITCH_TRACER is not set
1441# CONFIG_EVENT_TRACER is not set
1442# CONFIG_BOOT_TRACER is not set
1443# CONFIG_TRACE_BRANCH_PROFILING is not set
1444# CONFIG_STACK_TRACER is not set
1445# CONFIG_KMEMTRACE is not set
1446# CONFIG_WORKQUEUE_TRACER is not set
1447# CONFIG_BLK_DEV_IO_TRACE is not set
1448# CONFIG_FTRACE_STARTUP_TEST is not set
1424# CONFIG_DYNAMIC_DEBUG is not set 1449# CONFIG_DYNAMIC_DEBUG is not set
1450# CONFIG_DMA_API_DEBUG is not set
1425# CONFIG_SAMPLES is not set 1451# CONFIG_SAMPLES is not set
1426CONFIG_HAVE_ARCH_KGDB=y 1452CONFIG_HAVE_ARCH_KGDB=y
1427# CONFIG_SH_STANDARD_BIOS is not set 1453# CONFIG_SH_STANDARD_BIOS is not set
@@ -1524,6 +1550,7 @@ CONFIG_CRYPTO=y
1524# CONFIG_CRYPTO_ANSI_CPRNG is not set 1550# CONFIG_CRYPTO_ANSI_CPRNG is not set
1525CONFIG_CRYPTO_HW=y 1551CONFIG_CRYPTO_HW=y
1526# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1552# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1553CONFIG_BINARY_PRINTF=y
1527 1554
1528# 1555#
1529# Library routines 1556# Library routines
diff --git a/arch/sh/configs/rts7751r2dplus_defconfig b/arch/sh/configs/rts7751r2dplus_defconfig
index 8feef629e49c..a860435b8847 100644
--- a/arch/sh/configs/rts7751r2dplus_defconfig
+++ b/arch/sh/configs/rts7751r2dplus_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:34:12 2009 4# Mon Apr 27 12:59:01 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -70,6 +71,7 @@ CONFIG_UID16=y
70# CONFIG_SYSCTL_SYSCALL is not set 71# CONFIG_SYSCTL_SYSCALL is not set
71CONFIG_KALLSYMS=y 72CONFIG_KALLSYMS=y
72# CONFIG_KALLSYMS_EXTRA_PASS is not set 73# CONFIG_KALLSYMS_EXTRA_PASS is not set
74# CONFIG_STRIP_ASM_SYMS is not set
73CONFIG_HOTPLUG=y 75CONFIG_HOTPLUG=y
74CONFIG_PRINTK=y 76CONFIG_PRINTK=y
75CONFIG_BUG=y 77CONFIG_BUG=y
@@ -99,6 +101,8 @@ CONFIG_HAVE_KPROBES=y
99CONFIG_HAVE_KRETPROBES=y 101CONFIG_HAVE_KRETPROBES=y
100CONFIG_HAVE_ARCH_TRACEHOOK=y 102CONFIG_HAVE_ARCH_TRACEHOOK=y
101CONFIG_HAVE_CLK=y 103CONFIG_HAVE_CLK=y
104CONFIG_HAVE_DMA_API_DEBUG=y
105# CONFIG_SLOW_WORK is not set
102CONFIG_HAVE_GENERIC_DMA_COHERENT=y 106CONFIG_HAVE_GENERIC_DMA_COHERENT=y
103CONFIG_SLABINFO=y 107CONFIG_SLABINFO=y
104CONFIG_RT_MUTEXES=y 108CONFIG_RT_MUTEXES=y
@@ -110,7 +114,6 @@ CONFIG_MODULES=y
110# CONFIG_MODULE_SRCVERSION_ALL is not set 114# CONFIG_MODULE_SRCVERSION_ALL is not set
111CONFIG_BLOCK=y 115CONFIG_BLOCK=y
112# CONFIG_LBD is not set 116# CONFIG_LBD is not set
113# CONFIG_BLK_DEV_IO_TRACE is not set
114# CONFIG_BLK_DEV_BSG is not set 117# CONFIG_BLK_DEV_BSG is not set
115# CONFIG_BLK_DEV_INTEGRITY is not set 118# CONFIG_BLK_DEV_INTEGRITY is not set
116 119
@@ -156,6 +159,7 @@ CONFIG_CPU_SUBTYPE_SH7751R=y
156# CONFIG_CPU_SUBTYPE_SH7760 is not set 159# CONFIG_CPU_SUBTYPE_SH7760 is not set
157# CONFIG_CPU_SUBTYPE_SH4_202 is not set 160# CONFIG_CPU_SUBTYPE_SH4_202 is not set
158# CONFIG_CPU_SUBTYPE_SH7723 is not set 161# CONFIG_CPU_SUBTYPE_SH7723 is not set
162# CONFIG_CPU_SUBTYPE_SH7724 is not set
159# CONFIG_CPU_SUBTYPE_SH7763 is not set 163# CONFIG_CPU_SUBTYPE_SH7763 is not set
160# CONFIG_CPU_SUBTYPE_SH7770 is not set 164# CONFIG_CPU_SUBTYPE_SH7770 is not set
161# CONFIG_CPU_SUBTYPE_SH7780 is not set 165# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -165,8 +169,6 @@ CONFIG_CPU_SUBTYPE_SH7751R=y
165# CONFIG_CPU_SUBTYPE_SH7343 is not set 169# CONFIG_CPU_SUBTYPE_SH7343 is not set
166# CONFIG_CPU_SUBTYPE_SH7722 is not set 170# CONFIG_CPU_SUBTYPE_SH7722 is not set
167# CONFIG_CPU_SUBTYPE_SH7366 is not set 171# CONFIG_CPU_SUBTYPE_SH7366 is not set
168# CONFIG_CPU_SUBTYPE_SH5_101 is not set
169# CONFIG_CPU_SUBTYPE_SH5_103 is not set
170 172
171# 173#
172# Memory management options 174# Memory management options
@@ -302,8 +304,6 @@ CONFIG_CMDLINE="console=tty0 console=ttySC0,115200 root=/dev/sda1 earlyprintk=se
302# 304#
303CONFIG_PCI=y 305CONFIG_PCI=y
304CONFIG_SH_PCIDMA_NONCOHERENT=y 306CONFIG_SH_PCIDMA_NONCOHERENT=y
305CONFIG_PCI_AUTO=y
306CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
307# CONFIG_PCIEPORTBUS is not set 307# CONFIG_PCIEPORTBUS is not set
308# CONFIG_ARCH_SUPPORTS_MSI is not set 308# CONFIG_ARCH_SUPPORTS_MSI is not set
309CONFIG_PCI_LEGACY=y 309CONFIG_PCI_LEGACY=y
@@ -424,7 +424,92 @@ CONFIG_FIRMWARE_IN_KERNEL=y
424CONFIG_EXTRA_FIRMWARE="" 424CONFIG_EXTRA_FIRMWARE=""
425# CONFIG_SYS_HYPERVISOR is not set 425# CONFIG_SYS_HYPERVISOR is not set
426# CONFIG_CONNECTOR is not set 426# CONFIG_CONNECTOR is not set
427# CONFIG_MTD is not set 427CONFIG_MTD=y
428# CONFIG_MTD_DEBUG is not set
429CONFIG_MTD_CONCAT=y
430CONFIG_MTD_PARTITIONS=y
431# CONFIG_MTD_TESTS is not set
432# CONFIG_MTD_REDBOOT_PARTS is not set
433CONFIG_MTD_CMDLINE_PARTS=y
434# CONFIG_MTD_AR7_PARTS is not set
435
436#
437# User Modules And Translation Layers
438#
439CONFIG_MTD_CHAR=y
440# CONFIG_MTD_BLKDEVS is not set
441# CONFIG_MTD_BLOCK is not set
442# CONFIG_MTD_BLOCK_RO is not set
443# CONFIG_FTL is not set
444# CONFIG_NFTL is not set
445# CONFIG_INFTL is not set
446# CONFIG_RFD_FTL is not set
447# CONFIG_SSFDC is not set
448# CONFIG_MTD_OOPS is not set
449
450#
451# RAM/ROM/Flash chip drivers
452#
453CONFIG_MTD_CFI=y
454# CONFIG_MTD_JEDECPROBE is not set
455CONFIG_MTD_GEN_PROBE=y
456# CONFIG_MTD_CFI_ADV_OPTIONS is not set
457CONFIG_MTD_MAP_BANK_WIDTH_1=y
458CONFIG_MTD_MAP_BANK_WIDTH_2=y
459CONFIG_MTD_MAP_BANK_WIDTH_4=y
460# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
461# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
462# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
463CONFIG_MTD_CFI_I1=y
464CONFIG_MTD_CFI_I2=y
465# CONFIG_MTD_CFI_I4 is not set
466# CONFIG_MTD_CFI_I8 is not set
467# CONFIG_MTD_CFI_INTELEXT is not set
468CONFIG_MTD_CFI_AMDSTD=y
469# CONFIG_MTD_CFI_STAA is not set
470CONFIG_MTD_CFI_UTIL=y
471# CONFIG_MTD_RAM is not set
472# CONFIG_MTD_ROM is not set
473# CONFIG_MTD_ABSENT is not set
474
475#
476# Mapping drivers for chip access
477#
478# CONFIG_MTD_COMPLEX_MAPPINGS is not set
479CONFIG_MTD_PHYSMAP=y
480# CONFIG_MTD_PHYSMAP_COMPAT is not set
481# CONFIG_MTD_INTEL_VR_NOR is not set
482# CONFIG_MTD_PLATRAM is not set
483
484#
485# Self-contained MTD device drivers
486#
487# CONFIG_MTD_PMC551 is not set
488# CONFIG_MTD_DATAFLASH is not set
489# CONFIG_MTD_M25P80 is not set
490# CONFIG_MTD_SLRAM is not set
491# CONFIG_MTD_PHRAM is not set
492# CONFIG_MTD_MTDRAM is not set
493# CONFIG_MTD_BLOCK2MTD is not set
494
495#
496# Disk-On-Chip Device Drivers
497#
498# CONFIG_MTD_DOC2000 is not set
499# CONFIG_MTD_DOC2001 is not set
500# CONFIG_MTD_DOC2001PLUS is not set
501# CONFIG_MTD_NAND is not set
502# CONFIG_MTD_ONENAND is not set
503
504#
505# LPDDR flash memory drivers
506#
507# CONFIG_MTD_LPDDR is not set
508
509#
510# UBI - Unsorted block images
511#
512# CONFIG_MTD_UBI is not set
428# CONFIG_PARPORT is not set 513# CONFIG_PARPORT is not set
429CONFIG_BLK_DEV=y 514CONFIG_BLK_DEV=y
430# CONFIG_BLK_CPQ_CISS_DA is not set 515# CONFIG_BLK_CPQ_CISS_DA is not set
@@ -513,6 +598,7 @@ CONFIG_SCSI_LOWLEVEL=y
513# CONFIG_SCSI_MPT2SAS is not set 598# CONFIG_SCSI_MPT2SAS is not set
514# CONFIG_SCSI_HPTIOP is not set 599# CONFIG_SCSI_HPTIOP is not set
515# CONFIG_LIBFC is not set 600# CONFIG_LIBFC is not set
601# CONFIG_LIBFCOE is not set
516# CONFIG_FCOE is not set 602# CONFIG_FCOE is not set
517# CONFIG_SCSI_DMX3191D is not set 603# CONFIG_SCSI_DMX3191D is not set
518# CONFIG_SCSI_FUTURE_DOMAIN is not set 604# CONFIG_SCSI_FUTURE_DOMAIN is not set
@@ -672,6 +758,7 @@ CONFIG_NETDEV_1000=y
672# CONFIG_E1000E is not set 758# CONFIG_E1000E is not set
673# CONFIG_IP1000 is not set 759# CONFIG_IP1000 is not set
674# CONFIG_IGB is not set 760# CONFIG_IGB is not set
761# CONFIG_IGBVF is not set
675# CONFIG_NS83820 is not set 762# CONFIG_NS83820 is not set
676# CONFIG_HAMACHI is not set 763# CONFIG_HAMACHI is not set
677# CONFIG_YELLOWFIN is not set 764# CONFIG_YELLOWFIN is not set
@@ -695,6 +782,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
695# CONFIG_IXGBE is not set 782# CONFIG_IXGBE is not set
696# CONFIG_IXGB is not set 783# CONFIG_IXGB is not set
697# CONFIG_S2IO is not set 784# CONFIG_S2IO is not set
785# CONFIG_VXGE is not set
698# CONFIG_MYRI10GE is not set 786# CONFIG_MYRI10GE is not set
699# CONFIG_NETXEN_NIC is not set 787# CONFIG_NETXEN_NIC is not set
700# CONFIG_NIU is not set 788# CONFIG_NIU is not set
@@ -793,6 +881,7 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
793# 881#
794# Non-8250 serial port support 882# Non-8250 serial port support
795# 883#
884# CONFIG_SERIAL_MAX3100 is not set
796CONFIG_SERIAL_SH_SCI=y 885CONFIG_SERIAL_SH_SCI=y
797CONFIG_SERIAL_SH_SCI_NR_UARTS=1 886CONFIG_SERIAL_SH_SCI_NR_UARTS=1
798CONFIG_SERIAL_SH_SCI_CONSOLE=y 887CONFIG_SERIAL_SH_SCI_CONSOLE=y
@@ -1079,15 +1168,17 @@ CONFIG_USB_HID=y
1079# 1168#
1080# Special HID drivers 1169# Special HID drivers
1081# 1170#
1082CONFIG_HID_COMPAT=y
1083CONFIG_HID_A4TECH=y 1171CONFIG_HID_A4TECH=y
1084CONFIG_HID_APPLE=y 1172CONFIG_HID_APPLE=y
1085CONFIG_HID_BELKIN=y 1173CONFIG_HID_BELKIN=y
1086CONFIG_HID_CHERRY=y 1174CONFIG_HID_CHERRY=y
1087CONFIG_HID_CHICONY=y 1175CONFIG_HID_CHICONY=y
1088CONFIG_HID_CYPRESS=y 1176CONFIG_HID_CYPRESS=y
1177# CONFIG_DRAGONRISE_FF is not set
1089CONFIG_HID_EZKEY=y 1178CONFIG_HID_EZKEY=y
1179# CONFIG_HID_KYE is not set
1090CONFIG_HID_GYRATION=y 1180CONFIG_HID_GYRATION=y
1181# CONFIG_HID_KENSINGTON is not set
1091CONFIG_HID_LOGITECH=y 1182CONFIG_HID_LOGITECH=y
1092# CONFIG_LOGITECH_FF is not set 1183# CONFIG_LOGITECH_FF is not set
1093# CONFIG_LOGIRUMBLEPAD2_FF is not set 1184# CONFIG_LOGIRUMBLEPAD2_FF is not set
@@ -1291,6 +1382,11 @@ CONFIG_INOTIFY_USER=y
1291# CONFIG_FUSE_FS is not set 1382# CONFIG_FUSE_FS is not set
1292 1383
1293# 1384#
1385# Caches
1386#
1387# CONFIG_FSCACHE is not set
1388
1389#
1294# CD-ROM/DVD Filesystems 1390# CD-ROM/DVD Filesystems
1295# 1391#
1296# CONFIG_ISO9660_FS is not set 1392# CONFIG_ISO9660_FS is not set
@@ -1337,6 +1433,7 @@ CONFIG_MINIX_FS=y
1337# CONFIG_ROMFS_FS is not set 1433# CONFIG_ROMFS_FS is not set
1338# CONFIG_SYSV_FS is not set 1434# CONFIG_SYSV_FS is not set
1339# CONFIG_UFS_FS is not set 1435# CONFIG_UFS_FS is not set
1436# CONFIG_NILFS2_FS is not set
1340CONFIG_NETWORK_FILESYSTEMS=y 1437CONFIG_NETWORK_FILESYSTEMS=y
1341# CONFIG_NFS_FS is not set 1438# CONFIG_NFS_FS is not set
1342# CONFIG_NFSD is not set 1439# CONFIG_NFSD is not set
@@ -1417,11 +1514,25 @@ CONFIG_HAVE_DYNAMIC_FTRACE=y
1417CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1514CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1418CONFIG_RING_BUFFER=y 1515CONFIG_RING_BUFFER=y
1419CONFIG_TRACING=y 1516CONFIG_TRACING=y
1517CONFIG_TRACING_SUPPORT=y
1420 1518
1421# 1519#
1422# Tracers 1520# Tracers
1423# 1521#
1522# CONFIG_FUNCTION_TRACER is not set
1523# CONFIG_IRQSOFF_TRACER is not set
1524# CONFIG_SCHED_TRACER is not set
1525# CONFIG_CONTEXT_SWITCH_TRACER is not set
1526# CONFIG_EVENT_TRACER is not set
1527# CONFIG_BOOT_TRACER is not set
1528# CONFIG_TRACE_BRANCH_PROFILING is not set
1529# CONFIG_STACK_TRACER is not set
1530# CONFIG_KMEMTRACE is not set
1531# CONFIG_WORKQUEUE_TRACER is not set
1532# CONFIG_BLK_DEV_IO_TRACE is not set
1533# CONFIG_FTRACE_STARTUP_TEST is not set
1424# CONFIG_DYNAMIC_DEBUG is not set 1534# CONFIG_DYNAMIC_DEBUG is not set
1535# CONFIG_DMA_API_DEBUG is not set
1425# CONFIG_SAMPLES is not set 1536# CONFIG_SAMPLES is not set
1426CONFIG_HAVE_ARCH_KGDB=y 1537CONFIG_HAVE_ARCH_KGDB=y
1427# CONFIG_SH_STANDARD_BIOS is not set 1538# CONFIG_SH_STANDARD_BIOS is not set
@@ -1524,6 +1635,7 @@ CONFIG_CRYPTO=y
1524# CONFIG_CRYPTO_ANSI_CPRNG is not set 1635# CONFIG_CRYPTO_ANSI_CPRNG is not set
1525CONFIG_CRYPTO_HW=y 1636CONFIG_CRYPTO_HW=y
1526# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1637# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1638CONFIG_BINARY_PRINTF=y
1527 1639
1528# 1640#
1529# Library routines 1641# Library routines
diff --git a/arch/sh/configs/sdk7780_defconfig b/arch/sh/configs/sdk7780_defconfig
index 739e2299ae80..a629b79a1844 100644
--- a/arch/sh/configs/sdk7780_defconfig
+++ b/arch/sh/configs/sdk7780_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:34:43 2009 4# Mon Apr 27 12:59:32 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -41,6 +42,7 @@ CONFIG_SWAP=y
41CONFIG_SYSVIPC=y 42CONFIG_SYSVIPC=y
42CONFIG_SYSVIPC_SYSCTL=y 43CONFIG_SYSVIPC_SYSCTL=y
43CONFIG_POSIX_MQUEUE=y 44CONFIG_POSIX_MQUEUE=y
45CONFIG_POSIX_MQUEUE_SYSCTL=y
44CONFIG_BSD_PROCESS_ACCT=y 46CONFIG_BSD_PROCESS_ACCT=y
45# CONFIG_BSD_PROCESS_ACCT_V3 is not set 47# CONFIG_BSD_PROCESS_ACCT_V3 is not set
46# CONFIG_TASKSTATS is not set 48# CONFIG_TASKSTATS is not set
@@ -73,6 +75,7 @@ CONFIG_SYSCTL_SYSCALL=y
73CONFIG_KALLSYMS=y 75CONFIG_KALLSYMS=y
74CONFIG_KALLSYMS_ALL=y 76CONFIG_KALLSYMS_ALL=y
75# CONFIG_KALLSYMS_EXTRA_PASS is not set 77# CONFIG_KALLSYMS_EXTRA_PASS is not set
78# CONFIG_STRIP_ASM_SYMS is not set
76CONFIG_HOTPLUG=y 79CONFIG_HOTPLUG=y
77CONFIG_PRINTK=y 80CONFIG_PRINTK=y
78CONFIG_BUG=y 81CONFIG_BUG=y
@@ -93,6 +96,7 @@ CONFIG_COMPAT_BRK=y
93CONFIG_SLUB=y 96CONFIG_SLUB=y
94# CONFIG_SLOB is not set 97# CONFIG_SLOB is not set
95# CONFIG_PROFILING is not set 98# CONFIG_PROFILING is not set
99# CONFIG_MARKERS is not set
96CONFIG_HAVE_OPROFILE=y 100CONFIG_HAVE_OPROFILE=y
97# CONFIG_KPROBES is not set 101# CONFIG_KPROBES is not set
98CONFIG_HAVE_IOREMAP_PROT=y 102CONFIG_HAVE_IOREMAP_PROT=y
@@ -100,6 +104,8 @@ CONFIG_HAVE_KPROBES=y
100CONFIG_HAVE_KRETPROBES=y 104CONFIG_HAVE_KRETPROBES=y
101CONFIG_HAVE_ARCH_TRACEHOOK=y 105CONFIG_HAVE_ARCH_TRACEHOOK=y
102CONFIG_HAVE_CLK=y 106CONFIG_HAVE_CLK=y
107CONFIG_HAVE_DMA_API_DEBUG=y
108# CONFIG_SLOW_WORK is not set
103CONFIG_HAVE_GENERIC_DMA_COHERENT=y 109CONFIG_HAVE_GENERIC_DMA_COHERENT=y
104CONFIG_SLABINFO=y 110CONFIG_SLABINFO=y
105CONFIG_RT_MUTEXES=y 111CONFIG_RT_MUTEXES=y
@@ -112,7 +118,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y
112# CONFIG_MODULE_SRCVERSION_ALL is not set 118# CONFIG_MODULE_SRCVERSION_ALL is not set
113CONFIG_BLOCK=y 119CONFIG_BLOCK=y
114CONFIG_LBD=y 120CONFIG_LBD=y
115# CONFIG_BLK_DEV_IO_TRACE is not set
116# CONFIG_BLK_DEV_BSG is not set 121# CONFIG_BLK_DEV_BSG is not set
117# CONFIG_BLK_DEV_INTEGRITY is not set 122# CONFIG_BLK_DEV_INTEGRITY is not set
118 123
@@ -159,6 +164,7 @@ CONFIG_CPU_SH4A=y
159# CONFIG_CPU_SUBTYPE_SH7760 is not set 164# CONFIG_CPU_SUBTYPE_SH7760 is not set
160# CONFIG_CPU_SUBTYPE_SH4_202 is not set 165# CONFIG_CPU_SUBTYPE_SH4_202 is not set
161# CONFIG_CPU_SUBTYPE_SH7723 is not set 166# CONFIG_CPU_SUBTYPE_SH7723 is not set
167# CONFIG_CPU_SUBTYPE_SH7724 is not set
162# CONFIG_CPU_SUBTYPE_SH7763 is not set 168# CONFIG_CPU_SUBTYPE_SH7763 is not set
163# CONFIG_CPU_SUBTYPE_SH7770 is not set 169# CONFIG_CPU_SUBTYPE_SH7770 is not set
164CONFIG_CPU_SUBTYPE_SH7780=y 170CONFIG_CPU_SUBTYPE_SH7780=y
@@ -168,8 +174,6 @@ CONFIG_CPU_SUBTYPE_SH7780=y
168# CONFIG_CPU_SUBTYPE_SH7343 is not set 174# CONFIG_CPU_SUBTYPE_SH7343 is not set
169# CONFIG_CPU_SUBTYPE_SH7722 is not set 175# CONFIG_CPU_SUBTYPE_SH7722 is not set
170# CONFIG_CPU_SUBTYPE_SH7366 is not set 176# CONFIG_CPU_SUBTYPE_SH7366 is not set
171# CONFIG_CPU_SUBTYPE_SH5_101 is not set
172# CONFIG_CPU_SUBTYPE_SH5_103 is not set
173 177
174# 178#
175# Memory management options 179# Memory management options
@@ -310,8 +314,6 @@ CONFIG_CMDLINE="mem=128M console=tty0 console=ttySC0,115200 ip=bootp root=/dev/n
310# 314#
311CONFIG_PCI=y 315CONFIG_PCI=y
312CONFIG_SH_PCIDMA_NONCOHERENT=y 316CONFIG_SH_PCIDMA_NONCOHERENT=y
313CONFIG_PCI_AUTO=y
314CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
315# CONFIG_PCIEPORTBUS is not set 317# CONFIG_PCIEPORTBUS is not set
316# CONFIG_ARCH_SUPPORTS_MSI is not set 318# CONFIG_ARCH_SUPPORTS_MSI is not set
317# CONFIG_PCI_LEGACY is not set 319# CONFIG_PCI_LEGACY is not set
@@ -646,6 +648,7 @@ CONFIG_SCSI_LOWLEVEL=y
646# CONFIG_SCSI_MPT2SAS is not set 648# CONFIG_SCSI_MPT2SAS is not set
647# CONFIG_SCSI_HPTIOP is not set 649# CONFIG_SCSI_HPTIOP is not set
648# CONFIG_LIBFC is not set 650# CONFIG_LIBFC is not set
651# CONFIG_LIBFCOE is not set
649# CONFIG_FCOE is not set 652# CONFIG_FCOE is not set
650# CONFIG_SCSI_DMX3191D is not set 653# CONFIG_SCSI_DMX3191D is not set
651# CONFIG_SCSI_FUTURE_DOMAIN is not set 654# CONFIG_SCSI_FUTURE_DOMAIN is not set
@@ -1091,15 +1094,17 @@ CONFIG_USB_HID=y
1091# 1094#
1092# Special HID drivers 1095# Special HID drivers
1093# 1096#
1094CONFIG_HID_COMPAT=y
1095CONFIG_HID_A4TECH=y 1097CONFIG_HID_A4TECH=y
1096CONFIG_HID_APPLE=y 1098CONFIG_HID_APPLE=y
1097CONFIG_HID_BELKIN=y 1099CONFIG_HID_BELKIN=y
1098CONFIG_HID_CHERRY=y 1100CONFIG_HID_CHERRY=y
1099CONFIG_HID_CHICONY=y 1101CONFIG_HID_CHICONY=y
1100CONFIG_HID_CYPRESS=y 1102CONFIG_HID_CYPRESS=y
1103# CONFIG_DRAGONRISE_FF is not set
1101CONFIG_HID_EZKEY=y 1104CONFIG_HID_EZKEY=y
1105# CONFIG_HID_KYE is not set
1102CONFIG_HID_GYRATION=y 1106CONFIG_HID_GYRATION=y
1107# CONFIG_HID_KENSINGTON is not set
1103CONFIG_HID_LOGITECH=y 1108CONFIG_HID_LOGITECH=y
1104# CONFIG_LOGITECH_FF is not set 1109# CONFIG_LOGITECH_FF is not set
1105# CONFIG_LOGIRUMBLEPAD2_FF is not set 1110# CONFIG_LOGIRUMBLEPAD2_FF is not set
@@ -1257,6 +1262,7 @@ CONFIG_EXT2_FS_POSIX_ACL=y
1257# CONFIG_EXT2_FS_SECURITY is not set 1262# CONFIG_EXT2_FS_SECURITY is not set
1258# CONFIG_EXT2_FS_XIP is not set 1263# CONFIG_EXT2_FS_XIP is not set
1259CONFIG_EXT3_FS=y 1264CONFIG_EXT3_FS=y
1265# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1260CONFIG_EXT3_FS_XATTR=y 1266CONFIG_EXT3_FS_XATTR=y
1261CONFIG_EXT3_FS_POSIX_ACL=y 1267CONFIG_EXT3_FS_POSIX_ACL=y
1262# CONFIG_EXT3_FS_SECURITY is not set 1268# CONFIG_EXT3_FS_SECURITY is not set
@@ -1281,6 +1287,11 @@ CONFIG_AUTOFS4_FS=y
1281CONFIG_GENERIC_ACL=y 1287CONFIG_GENERIC_ACL=y
1282 1288
1283# 1289#
1290# Caches
1291#
1292# CONFIG_FSCACHE is not set
1293
1294#
1284# CD-ROM/DVD Filesystems 1295# CD-ROM/DVD Filesystems
1285# 1296#
1286CONFIG_ISO9660_FS=y 1297CONFIG_ISO9660_FS=y
@@ -1331,6 +1342,7 @@ CONFIG_MINIX_FS=y
1331# CONFIG_ROMFS_FS is not set 1342# CONFIG_ROMFS_FS is not set
1332# CONFIG_SYSV_FS is not set 1343# CONFIG_SYSV_FS is not set
1333# CONFIG_UFS_FS is not set 1344# CONFIG_UFS_FS is not set
1345# CONFIG_NILFS2_FS is not set
1334CONFIG_NETWORK_FILESYSTEMS=y 1346CONFIG_NETWORK_FILESYSTEMS=y
1335CONFIG_NFS_FS=y 1347CONFIG_NFS_FS=y
1336CONFIG_NFS_V3=y 1348CONFIG_NFS_V3=y
@@ -1418,6 +1430,9 @@ CONFIG_DEBUG_KERNEL=y
1418CONFIG_DETECT_SOFTLOCKUP=y 1430CONFIG_DETECT_SOFTLOCKUP=y
1419# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set 1431# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1420CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 1432CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1433CONFIG_DETECT_HUNG_TASK=y
1434# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1435CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1421# CONFIG_SCHED_DEBUG is not set 1436# CONFIG_SCHED_DEBUG is not set
1422# CONFIG_SCHEDSTATS is not set 1437# CONFIG_SCHEDSTATS is not set
1423CONFIG_TIMER_STATS=y 1438CONFIG_TIMER_STATS=y
@@ -1455,6 +1470,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
1455CONFIG_HAVE_FUNCTION_TRACER=y 1470CONFIG_HAVE_FUNCTION_TRACER=y
1456CONFIG_HAVE_DYNAMIC_FTRACE=y 1471CONFIG_HAVE_DYNAMIC_FTRACE=y
1457CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1472CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1473CONFIG_TRACING_SUPPORT=y
1458 1474
1459# 1475#
1460# Tracers 1476# Tracers
@@ -1464,9 +1480,14 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1464# CONFIG_PREEMPT_TRACER is not set 1480# CONFIG_PREEMPT_TRACER is not set
1465# CONFIG_SCHED_TRACER is not set 1481# CONFIG_SCHED_TRACER is not set
1466# CONFIG_CONTEXT_SWITCH_TRACER is not set 1482# CONFIG_CONTEXT_SWITCH_TRACER is not set
1483# CONFIG_EVENT_TRACER is not set
1467# CONFIG_BOOT_TRACER is not set 1484# CONFIG_BOOT_TRACER is not set
1468# CONFIG_TRACE_BRANCH_PROFILING is not set 1485# CONFIG_TRACE_BRANCH_PROFILING is not set
1469# CONFIG_STACK_TRACER is not set 1486# CONFIG_STACK_TRACER is not set
1487# CONFIG_KMEMTRACE is not set
1488# CONFIG_WORKQUEUE_TRACER is not set
1489# CONFIG_BLK_DEV_IO_TRACE is not set
1490# CONFIG_DMA_API_DEBUG is not set
1470# CONFIG_SAMPLES is not set 1491# CONFIG_SAMPLES is not set
1471CONFIG_HAVE_ARCH_KGDB=y 1492CONFIG_HAVE_ARCH_KGDB=y
1472# CONFIG_KGDB is not set 1493# CONFIG_KGDB is not set
@@ -1580,6 +1601,7 @@ CONFIG_CRYPTO_DES=y
1580# CONFIG_CRYPTO_ANSI_CPRNG is not set 1601# CONFIG_CRYPTO_ANSI_CPRNG is not set
1581CONFIG_CRYPTO_HW=y 1602CONFIG_CRYPTO_HW=y
1582# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1603# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1604# CONFIG_BINARY_PRINTF is not set
1583 1605
1584# 1606#
1585# Library routines 1607# Library routines
diff --git a/arch/sh/configs/se7206_defconfig b/arch/sh/configs/se7206_defconfig
index d30e0a7ad9f1..5caf85a3312d 100644
--- a/arch/sh/configs/se7206_defconfig
+++ b/arch/sh/configs/se7206_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:39:37 2009 4# Mon Apr 27 13:01:02 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -40,6 +41,7 @@ CONFIG_LOCALVERSION_AUTO=y
40CONFIG_SYSVIPC=y 41CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y 42CONFIG_SYSVIPC_SYSCTL=y
42CONFIG_POSIX_MQUEUE=y 43CONFIG_POSIX_MQUEUE=y
44CONFIG_POSIX_MQUEUE_SYSCTL=y
43CONFIG_BSD_PROCESS_ACCT=y 45CONFIG_BSD_PROCESS_ACCT=y
44# CONFIG_BSD_PROCESS_ACCT_V3 is not set 46# CONFIG_BSD_PROCESS_ACCT_V3 is not set
45# CONFIG_TASKSTATS is not set 47# CONFIG_TASKSTATS is not set
@@ -63,6 +65,7 @@ CONFIG_CGROUP_DEBUG=y
63CONFIG_CGROUP_NS=y 65CONFIG_CGROUP_NS=y
64# CONFIG_CGROUP_FREEZER is not set 66# CONFIG_CGROUP_FREEZER is not set
65CONFIG_CGROUP_DEVICE=y 67CONFIG_CGROUP_DEVICE=y
68# CONFIG_CPUSETS is not set
66CONFIG_CGROUP_CPUACCT=y 69CONFIG_CGROUP_CPUACCT=y
67CONFIG_RESOURCE_COUNTERS=y 70CONFIG_RESOURCE_COUNTERS=y
68CONFIG_CGROUP_MEM_RES_CTLR=y 71CONFIG_CGROUP_MEM_RES_CTLR=y
@@ -80,7 +83,6 @@ CONFIG_INITRAMFS_SOURCE=""
80CONFIG_RD_GZIP=y 83CONFIG_RD_GZIP=y
81# CONFIG_RD_BZIP2 is not set 84# CONFIG_RD_BZIP2 is not set
82# CONFIG_RD_LZMA is not set 85# CONFIG_RD_LZMA is not set
83CONFIG_INITRAMFS_COMPRESSION_NONE=y
84CONFIG_CC_OPTIMIZE_FOR_SIZE=y 86CONFIG_CC_OPTIMIZE_FOR_SIZE=y
85CONFIG_SYSCTL=y 87CONFIG_SYSCTL=y
86CONFIG_ANON_INODES=y 88CONFIG_ANON_INODES=y
@@ -90,6 +92,7 @@ CONFIG_EMBEDDED=y
90CONFIG_KALLSYMS=y 92CONFIG_KALLSYMS=y
91CONFIG_KALLSYMS_ALL=y 93CONFIG_KALLSYMS_ALL=y
92# CONFIG_KALLSYMS_EXTRA_PASS is not set 94# CONFIG_KALLSYMS_EXTRA_PASS is not set
95# CONFIG_STRIP_ASM_SYMS is not set
93CONFIG_HOTPLUG=y 96CONFIG_HOTPLUG=y
94CONFIG_PRINTK=y 97CONFIG_PRINTK=y
95CONFIG_BUG=y 98CONFIG_BUG=y
@@ -116,6 +119,8 @@ CONFIG_HAVE_KPROBES=y
116CONFIG_HAVE_KRETPROBES=y 119CONFIG_HAVE_KRETPROBES=y
117CONFIG_HAVE_ARCH_TRACEHOOK=y 120CONFIG_HAVE_ARCH_TRACEHOOK=y
118CONFIG_HAVE_CLK=y 121CONFIG_HAVE_CLK=y
122CONFIG_HAVE_DMA_API_DEBUG=y
123# CONFIG_SLOW_WORK is not set
119CONFIG_HAVE_GENERIC_DMA_COHERENT=y 124CONFIG_HAVE_GENERIC_DMA_COHERENT=y
120CONFIG_RT_MUTEXES=y 125CONFIG_RT_MUTEXES=y
121CONFIG_BASE_SMALL=0 126CONFIG_BASE_SMALL=0
@@ -127,7 +132,6 @@ CONFIG_MODULE_UNLOAD=y
127# CONFIG_MODULE_SRCVERSION_ALL is not set 132# CONFIG_MODULE_SRCVERSION_ALL is not set
128CONFIG_BLOCK=y 133CONFIG_BLOCK=y
129# CONFIG_LBD is not set 134# CONFIG_LBD is not set
130# CONFIG_BLK_DEV_IO_TRACE is not set
131# CONFIG_BLK_DEV_BSG is not set 135# CONFIG_BLK_DEV_BSG is not set
132# CONFIG_BLK_DEV_INTEGRITY is not set 136# CONFIG_BLK_DEV_INTEGRITY is not set
133 137
@@ -174,6 +178,7 @@ CONFIG_CPU_SUBTYPE_SH7206=y
174# CONFIG_CPU_SUBTYPE_SH7760 is not set 178# CONFIG_CPU_SUBTYPE_SH7760 is not set
175# CONFIG_CPU_SUBTYPE_SH4_202 is not set 179# CONFIG_CPU_SUBTYPE_SH4_202 is not set
176# CONFIG_CPU_SUBTYPE_SH7723 is not set 180# CONFIG_CPU_SUBTYPE_SH7723 is not set
181# CONFIG_CPU_SUBTYPE_SH7724 is not set
177# CONFIG_CPU_SUBTYPE_SH7763 is not set 182# CONFIG_CPU_SUBTYPE_SH7763 is not set
178# CONFIG_CPU_SUBTYPE_SH7770 is not set 183# CONFIG_CPU_SUBTYPE_SH7770 is not set
179# CONFIG_CPU_SUBTYPE_SH7780 is not set 184# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -183,8 +188,6 @@ CONFIG_CPU_SUBTYPE_SH7206=y
183# CONFIG_CPU_SUBTYPE_SH7343 is not set 188# CONFIG_CPU_SUBTYPE_SH7343 is not set
184# CONFIG_CPU_SUBTYPE_SH7722 is not set 189# CONFIG_CPU_SUBTYPE_SH7722 is not set
185# CONFIG_CPU_SUBTYPE_SH7366 is not set 190# CONFIG_CPU_SUBTYPE_SH7366 is not set
186# CONFIG_CPU_SUBTYPE_SH5_101 is not set
187# CONFIG_CPU_SUBTYPE_SH5_103 is not set
188 191
189# 192#
190# Memory management options 193# Memory management options
@@ -746,6 +749,11 @@ CONFIG_FILE_LOCKING=y
746# CONFIG_FUSE_FS is not set 749# CONFIG_FUSE_FS is not set
747 750
748# 751#
752# Caches
753#
754# CONFIG_FSCACHE is not set
755
756#
749# CD-ROM/DVD Filesystems 757# CD-ROM/DVD Filesystems
750# 758#
751# CONFIG_ISO9660_FS is not set 759# CONFIG_ISO9660_FS is not set
@@ -785,8 +793,13 @@ CONFIG_CRAMFS=y
785# CONFIG_HPFS_FS is not set 793# CONFIG_HPFS_FS is not set
786# CONFIG_QNX4FS_FS is not set 794# CONFIG_QNX4FS_FS is not set
787CONFIG_ROMFS_FS=y 795CONFIG_ROMFS_FS=y
796CONFIG_ROMFS_BACKED_BY_BLOCK=y
797# CONFIG_ROMFS_BACKED_BY_MTD is not set
798# CONFIG_ROMFS_BACKED_BY_BOTH is not set
799CONFIG_ROMFS_ON_BLOCK=y
788# CONFIG_SYSV_FS is not set 800# CONFIG_SYSV_FS is not set
789# CONFIG_UFS_FS is not set 801# CONFIG_UFS_FS is not set
802# CONFIG_NILFS2_FS is not set
790CONFIG_NETWORK_FILESYSTEMS=y 803CONFIG_NETWORK_FILESYSTEMS=y
791CONFIG_NFS_FS=y 804CONFIG_NFS_FS=y
792CONFIG_NFS_V3=y 805CONFIG_NFS_V3=y
@@ -831,6 +844,9 @@ CONFIG_DEBUG_KERNEL=y
831CONFIG_DETECT_SOFTLOCKUP=y 844CONFIG_DETECT_SOFTLOCKUP=y
832# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set 845# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
833CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 846CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
847CONFIG_DETECT_HUNG_TASK=y
848# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
849CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
834CONFIG_SCHED_DEBUG=y 850CONFIG_SCHED_DEBUG=y
835# CONFIG_SCHEDSTATS is not set 851# CONFIG_SCHEDSTATS is not set
836# CONFIG_TIMER_STATS is not set 852# CONFIG_TIMER_STATS is not set
@@ -869,6 +885,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE=y
869CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 885CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
870CONFIG_RING_BUFFER=y 886CONFIG_RING_BUFFER=y
871CONFIG_TRACING=y 887CONFIG_TRACING=y
888CONFIG_TRACING_SUPPORT=y
872 889
873# 890#
874# Tracers 891# Tracers
@@ -876,11 +893,16 @@ CONFIG_TRACING=y
876# CONFIG_FUNCTION_TRACER is not set 893# CONFIG_FUNCTION_TRACER is not set
877# CONFIG_SCHED_TRACER is not set 894# CONFIG_SCHED_TRACER is not set
878# CONFIG_CONTEXT_SWITCH_TRACER is not set 895# CONFIG_CONTEXT_SWITCH_TRACER is not set
896# CONFIG_EVENT_TRACER is not set
879# CONFIG_BOOT_TRACER is not set 897# CONFIG_BOOT_TRACER is not set
880# CONFIG_TRACE_BRANCH_PROFILING is not set 898# CONFIG_TRACE_BRANCH_PROFILING is not set
881# CONFIG_STACK_TRACER is not set 899# CONFIG_STACK_TRACER is not set
900# CONFIG_KMEMTRACE is not set
901# CONFIG_WORKQUEUE_TRACER is not set
902# CONFIG_BLK_DEV_IO_TRACE is not set
882# CONFIG_FTRACE_STARTUP_TEST is not set 903# CONFIG_FTRACE_STARTUP_TEST is not set
883# CONFIG_DYNAMIC_DEBUG is not set 904# CONFIG_DYNAMIC_DEBUG is not set
905# CONFIG_DMA_API_DEBUG is not set
884# CONFIG_SAMPLES is not set 906# CONFIG_SAMPLES is not set
885CONFIG_HAVE_ARCH_KGDB=y 907CONFIG_HAVE_ARCH_KGDB=y
886# CONFIG_KGDB is not set 908# CONFIG_KGDB is not set
@@ -991,6 +1013,7 @@ CONFIG_CRYPTO_LZO=y
991# 1013#
992# CONFIG_CRYPTO_ANSI_CPRNG is not set 1014# CONFIG_CRYPTO_ANSI_CPRNG is not set
993# CONFIG_CRYPTO_HW is not set 1015# CONFIG_CRYPTO_HW is not set
1016CONFIG_BINARY_PRINTF=y
994 1017
995# 1018#
996# Library routines 1019# Library routines
diff --git a/arch/sh/configs/se7343_defconfig b/arch/sh/configs/se7343_defconfig
index fbb72d029e68..004d531716dc 100644
--- a/arch/sh/configs/se7343_defconfig
+++ b/arch/sh/configs/se7343_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:42:00 2009 4# Mon Apr 27 13:01:44 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -40,6 +41,7 @@ CONFIG_LOCALVERSION_AUTO=y
40CONFIG_SYSVIPC=y 41CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y 42CONFIG_SYSVIPC_SYSCTL=y
42CONFIG_POSIX_MQUEUE=y 43CONFIG_POSIX_MQUEUE=y
44CONFIG_POSIX_MQUEUE_SYSCTL=y
43# CONFIG_BSD_PROCESS_ACCT is not set 45# CONFIG_BSD_PROCESS_ACCT is not set
44# CONFIG_TASKSTATS is not set 46# CONFIG_TASKSTATS is not set
45# CONFIG_AUDIT is not set 47# CONFIG_AUDIT is not set
@@ -73,6 +75,7 @@ CONFIG_UID16=y
73# CONFIG_SYSCTL_SYSCALL is not set 75# CONFIG_SYSCTL_SYSCALL is not set
74CONFIG_KALLSYMS=y 76CONFIG_KALLSYMS=y
75# CONFIG_KALLSYMS_EXTRA_PASS is not set 77# CONFIG_KALLSYMS_EXTRA_PASS is not set
78# CONFIG_STRIP_ASM_SYMS is not set
76CONFIG_HOTPLUG=y 79CONFIG_HOTPLUG=y
77CONFIG_PRINTK=y 80CONFIG_PRINTK=y
78CONFIG_BUG=y 81CONFIG_BUG=y
@@ -91,6 +94,7 @@ CONFIG_SLAB=y
91# CONFIG_SLUB is not set 94# CONFIG_SLUB is not set
92# CONFIG_SLOB is not set 95# CONFIG_SLOB is not set
93# CONFIG_PROFILING is not set 96# CONFIG_PROFILING is not set
97# CONFIG_MARKERS is not set
94CONFIG_HAVE_OPROFILE=y 98CONFIG_HAVE_OPROFILE=y
95# CONFIG_KPROBES is not set 99# CONFIG_KPROBES is not set
96CONFIG_HAVE_IOREMAP_PROT=y 100CONFIG_HAVE_IOREMAP_PROT=y
@@ -98,6 +102,8 @@ CONFIG_HAVE_KPROBES=y
98CONFIG_HAVE_KRETPROBES=y 102CONFIG_HAVE_KRETPROBES=y
99CONFIG_HAVE_ARCH_TRACEHOOK=y 103CONFIG_HAVE_ARCH_TRACEHOOK=y
100CONFIG_HAVE_CLK=y 104CONFIG_HAVE_CLK=y
105CONFIG_HAVE_DMA_API_DEBUG=y
106# CONFIG_SLOW_WORK is not set
101CONFIG_HAVE_GENERIC_DMA_COHERENT=y 107CONFIG_HAVE_GENERIC_DMA_COHERENT=y
102CONFIG_SLABINFO=y 108CONFIG_SLABINFO=y
103CONFIG_BASE_SMALL=0 109CONFIG_BASE_SMALL=0
@@ -109,7 +115,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y
109# CONFIG_MODULE_SRCVERSION_ALL is not set 115# CONFIG_MODULE_SRCVERSION_ALL is not set
110CONFIG_BLOCK=y 116CONFIG_BLOCK=y
111# CONFIG_LBD is not set 117# CONFIG_LBD is not set
112# CONFIG_BLK_DEV_IO_TRACE is not set
113# CONFIG_BLK_DEV_BSG is not set 118# CONFIG_BLK_DEV_BSG is not set
114# CONFIG_BLK_DEV_INTEGRITY is not set 119# CONFIG_BLK_DEV_INTEGRITY is not set
115 120
@@ -158,6 +163,7 @@ CONFIG_ARCH_SHMOBILE=y
158# CONFIG_CPU_SUBTYPE_SH7760 is not set 163# CONFIG_CPU_SUBTYPE_SH7760 is not set
159# CONFIG_CPU_SUBTYPE_SH4_202 is not set 164# CONFIG_CPU_SUBTYPE_SH4_202 is not set
160# CONFIG_CPU_SUBTYPE_SH7723 is not set 165# CONFIG_CPU_SUBTYPE_SH7723 is not set
166# CONFIG_CPU_SUBTYPE_SH7724 is not set
161# CONFIG_CPU_SUBTYPE_SH7763 is not set 167# CONFIG_CPU_SUBTYPE_SH7763 is not set
162# CONFIG_CPU_SUBTYPE_SH7770 is not set 168# CONFIG_CPU_SUBTYPE_SH7770 is not set
163# CONFIG_CPU_SUBTYPE_SH7780 is not set 169# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -167,8 +173,6 @@ CONFIG_ARCH_SHMOBILE=y
167CONFIG_CPU_SUBTYPE_SH7343=y 173CONFIG_CPU_SUBTYPE_SH7343=y
168# CONFIG_CPU_SUBTYPE_SH7722 is not set 174# CONFIG_CPU_SUBTYPE_SH7722 is not set
169# CONFIG_CPU_SUBTYPE_SH7366 is not set 175# CONFIG_CPU_SUBTYPE_SH7366 is not set
170# CONFIG_CPU_SUBTYPE_SH5_101 is not set
171# CONFIG_CPU_SUBTYPE_SH5_103 is not set
172 176
173# 177#
174# Memory management options 178# Memory management options
@@ -769,6 +773,7 @@ CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
769# CONFIG_SOC_CAMERA is not set 773# CONFIG_SOC_CAMERA is not set
770CONFIG_V4L_USB_DRIVERS=y 774CONFIG_V4L_USB_DRIVERS=y
771# CONFIG_USB_VIDEO_CLASS is not set 775# CONFIG_USB_VIDEO_CLASS is not set
776CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
772CONFIG_USB_GSPCA=m 777CONFIG_USB_GSPCA=m
773# CONFIG_USB_M5602 is not set 778# CONFIG_USB_M5602 is not set
774# CONFIG_USB_STV06XX is not set 779# CONFIG_USB_STV06XX is not set
@@ -800,6 +805,7 @@ CONFIG_USB_GSPCA=m
800# CONFIG_VIDEO_PVRUSB2 is not set 805# CONFIG_VIDEO_PVRUSB2 is not set
801# CONFIG_VIDEO_HDPVR is not set 806# CONFIG_VIDEO_HDPVR is not set
802# CONFIG_VIDEO_EM28XX is not set 807# CONFIG_VIDEO_EM28XX is not set
808# CONFIG_VIDEO_CX231XX is not set
803# CONFIG_VIDEO_USBVISION is not set 809# CONFIG_VIDEO_USBVISION is not set
804# CONFIG_USB_VICAM is not set 810# CONFIG_USB_VICAM is not set
805# CONFIG_USB_IBMCAM is not set 811# CONFIG_USB_IBMCAM is not set
@@ -813,6 +819,7 @@ CONFIG_USB_GSPCA=m
813# CONFIG_USB_STV680 is not set 819# CONFIG_USB_STV680 is not set
814# CONFIG_USB_ZC0301 is not set 820# CONFIG_USB_ZC0301 is not set
815# CONFIG_USB_PWC is not set 821# CONFIG_USB_PWC is not set
822CONFIG_USB_PWC_INPUT_EVDEV=y
816# CONFIG_USB_ZR364XX is not set 823# CONFIG_USB_ZR364XX is not set
817# CONFIG_USB_STKWEBCAM is not set 824# CONFIG_USB_STKWEBCAM is not set
818# CONFIG_USB_S2255 is not set 825# CONFIG_USB_S2255 is not set
@@ -914,15 +921,17 @@ CONFIG_USB_HID=y
914# 921#
915# Special HID drivers 922# Special HID drivers
916# 923#
917CONFIG_HID_COMPAT=y
918CONFIG_HID_A4TECH=y 924CONFIG_HID_A4TECH=y
919CONFIG_HID_APPLE=y 925CONFIG_HID_APPLE=y
920CONFIG_HID_BELKIN=y 926CONFIG_HID_BELKIN=y
921CONFIG_HID_CHERRY=y 927CONFIG_HID_CHERRY=y
922CONFIG_HID_CHICONY=y 928CONFIG_HID_CHICONY=y
923CONFIG_HID_CYPRESS=y 929CONFIG_HID_CYPRESS=y
930# CONFIG_DRAGONRISE_FF is not set
924CONFIG_HID_EZKEY=y 931CONFIG_HID_EZKEY=y
932# CONFIG_HID_KYE is not set
925CONFIG_HID_GYRATION=y 933CONFIG_HID_GYRATION=y
934# CONFIG_HID_KENSINGTON is not set
926CONFIG_HID_LOGITECH=y 935CONFIG_HID_LOGITECH=y
927# CONFIG_LOGITECH_FF is not set 936# CONFIG_LOGITECH_FF is not set
928# CONFIG_LOGIRUMBLEPAD2_FF is not set 937# CONFIG_LOGIRUMBLEPAD2_FF is not set
@@ -1050,6 +1059,7 @@ CONFIG_EXT2_FS=y
1050# CONFIG_EXT2_FS_XATTR is not set 1059# CONFIG_EXT2_FS_XATTR is not set
1051# CONFIG_EXT2_FS_XIP is not set 1060# CONFIG_EXT2_FS_XIP is not set
1052CONFIG_EXT3_FS=y 1061CONFIG_EXT3_FS=y
1062# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1053CONFIG_EXT3_FS_XATTR=y 1063CONFIG_EXT3_FS_XATTR=y
1054# CONFIG_EXT3_FS_POSIX_ACL is not set 1064# CONFIG_EXT3_FS_POSIX_ACL is not set
1055# CONFIG_EXT3_FS_SECURITY is not set 1065# CONFIG_EXT3_FS_SECURITY is not set
@@ -1071,6 +1081,11 @@ CONFIG_FILE_LOCKING=y
1071# CONFIG_FUSE_FS is not set 1081# CONFIG_FUSE_FS is not set
1072 1082
1073# 1083#
1084# Caches
1085#
1086# CONFIG_FSCACHE is not set
1087
1088#
1074# CD-ROM/DVD Filesystems 1089# CD-ROM/DVD Filesystems
1075# 1090#
1076# CONFIG_ISO9660_FS is not set 1091# CONFIG_ISO9660_FS is not set
@@ -1125,6 +1140,7 @@ CONFIG_CRAMFS=y
1125# CONFIG_ROMFS_FS is not set 1140# CONFIG_ROMFS_FS is not set
1126# CONFIG_SYSV_FS is not set 1141# CONFIG_SYSV_FS is not set
1127# CONFIG_UFS_FS is not set 1142# CONFIG_UFS_FS is not set
1143# CONFIG_NILFS2_FS is not set
1128CONFIG_NETWORK_FILESYSTEMS=y 1144CONFIG_NETWORK_FILESYSTEMS=y
1129CONFIG_NFS_FS=y 1145CONFIG_NFS_FS=y
1130CONFIG_NFS_V3=y 1146CONFIG_NFS_V3=y
@@ -1174,10 +1190,23 @@ CONFIG_FRAME_WARN=1024
1174CONFIG_HAVE_FUNCTION_TRACER=y 1190CONFIG_HAVE_FUNCTION_TRACER=y
1175CONFIG_HAVE_DYNAMIC_FTRACE=y 1191CONFIG_HAVE_DYNAMIC_FTRACE=y
1176CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1192CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1193CONFIG_TRACING_SUPPORT=y
1177 1194
1178# 1195#
1179# Tracers 1196# Tracers
1180# 1197#
1198# CONFIG_FUNCTION_TRACER is not set
1199# CONFIG_IRQSOFF_TRACER is not set
1200# CONFIG_SCHED_TRACER is not set
1201# CONFIG_CONTEXT_SWITCH_TRACER is not set
1202# CONFIG_EVENT_TRACER is not set
1203# CONFIG_BOOT_TRACER is not set
1204# CONFIG_TRACE_BRANCH_PROFILING is not set
1205# CONFIG_STACK_TRACER is not set
1206# CONFIG_KMEMTRACE is not set
1207# CONFIG_WORKQUEUE_TRACER is not set
1208# CONFIG_BLK_DEV_IO_TRACE is not set
1209# CONFIG_DMA_API_DEBUG is not set
1181# CONFIG_SAMPLES is not set 1210# CONFIG_SAMPLES is not set
1182CONFIG_HAVE_ARCH_KGDB=y 1211CONFIG_HAVE_ARCH_KGDB=y
1183# CONFIG_SH_STANDARD_BIOS is not set 1212# CONFIG_SH_STANDARD_BIOS is not set
@@ -1279,6 +1308,7 @@ CONFIG_CRYPTO=y
1279# 1308#
1280# CONFIG_CRYPTO_ANSI_CPRNG is not set 1309# CONFIG_CRYPTO_ANSI_CPRNG is not set
1281CONFIG_CRYPTO_HW=y 1310CONFIG_CRYPTO_HW=y
1311# CONFIG_BINARY_PRINTF is not set
1282 1312
1283# 1313#
1284# Library routines 1314# Library routines
diff --git a/arch/sh/configs/se7619_defconfig b/arch/sh/configs/se7619_defconfig
index 125304e80f57..edbece52afc1 100644
--- a/arch/sh/configs/se7619_defconfig
+++ b/arch/sh/configs/se7619_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:44:53 2009 4# Mon Apr 27 13:02:32 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -61,6 +62,7 @@ CONFIG_EMBEDDED=y
61# CONFIG_UID16 is not set 62# CONFIG_UID16 is not set
62# CONFIG_SYSCTL_SYSCALL is not set 63# CONFIG_SYSCTL_SYSCALL is not set
63# CONFIG_KALLSYMS is not set 64# CONFIG_KALLSYMS is not set
65# CONFIG_STRIP_ASM_SYMS is not set
64# CONFIG_HOTPLUG is not set 66# CONFIG_HOTPLUG is not set
65CONFIG_PRINTK=y 67CONFIG_PRINTK=y
66CONFIG_BUG=y 68CONFIG_BUG=y
@@ -78,11 +80,14 @@ CONFIG_SLAB=y
78# CONFIG_SLUB is not set 80# CONFIG_SLUB is not set
79# CONFIG_SLOB is not set 81# CONFIG_SLOB is not set
80# CONFIG_PROFILING is not set 82# CONFIG_PROFILING is not set
83# CONFIG_MARKERS is not set
81CONFIG_HAVE_OPROFILE=y 84CONFIG_HAVE_OPROFILE=y
82CONFIG_HAVE_KPROBES=y 85CONFIG_HAVE_KPROBES=y
83CONFIG_HAVE_KRETPROBES=y 86CONFIG_HAVE_KRETPROBES=y
84CONFIG_HAVE_ARCH_TRACEHOOK=y 87CONFIG_HAVE_ARCH_TRACEHOOK=y
85CONFIG_HAVE_CLK=y 88CONFIG_HAVE_CLK=y
89CONFIG_HAVE_DMA_API_DEBUG=y
90# CONFIG_SLOW_WORK is not set
86CONFIG_HAVE_GENERIC_DMA_COHERENT=y 91CONFIG_HAVE_GENERIC_DMA_COHERENT=y
87CONFIG_SLABINFO=y 92CONFIG_SLABINFO=y
88CONFIG_BASE_SMALL=1 93CONFIG_BASE_SMALL=1
@@ -134,6 +139,7 @@ CONFIG_CPU_SUBTYPE_SH7619=y
134# CONFIG_CPU_SUBTYPE_SH7760 is not set 139# CONFIG_CPU_SUBTYPE_SH7760 is not set
135# CONFIG_CPU_SUBTYPE_SH4_202 is not set 140# CONFIG_CPU_SUBTYPE_SH4_202 is not set
136# CONFIG_CPU_SUBTYPE_SH7723 is not set 141# CONFIG_CPU_SUBTYPE_SH7723 is not set
142# CONFIG_CPU_SUBTYPE_SH7724 is not set
137# CONFIG_CPU_SUBTYPE_SH7763 is not set 143# CONFIG_CPU_SUBTYPE_SH7763 is not set
138# CONFIG_CPU_SUBTYPE_SH7770 is not set 144# CONFIG_CPU_SUBTYPE_SH7770 is not set
139# CONFIG_CPU_SUBTYPE_SH7780 is not set 145# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -143,8 +149,6 @@ CONFIG_CPU_SUBTYPE_SH7619=y
143# CONFIG_CPU_SUBTYPE_SH7343 is not set 149# CONFIG_CPU_SUBTYPE_SH7343 is not set
144# CONFIG_CPU_SUBTYPE_SH7722 is not set 150# CONFIG_CPU_SUBTYPE_SH7722 is not set
145# CONFIG_CPU_SUBTYPE_SH7366 is not set 151# CONFIG_CPU_SUBTYPE_SH7366 is not set
146# CONFIG_CPU_SUBTYPE_SH5_101 is not set
147# CONFIG_CPU_SUBTYPE_SH5_103 is not set
148 152
149# 153#
150# Memory management options 154# Memory management options
@@ -513,7 +517,6 @@ CONFIG_HID=y
513# 517#
514# Special HID drivers 518# Special HID drivers
515# 519#
516CONFIG_HID_COMPAT=y
517CONFIG_USB_SUPPORT=y 520CONFIG_USB_SUPPORT=y
518CONFIG_USB_ARCH_HAS_HCD=y 521CONFIG_USB_ARCH_HAS_HCD=y
519# CONFIG_USB_ARCH_HAS_OHCI is not set 522# CONFIG_USB_ARCH_HAS_OHCI is not set
@@ -564,6 +567,11 @@ CONFIG_FILE_LOCKING=y
564# CONFIG_FUSE_FS is not set 567# CONFIG_FUSE_FS is not set
565 568
566# 569#
570# Caches
571#
572# CONFIG_FSCACHE is not set
573
574#
567# CD-ROM/DVD Filesystems 575# CD-ROM/DVD Filesystems
568# 576#
569# CONFIG_ISO9660_FS is not set 577# CONFIG_ISO9660_FS is not set
@@ -601,8 +609,13 @@ CONFIG_MISC_FILESYSTEMS=y
601# CONFIG_HPFS_FS is not set 609# CONFIG_HPFS_FS is not set
602# CONFIG_QNX4FS_FS is not set 610# CONFIG_QNX4FS_FS is not set
603CONFIG_ROMFS_FS=y 611CONFIG_ROMFS_FS=y
612CONFIG_ROMFS_BACKED_BY_BLOCK=y
613# CONFIG_ROMFS_BACKED_BY_MTD is not set
614# CONFIG_ROMFS_BACKED_BY_BOTH is not set
615CONFIG_ROMFS_ON_BLOCK=y
604# CONFIG_SYSV_FS is not set 616# CONFIG_SYSV_FS is not set
605# CONFIG_UFS_FS is not set 617# CONFIG_UFS_FS is not set
618# CONFIG_NILFS2_FS is not set
606 619
607# 620#
608# Partition Types 621# Partition Types
@@ -630,10 +643,21 @@ CONFIG_FRAME_WARN=1024
630CONFIG_HAVE_FUNCTION_TRACER=y 643CONFIG_HAVE_FUNCTION_TRACER=y
631CONFIG_HAVE_DYNAMIC_FTRACE=y 644CONFIG_HAVE_DYNAMIC_FTRACE=y
632CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 645CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
646CONFIG_TRACING_SUPPORT=y
633 647
634# 648#
635# Tracers 649# Tracers
636# 650#
651# CONFIG_FUNCTION_TRACER is not set
652# CONFIG_SCHED_TRACER is not set
653# CONFIG_CONTEXT_SWITCH_TRACER is not set
654# CONFIG_EVENT_TRACER is not set
655# CONFIG_BOOT_TRACER is not set
656# CONFIG_TRACE_BRANCH_PROFILING is not set
657# CONFIG_STACK_TRACER is not set
658# CONFIG_KMEMTRACE is not set
659# CONFIG_WORKQUEUE_TRACER is not set
660# CONFIG_DMA_API_DEBUG is not set
637# CONFIG_SAMPLES is not set 661# CONFIG_SAMPLES is not set
638CONFIG_HAVE_ARCH_KGDB=y 662CONFIG_HAVE_ARCH_KGDB=y
639# CONFIG_SH_STANDARD_BIOS is not set 663# CONFIG_SH_STANDARD_BIOS is not set
@@ -647,6 +671,7 @@ CONFIG_HAVE_ARCH_KGDB=y
647# CONFIG_SECURITYFS is not set 671# CONFIG_SECURITYFS is not set
648# CONFIG_SECURITY_FILE_CAPABILITIES is not set 672# CONFIG_SECURITY_FILE_CAPABILITIES is not set
649# CONFIG_CRYPTO is not set 673# CONFIG_CRYPTO is not set
674# CONFIG_BINARY_PRINTF is not set
650 675
651# 676#
652# Library routines 677# Library routines
diff --git a/arch/sh/configs/se7705_defconfig b/arch/sh/configs/se7705_defconfig
index 0308abf52384..bae161c66835 100644
--- a/arch/sh/configs/se7705_defconfig
+++ b/arch/sh/configs/se7705_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:45:56 2009 4# Mon Apr 27 13:02:52 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -62,7 +63,6 @@ CONFIG_INITRAMFS_SOURCE=""
62CONFIG_RD_GZIP=y 63CONFIG_RD_GZIP=y
63# CONFIG_RD_BZIP2 is not set 64# CONFIG_RD_BZIP2 is not set
64# CONFIG_RD_LZMA is not set 65# CONFIG_RD_LZMA is not set
65CONFIG_INITRAMFS_COMPRESSION_NONE=y
66# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 66# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
67CONFIG_SYSCTL=y 67CONFIG_SYSCTL=y
68CONFIG_ANON_INODES=y 68CONFIG_ANON_INODES=y
@@ -70,6 +70,7 @@ CONFIG_EMBEDDED=y
70CONFIG_UID16=y 70CONFIG_UID16=y
71# CONFIG_SYSCTL_SYSCALL is not set 71# CONFIG_SYSCTL_SYSCALL is not set
72# CONFIG_KALLSYMS is not set 72# CONFIG_KALLSYMS is not set
73# CONFIG_STRIP_ASM_SYMS is not set
73# CONFIG_HOTPLUG is not set 74# CONFIG_HOTPLUG is not set
74CONFIG_PRINTK=y 75CONFIG_PRINTK=y
75CONFIG_BUG=y 76CONFIG_BUG=y
@@ -88,12 +89,15 @@ CONFIG_SLAB=y
88# CONFIG_SLUB is not set 89# CONFIG_SLUB is not set
89# CONFIG_SLOB is not set 90# CONFIG_SLOB is not set
90# CONFIG_PROFILING is not set 91# CONFIG_PROFILING is not set
92# CONFIG_MARKERS is not set
91CONFIG_HAVE_OPROFILE=y 93CONFIG_HAVE_OPROFILE=y
92CONFIG_HAVE_IOREMAP_PROT=y 94CONFIG_HAVE_IOREMAP_PROT=y
93CONFIG_HAVE_KPROBES=y 95CONFIG_HAVE_KPROBES=y
94CONFIG_HAVE_KRETPROBES=y 96CONFIG_HAVE_KRETPROBES=y
95CONFIG_HAVE_ARCH_TRACEHOOK=y 97CONFIG_HAVE_ARCH_TRACEHOOK=y
96CONFIG_HAVE_CLK=y 98CONFIG_HAVE_CLK=y
99CONFIG_HAVE_DMA_API_DEBUG=y
100# CONFIG_SLOW_WORK is not set
97CONFIG_HAVE_GENERIC_DMA_COHERENT=y 101CONFIG_HAVE_GENERIC_DMA_COHERENT=y
98CONFIG_SLABINFO=y 102CONFIG_SLABINFO=y
99CONFIG_RT_MUTEXES=y 103CONFIG_RT_MUTEXES=y
@@ -150,6 +154,7 @@ CONFIG_CPU_SUBTYPE_SH7705=y
150# CONFIG_CPU_SUBTYPE_SH7760 is not set 154# CONFIG_CPU_SUBTYPE_SH7760 is not set
151# CONFIG_CPU_SUBTYPE_SH4_202 is not set 155# CONFIG_CPU_SUBTYPE_SH4_202 is not set
152# CONFIG_CPU_SUBTYPE_SH7723 is not set 156# CONFIG_CPU_SUBTYPE_SH7723 is not set
157# CONFIG_CPU_SUBTYPE_SH7724 is not set
153# CONFIG_CPU_SUBTYPE_SH7763 is not set 158# CONFIG_CPU_SUBTYPE_SH7763 is not set
154# CONFIG_CPU_SUBTYPE_SH7770 is not set 159# CONFIG_CPU_SUBTYPE_SH7770 is not set
155# CONFIG_CPU_SUBTYPE_SH7780 is not set 160# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -159,8 +164,6 @@ CONFIG_CPU_SUBTYPE_SH7705=y
159# CONFIG_CPU_SUBTYPE_SH7343 is not set 164# CONFIG_CPU_SUBTYPE_SH7343 is not set
160# CONFIG_CPU_SUBTYPE_SH7722 is not set 165# CONFIG_CPU_SUBTYPE_SH7722 is not set
161# CONFIG_CPU_SUBTYPE_SH7366 is not set 166# CONFIG_CPU_SUBTYPE_SH7366 is not set
162# CONFIG_CPU_SUBTYPE_SH5_101 is not set
163# CONFIG_CPU_SUBTYPE_SH5_103 is not set
164 167
165# 168#
166# Memory management options 169# Memory management options
@@ -698,7 +701,6 @@ CONFIG_HID=y
698# 701#
699# Special HID drivers 702# Special HID drivers
700# 703#
701CONFIG_HID_COMPAT=y
702CONFIG_USB_SUPPORT=y 704CONFIG_USB_SUPPORT=y
703CONFIG_USB_ARCH_HAS_HCD=y 705CONFIG_USB_ARCH_HAS_HCD=y
704# CONFIG_USB_ARCH_HAS_OHCI is not set 706# CONFIG_USB_ARCH_HAS_OHCI is not set
@@ -752,6 +754,11 @@ CONFIG_INOTIFY_USER=y
752# CONFIG_FUSE_FS is not set 754# CONFIG_FUSE_FS is not set
753 755
754# 756#
757# Caches
758#
759# CONFIG_FSCACHE is not set
760
761#
755# CD-ROM/DVD Filesystems 762# CD-ROM/DVD Filesystems
756# 763#
757# CONFIG_ISO9660_FS is not set 764# CONFIG_ISO9660_FS is not set
@@ -804,6 +811,7 @@ CONFIG_JFFS2_RTIME=y
804# CONFIG_ROMFS_FS is not set 811# CONFIG_ROMFS_FS is not set
805# CONFIG_SYSV_FS is not set 812# CONFIG_SYSV_FS is not set
806# CONFIG_UFS_FS is not set 813# CONFIG_UFS_FS is not set
814# CONFIG_NILFS2_FS is not set
807CONFIG_NETWORK_FILESYSTEMS=y 815CONFIG_NETWORK_FILESYSTEMS=y
808CONFIG_NFS_FS=y 816CONFIG_NFS_FS=y
809# CONFIG_NFS_V3 is not set 817# CONFIG_NFS_V3 is not set
@@ -847,10 +855,23 @@ CONFIG_FRAME_WARN=1024
847CONFIG_HAVE_FUNCTION_TRACER=y 855CONFIG_HAVE_FUNCTION_TRACER=y
848CONFIG_HAVE_DYNAMIC_FTRACE=y 856CONFIG_HAVE_DYNAMIC_FTRACE=y
849CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 857CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
858CONFIG_TRACING_SUPPORT=y
850 859
851# 860#
852# Tracers 861# Tracers
853# 862#
863# CONFIG_FUNCTION_TRACER is not set
864# CONFIG_IRQSOFF_TRACER is not set
865# CONFIG_PREEMPT_TRACER is not set
866# CONFIG_SCHED_TRACER is not set
867# CONFIG_CONTEXT_SWITCH_TRACER is not set
868# CONFIG_EVENT_TRACER is not set
869# CONFIG_BOOT_TRACER is not set
870# CONFIG_TRACE_BRANCH_PROFILING is not set
871# CONFIG_STACK_TRACER is not set
872# CONFIG_KMEMTRACE is not set
873# CONFIG_WORKQUEUE_TRACER is not set
874# CONFIG_DMA_API_DEBUG is not set
854# CONFIG_SAMPLES is not set 875# CONFIG_SAMPLES is not set
855CONFIG_HAVE_ARCH_KGDB=y 876CONFIG_HAVE_ARCH_KGDB=y
856# CONFIG_SH_STANDARD_BIOS is not set 877# CONFIG_SH_STANDARD_BIOS is not set
@@ -949,6 +970,7 @@ CONFIG_CRYPTO=y
949# 970#
950# CONFIG_CRYPTO_ANSI_CPRNG is not set 971# CONFIG_CRYPTO_ANSI_CPRNG is not set
951CONFIG_CRYPTO_HW=y 972CONFIG_CRYPTO_HW=y
973# CONFIG_BINARY_PRINTF is not set
952 974
953# 975#
954# Library routines 976# Library routines
diff --git a/arch/sh/configs/se7712_defconfig b/arch/sh/configs/se7712_defconfig
index a8c24b703489..330043f3c316 100644
--- a/arch/sh/configs/se7712_defconfig
+++ b/arch/sh/configs/se7712_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:48:18 2009 4# Mon Apr 27 13:03:27 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_FIND_NEXT_BIT=y 11CONFIG_GENERIC_FIND_NEXT_BIT=y
@@ -38,6 +39,7 @@ CONFIG_LOCALVERSION=""
38CONFIG_SYSVIPC=y 39CONFIG_SYSVIPC=y
39CONFIG_SYSVIPC_SYSCTL=y 40CONFIG_SYSVIPC_SYSCTL=y
40CONFIG_POSIX_MQUEUE=y 41CONFIG_POSIX_MQUEUE=y
42CONFIG_POSIX_MQUEUE_SYSCTL=y
41CONFIG_BSD_PROCESS_ACCT=y 43CONFIG_BSD_PROCESS_ACCT=y
42# CONFIG_BSD_PROCESS_ACCT_V3 is not set 44# CONFIG_BSD_PROCESS_ACCT_V3 is not set
43# CONFIG_TASKSTATS is not set 45# CONFIG_TASKSTATS is not set
@@ -69,6 +71,7 @@ CONFIG_SYSCTL_SYSCALL=y
69CONFIG_KALLSYMS=y 71CONFIG_KALLSYMS=y
70CONFIG_KALLSYMS_ALL=y 72CONFIG_KALLSYMS_ALL=y
71# CONFIG_KALLSYMS_EXTRA_PASS is not set 73# CONFIG_KALLSYMS_EXTRA_PASS is not set
74# CONFIG_STRIP_ASM_SYMS is not set
72CONFIG_HOTPLUG=y 75CONFIG_HOTPLUG=y
73CONFIG_PRINTK=y 76CONFIG_PRINTK=y
74# CONFIG_BUG is not set 77# CONFIG_BUG is not set
@@ -87,6 +90,7 @@ CONFIG_SLAB=y
87# CONFIG_SLUB is not set 90# CONFIG_SLUB is not set
88# CONFIG_SLOB is not set 91# CONFIG_SLOB is not set
89# CONFIG_PROFILING is not set 92# CONFIG_PROFILING is not set
93# CONFIG_MARKERS is not set
90CONFIG_HAVE_OPROFILE=y 94CONFIG_HAVE_OPROFILE=y
91# CONFIG_KPROBES is not set 95# CONFIG_KPROBES is not set
92CONFIG_HAVE_IOREMAP_PROT=y 96CONFIG_HAVE_IOREMAP_PROT=y
@@ -94,6 +98,8 @@ CONFIG_HAVE_KPROBES=y
94CONFIG_HAVE_KRETPROBES=y 98CONFIG_HAVE_KRETPROBES=y
95CONFIG_HAVE_ARCH_TRACEHOOK=y 99CONFIG_HAVE_ARCH_TRACEHOOK=y
96CONFIG_HAVE_CLK=y 100CONFIG_HAVE_CLK=y
101CONFIG_HAVE_DMA_API_DEBUG=y
102# CONFIG_SLOW_WORK is not set
97CONFIG_HAVE_GENERIC_DMA_COHERENT=y 103CONFIG_HAVE_GENERIC_DMA_COHERENT=y
98CONFIG_SLABINFO=y 104CONFIG_SLABINFO=y
99CONFIG_RT_MUTEXES=y 105CONFIG_RT_MUTEXES=y
@@ -105,7 +111,6 @@ CONFIG_MODULES=y
105# CONFIG_MODULE_SRCVERSION_ALL is not set 111# CONFIG_MODULE_SRCVERSION_ALL is not set
106CONFIG_BLOCK=y 112CONFIG_BLOCK=y
107# CONFIG_LBD is not set 113# CONFIG_LBD is not set
108# CONFIG_BLK_DEV_IO_TRACE is not set
109# CONFIG_BLK_DEV_BSG is not set 114# CONFIG_BLK_DEV_BSG is not set
110# CONFIG_BLK_DEV_INTEGRITY is not set 115# CONFIG_BLK_DEV_INTEGRITY is not set
111 116
@@ -151,6 +156,7 @@ CONFIG_CPU_SUBTYPE_SH7712=y
151# CONFIG_CPU_SUBTYPE_SH7760 is not set 156# CONFIG_CPU_SUBTYPE_SH7760 is not set
152# CONFIG_CPU_SUBTYPE_SH4_202 is not set 157# CONFIG_CPU_SUBTYPE_SH4_202 is not set
153# CONFIG_CPU_SUBTYPE_SH7723 is not set 158# CONFIG_CPU_SUBTYPE_SH7723 is not set
159# CONFIG_CPU_SUBTYPE_SH7724 is not set
154# CONFIG_CPU_SUBTYPE_SH7763 is not set 160# CONFIG_CPU_SUBTYPE_SH7763 is not set
155# CONFIG_CPU_SUBTYPE_SH7770 is not set 161# CONFIG_CPU_SUBTYPE_SH7770 is not set
156# CONFIG_CPU_SUBTYPE_SH7780 is not set 162# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -160,8 +166,6 @@ CONFIG_CPU_SUBTYPE_SH7712=y
160# CONFIG_CPU_SUBTYPE_SH7343 is not set 166# CONFIG_CPU_SUBTYPE_SH7343 is not set
161# CONFIG_CPU_SUBTYPE_SH7722 is not set 167# CONFIG_CPU_SUBTYPE_SH7722 is not set
162# CONFIG_CPU_SUBTYPE_SH7366 is not set 168# CONFIG_CPU_SUBTYPE_SH7366 is not set
163# CONFIG_CPU_SUBTYPE_SH5_101 is not set
164# CONFIG_CPU_SUBTYPE_SH5_103 is not set
165 169
166# 170#
167# Memory management options 171# Memory management options
@@ -585,6 +589,7 @@ CONFIG_SCSI_WAIT_SCAN=m
585CONFIG_SCSI_LOWLEVEL=y 589CONFIG_SCSI_LOWLEVEL=y
586# CONFIG_ISCSI_TCP is not set 590# CONFIG_ISCSI_TCP is not set
587# CONFIG_LIBFC is not set 591# CONFIG_LIBFC is not set
592# CONFIG_LIBFCOE is not set
588# CONFIG_SCSI_DEBUG is not set 593# CONFIG_SCSI_DEBUG is not set
589# CONFIG_SCSI_DH is not set 594# CONFIG_SCSI_DH is not set
590# CONFIG_SCSI_OSD_INITIATOR is not set 595# CONFIG_SCSI_OSD_INITIATOR is not set
@@ -812,6 +817,7 @@ CONFIG_EXT2_FS_POSIX_ACL=y
812CONFIG_EXT2_FS_SECURITY=y 817CONFIG_EXT2_FS_SECURITY=y
813# CONFIG_EXT2_FS_XIP is not set 818# CONFIG_EXT2_FS_XIP is not set
814CONFIG_EXT3_FS=y 819CONFIG_EXT3_FS=y
820# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
815CONFIG_EXT3_FS_XATTR=y 821CONFIG_EXT3_FS_XATTR=y
816# CONFIG_EXT3_FS_POSIX_ACL is not set 822# CONFIG_EXT3_FS_POSIX_ACL is not set
817# CONFIG_EXT3_FS_SECURITY is not set 823# CONFIG_EXT3_FS_SECURITY is not set
@@ -833,6 +839,11 @@ CONFIG_FILE_LOCKING=y
833# CONFIG_FUSE_FS is not set 839# CONFIG_FUSE_FS is not set
834 840
835# 841#
842# Caches
843#
844# CONFIG_FSCACHE is not set
845
846#
836# CD-ROM/DVD Filesystems 847# CD-ROM/DVD Filesystems
837# 848#
838# CONFIG_ISO9660_FS is not set 849# CONFIG_ISO9660_FS is not set
@@ -887,6 +898,7 @@ CONFIG_CRAMFS=y
887# CONFIG_ROMFS_FS is not set 898# CONFIG_ROMFS_FS is not set
888# CONFIG_SYSV_FS is not set 899# CONFIG_SYSV_FS is not set
889# CONFIG_UFS_FS is not set 900# CONFIG_UFS_FS is not set
901# CONFIG_NILFS2_FS is not set
890CONFIG_NETWORK_FILESYSTEMS=y 902CONFIG_NETWORK_FILESYSTEMS=y
891CONFIG_NFS_FS=y 903CONFIG_NFS_FS=y
892# CONFIG_NFS_V3 is not set 904# CONFIG_NFS_V3 is not set
@@ -927,6 +939,7 @@ CONFIG_FRAME_WARN=1024
927CONFIG_DEBUG_KERNEL=y 939CONFIG_DEBUG_KERNEL=y
928# CONFIG_DEBUG_SHIRQ is not set 940# CONFIG_DEBUG_SHIRQ is not set
929# CONFIG_DETECT_SOFTLOCKUP is not set 941# CONFIG_DETECT_SOFTLOCKUP is not set
942# CONFIG_DETECT_HUNG_TASK is not set
930CONFIG_SCHED_DEBUG=y 943CONFIG_SCHED_DEBUG=y
931# CONFIG_SCHEDSTATS is not set 944# CONFIG_SCHEDSTATS is not set
932# CONFIG_TIMER_STATS is not set 945# CONFIG_TIMER_STATS is not set
@@ -961,6 +974,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
961CONFIG_HAVE_FUNCTION_TRACER=y 974CONFIG_HAVE_FUNCTION_TRACER=y
962CONFIG_HAVE_DYNAMIC_FTRACE=y 975CONFIG_HAVE_DYNAMIC_FTRACE=y
963CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 976CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
977CONFIG_TRACING_SUPPORT=y
964 978
965# 979#
966# Tracers 980# Tracers
@@ -969,9 +983,14 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
969# CONFIG_IRQSOFF_TRACER is not set 983# CONFIG_IRQSOFF_TRACER is not set
970# CONFIG_SCHED_TRACER is not set 984# CONFIG_SCHED_TRACER is not set
971# CONFIG_CONTEXT_SWITCH_TRACER is not set 985# CONFIG_CONTEXT_SWITCH_TRACER is not set
986# CONFIG_EVENT_TRACER is not set
972# CONFIG_BOOT_TRACER is not set 987# CONFIG_BOOT_TRACER is not set
973# CONFIG_TRACE_BRANCH_PROFILING is not set 988# CONFIG_TRACE_BRANCH_PROFILING is not set
974# CONFIG_STACK_TRACER is not set 989# CONFIG_STACK_TRACER is not set
990# CONFIG_KMEMTRACE is not set
991# CONFIG_WORKQUEUE_TRACER is not set
992# CONFIG_BLK_DEV_IO_TRACE is not set
993# CONFIG_DMA_API_DEBUG is not set
975# CONFIG_SAMPLES is not set 994# CONFIG_SAMPLES is not set
976CONFIG_HAVE_ARCH_KGDB=y 995CONFIG_HAVE_ARCH_KGDB=y
977# CONFIG_KGDB is not set 996# CONFIG_KGDB is not set
@@ -1090,6 +1109,7 @@ CONFIG_CRYPTO_DEFLATE=y
1090# 1109#
1091# CONFIG_CRYPTO_ANSI_CPRNG is not set 1110# CONFIG_CRYPTO_ANSI_CPRNG is not set
1092CONFIG_CRYPTO_HW=y 1111CONFIG_CRYPTO_HW=y
1112# CONFIG_BINARY_PRINTF is not set
1093 1113
1094# 1114#
1095# Library routines 1115# Library routines
diff --git a/arch/sh/configs/se7721_defconfig b/arch/sh/configs/se7721_defconfig
index 4b79c2567dc8..56478918440d 100644
--- a/arch/sh/configs/se7721_defconfig
+++ b/arch/sh/configs/se7721_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:51:44 2009 4# Mon Apr 27 13:04:19 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_FIND_NEXT_BIT=y 11CONFIG_GENERIC_FIND_NEXT_BIT=y
@@ -38,6 +39,7 @@ CONFIG_LOCALVERSION=""
38CONFIG_SYSVIPC=y 39CONFIG_SYSVIPC=y
39CONFIG_SYSVIPC_SYSCTL=y 40CONFIG_SYSVIPC_SYSCTL=y
40CONFIG_POSIX_MQUEUE=y 41CONFIG_POSIX_MQUEUE=y
42CONFIG_POSIX_MQUEUE_SYSCTL=y
41CONFIG_BSD_PROCESS_ACCT=y 43CONFIG_BSD_PROCESS_ACCT=y
42# CONFIG_BSD_PROCESS_ACCT_V3 is not set 44# CONFIG_BSD_PROCESS_ACCT_V3 is not set
43# CONFIG_TASKSTATS is not set 45# CONFIG_TASKSTATS is not set
@@ -73,6 +75,7 @@ CONFIG_SYSCTL_SYSCALL=y
73CONFIG_KALLSYMS=y 75CONFIG_KALLSYMS=y
74CONFIG_KALLSYMS_ALL=y 76CONFIG_KALLSYMS_ALL=y
75# CONFIG_KALLSYMS_EXTRA_PASS is not set 77# CONFIG_KALLSYMS_EXTRA_PASS is not set
78# CONFIG_STRIP_ASM_SYMS is not set
76CONFIG_HOTPLUG=y 79CONFIG_HOTPLUG=y
77CONFIG_PRINTK=y 80CONFIG_PRINTK=y
78# CONFIG_BUG is not set 81# CONFIG_BUG is not set
@@ -91,6 +94,7 @@ CONFIG_SLAB=y
91# CONFIG_SLUB is not set 94# CONFIG_SLUB is not set
92# CONFIG_SLOB is not set 95# CONFIG_SLOB is not set
93# CONFIG_PROFILING is not set 96# CONFIG_PROFILING is not set
97# CONFIG_MARKERS is not set
94CONFIG_HAVE_OPROFILE=y 98CONFIG_HAVE_OPROFILE=y
95# CONFIG_KPROBES is not set 99# CONFIG_KPROBES is not set
96CONFIG_HAVE_IOREMAP_PROT=y 100CONFIG_HAVE_IOREMAP_PROT=y
@@ -98,6 +102,8 @@ CONFIG_HAVE_KPROBES=y
98CONFIG_HAVE_KRETPROBES=y 102CONFIG_HAVE_KRETPROBES=y
99CONFIG_HAVE_ARCH_TRACEHOOK=y 103CONFIG_HAVE_ARCH_TRACEHOOK=y
100CONFIG_HAVE_CLK=y 104CONFIG_HAVE_CLK=y
105CONFIG_HAVE_DMA_API_DEBUG=y
106# CONFIG_SLOW_WORK is not set
101CONFIG_HAVE_GENERIC_DMA_COHERENT=y 107CONFIG_HAVE_GENERIC_DMA_COHERENT=y
102CONFIG_SLABINFO=y 108CONFIG_SLABINFO=y
103CONFIG_RT_MUTEXES=y 109CONFIG_RT_MUTEXES=y
@@ -109,7 +115,6 @@ CONFIG_MODULES=y
109# CONFIG_MODULE_SRCVERSION_ALL is not set 115# CONFIG_MODULE_SRCVERSION_ALL is not set
110CONFIG_BLOCK=y 116CONFIG_BLOCK=y
111# CONFIG_LBD is not set 117# CONFIG_LBD is not set
112# CONFIG_BLK_DEV_IO_TRACE is not set
113# CONFIG_BLK_DEV_BSG is not set 118# CONFIG_BLK_DEV_BSG is not set
114# CONFIG_BLK_DEV_INTEGRITY is not set 119# CONFIG_BLK_DEV_INTEGRITY is not set
115 120
@@ -155,6 +160,7 @@ CONFIG_CPU_SUBTYPE_SH7721=y
155# CONFIG_CPU_SUBTYPE_SH7760 is not set 160# CONFIG_CPU_SUBTYPE_SH7760 is not set
156# CONFIG_CPU_SUBTYPE_SH4_202 is not set 161# CONFIG_CPU_SUBTYPE_SH4_202 is not set
157# CONFIG_CPU_SUBTYPE_SH7723 is not set 162# CONFIG_CPU_SUBTYPE_SH7723 is not set
163# CONFIG_CPU_SUBTYPE_SH7724 is not set
158# CONFIG_CPU_SUBTYPE_SH7763 is not set 164# CONFIG_CPU_SUBTYPE_SH7763 is not set
159# CONFIG_CPU_SUBTYPE_SH7770 is not set 165# CONFIG_CPU_SUBTYPE_SH7770 is not set
160# CONFIG_CPU_SUBTYPE_SH7780 is not set 166# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -164,8 +170,6 @@ CONFIG_CPU_SUBTYPE_SH7721=y
164# CONFIG_CPU_SUBTYPE_SH7343 is not set 170# CONFIG_CPU_SUBTYPE_SH7343 is not set
165# CONFIG_CPU_SUBTYPE_SH7722 is not set 171# CONFIG_CPU_SUBTYPE_SH7722 is not set
166# CONFIG_CPU_SUBTYPE_SH7366 is not set 172# CONFIG_CPU_SUBTYPE_SH7366 is not set
167# CONFIG_CPU_SUBTYPE_SH5_101 is not set
168# CONFIG_CPU_SUBTYPE_SH5_103 is not set
169 173
170# 174#
171# Memory management options 175# Memory management options
@@ -776,15 +780,17 @@ CONFIG_USB_HID=y
776# 780#
777# Special HID drivers 781# Special HID drivers
778# 782#
779CONFIG_HID_COMPAT=y
780CONFIG_HID_A4TECH=y 783CONFIG_HID_A4TECH=y
781CONFIG_HID_APPLE=y 784CONFIG_HID_APPLE=y
782CONFIG_HID_BELKIN=y 785CONFIG_HID_BELKIN=y
783CONFIG_HID_CHERRY=y 786CONFIG_HID_CHERRY=y
784CONFIG_HID_CHICONY=y 787CONFIG_HID_CHICONY=y
785CONFIG_HID_CYPRESS=y 788CONFIG_HID_CYPRESS=y
789# CONFIG_DRAGONRISE_FF is not set
786CONFIG_HID_EZKEY=y 790CONFIG_HID_EZKEY=y
791# CONFIG_HID_KYE is not set
787CONFIG_HID_GYRATION=y 792CONFIG_HID_GYRATION=y
793# CONFIG_HID_KENSINGTON is not set
788CONFIG_HID_LOGITECH=y 794CONFIG_HID_LOGITECH=y
789# CONFIG_LOGITECH_FF is not set 795# CONFIG_LOGITECH_FF is not set
790# CONFIG_LOGIRUMBLEPAD2_FF is not set 796# CONFIG_LOGIRUMBLEPAD2_FF is not set
@@ -943,6 +949,7 @@ CONFIG_EXT2_FS_POSIX_ACL=y
943CONFIG_EXT2_FS_SECURITY=y 949CONFIG_EXT2_FS_SECURITY=y
944# CONFIG_EXT2_FS_XIP is not set 950# CONFIG_EXT2_FS_XIP is not set
945CONFIG_EXT3_FS=y 951CONFIG_EXT3_FS=y
952# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
946CONFIG_EXT3_FS_XATTR=y 953CONFIG_EXT3_FS_XATTR=y
947# CONFIG_EXT3_FS_POSIX_ACL is not set 954# CONFIG_EXT3_FS_POSIX_ACL is not set
948# CONFIG_EXT3_FS_SECURITY is not set 955# CONFIG_EXT3_FS_SECURITY is not set
@@ -964,6 +971,11 @@ CONFIG_FILE_LOCKING=y
964# CONFIG_FUSE_FS is not set 971# CONFIG_FUSE_FS is not set
965 972
966# 973#
974# Caches
975#
976# CONFIG_FSCACHE is not set
977
978#
967# CD-ROM/DVD Filesystems 979# CD-ROM/DVD Filesystems
968# 980#
969# CONFIG_ISO9660_FS is not set 981# CONFIG_ISO9660_FS is not set
@@ -1021,6 +1033,7 @@ CONFIG_CRAMFS=y
1021# CONFIG_ROMFS_FS is not set 1033# CONFIG_ROMFS_FS is not set
1022# CONFIG_SYSV_FS is not set 1034# CONFIG_SYSV_FS is not set
1023# CONFIG_UFS_FS is not set 1035# CONFIG_UFS_FS is not set
1036# CONFIG_NILFS2_FS is not set
1024# CONFIG_NETWORK_FILESYSTEMS is not set 1037# CONFIG_NETWORK_FILESYSTEMS is not set
1025 1038
1026# 1039#
@@ -1085,6 +1098,7 @@ CONFIG_FRAME_WARN=1024
1085CONFIG_DEBUG_KERNEL=y 1098CONFIG_DEBUG_KERNEL=y
1086# CONFIG_DEBUG_SHIRQ is not set 1099# CONFIG_DEBUG_SHIRQ is not set
1087# CONFIG_DETECT_SOFTLOCKUP is not set 1100# CONFIG_DETECT_SOFTLOCKUP is not set
1101# CONFIG_DETECT_HUNG_TASK is not set
1088CONFIG_SCHED_DEBUG=y 1102CONFIG_SCHED_DEBUG=y
1089# CONFIG_SCHEDSTATS is not set 1103# CONFIG_SCHEDSTATS is not set
1090# CONFIG_TIMER_STATS is not set 1104# CONFIG_TIMER_STATS is not set
@@ -1119,6 +1133,7 @@ CONFIG_FRAME_POINTER=y
1119CONFIG_HAVE_FUNCTION_TRACER=y 1133CONFIG_HAVE_FUNCTION_TRACER=y
1120CONFIG_HAVE_DYNAMIC_FTRACE=y 1134CONFIG_HAVE_DYNAMIC_FTRACE=y
1121CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1135CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1136CONFIG_TRACING_SUPPORT=y
1122 1137
1123# 1138#
1124# Tracers 1139# Tracers
@@ -1127,9 +1142,14 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1127# CONFIG_IRQSOFF_TRACER is not set 1142# CONFIG_IRQSOFF_TRACER is not set
1128# CONFIG_SCHED_TRACER is not set 1143# CONFIG_SCHED_TRACER is not set
1129# CONFIG_CONTEXT_SWITCH_TRACER is not set 1144# CONFIG_CONTEXT_SWITCH_TRACER is not set
1145# CONFIG_EVENT_TRACER is not set
1130# CONFIG_BOOT_TRACER is not set 1146# CONFIG_BOOT_TRACER is not set
1131# CONFIG_TRACE_BRANCH_PROFILING is not set 1147# CONFIG_TRACE_BRANCH_PROFILING is not set
1132# CONFIG_STACK_TRACER is not set 1148# CONFIG_STACK_TRACER is not set
1149# CONFIG_KMEMTRACE is not set
1150# CONFIG_WORKQUEUE_TRACER is not set
1151# CONFIG_BLK_DEV_IO_TRACE is not set
1152# CONFIG_DMA_API_DEBUG is not set
1133# CONFIG_SAMPLES is not set 1153# CONFIG_SAMPLES is not set
1134CONFIG_HAVE_ARCH_KGDB=y 1154CONFIG_HAVE_ARCH_KGDB=y
1135# CONFIG_KGDB is not set 1155# CONFIG_KGDB is not set
@@ -1248,6 +1268,7 @@ CONFIG_CRYPTO_DEFLATE=y
1248# 1268#
1249# CONFIG_CRYPTO_ANSI_CPRNG is not set 1269# CONFIG_CRYPTO_ANSI_CPRNG is not set
1250CONFIG_CRYPTO_HW=y 1270CONFIG_CRYPTO_HW=y
1271# CONFIG_BINARY_PRINTF is not set
1251 1272
1252# 1273#
1253# Library routines 1274# Library routines
diff --git a/arch/sh/configs/se7722_defconfig b/arch/sh/configs/se7722_defconfig
index 82bdaac45fb5..726fdbdb2807 100644
--- a/arch/sh/configs/se7722_defconfig
+++ b/arch/sh/configs/se7722_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:55:10 2009 4# Mon Apr 27 13:05:29 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -69,7 +70,6 @@ CONFIG_INITRAMFS_SOURCE=""
69CONFIG_RD_GZIP=y 70CONFIG_RD_GZIP=y
70# CONFIG_RD_BZIP2 is not set 71# CONFIG_RD_BZIP2 is not set
71# CONFIG_RD_LZMA is not set 72# CONFIG_RD_LZMA is not set
72CONFIG_INITRAMFS_COMPRESSION_NONE=y
73CONFIG_CC_OPTIMIZE_FOR_SIZE=y 73CONFIG_CC_OPTIMIZE_FOR_SIZE=y
74CONFIG_SYSCTL=y 74CONFIG_SYSCTL=y
75CONFIG_ANON_INODES=y 75CONFIG_ANON_INODES=y
@@ -78,6 +78,7 @@ CONFIG_UID16=y
78CONFIG_SYSCTL_SYSCALL=y 78CONFIG_SYSCTL_SYSCALL=y
79CONFIG_KALLSYMS=y 79CONFIG_KALLSYMS=y
80# CONFIG_KALLSYMS_EXTRA_PASS is not set 80# CONFIG_KALLSYMS_EXTRA_PASS is not set
81# CONFIG_STRIP_ASM_SYMS is not set
81CONFIG_HOTPLUG=y 82CONFIG_HOTPLUG=y
82CONFIG_PRINTK=y 83CONFIG_PRINTK=y
83CONFIG_BUG=y 84CONFIG_BUG=y
@@ -97,6 +98,7 @@ CONFIG_COMPAT_BRK=y
97CONFIG_SLUB=y 98CONFIG_SLUB=y
98# CONFIG_SLOB is not set 99# CONFIG_SLOB is not set
99CONFIG_PROFILING=y 100CONFIG_PROFILING=y
101# CONFIG_MARKERS is not set
100# CONFIG_OPROFILE is not set 102# CONFIG_OPROFILE is not set
101CONFIG_HAVE_OPROFILE=y 103CONFIG_HAVE_OPROFILE=y
102# CONFIG_KPROBES is not set 104# CONFIG_KPROBES is not set
@@ -105,6 +107,8 @@ CONFIG_HAVE_KPROBES=y
105CONFIG_HAVE_KRETPROBES=y 107CONFIG_HAVE_KRETPROBES=y
106CONFIG_HAVE_ARCH_TRACEHOOK=y 108CONFIG_HAVE_ARCH_TRACEHOOK=y
107CONFIG_HAVE_CLK=y 109CONFIG_HAVE_CLK=y
110CONFIG_HAVE_DMA_API_DEBUG=y
111# CONFIG_SLOW_WORK is not set
108CONFIG_HAVE_GENERIC_DMA_COHERENT=y 112CONFIG_HAVE_GENERIC_DMA_COHERENT=y
109CONFIG_SLABINFO=y 113CONFIG_SLABINFO=y
110CONFIG_RT_MUTEXES=y 114CONFIG_RT_MUTEXES=y
@@ -117,7 +121,6 @@ CONFIG_MODULE_UNLOAD=y
117# CONFIG_MODULE_SRCVERSION_ALL is not set 121# CONFIG_MODULE_SRCVERSION_ALL is not set
118CONFIG_BLOCK=y 122CONFIG_BLOCK=y
119# CONFIG_LBD is not set 123# CONFIG_LBD is not set
120# CONFIG_BLK_DEV_IO_TRACE is not set
121# CONFIG_BLK_DEV_BSG is not set 124# CONFIG_BLK_DEV_BSG is not set
122# CONFIG_BLK_DEV_INTEGRITY is not set 125# CONFIG_BLK_DEV_INTEGRITY is not set
123 126
@@ -167,6 +170,7 @@ CONFIG_ARCH_SHMOBILE=y
167# CONFIG_CPU_SUBTYPE_SH7760 is not set 170# CONFIG_CPU_SUBTYPE_SH7760 is not set
168# CONFIG_CPU_SUBTYPE_SH4_202 is not set 171# CONFIG_CPU_SUBTYPE_SH4_202 is not set
169# CONFIG_CPU_SUBTYPE_SH7723 is not set 172# CONFIG_CPU_SUBTYPE_SH7723 is not set
173# CONFIG_CPU_SUBTYPE_SH7724 is not set
170# CONFIG_CPU_SUBTYPE_SH7763 is not set 174# CONFIG_CPU_SUBTYPE_SH7763 is not set
171# CONFIG_CPU_SUBTYPE_SH7770 is not set 175# CONFIG_CPU_SUBTYPE_SH7770 is not set
172# CONFIG_CPU_SUBTYPE_SH7780 is not set 176# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -176,8 +180,6 @@ CONFIG_ARCH_SHMOBILE=y
176# CONFIG_CPU_SUBTYPE_SH7343 is not set 180# CONFIG_CPU_SUBTYPE_SH7343 is not set
177CONFIG_CPU_SUBTYPE_SH7722=y 181CONFIG_CPU_SUBTYPE_SH7722=y
178# CONFIG_CPU_SUBTYPE_SH7366 is not set 182# CONFIG_CPU_SUBTYPE_SH7366 is not set
179# CONFIG_CPU_SUBTYPE_SH5_101 is not set
180# CONFIG_CPU_SUBTYPE_SH5_103 is not set
181 183
182# 184#
183# Memory management options 185# Memory management options
@@ -486,6 +488,7 @@ CONFIG_SCSI_WAIT_SCAN=m
486CONFIG_SCSI_LOWLEVEL=y 488CONFIG_SCSI_LOWLEVEL=y
487# CONFIG_ISCSI_TCP is not set 489# CONFIG_ISCSI_TCP is not set
488# CONFIG_LIBFC is not set 490# CONFIG_LIBFC is not set
491# CONFIG_LIBFCOE is not set
489# CONFIG_SCSI_DEBUG is not set 492# CONFIG_SCSI_DEBUG is not set
490# CONFIG_SCSI_DH is not set 493# CONFIG_SCSI_DH is not set
491# CONFIG_SCSI_OSD_INITIATOR is not set 494# CONFIG_SCSI_OSD_INITIATOR is not set
@@ -692,7 +695,6 @@ CONFIG_HID=y
692# 695#
693# Special HID drivers 696# Special HID drivers
694# 697#
695CONFIG_HID_COMPAT=y
696CONFIG_USB_SUPPORT=y 698CONFIG_USB_SUPPORT=y
697CONFIG_USB_ARCH_HAS_HCD=y 699CONFIG_USB_ARCH_HAS_HCD=y
698# CONFIG_USB_ARCH_HAS_OHCI is not set 700# CONFIG_USB_ARCH_HAS_OHCI is not set
@@ -766,6 +768,7 @@ CONFIG_EXT2_FS=y
766# CONFIG_EXT2_FS_XATTR is not set 768# CONFIG_EXT2_FS_XATTR is not set
767# CONFIG_EXT2_FS_XIP is not set 769# CONFIG_EXT2_FS_XIP is not set
768CONFIG_EXT3_FS=y 770CONFIG_EXT3_FS=y
771# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
769CONFIG_EXT3_FS_XATTR=y 772CONFIG_EXT3_FS_XATTR=y
770# CONFIG_EXT3_FS_POSIX_ACL is not set 773# CONFIG_EXT3_FS_POSIX_ACL is not set
771# CONFIG_EXT3_FS_SECURITY is not set 774# CONFIG_EXT3_FS_SECURITY is not set
@@ -789,6 +792,11 @@ CONFIG_INOTIFY_USER=y
789# CONFIG_FUSE_FS is not set 792# CONFIG_FUSE_FS is not set
790 793
791# 794#
795# Caches
796#
797# CONFIG_FSCACHE is not set
798
799#
792# CD-ROM/DVD Filesystems 800# CD-ROM/DVD Filesystems
793# 801#
794# CONFIG_ISO9660_FS is not set 802# CONFIG_ISO9660_FS is not set
@@ -832,6 +840,7 @@ CONFIG_MISC_FILESYSTEMS=y
832# CONFIG_ROMFS_FS is not set 840# CONFIG_ROMFS_FS is not set
833# CONFIG_SYSV_FS is not set 841# CONFIG_SYSV_FS is not set
834# CONFIG_UFS_FS is not set 842# CONFIG_UFS_FS is not set
843# CONFIG_NILFS2_FS is not set
835CONFIG_NETWORK_FILESYSTEMS=y 844CONFIG_NETWORK_FILESYSTEMS=y
836# CONFIG_NFS_FS is not set 845# CONFIG_NFS_FS is not set
837# CONFIG_NFSD is not set 846# CONFIG_NFSD is not set
@@ -872,11 +881,25 @@ CONFIG_DEBUG_FS=y
872CONFIG_HAVE_FUNCTION_TRACER=y 881CONFIG_HAVE_FUNCTION_TRACER=y
873CONFIG_HAVE_DYNAMIC_FTRACE=y 882CONFIG_HAVE_DYNAMIC_FTRACE=y
874CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 883CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
884CONFIG_TRACING_SUPPORT=y
875 885
876# 886#
877# Tracers 887# Tracers
878# 888#
889# CONFIG_FUNCTION_TRACER is not set
890# CONFIG_IRQSOFF_TRACER is not set
891# CONFIG_PREEMPT_TRACER is not set
892# CONFIG_SCHED_TRACER is not set
893# CONFIG_CONTEXT_SWITCH_TRACER is not set
894# CONFIG_EVENT_TRACER is not set
895# CONFIG_BOOT_TRACER is not set
896# CONFIG_TRACE_BRANCH_PROFILING is not set
897# CONFIG_STACK_TRACER is not set
898# CONFIG_KMEMTRACE is not set
899# CONFIG_WORKQUEUE_TRACER is not set
900# CONFIG_BLK_DEV_IO_TRACE is not set
879# CONFIG_DYNAMIC_DEBUG is not set 901# CONFIG_DYNAMIC_DEBUG is not set
902# CONFIG_DMA_API_DEBUG is not set
880# CONFIG_SAMPLES is not set 903# CONFIG_SAMPLES is not set
881CONFIG_HAVE_ARCH_KGDB=y 904CONFIG_HAVE_ARCH_KGDB=y
882CONFIG_SH_STANDARD_BIOS=y 905CONFIG_SH_STANDARD_BIOS=y
@@ -977,6 +1000,7 @@ CONFIG_CRYPTO=y
977# 1000#
978# CONFIG_CRYPTO_ANSI_CPRNG is not set 1001# CONFIG_CRYPTO_ANSI_CPRNG is not set
979CONFIG_CRYPTO_HW=y 1002CONFIG_CRYPTO_HW=y
1003# CONFIG_BINARY_PRINTF is not set
980 1004
981# 1005#
982# Library routines 1006# Library routines
diff --git a/arch/sh/configs/se7724_defconfig b/arch/sh/configs/se7724_defconfig
new file mode 100644
index 000000000000..96d2587467e6
--- /dev/null
+++ b/arch/sh/configs/se7724_defconfig
@@ -0,0 +1,1552 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.30-rc6
4# Tue May 26 13:18:09 2009
5#
6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
10CONFIG_RWSEM_GENERIC_SPINLOCK=y
11CONFIG_GENERIC_BUG=y
12CONFIG_GENERIC_FIND_NEXT_BIT=y
13CONFIG_GENERIC_HWEIGHT=y
14CONFIG_GENERIC_HARDIRQS=y
15CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
16CONFIG_GENERIC_IRQ_PROBE=y
17CONFIG_GENERIC_GPIO=y
18CONFIG_GENERIC_TIME=y
19CONFIG_GENERIC_CLOCKEVENTS=y
20CONFIG_ARCH_SUSPEND_POSSIBLE=y
21CONFIG_ARCH_HIBERNATION_POSSIBLE=y
22CONFIG_SYS_SUPPORTS_CMT=y
23CONFIG_SYS_SUPPORTS_TMU=y
24CONFIG_STACKTRACE_SUPPORT=y
25CONFIG_LOCKDEP_SUPPORT=y
26CONFIG_HAVE_LATENCYTOP_SUPPORT=y
27# CONFIG_ARCH_HAS_ILOG2_U32 is not set
28# CONFIG_ARCH_HAS_ILOG2_U64 is not set
29CONFIG_ARCH_NO_VIRT_TO_BUS=y
30CONFIG_ARCH_HAS_DEFAULT_IDLE=y
31CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
32
33#
34# General setup
35#
36CONFIG_EXPERIMENTAL=y
37CONFIG_BROKEN_ON_SMP=y
38CONFIG_LOCK_KERNEL=y
39CONFIG_INIT_ENV_ARG_LIMIT=32
40CONFIG_LOCALVERSION=""
41# CONFIG_LOCALVERSION_AUTO is not set
42CONFIG_SWAP=y
43CONFIG_SYSVIPC=y
44CONFIG_SYSVIPC_SYSCTL=y
45# CONFIG_POSIX_MQUEUE is not set
46CONFIG_BSD_PROCESS_ACCT=y
47# CONFIG_BSD_PROCESS_ACCT_V3 is not set
48# CONFIG_TASKSTATS is not set
49# CONFIG_AUDIT is not set
50
51#
52# RCU Subsystem
53#
54CONFIG_CLASSIC_RCU=y
55# CONFIG_TREE_RCU is not set
56# CONFIG_PREEMPT_RCU is not set
57# CONFIG_TREE_RCU_TRACE is not set
58# CONFIG_PREEMPT_RCU_TRACE is not set
59# CONFIG_IKCONFIG is not set
60CONFIG_LOG_BUF_SHIFT=14
61CONFIG_GROUP_SCHED=y
62CONFIG_FAIR_GROUP_SCHED=y
63# CONFIG_RT_GROUP_SCHED is not set
64CONFIG_USER_SCHED=y
65# CONFIG_CGROUP_SCHED is not set
66# CONFIG_CGROUPS is not set
67CONFIG_SYSFS_DEPRECATED=y
68CONFIG_SYSFS_DEPRECATED_V2=y
69# CONFIG_RELAY is not set
70# CONFIG_NAMESPACES is not set
71# CONFIG_BLK_DEV_INITRD is not set
72CONFIG_CC_OPTIMIZE_FOR_SIZE=y
73CONFIG_SYSCTL=y
74CONFIG_ANON_INODES=y
75CONFIG_EMBEDDED=y
76CONFIG_UID16=y
77CONFIG_SYSCTL_SYSCALL=y
78# CONFIG_KALLSYMS is not set
79# CONFIG_STRIP_ASM_SYMS is not set
80CONFIG_HOTPLUG=y
81CONFIG_PRINTK=y
82CONFIG_BUG=y
83CONFIG_ELF_CORE=y
84CONFIG_BASE_FULL=y
85CONFIG_FUTEX=y
86CONFIG_EPOLL=y
87CONFIG_SIGNALFD=y
88CONFIG_TIMERFD=y
89CONFIG_EVENTFD=y
90CONFIG_SHMEM=y
91CONFIG_AIO=y
92CONFIG_VM_EVENT_COUNTERS=y
93CONFIG_COMPAT_BRK=y
94CONFIG_SLAB=y
95# CONFIG_SLUB is not set
96# CONFIG_SLOB is not set
97# CONFIG_PROFILING is not set
98# CONFIG_MARKERS is not set
99CONFIG_HAVE_OPROFILE=y
100CONFIG_HAVE_IOREMAP_PROT=y
101CONFIG_HAVE_KPROBES=y
102CONFIG_HAVE_KRETPROBES=y
103CONFIG_HAVE_ARCH_TRACEHOOK=y
104CONFIG_HAVE_CLK=y
105CONFIG_HAVE_DMA_API_DEBUG=y
106# CONFIG_SLOW_WORK is not set
107CONFIG_HAVE_GENERIC_DMA_COHERENT=y
108CONFIG_SLABINFO=y
109CONFIG_RT_MUTEXES=y
110CONFIG_BASE_SMALL=0
111CONFIG_MODULES=y
112# CONFIG_MODULE_FORCE_LOAD is not set
113CONFIG_MODULE_UNLOAD=y
114# CONFIG_MODULE_FORCE_UNLOAD is not set
115# CONFIG_MODVERSIONS is not set
116# CONFIG_MODULE_SRCVERSION_ALL is not set
117CONFIG_BLOCK=y
118# CONFIG_LBD is not set
119# CONFIG_BLK_DEV_BSG is not set
120# CONFIG_BLK_DEV_INTEGRITY is not set
121
122#
123# IO Schedulers
124#
125CONFIG_IOSCHED_NOOP=y
126CONFIG_IOSCHED_AS=y
127CONFIG_IOSCHED_DEADLINE=y
128CONFIG_IOSCHED_CFQ=y
129# CONFIG_DEFAULT_AS is not set
130# CONFIG_DEFAULT_DEADLINE is not set
131CONFIG_DEFAULT_CFQ=y
132# CONFIG_DEFAULT_NOOP is not set
133CONFIG_DEFAULT_IOSCHED="cfq"
134# CONFIG_FREEZER is not set
135
136#
137# System type
138#
139CONFIG_CPU_SH4=y
140CONFIG_CPU_SH4A=y
141CONFIG_CPU_SHX2=y
142CONFIG_ARCH_SHMOBILE=y
143# CONFIG_CPU_SUBTYPE_SH7619 is not set
144# CONFIG_CPU_SUBTYPE_SH7201 is not set
145# CONFIG_CPU_SUBTYPE_SH7203 is not set
146# CONFIG_CPU_SUBTYPE_SH7206 is not set
147# CONFIG_CPU_SUBTYPE_SH7263 is not set
148# CONFIG_CPU_SUBTYPE_MXG is not set
149# CONFIG_CPU_SUBTYPE_SH7705 is not set
150# CONFIG_CPU_SUBTYPE_SH7706 is not set
151# CONFIG_CPU_SUBTYPE_SH7707 is not set
152# CONFIG_CPU_SUBTYPE_SH7708 is not set
153# CONFIG_CPU_SUBTYPE_SH7709 is not set
154# CONFIG_CPU_SUBTYPE_SH7710 is not set
155# CONFIG_CPU_SUBTYPE_SH7712 is not set
156# CONFIG_CPU_SUBTYPE_SH7720 is not set
157# CONFIG_CPU_SUBTYPE_SH7721 is not set
158# CONFIG_CPU_SUBTYPE_SH7750 is not set
159# CONFIG_CPU_SUBTYPE_SH7091 is not set
160# CONFIG_CPU_SUBTYPE_SH7750R is not set
161# CONFIG_CPU_SUBTYPE_SH7750S is not set
162# CONFIG_CPU_SUBTYPE_SH7751 is not set
163# CONFIG_CPU_SUBTYPE_SH7751R is not set
164# CONFIG_CPU_SUBTYPE_SH7760 is not set
165# CONFIG_CPU_SUBTYPE_SH4_202 is not set
166# CONFIG_CPU_SUBTYPE_SH7723 is not set
167CONFIG_CPU_SUBTYPE_SH7724=y
168# CONFIG_CPU_SUBTYPE_SH7763 is not set
169# CONFIG_CPU_SUBTYPE_SH7770 is not set
170# CONFIG_CPU_SUBTYPE_SH7780 is not set
171# CONFIG_CPU_SUBTYPE_SH7785 is not set
172# CONFIG_CPU_SUBTYPE_SH7786 is not set
173# CONFIG_CPU_SUBTYPE_SHX3 is not set
174# CONFIG_CPU_SUBTYPE_SH7343 is not set
175# CONFIG_CPU_SUBTYPE_SH7722 is not set
176# CONFIG_CPU_SUBTYPE_SH7366 is not set
177
178#
179# Memory management options
180#
181CONFIG_QUICKLIST=y
182CONFIG_MMU=y
183CONFIG_PAGE_OFFSET=0x80000000
184CONFIG_FORCE_MAX_ZONEORDER=11
185CONFIG_MEMORY_START=0x08000000
186CONFIG_MEMORY_SIZE=0x08000000
187CONFIG_29BIT=y
188# CONFIG_X2TLB is not set
189CONFIG_VSYSCALL=y
190CONFIG_ARCH_FLATMEM_ENABLE=y
191CONFIG_ARCH_SPARSEMEM_ENABLE=y
192CONFIG_ARCH_SPARSEMEM_DEFAULT=y
193CONFIG_MAX_ACTIVE_REGIONS=1
194CONFIG_ARCH_POPULATES_NODE_MAP=y
195CONFIG_ARCH_SELECT_MEMORY_MODEL=y
196CONFIG_PAGE_SIZE_4KB=y
197# CONFIG_PAGE_SIZE_8KB is not set
198# CONFIG_PAGE_SIZE_16KB is not set
199# CONFIG_PAGE_SIZE_64KB is not set
200CONFIG_SELECT_MEMORY_MODEL=y
201CONFIG_FLATMEM_MANUAL=y
202# CONFIG_DISCONTIGMEM_MANUAL is not set
203# CONFIG_SPARSEMEM_MANUAL is not set
204CONFIG_FLATMEM=y
205CONFIG_FLAT_NODE_MEM_MAP=y
206CONFIG_SPARSEMEM_STATIC=y
207CONFIG_PAGEFLAGS_EXTENDED=y
208CONFIG_SPLIT_PTLOCK_CPUS=4
209# CONFIG_PHYS_ADDR_T_64BIT is not set
210CONFIG_ZONE_DMA_FLAG=0
211CONFIG_NR_QUICK=2
212CONFIG_UNEVICTABLE_LRU=y
213CONFIG_HAVE_MLOCK=y
214CONFIG_HAVE_MLOCKED_PAGE_BIT=y
215
216#
217# Cache configuration
218#
219CONFIG_CACHE_WRITEBACK=y
220# CONFIG_CACHE_WRITETHROUGH is not set
221# CONFIG_CACHE_OFF is not set
222
223#
224# Processor features
225#
226CONFIG_CPU_LITTLE_ENDIAN=y
227# CONFIG_CPU_BIG_ENDIAN is not set
228CONFIG_SH_FPU=y
229# CONFIG_SH_STORE_QUEUES is not set
230CONFIG_CPU_HAS_INTEVT=y
231CONFIG_CPU_HAS_SR_RB=y
232CONFIG_CPU_HAS_PTEA=y
233CONFIG_CPU_HAS_FPU=y
234
235#
236# Board support
237#
238CONFIG_SOLUTION_ENGINE=y
239CONFIG_SH_7724_SOLUTION_ENGINE=y
240
241#
242# Timer and clock configuration
243#
244CONFIG_SH_TIMER_TMU=y
245# CONFIG_SH_TIMER_CMT is not set
246CONFIG_SH_PCLK_FREQ=33333333
247# CONFIG_NO_HZ is not set
248# CONFIG_HIGH_RES_TIMERS is not set
249CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
250
251#
252# CPU Frequency scaling
253#
254# CONFIG_CPU_FREQ is not set
255
256#
257# DMA support
258#
259# CONFIG_SH_DMA is not set
260
261#
262# Companion Chips
263#
264
265#
266# Additional SuperH Device Drivers
267#
268CONFIG_HEARTBEAT=y
269# CONFIG_PUSH_SWITCH is not set
270
271#
272# Kernel features
273#
274# CONFIG_HZ_100 is not set
275CONFIG_HZ_250=y
276# CONFIG_HZ_300 is not set
277# CONFIG_HZ_1000 is not set
278CONFIG_HZ=250
279# CONFIG_SCHED_HRTICK is not set
280# CONFIG_KEXEC is not set
281# CONFIG_CRASH_DUMP is not set
282CONFIG_SECCOMP=y
283# CONFIG_PREEMPT_NONE is not set
284# CONFIG_PREEMPT_VOLUNTARY is not set
285CONFIG_PREEMPT=y
286CONFIG_GUSA=y
287
288#
289# Boot options
290#
291CONFIG_ZERO_PAGE_OFFSET=0x00001000
292CONFIG_BOOT_LINK_OFFSET=0x00800000
293CONFIG_ENTRY_OFFSET=0x00001000
294CONFIG_CMDLINE_BOOL=y
295CONFIG_CMDLINE="console=tty1 console=ttySC3,115200 root=/dev/nfs ip=dhcp memchunk.vpu=4m"
296
297#
298# Bus options
299#
300# CONFIG_ARCH_SUPPORTS_MSI is not set
301# CONFIG_PCCARD is not set
302
303#
304# Executable file formats
305#
306CONFIG_BINFMT_ELF=y
307# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
308# CONFIG_HAVE_AOUT is not set
309# CONFIG_BINFMT_MISC is not set
310
311#
312# Power management options (EXPERIMENTAL)
313#
314# CONFIG_PM is not set
315# CONFIG_CPU_IDLE is not set
316CONFIG_NET=y
317
318#
319# Networking options
320#
321CONFIG_PACKET=y
322# CONFIG_PACKET_MMAP is not set
323CONFIG_UNIX=y
324# CONFIG_NET_KEY is not set
325CONFIG_INET=y
326# CONFIG_IP_MULTICAST is not set
327CONFIG_IP_ADVANCED_ROUTER=y
328CONFIG_ASK_IP_FIB_HASH=y
329# CONFIG_IP_FIB_TRIE is not set
330CONFIG_IP_FIB_HASH=y
331# CONFIG_IP_MULTIPLE_TABLES is not set
332# CONFIG_IP_ROUTE_MULTIPATH is not set
333# CONFIG_IP_ROUTE_VERBOSE is not set
334CONFIG_IP_PNP=y
335CONFIG_IP_PNP_DHCP=y
336# CONFIG_IP_PNP_BOOTP is not set
337# CONFIG_IP_PNP_RARP is not set
338# CONFIG_NET_IPIP is not set
339# CONFIG_NET_IPGRE is not set
340# CONFIG_ARPD is not set
341# CONFIG_SYN_COOKIES is not set
342# CONFIG_INET_AH is not set
343# CONFIG_INET_ESP is not set
344# CONFIG_INET_IPCOMP is not set
345# CONFIG_INET_XFRM_TUNNEL is not set
346# CONFIG_INET_TUNNEL is not set
347# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
348# CONFIG_INET_XFRM_MODE_TUNNEL is not set
349# CONFIG_INET_XFRM_MODE_BEET is not set
350# CONFIG_INET_LRO is not set
351CONFIG_INET_DIAG=y
352CONFIG_INET_TCP_DIAG=y
353# CONFIG_TCP_CONG_ADVANCED is not set
354CONFIG_TCP_CONG_CUBIC=y
355CONFIG_DEFAULT_TCP_CONG="cubic"
356# CONFIG_TCP_MD5SIG is not set
357# CONFIG_IPV6 is not set
358# CONFIG_NETWORK_SECMARK is not set
359# CONFIG_NETFILTER is not set
360# CONFIG_IP_DCCP is not set
361# CONFIG_IP_SCTP is not set
362# CONFIG_TIPC is not set
363# CONFIG_ATM is not set
364# CONFIG_BRIDGE is not set
365# CONFIG_NET_DSA is not set
366# CONFIG_VLAN_8021Q is not set
367# CONFIG_DECNET is not set
368# CONFIG_LLC2 is not set
369# CONFIG_IPX is not set
370# CONFIG_ATALK is not set
371# CONFIG_X25 is not set
372# CONFIG_LAPB is not set
373# CONFIG_ECONET is not set
374# CONFIG_WAN_ROUTER is not set
375# CONFIG_PHONET is not set
376# CONFIG_NET_SCHED is not set
377# CONFIG_DCB is not set
378
379#
380# Network testing
381#
382# CONFIG_NET_PKTGEN is not set
383# CONFIG_HAMRADIO is not set
384# CONFIG_CAN is not set
385# CONFIG_IRDA is not set
386# CONFIG_BT is not set
387# CONFIG_AF_RXRPC is not set
388CONFIG_WIRELESS=y
389# CONFIG_CFG80211 is not set
390# CONFIG_WIRELESS_OLD_REGULATORY is not set
391# CONFIG_WIRELESS_EXT is not set
392# CONFIG_LIB80211 is not set
393# CONFIG_MAC80211 is not set
394# CONFIG_WIMAX is not set
395# CONFIG_RFKILL is not set
396# CONFIG_NET_9P is not set
397
398#
399# Device Drivers
400#
401
402#
403# Generic Driver Options
404#
405CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
406CONFIG_STANDALONE=y
407CONFIG_PREVENT_FIRMWARE_BUILD=y
408CONFIG_FW_LOADER=y
409CONFIG_FIRMWARE_IN_KERNEL=y
410CONFIG_EXTRA_FIRMWARE=""
411# CONFIG_SYS_HYPERVISOR is not set
412# CONFIG_CONNECTOR is not set
413CONFIG_MTD=y
414# CONFIG_MTD_DEBUG is not set
415CONFIG_MTD_CONCAT=y
416CONFIG_MTD_PARTITIONS=y
417# CONFIG_MTD_TESTS is not set
418# CONFIG_MTD_REDBOOT_PARTS is not set
419CONFIG_MTD_CMDLINE_PARTS=y
420# CONFIG_MTD_AR7_PARTS is not set
421
422#
423# User Modules And Translation Layers
424#
425CONFIG_MTD_CHAR=y
426CONFIG_MTD_BLKDEVS=y
427CONFIG_MTD_BLOCK=y
428# CONFIG_FTL is not set
429# CONFIG_NFTL is not set
430# CONFIG_INFTL is not set
431# CONFIG_RFD_FTL is not set
432# CONFIG_SSFDC is not set
433# CONFIG_MTD_OOPS is not set
434
435#
436# RAM/ROM/Flash chip drivers
437#
438CONFIG_MTD_CFI=y
439# CONFIG_MTD_JEDECPROBE is not set
440CONFIG_MTD_GEN_PROBE=y
441# CONFIG_MTD_CFI_ADV_OPTIONS is not set
442CONFIG_MTD_MAP_BANK_WIDTH_1=y
443CONFIG_MTD_MAP_BANK_WIDTH_2=y
444CONFIG_MTD_MAP_BANK_WIDTH_4=y
445# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
446# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
447# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
448CONFIG_MTD_CFI_I1=y
449CONFIG_MTD_CFI_I2=y
450# CONFIG_MTD_CFI_I4 is not set
451# CONFIG_MTD_CFI_I8 is not set
452# CONFIG_MTD_CFI_INTELEXT is not set
453CONFIG_MTD_CFI_AMDSTD=y
454# CONFIG_MTD_CFI_STAA is not set
455CONFIG_MTD_CFI_UTIL=y
456# CONFIG_MTD_RAM is not set
457# CONFIG_MTD_ROM is not set
458# CONFIG_MTD_ABSENT is not set
459
460#
461# Mapping drivers for chip access
462#
463# CONFIG_MTD_COMPLEX_MAPPINGS is not set
464CONFIG_MTD_PHYSMAP=y
465# CONFIG_MTD_PHYSMAP_COMPAT is not set
466# CONFIG_MTD_PLATRAM is not set
467
468#
469# Self-contained MTD device drivers
470#
471# CONFIG_MTD_DATAFLASH is not set
472# CONFIG_MTD_M25P80 is not set
473# CONFIG_MTD_SLRAM is not set
474# CONFIG_MTD_PHRAM is not set
475# CONFIG_MTD_MTDRAM is not set
476# CONFIG_MTD_BLOCK2MTD is not set
477
478#
479# Disk-On-Chip Device Drivers
480#
481# CONFIG_MTD_DOC2000 is not set
482# CONFIG_MTD_DOC2001 is not set
483# CONFIG_MTD_DOC2001PLUS is not set
484CONFIG_MTD_NAND=y
485# CONFIG_MTD_NAND_VERIFY_WRITE is not set
486# CONFIG_MTD_NAND_ECC_SMC is not set
487# CONFIG_MTD_NAND_MUSEUM_IDS is not set
488CONFIG_MTD_NAND_IDS=y
489# CONFIG_MTD_NAND_DISKONCHIP is not set
490# CONFIG_MTD_NAND_NANDSIM is not set
491# CONFIG_MTD_NAND_PLATFORM is not set
492# CONFIG_MTD_ALAUDA is not set
493# CONFIG_MTD_ONENAND is not set
494
495#
496# LPDDR flash memory drivers
497#
498# CONFIG_MTD_LPDDR is not set
499
500#
501# UBI - Unsorted block images
502#
503CONFIG_MTD_UBI=y
504CONFIG_MTD_UBI_WL_THRESHOLD=4096
505CONFIG_MTD_UBI_BEB_RESERVE=1
506# CONFIG_MTD_UBI_GLUEBI is not set
507
508#
509# UBI debugging options
510#
511# CONFIG_MTD_UBI_DEBUG is not set
512# CONFIG_PARPORT is not set
513CONFIG_BLK_DEV=y
514# CONFIG_BLK_DEV_COW_COMMON is not set
515# CONFIG_BLK_DEV_LOOP is not set
516# CONFIG_BLK_DEV_NBD is not set
517# CONFIG_BLK_DEV_UB is not set
518CONFIG_BLK_DEV_RAM=y
519CONFIG_BLK_DEV_RAM_COUNT=4
520CONFIG_BLK_DEV_RAM_SIZE=4096
521# CONFIG_BLK_DEV_XIP is not set
522# CONFIG_CDROM_PKTCDVD is not set
523# CONFIG_ATA_OVER_ETH is not set
524# CONFIG_BLK_DEV_HD is not set
525CONFIG_MISC_DEVICES=y
526# CONFIG_ICS932S401 is not set
527# CONFIG_ENCLOSURE_SERVICES is not set
528# CONFIG_ISL29003 is not set
529# CONFIG_C2PORT is not set
530
531#
532# EEPROM support
533#
534# CONFIG_EEPROM_AT24 is not set
535# CONFIG_EEPROM_AT25 is not set
536# CONFIG_EEPROM_LEGACY is not set
537# CONFIG_EEPROM_93CX6 is not set
538CONFIG_HAVE_IDE=y
539# CONFIG_IDE is not set
540
541#
542# SCSI device support
543#
544# CONFIG_RAID_ATTRS is not set
545CONFIG_SCSI=y
546CONFIG_SCSI_DMA=y
547# CONFIG_SCSI_TGT is not set
548# CONFIG_SCSI_NETLINK is not set
549CONFIG_SCSI_PROC_FS=y
550
551#
552# SCSI support type (disk, tape, CD-ROM)
553#
554CONFIG_BLK_DEV_SD=y
555# CONFIG_CHR_DEV_ST is not set
556# CONFIG_CHR_DEV_OSST is not set
557# CONFIG_BLK_DEV_SR is not set
558# CONFIG_CHR_DEV_SG is not set
559# CONFIG_CHR_DEV_SCH is not set
560
561#
562# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
563#
564# CONFIG_SCSI_MULTI_LUN is not set
565# CONFIG_SCSI_CONSTANTS is not set
566# CONFIG_SCSI_LOGGING is not set
567# CONFIG_SCSI_SCAN_ASYNC is not set
568CONFIG_SCSI_WAIT_SCAN=m
569
570#
571# SCSI Transports
572#
573# CONFIG_SCSI_SPI_ATTRS is not set
574# CONFIG_SCSI_FC_ATTRS is not set
575# CONFIG_SCSI_ISCSI_ATTRS is not set
576# CONFIG_SCSI_SAS_LIBSAS is not set
577# CONFIG_SCSI_SRP_ATTRS is not set
578CONFIG_SCSI_LOWLEVEL=y
579# CONFIG_ISCSI_TCP is not set
580# CONFIG_LIBFC is not set
581# CONFIG_LIBFCOE is not set
582# CONFIG_SCSI_DEBUG is not set
583# CONFIG_SCSI_DH is not set
584# CONFIG_SCSI_OSD_INITIATOR is not set
585# CONFIG_ATA is not set
586# CONFIG_MD is not set
587CONFIG_NETDEVICES=y
588CONFIG_COMPAT_NET_DEV_OPS=y
589# CONFIG_DUMMY is not set
590# CONFIG_BONDING is not set
591# CONFIG_MACVLAN is not set
592# CONFIG_EQUALIZER is not set
593# CONFIG_TUN is not set
594# CONFIG_VETH is not set
595CONFIG_PHYLIB=y
596
597#
598# MII PHY device drivers
599#
600# CONFIG_MARVELL_PHY is not set
601# CONFIG_DAVICOM_PHY is not set
602# CONFIG_QSEMI_PHY is not set
603# CONFIG_LXT_PHY is not set
604# CONFIG_CICADA_PHY is not set
605# CONFIG_VITESSE_PHY is not set
606CONFIG_SMSC_PHY=y
607# CONFIG_BROADCOM_PHY is not set
608# CONFIG_ICPLUS_PHY is not set
609# CONFIG_REALTEK_PHY is not set
610# CONFIG_NATIONAL_PHY is not set
611# CONFIG_STE10XP is not set
612# CONFIG_LSI_ET1011C_PHY is not set
613# CONFIG_FIXED_PHY is not set
614CONFIG_MDIO_BITBANG=y
615# CONFIG_MDIO_GPIO is not set
616CONFIG_NET_ETHERNET=y
617CONFIG_MII=y
618# CONFIG_AX88796 is not set
619# CONFIG_STNIC is not set
620CONFIG_SMC91X=y
621# CONFIG_ENC28J60 is not set
622# CONFIG_ETHOC is not set
623# CONFIG_SMC911X is not set
624# CONFIG_SMSC911X is not set
625# CONFIG_DNET is not set
626# CONFIG_IBM_NEW_EMAC_ZMII is not set
627# CONFIG_IBM_NEW_EMAC_RGMII is not set
628# CONFIG_IBM_NEW_EMAC_TAH is not set
629# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
630# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
631# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
632# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
633# CONFIG_B44 is not set
634# CONFIG_NETDEV_1000 is not set
635# CONFIG_NETDEV_10000 is not set
636
637#
638# Wireless LAN
639#
640# CONFIG_WLAN_PRE80211 is not set
641# CONFIG_WLAN_80211 is not set
642
643#
644# Enable WiMAX (Networking options) to see the WiMAX drivers
645#
646
647#
648# USB Network Adapters
649#
650# CONFIG_USB_CATC is not set
651# CONFIG_USB_KAWETH is not set
652# CONFIG_USB_PEGASUS is not set
653# CONFIG_USB_RTL8150 is not set
654# CONFIG_USB_USBNET is not set
655# CONFIG_WAN is not set
656# CONFIG_PPP is not set
657# CONFIG_SLIP is not set
658# CONFIG_NETCONSOLE is not set
659# CONFIG_NETPOLL is not set
660# CONFIG_NET_POLL_CONTROLLER is not set
661# CONFIG_ISDN is not set
662# CONFIG_PHONE is not set
663
664#
665# Input device support
666#
667CONFIG_INPUT=y
668# CONFIG_INPUT_FF_MEMLESS is not set
669# CONFIG_INPUT_POLLDEV is not set
670
671#
672# Userland interfaces
673#
674# CONFIG_INPUT_MOUSEDEV is not set
675# CONFIG_INPUT_JOYDEV is not set
676CONFIG_INPUT_EVDEV=y
677# CONFIG_INPUT_EVBUG is not set
678
679#
680# Input Device Drivers
681#
682CONFIG_INPUT_KEYBOARD=y
683# CONFIG_KEYBOARD_ATKBD is not set
684# CONFIG_KEYBOARD_SUNKBD is not set
685# CONFIG_KEYBOARD_LKKBD is not set
686# CONFIG_KEYBOARD_XTKBD is not set
687# CONFIG_KEYBOARD_NEWTON is not set
688# CONFIG_KEYBOARD_STOWAWAY is not set
689# CONFIG_KEYBOARD_GPIO is not set
690CONFIG_KEYBOARD_SH_KEYSC=y
691# CONFIG_INPUT_MOUSE is not set
692# CONFIG_INPUT_JOYSTICK is not set
693# CONFIG_INPUT_TABLET is not set
694# CONFIG_INPUT_TOUCHSCREEN is not set
695# CONFIG_INPUT_MISC is not set
696
697#
698# Hardware I/O ports
699#
700# CONFIG_SERIO is not set
701# CONFIG_GAMEPORT is not set
702
703#
704# Character devices
705#
706CONFIG_VT=y
707CONFIG_CONSOLE_TRANSLATIONS=y
708CONFIG_VT_CONSOLE=y
709CONFIG_HW_CONSOLE=y
710CONFIG_VT_HW_CONSOLE_BINDING=y
711CONFIG_DEVKMEM=y
712# CONFIG_SERIAL_NONSTANDARD is not set
713
714#
715# Serial drivers
716#
717# CONFIG_SERIAL_8250 is not set
718
719#
720# Non-8250 serial port support
721#
722# CONFIG_SERIAL_MAX3100 is not set
723CONFIG_SERIAL_SH_SCI=y
724CONFIG_SERIAL_SH_SCI_NR_UARTS=6
725CONFIG_SERIAL_SH_SCI_CONSOLE=y
726CONFIG_SERIAL_CORE=y
727CONFIG_SERIAL_CORE_CONSOLE=y
728CONFIG_UNIX98_PTYS=y
729# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
730CONFIG_LEGACY_PTYS=y
731CONFIG_LEGACY_PTY_COUNT=256
732# CONFIG_IPMI_HANDLER is not set
733CONFIG_HW_RANDOM=y
734# CONFIG_HW_RANDOM_TIMERIOMEM is not set
735# CONFIG_R3964 is not set
736# CONFIG_RAW_DRIVER is not set
737# CONFIG_TCG_TPM is not set
738CONFIG_I2C=y
739CONFIG_I2C_BOARDINFO=y
740CONFIG_I2C_CHARDEV=y
741CONFIG_I2C_HELPER_AUTO=y
742
743#
744# I2C Hardware Bus support
745#
746
747#
748# I2C system bus drivers (mostly embedded / system-on-chip)
749#
750# CONFIG_I2C_GPIO is not set
751# CONFIG_I2C_OCORES is not set
752CONFIG_I2C_SH_MOBILE=y
753# CONFIG_I2C_SIMTEC is not set
754
755#
756# External I2C/SMBus adapter drivers
757#
758# CONFIG_I2C_PARPORT_LIGHT is not set
759# CONFIG_I2C_TAOS_EVM is not set
760# CONFIG_I2C_TINY_USB is not set
761
762#
763# Other I2C/SMBus bus drivers
764#
765# CONFIG_I2C_PCA_PLATFORM is not set
766# CONFIG_I2C_STUB is not set
767
768#
769# Miscellaneous I2C Chip support
770#
771# CONFIG_DS1682 is not set
772# CONFIG_SENSORS_PCF8574 is not set
773# CONFIG_PCF8575 is not set
774# CONFIG_SENSORS_PCA9539 is not set
775# CONFIG_SENSORS_MAX6875 is not set
776# CONFIG_SENSORS_TSL2550 is not set
777# CONFIG_I2C_DEBUG_CORE is not set
778# CONFIG_I2C_DEBUG_ALGO is not set
779# CONFIG_I2C_DEBUG_BUS is not set
780# CONFIG_I2C_DEBUG_CHIP is not set
781CONFIG_SPI=y
782CONFIG_SPI_MASTER=y
783
784#
785# SPI Master Controller Drivers
786#
787CONFIG_SPI_BITBANG=y
788# CONFIG_SPI_GPIO is not set
789# CONFIG_SPI_SH_SCI is not set
790
791#
792# SPI Protocol Masters
793#
794# CONFIG_SPI_SPIDEV is not set
795# CONFIG_SPI_TLE62X0 is not set
796CONFIG_ARCH_REQUIRE_GPIOLIB=y
797CONFIG_GPIOLIB=y
798# CONFIG_GPIO_SYSFS is not set
799
800#
801# Memory mapped GPIO expanders:
802#
803
804#
805# I2C GPIO expanders:
806#
807# CONFIG_GPIO_MAX732X is not set
808# CONFIG_GPIO_PCA953X is not set
809# CONFIG_GPIO_PCF857X is not set
810
811#
812# PCI GPIO expanders:
813#
814
815#
816# SPI GPIO expanders:
817#
818# CONFIG_GPIO_MAX7301 is not set
819# CONFIG_GPIO_MCP23S08 is not set
820# CONFIG_W1 is not set
821# CONFIG_POWER_SUPPLY is not set
822# CONFIG_HWMON is not set
823# CONFIG_THERMAL is not set
824# CONFIG_THERMAL_HWMON is not set
825# CONFIG_WATCHDOG is not set
826CONFIG_SSB_POSSIBLE=y
827
828#
829# Sonics Silicon Backplane
830#
831# CONFIG_SSB is not set
832
833#
834# Multifunction device drivers
835#
836# CONFIG_MFD_CORE is not set
837# CONFIG_MFD_SM501 is not set
838# CONFIG_HTC_PASIC3 is not set
839# CONFIG_TPS65010 is not set
840# CONFIG_TWL4030_CORE is not set
841# CONFIG_MFD_TMIO is not set
842# CONFIG_PMIC_DA903X is not set
843# CONFIG_MFD_WM8400 is not set
844# CONFIG_MFD_WM8350_I2C is not set
845# CONFIG_MFD_PCF50633 is not set
846# CONFIG_REGULATOR is not set
847
848#
849# Multimedia devices
850#
851
852#
853# Multimedia core support
854#
855CONFIG_VIDEO_DEV=y
856CONFIG_VIDEO_V4L2_COMMON=y
857# CONFIG_VIDEO_ALLOW_V4L1 is not set
858CONFIG_VIDEO_V4L1_COMPAT=y
859# CONFIG_DVB_CORE is not set
860CONFIG_VIDEO_MEDIA=y
861
862#
863# Multimedia drivers
864#
865# CONFIG_MEDIA_ATTACH is not set
866CONFIG_MEDIA_TUNER=y
867# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
868CONFIG_MEDIA_TUNER_SIMPLE=y
869CONFIG_MEDIA_TUNER_TDA8290=y
870CONFIG_MEDIA_TUNER_TDA9887=y
871CONFIG_MEDIA_TUNER_TEA5761=y
872CONFIG_MEDIA_TUNER_TEA5767=y
873CONFIG_MEDIA_TUNER_MT20XX=y
874CONFIG_MEDIA_TUNER_XC2028=y
875CONFIG_MEDIA_TUNER_XC5000=y
876CONFIG_MEDIA_TUNER_MC44S803=y
877CONFIG_VIDEO_V4L2=y
878CONFIG_VIDEOBUF_GEN=y
879CONFIG_VIDEOBUF_DMA_CONTIG=y
880CONFIG_VIDEO_CAPTURE_DRIVERS=y
881# CONFIG_VIDEO_ADV_DEBUG is not set
882# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
883CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
884# CONFIG_VIDEO_VIVI is not set
885# CONFIG_VIDEO_SAA5246A is not set
886# CONFIG_VIDEO_SAA5249 is not set
887CONFIG_SOC_CAMERA=y
888# CONFIG_SOC_CAMERA_MT9M001 is not set
889# CONFIG_SOC_CAMERA_MT9M111 is not set
890# CONFIG_SOC_CAMERA_MT9T031 is not set
891# CONFIG_SOC_CAMERA_MT9V022 is not set
892# CONFIG_SOC_CAMERA_TW9910 is not set
893# CONFIG_SOC_CAMERA_PLATFORM is not set
894CONFIG_SOC_CAMERA_OV772X=y
895CONFIG_VIDEO_SH_MOBILE_CEU=y
896CONFIG_V4L_USB_DRIVERS=y
897# CONFIG_USB_VIDEO_CLASS is not set
898CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
899CONFIG_USB_GSPCA=m
900# CONFIG_USB_M5602 is not set
901# CONFIG_USB_STV06XX is not set
902# CONFIG_USB_GSPCA_CONEX is not set
903# CONFIG_USB_GSPCA_ETOMS is not set
904# CONFIG_USB_GSPCA_FINEPIX is not set
905# CONFIG_USB_GSPCA_MARS is not set
906# CONFIG_USB_GSPCA_MR97310A is not set
907# CONFIG_USB_GSPCA_OV519 is not set
908# CONFIG_USB_GSPCA_OV534 is not set
909# CONFIG_USB_GSPCA_PAC207 is not set
910# CONFIG_USB_GSPCA_PAC7311 is not set
911# CONFIG_USB_GSPCA_SONIXB is not set
912# CONFIG_USB_GSPCA_SONIXJ is not set
913# CONFIG_USB_GSPCA_SPCA500 is not set
914# CONFIG_USB_GSPCA_SPCA501 is not set
915# CONFIG_USB_GSPCA_SPCA505 is not set
916# CONFIG_USB_GSPCA_SPCA506 is not set
917# CONFIG_USB_GSPCA_SPCA508 is not set
918# CONFIG_USB_GSPCA_SPCA561 is not set
919# CONFIG_USB_GSPCA_SQ905 is not set
920# CONFIG_USB_GSPCA_SQ905C is not set
921# CONFIG_USB_GSPCA_STK014 is not set
922# CONFIG_USB_GSPCA_SUNPLUS is not set
923# CONFIG_USB_GSPCA_T613 is not set
924# CONFIG_USB_GSPCA_TV8532 is not set
925# CONFIG_USB_GSPCA_VC032X is not set
926# CONFIG_USB_GSPCA_ZC3XX is not set
927# CONFIG_VIDEO_PVRUSB2 is not set
928# CONFIG_VIDEO_HDPVR is not set
929# CONFIG_VIDEO_EM28XX is not set
930# CONFIG_VIDEO_CX231XX is not set
931# CONFIG_VIDEO_USBVISION is not set
932# CONFIG_USB_ET61X251 is not set
933# CONFIG_USB_SN9C102 is not set
934# CONFIG_USB_ZC0301 is not set
935CONFIG_USB_PWC_INPUT_EVDEV=y
936# CONFIG_USB_ZR364XX is not set
937# CONFIG_USB_STKWEBCAM is not set
938# CONFIG_USB_S2255 is not set
939# CONFIG_RADIO_ADAPTERS is not set
940# CONFIG_DAB is not set
941
942#
943# Graphics support
944#
945# CONFIG_VGASTATE is not set
946# CONFIG_VIDEO_OUTPUT_CONTROL is not set
947CONFIG_FB=y
948# CONFIG_FIRMWARE_EDID is not set
949# CONFIG_FB_DDC is not set
950# CONFIG_FB_BOOT_VESA_SUPPORT is not set
951# CONFIG_FB_CFB_FILLRECT is not set
952# CONFIG_FB_CFB_COPYAREA is not set
953# CONFIG_FB_CFB_IMAGEBLIT is not set
954# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
955CONFIG_FB_SYS_FILLRECT=y
956CONFIG_FB_SYS_COPYAREA=y
957CONFIG_FB_SYS_IMAGEBLIT=y
958# CONFIG_FB_FOREIGN_ENDIAN is not set
959CONFIG_FB_SYS_FOPS=y
960CONFIG_FB_DEFERRED_IO=y
961# CONFIG_FB_SVGALIB is not set
962# CONFIG_FB_MACMODES is not set
963# CONFIG_FB_BACKLIGHT is not set
964# CONFIG_FB_MODE_HELPERS is not set
965# CONFIG_FB_TILEBLITTING is not set
966
967#
968# Frame buffer hardware drivers
969#
970# CONFIG_FB_S1D13XXX is not set
971CONFIG_FB_SH_MOBILE_LCDC=y
972# CONFIG_FB_VIRTUAL is not set
973# CONFIG_FB_METRONOME is not set
974# CONFIG_FB_MB862XX is not set
975# CONFIG_FB_BROADSHEET is not set
976# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
977
978#
979# Display device support
980#
981# CONFIG_DISPLAY_SUPPORT is not set
982
983#
984# Console display driver support
985#
986CONFIG_DUMMY_CONSOLE=y
987CONFIG_FRAMEBUFFER_CONSOLE=y
988# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
989# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
990# CONFIG_FONTS is not set
991CONFIG_FONT_8x8=y
992CONFIG_FONT_8x16=y
993CONFIG_LOGO=y
994# CONFIG_LOGO_LINUX_MONO is not set
995# CONFIG_LOGO_LINUX_VGA16 is not set
996# CONFIG_LOGO_LINUX_CLUT224 is not set
997# CONFIG_LOGO_SUPERH_MONO is not set
998# CONFIG_LOGO_SUPERH_VGA16 is not set
999CONFIG_LOGO_SUPERH_CLUT224=y
1000# CONFIG_SOUND is not set
1001CONFIG_HID_SUPPORT=y
1002CONFIG_HID=y
1003# CONFIG_HID_DEBUG is not set
1004# CONFIG_HIDRAW is not set
1005
1006#
1007# USB Input Devices
1008#
1009CONFIG_USB_HID=y
1010# CONFIG_HID_PID is not set
1011# CONFIG_USB_HIDDEV is not set
1012
1013#
1014# Special HID drivers
1015#
1016# CONFIG_HID_A4TECH is not set
1017# CONFIG_HID_APPLE is not set
1018# CONFIG_HID_BELKIN is not set
1019# CONFIG_HID_CHERRY is not set
1020# CONFIG_HID_CHICONY is not set
1021# CONFIG_HID_CYPRESS is not set
1022# CONFIG_DRAGONRISE_FF is not set
1023# CONFIG_HID_EZKEY is not set
1024# CONFIG_HID_KYE is not set
1025# CONFIG_HID_GYRATION is not set
1026# CONFIG_HID_KENSINGTON is not set
1027# CONFIG_HID_LOGITECH is not set
1028# CONFIG_HID_MICROSOFT is not set
1029# CONFIG_HID_MONTEREY is not set
1030# CONFIG_HID_NTRIG is not set
1031# CONFIG_HID_PANTHERLORD is not set
1032# CONFIG_HID_PETALYNX is not set
1033# CONFIG_HID_SAMSUNG is not set
1034# CONFIG_HID_SONY is not set
1035# CONFIG_HID_SUNPLUS is not set
1036# CONFIG_GREENASIA_FF is not set
1037# CONFIG_HID_TOPSEED is not set
1038# CONFIG_THRUSTMASTER_FF is not set
1039# CONFIG_ZEROPLUS_FF is not set
1040CONFIG_USB_SUPPORT=y
1041CONFIG_USB_ARCH_HAS_HCD=y
1042# CONFIG_USB_ARCH_HAS_OHCI is not set
1043# CONFIG_USB_ARCH_HAS_EHCI is not set
1044CONFIG_USB=y
1045# CONFIG_USB_DEBUG is not set
1046# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
1047
1048#
1049# Miscellaneous USB options
1050#
1051# CONFIG_USB_DEVICEFS is not set
1052CONFIG_USB_DEVICE_CLASS=y
1053# CONFIG_USB_DYNAMIC_MINORS is not set
1054# CONFIG_USB_OTG is not set
1055# CONFIG_USB_OTG_WHITELIST is not set
1056# CONFIG_USB_OTG_BLACKLIST_HUB is not set
1057CONFIG_USB_MON=y
1058# CONFIG_USB_WUSB is not set
1059# CONFIG_USB_WUSB_CBAF is not set
1060
1061#
1062# USB Host Controller Drivers
1063#
1064# CONFIG_USB_C67X00_HCD is not set
1065# CONFIG_USB_OXU210HP_HCD is not set
1066# CONFIG_USB_ISP116X_HCD is not set
1067# CONFIG_USB_ISP1760_HCD is not set
1068# CONFIG_USB_SL811_HCD is not set
1069CONFIG_USB_R8A66597_HCD=y
1070# CONFIG_USB_HWA_HCD is not set
1071
1072#
1073# USB Device Class drivers
1074#
1075# CONFIG_USB_ACM is not set
1076# CONFIG_USB_PRINTER is not set
1077# CONFIG_USB_WDM is not set
1078# CONFIG_USB_TMC is not set
1079
1080#
1081# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
1082#
1083
1084#
1085# also be needed; see USB_STORAGE Help for more info
1086#
1087CONFIG_USB_STORAGE=y
1088# CONFIG_USB_STORAGE_DEBUG is not set
1089# CONFIG_USB_STORAGE_DATAFAB is not set
1090# CONFIG_USB_STORAGE_FREECOM is not set
1091# CONFIG_USB_STORAGE_ISD200 is not set
1092# CONFIG_USB_STORAGE_USBAT is not set
1093# CONFIG_USB_STORAGE_SDDR09 is not set
1094# CONFIG_USB_STORAGE_SDDR55 is not set
1095# CONFIG_USB_STORAGE_JUMPSHOT is not set
1096# CONFIG_USB_STORAGE_ALAUDA is not set
1097# CONFIG_USB_STORAGE_ONETOUCH is not set
1098# CONFIG_USB_STORAGE_KARMA is not set
1099# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1100# CONFIG_USB_LIBUSUAL is not set
1101
1102#
1103# USB Imaging devices
1104#
1105# CONFIG_USB_MDC800 is not set
1106# CONFIG_USB_MICROTEK is not set
1107
1108#
1109# USB port drivers
1110#
1111# CONFIG_USB_SERIAL is not set
1112
1113#
1114# USB Miscellaneous drivers
1115#
1116# CONFIG_USB_EMI62 is not set
1117# CONFIG_USB_EMI26 is not set
1118# CONFIG_USB_ADUTUX is not set
1119# CONFIG_USB_SEVSEG is not set
1120# CONFIG_USB_RIO500 is not set
1121# CONFIG_USB_LEGOTOWER is not set
1122# CONFIG_USB_LCD is not set
1123# CONFIG_USB_BERRY_CHARGE is not set
1124# CONFIG_USB_LED is not set
1125# CONFIG_USB_CYPRESS_CY7C63 is not set
1126# CONFIG_USB_CYTHERM is not set
1127# CONFIG_USB_IDMOUSE is not set
1128# CONFIG_USB_FTDI_ELAN is not set
1129# CONFIG_USB_APPLEDISPLAY is not set
1130# CONFIG_USB_LD is not set
1131# CONFIG_USB_TRANCEVIBRATOR is not set
1132# CONFIG_USB_IOWARRIOR is not set
1133# CONFIG_USB_ISIGHTFW is not set
1134# CONFIG_USB_VST is not set
1135# CONFIG_USB_GADGET is not set
1136
1137#
1138# OTG and related infrastructure
1139#
1140# CONFIG_USB_GPIO_VBUS is not set
1141# CONFIG_NOP_USB_XCEIV is not set
1142CONFIG_MMC=y
1143# CONFIG_MMC_DEBUG is not set
1144# CONFIG_MMC_UNSAFE_RESUME is not set
1145
1146#
1147# MMC/SD/SDIO Card Drivers
1148#
1149CONFIG_MMC_BLOCK=y
1150CONFIG_MMC_BLOCK_BOUNCE=y
1151# CONFIG_SDIO_UART is not set
1152# CONFIG_MMC_TEST is not set
1153
1154#
1155# MMC/SD/SDIO Host Controller Drivers
1156#
1157# CONFIG_MMC_SDHCI is not set
1158CONFIG_MMC_SPI=y
1159# CONFIG_MEMSTICK is not set
1160# CONFIG_NEW_LEDS is not set
1161# CONFIG_ACCESSIBILITY is not set
1162CONFIG_RTC_LIB=y
1163CONFIG_RTC_CLASS=y
1164CONFIG_RTC_HCTOSYS=y
1165CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1166# CONFIG_RTC_DEBUG is not set
1167
1168#
1169# RTC interfaces
1170#
1171CONFIG_RTC_INTF_SYSFS=y
1172CONFIG_RTC_INTF_PROC=y
1173CONFIG_RTC_INTF_DEV=y
1174# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1175# CONFIG_RTC_DRV_TEST is not set
1176
1177#
1178# I2C RTC drivers
1179#
1180# CONFIG_RTC_DRV_DS1307 is not set
1181# CONFIG_RTC_DRV_DS1374 is not set
1182# CONFIG_RTC_DRV_DS1672 is not set
1183# CONFIG_RTC_DRV_MAX6900 is not set
1184# CONFIG_RTC_DRV_RS5C372 is not set
1185# CONFIG_RTC_DRV_ISL1208 is not set
1186# CONFIG_RTC_DRV_X1205 is not set
1187CONFIG_RTC_DRV_PCF8563=y
1188# CONFIG_RTC_DRV_PCF8583 is not set
1189# CONFIG_RTC_DRV_M41T80 is not set
1190# CONFIG_RTC_DRV_S35390A is not set
1191# CONFIG_RTC_DRV_FM3130 is not set
1192# CONFIG_RTC_DRV_RX8581 is not set
1193
1194#
1195# SPI RTC drivers
1196#
1197# CONFIG_RTC_DRV_M41T94 is not set
1198# CONFIG_RTC_DRV_DS1305 is not set
1199# CONFIG_RTC_DRV_DS1390 is not set
1200# CONFIG_RTC_DRV_MAX6902 is not set
1201# CONFIG_RTC_DRV_R9701 is not set
1202# CONFIG_RTC_DRV_RS5C348 is not set
1203# CONFIG_RTC_DRV_DS3234 is not set
1204
1205#
1206# Platform RTC drivers
1207#
1208# CONFIG_RTC_DRV_DS1286 is not set
1209# CONFIG_RTC_DRV_DS1511 is not set
1210# CONFIG_RTC_DRV_DS1553 is not set
1211# CONFIG_RTC_DRV_DS1742 is not set
1212# CONFIG_RTC_DRV_STK17TA8 is not set
1213# CONFIG_RTC_DRV_M48T86 is not set
1214# CONFIG_RTC_DRV_M48T35 is not set
1215# CONFIG_RTC_DRV_M48T59 is not set
1216# CONFIG_RTC_DRV_BQ4802 is not set
1217# CONFIG_RTC_DRV_V3020 is not set
1218
1219#
1220# on-CPU RTC drivers
1221#
1222# CONFIG_RTC_DRV_SH is not set
1223# CONFIG_RTC_DRV_GENERIC is not set
1224# CONFIG_DMADEVICES is not set
1225# CONFIG_AUXDISPLAY is not set
1226CONFIG_UIO=y
1227# CONFIG_UIO_PDRV is not set
1228CONFIG_UIO_PDRV_GENIRQ=y
1229# CONFIG_UIO_SMX is not set
1230# CONFIG_UIO_SERCOS3 is not set
1231# CONFIG_STAGING is not set
1232
1233#
1234# File systems
1235#
1236CONFIG_EXT2_FS=y
1237CONFIG_EXT2_FS_XATTR=y
1238CONFIG_EXT2_FS_POSIX_ACL=y
1239CONFIG_EXT2_FS_SECURITY=y
1240# CONFIG_EXT2_FS_XIP is not set
1241CONFIG_EXT3_FS=y
1242# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1243CONFIG_EXT3_FS_XATTR=y
1244CONFIG_EXT3_FS_POSIX_ACL=y
1245CONFIG_EXT3_FS_SECURITY=y
1246# CONFIG_EXT4_FS is not set
1247CONFIG_JBD=y
1248CONFIG_FS_MBCACHE=y
1249# CONFIG_REISERFS_FS is not set
1250# CONFIG_JFS_FS is not set
1251CONFIG_FS_POSIX_ACL=y
1252CONFIG_FILE_LOCKING=y
1253# CONFIG_XFS_FS is not set
1254# CONFIG_OCFS2_FS is not set
1255# CONFIG_BTRFS_FS is not set
1256CONFIG_DNOTIFY=y
1257CONFIG_INOTIFY=y
1258CONFIG_INOTIFY_USER=y
1259# CONFIG_QUOTA is not set
1260# CONFIG_AUTOFS_FS is not set
1261# CONFIG_AUTOFS4_FS is not set
1262# CONFIG_FUSE_FS is not set
1263
1264#
1265# Caches
1266#
1267# CONFIG_FSCACHE is not set
1268
1269#
1270# CD-ROM/DVD Filesystems
1271#
1272# CONFIG_ISO9660_FS is not set
1273# CONFIG_UDF_FS is not set
1274
1275#
1276# DOS/FAT/NT Filesystems
1277#
1278CONFIG_FAT_FS=y
1279# CONFIG_MSDOS_FS is not set
1280CONFIG_VFAT_FS=y
1281CONFIG_FAT_DEFAULT_CODEPAGE=437
1282CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1283# CONFIG_NTFS_FS is not set
1284
1285#
1286# Pseudo filesystems
1287#
1288CONFIG_PROC_FS=y
1289CONFIG_PROC_KCORE=y
1290CONFIG_PROC_SYSCTL=y
1291CONFIG_PROC_PAGE_MONITOR=y
1292CONFIG_SYSFS=y
1293CONFIG_TMPFS=y
1294# CONFIG_TMPFS_POSIX_ACL is not set
1295# CONFIG_HUGETLBFS is not set
1296# CONFIG_HUGETLB_PAGE is not set
1297# CONFIG_CONFIGFS_FS is not set
1298CONFIG_MISC_FILESYSTEMS=y
1299# CONFIG_ADFS_FS is not set
1300# CONFIG_AFFS_FS is not set
1301# CONFIG_HFS_FS is not set
1302# CONFIG_HFSPLUS_FS is not set
1303# CONFIG_BEFS_FS is not set
1304# CONFIG_BFS_FS is not set
1305# CONFIG_EFS_FS is not set
1306# CONFIG_JFFS2_FS is not set
1307# CONFIG_UBIFS_FS is not set
1308# CONFIG_CRAMFS is not set
1309# CONFIG_SQUASHFS is not set
1310# CONFIG_VXFS_FS is not set
1311# CONFIG_MINIX_FS is not set
1312# CONFIG_OMFS_FS is not set
1313# CONFIG_HPFS_FS is not set
1314# CONFIG_QNX4FS_FS is not set
1315# CONFIG_ROMFS_FS is not set
1316# CONFIG_SYSV_FS is not set
1317# CONFIG_UFS_FS is not set
1318# CONFIG_NILFS2_FS is not set
1319CONFIG_NETWORK_FILESYSTEMS=y
1320CONFIG_NFS_FS=y
1321CONFIG_NFS_V3=y
1322# CONFIG_NFS_V3_ACL is not set
1323# CONFIG_NFS_V4 is not set
1324CONFIG_ROOT_NFS=y
1325CONFIG_NFSD=y
1326CONFIG_NFSD_V3=y
1327# CONFIG_NFSD_V3_ACL is not set
1328# CONFIG_NFSD_V4 is not set
1329CONFIG_LOCKD=y
1330CONFIG_LOCKD_V4=y
1331CONFIG_EXPORTFS=y
1332CONFIG_NFS_COMMON=y
1333CONFIG_SUNRPC=y
1334# CONFIG_RPCSEC_GSS_KRB5 is not set
1335# CONFIG_RPCSEC_GSS_SPKM3 is not set
1336# CONFIG_SMB_FS is not set
1337# CONFIG_CIFS is not set
1338# CONFIG_NCP_FS is not set
1339# CONFIG_CODA_FS is not set
1340# CONFIG_AFS_FS is not set
1341
1342#
1343# Partition Types
1344#
1345# CONFIG_PARTITION_ADVANCED is not set
1346CONFIG_MSDOS_PARTITION=y
1347CONFIG_NLS=y
1348CONFIG_NLS_DEFAULT="iso8859-1"
1349CONFIG_NLS_CODEPAGE_437=y
1350# CONFIG_NLS_CODEPAGE_737 is not set
1351# CONFIG_NLS_CODEPAGE_775 is not set
1352# CONFIG_NLS_CODEPAGE_850 is not set
1353# CONFIG_NLS_CODEPAGE_852 is not set
1354# CONFIG_NLS_CODEPAGE_855 is not set
1355# CONFIG_NLS_CODEPAGE_857 is not set
1356# CONFIG_NLS_CODEPAGE_860 is not set
1357# CONFIG_NLS_CODEPAGE_861 is not set
1358# CONFIG_NLS_CODEPAGE_862 is not set
1359# CONFIG_NLS_CODEPAGE_863 is not set
1360# CONFIG_NLS_CODEPAGE_864 is not set
1361# CONFIG_NLS_CODEPAGE_865 is not set
1362# CONFIG_NLS_CODEPAGE_866 is not set
1363# CONFIG_NLS_CODEPAGE_869 is not set
1364# CONFIG_NLS_CODEPAGE_936 is not set
1365# CONFIG_NLS_CODEPAGE_950 is not set
1366CONFIG_NLS_CODEPAGE_932=y
1367# CONFIG_NLS_CODEPAGE_949 is not set
1368# CONFIG_NLS_CODEPAGE_874 is not set
1369# CONFIG_NLS_ISO8859_8 is not set
1370# CONFIG_NLS_CODEPAGE_1250 is not set
1371# CONFIG_NLS_CODEPAGE_1251 is not set
1372# CONFIG_NLS_ASCII is not set
1373CONFIG_NLS_ISO8859_1=y
1374# CONFIG_NLS_ISO8859_2 is not set
1375# CONFIG_NLS_ISO8859_3 is not set
1376# CONFIG_NLS_ISO8859_4 is not set
1377# CONFIG_NLS_ISO8859_5 is not set
1378# CONFIG_NLS_ISO8859_6 is not set
1379# CONFIG_NLS_ISO8859_7 is not set
1380# CONFIG_NLS_ISO8859_9 is not set
1381# CONFIG_NLS_ISO8859_13 is not set
1382# CONFIG_NLS_ISO8859_14 is not set
1383# CONFIG_NLS_ISO8859_15 is not set
1384# CONFIG_NLS_KOI8_R is not set
1385# CONFIG_NLS_KOI8_U is not set
1386# CONFIG_NLS_UTF8 is not set
1387# CONFIG_DLM is not set
1388
1389#
1390# Kernel hacking
1391#
1392CONFIG_TRACE_IRQFLAGS_SUPPORT=y
1393# CONFIG_PRINTK_TIME is not set
1394CONFIG_ENABLE_WARN_DEPRECATED=y
1395# CONFIG_ENABLE_MUST_CHECK is not set
1396CONFIG_FRAME_WARN=1024
1397# CONFIG_MAGIC_SYSRQ is not set
1398# CONFIG_UNUSED_SYMBOLS is not set
1399# CONFIG_DEBUG_FS is not set
1400# CONFIG_HEADERS_CHECK is not set
1401# CONFIG_DEBUG_KERNEL is not set
1402# CONFIG_DEBUG_BUGVERBOSE is not set
1403# CONFIG_DEBUG_MEMORY_INIT is not set
1404# CONFIG_RCU_CPU_STALL_DETECTOR is not set
1405# CONFIG_LATENCYTOP is not set
1406CONFIG_SYSCTL_SYSCALL_CHECK=y
1407CONFIG_HAVE_FUNCTION_TRACER=y
1408CONFIG_HAVE_DYNAMIC_FTRACE=y
1409CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1410CONFIG_TRACING_SUPPORT=y
1411
1412#
1413# Tracers
1414#
1415# CONFIG_FUNCTION_TRACER is not set
1416# CONFIG_IRQSOFF_TRACER is not set
1417# CONFIG_PREEMPT_TRACER is not set
1418# CONFIG_SCHED_TRACER is not set
1419# CONFIG_CONTEXT_SWITCH_TRACER is not set
1420# CONFIG_EVENT_TRACER is not set
1421# CONFIG_BOOT_TRACER is not set
1422# CONFIG_TRACE_BRANCH_PROFILING is not set
1423# CONFIG_STACK_TRACER is not set
1424# CONFIG_KMEMTRACE is not set
1425# CONFIG_WORKQUEUE_TRACER is not set
1426# CONFIG_BLK_DEV_IO_TRACE is not set
1427# CONFIG_DMA_API_DEBUG is not set
1428# CONFIG_SAMPLES is not set
1429CONFIG_HAVE_ARCH_KGDB=y
1430# CONFIG_SH_STANDARD_BIOS is not set
1431# CONFIG_EARLY_SCIF_CONSOLE is not set
1432
1433#
1434# Security options
1435#
1436# CONFIG_KEYS is not set
1437# CONFIG_SECURITY is not set
1438# CONFIG_SECURITYFS is not set
1439# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1440CONFIG_CRYPTO=y
1441
1442#
1443# Crypto core or helper
1444#
1445# CONFIG_CRYPTO_FIPS is not set
1446CONFIG_CRYPTO_ALGAPI=y
1447CONFIG_CRYPTO_ALGAPI2=y
1448CONFIG_CRYPTO_AEAD2=y
1449CONFIG_CRYPTO_BLKCIPHER=y
1450CONFIG_CRYPTO_BLKCIPHER2=y
1451CONFIG_CRYPTO_HASH2=y
1452CONFIG_CRYPTO_RNG2=y
1453CONFIG_CRYPTO_PCOMP=y
1454CONFIG_CRYPTO_MANAGER=y
1455CONFIG_CRYPTO_MANAGER2=y
1456# CONFIG_CRYPTO_GF128MUL is not set
1457# CONFIG_CRYPTO_NULL is not set
1458CONFIG_CRYPTO_WORKQUEUE=y
1459# CONFIG_CRYPTO_CRYPTD is not set
1460# CONFIG_CRYPTO_AUTHENC is not set
1461# CONFIG_CRYPTO_TEST is not set
1462
1463#
1464# Authenticated Encryption with Associated Data
1465#
1466# CONFIG_CRYPTO_CCM is not set
1467# CONFIG_CRYPTO_GCM is not set
1468# CONFIG_CRYPTO_SEQIV is not set
1469
1470#
1471# Block modes
1472#
1473CONFIG_CRYPTO_CBC=y
1474# CONFIG_CRYPTO_CTR is not set
1475# CONFIG_CRYPTO_CTS is not set
1476# CONFIG_CRYPTO_ECB is not set
1477# CONFIG_CRYPTO_LRW is not set
1478# CONFIG_CRYPTO_PCBC is not set
1479# CONFIG_CRYPTO_XTS is not set
1480
1481#
1482# Hash modes
1483#
1484# CONFIG_CRYPTO_HMAC is not set
1485# CONFIG_CRYPTO_XCBC is not set
1486
1487#
1488# Digest
1489#
1490# CONFIG_CRYPTO_CRC32C is not set
1491# CONFIG_CRYPTO_MD4 is not set
1492# CONFIG_CRYPTO_MD5 is not set
1493# CONFIG_CRYPTO_MICHAEL_MIC is not set
1494# CONFIG_CRYPTO_RMD128 is not set
1495# CONFIG_CRYPTO_RMD160 is not set
1496# CONFIG_CRYPTO_RMD256 is not set
1497# CONFIG_CRYPTO_RMD320 is not set
1498# CONFIG_CRYPTO_SHA1 is not set
1499# CONFIG_CRYPTO_SHA256 is not set
1500# CONFIG_CRYPTO_SHA512 is not set
1501# CONFIG_CRYPTO_TGR192 is not set
1502# CONFIG_CRYPTO_WP512 is not set
1503
1504#
1505# Ciphers
1506#
1507# CONFIG_CRYPTO_AES is not set
1508# CONFIG_CRYPTO_ANUBIS is not set
1509# CONFIG_CRYPTO_ARC4 is not set
1510# CONFIG_CRYPTO_BLOWFISH is not set
1511# CONFIG_CRYPTO_CAMELLIA is not set
1512# CONFIG_CRYPTO_CAST5 is not set
1513# CONFIG_CRYPTO_CAST6 is not set
1514# CONFIG_CRYPTO_DES is not set
1515# CONFIG_CRYPTO_FCRYPT is not set
1516# CONFIG_CRYPTO_KHAZAD is not set
1517# CONFIG_CRYPTO_SALSA20 is not set
1518# CONFIG_CRYPTO_SEED is not set
1519# CONFIG_CRYPTO_SERPENT is not set
1520# CONFIG_CRYPTO_TEA is not set
1521# CONFIG_CRYPTO_TWOFISH is not set
1522
1523#
1524# Compression
1525#
1526# CONFIG_CRYPTO_DEFLATE is not set
1527# CONFIG_CRYPTO_ZLIB is not set
1528# CONFIG_CRYPTO_LZO is not set
1529
1530#
1531# Random Number Generation
1532#
1533# CONFIG_CRYPTO_ANSI_CPRNG is not set
1534CONFIG_CRYPTO_HW=y
1535# CONFIG_BINARY_PRINTF is not set
1536
1537#
1538# Library routines
1539#
1540CONFIG_BITREVERSE=y
1541CONFIG_GENERIC_FIND_LAST_BIT=y
1542# CONFIG_CRC_CCITT is not set
1543# CONFIG_CRC16 is not set
1544CONFIG_CRC_T10DIF=y
1545CONFIG_CRC_ITU_T=y
1546CONFIG_CRC32=y
1547CONFIG_CRC7=y
1548# CONFIG_LIBCRC32C is not set
1549CONFIG_HAS_IOMEM=y
1550CONFIG_HAS_IOPORT=y
1551CONFIG_HAS_DMA=y
1552CONFIG_NLATTR=y
diff --git a/arch/sh/configs/se7750_defconfig b/arch/sh/configs/se7750_defconfig
index ceef6d9138ee..ed1a1230f636 100644
--- a/arch/sh/configs/se7750_defconfig
+++ b/arch/sh/configs/se7750_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:57:31 2009 4# Mon Apr 27 13:06:02 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -70,6 +71,7 @@ CONFIG_UID16=y
70# CONFIG_SYSCTL_SYSCALL is not set 71# CONFIG_SYSCTL_SYSCALL is not set
71CONFIG_KALLSYMS=y 72CONFIG_KALLSYMS=y
72# CONFIG_KALLSYMS_EXTRA_PASS is not set 73# CONFIG_KALLSYMS_EXTRA_PASS is not set
74# CONFIG_STRIP_ASM_SYMS is not set
73# CONFIG_HOTPLUG is not set 75# CONFIG_HOTPLUG is not set
74CONFIG_PRINTK=y 76CONFIG_PRINTK=y
75CONFIG_BUG=y 77CONFIG_BUG=y
@@ -88,6 +90,7 @@ CONFIG_SLAB=y
88# CONFIG_SLUB is not set 90# CONFIG_SLUB is not set
89# CONFIG_SLOB is not set 91# CONFIG_SLOB is not set
90# CONFIG_PROFILING is not set 92# CONFIG_PROFILING is not set
93# CONFIG_MARKERS is not set
91CONFIG_HAVE_OPROFILE=y 94CONFIG_HAVE_OPROFILE=y
92# CONFIG_KPROBES is not set 95# CONFIG_KPROBES is not set
93CONFIG_HAVE_IOREMAP_PROT=y 96CONFIG_HAVE_IOREMAP_PROT=y
@@ -95,6 +98,8 @@ CONFIG_HAVE_KPROBES=y
95CONFIG_HAVE_KRETPROBES=y 98CONFIG_HAVE_KRETPROBES=y
96CONFIG_HAVE_ARCH_TRACEHOOK=y 99CONFIG_HAVE_ARCH_TRACEHOOK=y
97CONFIG_HAVE_CLK=y 100CONFIG_HAVE_CLK=y
101CONFIG_HAVE_DMA_API_DEBUG=y
102# CONFIG_SLOW_WORK is not set
98CONFIG_HAVE_GENERIC_DMA_COHERENT=y 103CONFIG_HAVE_GENERIC_DMA_COHERENT=y
99CONFIG_SLABINFO=y 104CONFIG_SLABINFO=y
100CONFIG_RT_MUTEXES=y 105CONFIG_RT_MUTEXES=y
@@ -106,7 +111,6 @@ CONFIG_MODULES=y
106# CONFIG_MODULE_SRCVERSION_ALL is not set 111# CONFIG_MODULE_SRCVERSION_ALL is not set
107CONFIG_BLOCK=y 112CONFIG_BLOCK=y
108# CONFIG_LBD is not set 113# CONFIG_LBD is not set
109# CONFIG_BLK_DEV_IO_TRACE is not set
110# CONFIG_BLK_DEV_BSG is not set 114# CONFIG_BLK_DEV_BSG is not set
111# CONFIG_BLK_DEV_INTEGRITY is not set 115# CONFIG_BLK_DEV_INTEGRITY is not set
112 116
@@ -152,6 +156,7 @@ CONFIG_CPU_SUBTYPE_SH7750=y
152# CONFIG_CPU_SUBTYPE_SH7760 is not set 156# CONFIG_CPU_SUBTYPE_SH7760 is not set
153# CONFIG_CPU_SUBTYPE_SH4_202 is not set 157# CONFIG_CPU_SUBTYPE_SH4_202 is not set
154# CONFIG_CPU_SUBTYPE_SH7723 is not set 158# CONFIG_CPU_SUBTYPE_SH7723 is not set
159# CONFIG_CPU_SUBTYPE_SH7724 is not set
155# CONFIG_CPU_SUBTYPE_SH7763 is not set 160# CONFIG_CPU_SUBTYPE_SH7763 is not set
156# CONFIG_CPU_SUBTYPE_SH7770 is not set 161# CONFIG_CPU_SUBTYPE_SH7770 is not set
157# CONFIG_CPU_SUBTYPE_SH7780 is not set 162# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -161,8 +166,6 @@ CONFIG_CPU_SUBTYPE_SH7750=y
161# CONFIG_CPU_SUBTYPE_SH7343 is not set 166# CONFIG_CPU_SUBTYPE_SH7343 is not set
162# CONFIG_CPU_SUBTYPE_SH7722 is not set 167# CONFIG_CPU_SUBTYPE_SH7722 is not set
163# CONFIG_CPU_SUBTYPE_SH7366 is not set 168# CONFIG_CPU_SUBTYPE_SH7366 is not set
164# CONFIG_CPU_SUBTYPE_SH5_101 is not set
165# CONFIG_CPU_SUBTYPE_SH5_103 is not set
166 169
167# 170#
168# Memory management options 171# Memory management options
@@ -553,6 +556,7 @@ CONFIG_SCSI_WAIT_SCAN=m
553CONFIG_SCSI_LOWLEVEL=y 556CONFIG_SCSI_LOWLEVEL=y
554# CONFIG_ISCSI_TCP is not set 557# CONFIG_ISCSI_TCP is not set
555# CONFIG_LIBFC is not set 558# CONFIG_LIBFC is not set
559# CONFIG_LIBFCOE is not set
556# CONFIG_SCSI_DEBUG is not set 560# CONFIG_SCSI_DEBUG is not set
557# CONFIG_SCSI_DH is not set 561# CONFIG_SCSI_DH is not set
558# CONFIG_SCSI_OSD_INITIATOR is not set 562# CONFIG_SCSI_OSD_INITIATOR is not set
@@ -775,6 +779,11 @@ CONFIG_INOTIFY_USER=y
775# CONFIG_FUSE_FS is not set 779# CONFIG_FUSE_FS is not set
776 780
777# 781#
782# Caches
783#
784# CONFIG_FSCACHE is not set
785
786#
778# CD-ROM/DVD Filesystems 787# CD-ROM/DVD Filesystems
779# 788#
780# CONFIG_ISO9660_FS is not set 789# CONFIG_ISO9660_FS is not set
@@ -829,6 +838,7 @@ CONFIG_JFFS2_RTIME=y
829# CONFIG_ROMFS_FS is not set 838# CONFIG_ROMFS_FS is not set
830# CONFIG_SYSV_FS is not set 839# CONFIG_SYSV_FS is not set
831# CONFIG_UFS_FS is not set 840# CONFIG_UFS_FS is not set
841# CONFIG_NILFS2_FS is not set
832CONFIG_NETWORK_FILESYSTEMS=y 842CONFIG_NETWORK_FILESYSTEMS=y
833CONFIG_NFS_FS=y 843CONFIG_NFS_FS=y
834# CONFIG_NFS_V3 is not set 844# CONFIG_NFS_V3 is not set
@@ -886,10 +896,23 @@ CONFIG_FRAME_WARN=1024
886CONFIG_HAVE_FUNCTION_TRACER=y 896CONFIG_HAVE_FUNCTION_TRACER=y
887CONFIG_HAVE_DYNAMIC_FTRACE=y 897CONFIG_HAVE_DYNAMIC_FTRACE=y
888CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 898CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
899CONFIG_TRACING_SUPPORT=y
889 900
890# 901#
891# Tracers 902# Tracers
892# 903#
904# CONFIG_FUNCTION_TRACER is not set
905# CONFIG_IRQSOFF_TRACER is not set
906# CONFIG_SCHED_TRACER is not set
907# CONFIG_CONTEXT_SWITCH_TRACER is not set
908# CONFIG_EVENT_TRACER is not set
909# CONFIG_BOOT_TRACER is not set
910# CONFIG_TRACE_BRANCH_PROFILING is not set
911# CONFIG_STACK_TRACER is not set
912# CONFIG_KMEMTRACE is not set
913# CONFIG_WORKQUEUE_TRACER is not set
914# CONFIG_BLK_DEV_IO_TRACE is not set
915# CONFIG_DMA_API_DEBUG is not set
893# CONFIG_SAMPLES is not set 916# CONFIG_SAMPLES is not set
894CONFIG_HAVE_ARCH_KGDB=y 917CONFIG_HAVE_ARCH_KGDB=y
895# CONFIG_SH_STANDARD_BIOS is not set 918# CONFIG_SH_STANDARD_BIOS is not set
@@ -989,6 +1012,7 @@ CONFIG_CRYPTO=y
989# 1012#
990# CONFIG_CRYPTO_ANSI_CPRNG is not set 1013# CONFIG_CRYPTO_ANSI_CPRNG is not set
991CONFIG_CRYPTO_HW=y 1014CONFIG_CRYPTO_HW=y
1015# CONFIG_BINARY_PRINTF is not set
992 1016
993# 1017#
994# Library routines 1018# Library routines
diff --git a/arch/sh/configs/se7751_defconfig b/arch/sh/configs/se7751_defconfig
index 67fc26b3a7d0..55f3b788e0cb 100644
--- a/arch/sh/configs/se7751_defconfig
+++ b/arch/sh/configs/se7751_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 18:59:59 2009 4# Mon Apr 27 13:06:44 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -65,7 +66,6 @@ CONFIG_INITRAMFS_SOURCE=""
65CONFIG_RD_GZIP=y 66CONFIG_RD_GZIP=y
66# CONFIG_RD_BZIP2 is not set 67# CONFIG_RD_BZIP2 is not set
67# CONFIG_RD_LZMA is not set 68# CONFIG_RD_LZMA is not set
68CONFIG_INITRAMFS_COMPRESSION_NONE=y
69# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 69# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
70CONFIG_SYSCTL=y 70CONFIG_SYSCTL=y
71CONFIG_ANON_INODES=y 71CONFIG_ANON_INODES=y
@@ -74,6 +74,7 @@ CONFIG_UID16=y
74# CONFIG_SYSCTL_SYSCALL is not set 74# CONFIG_SYSCTL_SYSCALL is not set
75CONFIG_KALLSYMS=y 75CONFIG_KALLSYMS=y
76# CONFIG_KALLSYMS_EXTRA_PASS is not set 76# CONFIG_KALLSYMS_EXTRA_PASS is not set
77# CONFIG_STRIP_ASM_SYMS is not set
77# CONFIG_HOTPLUG is not set 78# CONFIG_HOTPLUG is not set
78CONFIG_PRINTK=y 79CONFIG_PRINTK=y
79CONFIG_BUG=y 80CONFIG_BUG=y
@@ -92,6 +93,7 @@ CONFIG_SLAB=y
92# CONFIG_SLUB is not set 93# CONFIG_SLUB is not set
93# CONFIG_SLOB is not set 94# CONFIG_SLOB is not set
94# CONFIG_PROFILING is not set 95# CONFIG_PROFILING is not set
96# CONFIG_MARKERS is not set
95CONFIG_HAVE_OPROFILE=y 97CONFIG_HAVE_OPROFILE=y
96# CONFIG_KPROBES is not set 98# CONFIG_KPROBES is not set
97CONFIG_HAVE_IOREMAP_PROT=y 99CONFIG_HAVE_IOREMAP_PROT=y
@@ -99,6 +101,8 @@ CONFIG_HAVE_KPROBES=y
99CONFIG_HAVE_KRETPROBES=y 101CONFIG_HAVE_KRETPROBES=y
100CONFIG_HAVE_ARCH_TRACEHOOK=y 102CONFIG_HAVE_ARCH_TRACEHOOK=y
101CONFIG_HAVE_CLK=y 103CONFIG_HAVE_CLK=y
104CONFIG_HAVE_DMA_API_DEBUG=y
105# CONFIG_SLOW_WORK is not set
102CONFIG_HAVE_GENERIC_DMA_COHERENT=y 106CONFIG_HAVE_GENERIC_DMA_COHERENT=y
103CONFIG_SLABINFO=y 107CONFIG_SLABINFO=y
104CONFIG_RT_MUTEXES=y 108CONFIG_RT_MUTEXES=y
@@ -110,7 +114,6 @@ CONFIG_MODULES=y
110# CONFIG_MODULE_SRCVERSION_ALL is not set 114# CONFIG_MODULE_SRCVERSION_ALL is not set
111CONFIG_BLOCK=y 115CONFIG_BLOCK=y
112# CONFIG_LBD is not set 116# CONFIG_LBD is not set
113# CONFIG_BLK_DEV_IO_TRACE is not set
114# CONFIG_BLK_DEV_BSG is not set 117# CONFIG_BLK_DEV_BSG is not set
115# CONFIG_BLK_DEV_INTEGRITY is not set 118# CONFIG_BLK_DEV_INTEGRITY is not set
116 119
@@ -156,6 +159,7 @@ CONFIG_CPU_SUBTYPE_SH7751=y
156# CONFIG_CPU_SUBTYPE_SH7760 is not set 159# CONFIG_CPU_SUBTYPE_SH7760 is not set
157# CONFIG_CPU_SUBTYPE_SH4_202 is not set 160# CONFIG_CPU_SUBTYPE_SH4_202 is not set
158# CONFIG_CPU_SUBTYPE_SH7723 is not set 161# CONFIG_CPU_SUBTYPE_SH7723 is not set
162# CONFIG_CPU_SUBTYPE_SH7724 is not set
159# CONFIG_CPU_SUBTYPE_SH7763 is not set 163# CONFIG_CPU_SUBTYPE_SH7763 is not set
160# CONFIG_CPU_SUBTYPE_SH7770 is not set 164# CONFIG_CPU_SUBTYPE_SH7770 is not set
161# CONFIG_CPU_SUBTYPE_SH7780 is not set 165# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -165,8 +169,6 @@ CONFIG_CPU_SUBTYPE_SH7751=y
165# CONFIG_CPU_SUBTYPE_SH7343 is not set 169# CONFIG_CPU_SUBTYPE_SH7343 is not set
166# CONFIG_CPU_SUBTYPE_SH7722 is not set 170# CONFIG_CPU_SUBTYPE_SH7722 is not set
167# CONFIG_CPU_SUBTYPE_SH7366 is not set 171# CONFIG_CPU_SUBTYPE_SH7366 is not set
168# CONFIG_CPU_SUBTYPE_SH5_101 is not set
169# CONFIG_CPU_SUBTYPE_SH5_103 is not set
170 172
171# 173#
172# Memory management options 174# Memory management options
@@ -742,6 +744,11 @@ CONFIG_INOTIFY_USER=y
742# CONFIG_FUSE_FS is not set 744# CONFIG_FUSE_FS is not set
743 745
744# 746#
747# Caches
748#
749# CONFIG_FSCACHE is not set
750
751#
745# CD-ROM/DVD Filesystems 752# CD-ROM/DVD Filesystems
746# 753#
747# CONFIG_ISO9660_FS is not set 754# CONFIG_ISO9660_FS is not set
@@ -796,6 +803,7 @@ CONFIG_JFFS2_RTIME=y
796# CONFIG_ROMFS_FS is not set 803# CONFIG_ROMFS_FS is not set
797# CONFIG_SYSV_FS is not set 804# CONFIG_SYSV_FS is not set
798# CONFIG_UFS_FS is not set 805# CONFIG_UFS_FS is not set
806# CONFIG_NILFS2_FS is not set
799CONFIG_NETWORK_FILESYSTEMS=y 807CONFIG_NETWORK_FILESYSTEMS=y
800# CONFIG_NFS_FS is not set 808# CONFIG_NFS_FS is not set
801# CONFIG_NFSD is not set 809# CONFIG_NFSD is not set
@@ -833,10 +841,23 @@ CONFIG_FRAME_WARN=1024
833CONFIG_HAVE_FUNCTION_TRACER=y 841CONFIG_HAVE_FUNCTION_TRACER=y
834CONFIG_HAVE_DYNAMIC_FTRACE=y 842CONFIG_HAVE_DYNAMIC_FTRACE=y
835CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 843CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
844CONFIG_TRACING_SUPPORT=y
836 845
837# 846#
838# Tracers 847# Tracers
839# 848#
849# CONFIG_FUNCTION_TRACER is not set
850# CONFIG_IRQSOFF_TRACER is not set
851# CONFIG_SCHED_TRACER is not set
852# CONFIG_CONTEXT_SWITCH_TRACER is not set
853# CONFIG_EVENT_TRACER is not set
854# CONFIG_BOOT_TRACER is not set
855# CONFIG_TRACE_BRANCH_PROFILING is not set
856# CONFIG_STACK_TRACER is not set
857# CONFIG_KMEMTRACE is not set
858# CONFIG_WORKQUEUE_TRACER is not set
859# CONFIG_BLK_DEV_IO_TRACE is not set
860# CONFIG_DMA_API_DEBUG is not set
840# CONFIG_SAMPLES is not set 861# CONFIG_SAMPLES is not set
841CONFIG_HAVE_ARCH_KGDB=y 862CONFIG_HAVE_ARCH_KGDB=y
842# CONFIG_SH_STANDARD_BIOS is not set 863# CONFIG_SH_STANDARD_BIOS is not set
@@ -936,6 +957,7 @@ CONFIG_CRYPTO=y
936# 957#
937# CONFIG_CRYPTO_ANSI_CPRNG is not set 958# CONFIG_CRYPTO_ANSI_CPRNG is not set
938CONFIG_CRYPTO_HW=y 959CONFIG_CRYPTO_HW=y
960# CONFIG_BINARY_PRINTF is not set
939 961
940# 962#
941# Library routines 963# Library routines
diff --git a/arch/sh/configs/se7780_defconfig b/arch/sh/configs/se7780_defconfig
index ebce23cc2ad8..c4f0af32efa9 100644
--- a/arch/sh/configs/se7780_defconfig
+++ b/arch/sh/configs/se7780_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 19:02:05 2009 4# Mon Apr 27 13:07:14 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -67,6 +68,7 @@ CONFIG_EMBEDDED=y
67CONFIG_UID16=y 68CONFIG_UID16=y
68CONFIG_SYSCTL_SYSCALL=y 69CONFIG_SYSCTL_SYSCALL=y
69# CONFIG_KALLSYMS is not set 70# CONFIG_KALLSYMS is not set
71# CONFIG_STRIP_ASM_SYMS is not set
70# CONFIG_HOTPLUG is not set 72# CONFIG_HOTPLUG is not set
71CONFIG_PRINTK=y 73CONFIG_PRINTK=y
72CONFIG_BUG=y 74CONFIG_BUG=y
@@ -86,12 +88,15 @@ CONFIG_SLAB=y
86# CONFIG_SLUB is not set 88# CONFIG_SLUB is not set
87# CONFIG_SLOB is not set 89# CONFIG_SLOB is not set
88# CONFIG_PROFILING is not set 90# CONFIG_PROFILING is not set
91# CONFIG_MARKERS is not set
89CONFIG_HAVE_OPROFILE=y 92CONFIG_HAVE_OPROFILE=y
90CONFIG_HAVE_IOREMAP_PROT=y 93CONFIG_HAVE_IOREMAP_PROT=y
91CONFIG_HAVE_KPROBES=y 94CONFIG_HAVE_KPROBES=y
92CONFIG_HAVE_KRETPROBES=y 95CONFIG_HAVE_KRETPROBES=y
93CONFIG_HAVE_ARCH_TRACEHOOK=y 96CONFIG_HAVE_ARCH_TRACEHOOK=y
94CONFIG_HAVE_CLK=y 97CONFIG_HAVE_CLK=y
98CONFIG_HAVE_DMA_API_DEBUG=y
99# CONFIG_SLOW_WORK is not set
95CONFIG_HAVE_GENERIC_DMA_COHERENT=y 100CONFIG_HAVE_GENERIC_DMA_COHERENT=y
96CONFIG_SLABINFO=y 101CONFIG_SLABINFO=y
97CONFIG_RT_MUTEXES=y 102CONFIG_RT_MUTEXES=y
@@ -103,7 +108,6 @@ CONFIG_MODULE_UNLOAD=y
103# CONFIG_MODULE_SRCVERSION_ALL is not set 108# CONFIG_MODULE_SRCVERSION_ALL is not set
104CONFIG_BLOCK=y 109CONFIG_BLOCK=y
105# CONFIG_LBD is not set 110# CONFIG_LBD is not set
106# CONFIG_BLK_DEV_IO_TRACE is not set
107# CONFIG_BLK_DEV_INTEGRITY is not set 111# CONFIG_BLK_DEV_INTEGRITY is not set
108 112
109# 113#
@@ -149,6 +153,7 @@ CONFIG_CPU_SH4A=y
149# CONFIG_CPU_SUBTYPE_SH7760 is not set 153# CONFIG_CPU_SUBTYPE_SH7760 is not set
150# CONFIG_CPU_SUBTYPE_SH4_202 is not set 154# CONFIG_CPU_SUBTYPE_SH4_202 is not set
151# CONFIG_CPU_SUBTYPE_SH7723 is not set 155# CONFIG_CPU_SUBTYPE_SH7723 is not set
156# CONFIG_CPU_SUBTYPE_SH7724 is not set
152# CONFIG_CPU_SUBTYPE_SH7763 is not set 157# CONFIG_CPU_SUBTYPE_SH7763 is not set
153# CONFIG_CPU_SUBTYPE_SH7770 is not set 158# CONFIG_CPU_SUBTYPE_SH7770 is not set
154CONFIG_CPU_SUBTYPE_SH7780=y 159CONFIG_CPU_SUBTYPE_SH7780=y
@@ -158,8 +163,6 @@ CONFIG_CPU_SUBTYPE_SH7780=y
158# CONFIG_CPU_SUBTYPE_SH7343 is not set 163# CONFIG_CPU_SUBTYPE_SH7343 is not set
159# CONFIG_CPU_SUBTYPE_SH7722 is not set 164# CONFIG_CPU_SUBTYPE_SH7722 is not set
160# CONFIG_CPU_SUBTYPE_SH7366 is not set 165# CONFIG_CPU_SUBTYPE_SH7366 is not set
161# CONFIG_CPU_SUBTYPE_SH5_101 is not set
162# CONFIG_CPU_SUBTYPE_SH5_103 is not set
163 166
164# 167#
165# Memory management options 168# Memory management options
@@ -285,8 +288,6 @@ CONFIG_CMDLINE="console=ttySC0.115200 root=/dev/sda1"
285# 288#
286CONFIG_PCI=y 289CONFIG_PCI=y
287CONFIG_SH_PCIDMA_NONCOHERENT=y 290CONFIG_SH_PCIDMA_NONCOHERENT=y
288CONFIG_PCI_AUTO=y
289CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
290# CONFIG_PCIEPORTBUS is not set 291# CONFIG_PCIEPORTBUS is not set
291# CONFIG_ARCH_SUPPORTS_MSI is not set 292# CONFIG_ARCH_SUPPORTS_MSI is not set
292CONFIG_PCI_LEGACY=y 293CONFIG_PCI_LEGACY=y
@@ -558,6 +559,7 @@ CONFIG_SCSI_LOWLEVEL=y
558# CONFIG_SCSI_MPT2SAS is not set 559# CONFIG_SCSI_MPT2SAS is not set
559# CONFIG_SCSI_HPTIOP is not set 560# CONFIG_SCSI_HPTIOP is not set
560# CONFIG_LIBFC is not set 561# CONFIG_LIBFC is not set
562# CONFIG_LIBFCOE is not set
561# CONFIG_FCOE is not set 563# CONFIG_FCOE is not set
562# CONFIG_SCSI_DMX3191D is not set 564# CONFIG_SCSI_DMX3191D is not set
563# CONFIG_SCSI_FUTURE_DOMAIN is not set 565# CONFIG_SCSI_FUTURE_DOMAIN is not set
@@ -957,15 +959,17 @@ CONFIG_USB_HID=y
957# 959#
958# Special HID drivers 960# Special HID drivers
959# 961#
960CONFIG_HID_COMPAT=y
961CONFIG_HID_A4TECH=y 962CONFIG_HID_A4TECH=y
962CONFIG_HID_APPLE=y 963CONFIG_HID_APPLE=y
963CONFIG_HID_BELKIN=y 964CONFIG_HID_BELKIN=y
964CONFIG_HID_CHERRY=y 965CONFIG_HID_CHERRY=y
965CONFIG_HID_CHICONY=y 966CONFIG_HID_CHICONY=y
966CONFIG_HID_CYPRESS=y 967CONFIG_HID_CYPRESS=y
968# CONFIG_DRAGONRISE_FF is not set
967CONFIG_HID_EZKEY=y 969CONFIG_HID_EZKEY=y
970# CONFIG_HID_KYE is not set
968CONFIG_HID_GYRATION=y 971CONFIG_HID_GYRATION=y
972# CONFIG_HID_KENSINGTON is not set
969CONFIG_HID_LOGITECH=y 973CONFIG_HID_LOGITECH=y
970# CONFIG_LOGITECH_FF is not set 974# CONFIG_LOGITECH_FF is not set
971# CONFIG_LOGIRUMBLEPAD2_FF is not set 975# CONFIG_LOGIRUMBLEPAD2_FF is not set
@@ -1122,6 +1126,10 @@ CONFIG_INOTIFY_USER=y
1122# CONFIG_FUSE_FS is not set 1126# CONFIG_FUSE_FS is not set
1123 1127
1124# 1128#
1129# Caches
1130#
1131
1132#
1125# CD-ROM/DVD Filesystems 1133# CD-ROM/DVD Filesystems
1126# 1134#
1127# CONFIG_ISO9660_FS is not set 1135# CONFIG_ISO9660_FS is not set
@@ -1245,11 +1253,24 @@ CONFIG_DEBUG_FS=y
1245CONFIG_HAVE_FUNCTION_TRACER=y 1253CONFIG_HAVE_FUNCTION_TRACER=y
1246CONFIG_HAVE_DYNAMIC_FTRACE=y 1254CONFIG_HAVE_DYNAMIC_FTRACE=y
1247CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1255CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1256CONFIG_TRACING_SUPPORT=y
1248 1257
1249# 1258#
1250# Tracers 1259# Tracers
1251# 1260#
1261# CONFIG_FUNCTION_TRACER is not set
1262# CONFIG_IRQSOFF_TRACER is not set
1263# CONFIG_SCHED_TRACER is not set
1264# CONFIG_CONTEXT_SWITCH_TRACER is not set
1265# CONFIG_EVENT_TRACER is not set
1266# CONFIG_BOOT_TRACER is not set
1267# CONFIG_TRACE_BRANCH_PROFILING is not set
1268# CONFIG_STACK_TRACER is not set
1269# CONFIG_KMEMTRACE is not set
1270# CONFIG_WORKQUEUE_TRACER is not set
1271# CONFIG_BLK_DEV_IO_TRACE is not set
1252# CONFIG_DYNAMIC_DEBUG is not set 1272# CONFIG_DYNAMIC_DEBUG is not set
1273# CONFIG_DMA_API_DEBUG is not set
1253# CONFIG_SAMPLES is not set 1274# CONFIG_SAMPLES is not set
1254CONFIG_HAVE_ARCH_KGDB=y 1275CONFIG_HAVE_ARCH_KGDB=y
1255# CONFIG_SH_STANDARD_BIOS is not set 1276# CONFIG_SH_STANDARD_BIOS is not set
@@ -1345,6 +1366,7 @@ CONFIG_CRYPTO=y
1345# CONFIG_CRYPTO_ANSI_CPRNG is not set 1366# CONFIG_CRYPTO_ANSI_CPRNG is not set
1346CONFIG_CRYPTO_HW=y 1367CONFIG_CRYPTO_HW=y
1347# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1368# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1369# CONFIG_BINARY_PRINTF is not set
1348 1370
1349# 1371#
1350# Library routines 1372# Library routines
diff --git a/arch/sh/configs/sh03_defconfig b/arch/sh/configs/sh03_defconfig
index 6fcdb090cf32..f9c6e51dc0b0 100644
--- a/arch/sh/configs/sh03_defconfig
+++ b/arch/sh/configs/sh03_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 19:04:59 2009 4# Mon Apr 27 13:07:56 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -41,6 +42,7 @@ CONFIG_SWAP=y
41CONFIG_SYSVIPC=y 42CONFIG_SYSVIPC=y
42CONFIG_SYSVIPC_SYSCTL=y 43CONFIG_SYSVIPC_SYSCTL=y
43CONFIG_POSIX_MQUEUE=y 44CONFIG_POSIX_MQUEUE=y
45CONFIG_POSIX_MQUEUE_SYSCTL=y
44CONFIG_BSD_PROCESS_ACCT=y 46CONFIG_BSD_PROCESS_ACCT=y
45# CONFIG_BSD_PROCESS_ACCT_V3 is not set 47# CONFIG_BSD_PROCESS_ACCT_V3 is not set
46# CONFIG_TASKSTATS is not set 48# CONFIG_TASKSTATS is not set
@@ -67,7 +69,6 @@ CONFIG_INITRAMFS_SOURCE=""
67CONFIG_RD_GZIP=y 69CONFIG_RD_GZIP=y
68# CONFIG_RD_BZIP2 is not set 70# CONFIG_RD_BZIP2 is not set
69# CONFIG_RD_LZMA is not set 71# CONFIG_RD_LZMA is not set
70CONFIG_INITRAMFS_COMPRESSION_NONE=y
71CONFIG_CC_OPTIMIZE_FOR_SIZE=y 72CONFIG_CC_OPTIMIZE_FOR_SIZE=y
72CONFIG_SYSCTL=y 73CONFIG_SYSCTL=y
73CONFIG_ANON_INODES=y 74CONFIG_ANON_INODES=y
@@ -76,6 +77,7 @@ CONFIG_UID16=y
76# CONFIG_SYSCTL_SYSCALL is not set 77# CONFIG_SYSCTL_SYSCALL is not set
77CONFIG_KALLSYMS=y 78CONFIG_KALLSYMS=y
78# CONFIG_KALLSYMS_EXTRA_PASS is not set 79# CONFIG_KALLSYMS_EXTRA_PASS is not set
80# CONFIG_STRIP_ASM_SYMS is not set
79CONFIG_HOTPLUG=y 81CONFIG_HOTPLUG=y
80CONFIG_PRINTK=y 82CONFIG_PRINTK=y
81CONFIG_BUG=y 83CONFIG_BUG=y
@@ -105,6 +107,8 @@ CONFIG_HAVE_KPROBES=y
105CONFIG_HAVE_KRETPROBES=y 107CONFIG_HAVE_KRETPROBES=y
106CONFIG_HAVE_ARCH_TRACEHOOK=y 108CONFIG_HAVE_ARCH_TRACEHOOK=y
107CONFIG_HAVE_CLK=y 109CONFIG_HAVE_CLK=y
110CONFIG_HAVE_DMA_API_DEBUG=y
111# CONFIG_SLOW_WORK is not set
108CONFIG_HAVE_GENERIC_DMA_COHERENT=y 112CONFIG_HAVE_GENERIC_DMA_COHERENT=y
109CONFIG_SLABINFO=y 113CONFIG_SLABINFO=y
110CONFIG_RT_MUTEXES=y 114CONFIG_RT_MUTEXES=y
@@ -117,7 +121,6 @@ CONFIG_MODVERSIONS=y
117# CONFIG_MODULE_SRCVERSION_ALL is not set 121# CONFIG_MODULE_SRCVERSION_ALL is not set
118CONFIG_BLOCK=y 122CONFIG_BLOCK=y
119# CONFIG_LBD is not set 123# CONFIG_LBD is not set
120# CONFIG_BLK_DEV_IO_TRACE is not set
121# CONFIG_BLK_DEV_BSG is not set 124# CONFIG_BLK_DEV_BSG is not set
122# CONFIG_BLK_DEV_INTEGRITY is not set 125# CONFIG_BLK_DEV_INTEGRITY is not set
123 126
@@ -163,6 +166,7 @@ CONFIG_CPU_SUBTYPE_SH7751=y
163# CONFIG_CPU_SUBTYPE_SH7760 is not set 166# CONFIG_CPU_SUBTYPE_SH7760 is not set
164# CONFIG_CPU_SUBTYPE_SH4_202 is not set 167# CONFIG_CPU_SUBTYPE_SH4_202 is not set
165# CONFIG_CPU_SUBTYPE_SH7723 is not set 168# CONFIG_CPU_SUBTYPE_SH7723 is not set
169# CONFIG_CPU_SUBTYPE_SH7724 is not set
166# CONFIG_CPU_SUBTYPE_SH7763 is not set 170# CONFIG_CPU_SUBTYPE_SH7763 is not set
167# CONFIG_CPU_SUBTYPE_SH7770 is not set 171# CONFIG_CPU_SUBTYPE_SH7770 is not set
168# CONFIG_CPU_SUBTYPE_SH7780 is not set 172# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -172,8 +176,6 @@ CONFIG_CPU_SUBTYPE_SH7751=y
172# CONFIG_CPU_SUBTYPE_SH7343 is not set 176# CONFIG_CPU_SUBTYPE_SH7343 is not set
173# CONFIG_CPU_SUBTYPE_SH7722 is not set 177# CONFIG_CPU_SUBTYPE_SH7722 is not set
174# CONFIG_CPU_SUBTYPE_SH7366 is not set 178# CONFIG_CPU_SUBTYPE_SH7366 is not set
175# CONFIG_CPU_SUBTYPE_SH5_101 is not set
176# CONFIG_CPU_SUBTYPE_SH5_103 is not set
177 179
178# 180#
179# Memory management options 181# Memory management options
@@ -300,8 +302,6 @@ CONFIG_CMDLINE="console=ttySC1,115200 mem=64M root=/dev/nfs"
300# 302#
301CONFIG_PCI=y 303CONFIG_PCI=y
302CONFIG_SH_PCIDMA_NONCOHERENT=y 304CONFIG_SH_PCIDMA_NONCOHERENT=y
303CONFIG_PCI_AUTO=y
304CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
305# CONFIG_PCIEPORTBUS is not set 305# CONFIG_PCIEPORTBUS is not set
306# CONFIG_ARCH_SUPPORTS_MSI is not set 306# CONFIG_ARCH_SUPPORTS_MSI is not set
307CONFIG_PCI_LEGACY=y 307CONFIG_PCI_LEGACY=y
@@ -562,6 +562,7 @@ CONFIG_SCSI_LOWLEVEL=y
562# CONFIG_SCSI_MPT2SAS is not set 562# CONFIG_SCSI_MPT2SAS is not set
563# CONFIG_SCSI_HPTIOP is not set 563# CONFIG_SCSI_HPTIOP is not set
564# CONFIG_LIBFC is not set 564# CONFIG_LIBFC is not set
565# CONFIG_LIBFCOE is not set
565# CONFIG_FCOE is not set 566# CONFIG_FCOE is not set
566# CONFIG_SCSI_DMX3191D is not set 567# CONFIG_SCSI_DMX3191D is not set
567# CONFIG_SCSI_FUTURE_DOMAIN is not set 568# CONFIG_SCSI_FUTURE_DOMAIN is not set
@@ -656,6 +657,7 @@ CONFIG_NETDEV_1000=y
656# CONFIG_E1000E is not set 657# CONFIG_E1000E is not set
657# CONFIG_IP1000 is not set 658# CONFIG_IP1000 is not set
658# CONFIG_IGB is not set 659# CONFIG_IGB is not set
660# CONFIG_IGBVF is not set
659# CONFIG_NS83820 is not set 661# CONFIG_NS83820 is not set
660# CONFIG_HAMACHI is not set 662# CONFIG_HAMACHI is not set
661# CONFIG_YELLOWFIN is not set 663# CONFIG_YELLOWFIN is not set
@@ -679,6 +681,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
679# CONFIG_IXGBE is not set 681# CONFIG_IXGBE is not set
680# CONFIG_IXGB is not set 682# CONFIG_IXGB is not set
681# CONFIG_S2IO is not set 683# CONFIG_S2IO is not set
684# CONFIG_VXGE is not set
682# CONFIG_MYRI10GE is not set 685# CONFIG_MYRI10GE is not set
683# CONFIG_NETXEN_NIC is not set 686# CONFIG_NETXEN_NIC is not set
684# CONFIG_NIU is not set 687# CONFIG_NIU is not set
@@ -887,7 +890,6 @@ CONFIG_HID=y
887# 890#
888# Special HID drivers 891# Special HID drivers
889# 892#
890CONFIG_HID_COMPAT=y
891CONFIG_USB_SUPPORT=y 893CONFIG_USB_SUPPORT=y
892CONFIG_USB_ARCH_HAS_HCD=y 894CONFIG_USB_ARCH_HAS_HCD=y
893CONFIG_USB_ARCH_HAS_OHCI=y 895CONFIG_USB_ARCH_HAS_OHCI=y
@@ -929,6 +931,7 @@ CONFIG_EXT2_FS_XATTR=y
929# CONFIG_EXT2_FS_SECURITY is not set 931# CONFIG_EXT2_FS_SECURITY is not set
930# CONFIG_EXT2_FS_XIP is not set 932# CONFIG_EXT2_FS_XIP is not set
931CONFIG_EXT3_FS=y 933CONFIG_EXT3_FS=y
934# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
932CONFIG_EXT3_FS_XATTR=y 935CONFIG_EXT3_FS_XATTR=y
933CONFIG_EXT3_FS_POSIX_ACL=y 936CONFIG_EXT3_FS_POSIX_ACL=y
934# CONFIG_EXT3_FS_SECURITY is not set 937# CONFIG_EXT3_FS_SECURITY is not set
@@ -952,6 +955,11 @@ CONFIG_AUTOFS4_FS=y
952# CONFIG_FUSE_FS is not set 955# CONFIG_FUSE_FS is not set
953 956
954# 957#
958# Caches
959#
960# CONFIG_FSCACHE is not set
961
962#
955# CD-ROM/DVD Filesystems 963# CD-ROM/DVD Filesystems
956# 964#
957CONFIG_ISO9660_FS=m 965CONFIG_ISO9660_FS=m
@@ -1001,6 +1009,7 @@ CONFIG_MISC_FILESYSTEMS=y
1001# CONFIG_ROMFS_FS is not set 1009# CONFIG_ROMFS_FS is not set
1002# CONFIG_SYSV_FS is not set 1010# CONFIG_SYSV_FS is not set
1003# CONFIG_UFS_FS is not set 1011# CONFIG_UFS_FS is not set
1012# CONFIG_NILFS2_FS is not set
1004CONFIG_NETWORK_FILESYSTEMS=y 1013CONFIG_NETWORK_FILESYSTEMS=y
1005CONFIG_NFS_FS=y 1014CONFIG_NFS_FS=y
1006CONFIG_NFS_V3=y 1015CONFIG_NFS_V3=y
@@ -1112,11 +1121,26 @@ CONFIG_HAVE_DYNAMIC_FTRACE=y
1112CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1121CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1113CONFIG_RING_BUFFER=y 1122CONFIG_RING_BUFFER=y
1114CONFIG_TRACING=y 1123CONFIG_TRACING=y
1124CONFIG_TRACING_SUPPORT=y
1115 1125
1116# 1126#
1117# Tracers 1127# Tracers
1118# 1128#
1129# CONFIG_FUNCTION_TRACER is not set
1130# CONFIG_IRQSOFF_TRACER is not set
1131# CONFIG_PREEMPT_TRACER is not set
1132# CONFIG_SCHED_TRACER is not set
1133# CONFIG_CONTEXT_SWITCH_TRACER is not set
1134# CONFIG_EVENT_TRACER is not set
1135# CONFIG_BOOT_TRACER is not set
1136# CONFIG_TRACE_BRANCH_PROFILING is not set
1137# CONFIG_STACK_TRACER is not set
1138# CONFIG_KMEMTRACE is not set
1139# CONFIG_WORKQUEUE_TRACER is not set
1140# CONFIG_BLK_DEV_IO_TRACE is not set
1141# CONFIG_FTRACE_STARTUP_TEST is not set
1119# CONFIG_DYNAMIC_DEBUG is not set 1142# CONFIG_DYNAMIC_DEBUG is not set
1143# CONFIG_DMA_API_DEBUG is not set
1120# CONFIG_SAMPLES is not set 1144# CONFIG_SAMPLES is not set
1121CONFIG_HAVE_ARCH_KGDB=y 1145CONFIG_HAVE_ARCH_KGDB=y
1122CONFIG_SH_STANDARD_BIOS=y 1146CONFIG_SH_STANDARD_BIOS=y
@@ -1228,6 +1252,7 @@ CONFIG_CRYPTO_DEFLATE=y
1228# CONFIG_CRYPTO_ANSI_CPRNG is not set 1252# CONFIG_CRYPTO_ANSI_CPRNG is not set
1229CONFIG_CRYPTO_HW=y 1253CONFIG_CRYPTO_HW=y
1230# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1254# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1255CONFIG_BINARY_PRINTF=y
1231 1256
1232# 1257#
1233# Library routines 1258# Library routines
diff --git a/arch/sh/configs/sh7710voipgw_defconfig b/arch/sh/configs/sh7710voipgw_defconfig
index 1ab37c01da6e..48b58098cf84 100644
--- a/arch/sh/configs/sh7710voipgw_defconfig
+++ b/arch/sh/configs/sh7710voipgw_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 19:09:01 2009 4# Mon Apr 27 13:09:16 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -39,6 +40,7 @@ CONFIG_LOCALVERSION_AUTO=y
39CONFIG_SYSVIPC=y 40CONFIG_SYSVIPC=y
40CONFIG_SYSVIPC_SYSCTL=y 41CONFIG_SYSVIPC_SYSCTL=y
41CONFIG_POSIX_MQUEUE=y 42CONFIG_POSIX_MQUEUE=y
43CONFIG_POSIX_MQUEUE_SYSCTL=y
42# CONFIG_BSD_PROCESS_ACCT is not set 44# CONFIG_BSD_PROCESS_ACCT is not set
43# CONFIG_TASKSTATS is not set 45# CONFIG_TASKSTATS is not set
44# CONFIG_AUDIT is not set 46# CONFIG_AUDIT is not set
@@ -72,6 +74,7 @@ CONFIG_UID16=y
72# CONFIG_SYSCTL_SYSCALL is not set 74# CONFIG_SYSCTL_SYSCALL is not set
73CONFIG_KALLSYMS=y 75CONFIG_KALLSYMS=y
74# CONFIG_KALLSYMS_EXTRA_PASS is not set 76# CONFIG_KALLSYMS_EXTRA_PASS is not set
77# CONFIG_STRIP_ASM_SYMS is not set
75CONFIG_HOTPLUG=y 78CONFIG_HOTPLUG=y
76CONFIG_PRINTK=y 79CONFIG_PRINTK=y
77CONFIG_BUG=y 80CONFIG_BUG=y
@@ -90,6 +93,7 @@ CONFIG_SLAB=y
90# CONFIG_SLUB is not set 93# CONFIG_SLUB is not set
91# CONFIG_SLOB is not set 94# CONFIG_SLOB is not set
92# CONFIG_PROFILING is not set 95# CONFIG_PROFILING is not set
96# CONFIG_MARKERS is not set
93CONFIG_HAVE_OPROFILE=y 97CONFIG_HAVE_OPROFILE=y
94# CONFIG_KPROBES is not set 98# CONFIG_KPROBES is not set
95CONFIG_HAVE_IOREMAP_PROT=y 99CONFIG_HAVE_IOREMAP_PROT=y
@@ -97,6 +101,8 @@ CONFIG_HAVE_KPROBES=y
97CONFIG_HAVE_KRETPROBES=y 101CONFIG_HAVE_KRETPROBES=y
98CONFIG_HAVE_ARCH_TRACEHOOK=y 102CONFIG_HAVE_ARCH_TRACEHOOK=y
99CONFIG_HAVE_CLK=y 103CONFIG_HAVE_CLK=y
104CONFIG_HAVE_DMA_API_DEBUG=y
105# CONFIG_SLOW_WORK is not set
100CONFIG_HAVE_GENERIC_DMA_COHERENT=y 106CONFIG_HAVE_GENERIC_DMA_COHERENT=y
101CONFIG_SLABINFO=y 107CONFIG_SLABINFO=y
102CONFIG_BASE_SMALL=0 108CONFIG_BASE_SMALL=0
@@ -108,7 +114,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y
108# CONFIG_MODULE_SRCVERSION_ALL is not set 114# CONFIG_MODULE_SRCVERSION_ALL is not set
109CONFIG_BLOCK=y 115CONFIG_BLOCK=y
110# CONFIG_LBD is not set 116# CONFIG_LBD is not set
111# CONFIG_BLK_DEV_IO_TRACE is not set
112# CONFIG_BLK_DEV_BSG is not set 117# CONFIG_BLK_DEV_BSG is not set
113# CONFIG_BLK_DEV_INTEGRITY is not set 118# CONFIG_BLK_DEV_INTEGRITY is not set
114 119
@@ -154,6 +159,7 @@ CONFIG_CPU_SUBTYPE_SH7710=y
154# CONFIG_CPU_SUBTYPE_SH7760 is not set 159# CONFIG_CPU_SUBTYPE_SH7760 is not set
155# CONFIG_CPU_SUBTYPE_SH4_202 is not set 160# CONFIG_CPU_SUBTYPE_SH4_202 is not set
156# CONFIG_CPU_SUBTYPE_SH7723 is not set 161# CONFIG_CPU_SUBTYPE_SH7723 is not set
162# CONFIG_CPU_SUBTYPE_SH7724 is not set
157# CONFIG_CPU_SUBTYPE_SH7763 is not set 163# CONFIG_CPU_SUBTYPE_SH7763 is not set
158# CONFIG_CPU_SUBTYPE_SH7770 is not set 164# CONFIG_CPU_SUBTYPE_SH7770 is not set
159# CONFIG_CPU_SUBTYPE_SH7780 is not set 165# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -163,8 +169,6 @@ CONFIG_CPU_SUBTYPE_SH7710=y
163# CONFIG_CPU_SUBTYPE_SH7343 is not set 169# CONFIG_CPU_SUBTYPE_SH7343 is not set
164# CONFIG_CPU_SUBTYPE_SH7722 is not set 170# CONFIG_CPU_SUBTYPE_SH7722 is not set
165# CONFIG_CPU_SUBTYPE_SH7366 is not set 171# CONFIG_CPU_SUBTYPE_SH7366 is not set
166# CONFIG_CPU_SUBTYPE_SH5_101 is not set
167# CONFIG_CPU_SUBTYPE_SH5_103 is not set
168 172
169# 173#
170# Memory management options 174# Memory management options
@@ -728,7 +732,6 @@ CONFIG_HID=y
728# 732#
729# Special HID drivers 733# Special HID drivers
730# 734#
731CONFIG_HID_COMPAT=y
732CONFIG_USB_SUPPORT=y 735CONFIG_USB_SUPPORT=y
733CONFIG_USB_ARCH_HAS_HCD=y 736CONFIG_USB_ARCH_HAS_HCD=y
734# CONFIG_USB_ARCH_HAS_OHCI is not set 737# CONFIG_USB_ARCH_HAS_OHCI is not set
@@ -780,6 +783,11 @@ CONFIG_FILE_LOCKING=y
780# CONFIG_FUSE_FS is not set 783# CONFIG_FUSE_FS is not set
781 784
782# 785#
786# Caches
787#
788# CONFIG_FSCACHE is not set
789
790#
783# CD-ROM/DVD Filesystems 791# CD-ROM/DVD Filesystems
784# 792#
785# CONFIG_ISO9660_FS is not set 793# CONFIG_ISO9660_FS is not set
@@ -834,6 +842,7 @@ CONFIG_JFFS2_RTIME=y
834# CONFIG_ROMFS_FS is not set 842# CONFIG_ROMFS_FS is not set
835# CONFIG_SYSV_FS is not set 843# CONFIG_SYSV_FS is not set
836# CONFIG_UFS_FS is not set 844# CONFIG_UFS_FS is not set
845# CONFIG_NILFS2_FS is not set
837CONFIG_NETWORK_FILESYSTEMS=y 846CONFIG_NETWORK_FILESYSTEMS=y
838# CONFIG_NFS_FS is not set 847# CONFIG_NFS_FS is not set
839# CONFIG_NFSD is not set 848# CONFIG_NFSD is not set
@@ -871,11 +880,24 @@ CONFIG_DEBUG_FS=y
871CONFIG_HAVE_FUNCTION_TRACER=y 880CONFIG_HAVE_FUNCTION_TRACER=y
872CONFIG_HAVE_DYNAMIC_FTRACE=y 881CONFIG_HAVE_DYNAMIC_FTRACE=y
873CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 882CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
883CONFIG_TRACING_SUPPORT=y
874 884
875# 885#
876# Tracers 886# Tracers
877# 887#
888# CONFIG_FUNCTION_TRACER is not set
889# CONFIG_IRQSOFF_TRACER is not set
890# CONFIG_SCHED_TRACER is not set
891# CONFIG_CONTEXT_SWITCH_TRACER is not set
892# CONFIG_EVENT_TRACER is not set
893# CONFIG_BOOT_TRACER is not set
894# CONFIG_TRACE_BRANCH_PROFILING is not set
895# CONFIG_STACK_TRACER is not set
896# CONFIG_KMEMTRACE is not set
897# CONFIG_WORKQUEUE_TRACER is not set
898# CONFIG_BLK_DEV_IO_TRACE is not set
878# CONFIG_DYNAMIC_DEBUG is not set 899# CONFIG_DYNAMIC_DEBUG is not set
900# CONFIG_DMA_API_DEBUG is not set
879# CONFIG_SAMPLES is not set 901# CONFIG_SAMPLES is not set
880CONFIG_HAVE_ARCH_KGDB=y 902CONFIG_HAVE_ARCH_KGDB=y
881# CONFIG_SH_STANDARD_BIOS is not set 903# CONFIG_SH_STANDARD_BIOS is not set
@@ -975,6 +997,7 @@ CONFIG_CRYPTO=y
975# 997#
976# CONFIG_CRYPTO_ANSI_CPRNG is not set 998# CONFIG_CRYPTO_ANSI_CPRNG is not set
977CONFIG_CRYPTO_HW=y 999CONFIG_CRYPTO_HW=y
1000# CONFIG_BINARY_PRINTF is not set
978 1001
979# 1002#
980# Library routines 1003# Library routines
diff --git a/arch/sh/configs/sh7724_generic_defconfig b/arch/sh/configs/sh7724_generic_defconfig
new file mode 100644
index 000000000000..ec8f18c7684c
--- /dev/null
+++ b/arch/sh/configs/sh7724_generic_defconfig
@@ -0,0 +1,707 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.30-rc3
4# Mon Apr 27 13:09:47 2009
5#
6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
10CONFIG_RWSEM_GENERIC_SPINLOCK=y
11CONFIG_GENERIC_BUG=y
12CONFIG_GENERIC_FIND_NEXT_BIT=y
13CONFIG_GENERIC_HWEIGHT=y
14CONFIG_GENERIC_HARDIRQS=y
15CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
16CONFIG_GENERIC_IRQ_PROBE=y
17# CONFIG_GENERIC_GPIO is not set
18CONFIG_GENERIC_TIME=y
19CONFIG_GENERIC_CLOCKEVENTS=y
20CONFIG_ARCH_SUSPEND_POSSIBLE=y
21CONFIG_ARCH_HIBERNATION_POSSIBLE=y
22CONFIG_SYS_SUPPORTS_CMT=y
23CONFIG_STACKTRACE_SUPPORT=y
24CONFIG_LOCKDEP_SUPPORT=y
25CONFIG_HAVE_LATENCYTOP_SUPPORT=y
26# CONFIG_ARCH_HAS_ILOG2_U32 is not set
27# CONFIG_ARCH_HAS_ILOG2_U64 is not set
28CONFIG_ARCH_NO_VIRT_TO_BUS=y
29CONFIG_ARCH_HAS_DEFAULT_IDLE=y
30CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
31
32#
33# General setup
34#
35CONFIG_EXPERIMENTAL=y
36CONFIG_BROKEN_ON_SMP=y
37CONFIG_INIT_ENV_ARG_LIMIT=32
38CONFIG_LOCALVERSION=""
39# CONFIG_LOCALVERSION_AUTO is not set
40CONFIG_SWAP=y
41CONFIG_SYSVIPC=y
42CONFIG_SYSVIPC_SYSCTL=y
43# CONFIG_BSD_PROCESS_ACCT is not set
44
45#
46# RCU Subsystem
47#
48# CONFIG_CLASSIC_RCU is not set
49CONFIG_TREE_RCU=y
50# CONFIG_PREEMPT_RCU is not set
51# CONFIG_RCU_TRACE is not set
52CONFIG_RCU_FANOUT=32
53# CONFIG_RCU_FANOUT_EXACT is not set
54# CONFIG_TREE_RCU_TRACE is not set
55# CONFIG_PREEMPT_RCU_TRACE is not set
56# CONFIG_IKCONFIG is not set
57CONFIG_LOG_BUF_SHIFT=17
58CONFIG_GROUP_SCHED=y
59CONFIG_FAIR_GROUP_SCHED=y
60CONFIG_RT_GROUP_SCHED=y
61CONFIG_USER_SCHED=y
62# CONFIG_CGROUP_SCHED is not set
63CONFIG_CGROUPS=y
64# CONFIG_CGROUP_DEBUG is not set
65# CONFIG_CGROUP_NS is not set
66# CONFIG_CGROUP_FREEZER is not set
67# CONFIG_CGROUP_DEVICE is not set
68# CONFIG_CPUSETS is not set
69# CONFIG_CGROUP_CPUACCT is not set
70# CONFIG_RESOURCE_COUNTERS is not set
71# CONFIG_RELAY is not set
72# CONFIG_NAMESPACES is not set
73# CONFIG_BLK_DEV_INITRD is not set
74CONFIG_CC_OPTIMIZE_FOR_SIZE=y
75CONFIG_SYSCTL=y
76CONFIG_ANON_INODES=y
77CONFIG_EMBEDDED=y
78# CONFIG_UID16 is not set
79CONFIG_SYSCTL_SYSCALL=y
80CONFIG_KALLSYMS=y
81# CONFIG_KALLSYMS_EXTRA_PASS is not set
82# CONFIG_STRIP_ASM_SYMS is not set
83CONFIG_HOTPLUG=y
84CONFIG_PRINTK=y
85CONFIG_BUG=y
86CONFIG_ELF_CORE=y
87CONFIG_BASE_FULL=y
88CONFIG_FUTEX=y
89CONFIG_EPOLL=y
90CONFIG_SIGNALFD=y
91CONFIG_TIMERFD=y
92CONFIG_EVENTFD=y
93CONFIG_SHMEM=y
94CONFIG_AIO=y
95CONFIG_VM_EVENT_COUNTERS=y
96# CONFIG_COMPAT_BRK is not set
97# CONFIG_SLAB is not set
98CONFIG_SLUB=y
99# CONFIG_SLOB is not set
100CONFIG_PROFILING=y
101CONFIG_TRACEPOINTS=y
102# CONFIG_MARKERS is not set
103CONFIG_OPROFILE=y
104CONFIG_HAVE_OPROFILE=y
105CONFIG_HAVE_IOREMAP_PROT=y
106CONFIG_HAVE_KPROBES=y
107CONFIG_HAVE_KRETPROBES=y
108CONFIG_HAVE_ARCH_TRACEHOOK=y
109CONFIG_HAVE_CLK=y
110CONFIG_HAVE_DMA_API_DEBUG=y
111# CONFIG_SLOW_WORK is not set
112CONFIG_HAVE_GENERIC_DMA_COHERENT=y
113CONFIG_RT_MUTEXES=y
114CONFIG_BASE_SMALL=0
115# CONFIG_MODULES is not set
116CONFIG_BLOCK=y
117# CONFIG_LBD is not set
118# CONFIG_BLK_DEV_BSG is not set
119# CONFIG_BLK_DEV_INTEGRITY is not set
120
121#
122# IO Schedulers
123#
124CONFIG_IOSCHED_NOOP=y
125CONFIG_IOSCHED_AS=y
126CONFIG_IOSCHED_DEADLINE=y
127CONFIG_IOSCHED_CFQ=y
128CONFIG_DEFAULT_AS=y
129# CONFIG_DEFAULT_DEADLINE is not set
130# CONFIG_DEFAULT_CFQ is not set
131# CONFIG_DEFAULT_NOOP is not set
132CONFIG_DEFAULT_IOSCHED="anticipatory"
133CONFIG_FREEZER=y
134
135#
136# System type
137#
138CONFIG_CPU_SH4=y
139CONFIG_CPU_SH4A=y
140CONFIG_CPU_SHX2=y
141CONFIG_ARCH_SHMOBILE=y
142# CONFIG_CPU_SUBTYPE_SH7619 is not set
143# CONFIG_CPU_SUBTYPE_SH7201 is not set
144# CONFIG_CPU_SUBTYPE_SH7203 is not set
145# CONFIG_CPU_SUBTYPE_SH7206 is not set
146# CONFIG_CPU_SUBTYPE_SH7263 is not set
147# CONFIG_CPU_SUBTYPE_MXG is not set
148# CONFIG_CPU_SUBTYPE_SH7705 is not set
149# CONFIG_CPU_SUBTYPE_SH7706 is not set
150# CONFIG_CPU_SUBTYPE_SH7707 is not set
151# CONFIG_CPU_SUBTYPE_SH7708 is not set
152# CONFIG_CPU_SUBTYPE_SH7709 is not set
153# CONFIG_CPU_SUBTYPE_SH7710 is not set
154# CONFIG_CPU_SUBTYPE_SH7712 is not set
155# CONFIG_CPU_SUBTYPE_SH7720 is not set
156# CONFIG_CPU_SUBTYPE_SH7721 is not set
157# CONFIG_CPU_SUBTYPE_SH7750 is not set
158# CONFIG_CPU_SUBTYPE_SH7091 is not set
159# CONFIG_CPU_SUBTYPE_SH7750R is not set
160# CONFIG_CPU_SUBTYPE_SH7750S is not set
161# CONFIG_CPU_SUBTYPE_SH7751 is not set
162# CONFIG_CPU_SUBTYPE_SH7751R is not set
163# CONFIG_CPU_SUBTYPE_SH7760 is not set
164# CONFIG_CPU_SUBTYPE_SH4_202 is not set
165# CONFIG_CPU_SUBTYPE_SH7723 is not set
166CONFIG_CPU_SUBTYPE_SH7724=y
167# CONFIG_CPU_SUBTYPE_SH7763 is not set
168# CONFIG_CPU_SUBTYPE_SH7770 is not set
169# CONFIG_CPU_SUBTYPE_SH7780 is not set
170# CONFIG_CPU_SUBTYPE_SH7785 is not set
171# CONFIG_CPU_SUBTYPE_SH7786 is not set
172# CONFIG_CPU_SUBTYPE_SHX3 is not set
173# CONFIG_CPU_SUBTYPE_SH7343 is not set
174# CONFIG_CPU_SUBTYPE_SH7722 is not set
175# CONFIG_CPU_SUBTYPE_SH7366 is not set
176
177#
178# Memory management options
179#
180CONFIG_QUICKLIST=y
181CONFIG_MMU=y
182CONFIG_PAGE_OFFSET=0x80000000
183CONFIG_MEMORY_START=0x08000000
184CONFIG_MEMORY_SIZE=0x04000000
185CONFIG_29BIT=y
186# CONFIG_X2TLB is not set
187CONFIG_VSYSCALL=y
188CONFIG_ARCH_FLATMEM_ENABLE=y
189CONFIG_ARCH_SPARSEMEM_ENABLE=y
190CONFIG_ARCH_SPARSEMEM_DEFAULT=y
191CONFIG_MAX_ACTIVE_REGIONS=1
192CONFIG_ARCH_POPULATES_NODE_MAP=y
193CONFIG_ARCH_SELECT_MEMORY_MODEL=y
194CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
195CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
196CONFIG_PAGE_SIZE_4KB=y
197# CONFIG_PAGE_SIZE_8KB is not set
198# CONFIG_PAGE_SIZE_16KB is not set
199# CONFIG_PAGE_SIZE_64KB is not set
200CONFIG_ENTRY_OFFSET=0x00001000
201CONFIG_SELECT_MEMORY_MODEL=y
202# CONFIG_FLATMEM_MANUAL is not set
203# CONFIG_DISCONTIGMEM_MANUAL is not set
204CONFIG_SPARSEMEM_MANUAL=y
205CONFIG_SPARSEMEM=y
206CONFIG_HAVE_MEMORY_PRESENT=y
207CONFIG_SPARSEMEM_STATIC=y
208
209#
210# Memory hotplug is currently incompatible with Software Suspend
211#
212CONFIG_PAGEFLAGS_EXTENDED=y
213CONFIG_SPLIT_PTLOCK_CPUS=4
214CONFIG_MIGRATION=y
215# CONFIG_PHYS_ADDR_T_64BIT is not set
216CONFIG_ZONE_DMA_FLAG=0
217CONFIG_NR_QUICK=2
218CONFIG_UNEVICTABLE_LRU=y
219CONFIG_HAVE_MLOCK=y
220CONFIG_HAVE_MLOCKED_PAGE_BIT=y
221
222#
223# Cache configuration
224#
225CONFIG_CACHE_WRITEBACK=y
226# CONFIG_CACHE_WRITETHROUGH is not set
227# CONFIG_CACHE_OFF is not set
228
229#
230# Processor features
231#
232CONFIG_CPU_LITTLE_ENDIAN=y
233# CONFIG_CPU_BIG_ENDIAN is not set
234CONFIG_SH_FPU=y
235# CONFIG_SH_STORE_QUEUES is not set
236CONFIG_CPU_HAS_INTEVT=y
237CONFIG_CPU_HAS_SR_RB=y
238CONFIG_CPU_HAS_PTEA=y
239CONFIG_CPU_HAS_FPU=y
240
241#
242# Board support
243#
244
245#
246# Timer and clock configuration
247#
248CONFIG_SH_TMU=y
249CONFIG_SH_TIMER_CMT=y
250CONFIG_SH_TIMER_IRQ=16
251CONFIG_SH_PCLK_FREQ=41666666
252CONFIG_TICK_ONESHOT=y
253CONFIG_NO_HZ=y
254CONFIG_HIGH_RES_TIMERS=y
255CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
256
257#
258# CPU Frequency scaling
259#
260CONFIG_CPU_FREQ=y
261CONFIG_CPU_FREQ_TABLE=y
262# CONFIG_CPU_FREQ_DEBUG is not set
263CONFIG_CPU_FREQ_STAT=y
264# CONFIG_CPU_FREQ_STAT_DETAILS is not set
265CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
266# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
267# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
268# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
269# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
270CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
271# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
272# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
273# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
274# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
275CONFIG_SH_CPU_FREQ=y
276
277#
278# DMA support
279#
280# CONFIG_SH_DMA is not set
281
282#
283# Companion Chips
284#
285
286#
287# Additional SuperH Device Drivers
288#
289# CONFIG_HEARTBEAT is not set
290# CONFIG_PUSH_SWITCH is not set
291
292#
293# Kernel features
294#
295# CONFIG_HZ_100 is not set
296CONFIG_HZ_250=y
297# CONFIG_HZ_300 is not set
298# CONFIG_HZ_1000 is not set
299CONFIG_HZ=250
300CONFIG_SCHED_HRTICK=y
301CONFIG_KEXEC=y
302# CONFIG_CRASH_DUMP is not set
303CONFIG_KEXEC_JUMP=y
304CONFIG_PREEMPT_NONE=y
305# CONFIG_PREEMPT_VOLUNTARY is not set
306# CONFIG_PREEMPT is not set
307CONFIG_GUSA=y
308
309#
310# Boot options
311#
312CONFIG_ZERO_PAGE_OFFSET=0x00001000
313CONFIG_BOOT_LINK_OFFSET=0x00800000
314# CONFIG_CMDLINE_BOOL is not set
315
316#
317# Bus options
318#
319# CONFIG_ARCH_SUPPORTS_MSI is not set
320# CONFIG_PCCARD is not set
321
322#
323# Executable file formats
324#
325CONFIG_BINFMT_ELF=y
326# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
327# CONFIG_HAVE_AOUT is not set
328# CONFIG_BINFMT_MISC is not set
329
330#
331# Power management options (EXPERIMENTAL)
332#
333CONFIG_PM=y
334# CONFIG_PM_DEBUG is not set
335CONFIG_PM_SLEEP=y
336CONFIG_SUSPEND=y
337CONFIG_SUSPEND_FREEZER=y
338CONFIG_HIBERNATION=y
339CONFIG_PM_STD_PARTITION=""
340CONFIG_CPU_IDLE=y
341CONFIG_CPU_IDLE_GOV_LADDER=y
342CONFIG_CPU_IDLE_GOV_MENU=y
343# CONFIG_NET is not set
344
345#
346# Device Drivers
347#
348
349#
350# Generic Driver Options
351#
352CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
353CONFIG_STANDALONE=y
354# CONFIG_PREVENT_FIRMWARE_BUILD is not set
355CONFIG_FW_LOADER=y
356CONFIG_FIRMWARE_IN_KERNEL=y
357CONFIG_EXTRA_FIRMWARE=""
358# CONFIG_SYS_HYPERVISOR is not set
359# CONFIG_MTD is not set
360# CONFIG_PARPORT is not set
361CONFIG_BLK_DEV=y
362# CONFIG_BLK_DEV_COW_COMMON is not set
363# CONFIG_BLK_DEV_LOOP is not set
364# CONFIG_BLK_DEV_RAM is not set
365# CONFIG_CDROM_PKTCDVD is not set
366# CONFIG_BLK_DEV_HD is not set
367# CONFIG_MISC_DEVICES is not set
368CONFIG_HAVE_IDE=y
369# CONFIG_IDE is not set
370
371#
372# SCSI device support
373#
374# CONFIG_RAID_ATTRS is not set
375# CONFIG_SCSI is not set
376# CONFIG_SCSI_DMA is not set
377# CONFIG_SCSI_NETLINK is not set
378# CONFIG_ATA is not set
379# CONFIG_MD is not set
380# CONFIG_PHONE is not set
381
382#
383# Input device support
384#
385# CONFIG_INPUT is not set
386
387#
388# Hardware I/O ports
389#
390# CONFIG_SERIO is not set
391# CONFIG_GAMEPORT is not set
392
393#
394# Character devices
395#
396# CONFIG_VT is not set
397# CONFIG_DEVKMEM is not set
398# CONFIG_SERIAL_NONSTANDARD is not set
399
400#
401# Serial drivers
402#
403# CONFIG_SERIAL_8250 is not set
404
405#
406# Non-8250 serial port support
407#
408CONFIG_SERIAL_SH_SCI=y
409CONFIG_SERIAL_SH_SCI_NR_UARTS=6
410CONFIG_SERIAL_SH_SCI_CONSOLE=y
411CONFIG_SERIAL_CORE=y
412CONFIG_SERIAL_CORE_CONSOLE=y
413# CONFIG_UNIX98_PTYS is not set
414# CONFIG_LEGACY_PTYS is not set
415# CONFIG_IPMI_HANDLER is not set
416# CONFIG_HW_RANDOM is not set
417# CONFIG_R3964 is not set
418# CONFIG_RAW_DRIVER is not set
419# CONFIG_TCG_TPM is not set
420CONFIG_I2C=y
421CONFIG_I2C_BOARDINFO=y
422CONFIG_I2C_CHARDEV=y
423CONFIG_I2C_HELPER_AUTO=y
424
425#
426# I2C Hardware Bus support
427#
428
429#
430# I2C system bus drivers (mostly embedded / system-on-chip)
431#
432# CONFIG_I2C_OCORES is not set
433CONFIG_I2C_SH_MOBILE=y
434# CONFIG_I2C_SIMTEC is not set
435
436#
437# External I2C/SMBus adapter drivers
438#
439# CONFIG_I2C_PARPORT_LIGHT is not set
440# CONFIG_I2C_TAOS_EVM is not set
441
442#
443# Other I2C/SMBus bus drivers
444#
445# CONFIG_I2C_PCA_PLATFORM is not set
446
447#
448# Miscellaneous I2C Chip support
449#
450# CONFIG_DS1682 is not set
451# CONFIG_SENSORS_PCF8574 is not set
452# CONFIG_PCF8575 is not set
453# CONFIG_SENSORS_PCA9539 is not set
454# CONFIG_SENSORS_MAX6875 is not set
455# CONFIG_SENSORS_TSL2550 is not set
456# CONFIG_I2C_DEBUG_CORE is not set
457# CONFIG_I2C_DEBUG_ALGO is not set
458# CONFIG_I2C_DEBUG_BUS is not set
459# CONFIG_I2C_DEBUG_CHIP is not set
460# CONFIG_SPI is not set
461# CONFIG_W1 is not set
462# CONFIG_POWER_SUPPLY is not set
463# CONFIG_HWMON is not set
464# CONFIG_THERMAL is not set
465# CONFIG_THERMAL_HWMON is not set
466# CONFIG_WATCHDOG is not set
467CONFIG_SSB_POSSIBLE=y
468
469#
470# Sonics Silicon Backplane
471#
472# CONFIG_SSB is not set
473
474#
475# Multifunction device drivers
476#
477# CONFIG_MFD_CORE is not set
478# CONFIG_MFD_SM501 is not set
479# CONFIG_HTC_PASIC3 is not set
480# CONFIG_TWL4030_CORE is not set
481# CONFIG_MFD_TMIO is not set
482# CONFIG_PMIC_DA903X is not set
483# CONFIG_MFD_WM8400 is not set
484# CONFIG_MFD_WM8350_I2C is not set
485# CONFIG_MFD_PCF50633 is not set
486# CONFIG_REGULATOR is not set
487
488#
489# Multimedia devices
490#
491
492#
493# Multimedia core support
494#
495# CONFIG_VIDEO_DEV is not set
496# CONFIG_VIDEO_MEDIA is not set
497
498#
499# Multimedia drivers
500#
501# CONFIG_DAB is not set
502
503#
504# Graphics support
505#
506# CONFIG_VGASTATE is not set
507# CONFIG_VIDEO_OUTPUT_CONTROL is not set
508# CONFIG_FB is not set
509# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
510
511#
512# Display device support
513#
514# CONFIG_DISPLAY_SUPPORT is not set
515# CONFIG_SOUND is not set
516# CONFIG_USB_SUPPORT is not set
517# CONFIG_MMC is not set
518# CONFIG_MEMSTICK is not set
519# CONFIG_NEW_LEDS is not set
520# CONFIG_ACCESSIBILITY is not set
521CONFIG_RTC_LIB=y
522CONFIG_RTC_CLASS=y
523CONFIG_RTC_HCTOSYS=y
524CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
525# CONFIG_RTC_DEBUG is not set
526
527#
528# RTC interfaces
529#
530CONFIG_RTC_INTF_DEV=y
531# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
532# CONFIG_RTC_DRV_TEST is not set
533
534#
535# I2C RTC drivers
536#
537# CONFIG_RTC_DRV_DS1307 is not set
538# CONFIG_RTC_DRV_DS1374 is not set
539# CONFIG_RTC_DRV_DS1672 is not set
540# CONFIG_RTC_DRV_MAX6900 is not set
541# CONFIG_RTC_DRV_RS5C372 is not set
542# CONFIG_RTC_DRV_ISL1208 is not set
543# CONFIG_RTC_DRV_X1205 is not set
544# CONFIG_RTC_DRV_PCF8563 is not set
545# CONFIG_RTC_DRV_PCF8583 is not set
546# CONFIG_RTC_DRV_M41T80 is not set
547# CONFIG_RTC_DRV_S35390A is not set
548# CONFIG_RTC_DRV_FM3130 is not set
549# CONFIG_RTC_DRV_RX8581 is not set
550
551#
552# SPI RTC drivers
553#
554
555#
556# Platform RTC drivers
557#
558# CONFIG_RTC_DRV_DS1286 is not set
559# CONFIG_RTC_DRV_DS1511 is not set
560# CONFIG_RTC_DRV_DS1553 is not set
561# CONFIG_RTC_DRV_DS1742 is not set
562# CONFIG_RTC_DRV_STK17TA8 is not set
563# CONFIG_RTC_DRV_M48T86 is not set
564# CONFIG_RTC_DRV_M48T35 is not set
565# CONFIG_RTC_DRV_M48T59 is not set
566# CONFIG_RTC_DRV_BQ4802 is not set
567# CONFIG_RTC_DRV_V3020 is not set
568
569#
570# on-CPU RTC drivers
571#
572CONFIG_RTC_DRV_SH=y
573# CONFIG_DMADEVICES is not set
574# CONFIG_AUXDISPLAY is not set
575CONFIG_UIO=y
576# CONFIG_UIO_PDRV is not set
577CONFIG_UIO_PDRV_GENIRQ=y
578# CONFIG_UIO_SMX is not set
579# CONFIG_UIO_SERCOS3 is not set
580# CONFIG_STAGING is not set
581
582#
583# File systems
584#
585# CONFIG_EXT2_FS is not set
586# CONFIG_EXT3_FS is not set
587# CONFIG_EXT4_FS is not set
588# CONFIG_REISERFS_FS is not set
589# CONFIG_JFS_FS is not set
590# CONFIG_FS_POSIX_ACL is not set
591CONFIG_FILE_LOCKING=y
592# CONFIG_XFS_FS is not set
593# CONFIG_BTRFS_FS is not set
594# CONFIG_DNOTIFY is not set
595# CONFIG_INOTIFY is not set
596# CONFIG_QUOTA is not set
597# CONFIG_AUTOFS_FS is not set
598# CONFIG_AUTOFS4_FS is not set
599# CONFIG_FUSE_FS is not set
600
601#
602# Caches
603#
604# CONFIG_FSCACHE is not set
605
606#
607# CD-ROM/DVD Filesystems
608#
609# CONFIG_ISO9660_FS is not set
610# CONFIG_UDF_FS is not set
611
612#
613# DOS/FAT/NT Filesystems
614#
615# CONFIG_MSDOS_FS is not set
616# CONFIG_VFAT_FS is not set
617# CONFIG_NTFS_FS is not set
618
619#
620# Pseudo filesystems
621#
622# CONFIG_PROC_FS is not set
623# CONFIG_SYSFS is not set
624# CONFIG_TMPFS is not set
625# CONFIG_HUGETLBFS is not set
626# CONFIG_HUGETLB_PAGE is not set
627# CONFIG_MISC_FILESYSTEMS is not set
628
629#
630# Partition Types
631#
632# CONFIG_PARTITION_ADVANCED is not set
633CONFIG_MSDOS_PARTITION=y
634# CONFIG_NLS is not set
635
636#
637# Kernel hacking
638#
639CONFIG_TRACE_IRQFLAGS_SUPPORT=y
640# CONFIG_PRINTK_TIME is not set
641# CONFIG_ENABLE_WARN_DEPRECATED is not set
642# CONFIG_ENABLE_MUST_CHECK is not set
643CONFIG_FRAME_WARN=1024
644# CONFIG_MAGIC_SYSRQ is not set
645# CONFIG_UNUSED_SYMBOLS is not set
646CONFIG_DEBUG_FS=y
647# CONFIG_HEADERS_CHECK is not set
648# CONFIG_DEBUG_KERNEL is not set
649CONFIG_STACKTRACE=y
650# CONFIG_DEBUG_BUGVERBOSE is not set
651# CONFIG_DEBUG_MEMORY_INIT is not set
652# CONFIG_RCU_CPU_STALL_DETECTOR is not set
653# CONFIG_LATENCYTOP is not set
654# CONFIG_SYSCTL_SYSCALL_CHECK is not set
655CONFIG_NOP_TRACER=y
656CONFIG_HAVE_FUNCTION_TRACER=y
657CONFIG_HAVE_DYNAMIC_FTRACE=y
658CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
659CONFIG_RING_BUFFER=y
660CONFIG_TRACING=y
661CONFIG_TRACING_SUPPORT=y
662
663#
664# Tracers
665#
666# CONFIG_FUNCTION_TRACER is not set
667# CONFIG_IRQSOFF_TRACER is not set
668# CONFIG_SCHED_TRACER is not set
669# CONFIG_CONTEXT_SWITCH_TRACER is not set
670# CONFIG_EVENT_TRACER is not set
671# CONFIG_BOOT_TRACER is not set
672# CONFIG_TRACE_BRANCH_PROFILING is not set
673# CONFIG_STACK_TRACER is not set
674# CONFIG_KMEMTRACE is not set
675# CONFIG_WORKQUEUE_TRACER is not set
676# CONFIG_FTRACE_STARTUP_TEST is not set
677# CONFIG_DYNAMIC_DEBUG is not set
678# CONFIG_DMA_API_DEBUG is not set
679# CONFIG_SAMPLES is not set
680CONFIG_HAVE_ARCH_KGDB=y
681# CONFIG_SH_STANDARD_BIOS is not set
682# CONFIG_EARLY_SCIF_CONSOLE is not set
683# CONFIG_MORE_COMPILE_OPTIONS is not set
684
685#
686# Security options
687#
688# CONFIG_KEYS is not set
689# CONFIG_SECURITYFS is not set
690# CONFIG_SECURITY_FILE_CAPABILITIES is not set
691# CONFIG_CRYPTO is not set
692CONFIG_BINARY_PRINTF=y
693
694#
695# Library routines
696#
697CONFIG_GENERIC_FIND_LAST_BIT=y
698# CONFIG_CRC_CCITT is not set
699# CONFIG_CRC16 is not set
700# CONFIG_CRC_T10DIF is not set
701# CONFIG_CRC_ITU_T is not set
702# CONFIG_CRC32 is not set
703# CONFIG_CRC7 is not set
704# CONFIG_LIBCRC32C is not set
705CONFIG_HAS_IOMEM=y
706CONFIG_HAS_IOPORT=y
707CONFIG_HAS_DMA=y
diff --git a/arch/sh/configs/sh7763rdp_defconfig b/arch/sh/configs/sh7763rdp_defconfig
index c79bb84ec305..f77bc7998d2f 100644
--- a/arch/sh/configs/sh7763rdp_defconfig
+++ b/arch/sh/configs/sh7763rdp_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 19:10:57 2009 4# Mon Apr 27 13:10:12 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -78,6 +79,7 @@ CONFIG_UID16=y
78# CONFIG_SYSCTL_SYSCALL is not set 79# CONFIG_SYSCTL_SYSCALL is not set
79CONFIG_KALLSYMS=y 80CONFIG_KALLSYMS=y
80# CONFIG_KALLSYMS_EXTRA_PASS is not set 81# CONFIG_KALLSYMS_EXTRA_PASS is not set
82# CONFIG_STRIP_ASM_SYMS is not set
81CONFIG_HOTPLUG=y 83CONFIG_HOTPLUG=y
82CONFIG_PRINTK=y 84CONFIG_PRINTK=y
83CONFIG_BUG=y 85CONFIG_BUG=y
@@ -106,6 +108,8 @@ CONFIG_HAVE_KPROBES=y
106CONFIG_HAVE_KRETPROBES=y 108CONFIG_HAVE_KRETPROBES=y
107CONFIG_HAVE_ARCH_TRACEHOOK=y 109CONFIG_HAVE_ARCH_TRACEHOOK=y
108CONFIG_HAVE_CLK=y 110CONFIG_HAVE_CLK=y
111CONFIG_HAVE_DMA_API_DEBUG=y
112# CONFIG_SLOW_WORK is not set
109CONFIG_HAVE_GENERIC_DMA_COHERENT=y 113CONFIG_HAVE_GENERIC_DMA_COHERENT=y
110CONFIG_SLABINFO=y 114CONFIG_SLABINFO=y
111CONFIG_RT_MUTEXES=y 115CONFIG_RT_MUTEXES=y
@@ -117,7 +121,6 @@ CONFIG_MODULES=y
117# CONFIG_MODULE_SRCVERSION_ALL is not set 121# CONFIG_MODULE_SRCVERSION_ALL is not set
118CONFIG_BLOCK=y 122CONFIG_BLOCK=y
119# CONFIG_LBD is not set 123# CONFIG_LBD is not set
120# CONFIG_BLK_DEV_IO_TRACE is not set
121# CONFIG_BLK_DEV_BSG is not set 124# CONFIG_BLK_DEV_BSG is not set
122# CONFIG_BLK_DEV_INTEGRITY is not set 125# CONFIG_BLK_DEV_INTEGRITY is not set
123 126
@@ -164,6 +167,7 @@ CONFIG_CPU_SH4A=y
164# CONFIG_CPU_SUBTYPE_SH7760 is not set 167# CONFIG_CPU_SUBTYPE_SH7760 is not set
165# CONFIG_CPU_SUBTYPE_SH4_202 is not set 168# CONFIG_CPU_SUBTYPE_SH4_202 is not set
166# CONFIG_CPU_SUBTYPE_SH7723 is not set 169# CONFIG_CPU_SUBTYPE_SH7723 is not set
170# CONFIG_CPU_SUBTYPE_SH7724 is not set
167CONFIG_CPU_SUBTYPE_SH7763=y 171CONFIG_CPU_SUBTYPE_SH7763=y
168# CONFIG_CPU_SUBTYPE_SH7770 is not set 172# CONFIG_CPU_SUBTYPE_SH7770 is not set
169# CONFIG_CPU_SUBTYPE_SH7780 is not set 173# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -173,8 +177,6 @@ CONFIG_CPU_SUBTYPE_SH7763=y
173# CONFIG_CPU_SUBTYPE_SH7343 is not set 177# CONFIG_CPU_SUBTYPE_SH7343 is not set
174# CONFIG_CPU_SUBTYPE_SH7722 is not set 178# CONFIG_CPU_SUBTYPE_SH7722 is not set
175# CONFIG_CPU_SUBTYPE_SH7366 is not set 179# CONFIG_CPU_SUBTYPE_SH7366 is not set
176# CONFIG_CPU_SUBTYPE_SH5_101 is not set
177# CONFIG_CPU_SUBTYPE_SH5_103 is not set
178 180
179# 181#
180# Memory management options 182# Memory management options
@@ -555,6 +557,7 @@ CONFIG_SCSI_WAIT_SCAN=m
555CONFIG_SCSI_LOWLEVEL=y 557CONFIG_SCSI_LOWLEVEL=y
556# CONFIG_ISCSI_TCP is not set 558# CONFIG_ISCSI_TCP is not set
557# CONFIG_LIBFC is not set 559# CONFIG_LIBFC is not set
560# CONFIG_LIBFCOE is not set
558# CONFIG_SCSI_DEBUG is not set 561# CONFIG_SCSI_DEBUG is not set
559# CONFIG_SCSI_DH is not set 562# CONFIG_SCSI_DH is not set
560# CONFIG_SCSI_OSD_INITIATOR is not set 563# CONFIG_SCSI_OSD_INITIATOR is not set
@@ -941,6 +944,7 @@ CONFIG_EXT2_FS=y
941# CONFIG_EXT2_FS_XATTR is not set 944# CONFIG_EXT2_FS_XATTR is not set
942# CONFIG_EXT2_FS_XIP is not set 945# CONFIG_EXT2_FS_XIP is not set
943CONFIG_EXT3_FS=y 946CONFIG_EXT3_FS=y
947# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
944CONFIG_EXT3_FS_XATTR=y 948CONFIG_EXT3_FS_XATTR=y
945# CONFIG_EXT3_FS_POSIX_ACL is not set 949# CONFIG_EXT3_FS_POSIX_ACL is not set
946# CONFIG_EXT3_FS_SECURITY is not set 950# CONFIG_EXT3_FS_SECURITY is not set
@@ -965,6 +969,11 @@ CONFIG_AUTOFS4_FS=y
965CONFIG_GENERIC_ACL=y 969CONFIG_GENERIC_ACL=y
966 970
967# 971#
972# Caches
973#
974# CONFIG_FSCACHE is not set
975
976#
968# CD-ROM/DVD Filesystems 977# CD-ROM/DVD Filesystems
969# 978#
970# CONFIG_ISO9660_FS is not set 979# CONFIG_ISO9660_FS is not set
@@ -1012,6 +1021,7 @@ CONFIG_MISC_FILESYSTEMS=y
1012# CONFIG_ROMFS_FS is not set 1021# CONFIG_ROMFS_FS is not set
1013# CONFIG_SYSV_FS is not set 1022# CONFIG_SYSV_FS is not set
1014# CONFIG_UFS_FS is not set 1023# CONFIG_UFS_FS is not set
1024# CONFIG_NILFS2_FS is not set
1015CONFIG_NETWORK_FILESYSTEMS=y 1025CONFIG_NETWORK_FILESYSTEMS=y
1016CONFIG_NFS_FS=y 1026CONFIG_NFS_FS=y
1017# CONFIG_NFS_V3 is not set 1027# CONFIG_NFS_V3 is not set
@@ -1100,11 +1110,25 @@ CONFIG_HAVE_DYNAMIC_FTRACE=y
1100CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1110CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1101CONFIG_RING_BUFFER=y 1111CONFIG_RING_BUFFER=y
1102CONFIG_TRACING=y 1112CONFIG_TRACING=y
1113CONFIG_TRACING_SUPPORT=y
1103 1114
1104# 1115#
1105# Tracers 1116# Tracers
1106# 1117#
1118# CONFIG_FUNCTION_TRACER is not set
1119# CONFIG_IRQSOFF_TRACER is not set
1120# CONFIG_SCHED_TRACER is not set
1121# CONFIG_CONTEXT_SWITCH_TRACER is not set
1122# CONFIG_EVENT_TRACER is not set
1123# CONFIG_BOOT_TRACER is not set
1124# CONFIG_TRACE_BRANCH_PROFILING is not set
1125# CONFIG_STACK_TRACER is not set
1126# CONFIG_KMEMTRACE is not set
1127# CONFIG_WORKQUEUE_TRACER is not set
1128# CONFIG_BLK_DEV_IO_TRACE is not set
1129# CONFIG_FTRACE_STARTUP_TEST is not set
1107# CONFIG_DYNAMIC_DEBUG is not set 1130# CONFIG_DYNAMIC_DEBUG is not set
1131# CONFIG_DMA_API_DEBUG is not set
1108# CONFIG_SAMPLES is not set 1132# CONFIG_SAMPLES is not set
1109CONFIG_HAVE_ARCH_KGDB=y 1133CONFIG_HAVE_ARCH_KGDB=y
1110# CONFIG_SH_STANDARD_BIOS is not set 1134# CONFIG_SH_STANDARD_BIOS is not set
@@ -1204,6 +1228,7 @@ CONFIG_CRYPTO=y
1204# 1228#
1205# CONFIG_CRYPTO_ANSI_CPRNG is not set 1229# CONFIG_CRYPTO_ANSI_CPRNG is not set
1206CONFIG_CRYPTO_HW=y 1230CONFIG_CRYPTO_HW=y
1231CONFIG_BINARY_PRINTF=y
1207 1232
1208# 1233#
1209# Library routines 1234# Library routines
diff --git a/arch/sh/configs/sh7770_generic_defconfig b/arch/sh/configs/sh7770_generic_defconfig
new file mode 100644
index 000000000000..d6489b46ca5b
--- /dev/null
+++ b/arch/sh/configs/sh7770_generic_defconfig
@@ -0,0 +1,700 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.30-rc4
4# Tue May 12 14:48:21 2009
5#
6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
10CONFIG_RWSEM_GENERIC_SPINLOCK=y
11CONFIG_GENERIC_BUG=y
12CONFIG_GENERIC_FIND_NEXT_BIT=y
13CONFIG_GENERIC_HWEIGHT=y
14CONFIG_GENERIC_HARDIRQS=y
15CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
16CONFIG_GENERIC_IRQ_PROBE=y
17# CONFIG_GENERIC_GPIO is not set
18CONFIG_GENERIC_TIME=y
19CONFIG_GENERIC_CLOCKEVENTS=y
20# CONFIG_ARCH_SUSPEND_POSSIBLE is not set
21CONFIG_ARCH_HIBERNATION_POSSIBLE=y
22CONFIG_SYS_SUPPORTS_TMU=y
23CONFIG_STACKTRACE_SUPPORT=y
24CONFIG_LOCKDEP_SUPPORT=y
25CONFIG_HAVE_LATENCYTOP_SUPPORT=y
26# CONFIG_ARCH_HAS_ILOG2_U32 is not set
27# CONFIG_ARCH_HAS_ILOG2_U64 is not set
28CONFIG_ARCH_NO_VIRT_TO_BUS=y
29CONFIG_ARCH_HAS_DEFAULT_IDLE=y
30CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
31
32#
33# General setup
34#
35CONFIG_EXPERIMENTAL=y
36CONFIG_BROKEN_ON_SMP=y
37CONFIG_INIT_ENV_ARG_LIMIT=32
38CONFIG_LOCALVERSION=""
39# CONFIG_LOCALVERSION_AUTO is not set
40CONFIG_SWAP=y
41CONFIG_SYSVIPC=y
42CONFIG_SYSVIPC_SYSCTL=y
43# CONFIG_BSD_PROCESS_ACCT is not set
44
45#
46# RCU Subsystem
47#
48# CONFIG_CLASSIC_RCU is not set
49CONFIG_TREE_RCU=y
50# CONFIG_PREEMPT_RCU is not set
51# CONFIG_RCU_TRACE is not set
52CONFIG_RCU_FANOUT=32
53# CONFIG_RCU_FANOUT_EXACT is not set
54# CONFIG_TREE_RCU_TRACE is not set
55# CONFIG_PREEMPT_RCU_TRACE is not set
56# CONFIG_IKCONFIG is not set
57CONFIG_LOG_BUF_SHIFT=17
58CONFIG_GROUP_SCHED=y
59CONFIG_FAIR_GROUP_SCHED=y
60CONFIG_RT_GROUP_SCHED=y
61CONFIG_USER_SCHED=y
62# CONFIG_CGROUP_SCHED is not set
63CONFIG_CGROUPS=y
64# CONFIG_CGROUP_DEBUG is not set
65# CONFIG_CGROUP_NS is not set
66# CONFIG_CGROUP_FREEZER is not set
67# CONFIG_CGROUP_DEVICE is not set
68# CONFIG_CPUSETS is not set
69# CONFIG_CGROUP_CPUACCT is not set
70# CONFIG_RESOURCE_COUNTERS is not set
71# CONFIG_RELAY is not set
72# CONFIG_NAMESPACES is not set
73# CONFIG_BLK_DEV_INITRD is not set
74CONFIG_CC_OPTIMIZE_FOR_SIZE=y
75CONFIG_SYSCTL=y
76CONFIG_ANON_INODES=y
77CONFIG_EMBEDDED=y
78# CONFIG_UID16 is not set
79CONFIG_SYSCTL_SYSCALL=y
80CONFIG_KALLSYMS=y
81# CONFIG_KALLSYMS_EXTRA_PASS is not set
82# CONFIG_STRIP_ASM_SYMS is not set
83CONFIG_HOTPLUG=y
84CONFIG_PRINTK=y
85CONFIG_BUG=y
86CONFIG_ELF_CORE=y
87CONFIG_BASE_FULL=y
88CONFIG_FUTEX=y
89CONFIG_EPOLL=y
90CONFIG_SIGNALFD=y
91CONFIG_TIMERFD=y
92CONFIG_EVENTFD=y
93CONFIG_SHMEM=y
94CONFIG_AIO=y
95CONFIG_VM_EVENT_COUNTERS=y
96# CONFIG_COMPAT_BRK is not set
97# CONFIG_SLAB is not set
98CONFIG_SLUB=y
99# CONFIG_SLOB is not set
100CONFIG_PROFILING=y
101CONFIG_TRACEPOINTS=y
102# CONFIG_MARKERS is not set
103CONFIG_OPROFILE=y
104CONFIG_HAVE_OPROFILE=y
105CONFIG_HAVE_IOREMAP_PROT=y
106CONFIG_HAVE_KPROBES=y
107CONFIG_HAVE_KRETPROBES=y
108CONFIG_HAVE_ARCH_TRACEHOOK=y
109CONFIG_HAVE_CLK=y
110CONFIG_HAVE_DMA_API_DEBUG=y
111# CONFIG_SLOW_WORK is not set
112CONFIG_HAVE_GENERIC_DMA_COHERENT=y
113CONFIG_RT_MUTEXES=y
114CONFIG_BASE_SMALL=0
115# CONFIG_MODULES is not set
116CONFIG_BLOCK=y
117# CONFIG_LBD is not set
118# CONFIG_BLK_DEV_BSG is not set
119# CONFIG_BLK_DEV_INTEGRITY is not set
120
121#
122# IO Schedulers
123#
124CONFIG_IOSCHED_NOOP=y
125CONFIG_IOSCHED_AS=y
126CONFIG_IOSCHED_DEADLINE=y
127CONFIG_IOSCHED_CFQ=y
128CONFIG_DEFAULT_AS=y
129# CONFIG_DEFAULT_DEADLINE is not set
130# CONFIG_DEFAULT_CFQ is not set
131# CONFIG_DEFAULT_NOOP is not set
132CONFIG_DEFAULT_IOSCHED="anticipatory"
133CONFIG_FREEZER=y
134
135#
136# System type
137#
138CONFIG_CPU_SH4=y
139CONFIG_CPU_SH4A=y
140# CONFIG_CPU_SUBTYPE_SH7619 is not set
141# CONFIG_CPU_SUBTYPE_SH7201 is not set
142# CONFIG_CPU_SUBTYPE_SH7203 is not set
143# CONFIG_CPU_SUBTYPE_SH7206 is not set
144# CONFIG_CPU_SUBTYPE_SH7263 is not set
145# CONFIG_CPU_SUBTYPE_MXG is not set
146# CONFIG_CPU_SUBTYPE_SH7705 is not set
147# CONFIG_CPU_SUBTYPE_SH7706 is not set
148# CONFIG_CPU_SUBTYPE_SH7707 is not set
149# CONFIG_CPU_SUBTYPE_SH7708 is not set
150# CONFIG_CPU_SUBTYPE_SH7709 is not set
151# CONFIG_CPU_SUBTYPE_SH7710 is not set
152# CONFIG_CPU_SUBTYPE_SH7712 is not set
153# CONFIG_CPU_SUBTYPE_SH7720 is not set
154# CONFIG_CPU_SUBTYPE_SH7721 is not set
155# CONFIG_CPU_SUBTYPE_SH7750 is not set
156# CONFIG_CPU_SUBTYPE_SH7091 is not set
157# CONFIG_CPU_SUBTYPE_SH7750R is not set
158# CONFIG_CPU_SUBTYPE_SH7750S is not set
159# CONFIG_CPU_SUBTYPE_SH7751 is not set
160# CONFIG_CPU_SUBTYPE_SH7751R is not set
161# CONFIG_CPU_SUBTYPE_SH7760 is not set
162# CONFIG_CPU_SUBTYPE_SH4_202 is not set
163# CONFIG_CPU_SUBTYPE_SH7723 is not set
164# CONFIG_CPU_SUBTYPE_SH7724 is not set
165# CONFIG_CPU_SUBTYPE_SH7763 is not set
166CONFIG_CPU_SUBTYPE_SH7770=y
167# CONFIG_CPU_SUBTYPE_SH7780 is not set
168# CONFIG_CPU_SUBTYPE_SH7785 is not set
169# CONFIG_CPU_SUBTYPE_SH7786 is not set
170# CONFIG_CPU_SUBTYPE_SHX3 is not set
171# CONFIG_CPU_SUBTYPE_SH7343 is not set
172# CONFIG_CPU_SUBTYPE_SH7722 is not set
173# CONFIG_CPU_SUBTYPE_SH7366 is not set
174
175#
176# Memory management options
177#
178CONFIG_QUICKLIST=y
179CONFIG_MMU=y
180CONFIG_PAGE_OFFSET=0x80000000
181CONFIG_MEMORY_START=0x08000000
182CONFIG_MEMORY_SIZE=0x04000000
183CONFIG_29BIT=y
184CONFIG_VSYSCALL=y
185CONFIG_ARCH_FLATMEM_ENABLE=y
186CONFIG_ARCH_SPARSEMEM_ENABLE=y
187CONFIG_ARCH_SPARSEMEM_DEFAULT=y
188CONFIG_MAX_ACTIVE_REGIONS=1
189CONFIG_ARCH_POPULATES_NODE_MAP=y
190CONFIG_ARCH_SELECT_MEMORY_MODEL=y
191CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
192CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
193CONFIG_PAGE_SIZE_4KB=y
194# CONFIG_PAGE_SIZE_8KB is not set
195# CONFIG_PAGE_SIZE_16KB is not set
196# CONFIG_PAGE_SIZE_64KB is not set
197CONFIG_SELECT_MEMORY_MODEL=y
198# CONFIG_FLATMEM_MANUAL is not set
199# CONFIG_DISCONTIGMEM_MANUAL is not set
200CONFIG_SPARSEMEM_MANUAL=y
201CONFIG_SPARSEMEM=y
202CONFIG_HAVE_MEMORY_PRESENT=y
203CONFIG_SPARSEMEM_STATIC=y
204
205#
206# Memory hotplug is currently incompatible with Software Suspend
207#
208CONFIG_PAGEFLAGS_EXTENDED=y
209CONFIG_SPLIT_PTLOCK_CPUS=4
210CONFIG_MIGRATION=y
211# CONFIG_PHYS_ADDR_T_64BIT is not set
212CONFIG_ZONE_DMA_FLAG=0
213CONFIG_NR_QUICK=2
214CONFIG_UNEVICTABLE_LRU=y
215CONFIG_HAVE_MLOCK=y
216CONFIG_HAVE_MLOCKED_PAGE_BIT=y
217
218#
219# Cache configuration
220#
221CONFIG_CACHE_WRITEBACK=y
222# CONFIG_CACHE_WRITETHROUGH is not set
223# CONFIG_CACHE_OFF is not set
224
225#
226# Processor features
227#
228CONFIG_CPU_LITTLE_ENDIAN=y
229# CONFIG_CPU_BIG_ENDIAN is not set
230CONFIG_SH_FPU=y
231# CONFIG_SH_STORE_QUEUES is not set
232CONFIG_CPU_HAS_INTEVT=y
233CONFIG_CPU_HAS_SR_RB=y
234CONFIG_CPU_HAS_FPU=y
235
236#
237# Board support
238#
239
240#
241# Timer and clock configuration
242#
243CONFIG_SH_TMU=y
244CONFIG_SH_TIMER_IRQ=16
245CONFIG_SH_PCLK_FREQ=41666666
246CONFIG_TICK_ONESHOT=y
247CONFIG_NO_HZ=y
248CONFIG_HIGH_RES_TIMERS=y
249CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
250
251#
252# CPU Frequency scaling
253#
254CONFIG_CPU_FREQ=y
255CONFIG_CPU_FREQ_TABLE=y
256# CONFIG_CPU_FREQ_DEBUG is not set
257CONFIG_CPU_FREQ_STAT=y
258# CONFIG_CPU_FREQ_STAT_DETAILS is not set
259CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
260# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
261# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
262# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
263# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
264CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
265# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
266# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
267# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
268# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
269CONFIG_SH_CPU_FREQ=y
270
271#
272# DMA support
273#
274# CONFIG_SH_DMA is not set
275
276#
277# Companion Chips
278#
279
280#
281# Additional SuperH Device Drivers
282#
283# CONFIG_HEARTBEAT is not set
284# CONFIG_PUSH_SWITCH is not set
285
286#
287# Kernel features
288#
289# CONFIG_HZ_100 is not set
290CONFIG_HZ_250=y
291# CONFIG_HZ_300 is not set
292# CONFIG_HZ_1000 is not set
293CONFIG_HZ=250
294CONFIG_SCHED_HRTICK=y
295CONFIG_KEXEC=y
296# CONFIG_CRASH_DUMP is not set
297CONFIG_KEXEC_JUMP=y
298CONFIG_PREEMPT_NONE=y
299# CONFIG_PREEMPT_VOLUNTARY is not set
300# CONFIG_PREEMPT is not set
301CONFIG_GUSA=y
302
303#
304# Boot options
305#
306CONFIG_ZERO_PAGE_OFFSET=0x00001000
307CONFIG_BOOT_LINK_OFFSET=0x00800000
308CONFIG_ENTRY_OFFSET=0x00001000
309# CONFIG_CMDLINE_BOOL is not set
310
311#
312# Bus options
313#
314# CONFIG_ARCH_SUPPORTS_MSI is not set
315# CONFIG_PCCARD is not set
316
317#
318# Executable file formats
319#
320CONFIG_BINFMT_ELF=y
321# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
322# CONFIG_HAVE_AOUT is not set
323# CONFIG_BINFMT_MISC is not set
324
325#
326# Power management options (EXPERIMENTAL)
327#
328CONFIG_PM=y
329# CONFIG_PM_DEBUG is not set
330CONFIG_PM_SLEEP=y
331CONFIG_HIBERNATION=y
332CONFIG_PM_STD_PARTITION=""
333CONFIG_CPU_IDLE=y
334CONFIG_CPU_IDLE_GOV_LADDER=y
335CONFIG_CPU_IDLE_GOV_MENU=y
336# CONFIG_NET is not set
337
338#
339# Device Drivers
340#
341
342#
343# Generic Driver Options
344#
345CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
346CONFIG_STANDALONE=y
347# CONFIG_PREVENT_FIRMWARE_BUILD is not set
348CONFIG_FW_LOADER=y
349CONFIG_FIRMWARE_IN_KERNEL=y
350CONFIG_EXTRA_FIRMWARE=""
351# CONFIG_SYS_HYPERVISOR is not set
352# CONFIG_MTD is not set
353# CONFIG_PARPORT is not set
354CONFIG_BLK_DEV=y
355# CONFIG_BLK_DEV_COW_COMMON is not set
356# CONFIG_BLK_DEV_LOOP is not set
357# CONFIG_BLK_DEV_RAM is not set
358# CONFIG_CDROM_PKTCDVD is not set
359# CONFIG_BLK_DEV_HD is not set
360# CONFIG_MISC_DEVICES is not set
361CONFIG_HAVE_IDE=y
362# CONFIG_IDE is not set
363
364#
365# SCSI device support
366#
367# CONFIG_RAID_ATTRS is not set
368# CONFIG_SCSI is not set
369# CONFIG_SCSI_DMA is not set
370# CONFIG_SCSI_NETLINK is not set
371# CONFIG_ATA is not set
372# CONFIG_MD is not set
373# CONFIG_PHONE is not set
374
375#
376# Input device support
377#
378# CONFIG_INPUT is not set
379
380#
381# Hardware I/O ports
382#
383# CONFIG_SERIO is not set
384# CONFIG_GAMEPORT is not set
385
386#
387# Character devices
388#
389# CONFIG_VT is not set
390# CONFIG_DEVKMEM is not set
391# CONFIG_SERIAL_NONSTANDARD is not set
392
393#
394# Serial drivers
395#
396# CONFIG_SERIAL_8250 is not set
397
398#
399# Non-8250 serial port support
400#
401CONFIG_SERIAL_SH_SCI=y
402CONFIG_SERIAL_SH_SCI_NR_UARTS=6
403CONFIG_SERIAL_SH_SCI_CONSOLE=y
404CONFIG_SERIAL_CORE=y
405CONFIG_SERIAL_CORE_CONSOLE=y
406# CONFIG_UNIX98_PTYS is not set
407# CONFIG_LEGACY_PTYS is not set
408# CONFIG_IPMI_HANDLER is not set
409# CONFIG_HW_RANDOM is not set
410# CONFIG_R3964 is not set
411# CONFIG_RAW_DRIVER is not set
412# CONFIG_TCG_TPM is not set
413CONFIG_I2C=y
414CONFIG_I2C_BOARDINFO=y
415CONFIG_I2C_CHARDEV=y
416CONFIG_I2C_HELPER_AUTO=y
417
418#
419# I2C Hardware Bus support
420#
421
422#
423# I2C system bus drivers (mostly embedded / system-on-chip)
424#
425# CONFIG_I2C_OCORES is not set
426CONFIG_I2C_SH_MOBILE=y
427# CONFIG_I2C_SIMTEC is not set
428
429#
430# External I2C/SMBus adapter drivers
431#
432# CONFIG_I2C_PARPORT_LIGHT is not set
433# CONFIG_I2C_TAOS_EVM is not set
434
435#
436# Other I2C/SMBus bus drivers
437#
438# CONFIG_I2C_PCA_PLATFORM is not set
439
440#
441# Miscellaneous I2C Chip support
442#
443# CONFIG_DS1682 is not set
444# CONFIG_SENSORS_PCF8574 is not set
445# CONFIG_PCF8575 is not set
446# CONFIG_SENSORS_PCA9539 is not set
447# CONFIG_SENSORS_MAX6875 is not set
448# CONFIG_SENSORS_TSL2550 is not set
449# CONFIG_I2C_DEBUG_CORE is not set
450# CONFIG_I2C_DEBUG_ALGO is not set
451# CONFIG_I2C_DEBUG_BUS is not set
452# CONFIG_I2C_DEBUG_CHIP is not set
453# CONFIG_SPI is not set
454# CONFIG_W1 is not set
455# CONFIG_POWER_SUPPLY is not set
456# CONFIG_HWMON is not set
457# CONFIG_THERMAL is not set
458# CONFIG_THERMAL_HWMON is not set
459# CONFIG_WATCHDOG is not set
460CONFIG_SSB_POSSIBLE=y
461
462#
463# Sonics Silicon Backplane
464#
465# CONFIG_SSB is not set
466
467#
468# Multifunction device drivers
469#
470# CONFIG_MFD_CORE is not set
471# CONFIG_MFD_SM501 is not set
472# CONFIG_HTC_PASIC3 is not set
473# CONFIG_TWL4030_CORE is not set
474# CONFIG_MFD_TMIO is not set
475# CONFIG_PMIC_DA903X is not set
476# CONFIG_MFD_WM8400 is not set
477# CONFIG_MFD_WM8350_I2C is not set
478# CONFIG_MFD_PCF50633 is not set
479# CONFIG_REGULATOR is not set
480
481#
482# Multimedia devices
483#
484
485#
486# Multimedia core support
487#
488# CONFIG_VIDEO_DEV is not set
489# CONFIG_VIDEO_MEDIA is not set
490
491#
492# Multimedia drivers
493#
494# CONFIG_DAB is not set
495
496#
497# Graphics support
498#
499# CONFIG_VGASTATE is not set
500# CONFIG_VIDEO_OUTPUT_CONTROL is not set
501# CONFIG_FB is not set
502# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
503
504#
505# Display device support
506#
507# CONFIG_DISPLAY_SUPPORT is not set
508# CONFIG_SOUND is not set
509# CONFIG_USB_SUPPORT is not set
510# CONFIG_MMC is not set
511# CONFIG_MEMSTICK is not set
512# CONFIG_NEW_LEDS is not set
513# CONFIG_ACCESSIBILITY is not set
514CONFIG_RTC_LIB=y
515CONFIG_RTC_CLASS=y
516CONFIG_RTC_HCTOSYS=y
517CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
518# CONFIG_RTC_DEBUG is not set
519
520#
521# RTC interfaces
522#
523CONFIG_RTC_INTF_DEV=y
524# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
525# CONFIG_RTC_DRV_TEST is not set
526
527#
528# I2C RTC drivers
529#
530# CONFIG_RTC_DRV_DS1307 is not set
531# CONFIG_RTC_DRV_DS1374 is not set
532# CONFIG_RTC_DRV_DS1672 is not set
533# CONFIG_RTC_DRV_MAX6900 is not set
534# CONFIG_RTC_DRV_RS5C372 is not set
535# CONFIG_RTC_DRV_ISL1208 is not set
536# CONFIG_RTC_DRV_X1205 is not set
537# CONFIG_RTC_DRV_PCF8563 is not set
538# CONFIG_RTC_DRV_PCF8583 is not set
539# CONFIG_RTC_DRV_M41T80 is not set
540# CONFIG_RTC_DRV_S35390A is not set
541# CONFIG_RTC_DRV_FM3130 is not set
542# CONFIG_RTC_DRV_RX8581 is not set
543
544#
545# SPI RTC drivers
546#
547
548#
549# Platform RTC drivers
550#
551# CONFIG_RTC_DRV_DS1286 is not set
552# CONFIG_RTC_DRV_DS1511 is not set
553# CONFIG_RTC_DRV_DS1553 is not set
554# CONFIG_RTC_DRV_DS1742 is not set
555# CONFIG_RTC_DRV_STK17TA8 is not set
556# CONFIG_RTC_DRV_M48T86 is not set
557# CONFIG_RTC_DRV_M48T35 is not set
558# CONFIG_RTC_DRV_M48T59 is not set
559# CONFIG_RTC_DRV_BQ4802 is not set
560# CONFIG_RTC_DRV_V3020 is not set
561
562#
563# on-CPU RTC drivers
564#
565CONFIG_RTC_DRV_SH=y
566# CONFIG_RTC_DRV_GENERIC is not set
567# CONFIG_DMADEVICES is not set
568# CONFIG_AUXDISPLAY is not set
569CONFIG_UIO=y
570# CONFIG_UIO_PDRV is not set
571CONFIG_UIO_PDRV_GENIRQ=y
572# CONFIG_UIO_SMX is not set
573# CONFIG_UIO_SERCOS3 is not set
574# CONFIG_STAGING is not set
575
576#
577# File systems
578#
579# CONFIG_EXT2_FS is not set
580# CONFIG_EXT3_FS is not set
581# CONFIG_EXT4_FS is not set
582# CONFIG_REISERFS_FS is not set
583# CONFIG_JFS_FS is not set
584# CONFIG_FS_POSIX_ACL is not set
585CONFIG_FILE_LOCKING=y
586# CONFIG_XFS_FS is not set
587# CONFIG_BTRFS_FS is not set
588# CONFIG_DNOTIFY is not set
589# CONFIG_INOTIFY is not set
590# CONFIG_QUOTA is not set
591# CONFIG_AUTOFS_FS is not set
592# CONFIG_AUTOFS4_FS is not set
593# CONFIG_FUSE_FS is not set
594
595#
596# Caches
597#
598# CONFIG_FSCACHE is not set
599
600#
601# CD-ROM/DVD Filesystems
602#
603# CONFIG_ISO9660_FS is not set
604# CONFIG_UDF_FS is not set
605
606#
607# DOS/FAT/NT Filesystems
608#
609# CONFIG_MSDOS_FS is not set
610# CONFIG_VFAT_FS is not set
611# CONFIG_NTFS_FS is not set
612
613#
614# Pseudo filesystems
615#
616# CONFIG_PROC_FS is not set
617# CONFIG_SYSFS is not set
618# CONFIG_TMPFS is not set
619# CONFIG_HUGETLBFS is not set
620# CONFIG_HUGETLB_PAGE is not set
621# CONFIG_MISC_FILESYSTEMS is not set
622
623#
624# Partition Types
625#
626# CONFIG_PARTITION_ADVANCED is not set
627CONFIG_MSDOS_PARTITION=y
628# CONFIG_NLS is not set
629
630#
631# Kernel hacking
632#
633CONFIG_TRACE_IRQFLAGS_SUPPORT=y
634# CONFIG_PRINTK_TIME is not set
635# CONFIG_ENABLE_WARN_DEPRECATED is not set
636# CONFIG_ENABLE_MUST_CHECK is not set
637CONFIG_FRAME_WARN=1024
638# CONFIG_MAGIC_SYSRQ is not set
639# CONFIG_UNUSED_SYMBOLS is not set
640CONFIG_DEBUG_FS=y
641# CONFIG_HEADERS_CHECK is not set
642# CONFIG_DEBUG_KERNEL is not set
643CONFIG_STACKTRACE=y
644# CONFIG_DEBUG_BUGVERBOSE is not set
645# CONFIG_DEBUG_MEMORY_INIT is not set
646# CONFIG_RCU_CPU_STALL_DETECTOR is not set
647# CONFIG_LATENCYTOP is not set
648# CONFIG_SYSCTL_SYSCALL_CHECK is not set
649CONFIG_NOP_TRACER=y
650CONFIG_HAVE_FUNCTION_TRACER=y
651CONFIG_HAVE_DYNAMIC_FTRACE=y
652CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
653CONFIG_RING_BUFFER=y
654CONFIG_TRACING=y
655CONFIG_TRACING_SUPPORT=y
656
657#
658# Tracers
659#
660# CONFIG_FUNCTION_TRACER is not set
661# CONFIG_IRQSOFF_TRACER is not set
662# CONFIG_SCHED_TRACER is not set
663# CONFIG_CONTEXT_SWITCH_TRACER is not set
664# CONFIG_EVENT_TRACER is not set
665# CONFIG_BOOT_TRACER is not set
666# CONFIG_TRACE_BRANCH_PROFILING is not set
667# CONFIG_STACK_TRACER is not set
668# CONFIG_KMEMTRACE is not set
669# CONFIG_WORKQUEUE_TRACER is not set
670# CONFIG_FTRACE_STARTUP_TEST is not set
671# CONFIG_DYNAMIC_DEBUG is not set
672# CONFIG_DMA_API_DEBUG is not set
673# CONFIG_SAMPLES is not set
674CONFIG_HAVE_ARCH_KGDB=y
675# CONFIG_SH_STANDARD_BIOS is not set
676# CONFIG_EARLY_SCIF_CONSOLE is not set
677
678#
679# Security options
680#
681# CONFIG_KEYS is not set
682# CONFIG_SECURITYFS is not set
683# CONFIG_SECURITY_FILE_CAPABILITIES is not set
684# CONFIG_CRYPTO is not set
685CONFIG_BINARY_PRINTF=y
686
687#
688# Library routines
689#
690CONFIG_GENERIC_FIND_LAST_BIT=y
691# CONFIG_CRC_CCITT is not set
692# CONFIG_CRC16 is not set
693# CONFIG_CRC_T10DIF is not set
694# CONFIG_CRC_ITU_T is not set
695# CONFIG_CRC32 is not set
696# CONFIG_CRC7 is not set
697# CONFIG_LIBCRC32C is not set
698CONFIG_HAS_IOMEM=y
699CONFIG_HAS_IOPORT=y
700CONFIG_HAS_DMA=y
diff --git a/arch/sh/configs/sh7785lcr_32bit_defconfig b/arch/sh/configs/sh7785lcr_32bit_defconfig
index a6cf4505741c..1c55b800d124 100644
--- a/arch/sh/configs/sh7785lcr_32bit_defconfig
+++ b/arch/sh/configs/sh7785lcr_32bit_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 19:12:18 2009 4# Mon Apr 27 13:10:53 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -79,6 +80,7 @@ CONFIG_SYSCTL_SYSCALL=y
79CONFIG_KALLSYMS=y 80CONFIG_KALLSYMS=y
80# CONFIG_KALLSYMS_ALL is not set 81# CONFIG_KALLSYMS_ALL is not set
81# CONFIG_KALLSYMS_EXTRA_PASS is not set 82# CONFIG_KALLSYMS_EXTRA_PASS is not set
83# CONFIG_STRIP_ASM_SYMS is not set
82CONFIG_HOTPLUG=y 84CONFIG_HOTPLUG=y
83CONFIG_PRINTK=y 85CONFIG_PRINTK=y
84CONFIG_BUG=y 86CONFIG_BUG=y
@@ -98,6 +100,7 @@ CONFIG_SLAB=y
98# CONFIG_SLUB is not set 100# CONFIG_SLUB is not set
99# CONFIG_SLOB is not set 101# CONFIG_SLOB is not set
100CONFIG_PROFILING=y 102CONFIG_PROFILING=y
103# CONFIG_MARKERS is not set
101# CONFIG_OPROFILE is not set 104# CONFIG_OPROFILE is not set
102CONFIG_HAVE_OPROFILE=y 105CONFIG_HAVE_OPROFILE=y
103# CONFIG_KPROBES is not set 106# CONFIG_KPROBES is not set
@@ -106,6 +109,8 @@ CONFIG_HAVE_KPROBES=y
106CONFIG_HAVE_KRETPROBES=y 109CONFIG_HAVE_KRETPROBES=y
107CONFIG_HAVE_ARCH_TRACEHOOK=y 110CONFIG_HAVE_ARCH_TRACEHOOK=y
108CONFIG_HAVE_CLK=y 111CONFIG_HAVE_CLK=y
112CONFIG_HAVE_DMA_API_DEBUG=y
113# CONFIG_SLOW_WORK is not set
109CONFIG_HAVE_GENERIC_DMA_COHERENT=y 114CONFIG_HAVE_GENERIC_DMA_COHERENT=y
110CONFIG_SLABINFO=y 115CONFIG_SLABINFO=y
111CONFIG_RT_MUTEXES=y 116CONFIG_RT_MUTEXES=y
@@ -118,7 +123,6 @@ CONFIG_MODULE_UNLOAD=y
118# CONFIG_MODULE_SRCVERSION_ALL is not set 123# CONFIG_MODULE_SRCVERSION_ALL is not set
119CONFIG_BLOCK=y 124CONFIG_BLOCK=y
120# CONFIG_LBD is not set 125# CONFIG_LBD is not set
121# CONFIG_BLK_DEV_IO_TRACE is not set
122# CONFIG_BLK_DEV_BSG is not set 126# CONFIG_BLK_DEV_BSG is not set
123# CONFIG_BLK_DEV_INTEGRITY is not set 127# CONFIG_BLK_DEV_INTEGRITY is not set
124 128
@@ -166,6 +170,7 @@ CONFIG_CPU_SHX2=y
166# CONFIG_CPU_SUBTYPE_SH7760 is not set 170# CONFIG_CPU_SUBTYPE_SH7760 is not set
167# CONFIG_CPU_SUBTYPE_SH4_202 is not set 171# CONFIG_CPU_SUBTYPE_SH4_202 is not set
168# CONFIG_CPU_SUBTYPE_SH7723 is not set 172# CONFIG_CPU_SUBTYPE_SH7723 is not set
173# CONFIG_CPU_SUBTYPE_SH7724 is not set
169# CONFIG_CPU_SUBTYPE_SH7763 is not set 174# CONFIG_CPU_SUBTYPE_SH7763 is not set
170# CONFIG_CPU_SUBTYPE_SH7770 is not set 175# CONFIG_CPU_SUBTYPE_SH7770 is not set
171# CONFIG_CPU_SUBTYPE_SH7780 is not set 176# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -175,8 +180,6 @@ CONFIG_CPU_SUBTYPE_SH7785=y
175# CONFIG_CPU_SUBTYPE_SH7343 is not set 180# CONFIG_CPU_SUBTYPE_SH7343 is not set
176# CONFIG_CPU_SUBTYPE_SH7722 is not set 181# CONFIG_CPU_SUBTYPE_SH7722 is not set
177# CONFIG_CPU_SUBTYPE_SH7366 is not set 182# CONFIG_CPU_SUBTYPE_SH7366 is not set
178# CONFIG_CPU_SUBTYPE_SH5_101 is not set
179# CONFIG_CPU_SUBTYPE_SH5_103 is not set
180 183
181# 184#
182# Memory management options 185# Memory management options
@@ -310,8 +313,6 @@ CONFIG_BOOT_LINK_OFFSET=0x00800000
310# 313#
311CONFIG_PCI=y 314CONFIG_PCI=y
312CONFIG_SH_PCIDMA_NONCOHERENT=y 315CONFIG_SH_PCIDMA_NONCOHERENT=y
313CONFIG_PCI_AUTO=y
314CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
315# CONFIG_PCIEPORTBUS is not set 316# CONFIG_PCIEPORTBUS is not set
316# CONFIG_ARCH_SUPPORTS_MSI is not set 317# CONFIG_ARCH_SUPPORTS_MSI is not set
317CONFIG_PCI_LEGACY=y 318CONFIG_PCI_LEGACY=y
@@ -672,6 +673,7 @@ CONFIG_NETDEV_1000=y
672# CONFIG_E1000E is not set 673# CONFIG_E1000E is not set
673# CONFIG_IP1000 is not set 674# CONFIG_IP1000 is not set
674# CONFIG_IGB is not set 675# CONFIG_IGB is not set
676# CONFIG_IGBVF is not set
675# CONFIG_NS83820 is not set 677# CONFIG_NS83820 is not set
676# CONFIG_HAMACHI is not set 678# CONFIG_HAMACHI is not set
677# CONFIG_YELLOWFIN is not set 679# CONFIG_YELLOWFIN is not set
@@ -1009,15 +1011,17 @@ CONFIG_USB_HID=y
1009# 1011#
1010# Special HID drivers 1012# Special HID drivers
1011# 1013#
1012CONFIG_HID_COMPAT=y
1013CONFIG_HID_A4TECH=y 1014CONFIG_HID_A4TECH=y
1014CONFIG_HID_APPLE=y 1015CONFIG_HID_APPLE=y
1015CONFIG_HID_BELKIN=y 1016CONFIG_HID_BELKIN=y
1016CONFIG_HID_CHERRY=y 1017CONFIG_HID_CHERRY=y
1017CONFIG_HID_CHICONY=y 1018CONFIG_HID_CHICONY=y
1018CONFIG_HID_CYPRESS=y 1019CONFIG_HID_CYPRESS=y
1020# CONFIG_DRAGONRISE_FF is not set
1019CONFIG_HID_EZKEY=y 1021CONFIG_HID_EZKEY=y
1022# CONFIG_HID_KYE is not set
1020CONFIG_HID_GYRATION=y 1023CONFIG_HID_GYRATION=y
1024# CONFIG_HID_KENSINGTON is not set
1021CONFIG_HID_LOGITECH=y 1025CONFIG_HID_LOGITECH=y
1022# CONFIG_LOGITECH_FF is not set 1026# CONFIG_LOGITECH_FF is not set
1023# CONFIG_LOGIRUMBLEPAD2_FF is not set 1027# CONFIG_LOGIRUMBLEPAD2_FF is not set
@@ -1218,6 +1222,7 @@ CONFIG_EXT2_FS=y
1218# CONFIG_EXT2_FS_XATTR is not set 1222# CONFIG_EXT2_FS_XATTR is not set
1219# CONFIG_EXT2_FS_XIP is not set 1223# CONFIG_EXT2_FS_XIP is not set
1220CONFIG_EXT3_FS=y 1224CONFIG_EXT3_FS=y
1225# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1221CONFIG_EXT3_FS_XATTR=y 1226CONFIG_EXT3_FS_XATTR=y
1222# CONFIG_EXT3_FS_POSIX_ACL is not set 1227# CONFIG_EXT3_FS_POSIX_ACL is not set
1223# CONFIG_EXT3_FS_SECURITY is not set 1228# CONFIG_EXT3_FS_SECURITY is not set
@@ -1240,6 +1245,11 @@ CONFIG_INOTIFY_USER=y
1240# CONFIG_FUSE_FS is not set 1245# CONFIG_FUSE_FS is not set
1241 1246
1242# 1247#
1248# Caches
1249#
1250# CONFIG_FSCACHE is not set
1251
1252#
1243# CD-ROM/DVD Filesystems 1253# CD-ROM/DVD Filesystems
1244# 1254#
1245# CONFIG_ISO9660_FS is not set 1255# CONFIG_ISO9660_FS is not set
@@ -1289,6 +1299,7 @@ CONFIG_MINIX_FS=y
1289# CONFIG_ROMFS_FS is not set 1299# CONFIG_ROMFS_FS is not set
1290# CONFIG_SYSV_FS is not set 1300# CONFIG_SYSV_FS is not set
1291# CONFIG_UFS_FS is not set 1301# CONFIG_UFS_FS is not set
1302# CONFIG_NILFS2_FS is not set
1292CONFIG_NETWORK_FILESYSTEMS=y 1303CONFIG_NETWORK_FILESYSTEMS=y
1293CONFIG_NFS_FS=y 1304CONFIG_NFS_FS=y
1294CONFIG_NFS_V3=y 1305CONFIG_NFS_V3=y
@@ -1377,6 +1388,9 @@ CONFIG_DEBUG_KERNEL=y
1377CONFIG_DETECT_SOFTLOCKUP=y 1388CONFIG_DETECT_SOFTLOCKUP=y
1378# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set 1389# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1379CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 1390CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1391CONFIG_DETECT_HUNG_TASK=y
1392# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1393CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1380CONFIG_SCHED_DEBUG=y 1394CONFIG_SCHED_DEBUG=y
1381# CONFIG_SCHEDSTATS is not set 1395# CONFIG_SCHEDSTATS is not set
1382# CONFIG_TIMER_STATS is not set 1396# CONFIG_TIMER_STATS is not set
@@ -1413,6 +1427,7 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
1413CONFIG_HAVE_FUNCTION_TRACER=y 1427CONFIG_HAVE_FUNCTION_TRACER=y
1414CONFIG_HAVE_DYNAMIC_FTRACE=y 1428CONFIG_HAVE_DYNAMIC_FTRACE=y
1415CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1429CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1430CONFIG_TRACING_SUPPORT=y
1416 1431
1417# 1432#
1418# Tracers 1433# Tracers
@@ -1422,9 +1437,14 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1422# CONFIG_PREEMPT_TRACER is not set 1437# CONFIG_PREEMPT_TRACER is not set
1423# CONFIG_SCHED_TRACER is not set 1438# CONFIG_SCHED_TRACER is not set
1424# CONFIG_CONTEXT_SWITCH_TRACER is not set 1439# CONFIG_CONTEXT_SWITCH_TRACER is not set
1440# CONFIG_EVENT_TRACER is not set
1425# CONFIG_BOOT_TRACER is not set 1441# CONFIG_BOOT_TRACER is not set
1426# CONFIG_TRACE_BRANCH_PROFILING is not set 1442# CONFIG_TRACE_BRANCH_PROFILING is not set
1427# CONFIG_STACK_TRACER is not set 1443# CONFIG_STACK_TRACER is not set
1444# CONFIG_KMEMTRACE is not set
1445# CONFIG_WORKQUEUE_TRACER is not set
1446# CONFIG_BLK_DEV_IO_TRACE is not set
1447# CONFIG_DMA_API_DEBUG is not set
1428# CONFIG_SAMPLES is not set 1448# CONFIG_SAMPLES is not set
1429CONFIG_HAVE_ARCH_KGDB=y 1449CONFIG_HAVE_ARCH_KGDB=y
1430# CONFIG_KGDB is not set 1450# CONFIG_KGDB is not set
@@ -1542,6 +1562,7 @@ CONFIG_CRYPTO_DES=y
1542# 1562#
1543# CONFIG_CRYPTO_ANSI_CPRNG is not set 1563# CONFIG_CRYPTO_ANSI_CPRNG is not set
1544# CONFIG_CRYPTO_HW is not set 1564# CONFIG_CRYPTO_HW is not set
1565# CONFIG_BINARY_PRINTF is not set
1545 1566
1546# 1567#
1547# Library routines 1568# Library routines
diff --git a/arch/sh/configs/sh7785lcr_defconfig b/arch/sh/configs/sh7785lcr_defconfig
index e4fac2efc055..4385fe97a780 100644
--- a/arch/sh/configs/sh7785lcr_defconfig
+++ b/arch/sh/configs/sh7785lcr_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.30-rc2 3# Linux kernel version: 2.6.30-rc3
4# Wed Apr 22 19:17:56 2009 4# Mon Apr 27 13:11:48 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
@@ -307,8 +307,6 @@ CONFIG_BOOT_LINK_OFFSET=0x00800000
307# 307#
308CONFIG_PCI=y 308CONFIG_PCI=y
309CONFIG_SH_PCIDMA_NONCOHERENT=y 309CONFIG_SH_PCIDMA_NONCOHERENT=y
310CONFIG_PCI_AUTO=y
311CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
312# CONFIG_PCIEPORTBUS is not set 310# CONFIG_PCIEPORTBUS is not set
313# CONFIG_ARCH_SUPPORTS_MSI is not set 311# CONFIG_ARCH_SUPPORTS_MSI is not set
314CONFIG_PCI_LEGACY=y 312CONFIG_PCI_LEGACY=y
diff --git a/arch/sh/configs/shmin_defconfig b/arch/sh/configs/shmin_defconfig
index d695e9061874..4e120256ec63 100644
--- a/arch/sh/configs/shmin_defconfig
+++ b/arch/sh/configs/shmin_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 19:19:03 2009 4# Mon Apr 27 13:12:41 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_FIND_NEXT_BIT=y 11CONFIG_GENERIC_FIND_NEXT_BIT=y
@@ -63,6 +64,7 @@ CONFIG_EMBEDDED=y
63# CONFIG_UID16 is not set 64# CONFIG_UID16 is not set
64# CONFIG_SYSCTL_SYSCALL is not set 65# CONFIG_SYSCTL_SYSCALL is not set
65# CONFIG_KALLSYMS is not set 66# CONFIG_KALLSYMS is not set
67# CONFIG_STRIP_ASM_SYMS is not set
66# CONFIG_HOTPLUG is not set 68# CONFIG_HOTPLUG is not set
67CONFIG_PRINTK=y 69CONFIG_PRINTK=y
68# CONFIG_BUG is not set 70# CONFIG_BUG is not set
@@ -81,12 +83,15 @@ CONFIG_COMPAT_BRK=y
81# CONFIG_SLUB is not set 83# CONFIG_SLUB is not set
82CONFIG_SLOB=y 84CONFIG_SLOB=y
83# CONFIG_PROFILING is not set 85# CONFIG_PROFILING is not set
86# CONFIG_MARKERS is not set
84CONFIG_HAVE_OPROFILE=y 87CONFIG_HAVE_OPROFILE=y
85CONFIG_HAVE_IOREMAP_PROT=y 88CONFIG_HAVE_IOREMAP_PROT=y
86CONFIG_HAVE_KPROBES=y 89CONFIG_HAVE_KPROBES=y
87CONFIG_HAVE_KRETPROBES=y 90CONFIG_HAVE_KRETPROBES=y
88CONFIG_HAVE_ARCH_TRACEHOOK=y 91CONFIG_HAVE_ARCH_TRACEHOOK=y
89CONFIG_HAVE_CLK=y 92CONFIG_HAVE_CLK=y
93CONFIG_HAVE_DMA_API_DEBUG=y
94# CONFIG_SLOW_WORK is not set
90CONFIG_HAVE_GENERIC_DMA_COHERENT=y 95CONFIG_HAVE_GENERIC_DMA_COHERENT=y
91CONFIG_BASE_SMALL=1 96CONFIG_BASE_SMALL=1
92# CONFIG_MODULES is not set 97# CONFIG_MODULES is not set
@@ -137,6 +142,7 @@ CONFIG_CPU_SUBTYPE_SH7706=y
137# CONFIG_CPU_SUBTYPE_SH7760 is not set 142# CONFIG_CPU_SUBTYPE_SH7760 is not set
138# CONFIG_CPU_SUBTYPE_SH4_202 is not set 143# CONFIG_CPU_SUBTYPE_SH4_202 is not set
139# CONFIG_CPU_SUBTYPE_SH7723 is not set 144# CONFIG_CPU_SUBTYPE_SH7723 is not set
145# CONFIG_CPU_SUBTYPE_SH7724 is not set
140# CONFIG_CPU_SUBTYPE_SH7763 is not set 146# CONFIG_CPU_SUBTYPE_SH7763 is not set
141# CONFIG_CPU_SUBTYPE_SH7770 is not set 147# CONFIG_CPU_SUBTYPE_SH7770 is not set
142# CONFIG_CPU_SUBTYPE_SH7780 is not set 148# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -146,8 +152,6 @@ CONFIG_CPU_SUBTYPE_SH7706=y
146# CONFIG_CPU_SUBTYPE_SH7343 is not set 152# CONFIG_CPU_SUBTYPE_SH7343 is not set
147# CONFIG_CPU_SUBTYPE_SH7722 is not set 153# CONFIG_CPU_SUBTYPE_SH7722 is not set
148# CONFIG_CPU_SUBTYPE_SH7366 is not set 154# CONFIG_CPU_SUBTYPE_SH7366 is not set
149# CONFIG_CPU_SUBTYPE_SH5_101 is not set
150# CONFIG_CPU_SUBTYPE_SH5_103 is not set
151 155
152# 156#
153# Memory management options 157# Memory management options
@@ -675,6 +679,11 @@ CONFIG_FILE_LOCKING=y
675# CONFIG_FUSE_FS is not set 679# CONFIG_FUSE_FS is not set
676 680
677# 681#
682# Caches
683#
684# CONFIG_FSCACHE is not set
685
686#
678# CD-ROM/DVD Filesystems 687# CD-ROM/DVD Filesystems
679# 688#
680# CONFIG_ISO9660_FS is not set 689# CONFIG_ISO9660_FS is not set
@@ -718,6 +727,7 @@ CONFIG_CRAMFS=y
718# CONFIG_ROMFS_FS is not set 727# CONFIG_ROMFS_FS is not set
719# CONFIG_SYSV_FS is not set 728# CONFIG_SYSV_FS is not set
720# CONFIG_UFS_FS is not set 729# CONFIG_UFS_FS is not set
730# CONFIG_NILFS2_FS is not set
721CONFIG_NETWORK_FILESYSTEMS=y 731CONFIG_NETWORK_FILESYSTEMS=y
722CONFIG_NFS_FS=y 732CONFIG_NFS_FS=y
723CONFIG_NFS_V3=y 733CONFIG_NFS_V3=y
@@ -762,10 +772,22 @@ CONFIG_FRAME_WARN=1024
762CONFIG_HAVE_FUNCTION_TRACER=y 772CONFIG_HAVE_FUNCTION_TRACER=y
763CONFIG_HAVE_DYNAMIC_FTRACE=y 773CONFIG_HAVE_DYNAMIC_FTRACE=y
764CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 774CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
775CONFIG_TRACING_SUPPORT=y
765 776
766# 777#
767# Tracers 778# Tracers
768# 779#
780# CONFIG_FUNCTION_TRACER is not set
781# CONFIG_IRQSOFF_TRACER is not set
782# CONFIG_SCHED_TRACER is not set
783# CONFIG_CONTEXT_SWITCH_TRACER is not set
784# CONFIG_EVENT_TRACER is not set
785# CONFIG_BOOT_TRACER is not set
786# CONFIG_TRACE_BRANCH_PROFILING is not set
787# CONFIG_STACK_TRACER is not set
788# CONFIG_KMEMTRACE is not set
789# CONFIG_WORKQUEUE_TRACER is not set
790# CONFIG_DMA_API_DEBUG is not set
769# CONFIG_SAMPLES is not set 791# CONFIG_SAMPLES is not set
770CONFIG_HAVE_ARCH_KGDB=y 792CONFIG_HAVE_ARCH_KGDB=y
771CONFIG_SH_STANDARD_BIOS=y 793CONFIG_SH_STANDARD_BIOS=y
@@ -864,6 +886,7 @@ CONFIG_CRYPTO=y
864# 886#
865# CONFIG_CRYPTO_ANSI_CPRNG is not set 887# CONFIG_CRYPTO_ANSI_CPRNG is not set
866CONFIG_CRYPTO_HW=y 888CONFIG_CRYPTO_HW=y
889# CONFIG_BINARY_PRINTF is not set
867 890
868# 891#
869# Library routines 892# Library routines
diff --git a/arch/sh/configs/shx3_defconfig b/arch/sh/configs/shx3_defconfig
index e3651f574399..c088144925fa 100644
--- a/arch/sh/configs/shx3_defconfig
+++ b/arch/sh/configs/shx3_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 19:20:54 2009 4# Mon Apr 27 13:13:12 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -42,6 +43,7 @@ CONFIG_SWAP=y
42CONFIG_SYSVIPC=y 43CONFIG_SYSVIPC=y
43CONFIG_SYSVIPC_SYSCTL=y 44CONFIG_SYSVIPC_SYSCTL=y
44CONFIG_POSIX_MQUEUE=y 45CONFIG_POSIX_MQUEUE=y
46CONFIG_POSIX_MQUEUE_SYSCTL=y
45CONFIG_BSD_PROCESS_ACCT=y 47CONFIG_BSD_PROCESS_ACCT=y
46# CONFIG_BSD_PROCESS_ACCT_V3 is not set 48# CONFIG_BSD_PROCESS_ACCT_V3 is not set
47# CONFIG_TASKSTATS is not set 49# CONFIG_TASKSTATS is not set
@@ -96,6 +98,7 @@ CONFIG_SYSCTL_SYSCALL=y
96CONFIG_KALLSYMS=y 98CONFIG_KALLSYMS=y
97CONFIG_KALLSYMS_ALL=y 99CONFIG_KALLSYMS_ALL=y
98# CONFIG_KALLSYMS_EXTRA_PASS is not set 100# CONFIG_KALLSYMS_EXTRA_PASS is not set
101# CONFIG_STRIP_ASM_SYMS is not set
99CONFIG_HOTPLUG=y 102CONFIG_HOTPLUG=y
100CONFIG_PRINTK=y 103CONFIG_PRINTK=y
101CONFIG_BUG=y 104CONFIG_BUG=y
@@ -126,6 +129,8 @@ CONFIG_HAVE_KRETPROBES=y
126CONFIG_HAVE_ARCH_TRACEHOOK=y 129CONFIG_HAVE_ARCH_TRACEHOOK=y
127CONFIG_USE_GENERIC_SMP_HELPERS=y 130CONFIG_USE_GENERIC_SMP_HELPERS=y
128CONFIG_HAVE_CLK=y 131CONFIG_HAVE_CLK=y
132CONFIG_HAVE_DMA_API_DEBUG=y
133# CONFIG_SLOW_WORK is not set
129CONFIG_HAVE_GENERIC_DMA_COHERENT=y 134CONFIG_HAVE_GENERIC_DMA_COHERENT=y
130CONFIG_RT_MUTEXES=y 135CONFIG_RT_MUTEXES=y
131CONFIG_BASE_SMALL=0 136CONFIG_BASE_SMALL=0
@@ -138,7 +143,6 @@ CONFIG_MODULE_UNLOAD=y
138CONFIG_STOP_MACHINE=y 143CONFIG_STOP_MACHINE=y
139CONFIG_BLOCK=y 144CONFIG_BLOCK=y
140# CONFIG_LBD is not set 145# CONFIG_LBD is not set
141# CONFIG_BLK_DEV_IO_TRACE is not set
142# CONFIG_BLK_DEV_BSG is not set 146# CONFIG_BLK_DEV_BSG is not set
143# CONFIG_BLK_DEV_INTEGRITY is not set 147# CONFIG_BLK_DEV_INTEGRITY is not set
144 148
@@ -186,6 +190,7 @@ CONFIG_CPU_SHX3=y
186# CONFIG_CPU_SUBTYPE_SH7760 is not set 190# CONFIG_CPU_SUBTYPE_SH7760 is not set
187# CONFIG_CPU_SUBTYPE_SH4_202 is not set 191# CONFIG_CPU_SUBTYPE_SH4_202 is not set
188# CONFIG_CPU_SUBTYPE_SH7723 is not set 192# CONFIG_CPU_SUBTYPE_SH7723 is not set
193# CONFIG_CPU_SUBTYPE_SH7724 is not set
189# CONFIG_CPU_SUBTYPE_SH7763 is not set 194# CONFIG_CPU_SUBTYPE_SH7763 is not set
190# CONFIG_CPU_SUBTYPE_SH7770 is not set 195# CONFIG_CPU_SUBTYPE_SH7770 is not set
191# CONFIG_CPU_SUBTYPE_SH7780 is not set 196# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -195,8 +200,6 @@ CONFIG_CPU_SUBTYPE_SHX3=y
195# CONFIG_CPU_SUBTYPE_SH7343 is not set 200# CONFIG_CPU_SUBTYPE_SH7343 is not set
196# CONFIG_CPU_SUBTYPE_SH7722 is not set 201# CONFIG_CPU_SUBTYPE_SH7722 is not set
197# CONFIG_CPU_SUBTYPE_SH7366 is not set 202# CONFIG_CPU_SUBTYPE_SH7366 is not set
198# CONFIG_CPU_SUBTYPE_SH5_101 is not set
199# CONFIG_CPU_SUBTYPE_SH5_103 is not set
200 203
201# 204#
202# Memory management options 205# Memory management options
@@ -553,6 +556,7 @@ CONFIG_SCSI_WAIT_SCAN=m
553CONFIG_SCSI_LOWLEVEL=y 556CONFIG_SCSI_LOWLEVEL=y
554# CONFIG_ISCSI_TCP is not set 557# CONFIG_ISCSI_TCP is not set
555# CONFIG_LIBFC is not set 558# CONFIG_LIBFC is not set
559# CONFIG_LIBFCOE is not set
556# CONFIG_SCSI_DEBUG is not set 560# CONFIG_SCSI_DEBUG is not set
557# CONFIG_SCSI_DH is not set 561# CONFIG_SCSI_DH is not set
558# CONFIG_SCSI_OSD_INITIATOR is not set 562# CONFIG_SCSI_OSD_INITIATOR is not set
@@ -646,6 +650,7 @@ CONFIG_DEVKMEM=y
646# 650#
647# Non-8250 serial port support 651# Non-8250 serial port support
648# 652#
653# CONFIG_SERIAL_MAX3100 is not set
649CONFIG_SERIAL_SH_SCI=y 654CONFIG_SERIAL_SH_SCI=y
650CONFIG_SERIAL_SH_SCI_NR_UARTS=2 655CONFIG_SERIAL_SH_SCI_NR_UARTS=2
651CONFIG_SERIAL_SH_SCI_CONSOLE=y 656CONFIG_SERIAL_SH_SCI_CONSOLE=y
@@ -985,6 +990,7 @@ CONFIG_EXT2_FS=y
985# CONFIG_EXT2_FS_XATTR is not set 990# CONFIG_EXT2_FS_XATTR is not set
986# CONFIG_EXT2_FS_XIP is not set 991# CONFIG_EXT2_FS_XIP is not set
987CONFIG_EXT3_FS=y 992CONFIG_EXT3_FS=y
993# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
988CONFIG_EXT3_FS_XATTR=y 994CONFIG_EXT3_FS_XATTR=y
989# CONFIG_EXT3_FS_POSIX_ACL is not set 995# CONFIG_EXT3_FS_POSIX_ACL is not set
990# CONFIG_EXT3_FS_SECURITY is not set 996# CONFIG_EXT3_FS_SECURITY is not set
@@ -1008,6 +1014,11 @@ CONFIG_INOTIFY_USER=y
1008# CONFIG_FUSE_FS is not set 1014# CONFIG_FUSE_FS is not set
1009 1015
1010# 1016#
1017# Caches
1018#
1019# CONFIG_FSCACHE is not set
1020
1021#
1011# CD-ROM/DVD Filesystems 1022# CD-ROM/DVD Filesystems
1012# 1023#
1013# CONFIG_ISO9660_FS is not set 1024# CONFIG_ISO9660_FS is not set
@@ -1051,6 +1062,7 @@ CONFIG_MISC_FILESYSTEMS=y
1051# CONFIG_ROMFS_FS is not set 1062# CONFIG_ROMFS_FS is not set
1052# CONFIG_SYSV_FS is not set 1063# CONFIG_SYSV_FS is not set
1053# CONFIG_UFS_FS is not set 1064# CONFIG_UFS_FS is not set
1065# CONFIG_NILFS2_FS is not set
1054CONFIG_NETWORK_FILESYSTEMS=y 1066CONFIG_NETWORK_FILESYSTEMS=y
1055# CONFIG_NFS_FS is not set 1067# CONFIG_NFS_FS is not set
1056# CONFIG_NFSD is not set 1068# CONFIG_NFSD is not set
@@ -1085,6 +1097,9 @@ CONFIG_DEBUG_SHIRQ=y
1085CONFIG_DETECT_SOFTLOCKUP=y 1097CONFIG_DETECT_SOFTLOCKUP=y
1086# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set 1098# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
1087CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 1099CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
1100CONFIG_DETECT_HUNG_TASK=y
1101# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
1102CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
1088CONFIG_SCHED_DEBUG=y 1103CONFIG_SCHED_DEBUG=y
1089# CONFIG_SCHEDSTATS is not set 1104# CONFIG_SCHEDSTATS is not set
1090# CONFIG_TIMER_STATS is not set 1105# CONFIG_TIMER_STATS is not set
@@ -1124,6 +1139,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE=y
1124CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1139CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1125CONFIG_RING_BUFFER=y 1140CONFIG_RING_BUFFER=y
1126CONFIG_TRACING=y 1141CONFIG_TRACING=y
1142CONFIG_TRACING_SUPPORT=y
1127 1143
1128# 1144#
1129# Tracers 1145# Tracers
@@ -1133,11 +1149,16 @@ CONFIG_TRACING=y
1133# CONFIG_PREEMPT_TRACER is not set 1149# CONFIG_PREEMPT_TRACER is not set
1134# CONFIG_SCHED_TRACER is not set 1150# CONFIG_SCHED_TRACER is not set
1135# CONFIG_CONTEXT_SWITCH_TRACER is not set 1151# CONFIG_CONTEXT_SWITCH_TRACER is not set
1152# CONFIG_EVENT_TRACER is not set
1136# CONFIG_BOOT_TRACER is not set 1153# CONFIG_BOOT_TRACER is not set
1137# CONFIG_TRACE_BRANCH_PROFILING is not set 1154# CONFIG_TRACE_BRANCH_PROFILING is not set
1138# CONFIG_STACK_TRACER is not set 1155# CONFIG_STACK_TRACER is not set
1156# CONFIG_KMEMTRACE is not set
1157# CONFIG_WORKQUEUE_TRACER is not set
1158# CONFIG_BLK_DEV_IO_TRACE is not set
1139# CONFIG_FTRACE_STARTUP_TEST is not set 1159# CONFIG_FTRACE_STARTUP_TEST is not set
1140# CONFIG_DYNAMIC_DEBUG is not set 1160# CONFIG_DYNAMIC_DEBUG is not set
1161# CONFIG_DMA_API_DEBUG is not set
1141# CONFIG_SAMPLES is not set 1162# CONFIG_SAMPLES is not set
1142CONFIG_HAVE_ARCH_KGDB=y 1163CONFIG_HAVE_ARCH_KGDB=y
1143# CONFIG_KGDB is not set 1164# CONFIG_KGDB is not set
@@ -1245,6 +1266,7 @@ CONFIG_CRYPTO=y
1245# 1266#
1246# CONFIG_CRYPTO_ANSI_CPRNG is not set 1267# CONFIG_CRYPTO_ANSI_CPRNG is not set
1247CONFIG_CRYPTO_HW=y 1268CONFIG_CRYPTO_HW=y
1269CONFIG_BINARY_PRINTF=y
1248 1270
1249# 1271#
1250# Library routines 1272# Library routines
diff --git a/arch/sh/configs/snapgear_defconfig b/arch/sh/configs/snapgear_defconfig
index 6960f60bf52e..54a7a3c41f34 100644
--- a/arch/sh/configs/snapgear_defconfig
+++ b/arch/sh/configs/snapgear_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 19:21:39 2009 4# Mon Apr 27 13:14:00 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -64,7 +65,6 @@ CONFIG_INITRAMFS_SOURCE=""
64CONFIG_RD_GZIP=y 65CONFIG_RD_GZIP=y
65# CONFIG_RD_BZIP2 is not set 66# CONFIG_RD_BZIP2 is not set
66# CONFIG_RD_LZMA is not set 67# CONFIG_RD_LZMA is not set
67CONFIG_INITRAMFS_COMPRESSION_NONE=y
68CONFIG_CC_OPTIMIZE_FOR_SIZE=y 68CONFIG_CC_OPTIMIZE_FOR_SIZE=y
69CONFIG_SYSCTL=y 69CONFIG_SYSCTL=y
70CONFIG_ANON_INODES=y 70CONFIG_ANON_INODES=y
@@ -73,6 +73,7 @@ CONFIG_UID16=y
73# CONFIG_SYSCTL_SYSCALL is not set 73# CONFIG_SYSCTL_SYSCALL is not set
74CONFIG_KALLSYMS=y 74CONFIG_KALLSYMS=y
75# CONFIG_KALLSYMS_EXTRA_PASS is not set 75# CONFIG_KALLSYMS_EXTRA_PASS is not set
76# CONFIG_STRIP_ASM_SYMS is not set
76# CONFIG_HOTPLUG is not set 77# CONFIG_HOTPLUG is not set
77CONFIG_PRINTK=y 78CONFIG_PRINTK=y
78CONFIG_BUG=y 79CONFIG_BUG=y
@@ -92,12 +93,15 @@ CONFIG_SLAB=y
92# CONFIG_SLUB is not set 93# CONFIG_SLUB is not set
93# CONFIG_SLOB is not set 94# CONFIG_SLOB is not set
94# CONFIG_PROFILING is not set 95# CONFIG_PROFILING is not set
96# CONFIG_MARKERS is not set
95CONFIG_HAVE_OPROFILE=y 97CONFIG_HAVE_OPROFILE=y
96CONFIG_HAVE_IOREMAP_PROT=y 98CONFIG_HAVE_IOREMAP_PROT=y
97CONFIG_HAVE_KPROBES=y 99CONFIG_HAVE_KPROBES=y
98CONFIG_HAVE_KRETPROBES=y 100CONFIG_HAVE_KRETPROBES=y
99CONFIG_HAVE_ARCH_TRACEHOOK=y 101CONFIG_HAVE_ARCH_TRACEHOOK=y
100CONFIG_HAVE_CLK=y 102CONFIG_HAVE_CLK=y
103CONFIG_HAVE_DMA_API_DEBUG=y
104# CONFIG_SLOW_WORK is not set
101CONFIG_HAVE_GENERIC_DMA_COHERENT=y 105CONFIG_HAVE_GENERIC_DMA_COHERENT=y
102CONFIG_SLABINFO=y 106CONFIG_SLABINFO=y
103CONFIG_RT_MUTEXES=y 107CONFIG_RT_MUTEXES=y
@@ -105,7 +109,6 @@ CONFIG_BASE_SMALL=0
105# CONFIG_MODULES is not set 109# CONFIG_MODULES is not set
106CONFIG_BLOCK=y 110CONFIG_BLOCK=y
107# CONFIG_LBD is not set 111# CONFIG_LBD is not set
108# CONFIG_BLK_DEV_IO_TRACE is not set
109# CONFIG_BLK_DEV_BSG is not set 112# CONFIG_BLK_DEV_BSG is not set
110# CONFIG_BLK_DEV_INTEGRITY is not set 113# CONFIG_BLK_DEV_INTEGRITY is not set
111 114
@@ -151,6 +154,7 @@ CONFIG_CPU_SUBTYPE_SH7751R=y
151# CONFIG_CPU_SUBTYPE_SH7760 is not set 154# CONFIG_CPU_SUBTYPE_SH7760 is not set
152# CONFIG_CPU_SUBTYPE_SH4_202 is not set 155# CONFIG_CPU_SUBTYPE_SH4_202 is not set
153# CONFIG_CPU_SUBTYPE_SH7723 is not set 156# CONFIG_CPU_SUBTYPE_SH7723 is not set
157# CONFIG_CPU_SUBTYPE_SH7724 is not set
154# CONFIG_CPU_SUBTYPE_SH7763 is not set 158# CONFIG_CPU_SUBTYPE_SH7763 is not set
155# CONFIG_CPU_SUBTYPE_SH7770 is not set 159# CONFIG_CPU_SUBTYPE_SH7770 is not set
156# CONFIG_CPU_SUBTYPE_SH7780 is not set 160# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -160,8 +164,6 @@ CONFIG_CPU_SUBTYPE_SH7751R=y
160# CONFIG_CPU_SUBTYPE_SH7343 is not set 164# CONFIG_CPU_SUBTYPE_SH7343 is not set
161# CONFIG_CPU_SUBTYPE_SH7722 is not set 165# CONFIG_CPU_SUBTYPE_SH7722 is not set
162# CONFIG_CPU_SUBTYPE_SH7366 is not set 166# CONFIG_CPU_SUBTYPE_SH7366 is not set
163# CONFIG_CPU_SUBTYPE_SH5_101 is not set
164# CONFIG_CPU_SUBTYPE_SH5_103 is not set
165 167
166# 168#
167# Memory management options 169# Memory management options
@@ -295,8 +297,6 @@ CONFIG_BOOT_LINK_OFFSET=0x00800000
295# 297#
296CONFIG_PCI=y 298CONFIG_PCI=y
297CONFIG_SH_PCIDMA_NONCOHERENT=y 299CONFIG_SH_PCIDMA_NONCOHERENT=y
298CONFIG_PCI_AUTO=y
299CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
300# CONFIG_PCIEPORTBUS is not set 300# CONFIG_PCIEPORTBUS is not set
301# CONFIG_ARCH_SUPPORTS_MSI is not set 301# CONFIG_ARCH_SUPPORTS_MSI is not set
302CONFIG_PCI_LEGACY=y 302CONFIG_PCI_LEGACY=y
@@ -763,6 +763,11 @@ CONFIG_FILE_LOCKING=y
763# CONFIG_FUSE_FS is not set 763# CONFIG_FUSE_FS is not set
764 764
765# 765#
766# Caches
767#
768# CONFIG_FSCACHE is not set
769
770#
766# CD-ROM/DVD Filesystems 771# CD-ROM/DVD Filesystems
767# 772#
768# CONFIG_ISO9660_FS is not set 773# CONFIG_ISO9660_FS is not set
@@ -805,8 +810,13 @@ CONFIG_CRAMFS=y
805# CONFIG_HPFS_FS is not set 810# CONFIG_HPFS_FS is not set
806# CONFIG_QNX4FS_FS is not set 811# CONFIG_QNX4FS_FS is not set
807CONFIG_ROMFS_FS=y 812CONFIG_ROMFS_FS=y
813CONFIG_ROMFS_BACKED_BY_BLOCK=y
814# CONFIG_ROMFS_BACKED_BY_MTD is not set
815# CONFIG_ROMFS_BACKED_BY_BOTH is not set
816CONFIG_ROMFS_ON_BLOCK=y
808# CONFIG_SYSV_FS is not set 817# CONFIG_SYSV_FS is not set
809# CONFIG_UFS_FS is not set 818# CONFIG_UFS_FS is not set
819# CONFIG_NILFS2_FS is not set
810CONFIG_NETWORK_FILESYSTEMS=y 820CONFIG_NETWORK_FILESYSTEMS=y
811# CONFIG_NFS_FS is not set 821# CONFIG_NFS_FS is not set
812# CONFIG_NFSD is not set 822# CONFIG_NFSD is not set
@@ -844,10 +854,23 @@ CONFIG_FRAME_WARN=1024
844CONFIG_HAVE_FUNCTION_TRACER=y 854CONFIG_HAVE_FUNCTION_TRACER=y
845CONFIG_HAVE_DYNAMIC_FTRACE=y 855CONFIG_HAVE_DYNAMIC_FTRACE=y
846CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 856CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
857CONFIG_TRACING_SUPPORT=y
847 858
848# 859#
849# Tracers 860# Tracers
850# 861#
862# CONFIG_FUNCTION_TRACER is not set
863# CONFIG_IRQSOFF_TRACER is not set
864# CONFIG_SCHED_TRACER is not set
865# CONFIG_CONTEXT_SWITCH_TRACER is not set
866# CONFIG_EVENT_TRACER is not set
867# CONFIG_BOOT_TRACER is not set
868# CONFIG_TRACE_BRANCH_PROFILING is not set
869# CONFIG_STACK_TRACER is not set
870# CONFIG_KMEMTRACE is not set
871# CONFIG_WORKQUEUE_TRACER is not set
872# CONFIG_BLK_DEV_IO_TRACE is not set
873# CONFIG_DMA_API_DEBUG is not set
851# CONFIG_SAMPLES is not set 874# CONFIG_SAMPLES is not set
852CONFIG_HAVE_ARCH_KGDB=y 875CONFIG_HAVE_ARCH_KGDB=y
853# CONFIG_SH_STANDARD_BIOS is not set 876# CONFIG_SH_STANDARD_BIOS is not set
@@ -862,6 +885,7 @@ CONFIG_HAVE_ARCH_KGDB=y
862# CONFIG_SECURITYFS is not set 885# CONFIG_SECURITYFS is not set
863# CONFIG_SECURITY_FILE_CAPABILITIES is not set 886# CONFIG_SECURITY_FILE_CAPABILITIES is not set
864# CONFIG_CRYPTO is not set 887# CONFIG_CRYPTO is not set
888# CONFIG_BINARY_PRINTF is not set
865 889
866# 890#
867# Library routines 891# Library routines
diff --git a/arch/sh/configs/systemh_defconfig b/arch/sh/configs/systemh_defconfig
index 7ea639bc5936..dbe7e546f0bb 100644
--- a/arch/sh/configs/systemh_defconfig
+++ b/arch/sh/configs/systemh_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 19:23:31 2009 4# Mon Apr 27 13:14:33 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -61,7 +62,6 @@ CONFIG_INITRAMFS_SOURCE=""
61CONFIG_RD_GZIP=y 62CONFIG_RD_GZIP=y
62# CONFIG_RD_BZIP2 is not set 63# CONFIG_RD_BZIP2 is not set
63# CONFIG_RD_LZMA is not set 64# CONFIG_RD_LZMA is not set
64CONFIG_INITRAMFS_COMPRESSION_NONE=y
65# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 65# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
66CONFIG_SYSCTL=y 66CONFIG_SYSCTL=y
67CONFIG_ANON_INODES=y 67CONFIG_ANON_INODES=y
@@ -70,6 +70,7 @@ CONFIG_UID16=y
70# CONFIG_SYSCTL_SYSCALL is not set 70# CONFIG_SYSCTL_SYSCALL is not set
71CONFIG_KALLSYMS=y 71CONFIG_KALLSYMS=y
72# CONFIG_KALLSYMS_EXTRA_PASS is not set 72# CONFIG_KALLSYMS_EXTRA_PASS is not set
73# CONFIG_STRIP_ASM_SYMS is not set
73# CONFIG_HOTPLUG is not set 74# CONFIG_HOTPLUG is not set
74CONFIG_PRINTK=y 75CONFIG_PRINTK=y
75CONFIG_BUG=y 76CONFIG_BUG=y
@@ -88,6 +89,7 @@ CONFIG_SLAB=y
88# CONFIG_SLUB is not set 89# CONFIG_SLUB is not set
89# CONFIG_SLOB is not set 90# CONFIG_SLOB is not set
90# CONFIG_PROFILING is not set 91# CONFIG_PROFILING is not set
92# CONFIG_MARKERS is not set
91CONFIG_HAVE_OPROFILE=y 93CONFIG_HAVE_OPROFILE=y
92# CONFIG_KPROBES is not set 94# CONFIG_KPROBES is not set
93CONFIG_HAVE_IOREMAP_PROT=y 95CONFIG_HAVE_IOREMAP_PROT=y
@@ -95,6 +97,8 @@ CONFIG_HAVE_KPROBES=y
95CONFIG_HAVE_KRETPROBES=y 97CONFIG_HAVE_KRETPROBES=y
96CONFIG_HAVE_ARCH_TRACEHOOK=y 98CONFIG_HAVE_ARCH_TRACEHOOK=y
97CONFIG_HAVE_CLK=y 99CONFIG_HAVE_CLK=y
100CONFIG_HAVE_DMA_API_DEBUG=y
101# CONFIG_SLOW_WORK is not set
98CONFIG_HAVE_GENERIC_DMA_COHERENT=y 102CONFIG_HAVE_GENERIC_DMA_COHERENT=y
99CONFIG_SLABINFO=y 103CONFIG_SLABINFO=y
100CONFIG_RT_MUTEXES=y 104CONFIG_RT_MUTEXES=y
@@ -107,7 +111,6 @@ CONFIG_MODULE_UNLOAD=y
107# CONFIG_MODULE_SRCVERSION_ALL is not set 111# CONFIG_MODULE_SRCVERSION_ALL is not set
108CONFIG_BLOCK=y 112CONFIG_BLOCK=y
109# CONFIG_LBD is not set 113# CONFIG_LBD is not set
110# CONFIG_BLK_DEV_IO_TRACE is not set
111# CONFIG_BLK_DEV_BSG is not set 114# CONFIG_BLK_DEV_BSG is not set
112# CONFIG_BLK_DEV_INTEGRITY is not set 115# CONFIG_BLK_DEV_INTEGRITY is not set
113 116
@@ -153,6 +156,7 @@ CONFIG_CPU_SUBTYPE_SH7751R=y
153# CONFIG_CPU_SUBTYPE_SH7760 is not set 156# CONFIG_CPU_SUBTYPE_SH7760 is not set
154# CONFIG_CPU_SUBTYPE_SH4_202 is not set 157# CONFIG_CPU_SUBTYPE_SH4_202 is not set
155# CONFIG_CPU_SUBTYPE_SH7723 is not set 158# CONFIG_CPU_SUBTYPE_SH7723 is not set
159# CONFIG_CPU_SUBTYPE_SH7724 is not set
156# CONFIG_CPU_SUBTYPE_SH7763 is not set 160# CONFIG_CPU_SUBTYPE_SH7763 is not set
157# CONFIG_CPU_SUBTYPE_SH7770 is not set 161# CONFIG_CPU_SUBTYPE_SH7770 is not set
158# CONFIG_CPU_SUBTYPE_SH7780 is not set 162# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -162,8 +166,6 @@ CONFIG_CPU_SUBTYPE_SH7751R=y
162# CONFIG_CPU_SUBTYPE_SH7343 is not set 166# CONFIG_CPU_SUBTYPE_SH7343 is not set
163# CONFIG_CPU_SUBTYPE_SH7722 is not set 167# CONFIG_CPU_SUBTYPE_SH7722 is not set
164# CONFIG_CPU_SUBTYPE_SH7366 is not set 168# CONFIG_CPU_SUBTYPE_SH7366 is not set
165# CONFIG_CPU_SUBTYPE_SH5_101 is not set
166# CONFIG_CPU_SUBTYPE_SH5_103 is not set
167 169
168# 170#
169# Memory management options 171# Memory management options
@@ -506,6 +508,11 @@ CONFIG_INOTIFY_USER=y
506# CONFIG_FUSE_FS is not set 508# CONFIG_FUSE_FS is not set
507 509
508# 510#
511# Caches
512#
513# CONFIG_FSCACHE is not set
514
515#
509# CD-ROM/DVD Filesystems 516# CD-ROM/DVD Filesystems
510# 517#
511# CONFIG_ISO9660_FS is not set 518# CONFIG_ISO9660_FS is not set
@@ -547,8 +554,13 @@ CONFIG_CRAMFS=y
547# CONFIG_HPFS_FS is not set 554# CONFIG_HPFS_FS is not set
548# CONFIG_QNX4FS_FS is not set 555# CONFIG_QNX4FS_FS is not set
549CONFIG_ROMFS_FS=y 556CONFIG_ROMFS_FS=y
557CONFIG_ROMFS_BACKED_BY_BLOCK=y
558# CONFIG_ROMFS_BACKED_BY_MTD is not set
559# CONFIG_ROMFS_BACKED_BY_BOTH is not set
560CONFIG_ROMFS_ON_BLOCK=y
550# CONFIG_SYSV_FS is not set 561# CONFIG_SYSV_FS is not set
551# CONFIG_UFS_FS is not set 562# CONFIG_UFS_FS is not set
563# CONFIG_NILFS2_FS is not set
552 564
553# 565#
554# Partition Types 566# Partition Types
@@ -577,10 +589,24 @@ CONFIG_FRAME_WARN=1024
577CONFIG_HAVE_FUNCTION_TRACER=y 589CONFIG_HAVE_FUNCTION_TRACER=y
578CONFIG_HAVE_DYNAMIC_FTRACE=y 590CONFIG_HAVE_DYNAMIC_FTRACE=y
579CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 591CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
592CONFIG_TRACING_SUPPORT=y
580 593
581# 594#
582# Tracers 595# Tracers
583# 596#
597# CONFIG_FUNCTION_TRACER is not set
598# CONFIG_IRQSOFF_TRACER is not set
599# CONFIG_PREEMPT_TRACER is not set
600# CONFIG_SCHED_TRACER is not set
601# CONFIG_CONTEXT_SWITCH_TRACER is not set
602# CONFIG_EVENT_TRACER is not set
603# CONFIG_BOOT_TRACER is not set
604# CONFIG_TRACE_BRANCH_PROFILING is not set
605# CONFIG_STACK_TRACER is not set
606# CONFIG_KMEMTRACE is not set
607# CONFIG_WORKQUEUE_TRACER is not set
608# CONFIG_BLK_DEV_IO_TRACE is not set
609# CONFIG_DMA_API_DEBUG is not set
584# CONFIG_SAMPLES is not set 610# CONFIG_SAMPLES is not set
585CONFIG_HAVE_ARCH_KGDB=y 611CONFIG_HAVE_ARCH_KGDB=y
586# CONFIG_SH_STANDARD_BIOS is not set 612# CONFIG_SH_STANDARD_BIOS is not set
@@ -595,6 +621,7 @@ CONFIG_HAVE_ARCH_KGDB=y
595# CONFIG_SECURITYFS is not set 621# CONFIG_SECURITYFS is not set
596# CONFIG_SECURITY_FILE_CAPABILITIES is not set 622# CONFIG_SECURITY_FILE_CAPABILITIES is not set
597# CONFIG_CRYPTO is not set 623# CONFIG_CRYPTO is not set
624# CONFIG_BINARY_PRINTF is not set
598 625
599# 626#
600# Library routines 627# Library routines
diff --git a/arch/sh/configs/titan_defconfig b/arch/sh/configs/titan_defconfig
index bbeb4c6ebb95..8ca94ef74278 100644
--- a/arch/sh/configs/titan_defconfig
+++ b/arch/sh/configs/titan_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 19:24:55 2009 4# Mon Apr 27 13:14:55 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -40,6 +41,7 @@ CONFIG_SWAP=y
40CONFIG_SYSVIPC=y 41CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y 42CONFIG_SYSVIPC_SYSCTL=y
42CONFIG_POSIX_MQUEUE=y 43CONFIG_POSIX_MQUEUE=y
44CONFIG_POSIX_MQUEUE_SYSCTL=y
43# CONFIG_BSD_PROCESS_ACCT is not set 45# CONFIG_BSD_PROCESS_ACCT is not set
44# CONFIG_TASKSTATS is not set 46# CONFIG_TASKSTATS is not set
45# CONFIG_AUDIT is not set 47# CONFIG_AUDIT is not set
@@ -66,7 +68,6 @@ CONFIG_INITRAMFS_SOURCE=""
66CONFIG_RD_GZIP=y 68CONFIG_RD_GZIP=y
67# CONFIG_RD_BZIP2 is not set 69# CONFIG_RD_BZIP2 is not set
68# CONFIG_RD_LZMA is not set 70# CONFIG_RD_LZMA is not set
69CONFIG_INITRAMFS_COMPRESSION_NONE=y
70# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set 71# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
71CONFIG_SYSCTL=y 72CONFIG_SYSCTL=y
72CONFIG_ANON_INODES=y 73CONFIG_ANON_INODES=y
@@ -76,6 +77,7 @@ CONFIG_UID16=y
76CONFIG_KALLSYMS=y 77CONFIG_KALLSYMS=y
77# CONFIG_KALLSYMS_ALL is not set 78# CONFIG_KALLSYMS_ALL is not set
78# CONFIG_KALLSYMS_EXTRA_PASS is not set 79# CONFIG_KALLSYMS_EXTRA_PASS is not set
80# CONFIG_STRIP_ASM_SYMS is not set
79CONFIG_HOTPLUG=y 81CONFIG_HOTPLUG=y
80CONFIG_PRINTK=y 82CONFIG_PRINTK=y
81CONFIG_BUG=y 83CONFIG_BUG=y
@@ -95,6 +97,7 @@ CONFIG_SLAB=y
95# CONFIG_SLUB is not set 97# CONFIG_SLUB is not set
96# CONFIG_SLOB is not set 98# CONFIG_SLOB is not set
97# CONFIG_PROFILING is not set 99# CONFIG_PROFILING is not set
100# CONFIG_MARKERS is not set
98CONFIG_HAVE_OPROFILE=y 101CONFIG_HAVE_OPROFILE=y
99# CONFIG_KPROBES is not set 102# CONFIG_KPROBES is not set
100CONFIG_HAVE_IOREMAP_PROT=y 103CONFIG_HAVE_IOREMAP_PROT=y
@@ -102,6 +105,8 @@ CONFIG_HAVE_KPROBES=y
102CONFIG_HAVE_KRETPROBES=y 105CONFIG_HAVE_KRETPROBES=y
103CONFIG_HAVE_ARCH_TRACEHOOK=y 106CONFIG_HAVE_ARCH_TRACEHOOK=y
104CONFIG_HAVE_CLK=y 107CONFIG_HAVE_CLK=y
108CONFIG_HAVE_DMA_API_DEBUG=y
109# CONFIG_SLOW_WORK is not set
105CONFIG_HAVE_GENERIC_DMA_COHERENT=y 110CONFIG_HAVE_GENERIC_DMA_COHERENT=y
106CONFIG_SLABINFO=y 111CONFIG_SLABINFO=y
107CONFIG_RT_MUTEXES=y 112CONFIG_RT_MUTEXES=y
@@ -114,7 +119,6 @@ CONFIG_MODULE_FORCE_UNLOAD=y
114# CONFIG_MODULE_SRCVERSION_ALL is not set 119# CONFIG_MODULE_SRCVERSION_ALL is not set
115CONFIG_BLOCK=y 120CONFIG_BLOCK=y
116# CONFIG_LBD is not set 121# CONFIG_LBD is not set
117# CONFIG_BLK_DEV_IO_TRACE is not set
118# CONFIG_BLK_DEV_BSG is not set 122# CONFIG_BLK_DEV_BSG is not set
119# CONFIG_BLK_DEV_INTEGRITY is not set 123# CONFIG_BLK_DEV_INTEGRITY is not set
120 124
@@ -160,6 +164,7 @@ CONFIG_CPU_SUBTYPE_SH7751R=y
160# CONFIG_CPU_SUBTYPE_SH7760 is not set 164# CONFIG_CPU_SUBTYPE_SH7760 is not set
161# CONFIG_CPU_SUBTYPE_SH4_202 is not set 165# CONFIG_CPU_SUBTYPE_SH4_202 is not set
162# CONFIG_CPU_SUBTYPE_SH7723 is not set 166# CONFIG_CPU_SUBTYPE_SH7723 is not set
167# CONFIG_CPU_SUBTYPE_SH7724 is not set
163# CONFIG_CPU_SUBTYPE_SH7763 is not set 168# CONFIG_CPU_SUBTYPE_SH7763 is not set
164# CONFIG_CPU_SUBTYPE_SH7770 is not set 169# CONFIG_CPU_SUBTYPE_SH7770 is not set
165# CONFIG_CPU_SUBTYPE_SH7780 is not set 170# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -169,8 +174,6 @@ CONFIG_CPU_SUBTYPE_SH7751R=y
169# CONFIG_CPU_SUBTYPE_SH7343 is not set 174# CONFIG_CPU_SUBTYPE_SH7343 is not set
170# CONFIG_CPU_SUBTYPE_SH7722 is not set 175# CONFIG_CPU_SUBTYPE_SH7722 is not set
171# CONFIG_CPU_SUBTYPE_SH7366 is not set 176# CONFIG_CPU_SUBTYPE_SH7366 is not set
172# CONFIG_CPU_SUBTYPE_SH5_101 is not set
173# CONFIG_CPU_SUBTYPE_SH5_103 is not set
174 177
175# 178#
176# Memory management options 179# Memory management options
@@ -305,8 +308,6 @@ CONFIG_CMDLINE="console=ttySC1,38400N81 root=/dev/nfs ip=:::::eth1:autoconf rw"
305# 308#
306CONFIG_PCI=y 309CONFIG_PCI=y
307CONFIG_SH_PCIDMA_NONCOHERENT=y 310CONFIG_SH_PCIDMA_NONCOHERENT=y
308CONFIG_PCI_AUTO=y
309CONFIG_PCI_AUTO_UPDATE_RESOURCES=y
310# CONFIG_PCIEPORTBUS is not set 311# CONFIG_PCIEPORTBUS is not set
311# CONFIG_ARCH_SUPPORTS_MSI is not set 312# CONFIG_ARCH_SUPPORTS_MSI is not set
312CONFIG_PCI_LEGACY=y 313CONFIG_PCI_LEGACY=y
@@ -789,6 +790,7 @@ CONFIG_SCSI_LOWLEVEL=y
789# CONFIG_SCSI_MPT2SAS is not set 790# CONFIG_SCSI_MPT2SAS is not set
790# CONFIG_SCSI_HPTIOP is not set 791# CONFIG_SCSI_HPTIOP is not set
791# CONFIG_LIBFC is not set 792# CONFIG_LIBFC is not set
793# CONFIG_LIBFCOE is not set
792# CONFIG_FCOE is not set 794# CONFIG_FCOE is not set
793# CONFIG_SCSI_DMX3191D is not set 795# CONFIG_SCSI_DMX3191D is not set
794# CONFIG_SCSI_FUTURE_DOMAIN is not set 796# CONFIG_SCSI_FUTURE_DOMAIN is not set
@@ -906,6 +908,7 @@ CONFIG_NETDEV_1000=y
906# CONFIG_E1000E is not set 908# CONFIG_E1000E is not set
907# CONFIG_IP1000 is not set 909# CONFIG_IP1000 is not set
908# CONFIG_IGB is not set 910# CONFIG_IGB is not set
911# CONFIG_IGBVF is not set
909# CONFIG_NS83820 is not set 912# CONFIG_NS83820 is not set
910# CONFIG_HAMACHI is not set 913# CONFIG_HAMACHI is not set
911# CONFIG_YELLOWFIN is not set 914# CONFIG_YELLOWFIN is not set
@@ -929,6 +932,7 @@ CONFIG_CHELSIO_T3_DEPENDS=y
929# CONFIG_IXGBE is not set 932# CONFIG_IXGBE is not set
930# CONFIG_IXGB is not set 933# CONFIG_IXGB is not set
931# CONFIG_S2IO is not set 934# CONFIG_S2IO is not set
935# CONFIG_VXGE is not set
932# CONFIG_MYRI10GE is not set 936# CONFIG_MYRI10GE is not set
933# CONFIG_NETXEN_NIC is not set 937# CONFIG_NETXEN_NIC is not set
934# CONFIG_NIU is not set 938# CONFIG_NIU is not set
@@ -1182,7 +1186,6 @@ CONFIG_HID=y
1182# 1186#
1183# Special HID drivers 1187# Special HID drivers
1184# 1188#
1185CONFIG_HID_COMPAT=y
1186CONFIG_USB_SUPPORT=y 1189CONFIG_USB_SUPPORT=y
1187CONFIG_USB_ARCH_HAS_HCD=y 1190CONFIG_USB_ARCH_HAS_HCD=y
1188CONFIG_USB_ARCH_HAS_OHCI=y 1191CONFIG_USB_ARCH_HAS_OHCI=y
@@ -1393,6 +1396,7 @@ CONFIG_EXT2_FS=y
1393# CONFIG_EXT2_FS_XATTR is not set 1396# CONFIG_EXT2_FS_XATTR is not set
1394# CONFIG_EXT2_FS_XIP is not set 1397# CONFIG_EXT2_FS_XIP is not set
1395CONFIG_EXT3_FS=y 1398CONFIG_EXT3_FS=y
1399# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1396# CONFIG_EXT3_FS_XATTR is not set 1400# CONFIG_EXT3_FS_XATTR is not set
1397# CONFIG_EXT4_FS is not set 1401# CONFIG_EXT4_FS is not set
1398CONFIG_JBD=y 1402CONFIG_JBD=y
@@ -1419,6 +1423,11 @@ CONFIG_INOTIFY_USER=y
1419CONFIG_FUSE_FS=m 1423CONFIG_FUSE_FS=m
1420 1424
1421# 1425#
1426# Caches
1427#
1428# CONFIG_FSCACHE is not set
1429
1430#
1422# CD-ROM/DVD Filesystems 1431# CD-ROM/DVD Filesystems
1423# 1432#
1424CONFIG_ISO9660_FS=m 1433CONFIG_ISO9660_FS=m
@@ -1467,8 +1476,13 @@ CONFIG_MISC_FILESYSTEMS=y
1467# CONFIG_HPFS_FS is not set 1476# CONFIG_HPFS_FS is not set
1468# CONFIG_QNX4FS_FS is not set 1477# CONFIG_QNX4FS_FS is not set
1469CONFIG_ROMFS_FS=y 1478CONFIG_ROMFS_FS=y
1479CONFIG_ROMFS_BACKED_BY_BLOCK=y
1480# CONFIG_ROMFS_BACKED_BY_MTD is not set
1481# CONFIG_ROMFS_BACKED_BY_BOTH is not set
1482CONFIG_ROMFS_ON_BLOCK=y
1470# CONFIG_SYSV_FS is not set 1483# CONFIG_SYSV_FS is not set
1471# CONFIG_UFS_FS is not set 1484# CONFIG_UFS_FS is not set
1485# CONFIG_NILFS2_FS is not set
1472CONFIG_NETWORK_FILESYSTEMS=y 1486CONFIG_NETWORK_FILESYSTEMS=y
1473CONFIG_NFS_FS=y 1487CONFIG_NFS_FS=y
1474CONFIG_NFS_V3=y 1488CONFIG_NFS_V3=y
@@ -1576,6 +1590,7 @@ CONFIG_MAGIC_SYSRQ=y
1576CONFIG_DEBUG_KERNEL=y 1590CONFIG_DEBUG_KERNEL=y
1577# CONFIG_DEBUG_SHIRQ is not set 1591# CONFIG_DEBUG_SHIRQ is not set
1578# CONFIG_DETECT_SOFTLOCKUP is not set 1592# CONFIG_DETECT_SOFTLOCKUP is not set
1593# CONFIG_DETECT_HUNG_TASK is not set
1579CONFIG_SCHED_DEBUG=y 1594CONFIG_SCHED_DEBUG=y
1580# CONFIG_SCHEDSTATS is not set 1595# CONFIG_SCHEDSTATS is not set
1581# CONFIG_TIMER_STATS is not set 1596# CONFIG_TIMER_STATS is not set
@@ -1610,6 +1625,7 @@ CONFIG_SCHED_DEBUG=y
1610CONFIG_HAVE_FUNCTION_TRACER=y 1625CONFIG_HAVE_FUNCTION_TRACER=y
1611CONFIG_HAVE_DYNAMIC_FTRACE=y 1626CONFIG_HAVE_DYNAMIC_FTRACE=y
1612CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1627CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1628CONFIG_TRACING_SUPPORT=y
1613 1629
1614# 1630#
1615# Tracers 1631# Tracers
@@ -1618,9 +1634,14 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1618# CONFIG_IRQSOFF_TRACER is not set 1634# CONFIG_IRQSOFF_TRACER is not set
1619# CONFIG_SCHED_TRACER is not set 1635# CONFIG_SCHED_TRACER is not set
1620# CONFIG_CONTEXT_SWITCH_TRACER is not set 1636# CONFIG_CONTEXT_SWITCH_TRACER is not set
1637# CONFIG_EVENT_TRACER is not set
1621# CONFIG_BOOT_TRACER is not set 1638# CONFIG_BOOT_TRACER is not set
1622# CONFIG_TRACE_BRANCH_PROFILING is not set 1639# CONFIG_TRACE_BRANCH_PROFILING is not set
1623# CONFIG_STACK_TRACER is not set 1640# CONFIG_STACK_TRACER is not set
1641# CONFIG_KMEMTRACE is not set
1642# CONFIG_WORKQUEUE_TRACER is not set
1643# CONFIG_BLK_DEV_IO_TRACE is not set
1644# CONFIG_DMA_API_DEBUG is not set
1624# CONFIG_SAMPLES is not set 1645# CONFIG_SAMPLES is not set
1625CONFIG_HAVE_ARCH_KGDB=y 1646CONFIG_HAVE_ARCH_KGDB=y
1626# CONFIG_KGDB is not set 1647# CONFIG_KGDB is not set
@@ -1741,6 +1762,7 @@ CONFIG_CRYPTO_DEFLATE=y
1741# CONFIG_CRYPTO_ANSI_CPRNG is not set 1762# CONFIG_CRYPTO_ANSI_CPRNG is not set
1742CONFIG_CRYPTO_HW=y 1763CONFIG_CRYPTO_HW=y
1743# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1764# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1765# CONFIG_BINARY_PRINTF is not set
1744 1766
1745# 1767#
1746# Library routines 1768# Library routines
diff --git a/arch/sh/configs/ul2_defconfig b/arch/sh/configs/ul2_defconfig
index 34f5192a3241..bfb4d9806892 100644
--- a/arch/sh/configs/ul2_defconfig
+++ b/arch/sh/configs/ul2_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 19:30:27 2009 4# Mon Apr 27 13:17:05 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -69,7 +70,6 @@ CONFIG_INITRAMFS_SOURCE=""
69CONFIG_RD_GZIP=y 70CONFIG_RD_GZIP=y
70# CONFIG_RD_BZIP2 is not set 71# CONFIG_RD_BZIP2 is not set
71# CONFIG_RD_LZMA is not set 72# CONFIG_RD_LZMA is not set
72CONFIG_INITRAMFS_COMPRESSION_NONE=y
73CONFIG_CC_OPTIMIZE_FOR_SIZE=y 73CONFIG_CC_OPTIMIZE_FOR_SIZE=y
74CONFIG_SYSCTL=y 74CONFIG_SYSCTL=y
75CONFIG_ANON_INODES=y 75CONFIG_ANON_INODES=y
@@ -78,6 +78,7 @@ CONFIG_UID16=y
78CONFIG_SYSCTL_SYSCALL=y 78CONFIG_SYSCTL_SYSCALL=y
79CONFIG_KALLSYMS=y 79CONFIG_KALLSYMS=y
80# CONFIG_KALLSYMS_EXTRA_PASS is not set 80# CONFIG_KALLSYMS_EXTRA_PASS is not set
81# CONFIG_STRIP_ASM_SYMS is not set
81CONFIG_HOTPLUG=y 82CONFIG_HOTPLUG=y
82CONFIG_PRINTK=y 83CONFIG_PRINTK=y
83CONFIG_BUG=y 84CONFIG_BUG=y
@@ -97,6 +98,7 @@ CONFIG_COMPAT_BRK=y
97CONFIG_SLUB=y 98CONFIG_SLUB=y
98# CONFIG_SLOB is not set 99# CONFIG_SLOB is not set
99CONFIG_PROFILING=y 100CONFIG_PROFILING=y
101# CONFIG_MARKERS is not set
100# CONFIG_OPROFILE is not set 102# CONFIG_OPROFILE is not set
101CONFIG_HAVE_OPROFILE=y 103CONFIG_HAVE_OPROFILE=y
102# CONFIG_KPROBES is not set 104# CONFIG_KPROBES is not set
@@ -105,6 +107,8 @@ CONFIG_HAVE_KPROBES=y
105CONFIG_HAVE_KRETPROBES=y 107CONFIG_HAVE_KRETPROBES=y
106CONFIG_HAVE_ARCH_TRACEHOOK=y 108CONFIG_HAVE_ARCH_TRACEHOOK=y
107CONFIG_HAVE_CLK=y 109CONFIG_HAVE_CLK=y
110CONFIG_HAVE_DMA_API_DEBUG=y
111# CONFIG_SLOW_WORK is not set
108CONFIG_HAVE_GENERIC_DMA_COHERENT=y 112CONFIG_HAVE_GENERIC_DMA_COHERENT=y
109CONFIG_SLABINFO=y 113CONFIG_SLABINFO=y
110CONFIG_RT_MUTEXES=y 114CONFIG_RT_MUTEXES=y
@@ -117,7 +121,6 @@ CONFIG_MODULE_UNLOAD=y
117# CONFIG_MODULE_SRCVERSION_ALL is not set 121# CONFIG_MODULE_SRCVERSION_ALL is not set
118CONFIG_BLOCK=y 122CONFIG_BLOCK=y
119# CONFIG_LBD is not set 123# CONFIG_LBD is not set
120# CONFIG_BLK_DEV_IO_TRACE is not set
121# CONFIG_BLK_DEV_BSG is not set 124# CONFIG_BLK_DEV_BSG is not set
122# CONFIG_BLK_DEV_INTEGRITY is not set 125# CONFIG_BLK_DEV_INTEGRITY is not set
123 126
@@ -167,6 +170,7 @@ CONFIG_ARCH_SHMOBILE=y
167# CONFIG_CPU_SUBTYPE_SH7760 is not set 170# CONFIG_CPU_SUBTYPE_SH7760 is not set
168# CONFIG_CPU_SUBTYPE_SH4_202 is not set 171# CONFIG_CPU_SUBTYPE_SH4_202 is not set
169# CONFIG_CPU_SUBTYPE_SH7723 is not set 172# CONFIG_CPU_SUBTYPE_SH7723 is not set
173# CONFIG_CPU_SUBTYPE_SH7724 is not set
170# CONFIG_CPU_SUBTYPE_SH7763 is not set 174# CONFIG_CPU_SUBTYPE_SH7763 is not set
171# CONFIG_CPU_SUBTYPE_SH7770 is not set 175# CONFIG_CPU_SUBTYPE_SH7770 is not set
172# CONFIG_CPU_SUBTYPE_SH7780 is not set 176# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -176,8 +180,6 @@ CONFIG_ARCH_SHMOBILE=y
176# CONFIG_CPU_SUBTYPE_SH7343 is not set 180# CONFIG_CPU_SUBTYPE_SH7343 is not set
177# CONFIG_CPU_SUBTYPE_SH7722 is not set 181# CONFIG_CPU_SUBTYPE_SH7722 is not set
178CONFIG_CPU_SUBTYPE_SH7366=y 182CONFIG_CPU_SUBTYPE_SH7366=y
179# CONFIG_CPU_SUBTYPE_SH5_101 is not set
180# CONFIG_CPU_SUBTYPE_SH5_103 is not set
181 183
182# 184#
183# Memory management options 185# Memory management options
@@ -584,6 +586,7 @@ CONFIG_SCSI_WAIT_SCAN=m
584CONFIG_SCSI_LOWLEVEL=y 586CONFIG_SCSI_LOWLEVEL=y
585# CONFIG_ISCSI_TCP is not set 587# CONFIG_ISCSI_TCP is not set
586# CONFIG_LIBFC is not set 588# CONFIG_LIBFC is not set
589# CONFIG_LIBFCOE is not set
587# CONFIG_SCSI_DEBUG is not set 590# CONFIG_SCSI_DEBUG is not set
588# CONFIG_SCSI_DH is not set 591# CONFIG_SCSI_DH is not set
589# CONFIG_SCSI_OSD_INITIATOR is not set 592# CONFIG_SCSI_OSD_INITIATOR is not set
@@ -936,6 +939,7 @@ CONFIG_EXT2_FS=y
936# CONFIG_EXT2_FS_XATTR is not set 939# CONFIG_EXT2_FS_XATTR is not set
937# CONFIG_EXT2_FS_XIP is not set 940# CONFIG_EXT2_FS_XIP is not set
938CONFIG_EXT3_FS=y 941CONFIG_EXT3_FS=y
942# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
939CONFIG_EXT3_FS_XATTR=y 943CONFIG_EXT3_FS_XATTR=y
940# CONFIG_EXT3_FS_POSIX_ACL is not set 944# CONFIG_EXT3_FS_POSIX_ACL is not set
941# CONFIG_EXT3_FS_SECURITY is not set 945# CONFIG_EXT3_FS_SECURITY is not set
@@ -958,6 +962,11 @@ CONFIG_INOTIFY_USER=y
958# CONFIG_FUSE_FS is not set 962# CONFIG_FUSE_FS is not set
959 963
960# 964#
965# Caches
966#
967# CONFIG_FSCACHE is not set
968
969#
961# CD-ROM/DVD Filesystems 970# CD-ROM/DVD Filesystems
962# 971#
963# CONFIG_ISO9660_FS is not set 972# CONFIG_ISO9660_FS is not set
@@ -1005,6 +1014,7 @@ CONFIG_CRAMFS=y
1005# CONFIG_ROMFS_FS is not set 1014# CONFIG_ROMFS_FS is not set
1006# CONFIG_SYSV_FS is not set 1015# CONFIG_SYSV_FS is not set
1007# CONFIG_UFS_FS is not set 1016# CONFIG_UFS_FS is not set
1017# CONFIG_NILFS2_FS is not set
1008CONFIG_NETWORK_FILESYSTEMS=y 1018CONFIG_NETWORK_FILESYSTEMS=y
1009CONFIG_NFS_FS=y 1019CONFIG_NFS_FS=y
1010# CONFIG_NFS_V3 is not set 1020# CONFIG_NFS_V3 is not set
@@ -1095,10 +1105,24 @@ CONFIG_FRAME_WARN=1024
1095CONFIG_HAVE_FUNCTION_TRACER=y 1105CONFIG_HAVE_FUNCTION_TRACER=y
1096CONFIG_HAVE_DYNAMIC_FTRACE=y 1106CONFIG_HAVE_DYNAMIC_FTRACE=y
1097CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1107CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1108CONFIG_TRACING_SUPPORT=y
1098 1109
1099# 1110#
1100# Tracers 1111# Tracers
1101# 1112#
1113# CONFIG_FUNCTION_TRACER is not set
1114# CONFIG_IRQSOFF_TRACER is not set
1115# CONFIG_PREEMPT_TRACER is not set
1116# CONFIG_SCHED_TRACER is not set
1117# CONFIG_CONTEXT_SWITCH_TRACER is not set
1118# CONFIG_EVENT_TRACER is not set
1119# CONFIG_BOOT_TRACER is not set
1120# CONFIG_TRACE_BRANCH_PROFILING is not set
1121# CONFIG_STACK_TRACER is not set
1122# CONFIG_KMEMTRACE is not set
1123# CONFIG_WORKQUEUE_TRACER is not set
1124# CONFIG_BLK_DEV_IO_TRACE is not set
1125# CONFIG_DMA_API_DEBUG is not set
1102# CONFIG_SAMPLES is not set 1126# CONFIG_SAMPLES is not set
1103CONFIG_HAVE_ARCH_KGDB=y 1127CONFIG_HAVE_ARCH_KGDB=y
1104# CONFIG_SH_STANDARD_BIOS is not set 1128# CONFIG_SH_STANDARD_BIOS is not set
@@ -1208,6 +1232,7 @@ CONFIG_CRYPTO_ARC4=y
1208# 1232#
1209# CONFIG_CRYPTO_ANSI_CPRNG is not set 1233# CONFIG_CRYPTO_ANSI_CPRNG is not set
1210CONFIG_CRYPTO_HW=y 1234CONFIG_CRYPTO_HW=y
1235# CONFIG_BINARY_PRINTF is not set
1211 1236
1212# 1237#
1213# Library routines 1238# Library routines
diff --git a/arch/sh/configs/urquell_defconfig b/arch/sh/configs/urquell_defconfig
index d174b1a4d802..512664fed66c 100644
--- a/arch/sh/configs/urquell_defconfig
+++ b/arch/sh/configs/urquell_defconfig
@@ -1,10 +1,11 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29 3# Linux kernel version: 2.6.30-rc3
4# Thu Apr 2 19:33:39 2009 4# Mon Apr 27 14:02:55 2009
5# 5#
6CONFIG_SUPERH=y 6CONFIG_SUPERH=y
7CONFIG_SUPERH32=y 7CONFIG_SUPERH32=y
8# CONFIG_SUPERH64 is not set
8CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig" 9CONFIG_ARCH_DEFCONFIG="arch/sh/configs/shx3_defconfig"
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 10CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_BUG=y 11CONFIG_GENERIC_BUG=y
@@ -76,6 +77,7 @@ CONFIG_UID16=y
76CONFIG_SYSCTL_SYSCALL=y 77CONFIG_SYSCTL_SYSCALL=y
77CONFIG_KALLSYMS=y 78CONFIG_KALLSYMS=y
78# CONFIG_KALLSYMS_EXTRA_PASS is not set 79# CONFIG_KALLSYMS_EXTRA_PASS is not set
80# CONFIG_STRIP_ASM_SYMS is not set
79CONFIG_HOTPLUG=y 81CONFIG_HOTPLUG=y
80CONFIG_PRINTK=y 82CONFIG_PRINTK=y
81CONFIG_BUG=y 83CONFIG_BUG=y
@@ -94,6 +96,7 @@ CONFIG_SLAB=y
94# CONFIG_SLUB is not set 96# CONFIG_SLUB is not set
95# CONFIG_SLOB is not set 97# CONFIG_SLOB is not set
96CONFIG_PROFILING=y 98CONFIG_PROFILING=y
99# CONFIG_MARKERS is not set
97# CONFIG_OPROFILE is not set 100# CONFIG_OPROFILE is not set
98CONFIG_HAVE_OPROFILE=y 101CONFIG_HAVE_OPROFILE=y
99# CONFIG_KPROBES is not set 102# CONFIG_KPROBES is not set
@@ -102,6 +105,8 @@ CONFIG_HAVE_KPROBES=y
102CONFIG_HAVE_KRETPROBES=y 105CONFIG_HAVE_KRETPROBES=y
103CONFIG_HAVE_ARCH_TRACEHOOK=y 106CONFIG_HAVE_ARCH_TRACEHOOK=y
104CONFIG_HAVE_CLK=y 107CONFIG_HAVE_CLK=y
108CONFIG_HAVE_DMA_API_DEBUG=y
109# CONFIG_SLOW_WORK is not set
105CONFIG_HAVE_GENERIC_DMA_COHERENT=y 110CONFIG_HAVE_GENERIC_DMA_COHERENT=y
106CONFIG_SLABINFO=y 111CONFIG_SLABINFO=y
107CONFIG_RT_MUTEXES=y 112CONFIG_RT_MUTEXES=y
@@ -114,7 +119,6 @@ CONFIG_MODULE_UNLOAD=y
114# CONFIG_MODULE_SRCVERSION_ALL is not set 119# CONFIG_MODULE_SRCVERSION_ALL is not set
115CONFIG_BLOCK=y 120CONFIG_BLOCK=y
116# CONFIG_LBD is not set 121# CONFIG_LBD is not set
117# CONFIG_BLK_DEV_IO_TRACE is not set
118# CONFIG_BLK_DEV_BSG is not set 122# CONFIG_BLK_DEV_BSG is not set
119# CONFIG_BLK_DEV_INTEGRITY is not set 123# CONFIG_BLK_DEV_INTEGRITY is not set
120 124
@@ -162,6 +166,7 @@ CONFIG_CPU_SHX3=y
162# CONFIG_CPU_SUBTYPE_SH7760 is not set 166# CONFIG_CPU_SUBTYPE_SH7760 is not set
163# CONFIG_CPU_SUBTYPE_SH4_202 is not set 167# CONFIG_CPU_SUBTYPE_SH4_202 is not set
164# CONFIG_CPU_SUBTYPE_SH7723 is not set 168# CONFIG_CPU_SUBTYPE_SH7723 is not set
169# CONFIG_CPU_SUBTYPE_SH7724 is not set
165# CONFIG_CPU_SUBTYPE_SH7763 is not set 170# CONFIG_CPU_SUBTYPE_SH7763 is not set
166# CONFIG_CPU_SUBTYPE_SH7770 is not set 171# CONFIG_CPU_SUBTYPE_SH7770 is not set
167# CONFIG_CPU_SUBTYPE_SH7780 is not set 172# CONFIG_CPU_SUBTYPE_SH7780 is not set
@@ -171,8 +176,6 @@ CONFIG_CPU_SUBTYPE_SH7786=y
171# CONFIG_CPU_SUBTYPE_SH7343 is not set 176# CONFIG_CPU_SUBTYPE_SH7343 is not set
172# CONFIG_CPU_SUBTYPE_SH7722 is not set 177# CONFIG_CPU_SUBTYPE_SH7722 is not set
173# CONFIG_CPU_SUBTYPE_SH7366 is not set 178# CONFIG_CPU_SUBTYPE_SH7366 is not set
174# CONFIG_CPU_SUBTYPE_SH5_101 is not set
175# CONFIG_CPU_SUBTYPE_SH5_103 is not set
176 179
177# 180#
178# Memory management options 181# Memory management options
@@ -900,15 +903,17 @@ CONFIG_USB_HID=y
900# 903#
901# Special HID drivers 904# Special HID drivers
902# 905#
903CONFIG_HID_COMPAT=y
904CONFIG_HID_A4TECH=y 906CONFIG_HID_A4TECH=y
905CONFIG_HID_APPLE=y 907CONFIG_HID_APPLE=y
906CONFIG_HID_BELKIN=y 908CONFIG_HID_BELKIN=y
907CONFIG_HID_CHERRY=y 909CONFIG_HID_CHERRY=y
908CONFIG_HID_CHICONY=y 910CONFIG_HID_CHICONY=y
909CONFIG_HID_CYPRESS=y 911CONFIG_HID_CYPRESS=y
912# CONFIG_DRAGONRISE_FF is not set
910CONFIG_HID_EZKEY=y 913CONFIG_HID_EZKEY=y
914# CONFIG_HID_KYE is not set
911CONFIG_HID_GYRATION=y 915CONFIG_HID_GYRATION=y
916# CONFIG_HID_KENSINGTON is not set
912CONFIG_HID_LOGITECH=y 917CONFIG_HID_LOGITECH=y
913# CONFIG_LOGITECH_FF is not set 918# CONFIG_LOGITECH_FF is not set
914# CONFIG_LOGIRUMBLEPAD2_FF is not set 919# CONFIG_LOGIRUMBLEPAD2_FF is not set
@@ -1046,6 +1051,7 @@ CONFIG_EXT2_FS=y
1046# CONFIG_EXT2_FS_XATTR is not set 1051# CONFIG_EXT2_FS_XATTR is not set
1047# CONFIG_EXT2_FS_XIP is not set 1052# CONFIG_EXT2_FS_XIP is not set
1048CONFIG_EXT3_FS=y 1053CONFIG_EXT3_FS=y
1054# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
1049CONFIG_EXT3_FS_XATTR=y 1055CONFIG_EXT3_FS_XATTR=y
1050# CONFIG_EXT3_FS_POSIX_ACL is not set 1056# CONFIG_EXT3_FS_POSIX_ACL is not set
1051# CONFIG_EXT3_FS_SECURITY is not set 1057# CONFIG_EXT3_FS_SECURITY is not set
@@ -1068,6 +1074,11 @@ CONFIG_INOTIFY_USER=y
1068# CONFIG_FUSE_FS is not set 1074# CONFIG_FUSE_FS is not set
1069 1075
1070# 1076#
1077# Caches
1078#
1079# CONFIG_FSCACHE is not set
1080
1081#
1071# CD-ROM/DVD Filesystems 1082# CD-ROM/DVD Filesystems
1072# 1083#
1073# CONFIG_ISO9660_FS is not set 1084# CONFIG_ISO9660_FS is not set
@@ -1117,6 +1128,7 @@ CONFIG_MINIX_FS=y
1117# CONFIG_ROMFS_FS is not set 1128# CONFIG_ROMFS_FS is not set
1118# CONFIG_SYSV_FS is not set 1129# CONFIG_SYSV_FS is not set
1119# CONFIG_UFS_FS is not set 1130# CONFIG_UFS_FS is not set
1131# CONFIG_NILFS2_FS is not set
1120CONFIG_NETWORK_FILESYSTEMS=y 1132CONFIG_NETWORK_FILESYSTEMS=y
1121CONFIG_NFS_FS=y 1133CONFIG_NFS_FS=y
1122CONFIG_NFS_V3=y 1134CONFIG_NFS_V3=y
@@ -1209,10 +1221,24 @@ CONFIG_SYSCTL_SYSCALL_CHECK=y
1209CONFIG_HAVE_FUNCTION_TRACER=y 1221CONFIG_HAVE_FUNCTION_TRACER=y
1210CONFIG_HAVE_DYNAMIC_FTRACE=y 1222CONFIG_HAVE_DYNAMIC_FTRACE=y
1211CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y 1223CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
1224CONFIG_TRACING_SUPPORT=y
1212 1225
1213# 1226#
1214# Tracers 1227# Tracers
1215# 1228#
1229# CONFIG_FUNCTION_TRACER is not set
1230# CONFIG_IRQSOFF_TRACER is not set
1231# CONFIG_PREEMPT_TRACER is not set
1232# CONFIG_SCHED_TRACER is not set
1233# CONFIG_CONTEXT_SWITCH_TRACER is not set
1234# CONFIG_EVENT_TRACER is not set
1235# CONFIG_BOOT_TRACER is not set
1236# CONFIG_TRACE_BRANCH_PROFILING is not set
1237# CONFIG_STACK_TRACER is not set
1238# CONFIG_KMEMTRACE is not set
1239# CONFIG_WORKQUEUE_TRACER is not set
1240# CONFIG_BLK_DEV_IO_TRACE is not set
1241# CONFIG_DMA_API_DEBUG is not set
1216# CONFIG_SAMPLES is not set 1242# CONFIG_SAMPLES is not set
1217CONFIG_HAVE_ARCH_KGDB=y 1243CONFIG_HAVE_ARCH_KGDB=y
1218# CONFIG_SH_STANDARD_BIOS is not set 1244# CONFIG_SH_STANDARD_BIOS is not set
@@ -1322,6 +1348,7 @@ CONFIG_CRYPTO_DES=y
1322# 1348#
1323# CONFIG_CRYPTO_ANSI_CPRNG is not set 1349# CONFIG_CRYPTO_ANSI_CPRNG is not set
1324# CONFIG_CRYPTO_HW is not set 1350# CONFIG_CRYPTO_HW is not set
1351# CONFIG_BINARY_PRINTF is not set
1325 1352
1326# 1353#
1327# Library routines 1354# Library routines
diff --git a/arch/sh/drivers/dma/Kconfig b/arch/sh/drivers/dma/Kconfig
index 666713ac5fcf..63e9dd30b41c 100644
--- a/arch/sh/drivers/dma/Kconfig
+++ b/arch/sh/drivers/dma/Kconfig
@@ -16,7 +16,8 @@ config SH_DMA_IRQ_MULTI
16 CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7750R || \ 16 CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7750R || \
17 CPU_SUBTYPE_SH7751R || CPU_SUBTYPE_SH7091 || \ 17 CPU_SUBTYPE_SH7751R || CPU_SUBTYPE_SH7091 || \
18 CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7764 || \ 18 CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7764 || \
19 CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 19 CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785 || \
20 CPU_SUBTYPE_SH7760
20 21
21config NR_ONCHIP_DMA_CHANNELS 22config NR_ONCHIP_DMA_CHANNELS
22 int 23 int
diff --git a/arch/sh/drivers/pci/Kconfig b/arch/sh/drivers/pci/Kconfig
index 7e816ededed7..e8db585a6638 100644
--- a/arch/sh/drivers/pci/Kconfig
+++ b/arch/sh/drivers/pci/Kconfig
@@ -17,21 +17,3 @@ config SH_PCIDMA_NONCOHERENT
17 code will not have to flush the CPU's caches. If you have a PCI host 17 code will not have to flush the CPU's caches. If you have a PCI host
18 bridge integrated with your SH CPU, refer carefully to the chip specs 18 bridge integrated with your SH CPU, refer carefully to the chip specs
19 to see if you can say 'N' here. Otherwise, leave it as 'Y'. 19 to see if you can say 'N' here. Otherwise, leave it as 'Y'.
20
21# This is also board-specific
22config PCI_AUTO
23 bool
24 depends on PCI
25 default y
26
27config PCI_AUTO_UPDATE_RESOURCES
28 bool
29 depends on PCI_AUTO
30 default y if !SH_DREAMCAST
31 help
32 Selecting this option will cause the PCI auto code to leave your
33 BAR values alone. Otherwise they will be updated automatically. If
34 for some reason, you have a board that simply refuses to work
35 with its resources updated beyond what they are when the device
36 is powered up, set this to N. Everyone else will want this as Y.
37
diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile
index 847e90894d1b..d2ffc477549a 100644
--- a/arch/sh/drivers/pci/Makefile
+++ b/arch/sh/drivers/pci/Makefile
@@ -1,9 +1,7 @@
1# 1#
2# Makefile for the PCI specific kernel interface routines under Linux. 2# Makefile for the PCI specific kernel interface routines under Linux.
3# 3#
4
5obj-y += pci.o 4obj-y += pci.o
6obj-$(CONFIG_PCI_AUTO) += pci-auto.o
7 5
8obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o 6obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o
9obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o 7obj-$(CONFIG_CPU_SUBTYPE_SH7751R) += pci-sh7751.o ops-sh4.o
@@ -12,15 +10,17 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7785) += pci-sh7780.o ops-sh4.o
13obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o 11obj-$(CONFIG_CPU_SH5) += pci-sh5.o ops-sh5.o
14 12
15obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o 13obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
16obj-$(CONFIG_SH_SECUREEDGE5410) += ops-snapgear.o 14 pci-dreamcast.o
17obj-$(CONFIG_SH_RTS7751R2D) += ops-rts7751r2d.o fixups-rts7751r2d.o 15obj-$(CONFIG_SH_SECUREEDGE5410) += fixups-snapgear.o
18obj-$(CONFIG_SH_SH03) += ops-sh03.o fixups-sh03.o 16obj-$(CONFIG_SH_7751_SOLUTION_ENGINE) += fixups-se7751.o
19obj-$(CONFIG_SH_HIGHLANDER) += ops-r7780rp.o fixups-r7780rp.o 17obj-$(CONFIG_SH_RTS7751R2D) += fixups-rts7751r2d.o
20obj-$(CONFIG_SH_SDK7780) += ops-sdk7780.o fixups-sdk7780.o 18obj-$(CONFIG_SH_SH03) += fixups-sh03.o
21obj-$(CONFIG_SH_TITAN) += ops-titan.o 19obj-$(CONFIG_SH_HIGHLANDER) += fixups-r7780rp.o
22obj-$(CONFIG_SH_LANDISK) += ops-landisk.o 20obj-$(CONFIG_SH_SH7785LCR) += fixups-r7780rp.o
23obj-$(CONFIG_SH_LBOX_RE2) += ops-lboxre2.o fixups-lboxre2.o 21obj-$(CONFIG_SH_SDK7780) += fixups-sdk7780.o
24obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += ops-se7780.o fixups-se7780.o 22obj-$(CONFIG_SH_7780_SOLUTION_ENGINE) += fixups-sdk7780.o
25obj-$(CONFIG_SH_CAYMAN) += ops-cayman.o 23obj-$(CONFIG_SH_TITAN) += fixups-titan.o
26obj-$(CONFIG_SH_SH7785LCR) += ops-sh7785lcr.o fixups-sh7785lcr.o 24obj-$(CONFIG_SH_LANDISK) += fixups-landisk.o
25obj-$(CONFIG_SH_LBOX_RE2) += fixups-rts7751r2d.o
26obj-$(CONFIG_SH_CAYMAN) += fixups-cayman.o
diff --git a/arch/sh/drivers/pci/ops-cayman.c b/arch/sh/drivers/pci/fixups-cayman.c
index 38ef76207af6..b68b61d22c6c 100644
--- a/arch/sh/drivers/pci/ops-cayman.c
+++ b/arch/sh/drivers/pci/fixups-cayman.c
@@ -75,15 +75,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin)
75 75
76 return result; 76 return result;
77} 77}
78
79struct pci_channel board_pci_channels[] = {
80 { &sh5_pci_ops, NULL, NULL, 0, 0xff },
81 { NULL, NULL, NULL, 0, 0 },
82};
83EXPORT_SYMBOL(board_pci_channels);
84
85int __init pcibios_init_platform(void)
86{
87 return sh5pci_init(__pa(memory_start),
88 __pa(memory_end) - __pa(memory_start));
89}
diff --git a/arch/sh/drivers/pci/fixups-dreamcast.c b/arch/sh/drivers/pci/fixups-dreamcast.c
index 2bf85cf091e1..ed7f489936f1 100644
--- a/arch/sh/drivers/pci/fixups-dreamcast.c
+++ b/arch/sh/drivers/pci/fixups-dreamcast.c
@@ -30,7 +30,7 @@
30 30
31static void __init gapspci_fixup_resources(struct pci_dev *dev) 31static void __init gapspci_fixup_resources(struct pci_dev *dev)
32{ 32{
33 struct pci_channel *p = board_pci_channels; 33 struct pci_channel *p = dev->sysdata;
34 34
35 printk(KERN_NOTICE "PCI: Fixing up device %s\n", pci_name(dev)); 35 printk(KERN_NOTICE "PCI: Fixing up device %s\n", pci_name(dev));
36 36
@@ -41,6 +41,13 @@ static void __init gapspci_fixup_resources(struct pci_dev *dev)
41 */ 41 */
42 dev->resource[1].start = p->io_resource->start + 0x100; 42 dev->resource[1].start = p->io_resource->start + 0x100;
43 dev->resource[1].end = dev->resource[1].start + 0x200 - 1; 43 dev->resource[1].end = dev->resource[1].start + 0x200 - 1;
44
45 /*
46 * This is not a normal BAR, prevent any attempts to move
47 * the BAR, as this will result in a bus lock.
48 */
49 dev->resource[1].flags |= IORESOURCE_PCI_FIXED;
50
44 /* 51 /*
45 * Redirect dma memory allocations to special memory window. 52 * Redirect dma memory allocations to special memory window.
46 */ 53 */
diff --git a/arch/sh/drivers/pci/ops-landisk.c b/arch/sh/drivers/pci/fixups-landisk.c
index bff09ecf3419..bb1a6bb5149e 100644
--- a/arch/sh/drivers/pci/ops-landisk.c
+++ b/arch/sh/drivers/pci/fixups-landisk.c
@@ -15,39 +15,6 @@
15#include <linux/pci.h> 15#include <linux/pci.h>
16#include "pci-sh4.h" 16#include "pci-sh4.h"
17 17
18static struct resource sh7751_io_resource = {
19 .name = "SH7751 IO",
20 .start = SH7751_PCI_IO_BASE,
21 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
22 .flags = IORESOURCE_IO
23};
24
25static struct resource sh7751_mem_resource = {
26 .name = "SH7751 mem",
27 .start = SH7751_PCI_MEMORY_BASE,
28 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
29 .flags = IORESOURCE_MEM
30};
31
32struct pci_channel board_pci_channels[] = {
33 {&sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0x3ff},
34 {NULL, NULL, NULL, 0, 0},
35};
36
37static struct sh4_pci_address_map sh7751_pci_map = {
38 .window0 = {
39 .base = SH7751_CS3_BASE_ADDR,
40 .size = (64 << 20), /* 64MB */
41 },
42
43 .flags = SH4_PCIC_NO_RESET,
44};
45
46int __init pcibios_init_platform(void)
47{
48 return sh7751_pcic_init(&sh7751_pci_map);
49}
50
51int pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) 18int pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
52{ 19{
53 /* 20 /*
diff --git a/arch/sh/drivers/pci/fixups-lboxre2.c b/arch/sh/drivers/pci/fixups-lboxre2.c
deleted file mode 100644
index 1c1d41255ec0..000000000000
--- a/arch/sh/drivers/pci/fixups-lboxre2.c
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * arch/sh/drivers/pci/fixups-lboxre2.c
3 *
4 * L-BOX RE2 PCI fixups
5 *
6 * Copyright (C) 2007 Nobuhiro Iwamatsu
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include "pci-sh4.h"
13
14#define PCIMCR_MRSET_OFF 0xBFFFFFFF
15#define PCIMCR_RFSH_OFF 0xFFFFFFFB
16
17int pci_fixup_pcic(void)
18{
19 unsigned long bcr1, mcr;
20
21 bcr1 = ctrl_inl(SH7751_BCR1);
22 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
23 pci_write_reg(bcr1, SH4_PCIBCR1);
24
25 /* Enable all interrupts, so we known what to fix */
26 pci_write_reg(0x0000c3ff, SH4_PCIINTM);
27 pci_write_reg(0x0000380f, SH4_PCIAINTM);
28 pci_write_reg(0xfb900047, SH7751_PCICONF1);
29 pci_write_reg(0xab000001, SH7751_PCICONF4);
30
31 mcr = ctrl_inl(SH7751_MCR);
32 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
33 pci_write_reg(mcr, SH4_PCIMCR);
34
35 pci_write_reg(0x0c000000, SH7751_PCICONF5);
36 pci_write_reg(0xd0000000, SH7751_PCICONF6);
37 pci_write_reg(0x0c000000, SH4_PCILAR0);
38 pci_write_reg(0x00000000, SH4_PCILAR1);
39
40 return 0;
41}
diff --git a/arch/sh/drivers/pci/fixups-r7780rp.c b/arch/sh/drivers/pci/fixups-r7780rp.c
index 3e321df65d22..15ca65cb667e 100644
--- a/arch/sh/drivers/pci/fixups-r7780rp.c
+++ b/arch/sh/drivers/pci/fixups-r7780rp.c
@@ -11,35 +11,26 @@
11 * for more details. 11 * for more details.
12 */ 12 */
13#include <linux/pci.h> 13#include <linux/pci.h>
14#include <linux/io.h>
14#include "pci-sh4.h" 15#include "pci-sh4.h"
15#include <asm/io.h>
16 16
17int pci_fixup_pcic(void) 17static char irq_tab[] __initdata = {
18{ 18 65, 66, 67, 68,
19 pci_write_reg(0x000043ff, SH4_PCIINTM); 19};
20 pci_write_reg(0x0000380f, SH4_PCIAINTM);
21
22 pci_write_reg(0xfbb00047, SH7780_PCICMD);
23 pci_write_reg(0x00000000, SH7780_PCIIBAR);
24
25 pci_write_reg(0x00011912, SH7780_PCISVID);
26 pci_write_reg(0x08000000, SH7780_PCICSCR0);
27 pci_write_reg(0x0000001b, SH7780_PCICSAR0);
28 pci_write_reg(0xfd000000, SH7780_PCICSCR1);
29 pci_write_reg(0x0000000f, SH7780_PCICSAR1);
30
31 pci_write_reg(0xfd000000, SH7780_PCIMBR0);
32 pci_write_reg(0x00fc0000, SH7780_PCIMBMR0);
33 20
34#ifdef CONFIG_32BIT 21int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
35 pci_write_reg(0xc0000000, SH7780_PCIMBR2); 22{
36 pci_write_reg(0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2); 23 return irq_tab[slot];
37#endif 24}
38 25
39 /* Set IOBR for windows containing area specified in pci.h */ 26int pci_fixup_pcic(struct pci_channel *chan)
40 pci_write_reg((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)), 27{
41 SH7780_PCIIOBR); 28 pci_write_reg(chan, 0x000043ff, SH4_PCIINTM);
42 pci_write_reg(((SH7780_PCI_IO_SIZE-1) & (7<<18)), SH7780_PCIIOBMR); 29 pci_write_reg(chan, 0x00000000, SH7780_PCIIBAR);
30 pci_write_reg(chan, 0x08000000, SH7780_PCICSCR0);
31 pci_write_reg(chan, 0x0000001b, SH7780_PCICSAR0);
32 pci_write_reg(chan, 0xfd000000, SH7780_PCICSCR1);
33 pci_write_reg(chan, 0x0000000f, SH7780_PCICSAR1);
43 34
44 return 0; 35 return 0;
45} 36}
diff --git a/arch/sh/drivers/pci/fixups-rts7751r2d.c b/arch/sh/drivers/pci/fixups-rts7751r2d.c
index 904bce8768d3..052b354236dc 100644
--- a/arch/sh/drivers/pci/fixups-rts7751r2d.c
+++ b/arch/sh/drivers/pci/fixups-rts7751r2d.c
@@ -1,43 +1,67 @@
1/* 1/*
2 * arch/sh/drivers/pci/fixups-rts7751r2d.c 2 * arch/sh/drivers/pci/fixups-rts7751r2d.c
3 * 3 *
4 * RTS7751R2D PCI fixups 4 * RTS7751R2D / LBOXRE2 PCI fixups
5 * 5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc. 6 * Copyright (C) 2003 Lineo uSolutions, Inc.
7 * Copyright (C) 2004 Paul Mundt 7 * Copyright (C) 2004 Paul Mundt
8 * Copyright (C) 2007 Nobuhiro Iwamatsu
8 * 9 *
9 * This file is subject to the terms and conditions of the GNU General Public 10 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive 11 * License. See the file "COPYING" in the main directory of this archive
11 * for more details. 12 * for more details.
12 */ 13 */
14#include <linux/pci.h>
15#include <mach/lboxre2.h>
16#include <mach/r2d.h>
13#include "pci-sh4.h" 17#include "pci-sh4.h"
18#include <asm/machtypes.h>
14 19
15#define PCIMCR_MRSET_OFF 0xBFFFFFFF 20#define PCIMCR_MRSET_OFF 0xBFFFFFFF
16#define PCIMCR_RFSH_OFF 0xFFFFFFFB 21#define PCIMCR_RFSH_OFF 0xFFFFFFFB
17 22
18int pci_fixup_pcic(void) 23static u8 rts7751r2d_irq_tab[] __initdata = {
24 IRQ_PCI_INTA,
25 IRQ_PCI_INTB,
26 IRQ_PCI_INTC,
27 IRQ_PCI_INTD,
28};
29
30static char lboxre2_irq_tab[] __initdata = {
31 IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD,
32};
33
34int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
35{
36 if (mach_is_lboxre2())
37 return lboxre2_irq_tab[slot];
38 else
39 return rts7751r2d_irq_tab[slot];
40}
41
42int pci_fixup_pcic(struct pci_channel *chan)
19{ 43{
20 unsigned long bcr1, mcr; 44 unsigned long bcr1, mcr;
21 45
22 bcr1 = ctrl_inl(SH7751_BCR1); 46 bcr1 = ctrl_inl(SH7751_BCR1);
23 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ 47 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
24 pci_write_reg(bcr1, SH4_PCIBCR1); 48 pci_write_reg(chan, bcr1, SH4_PCIBCR1);
25 49
26 /* Enable all interrupts, so we known what to fix */ 50 /* Enable all interrupts, so we known what to fix */
27 pci_write_reg(0x0000c3ff, SH4_PCIINTM); 51 pci_write_reg(chan, 0x0000c3ff, SH4_PCIINTM);
28 pci_write_reg(0x0000380f, SH4_PCIAINTM); 52 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
29 53
30 pci_write_reg(0xfb900047, SH7751_PCICONF1); 54 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
31 pci_write_reg(0xab000001, SH7751_PCICONF4); 55 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
32 56
33 mcr = ctrl_inl(SH7751_MCR); 57 mcr = ctrl_inl(SH7751_MCR);
34 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; 58 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
35 pci_write_reg(mcr, SH4_PCIMCR); 59 pci_write_reg(chan, mcr, SH4_PCIMCR);
36 60
37 pci_write_reg(0x0c000000, SH7751_PCICONF5); 61 pci_write_reg(chan, 0x0c000000, SH7751_PCICONF5);
38 pci_write_reg(0xd0000000, SH7751_PCICONF6); 62 pci_write_reg(chan, 0xd0000000, SH7751_PCICONF6);
39 pci_write_reg(0x0c000000, SH4_PCILAR0); 63 pci_write_reg(chan, 0x0c000000, SH4_PCILAR0);
40 pci_write_reg(0x00000000, SH4_PCILAR1); 64 pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
41 65
42 return 0; 66 return 0;
43} 67}
diff --git a/arch/sh/drivers/pci/fixups-sdk7780.c b/arch/sh/drivers/pci/fixups-sdk7780.c
index 2f8863099dd1..250b0edd7365 100644
--- a/arch/sh/drivers/pci/fixups-sdk7780.c
+++ b/arch/sh/drivers/pci/fixups-sdk7780.c
@@ -5,55 +5,48 @@
5 * 5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc. 6 * Copyright (C) 2003 Lineo uSolutions, Inc.
7 * Copyright (C) 2004 - 2006 Paul Mundt 7 * Copyright (C) 2004 - 2006 Paul Mundt
8 * Copyright (C) 2006 Nobuhiro Iwamatsu
8 * 9 *
9 * This file is subject to the terms and conditions of the GNU General Public 10 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive 11 * License. See the file "COPYING" in the main directory of this archive
11 * for more details. 12 * for more details.
12 */ 13 */
13#include <linux/pci.h> 14#include <linux/pci.h>
15#include <linux/io.h>
14#include "pci-sh4.h" 16#include "pci-sh4.h"
15#include <asm/io.h>
16 17
17int pci_fixup_pcic(void) 18/* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */
19static char sdk7780_irq_tab[4][16] __initdata = {
20 /* INTA */
21 { 65, 68, 67, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
22 /* INTB */
23 { 66, 65, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
24 /* INTC */
25 { 67, 66, -1, 66, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
26 /* INTD */
27 { 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
28};
29
30int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
31{
32 return sdk7780_irq_tab[pin-1][slot];
33}
34int pci_fixup_pcic(struct pci_channel *chan)
18{ 35{
19 ctrl_outl(0x00000001, SH7780_PCI_VCR2);
20
21 /* Enable all interrupts, so we know what to fix */ 36 /* Enable all interrupts, so we know what to fix */
22 pci_write_reg(0x0000C3FF, SH7780_PCIIMR); 37 pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);
23 pci_write_reg(0x0000380F, SH7780_PCIAINTM);
24 38
25 /* Set up standard PCI config registers */ 39 /* Set up standard PCI config registers */
26 pci_write_reg(0xFB00, SH7780_PCISTATUS); 40 pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0); /* PCI */
27 pci_write_reg(0x0047, SH7780_PCICMD); 41 pci_write_reg(chan, 0x08000000, SH4_PCILAR0); /* SHwy */
28 pci_write_reg(0x00, SH7780_PCIPIF); 42 pci_write_reg(chan, 0x07F00001, SH4_PCILSR0); /* size 128M w/ MBAR */
29 pci_write_reg(0x00, SH7780_PCISUB);
30 pci_write_reg(0x06, SH7780_PCIBCC);
31 pci_write_reg(0x1912, SH7780_PCISVID);
32 pci_write_reg(0x0001, SH7780_PCISID);
33
34 pci_write_reg(0x08000000, SH7780_PCIMBAR0); /* PCI */
35 pci_write_reg(0x08000000, SH7780_PCILAR0); /* SHwy */
36 pci_write_reg(0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */
37
38 pci_write_reg(0x00000000, SH7780_PCIMBAR1);
39 pci_write_reg(0x00000000, SH7780_PCILAR1);
40 pci_write_reg(0x00000000, SH7780_PCILSR1);
41
42 pci_write_reg(0xAB000801, SH7780_PCIIBAR);
43
44 /*
45 * Set the MBR so PCI address is one-to-one with window,
46 * meaning all calls go straight through... use ifdef to
47 * catch erroneous assumption.
48 */
49 pci_write_reg(0xFD000000 , SH7780_PCIMBR0);
50 pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
51 43
52 /* Set IOBR for window containing area specified in pci.h */ 44 pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);
53 pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR); 45 pci_write_reg(chan, 0x00000000, SH4_PCILAR1);
54 pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR); 46 pci_write_reg(chan, 0x00000000, SH4_PCILSR1);
55 47
56 pci_write_reg(0xA5000C01, SH7780_PCICR); 48 pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);
49 pci_write_reg(chan, 0xA5000C01, SH4_PCICR);
57 50
58 return 0; 51 return 0;
59} 52}
diff --git a/arch/sh/drivers/pci/fixups-se7751.c b/arch/sh/drivers/pci/fixups-se7751.c
new file mode 100644
index 000000000000..475fa9f0fe2c
--- /dev/null
+++ b/arch/sh/drivers/pci/fixups-se7751.c
@@ -0,0 +1,111 @@
1#include <linux/kernel.h>
2#include <linux/types.h>
3#include <linux/init.h>
4#include <linux/delay.h>
5#include <linux/pci.h>
6#include <linux/io.h>
7#include "pci-sh4.h"
8
9int __init pcibios_map_platform_irq(u8 slot, u8 pin)
10{
11 switch (slot) {
12 case 0: return 13;
13 case 1: return 13; /* AMD Ethernet controller */
14 case 2: return -1;
15 case 3: return -1;
16 case 4: return -1;
17 default:
18 printk("PCI: Bad IRQ mapping request for slot %d\n", slot);
19 return -1;
20 }
21}
22
23#define PCIMCR_MRSET_OFF 0xBFFFFFFF
24#define PCIMCR_RFSH_OFF 0xFFFFFFFB
25
26/*
27 * Only long word accesses of the PCIC's internal local registers and the
28 * configuration registers from the CPU is supported.
29 */
30#define PCIC_WRITE(x,v) writel((v), PCI_REG(x))
31#define PCIC_READ(x) readl(PCI_REG(x))
32
33/*
34 * Description: This function sets up and initializes the pcic, sets
35 * up the BARS, maps the DRAM into the address space etc, etc.
36 */
37int pci_fixup_pcic(struct pci_channel *chan)
38{
39 unsigned long bcr1, wcr1, wcr2, wcr3, mcr;
40 unsigned short bcr2;
41
42 /*
43 * Initialize the slave bus controller on the pcic. The values used
44 * here should not be hardcoded, but they should be taken from the bsc
45 * on the processor, to make this function as generic as possible.
46 * (i.e. Another sbc may usr different SDRAM timing settings -- in order
47 * for the pcic to work, its settings need to be exactly the same.)
48 */
49 bcr1 = (*(volatile unsigned long*)(SH7751_BCR1));
50 bcr2 = (*(volatile unsigned short*)(SH7751_BCR2));
51 wcr1 = (*(volatile unsigned long*)(SH7751_WCR1));
52 wcr2 = (*(volatile unsigned long*)(SH7751_WCR2));
53 wcr3 = (*(volatile unsigned long*)(SH7751_WCR3));
54 mcr = (*(volatile unsigned long*)(SH7751_MCR));
55
56 bcr1 = bcr1 | 0x00080000; /* Enable Bit 19, BREQEN */
57 (*(volatile unsigned long*)(SH7751_BCR1)) = bcr1;
58
59 bcr1 = bcr1 | 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
60 PCIC_WRITE(SH7751_PCIBCR1, bcr1); /* PCIC BCR1 */
61 PCIC_WRITE(SH7751_PCIBCR2, bcr2); /* PCIC BCR2 */
62 PCIC_WRITE(SH7751_PCIWCR1, wcr1); /* PCIC WCR1 */
63 PCIC_WRITE(SH7751_PCIWCR2, wcr2); /* PCIC WCR2 */
64 PCIC_WRITE(SH7751_PCIWCR3, wcr3); /* PCIC WCR3 */
65 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
66 PCIC_WRITE(SH7751_PCIMCR, mcr); /* PCIC MCR */
67
68
69 /* Enable all interrupts, so we know what to fix */
70 PCIC_WRITE(SH7751_PCIINTM, 0x0000c3ff);
71 PCIC_WRITE(SH7751_PCIAINTM, 0x0000380f);
72
73 /* Set up standard PCI config registers */
74 PCIC_WRITE(SH7751_PCICONF1, 0xF39000C7); /* Bus Master, Mem & I/O access */
75 PCIC_WRITE(SH7751_PCICONF2, 0x00000000); /* PCI Class code & Revision ID */
76 PCIC_WRITE(SH7751_PCICONF4, 0xab000001); /* PCI I/O address (local regs) */
77 PCIC_WRITE(SH7751_PCICONF5, 0x0c000000); /* PCI MEM address (local RAM) */
78 PCIC_WRITE(SH7751_PCICONF6, 0xd0000000); /* PCI MEM address (unused) */
79 PCIC_WRITE(SH7751_PCICONF11, 0x35051054); /* PCI Subsystem ID & Vendor ID */
80 PCIC_WRITE(SH7751_PCILSR0, 0x03f00000); /* MEM (full 64M exposed) */
81 PCIC_WRITE(SH7751_PCILSR1, 0x00000000); /* MEM (unused) */
82 PCIC_WRITE(SH7751_PCILAR0, 0x0c000000); /* MEM (direct map from PCI) */
83 PCIC_WRITE(SH7751_PCILAR1, 0x00000000); /* MEM (unused) */
84
85 /* Now turn it on... */
86 PCIC_WRITE(SH7751_PCICR, 0xa5000001);
87
88 /*
89 * Set PCIMBR and PCIIOBR here, assuming a single window
90 * (16M MEM, 256K IO) is enough. If a larger space is
91 * needed, the readx/writex and inx/outx functions will
92 * have to do more (e.g. setting registers for each call).
93 */
94
95 /*
96 * Set the MBR so PCI address is one-to-one with window,
97 * meaning all calls go straight through... use BUG_ON to
98 * catch erroneous assumption.
99 */
100 BUG_ON(chan->mem_resource->start != SH7751_PCI_MEMORY_BASE);
101
102 PCIC_WRITE(SH7751_PCIMBR, chan->mem_resource->start);
103
104 /* Set IOBR for window containing area specified in pci.h */
105 PCIC_WRITE(SH7751_PCIIOBR, (chan->io_resource->start & SH7751_PCIIOBR_MASK));
106
107 /* All done, may as well say so... */
108 printk("SH7751 PCI: Finished initialization of the PCI controller\n");
109
110 return 1;
111}
diff --git a/arch/sh/drivers/pci/fixups-se7780.c b/arch/sh/drivers/pci/fixups-se7780.c
deleted file mode 100644
index 880cea1c0d89..000000000000
--- a/arch/sh/drivers/pci/fixups-se7780.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * arch/sh/drivers/pci/fixups-se7780.c
3 *
4 * HITACHI UL Solution Engine 7780 PCI fixups
5 *
6 * Copyright (C) 2003 Lineo uSolutions, Inc.
7 * Copyright (C) 2004 - 2006 Paul Mundt
8 * Copyright (C) 2006 Nobuhiro Iwamatsu
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <linux/pci.h>
15#include "pci-sh4.h"
16#include <asm/io.h>
17
18int pci_fixup_pcic(void)
19{
20 ctrl_outl(0x00000001, SH7780_PCI_VCR2);
21
22 /* Enable all interrupts, so we know what to fix */
23 pci_write_reg(0x0000C3FF, SH7780_PCIIMR);
24 pci_write_reg(0x0000380F, SH7780_PCIAINTM);
25
26 /* Set up standard PCI config registers */
27 ctrl_outw(0xFB00, PCI_REG(SH7780_PCISTATUS));
28 ctrl_outw(0x0047, PCI_REG(SH7780_PCICMD));
29 ctrl_outb( 0x00, PCI_REG(SH7780_PCIPIF));
30 ctrl_outb( 0x00, PCI_REG(SH7780_PCISUB));
31 ctrl_outb( 0x06, PCI_REG(SH7780_PCIBCC));
32 ctrl_outw(0x1912, PCI_REG(SH7780_PCISVID));
33 ctrl_outw(0x0001, PCI_REG(SH7780_PCISID));
34
35 pci_write_reg(0x08000000, SH7780_PCIMBAR0); /* PCI */
36 pci_write_reg(0x08000000, SH7780_PCILAR0); /* SHwy */
37 pci_write_reg(0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */
38
39 pci_write_reg(0x00000000, SH7780_PCIMBAR1);
40 pci_write_reg(0x00000000, SH7780_PCILAR1);
41 pci_write_reg(0x00000000, SH7780_PCILSR1);
42
43 pci_write_reg(0xAB000801, SH7780_PCIIBAR);
44
45 /*
46 * Set the MBR so PCI address is one-to-one with window,
47 * meaning all calls go straight through... use ifdef to
48 * catch erroneous assumption.
49 */
50 pci_write_reg(0xFD000000 , SH7780_PCIMBR0);
51 pci_write_reg(0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
52
53 /* Set IOBR for window containing area specified in pci.h */
54 pci_write_reg(PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1), SH7780_PCIIOBR);
55 pci_write_reg((SH7780_PCI_IO_SIZE-1) & (7 << 18), SH7780_PCIIOBMR);
56
57 pci_write_reg(0xA5000C01, SH7780_PCICR);
58
59 return 0;
60}
diff --git a/arch/sh/drivers/pci/fixups-sh7785lcr.c b/arch/sh/drivers/pci/fixups-sh7785lcr.c
deleted file mode 100644
index 4949e601387a..000000000000
--- a/arch/sh/drivers/pci/fixups-sh7785lcr.c
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * arch/sh/drivers/pci/fixups-sh7785lcr.c
3 *
4 * R0P7785LC0011RL PCI fixups
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * Based on arch/sh/drivers/pci/fixups-r7780rp.c
8 * Copyright (C) 2003 Lineo uSolutions, Inc.
9 * Copyright (C) 2004 - 2006 Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/pci.h>
16#include "pci-sh4.h"
17
18int pci_fixup_pcic(void)
19{
20 pci_write_reg(0x000043ff, SH4_PCIINTM);
21 pci_write_reg(0x0000380f, SH4_PCIAINTM);
22
23 pci_write_reg(0xfbb00047, SH7780_PCICMD);
24 pci_write_reg(0x00000000, SH7780_PCIIBAR);
25
26 pci_write_reg(0x00011912, SH7780_PCISVID);
27 pci_write_reg(0x08000000, SH7780_PCICSCR0);
28 pci_write_reg(0x0000001b, SH7780_PCICSAR0);
29 pci_write_reg(0xfd000000, SH7780_PCICSCR1);
30 pci_write_reg(0x0000000f, SH7780_PCICSAR1);
31
32 pci_write_reg(0xfd000000, SH7780_PCIMBR0);
33 pci_write_reg(0x00fc0000, SH7780_PCIMBMR0);
34
35#ifdef CONFIG_32BIT
36 pci_write_reg(0xc0000000, SH7780_PCIMBR2);
37 pci_write_reg(0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
38#endif
39
40 /* Set IOBR for windows containing area specified in pci.h */
41 pci_write_reg((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)),
42 SH7780_PCIIOBR);
43 pci_write_reg(((SH7780_PCI_IO_SIZE - 1) & (7 << 18)), SH7780_PCIIOBMR);
44
45 return 0;
46}
diff --git a/arch/sh/drivers/pci/fixups-snapgear.c b/arch/sh/drivers/pci/fixups-snapgear.c
new file mode 100644
index 000000000000..5a39ecc1adb8
--- /dev/null
+++ b/arch/sh/drivers/pci/fixups-snapgear.c
@@ -0,0 +1,38 @@
1/*
2 * arch/sh/drivers/pci/ops-snapgear.c
3 *
4 * Author: David McCullough <davidm@snapgear.com>
5 *
6 * Ported to new API by Paul Mundt <lethal@linux-sh.org>
7 *
8 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
9 *
10 * May be copied or modified under the terms of the GNU General Public
11 * License. See linux/COPYING for more information.
12 *
13 * PCI initialization for the SnapGear boards
14 */
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/init.h>
18#include <linux/pci.h>
19#include "pci-sh4.h"
20
21int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
22{
23 int irq = -1;
24
25 switch (slot) {
26 case 8: /* the PCI bridge */ break;
27 case 11: irq = 8; break; /* USB */
28 case 12: irq = 11; break; /* PCMCIA */
29 case 13: irq = 5; break; /* eth0 */
30 case 14: irq = 8; break; /* eth1 */
31 case 15: irq = 11; break; /* safenet (unused) */
32 }
33
34 printk("PCI: Mapping SnapGear IRQ for slot %d, pin %c to irq %d\n",
35 slot, pin - 1 + 'A', irq);
36
37 return irq;
38}
diff --git a/arch/sh/drivers/pci/ops-titan.c b/arch/sh/drivers/pci/fixups-titan.c
index a8f7801a34af..3a79fa8254a6 100644
--- a/arch/sh/drivers/pci/ops-titan.c
+++ b/arch/sh/drivers/pci/fixups-titan.c
@@ -36,42 +36,3 @@ int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
36 36
37 return irq; 37 return irq;
38} 38}
39
40static struct resource sh7751_io_resource = {
41 .name = "SH7751_IO",
42 .start = SH7751_PCI_IO_BASE,
43 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
44 .flags = IORESOURCE_IO
45};
46
47static struct resource sh7751_mem_resource = {
48 .name = "SH7751_mem",
49 .start = SH7751_PCI_MEMORY_BASE,
50 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
51 .flags = IORESOURCE_MEM
52};
53
54struct pci_channel board_pci_channels[] = {
55 { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
56 { NULL, NULL, NULL, 0, 0 },
57};
58EXPORT_SYMBOL(board_pci_channels);
59
60static struct sh4_pci_address_map sh7751_pci_map = {
61 .window0 = {
62 .base = SH7751_CS2_BASE_ADDR,
63 .size = SH7751_MEM_REGION_SIZE*2, /* cs2 and cs3 */
64 },
65
66 .window1 = {
67 .base = SH7751_CS2_BASE_ADDR,
68 .size = SH7751_MEM_REGION_SIZE*2,
69 },
70
71 .flags = SH4_PCIC_NO_RESET,
72};
73
74int __init pcibios_init_platform(void)
75{
76 return sh7751_pcic_init(&sh7751_pci_map);
77}
diff --git a/arch/sh/drivers/pci/ops-dreamcast.c b/arch/sh/drivers/pci/ops-dreamcast.c
index f5d2a2aa6f3f..e83d0d3aabe2 100644
--- a/arch/sh/drivers/pci/ops-dreamcast.c
+++ b/arch/sh/drivers/pci/ops-dreamcast.c
@@ -1,15 +1,9 @@
1/* 1/*
2 * arch/sh/drivers/pci/ops-dreamcast.c
3 *
4 * PCI operations for the Sega Dreamcast 2 * PCI operations for the Sega Dreamcast
5 * 3 *
6 * Copyright (C) 2001, 2002 M. R. Brown 4 * Copyright (C) 2001, 2002 M. R. Brown
7 * Copyright (C) 2002, 2003 Paul Mundt 5 * Copyright (C) 2002, 2003 Paul Mundt
8 * 6 *
9 * This file originally bore the message (with enclosed-$):
10 * Id: pci.c,v 1.3 2003/05/04 19:29:46 lethal Exp
11 * Dreamcast PCI: Supports SEGA Broadband Adaptor only.
12 *
13 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
15 * for more details. 9 * for more details.
@@ -23,34 +17,10 @@
23#include <linux/irq.h> 17#include <linux/irq.h>
24#include <linux/pci.h> 18#include <linux/pci.h>
25#include <linux/module.h> 19#include <linux/module.h>
26 20#include <linux/io.h>
27#include <asm/io.h> 21#include <linux/irq.h>
28#include <asm/irq.h>
29#include <mach/pci.h> 22#include <mach/pci.h>
30 23
31static struct resource gapspci_io_resource = {
32 .name = "GAPSPCI IO",
33 .start = GAPSPCI_BBA_CONFIG,
34 .end = GAPSPCI_BBA_CONFIG + GAPSPCI_BBA_CONFIG_SIZE - 1,
35 .flags = IORESOURCE_IO,
36};
37
38static struct resource gapspci_mem_resource = {
39 .name = "GAPSPCI mem",
40 .start = GAPSPCI_DMA_BASE,
41 .end = GAPSPCI_DMA_BASE + GAPSPCI_DMA_SIZE - 1,
42 .flags = IORESOURCE_MEM,
43};
44
45static struct pci_ops gapspci_pci_ops;
46
47struct pci_channel board_pci_channels[] = {
48 { &gapspci_pci_ops, &gapspci_io_resource,
49 &gapspci_mem_resource, 0, 1 },
50 { 0, }
51};
52EXPORT_SYMBOL(board_pci_channels);
53
54/* 24/*
55 * The !gapspci_config_access case really shouldn't happen, ever, unless 25 * The !gapspci_config_access case really shouldn't happen, ever, unless
56 * someone implicitly messes around with the last devfn value.. otherwise we 26 * someone implicitly messes around with the last devfn value.. otherwise we
@@ -85,10 +55,10 @@ static int gapspci_read(struct pci_bus *bus, unsigned int devfn, int where, int
85 return PCIBIOS_DEVICE_NOT_FOUND; 55 return PCIBIOS_DEVICE_NOT_FOUND;
86 56
87 switch (size) { 57 switch (size) {
88 case 1: *val = inb(GAPSPCI_BBA_CONFIG+where); break; 58 case 1: *val = inb(GAPSPCI_BBA_CONFIG+where); break;
89 case 2: *val = inw(GAPSPCI_BBA_CONFIG+where); break; 59 case 2: *val = inw(GAPSPCI_BBA_CONFIG+where); break;
90 case 4: *val = inl(GAPSPCI_BBA_CONFIG+where); break; 60 case 4: *val = inl(GAPSPCI_BBA_CONFIG+where); break;
91 } 61 }
92 62
93 return PCIBIOS_SUCCESSFUL; 63 return PCIBIOS_SUCCESSFUL;
94} 64}
@@ -99,72 +69,15 @@ static int gapspci_write(struct pci_bus *bus, unsigned int devfn, int where, int
99 return PCIBIOS_DEVICE_NOT_FOUND; 69 return PCIBIOS_DEVICE_NOT_FOUND;
100 70
101 switch (size) { 71 switch (size) {
102 case 1: outb(( u8)val, GAPSPCI_BBA_CONFIG+where); break; 72 case 1: outb(( u8)val, GAPSPCI_BBA_CONFIG+where); break;
103 case 2: outw((u16)val, GAPSPCI_BBA_CONFIG+where); break; 73 case 2: outw((u16)val, GAPSPCI_BBA_CONFIG+where); break;
104 case 4: outl((u32)val, GAPSPCI_BBA_CONFIG+where); break; 74 case 4: outl((u32)val, GAPSPCI_BBA_CONFIG+where); break;
105 } 75 }
106 76
107 return PCIBIOS_SUCCESSFUL; 77 return PCIBIOS_SUCCESSFUL;
108} 78}
109 79
110static struct pci_ops gapspci_pci_ops = { 80struct pci_ops gapspci_pci_ops = {
111 .read = gapspci_read, 81 .read = gapspci_read,
112 .write = gapspci_write, 82 .write = gapspci_write,
113}; 83};
114
115/*
116 * gapspci init
117 */
118
119int __init gapspci_init(void)
120{
121 char idbuf[16];
122 int i;
123
124 /*
125 * FIXME: All of this wants documenting to some degree,
126 * even some basic register definitions would be nice.
127 *
128 * I haven't seen anything this ugly since.. maple.
129 */
130
131 for (i=0; i<16; i++)
132 idbuf[i] = inb(GAPSPCI_REGS+i);
133
134 if (strncmp(idbuf, "GAPSPCI_BRIDGE_2", 16))
135 return -ENODEV;
136
137 outl(0x5a14a501, GAPSPCI_REGS+0x18);
138
139 for (i=0; i<1000000; i++)
140 ;
141
142 if (inl(GAPSPCI_REGS+0x18) != 1)
143 return -EINVAL;
144
145 outl(0x01000000, GAPSPCI_REGS+0x20);
146 outl(0x01000000, GAPSPCI_REGS+0x24);
147
148 outl(GAPSPCI_DMA_BASE, GAPSPCI_REGS+0x28);
149 outl(GAPSPCI_DMA_BASE+GAPSPCI_DMA_SIZE, GAPSPCI_REGS+0x2c);
150
151 outl(1, GAPSPCI_REGS+0x14);
152 outl(1, GAPSPCI_REGS+0x34);
153
154 /* Setting Broadband Adapter */
155 outw(0xf900, GAPSPCI_BBA_CONFIG+0x06);
156 outl(0x00000000, GAPSPCI_BBA_CONFIG+0x30);
157 outb(0x00, GAPSPCI_BBA_CONFIG+0x3c);
158 outb(0xf0, GAPSPCI_BBA_CONFIG+0x0d);
159 outw(0x0006, GAPSPCI_BBA_CONFIG+0x04);
160 outl(0x00002001, GAPSPCI_BBA_CONFIG+0x10);
161 outl(0x01000000, GAPSPCI_BBA_CONFIG+0x14);
162
163 return 0;
164}
165
166/* Haven't done anything here as yet */
167char * __devinit pcibios_setup(char *str)
168{
169 return str;
170}
diff --git a/arch/sh/drivers/pci/ops-lboxre2.c b/arch/sh/drivers/pci/ops-lboxre2.c
deleted file mode 100644
index 86c0b6fb7375..000000000000
--- a/arch/sh/drivers/pci/ops-lboxre2.c
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * linux/arch/sh/drivers/pci/ops-lboxre2.c
3 *
4 * Copyright (C) 2007 Nobuhiro Iwamatsu
5 *
6 * PCI initialization for the NTT COMWARE L-BOX RE2
7 */
8#include <linux/kernel.h>
9#include <linux/types.h>
10#include <linux/init.h>
11#include <linux/pci.h>
12#include <linux/io.h>
13#include <mach/lboxre2.h>
14#include "pci-sh4.h"
15
16static char lboxre2_irq_tab[] __initdata = {
17 IRQ_ETH0, IRQ_ETH1, IRQ_INTA, IRQ_INTD,
18};
19
20int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
21{
22 return lboxre2_irq_tab[slot];
23}
24
25static struct resource sh7751_io_resource = {
26 .name = "SH7751_IO",
27 .start = SH7751_PCI_IO_BASE ,
28 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
29 .flags = IORESOURCE_IO
30};
31
32static struct resource sh7751_mem_resource = {
33 .name = "SH7751_mem",
34 .start = SH7751_PCI_MEMORY_BASE,
35 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
36 .flags = IORESOURCE_MEM
37};
38
39extern struct pci_ops sh7751_pci_ops;
40
41struct pci_channel board_pci_channels[] = {
42 { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
43 { NULL, NULL, NULL, 0, 0 },
44};
45
46EXPORT_SYMBOL(board_pci_channels);
47
48static struct sh4_pci_address_map sh7751_pci_map = {
49 .window0 = {
50 .base = SH7751_CS3_BASE_ADDR,
51 .size = 0x04000000,
52 },
53 .window1 = {
54 .base = 0x00000000, /* Unused */
55 .size = 0x00000000, /* Unused */
56 },
57 .flags = SH4_PCIC_NO_RESET,
58};
59
60int __init pcibios_init_platform(void)
61{
62 return sh7751_pcic_init(&sh7751_pci_map);
63}
diff --git a/arch/sh/drivers/pci/ops-r7780rp.c b/arch/sh/drivers/pci/ops-r7780rp.c
deleted file mode 100644
index 8555238e63eb..000000000000
--- a/arch/sh/drivers/pci/ops-r7780rp.c
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * Author: Ian DaSilva (idasilva@mvista.com)
3 *
4 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * PCI initialization for the Renesas SH7780 Highlander R7780RP-1 board
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pci.h>
16#include <mach/highlander.h>
17#include <asm/io.h>
18#include "pci-sh4.h"
19
20static char irq_tab[] __initdata = {
21 65, 66, 67, 68,
22};
23
24int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
25{
26 return irq_tab[slot];
27}
28
29static struct resource sh7780_io_resource = {
30 .name = "SH7780_IO",
31 .start = SH7780_PCI_IO_BASE,
32 .end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
33 .flags = IORESOURCE_IO
34};
35
36static struct resource sh7780_mem_resource = {
37 .name = "SH7780_mem",
38 .start = SH7780_PCI_MEMORY_BASE,
39 .end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
40 .flags = IORESOURCE_MEM
41};
42
43extern struct pci_ops sh7780_pci_ops;
44
45struct pci_channel board_pci_channels[] = {
46 { &sh4_pci_ops, &sh7780_io_resource, &sh7780_mem_resource, 0, 0xff },
47 { NULL, NULL, NULL, 0, 0 },
48};
49EXPORT_SYMBOL(board_pci_channels);
50
51static struct sh4_pci_address_map sh7780_pci_map = {
52 .window0 = {
53 .base = SH7780_CS2_BASE_ADDR,
54 .size = 0x04000000,
55 },
56
57 .window1 = {
58 .base = SH7780_CS3_BASE_ADDR,
59 .size = 0x04000000,
60 },
61
62 .flags = SH4_PCIC_NO_RESET,
63};
64
65int __init pcibios_init_platform(void)
66{
67 return sh7780_pcic_init(&sh7780_pci_map);
68}
diff --git a/arch/sh/drivers/pci/ops-rts7751r2d.c b/arch/sh/drivers/pci/ops-rts7751r2d.c
deleted file mode 100644
index d6ca74b25d5f..000000000000
--- a/arch/sh/drivers/pci/ops-rts7751r2d.c
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * linux/arch/sh/drivers/pci/ops-rts7751r2d.c
3 *
4 * Author: Ian DaSilva (idasilva@mvista.com)
5 *
6 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 *
11 * PCI initialization for the Renesas SH7751R RTS7751R2D board
12 */
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/io.h>
18#include <mach/r2d.h>
19#include "pci-sh4.h"
20
21static u8 rts7751r2d_irq_tab[] __initdata = {
22 IRQ_PCI_INTA,
23 IRQ_PCI_INTB,
24 IRQ_PCI_INTC,
25 IRQ_PCI_INTD,
26};
27
28int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
29{
30 return rts7751r2d_irq_tab[slot];
31}
32
33static struct resource sh7751_io_resource = {
34 .name = "SH7751_IO",
35 .start = 0x4000,
36 .end = SH7751_PCI_IO_SIZE - 1,
37 .flags = IORESOURCE_IO
38};
39
40static struct resource sh7751_mem_resource = {
41 .name = "SH7751_mem",
42 .start = SH7751_PCI_MEMORY_BASE,
43 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
44 .flags = IORESOURCE_MEM
45};
46
47extern struct pci_ops sh7751_pci_ops;
48
49struct pci_channel board_pci_channels[] = {
50 { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
51 { NULL, NULL, NULL, 0, 0 },
52};
53EXPORT_SYMBOL(board_pci_channels);
54
55static struct sh4_pci_address_map sh7751_pci_map = {
56 .window0 = {
57 .base = SH7751_CS3_BASE_ADDR,
58 .size = 0x04000000,
59 },
60
61 .window1 = {
62 .base = 0x00000000, /* Unused */
63 .size = 0x00000000, /* Unused */
64 },
65
66 .flags = SH4_PCIC_NO_RESET,
67};
68
69int __init pcibios_init_platform(void)
70{
71 __set_io_port_base(SH7751_PCI_IO_BASE);
72 return sh7751_pcic_init(&sh7751_pci_map);
73}
74
diff --git a/arch/sh/drivers/pci/ops-sdk7780.c b/arch/sh/drivers/pci/ops-sdk7780.c
deleted file mode 100644
index 4dcc64184b23..000000000000
--- a/arch/sh/drivers/pci/ops-sdk7780.c
+++ /dev/null
@@ -1,73 +0,0 @@
1/*
2 * linux/arch/sh/drivers/pci/ops-sdk7780.c
3 *
4 * Copyright (C) 2006 Nobuhiro Iwamatsu
5 *
6 * PCI initialization for the SDK7780SE03
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pci.h>
16#include <mach/sdk7780.h>
17#include <asm/io.h>
18#include "pci-sh4.h"
19
20/* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */
21static char sdk7780_irq_tab[4][16] __initdata = {
22 /* INTA */
23 { 65, 68, 67, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
24 /* INTB */
25 { 66, 65, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
26 /* INTC */
27 { 67, 66, -1, 66, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
28 /* INTD */
29 { 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
30};
31
32int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
33{
34 return sdk7780_irq_tab[pin-1][slot];
35}
36
37static struct resource sdk7780_io_resource = {
38 .name = "SH7780_IO",
39 .start = SH7780_PCI_IO_BASE,
40 .end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
41 .flags = IORESOURCE_IO
42};
43
44static struct resource sdk7780_mem_resource = {
45 .name = "SH7780_mem",
46 .start = SH7780_PCI_MEMORY_BASE,
47 .end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
48 .flags = IORESOURCE_MEM
49};
50
51struct pci_channel board_pci_channels[] = {
52 { &sh4_pci_ops, &sdk7780_io_resource, &sdk7780_mem_resource, 0, 0xff },
53 { NULL, NULL, NULL, 0, 0 },
54};
55EXPORT_SYMBOL(board_pci_channels);
56
57static struct sh4_pci_address_map sdk7780_pci_map = {
58 .window0 = {
59 .base = SH7780_CS2_BASE_ADDR,
60 .size = 0x04000000,
61 },
62 .window1 = {
63 .base = SH7780_CS3_BASE_ADDR,
64 .size = 0x04000000,
65 },
66 .flags = SH4_PCIC_NO_RESET,
67};
68
69int __init pcibios_init_platform(void)
70{
71 printk(KERN_INFO "SH7780 PCI: Finished initializing PCI controller\n");
72 return sh7780_pcic_init(&sdk7780_pci_map);
73}
diff --git a/arch/sh/drivers/pci/ops-se7780.c b/arch/sh/drivers/pci/ops-se7780.c
deleted file mode 100644
index 3145c62484d6..000000000000
--- a/arch/sh/drivers/pci/ops-se7780.c
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * linux/arch/sh/drivers/pci/ops-se7780.c
3 *
4 * Copyright (C) 2006 Nobuhiro Iwamatsu
5 *
6 * PCI initialization for the Hitachi UL Solution Engine 7780SE03
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 */
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/delay.h>
15#include <linux/pci.h>
16#include <mach-se/mach/se7780.h>
17#include <asm/io.h>
18#include "pci-sh4.h"
19
20/*
21 * IDSEL = AD16 PCI slot
22 * IDSEL = AD17 PCI slot
23 * IDSEL = AD18 Serial ATA Controller (Silicon Image SiL3512A)
24 * IDSEL = AD19 USB Host Controller (NEC uPD7210100A)
25 */
26
27/* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */
28static char se7780_irq_tab[4][16] __initdata = {
29 /* INTA */
30 { 65, 68, 67, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
31 /* INTB */
32 { 66, 65, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
33 /* INTC */
34 { 67, 66, -1, 66, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
35 /* INTD */
36 { 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
37};
38
39int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
40{
41 return se7780_irq_tab[pin-1][slot];
42}
43
44static struct resource se7780_io_resource = {
45 .name = "SH7780_IO",
46 .start = SH7780_PCI_IO_BASE,
47 .end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
48 .flags = IORESOURCE_IO
49};
50
51static struct resource se7780_mem_resource = {
52 .name = "SH7780_mem",
53 .start = SH7780_PCI_MEMORY_BASE,
54 .end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
55 .flags = IORESOURCE_MEM
56};
57
58extern struct pci_ops se7780_pci_ops;
59
60struct pci_channel board_pci_channels[] = {
61 { &sh4_pci_ops, &se7780_io_resource, &se7780_mem_resource, 0, 0xff },
62 { NULL, NULL, NULL, 0, 0 },
63};
64EXPORT_SYMBOL(board_pci_channels);
65
66static struct sh4_pci_address_map se7780_pci_map = {
67 .window0 = {
68 .base = SH7780_CS2_BASE_ADDR,
69 .size = 0x04000000,
70 },
71 .flags = SH4_PCIC_NO_RESET,
72};
73
74int __init pcibios_init_platform(void)
75{
76 printk("SH7780 PCI: Finished initialization of the PCI controller\n");
77
78 /*
79 * FPGA PCISEL register initialize
80 *
81 * CPU || SLOT1 | SLOT2 | S-ATA | USB
82 * -------------------------------------
83 * INTA || INTA | INTD | -- | INTB
84 * -------------------------------------
85 * INTB || INTB | INTA | -- | INTC
86 * -------------------------------------
87 * INTC || INTC | INTB | INTA | --
88 * -------------------------------------
89 * INTD || INTD | INTC | -- | INTA
90 * -------------------------------------
91 */
92 ctrl_outw(0x0013, FPGA_PCI_INTSEL1);
93 ctrl_outw(0xE402, FPGA_PCI_INTSEL2);
94
95 return sh7780_pcic_init(&se7780_pci_map);
96}
diff --git a/arch/sh/drivers/pci/ops-sh03.c b/arch/sh/drivers/pci/ops-sh03.c
deleted file mode 100644
index e1703ff5a4d2..000000000000
--- a/arch/sh/drivers/pci/ops-sh03.c
+++ /dev/null
@@ -1,45 +0,0 @@
1/*
2 * linux/arch/sh/drivers/pci/ops-sh03.c
3 *
4 * PCI initialization for the Interface CTP/PCI-SH03 board
5 */
6
7#include <linux/kernel.h>
8#include <linux/types.h>
9#include <linux/init.h>
10#include <linux/delay.h>
11#include <linux/pci.h>
12#include <asm/io.h>
13#include "pci-sh7751.h"
14
15/*
16 * Description: This function sets up and initializes the pcic, sets
17 * up the BARS, maps the DRAM into the address space etc, etc.
18 */
19int __init pcibios_init_platform(void)
20{
21 __set_io_port_base(SH7751_PCI_IO_BASE);
22 return 1;
23}
24
25static struct resource sh7751_io_resource = {
26 .name = "SH03 IO",
27 .start = SH7751_PCI_IO_BASE,
28 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
29 .flags = IORESOURCE_IO
30};
31
32static struct resource sh7751_mem_resource = {
33 .name = "SH03 mem",
34 .start = SH7751_PCI_MEMORY_BASE,
35 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
36 .flags = IORESOURCE_MEM
37};
38
39extern struct pci_ops sh4_pci_ops;
40
41struct pci_channel board_pci_channels[] = {
42 { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
43 { NULL, NULL, NULL, 0, 0 },
44};
45
diff --git a/arch/sh/drivers/pci/ops-sh4.c b/arch/sh/drivers/pci/ops-sh4.c
index 710a3b0306e5..78bebebdc99c 100644
--- a/arch/sh/drivers/pci/ops-sh4.c
+++ b/arch/sh/drivers/pci/ops-sh4.c
@@ -1,22 +1,22 @@
1/* 1/*
2 * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780). 2 * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780).
3 * 3 *
4 * Copyright (C) 2002 - 2006 Paul Mundt 4 * Copyright (C) 2002 - 2009 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License v2. See the file "COPYING" in the main directory of this archive 7 * License v2. See the file "COPYING" in the main directory of this archive
8 * for more details. 8 * for more details.
9 */ 9 */
10#include <linux/pci.h> 10#include <linux/pci.h>
11#include <linux/io.h>
11#include <asm/addrspace.h> 12#include <asm/addrspace.h>
12#include <asm/io.h>
13#include "pci-sh4.h" 13#include "pci-sh4.h"
14 14
15/* 15/*
16 * Direct access to PCI hardware... 16 * Direct access to PCI hardware...
17 */ 17 */
18#define CONFIG_CMD(bus, devfn, where) \ 18#define CONFIG_CMD(bus, devfn, where) \
19 P1SEGADDR((bus->number << 16) | (devfn << 8) | (where & ~3)) 19 (P1SEG | (bus->number << 16) | (devfn << 8) | (where & ~3))
20 20
21static DEFINE_SPINLOCK(sh4_pci_lock); 21static DEFINE_SPINLOCK(sh4_pci_lock);
22 22
@@ -26,6 +26,7 @@ static DEFINE_SPINLOCK(sh4_pci_lock);
26static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn, 26static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
27 int where, int size, u32 *val) 27 int where, int size, u32 *val)
28{ 28{
29 struct pci_channel *chan = bus->sysdata;
29 unsigned long flags; 30 unsigned long flags;
30 u32 data; 31 u32 data;
31 32
@@ -34,8 +35,8 @@ static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
34 * so we must do byte alignment by hand 35 * so we must do byte alignment by hand
35 */ 36 */
36 spin_lock_irqsave(&sh4_pci_lock, flags); 37 spin_lock_irqsave(&sh4_pci_lock, flags);
37 pci_write_reg(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR); 38 pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
38 data = pci_read_reg(SH4_PCIPDR); 39 data = pci_read_reg(chan, SH4_PCIPDR);
39 spin_unlock_irqrestore(&sh4_pci_lock, flags); 40 spin_unlock_irqrestore(&sh4_pci_lock, flags);
40 41
41 switch (size) { 42 switch (size) {
@@ -63,13 +64,14 @@ static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn,
63static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn, 64static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
64 int where, int size, u32 val) 65 int where, int size, u32 val)
65{ 66{
67 struct pci_channel *chan = bus->sysdata;
66 unsigned long flags; 68 unsigned long flags;
67 int shift; 69 int shift;
68 u32 data; 70 u32 data;
69 71
70 spin_lock_irqsave(&sh4_pci_lock, flags); 72 spin_lock_irqsave(&sh4_pci_lock, flags);
71 pci_write_reg(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR); 73 pci_write_reg(chan, CONFIG_CMD(bus, devfn, where), SH4_PCIPAR);
72 data = pci_read_reg(SH4_PCIPDR); 74 data = pci_read_reg(chan, SH4_PCIPDR);
73 spin_unlock_irqrestore(&sh4_pci_lock, flags); 75 spin_unlock_irqrestore(&sh4_pci_lock, flags);
74 76
75 switch (size) { 77 switch (size) {
@@ -90,7 +92,7 @@ static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn,
90 return PCIBIOS_FUNC_NOT_SUPPORTED; 92 return PCIBIOS_FUNC_NOT_SUPPORTED;
91 } 93 }
92 94
93 pci_write_reg(data, SH4_PCIPDR); 95 pci_write_reg(chan, data, SH4_PCIPDR);
94 96
95 return PCIBIOS_SUCCESSFUL; 97 return PCIBIOS_SUCCESSFUL;
96} 98}
@@ -104,66 +106,31 @@ struct pci_ops sh4_pci_ops = {
104 * Not really related to pci_ops, but it's common and not worth shoving 106 * Not really related to pci_ops, but it's common and not worth shoving
105 * somewhere else for now.. 107 * somewhere else for now..
106 */ 108 */
107static unsigned int pci_probe = PCI_PROBE_CONF1; 109int __init sh4_pci_check_direct(struct pci_channel *chan)
108
109int __init sh4_pci_check_direct(void)
110{ 110{
111 /* 111 /*
112 * Check if configuration works. 112 * Check if configuration works.
113 */ 113 */
114 if (pci_probe & PCI_PROBE_CONF1) { 114 unsigned int tmp = pci_read_reg(chan, SH4_PCIPAR);
115 unsigned int tmp = pci_read_reg(SH4_PCIPAR);
116
117 pci_write_reg(P1SEG, SH4_PCIPAR);
118 115
119 if (pci_read_reg(SH4_PCIPAR) == P1SEG) { 116 pci_write_reg(chan, P1SEG, SH4_PCIPAR);
120 pci_write_reg(tmp, SH4_PCIPAR);
121 printk(KERN_INFO "PCI: Using configuration type 1\n");
122 request_region(PCI_REG(SH4_PCIPAR), 8, "PCI conf1");
123 117
124 return 0; 118 if (pci_read_reg(chan, SH4_PCIPAR) == P1SEG) {
125 } 119 pci_write_reg(chan, tmp, SH4_PCIPAR);
126 120 printk(KERN_INFO "PCI: Using configuration type 1\n");
127 pci_write_reg(tmp, SH4_PCIPAR); 121 request_region(chan->reg_base + SH4_PCIPAR, 8,
122 "PCI conf1");
123 return 0;
128 } 124 }
129 125
130 pr_debug("PCI: pci_check_direct failed\n"); 126 pci_write_reg(chan, tmp, SH4_PCIPAR);
131 return -EINVAL;
132}
133 127
134/* Handle generic fixups */ 128 printk(KERN_ERR "PCI: %s failed\n", __func__);
135static void __init pci_fixup_ide_bases(struct pci_dev *d)
136{
137 int i;
138 129
139 /* 130 return -EINVAL;
140 * PCI IDE controllers use non-standard I/O port decoding, respect it.
141 */
142 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
143 return;
144 pr_debug("PCI: IDE base address fixup for %s\n", pci_name(d));
145 for(i = 0; i < 4; i++) {
146 struct resource *r = &d->resource[i];
147
148 if ((r->start & ~0x80) == 0x374) {
149 r->start |= 2;
150 r->end = r->start;
151 }
152 }
153}
154DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
155
156char * __devinit pcibios_setup(char *str)
157{
158 if (!strcmp(str, "off")) {
159 pci_probe = 0;
160 return NULL;
161 }
162
163 return str;
164} 131}
165 132
166int __attribute__((weak)) pci_fixup_pcic(void) 133int __attribute__((weak)) pci_fixup_pcic(struct pci_channel *chan)
167{ 134{
168 /* Nothing to do. */ 135 /* Nothing to do. */
169 return 0; 136 return 0;
diff --git a/arch/sh/drivers/pci/ops-sh5.c b/arch/sh/drivers/pci/ops-sh5.c
index 729e38a6fe07..4ce95a001b80 100644
--- a/arch/sh/drivers/pci/ops-sh5.c
+++ b/arch/sh/drivers/pci/ops-sh5.c
@@ -22,31 +22,6 @@
22#include <asm/io.h> 22#include <asm/io.h>
23#include "pci-sh5.h" 23#include "pci-sh5.h"
24 24
25static void __init pci_fixup_ide_bases(struct pci_dev *d)
26{
27 int i;
28
29 /*
30 * PCI IDE controllers use non-standard I/O port decoding, respect it.
31 */
32 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
33 return;
34 printk("PCI: IDE base address fixup for %s\n", pci_name(d));
35 for(i=0; i<4; i++) {
36 struct resource *r = &d->resource[i];
37 if ((r->start & ~0x80) == 0x374) {
38 r->start |= 2;
39 r->end = r->start;
40 }
41 }
42}
43DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
44
45char * __devinit pcibios_setup(char *str)
46{
47 return str;
48}
49
50static int sh5pci_read(struct pci_bus *bus, unsigned int devfn, int where, 25static int sh5pci_read(struct pci_bus *bus, unsigned int devfn, int where,
51 int size, u32 *val) 26 int size, u32 *val)
52{ 27{
diff --git a/arch/sh/drivers/pci/ops-sh7785lcr.c b/arch/sh/drivers/pci/ops-sh7785lcr.c
deleted file mode 100644
index fb0869f0bef8..000000000000
--- a/arch/sh/drivers/pci/ops-sh7785lcr.c
+++ /dev/null
@@ -1,66 +0,0 @@
1/*
2 * Author: Ian DaSilva (idasilva@mvista.com)
3 *
4 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
5 *
6 * May be copied or modified under the terms of the GNU General Public
7 * License. See linux/COPYING for more information.
8 *
9 * PCI initialization for the Renesas R0P7785LC0011RL board
10 * Based on arch/sh/drivers/pci/ops-r7780rp.c
11 *
12 */
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/pci.h>
18#include "pci-sh4.h"
19
20static char irq_tab[] __initdata = {
21 65, 66, 67, 68,
22};
23
24int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
25{
26 return irq_tab[slot];
27}
28
29static struct resource sh7785_io_resource = {
30 .name = "SH7785_IO",
31 .start = SH7780_PCI_IO_BASE,
32 .end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
33 .flags = IORESOURCE_IO
34};
35
36static struct resource sh7785_mem_resource = {
37 .name = "SH7785_mem",
38 .start = SH7780_PCI_MEMORY_BASE,
39 .end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
40 .flags = IORESOURCE_MEM
41};
42
43struct pci_channel board_pci_channels[] = {
44 { &sh4_pci_ops, &sh7785_io_resource, &sh7785_mem_resource, 0, 0xff },
45 { NULL, NULL, NULL, 0, 0 },
46};
47EXPORT_SYMBOL(board_pci_channels);
48
49static struct sh4_pci_address_map sh7785_pci_map = {
50 .window0 = {
51#if defined(CONFIG_32BIT)
52 .base = SH7780_32BIT_DDR_BASE_ADDR,
53 .size = 0x40000000,
54#else
55 .base = SH7780_CS0_BASE_ADDR,
56 .size = 0x20000000,
57#endif
58 },
59
60 .flags = SH4_PCIC_NO_RESET,
61};
62
63int __init pcibios_init_platform(void)
64{
65 return sh7780_pcic_init(&sh7785_pci_map);
66}
diff --git a/arch/sh/drivers/pci/ops-snapgear.c b/arch/sh/drivers/pci/ops-snapgear.c
deleted file mode 100644
index 53dd893d4e54..000000000000
--- a/arch/sh/drivers/pci/ops-snapgear.c
+++ /dev/null
@@ -1,94 +0,0 @@
1/*
2 * arch/sh/drivers/pci/ops-snapgear.c
3 *
4 * Author: David McCullough <davidm@snapgear.com>
5 *
6 * Ported to new API by Paul Mundt <lethal@linux-sh.org>
7 *
8 * Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
9 *
10 * May be copied or modified under the terms of the GNU General Public
11 * License. See linux/COPYING for more information.
12 *
13 * PCI initialization for the SnapGear boards
14 */
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/init.h>
18#include <linux/pci.h>
19#include "pci-sh4.h"
20
21#define SNAPGEAR_PCI_IO 0x4000
22#define SNAPGEAR_PCI_MEM 0xfd000000
23
24/* PCI: default LOCAL memory window sizes (seen from PCI bus) */
25#define SNAPGEAR_LSR0_SIZE (64*(1<<20)) //64MB
26#define SNAPGEAR_LSR1_SIZE (64*(1<<20)) //64MB
27
28static struct resource sh7751_io_resource = {
29 .name = "SH7751 IO",
30 .start = SNAPGEAR_PCI_IO,
31 .end = SNAPGEAR_PCI_IO + (64*1024) - 1, /* 64KiB I/O */
32 .flags = IORESOURCE_IO,
33};
34
35static struct resource sh7751_mem_resource = {
36 .name = "SH7751 mem",
37 .start = SNAPGEAR_PCI_MEM,
38 .end = SNAPGEAR_PCI_MEM + (64*1024*1024) - 1, /* 64MiB mem */
39 .flags = IORESOURCE_MEM,
40};
41
42struct pci_channel board_pci_channels[] = {
43 { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
44 { 0, }
45};
46
47static struct sh4_pci_address_map sh7751_pci_map = {
48 .window0 = {
49 .base = SH7751_CS2_BASE_ADDR,
50 .size = SNAPGEAR_LSR0_SIZE,
51 },
52
53 .window1 = {
54 .base = SH7751_CS2_BASE_ADDR,
55 .size = SNAPGEAR_LSR1_SIZE,
56 },
57
58 .flags = SH4_PCIC_NO_RESET,
59};
60
61/*
62 * Initialize the SnapGear PCI interface
63 * Setup hardware to be Central Funtion
64 * Copy the BSR regs to the PCI interface
65 * Setup PCI windows into local RAM
66 */
67int __init pcibios_init_platform(void)
68{
69 return sh7751_pcic_init(&sh7751_pci_map);
70}
71
72int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
73{
74 int irq = -1;
75
76 switch (slot) {
77 case 8: /* the PCI bridge */ break;
78 case 11: irq = 8; break; /* USB */
79 case 12: irq = 11; break; /* PCMCIA */
80 case 13: irq = 5; break; /* eth0 */
81 case 14: irq = 8; break; /* eth1 */
82 case 15: irq = 11; break; /* safenet (unused) */
83 }
84
85 printk("PCI: Mapping SnapGear IRQ for slot %d, pin %c to irq %d\n",
86 slot, pin - 1 + 'A', irq);
87
88 return irq;
89}
90
91void __init pcibios_fixup(void)
92{
93 /* Nothing to fixup .. */
94}
diff --git a/arch/sh/drivers/pci/pci-auto.c b/arch/sh/drivers/pci/pci-auto.c
deleted file mode 100644
index cf48b12ee58c..000000000000
--- a/arch/sh/drivers/pci/pci-auto.c
+++ /dev/null
@@ -1,545 +0,0 @@
1/*
2 * PCI autoconfiguration library
3 *
4 * Author: Matt Porter <mporter@mvista.com>
5 *
6 * Copyright 2000, 2001 MontaVista Software Inc.
7 * Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
8 * Copyright 2003 Paul Mundt <lethal@linux-sh.org>
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16/*
17 * Modified for MIPS by Jun Sun, jsun@mvista.com
18 *
19 * . Simplify the interface between pci_auto and the rest: a single function.
20 * . Assign resources from low address to upper address.
21 * . change most int to u32.
22 *
23 * Further modified to include it as mips generic code, ppopov@mvista.com.
24 *
25 * 2001-10-26 Bradley D. LaRonde <brad@ltc.com>
26 * - Add a top_bus argument to the "early config" functions so that
27 * they can set a fake parent bus pointer to convince the underlying
28 * pci ops to use type 1 configuration for sub busses.
29 * - Set bridge base and limit registers correctly.
30 * - Align io and memory base properly before and after bridge setup.
31 * - Don't fall through to pci_setup_bars for bridge.
32 * - Reformat the debug output to look more like lspci's output.
33 *
34 * Cloned for SuperH by M. R. Brown, mrbrown@0xd6.org
35 *
36 * 2003-08-05 Paul Mundt <lethal@linux-sh.org>
37 * - Don't update the BAR values on systems that already have valid addresses
38 * and don't want these updated for whatever reason, by way of a new config
39 * option check. However, we still read in the old BAR values so that they
40 * can still be reported through the debug output.
41 */
42
43#include <linux/kernel.h>
44#include <linux/init.h>
45#include <linux/types.h>
46#include <linux/pci.h>
47
48#define DEBUG
49#ifdef DEBUG
50#define DBG(x...) printk(x)
51#else
52#define DBG(x...)
53#endif
54
55/*
56 * These functions are used early on before PCI scanning is done
57 * and all of the pci_dev and pci_bus structures have been created.
58 */
59static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
60 int top_bus, int busnr, int devfn)
61{
62 static struct pci_dev dev;
63 static struct pci_bus bus;
64
65 dev.bus = &bus;
66 dev.sysdata = hose;
67 dev.devfn = devfn;
68 bus.number = busnr;
69 bus.ops = hose->pci_ops;
70
71 if(busnr != top_bus)
72 /* Fake a parent bus structure. */
73 bus.parent = &bus;
74 else
75 bus.parent = NULL;
76
77 return &dev;
78}
79
80#define EARLY_PCI_OP(rw, size, type) \
81static int early_##rw##_config_##size(struct pci_channel *hose, \
82 int top_bus, int bus, int devfn, int offset, type value) \
83{ \
84 return pci_##rw##_config_##size( \
85 fake_pci_dev(hose, top_bus, bus, devfn), \
86 offset, value); \
87}
88
89EARLY_PCI_OP(read, byte, u8 *)
90EARLY_PCI_OP(read, word, u16 *)
91EARLY_PCI_OP(read, dword, u32 *)
92EARLY_PCI_OP(write, byte, u8)
93EARLY_PCI_OP(write, word, u16)
94EARLY_PCI_OP(write, dword, u32)
95
96static struct resource *io_resource_inuse;
97static struct resource *mem_resource_inuse;
98
99static u32 pciauto_lower_iospc;
100static u32 pciauto_upper_iospc;
101
102static u32 pciauto_lower_memspc;
103static u32 pciauto_upper_memspc;
104
105static void __init
106pciauto_setup_bars(struct pci_channel *hose,
107 int top_bus,
108 int current_bus,
109 int pci_devfn,
110 int bar_limit)
111{
112 u32 bar_response, bar_size, bar_value;
113 u32 bar, addr_mask, bar_nr = 0;
114 u32 * upper_limit;
115 u32 * lower_limit;
116 int found_mem64 = 0;
117
118 for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
119 u32 bar_addr;
120
121 /* Read the old BAR value */
122 early_read_config_dword(hose, top_bus,
123 current_bus,
124 pci_devfn,
125 bar,
126 &bar_addr);
127
128 /* Tickle the BAR and get the response */
129 early_write_config_dword(hose, top_bus,
130 current_bus,
131 pci_devfn,
132 bar,
133 0xffffffff);
134
135 early_read_config_dword(hose, top_bus,
136 current_bus,
137 pci_devfn,
138 bar,
139 &bar_response);
140
141 /*
142 * Write the old BAR value back out, only update the BAR
143 * if we implicitly want resources to be updated, which
144 * is done by the generic code further down. -- PFM.
145 */
146 early_write_config_dword(hose, top_bus,
147 current_bus,
148 pci_devfn,
149 bar,
150 bar_addr);
151
152 /* If BAR is not implemented go to the next BAR */
153 if (!bar_response)
154 continue;
155
156 /*
157 * Workaround for a BAR that doesn't use its upper word,
158 * like the ALi 1535D+ PCI DC-97 Controller Modem (M5457).
159 * bdl <brad@ltc.com>
160 */
161 if (!(bar_response & 0xffff0000))
162 bar_response |= 0xffff0000;
163
164retry:
165 /* Check the BAR type and set our address mask */
166 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
167 addr_mask = PCI_BASE_ADDRESS_IO_MASK;
168 upper_limit = &pciauto_upper_iospc;
169 lower_limit = &pciauto_lower_iospc;
170 DBG(" I/O");
171 } else {
172 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
173 PCI_BASE_ADDRESS_MEM_TYPE_64)
174 found_mem64 = 1;
175
176 addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
177 upper_limit = &pciauto_upper_memspc;
178 lower_limit = &pciauto_lower_memspc;
179 DBG(" Mem");
180 }
181
182
183 /* Calculate requested size */
184 bar_size = ~(bar_response & addr_mask) + 1;
185
186 /* Allocate a base address */
187 bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
188
189 if ((bar_value + bar_size) > *upper_limit) {
190 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
191 if (io_resource_inuse->child) {
192 io_resource_inuse =
193 io_resource_inuse->child;
194 pciauto_lower_iospc =
195 io_resource_inuse->start;
196 pciauto_upper_iospc =
197 io_resource_inuse->end + 1;
198 goto retry;
199 }
200
201 } else {
202 if (mem_resource_inuse->child) {
203 mem_resource_inuse =
204 mem_resource_inuse->child;
205 pciauto_lower_memspc =
206 mem_resource_inuse->start;
207 pciauto_upper_memspc =
208 mem_resource_inuse->end + 1;
209 goto retry;
210 }
211 }
212 DBG(" unavailable -- skipping, value %x size %x\n",
213 bar_value, bar_size);
214 continue;
215 }
216
217 if (bar_value < *lower_limit || (bar_value + bar_size) >= *upper_limit) {
218 DBG(" unavailable -- skipping, value %x size %x\n",
219 bar_value, bar_size);
220 continue;
221 }
222
223#ifdef CONFIG_PCI_AUTO_UPDATE_RESOURCES
224 /* Write it out and update our limit */
225 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
226 bar, bar_value);
227#endif
228
229 *lower_limit = bar_value + bar_size;
230
231 /*
232 * If we are a 64-bit decoder then increment to the
233 * upper 32 bits of the bar and force it to locate
234 * in the lower 4GB of memory.
235 */
236 if (found_mem64) {
237 bar += 4;
238 early_write_config_dword(hose, top_bus,
239 current_bus,
240 pci_devfn,
241 bar,
242 0x00000000);
243 }
244
245 DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size);
246
247 bar_nr++;
248 }
249
250}
251
252static void __init
253pciauto_prescan_setup_bridge(struct pci_channel *hose,
254 int top_bus,
255 int current_bus,
256 int pci_devfn,
257 int sub_bus)
258{
259 /* Configure bus number registers */
260 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
261 PCI_PRIMARY_BUS, current_bus);
262 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
263 PCI_SECONDARY_BUS, sub_bus + 1);
264 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
265 PCI_SUBORDINATE_BUS, 0xff);
266
267 /* Align memory and I/O to 1MB and 4KB boundaries. */
268 pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
269 & ~(0x100000 - 1);
270 pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
271 & ~(0x1000 - 1);
272
273 /* Set base (lower limit) of address range behind bridge. */
274 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
275 PCI_MEMORY_BASE, pciauto_lower_memspc >> 16);
276 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
277 PCI_IO_BASE, (pciauto_lower_iospc & 0x0000f000) >> 8);
278 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
279 PCI_IO_BASE_UPPER16, pciauto_lower_iospc >> 16);
280
281 /* We don't support prefetchable memory for now, so disable */
282 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
283 PCI_PREF_MEMORY_BASE, 0);
284 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
285 PCI_PREF_MEMORY_LIMIT, 0);
286}
287
288static void __init
289pciauto_postscan_setup_bridge(struct pci_channel *hose,
290 int top_bus,
291 int current_bus,
292 int pci_devfn,
293 int sub_bus)
294{
295 u32 temp;
296
297 /*
298 * [jsun] we always bump up baselines a little, so that if there
299 * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
300 * spaces.
301 */
302 pciauto_lower_memspc += 1;
303 pciauto_lower_iospc += 1;
304
305 /* Configure bus number registers */
306 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
307 PCI_SUBORDINATE_BUS, sub_bus);
308
309 /* Set upper limit of address range behind bridge. */
310 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
311 PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16);
312 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
313 PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8);
314 early_write_config_word(hose, top_bus, current_bus, pci_devfn,
315 PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16);
316
317 /* Align memory and I/O to 1MB and 4KB boundaries. */
318 pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
319 & ~(0x100000 - 1);
320 pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
321 & ~(0x1000 - 1);
322
323 /* Enable memory and I/O accesses, enable bus master */
324 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
325 PCI_COMMAND, &temp);
326 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
327 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
328 | PCI_COMMAND_MASTER);
329}
330
331static void __init
332pciauto_prescan_setup_cardbus_bridge(struct pci_channel *hose,
333 int top_bus,
334 int current_bus,
335 int pci_devfn,
336 int sub_bus)
337{
338 /* Configure bus number registers */
339 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
340 PCI_PRIMARY_BUS, current_bus);
341 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
342 PCI_SECONDARY_BUS, sub_bus + 1);
343 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
344 PCI_SUBORDINATE_BUS, 0xff);
345
346 /* Align memory and I/O to 4KB and 4 byte boundaries. */
347 pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
348 & ~(0x1000 - 1);
349 pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
350 & ~(0x4 - 1);
351
352 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
353 PCI_CB_MEMORY_BASE_0, pciauto_lower_memspc);
354 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
355 PCI_CB_IO_BASE_0, pciauto_lower_iospc);
356}
357
358static void __init
359pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
360 int top_bus,
361 int current_bus,
362 int pci_devfn,
363 int sub_bus)
364{
365 u32 temp;
366
367 /*
368 * [jsun] we always bump up baselines a little, so that if there
369 * nothing behind P2P bridge, we don't wind up overlapping IO/MEM
370 * spaces.
371 */
372 pciauto_lower_memspc += 1;
373 pciauto_lower_iospc += 1;
374
375 /*
376 * Configure subordinate bus number. The PCI subsystem
377 * bus scan will renumber buses (reserving three additional
378 * for this PCI<->CardBus bridge for the case where a CardBus
379 * adapter contains a P2P or CB2CB bridge.
380 */
381
382 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
383 PCI_SUBORDINATE_BUS, sub_bus);
384
385 /*
386 * Reserve an additional 4MB for mem space and 16KB for
387 * I/O space. This should cover any additional space
388 * requirement of unusual CardBus devices with
389 * additional bridges that can consume more address space.
390 *
391 * Although pcmcia-cs currently will reprogram bridge
392 * windows, the goal is to add an option to leave them
393 * alone and use the bridge window ranges as the regions
394 * that are searched for free resources upon hot-insertion
395 * of a device. This will allow a PCI<->CardBus bridge
396 * configured by this routine to happily live behind a
397 * P2P bridge in a system.
398 */
399 /* Align memory and I/O to 4KB and 4 byte boundaries. */
400 pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
401 & ~(0x1000 - 1);
402 pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
403 & ~(0x4 - 1);
404 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
405 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
406 PCI_CB_MEMORY_LIMIT_0, pciauto_lower_memspc - 1);
407 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
408 PCI_CB_IO_LIMIT_0, pciauto_lower_iospc - 1);
409
410 /* Enable memory and I/O accesses, enable bus master */
411 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
412 PCI_COMMAND, &temp);
413 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
414 PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
415 PCI_COMMAND_MASTER);
416}
417
418#define PCIAUTO_IDE_MODE_MASK 0x05
419
420static int __init
421pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
422{
423 int sub_bus;
424 u32 pci_devfn, pci_class, cmdstat, found_multi=0;
425 unsigned short vid, did;
426 unsigned char header_type;
427 int devfn_start = 0;
428 int devfn_stop = 0xff;
429
430 sub_bus = current_bus;
431
432 if (hose->first_devfn)
433 devfn_start = hose->first_devfn;
434 if (hose->last_devfn)
435 devfn_stop = hose->last_devfn;
436
437 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
438
439 if (PCI_FUNC(pci_devfn) && !found_multi)
440 continue;
441
442 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
443 PCI_VENDOR_ID, &vid);
444
445 if (vid == 0xffff) continue;
446
447 early_read_config_byte(hose, top_bus, current_bus, pci_devfn,
448 PCI_HEADER_TYPE, &header_type);
449
450 if (!PCI_FUNC(pci_devfn))
451 found_multi = header_type & 0x80;
452
453 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
454 PCI_DEVICE_ID, &did);
455
456 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
457 PCI_CLASS_REVISION, &pci_class);
458
459 DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
460 current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
461 pci_class >> 16, vid, did);
462 if (pci_class & 0xff)
463 DBG(" (rev %.2x)", pci_class & 0xff);
464 DBG("\n");
465
466 if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
467 DBG(" Bridge: primary=%.2x, secondary=%.2x\n",
468 current_bus, sub_bus + 1);
469 pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
470 pci_devfn, sub_bus);
471 DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
472 sub_bus + 1,
473 pciauto_lower_iospc, pciauto_lower_memspc);
474 sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
475 DBG("Back to bus %.2x\n", current_bus);
476 pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
477 pci_devfn, sub_bus);
478 continue;
479 } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
480 DBG(" CARDBUS Bridge: primary=%.2x, secondary=%.2x\n",
481 current_bus, sub_bus + 1);
482 DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
483 /* Place CardBus Socket/ExCA registers */
484 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_0);
485
486 pciauto_prescan_setup_cardbus_bridge(hose, top_bus,
487 current_bus, pci_devfn, sub_bus);
488
489 DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
490 sub_bus + 1,
491 pciauto_lower_iospc, pciauto_lower_memspc);
492 sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
493 DBG("Back to bus %.2x, sub_bus is %x\n", current_bus, sub_bus);
494 pciauto_postscan_setup_cardbus_bridge(hose, top_bus,
495 current_bus, pci_devfn, sub_bus);
496 continue;
497 } else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
498
499 unsigned char prg_iface;
500
501 early_read_config_byte(hose, top_bus, current_bus,
502 pci_devfn, PCI_CLASS_PROG, &prg_iface);
503 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
504 DBG("Skipping legacy mode IDE controller\n");
505 continue;
506 }
507 }
508
509 /*
510 * Found a peripheral, enable some standard
511 * settings
512 */
513 early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
514 PCI_COMMAND, &cmdstat);
515 early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
516 PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
517 PCI_COMMAND_MEMORY |
518 PCI_COMMAND_MASTER);
519 early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
520 PCI_LATENCY_TIMER, 0x80);
521
522 /* Allocate PCI I/O and/or memory space */
523 pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_5);
524 }
525 return sub_bus;
526}
527
528int __init
529pciauto_assign_resources(int busno, struct pci_channel *hose)
530{
531 /* setup resource limits */
532 io_resource_inuse = hose->io_resource;
533 mem_resource_inuse = hose->mem_resource;
534
535 pciauto_lower_iospc = io_resource_inuse->start;
536 pciauto_upper_iospc = io_resource_inuse->end + 1;
537 pciauto_lower_memspc = mem_resource_inuse->start;
538 pciauto_upper_memspc = mem_resource_inuse->end + 1;
539 DBG("Autoconfig PCI channel 0x%p\n", hose);
540 DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n",
541 busno, pciauto_lower_iospc, pciauto_upper_iospc,
542 pciauto_lower_memspc, pciauto_upper_memspc);
543
544 return pciauto_bus_scan(hose, busno, busno);
545}
diff --git a/arch/sh/drivers/pci/pci-dreamcast.c b/arch/sh/drivers/pci/pci-dreamcast.c
new file mode 100644
index 000000000000..210f9d4af141
--- /dev/null
+++ b/arch/sh/drivers/pci/pci-dreamcast.c
@@ -0,0 +1,102 @@
1/*
2 * PCI support for the Sega Dreamcast
3 *
4 * Copyright (C) 2001, 2002 M. R. Brown
5 * Copyright (C) 2002, 2003 Paul Mundt
6 *
7 * This file originally bore the message (with enclosed-$):
8 * Id: pci.c,v 1.3 2003/05/04 19:29:46 lethal Exp
9 * Dreamcast PCI: Supports SEGA Broadband Adaptor only.
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15
16#include <linux/sched.h>
17#include <linux/kernel.h>
18#include <linux/param.h>
19#include <linux/interrupt.h>
20#include <linux/init.h>
21#include <linux/irq.h>
22#include <linux/pci.h>
23#include <linux/module.h>
24#include <asm/io.h>
25#include <asm/irq.h>
26#include <mach/pci.h>
27
28static struct resource gapspci_io_resource = {
29 .name = "GAPSPCI IO",
30 .start = GAPSPCI_BBA_CONFIG,
31 .end = GAPSPCI_BBA_CONFIG + GAPSPCI_BBA_CONFIG_SIZE - 1,
32 .flags = IORESOURCE_IO,
33};
34
35static struct resource gapspci_mem_resource = {
36 .name = "GAPSPCI mem",
37 .start = GAPSPCI_DMA_BASE,
38 .end = GAPSPCI_DMA_BASE + GAPSPCI_DMA_SIZE - 1,
39 .flags = IORESOURCE_MEM,
40};
41
42static struct pci_channel dreamcast_pci_controller = {
43 .pci_ops = &gapspci_pci_ops,
44 .io_resource = &gapspci_io_resource,
45 .io_offset = 0x00000000,
46 .mem_resource = &gapspci_mem_resource,
47 .mem_offset = 0x00000000,
48};
49
50/*
51 * gapspci init
52 */
53
54static int __init gapspci_init(void)
55{
56 char idbuf[16];
57 int i;
58
59 /*
60 * FIXME: All of this wants documenting to some degree,
61 * even some basic register definitions would be nice.
62 *
63 * I haven't seen anything this ugly since.. maple.
64 */
65
66 for (i=0; i<16; i++)
67 idbuf[i] = inb(GAPSPCI_REGS+i);
68
69 if (strncmp(idbuf, "GAPSPCI_BRIDGE_2", 16))
70 return -ENODEV;
71
72 outl(0x5a14a501, GAPSPCI_REGS+0x18);
73
74 for (i=0; i<1000000; i++)
75 cpu_relax();
76
77 if (inl(GAPSPCI_REGS+0x18) != 1)
78 return -EINVAL;
79
80 outl(0x01000000, GAPSPCI_REGS+0x20);
81 outl(0x01000000, GAPSPCI_REGS+0x24);
82
83 outl(GAPSPCI_DMA_BASE, GAPSPCI_REGS+0x28);
84 outl(GAPSPCI_DMA_BASE+GAPSPCI_DMA_SIZE, GAPSPCI_REGS+0x2c);
85
86 outl(1, GAPSPCI_REGS+0x14);
87 outl(1, GAPSPCI_REGS+0x34);
88
89 /* Setting Broadband Adapter */
90 outw(0xf900, GAPSPCI_BBA_CONFIG+0x06);
91 outl(0x00000000, GAPSPCI_BBA_CONFIG+0x30);
92 outb(0x00, GAPSPCI_BBA_CONFIG+0x3c);
93 outb(0xf0, GAPSPCI_BBA_CONFIG+0x0d);
94 outw(0x0006, GAPSPCI_BBA_CONFIG+0x04);
95 outl(0x00002001, GAPSPCI_BBA_CONFIG+0x10);
96 outl(0x01000000, GAPSPCI_BBA_CONFIG+0x14);
97
98 register_pci_controller(&dreamcast_pci_controller);
99
100 return 0;
101}
102arch_initcall(gapspci_init);
diff --git a/arch/sh/drivers/pci/pci-sh4.h b/arch/sh/drivers/pci/pci-sh4.h
index a83dcf70c13b..3d5296cde622 100644
--- a/arch/sh/drivers/pci/pci-sh4.h
+++ b/arch/sh/drivers/pci/pci-sh4.h
@@ -149,13 +149,10 @@
149 #define SH4_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */ 149 #define SH4_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */
150#define SH4_PCIPDR 0x220 /* Port IO Data Register */ 150#define SH4_PCIPDR 0x220 /* Port IO Data Register */
151 151
152/* Flags */
153#define SH4_PCIC_NO_RESET 0x0001
154
155/* arch/sh/kernel/drivers/pci/ops-sh4.c */ 152/* arch/sh/kernel/drivers/pci/ops-sh4.c */
156extern struct pci_ops sh4_pci_ops; 153extern struct pci_ops sh4_pci_ops;
157int sh4_pci_check_direct(void); 154int sh4_pci_check_direct(struct pci_channel *chan);
158int pci_fixup_pcic(void); 155int pci_fixup_pcic(struct pci_channel *chan);
159 156
160struct sh4_pci_address_space { 157struct sh4_pci_address_space {
161 unsigned long base; 158 unsigned long base;
@@ -165,16 +162,18 @@ struct sh4_pci_address_space {
165struct sh4_pci_address_map { 162struct sh4_pci_address_map {
166 struct sh4_pci_address_space window0; 163 struct sh4_pci_address_space window0;
167 struct sh4_pci_address_space window1; 164 struct sh4_pci_address_space window1;
168 unsigned long flags;
169}; 165};
170 166
171static inline void pci_write_reg(unsigned long val, unsigned long reg) 167static inline void pci_write_reg(struct pci_channel *chan,
168 unsigned long val, unsigned long reg)
172{ 169{
173 ctrl_outl(val, PCI_REG(reg)); 170 ctrl_outl(val, chan->reg_base + reg);
174} 171}
175 172
176static inline unsigned long pci_read_reg(unsigned long reg) 173static inline unsigned long pci_read_reg(struct pci_channel *chan,
174 unsigned long reg)
177{ 175{
178 return ctrl_inl(PCI_REG(reg)); 176 return ctrl_inl(chan->reg_base + reg);
179} 177}
178
180#endif /* __PCI_SH4_H */ 179#endif /* __PCI_SH4_H */
diff --git a/arch/sh/drivers/pci/pci-sh5.c b/arch/sh/drivers/pci/pci-sh5.c
index 7a97438762c8..873ed2b44055 100644
--- a/arch/sh/drivers/pci/pci-sh5.c
+++ b/arch/sh/drivers/pci/pci-sh5.c
@@ -89,8 +89,21 @@ static irqreturn_t pcish5_serr_irq(int irq, void *dev_id)
89 return IRQ_NONE; 89 return IRQ_NONE;
90} 90}
91 91
92int __init sh5pci_init(unsigned long memStart, unsigned long memSize) 92static struct resource sh5_io_resource = { /* place holder */ };
93static struct resource sh5_mem_resource = { /* place holder */ };
94
95static struct pci_channel sh5pci_controller = {
96 .pci_ops = &sh5_pci_ops,
97 .mem_resource = &sh5_mem_resource,
98 .mem_offset = 0x00000000,
99 .io_resource = &sh5_io_resource,
100 .io_offset = 0x00000000,
101};
102
103static int __init sh5pci_init(void)
93{ 104{
105 unsigned long memStart = __pa(memory_start);
106 unsigned long memSize = __pa(memory_end) - memStart;
94 u32 lsr0; 107 u32 lsr0;
95 u32 uval; 108 u32 uval;
96 109
@@ -106,12 +119,12 @@ int __init sh5pci_init(unsigned long memStart, unsigned long memSize)
106 return -EINVAL; 119 return -EINVAL;
107 } 120 }
108 121
109 pcicr_virt = onchip_remap(SH5PCI_ICR_BASE, 1024, "PCICR"); 122 pcicr_virt = (unsigned long)ioremap_nocache(SH5PCI_ICR_BASE, 1024);
110 if (!pcicr_virt) { 123 if (!pcicr_virt) {
111 panic("Unable to remap PCICR\n"); 124 panic("Unable to remap PCICR\n");
112 } 125 }
113 126
114 PCI_IO_AREA = onchip_remap(SH5PCI_IO_BASE, 0x10000, "PCIIO"); 127 PCI_IO_AREA = (unsigned long)ioremap_nocache(SH5PCI_IO_BASE, 0x10000);
115 if (!PCI_IO_AREA) { 128 if (!PCI_IO_AREA) {
116 panic("Unable to remap PCIIO\n"); 129 panic("Unable to remap PCIIO\n");
117 } 130 }
@@ -197,32 +210,14 @@ int __init sh5pci_init(unsigned long memStart, unsigned long memSize)
197 SH5PCI_WRITE(AINTM, ~0); 210 SH5PCI_WRITE(AINTM, ~0);
198 SH5PCI_WRITE(PINTM, ~0); 211 SH5PCI_WRITE(PINTM, ~0);
199 212
200 return 0; 213 sh5_io_resource.start = PCI_IO_AREA;
201} 214 sh5_io_resource.end = PCI_IO_AREA + 0x10000;
202 215
203void __devinit pcibios_fixup_bus(struct pci_bus *bus) 216 sh5_mem_resource.start = memStart;
204{ 217 sh5_mem_resource.end = memStart + memSize;
205 struct pci_dev *dev = bus->self; 218
206 int i; 219 register_pci_controller(&sh5pci_controller);
207 220
208 if (dev) { 221 return 0;
209 for (i= 0; i < 3; i++) {
210 bus->resource[i] =
211 &dev->resource[PCI_BRIDGE_RESOURCES+i];
212 bus->resource[i]->name = bus->name;
213 }
214 bus->resource[0]->flags |= IORESOURCE_IO;
215 bus->resource[1]->flags |= IORESOURCE_MEM;
216
217 /* For now, propagate host limits to the bus;
218 * we'll adjust them later. */
219 bus->resource[0]->end = 64*1024 - 1 ;
220 bus->resource[1]->end = PCIBIOS_MIN_MEM+(256*1024*1024)-1;
221 bus->resource[0]->start = PCIBIOS_MIN_IO;
222 bus->resource[1]->start = PCIBIOS_MIN_MEM;
223
224 /* Turn off downstream PF memory address range by default */
225 bus->resource[2]->start = 1024*1024;
226 bus->resource[2]->end = bus->resource[2]->start - 1;
227 }
228} 222}
223arch_initcall(sh5pci_init);
diff --git a/arch/sh/drivers/pci/pci-sh5.h b/arch/sh/drivers/pci/pci-sh5.h
index 7cff3fc04d30..f277628221f3 100644
--- a/arch/sh/drivers/pci/pci-sh5.h
+++ b/arch/sh/drivers/pci/pci-sh5.h
@@ -107,7 +107,4 @@ extern unsigned long pcicr_virt;
107 107
108extern struct pci_ops sh5_pci_ops; 108extern struct pci_ops sh5_pci_ops;
109 109
110/* arch/sh/drivers/pci/pci-sh5.c */
111int sh5pci_init(unsigned long memStart, unsigned long memSize);
112
113#endif /* __PCI_SH5_H */ 110#endif /* __PCI_SH5_H */
diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c
index 3065eb184f01..70c1999a0ec4 100644
--- a/arch/sh/drivers/pci/pci-sh7751.c
+++ b/arch/sh/drivers/pci/pci-sh7751.c
@@ -1,88 +1,100 @@
1/* 1/*
2 * Low-Level PCI Support for the SH7751 2 * Low-Level PCI Support for the SH7751
3 * 3 *
4 * Dustin McIntire (dustin@sensoria.com) 4 * Copyright (C) 2003 - 2009 Paul Mundt
5 * Derived from arch/i386/kernel/pci-*.c which bore the message: 5 * Copyright (C) 2001 Dustin McIntire
6 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
7 * 6 *
8 * Ported to the new API by Paul Mundt <lethal@linux-sh.org> 7 * With cleanup by Paul van Gool <pvangool@mimotech.com>, 2003.
9 * With cleanup by Paul van Gool <pvangool@mimotech.com>
10 *
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
13 * 8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
14 */ 12 */
15#undef DEBUG
16
17#include <linux/init.h> 13#include <linux/init.h>
18#include <linux/pci.h> 14#include <linux/pci.h>
19#include <linux/types.h> 15#include <linux/types.h>
20#include <linux/errno.h> 16#include <linux/errno.h>
21#include <linux/delay.h> 17#include <linux/io.h>
22#include "pci-sh4.h" 18#include "pci-sh4.h"
23#include <asm/addrspace.h> 19#include <asm/addrspace.h>
24#include <asm/io.h>
25 20
26/* 21static int __init __area_sdram_check(struct pci_channel *chan,
27 * Initialization. Try all known PCI access methods. Note that we support 22 unsigned int area)
28 * using both PCI BIOS and direct access: in such cases, we use I/O ports
29 * to access config space.
30 *
31 * Note that the platform specific initialization (BSC registers, and memory
32 * space mapping) will be called via the platform defined function
33 * pcibios_init_platform().
34 */
35static int __init sh7751_pci_init(void)
36{ 23{
37 unsigned int id; 24 unsigned long word;
38 int ret;
39
40 pr_debug("PCI: Starting intialization.\n");
41 25
42 /* check for SH7751/SH7751R hardware */ 26 word = __raw_readl(SH7751_BCR1);
43 id = pci_read_reg(SH7751_PCICONF0);
44 if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
45 id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
46 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
47 return -ENODEV;
48 }
49
50 if ((ret = sh4_pci_check_direct()) != 0)
51 return ret;
52
53 return pcibios_init_platform();
54}
55subsys_initcall(sh7751_pci_init);
56
57static int __init __area_sdram_check(unsigned int area)
58{
59 u32 word;
60
61 word = ctrl_inl(SH7751_BCR1);
62 /* check BCR for SDRAM in area */ 27 /* check BCR for SDRAM in area */
63 if (((word >> area) & 1) == 0) { 28 if (((word >> area) & 1) == 0) {
64 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n", 29 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%lx\n",
65 area, word); 30 area, word);
66 return 0; 31 return 0;
67 } 32 }
68 pci_write_reg(word, SH4_PCIBCR1); 33 pci_write_reg(chan, word, SH4_PCIBCR1);
69 34
70 word = (u16)ctrl_inw(SH7751_BCR2); 35 word = __raw_readw(SH7751_BCR2);
71 /* check BCR2 for 32bit SDRAM interface*/ 36 /* check BCR2 for 32bit SDRAM interface*/
72 if (((word >> (area << 1)) & 0x3) != 0x3) { 37 if (((word >> (area << 1)) & 0x3) != 0x3) {
73 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n", 38 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%lx\n",
74 area, word); 39 area, word);
75 return 0; 40 return 0;
76 } 41 }
77 pci_write_reg(word, SH4_PCIBCR2); 42 pci_write_reg(chan, word, SH4_PCIBCR2);
78 43
79 return 1; 44 return 1;
80} 45}
81 46
82int __init sh7751_pcic_init(struct sh4_pci_address_map *map) 47static struct resource sh7751_io_resource = {
48 .name = "SH7751_IO",
49 .start = SH7751_PCI_IO_BASE,
50 .end = SH7751_PCI_IO_BASE + SH7751_PCI_IO_SIZE - 1,
51 .flags = IORESOURCE_IO
52};
53
54static struct resource sh7751_mem_resource = {
55 .name = "SH7751_mem",
56 .start = SH7751_PCI_MEMORY_BASE,
57 .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1,
58 .flags = IORESOURCE_MEM
59};
60
61static struct pci_channel sh7751_pci_controller = {
62 .pci_ops = &sh4_pci_ops,
63 .mem_resource = &sh7751_mem_resource,
64 .mem_offset = 0x00000000,
65 .io_resource = &sh7751_io_resource,
66 .io_offset = 0x00000000,
67 .io_map_base = SH7751_PCI_IO_BASE,
68};
69
70static struct sh4_pci_address_map sh7751_pci_map = {
71 .window0 = {
72 .base = SH7751_CS3_BASE_ADDR,
73 .size = 0x04000000,
74 },
75};
76
77static int __init sh7751_pci_init(void)
83{ 78{
84 u32 reg; 79 struct pci_channel *chan = &sh7751_pci_controller;
85 u32 word; 80 unsigned int id;
81 u32 word, reg;
82 int ret;
83
84 printk(KERN_NOTICE "PCI: Starting intialization.\n");
85
86 chan->reg_base = 0xfe200000;
87
88 /* check for SH7751/SH7751R hardware */
89 id = pci_read_reg(chan, SH7751_PCICONF0);
90 if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
91 id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
92 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
93 return -ENODEV;
94 }
95
96 if ((ret = sh4_pci_check_direct(chan)) != 0)
97 return ret;
86 98
87 /* Set the BCR's to enable PCI access */ 99 /* Set the BCR's to enable PCI access */
88 reg = ctrl_inl(SH7751_BCR1); 100 reg = ctrl_inl(SH7751_BCR1);
@@ -90,25 +102,10 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
90 ctrl_outl(reg, SH7751_BCR1); 102 ctrl_outl(reg, SH7751_BCR1);
91 103
92 /* Turn the clocks back on (not done in reset)*/ 104 /* Turn the clocks back on (not done in reset)*/
93 pci_write_reg(0, SH4_PCICLKR); 105 pci_write_reg(chan, 0, SH4_PCICLKR);
94 /* Clear Powerdown IRQ's (not done in reset) */ 106 /* Clear Powerdown IRQ's (not done in reset) */
95 word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0; 107 word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0;
96 pci_write_reg(word, SH4_PCIPINT); 108 pci_write_reg(chan, word, SH4_PCIPINT);
97
98 /*
99 * This code is unused for some boards as it is done in the
100 * bootloader and doing it here means the MAC addresses loaded
101 * by the bootloader get lost.
102 */
103 if (!(map->flags & SH4_PCIC_NO_RESET)) {
104 /* toggle PCI reset pin */
105 word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
106 pci_write_reg(word, SH4_PCICR);
107 /* Wait for a long time... not 1 sec. but long enough */
108 mdelay(100);
109 word = SH4_PCICR_PREFIX;
110 pci_write_reg(word, SH4_PCICR);
111 }
112 109
113 /* set the command/status bits to: 110 /* set the command/status bits to:
114 * Wait Cycle Control + Parity Enable + Bus Master + 111 * Wait Cycle Control + Parity Enable + Bus Master +
@@ -116,89 +113,75 @@ int __init sh7751_pcic_init(struct sh4_pci_address_map *map)
116 */ 113 */
117 word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER | 114 word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
118 SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES; 115 SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
119 pci_write_reg(word, SH7751_PCICONF1); 116 pci_write_reg(chan, word, SH7751_PCICONF1);
120 117
121 /* define this host as the host bridge */ 118 /* define this host as the host bridge */
122 word = PCI_BASE_CLASS_BRIDGE << 24; 119 word = PCI_BASE_CLASS_BRIDGE << 24;
123 pci_write_reg(word, SH7751_PCICONF2); 120 pci_write_reg(chan, word, SH7751_PCICONF2);
124 121
125 /* Set IO and Mem windows to local address 122 /* Set IO and Mem windows to local address
126 * Make PCI and local address the same for easy 1 to 1 mapping 123 * Make PCI and local address the same for easy 1 to 1 mapping
127 * Window0 = map->window0.size @ non-cached area base = SDRAM
128 * Window1 = map->window1.size @ cached area base = SDRAM
129 */ 124 */
130 word = map->window0.size - 1; 125 word = sh7751_pci_map.window0.size - 1;
131 pci_write_reg(word, SH4_PCILSR0); 126 pci_write_reg(chan, word, SH4_PCILSR0);
132 word = map->window1.size - 1;
133 pci_write_reg(word, SH4_PCILSR1);
134 /* Set the values on window 0 PCI config registers */ 127 /* Set the values on window 0 PCI config registers */
135 word = P2SEGADDR(map->window0.base); 128 word = P2SEGADDR(sh7751_pci_map.window0.base);
136 pci_write_reg(word, SH4_PCILAR0); 129 pci_write_reg(chan, word, SH4_PCILAR0);
137 pci_write_reg(word, SH7751_PCICONF5); 130 pci_write_reg(chan, word, SH7751_PCICONF5);
138 /* Set the values on window 1 PCI config registers */
139 word = PHYSADDR(map->window1.base);
140 pci_write_reg(word, SH4_PCILAR1);
141 pci_write_reg(word, SH7751_PCICONF6);
142 131
143 /* Set the local 16MB PCI memory space window to 132 /* Set the local 16MB PCI memory space window to
144 * the lowest PCI mapped address 133 * the lowest PCI mapped address
145 */ 134 */
146 word = PCIBIOS_MIN_MEM & SH4_PCIMBR_MASK; 135 word = chan->mem_resource->start & SH4_PCIMBR_MASK;
147 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word); 136 pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word);
148 pci_write_reg(word , SH4_PCIMBR); 137 pci_write_reg(chan, word , SH4_PCIMBR);
149
150 /* Map IO space into PCI IO window
151 * The IO window is 64K-PCIBIOS_MIN_IO in size
152 * IO addresses will be translated to the
153 * PCI IO window base address
154 */
155 pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
156 PCIBIOS_MIN_IO, (64 << 10),
157 SH7751_PCI_IO_BASE + PCIBIOS_MIN_IO);
158 138
159 /* Make sure the MSB's of IO window are set to access PCI space 139 /* Make sure the MSB's of IO window are set to access PCI space
160 * correctly */ 140 * correctly */
161 word = PCIBIOS_MIN_IO & SH4_PCIIOBR_MASK; 141 word = chan->io_resource->start & SH4_PCIIOBR_MASK;
162 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word); 142 pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word);
163 pci_write_reg(word, SH4_PCIIOBR); 143 pci_write_reg(chan, word, SH4_PCIIOBR);
164 144
165 /* Set PCI WCRx, BCRx's, copy from BSC locations */ 145 /* Set PCI WCRx, BCRx's, copy from BSC locations */
166 146
167 /* check BCR for SDRAM in specified area */ 147 /* check BCR for SDRAM in specified area */
168 switch (map->window0.base) { 148 switch (sh7751_pci_map.window0.base) {
169 case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(0); break; 149 case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(chan, 0); break;
170 case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(1); break; 150 case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(chan, 1); break;
171 case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(2); break; 151 case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(chan, 2); break;
172 case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(3); break; 152 case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(chan, 3); break;
173 case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(4); break; 153 case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(chan, 4); break;
174 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(5); break; 154 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(chan, 5); break;
175 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(6); break; 155 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(chan, 6); break;
176 } 156 }
177 157
178 if (!word) 158 if (!word)
179 return 0; 159 return -1;
180 160
181 /* configure the wait control registers */ 161 /* configure the wait control registers */
182 word = ctrl_inl(SH7751_WCR1); 162 word = ctrl_inl(SH7751_WCR1);
183 pci_write_reg(word, SH4_PCIWCR1); 163 pci_write_reg(chan, word, SH4_PCIWCR1);
184 word = ctrl_inl(SH7751_WCR2); 164 word = ctrl_inl(SH7751_WCR2);
185 pci_write_reg(word, SH4_PCIWCR2); 165 pci_write_reg(chan, word, SH4_PCIWCR2);
186 word = ctrl_inl(SH7751_WCR3); 166 word = ctrl_inl(SH7751_WCR3);
187 pci_write_reg(word, SH4_PCIWCR3); 167 pci_write_reg(chan, word, SH4_PCIWCR3);
188 word = ctrl_inl(SH7751_MCR); 168 word = ctrl_inl(SH7751_MCR);
189 pci_write_reg(word, SH4_PCIMCR); 169 pci_write_reg(chan, word, SH4_PCIMCR);
190 170
191 /* NOTE: I'm ignoring the PCI error IRQs for now.. 171 /* NOTE: I'm ignoring the PCI error IRQs for now..
192 * TODO: add support for the internal error interrupts and 172 * TODO: add support for the internal error interrupts and
193 * DMA interrupts... 173 * DMA interrupts...
194 */ 174 */
195 175
196 pci_fixup_pcic(); 176 pci_fixup_pcic(chan);
197 177
198 /* SH7751 init done, set central function init complete */ 178 /* SH7751 init done, set central function init complete */
199 /* use round robin mode to stop a device starving/overruning */ 179 /* use round robin mode to stop a device starving/overruning */
200 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM; 180 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM;
201 pci_write_reg(word, SH4_PCICR); 181 pci_write_reg(chan, word, SH4_PCICR);
202 182
203 return 1; 183 register_pci_controller(chan);
184
185 return 0;
204} 186}
187arch_initcall(sh7751_pci_init);
diff --git a/arch/sh/drivers/pci/pci-sh7751.h b/arch/sh/drivers/pci/pci-sh7751.h
index 68e3cb5e6bec..4983a4d20355 100644
--- a/arch/sh/drivers/pci/pci-sh7751.h
+++ b/arch/sh/drivers/pci/pci-sh7751.h
@@ -26,7 +26,6 @@
26#define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */ 26#define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
27 27
28#define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */ 28#define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
29#define PCI_REG(n) (SH7751_PCIREG_BASE+ n)
30 29
31#define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */ 30#define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */
32 #define SH7751_PCICONF0_DEVID 0xFFFF0000 /* Device ID */ 31 #define SH7751_PCICONF0_DEVID 0xFFFF0000 /* Device ID */
@@ -58,7 +57,7 @@
58 #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */ 57 #define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */
59 #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */ 58 #define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */
60 #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */ 59 #define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */
61#define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */ 60#define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */
62 #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */ 61 #define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */
63 #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */ 62 #define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */
64 #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */ 63 #define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */
@@ -73,12 +72,12 @@
73 #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */ 72 #define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
74 #define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */ 73 #define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */
75 #define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */ 74 #define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */
76 #define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */ 75 #define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */
77#define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */ 76#define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */
78 #define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */ 77 #define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
79 #define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */ 78 #define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */
80 #define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */ 79 #define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */
81 #define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */ 80 #define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */
82/* PCICONF7 - PCICONF10 are undefined */ 81/* PCICONF7 - PCICONF10 are undefined */
83#define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */ 82#define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */
84 #define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */ 83 #define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */
@@ -127,9 +126,4 @@
127#define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE) 126#define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE)
128#define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE) 127#define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE)
129 128
130struct sh4_pci_address_map;
131
132/* arch/sh/drivers/pci/pci-sh7751.c */
133int sh7751_pcic_init(struct sh4_pci_address_map *map);
134
135#endif /* _PCI_SH7751_H_ */ 129#endif /* _PCI_SH7751_H_ */
diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c
index bae6a2cf047d..323b92d565fe 100644
--- a/arch/sh/drivers/pci/pci-sh7780.c
+++ b/arch/sh/drivers/pci/pci-sh7780.c
@@ -1,19 +1,12 @@
1/* 1/*
2 * Low-Level PCI Support for the SH7780 2 * Low-Level PCI Support for the SH7780
3 * 3 *
4 * Dustin McIntire (dustin@sensoria.com) 4 * Copyright (C) 2005 - 2009 Paul Mundt
5 * Derived from arch/i386/kernel/pci-*.c which bore the message:
6 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
7 *
8 * Ported to the new API by Paul Mundt <lethal@linux-sh.org>
9 * With cleanup by Paul van Gool <pvangool@mimotech.com>
10 *
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
13 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
14 */ 9 */
15#undef DEBUG
16
17#include <linux/types.h> 10#include <linux/types.h>
18#include <linux/kernel.h> 11#include <linux/kernel.h>
19#include <linux/init.h> 12#include <linux/init.h>
@@ -22,135 +15,132 @@
22#include <linux/delay.h> 15#include <linux/delay.h>
23#include "pci-sh4.h" 16#include "pci-sh4.h"
24 17
25#define INTC_BASE 0xffd00000 18static struct resource sh7785_io_resource = {
26#define INTC_ICR0 (INTC_BASE+0x0) 19 .name = "SH7785_IO",
27#define INTC_ICR1 (INTC_BASE+0x1c) 20 .start = SH7780_PCI_IO_BASE,
28#define INTC_INTPRI (INTC_BASE+0x10) 21 .end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
29#define INTC_INTREQ (INTC_BASE+0x24) 22 .flags = IORESOURCE_IO
30#define INTC_INTMSK0 (INTC_BASE+0x44) 23};
31#define INTC_INTMSK1 (INTC_BASE+0x48) 24
32#define INTC_INTMSK2 (INTC_BASE+0x40080) 25static struct resource sh7785_mem_resource = {
33#define INTC_INTMSKCLR0 (INTC_BASE+0x64) 26 .name = "SH7785_mem",
34#define INTC_INTMSKCLR1 (INTC_BASE+0x68) 27 .start = SH7780_PCI_MEMORY_BASE,
35#define INTC_INTMSKCLR2 (INTC_BASE+0x40084) 28 .end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
36#define INTC_INT2MSKR (INTC_BASE+0x40038) 29 .flags = IORESOURCE_MEM
37#define INTC_INT2MSKCR (INTC_BASE+0x4003c) 30};
31
32static struct pci_channel sh7780_pci_controller = {
33 .pci_ops = &sh4_pci_ops,
34 .mem_resource = &sh7785_mem_resource,
35 .mem_offset = 0x00000000,
36 .io_resource = &sh7785_io_resource,
37 .io_offset = 0x00000000,
38 .io_map_base = SH7780_PCI_IO_BASE,
39};
40
41static struct sh4_pci_address_map sh7780_pci_map = {
42 .window0 = {
43#if defined(CONFIG_32BIT)
44 .base = SH7780_32BIT_DDR_BASE_ADDR,
45 .size = 0x40000000,
46#else
47 .base = SH7780_CS0_BASE_ADDR,
48 .size = 0x20000000,
49#endif
50 },
51};
38 52
39/*
40 * Initialization. Try all known PCI access methods. Note that we support
41 * using both PCI BIOS and direct access: in such cases, we use I/O ports
42 * to access config space.
43 *
44 * Note that the platform specific initialization (BSC registers, and memory
45 * space mapping) will be called via the platform defined function
46 * pcibios_init_platform().
47 */
48static int __init sh7780_pci_init(void) 53static int __init sh7780_pci_init(void)
49{ 54{
55 struct pci_channel *chan = &sh7780_pci_controller;
50 unsigned int id; 56 unsigned int id;
51 int ret, match = 0; 57 const char *type = NULL;
52 58 int ret;
53 pr_debug("PCI: Starting intialization.\n"); 59 u32 word;
54
55 ctrl_outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
56
57 /* check for SH7780/SH7780R hardware */
58 id = pci_read_reg(SH7780_PCIVID);
59 if ((id & 0xffff) == SH7780_VENDOR_ID) {
60 switch ((id >> 16) & 0xffff) {
61 case SH7763_DEVICE_ID:
62 case SH7780_DEVICE_ID:
63 case SH7781_DEVICE_ID:
64 case SH7785_DEVICE_ID:
65 match = 1;
66 break;
67 }
68 }
69 60
70 if (unlikely(!match)) { 61 printk(KERN_NOTICE "PCI: Starting intialization.\n");
71 printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id); 62
63 chan->reg_base = 0xfe040000;
64
65 /* Enable CPU access to the PCIC registers. */
66 __raw_writel(PCIECR_ENBL, PCIECR);
67
68 id = __raw_readw(chan->reg_base + SH7780_PCIVID);
69 if (id != SH7780_VENDOR_ID) {
70 printk(KERN_ERR "PCI: Unknown vendor ID 0x%04x.\n", id);
72 return -ENODEV; 71 return -ENODEV;
73 } 72 }
74 73
75 /* Setup the INTC */ 74 id = __raw_readw(chan->reg_base + SH7780_PCIDID);
76 if (mach_is_7780se()) { 75 type = (id == SH7763_DEVICE_ID) ? "SH7763" :
77 /* ICR0: IRL=use separately */ 76 (id == SH7780_DEVICE_ID) ? "SH7780" :
78 ctrl_outl(0x00C00020, INTC_ICR0); 77 (id == SH7781_DEVICE_ID) ? "SH7781" :
79 /* ICR1: detect low level(for 2ndcut) */ 78 (id == SH7785_DEVICE_ID) ? "SH7785" :
80 ctrl_outl(0xAAAA0000, INTC_ICR1); 79 NULL;
81 /* INTPRI: priority=3(all) */ 80 if (unlikely(!type)) {
82 ctrl_outl(0x33333333, INTC_INTPRI); 81 printk(KERN_ERR "PCI: Found an unsupported Renesas host "
82 "controller, device id 0x%04x.\n", id);
83 return -EINVAL;
83 } 84 }
84 85
85 if ((ret = sh4_pci_check_direct()) != 0) 86 printk(KERN_NOTICE "PCI: Found a Renesas %s host "
86 return ret; 87 "controller, revision %d.\n", type,
88 __raw_readb(chan->reg_base + SH7780_PCIRID));
87 89
88 return pcibios_init_platform(); 90 if ((ret = sh4_pci_check_direct(chan)) != 0)
89} 91 return ret;
90core_initcall(sh7780_pci_init);
91
92int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
93{
94 u32 word;
95 92
96 /* 93 /*
97 * This code is unused for some boards as it is done in the 94 * Set the class and sub-class codes.
98 * bootloader and doing it here means the MAC addresses loaded
99 * by the bootloader get lost.
100 */
101 if (!(map->flags & SH4_PCIC_NO_RESET)) {
102 /* toggle PCI reset pin */
103 word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
104 pci_write_reg(word, SH4_PCICR);
105 /* Wait for a long time... not 1 sec. but long enough */
106 mdelay(100);
107 word = SH4_PCICR_PREFIX;
108 pci_write_reg(word, SH4_PCICR);
109 }
110
111 /* set the command/status bits to:
112 * Wait Cycle Control + Parity Enable + Bus Master +
113 * Mem space enable
114 */ 95 */
115 pci_write_reg(0x00000046, SH7780_PCICMD); 96 __raw_writeb(PCI_CLASS_BRIDGE_HOST >> 8,
116 97 chan->reg_base + SH7780_PCIBCC);
117 /* define this host as the host bridge */ 98 __raw_writeb(PCI_CLASS_BRIDGE_HOST & 0xff,
118 word = PCI_BASE_CLASS_BRIDGE << 24; 99 chan->reg_base + SH7780_PCISUB);
119 pci_write_reg(word, SH7780_PCIRID);
120 100
121 /* Set IO and Mem windows to local address 101 /*
102 * Set IO and Mem windows to local address
122 * Make PCI and local address the same for easy 1 to 1 mapping 103 * Make PCI and local address the same for easy 1 to 1 mapping
123 */ 104 */
124 pci_write_reg(map->window0.size - 0xfffff, SH4_PCILSR0); 105 pci_write_reg(chan, sh7780_pci_map.window0.size - 0xfffff, SH4_PCILSR0);
125 pci_write_reg(map->window1.size - 0xfffff, SH4_PCILSR1);
126 /* Set the values on window 0 PCI config registers */ 106 /* Set the values on window 0 PCI config registers */
127 pci_write_reg(map->window0.base, SH4_PCILAR0); 107 pci_write_reg(chan, sh7780_pci_map.window0.base, SH4_PCILAR0);
128 pci_write_reg(map->window0.base, SH7780_PCIMBAR0); 108 pci_write_reg(chan, sh7780_pci_map.window0.base, SH7780_PCIMBAR0);
129 /* Set the values on window 1 PCI config registers */
130 pci_write_reg(map->window1.base, SH4_PCILAR1);
131 pci_write_reg(map->window1.base, SH7780_PCIMBAR1);
132
133 /* Map IO space into PCI IO window
134 * The IO window is 64K-PCIBIOS_MIN_IO in size
135 * IO addresses will be translated to the
136 * PCI IO window base address
137 */
138 pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
139 PCIBIOS_MIN_IO, (64 << 10),
140 SH7780_PCI_IO_BASE + PCIBIOS_MIN_IO);
141 109
142 /* NOTE: I'm ignoring the PCI error IRQs for now.. 110 pci_write_reg(chan, 0x0000380f, SH4_PCIAINTM);
143 * TODO: add support for the internal error interrupts and 111
144 * DMA interrupts... 112 /* Set up standard PCI config registers */
145 */ 113 __raw_writew(0xFB00, chan->reg_base + SH7780_PCISTATUS);
114 __raw_writew(0x0047, chan->reg_base + SH7780_PCICMD);
115 __raw_writew(0x1912, chan->reg_base + SH7780_PCISVID);
116 __raw_writew(0x0001, chan->reg_base + SH7780_PCISID);
117
118 __raw_writeb(0x00, chan->reg_base + SH7780_PCIPIF);
146 119
147 /* Apply any last-minute PCIC fixups */ 120 /* Apply any last-minute PCIC fixups */
148 pci_fixup_pcic(); 121 pci_fixup_pcic(chan);
122
123 pci_write_reg(chan, 0xfd000000, SH7780_PCIMBR0);
124 pci_write_reg(chan, 0x00fc0000, SH7780_PCIMBMR0);
125
126#ifdef CONFIG_32BIT
127 pci_write_reg(chan, 0xc0000000, SH7780_PCIMBR2);
128 pci_write_reg(chan, 0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2);
129#endif
130
131 /* Set IOBR for windows containing area specified in pci.h */
132 pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),
133 SH7780_PCIIOBR);
134 pci_write_reg(chan, ((SH7780_PCI_IO_SIZE-1) & (7<<18)),
135 SH7780_PCIIOBMR);
149 136
150 /* SH7780 init done, set central function init complete */ 137 /* SH7780 init done, set central function init complete */
151 /* use round robin mode to stop a device starving/overruning */ 138 /* use round robin mode to stop a device starving/overruning */
152 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO; 139 word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
153 pci_write_reg(word, SH4_PCICR); 140 pci_write_reg(chan, word, SH4_PCICR);
141
142 register_pci_controller(chan);
154 143
155 return 1; 144 return 0;
156} 145}
146arch_initcall(sh7780_pci_init);
diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h
index 93adc7119b79..4a52478c97cf 100644
--- a/arch/sh/drivers/pci/pci-sh7780.h
+++ b/arch/sh/drivers/pci/pci-sh7780.h
@@ -20,9 +20,8 @@
20#define SH7785_DEVICE_ID 0x0007 20#define SH7785_DEVICE_ID 0x0007
21 21
22/* SH7780 Control Registers */ 22/* SH7780 Control Registers */
23#define SH7780_PCI_VCR0 0xFE000000 23#define PCIECR 0xFE000008
24#define SH7780_PCI_VCR1 0xFE000004 24#define PCIECR_ENBL 0x01
25#define SH7780_PCI_VCR2 0xFE000008
26 25
27/* SH7780 Specific Values */ 26/* SH7780 Specific Values */
28#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */ 27#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
@@ -35,7 +34,6 @@
35#define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */ 34#define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */
36 35
37#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */ 36#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
38#define PCI_REG(n) (SH7780_PCIREG_BASE+n)
39 37
40/* SH7780 PCI Config Registers */ 38/* SH7780 PCI Config Registers */
41#define SH7780_PCIVID 0x000 /* Vendor ID */ 39#define SH7780_PCIVID 0x000 /* Vendor ID */
@@ -67,11 +65,6 @@
67#define SH7780_PCIPMCSR_BSE 0x046 65#define SH7780_PCIPMCSR_BSE 0x046
68#define SH7780_PCICDD 0x047 66#define SH7780_PCICDD 0x047
69 67
70#define SH7780_PCICR 0x100 /* PCI Control Register */
71#define SH7780_PCILSR 0x104 /* PCI Local Space Register0 */
72#define SH7780_PCILSR1 0x108 /* PCI Local Space Register1 */
73#define SH7780_PCILAR0 0x10C /* PCI Local Address Register1 */
74#define SH7780_PCILAR1 0x110 /* PCI Local Address Register1 */
75#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */ 68#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */
76#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */ 69#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */
77#define SH7780_PCIAIR 0x11C /* Error Address Register */ 70#define SH7780_PCIAIR 0x11C /* Error Address Register */
@@ -106,9 +99,4 @@
106 99
107#define SH7780_32BIT_DDR_BASE_ADDR 0x40000000 100#define SH7780_32BIT_DDR_BASE_ADDR 0x40000000
108 101
109struct sh4_pci_address_map;
110
111/* arch/sh/drivers/pci/pci-sh7780.c */
112int sh7780_pcic_init(struct sh4_pci_address_map *map);
113
114#endif /* _PCI_SH7780_H_ */ 102#endif /* _PCI_SH7780_H_ */
diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c
index 0d6ac7a1db49..54d77cbb8b39 100644
--- a/arch/sh/drivers/pci/pci.c
+++ b/arch/sh/drivers/pci/pci.c
@@ -1,67 +1,156 @@
1/* 1/*
2 * arch/sh/drivers/pci/pci.c 2 * New-style PCI core.
3 * 3 *
4 * Copyright (c) 2002 M. R. Brown <mrbrown@linux-sh.org> 4 * Copyright (c) 2004 - 2009 Paul Mundt
5 * Copyright (c) 2004 - 2006 Paul Mundt <lethal@linux-sh.org> 5 * Copyright (c) 2002 M. R. Brown
6 * 6 *
7 * These functions are collected here to reduce duplication of common 7 * Modelled after arch/mips/pci/pci.c:
8 * code amongst the many platform-specific PCI support code files. 8 * Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
9 *
10 * These routines require the following board-specific routines:
11 * void pcibios_fixup_irqs();
12 *
13 * See include/asm-sh/pci.h for more information.
14 * 9 *
15 * This file is subject to the terms and conditions of the GNU General Public 10 * This file is subject to the terms and conditions of the GNU General Public
16 * License. See the file "COPYING" in the main directory of this archive 11 * License. See the file "COPYING" in the main directory of this archive
17 * for more details. 12 * for more details.
18 */ 13 */
19#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/mm.h>
20#include <linux/pci.h> 16#include <linux/pci.h>
21#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/types.h>
22#include <linux/dma-debug.h> 19#include <linux/dma-debug.h>
23#include <asm/io.h> 20#include <linux/io.h>
21#include <linux/mutex.h>
24 22
25static int __init pcibios_init(void) 23unsigned long PCIBIOS_MIN_IO = 0x0000;
24unsigned long PCIBIOS_MIN_MEM = 0;
25
26/*
27 * The PCI controller list.
28 */
29static struct pci_channel *hose_head, **hose_tail = &hose_head;
30
31static int pci_initialized;
32
33static void __devinit pcibios_scanbus(struct pci_channel *hose)
26{ 34{
27 struct pci_channel *p; 35 static int next_busno;
28 struct pci_bus *bus; 36 struct pci_bus *bus;
29 int busno;
30 37
31#ifdef CONFIG_PCI_AUTO 38 bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
32 /* assign resources */ 39 if (bus) {
33 busno = 0; 40 next_busno = bus->subordinate + 1;
34 for (p = board_pci_channels; p->pci_ops != NULL; p++) 41 /* Don't allow 8-bit bus number overflow inside the hose -
35 busno = pciauto_assign_resources(busno, p) + 1; 42 reserve some space for bridges. */
36#endif 43 if (next_busno > 224)
44 next_busno = 0;
45
46 pci_bus_size_bridges(bus);
47 pci_bus_assign_resources(bus);
48 pci_enable_bridges(bus);
49 }
50}
51
52static DEFINE_MUTEX(pci_scan_mutex);
37 53
38 /* scan the buses */ 54void __devinit register_pci_controller(struct pci_channel *hose)
39 busno = 0; 55{
40 for (p = board_pci_channels; p->pci_ops != NULL; p++) { 56 if (request_resource(&iomem_resource, hose->mem_resource) < 0)
41 bus = pci_scan_bus(busno, p->pci_ops, p); 57 goto out;
42 busno = bus->subordinate + 1; 58 if (request_resource(&ioport_resource, hose->io_resource) < 0) {
59 release_resource(hose->mem_resource);
60 goto out;
43 } 61 }
44 62
63 *hose_tail = hose;
64 hose_tail = &hose->next;
65
66 /*
67 * Do not panic here but later - this might hapen before console init.
68 */
69 if (!hose->io_map_base) {
70 printk(KERN_WARNING
71 "registering PCI controller with io_map_base unset\n");
72 }
73
74 /*
75 * Scan the bus if it is register after the PCI subsystem
76 * initialization.
77 */
78 if (pci_initialized) {
79 mutex_lock(&pci_scan_mutex);
80 pcibios_scanbus(hose);
81 mutex_unlock(&pci_scan_mutex);
82 }
83
84 return;
85
86out:
87 printk(KERN_WARNING
88 "Skipping PCI bus scan due to resource conflict\n");
89}
90
91static int __init pcibios_init(void)
92{
93 struct pci_channel *hose;
94
95 /* Scan all of the recorded PCI controllers. */
96 for (hose = hose_head; hose; hose = hose->next)
97 pcibios_scanbus(hose);
98
45 pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq); 99 pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq);
46 100
47 dma_debug_add_bus(&pci_bus_type); 101 dma_debug_add_bus(&pci_bus_type);
48 102
103 pci_initialized = 1;
104
49 return 0; 105 return 0;
50} 106}
51subsys_initcall(pcibios_init); 107subsys_initcall(pcibios_init);
52 108
109static void pcibios_fixup_device_resources(struct pci_dev *dev,
110 struct pci_bus *bus)
111{
112 /* Update device resources. */
113 struct pci_channel *hose = bus->sysdata;
114 unsigned long offset = 0;
115 int i;
116
117 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
118 if (!dev->resource[i].start)
119 continue;
120 if (dev->resource[i].flags & IORESOURCE_PCI_FIXED)
121 continue;
122 if (dev->resource[i].flags & IORESOURCE_IO)
123 offset = hose->io_offset;
124 else if (dev->resource[i].flags & IORESOURCE_MEM)
125 offset = hose->mem_offset;
126
127 dev->resource[i].start += offset;
128 dev->resource[i].end += offset;
129 }
130}
131
53/* 132/*
54 * Called after each bus is probed, but before its children 133 * Called after each bus is probed, but before its children
55 * are examined. 134 * are examined.
56 */ 135 */
57void __devinit __weak pcibios_fixup_bus(struct pci_bus *bus) 136void __devinit pcibios_fixup_bus(struct pci_bus *bus)
58{ 137{
59 pci_read_bridge_bases(bus); 138 struct pci_dev *dev = bus->self;
60} 139 struct list_head *ln;
140 struct pci_channel *chan = bus->sysdata;
61 141
62void pcibios_align_resource(void *data, struct resource *res, 142 if (!dev) {
63 resource_size_t size, resource_size_t align) 143 bus->resource[0] = chan->io_resource;
64 __attribute__ ((weak)); 144 bus->resource[1] = chan->mem_resource;
145 }
146
147 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
148 dev = pci_dev_b(ln);
149
150 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
151 pcibios_fixup_device_resources(dev, bus);
152 }
153}
65 154
66/* 155/*
67 * We need to avoid collisions with `mirrored' VGA ports 156 * We need to avoid collisions with `mirrored' VGA ports
@@ -72,14 +161,58 @@ void pcibios_align_resource(void *data, struct resource *res,
72void pcibios_align_resource(void *data, struct resource *res, 161void pcibios_align_resource(void *data, struct resource *res,
73 resource_size_t size, resource_size_t align) 162 resource_size_t size, resource_size_t align)
74{ 163{
164 struct pci_dev *dev = data;
165 struct pci_channel *chan = dev->sysdata;
166 resource_size_t start = res->start;
167
75 if (res->flags & IORESOURCE_IO) { 168 if (res->flags & IORESOURCE_IO) {
76 resource_size_t start = res->start; 169 if (start < PCIBIOS_MIN_IO + chan->io_resource->start)
170 start = PCIBIOS_MIN_IO + chan->io_resource->start;
77 171
172 /*
173 * Put everything into 0x00-0xff region modulo 0x400.
174 */
78 if (start & 0x300) { 175 if (start & 0x300) {
79 start = (start + 0x3ff) & ~0x3ff; 176 start = (start + 0x3ff) & ~0x3ff;
80 res->start = start; 177 res->start = start;
81 } 178 }
179 } else if (res->flags & IORESOURCE_MEM) {
180 if (start < PCIBIOS_MIN_MEM + chan->mem_resource->start)
181 start = PCIBIOS_MIN_MEM + chan->mem_resource->start;
82 } 182 }
183
184 res->start = start;
185}
186
187void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
188 struct resource *res)
189{
190 struct pci_channel *hose = dev->sysdata;
191 unsigned long offset = 0;
192
193 if (res->flags & IORESOURCE_IO)
194 offset = hose->io_offset;
195 else if (res->flags & IORESOURCE_MEM)
196 offset = hose->mem_offset;
197
198 region->start = res->start - offset;
199 region->end = res->end - offset;
200}
201
202void __devinit
203pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
204 struct pci_bus_region *region)
205{
206 struct pci_channel *hose = dev->sysdata;
207 unsigned long offset = 0;
208
209 if (res->flags & IORESOURCE_IO)
210 offset = hose->io_offset;
211 else if (res->flags & IORESOURCE_MEM)
212 offset = hose->mem_offset;
213
214 res->start = region->start + offset;
215 res->end = region->end + offset;
83} 216}
84 217
85int pcibios_enable_device(struct pci_dev *dev, int mask) 218int pcibios_enable_device(struct pci_dev *dev, int mask)
@@ -90,13 +223,21 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
90 223
91 pci_read_config_word(dev, PCI_COMMAND, &cmd); 224 pci_read_config_word(dev, PCI_COMMAND, &cmd);
92 old_cmd = cmd; 225 old_cmd = cmd;
93 for(idx=0; idx<6; idx++) { 226 for (idx=0; idx < PCI_NUM_RESOURCES; idx++) {
94 if (!(mask & (1 << idx))) 227 /* Only set up the requested stuff */
228 if (!(mask & (1<<idx)))
95 continue; 229 continue;
230
96 r = &dev->resource[idx]; 231 r = &dev->resource[idx];
232 if (!(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
233 continue;
234 if ((idx == PCI_ROM_RESOURCE) &&
235 (!(r->flags & IORESOURCE_ROM_ENABLE)))
236 continue;
97 if (!r->start && r->end) { 237 if (!r->start && r->end) {
98 printk(KERN_ERR "PCI: Device %s not available because " 238 printk(KERN_ERR "PCI: Device %s not available "
99 "of resource collisions\n", pci_name(dev)); 239 "because of resource collisions\n",
240 pci_name(dev));
100 return -EINVAL; 241 return -EINVAL;
101 } 242 }
102 if (r->flags & IORESOURCE_IO) 243 if (r->flags & IORESOURCE_IO)
@@ -104,10 +245,8 @@ int pcibios_enable_device(struct pci_dev *dev, int mask)
104 if (r->flags & IORESOURCE_MEM) 245 if (r->flags & IORESOURCE_MEM)
105 cmd |= PCI_COMMAND_MEMORY; 246 cmd |= PCI_COMMAND_MEMORY;
106 } 247 }
107 if (dev->resource[PCI_ROM_RESOURCE].start)
108 cmd |= PCI_COMMAND_MEMORY;
109 if (cmd != old_cmd) { 248 if (cmd != old_cmd) {
110 printk(KERN_INFO "PCI: Enabling device %s (%04x -> %04x)\n", 249 printk("PCI: Enabling device %s (%04x -> %04x)\n",
111 pci_name(dev), old_cmd, cmd); 250 pci_name(dev), old_cmd, cmd);
112 pci_write_config_word(dev, PCI_COMMAND, cmd); 251 pci_write_config_word(dev, PCI_COMMAND, cmd);
113 } 252 }
@@ -140,6 +279,43 @@ void __init pcibios_update_irq(struct pci_dev *dev, int irq)
140 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); 279 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
141} 280}
142 281
282char * __devinit pcibios_setup(char *str)
283{
284 return str;
285}
286
287int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
288 enum pci_mmap_state mmap_state, int write_combine)
289{
290 /*
291 * I/O space can be accessed via normal processor loads and stores on
292 * this platform but for now we elect not to do this and portable
293 * drivers should not do this anyway.
294 */
295 if (mmap_state == pci_mmap_io)
296 return -EINVAL;
297
298 /*
299 * Ignore write-combine; for now only return uncached mappings.
300 */
301 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
302
303 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
304 vma->vm_end - vma->vm_start,
305 vma->vm_page_prot);
306}
307
308static void __iomem *ioport_map_pci(struct pci_dev *dev,
309 unsigned long port, unsigned int nr)
310{
311 struct pci_channel *chan = dev->sysdata;
312
313 if (!chan->io_map_base)
314 chan->io_map_base = generic_io_base;
315
316 return (void __iomem *)(chan->io_map_base + port);
317}
318
143void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) 319void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
144{ 320{
145 resource_size_t start = pci_resource_start(dev, bar); 321 resource_size_t start = pci_resource_start(dev, bar);
@@ -151,20 +327,24 @@ void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
151 if (maxlen && len > maxlen) 327 if (maxlen && len > maxlen)
152 len = maxlen; 328 len = maxlen;
153 329
330 if (flags & IORESOURCE_IO)
331 return ioport_map_pci(dev, start, len);
332
154 /* 333 /*
155 * Presently the IORESOURCE_MEM case is a bit special, most 334 * Presently the IORESOURCE_MEM case is a bit special, most
156 * SH7751 style PCI controllers have PCI memory at a fixed 335 * SH7751 style PCI controllers have PCI memory at a fixed
157 * location in the address space where no remapping is desired 336 * location in the address space where no remapping is desired.
158 * (typically at 0xfd000000, but is_pci_memaddr() will know 337 * With the IORESOURCE_MEM case more care has to be taken
159 * best). With the IORESOURCE_MEM case more care has to be taken
160 * to inhibit page table mapping for legacy cores, but this is 338 * to inhibit page table mapping for legacy cores, but this is
161 * punted off to __ioremap(). 339 * punted off to __ioremap().
162 * -- PFM. 340 * -- PFM.
163 */ 341 */
164 if (flags & IORESOURCE_IO) 342 if (flags & IORESOURCE_MEM) {
165 return ioport_map(start, len); 343 if (flags & IORESOURCE_CACHEABLE)
166 if (flags & IORESOURCE_MEM) 344 return ioremap(start, len);
167 return ioremap(start, len); 345
346 return ioremap_nocache(start, len);
347 }
168 348
169 return NULL; 349 return NULL;
170} 350}
@@ -175,3 +355,10 @@ void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
175 iounmap(addr); 355 iounmap(addr);
176} 356}
177EXPORT_SYMBOL(pci_iounmap); 357EXPORT_SYMBOL(pci_iounmap);
358
359#ifdef CONFIG_HOTPLUG
360EXPORT_SYMBOL(pcibios_resource_to_bus);
361EXPORT_SYMBOL(pcibios_bus_to_resource);
362EXPORT_SYMBOL(PCIBIOS_MIN_IO);
363EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
364#endif
diff --git a/arch/sh/include/asm/atomic-llsc.h b/arch/sh/include/asm/atomic-llsc.h
index 4b00b78e3f4f..b040e1e08610 100644
--- a/arch/sh/include/asm/atomic-llsc.h
+++ b/arch/sh/include/asm/atomic-llsc.h
@@ -104,4 +104,31 @@ static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
104 : "t"); 104 : "t");
105} 105}
106 106
107#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
108
109/**
110 * atomic_add_unless - add unless the number is a given value
111 * @v: pointer of type atomic_t
112 * @a: the amount to add to v...
113 * @u: ...unless v is equal to u.
114 *
115 * Atomically adds @a to @v, so long as it was not @u.
116 * Returns non-zero if @v was not @u, and zero otherwise.
117 */
118static inline int atomic_add_unless(atomic_t *v, int a, int u)
119{
120 int c, old;
121 c = atomic_read(v);
122 for (;;) {
123 if (unlikely(c == (u)))
124 break;
125 old = atomic_cmpxchg((v), c, c + (a));
126 if (likely(old == c))
127 break;
128 c = old;
129 }
130
131 return c != (u);
132}
133
107#endif /* __ASM_SH_ATOMIC_LLSC_H */ 134#endif /* __ASM_SH_ATOMIC_LLSC_H */
diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h
index 6327ffbb1992..978b58efb1e9 100644
--- a/arch/sh/include/asm/atomic.h
+++ b/arch/sh/include/asm/atomic.h
@@ -45,7 +45,7 @@
45#define atomic_inc(v) atomic_add(1,(v)) 45#define atomic_inc(v) atomic_add(1,(v))
46#define atomic_dec(v) atomic_sub(1,(v)) 46#define atomic_dec(v) atomic_sub(1,(v))
47 47
48#ifndef CONFIG_GUSA_RB 48#if !defined(CONFIG_GUSA_RB) && !defined(CONFIG_CPU_SH4A)
49static inline int atomic_cmpxchg(atomic_t *v, int old, int new) 49static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
50{ 50{
51 int ret; 51 int ret;
@@ -73,7 +73,7 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
73 73
74 return ret != u; 74 return ret != u;
75} 75}
76#endif 76#endif /* !CONFIG_GUSA_RB && !CONFIG_CPU_SH4A */
77 77
78#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) 78#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
79#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) 79#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
diff --git a/arch/sh/include/asm/cacheflush.h b/arch/sh/include/asm/cacheflush.h
index 09acbc32d6c7..4c5462daa74c 100644
--- a/arch/sh/include/asm/cacheflush.h
+++ b/arch/sh/include/asm/cacheflush.h
@@ -75,7 +75,5 @@ extern void copy_from_user_page(struct vm_area_struct *vma,
75#define flush_cache_vmap(start, end) flush_cache_all() 75#define flush_cache_vmap(start, end) flush_cache_all()
76#define flush_cache_vunmap(start, end) flush_cache_all() 76#define flush_cache_vunmap(start, end) flush_cache_all()
77 77
78#define HAVE_ARCH_UNMAPPED_AREA
79
80#endif /* __KERNEL__ */ 78#endif /* __KERNEL__ */
81#endif /* __ASM_SH_CACHEFLUSH_H */ 79#endif /* __ASM_SH_CACHEFLUSH_H */
diff --git a/arch/sh/include/asm/clock.h b/arch/sh/include/asm/clock.h
index 2f6c9627bc1f..9fe7d7f8af40 100644
--- a/arch/sh/include/asm/clock.h
+++ b/arch/sh/include/asm/clock.h
@@ -1,9 +1,9 @@
1#ifndef __ASM_SH_CLOCK_H 1#ifndef __ASM_SH_CLOCK_H
2#define __ASM_SH_CLOCK_H 2#define __ASM_SH_CLOCK_H
3 3
4#include <linux/kref.h>
5#include <linux/list.h> 4#include <linux/list.h>
6#include <linux/seq_file.h> 5#include <linux/seq_file.h>
6#include <linux/cpufreq.h>
7#include <linux/clk.h> 7#include <linux/clk.h>
8#include <linux/err.h> 8#include <linux/err.h>
9 9
@@ -11,9 +11,9 @@ struct clk;
11 11
12struct clk_ops { 12struct clk_ops {
13 void (*init)(struct clk *clk); 13 void (*init)(struct clk *clk);
14 void (*enable)(struct clk *clk); 14 int (*enable)(struct clk *clk);
15 void (*disable)(struct clk *clk); 15 void (*disable)(struct clk *clk);
16 void (*recalc)(struct clk *clk); 16 unsigned long (*recalc)(struct clk *clk);
17 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id); 17 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
18 int (*set_parent)(struct clk *clk, struct clk *parent); 18 int (*set_parent)(struct clk *clk, struct clk *parent);
19 long (*round_rate)(struct clk *clk, unsigned long rate); 19 long (*round_rate)(struct clk *clk, unsigned long rate);
@@ -28,43 +28,47 @@ struct clk {
28 struct clk *parent; 28 struct clk *parent;
29 struct clk_ops *ops; 29 struct clk_ops *ops;
30 30
31 struct kref kref; 31 struct list_head children;
32 struct list_head sibling; /* node for children */
33
34 int usecount;
32 35
33 unsigned long rate; 36 unsigned long rate;
34 unsigned long flags; 37 unsigned long flags;
38
39 void __iomem *enable_reg;
40 unsigned int enable_bit;
41
35 unsigned long arch_flags; 42 unsigned long arch_flags;
43 void *priv;
44 struct dentry *dentry;
45 struct cpufreq_frequency_table *freq_table;
46};
47
48struct clk_lookup {
49 struct list_head node;
50 const char *dev_id;
51 const char *con_id;
52 struct clk *clk;
36}; 53};
37 54
38#define CLK_ALWAYS_ENABLED (1 << 0) 55#define CLK_ENABLE_ON_INIT (1 << 0)
39#define CLK_RATE_PROPAGATES (1 << 1)
40 56
41/* Should be defined by processor-specific code */ 57/* Should be defined by processor-specific code */
42void arch_init_clk_ops(struct clk_ops **, int type); 58void __deprecated arch_init_clk_ops(struct clk_ops **, int type);
43int __init arch_clk_init(void); 59int __init arch_clk_init(void);
44 60
45/* arch/sh/kernel/cpu/clock.c */ 61/* arch/sh/kernel/cpu/clock.c */
46int clk_init(void); 62int clk_init(void);
47 63unsigned long followparent_recalc(struct clk *);
48void clk_recalc_rate(struct clk *); 64void recalculate_root_clocks(void);
49 65void propagate_rate(struct clk *);
66int clk_reparent(struct clk *child, struct clk *parent);
50int clk_register(struct clk *); 67int clk_register(struct clk *);
51void clk_unregister(struct clk *); 68void clk_unregister(struct clk *);
52 69
53static inline int clk_always_enable(const char *id) 70/* arch/sh/kernel/cpu/clock-cpg.c */
54{ 71int __init __deprecated cpg_clk_init(void);
55 struct clk *clk;
56 int ret;
57
58 clk = clk_get(NULL, id);
59 if (IS_ERR(clk))
60 return PTR_ERR(clk);
61
62 ret = clk_enable(clk);
63 if (ret)
64 clk_put(clk);
65
66 return ret;
67}
68 72
69/* the exported API, in addition to clk_set_rate */ 73/* the exported API, in addition to clk_set_rate */
70/** 74/**
@@ -96,4 +100,63 @@ enum clk_sh_algo_id {
96 100
97 IP_N1, 101 IP_N1,
98}; 102};
103
104struct clk_div_mult_table {
105 unsigned int *divisors;
106 unsigned int nr_divisors;
107 unsigned int *multipliers;
108 unsigned int nr_multipliers;
109};
110
111struct cpufreq_frequency_table;
112void clk_rate_table_build(struct clk *clk,
113 struct cpufreq_frequency_table *freq_table,
114 int nr_freqs,
115 struct clk_div_mult_table *src_table,
116 unsigned long *bitmap);
117
118long clk_rate_table_round(struct clk *clk,
119 struct cpufreq_frequency_table *freq_table,
120 unsigned long rate);
121
122int clk_rate_table_find(struct clk *clk,
123 struct cpufreq_frequency_table *freq_table,
124 unsigned long rate);
125
126#define SH_CLK_MSTP32(_name, _id, _parent, _enable_reg, \
127 _enable_bit, _flags) \
128{ \
129 .name = _name, \
130 .id = _id, \
131 .parent = _parent, \
132 .enable_reg = (void __iomem *)_enable_reg, \
133 .enable_bit = _enable_bit, \
134 .flags = _flags, \
135}
136
137int sh_clk_mstp32_register(struct clk *clks, int nr);
138
139#define SH_CLK_DIV4(_name, _parent, _reg, _shift, _div_bitmap, _flags) \
140{ \
141 .name = _name, \
142 .parent = _parent, \
143 .enable_reg = (void __iomem *)_reg, \
144 .enable_bit = _shift, \
145 .arch_flags = _div_bitmap, \
146 .flags = _flags, \
147}
148
149int sh_clk_div4_register(struct clk *clks, int nr,
150 struct clk_div_mult_table *table);
151
152#define SH_CLK_DIV6(_name, _parent, _reg, _flags) \
153{ \
154 .name = _name, \
155 .parent = _parent, \
156 .enable_reg = (void __iomem *)_reg, \
157 .flags = _flags, \
158}
159
160int sh_clk_div6_register(struct clk *clks, int nr);
161
99#endif /* __ASM_SH_CLOCK_H */ 162#endif /* __ASM_SH_CLOCK_H */
diff --git a/arch/sh/include/asm/cmpxchg-llsc.h b/arch/sh/include/asm/cmpxchg-llsc.h
index 0fac3da536ca..47136661a203 100644
--- a/arch/sh/include/asm/cmpxchg-llsc.h
+++ b/arch/sh/include/asm/cmpxchg-llsc.h
@@ -55,7 +55,7 @@ __cmpxchg_u32(volatile int *m, unsigned long old, unsigned long new)
55 "mov %0, %1 \n\t" 55 "mov %0, %1 \n\t"
56 "cmp/eq %1, %3 \n\t" 56 "cmp/eq %1, %3 \n\t"
57 "bf 2f \n\t" 57 "bf 2f \n\t"
58 "mov %3, %0 \n\t" 58 "mov %4, %0 \n\t"
59 "2: \n\t" 59 "2: \n\t"
60 "movco.l %0, @%2 \n\t" 60 "movco.l %0, @%2 \n\t"
61 "bf 1b \n\t" 61 "bf 1b \n\t"
diff --git a/arch/sh/include/asm/device.h b/arch/sh/include/asm/device.h
index efd511d0803a..8688a88303ee 100644
--- a/arch/sh/include/asm/device.h
+++ b/arch/sh/include/asm/device.h
@@ -10,3 +10,5 @@ struct platform_device;
10int platform_resource_setup_memory(struct platform_device *pdev, 10int platform_resource_setup_memory(struct platform_device *pdev,
11 char *name, unsigned long memsize); 11 char *name, unsigned long memsize);
12 12
13void plat_early_device_setup(void);
14
diff --git a/arch/sh/include/asm/hd64461.h b/arch/sh/include/asm/hd64461.h
index 52b4b6238277..977355f0a483 100644
--- a/arch/sh/include/asm/hd64461.h
+++ b/arch/sh/include/asm/hd64461.h
@@ -13,18 +13,20 @@
13#define HD64461_PCC_WINDOW 0x01000000 13#define HD64461_PCC_WINDOW 0x01000000
14 14
15/* Area 6 - Slot 0 - memory and/or IO card */ 15/* Area 6 - Slot 0 - memory and/or IO card */
16#define HD64461_PCC0_BASE (CONFIG_HD64461_IOBASE + 0x8000000) 16#define HD64461_IOBASE 0xb0000000
17#define HD64461_IO_OFFSET(x) (HD64461_IOBASE + (x))
18#define HD64461_PCC0_BASE HD64461_IO_OFFSET(0x8000000)
17#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */ 19#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) /* 0xb80000000 */
18#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */ 20#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) /* 0xb90000000 */
19#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */ 21#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) /* 0xba0000000 */
20 22
21/* Area 5 - Slot 1 - memory card only */ 23/* Area 5 - Slot 1 - memory card only */
22#define HD64461_PCC1_BASE (CONFIG_HD64461_IOBASE + 0x4000000) 24#define HD64461_PCC1_BASE HD64461_IO_OFFSET(0x4000000)
23#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */ 25#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) /* 0xb4000000 */
24#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */ 26#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) /* 0xb5000000 */
25 27
26/* Standby Control Register for HD64461 */ 28/* Standby Control Register for HD64461 */
27#define HD64461_STBCR CONFIG_HD64461_IOBASE 29#define HD64461_STBCR HD64461_IO_OFFSET(0x00000000)
28#define HD64461_STBCR_CKIO_STBY 0x2000 30#define HD64461_STBCR_CKIO_STBY 0x2000
29#define HD64461_STBCR_SAFECKE_IST 0x1000 31#define HD64461_STBCR_SAFECKE_IST 0x1000
30#define HD64461_STBCR_SLCKE_IST 0x0800 32#define HD64461_STBCR_SLCKE_IST 0x0800
@@ -41,19 +43,19 @@
41#define HD64461_STBCR_SURTST 0x0001 43#define HD64461_STBCR_SURTST 0x0001
42 44
43/* System Configuration Register */ 45/* System Configuration Register */
44#define HD64461_SYSCR (CONFIG_HD64461_IOBASE + 0x02) 46#define HD64461_SYSCR HD64461_IO_OFFSET(0x02)
45 47
46/* CPU Data Bus Control Register */ 48/* CPU Data Bus Control Register */
47#define HD64461_SCPUCR (CONFIG_HD64461_IOBASE + 0x04) 49#define HD64461_SCPUCR HD64461_IO_OFFSET(0x04)
48 50
49/* Base Address Register */ 51/* Base Address Register */
50#define HD64461_LCDCBAR (CONFIG_HD64461_IOBASE + 0x1000) 52#define HD64461_LCDCBAR HD64461_IO_OFFSET(0x1000)
51 53
52/* Line increment address */ 54/* Line increment address */
53#define HD64461_LCDCLOR (CONFIG_HD64461_IOBASE + 0x1002) 55#define HD64461_LCDCLOR HD64461_IO_OFFSET(0x1002)
54 56
55/* Controls LCD controller */ 57/* Controls LCD controller */
56#define HD64461_LCDCCR (CONFIG_HD64461_IOBASE + 0x1004) 58#define HD64461_LCDCCR HD64461_IO_OFFSET(0x1004)
57 59
58/* LCCDR control bits */ 60/* LCCDR control bits */
59#define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */ 61#define HD64461_LCDCCR_STBACK 0x0400 /* Standby Back */
@@ -64,30 +66,30 @@
64#define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */ 66#define HD64461_LCDCCR_SPON 0x0010 /* Start Power On */
65 67
66/* Controls LCD (1) */ 68/* Controls LCD (1) */
67#define HD64461_LDR1 (CONFIG_HD64461_IOBASE + 0x1010) 69#define HD64461_LDR1 HD64461_IO_OFFSET(0x1010)
68#define HD64461_LDR1_DON 0x01 /* Display On */ 70#define HD64461_LDR1_DON 0x01 /* Display On */
69#define HD64461_LDR1_DINV 0x80 /* Display Invert */ 71#define HD64461_LDR1_DINV 0x80 /* Display Invert */
70 72
71/* Controls LCD (2) */ 73/* Controls LCD (2) */
72#define HD64461_LDR2 (CONFIG_HD64461_IOBASE + 0x1012) 74#define HD64461_LDR2 HD64461_IO_OFFSET(0x1012)
73#define HD64461_LDHNCR (CONFIG_HD64461_IOBASE + 0x1014) /* Number of horizontal characters */ 75#define HD64461_LDHNCR HD64461_IO_OFFSET(0x1014) /* Number of horizontal characters */
74#define HD64461_LDHNSR (CONFIG_HD64461_IOBASE + 0x1016) /* Specify output start position + width of CL1 */ 76#define HD64461_LDHNSR HD64461_IO_OFFSET(0x1016) /* Specify output start position + width of CL1 */
75#define HD64461_LDVNTR (CONFIG_HD64461_IOBASE + 0x1018) /* Specify total vertical lines */ 77#define HD64461_LDVNTR HD64461_IO_OFFSET(0x1018) /* Specify total vertical lines */
76#define HD64461_LDVNDR (CONFIG_HD64461_IOBASE + 0x101a) /* specify number of display vertical lines */ 78#define HD64461_LDVNDR HD64461_IO_OFFSET(0x101a) /* specify number of display vertical lines */
77#define HD64461_LDVSPR (CONFIG_HD64461_IOBASE + 0x101c) /* specify vertical synchronization pos and AC nr */ 79#define HD64461_LDVSPR HD64461_IO_OFFSET(0x101c) /* specify vertical synchronization pos and AC nr */
78 80
79/* Controls LCD (3) */ 81/* Controls LCD (3) */
80#define HD64461_LDR3 (CONFIG_HD64461_IOBASE + 0x101e) 82#define HD64461_LDR3 HD64461_IO_OFFSET(0x101e)
81 83
82/* Palette Registers */ 84/* Palette Registers */
83#define HD64461_CPTWAR (CONFIG_HD64461_IOBASE + 0x1030) /* Color Palette Write Address Register */ 85#define HD64461_CPTWAR HD64461_IO_OFFSET(0x1030) /* Color Palette Write Address Register */
84#define HD64461_CPTWDR (CONFIG_HD64461_IOBASE + 0x1032) /* Color Palette Write Data Register */ 86#define HD64461_CPTWDR HD64461_IO_OFFSET(0x1032) /* Color Palette Write Data Register */
85#define HD64461_CPTRAR (CONFIG_HD64461_IOBASE + 0x1034) /* Color Palette Read Address Register */ 87#define HD64461_CPTRAR HD64461_IO_OFFSET(0x1034) /* Color Palette Read Address Register */
86#define HD64461_CPTRDR (CONFIG_HD64461_IOBASE + 0x1036) /* Color Palette Read Data Register */ 88#define HD64461_CPTRDR HD64461_IO_OFFSET(0x1036) /* Color Palette Read Data Register */
87 89
88#define HD64461_GRDOR (CONFIG_HD64461_IOBASE + 0x1040) /* Display Resolution Offset Register */ 90#define HD64461_GRDOR HD64461_IO_OFFSET(0x1040) /* Display Resolution Offset Register */
89#define HD64461_GRSCR (CONFIG_HD64461_IOBASE + 0x1042) /* Solid Color Register */ 91#define HD64461_GRSCR HD64461_IO_OFFSET(0x1042) /* Solid Color Register */
90#define HD64461_GRCFGR (CONFIG_HD64461_IOBASE + 0x1044) /* Accelerator Configuration Register */ 92#define HD64461_GRCFGR HD64461_IO_OFFSET(0x1044) /* Accelerator Configuration Register */
91 93
92#define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */ 94#define HD64461_GRCFGR_ACCSTATUS 0x10 /* Accelerator Status */
93#define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */ 95#define HD64461_GRCFGR_ACCRESET 0x08 /* Accelerator Reset */
@@ -97,41 +99,41 @@
97#define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */ 99#define HD64461_GRCFGR_COLORDEPTH8 0x01 /* Sets Colordepth 8 for Accelerator */
98 100
99/* Line Drawing Registers */ 101/* Line Drawing Registers */
100#define HD64461_LNSARH (CONFIG_HD64461_IOBASE + 0x1046) /* Line Start Address Register (H) */ 102#define HD64461_LNSARH HD64461_IO_OFFSET(0x1046) /* Line Start Address Register (H) */
101#define HD64461_LNSARL (CONFIG_HD64461_IOBASE + 0x1048) /* Line Start Address Register (L) */ 103#define HD64461_LNSARL HD64461_IO_OFFSET(0x1048) /* Line Start Address Register (L) */
102#define HD64461_LNAXLR (CONFIG_HD64461_IOBASE + 0x104a) /* Axis Pixel Length Register */ 104#define HD64461_LNAXLR HD64461_IO_OFFSET(0x104a) /* Axis Pixel Length Register */
103#define HD64461_LNDGR (CONFIG_HD64461_IOBASE + 0x104c) /* Diagonal Register */ 105#define HD64461_LNDGR HD64461_IO_OFFSET(0x104c) /* Diagonal Register */
104#define HD64461_LNAXR (CONFIG_HD64461_IOBASE + 0x104e) /* Axial Register */ 106#define HD64461_LNAXR HD64461_IO_OFFSET(0x104e) /* Axial Register */
105#define HD64461_LNERTR (CONFIG_HD64461_IOBASE + 0x1050) /* Start Error Term Register */ 107#define HD64461_LNERTR HD64461_IO_OFFSET(0x1050) /* Start Error Term Register */
106#define HD64461_LNMDR (CONFIG_HD64461_IOBASE + 0x1052) /* Line Mode Register */ 108#define HD64461_LNMDR HD64461_IO_OFFSET(0x1052) /* Line Mode Register */
107 109
108/* BitBLT Registers */ 110/* BitBLT Registers */
109#define HD64461_BBTSSARH (CONFIG_HD64461_IOBASE + 0x1054) /* Source Start Address Register (H) */ 111#define HD64461_BBTSSARH HD64461_IO_OFFSET(0x1054) /* Source Start Address Register (H) */
110#define HD64461_BBTSSARL (CONFIG_HD64461_IOBASE + 0x1056) /* Source Start Address Register (L) */ 112#define HD64461_BBTSSARL HD64461_IO_OFFSET(0x1056) /* Source Start Address Register (L) */
111#define HD64461_BBTDSARH (CONFIG_HD64461_IOBASE + 0x1058) /* Destination Start Address Register (H) */ 113#define HD64461_BBTDSARH HD64461_IO_OFFSET(0x1058) /* Destination Start Address Register (H) */
112#define HD64461_BBTDSARL (CONFIG_HD64461_IOBASE + 0x105a) /* Destination Start Address Register (L) */ 114#define HD64461_BBTDSARL HD64461_IO_OFFSET(0x105a) /* Destination Start Address Register (L) */
113#define HD64461_BBTDWR (CONFIG_HD64461_IOBASE + 0x105c) /* Destination Block Width Register */ 115#define HD64461_BBTDWR HD64461_IO_OFFSET(0x105c) /* Destination Block Width Register */
114#define HD64461_BBTDHR (CONFIG_HD64461_IOBASE + 0x105e) /* Destination Block Height Register */ 116#define HD64461_BBTDHR HD64461_IO_OFFSET(0x105e) /* Destination Block Height Register */
115#define HD64461_BBTPARH (CONFIG_HD64461_IOBASE + 0x1060) /* Pattern Start Address Register (H) */ 117#define HD64461_BBTPARH HD64461_IO_OFFSET(0x1060) /* Pattern Start Address Register (H) */
116#define HD64461_BBTPARL (CONFIG_HD64461_IOBASE + 0x1062) /* Pattern Start Address Register (L) */ 118#define HD64461_BBTPARL HD64461_IO_OFFSET(0x1062) /* Pattern Start Address Register (L) */
117#define HD64461_BBTMARH (CONFIG_HD64461_IOBASE + 0x1064) /* Mask Start Address Register (H) */ 119#define HD64461_BBTMARH HD64461_IO_OFFSET(0x1064) /* Mask Start Address Register (H) */
118#define HD64461_BBTMARL (CONFIG_HD64461_IOBASE + 0x1066) /* Mask Start Address Register (L) */ 120#define HD64461_BBTMARL HD64461_IO_OFFSET(0x1066) /* Mask Start Address Register (L) */
119#define HD64461_BBTROPR (CONFIG_HD64461_IOBASE + 0x1068) /* ROP Register */ 121#define HD64461_BBTROPR HD64461_IO_OFFSET(0x1068) /* ROP Register */
120#define HD64461_BBTMDR (CONFIG_HD64461_IOBASE + 0x106a) /* BitBLT Mode Register */ 122#define HD64461_BBTMDR HD64461_IO_OFFSET(0x106a) /* BitBLT Mode Register */
121 123
122/* PC Card Controller Registers */ 124/* PC Card Controller Registers */
123/* Maps to Physical Area 6 */ 125/* Maps to Physical Area 6 */
124#define HD64461_PCC0ISR (CONFIG_HD64461_IOBASE + 0x2000) /* socket 0 interface status */ 126#define HD64461_PCC0ISR HD64461_IO_OFFSET(0x2000) /* socket 0 interface status */
125#define HD64461_PCC0GCR (CONFIG_HD64461_IOBASE + 0x2002) /* socket 0 general control */ 127#define HD64461_PCC0GCR HD64461_IO_OFFSET(0x2002) /* socket 0 general control */
126#define HD64461_PCC0CSCR (CONFIG_HD64461_IOBASE + 0x2004) /* socket 0 card status change */ 128#define HD64461_PCC0CSCR HD64461_IO_OFFSET(0x2004) /* socket 0 card status change */
127#define HD64461_PCC0CSCIER (CONFIG_HD64461_IOBASE + 0x2006) /* socket 0 card status change interrupt enable */ 129#define HD64461_PCC0CSCIER HD64461_IO_OFFSET(0x2006) /* socket 0 card status change interrupt enable */
128#define HD64461_PCC0SCR (CONFIG_HD64461_IOBASE + 0x2008) /* socket 0 software control */ 130#define HD64461_PCC0SCR HD64461_IO_OFFSET(0x2008) /* socket 0 software control */
129/* Maps to Physical Area 5 */ 131/* Maps to Physical Area 5 */
130#define HD64461_PCC1ISR (CONFIG_HD64461_IOBASE + 0x2010) /* socket 1 interface status */ 132#define HD64461_PCC1ISR HD64461_IO_OFFSET(0x2010) /* socket 1 interface status */
131#define HD64461_PCC1GCR (CONFIG_HD64461_IOBASE + 0x2012) /* socket 1 general control */ 133#define HD64461_PCC1GCR HD64461_IO_OFFSET(0x2012) /* socket 1 general control */
132#define HD64461_PCC1CSCR (CONFIG_HD64461_IOBASE + 0x2014) /* socket 1 card status change */ 134#define HD64461_PCC1CSCR HD64461_IO_OFFSET(0x2014) /* socket 1 card status change */
133#define HD64461_PCC1CSCIER (CONFIG_HD64461_IOBASE + 0x2016) /* socket 1 card status change interrupt enable */ 135#define HD64461_PCC1CSCIER HD64461_IO_OFFSET(0x2016) /* socket 1 card status change interrupt enable */
134#define HD64461_PCC1SCR (CONFIG_HD64461_IOBASE + 0x2018) /* socket 1 software control */ 136#define HD64461_PCC1SCR HD64461_IO_OFFSET(0x2018) /* socket 1 software control */
135 137
136/* PCC Interface Status Register */ 138/* PCC Interface Status Register */
137#define HD64461_PCCISR_READY 0x80 /* card ready */ 139#define HD64461_PCCISR_READY 0x80 /* card ready */
@@ -189,41 +191,41 @@
189#define HD64461_PCCSCR_SWP 0x01 /* write protect */ 191#define HD64461_PCCSCR_SWP 0x01 /* write protect */
190 192
191/* PCC0 Output Pins Control Register */ 193/* PCC0 Output Pins Control Register */
192#define HD64461_P0OCR (CONFIG_HD64461_IOBASE + 0x202a) 194#define HD64461_P0OCR HD64461_IO_OFFSET(0x202a)
193 195
194/* PCC1 Output Pins Control Register */ 196/* PCC1 Output Pins Control Register */
195#define HD64461_P1OCR (CONFIG_HD64461_IOBASE + 0x202c) 197#define HD64461_P1OCR HD64461_IO_OFFSET(0x202c)
196 198
197/* PC Card General Control Register */ 199/* PC Card General Control Register */
198#define HD64461_PGCR (CONFIG_HD64461_IOBASE + 0x202e) 200#define HD64461_PGCR HD64461_IO_OFFSET(0x202e)
199 201
200/* Port Control Registers */ 202/* Port Control Registers */
201#define HD64461_GPACR (CONFIG_HD64461_IOBASE + 0x4000) /* Port A - Handles IRDA/TIMER */ 203#define HD64461_GPACR HD64461_IO_OFFSET(0x4000) /* Port A - Handles IRDA/TIMER */
202#define HD64461_GPBCR (CONFIG_HD64461_IOBASE + 0x4002) /* Port B - Handles UART */ 204#define HD64461_GPBCR HD64461_IO_OFFSET(0x4002) /* Port B - Handles UART */
203#define HD64461_GPCCR (CONFIG_HD64461_IOBASE + 0x4004) /* Port C - Handles PCMCIA 1 */ 205#define HD64461_GPCCR HD64461_IO_OFFSET(0x4004) /* Port C - Handles PCMCIA 1 */
204#define HD64461_GPDCR (CONFIG_HD64461_IOBASE + 0x4006) /* Port D - Handles PCMCIA 1 */ 206#define HD64461_GPDCR HD64461_IO_OFFSET(0x4006) /* Port D - Handles PCMCIA 1 */
205 207
206/* Port Control Data Registers */ 208/* Port Control Data Registers */
207#define HD64461_GPADR (CONFIG_HD64461_IOBASE + 0x4010) /* A */ 209#define HD64461_GPADR HD64461_IO_OFFSET(0x4010) /* A */
208#define HD64461_GPBDR (CONFIG_HD64461_IOBASE + 0x4012) /* B */ 210#define HD64461_GPBDR HD64461_IO_OFFSET(0x4012) /* B */
209#define HD64461_GPCDR (CONFIG_HD64461_IOBASE + 0x4014) /* C */ 211#define HD64461_GPCDR HD64461_IO_OFFSET(0x4014) /* C */
210#define HD64461_GPDDR (CONFIG_HD64461_IOBASE + 0x4016) /* D */ 212#define HD64461_GPDDR HD64461_IO_OFFSET(0x4016) /* D */
211 213
212/* Interrupt Control Registers */ 214/* Interrupt Control Registers */
213#define HD64461_GPAICR (CONFIG_HD64461_IOBASE + 0x4020) /* A */ 215#define HD64461_GPAICR HD64461_IO_OFFSET(0x4020) /* A */
214#define HD64461_GPBICR (CONFIG_HD64461_IOBASE + 0x4022) /* B */ 216#define HD64461_GPBICR HD64461_IO_OFFSET(0x4022) /* B */
215#define HD64461_GPCICR (CONFIG_HD64461_IOBASE + 0x4024) /* C */ 217#define HD64461_GPCICR HD64461_IO_OFFSET(0x4024) /* C */
216#define HD64461_GPDICR (CONFIG_HD64461_IOBASE + 0x4026) /* D */ 218#define HD64461_GPDICR HD64461_IO_OFFSET(0x4026) /* D */
217 219
218/* Interrupt Status Registers */ 220/* Interrupt Status Registers */
219#define HD64461_GPAISR (CONFIG_HD64461_IOBASE + 0x4040) /* A */ 221#define HD64461_GPAISR HD64461_IO_OFFSET(0x4040) /* A */
220#define HD64461_GPBISR (CONFIG_HD64461_IOBASE + 0x4042) /* B */ 222#define HD64461_GPBISR HD64461_IO_OFFSET(0x4042) /* B */
221#define HD64461_GPCISR (CONFIG_HD64461_IOBASE + 0x4044) /* C */ 223#define HD64461_GPCISR HD64461_IO_OFFSET(0x4044) /* C */
222#define HD64461_GPDISR (CONFIG_HD64461_IOBASE + 0x4046) /* D */ 224#define HD64461_GPDISR HD64461_IO_OFFSET(0x4046) /* D */
223 225
224/* Interrupt Request Register & Interrupt Mask Register */ 226/* Interrupt Request Register & Interrupt Mask Register */
225#define HD64461_NIRR (CONFIG_HD64461_IOBASE + 0x5000) 227#define HD64461_NIRR HD64461_IO_OFFSET(0x5000)
226#define HD64461_NIMR (CONFIG_HD64461_IOBASE + 0x5002) 228#define HD64461_NIMR HD64461_IO_OFFSET(0x5002)
227 229
228#define HD64461_IRQBASE OFFCHIP_IRQ_BASE 230#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
229#define OFFCHIP_IRQ_BASE 64 231#define OFFCHIP_IRQ_BASE 64
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 0454f8d68059..25348141674b 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -123,10 +123,15 @@ static inline void __raw_reads##bwlq(volatile void __iomem *mem, \
123 123
124__BUILD_MEMORY_STRING(b, u8) 124__BUILD_MEMORY_STRING(b, u8)
125__BUILD_MEMORY_STRING(w, u16) 125__BUILD_MEMORY_STRING(w, u16)
126__BUILD_MEMORY_STRING(q, u64)
127 126
127#ifdef CONFIG_SUPERH32
128void __raw_writesl(void __iomem *addr, const void *data, int longlen); 128void __raw_writesl(void __iomem *addr, const void *data, int longlen);
129void __raw_readsl(const void __iomem *addr, void *data, int longlen); 129void __raw_readsl(const void __iomem *addr, void *data, int longlen);
130#else
131__BUILD_MEMORY_STRING(l, u32)
132#endif
133
134__BUILD_MEMORY_STRING(q, u64)
130 135
131#define writesb __raw_writesb 136#define writesb __raw_writesb
132#define writesw __raw_writesw 137#define writesw __raw_writesw
@@ -224,17 +229,6 @@ void __iomem *__ioremap(unsigned long offset, unsigned long size,
224 unsigned long flags); 229 unsigned long flags);
225void __iounmap(void __iomem *addr); 230void __iounmap(void __iomem *addr);
226 231
227/* arch/sh/mm/ioremap_64.c */
228unsigned long onchip_remap(unsigned long addr, unsigned long size,
229 const char *name);
230extern void onchip_unmap(unsigned long vaddr);
231#else
232#define __ioremap(offset, size, flags) ((void __iomem *)(offset))
233#define __iounmap(addr) do { } while (0)
234#define onchip_remap(addr, size, name) (addr)
235#define onchip_unmap(addr) do { } while (0)
236#endif /* CONFIG_MMU */
237
238static inline void __iomem * 232static inline void __iomem *
239__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags) 233__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
240{ 234{
@@ -268,6 +262,10 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
268 262
269 return __ioremap(offset, size, flags); 263 return __ioremap(offset, size, flags);
270} 264}
265#else
266#define __ioremap_mode(offset, size, flags) ((void __iomem *)(offset))
267#define __iounmap(addr) do { } while (0)
268#endif /* CONFIG_MMU */
271 269
272#define ioremap(offset, size) \ 270#define ioremap(offset, size) \
273 __ioremap_mode((offset), (size), 0) 271 __ioremap_mode((offset), (size), 0)
diff --git a/arch/sh/include/asm/irq.h b/arch/sh/include/asm/irq.h
index d319baaf4fbd..a2b8c99cc06f 100644
--- a/arch/sh/include/asm/irq.h
+++ b/arch/sh/include/asm/irq.h
@@ -8,7 +8,8 @@
8 * advised to cap this at the hard limit that they're interested in 8 * advised to cap this at the hard limit that they're interested in
9 * through the machvec. 9 * through the machvec.
10 */ 10 */
11#define NR_IRQS 256 11#define NR_IRQS 256
12#define NR_IRQS_LEGACY 8 /* Legacy external IRQ0-7 */
12 13
13/* 14/*
14 * Convert back and forth between INTEVT and IRQ values. 15 * Convert back and forth between INTEVT and IRQ values.
diff --git a/arch/sh/include/asm/kprobes.h b/arch/sh/include/asm/kprobes.h
index 613644a758e8..036c3311233c 100644
--- a/arch/sh/include/asm/kprobes.h
+++ b/arch/sh/include/asm/kprobes.h
@@ -6,7 +6,7 @@
6#include <linux/types.h> 6#include <linux/types.h>
7#include <linux/ptrace.h> 7#include <linux/ptrace.h>
8 8
9typedef u16 kprobe_opcode_t; 9typedef insn_size_t kprobe_opcode_t;
10#define BREAKPOINT_INSTRUCTION 0xc33a 10#define BREAKPOINT_INSTRUCTION 0xc33a
11 11
12#define MAX_INSN_SIZE 16 12#define MAX_INSN_SIZE 16
diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h
index 64b1c16a0f03..84dd37761f56 100644
--- a/arch/sh/include/asm/machvec.h
+++ b/arch/sh/include/asm/machvec.h
@@ -46,6 +46,9 @@ struct sh_machine_vector {
46 46
47 void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size); 47 void __iomem *(*mv_ioport_map)(unsigned long port, unsigned int size);
48 void (*mv_ioport_unmap)(void __iomem *); 48 void (*mv_ioport_unmap)(void __iomem *);
49
50 int (*mv_clk_init)(void);
51 int (*mv_mode_pins)(void);
49}; 52};
50 53
51extern struct sh_machine_vector sh_mv; 54extern struct sh_machine_vector sh_mv;
diff --git a/arch/sh/include/asm/pci.h b/arch/sh/include/asm/pci.h
index df1d383e18a5..ae0da6f48b6d 100644
--- a/arch/sh/include/asm/pci.h
+++ b/arch/sh/include/asm/pci.h
@@ -17,54 +17,29 @@
17 * external) PCI controllers. 17 * external) PCI controllers.
18 */ 18 */
19struct pci_channel { 19struct pci_channel {
20 struct pci_ops *pci_ops; 20 struct pci_channel *next;
21 struct resource *io_resource;
22 struct resource *mem_resource;
23 int first_devfn;
24 int last_devfn;
25};
26 21
27/* 22 struct pci_ops *pci_ops;
28 * Each board initializes this array and terminates it with a NULL entry. 23 struct resource *io_resource;
29 */ 24 struct resource *mem_resource;
30extern struct pci_channel board_pci_channels[];
31 25
32#define PCIBIOS_MIN_IO board_pci_channels->io_resource->start 26 unsigned long io_offset;
33#define PCIBIOS_MIN_MEM board_pci_channels->mem_resource->start 27 unsigned long mem_offset;
34 28
35/* 29 unsigned long reg_base;
36 * I/O routine helpers
37 */
38#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
39#define PCI_IO_AREA 0xFE400000
40#define PCI_IO_SIZE 0x00400000
41#elif defined(CONFIG_CPU_SH5)
42extern unsigned long PCI_IO_AREA;
43#define PCI_IO_SIZE 0x00010000
44#else
45#define PCI_IO_AREA 0xFE240000
46#define PCI_IO_SIZE 0x00040000
47#endif
48 30
49#define PCI_MEM_SIZE 0x01000000 31 unsigned long io_map_base;
32};
50 33
51#define SH4_PCIIOBR_MASK 0xFFFC0000 34extern void register_pci_controller(struct pci_channel *hose);
52#define pci_ioaddr(addr) (PCI_IO_AREA + (addr & ~SH4_PCIIOBR_MASK))
53 35
54#if defined(CONFIG_PCI) 36extern unsigned long PCIBIOS_MIN_IO, PCIBIOS_MIN_MEM;
55#define is_pci_ioaddr(port) \
56 (((port) >= PCIBIOS_MIN_IO) && \
57 ((port) < (PCIBIOS_MIN_IO + PCI_IO_SIZE)))
58#define is_pci_memaddr(port) \
59 (((port) >= PCIBIOS_MIN_MEM) && \
60 ((port) < (PCIBIOS_MIN_MEM + PCI_MEM_SIZE)))
61#else
62#define is_pci_ioaddr(port) (0)
63#define is_pci_memaddr(port) (0)
64#endif
65 37
66struct pci_dev; 38struct pci_dev;
67 39
40#define HAVE_PCI_MMAP
41extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
42 enum pci_mmap_state mmap_state, int write_combine);
68extern void pcibios_set_master(struct pci_dev *dev); 43extern void pcibios_set_master(struct pci_dev *dev);
69 44
70static inline void pcibios_penalize_isa_irq(int irq, int active) 45static inline void pcibios_penalize_isa_irq(int irq, int active)
@@ -114,31 +89,76 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
114#endif 89#endif
115 90
116#ifdef CONFIG_PCI 91#ifdef CONFIG_PCI
92/*
93 * None of the SH PCI controllers support MWI, it is always treated as a
94 * direct memory write.
95 */
96#define PCI_DISABLE_MWI
97
117static inline void pci_dma_burst_advice(struct pci_dev *pdev, 98static inline void pci_dma_burst_advice(struct pci_dev *pdev,
118 enum pci_dma_burst_strategy *strat, 99 enum pci_dma_burst_strategy *strat,
119 unsigned long *strategy_parameter) 100 unsigned long *strategy_parameter)
120{ 101{
121 *strat = PCI_DMA_BURST_INFINITY; 102 unsigned long cacheline_size;
122 *strategy_parameter = ~0UL; 103 u8 byte;
104
105 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
106
107 if (byte == 0)
108 cacheline_size = L1_CACHE_BYTES;
109 else
110 cacheline_size = byte << 2;
111
112 *strat = PCI_DMA_BURST_MULTIPLE;
113 *strategy_parameter = cacheline_size;
123} 114}
124#endif 115#endif
125 116
117#ifdef CONFIG_SUPERH32
118/*
119 * If we're on an SH7751 or SH7780 PCI controller, PCI memory is mapped
120 * at the end of the address space in a special non-translatable area.
121 */
122#define PCI_MEM_FIXED_START 0xfd000000
123#define PCI_MEM_FIXED_END (PCI_MEM_FIXED_START + 0x01000000)
124
125#define is_pci_memory_fixed_range(s, e) \
126 ((s) >= PCI_MEM_FIXED_START && (e) < PCI_MEM_FIXED_END)
127#else
128#define is_pci_memory_fixed_range(s, e) (0)
129#endif
130
126/* Board-specific fixup routines. */ 131/* Board-specific fixup routines. */
127void pcibios_fixup(void);
128int pcibios_init_platform(void);
129int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin); 132int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin);
130 133
131#ifdef CONFIG_PCI_AUTO 134extern void pcibios_resource_to_bus(struct pci_dev *dev,
132int pciauto_assign_resources(int busno, struct pci_channel *hose); 135 struct pci_bus_region *region, struct resource *res);
133#endif
134 136
135#endif /* __KERNEL__ */ 137extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
138 struct pci_bus_region *region);
136 139
137/* generic pci stuff */ 140static inline struct resource *
138#include <asm-generic/pci.h> 141pcibios_select_root(struct pci_dev *pdev, struct resource *res)
142{
143 struct resource *root = NULL;
144
145 if (res->flags & IORESOURCE_IO)
146 root = &ioport_resource;
147 if (res->flags & IORESOURCE_MEM)
148 root = &iomem_resource;
149
150 return root;
151}
152
153/* Chances are this interrupt is wired PC-style ... */
154static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
155{
156 return channel ? 15 : 14;
157}
139 158
140/* generic DMA-mapping stuff */ 159/* generic DMA-mapping stuff */
141#include <asm-generic/pci-dma-compat.h> 160#include <asm-generic/pci-dma-compat.h>
142 161
162#endif /* __KERNEL__ */
143#endif /* __ASM_SH_PCI_H */ 163#endif /* __ASM_SH_PCI_H */
144 164
diff --git a/arch/sh/include/asm/pgtable.h b/arch/sh/include/asm/pgtable.h
index b517ae08b9c0..2a011b18090b 100644
--- a/arch/sh/include/asm/pgtable.h
+++ b/arch/sh/include/asm/pgtable.h
@@ -154,6 +154,10 @@ extern void kmap_coherent_init(void);
154#define kmap_coherent_init() do { } while (0) 154#define kmap_coherent_init() do { } while (0)
155#endif 155#endif
156 156
157/* arch/sh/mm/mmap.c */
158#define HAVE_ARCH_UNMAPPED_AREA
159#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
160
157#include <asm-generic/pgtable.h> 161#include <asm-generic/pgtable.h>
158 162
159#endif /* __ASM_SH_PGTABLE_H */ 163#endif /* __ASM_SH_PGTABLE_H */
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 1fd58b421438..ff7daaf9a620 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -32,7 +32,7 @@ enum cpu_type {
32 32
33 /* SH-4A types */ 33 /* SH-4A types */
34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, 34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
35 CPU_SH7723, CPU_SHX3, 35 CPU_SH7723, CPU_SH7724, CPU_SHX3,
36 36
37 /* SH4AL-DSP types */ 37 /* SH4AL-DSP types */
38 CPU_SH7343, CPU_SH7722, CPU_SH7366, 38 CPU_SH7343, CPU_SH7722, CPU_SH7366,
@@ -94,6 +94,27 @@ extern struct pt_regs fake_swapper_regs;
94const char *get_cpu_subtype(struct sh_cpuinfo *c); 94const char *get_cpu_subtype(struct sh_cpuinfo *c);
95extern const struct seq_operations cpuinfo_op; 95extern const struct seq_operations cpuinfo_op;
96 96
97/* processor boot mode configuration */
98#define MODE_PIN0 (1 << 0)
99#define MODE_PIN1 (1 << 1)
100#define MODE_PIN2 (1 << 2)
101#define MODE_PIN3 (1 << 3)
102#define MODE_PIN4 (1 << 4)
103#define MODE_PIN5 (1 << 5)
104#define MODE_PIN6 (1 << 6)
105#define MODE_PIN7 (1 << 7)
106#define MODE_PIN8 (1 << 8)
107#define MODE_PIN9 (1 << 9)
108#define MODE_PIN10 (1 << 10)
109#define MODE_PIN11 (1 << 11)
110#define MODE_PIN12 (1 << 12)
111#define MODE_PIN13 (1 << 13)
112#define MODE_PIN14 (1 << 14)
113#define MODE_PIN15 (1 << 15)
114
115int generic_mode_pins(void);
116int test_mode_pin(int pin);
117
97#ifdef CONFIG_VSYSCALL 118#ifdef CONFIG_VSYSCALL
98int vsyscall_init(void); 119int vsyscall_init(void);
99#else 120#else
diff --git a/arch/sh/include/asm/ptrace.h b/arch/sh/include/asm/ptrace.h
index 68e20ff9aa9b..1dc12cb44a2d 100644
--- a/arch/sh/include/asm/ptrace.h
+++ b/arch/sh/include/asm/ptrace.h
@@ -102,6 +102,11 @@ struct pt_dspregs {
102#define PTRACE_GETDSPREGS 55 /* DSP registers */ 102#define PTRACE_GETDSPREGS 55 /* DSP registers */
103#define PTRACE_SETDSPREGS 56 103#define PTRACE_SETDSPREGS 56
104 104
105#define PT_TEXT_END_ADDR 240
106#define PT_TEXT_ADDR 244 /* &(struct user)->start_code */
107#define PT_DATA_ADDR 248 /* &(struct user)->start_data */
108#define PT_TEXT_LEN 252
109
105#ifdef __KERNEL__ 110#ifdef __KERNEL__
106#include <asm/addrspace.h> 111#include <asm/addrspace.h>
107 112
diff --git a/arch/sh/include/asm/rtc.h b/arch/sh/include/asm/rtc.h
index f7b010d48af7..52b0c2dba979 100644
--- a/arch/sh/include/asm/rtc.h
+++ b/arch/sh/include/asm/rtc.h
@@ -6,6 +6,17 @@ extern void (*board_time_init)(void);
6extern void (*rtc_sh_get_time)(struct timespec *); 6extern void (*rtc_sh_get_time)(struct timespec *);
7extern int (*rtc_sh_set_time)(const time_t); 7extern int (*rtc_sh_set_time)(const time_t);
8 8
9/* some dummy definitions */
10#define RTC_BATT_BAD 0x100 /* battery bad */
11#define RTC_SQWE 0x08 /* enable square-wave output */
12#define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
13#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
14#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
15
16struct rtc_time;
17unsigned int get_rtc_time(struct rtc_time *);
18int set_rtc_time(struct rtc_time *);
19
9#define RTC_CAP_4_DIGIT_YEAR (1 << 0) 20#define RTC_CAP_4_DIGIT_YEAR (1 << 0)
10 21
11struct sh_rtc_platform_info { 22struct sh_rtc_platform_info {
diff --git a/arch/sh/include/asm/spinlock.h b/arch/sh/include/asm/spinlock.h
index 60283565f89b..a28c9f0053fd 100644
--- a/arch/sh/include/asm/spinlock.h
+++ b/arch/sh/include/asm/spinlock.h
@@ -26,7 +26,7 @@
26#define __raw_spin_is_locked(x) ((x)->lock <= 0) 26#define __raw_spin_is_locked(x) ((x)->lock <= 0)
27#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) 27#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
28#define __raw_spin_unlock_wait(x) \ 28#define __raw_spin_unlock_wait(x) \
29 do { cpu_relax(); } while ((x)->lock) 29 do { while (__raw_spin_is_locked(x)) cpu_relax(); } while (0)
30 30
31/* 31/*
32 * Simple spin lock operations. There are two variants, one clears IRQ's 32 * Simple spin lock operations. There are two variants, one clears IRQ's
diff --git a/arch/sh/include/asm/swab.h b/arch/sh/include/asm/swab.h
index e69315935107..0e08fe54ad71 100644
--- a/arch/sh/include/asm/swab.h
+++ b/arch/sh/include/asm/swab.h
@@ -14,15 +14,15 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
14{ 14{
15 __asm__( 15 __asm__(
16#ifdef __SH5__ 16#ifdef __SH5__
17 "byterev %0, %0\n\t" 17 "byterev %1, %0\n\t"
18 "shari %0, 32, %0" 18 "shari %0, 32, %0"
19#else 19#else
20 "swap.b %0, %0\n\t" 20 "swap.b %1, %0\n\t"
21 "swap.w %0, %0\n\t" 21 "swap.w %0, %0\n\t"
22 "swap.b %0, %0" 22 "swap.b %0, %0"
23#endif 23#endif
24 : "=r" (x) 24 : "=r" (x)
25 : "0" (x)); 25 : "r" (x));
26 26
27 return x; 27 return x;
28} 28}
@@ -32,13 +32,13 @@ static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
32{ 32{
33 __asm__( 33 __asm__(
34#ifdef __SH5__ 34#ifdef __SH5__
35 "byterev %0, %0\n\t" 35 "byterev %1, %0\n\t"
36 "shari %0, 32, %0" 36 "shari %0, 32, %0"
37#else 37#else
38 "swap.b %0, %0" 38 "swap.b %1, %0"
39#endif 39#endif
40 : "=r" (x) 40 : "=r" (x)
41 : "0" (x)); 41 : "r" (x));
42 42
43 return x; 43 return x;
44} 44}
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h
index 240b31e1142c..6c68a51f1cc5 100644
--- a/arch/sh/include/asm/system_32.h
+++ b/arch/sh/include/asm/system_32.h
@@ -198,7 +198,7 @@ do { \
198}) 198})
199#endif 199#endif
200 200
201int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs, 201int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
202 struct mem_access *ma); 202 struct mem_access *ma);
203 203
204asmlinkage void do_address_error(struct pt_regs *regs, 204asmlinkage void do_address_error(struct pt_regs *regs,
diff --git a/arch/sh/include/asm/timer.h b/arch/sh/include/asm/timer.h
deleted file mode 100644
index 4c3b66e30af2..000000000000
--- a/arch/sh/include/asm/timer.h
+++ /dev/null
@@ -1,44 +0,0 @@
1#ifndef __ASM_SH_TIMER_H
2#define __ASM_SH_TIMER_H
3
4#include <linux/sysdev.h>
5#include <linux/clocksource.h>
6#include <cpu/timer.h>
7
8struct sys_timer_ops {
9 int (*init)(void);
10 int (*start)(void);
11 int (*stop)(void);
12#ifndef CONFIG_GENERIC_TIME
13 unsigned long (*get_offset)(void);
14#endif
15};
16
17struct sys_timer {
18 const char *name;
19
20 struct sys_device dev;
21 struct sys_timer_ops *ops;
22};
23
24#define TICK_SIZE (tick_nsec / 1000)
25
26extern struct sys_timer tmu_timer, cmt_timer, mtu2_timer;
27extern struct sys_timer *sys_timer;
28
29#ifndef CONFIG_GENERIC_TIME
30static inline unsigned long get_timer_offset(void)
31{
32 return sys_timer->ops->get_offset();
33}
34#endif
35
36/* arch/sh/kernel/timers/timer.c */
37struct sys_timer *get_sys_timer(void);
38
39/* arch/sh/kernel/time.c */
40void handle_timer_tick(void);
41
42extern struct clocksource clocksource_sh;
43
44#endif /* __ASM_SH_TIMER_H */
diff --git a/arch/sh/include/asm/types.h b/arch/sh/include/asm/types.h
index beea4e6f8dfd..b13caca62a76 100644
--- a/arch/sh/include/asm/types.h
+++ b/arch/sh/include/asm/types.h
@@ -23,9 +23,9 @@ typedef unsigned short umode_t;
23typedef u32 dma_addr_t; 23typedef u32 dma_addr_t;
24 24
25#ifdef CONFIG_SUPERH32 25#ifdef CONFIG_SUPERH32
26typedef u16 opcode_t; 26typedef u16 insn_size_t;
27#else 27#else
28typedef u32 opcode_t; 28typedef u32 insn_size_t;
29#endif 29#endif
30 30
31#endif /* __ASSEMBLY__ */ 31#endif /* __ASSEMBLY__ */
diff --git a/arch/sh/include/asm/ubc.h b/arch/sh/include/asm/ubc.h
index a7b9028bbfbb..4ca4b7717371 100644
--- a/arch/sh/include/asm/ubc.h
+++ b/arch/sh/include/asm/ubc.h
@@ -42,12 +42,23 @@
42 42
43#define BRCR_CMFA (1 << 15) 43#define BRCR_CMFA (1 << 15)
44#define BRCR_CMFB (1 << 14) 44#define BRCR_CMFB (1 << 14)
45
46#if defined CONFIG_CPU_SH2A
47#define BRCR_CMFCA (1 << 15)
48#define BRCR_CMFCB (1 << 14)
49#define BRCR_CMFDA (1 << 13)
50#define BRCR_CMFDB (1 << 12)
51#define BRCR_PCBB (1 << 6) /* 1: after execution */
52#define BRCR_PCBA (1 << 5) /* 1: after execution */
53#define BRCR_PCTE 0
54#else
45#define BRCR_PCTE (1 << 11) 55#define BRCR_PCTE (1 << 11)
46#define BRCR_PCBA (1 << 10) /* 1: after execution */ 56#define BRCR_PCBA (1 << 10) /* 1: after execution */
47#define BRCR_DBEB (1 << 7) 57#define BRCR_DBEB (1 << 7)
48#define BRCR_PCBB (1 << 6) 58#define BRCR_PCBB (1 << 6)
49#define BRCR_SEQ (1 << 3) 59#define BRCR_SEQ (1 << 3)
50#define BRCR_UBDE (1 << 0) 60#define BRCR_UBDE (1 << 0)
61#endif
51 62
52#ifndef __ASSEMBLY__ 63#ifndef __ASSEMBLY__
53/* arch/sh/kernel/cpu/ubc.S */ 64/* arch/sh/kernel/cpu/ubc.S */
diff --git a/arch/sh/include/asm/unaligned-sh4a.h b/arch/sh/include/asm/unaligned-sh4a.h
index d8f89770275b..9f4dd252c981 100644
--- a/arch/sh/include/asm/unaligned-sh4a.h
+++ b/arch/sh/include/asm/unaligned-sh4a.h
@@ -3,9 +3,9 @@
3 3
4/* 4/*
5 * SH-4A has support for unaligned 32-bit loads, and 32-bit loads only. 5 * SH-4A has support for unaligned 32-bit loads, and 32-bit loads only.
6 * Support for 16 and 64-bit accesses are done through shifting and 6 * Support for 64-bit accesses are done through shifting and masking
7 * masking relative to the endianness. Unaligned stores are not supported 7 * relative to the endianness. Unaligned stores are not supported by the
8 * by the instruction encoding, so these continue to use the packed 8 * instruction encoding, so these continue to use the packed
9 * struct. 9 * struct.
10 * 10 *
11 * The same note as with the movli.l/movco.l pair applies here, as long 11 * The same note as with the movli.l/movco.l pair applies here, as long
@@ -41,9 +41,9 @@ struct __una_u64 { u64 x __attribute__((packed)); };
41static inline u16 __get_unaligned_cpu16(const u8 *p) 41static inline u16 __get_unaligned_cpu16(const u8 *p)
42{ 42{
43#ifdef __LITTLE_ENDIAN 43#ifdef __LITTLE_ENDIAN
44 return __get_unaligned_cpu32(p) & 0xffff; 44 return p[0] | p[1] << 8;
45#else 45#else
46 return __get_unaligned_cpu32(p) >> 16; 46 return p[0] << 8 | p[1];
47#endif 47#endif
48} 48}
49 49
diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h
index 2efb819e2db3..65197086a1c5 100644
--- a/arch/sh/include/asm/unistd_32.h
+++ b/arch/sh/include/asm/unistd_32.h
@@ -343,8 +343,9 @@
343#define __NR_inotify_init1 332 343#define __NR_inotify_init1 332
344#define __NR_preadv 333 344#define __NR_preadv 333
345#define __NR_pwritev 334 345#define __NR_pwritev 334
346#define __NR_rt_tgsigqueueinfo 335
346 347
347#define NR_syscalls 335 348#define NR_syscalls 336
348 349
349#ifdef __KERNEL__ 350#ifdef __KERNEL__
350 351
diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h
index 6eb9d2934c0f..8014aea88ec3 100644
--- a/arch/sh/include/asm/unistd_64.h
+++ b/arch/sh/include/asm/unistd_64.h
@@ -383,10 +383,11 @@
383#define __NR_inotify_init1 360 383#define __NR_inotify_init1 360
384#define __NR_preadv 361 384#define __NR_preadv 361
385#define __NR_pwritev 362 385#define __NR_pwritev 362
386#define __NR_rt_tgsigqueueinfo 363
386 387
387#ifdef __KERNEL__ 388#ifdef __KERNEL__
388 389
389#define NR_syscalls 363 390#define NR_syscalls 364
390 391
391#define __ARCH_WANT_IPC_PARSE_VERSION 392#define __ARCH_WANT_IPC_PARSE_VERSION
392#define __ARCH_WANT_OLD_READDIR 393#define __ARCH_WANT_OLD_READDIR
diff --git a/arch/sh/include/cpu-sh2a/cpu/ubc.h b/arch/sh/include/cpu-sh2a/cpu/ubc.h
index 8ce2fc1cf625..1192e1c761a7 100644
--- a/arch/sh/include/cpu-sh2a/cpu/ubc.h
+++ b/arch/sh/include/cpu-sh2a/cpu/ubc.h
@@ -1 +1,28 @@
1#include <cpu-sh2/cpu/ubc.h> 1/*
2 * SH-2A UBC definitions
3 *
4 * Copyright (C) 2008 Kieran Bingham
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef __ASM_CPU_SH2A_UBC_H
12#define __ASM_CPU_SH2A_UBC_H
13
14#define UBC_BARA 0xfffc0400
15#define UBC_BAMRA 0xfffc0404
16#define UBC_BBRA 0xfffc04a0 /* 16 bit access */
17#define UBC_BDRA 0xfffc0408
18#define UBC_BDMRA 0xfffc040c
19
20#define UBC_BARB 0xfffc0410
21#define UBC_BAMRB 0xfffc0414
22#define UBC_BBRB 0xfffc04b0 /* 16 bit access */
23#define UBC_BDRB 0xfffc0418
24#define UBC_BDMRB 0xfffc041c
25
26#define UBC_BRCR 0xfffc04c0
27
28#endif /* __ASM_CPU_SH2A_UBC_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/timer.h b/arch/sh/include/cpu-sh3/cpu/timer.h
deleted file mode 100644
index 793acf12aa08..000000000000
--- a/arch/sh/include/cpu-sh3/cpu/timer.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/timer.h
3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_TIMER_H
11#define __ASM_CPU_SH3_TIMER_H
12
13/*
14 * ---------------------------------------------------------------------------
15 * TMU Common definitions for SH3 processors
16 * SH7706
17 * SH7709S
18 * SH7727
19 * SH7729R
20 * SH7710
21 * SH7720
22 * SH7710
23 * ---------------------------------------------------------------------------
24 */
25
26#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
27#define TMU_TOCR 0xfffffe90 /* Byte access */
28#endif
29
30#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7721)
33#define TMU_012_TSTR 0xa412fe92 /* Byte access */
34
35#define TMU0_TCOR 0xa412fe94 /* Long access */
36#define TMU0_TCNT 0xa412fe98 /* Long access */
37#define TMU0_TCR 0xa412fe9c /* Word access */
38
39#define TMU1_TCOR 0xa412fea0 /* Long access */
40#define TMU1_TCNT 0xa412fea4 /* Long access */
41#define TMU1_TCR 0xa412fea8 /* Word access */
42
43#define TMU2_TCOR 0xa412feac /* Long access */
44#define TMU2_TCNT 0xa412feb0 /* Long access */
45#define TMU2_TCR 0xa412feb4 /* Word access */
46
47#else
48#define TMU_012_TSTR 0xfffffe92 /* Byte access */
49
50#define TMU0_TCOR 0xfffffe94 /* Long access */
51#define TMU0_TCNT 0xfffffe98 /* Long access */
52#define TMU0_TCR 0xfffffe9c /* Word access */
53
54#define TMU1_TCOR 0xfffffea0 /* Long access */
55#define TMU1_TCNT 0xfffffea4 /* Long access */
56#define TMU1_TCR 0xfffffea8 /* Word access */
57
58#define TMU2_TCOR 0xfffffeac /* Long access */
59#define TMU2_TCNT 0xfffffeb0 /* Long access */
60#define TMU2_TCR 0xfffffeb4 /* Word access */
61#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
62#define TMU2_TCPR2 0xfffffeb8 /* Long access */
63#endif
64#endif
65
66#endif /* __ASM_CPU_SH3_TIMER_H */
67
diff --git a/arch/sh/include/cpu-sh4/cpu/cache.h b/arch/sh/include/cpu-sh4/cpu/cache.h
index 1c61ebf5c8e3..7bfb9e8b069c 100644
--- a/arch/sh/include/cpu-sh4/cpu/cache.h
+++ b/arch/sh/include/cpu-sh4/cpu/cache.h
@@ -38,5 +38,7 @@
38#define CACHE_IC_ADDRESS_ARRAY 0xf0000000 38#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
39#define CACHE_OC_ADDRESS_ARRAY 0xf4000000 39#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
40 40
41#define RAMCR 0xFF000074
42
41#endif /* __ASM_CPU_SH4_CACHE_H */ 43#endif /* __ASM_CPU_SH4_CACHE_H */
42 44
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index 749d1c434337..ccf1d999db6d 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -25,6 +25,24 @@
25#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 25#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
26 defined(CONFIG_CPU_SUBTYPE_SH7780) 26 defined(CONFIG_CPU_SUBTYPE_SH7780)
27#define FRQCR 0xffc80000 27#define FRQCR 0xffc80000
28#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
29#define FRQCRA 0xa4150000
30#define FRQCRB 0xa4150004
31#define VCLKCR 0xa4150048
32
33#define FCLKACR 0xa4150008
34#define FCLKBCR 0xa415000c
35#define FRQCR FRQCRA
36#define SCLKACR FCLKACR
37#define SCLKBCR FCLKBCR
38#define FCLKACR 0xa4150008
39#define FCLKBCR 0xa415000c
40#define IrDACLKCR 0xa4150018
41
42#define MSTPCR0 0xa4150030
43#define MSTPCR1 0xa4150034
44#define MSTPCR2 0xa4150038
45
28#elif defined(CONFIG_CPU_SUBTYPE_SH7785) 46#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
29#define FRQCR0 0xffc80000 47#define FRQCR0 0xffc80000
30#define FRQCR1 0xffc80004 48#define FRQCR1 0xffc80004
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7722.h b/arch/sh/include/cpu-sh4/cpu/sh7722.h
index 4b3096f5307b..738ea43c5038 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7722.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7722.h
@@ -1,6 +1,20 @@
1#ifndef __ASM_SH7722_H__ 1#ifndef __ASM_SH7722_H__
2#define __ASM_SH7722_H__ 2#define __ASM_SH7722_H__
3 3
4/* Boot Mode Pins:
5 *
6 * MD0: CPG - Clock Mode 0->3
7 * MD1: CPG - Clock Mode 0->3
8 * MD2: CPG - Reserved (L: Normal operation)
9 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
10 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
11 * MD8: Test Mode
12 */
13
14/* Pin Function Controller:
15 * GPIO_FN_xx - GPIO used to select pin function
16 * GPIO_Pxx - GPIO mapped to real I/O pin on CPU
17 */
4enum { 18enum {
5 /* PTA */ 19 /* PTA */
6 GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4, 20 GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7723.h b/arch/sh/include/cpu-sh4/cpu/sh7723.h
index 9d2f6d7aa938..14c8ca936781 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7723.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7723.h
@@ -1,6 +1,20 @@
1#ifndef __ASM_SH7723_H__ 1#ifndef __ASM_SH7723_H__
2#define __ASM_SH7723_H__ 2#define __ASM_SH7723_H__
3 3
4/* Boot Mode Pins:
5 *
6 * MD0: CPG - Clock Mode 0->3
7 * MD1: CPG - Clock Mode 0->3
8 * MD2: CPG - Reserved (L: Normal operation)
9 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
10 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
11 * MD8: Test Mode
12 */
13
14/* Pin Function Controller:
15 * GPIO_FN_xx - GPIO used to select pin function
16 * GPIO_Pxx - GPIO mapped to real I/O pin on CPU
17 */
4enum { 18enum {
5 /* PTA */ 19 /* PTA */
6 GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4, 20 GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7724.h b/arch/sh/include/cpu-sh4/cpu/sh7724.h
new file mode 100644
index 000000000000..66fd1184359e
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7724.h
@@ -0,0 +1,269 @@
1#ifndef __ASM_SH7724_H__
2#define __ASM_SH7724_H__
3
4/* Boot Mode Pins:
5 *
6 * MD0: CPG - Clock Mode 0->7
7 * MD1: CPG - Clock Mode 0->7
8 * MD2: CPG - Clock Mode 0->7
9 * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10]
10 * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3]
11 * MD8: Test Mode
12 */
13
14/* Pin Function Controller:
15 * GPIO_FN_xx - GPIO used to select pin function
16 * GPIO_Pxx - GPIO mapped to real I/O pin on CPU
17 */
18enum {
19 /* PTA */
20 GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
21 GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
22
23 /* PTB */
24 GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
25 GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
26
27 /* PTC */
28 GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4,
29 GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0,
30
31 /* PTD */
32 GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
33 GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
34
35 /* PTE */
36 GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4,
37 GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0,
38
39 /* PTF */
40 GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4,
41 GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0,
42
43 /* PTG */
44 GPIO_PTG5, GPIO_PTG4,
45 GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0,
46
47 /* PTH */
48 GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4,
49 GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
50
51 /* PTJ */
52 GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5,
53 GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0,
54
55 /* PTK */
56 GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4,
57 GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
58
59 /* PTL */
60 GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4,
61 GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0,
62
63 /* PTM */
64 GPIO_PTM7, GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
65 GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
66
67 /* PTN */
68 GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4,
69 GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,
70
71 /* PTQ */
72 GPIO_PTQ7, GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,
73 GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,
74
75 /* PTR */
76 GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4,
77 GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
78
79 /* PTS */
80 GPIO_PTS6, GPIO_PTS5, GPIO_PTS4,
81 GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
82
83 /* PTT */
84 GPIO_PTT7, GPIO_PTT6, GPIO_PTT5, GPIO_PTT4,
85 GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0,
86
87 /* PTU */
88 GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4,
89 GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0,
90
91 /* PTV */
92 GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4,
93 GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
94
95 /* PTW */
96 GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4,
97 GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0,
98
99 /* PTX */
100 GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4,
101 GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0,
102
103 /* PTY */
104 GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4,
105 GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0,
106
107 /* PTZ */
108 GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4,
109 GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0,
110
111 /* BSC (PTA/PTB/PTJ/PTQ/PTR/PTT) */
112 GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28,
113 GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24,
114 GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20,
115 GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16,
116 GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
117 GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
118 GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
119 GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
120 GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22,
121 GPIO_FN_CS6B_CE1B, GPIO_FN_CS6A_CE2B,
122 GPIO_FN_CS5B_CE1A, GPIO_FN_CS5A_CE2A,
123 GPIO_FN_WE3_ICIOWR, GPIO_FN_WE2_ICIORD,
124 GPIO_FN_IOIS16, GPIO_FN_WAIT,
125 GPIO_FN_BS,
126
127 /* KEYSC (PTA/PTB)*/
128 GPIO_FN_KEYOUT5_IN5, GPIO_FN_KEYOUT4_IN6, GPIO_FN_KEYIN4,
129 GPIO_FN_KEYIN3, GPIO_FN_KEYIN2, GPIO_FN_KEYIN1, GPIO_FN_KEYIN0,
130 GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT2, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT0,
131
132 /* ATAPI (PTA/PTB/PTK/PTR/PTS/PTW) */
133 GPIO_FN_IDED15, GPIO_FN_IDED14, GPIO_FN_IDED13, GPIO_FN_IDED12,
134 GPIO_FN_IDED11, GPIO_FN_IDED10, GPIO_FN_IDED9, GPIO_FN_IDED8,
135 GPIO_FN_IDED7, GPIO_FN_IDED6, GPIO_FN_IDED5, GPIO_FN_IDED4,
136 GPIO_FN_IDED3, GPIO_FN_IDED2, GPIO_FN_IDED1, GPIO_FN_IDED0,
137 GPIO_FN_IDEA2, GPIO_FN_IDEA1, GPIO_FN_IDEA0, GPIO_FN_IDEIOWR,
138 GPIO_FN_IODREQ, GPIO_FN_IDECS0, GPIO_FN_IDECS1, GPIO_FN_IDEIORD,
139 GPIO_FN_DIRECTION, GPIO_FN_EXBUF_ENB, GPIO_FN_IDERST, GPIO_FN_IODACK,
140 GPIO_FN_IDEINT, GPIO_FN_IDEIORDY,
141
142 /* TPU (PTB/PTR/PTS) */
143 GPIO_FN_TPUTO3, GPIO_FN_TPUTO2, GPIO_FN_TPUTO1, GPIO_FN_TPUTO0,
144 GPIO_FN_TPUTI3, GPIO_FN_TPUTI2,
145
146 /* LCDC (PTC/PTD/PTE/PTF/PTM/PTR) */
147 GPIO_FN_LCDD23, GPIO_FN_LCDD22, GPIO_FN_LCDD21, GPIO_FN_LCDD20,
148 GPIO_FN_LCDD19, GPIO_FN_LCDD18, GPIO_FN_LCDD17, GPIO_FN_LCDD16,
149 GPIO_FN_LCDD15, GPIO_FN_LCDD14, GPIO_FN_LCDD13, GPIO_FN_LCDD12,
150 GPIO_FN_LCDD11, GPIO_FN_LCDD10, GPIO_FN_LCDD9, GPIO_FN_LCDD8,
151 GPIO_FN_LCDD7, GPIO_FN_LCDD6, GPIO_FN_LCDD5, GPIO_FN_LCDD4,
152 GPIO_FN_LCDD3, GPIO_FN_LCDD2, GPIO_FN_LCDD1, GPIO_FN_LCDD0,
153 GPIO_FN_LCDVSYN, GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_LCDHSYN,
154 GPIO_FN_LCDCS, GPIO_FN_LCDDON, GPIO_FN_LCDDCK, GPIO_FN_LCDWR,
155 GPIO_FN_LCDVEPWC, GPIO_FN_LCDVCPWC, GPIO_FN_LCDRD, GPIO_FN_LCDLCLK,
156
157 /* SCIF0 (PTF/PTM) */
158 GPIO_FN_SCIF0_TXD, GPIO_FN_SCIF0_RXD, GPIO_FN_SCIF0_SCK,
159
160 /* SCIF1 (PTL) */
161 GPIO_FN_SCIF1_SCK, GPIO_FN_SCIF1_RXD, GPIO_FN_SCIF1_TXD,
162
163 /* SCIF2 (PTE/PTF/PTN) with LCDC, VOU */
164 GPIO_FN_SCIF2_L_TXD, GPIO_FN_SCIF2_L_SCK, GPIO_FN_SCIF2_L_RXD,
165 GPIO_FN_SCIF2_V_TXD, GPIO_FN_SCIF2_V_SCK, GPIO_FN_SCIF2_V_RXD,
166
167 /* SCIF3 (PTL/PTN/PTZ) with VOU, IRQ */
168 GPIO_FN_SCIF3_V_SCK, GPIO_FN_SCIF3_V_RXD, GPIO_FN_SCIF3_V_TXD,
169 GPIO_FN_SCIF3_V_CTS, GPIO_FN_SCIF3_V_RTS,
170 GPIO_FN_SCIF3_I_SCK, GPIO_FN_SCIF3_I_RXD, GPIO_FN_SCIF3_I_TXD,
171 GPIO_FN_SCIF3_I_CTS, GPIO_FN_SCIF3_I_RTS,
172
173 /* SCIF4 (PTE) */
174 GPIO_FN_SCIF4_SCK, GPIO_FN_SCIF4_RXD, GPIO_FN_SCIF4_TXD,
175
176 /* SCIF5 (PTS) */
177 GPIO_FN_SCIF5_SCK, GPIO_FN_SCIF5_RXD, GPIO_FN_SCIF5_TXD,
178
179 /* FSI (PTE/PTU/PTV) */
180 GPIO_FN_FSIMCKB, GPIO_FN_FSIMCKA, GPIO_FN_FSIOASD,
181 GPIO_FN_FSIIABCK, GPIO_FN_FSIIALRCK, GPIO_FN_FSIOABCK,
182 GPIO_FN_FSIOALRCK, GPIO_FN_CLKAUDIOAO, GPIO_FN_FSIIBSD,
183 GPIO_FN_FSIOBSD, GPIO_FN_FSIIBBCK, GPIO_FN_FSIIBLRCK,
184 GPIO_FN_FSIOBBCK, GPIO_FN_FSIOBLRCK, GPIO_FN_CLKAUDIOBO,
185 GPIO_FN_FSIIASD,
186
187 /* AUD (PTG) */
188 GPIO_FN_AUDCK, GPIO_FN_AUDSYNC, GPIO_FN_AUDATA3,
189 GPIO_FN_AUDATA2, GPIO_FN_AUDATA1, GPIO_FN_AUDATA0,
190
191 /* VIO (PTS) (common?) */
192 GPIO_FN_VIO_CKO,
193
194 /* VIO0 (PTH/PTK) */
195 GPIO_FN_VIO0_D15, GPIO_FN_VIO0_D14, GPIO_FN_VIO0_D13, GPIO_FN_VIO0_D12,
196 GPIO_FN_VIO0_D11, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D8,
197 GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D5, GPIO_FN_VIO0_D4,
198 GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D2, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D0,
199 GPIO_FN_VIO0_VD, GPIO_FN_VIO0_CLK,
200 GPIO_FN_VIO0_FLD, GPIO_FN_VIO0_HD,
201
202 /* VIO1 (PTK/PTS) */
203 GPIO_FN_VIO1_D7, GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D5, GPIO_FN_VIO1_D4,
204 GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D2, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D0,
205 GPIO_FN_VIO1_FLD, GPIO_FN_VIO1_HD, GPIO_FN_VIO1_VD, GPIO_FN_VIO1_CLK,
206
207 /* Eth (PTL/PTN/PTX) */
208 GPIO_FN_RMII_RXD0, GPIO_FN_RMII_RXD1,
209 GPIO_FN_RMII_TXD0, GPIO_FN_RMII_TXD1,
210 GPIO_FN_RMII_REF_CLK, GPIO_FN_RMII_TX_EN,
211 GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_CRS_DV,
212 GPIO_FN_LNKSTA, GPIO_FN_MDIO,
213 GPIO_FN_MDC,
214
215 /* System (PTJ) */
216 GPIO_FN_PDSTATUS, GPIO_FN_STATUS2, GPIO_FN_STATUS0,
217
218 /* VOU (PTL/PTM/PTN*/
219 GPIO_FN_DV_D15, GPIO_FN_DV_D14, GPIO_FN_DV_D13, GPIO_FN_DV_D12,
220 GPIO_FN_DV_D11, GPIO_FN_DV_D10, GPIO_FN_DV_D9, GPIO_FN_DV_D8,
221 GPIO_FN_DV_D7, GPIO_FN_DV_D6, GPIO_FN_DV_D5, GPIO_FN_DV_D4,
222 GPIO_FN_DV_D3, GPIO_FN_DV_D2, GPIO_FN_DV_D1, GPIO_FN_DV_D0,
223 GPIO_FN_DV_CLKI, GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC,
224
225 /* MSIOF0 (PTL/PTM) */
226 GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
227 GPIO_FN_MSIOF0_MCK, GPIO_FN_MSIOF0_TSCK,
228 GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
229 GPIO_FN_MSIOF0_TSYNC, GPIO_FN_MSIOF0_RSCK,
230 GPIO_FN_MSIOF0_RSYNC,
231
232 /* MSIOF1 (PTV) */
233 GPIO_FN_MSIOF1_RXD, GPIO_FN_MSIOF1_TXD,
234 GPIO_FN_MSIOF1_MCK, GPIO_FN_MSIOF1_TSCK,
235 GPIO_FN_MSIOF1_SS1, GPIO_FN_MSIOF1_SS2,
236 GPIO_FN_MSIOF1_TSYNC, GPIO_FN_MSIOF1_RSCK,
237 GPIO_FN_MSIOF1_RSYNC,
238
239 /* DMAC (PTU/PTX) */
240 GPIO_FN_DMAC_DACK0, GPIO_FN_DMAC_DREQ0,
241 GPIO_FN_DMAC_DACK1, GPIO_FN_DMAC_DREQ1,
242
243 /* SDHI0 (PTY) */
244 GPIO_FN_SDHI0CD, GPIO_FN_SDHI0WP, GPIO_FN_SDHI0CMD, GPIO_FN_SDHI0CLK,
245 GPIO_FN_SDHI0D3, GPIO_FN_SDHI0D2, GPIO_FN_SDHI0D1, GPIO_FN_SDHI0D0,
246
247 /* SDHI1 (PTW) */
248 GPIO_FN_SDHI1CD, GPIO_FN_SDHI1WP, GPIO_FN_SDHI1CMD, GPIO_FN_SDHI1CLK,
249 GPIO_FN_SDHI1D3, GPIO_FN_SDHI1D2, GPIO_FN_SDHI1D1, GPIO_FN_SDHI1D0,
250
251 /* MMC (PTW/PTX)*/
252 GPIO_FN_MMC_D7, GPIO_FN_MMC_D6, GPIO_FN_MMC_D5, GPIO_FN_MMC_D4,
253 GPIO_FN_MMC_D3, GPIO_FN_MMC_D2, GPIO_FN_MMC_D1, GPIO_FN_MMC_D0,
254 GPIO_FN_MMC_CLK, GPIO_FN_MMC_CMD,
255
256 /* IrDA (PTX) */
257 GPIO_FN_IRDA_OUT, GPIO_FN_IRDA_IN,
258
259 /* TSIF (PTX) */
260 GPIO_FN_TSIF_TS0_SDAT, GPIO_FN_TSIF_TS0_SCK,
261 GPIO_FN_TSIF_TS0_SDEN, GPIO_FN_TSIF_TS0_SPSYNC,
262
263 /* IRQ (PTZ) */
264 GPIO_FN_INTC_IRQ7, GPIO_FN_INTC_IRQ6, GPIO_FN_INTC_IRQ5,
265 GPIO_FN_INTC_IRQ4, GPIO_FN_INTC_IRQ3, GPIO_FN_INTC_IRQ2,
266 GPIO_FN_INTC_IRQ1, GPIO_FN_INTC_IRQ0,
267};
268
269#endif /* __ASM_SH7724_H__ */
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7785.h b/arch/sh/include/cpu-sh4/cpu/sh7785.h
index e4006afb735e..9dc9d91e0a8e 100644
--- a/arch/sh/include/cpu-sh4/cpu/sh7785.h
+++ b/arch/sh/include/cpu-sh4/cpu/sh7785.h
@@ -1,6 +1,31 @@
1#ifndef __ASM_SH7785_H__ 1#ifndef __ASM_SH7785_H__
2#define __ASM_SH7785_H__ 2#define __ASM_SH7785_H__
3 3
4/* Boot Mode Pins:
5 *
6 * MODE0: CPG - Initial Pck/Bck Frequency [FRQMR1]
7 * MODE1: CPG - Initial Uck/SHck/DDRck Frequency [FRQMR1]
8 * MODE2: CPG - Reserved (L: Normal operation)
9 * MODE3: CPG - Reserved (L: Normal operation)
10 * MODE4: CPG - Initial PLL setting (72x/36x)
11 * MODE5: LBSC - Area0 Memory Type / Bus Width [CS0BCR.8]
12 * MODE6: LBSC - Area0 Memory Type / Bus Width [CS0BCR.9]
13 * MODE7: LBSC - Area0 Memory Type / Bus Width [CS0BCR.3]
14 * MODE8: LBSC - Endian Mode (L: Big, H: Little) [BCR.31]
15 * MODE9: LBSC - Master/Slave Mode (L: Slave) [BCR.30]
16 * MODE10: CPG - Clock Input (L: Ext Clk, H: Crystal)
17 * MODE11: PCI - Pin Mode (LL: PCI host, LH: PCI slave)
18 * MODE12: PCI - Pin Mode (HL: Local bus, HH: DU)
19 * MODE13: Boot Address Mode (L: 29-bit, H: 32-bit)
20 * MODE14: Reserved (H: Normal operation)
21 *
22 * More information in sh7785 manual Rev.1.00, page 1628.
23 */
24
25/* Pin Function Controller:
26 * GPIO_FN_xx - GPIO used to select pin function
27 * GPIO_Pxx - GPIO mapped to real I/O pin on CPU
28 */
4enum { 29enum {
5 /* PA */ 30 /* PA */
6 GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4, 31 GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
diff --git a/arch/sh/include/cpu-sh4/cpu/timer.h b/arch/sh/include/cpu-sh4/cpu/timer.h
deleted file mode 100644
index d1e796b96888..000000000000
--- a/arch/sh/include/cpu-sh4/cpu/timer.h
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh4/timer.h
3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH4_TIMER_H
11#define __ASM_CPU_SH4_TIMER_H
12
13/*
14 * ---------------------------------------------------------------------------
15 * TMU Common definitions for SH4 processors
16 * SH7750S/SH7750R
17 * SH7751/SH7751R
18 * SH7760
19 * SH-X3
20 * ---------------------------------------------------------------------------
21 */
22#ifdef CONFIG_CPU_SUBTYPE_SHX3
23#define TMU_012_BASE 0xffc10000
24#define TMU_345_BASE 0xffc20000
25#else
26#define TMU_012_BASE 0xffd80000
27#define TMU_345_BASE 0xfe100000
28#endif
29
30#define TMU_TOCR TMU_012_BASE /* Not supported on all CPUs */
31
32#define TMU_012_TSTR (TMU_012_BASE + 0x04)
33#define TMU_345_TSTR (TMU_345_BASE + 0x04)
34
35#define TMU0_TCOR (TMU_012_BASE + 0x08)
36#define TMU0_TCNT (TMU_012_BASE + 0x0c)
37#define TMU0_TCR (TMU_012_BASE + 0x10)
38
39#define TMU1_TCOR (TMU_012_BASE + 0x14)
40#define TMU1_TCNT (TMU_012_BASE + 0x18)
41#define TMU1_TCR (TMU_012_BASE + 0x1c)
42
43#define TMU2_TCOR (TMU_012_BASE + 0x20)
44#define TMU2_TCNT (TMU_012_BASE + 0x24)
45#define TMU2_TCR (TMU_012_BASE + 0x28)
46#define TMU2_TCPR (TMU_012_BASE + 0x2c)
47
48#define TMU3_TCOR (TMU_345_BASE + 0x08)
49#define TMU3_TCNT (TMU_345_BASE + 0x0c)
50#define TMU3_TCR (TMU_345_BASE + 0x10)
51
52#define TMU4_TCOR (TMU_345_BASE + 0x14)
53#define TMU4_TCNT (TMU_345_BASE + 0x18)
54#define TMU4_TCR (TMU_345_BASE + 0x1c)
55
56#define TMU5_TCOR (TMU_345_BASE + 0x20)
57#define TMU5_TCNT (TMU_345_BASE + 0x24)
58#define TMU5_TCR (TMU_345_BASE + 0x28)
59
60#endif /* __ASM_CPU_SH4_TIMER_H */
diff --git a/arch/sh/include/cpu-sh5/cpu/irq.h b/arch/sh/include/cpu-sh5/cpu/irq.h
index f0f0756e6e84..0ccf257a72d1 100644
--- a/arch/sh/include/cpu-sh5/cpu/irq.h
+++ b/arch/sh/include/cpu-sh5/cpu/irq.h
@@ -111,7 +111,6 @@
111#define TOP_PRIORITY 15 111#define TOP_PRIORITY 15
112 112
113extern int intc_evt_to_irq[(0xE20/0x20)+1]; 113extern int intc_evt_to_irq[(0xE20/0x20)+1];
114int intc_irq_describe(char* p, int irq);
115extern int platform_int_priority[NR_INTC_IRQS]; 114extern int platform_int_priority[NR_INTC_IRQS];
116 115
117#endif /* __ASM_SH_CPU_SH5_IRQ_H */ 116#endif /* __ASM_SH_CPU_SH5_IRQ_H */
diff --git a/arch/sh/include/mach-common/mach/sh7785lcr.h b/arch/sh/include/mach-common/mach/sh7785lcr.h
index 1ce27d5c7491..90011d435f30 100644
--- a/arch/sh/include/mach-common/mach/sh7785lcr.h
+++ b/arch/sh/include/mach-common/mach/sh7785lcr.h
@@ -9,11 +9,11 @@
9 * -----------------------------+---------------+--------------- 9 * -----------------------------+---------------+---------------
10 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash 10 * 0x00000000 - 0x03ffffff(CS0) | NOR Flash | NOR Flash
11 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD 11 * 0x04000000 - 0x05ffffff(CS1) | PLD | PLD
12 * 0x06000000 - 0x07ffffff(CS1) | reserved | I2C 12 * 0x06000000 - 0x07ffffff(CS1) | I2C | I2C
13 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM 13 * 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
14 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM 14 * 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
15 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107 15 * 0x10000000 - 0x13ffffff(CS4) | SM107 | SM107
16 * 0x14000000 - 0x17ffffff(CS5) | I2C | USB 16 * 0x14000000 - 0x17ffffff(CS5) | reserved | USB
17 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD 17 * 0x18000000 - 0x1bffffff(CS6) | reserved | SD
18 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use) 18 * 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
19 * 19 *
@@ -32,6 +32,9 @@
32#define PLD_VERSR (PLD_BASE_ADDR + 0x0c) 32#define PLD_VERSR (PLD_BASE_ADDR + 0x0c)
33#define PLD_MMSR (PLD_BASE_ADDR + 0x0e) 33#define PLD_MMSR (PLD_BASE_ADDR + 0x0e)
34 34
35#define PCA9564_ADDR 0x06000000 /* I2C */
36#define PCA9564_SIZE 0x00000100
37
35#define SM107_MEM_ADDR 0x10000000 38#define SM107_MEM_ADDR 0x10000000
36#define SM107_MEM_SIZE 0x00e00000 39#define SM107_MEM_SIZE 0x00e00000
37#define SM107_REG_ADDR 0x13e00000 40#define SM107_REG_ADDR 0x13e00000
@@ -40,16 +43,13 @@
40#if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS) 43#if defined(CONFIG_SH_SH7785LCR_29BIT_PHYSMAPS)
41#define R8A66597_ADDR 0x14000000 /* USB */ 44#define R8A66597_ADDR 0x14000000 /* USB */
42#define CG200_ADDR 0x18000000 /* SD */ 45#define CG200_ADDR 0x18000000 /* SD */
43#define PCA9564_ADDR 0x06000000 /* I2C */
44#else 46#else
45#define R8A66597_ADDR 0x08000000 47#define R8A66597_ADDR 0x08000000
46#define CG200_ADDR 0x0c000000 48#define CG200_ADDR 0x0c000000
47#define PCA9564_ADDR 0x14000000
48#endif 49#endif
49 50
50#define R8A66597_SIZE 0x00000100 51#define R8A66597_SIZE 0x00000100
51#define CG200_SIZE 0x00010000 52#define CG200_SIZE 0x00010000
52#define PCA9564_SIZE 0x00000100
53 53
54#endif /* __ASM_SH_RENESAS_SH7785LCR_H */ 54#endif /* __ASM_SH_RENESAS_SH7785LCR_H */
55 55
diff --git a/arch/sh/include/mach-dreamcast/mach/pci.h b/arch/sh/include/mach-dreamcast/mach/pci.h
index 75fc9009e092..0314d975e626 100644
--- a/arch/sh/include/mach-dreamcast/mach/pci.h
+++ b/arch/sh/include/mach-dreamcast/mach/pci.h
@@ -21,5 +21,7 @@
21 21
22#define GAPSPCI_IRQ HW_EVENT_EXTERNAL 22#define GAPSPCI_IRQ HW_EVENT_EXTERNAL
23 23
24extern struct pci_ops gapspci_pci_ops;
25
24#endif /* __ASM_SH_DREAMCAST_PCI_H */ 26#endif /* __ASM_SH_DREAMCAST_PCI_H */
25 27
diff --git a/arch/sh/include/mach-se/mach/se7724.h b/arch/sh/include/mach-se/mach/se7724.h
new file mode 100644
index 000000000000..74164b60d0db
--- /dev/null
+++ b/arch/sh/include/mach-se/mach/se7724.h
@@ -0,0 +1,67 @@
1#ifndef __ASM_SH_SE7724_H
2#define __ASM_SH_SE7724_H
3
4/*
5 * linux/include/asm-sh/se7724.h
6 *
7 * Copyright (C) 2009 Renesas Solutions Corp.
8 *
9 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
10 *
11 * Hitachi UL SolutionEngine 7724 Support.
12 *
13 * Based on se7722.h
14 * Copyright (C) 2007 Nobuhiro Iwamatsu
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 *
20 */
21#include <asm/addrspace.h>
22
23#define PA_LED (0xba203000) /* 8bit LED */
24#define IRQ_MODE (0xba200010)
25#define IRQ0_SR (0xba200014)
26#define IRQ1_SR (0xba200018)
27#define IRQ2_SR (0xba20001c)
28#define IRQ0_MR (0xba200020)
29#define IRQ1_MR (0xba200024)
30#define IRQ2_MR (0xba200028)
31
32/* IRQ */
33#define IRQ0_IRQ 32
34#define IRQ1_IRQ 33
35#define IRQ2_IRQ 34
36
37/* Bits in IRQ012 registers */
38#define SE7724_FPGA_IRQ_BASE 220
39
40/* IRQ0 */
41#define IRQ0_BASE SE7724_FPGA_IRQ_BASE
42#define IRQ0_KEY (IRQ0_BASE + 12)
43#define IRQ0_RMII (IRQ0_BASE + 13)
44#define IRQ0_SMC (IRQ0_BASE + 14)
45#define IRQ0_MASK 0x7fff
46#define IRQ0_END IRQ0_SMC
47/* IRQ1 */
48#define IRQ1_BASE (IRQ0_END + 1)
49#define IRQ1_TS (IRQ1_BASE + 0)
50#define IRQ1_MASK 0x0001
51#define IRQ1_END IRQ1_TS
52/* IRQ2 */
53#define IRQ2_BASE (IRQ1_END + 1)
54#define IRQ2_USB0 (IRQ1_BASE + 0)
55#define IRQ2_USB1 (IRQ1_BASE + 1)
56#define IRQ2_MASK 0x0003
57#define IRQ2_END IRQ2_USB1
58
59#define SE7724_FPGA_IRQ_NR (IRQ2_END - IRQ0_BASE)
60
61/* arch/sh/boards/se/7724/irq.c */
62void init_se7724_IRQ(void);
63
64#define __IO_PREFIX se7724
65#include <asm/io_generic.h>
66
67#endif /* __ASM_SH_SE7724_H */
diff --git a/arch/sh/kernel/Makefile_32 b/arch/sh/kernel/Makefile_32
index 82a3a150c00d..9411e3e31e68 100644
--- a/arch/sh/kernel/Makefile_32
+++ b/arch/sh/kernel/Makefile_32
@@ -11,10 +11,10 @@ endif
11 11
12obj-y := debugtraps.o idle.o io.o io_generic.o irq.o \ 12obj-y := debugtraps.o idle.o io.o io_generic.o irq.o \
13 machvec.o process_32.o ptrace_32.o setup.o signal_32.o \ 13 machvec.o process_32.o ptrace_32.o setup.o signal_32.o \
14 sys_sh.o sys_sh32.o syscalls_32.o time_32.o topology.o \ 14 sys_sh.o sys_sh32.o syscalls_32.o time.o topology.o \
15 traps.o traps_32.o 15 traps.o traps_32.o
16 16
17obj-y += cpu/ timers/ 17obj-y += cpu/
18obj-$(CONFIG_VSYSCALL) += vsyscall/ 18obj-$(CONFIG_VSYSCALL) += vsyscall/
19obj-$(CONFIG_SMP) += smp.o 19obj-$(CONFIG_SMP) += smp.o
20obj-$(CONFIG_SH_STANDARD_BIOS) += sh_bios.o 20obj-$(CONFIG_SH_STANDARD_BIOS) += sh_bios.o
@@ -32,4 +32,6 @@ obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
32obj-$(CONFIG_DUMP_CODE) += disassemble.o 32obj-$(CONFIG_DUMP_CODE) += disassemble.o
33obj-$(CONFIG_HIBERNATION) += swsusp.o 33obj-$(CONFIG_HIBERNATION) += swsusp.o
34 34
35obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o
36
35EXTRA_CFLAGS += -Werror 37EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/kernel/Makefile_64 b/arch/sh/kernel/Makefile_64
index fe425d7f6871..67b9f6c6326b 100644
--- a/arch/sh/kernel/Makefile_64
+++ b/arch/sh/kernel/Makefile_64
@@ -2,19 +2,18 @@ extra-y := head_64.o init_task.o vmlinux.lds
2 2
3obj-y := debugtraps.o idle.o io.o io_generic.o irq.o machvec.o process_64.o \ 3obj-y := debugtraps.o idle.o io.o io_generic.o irq.o machvec.o process_64.o \
4 ptrace_64.o setup.o signal_64.o sys_sh.o sys_sh64.o \ 4 ptrace_64.o setup.o signal_64.o sys_sh.o sys_sh64.o \
5 syscalls_64.o time_64.o topology.o traps.o traps_64.o 5 syscalls_64.o time.o topology.o traps.o traps_64.o
6 6
7obj-y += cpu/ timers/ 7obj-y += cpu/
8obj-$(CONFIG_VSYSCALL) += vsyscall/
9obj-$(CONFIG_SMP) += smp.o 8obj-$(CONFIG_SMP) += smp.o
10obj-$(CONFIG_SH_STANDARD_BIOS) += sh_bios.o
11obj-$(CONFIG_SH_CPU_FREQ) += cpufreq.o 9obj-$(CONFIG_SH_CPU_FREQ) += cpufreq.o
12obj-$(CONFIG_MODULES) += sh_ksyms_64.o module.o 10obj-$(CONFIG_MODULES) += sh_ksyms_64.o module.o
13obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 11obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
14obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
15obj-$(CONFIG_CRASH_DUMP) += crash_dump.o 12obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
16obj-$(CONFIG_STACKTRACE) += stacktrace.o 13obj-$(CONFIG_STACKTRACE) += stacktrace.o
17obj-$(CONFIG_IO_TRAPPED) += io_trapped.o 14obj-$(CONFIG_IO_TRAPPED) += io_trapped.o
18obj-$(CONFIG_GENERIC_GPIO) += gpio.o 15obj-$(CONFIG_GENERIC_GPIO) += gpio.o
19 16
17obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += localtimer.o
18
20EXTRA_CFLAGS += -Werror 19EXTRA_CFLAGS += -Werror
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index 2600641a483f..eecad7cbd61e 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -17,5 +17,6 @@ obj-$(CONFIG_ARCH_SHMOBILE) += shmobile/
17 17
18obj-$(CONFIG_UBC_WAKEUP) += ubc.o 18obj-$(CONFIG_UBC_WAKEUP) += ubc.o
19obj-$(CONFIG_SH_ADC) += adc.o 19obj-$(CONFIG_SH_ADC) += adc.o
20obj-$(CONFIG_SH_CLK_CPG) += clock-cpg.o
20 21
21obj-y += irq/ init.o clock.o 22obj-y += irq/ init.o clock.o
diff --git a/arch/sh/kernel/cpu/clock-cpg.c b/arch/sh/kernel/cpu/clock-cpg.c
new file mode 100644
index 000000000000..275942e58e4f
--- /dev/null
+++ b/arch/sh/kernel/cpu/clock-cpg.c
@@ -0,0 +1,256 @@
1#include <linux/clk.h>
2#include <linux/compiler.h>
3#include <linux/bootmem.h>
4#include <linux/io.h>
5#include <asm/clock.h>
6
7static int sh_clk_mstp32_enable(struct clk *clk)
8{
9 __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
10 clk->enable_reg);
11 return 0;
12}
13
14static void sh_clk_mstp32_disable(struct clk *clk)
15{
16 __raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
17 clk->enable_reg);
18}
19
20static struct clk_ops sh_clk_mstp32_clk_ops = {
21 .enable = sh_clk_mstp32_enable,
22 .disable = sh_clk_mstp32_disable,
23 .recalc = followparent_recalc,
24};
25
26int __init sh_clk_mstp32_register(struct clk *clks, int nr)
27{
28 struct clk *clkp;
29 int ret = 0;
30 int k;
31
32 for (k = 0; !ret && (k < nr); k++) {
33 clkp = clks + k;
34 clkp->ops = &sh_clk_mstp32_clk_ops;
35 ret |= clk_register(clkp);
36 }
37
38 return ret;
39}
40
41static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
42{
43 return clk_rate_table_round(clk, clk->freq_table, rate);
44}
45
46static int sh_clk_div6_divisors[64] = {
47 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
48 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
49 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
50 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
51};
52
53static struct clk_div_mult_table sh_clk_div6_table = {
54 .divisors = sh_clk_div6_divisors,
55 .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
56};
57
58static unsigned long sh_clk_div6_recalc(struct clk *clk)
59{
60 struct clk_div_mult_table *table = &sh_clk_div6_table;
61 unsigned int idx;
62
63 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
64 table, NULL);
65
66 idx = __raw_readl(clk->enable_reg) & 0x003f;
67
68 return clk->freq_table[idx].frequency;
69}
70
71static int sh_clk_div6_set_rate(struct clk *clk,
72 unsigned long rate, int algo_id)
73{
74 unsigned long value;
75 int idx;
76
77 idx = clk_rate_table_find(clk, clk->freq_table, rate);
78 if (idx < 0)
79 return idx;
80
81 value = __raw_readl(clk->enable_reg);
82 value &= ~0x3f;
83 value |= idx;
84 __raw_writel(value, clk->enable_reg);
85 return 0;
86}
87
88static int sh_clk_div6_enable(struct clk *clk)
89{
90 unsigned long value;
91 int ret;
92
93 ret = sh_clk_div6_set_rate(clk, clk->rate, 0);
94 if (ret == 0) {
95 value = __raw_readl(clk->enable_reg);
96 value &= ~0x100; /* clear stop bit to enable clock */
97 __raw_writel(value, clk->enable_reg);
98 }
99 return ret;
100}
101
102static void sh_clk_div6_disable(struct clk *clk)
103{
104 unsigned long value;
105
106 value = __raw_readl(clk->enable_reg);
107 value |= 0x100; /* stop clock */
108 value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
109 __raw_writel(value, clk->enable_reg);
110}
111
112static struct clk_ops sh_clk_div6_clk_ops = {
113 .recalc = sh_clk_div6_recalc,
114 .round_rate = sh_clk_div_round_rate,
115 .set_rate = sh_clk_div6_set_rate,
116 .enable = sh_clk_div6_enable,
117 .disable = sh_clk_div6_disable,
118};
119
120int __init sh_clk_div6_register(struct clk *clks, int nr)
121{
122 struct clk *clkp;
123 void *freq_table;
124 int nr_divs = sh_clk_div6_table.nr_divisors;
125 int freq_table_size = sizeof(struct cpufreq_frequency_table);
126 int ret = 0;
127 int k;
128
129 freq_table_size *= (nr_divs + 1);
130
131 freq_table = alloc_bootmem(freq_table_size * nr);
132 if (!freq_table)
133 return -ENOMEM;
134
135 for (k = 0; !ret && (k < nr); k++) {
136 clkp = clks + k;
137
138 clkp->ops = &sh_clk_div6_clk_ops;
139 clkp->id = -1;
140 clkp->freq_table = freq_table + (k * freq_table_size);
141 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
142
143 ret = clk_register(clkp);
144 }
145
146 return ret;
147}
148
149static unsigned long sh_clk_div4_recalc(struct clk *clk)
150{
151 struct clk_div_mult_table *table = clk->priv;
152 unsigned int idx;
153
154 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
155 table, &clk->arch_flags);
156
157 idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f;
158
159 return clk->freq_table[idx].frequency;
160}
161
162static struct clk_ops sh_clk_div4_clk_ops = {
163 .recalc = sh_clk_div4_recalc,
164 .round_rate = sh_clk_div_round_rate,
165};
166
167int __init sh_clk_div4_register(struct clk *clks, int nr,
168 struct clk_div_mult_table *table)
169{
170 struct clk *clkp;
171 void *freq_table;
172 int nr_divs = table->nr_divisors;
173 int freq_table_size = sizeof(struct cpufreq_frequency_table);
174 int ret = 0;
175 int k;
176
177 freq_table_size *= (nr_divs + 1);
178
179 freq_table = alloc_bootmem(freq_table_size * nr);
180 if (!freq_table)
181 return -ENOMEM;
182
183 for (k = 0; !ret && (k < nr); k++) {
184 clkp = clks + k;
185
186 clkp->ops = &sh_clk_div4_clk_ops;
187 clkp->id = -1;
188 clkp->priv = table;
189
190 clkp->freq_table = freq_table + (k * freq_table_size);
191 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
192
193 ret = clk_register(clkp);
194 }
195
196 return ret;
197}
198
199#ifdef CONFIG_SH_CLK_CPG_LEGACY
200static struct clk master_clk = {
201 .name = "master_clk",
202 .flags = CLK_ENABLE_ON_INIT,
203 .rate = CONFIG_SH_PCLK_FREQ,
204};
205
206static struct clk peripheral_clk = {
207 .name = "peripheral_clk",
208 .parent = &master_clk,
209 .flags = CLK_ENABLE_ON_INIT,
210};
211
212static struct clk bus_clk = {
213 .name = "bus_clk",
214 .parent = &master_clk,
215 .flags = CLK_ENABLE_ON_INIT,
216};
217
218static struct clk cpu_clk = {
219 .name = "cpu_clk",
220 .parent = &master_clk,
221 .flags = CLK_ENABLE_ON_INIT,
222};
223
224/*
225 * The ordering of these clocks matters, do not change it.
226 */
227static struct clk *onchip_clocks[] = {
228 &master_clk,
229 &peripheral_clk,
230 &bus_clk,
231 &cpu_clk,
232};
233
234int __init __deprecated cpg_clk_init(void)
235{
236 int i, ret = 0;
237
238 for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
239 struct clk *clk = onchip_clocks[i];
240 arch_init_clk_ops(&clk->ops, i);
241 if (clk->ops)
242 ret |= clk_register(clk);
243 }
244
245 return ret;
246}
247
248/*
249 * Placeholder for compatability, until the lazy CPUs do this
250 * on their own.
251 */
252int __init __weak arch_clk_init(void)
253{
254 return cpg_clk_init();
255}
256#endif /* CONFIG_SH_CPG_CLK_LEGACY */
diff --git a/arch/sh/kernel/cpu/clock.c b/arch/sh/kernel/cpu/clock.c
index 1dc896483b59..f3a46be2ae81 100644
--- a/arch/sh/kernel/cpu/clock.c
+++ b/arch/sh/kernel/cpu/clock.c
@@ -1,15 +1,19 @@
1/* 1/*
2 * arch/sh/kernel/cpu/clock.c - SuperH clock framework 2 * arch/sh/kernel/cpu/clock.c - SuperH clock framework
3 * 3 *
4 * Copyright (C) 2005, 2006, 2007 Paul Mundt 4 * Copyright (C) 2005 - 2009 Paul Mundt
5 * 5 *
6 * This clock framework is derived from the OMAP version by: 6 * This clock framework is derived from the OMAP version by:
7 * 7 *
8 * Copyright (C) 2004 - 2005 Nokia Corporation 8 * Copyright (C) 2004 - 2008 Nokia Corporation
9 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 9 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
10 * 10 *
11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com> 11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
12 * 12 *
13 * With clkdev bits:
14 *
15 * Copyright (C) 2008 Russell King.
16 *
13 * This file is subject to the terms and conditions of the GNU General Public 17 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive 18 * License. See the file "COPYING" in the main directory of this archive
15 * for more details. 19 * for more details.
@@ -19,134 +23,159 @@
19#include <linux/module.h> 23#include <linux/module.h>
20#include <linux/mutex.h> 24#include <linux/mutex.h>
21#include <linux/list.h> 25#include <linux/list.h>
22#include <linux/kref.h>
23#include <linux/kobject.h> 26#include <linux/kobject.h>
24#include <linux/sysdev.h> 27#include <linux/sysdev.h>
25#include <linux/seq_file.h> 28#include <linux/seq_file.h>
26#include <linux/err.h> 29#include <linux/err.h>
27#include <linux/platform_device.h> 30#include <linux/platform_device.h>
28#include <linux/proc_fs.h> 31#include <linux/debugfs.h>
32#include <linux/cpufreq.h>
29#include <asm/clock.h> 33#include <asm/clock.h>
30#include <asm/timer.h> 34#include <asm/machvec.h>
31 35
32static LIST_HEAD(clock_list); 36static LIST_HEAD(clock_list);
33static DEFINE_SPINLOCK(clock_lock); 37static DEFINE_SPINLOCK(clock_lock);
34static DEFINE_MUTEX(clock_list_sem); 38static DEFINE_MUTEX(clock_list_sem);
35 39
36/* 40void clk_rate_table_build(struct clk *clk,
37 * Each subtype is expected to define the init routines for these clocks, 41 struct cpufreq_frequency_table *freq_table,
38 * as each subtype (or processor family) will have these clocks at the 42 int nr_freqs,
39 * very least. These are all provided through the CPG, which even some of 43 struct clk_div_mult_table *src_table,
40 * the more quirky parts (such as ST40, SH4-202, etc.) still have. 44 unsigned long *bitmap)
41 * 45{
42 * The processor-specific code is expected to register any additional 46 unsigned long mult, div;
43 * clock sources that are of interest. 47 unsigned long freq;
44 */ 48 int i;
45static struct clk master_clk = {
46 .name = "master_clk",
47 .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
48 .rate = CONFIG_SH_PCLK_FREQ,
49};
50 49
51static struct clk module_clk = { 50 for (i = 0; i < nr_freqs; i++) {
52 .name = "module_clk", 51 div = 1;
53 .parent = &master_clk, 52 mult = 1;
54 .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
55};
56 53
57static struct clk bus_clk = { 54 if (src_table->divisors && i < src_table->nr_divisors)
58 .name = "bus_clk", 55 div = src_table->divisors[i];
59 .parent = &master_clk,
60 .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
61};
62 56
63static struct clk cpu_clk = { 57 if (src_table->multipliers && i < src_table->nr_multipliers)
64 .name = "cpu_clk", 58 mult = src_table->multipliers[i];
65 .parent = &master_clk,
66 .flags = CLK_ALWAYS_ENABLED,
67};
68 59
69/* 60 if (!div || !mult || (bitmap && !test_bit(i, bitmap)))
70 * The ordering of these clocks matters, do not change it. 61 freq = CPUFREQ_ENTRY_INVALID;
71 */ 62 else
72static struct clk *onchip_clocks[] = { 63 freq = clk->parent->rate * mult / div;
73 &master_clk,
74 &module_clk,
75 &bus_clk,
76 &cpu_clk,
77};
78 64
79static void propagate_rate(struct clk *clk) 65 freq_table[i].index = i;
66 freq_table[i].frequency = freq;
67 }
68
69 /* Termination entry */
70 freq_table[i].index = i;
71 freq_table[i].frequency = CPUFREQ_TABLE_END;
72}
73
74long clk_rate_table_round(struct clk *clk,
75 struct cpufreq_frequency_table *freq_table,
76 unsigned long rate)
80{ 77{
81 struct clk *clkp; 78 unsigned long rate_error, rate_error_prev = ~0UL;
79 unsigned long rate_best_fit = rate;
80 unsigned long highest, lowest;
81 int i;
82
83 highest = lowest = 0;
84
85 for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
86 unsigned long freq = freq_table[i].frequency;
82 87
83 list_for_each_entry(clkp, &clock_list, node) { 88 if (freq == CPUFREQ_ENTRY_INVALID)
84 if (likely(clkp->parent != clk))
85 continue; 89 continue;
86 if (likely(clkp->ops && clkp->ops->recalc)) 90
87 clkp->ops->recalc(clkp); 91 if (freq > highest)
88 if (unlikely(clkp->flags & CLK_RATE_PROPAGATES)) 92 highest = freq;
89 propagate_rate(clkp); 93 if (freq < lowest)
94 lowest = freq;
95
96 rate_error = abs(freq - rate);
97 if (rate_error < rate_error_prev) {
98 rate_best_fit = freq;
99 rate_error_prev = rate_error;
100 }
101
102 if (rate_error == 0)
103 break;
90 } 104 }
105
106 if (rate >= highest)
107 rate_best_fit = highest;
108 if (rate <= lowest)
109 rate_best_fit = lowest;
110
111 return rate_best_fit;
91} 112}
92 113
93static int __clk_enable(struct clk *clk) 114int clk_rate_table_find(struct clk *clk,
115 struct cpufreq_frequency_table *freq_table,
116 unsigned long rate)
94{ 117{
95 /* 118 int i;
96 * See if this is the first time we're enabling the clock, some
97 * clocks that are always enabled still require "special"
98 * initialization. This is especially true if the clock mode
99 * changes and the clock needs to hunt for the proper set of
100 * divisors to use before it can effectively recalc.
101 */
102 if (unlikely(atomic_read(&clk->kref.refcount) == 1))
103 if (clk->ops && clk->ops->init)
104 clk->ops->init(clk);
105 119
106 kref_get(&clk->kref); 120 for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) {
121 unsigned long freq = freq_table[i].frequency;
107 122
108 if (clk->flags & CLK_ALWAYS_ENABLED) 123 if (freq == CPUFREQ_ENTRY_INVALID)
109 return 0; 124 continue;
110 125
111 if (likely(clk->ops && clk->ops->enable)) 126 if (freq == rate)
112 clk->ops->enable(clk); 127 return i;
128 }
113 129
114 return 0; 130 return -ENOENT;
115} 131}
116 132
117int clk_enable(struct clk *clk) 133/* Used for clocks that always have same value as the parent clock */
134unsigned long followparent_recalc(struct clk *clk)
118{ 135{
119 unsigned long flags; 136 return clk->parent ? clk->parent->rate : 0;
120 int ret; 137}
121
122 if (!clk)
123 return -EINVAL;
124 138
125 clk_enable(clk->parent); 139int clk_reparent(struct clk *child, struct clk *parent)
140{
141 list_del_init(&child->sibling);
142 if (parent)
143 list_add(&child->sibling, &parent->children);
144 child->parent = parent;
126 145
127 spin_lock_irqsave(&clock_lock, flags); 146 /* now do the debugfs renaming to reattach the child
128 ret = __clk_enable(clk); 147 to the proper parent */
129 spin_unlock_irqrestore(&clock_lock, flags);
130 148
131 return ret; 149 return 0;
132} 150}
133EXPORT_SYMBOL_GPL(clk_enable);
134 151
135static void clk_kref_release(struct kref *kref) 152/* Propagate rate to children */
153void propagate_rate(struct clk *tclk)
136{ 154{
137 /* Nothing to do */ 155 struct clk *clkp;
156
157 list_for_each_entry(clkp, &tclk->children, sibling) {
158 if (clkp->ops && clkp->ops->recalc)
159 clkp->rate = clkp->ops->recalc(clkp);
160
161 propagate_rate(clkp);
162 }
138} 163}
139 164
140static void __clk_disable(struct clk *clk) 165static void __clk_disable(struct clk *clk)
141{ 166{
142 int count = kref_put(&clk->kref, clk_kref_release); 167 if (clk->usecount == 0) {
143 168 printk(KERN_ERR "Trying disable clock %s with 0 usecount\n",
144 if (clk->flags & CLK_ALWAYS_ENABLED) 169 clk->name);
170 WARN_ON(1);
145 return; 171 return;
172 }
146 173
147 if (!count) { /* count reaches zero, disable the clock */ 174 if (!(--clk->usecount)) {
148 if (likely(clk->ops && clk->ops->disable)) 175 if (likely(clk->ops && clk->ops->disable))
149 clk->ops->disable(clk); 176 clk->ops->disable(clk);
177 if (likely(clk->parent))
178 __clk_disable(clk->parent);
150 } 179 }
151} 180}
152 181
@@ -160,28 +189,97 @@ void clk_disable(struct clk *clk)
160 spin_lock_irqsave(&clock_lock, flags); 189 spin_lock_irqsave(&clock_lock, flags);
161 __clk_disable(clk); 190 __clk_disable(clk);
162 spin_unlock_irqrestore(&clock_lock, flags); 191 spin_unlock_irqrestore(&clock_lock, flags);
163
164 clk_disable(clk->parent);
165} 192}
166EXPORT_SYMBOL_GPL(clk_disable); 193EXPORT_SYMBOL_GPL(clk_disable);
167 194
195static int __clk_enable(struct clk *clk)
196{
197 int ret = 0;
198
199 if (clk->usecount++ == 0) {
200 if (clk->parent) {
201 ret = __clk_enable(clk->parent);
202 if (unlikely(ret))
203 goto err;
204 }
205
206 if (clk->ops && clk->ops->enable) {
207 ret = clk->ops->enable(clk);
208 if (ret) {
209 if (clk->parent)
210 __clk_disable(clk->parent);
211 goto err;
212 }
213 }
214 }
215
216 return ret;
217err:
218 clk->usecount--;
219 return ret;
220}
221
222int clk_enable(struct clk *clk)
223{
224 unsigned long flags;
225 int ret;
226
227 if (!clk)
228 return -EINVAL;
229
230 spin_lock_irqsave(&clock_lock, flags);
231 ret = __clk_enable(clk);
232 spin_unlock_irqrestore(&clock_lock, flags);
233
234 return ret;
235}
236EXPORT_SYMBOL_GPL(clk_enable);
237
238static LIST_HEAD(root_clks);
239
240/**
241 * recalculate_root_clocks - recalculate and propagate all root clocks
242 *
243 * Recalculates all root clocks (clocks with no parent), which if the
244 * clock's .recalc is set correctly, should also propagate their rates.
245 * Called at init.
246 */
247void recalculate_root_clocks(void)
248{
249 struct clk *clkp;
250
251 list_for_each_entry(clkp, &root_clks, sibling) {
252 if (clkp->ops && clkp->ops->recalc)
253 clkp->rate = clkp->ops->recalc(clkp);
254 propagate_rate(clkp);
255 }
256}
257
168int clk_register(struct clk *clk) 258int clk_register(struct clk *clk)
169{ 259{
260 if (clk == NULL || IS_ERR(clk))
261 return -EINVAL;
262
263 /*
264 * trap out already registered clocks
265 */
266 if (clk->node.next || clk->node.prev)
267 return 0;
268
170 mutex_lock(&clock_list_sem); 269 mutex_lock(&clock_list_sem);
171 270
172 list_add(&clk->node, &clock_list); 271 INIT_LIST_HEAD(&clk->children);
173 kref_init(&clk->kref); 272 clk->usecount = 0;
174 273
175 mutex_unlock(&clock_list_sem); 274 if (clk->parent)
275 list_add(&clk->sibling, &clk->parent->children);
276 else
277 list_add(&clk->sibling, &root_clks);
176 278
177 if (clk->flags & CLK_ALWAYS_ENABLED) { 279 list_add(&clk->node, &clock_list);
178 pr_debug( "Clock '%s' is ALWAYS_ENABLED\n", clk->name); 280 if (clk->ops && clk->ops->init)
179 if (clk->ops && clk->ops->init) 281 clk->ops->init(clk);
180 clk->ops->init(clk); 282 mutex_unlock(&clock_list_sem);
181 if (clk->ops && clk->ops->enable)
182 clk->ops->enable(clk);
183 pr_debug( "Enabled.");
184 }
185 283
186 return 0; 284 return 0;
187} 285}
@@ -190,11 +288,21 @@ EXPORT_SYMBOL_GPL(clk_register);
190void clk_unregister(struct clk *clk) 288void clk_unregister(struct clk *clk)
191{ 289{
192 mutex_lock(&clock_list_sem); 290 mutex_lock(&clock_list_sem);
291 list_del(&clk->sibling);
193 list_del(&clk->node); 292 list_del(&clk->node);
194 mutex_unlock(&clock_list_sem); 293 mutex_unlock(&clock_list_sem);
195} 294}
196EXPORT_SYMBOL_GPL(clk_unregister); 295EXPORT_SYMBOL_GPL(clk_unregister);
197 296
297static void clk_enable_init_clocks(void)
298{
299 struct clk *clkp;
300
301 list_for_each_entry(clkp, &clock_list, node)
302 if (clkp->flags & CLK_ENABLE_ON_INIT)
303 clk_enable(clkp);
304}
305
198unsigned long clk_get_rate(struct clk *clk) 306unsigned long clk_get_rate(struct clk *clk)
199{ 307{
200 return clk->rate; 308 return clk->rate;
@@ -210,56 +318,59 @@ EXPORT_SYMBOL_GPL(clk_set_rate);
210int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id) 318int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
211{ 319{
212 int ret = -EOPNOTSUPP; 320 int ret = -EOPNOTSUPP;
321 unsigned long flags;
213 322
214 if (likely(clk->ops && clk->ops->set_rate)) { 323 spin_lock_irqsave(&clock_lock, flags);
215 unsigned long flags;
216 324
217 spin_lock_irqsave(&clock_lock, flags); 325 if (likely(clk->ops && clk->ops->set_rate)) {
218 ret = clk->ops->set_rate(clk, rate, algo_id); 326 ret = clk->ops->set_rate(clk, rate, algo_id);
219 spin_unlock_irqrestore(&clock_lock, flags); 327 if (ret != 0)
328 goto out_unlock;
329 } else {
330 clk->rate = rate;
331 ret = 0;
220 } 332 }
221 333
222 if (unlikely(clk->flags & CLK_RATE_PROPAGATES)) 334 if (clk->ops && clk->ops->recalc)
223 propagate_rate(clk); 335 clk->rate = clk->ops->recalc(clk);
224 336
225 return ret; 337 propagate_rate(clk);
226}
227EXPORT_SYMBOL_GPL(clk_set_rate_ex);
228 338
229void clk_recalc_rate(struct clk *clk) 339out_unlock:
230{ 340 spin_unlock_irqrestore(&clock_lock, flags);
231 if (likely(clk->ops && clk->ops->recalc)) {
232 unsigned long flags;
233
234 spin_lock_irqsave(&clock_lock, flags);
235 clk->ops->recalc(clk);
236 spin_unlock_irqrestore(&clock_lock, flags);
237 }
238 341
239 if (unlikely(clk->flags & CLK_RATE_PROPAGATES)) 342 return ret;
240 propagate_rate(clk);
241} 343}
242EXPORT_SYMBOL_GPL(clk_recalc_rate); 344EXPORT_SYMBOL_GPL(clk_set_rate_ex);
243 345
244int clk_set_parent(struct clk *clk, struct clk *parent) 346int clk_set_parent(struct clk *clk, struct clk *parent)
245{ 347{
348 unsigned long flags;
246 int ret = -EINVAL; 349 int ret = -EINVAL;
247 struct clk *old;
248 350
249 if (!parent || !clk) 351 if (!parent || !clk)
250 return ret; 352 return ret;
353 if (clk->parent == parent)
354 return 0;
251 355
252 old = clk->parent; 356 spin_lock_irqsave(&clock_lock, flags);
253 if (likely(clk->ops && clk->ops->set_parent)) { 357 if (clk->usecount == 0) {
254 unsigned long flags; 358 if (clk->ops->set_parent)
255 spin_lock_irqsave(&clock_lock, flags); 359 ret = clk->ops->set_parent(clk, parent);
256 ret = clk->ops->set_parent(clk, parent); 360 else
257 spin_unlock_irqrestore(&clock_lock, flags); 361 ret = clk_reparent(clk, parent);
258 clk->parent = (ret ? old : parent); 362
259 } 363 if (ret == 0) {
364 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
365 clk->name, clk->parent->name, clk->rate);
366 if (clk->ops->recalc)
367 clk->rate = clk->ops->recalc(clk);
368 propagate_rate(clk);
369 }
370 } else
371 ret = -EBUSY;
372 spin_unlock_irqrestore(&clock_lock, flags);
260 373
261 if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
262 propagate_rate(clk);
263 return ret; 374 return ret;
264} 375}
265EXPORT_SYMBOL_GPL(clk_set_parent); 376EXPORT_SYMBOL_GPL(clk_set_parent);
@@ -287,14 +398,69 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
287EXPORT_SYMBOL_GPL(clk_round_rate); 398EXPORT_SYMBOL_GPL(clk_round_rate);
288 399
289/* 400/*
401 * Find the correct struct clk for the device and connection ID.
402 * We do slightly fuzzy matching here:
403 * An entry with a NULL ID is assumed to be a wildcard.
404 * If an entry has a device ID, it must match
405 * If an entry has a connection ID, it must match
406 * Then we take the most specific entry - with the following
407 * order of precidence: dev+con > dev only > con only.
408 */
409static struct clk *clk_find(const char *dev_id, const char *con_id)
410{
411 struct clk_lookup *p;
412 struct clk *clk = NULL;
413 int match, best = 0;
414
415 list_for_each_entry(p, &clock_list, node) {
416 match = 0;
417 if (p->dev_id) {
418 if (!dev_id || strcmp(p->dev_id, dev_id))
419 continue;
420 match += 2;
421 }
422 if (p->con_id) {
423 if (!con_id || strcmp(p->con_id, con_id))
424 continue;
425 match += 1;
426 }
427 if (match == 0)
428 continue;
429
430 if (match > best) {
431 clk = p->clk;
432 best = match;
433 }
434 }
435 return clk;
436}
437
438struct clk *clk_get_sys(const char *dev_id, const char *con_id)
439{
440 struct clk *clk;
441
442 mutex_lock(&clock_list_sem);
443 clk = clk_find(dev_id, con_id);
444 mutex_unlock(&clock_list_sem);
445
446 return clk ? clk : ERR_PTR(-ENOENT);
447}
448EXPORT_SYMBOL_GPL(clk_get_sys);
449
450/*
290 * Returns a clock. Note that we first try to use device id on the bus 451 * Returns a clock. Note that we first try to use device id on the bus
291 * and clock name. If this fails, we try to use clock name only. 452 * and clock name. If this fails, we try to use clock name only.
292 */ 453 */
293struct clk *clk_get(struct device *dev, const char *id) 454struct clk *clk_get(struct device *dev, const char *id)
294{ 455{
456 const char *dev_id = dev ? dev_name(dev) : NULL;
295 struct clk *p, *clk = ERR_PTR(-ENOENT); 457 struct clk *p, *clk = ERR_PTR(-ENOENT);
296 int idno; 458 int idno;
297 459
460 clk = clk_get_sys(dev_id, id);
461 if (clk && !IS_ERR(clk))
462 return clk;
463
298 if (dev == NULL || dev->bus != &platform_bus_type) 464 if (dev == NULL || dev->bus != &platform_bus_type)
299 idno = -1; 465 idno = -1;
300 else 466 else
@@ -330,36 +496,6 @@ void clk_put(struct clk *clk)
330} 496}
331EXPORT_SYMBOL_GPL(clk_put); 497EXPORT_SYMBOL_GPL(clk_put);
332 498
333void __init __attribute__ ((weak))
334arch_init_clk_ops(struct clk_ops **ops, int type)
335{
336}
337
338int __init __attribute__ ((weak))
339arch_clk_init(void)
340{
341 return 0;
342}
343
344static int show_clocks(char *buf, char **start, off_t off,
345 int len, int *eof, void *data)
346{
347 struct clk *clk;
348 char *p = buf;
349
350 list_for_each_entry_reverse(clk, &clock_list, node) {
351 unsigned long rate = clk_get_rate(clk);
352
353 p += sprintf(p, "%-12s\t: %ld.%02ldMHz\t%s\n", clk->name,
354 rate / 1000000, (rate % 1000000) / 10000,
355 ((clk->flags & CLK_ALWAYS_ENABLED) ||
356 (atomic_read(&clk->kref.refcount) != 1)) ?
357 "enabled" : "disabled");
358 }
359
360 return p - buf;
361}
362
363#ifdef CONFIG_PM 499#ifdef CONFIG_PM
364static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state) 500static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state)
365{ 501{
@@ -369,20 +505,22 @@ static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state)
369 switch (state.event) { 505 switch (state.event) {
370 case PM_EVENT_ON: 506 case PM_EVENT_ON:
371 /* Resumeing from hibernation */ 507 /* Resumeing from hibernation */
372 if (prev_state.event == PM_EVENT_FREEZE) { 508 if (prev_state.event != PM_EVENT_FREEZE)
373 list_for_each_entry(clkp, &clock_list, node) 509 break;
374 if (likely(clkp->ops)) { 510
375 unsigned long rate = clkp->rate; 511 list_for_each_entry(clkp, &clock_list, node) {
376 512 if (likely(clkp->ops)) {
377 if (likely(clkp->ops->set_parent)) 513 unsigned long rate = clkp->rate;
378 clkp->ops->set_parent(clkp, 514
379 clkp->parent); 515 if (likely(clkp->ops->set_parent))
380 if (likely(clkp->ops->set_rate)) 516 clkp->ops->set_parent(clkp,
381 clkp->ops->set_rate(clkp, 517 clkp->parent);
382 rate, NO_CHANGE); 518 if (likely(clkp->ops->set_rate))
383 else if (likely(clkp->ops->recalc)) 519 clkp->ops->set_rate(clkp,
384 clkp->ops->recalc(clkp); 520 rate, NO_CHANGE);
385 } 521 else if (likely(clkp->ops->recalc))
522 clkp->rate = clkp->ops->recalc(clkp);
523 }
386 } 524 }
387 break; 525 break;
388 case PM_EVENT_FREEZE: 526 case PM_EVENT_FREEZE:
@@ -426,34 +564,116 @@ subsys_initcall(clk_sysdev_init);
426 564
427int __init clk_init(void) 565int __init clk_init(void)
428{ 566{
429 int i, ret = 0; 567 int ret;
430
431 BUG_ON(!master_clk.rate);
432
433 for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
434 struct clk *clk = onchip_clocks[i];
435 568
436 arch_init_clk_ops(&clk->ops, i); 569 ret = arch_clk_init();
437 ret |= clk_register(clk); 570 if (unlikely(ret)) {
571 pr_err("%s: CPU clock registration failed.\n", __func__);
572 return ret;
438 } 573 }
439 574
440 ret |= arch_clk_init(); 575 if (sh_mv.mv_clk_init) {
576 ret = sh_mv.mv_clk_init();
577 if (unlikely(ret)) {
578 pr_err("%s: machvec clock initialization failed.\n",
579 __func__);
580 return ret;
581 }
582 }
441 583
442 /* Kick the child clocks.. */ 584 /* Kick the child clocks.. */
443 propagate_rate(&master_clk); 585 recalculate_root_clocks();
444 propagate_rate(&bus_clk); 586
587 /* Enable the necessary init clocks */
588 clk_enable_init_clocks();
445 589
446 return ret; 590 return ret;
447} 591}
448 592
449static int __init clk_proc_init(void) 593/*
594 * debugfs support to trace clock tree hierarchy and attributes
595 */
596static struct dentry *clk_debugfs_root;
597
598static int clk_debugfs_register_one(struct clk *c)
450{ 599{
451 struct proc_dir_entry *p; 600 int err;
452 p = create_proc_read_entry("clocks", S_IRUSR, NULL, 601 struct dentry *d, *child;
453 show_clocks, NULL); 602 struct clk *pa = c->parent;
454 if (unlikely(!p)) 603 char s[255];
455 return -EINVAL; 604 char *p = s;
605
606 p += sprintf(p, "%s", c->name);
607 if (c->id >= 0)
608 sprintf(p, ":%d", c->id);
609 d = debugfs_create_dir(s, pa ? pa->dentry : clk_debugfs_root);
610 if (!d)
611 return -ENOMEM;
612 c->dentry = d;
613
614 d = debugfs_create_u8("usecount", S_IRUGO, c->dentry, (u8 *)&c->usecount);
615 if (!d) {
616 err = -ENOMEM;
617 goto err_out;
618 }
619 d = debugfs_create_u32("rate", S_IRUGO, c->dentry, (u32 *)&c->rate);
620 if (!d) {
621 err = -ENOMEM;
622 goto err_out;
623 }
624 d = debugfs_create_x32("flags", S_IRUGO, c->dentry, (u32 *)&c->flags);
625 if (!d) {
626 err = -ENOMEM;
627 goto err_out;
628 }
629 return 0;
456 630
631err_out:
632 d = c->dentry;
633 list_for_each_entry(child, &d->d_subdirs, d_u.d_child)
634 debugfs_remove(child);
635 debugfs_remove(c->dentry);
636 return err;
637}
638
639static int clk_debugfs_register(struct clk *c)
640{
641 int err;
642 struct clk *pa = c->parent;
643
644 if (pa && !pa->dentry) {
645 err = clk_debugfs_register(pa);
646 if (err)
647 return err;
648 }
649
650 if (!c->dentry) {
651 err = clk_debugfs_register_one(c);
652 if (err)
653 return err;
654 }
655 return 0;
656}
657
658static int __init clk_debugfs_init(void)
659{
660 struct clk *c;
661 struct dentry *d;
662 int err;
663
664 d = debugfs_create_dir("clock", NULL);
665 if (!d)
666 return -ENOMEM;
667 clk_debugfs_root = d;
668
669 list_for_each_entry(c, &clock_list, node) {
670 err = clk_debugfs_register(c);
671 if (err)
672 goto err_out;
673 }
457 return 0; 674 return 0;
675err_out:
676 debugfs_remove(clk_debugfs_root); /* REVISIT: Cleanup correctly */
677 return err;
458} 678}
459subsys_initcall(clk_proc_init); 679late_initcall(clk_debugfs_init);
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index d29e69c156f0..ad85421099cd 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -62,6 +62,11 @@ static void __init speculative_execution_init(void)
62#define speculative_execution_init() do { } while (0) 62#define speculative_execution_init() do { } while (0)
63#endif 63#endif
64 64
65/* 2nd-level cache init */
66void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void)
67{
68}
69
65/* 70/*
66 * Generic first-level cache init 71 * Generic first-level cache init
67 */ 72 */
@@ -146,6 +151,8 @@ static void __uses_jump_to_uncached cache_init(void)
146 flags &= ~CCR_CACHE_ENABLE; 151 flags &= ~CCR_CACHE_ENABLE;
147#endif 152#endif
148 153
154 l2_cache_init();
155
149 ctrl_outl(flags, CCR); 156 ctrl_outl(flags, CCR);
150 back_to_cached(); 157 back_to_cached();
151} 158}
diff --git a/arch/sh/kernel/cpu/irq/imask.c b/arch/sh/kernel/cpu/irq/imask.c
index 301b505c4278..6b5d191eec3a 100644
--- a/arch/sh/kernel/cpu/irq/imask.c
+++ b/arch/sh/kernel/cpu/irq/imask.c
@@ -18,38 +18,17 @@
18#include <linux/spinlock.h> 18#include <linux/spinlock.h>
19#include <linux/cache.h> 19#include <linux/cache.h>
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/bitmap.h>
21#include <asm/system.h> 22#include <asm/system.h>
22#include <asm/irq.h> 23#include <asm/irq.h>
23 24
24/* Bitmap of IRQ masked */ 25/* Bitmap of IRQ masked */
25static unsigned long imask_mask = 0x7fff;
26static int interrupt_priority = 0;
27
28static void enable_imask_irq(unsigned int irq);
29static void disable_imask_irq(unsigned int irq);
30static void shutdown_imask_irq(unsigned int irq);
31static void mask_and_ack_imask(unsigned int);
32static void end_imask_irq(unsigned int irq);
33
34#define IMASK_PRIORITY 15 26#define IMASK_PRIORITY 15
35 27
36static unsigned int startup_imask_irq(unsigned int irq) 28static DECLARE_BITMAP(imask_mask, IMASK_PRIORITY);
37{ 29static int interrupt_priority;
38 /* Nothing to do */
39 return 0; /* never anything pending */
40}
41 30
42static struct hw_interrupt_type imask_irq_type = { 31static inline void set_interrupt_registers(int ip)
43 .typename = "SR.IMASK",
44 .startup = startup_imask_irq,
45 .shutdown = shutdown_imask_irq,
46 .enable = enable_imask_irq,
47 .disable = disable_imask_irq,
48 .ack = mask_and_ack_imask,
49 .end = end_imask_irq
50};
51
52void static inline set_interrupt_registers(int ip)
53{ 32{
54 unsigned long __dummy; 33 unsigned long __dummy;
55 34
@@ -72,42 +51,31 @@ void static inline set_interrupt_registers(int ip)
72 : "t"); 51 : "t");
73} 52}
74 53
75static void disable_imask_irq(unsigned int irq) 54static void mask_imask_irq(unsigned int irq)
76{ 55{
77 clear_bit(irq, &imask_mask); 56 clear_bit(irq, imask_mask);
78 if (interrupt_priority < IMASK_PRIORITY - irq) 57 if (interrupt_priority < IMASK_PRIORITY - irq)
79 interrupt_priority = IMASK_PRIORITY - irq; 58 interrupt_priority = IMASK_PRIORITY - irq;
80
81 set_interrupt_registers(interrupt_priority); 59 set_interrupt_registers(interrupt_priority);
82} 60}
83 61
84static void enable_imask_irq(unsigned int irq) 62static void unmask_imask_irq(unsigned int irq)
85{ 63{
86 set_bit(irq, &imask_mask); 64 set_bit(irq, imask_mask);
87 interrupt_priority = IMASK_PRIORITY - ffz(imask_mask); 65 interrupt_priority = IMASK_PRIORITY -
88 66 find_first_zero_bit(imask_mask, IMASK_PRIORITY);
89 set_interrupt_registers(interrupt_priority); 67 set_interrupt_registers(interrupt_priority);
90} 68}
91 69
92static void mask_and_ack_imask(unsigned int irq) 70static struct irq_chip imask_irq_chip = {
93{ 71 .typename = "SR.IMASK",
94 disable_imask_irq(irq); 72 .mask = mask_imask_irq,
95} 73 .unmask = unmask_imask_irq,
96 74 .mask_ack = mask_imask_irq,
97static void end_imask_irq(unsigned int irq) 75};
98{
99 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
100 enable_imask_irq(irq);
101}
102
103static void shutdown_imask_irq(unsigned int irq)
104{
105 /* Nothing to do */
106}
107 76
108void make_imask_irq(unsigned int irq) 77void make_imask_irq(unsigned int irq)
109{ 78{
110 disable_irq_nosync(irq); 79 set_irq_chip_and_handler_name(irq, &imask_irq_chip,
111 irq_desc[irq].chip = &imask_irq_type; 80 handle_level_irq, "level");
112 enable_irq(irq);
113} 81}
diff --git a/arch/sh/kernel/cpu/irq/intc-sh5.c b/arch/sh/kernel/cpu/irq/intc-sh5.c
index 726f0335da76..6c092f1f5557 100644
--- a/arch/sh/kernel/cpu/irq/intc-sh5.c
+++ b/arch/sh/kernel/cpu/irq/intc-sh5.c
@@ -84,7 +84,7 @@ static void disable_intc_irq(unsigned int irq);
84static void mask_and_ack_intc(unsigned int); 84static void mask_and_ack_intc(unsigned int);
85static void end_intc_irq(unsigned int irq); 85static void end_intc_irq(unsigned int irq);
86 86
87static struct hw_interrupt_type intc_irq_type = { 87static struct irq_chip intc_irq_type = {
88 .typename = "INTC", 88 .typename = "INTC",
89 .startup = startup_intc_irq, 89 .startup = startup_intc_irq,
90 .shutdown = shutdown_intc_irq, 90 .shutdown = shutdown_intc_irq,
@@ -152,43 +152,13 @@ static void end_intc_irq(unsigned int irq)
152 enable_intc_irq(irq); 152 enable_intc_irq(irq);
153} 153}
154 154
155/* For future use, if we ever support IRLM=0) */
156void make_intc_irq(unsigned int irq)
157{
158 disable_irq_nosync(irq);
159 irq_desc[irq].chip = &intc_irq_type;
160 disable_intc_irq(irq);
161}
162
163#if defined(CONFIG_PROC_FS) && defined(CONFIG_SYSCTL)
164static int IRQ_to_vectorN[NR_INTC_IRQS] = {
165 0x12, 0x15, 0x18, 0x1B, 0x40, 0x41, 0x42, 0x43, /* 0- 7 */
166 -1, -1, -1, -1, 0x50, 0x51, 0x52, 0x53, /* 8-15 */
167 0x54, 0x55, 0x32, 0x33, 0x34, 0x35, 0x36, -1, /* 16-23 */
168 -1, -1, -1, -1, -1, -1, -1, -1, /* 24-31 */
169 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x38, /* 32-39 */
170 0x39, 0x3A, 0x3B, -1, -1, -1, -1, -1, /* 40-47 */
171 -1, -1, -1, -1, -1, -1, -1, -1, /* 48-55 */
172 -1, -1, -1, -1, -1, -1, -1, 0x2B, /* 56-63 */
173
174};
175
176int intc_irq_describe(char* p, int irq)
177{
178 if (irq < NR_INTC_IRQS)
179 return sprintf(p, "(0x%3x)", IRQ_to_vectorN[irq]*0x20);
180 else
181 return 0;
182}
183#endif
184
185void __init plat_irq_setup(void) 155void __init plat_irq_setup(void)
186{ 156{
187 unsigned long long __dummy0, __dummy1=~0x00000000100000f0; 157 unsigned long long __dummy0, __dummy1=~0x00000000100000f0;
188 unsigned long reg; 158 unsigned long reg;
189 int i; 159 int i;
190 160
191 intc_virt = onchip_remap(INTC_BASE, 1024, "INTC"); 161 intc_virt = (unsigned long)ioremap_nocache(INTC_BASE, 1024);
192 if (!intc_virt) { 162 if (!intc_virt) {
193 panic("Unable to remap INTC\n"); 163 panic("Unable to remap INTC\n");
194 } 164 }
@@ -196,7 +166,7 @@ void __init plat_irq_setup(void)
196 166
197 /* Set default: per-line enable/disable, priority driven ack/eoi */ 167 /* Set default: per-line enable/disable, priority driven ack/eoi */
198 for (i = 0; i < NR_INTC_IRQS; i++) 168 for (i = 0; i < NR_INTC_IRQS; i++)
199 irq_desc[i].chip = &intc_irq_type; 169 set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
200 170
201 171
202 /* Disable all interrupts and set all priorities to 0 to avoid trouble */ 172 /* Disable all interrupts and set all priorities to 0 to avoid trouble */
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index 3eb17ee5540e..808d99a48efb 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -21,6 +21,7 @@
21#include <linux/module.h> 21#include <linux/module.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/topology.h>
24 25
25static inline struct ipr_desc *get_ipr_desc(unsigned int irq) 26static inline struct ipr_desc *get_ipr_desc(unsigned int irq)
26{ 27{
@@ -59,10 +60,18 @@ void register_ipr_controller(struct ipr_desc *desc)
59 60
60 for (i = 0; i < desc->nr_irqs; i++) { 61 for (i = 0; i < desc->nr_irqs; i++) {
61 struct ipr_data *p = desc->ipr_data + i; 62 struct ipr_data *p = desc->ipr_data + i;
63 struct irq_desc *irq_desc;
62 64
63 BUG_ON(p->ipr_idx >= desc->nr_offsets); 65 BUG_ON(p->ipr_idx >= desc->nr_offsets);
64 BUG_ON(!desc->ipr_offsets[p->ipr_idx]); 66 BUG_ON(!desc->ipr_offsets[p->ipr_idx]);
65 67
68 irq_desc = irq_to_desc_alloc_node(p->irq, numa_node_id());
69 if (unlikely(!irq_desc)) {
70 printk(KERN_INFO "can not get irq_desc for %d\n",
71 p->irq);
72 continue;
73 }
74
66 disable_irq_nosync(p->irq); 75 disable_irq_nosync(p->irq);
67 set_irq_chip_and_handler_name(p->irq, &desc->chip, 76 set_irq_chip_and_handler_name(p->irq, &desc->chip,
68 handle_level_irq, "level"); 77 handle_level_irq, "level");
diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
index d2c157917999..4fe863170e31 100644
--- a/arch/sh/kernel/cpu/sh2/clock-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
@@ -38,32 +38,27 @@ static struct clk_ops sh7619_master_clk_ops = {
38 .init = master_clk_init, 38 .init = master_clk_init,
39}; 39};
40 40
41static void module_clk_recalc(struct clk *clk) 41static unsigned long module_clk_recalc(struct clk *clk)
42{ 42{
43 int idx = (ctrl_inw(FREQCR) & 0x0007); 43 int idx = (ctrl_inw(FREQCR) & 0x0007);
44 clk->rate = clk->parent->rate / pfc_divisors[idx]; 44 return clk->parent->rate / pfc_divisors[idx];
45} 45}
46 46
47static struct clk_ops sh7619_module_clk_ops = { 47static struct clk_ops sh7619_module_clk_ops = {
48 .recalc = module_clk_recalc, 48 .recalc = module_clk_recalc,
49}; 49};
50 50
51static void bus_clk_recalc(struct clk *clk) 51static unsigned long bus_clk_recalc(struct clk *clk)
52{ 52{
53 clk->rate = clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7]; 53 return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7];
54} 54}
55 55
56static struct clk_ops sh7619_bus_clk_ops = { 56static struct clk_ops sh7619_bus_clk_ops = {
57 .recalc = bus_clk_recalc, 57 .recalc = bus_clk_recalc,
58}; 58};
59 59
60static void cpu_clk_recalc(struct clk *clk)
61{
62 clk->rate = clk->parent->rate;
63}
64
65static struct clk_ops sh7619_cpu_clk_ops = { 60static struct clk_ops sh7619_cpu_clk_ops = {
66 .recalc = cpu_clk_recalc, 61 .recalc = followparent_recalc,
67}; 62};
68 63
69static struct clk_ops *sh7619_clk_ops[] = { 64static struct clk_ops *sh7619_clk_ops[] = {
@@ -78,4 +73,3 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
78 if (idx < ARRAY_SIZE(sh7619_clk_ops)) 73 if (idx < ARRAY_SIZE(sh7619_clk_ops))
79 *ops = sh7619_clk_ops[idx]; 74 *ops = sh7619_clk_ops[idx];
80} 75}
81
diff --git a/arch/sh/kernel/cpu/sh2/setup-sh7619.c b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
index 0e32d8e448ca..13798733f2db 100644
--- a/arch/sh/kernel/cpu/sh2/setup-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/setup-sh7619.c
@@ -12,6 +12,8 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/serial.h> 13#include <linux/serial.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16#include <linux/io.h>
15 17
16enum { 18enum {
17 UNUSED = 0, 19 UNUSED = 0,
@@ -109,9 +111,75 @@ static struct platform_device eth_device = {
109 .resource = eth_resources, 111 .resource = eth_resources,
110}; 112};
111 113
114static struct sh_timer_config cmt0_platform_data = {
115 .name = "CMT0",
116 .channel_offset = 0x02,
117 .timer_bit = 0,
118 .clk = "peripheral_clk",
119 .clockevent_rating = 125,
120 .clocksource_rating = 0, /* disabled due to code generation issues */
121};
122
123static struct resource cmt0_resources[] = {
124 [0] = {
125 .name = "CMT0",
126 .start = 0xf84a0072,
127 .end = 0xf84a0077,
128 .flags = IORESOURCE_MEM,
129 },
130 [1] = {
131 .start = 86,
132 .flags = IORESOURCE_IRQ,
133 },
134};
135
136static struct platform_device cmt0_device = {
137 .name = "sh_cmt",
138 .id = 0,
139 .dev = {
140 .platform_data = &cmt0_platform_data,
141 },
142 .resource = cmt0_resources,
143 .num_resources = ARRAY_SIZE(cmt0_resources),
144};
145
146static struct sh_timer_config cmt1_platform_data = {
147 .name = "CMT1",
148 .channel_offset = 0x08,
149 .timer_bit = 1,
150 .clk = "peripheral_clk",
151 .clockevent_rating = 125,
152 .clocksource_rating = 0, /* disabled due to code generation issues */
153};
154
155static struct resource cmt1_resources[] = {
156 [0] = {
157 .name = "CMT1",
158 .start = 0xf84a0078,
159 .end = 0xf84a007d,
160 .flags = IORESOURCE_MEM,
161 },
162 [1] = {
163 .start = 87,
164 .flags = IORESOURCE_IRQ,
165 },
166};
167
168static struct platform_device cmt1_device = {
169 .name = "sh_cmt",
170 .id = 1,
171 .dev = {
172 .platform_data = &cmt1_platform_data,
173 },
174 .resource = cmt1_resources,
175 .num_resources = ARRAY_SIZE(cmt1_resources),
176};
177
112static struct platform_device *sh7619_devices[] __initdata = { 178static struct platform_device *sh7619_devices[] __initdata = {
113 &sci_device, 179 &sci_device,
114 &eth_device, 180 &eth_device,
181 &cmt0_device,
182 &cmt1_device,
115}; 183};
116 184
117static int __init sh7619_devices_setup(void) 185static int __init sh7619_devices_setup(void)
@@ -125,3 +193,19 @@ void __init plat_irq_setup(void)
125{ 193{
126 register_intc_controller(&intc_desc); 194 register_intc_controller(&intc_desc);
127} 195}
196
197static struct platform_device *sh7619_early_devices[] __initdata = {
198 &cmt0_device,
199 &cmt1_device,
200};
201
202#define STBCR3 0xf80a0000
203
204void __init plat_early_device_setup(void)
205{
206 /* enable CMT clock */
207 __raw_writeb(__raw_readb(STBCR3) & ~0x10, STBCR3);
208
209 early_platform_add_devices(sh7619_early_devices,
210 ARRAY_SIZE(sh7619_early_devices));
211}
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
index 4a5e59732334..7814c76159a7 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -34,37 +34,37 @@ static const int pfc_divisors[]={1,2,3,4,6,8,12};
34 34
35static void master_clk_init(struct clk *clk) 35static void master_clk_init(struct clk *clk)
36{ 36{
37 clk->rate = 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; 37 return 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
38} 38}
39 39
40static struct clk_ops sh7201_master_clk_ops = { 40static struct clk_ops sh7201_master_clk_ops = {
41 .init = master_clk_init, 41 .init = master_clk_init,
42}; 42};
43 43
44static void module_clk_recalc(struct clk *clk) 44static unsigned long module_clk_recalc(struct clk *clk)
45{ 45{
46 int idx = (ctrl_inw(FREQCR) & 0x0007); 46 int idx = (ctrl_inw(FREQCR) & 0x0007);
47 clk->rate = clk->parent->rate / pfc_divisors[idx]; 47 return clk->parent->rate / pfc_divisors[idx];
48} 48}
49 49
50static struct clk_ops sh7201_module_clk_ops = { 50static struct clk_ops sh7201_module_clk_ops = {
51 .recalc = module_clk_recalc, 51 .recalc = module_clk_recalc,
52}; 52};
53 53
54static void bus_clk_recalc(struct clk *clk) 54static unsigned long bus_clk_recalc(struct clk *clk)
55{ 55{
56 int idx = (ctrl_inw(FREQCR) & 0x0007); 56 int idx = (ctrl_inw(FREQCR) & 0x0007);
57 clk->rate = clk->parent->rate / pfc_divisors[idx]; 57 return clk->parent->rate / pfc_divisors[idx];
58} 58}
59 59
60static struct clk_ops sh7201_bus_clk_ops = { 60static struct clk_ops sh7201_bus_clk_ops = {
61 .recalc = bus_clk_recalc, 61 .recalc = bus_clk_recalc,
62}; 62};
63 63
64static void cpu_clk_recalc(struct clk *clk) 64static unsigned long cpu_clk_recalc(struct clk *clk)
65{ 65{
66 int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007); 66 int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007);
67 clk->rate = clk->parent->rate / ifc_divisors[idx]; 67 return clk->parent->rate / ifc_divisors[idx];
68} 68}
69 69
70static struct clk_ops sh7201_cpu_clk_ops = { 70static struct clk_ops sh7201_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
index fb781329848a..940986965102 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
@@ -46,33 +46,28 @@ static struct clk_ops sh7203_master_clk_ops = {
46 .init = master_clk_init, 46 .init = master_clk_init,
47}; 47};
48 48
49static void module_clk_recalc(struct clk *clk) 49static unsigned long module_clk_recalc(struct clk *clk)
50{ 50{
51 int idx = (ctrl_inw(FREQCR) & 0x0007); 51 int idx = (ctrl_inw(FREQCR) & 0x0007);
52 clk->rate = clk->parent->rate / pfc_divisors[idx]; 52 return clk->parent->rate / pfc_divisors[idx];
53} 53}
54 54
55static struct clk_ops sh7203_module_clk_ops = { 55static struct clk_ops sh7203_module_clk_ops = {
56 .recalc = module_clk_recalc, 56 .recalc = module_clk_recalc,
57}; 57};
58 58
59static void bus_clk_recalc(struct clk *clk) 59static unsigned long bus_clk_recalc(struct clk *clk)
60{ 60{
61 int idx = (ctrl_inw(FREQCR) & 0x0007); 61 int idx = (ctrl_inw(FREQCR) & 0x0007);
62 clk->rate = clk->parent->rate / pfc_divisors[idx-2]; 62 return clk->parent->rate / pfc_divisors[idx-2];
63} 63}
64 64
65static struct clk_ops sh7203_bus_clk_ops = { 65static struct clk_ops sh7203_bus_clk_ops = {
66 .recalc = bus_clk_recalc, 66 .recalc = bus_clk_recalc,
67}; 67};
68 68
69static void cpu_clk_recalc(struct clk *clk)
70{
71 clk->rate = clk->parent->rate;
72}
73
74static struct clk_ops sh7203_cpu_clk_ops = { 69static struct clk_ops sh7203_cpu_clk_ops = {
75 .recalc = cpu_clk_recalc, 70 .recalc = followparent_recalc,
76}; 71};
77 72
78static struct clk_ops *sh7203_clk_ops[] = { 73static struct clk_ops *sh7203_clk_ops[] = {
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
index 82d7f991ef6b..c2268bdeceeb 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
@@ -41,29 +41,29 @@ static struct clk_ops sh7206_master_clk_ops = {
41 .init = master_clk_init, 41 .init = master_clk_init,
42}; 42};
43 43
44static void module_clk_recalc(struct clk *clk) 44static unsigned long module_clk_recalc(struct clk *clk)
45{ 45{
46 int idx = (ctrl_inw(FREQCR) & 0x0007); 46 int idx = (ctrl_inw(FREQCR) & 0x0007);
47 clk->rate = clk->parent->rate / pfc_divisors[idx]; 47 return clk->parent->rate / pfc_divisors[idx];
48} 48}
49 49
50static struct clk_ops sh7206_module_clk_ops = { 50static struct clk_ops sh7206_module_clk_ops = {
51 .recalc = module_clk_recalc, 51 .recalc = module_clk_recalc,
52}; 52};
53 53
54static void bus_clk_recalc(struct clk *clk) 54static unsigned long bus_clk_recalc(struct clk *clk)
55{ 55{
56 clk->rate = clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; 56 return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007];
57} 57}
58 58
59static struct clk_ops sh7206_bus_clk_ops = { 59static struct clk_ops sh7206_bus_clk_ops = {
60 .recalc = bus_clk_recalc, 60 .recalc = bus_clk_recalc,
61}; 61};
62 62
63static void cpu_clk_recalc(struct clk *clk) 63static unsigned long cpu_clk_recalc(struct clk *clk)
64{ 64{
65 int idx = (ctrl_inw(FREQCR) & 0x0007); 65 int idx = (ctrl_inw(FREQCR) & 0x0007);
66 clk->rate = clk->parent->rate / ifc_divisors[idx]; 66 return clk->parent->rate / ifc_divisors[idx];
67} 67}
68 68
69static struct clk_ops sh7206_cpu_clk_ops = { 69static struct clk_ops sh7206_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh2a/setup-mxg.c b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
index 844293723cfc..869c2da4820b 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-mxg.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-mxg.c
@@ -11,6 +11,7 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/sh_timer.h>
14 15
15enum { 16enum {
16 UNUSED = 0, 17 UNUSED = 0,
@@ -24,7 +25,7 @@ enum {
24 25
25 SCIF0, SCIF1, 26 SCIF0, SCIF1,
26 27
27 MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5 28 MTU2_GROUP1, MTU2_GROUP2, MTU2_GROUP3, MTU2_GROUP4, MTU2_GROUP5,
28 MTU2_TGI3B, MTU2_TGI3C, 29 MTU2_TGI3B, MTU2_TGI3C,
29 30
30 /* interrupt groups */ 31 /* interrupt groups */
@@ -113,6 +114,99 @@ static struct intc_mask_reg mask_registers[] __initdata = {
113static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups, 114static DECLARE_INTC_DESC(intc_desc, "mxg", vectors, groups,
114 mask_registers, prio_registers, NULL); 115 mask_registers, prio_registers, NULL);
115 116
117static struct sh_timer_config mtu2_0_platform_data = {
118 .name = "MTU2_0",
119 .channel_offset = -0x80,
120 .timer_bit = 0,
121 .clk = "peripheral_clk",
122 .clockevent_rating = 200,
123};
124
125static struct resource mtu2_0_resources[] = {
126 [0] = {
127 .name = "MTU2_0",
128 .start = 0xff801300,
129 .end = 0xff801326,
130 .flags = IORESOURCE_MEM,
131 },
132 [1] = {
133 .start = 228,
134 .flags = IORESOURCE_IRQ,
135 },
136};
137
138static struct platform_device mtu2_0_device = {
139 .name = "sh_mtu2",
140 .id = 0,
141 .dev = {
142 .platform_data = &mtu2_0_platform_data,
143 },
144 .resource = mtu2_0_resources,
145 .num_resources = ARRAY_SIZE(mtu2_0_resources),
146};
147
148static struct sh_timer_config mtu2_1_platform_data = {
149 .name = "MTU2_1",
150 .channel_offset = -0x100,
151 .timer_bit = 1,
152 .clk = "peripheral_clk",
153 .clockevent_rating = 200,
154};
155
156static struct resource mtu2_1_resources[] = {
157 [0] = {
158 .name = "MTU2_1",
159 .start = 0xff801380,
160 .end = 0xff801390,
161 .flags = IORESOURCE_MEM,
162 },
163 [1] = {
164 .start = 234,
165 .flags = IORESOURCE_IRQ,
166 },
167};
168
169static struct platform_device mtu2_1_device = {
170 .name = "sh_mtu2",
171 .id = 1,
172 .dev = {
173 .platform_data = &mtu2_1_platform_data,
174 },
175 .resource = mtu2_1_resources,
176 .num_resources = ARRAY_SIZE(mtu2_1_resources),
177};
178
179static struct sh_timer_config mtu2_2_platform_data = {
180 .name = "MTU2_2",
181 .channel_offset = 0x80,
182 .timer_bit = 2,
183 .clk = "peripheral_clk",
184 .clockevent_rating = 200,
185};
186
187static struct resource mtu2_2_resources[] = {
188 [0] = {
189 .name = "MTU2_2",
190 .start = 0xff801000,
191 .end = 0xff80100a,
192 .flags = IORESOURCE_MEM,
193 },
194 [1] = {
195 .start = 240,
196 .flags = IORESOURCE_IRQ,
197 },
198};
199
200static struct platform_device mtu2_2_device = {
201 .name = "sh_mtu2",
202 .id = 2,
203 .dev = {
204 .platform_data = &mtu2_2_platform_data,
205 },
206 .resource = mtu2_2_resources,
207 .num_resources = ARRAY_SIZE(mtu2_2_resources),
208};
209
116static struct plat_sci_port sci_platform_data[] = { 210static struct plat_sci_port sci_platform_data[] = {
117 { 211 {
118 .mapbase = 0xff804000, 212 .mapbase = 0xff804000,
@@ -134,6 +228,9 @@ static struct platform_device sci_device = {
134 228
135static struct platform_device *mxg_devices[] __initdata = { 229static struct platform_device *mxg_devices[] __initdata = {
136 &sci_device, 230 &sci_device,
231 &mtu2_0_device,
232 &mtu2_1_device,
233 &mtu2_2_device,
137}; 234};
138 235
139static int __init mxg_devices_setup(void) 236static int __init mxg_devices_setup(void)
@@ -147,3 +244,15 @@ void __init plat_irq_setup(void)
147{ 244{
148 register_intc_controller(&intc_desc); 245 register_intc_controller(&intc_desc);
149} 246}
247
248static struct platform_device *mxg_early_devices[] __initdata = {
249 &mtu2_0_device,
250 &mtu2_1_device,
251 &mtu2_2_device,
252};
253
254void __init plat_early_device_setup(void)
255{
256 early_platform_add_devices(mxg_early_devices,
257 ARRAY_SIZE(mxg_early_devices));
258}
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
index 00f42f9e3f5c..d8febe128066 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7201.c
@@ -12,6 +12,8 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/serial.h> 13#include <linux/serial.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16#include <linux/io.h>
15 17
16enum { 18enum {
17 UNUSED = 0, 19 UNUSED = 0,
@@ -249,9 +251,105 @@ static struct platform_device rtc_device = {
249 .resource = rtc_resources, 251 .resource = rtc_resources,
250}; 252};
251 253
254static struct sh_timer_config mtu2_0_platform_data = {
255 .name = "MTU2_0",
256 .channel_offset = -0x80,
257 .timer_bit = 0,
258 .clk = "peripheral_clk",
259 .clockevent_rating = 200,
260};
261
262static struct resource mtu2_0_resources[] = {
263 [0] = {
264 .name = "MTU2_0",
265 .start = 0xfffe4300,
266 .end = 0xfffe4326,
267 .flags = IORESOURCE_MEM,
268 },
269 [1] = {
270 .start = 108,
271 .flags = IORESOURCE_IRQ,
272 },
273};
274
275static struct platform_device mtu2_0_device = {
276 .name = "sh_mtu2",
277 .id = 0,
278 .dev = {
279 .platform_data = &mtu2_0_platform_data,
280 },
281 .resource = mtu2_0_resources,
282 .num_resources = ARRAY_SIZE(mtu2_0_resources),
283};
284
285static struct sh_timer_config mtu2_1_platform_data = {
286 .name = "MTU2_1",
287 .channel_offset = -0x100,
288 .timer_bit = 1,
289 .clk = "peripheral_clk",
290 .clockevent_rating = 200,
291};
292
293static struct resource mtu2_1_resources[] = {
294 [0] = {
295 .name = "MTU2_1",
296 .start = 0xfffe4380,
297 .end = 0xfffe4390,
298 .flags = IORESOURCE_MEM,
299 },
300 [1] = {
301 .start = 116,
302 .flags = IORESOURCE_IRQ,
303 },
304};
305
306static struct platform_device mtu2_1_device = {
307 .name = "sh_mtu2",
308 .id = 1,
309 .dev = {
310 .platform_data = &mtu2_1_platform_data,
311 },
312 .resource = mtu2_1_resources,
313 .num_resources = ARRAY_SIZE(mtu2_1_resources),
314};
315
316static struct sh_timer_config mtu2_2_platform_data = {
317 .name = "MTU2_2",
318 .channel_offset = 0x80,
319 .timer_bit = 2,
320 .clk = "peripheral_clk",
321 .clockevent_rating = 200,
322};
323
324static struct resource mtu2_2_resources[] = {
325 [0] = {
326 .name = "MTU2_2",
327 .start = 0xfffe4000,
328 .end = 0xfffe400a,
329 .flags = IORESOURCE_MEM,
330 },
331 [1] = {
332 .start = 124,
333 .flags = IORESOURCE_IRQ,
334 },
335};
336
337static struct platform_device mtu2_2_device = {
338 .name = "sh_mtu2",
339 .id = 2,
340 .dev = {
341 .platform_data = &mtu2_2_platform_data,
342 },
343 .resource = mtu2_2_resources,
344 .num_resources = ARRAY_SIZE(mtu2_2_resources),
345};
346
252static struct platform_device *sh7201_devices[] __initdata = { 347static struct platform_device *sh7201_devices[] __initdata = {
253 &sci_device, 348 &sci_device,
254 &rtc_device, 349 &rtc_device,
350 &mtu2_0_device,
351 &mtu2_1_device,
352 &mtu2_2_device,
255}; 353};
256 354
257static int __init sh7201_devices_setup(void) 355static int __init sh7201_devices_setup(void)
@@ -265,3 +363,20 @@ void __init plat_irq_setup(void)
265{ 363{
266 register_intc_controller(&intc_desc); 364 register_intc_controller(&intc_desc);
267} 365}
366
367static struct platform_device *sh7201_early_devices[] __initdata = {
368 &mtu2_0_device,
369 &mtu2_1_device,
370 &mtu2_2_device,
371};
372
373#define STBCR3 0xfffe0408
374
375void __init plat_early_device_setup(void)
376{
377 /* enable MTU2 clock */
378 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
379
380 early_platform_add_devices(sh7201_early_devices,
381 ARRAY_SIZE(sh7201_early_devices));
382}
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
index 820dfb2e8656..62e3039d2398 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7203.c
@@ -11,6 +11,8 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/sh_timer.h>
15#include <linux/io.h>
14 16
15enum { 17enum {
16 UNUSED = 0, 18 UNUSED = 0,
@@ -205,6 +207,132 @@ static struct platform_device sci_device = {
205 }, 207 },
206}; 208};
207 209
210static struct sh_timer_config cmt0_platform_data = {
211 .name = "CMT0",
212 .channel_offset = 0x02,
213 .timer_bit = 0,
214 .clk = "peripheral_clk",
215 .clockevent_rating = 125,
216 .clocksource_rating = 0, /* disabled due to code generation issues */
217};
218
219static struct resource cmt0_resources[] = {
220 [0] = {
221 .name = "CMT0",
222 .start = 0xfffec002,
223 .end = 0xfffec007,
224 .flags = IORESOURCE_MEM,
225 },
226 [1] = {
227 .start = 142,
228 .flags = IORESOURCE_IRQ,
229 },
230};
231
232static struct platform_device cmt0_device = {
233 .name = "sh_cmt",
234 .id = 0,
235 .dev = {
236 .platform_data = &cmt0_platform_data,
237 },
238 .resource = cmt0_resources,
239 .num_resources = ARRAY_SIZE(cmt0_resources),
240};
241
242static struct sh_timer_config cmt1_platform_data = {
243 .name = "CMT1",
244 .channel_offset = 0x08,
245 .timer_bit = 1,
246 .clk = "peripheral_clk",
247 .clockevent_rating = 125,
248 .clocksource_rating = 0, /* disabled due to code generation issues */
249};
250
251static struct resource cmt1_resources[] = {
252 [0] = {
253 .name = "CMT1",
254 .start = 0xfffec008,
255 .end = 0xfffec00d,
256 .flags = IORESOURCE_MEM,
257 },
258 [1] = {
259 .start = 143,
260 .flags = IORESOURCE_IRQ,
261 },
262};
263
264static struct platform_device cmt1_device = {
265 .name = "sh_cmt",
266 .id = 1,
267 .dev = {
268 .platform_data = &cmt1_platform_data,
269 },
270 .resource = cmt1_resources,
271 .num_resources = ARRAY_SIZE(cmt1_resources),
272};
273
274static struct sh_timer_config mtu2_0_platform_data = {
275 .name = "MTU2_0",
276 .channel_offset = -0x80,
277 .timer_bit = 0,
278 .clk = "peripheral_clk",
279 .clockevent_rating = 200,
280};
281
282static struct resource mtu2_0_resources[] = {
283 [0] = {
284 .name = "MTU2_0",
285 .start = 0xfffe4300,
286 .end = 0xfffe4326,
287 .flags = IORESOURCE_MEM,
288 },
289 [1] = {
290 .start = 146,
291 .flags = IORESOURCE_IRQ,
292 },
293};
294
295static struct platform_device mtu2_0_device = {
296 .name = "sh_mtu2",
297 .id = 0,
298 .dev = {
299 .platform_data = &mtu2_0_platform_data,
300 },
301 .resource = mtu2_0_resources,
302 .num_resources = ARRAY_SIZE(mtu2_0_resources),
303};
304
305static struct sh_timer_config mtu2_1_platform_data = {
306 .name = "MTU2_1",
307 .channel_offset = -0x100,
308 .timer_bit = 1,
309 .clk = "peripheral_clk",
310 .clockevent_rating = 200,
311};
312
313static struct resource mtu2_1_resources[] = {
314 [0] = {
315 .name = "MTU2_1",
316 .start = 0xfffe4380,
317 .end = 0xfffe4390,
318 .flags = IORESOURCE_MEM,
319 },
320 [1] = {
321 .start = 153,
322 .flags = IORESOURCE_IRQ,
323 },
324};
325
326static struct platform_device mtu2_1_device = {
327 .name = "sh_mtu2",
328 .id = 1,
329 .dev = {
330 .platform_data = &mtu2_1_platform_data,
331 },
332 .resource = mtu2_1_resources,
333 .num_resources = ARRAY_SIZE(mtu2_1_resources),
334};
335
208static struct resource rtc_resources[] = { 336static struct resource rtc_resources[] = {
209 [0] = { 337 [0] = {
210 .start = 0xffff2000, 338 .start = 0xffff2000,
@@ -227,6 +355,10 @@ static struct platform_device rtc_device = {
227 355
228static struct platform_device *sh7203_devices[] __initdata = { 356static struct platform_device *sh7203_devices[] __initdata = {
229 &sci_device, 357 &sci_device,
358 &cmt0_device,
359 &cmt1_device,
360 &mtu2_0_device,
361 &mtu2_1_device,
230 &rtc_device, 362 &rtc_device,
231}; 363};
232 364
@@ -241,3 +373,25 @@ void __init plat_irq_setup(void)
241{ 373{
242 register_intc_controller(&intc_desc); 374 register_intc_controller(&intc_desc);
243} 375}
376
377static struct platform_device *sh7203_early_devices[] __initdata = {
378 &cmt0_device,
379 &cmt1_device,
380 &mtu2_0_device,
381 &mtu2_1_device,
382};
383
384#define STBCR3 0xfffe0408
385#define STBCR4 0xfffe040c
386
387void __init plat_early_device_setup(void)
388{
389 /* enable CMT clock */
390 __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
391
392 /* enable MTU2 clock */
393 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
394
395 early_platform_add_devices(sh7203_early_devices,
396 ARRAY_SIZE(sh7203_early_devices));
397}
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
index c46a8355726d..3e6f3d7a58be 100644
--- a/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7206.c
@@ -12,6 +12,8 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/serial.h> 13#include <linux/serial.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16#include <linux/io.h>
15 17
16enum { 18enum {
17 UNUSED = 0, 19 UNUSED = 0,
@@ -165,8 +167,170 @@ static struct platform_device sci_device = {
165 }, 167 },
166}; 168};
167 169
170static struct sh_timer_config cmt0_platform_data = {
171 .name = "CMT0",
172 .channel_offset = 0x02,
173 .timer_bit = 0,
174 .clk = "peripheral_clk",
175 .clockevent_rating = 125,
176 .clocksource_rating = 0, /* disabled due to code generation issues */
177};
178
179static struct resource cmt0_resources[] = {
180 [0] = {
181 .name = "CMT0",
182 .start = 0xfffec002,
183 .end = 0xfffec007,
184 .flags = IORESOURCE_MEM,
185 },
186 [1] = {
187 .start = 140,
188 .flags = IORESOURCE_IRQ,
189 },
190};
191
192static struct platform_device cmt0_device = {
193 .name = "sh_cmt",
194 .id = 0,
195 .dev = {
196 .platform_data = &cmt0_platform_data,
197 },
198 .resource = cmt0_resources,
199 .num_resources = ARRAY_SIZE(cmt0_resources),
200};
201
202static struct sh_timer_config cmt1_platform_data = {
203 .name = "CMT1",
204 .channel_offset = 0x08,
205 .timer_bit = 1,
206 .clk = "peripheral_clk",
207 .clockevent_rating = 125,
208 .clocksource_rating = 0, /* disabled due to code generation issues */
209};
210
211static struct resource cmt1_resources[] = {
212 [0] = {
213 .name = "CMT1",
214 .start = 0xfffec008,
215 .end = 0xfffec00d,
216 .flags = IORESOURCE_MEM,
217 },
218 [1] = {
219 .start = 144,
220 .flags = IORESOURCE_IRQ,
221 },
222};
223
224static struct platform_device cmt1_device = {
225 .name = "sh_cmt",
226 .id = 1,
227 .dev = {
228 .platform_data = &cmt1_platform_data,
229 },
230 .resource = cmt1_resources,
231 .num_resources = ARRAY_SIZE(cmt1_resources),
232};
233
234static struct sh_timer_config mtu2_0_platform_data = {
235 .name = "MTU2_0",
236 .channel_offset = -0x80,
237 .timer_bit = 0,
238 .clk = "peripheral_clk",
239 .clockevent_rating = 200,
240};
241
242static struct resource mtu2_0_resources[] = {
243 [0] = {
244 .name = "MTU2_0",
245 .start = 0xfffe4300,
246 .end = 0xfffe4326,
247 .flags = IORESOURCE_MEM,
248 },
249 [1] = {
250 .start = 156,
251 .flags = IORESOURCE_IRQ,
252 },
253};
254
255static struct platform_device mtu2_0_device = {
256 .name = "sh_mtu2",
257 .id = 0,
258 .dev = {
259 .platform_data = &mtu2_0_platform_data,
260 },
261 .resource = mtu2_0_resources,
262 .num_resources = ARRAY_SIZE(mtu2_0_resources),
263};
264
265static struct sh_timer_config mtu2_1_platform_data = {
266 .name = "MTU2_1",
267 .channel_offset = -0x100,
268 .timer_bit = 1,
269 .clk = "peripheral_clk",
270 .clockevent_rating = 200,
271};
272
273static struct resource mtu2_1_resources[] = {
274 [0] = {
275 .name = "MTU2_1",
276 .start = 0xfffe4380,
277 .end = 0xfffe4390,
278 .flags = IORESOURCE_MEM,
279 },
280 [1] = {
281 .start = 164,
282 .flags = IORESOURCE_IRQ,
283 },
284};
285
286static struct platform_device mtu2_1_device = {
287 .name = "sh_mtu2",
288 .id = 1,
289 .dev = {
290 .platform_data = &mtu2_1_platform_data,
291 },
292 .resource = mtu2_1_resources,
293 .num_resources = ARRAY_SIZE(mtu2_1_resources),
294};
295
296static struct sh_timer_config mtu2_2_platform_data = {
297 .name = "MTU2_2",
298 .channel_offset = 0x80,
299 .timer_bit = 2,
300 .clk = "peripheral_clk",
301 .clockevent_rating = 200,
302};
303
304static struct resource mtu2_2_resources[] = {
305 [0] = {
306 .name = "MTU2_2",
307 .start = 0xfffe4000,
308 .end = 0xfffe400a,
309 .flags = IORESOURCE_MEM,
310 },
311 [1] = {
312 .start = 180,
313 .flags = IORESOURCE_IRQ,
314 },
315};
316
317static struct platform_device mtu2_2_device = {
318 .name = "sh_mtu2",
319 .id = 2,
320 .dev = {
321 .platform_data = &mtu2_2_platform_data,
322 },
323 .resource = mtu2_2_resources,
324 .num_resources = ARRAY_SIZE(mtu2_2_resources),
325};
326
168static struct platform_device *sh7206_devices[] __initdata = { 327static struct platform_device *sh7206_devices[] __initdata = {
169 &sci_device, 328 &sci_device,
329 &cmt0_device,
330 &cmt1_device,
331 &mtu2_0_device,
332 &mtu2_1_device,
333 &mtu2_2_device,
170}; 334};
171 335
172static int __init sh7206_devices_setup(void) 336static int __init sh7206_devices_setup(void)
@@ -180,3 +344,26 @@ void __init plat_irq_setup(void)
180{ 344{
181 register_intc_controller(&intc_desc); 345 register_intc_controller(&intc_desc);
182} 346}
347
348static struct platform_device *sh7206_early_devices[] __initdata = {
349 &cmt0_device,
350 &cmt1_device,
351 &mtu2_0_device,
352 &mtu2_1_device,
353 &mtu2_2_device,
354};
355
356#define STBCR3 0xfffe0408
357#define STBCR4 0xfffe040c
358
359void __init plat_early_device_setup(void)
360{
361 /* enable CMT clock */
362 __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
363
364 /* enable MTU2 clock */
365 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
366
367 early_platform_add_devices(sh7206_early_devices,
368 ARRAY_SIZE(sh7206_early_devices));
369}
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh3.c b/arch/sh/kernel/cpu/sh3/clock-sh3.c
index c3c945958baf..27b8738f0b09 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh3.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh3.c
@@ -38,36 +38,36 @@ static struct clk_ops sh3_master_clk_ops = {
38 .init = master_clk_init, 38 .init = master_clk_init,
39}; 39};
40 40
41static void module_clk_recalc(struct clk *clk) 41static unsigned long module_clk_recalc(struct clk *clk)
42{ 42{
43 int frqcr = ctrl_inw(FRQCR); 43 int frqcr = ctrl_inw(FRQCR);
44 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 44 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
45 45
46 clk->rate = clk->parent->rate / pfc_divisors[idx]; 46 return clk->parent->rate / pfc_divisors[idx];
47} 47}
48 48
49static struct clk_ops sh3_module_clk_ops = { 49static struct clk_ops sh3_module_clk_ops = {
50 .recalc = module_clk_recalc, 50 .recalc = module_clk_recalc,
51}; 51};
52 52
53static void bus_clk_recalc(struct clk *clk) 53static unsigned long bus_clk_recalc(struct clk *clk)
54{ 54{
55 int frqcr = ctrl_inw(FRQCR); 55 int frqcr = ctrl_inw(FRQCR);
56 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4); 56 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
57 57
58 clk->rate = clk->parent->rate / stc_multipliers[idx]; 58 return clk->parent->rate / stc_multipliers[idx];
59} 59}
60 60
61static struct clk_ops sh3_bus_clk_ops = { 61static struct clk_ops sh3_bus_clk_ops = {
62 .recalc = bus_clk_recalc, 62 .recalc = bus_clk_recalc,
63}; 63};
64 64
65static void cpu_clk_recalc(struct clk *clk) 65static unsigned long cpu_clk_recalc(struct clk *clk)
66{ 66{
67 int frqcr = ctrl_inw(FRQCR); 67 int frqcr = ctrl_inw(FRQCR);
68 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); 68 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
69 69
70 clk->rate = clk->parent->rate / ifc_divisors[idx]; 70 return clk->parent->rate / ifc_divisors[idx];
71} 71}
72 72
73static struct clk_ops sh3_cpu_clk_ops = { 73static struct clk_ops sh3_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7705.c b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
index dfdbf3277fd7..0ca8f2c3646c 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
@@ -39,30 +39,30 @@ static struct clk_ops sh7705_master_clk_ops = {
39 .init = master_clk_init, 39 .init = master_clk_init,
40}; 40};
41 41
42static void module_clk_recalc(struct clk *clk) 42static unsigned long module_clk_recalc(struct clk *clk)
43{ 43{
44 int idx = ctrl_inw(FRQCR) & 0x0003; 44 int idx = ctrl_inw(FRQCR) & 0x0003;
45 clk->rate = clk->parent->rate / pfc_divisors[idx]; 45 return clk->parent->rate / pfc_divisors[idx];
46} 46}
47 47
48static struct clk_ops sh7705_module_clk_ops = { 48static struct clk_ops sh7705_module_clk_ops = {
49 .recalc = module_clk_recalc, 49 .recalc = module_clk_recalc,
50}; 50};
51 51
52static void bus_clk_recalc(struct clk *clk) 52static unsigned long bus_clk_recalc(struct clk *clk)
53{ 53{
54 int idx = (ctrl_inw(FRQCR) & 0x0300) >> 8; 54 int idx = (ctrl_inw(FRQCR) & 0x0300) >> 8;
55 clk->rate = clk->parent->rate / stc_multipliers[idx]; 55 return clk->parent->rate / stc_multipliers[idx];
56} 56}
57 57
58static struct clk_ops sh7705_bus_clk_ops = { 58static struct clk_ops sh7705_bus_clk_ops = {
59 .recalc = bus_clk_recalc, 59 .recalc = bus_clk_recalc,
60}; 60};
61 61
62static void cpu_clk_recalc(struct clk *clk) 62static unsigned long cpu_clk_recalc(struct clk *clk)
63{ 63{
64 int idx = (ctrl_inw(FRQCR) & 0x0030) >> 4; 64 int idx = (ctrl_inw(FRQCR) & 0x0030) >> 4;
65 clk->rate = clk->parent->rate / ifc_divisors[idx]; 65 return clk->parent->rate / ifc_divisors[idx];
66} 66}
67 67
68static struct clk_ops sh7705_cpu_clk_ops = { 68static struct clk_ops sh7705_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7706.c b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
index 0cf96f9833bc..4bf7887d310a 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7706.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
@@ -34,36 +34,36 @@ static struct clk_ops sh7706_master_clk_ops = {
34 .init = master_clk_init, 34 .init = master_clk_init,
35}; 35};
36 36
37static void module_clk_recalc(struct clk *clk) 37static unsigned long module_clk_recalc(struct clk *clk)
38{ 38{
39 int frqcr = ctrl_inw(FRQCR); 39 int frqcr = ctrl_inw(FRQCR);
40 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 40 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
41 41
42 clk->rate = clk->parent->rate / pfc_divisors[idx]; 42 return clk->parent->rate / pfc_divisors[idx];
43} 43}
44 44
45static struct clk_ops sh7706_module_clk_ops = { 45static struct clk_ops sh7706_module_clk_ops = {
46 .recalc = module_clk_recalc, 46 .recalc = module_clk_recalc,
47}; 47};
48 48
49static void bus_clk_recalc(struct clk *clk) 49static unsigned long bus_clk_recalc(struct clk *clk)
50{ 50{
51 int frqcr = ctrl_inw(FRQCR); 51 int frqcr = ctrl_inw(FRQCR);
52 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4); 52 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
53 53
54 clk->rate = clk->parent->rate / stc_multipliers[idx]; 54 return clk->parent->rate / stc_multipliers[idx];
55} 55}
56 56
57static struct clk_ops sh7706_bus_clk_ops = { 57static struct clk_ops sh7706_bus_clk_ops = {
58 .recalc = bus_clk_recalc, 58 .recalc = bus_clk_recalc,
59}; 59};
60 60
61static void cpu_clk_recalc(struct clk *clk) 61static unsigned long cpu_clk_recalc(struct clk *clk)
62{ 62{
63 int frqcr = ctrl_inw(FRQCR); 63 int frqcr = ctrl_inw(FRQCR);
64 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); 64 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
65 65
66 clk->rate = clk->parent->rate / ifc_divisors[idx]; 66 return clk->parent->rate / ifc_divisors[idx];
67} 67}
68 68
69static struct clk_ops sh7706_cpu_clk_ops = { 69static struct clk_ops sh7706_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7709.c b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
index b791a29fdb62..fa30b6017730 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7709.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
@@ -41,12 +41,12 @@ static struct clk_ops sh7709_master_clk_ops = {
41 .init = master_clk_init, 41 .init = master_clk_init,
42}; 42};
43 43
44static void module_clk_recalc(struct clk *clk) 44static unsigned long module_clk_recalc(struct clk *clk)
45{ 45{
46 int frqcr = ctrl_inw(FRQCR); 46 int frqcr = ctrl_inw(FRQCR);
47 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 47 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
48 48
49 clk->rate = clk->parent->rate / pfc_divisors[idx]; 49 return clk->parent->rate / pfc_divisors[idx];
50} 50}
51 51
52static struct clk_ops sh7709_module_clk_ops = { 52static struct clk_ops sh7709_module_clk_ops = {
@@ -56,25 +56,25 @@ static struct clk_ops sh7709_module_clk_ops = {
56 .recalc = module_clk_recalc, 56 .recalc = module_clk_recalc,
57}; 57};
58 58
59static void bus_clk_recalc(struct clk *clk) 59static unsigned long bus_clk_recalc(struct clk *clk)
60{ 60{
61 int frqcr = ctrl_inw(FRQCR); 61 int frqcr = ctrl_inw(FRQCR);
62 int idx = (frqcr & 0x0080) ? 62 int idx = (frqcr & 0x0080) ?
63 ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4) : 1; 63 ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4) : 1;
64 64
65 clk->rate = clk->parent->rate * stc_multipliers[idx]; 65 return clk->parent->rate * stc_multipliers[idx];
66} 66}
67 67
68static struct clk_ops sh7709_bus_clk_ops = { 68static struct clk_ops sh7709_bus_clk_ops = {
69 .recalc = bus_clk_recalc, 69 .recalc = bus_clk_recalc,
70}; 70};
71 71
72static void cpu_clk_recalc(struct clk *clk) 72static unsigned long cpu_clk_recalc(struct clk *clk)
73{ 73{
74 int frqcr = ctrl_inw(FRQCR); 74 int frqcr = ctrl_inw(FRQCR);
75 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); 75 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
76 76
77 clk->rate = clk->parent->rate / ifc_divisors[idx]; 77 return clk->parent->rate / ifc_divisors[idx];
78} 78}
79 79
80static struct clk_ops sh7709_cpu_clk_ops = { 80static struct clk_ops sh7709_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7710.c b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
index 4744c50ec449..030a58ba18a5 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
@@ -33,30 +33,30 @@ static struct clk_ops sh7710_master_clk_ops = {
33 .init = master_clk_init, 33 .init = master_clk_init,
34}; 34};
35 35
36static void module_clk_recalc(struct clk *clk) 36static unsigned long module_clk_recalc(struct clk *clk)
37{ 37{
38 int idx = (ctrl_inw(FRQCR) & 0x0007); 38 int idx = (ctrl_inw(FRQCR) & 0x0007);
39 clk->rate = clk->parent->rate / md_table[idx]; 39 return clk->parent->rate / md_table[idx];
40} 40}
41 41
42static struct clk_ops sh7710_module_clk_ops = { 42static struct clk_ops sh7710_module_clk_ops = {
43 .recalc = module_clk_recalc, 43 .recalc = module_clk_recalc,
44}; 44};
45 45
46static void bus_clk_recalc(struct clk *clk) 46static unsigned long bus_clk_recalc(struct clk *clk)
47{ 47{
48 int idx = (ctrl_inw(FRQCR) & 0x0700) >> 8; 48 int idx = (ctrl_inw(FRQCR) & 0x0700) >> 8;
49 clk->rate = clk->parent->rate / md_table[idx]; 49 return clk->parent->rate / md_table[idx];
50} 50}
51 51
52static struct clk_ops sh7710_bus_clk_ops = { 52static struct clk_ops sh7710_bus_clk_ops = {
53 .recalc = bus_clk_recalc, 53 .recalc = bus_clk_recalc,
54}; 54};
55 55
56static void cpu_clk_recalc(struct clk *clk) 56static unsigned long cpu_clk_recalc(struct clk *clk)
57{ 57{
58 int idx = (ctrl_inw(FRQCR) & 0x0070) >> 4; 58 int idx = (ctrl_inw(FRQCR) & 0x0070) >> 4;
59 clk->rate = clk->parent->rate / md_table[idx]; 59 return clk->parent->rate / md_table[idx];
60} 60}
61 61
62static struct clk_ops sh7710_cpu_clk_ops = { 62static struct clk_ops sh7710_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7712.c b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
index 54f54df51ef0..6428ee6c77ed 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7712.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
@@ -33,24 +33,24 @@ static struct clk_ops sh7712_master_clk_ops = {
33 .init = master_clk_init, 33 .init = master_clk_init,
34}; 34};
35 35
36static void module_clk_recalc(struct clk *clk) 36static unsigned long module_clk_recalc(struct clk *clk)
37{ 37{
38 int frqcr = ctrl_inw(FRQCR); 38 int frqcr = ctrl_inw(FRQCR);
39 int idx = frqcr & 0x0007; 39 int idx = frqcr & 0x0007;
40 40
41 clk->rate = clk->parent->rate / divisors[idx]; 41 return clk->parent->rate / divisors[idx];
42} 42}
43 43
44static struct clk_ops sh7712_module_clk_ops = { 44static struct clk_ops sh7712_module_clk_ops = {
45 .recalc = module_clk_recalc, 45 .recalc = module_clk_recalc,
46}; 46};
47 47
48static void cpu_clk_recalc(struct clk *clk) 48static unsigned long cpu_clk_recalc(struct clk *clk)
49{ 49{
50 int frqcr = ctrl_inw(FRQCR); 50 int frqcr = ctrl_inw(FRQCR);
51 int idx = (frqcr & 0x0030) >> 4; 51 int idx = (frqcr & 0x0030) >> 4;
52 52
53 clk->rate = clk->parent->rate / divisors[idx]; 53 return clk->parent->rate / divisors[idx];
54} 54}
55 55
56static struct clk_ops sh7712_cpu_clk_ops = { 56static struct clk_ops sh7712_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index 63b67badd67e..88f742fed9ed 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -13,6 +13,7 @@
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/serial.h> 14#include <linux/serial.h>
15#include <linux/serial_sci.h> 15#include <linux/serial_sci.h>
16#include <linux/sh_timer.h>
16#include <asm/rtc.h> 17#include <asm/rtc.h>
17 18
18enum { 19enum {
@@ -116,7 +117,102 @@ static struct platform_device rtc_device = {
116 }, 117 },
117}; 118};
118 119
120static struct sh_timer_config tmu0_platform_data = {
121 .name = "TMU0",
122 .channel_offset = 0x02,
123 .timer_bit = 0,
124 .clk = "peripheral_clk",
125 .clockevent_rating = 200,
126};
127
128static struct resource tmu0_resources[] = {
129 [0] = {
130 .name = "TMU0",
131 .start = 0xfffffe94,
132 .end = 0xfffffe9f,
133 .flags = IORESOURCE_MEM,
134 },
135 [1] = {
136 .start = 16,
137 .flags = IORESOURCE_IRQ,
138 },
139};
140
141static struct platform_device tmu0_device = {
142 .name = "sh_tmu",
143 .id = 0,
144 .dev = {
145 .platform_data = &tmu0_platform_data,
146 },
147 .resource = tmu0_resources,
148 .num_resources = ARRAY_SIZE(tmu0_resources),
149};
150
151static struct sh_timer_config tmu1_platform_data = {
152 .name = "TMU1",
153 .channel_offset = 0xe,
154 .timer_bit = 1,
155 .clk = "peripheral_clk",
156 .clocksource_rating = 200,
157};
158
159static struct resource tmu1_resources[] = {
160 [0] = {
161 .name = "TMU1",
162 .start = 0xfffffea0,
163 .end = 0xfffffeab,
164 .flags = IORESOURCE_MEM,
165 },
166 [1] = {
167 .start = 17,
168 .flags = IORESOURCE_IRQ,
169 },
170};
171
172static struct platform_device tmu1_device = {
173 .name = "sh_tmu",
174 .id = 1,
175 .dev = {
176 .platform_data = &tmu1_platform_data,
177 },
178 .resource = tmu1_resources,
179 .num_resources = ARRAY_SIZE(tmu1_resources),
180};
181
182static struct sh_timer_config tmu2_platform_data = {
183 .name = "TMU2",
184 .channel_offset = 0x1a,
185 .timer_bit = 2,
186 .clk = "peripheral_clk",
187};
188
189static struct resource tmu2_resources[] = {
190 [0] = {
191 .name = "TMU2",
192 .start = 0xfffffeac,
193 .end = 0xfffffebb,
194 .flags = IORESOURCE_MEM,
195 },
196 [1] = {
197 .start = 18,
198 .flags = IORESOURCE_IRQ,
199 },
200};
201
202static struct platform_device tmu2_device = {
203 .name = "sh_tmu",
204 .id = 2,
205 .dev = {
206 .platform_data = &tmu2_platform_data,
207 },
208 .resource = tmu2_resources,
209 .num_resources = ARRAY_SIZE(tmu2_resources),
210};
211
119static struct platform_device *sh7705_devices[] __initdata = { 212static struct platform_device *sh7705_devices[] __initdata = {
213 &tmu0_device,
214 &tmu1_device,
215 &tmu2_device,
120 &sci_device, 216 &sci_device,
121 &rtc_device, 217 &rtc_device,
122}; 218};
@@ -128,6 +224,18 @@ static int __init sh7705_devices_setup(void)
128} 224}
129__initcall(sh7705_devices_setup); 225__initcall(sh7705_devices_setup);
130 226
227static struct platform_device *sh7705_early_devices[] __initdata = {
228 &tmu0_device,
229 &tmu1_device,
230 &tmu2_device,
231};
232
233void __init plat_early_device_setup(void)
234{
235 early_platform_add_devices(sh7705_early_devices,
236 ARRAY_SIZE(sh7705_early_devices));
237}
238
131void __init plat_irq_setup(void) 239void __init plat_irq_setup(void)
132{ 240{
133 register_intc_controller(&intc_desc); 241 register_intc_controller(&intc_desc);
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index a74f960b5e79..c56306798584 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -18,6 +18,7 @@
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/serial.h> 19#include <linux/serial.h>
20#include <linux/serial_sci.h> 20#include <linux/serial_sci.h>
21#include <linux/sh_timer.h>
21 22
22enum { 23enum {
23 UNUSED = 0, 24 UNUSED = 0,
@@ -144,7 +145,102 @@ static struct platform_device sci_device = {
144 }, 145 },
145}; 146};
146 147
148static struct sh_timer_config tmu0_platform_data = {
149 .name = "TMU0",
150 .channel_offset = 0x02,
151 .timer_bit = 0,
152 .clk = "peripheral_clk",
153 .clockevent_rating = 200,
154};
155
156static struct resource tmu0_resources[] = {
157 [0] = {
158 .name = "TMU0",
159 .start = 0xfffffe94,
160 .end = 0xfffffe9f,
161 .flags = IORESOURCE_MEM,
162 },
163 [1] = {
164 .start = 16,
165 .flags = IORESOURCE_IRQ,
166 },
167};
168
169static struct platform_device tmu0_device = {
170 .name = "sh_tmu",
171 .id = 0,
172 .dev = {
173 .platform_data = &tmu0_platform_data,
174 },
175 .resource = tmu0_resources,
176 .num_resources = ARRAY_SIZE(tmu0_resources),
177};
178
179static struct sh_timer_config tmu1_platform_data = {
180 .name = "TMU1",
181 .channel_offset = 0xe,
182 .timer_bit = 1,
183 .clk = "peripheral_clk",
184 .clocksource_rating = 200,
185};
186
187static struct resource tmu1_resources[] = {
188 [0] = {
189 .name = "TMU1",
190 .start = 0xfffffea0,
191 .end = 0xfffffeab,
192 .flags = IORESOURCE_MEM,
193 },
194 [1] = {
195 .start = 17,
196 .flags = IORESOURCE_IRQ,
197 },
198};
199
200static struct platform_device tmu1_device = {
201 .name = "sh_tmu",
202 .id = 1,
203 .dev = {
204 .platform_data = &tmu1_platform_data,
205 },
206 .resource = tmu1_resources,
207 .num_resources = ARRAY_SIZE(tmu1_resources),
208};
209
210static struct sh_timer_config tmu2_platform_data = {
211 .name = "TMU2",
212 .channel_offset = 0x1a,
213 .timer_bit = 2,
214 .clk = "peripheral_clk",
215};
216
217static struct resource tmu2_resources[] = {
218 [0] = {
219 .name = "TMU2",
220 .start = 0xfffffeac,
221 .end = 0xfffffebb,
222 .flags = IORESOURCE_MEM,
223 },
224 [1] = {
225 .start = 18,
226 .flags = IORESOURCE_IRQ,
227 },
228};
229
230static struct platform_device tmu2_device = {
231 .name = "sh_tmu",
232 .id = 2,
233 .dev = {
234 .platform_data = &tmu2_platform_data,
235 },
236 .resource = tmu2_resources,
237 .num_resources = ARRAY_SIZE(tmu2_resources),
238};
239
147static struct platform_device *sh770x_devices[] __initdata = { 240static struct platform_device *sh770x_devices[] __initdata = {
241 &tmu0_device,
242 &tmu1_device,
243 &tmu2_device,
148 &sci_device, 244 &sci_device,
149 &rtc_device, 245 &rtc_device,
150}; 246};
@@ -156,6 +252,18 @@ static int __init sh770x_devices_setup(void)
156} 252}
157__initcall(sh770x_devices_setup); 253__initcall(sh770x_devices_setup);
158 254
255static struct platform_device *sh770x_early_devices[] __initdata = {
256 &tmu0_device,
257 &tmu1_device,
258 &tmu2_device,
259};
260
261void __init plat_early_device_setup(void)
262{
263 early_platform_add_devices(sh770x_early_devices,
264 ARRAY_SIZE(sh770x_early_devices));
265}
266
159void __init plat_irq_setup(void) 267void __init plat_irq_setup(void)
160{ 268{
161 register_intc_controller(&intc_desc); 269 register_intc_controller(&intc_desc);
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
index 335098b66e2f..efa76c8148f4 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c
@@ -13,6 +13,7 @@
13#include <linux/irq.h> 13#include <linux/irq.h>
14#include <linux/serial.h> 14#include <linux/serial.h>
15#include <linux/serial_sci.h> 15#include <linux/serial_sci.h>
16#include <linux/sh_timer.h>
16#include <asm/rtc.h> 17#include <asm/rtc.h>
17 18
18enum { 19enum {
@@ -120,7 +121,102 @@ static struct platform_device sci_device = {
120 }, 121 },
121}; 122};
122 123
124static struct sh_timer_config tmu0_platform_data = {
125 .name = "TMU0",
126 .channel_offset = 0x02,
127 .timer_bit = 0,
128 .clk = "peripheral_clk",
129 .clockevent_rating = 200,
130};
131
132static struct resource tmu0_resources[] = {
133 [0] = {
134 .name = "TMU0",
135 .start = 0xa412fe94,
136 .end = 0xa412fe9f,
137 .flags = IORESOURCE_MEM,
138 },
139 [1] = {
140 .start = 16,
141 .flags = IORESOURCE_IRQ,
142 },
143};
144
145static struct platform_device tmu0_device = {
146 .name = "sh_tmu",
147 .id = 0,
148 .dev = {
149 .platform_data = &tmu0_platform_data,
150 },
151 .resource = tmu0_resources,
152 .num_resources = ARRAY_SIZE(tmu0_resources),
153};
154
155static struct sh_timer_config tmu1_platform_data = {
156 .name = "TMU1",
157 .channel_offset = 0xe,
158 .timer_bit = 1,
159 .clk = "peripheral_clk",
160 .clocksource_rating = 200,
161};
162
163static struct resource tmu1_resources[] = {
164 [0] = {
165 .name = "TMU1",
166 .start = 0xa412fea0,
167 .end = 0xa412feab,
168 .flags = IORESOURCE_MEM,
169 },
170 [1] = {
171 .start = 17,
172 .flags = IORESOURCE_IRQ,
173 },
174};
175
176static struct platform_device tmu1_device = {
177 .name = "sh_tmu",
178 .id = 1,
179 .dev = {
180 .platform_data = &tmu1_platform_data,
181 },
182 .resource = tmu1_resources,
183 .num_resources = ARRAY_SIZE(tmu1_resources),
184};
185
186static struct sh_timer_config tmu2_platform_data = {
187 .name = "TMU2",
188 .channel_offset = 0x1a,
189 .timer_bit = 2,
190 .clk = "peripheral_clk",
191};
192
193static struct resource tmu2_resources[] = {
194 [0] = {
195 .name = "TMU2",
196 .start = 0xa412feac,
197 .end = 0xa412feb5,
198 .flags = IORESOURCE_MEM,
199 },
200 [1] = {
201 .start = 18,
202 .flags = IORESOURCE_IRQ,
203 },
204};
205
206static struct platform_device tmu2_device = {
207 .name = "sh_tmu",
208 .id = 2,
209 .dev = {
210 .platform_data = &tmu2_platform_data,
211 },
212 .resource = tmu2_resources,
213 .num_resources = ARRAY_SIZE(tmu2_resources),
214};
215
123static struct platform_device *sh7710_devices[] __initdata = { 216static struct platform_device *sh7710_devices[] __initdata = {
217 &tmu0_device,
218 &tmu1_device,
219 &tmu2_device,
124 &sci_device, 220 &sci_device,
125 &rtc_device, 221 &rtc_device,
126}; 222};
@@ -132,6 +228,18 @@ static int __init sh7710_devices_setup(void)
132} 228}
133__initcall(sh7710_devices_setup); 229__initcall(sh7710_devices_setup);
134 230
231static struct platform_device *sh7710_early_devices[] __initdata = {
232 &tmu0_device,
233 &tmu1_device,
234 &tmu2_device,
235};
236
237void __init plat_early_device_setup(void)
238{
239 early_platform_add_devices(sh7710_early_devices,
240 ARRAY_SIZE(sh7710_early_devices));
241}
242
135void __init plat_irq_setup(void) 243void __init plat_irq_setup(void)
136{ 244{
137 register_intc_controller(&intc_desc); 245 register_intc_controller(&intc_desc);
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 003874a2fd2a..5b2107798edb 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -18,6 +18,7 @@
18#include <linux/serial.h> 18#include <linux/serial.h>
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/serial_sci.h> 20#include <linux/serial_sci.h>
21#include <linux/sh_timer.h>
21#include <asm/rtc.h> 22#include <asm/rtc.h>
22 23
23static struct resource rtc_resources[] = { 24static struct resource rtc_resources[] = {
@@ -123,7 +124,259 @@ static struct platform_device usbf_device = {
123 .resource = usbf_resources, 124 .resource = usbf_resources,
124}; 125};
125 126
127static struct sh_timer_config cmt0_platform_data = {
128 .name = "CMT0",
129 .channel_offset = 0x10,
130 .timer_bit = 0,
131 .clk = "peripheral_clk",
132 .clockevent_rating = 125,
133 .clocksource_rating = 125,
134};
135
136static struct resource cmt0_resources[] = {
137 [0] = {
138 .name = "CMT0",
139 .start = 0x044a0010,
140 .end = 0x044a001b,
141 .flags = IORESOURCE_MEM,
142 },
143 [1] = {
144 .start = 104,
145 .flags = IORESOURCE_IRQ,
146 },
147};
148
149static struct platform_device cmt0_device = {
150 .name = "sh_cmt",
151 .id = 0,
152 .dev = {
153 .platform_data = &cmt0_platform_data,
154 },
155 .resource = cmt0_resources,
156 .num_resources = ARRAY_SIZE(cmt0_resources),
157};
158
159static struct sh_timer_config cmt1_platform_data = {
160 .name = "CMT1",
161 .channel_offset = 0x20,
162 .timer_bit = 1,
163 .clk = "peripheral_clk",
164};
165
166static struct resource cmt1_resources[] = {
167 [0] = {
168 .name = "CMT1",
169 .start = 0x044a0020,
170 .end = 0x044a002b,
171 .flags = IORESOURCE_MEM,
172 },
173 [1] = {
174 .start = 104,
175 .flags = IORESOURCE_IRQ,
176 },
177};
178
179static struct platform_device cmt1_device = {
180 .name = "sh_cmt",
181 .id = 1,
182 .dev = {
183 .platform_data = &cmt1_platform_data,
184 },
185 .resource = cmt1_resources,
186 .num_resources = ARRAY_SIZE(cmt1_resources),
187};
188
189static struct sh_timer_config cmt2_platform_data = {
190 .name = "CMT2",
191 .channel_offset = 0x30,
192 .timer_bit = 2,
193 .clk = "peripheral_clk",
194};
195
196static struct resource cmt2_resources[] = {
197 [0] = {
198 .name = "CMT2",
199 .start = 0x044a0030,
200 .end = 0x044a003b,
201 .flags = IORESOURCE_MEM,
202 },
203 [1] = {
204 .start = 104,
205 .flags = IORESOURCE_IRQ,
206 },
207};
208
209static struct platform_device cmt2_device = {
210 .name = "sh_cmt",
211 .id = 2,
212 .dev = {
213 .platform_data = &cmt2_platform_data,
214 },
215 .resource = cmt2_resources,
216 .num_resources = ARRAY_SIZE(cmt2_resources),
217};
218
219static struct sh_timer_config cmt3_platform_data = {
220 .name = "CMT3",
221 .channel_offset = 0x40,
222 .timer_bit = 3,
223 .clk = "peripheral_clk",
224};
225
226static struct resource cmt3_resources[] = {
227 [0] = {
228 .name = "CMT3",
229 .start = 0x044a0040,
230 .end = 0x044a004b,
231 .flags = IORESOURCE_MEM,
232 },
233 [1] = {
234 .start = 104,
235 .flags = IORESOURCE_IRQ,
236 },
237};
238
239static struct platform_device cmt3_device = {
240 .name = "sh_cmt",
241 .id = 3,
242 .dev = {
243 .platform_data = &cmt3_platform_data,
244 },
245 .resource = cmt3_resources,
246 .num_resources = ARRAY_SIZE(cmt3_resources),
247};
248
249static struct sh_timer_config cmt4_platform_data = {
250 .name = "CMT4",
251 .channel_offset = 0x50,
252 .timer_bit = 4,
253 .clk = "peripheral_clk",
254};
255
256static struct resource cmt4_resources[] = {
257 [0] = {
258 .name = "CMT4",
259 .start = 0x044a0050,
260 .end = 0x044a005b,
261 .flags = IORESOURCE_MEM,
262 },
263 [1] = {
264 .start = 104,
265 .flags = IORESOURCE_IRQ,
266 },
267};
268
269static struct platform_device cmt4_device = {
270 .name = "sh_cmt",
271 .id = 4,
272 .dev = {
273 .platform_data = &cmt4_platform_data,
274 },
275 .resource = cmt4_resources,
276 .num_resources = ARRAY_SIZE(cmt4_resources),
277};
278
279static struct sh_timer_config tmu0_platform_data = {
280 .name = "TMU0",
281 .channel_offset = 0x02,
282 .timer_bit = 0,
283 .clk = "peripheral_clk",
284 .clockevent_rating = 200,
285};
286
287static struct resource tmu0_resources[] = {
288 [0] = {
289 .name = "TMU0",
290 .start = 0xa412fe94,
291 .end = 0xa412fe9f,
292 .flags = IORESOURCE_MEM,
293 },
294 [1] = {
295 .start = 16,
296 .flags = IORESOURCE_IRQ,
297 },
298};
299
300static struct platform_device tmu0_device = {
301 .name = "sh_tmu",
302 .id = 0,
303 .dev = {
304 .platform_data = &tmu0_platform_data,
305 },
306 .resource = tmu0_resources,
307 .num_resources = ARRAY_SIZE(tmu0_resources),
308};
309
310static struct sh_timer_config tmu1_platform_data = {
311 .name = "TMU1",
312 .channel_offset = 0xe,
313 .timer_bit = 1,
314 .clk = "peripheral_clk",
315 .clocksource_rating = 200,
316};
317
318static struct resource tmu1_resources[] = {
319 [0] = {
320 .name = "TMU1",
321 .start = 0xa412fea0,
322 .end = 0xa412feab,
323 .flags = IORESOURCE_MEM,
324 },
325 [1] = {
326 .start = 17,
327 .flags = IORESOURCE_IRQ,
328 },
329};
330
331static struct platform_device tmu1_device = {
332 .name = "sh_tmu",
333 .id = 1,
334 .dev = {
335 .platform_data = &tmu1_platform_data,
336 },
337 .resource = tmu1_resources,
338 .num_resources = ARRAY_SIZE(tmu1_resources),
339};
340
341static struct sh_timer_config tmu2_platform_data = {
342 .name = "TMU2",
343 .channel_offset = 0x1a,
344 .timer_bit = 2,
345 .clk = "peripheral_clk",
346};
347
348static struct resource tmu2_resources[] = {
349 [0] = {
350 .name = "TMU2",
351 .start = 0xa412feac,
352 .end = 0xa412feb5,
353 .flags = IORESOURCE_MEM,
354 },
355 [1] = {
356 .start = 18,
357 .flags = IORESOURCE_IRQ,
358 },
359};
360
361static struct platform_device tmu2_device = {
362 .name = "sh_tmu",
363 .id = 2,
364 .dev = {
365 .platform_data = &tmu2_platform_data,
366 },
367 .resource = tmu2_resources,
368 .num_resources = ARRAY_SIZE(tmu2_resources),
369};
370
126static struct platform_device *sh7720_devices[] __initdata = { 371static struct platform_device *sh7720_devices[] __initdata = {
372 &cmt0_device,
373 &cmt1_device,
374 &cmt2_device,
375 &cmt3_device,
376 &cmt4_device,
377 &tmu0_device,
378 &tmu1_device,
379 &tmu2_device,
127 &rtc_device, 380 &rtc_device,
128 &sci_device, 381 &sci_device,
129 &usb_ohci_device, 382 &usb_ohci_device,
@@ -137,6 +390,23 @@ static int __init sh7720_devices_setup(void)
137} 390}
138__initcall(sh7720_devices_setup); 391__initcall(sh7720_devices_setup);
139 392
393static struct platform_device *sh7720_early_devices[] __initdata = {
394 &cmt0_device,
395 &cmt1_device,
396 &cmt2_device,
397 &cmt3_device,
398 &cmt4_device,
399 &tmu0_device,
400 &tmu1_device,
401 &tmu2_device,
402};
403
404void __init plat_early_device_setup(void)
405{
406 early_platform_add_devices(sh7720_early_devices,
407 ARRAY_SIZE(sh7720_early_devices));
408}
409
140enum { 410enum {
141 UNUSED = 0, 411 UNUSED = 0,
142 412
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index a33429463e96..21421e34e7d5 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -21,10 +21,10 @@
21static int frqcr3_divisors[] = { 1, 2, 3, 4, 6, 8, 16 }; 21static int frqcr3_divisors[] = { 1, 2, 3, 4, 6, 8, 16 };
22static int frqcr3_values[] = { 0, 1, 2, 3, 4, 5, 6 }; 22static int frqcr3_values[] = { 0, 1, 2, 3, 4, 5, 6 };
23 23
24static void emi_clk_recalc(struct clk *clk) 24static unsigned long emi_clk_recalc(struct clk *clk)
25{ 25{
26 int idx = ctrl_inl(CPG2_FRQCR3) & 0x0007; 26 int idx = ctrl_inl(CPG2_FRQCR3) & 0x0007;
27 clk->rate = clk->parent->rate / frqcr3_divisors[idx]; 27 return clk->parent->rate / frqcr3_divisors[idx];
28} 28}
29 29
30static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) 30static inline int frqcr3_lookup(struct clk *clk, unsigned long rate)
@@ -46,14 +46,14 @@ static struct clk_ops sh4202_emi_clk_ops = {
46 46
47static struct clk sh4202_emi_clk = { 47static struct clk sh4202_emi_clk = {
48 .name = "emi_clk", 48 .name = "emi_clk",
49 .flags = CLK_ALWAYS_ENABLED, 49 .flags = CLK_ENABLE_ON_INIT,
50 .ops = &sh4202_emi_clk_ops, 50 .ops = &sh4202_emi_clk_ops,
51}; 51};
52 52
53static void femi_clk_recalc(struct clk *clk) 53static unsigned long femi_clk_recalc(struct clk *clk)
54{ 54{
55 int idx = (ctrl_inl(CPG2_FRQCR3) >> 3) & 0x0007; 55 int idx = (ctrl_inl(CPG2_FRQCR3) >> 3) & 0x0007;
56 clk->rate = clk->parent->rate / frqcr3_divisors[idx]; 56 return clk->parent->rate / frqcr3_divisors[idx];
57} 57}
58 58
59static struct clk_ops sh4202_femi_clk_ops = { 59static struct clk_ops sh4202_femi_clk_ops = {
@@ -62,7 +62,7 @@ static struct clk_ops sh4202_femi_clk_ops = {
62 62
63static struct clk sh4202_femi_clk = { 63static struct clk sh4202_femi_clk = {
64 .name = "femi_clk", 64 .name = "femi_clk",
65 .flags = CLK_ALWAYS_ENABLED, 65 .flags = CLK_ENABLE_ON_INIT,
66 .ops = &sh4202_femi_clk_ops, 66 .ops = &sh4202_femi_clk_ops,
67}; 67};
68 68
@@ -90,10 +90,10 @@ static void shoc_clk_init(struct clk *clk)
90 WARN_ON(i == ARRAY_SIZE(frqcr3_divisors)); /* Undefined clock */ 90 WARN_ON(i == ARRAY_SIZE(frqcr3_divisors)); /* Undefined clock */
91} 91}
92 92
93static void shoc_clk_recalc(struct clk *clk) 93static unsigned long shoc_clk_recalc(struct clk *clk)
94{ 94{
95 int idx = (ctrl_inl(CPG2_FRQCR3) >> 6) & 0x0007; 95 int idx = (ctrl_inl(CPG2_FRQCR3) >> 6) & 0x0007;
96 clk->rate = clk->parent->rate / frqcr3_divisors[idx]; 96 return clk->parent->rate / frqcr3_divisors[idx];
97} 97}
98 98
99static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate) 99static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate)
@@ -140,7 +140,7 @@ static struct clk_ops sh4202_shoc_clk_ops = {
140 140
141static struct clk sh4202_shoc_clk = { 141static struct clk sh4202_shoc_clk = {
142 .name = "shoc_clk", 142 .name = "shoc_clk",
143 .flags = CLK_ALWAYS_ENABLED, 143 .flags = CLK_ENABLE_ON_INIT,
144 .ops = &sh4202_shoc_clk_ops, 144 .ops = &sh4202_shoc_clk_ops,
145}; 145};
146 146
@@ -150,31 +150,22 @@ static struct clk *sh4202_onchip_clocks[] = {
150 &sh4202_shoc_clk, 150 &sh4202_shoc_clk,
151}; 151};
152 152
153static int __init sh4202_clk_init(void) 153int __init arch_clk_init(void)
154{ 154{
155 struct clk *clk = clk_get(NULL, "master_clk"); 155 struct clk *clk;
156 int i; 156 int i, ret = 0;
157
158 cpg_clk_init();
157 159
160 clk = clk_get(NULL, "master_clk");
158 for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) { 161 for (i = 0; i < ARRAY_SIZE(sh4202_onchip_clocks); i++) {
159 struct clk *clkp = sh4202_onchip_clocks[i]; 162 struct clk *clkp = sh4202_onchip_clocks[i];
160 163
161 clkp->parent = clk; 164 clkp->parent = clk;
162 clk_register(clkp); 165 ret |= clk_register(clkp);
163 clk_enable(clkp);
164 } 166 }
165 167
166 /*
167 * Now that we have the rest of the clocks registered, we need to
168 * force the parent clock to propagate so that these clocks will
169 * automatically figure out their rate. We cheat by handing the
170 * parent clock its current rate and forcing child propagation.
171 */
172 clk_set_rate(clk, clk_get_rate(clk));
173
174 clk_put(clk); 168 clk_put(clk);
175 169
176 return 0; 170 return ret;
177} 171}
178
179arch_initcall(sh4202_clk_init);
180
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4.c b/arch/sh/kernel/cpu/sh4/clock-sh4.c
index dca9f87a12d6..73294d9cd049 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4.c
@@ -35,30 +35,30 @@ static struct clk_ops sh4_master_clk_ops = {
35 .init = master_clk_init, 35 .init = master_clk_init,
36}; 36};
37 37
38static void module_clk_recalc(struct clk *clk) 38static unsigned long module_clk_recalc(struct clk *clk)
39{ 39{
40 int idx = (ctrl_inw(FRQCR) & 0x0007); 40 int idx = (ctrl_inw(FRQCR) & 0x0007);
41 clk->rate = clk->parent->rate / pfc_divisors[idx]; 41 return clk->parent->rate / pfc_divisors[idx];
42} 42}
43 43
44static struct clk_ops sh4_module_clk_ops = { 44static struct clk_ops sh4_module_clk_ops = {
45 .recalc = module_clk_recalc, 45 .recalc = module_clk_recalc,
46}; 46};
47 47
48static void bus_clk_recalc(struct clk *clk) 48static unsigned long bus_clk_recalc(struct clk *clk)
49{ 49{
50 int idx = (ctrl_inw(FRQCR) >> 3) & 0x0007; 50 int idx = (ctrl_inw(FRQCR) >> 3) & 0x0007;
51 clk->rate = clk->parent->rate / bfc_divisors[idx]; 51 return clk->parent->rate / bfc_divisors[idx];
52} 52}
53 53
54static struct clk_ops sh4_bus_clk_ops = { 54static struct clk_ops sh4_bus_clk_ops = {
55 .recalc = bus_clk_recalc, 55 .recalc = bus_clk_recalc,
56}; 56};
57 57
58static void cpu_clk_recalc(struct clk *clk) 58static unsigned long cpu_clk_recalc(struct clk *clk)
59{ 59{
60 int idx = (ctrl_inw(FRQCR) >> 6) & 0x0007; 60 int idx = (ctrl_inw(FRQCR) >> 6) & 0x0007;
61 clk->rate = clk->parent->rate / ifc_divisors[idx]; 61 return clk->parent->rate / ifc_divisors[idx];
62} 62}
63 63
64static struct clk_ops sh4_cpu_clk_ops = { 64static struct clk_ops sh4_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 91e3677ae09d..6c78d0a9c857 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -60,12 +60,18 @@ int __init detect_cpu_and_cache_system(void)
60 if ((cvr & 0x10000000) == 0) 60 if ((cvr & 0x10000000) == 0)
61 boot_cpu_data.flags |= CPU_HAS_DSP; 61 boot_cpu_data.flags |= CPU_HAS_DSP;
62 62
63 boot_cpu_data.flags |= CPU_HAS_LLSC; 63 boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER;
64 boot_cpu_data.cut_major = pvr & 0x7f; 64 boot_cpu_data.cut_major = pvr & 0x7f;
65
66 boot_cpu_data.icache.ways = 4;
67 boot_cpu_data.dcache.ways = 4;
68 } else {
69 /* And some SH-4 defaults.. */
70 boot_cpu_data.flags |= CPU_HAS_PTEA;
65 } 71 }
66 72
67 /* FPU detection works for everyone */ 73 /* FPU detection works for everyone */
68 if ((cvr & 0x20000000) == 1) 74 if ((cvr & 0x20000000))
69 boot_cpu_data.flags |= CPU_HAS_FPU; 75 boot_cpu_data.flags |= CPU_HAS_FPU;
70 76
71 /* Mask off the upper chip ID */ 77 /* Mask off the upper chip ID */
@@ -78,25 +84,20 @@ int __init detect_cpu_and_cache_system(void)
78 switch (pvr) { 84 switch (pvr) {
79 case 0x205: 85 case 0x205:
80 boot_cpu_data.type = CPU_SH7750; 86 boot_cpu_data.type = CPU_SH7750;
81 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | 87 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG |
82 CPU_HAS_PERF_COUNTER; 88 CPU_HAS_PERF_COUNTER;
83 break; 89 break;
84 case 0x206: 90 case 0x206:
85 boot_cpu_data.type = CPU_SH7750S; 91 boot_cpu_data.type = CPU_SH7750S;
86 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | 92 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG |
87 CPU_HAS_PERF_COUNTER; 93 CPU_HAS_PERF_COUNTER;
88 break; 94 break;
89 case 0x1100: 95 case 0x1100:
90 boot_cpu_data.type = CPU_SH7751; 96 boot_cpu_data.type = CPU_SH7751;
91 boot_cpu_data.flags |= CPU_HAS_FPU;
92 break; 97 break;
93 case 0x2001: 98 case 0x2001:
94 case 0x2004: 99 case 0x2004:
95 boot_cpu_data.type = CPU_SH7770; 100 boot_cpu_data.type = CPU_SH7770;
96 boot_cpu_data.icache.ways = 4;
97 boot_cpu_data.dcache.ways = 4;
98
99 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
100 break; 101 break;
101 case 0x2006: 102 case 0x2006:
102 case 0x200A: 103 case 0x200A:
@@ -107,45 +108,26 @@ int __init detect_cpu_and_cache_system(void)
107 else 108 else
108 boot_cpu_data.type = CPU_SH7780; 109 boot_cpu_data.type = CPU_SH7780;
109 110
110 boot_cpu_data.icache.ways = 4;
111 boot_cpu_data.dcache.ways = 4;
112
113 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
114 CPU_HAS_LLSC;
115 break; 111 break;
116 case 0x3000: 112 case 0x3000:
117 case 0x3003: 113 case 0x3003:
118 case 0x3009: 114 case 0x3009:
119 boot_cpu_data.type = CPU_SH7343; 115 boot_cpu_data.type = CPU_SH7343;
120 boot_cpu_data.icache.ways = 4;
121 boot_cpu_data.dcache.ways = 4;
122 boot_cpu_data.flags |= CPU_HAS_LLSC;
123 break; 116 break;
124 case 0x3004: 117 case 0x3004:
125 case 0x3007: 118 case 0x3007:
126 boot_cpu_data.type = CPU_SH7785; 119 boot_cpu_data.type = CPU_SH7785;
127 boot_cpu_data.icache.ways = 4;
128 boot_cpu_data.dcache.ways = 4;
129 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
130 CPU_HAS_LLSC;
131 break; 120 break;
132 case 0x4004: 121 case 0x4004:
133 boot_cpu_data.type = CPU_SH7786; 122 boot_cpu_data.type = CPU_SH7786;
134 boot_cpu_data.icache.ways = 4; 123 boot_cpu_data.flags |= CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE;
135 boot_cpu_data.dcache.ways = 4;
136 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
137 CPU_HAS_LLSC | CPU_HAS_PTEAEX;
138 break; 124 break;
139 case 0x3008: 125 case 0x3008:
140 boot_cpu_data.icache.ways = 4;
141 boot_cpu_data.dcache.ways = 4;
142 boot_cpu_data.flags |= CPU_HAS_LLSC;
143
144 switch (prr) { 126 switch (prr) {
145 case 0x50: 127 case 0x50:
146 case 0x51: 128 case 0x51:
147 boot_cpu_data.type = CPU_SH7723; 129 boot_cpu_data.type = CPU_SH7723;
148 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_L2_CACHE; 130 boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
149 break; 131 break;
150 case 0x70: 132 case 0x70:
151 boot_cpu_data.type = CPU_SH7366; 133 boot_cpu_data.type = CPU_SH7366;
@@ -156,13 +138,13 @@ int __init detect_cpu_and_cache_system(void)
156 break; 138 break;
157 } 139 }
158 break; 140 break;
141 case 0x300b:
142 boot_cpu_data.type = CPU_SH7724;
143 boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
144 break;
159 case 0x4000: /* 1st cut */ 145 case 0x4000: /* 1st cut */
160 case 0x4001: /* 2nd cut */ 146 case 0x4001: /* 2nd cut */
161 boot_cpu_data.type = CPU_SHX3; 147 boot_cpu_data.type = CPU_SHX3;
162 boot_cpu_data.icache.ways = 4;
163 boot_cpu_data.dcache.ways = 4;
164 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
165 CPU_HAS_LLSC;
166 break; 148 break;
167 case 0x700: 149 case 0x700:
168 boot_cpu_data.type = CPU_SH4_501; 150 boot_cpu_data.type = CPU_SH4_501;
@@ -173,7 +155,6 @@ int __init detect_cpu_and_cache_system(void)
173 boot_cpu_data.type = CPU_SH4_202; 155 boot_cpu_data.type = CPU_SH4_202;
174 boot_cpu_data.icache.ways = 2; 156 boot_cpu_data.icache.ways = 2;
175 boot_cpu_data.dcache.ways = 2; 157 boot_cpu_data.dcache.ways = 2;
176 boot_cpu_data.flags |= CPU_HAS_FPU;
177 break; 158 break;
178 case 0x500 ... 0x501: 159 case 0x500 ... 0x501:
179 switch (prr) { 160 switch (prr) {
@@ -191,18 +172,12 @@ int __init detect_cpu_and_cache_system(void)
191 boot_cpu_data.icache.ways = 2; 172 boot_cpu_data.icache.ways = 2;
192 boot_cpu_data.dcache.ways = 2; 173 boot_cpu_data.dcache.ways = 2;
193 174
194 boot_cpu_data.flags |= CPU_HAS_FPU;
195
196 break; 175 break;
197 default: 176 default:
198 boot_cpu_data.type = CPU_SH_NONE; 177 boot_cpu_data.type = CPU_SH_NONE;
199 break; 178 break;
200 } 179 }
201 180
202#ifdef CONFIG_CPU_HAS_PTEA
203 boot_cpu_data.flags |= CPU_HAS_PTEA;
204#endif
205
206 /* 181 /*
207 * On anything that's not a direct-mapped cache, look to the CVR 182 * On anything that's not a direct-mapped cache, look to the CVR
208 * for I/D-cache specifics. 183 * for I/D-cache specifics.
@@ -222,43 +197,48 @@ int __init detect_cpu_and_cache_system(void)
222 } 197 }
223 198
224 /* 199 /*
225 * Setup the L2 cache desc
226 *
227 * SH-4A's have an optional PIPT L2. 200 * SH-4A's have an optional PIPT L2.
228 */ 201 */
229 if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) { 202 if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
230 /* Bug if we can't decode the L2 info */
231 BUG_ON(!(cvr & 0xf));
232
233 /* Silicon and specifications have clearly never met.. */
234 cvr ^= 0xf;
235
236 /* 203 /*
237 * Size calculation is much more sensible 204 * Verify that it really has something hooked up, this
238 * than it is for the L1. 205 * is the safety net for CPUs that have optional L2
239 * 206 * support yet do not implement it.
240 * Sizes are 128KB, 258KB, 512KB, and 1MB.
241 */ 207 */
242 size = (cvr & 0xf) << 17; 208 if ((cvr & 0xf) == 0)
243 209 boot_cpu_data.flags &= ~CPU_HAS_L2_CACHE;
244 BUG_ON(!size); 210 else {
245 211 /*
246 boot_cpu_data.scache.way_incr = (1 << 16); 212 * Silicon and specifications have clearly never
247 boot_cpu_data.scache.entry_shift = 5; 213 * met..
248 boot_cpu_data.scache.ways = 4; 214 */
249 boot_cpu_data.scache.linesz = L1_CACHE_BYTES; 215 cvr ^= 0xf;
250 216
251 boot_cpu_data.scache.entry_mask = 217 /*
252 (boot_cpu_data.scache.way_incr - 218 * Size calculation is much more sensible
253 boot_cpu_data.scache.linesz); 219 * than it is for the L1.
254 220 *
255 boot_cpu_data.scache.sets = size / 221 * Sizes are 128KB, 258KB, 512KB, and 1MB.
256 (boot_cpu_data.scache.linesz * 222 */
257 boot_cpu_data.scache.ways); 223 size = (cvr & 0xf) << 17;
258 224
259 boot_cpu_data.scache.way_size = 225 boot_cpu_data.scache.way_incr = (1 << 16);
260 (boot_cpu_data.scache.sets * 226 boot_cpu_data.scache.entry_shift = 5;
261 boot_cpu_data.scache.linesz); 227 boot_cpu_data.scache.ways = 4;
228 boot_cpu_data.scache.linesz = L1_CACHE_BYTES;
229
230 boot_cpu_data.scache.entry_mask =
231 (boot_cpu_data.scache.way_incr -
232 boot_cpu_data.scache.linesz);
233
234 boot_cpu_data.scache.sets = size /
235 (boot_cpu_data.scache.linesz *
236 boot_cpu_data.scache.ways);
237
238 boot_cpu_data.scache.way_size =
239 (boot_cpu_data.scache.sets *
240 boot_cpu_data.scache.linesz);
241 }
262 } 242 }
263 243
264 return 0; 244 return 0;
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index 7371abf64f80..6d088d123591 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -2,6 +2,7 @@
2 * SH4-202 Setup 2 * SH4-202 Setup
3 * 3 *
4 * Copyright (C) 2006 Paul Mundt 4 * Copyright (C) 2006 Paul Mundt
5 * Copyright (C) 2009 Magnus Damm
5 * 6 *
6 * This file is subject to the terms and conditions of the GNU General Public 7 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
@@ -11,6 +12,8 @@
11#include <linux/init.h> 12#include <linux/init.h>
12#include <linux/serial.h> 13#include <linux/serial.h>
13#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16#include <linux/io.h>
14 17
15static struct plat_sci_port sci_platform_data[] = { 18static struct plat_sci_port sci_platform_data[] = {
16 { 19 {
@@ -31,8 +34,103 @@ static struct platform_device sci_device = {
31 }, 34 },
32}; 35};
33 36
37static struct sh_timer_config tmu0_platform_data = {
38 .name = "TMU0",
39 .channel_offset = 0x04,
40 .timer_bit = 0,
41 .clk = "peripheral_clk",
42 .clockevent_rating = 200,
43};
44
45static struct resource tmu0_resources[] = {
46 [0] = {
47 .name = "TMU0",
48 .start = 0xffd80008,
49 .end = 0xffd80013,
50 .flags = IORESOURCE_MEM,
51 },
52 [1] = {
53 .start = 16,
54 .flags = IORESOURCE_IRQ,
55 },
56};
57
58static struct platform_device tmu0_device = {
59 .name = "sh_tmu",
60 .id = 0,
61 .dev = {
62 .platform_data = &tmu0_platform_data,
63 },
64 .resource = tmu0_resources,
65 .num_resources = ARRAY_SIZE(tmu0_resources),
66};
67
68static struct sh_timer_config tmu1_platform_data = {
69 .name = "TMU1",
70 .channel_offset = 0x10,
71 .timer_bit = 1,
72 .clk = "peripheral_clk",
73 .clocksource_rating = 200,
74};
75
76static struct resource tmu1_resources[] = {
77 [0] = {
78 .name = "TMU1",
79 .start = 0xffd80014,
80 .end = 0xffd8001f,
81 .flags = IORESOURCE_MEM,
82 },
83 [1] = {
84 .start = 17,
85 .flags = IORESOURCE_IRQ,
86 },
87};
88
89static struct platform_device tmu1_device = {
90 .name = "sh_tmu",
91 .id = 1,
92 .dev = {
93 .platform_data = &tmu1_platform_data,
94 },
95 .resource = tmu1_resources,
96 .num_resources = ARRAY_SIZE(tmu1_resources),
97};
98
99static struct sh_timer_config tmu2_platform_data = {
100 .name = "TMU2",
101 .channel_offset = 0x1c,
102 .timer_bit = 2,
103 .clk = "peripheral_clk",
104};
105
106static struct resource tmu2_resources[] = {
107 [0] = {
108 .name = "TMU2",
109 .start = 0xffd80020,
110 .end = 0xffd8002f,
111 .flags = IORESOURCE_MEM,
112 },
113 [1] = {
114 .start = 18,
115 .flags = IORESOURCE_IRQ,
116 },
117};
118
119static struct platform_device tmu2_device = {
120 .name = "sh_tmu",
121 .id = 2,
122 .dev = {
123 .platform_data = &tmu2_platform_data,
124 },
125 .resource = tmu2_resources,
126 .num_resources = ARRAY_SIZE(tmu2_resources),
127};
128
34static struct platform_device *sh4202_devices[] __initdata = { 129static struct platform_device *sh4202_devices[] __initdata = {
35 &sci_device, 130 &sci_device,
131 &tmu0_device,
132 &tmu1_device,
133 &tmu2_device,
36}; 134};
37 135
38static int __init sh4202_devices_setup(void) 136static int __init sh4202_devices_setup(void)
@@ -42,7 +140,71 @@ static int __init sh4202_devices_setup(void)
42} 140}
43__initcall(sh4202_devices_setup); 141__initcall(sh4202_devices_setup);
44 142
143static struct platform_device *sh4202_early_devices[] __initdata = {
144 &tmu0_device,
145 &tmu1_device,
146 &tmu2_device,
147};
148
149void __init plat_early_device_setup(void)
150{
151 early_platform_add_devices(sh4202_early_devices,
152 ARRAY_SIZE(sh4202_early_devices));
153}
154
155enum {
156 UNUSED = 0,
157
158 /* interrupt sources */
159 IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
160 HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT,
161};
162
163static struct intc_vect vectors[] __initdata = {
164 INTC_VECT(HUDI, 0x600),
165 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
166 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
167 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
168 INTC_VECT(RTC, 0x4c0),
169 INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
170 INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
171 INTC_VECT(WDT, 0x560),
172};
173
174static struct intc_prio_reg prio_registers[] __initdata = {
175 { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
176 { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } },
177 { 0xffd0000c, 0, 16, 4, /* IPRC */ { 0, 0, SCIF, HUDI } },
178 { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
179};
180
181static DECLARE_INTC_DESC(intc_desc, "sh4-202", vectors, NULL,
182 NULL, prio_registers, NULL);
183
184static struct intc_vect vectors_irlm[] __initdata = {
185 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
186 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
187};
188
189static DECLARE_INTC_DESC(intc_desc_irlm, "sh4-202_irlm", vectors_irlm, NULL,
190 NULL, prio_registers, NULL);
191
45void __init plat_irq_setup(void) 192void __init plat_irq_setup(void)
46{ 193{
47 /* do nothing - all IRL interrupts are handled by the board code */ 194 register_intc_controller(&intc_desc);
195}
196
197#define INTC_ICR 0xffd00000UL
198#define INTC_ICR_IRLM (1<<7)
199
200void __init plat_irq_setup_pins(int mode)
201{
202 switch (mode) {
203 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
204 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
205 register_intc_controller(&intc_desc_irlm);
206 break;
207 default:
208 BUG();
209 }
48} 210}
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index a1c80d909cd6..851672d15cf4 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -12,6 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/serial.h> 13#include <linux/serial.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/sh_timer.h>
15#include <linux/serial_sci.h> 16#include <linux/serial_sci.h>
16 17
17static struct resource rtc_resources[] = { 18static struct resource rtc_resources[] = {
@@ -60,9 +61,177 @@ static struct platform_device sci_device = {
60 }, 61 },
61}; 62};
62 63
64static struct sh_timer_config tmu0_platform_data = {
65 .name = "TMU0",
66 .channel_offset = 0x04,
67 .timer_bit = 0,
68 .clk = "peripheral_clk",
69 .clockevent_rating = 200,
70};
71
72static struct resource tmu0_resources[] = {
73 [0] = {
74 .name = "TMU0",
75 .start = 0xffd80008,
76 .end = 0xffd80013,
77 .flags = IORESOURCE_MEM,
78 },
79 [1] = {
80 .start = 16,
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85static struct platform_device tmu0_device = {
86 .name = "sh_tmu",
87 .id = 0,
88 .dev = {
89 .platform_data = &tmu0_platform_data,
90 },
91 .resource = tmu0_resources,
92 .num_resources = ARRAY_SIZE(tmu0_resources),
93};
94
95static struct sh_timer_config tmu1_platform_data = {
96 .name = "TMU1",
97 .channel_offset = 0x10,
98 .timer_bit = 1,
99 .clk = "peripheral_clk",
100 .clocksource_rating = 200,
101};
102
103static struct resource tmu1_resources[] = {
104 [0] = {
105 .name = "TMU1",
106 .start = 0xffd80014,
107 .end = 0xffd8001f,
108 .flags = IORESOURCE_MEM,
109 },
110 [1] = {
111 .start = 17,
112 .flags = IORESOURCE_IRQ,
113 },
114};
115
116static struct platform_device tmu1_device = {
117 .name = "sh_tmu",
118 .id = 1,
119 .dev = {
120 .platform_data = &tmu1_platform_data,
121 },
122 .resource = tmu1_resources,
123 .num_resources = ARRAY_SIZE(tmu1_resources),
124};
125
126static struct sh_timer_config tmu2_platform_data = {
127 .name = "TMU2",
128 .channel_offset = 0x1c,
129 .timer_bit = 2,
130 .clk = "peripheral_clk",
131};
132
133static struct resource tmu2_resources[] = {
134 [0] = {
135 .name = "TMU2",
136 .start = 0xffd80020,
137 .end = 0xffd8002f,
138 .flags = IORESOURCE_MEM,
139 },
140 [1] = {
141 .start = 18,
142 .flags = IORESOURCE_IRQ,
143 },
144};
145
146static struct platform_device tmu2_device = {
147 .name = "sh_tmu",
148 .id = 2,
149 .dev = {
150 .platform_data = &tmu2_platform_data,
151 },
152 .resource = tmu2_resources,
153 .num_resources = ARRAY_SIZE(tmu2_resources),
154};
155
156/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
157#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
158 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
159 defined(CONFIG_CPU_SUBTYPE_SH7751R)
160
161static struct sh_timer_config tmu3_platform_data = {
162 .name = "TMU3",
163 .channel_offset = 0x04,
164 .timer_bit = 0,
165 .clk = "peripheral_clk",
166};
167
168static struct resource tmu3_resources[] = {
169 [0] = {
170 .name = "TMU3",
171 .start = 0xfe100008,
172 .end = 0xfe100013,
173 .flags = IORESOURCE_MEM,
174 },
175 [1] = {
176 .start = 72,
177 .flags = IORESOURCE_IRQ,
178 },
179};
180
181static struct platform_device tmu3_device = {
182 .name = "sh_tmu",
183 .id = 3,
184 .dev = {
185 .platform_data = &tmu3_platform_data,
186 },
187 .resource = tmu3_resources,
188 .num_resources = ARRAY_SIZE(tmu3_resources),
189};
190
191static struct sh_timer_config tmu4_platform_data = {
192 .name = "TMU4",
193 .channel_offset = 0x10,
194 .timer_bit = 1,
195 .clk = "peripheral_clk",
196};
197
198static struct resource tmu4_resources[] = {
199 [0] = {
200 .name = "TMU4",
201 .start = 0xfe100014,
202 .end = 0xfe10001f,
203 .flags = IORESOURCE_MEM,
204 },
205 [1] = {
206 .start = 76,
207 .flags = IORESOURCE_IRQ,
208 },
209};
210
211static struct platform_device tmu4_device = {
212 .name = "sh_tmu",
213 .id = 4,
214 .dev = {
215 .platform_data = &tmu4_platform_data,
216 },
217 .resource = tmu4_resources,
218 .num_resources = ARRAY_SIZE(tmu4_resources),
219};
220
221#endif
222
63static struct platform_device *sh7750_devices[] __initdata = { 223static struct platform_device *sh7750_devices[] __initdata = {
64 &rtc_device, 224 &rtc_device,
65 &sci_device, 225 &sci_device,
226 &tmu0_device,
227 &tmu1_device,
228 &tmu2_device,
229#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
230 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
231 defined(CONFIG_CPU_SUBTYPE_SH7751R)
232 &tmu3_device,
233 &tmu4_device,
234#endif
66}; 235};
67 236
68static int __init sh7750_devices_setup(void) 237static int __init sh7750_devices_setup(void)
@@ -72,6 +241,24 @@ static int __init sh7750_devices_setup(void)
72} 241}
73__initcall(sh7750_devices_setup); 242__initcall(sh7750_devices_setup);
74 243
244static struct platform_device *sh7750_early_devices[] __initdata = {
245 &tmu0_device,
246 &tmu1_device,
247 &tmu2_device,
248#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
249 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
250 defined(CONFIG_CPU_SUBTYPE_SH7751R)
251 &tmu3_device,
252 &tmu4_device,
253#endif
254};
255
256void __init plat_early_device_setup(void)
257{
258 early_platform_add_devices(sh7750_early_devices,
259 ARRAY_SIZE(sh7750_early_devices));
260}
261
75enum { 262enum {
76 UNUSED = 0, 263 UNUSED = 0,
77 264
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index d9bdc931ac09..5b822519bd90 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -10,6 +10,7 @@
10#include <linux/platform_device.h> 10#include <linux/platform_device.h>
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/sh_timer.h>
13#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
14#include <linux/io.h> 15#include <linux/io.h>
15 16
@@ -18,10 +19,7 @@ enum {
18 19
19 /* interrupt sources */ 20 /* interrupt sources */
20 IRL0, IRL1, IRL2, IRL3, 21 IRL0, IRL1, IRL2, IRL3,
21 HUDI, GPIOI, 22 HUDI, GPIOI, DMAC,
22 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
23 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
24 DMAC_DMAE,
25 IRQ4, IRQ5, IRQ6, IRQ7, 23 IRQ4, IRQ5, IRQ6, IRQ7,
26 HCAN20, HCAN21, 24 HCAN20, HCAN21,
27 SSI0, SSI1, 25 SSI0, SSI1,
@@ -36,21 +34,20 @@ enum {
36 HSPI, 34 HSPI,
37 MMCIF0, MMCIF1, MMCIF2, MMCIF3, 35 MMCIF0, MMCIF1, MMCIF2, MMCIF3,
38 MFI, ADC, CMT, 36 MFI, ADC, CMT,
39 TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, 37 TMU0, TMU1, TMU2,
40 WDT, 38 WDT, REF,
41 REF_RCMI, REF_ROVI,
42 39
43 /* interrupt groups */ 40 /* interrupt groups */
44 DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF, 41 DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF,
45}; 42};
46 43
47static struct intc_vect vectors[] __initdata = { 44static struct intc_vect vectors[] __initdata = {
48 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), 45 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
49 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), 46 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
50 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), 47 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
51 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), 48 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
52 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), 49 INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
53 INTC_VECT(DMAC_DMAE, 0x6c0), 50 INTC_VECT(DMAC, 0x6c0),
54 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820), 51 INTC_VECT(IRQ4, 0x800), INTC_VECT(IRQ5, 0x820),
55 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860), 52 INTC_VECT(IRQ6, 0x840), INTC_VECT(IRQ6, 0x860),
56 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920), 53 INTC_VECT(HCAN20, 0x900), INTC_VECT(HCAN21, 0x920),
@@ -74,23 +71,18 @@ static struct intc_vect vectors[] __initdata = {
74 INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */ 71 INTC_VECT(MFI, 0xe80), /* 0xf80 according to data sheet */
75 INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0), 72 INTC_VECT(ADC, 0xf80), INTC_VECT(CMT, 0xfa0),
76 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), 73 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
77 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), 74 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
78 INTC_VECT(WDT, 0x560), 75 INTC_VECT(WDT, 0x560),
79 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), 76 INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
80}; 77};
81 78
82static struct intc_group groups[] __initdata = { 79static struct intc_group groups[] __initdata = {
83 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
84 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
85 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
86 INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2), 80 INTC_GROUP(DMABRG, DMABRG0, DMABRG1, DMABRG2),
87 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), 81 INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
88 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), 82 INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
89 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI), 83 INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI),
90 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), 84 INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
91 INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3), 85 INTC_GROUP(MMCIF, MMCIF0, MMCIF1, MMCIF2, MMCIF3),
92 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
93 INTC_GROUP(REF, REF_RCMI, REF_ROVI),
94}; 86};
95 87
96static struct intc_mask_reg mask_registers[] __initdata = { 88static struct intc_mask_reg mask_registers[] __initdata = {
@@ -168,8 +160,104 @@ static struct platform_device sci_device = {
168 }, 160 },
169}; 161};
170 162
163static struct sh_timer_config tmu0_platform_data = {
164 .name = "TMU0",
165 .channel_offset = 0x04,
166 .timer_bit = 0,
167 .clk = "peripheral_clk",
168 .clockevent_rating = 200,
169};
170
171static struct resource tmu0_resources[] = {
172 [0] = {
173 .name = "TMU0",
174 .start = 0xffd80008,
175 .end = 0xffd80013,
176 .flags = IORESOURCE_MEM,
177 },
178 [1] = {
179 .start = 16,
180 .flags = IORESOURCE_IRQ,
181 },
182};
183
184static struct platform_device tmu0_device = {
185 .name = "sh_tmu",
186 .id = 0,
187 .dev = {
188 .platform_data = &tmu0_platform_data,
189 },
190 .resource = tmu0_resources,
191 .num_resources = ARRAY_SIZE(tmu0_resources),
192};
193
194static struct sh_timer_config tmu1_platform_data = {
195 .name = "TMU1",
196 .channel_offset = 0x10,
197 .timer_bit = 1,
198 .clk = "peripheral_clk",
199 .clocksource_rating = 200,
200};
201
202static struct resource tmu1_resources[] = {
203 [0] = {
204 .name = "TMU1",
205 .start = 0xffd80014,
206 .end = 0xffd8001f,
207 .flags = IORESOURCE_MEM,
208 },
209 [1] = {
210 .start = 17,
211 .flags = IORESOURCE_IRQ,
212 },
213};
214
215static struct platform_device tmu1_device = {
216 .name = "sh_tmu",
217 .id = 1,
218 .dev = {
219 .platform_data = &tmu1_platform_data,
220 },
221 .resource = tmu1_resources,
222 .num_resources = ARRAY_SIZE(tmu1_resources),
223};
224
225static struct sh_timer_config tmu2_platform_data = {
226 .name = "TMU2",
227 .channel_offset = 0x1c,
228 .timer_bit = 2,
229 .clk = "peripheral_clk",
230};
231
232static struct resource tmu2_resources[] = {
233 [0] = {
234 .name = "TMU2",
235 .start = 0xffd80020,
236 .end = 0xffd8002f,
237 .flags = IORESOURCE_MEM,
238 },
239 [1] = {
240 .start = 18,
241 .flags = IORESOURCE_IRQ,
242 },
243};
244
245static struct platform_device tmu2_device = {
246 .name = "sh_tmu",
247 .id = 2,
248 .dev = {
249 .platform_data = &tmu2_platform_data,
250 },
251 .resource = tmu2_resources,
252 .num_resources = ARRAY_SIZE(tmu2_resources),
253};
254
255
171static struct platform_device *sh7760_devices[] __initdata = { 256static struct platform_device *sh7760_devices[] __initdata = {
172 &sci_device, 257 &sci_device,
258 &tmu0_device,
259 &tmu1_device,
260 &tmu2_device,
173}; 261};
174 262
175static int __init sh7760_devices_setup(void) 263static int __init sh7760_devices_setup(void)
@@ -179,6 +267,18 @@ static int __init sh7760_devices_setup(void)
179} 267}
180__initcall(sh7760_devices_setup); 268__initcall(sh7760_devices_setup);
181 269
270static struct platform_device *sh7760_early_devices[] __initdata = {
271 &tmu0_device,
272 &tmu1_device,
273 &tmu2_device,
274};
275
276void __init plat_early_device_setup(void)
277{
278 early_platform_add_devices(sh7760_early_devices,
279 ARRAY_SIZE(sh7760_early_devices));
280}
281
182#define INTC_ICR 0xffd00000UL 282#define INTC_ICR 0xffd00000UL
183#define INTC_ICR_IRLM (1 << 7) 283#define INTC_ICR_IRLM (1 << 7)
184 284
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 1a92361feeb9..96ea09ca8cc1 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o
15obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o 16obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o
16 17
@@ -23,15 +24,17 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
23clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o 24clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
24clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o 25clock-$(CONFIG_CPU_SUBTYPE_SH7785) := clock-sh7785.o
25clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o 26clock-$(CONFIG_CPU_SUBTYPE_SH7786) := clock-sh7786.o
26clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7722.o 27clock-$(CONFIG_CPU_SUBTYPE_SH7343) := clock-sh7343.o
27clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o 28clock-$(CONFIG_CPU_SUBTYPE_SH7722) := clock-sh7722.o
28clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7722.o 29clock-$(CONFIG_CPU_SUBTYPE_SH7723) := clock-sh7723.o
29clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7722.o 30clock-$(CONFIG_CPU_SUBTYPE_SH7724) := clock-sh7724.o
31clock-$(CONFIG_CPU_SUBTYPE_SH7366) := clock-sh7366.o
30clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o 32clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
31 33
32# Pinmux setup 34# Pinmux setup
33pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o 35pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
34pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o 36pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
37pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o
35pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o 38pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
36pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o 39pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
37 40
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7343.c b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
new file mode 100644
index 000000000000..0ee3ee861252
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7343.c
@@ -0,0 +1,211 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/clock-sh7343.c
3 *
4 * SH7343 clock framework support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/clock.h>
25
26/* SH7343 registers */
27#define FRQCR 0xa4150000
28#define VCLKCR 0xa4150004
29#define SCLKACR 0xa4150008
30#define SCLKBCR 0xa415000c
31#define PLLCR 0xa4150024
32#define MSTPCR0 0xa4150030
33#define MSTPCR1 0xa4150034
34#define MSTPCR2 0xa4150038
35#define DLLFRQ 0xa4150050
36
37/* Fixed 32 KHz root clock for RTC and Power Management purposes */
38static struct clk r_clk = {
39 .name = "rclk",
40 .id = -1,
41 .rate = 32768,
42};
43
44/*
45 * Default rate for the root input clock, reset this with clk_set_rate()
46 * from the platform code.
47 */
48struct clk extal_clk = {
49 .name = "extal",
50 .id = -1,
51 .rate = 33333333,
52};
53
54/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
55static unsigned long dll_recalc(struct clk *clk)
56{
57 unsigned long mult;
58
59 if (__raw_readl(PLLCR) & 0x1000)
60 mult = __raw_readl(DLLFRQ);
61 else
62 mult = 0;
63
64 return clk->parent->rate * mult;
65}
66
67static struct clk_ops dll_clk_ops = {
68 .recalc = dll_recalc,
69};
70
71static struct clk dll_clk = {
72 .name = "dll_clk",
73 .id = -1,
74 .ops = &dll_clk_ops,
75 .parent = &r_clk,
76 .flags = CLK_ENABLE_ON_INIT,
77};
78
79static unsigned long pll_recalc(struct clk *clk)
80{
81 unsigned long mult = 1;
82
83 if (__raw_readl(PLLCR) & 0x4000)
84 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
85
86 return clk->parent->rate * mult;
87}
88
89static struct clk_ops pll_clk_ops = {
90 .recalc = pll_recalc,
91};
92
93static struct clk pll_clk = {
94 .name = "pll_clk",
95 .id = -1,
96 .ops = &pll_clk_ops,
97 .flags = CLK_ENABLE_ON_INIT,
98};
99
100struct clk *main_clks[] = {
101 &r_clk,
102 &extal_clk,
103 &dll_clk,
104 &pll_clk,
105};
106
107static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
108static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
109
110static struct clk_div_mult_table div4_table = {
111 .divisors = divisors,
112 .nr_divisors = ARRAY_SIZE(divisors),
113 .multipliers = multipliers,
114 .nr_multipliers = ARRAY_SIZE(multipliers),
115};
116
117enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
118 DIV4_SIUA, DIV4_SIUB, DIV4_NR };
119
120#define DIV4(_str, _reg, _bit, _mask, _flags) \
121 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
122
123struct clk div4_clks[DIV4_NR] = {
124 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
125 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
126 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
127 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
128 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
129 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
130 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
131 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
132};
133
134struct clk div6_clks[] = {
135 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
136};
137
138#define MSTP(_str, _parent, _reg, _bit, _flags) \
139 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
140
141static struct clk mstp_clks[] = {
142 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
143 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
144 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
145 MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
146 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
147 MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
148 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
149 MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
150 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
151 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
152 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
153 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
154 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0),
155 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
156 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
157 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
158 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0),
159 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0),
160 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0),
161 MSTP("scif3", &div4_clks[DIV4_P], MSTPCR0, 4, 0),
162 MSTP("sio0", &div4_clks[DIV4_P], MSTPCR0, 3, 0),
163 MSTP("siof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
164 MSTP("siof1", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
165
166 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
167 MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0),
168
169 MSTP("tpu0", &div4_clks[DIV4_P], MSTPCR2, 25, 0),
170 MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
171 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
172 MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
173 MSTP("sim0", &div4_clks[DIV4_P], MSTPCR2, 16, 0),
174 MSTP("keysc0", &r_clk, MSTPCR2, 14, 0),
175 MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 13, 0),
176 MSTP("s3d40", &div4_clks[DIV4_P], MSTPCR2, 12, 0),
177 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
178 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0),
179 MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
180 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
181 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
182 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
183 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
184 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
185 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
186};
187
188int __init arch_clk_init(void)
189{
190 int k, ret = 0;
191
192 /* autodetect extal or dll configuration */
193 if (__raw_readl(PLLCR) & 0x1000)
194 pll_clk.parent = &dll_clk;
195 else
196 pll_clk.parent = &extal_clk;
197
198 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
199 ret = clk_register(main_clks[k]);
200
201 if (!ret)
202 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
203
204 if (!ret)
205 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
206
207 if (!ret)
208 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
209
210 return ret;
211}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7366.c b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
new file mode 100644
index 000000000000..a95ebaba095c
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7366.c
@@ -0,0 +1,211 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/clock-sh7366.c
3 *
4 * SH7366 clock framework support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/clock.h>
25
26/* SH7366 registers */
27#define FRQCR 0xa4150000
28#define VCLKCR 0xa4150004
29#define SCLKACR 0xa4150008
30#define SCLKBCR 0xa415000c
31#define PLLCR 0xa4150024
32#define MSTPCR0 0xa4150030
33#define MSTPCR1 0xa4150034
34#define MSTPCR2 0xa4150038
35#define DLLFRQ 0xa4150050
36
37/* Fixed 32 KHz root clock for RTC and Power Management purposes */
38static struct clk r_clk = {
39 .name = "rclk",
40 .id = -1,
41 .rate = 32768,
42};
43
44/*
45 * Default rate for the root input clock, reset this with clk_set_rate()
46 * from the platform code.
47 */
48struct clk extal_clk = {
49 .name = "extal",
50 .id = -1,
51 .rate = 33333333,
52};
53
54/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
55static unsigned long dll_recalc(struct clk *clk)
56{
57 unsigned long mult;
58
59 if (__raw_readl(PLLCR) & 0x1000)
60 mult = __raw_readl(DLLFRQ);
61 else
62 mult = 0;
63
64 return clk->parent->rate * mult;
65}
66
67static struct clk_ops dll_clk_ops = {
68 .recalc = dll_recalc,
69};
70
71static struct clk dll_clk = {
72 .name = "dll_clk",
73 .id = -1,
74 .ops = &dll_clk_ops,
75 .parent = &r_clk,
76 .flags = CLK_ENABLE_ON_INIT,
77};
78
79static unsigned long pll_recalc(struct clk *clk)
80{
81 unsigned long mult = 1;
82 unsigned long div = 1;
83
84 if (__raw_readl(PLLCR) & 0x4000)
85 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
86 else
87 div = 2;
88
89 return (clk->parent->rate * mult) / div;
90}
91
92static struct clk_ops pll_clk_ops = {
93 .recalc = pll_recalc,
94};
95
96static struct clk pll_clk = {
97 .name = "pll_clk",
98 .id = -1,
99 .ops = &pll_clk_ops,
100 .flags = CLK_ENABLE_ON_INIT,
101};
102
103struct clk *main_clks[] = {
104 &r_clk,
105 &extal_clk,
106 &dll_clk,
107 &pll_clk,
108};
109
110static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
111static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
112
113static struct clk_div_mult_table div4_table = {
114 .divisors = divisors,
115 .nr_divisors = ARRAY_SIZE(divisors),
116 .multipliers = multipliers,
117 .nr_multipliers = ARRAY_SIZE(multipliers),
118};
119
120enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
121 DIV4_SIUA, DIV4_SIUB, DIV4_NR };
122
123#define DIV4(_str, _reg, _bit, _mask, _flags) \
124 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
125
126struct clk div4_clks[DIV4_NR] = {
127 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
128 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
129 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
130 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
131 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
132 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
133 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
134 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
135};
136
137struct clk div6_clks[] = {
138 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
139};
140
141#define MSTP(_str, _parent, _reg, _bit, _flags) \
142 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
143
144static struct clk mstp_clks[] = {
145 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
146 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
147 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
148 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
149 MSTP("rsmem0", &div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
150 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
151 MSTP("intc3", &div4_clks[DIV4_P], MSTPCR0, 23, 0),
152 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 0),
153 MSTP("dmac0", &div4_clks[DIV4_P], MSTPCR0, 21, 0),
154 MSTP("sh0", &div4_clks[DIV4_P], MSTPCR0, 20, 0),
155 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0),
156 MSTP("ubc0", &div4_clks[DIV4_P], MSTPCR0, 17, 0),
157 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
158 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0),
159 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
160 MSTP("mfi0", &div4_clks[DIV4_P], MSTPCR0, 11, 0),
161 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
162 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0),
163 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0),
164 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0),
165 MSTP("msiof0", &div4_clks[DIV4_P], MSTPCR0, 2, 0),
166 MSTP("sbr0", &div4_clks[DIV4_P], MSTPCR0, 1, 0),
167
168 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
169
170 MSTP("icb0", &div4_clks[DIV4_P], MSTPCR2, 27, 0),
171 MSTP("meram0", &div4_clks[DIV4_P], MSTPCR2, 26, 0),
172 MSTP("dacy1", &div4_clks[DIV4_P], MSTPCR2, 24, 0),
173 MSTP("dacy0", &div4_clks[DIV4_P], MSTPCR2, 23, 0),
174 MSTP("tsif0", &div4_clks[DIV4_P], MSTPCR2, 22, 0),
175 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
176 MSTP("mmcif0", &div4_clks[DIV4_P], MSTPCR2, 17, 0),
177 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
178 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0),
179 MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
180 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
181 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
182 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
183 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
184 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
185 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
186};
187
188int __init arch_clk_init(void)
189{
190 int k, ret = 0;
191
192 /* autodetect extal or dll configuration */
193 if (__raw_readl(PLLCR) & 0x1000)
194 pll_clk.parent = &dll_clk;
195 else
196 pll_clk.parent = &extal_clk;
197
198 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
199 ret = clk_register(main_clks[k]);
200
201 if (!ret)
202 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
203
204 if (!ret)
205 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
206
207 if (!ret)
208 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
209
210 return ret;
211}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
index 0e174af21874..40f859354f79 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c
@@ -1,844 +1,197 @@
1/* 1/*
2 * arch/sh/kernel/cpu/sh4a/clock-sh7722.c 2 * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
3 * 3 *
4 * SH7343, SH7722, SH7723 & SH7366 support for the clock framework 4 * SH7722 clock framework support
5 * 5 *
6 * Copyright (c) 2006-2007 Nomad Global Solutions Inc 6 * Copyright (C) 2009 Magnus Damm
7 * Based on code for sh7343 by Paul Mundt
8 * 7 *
9 * This file is subject to the terms and conditions of the GNU General Public 8 * This program is free software; you can redistribute it and/or modify
10 * License. See the file "COPYING" in the main directory of this archive 9 * it under the terms of the GNU General Public License as published by
11 * for more details. 10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
12 */ 20 */
13#include <linux/init.h> 21#include <linux/init.h>
14#include <linux/kernel.h> 22#include <linux/kernel.h>
15#include <linux/io.h> 23#include <linux/io.h>
16#include <linux/errno.h>
17#include <linux/stringify.h>
18#include <asm/clock.h> 24#include <asm/clock.h>
19#include <asm/freq.h>
20
21#define N (-1)
22#define NM (-2)
23#define ROUND_NEAREST 0
24#define ROUND_DOWN -1
25#define ROUND_UP +1
26
27static int adjust_algos[][3] = {
28 {}, /* NO_CHANGE */
29 { NM, N, 1 }, /* N:1, N:1 */
30 { 3, 2, 2 }, /* 3:2:2 */
31 { 5, 2, 2 }, /* 5:2:2 */
32 { N, 1, 1 }, /* N:1:1 */
33
34 { N, 1 }, /* N:1 */
35 25
36 { N, 1 }, /* N:1 */ 26/* SH7722 registers */
37 { 3, 2 }, 27#define FRQCR 0xa4150000
38 { 4, 3 }, 28#define VCLKCR 0xa4150004
39 { 5, 4 }, 29#define SCLKACR 0xa4150008
40 30#define SCLKBCR 0xa415000c
41 { N, 1 } 31#define IRDACLKCR 0xa4150018
32#define PLLCR 0xa4150024
33#define MSTPCR0 0xa4150030
34#define MSTPCR1 0xa4150034
35#define MSTPCR2 0xa4150038
36#define DLLFRQ 0xa4150050
37
38/* Fixed 32 KHz root clock for RTC and Power Management purposes */
39static struct clk r_clk = {
40 .name = "rclk",
41 .id = -1,
42 .rate = 32768,
42}; 43};
43 44
44static unsigned long adjust_pair_of_clocks(unsigned long r1, unsigned long r2,
45 int m1, int m2, int round_flag)
46{
47 unsigned long rem, div;
48 int the_one = 0;
49
50 pr_debug( "Actual values: r1 = %ld\n", r1);
51 pr_debug( "...............r2 = %ld\n", r2);
52
53 if (m1 == m2) {
54 r2 = r1;
55 pr_debug( "setting equal rates: r2 now %ld\n", r2);
56 } else if ((m2 == N && m1 == 1) ||
57 (m2 == NM && m1 == N)) { /* N:1 or NM:N */
58 pr_debug( "Setting rates as 1:N (N:N*M)\n");
59 rem = r2 % r1;
60 pr_debug( "...remainder = %ld\n", rem);
61 if (rem) {
62 div = r2 / r1;
63 pr_debug( "...div = %ld\n", div);
64 switch (round_flag) {
65 case ROUND_NEAREST:
66 the_one = rem >= r1/2 ? 1 : 0; break;
67 case ROUND_UP:
68 the_one = 1; break;
69 case ROUND_DOWN:
70 the_one = 0; break;
71 }
72
73 r2 = r1 * (div + the_one);
74 pr_debug( "...setting r2 to %ld\n", r2);
75 }
76 } else if ((m2 == 1 && m1 == N) ||
77 (m2 == N && m1 == NM)) { /* 1:N or N:NM */
78 pr_debug( "Setting rates as N:1 (N*M:N)\n");
79 rem = r1 % r2;
80 pr_debug( "...remainder = %ld\n", rem);
81 if (rem) {
82 div = r1 / r2;
83 pr_debug( "...div = %ld\n", div);
84 switch (round_flag) {
85 case ROUND_NEAREST:
86 the_one = rem > r2/2 ? 1 : 0; break;
87 case ROUND_UP:
88 the_one = 0; break;
89 case ROUND_DOWN:
90 the_one = 1; break;
91 }
92
93 r2 = r1 / (div + the_one);
94 pr_debug( "...setting r2 to %ld\n", r2);
95 }
96 } else { /* value:value */
97 pr_debug( "Setting rates as %d:%d\n", m1, m2);
98 div = r1 / m1;
99 r2 = div * m2;
100 pr_debug( "...div = %ld\n", div);
101 pr_debug( "...setting r2 to %ld\n", r2);
102 }
103
104 return r2;
105}
106
107static void adjust_clocks(int originate, int *l, unsigned long v[],
108 int n_in_line)
109{
110 int x;
111
112 pr_debug( "Go down from %d...\n", originate);
113 /* go up recalculation clocks */
114 for (x = originate; x>0; x -- )
115 v[x-1] = adjust_pair_of_clocks(v[x], v[x-1],
116 l[x], l[x-1],
117 ROUND_UP);
118
119 pr_debug( "Go up from %d...\n", originate);
120 /* go down recalculation clocks */
121 for (x = originate; x<n_in_line - 1; x ++ )
122 v[x+1] = adjust_pair_of_clocks(v[x], v[x+1],
123 l[x], l[x+1],
124 ROUND_UP);
125}
126
127
128/* 45/*
129 * SH7722 uses a common set of multipliers and divisors, so this 46 * Default rate for the root input clock, reset this with clk_set_rate()
130 * is quite simple.. 47 * from the platform code.
131 */ 48 */
132 49struct clk extal_clk = {
133/* 50 .name = "extal",
134 * Instead of having two separate multipliers/divisors set, like this: 51 .id = -1,
135 * 52 .rate = 33333333,
136 * static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
137 * static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
138 *
139 * I created the divisors2 array, which is used to calculate rate like
140 * rate = parent * 2 / divisors2[ divisor ];
141*/
142static int divisors2[] = { 2, 3, 4, 5, 6, 8, 10, 12, 16, 20, 24, 32, 40 };
143
144static void master_clk_recalc(struct clk *clk)
145{
146 unsigned frqcr = ctrl_inl(FRQCR);
147
148 clk->rate = CONFIG_SH_PCLK_FREQ * (((frqcr >> 24) & 0x1f) + 1);
149}
150
151static void master_clk_init(struct clk *clk)
152{
153 clk->parent = NULL;
154 clk->flags |= CLK_RATE_PROPAGATES;
155 clk->rate = CONFIG_SH_PCLK_FREQ;
156 master_clk_recalc(clk);
157}
158
159
160static void module_clk_recalc(struct clk *clk)
161{
162 unsigned long frqcr = ctrl_inl(FRQCR);
163
164 clk->rate = clk->parent->rate / (((frqcr >> 24) & 0x1f) + 1);
165}
166
167static int master_clk_setrate(struct clk *clk, unsigned long rate, int id)
168{
169 int div = rate / clk->rate;
170 int master_divs[] = { 2, 3, 4, 6, 8, 16 };
171 int index;
172 unsigned long frqcr;
173
174 for (index = 1; index < ARRAY_SIZE(master_divs); index++)
175 if (div >= master_divs[index - 1] && div < master_divs[index])
176 break;
177
178 if (index >= ARRAY_SIZE(master_divs))
179 index = ARRAY_SIZE(master_divs);
180 div = master_divs[index - 1];
181
182 frqcr = ctrl_inl(FRQCR);
183 frqcr &= ~(0xF << 24);
184 frqcr |= ( (div-1) << 24);
185 ctrl_outl(frqcr, FRQCR);
186
187 return 0;
188}
189
190static struct clk_ops sh7722_master_clk_ops = {
191 .init = master_clk_init,
192 .recalc = master_clk_recalc,
193 .set_rate = master_clk_setrate,
194};
195
196static struct clk_ops sh7722_module_clk_ops = {
197 .recalc = module_clk_recalc,
198};
199
200struct frqcr_context {
201 unsigned mask;
202 unsigned shift;
203};
204
205struct frqcr_context sh7722_get_clk_context(const char *name)
206{
207 struct frqcr_context ctx = { 0, };
208
209 if (!strcmp(name, "peripheral_clk")) {
210 ctx.shift = 0;
211 ctx.mask = 0xF;
212 } else if (!strcmp(name, "sdram_clk")) {
213 ctx.shift = 4;
214 ctx.mask = 0xF;
215 } else if (!strcmp(name, "bus_clk")) {
216 ctx.shift = 8;
217 ctx.mask = 0xF;
218 } else if (!strcmp(name, "sh_clk")) {
219 ctx.shift = 12;
220 ctx.mask = 0xF;
221 } else if (!strcmp(name, "umem_clk")) {
222 ctx.shift = 16;
223 ctx.mask = 0xF;
224 } else if (!strcmp(name, "cpu_clk")) {
225 ctx.shift = 20;
226 ctx.mask = 7;
227 }
228 return ctx;
229}
230
231/**
232 * sh7722_find_div_index - find divisor for setting rate
233 *
234 * All sh7722 clocks use the same set of multipliers/divisors. This function
235 * chooses correct divisor to set the rate of clock with parent clock that
236 * generates frequency of 'parent_rate'
237 *
238 * @parent_rate: rate of parent clock
239 * @rate: requested rate to be set
240 */
241static int sh7722_find_div_index(unsigned long parent_rate, unsigned rate)
242{
243 unsigned div2 = parent_rate * 2 / rate;
244 int index;
245
246 if (rate > parent_rate)
247 return -EINVAL;
248
249 for (index = 1; index < ARRAY_SIZE(divisors2); index++) {
250 if (div2 > divisors2[index - 1] && div2 <= divisors2[index])
251 break;
252 }
253 if (index >= ARRAY_SIZE(divisors2))
254 index = ARRAY_SIZE(divisors2) - 1;
255 return index;
256}
257
258static void sh7722_frqcr_recalc(struct clk *clk)
259{
260 struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
261 unsigned long frqcr = ctrl_inl(FRQCR);
262 int index;
263
264 index = (frqcr >> ctx.shift) & ctx.mask;
265 clk->rate = clk->parent->rate * 2 / divisors2[index];
266}
267
268static int sh7722_frqcr_set_rate(struct clk *clk, unsigned long rate,
269 int algo_id)
270{
271 struct frqcr_context ctx = sh7722_get_clk_context(clk->name);
272 unsigned long parent_rate = clk->parent->rate;
273 int div;
274 unsigned long frqcr;
275 int err = 0;
276
277 /* pretty invalid */
278 if (parent_rate < rate)
279 return -EINVAL;
280
281 /* look for multiplier/divisor pair */
282 div = sh7722_find_div_index(parent_rate, rate);
283 if (div<0)
284 return div;
285
286 /* calculate new value of clock rate */
287 clk->rate = parent_rate * 2 / divisors2[div];
288 frqcr = ctrl_inl(FRQCR);
289
290 /* FIXME: adjust as algo_id specifies */
291 if (algo_id != NO_CHANGE) {
292 int originator;
293 char *algo_group_1[] = { "cpu_clk", "umem_clk", "sh_clk" };
294 char *algo_group_2[] = { "sh_clk", "bus_clk" };
295 char *algo_group_3[] = { "sh_clk", "sdram_clk" };
296 char *algo_group_4[] = { "bus_clk", "peripheral_clk" };
297 char *algo_group_5[] = { "cpu_clk", "peripheral_clk" };
298 char **algo_current = NULL;
299 /* 3 is the maximum number of clocks in relation */
300 struct clk *ck[3];
301 unsigned long values[3]; /* the same comment as above */
302 int part_length = -1;
303 int i;
304
305 /*
306 * all the steps below only required if adjustion was
307 * requested
308 */
309 if (algo_id == IUS_N1_N1 ||
310 algo_id == IUS_322 ||
311 algo_id == IUS_522 ||
312 algo_id == IUS_N11) {
313 algo_current = algo_group_1;
314 part_length = 3;
315 }
316 if (algo_id == SB_N1) {
317 algo_current = algo_group_2;
318 part_length = 2;
319 }
320 if (algo_id == SB3_N1 ||
321 algo_id == SB3_32 ||
322 algo_id == SB3_43 ||
323 algo_id == SB3_54) {
324 algo_current = algo_group_3;
325 part_length = 2;
326 }
327 if (algo_id == BP_N1) {
328 algo_current = algo_group_4;
329 part_length = 2;
330 }
331 if (algo_id == IP_N1) {
332 algo_current = algo_group_5;
333 part_length = 2;
334 }
335 if (!algo_current)
336 goto incorrect_algo_id;
337
338 originator = -1;
339 for (i = 0; i < part_length; i ++ ) {
340 if (originator >= 0 && !strcmp(clk->name,
341 algo_current[i]))
342 originator = i;
343 ck[i] = clk_get(NULL, algo_current[i]);
344 values[i] = clk_get_rate(ck[i]);
345 }
346
347 if (originator >= 0)
348 adjust_clocks(originator, adjust_algos[algo_id],
349 values, part_length);
350
351 for (i = 0; i < part_length; i ++ ) {
352 struct frqcr_context part_ctx;
353 int part_div;
354
355 if (likely(!err)) {
356 part_div = sh7722_find_div_index(parent_rate,
357 rate);
358 if (part_div > 0) {
359 part_ctx = sh7722_get_clk_context(
360 ck[i]->name);
361 frqcr &= ~(part_ctx.mask <<
362 part_ctx.shift);
363 frqcr |= part_div << part_ctx.shift;
364 } else
365 err = part_div;
366 }
367
368 ck[i]->ops->recalc(ck[i]);
369 clk_put(ck[i]);
370 }
371 }
372
373 /* was there any error during recalculation ? If so, bail out.. */
374 if (unlikely(err!=0))
375 goto out_err;
376
377 /* clear FRQCR bits */
378 frqcr &= ~(ctx.mask << ctx.shift);
379 frqcr |= div << ctx.shift;
380
381 /* ...and perform actual change */
382 ctrl_outl(frqcr, FRQCR);
383 return 0;
384
385incorrect_algo_id:
386 return -EINVAL;
387out_err:
388 return err;
389}
390
391static long sh7722_frqcr_round_rate(struct clk *clk, unsigned long rate)
392{
393 unsigned long parent_rate = clk->parent->rate;
394 int div;
395
396 /* look for multiplier/divisor pair */
397 div = sh7722_find_div_index(parent_rate, rate);
398 if (div < 0)
399 return clk->rate;
400
401 /* calculate new value of clock rate */
402 return parent_rate * 2 / divisors2[div];
403}
404
405static struct clk_ops sh7722_frqcr_clk_ops = {
406 .recalc = sh7722_frqcr_recalc,
407 .set_rate = sh7722_frqcr_set_rate,
408 .round_rate = sh7722_frqcr_round_rate,
409}; 53};
410 54
411/* 55/* The dll block multiplies the 32khz r_clk, may be used instead of extal */
412 * clock ops methods for SIU A/B and IrDA clock 56static unsigned long dll_recalc(struct clk *clk)
413 *
414 */
415
416#ifndef CONFIG_CPU_SUBTYPE_SH7343
417
418static int sh7722_siu_set_rate(struct clk *clk, unsigned long rate, int algo_id)
419{
420 unsigned long r;
421 int div;
422
423 r = ctrl_inl(clk->arch_flags);
424 div = sh7722_find_div_index(clk->parent->rate, rate);
425 if (div < 0)
426 return div;
427 r = (r & ~0xF) | div;
428 ctrl_outl(r, clk->arch_flags);
429 return 0;
430}
431
432static void sh7722_siu_recalc(struct clk *clk)
433{
434 unsigned long r;
435
436 r = ctrl_inl(clk->arch_flags);
437 clk->rate = clk->parent->rate * 2 / divisors2[r & 0xF];
438}
439
440static int sh7722_siu_start_stop(struct clk *clk, int enable)
441{ 57{
442 unsigned long r; 58 unsigned long mult;
443 59
444 r = ctrl_inl(clk->arch_flags); 60 if (__raw_readl(PLLCR) & 0x1000)
445 if (enable) 61 mult = __raw_readl(DLLFRQ);
446 ctrl_outl(r & ~(1 << 8), clk->arch_flags);
447 else 62 else
448 ctrl_outl(r | (1 << 8), clk->arch_flags); 63 mult = 0;
449 return 0;
450}
451
452static void sh7722_siu_enable(struct clk *clk)
453{
454 sh7722_siu_start_stop(clk, 1);
455}
456 64
457static void sh7722_siu_disable(struct clk *clk) 65 return clk->parent->rate * mult;
458{
459 sh7722_siu_start_stop(clk, 0);
460} 66}
461 67
462static struct clk_ops sh7722_siu_clk_ops = { 68static struct clk_ops dll_clk_ops = {
463 .recalc = sh7722_siu_recalc, 69 .recalc = dll_recalc,
464 .set_rate = sh7722_siu_set_rate,
465 .enable = sh7722_siu_enable,
466 .disable = sh7722_siu_disable,
467}; 70};
468 71
469#endif /* CONFIG_CPU_SUBTYPE_SH7343 */ 72static struct clk dll_clk = {
470 73 .name = "dll_clk",
471static void sh7722_video_enable(struct clk *clk) 74 .id = -1,
472{ 75 .ops = &dll_clk_ops,
473 unsigned long r; 76 .parent = &r_clk,
474 77 .flags = CLK_ENABLE_ON_INIT,
475 r = ctrl_inl(VCLKCR); 78};
476 ctrl_outl( r & ~(1<<8), VCLKCR);
477}
478
479static void sh7722_video_disable(struct clk *clk)
480{
481 unsigned long r;
482
483 r = ctrl_inl(VCLKCR);
484 ctrl_outl( r | (1<<8), VCLKCR);
485}
486 79
487static int sh7722_video_set_rate(struct clk *clk, unsigned long rate, 80static unsigned long pll_recalc(struct clk *clk)
488 int algo_id)
489{ 81{
490 unsigned long r; 82 unsigned long mult = 1;
491 83 unsigned long div = 1;
492 r = ctrl_inl(VCLKCR);
493 r &= ~0x3F;
494 r |= ((clk->parent->rate / rate - 1) & 0x3F);
495 ctrl_outl(r, VCLKCR);
496 return 0;
497}
498 84
499static void sh7722_video_recalc(struct clk *clk) 85 if (__raw_readl(PLLCR) & 0x4000)
500{ 86 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
501 unsigned long r; 87 else
88 div = 2;
502 89
503 r = ctrl_inl(VCLKCR); 90 return (clk->parent->rate * mult) / div;
504 clk->rate = clk->parent->rate / ((r & 0x3F) + 1);
505} 91}
506 92
507static struct clk_ops sh7722_video_clk_ops = { 93static struct clk_ops pll_clk_ops = {
508 .recalc = sh7722_video_recalc, 94 .recalc = pll_recalc,
509 .set_rate = sh7722_video_set_rate,
510 .enable = sh7722_video_enable,
511 .disable = sh7722_video_disable,
512};
513/*
514 * and at last, clock definitions themselves
515 */
516static struct clk sh7722_umem_clock = {
517 .name = "umem_clk",
518 .ops = &sh7722_frqcr_clk_ops,
519 .flags = CLK_RATE_PROPAGATES,
520}; 95};
521 96
522static struct clk sh7722_sh_clock = { 97static struct clk pll_clk = {
523 .name = "sh_clk", 98 .name = "pll_clk",
524 .ops = &sh7722_frqcr_clk_ops, 99 .id = -1,
525 .flags = CLK_RATE_PROPAGATES, 100 .ops = &pll_clk_ops,
101 .flags = CLK_ENABLE_ON_INIT,
526}; 102};
527 103
528static struct clk sh7722_peripheral_clock = { 104struct clk *main_clks[] = {
529 .name = "peripheral_clk", 105 &r_clk,
530 .ops = &sh7722_frqcr_clk_ops, 106 &extal_clk,
531 .flags = CLK_RATE_PROPAGATES, 107 &dll_clk,
108 &pll_clk,
532}; 109};
533 110
534static struct clk sh7722_sdram_clock = { 111static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
535 .name = "sdram_clk", 112static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
536 .ops = &sh7722_frqcr_clk_ops,
537};
538 113
539static struct clk sh7722_r_clock = { 114static struct clk_div_mult_table div4_table = {
540 .name = "r_clk", 115 .divisors = divisors,
541 .rate = 32768, 116 .nr_divisors = ARRAY_SIZE(divisors),
542 .flags = CLK_RATE_PROPAGATES, 117 .multipliers = multipliers,
118 .nr_multipliers = ARRAY_SIZE(multipliers),
543}; 119};
544 120
545#ifndef CONFIG_CPU_SUBTYPE_SH7343 121enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
546 122 DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR };
547/*
548 * these three clocks - SIU A, SIU B, IrDA - share the same clk_ops
549 * methods of clk_ops determine which register they should access by
550 * examining clk->name field
551 */
552static struct clk sh7722_siu_a_clock = {
553 .name = "siu_a_clk",
554 .arch_flags = SCLKACR,
555 .ops = &sh7722_siu_clk_ops,
556};
557 123
558static struct clk sh7722_siu_b_clock = { 124#define DIV4(_str, _reg, _bit, _mask, _flags) \
559 .name = "siu_b_clk", 125 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
560 .arch_flags = SCLKBCR,
561 .ops = &sh7722_siu_clk_ops,
562};
563 126
564#if defined(CONFIG_CPU_SUBTYPE_SH7722) 127struct clk div4_clks[DIV4_NR] = {
565static struct clk sh7722_irda_clock = { 128 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
566 .name = "irda_clk", 129 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
567 .arch_flags = IrDACLKCR, 130 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
568 .ops = &sh7722_siu_clk_ops, 131 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
132 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
133 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x1fff, 0),
134 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x1fff, 0),
135 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x1fff, 0),
136 [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x1fff, 0),
569}; 137};
570#endif
571#endif /* CONFIG_CPU_SUBTYPE_SH7343 */
572 138
573static struct clk sh7722_video_clock = { 139struct clk div6_clks[] = {
574 .name = "video_clk", 140 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
575 .ops = &sh7722_video_clk_ops,
576}; 141};
577 142
578#define MSTPCR_ARCH_FLAGS(reg, bit) (((reg) << 8) | (bit)) 143#define MSTP(_str, _parent, _reg, _bit, _flags) \
579#define MSTPCR_ARCH_FLAGS_REG(value) ((value) >> 8) 144 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _flags)
580#define MSTPCR_ARCH_FLAGS_BIT(value) ((value) & 0xff)
581
582static int sh7722_mstpcr_start_stop(struct clk *clk, int enable)
583{
584 unsigned long bit = MSTPCR_ARCH_FLAGS_BIT(clk->arch_flags);
585 unsigned long reg;
586 unsigned long r;
587
588 switch(MSTPCR_ARCH_FLAGS_REG(clk->arch_flags)) {
589 case 0:
590 reg = MSTPCR0;
591 break;
592 case 1:
593 reg = MSTPCR1;
594 break;
595 case 2:
596 reg = MSTPCR2;
597 break;
598 default:
599 return -EINVAL;
600 }
601
602 r = ctrl_inl(reg);
603
604 if (enable)
605 r &= ~(1 << bit);
606 else
607 r |= (1 << bit);
608 145
609 ctrl_outl(r, reg); 146static struct clk mstp_clks[] = {
610 return 0; 147 MSTP("uram0", &div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
611} 148 MSTP("xymem0", &div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
149 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0),
150 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0),
151 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0),
152 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0),
153 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 7, 0),
154 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 6, 0),
155 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 5, 0),
612 156
613static void sh7722_mstpcr_enable(struct clk *clk) 157 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0),
614{ 158 MSTP("rtc0", &r_clk, MSTPCR1, 8, 0),
615 sh7722_mstpcr_start_stop(clk, 1);
616}
617 159
618static void sh7722_mstpcr_disable(struct clk *clk) 160 MSTP("sdhi0", &div4_clks[DIV4_P], MSTPCR2, 18, 0),
619{ 161 MSTP("keysc0", &r_clk, MSTPCR2, 14, 0),
620 sh7722_mstpcr_start_stop(clk, 0); 162 MSTP("usbf0", &div4_clks[DIV4_P], MSTPCR2, 11, 0),
621} 163 MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 9, 0),
622 164 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0),
623static void sh7722_mstpcr_recalc(struct clk *clk) 165 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0),
624{ 166 MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
625 if (clk->parent) 167 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0),
626 clk->rate = clk->parent->rate; 168 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0),
627} 169 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
628 170 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
629static struct clk_ops sh7722_mstpcr_clk_ops = { 171 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0),
630 .enable = sh7722_mstpcr_enable,
631 .disable = sh7722_mstpcr_disable,
632 .recalc = sh7722_mstpcr_recalc,
633};
634
635#define MSTPCR(_name, _parent, regnr, bitnr) \
636{ \
637 .name = _name, \
638 .arch_flags = MSTPCR_ARCH_FLAGS(regnr, bitnr), \
639 .ops = (void *)_parent, \
640}
641
642static struct clk sh7722_mstpcr_clocks[] = {
643#if defined(CONFIG_CPU_SUBTYPE_SH7722)
644 MSTPCR("uram0", "umem_clk", 0, 28),
645 MSTPCR("xymem0", "bus_clk", 0, 26),
646 MSTPCR("tmu0", "peripheral_clk", 0, 15),
647 MSTPCR("cmt0", "r_clk", 0, 14),
648 MSTPCR("rwdt0", "r_clk", 0, 13),
649 MSTPCR("flctl0", "peripheral_clk", 0, 10),
650 MSTPCR("scif0", "peripheral_clk", 0, 7),
651 MSTPCR("scif1", "peripheral_clk", 0, 6),
652 MSTPCR("scif2", "peripheral_clk", 0, 5),
653 MSTPCR("i2c0", "peripheral_clk", 1, 9),
654 MSTPCR("rtc0", "r_clk", 1, 8),
655 MSTPCR("sdhi0", "peripheral_clk", 2, 18),
656 MSTPCR("keysc0", "r_clk", 2, 14),
657 MSTPCR("usbf0", "peripheral_clk", 2, 11),
658 MSTPCR("2dg0", "bus_clk", 2, 9),
659 MSTPCR("siu0", "bus_clk", 2, 8),
660 MSTPCR("vou0", "bus_clk", 2, 5),
661 MSTPCR("jpu0", "bus_clk", 2, 6),
662 MSTPCR("beu0", "bus_clk", 2, 4),
663 MSTPCR("ceu0", "bus_clk", 2, 3),
664 MSTPCR("veu0", "bus_clk", 2, 2),
665 MSTPCR("vpu0", "bus_clk", 2, 1),
666 MSTPCR("lcdc0", "bus_clk", 2, 0),
667#endif
668#if defined(CONFIG_CPU_SUBTYPE_SH7723)
669 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
670 MSTPCR("tlb0", "cpu_clk", 0, 31),
671 MSTPCR("ic0", "cpu_clk", 0, 30),
672 MSTPCR("oc0", "cpu_clk", 0, 29),
673 MSTPCR("l2c0", "sh_clk", 0, 28),
674 MSTPCR("ilmem0", "cpu_clk", 0, 27),
675 MSTPCR("fpu0", "cpu_clk", 0, 24),
676 MSTPCR("intc0", "cpu_clk", 0, 22),
677 MSTPCR("dmac0", "bus_clk", 0, 21),
678 MSTPCR("sh0", "sh_clk", 0, 20),
679 MSTPCR("hudi0", "peripheral_clk", 0, 19),
680 MSTPCR("ubc0", "cpu_clk", 0, 17),
681 MSTPCR("tmu0", "peripheral_clk", 0, 15),
682 MSTPCR("cmt0", "r_clk", 0, 14),
683 MSTPCR("rwdt0", "r_clk", 0, 13),
684 MSTPCR("dmac1", "bus_clk", 0, 12),
685 MSTPCR("tmu1", "peripheral_clk", 0, 11),
686 MSTPCR("flctl0", "peripheral_clk", 0, 10),
687 MSTPCR("scif0", "peripheral_clk", 0, 9),
688 MSTPCR("scif1", "peripheral_clk", 0, 8),
689 MSTPCR("scif2", "peripheral_clk", 0, 7),
690 MSTPCR("scif3", "bus_clk", 0, 6),
691 MSTPCR("scif4", "bus_clk", 0, 5),
692 MSTPCR("scif5", "bus_clk", 0, 4),
693 MSTPCR("msiof0", "bus_clk", 0, 2),
694 MSTPCR("msiof1", "bus_clk", 0, 1),
695 MSTPCR("meram0", "sh_clk", 0, 0),
696 MSTPCR("i2c0", "peripheral_clk", 1, 9),
697 MSTPCR("rtc0", "r_clk", 1, 8),
698 MSTPCR("atapi0", "sh_clk", 2, 28),
699 MSTPCR("adc0", "peripheral_clk", 2, 28),
700 MSTPCR("tpu0", "bus_clk", 2, 25),
701 MSTPCR("irda0", "peripheral_clk", 2, 24),
702 MSTPCR("tsif0", "bus_clk", 2, 22),
703 MSTPCR("icb0", "bus_clk", 2, 21),
704 MSTPCR("sdhi0", "bus_clk", 2, 18),
705 MSTPCR("sdhi1", "bus_clk", 2, 17),
706 MSTPCR("keysc0", "r_clk", 2, 14),
707 MSTPCR("usb0", "bus_clk", 2, 11),
708 MSTPCR("2dg0", "bus_clk", 2, 10),
709 MSTPCR("siu0", "bus_clk", 2, 8),
710 MSTPCR("veu1", "bus_clk", 2, 6),
711 MSTPCR("vou0", "bus_clk", 2, 5),
712 MSTPCR("beu0", "bus_clk", 2, 4),
713 MSTPCR("ceu0", "bus_clk", 2, 3),
714 MSTPCR("veu0", "bus_clk", 2, 2),
715 MSTPCR("vpu0", "bus_clk", 2, 1),
716 MSTPCR("lcdc0", "bus_clk", 2, 0),
717#endif
718#if defined(CONFIG_CPU_SUBTYPE_SH7343)
719 MSTPCR("uram0", "umem_clk", 0, 28),
720 MSTPCR("xymem0", "bus_clk", 0, 26),
721 MSTPCR("tmu0", "peripheral_clk", 0, 15),
722 MSTPCR("cmt0", "r_clk", 0, 14),
723 MSTPCR("rwdt0", "r_clk", 0, 13),
724 MSTPCR("scif0", "peripheral_clk", 0, 7),
725 MSTPCR("scif1", "peripheral_clk", 0, 6),
726 MSTPCR("scif2", "peripheral_clk", 0, 5),
727 MSTPCR("scif3", "peripheral_clk", 0, 4),
728 MSTPCR("i2c0", "peripheral_clk", 1, 9),
729 MSTPCR("i2c1", "peripheral_clk", 1, 8),
730 MSTPCR("sdhi0", "peripheral_clk", 2, 18),
731 MSTPCR("keysc0", "r_clk", 2, 14),
732 MSTPCR("usbf0", "peripheral_clk", 2, 11),
733 MSTPCR("siu0", "bus_clk", 2, 8),
734 MSTPCR("jpu0", "bus_clk", 2, 6),
735 MSTPCR("vou0", "bus_clk", 2, 5),
736 MSTPCR("beu0", "bus_clk", 2, 4),
737 MSTPCR("ceu0", "bus_clk", 2, 3),
738 MSTPCR("veu0", "bus_clk", 2, 2),
739 MSTPCR("vpu0", "bus_clk", 2, 1),
740 MSTPCR("lcdc0", "bus_clk", 2, 0),
741#endif
742#if defined(CONFIG_CPU_SUBTYPE_SH7366)
743 /* See page 52 of Datasheet V0.40: Overview -> Block Diagram */
744 MSTPCR("tlb0", "cpu_clk", 0, 31),
745 MSTPCR("ic0", "cpu_clk", 0, 30),
746 MSTPCR("oc0", "cpu_clk", 0, 29),
747 MSTPCR("rsmem0", "sh_clk", 0, 28),
748 MSTPCR("xymem0", "cpu_clk", 0, 26),
749 MSTPCR("intc30", "peripheral_clk", 0, 23),
750 MSTPCR("intc0", "peripheral_clk", 0, 22),
751 MSTPCR("dmac0", "bus_clk", 0, 21),
752 MSTPCR("sh0", "sh_clk", 0, 20),
753 MSTPCR("hudi0", "peripheral_clk", 0, 19),
754 MSTPCR("ubc0", "cpu_clk", 0, 17),
755 MSTPCR("tmu0", "peripheral_clk", 0, 15),
756 MSTPCR("cmt0", "r_clk", 0, 14),
757 MSTPCR("rwdt0", "r_clk", 0, 13),
758 MSTPCR("flctl0", "peripheral_clk", 0, 10),
759 MSTPCR("scif0", "peripheral_clk", 0, 7),
760 MSTPCR("scif1", "bus_clk", 0, 6),
761 MSTPCR("scif2", "bus_clk", 0, 5),
762 MSTPCR("msiof0", "peripheral_clk", 0, 2),
763 MSTPCR("sbr0", "peripheral_clk", 0, 1),
764 MSTPCR("i2c0", "peripheral_clk", 1, 9),
765 MSTPCR("icb0", "bus_clk", 2, 27),
766 MSTPCR("meram0", "sh_clk", 2, 26),
767 MSTPCR("dacc0", "peripheral_clk", 2, 24),
768 MSTPCR("dacy0", "peripheral_clk", 2, 23),
769 MSTPCR("tsif0", "bus_clk", 2, 22),
770 MSTPCR("sdhi0", "bus_clk", 2, 18),
771 MSTPCR("mmcif0", "bus_clk", 2, 17),
772 MSTPCR("usb0", "bus_clk", 2, 11),
773 MSTPCR("siu0", "bus_clk", 2, 8),
774 MSTPCR("veu1", "bus_clk", 2, 7),
775 MSTPCR("vou0", "bus_clk", 2, 5),
776 MSTPCR("beu0", "bus_clk", 2, 4),
777 MSTPCR("ceu0", "bus_clk", 2, 3),
778 MSTPCR("veu0", "bus_clk", 2, 2),
779 MSTPCR("vpu0", "bus_clk", 2, 1),
780 MSTPCR("lcdc0", "bus_clk", 2, 0),
781#endif
782};
783
784static struct clk *sh7722_clocks[] = {
785 &sh7722_umem_clock,
786 &sh7722_sh_clock,
787 &sh7722_peripheral_clock,
788 &sh7722_sdram_clock,
789#ifndef CONFIG_CPU_SUBTYPE_SH7343
790 &sh7722_siu_a_clock,
791 &sh7722_siu_b_clock,
792#if defined(CONFIG_CPU_SUBTYPE_SH7722)
793 &sh7722_irda_clock,
794#endif
795#endif
796 &sh7722_video_clock,
797}; 172};
798 173
799/*
800 * init in order: master, module, bus, cpu
801 */
802struct clk_ops *onchip_ops[] = {
803 &sh7722_master_clk_ops,
804 &sh7722_module_clk_ops,
805 &sh7722_frqcr_clk_ops,
806 &sh7722_frqcr_clk_ops,
807};
808
809void __init
810arch_init_clk_ops(struct clk_ops **ops, int type)
811{
812 BUG_ON(type < 0 || type > ARRAY_SIZE(onchip_ops));
813 *ops = onchip_ops[type];
814}
815
816int __init arch_clk_init(void) 174int __init arch_clk_init(void)
817{ 175{
818 struct clk *clk; 176 int k, ret = 0;
819 int i; 177
178 /* autodetect extal or dll configuration */
179 if (__raw_readl(PLLCR) & 0x1000)
180 pll_clk.parent = &dll_clk;
181 else
182 pll_clk.parent = &extal_clk;
820 183
821 clk = clk_get(NULL, "master_clk"); 184 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
822 for (i = 0; i < ARRAY_SIZE(sh7722_clocks); i++) { 185 ret = clk_register(main_clks[k]);
823 pr_debug( "Registering clock '%s'\n", sh7722_clocks[i]->name);
824 sh7722_clocks[i]->parent = clk;
825 clk_register(sh7722_clocks[i]);
826 }
827 clk_put(clk);
828 186
829 clk_register(&sh7722_r_clock); 187 if (!ret)
188 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
830 189
831 for (i = 0; i < ARRAY_SIZE(sh7722_mstpcr_clocks); i++) { 190 if (!ret)
832 pr_debug( "Registering mstpcr clock '%s'\n", 191 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
833 sh7722_mstpcr_clocks[i].name);
834 clk = clk_get(NULL, (void *) sh7722_mstpcr_clocks[i].ops);
835 sh7722_mstpcr_clocks[i].parent = clk;
836 sh7722_mstpcr_clocks[i].ops = &sh7722_mstpcr_clk_ops;
837 clk_register(&sh7722_mstpcr_clocks[i]);
838 clk_put(clk);
839 }
840 192
841 clk_recalc_rate(&sh7722_r_clock); /* make sure rate gets propagated */ 193 if (!ret)
194 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
842 195
843 return 0; 196 return ret;
844} 197}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
new file mode 100644
index 000000000000..e67c2678b8ae
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c
@@ -0,0 +1,222 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/clock-sh7723.c
3 *
4 * SH7723 clock framework support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/clock.h>
25
26/* SH7723 registers */
27#define FRQCR 0xa4150000
28#define VCLKCR 0xa4150004
29#define SCLKACR 0xa4150008
30#define SCLKBCR 0xa415000c
31#define IRDACLKCR 0xa4150018
32#define PLLCR 0xa4150024
33#define MSTPCR0 0xa4150030
34#define MSTPCR1 0xa4150034
35#define MSTPCR2 0xa4150038
36#define DLLFRQ 0xa4150050
37
38/* Fixed 32 KHz root clock for RTC and Power Management purposes */
39static struct clk r_clk = {
40 .name = "rclk",
41 .id = -1,
42 .rate = 32768,
43};
44
45/*
46 * Default rate for the root input clock, reset this with clk_set_rate()
47 * from the platform code.
48 */
49struct clk extal_clk = {
50 .name = "extal",
51 .id = -1,
52 .rate = 33333333,
53};
54
55/* The dll multiplies the 32khz r_clk, may be used instead of extal */
56static unsigned long dll_recalc(struct clk *clk)
57{
58 unsigned long mult;
59
60 if (__raw_readl(PLLCR) & 0x1000)
61 mult = __raw_readl(DLLFRQ);
62 else
63 mult = 0;
64
65 return clk->parent->rate * mult;
66}
67
68static struct clk_ops dll_clk_ops = {
69 .recalc = dll_recalc,
70};
71
72static struct clk dll_clk = {
73 .name = "dll_clk",
74 .id = -1,
75 .ops = &dll_clk_ops,
76 .parent = &r_clk,
77 .flags = CLK_ENABLE_ON_INIT,
78};
79
80static unsigned long pll_recalc(struct clk *clk)
81{
82 unsigned long mult = 1;
83 unsigned long div = 1;
84
85 if (__raw_readl(PLLCR) & 0x4000)
86 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
87 else
88 div = 2;
89
90 return (clk->parent->rate * mult) / div;
91}
92
93static struct clk_ops pll_clk_ops = {
94 .recalc = pll_recalc,
95};
96
97static struct clk pll_clk = {
98 .name = "pll_clk",
99 .id = -1,
100 .ops = &pll_clk_ops,
101 .flags = CLK_ENABLE_ON_INIT,
102};
103
104struct clk *main_clks[] = {
105 &r_clk,
106 &extal_clk,
107 &dll_clk,
108 &pll_clk,
109};
110
111static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
112static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
113
114static struct clk_div_mult_table div4_table = {
115 .divisors = divisors,
116 .nr_divisors = ARRAY_SIZE(divisors),
117 .multipliers = multipliers,
118 .nr_multipliers = ARRAY_SIZE(multipliers),
119};
120
121enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P,
122 DIV4_SIUA, DIV4_SIUB, DIV4_IRDA, DIV4_NR };
123
124#define DIV4(_str, _reg, _bit, _mask, _flags) \
125 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
126
127struct clk div4_clks[DIV4_NR] = {
128 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
129 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
130 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
131 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
132 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
133 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0),
134 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
135 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
136 [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0),
137};
138
139struct clk div6_clks[] = {
140 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
141};
142
143#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \
144 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT)
145
146static struct clk mstp_clks[] = {
147 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
148 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0),
149 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0),
150 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0),
151 MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 28, 1, 1, 0),
152 MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0),
153 MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0),
154 MSTP("intc0", &div4_clks[DIV4_I], MSTPCR0, 22, 1, 1, 0),
155 MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1),
156 MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0),
157 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0),
158 MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0),
159 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0),
160 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0),
161 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0),
162 MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1),
163 MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 11, 0, 1, 0),
164 MSTP("flctl0", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0),
165 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0),
166 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0),
167 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0),
168 MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0),
169 MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0),
170 MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0),
171 MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0),
172 MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0),
173 MSTP("meram0", &div4_clks[DIV4_SH], MSTPCR0, 0, 1, 1, 0),
174
175 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0),
176 MSTP("rtc0", &r_clk, MSTPCR1, 8, 0, 0, 0),
177
178 MSTP("atapi0", &div4_clks[DIV4_SH], MSTPCR2, 28, 0, 1, 0),
179 MSTP("adc0", &div4_clks[DIV4_P], MSTPCR2, 27, 0, 1, 0),
180 MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0),
181 MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0),
182 MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0),
183 MSTP("icb0", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1),
184 MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0),
185 MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0),
186 MSTP("keysc0", &r_clk, MSTPCR2, 14, 0, 0, 0),
187 MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 11, 0, 1, 0),
188 MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 10, 0, 1, 1),
189 MSTP("siu0", &div4_clks[DIV4_B], MSTPCR2, 8, 0, 1, 0),
190 MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1),
191 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1),
192 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1),
193 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1),
194 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1),
195 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1),
196 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1),
197};
198
199int __init arch_clk_init(void)
200{
201 int k, ret = 0;
202
203 /* autodetect extal or dll configuration */
204 if (__raw_readl(PLLCR) & 0x1000)
205 pll_clk.parent = &dll_clk;
206 else
207 pll_clk.parent = &extal_clk;
208
209 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
210 ret = clk_register(main_clks[k]);
211
212 if (!ret)
213 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
214
215 if (!ret)
216 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
217
218 if (!ret)
219 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
220
221 return ret;
222}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
new file mode 100644
index 000000000000..5d5c9b952883
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c
@@ -0,0 +1,242 @@
1/*
2 * arch/sh/kernel/cpu/sh4a/clock-sh7724.c
3 *
4 * SH7724 clock framework support
5 *
6 * Copyright (C) 2009 Magnus Damm
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <asm/clock.h>
25
26/* SH7724 registers */
27#define FRQCRA 0xa4150000
28#define FRQCRB 0xa4150004
29#define VCLKCR 0xa4150048
30#define FCLKACR 0xa4150008
31#define FCLKBCR 0xa415000c
32#define IRDACLKCR 0xa4150018
33#define PLLCR 0xa4150024
34#define MSTPCR0 0xa4150030
35#define MSTPCR1 0xa4150034
36#define MSTPCR2 0xa4150038
37#define SPUCLKCR 0xa415003c
38#define FLLFRQ 0xa4150050
39#define LSTATS 0xa4150060
40
41/* Fixed 32 KHz root clock for RTC and Power Management purposes */
42static struct clk r_clk = {
43 .name = "rclk",
44 .id = -1,
45 .rate = 32768,
46};
47
48/*
49 * Default rate for the root input clock, reset this with clk_set_rate()
50 * from the platform code.
51 */
52struct clk extal_clk = {
53 .name = "extal",
54 .id = -1,
55 .rate = 33333333,
56};
57
58/* The fll multiplies the 32khz r_clk, may be used instead of extal */
59static unsigned long fll_recalc(struct clk *clk)
60{
61 unsigned long mult = 0;
62 unsigned long div = 1;
63
64 if (__raw_readl(PLLCR) & 0x1000)
65 mult = __raw_readl(FLLFRQ) & 0x3ff;
66
67 if (__raw_readl(FLLFRQ) & 0x4000)
68 div = 2;
69
70 return (clk->parent->rate * mult) / div;
71}
72
73static struct clk_ops fll_clk_ops = {
74 .recalc = fll_recalc,
75};
76
77static struct clk fll_clk = {
78 .name = "fll_clk",
79 .id = -1,
80 .ops = &fll_clk_ops,
81 .parent = &r_clk,
82 .flags = CLK_ENABLE_ON_INIT,
83};
84
85static unsigned long pll_recalc(struct clk *clk)
86{
87 unsigned long mult = 1;
88
89 if (__raw_readl(PLLCR) & 0x4000)
90 mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2;
91
92 return clk->parent->rate * mult;
93}
94
95static struct clk_ops pll_clk_ops = {
96 .recalc = pll_recalc,
97};
98
99static struct clk pll_clk = {
100 .name = "pll_clk",
101 .id = -1,
102 .ops = &pll_clk_ops,
103 .flags = CLK_ENABLE_ON_INIT,
104};
105
106/* A fixed divide-by-3 block use by the div6 clocks */
107static unsigned long div3_recalc(struct clk *clk)
108{
109 return clk->parent->rate / 3;
110}
111
112static struct clk_ops div3_clk_ops = {
113 .recalc = div3_recalc,
114};
115
116static struct clk div3_clk = {
117 .name = "div3_clk",
118 .id = -1,
119 .ops = &div3_clk_ops,
120 .parent = &pll_clk,
121};
122
123struct clk *main_clks[] = {
124 &r_clk,
125 &extal_clk,
126 &fll_clk,
127 &pll_clk,
128 &div3_clk,
129};
130
131static int divisors[] = { 2, 0, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
132
133static struct clk_div_mult_table div4_table = {
134 .divisors = divisors,
135 .nr_divisors = ARRAY_SIZE(divisors),
136};
137
138enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
139
140#define DIV4(_str, _reg, _bit, _mask, _flags) \
141 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
142
143struct clk div4_clks[DIV4_NR] = {
144 [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
145 [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
146 [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
147 [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
148 [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, 0),
149};
150
151struct clk div6_clks[] = {
152 SH_CLK_DIV6("video_clk", &div3_clk, VCLKCR, 0),
153 SH_CLK_DIV6("fsia_clk", &div3_clk, FCLKACR, 0),
154 SH_CLK_DIV6("fsib_clk", &div3_clk, FCLKBCR, 0),
155 SH_CLK_DIV6("irda_clk", &div3_clk, IRDACLKCR, 0),
156 SH_CLK_DIV6("spu_clk", &div3_clk, SPUCLKCR, 0),
157};
158
159#define MSTP(_str, _parent, _reg, _bit, _force_on, _need_cpg, _need_ram) \
160 SH_CLK_MSTP32(_str, -1, _parent, _reg, _bit, _force_on * CLK_ENABLE_ON_INIT)
161
162static struct clk mstp_clks[] = {
163 MSTP("tlb0", &div4_clks[DIV4_I], MSTPCR0, 31, 1, 1, 0),
164 MSTP("ic0", &div4_clks[DIV4_I], MSTPCR0, 30, 1, 1, 0),
165 MSTP("oc0", &div4_clks[DIV4_I], MSTPCR0, 29, 1, 1, 0),
166 MSTP("rs0", &div4_clks[DIV4_B], MSTPCR0, 28, 1, 1, 0),
167 MSTP("ilmem0", &div4_clks[DIV4_I], MSTPCR0, 27, 1, 1, 0),
168 MSTP("l2c0", &div4_clks[DIV4_SH], MSTPCR0, 26, 1, 1, 0),
169 MSTP("fpu0", &div4_clks[DIV4_I], MSTPCR0, 24, 1, 1, 0),
170 MSTP("intc0", &div4_clks[DIV4_P], MSTPCR0, 22, 1, 1, 0),
171 MSTP("dmac0", &div4_clks[DIV4_B], MSTPCR0, 21, 0, 1, 1),
172 MSTP("sh0", &div4_clks[DIV4_SH], MSTPCR0, 20, 0, 1, 0),
173 MSTP("hudi0", &div4_clks[DIV4_P], MSTPCR0, 19, 0, 1, 0),
174 MSTP("ubc0", &div4_clks[DIV4_I], MSTPCR0, 17, 0, 1, 0),
175 MSTP("tmu0", &div4_clks[DIV4_P], MSTPCR0, 15, 0, 1, 0),
176 MSTP("cmt0", &r_clk, MSTPCR0, 14, 0, 0, 0),
177 MSTP("rwdt0", &r_clk, MSTPCR0, 13, 0, 0, 0),
178 MSTP("dmac1", &div4_clks[DIV4_B], MSTPCR0, 12, 0, 1, 1),
179 MSTP("tmu1", &div4_clks[DIV4_P], MSTPCR0, 10, 0, 1, 0),
180 MSTP("scif0", &div4_clks[DIV4_P], MSTPCR0, 9, 0, 1, 0),
181 MSTP("scif1", &div4_clks[DIV4_P], MSTPCR0, 8, 0, 1, 0),
182 MSTP("scif2", &div4_clks[DIV4_P], MSTPCR0, 7, 0, 1, 0),
183 MSTP("scif3", &div4_clks[DIV4_B], MSTPCR0, 6, 0, 1, 0),
184 MSTP("scif4", &div4_clks[DIV4_B], MSTPCR0, 5, 0, 1, 0),
185 MSTP("scif5", &div4_clks[DIV4_B], MSTPCR0, 4, 0, 1, 0),
186 MSTP("msiof0", &div4_clks[DIV4_B], MSTPCR0, 2, 0, 1, 0),
187 MSTP("msiof1", &div4_clks[DIV4_B], MSTPCR0, 1, 0, 1, 0),
188
189 MSTP("keysc0", &r_clk, MSTPCR1, 12, 0, 0, 0),
190 MSTP("rtc0", &r_clk, MSTPCR1, 11, 0, 0, 0),
191 MSTP("i2c0", &div4_clks[DIV4_P], MSTPCR1, 9, 0, 1, 0),
192 MSTP("i2c1", &div4_clks[DIV4_P], MSTPCR1, 8, 0, 1, 0),
193
194 MSTP("mmc0", &div4_clks[DIV4_B], MSTPCR2, 29, 0, 1, 0),
195 MSTP("eth0", &div4_clks[DIV4_B], MSTPCR2, 28, 0, 1, 0),
196 MSTP("atapi0", &div4_clks[DIV4_B], MSTPCR2, 26, 0, 1, 0),
197 MSTP("tpu0", &div4_clks[DIV4_B], MSTPCR2, 25, 0, 1, 0),
198 MSTP("irda0", &div4_clks[DIV4_P], MSTPCR2, 24, 0, 1, 0),
199 MSTP("tsif0", &div4_clks[DIV4_B], MSTPCR2, 22, 0, 1, 0),
200 MSTP("usb1", &div4_clks[DIV4_B], MSTPCR2, 21, 0, 1, 1),
201 MSTP("usb0", &div4_clks[DIV4_B], MSTPCR2, 20, 0, 1, 1),
202 MSTP("2dg0", &div4_clks[DIV4_B], MSTPCR2, 19, 0, 1, 1),
203 MSTP("sdhi0", &div4_clks[DIV4_B], MSTPCR2, 18, 0, 1, 0),
204 MSTP("sdhi1", &div4_clks[DIV4_B], MSTPCR2, 17, 0, 1, 0),
205 MSTP("veu1", &div4_clks[DIV4_B], MSTPCR2, 15, 1, 1, 1),
206 MSTP("ceu1", &div4_clks[DIV4_B], MSTPCR2, 13, 0, 1, 1),
207 MSTP("beu1", &div4_clks[DIV4_B], MSTPCR2, 12, 0, 1, 1),
208 MSTP("2ddmac0", &div4_clks[DIV4_SH], MSTPCR2, 10, 0, 1, 1),
209 MSTP("spu0", &div4_clks[DIV4_B], MSTPCR2, 9, 0, 1, 0),
210 MSTP("jpu0", &div4_clks[DIV4_B], MSTPCR2, 6, 1, 1, 1),
211 MSTP("vou0", &div4_clks[DIV4_B], MSTPCR2, 5, 0, 1, 1),
212 MSTP("beu0", &div4_clks[DIV4_B], MSTPCR2, 4, 0, 1, 1),
213 MSTP("ceu0", &div4_clks[DIV4_B], MSTPCR2, 3, 0, 1, 1),
214 MSTP("veu0", &div4_clks[DIV4_B], MSTPCR2, 2, 1, 1, 1),
215 MSTP("vpu0", &div4_clks[DIV4_B], MSTPCR2, 1, 1, 1, 1),
216 MSTP("lcdc0", &div4_clks[DIV4_B], MSTPCR2, 0, 0, 1, 1),
217};
218
219int __init arch_clk_init(void)
220{
221 int k, ret = 0;
222
223 /* autodetect extal or fll configuration */
224 if (__raw_readl(PLLCR) & 0x1000)
225 pll_clk.parent = &fll_clk;
226 else
227 pll_clk.parent = &extal_clk;
228
229 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
230 ret = clk_register(main_clks[k]);
231
232 if (!ret)
233 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
234
235 if (!ret)
236 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
237
238 if (!ret)
239 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
240
241 return ret;
242}
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 3177d0d1e06d..370cd47642ef 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -29,33 +29,28 @@ static struct clk_ops sh7763_master_clk_ops = {
29 .init = master_clk_init, 29 .init = master_clk_init,
30}; 30};
31 31
32static void module_clk_recalc(struct clk *clk) 32static unsigned long module_clk_recalc(struct clk *clk)
33{ 33{
34 int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07); 34 int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07);
35 clk->rate = clk->parent->rate / p0fc_divisors[idx]; 35 return clk->parent->rate / p0fc_divisors[idx];
36} 36}
37 37
38static struct clk_ops sh7763_module_clk_ops = { 38static struct clk_ops sh7763_module_clk_ops = {
39 .recalc = module_clk_recalc, 39 .recalc = module_clk_recalc,
40}; 40};
41 41
42static void bus_clk_recalc(struct clk *clk) 42static unsigned long bus_clk_recalc(struct clk *clk)
43{ 43{
44 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07); 44 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07);
45 clk->rate = clk->parent->rate / bfc_divisors[idx]; 45 return clk->parent->rate / bfc_divisors[idx];
46} 46}
47 47
48static struct clk_ops sh7763_bus_clk_ops = { 48static struct clk_ops sh7763_bus_clk_ops = {
49 .recalc = bus_clk_recalc, 49 .recalc = bus_clk_recalc,
50}; 50};
51 51
52static void cpu_clk_recalc(struct clk *clk)
53{
54 clk->rate = clk->parent->rate;
55}
56
57static struct clk_ops sh7763_cpu_clk_ops = { 52static struct clk_ops sh7763_cpu_clk_ops = {
58 .recalc = cpu_clk_recalc, 53 .recalc = followparent_recalc,
59}; 54};
60 55
61static struct clk_ops *sh7763_clk_ops[] = { 56static struct clk_ops *sh7763_clk_ops[] = {
@@ -71,10 +66,10 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
71 *ops = sh7763_clk_ops[idx]; 66 *ops = sh7763_clk_ops[idx];
72} 67}
73 68
74static void shyway_clk_recalc(struct clk *clk) 69static unsigned long shyway_clk_recalc(struct clk *clk)
75{ 70{
76 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07); 71 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07);
77 clk->rate = clk->parent->rate / cfc_divisors[idx]; 72 return clk->parent->rate / cfc_divisors[idx];
78} 73}
79 74
80static struct clk_ops sh7763_shyway_clk_ops = { 75static struct clk_ops sh7763_shyway_clk_ops = {
@@ -83,7 +78,7 @@ static struct clk_ops sh7763_shyway_clk_ops = {
83 78
84static struct clk sh7763_shyway_clk = { 79static struct clk sh7763_shyway_clk = {
85 .name = "shyway_clk", 80 .name = "shyway_clk",
86 .flags = CLK_ALWAYS_ENABLED, 81 .flags = CLK_ENABLE_ON_INIT,
87 .ops = &sh7763_shyway_clk_ops, 82 .ops = &sh7763_shyway_clk_ops,
88}; 83};
89 84
@@ -95,31 +90,22 @@ static struct clk *sh7763_onchip_clocks[] = {
95 &sh7763_shyway_clk, 90 &sh7763_shyway_clk,
96}; 91};
97 92
98static int __init sh7763_clk_init(void) 93int __init arch_clk_init(void)
99{ 94{
100 struct clk *clk = clk_get(NULL, "master_clk"); 95 struct clk *clk;
101 int i; 96 int i, ret = 0;
97
98 cpg_clk_init();
102 99
100 clk = clk_get(NULL, "master_clk");
103 for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) { 101 for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) {
104 struct clk *clkp = sh7763_onchip_clocks[i]; 102 struct clk *clkp = sh7763_onchip_clocks[i];
105 103
106 clkp->parent = clk; 104 clkp->parent = clk;
107 clk_register(clkp); 105 ret |= clk_register(clkp);
108 clk_enable(clkp);
109 } 106 }
110 107
111 /*
112 * Now that we have the rest of the clocks registered, we need to
113 * force the parent clock to propagate so that these clocks will
114 * automatically figure out their rate. We cheat by handing the
115 * parent clock its current rate and forcing child propagation.
116 */
117 clk_set_rate(clk, clk_get_rate(clk));
118
119 clk_put(clk); 108 clk_put(clk);
120 109
121 return 0; 110 return ret;
122} 111}
123
124arch_initcall(sh7763_clk_init);
125
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
index 8e236062c721..e0b896769205 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
@@ -28,30 +28,30 @@ static struct clk_ops sh7770_master_clk_ops = {
28 .init = master_clk_init, 28 .init = master_clk_init,
29}; 29};
30 30
31static void module_clk_recalc(struct clk *clk) 31static unsigned long module_clk_recalc(struct clk *clk)
32{ 32{
33 int idx = ((ctrl_inl(FRQCR) >> 28) & 0x000f); 33 int idx = ((ctrl_inl(FRQCR) >> 28) & 0x000f);
34 clk->rate = clk->parent->rate / pfc_divisors[idx]; 34 return clk->parent->rate / pfc_divisors[idx];
35} 35}
36 36
37static struct clk_ops sh7770_module_clk_ops = { 37static struct clk_ops sh7770_module_clk_ops = {
38 .recalc = module_clk_recalc, 38 .recalc = module_clk_recalc,
39}; 39};
40 40
41static void bus_clk_recalc(struct clk *clk) 41static unsigned long bus_clk_recalc(struct clk *clk)
42{ 42{
43 int idx = (ctrl_inl(FRQCR) & 0x000f); 43 int idx = (ctrl_inl(FRQCR) & 0x000f);
44 clk->rate = clk->parent->rate / bfc_divisors[idx]; 44 return clk->parent->rate / bfc_divisors[idx];
45} 45}
46 46
47static struct clk_ops sh7770_bus_clk_ops = { 47static struct clk_ops sh7770_bus_clk_ops = {
48 .recalc = bus_clk_recalc, 48 .recalc = bus_clk_recalc,
49}; 49};
50 50
51static void cpu_clk_recalc(struct clk *clk) 51static unsigned long cpu_clk_recalc(struct clk *clk)
52{ 52{
53 int idx = ((ctrl_inl(FRQCR) >> 24) & 0x000f); 53 int idx = ((ctrl_inl(FRQCR) >> 24) & 0x000f);
54 clk->rate = clk->parent->rate / ifc_divisors[idx]; 54 return clk->parent->rate / ifc_divisors[idx];
55} 55}
56 56
57static struct clk_ops sh7770_cpu_clk_ops = { 57static struct clk_ops sh7770_cpu_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index 01f3da619d3d..a249d823578e 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -29,30 +29,30 @@ static struct clk_ops sh7780_master_clk_ops = {
29 .init = master_clk_init, 29 .init = master_clk_init,
30}; 30};
31 31
32static void module_clk_recalc(struct clk *clk) 32static unsigned long module_clk_recalc(struct clk *clk)
33{ 33{
34 int idx = (ctrl_inl(FRQCR) & 0x0003); 34 int idx = (ctrl_inl(FRQCR) & 0x0003);
35 clk->rate = clk->parent->rate / pfc_divisors[idx]; 35 return clk->parent->rate / pfc_divisors[idx];
36} 36}
37 37
38static struct clk_ops sh7780_module_clk_ops = { 38static struct clk_ops sh7780_module_clk_ops = {
39 .recalc = module_clk_recalc, 39 .recalc = module_clk_recalc,
40}; 40};
41 41
42static void bus_clk_recalc(struct clk *clk) 42static unsigned long bus_clk_recalc(struct clk *clk)
43{ 43{
44 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007); 44 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007);
45 clk->rate = clk->parent->rate / bfc_divisors[idx]; 45 return clk->parent->rate / bfc_divisors[idx];
46} 46}
47 47
48static struct clk_ops sh7780_bus_clk_ops = { 48static struct clk_ops sh7780_bus_clk_ops = {
49 .recalc = bus_clk_recalc, 49 .recalc = bus_clk_recalc,
50}; 50};
51 51
52static void cpu_clk_recalc(struct clk *clk) 52static unsigned long cpu_clk_recalc(struct clk *clk)
53{ 53{
54 int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001); 54 int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001);
55 clk->rate = clk->parent->rate / ifc_divisors[idx]; 55 return clk->parent->rate / ifc_divisors[idx];
56} 56}
57 57
58static struct clk_ops sh7780_cpu_clk_ops = { 58static struct clk_ops sh7780_cpu_clk_ops = {
@@ -72,10 +72,10 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
72 *ops = sh7780_clk_ops[idx]; 72 *ops = sh7780_clk_ops[idx];
73} 73}
74 74
75static void shyway_clk_recalc(struct clk *clk) 75static unsigned long shyway_clk_recalc(struct clk *clk)
76{ 76{
77 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007); 77 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007);
78 clk->rate = clk->parent->rate / cfc_divisors[idx]; 78 return clk->parent->rate / cfc_divisors[idx];
79} 79}
80 80
81static struct clk_ops sh7780_shyway_clk_ops = { 81static struct clk_ops sh7780_shyway_clk_ops = {
@@ -84,7 +84,7 @@ static struct clk_ops sh7780_shyway_clk_ops = {
84 84
85static struct clk sh7780_shyway_clk = { 85static struct clk sh7780_shyway_clk = {
86 .name = "shyway_clk", 86 .name = "shyway_clk",
87 .flags = CLK_ALWAYS_ENABLED, 87 .flags = CLK_ENABLE_ON_INIT,
88 .ops = &sh7780_shyway_clk_ops, 88 .ops = &sh7780_shyway_clk_ops,
89}; 89};
90 90
@@ -96,31 +96,22 @@ static struct clk *sh7780_onchip_clocks[] = {
96 &sh7780_shyway_clk, 96 &sh7780_shyway_clk,
97}; 97};
98 98
99static int __init sh7780_clk_init(void) 99int __init arch_clk_init(void)
100{ 100{
101 struct clk *clk = clk_get(NULL, "master_clk"); 101 struct clk *clk;
102 int i; 102 int i, ret = 0;
103 103
104 cpg_clk_init();
105
106 clk = clk_get(NULL, "master_clk");
104 for (i = 0; i < ARRAY_SIZE(sh7780_onchip_clocks); i++) { 107 for (i = 0; i < ARRAY_SIZE(sh7780_onchip_clocks); i++) {
105 struct clk *clkp = sh7780_onchip_clocks[i]; 108 struct clk *clkp = sh7780_onchip_clocks[i];
106 109
107 clkp->parent = clk; 110 clkp->parent = clk;
108 clk_register(clkp); 111 ret |= clk_register(clkp);
109 clk_enable(clkp);
110 } 112 }
111 113
112 /*
113 * Now that we have the rest of the clocks registered, we need to
114 * force the parent clock to propagate so that these clocks will
115 * automatically figure out their rate. We cheat by handing the
116 * parent clock its current rate and forcing child propagation.
117 */
118 clk_set_rate(clk, clk_get_rate(clk));
119
120 clk_put(clk); 114 clk_put(clk);
121 115
122 return 0; 116 return ret;
123} 117}
124
125arch_initcall(sh7780_clk_init);
126
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
index 27fa81bef6a0..73abfbf2f16d 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * SH7785 support for the clock framework 4 * SH7785 support for the clock framework
5 * 5 *
6 * Copyright (C) 2007 Paul Mundt 6 * Copyright (C) 2007 - 2009 Paul Mundt
7 * 7 *
8 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive 9 * License. See the file "COPYING" in the main directory of this archive
@@ -11,152 +11,116 @@
11 */ 11 */
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/cpufreq.h>
14#include <asm/clock.h> 17#include <asm/clock.h>
15#include <asm/freq.h> 18#include <asm/freq.h>
16#include <asm/io.h> 19#include <cpu/sh7785.h>
17
18static int ifc_divisors[] = { 1, 2, 4, 6 };
19static int ufc_divisors[] = { 1, 1, 4, 6 };
20static int sfc_divisors[] = { 1, 1, 4, 6 };
21static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 18,
22 24, 32, 36, 48, 1, 1, 1, 1 };
23static int mfc_divisors[] = { 1, 1, 4, 6 };
24static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 1, 18,
25 24, 32, 36, 48, 1, 1, 1, 1 };
26
27static void master_clk_init(struct clk *clk)
28{
29 clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
30}
31 20
32static struct clk_ops sh7785_master_clk_ops = { 21/*
33 .init = master_clk_init, 22 * Default rate for the root input clock, reset this with clk_set_rate()
23 * from the platform code.
24 */
25static struct clk extal_clk = {
26 .name = "extal",
27 .id = -1,
28 .rate = 33333333,
34}; 29};
35 30
36static void module_clk_recalc(struct clk *clk) 31static unsigned long pll_recalc(struct clk *clk)
37{ 32{
38 int idx = (ctrl_inl(FRQMR1) & 0x000f); 33 int multiplier;
39 clk->rate = clk->parent->rate / pfc_divisors[idx];
40}
41 34
42static struct clk_ops sh7785_module_clk_ops = { 35 multiplier = test_mode_pin(MODE_PIN4) ? 36 : 72;
43 .recalc = module_clk_recalc,
44};
45 36
46static void bus_clk_recalc(struct clk *clk) 37 return clk->parent->rate * multiplier;
47{
48 int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
49 clk->rate = clk->parent->rate / bfc_divisors[idx];
50} 38}
51 39
52static struct clk_ops sh7785_bus_clk_ops = { 40static struct clk_ops pll_clk_ops = {
53 .recalc = bus_clk_recalc, 41 .recalc = pll_recalc,
54}; 42};
55 43
56static void cpu_clk_recalc(struct clk *clk) 44static struct clk pll_clk = {
57{ 45 .name = "pll_clk",
58 int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003); 46 .id = -1,
59 clk->rate = clk->parent->rate / ifc_divisors[idx]; 47 .ops = &pll_clk_ops,
60} 48 .parent = &extal_clk,
61 49 .flags = CLK_ENABLE_ON_INIT,
62static struct clk_ops sh7785_cpu_clk_ops = {
63 .recalc = cpu_clk_recalc,
64}; 50};
65 51
66static struct clk_ops *sh7785_clk_ops[] = { 52static struct clk *clks[] = {
67 &sh7785_master_clk_ops, 53 &extal_clk,
68 &sh7785_module_clk_ops, 54 &pll_clk,
69 &sh7785_bus_clk_ops,
70 &sh7785_cpu_clk_ops,
71}; 55};
72 56
73void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 57static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
74{ 58 24, 32, 36, 48 };
75 if (idx < ARRAY_SIZE(sh7785_clk_ops))
76 *ops = sh7785_clk_ops[idx];
77}
78
79static void shyway_clk_recalc(struct clk *clk)
80{
81 int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
82 clk->rate = clk->parent->rate / sfc_divisors[idx];
83}
84 59
85static struct clk_ops sh7785_shyway_clk_ops = { 60static struct clk_div_mult_table div4_table = {
86 .recalc = shyway_clk_recalc, 61 .divisors = div2,
62 .nr_divisors = ARRAY_SIZE(div2),
87}; 63};
88 64
89static struct clk sh7785_shyway_clk = { 65enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_GA,
90 .name = "shyway_clk", 66 DIV4_DU, DIV4_P, DIV4_NR };
91 .flags = CLK_ALWAYS_ENABLED, 67
92 .ops = &sh7785_shyway_clk_ops, 68#define DIV4(_str, _bit, _mask, _flags) \
69 SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
70
71struct clk div4_clks[DIV4_NR] = {
72 [DIV4_P] = DIV4("peripheral_clk", 0, 0x0f80, 0),
73 [DIV4_DU] = DIV4("du_clk", 4, 0x0ff0, 0),
74 [DIV4_GA] = DIV4("ga_clk", 8, 0x0030, 0),
75 [DIV4_DDR] = DIV4("ddr_clk", 12, 0x000c, CLK_ENABLE_ON_INIT),
76 [DIV4_B] = DIV4("bus_clk", 16, 0x0fe0, CLK_ENABLE_ON_INIT),
77 [DIV4_SH] = DIV4("shyway_clk", 20, 0x000c, CLK_ENABLE_ON_INIT),
78 [DIV4_U] = DIV4("umem_clk", 24, 0x000c, CLK_ENABLE_ON_INIT),
79 [DIV4_I] = DIV4("cpu_clk", 28, 0x000e, CLK_ENABLE_ON_INIT),
93}; 80};
94 81
95static void ddr_clk_recalc(struct clk *clk) 82#define MSTPCR0 0xffc80030
96{ 83#define MSTPCR1 0xffc80034
97 int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003); 84
98 clk->rate = clk->parent->rate / mfc_divisors[idx]; 85static struct clk mstp_clks[] = {
99} 86 /* MSTPCR0 */
100 87 SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
101static struct clk_ops sh7785_ddr_clk_ops = { 88 SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
102 .recalc = ddr_clk_recalc, 89 SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
103}; 90 SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
104 91 SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
105static struct clk sh7785_ddr_clk = { 92 SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
106 .name = "ddr_clk", 93 SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
107 .flags = CLK_ALWAYS_ENABLED, 94 SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
108 .ops = &sh7785_ddr_clk_ops, 95 SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
109}; 96 SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
110 97 SH_CLK_MSTP32("mmcif_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 13, 0),
111static void ram_clk_recalc(struct clk *clk) 98 SH_CLK_MSTP32("flctl_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 12, 0),
112{ 99 SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
113 int idx = ((ctrl_inl(FRQMR1) >> 24) & 0x0003); 100 SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
114 clk->rate = clk->parent->rate / ufc_divisors[idx]; 101 SH_CLK_MSTP32("siof_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 3, 0),
115} 102 SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
116 103
117static struct clk_ops sh7785_ram_clk_ops = { 104 /* MSTPCR1 */
118 .recalc = ram_clk_recalc, 105 SH_CLK_MSTP32("hudi_fck", -1, NULL, MSTPCR1, 19, 0),
106 SH_CLK_MSTP32("ubc_fck", -1, NULL, MSTPCR1, 17, 0),
107 SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
108 SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
109 SH_CLK_MSTP32("gdta_fck", -1, NULL, MSTPCR1, 0, 0),
119}; 110};
120 111
121static struct clk sh7785_ram_clk = { 112int __init arch_clk_init(void)
122 .name = "ram_clk",
123 .flags = CLK_ALWAYS_ENABLED,
124 .ops = &sh7785_ram_clk_ops,
125};
126
127/*
128 * Additional SH7785-specific on-chip clocks that aren't already part of the
129 * clock framework
130 */
131static struct clk *sh7785_onchip_clocks[] = {
132 &sh7785_shyway_clk,
133 &sh7785_ddr_clk,
134 &sh7785_ram_clk,
135};
136
137static int __init sh7785_clk_init(void)
138{ 113{
139 struct clk *clk = clk_get(NULL, "master_clk"); 114 int i, ret = 0;
140 int i;
141
142 for (i = 0; i < ARRAY_SIZE(sh7785_onchip_clocks); i++) {
143 struct clk *clkp = sh7785_onchip_clocks[i];
144
145 clkp->parent = clk;
146 clk_register(clkp);
147 clk_enable(clkp);
148 }
149 115
150 /* 116 for (i = 0; i < ARRAY_SIZE(clks); i++)
151 * Now that we have the rest of the clocks registered, we need to 117 ret |= clk_register(clks[i]);
152 * force the parent clock to propagate so that these clocks will
153 * automatically figure out their rate. We cheat by handing the
154 * parent clock its current rate and forcing child propagation.
155 */
156 clk_set_rate(clk, clk_get_rate(clk));
157 118
158 clk_put(clk); 119 if (!ret)
120 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
121 &div4_table);
122 if (!ret)
123 ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
159 124
160 return 0; 125 return ret;
161} 126}
162arch_initcall(sh7785_clk_init);
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
index f84a9c134471..a0e8869071ac 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7786.c
@@ -36,30 +36,30 @@ static struct clk_ops sh7786_master_clk_ops = {
36 .init = master_clk_init, 36 .init = master_clk_init,
37}; 37};
38 38
39static void module_clk_recalc(struct clk *clk) 39static unsigned long module_clk_recalc(struct clk *clk)
40{ 40{
41 int idx = (ctrl_inl(FRQMR1) & 0x000f); 41 int idx = (ctrl_inl(FRQMR1) & 0x000f);
42 clk->rate = clk->parent->rate / pfc_divisors[idx]; 42 return clk->parent->rate / pfc_divisors[idx];
43} 43}
44 44
45static struct clk_ops sh7786_module_clk_ops = { 45static struct clk_ops sh7786_module_clk_ops = {
46 .recalc = module_clk_recalc, 46 .recalc = module_clk_recalc,
47}; 47};
48 48
49static void bus_clk_recalc(struct clk *clk) 49static unsigned long bus_clk_recalc(struct clk *clk)
50{ 50{
51 int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f); 51 int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
52 clk->rate = clk->parent->rate / bfc_divisors[idx]; 52 return clk->parent->rate / bfc_divisors[idx];
53} 53}
54 54
55static struct clk_ops sh7786_bus_clk_ops = { 55static struct clk_ops sh7786_bus_clk_ops = {
56 .recalc = bus_clk_recalc, 56 .recalc = bus_clk_recalc,
57}; 57};
58 58
59static void cpu_clk_recalc(struct clk *clk) 59static unsigned long cpu_clk_recalc(struct clk *clk)
60{ 60{
61 int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003); 61 int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
62 clk->rate = clk->parent->rate / ifc_divisors[idx]; 62 return clk->parent->rate / ifc_divisors[idx];
63} 63}
64 64
65static struct clk_ops sh7786_cpu_clk_ops = { 65static struct clk_ops sh7786_cpu_clk_ops = {
@@ -79,10 +79,10 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
79 *ops = sh7786_clk_ops[idx]; 79 *ops = sh7786_clk_ops[idx];
80} 80}
81 81
82static void shyway_clk_recalc(struct clk *clk) 82static unsigned long shyway_clk_recalc(struct clk *clk)
83{ 83{
84 int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003); 84 int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
85 clk->rate = clk->parent->rate / sfc_divisors[idx]; 85 return clk->parent->rate / sfc_divisors[idx];
86} 86}
87 87
88static struct clk_ops sh7786_shyway_clk_ops = { 88static struct clk_ops sh7786_shyway_clk_ops = {
@@ -91,14 +91,14 @@ static struct clk_ops sh7786_shyway_clk_ops = {
91 91
92static struct clk sh7786_shyway_clk = { 92static struct clk sh7786_shyway_clk = {
93 .name = "shyway_clk", 93 .name = "shyway_clk",
94 .flags = CLK_ALWAYS_ENABLED, 94 .flags = CLK_ENABLE_ON_INIT,
95 .ops = &sh7786_shyway_clk_ops, 95 .ops = &sh7786_shyway_clk_ops,
96}; 96};
97 97
98static void ddr_clk_recalc(struct clk *clk) 98static unsigned long ddr_clk_recalc(struct clk *clk)
99{ 99{
100 int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003); 100 int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
101 clk->rate = clk->parent->rate / mfc_divisors[idx]; 101 return clk->parent->rate / mfc_divisors[idx];
102} 102}
103 103
104static struct clk_ops sh7786_ddr_clk_ops = { 104static struct clk_ops sh7786_ddr_clk_ops = {
@@ -107,7 +107,7 @@ static struct clk_ops sh7786_ddr_clk_ops = {
107 107
108static struct clk sh7786_ddr_clk = { 108static struct clk sh7786_ddr_clk = {
109 .name = "ddr_clk", 109 .name = "ddr_clk",
110 .flags = CLK_ALWAYS_ENABLED, 110 .flags = CLK_ENABLE_ON_INIT,
111 .ops = &sh7786_ddr_clk_ops, 111 .ops = &sh7786_ddr_clk_ops,
112}; 112};
113 113
@@ -120,29 +120,22 @@ static struct clk *sh7786_onchip_clocks[] = {
120 &sh7786_ddr_clk, 120 &sh7786_ddr_clk,
121}; 121};
122 122
123static int __init sh7786_clk_init(void) 123int __init arch_clk_init(void)
124{ 124{
125 struct clk *clk = clk_get(NULL, "master_clk"); 125 struct clk *clk;
126 int i; 126 int i, ret = 0;
127 127
128 cpg_clk_init();
129
130 clk = clk_get(NULL, "master_clk");
128 for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) { 131 for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
129 struct clk *clkp = sh7786_onchip_clocks[i]; 132 struct clk *clkp = sh7786_onchip_clocks[i];
130 133
131 clkp->parent = clk; 134 clkp->parent = clk;
132 clk_register(clkp); 135 ret |= clk_register(clkp);
133 clk_enable(clkp);
134 } 136 }
135 137
136 /*
137 * Now that we have the rest of the clocks registered, we need to
138 * force the parent clock to propagate so that these clocks will
139 * automatically figure out their rate. We cheat by handing the
140 * parent clock its current rate and forcing child propagation.
141 */
142 clk_set_rate(clk, clk_get_rate(clk));
143
144 clk_put(clk); 138 clk_put(clk);
145 139
146 return 0; 140 return ret;
147} 141}
148arch_initcall(sh7786_clk_init);
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index c630b29e06a8..23c27d32d982 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -40,30 +40,30 @@ static struct clk_ops shx3_master_clk_ops = {
40 .init = master_clk_init, 40 .init = master_clk_init,
41}; 41};
42 42
43static void module_clk_recalc(struct clk *clk) 43static unsigned long module_clk_recalc(struct clk *clk)
44{ 44{
45 int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK); 45 int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK);
46 clk->rate = clk->parent->rate / pfc_divisors[idx]; 46 return clk->parent->rate / pfc_divisors[idx];
47} 47}
48 48
49static struct clk_ops shx3_module_clk_ops = { 49static struct clk_ops shx3_module_clk_ops = {
50 .recalc = module_clk_recalc, 50 .recalc = module_clk_recalc,
51}; 51};
52 52
53static void bus_clk_recalc(struct clk *clk) 53static unsigned long bus_clk_recalc(struct clk *clk)
54{ 54{
55 int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK); 55 int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK);
56 clk->rate = clk->parent->rate / bfc_divisors[idx]; 56 return clk->parent->rate / bfc_divisors[idx];
57} 57}
58 58
59static struct clk_ops shx3_bus_clk_ops = { 59static struct clk_ops shx3_bus_clk_ops = {
60 .recalc = bus_clk_recalc, 60 .recalc = bus_clk_recalc,
61}; 61};
62 62
63static void cpu_clk_recalc(struct clk *clk) 63static unsigned long cpu_clk_recalc(struct clk *clk)
64{ 64{
65 int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK); 65 int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK);
66 clk->rate = clk->parent->rate / ifc_divisors[idx]; 66 return clk->parent->rate / ifc_divisors[idx];
67} 67}
68 68
69static struct clk_ops shx3_cpu_clk_ops = { 69static struct clk_ops shx3_cpu_clk_ops = {
@@ -83,10 +83,10 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
83 *ops = shx3_clk_ops[idx]; 83 *ops = shx3_clk_ops[idx];
84} 84}
85 85
86static void shyway_clk_recalc(struct clk *clk) 86static unsigned long shyway_clk_recalc(struct clk *clk)
87{ 87{
88 int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK); 88 int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK);
89 clk->rate = clk->parent->rate / cfc_divisors[idx]; 89 return clk->parent->rate / cfc_divisors[idx];
90} 90}
91 91
92static struct clk_ops shx3_shyway_clk_ops = { 92static struct clk_ops shx3_shyway_clk_ops = {
@@ -95,7 +95,7 @@ static struct clk_ops shx3_shyway_clk_ops = {
95 95
96static struct clk shx3_shyway_clk = { 96static struct clk shx3_shyway_clk = {
97 .name = "shyway_clk", 97 .name = "shyway_clk",
98 .flags = CLK_ALWAYS_ENABLED, 98 .flags = CLK_ENABLE_ON_INIT,
99 .ops = &shx3_shyway_clk_ops, 99 .ops = &shx3_shyway_clk_ops,
100}; 100};
101 101
@@ -107,29 +107,22 @@ static struct clk *shx3_onchip_clocks[] = {
107 &shx3_shyway_clk, 107 &shx3_shyway_clk,
108}; 108};
109 109
110static int __init shx3_clk_init(void) 110int __init arch_clk_init(void)
111{ 111{
112 struct clk *clk = clk_get(NULL, "master_clk"); 112 struct clk *clk;
113 int i; 113 int i, ret = 0;
114 114
115 cpg_clk_init();
116
117 clk = clk_get(NULL, "master_clk");
115 for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) { 118 for (i = 0; i < ARRAY_SIZE(shx3_onchip_clocks); i++) {
116 struct clk *clkp = shx3_onchip_clocks[i]; 119 struct clk *clkp = shx3_onchip_clocks[i];
117 120
118 clkp->parent = clk; 121 clkp->parent = clk;
119 clk_register(clkp); 122 ret |= clk_register(clkp);
120 clk_enable(clkp);
121 } 123 }
122 124
123 /*
124 * Now that we have the rest of the clocks registered, we need to
125 * force the parent clock to propagate so that these clocks will
126 * automatically figure out their rate. We cheat by handing the
127 * parent clock its current rate and forcing child propagation.
128 */
129 clk_set_rate(clk, clk_get_rate(clk));
130
131 clk_put(clk); 125 clk_put(clk);
132 126
133 return 0; 127 return ret;
134} 128}
135arch_initcall(shx3_clk_init);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
new file mode 100644
index 000000000000..1af0f9586379
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
@@ -0,0 +1,2230 @@
1/*
2 * SH7724 Pinmux
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 *
8 * Based on SH7723 Pinmux
9 * Copyright (C) 2008 Magnus Damm
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/gpio.h>
19#include <cpu/sh7724.h>
20
21enum {
22 PINMUX_RESERVED = 0,
23
24 PINMUX_DATA_BEGIN,
25 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
26 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
27 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
28 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
29 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
30 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
31 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
32 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
33 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
34 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
35 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
36 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
37 PTG5_DATA, PTG4_DATA,
38 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
39 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
40 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
41 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA,
42 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
43 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
44 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
45 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
46 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
47 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
48 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
49 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
50 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
51 PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
52 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
53 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
54 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
55 PTS6_DATA, PTS5_DATA, PTS4_DATA,
56 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
57 PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
58 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
59 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
60 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
61 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
62 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
63 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
64 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
65 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
66 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
67 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
68 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
69 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
70 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
71 PINMUX_DATA_END,
72
73 PINMUX_INPUT_BEGIN,
74 PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
75 PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
76 PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
77 PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
78 PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
79 PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
80 PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
81 PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
82 PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN,
83 PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
84 PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN,
85 PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
86 PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN,
87 PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
88 PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
89 PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
90 PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
91 PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN,
92 PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
93 PTM7_IN, PTM6_IN, PTM5_IN, PTM4_IN,
94 PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
95 PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN,
96 PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
97 PTQ7_IN, PTQ6_IN, PTQ5_IN, PTQ4_IN,
98 PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
99 PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
100 PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
101 PTS6_IN, PTS5_IN, PTS4_IN,
102 PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
103 PTT7_IN, PTT6_IN, PTT5_IN, PTT4_IN,
104 PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
105 PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN,
106 PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
107 PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN,
108 PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
109 PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN,
110 PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
111 PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN,
112 PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
113 PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN,
114 PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN,
115 PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN,
116 PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
117 PINMUX_INPUT_END,
118
119 PINMUX_INPUT_PULLUP_BEGIN,
120 PTA7_IN_PU, PTA6_IN_PU, PTA5_IN_PU, PTA4_IN_PU,
121 PTA3_IN_PU, PTA2_IN_PU, PTA1_IN_PU, PTA0_IN_PU,
122 PTB7_IN_PU, PTB6_IN_PU, PTB5_IN_PU, PTB4_IN_PU,
123 PTB3_IN_PU, PTB2_IN_PU, PTB1_IN_PU, PTB0_IN_PU,
124 PTC7_IN_PU, PTC6_IN_PU, PTC5_IN_PU, PTC4_IN_PU,
125 PTC3_IN_PU, PTC2_IN_PU, PTC1_IN_PU, PTC0_IN_PU,
126 PTD7_IN_PU, PTD6_IN_PU, PTD5_IN_PU, PTD4_IN_PU,
127 PTD3_IN_PU, PTD2_IN_PU, PTD1_IN_PU, PTD0_IN_PU,
128 PTE7_IN_PU, PTE6_IN_PU, PTE5_IN_PU, PTE4_IN_PU,
129 PTE3_IN_PU, PTE2_IN_PU, PTE1_IN_PU, PTE0_IN_PU,
130 PTF7_IN_PU, PTF6_IN_PU, PTF5_IN_PU, PTF4_IN_PU,
131 PTF3_IN_PU, PTF2_IN_PU, PTF1_IN_PU, PTF0_IN_PU,
132 PTH7_IN_PU, PTH6_IN_PU, PTH5_IN_PU, PTH4_IN_PU,
133 PTH3_IN_PU, PTH2_IN_PU, PTH1_IN_PU, PTH0_IN_PU,
134 PTJ3_IN_PU, PTJ2_IN_PU, PTJ1_IN_PU, PTJ0_IN_PU,
135 PTK7_IN_PU, PTK6_IN_PU, PTK5_IN_PU, PTK4_IN_PU,
136 PTK3_IN_PU, PTK2_IN_PU, PTK1_IN_PU, PTK0_IN_PU,
137 PTL7_IN_PU, PTL6_IN_PU, PTL5_IN_PU, PTL4_IN_PU,
138 PTL3_IN_PU, PTL2_IN_PU, PTL1_IN_PU, PTL0_IN_PU,
139 PTM7_IN_PU, PTM6_IN_PU, PTM5_IN_PU, PTM4_IN_PU,
140 PTM3_IN_PU, PTM2_IN_PU, PTM1_IN_PU, PTM0_IN_PU,
141 PTN7_IN_PU, PTN6_IN_PU, PTN5_IN_PU, PTN4_IN_PU,
142 PTN3_IN_PU, PTN2_IN_PU, PTN1_IN_PU, PTN0_IN_PU,
143 PTQ7_IN_PU, PTQ6_IN_PU, PTQ5_IN_PU, PTQ4_IN_PU,
144 PTQ3_IN_PU, PTQ2_IN_PU, PTQ1_IN_PU, PTQ0_IN_PU,
145 PTR7_IN_PU, PTR6_IN_PU, PTR5_IN_PU, PTR4_IN_PU,
146 PTR3_IN_PU, PTR2_IN_PU, PTR1_IN_PU, PTR0_IN_PU,
147 PTS6_IN_PU, PTS5_IN_PU, PTS4_IN_PU,
148 PTS3_IN_PU, PTS2_IN_PU, PTS1_IN_PU, PTS0_IN_PU,
149 PTT7_IN_PU, PTT6_IN_PU, PTT5_IN_PU, PTT4_IN_PU,
150 PTT3_IN_PU, PTT2_IN_PU, PTT1_IN_PU, PTT0_IN_PU,
151 PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU,
152 PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
153 PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU,
154 PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU,
155 PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU,
156 PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU,
157 PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU,
158 PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU,
159 PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU,
160 PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU,
161 PTZ7_IN_PU, PTZ6_IN_PU, PTZ5_IN_PU, PTZ4_IN_PU,
162 PTZ3_IN_PU, PTZ2_IN_PU, PTZ1_IN_PU, PTZ0_IN_PU,
163 PINMUX_INPUT_PULLUP_END,
164
165 PINMUX_OUTPUT_BEGIN,
166 PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
167 PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
168 PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
169 PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
170 PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
171 PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
172 PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
173 PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
174 PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT,
175 PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
176 PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT,
177 PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT,
178 PTG5_OUT, PTG4_OUT,
179 PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
180 PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
181 PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
182 PTJ7_OUT, PTJ6_OUT, PTJ5_OUT,
183 PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
184 PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
185 PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
186 PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT,
187 PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
188 PTM7_OUT, PTM6_OUT, PTM5_OUT, PTM4_OUT,
189 PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
190 PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT,
191 PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
192 PTQ7_OUT, PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
193 PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
194 PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
195 PTR1_OUT, PTR0_OUT,
196 PTS6_OUT, PTS5_OUT, PTS4_OUT,
197 PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
198 PTT7_OUT, PTT6_OUT, PTT5_OUT, PTT4_OUT,
199 PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
200 PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT,
201 PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
202 PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT,
203 PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
204 PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT,
205 PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
206 PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT,
207 PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
208 PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT,
209 PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
210 PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT,
211 PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT,
212 PINMUX_OUTPUT_END,
213
214 PINMUX_FUNCTION_BEGIN,
215 PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
216 PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
217 PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
218 PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
219 PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
220 PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
221 PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
222 PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
223 PTE7_FN, PTE6_FN, PTE5_FN, PTE4_FN,
224 PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
225 PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN,
226 PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
227 PTG5_FN, PTG4_FN,
228 PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
229 PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN,
230 PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
231 PTJ7_FN, PTJ6_FN, PTJ5_FN,
232 PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
233 PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
234 PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
235 PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN,
236 PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
237 PTM7_FN, PTM6_FN, PTM5_FN, PTM4_FN,
238 PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
239 PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN,
240 PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
241 PTQ7_FN, PTQ6_FN, PTQ5_FN, PTQ4_FN,
242 PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
243 PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
244 PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
245 PTS6_FN, PTS5_FN, PTS4_FN,
246 PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
247 PTT7_FN, PTT6_FN, PTT5_FN, PTT4_FN,
248 PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
249 PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN,
250 PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
251 PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN,
252 PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
253 PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN,
254 PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN,
255 PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN,
256 PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN,
257 PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN,
258 PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN,
259 PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
260 PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
261
262
263 PSA15_0, PSA15_1,
264 PSA14_0, PSA14_1,
265 PSA13_0, PSA13_1,
266 PSA12_0, PSA12_1,
267 PSA10_0, PSA10_1,
268 PSA9_0, PSA9_1,
269 PSA8_0, PSA8_1,
270 PSA7_0, PSA7_1,
271 PSA6_0, PSA6_1,
272 PSA5_0, PSA5_1,
273 PSA3_0, PSA3_1,
274 PSA2_0, PSA2_1,
275 PSA1_0, PSA1_1,
276 PSA0_0, PSA0_1,
277
278 PSB14_0, PSB14_1,
279 PSB13_0, PSB13_1,
280 PSB12_0, PSB12_1,
281 PSB11_0, PSB11_1,
282 PSB10_0, PSB10_1,
283 PSB9_0, PSB9_1,
284 PSB8_0, PSB8_1,
285 PSB7_0, PSB7_1,
286 PSB6_0, PSB6_1,
287 PSB5_0, PSB5_1,
288 PSB4_0, PSB4_1,
289 PSB3_0, PSB3_1,
290 PSB2_0, PSB2_1,
291 PSB1_0, PSB1_1,
292 PSB0_0, PSB0_1,
293
294 PSC15_0, PSC15_1,
295 PSC14_0, PSC14_1,
296 PSC13_0, PSC13_1,
297 PSC12_0, PSC12_1,
298 PSC11_0, PSC11_1,
299 PSC10_0, PSC10_1,
300 PSC9_0, PSC9_1,
301 PSC8_0, PSC8_1,
302 PSC7_0, PSC7_1,
303 PSC6_0, PSC6_1,
304 PSC5_0, PSC5_1,
305 PSC4_0, PSC4_1,
306 PSC2_0, PSC2_1,
307 PSC1_0, PSC1_1,
308 PSC0_0, PSC0_1,
309
310 PSD15_0, PSD15_1,
311 PSD14_0, PSD14_1,
312 PSD13_0, PSD13_1,
313 PSD12_0, PSD12_1,
314 PSD11_0, PSD11_1,
315 PSD10_0, PSD10_1,
316 PSD9_0, PSD9_1,
317 PSD8_0, PSD8_1,
318 PSD7_0, PSD7_1,
319 PSD6_0, PSD6_1,
320 PSD5_0, PSD5_1,
321 PSD4_0, PSD4_1,
322 PSD3_0, PSD3_1,
323 PSD2_0, PSD2_1,
324 PSD1_0, PSD1_1,
325 PSD0_0, PSD0_1,
326
327 PSE15_0, PSE15_1,
328 PSE14_0, PSE14_1,
329 PSE13_0, PSE13_1,
330 PSE12_0, PSE12_1,
331 PSE11_0, PSE11_1,
332 PSE10_0, PSE10_1,
333 PSE9_0, PSE9_1,
334 PSE8_0, PSE8_1,
335 PSE7_0, PSE7_1,
336 PSE6_0, PSE6_1,
337 PSE5_0, PSE5_1,
338 PSE4_0, PSE4_1,
339 PSE3_0, PSE3_1,
340 PSE2_0, PSE2_1,
341 PSE1_0, PSE1_1,
342 PSE0_0, PSE0_1,
343 PINMUX_FUNCTION_END,
344
345 PINMUX_MARK_BEGIN,
346 /*PTA*/
347 D23_MARK, KEYOUT2_MARK, IDED15_MARK,
348 D22_MARK, KEYOUT1_MARK, IDED14_MARK,
349 D21_MARK, KEYOUT0_MARK, IDED13_MARK,
350 D20_MARK, KEYIN4_MARK, IDED12_MARK,
351 D19_MARK, KEYIN3_MARK, IDED11_MARK,
352 D18_MARK, KEYIN2_MARK, IDED10_MARK,
353 D17_MARK, KEYIN1_MARK, IDED9_MARK,
354 D16_MARK, KEYIN0_MARK, IDED8_MARK,
355
356 /*PTB*/
357 D31_MARK, TPUTO1_MARK, IDEA1_MARK,
358 D30_MARK, TPUTO0_MARK, IDEA0_MARK,
359 D29_MARK, IODREQ_MARK,
360 D28_MARK, IDECS0_MARK,
361 D27_MARK, IDECS1_MARK,
362 D26_MARK, KEYOUT5_IN5_MARK, IDEIORD_MARK,
363 D25_MARK, KEYOUT4_IN6_MARK, IDEIOWR_MARK,
364 D24_MARK, KEYOUT3_MARK, IDEINT_MARK,
365
366 /*PTC*/
367 LCDD7_MARK,
368 LCDD6_MARK,
369 LCDD5_MARK,
370 LCDD4_MARK,
371 LCDD3_MARK,
372 LCDD2_MARK,
373 LCDD1_MARK,
374 LCDD0_MARK,
375
376 /*PTD*/
377 LCDD15_MARK,
378 LCDD14_MARK,
379 LCDD13_MARK,
380 LCDD12_MARK,
381 LCDD11_MARK,
382 LCDD10_MARK,
383 LCDD9_MARK,
384 LCDD8_MARK,
385
386 /*PTE*/
387 FSIMCKB_MARK,
388 FSIMCKA_MARK,
389 LCDD21_MARK, SCIF2_L_TXD_MARK,
390 LCDD20_MARK, SCIF4_SCK_MARK,
391 LCDD19_MARK, SCIF4_RXD_MARK,
392 LCDD18_MARK, SCIF4_TXD_MARK,
393 LCDD17_MARK,
394 LCDD16_MARK,
395
396 /*PTF*/
397 LCDVSYN_MARK,
398 LCDDISP_MARK, LCDRS_MARK,
399 LCDHSYN_MARK, LCDCS_MARK,
400 LCDDON_MARK,
401 LCDDCK_MARK, LCDWR_MARK,
402 LCDVEPWC_MARK, SCIF0_TXD_MARK,
403 LCDD23_MARK, SCIF2_L_SCK_MARK,
404 LCDD22_MARK, SCIF2_L_RXD_MARK,
405
406 /*PTG*/
407 AUDCK_MARK,
408 AUDSYNC_MARK,
409 AUDATA3_MARK,
410 AUDATA2_MARK,
411 AUDATA1_MARK,
412 AUDATA0_MARK,
413
414 /*PTH*/
415 VIO0_VD_MARK,
416 VIO0_CLK_MARK,
417 VIO0_D7_MARK,
418 VIO0_D6_MARK,
419 VIO0_D5_MARK,
420 VIO0_D4_MARK,
421 VIO0_D3_MARK,
422 VIO0_D2_MARK,
423
424 /*PTJ*/
425 PDSTATUS_MARK,
426 STATUS2_MARK,
427 STATUS0_MARK,
428 A25_MARK, BS_MARK,
429 A24_MARK,
430 A23_MARK,
431 A22_MARK,
432
433 /*PTK*/
434 VIO1_D5_MARK, VIO0_D13_MARK, IDED5_MARK,
435 VIO1_D4_MARK, VIO0_D12_MARK, IDED4_MARK,
436 VIO1_D3_MARK, VIO0_D11_MARK, IDED3_MARK,
437 VIO1_D2_MARK, VIO0_D10_MARK, IDED2_MARK,
438 VIO1_D1_MARK, VIO0_D9_MARK, IDED1_MARK,
439 VIO1_D0_MARK, VIO0_D8_MARK, IDED0_MARK,
440 VIO0_FLD_MARK,
441 VIO0_HD_MARK,
442
443 /*PTL*/
444 DV_D5_MARK, SCIF3_V_SCK_MARK, RMII_RXD0_MARK,
445 DV_D4_MARK, SCIF3_V_RXD_MARK, RMII_RXD1_MARK,
446 DV_D3_MARK, SCIF3_V_TXD_MARK, RMII_REF_CLK_MARK,
447 DV_D2_MARK, SCIF1_SCK_MARK, RMII_TX_EN_MARK,
448 DV_D1_MARK, SCIF1_RXD_MARK, RMII_TXD0_MARK,
449 DV_D0_MARK, SCIF1_TXD_MARK, RMII_TXD1_MARK,
450 DV_D15_MARK,
451 DV_D14_MARK, MSIOF0_MCK_MARK,
452
453 /*PTM*/
454 DV_D13_MARK, MSIOF0_TSCK_MARK,
455 DV_D12_MARK, MSIOF0_RXD_MARK,
456 DV_D11_MARK, MSIOF0_TXD_MARK,
457 DV_D10_MARK, MSIOF0_TSYNC_MARK,
458 DV_D9_MARK, MSIOF0_SS1_MARK, MSIOF0_RSCK_MARK,
459 DV_D8_MARK, MSIOF0_SS2_MARK, MSIOF0_RSYNC_MARK,
460 LCDVCPWC_MARK, SCIF0_RXD_MARK,
461 LCDRD_MARK, SCIF0_SCK_MARK,
462
463 /*PTN*/
464 VIO0_D1_MARK,
465 VIO0_D0_MARK,
466 DV_CLKI_MARK,
467 DV_CLK_MARK, SCIF2_V_SCK_MARK,
468 DV_VSYNC_MARK, SCIF2_V_RXD_MARK,
469 DV_HSYNC_MARK, SCIF2_V_TXD_MARK,
470 DV_D7_MARK, SCIF3_V_CTS_MARK, RMII_RX_ER_MARK,
471 DV_D6_MARK, SCIF3_V_RTS_MARK, RMII_CRS_DV_MARK,
472
473 /*PTQ*/
474 D7_MARK,
475 D6_MARK,
476 D5_MARK,
477 D4_MARK,
478 D3_MARK,
479 D2_MARK,
480 D1_MARK,
481 D0_MARK,
482
483 /*PTR*/
484 CS6B_CE1B_MARK,
485 CS6A_CE2B_MARK,
486 CS5B_CE1A_MARK,
487 CS5A_CE2A_MARK,
488 IOIS16_MARK, LCDLCLK_MARK,
489 WAIT_MARK,
490 WE3_ICIOWR_MARK, TPUTO3_MARK, TPUTI3_MARK,
491 WE2_ICIORD_MARK, TPUTO2_MARK, IDEA2_MARK,
492
493 /*PTS*/
494 VIO_CKO_MARK,
495 VIO1_FLD_MARK, TPUTI2_MARK, IDEIORDY_MARK,
496 VIO1_HD_MARK, SCIF5_SCK_MARK,
497 VIO1_VD_MARK, SCIF5_RXD_MARK,
498 VIO1_CLK_MARK, SCIF5_TXD_MARK,
499 VIO1_D7_MARK, VIO0_D15_MARK, IDED7_MARK,
500 VIO1_D6_MARK, VIO0_D14_MARK, IDED6_MARK,
501
502 /*PTT*/
503 D15_MARK,
504 D14_MARK,
505 D13_MARK,
506 D12_MARK,
507 D11_MARK,
508 D10_MARK,
509 D9_MARK,
510 D8_MARK,
511
512 /*PTU*/
513 DMAC_DACK0_MARK,
514 DMAC_DREQ0_MARK,
515 FSIOASD_MARK,
516 FSIIABCK_MARK,
517 FSIIALRCK_MARK,
518 FSIOABCK_MARK,
519 FSIOALRCK_MARK,
520 CLKAUDIOAO_MARK,
521
522 /*PTV*/
523 FSIIBSD_MARK, MSIOF1_SS2_MARK, MSIOF1_RSYNC_MARK,
524 FSIOBSD_MARK, MSIOF1_SS1_MARK, MSIOF1_RSCK_MARK,
525 FSIIBBCK_MARK, MSIOF1_RXD_MARK,
526 FSIIBLRCK_MARK, MSIOF1_TSYNC_MARK,
527 FSIOBBCK_MARK, MSIOF1_TSCK_MARK,
528 FSIOBLRCK_MARK, MSIOF1_TXD_MARK,
529 CLKAUDIOBO_MARK, MSIOF1_MCK_MARK,
530 FSIIASD_MARK,
531
532 /*PTW*/
533 MMC_D7_MARK, SDHI1CD_MARK, IODACK_MARK,
534 MMC_D6_MARK, SDHI1WP_MARK, IDERST_MARK,
535 MMC_D5_MARK, SDHI1D3_MARK, EXBUF_ENB_MARK,
536 MMC_D4_MARK, SDHI1D2_MARK, DIRECTION_MARK,
537 MMC_D3_MARK, SDHI1D1_MARK,
538 MMC_D2_MARK, SDHI1D0_MARK,
539 MMC_D1_MARK, SDHI1CMD_MARK,
540 MMC_D0_MARK, SDHI1CLK_MARK,
541
542 /*PTX*/
543 DMAC_DACK1_MARK, IRDA_OUT_MARK,
544 DMAC_DREQ1_MARK, IRDA_IN_MARK,
545 TSIF_TS0_SDAT_MARK, LNKSTA_MARK,
546 TSIF_TS0_SCK_MARK, MDIO_MARK,
547 TSIF_TS0_SDEN_MARK, MDC_MARK,
548 TSIF_TS0_SPSYNC_MARK,
549 MMC_CLK_MARK,
550 MMC_CMD_MARK,
551
552 /*PTY*/
553 SDHI0CD_MARK,
554 SDHI0WP_MARK,
555 SDHI0D3_MARK,
556 SDHI0D2_MARK,
557 SDHI0D1_MARK,
558 SDHI0D0_MARK,
559 SDHI0CMD_MARK,
560 SDHI0CLK_MARK,
561
562 /*PTZ*/
563 INTC_IRQ7_MARK, SCIF3_I_CTS_MARK,
564 INTC_IRQ6_MARK, SCIF3_I_RTS_MARK,
565 INTC_IRQ5_MARK, SCIF3_I_SCK_MARK,
566 INTC_IRQ4_MARK, SCIF3_I_RXD_MARK,
567 INTC_IRQ3_MARK, SCIF3_I_TXD_MARK,
568 INTC_IRQ2_MARK,
569 INTC_IRQ1_MARK,
570 INTC_IRQ0_MARK,
571 PINMUX_MARK_END,
572};
573
574static pinmux_enum_t pinmux_data[] = {
575 /* PTA GPIO */
576 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
577 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
578 PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT, PTA5_IN_PU),
579 PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT, PTA4_IN_PU),
580 PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT, PTA3_IN_PU),
581 PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT, PTA2_IN_PU),
582 PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT, PTA1_IN_PU),
583 PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT, PTA0_IN_PU),
584
585 /* PTB GPIO */
586 PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT, PTB7_IN_PU),
587 PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT, PTB6_IN_PU),
588 PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT, PTB5_IN_PU),
589 PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT, PTB4_IN_PU),
590 PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT, PTB3_IN_PU),
591 PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT, PTB2_IN_PU),
592 PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT, PTB1_IN_PU),
593 PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT, PTB0_IN_PU),
594
595 /* PTC GPIO */
596 PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT, PTC7_IN_PU),
597 PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT, PTC6_IN_PU),
598 PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT, PTC5_IN_PU),
599 PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT, PTC4_IN_PU),
600 PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT, PTC3_IN_PU),
601 PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT, PTC2_IN_PU),
602 PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT, PTC1_IN_PU),
603 PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT, PTC0_IN_PU),
604
605 /* PTD GPIO */
606 PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT, PTD7_IN_PU),
607 PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT, PTD6_IN_PU),
608 PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT, PTD5_IN_PU),
609 PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT, PTD4_IN_PU),
610 PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT, PTD3_IN_PU),
611 PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT, PTD2_IN_PU),
612 PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT, PTD1_IN_PU),
613 PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT, PTD0_IN_PU),
614
615 /* PTE GPIO */
616 PINMUX_DATA(PTE7_DATA, PTE7_IN, PTE7_OUT, PTE7_IN_PU),
617 PINMUX_DATA(PTE6_DATA, PTE6_IN, PTE6_OUT, PTE6_IN_PU),
618 PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT, PTE5_IN_PU),
619 PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT, PTE4_IN_PU),
620 PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT, PTE3_IN_PU),
621 PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT, PTE2_IN_PU),
622 PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT, PTE1_IN_PU),
623 PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT, PTE0_IN_PU),
624
625 /* PTF GPIO */
626 PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT, PTF7_IN_PU),
627 PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT, PTF6_IN_PU),
628 PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT, PTF5_IN_PU),
629 PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT, PTF4_IN_PU),
630 PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT, PTF3_IN_PU),
631 PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT, PTF2_IN_PU),
632 PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT, PTF1_IN_PU),
633 PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT, PTF0_IN_PU),
634
635 /* PTG GPIO */
636 PINMUX_DATA(PTG5_DATA, PTG5_OUT),
637 PINMUX_DATA(PTG4_DATA, PTG4_OUT),
638 PINMUX_DATA(PTG3_DATA, PTG3_OUT),
639 PINMUX_DATA(PTG2_DATA, PTG2_OUT),
640 PINMUX_DATA(PTG1_DATA, PTG1_OUT),
641 PINMUX_DATA(PTG0_DATA, PTG0_OUT),
642
643 /* PTH GPIO */
644 PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT, PTH7_IN_PU),
645 PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT, PTH6_IN_PU),
646 PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT, PTH5_IN_PU),
647 PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT, PTH4_IN_PU),
648 PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT, PTH3_IN_PU),
649 PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT, PTH2_IN_PU),
650 PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT, PTH1_IN_PU),
651 PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT, PTH0_IN_PU),
652
653 /* PTJ GPIO */
654 PINMUX_DATA(PTJ7_DATA, PTJ7_OUT),
655 PINMUX_DATA(PTJ6_DATA, PTJ6_OUT),
656 PINMUX_DATA(PTJ5_DATA, PTJ5_OUT),
657 PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT, PTJ3_IN_PU),
658 PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT, PTJ2_IN_PU),
659 PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT, PTJ1_IN_PU),
660 PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT, PTJ0_IN_PU),
661
662 /* PTK GPIO */
663 PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT, PTK7_IN_PU),
664 PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT, PTK6_IN_PU),
665 PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT, PTK5_IN_PU),
666 PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT, PTK4_IN_PU),
667 PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT, PTK3_IN_PU),
668 PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT, PTK2_IN_PU),
669 PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT, PTK1_IN_PU),
670 PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT, PTK0_IN_PU),
671
672 /* PTL GPIO */
673 PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT, PTL7_IN_PU),
674 PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT, PTL6_IN_PU),
675 PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT, PTL5_IN_PU),
676 PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT, PTL4_IN_PU),
677 PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT, PTL3_IN_PU),
678 PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT, PTL2_IN_PU),
679 PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT, PTL1_IN_PU),
680 PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT, PTL0_IN_PU),
681
682 /* PTM GPIO */
683 PINMUX_DATA(PTM7_DATA, PTM7_IN, PTM7_OUT, PTM7_IN_PU),
684 PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT, PTM6_IN_PU),
685 PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT, PTM5_IN_PU),
686 PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT, PTM4_IN_PU),
687 PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT, PTM3_IN_PU),
688 PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT, PTM2_IN_PU),
689 PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT, PTM1_IN_PU),
690 PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT, PTM0_IN_PU),
691
692 /* PTN GPIO */
693 PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT, PTN7_IN_PU),
694 PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT, PTN6_IN_PU),
695 PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT, PTN5_IN_PU),
696 PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT, PTN4_IN_PU),
697 PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT, PTN3_IN_PU),
698 PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT, PTN2_IN_PU),
699 PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT, PTN1_IN_PU),
700 PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT, PTN0_IN_PU),
701
702 /* PTQ GPIO */
703 PINMUX_DATA(PTQ7_DATA, PTQ7_IN, PTQ7_OUT, PTQ7_IN_PU),
704 PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT, PTQ6_IN_PU),
705 PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT, PTQ5_IN_PU),
706 PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT, PTQ4_IN_PU),
707 PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT, PTQ3_IN_PU),
708 PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT, PTQ2_IN_PU),
709 PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT, PTQ1_IN_PU),
710 PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT, PTQ0_IN_PU),
711
712 /* PTR GPIO */
713 PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT, PTR7_IN_PU),
714 PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT, PTR6_IN_PU),
715 PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT, PTR5_IN_PU),
716 PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT, PTR4_IN_PU),
717 PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_IN_PU),
718 PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_IN_PU),
719 PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT, PTR1_IN_PU),
720 PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT, PTR0_IN_PU),
721
722 /* PTS GPIO */
723 PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT, PTS6_IN_PU),
724 PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT, PTS5_IN_PU),
725 PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT, PTS4_IN_PU),
726 PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT, PTS3_IN_PU),
727 PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT, PTS2_IN_PU),
728 PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT, PTS1_IN_PU),
729 PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT, PTS0_IN_PU),
730
731 /* PTT GPIO */
732 PINMUX_DATA(PTT7_DATA, PTT7_IN, PTT7_OUT, PTT7_IN_PU),
733 PINMUX_DATA(PTT6_DATA, PTT6_IN, PTT6_OUT, PTT6_IN_PU),
734 PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT, PTT5_IN_PU),
735 PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT, PTT4_IN_PU),
736 PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT, PTT3_IN_PU),
737 PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT, PTT2_IN_PU),
738 PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT, PTT1_IN_PU),
739 PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT, PTT0_IN_PU),
740
741 /* PTU GPIO */
742 PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT, PTU7_IN_PU),
743 PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT, PTU6_IN_PU),
744 PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT, PTU5_IN_PU),
745 PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT, PTU4_IN_PU),
746 PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT, PTU3_IN_PU),
747 PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT, PTU2_IN_PU),
748 PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT, PTU1_IN_PU),
749 PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT, PTU0_IN_PU),
750
751 /* PTV GPIO */
752 PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT, PTV7_IN_PU),
753 PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT, PTV6_IN_PU),
754 PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT, PTV5_IN_PU),
755 PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT, PTV4_IN_PU),
756 PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT, PTV3_IN_PU),
757 PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT, PTV2_IN_PU),
758 PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT, PTV1_IN_PU),
759 PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT, PTV0_IN_PU),
760
761 /* PTW GPIO */
762 PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT, PTW7_IN_PU),
763 PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT, PTW6_IN_PU),
764 PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT, PTW5_IN_PU),
765 PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT, PTW4_IN_PU),
766 PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT, PTW3_IN_PU),
767 PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT, PTW2_IN_PU),
768 PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT, PTW1_IN_PU),
769 PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT, PTW0_IN_PU),
770
771 /* PTX GPIO */
772 PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT, PTX7_IN_PU),
773 PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT, PTX6_IN_PU),
774 PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT, PTX5_IN_PU),
775 PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT, PTX4_IN_PU),
776 PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT, PTX3_IN_PU),
777 PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT, PTX2_IN_PU),
778 PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT, PTX1_IN_PU),
779 PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT, PTX0_IN_PU),
780
781 /* PTY GPIO */
782 PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT, PTY7_IN_PU),
783 PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT, PTY6_IN_PU),
784 PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT, PTY5_IN_PU),
785 PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT, PTY4_IN_PU),
786 PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT, PTY3_IN_PU),
787 PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT, PTY2_IN_PU),
788 PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT, PTY1_IN_PU),
789 PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT, PTY0_IN_PU),
790
791 /* PTZ GPIO */
792 PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT, PTZ7_IN_PU),
793 PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT, PTZ6_IN_PU),
794 PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT, PTZ5_IN_PU),
795 PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT, PTZ4_IN_PU),
796 PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT, PTZ3_IN_PU),
797 PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT, PTZ2_IN_PU),
798 PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT, PTZ1_IN_PU),
799 PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT, PTZ0_IN_PU),
800
801 /* PTA FN */
802 PINMUX_DATA(D23_MARK, PSA15_0, PSA14_0, PTA7_FN),
803 PINMUX_DATA(D22_MARK, PSA15_0, PSA14_0, PTA6_FN),
804 PINMUX_DATA(D21_MARK, PSA15_0, PSA14_0, PTA5_FN),
805 PINMUX_DATA(D20_MARK, PSA15_0, PSA14_0, PTA4_FN),
806 PINMUX_DATA(D19_MARK, PSA15_0, PSA14_0, PTA3_FN),
807 PINMUX_DATA(D18_MARK, PSA15_0, PSA14_0, PTA2_FN),
808 PINMUX_DATA(D17_MARK, PSA15_0, PSA14_0, PTA1_FN),
809 PINMUX_DATA(D16_MARK, PSA15_0, PSA14_0, PTA0_FN),
810
811 PINMUX_DATA(KEYOUT2_MARK, PSA15_0, PSA14_1, PTA7_FN),
812 PINMUX_DATA(KEYOUT1_MARK, PSA15_0, PSA14_1, PTA6_FN),
813 PINMUX_DATA(KEYOUT0_MARK, PSA15_0, PSA14_1, PTA5_FN),
814 PINMUX_DATA(KEYIN4_MARK, PSA15_0, PSA14_1, PTA4_FN),
815 PINMUX_DATA(KEYIN3_MARK, PSA15_0, PSA14_1, PTA3_FN),
816 PINMUX_DATA(KEYIN2_MARK, PSA15_0, PSA14_1, PTA2_FN),
817 PINMUX_DATA(KEYIN1_MARK, PSA15_0, PSA14_1, PTA1_FN),
818 PINMUX_DATA(KEYIN0_MARK, PSA15_0, PSA14_1, PTA0_FN),
819
820 PINMUX_DATA(IDED15_MARK, PSA15_1, PSA14_0, PTA7_FN),
821 PINMUX_DATA(IDED14_MARK, PSA15_1, PSA14_0, PTA6_FN),
822 PINMUX_DATA(IDED13_MARK, PSA15_1, PSA14_0, PTA5_FN),
823 PINMUX_DATA(IDED12_MARK, PSA15_1, PSA14_0, PTA4_FN),
824 PINMUX_DATA(IDED11_MARK, PSA15_1, PSA14_0, PTA3_FN),
825 PINMUX_DATA(IDED10_MARK, PSA15_1, PSA14_0, PTA2_FN),
826 PINMUX_DATA(IDED9_MARK, PSA15_1, PSA14_0, PTA1_FN),
827 PINMUX_DATA(IDED8_MARK, PSA15_1, PSA14_0, PTA0_FN),
828
829 /* PTB FN */
830 PINMUX_DATA(D31_MARK, PSE15_0, PSE14_0, PTB7_FN),
831 PINMUX_DATA(D30_MARK, PSE15_0, PSE14_0, PTB6_FN),
832 PINMUX_DATA(D29_MARK, PSE11_0, PTB5_FN),
833 PINMUX_DATA(D28_MARK, PSE11_0, PTB4_FN),
834 PINMUX_DATA(D27_MARK, PSE11_0, PTB3_FN),
835 PINMUX_DATA(D26_MARK, PSA15_0, PSA14_0, PTB2_FN),
836 PINMUX_DATA(D25_MARK, PSA15_0, PSA14_0, PTB1_FN),
837 PINMUX_DATA(D24_MARK, PSA15_0, PSA14_0, PTB0_FN),
838
839 PINMUX_DATA(IDEA1_MARK, PSE15_1, PSE14_0, PTB7_FN),
840 PINMUX_DATA(IDEA0_MARK, PSE15_1, PSE14_0, PTB6_FN),
841 PINMUX_DATA(IODREQ_MARK, PSE11_1, PTB5_FN),
842 PINMUX_DATA(IDECS0_MARK, PSE11_1, PTB4_FN),
843 PINMUX_DATA(IDECS1_MARK, PSE11_1, PTB3_FN),
844 PINMUX_DATA(IDEIORD_MARK, PSA15_1, PSA14_0, PTB2_FN),
845 PINMUX_DATA(IDEIOWR_MARK, PSA15_1, PSA14_0, PTB1_FN),
846 PINMUX_DATA(IDEINT_MARK, PSA15_1, PSA14_0, PTB0_FN),
847
848 PINMUX_DATA(TPUTO1_MARK, PSE15_0, PSE14_1, PTB7_FN),
849 PINMUX_DATA(TPUTO0_MARK, PSE15_0, PSE14_1, PTB6_FN),
850
851 PINMUX_DATA(KEYOUT5_IN5_MARK, PSA15_0, PSA14_1, PTB2_FN),
852 PINMUX_DATA(KEYOUT4_IN6_MARK, PSA15_0, PSA14_1, PTB1_FN),
853 PINMUX_DATA(KEYOUT3_MARK, PSA15_0, PSA14_1, PTB0_FN),
854
855 /* PTC FN */
856 PINMUX_DATA(LCDD7_MARK, PSD5_0, PTC7_FN),
857 PINMUX_DATA(LCDD6_MARK, PSD5_0, PTC6_FN),
858 PINMUX_DATA(LCDD5_MARK, PSD5_0, PTC5_FN),
859 PINMUX_DATA(LCDD4_MARK, PSD5_0, PTC4_FN),
860 PINMUX_DATA(LCDD3_MARK, PSD5_0, PTC3_FN),
861 PINMUX_DATA(LCDD2_MARK, PSD5_0, PTC2_FN),
862 PINMUX_DATA(LCDD1_MARK, PSD5_0, PTC1_FN),
863 PINMUX_DATA(LCDD0_MARK, PSD5_0, PTC0_FN),
864
865 /* PTD FN */
866 PINMUX_DATA(LCDD15_MARK, PSD5_0, PTD7_FN),
867 PINMUX_DATA(LCDD14_MARK, PSD5_0, PTD6_FN),
868 PINMUX_DATA(LCDD13_MARK, PSD5_0, PTD5_FN),
869 PINMUX_DATA(LCDD12_MARK, PSD5_0, PTD4_FN),
870 PINMUX_DATA(LCDD11_MARK, PSD5_0, PTD3_FN),
871 PINMUX_DATA(LCDD10_MARK, PSD5_0, PTD2_FN),
872 PINMUX_DATA(LCDD9_MARK, PSD5_0, PTD1_FN),
873 PINMUX_DATA(LCDD8_MARK, PSD5_0, PTD0_FN),
874
875 /* PTE FN */
876 PINMUX_DATA(FSIMCKB_MARK, PTE7_FN),
877 PINMUX_DATA(FSIMCKA_MARK, PTE6_FN),
878
879 PINMUX_DATA(LCDD21_MARK, PSC5_0, PSC4_0, PTE5_FN),
880 PINMUX_DATA(LCDD20_MARK, PSD3_0, PSD2_0, PTE4_FN),
881 PINMUX_DATA(LCDD19_MARK, PSA3_0, PSA2_0, PTE3_FN),
882 PINMUX_DATA(LCDD18_MARK, PSA3_0, PSA2_0, PTE2_FN),
883 PINMUX_DATA(LCDD17_MARK, PSD5_0, PTE1_FN),
884 PINMUX_DATA(LCDD16_MARK, PSD5_0, PTE0_FN),
885
886 PINMUX_DATA(SCIF2_L_TXD_MARK, PSC5_0, PSC4_1, PTE5_FN),
887 PINMUX_DATA(SCIF4_SCK_MARK, PSD3_0, PSD2_1, PTE4_FN),
888 PINMUX_DATA(SCIF4_RXD_MARK, PSA3_0, PSA2_1, PTE3_FN),
889 PINMUX_DATA(SCIF4_TXD_MARK, PSA3_0, PSA2_1, PTE2_FN),
890
891 /* PTF FN */
892 PINMUX_DATA(LCDVSYN_MARK, PSD8_0, PTF7_FN),
893 PINMUX_DATA(LCDDISP_MARK, PSD10_0, PSD9_0, PTF6_FN),
894 PINMUX_DATA(LCDHSYN_MARK, PSD10_0, PSD9_0, PTF5_FN),
895 PINMUX_DATA(LCDDON_MARK, PSD8_0, PTF4_FN),
896 PINMUX_DATA(LCDDCK_MARK, PSD10_0, PSD9_0, PTF3_FN),
897 PINMUX_DATA(LCDVEPWC_MARK, PSA6_0, PTF2_FN),
898 PINMUX_DATA(LCDD23_MARK, PSC7_0, PSC6_0, PTF1_FN),
899 PINMUX_DATA(LCDD22_MARK, PSC5_0, PSC4_0, PTF0_FN),
900
901 PINMUX_DATA(LCDRS_MARK, PSD10_0, PSD9_1, PTF6_FN),
902 PINMUX_DATA(LCDCS_MARK, PSD10_0, PSD9_1, PTF5_FN),
903 PINMUX_DATA(LCDWR_MARK, PSD10_0, PSD9_1, PTF3_FN),
904
905 PINMUX_DATA(SCIF0_TXD_MARK, PSA6_1, PTF2_FN),
906 PINMUX_DATA(SCIF2_L_SCK_MARK, PSC7_0, PSC6_1, PTF1_FN),
907 PINMUX_DATA(SCIF2_L_RXD_MARK, PSC5_0, PSC4_1, PTF0_FN),
908
909 /* PTG FN */
910 PINMUX_DATA(AUDCK_MARK, PTG5_FN),
911 PINMUX_DATA(AUDSYNC_MARK, PTG4_FN),
912 PINMUX_DATA(AUDATA3_MARK, PTG3_FN),
913 PINMUX_DATA(AUDATA2_MARK, PTG2_FN),
914 PINMUX_DATA(AUDATA1_MARK, PTG1_FN),
915 PINMUX_DATA(AUDATA0_MARK, PTG0_FN),
916
917 /* PTH FN */
918 PINMUX_DATA(VIO0_VD_MARK, PTH7_FN),
919 PINMUX_DATA(VIO0_CLK_MARK, PTH6_FN),
920 PINMUX_DATA(VIO0_D7_MARK, PTH5_FN),
921 PINMUX_DATA(VIO0_D6_MARK, PTH4_FN),
922 PINMUX_DATA(VIO0_D5_MARK, PTH3_FN),
923 PINMUX_DATA(VIO0_D4_MARK, PTH2_FN),
924 PINMUX_DATA(VIO0_D3_MARK, PTH1_FN),
925 PINMUX_DATA(VIO0_D2_MARK, PTH0_FN),
926
927 /* PTJ FN */
928 PINMUX_DATA(PDSTATUS_MARK, PTJ7_FN),
929 PINMUX_DATA(STATUS2_MARK, PTJ6_FN),
930 PINMUX_DATA(STATUS0_MARK, PTJ5_FN),
931 PINMUX_DATA(A25_MARK, PSA8_0, PTJ3_FN),
932 PINMUX_DATA(BS_MARK, PSA8_1, PTJ3_FN),
933 PINMUX_DATA(A24_MARK, PTJ2_FN),
934 PINMUX_DATA(A23_MARK, PTJ1_FN),
935 PINMUX_DATA(A22_MARK, PTJ0_FN),
936
937 /* PTK FN */
938 PINMUX_DATA(VIO1_D5_MARK, PSB7_0, PSB6_0, PTK7_FN),
939 PINMUX_DATA(VIO1_D4_MARK, PSB7_0, PSB6_0, PTK6_FN),
940 PINMUX_DATA(VIO1_D3_MARK, PSB7_0, PSB6_0, PTK5_FN),
941 PINMUX_DATA(VIO1_D2_MARK, PSB7_0, PSB6_0, PTK4_FN),
942 PINMUX_DATA(VIO1_D1_MARK, PSB7_0, PSB6_0, PTK3_FN),
943 PINMUX_DATA(VIO1_D0_MARK, PSB7_0, PSB6_0, PTK2_FN),
944
945 PINMUX_DATA(VIO0_D13_MARK, PSB7_0, PSB6_1, PTK7_FN),
946 PINMUX_DATA(VIO0_D12_MARK, PSB7_0, PSB6_1, PTK6_FN),
947 PINMUX_DATA(VIO0_D11_MARK, PSB7_0, PSB6_1, PTK5_FN),
948 PINMUX_DATA(VIO0_D10_MARK, PSB7_0, PSB6_1, PTK4_FN),
949 PINMUX_DATA(VIO0_D9_MARK, PSB7_0, PSB6_1, PTK3_FN),
950 PINMUX_DATA(VIO0_D8_MARK, PSB7_0, PSB6_1, PTK2_FN),
951
952 PINMUX_DATA(IDED5_MARK, PSB7_1, PSB6_0, PTK7_FN),
953 PINMUX_DATA(IDED4_MARK, PSB7_1, PSB6_0, PTK6_FN),
954 PINMUX_DATA(IDED3_MARK, PSB7_1, PSB6_0, PTK5_FN),
955 PINMUX_DATA(IDED2_MARK, PSB7_1, PSB6_0, PTK4_FN),
956 PINMUX_DATA(IDED1_MARK, PSB7_1, PSB6_0, PTK3_FN),
957 PINMUX_DATA(IDED0_MARK, PSB7_1, PSB6_0, PTK2_FN),
958
959 PINMUX_DATA(VIO0_FLD_MARK, PTK1_FN),
960 PINMUX_DATA(VIO0_HD_MARK, PTK0_FN),
961
962 /* PTL FN */
963 PINMUX_DATA(DV_D5_MARK, PSB9_0, PSB8_0, PTL7_FN),
964 PINMUX_DATA(DV_D4_MARK, PSB9_0, PSB8_0, PTL6_FN),
965 PINMUX_DATA(DV_D3_MARK, PSE7_0, PSE6_0, PTL5_FN),
966 PINMUX_DATA(DV_D2_MARK, PSC9_0, PSC8_0, PTL4_FN),
967 PINMUX_DATA(DV_D1_MARK, PSC9_0, PSC8_0, PTL3_FN),
968 PINMUX_DATA(DV_D0_MARK, PSC9_0, PSC8_0, PTL2_FN),
969 PINMUX_DATA(DV_D15_MARK, PSD4_0, PTL1_FN),
970 PINMUX_DATA(DV_D14_MARK, PSE5_0, PSE4_0, PTL0_FN),
971
972 PINMUX_DATA(SCIF3_V_SCK_MARK, PSB9_0, PSB8_1, PTL7_FN),
973 PINMUX_DATA(SCIF3_V_RXD_MARK, PSB9_0, PSB8_1, PTL6_FN),
974 PINMUX_DATA(SCIF3_V_TXD_MARK, PSE7_0, PSE6_1, PTL5_FN),
975 PINMUX_DATA(SCIF1_SCK_MARK, PSC9_0, PSC8_1, PTL4_FN),
976 PINMUX_DATA(SCIF1_RXD_MARK, PSC9_0, PSC8_1, PTL3_FN),
977 PINMUX_DATA(SCIF1_TXD_MARK, PSC9_0, PSC8_1, PTL2_FN),
978
979 PINMUX_DATA(RMII_RXD0_MARK, PSB9_1, PSB8_0, PTL7_FN),
980 PINMUX_DATA(RMII_RXD1_MARK, PSB9_1, PSB8_0, PTL6_FN),
981 PINMUX_DATA(RMII_REF_CLK_MARK, PSE7_1, PSE6_0, PTL5_FN),
982 PINMUX_DATA(RMII_TX_EN_MARK, PSC9_1, PSC8_0, PTL4_FN),
983 PINMUX_DATA(RMII_TXD0_MARK, PSC9_1, PSC8_0, PTL3_FN),
984 PINMUX_DATA(RMII_TXD1_MARK, PSC9_1, PSC8_0, PTL2_FN),
985
986 PINMUX_DATA(MSIOF0_MCK_MARK, PSE5_0, PSE4_1, PTL0_FN),
987
988 /* PTM FN */
989 PINMUX_DATA(DV_D13_MARK, PSC13_0, PSC12_0, PTM7_FN),
990 PINMUX_DATA(DV_D12_MARK, PSC13_0, PSC12_0, PTM6_FN),
991 PINMUX_DATA(DV_D11_MARK, PSC13_0, PSC12_0, PTM5_FN),
992 PINMUX_DATA(DV_D10_MARK, PSC13_0, PSC12_0, PTM4_FN),
993 PINMUX_DATA(DV_D9_MARK, PSC11_0, PSC10_0, PTM3_FN),
994 PINMUX_DATA(DV_D8_MARK, PSC11_0, PSC10_0, PTM2_FN),
995
996 PINMUX_DATA(MSIOF0_TSCK_MARK, PSC13_0, PSC12_1, PTM7_FN),
997 PINMUX_DATA(MSIOF0_RXD_MARK, PSC13_0, PSC12_1, PTM6_FN),
998 PINMUX_DATA(MSIOF0_TXD_MARK, PSC13_0, PSC12_1, PTM5_FN),
999 PINMUX_DATA(MSIOF0_TSYNC_MARK, PSC13_0, PSC12_1, PTM4_FN),
1000 PINMUX_DATA(MSIOF0_SS1_MARK, PSC11_0, PSC10_1, PTM3_FN),
1001 PINMUX_DATA(MSIOF0_RSCK_MARK, PSC11_1, PSC10_0, PTM3_FN),
1002 PINMUX_DATA(MSIOF0_SS2_MARK, PSC11_0, PSC10_1, PTM2_FN),
1003 PINMUX_DATA(MSIOF0_RSYNC_MARK, PSC11_1, PSC10_0, PTM2_FN),
1004
1005 PINMUX_DATA(LCDVCPWC_MARK, PSA6_0, PTM1_FN),
1006 PINMUX_DATA(LCDRD_MARK, PSA7_0, PTM0_FN),
1007
1008 PINMUX_DATA(SCIF0_RXD_MARK, PSA6_1, PTM1_FN),
1009 PINMUX_DATA(SCIF0_SCK_MARK, PSA7_1, PTM0_FN),
1010
1011 /* PTN FN */
1012 PINMUX_DATA(VIO0_D1_MARK, PTN7_FN),
1013 PINMUX_DATA(VIO0_D0_MARK, PTN6_FN),
1014
1015 PINMUX_DATA(DV_CLKI_MARK, PSD11_0, PTN5_FN),
1016 PINMUX_DATA(DV_CLK_MARK, PSD13_0, PSD12_0, PTN4_FN),
1017 PINMUX_DATA(DV_VSYNC_MARK, PSD15_0, PSD14_0, PTN3_FN),
1018 PINMUX_DATA(DV_HSYNC_MARK, PSB5_0, PSB4_0, PTN2_FN),
1019 PINMUX_DATA(DV_D7_MARK, PSB3_0, PSB2_0, PTN1_FN),
1020 PINMUX_DATA(DV_D6_MARK, PSB1_0, PSB0_0, PTN0_FN),
1021
1022 PINMUX_DATA(SCIF2_V_SCK_MARK, PSD13_0, PSD12_1, PTN4_FN),
1023 PINMUX_DATA(SCIF2_V_RXD_MARK, PSD15_0, PSD14_1, PTN3_FN),
1024 PINMUX_DATA(SCIF2_V_TXD_MARK, PSB5_0, PSB4_1, PTN2_FN),
1025 PINMUX_DATA(SCIF3_V_CTS_MARK, PSB3_0, PSB2_1, PTN1_FN),
1026 PINMUX_DATA(SCIF3_V_RTS_MARK, PSB1_0, PSB0_1, PTN0_FN),
1027
1028 PINMUX_DATA(RMII_RX_ER_MARK, PSB3_1, PSB2_0, PTN1_FN),
1029 PINMUX_DATA(RMII_CRS_DV_MARK, PSB1_1, PSB0_0, PTN0_FN),
1030
1031 /* PTQ FN */
1032 PINMUX_DATA(D7_MARK, PTQ7_FN),
1033 PINMUX_DATA(D6_MARK, PTQ6_FN),
1034 PINMUX_DATA(D5_MARK, PTQ5_FN),
1035 PINMUX_DATA(D4_MARK, PTQ4_FN),
1036 PINMUX_DATA(D3_MARK, PTQ3_FN),
1037 PINMUX_DATA(D2_MARK, PTQ2_FN),
1038 PINMUX_DATA(D1_MARK, PTQ1_FN),
1039 PINMUX_DATA(D0_MARK, PTQ0_FN),
1040
1041 /* PTR FN */
1042 PINMUX_DATA(CS6B_CE1B_MARK, PTR7_FN),
1043 PINMUX_DATA(CS6A_CE2B_MARK, PTR6_FN),
1044 PINMUX_DATA(CS5B_CE1A_MARK, PTR5_FN),
1045 PINMUX_DATA(CS5A_CE2A_MARK, PTR4_FN),
1046 PINMUX_DATA(IOIS16_MARK, PSA5_0, PTR3_FN),
1047 PINMUX_DATA(WAIT_MARK, PTR2_FN),
1048 PINMUX_DATA(WE3_ICIOWR_MARK, PSA1_0, PSA0_0, PTR1_FN),
1049 PINMUX_DATA(WE2_ICIORD_MARK, PSD1_0, PSD0_0, PTR0_FN),
1050
1051 PINMUX_DATA(LCDLCLK_MARK, PSA5_1, PTR3_FN),
1052
1053 PINMUX_DATA(IDEA2_MARK, PSD1_1, PSD0_0, PTR0_FN),
1054
1055 PINMUX_DATA(TPUTO3_MARK, PSA1_0, PSA0_1, PTR1_FN),
1056 PINMUX_DATA(TPUTI3_MARK, PSA1_1, PSA0_0, PTR1_FN),
1057 PINMUX_DATA(TPUTO2_MARK, PSD1_0, PSD0_1, PTR0_FN),
1058
1059 /* PTS FN */
1060 PINMUX_DATA(VIO_CKO_MARK, PTS6_FN),
1061
1062 PINMUX_DATA(TPUTI2_MARK, PSE9_0, PSE8_1, PTS5_FN),
1063
1064 PINMUX_DATA(IDEIORDY_MARK, PSE9_1, PSE8_0, PTS5_FN),
1065
1066 PINMUX_DATA(VIO1_FLD_MARK, PSE9_0, PSE8_0, PTS5_FN),
1067 PINMUX_DATA(VIO1_HD_MARK, PSA10_0, PTS4_FN),
1068 PINMUX_DATA(VIO1_VD_MARK, PSA9_0, PTS3_FN),
1069 PINMUX_DATA(VIO1_CLK_MARK, PSA9_0, PTS2_FN),
1070 PINMUX_DATA(VIO1_D7_MARK, PSB7_0, PSB6_0, PTS1_FN),
1071 PINMUX_DATA(VIO1_D6_MARK, PSB7_0, PSB6_0, PTS0_FN),
1072
1073 PINMUX_DATA(SCIF5_SCK_MARK, PSA10_1, PTS4_FN),
1074 PINMUX_DATA(SCIF5_RXD_MARK, PSA9_1, PTS3_FN),
1075 PINMUX_DATA(SCIF5_TXD_MARK, PSA9_1, PTS2_FN),
1076
1077 PINMUX_DATA(VIO0_D15_MARK, PSB7_0, PSB6_1, PTS1_FN),
1078 PINMUX_DATA(VIO0_D14_MARK, PSB7_0, PSB6_1, PTS0_FN),
1079
1080 PINMUX_DATA(IDED7_MARK, PSB7_1, PSB6_0, PTS1_FN),
1081 PINMUX_DATA(IDED6_MARK, PSB7_1, PSB6_0, PTS0_FN),
1082
1083 /* PTT FN */
1084 PINMUX_DATA(D15_MARK, PTT7_FN),
1085 PINMUX_DATA(D14_MARK, PTT6_FN),
1086 PINMUX_DATA(D13_MARK, PTT5_FN),
1087 PINMUX_DATA(D12_MARK, PTT4_FN),
1088 PINMUX_DATA(D11_MARK, PTT3_FN),
1089 PINMUX_DATA(D10_MARK, PTT2_FN),
1090 PINMUX_DATA(D9_MARK, PTT1_FN),
1091 PINMUX_DATA(D8_MARK, PTT0_FN),
1092
1093 /* PTU FN */
1094 PINMUX_DATA(DMAC_DACK0_MARK, PTU7_FN),
1095 PINMUX_DATA(DMAC_DREQ0_MARK, PTU6_FN),
1096
1097 PINMUX_DATA(FSIOASD_MARK, PSE1_0, PTU5_FN),
1098 PINMUX_DATA(FSIIABCK_MARK, PSE1_0, PTU4_FN),
1099 PINMUX_DATA(FSIIALRCK_MARK, PSE1_0, PTU3_FN),
1100 PINMUX_DATA(FSIOABCK_MARK, PSE1_0, PTU2_FN),
1101 PINMUX_DATA(FSIOALRCK_MARK, PSE1_0, PTU1_FN),
1102 PINMUX_DATA(CLKAUDIOAO_MARK, PSE0_0, PTU0_FN),
1103
1104 /* PTV FN */
1105 PINMUX_DATA(FSIIBSD_MARK, PSD7_0, PSD6_0, PTV7_FN),
1106 PINMUX_DATA(FSIOBSD_MARK, PSD7_0, PSD6_0, PTV6_FN),
1107 PINMUX_DATA(FSIIBBCK_MARK, PSC15_0, PSC14_0, PTV5_FN),
1108 PINMUX_DATA(FSIIBLRCK_MARK, PSC15_0, PSC14_0, PTV4_FN),
1109 PINMUX_DATA(FSIOBBCK_MARK, PSC15_0, PSC14_0, PTV3_FN),
1110 PINMUX_DATA(FSIOBLRCK_MARK, PSC15_0, PSC14_0, PTV2_FN),
1111 PINMUX_DATA(CLKAUDIOBO_MARK, PSE3_0, PSE2_0, PTV1_FN),
1112 PINMUX_DATA(FSIIASD_MARK, PSE10_0, PTV0_FN),
1113
1114 PINMUX_DATA(MSIOF1_SS2_MARK, PSD7_0, PSD6_1, PTV7_FN),
1115 PINMUX_DATA(MSIOF1_RSYNC_MARK, PSD7_1, PSD6_0, PTV7_FN),
1116 PINMUX_DATA(MSIOF1_SS1_MARK, PSD7_0, PSD6_1, PTV6_FN),
1117 PINMUX_DATA(MSIOF1_RSCK_MARK, PSD7_1, PSD6_0, PTV6_FN),
1118 PINMUX_DATA(MSIOF1_RXD_MARK, PSC15_0, PSC14_1, PTV5_FN),
1119 PINMUX_DATA(MSIOF1_TSYNC_MARK, PSC15_0, PSC14_1, PTV4_FN),
1120 PINMUX_DATA(MSIOF1_TSCK_MARK, PSC15_0, PSC14_1, PTV3_FN),
1121 PINMUX_DATA(MSIOF1_TXD_MARK, PSC15_0, PSC14_1, PTV2_FN),
1122 PINMUX_DATA(MSIOF1_MCK_MARK, PSE3_0, PSE2_1, PTV1_FN),
1123
1124 /* PTW FN */
1125 PINMUX_DATA(MMC_D7_MARK, PSE13_0, PSE12_0, PTW7_FN),
1126 PINMUX_DATA(MMC_D6_MARK, PSE13_0, PSE12_0, PTW6_FN),
1127 PINMUX_DATA(MMC_D5_MARK, PSE13_0, PSE12_0, PTW5_FN),
1128 PINMUX_DATA(MMC_D4_MARK, PSE13_0, PSE12_0, PTW4_FN),
1129 PINMUX_DATA(MMC_D3_MARK, PSA13_0, PTW3_FN),
1130 PINMUX_DATA(MMC_D2_MARK, PSA13_0, PTW2_FN),
1131 PINMUX_DATA(MMC_D1_MARK, PSA13_0, PTW1_FN),
1132 PINMUX_DATA(MMC_D0_MARK, PSA13_0, PTW0_FN),
1133
1134 PINMUX_DATA(SDHI1CD_MARK, PSE13_0, PSE12_1, PTW7_FN),
1135 PINMUX_DATA(SDHI1WP_MARK, PSE13_0, PSE12_1, PTW6_FN),
1136 PINMUX_DATA(SDHI1D3_MARK, PSE13_0, PSE12_1, PTW5_FN),
1137 PINMUX_DATA(SDHI1D2_MARK, PSE13_0, PSE12_1, PTW4_FN),
1138 PINMUX_DATA(SDHI1D1_MARK, PSA13_1, PTW3_FN),
1139 PINMUX_DATA(SDHI1D0_MARK, PSA13_1, PTW2_FN),
1140 PINMUX_DATA(SDHI1CMD_MARK, PSA13_1, PTW1_FN),
1141 PINMUX_DATA(SDHI1CLK_MARK, PSA13_1, PTW0_FN),
1142
1143 PINMUX_DATA(IODACK_MARK, PSE13_1, PSE12_0, PTW7_FN),
1144 PINMUX_DATA(IDERST_MARK, PSE13_1, PSE12_0, PTW6_FN),
1145 PINMUX_DATA(EXBUF_ENB_MARK, PSE13_1, PSE12_0, PTW5_FN),
1146 PINMUX_DATA(DIRECTION_MARK, PSE13_1, PSE12_0, PTW4_FN),
1147
1148 /* PTX FN */
1149 PINMUX_DATA(DMAC_DACK1_MARK, PSA12_0, PTX7_FN),
1150 PINMUX_DATA(DMAC_DREQ1_MARK, PSA12_0, PTX6_FN),
1151
1152 PINMUX_DATA(IRDA_OUT_MARK, PSA12_1, PTX7_FN),
1153 PINMUX_DATA(IRDA_IN_MARK, PSA12_1, PTX6_FN),
1154
1155 PINMUX_DATA(TSIF_TS0_SDAT_MARK, PSC0_0, PTX5_FN),
1156 PINMUX_DATA(TSIF_TS0_SCK_MARK, PSC1_0, PTX4_FN),
1157 PINMUX_DATA(TSIF_TS0_SDEN_MARK, PSC2_0, PTX3_FN),
1158 PINMUX_DATA(TSIF_TS0_SPSYNC_MARK, PTX2_FN),
1159
1160 PINMUX_DATA(LNKSTA_MARK, PSC0_1, PTX5_FN),
1161 PINMUX_DATA(MDIO_MARK, PSC1_1, PTX4_FN),
1162 PINMUX_DATA(MDC_MARK, PSC2_1, PTX3_FN),
1163
1164 PINMUX_DATA(MMC_CLK_MARK, PTX1_FN),
1165 PINMUX_DATA(MMC_CMD_MARK, PTX0_FN),
1166
1167 /* PTY FN */
1168 PINMUX_DATA(SDHI0CD_MARK, PTY7_FN),
1169 PINMUX_DATA(SDHI0WP_MARK, PTY6_FN),
1170 PINMUX_DATA(SDHI0D3_MARK, PTY5_FN),
1171 PINMUX_DATA(SDHI0D2_MARK, PTY4_FN),
1172 PINMUX_DATA(SDHI0D1_MARK, PTY3_FN),
1173 PINMUX_DATA(SDHI0D0_MARK, PTY2_FN),
1174 PINMUX_DATA(SDHI0CMD_MARK, PTY1_FN),
1175 PINMUX_DATA(SDHI0CLK_MARK, PTY0_FN),
1176
1177 /* PTZ FN */
1178 PINMUX_DATA(INTC_IRQ7_MARK, PSB10_0, PTZ7_FN),
1179 PINMUX_DATA(INTC_IRQ6_MARK, PSB11_0, PTZ6_FN),
1180 PINMUX_DATA(INTC_IRQ5_MARK, PSB12_0, PTZ5_FN),
1181 PINMUX_DATA(INTC_IRQ4_MARK, PSB13_0, PTZ4_FN),
1182 PINMUX_DATA(INTC_IRQ3_MARK, PSB14_0, PTZ3_FN),
1183 PINMUX_DATA(INTC_IRQ2_MARK, PTZ2_FN),
1184 PINMUX_DATA(INTC_IRQ1_MARK, PTZ1_FN),
1185 PINMUX_DATA(INTC_IRQ0_MARK, PTZ0_FN),
1186
1187 PINMUX_DATA(SCIF3_I_CTS_MARK, PSB10_1, PTZ7_FN),
1188 PINMUX_DATA(SCIF3_I_RTS_MARK, PSB11_1, PTZ6_FN),
1189 PINMUX_DATA(SCIF3_I_SCK_MARK, PSB12_1, PTZ5_FN),
1190 PINMUX_DATA(SCIF3_I_RXD_MARK, PSB13_1, PTZ4_FN),
1191 PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN),
1192};
1193
1194static struct pinmux_gpio pinmux_gpios[] = {
1195 /* PTA */
1196 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
1197 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
1198 PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
1199 PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
1200 PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
1201 PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
1202 PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
1203 PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
1204
1205 /* PTB */
1206 PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
1207 PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
1208 PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
1209 PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
1210 PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
1211 PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
1212 PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
1213 PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
1214
1215 /* PTC */
1216 PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
1217 PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
1218 PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
1219 PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
1220 PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
1221 PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
1222 PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
1223 PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
1224
1225 /* PTD */
1226 PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
1227 PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
1228 PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
1229 PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
1230 PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
1231 PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
1232 PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
1233 PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
1234
1235 /* PTE */
1236 PINMUX_GPIO(GPIO_PTE7, PTE7_DATA),
1237 PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
1238 PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
1239 PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
1240 PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
1241 PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
1242 PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
1243 PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
1244
1245 /* PTF */
1246 PINMUX_GPIO(GPIO_PTF7, PTF7_DATA),
1247 PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
1248 PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
1249 PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
1250 PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
1251 PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
1252 PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
1253 PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
1254
1255 /* PTG */
1256 PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
1257 PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
1258 PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
1259 PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
1260 PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
1261 PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
1262
1263 /* PTH */
1264 PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
1265 PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
1266 PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
1267 PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
1268 PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
1269 PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
1270 PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
1271 PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
1272
1273 /* PTJ */
1274 PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
1275 PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
1276 PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
1277 PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
1278 PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
1279 PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
1280 PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
1281
1282 /* PTK */
1283 PINMUX_GPIO(GPIO_PTK7, PTK7_DATA),
1284 PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
1285 PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
1286 PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
1287 PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
1288 PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
1289 PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
1290 PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
1291
1292 /* PTL */
1293 PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
1294 PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
1295 PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
1296 PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
1297 PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
1298 PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
1299 PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
1300 PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
1301
1302 /* PTM */
1303 PINMUX_GPIO(GPIO_PTM7, PTM7_DATA),
1304 PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
1305 PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
1306 PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
1307 PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
1308 PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
1309 PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
1310 PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
1311
1312 /* PTN */
1313 PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
1314 PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
1315 PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
1316 PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
1317 PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
1318 PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
1319 PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
1320 PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
1321
1322 /* PTQ */
1323 PINMUX_GPIO(GPIO_PTQ7, PTQ7_DATA),
1324 PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA),
1325 PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA),
1326 PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA),
1327 PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
1328 PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
1329 PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
1330 PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
1331
1332 /* PTR */
1333 PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
1334 PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
1335 PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
1336 PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
1337 PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
1338 PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
1339 PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
1340 PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
1341
1342 /* PTS */
1343 PINMUX_GPIO(GPIO_PTS6, PTS6_DATA),
1344 PINMUX_GPIO(GPIO_PTS5, PTS5_DATA),
1345 PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
1346 PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
1347 PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
1348 PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
1349 PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
1350
1351 /* PTT */
1352 PINMUX_GPIO(GPIO_PTT7, PTT7_DATA),
1353 PINMUX_GPIO(GPIO_PTT6, PTT6_DATA),
1354 PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
1355 PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
1356 PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
1357 PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
1358 PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
1359 PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
1360
1361 /* PTU */
1362 PINMUX_GPIO(GPIO_PTU7, PTU7_DATA),
1363 PINMUX_GPIO(GPIO_PTU6, PTU6_DATA),
1364 PINMUX_GPIO(GPIO_PTU5, PTU5_DATA),
1365 PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
1366 PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
1367 PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
1368 PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
1369 PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
1370
1371 /* PTV */
1372 PINMUX_GPIO(GPIO_PTV7, PTV7_DATA),
1373 PINMUX_GPIO(GPIO_PTV6, PTV6_DATA),
1374 PINMUX_GPIO(GPIO_PTV5, PTV5_DATA),
1375 PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
1376 PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
1377 PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
1378 PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
1379 PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
1380
1381 /* PTW */
1382 PINMUX_GPIO(GPIO_PTW7, PTW7_DATA),
1383 PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
1384 PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
1385 PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
1386 PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
1387 PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
1388 PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
1389 PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
1390
1391 /* PTX */
1392 PINMUX_GPIO(GPIO_PTX7, PTX7_DATA),
1393 PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
1394 PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
1395 PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
1396 PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
1397 PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
1398 PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
1399 PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
1400
1401 /* PTY */
1402 PINMUX_GPIO(GPIO_PTY7, PTY7_DATA),
1403 PINMUX_GPIO(GPIO_PTY6, PTY6_DATA),
1404 PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
1405 PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
1406 PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
1407 PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
1408 PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
1409 PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
1410
1411 /* PTZ */
1412 PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA),
1413 PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA),
1414 PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
1415 PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
1416 PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
1417 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
1418 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
1419 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
1420
1421 /* BSC */
1422 PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
1423 PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
1424 PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
1425 PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
1426 PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
1427 PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
1428 PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
1429 PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
1430 PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
1431 PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
1432 PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
1433 PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
1434 PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
1435 PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
1436 PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
1437 PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
1438 PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
1439 PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
1440 PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
1441 PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
1442 PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
1443 PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
1444 PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
1445 PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
1446 PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
1447 PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
1448 PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
1449 PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
1450 PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
1451 PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
1452 PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
1453 PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
1454 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
1455 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
1456 PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
1457 PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
1458 PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK),
1459 PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK),
1460 PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK),
1461 PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK),
1462 PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK),
1463 PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK),
1464 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
1465 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
1466 PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
1467
1468 /* KEYSC */
1469 PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK),
1470 PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK),
1471 PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK),
1472 PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK),
1473 PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK),
1474 PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK),
1475 PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK),
1476 PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK),
1477 PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK),
1478 PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK),
1479 PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK),
1480
1481 /* ATAPI */
1482 PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK),
1483 PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK),
1484 PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK),
1485 PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK),
1486 PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK),
1487 PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK),
1488 PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK),
1489 PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK),
1490 PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK),
1491 PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK),
1492 PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK),
1493 PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK),
1494 PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK),
1495 PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK),
1496 PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK),
1497 PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK),
1498 PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK),
1499 PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK),
1500 PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK),
1501 PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK),
1502 PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK),
1503 PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK),
1504 PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK),
1505 PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK),
1506 PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK),
1507 PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK),
1508 PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK),
1509 PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK),
1510 PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK),
1511 PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK),
1512
1513 /* TPU */
1514 PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK),
1515 PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK),
1516 PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK),
1517 PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK),
1518 PINMUX_GPIO(GPIO_FN_TPUTI3, TPUTI3_MARK),
1519 PINMUX_GPIO(GPIO_FN_TPUTI2, TPUTI2_MARK),
1520
1521 /* LCDC */
1522 PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK),
1523 PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK),
1524 PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK),
1525 PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK),
1526 PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK),
1527 PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK),
1528 PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK),
1529 PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK),
1530 PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK),
1531 PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK),
1532 PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK),
1533 PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK),
1534 PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK),
1535 PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK),
1536 PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK),
1537 PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK),
1538 PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK),
1539 PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK),
1540 PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK),
1541 PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK),
1542 PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK),
1543 PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK),
1544 PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK),
1545 PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK),
1546 PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK),
1547 PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK),
1548 PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK),
1549 PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK),
1550 PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK),
1551 PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK),
1552 PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK),
1553 PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK),
1554 PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK),
1555 PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK),
1556 PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK),
1557 PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK),
1558
1559 /* SCIF0 */
1560 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK),
1561 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK),
1562 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK),
1563
1564 /* SCIF1 */
1565 PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK),
1566 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK),
1567 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK),
1568
1569 /* SCIF2 */
1570 PINMUX_GPIO(GPIO_FN_SCIF2_L_TXD, SCIF2_L_TXD_MARK),
1571 PINMUX_GPIO(GPIO_FN_SCIF2_L_SCK, SCIF2_L_SCK_MARK),
1572 PINMUX_GPIO(GPIO_FN_SCIF2_L_RXD, SCIF2_L_RXD_MARK),
1573 PINMUX_GPIO(GPIO_FN_SCIF2_V_TXD, SCIF2_V_TXD_MARK),
1574 PINMUX_GPIO(GPIO_FN_SCIF2_V_SCK, SCIF2_V_SCK_MARK),
1575 PINMUX_GPIO(GPIO_FN_SCIF2_V_RXD, SCIF2_V_RXD_MARK),
1576
1577 /* SCIF3 */
1578 PINMUX_GPIO(GPIO_FN_SCIF3_V_SCK, SCIF3_V_SCK_MARK),
1579 PINMUX_GPIO(GPIO_FN_SCIF3_V_RXD, SCIF3_V_RXD_MARK),
1580 PINMUX_GPIO(GPIO_FN_SCIF3_V_TXD, SCIF3_V_TXD_MARK),
1581 PINMUX_GPIO(GPIO_FN_SCIF3_V_CTS, SCIF3_V_CTS_MARK),
1582 PINMUX_GPIO(GPIO_FN_SCIF3_V_RTS, SCIF3_V_RTS_MARK),
1583 PINMUX_GPIO(GPIO_FN_SCIF3_I_SCK, SCIF3_I_SCK_MARK),
1584 PINMUX_GPIO(GPIO_FN_SCIF3_I_RXD, SCIF3_I_RXD_MARK),
1585 PINMUX_GPIO(GPIO_FN_SCIF3_I_TXD, SCIF3_I_TXD_MARK),
1586 PINMUX_GPIO(GPIO_FN_SCIF3_I_CTS, SCIF3_I_CTS_MARK),
1587 PINMUX_GPIO(GPIO_FN_SCIF3_I_RTS, SCIF3_I_RTS_MARK),
1588
1589 /* SCIF4 */
1590 PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK),
1591 PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK),
1592 PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK),
1593
1594 /* SCIF5 */
1595 PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK),
1596 PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK),
1597 PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK),
1598
1599 /* FSI */
1600 PINMUX_GPIO(GPIO_FN_FSIMCKB, FSIMCKB_MARK),
1601 PINMUX_GPIO(GPIO_FN_FSIMCKA, FSIMCKA_MARK),
1602 PINMUX_GPIO(GPIO_FN_FSIOASD, FSIOASD_MARK),
1603 PINMUX_GPIO(GPIO_FN_FSIIABCK, FSIIABCK_MARK),
1604 PINMUX_GPIO(GPIO_FN_FSIIALRCK, FSIIALRCK_MARK),
1605 PINMUX_GPIO(GPIO_FN_FSIOABCK, FSIOABCK_MARK),
1606 PINMUX_GPIO(GPIO_FN_FSIOALRCK, FSIOALRCK_MARK),
1607 PINMUX_GPIO(GPIO_FN_CLKAUDIOAO, CLKAUDIOAO_MARK),
1608 PINMUX_GPIO(GPIO_FN_FSIIBSD, FSIIBSD_MARK),
1609 PINMUX_GPIO(GPIO_FN_FSIOBSD, FSIOBSD_MARK),
1610 PINMUX_GPIO(GPIO_FN_FSIIBBCK, FSIIBBCK_MARK),
1611 PINMUX_GPIO(GPIO_FN_FSIIBLRCK, FSIIBLRCK_MARK),
1612 PINMUX_GPIO(GPIO_FN_FSIOBBCK, FSIOBBCK_MARK),
1613 PINMUX_GPIO(GPIO_FN_FSIOBLRCK, FSIOBLRCK_MARK),
1614 PINMUX_GPIO(GPIO_FN_CLKAUDIOBO, CLKAUDIOBO_MARK),
1615 PINMUX_GPIO(GPIO_FN_FSIIASD, FSIIASD_MARK),
1616
1617 /* AUD */
1618 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
1619 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
1620 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
1621 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
1622 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
1623 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
1624
1625 /* VIO */
1626 PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK),
1627
1628 /* VIO0 */
1629 PINMUX_GPIO(GPIO_FN_VIO0_D15, VIO0_D15_MARK),
1630 PINMUX_GPIO(GPIO_FN_VIO0_D14, VIO0_D14_MARK),
1631 PINMUX_GPIO(GPIO_FN_VIO0_D13, VIO0_D13_MARK),
1632 PINMUX_GPIO(GPIO_FN_VIO0_D12, VIO0_D12_MARK),
1633 PINMUX_GPIO(GPIO_FN_VIO0_D11, VIO0_D11_MARK),
1634 PINMUX_GPIO(GPIO_FN_VIO0_D10, VIO0_D10_MARK),
1635 PINMUX_GPIO(GPIO_FN_VIO0_D9, VIO0_D9_MARK),
1636 PINMUX_GPIO(GPIO_FN_VIO0_D8, VIO0_D8_MARK),
1637 PINMUX_GPIO(GPIO_FN_VIO0_D7, VIO0_D7_MARK),
1638 PINMUX_GPIO(GPIO_FN_VIO0_D6, VIO0_D6_MARK),
1639 PINMUX_GPIO(GPIO_FN_VIO0_D5, VIO0_D5_MARK),
1640 PINMUX_GPIO(GPIO_FN_VIO0_D4, VIO0_D4_MARK),
1641 PINMUX_GPIO(GPIO_FN_VIO0_D3, VIO0_D3_MARK),
1642 PINMUX_GPIO(GPIO_FN_VIO0_D2, VIO0_D2_MARK),
1643 PINMUX_GPIO(GPIO_FN_VIO0_D1, VIO0_D1_MARK),
1644 PINMUX_GPIO(GPIO_FN_VIO0_D0, VIO0_D0_MARK),
1645 PINMUX_GPIO(GPIO_FN_VIO0_VD, VIO0_VD_MARK),
1646 PINMUX_GPIO(GPIO_FN_VIO0_CLK, VIO0_CLK_MARK),
1647 PINMUX_GPIO(GPIO_FN_VIO0_FLD, VIO0_FLD_MARK),
1648 PINMUX_GPIO(GPIO_FN_VIO0_HD, VIO0_HD_MARK),
1649
1650 /* VIO1 */
1651 PINMUX_GPIO(GPIO_FN_VIO1_D7, VIO1_D7_MARK),
1652 PINMUX_GPIO(GPIO_FN_VIO1_D6, VIO1_D6_MARK),
1653 PINMUX_GPIO(GPIO_FN_VIO1_D5, VIO1_D5_MARK),
1654 PINMUX_GPIO(GPIO_FN_VIO1_D4, VIO1_D4_MARK),
1655 PINMUX_GPIO(GPIO_FN_VIO1_D3, VIO1_D3_MARK),
1656 PINMUX_GPIO(GPIO_FN_VIO1_D2, VIO1_D2_MARK),
1657 PINMUX_GPIO(GPIO_FN_VIO1_D1, VIO1_D1_MARK),
1658 PINMUX_GPIO(GPIO_FN_VIO1_D0, VIO1_D0_MARK),
1659 PINMUX_GPIO(GPIO_FN_VIO1_FLD, VIO1_FLD_MARK),
1660 PINMUX_GPIO(GPIO_FN_VIO1_HD, VIO1_HD_MARK),
1661 PINMUX_GPIO(GPIO_FN_VIO1_VD, VIO1_VD_MARK),
1662 PINMUX_GPIO(GPIO_FN_VIO1_CLK, VIO1_CLK_MARK),
1663
1664 /* Eth */
1665 PINMUX_GPIO(GPIO_FN_RMII_RXD0, RMII_RXD0_MARK),
1666 PINMUX_GPIO(GPIO_FN_RMII_RXD1, RMII_RXD1_MARK),
1667 PINMUX_GPIO(GPIO_FN_RMII_TXD0, RMII_TXD0_MARK),
1668 PINMUX_GPIO(GPIO_FN_RMII_TXD1, RMII_TXD1_MARK),
1669 PINMUX_GPIO(GPIO_FN_RMII_REF_CLK, RMII_REF_CLK_MARK),
1670 PINMUX_GPIO(GPIO_FN_RMII_TX_EN, RMII_TX_EN_MARK),
1671 PINMUX_GPIO(GPIO_FN_RMII_RX_ER, RMII_RX_ER_MARK),
1672 PINMUX_GPIO(GPIO_FN_RMII_CRS_DV, RMII_CRS_DV_MARK),
1673 PINMUX_GPIO(GPIO_FN_LNKSTA, LNKSTA_MARK),
1674 PINMUX_GPIO(GPIO_FN_MDIO, MDIO_MARK),
1675 PINMUX_GPIO(GPIO_FN_MDC, MDC_MARK),
1676
1677 /* System */
1678 PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK),
1679 PINMUX_GPIO(GPIO_FN_STATUS2, STATUS2_MARK),
1680 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
1681
1682 /* VOU */
1683 PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK),
1684 PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK),
1685 PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK),
1686 PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK),
1687 PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK),
1688 PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK),
1689 PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK),
1690 PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK),
1691 PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK),
1692 PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK),
1693 PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK),
1694 PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK),
1695 PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK),
1696 PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK),
1697 PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK),
1698 PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK),
1699 PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK),
1700 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
1701 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
1702 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
1703
1704 /* MSIOF0 */
1705 PINMUX_GPIO(GPIO_FN_MSIOF0_RXD, MSIOF0_RXD_MARK),
1706 PINMUX_GPIO(GPIO_FN_MSIOF0_TXD, MSIOF0_TXD_MARK),
1707 PINMUX_GPIO(GPIO_FN_MSIOF0_MCK, MSIOF0_MCK_MARK),
1708 PINMUX_GPIO(GPIO_FN_MSIOF0_TSCK, MSIOF0_TSCK_MARK),
1709 PINMUX_GPIO(GPIO_FN_MSIOF0_SS1, MSIOF0_SS1_MARK),
1710 PINMUX_GPIO(GPIO_FN_MSIOF0_SS2, MSIOF0_SS2_MARK),
1711 PINMUX_GPIO(GPIO_FN_MSIOF0_TSYNC, MSIOF0_TSYNC_MARK),
1712 PINMUX_GPIO(GPIO_FN_MSIOF0_RSCK, MSIOF0_RSCK_MARK),
1713 PINMUX_GPIO(GPIO_FN_MSIOF0_RSYNC, MSIOF0_RSYNC_MARK),
1714
1715 /* MSIOF1 */
1716 PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK),
1717 PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK),
1718 PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK),
1719 PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK),
1720 PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK),
1721 PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK),
1722 PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK),
1723 PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK),
1724 PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK),
1725
1726 /* DMAC */
1727 PINMUX_GPIO(GPIO_FN_DMAC_DACK0, DMAC_DACK0_MARK),
1728 PINMUX_GPIO(GPIO_FN_DMAC_DREQ0, DMAC_DREQ0_MARK),
1729 PINMUX_GPIO(GPIO_FN_DMAC_DACK1, DMAC_DACK1_MARK),
1730 PINMUX_GPIO(GPIO_FN_DMAC_DREQ1, DMAC_DREQ1_MARK),
1731
1732 /* SDHI0 */
1733 PINMUX_GPIO(GPIO_FN_SDHI0CD, SDHI0CD_MARK),
1734 PINMUX_GPIO(GPIO_FN_SDHI0WP, SDHI0WP_MARK),
1735 PINMUX_GPIO(GPIO_FN_SDHI0CMD, SDHI0CMD_MARK),
1736 PINMUX_GPIO(GPIO_FN_SDHI0CLK, SDHI0CLK_MARK),
1737 PINMUX_GPIO(GPIO_FN_SDHI0D3, SDHI0D3_MARK),
1738 PINMUX_GPIO(GPIO_FN_SDHI0D2, SDHI0D2_MARK),
1739 PINMUX_GPIO(GPIO_FN_SDHI0D1, SDHI0D1_MARK),
1740 PINMUX_GPIO(GPIO_FN_SDHI0D0, SDHI0D0_MARK),
1741
1742 /* SDHI1 */
1743 PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK),
1744 PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK),
1745 PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK),
1746 PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK),
1747 PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK),
1748 PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK),
1749 PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK),
1750 PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK),
1751
1752 /* MMC */
1753 PINMUX_GPIO(GPIO_FN_MMC_D7, MMC_D7_MARK),
1754 PINMUX_GPIO(GPIO_FN_MMC_D6, MMC_D6_MARK),
1755 PINMUX_GPIO(GPIO_FN_MMC_D5, MMC_D5_MARK),
1756 PINMUX_GPIO(GPIO_FN_MMC_D4, MMC_D4_MARK),
1757 PINMUX_GPIO(GPIO_FN_MMC_D3, MMC_D3_MARK),
1758 PINMUX_GPIO(GPIO_FN_MMC_D2, MMC_D2_MARK),
1759 PINMUX_GPIO(GPIO_FN_MMC_D1, MMC_D1_MARK),
1760 PINMUX_GPIO(GPIO_FN_MMC_D0, MMC_D0_MARK),
1761 PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK),
1762 PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK),
1763
1764 /* IrDA */
1765 PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK),
1766 PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK),
1767
1768 /* TSIF */
1769 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDAT, TSIF_TS0_SDAT_MARK),
1770 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SCK, TSIF_TS0_SCK_MARK),
1771 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDEN, TSIF_TS0_SDEN_MARK),
1772 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SPSYNC, TSIF_TS0_SPSYNC_MARK),
1773
1774 /* IRQ */
1775 PINMUX_GPIO(GPIO_FN_INTC_IRQ7, INTC_IRQ7_MARK),
1776 PINMUX_GPIO(GPIO_FN_INTC_IRQ6, INTC_IRQ6_MARK),
1777 PINMUX_GPIO(GPIO_FN_INTC_IRQ5, INTC_IRQ5_MARK),
1778 PINMUX_GPIO(GPIO_FN_INTC_IRQ4, INTC_IRQ4_MARK),
1779 PINMUX_GPIO(GPIO_FN_INTC_IRQ3, INTC_IRQ3_MARK),
1780 PINMUX_GPIO(GPIO_FN_INTC_IRQ2, INTC_IRQ2_MARK),
1781 PINMUX_GPIO(GPIO_FN_INTC_IRQ1, INTC_IRQ1_MARK),
1782 PINMUX_GPIO(GPIO_FN_INTC_IRQ0, INTC_IRQ0_MARK),
1783 };
1784
1785static struct pinmux_cfg_reg pinmux_config_regs[] = {
1786 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
1787 PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
1788 PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
1789 PTA5_FN, PTA5_OUT, PTA5_IN_PU, PTA5_IN,
1790 PTA4_FN, PTA4_OUT, PTA4_IN_PU, PTA4_IN,
1791 PTA3_FN, PTA3_OUT, PTA3_IN_PU, PTA3_IN,
1792 PTA2_FN, PTA2_OUT, PTA2_IN_PU, PTA2_IN,
1793 PTA1_FN, PTA1_OUT, PTA1_IN_PU, PTA1_IN,
1794 PTA0_FN, PTA0_OUT, PTA0_IN_PU, PTA0_IN }
1795 },
1796 { PINMUX_CFG_REG("PBCR", 0xa4050102, 16, 2) {
1797 PTB7_FN, PTB7_OUT, PTB7_IN_PU, PTB7_IN,
1798 PTB6_FN, PTB6_OUT, PTB6_IN_PU, PTB6_IN,
1799 PTB5_FN, PTB5_OUT, PTB5_IN_PU, PTB5_IN,
1800 PTB4_FN, PTB4_OUT, PTB4_IN_PU, PTB4_IN,
1801 PTB3_FN, PTB3_OUT, PTB3_IN_PU, PTB3_IN,
1802 PTB2_FN, PTB2_OUT, PTB2_IN_PU, PTB2_IN,
1803 PTB1_FN, PTB1_OUT, PTB1_IN_PU, PTB1_IN,
1804 PTB0_FN, PTB0_OUT, PTB0_IN_PU, PTB0_IN }
1805 },
1806 { PINMUX_CFG_REG("PCCR", 0xa4050104, 16, 2) {
1807 PTC7_FN, PTC7_OUT, PTC7_IN_PU, PTC7_IN,
1808 PTC6_FN, PTC6_OUT, PTC6_IN_PU, PTC6_IN,
1809 PTC5_FN, PTC5_OUT, PTC5_IN_PU, PTC5_IN,
1810 PTC4_FN, PTC4_OUT, PTC4_IN_PU, PTC4_IN,
1811 PTC3_FN, PTC3_OUT, PTC3_IN_PU, PTC3_IN,
1812 PTC2_FN, PTC2_OUT, PTC2_IN_PU, PTC2_IN,
1813 PTC1_FN, PTC1_OUT, PTC1_IN_PU, PTC1_IN,
1814 PTC0_FN, PTC0_OUT, PTC0_IN_PU, PTC0_IN }
1815 },
1816 { PINMUX_CFG_REG("PDCR", 0xa4050106, 16, 2) {
1817 PTD7_FN, PTD7_OUT, PTD7_IN_PU, PTD7_IN,
1818 PTD6_FN, PTD6_OUT, PTD6_IN_PU, PTD6_IN,
1819 PTD5_FN, PTD5_OUT, PTD5_IN_PU, PTD5_IN,
1820 PTD4_FN, PTD4_OUT, PTD4_IN_PU, PTD4_IN,
1821 PTD3_FN, PTD3_OUT, PTD3_IN_PU, PTD3_IN,
1822 PTD2_FN, PTD2_OUT, PTD2_IN_PU, PTD2_IN,
1823 PTD1_FN, PTD1_OUT, PTD1_IN_PU, PTD1_IN,
1824 PTD0_FN, PTD0_OUT, PTD0_IN_PU, PTD0_IN }
1825 },
1826 { PINMUX_CFG_REG("PECR", 0xa4050108, 16, 2) {
1827 PTE7_FN, PTE7_OUT, PTE7_IN_PU, PTE7_IN,
1828 PTE6_FN, PTE6_OUT, PTE6_IN_PU, PTE6_IN,
1829 PTE5_FN, PTE5_OUT, PTE5_IN_PU, PTE5_IN,
1830 PTE4_FN, PTE4_OUT, PTE4_IN_PU, PTE4_IN,
1831 PTE3_FN, PTE3_OUT, PTE3_IN_PU, PTE3_IN,
1832 PTE2_FN, PTE2_OUT, PTE2_IN_PU, PTE2_IN,
1833 PTE1_FN, PTE1_OUT, PTE1_IN_PU, PTE1_IN,
1834 PTE0_FN, PTE0_OUT, PTE0_IN_PU, PTE0_IN }
1835 },
1836 { PINMUX_CFG_REG("PFCR", 0xa405010a, 16, 2) {
1837 PTF7_FN, PTF7_OUT, PTF7_IN_PU, PTF7_IN,
1838 PTF6_FN, PTF6_OUT, PTF6_IN_PU, PTF6_IN,
1839 PTF5_FN, PTF5_OUT, PTF5_IN_PU, PTF5_IN,
1840 PTF4_FN, PTF4_OUT, PTF4_IN_PU, PTF4_IN,
1841 PTF3_FN, PTF3_OUT, PTF3_IN_PU, PTF3_IN,
1842 PTF2_FN, PTF2_OUT, PTF2_IN_PU, PTF2_IN,
1843 PTF1_FN, PTF1_OUT, PTF1_IN_PU, PTF1_IN,
1844 PTF0_FN, PTF0_OUT, PTF0_IN_PU, PTF0_IN }
1845 },
1846 { PINMUX_CFG_REG("PGCR", 0xa405010c, 16, 2) {
1847 0, 0, 0, 0,
1848 0, 0, 0, 0,
1849 PTG5_FN, PTG5_OUT, 0, 0,
1850 PTG4_FN, PTG4_OUT, 0, 0,
1851 PTG3_FN, PTG3_OUT, 0, 0,
1852 PTG2_FN, PTG2_OUT, 0, 0,
1853 PTG1_FN, PTG1_OUT, 0, 0,
1854 PTG0_FN, PTG0_OUT, 0, 0 }
1855 },
1856 { PINMUX_CFG_REG("PHCR", 0xa405010e, 16, 2) {
1857 PTH7_FN, PTH7_OUT, PTH7_IN_PU, PTH7_IN,
1858 PTH6_FN, PTH6_OUT, PTH6_IN_PU, PTH6_IN,
1859 PTH5_FN, PTH5_OUT, PTH5_IN_PU, PTH5_IN,
1860 PTH4_FN, PTH4_OUT, PTH4_IN_PU, PTH4_IN,
1861 PTH3_FN, PTH3_OUT, PTH3_IN_PU, PTH3_IN,
1862 PTH2_FN, PTH2_OUT, PTH2_IN_PU, PTH2_IN,
1863 PTH1_FN, PTH1_OUT, PTH1_IN_PU, PTH1_IN,
1864 PTH0_FN, PTH0_OUT, PTH0_IN_PU, PTH0_IN }
1865 },
1866 { PINMUX_CFG_REG("PJCR", 0xa4050110, 16, 2) {
1867 PTJ7_FN, PTJ7_OUT, 0, 0,
1868 PTJ6_FN, PTJ6_OUT, 0, 0,
1869 PTJ5_FN, PTJ5_OUT, 0, 0,
1870 0, 0, 0, 0,
1871 PTJ3_FN, PTJ3_OUT, PTJ3_IN_PU, PTJ3_IN,
1872 PTJ2_FN, PTJ2_OUT, PTJ2_IN_PU, PTJ2_IN,
1873 PTJ1_FN, PTJ1_OUT, PTJ1_IN_PU, PTJ1_IN,
1874 PTJ0_FN, PTJ0_OUT, PTJ0_IN_PU, PTJ0_IN }
1875 },
1876 { PINMUX_CFG_REG("PKCR", 0xa4050112, 16, 2) {
1877 PTK7_FN, PTK7_OUT, PTK7_IN_PU, PTK7_IN,
1878 PTK6_FN, PTK6_OUT, PTK6_IN_PU, PTK6_IN,
1879 PTK5_FN, PTK5_OUT, PTK5_IN_PU, PTK5_IN,
1880 PTK4_FN, PTK4_OUT, PTK4_IN_PU, PTK4_IN,
1881 PTK3_FN, PTK3_OUT, PTK3_IN_PU, PTK3_IN,
1882 PTK2_FN, PTK2_OUT, PTK2_IN_PU, PTK2_IN,
1883 PTK1_FN, PTK1_OUT, PTK1_IN_PU, PTK1_IN,
1884 PTK0_FN, PTK0_OUT, PTK0_IN_PU, PTK0_IN }
1885 },
1886 { PINMUX_CFG_REG("PLCR", 0xa4050114, 16, 2) {
1887 PTL7_FN, PTL7_OUT, PTL7_IN_PU, PTL7_IN,
1888 PTL6_FN, PTL6_OUT, PTL6_IN_PU, PTL6_IN,
1889 PTL5_FN, PTL5_OUT, PTL5_IN_PU, PTL5_IN,
1890 PTL4_FN, PTL4_OUT, PTL4_IN_PU, PTL4_IN,
1891 PTL3_FN, PTL3_OUT, PTL3_IN_PU, PTL3_IN,
1892 PTL2_FN, PTL2_OUT, PTL2_IN_PU, PTL2_IN,
1893 PTL1_FN, PTL1_OUT, PTL1_IN_PU, PTL1_IN,
1894 PTL0_FN, PTL0_OUT, PTL0_IN_PU, PTL0_IN }
1895 },
1896 { PINMUX_CFG_REG("PMCR", 0xa4050116, 16, 2) {
1897 PTM7_FN, PTM7_OUT, PTM7_IN_PU, PTM7_IN,
1898 PTM6_FN, PTM6_OUT, PTM6_IN_PU, PTM6_IN,
1899 PTM5_FN, PTM5_OUT, PTM5_IN_PU, PTM5_IN,
1900 PTM4_FN, PTM4_OUT, PTM4_IN_PU, PTM4_IN,
1901 PTM3_FN, PTM3_OUT, PTM3_IN_PU, PTM3_IN,
1902 PTM2_FN, PTM2_OUT, PTM2_IN_PU, PTM2_IN,
1903 PTM1_FN, PTM1_OUT, PTM1_IN_PU, PTM1_IN,
1904 PTM0_FN, PTM0_OUT, PTM0_IN_PU, PTM0_IN }
1905 },
1906 { PINMUX_CFG_REG("PNCR", 0xa4050118, 16, 2) {
1907 PTN7_FN, PTN7_OUT, PTN7_IN_PU, PTN7_IN,
1908 PTN6_FN, PTN6_OUT, PTN6_IN_PU, PTN6_IN,
1909 PTN5_FN, PTN5_OUT, PTN5_IN_PU, PTN5_IN,
1910 PTN4_FN, PTN4_OUT, PTN4_IN_PU, PTN4_IN,
1911 PTN3_FN, PTN3_OUT, PTN3_IN_PU, PTN3_IN,
1912 PTN2_FN, PTN2_OUT, PTN2_IN_PU, PTN2_IN,
1913 PTN1_FN, PTN1_OUT, PTN1_IN_PU, PTN1_IN,
1914 PTN0_FN, PTN0_OUT, PTN0_IN_PU, PTN0_IN }
1915 },
1916 { PINMUX_CFG_REG("PQCR", 0xa405011a, 16, 2) {
1917 PTQ7_FN, PTQ7_OUT, PTQ7_IN_PU, PTQ7_IN,
1918 PTQ6_FN, PTQ6_OUT, PTQ6_IN_PU, PTQ6_IN,
1919 PTQ5_FN, PTQ5_OUT, PTQ5_IN_PU, PTQ5_IN,
1920 PTQ4_FN, PTQ4_OUT, PTQ4_IN_PU, PTQ4_IN,
1921 PTQ3_FN, PTQ3_OUT, PTQ3_IN_PU, PTQ3_IN,
1922 PTQ2_FN, PTQ2_OUT, PTQ2_IN_PU, PTQ2_IN,
1923 PTQ1_FN, PTQ1_OUT, PTQ1_IN_PU, PTQ1_IN,
1924 PTQ0_FN, PTQ0_OUT, PTQ0_IN_PU, PTQ0_IN }
1925 },
1926 { PINMUX_CFG_REG("PRCR", 0xa405011c, 16, 2) {
1927 PTR7_FN, PTR7_OUT, PTR7_IN_PU, PTR7_IN,
1928 PTR6_FN, PTR6_OUT, PTR6_IN_PU, PTR6_IN,
1929 PTR5_FN, PTR5_OUT, PTR5_IN_PU, PTR5_IN,
1930 PTR4_FN, PTR4_OUT, PTR4_IN_PU, PTR4_IN,
1931 PTR3_FN, 0, PTR3_IN_PU, PTR3_IN,
1932 PTR2_FN, 0, PTR2_IN_PU, PTR2_IN,
1933 PTR1_FN, PTR1_OUT, PTR1_IN_PU, PTR1_IN,
1934 PTR0_FN, PTR0_OUT, PTR0_IN_PU, PTR0_IN }
1935 },
1936 { PINMUX_CFG_REG("PSCR", 0xa405011e, 16, 2) {
1937 0, 0, 0, 0,
1938 PTS6_FN, PTS6_OUT, PTS6_IN_PU, PTS6_IN,
1939 PTS5_FN, PTS5_OUT, PTS5_IN_PU, PTS5_IN,
1940 PTS4_FN, PTS4_OUT, PTS4_IN_PU, PTS4_IN,
1941 PTS3_FN, PTS3_OUT, PTS3_IN_PU, PTS3_IN,
1942 PTS2_FN, PTS2_OUT, PTS2_IN_PU, PTS2_IN,
1943 PTS1_FN, PTS1_OUT, PTS1_IN_PU, PTS1_IN,
1944 PTS0_FN, PTS0_OUT, PTS0_IN_PU, PTS0_IN }
1945 },
1946 { PINMUX_CFG_REG("PTCR", 0xa4050140, 16, 2) {
1947 PTT7_FN, PTT7_OUT, PTT7_IN_PU, PTT7_IN,
1948 PTT6_FN, PTT6_OUT, PTT6_IN_PU, PTT6_IN,
1949 PTT5_FN, PTT5_OUT, PTT5_IN_PU, PTT5_IN,
1950 PTT4_FN, PTT4_OUT, PTT4_IN_PU, PTT4_IN,
1951 PTT3_FN, PTT3_OUT, PTT3_IN_PU, PTT3_IN,
1952 PTT2_FN, PTT2_OUT, PTT2_IN_PU, PTT2_IN,
1953 PTT1_FN, PTT1_OUT, PTT1_IN_PU, PTT1_IN,
1954 PTT0_FN, PTT0_OUT, PTT0_IN_PU, PTT0_IN }
1955 },
1956 { PINMUX_CFG_REG("PUCR", 0xa4050142, 16, 2) {
1957 PTU7_FN, PTU7_OUT, PTU7_IN_PU, PTU7_IN,
1958 PTU6_FN, PTU6_OUT, PTU6_IN_PU, PTU6_IN,
1959 PTU5_FN, PTU5_OUT, PTU5_IN_PU, PTU5_IN,
1960 PTU4_FN, PTU4_OUT, PTU4_IN_PU, PTU4_IN,
1961 PTU3_FN, PTU3_OUT, PTU3_IN_PU, PTU3_IN,
1962 PTU2_FN, PTU2_OUT, PTU2_IN_PU, PTU2_IN,
1963 PTU1_FN, PTU1_OUT, PTU1_IN_PU, PTU1_IN,
1964 PTU0_FN, PTU0_OUT, PTU0_IN_PU, PTU0_IN }
1965 },
1966 { PINMUX_CFG_REG("PVCR", 0xa4050144, 16, 2) {
1967 PTV7_FN, PTV7_OUT, PTV7_IN_PU, PTV7_IN,
1968 PTV6_FN, PTV6_OUT, PTV6_IN_PU, PTV6_IN,
1969 PTV5_FN, PTV5_OUT, PTV5_IN_PU, PTV5_IN,
1970 PTV4_FN, PTV4_OUT, PTV4_IN_PU, PTV4_IN,
1971 PTV3_FN, PTV3_OUT, PTV3_IN_PU, PTV3_IN,
1972 PTV2_FN, PTV2_OUT, PTV2_IN_PU, PTV2_IN,
1973 PTV1_FN, PTV1_OUT, PTV1_IN_PU, PTV1_IN,
1974 PTV0_FN, PTV0_OUT, PTV0_IN_PU, PTV0_IN }
1975 },
1976 { PINMUX_CFG_REG("PWCR", 0xa4050146, 16, 2) {
1977 PTW7_FN, PTW7_OUT, PTW7_IN_PU, PTW7_IN,
1978 PTW6_FN, PTW6_OUT, PTW6_IN_PU, PTW6_IN,
1979 PTW5_FN, PTW5_OUT, PTW5_IN_PU, PTW5_IN,
1980 PTW4_FN, PTW4_OUT, PTW4_IN_PU, PTW4_IN,
1981 PTW3_FN, PTW3_OUT, PTW3_IN_PU, PTW3_IN,
1982 PTW2_FN, PTW2_OUT, PTW2_IN_PU, PTW2_IN,
1983 PTW1_FN, PTW1_OUT, PTW1_IN_PU, PTW1_IN,
1984 PTW0_FN, PTW0_OUT, PTW0_IN_PU, PTW0_IN }
1985 },
1986 { PINMUX_CFG_REG("PXCR", 0xa4050148, 16, 2) {
1987 PTX7_FN, PTX7_OUT, PTX7_IN_PU, PTX7_IN,
1988 PTX6_FN, PTX6_OUT, PTX6_IN_PU, PTX6_IN,
1989 PTX5_FN, PTX5_OUT, PTX5_IN_PU, PTX5_IN,
1990 PTX4_FN, PTX4_OUT, PTX4_IN_PU, PTX4_IN,
1991 PTX3_FN, PTX3_OUT, PTX3_IN_PU, PTX3_IN,
1992 PTX2_FN, PTX2_OUT, PTX2_IN_PU, PTX2_IN,
1993 PTX1_FN, PTX1_OUT, PTX1_IN_PU, PTX1_IN,
1994 PTX0_FN, PTX0_OUT, PTX0_IN_PU, PTX0_IN }
1995 },
1996 { PINMUX_CFG_REG("PYCR", 0xa405014a, 16, 2) {
1997 PTY7_FN, PTY7_OUT, PTY7_IN_PU, PTY7_IN,
1998 PTY6_FN, PTY6_OUT, PTY6_IN_PU, PTY6_IN,
1999 PTY5_FN, PTY5_OUT, PTY5_IN_PU, PTY5_IN,
2000 PTY4_FN, PTY4_OUT, PTY4_IN_PU, PTY4_IN,
2001 PTY3_FN, PTY3_OUT, PTY3_IN_PU, PTY3_IN,
2002 PTY2_FN, PTY2_OUT, PTY2_IN_PU, PTY2_IN,
2003 PTY1_FN, PTY1_OUT, PTY1_IN_PU, PTY1_IN,
2004 PTY0_FN, PTY0_OUT, PTY0_IN_PU, PTY0_IN }
2005 },
2006 { PINMUX_CFG_REG("PZCR", 0xa405014c, 16, 2) {
2007 PTZ7_FN, PTZ7_OUT, PTZ7_IN_PU, PTZ7_IN,
2008 PTZ6_FN, PTZ6_OUT, PTZ6_IN_PU, PTZ6_IN,
2009 PTZ5_FN, PTZ5_OUT, PTZ5_IN_PU, PTZ5_IN,
2010 PTZ4_FN, PTZ4_OUT, PTZ4_IN_PU, PTZ4_IN,
2011 PTZ3_FN, PTZ3_OUT, PTZ3_IN_PU, PTZ3_IN,
2012 PTZ2_FN, PTZ2_OUT, PTZ2_IN_PU, PTZ2_IN,
2013 PTZ1_FN, PTZ1_OUT, PTZ1_IN_PU, PTZ1_IN,
2014 PTZ0_FN, PTZ0_OUT, PTZ0_IN_PU, PTZ0_IN }
2015 },
2016 { PINMUX_CFG_REG("PSELA", 0xa405014e, 16, 1) {
2017 PSA15_0, PSA15_1,
2018 PSA14_0, PSA14_1,
2019 PSA13_0, PSA13_1,
2020 PSA12_0, PSA12_1,
2021 0, 0,
2022 PSA10_0, PSA10_1,
2023 PSA9_0, PSA9_1,
2024 PSA8_0, PSA8_1,
2025 PSA7_0, PSA7_1,
2026 PSA6_0, PSA6_1,
2027 PSA5_0, PSA5_1,
2028 0, 0,
2029 PSA3_0, PSA3_1,
2030 PSA2_0, PSA2_1,
2031 PSA1_0, PSA1_1,
2032 PSA0_0, PSA0_1}
2033 },
2034 { PINMUX_CFG_REG("PSELB", 0xa4050150, 16, 1) {
2035 0, 0,
2036 PSB14_0, PSB14_1,
2037 PSB13_0, PSB13_1,
2038 PSB12_0, PSB12_1,
2039 PSB11_0, PSB11_1,
2040 PSB10_0, PSB10_1,
2041 PSB9_0, PSB9_1,
2042 PSB8_0, PSB8_1,
2043 PSB7_0, PSB7_1,
2044 PSB6_0, PSB6_1,
2045 PSB5_0, PSB5_1,
2046 PSB4_0, PSB4_1,
2047 PSB3_0, PSB3_1,
2048 PSB2_0, PSB2_1,
2049 PSB1_0, PSB1_1,
2050 PSB0_0, PSB0_1}
2051 },
2052 { PINMUX_CFG_REG("PSELC", 0xa4050152, 16, 1) {
2053 PSC15_0, PSC15_1,
2054 PSC14_0, PSC14_1,
2055 PSC13_0, PSC13_1,
2056 PSC12_0, PSC12_1,
2057 PSC11_0, PSC11_1,
2058 PSC10_0, PSC10_1,
2059 PSC9_0, PSC9_1,
2060 PSC8_0, PSC8_1,
2061 PSC7_0, PSC7_1,
2062 PSC6_0, PSC6_1,
2063 PSC5_0, PSC5_1,
2064 PSC4_0, PSC4_1,
2065 0, 0,
2066 PSC2_0, PSC2_1,
2067 PSC1_0, PSC1_1,
2068 PSC0_0, PSC0_1}
2069 },
2070 { PINMUX_CFG_REG("PSELD", 0xa4050154, 16, 1) {
2071 PSD15_0, PSD15_1,
2072 PSD14_0, PSD14_1,
2073 PSD13_0, PSD13_1,
2074 PSD12_0, PSD12_1,
2075 PSD11_0, PSD11_1,
2076 PSD10_0, PSD10_1,
2077 PSD9_0, PSD9_1,
2078 PSD8_0, PSD8_1,
2079 PSD7_0, PSD7_1,
2080 PSD6_0, PSD6_1,
2081 PSD5_0, PSD5_1,
2082 PSD4_0, PSD4_1,
2083 PSD3_0, PSD3_1,
2084 PSD2_0, PSD2_1,
2085 PSD1_0, PSD1_1,
2086 PSD0_0, PSD0_1}
2087 },
2088 { PINMUX_CFG_REG("PSELE", 0xa4050156, 16, 1) {
2089 PSE15_0, PSE15_1,
2090 PSE14_0, PSE14_1,
2091 PSE13_0, PSE13_1,
2092 PSE12_0, PSE12_1,
2093 PSE11_0, PSE11_1,
2094 PSE10_0, PSE10_1,
2095 PSE9_0, PSE9_1,
2096 PSE8_0, PSE8_1,
2097 PSE7_0, PSE7_1,
2098 PSE6_0, PSE6_1,
2099 PSE5_0, PSE5_1,
2100 PSE4_0, PSE4_1,
2101 PSE3_0, PSE3_1,
2102 PSE2_0, PSE2_1,
2103 PSE1_0, PSE1_1,
2104 PSE0_0, PSE0_1}
2105 },
2106 {}
2107};
2108
2109static struct pinmux_data_reg pinmux_data_regs[] = {
2110 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
2111 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
2112 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
2113 },
2114 { PINMUX_DATA_REG("PBDR", 0xa4050122, 8) {
2115 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
2116 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
2117 },
2118 { PINMUX_DATA_REG("PCDR", 0xa4050124, 8) {
2119 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
2120 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
2121 },
2122 { PINMUX_DATA_REG("PDDR", 0xa4050126, 8) {
2123 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
2124 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
2125 },
2126 { PINMUX_DATA_REG("PEDR", 0xa4050128, 8) {
2127 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
2128 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
2129 },
2130 { PINMUX_DATA_REG("PFDR", 0xa405012a, 8) {
2131 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
2132 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
2133 },
2134 { PINMUX_DATA_REG("PGDR", 0xa405012c, 8) {
2135 0, 0, PTG5_DATA, PTG4_DATA,
2136 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
2137 },
2138 { PINMUX_DATA_REG("PHDR", 0xa405012e, 8) {
2139 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
2140 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
2141 },
2142 { PINMUX_DATA_REG("PJDR", 0xa4050130, 8) {
2143 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, 0,
2144 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
2145 },
2146 { PINMUX_DATA_REG("PKDR", 0xa4050132, 8) {
2147 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
2148 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
2149 },
2150 { PINMUX_DATA_REG("PLDR", 0xa4050134, 8) {
2151 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
2152 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
2153 },
2154 { PINMUX_DATA_REG("PMDR", 0xa4050136, 8) {
2155 PTM7_DATA, PTM6_DATA, PTM5_DATA, PTM4_DATA,
2156 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
2157 },
2158 { PINMUX_DATA_REG("PNDR", 0xa4050138, 8) {
2159 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
2160 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
2161 },
2162 { PINMUX_DATA_REG("PQDR", 0xa405013a, 8) {
2163 PTQ7_DATA, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
2164 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
2165 },
2166 { PINMUX_DATA_REG("PRDR", 0xa405013c, 8) {
2167 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
2168 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
2169 },
2170 { PINMUX_DATA_REG("PSDR", 0xa405013e, 8) {
2171 0, PTS6_DATA, PTS5_DATA, PTS4_DATA,
2172 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
2173 },
2174 { PINMUX_DATA_REG("PTDR", 0xa4050160, 8) {
2175 PTT7_DATA, PTT6_DATA, PTT5_DATA, PTT4_DATA,
2176 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
2177 },
2178 { PINMUX_DATA_REG("PUDR", 0xa4050162, 8) {
2179 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
2180 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
2181 },
2182 { PINMUX_DATA_REG("PVDR", 0xa4050164, 8) {
2183 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
2184 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
2185 },
2186 { PINMUX_DATA_REG("PWDR", 0xa4050166, 8) {
2187 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
2188 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
2189 },
2190 { PINMUX_DATA_REG("PXDR", 0xa4050168, 8) {
2191 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
2192 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
2193 },
2194 { PINMUX_DATA_REG("PYDR", 0xa405016a, 8) {
2195 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
2196 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
2197 },
2198 { PINMUX_DATA_REG("PZDR", 0xa405016c, 8) {
2199 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
2200 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
2201 },
2202 { },
2203};
2204
2205static struct pinmux_info sh7724_pinmux_info = {
2206 .name = "sh7724_pfc",
2207 .reserved_id = PINMUX_RESERVED,
2208 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2209 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2210 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
2211 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2212 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2213 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2214
2215 .first_gpio = GPIO_PTA7,
2216 .last_gpio = GPIO_FN_INTC_IRQ0,
2217
2218 .gpios = pinmux_gpios,
2219 .cfg_regs = pinmux_config_regs,
2220 .data_regs = pinmux_data_regs,
2221
2222 .gpio_data = pinmux_data,
2223 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2224};
2225
2226static int __init plat_pinmux_setup(void)
2227{
2228 return register_pinmux(&sh7724_pinmux_info);
2229}
2230arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
index c1549382c87c..6307e087c864 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7343.c
@@ -12,7 +12,7 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/uio_driver.h> 14#include <linux/uio_driver.h>
15#include <linux/sh_cmt.h> 15#include <linux/sh_timer.h>
16#include <asm/clock.h> 16#include <asm/clock.h>
17 17
18static struct resource iic0_resources[] = { 18static struct resource iic0_resources[] = {
@@ -141,7 +141,7 @@ static struct platform_device jpu_device = {
141 .num_resources = ARRAY_SIZE(jpu_resources), 141 .num_resources = ARRAY_SIZE(jpu_resources),
142}; 142};
143 143
144static struct sh_cmt_config cmt_platform_data = { 144static struct sh_timer_config cmt_platform_data = {
145 .name = "CMT", 145 .name = "CMT",
146 .channel_offset = 0x60, 146 .channel_offset = 0x60,
147 .timer_bit = 5, 147 .timer_bit = 5,
@@ -173,27 +173,123 @@ static struct platform_device cmt_device = {
173 .num_resources = ARRAY_SIZE(cmt_resources), 173 .num_resources = ARRAY_SIZE(cmt_resources),
174}; 174};
175 175
176static struct sh_timer_config tmu0_platform_data = {
177 .name = "TMU0",
178 .channel_offset = 0x04,
179 .timer_bit = 0,
180 .clk = "tmu0",
181 .clockevent_rating = 200,
182};
183
184static struct resource tmu0_resources[] = {
185 [0] = {
186 .name = "TMU0",
187 .start = 0xffd80008,
188 .end = 0xffd80013,
189 .flags = IORESOURCE_MEM,
190 },
191 [1] = {
192 .start = 16,
193 .flags = IORESOURCE_IRQ,
194 },
195};
196
197static struct platform_device tmu0_device = {
198 .name = "sh_tmu",
199 .id = 0,
200 .dev = {
201 .platform_data = &tmu0_platform_data,
202 },
203 .resource = tmu0_resources,
204 .num_resources = ARRAY_SIZE(tmu0_resources),
205};
206
207static struct sh_timer_config tmu1_platform_data = {
208 .name = "TMU1",
209 .channel_offset = 0x10,
210 .timer_bit = 1,
211 .clk = "tmu0",
212 .clocksource_rating = 200,
213};
214
215static struct resource tmu1_resources[] = {
216 [0] = {
217 .name = "TMU1",
218 .start = 0xffd80014,
219 .end = 0xffd8001f,
220 .flags = IORESOURCE_MEM,
221 },
222 [1] = {
223 .start = 17,
224 .flags = IORESOURCE_IRQ,
225 },
226};
227
228static struct platform_device tmu1_device = {
229 .name = "sh_tmu",
230 .id = 1,
231 .dev = {
232 .platform_data = &tmu1_platform_data,
233 },
234 .resource = tmu1_resources,
235 .num_resources = ARRAY_SIZE(tmu1_resources),
236};
237
238static struct sh_timer_config tmu2_platform_data = {
239 .name = "TMU2",
240 .channel_offset = 0x1c,
241 .timer_bit = 2,
242 .clk = "tmu0",
243};
244
245static struct resource tmu2_resources[] = {
246 [0] = {
247 .name = "TMU2",
248 .start = 0xffd80020,
249 .end = 0xffd8002b,
250 .flags = IORESOURCE_MEM,
251 },
252 [1] = {
253 .start = 18,
254 .flags = IORESOURCE_IRQ,
255 },
256};
257
258static struct platform_device tmu2_device = {
259 .name = "sh_tmu",
260 .id = 2,
261 .dev = {
262 .platform_data = &tmu2_platform_data,
263 },
264 .resource = tmu2_resources,
265 .num_resources = ARRAY_SIZE(tmu2_resources),
266};
267
176static struct plat_sci_port sci_platform_data[] = { 268static struct plat_sci_port sci_platform_data[] = {
177 { 269 {
178 .mapbase = 0xffe00000, 270 .mapbase = 0xffe00000,
179 .flags = UPF_BOOT_AUTOCONF, 271 .flags = UPF_BOOT_AUTOCONF,
180 .type = PORT_SCIF, 272 .type = PORT_SCIF,
181 .irqs = { 80, 80, 80, 80 }, 273 .irqs = { 80, 80, 80, 80 },
274 .clk = "scif0",
182 }, { 275 }, {
183 .mapbase = 0xffe10000, 276 .mapbase = 0xffe10000,
184 .flags = UPF_BOOT_AUTOCONF, 277 .flags = UPF_BOOT_AUTOCONF,
185 .type = PORT_SCIF, 278 .type = PORT_SCIF,
186 .irqs = { 81, 81, 81, 81 }, 279 .irqs = { 81, 81, 81, 81 },
280 .clk = "scif1",
187 }, { 281 }, {
188 .mapbase = 0xffe20000, 282 .mapbase = 0xffe20000,
189 .flags = UPF_BOOT_AUTOCONF, 283 .flags = UPF_BOOT_AUTOCONF,
190 .type = PORT_SCIF, 284 .type = PORT_SCIF,
191 .irqs = { 82, 82, 82, 82 }, 285 .irqs = { 82, 82, 82, 82 },
286 .clk = "scif2",
192 }, { 287 }, {
193 .mapbase = 0xffe30000, 288 .mapbase = 0xffe30000,
194 .flags = UPF_BOOT_AUTOCONF, 289 .flags = UPF_BOOT_AUTOCONF,
195 .type = PORT_SCIF, 290 .type = PORT_SCIF,
196 .irqs = { 83, 83, 83, 83 }, 291 .irqs = { 83, 83, 83, 83 },
292 .clk = "scif3",
197 }, { 293 }, {
198 .flags = 0, 294 .flags = 0,
199 } 295 }
@@ -209,6 +305,9 @@ static struct platform_device sci_device = {
209 305
210static struct platform_device *sh7343_devices[] __initdata = { 306static struct platform_device *sh7343_devices[] __initdata = {
211 &cmt_device, 307 &cmt_device,
308 &tmu0_device,
309 &tmu1_device,
310 &tmu2_device,
212 &iic0_device, 311 &iic0_device,
213 &iic1_device, 312 &iic1_device,
214 &sci_device, 313 &sci_device,
@@ -219,12 +318,6 @@ static struct platform_device *sh7343_devices[] __initdata = {
219 318
220static int __init sh7343_devices_setup(void) 319static int __init sh7343_devices_setup(void)
221{ 320{
222 clk_always_enable("uram0"); /* URAM */
223 clk_always_enable("xymem0"); /* XYMEM */
224 clk_always_enable("veu0"); /* VEU */
225 clk_always_enable("vpu0"); /* VPU */
226 clk_always_enable("jpu0"); /* JPU */
227
228 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 321 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
229 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 322 platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
230 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 323 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
@@ -234,6 +327,19 @@ static int __init sh7343_devices_setup(void)
234} 327}
235__initcall(sh7343_devices_setup); 328__initcall(sh7343_devices_setup);
236 329
330static struct platform_device *sh7343_early_devices[] __initdata = {
331 &cmt_device,
332 &tmu0_device,
333 &tmu1_device,
334 &tmu2_device,
335};
336
337void __init plat_early_device_setup(void)
338{
339 early_platform_add_devices(sh7343_early_devices,
340 ARRAY_SIZE(sh7343_early_devices));
341}
342
237enum { 343enum {
238 UNUSED = 0, 344 UNUSED = 0,
239 345
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 93ecf8ed5c6c..318516f6bfad 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -14,7 +14,7 @@
14#include <linux/serial.h> 14#include <linux/serial.h>
15#include <linux/serial_sci.h> 15#include <linux/serial_sci.h>
16#include <linux/uio_driver.h> 16#include <linux/uio_driver.h>
17#include <linux/sh_cmt.h> 17#include <linux/sh_timer.h>
18#include <asm/clock.h> 18#include <asm/clock.h>
19 19
20static struct resource iic_resources[] = { 20static struct resource iic_resources[] = {
@@ -148,7 +148,7 @@ static struct platform_device veu1_device = {
148 .num_resources = ARRAY_SIZE(veu1_resources), 148 .num_resources = ARRAY_SIZE(veu1_resources),
149}; 149};
150 150
151static struct sh_cmt_config cmt_platform_data = { 151static struct sh_timer_config cmt_platform_data = {
152 .name = "CMT", 152 .name = "CMT",
153 .channel_offset = 0x60, 153 .channel_offset = 0x60,
154 .timer_bit = 5, 154 .timer_bit = 5,
@@ -180,12 +180,105 @@ static struct platform_device cmt_device = {
180 .num_resources = ARRAY_SIZE(cmt_resources), 180 .num_resources = ARRAY_SIZE(cmt_resources),
181}; 181};
182 182
183static struct sh_timer_config tmu0_platform_data = {
184 .name = "TMU0",
185 .channel_offset = 0x04,
186 .timer_bit = 0,
187 .clk = "tmu0",
188 .clockevent_rating = 200,
189};
190
191static struct resource tmu0_resources[] = {
192 [0] = {
193 .name = "TMU0",
194 .start = 0xffd80008,
195 .end = 0xffd80013,
196 .flags = IORESOURCE_MEM,
197 },
198 [1] = {
199 .start = 16,
200 .flags = IORESOURCE_IRQ,
201 },
202};
203
204static struct platform_device tmu0_device = {
205 .name = "sh_tmu",
206 .id = 0,
207 .dev = {
208 .platform_data = &tmu0_platform_data,
209 },
210 .resource = tmu0_resources,
211 .num_resources = ARRAY_SIZE(tmu0_resources),
212};
213
214static struct sh_timer_config tmu1_platform_data = {
215 .name = "TMU1",
216 .channel_offset = 0x10,
217 .timer_bit = 1,
218 .clk = "tmu0",
219 .clocksource_rating = 200,
220};
221
222static struct resource tmu1_resources[] = {
223 [0] = {
224 .name = "TMU1",
225 .start = 0xffd80014,
226 .end = 0xffd8001f,
227 .flags = IORESOURCE_MEM,
228 },
229 [1] = {
230 .start = 17,
231 .flags = IORESOURCE_IRQ,
232 },
233};
234
235static struct platform_device tmu1_device = {
236 .name = "sh_tmu",
237 .id = 1,
238 .dev = {
239 .platform_data = &tmu1_platform_data,
240 },
241 .resource = tmu1_resources,
242 .num_resources = ARRAY_SIZE(tmu1_resources),
243};
244
245static struct sh_timer_config tmu2_platform_data = {
246 .name = "TMU2",
247 .channel_offset = 0x1c,
248 .timer_bit = 2,
249 .clk = "tmu0",
250};
251
252static struct resource tmu2_resources[] = {
253 [0] = {
254 .name = "TMU2",
255 .start = 0xffd80020,
256 .end = 0xffd8002b,
257 .flags = IORESOURCE_MEM,
258 },
259 [1] = {
260 .start = 18,
261 .flags = IORESOURCE_IRQ,
262 },
263};
264
265static struct platform_device tmu2_device = {
266 .name = "sh_tmu",
267 .id = 2,
268 .dev = {
269 .platform_data = &tmu2_platform_data,
270 },
271 .resource = tmu2_resources,
272 .num_resources = ARRAY_SIZE(tmu2_resources),
273};
274
183static struct plat_sci_port sci_platform_data[] = { 275static struct plat_sci_port sci_platform_data[] = {
184 { 276 {
185 .mapbase = 0xffe00000, 277 .mapbase = 0xffe00000,
186 .flags = UPF_BOOT_AUTOCONF, 278 .flags = UPF_BOOT_AUTOCONF,
187 .type = PORT_SCIF, 279 .type = PORT_SCIF,
188 .irqs = { 80, 80, 80, 80 }, 280 .irqs = { 80, 80, 80, 80 },
281 .clk = "scif0",
189 }, { 282 }, {
190 .flags = 0, 283 .flags = 0,
191 } 284 }
@@ -201,6 +294,9 @@ static struct platform_device sci_device = {
201 294
202static struct platform_device *sh7366_devices[] __initdata = { 295static struct platform_device *sh7366_devices[] __initdata = {
203 &cmt_device, 296 &cmt_device,
297 &tmu0_device,
298 &tmu1_device,
299 &tmu2_device,
204 &iic_device, 300 &iic_device,
205 &sci_device, 301 &sci_device,
206 &usb_host_device, 302 &usb_host_device,
@@ -211,12 +307,6 @@ static struct platform_device *sh7366_devices[] __initdata = {
211 307
212static int __init sh7366_devices_setup(void) 308static int __init sh7366_devices_setup(void)
213{ 309{
214 clk_always_enable("rsmem0"); /* RSMEM */
215 clk_always_enable("xymem0"); /* XYMEM */
216 clk_always_enable("veu1"); /* VEU-2 */
217 clk_always_enable("veu0"); /* VEU-1 */
218 clk_always_enable("vpu0"); /* VPU */
219
220 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 310 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
221 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 311 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
222 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 312 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
@@ -226,6 +316,19 @@ static int __init sh7366_devices_setup(void)
226} 316}
227__initcall(sh7366_devices_setup); 317__initcall(sh7366_devices_setup);
228 318
319static struct platform_device *sh7366_early_devices[] __initdata = {
320 &cmt_device,
321 &tmu0_device,
322 &tmu1_device,
323 &tmu2_device,
324};
325
326void __init plat_early_device_setup(void)
327{
328 early_platform_add_devices(sh7366_early_devices,
329 ARRAY_SIZE(sh7366_early_devices));
330}
331
229enum { 332enum {
230 UNUSED=0, 333 UNUSED=0,
231 334
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 406747f07dc0..ea524a2da3e4 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -13,7 +13,7 @@
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/mm.h> 14#include <linux/mm.h>
15#include <linux/uio_driver.h> 15#include <linux/uio_driver.h>
16#include <linux/sh_cmt.h> 16#include <linux/sh_timer.h>
17#include <asm/clock.h> 17#include <asm/clock.h>
18#include <asm/mmzone.h> 18#include <asm/mmzone.h>
19 19
@@ -177,13 +177,13 @@ static struct platform_device jpu_device = {
177 .num_resources = ARRAY_SIZE(jpu_resources), 177 .num_resources = ARRAY_SIZE(jpu_resources),
178}; 178};
179 179
180static struct sh_cmt_config cmt_platform_data = { 180static struct sh_timer_config cmt_platform_data = {
181 .name = "CMT", 181 .name = "CMT",
182 .channel_offset = 0x60, 182 .channel_offset = 0x60,
183 .timer_bit = 5, 183 .timer_bit = 5,
184 .clk = "cmt0", 184 .clk = "cmt0",
185 .clockevent_rating = 125, 185 .clockevent_rating = 125,
186 .clocksource_rating = 200, 186 .clocksource_rating = 125,
187}; 187};
188 188
189static struct resource cmt_resources[] = { 189static struct resource cmt_resources[] = {
@@ -209,24 +209,119 @@ static struct platform_device cmt_device = {
209 .num_resources = ARRAY_SIZE(cmt_resources), 209 .num_resources = ARRAY_SIZE(cmt_resources),
210}; 210};
211 211
212static struct sh_timer_config tmu0_platform_data = {
213 .name = "TMU0",
214 .channel_offset = 0x04,
215 .timer_bit = 0,
216 .clk = "tmu0",
217 .clockevent_rating = 200,
218};
219
220static struct resource tmu0_resources[] = {
221 [0] = {
222 .name = "TMU0",
223 .start = 0xffd80008,
224 .end = 0xffd80013,
225 .flags = IORESOURCE_MEM,
226 },
227 [1] = {
228 .start = 16,
229 .flags = IORESOURCE_IRQ,
230 },
231};
232
233static struct platform_device tmu0_device = {
234 .name = "sh_tmu",
235 .id = 0,
236 .dev = {
237 .platform_data = &tmu0_platform_data,
238 },
239 .resource = tmu0_resources,
240 .num_resources = ARRAY_SIZE(tmu0_resources),
241};
242
243static struct sh_timer_config tmu1_platform_data = {
244 .name = "TMU1",
245 .channel_offset = 0x10,
246 .timer_bit = 1,
247 .clk = "tmu0",
248 .clocksource_rating = 200,
249};
250
251static struct resource tmu1_resources[] = {
252 [0] = {
253 .name = "TMU1",
254 .start = 0xffd80014,
255 .end = 0xffd8001f,
256 .flags = IORESOURCE_MEM,
257 },
258 [1] = {
259 .start = 17,
260 .flags = IORESOURCE_IRQ,
261 },
262};
263
264static struct platform_device tmu1_device = {
265 .name = "sh_tmu",
266 .id = 1,
267 .dev = {
268 .platform_data = &tmu1_platform_data,
269 },
270 .resource = tmu1_resources,
271 .num_resources = ARRAY_SIZE(tmu1_resources),
272};
273
274static struct sh_timer_config tmu2_platform_data = {
275 .name = "TMU2",
276 .channel_offset = 0x1c,
277 .timer_bit = 2,
278 .clk = "tmu0",
279};
280
281static struct resource tmu2_resources[] = {
282 [0] = {
283 .name = "TMU2",
284 .start = 0xffd80020,
285 .end = 0xffd8002b,
286 .flags = IORESOURCE_MEM,
287 },
288 [1] = {
289 .start = 18,
290 .flags = IORESOURCE_IRQ,
291 },
292};
293
294static struct platform_device tmu2_device = {
295 .name = "sh_tmu",
296 .id = 2,
297 .dev = {
298 .platform_data = &tmu2_platform_data,
299 },
300 .resource = tmu2_resources,
301 .num_resources = ARRAY_SIZE(tmu2_resources),
302};
303
212static struct plat_sci_port sci_platform_data[] = { 304static struct plat_sci_port sci_platform_data[] = {
213 { 305 {
214 .mapbase = 0xffe00000, 306 .mapbase = 0xffe00000,
215 .flags = UPF_BOOT_AUTOCONF, 307 .flags = UPF_BOOT_AUTOCONF,
216 .type = PORT_SCIF, 308 .type = PORT_SCIF,
217 .irqs = { 80, 80, 80, 80 }, 309 .irqs = { 80, 80, 80, 80 },
310 .clk = "scif0",
218 }, 311 },
219 { 312 {
220 .mapbase = 0xffe10000, 313 .mapbase = 0xffe10000,
221 .flags = UPF_BOOT_AUTOCONF, 314 .flags = UPF_BOOT_AUTOCONF,
222 .type = PORT_SCIF, 315 .type = PORT_SCIF,
223 .irqs = { 81, 81, 81, 81 }, 316 .irqs = { 81, 81, 81, 81 },
317 .clk = "scif1",
224 }, 318 },
225 { 319 {
226 .mapbase = 0xffe20000, 320 .mapbase = 0xffe20000,
227 .flags = UPF_BOOT_AUTOCONF, 321 .flags = UPF_BOOT_AUTOCONF,
228 .type = PORT_SCIF, 322 .type = PORT_SCIF,
229 .irqs = { 82, 82, 82, 82 }, 323 .irqs = { 82, 82, 82, 82 },
324 .clk = "scif2",
230 }, 325 },
231 { 326 {
232 .flags = 0, 327 .flags = 0,
@@ -243,6 +338,9 @@ static struct platform_device sci_device = {
243 338
244static struct platform_device *sh7722_devices[] __initdata = { 339static struct platform_device *sh7722_devices[] __initdata = {
245 &cmt_device, 340 &cmt_device,
341 &tmu0_device,
342 &tmu1_device,
343 &tmu2_device,
246 &rtc_device, 344 &rtc_device,
247 &usbf_device, 345 &usbf_device,
248 &iic_device, 346 &iic_device,
@@ -254,12 +352,6 @@ static struct platform_device *sh7722_devices[] __initdata = {
254 352
255static int __init sh7722_devices_setup(void) 353static int __init sh7722_devices_setup(void)
256{ 354{
257 clk_always_enable("uram0"); /* URAM */
258 clk_always_enable("xymem0"); /* XYMEM */
259 clk_always_enable("veu0"); /* VEU */
260 clk_always_enable("vpu0"); /* VPU */
261 clk_always_enable("jpu0"); /* JPU */
262
263 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20); 355 platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
264 platform_resource_setup_memory(&veu_device, "veu", 2 << 20); 356 platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
265 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20); 357 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
@@ -269,6 +361,19 @@ static int __init sh7722_devices_setup(void)
269} 361}
270__initcall(sh7722_devices_setup); 362__initcall(sh7722_devices_setup);
271 363
364static struct platform_device *sh7722_early_devices[] __initdata = {
365 &cmt_device,
366 &tmu0_device,
367 &tmu1_device,
368 &tmu2_device,
369};
370
371void __init plat_early_device_setup(void)
372{
373 early_platform_add_devices(sh7722_early_devices,
374 ARRAY_SIZE(sh7722_early_devices));
375}
376
272enum { 377enum {
273 UNUSED=0, 378 UNUSED=0,
274 379
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index a800466b938c..d8f4a13aeff9 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -13,7 +13,8 @@
13#include <linux/mm.h> 13#include <linux/mm.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/uio_driver.h> 15#include <linux/uio_driver.h>
16#include <linux/sh_cmt.h> 16#include <linux/sh_timer.h>
17#include <linux/io.h>
17#include <asm/clock.h> 18#include <asm/clock.h>
18#include <asm/mmzone.h> 19#include <asm/mmzone.h>
19 20
@@ -101,13 +102,13 @@ static struct platform_device veu1_device = {
101 .num_resources = ARRAY_SIZE(veu1_resources), 102 .num_resources = ARRAY_SIZE(veu1_resources),
102}; 103};
103 104
104static struct sh_cmt_config cmt_platform_data = { 105static struct sh_timer_config cmt_platform_data = {
105 .name = "CMT", 106 .name = "CMT",
106 .channel_offset = 0x60, 107 .channel_offset = 0x60,
107 .timer_bit = 5, 108 .timer_bit = 5,
108 .clk = "cmt0", 109 .clk = "cmt0",
109 .clockevent_rating = 125, 110 .clockevent_rating = 125,
110 .clocksource_rating = 200, 111 .clocksource_rating = 125,
111}; 112};
112 113
113static struct resource cmt_resources[] = { 114static struct resource cmt_resources[] = {
@@ -133,37 +134,225 @@ static struct platform_device cmt_device = {
133 .num_resources = ARRAY_SIZE(cmt_resources), 134 .num_resources = ARRAY_SIZE(cmt_resources),
134}; 135};
135 136
137static struct sh_timer_config tmu0_platform_data = {
138 .name = "TMU0",
139 .channel_offset = 0x04,
140 .timer_bit = 0,
141 .clk = "tmu0",
142 .clockevent_rating = 200,
143};
144
145static struct resource tmu0_resources[] = {
146 [0] = {
147 .name = "TMU0",
148 .start = 0xffd80008,
149 .end = 0xffd80013,
150 .flags = IORESOURCE_MEM,
151 },
152 [1] = {
153 .start = 16,
154 .flags = IORESOURCE_IRQ,
155 },
156};
157
158static struct platform_device tmu0_device = {
159 .name = "sh_tmu",
160 .id = 0,
161 .dev = {
162 .platform_data = &tmu0_platform_data,
163 },
164 .resource = tmu0_resources,
165 .num_resources = ARRAY_SIZE(tmu0_resources),
166};
167
168static struct sh_timer_config tmu1_platform_data = {
169 .name = "TMU1",
170 .channel_offset = 0x10,
171 .timer_bit = 1,
172 .clk = "tmu0",
173 .clocksource_rating = 200,
174};
175
176static struct resource tmu1_resources[] = {
177 [0] = {
178 .name = "TMU1",
179 .start = 0xffd80014,
180 .end = 0xffd8001f,
181 .flags = IORESOURCE_MEM,
182 },
183 [1] = {
184 .start = 17,
185 .flags = IORESOURCE_IRQ,
186 },
187};
188
189static struct platform_device tmu1_device = {
190 .name = "sh_tmu",
191 .id = 1,
192 .dev = {
193 .platform_data = &tmu1_platform_data,
194 },
195 .resource = tmu1_resources,
196 .num_resources = ARRAY_SIZE(tmu1_resources),
197};
198
199static struct sh_timer_config tmu2_platform_data = {
200 .name = "TMU2",
201 .channel_offset = 0x1c,
202 .timer_bit = 2,
203 .clk = "tmu0",
204};
205
206static struct resource tmu2_resources[] = {
207 [0] = {
208 .name = "TMU2",
209 .start = 0xffd80020,
210 .end = 0xffd8002b,
211 .flags = IORESOURCE_MEM,
212 },
213 [1] = {
214 .start = 18,
215 .flags = IORESOURCE_IRQ,
216 },
217};
218
219static struct platform_device tmu2_device = {
220 .name = "sh_tmu",
221 .id = 2,
222 .dev = {
223 .platform_data = &tmu2_platform_data,
224 },
225 .resource = tmu2_resources,
226 .num_resources = ARRAY_SIZE(tmu2_resources),
227};
228
229static struct sh_timer_config tmu3_platform_data = {
230 .name = "TMU3",
231 .channel_offset = 0x04,
232 .timer_bit = 0,
233 .clk = "tmu1",
234};
235
236static struct resource tmu3_resources[] = {
237 [0] = {
238 .name = "TMU3",
239 .start = 0xffd90008,
240 .end = 0xffd90013,
241 .flags = IORESOURCE_MEM,
242 },
243 [1] = {
244 .start = 57,
245 .flags = IORESOURCE_IRQ,
246 },
247};
248
249static struct platform_device tmu3_device = {
250 .name = "sh_tmu",
251 .id = 3,
252 .dev = {
253 .platform_data = &tmu3_platform_data,
254 },
255 .resource = tmu3_resources,
256 .num_resources = ARRAY_SIZE(tmu3_resources),
257};
258
259static struct sh_timer_config tmu4_platform_data = {
260 .name = "TMU4",
261 .channel_offset = 0x10,
262 .timer_bit = 1,
263 .clk = "tmu1",
264};
265
266static struct resource tmu4_resources[] = {
267 [0] = {
268 .name = "TMU4",
269 .start = 0xffd90014,
270 .end = 0xffd9001f,
271 .flags = IORESOURCE_MEM,
272 },
273 [1] = {
274 .start = 58,
275 .flags = IORESOURCE_IRQ,
276 },
277};
278
279static struct platform_device tmu4_device = {
280 .name = "sh_tmu",
281 .id = 4,
282 .dev = {
283 .platform_data = &tmu4_platform_data,
284 },
285 .resource = tmu4_resources,
286 .num_resources = ARRAY_SIZE(tmu4_resources),
287};
288
289static struct sh_timer_config tmu5_platform_data = {
290 .name = "TMU5",
291 .channel_offset = 0x1c,
292 .timer_bit = 2,
293 .clk = "tmu1",
294};
295
296static struct resource tmu5_resources[] = {
297 [0] = {
298 .name = "TMU5",
299 .start = 0xffd90020,
300 .end = 0xffd9002b,
301 .flags = IORESOURCE_MEM,
302 },
303 [1] = {
304 .start = 57,
305 .flags = IORESOURCE_IRQ,
306 },
307};
308
309static struct platform_device tmu5_device = {
310 .name = "sh_tmu",
311 .id = 5,
312 .dev = {
313 .platform_data = &tmu5_platform_data,
314 },
315 .resource = tmu5_resources,
316 .num_resources = ARRAY_SIZE(tmu5_resources),
317};
318
136static struct plat_sci_port sci_platform_data[] = { 319static struct plat_sci_port sci_platform_data[] = {
137 { 320 {
138 .mapbase = 0xffe00000, 321 .mapbase = 0xffe00000,
139 .flags = UPF_BOOT_AUTOCONF, 322 .flags = UPF_BOOT_AUTOCONF,
140 .type = PORT_SCIF, 323 .type = PORT_SCIF,
141 .irqs = { 80, 80, 80, 80 }, 324 .irqs = { 80, 80, 80, 80 },
325 .clk = "scif0",
142 },{ 326 },{
143 .mapbase = 0xffe10000, 327 .mapbase = 0xffe10000,
144 .flags = UPF_BOOT_AUTOCONF, 328 .flags = UPF_BOOT_AUTOCONF,
145 .type = PORT_SCIF, 329 .type = PORT_SCIF,
146 .irqs = { 81, 81, 81, 81 }, 330 .irqs = { 81, 81, 81, 81 },
331 .clk = "scif1",
147 },{ 332 },{
148 .mapbase = 0xffe20000, 333 .mapbase = 0xffe20000,
149 .flags = UPF_BOOT_AUTOCONF, 334 .flags = UPF_BOOT_AUTOCONF,
150 .type = PORT_SCIF, 335 .type = PORT_SCIF,
151 .irqs = { 82, 82, 82, 82 }, 336 .irqs = { 82, 82, 82, 82 },
337 .clk = "scif2",
152 },{ 338 },{
153 .mapbase = 0xa4e30000, 339 .mapbase = 0xa4e30000,
154 .flags = UPF_BOOT_AUTOCONF, 340 .flags = UPF_BOOT_AUTOCONF,
155 .type = PORT_SCIFA, 341 .type = PORT_SCIFA,
156 .irqs = { 56, 56, 56, 56 }, 342 .irqs = { 56, 56, 56, 56 },
343 .clk = "scif3",
157 },{ 344 },{
158 .mapbase = 0xa4e40000, 345 .mapbase = 0xa4e40000,
159 .flags = UPF_BOOT_AUTOCONF, 346 .flags = UPF_BOOT_AUTOCONF,
160 .type = PORT_SCIFA, 347 .type = PORT_SCIFA,
161 .irqs = { 88, 88, 88, 88 }, 348 .irqs = { 88, 88, 88, 88 },
349 .clk = "scif4",
162 },{ 350 },{
163 .mapbase = 0xa4e50000, 351 .mapbase = 0xa4e50000,
164 .flags = UPF_BOOT_AUTOCONF, 352 .flags = UPF_BOOT_AUTOCONF,
165 .type = PORT_SCIFA, 353 .type = PORT_SCIFA,
166 .irqs = { 109, 109, 109, 109 }, 354 .irqs = { 109, 109, 109, 109 },
355 .clk = "scif5",
167 }, { 356 }, {
168 .flags = 0, 357 .flags = 0,
169 } 358 }
@@ -255,6 +444,12 @@ static struct platform_device iic_device = {
255 444
256static struct platform_device *sh7723_devices[] __initdata = { 445static struct platform_device *sh7723_devices[] __initdata = {
257 &cmt_device, 446 &cmt_device,
447 &tmu0_device,
448 &tmu1_device,
449 &tmu2_device,
450 &tmu3_device,
451 &tmu4_device,
452 &tmu5_device,
258 &sci_device, 453 &sci_device,
259 &rtc_device, 454 &rtc_device,
260 &iic_device, 455 &iic_device,
@@ -266,11 +461,6 @@ static struct platform_device *sh7723_devices[] __initdata = {
266 461
267static int __init sh7723_devices_setup(void) 462static int __init sh7723_devices_setup(void)
268{ 463{
269 clk_always_enable("meram0"); /* MERAM */
270 clk_always_enable("veu1"); /* VEU2H1 */
271 clk_always_enable("veu0"); /* VEU2H0 */
272 clk_always_enable("vpu0"); /* VPU */
273
274 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20); 464 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
275 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20); 465 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
276 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20); 466 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
@@ -280,6 +470,31 @@ static int __init sh7723_devices_setup(void)
280} 470}
281__initcall(sh7723_devices_setup); 471__initcall(sh7723_devices_setup);
282 472
473static struct platform_device *sh7723_early_devices[] __initdata = {
474 &cmt_device,
475 &tmu0_device,
476 &tmu1_device,
477 &tmu2_device,
478 &tmu3_device,
479 &tmu4_device,
480 &tmu5_device,
481};
482
483void __init plat_early_device_setup(void)
484{
485 early_platform_add_devices(sh7723_early_devices,
486 ARRAY_SIZE(sh7723_early_devices));
487}
488
489#define RAMCR_CACHE_L2FC 0x0002
490#define RAMCR_CACHE_L2E 0x0001
491#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
492void __uses_jump_to_uncached l2_cache_init(void)
493{
494 /* Enable L2 cache */
495 ctrl_outl(L2_CACHE_ENABLE, RAMCR);
496}
497
283enum { 498enum {
284 UNUSED=0, 499 UNUSED=0,
285 500
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
new file mode 100644
index 000000000000..e5ac9eb11c63
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -0,0 +1,786 @@
1/*
2 * SH7724 Setup
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
7 *
8 * Based on SH7723 Setup
9 * Copyright (C) 2008 Paul Mundt
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/platform_device.h>
16#include <linux/init.h>
17#include <linux/serial.h>
18#include <linux/mm.h>
19#include <linux/serial_sci.h>
20#include <linux/uio_driver.h>
21#include <linux/sh_timer.h>
22#include <linux/io.h>
23#include <asm/clock.h>
24#include <asm/mmzone.h>
25
26/* Serial */
27static struct plat_sci_port sci_platform_data[] = {
28 {
29 .mapbase = 0xffe00000,
30 .flags = UPF_BOOT_AUTOCONF,
31 .type = PORT_SCIF,
32 .irqs = { 80, 80, 80, 80 },
33 .clk = "scif0",
34 }, {
35 .mapbase = 0xffe10000,
36 .flags = UPF_BOOT_AUTOCONF,
37 .type = PORT_SCIF,
38 .irqs = { 81, 81, 81, 81 },
39 .clk = "scif1",
40 }, {
41 .mapbase = 0xffe20000,
42 .flags = UPF_BOOT_AUTOCONF,
43 .type = PORT_SCIF,
44 .irqs = { 82, 82, 82, 82 },
45 .clk = "scif2",
46 }, {
47 .mapbase = 0xa4e30000,
48 .flags = UPF_BOOT_AUTOCONF,
49 .type = PORT_SCIFA,
50 .irqs = { 56, 56, 56, 56 },
51 .clk = "scif3",
52 }, {
53 .mapbase = 0xa4e40000,
54 .flags = UPF_BOOT_AUTOCONF,
55 .type = PORT_SCIFA,
56 .irqs = { 88, 88, 88, 88 },
57 .clk = "scif4",
58 }, {
59 .mapbase = 0xa4e50000,
60 .flags = UPF_BOOT_AUTOCONF,
61 .type = PORT_SCIFA,
62 .irqs = { 109, 109, 109, 109 },
63 .clk = "scif5",
64 }, {
65 .flags = 0,
66 }
67};
68
69static struct platform_device sci_device = {
70 .name = "sh-sci",
71 .id = -1,
72 .dev = {
73 .platform_data = sci_platform_data,
74 },
75};
76
77/* RTC */
78static struct resource rtc_resources[] = {
79 [0] = {
80 .start = 0xa465fec0,
81 .end = 0xa465fec0 + 0x58 - 1,
82 .flags = IORESOURCE_IO,
83 },
84 [1] = {
85 /* Period IRQ */
86 .start = 69,
87 .flags = IORESOURCE_IRQ,
88 },
89 [2] = {
90 /* Carry IRQ */
91 .start = 70,
92 .flags = IORESOURCE_IRQ,
93 },
94 [3] = {
95 /* Alarm IRQ */
96 .start = 68,
97 .flags = IORESOURCE_IRQ,
98 },
99};
100
101static struct platform_device rtc_device = {
102 .name = "sh-rtc",
103 .id = -1,
104 .num_resources = ARRAY_SIZE(rtc_resources),
105 .resource = rtc_resources,
106};
107
108/* I2C0 */
109static struct resource iic0_resources[] = {
110 [0] = {
111 .name = "IIC0",
112 .start = 0x04470000,
113 .end = 0x04470018 - 1,
114 .flags = IORESOURCE_MEM,
115 },
116 [1] = {
117 .start = 96,
118 .end = 99,
119 .flags = IORESOURCE_IRQ,
120 },
121};
122
123static struct platform_device iic0_device = {
124 .name = "i2c-sh_mobile",
125 .id = 0, /* "i2c0" clock */
126 .num_resources = ARRAY_SIZE(iic0_resources),
127 .resource = iic0_resources,
128};
129
130/* I2C1 */
131static struct resource iic1_resources[] = {
132 [0] = {
133 .name = "IIC1",
134 .start = 0x04750000,
135 .end = 0x04750018 - 1,
136 .flags = IORESOURCE_MEM,
137 },
138 [1] = {
139 .start = 92,
140 .end = 95,
141 .flags = IORESOURCE_IRQ,
142 },
143};
144
145static struct platform_device iic1_device = {
146 .name = "i2c-sh_mobile",
147 .id = 1, /* "i2c1" clock */
148 .num_resources = ARRAY_SIZE(iic1_resources),
149 .resource = iic1_resources,
150};
151
152/* VPU */
153static struct uio_info vpu_platform_data = {
154 .name = "VPU5F",
155 .version = "0",
156 .irq = 60,
157};
158
159static struct resource vpu_resources[] = {
160 [0] = {
161 .name = "VPU",
162 .start = 0xfe900000,
163 .end = 0xfe902807,
164 .flags = IORESOURCE_MEM,
165 },
166 [1] = {
167 /* place holder for contiguous memory */
168 },
169};
170
171static struct platform_device vpu_device = {
172 .name = "uio_pdrv_genirq",
173 .id = 0,
174 .dev = {
175 .platform_data = &vpu_platform_data,
176 },
177 .resource = vpu_resources,
178 .num_resources = ARRAY_SIZE(vpu_resources),
179};
180
181/* VEU0 */
182static struct uio_info veu0_platform_data = {
183 .name = "VEU3F0",
184 .version = "0",
185 .irq = 83,
186};
187
188static struct resource veu0_resources[] = {
189 [0] = {
190 .name = "VEU3F0",
191 .start = 0xfe920000,
192 .end = 0xfe9200cb - 1,
193 .flags = IORESOURCE_MEM,
194 },
195 [1] = {
196 /* place holder for contiguous memory */
197 },
198};
199
200static struct platform_device veu0_device = {
201 .name = "uio_pdrv_genirq",
202 .id = 1,
203 .dev = {
204 .platform_data = &veu0_platform_data,
205 },
206 .resource = veu0_resources,
207 .num_resources = ARRAY_SIZE(veu0_resources),
208};
209
210/* VEU1 */
211static struct uio_info veu1_platform_data = {
212 .name = "VEU3F1",
213 .version = "0",
214 .irq = 54,
215};
216
217static struct resource veu1_resources[] = {
218 [0] = {
219 .name = "VEU3F1",
220 .start = 0xfe924000,
221 .end = 0xfe9240cb - 1,
222 .flags = IORESOURCE_MEM,
223 },
224 [1] = {
225 /* place holder for contiguous memory */
226 },
227};
228
229static struct platform_device veu1_device = {
230 .name = "uio_pdrv_genirq",
231 .id = 2,
232 .dev = {
233 .platform_data = &veu1_platform_data,
234 },
235 .resource = veu1_resources,
236 .num_resources = ARRAY_SIZE(veu1_resources),
237};
238
239static struct sh_timer_config cmt_platform_data = {
240 .name = "CMT",
241 .channel_offset = 0x60,
242 .timer_bit = 5,
243 .clk = "cmt0",
244 .clockevent_rating = 125,
245 .clocksource_rating = 200,
246};
247
248static struct resource cmt_resources[] = {
249 [0] = {
250 .name = "CMT",
251 .start = 0x044a0060,
252 .end = 0x044a006b,
253 .flags = IORESOURCE_MEM,
254 },
255 [1] = {
256 .start = 104,
257 .flags = IORESOURCE_IRQ,
258 },
259};
260
261static struct platform_device cmt_device = {
262 .name = "sh_cmt",
263 .id = 0,
264 .dev = {
265 .platform_data = &cmt_platform_data,
266 },
267 .resource = cmt_resources,
268 .num_resources = ARRAY_SIZE(cmt_resources),
269};
270
271static struct sh_timer_config tmu0_platform_data = {
272 .name = "TMU0",
273 .channel_offset = 0x04,
274 .timer_bit = 0,
275 .clk = "tmu0",
276 .clockevent_rating = 200,
277};
278
279static struct resource tmu0_resources[] = {
280 [0] = {
281 .name = "TMU0",
282 .start = 0xffd80008,
283 .end = 0xffd80013,
284 .flags = IORESOURCE_MEM,
285 },
286 [1] = {
287 .start = 16,
288 .flags = IORESOURCE_IRQ,
289 },
290};
291
292static struct platform_device tmu0_device = {
293 .name = "sh_tmu",
294 .id = 0,
295 .dev = {
296 .platform_data = &tmu0_platform_data,
297 },
298 .resource = tmu0_resources,
299 .num_resources = ARRAY_SIZE(tmu0_resources),
300};
301
302static struct sh_timer_config tmu1_platform_data = {
303 .name = "TMU1",
304 .channel_offset = 0x10,
305 .timer_bit = 1,
306 .clk = "tmu0",
307 .clocksource_rating = 200,
308};
309
310static struct resource tmu1_resources[] = {
311 [0] = {
312 .name = "TMU1",
313 .start = 0xffd80014,
314 .end = 0xffd8001f,
315 .flags = IORESOURCE_MEM,
316 },
317 [1] = {
318 .start = 17,
319 .flags = IORESOURCE_IRQ,
320 },
321};
322
323static struct platform_device tmu1_device = {
324 .name = "sh_tmu",
325 .id = 1,
326 .dev = {
327 .platform_data = &tmu1_platform_data,
328 },
329 .resource = tmu1_resources,
330 .num_resources = ARRAY_SIZE(tmu1_resources),
331};
332
333static struct sh_timer_config tmu2_platform_data = {
334 .name = "TMU2",
335 .channel_offset = 0x1c,
336 .timer_bit = 2,
337 .clk = "tmu0",
338};
339
340static struct resource tmu2_resources[] = {
341 [0] = {
342 .name = "TMU2",
343 .start = 0xffd80020,
344 .end = 0xffd8002b,
345 .flags = IORESOURCE_MEM,
346 },
347 [1] = {
348 .start = 18,
349 .flags = IORESOURCE_IRQ,
350 },
351};
352
353static struct platform_device tmu2_device = {
354 .name = "sh_tmu",
355 .id = 2,
356 .dev = {
357 .platform_data = &tmu2_platform_data,
358 },
359 .resource = tmu2_resources,
360 .num_resources = ARRAY_SIZE(tmu2_resources),
361};
362
363
364static struct sh_timer_config tmu3_platform_data = {
365 .name = "TMU3",
366 .channel_offset = 0x04,
367 .timer_bit = 0,
368 .clk = "tmu1",
369};
370
371static struct resource tmu3_resources[] = {
372 [0] = {
373 .name = "TMU3",
374 .start = 0xffd90008,
375 .end = 0xffd90013,
376 .flags = IORESOURCE_MEM,
377 },
378 [1] = {
379 .start = 57,
380 .flags = IORESOURCE_IRQ,
381 },
382};
383
384static struct platform_device tmu3_device = {
385 .name = "sh_tmu",
386 .id = 3,
387 .dev = {
388 .platform_data = &tmu3_platform_data,
389 },
390 .resource = tmu3_resources,
391 .num_resources = ARRAY_SIZE(tmu3_resources),
392};
393
394static struct sh_timer_config tmu4_platform_data = {
395 .name = "TMU4",
396 .channel_offset = 0x10,
397 .timer_bit = 1,
398 .clk = "tmu1",
399};
400
401static struct resource tmu4_resources[] = {
402 [0] = {
403 .name = "TMU4",
404 .start = 0xffd90014,
405 .end = 0xffd9001f,
406 .flags = IORESOURCE_MEM,
407 },
408 [1] = {
409 .start = 58,
410 .flags = IORESOURCE_IRQ,
411 },
412};
413
414static struct platform_device tmu4_device = {
415 .name = "sh_tmu",
416 .id = 4,
417 .dev = {
418 .platform_data = &tmu4_platform_data,
419 },
420 .resource = tmu4_resources,
421 .num_resources = ARRAY_SIZE(tmu4_resources),
422};
423
424static struct sh_timer_config tmu5_platform_data = {
425 .name = "TMU5",
426 .channel_offset = 0x1c,
427 .timer_bit = 2,
428 .clk = "tmu1",
429};
430
431static struct resource tmu5_resources[] = {
432 [0] = {
433 .name = "TMU5",
434 .start = 0xffd90020,
435 .end = 0xffd9002b,
436 .flags = IORESOURCE_MEM,
437 },
438 [1] = {
439 .start = 57,
440 .flags = IORESOURCE_IRQ,
441 },
442};
443
444static struct platform_device tmu5_device = {
445 .name = "sh_tmu",
446 .id = 5,
447 .dev = {
448 .platform_data = &tmu5_platform_data,
449 },
450 .resource = tmu5_resources,
451 .num_resources = ARRAY_SIZE(tmu5_resources),
452};
453
454/* JPU */
455static struct uio_info jpu_platform_data = {
456 .name = "JPU",
457 .version = "0",
458 .irq = 27,
459};
460
461static struct resource jpu_resources[] = {
462 [0] = {
463 .name = "JPU",
464 .start = 0xfe980000,
465 .end = 0xfe9902d3,
466 .flags = IORESOURCE_MEM,
467 },
468 [1] = {
469 /* place holder for contiguous memory */
470 },
471};
472
473static struct platform_device jpu_device = {
474 .name = "uio_pdrv_genirq",
475 .id = 3,
476 .dev = {
477 .platform_data = &jpu_platform_data,
478 },
479 .resource = jpu_resources,
480 .num_resources = ARRAY_SIZE(jpu_resources),
481};
482
483static struct platform_device *sh7724_devices[] __initdata = {
484 &cmt_device,
485 &tmu0_device,
486 &tmu1_device,
487 &tmu2_device,
488 &tmu3_device,
489 &tmu4_device,
490 &tmu5_device,
491 &sci_device,
492 &rtc_device,
493 &iic0_device,
494 &iic1_device,
495 &vpu_device,
496 &veu0_device,
497 &veu1_device,
498 &jpu_device,
499};
500
501static int __init sh7724_devices_setup(void)
502{
503 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
504 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
505 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
506 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
507
508 return platform_add_devices(sh7724_devices,
509 ARRAY_SIZE(sh7724_devices));
510}
511device_initcall(sh7724_devices_setup);
512
513static struct platform_device *sh7724_early_devices[] __initdata = {
514 &cmt_device,
515 &tmu0_device,
516 &tmu1_device,
517 &tmu2_device,
518 &tmu3_device,
519 &tmu4_device,
520 &tmu5_device,
521};
522
523void __init plat_early_device_setup(void)
524{
525 early_platform_add_devices(sh7724_early_devices,
526 ARRAY_SIZE(sh7724_early_devices));
527}
528
529#define RAMCR_CACHE_L2FC 0x0002
530#define RAMCR_CACHE_L2E 0x0001
531#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
532void __uses_jump_to_uncached l2_cache_init(void)
533{
534 /* Enable L2 cache */
535 ctrl_outl(L2_CACHE_ENABLE, RAMCR);
536}
537
538enum {
539 UNUSED = 0,
540
541 /* interrupt sources */
542 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
543 HUDI,
544 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
545 _2DG_TRI, _2DG_INI, _2DG_CEI,
546 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
547 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
548 SCIFA3,
549 VPU,
550 TPU,
551 CEU1,
552 BEU1,
553 USB0, USB1,
554 ATAPI,
555 RTC_ATI, RTC_PRI, RTC_CUI,
556 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
557 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
558 KEYSC,
559 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
560 VEU0,
561 MSIOF_MSIOFI0, MSIOF_MSIOFI1,
562 SPU_SPUI0, SPU_SPUI1,
563 SCIFA4,
564 ICB,
565 ETHI,
566 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
567 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
568 SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3,
569 CMT,
570 TSIF,
571 FSI,
572 SCIFA5,
573 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
574 IRDA,
575 SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2,
576 JPU,
577 _2DDMAC,
578 MMC_MMC2I, MMC_MMC3I,
579 LCDC,
580 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
581
582 /* interrupt groups */
583 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
584 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
585};
586
587static struct intc_vect vectors[] __initdata = {
588 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
589 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
590 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
591 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
592
593 INTC_VECT(DMAC1A_DEI0, 0x700),
594 INTC_VECT(DMAC1A_DEI1, 0x720),
595 INTC_VECT(DMAC1A_DEI2, 0x740),
596 INTC_VECT(DMAC1A_DEI3, 0x760),
597
598 INTC_VECT(_2DG_TRI, 0x780),
599 INTC_VECT(_2DG_INI, 0x7A0),
600 INTC_VECT(_2DG_CEI, 0x7C0),
601
602 INTC_VECT(DMAC0A_DEI0, 0x800),
603 INTC_VECT(DMAC0A_DEI1, 0x820),
604 INTC_VECT(DMAC0A_DEI2, 0x840),
605 INTC_VECT(DMAC0A_DEI3, 0x860),
606
607 INTC_VECT(VIO_CEU0, 0x880),
608 INTC_VECT(VIO_BEU0, 0x8A0),
609 INTC_VECT(VIO_VEU1, 0x8C0),
610 INTC_VECT(VIO_VOU, 0x8E0),
611
612 INTC_VECT(SCIFA3, 0x900),
613 INTC_VECT(VPU, 0x980),
614 INTC_VECT(TPU, 0x9A0),
615 INTC_VECT(CEU1, 0x9E0),
616 INTC_VECT(BEU1, 0xA00),
617 INTC_VECT(USB0, 0xA20),
618 INTC_VECT(USB1, 0xA40),
619 INTC_VECT(ATAPI, 0xA60),
620
621 INTC_VECT(RTC_ATI, 0xA80),
622 INTC_VECT(RTC_PRI, 0xAA0),
623 INTC_VECT(RTC_CUI, 0xAC0),
624
625 INTC_VECT(DMAC1B_DEI4, 0xB00),
626 INTC_VECT(DMAC1B_DEI5, 0xB20),
627 INTC_VECT(DMAC1B_DADERR, 0xB40),
628
629 INTC_VECT(DMAC0B_DEI4, 0xB80),
630 INTC_VECT(DMAC0B_DEI5, 0xBA0),
631 INTC_VECT(DMAC0B_DADERR, 0xBC0),
632
633 INTC_VECT(KEYSC, 0xBE0),
634 INTC_VECT(SCIF_SCIF0, 0xC00),
635 INTC_VECT(SCIF_SCIF1, 0xC20),
636 INTC_VECT(SCIF_SCIF2, 0xC40),
637 INTC_VECT(VEU0, 0xC60),
638 INTC_VECT(MSIOF_MSIOFI0, 0xC80),
639 INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
640 INTC_VECT(SPU_SPUI0, 0xCC0),
641 INTC_VECT(SPU_SPUI1, 0xCE0),
642 INTC_VECT(SCIFA4, 0xD00),
643
644 INTC_VECT(ICB, 0xD20),
645 INTC_VECT(ETHI, 0xD60),
646
647 INTC_VECT(I2C1_ALI, 0xD80),
648 INTC_VECT(I2C1_TACKI, 0xDA0),
649 INTC_VECT(I2C1_WAITI, 0xDC0),
650 INTC_VECT(I2C1_DTEI, 0xDE0),
651
652 INTC_VECT(I2C0_ALI, 0xE00),
653 INTC_VECT(I2C0_TACKI, 0xE20),
654 INTC_VECT(I2C0_WAITI, 0xE40),
655 INTC_VECT(I2C0_DTEI, 0xE60),
656
657 INTC_VECT(SDHI0_SDHII0, 0xE80),
658 INTC_VECT(SDHI0_SDHII1, 0xEA0),
659 INTC_VECT(SDHI0_SDHII2, 0xEC0),
660 INTC_VECT(SDHI0_SDHII3, 0xEE0),
661
662 INTC_VECT(CMT, 0xF00),
663 INTC_VECT(TSIF, 0xF20),
664 INTC_VECT(FSI, 0xF80),
665 INTC_VECT(SCIFA5, 0xFA0),
666
667 INTC_VECT(TMU0_TUNI0, 0x400),
668 INTC_VECT(TMU0_TUNI1, 0x420),
669 INTC_VECT(TMU0_TUNI2, 0x440),
670
671 INTC_VECT(IRDA, 0x480),
672
673 INTC_VECT(SDHI1_SDHII0, 0x4E0),
674 INTC_VECT(SDHI1_SDHII1, 0x500),
675 INTC_VECT(SDHI1_SDHII2, 0x520),
676
677 INTC_VECT(JPU, 0x560),
678 INTC_VECT(_2DDMAC, 0x4A0),
679
680 INTC_VECT(MMC_MMC2I, 0x5A0),
681 INTC_VECT(MMC_MMC3I, 0x5C0),
682
683 INTC_VECT(LCDC, 0xF40),
684
685 INTC_VECT(TMU1_TUNI0, 0x920),
686 INTC_VECT(TMU1_TUNI1, 0x940),
687 INTC_VECT(TMU1_TUNI2, 0x960),
688};
689
690static struct intc_group groups[] __initdata = {
691 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
692 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
693 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
694 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
695 INTC_GROUP(USB, USB0, USB1),
696 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
697 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
698 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
699 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
700 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
701 INTC_GROUP(SDHI0, SDHI0_SDHII0, SDHI0_SDHII1, SDHI0_SDHII2, SDHI0_SDHII3),
702 INTC_GROUP(SDHI1, SDHI1_SDHII0, SDHI1_SDHII1, SDHI1_SDHII2),
703 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
704 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
705};
706
707static struct intc_mask_reg mask_registers[] __initdata = {
708 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
709 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
710 0, SDHI1_SDHII2, SDHI1_SDHII1, SDHI1_SDHII0 } },
711 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
712 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
713 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
714 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
715 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
716 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
717 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
718 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
719 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
720 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
721 JPU, 0, 0, LCDC } },
722 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
723 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
724 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
725 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
726 { 0, 0, ICB, SCIFA4,
727 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
728 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
729 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
730 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
731 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
732 { SDHI0_SDHII3, SDHI0_SDHII2, SDHI0_SDHII1, SDHI0_SDHII0,
733 0, 0, SCIFA5, FSI } },
734 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
735 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
736 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
737 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
738 0, RTC_CUI, RTC_PRI, RTC_ATI } },
739 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
740 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
741 0, TPU, 0, TSIF } },
742 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
743 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
744 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
745 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
746};
747
748static struct intc_prio_reg prio_registers[] __initdata = {
749 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
750 TMU0_TUNI2, IRDA } },
751 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
752 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
753 TMU1_TUNI2, SPU } },
754 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } },
755 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
756 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } },
757 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
758 SCIF_SCIF2, VEU0 } },
759 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
760 I2C1, I2C0 } },
761 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } },
762 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } },
763 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } },
764 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
765 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
766 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
767};
768
769static struct intc_sense_reg sense_registers[] __initdata = {
770 { 0xa414001c, 16, 2, /* ICR1 */
771 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
772};
773
774static struct intc_mask_reg ack_registers[] __initdata = {
775 { 0xa4140024, 0, 8, /* INTREQ00 */
776 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
777};
778
779static DECLARE_INTC_DESC_ACK(intc_desc, "sh7724", vectors, groups,
780 mask_registers, prio_registers, sense_registers,
781 ack_registers);
782
783void __init plat_irq_setup(void)
784{
785 register_intc_controller(&intc_desc);
786}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index bdf0f61ae1ed..f1e0c0d36da7 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -12,6 +12,7 @@
12#include <linux/platform_device.h> 12#include <linux/platform_device.h>
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/serial.h> 14#include <linux/serial.h>
15#include <linux/sh_timer.h>
15#include <linux/io.h> 16#include <linux/io.h>
16#include <linux/serial_sci.h> 17#include <linux/serial_sci.h>
17 18
@@ -113,7 +114,195 @@ static struct platform_device usbf_device = {
113 .resource = usbf_resources, 114 .resource = usbf_resources,
114}; 115};
115 116
117static struct sh_timer_config tmu0_platform_data = {
118 .name = "TMU0",
119 .channel_offset = 0x04,
120 .timer_bit = 0,
121 .clk = "peripheral_clk",
122 .clockevent_rating = 200,
123};
124
125static struct resource tmu0_resources[] = {
126 [0] = {
127 .name = "TMU0",
128 .start = 0xffd80008,
129 .end = 0xffd80013,
130 .flags = IORESOURCE_MEM,
131 },
132 [1] = {
133 .start = 28,
134 .flags = IORESOURCE_IRQ,
135 },
136};
137
138static struct platform_device tmu0_device = {
139 .name = "sh_tmu",
140 .id = 0,
141 .dev = {
142 .platform_data = &tmu0_platform_data,
143 },
144 .resource = tmu0_resources,
145 .num_resources = ARRAY_SIZE(tmu0_resources),
146};
147
148static struct sh_timer_config tmu1_platform_data = {
149 .name = "TMU1",
150 .channel_offset = 0x10,
151 .timer_bit = 1,
152 .clk = "peripheral_clk",
153 .clocksource_rating = 200,
154};
155
156static struct resource tmu1_resources[] = {
157 [0] = {
158 .name = "TMU1",
159 .start = 0xffd80014,
160 .end = 0xffd8001f,
161 .flags = IORESOURCE_MEM,
162 },
163 [1] = {
164 .start = 29,
165 .flags = IORESOURCE_IRQ,
166 },
167};
168
169static struct platform_device tmu1_device = {
170 .name = "sh_tmu",
171 .id = 1,
172 .dev = {
173 .platform_data = &tmu1_platform_data,
174 },
175 .resource = tmu1_resources,
176 .num_resources = ARRAY_SIZE(tmu1_resources),
177};
178
179static struct sh_timer_config tmu2_platform_data = {
180 .name = "TMU2",
181 .channel_offset = 0x1c,
182 .timer_bit = 2,
183 .clk = "peripheral_clk",
184};
185
186static struct resource tmu2_resources[] = {
187 [0] = {
188 .name = "TMU2",
189 .start = 0xffd80020,
190 .end = 0xffd8002f,
191 .flags = IORESOURCE_MEM,
192 },
193 [1] = {
194 .start = 30,
195 .flags = IORESOURCE_IRQ,
196 },
197};
198
199static struct platform_device tmu2_device = {
200 .name = "sh_tmu",
201 .id = 2,
202 .dev = {
203 .platform_data = &tmu2_platform_data,
204 },
205 .resource = tmu2_resources,
206 .num_resources = ARRAY_SIZE(tmu2_resources),
207};
208
209static struct sh_timer_config tmu3_platform_data = {
210 .name = "TMU3",
211 .channel_offset = 0x04,
212 .timer_bit = 0,
213 .clk = "peripheral_clk",
214};
215
216static struct resource tmu3_resources[] = {
217 [0] = {
218 .name = "TMU3",
219 .start = 0xffd88008,
220 .end = 0xffd88013,
221 .flags = IORESOURCE_MEM,
222 },
223 [1] = {
224 .start = 96,
225 .flags = IORESOURCE_IRQ,
226 },
227};
228
229static struct platform_device tmu3_device = {
230 .name = "sh_tmu",
231 .id = 3,
232 .dev = {
233 .platform_data = &tmu3_platform_data,
234 },
235 .resource = tmu3_resources,
236 .num_resources = ARRAY_SIZE(tmu3_resources),
237};
238
239static struct sh_timer_config tmu4_platform_data = {
240 .name = "TMU4",
241 .channel_offset = 0x10,
242 .timer_bit = 1,
243 .clk = "peripheral_clk",
244};
245
246static struct resource tmu4_resources[] = {
247 [0] = {
248 .name = "TMU4",
249 .start = 0xffd88014,
250 .end = 0xffd8801f,
251 .flags = IORESOURCE_MEM,
252 },
253 [1] = {
254 .start = 97,
255 .flags = IORESOURCE_IRQ,
256 },
257};
258
259static struct platform_device tmu4_device = {
260 .name = "sh_tmu",
261 .id = 4,
262 .dev = {
263 .platform_data = &tmu4_platform_data,
264 },
265 .resource = tmu4_resources,
266 .num_resources = ARRAY_SIZE(tmu4_resources),
267};
268
269static struct sh_timer_config tmu5_platform_data = {
270 .name = "TMU5",
271 .channel_offset = 0x1c,
272 .timer_bit = 2,
273 .clk = "peripheral_clk",
274};
275
276static struct resource tmu5_resources[] = {
277 [0] = {
278 .name = "TMU5",
279 .start = 0xffd88020,
280 .end = 0xffd8802b,
281 .flags = IORESOURCE_MEM,
282 },
283 [1] = {
284 .start = 98,
285 .flags = IORESOURCE_IRQ,
286 },
287};
288
289static struct platform_device tmu5_device = {
290 .name = "sh_tmu",
291 .id = 5,
292 .dev = {
293 .platform_data = &tmu5_platform_data,
294 },
295 .resource = tmu5_resources,
296 .num_resources = ARRAY_SIZE(tmu5_resources),
297};
298
116static struct platform_device *sh7763_devices[] __initdata = { 299static struct platform_device *sh7763_devices[] __initdata = {
300 &tmu0_device,
301 &tmu1_device,
302 &tmu2_device,
303 &tmu3_device,
304 &tmu4_device,
305 &tmu5_device,
117 &rtc_device, 306 &rtc_device,
118 &sci_device, 307 &sci_device,
119 &usb_ohci_device, 308 &usb_ohci_device,
@@ -127,6 +316,21 @@ static int __init sh7763_devices_setup(void)
127} 316}
128__initcall(sh7763_devices_setup); 317__initcall(sh7763_devices_setup);
129 318
319static struct platform_device *sh7763_early_devices[] __initdata = {
320 &tmu0_device,
321 &tmu1_device,
322 &tmu2_device,
323 &tmu3_device,
324 &tmu4_device,
325 &tmu5_device,
326};
327
328void __init plat_early_device_setup(void)
329{
330 early_platform_add_devices(sh7763_early_devices,
331 ARRAY_SIZE(sh7763_early_devices));
332}
333
130enum { 334enum {
131 UNUSED = 0, 335 UNUSED = 0,
132 336
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index b73578ee295d..1e86209db284 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -11,6 +11,8 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/sh_timer.h>
15#include <linux/io.h>
14 16
15static struct plat_sci_port sci_platform_data[] = { 17static struct plat_sci_port sci_platform_data[] = {
16 { 18 {
@@ -76,7 +78,288 @@ static struct platform_device sci_device = {
76 }, 78 },
77}; 79};
78 80
81static struct sh_timer_config tmu0_platform_data = {
82 .name = "TMU0",
83 .channel_offset = 0x04,
84 .timer_bit = 0,
85 .clk = "peripheral_clk",
86 .clockevent_rating = 200,
87};
88
89static struct resource tmu0_resources[] = {
90 [0] = {
91 .name = "TMU0",
92 .start = 0xffd80008,
93 .end = 0xffd80013,
94 .flags = IORESOURCE_MEM,
95 },
96 [1] = {
97 .start = 16,
98 .flags = IORESOURCE_IRQ,
99 },
100};
101
102static struct platform_device tmu0_device = {
103 .name = "sh_tmu",
104 .id = 0,
105 .dev = {
106 .platform_data = &tmu0_platform_data,
107 },
108 .resource = tmu0_resources,
109 .num_resources = ARRAY_SIZE(tmu0_resources),
110};
111
112static struct sh_timer_config tmu1_platform_data = {
113 .name = "TMU1",
114 .channel_offset = 0x10,
115 .timer_bit = 1,
116 .clk = "peripheral_clk",
117 .clocksource_rating = 200,
118};
119
120static struct resource tmu1_resources[] = {
121 [0] = {
122 .name = "TMU1",
123 .start = 0xffd80014,
124 .end = 0xffd8001f,
125 .flags = IORESOURCE_MEM,
126 },
127 [1] = {
128 .start = 17,
129 .flags = IORESOURCE_IRQ,
130 },
131};
132
133static struct platform_device tmu1_device = {
134 .name = "sh_tmu",
135 .id = 1,
136 .dev = {
137 .platform_data = &tmu1_platform_data,
138 },
139 .resource = tmu1_resources,
140 .num_resources = ARRAY_SIZE(tmu1_resources),
141};
142
143static struct sh_timer_config tmu2_platform_data = {
144 .name = "TMU2",
145 .channel_offset = 0x1c,
146 .timer_bit = 2,
147 .clk = "peripheral_clk",
148};
149
150static struct resource tmu2_resources[] = {
151 [0] = {
152 .name = "TMU2",
153 .start = 0xffd80020,
154 .end = 0xffd8002f,
155 .flags = IORESOURCE_MEM,
156 },
157 [1] = {
158 .start = 18,
159 .flags = IORESOURCE_IRQ,
160 },
161};
162
163static struct platform_device tmu2_device = {
164 .name = "sh_tmu",
165 .id = 2,
166 .dev = {
167 .platform_data = &tmu2_platform_data,
168 },
169 .resource = tmu2_resources,
170 .num_resources = ARRAY_SIZE(tmu2_resources),
171};
172
173static struct sh_timer_config tmu3_platform_data = {
174 .name = "TMU3",
175 .channel_offset = 0x04,
176 .timer_bit = 0,
177 .clk = "peripheral_clk",
178};
179
180static struct resource tmu3_resources[] = {
181 [0] = {
182 .name = "TMU3",
183 .start = 0xffd81008,
184 .end = 0xffd81013,
185 .flags = IORESOURCE_MEM,
186 },
187 [1] = {
188 .start = 19,
189 .flags = IORESOURCE_IRQ,
190 },
191};
192
193static struct platform_device tmu3_device = {
194 .name = "sh_tmu",
195 .id = 3,
196 .dev = {
197 .platform_data = &tmu3_platform_data,
198 },
199 .resource = tmu3_resources,
200 .num_resources = ARRAY_SIZE(tmu3_resources),
201};
202
203static struct sh_timer_config tmu4_platform_data = {
204 .name = "TMU4",
205 .channel_offset = 0x10,
206 .timer_bit = 1,
207 .clk = "peripheral_clk",
208};
209
210static struct resource tmu4_resources[] = {
211 [0] = {
212 .name = "TMU4",
213 .start = 0xffd81014,
214 .end = 0xffd8101f,
215 .flags = IORESOURCE_MEM,
216 },
217 [1] = {
218 .start = 20,
219 .flags = IORESOURCE_IRQ,
220 },
221};
222
223static struct platform_device tmu4_device = {
224 .name = "sh_tmu",
225 .id = 4,
226 .dev = {
227 .platform_data = &tmu4_platform_data,
228 },
229 .resource = tmu4_resources,
230 .num_resources = ARRAY_SIZE(tmu4_resources),
231};
232
233static struct sh_timer_config tmu5_platform_data = {
234 .name = "TMU5",
235 .channel_offset = 0x1c,
236 .timer_bit = 2,
237 .clk = "peripheral_clk",
238};
239
240static struct resource tmu5_resources[] = {
241 [0] = {
242 .name = "TMU5",
243 .start = 0xffd81020,
244 .end = 0xffd8102f,
245 .flags = IORESOURCE_MEM,
246 },
247 [1] = {
248 .start = 21,
249 .flags = IORESOURCE_IRQ,
250 },
251};
252
253static struct platform_device tmu5_device = {
254 .name = "sh_tmu",
255 .id = 5,
256 .dev = {
257 .platform_data = &tmu5_platform_data,
258 },
259 .resource = tmu5_resources,
260 .num_resources = ARRAY_SIZE(tmu5_resources),
261};
262
263static struct sh_timer_config tmu6_platform_data = {
264 .name = "TMU6",
265 .channel_offset = 0x04,
266 .timer_bit = 0,
267 .clk = "peripheral_clk",
268};
269
270static struct resource tmu6_resources[] = {
271 [0] = {
272 .name = "TMU6",
273 .start = 0xffd82008,
274 .end = 0xffd82013,
275 .flags = IORESOURCE_MEM,
276 },
277 [1] = {
278 .start = 22,
279 .flags = IORESOURCE_IRQ,
280 },
281};
282
283static struct platform_device tmu6_device = {
284 .name = "sh_tmu",
285 .id = 6,
286 .dev = {
287 .platform_data = &tmu6_platform_data,
288 },
289 .resource = tmu6_resources,
290 .num_resources = ARRAY_SIZE(tmu6_resources),
291};
292
293static struct sh_timer_config tmu7_platform_data = {
294 .name = "TMU7",
295 .channel_offset = 0x10,
296 .timer_bit = 1,
297 .clk = "peripheral_clk",
298};
299
300static struct resource tmu7_resources[] = {
301 [0] = {
302 .name = "TMU7",
303 .start = 0xffd82014,
304 .end = 0xffd8201f,
305 .flags = IORESOURCE_MEM,
306 },
307 [1] = {
308 .start = 23,
309 .flags = IORESOURCE_IRQ,
310 },
311};
312
313static struct platform_device tmu7_device = {
314 .name = "sh_tmu",
315 .id = 7,
316 .dev = {
317 .platform_data = &tmu7_platform_data,
318 },
319 .resource = tmu7_resources,
320 .num_resources = ARRAY_SIZE(tmu7_resources),
321};
322
323static struct sh_timer_config tmu8_platform_data = {
324 .name = "TMU8",
325 .channel_offset = 0x1c,
326 .timer_bit = 2,
327 .clk = "peripheral_clk",
328};
329
330static struct resource tmu8_resources[] = {
331 [0] = {
332 .name = "TMU8",
333 .start = 0xffd82020,
334 .end = 0xffd8202b,
335 .flags = IORESOURCE_MEM,
336 },
337 [1] = {
338 .start = 24,
339 .flags = IORESOURCE_IRQ,
340 },
341};
342
343static struct platform_device tmu8_device = {
344 .name = "sh_tmu",
345 .id = 8,
346 .dev = {
347 .platform_data = &tmu8_platform_data,
348 },
349 .resource = tmu8_resources,
350 .num_resources = ARRAY_SIZE(tmu8_resources),
351};
352
79static struct platform_device *sh7770_devices[] __initdata = { 353static struct platform_device *sh7770_devices[] __initdata = {
354 &tmu0_device,
355 &tmu1_device,
356 &tmu2_device,
357 &tmu3_device,
358 &tmu4_device,
359 &tmu5_device,
360 &tmu6_device,
361 &tmu7_device,
362 &tmu8_device,
80 &sci_device, 363 &sci_device,
81}; 364};
82 365
@@ -87,6 +370,269 @@ static int __init sh7770_devices_setup(void)
87} 370}
88__initcall(sh7770_devices_setup); 371__initcall(sh7770_devices_setup);
89 372
373static struct platform_device *sh7770_early_devices[] __initdata = {
374 &tmu0_device,
375 &tmu1_device,
376 &tmu2_device,
377 &tmu3_device,
378 &tmu4_device,
379 &tmu5_device,
380 &tmu6_device,
381 &tmu7_device,
382 &tmu8_device,
383};
384
385void __init plat_early_device_setup(void)
386{
387 early_platform_add_devices(sh7770_early_devices,
388 ARRAY_SIZE(sh7770_early_devices));
389}
390
391enum {
392 UNUSED = 0,
393
394 /* interrupt sources */
395 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
396 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
397 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
398 IRL_HHLL, IRL_HHLH, IRL_HHHL,
399
400 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
401
402 GPIO,
403 TMU0, TMU1, TMU2, TMU2_TICPI,
404 TMU3, TMU4, TMU5, TMU5_TICPI,
405 TMU6, TMU7, TMU8,
406 HAC, IPI, SPDIF, HUDI, I2C,
407 DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
408 I2S0, I2S1, I2S2, I2S3,
409 SRC_RX, SRC_TX, SRC_SPDIF,
410 DU, VIDEO_IN, REMOTE, YUV, USB, ATAPI, CAN, GPS, GFX2D,
411 GFX3D_MBX, GFX3D_DMAC,
412 EXBUS_ATA,
413 SPI0, SPI1,
414 SCIF089, SCIF1234, SCIF567,
415 ADC,
416 BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
417 BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
418 BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31,
419
420 /* interrupt groups */
421 TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC,
422};
423
424static struct intc_vect vectors[] __initdata = {
425 INTC_VECT(GPIO, 0x3e0),
426 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
427 INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
428 INTC_VECT(TMU3, 0x480), INTC_VECT(TMU4, 0x4a0),
429 INTC_VECT(TMU5, 0x4c0), INTC_VECT(TMU5_TICPI, 0x4e0),
430 INTC_VECT(TMU6, 0x500), INTC_VECT(TMU7, 0x520),
431 INTC_VECT(TMU8, 0x540),
432 INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0),
433 INTC_VECT(SPDIF, 0x5e0),
434 INTC_VECT(HUDI, 0x600), INTC_VECT(I2C, 0x620),
435 INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
436 INTC_VECT(DMAC0_DMINT2, 0x680),
437 INTC_VECT(I2S0, 0x6a0), INTC_VECT(I2S1, 0x6c0),
438 INTC_VECT(I2S2, 0x6e0), INTC_VECT(I2S3, 0x700),
439 INTC_VECT(SRC_RX, 0x720), INTC_VECT(SRC_TX, 0x740),
440 INTC_VECT(SRC_SPDIF, 0x760),
441 INTC_VECT(DU, 0x780), INTC_VECT(VIDEO_IN, 0x7a0),
442 INTC_VECT(REMOTE, 0x7c0), INTC_VECT(YUV, 0x7e0),
443 INTC_VECT(USB, 0x840), INTC_VECT(ATAPI, 0x860),
444 INTC_VECT(CAN, 0x880), INTC_VECT(GPS, 0x8a0),
445 INTC_VECT(GFX2D, 0x8c0),
446 INTC_VECT(GFX3D_MBX, 0x900), INTC_VECT(GFX3D_DMAC, 0x920),
447 INTC_VECT(EXBUS_ATA, 0x940),
448 INTC_VECT(SPI0, 0x960), INTC_VECT(SPI1, 0x980),
449 INTC_VECT(SCIF089, 0x9a0), INTC_VECT(SCIF1234, 0x9c0),
450 INTC_VECT(SCIF1234, 0x9e0), INTC_VECT(SCIF1234, 0xa00),
451 INTC_VECT(SCIF1234, 0xa20), INTC_VECT(SCIF567, 0xa40),
452 INTC_VECT(SCIF567, 0xa60), INTC_VECT(SCIF567, 0xa80),
453 INTC_VECT(SCIF089, 0xaa0), INTC_VECT(SCIF089, 0xac0),
454 INTC_VECT(ADC, 0xb20),
455 INTC_VECT(BBDMAC_0_3, 0xba0), INTC_VECT(BBDMAC_0_3, 0xbc0),
456 INTC_VECT(BBDMAC_0_3, 0xbe0), INTC_VECT(BBDMAC_0_3, 0xc00),
457 INTC_VECT(BBDMAC_4_7, 0xc20), INTC_VECT(BBDMAC_4_7, 0xc40),
458 INTC_VECT(BBDMAC_4_7, 0xc60), INTC_VECT(BBDMAC_4_7, 0xc80),
459 INTC_VECT(BBDMAC_8_10, 0xca0), INTC_VECT(BBDMAC_8_10, 0xcc0),
460 INTC_VECT(BBDMAC_8_10, 0xce0), INTC_VECT(BBDMAC_11_14, 0xd00),
461 INTC_VECT(BBDMAC_11_14, 0xd20), INTC_VECT(BBDMAC_11_14, 0xd40),
462 INTC_VECT(BBDMAC_11_14, 0xd60), INTC_VECT(BBDMAC_15_18, 0xd80),
463 INTC_VECT(BBDMAC_15_18, 0xda0), INTC_VECT(BBDMAC_15_18, 0xdc0),
464 INTC_VECT(BBDMAC_15_18, 0xde0), INTC_VECT(BBDMAC_19_22, 0xe00),
465 INTC_VECT(BBDMAC_19_22, 0xe20), INTC_VECT(BBDMAC_19_22, 0xe40),
466 INTC_VECT(BBDMAC_19_22, 0xe60), INTC_VECT(BBDMAC_23_26, 0xe80),
467 INTC_VECT(BBDMAC_23_26, 0xea0), INTC_VECT(BBDMAC_23_26, 0xec0),
468 INTC_VECT(BBDMAC_23_26, 0xee0), INTC_VECT(BBDMAC_27, 0xf00),
469 INTC_VECT(BBDMAC_28, 0xf20), INTC_VECT(BBDMAC_29, 0xf40),
470 INTC_VECT(BBDMAC_30, 0xf60), INTC_VECT(BBDMAC_31, 0xf80),
471};
472
473static struct intc_group groups[] __initdata = {
474 INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
475 TMU5_TICPI, TMU6, TMU7, TMU8),
476 INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2),
477 INTC_GROUP(I2S, I2S0, I2S1, I2S2, I2S3),
478 INTC_GROUP(SRC, SRC_RX, SRC_TX, SRC_SPDIF),
479 INTC_GROUP(GFX3D, GFX3D_MBX, GFX3D_DMAC),
480 INTC_GROUP(SPI, SPI0, SPI1),
481 INTC_GROUP(SCIF, SCIF089, SCIF1234, SCIF567),
482 INTC_GROUP(BBDMAC,
483 BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
484 BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
485 BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31),
486};
487
488static struct intc_mask_reg mask_registers[] __initdata = {
489 { 0xffe00040, 0xffe00044, 32, /* INT2MSKR / INT2MSKCR */
490 { 0, BBDMAC, ADC, SCIF, SPI, EXBUS_ATA, GFX3D, GFX2D,
491 GPS, CAN, ATAPI, USB, YUV, REMOTE, VIDEO_IN, DU, SRC, I2S,
492 DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },
493};
494
495static struct intc_prio_reg prio_registers[] __initdata = {
496 { 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO, TMU0, 0, HAC } },
497 { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } },
498 { 0xffe00008, 0, 32, 8, /* INT2PRI2 */ { DMAC, I2S, SRC, DU } },
499 { 0xffe0000c, 0, 32, 8, /* INT2PRI3 */ { VIDEO_IN, REMOTE, YUV, USB } },
500 { 0xffe00010, 0, 32, 8, /* INT2PRI4 */ { ATAPI, CAN, GPS, GFX2D } },
501 { 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D, EXBUS_ATA, SPI } },
502 { 0xffe00018, 0, 32, 8, /* INT2PRI6 */ { SCIF1234, SCIF567, SCIF089 } },
503 { 0xffe0001c, 0, 32, 8, /* INT2PRI7 */ { ADC, 0, 0, BBDMAC_0_3 } },
504 { 0xffe00020, 0, 32, 8, /* INT2PRI8 */
505 { BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, BBDMAC_15_18 } },
506 { 0xffe00024, 0, 32, 8, /* INT2PRI9 */
507 { BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, BBDMAC_28 } },
508 { 0xffe00028, 0, 32, 8, /* INT2PRI10 */
509 { BBDMAC_29, BBDMAC_30, BBDMAC_31 } },
510 { 0xffe0002c, 0, 32, 8, /* INT2PRI11 */
511 { TMU1, TMU2, TMU2_TICPI, TMU3 } },
512 { 0xffe00030, 0, 32, 8, /* INT2PRI12 */
513 { TMU4, TMU5, TMU5_TICPI, TMU6 } },
514 { 0xffe00034, 0, 32, 8, /* INT2PRI13 */
515 { TMU7, TMU8 } },
516};
517
518static DECLARE_INTC_DESC(intc_desc, "sh7770", vectors, groups,
519 mask_registers, prio_registers, NULL);
520
521/* Support for external interrupt pins in IRQ mode */
522static struct intc_vect irq_vectors[] __initdata = {
523 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
524 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
525 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
526};
527
528static struct intc_mask_reg irq_mask_registers[] __initdata = {
529 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
530 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, } },
531};
532
533static struct intc_prio_reg irq_prio_registers[] __initdata = {
534 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
535 IRQ4, IRQ5, } },
536};
537
538static struct intc_sense_reg irq_sense_registers[] __initdata = {
539 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
540 IRQ4, IRQ5, } },
541};
542
543static DECLARE_INTC_DESC(intc_irq_desc, "sh7770-irq", irq_vectors,
544 NULL, irq_mask_registers, irq_prio_registers,
545 irq_sense_registers);
546
547/* External interrupt pins in IRL mode */
548static struct intc_vect irl_vectors[] __initdata = {
549 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
550 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
551 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
552 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
553 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
554 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
555 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
556 INTC_VECT(IRL_HHHL, 0x3c0),
557};
558
559static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
560 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
561 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
562 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
563 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
564 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
565};
566
567static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
568 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
569 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
570 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
571 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
572 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
573 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
574};
575
576static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
577 NULL, irl7654_mask_registers, NULL, NULL);
578
579static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
580 NULL, irl3210_mask_registers, NULL, NULL);
581
582#define INTC_ICR0 0xffd00000
583#define INTC_INTMSK0 0xffd00044
584#define INTC_INTMSK1 0xffd00048
585#define INTC_INTMSK2 0xffd40080
586#define INTC_INTMSKCLR1 0xffd00068
587#define INTC_INTMSKCLR2 0xffd40084
588
90void __init plat_irq_setup(void) 589void __init plat_irq_setup(void)
91{ 590{
591 /* disable IRQ7-0 */
592 ctrl_outl(0xff000000, INTC_INTMSK0);
593
594 /* disable IRL3-0 + IRL7-4 */
595 ctrl_outl(0xc0000000, INTC_INTMSK1);
596 ctrl_outl(0xfffefffe, INTC_INTMSK2);
597
598 /* select IRL mode for IRL3-0 + IRL7-4 */
599 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
600
601 /* disable holding function, ie enable "SH-4 Mode" */
602 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
603
604 register_intc_controller(&intc_desc);
605}
606
607void __init plat_irq_setup_pins(int mode)
608{
609 switch (mode) {
610 case IRQ_MODE_IRQ:
611 /* select IRQ mode for IRL3-0 + IRL7-4 */
612 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
613 register_intc_controller(&intc_irq_desc);
614 break;
615 case IRQ_MODE_IRL7654:
616 /* enable IRL7-4 but don't provide any masking */
617 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
618 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
619 break;
620 case IRQ_MODE_IRL3210:
621 /* enable IRL0-3 but don't provide any masking */
622 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
623 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
624 break;
625 case IRQ_MODE_IRL7654_MASK:
626 /* enable IRL7-4 and mask using cpu intc controller */
627 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
628 register_intc_controller(&intc_irl7654_desc);
629 break;
630 case IRQ_MODE_IRL3210_MASK:
631 /* enable IRL0-3 and mask using cpu intc controller */
632 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
633 register_intc_controller(&intc_irl3210_desc);
634 break;
635 default:
636 BUG();
637 }
92} 638}
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 6f7227cd65bf..715e05b431e5 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -12,6 +12,189 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_timer.h>
16
17static struct sh_timer_config tmu0_platform_data = {
18 .name = "TMU0",
19 .channel_offset = 0x04,
20 .timer_bit = 0,
21 .clk = "peripheral_clk",
22 .clockevent_rating = 200,
23};
24
25static struct resource tmu0_resources[] = {
26 [0] = {
27 .name = "TMU0",
28 .start = 0xffd80008,
29 .end = 0xffd80013,
30 .flags = IORESOURCE_MEM,
31 },
32 [1] = {
33 .start = 28,
34 .flags = IORESOURCE_IRQ,
35 },
36};
37
38static struct platform_device tmu0_device = {
39 .name = "sh_tmu",
40 .id = 0,
41 .dev = {
42 .platform_data = &tmu0_platform_data,
43 },
44 .resource = tmu0_resources,
45 .num_resources = ARRAY_SIZE(tmu0_resources),
46};
47
48static struct sh_timer_config tmu1_platform_data = {
49 .name = "TMU1",
50 .channel_offset = 0x10,
51 .timer_bit = 1,
52 .clk = "peripheral_clk",
53 .clocksource_rating = 200,
54};
55
56static struct resource tmu1_resources[] = {
57 [0] = {
58 .name = "TMU1",
59 .start = 0xffd80014,
60 .end = 0xffd8001f,
61 .flags = IORESOURCE_MEM,
62 },
63 [1] = {
64 .start = 29,
65 .flags = IORESOURCE_IRQ,
66 },
67};
68
69static struct platform_device tmu1_device = {
70 .name = "sh_tmu",
71 .id = 1,
72 .dev = {
73 .platform_data = &tmu1_platform_data,
74 },
75 .resource = tmu1_resources,
76 .num_resources = ARRAY_SIZE(tmu1_resources),
77};
78
79static struct sh_timer_config tmu2_platform_data = {
80 .name = "TMU2",
81 .channel_offset = 0x1c,
82 .timer_bit = 2,
83 .clk = "peripheral_clk",
84};
85
86static struct resource tmu2_resources[] = {
87 [0] = {
88 .name = "TMU2",
89 .start = 0xffd80020,
90 .end = 0xffd8002f,
91 .flags = IORESOURCE_MEM,
92 },
93 [1] = {
94 .start = 30,
95 .flags = IORESOURCE_IRQ,
96 },
97};
98
99static struct platform_device tmu2_device = {
100 .name = "sh_tmu",
101 .id = 2,
102 .dev = {
103 .platform_data = &tmu2_platform_data,
104 },
105 .resource = tmu2_resources,
106 .num_resources = ARRAY_SIZE(tmu2_resources),
107};
108
109static struct sh_timer_config tmu3_platform_data = {
110 .name = "TMU3",
111 .channel_offset = 0x04,
112 .timer_bit = 0,
113 .clk = "peripheral_clk",
114};
115
116static struct resource tmu3_resources[] = {
117 [0] = {
118 .name = "TMU3",
119 .start = 0xffdc0008,
120 .end = 0xffdc0013,
121 .flags = IORESOURCE_MEM,
122 },
123 [1] = {
124 .start = 96,
125 .flags = IORESOURCE_IRQ,
126 },
127};
128
129static struct platform_device tmu3_device = {
130 .name = "sh_tmu",
131 .id = 3,
132 .dev = {
133 .platform_data = &tmu3_platform_data,
134 },
135 .resource = tmu3_resources,
136 .num_resources = ARRAY_SIZE(tmu3_resources),
137};
138
139static struct sh_timer_config tmu4_platform_data = {
140 .name = "TMU4",
141 .channel_offset = 0x10,
142 .timer_bit = 1,
143 .clk = "peripheral_clk",
144};
145
146static struct resource tmu4_resources[] = {
147 [0] = {
148 .name = "TMU4",
149 .start = 0xffdc0014,
150 .end = 0xffdc001f,
151 .flags = IORESOURCE_MEM,
152 },
153 [1] = {
154 .start = 97,
155 .flags = IORESOURCE_IRQ,
156 },
157};
158
159static struct platform_device tmu4_device = {
160 .name = "sh_tmu",
161 .id = 4,
162 .dev = {
163 .platform_data = &tmu4_platform_data,
164 },
165 .resource = tmu4_resources,
166 .num_resources = ARRAY_SIZE(tmu4_resources),
167};
168
169static struct sh_timer_config tmu5_platform_data = {
170 .name = "TMU5",
171 .channel_offset = 0x1c,
172 .timer_bit = 2,
173 .clk = "peripheral_clk",
174};
175
176static struct resource tmu5_resources[] = {
177 [0] = {
178 .name = "TMU5",
179 .start = 0xffdc0020,
180 .end = 0xffdc002b,
181 .flags = IORESOURCE_MEM,
182 },
183 [1] = {
184 .start = 98,
185 .flags = IORESOURCE_IRQ,
186 },
187};
188
189static struct platform_device tmu5_device = {
190 .name = "sh_tmu",
191 .id = 5,
192 .dev = {
193 .platform_data = &tmu5_platform_data,
194 },
195 .resource = tmu5_resources,
196 .num_resources = ARRAY_SIZE(tmu5_resources),
197};
15 198
16static struct resource rtc_resources[] = { 199static struct resource rtc_resources[] = {
17 [0] = { 200 [0] = {
@@ -58,6 +241,12 @@ static struct platform_device sci_device = {
58}; 241};
59 242
60static struct platform_device *sh7780_devices[] __initdata = { 243static struct platform_device *sh7780_devices[] __initdata = {
244 &tmu0_device,
245 &tmu1_device,
246 &tmu2_device,
247 &tmu3_device,
248 &tmu4_device,
249 &tmu5_device,
61 &rtc_device, 250 &rtc_device,
62 &sci_device, 251 &sci_device,
63}; 252};
@@ -69,6 +258,21 @@ static int __init sh7780_devices_setup(void)
69} 258}
70__initcall(sh7780_devices_setup); 259__initcall(sh7780_devices_setup);
71 260
261static struct platform_device *sh7780_early_devices[] __initdata = {
262 &tmu0_device,
263 &tmu1_device,
264 &tmu2_device,
265 &tmu3_device,
266 &tmu4_device,
267 &tmu5_device,
268};
269
270void __init plat_early_device_setup(void)
271{
272 early_platform_add_devices(sh7780_early_devices,
273 ARRAY_SIZE(sh7780_early_devices));
274}
275
72enum { 276enum {
73 UNUSED = 0, 277 UNUSED = 0,
74 278
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index d80802a49dbd..af561402570b 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -13,39 +13,228 @@
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/mm.h> 15#include <linux/mm.h>
16#include <linux/sh_timer.h>
16#include <asm/mmzone.h> 17#include <asm/mmzone.h>
17 18
19static struct sh_timer_config tmu0_platform_data = {
20 .name = "TMU0",
21 .channel_offset = 0x04,
22 .timer_bit = 0,
23 .clk = "tmu012_fck",
24 .clockevent_rating = 200,
25};
26
27static struct resource tmu0_resources[] = {
28 [0] = {
29 .name = "TMU0",
30 .start = 0xffd80008,
31 .end = 0xffd80013,
32 .flags = IORESOURCE_MEM,
33 },
34 [1] = {
35 .start = 28,
36 .flags = IORESOURCE_IRQ,
37 },
38};
39
40static struct platform_device tmu0_device = {
41 .name = "sh_tmu",
42 .id = 0,
43 .dev = {
44 .platform_data = &tmu0_platform_data,
45 },
46 .resource = tmu0_resources,
47 .num_resources = ARRAY_SIZE(tmu0_resources),
48};
49
50static struct sh_timer_config tmu1_platform_data = {
51 .name = "TMU1",
52 .channel_offset = 0x10,
53 .timer_bit = 1,
54 .clk = "tmu012_fck",
55 .clocksource_rating = 200,
56};
57
58static struct resource tmu1_resources[] = {
59 [0] = {
60 .name = "TMU1",
61 .start = 0xffd80014,
62 .end = 0xffd8001f,
63 .flags = IORESOURCE_MEM,
64 },
65 [1] = {
66 .start = 29,
67 .flags = IORESOURCE_IRQ,
68 },
69};
70
71static struct platform_device tmu1_device = {
72 .name = "sh_tmu",
73 .id = 1,
74 .dev = {
75 .platform_data = &tmu1_platform_data,
76 },
77 .resource = tmu1_resources,
78 .num_resources = ARRAY_SIZE(tmu1_resources),
79};
80
81static struct sh_timer_config tmu2_platform_data = {
82 .name = "TMU2",
83 .channel_offset = 0x1c,
84 .timer_bit = 2,
85 .clk = "tmu012_fck",
86};
87
88static struct resource tmu2_resources[] = {
89 [0] = {
90 .name = "TMU2",
91 .start = 0xffd80020,
92 .end = 0xffd8002f,
93 .flags = IORESOURCE_MEM,
94 },
95 [1] = {
96 .start = 30,
97 .flags = IORESOURCE_IRQ,
98 },
99};
100
101static struct platform_device tmu2_device = {
102 .name = "sh_tmu",
103 .id = 2,
104 .dev = {
105 .platform_data = &tmu2_platform_data,
106 },
107 .resource = tmu2_resources,
108 .num_resources = ARRAY_SIZE(tmu2_resources),
109};
110
111static struct sh_timer_config tmu3_platform_data = {
112 .name = "TMU3",
113 .channel_offset = 0x04,
114 .timer_bit = 0,
115 .clk = "tmu345_fck",
116};
117
118static struct resource tmu3_resources[] = {
119 [0] = {
120 .name = "TMU3",
121 .start = 0xffdc0008,
122 .end = 0xffdc0013,
123 .flags = IORESOURCE_MEM,
124 },
125 [1] = {
126 .start = 96,
127 .flags = IORESOURCE_IRQ,
128 },
129};
130
131static struct platform_device tmu3_device = {
132 .name = "sh_tmu",
133 .id = 3,
134 .dev = {
135 .platform_data = &tmu3_platform_data,
136 },
137 .resource = tmu3_resources,
138 .num_resources = ARRAY_SIZE(tmu3_resources),
139};
140
141static struct sh_timer_config tmu4_platform_data = {
142 .name = "TMU4",
143 .channel_offset = 0x10,
144 .timer_bit = 1,
145 .clk = "tmu345_fck",
146};
147
148static struct resource tmu4_resources[] = {
149 [0] = {
150 .name = "TMU4",
151 .start = 0xffdc0014,
152 .end = 0xffdc001f,
153 .flags = IORESOURCE_MEM,
154 },
155 [1] = {
156 .start = 97,
157 .flags = IORESOURCE_IRQ,
158 },
159};
160
161static struct platform_device tmu4_device = {
162 .name = "sh_tmu",
163 .id = 4,
164 .dev = {
165 .platform_data = &tmu4_platform_data,
166 },
167 .resource = tmu4_resources,
168 .num_resources = ARRAY_SIZE(tmu4_resources),
169};
170
171static struct sh_timer_config tmu5_platform_data = {
172 .name = "TMU5",
173 .channel_offset = 0x1c,
174 .timer_bit = 2,
175 .clk = "tmu345_fck",
176};
177
178static struct resource tmu5_resources[] = {
179 [0] = {
180 .name = "TMU5",
181 .start = 0xffdc0020,
182 .end = 0xffdc002b,
183 .flags = IORESOURCE_MEM,
184 },
185 [1] = {
186 .start = 98,
187 .flags = IORESOURCE_IRQ,
188 },
189};
190
191static struct platform_device tmu5_device = {
192 .name = "sh_tmu",
193 .id = 5,
194 .dev = {
195 .platform_data = &tmu5_platform_data,
196 },
197 .resource = tmu5_resources,
198 .num_resources = ARRAY_SIZE(tmu5_resources),
199};
200
18static struct plat_sci_port sci_platform_data[] = { 201static struct plat_sci_port sci_platform_data[] = {
19 { 202 {
20 .mapbase = 0xffea0000, 203 .mapbase = 0xffea0000,
21 .flags = UPF_BOOT_AUTOCONF, 204 .flags = UPF_BOOT_AUTOCONF,
22 .type = PORT_SCIF, 205 .type = PORT_SCIF,
23 .irqs = { 40, 40, 40, 40 }, 206 .irqs = { 40, 40, 40, 40 },
207 .clk = "scif_fck",
24 }, { 208 }, {
25 .mapbase = 0xffeb0000, 209 .mapbase = 0xffeb0000,
26 .flags = UPF_BOOT_AUTOCONF, 210 .flags = UPF_BOOT_AUTOCONF,
27 .type = PORT_SCIF, 211 .type = PORT_SCIF,
28 .irqs = { 44, 44, 44, 44 }, 212 .irqs = { 44, 44, 44, 44 },
213 .clk = "scif_fck",
29 }, { 214 }, {
30 .mapbase = 0xffec0000, 215 .mapbase = 0xffec0000,
31 .flags = UPF_BOOT_AUTOCONF, 216 .flags = UPF_BOOT_AUTOCONF,
32 .type = PORT_SCIF, 217 .type = PORT_SCIF,
33 .irqs = { 60, 60, 60, 60 }, 218 .irqs = { 60, 60, 60, 60 },
219 .clk = "scif_fck",
34 }, { 220 }, {
35 .mapbase = 0xffed0000, 221 .mapbase = 0xffed0000,
36 .flags = UPF_BOOT_AUTOCONF, 222 .flags = UPF_BOOT_AUTOCONF,
37 .type = PORT_SCIF, 223 .type = PORT_SCIF,
38 .irqs = { 61, 61, 61, 61 }, 224 .irqs = { 61, 61, 61, 61 },
225 .clk = "scif_fck",
39 }, { 226 }, {
40 .mapbase = 0xffee0000, 227 .mapbase = 0xffee0000,
41 .flags = UPF_BOOT_AUTOCONF, 228 .flags = UPF_BOOT_AUTOCONF,
42 .type = PORT_SCIF, 229 .type = PORT_SCIF,
43 .irqs = { 62, 62, 62, 62 }, 230 .irqs = { 62, 62, 62, 62 },
231 .clk = "scif_fck",
44 }, { 232 }, {
45 .mapbase = 0xffef0000, 233 .mapbase = 0xffef0000,
46 .flags = UPF_BOOT_AUTOCONF, 234 .flags = UPF_BOOT_AUTOCONF,
47 .type = PORT_SCIF, 235 .type = PORT_SCIF,
48 .irqs = { 63, 63, 63, 63 }, 236 .irqs = { 63, 63, 63, 63 },
237 .clk = "scif_fck",
49 }, { 238 }, {
50 .flags = 0, 239 .flags = 0,
51 } 240 }
@@ -60,6 +249,12 @@ static struct platform_device sci_device = {
60}; 249};
61 250
62static struct platform_device *sh7785_devices[] __initdata = { 251static struct platform_device *sh7785_devices[] __initdata = {
252 &tmu0_device,
253 &tmu1_device,
254 &tmu2_device,
255 &tmu3_device,
256 &tmu4_device,
257 &tmu5_device,
63 &sci_device, 258 &sci_device,
64}; 259};
65 260
@@ -70,6 +265,21 @@ static int __init sh7785_devices_setup(void)
70} 265}
71__initcall(sh7785_devices_setup); 266__initcall(sh7785_devices_setup);
72 267
268static struct platform_device *sh7785_early_devices[] __initdata = {
269 &tmu0_device,
270 &tmu1_device,
271 &tmu2_device,
272 &tmu3_device,
273 &tmu4_device,
274 &tmu5_device,
275};
276
277void __init plat_early_device_setup(void)
278{
279 early_platform_add_devices(sh7785_early_devices,
280 ARRAY_SIZE(sh7785_early_devices));
281}
282
73enum { 283enum {
74 UNUSED = 0, 284 UNUSED = 0,
75 285
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 90e8cfff55fd..93e0d2c017e8 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -3,6 +3,7 @@
3 * 3 *
4 * Copyright (C) 2009 Renesas Solutions Corp. 4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 * Paul Mundt <paul.mundt@renesas.com>
6 * 7 *
7 * Based on SH7785 Setup 8 * Based on SH7785 Setup
8 * 9 *
@@ -19,6 +20,7 @@
19#include <linux/io.h> 20#include <linux/io.h>
20#include <linux/mm.h> 21#include <linux/mm.h>
21#include <linux/dma-mapping.h> 22#include <linux/dma-mapping.h>
23#include <linux/sh_timer.h>
22#include <asm/mmzone.h> 24#include <asm/mmzone.h>
23 25
24static struct plat_sci_port sci_platform_data[] = { 26static struct plat_sci_port sci_platform_data[] = {
@@ -69,6 +71,368 @@ static struct platform_device sci_device = {
69 }, 71 },
70}; 72};
71 73
74static struct sh_timer_config tmu0_platform_data = {
75 .name = "TMU0",
76 .channel_offset = 0x04,
77 .timer_bit = 0,
78 .clk = "peripheral_clk",
79 .clockevent_rating = 200,
80};
81
82static struct resource tmu0_resources[] = {
83 [0] = {
84 .name = "TMU0",
85 .start = 0xffd80008,
86 .end = 0xffd80013,
87 .flags = IORESOURCE_MEM,
88 },
89 [1] = {
90 .start = 16,
91 .flags = IORESOURCE_IRQ,
92 },
93};
94
95static struct platform_device tmu0_device = {
96 .name = "sh_tmu",
97 .id = 0,
98 .dev = {
99 .platform_data = &tmu0_platform_data,
100 },
101 .resource = tmu0_resources,
102 .num_resources = ARRAY_SIZE(tmu0_resources),
103};
104
105static struct sh_timer_config tmu1_platform_data = {
106 .name = "TMU1",
107 .channel_offset = 0x10,
108 .timer_bit = 1,
109 .clk = "peripheral_clk",
110 .clocksource_rating = 200,
111};
112
113static struct resource tmu1_resources[] = {
114 [0] = {
115 .name = "TMU1",
116 .start = 0xffd80014,
117 .end = 0xffd8001f,
118 .flags = IORESOURCE_MEM,
119 },
120 [1] = {
121 .start = 17,
122 .flags = IORESOURCE_IRQ,
123 },
124};
125
126static struct platform_device tmu1_device = {
127 .name = "sh_tmu",
128 .id = 1,
129 .dev = {
130 .platform_data = &tmu1_platform_data,
131 },
132 .resource = tmu1_resources,
133 .num_resources = ARRAY_SIZE(tmu1_resources),
134};
135
136static struct sh_timer_config tmu2_platform_data = {
137 .name = "TMU2",
138 .channel_offset = 0x1c,
139 .timer_bit = 2,
140 .clk = "peripheral_clk",
141};
142
143static struct resource tmu2_resources[] = {
144 [0] = {
145 .name = "TMU2",
146 .start = 0xffd80020,
147 .end = 0xffd8002f,
148 .flags = IORESOURCE_MEM,
149 },
150 [1] = {
151 .start = 18,
152 .flags = IORESOURCE_IRQ,
153 },
154};
155
156static struct platform_device tmu2_device = {
157 .name = "sh_tmu",
158 .id = 2,
159 .dev = {
160 .platform_data = &tmu2_platform_data,
161 },
162 .resource = tmu2_resources,
163 .num_resources = ARRAY_SIZE(tmu2_resources),
164};
165
166static struct sh_timer_config tmu3_platform_data = {
167 .name = "TMU3",
168 .channel_offset = 0x04,
169 .timer_bit = 0,
170 .clk = "peripheral_clk",
171};
172
173static struct resource tmu3_resources[] = {
174 [0] = {
175 .name = "TMU3",
176 .start = 0xffda0008,
177 .end = 0xffda0013,
178 .flags = IORESOURCE_MEM,
179 },
180 [1] = {
181 .start = 20,
182 .flags = IORESOURCE_IRQ,
183 },
184};
185
186static struct platform_device tmu3_device = {
187 .name = "sh_tmu",
188 .id = 3,
189 .dev = {
190 .platform_data = &tmu3_platform_data,
191 },
192 .resource = tmu3_resources,
193 .num_resources = ARRAY_SIZE(tmu3_resources),
194};
195
196static struct sh_timer_config tmu4_platform_data = {
197 .name = "TMU4",
198 .channel_offset = 0x10,
199 .timer_bit = 1,
200 .clk = "peripheral_clk",
201};
202
203static struct resource tmu4_resources[] = {
204 [0] = {
205 .name = "TMU4",
206 .start = 0xffda0014,
207 .end = 0xffda001f,
208 .flags = IORESOURCE_MEM,
209 },
210 [1] = {
211 .start = 21,
212 .flags = IORESOURCE_IRQ,
213 },
214};
215
216static struct platform_device tmu4_device = {
217 .name = "sh_tmu",
218 .id = 4,
219 .dev = {
220 .platform_data = &tmu4_platform_data,
221 },
222 .resource = tmu4_resources,
223 .num_resources = ARRAY_SIZE(tmu4_resources),
224};
225
226static struct sh_timer_config tmu5_platform_data = {
227 .name = "TMU5",
228 .channel_offset = 0x1c,
229 .timer_bit = 2,
230 .clk = "peripheral_clk",
231};
232
233static struct resource tmu5_resources[] = {
234 [0] = {
235 .name = "TMU5",
236 .start = 0xffda0020,
237 .end = 0xffda002b,
238 .flags = IORESOURCE_MEM,
239 },
240 [1] = {
241 .start = 22,
242 .flags = IORESOURCE_IRQ,
243 },
244};
245
246static struct platform_device tmu5_device = {
247 .name = "sh_tmu",
248 .id = 5,
249 .dev = {
250 .platform_data = &tmu5_platform_data,
251 },
252 .resource = tmu5_resources,
253 .num_resources = ARRAY_SIZE(tmu5_resources),
254};
255
256static struct sh_timer_config tmu6_platform_data = {
257 .name = "TMU6",
258 .channel_offset = 0x04,
259 .timer_bit = 0,
260 .clk = "peripheral_clk",
261};
262
263static struct resource tmu6_resources[] = {
264 [0] = {
265 .name = "TMU6",
266 .start = 0xffdc0008,
267 .end = 0xffdc0013,
268 .flags = IORESOURCE_MEM,
269 },
270 [1] = {
271 .start = 45,
272 .flags = IORESOURCE_IRQ,
273 },
274};
275
276static struct platform_device tmu6_device = {
277 .name = "sh_tmu",
278 .id = 6,
279 .dev = {
280 .platform_data = &tmu6_platform_data,
281 },
282 .resource = tmu6_resources,
283 .num_resources = ARRAY_SIZE(tmu6_resources),
284};
285
286static struct sh_timer_config tmu7_platform_data = {
287 .name = "TMU7",
288 .channel_offset = 0x10,
289 .timer_bit = 1,
290 .clk = "peripheral_clk",
291};
292
293static struct resource tmu7_resources[] = {
294 [0] = {
295 .name = "TMU7",
296 .start = 0xffdc0014,
297 .end = 0xffdc001f,
298 .flags = IORESOURCE_MEM,
299 },
300 [1] = {
301 .start = 45,
302 .flags = IORESOURCE_IRQ,
303 },
304};
305
306static struct platform_device tmu7_device = {
307 .name = "sh_tmu",
308 .id = 7,
309 .dev = {
310 .platform_data = &tmu7_platform_data,
311 },
312 .resource = tmu7_resources,
313 .num_resources = ARRAY_SIZE(tmu7_resources),
314};
315
316static struct sh_timer_config tmu8_platform_data = {
317 .name = "TMU8",
318 .channel_offset = 0x1c,
319 .timer_bit = 2,
320 .clk = "peripheral_clk",
321};
322
323static struct resource tmu8_resources[] = {
324 [0] = {
325 .name = "TMU8",
326 .start = 0xffdc0020,
327 .end = 0xffdc002b,
328 .flags = IORESOURCE_MEM,
329 },
330 [1] = {
331 .start = 45,
332 .flags = IORESOURCE_IRQ,
333 },
334};
335
336static struct platform_device tmu8_device = {
337 .name = "sh_tmu",
338 .id = 8,
339 .dev = {
340 .platform_data = &tmu8_platform_data,
341 },
342 .resource = tmu8_resources,
343 .num_resources = ARRAY_SIZE(tmu8_resources),
344};
345
346static struct sh_timer_config tmu9_platform_data = {
347 .name = "TMU9",
348 .channel_offset = 0x04,
349 .timer_bit = 0,
350 .clk = "peripheral_clk",
351};
352
353static struct resource tmu9_resources[] = {
354 [0] = {
355 .name = "TMU9",
356 .start = 0xffde0008,
357 .end = 0xffde0013,
358 .flags = IORESOURCE_MEM,
359 },
360 [1] = {
361 .start = 46,
362 .flags = IORESOURCE_IRQ,
363 },
364};
365
366static struct platform_device tmu9_device = {
367 .name = "sh_tmu",
368 .id = 9,
369 .dev = {
370 .platform_data = &tmu9_platform_data,
371 },
372 .resource = tmu9_resources,
373 .num_resources = ARRAY_SIZE(tmu9_resources),
374};
375
376static struct sh_timer_config tmu10_platform_data = {
377 .name = "TMU10",
378 .channel_offset = 0x10,
379 .timer_bit = 1,
380 .clk = "peripheral_clk",
381};
382
383static struct resource tmu10_resources[] = {
384 [0] = {
385 .name = "TMU10",
386 .start = 0xffde0014,
387 .end = 0xffde001f,
388 .flags = IORESOURCE_MEM,
389 },
390 [1] = {
391 .start = 46,
392 .flags = IORESOURCE_IRQ,
393 },
394};
395
396static struct platform_device tmu10_device = {
397 .name = "sh_tmu",
398 .id = 10,
399 .dev = {
400 .platform_data = &tmu10_platform_data,
401 },
402 .resource = tmu10_resources,
403 .num_resources = ARRAY_SIZE(tmu10_resources),
404};
405
406static struct sh_timer_config tmu11_platform_data = {
407 .name = "TMU11",
408 .channel_offset = 0x1c,
409 .timer_bit = 2,
410 .clk = "peripheral_clk",
411};
412
413static struct resource tmu11_resources[] = {
414 [0] = {
415 .name = "TMU11",
416 .start = 0xffde0020,
417 .end = 0xffde002b,
418 .flags = IORESOURCE_MEM,
419 },
420 [1] = {
421 .start = 46,
422 .flags = IORESOURCE_IRQ,
423 },
424};
425
426static struct platform_device tmu11_device = {
427 .name = "sh_tmu",
428 .id = 11,
429 .dev = {
430 .platform_data = &tmu11_platform_data,
431 },
432 .resource = tmu11_resources,
433 .num_resources = ARRAY_SIZE(tmu11_resources),
434};
435
72static struct resource usb_ohci_resources[] = { 436static struct resource usb_ohci_resources[] = {
73 [0] = { 437 [0] = {
74 .start = 0xffe70400, 438 .start = 0xffe70400,
@@ -94,6 +458,21 @@ static struct platform_device usb_ohci_device = {
94 .resource = usb_ohci_resources, 458 .resource = usb_ohci_resources,
95}; 459};
96 460
461static struct platform_device *sh7786_early_devices[] __initdata = {
462 &tmu0_device,
463 &tmu1_device,
464 &tmu2_device,
465 &tmu3_device,
466 &tmu4_device,
467 &tmu5_device,
468 &tmu6_device,
469 &tmu7_device,
470 &tmu8_device,
471 &tmu9_device,
472 &tmu10_device,
473 &tmu11_device,
474};
475
97static struct platform_device *sh7786_devices[] __initdata = { 476static struct platform_device *sh7786_devices[] __initdata = {
98 &sci_device, 477 &sci_device,
99 &usb_ohci_device, 478 &usb_ohci_device,
@@ -156,12 +535,26 @@ static void __init sh7786_usb_setup(void)
156 535
157static int __init sh7786_devices_setup(void) 536static int __init sh7786_devices_setup(void)
158{ 537{
538 int ret;
539
159 sh7786_usb_setup(); 540 sh7786_usb_setup();
541
542 ret = platform_add_devices(sh7786_early_devices,
543 ARRAY_SIZE(sh7786_early_devices));
544 if (unlikely(ret != 0))
545 return ret;
546
160 return platform_add_devices(sh7786_devices, 547 return platform_add_devices(sh7786_devices,
161 ARRAY_SIZE(sh7786_devices)); 548 ARRAY_SIZE(sh7786_devices));
162} 549}
163device_initcall(sh7786_devices_setup); 550device_initcall(sh7786_devices_setup);
164 551
552void __init plat_early_device_setup(void)
553{
554 early_platform_add_devices(sh7786_early_devices,
555 ARRAY_SIZE(sh7786_early_devices));
556}
557
165enum { 558enum {
166 UNUSED = 0, 559 UNUSED = 0,
167 560
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
index bd35f32534b9..53c65fd9ccef 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH-X3 Setup 2 * SH-X3 Prototype Setup
3 * 3 *
4 * Copyright (C) 2007 Paul Mundt 4 * Copyright (C) 2007 - 2009 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -12,6 +12,7 @@
12#include <linux/serial.h> 12#include <linux/serial.h>
13#include <linux/serial_sci.h> 13#include <linux/serial_sci.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/sh_timer.h>
15#include <asm/mmzone.h> 16#include <asm/mmzone.h>
16 17
17static struct plat_sci_port sci_platform_data[] = { 18static struct plat_sci_port sci_platform_data[] = {
@@ -48,17 +49,221 @@ static struct platform_device sci_device = {
48 }, 49 },
49}; 50};
50 51
52static struct sh_timer_config tmu0_platform_data = {
53 .name = "TMU0",
54 .channel_offset = 0x04,
55 .timer_bit = 0,
56 .clk = "peripheral_clk",
57 .clockevent_rating = 200,
58};
59
60static struct resource tmu0_resources[] = {
61 [0] = {
62 .name = "TMU0",
63 .start = 0xffc10008,
64 .end = 0xffc10013,
65 .flags = IORESOURCE_MEM,
66 },
67 [1] = {
68 .start = 16,
69 .flags = IORESOURCE_IRQ,
70 },
71};
72
73static struct platform_device tmu0_device = {
74 .name = "sh_tmu",
75 .id = 0,
76 .dev = {
77 .platform_data = &tmu0_platform_data,
78 },
79 .resource = tmu0_resources,
80 .num_resources = ARRAY_SIZE(tmu0_resources),
81};
82
83static struct sh_timer_config tmu1_platform_data = {
84 .name = "TMU1",
85 .channel_offset = 0x10,
86 .timer_bit = 1,
87 .clk = "peripheral_clk",
88 .clocksource_rating = 200,
89};
90
91static struct resource tmu1_resources[] = {
92 [0] = {
93 .name = "TMU1",
94 .start = 0xffc10014,
95 .end = 0xffc1001f,
96 .flags = IORESOURCE_MEM,
97 },
98 [1] = {
99 .start = 17,
100 .flags = IORESOURCE_IRQ,
101 },
102};
103
104static struct platform_device tmu1_device = {
105 .name = "sh_tmu",
106 .id = 1,
107 .dev = {
108 .platform_data = &tmu1_platform_data,
109 },
110 .resource = tmu1_resources,
111 .num_resources = ARRAY_SIZE(tmu1_resources),
112};
113
114static struct sh_timer_config tmu2_platform_data = {
115 .name = "TMU2",
116 .channel_offset = 0x1c,
117 .timer_bit = 2,
118 .clk = "peripheral_clk",
119};
120
121static struct resource tmu2_resources[] = {
122 [0] = {
123 .name = "TMU2",
124 .start = 0xffc10020,
125 .end = 0xffc1002f,
126 .flags = IORESOURCE_MEM,
127 },
128 [1] = {
129 .start = 18,
130 .flags = IORESOURCE_IRQ,
131 },
132};
133
134static struct platform_device tmu2_device = {
135 .name = "sh_tmu",
136 .id = 2,
137 .dev = {
138 .platform_data = &tmu2_platform_data,
139 },
140 .resource = tmu2_resources,
141 .num_resources = ARRAY_SIZE(tmu2_resources),
142};
143
144static struct sh_timer_config tmu3_platform_data = {
145 .name = "TMU3",
146 .channel_offset = 0x04,
147 .timer_bit = 0,
148 .clk = "peripheral_clk",
149};
150
151static struct resource tmu3_resources[] = {
152 [0] = {
153 .name = "TMU3",
154 .start = 0xffc20008,
155 .end = 0xffc20013,
156 .flags = IORESOURCE_MEM,
157 },
158 [1] = {
159 .start = 19,
160 .flags = IORESOURCE_IRQ,
161 },
162};
163
164static struct platform_device tmu3_device = {
165 .name = "sh_tmu",
166 .id = 3,
167 .dev = {
168 .platform_data = &tmu3_platform_data,
169 },
170 .resource = tmu3_resources,
171 .num_resources = ARRAY_SIZE(tmu3_resources),
172};
173
174static struct sh_timer_config tmu4_platform_data = {
175 .name = "TMU4",
176 .channel_offset = 0x10,
177 .timer_bit = 1,
178 .clk = "peripheral_clk",
179};
180
181static struct resource tmu4_resources[] = {
182 [0] = {
183 .name = "TMU4",
184 .start = 0xffc20014,
185 .end = 0xffc2001f,
186 .flags = IORESOURCE_MEM,
187 },
188 [1] = {
189 .start = 20,
190 .flags = IORESOURCE_IRQ,
191 },
192};
193
194static struct platform_device tmu4_device = {
195 .name = "sh_tmu",
196 .id = 4,
197 .dev = {
198 .platform_data = &tmu4_platform_data,
199 },
200 .resource = tmu4_resources,
201 .num_resources = ARRAY_SIZE(tmu4_resources),
202};
203
204static struct sh_timer_config tmu5_platform_data = {
205 .name = "TMU5",
206 .channel_offset = 0x1c,
207 .timer_bit = 2,
208 .clk = "peripheral_clk",
209};
210
211static struct resource tmu5_resources[] = {
212 [0] = {
213 .name = "TMU5",
214 .start = 0xffc20020,
215 .end = 0xffc2002b,
216 .flags = IORESOURCE_MEM,
217 },
218 [1] = {
219 .start = 21,
220 .flags = IORESOURCE_IRQ,
221 },
222};
223
224static struct platform_device tmu5_device = {
225 .name = "sh_tmu",
226 .id = 5,
227 .dev = {
228 .platform_data = &tmu5_platform_data,
229 },
230 .resource = tmu5_resources,
231 .num_resources = ARRAY_SIZE(tmu5_resources),
232};
233
234static struct platform_device *shx3_early_devices[] __initdata = {
235 &tmu0_device,
236 &tmu1_device,
237 &tmu2_device,
238 &tmu3_device,
239 &tmu4_device,
240 &tmu5_device,
241};
242
51static struct platform_device *shx3_devices[] __initdata = { 243static struct platform_device *shx3_devices[] __initdata = {
52 &sci_device, 244 &sci_device,
53}; 245};
54 246
55static int __init shx3_devices_setup(void) 247static int __init shx3_devices_setup(void)
56{ 248{
249 int ret;
250
251 ret = platform_add_devices(shx3_early_devices,
252 ARRAY_SIZE(shx3_early_devices));
253 if (unlikely(ret != 0))
254 return ret;
255
57 return platform_add_devices(shx3_devices, 256 return platform_add_devices(shx3_devices,
58 ARRAY_SIZE(shx3_devices)); 257 ARRAY_SIZE(shx3_devices));
59} 258}
60__initcall(shx3_devices_setup); 259__initcall(shx3_devices_setup);
61 260
261void __init plat_early_device_setup(void)
262{
263 early_platform_add_devices(shx3_early_devices,
264 ARRAY_SIZE(shx3_early_devices));
265}
266
62enum { 267enum {
63 UNUSED = 0, 268 UNUSED = 0,
64 269
diff --git a/arch/sh/kernel/cpu/sh5/Makefile b/arch/sh/kernel/cpu/sh5/Makefile
index ce4602ea23a8..a184a31e686e 100644
--- a/arch/sh/kernel/cpu/sh5/Makefile
+++ b/arch/sh/kernel/cpu/sh5/Makefile
@@ -6,6 +6,9 @@ obj-y := entry.o probe.o switchto.o
6obj-$(CONFIG_SH_FPU) += fpu.o 6obj-$(CONFIG_SH_FPU) += fpu.o
7obj-$(CONFIG_KALLSYMS) += unwind.o 7obj-$(CONFIG_KALLSYMS) += unwind.o
8 8
9# CPU subtype setup
10obj-$(CONFIG_CPU_SH5) += setup-sh5.o
11
9# Primary on-chip clocks (common) 12# Primary on-chip clocks (common)
10clock-$(CONFIG_CPU_SH5) := clock-sh5.o 13clock-$(CONFIG_CPU_SH5) := clock-sh5.o
11 14
diff --git a/arch/sh/kernel/cpu/sh5/clock-sh5.c b/arch/sh/kernel/cpu/sh5/clock-sh5.c
index 52c49248833a..7f864ebc51d3 100644
--- a/arch/sh/kernel/cpu/sh5/clock-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/clock-sh5.c
@@ -32,30 +32,30 @@ static struct clk_ops sh5_master_clk_ops = {
32 .init = master_clk_init, 32 .init = master_clk_init,
33}; 33};
34 34
35static void module_clk_recalc(struct clk *clk) 35static unsigned long module_clk_recalc(struct clk *clk)
36{ 36{
37 int idx = (ctrl_inw(cprc_base) >> 12) & 0x0007; 37 int idx = (ctrl_inw(cprc_base) >> 12) & 0x0007;
38 clk->rate = clk->parent->rate / ifc_table[idx]; 38 return clk->parent->rate / ifc_table[idx];
39} 39}
40 40
41static struct clk_ops sh5_module_clk_ops = { 41static struct clk_ops sh5_module_clk_ops = {
42 .recalc = module_clk_recalc, 42 .recalc = module_clk_recalc,
43}; 43};
44 44
45static void bus_clk_recalc(struct clk *clk) 45static unsigned long bus_clk_recalc(struct clk *clk)
46{ 46{
47 int idx = (ctrl_inw(cprc_base) >> 3) & 0x0007; 47 int idx = (ctrl_inw(cprc_base) >> 3) & 0x0007;
48 clk->rate = clk->parent->rate / ifc_table[idx]; 48 return clk->parent->rate / ifc_table[idx];
49} 49}
50 50
51static struct clk_ops sh5_bus_clk_ops = { 51static struct clk_ops sh5_bus_clk_ops = {
52 .recalc = bus_clk_recalc, 52 .recalc = bus_clk_recalc,
53}; 53};
54 54
55static void cpu_clk_recalc(struct clk *clk) 55static unsigned long cpu_clk_recalc(struct clk *clk)
56{ 56{
57 int idx = (ctrl_inw(cprc_base) & 0x0007); 57 int idx = (ctrl_inw(cprc_base) & 0x0007);
58 clk->rate = clk->parent->rate / ifc_table[idx]; 58 return clk->parent->rate / ifc_table[idx];
59} 59}
60 60
61static struct clk_ops sh5_cpu_clk_ops = { 61static struct clk_ops sh5_cpu_clk_ops = {
@@ -71,7 +71,7 @@ static struct clk_ops *sh5_clk_ops[] = {
71 71
72void __init arch_init_clk_ops(struct clk_ops **ops, int idx) 72void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
73{ 73{
74 cprc_base = onchip_remap(CPRC_BASE, 1024, "CPRC"); 74 cprc_base = (unsigned long)ioremap_nocache(CPRC_BASE, 1024);
75 BUG_ON(!cprc_base); 75 BUG_ON(!cprc_base);
76 76
77 if (idx < ARRAY_SIZE(sh5_clk_ops)) 77 if (idx < ARRAY_SIZE(sh5_clk_ops))
diff --git a/arch/sh/kernel/cpu/sh5/entry.S b/arch/sh/kernel/cpu/sh5/entry.S
index 7e49cb812f8b..b0aacf675258 100644
--- a/arch/sh/kernel/cpu/sh5/entry.S
+++ b/arch/sh/kernel/cpu/sh5/entry.S
@@ -812,27 +812,6 @@ no_underflow:
812 ! exceptions 812 ! exceptions
813 add SP, ZERO, r14 813 add SP, ZERO, r14
814 814
815#ifdef CONFIG_POOR_MANS_STRACE
816 /* We've pushed all the registers now, so only r2-r4 hold anything
817 * useful. Move them into callee save registers */
818 or r2, ZERO, r28
819 or r3, ZERO, r29
820 or r4, ZERO, r30
821
822 /* Preserve r2 as the event code */
823 movi evt_debug, r3
824 ori r3, 1, r3
825 ptabs r3, tr0
826
827 or SP, ZERO, r6
828 getcon TRA, r5
829 blink tr0, LINK
830
831 or r28, ZERO, r2
832 or r29, ZERO, r3
833 or r30, ZERO, r4
834#endif
835
836 /* For syscall and debug race condition, get TRA now */ 815 /* For syscall and debug race condition, get TRA now */
837 getcon TRA, r5 816 getcon TRA, r5
838 817
@@ -887,11 +866,6 @@ no_underflow:
887 */ 866 */
888 .global ret_from_irq 867 .global ret_from_irq
889ret_from_irq: 868ret_from_irq:
890#ifdef CONFIG_POOR_MANS_STRACE
891 pta evt_debug_ret_from_irq, tr0
892 ori SP, 0, r2
893 blink tr0, LINK
894#endif
895 ld.q SP, FRAME_S(FSSR), r6 869 ld.q SP, FRAME_S(FSSR), r6
896 shlri r6, 30, r6 870 shlri r6, 30, r6
897 andi r6, 1, r6 871 andi r6, 1, r6
@@ -905,12 +879,6 @@ ret_from_irq:
905ret_from_exception: 879ret_from_exception:
906 preempt_stop() 880 preempt_stop()
907 881
908#ifdef CONFIG_POOR_MANS_STRACE
909 pta evt_debug_ret_from_exc, tr0
910 ori SP, 0, r2
911 blink tr0, LINK
912#endif
913
914 ld.q SP, FRAME_S(FSSR), r6 882 ld.q SP, FRAME_S(FSSR), r6
915 shlri r6, 30, r6 883 shlri r6, 30, r6
916 andi r6, 1, r6 884 andi r6, 1, r6
@@ -1236,18 +1204,6 @@ syscall_bad:
1236 .global syscall_ret 1204 .global syscall_ret
1237syscall_ret: 1205syscall_ret:
1238 st.q SP, FRAME_R(9), r2 /* Expecting SP back to BASIC frame */ 1206 st.q SP, FRAME_R(9), r2 /* Expecting SP back to BASIC frame */
1239
1240#ifdef CONFIG_POOR_MANS_STRACE
1241 /* nothing useful in registers at this point */
1242
1243 movi evt_debug2, r5
1244 ori r5, 1, r5
1245 ptabs r5, tr0
1246 ld.q SP, FRAME_R(9), r2
1247 or SP, ZERO, r3
1248 blink tr0, LINK
1249#endif
1250
1251 ld.q SP, FRAME_S(FSPC), r2 1207 ld.q SP, FRAME_S(FSPC), r2
1252 addi r2, 4, r2 /* Move PC, being pre-execution event */ 1208 addi r2, 4, r2 /* Move PC, being pre-execution event */
1253 st.q SP, FRAME_S(FSPC), r2 1209 st.q SP, FRAME_S(FSPC), r2
@@ -1268,25 +1224,12 @@ ret_from_fork:
1268 ptabs r5, tr0 1224 ptabs r5, tr0
1269 blink tr0, LINK 1225 blink tr0, LINK
1270 1226
1271#ifdef CONFIG_POOR_MANS_STRACE
1272 /* nothing useful in registers at this point */
1273
1274 movi evt_debug2, r5
1275 ori r5, 1, r5
1276 ptabs r5, tr0
1277 ld.q SP, FRAME_R(9), r2
1278 or SP, ZERO, r3
1279 blink tr0, LINK
1280#endif
1281
1282 ld.q SP, FRAME_S(FSPC), r2 1227 ld.q SP, FRAME_S(FSPC), r2
1283 addi r2, 4, r2 /* Move PC, being pre-execution event */ 1228 addi r2, 4, r2 /* Move PC, being pre-execution event */
1284 st.q SP, FRAME_S(FSPC), r2 1229 st.q SP, FRAME_S(FSPC), r2
1285 pta ret_from_syscall, tr0 1230 pta ret_from_syscall, tr0
1286 blink tr0, ZERO 1231 blink tr0, ZERO
1287 1232
1288
1289
1290syscall_allowed: 1233syscall_allowed:
1291 /* Use LINK to deflect the exit point, default is syscall_ret */ 1234 /* Use LINK to deflect the exit point, default is syscall_ret */
1292 pta syscall_ret, tr0 1235 pta syscall_ret, tr0
@@ -1410,8 +1353,8 @@ peek_real_address_q:
1410 r2(out) : result quadword 1353 r2(out) : result quadword
1411 1354
1412 This is provided as a cheapskate way of manipulating device 1355 This is provided as a cheapskate way of manipulating device
1413 registers for debugging (to avoid the need to onchip_remap the debug 1356 registers for debugging (to avoid the need to ioremap the debug
1414 module, and to avoid the need to onchip_remap the watchpoint 1357 module, and to avoid the need to ioremap the watchpoint
1415 controller in a way that identity maps sufficient bits to avoid the 1358 controller in a way that identity maps sufficient bits to avoid the
1416 SH5-101 cut2 silicon defect). 1359 SH5-101 cut2 silicon defect).
1417 1360
@@ -1459,8 +1402,8 @@ poke_real_address_q:
1459 r3 : quadword value to write. 1402 r3 : quadword value to write.
1460 1403
1461 This is provided as a cheapskate way of manipulating device 1404 This is provided as a cheapskate way of manipulating device
1462 registers for debugging (to avoid the need to onchip_remap the debug 1405 registers for debugging (to avoid the need to ioremap the debug
1463 module, and to avoid the need to onchip_remap the watchpoint 1406 module, and to avoid the need to ioremap the watchpoint
1464 controller in a way that identity maps sufficient bits to avoid the 1407 controller in a way that identity maps sufficient bits to avoid the
1465 SH5-101 cut2 silicon defect). 1408 SH5-101 cut2 silicon defect).
1466 1409
diff --git a/arch/sh/kernel/cpu/sh5/setup-sh5.c b/arch/sh/kernel/cpu/sh5/setup-sh5.c
new file mode 100644
index 000000000000..f5ff1ac57fc2
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh5/setup-sh5.c
@@ -0,0 +1,195 @@
1/*
2 * SH5-101/SH5-103 CPU Setup
3 *
4 * Copyright (C) 2009 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/platform_device.h>
11#include <linux/init.h>
12#include <linux/serial.h>
13#include <linux/serial_sci.h>
14#include <linux/io.h>
15#include <linux/mm.h>
16#include <linux/sh_timer.h>
17#include <asm/addrspace.h>
18
19static struct plat_sci_port sci_platform_data[] = {
20 {
21 .mapbase = PHYS_PERIPHERAL_BLOCK + 0x01030000,
22 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
23 .type = PORT_SCIF,
24 .irqs = { 39, 40, 42, 0 },
25 }, {
26 .flags = 0,
27 }
28};
29
30static struct platform_device sci_device = {
31 .name = "sh-sci",
32 .id = -1,
33 .dev = {
34 .platform_data = sci_platform_data,
35 },
36};
37
38static struct resource rtc_resources[] = {
39 [0] = {
40 .start = PHYS_PERIPHERAL_BLOCK + 0x01040000,
41 .end = PHYS_PERIPHERAL_BLOCK + 0x01040000 + 0x58 - 1,
42 .flags = IORESOURCE_IO,
43 },
44 [1] = {
45 /* Period IRQ */
46 .start = IRQ_PRI,
47 .flags = IORESOURCE_IRQ,
48 },
49 [2] = {
50 /* Carry IRQ */
51 .start = IRQ_CUI,
52 .flags = IORESOURCE_IRQ,
53 },
54 [3] = {
55 /* Alarm IRQ */
56 .start = IRQ_ATI,
57 .flags = IORESOURCE_IRQ,
58 },
59};
60
61static struct platform_device rtc_device = {
62 .name = "sh-rtc",
63 .id = -1,
64 .num_resources = ARRAY_SIZE(rtc_resources),
65 .resource = rtc_resources,
66};
67
68#define TMU_BLOCK_OFF 0x01020000
69#define TMU_BASE PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF
70#define TMU0_BASE (TMU_BASE + 0x8 + (0xc * 0x0))
71#define TMU1_BASE (TMU_BASE + 0x8 + (0xc * 0x1))
72#define TMU2_BASE (TMU_BASE + 0x8 + (0xc * 0x2))
73
74static struct sh_timer_config tmu0_platform_data = {
75 .name = "TMU0",
76 .channel_offset = 0x04,
77 .timer_bit = 0,
78 .clk = "peripheral_clk",
79 .clockevent_rating = 200,
80};
81
82static struct resource tmu0_resources[] = {
83 [0] = {
84 .name = "TMU0",
85 .start = TMU0_BASE,
86 .end = TMU0_BASE + 0xc - 1,
87 .flags = IORESOURCE_MEM,
88 },
89 [1] = {
90 .start = IRQ_TUNI0,
91 .flags = IORESOURCE_IRQ,
92 },
93};
94
95static struct platform_device tmu0_device = {
96 .name = "sh_tmu",
97 .id = 0,
98 .dev = {
99 .platform_data = &tmu0_platform_data,
100 },
101 .resource = tmu0_resources,
102 .num_resources = ARRAY_SIZE(tmu0_resources),
103};
104
105static struct sh_timer_config tmu1_platform_data = {
106 .name = "TMU1",
107 .channel_offset = 0x10,
108 .timer_bit = 1,
109 .clk = "peripheral_clk",
110 .clocksource_rating = 200,
111};
112
113static struct resource tmu1_resources[] = {
114 [0] = {
115 .name = "TMU1",
116 .start = TMU1_BASE,
117 .end = TMU1_BASE + 0xc - 1,
118 .flags = IORESOURCE_MEM,
119 },
120 [1] = {
121 .start = IRQ_TUNI1,
122 .flags = IORESOURCE_IRQ,
123 },
124};
125
126static struct platform_device tmu1_device = {
127 .name = "sh_tmu",
128 .id = 1,
129 .dev = {
130 .platform_data = &tmu1_platform_data,
131 },
132 .resource = tmu1_resources,
133 .num_resources = ARRAY_SIZE(tmu1_resources),
134};
135
136static struct sh_timer_config tmu2_platform_data = {
137 .name = "TMU2",
138 .channel_offset = 0x1c,
139 .timer_bit = 2,
140 .clk = "peripheral_clk",
141};
142
143static struct resource tmu2_resources[] = {
144 [0] = {
145 .name = "TMU2",
146 .start = TMU2_BASE,
147 .end = TMU2_BASE + 0xc - 1,
148 .flags = IORESOURCE_MEM,
149 },
150 [1] = {
151 .start = IRQ_TUNI2,
152 .flags = IORESOURCE_IRQ,
153 },
154};
155
156static struct platform_device tmu2_device = {
157 .name = "sh_tmu",
158 .id = 2,
159 .dev = {
160 .platform_data = &tmu2_platform_data,
161 },
162 .resource = tmu2_resources,
163 .num_resources = ARRAY_SIZE(tmu2_resources),
164};
165
166static struct platform_device *sh5_early_devices[] __initdata = {
167 &tmu0_device,
168 &tmu1_device,
169 &tmu2_device,
170};
171
172static struct platform_device *sh5_devices[] __initdata = {
173 &sci_device,
174 &rtc_device,
175};
176
177static int __init sh5_devices_setup(void)
178{
179 int ret;
180
181 ret = platform_add_devices(sh5_early_devices,
182 ARRAY_SIZE(sh5_early_devices));
183 if (unlikely(ret != 0))
184 return ret;
185
186 return platform_add_devices(sh5_devices,
187 ARRAY_SIZE(sh5_devices));
188}
189__initcall(sh5_devices_setup);
190
191void __init plat_early_device_setup(void)
192{
193 early_platform_add_devices(sh5_early_devices,
194 ARRAY_SIZE(sh5_early_devices));
195}
diff --git a/arch/sh/kernel/io.c b/arch/sh/kernel/io.c
index 29cf4588fc05..4f85fffaa557 100644
--- a/arch/sh/kernel/io.c
+++ b/arch/sh/kernel/io.c
@@ -12,6 +12,7 @@
12 * for more details. 12 * for more details.
13 */ 13 */
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/pci.h>
15#include <asm/machvec.h> 16#include <asm/machvec.h>
16#include <asm/io.h> 17#include <asm/io.h>
17 18
diff --git a/arch/sh/kernel/io_trapped.c b/arch/sh/kernel/io_trapped.c
index c22853b059ef..77dfecb64373 100644
--- a/arch/sh/kernel/io_trapped.c
+++ b/arch/sh/kernel/io_trapped.c
@@ -267,7 +267,7 @@ static struct mem_access trapped_io_access = {
267int handle_trapped_io(struct pt_regs *regs, unsigned long address) 267int handle_trapped_io(struct pt_regs *regs, unsigned long address)
268{ 268{
269 mm_segment_t oldfs; 269 mm_segment_t oldfs;
270 opcode_t instruction; 270 insn_size_t instruction;
271 int tmp; 271 int tmp;
272 272
273 if (!lookup_tiop(address)) 273 if (!lookup_tiop(address))
diff --git a/arch/sh/kernel/irq.c b/arch/sh/kernel/irq.c
index 3f1372eb0091..3d09062f4682 100644
--- a/arch/sh/kernel/irq.c
+++ b/arch/sh/kernel/irq.c
@@ -31,39 +31,64 @@ void ack_bad_irq(unsigned int irq)
31} 31}
32 32
33#if defined(CONFIG_PROC_FS) 33#if defined(CONFIG_PROC_FS)
34/*
35 * /proc/interrupts printing:
36 */
37static int show_other_interrupts(struct seq_file *p, int prec)
38{
39 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
40 return 0;
41}
42
34int show_interrupts(struct seq_file *p, void *v) 43int show_interrupts(struct seq_file *p, void *v)
35{ 44{
36 int i = *(loff_t *) v, j; 45 unsigned long flags, any_count = 0;
37 struct irqaction * action; 46 int i = *(loff_t *)v, j, prec;
38 unsigned long flags; 47 struct irqaction *action;
48 struct irq_desc *desc;
49
50 if (i > nr_irqs)
51 return 0;
52
53 for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
54 j *= 10;
55
56 if (i == nr_irqs)
57 return show_other_interrupts(p, prec);
39 58
40 if (i == 0) { 59 if (i == 0) {
41 seq_puts(p, " "); 60 seq_printf(p, "%*s", prec + 8, "");
42 for_each_online_cpu(j) 61 for_each_online_cpu(j)
43 seq_printf(p, "CPU%d ",j); 62 seq_printf(p, "CPU%-8d", j);
44 seq_putc(p, '\n'); 63 seq_putc(p, '\n');
45 } 64 }
46 65
47 if (i < sh_mv.mv_nr_irqs) { 66 desc = irq_to_desc(i);
48 spin_lock_irqsave(&irq_desc[i].lock, flags); 67 if (!desc)
49 action = irq_desc[i].action; 68 return 0;
50 if (!action) 69
51 goto unlock; 70 spin_lock_irqsave(&desc->lock, flags);
52 seq_printf(p, "%3d: ",i); 71 for_each_online_cpu(j)
53 for_each_online_cpu(j) 72 any_count |= kstat_irqs_cpu(i, j);
54 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); 73 action = desc->action;
55 seq_printf(p, " %14s", irq_desc[i].chip->name); 74 if (!action && !any_count)
56 seq_printf(p, "-%-8s", irq_desc[i].name); 75 goto out;
57 seq_printf(p, " %s", action->name); 76
77 seq_printf(p, "%*d: ", prec, i);
78 for_each_online_cpu(j)
79 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
80 seq_printf(p, " %14s", desc->chip->name);
81 seq_printf(p, "-%-8s", desc->name);
58 82
59 for (action=action->next; action; action = action->next) 83 if (action) {
84 seq_printf(p, " %s", action->name);
85 while ((action = action->next) != NULL)
60 seq_printf(p, ", %s", action->name); 86 seq_printf(p, ", %s", action->name);
61 seq_putc(p, '\n'); 87 }
62unlock:
63 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
64 } else if (i == sh_mv.mv_nr_irqs)
65 seq_printf(p, "Err: %10u\n", atomic_read(&irq_err_count));
66 88
89 seq_putc(p, '\n');
90out:
91 spin_unlock_irqrestore(&desc->lock, flags);
67 return 0; 92 return 0;
68} 93}
69#endif 94#endif
@@ -254,3 +279,11 @@ void __init init_IRQ(void)
254 279
255 irq_ctx_init(smp_processor_id()); 280 irq_ctx_init(smp_processor_id());
256} 281}
282
283#ifdef CONFIG_SPARSE_IRQ
284int __init arch_probe_nr_irqs(void)
285{
286 nr_irqs = sh_mv.mv_nr_irqs;
287 return 0;
288}
289#endif
diff --git a/arch/sh/kernel/kgdb.c b/arch/sh/kernel/kgdb.c
index 7c747e7d71b8..305aad742aec 100644
--- a/arch/sh/kernel/kgdb.c
+++ b/arch/sh/kernel/kgdb.c
@@ -47,7 +47,7 @@ char in_nmi = 0; /* Set during NMI to prevent re-entry */
47/* Calculate the new address for after a step */ 47/* Calculate the new address for after a step */
48static short *get_step_address(struct pt_regs *linux_regs) 48static short *get_step_address(struct pt_regs *linux_regs)
49{ 49{
50 opcode_t op = __raw_readw(linux_regs->pc); 50 insn_size_t op = __raw_readw(linux_regs->pc);
51 long addr; 51 long addr;
52 52
53 /* BT */ 53 /* BT */
@@ -134,7 +134,7 @@ static short *get_step_address(struct pt_regs *linux_regs)
134 */ 134 */
135 135
136static unsigned long stepped_address; 136static unsigned long stepped_address;
137static opcode_t stepped_opcode; 137static insn_size_t stepped_opcode;
138 138
139static void do_single_step(struct pt_regs *linux_regs) 139static void do_single_step(struct pt_regs *linux_regs)
140{ 140{
diff --git a/arch/sh/kernel/timers/timer-broadcast.c b/arch/sh/kernel/localtimer.c
index 96e8eaea1e62..96e8eaea1e62 100644
--- a/arch/sh/kernel/timers/timer-broadcast.c
+++ b/arch/sh/kernel/localtimer.c
diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c
index c1ea41e5812a..548f6607fd0f 100644
--- a/arch/sh/kernel/machvec.c
+++ b/arch/sh/kernel/machvec.c
@@ -129,6 +129,7 @@ void __init sh_mv_setup(void)
129 mv_set(ioport_map); 129 mv_set(ioport_map);
130 mv_set(ioport_unmap); 130 mv_set(ioport_unmap);
131 mv_set(irq_demux); 131 mv_set(irq_demux);
132 mv_set(mode_pins);
132 133
133 if (!sh_mv.mv_nr_irqs) 134 if (!sh_mv.mv_nr_irqs)
134 sh_mv.mv_nr_irqs = NR_IRQS; 135 sh_mv.mv_nr_irqs = NR_IRQS;
diff --git a/arch/sh/kernel/module.c b/arch/sh/kernel/module.c
index c43081039dd5..c19b0f7d2cc1 100644
--- a/arch/sh/kernel/module.c
+++ b/arch/sh/kernel/module.c
@@ -90,7 +90,7 @@ int apply_relocate_add(Elf32_Shdr *sechdrs,
90 * SHmedia, the LSB of the symbol needs to be asserted 90 * SHmedia, the LSB of the symbol needs to be asserted
91 * for the CPU to be in SHmedia mode when it starts executing 91 * for the CPU to be in SHmedia mode when it starts executing
92 * the branch target. */ 92 * the branch target. */
93 relocation |= (sym->st_other & 4); 93 relocation |= !!(sym->st_other & 4);
94#endif 94#endif
95 95
96 switch (ELF32_R_TYPE(rel[i].r_info)) { 96 switch (ELF32_R_TYPE(rel[i].r_info)) {
diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c
index 6d94725d22f2..9289ede29c7b 100644
--- a/arch/sh/kernel/process_32.c
+++ b/arch/sh/kernel/process_32.c
@@ -251,7 +251,8 @@ static void ubc_set_tracing(int asid, unsigned long pc)
251 251
252 if (current_cpu_data.type == CPU_SH7729 || 252 if (current_cpu_data.type == CPU_SH7729 ||
253 current_cpu_data.type == CPU_SH7710 || 253 current_cpu_data.type == CPU_SH7710 ||
254 current_cpu_data.type == CPU_SH7712) { 254 current_cpu_data.type == CPU_SH7712 ||
255 current_cpu_data.type == CPU_SH7203){
255 ctrl_outw(BBR_INST | BBR_READ | BBR_CPU, UBC_BBRA); 256 ctrl_outw(BBR_INST | BBR_READ | BBR_CPU, UBC_BBRA);
256 ctrl_outl(BRCR_PCBA | BRCR_PCTE, UBC_BRCR); 257 ctrl_outl(BRCR_PCBA | BRCR_PCTE, UBC_BRCR);
257 } else { 258 } else {
@@ -407,6 +408,7 @@ asmlinkage void break_point_trap(void)
407#else 408#else
408 ctrl_outw(0, UBC_BBRA); 409 ctrl_outw(0, UBC_BBRA);
409 ctrl_outw(0, UBC_BBRB); 410 ctrl_outw(0, UBC_BBRB);
411 ctrl_outl(0, UBC_BRCR);
410#endif 412#endif
411 current->thread.ubc_pc = 0; 413 current->thread.ubc_pc = 0;
412 ubc_usercnt -= 1; 414 ubc_usercnt -= 1;
diff --git a/arch/sh/kernel/ptrace_32.c b/arch/sh/kernel/ptrace_32.c
index f7b22dd83b0c..3392e835a374 100644
--- a/arch/sh/kernel/ptrace_32.c
+++ b/arch/sh/kernel/ptrace_32.c
@@ -334,6 +334,14 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
334 [(addr - (long)&dummy->fpu) >> 2]; 334 [(addr - (long)&dummy->fpu) >> 2];
335 } else if (addr == (long) &dummy->u_fpvalid) 335 } else if (addr == (long) &dummy->u_fpvalid)
336 tmp = !!tsk_used_math(child); 336 tmp = !!tsk_used_math(child);
337 else if (addr == PT_TEXT_ADDR)
338 tmp = child->mm->start_code;
339 else if (addr == PT_DATA_ADDR)
340 tmp = child->mm->start_data;
341 else if (addr == PT_TEXT_END_ADDR)
342 tmp = child->mm->end_code;
343 else if (addr == PT_TEXT_LEN)
344 tmp = child->mm->end_code - child->mm->start_code;
337 else 345 else
338 tmp = 0; 346 tmp = 0;
339 ret = put_user(tmp, datap); 347 ret = put_user(tmp, datap);
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index 04a6004fccc4..dd38338553ef 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -29,6 +29,7 @@
29#include <linux/mmzone.h> 29#include <linux/mmzone.h>
30#include <linux/clk.h> 30#include <linux/clk.h>
31#include <linux/delay.h> 31#include <linux/delay.h>
32#include <linux/platform_device.h>
32#include <asm/uaccess.h> 33#include <asm/uaccess.h>
33#include <asm/io.h> 34#include <asm/io.h>
34#include <asm/page.h> 35#include <asm/page.h>
@@ -155,7 +156,7 @@ static void __init reserve_crashkernel(void)
155 &crash_size, &crash_base); 156 &crash_size, &crash_base);
156 if (ret == 0 && crash_size) { 157 if (ret == 0 && crash_size) {
157 if (crash_base <= 0) { 158 if (crash_base <= 0) {
158 vp = alloc_bootmem_nopanic(crash_size); 159 vp = alloc_bootmem_nopanic(crash_size);
159 if (!vp) { 160 if (!vp) {
160 printk(KERN_INFO "crashkernel allocation " 161 printk(KERN_INFO "crashkernel allocation "
161 "failed\n"); 162 "failed\n");
@@ -184,7 +185,6 @@ static inline void __init reserve_crashkernel(void)
184{} 185{}
185#endif 186#endif
186 187
187#ifndef CONFIG_GENERIC_CALIBRATE_DELAY
188void __cpuinit calibrate_delay(void) 188void __cpuinit calibrate_delay(void)
189{ 189{
190 struct clk *clk = clk_get(NULL, "cpu_clk"); 190 struct clk *clk = clk_get(NULL, "cpu_clk");
@@ -200,7 +200,6 @@ void __cpuinit calibrate_delay(void)
200 (loops_per_jiffy/(5000/HZ)) % 100, 200 (loops_per_jiffy/(5000/HZ)) % 100,
201 loops_per_jiffy); 201 loops_per_jiffy);
202} 202}
203#endif
204 203
205void __init __add_active_range(unsigned int nid, unsigned long start_pfn, 204void __init __add_active_range(unsigned int nid, unsigned long start_pfn,
206 unsigned long end_pfn) 205 unsigned long end_pfn)
@@ -328,6 +327,10 @@ static int __init parse_elfcorehdr(char *arg)
328early_param("elfcorehdr", parse_elfcorehdr); 327early_param("elfcorehdr", parse_elfcorehdr);
329#endif 328#endif
330 329
330void __init __attribute__ ((weak)) plat_early_device_setup(void)
331{
332}
333
331void __init setup_arch(char **cmdline_p) 334void __init setup_arch(char **cmdline_p)
332{ 335{
333 enable_mmu(); 336 enable_mmu();
@@ -381,6 +384,8 @@ void __init setup_arch(char **cmdline_p)
381 384
382 parse_early_param(); 385 parse_early_param();
383 386
387 plat_early_device_setup();
388
384 sh_mv_setup(); 389 sh_mv_setup();
385 390
386 /* 391 /*
@@ -415,6 +420,18 @@ void __init setup_arch(char **cmdline_p)
415#endif 420#endif
416} 421}
417 422
423/* processor boot mode configuration */
424int generic_mode_pins(void)
425{
426 pr_warning("generic_mode_pins(): missing mode pin configuration\n");
427 return 0;
428}
429
430int test_mode_pin(int pin)
431{
432 return sh_mv.mv_mode_pins() & pin;
433}
434
418static const char *cpu_name[] = { 435static const char *cpu_name[] = {
419 [CPU_SH7201] = "SH7201", 436 [CPU_SH7201] = "SH7201",
420 [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263", 437 [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263",
@@ -435,7 +452,8 @@ static const char *cpu_name[] = {
435 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3", 452 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
436 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103", 453 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
437 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723", 454 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
438 [CPU_SH7366] = "SH7366", [CPU_SH_NONE] = "Unknown" 455 [CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724",
456 [CPU_SH_NONE] = "Unknown"
439}; 457};
440 458
441const char *get_cpu_subtype(struct sh_cpuinfo *c) 459const char *get_cpu_subtype(struct sh_cpuinfo *c)
diff --git a/arch/sh/kernel/sh_ksyms_32.c b/arch/sh/kernel/sh_ksyms_32.c
index 528de2955c81..fcc5de31f83b 100644
--- a/arch/sh/kernel/sh_ksyms_32.c
+++ b/arch/sh/kernel/sh_ksyms_32.c
@@ -19,14 +19,10 @@
19#include <asm/ftrace.h> 19#include <asm/ftrace.h>
20 20
21extern int dump_fpu(struct pt_regs *, elf_fpregset_t *); 21extern int dump_fpu(struct pt_regs *, elf_fpregset_t *);
22extern struct hw_interrupt_type no_irq_type;
23 22
24/* platform dependent support */ 23/* platform dependent support */
25EXPORT_SYMBOL(dump_fpu); 24EXPORT_SYMBOL(dump_fpu);
26EXPORT_SYMBOL(kernel_thread); 25EXPORT_SYMBOL(kernel_thread);
27EXPORT_SYMBOL(irq_desc);
28EXPORT_SYMBOL(no_irq_type);
29
30EXPORT_SYMBOL(strlen); 26EXPORT_SYMBOL(strlen);
31 27
32/* PCI exports */ 28/* PCI exports */
@@ -41,11 +37,6 @@ EXPORT_SYMBOL(memcpy);
41EXPORT_SYMBOL(memset); 37EXPORT_SYMBOL(memset);
42EXPORT_SYMBOL(memmove); 38EXPORT_SYMBOL(memmove);
43EXPORT_SYMBOL(__copy_user); 39EXPORT_SYMBOL(__copy_user);
44
45#ifdef CONFIG_MMU
46EXPORT_SYMBOL(get_vm_area);
47#endif
48
49EXPORT_SYMBOL(__udelay); 40EXPORT_SYMBOL(__udelay);
50EXPORT_SYMBOL(__ndelay); 41EXPORT_SYMBOL(__ndelay);
51EXPORT_SYMBOL(__const_udelay); 42EXPORT_SYMBOL(__const_udelay);
diff --git a/arch/sh/kernel/sh_ksyms_64.c b/arch/sh/kernel/sh_ksyms_64.c
index 0d74d6b8774e..8f54ef0cfbca 100644
--- a/arch/sh/kernel/sh_ksyms_64.c
+++ b/arch/sh/kernel/sh_ksyms_64.c
@@ -76,5 +76,7 @@ EXPORT_SYMBOL(strcpy);
76#define DECLARE_EXPORT(name) extern void name(void);EXPORT_SYMBOL(name) 76#define DECLARE_EXPORT(name) extern void name(void);EXPORT_SYMBOL(name)
77 77
78DECLARE_EXPORT(__sdivsi3); 78DECLARE_EXPORT(__sdivsi3);
79DECLARE_EXPORT(__sdivsi3_1);
80DECLARE_EXPORT(__sdivsi3_2);
79DECLARE_EXPORT(__udivsi3); 81DECLARE_EXPORT(__udivsi3);
80DECLARE_EXPORT(__div_table); 82DECLARE_EXPORT(__div_table);
diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S
index 05202edd8e21..a9fff9f731ec 100644
--- a/arch/sh/kernel/syscalls_32.S
+++ b/arch/sh/kernel/syscalls_32.S
@@ -350,4 +350,5 @@ ENTRY(sys_call_table)
350 .long sys_pipe2 350 .long sys_pipe2
351 .long sys_inotify_init1 351 .long sys_inotify_init1
352 .long sys_preadv 352 .long sys_preadv
353 .long sys_writev 353 .long sys_pwritev
354 .long sys_rt_tgsigqueueinfo /* 335 */
diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S
index a083609f9284..75c1889af1ed 100644
--- a/arch/sh/kernel/syscalls_64.S
+++ b/arch/sh/kernel/syscalls_64.S
@@ -389,3 +389,4 @@ sys_call_table:
389 .long sys_inotify_init1 /* 360 */ 389 .long sys_inotify_init1 /* 360 */
390 .long sys_preadv 390 .long sys_preadv
391 .long sys_pwritev 391 .long sys_pwritev
392 .long sys_rt_tgsigqueueinfo
diff --git a/arch/sh/kernel/time.c b/arch/sh/kernel/time.c
new file mode 100644
index 000000000000..2edde32c764b
--- /dev/null
+++ b/arch/sh/kernel/time.c
@@ -0,0 +1,125 @@
1/*
2 * arch/sh/kernel/time.c
3 *
4 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
5 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
6 * Copyright (C) 2002 - 2009 Paul Mundt
7 * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
11 * for more details.
12 */
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/profile.h>
17#include <linux/timex.h>
18#include <linux/sched.h>
19#include <linux/clockchips.h>
20#include <linux/platform_device.h>
21#include <linux/smp.h>
22#include <linux/rtc.h>
23#include <asm/clock.h>
24#include <asm/rtc.h>
25
26/* Dummy RTC ops */
27static void null_rtc_get_time(struct timespec *tv)
28{
29 tv->tv_sec = mktime(2000, 1, 1, 0, 0, 0);
30 tv->tv_nsec = 0;
31}
32
33static int null_rtc_set_time(const time_t secs)
34{
35 return 0;
36}
37
38void (*rtc_sh_get_time)(struct timespec *) = null_rtc_get_time;
39int (*rtc_sh_set_time)(const time_t) = null_rtc_set_time;
40
41#ifdef CONFIG_GENERIC_CMOS_UPDATE
42unsigned long read_persistent_clock(void)
43{
44 struct timespec tv;
45 rtc_sh_get_time(&tv);
46 return tv.tv_sec;
47}
48
49int update_persistent_clock(struct timespec now)
50{
51 return rtc_sh_set_time(now.tv_sec);
52}
53#endif
54
55unsigned int get_rtc_time(struct rtc_time *tm)
56{
57 if (rtc_sh_get_time != null_rtc_get_time) {
58 struct timespec tv;
59
60 rtc_sh_get_time(&tv);
61 rtc_time_to_tm(tv.tv_sec, tm);
62 }
63
64 return RTC_24H;
65}
66EXPORT_SYMBOL(get_rtc_time);
67
68int set_rtc_time(struct rtc_time *tm)
69{
70 unsigned long secs;
71
72 rtc_tm_to_time(tm, &secs);
73 return rtc_sh_set_time(secs);
74}
75EXPORT_SYMBOL(set_rtc_time);
76
77static int __init rtc_generic_init(void)
78{
79 struct platform_device *pdev;
80
81 if (rtc_sh_get_time == null_rtc_get_time)
82 return -ENODEV;
83
84 pdev = platform_device_register_simple("rtc-generic", -1, NULL, 0);
85 if (IS_ERR(pdev))
86 return PTR_ERR(pdev);
87
88 return 0;
89}
90module_init(rtc_generic_init);
91
92void (*board_time_init)(void);
93
94unsigned long long sched_clock(void)
95{
96 return (jiffies_64 - INITIAL_JIFFIES) * (NSEC_PER_SEC / HZ);
97}
98
99static void __init sh_late_time_init(void)
100{
101 /*
102 * Make sure all compiled-in early timers register themselves.
103 * Run probe() for one "earlytimer" device.
104 */
105 early_platform_driver_register_all("earlytimer");
106 early_platform_driver_probe("earlytimer", 1, 0);
107}
108
109void __init time_init(void)
110{
111 if (board_time_init)
112 board_time_init();
113
114 clk_init();
115
116 rtc_sh_get_time(&xtime);
117 set_normalized_timespec(&wall_to_monotonic,
118 -xtime.tv_sec, -xtime.tv_nsec);
119
120#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
121 local_timer_setup(smp_processor_id());
122#endif
123
124 late_time_init = sh_late_time_init;
125}
diff --git a/arch/sh/kernel/time_32.c b/arch/sh/kernel/time_32.c
deleted file mode 100644
index 1700d2465f6c..000000000000
--- a/arch/sh/kernel/time_32.c
+++ /dev/null
@@ -1,240 +0,0 @@
1/*
2 * arch/sh/kernel/time_32.c
3 *
4 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
5 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
6 * Copyright (C) 2002 - 2008 Paul Mundt
7 * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
8 *
9 * Some code taken from i386 version.
10 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
11 */
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/profile.h>
16#include <linux/timex.h>
17#include <linux/sched.h>
18#include <linux/clockchips.h>
19#include <linux/mc146818rtc.h> /* for rtc_lock */
20#include <linux/smp.h>
21#include <asm/clock.h>
22#include <asm/rtc.h>
23#include <asm/timer.h>
24#include <asm/kgdb.h>
25
26struct sys_timer *sys_timer;
27
28/* Move this somewhere more sensible.. */
29DEFINE_SPINLOCK(rtc_lock);
30EXPORT_SYMBOL(rtc_lock);
31
32/* Dummy RTC ops */
33static void null_rtc_get_time(struct timespec *tv)
34{
35 tv->tv_sec = mktime(2000, 1, 1, 0, 0, 0);
36 tv->tv_nsec = 0;
37}
38
39static int null_rtc_set_time(const time_t secs)
40{
41 return 0;
42}
43
44void (*rtc_sh_get_time)(struct timespec *) = null_rtc_get_time;
45int (*rtc_sh_set_time)(const time_t) = null_rtc_set_time;
46
47#ifndef CONFIG_GENERIC_TIME
48void do_gettimeofday(struct timeval *tv)
49{
50 unsigned long flags;
51 unsigned long seq;
52 unsigned long usec, sec;
53
54 do {
55 /*
56 * Turn off IRQs when grabbing xtime_lock, so that
57 * the sys_timer get_offset code doesn't have to handle it.
58 */
59 seq = read_seqbegin_irqsave(&xtime_lock, flags);
60 usec = get_timer_offset();
61 sec = xtime.tv_sec;
62 usec += xtime.tv_nsec / NSEC_PER_USEC;
63 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
64
65 while (usec >= 1000000) {
66 usec -= 1000000;
67 sec++;
68 }
69
70 tv->tv_sec = sec;
71 tv->tv_usec = usec;
72}
73EXPORT_SYMBOL(do_gettimeofday);
74
75int do_settimeofday(struct timespec *tv)
76{
77 time_t wtm_sec, sec = tv->tv_sec;
78 long wtm_nsec, nsec = tv->tv_nsec;
79
80 if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
81 return -EINVAL;
82
83 write_seqlock_irq(&xtime_lock);
84 /*
85 * This is revolting. We need to set "xtime" correctly. However, the
86 * value in this location is the value at the most recent update of
87 * wall time. Discover what correction gettimeofday() would have
88 * made, and then undo it!
89 */
90 nsec -= get_timer_offset() * NSEC_PER_USEC;
91
92 wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
93 wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
94
95 set_normalized_timespec(&xtime, sec, nsec);
96 set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
97
98 ntp_clear();
99 write_sequnlock_irq(&xtime_lock);
100 clock_was_set();
101
102 return 0;
103}
104EXPORT_SYMBOL(do_settimeofday);
105#endif /* !CONFIG_GENERIC_TIME */
106
107/* last time the RTC clock got updated */
108static long last_rtc_update;
109
110/*
111 * handle_timer_tick() needs to keep up the real-time clock,
112 * as well as call the "do_timer()" routine every clocktick
113 */
114void handle_timer_tick(void)
115{
116 if (current->pid)
117 profile_tick(CPU_PROFILING);
118
119 /*
120 * Here we are in the timer irq handler. We just have irqs locally
121 * disabled but we don't know if the timer_bh is running on the other
122 * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
123 * the irq version of write_lock because as just said we have irq
124 * locally disabled. -arca
125 */
126 write_seqlock(&xtime_lock);
127 do_timer(1);
128
129 /*
130 * If we have an externally synchronized Linux clock, then update
131 * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
132 * called as close as possible to 500 ms before the new second starts.
133 */
134 if (ntp_synced() &&
135 xtime.tv_sec > last_rtc_update + 660 &&
136 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
137 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
138 if (rtc_sh_set_time(xtime.tv_sec) == 0)
139 last_rtc_update = xtime.tv_sec;
140 else
141 /* do it again in 60s */
142 last_rtc_update = xtime.tv_sec - 600;
143 }
144 write_sequnlock(&xtime_lock);
145
146#ifndef CONFIG_SMP
147 update_process_times(user_mode(get_irq_regs()));
148#endif
149}
150
151#ifdef CONFIG_PM
152int timer_suspend(struct sys_device *dev, pm_message_t state)
153{
154 struct sys_timer *sys_timer = container_of(dev, struct sys_timer, dev);
155
156 sys_timer->ops->stop();
157
158 return 0;
159}
160
161int timer_resume(struct sys_device *dev)
162{
163 struct sys_timer *sys_timer = container_of(dev, struct sys_timer, dev);
164
165 sys_timer->ops->start();
166
167 return 0;
168}
169#else
170#define timer_suspend NULL
171#define timer_resume NULL
172#endif
173
174static struct sysdev_class timer_sysclass = {
175 .name = "timer",
176 .suspend = timer_suspend,
177 .resume = timer_resume,
178};
179
180static int __init timer_init_sysfs(void)
181{
182 int ret;
183
184 if (!sys_timer)
185 return 0;
186
187 ret = sysdev_class_register(&timer_sysclass);
188 if (ret != 0)
189 return ret;
190
191 sys_timer->dev.cls = &timer_sysclass;
192 return sysdev_register(&sys_timer->dev);
193}
194device_initcall(timer_init_sysfs);
195
196void (*board_time_init)(void);
197
198struct clocksource clocksource_sh = {
199 .name = "SuperH",
200};
201
202#ifdef CONFIG_GENERIC_TIME
203unsigned long long sched_clock(void)
204{
205 unsigned long long cycles;
206
207 /* jiffies based sched_clock if no clocksource is installed */
208 if (!clocksource_sh.rating)
209 return (unsigned long long)jiffies * (NSEC_PER_SEC / HZ);
210
211 cycles = clocksource_sh.read(&clocksource_sh);
212 return cyc2ns(&clocksource_sh, cycles);
213}
214#endif
215
216void __init time_init(void)
217{
218 if (board_time_init)
219 board_time_init();
220
221 clk_init();
222
223 rtc_sh_get_time(&xtime);
224 set_normalized_timespec(&wall_to_monotonic,
225 -xtime.tv_sec, -xtime.tv_nsec);
226
227#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
228 local_timer_setup(smp_processor_id());
229#endif
230
231 /*
232 * Find the timer to use as the system timer, it will be
233 * initialized for us.
234 */
235 sys_timer = get_sys_timer();
236 if (unlikely(!sys_timer))
237 panic("System timer missing.\n");
238
239 printk(KERN_INFO "Using %s for system timer\n", sys_timer->name);
240}
diff --git a/arch/sh/kernel/time_64.c b/arch/sh/kernel/time_64.c
deleted file mode 100644
index 988c77c37231..000000000000
--- a/arch/sh/kernel/time_64.c
+++ /dev/null
@@ -1,363 +0,0 @@
1/*
2 * arch/sh/kernel/time_64.c
3 *
4 * Copyright (C) 2000, 2001 Paolo Alberelli
5 * Copyright (C) 2003 - 2007 Paul Mundt
6 * Copyright (C) 2003 Richard Curnow
7 *
8 * Original TMU/RTC code taken from sh version.
9 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
10 * Some code taken from i386 version.
11 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
15 * for more details.
16 */
17#include <linux/errno.h>
18#include <linux/rwsem.h>
19#include <linux/sched.h>
20#include <linux/kernel.h>
21#include <linux/param.h>
22#include <linux/string.h>
23#include <linux/mm.h>
24#include <linux/interrupt.h>
25#include <linux/time.h>
26#include <linux/delay.h>
27#include <linux/init.h>
28#include <linux/profile.h>
29#include <linux/smp.h>
30#include <linux/module.h>
31#include <linux/bcd.h>
32#include <linux/timex.h>
33#include <linux/irq.h>
34#include <linux/io.h>
35#include <linux/platform_device.h>
36#include <cpu/registers.h> /* required by inline __asm__ stmt. */
37#include <cpu/irq.h>
38#include <asm/addrspace.h>
39#include <asm/processor.h>
40#include <asm/uaccess.h>
41#include <asm/delay.h>
42#include <asm/clock.h>
43
44#define TMU_TOCR_INIT 0x00
45#define TMU0_TCR_INIT 0x0020
46#define TMU_TSTR_INIT 1
47#define TMU_TSTR_OFF 0
48
49/* Real Time Clock */
50#define RTC_BLOCK_OFF 0x01040000
51#define RTC_BASE PHYS_PERIPHERAL_BLOCK + RTC_BLOCK_OFF
52#define RTC_RCR1_CIE 0x10 /* Carry Interrupt Enable */
53#define RTC_RCR1 (rtc_base + 0x38)
54
55/* Time Management Unit */
56#define TMU_BLOCK_OFF 0x01020000
57#define TMU_BASE PHYS_PERIPHERAL_BLOCK + TMU_BLOCK_OFF
58#define TMU0_BASE tmu_base + 0x8 + (0xc * 0x0)
59#define TMU1_BASE tmu_base + 0x8 + (0xc * 0x1)
60#define TMU2_BASE tmu_base + 0x8 + (0xc * 0x2)
61
62#define TMU_TOCR tmu_base+0x0 /* Byte access */
63#define TMU_TSTR tmu_base+0x4 /* Byte access */
64
65#define TMU0_TCOR TMU0_BASE+0x0 /* Long access */
66#define TMU0_TCNT TMU0_BASE+0x4 /* Long access */
67#define TMU0_TCR TMU0_BASE+0x8 /* Word access */
68
69#define TICK_SIZE (tick_nsec / 1000)
70
71static unsigned long tmu_base, rtc_base;
72unsigned long cprc_base;
73
74/* Variables to allow interpolation of time of day to resolution better than a
75 * jiffy. */
76
77/* This is effectively protected by xtime_lock */
78static unsigned long ctc_last_interrupt;
79static unsigned long long usecs_per_jiffy = 1000000/HZ; /* Approximation */
80
81#define CTC_JIFFY_SCALE_SHIFT 40
82
83/* 2**CTC_JIFFY_SCALE_SHIFT / ctc_ticks_per_jiffy */
84static unsigned long long scaled_recip_ctc_ticks_per_jiffy;
85
86/* Estimate number of microseconds that have elapsed since the last timer tick,
87 by scaling the delta that has occurred in the CTC register.
88
89 WARNING WARNING WARNING : This algorithm relies on the CTC decrementing at
90 the CPU clock rate. If the CPU sleeps, the CTC stops counting. Bear this
91 in mind if enabling SLEEP_WORKS in process.c. In that case, this algorithm
92 probably needs to use TMU.TCNT0 instead. This will work even if the CPU is
93 sleeping, though will be coarser.
94
95 FIXME : What if usecs_per_tick is moving around too much, e.g. if an adjtime
96 is running or if the freq or tick arguments of adjtimex are modified after
97 we have calibrated the scaling factor? This will result in either a jump at
98 the end of a tick period, or a wrap backwards at the start of the next one,
99 if the application is reading the time of day often enough. I think we
100 ought to do better than this. For this reason, usecs_per_jiffy is left
101 separated out in the calculation below. This allows some future hook into
102 the adjtime-related stuff in kernel/timer.c to remove this hazard.
103
104*/
105
106static unsigned long usecs_since_tick(void)
107{
108 unsigned long long current_ctc;
109 long ctc_ticks_since_interrupt;
110 unsigned long long ull_ctc_ticks_since_interrupt;
111 unsigned long result;
112
113 unsigned long long mul1_out;
114 unsigned long long mul1_out_high;
115 unsigned long long mul2_out_low, mul2_out_high;
116
117 /* Read CTC register */
118 asm ("getcon cr62, %0" : "=r" (current_ctc));
119 /* Note, the CTC counts down on each CPU clock, not up.
120 Note(2), use long type to get correct wraparound arithmetic when
121 the counter crosses zero. */
122 ctc_ticks_since_interrupt = (long) ctc_last_interrupt - (long) current_ctc;
123 ull_ctc_ticks_since_interrupt = (unsigned long long) ctc_ticks_since_interrupt;
124
125 /* Inline assembly to do 32x32x32->64 multiplier */
126 asm volatile ("mulu.l %1, %2, %0" :
127 "=r" (mul1_out) :
128 "r" (ull_ctc_ticks_since_interrupt), "r" (usecs_per_jiffy));
129
130 mul1_out_high = mul1_out >> 32;
131
132 asm volatile ("mulu.l %1, %2, %0" :
133 "=r" (mul2_out_low) :
134 "r" (mul1_out), "r" (scaled_recip_ctc_ticks_per_jiffy));
135
136#if 1
137 asm volatile ("mulu.l %1, %2, %0" :
138 "=r" (mul2_out_high) :
139 "r" (mul1_out_high), "r" (scaled_recip_ctc_ticks_per_jiffy));
140#endif
141
142 result = (unsigned long) (((mul2_out_high << 32) + mul2_out_low) >> CTC_JIFFY_SCALE_SHIFT);
143
144 return result;
145}
146
147void do_gettimeofday(struct timeval *tv)
148{
149 unsigned long flags;
150 unsigned long seq;
151 unsigned long usec, sec;
152
153 do {
154 seq = read_seqbegin_irqsave(&xtime_lock, flags);
155 usec = usecs_since_tick();
156 sec = xtime.tv_sec;
157 usec += xtime.tv_nsec / 1000;
158 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
159
160 while (usec >= 1000000) {
161 usec -= 1000000;
162 sec++;
163 }
164
165 tv->tv_sec = sec;
166 tv->tv_usec = usec;
167}
168EXPORT_SYMBOL(do_gettimeofday);
169
170int do_settimeofday(struct timespec *tv)
171{
172 time_t wtm_sec, sec = tv->tv_sec;
173 long wtm_nsec, nsec = tv->tv_nsec;
174
175 if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
176 return -EINVAL;
177
178 write_seqlock_irq(&xtime_lock);
179 /*
180 * This is revolting. We need to set "xtime" correctly. However, the
181 * value in this location is the value at the most recent update of
182 * wall time. Discover what correction gettimeofday() would have
183 * made, and then undo it!
184 */
185 nsec -= 1000 * usecs_since_tick();
186
187 wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
188 wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
189
190 set_normalized_timespec(&xtime, sec, nsec);
191 set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
192
193 ntp_clear();
194 write_sequnlock_irq(&xtime_lock);
195 clock_was_set();
196
197 return 0;
198}
199EXPORT_SYMBOL(do_settimeofday);
200
201/* Dummy RTC ops */
202static void null_rtc_get_time(struct timespec *tv)
203{
204 tv->tv_sec = mktime(2000, 1, 1, 0, 0, 0);
205 tv->tv_nsec = 0;
206}
207
208static int null_rtc_set_time(const time_t secs)
209{
210 return 0;
211}
212
213void (*rtc_sh_get_time)(struct timespec *) = null_rtc_get_time;
214int (*rtc_sh_set_time)(const time_t) = null_rtc_set_time;
215
216/* last time the RTC clock got updated */
217static long last_rtc_update;
218
219/*
220 * timer_interrupt() needs to keep up the real-time clock,
221 * as well as call the "do_timer()" routine every clocktick
222 */
223static inline void do_timer_interrupt(void)
224{
225 unsigned long long current_ctc;
226
227 if (current->pid)
228 profile_tick(CPU_PROFILING);
229
230 /*
231 * Here we are in the timer irq handler. We just have irqs locally
232 * disabled but we don't know if the timer_bh is running on the other
233 * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
234 * the irq version of write_lock because as just said we have irq
235 * locally disabled. -arca
236 */
237 write_seqlock(&xtime_lock);
238 asm ("getcon cr62, %0" : "=r" (current_ctc));
239 ctc_last_interrupt = (unsigned long) current_ctc;
240
241 do_timer(1);
242
243 /*
244 * If we have an externally synchronized Linux clock, then update
245 * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
246 * called as close as possible to 500 ms before the new second starts.
247 */
248 if (ntp_synced() &&
249 xtime.tv_sec > last_rtc_update + 660 &&
250 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
251 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
252 if (rtc_sh_set_time(xtime.tv_sec) == 0)
253 last_rtc_update = xtime.tv_sec;
254 else
255 /* do it again in 60 s */
256 last_rtc_update = xtime.tv_sec - 600;
257 }
258 write_sequnlock(&xtime_lock);
259
260#ifndef CONFIG_SMP
261 update_process_times(user_mode(get_irq_regs()));
262#endif
263}
264
265/*
266 * This is the same as the above, except we _also_ save the current
267 * Time Stamp Counter value at the time of the timer interrupt, so that
268 * we later on can estimate the time of day more exactly.
269 */
270static irqreturn_t timer_interrupt(int irq, void *dev_id)
271{
272 unsigned long timer_status;
273
274 /* Clear UNF bit */
275 timer_status = ctrl_inw(TMU0_TCR);
276 timer_status &= ~0x100;
277 ctrl_outw(timer_status, TMU0_TCR);
278
279 do_timer_interrupt();
280
281 return IRQ_HANDLED;
282}
283
284static struct irqaction irq0 = {
285 .handler = timer_interrupt,
286 .flags = IRQF_DISABLED,
287 .name = "timer",
288};
289
290void __init time_init(void)
291{
292 unsigned long interval;
293 struct clk *clk;
294
295 tmu_base = onchip_remap(TMU_BASE, 1024, "TMU");
296 if (!tmu_base) {
297 panic("Unable to remap TMU\n");
298 }
299
300 rtc_base = onchip_remap(RTC_BASE, 1024, "RTC");
301 if (!rtc_base) {
302 panic("Unable to remap RTC\n");
303 }
304
305 clk = clk_get(NULL, "cpu_clk");
306 scaled_recip_ctc_ticks_per_jiffy = ((1ULL << CTC_JIFFY_SCALE_SHIFT) /
307 (unsigned long long)(clk_get_rate(clk) / HZ));
308
309 rtc_sh_get_time(&xtime);
310
311 setup_irq(TIMER_IRQ, &irq0);
312
313 clk = clk_get(NULL, "module_clk");
314 interval = (clk_get_rate(clk)/(HZ*4));
315
316 printk("Interval = %ld\n", interval);
317
318 /* Start TMU0 */
319 ctrl_outb(TMU_TSTR_OFF, TMU_TSTR);
320 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
321 ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
322 ctrl_outl(interval, TMU0_TCOR);
323 ctrl_outl(interval, TMU0_TCNT);
324 ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
325}
326
327static struct resource rtc_resources[] = {
328 [0] = {
329 /* RTC base, filled in by rtc_init */
330 .flags = IORESOURCE_IO,
331 },
332 [1] = {
333 /* Period IRQ */
334 .start = IRQ_PRI,
335 .flags = IORESOURCE_IRQ,
336 },
337 [2] = {
338 /* Carry IRQ */
339 .start = IRQ_CUI,
340 .flags = IORESOURCE_IRQ,
341 },
342 [3] = {
343 /* Alarm IRQ */
344 .start = IRQ_ATI,
345 .flags = IORESOURCE_IRQ,
346 },
347};
348
349static struct platform_device rtc_device = {
350 .name = "sh-rtc",
351 .id = -1,
352 .num_resources = ARRAY_SIZE(rtc_resources),
353 .resource = rtc_resources,
354};
355
356static int __init rtc_init(void)
357{
358 rtc_resources[0].start = rtc_base;
359 rtc_resources[0].end = rtc_resources[0].start + 0x58 - 1;
360
361 return platform_device_register(&rtc_device);
362}
363device_initcall(rtc_init);
diff --git a/arch/sh/kernel/timers/Makefile b/arch/sh/kernel/timers/Makefile
deleted file mode 100644
index 0b7f8577193f..000000000000
--- a/arch/sh/kernel/timers/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
1#
2# Makefile for the various Linux/SuperH timers
3#
4
5obj-y := timer.o
6
7obj-$(CONFIG_SH_TMU) += timer-tmu.o
8obj-$(CONFIG_SH_MTU2) += timer-mtu2.o
9obj-$(CONFIG_SH_CMT) += timer-cmt.o
10
11obj-$(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST) += timer-broadcast.o
diff --git a/arch/sh/kernel/timers/timer-cmt.c b/arch/sh/kernel/timers/timer-cmt.c
deleted file mode 100644
index 9aa348658ae3..000000000000
--- a/arch/sh/kernel/timers/timer-cmt.c
+++ /dev/null
@@ -1,188 +0,0 @@
1/*
2 * arch/sh/kernel/timers/timer-cmt.c - CMT Timer Support
3 *
4 * Copyright (C) 2005 Yoshinori Sato
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/init.h>
12#include <linux/kernel.h>
13#include <linux/interrupt.h>
14#include <linux/seqlock.h>
15#include <asm/timer.h>
16#include <asm/rtc.h>
17#include <asm/io.h>
18#include <asm/irq.h>
19#include <asm/clock.h>
20
21#if defined(CONFIG_CPU_SUBTYPE_SH7619)
22#define CMT_CMSTR 0xf84a0070
23#define CMT_CMCSR_0 0xf84a0072
24#define CMT_CMCNT_0 0xf84a0074
25#define CMT_CMCOR_0 0xf84a0076
26#define CMT_CMCSR_1 0xf84a0078
27#define CMT_CMCNT_1 0xf84a007a
28#define CMT_CMCOR_1 0xf84a007c
29
30#define STBCR3 0xf80a0000
31#define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR3) & ~0x10, STBCR3); } while(0)
32#define CMT_CMCSR_INIT 0x0040
33#define CMT_CMCSR_CALIB 0x0000
34#elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
36 defined(CONFIG_CPU_SUBTYPE_SH7263)
37#define CMT_CMSTR 0xfffec000
38#define CMT_CMCSR_0 0xfffec002
39#define CMT_CMCNT_0 0xfffec004
40#define CMT_CMCOR_0 0xfffec006
41
42#define STBCR4 0xfffe040c
43#define cmt_clock_enable() do { ctrl_outb(ctrl_inb(STBCR4) & ~0x04, STBCR4); } while(0)
44#define CMT_CMCSR_INIT 0x0040
45#define CMT_CMCSR_CALIB 0x0000
46#else
47#error "Unknown CPU SUBTYPE"
48#endif
49
50static unsigned long cmt_timer_get_offset(void)
51{
52 int count;
53 static unsigned short count_p = 0xffff; /* for the first call after boot */
54 static unsigned long jiffies_p = 0;
55
56 /*
57 * cache volatile jiffies temporarily; we have IRQs turned off.
58 */
59 unsigned long jiffies_t;
60
61 /* timer count may underflow right here */
62 count = ctrl_inw(CMT_CMCOR_0);
63 count -= ctrl_inw(CMT_CMCNT_0);
64
65 jiffies_t = jiffies;
66
67 /*
68 * avoiding timer inconsistencies (they are rare, but they happen)...
69 * there is one kind of problem that must be avoided here:
70 * 1. the timer counter underflows
71 */
72
73 if (jiffies_t == jiffies_p) {
74 if (count > count_p) {
75 /* the nutcase */
76 if (ctrl_inw(CMT_CMCSR_0) & 0x80) { /* Check CMF bit */
77 count -= LATCH;
78 } else {
79 printk("%s (): hardware timer problem?\n",
80 __func__);
81 }
82 }
83 } else
84 jiffies_p = jiffies_t;
85
86 count_p = count;
87
88 count = ((LATCH-1) - count) * TICK_SIZE;
89 count = (count + LATCH/2) / LATCH;
90
91 return count;
92}
93
94static irqreturn_t cmt_timer_interrupt(int irq, void *dev_id)
95{
96 unsigned long timer_status;
97
98 /* Clear CMF bit */
99 timer_status = ctrl_inw(CMT_CMCSR_0);
100 timer_status &= ~0x80;
101 ctrl_outw(timer_status, CMT_CMCSR_0);
102
103 handle_timer_tick();
104
105 return IRQ_HANDLED;
106}
107
108static struct irqaction cmt_irq = {
109 .name = "timer",
110 .handler = cmt_timer_interrupt,
111 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
112};
113
114static void cmt_clk_init(struct clk *clk)
115{
116 u8 divisor = CMT_CMCSR_INIT & 0x3;
117 ctrl_inw(CMT_CMCSR_0);
118 ctrl_outw(CMT_CMCSR_INIT, CMT_CMCSR_0);
119 clk->parent = clk_get(NULL, "module_clk");
120 clk->rate = clk->parent->rate / (8 << (divisor << 1));
121}
122
123static void cmt_clk_recalc(struct clk *clk)
124{
125 u8 divisor = ctrl_inw(CMT_CMCSR_0) & 0x3;
126 clk->rate = clk->parent->rate / (8 << (divisor << 1));
127}
128
129static struct clk_ops cmt_clk_ops = {
130 .init = cmt_clk_init,
131 .recalc = cmt_clk_recalc,
132};
133
134static struct clk cmt0_clk = {
135 .name = "cmt0_clk",
136 .ops = &cmt_clk_ops,
137};
138
139static int cmt_timer_start(void)
140{
141 ctrl_outw(ctrl_inw(CMT_CMSTR) | 0x01, CMT_CMSTR);
142 return 0;
143}
144
145static int cmt_timer_stop(void)
146{
147 ctrl_outw(ctrl_inw(CMT_CMSTR) & ~0x01, CMT_CMSTR);
148 return 0;
149}
150
151static int cmt_timer_init(void)
152{
153 unsigned long interval;
154
155 cmt_clock_enable();
156
157 setup_irq(CONFIG_SH_TIMER_IRQ, &cmt_irq);
158
159 cmt0_clk.parent = clk_get(NULL, "module_clk");
160
161 cmt_timer_stop();
162
163 interval = cmt0_clk.parent->rate / 8 / HZ;
164 printk(KERN_INFO "Interval = %ld\n", interval);
165
166 ctrl_outw(interval, CMT_CMCOR_0);
167
168 clk_register(&cmt0_clk);
169 clk_enable(&cmt0_clk);
170
171 cmt_timer_start();
172
173 return 0;
174}
175
176static struct sys_timer_ops cmt_timer_ops = {
177 .init = cmt_timer_init,
178 .start = cmt_timer_start,
179 .stop = cmt_timer_stop,
180#ifndef CONFIG_GENERIC_TIME
181 .get_offset = cmt_timer_get_offset,
182#endif
183};
184
185struct sys_timer cmt_timer = {
186 .name = "cmt",
187 .ops = &cmt_timer_ops,
188};
diff --git a/arch/sh/kernel/timers/timer-mtu2.c b/arch/sh/kernel/timers/timer-mtu2.c
deleted file mode 100644
index 9b0ef0126479..000000000000
--- a/arch/sh/kernel/timers/timer-mtu2.c
+++ /dev/null
@@ -1,202 +0,0 @@
1/*
2 * arch/sh/kernel/timers/timer-mtu2.c - MTU2 Timer Support
3 *
4 * Copyright (C) 2005 Paul Mundt
5 *
6 * Based off of arch/sh/kernel/timers/timer-tmu.c
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/seqlock.h>
16#include <asm/timer.h>
17#include <asm/io.h>
18#include <asm/irq.h>
19#include <asm/clock.h>
20
21/*
22 * We use channel 1 for our lowly system timer. Channel 2 would be the other
23 * likely candidate, but we leave it alone as it has higher divisors that
24 * would be of more use to other more interesting applications.
25 *
26 * TODO: Presently we only implement a 16-bit single-channel system timer.
27 * However, we can implement channel cascade if we go the overflow route and
28 * get away with using 2 MTU2 channels as a 32-bit timer.
29 */
30#define MTU2_TSTR 0xfffe4280
31#define MTU2_TCR_1 0xfffe4380
32#define MTU2_TMDR_1 0xfffe4381
33#define MTU2_TIOR_1 0xfffe4382
34#define MTU2_TIER_1 0xfffe4384
35#define MTU2_TSR_1 0xfffe4385
36#define MTU2_TCNT_1 0xfffe4386 /* 16-bit counter */
37
38#if defined(CONFIG_CPU_SUBTYPE_SH7201) || \
39 defined(CONFIG_CPU_SUBTYPE_SH7203)
40#define MTU2_TGRA_1 0xfffe4388
41#else
42#define MTU2_TGRA_1 0xfffe438a
43#endif
44
45#define STBCR3 0xfffe0408
46
47#define MTU2_TSTR_CST1 (1 << 1) /* Counter Start 1 */
48
49#define MTU2_TSR_TGFA (1 << 0) /* GRA compare match */
50
51#define MTU2_TIER_TGIEA (1 << 0) /* GRA compare match interrupt enable */
52
53#define MTU2_TCR_INIT 0x22
54
55#define MTU2_TCR_CALIB 0x00
56
57static unsigned long mtu2_timer_get_offset(void)
58{
59 int count;
60 static int count_p = 0x7fff; /* for the first call after boot */
61 static unsigned long jiffies_p = 0;
62
63 /*
64 * cache volatile jiffies temporarily; we have IRQs turned off.
65 */
66 unsigned long jiffies_t;
67
68 /* timer count may underflow right here */
69 count = ctrl_inw(MTU2_TCNT_1); /* read the latched count */
70
71 jiffies_t = jiffies;
72
73 /*
74 * avoiding timer inconsistencies (they are rare, but they happen)...
75 * there is one kind of problem that must be avoided here:
76 * 1. the timer counter underflows
77 */
78
79 if (jiffies_t == jiffies_p) {
80 if (count > count_p) {
81 if (ctrl_inb(MTU2_TSR_1) & MTU2_TSR_TGFA) {
82 count -= LATCH;
83 } else {
84 printk("%s (): hardware timer problem?\n",
85 __func__);
86 }
87 }
88 } else
89 jiffies_p = jiffies_t;
90
91 count_p = count;
92
93 count = ((LATCH-1) - count) * TICK_SIZE;
94 count = (count + LATCH/2) / LATCH;
95
96 return count;
97}
98
99static irqreturn_t mtu2_timer_interrupt(int irq, void *dev_id)
100{
101 unsigned long timer_status;
102
103 /* Clear TGFA bit */
104 timer_status = ctrl_inb(MTU2_TSR_1);
105 timer_status &= ~MTU2_TSR_TGFA;
106 ctrl_outb(timer_status, MTU2_TSR_1);
107
108 /* Do timer tick */
109 handle_timer_tick();
110
111 return IRQ_HANDLED;
112}
113
114static struct irqaction mtu2_irq = {
115 .name = "timer",
116 .handler = mtu2_timer_interrupt,
117 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
118};
119
120static unsigned int divisors[] = { 1, 4, 16, 64, 1, 1, 256 };
121
122static void mtu2_clk_init(struct clk *clk)
123{
124 u8 idx = MTU2_TCR_INIT & 0x7;
125
126 clk->rate = clk->parent->rate / divisors[idx];
127 /* Start TCNT counting */
128 ctrl_outb(ctrl_inb(MTU2_TSTR) | MTU2_TSTR_CST1, MTU2_TSTR);
129
130}
131
132static void mtu2_clk_recalc(struct clk *clk)
133{
134 u8 idx = ctrl_inb(MTU2_TCR_1) & 0x7;
135 clk->rate = clk->parent->rate / divisors[idx];
136}
137
138static struct clk_ops mtu2_clk_ops = {
139 .init = mtu2_clk_init,
140 .recalc = mtu2_clk_recalc,
141};
142
143static struct clk mtu2_clk1 = {
144 .name = "mtu2_clk1",
145 .ops = &mtu2_clk_ops,
146};
147
148static int mtu2_timer_start(void)
149{
150 ctrl_outb(ctrl_inb(MTU2_TSTR) | MTU2_TSTR_CST1, MTU2_TSTR);
151 return 0;
152}
153
154static int mtu2_timer_stop(void)
155{
156 ctrl_outb(ctrl_inb(MTU2_TSTR) & ~MTU2_TSTR_CST1, MTU2_TSTR);
157 return 0;
158}
159
160static int mtu2_timer_init(void)
161{
162 unsigned long interval;
163
164 setup_irq(CONFIG_SH_TIMER_IRQ, &mtu2_irq);
165
166 mtu2_clk1.parent = clk_get(NULL, "module_clk");
167
168 ctrl_outb(ctrl_inb(STBCR3) & (~0x20), STBCR3);
169
170 /* Normal operation */
171 ctrl_outb(0, MTU2_TMDR_1);
172 ctrl_outb(MTU2_TCR_INIT, MTU2_TCR_1);
173 ctrl_outb(0x01, MTU2_TIOR_1);
174
175 /* Enable underflow interrupt */
176 ctrl_outb(ctrl_inb(MTU2_TIER_1) | MTU2_TIER_TGIEA, MTU2_TIER_1);
177
178 interval = CONFIG_SH_PCLK_FREQ / 16 / HZ;
179 printk(KERN_INFO "Interval = %ld\n", interval);
180
181 ctrl_outw(interval, MTU2_TGRA_1);
182 ctrl_outw(0, MTU2_TCNT_1);
183
184 clk_register(&mtu2_clk1);
185 clk_enable(&mtu2_clk1);
186
187 return 0;
188}
189
190struct sys_timer_ops mtu2_timer_ops = {
191 .init = mtu2_timer_init,
192 .start = mtu2_timer_start,
193 .stop = mtu2_timer_stop,
194#ifndef CONFIG_GENERIC_TIME
195 .get_offset = mtu2_timer_get_offset,
196#endif
197};
198
199struct sys_timer mtu2_timer = {
200 .name = "mtu2",
201 .ops = &mtu2_timer_ops,
202};
diff --git a/arch/sh/kernel/timers/timer-tmu.c b/arch/sh/kernel/timers/timer-tmu.c
deleted file mode 100644
index fe8d8930ccb6..000000000000
--- a/arch/sh/kernel/timers/timer-tmu.c
+++ /dev/null
@@ -1,297 +0,0 @@
1/*
2 * arch/sh/kernel/timers/timer-tmu.c - TMU Timer Support
3 *
4 * Copyright (C) 2005 - 2007 Paul Mundt
5 *
6 * TMU handling code hacked out of arch/sh/kernel/time.c
7 *
8 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
9 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
10 * Copyright (C) 2002, 2003, 2004 Paul Mundt
11 * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
12 *
13 * This file is subject to the terms and conditions of the GNU General Public
14 * License. See the file "COPYING" in the main directory of this archive
15 * for more details.
16 */
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/interrupt.h>
20#include <linux/seqlock.h>
21#include <linux/clockchips.h>
22#include <asm/timer.h>
23#include <asm/rtc.h>
24#include <asm/io.h>
25#include <asm/irq.h>
26#include <asm/clock.h>
27
28#define TMU_TOCR_INIT 0x00
29#define TMU_TCR_INIT 0x0020
30
31#define TMU0 (0)
32#define TMU1 (1)
33
34static inline void _tmu_start(int tmu_num)
35{
36 ctrl_outb(ctrl_inb(TMU_012_TSTR) | (0x1<<tmu_num), TMU_012_TSTR);
37}
38
39static inline void _tmu_set_irq(int tmu_num, int enabled)
40{
41 register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
42 ctrl_outw( (enabled ? ctrl_inw(tmu_tcr) | (1<<5) : ctrl_inw(tmu_tcr) & ~(1<<5)), tmu_tcr);
43}
44
45static inline void _tmu_stop(int tmu_num)
46{
47 ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~(0x1<<tmu_num), TMU_012_TSTR);
48}
49
50static inline void _tmu_clear_status(int tmu_num)
51{
52 register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
53 /* Clear UNF bit */
54 ctrl_outw(ctrl_inw(tmu_tcr) & ~0x100, tmu_tcr);
55}
56
57static inline unsigned long _tmu_read(int tmu_num)
58{
59 return ctrl_inl(TMU0_TCNT+0xC*tmu_num);
60}
61
62static int tmu_timer_start(void)
63{
64 _tmu_start(TMU0);
65 _tmu_start(TMU1);
66 _tmu_set_irq(TMU0,1);
67 return 0;
68}
69
70static int tmu_timer_stop(void)
71{
72 _tmu_stop(TMU0);
73 _tmu_stop(TMU1);
74 _tmu_clear_status(TMU0);
75 return 0;
76}
77
78/*
79 * also when the module_clk is scaled the TMU1
80 * will show the same frequency
81 */
82static int tmus_are_scaled;
83
84static cycle_t tmu_timer_read(struct clocksource *cs)
85{
86 return ((cycle_t)(~_tmu_read(TMU1)))<<tmus_are_scaled;
87}
88
89
90static unsigned long tmu_latest_interval[3];
91static void tmu_timer_set_interval(int tmu_num, unsigned long interval, unsigned int reload)
92{
93 unsigned long tmu_tcnt = TMU0_TCNT + tmu_num*0xC;
94 unsigned long tmu_tcor = TMU0_TCOR + tmu_num*0xC;
95
96 _tmu_stop(tmu_num);
97
98 ctrl_outl(interval, tmu_tcnt);
99 tmu_latest_interval[tmu_num] = interval;
100
101 /*
102 * TCNT reloads from TCOR on underflow, clear it if we don't
103 * intend to auto-reload
104 */
105 ctrl_outl( reload ? interval : 0 , tmu_tcor);
106
107 _tmu_start(tmu_num);
108}
109
110static int tmu_set_next_event(unsigned long cycles,
111 struct clock_event_device *evt)
112{
113 tmu_timer_set_interval(TMU0,cycles, evt->mode == CLOCK_EVT_MODE_PERIODIC);
114 _tmu_set_irq(TMU0,1);
115 return 0;
116}
117
118static void tmu_set_mode(enum clock_event_mode mode,
119 struct clock_event_device *evt)
120{
121 switch (mode) {
122 case CLOCK_EVT_MODE_PERIODIC:
123 ctrl_outl(tmu_latest_interval[TMU0], TMU0_TCOR);
124 break;
125 case CLOCK_EVT_MODE_ONESHOT:
126 ctrl_outl(0, TMU0_TCOR);
127 break;
128 case CLOCK_EVT_MODE_UNUSED:
129 case CLOCK_EVT_MODE_SHUTDOWN:
130 case CLOCK_EVT_MODE_RESUME:
131 break;
132 }
133}
134
135static struct clock_event_device tmu0_clockevent = {
136 .name = "tmu0",
137 .shift = 32,
138 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
139 .set_mode = tmu_set_mode,
140 .set_next_event = tmu_set_next_event,
141};
142
143static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
144{
145 struct clock_event_device *evt = &tmu0_clockevent;
146 _tmu_clear_status(TMU0);
147 _tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT);
148
149 switch (tmu0_clockevent.mode) {
150 case CLOCK_EVT_MODE_ONESHOT:
151 case CLOCK_EVT_MODE_PERIODIC:
152 evt->event_handler(evt);
153 break;
154 default:
155 break;
156 }
157
158 return IRQ_HANDLED;
159}
160
161static struct irqaction tmu0_irq = {
162 .name = "periodic/oneshot timer",
163 .handler = tmu_timer_interrupt,
164 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
165};
166
167static void __init tmu_clk_init(struct clk *clk)
168{
169 u8 divisor = TMU_TCR_INIT & 0x7;
170 int tmu_num = clk->name[3]-'0';
171 ctrl_outw(TMU_TCR_INIT, TMU0_TCR+(tmu_num*0xC));
172 clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
173}
174
175static void tmu_clk_recalc(struct clk *clk)
176{
177 int tmu_num = clk->name[3]-'0';
178 unsigned long prev_rate = clk_get_rate(clk);
179 unsigned long flags;
180 u8 divisor = ctrl_inw(TMU0_TCR+tmu_num*0xC) & 0x7;
181 clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
182
183 if(prev_rate==clk_get_rate(clk))
184 return;
185
186 if(tmu_num)
187 return; /* No more work on TMU1 */
188
189 local_irq_save(flags);
190 tmus_are_scaled = (prev_rate > clk->rate);
191
192 _tmu_stop(TMU0);
193
194 tmu0_clockevent.mult = div_sc(clk->rate, NSEC_PER_SEC,
195 tmu0_clockevent.shift);
196 tmu0_clockevent.max_delta_ns =
197 clockevent_delta2ns(-1, &tmu0_clockevent);
198 tmu0_clockevent.min_delta_ns =
199 clockevent_delta2ns(1, &tmu0_clockevent);
200
201 if (tmus_are_scaled)
202 tmu_latest_interval[TMU0] >>= 1;
203 else
204 tmu_latest_interval[TMU0] <<= 1;
205
206 tmu_timer_set_interval(TMU0,
207 tmu_latest_interval[TMU0],
208 tmu0_clockevent.mode == CLOCK_EVT_MODE_PERIODIC);
209
210 _tmu_start(TMU0);
211
212 local_irq_restore(flags);
213}
214
215static struct clk_ops tmu_clk_ops = {
216 .init = tmu_clk_init,
217 .recalc = tmu_clk_recalc,
218};
219
220static struct clk tmu0_clk = {
221 .name = "tmu0_clk",
222 .ops = &tmu_clk_ops,
223};
224
225static struct clk tmu1_clk = {
226 .name = "tmu1_clk",
227 .ops = &tmu_clk_ops,
228};
229
230static int tmu_timer_init(void)
231{
232 unsigned long interval;
233 unsigned long frequency;
234
235 setup_irq(CONFIG_SH_TIMER_IRQ, &tmu0_irq);
236
237 tmu0_clk.parent = clk_get(NULL, "module_clk");
238 tmu1_clk.parent = clk_get(NULL, "module_clk");
239
240 tmu_timer_stop();
241
242#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
243 !defined(CONFIG_CPU_SUBTYPE_SH7721) && \
244 !defined(CONFIG_CPU_SUBTYPE_SH7760) && \
245 !defined(CONFIG_CPU_SUBTYPE_SH7785) && \
246 !defined(CONFIG_CPU_SUBTYPE_SH7786) && \
247 !defined(CONFIG_CPU_SUBTYPE_SHX3)
248 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
249#endif
250
251 clk_register(&tmu0_clk);
252 clk_register(&tmu1_clk);
253 clk_enable(&tmu0_clk);
254 clk_enable(&tmu1_clk);
255
256 frequency = clk_get_rate(&tmu0_clk);
257 interval = (frequency + HZ / 2) / HZ;
258
259 tmu_timer_set_interval(TMU0,interval, 1);
260 tmu_timer_set_interval(TMU1,~0,1);
261
262 _tmu_start(TMU1);
263
264 clocksource_sh.rating = 200;
265 clocksource_sh.mask = CLOCKSOURCE_MASK(32);
266 clocksource_sh.read = tmu_timer_read;
267 clocksource_sh.shift = 10;
268 clocksource_sh.mult = clocksource_hz2mult(clk_get_rate(&tmu1_clk),
269 clocksource_sh.shift);
270 clocksource_sh.flags = CLOCK_SOURCE_IS_CONTINUOUS;
271 clocksource_register(&clocksource_sh);
272
273 tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC,
274 tmu0_clockevent.shift);
275 tmu0_clockevent.max_delta_ns =
276 clockevent_delta2ns(-1, &tmu0_clockevent);
277 tmu0_clockevent.min_delta_ns =
278 clockevent_delta2ns(1, &tmu0_clockevent);
279
280 tmu0_clockevent.cpumask = cpumask_of(0);
281 tmu0_clockevent.rating = 100;
282
283 clockevents_register_device(&tmu0_clockevent);
284
285 return 0;
286}
287
288static struct sys_timer_ops tmu_timer_ops = {
289 .init = tmu_timer_init,
290 .start = tmu_timer_start,
291 .stop = tmu_timer_stop,
292};
293
294struct sys_timer tmu_timer = {
295 .name = "tmu",
296 .ops = &tmu_timer_ops,
297};
diff --git a/arch/sh/kernel/timers/timer.c b/arch/sh/kernel/timers/timer.c
deleted file mode 100644
index 4e7e747d1b69..000000000000
--- a/arch/sh/kernel/timers/timer.c
+++ /dev/null
@@ -1,55 +0,0 @@
1/*
2 * arch/sh/kernel/timers/timer.c - Common timer code
3 *
4 * Copyright (C) 2005 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/timer.h>
13#include <linux/string.h>
14#include <asm/timer.h>
15
16static struct sys_timer *sys_timers[] = {
17#ifdef CONFIG_SH_TMU
18 &tmu_timer,
19#endif
20#ifdef CONFIG_SH_MTU2
21 &mtu2_timer,
22#endif
23#ifdef CONFIG_SH_CMT
24 &cmt_timer,
25#endif
26 NULL,
27};
28
29static char timer_override[10];
30static int __init timer_setup(char *str)
31{
32 if (str)
33 strlcpy(timer_override, str, sizeof(timer_override));
34 return 1;
35}
36__setup("timer=", timer_setup);
37
38struct sys_timer *get_sys_timer(void)
39{
40 int i;
41
42 for (i = 0; i < ARRAY_SIZE(sys_timers); i++) {
43 struct sys_timer *t = sys_timers[i];
44
45 if (unlikely(!t))
46 break;
47 if (unlikely(timer_override[0]))
48 if ((strcmp(timer_override, t->name) != 0))
49 continue;
50 if (likely(t->ops->init() == 0))
51 return t;
52 }
53
54 return NULL;
55}
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c
index 438f1ebcc453..46348ed07cc3 100644
--- a/arch/sh/kernel/traps.c
+++ b/arch/sh/kernel/traps.c
@@ -22,11 +22,11 @@ static void handle_BUG(struct pt_regs *regs)
22 22
23int is_valid_bugaddr(unsigned long addr) 23int is_valid_bugaddr(unsigned long addr)
24{ 24{
25 unsigned short opcode; 25 insn_size_t opcode;
26 26
27 if (addr < PAGE_OFFSET) 27 if (addr < PAGE_OFFSET)
28 return 0; 28 return 0;
29 if (probe_kernel_address((u16 *)addr, opcode)) 29 if (probe_kernel_address((insn_size_t *)addr, opcode))
30 return 0; 30 return 0;
31 31
32 return opcode == TRAPA_BUG_OPCODE; 32 return opcode == TRAPA_BUG_OPCODE;
@@ -66,7 +66,7 @@ BUILD_TRAP_HANDLER(bug)
66 66
67#ifdef CONFIG_BUG 67#ifdef CONFIG_BUG
68 if (__kernel_text_address(instruction_pointer(regs))) { 68 if (__kernel_text_address(instruction_pointer(regs))) {
69 opcode_t insn = *(opcode_t *)instruction_pointer(regs); 69 insn_size_t insn = *(insn_size_t *)instruction_pointer(regs);
70 if (insn == TRAPA_BUG_OPCODE) 70 if (insn == TRAPA_BUG_OPCODE)
71 handle_BUG(regs); 71 handle_BUG(regs);
72 } 72 }
diff --git a/arch/sh/kernel/traps_32.c b/arch/sh/kernel/traps_32.c
index 30ca9c51e52d..2b772776fcda 100644
--- a/arch/sh/kernel/traps_32.c
+++ b/arch/sh/kernel/traps_32.c
@@ -34,6 +34,7 @@
34# define TRAP_ILLEGAL_SLOT_INST 6 34# define TRAP_ILLEGAL_SLOT_INST 6
35# define TRAP_ADDRESS_ERROR 9 35# define TRAP_ADDRESS_ERROR 9
36# ifdef CONFIG_CPU_SH2A 36# ifdef CONFIG_CPU_SH2A
37# define TRAP_UBC 12
37# define TRAP_FPU_ERROR 13 38# define TRAP_FPU_ERROR 13
38# define TRAP_DIVZERO_ERROR 17 39# define TRAP_DIVZERO_ERROR 17
39# define TRAP_DIVOVF_ERROR 18 40# define TRAP_DIVOVF_ERROR 18
@@ -176,7 +177,7 @@ static struct mem_access user_mem_access = {
176 * (if that instruction is in a branch delay slot) 177 * (if that instruction is in a branch delay slot)
177 * - return 0 if emulation okay, -EFAULT on existential error 178 * - return 0 if emulation okay, -EFAULT on existential error
178 */ 179 */
179static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs, 180static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
180 struct mem_access *ma) 181 struct mem_access *ma)
181{ 182{
182 int ret, index, count; 183 int ret, index, count;
@@ -321,10 +322,10 @@ static int handle_unaligned_ins(opcode_t instruction, struct pt_regs *regs,
321 * - fetches the instruction from PC+2 322 * - fetches the instruction from PC+2
322 */ 323 */
323static inline int handle_delayslot(struct pt_regs *regs, 324static inline int handle_delayslot(struct pt_regs *regs,
324 opcode_t old_instruction, 325 insn_size_t old_instruction,
325 struct mem_access *ma) 326 struct mem_access *ma)
326{ 327{
327 opcode_t instruction; 328 insn_size_t instruction;
328 void __user *addr = (void __user *)(regs->pc + 329 void __user *addr = (void __user *)(regs->pc +
329 instruction_size(old_instruction)); 330 instruction_size(old_instruction));
330 331
@@ -364,7 +365,7 @@ static inline int handle_delayslot(struct pt_regs *regs,
364 365
365static int handle_unaligned_notify_count = 10; 366static int handle_unaligned_notify_count = 10;
366 367
367int handle_unaligned_access(opcode_t instruction, struct pt_regs *regs, 368int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
368 struct mem_access *ma) 369 struct mem_access *ma)
369{ 370{
370 u_int rm; 371 u_int rm;
@@ -522,7 +523,7 @@ asmlinkage void do_address_error(struct pt_regs *regs,
522 unsigned long error_code = 0; 523 unsigned long error_code = 0;
523 mm_segment_t oldfs; 524 mm_segment_t oldfs;
524 siginfo_t info; 525 siginfo_t info;
525 opcode_t instruction; 526 insn_size_t instruction;
526 int tmp; 527 int tmp;
527 528
528 /* Intentional ifdef */ 529 /* Intentional ifdef */
@@ -849,6 +850,10 @@ void __init trap_init(void)
849#endif 850#endif
850#endif 851#endif
851 852
853#ifdef TRAP_UBC
854 set_exception_table_vec(TRAP_UBC, break_point_trap);
855#endif
856
852 /* Setup VBR for boot cpu */ 857 /* Setup VBR for boot cpu */
853 per_cpu_trap_init(); 858 per_cpu_trap_init();
854} 859}
diff --git a/arch/sh/kernel/traps_64.c b/arch/sh/kernel/traps_64.c
index a85831cbf18b..267e5ebbb475 100644
--- a/arch/sh/kernel/traps_64.c
+++ b/arch/sh/kernel/traps_64.c
@@ -370,7 +370,6 @@ static int generate_and_check_address(struct pt_regs *regs,
370 return -1; 370 return -1;
371 } 371 }
372 372
373#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
374 /* Check accessible. For misaligned access in the kernel, assume the 373 /* Check accessible. For misaligned access in the kernel, assume the
375 address is always accessible (and if not, just fault when the 374 address is always accessible (and if not, just fault when the
376 load/store gets done.) */ 375 load/store gets done.) */
@@ -380,18 +379,13 @@ static int generate_and_check_address(struct pt_regs *regs,
380 } 379 }
381 /* Do access_ok check later - it depends on whether it's a load or a store. */ 380 /* Do access_ok check later - it depends on whether it's a load or a store. */
382 } 381 }
383#endif
384 382
385 *address = addr; 383 *address = addr;
386 return 0; 384 return 0;
387} 385}
388 386
389/* Default value as for sh */
390#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
391static int user_mode_unaligned_fixup_count = 10; 387static int user_mode_unaligned_fixup_count = 10;
392static int user_mode_unaligned_fixup_enable = 1; 388static int user_mode_unaligned_fixup_enable = 1;
393#endif
394
395static int kernel_mode_unaligned_fixup_count = 32; 389static int kernel_mode_unaligned_fixup_count = 32;
396 390
397static void misaligned_kernel_word_load(__u64 address, int do_sign_extend, __u64 *result) 391static void misaligned_kernel_word_load(__u64 address, int do_sign_extend, __u64 *result)
@@ -440,7 +434,6 @@ static int misaligned_load(struct pt_regs *regs,
440 } 434 }
441 435
442 destreg = (opcode >> 4) & 0x3f; 436 destreg = (opcode >> 4) & 0x3f;
443#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
444 if (user_mode(regs)) { 437 if (user_mode(regs)) {
445 __u64 buffer; 438 __u64 buffer;
446 439
@@ -470,9 +463,7 @@ static int misaligned_load(struct pt_regs *regs,
470 width_shift, (unsigned long) regs->pc); 463 width_shift, (unsigned long) regs->pc);
471 break; 464 break;
472 } 465 }
473 } else 466 } else {
474#endif
475 {
476 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */ 467 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
477 __u64 lo, hi; 468 __u64 lo, hi;
478 469
@@ -519,7 +510,6 @@ static int misaligned_store(struct pt_regs *regs,
519 } 510 }
520 511
521 srcreg = (opcode >> 4) & 0x3f; 512 srcreg = (opcode >> 4) & 0x3f;
522#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
523 if (user_mode(regs)) { 513 if (user_mode(regs)) {
524 __u64 buffer; 514 __u64 buffer;
525 515
@@ -546,9 +536,7 @@ static int misaligned_store(struct pt_regs *regs,
546 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) { 536 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
547 return -1; /* fault */ 537 return -1; /* fault */
548 } 538 }
549 } else 539 } else {
550#endif
551 {
552 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */ 540 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
553 __u64 val = regs->regs[srcreg]; 541 __u64 val = regs->regs[srcreg];
554 542
@@ -576,7 +564,6 @@ static int misaligned_store(struct pt_regs *regs,
576 564
577} 565}
578 566
579#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
580/* Never need to fix up misaligned FPU accesses within the kernel since that's a real 567/* Never need to fix up misaligned FPU accesses within the kernel since that's a real
581 error. */ 568 error. */
582static int misaligned_fpu_load(struct pt_regs *regs, 569static int misaligned_fpu_load(struct pt_regs *regs,
@@ -727,7 +714,6 @@ static int misaligned_fpu_store(struct pt_regs *regs,
727 return -1; 714 return -1;
728 } 715 }
729} 716}
730#endif
731 717
732static int misaligned_fixup(struct pt_regs *regs) 718static int misaligned_fixup(struct pt_regs *regs)
733{ 719{
@@ -735,12 +721,8 @@ static int misaligned_fixup(struct pt_regs *regs)
735 int error; 721 int error;
736 int major, minor; 722 int major, minor;
737 723
738#if !defined(CONFIG_SH64_USER_MISALIGNED_FIXUP) 724 if (!user_mode_unaligned_fixup_enable)
739 /* Never fixup user mode misaligned accesses without this option enabled. */ 725 return -1;
740 return -1;
741#else
742 if (!user_mode_unaligned_fixup_enable) return -1;
743#endif
744 726
745 error = read_opcode(regs->pc, &opcode, user_mode(regs)); 727 error = read_opcode(regs->pc, &opcode, user_mode(regs));
746 if (error < 0) { 728 if (error < 0) {
@@ -749,15 +731,12 @@ static int misaligned_fixup(struct pt_regs *regs)
749 major = (opcode >> 26) & 0x3f; 731 major = (opcode >> 26) & 0x3f;
750 minor = (opcode >> 16) & 0xf; 732 minor = (opcode >> 16) & 0xf;
751 733
752#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
753 if (user_mode(regs) && (user_mode_unaligned_fixup_count > 0)) { 734 if (user_mode(regs) && (user_mode_unaligned_fixup_count > 0)) {
754 --user_mode_unaligned_fixup_count; 735 --user_mode_unaligned_fixup_count;
755 /* Only do 'count' worth of these reports, to remove a potential DoS against syslog */ 736 /* Only do 'count' worth of these reports, to remove a potential DoS against syslog */
756 printk("Fixing up unaligned userspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n", 737 printk("Fixing up unaligned userspace access in \"%s\" pid=%d pc=0x%08x ins=0x%08lx\n",
757 current->comm, task_pid_nr(current), (__u32)regs->pc, opcode); 738 current->comm, task_pid_nr(current), (__u32)regs->pc, opcode);
758 } else 739 } else if (!user_mode(regs) && (kernel_mode_unaligned_fixup_count > 0)) {
759#endif
760 if (!user_mode(regs) && (kernel_mode_unaligned_fixup_count > 0)) {
761 --kernel_mode_unaligned_fixup_count; 740 --kernel_mode_unaligned_fixup_count;
762 if (in_interrupt()) { 741 if (in_interrupt()) {
763 printk("Fixing up unaligned kernelspace access in interrupt pc=0x%08x ins=0x%08lx\n", 742 printk("Fixing up unaligned kernelspace access in interrupt pc=0x%08x ins=0x%08lx\n",
@@ -830,7 +809,6 @@ static int misaligned_fixup(struct pt_regs *regs)
830 } 809 }
831 break; 810 break;
832 811
833#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
834 case (0x94>>2): /* FLD.S */ 812 case (0x94>>2): /* FLD.S */
835 error = misaligned_fpu_load(regs, opcode, 1, 2, 0); 813 error = misaligned_fpu_load(regs, opcode, 1, 2, 0);
836 break; 814 break;
@@ -881,7 +859,6 @@ static int misaligned_fixup(struct pt_regs *regs)
881 break; 859 break;
882 } 860 }
883 break; 861 break;
884#endif
885 862
886 default: 863 default:
887 /* Fault */ 864 /* Fault */
@@ -907,7 +884,6 @@ static ctl_table unaligned_table[] = {
907 .mode = 0644, 884 .mode = 0644,
908 .proc_handler = &proc_dointvec 885 .proc_handler = &proc_dointvec
909 }, 886 },
910#if defined(CONFIG_SH64_USER_MISALIGNED_FIXUP)
911 { 887 {
912 .ctl_name = CTL_UNNUMBERED, 888 .ctl_name = CTL_UNNUMBERED,
913 .procname = "user_reports", 889 .procname = "user_reports",
@@ -923,7 +899,6 @@ static ctl_table unaligned_table[] = {
923 .maxlen = sizeof(int), 899 .maxlen = sizeof(int),
924 .mode = 0644, 900 .mode = 0644,
925 .proc_handler = &proc_dointvec}, 901 .proc_handler = &proc_dointvec},
926#endif
927 {} 902 {}
928}; 903};
929 904
diff --git a/arch/sh/kernel/vmlinux.lds.S b/arch/sh/kernel/vmlinux.lds.S
index d7d4991f32af..f53c76acaede 100644
--- a/arch/sh/kernel/vmlinux.lds.S
+++ b/arch/sh/kernel/vmlinux.lds.S
@@ -1,5 +1,178 @@
1#ifdef CONFIG_SUPERH32 1/*
2# include "vmlinux_32.lds.S" 2 * ld script to make SuperH Linux kernel
3 * Written by Niibe Yutaka and Paul Mundt
4 */
5#ifdef CONFIG_SUPERH64
6#define LOAD_OFFSET CONFIG_PAGE_OFFSET
7OUTPUT_ARCH(sh:sh5)
3#else 8#else
4# include "vmlinux_64.lds.S" 9#define LOAD_OFFSET 0
10OUTPUT_ARCH(sh)
5#endif 11#endif
12
13#include <asm/thread_info.h>
14#include <asm/cache.h>
15#include <asm-generic/vmlinux.lds.h>
16
17ENTRY(_start)
18SECTIONS
19{
20#ifdef CONFIG_PMB_FIXED
21 . = CONFIG_PAGE_OFFSET + (CONFIG_MEMORY_START & 0x1fffffff) +
22 CONFIG_ZERO_PAGE_OFFSET;
23#elif defined(CONFIG_32BIT)
24 . = CONFIG_PAGE_OFFSET + CONFIG_ZERO_PAGE_OFFSET;
25#else
26 . = CONFIG_PAGE_OFFSET + CONFIG_MEMORY_START + CONFIG_ZERO_PAGE_OFFSET;
27#endif
28
29 _text = .; /* Text and read-only data */
30
31 .empty_zero_page : AT(ADDR(.empty_zero_page) - LOAD_OFFSET) {
32 *(.empty_zero_page)
33 } = 0
34
35 .text : AT(ADDR(.text) - LOAD_OFFSET) {
36 HEAD_TEXT
37 TEXT_TEXT
38
39#ifdef CONFIG_SUPERH64
40 *(.text64)
41 *(.text..SHmedia32)
42#endif
43
44 SCHED_TEXT
45 LOCK_TEXT
46 KPROBES_TEXT
47 IRQENTRY_TEXT
48 *(.fixup)
49 *(.gnu.warning)
50 _etext = .; /* End of text section */
51 } = 0x0009
52
53 . = ALIGN(16); /* Exception table */
54 __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) {
55 __start___ex_table = .;
56 *(__ex_table)
57 __stop___ex_table = .;
58 }
59
60 NOTES
61 RO_DATA(PAGE_SIZE)
62
63 /*
64 * Code which must be executed uncached and the associated data
65 */
66 . = ALIGN(PAGE_SIZE);
67 .uncached : AT(ADDR(.uncached) - LOAD_OFFSET) {
68 __uncached_start = .;
69 *(.uncached.text)
70 *(.uncached.data)
71 __uncached_end = .;
72 }
73
74 . = ALIGN(THREAD_SIZE);
75 .data : AT(ADDR(.data) - LOAD_OFFSET) { /* Data */
76 *(.data.init_task)
77
78 . = ALIGN(L1_CACHE_BYTES);
79 *(.data.cacheline_aligned)
80
81 . = ALIGN(L1_CACHE_BYTES);
82 *(.data.read_mostly)
83
84 . = ALIGN(PAGE_SIZE);
85 *(.data.page_aligned)
86
87 __nosave_begin = .;
88 *(.data.nosave)
89 . = ALIGN(PAGE_SIZE);
90 __nosave_end = .;
91
92 DATA_DATA
93 CONSTRUCTORS
94 }
95
96 _edata = .; /* End of data section */
97
98 . = ALIGN(PAGE_SIZE); /* Init code and data */
99 .init.text : AT(ADDR(.init.text) - LOAD_OFFSET) {
100 __init_begin = .;
101 _sinittext = .;
102 INIT_TEXT
103 _einittext = .;
104 }
105
106 .init.data : AT(ADDR(.init.data) - LOAD_OFFSET) { INIT_DATA }
107
108 . = ALIGN(16);
109 .init.setup : AT(ADDR(.init.setup) - LOAD_OFFSET) {
110 __setup_start = .;
111 *(.init.setup)
112 __setup_end = .;
113 }
114
115 .initcall.init : AT(ADDR(.initcall.init) - LOAD_OFFSET) {
116 __initcall_start = .;
117 INITCALLS
118 __initcall_end = .;
119 }
120
121 .con_initcall.init : AT(ADDR(.con_initcall.init) - LOAD_OFFSET) {
122 __con_initcall_start = .;
123 *(.con_initcall.init)
124 __con_initcall_end = .;
125 }
126
127 SECURITY_INIT
128
129#ifdef CONFIG_BLK_DEV_INITRD
130 . = ALIGN(PAGE_SIZE);
131 .init.ramfs : AT(ADDR(.init.ramfs) - LOAD_OFFSET) {
132 __initramfs_start = .;
133 *(.init.ramfs)
134 __initramfs_end = .;
135 }
136#endif
137
138 . = ALIGN(4);
139 .machvec.init : AT(ADDR(.machvec.init) - LOAD_OFFSET) {
140 __machvec_start = .;
141 *(.machvec.init)
142 __machvec_end = .;
143 }
144
145 PERCPU(PAGE_SIZE)
146
147 /*
148 * .exit.text is discarded at runtime, not link time, to deal with
149 * references from __bug_table
150 */
151 .exit.text : AT(ADDR(.exit.text) - LOAD_OFFSET) { EXIT_TEXT }
152 .exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) { EXIT_DATA }
153
154 . = ALIGN(PAGE_SIZE);
155 .bss : AT(ADDR(.bss) - LOAD_OFFSET) {
156 __init_end = .;
157 __bss_start = .; /* BSS */
158 *(.bss.page_aligned)
159 *(.bss)
160 *(COMMON)
161 . = ALIGN(4);
162 _ebss = .; /* uClinux MTD sucks */
163 _end = . ;
164 }
165
166 /*
167 * When something in the kernel is NOT compiled as a module, the
168 * module cleanup code and data are put into these segments. Both
169 * can then be thrown away, as cleanup code is never called unless
170 * it's a module.
171 */
172 /DISCARD/ : {
173 *(.exitcall.exit)
174 }
175
176 STABS_DEBUG
177 DWARF_DEBUG
178}
diff --git a/arch/sh/kernel/vmlinux_32.lds.S b/arch/sh/kernel/vmlinux_32.lds.S
deleted file mode 100644
index dd9b2ee1312d..000000000000
--- a/arch/sh/kernel/vmlinux_32.lds.S
+++ /dev/null
@@ -1,154 +0,0 @@
1/*
2 * ld script to make SuperH Linux kernel
3 * Written by Niibe Yutaka
4 */
5#include <asm/thread_info.h>
6#include <asm/cache.h>
7#include <asm-generic/vmlinux.lds.h>
8
9#ifdef CONFIG_CPU_LITTLE_ENDIAN
10OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
11#else
12OUTPUT_FORMAT("elf32-shbig-linux", "elf32-shbig-linux", "elf32-shbig-linux")
13#endif
14OUTPUT_ARCH(sh)
15ENTRY(_start)
16SECTIONS
17{
18#ifdef CONFIG_PMB_FIXED
19 . = CONFIG_PAGE_OFFSET + (CONFIG_MEMORY_START & 0x1fffffff) +
20 CONFIG_ZERO_PAGE_OFFSET;
21#elif defined(CONFIG_32BIT)
22 . = CONFIG_PAGE_OFFSET + CONFIG_ZERO_PAGE_OFFSET;
23#else
24 . = CONFIG_PAGE_OFFSET + CONFIG_MEMORY_START + CONFIG_ZERO_PAGE_OFFSET;
25#endif
26
27 _text = .; /* Text and read-only data */
28
29 .empty_zero_page : {
30 *(.empty_zero_page)
31 } = 0
32
33 .text : {
34 HEAD_TEXT
35 TEXT_TEXT
36 SCHED_TEXT
37 LOCK_TEXT
38 KPROBES_TEXT
39 *(.fixup)
40 *(.gnu.warning)
41 } = 0x0009
42
43 . = ALIGN(16); /* Exception table */
44 __start___ex_table = .;
45 __ex_table : { *(__ex_table) }
46 __stop___ex_table = .;
47
48 _etext = .; /* End of text section */
49
50 NOTES
51 RO_DATA(PAGE_SIZE)
52
53 /*
54 * Code which must be executed uncached and the associated data
55 */
56 . = ALIGN(PAGE_SIZE);
57 __uncached_start = .;
58 .uncached.text : { *(.uncached.text) }
59 .uncached.data : { *(.uncached.data) }
60 __uncached_end = .;
61
62 . = ALIGN(THREAD_SIZE);
63 .data : { /* Data */
64 *(.data.init_task)
65
66 . = ALIGN(L1_CACHE_BYTES);
67 *(.data.cacheline_aligned)
68
69 . = ALIGN(L1_CACHE_BYTES);
70 *(.data.read_mostly)
71
72 . = ALIGN(PAGE_SIZE);
73 *(.data.page_aligned)
74
75 __nosave_begin = .;
76 *(.data.nosave)
77 . = ALIGN(PAGE_SIZE);
78 __nosave_end = .;
79
80 DATA_DATA
81 CONSTRUCTORS
82 }
83
84 _edata = .; /* End of data section */
85
86 . = ALIGN(PAGE_SIZE); /* Init code and data */
87 __init_begin = .;
88 _sinittext = .;
89 .init.text : { INIT_TEXT }
90 _einittext = .;
91 .init.data : { INIT_DATA }
92
93 . = ALIGN(16);
94 __setup_start = .;
95 .init.setup : { *(.init.setup) }
96 __setup_end = .;
97
98 __initcall_start = .;
99 .initcall.init : {
100 INITCALLS
101 }
102 __initcall_end = .;
103 __con_initcall_start = .;
104 .con_initcall.init : { *(.con_initcall.init) }
105 __con_initcall_end = .;
106
107 SECURITY_INIT
108
109#ifdef CONFIG_BLK_DEV_INITRD
110 . = ALIGN(PAGE_SIZE);
111 __initramfs_start = .;
112 .init.ramfs : { *(.init.ramfs) }
113 __initramfs_end = .;
114#endif
115
116 . = ALIGN(4);
117 __machvec_start = .;
118 .machvec.init : { *(.machvec.init) }
119 __machvec_end = .;
120
121 PERCPU(PAGE_SIZE)
122
123 /*
124 * .exit.text is discarded at runtime, not link time, to deal with
125 * references from __bug_table
126 */
127 .exit.text : { EXIT_TEXT }
128 .exit.data : { EXIT_DATA }
129
130 . = ALIGN(PAGE_SIZE);
131 .bss : {
132 __init_end = .;
133 __bss_start = .; /* BSS */
134 *(.bss.page_aligned)
135 *(.bss)
136 *(COMMON)
137 . = ALIGN(4);
138 _ebss = .; /* uClinux MTD sucks */
139 _end = . ;
140 }
141
142 /*
143 * When something in the kernel is NOT compiled as a module, the
144 * module cleanup code and data are put into these segments. Both
145 * can then be thrown away, as cleanup code is never called unless
146 * it's a module.
147 */
148 /DISCARD/ : {
149 *(.exitcall.exit)
150 }
151
152 STABS_DEBUG
153 DWARF_DEBUG
154}
diff --git a/arch/sh/kernel/vmlinux_64.lds.S b/arch/sh/kernel/vmlinux_64.lds.S
deleted file mode 100644
index 69664460c688..000000000000
--- a/arch/sh/kernel/vmlinux_64.lds.S
+++ /dev/null
@@ -1,163 +0,0 @@
1/*
2 * ld script to make SH64 Linux kernel
3 *
4 * Copyright (C) 2000, 2001 Paolo Alberelli
5 *
6 * benedict.gaster@superh.com: 2nd May 2002
7 * Add definition of empty_zero_page to be the first page of kernel image.
8 *
9 * benedict.gaster@superh.com: 3rd May 2002
10 * Added support for ramdisk, removing statically linked romfs at the
11 * same time.
12 *
13 * lethal@linux-sh.org: 9th May 2003
14 * Kill off GLOBAL_NAME() usage and other CDC-isms.
15 *
16 * lethal@linux-sh.org: 19th May 2003
17 * Remove support for ancient toolchains.
18 *
19 * This file is subject to the terms and conditions of the GNU General Public
20 * License. See the file "COPYING" in the main directory of this archive
21 * for more details.
22 */
23#include <asm/page.h>
24#include <asm/cache.h>
25#include <asm/thread_info.h>
26
27#define LOAD_OFFSET CONFIG_PAGE_OFFSET
28#include <asm-generic/vmlinux.lds.h>
29
30OUTPUT_ARCH(sh:sh5)
31
32#define C_PHYS(x) AT (ADDR(x) - LOAD_OFFSET)
33
34ENTRY(__start)
35SECTIONS
36{
37 . = CONFIG_PAGE_OFFSET + CONFIG_MEMORY_START + PAGE_SIZE;
38 _text = .; /* Text and read-only data */
39
40 .empty_zero_page : C_PHYS(.empty_zero_page) {
41 *(.empty_zero_page)
42 } = 0
43
44 .text : C_PHYS(.text) {
45 HEAD_TEXT
46 TEXT_TEXT
47 *(.text64)
48 *(.text..SHmedia32)
49 SCHED_TEXT
50 LOCK_TEXT
51 KPROBES_TEXT
52 *(.fixup)
53 *(.gnu.warning)
54#ifdef CONFIG_CPU_LITTLE_ENDIAN
55 } = 0x6ff0fff0
56#else
57 } = 0xf0fff06f
58#endif
59
60 /* We likely want __ex_table to be Cache Line aligned */
61 . = ALIGN(L1_CACHE_BYTES); /* Exception table */
62 __start___ex_table = .;
63 __ex_table : C_PHYS(__ex_table) { *(__ex_table) }
64 __stop___ex_table = .;
65
66 _etext = .; /* End of text section */
67
68 NOTES
69 RO_DATA(PAGE_SIZE)
70
71 . = ALIGN(THREAD_SIZE);
72 .data : C_PHYS(.data) { /* Data */
73 *(.data.init_task)
74
75 . = ALIGN(L1_CACHE_BYTES);
76 *(.data.cacheline_aligned)
77
78 . = ALIGN(L1_CACHE_BYTES);
79 *(.data.read_mostly)
80
81 . = ALIGN(PAGE_SIZE);
82 *(.data.page_aligned)
83
84 __nosave_begin = .;
85 *(.data.nosave)
86 . = ALIGN(PAGE_SIZE);
87 __nosave_end = .;
88
89 DATA_DATA
90 CONSTRUCTORS
91 }
92
93 _edata = .; /* End of data section */
94
95 . = ALIGN(PAGE_SIZE); /* Init code and data */
96 __init_begin = .;
97 _sinittext = .;
98 .init.text : C_PHYS(.init.text) { INIT_TEXT }
99 _einittext = .;
100 .init.data : C_PHYS(.init.data) { INIT_DATA }
101 . = ALIGN(L1_CACHE_BYTES); /* Better if Cache Line aligned */
102 __setup_start = .;
103 .init.setup : C_PHYS(.init.setup) { *(.init.setup) }
104 __setup_end = .;
105 __initcall_start = .;
106 .initcall.init : C_PHYS(.initcall.init) {
107 INITCALLS
108 }
109 __initcall_end = .;
110 __con_initcall_start = .;
111 .con_initcall.init : C_PHYS(.con_initcall.init) {
112 *(.con_initcall.init)
113 }
114 __con_initcall_end = .;
115
116 SECURITY_INIT
117
118#ifdef CONFIG_BLK_DEV_INITRD
119 . = ALIGN(PAGE_SIZE);
120 __initramfs_start = .;
121 .init.ramfs : C_PHYS(.init.ramfs) { *(.init.ramfs) }
122 __initramfs_end = .;
123#endif
124
125 . = ALIGN(8);
126 __machvec_start = .;
127 .machvec.init : C_PHYS(.machvec.init) { *(.machvec.init) }
128 __machvec_end = .;
129
130 PERCPU(PAGE_SIZE)
131
132 /*
133 * .exit.text is discarded at runtime, not link time, to deal with
134 * references from __bug_table
135 */
136 .exit.text : C_PHYS(.exit.text) { EXIT_TEXT }
137 .exit.data : C_PHYS(.exit.data) { EXIT_DATA }
138
139 . = ALIGN(PAGE_SIZE);
140 .bss : C_PHYS(.bss) {
141 __init_end = .;
142 __bss_start = .; /* BSS */
143 *(.bss.page_aligned)
144 *(.bss)
145 *(COMMON)
146 . = ALIGN(4);
147 _ebss = .; /* uClinux MTD sucks */
148 _end = . ;
149 }
150
151 /*
152 * When something in the kernel is NOT compiled as a module, the
153 * module cleanup code and data are put into these segments. Both
154 * can then be thrown away, as cleanup code is never called unless
155 * it's a module.
156 */
157 /DISCARD/ : {
158 *(.exitcall.exit)
159 }
160
161 STABS_DEBUG
162 DWARF_DEBUG
163}
diff --git a/arch/sh/lib64/.gitignore b/arch/sh/lib64/.gitignore
deleted file mode 100644
index 3508c2cb23c4..000000000000
--- a/arch/sh/lib64/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
1syscalltab.h
diff --git a/arch/sh/lib64/dbg.c b/arch/sh/lib64/dbg.c
index 2fb8eaf6de60..6152a6a6d9c6 100644
--- a/arch/sh/lib64/dbg.c
+++ b/arch/sh/lib64/dbg.c
@@ -135,140 +135,6 @@ void print_itlb(void)
135 (" =============================================================\n"); 135 (" =============================================================\n");
136} 136}
137 137
138/* ======================================================================= */
139
140#ifdef CONFIG_POOR_MANS_STRACE
141
142#include "syscalltab.h"
143
144struct ring_node {
145 int evt;
146 int ret_addr;
147 int event;
148 int tra;
149 int pid;
150 unsigned long sp;
151 unsigned long pc;
152};
153
154static struct ring_node event_ring[16];
155static int event_ptr = 0;
156
157struct stored_syscall_data {
158 int pid;
159 int syscall_number;
160};
161
162#define N_STORED_SYSCALLS 16
163
164static struct stored_syscall_data stored_syscalls[N_STORED_SYSCALLS];
165static int syscall_next=0;
166static int syscall_next_print=0;
167
168void evt_debug(int evt, int ret_addr, int event, int tra, struct pt_regs *regs)
169{
170 int syscallno = tra & 0xff;
171 unsigned long sp;
172 unsigned long stack_bottom;
173 int pid;
174 struct ring_node *rr;
175
176 pid = current->pid;
177 stack_bottom = (unsigned long) task_stack_page(current);
178 asm volatile("ori r15, 0, %0" : "=r" (sp));
179 rr = event_ring + event_ptr;
180 rr->evt = evt;
181 rr->ret_addr = ret_addr;
182 rr->event = event;
183 rr->tra = tra;
184 rr->pid = pid;
185 rr->sp = sp;
186 rr->pc = regs->pc;
187
188 if (sp < stack_bottom + 3092) {
189 int i, j;
190 printk("evt_debug : stack underflow report\n");
191 for (j=0, i = event_ptr; j<16; j++) {
192 rr = event_ring + i;
193 printk("evt=%08x event=%08x tra=%08x pid=%5d sp=%08lx pc=%08lx\n",
194 rr->evt, rr->event, rr->tra, rr->pid, rr->sp, rr->pc);
195 i--;
196 i &= 15;
197 }
198 panic("STACK UNDERFLOW\n");
199 }
200
201 event_ptr = (event_ptr + 1) & 15;
202
203 if ((event == 2) && (evt == 0x160)) {
204 if (syscallno < NUM_SYSCALL_INFO_ENTRIES) {
205 /* Store the syscall information to print later. We
206 * can't print this now - currently we're running with
207 * SR.BL=1, so we can't take a tlbmiss (which could occur
208 * in the console drivers under printk).
209 *
210 * Just overwrite old entries on ring overflow - this
211 * is only for last-hope debugging. */
212 stored_syscalls[syscall_next].pid = current->pid;
213 stored_syscalls[syscall_next].syscall_number = syscallno;
214 syscall_next++;
215 syscall_next &= (N_STORED_SYSCALLS - 1);
216 }
217 }
218}
219
220static void drain_syscalls(void) {
221 while (syscall_next_print != syscall_next) {
222 printk("Task %d: %s()\n",
223 stored_syscalls[syscall_next_print].pid,
224 syscall_info_table[stored_syscalls[syscall_next_print].syscall_number].name);
225 syscall_next_print++;
226 syscall_next_print &= (N_STORED_SYSCALLS - 1);
227 }
228}
229
230void evt_debug2(unsigned int ret)
231{
232 drain_syscalls();
233 printk("Task %d: syscall returns %08x\n", current->pid, ret);
234}
235
236void evt_debug_ret_from_irq(struct pt_regs *regs)
237{
238 int pid;
239 struct ring_node *rr;
240
241 pid = current->pid;
242 rr = event_ring + event_ptr;
243 rr->evt = 0xffff;
244 rr->ret_addr = 0;
245 rr->event = 0;
246 rr->tra = 0;
247 rr->pid = pid;
248 rr->pc = regs->pc;
249 event_ptr = (event_ptr + 1) & 15;
250}
251
252void evt_debug_ret_from_exc(struct pt_regs *regs)
253{
254 int pid;
255 struct ring_node *rr;
256
257 pid = current->pid;
258 rr = event_ring + event_ptr;
259 rr->evt = 0xfffe;
260 rr->ret_addr = 0;
261 rr->event = 0;
262 rr->tra = 0;
263 rr->pid = pid;
264 rr->pc = regs->pc;
265 event_ptr = (event_ptr + 1) & 15;
266}
267
268#endif /* CONFIG_POOR_MANS_STRACE */
269
270/* ======================================================================= */
271
272void show_excp_regs(char *from, int trapnr, int signr, struct pt_regs *regs) 138void show_excp_regs(char *from, int trapnr, int signr, struct pt_regs *regs)
273{ 139{
274 140
@@ -380,51 +246,3 @@ void show_excp_regs(char *from, int trapnr, int signr, struct pt_regs *regs)
380 print_dtlb(); 246 print_dtlb();
381 print_itlb(); 247 print_itlb();
382} 248}
383
384/* ======================================================================= */
385
386/*
387** Depending on <base> scan the MMU, Data or Instruction side
388** looking for a valid mapping matching Eaddr & asid.
389** Return -1 if not found or the TLB id entry otherwise.
390** Note: it works only for 4k pages!
391*/
392static unsigned long
393lookup_mmu_side(unsigned long base, unsigned long Eaddr, unsigned long asid)
394{
395 regType_t pteH;
396 unsigned long epn;
397 int count;
398
399 epn = Eaddr & 0xfffff000;
400
401 for (count = 0; count < MAX_TLBs; count++, base += TLB_STEP) {
402 pteH = getConfigReg(base);
403 if (GET_VALID(pteH))
404 if ((unsigned long) GET_EPN(pteH) == epn)
405 if ((unsigned long) GET_ASID(pteH) == asid)
406 break;
407 }
408 return ((unsigned long) ((count < MAX_TLBs) ? base : -1));
409}
410
411unsigned long lookup_dtlb(unsigned long Eaddr)
412{
413 unsigned long asid = get_asid();
414 return (lookup_mmu_side((u64) DTLB_BASE, Eaddr, asid));
415}
416
417unsigned long lookup_itlb(unsigned long Eaddr)
418{
419 unsigned long asid = get_asid();
420 return (lookup_mmu_side((u64) ITLB_BASE, Eaddr, asid));
421}
422
423void print_page(struct page *page)
424{
425 printk(" page[%p] -> index 0x%lx, count 0x%x, flags 0x%lx\n",
426 page, page->index, page_count(page), page->flags);
427 printk(" address_space = %p, pages =%ld\n", page->mapping,
428 page->mapping->nrpages);
429
430}
diff --git a/arch/sh/lib64/panic.c b/arch/sh/lib64/panic.c
index da32ba7b5fcc..38c954e04f6a 100644
--- a/arch/sh/lib64/panic.c
+++ b/arch/sh/lib64/panic.c
@@ -6,53 +6,10 @@
6 * for more details. 6 * for more details.
7 */ 7 */
8 8
9#include <linux/kernel.h>
10#include <asm/io.h>
11#include <cpu/registers.h>
12
13/* THIS IS A PHYSICAL ADDRESS */
14#define HDSP2534_ADDR (0x04002100)
15
16#ifdef CONFIG_SH_CAYMAN
17
18static void poor_mans_delay(void)
19{
20 int i;
21 for (i = 0; i < 2500000; i++) {
22 } /* poor man's delay */
23}
24
25static void show_value(unsigned long x)
26{
27 int i;
28 unsigned nibble;
29 for (i = 0; i < 8; i++) {
30 nibble = ((x >> (i * 4)) & 0xf);
31
32 ctrl_outb(nibble + ((nibble > 9) ? 55 : 48),
33 HDSP2534_ADDR + 0xe0 + ((7 - i) << 2));
34 }
35}
36
37#endif
38
39void 9void
40panic_handler(unsigned long panicPC, unsigned long panicSSR, 10panic_handler(unsigned long panicPC, unsigned long panicSSR,
41 unsigned long panicEXPEVT) 11 unsigned long panicEXPEVT)
42{ 12{
43#ifdef CONFIG_SH_CAYMAN
44 while (1) {
45 /* This piece of code displays the PC on the LED display */
46 show_value(panicPC);
47 poor_mans_delay();
48 show_value(panicSSR);
49 poor_mans_delay();
50 show_value(panicEXPEVT);
51 poor_mans_delay();
52 }
53#endif
54
55 /* Never return from the panic handler */ 13 /* Never return from the panic handler */
56 for (;;) ; 14 for (;;) ;
57
58} 15}
diff --git a/arch/sh/lib64/sdivsi3.S b/arch/sh/lib64/sdivsi3.S
index 6a800c6a4904..1963bbd42288 100644
--- a/arch/sh/lib64/sdivsi3.S
+++ b/arch/sh/lib64/sdivsi3.S
@@ -1,4 +1,6 @@
1 .global __sdivsi3 1 .global __sdivsi3
2 .global __sdivsi3_1
3 .global __sdivsi3_2
2 .section .text..SHmedia32,"ax" 4 .section .text..SHmedia32,"ax"
3 .align 2 5 .align 2
4 6
@@ -6,13 +8,15 @@
6 /* clobbered: r1,r18,r19,r20,r21,r25,tr0 */ 8 /* clobbered: r1,r18,r19,r20,r21,r25,tr0 */
7 /* result in r0 */ 9 /* result in r0 */
8__sdivsi3: 10__sdivsi3:
11__sdivsi3_1:
9 ptb __div_table,tr0 12 ptb __div_table,tr0
13 gettr tr0,r20
10 14
15__sdivsi3_2:
11 nsb r5, r1 16 nsb r5, r1
12 shlld r5, r1, r25 /* normalize; [-2 ..1, 1..2) in s2.62 */ 17 shlld r5, r1, r25 /* normalize; [-2 ..1, 1..2) in s2.62 */
13 shari r25, 58, r21 /* extract 5(6) bit index (s2.4 with hole -1..1) */ 18 shari r25, 58, r21 /* extract 5(6) bit index (s2.4 with hole -1..1) */
14 /* bubble */ 19 /* bubble */
15 gettr tr0,r20
16 ldx.ub r20, r21, r19 /* u0.8 */ 20 ldx.ub r20, r21, r19 /* u0.8 */
17 shari r25, 32, r25 /* normalize to s2.30 */ 21 shari r25, 32, r25 /* normalize to s2.30 */
18 shlli r21, 1, r21 22 shlli r21, 1, r21
diff --git a/arch/sh/lib64/udelay.c b/arch/sh/lib64/udelay.c
index d76bd801194f..f215b063da70 100644
--- a/arch/sh/lib64/udelay.c
+++ b/arch/sh/lib64/udelay.c
@@ -33,7 +33,7 @@ void __delay(unsigned long loops)
33 :"0"(loops)); 33 :"0"(loops));
34} 34}
35 35
36inline void __const_udelay(unsigned long xloops) 36void __const_udelay(unsigned long xloops)
37{ 37{
38 __delay(xloops * (HZ * cpu_data[raw_smp_processor_id()].loops_per_jiffy)); 38 __delay(xloops * (HZ * cpu_data[raw_smp_processor_id()].loops_per_jiffy));
39} 39}
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index d4079cab2d58..2795618e4f07 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -21,6 +21,29 @@ config PAGE_OFFSET
21 default "0x20000000" if MMU && SUPERH64 21 default "0x20000000" if MMU && SUPERH64
22 default "0x00000000" 22 default "0x00000000"
23 23
24config FORCE_MAX_ZONEORDER
25 int "Maximum zone order"
26 range 9 64 if PAGE_SIZE_16KB
27 default "9" if PAGE_SIZE_16KB
28 range 7 64 if PAGE_SIZE_64KB
29 default "7" if PAGE_SIZE_64KB
30 range 11 64
31 default "14" if !MMU
32 default "11"
33 help
34 The kernel memory allocator divides physically contiguous memory
35 blocks into "zones", where each zone is a power of two number of
36 pages. This option selects the largest power of two that the kernel
37 keeps in the memory allocator. If you need to allocate very large
38 blocks of physically contiguous memory, then you may need to
39 increase this value.
40
41 This config option is actually maximum order plus one. For example,
42 a value of 11 means that the largest free memory block is 2^10 pages.
43
44 The page size is not necessarily 4KB. Keep this in mind when
45 choosing a value for this option.
46
24config MEMORY_START 47config MEMORY_START
25 hex "Physical memory start address" 48 hex "Physical memory start address"
26 default "0x08000000" 49 default "0x08000000"
@@ -201,14 +224,6 @@ config PAGE_SIZE_64KB
201 224
202endchoice 225endchoice
203 226
204config ENTRY_OFFSET
205 hex
206 default "0x00001000" if PAGE_SIZE_4KB
207 default "0x00002000" if PAGE_SIZE_8KB
208 default "0x00004000" if PAGE_SIZE_16KB
209 default "0x00010000" if PAGE_SIZE_64KB
210 default "0x00000000"
211
212choice 227choice
213 prompt "HugeTLB page size" 228 prompt "HugeTLB page size"
214 depends on HUGETLB_PAGE && (CPU_SH4 || CPU_SH5) && MMU 229 depends on HUGETLB_PAGE && (CPU_SH4 || CPU_SH5) && MMU
diff --git a/arch/sh/mm/cache-sh5.c b/arch/sh/mm/cache-sh5.c
index 9e277ec7d536..86762092508c 100644
--- a/arch/sh/mm/cache-sh5.c
+++ b/arch/sh/mm/cache-sh5.c
@@ -60,7 +60,7 @@ static inline void sh64_teardown_dtlb_cache_slot(void)
60static inline void sh64_icache_inv_all(void) 60static inline void sh64_icache_inv_all(void)
61{ 61{
62 unsigned long long addr, flag, data; 62 unsigned long long addr, flag, data;
63 unsigned int flags; 63 unsigned long flags;
64 64
65 addr = ICCR0; 65 addr = ICCR0;
66 flag = ICCR0_ICI; 66 flag = ICCR0_ICI;
@@ -172,7 +172,7 @@ static void sh64_icache_inv_user_page_range(struct mm_struct *mm,
172 unsigned long eaddr; 172 unsigned long eaddr;
173 unsigned long after_last_page_start; 173 unsigned long after_last_page_start;
174 unsigned long mm_asid, current_asid; 174 unsigned long mm_asid, current_asid;
175 unsigned long long flags = 0ULL; 175 unsigned long flags = 0;
176 176
177 mm_asid = cpu_asid(smp_processor_id(), mm); 177 mm_asid = cpu_asid(smp_processor_id(), mm);
178 current_asid = get_asid(); 178 current_asid = get_asid();
@@ -236,7 +236,7 @@ static void sh64_icache_inv_user_small_range(struct mm_struct *mm,
236 unsigned long long eaddr = start; 236 unsigned long long eaddr = start;
237 unsigned long long eaddr_end = start + len; 237 unsigned long long eaddr_end = start + len;
238 unsigned long current_asid, mm_asid; 238 unsigned long current_asid, mm_asid;
239 unsigned long long flags; 239 unsigned long flags;
240 unsigned long long epage_start; 240 unsigned long long epage_start;
241 241
242 /* 242 /*
@@ -342,7 +342,7 @@ static void inline sh64_dcache_purge_sets(int sets_to_purge_base, int n_sets)
342 * alloco is a NOP if the cache is write-through. 342 * alloco is a NOP if the cache is write-through.
343 */ 343 */
344 if (test_bit(SH_CACHE_MODE_WT, &(cpu_data->dcache.flags))) 344 if (test_bit(SH_CACHE_MODE_WT, &(cpu_data->dcache.flags)))
345 ctrl_inb(eaddr); 345 __raw_readb((unsigned long)eaddr);
346 } 346 }
347 } 347 }
348 348
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index 3edf297c829b..ee8e6bbe882c 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -184,7 +184,6 @@ void __init paging_init(void)
184} 184}
185 185
186static struct kcore_list kcore_mem, kcore_vmalloc; 186static struct kcore_list kcore_mem, kcore_vmalloc;
187int after_bootmem = 0;
188 187
189void __init mem_init(void) 188void __init mem_init(void)
190{ 189{
@@ -217,8 +216,6 @@ void __init mem_init(void)
217 memset(empty_zero_page, 0, PAGE_SIZE); 216 memset(empty_zero_page, 0, PAGE_SIZE);
218 __flush_wback_region(empty_zero_page, PAGE_SIZE); 217 __flush_wback_region(empty_zero_page, PAGE_SIZE);
219 218
220 after_bootmem = 1;
221
222 codesize = (unsigned long) &_etext - (unsigned long) &_text; 219 codesize = (unsigned long) &_etext - (unsigned long) &_text;
223 datasize = (unsigned long) &_edata - (unsigned long) &_etext; 220 datasize = (unsigned long) &_edata - (unsigned long) &_etext;
224 initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin; 221 initsize = (unsigned long) &__init_end - (unsigned long) &__init_begin;
diff --git a/arch/sh/mm/ioremap_32.c b/arch/sh/mm/ioremap_32.c
index 60cc486d2c2c..da2f4186f2cd 100644
--- a/arch/sh/mm/ioremap_32.c
+++ b/arch/sh/mm/ioremap_32.c
@@ -46,17 +46,15 @@ void __iomem *__ioremap(unsigned long phys_addr, unsigned long size,
46 return NULL; 46 return NULL;
47 47
48 /* 48 /*
49 * If we're on an SH7751 or SH7780 PCI controller, PCI memory is 49 * If we're in the fixed PCI memory range, mapping through page
50 * mapped at the end of the address space (typically 0xfd000000) 50 * tables is not only pointless, but also fundamentally broken.
51 * in a non-translatable area, so mapping through page tables for 51 * Just return the physical address instead.
52 * this area is not only pointless, but also fundamentally
53 * broken. Just return the physical address instead.
54 * 52 *
55 * For boards that map a small PCI memory aperture somewhere in 53 * For boards that map a small PCI memory aperture somewhere in
56 * P1/P2 space, ioremap() will already do the right thing, 54 * P1/P2 space, ioremap() will already do the right thing,
57 * and we'll never get this far. 55 * and we'll never get this far.
58 */ 56 */
59 if (is_pci_memaddr(phys_addr) && is_pci_memaddr(last_addr)) 57 if (is_pci_memory_fixed_range(phys_addr, size))
60 return (void __iomem *)phys_addr; 58 return (void __iomem *)phys_addr;
61 59
62#if !defined(CONFIG_PMB_FIXED) 60#if !defined(CONFIG_PMB_FIXED)
@@ -121,7 +119,9 @@ void __iounmap(void __iomem *addr)
121 unsigned long seg = PXSEG(vaddr); 119 unsigned long seg = PXSEG(vaddr);
122 struct vm_struct *p; 120 struct vm_struct *p;
123 121
124 if (seg < P3SEG || vaddr >= P3_ADDR_MAX || is_pci_memaddr(vaddr)) 122 if (seg < P3SEG || vaddr >= P3_ADDR_MAX)
123 return;
124 if (is_pci_memory_fixed_range(vaddr, 0))
125 return; 125 return;
126 126
127#ifdef CONFIG_PMB 127#ifdef CONFIG_PMB
diff --git a/arch/sh/mm/ioremap_64.c b/arch/sh/mm/ioremap_64.c
index 31e1bb5effbe..828c8597219d 100644
--- a/arch/sh/mm/ioremap_64.c
+++ b/arch/sh/mm/ioremap_64.c
@@ -20,6 +20,7 @@
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/bootmem.h> 21#include <linux/bootmem.h>
22#include <linux/proc_fs.h> 22#include <linux/proc_fs.h>
23#include <linux/slab.h>
23#include <asm/page.h> 24#include <asm/page.h>
24#include <asm/pgalloc.h> 25#include <asm/pgalloc.h>
25#include <asm/addrspace.h> 26#include <asm/addrspace.h>
@@ -27,88 +28,17 @@
27#include <asm/tlbflush.h> 28#include <asm/tlbflush.h>
28#include <asm/mmu.h> 29#include <asm/mmu.h>
29 30
30static void shmedia_mapioaddr(unsigned long, unsigned long);
31static unsigned long shmedia_ioremap(struct resource *, u32, int);
32
33/*
34 * Generic mapping function (not visible outside):
35 */
36
37/*
38 * Remap an arbitrary physical address space into the kernel virtual
39 * address space. Needed when the kernel wants to access high addresses
40 * directly.
41 *
42 * NOTE! We need to allow non-page-aligned mappings too: we will obviously
43 * have to convert them into an offset in a page-aligned mapping, but the
44 * caller shouldn't need to know that small detail.
45 */
46void *__ioremap(unsigned long phys_addr, unsigned long size,
47 unsigned long flags)
48{
49 void * addr;
50 struct vm_struct * area;
51 unsigned long offset, last_addr;
52 pgprot_t pgprot;
53
54 /* Don't allow wraparound or zero size */
55 last_addr = phys_addr + size - 1;
56 if (!size || last_addr < phys_addr)
57 return NULL;
58
59 pgprot = __pgprot(_PAGE_PRESENT | _PAGE_READ |
60 _PAGE_WRITE | _PAGE_DIRTY |
61 _PAGE_ACCESSED | _PAGE_SHARED | flags);
62
63 /*
64 * Mappings have to be page-aligned
65 */
66 offset = phys_addr & ~PAGE_MASK;
67 phys_addr &= PAGE_MASK;
68 size = PAGE_ALIGN(last_addr + 1) - phys_addr;
69
70 /*
71 * Ok, go for it..
72 */
73 area = get_vm_area(size, VM_IOREMAP);
74 if (!area)
75 return NULL;
76 pr_debug("Get vm_area returns %p addr %p\n", area, area->addr);
77 area->phys_addr = phys_addr;
78 addr = area->addr;
79 if (ioremap_page_range((unsigned long)addr, (unsigned long)addr + size,
80 phys_addr, pgprot)) {
81 vunmap(addr);
82 return NULL;
83 }
84 return (void *) (offset + (char *)addr);
85}
86EXPORT_SYMBOL(__ioremap);
87
88void __iounmap(void *addr)
89{
90 struct vm_struct *area;
91
92 vfree((void *) (PAGE_MASK & (unsigned long) addr));
93 area = remove_vm_area((void *) (PAGE_MASK & (unsigned long) addr));
94 if (!area) {
95 printk(KERN_ERR "iounmap: bad address %p\n", addr);
96 return;
97 }
98
99 kfree(area);
100}
101EXPORT_SYMBOL(__iounmap);
102
103static struct resource shmedia_iomap = { 31static struct resource shmedia_iomap = {
104 .name = "shmedia_iomap", 32 .name = "shmedia_iomap",
105 .start = IOBASE_VADDR + PAGE_SIZE, 33 .start = IOBASE_VADDR + PAGE_SIZE,
106 .end = IOBASE_END - 1, 34 .end = IOBASE_END - 1,
107}; 35};
108 36
109static void shmedia_mapioaddr(unsigned long pa, unsigned long va); 37static void shmedia_mapioaddr(unsigned long pa, unsigned long va,
38 unsigned long flags);
110static void shmedia_unmapioaddr(unsigned long vaddr); 39static void shmedia_unmapioaddr(unsigned long vaddr);
111static unsigned long shmedia_ioremap(struct resource *res, u32 pa, int sz); 40static void __iomem *shmedia_ioremap(struct resource *res, u32 pa,
41 int sz, unsigned long flags);
112 42
113/* 43/*
114 * We have the same problem as the SPARC, so lets have the same comment: 44 * We have the same problem as the SPARC, so lets have the same comment:
@@ -130,18 +60,18 @@ static struct xresource xresv[XNRES];
130 60
131static struct xresource *xres_alloc(void) 61static struct xresource *xres_alloc(void)
132{ 62{
133 struct xresource *xrp; 63 struct xresource *xrp;
134 int n; 64 int n;
135 65
136 xrp = xresv; 66 xrp = xresv;
137 for (n = 0; n < XNRES; n++) { 67 for (n = 0; n < XNRES; n++) {
138 if (xrp->xflag == 0) { 68 if (xrp->xflag == 0) {
139 xrp->xflag = 1; 69 xrp->xflag = 1;
140 return xrp; 70 return xrp;
141 } 71 }
142 xrp++; 72 xrp++;
143 } 73 }
144 return NULL; 74 return NULL;
145} 75}
146 76
147static void xres_free(struct xresource *xrp) 77static void xres_free(struct xresource *xrp)
@@ -161,76 +91,71 @@ static struct resource *shmedia_find_resource(struct resource *root,
161 return NULL; 91 return NULL;
162} 92}
163 93
164static unsigned long shmedia_alloc_io(unsigned long phys, unsigned long size, 94static void __iomem *shmedia_alloc_io(unsigned long phys, unsigned long size,
165 const char *name) 95 const char *name, unsigned long flags)
166{ 96{
167 static int printed_full = 0; 97 static int printed_full;
168 struct xresource *xres; 98 struct xresource *xres;
169 struct resource *res; 99 struct resource *res;
170 char *tack; 100 char *tack;
171 int tlen; 101 int tlen;
172 102
173 if (name == NULL) name = "???"; 103 if (name == NULL)
174 104 name = "???";
175 if ((xres = xres_alloc()) != 0) { 105
176 tack = xres->xname; 106 xres = xres_alloc();
177 res = &xres->xres; 107 if (xres != 0) {
178 } else { 108 tack = xres->xname;
179 if (!printed_full) { 109 res = &xres->xres;
180 printk("%s: done with statics, switching to kmalloc\n", 110 } else {
181 __func__); 111 if (!printed_full) {
182 printed_full = 1; 112 printk(KERN_NOTICE "%s: done with statics, "
183 } 113 "switching to kmalloc\n", __func__);
184 tlen = strlen(name); 114 printed_full = 1;
185 tack = kmalloc(sizeof (struct resource) + tlen + 1, GFP_KERNEL); 115 }
186 if (!tack) 116 tlen = strlen(name);
187 return -ENOMEM; 117 tack = kmalloc(sizeof(struct resource) + tlen + 1, GFP_KERNEL);
188 memset(tack, 0, sizeof(struct resource)); 118 if (!tack)
189 res = (struct resource *) tack; 119 return NULL;
190 tack += sizeof (struct resource); 120 memset(tack, 0, sizeof(struct resource));
191 } 121 res = (struct resource *) tack;
192 122 tack += sizeof(struct resource);
193 strncpy(tack, name, XNMLN); 123 }
194 tack[XNMLN] = 0; 124
195 res->name = tack; 125 strncpy(tack, name, XNMLN);
196 126 tack[XNMLN] = 0;
197 return shmedia_ioremap(res, phys, size); 127 res->name = tack;
128
129 return shmedia_ioremap(res, phys, size, flags);
198} 130}
199 131
200static unsigned long shmedia_ioremap(struct resource *res, u32 pa, int sz) 132static void __iomem *shmedia_ioremap(struct resource *res, u32 pa, int sz,
133 unsigned long flags)
201{ 134{
202 unsigned long offset = ((unsigned long) pa) & (~PAGE_MASK); 135 unsigned long offset = ((unsigned long) pa) & (~PAGE_MASK);
203 unsigned long round_sz = (offset + sz + PAGE_SIZE-1) & PAGE_MASK; 136 unsigned long round_sz = (offset + sz + PAGE_SIZE-1) & PAGE_MASK;
204 unsigned long va; 137 unsigned long va;
205 unsigned int psz; 138 unsigned int psz;
206 139
207 if (allocate_resource(&shmedia_iomap, res, round_sz, 140 if (allocate_resource(&shmedia_iomap, res, round_sz,
208 shmedia_iomap.start, shmedia_iomap.end, 141 shmedia_iomap.start, shmedia_iomap.end,
209 PAGE_SIZE, NULL, NULL) != 0) { 142 PAGE_SIZE, NULL, NULL) != 0) {
210 panic("alloc_io_res(%s): cannot occupy\n", 143 panic("alloc_io_res(%s): cannot occupy\n",
211 (res->name != NULL)? res->name: "???"); 144 (res->name != NULL) ? res->name : "???");
212 } 145 }
213 146
214 va = res->start; 147 va = res->start;
215 pa &= PAGE_MASK; 148 pa &= PAGE_MASK;
216 149
217 psz = (res->end - res->start + (PAGE_SIZE - 1)) / PAGE_SIZE; 150 psz = (res->end - res->start + (PAGE_SIZE - 1)) / PAGE_SIZE;
218 151
219 /* log at boot time ... */ 152 for (psz = res->end - res->start + 1; psz != 0; psz -= PAGE_SIZE) {
220 printk("mapioaddr: %6s [%2d page%s] va 0x%08lx pa 0x%08x\n", 153 shmedia_mapioaddr(pa, va, flags);
221 ((res->name != NULL) ? res->name : "???"), 154 va += PAGE_SIZE;
222 psz, psz == 1 ? " " : "s", va, pa); 155 pa += PAGE_SIZE;
223 156 }
224 for (psz = res->end - res->start + 1; psz != 0; psz -= PAGE_SIZE) {
225 shmedia_mapioaddr(pa, va);
226 va += PAGE_SIZE;
227 pa += PAGE_SIZE;
228 }
229
230 res->start += offset;
231 res->end = res->start + sz - 1; /* not strictly necessary.. */
232 157
233 return res->start; 158 return (void __iomem *)(unsigned long)(res->start + offset);
234} 159}
235 160
236static void shmedia_free_io(struct resource *res) 161static void shmedia_free_io(struct resource *res)
@@ -249,14 +174,12 @@ static void shmedia_free_io(struct resource *res)
249 174
250static __init_refok void *sh64_get_page(void) 175static __init_refok void *sh64_get_page(void)
251{ 176{
252 extern int after_bootmem;
253 void *page; 177 void *page;
254 178
255 if (after_bootmem) { 179 if (slab_is_available())
256 page = (void *)get_zeroed_page(GFP_ATOMIC); 180 page = (void *)get_zeroed_page(GFP_KERNEL);
257 } else { 181 else
258 page = alloc_bootmem_pages(PAGE_SIZE); 182 page = alloc_bootmem_pages(PAGE_SIZE);
259 }
260 183
261 if (!page || ((unsigned long)page & ~PAGE_MASK)) 184 if (!page || ((unsigned long)page & ~PAGE_MASK))
262 panic("sh64_get_page: Out of memory already?\n"); 185 panic("sh64_get_page: Out of memory already?\n");
@@ -264,17 +187,20 @@ static __init_refok void *sh64_get_page(void)
264 return page; 187 return page;
265} 188}
266 189
267static void shmedia_mapioaddr(unsigned long pa, unsigned long va) 190static void shmedia_mapioaddr(unsigned long pa, unsigned long va,
191 unsigned long flags)
268{ 192{
269 pgd_t *pgdp; 193 pgd_t *pgdp;
270 pud_t *pudp; 194 pud_t *pudp;
271 pmd_t *pmdp; 195 pmd_t *pmdp;
272 pte_t *ptep, pte; 196 pte_t *ptep, pte;
273 pgprot_t prot; 197 pgprot_t prot;
274 unsigned long flags = 1; /* 1 = CB0-1 device */
275 198
276 pr_debug("shmedia_mapiopage pa %08lx va %08lx\n", pa, va); 199 pr_debug("shmedia_mapiopage pa %08lx va %08lx\n", pa, va);
277 200
201 if (!flags)
202 flags = 1; /* 1 = CB0-1 device */
203
278 pgdp = pgd_offset_k(va); 204 pgdp = pgd_offset_k(va);
279 if (pgd_none(*pgdp) || !pgd_present(*pgdp)) { 205 if (pgd_none(*pgdp) || !pgd_present(*pgdp)) {
280 pudp = (pud_t *)sh64_get_page(); 206 pudp = (pud_t *)sh64_get_page();
@@ -288,7 +214,7 @@ static void shmedia_mapioaddr(unsigned long pa, unsigned long va)
288 } 214 }
289 215
290 pmdp = pmd_offset(pudp, va); 216 pmdp = pmd_offset(pudp, va);
291 if (pmd_none(*pmdp) || !pmd_present(*pmdp) ) { 217 if (pmd_none(*pmdp) || !pmd_present(*pmdp)) {
292 ptep = (pte_t *)sh64_get_page(); 218 ptep = (pte_t *)sh64_get_page();
293 set_pmd(pmdp, __pmd((unsigned long)ptep + _PAGE_TABLE)); 219 set_pmd(pmdp, __pmd((unsigned long)ptep + _PAGE_TABLE));
294 } 220 }
@@ -336,17 +262,19 @@ static void shmedia_unmapioaddr(unsigned long vaddr)
336 pte_clear(&init_mm, vaddr, ptep); 262 pte_clear(&init_mm, vaddr, ptep);
337} 263}
338 264
339unsigned long onchip_remap(unsigned long phys, unsigned long size, const char *name) 265void __iomem *__ioremap(unsigned long offset, unsigned long size,
266 unsigned long flags)
340{ 267{
341 if (size < PAGE_SIZE) 268 char name[14];
342 size = PAGE_SIZE;
343 269
344 return shmedia_alloc_io(phys, size, name); 270 sprintf(name, "phys_%08x", (u32)offset);
271 return shmedia_alloc_io(offset, size, name, flags);
345} 272}
346EXPORT_SYMBOL(onchip_remap); 273EXPORT_SYMBOL(__ioremap);
347 274
348void onchip_unmap(unsigned long vaddr) 275void __iounmap(void __iomem *virtual)
349{ 276{
277 unsigned long vaddr = (unsigned long)virtual & PAGE_MASK;
350 struct resource *res; 278 struct resource *res;
351 unsigned int psz; 279 unsigned int psz;
352 280
@@ -357,10 +285,7 @@ void onchip_unmap(unsigned long vaddr)
357 return; 285 return;
358 } 286 }
359 287
360 psz = (res->end - res->start + (PAGE_SIZE - 1)) / PAGE_SIZE; 288 psz = (res->end - res->start + (PAGE_SIZE - 1)) / PAGE_SIZE;
361
362 printk(KERN_DEBUG "unmapioaddr: %6s [%2d page%s] freed\n",
363 res->name, psz, psz == 1 ? " " : "s");
364 289
365 shmedia_free_io(res); 290 shmedia_free_io(res);
366 291
@@ -371,9 +296,8 @@ void onchip_unmap(unsigned long vaddr)
371 kfree(res); 296 kfree(res);
372 } 297 }
373} 298}
374EXPORT_SYMBOL(onchip_unmap); 299EXPORT_SYMBOL(__iounmap);
375 300
376#ifdef CONFIG_PROC_FS
377static int 301static int
378ioremap_proc_info(char *buf, char **start, off_t fpos, int length, int *eof, 302ioremap_proc_info(char *buf, char **start, off_t fpos, int length, int *eof,
379 void *data) 303 void *data)
@@ -385,7 +309,10 @@ ioremap_proc_info(char *buf, char **start, off_t fpos, int length, int *eof,
385 for (r = ((struct resource *)data)->child; r != NULL; r = r->sibling) { 309 for (r = ((struct resource *)data)->child; r != NULL; r = r->sibling) {
386 if (p + 32 >= e) /* Better than nothing */ 310 if (p + 32 >= e) /* Better than nothing */
387 break; 311 break;
388 if ((nm = r->name) == 0) nm = "???"; 312 nm = r->name;
313 if (nm == NULL)
314 nm = "???";
315
389 p += sprintf(p, "%08lx-%08lx: %s\n", 316 p += sprintf(p, "%08lx-%08lx: %s\n",
390 (unsigned long)r->start, 317 (unsigned long)r->start,
391 (unsigned long)r->end, nm); 318 (unsigned long)r->end, nm);
@@ -393,14 +320,11 @@ ioremap_proc_info(char *buf, char **start, off_t fpos, int length, int *eof,
393 320
394 return p-buf; 321 return p-buf;
395} 322}
396#endif /* CONFIG_PROC_FS */
397 323
398static int __init register_proc_onchip(void) 324static int __init register_proc_onchip(void)
399{ 325{
400#ifdef CONFIG_PROC_FS 326 create_proc_read_entry("io_map", 0, 0, ioremap_proc_info,
401 create_proc_read_entry("io_map",0,0, ioremap_proc_info, &shmedia_iomap); 327 &shmedia_iomap);
402#endif
403 return 0; 328 return 0;
404} 329}
405 330late_initcall(register_proc_onchip);
406__initcall(register_proc_onchip);
diff --git a/arch/sh/mm/mmap.c b/arch/sh/mm/mmap.c
index 931f4d003fa0..1b5fdfb4e0c2 100644
--- a/arch/sh/mm/mmap.c
+++ b/arch/sh/mm/mmap.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/sh/mm/mmap.c 2 * arch/sh/mm/mmap.c
3 * 3 *
4 * Copyright (C) 2008 Paul Mundt 4 * Copyright (C) 2008 - 2009 Paul Mundt
5 * 5 *
6 * This file is subject to the terms and conditions of the GNU General Public 6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
@@ -21,9 +21,26 @@ EXPORT_SYMBOL(shm_align_mask);
21/* 21/*
22 * To avoid cache aliases, we map the shared page with same color. 22 * To avoid cache aliases, we map the shared page with same color.
23 */ 23 */
24#define COLOUR_ALIGN(addr, pgoff) \ 24static inline unsigned long COLOUR_ALIGN(unsigned long addr,
25 ((((addr) + shm_align_mask) & ~shm_align_mask) + \ 25 unsigned long pgoff)
26 (((pgoff) << PAGE_SHIFT) & shm_align_mask)) 26{
27 unsigned long base = (addr + shm_align_mask) & ~shm_align_mask;
28 unsigned long off = (pgoff << PAGE_SHIFT) & shm_align_mask;
29
30 return base + off;
31}
32
33static inline unsigned long COLOUR_ALIGN_DOWN(unsigned long addr,
34 unsigned long pgoff)
35{
36 unsigned long base = addr & ~shm_align_mask;
37 unsigned long off = (pgoff << PAGE_SHIFT) & shm_align_mask;
38
39 if (base + off <= addr)
40 return base + off;
41
42 return base - off;
43}
27 44
28unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, 45unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr,
29 unsigned long len, unsigned long pgoff, unsigned long flags) 46 unsigned long len, unsigned long pgoff, unsigned long flags)
@@ -103,6 +120,117 @@ full_search:
103 addr = COLOUR_ALIGN(addr, pgoff); 120 addr = COLOUR_ALIGN(addr, pgoff);
104 } 121 }
105} 122}
123
124unsigned long
125arch_get_unmapped_area_topdown(struct file *filp, const unsigned long addr0,
126 const unsigned long len, const unsigned long pgoff,
127 const unsigned long flags)
128{
129 struct vm_area_struct *vma;
130 struct mm_struct *mm = current->mm;
131 unsigned long addr = addr0;
132 int do_colour_align;
133
134 if (flags & MAP_FIXED) {
135 /* We do not accept a shared mapping if it would violate
136 * cache aliasing constraints.
137 */
138 if ((flags & MAP_SHARED) &&
139 ((addr - (pgoff << PAGE_SHIFT)) & shm_align_mask))
140 return -EINVAL;
141 return addr;
142 }
143
144 if (unlikely(len > TASK_SIZE))
145 return -ENOMEM;
146
147 do_colour_align = 0;
148 if (filp || (flags & MAP_SHARED))
149 do_colour_align = 1;
150
151 /* requesting a specific address */
152 if (addr) {
153 if (do_colour_align)
154 addr = COLOUR_ALIGN(addr, pgoff);
155 else
156 addr = PAGE_ALIGN(addr);
157
158 vma = find_vma(mm, addr);
159 if (TASK_SIZE - len >= addr &&
160 (!vma || addr + len <= vma->vm_start))
161 return addr;
162 }
163
164 /* check if free_area_cache is useful for us */
165 if (len <= mm->cached_hole_size) {
166 mm->cached_hole_size = 0;
167 mm->free_area_cache = mm->mmap_base;
168 }
169
170 /* either no address requested or can't fit in requested address hole */
171 addr = mm->free_area_cache;
172 if (do_colour_align) {
173 unsigned long base = COLOUR_ALIGN_DOWN(addr-len, pgoff);
174
175 addr = base + len;
176 }
177
178 /* make sure it can fit in the remaining address space */
179 if (likely(addr > len)) {
180 vma = find_vma(mm, addr-len);
181 if (!vma || addr <= vma->vm_start) {
182 /* remember the address as a hint for next time */
183 return (mm->free_area_cache = addr-len);
184 }
185 }
186
187 if (unlikely(mm->mmap_base < len))
188 goto bottomup;
189
190 addr = mm->mmap_base-len;
191 if (do_colour_align)
192 addr = COLOUR_ALIGN_DOWN(addr, pgoff);
193
194 do {
195 /*
196 * Lookup failure means no vma is above this address,
197 * else if new region fits below vma->vm_start,
198 * return with success:
199 */
200 vma = find_vma(mm, addr);
201 if (likely(!vma || addr+len <= vma->vm_start)) {
202 /* remember the address as a hint for next time */
203 return (mm->free_area_cache = addr);
204 }
205
206 /* remember the largest hole we saw so far */
207 if (addr + mm->cached_hole_size < vma->vm_start)
208 mm->cached_hole_size = vma->vm_start - addr;
209
210 /* try just below the current vma->vm_start */
211 addr = vma->vm_start-len;
212 if (do_colour_align)
213 addr = COLOUR_ALIGN_DOWN(addr, pgoff);
214 } while (likely(len < vma->vm_start));
215
216bottomup:
217 /*
218 * A failed mmap() very likely causes application failure,
219 * so fall back to the bottom-up function here. This scenario
220 * can happen with large stack limits and large mmap()
221 * allocations.
222 */
223 mm->cached_hole_size = ~0UL;
224 mm->free_area_cache = TASK_UNMAPPED_BASE;
225 addr = arch_get_unmapped_area(filp, addr0, len, pgoff, flags);
226 /*
227 * Restore the topdown base:
228 */
229 mm->free_area_cache = mm->mmap_base;
230 mm->cached_hole_size = ~0UL;
231
232 return addr;
233}
106#endif /* CONFIG_MMU */ 234#endif /* CONFIG_MMU */
107 235
108/* 236/*
diff --git a/arch/sh/oprofile/common.c b/arch/sh/oprofile/common.c
index 1b9d4304b3bf..44f4e31c6d63 100644
--- a/arch/sh/oprofile/common.c
+++ b/arch/sh/oprofile/common.c
@@ -109,6 +109,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
109 case CPU_SH7785: 109 case CPU_SH7785:
110 case CPU_SH7786: 110 case CPU_SH7786:
111 case CPU_SH7723: 111 case CPU_SH7723:
112 case CPU_SH7724:
112 case CPU_SHX3: 113 case CPU_SHX3:
113 lmodel = &op_model_sh4a_ops; 114 lmodel = &op_model_sh4a_ops;
114 break; 115 break;
diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types
index 8477b5d884fd..fec3a53b8650 100644
--- a/arch/sh/tools/mach-types
+++ b/arch/sh/tools/mach-types
@@ -23,6 +23,7 @@ HD64461 HD64461
237619SE SH_7619_SOLUTION_ENGINE 237619SE SH_7619_SOLUTION_ENGINE
247721SE SH_7721_SOLUTION_ENGINE 247721SE SH_7721_SOLUTION_ENGINE
257722SE SH_7722_SOLUTION_ENGINE 257722SE SH_7722_SOLUTION_ENGINE
267724SE SH_7724_SOLUTION_ENGINE
267751SE SH_7751_SOLUTION_ENGINE 277751SE SH_7751_SOLUTION_ENGINE
277780SE SH_7780_SOLUTION_ENGINE 287780SE SH_7780_SOLUTION_ENGINE
287751SYSTEMH SH_7751_SYSTEMH 297751SYSTEMH SH_7751_SYSTEMH
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 1efb2879a94f..eef216f7f61d 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o
3obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o 3obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
4obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o 4obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
5obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o 5obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o
6obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o
7obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index 1c92c39a53aa..cf56a2af5fe1 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -18,7 +18,6 @@
18 */ 18 */
19 19
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/bootmem.h>
22#include <linux/platform_device.h> 21#include <linux/platform_device.h>
23#include <linux/spinlock.h> 22#include <linux/spinlock.h>
24#include <linux/interrupt.h> 23#include <linux/interrupt.h>
@@ -29,7 +28,7 @@
29#include <linux/err.h> 28#include <linux/err.h>
30#include <linux/clocksource.h> 29#include <linux/clocksource.h>
31#include <linux/clockchips.h> 30#include <linux/clockchips.h>
32#include <linux/sh_cmt.h> 31#include <linux/sh_timer.h>
33 32
34struct sh_cmt_priv { 33struct sh_cmt_priv {
35 void __iomem *mapbase; 34 void __iomem *mapbase;
@@ -47,6 +46,7 @@ struct sh_cmt_priv {
47 unsigned long rate; 46 unsigned long rate;
48 spinlock_t lock; 47 spinlock_t lock;
49 struct clock_event_device ced; 48 struct clock_event_device ced;
49 struct clocksource cs;
50 unsigned long total_cycles; 50 unsigned long total_cycles;
51}; 51};
52 52
@@ -59,7 +59,7 @@ static DEFINE_SPINLOCK(sh_cmt_lock);
59 59
60static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr) 60static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
61{ 61{
62 struct sh_cmt_config *cfg = p->pdev->dev.platform_data; 62 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
63 void __iomem *base = p->mapbase; 63 void __iomem *base = p->mapbase;
64 unsigned long offs; 64 unsigned long offs;
65 65
@@ -83,7 +83,7 @@ static inline unsigned long sh_cmt_read(struct sh_cmt_priv *p, int reg_nr)
83static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr, 83static inline void sh_cmt_write(struct sh_cmt_priv *p, int reg_nr,
84 unsigned long value) 84 unsigned long value)
85{ 85{
86 struct sh_cmt_config *cfg = p->pdev->dev.platform_data; 86 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
87 void __iomem *base = p->mapbase; 87 void __iomem *base = p->mapbase;
88 unsigned long offs; 88 unsigned long offs;
89 89
@@ -110,23 +110,28 @@ static unsigned long sh_cmt_get_counter(struct sh_cmt_priv *p,
110 int *has_wrapped) 110 int *has_wrapped)
111{ 111{
112 unsigned long v1, v2, v3; 112 unsigned long v1, v2, v3;
113 int o1, o2;
114
115 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
113 116
114 /* Make sure the timer value is stable. Stolen from acpi_pm.c */ 117 /* Make sure the timer value is stable. Stolen from acpi_pm.c */
115 do { 118 do {
119 o2 = o1;
116 v1 = sh_cmt_read(p, CMCNT); 120 v1 = sh_cmt_read(p, CMCNT);
117 v2 = sh_cmt_read(p, CMCNT); 121 v2 = sh_cmt_read(p, CMCNT);
118 v3 = sh_cmt_read(p, CMCNT); 122 v3 = sh_cmt_read(p, CMCNT);
119 } while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1) 123 o1 = sh_cmt_read(p, CMCSR) & p->overflow_bit;
120 || (v3 > v1 && v3 < v2))); 124 } while (unlikely((o1 != o2) || (v1 > v2 && v1 < v3)
125 || (v2 > v3 && v2 < v1) || (v3 > v1 && v3 < v2)));
121 126
122 *has_wrapped = sh_cmt_read(p, CMCSR) & p->overflow_bit; 127 *has_wrapped = o1;
123 return v2; 128 return v2;
124} 129}
125 130
126 131
127static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start) 132static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
128{ 133{
129 struct sh_cmt_config *cfg = p->pdev->dev.platform_data; 134 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
130 unsigned long flags, value; 135 unsigned long flags, value;
131 136
132 /* start stop register shared by multiple timer channels */ 137 /* start stop register shared by multiple timer channels */
@@ -144,7 +149,7 @@ static void sh_cmt_start_stop_ch(struct sh_cmt_priv *p, int start)
144 149
145static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate) 150static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
146{ 151{
147 struct sh_cmt_config *cfg = p->pdev->dev.platform_data; 152 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
148 int ret; 153 int ret;
149 154
150 /* enable clock */ 155 /* enable clock */
@@ -153,16 +158,18 @@ static int sh_cmt_enable(struct sh_cmt_priv *p, unsigned long *rate)
153 pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg->clk); 158 pr_err("sh_cmt: cannot enable clock \"%s\"\n", cfg->clk);
154 return ret; 159 return ret;
155 } 160 }
156 *rate = clk_get_rate(p->clk) / 8;
157 161
158 /* make sure channel is disabled */ 162 /* make sure channel is disabled */
159 sh_cmt_start_stop_ch(p, 0); 163 sh_cmt_start_stop_ch(p, 0);
160 164
161 /* configure channel, periodic mode and maximum timeout */ 165 /* configure channel, periodic mode and maximum timeout */
162 if (p->width == 16) 166 if (p->width == 16) {
163 sh_cmt_write(p, CMCSR, 0); 167 *rate = clk_get_rate(p->clk) / 512;
164 else 168 sh_cmt_write(p, CMCSR, 0x43);
169 } else {
170 *rate = clk_get_rate(p->clk) / 8;
165 sh_cmt_write(p, CMCSR, 0x01a4); 171 sh_cmt_write(p, CMCSR, 0x01a4);
172 }
166 173
167 sh_cmt_write(p, CMCOR, 0xffffffff); 174 sh_cmt_write(p, CMCOR, 0xffffffff);
168 sh_cmt_write(p, CMCNT, 0); 175 sh_cmt_write(p, CMCNT, 0);
@@ -376,6 +383,68 @@ static void sh_cmt_stop(struct sh_cmt_priv *p, unsigned long flag)
376 spin_unlock_irqrestore(&p->lock, flags); 383 spin_unlock_irqrestore(&p->lock, flags);
377} 384}
378 385
386static struct sh_cmt_priv *cs_to_sh_cmt(struct clocksource *cs)
387{
388 return container_of(cs, struct sh_cmt_priv, cs);
389}
390
391static cycle_t sh_cmt_clocksource_read(struct clocksource *cs)
392{
393 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
394 unsigned long flags, raw;
395 unsigned long value;
396 int has_wrapped;
397
398 spin_lock_irqsave(&p->lock, flags);
399 value = p->total_cycles;
400 raw = sh_cmt_get_counter(p, &has_wrapped);
401
402 if (unlikely(has_wrapped))
403 raw += p->match_value;
404 spin_unlock_irqrestore(&p->lock, flags);
405
406 return value + raw;
407}
408
409static int sh_cmt_clocksource_enable(struct clocksource *cs)
410{
411 struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
412 int ret;
413
414 p->total_cycles = 0;
415
416 ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
417 if (ret)
418 return ret;
419
420 /* TODO: calculate good shift from rate and counter bit width */
421 cs->shift = 0;
422 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
423 return 0;
424}
425
426static void sh_cmt_clocksource_disable(struct clocksource *cs)
427{
428 sh_cmt_stop(cs_to_sh_cmt(cs), FLAG_CLOCKSOURCE);
429}
430
431static int sh_cmt_register_clocksource(struct sh_cmt_priv *p,
432 char *name, unsigned long rating)
433{
434 struct clocksource *cs = &p->cs;
435
436 cs->name = name;
437 cs->rating = rating;
438 cs->read = sh_cmt_clocksource_read;
439 cs->enable = sh_cmt_clocksource_enable;
440 cs->disable = sh_cmt_clocksource_disable;
441 cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
442 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
443 pr_info("sh_cmt: %s used as clock source\n", cs->name);
444 clocksource_register(cs);
445 return 0;
446}
447
379static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced) 448static struct sh_cmt_priv *ced_to_sh_cmt(struct clock_event_device *ced)
380{ 449{
381 return container_of(ced, struct sh_cmt_priv, ced); 450 return container_of(ced, struct sh_cmt_priv, ced);
@@ -468,9 +537,9 @@ static void sh_cmt_register_clockevent(struct sh_cmt_priv *p,
468 clockevents_register_device(ced); 537 clockevents_register_device(ced);
469} 538}
470 539
471int sh_cmt_register(struct sh_cmt_priv *p, char *name, 540static int sh_cmt_register(struct sh_cmt_priv *p, char *name,
472 unsigned long clockevent_rating, 541 unsigned long clockevent_rating,
473 unsigned long clocksource_rating) 542 unsigned long clocksource_rating)
474{ 543{
475 if (p->width == (sizeof(p->max_match_value) * 8)) 544 if (p->width == (sizeof(p->max_match_value) * 8))
476 p->max_match_value = ~0; 545 p->max_match_value = ~0;
@@ -483,12 +552,15 @@ int sh_cmt_register(struct sh_cmt_priv *p, char *name,
483 if (clockevent_rating) 552 if (clockevent_rating)
484 sh_cmt_register_clockevent(p, name, clockevent_rating); 553 sh_cmt_register_clockevent(p, name, clockevent_rating);
485 554
555 if (clocksource_rating)
556 sh_cmt_register_clocksource(p, name, clocksource_rating);
557
486 return 0; 558 return 0;
487} 559}
488 560
489static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev) 561static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
490{ 562{
491 struct sh_cmt_config *cfg = pdev->dev.platform_data; 563 struct sh_timer_config *cfg = pdev->dev.platform_data;
492 struct resource *res; 564 struct resource *res;
493 int irq, ret; 565 int irq, ret;
494 ret = -ENXIO; 566 ret = -ENXIO;
@@ -545,7 +617,7 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
545 if (resource_size(res) == 6) { 617 if (resource_size(res) == 6) {
546 p->width = 16; 618 p->width = 16;
547 p->overflow_bit = 0x80; 619 p->overflow_bit = 0x80;
548 p->clear_bits = ~0xc0; 620 p->clear_bits = ~0x80;
549 } else { 621 } else {
550 p->width = 32; 622 p->width = 32;
551 p->overflow_bit = 0x8000; 623 p->overflow_bit = 0x8000;
@@ -566,8 +638,14 @@ static int sh_cmt_setup(struct sh_cmt_priv *p, struct platform_device *pdev)
566static int __devinit sh_cmt_probe(struct platform_device *pdev) 638static int __devinit sh_cmt_probe(struct platform_device *pdev)
567{ 639{
568 struct sh_cmt_priv *p = platform_get_drvdata(pdev); 640 struct sh_cmt_priv *p = platform_get_drvdata(pdev);
641 struct sh_timer_config *cfg = pdev->dev.platform_data;
569 int ret; 642 int ret;
570 643
644 if (p) {
645 pr_info("sh_cmt: %s kept as earlytimer\n", cfg->name);
646 return 0;
647 }
648
571 p = kmalloc(sizeof(*p), GFP_KERNEL); 649 p = kmalloc(sizeof(*p), GFP_KERNEL);
572 if (p == NULL) { 650 if (p == NULL) {
573 dev_err(&pdev->dev, "failed to allocate driver data\n"); 651 dev_err(&pdev->dev, "failed to allocate driver data\n");
@@ -577,7 +655,6 @@ static int __devinit sh_cmt_probe(struct platform_device *pdev)
577 ret = sh_cmt_setup(p, pdev); 655 ret = sh_cmt_setup(p, pdev);
578 if (ret) { 656 if (ret) {
579 kfree(p); 657 kfree(p);
580
581 platform_set_drvdata(pdev, NULL); 658 platform_set_drvdata(pdev, NULL);
582 } 659 }
583 return ret; 660 return ret;
@@ -606,6 +683,7 @@ static void __exit sh_cmt_exit(void)
606 platform_driver_unregister(&sh_cmt_device_driver); 683 platform_driver_unregister(&sh_cmt_device_driver);
607} 684}
608 685
686early_platform_init("earlytimer", &sh_cmt_device_driver);
609module_init(sh_cmt_init); 687module_init(sh_cmt_init);
610module_exit(sh_cmt_exit); 688module_exit(sh_cmt_exit);
611 689
diff --git a/drivers/clocksource/sh_mtu2.c b/drivers/clocksource/sh_mtu2.c
new file mode 100644
index 000000000000..d1ae75454d10
--- /dev/null
+++ b/drivers/clocksource/sh_mtu2.c
@@ -0,0 +1,357 @@
1/*
2 * SuperH Timer Support - MTU2
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/clk.h>
28#include <linux/irq.h>
29#include <linux/err.h>
30#include <linux/clockchips.h>
31#include <linux/sh_timer.h>
32
33struct sh_mtu2_priv {
34 void __iomem *mapbase;
35 struct clk *clk;
36 struct irqaction irqaction;
37 struct platform_device *pdev;
38 unsigned long rate;
39 unsigned long periodic;
40 struct clock_event_device ced;
41};
42
43static DEFINE_SPINLOCK(sh_mtu2_lock);
44
45#define TSTR -1 /* shared register */
46#define TCR 0 /* channel register */
47#define TMDR 1 /* channel register */
48#define TIOR 2 /* channel register */
49#define TIER 3 /* channel register */
50#define TSR 4 /* channel register */
51#define TCNT 5 /* channel register */
52#define TGR 6 /* channel register */
53
54static unsigned long mtu2_reg_offs[] = {
55 [TCR] = 0,
56 [TMDR] = 1,
57 [TIOR] = 2,
58 [TIER] = 4,
59 [TSR] = 5,
60 [TCNT] = 6,
61 [TGR] = 8,
62};
63
64static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr)
65{
66 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
67 void __iomem *base = p->mapbase;
68 unsigned long offs;
69
70 if (reg_nr == TSTR)
71 return ioread8(base + cfg->channel_offset);
72
73 offs = mtu2_reg_offs[reg_nr];
74
75 if ((reg_nr == TCNT) || (reg_nr == TGR))
76 return ioread16(base + offs);
77 else
78 return ioread8(base + offs);
79}
80
81static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr,
82 unsigned long value)
83{
84 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
85 void __iomem *base = p->mapbase;
86 unsigned long offs;
87
88 if (reg_nr == TSTR) {
89 iowrite8(value, base + cfg->channel_offset);
90 return;
91 }
92
93 offs = mtu2_reg_offs[reg_nr];
94
95 if ((reg_nr == TCNT) || (reg_nr == TGR))
96 iowrite16(value, base + offs);
97 else
98 iowrite8(value, base + offs);
99}
100
101static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
102{
103 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
104 unsigned long flags, value;
105
106 /* start stop register shared by multiple timer channels */
107 spin_lock_irqsave(&sh_mtu2_lock, flags);
108 value = sh_mtu2_read(p, TSTR);
109
110 if (start)
111 value |= 1 << cfg->timer_bit;
112 else
113 value &= ~(1 << cfg->timer_bit);
114
115 sh_mtu2_write(p, TSTR, value);
116 spin_unlock_irqrestore(&sh_mtu2_lock, flags);
117}
118
119static int sh_mtu2_enable(struct sh_mtu2_priv *p)
120{
121 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
122 int ret;
123
124 /* enable clock */
125 ret = clk_enable(p->clk);
126 if (ret) {
127 pr_err("sh_mtu2: cannot enable clock \"%s\"\n", cfg->clk);
128 return ret;
129 }
130
131 /* make sure channel is disabled */
132 sh_mtu2_start_stop_ch(p, 0);
133
134 p->rate = clk_get_rate(p->clk) / 64;
135 p->periodic = (p->rate + HZ/2) / HZ;
136
137 /* "Periodic Counter Operation" */
138 sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */
139 sh_mtu2_write(p, TIOR, 0);
140 sh_mtu2_write(p, TGR, p->periodic);
141 sh_mtu2_write(p, TCNT, 0);
142 sh_mtu2_write(p, TMDR, 0);
143 sh_mtu2_write(p, TIER, 0x01);
144
145 /* enable channel */
146 sh_mtu2_start_stop_ch(p, 1);
147
148 return 0;
149}
150
151static void sh_mtu2_disable(struct sh_mtu2_priv *p)
152{
153 /* disable channel */
154 sh_mtu2_start_stop_ch(p, 0);
155
156 /* stop clock */
157 clk_disable(p->clk);
158}
159
160static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
161{
162 struct sh_mtu2_priv *p = dev_id;
163
164 /* acknowledge interrupt */
165 sh_mtu2_read(p, TSR);
166 sh_mtu2_write(p, TSR, 0xfe);
167
168 /* notify clockevent layer */
169 p->ced.event_handler(&p->ced);
170 return IRQ_HANDLED;
171}
172
173static struct sh_mtu2_priv *ced_to_sh_mtu2(struct clock_event_device *ced)
174{
175 return container_of(ced, struct sh_mtu2_priv, ced);
176}
177
178static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
179 struct clock_event_device *ced)
180{
181 struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced);
182 int disabled = 0;
183
184 /* deal with old setting first */
185 switch (ced->mode) {
186 case CLOCK_EVT_MODE_PERIODIC:
187 sh_mtu2_disable(p);
188 disabled = 1;
189 break;
190 default:
191 break;
192 }
193
194 switch (mode) {
195 case CLOCK_EVT_MODE_PERIODIC:
196 pr_info("sh_mtu2: %s used for periodic clock events\n",
197 ced->name);
198 sh_mtu2_enable(p);
199 break;
200 case CLOCK_EVT_MODE_UNUSED:
201 if (!disabled)
202 sh_mtu2_disable(p);
203 break;
204 case CLOCK_EVT_MODE_SHUTDOWN:
205 default:
206 break;
207 }
208}
209
210static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
211 char *name, unsigned long rating)
212{
213 struct clock_event_device *ced = &p->ced;
214 int ret;
215
216 memset(ced, 0, sizeof(*ced));
217
218 ced->name = name;
219 ced->features = CLOCK_EVT_FEAT_PERIODIC;
220 ced->rating = rating;
221 ced->cpumask = cpumask_of(0);
222 ced->set_mode = sh_mtu2_clock_event_mode;
223
224 ret = setup_irq(p->irqaction.irq, &p->irqaction);
225 if (ret) {
226 pr_err("sh_mtu2: failed to request irq %d\n",
227 p->irqaction.irq);
228 return;
229 }
230
231 pr_info("sh_mtu2: %s used for clock events\n", ced->name);
232 clockevents_register_device(ced);
233}
234
235static int sh_mtu2_register(struct sh_mtu2_priv *p, char *name,
236 unsigned long clockevent_rating)
237{
238 if (clockevent_rating)
239 sh_mtu2_register_clockevent(p, name, clockevent_rating);
240
241 return 0;
242}
243
244static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
245{
246 struct sh_timer_config *cfg = pdev->dev.platform_data;
247 struct resource *res;
248 int irq, ret;
249 ret = -ENXIO;
250
251 memset(p, 0, sizeof(*p));
252 p->pdev = pdev;
253
254 if (!cfg) {
255 dev_err(&p->pdev->dev, "missing platform data\n");
256 goto err0;
257 }
258
259 platform_set_drvdata(pdev, p);
260
261 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
262 if (!res) {
263 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
264 goto err0;
265 }
266
267 irq = platform_get_irq(p->pdev, 0);
268 if (irq < 0) {
269 dev_err(&p->pdev->dev, "failed to get irq\n");
270 goto err0;
271 }
272
273 /* map memory, let mapbase point to our channel */
274 p->mapbase = ioremap_nocache(res->start, resource_size(res));
275 if (p->mapbase == NULL) {
276 pr_err("sh_mtu2: failed to remap I/O memory\n");
277 goto err0;
278 }
279
280 /* setup data for setup_irq() (too early for request_irq()) */
281 p->irqaction.name = cfg->name;
282 p->irqaction.handler = sh_mtu2_interrupt;
283 p->irqaction.dev_id = p;
284 p->irqaction.irq = irq;
285 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
286 p->irqaction.mask = CPU_MASK_NONE;
287
288 /* get hold of clock */
289 p->clk = clk_get(&p->pdev->dev, cfg->clk);
290 if (IS_ERR(p->clk)) {
291 pr_err("sh_mtu2: cannot get clock \"%s\"\n", cfg->clk);
292 ret = PTR_ERR(p->clk);
293 goto err1;
294 }
295
296 return sh_mtu2_register(p, cfg->name, cfg->clockevent_rating);
297 err1:
298 iounmap(p->mapbase);
299 err0:
300 return ret;
301}
302
303static int __devinit sh_mtu2_probe(struct platform_device *pdev)
304{
305 struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
306 struct sh_timer_config *cfg = pdev->dev.platform_data;
307 int ret;
308
309 if (p) {
310 pr_info("sh_mtu2: %s kept as earlytimer\n", cfg->name);
311 return 0;
312 }
313
314 p = kmalloc(sizeof(*p), GFP_KERNEL);
315 if (p == NULL) {
316 dev_err(&pdev->dev, "failed to allocate driver data\n");
317 return -ENOMEM;
318 }
319
320 ret = sh_mtu2_setup(p, pdev);
321 if (ret) {
322 kfree(p);
323 platform_set_drvdata(pdev, NULL);
324 }
325 return ret;
326}
327
328static int __devexit sh_mtu2_remove(struct platform_device *pdev)
329{
330 return -EBUSY; /* cannot unregister clockevent */
331}
332
333static struct platform_driver sh_mtu2_device_driver = {
334 .probe = sh_mtu2_probe,
335 .remove = __devexit_p(sh_mtu2_remove),
336 .driver = {
337 .name = "sh_mtu2",
338 }
339};
340
341static int __init sh_mtu2_init(void)
342{
343 return platform_driver_register(&sh_mtu2_device_driver);
344}
345
346static void __exit sh_mtu2_exit(void)
347{
348 platform_driver_unregister(&sh_mtu2_device_driver);
349}
350
351early_platform_init("earlytimer", &sh_mtu2_device_driver);
352module_init(sh_mtu2_init);
353module_exit(sh_mtu2_exit);
354
355MODULE_AUTHOR("Magnus Damm");
356MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
357MODULE_LICENSE("GPL v2");
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
new file mode 100644
index 000000000000..d6ea4398bf62
--- /dev/null
+++ b/drivers/clocksource/sh_tmu.c
@@ -0,0 +1,461 @@
1/*
2 * SuperH Timer Support - TMU
3 *
4 * Copyright (C) 2009 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/init.h>
21#include <linux/platform_device.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/ioport.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/clk.h>
28#include <linux/irq.h>
29#include <linux/err.h>
30#include <linux/clocksource.h>
31#include <linux/clockchips.h>
32#include <linux/sh_timer.h>
33
34struct sh_tmu_priv {
35 void __iomem *mapbase;
36 struct clk *clk;
37 struct irqaction irqaction;
38 struct platform_device *pdev;
39 unsigned long rate;
40 unsigned long periodic;
41 struct clock_event_device ced;
42 struct clocksource cs;
43};
44
45static DEFINE_SPINLOCK(sh_tmu_lock);
46
47#define TSTR -1 /* shared register */
48#define TCOR 0 /* channel register */
49#define TCNT 1 /* channel register */
50#define TCR 2 /* channel register */
51
52static inline unsigned long sh_tmu_read(struct sh_tmu_priv *p, int reg_nr)
53{
54 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
55 void __iomem *base = p->mapbase;
56 unsigned long offs;
57
58 if (reg_nr == TSTR)
59 return ioread8(base - cfg->channel_offset);
60
61 offs = reg_nr << 2;
62
63 if (reg_nr == TCR)
64 return ioread16(base + offs);
65 else
66 return ioread32(base + offs);
67}
68
69static inline void sh_tmu_write(struct sh_tmu_priv *p, int reg_nr,
70 unsigned long value)
71{
72 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
73 void __iomem *base = p->mapbase;
74 unsigned long offs;
75
76 if (reg_nr == TSTR) {
77 iowrite8(value, base - cfg->channel_offset);
78 return;
79 }
80
81 offs = reg_nr << 2;
82
83 if (reg_nr == TCR)
84 iowrite16(value, base + offs);
85 else
86 iowrite32(value, base + offs);
87}
88
89static void sh_tmu_start_stop_ch(struct sh_tmu_priv *p, int start)
90{
91 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
92 unsigned long flags, value;
93
94 /* start stop register shared by multiple timer channels */
95 spin_lock_irqsave(&sh_tmu_lock, flags);
96 value = sh_tmu_read(p, TSTR);
97
98 if (start)
99 value |= 1 << cfg->timer_bit;
100 else
101 value &= ~(1 << cfg->timer_bit);
102
103 sh_tmu_write(p, TSTR, value);
104 spin_unlock_irqrestore(&sh_tmu_lock, flags);
105}
106
107static int sh_tmu_enable(struct sh_tmu_priv *p)
108{
109 struct sh_timer_config *cfg = p->pdev->dev.platform_data;
110 int ret;
111
112 /* enable clock */
113 ret = clk_enable(p->clk);
114 if (ret) {
115 pr_err("sh_tmu: cannot enable clock \"%s\"\n", cfg->clk);
116 return ret;
117 }
118
119 /* make sure channel is disabled */
120 sh_tmu_start_stop_ch(p, 0);
121
122 /* maximum timeout */
123 sh_tmu_write(p, TCOR, 0xffffffff);
124 sh_tmu_write(p, TCNT, 0xffffffff);
125
126 /* configure channel to parent clock / 4, irq off */
127 p->rate = clk_get_rate(p->clk) / 4;
128 sh_tmu_write(p, TCR, 0x0000);
129
130 /* enable channel */
131 sh_tmu_start_stop_ch(p, 1);
132
133 return 0;
134}
135
136static void sh_tmu_disable(struct sh_tmu_priv *p)
137{
138 /* disable channel */
139 sh_tmu_start_stop_ch(p, 0);
140
141 /* stop clock */
142 clk_disable(p->clk);
143}
144
145static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
146 int periodic)
147{
148 /* stop timer */
149 sh_tmu_start_stop_ch(p, 0);
150
151 /* acknowledge interrupt */
152 sh_tmu_read(p, TCR);
153
154 /* enable interrupt */
155 sh_tmu_write(p, TCR, 0x0020);
156
157 /* reload delta value in case of periodic timer */
158 if (periodic)
159 sh_tmu_write(p, TCOR, delta);
160 else
161 sh_tmu_write(p, TCOR, 0);
162
163 sh_tmu_write(p, TCNT, delta);
164
165 /* start timer */
166 sh_tmu_start_stop_ch(p, 1);
167}
168
169static irqreturn_t sh_tmu_interrupt(int irq, void *dev_id)
170{
171 struct sh_tmu_priv *p = dev_id;
172
173 /* disable or acknowledge interrupt */
174 if (p->ced.mode == CLOCK_EVT_MODE_ONESHOT)
175 sh_tmu_write(p, TCR, 0x0000);
176 else
177 sh_tmu_write(p, TCR, 0x0020);
178
179 /* notify clockevent layer */
180 p->ced.event_handler(&p->ced);
181 return IRQ_HANDLED;
182}
183
184static struct sh_tmu_priv *cs_to_sh_tmu(struct clocksource *cs)
185{
186 return container_of(cs, struct sh_tmu_priv, cs);
187}
188
189static cycle_t sh_tmu_clocksource_read(struct clocksource *cs)
190{
191 struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
192
193 return sh_tmu_read(p, TCNT) ^ 0xffffffff;
194}
195
196static int sh_tmu_clocksource_enable(struct clocksource *cs)
197{
198 struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
199 int ret;
200
201 ret = sh_tmu_enable(p);
202 if (ret)
203 return ret;
204
205 /* TODO: calculate good shift from rate and counter bit width */
206 cs->shift = 10;
207 cs->mult = clocksource_hz2mult(p->rate, cs->shift);
208 return 0;
209}
210
211static void sh_tmu_clocksource_disable(struct clocksource *cs)
212{
213 sh_tmu_disable(cs_to_sh_tmu(cs));
214}
215
216static int sh_tmu_register_clocksource(struct sh_tmu_priv *p,
217 char *name, unsigned long rating)
218{
219 struct clocksource *cs = &p->cs;
220
221 cs->name = name;
222 cs->rating = rating;
223 cs->read = sh_tmu_clocksource_read;
224 cs->enable = sh_tmu_clocksource_enable;
225 cs->disable = sh_tmu_clocksource_disable;
226 cs->mask = CLOCKSOURCE_MASK(32);
227 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
228 pr_info("sh_tmu: %s used as clock source\n", cs->name);
229 clocksource_register(cs);
230 return 0;
231}
232
233static struct sh_tmu_priv *ced_to_sh_tmu(struct clock_event_device *ced)
234{
235 return container_of(ced, struct sh_tmu_priv, ced);
236}
237
238static void sh_tmu_clock_event_start(struct sh_tmu_priv *p, int periodic)
239{
240 struct clock_event_device *ced = &p->ced;
241
242 sh_tmu_enable(p);
243
244 /* TODO: calculate good shift from rate and counter bit width */
245
246 ced->shift = 32;
247 ced->mult = div_sc(p->rate, NSEC_PER_SEC, ced->shift);
248 ced->max_delta_ns = clockevent_delta2ns(0xffffffff, ced);
249 ced->min_delta_ns = 5000;
250
251 if (periodic) {
252 p->periodic = (p->rate + HZ/2) / HZ;
253 sh_tmu_set_next(p, p->periodic, 1);
254 }
255}
256
257static void sh_tmu_clock_event_mode(enum clock_event_mode mode,
258 struct clock_event_device *ced)
259{
260 struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
261 int disabled = 0;
262
263 /* deal with old setting first */
264 switch (ced->mode) {
265 case CLOCK_EVT_MODE_PERIODIC:
266 case CLOCK_EVT_MODE_ONESHOT:
267 sh_tmu_disable(p);
268 disabled = 1;
269 break;
270 default:
271 break;
272 }
273
274 switch (mode) {
275 case CLOCK_EVT_MODE_PERIODIC:
276 pr_info("sh_tmu: %s used for periodic clock events\n",
277 ced->name);
278 sh_tmu_clock_event_start(p, 1);
279 break;
280 case CLOCK_EVT_MODE_ONESHOT:
281 pr_info("sh_tmu: %s used for oneshot clock events\n",
282 ced->name);
283 sh_tmu_clock_event_start(p, 0);
284 break;
285 case CLOCK_EVT_MODE_UNUSED:
286 if (!disabled)
287 sh_tmu_disable(p);
288 break;
289 case CLOCK_EVT_MODE_SHUTDOWN:
290 default:
291 break;
292 }
293}
294
295static int sh_tmu_clock_event_next(unsigned long delta,
296 struct clock_event_device *ced)
297{
298 struct sh_tmu_priv *p = ced_to_sh_tmu(ced);
299
300 BUG_ON(ced->mode != CLOCK_EVT_MODE_ONESHOT);
301
302 /* program new delta value */
303 sh_tmu_set_next(p, delta, 0);
304 return 0;
305}
306
307static void sh_tmu_register_clockevent(struct sh_tmu_priv *p,
308 char *name, unsigned long rating)
309{
310 struct clock_event_device *ced = &p->ced;
311 int ret;
312
313 memset(ced, 0, sizeof(*ced));
314
315 ced->name = name;
316 ced->features = CLOCK_EVT_FEAT_PERIODIC;
317 ced->features |= CLOCK_EVT_FEAT_ONESHOT;
318 ced->rating = rating;
319 ced->cpumask = cpumask_of(0);
320 ced->set_next_event = sh_tmu_clock_event_next;
321 ced->set_mode = sh_tmu_clock_event_mode;
322
323 ret = setup_irq(p->irqaction.irq, &p->irqaction);
324 if (ret) {
325 pr_err("sh_tmu: failed to request irq %d\n",
326 p->irqaction.irq);
327 return;
328 }
329
330 pr_info("sh_tmu: %s used for clock events\n", ced->name);
331 clockevents_register_device(ced);
332}
333
334static int sh_tmu_register(struct sh_tmu_priv *p, char *name,
335 unsigned long clockevent_rating,
336 unsigned long clocksource_rating)
337{
338 if (clockevent_rating)
339 sh_tmu_register_clockevent(p, name, clockevent_rating);
340 else if (clocksource_rating)
341 sh_tmu_register_clocksource(p, name, clocksource_rating);
342
343 return 0;
344}
345
346static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
347{
348 struct sh_timer_config *cfg = pdev->dev.platform_data;
349 struct resource *res;
350 int irq, ret;
351 ret = -ENXIO;
352
353 memset(p, 0, sizeof(*p));
354 p->pdev = pdev;
355
356 if (!cfg) {
357 dev_err(&p->pdev->dev, "missing platform data\n");
358 goto err0;
359 }
360
361 platform_set_drvdata(pdev, p);
362
363 res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
364 if (!res) {
365 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
366 goto err0;
367 }
368
369 irq = platform_get_irq(p->pdev, 0);
370 if (irq < 0) {
371 dev_err(&p->pdev->dev, "failed to get irq\n");
372 goto err0;
373 }
374
375 /* map memory, let mapbase point to our channel */
376 p->mapbase = ioremap_nocache(res->start, resource_size(res));
377 if (p->mapbase == NULL) {
378 pr_err("sh_tmu: failed to remap I/O memory\n");
379 goto err0;
380 }
381
382 /* setup data for setup_irq() (too early for request_irq()) */
383 p->irqaction.name = cfg->name;
384 p->irqaction.handler = sh_tmu_interrupt;
385 p->irqaction.dev_id = p;
386 p->irqaction.irq = irq;
387 p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL;
388 p->irqaction.mask = CPU_MASK_NONE;
389
390 /* get hold of clock */
391 p->clk = clk_get(&p->pdev->dev, cfg->clk);
392 if (IS_ERR(p->clk)) {
393 pr_err("sh_tmu: cannot get clock \"%s\"\n", cfg->clk);
394 ret = PTR_ERR(p->clk);
395 goto err1;
396 }
397
398 return sh_tmu_register(p, cfg->name,
399 cfg->clockevent_rating,
400 cfg->clocksource_rating);
401 err1:
402 iounmap(p->mapbase);
403 err0:
404 return ret;
405}
406
407static int __devinit sh_tmu_probe(struct platform_device *pdev)
408{
409 struct sh_tmu_priv *p = platform_get_drvdata(pdev);
410 struct sh_timer_config *cfg = pdev->dev.platform_data;
411 int ret;
412
413 if (p) {
414 pr_info("sh_tmu: %s kept as earlytimer\n", cfg->name);
415 return 0;
416 }
417
418 p = kmalloc(sizeof(*p), GFP_KERNEL);
419 if (p == NULL) {
420 dev_err(&pdev->dev, "failed to allocate driver data\n");
421 return -ENOMEM;
422 }
423
424 ret = sh_tmu_setup(p, pdev);
425 if (ret) {
426 kfree(p);
427 platform_set_drvdata(pdev, NULL);
428 }
429 return ret;
430}
431
432static int __devexit sh_tmu_remove(struct platform_device *pdev)
433{
434 return -EBUSY; /* cannot unregister clockevent and clocksource */
435}
436
437static struct platform_driver sh_tmu_device_driver = {
438 .probe = sh_tmu_probe,
439 .remove = __devexit_p(sh_tmu_remove),
440 .driver = {
441 .name = "sh_tmu",
442 }
443};
444
445static int __init sh_tmu_init(void)
446{
447 return platform_driver_register(&sh_tmu_device_driver);
448}
449
450static void __exit sh_tmu_exit(void)
451{
452 platform_driver_unregister(&sh_tmu_device_driver);
453}
454
455early_platform_init("earlytimer", &sh_tmu_device_driver);
456module_init(sh_tmu_init);
457module_exit(sh_tmu_exit);
458
459MODULE_AUTHOR("Magnus Damm");
460MODULE_DESCRIPTION("SuperH TMU Timer Driver");
461MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/busses/i2c-sh7760.c b/drivers/i2c/busses/i2c-sh7760.c
index baa28b73ae42..b9680f50f541 100644
--- a/drivers/i2c/busses/i2c-sh7760.c
+++ b/drivers/i2c/busses/i2c-sh7760.c
@@ -396,7 +396,7 @@ static int __devinit calc_CCR(unsigned long scl_hz)
396 signed char cdf, cdfm; 396 signed char cdf, cdfm;
397 int scgd, scgdm, scgds; 397 int scgd, scgdm, scgds;
398 398
399 mclk = clk_get(NULL, "module_clk"); 399 mclk = clk_get(NULL, "peripheral_clk");
400 if (IS_ERR(mclk)) { 400 if (IS_ERR(mclk)) {
401 return PTR_ERR(mclk); 401 return PTR_ERR(mclk);
402 } else { 402 } else {
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 4e9851fc1746..277d35d232fa 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -692,7 +692,7 @@ config RTC_DRV_GENERIC
692 tristate "Generic RTC support" 692 tristate "Generic RTC support"
693 # Please consider writing a new RTC driver instead of using the generic 693 # Please consider writing a new RTC driver instead of using the generic
694 # RTC abstraction 694 # RTC abstraction
695 depends on PARISC || M68K || PPC 695 depends on PARISC || M68K || PPC || SUPERH32
696 help 696 help
697 Say Y or M here to enable RTC support on systems using the generic 697 Say Y or M here to enable RTC support on systems using the generic
698 RTC abstraction. If you do not know what you are doing, you should 698 RTC abstraction. If you do not know what you are doing, you should
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index dbf5357a77b3..a4cf1079b312 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -47,12 +47,17 @@
47#include <linux/clk.h> 47#include <linux/clk.h>
48#include <linux/ctype.h> 48#include <linux/ctype.h>
49#include <linux/err.h> 49#include <linux/err.h>
50#include <linux/list.h>
50 51
51#ifdef CONFIG_SUPERH 52#ifdef CONFIG_SUPERH
52#include <asm/clock.h> 53#include <asm/clock.h>
53#include <asm/sh_bios.h> 54#include <asm/sh_bios.h>
54#endif 55#endif
55 56
57#ifdef CONFIG_H8300
58#include <asm/gpio.h>
59#endif
60
56#include "sh-sci.h" 61#include "sh-sci.h"
57 62
58struct sci_port { 63struct sci_port {
@@ -75,14 +80,22 @@ struct sci_port {
75 int break_flag; 80 int break_flag;
76 81
77#ifdef CONFIG_HAVE_CLK 82#ifdef CONFIG_HAVE_CLK
78 /* Port clock */ 83 /* Interface clock */
79 struct clk *clk; 84 struct clk *iclk;
85 /* Data clock */
86 struct clk *dclk;
80#endif 87#endif
88 struct list_head node;
81}; 89};
82 90
83#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 91struct sh_sci_priv {
84static struct sci_port *serial_console_port; 92 spinlock_t lock;
93 struct list_head ports;
94
95#ifdef CONFIG_HAVE_CLK
96 struct notifier_block clk_nb;
85#endif 97#endif
98};
86 99
87/* Function prototypes */ 100/* Function prototypes */
88static void sci_stop_tx(struct uart_port *port); 101static void sci_stop_tx(struct uart_port *port);
@@ -138,9 +151,8 @@ static void sci_poll_put_char(struct uart_port *port, unsigned char c)
138 status = sci_in(port, SCxSR); 151 status = sci_in(port, SCxSR);
139 } while (!(status & SCxSR_TDxE(port))); 152 } while (!(status & SCxSR_TDxE(port)));
140 153
141 sci_in(port, SCxSR); /* Dummy read */
142 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
143 sci_out(port, SCxTDR, c); 154 sci_out(port, SCxTDR, c);
155 sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
144} 156}
145#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 157#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
146 158
@@ -159,12 +171,12 @@ static void h8300_sci_config(struct uart_port *port, unsigned int ctrl)
159 *mstpcrl &= ~mask; 171 *mstpcrl &= ~mask;
160} 172}
161 173
162static inline void h8300_sci_enable(struct uart_port *port) 174static void h8300_sci_enable(struct uart_port *port)
163{ 175{
164 h8300_sci_config(port, sci_enable); 176 h8300_sci_config(port, sci_enable);
165} 177}
166 178
167static inline void h8300_sci_disable(struct uart_port *port) 179static void h8300_sci_disable(struct uart_port *port)
168{ 180{
169 h8300_sci_config(port, sci_disable); 181 h8300_sci_config(port, sci_disable);
170} 182}
@@ -611,7 +623,7 @@ static inline int sci_handle_breaks(struct uart_port *port)
611 int copied = 0; 623 int copied = 0;
612 unsigned short status = sci_in(port, SCxSR); 624 unsigned short status = sci_in(port, SCxSR);
613 struct tty_struct *tty = port->info->port.tty; 625 struct tty_struct *tty = port->info->port.tty;
614 struct sci_port *s = &sci_ports[port->line]; 626 struct sci_port *s = to_sci_port(port);
615 627
616 if (uart_handle_break(port)) 628 if (uart_handle_break(port))
617 return 0; 629 return 0;
@@ -726,19 +738,43 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
726static int sci_notifier(struct notifier_block *self, 738static int sci_notifier(struct notifier_block *self,
727 unsigned long phase, void *p) 739 unsigned long phase, void *p)
728{ 740{
729 int i; 741 struct sh_sci_priv *priv = container_of(self,
742 struct sh_sci_priv, clk_nb);
743 struct sci_port *sci_port;
744 unsigned long flags;
730 745
731 if ((phase == CPUFREQ_POSTCHANGE) || 746 if ((phase == CPUFREQ_POSTCHANGE) ||
732 (phase == CPUFREQ_RESUMECHANGE)) 747 (phase == CPUFREQ_RESUMECHANGE)) {
733 for (i = 0; i < SCI_NPORTS; i++) { 748 spin_lock_irqsave(&priv->lock, flags);
734 struct sci_port *s = &sci_ports[i]; 749 list_for_each_entry(sci_port, &priv->ports, node)
735 s->port.uartclk = clk_get_rate(s->clk); 750 sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
736 } 751
752 spin_unlock_irqrestore(&priv->lock, flags);
753 }
737 754
738 return NOTIFY_OK; 755 return NOTIFY_OK;
739} 756}
740 757
741static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 }; 758static void sci_clk_enable(struct uart_port *port)
759{
760 struct sci_port *sci_port = to_sci_port(port);
761
762 clk_enable(sci_port->dclk);
763 sci_port->port.uartclk = clk_get_rate(sci_port->dclk);
764
765 if (sci_port->iclk)
766 clk_enable(sci_port->iclk);
767}
768
769static void sci_clk_disable(struct uart_port *port)
770{
771 struct sci_port *sci_port = to_sci_port(port);
772
773 if (sci_port->iclk)
774 clk_disable(sci_port->iclk);
775
776 clk_disable(sci_port->dclk);
777}
742#endif 778#endif
743 779
744static int sci_request_irq(struct sci_port *port) 780static int sci_request_irq(struct sci_port *port)
@@ -865,15 +901,11 @@ static void sci_break_ctl(struct uart_port *port, int break_state)
865 901
866static int sci_startup(struct uart_port *port) 902static int sci_startup(struct uart_port *port)
867{ 903{
868 struct sci_port *s = &sci_ports[port->line]; 904 struct sci_port *s = to_sci_port(port);
869 905
870 if (s->enable) 906 if (s->enable)
871 s->enable(port); 907 s->enable(port);
872 908
873#ifdef CONFIG_HAVE_CLK
874 s->clk = clk_get(NULL, "module_clk");
875#endif
876
877 sci_request_irq(s); 909 sci_request_irq(s);
878 sci_start_tx(port); 910 sci_start_tx(port);
879 sci_start_rx(port, 1); 911 sci_start_rx(port, 1);
@@ -883,7 +915,7 @@ static int sci_startup(struct uart_port *port)
883 915
884static void sci_shutdown(struct uart_port *port) 916static void sci_shutdown(struct uart_port *port)
885{ 917{
886 struct sci_port *s = &sci_ports[port->line]; 918 struct sci_port *s = to_sci_port(port);
887 919
888 sci_stop_rx(port); 920 sci_stop_rx(port);
889 sci_stop_tx(port); 921 sci_stop_tx(port);
@@ -891,11 +923,6 @@ static void sci_shutdown(struct uart_port *port)
891 923
892 if (s->disable) 924 if (s->disable)
893 s->disable(port); 925 s->disable(port);
894
895#ifdef CONFIG_HAVE_CLK
896 clk_put(s->clk);
897 s->clk = NULL;
898#endif
899} 926}
900 927
901static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 928static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
@@ -980,25 +1007,31 @@ static int sci_request_port(struct uart_port *port)
980 1007
981static void sci_config_port(struct uart_port *port, int flags) 1008static void sci_config_port(struct uart_port *port, int flags)
982{ 1009{
983 struct sci_port *s = &sci_ports[port->line]; 1010 struct sci_port *s = to_sci_port(port);
984 1011
985 port->type = s->type; 1012 port->type = s->type;
986 1013
987 if (port->flags & UPF_IOREMAP && !port->membase) { 1014 if (port->membase)
988#if defined(CONFIG_SUPERH64) 1015 return;
989 port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF"); 1016
990 port->membase = (void __iomem *)port->mapbase; 1017 if (port->flags & UPF_IOREMAP) {
991#else
992 port->membase = ioremap_nocache(port->mapbase, 0x40); 1018 port->membase = ioremap_nocache(port->mapbase, 0x40);
993#endif
994 1019
995 dev_err(port->dev, "can't remap port#%d\n", port->line); 1020 if (IS_ERR(port->membase))
1021 dev_err(port->dev, "can't remap port#%d\n", port->line);
1022 } else {
1023 /*
1024 * For the simple (and majority of) cases where we don't
1025 * need to do any remapping, just cast the cookie
1026 * directly.
1027 */
1028 port->membase = (void __iomem *)port->mapbase;
996 } 1029 }
997} 1030}
998 1031
999static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) 1032static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
1000{ 1033{
1001 struct sci_port *s = &sci_ports[port->line]; 1034 struct sci_port *s = to_sci_port(port);
1002 1035
1003 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs) 1036 if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > nr_irqs)
1004 return -EINVAL; 1037 return -EINVAL;
@@ -1032,63 +1065,60 @@ static struct uart_ops sci_uart_ops = {
1032#endif 1065#endif
1033}; 1066};
1034 1067
1035static void __init sci_init_ports(void) 1068static void __devinit sci_init_single(struct platform_device *dev,
1069 struct sci_port *sci_port,
1070 unsigned int index,
1071 struct plat_sci_port *p)
1036{ 1072{
1037 static int first = 1; 1073 sci_port->port.ops = &sci_uart_ops;
1038 int i; 1074 sci_port->port.iotype = UPIO_MEM;
1039 1075 sci_port->port.line = index;
1040 if (!first) 1076 sci_port->port.fifosize = 1;
1041 return;
1042
1043 first = 0;
1044
1045 for (i = 0; i < SCI_NPORTS; i++) {
1046 sci_ports[i].port.ops = &sci_uart_ops;
1047 sci_ports[i].port.iotype = UPIO_MEM;
1048 sci_ports[i].port.line = i;
1049 sci_ports[i].port.fifosize = 1;
1050 1077
1051#if defined(__H8300H__) || defined(__H8300S__) 1078#if defined(__H8300H__) || defined(__H8300S__)
1052#ifdef __H8300S__ 1079#ifdef __H8300S__
1053 sci_ports[i].enable = h8300_sci_enable; 1080 sci_port->enable = h8300_sci_enable;
1054 sci_ports[i].disable = h8300_sci_disable; 1081 sci_port->disable = h8300_sci_disable;
1055#endif 1082#endif
1056 sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK; 1083 sci_port->port.uartclk = CONFIG_CPU_CLOCK;
1057#elif defined(CONFIG_HAVE_CLK) 1084#elif defined(CONFIG_HAVE_CLK)
1058 /* 1085 sci_port->iclk = p->clk ? clk_get(&dev->dev, p->clk) : NULL;
1059 * XXX: We should use a proper SCI/SCIF clock 1086 sci_port->dclk = clk_get(&dev->dev, "peripheral_clk");
1060 */ 1087 sci_port->enable = sci_clk_enable;
1061 { 1088 sci_port->disable = sci_clk_disable;
1062 struct clk *clk = clk_get(NULL, "module_clk");
1063 sci_ports[i].port.uartclk = clk_get_rate(clk);
1064 clk_put(clk);
1065 }
1066#else 1089#else
1067#error "Need a valid uartclk" 1090#error "Need a valid uartclk"
1068#endif 1091#endif
1069 1092
1070 sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i]; 1093 sci_port->break_timer.data = (unsigned long)sci_port;
1071 sci_ports[i].break_timer.function = sci_break_timer; 1094 sci_port->break_timer.function = sci_break_timer;
1095 init_timer(&sci_port->break_timer);
1072 1096
1073 init_timer(&sci_ports[i].break_timer); 1097 sci_port->port.mapbase = p->mapbase;
1074 } 1098 sci_port->port.membase = p->membase;
1075}
1076
1077int __init early_sci_setup(struct uart_port *port)
1078{
1079 if (unlikely(port->line > SCI_NPORTS))
1080 return -ENODEV;
1081 1099
1082 sci_init_ports(); 1100 sci_port->port.irq = p->irqs[SCIx_TXI_IRQ];
1101 sci_port->port.flags = p->flags;
1102 sci_port->port.dev = &dev->dev;
1103 sci_port->type = sci_port->port.type = p->type;
1083 1104
1084 sci_ports[port->line].port.membase = port->membase; 1105 memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
1085 sci_ports[port->line].port.mapbase = port->mapbase;
1086 sci_ports[port->line].port.type = port->type;
1087 1106
1088 return 0;
1089} 1107}
1090 1108
1091#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE 1109#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
1110static struct tty_driver *serial_console_device(struct console *co, int *index)
1111{
1112 struct uart_driver *p = &sci_uart_driver;
1113 *index = co->index;
1114 return p->tty_driver;
1115}
1116
1117static void serial_console_putchar(struct uart_port *port, int ch)
1118{
1119 sci_poll_put_char(port, ch);
1120}
1121
1092/* 1122/*
1093 * Print a string to the serial port trying not to disturb 1123 * Print a string to the serial port trying not to disturb
1094 * any possible real use of the port... 1124 * any possible real use of the port...
@@ -1096,25 +1126,27 @@ int __init early_sci_setup(struct uart_port *port)
1096static void serial_console_write(struct console *co, const char *s, 1126static void serial_console_write(struct console *co, const char *s,
1097 unsigned count) 1127 unsigned count)
1098{ 1128{
1099 struct uart_port *port = &serial_console_port->port; 1129 struct uart_port *port = co->data;
1130 struct sci_port *sci_port = to_sci_port(port);
1100 unsigned short bits; 1131 unsigned short bits;
1101 int i;
1102 1132
1103 for (i = 0; i < count; i++) { 1133 if (sci_port->enable)
1104 if (*s == 10) 1134 sci_port->enable(port);
1105 sci_poll_put_char(port, '\r');
1106 1135
1107 sci_poll_put_char(port, *s++); 1136 uart_console_write(port, s, count, serial_console_putchar);
1108 }
1109 1137
1110 /* wait until fifo is empty and last bit has been transmitted */ 1138 /* wait until fifo is empty and last bit has been transmitted */
1111 bits = SCxSR_TDxE(port) | SCxSR_TEND(port); 1139 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
1112 while ((sci_in(port, SCxSR) & bits) != bits) 1140 while ((sci_in(port, SCxSR) & bits) != bits)
1113 cpu_relax(); 1141 cpu_relax();
1142
1143 if (sci_port->disable);
1144 sci_port->disable(port);
1114} 1145}
1115 1146
1116static int __init serial_console_setup(struct console *co, char *options) 1147static int __init serial_console_setup(struct console *co, char *options)
1117{ 1148{
1149 struct sci_port *sci_port;
1118 struct uart_port *port; 1150 struct uart_port *port;
1119 int baud = 115200; 1151 int baud = 115200;
1120 int bits = 8; 1152 int bits = 8;
@@ -1130,8 +1162,9 @@ static int __init serial_console_setup(struct console *co, char *options)
1130 if (co->index >= SCI_NPORTS) 1162 if (co->index >= SCI_NPORTS)
1131 co->index = 0; 1163 co->index = 0;
1132 1164
1133 serial_console_port = &sci_ports[co->index]; 1165 sci_port = &sci_ports[co->index];
1134 port = &serial_console_port->port; 1166 port = &sci_port->port;
1167 co->data = port;
1135 1168
1136 /* 1169 /*
1137 * Also need to check port->type, we don't actually have any 1170 * Also need to check port->type, we don't actually have any
@@ -1141,21 +1174,11 @@ static int __init serial_console_setup(struct console *co, char *options)
1141 */ 1174 */
1142 if (!port->type) 1175 if (!port->type)
1143 return -ENODEV; 1176 return -ENODEV;
1144 if (!port->membase || !port->mapbase)
1145 return -ENODEV;
1146
1147 port->type = serial_console_port->type;
1148
1149#ifdef CONFIG_HAVE_CLK
1150 if (!serial_console_port->clk)
1151 serial_console_port->clk = clk_get(NULL, "module_clk");
1152#endif
1153 1177
1154 if (port->flags & UPF_IOREMAP) 1178 sci_config_port(port, 0);
1155 sci_config_port(port, 0);
1156 1179
1157 if (serial_console_port->enable) 1180 if (sci_port->enable)
1158 serial_console_port->enable(port); 1181 sci_port->enable(port);
1159 1182
1160 if (options) 1183 if (options)
1161 uart_parse_options(options, &baud, &parity, &bits, &flow); 1184 uart_parse_options(options, &baud, &parity, &bits, &flow);
@@ -1166,22 +1189,21 @@ static int __init serial_console_setup(struct console *co, char *options)
1166 if (ret == 0) 1189 if (ret == 0)
1167 sci_stop_rx(port); 1190 sci_stop_rx(port);
1168#endif 1191#endif
1192 /* TODO: disable clock */
1169 return ret; 1193 return ret;
1170} 1194}
1171 1195
1172static struct console serial_console = { 1196static struct console serial_console = {
1173 .name = "ttySC", 1197 .name = "ttySC",
1174 .device = uart_console_device, 1198 .device = serial_console_device,
1175 .write = serial_console_write, 1199 .write = serial_console_write,
1176 .setup = serial_console_setup, 1200 .setup = serial_console_setup,
1177 .flags = CON_PRINTBUFFER, 1201 .flags = CON_PRINTBUFFER,
1178 .index = -1, 1202 .index = -1,
1179 .data = &sci_uart_driver,
1180}; 1203};
1181 1204
1182static int __init sci_console_init(void) 1205static int __init sci_console_init(void)
1183{ 1206{
1184 sci_init_ports();
1185 register_console(&serial_console); 1207 register_console(&serial_console);
1186 return 0; 1208 return 0;
1187} 1209}
@@ -1207,6 +1229,61 @@ static struct uart_driver sci_uart_driver = {
1207 .cons = SCI_CONSOLE, 1229 .cons = SCI_CONSOLE,
1208}; 1230};
1209 1231
1232
1233static int sci_remove(struct platform_device *dev)
1234{
1235 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1236 struct sci_port *p;
1237 unsigned long flags;
1238
1239#ifdef CONFIG_HAVE_CLK
1240 cpufreq_unregister_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1241#endif
1242
1243 spin_lock_irqsave(&priv->lock, flags);
1244 list_for_each_entry(p, &priv->ports, node)
1245 uart_remove_one_port(&sci_uart_driver, &p->port);
1246
1247 spin_unlock_irqrestore(&priv->lock, flags);
1248
1249 kfree(priv);
1250 return 0;
1251}
1252
1253static int __devinit sci_probe_single(struct platform_device *dev,
1254 unsigned int index,
1255 struct plat_sci_port *p,
1256 struct sci_port *sciport)
1257{
1258 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1259 unsigned long flags;
1260 int ret;
1261
1262 /* Sanity check */
1263 if (unlikely(index >= SCI_NPORTS)) {
1264 dev_notice(&dev->dev, "Attempting to register port "
1265 "%d when only %d are available.\n",
1266 index+1, SCI_NPORTS);
1267 dev_notice(&dev->dev, "Consider bumping "
1268 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1269 return 0;
1270 }
1271
1272 sci_init_single(dev, sciport, index, p);
1273
1274 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
1275 if (ret)
1276 return ret;
1277
1278 INIT_LIST_HEAD(&sciport->node);
1279
1280 spin_lock_irqsave(&priv->lock, flags);
1281 list_add(&sciport->node, &priv->ports);
1282 spin_unlock_irqrestore(&priv->lock, flags);
1283
1284 return 0;
1285}
1286
1210/* 1287/*
1211 * Register a set of serial devices attached to a platform device. The 1288 * Register a set of serial devices attached to a platform device. The
1212 * list is terminated with a zero flags entry, which means we expect 1289 * list is terminated with a zero flags entry, which means we expect
@@ -1216,57 +1293,34 @@ static struct uart_driver sci_uart_driver = {
1216static int __devinit sci_probe(struct platform_device *dev) 1293static int __devinit sci_probe(struct platform_device *dev)
1217{ 1294{
1218 struct plat_sci_port *p = dev->dev.platform_data; 1295 struct plat_sci_port *p = dev->dev.platform_data;
1296 struct sh_sci_priv *priv;
1219 int i, ret = -EINVAL; 1297 int i, ret = -EINVAL;
1220 1298
1221 for (i = 0; p && p->flags != 0; p++, i++) { 1299 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1222 struct sci_port *sciport = &sci_ports[i]; 1300 if (!priv)
1301 return -ENOMEM;
1223 1302
1224 /* Sanity check */ 1303 INIT_LIST_HEAD(&priv->ports);
1225 if (unlikely(i == SCI_NPORTS)) { 1304 spin_lock_init(&priv->lock);
1226 dev_notice(&dev->dev, "Attempting to register port " 1305 platform_set_drvdata(dev, priv);
1227 "%d when only %d are available.\n",
1228 i+1, SCI_NPORTS);
1229 dev_notice(&dev->dev, "Consider bumping "
1230 "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
1231 break;
1232 }
1233 1306
1234 sciport->port.mapbase = p->mapbase; 1307#ifdef CONFIG_HAVE_CLK
1308 priv->clk_nb.notifier_call = sci_notifier;
1309 cpufreq_register_notifier(&priv->clk_nb, CPUFREQ_TRANSITION_NOTIFIER);
1310#endif
1235 1311
1236 if (p->mapbase && !p->membase) { 1312 if (dev->id != -1) {
1237 if (p->flags & UPF_IOREMAP) { 1313 ret = sci_probe_single(dev, dev->id, p, &sci_ports[dev->id]);
1238 p->membase = ioremap_nocache(p->mapbase, 0x40); 1314 if (ret)
1239 if (IS_ERR(p->membase)) { 1315 goto err_unreg;
1240 ret = PTR_ERR(p->membase); 1316 } else {
1241 goto err_unreg; 1317 for (i = 0; p && p->flags != 0; p++, i++) {
1242 } 1318 ret = sci_probe_single(dev, i, p, &sci_ports[i]);
1243 } else { 1319 if (ret)
1244 /* 1320 goto err_unreg;
1245 * For the simple (and majority of) cases
1246 * where we don't need to do any remapping,
1247 * just cast the cookie directly.
1248 */
1249 p->membase = (void __iomem *)p->mapbase;
1250 }
1251 } 1321 }
1252
1253 sciport->port.membase = p->membase;
1254
1255 sciport->port.irq = p->irqs[SCIx_TXI_IRQ];
1256 sciport->port.flags = p->flags;
1257 sciport->port.dev = &dev->dev;
1258
1259 sciport->type = sciport->port.type = p->type;
1260
1261 memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs));
1262
1263 uart_add_one_port(&sci_uart_driver, &sciport->port);
1264 } 1322 }
1265 1323
1266#ifdef CONFIG_HAVE_CLK
1267 cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1268#endif
1269
1270#ifdef CONFIG_SH_STANDARD_BIOS 1324#ifdef CONFIG_SH_STANDARD_BIOS
1271 sh_bios_gdb_detach(); 1325 sh_bios_gdb_detach();
1272#endif 1326#endif
@@ -1274,50 +1328,36 @@ static int __devinit sci_probe(struct platform_device *dev)
1274 return 0; 1328 return 0;
1275 1329
1276err_unreg: 1330err_unreg:
1277 for (i = i - 1; i >= 0; i--) 1331 sci_remove(dev);
1278 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1279
1280 return ret; 1332 return ret;
1281} 1333}
1282 1334
1283static int __devexit sci_remove(struct platform_device *dev)
1284{
1285 int i;
1286
1287#ifdef CONFIG_HAVE_CLK
1288 cpufreq_unregister_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER);
1289#endif
1290
1291 for (i = 0; i < SCI_NPORTS; i++)
1292 uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port);
1293
1294 return 0;
1295}
1296
1297static int sci_suspend(struct platform_device *dev, pm_message_t state) 1335static int sci_suspend(struct platform_device *dev, pm_message_t state)
1298{ 1336{
1299 int i; 1337 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1338 struct sci_port *p;
1339 unsigned long flags;
1300 1340
1301 for (i = 0; i < SCI_NPORTS; i++) { 1341 spin_lock_irqsave(&priv->lock, flags);
1302 struct sci_port *p = &sci_ports[i]; 1342 list_for_each_entry(p, &priv->ports, node)
1343 uart_suspend_port(&sci_uart_driver, &p->port);
1303 1344
1304 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev) 1345 spin_unlock_irqrestore(&priv->lock, flags);
1305 uart_suspend_port(&sci_uart_driver, &p->port);
1306 }
1307 1346
1308 return 0; 1347 return 0;
1309} 1348}
1310 1349
1311static int sci_resume(struct platform_device *dev) 1350static int sci_resume(struct platform_device *dev)
1312{ 1351{
1313 int i; 1352 struct sh_sci_priv *priv = platform_get_drvdata(dev);
1353 struct sci_port *p;
1354 unsigned long flags;
1314 1355
1315 for (i = 0; i < SCI_NPORTS; i++) { 1356 spin_lock_irqsave(&priv->lock, flags);
1316 struct sci_port *p = &sci_ports[i]; 1357 list_for_each_entry(p, &priv->ports, node)
1358 uart_resume_port(&sci_uart_driver, &p->port);
1317 1359
1318 if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev) 1360 spin_unlock_irqrestore(&priv->lock, flags);
1319 uart_resume_port(&sci_uart_driver, &p->port);
1320 }
1321 1361
1322 return 0; 1362 return 0;
1323} 1363}
@@ -1339,8 +1379,6 @@ static int __init sci_init(void)
1339 1379
1340 printk(banner); 1380 printk(banner);
1341 1381
1342 sci_init_ports();
1343
1344 ret = uart_register_driver(&sci_uart_driver); 1382 ret = uart_register_driver(&sci_uart_driver);
1345 if (likely(ret == 0)) { 1383 if (likely(ret == 0)) {
1346 ret = platform_driver_register(&sci_driver); 1384 ret = platform_driver_register(&sci_driver);
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index d0aa82d7fce0..38072c15b845 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -91,6 +91,9 @@
91# define SCSPTR5 0xa4050128 91# define SCSPTR5 0xa4050128
92# define SCIF_ORER 0x0001 /* overrun error bit */ 92# define SCIF_ORER 0x0001 /* overrun error bit */
93# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 93# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
94#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
95# define SCIF_ORER 0x0001 /* overrun error bit */
96# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
94#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) 97#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
95# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ 98# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
96# define SCIF_ORER 0x0001 /* overrun error bit */ 99# define SCIF_ORER 0x0001 /* overrun error bit */
@@ -314,7 +317,18 @@
314 } \ 317 } \
315 } 318 }
316 319
317#define CPU_SCIF_FNS(name, scif_offset, scif_size) \ 320#ifdef CONFIG_H8300
321/* h8300 don't have SCIF */
322#define CPU_SCIF_FNS(name) \
323 static inline unsigned int sci_##name##_in(struct uart_port *port) \
324 { \
325 return 0; \
326 } \
327 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
328 { \
329 }
330#else
331#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
318 static inline unsigned int sci_##name##_in(struct uart_port *port) \ 332 static inline unsigned int sci_##name##_in(struct uart_port *port) \
319 { \ 333 { \
320 SCI_IN(scif_size, scif_offset); \ 334 SCI_IN(scif_size, scif_offset); \
@@ -323,6 +337,7 @@
323 { \ 337 { \
324 SCI_OUT(scif_size, scif_offset, value); \ 338 SCI_OUT(scif_size, scif_offset, value); \
325 } 339 }
340#endif
326 341
327#define CPU_SCI_FNS(name, sci_offset, sci_size) \ 342#define CPU_SCI_FNS(name, sci_offset, sci_size) \
328 static inline unsigned int sci_##name##_in(struct uart_port* port) \ 343 static inline unsigned int sci_##name##_in(struct uart_port* port) \
@@ -360,8 +375,10 @@
360 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \ 375 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
361 h8_sci_offset, h8_sci_size) \ 376 h8_sci_offset, h8_sci_size) \
362 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size) 377 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
363#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) 378#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
364#elif defined(CONFIG_CPU_SUBTYPE_SH7723) 379 CPU_SCIF_FNS(name)
380#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
381 defined(CONFIG_CPU_SUBTYPE_SH7724)
365 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \ 382 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
366 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) 383 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
367 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \ 384 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
@@ -390,7 +407,8 @@ SCIF_FNS(SCFDR, 0x1c, 16)
390SCIF_FNS(SCxTDR, 0x20, 8) 407SCIF_FNS(SCxTDR, 0x20, 8)
391SCIF_FNS(SCxRDR, 0x24, 8) 408SCIF_FNS(SCxRDR, 0x24, 8)
392SCIF_FNS(SCLSR, 0x24, 16) 409SCIF_FNS(SCLSR, 0x24, 16)
393#elif defined(CONFIG_CPU_SUBTYPE_SH7723) 410#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
411 defined(CONFIG_CPU_SUBTYPE_SH7724)
394SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) 412SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
395SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8) 413SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
396SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16) 414SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
@@ -604,10 +622,21 @@ static inline int sci_rxd_in(struct uart_port *port)
604 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */ 622 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
605 return 1; 623 return 1;
606} 624}
625#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
626# define SCFSR 0x0010
627# define SCASSR 0x0014
628static inline int sci_rxd_in(struct uart_port *port)
629{
630 if (port->type == PORT_SCIF)
631 return ctrl_inw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0;
632 if (port->type == PORT_SCIFA)
633 return ctrl_inw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0;
634 return 1;
635}
607#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) 636#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
608static inline int sci_rxd_in(struct uart_port *port) 637static inline int sci_rxd_in(struct uart_port *port)
609{ 638{
610 return sci_in(port, SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ 639 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
611} 640}
612#elif defined(__H8300H__) || defined(__H8300S__) 641#elif defined(__H8300H__) || defined(__H8300S__)
613static inline int sci_rxd_in(struct uart_port *port) 642static inline int sci_rxd_in(struct uart_port *port)
@@ -757,7 +786,8 @@ static inline int sci_rxd_in(struct uart_port *port)
757 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 786 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
758 defined(CONFIG_CPU_SUBTYPE_SH7721) 787 defined(CONFIG_CPU_SUBTYPE_SH7721)
759#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) 788#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
760#elif defined(CONFIG_CPU_SUBTYPE_SH7723) 789#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
790 defined(CONFIG_CPU_SUBTYPE_SH7724)
761static inline int scbrr_calc(struct uart_port *port, int bps, int clk) 791static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
762{ 792{
763 if (port->type == PORT_SCIF) 793 if (port->type == PORT_SCIF)
diff --git a/drivers/sh/intc.c b/drivers/sh/intc.c
index 12d13d99b6f0..d687a9b93d03 100644
--- a/drivers/sh/intc.c
+++ b/drivers/sh/intc.c
@@ -24,6 +24,7 @@
24#include <linux/sh_intc.h> 24#include <linux/sh_intc.h>
25#include <linux/sysdev.h> 25#include <linux/sysdev.h>
26#include <linux/list.h> 26#include <linux/list.h>
27#include <linux/topology.h>
27 28
28#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \ 29#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
29 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \ 30 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
@@ -770,11 +771,19 @@ void __init register_intc_controller(struct intc_desc *desc)
770 /* register the vectors one by one */ 771 /* register the vectors one by one */
771 for (i = 0; i < desc->nr_vectors; i++) { 772 for (i = 0; i < desc->nr_vectors; i++) {
772 struct intc_vect *vect = desc->vectors + i; 773 struct intc_vect *vect = desc->vectors + i;
774 unsigned int irq = evt2irq(vect->vect);
775 struct irq_desc *irq_desc;
773 776
774 if (!vect->enum_id) 777 if (!vect->enum_id)
775 continue; 778 continue;
776 779
777 intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect)); 780 irq_desc = irq_to_desc_alloc_node(irq, numa_node_id());
781 if (unlikely(!irq_desc)) {
782 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
783 continue;
784 }
785
786 intc_register_irq(desc, d, vect->enum_id, irq);
778 } 787 }
779} 788}
780 789
diff --git a/drivers/video/hitfb.c b/drivers/video/hitfb.c
index e6467cf9f19f..020db7fc9153 100644
--- a/drivers/video/hitfb.c
+++ b/drivers/video/hitfb.c
@@ -335,9 +335,9 @@ static int __init hitfb_probe(struct platform_device *dev)
335 if (fb_get_options("hitfb", NULL)) 335 if (fb_get_options("hitfb", NULL))
336 return -ENODEV; 336 return -ENODEV;
337 337
338 hitfb_fix.mmio_start = CONFIG_HD64461_IOBASE+0x1000; 338 hitfb_fix.mmio_start = HD64461_IO_OFFSET(0x1000);
339 hitfb_fix.mmio_len = 0x1000; 339 hitfb_fix.mmio_len = 0x1000;
340 hitfb_fix.smem_start = CONFIG_HD64461_IOBASE + 0x02000000; 340 hitfb_fix.smem_start = HD64461_IO_OFFSET(0x02000000);
341 hitfb_fix.smem_len = 512 * 1024; 341 hitfb_fix.smem_len = 512 * 1024;
342 342
343 lcdclor = fb_readw(HD64461_LCDCLOR); 343 lcdclor = fb_readw(HD64461_LCDCLOR);
diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h
index 5a40d14daa9f..c56457c8334e 100644
--- a/include/linux/clocksource.h
+++ b/include/linux/clocksource.h
@@ -288,7 +288,15 @@ static inline cycle_t clocksource_read(struct clocksource *cs)
288 */ 288 */
289static inline int clocksource_enable(struct clocksource *cs) 289static inline int clocksource_enable(struct clocksource *cs)
290{ 290{
291 return cs->enable ? cs->enable(cs) : 0; 291 int ret = 0;
292
293 if (cs->enable)
294 ret = cs->enable(cs);
295
296 /* save mult_orig on enable */
297 cs->mult_orig = cs->mult;
298
299 return ret;
292} 300}
293 301
294/** 302/**
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index 893cc53486bc..1c297ddc9d5a 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -25,8 +25,7 @@ struct plat_sci_port {
25 unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */ 25 unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
26 unsigned int type; /* SCI / SCIF / IRDA */ 26 unsigned int type; /* SCI / SCIF / IRDA */
27 upf_t flags; /* UPF_* flags */ 27 upf_t flags; /* UPF_* flags */
28 char *clk; /* clock string */
28}; 29};
29 30
30int early_sci_setup(struct uart_port *port);
31
32#endif /* __LINUX_SERIAL_SCI_H */ 31#endif /* __LINUX_SERIAL_SCI_H */
diff --git a/include/linux/sh_cmt.h b/include/linux/sh_cmt.h
deleted file mode 100644
index 68cacde5954f..000000000000
--- a/include/linux/sh_cmt.h
+++ /dev/null
@@ -1,13 +0,0 @@
1#ifndef __SH_CMT_H__
2#define __SH_CMT_H__
3
4struct sh_cmt_config {
5 char *name;
6 unsigned long channel_offset;
7 int timer_bit;
8 char *clk;
9 unsigned long clockevent_rating;
10 unsigned long clocksource_rating;
11};
12
13#endif /* __SH_CMT_H__ */
diff --git a/include/linux/sh_timer.h b/include/linux/sh_timer.h
new file mode 100644
index 000000000000..864bd56bd3b0
--- /dev/null
+++ b/include/linux/sh_timer.h
@@ -0,0 +1,13 @@
1#ifndef __SH_TIMER_H__
2#define __SH_TIMER_H__
3
4struct sh_timer_config {
5 char *name;
6 long channel_offset;
7 int timer_bit;
8 char *clk;
9 unsigned long clockevent_rating;
10 unsigned long clocksource_rating;
11};
12
13#endif /* __SH_TIMER_H__ */
diff --git a/include/linux/time.h b/include/linux/time.h
index 242f62499bb7..ea16c1a01d51 100644
--- a/include/linux/time.h
+++ b/include/linux/time.h
@@ -113,6 +113,21 @@ struct timespec current_kernel_time(void);
113#define CURRENT_TIME (current_kernel_time()) 113#define CURRENT_TIME (current_kernel_time())
114#define CURRENT_TIME_SEC ((struct timespec) { get_seconds(), 0 }) 114#define CURRENT_TIME_SEC ((struct timespec) { get_seconds(), 0 })
115 115
116/* Some architectures do not supply their own clocksource.
117 * This is mainly the case in architectures that get their
118 * inter-tick times by reading the counter on their interval
119 * timer. Since these timers wrap every tick, they're not really
120 * useful as clocksources. Wrapping them to act like one is possible
121 * but not very efficient. So we provide a callout these arches
122 * can implement for use with the jiffies clocksource to provide
123 * finer then tick granular time.
124 */
125#ifdef CONFIG_ARCH_USES_GETTIMEOFFSET
126extern u32 arch_gettimeoffset(void);
127#else
128static inline u32 arch_gettimeoffset(void) { return 0; }
129#endif
130
116extern void do_gettimeofday(struct timeval *tv); 131extern void do_gettimeofday(struct timeval *tv);
117extern int do_settimeofday(struct timespec *tv); 132extern int do_settimeofday(struct timespec *tv);
118extern int do_sys_settimeofday(struct timespec *tv, struct timezone *tz); 133extern int do_sys_settimeofday(struct timespec *tv, struct timezone *tz);
diff --git a/kernel/time/clocksource.c b/kernel/time/clocksource.c
index ecfd7b5187e0..80189f6f1c5a 100644
--- a/kernel/time/clocksource.c
+++ b/kernel/time/clocksource.c
@@ -402,9 +402,6 @@ int clocksource_register(struct clocksource *c)
402 unsigned long flags; 402 unsigned long flags;
403 int ret; 403 int ret;
404 404
405 /* save mult_orig on registration */
406 c->mult_orig = c->mult;
407
408 spin_lock_irqsave(&clocksource_lock, flags); 405 spin_lock_irqsave(&clocksource_lock, flags);
409 ret = clocksource_enqueue(c); 406 ret = clocksource_enqueue(c);
410 if (!ret) 407 if (!ret)
diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c
index 52a8bf8931f3..e8c77d9c633a 100644
--- a/kernel/time/timekeeping.c
+++ b/kernel/time/timekeeping.c
@@ -77,6 +77,10 @@ static void clocksource_forward_now(void)
77 clock->cycle_last = cycle_now; 77 clock->cycle_last = cycle_now;
78 78
79 nsec = cyc2ns(clock, cycle_delta); 79 nsec = cyc2ns(clock, cycle_delta);
80
81 /* If arch requires, add in gettimeoffset() */
82 nsec += arch_gettimeoffset();
83
80 timespec_add_ns(&xtime, nsec); 84 timespec_add_ns(&xtime, nsec);
81 85
82 nsec = ((s64)cycle_delta * clock->mult_orig) >> clock->shift; 86 nsec = ((s64)cycle_delta * clock->mult_orig) >> clock->shift;
@@ -111,6 +115,9 @@ void getnstimeofday(struct timespec *ts)
111 /* convert to nanoseconds: */ 115 /* convert to nanoseconds: */
112 nsecs = cyc2ns(clock, cycle_delta); 116 nsecs = cyc2ns(clock, cycle_delta);
113 117
118 /* If arch requires, add in gettimeoffset() */
119 nsecs += arch_gettimeoffset();
120
114 } while (read_seqretry(&xtime_lock, seq)); 121 } while (read_seqretry(&xtime_lock, seq));
115 122
116 timespec_add_ns(ts, nsecs); 123 timespec_add_ns(ts, nsecs);
diff --git a/sound/oss/Kconfig b/sound/oss/Kconfig
index 1ca7427c4b6d..bcf2a0698d54 100644
--- a/sound/oss/Kconfig
+++ b/sound/oss/Kconfig
@@ -561,7 +561,7 @@ endif # SOUND_OSS
561 561
562config SOUND_SH_DAC_AUDIO 562config SOUND_SH_DAC_AUDIO
563 tristate "SuperH DAC audio support" 563 tristate "SuperH DAC audio support"
564 depends on CPU_SH3 564 depends on CPU_SH3 && HIGH_RES_TIMERS
565 565
566config SOUND_SH_DAC_AUDIO_CHANNEL 566config SOUND_SH_DAC_AUDIO_CHANNEL
567 int "DAC channel" 567 int "DAC channel"
diff --git a/sound/oss/sh_dac_audio.c b/sound/oss/sh_dac_audio.c
index 78cfb66e4c59..b2ed8757542a 100644
--- a/sound/oss/sh_dac_audio.c
+++ b/sound/oss/sh_dac_audio.c
@@ -18,47 +18,36 @@
18#include <linux/sound.h> 18#include <linux/sound.h>
19#include <linux/soundcard.h> 19#include <linux/soundcard.h>
20#include <linux/interrupt.h> 20#include <linux/interrupt.h>
21#include <linux/hrtimer.h>
21#include <asm/io.h> 22#include <asm/io.h>
22#include <asm/uaccess.h> 23#include <asm/uaccess.h>
23#include <asm/irq.h> 24#include <asm/irq.h>
24#include <asm/delay.h> 25#include <asm/delay.h>
25#include <asm/clock.h> 26#include <asm/clock.h>
26#include <asm/cpu/dac.h> 27#include <cpu/dac.h>
27#include <asm/cpu/timer.h>
28#include <asm/machvec.h> 28#include <asm/machvec.h>
29#include <mach/hp6xx.h> 29#include <mach/hp6xx.h>
30#include <asm/hd64461.h> 30#include <asm/hd64461.h>
31 31
32#define MODNAME "sh_dac_audio" 32#define MODNAME "sh_dac_audio"
33 33
34#define TMU_TOCR_INIT 0x00
35
36#define TMU1_TCR_INIT 0x0020 /* Clock/4, rising edge; interrupt on */
37#define TMU1_TSTR_INIT 0x02 /* Bit to turn on TMU1 */
38
39#define BUFFER_SIZE 48000 34#define BUFFER_SIZE 48000
40 35
41static int rate; 36static int rate;
42static int empty; 37static int empty;
43static char *data_buffer, *buffer_begin, *buffer_end; 38static char *data_buffer, *buffer_begin, *buffer_end;
44static int in_use, device_major; 39static int in_use, device_major;
40static struct hrtimer hrtimer;
41static ktime_t wakeups_per_second;
45 42
46static void dac_audio_start_timer(void) 43static void dac_audio_start_timer(void)
47{ 44{
48 u8 tstr; 45 hrtimer_start(&hrtimer, wakeups_per_second, HRTIMER_MODE_REL);
49
50 tstr = ctrl_inb(TMU_TSTR);
51 tstr |= TMU1_TSTR_INIT;
52 ctrl_outb(tstr, TMU_TSTR);
53} 46}
54 47
55static void dac_audio_stop_timer(void) 48static void dac_audio_stop_timer(void)
56{ 49{
57 u8 tstr; 50 hrtimer_cancel(&hrtimer);
58
59 tstr = ctrl_inb(TMU_TSTR);
60 tstr &= ~TMU1_TSTR_INIT;
61 ctrl_outb(tstr, TMU_TSTR);
62} 51}
63 52
64static void dac_audio_reset(void) 53static void dac_audio_reset(void)
@@ -77,38 +66,30 @@ static void dac_audio_sync(void)
77static void dac_audio_start(void) 66static void dac_audio_start(void)
78{ 67{
79 if (mach_is_hp6xx()) { 68 if (mach_is_hp6xx()) {
80 u16 v = inw(HD64461_GPADR); 69 u16 v = __raw_readw(HD64461_GPADR);
81 v &= ~HD64461_GPADR_SPEAKER; 70 v &= ~HD64461_GPADR_SPEAKER;
82 outw(v, HD64461_GPADR); 71 __raw_writew(v, HD64461_GPADR);
83 } 72 }
84 73
85 sh_dac_enable(CONFIG_SOUND_SH_DAC_AUDIO_CHANNEL); 74 sh_dac_enable(CONFIG_SOUND_SH_DAC_AUDIO_CHANNEL);
86 ctrl_outw(TMU1_TCR_INIT, TMU1_TCR);
87} 75}
88static void dac_audio_stop(void) 76static void dac_audio_stop(void)
89{ 77{
90 dac_audio_stop_timer(); 78 dac_audio_stop_timer();
91 79
92 if (mach_is_hp6xx()) { 80 if (mach_is_hp6xx()) {
93 u16 v = inw(HD64461_GPADR); 81 u16 v = __raw_readw(HD64461_GPADR);
94 v |= HD64461_GPADR_SPEAKER; 82 v |= HD64461_GPADR_SPEAKER;
95 outw(v, HD64461_GPADR); 83 __raw_writew(v, HD64461_GPADR);
96 } 84 }
97 85
98 sh_dac_output(0, CONFIG_SOUND_SH_DAC_AUDIO_CHANNEL); 86 sh_dac_output(0, CONFIG_SOUND_SH_DAC_AUDIO_CHANNEL);
99 sh_dac_disable(CONFIG_SOUND_SH_DAC_AUDIO_CHANNEL); 87 sh_dac_disable(CONFIG_SOUND_SH_DAC_AUDIO_CHANNEL);
100} 88}
101 89
102static void dac_audio_set_rate(void) 90static void dac_audio_set_rate(void)
103{ 91{
104 unsigned long interval; 92 wakeups_per_second = ktime_set(0, 1000000000 / rate);
105 struct clk *clk;
106
107 clk = clk_get(NULL, "module_clk");
108 interval = (clk_get_rate(clk) / 4) / rate;
109 clk_put(clk);
110 ctrl_outl(interval, TMU1_TCOR);
111 ctrl_outl(interval, TMU1_TCNT);
112} 93}
113 94
114static int dac_audio_ioctl(struct inode *inode, struct file *file, 95static int dac_audio_ioctl(struct inode *inode, struct file *file,
@@ -265,32 +246,26 @@ const struct file_operations dac_audio_fops = {
265 .release = dac_audio_release, 246 .release = dac_audio_release,
266}; 247};
267 248
268static irqreturn_t timer1_interrupt(int irq, void *dev) 249static enum hrtimer_restart sh_dac_audio_timer(struct hrtimer *handle)
269{ 250{
270 unsigned long timer_status;
271
272 timer_status = ctrl_inw(TMU1_TCR);
273 timer_status &= ~0x100;
274 ctrl_outw(timer_status, TMU1_TCR);
275
276 if (!empty) { 251 if (!empty) {
277 sh_dac_output(*buffer_begin, CONFIG_SOUND_SH_DAC_AUDIO_CHANNEL); 252 sh_dac_output(*buffer_begin, CONFIG_SOUND_SH_DAC_AUDIO_CHANNEL);
278 buffer_begin++; 253 buffer_begin++;
279 254
280 if (buffer_begin == data_buffer + BUFFER_SIZE) 255 if (buffer_begin == data_buffer + BUFFER_SIZE)
281 buffer_begin = data_buffer; 256 buffer_begin = data_buffer;
282 if (buffer_begin == buffer_end) { 257 if (buffer_begin == buffer_end)
283 empty = 1; 258 empty = 1;
284 dac_audio_stop_timer();
285 }
286 } 259 }
287 return IRQ_HANDLED; 260
261 if (!empty)
262 hrtimer_start(&hrtimer, wakeups_per_second, HRTIMER_MODE_REL);
263
264 return HRTIMER_NORESTART;
288} 265}
289 266
290static int __init dac_audio_init(void) 267static int __init dac_audio_init(void)
291{ 268{
292 int retval;
293
294 if ((device_major = register_sound_dsp(&dac_audio_fops, -1)) < 0) { 269 if ((device_major = register_sound_dsp(&dac_audio_fops, -1)) < 0) {
295 printk(KERN_ERR "Cannot register dsp device"); 270 printk(KERN_ERR "Cannot register dsp device");
296 return device_major; 271 return device_major;
@@ -306,21 +281,25 @@ static int __init dac_audio_init(void)
306 rate = 8000; 281 rate = 8000;
307 dac_audio_set_rate(); 282 dac_audio_set_rate();
308 283
309 retval = 284 /* Today: High Resolution Timer driven DAC playback.
310 request_irq(TIMER1_IRQ, timer1_interrupt, IRQF_DISABLED, MODNAME, 0); 285 * The timer callback gets called once per sample. Ouch.
311 if (retval < 0) { 286 *
312 printk(KERN_ERR "sh_dac_audio: IRQ %d request failed\n", 287 * Future: A much better approach would be to use the
313 TIMER1_IRQ); 288 * SH7720 CMT+DMAC+DAC hardware combination like this:
314 return retval; 289 * - Program sample rate using CMT0 or CMT1
315 } 290 * - Program DMAC to use CMT for timing and output to DAC
291 * - Play sound using DMAC, let CPU sleep.
292 * - While at it, rewrite this driver to use ALSA.
293 */
294
295 hrtimer_init(&hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
296 hrtimer.function = sh_dac_audio_timer;
316 297
317 return 0; 298 return 0;
318} 299}
319 300
320static void __exit dac_audio_exit(void) 301static void __exit dac_audio_exit(void)
321{ 302{
322 free_irq(TIMER1_IRQ, 0);
323
324 unregister_sound_dsp(device_major); 303 unregister_sound_dsp(device_major);
325 kfree((void *)data_buffer); 304 kfree((void *)data_buffer);
326} 305}