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-rw-r--r--arch/arm/mach-omap2/sram242x.S4
-rw-r--r--arch/arm/mach-omap2/sram243x.S4
-rw-r--r--arch/arm/plat-omap/common.c69
-rw-r--r--arch/arm/plat-omap/include/mach/omap24xx.h2
-rw-r--r--arch/arm/plat-omap/include/mach/omap34xx.h1
5 files changed, 62 insertions, 18 deletions
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index af4bd3490227..cbb893042487 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -128,7 +128,7 @@ omap242x_sdi_prcm_voltctrl:
128prcm_mask_val: 128prcm_mask_val:
129 .word 0xFFFF3FFC 129 .word 0xFFFF3FFC
130omap242x_sdi_timer_32ksynct_cr: 130omap242x_sdi_timer_32ksynct_cr:
131 .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) 131 .word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
132ENTRY(omap242x_sram_ddr_init_sz) 132ENTRY(omap242x_sram_ddr_init_sz)
133 .word . - omap242x_sram_ddr_init 133 .word . - omap242x_sram_ddr_init
134 134
@@ -224,7 +224,7 @@ omap242x_srs_prcm_voltctrl:
224ddr_prcm_mask_val: 224ddr_prcm_mask_val:
225 .word 0xFFFF3FFC 225 .word 0xFFFF3FFC
226omap242x_srs_timer_32ksynct: 226omap242x_srs_timer_32ksynct:
227 .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) 227 .word IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
228 228
229ENTRY(omap242x_sram_reprogram_sdrc_sz) 229ENTRY(omap242x_sram_reprogram_sdrc_sz)
230 .word . - omap242x_sram_reprogram_sdrc 230 .word . - omap242x_sram_reprogram_sdrc
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index 84363e269e8c..054b0f357aca 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -128,7 +128,7 @@ omap243x_sdi_prcm_voltctrl:
128prcm_mask_val: 128prcm_mask_val:
129 .word 0xFFFF3FFC 129 .word 0xFFFF3FFC
130omap243x_sdi_timer_32ksynct_cr: 130omap243x_sdi_timer_32ksynct_cr:
131 .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) 131 .word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
132ENTRY(omap243x_sram_ddr_init_sz) 132ENTRY(omap243x_sram_ddr_init_sz)
133 .word . - omap243x_sram_ddr_init 133 .word . - omap243x_sram_ddr_init
134 134
@@ -224,7 +224,7 @@ omap243x_srs_prcm_voltctrl:
224ddr_prcm_mask_val: 224ddr_prcm_mask_val:
225 .word 0xFFFF3FFC 225 .word 0xFFFF3FFC
226omap243x_srs_timer_32ksynct: 226omap243x_srs_timer_32ksynct:
227 .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010) 227 .word IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
228 228
229ENTRY(omap243x_sram_reprogram_sdrc_sz) 229ENTRY(omap243x_sram_reprogram_sdrc_sz)
230 .word . - omap243x_sram_reprogram_sdrc 230 .word . - omap243x_sram_reprogram_sdrc
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 433021f3d7cc..e1add789835f 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -175,25 +175,61 @@ console_initcall(omap_add_serial_console);
175 * but systems won't necessarily want to spend resources that way. 175 * but systems won't necessarily want to spend resources that way.
176 */ 176 */
177 177
178#if defined(CONFIG_ARCH_OMAP16XX) 178#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410
179#define TIMER_32K_SYNCHRONIZED 0xfffbc410
180#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
181#define TIMER_32K_SYNCHRONIZED (OMAP2_32KSYNCT_BASE + 0x10)
182#endif
183 179
184#ifdef TIMER_32K_SYNCHRONIZED 180#if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX))
185 181
186#include <linux/clocksource.h> 182#include <linux/clocksource.h>
187 183
188static cycle_t omap_32k_read(struct clocksource *cs) 184#ifdef CONFIG_ARCH_OMAP16XX
185static cycle_t omap16xx_32k_read(struct clocksource *cs)
186{
187 return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED);
188}
189#else
190#define omap16xx_32k_read NULL
191#endif
192
193#ifdef CONFIG_ARCH_OMAP2420
194static cycle_t omap2420_32k_read(struct clocksource *cs)
195{
196 return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10);
197}
198#else
199#define omap2420_32k_read NULL
200#endif
201
202#ifdef CONFIG_ARCH_OMAP2430
203static cycle_t omap2430_32k_read(struct clocksource *cs)
204{
205 return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10);
206}
207#else
208#define omap2430_32k_read NULL
209#endif
210
211#ifdef CONFIG_ARCH_OMAP34XX
212static cycle_t omap34xx_32k_read(struct clocksource *cs)
189{ 213{
190 return omap_readl(TIMER_32K_SYNCHRONIZED); 214 return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10);
215}
216#else
217#define omap34xx_32k_read NULL
218#endif
219
220/*
221 * Kernel assumes that sched_clock can be called early but may not have
222 * things ready yet.
223 */
224static cycle_t omap_32k_read_dummy(struct clocksource *cs)
225{
226 return 0;
191} 227}
192 228
193static struct clocksource clocksource_32k = { 229static struct clocksource clocksource_32k = {
194 .name = "32k_counter", 230 .name = "32k_counter",
195 .rating = 250, 231 .rating = 250,
196 .read = omap_32k_read, 232 .read = omap_32k_read_dummy,
197 .mask = CLOCKSOURCE_MASK(32), 233 .mask = CLOCKSOURCE_MASK(32),
198 .shift = 10, 234 .shift = 10,
199 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 235 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
@@ -207,7 +243,7 @@ unsigned long long sched_clock(void)
207{ 243{
208 unsigned long long ret; 244 unsigned long long ret;
209 245
210 ret = (unsigned long long)omap_32k_read(&clocksource_32k); 246 ret = (unsigned long long)clocksource_32k.read(&clocksource_32k);
211 ret = (ret * clocksource_32k.mult_orig) >> clocksource_32k.shift; 247 ret = (ret * clocksource_32k.mult_orig) >> clocksource_32k.shift;
212 return ret; 248 return ret;
213} 249}
@@ -220,6 +256,17 @@ static int __init omap_init_clocksource_32k(void)
220 if (cpu_is_omap16xx() || cpu_class_is_omap2()) { 256 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
221 struct clk *sync_32k_ick; 257 struct clk *sync_32k_ick;
222 258
259 if (cpu_is_omap16xx())
260 clocksource_32k.read = omap16xx_32k_read;
261 else if (cpu_is_omap2420())
262 clocksource_32k.read = omap2420_32k_read;
263 else if (cpu_is_omap2430())
264 clocksource_32k.read = omap2430_32k_read;
265 else if (cpu_is_omap34xx())
266 clocksource_32k.read = omap34xx_32k_read;
267 else
268 return -ENODEV;
269
223 sync_32k_ick = clk_get(NULL, "omap_32ksync_ick"); 270 sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
224 if (sync_32k_ick) 271 if (sync_32k_ick)
225 clk_enable(sync_32k_ick); 272 clk_enable(sync_32k_ick);
@@ -234,7 +281,7 @@ static int __init omap_init_clocksource_32k(void)
234} 281}
235arch_initcall(omap_init_clocksource_32k); 282arch_initcall(omap_init_clocksource_32k);
236 283
237#endif /* TIMER_32K_SYNCHRONIZED */ 284#endif /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */
238 285
239/* Global address base setup code */ 286/* Global address base setup code */
240 287
diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/mach/omap24xx.h
index 24335d4932f5..4202cf457e22 100644
--- a/arch/arm/plat-omap/include/mach/omap24xx.h
+++ b/arch/arm/plat-omap/include/mach/omap24xx.h
@@ -87,7 +87,6 @@
87 87
88#if defined(CONFIG_ARCH_OMAP2420) 88#if defined(CONFIG_ARCH_OMAP2420)
89 89
90#define OMAP2_32KSYNCT_BASE OMAP2420_32KSYNCT_BASE
91#define OMAP2_PRCM_BASE OMAP2420_PRCM_BASE 90#define OMAP2_PRCM_BASE OMAP2420_PRCM_BASE
92#define OMAP2_CM_BASE OMAP2420_CM_BASE 91#define OMAP2_CM_BASE OMAP2420_CM_BASE
93#define OMAP2_PRM_BASE OMAP2420_PRM_BASE 92#define OMAP2_PRM_BASE OMAP2420_PRM_BASE
@@ -95,7 +94,6 @@
95 94
96#elif defined(CONFIG_ARCH_OMAP2430) 95#elif defined(CONFIG_ARCH_OMAP2430)
97 96
98#define OMAP2_32KSYNCT_BASE OMAP2430_32KSYNCT_BASE
99#define OMAP2_PRCM_BASE OMAP2430_PRCM_BASE 97#define OMAP2_PRCM_BASE OMAP2430_PRCM_BASE
100#define OMAP2_CM_BASE OMAP2430_CM_BASE 98#define OMAP2_CM_BASE OMAP2430_CM_BASE
101#define OMAP2_PRM_BASE OMAP2430_PRM_BASE 99#define OMAP2_PRM_BASE OMAP2430_PRM_BASE
diff --git a/arch/arm/plat-omap/include/mach/omap34xx.h b/arch/arm/plat-omap/include/mach/omap34xx.h
index ab640151d3ec..581d9103c35d 100644
--- a/arch/arm/plat-omap/include/mach/omap34xx.h
+++ b/arch/arm/plat-omap/include/mach/omap34xx.h
@@ -85,7 +85,6 @@
85 85
86#if defined(CONFIG_ARCH_OMAP3430) 86#if defined(CONFIG_ARCH_OMAP3430)
87 87
88#define OMAP2_32KSYNCT_BASE OMAP3430_32KSYNCT_BASE
89#define OMAP2_CM_BASE OMAP3430_CM_BASE 88#define OMAP2_CM_BASE OMAP3430_CM_BASE
90#define OMAP2_PRM_BASE OMAP3430_PRM_BASE 89#define OMAP2_PRM_BASE OMAP3430_PRM_BASE
91#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE) 90#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE)