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-rw-r--r--arch/arm/mach-s3c2410/Makefile1
-rw-r--r--arch/arm/mach-s3c2410/s3c2412-dma.c160
-rw-r--r--include/asm-arm/arch-s3c2410/dma.h32
3 files changed, 193 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 23f0909915db..0d87a9de0034 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
34obj-$(CONFIG_CPU_S3C2412) += s3c2412.o 34obj-$(CONFIG_CPU_S3C2412) += s3c2412.o
35obj-$(CONFIG_CPU_S3C2412) += s3c2412-irq.o 35obj-$(CONFIG_CPU_S3C2412) += s3c2412-irq.o
36obj-$(CONFIG_CPU_S3C2412) += s3c2412-clock.o 36obj-$(CONFIG_CPU_S3C2412) += s3c2412-clock.o
37obj-dma-$(CONFIG_CPU_S3C2412) += s3c2412-dma.o
37 38
38# 39#
39# S3C244X support 40# S3C244X support
diff --git a/arch/arm/mach-s3c2410/s3c2412-dma.c b/arch/arm/mach-s3c2410/s3c2412-dma.c
new file mode 100644
index 000000000000..171f3706d36d
--- /dev/null
+++ b/arch/arm/mach-s3c2410/s3c2412-dma.c
@@ -0,0 +1,160 @@
1/* linux/arch/arm/mach-s3c2410/s3c2412-dma.c
2 *
3 * (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2412 DMA selection
7 *
8 * http://armlinux.simtec.co.uk/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/sysdev.h>
18
19#include <asm/dma.h>
20#include <asm/arch/dma.h>
21#include <asm/io.h>
22
23#include "dma.h"
24#include "cpu.h"
25
26#include <asm/arch/regs-serial.h>
27#include <asm/arch/regs-gpio.h>
28#include <asm/arch/regs-ac97.h>
29#include <asm/arch/regs-mem.h>
30#include <asm/arch/regs-lcd.h>
31#include <asm/arch/regs-sdi.h>
32#include <asm/arch/regs-iis.h>
33#include <asm/arch/regs-spi.h>
34
35#define MAP(x) { (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID, (x)| DMA_CH_VALID }
36
37static struct s3c24xx_dma_map __initdata s3c2412_dma_mappings[] = {
38 [DMACH_XD0] = {
39 .name = "xdreq0",
40 .channels = MAP(S3C2412_DMAREQSEL_XDREQ0),
41 },
42 [DMACH_XD1] = {
43 .name = "xdreq1",
44 .channels = MAP(S3C2412_DMAREQSEL_XDREQ1),
45 },
46 [DMACH_SDI] = {
47 .name = "sdi",
48 .channels = MAP(S3C2412_DMAREQSEL_SDI),
49 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
50 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
51 },
52 [DMACH_SPI0] = {
53 .name = "spi0",
54 .channels = MAP(S3C2412_DMAREQSEL_SPI0TX),
55 .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
56 .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
57 },
58 [DMACH_SPI1] = {
59 .name = "spi1",
60 .channels = MAP(S3C2412_DMAREQSEL_SPI1TX),
61 .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
62 .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
63 },
64 [DMACH_UART0] = {
65 .name = "uart0",
66 .channels = MAP(S3C2412_DMAREQSEL_UART0_0),
67 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
68 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
69 },
70 [DMACH_UART1] = {
71 .name = "uart1",
72 .channels = MAP(S3C2412_DMAREQSEL_UART1_0),
73 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
74 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
75 },
76 [DMACH_UART2] = {
77 .name = "uart2",
78 .channels = MAP(S3C2412_DMAREQSEL_UART2_0),
79 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
80 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
81 },
82 [DMACH_UART0_SRC2] = {
83 .name = "uart0",
84 .channels = MAP(S3C2412_DMAREQSEL_UART0_1),
85 .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
86 .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
87 },
88 [DMACH_UART1_SRC2] = {
89 .name = "uart1",
90 .channels = MAP(S3C2412_DMAREQSEL_UART1_1),
91 .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
92 .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
93 },
94 [DMACH_UART2_SRC2] = {
95 .name = "uart2",
96 .channels = MAP(S3C2412_DMAREQSEL_UART2_1),
97 .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
98 .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
99 },
100 [DMACH_TIMER] = {
101 .name = "timer",
102 .channels = MAP(S3C2412_DMAREQSEL_TIMER),
103 },
104 [DMACH_I2S_IN] = {
105 .name = "i2s-sdi",
106 .channels = MAP(S3C2412_DMAREQSEL_I2SRX),
107 .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
108 },
109 [DMACH_I2S_OUT] = {
110 .name = "i2s-sdo",
111 .channels = MAP(S3C2412_DMAREQSEL_I2STX),
112 .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
113 },
114 [DMACH_USB_EP1] = {
115 .name = "usb-ep1",
116 .channels = MAP(S3C2412_DMAREQSEL_USBEP1),
117 },
118 [DMACH_USB_EP2] = {
119 .name = "usb-ep2",
120 .channels = MAP(S3C2412_DMAREQSEL_USBEP2),
121 },
122 [DMACH_USB_EP3] = {
123 .name = "usb-ep3",
124 .channels = MAP(S3C2412_DMAREQSEL_USBEP3),
125 },
126 [DMACH_USB_EP4] = {
127 .name = "usb-ep4",
128 .channels = MAP(S3C2412_DMAREQSEL_USBEP4),
129 },
130};
131
132static void s3c2412_dma_select(struct s3c2410_dma_chan *chan,
133 struct s3c24xx_dma_map *map)
134{
135 writel(chan->regs + S3C2412_DMA_DMAREQSEL,
136 map->channels[0] | S3C2412_DMAREQSEL_HW);
137}
138
139static struct s3c24xx_dma_selection __initdata s3c2412_dma_sel = {
140 .select = s3c2412_dma_select,
141 .dcon_mask = 0,
142 .map = s3c2412_dma_mappings,
143 .map_size = ARRAY_SIZE(s3c2412_dma_mappings),
144};
145
146static int s3c2412_dma_add(struct sys_device *sysdev)
147{
148 return s3c24xx_dma_init_map(&s3c2412_dma_sel);
149}
150
151static struct sysdev_driver s3c2412_dma_driver = {
152 .add = s3c2412_dma_add,
153};
154
155static int __init s3c2412_dma_init(void)
156{
157 return sysdev_driver_register(&s3c2412_sysclass, &s3c2412_dma_driver);
158}
159
160arch_initcall(s3c2412_dma_init);
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
index 166fc89d62d7..7ac224836971 100644
--- a/include/asm-arm/arch-s3c2410/dma.h
+++ b/include/asm-arm/arch-s3c2410/dma.h
@@ -48,6 +48,9 @@ enum dma_ch {
48 DMACH_USB_EP2, 48 DMACH_USB_EP2,
49 DMACH_USB_EP3, 49 DMACH_USB_EP3,
50 DMACH_USB_EP4, 50 DMACH_USB_EP4,
51 DMACH_UART0_SRC2, /* s3c2412 second uart sources */
52 DMACH_UART1_SRC2,
53 DMACH_UART2_SRC2,
51 DMACH_MAX, /* the end entry */ 54 DMACH_MAX, /* the end entry */
52}; 55};
53 56
@@ -317,6 +320,7 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
317#define S3C2410_DMA_DCSRC (0x18) 320#define S3C2410_DMA_DCSRC (0x18)
318#define S3C2410_DMA_DCDST (0x1C) 321#define S3C2410_DMA_DCDST (0x1C)
319#define S3C2410_DMA_DMASKTRIG (0x20) 322#define S3C2410_DMA_DMASKTRIG (0x20)
323#define S3C2412_DMA_DMAREQSEL (0x24)
320 324
321#define S3C2410_DISRCC_INC (1<<0) 325#define S3C2410_DISRCC_INC (1<<0)
322#define S3C2410_DISRCC_APB (1<<1) 326#define S3C2410_DISRCC_APB (1<<1)
@@ -383,4 +387,32 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
383#define S3C2440_DCON_CH3_PCMOUT (6<<24) 387#define S3C2440_DCON_CH3_PCMOUT (6<<24)
384#endif 388#endif
385 389
390#ifdef CONFIG_CPU_S3C2412
391
392#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
393
394#define S3C2412_DMAREQSEL_HW (1)
395
396#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
397#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
398#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
399#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
400#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
401#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
402#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
403#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
404#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
405#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
406#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
407#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
408#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
409#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
410#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
411#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
412#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
413#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
414#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
415#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
416
417#endif
386#endif /* __ASM_ARCH_DMA_H */ 418#endif /* __ASM_ARCH_DMA_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-06 04:26:09 -0500