diff options
-rw-r--r-- | drivers/net/e1000e/defines.h | 1 | ||||
-rw-r--r-- | drivers/net/e1000e/e1000.h | 2 | ||||
-rw-r--r-- | drivers/net/e1000e/es2lan.c | 127 | ||||
-rw-r--r-- | drivers/net/e1000e/phy.c | 73 |
4 files changed, 137 insertions, 66 deletions
diff --git a/drivers/net/e1000e/defines.h b/drivers/net/e1000e/defines.h index 4fb9d8722739..2a53875cddbf 100644 --- a/drivers/net/e1000e/defines.h +++ b/drivers/net/e1000e/defines.h | |||
@@ -184,6 +184,7 @@ | |||
184 | #define E1000_SWFW_EEP_SM 0x1 | 184 | #define E1000_SWFW_EEP_SM 0x1 |
185 | #define E1000_SWFW_PHY0_SM 0x2 | 185 | #define E1000_SWFW_PHY0_SM 0x2 |
186 | #define E1000_SWFW_PHY1_SM 0x4 | 186 | #define E1000_SWFW_PHY1_SM 0x4 |
187 | #define E1000_SWFW_CSR_SM 0x8 | ||
187 | 188 | ||
188 | /* Device Control */ | 189 | /* Device Control */ |
189 | #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ | 190 | #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ |
diff --git a/drivers/net/e1000e/e1000.h b/drivers/net/e1000e/e1000.h index 79a426feffb7..f6835c321516 100644 --- a/drivers/net/e1000e/e1000.h +++ b/drivers/net/e1000e/e1000.h | |||
@@ -449,6 +449,8 @@ extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); | |||
449 | extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, | 449 | extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, |
450 | u32 usec_interval, bool *success); | 450 | u32 usec_interval, bool *success); |
451 | extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); | 451 | extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw); |
452 | extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); | ||
453 | extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); | ||
452 | extern s32 e1000e_check_downshift(struct e1000_hw *hw); | 454 | extern s32 e1000e_check_downshift(struct e1000_hw *hw); |
453 | 455 | ||
454 | static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) | 456 | static inline s32 e1000_phy_hw_reset(struct e1000_hw *hw) |
diff --git a/drivers/net/e1000e/es2lan.c b/drivers/net/e1000e/es2lan.c index 13a6f4484de9..dc552d7d6fac 100644 --- a/drivers/net/e1000e/es2lan.c +++ b/drivers/net/e1000e/es2lan.c | |||
@@ -41,6 +41,7 @@ | |||
41 | #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 | 41 | #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 |
42 | #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 | 42 | #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 |
43 | #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 | 43 | #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 |
44 | #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F | ||
44 | 45 | ||
45 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 | 46 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 |
46 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 | 47 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 |
@@ -48,6 +49,7 @@ | |||
48 | 49 | ||
49 | #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 | 50 | #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 |
50 | #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 | 51 | #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 |
52 | #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 | ||
51 | 53 | ||
52 | #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ | 54 | #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ |
53 | #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 | 55 | #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 |
@@ -85,6 +87,9 @@ | |||
85 | /* Kumeran Mode Control Register (Page 193, Register 16) */ | 87 | /* Kumeran Mode Control Register (Page 193, Register 16) */ |
86 | #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 | 88 | #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 |
87 | 89 | ||
90 | /* Max number of times Kumeran read/write should be validated */ | ||
91 | #define GG82563_MAX_KMRN_RETRY 0x5 | ||
92 | |||
88 | /* Power Management Control Register (Page 193, Register 20) */ | 93 | /* Power Management Control Register (Page 193, Register 20) */ |
89 | #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 | 94 | #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 |
90 | /* 1=Enable SERDES Electrical Idle */ | 95 | /* 1=Enable SERDES Electrical Idle */ |
@@ -270,6 +275,7 @@ static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw) | |||
270 | u16 mask; | 275 | u16 mask; |
271 | 276 | ||
272 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; | 277 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; |
278 | mask |= E1000_SWFW_CSR_SM; | ||
273 | 279 | ||
274 | return e1000_acquire_swfw_sync_80003es2lan(hw, mask); | 280 | return e1000_acquire_swfw_sync_80003es2lan(hw, mask); |
275 | } | 281 | } |
@@ -286,6 +292,8 @@ static void e1000_release_phy_80003es2lan(struct e1000_hw *hw) | |||
286 | u16 mask; | 292 | u16 mask; |
287 | 293 | ||
288 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; | 294 | mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM; |
295 | mask |= E1000_SWFW_CSR_SM; | ||
296 | |||
289 | e1000_release_swfw_sync_80003es2lan(hw, mask); | 297 | e1000_release_swfw_sync_80003es2lan(hw, mask); |
290 | } | 298 | } |
291 | 299 | ||
@@ -410,20 +418,27 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, | |||
410 | u32 page_select; | 418 | u32 page_select; |
411 | u16 temp; | 419 | u16 temp; |
412 | 420 | ||
421 | ret_val = e1000_acquire_phy_80003es2lan(hw); | ||
422 | if (ret_val) | ||
423 | return ret_val; | ||
424 | |||
413 | /* Select Configuration Page */ | 425 | /* Select Configuration Page */ |
414 | if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) | 426 | if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
415 | page_select = GG82563_PHY_PAGE_SELECT; | 427 | page_select = GG82563_PHY_PAGE_SELECT; |
416 | else | 428 | } else { |
417 | /* | 429 | /* |
418 | * Use Alternative Page Select register to access | 430 | * Use Alternative Page Select register to access |
419 | * registers 30 and 31 | 431 | * registers 30 and 31 |
420 | */ | 432 | */ |
421 | page_select = GG82563_PHY_PAGE_SELECT_ALT; | 433 | page_select = GG82563_PHY_PAGE_SELECT_ALT; |
434 | } | ||
422 | 435 | ||
423 | temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); | 436 | temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); |
424 | ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp); | 437 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); |
425 | if (ret_val) | 438 | if (ret_val) { |
439 | e1000_release_phy_80003es2lan(hw); | ||
426 | return ret_val; | 440 | return ret_val; |
441 | } | ||
427 | 442 | ||
428 | /* | 443 | /* |
429 | * The "ready" bit in the MDIC register may be incorrectly set | 444 | * The "ready" bit in the MDIC register may be incorrectly set |
@@ -433,20 +448,21 @@ static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, | |||
433 | udelay(200); | 448 | udelay(200); |
434 | 449 | ||
435 | /* ...and verify the command was successful. */ | 450 | /* ...and verify the command was successful. */ |
436 | ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp); | 451 | ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); |
437 | 452 | ||
438 | if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { | 453 | if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { |
439 | ret_val = -E1000_ERR_PHY; | 454 | ret_val = -E1000_ERR_PHY; |
455 | e1000_release_phy_80003es2lan(hw); | ||
440 | return ret_val; | 456 | return ret_val; |
441 | } | 457 | } |
442 | 458 | ||
443 | udelay(200); | 459 | udelay(200); |
444 | 460 | ||
445 | ret_val = e1000e_read_phy_reg_m88(hw, | 461 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
446 | MAX_PHY_REG_ADDRESS & offset, | 462 | data); |
447 | data); | ||
448 | 463 | ||
449 | udelay(200); | 464 | udelay(200); |
465 | e1000_release_phy_80003es2lan(hw); | ||
450 | 466 | ||
451 | return ret_val; | 467 | return ret_val; |
452 | } | 468 | } |
@@ -467,20 +483,27 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, | |||
467 | u32 page_select; | 483 | u32 page_select; |
468 | u16 temp; | 484 | u16 temp; |
469 | 485 | ||
486 | ret_val = e1000_acquire_phy_80003es2lan(hw); | ||
487 | if (ret_val) | ||
488 | return ret_val; | ||
489 | |||
470 | /* Select Configuration Page */ | 490 | /* Select Configuration Page */ |
471 | if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) | 491 | if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) { |
472 | page_select = GG82563_PHY_PAGE_SELECT; | 492 | page_select = GG82563_PHY_PAGE_SELECT; |
473 | else | 493 | } else { |
474 | /* | 494 | /* |
475 | * Use Alternative Page Select register to access | 495 | * Use Alternative Page Select register to access |
476 | * registers 30 and 31 | 496 | * registers 30 and 31 |
477 | */ | 497 | */ |
478 | page_select = GG82563_PHY_PAGE_SELECT_ALT; | 498 | page_select = GG82563_PHY_PAGE_SELECT_ALT; |
499 | } | ||
479 | 500 | ||
480 | temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); | 501 | temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT); |
481 | ret_val = e1000e_write_phy_reg_m88(hw, page_select, temp); | 502 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp); |
482 | if (ret_val) | 503 | if (ret_val) { |
504 | e1000_release_phy_80003es2lan(hw); | ||
483 | return ret_val; | 505 | return ret_val; |
506 | } | ||
484 | 507 | ||
485 | 508 | ||
486 | /* | 509 | /* |
@@ -491,18 +514,20 @@ static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, | |||
491 | udelay(200); | 514 | udelay(200); |
492 | 515 | ||
493 | /* ...and verify the command was successful. */ | 516 | /* ...and verify the command was successful. */ |
494 | ret_val = e1000e_read_phy_reg_m88(hw, page_select, &temp); | 517 | ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp); |
495 | 518 | ||
496 | if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) | 519 | if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) { |
520 | e1000_release_phy_80003es2lan(hw); | ||
497 | return -E1000_ERR_PHY; | 521 | return -E1000_ERR_PHY; |
522 | } | ||
498 | 523 | ||
499 | udelay(200); | 524 | udelay(200); |
500 | 525 | ||
501 | ret_val = e1000e_write_phy_reg_m88(hw, | 526 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
502 | MAX_PHY_REG_ADDRESS & offset, | 527 | data); |
503 | data); | ||
504 | 528 | ||
505 | udelay(200); | 529 | udelay(200); |
530 | e1000_release_phy_80003es2lan(hw); | ||
506 | 531 | ||
507 | return ret_val; | 532 | return ret_val; |
508 | } | 533 | } |
@@ -882,10 +907,10 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) | |||
882 | struct e1000_phy_info *phy = &hw->phy; | 907 | struct e1000_phy_info *phy = &hw->phy; |
883 | s32 ret_val; | 908 | s32 ret_val; |
884 | u32 ctrl_ext; | 909 | u32 ctrl_ext; |
885 | u16 data; | 910 | u32 i = 0; |
911 | u16 data, data2; | ||
886 | 912 | ||
887 | ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, | 913 | ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data); |
888 | &data); | ||
889 | if (ret_val) | 914 | if (ret_val) |
890 | return ret_val; | 915 | return ret_val; |
891 | 916 | ||
@@ -893,8 +918,7 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) | |||
893 | /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ | 918 | /* Use 25MHz for both link down and 1000Base-T for Tx clock. */ |
894 | data |= GG82563_MSCR_TX_CLK_1000MBPS_25; | 919 | data |= GG82563_MSCR_TX_CLK_1000MBPS_25; |
895 | 920 | ||
896 | ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, | 921 | ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data); |
897 | data); | ||
898 | if (ret_val) | 922 | if (ret_val) |
899 | return ret_val; | 923 | return ret_val; |
900 | 924 | ||
@@ -954,6 +978,18 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) | |||
954 | if (ret_val) | 978 | if (ret_val) |
955 | return ret_val; | 979 | return ret_val; |
956 | 980 | ||
981 | ret_val = e1000e_read_kmrn_reg(hw, | ||
982 | E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, | ||
983 | &data); | ||
984 | if (ret_val) | ||
985 | return ret_val; | ||
986 | data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE; | ||
987 | ret_val = e1000e_write_kmrn_reg(hw, | ||
988 | E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, | ||
989 | data); | ||
990 | if (ret_val) | ||
991 | return ret_val; | ||
992 | |||
957 | ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); | 993 | ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data); |
958 | if (ret_val) | 994 | if (ret_val) |
959 | return ret_val; | 995 | return ret_val; |
@@ -983,9 +1019,18 @@ static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw) | |||
983 | if (ret_val) | 1019 | if (ret_val) |
984 | return ret_val; | 1020 | return ret_val; |
985 | 1021 | ||
986 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data); | 1022 | do { |
987 | if (ret_val) | 1023 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, |
988 | return ret_val; | 1024 | &data); |
1025 | if (ret_val) | ||
1026 | return ret_val; | ||
1027 | |||
1028 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, | ||
1029 | &data2); | ||
1030 | if (ret_val) | ||
1031 | return ret_val; | ||
1032 | i++; | ||
1033 | } while ((data != data2) && (i < GG82563_MAX_KMRN_RETRY)); | ||
989 | 1034 | ||
990 | data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | 1035 | data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
991 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data); | 1036 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data); |
@@ -1074,7 +1119,8 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) | |||
1074 | { | 1119 | { |
1075 | s32 ret_val; | 1120 | s32 ret_val; |
1076 | u32 tipg; | 1121 | u32 tipg; |
1077 | u16 reg_data; | 1122 | u32 i = 0; |
1123 | u16 reg_data, reg_data2; | ||
1078 | 1124 | ||
1079 | reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; | 1125 | reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT; |
1080 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, | 1126 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, |
@@ -1088,9 +1134,16 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) | |||
1088 | tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; | 1134 | tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN; |
1089 | ew32(TIPG, tipg); | 1135 | ew32(TIPG, tipg); |
1090 | 1136 | ||
1091 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | 1137 | do { |
1092 | if (ret_val) | 1138 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); |
1093 | return ret_val; | 1139 | if (ret_val) |
1140 | return ret_val; | ||
1141 | |||
1142 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); | ||
1143 | if (ret_val) | ||
1144 | return ret_val; | ||
1145 | i++; | ||
1146 | } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); | ||
1094 | 1147 | ||
1095 | if (duplex == HALF_DUPLEX) | 1148 | if (duplex == HALF_DUPLEX) |
1096 | reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; | 1149 | reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER; |
@@ -1112,8 +1165,9 @@ static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex) | |||
1112 | static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) | 1165 | static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) |
1113 | { | 1166 | { |
1114 | s32 ret_val; | 1167 | s32 ret_val; |
1115 | u16 reg_data; | 1168 | u16 reg_data, reg_data2; |
1116 | u32 tipg; | 1169 | u32 tipg; |
1170 | u32 i = 0; | ||
1117 | 1171 | ||
1118 | reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; | 1172 | reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT; |
1119 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, | 1173 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, |
@@ -1127,9 +1181,16 @@ static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw) | |||
1127 | tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; | 1181 | tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN; |
1128 | ew32(TIPG, tipg); | 1182 | ew32(TIPG, tipg); |
1129 | 1183 | ||
1130 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); | 1184 | do { |
1131 | if (ret_val) | 1185 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data); |
1132 | return ret_val; | 1186 | if (ret_val) |
1187 | return ret_val; | ||
1188 | |||
1189 | ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2); | ||
1190 | if (ret_val) | ||
1191 | return ret_val; | ||
1192 | i++; | ||
1193 | } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY)); | ||
1133 | 1194 | ||
1134 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; | 1195 | reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER; |
1135 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); | 1196 | ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data); |
diff --git a/drivers/net/e1000e/phy.c b/drivers/net/e1000e/phy.c index 3a4574caa75b..e102332a6bee 100644 --- a/drivers/net/e1000e/phy.c +++ b/drivers/net/e1000e/phy.c | |||
@@ -116,7 +116,7 @@ s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) | |||
116 | } | 116 | } |
117 | 117 | ||
118 | /** | 118 | /** |
119 | * e1000_read_phy_reg_mdic - Read MDI control register | 119 | * e1000e_read_phy_reg_mdic - Read MDI control register |
120 | * @hw: pointer to the HW structure | 120 | * @hw: pointer to the HW structure |
121 | * @offset: register offset to be read | 121 | * @offset: register offset to be read |
122 | * @data: pointer to the read data | 122 | * @data: pointer to the read data |
@@ -124,7 +124,7 @@ s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) | |||
124 | * Reads the MDI control register in the PHY at offset and stores the | 124 | * Reads the MDI control register in the PHY at offset and stores the |
125 | * information read to data. | 125 | * information read to data. |
126 | **/ | 126 | **/ |
127 | static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) | 127 | s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) |
128 | { | 128 | { |
129 | struct e1000_phy_info *phy = &hw->phy; | 129 | struct e1000_phy_info *phy = &hw->phy; |
130 | u32 i, mdic = 0; | 130 | u32 i, mdic = 0; |
@@ -150,7 +150,7 @@ static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) | |||
150 | * Increasing the time out as testing showed failures with | 150 | * Increasing the time out as testing showed failures with |
151 | * the lower time out | 151 | * the lower time out |
152 | */ | 152 | */ |
153 | for (i = 0; i < 64; i++) { | 153 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
154 | udelay(50); | 154 | udelay(50); |
155 | mdic = er32(MDIC); | 155 | mdic = er32(MDIC); |
156 | if (mdic & E1000_MDIC_READY) | 156 | if (mdic & E1000_MDIC_READY) |
@@ -170,14 +170,14 @@ static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) | |||
170 | } | 170 | } |
171 | 171 | ||
172 | /** | 172 | /** |
173 | * e1000_write_phy_reg_mdic - Write MDI control register | 173 | * e1000e_write_phy_reg_mdic - Write MDI control register |
174 | * @hw: pointer to the HW structure | 174 | * @hw: pointer to the HW structure |
175 | * @offset: register offset to write to | 175 | * @offset: register offset to write to |
176 | * @data: data to write to register at offset | 176 | * @data: data to write to register at offset |
177 | * | 177 | * |
178 | * Writes data to MDI control register in the PHY at offset. | 178 | * Writes data to MDI control register in the PHY at offset. |
179 | **/ | 179 | **/ |
180 | static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) | 180 | s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) |
181 | { | 181 | { |
182 | struct e1000_phy_info *phy = &hw->phy; | 182 | struct e1000_phy_info *phy = &hw->phy; |
183 | u32 i, mdic = 0; | 183 | u32 i, mdic = 0; |
@@ -199,9 +199,13 @@ static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) | |||
199 | 199 | ||
200 | ew32(MDIC, mdic); | 200 | ew32(MDIC, mdic); |
201 | 201 | ||
202 | /* Poll the ready bit to see if the MDI read completed */ | 202 | /* |
203 | for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { | 203 | * Poll the ready bit to see if the MDI read completed |
204 | udelay(5); | 204 | * Increasing the time out as testing showed failures with |
205 | * the lower time out | ||
206 | */ | ||
207 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { | ||
208 | udelay(50); | ||
205 | mdic = er32(MDIC); | 209 | mdic = er32(MDIC); |
206 | if (mdic & E1000_MDIC_READY) | 210 | if (mdic & E1000_MDIC_READY) |
207 | break; | 211 | break; |
@@ -210,6 +214,10 @@ static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) | |||
210 | hw_dbg(hw, "MDI Write did not complete\n"); | 214 | hw_dbg(hw, "MDI Write did not complete\n"); |
211 | return -E1000_ERR_PHY; | 215 | return -E1000_ERR_PHY; |
212 | } | 216 | } |
217 | if (mdic & E1000_MDIC_ERROR) { | ||
218 | hw_dbg(hw, "MDI Error\n"); | ||
219 | return -E1000_ERR_PHY; | ||
220 | } | ||
213 | 221 | ||
214 | return 0; | 222 | return 0; |
215 | } | 223 | } |
@@ -232,9 +240,8 @@ s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) | |||
232 | if (ret_val) | 240 | if (ret_val) |
233 | return ret_val; | 241 | return ret_val; |
234 | 242 | ||
235 | ret_val = e1000_read_phy_reg_mdic(hw, | 243 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
236 | MAX_PHY_REG_ADDRESS & offset, | 244 | data); |
237 | data); | ||
238 | 245 | ||
239 | hw->phy.ops.release_phy(hw); | 246 | hw->phy.ops.release_phy(hw); |
240 | 247 | ||
@@ -258,9 +265,8 @@ s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) | |||
258 | if (ret_val) | 265 | if (ret_val) |
259 | return ret_val; | 266 | return ret_val; |
260 | 267 | ||
261 | ret_val = e1000_write_phy_reg_mdic(hw, | 268 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
262 | MAX_PHY_REG_ADDRESS & offset, | 269 | data); |
263 | data); | ||
264 | 270 | ||
265 | hw->phy.ops.release_phy(hw); | 271 | hw->phy.ops.release_phy(hw); |
266 | 272 | ||
@@ -286,18 +292,17 @@ s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) | |||
286 | return ret_val; | 292 | return ret_val; |
287 | 293 | ||
288 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | 294 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
289 | ret_val = e1000_write_phy_reg_mdic(hw, | 295 | ret_val = e1000e_write_phy_reg_mdic(hw, |
290 | IGP01E1000_PHY_PAGE_SELECT, | 296 | IGP01E1000_PHY_PAGE_SELECT, |
291 | (u16)offset); | 297 | (u16)offset); |
292 | if (ret_val) { | 298 | if (ret_val) { |
293 | hw->phy.ops.release_phy(hw); | 299 | hw->phy.ops.release_phy(hw); |
294 | return ret_val; | 300 | return ret_val; |
295 | } | 301 | } |
296 | } | 302 | } |
297 | 303 | ||
298 | ret_val = e1000_read_phy_reg_mdic(hw, | 304 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
299 | MAX_PHY_REG_ADDRESS & offset, | 305 | data); |
300 | data); | ||
301 | 306 | ||
302 | hw->phy.ops.release_phy(hw); | 307 | hw->phy.ops.release_phy(hw); |
303 | 308 | ||
@@ -322,18 +327,17 @@ s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) | |||
322 | return ret_val; | 327 | return ret_val; |
323 | 328 | ||
324 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | 329 | if (offset > MAX_PHY_MULTI_PAGE_REG) { |
325 | ret_val = e1000_write_phy_reg_mdic(hw, | 330 | ret_val = e1000e_write_phy_reg_mdic(hw, |
326 | IGP01E1000_PHY_PAGE_SELECT, | 331 | IGP01E1000_PHY_PAGE_SELECT, |
327 | (u16)offset); | 332 | (u16)offset); |
328 | if (ret_val) { | 333 | if (ret_val) { |
329 | hw->phy.ops.release_phy(hw); | 334 | hw->phy.ops.release_phy(hw); |
330 | return ret_val; | 335 | return ret_val; |
331 | } | 336 | } |
332 | } | 337 | } |
333 | 338 | ||
334 | ret_val = e1000_write_phy_reg_mdic(hw, | 339 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
335 | MAX_PHY_REG_ADDRESS & offset, | 340 | data); |
336 | data); | ||
337 | 341 | ||
338 | hw->phy.ops.release_phy(hw); | 342 | hw->phy.ops.release_phy(hw); |
339 | 343 | ||
@@ -420,7 +424,9 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) | |||
420 | if (ret_val) | 424 | if (ret_val) |
421 | return ret_val; | 425 | return ret_val; |
422 | 426 | ||
423 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | 427 | /* For newer PHYs this bit is downshift enable */ |
428 | if (phy->type == e1000_phy_m88) | ||
429 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | ||
424 | 430 | ||
425 | /* | 431 | /* |
426 | * Options: | 432 | * Options: |
@@ -463,7 +469,7 @@ s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) | |||
463 | if (ret_val) | 469 | if (ret_val) |
464 | return ret_val; | 470 | return ret_val; |
465 | 471 | ||
466 | if (phy->revision < 4) { | 472 | if ((phy->type == e1000_phy_m88) && (phy->revision < 4)) { |
467 | /* | 473 | /* |
468 | * Force TX_CLK in the Extended PHY Specific Control Register | 474 | * Force TX_CLK in the Extended PHY Specific Control Register |
469 | * to 25MHz clock. | 475 | * to 25MHz clock. |
@@ -518,8 +524,11 @@ s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) | |||
518 | return ret_val; | 524 | return ret_val; |
519 | } | 525 | } |
520 | 526 | ||
521 | /* Wait 15ms for MAC to configure PHY from NVM settings. */ | 527 | /* |
522 | msleep(15); | 528 | * Wait 100ms for MAC to configure PHY from NVM settings, to avoid |
529 | * timeout issues when LFS is enabled. | ||
530 | */ | ||
531 | msleep(100); | ||
523 | 532 | ||
524 | /* disable lplu d0 during driver init */ | 533 | /* disable lplu d0 during driver init */ |
525 | ret_val = e1000_set_d0_lplu_state(hw, 0); | 534 | ret_val = e1000_set_d0_lplu_state(hw, 0); |
@@ -1152,9 +1161,7 @@ s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) | |||
1152 | 1161 | ||
1153 | if (!active) { | 1162 | if (!active) { |
1154 | data &= ~IGP02E1000_PM_D3_LPLU; | 1163 | data &= ~IGP02E1000_PM_D3_LPLU; |
1155 | ret_val = e1e_wphy(hw, | 1164 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
1156 | IGP02E1000_PHY_POWER_MGMT, | ||
1157 | data); | ||
1158 | if (ret_val) | 1165 | if (ret_val) |
1159 | return ret_val; | 1166 | return ret_val; |
1160 | /* | 1167 | /* |