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-rw-r--r--arch/arm/mm/proc-xsc3.S3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 80873b36c3f7..8d32e21fe151 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -427,12 +427,13 @@ __xsc3_setup:
427#endif 427#endif
428 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg 428 mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
429 mrc p15, 0, r0, c1, c0, 0 @ get control register 429 mrc p15, 0, r0, c1, c0, 0 @ get control register
430 bic r0, r0, #0x0200 @ .... ..R. .... ....
431 bic r0, r0, #0x0002 @ .... .... .... ..A. 430 bic r0, r0, #0x0002 @ .... .... .... ..A.
432 orr r0, r0, #0x0005 @ .... .... .... .C.M 431 orr r0, r0, #0x0005 @ .... .... .... .C.M
433#if BTB_ENABLE 432#if BTB_ENABLE
433 bic r0, r0, #0x0200 @ .... ..R. .... ....
434 orr r0, r0, #0x3900 @ ..VI Z..S .... .... 434 orr r0, r0, #0x3900 @ ..VI Z..S .... ....
435#else 435#else
436 bic r0, r0, #0x0a00 @ .... Z.R. .... ....
436 orr r0, r0, #0x3100 @ ..VI ...S .... .... 437 orr r0, r0, #0x3100 @ ..VI ...S .... ....
437#endif 438#endif
438#if L2_CACHE_ENABLE 439#if L2_CACHE_ENABLE