diff options
-rw-r--r-- | arch/x86_64/kernel/setup.c | 6 | ||||
-rw-r--r-- | include/asm-x86_64/cpufeature.h | 2 |
2 files changed, 1 insertions, 7 deletions
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c index 173bdc55113b..a5ebd03ecbd1 100644 --- a/arch/x86_64/kernel/setup.c +++ b/arch/x86_64/kernel/setup.c | |||
@@ -879,7 +879,6 @@ static void __init amd_detect_cmp(struct cpuinfo_x86 *c) | |||
879 | static int __init init_amd(struct cpuinfo_x86 *c) | 879 | static int __init init_amd(struct cpuinfo_x86 *c) |
880 | { | 880 | { |
881 | int r; | 881 | int r; |
882 | int level; | ||
883 | 882 | ||
884 | #ifdef CONFIG_SMP | 883 | #ifdef CONFIG_SMP |
885 | unsigned long value; | 884 | unsigned long value; |
@@ -902,11 +901,6 @@ static int __init init_amd(struct cpuinfo_x86 *c) | |||
902 | 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ | 901 | 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ |
903 | clear_bit(0*32+31, &c->x86_capability); | 902 | clear_bit(0*32+31, &c->x86_capability); |
904 | 903 | ||
905 | /* C-stepping K8? */ | ||
906 | level = cpuid_eax(1); | ||
907 | if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) | ||
908 | set_bit(X86_FEATURE_K8_C, &c->x86_capability); | ||
909 | |||
910 | r = get_model_name(c); | 904 | r = get_model_name(c); |
911 | if (!r) { | 905 | if (!r) { |
912 | switch (c->x86) { | 906 | switch (c->x86) { |
diff --git a/include/asm-x86_64/cpufeature.h b/include/asm-x86_64/cpufeature.h index 72b39f514798..41c0ac8559be 100644 --- a/include/asm-x86_64/cpufeature.h +++ b/include/asm-x86_64/cpufeature.h | |||
@@ -61,7 +61,7 @@ | |||
61 | #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */ | 61 | #define X86_FEATURE_K6_MTRR (3*32+ 1) /* AMD K6 nonstandard MTRRs */ |
62 | #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ | 62 | #define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */ |
63 | #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ | 63 | #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */ |
64 | #define X86_FEATURE_K8_C (3*32+ 4) /* C stepping K8 */ | 64 | /* 4 free */ |
65 | #define X86_FEATURE_CONSTANT_TSC (3*32+5) /* TSC runs at constant rate */ | 65 | #define X86_FEATURE_CONSTANT_TSC (3*32+5) /* TSC runs at constant rate */ |
66 | #define X86_FEATURE_SYNC_RDTSC (3*32+6) /* RDTSC syncs CPU core */ | 66 | #define X86_FEATURE_SYNC_RDTSC (3*32+6) /* RDTSC syncs CPU core */ |
67 | 67 | ||