diff options
| -rw-r--r-- | arch/powerpc/kernel/misc_32.S | 12 | ||||
| -rw-r--r-- | arch/ppc/kernel/misc.S | 12 |
2 files changed, 22 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index e708ab7ca9e8..8533de50347d 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S | |||
| @@ -301,9 +301,19 @@ _GLOBAL(_tlbie) | |||
| 301 | mfspr r4,SPRN_MMUCR | 301 | mfspr r4,SPRN_MMUCR |
| 302 | mfspr r5,SPRN_PID /* Get PID */ | 302 | mfspr r5,SPRN_PID /* Get PID */ |
| 303 | rlwimi r4,r5,0,24,31 /* Set TID */ | 303 | rlwimi r4,r5,0,24,31 /* Set TID */ |
| 304 | mtspr SPRN_MMUCR,r4 | ||
| 305 | 304 | ||
| 305 | /* We have to run the search with interrupts disabled, even critical | ||
| 306 | * and debug interrupts (in fact the only critical exceptions we have | ||
| 307 | * are debug and machine check). Otherwise an interrupt which causes | ||
| 308 | * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */ | ||
| 309 | mfmsr r5 | ||
| 310 | lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha | ||
| 311 | addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l | ||
| 312 | andc r6,r5,r6 | ||
| 313 | mtmsr r6 | ||
| 314 | mtspr SPRN_MMUCR,r4 | ||
| 306 | tlbsx. r3, 0, r3 | 315 | tlbsx. r3, 0, r3 |
| 316 | mtmsr r5 | ||
| 307 | bne 10f | 317 | bne 10f |
| 308 | sync | 318 | sync |
| 309 | /* There are only 64 TLB entries, so r3 < 64, | 319 | /* There are only 64 TLB entries, so r3 < 64, |
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S index 0da55368655c..a22e1f4d94c8 100644 --- a/arch/ppc/kernel/misc.S +++ b/arch/ppc/kernel/misc.S | |||
| @@ -237,9 +237,19 @@ _GLOBAL(_tlbie) | |||
| 237 | mfspr r4,SPRN_MMUCR | 237 | mfspr r4,SPRN_MMUCR |
| 238 | mfspr r5,SPRN_PID /* Get PID */ | 238 | mfspr r5,SPRN_PID /* Get PID */ |
| 239 | rlwimi r4,r5,0,24,31 /* Set TID */ | 239 | rlwimi r4,r5,0,24,31 /* Set TID */ |
| 240 | mtspr SPRN_MMUCR,r4 | ||
| 241 | 240 | ||
| 241 | /* We have to run the search with interrupts disabled, even critical | ||
| 242 | * and debug interrupts (in fact the only critical exceptions we have | ||
| 243 | * are debug and machine check). Otherwise an interrupt which causes | ||
| 244 | * a TLB miss can clobber the MMUCR between the mtspr and the tlbsx. */ | ||
| 245 | mfmsr r5 | ||
| 246 | lis r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@ha | ||
| 247 | addi r6,r6,(MSR_EE|MSR_CE|MSR_ME|MSR_DE)@l | ||
| 248 | andc r6,r5,r6 | ||
| 249 | mtmsr r6 | ||
| 250 | mtspr SPRN_MMUCR,r4 | ||
| 242 | tlbsx. r3, 0, r3 | 251 | tlbsx. r3, 0, r3 |
| 252 | mtmsr r5 | ||
| 243 | bne 10f | 253 | bne 10f |
| 244 | sync | 254 | sync |
| 245 | /* There are only 64 TLB entries, so r3 < 64, | 255 | /* There are only 64 TLB entries, so r3 < 64, |