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-rw-r--r--drivers/parisc/lba_pci.c65
-rw-r--r--drivers/parisc/sba_iommu.c97
-rw-r--r--include/asm-parisc/ropes.h162
3 files changed, 162 insertions, 162 deletions
diff --git a/drivers/parisc/lba_pci.c b/drivers/parisc/lba_pci.c
index 98f03686a710..ba6769934c77 100644
--- a/drivers/parisc/lba_pci.c
+++ b/drivers/parisc/lba_pci.c
@@ -100,71 +100,6 @@
100 100
101#define MODULE_NAME "LBA" 101#define MODULE_NAME "LBA"
102 102
103#define LBA_FUNC_ID 0x0000 /* function id */
104#define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */
105#define LBA_CAPABLE 0x0030 /* capabilities register */
106
107#define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
108#define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */
109
110#define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */
111#define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */
112#define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */
113
114#define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */
115#define LBA_ARB_PRI 0x0088 /* firmware sets this. */
116#define LBA_ARB_MODE 0x0090 /* firmware sets this. */
117#define LBA_ARB_MTLT 0x0098 /* firmware sets this. */
118
119#define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */
120
121#define LBA_STAT_CTL 0x0108 /* Status & Control */
122#define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */
123#define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */
124#define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */
125#define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
126
127#define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */
128#define LBA_LMMIO_MASK 0x0208
129
130#define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */
131#define LBA_GMMIO_MASK 0x0218
132
133#define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */
134#define LBA_WLMMIO_MASK 0x0228
135
136#define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */
137#define LBA_WGMMIO_MASK 0x0238
138
139#define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */
140#define LBA_IOS_MASK 0x0248
141
142#define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */
143#define LBA_ELMMIO_MASK 0x0258
144
145#define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */
146#define LBA_EIOS_MASK 0x0268
147
148#define LBA_GLOBAL_MASK 0x0270 /* Mercury only: Global Address Mask */
149#define LBA_DMA_CTL 0x0278 /* firmware sets this */
150
151#define LBA_IBASE 0x0300 /* SBA DMA support */
152#define LBA_IMASK 0x0308
153
154/* FIXME: ignore DMA Hint stuff until we can measure performance */
155#define LBA_HINT_CFG 0x0310
156#define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */
157
158#define LBA_BUS_MODE 0x0620
159
160/* ERROR regs are needed for config cycle kluges */
161#define LBA_ERROR_CONFIG 0x0680
162#define LBA_SMART_MODE 0x20
163#define LBA_ERROR_STATUS 0x0688
164#define LBA_ROPE_CTL 0x06A0
165
166#define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */
167
168/* non-postable I/O port space, densely packed */ 103/* non-postable I/O port space, densely packed */
169#define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL) 104#define LBA_PORT_BASE (PCI_F_EXTEND | 0xfee00000UL)
170static void __iomem *astro_iop_base __read_mostly; 105static void __iomem *astro_iop_base __read_mostly;
diff --git a/drivers/parisc/sba_iommu.c b/drivers/parisc/sba_iommu.c
index 12776b7e3a84..eed99bdcfb6b 100644
--- a/drivers/parisc/sba_iommu.c
+++ b/drivers/parisc/sba_iommu.c
@@ -89,101 +89,6 @@
89 89
90#define DEFAULT_DMA_HINT_REG 0 90#define DEFAULT_DMA_HINT_REG 0
91 91
92#define SBA_FUNC_ID 0x0000 /* function id */
93#define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
94
95#define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
96
97#define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
98#define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
99/* Ike's IOC's occupy functions 2 and 3 */
100#define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
101
102#define IOC_CTRL 0x8 /* IOC_CTRL offset */
103#define IOC_CTRL_TC (1 << 0) /* TOC Enable */
104#define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */
105#define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
106#define IOC_CTRL_RM (1 << 8) /* Real Mode */
107#define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
108#define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
109#define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
110
111
112/*
113** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
114** Firmware programs this stuff. Don't touch it.
115*/
116#define LMMIO_DIRECT0_BASE 0x300
117#define LMMIO_DIRECT0_MASK 0x308
118#define LMMIO_DIRECT0_ROUTE 0x310
119
120#define LMMIO_DIST_BASE 0x360
121#define LMMIO_DIST_MASK 0x368
122#define LMMIO_DIST_ROUTE 0x370
123
124#define IOS_DIST_BASE 0x390
125#define IOS_DIST_MASK 0x398
126#define IOS_DIST_ROUTE 0x3A0
127
128#define IOS_DIRECT_BASE 0x3C0
129#define IOS_DIRECT_MASK 0x3C8
130#define IOS_DIRECT_ROUTE 0x3D0
131
132/*
133** Offsets into I/O TLB (Function 2 and 3 on Ike)
134*/
135#define ROPE0_CTL 0x200 /* "regbus pci0" */
136#define ROPE1_CTL 0x208
137#define ROPE2_CTL 0x210
138#define ROPE3_CTL 0x218
139#define ROPE4_CTL 0x220
140#define ROPE5_CTL 0x228
141#define ROPE6_CTL 0x230
142#define ROPE7_CTL 0x238
143
144#define IOC_ROPE0_CFG 0x500 /* pluto only */
145#define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */
146
147
148
149#define HF_ENABLE 0x40
150
151
152#define IOC_IBASE 0x300 /* IO TLB */
153#define IOC_IMASK 0x308
154#define IOC_PCOM 0x310
155#define IOC_TCNFG 0x318
156#define IOC_PDIR_BASE 0x320
157
158
159/*
160** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
161** It's safer (avoid memory corruption) to keep DMA page mappings
162** equivalently sized to VM PAGE_SIZE.
163**
164** We really can't avoid generating a new mapping for each
165** page since the Virtual Coherence Index has to be generated
166** and updated for each page.
167**
168** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse.
169*/
170#define IOVP_SIZE PAGE_SIZE
171#define IOVP_SHIFT PAGE_SHIFT
172#define IOVP_MASK PAGE_MASK
173
174#define SBA_PERF_CFG 0x708 /* Performance Counter stuff */
175#define SBA_PERF_MASK1 0x718
176#define SBA_PERF_MASK2 0x730
177
178
179/*
180** Offsets into PCI Performance Counters (functions 12 and 13)
181** Controlled by PERF registers in function 2 & 3 respectively.
182*/
183#define SBA_PERF_CNT1 0x200
184#define SBA_PERF_CNT2 0x208
185#define SBA_PERF_CNT3 0x210
186
187static struct sba_device *sba_list; 92static struct sba_device *sba_list;
188 93
189static unsigned long ioc_needs_fdc = 0; 94static unsigned long ioc_needs_fdc = 0;
@@ -638,7 +543,7 @@ sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
638 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba)); 543 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
639 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */ 544 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */
640 545
641 pa |= 0x8000000000000000ULL; /* set "valid" bit */ 546 pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */
642 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */ 547 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
643 548
644 /* 549 /*
diff --git a/include/asm-parisc/ropes.h b/include/asm-parisc/ropes.h
index 413dfcca15c7..2e3de0ae04d1 100644
--- a/include/asm-parisc/ropes.h
+++ b/include/asm-parisc/ropes.h
@@ -101,7 +101,102 @@ static inline int IS_PLUTO(struct parisc_device *d) {
101 return d->id.hversion == PLUTO_MCKINLEY_PORT; 101 return d->id.hversion == PLUTO_MCKINLEY_PORT;
102} 102}
103 103
104#define SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL 104#define PLUTO_IOVA_BASE (1UL*1024*1024*1024) /* 1GB */
105#define PLUTO_IOVA_SIZE (1UL*1024*1024*1024) /* 1GB */
106#define PLUTO_GART_SIZE (PLUTO_IOVA_SIZE / 2)
107
108#define SBA_PDIR_VALID_BIT 0x8000000000000000ULL
109
110#define SBA_AGPGART_COOKIE 0x0000badbadc0ffeeULL
111
112#define SBA_FUNC_ID 0x0000 /* function id */
113#define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
114
115#define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
116
117#define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
118#define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
119/* Ike's IOC's occupy functions 2 and 3 */
120#define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
121
122#define IOC_CTRL 0x8 /* IOC_CTRL offset */
123#define IOC_CTRL_TC (1 << 0) /* TOC Enable */
124#define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */
125#define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
126#define IOC_CTRL_RM (1 << 8) /* Real Mode */
127#define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
128#define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
129#define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
130
131/*
132** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
133** Firmware programs this stuff. Don't touch it.
134*/
135#define LMMIO_DIRECT0_BASE 0x300
136#define LMMIO_DIRECT0_MASK 0x308
137#define LMMIO_DIRECT0_ROUTE 0x310
138
139#define LMMIO_DIST_BASE 0x360
140#define LMMIO_DIST_MASK 0x368
141#define LMMIO_DIST_ROUTE 0x370
142
143#define IOS_DIST_BASE 0x390
144#define IOS_DIST_MASK 0x398
145#define IOS_DIST_ROUTE 0x3A0
146
147#define IOS_DIRECT_BASE 0x3C0
148#define IOS_DIRECT_MASK 0x3C8
149#define IOS_DIRECT_ROUTE 0x3D0
150
151/*
152** Offsets into I/O TLB (Function 2 and 3 on Ike)
153*/
154#define ROPE0_CTL 0x200 /* "regbus pci0" */
155#define ROPE1_CTL 0x208
156#define ROPE2_CTL 0x210
157#define ROPE3_CTL 0x218
158#define ROPE4_CTL 0x220
159#define ROPE5_CTL 0x228
160#define ROPE6_CTL 0x230
161#define ROPE7_CTL 0x238
162
163#define IOC_ROPE0_CFG 0x500 /* pluto only */
164#define IOC_ROPE_AO 0x10 /* Allow "Relaxed Ordering" */
165
166#define HF_ENABLE 0x40
167
168#define IOC_IBASE 0x300 /* IO TLB */
169#define IOC_IMASK 0x308
170#define IOC_PCOM 0x310
171#define IOC_TCNFG 0x318
172#define IOC_PDIR_BASE 0x320
173
174/*
175** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
176** It's safer (avoid memory corruption) to keep DMA page mappings
177** equivalently sized to VM PAGE_SIZE.
178**
179** We really can't avoid generating a new mapping for each
180** page since the Virtual Coherence Index has to be generated
181** and updated for each page.
182**
183** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse.
184*/
185#define IOVP_SIZE PAGE_SIZE
186#define IOVP_SHIFT PAGE_SHIFT
187#define IOVP_MASK PAGE_MASK
188
189#define SBA_PERF_CFG 0x708 /* Performance Counter stuff */
190#define SBA_PERF_MASK1 0x718
191#define SBA_PERF_MASK2 0x730
192
193/*
194** Offsets into PCI Performance Counters (functions 12 and 13)
195** Controlled by PERF registers in function 2 & 3 respectively.
196*/
197#define SBA_PERF_CNT1 0x200
198#define SBA_PERF_CNT2 0x208
199#define SBA_PERF_CNT3 0x210
105 200
106/* 201/*
107** lba_device: Per instance Elroy data structure 202** lba_device: Per instance Elroy data structure
@@ -147,4 +242,69 @@ static inline int IS_QUICKSILVER(struct parisc_device *d) {
147extern void *iosapic_register(unsigned long hpa); 242extern void *iosapic_register(unsigned long hpa);
148extern int iosapic_fixup_irq(void *obj, struct pci_dev *pcidev); 243extern int iosapic_fixup_irq(void *obj, struct pci_dev *pcidev);
149 244
245#define LBA_FUNC_ID 0x0000 /* function id */
246#define LBA_FCLASS 0x0008 /* function class, bist, header, rev... */
247#define LBA_CAPABLE 0x0030 /* capabilities register */
248
249#define LBA_PCI_CFG_ADDR 0x0040 /* poke CFG address here */
250#define LBA_PCI_CFG_DATA 0x0048 /* read or write data here */
251
252#define LBA_PMC_MTLT 0x0050 /* Firmware sets this - read only. */
253#define LBA_FW_SCRATCH 0x0058 /* Firmware writes the PCI bus number here. */
254#define LBA_ERROR_ADDR 0x0070 /* On error, address gets logged here */
255
256#define LBA_ARB_MASK 0x0080 /* bit 0 enable arbitration. PAT/PDC enables */
257#define LBA_ARB_PRI 0x0088 /* firmware sets this. */
258#define LBA_ARB_MODE 0x0090 /* firmware sets this. */
259#define LBA_ARB_MTLT 0x0098 /* firmware sets this. */
260
261#define LBA_MOD_ID 0x0100 /* Module ID. PDC_PAT_CELL reports 4 */
262
263#define LBA_STAT_CTL 0x0108 /* Status & Control */
264#define LBA_BUS_RESET 0x01 /* Deassert PCI Bus Reset Signal */
265#define CLEAR_ERRLOG 0x10 /* "Clear Error Log" cmd */
266#define CLEAR_ERRLOG_ENABLE 0x20 /* "Clear Error Log" Enable */
267#define HF_ENABLE 0x40 /* enable HF mode (default is -1 mode) */
268
269#define LBA_LMMIO_BASE 0x0200 /* < 4GB I/O address range */
270#define LBA_LMMIO_MASK 0x0208
271
272#define LBA_GMMIO_BASE 0x0210 /* > 4GB I/O address range */
273#define LBA_GMMIO_MASK 0x0218
274
275#define LBA_WLMMIO_BASE 0x0220 /* All < 4GB ranges under the same *SBA* */
276#define LBA_WLMMIO_MASK 0x0228
277
278#define LBA_WGMMIO_BASE 0x0230 /* All > 4GB ranges under the same *SBA* */
279#define LBA_WGMMIO_MASK 0x0238
280
281#define LBA_IOS_BASE 0x0240 /* I/O port space for this LBA */
282#define LBA_IOS_MASK 0x0248
283
284#define LBA_ELMMIO_BASE 0x0250 /* Extra LMMIO range */
285#define LBA_ELMMIO_MASK 0x0258
286
287#define LBA_EIOS_BASE 0x0260 /* Extra I/O port space */
288#define LBA_EIOS_MASK 0x0268
289
290#define LBA_GLOBAL_MASK 0x0270 /* Mercury only: Global Address Mask */
291#define LBA_DMA_CTL 0x0278 /* firmware sets this */
292
293#define LBA_IBASE 0x0300 /* SBA DMA support */
294#define LBA_IMASK 0x0308
295
296/* FIXME: ignore DMA Hint stuff until we can measure performance */
297#define LBA_HINT_CFG 0x0310
298#define LBA_HINT_BASE 0x0380 /* 14 registers at every 8 bytes. */
299
300#define LBA_BUS_MODE 0x0620
301
302/* ERROR regs are needed for config cycle kluges */
303#define LBA_ERROR_CONFIG 0x0680
304#define LBA_SMART_MODE 0x20
305#define LBA_ERROR_STATUS 0x0688
306#define LBA_ROPE_CTL 0x06A0
307
308#define LBA_IOSAPIC_BASE 0x800 /* Offset of IRQ logic */
309
150#endif /*_ASM_PARISC_ROPES_H_*/ 310#endif /*_ASM_PARISC_ROPES_H_*/
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 17:01:07 -0500