diff options
-rw-r--r-- | sound/pci/pcxhr/pcxhr_core.c | 291 | ||||
-rw-r--r-- | sound/pci/pcxhr/pcxhr_core.h | 5 |
2 files changed, 190 insertions, 106 deletions
diff --git a/sound/pci/pcxhr/pcxhr_core.c b/sound/pci/pcxhr/pcxhr_core.c index 7143259cfe34..d5f18226261d 100644 --- a/sound/pci/pcxhr/pcxhr_core.c +++ b/sound/pci/pcxhr/pcxhr_core.c | |||
@@ -132,13 +132,15 @@ static int pcxhr_check_reg_bit(struct pcxhr_mgr *mgr, unsigned int reg, | |||
132 | *read = PCXHR_INPB(mgr, reg); | 132 | *read = PCXHR_INPB(mgr, reg); |
133 | if ((*read & mask) == bit) { | 133 | if ((*read & mask) == bit) { |
134 | if (i > 100) | 134 | if (i > 100) |
135 | snd_printdd("ATTENTION! check_reg(%x) loopcount=%d\n", | 135 | snd_printdd("ATTENTION! check_reg(%x) " |
136 | "loopcount=%d\n", | ||
136 | reg, i); | 137 | reg, i); |
137 | return 0; | 138 | return 0; |
138 | } | 139 | } |
139 | i++; | 140 | i++; |
140 | } while (time_after_eq(end_time, jiffies)); | 141 | } while (time_after_eq(end_time, jiffies)); |
141 | snd_printk(KERN_ERR "pcxhr_check_reg_bit: timeout, reg=%x, mask=0x%x, val=0x%x\n", | 142 | snd_printk(KERN_ERR |
143 | "pcxhr_check_reg_bit: timeout, reg=%x, mask=0x%x, val=%x\n", | ||
142 | reg, mask, *read); | 144 | reg, mask, *read); |
143 | return -EIO; | 145 | return -EIO; |
144 | } | 146 | } |
@@ -159,18 +161,22 @@ static int pcxhr_check_reg_bit(struct pcxhr_mgr *mgr, unsigned int reg, | |||
159 | #define PCXHR_IT_TEST_XILINX (0x0000003C | PCXHR_MASK_IT_HF1 | \ | 161 | #define PCXHR_IT_TEST_XILINX (0x0000003C | PCXHR_MASK_IT_HF1 | \ |
160 | PCXHR_MASK_IT_MANAGE_HF5) | 162 | PCXHR_MASK_IT_MANAGE_HF5) |
161 | #define PCXHR_IT_DOWNLOAD_BOOT (0x0000000C | PCXHR_MASK_IT_HF1 | \ | 163 | #define PCXHR_IT_DOWNLOAD_BOOT (0x0000000C | PCXHR_MASK_IT_HF1 | \ |
162 | PCXHR_MASK_IT_MANAGE_HF5 | PCXHR_MASK_IT_WAIT) | 164 | PCXHR_MASK_IT_MANAGE_HF5 | \ |
165 | PCXHR_MASK_IT_WAIT) | ||
163 | #define PCXHR_IT_RESET_BOARD_FUNC (0x0000000C | PCXHR_MASK_IT_HF0 | \ | 166 | #define PCXHR_IT_RESET_BOARD_FUNC (0x0000000C | PCXHR_MASK_IT_HF0 | \ |
164 | PCXHR_MASK_IT_MANAGE_HF5 | PCXHR_MASK_IT_WAIT_EXTRA) | 167 | PCXHR_MASK_IT_MANAGE_HF5 | \ |
168 | PCXHR_MASK_IT_WAIT_EXTRA) | ||
165 | #define PCXHR_IT_DOWNLOAD_DSP (0x0000000C | \ | 169 | #define PCXHR_IT_DOWNLOAD_DSP (0x0000000C | \ |
166 | PCXHR_MASK_IT_MANAGE_HF5 | PCXHR_MASK_IT_WAIT) | 170 | PCXHR_MASK_IT_MANAGE_HF5 | \ |
171 | PCXHR_MASK_IT_WAIT) | ||
167 | #define PCXHR_IT_DEBUG (0x0000005A | PCXHR_MASK_IT_NO_HF0_HF1) | 172 | #define PCXHR_IT_DEBUG (0x0000005A | PCXHR_MASK_IT_NO_HF0_HF1) |
168 | #define PCXHR_IT_RESET_SEMAPHORE (0x0000005C | PCXHR_MASK_IT_NO_HF0_HF1) | 173 | #define PCXHR_IT_RESET_SEMAPHORE (0x0000005C | PCXHR_MASK_IT_NO_HF0_HF1) |
169 | #define PCXHR_IT_MESSAGE (0x00000074 | PCXHR_MASK_IT_NO_HF0_HF1) | 174 | #define PCXHR_IT_MESSAGE (0x00000074 | PCXHR_MASK_IT_NO_HF0_HF1) |
170 | #define PCXHR_IT_RESET_CHK (0x00000076 | PCXHR_MASK_IT_NO_HF0_HF1) | 175 | #define PCXHR_IT_RESET_CHK (0x00000076 | PCXHR_MASK_IT_NO_HF0_HF1) |
171 | #define PCXHR_IT_UPDATE_RBUFFER (0x00000078 | PCXHR_MASK_IT_NO_HF0_HF1) | 176 | #define PCXHR_IT_UPDATE_RBUFFER (0x00000078 | PCXHR_MASK_IT_NO_HF0_HF1) |
172 | 177 | ||
173 | static int pcxhr_send_it_dsp(struct pcxhr_mgr *mgr, unsigned int itdsp, int atomic) | 178 | static int pcxhr_send_it_dsp(struct pcxhr_mgr *mgr, |
179 | unsigned int itdsp, int atomic) | ||
174 | { | 180 | { |
175 | int err; | 181 | int err; |
176 | unsigned char reg; | 182 | unsigned char reg; |
@@ -178,17 +184,21 @@ static int pcxhr_send_it_dsp(struct pcxhr_mgr *mgr, unsigned int itdsp, int atom | |||
178 | if (itdsp & PCXHR_MASK_IT_MANAGE_HF5) { | 184 | if (itdsp & PCXHR_MASK_IT_MANAGE_HF5) { |
179 | /* clear hf5 bit */ | 185 | /* clear hf5 bit */ |
180 | PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX0, | 186 | PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX0, |
181 | PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) & ~PCXHR_MBOX0_HF5); | 187 | PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) & |
188 | ~PCXHR_MBOX0_HF5); | ||
182 | } | 189 | } |
183 | if ((itdsp & PCXHR_MASK_IT_NO_HF0_HF1) == 0) { | 190 | if ((itdsp & PCXHR_MASK_IT_NO_HF0_HF1) == 0) { |
184 | reg = PCXHR_ICR_HI08_RREQ | PCXHR_ICR_HI08_TREQ | PCXHR_ICR_HI08_HDRQ; | 191 | reg = (PCXHR_ICR_HI08_RREQ | |
192 | PCXHR_ICR_HI08_TREQ | | ||
193 | PCXHR_ICR_HI08_HDRQ); | ||
185 | if (itdsp & PCXHR_MASK_IT_HF0) | 194 | if (itdsp & PCXHR_MASK_IT_HF0) |
186 | reg |= PCXHR_ICR_HI08_HF0; | 195 | reg |= PCXHR_ICR_HI08_HF0; |
187 | if (itdsp & PCXHR_MASK_IT_HF1) | 196 | if (itdsp & PCXHR_MASK_IT_HF1) |
188 | reg |= PCXHR_ICR_HI08_HF1; | 197 | reg |= PCXHR_ICR_HI08_HF1; |
189 | PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg); | 198 | PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg); |
190 | } | 199 | } |
191 | reg = (unsigned char)(((itdsp & PCXHR_MASK_EXTRA_INFO) >> 1) | PCXHR_CVR_HI08_HC); | 200 | reg = (unsigned char)(((itdsp & PCXHR_MASK_EXTRA_INFO) >> 1) | |
201 | PCXHR_CVR_HI08_HC); | ||
192 | PCXHR_OUTPB(mgr, PCXHR_DSP_CVR, reg); | 202 | PCXHR_OUTPB(mgr, PCXHR_DSP_CVR, reg); |
193 | if (itdsp & PCXHR_MASK_IT_WAIT) { | 203 | if (itdsp & PCXHR_MASK_IT_WAIT) { |
194 | if (atomic) | 204 | if (atomic) |
@@ -211,10 +221,14 @@ static int pcxhr_send_it_dsp(struct pcxhr_mgr *mgr, unsigned int itdsp, int atom | |||
211 | } | 221 | } |
212 | if (itdsp & PCXHR_MASK_IT_MANAGE_HF5) { | 222 | if (itdsp & PCXHR_MASK_IT_MANAGE_HF5) { |
213 | /* wait for hf5 bit */ | 223 | /* wait for hf5 bit */ |
214 | err = pcxhr_check_reg_bit(mgr, PCXHR_PLX_MBOX0, PCXHR_MBOX0_HF5, | 224 | err = pcxhr_check_reg_bit(mgr, PCXHR_PLX_MBOX0, |
215 | PCXHR_MBOX0_HF5, PCXHR_TIMEOUT_DSP, ®); | 225 | PCXHR_MBOX0_HF5, |
226 | PCXHR_MBOX0_HF5, | ||
227 | PCXHR_TIMEOUT_DSP, | ||
228 | ®); | ||
216 | if (err) { | 229 | if (err) { |
217 | snd_printk(KERN_ERR "pcxhr_send_it_dsp : TIMEOUT HF5\n"); | 230 | snd_printk(KERN_ERR |
231 | "pcxhr_send_it_dsp : TIMEOUT HF5\n"); | ||
218 | return err; | 232 | return err; |
219 | } | 233 | } |
220 | } | 234 | } |
@@ -263,7 +277,8 @@ void pcxhr_enable_dsp(struct pcxhr_mgr *mgr) | |||
263 | /* | 277 | /* |
264 | * load the xilinx image | 278 | * load the xilinx image |
265 | */ | 279 | */ |
266 | int pcxhr_load_xilinx_binary(struct pcxhr_mgr *mgr, const struct firmware *xilinx, int second) | 280 | int pcxhr_load_xilinx_binary(struct pcxhr_mgr *mgr, |
281 | const struct firmware *xilinx, int second) | ||
267 | { | 282 | { |
268 | unsigned int i; | 283 | unsigned int i; |
269 | unsigned int chipsc; | 284 | unsigned int chipsc; |
@@ -274,7 +289,9 @@ int pcxhr_load_xilinx_binary(struct pcxhr_mgr *mgr, const struct firmware *xilin | |||
274 | /* test first xilinx */ | 289 | /* test first xilinx */ |
275 | chipsc = PCXHR_INPL(mgr, PCXHR_PLX_CHIPSC); | 290 | chipsc = PCXHR_INPL(mgr, PCXHR_PLX_CHIPSC); |
276 | /* REV01 cards do not support the PCXHR_CHIPSC_GPI_USERI bit anymore */ | 291 | /* REV01 cards do not support the PCXHR_CHIPSC_GPI_USERI bit anymore */ |
277 | /* this bit will always be 1; no possibility to test presence of first xilinx */ | 292 | /* this bit will always be 1; |
293 | * no possibility to test presence of first xilinx | ||
294 | */ | ||
278 | if(second) { | 295 | if(second) { |
279 | if ((chipsc & PCXHR_CHIPSC_GPI_USERI) == 0) { | 296 | if ((chipsc & PCXHR_CHIPSC_GPI_USERI) == 0) { |
280 | snd_printk(KERN_ERR "error loading first xilinx\n"); | 297 | snd_printk(KERN_ERR "error loading first xilinx\n"); |
@@ -290,7 +307,8 @@ int pcxhr_load_xilinx_binary(struct pcxhr_mgr *mgr, const struct firmware *xilin | |||
290 | data = *image; | 307 | data = *image; |
291 | mask = 0x80; | 308 | mask = 0x80; |
292 | while (mask) { | 309 | while (mask) { |
293 | chipsc &= ~(PCXHR_CHIPSC_DATA_CLK | PCXHR_CHIPSC_DATA_IN); | 310 | chipsc &= ~(PCXHR_CHIPSC_DATA_CLK | |
311 | PCXHR_CHIPSC_DATA_IN); | ||
294 | if (data & mask) | 312 | if (data & mask) |
295 | chipsc |= PCXHR_CHIPSC_DATA_IN; | 313 | chipsc |= PCXHR_CHIPSC_DATA_IN; |
296 | PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, chipsc); | 314 | PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, chipsc); |
@@ -330,15 +348,20 @@ static int pcxhr_download_dsp(struct pcxhr_mgr *mgr, const struct firmware *dsp) | |||
330 | data = dsp->data + i; | 348 | data = dsp->data + i; |
331 | if (i == 0) { | 349 | if (i == 0) { |
332 | /* test data header consistency */ | 350 | /* test data header consistency */ |
333 | len = (unsigned int)((data[0]<<16) + (data[1]<<8) + data[2]); | 351 | len = (unsigned int)((data[0]<<16) + |
334 | if (len && dsp->size != (len + 2) * 3) | 352 | (data[1]<<8) + |
353 | data[2]); | ||
354 | if (len && (dsp->size != (len + 2) * 3)) | ||
335 | return -EINVAL; | 355 | return -EINVAL; |
336 | } | 356 | } |
337 | /* wait DSP ready for new transfer */ | 357 | /* wait DSP ready for new transfer */ |
338 | err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY, | 358 | err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, |
339 | PCXHR_ISR_HI08_TRDY, PCXHR_TIMEOUT_DSP, &dummy); | 359 | PCXHR_ISR_HI08_TRDY, |
360 | PCXHR_ISR_HI08_TRDY, | ||
361 | PCXHR_TIMEOUT_DSP, &dummy); | ||
340 | if (err) { | 362 | if (err) { |
341 | snd_printk(KERN_ERR "dsp loading error at position %d\n", i); | 363 | snd_printk(KERN_ERR |
364 | "dsp loading error at position %d\n", i); | ||
342 | return err; | 365 | return err; |
343 | } | 366 | } |
344 | /* send host data */ | 367 | /* send host data */ |
@@ -357,7 +380,8 @@ static int pcxhr_download_dsp(struct pcxhr_mgr *mgr, const struct firmware *dsp) | |||
357 | /* | 380 | /* |
358 | * load the eeprom image | 381 | * load the eeprom image |
359 | */ | 382 | */ |
360 | int pcxhr_load_eeprom_binary(struct pcxhr_mgr *mgr, const struct firmware *eeprom) | 383 | int pcxhr_load_eeprom_binary(struct pcxhr_mgr *mgr, |
384 | const struct firmware *eeprom) | ||
361 | { | 385 | { |
362 | int err; | 386 | int err; |
363 | unsigned char reg; | 387 | unsigned char reg; |
@@ -365,7 +389,9 @@ int pcxhr_load_eeprom_binary(struct pcxhr_mgr *mgr, const struct firmware *eepro | |||
365 | /* init value of the ICR register */ | 389 | /* init value of the ICR register */ |
366 | reg = PCXHR_ICR_HI08_RREQ | PCXHR_ICR_HI08_TREQ | PCXHR_ICR_HI08_HDRQ; | 390 | reg = PCXHR_ICR_HI08_RREQ | PCXHR_ICR_HI08_TREQ | PCXHR_ICR_HI08_HDRQ; |
367 | if (PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) & PCXHR_MBOX0_BOOT_HERE) { | 391 | if (PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) & PCXHR_MBOX0_BOOT_HERE) { |
368 | /* no need to load the eeprom binary, but init the HI08 interface */ | 392 | /* no need to load the eeprom binary, |
393 | * but init the HI08 interface | ||
394 | */ | ||
369 | PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg | PCXHR_ICR_HI08_INIT); | 395 | PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg | PCXHR_ICR_HI08_INIT); |
370 | msleep(PCXHR_WAIT_DEFAULT); | 396 | msleep(PCXHR_WAIT_DEFAULT); |
371 | PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg); | 397 | PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg); |
@@ -429,8 +455,10 @@ int pcxhr_load_dsp_binary(struct pcxhr_mgr *mgr, const struct firmware *dsp) | |||
429 | if (err) | 455 | if (err) |
430 | return err; | 456 | return err; |
431 | /* wait for chk bit */ | 457 | /* wait for chk bit */ |
432 | return pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK, | 458 | return pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, |
433 | PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, &dummy); | 459 | PCXHR_ISR_HI08_CHK, |
460 | PCXHR_ISR_HI08_CHK, | ||
461 | PCXHR_TIMEOUT_DSP, &dummy); | ||
434 | } | 462 | } |
435 | 463 | ||
436 | 464 | ||
@@ -443,8 +471,8 @@ struct pcxhr_cmd_info { | |||
443 | /* RMH status type */ | 471 | /* RMH status type */ |
444 | enum { | 472 | enum { |
445 | RMH_SSIZE_FIXED = 0, /* status size fix (st_length = 0..x) */ | 473 | RMH_SSIZE_FIXED = 0, /* status size fix (st_length = 0..x) */ |
446 | RMH_SSIZE_ARG = 1, /* status size given in the LSB byte (used with st_length = 1) */ | 474 | RMH_SSIZE_ARG = 1, /* status size given in the LSB byte */ |
447 | RMH_SSIZE_MASK = 2, /* status size given in bitmask (used with st_length = 1) */ | 475 | RMH_SSIZE_MASK = 2, /* status size given in bitmask */ |
448 | }; | 476 | }; |
449 | 477 | ||
450 | /* | 478 | /* |
@@ -474,7 +502,7 @@ static struct pcxhr_cmd_info pcxhr_dsp_cmds[] = { | |||
474 | [CMD_UPDATE_R_BUFFERS] = { 0x840000, 0, RMH_SSIZE_FIXED }, | 502 | [CMD_UPDATE_R_BUFFERS] = { 0x840000, 0, RMH_SSIZE_FIXED }, |
475 | [CMD_FORMAT_STREAM_OUT] = { 0x860000, 0, RMH_SSIZE_FIXED }, | 503 | [CMD_FORMAT_STREAM_OUT] = { 0x860000, 0, RMH_SSIZE_FIXED }, |
476 | [CMD_FORMAT_STREAM_IN] = { 0x870000, 0, RMH_SSIZE_FIXED }, | 504 | [CMD_FORMAT_STREAM_IN] = { 0x870000, 0, RMH_SSIZE_FIXED }, |
477 | [CMD_STREAM_SAMPLE_COUNT] = { 0x902000, 2, RMH_SSIZE_FIXED }, /* stat_len = nb_streams * 2 */ | 505 | [CMD_STREAM_SAMPLE_COUNT] = { 0x902000, 2, RMH_SSIZE_FIXED }, |
478 | [CMD_AUDIO_LEVEL_ADJUST] = { 0xc22000, 0, RMH_SSIZE_FIXED }, | 506 | [CMD_AUDIO_LEVEL_ADJUST] = { 0xc22000, 0, RMH_SSIZE_FIXED }, |
479 | }; | 507 | }; |
480 | 508 | ||
@@ -524,10 +552,13 @@ static int pcxhr_read_rmh_status(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh) | |||
524 | 552 | ||
525 | for (i = 0; i < rmh->stat_len; i++) { | 553 | for (i = 0; i < rmh->stat_len; i++) { |
526 | /* wait for receiver full */ | 554 | /* wait for receiver full */ |
527 | err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_RXDF, | 555 | err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, |
528 | PCXHR_ISR_HI08_RXDF, PCXHR_TIMEOUT_DSP, ®); | 556 | PCXHR_ISR_HI08_RXDF, |
557 | PCXHR_ISR_HI08_RXDF, | ||
558 | PCXHR_TIMEOUT_DSP, ®); | ||
529 | if (err) { | 559 | if (err) { |
530 | snd_printk(KERN_ERR "ERROR RMH stat: ISR:RXDF=1 (ISR = %x; i=%d )\n", | 560 | snd_printk(KERN_ERR "ERROR RMH stat: " |
561 | "ISR:RXDF=1 (ISR = %x; i=%d )\n", | ||
531 | reg, i); | 562 | reg, i); |
532 | return err; | 563 | return err; |
533 | } | 564 | } |
@@ -537,10 +568,10 @@ static int pcxhr_read_rmh_status(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh) | |||
537 | data |= PCXHR_INPB(mgr, PCXHR_DSP_TXL); | 568 | data |= PCXHR_INPB(mgr, PCXHR_DSP_TXL); |
538 | 569 | ||
539 | /* need to update rmh->stat_len on the fly ?? */ | 570 | /* need to update rmh->stat_len on the fly ?? */ |
540 | if (i==0) { | 571 | if (!i) { |
541 | if (rmh->dsp_stat != RMH_SSIZE_FIXED) { | 572 | if (rmh->dsp_stat != RMH_SSIZE_FIXED) { |
542 | if (rmh->dsp_stat == RMH_SSIZE_ARG) { | 573 | if (rmh->dsp_stat == RMH_SSIZE_ARG) { |
543 | rmh->stat_len = (u16)(data & 0x0000ff) + 1; | 574 | rmh->stat_len = (data & 0x0000ff) + 1; |
544 | data &= 0xffff00; | 575 | data &= 0xffff00; |
545 | } else { | 576 | } else { |
546 | /* rmh->dsp_stat == RMH_SSIZE_MASK */ | 577 | /* rmh->dsp_stat == RMH_SSIZE_MASK */ |
@@ -562,7 +593,8 @@ static int pcxhr_read_rmh_status(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh) | |||
562 | rmh->stat[i] = data; | 593 | rmh->stat[i] = data; |
563 | } | 594 | } |
564 | if (rmh->stat_len > max_stat_len) { | 595 | if (rmh->stat_len > max_stat_len) { |
565 | snd_printdd("PCXHR : rmh->stat_len=%x too big\n", rmh->stat_len); | 596 | snd_printdd("PCXHR : rmh->stat_len=%x too big\n", |
597 | rmh->stat_len); | ||
566 | rmh->stat_len = max_stat_len; | 598 | rmh->stat_len = max_stat_len; |
567 | } | 599 | } |
568 | return 0; | 600 | return 0; |
@@ -605,7 +637,8 @@ static int pcxhr_send_msg_nolock(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh) | |||
605 | data &= 0xff7fff; /* MASK_1_WORD_COMMAND */ | 637 | data &= 0xff7fff; /* MASK_1_WORD_COMMAND */ |
606 | #ifdef CONFIG_SND_DEBUG_VERBOSE | 638 | #ifdef CONFIG_SND_DEBUG_VERBOSE |
607 | if (rmh->cmd_idx < CMD_LAST_INDEX) | 639 | if (rmh->cmd_idx < CMD_LAST_INDEX) |
608 | snd_printdd("MSG cmd[0]=%x (%s)\n", data, cmd_names[rmh->cmd_idx]); | 640 | snd_printdd("MSG cmd[0]=%x (%s)\n", |
641 | data, cmd_names[rmh->cmd_idx]); | ||
609 | #endif | 642 | #endif |
610 | 643 | ||
611 | err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY, | 644 | err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY, |
@@ -619,8 +652,10 @@ static int pcxhr_send_msg_nolock(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh) | |||
619 | if (rmh->cmd_len > 1) { | 652 | if (rmh->cmd_len > 1) { |
620 | /* send length */ | 653 | /* send length */ |
621 | data = rmh->cmd_len - 1; | 654 | data = rmh->cmd_len - 1; |
622 | err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY, | 655 | err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, |
623 | PCXHR_ISR_HI08_TRDY, PCXHR_TIMEOUT_DSP, ®); | 656 | PCXHR_ISR_HI08_TRDY, |
657 | PCXHR_ISR_HI08_TRDY, | ||
658 | PCXHR_TIMEOUT_DSP, ®); | ||
624 | if (err) | 659 | if (err) |
625 | return err; | 660 | return err; |
626 | PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, (data>>16)&0xFF); | 661 | PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, (data>>16)&0xFF); |
@@ -653,8 +688,10 @@ static int pcxhr_send_msg_nolock(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh) | |||
653 | /* test status ISR */ | 688 | /* test status ISR */ |
654 | if (reg & PCXHR_ISR_HI08_ERR) { | 689 | if (reg & PCXHR_ISR_HI08_ERR) { |
655 | /* ERROR, wait for receiver full */ | 690 | /* ERROR, wait for receiver full */ |
656 | err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_RXDF, | 691 | err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, |
657 | PCXHR_ISR_HI08_RXDF, PCXHR_TIMEOUT_DSP, ®); | 692 | PCXHR_ISR_HI08_RXDF, |
693 | PCXHR_ISR_HI08_RXDF, | ||
694 | PCXHR_TIMEOUT_DSP, ®); | ||
658 | if (err) { | 695 | if (err) { |
659 | snd_printk(KERN_ERR "ERROR RMH: ISR:RXDF=1 (ISR = %x)\n", reg); | 696 | snd_printk(KERN_ERR "ERROR RMH: ISR:RXDF=1 (ISR = %x)\n", reg); |
660 | return err; | 697 | return err; |
@@ -663,7 +700,8 @@ static int pcxhr_send_msg_nolock(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh) | |||
663 | data = PCXHR_INPB(mgr, PCXHR_DSP_TXH) << 16; | 700 | data = PCXHR_INPB(mgr, PCXHR_DSP_TXH) << 16; |
664 | data |= PCXHR_INPB(mgr, PCXHR_DSP_TXM) << 8; | 701 | data |= PCXHR_INPB(mgr, PCXHR_DSP_TXM) << 8; |
665 | data |= PCXHR_INPB(mgr, PCXHR_DSP_TXL); | 702 | data |= PCXHR_INPB(mgr, PCXHR_DSP_TXL); |
666 | snd_printk(KERN_ERR "ERROR RMH(%d): 0x%x\n", rmh->cmd_idx, data); | 703 | snd_printk(KERN_ERR "ERROR RMH(%d): 0x%x\n", |
704 | rmh->cmd_idx, data); | ||
667 | err = -EINVAL; | 705 | err = -EINVAL; |
668 | } else { | 706 | } else { |
669 | /* read the response data */ | 707 | /* read the response data */ |
@@ -732,8 +770,9 @@ int pcxhr_send_msg(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh) | |||
732 | static inline int pcxhr_pipes_running(struct pcxhr_mgr *mgr) | 770 | static inline int pcxhr_pipes_running(struct pcxhr_mgr *mgr) |
733 | { | 771 | { |
734 | int start_mask = PCXHR_INPL(mgr, PCXHR_PLX_MBOX2); | 772 | int start_mask = PCXHR_INPL(mgr, PCXHR_PLX_MBOX2); |
735 | /* least segnificant 12 bits are the pipe states for the playback audios */ | 773 | /* least segnificant 12 bits are the pipe states |
736 | /* next 12 bits are the pipe states for the capture audios | 774 | * for the playback audios |
775 | * next 12 bits are the pipe states for the capture audios | ||
737 | * (PCXHR_PIPE_STATE_CAPTURE_OFFSET) | 776 | * (PCXHR_PIPE_STATE_CAPTURE_OFFSET) |
738 | */ | 777 | */ |
739 | start_mask &= 0xffffff; | 778 | start_mask &= 0xffffff; |
@@ -744,7 +783,8 @@ static inline int pcxhr_pipes_running(struct pcxhr_mgr *mgr) | |||
744 | #define PCXHR_PIPE_STATE_CAPTURE_OFFSET 12 | 783 | #define PCXHR_PIPE_STATE_CAPTURE_OFFSET 12 |
745 | #define MAX_WAIT_FOR_DSP 20 | 784 | #define MAX_WAIT_FOR_DSP 20 |
746 | 785 | ||
747 | static int pcxhr_prepair_pipe_start(struct pcxhr_mgr *mgr, int audio_mask, int *retry) | 786 | static int pcxhr_prepair_pipe_start(struct pcxhr_mgr *mgr, |
787 | int audio_mask, int *retry) | ||
748 | { | 788 | { |
749 | struct pcxhr_rmh rmh; | 789 | struct pcxhr_rmh rmh; |
750 | int err; | 790 | int err; |
@@ -760,17 +800,20 @@ static int pcxhr_prepair_pipe_start(struct pcxhr_mgr *mgr, int audio_mask, int * | |||
760 | } else { | 800 | } else { |
761 | /* can start capture pipe */ | 801 | /* can start capture pipe */ |
762 | pcxhr_set_pipe_cmd_params(&rmh, 1, audio - | 802 | pcxhr_set_pipe_cmd_params(&rmh, 1, audio - |
763 | PCXHR_PIPE_STATE_CAPTURE_OFFSET, | 803 | PCXHR_PIPE_STATE_CAPTURE_OFFSET, |
764 | 0, 0); | 804 | 0, 0); |
765 | } | 805 | } |
766 | err = pcxhr_send_msg(mgr, &rmh); | 806 | err = pcxhr_send_msg(mgr, &rmh); |
767 | if (err) { | 807 | if (err) { |
768 | snd_printk(KERN_ERR | 808 | snd_printk(KERN_ERR |
769 | "error pipe start (CMD_CAN_START_PIPE) err=%x!\n", | 809 | "error pipe start " |
810 | "(CMD_CAN_START_PIPE) err=%x!\n", | ||
770 | err); | 811 | err); |
771 | return err; | 812 | return err; |
772 | } | 813 | } |
773 | /* if the pipe couldn't be prepaired for start, retry it later */ | 814 | /* if the pipe couldn't be prepaired for start, |
815 | * retry it later | ||
816 | */ | ||
774 | if (rmh.stat[0] == 0) | 817 | if (rmh.stat[0] == 0) |
775 | *retry |= (1<<audio); | 818 | *retry |= (1<<audio); |
776 | } | 819 | } |
@@ -795,14 +838,14 @@ static int pcxhr_stop_pipes(struct pcxhr_mgr *mgr, int audio_mask) | |||
795 | } else { | 838 | } else { |
796 | /* stop capture pipe */ | 839 | /* stop capture pipe */ |
797 | pcxhr_set_pipe_cmd_params(&rmh, 1, audio - | 840 | pcxhr_set_pipe_cmd_params(&rmh, 1, audio - |
798 | PCXHR_PIPE_STATE_CAPTURE_OFFSET, | 841 | PCXHR_PIPE_STATE_CAPTURE_OFFSET, |
799 | 0, 0); | 842 | 0, 0); |
800 | } | 843 | } |
801 | err = pcxhr_send_msg(mgr, &rmh); | 844 | err = pcxhr_send_msg(mgr, &rmh); |
802 | if (err) { | 845 | if (err) { |
803 | snd_printk(KERN_ERR | 846 | snd_printk(KERN_ERR |
804 | "error pipe stop (CMD_STOP_PIPE) err=%x!\n", | 847 | "error pipe stop " |
805 | err); | 848 | "(CMD_STOP_PIPE) err=%x!\n", err); |
806 | return err; | 849 | return err; |
807 | } | 850 | } |
808 | } | 851 | } |
@@ -822,15 +865,16 @@ static int pcxhr_toggle_pipes(struct pcxhr_mgr *mgr, int audio_mask) | |||
822 | if (audio_mask & 1) { | 865 | if (audio_mask & 1) { |
823 | pcxhr_init_rmh(&rmh, CMD_CONF_PIPE); | 866 | pcxhr_init_rmh(&rmh, CMD_CONF_PIPE); |
824 | if (audio < PCXHR_PIPE_STATE_CAPTURE_OFFSET) | 867 | if (audio < PCXHR_PIPE_STATE_CAPTURE_OFFSET) |
825 | pcxhr_set_pipe_cmd_params(&rmh, 0, 0, 0, 1 << audio); | 868 | pcxhr_set_pipe_cmd_params(&rmh, 0, 0, 0, |
869 | 1 << audio); | ||
826 | else | 870 | else |
827 | pcxhr_set_pipe_cmd_params(&rmh, 1, 0, 0, | 871 | pcxhr_set_pipe_cmd_params(&rmh, 1, 0, 0, |
828 | 1 << (audio - PCXHR_PIPE_STATE_CAPTURE_OFFSET)); | 872 | 1 << (audio - PCXHR_PIPE_STATE_CAPTURE_OFFSET)); |
829 | err = pcxhr_send_msg(mgr, &rmh); | 873 | err = pcxhr_send_msg(mgr, &rmh); |
830 | if (err) { | 874 | if (err) { |
831 | snd_printk(KERN_ERR | 875 | snd_printk(KERN_ERR |
832 | "error pipe start (CMD_CONF_PIPE) err=%x!\n", | 876 | "error pipe start " |
833 | err); | 877 | "(CMD_CONF_PIPE) err=%x!\n", err); |
834 | return err; | 878 | return err; |
835 | } | 879 | } |
836 | } | 880 | } |
@@ -841,7 +885,9 @@ static int pcxhr_toggle_pipes(struct pcxhr_mgr *mgr, int audio_mask) | |||
841 | pcxhr_init_rmh(&rmh, CMD_SEND_IRQA); | 885 | pcxhr_init_rmh(&rmh, CMD_SEND_IRQA); |
842 | err = pcxhr_send_msg(mgr, &rmh); | 886 | err = pcxhr_send_msg(mgr, &rmh); |
843 | if (err) { | 887 | if (err) { |
844 | snd_printk(KERN_ERR "error pipe start (CMD_SEND_IRQA) err=%x!\n", err ); | 888 | snd_printk(KERN_ERR |
889 | "error pipe start (CMD_SEND_IRQA) err=%x!\n", | ||
890 | err); | ||
845 | return err; | 891 | return err; |
846 | } | 892 | } |
847 | return 0; | 893 | return 0; |
@@ -849,7 +895,8 @@ static int pcxhr_toggle_pipes(struct pcxhr_mgr *mgr, int audio_mask) | |||
849 | 895 | ||
850 | 896 | ||
851 | 897 | ||
852 | int pcxhr_set_pipe_state(struct pcxhr_mgr *mgr, int playback_mask, int capture_mask, int start) | 898 | int pcxhr_set_pipe_state(struct pcxhr_mgr *mgr, int playback_mask, |
899 | int capture_mask, int start) | ||
853 | { | 900 | { |
854 | int state, i, err; | 901 | int state, i, err; |
855 | int audio_mask; | 902 | int audio_mask; |
@@ -858,21 +905,23 @@ int pcxhr_set_pipe_state(struct pcxhr_mgr *mgr, int playback_mask, int capture_m | |||
858 | struct timeval my_tv1, my_tv2; | 905 | struct timeval my_tv1, my_tv2; |
859 | do_gettimeofday(&my_tv1); | 906 | do_gettimeofday(&my_tv1); |
860 | #endif | 907 | #endif |
861 | audio_mask = (playback_mask | (capture_mask << PCXHR_PIPE_STATE_CAPTURE_OFFSET)); | 908 | audio_mask = (playback_mask | |
909 | (capture_mask << PCXHR_PIPE_STATE_CAPTURE_OFFSET)); | ||
862 | /* current pipe state (playback + record) */ | 910 | /* current pipe state (playback + record) */ |
863 | state = pcxhr_pipes_running(mgr); | 911 | state = pcxhr_pipes_running(mgr); |
864 | snd_printdd("pcxhr_set_pipe_state %s (mask %x current %x)\n", | 912 | snd_printdd("pcxhr_set_pipe_state %s (mask %x current %x)\n", |
865 | start ? "START" : "STOP", audio_mask, state); | 913 | start ? "START" : "STOP", audio_mask, state); |
866 | if (start) { | 914 | if (start) { |
867 | audio_mask &= ~state; /* start only pipes that are not yet started */ | 915 | /* start only pipes that are not yet started */ |
916 | audio_mask &= ~state; | ||
868 | state = audio_mask; | 917 | state = audio_mask; |
869 | for (i = 0; i < MAX_WAIT_FOR_DSP; i++) { | 918 | for (i = 0; i < MAX_WAIT_FOR_DSP; i++) { |
870 | err = pcxhr_prepair_pipe_start(mgr, state, &state); | 919 | err = pcxhr_prepair_pipe_start(mgr, state, &state); |
871 | if (err) | 920 | if (err) |
872 | return err; | 921 | return err; |
873 | if (state == 0) | 922 | if (state == 0) |
874 | break; /* success, all pipes prepaired for start */ | 923 | break; /* success, all pipes prepaired */ |
875 | mdelay(1); /* otherwise wait 1 millisecond and retry */ | 924 | mdelay(1); /* wait 1 millisecond and retry */ |
876 | } | 925 | } |
877 | } else { | 926 | } else { |
878 | audio_mask &= state; /* stop only pipes that are started */ | 927 | audio_mask &= state; /* stop only pipes that are started */ |
@@ -891,7 +940,7 @@ int pcxhr_set_pipe_state(struct pcxhr_mgr *mgr, int playback_mask, int capture_m | |||
891 | if ((state & audio_mask) == (start ? audio_mask : 0)) | 940 | if ((state & audio_mask) == (start ? audio_mask : 0)) |
892 | break; | 941 | break; |
893 | if (++i >= MAX_WAIT_FOR_DSP * 100) { | 942 | if (++i >= MAX_WAIT_FOR_DSP * 100) { |
894 | snd_printk(KERN_ERR "error pipe start/stop (ED_NO_RESPONSE_AT_IRQA)\n"); | 943 | snd_printk(KERN_ERR "error pipe start/stop\n"); |
895 | return -EBUSY; | 944 | return -EBUSY; |
896 | } | 945 | } |
897 | udelay(10); /* wait 10 microseconds */ | 946 | udelay(10); /* wait 10 microseconds */ |
@@ -918,7 +967,8 @@ int pcxhr_write_io_num_reg_cont(struct pcxhr_mgr *mgr, unsigned int mask, | |||
918 | 967 | ||
919 | spin_lock_irqsave(&mgr->msg_lock, flags); | 968 | spin_lock_irqsave(&mgr->msg_lock, flags); |
920 | if ((mgr->io_num_reg_cont & mask) == value) { | 969 | if ((mgr->io_num_reg_cont & mask) == value) { |
921 | snd_printdd("IO_NUM_REG_CONT mask %x already is set to %x\n", mask, value); | 970 | snd_printdd("IO_NUM_REG_CONT mask %x already is set to %x\n", |
971 | mask, value); | ||
922 | if (changed) | 972 | if (changed) |
923 | *changed = 0; | 973 | *changed = 0; |
924 | spin_unlock_irqrestore(&mgr->msg_lock, flags); | 974 | spin_unlock_irqrestore(&mgr->msg_lock, flags); |
@@ -971,7 +1021,8 @@ static int pcxhr_handle_async_err(struct pcxhr_mgr *mgr, u32 err, | |||
971 | err = ((err >> 12) & 0xfff); | 1021 | err = ((err >> 12) & 0xfff); |
972 | if (!err) | 1022 | if (!err) |
973 | return 0; | 1023 | return 0; |
974 | snd_printdd("CMD_ASYNC : Error %s %s Pipe %d err=%x\n", err_src_name[err_src], | 1024 | snd_printdd("CMD_ASYNC : Error %s %s Pipe %d err=%x\n", |
1025 | err_src_name[err_src], | ||
975 | is_capture ? "Record" : "Play", pipe, err); | 1026 | is_capture ? "Record" : "Play", pipe, err); |
976 | if (err == 0xe01) | 1027 | if (err == 0xe01) |
977 | mgr->async_err_stream_xrun++; | 1028 | mgr->async_err_stream_xrun++; |
@@ -996,6 +1047,13 @@ void pcxhr_msg_tasklet(unsigned long arg) | |||
996 | snd_printdd("TASKLET : PCXHR_IRQ_TIME_CODE event occured\n"); | 1047 | snd_printdd("TASKLET : PCXHR_IRQ_TIME_CODE event occured\n"); |
997 | if (mgr->src_it_dsp & PCXHR_IRQ_NOTIFY) | 1048 | if (mgr->src_it_dsp & PCXHR_IRQ_NOTIFY) |
998 | snd_printdd("TASKLET : PCXHR_IRQ_NOTIFY event occured\n"); | 1049 | snd_printdd("TASKLET : PCXHR_IRQ_NOTIFY event occured\n"); |
1050 | if (mgr->src_it_dsp & (PCXHR_IRQ_FREQ_CHANGE | PCXHR_IRQ_TIME_CODE)) { | ||
1051 | /* clear events FREQ_CHANGE and TIME_CODE */ | ||
1052 | pcxhr_init_rmh(prmh, CMD_TEST_IT); | ||
1053 | err = pcxhr_send_msg(mgr, prmh); | ||
1054 | snd_printdd("CMD_TEST_IT : err=%x, stat=%x\n", | ||
1055 | err, prmh->stat[0]); | ||
1056 | } | ||
999 | if (mgr->src_it_dsp & PCXHR_IRQ_ASYNC) { | 1057 | if (mgr->src_it_dsp & PCXHR_IRQ_ASYNC) { |
1000 | snd_printdd("TASKLET : PCXHR_IRQ_ASYNC event occured\n"); | 1058 | snd_printdd("TASKLET : PCXHR_IRQ_ASYNC event occured\n"); |
1001 | 1059 | ||
@@ -1005,18 +1063,22 @@ void pcxhr_msg_tasklet(unsigned long arg) | |||
1005 | prmh->stat_len = PCXHR_SIZE_MAX_LONG_STATUS; | 1063 | prmh->stat_len = PCXHR_SIZE_MAX_LONG_STATUS; |
1006 | err = pcxhr_send_msg(mgr, prmh); | 1064 | err = pcxhr_send_msg(mgr, prmh); |
1007 | if (err) | 1065 | if (err) |
1008 | snd_printk(KERN_ERR "ERROR pcxhr_msg_tasklet=%x;\n", err); | 1066 | snd_printk(KERN_ERR "ERROR pcxhr_msg_tasklet=%x;\n", |
1067 | err); | ||
1009 | i = 1; | 1068 | i = 1; |
1010 | while (i < prmh->stat_len) { | 1069 | while (i < prmh->stat_len) { |
1011 | int nb_audio = (prmh->stat[i] >> FIELD_SIZE) & MASK_FIRST_FIELD; | 1070 | int nb_audio = ((prmh->stat[i] >> FIELD_SIZE) & |
1012 | int nb_stream = (prmh->stat[i] >> (2*FIELD_SIZE)) & MASK_FIRST_FIELD; | 1071 | MASK_FIRST_FIELD); |
1072 | int nb_stream = ((prmh->stat[i] >> (2*FIELD_SIZE)) & | ||
1073 | MASK_FIRST_FIELD); | ||
1013 | int pipe = prmh->stat[i] & MASK_FIRST_FIELD; | 1074 | int pipe = prmh->stat[i] & MASK_FIRST_FIELD; |
1014 | int is_capture = prmh->stat[i] & 0x400000; | 1075 | int is_capture = prmh->stat[i] & 0x400000; |
1015 | u32 err2; | 1076 | u32 err2; |
1016 | 1077 | ||
1017 | if (prmh->stat[i] & 0x800000) { /* if BIT_END */ | 1078 | if (prmh->stat[i] & 0x800000) { /* if BIT_END */ |
1018 | snd_printdd("TASKLET : End%sPipe %d\n", | 1079 | snd_printdd("TASKLET : End%sPipe %d\n", |
1019 | is_capture ? "Record" : "Play", pipe); | 1080 | is_capture ? "Record" : "Play", |
1081 | pipe); | ||
1020 | } | 1082 | } |
1021 | i++; | 1083 | i++; |
1022 | err2 = prmh->stat[i] ? prmh->stat[i] : prmh->stat[i+1]; | 1084 | err2 = prmh->stat[i] ? prmh->stat[i] : prmh->stat[i+1]; |
@@ -1062,7 +1124,7 @@ static u_int64_t pcxhr_stream_read_position(struct pcxhr_mgr *mgr, | |||
1062 | pcxhr_init_rmh(&rmh, CMD_STREAM_SAMPLE_COUNT); | 1124 | pcxhr_init_rmh(&rmh, CMD_STREAM_SAMPLE_COUNT); |
1063 | pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, | 1125 | pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, |
1064 | stream->pipe->first_audio, 0, stream_mask); | 1126 | stream->pipe->first_audio, 0, stream_mask); |
1065 | /* rmh.stat_len = 2; */ /* 2 resp data for each stream of the pipe */ | 1127 | /* rmh.stat_len = 2; */ /* 2 resp data for each stream of the pipe */ |
1066 | 1128 | ||
1067 | err = pcxhr_send_msg(mgr, &rmh); | 1129 | err = pcxhr_send_msg(mgr, &rmh); |
1068 | if (err) | 1130 | if (err) |
@@ -1072,18 +1134,21 @@ static u_int64_t pcxhr_stream_read_position(struct pcxhr_mgr *mgr, | |||
1072 | hw_sample_count += (u_int64_t)rmh.stat[1]; | 1134 | hw_sample_count += (u_int64_t)rmh.stat[1]; |
1073 | 1135 | ||
1074 | snd_printdd("stream %c%d : abs samples real(%ld) timer(%ld)\n", | 1136 | snd_printdd("stream %c%d : abs samples real(%ld) timer(%ld)\n", |
1075 | stream->pipe->is_capture ? 'C':'P', stream->substream->number, | 1137 | stream->pipe->is_capture ? 'C' : 'P', |
1138 | stream->substream->number, | ||
1076 | (long unsigned int)hw_sample_count, | 1139 | (long unsigned int)hw_sample_count, |
1077 | (long unsigned int)(stream->timer_abs_periods + | 1140 | (long unsigned int)(stream->timer_abs_periods + |
1078 | stream->timer_period_frag + PCXHR_GRANULARITY)); | 1141 | stream->timer_period_frag + |
1079 | 1142 | mgr->granularity)); | |
1080 | return hw_sample_count; | 1143 | return hw_sample_count; |
1081 | } | 1144 | } |
1082 | 1145 | ||
1083 | static void pcxhr_update_timer_pos(struct pcxhr_mgr *mgr, | 1146 | static void pcxhr_update_timer_pos(struct pcxhr_mgr *mgr, |
1084 | struct pcxhr_stream *stream, int samples_to_add) | 1147 | struct pcxhr_stream *stream, |
1148 | int samples_to_add) | ||
1085 | { | 1149 | { |
1086 | if (stream->substream && (stream->status == PCXHR_STREAM_STATUS_RUNNING)) { | 1150 | if (stream->substream && |
1151 | (stream->status == PCXHR_STREAM_STATUS_RUNNING)) { | ||
1087 | u_int64_t new_sample_count; | 1152 | u_int64_t new_sample_count; |
1088 | int elapsed = 0; | 1153 | int elapsed = 0; |
1089 | int hardware_read = 0; | 1154 | int hardware_read = 0; |
@@ -1092,20 +1157,22 @@ static void pcxhr_update_timer_pos(struct pcxhr_mgr *mgr, | |||
1092 | if (samples_to_add < 0) { | 1157 | if (samples_to_add < 0) { |
1093 | stream->timer_is_synced = 0; | 1158 | stream->timer_is_synced = 0; |
1094 | /* add default if no hardware_read possible */ | 1159 | /* add default if no hardware_read possible */ |
1095 | samples_to_add = PCXHR_GRANULARITY; | 1160 | samples_to_add = mgr->granularity; |
1096 | } | 1161 | } |
1097 | 1162 | ||
1098 | if (!stream->timer_is_synced) { | 1163 | if (!stream->timer_is_synced) { |
1099 | if (stream->timer_abs_periods != 0 || | 1164 | if ((stream->timer_abs_periods != 0) || |
1100 | stream->timer_period_frag + PCXHR_GRANULARITY >= | 1165 | ((stream->timer_period_frag + samples_to_add) >= |
1101 | runtime->period_size) { | 1166 | runtime->period_size)) { |
1102 | new_sample_count = pcxhr_stream_read_position(mgr, stream); | 1167 | new_sample_count = |
1168 | pcxhr_stream_read_position(mgr, stream); | ||
1103 | hardware_read = 1; | 1169 | hardware_read = 1; |
1104 | if (new_sample_count >= PCXHR_GRANULARITY_MIN) { | 1170 | if (new_sample_count >= mgr->granularity) { |
1105 | /* sub security offset because of jitter and | 1171 | /* sub security offset because of |
1106 | * finer granularity of dsp time (MBOX4) | 1172 | * jitter and finer granularity of |
1173 | * dsp time (MBOX4) | ||
1107 | */ | 1174 | */ |
1108 | new_sample_count -= PCXHR_GRANULARITY_MIN; | 1175 | new_sample_count -= mgr->granularity; |
1109 | stream->timer_is_synced = 1; | 1176 | stream->timer_is_synced = 1; |
1110 | } | 1177 | } |
1111 | } | 1178 | } |
@@ -1128,12 +1195,15 @@ static void pcxhr_update_timer_pos(struct pcxhr_mgr *mgr, | |||
1128 | stream->timer_buf_periods = 0; | 1195 | stream->timer_buf_periods = 0; |
1129 | stream->timer_abs_periods = new_elapse_pos; | 1196 | stream->timer_abs_periods = new_elapse_pos; |
1130 | } | 1197 | } |
1131 | if (new_sample_count >= stream->timer_abs_periods) | 1198 | if (new_sample_count >= stream->timer_abs_periods) { |
1132 | stream->timer_period_frag = (u_int32_t)(new_sample_count - | 1199 | stream->timer_period_frag = |
1133 | stream->timer_abs_periods); | 1200 | (u_int32_t)(new_sample_count - |
1134 | else | 1201 | stream->timer_abs_periods); |
1135 | snd_printk(KERN_ERR "ERROR new_sample_count too small ??? %lx\n", | 1202 | } else { |
1203 | snd_printk(KERN_ERR | ||
1204 | "ERROR new_sample_count too small ??? %ld\n", | ||
1136 | (long unsigned int)new_sample_count); | 1205 | (long unsigned int)new_sample_count); |
1206 | } | ||
1137 | 1207 | ||
1138 | if (elapsed) { | 1208 | if (elapsed) { |
1139 | spin_unlock(&mgr->lock); | 1209 | spin_unlock(&mgr->lock); |
@@ -1143,7 +1213,6 @@ static void pcxhr_update_timer_pos(struct pcxhr_mgr *mgr, | |||
1143 | } | 1213 | } |
1144 | } | 1214 | } |
1145 | 1215 | ||
1146 | |||
1147 | irqreturn_t pcxhr_interrupt(int irq, void *dev_id) | 1216 | irqreturn_t pcxhr_interrupt(int irq, void *dev_id) |
1148 | { | 1217 | { |
1149 | struct pcxhr_mgr *mgr = dev_id; | 1218 | struct pcxhr_mgr *mgr = dev_id; |
@@ -1156,7 +1225,8 @@ irqreturn_t pcxhr_interrupt(int irq, void *dev_id) | |||
1156 | reg = PCXHR_INPL(mgr, PCXHR_PLX_IRQCS); | 1225 | reg = PCXHR_INPL(mgr, PCXHR_PLX_IRQCS); |
1157 | if (! (reg & PCXHR_IRQCS_ACTIVE_PCIDB)) { | 1226 | if (! (reg & PCXHR_IRQCS_ACTIVE_PCIDB)) { |
1158 | spin_unlock(&mgr->lock); | 1227 | spin_unlock(&mgr->lock); |
1159 | return IRQ_NONE; /* this device did not cause the interrupt */ | 1228 | /* this device did not cause the interrupt */ |
1229 | return IRQ_NONE; | ||
1160 | } | 1230 | } |
1161 | 1231 | ||
1162 | /* clear interrupt */ | 1232 | /* clear interrupt */ |
@@ -1167,10 +1237,12 @@ irqreturn_t pcxhr_interrupt(int irq, void *dev_id) | |||
1167 | if (reg & PCXHR_IRQ_TIMER) { | 1237 | if (reg & PCXHR_IRQ_TIMER) { |
1168 | int timer_toggle = reg & PCXHR_IRQ_TIMER; | 1238 | int timer_toggle = reg & PCXHR_IRQ_TIMER; |
1169 | /* is a 24 bit counter */ | 1239 | /* is a 24 bit counter */ |
1170 | int dsp_time_new = PCXHR_INPL(mgr, PCXHR_PLX_MBOX4) & PCXHR_DSP_TIME_MASK; | 1240 | int dsp_time_new = |
1241 | PCXHR_INPL(mgr, PCXHR_PLX_MBOX4) & PCXHR_DSP_TIME_MASK; | ||
1171 | int dsp_time_diff = dsp_time_new - mgr->dsp_time_last; | 1242 | int dsp_time_diff = dsp_time_new - mgr->dsp_time_last; |
1172 | 1243 | ||
1173 | if (dsp_time_diff < 0 && mgr->dsp_time_last != PCXHR_DSP_TIME_INVALID) { | 1244 | if ((dsp_time_diff < 0) && |
1245 | (mgr->dsp_time_last != PCXHR_DSP_TIME_INVALID)) { | ||
1174 | snd_printdd("ERROR DSP TIME old(%d) new(%d) -> " | 1246 | snd_printdd("ERROR DSP TIME old(%d) new(%d) -> " |
1175 | "resynchronize all streams\n", | 1247 | "resynchronize all streams\n", |
1176 | mgr->dsp_time_last, dsp_time_new); | 1248 | mgr->dsp_time_last, dsp_time_new); |
@@ -1178,40 +1250,49 @@ irqreturn_t pcxhr_interrupt(int irq, void *dev_id) | |||
1178 | } | 1250 | } |
1179 | #ifdef CONFIG_SND_DEBUG_VERBOSE | 1251 | #ifdef CONFIG_SND_DEBUG_VERBOSE |
1180 | if (dsp_time_diff == 0) | 1252 | if (dsp_time_diff == 0) |
1181 | snd_printdd("ERROR DSP TIME NO DIFF time(%d)\n", dsp_time_new); | 1253 | snd_printdd("ERROR DSP TIME NO DIFF time(%d)\n", |
1182 | else if (dsp_time_diff >= (2*PCXHR_GRANULARITY)) | 1254 | dsp_time_new); |
1255 | else if (dsp_time_diff >= (2*mgr->granularity)) | ||
1183 | snd_printdd("ERROR DSP TIME TOO BIG old(%d) add(%d)\n", | 1256 | snd_printdd("ERROR DSP TIME TOO BIG old(%d) add(%d)\n", |
1184 | mgr->dsp_time_last, dsp_time_new - mgr->dsp_time_last); | 1257 | mgr->dsp_time_last, |
1258 | dsp_time_new - mgr->dsp_time_last); | ||
1259 | else if (dsp_time_diff % mgr->granularity) | ||
1260 | snd_printdd("ERROR DSP TIME increased by %d\n", | ||
1261 | dsp_time_diff); | ||
1185 | #endif | 1262 | #endif |
1186 | mgr->dsp_time_last = dsp_time_new; | 1263 | mgr->dsp_time_last = dsp_time_new; |
1187 | 1264 | ||
1188 | if (timer_toggle == mgr->timer_toggle) | 1265 | if (timer_toggle == mgr->timer_toggle) { |
1189 | snd_printdd("ERROR TIMER TOGGLE\n"); | 1266 | snd_printdd("ERROR TIMER TOGGLE\n"); |
1267 | mgr->dsp_time_err++; | ||
1268 | } | ||
1190 | mgr->timer_toggle = timer_toggle; | 1269 | mgr->timer_toggle = timer_toggle; |
1191 | 1270 | ||
1192 | reg &= ~PCXHR_IRQ_TIMER; | 1271 | reg &= ~PCXHR_IRQ_TIMER; |
1193 | for (i = 0; i < mgr->num_cards; i++) { | 1272 | for (i = 0; i < mgr->num_cards; i++) { |
1194 | chip = mgr->chip[i]; | 1273 | chip = mgr->chip[i]; |
1195 | for (j = 0; j < chip->nb_streams_capt; j++) | 1274 | for (j = 0; j < chip->nb_streams_capt; j++) |
1196 | pcxhr_update_timer_pos(mgr, &chip->capture_stream[j], | 1275 | pcxhr_update_timer_pos(mgr, |
1197 | dsp_time_diff); | 1276 | &chip->capture_stream[j], |
1277 | dsp_time_diff); | ||
1198 | } | 1278 | } |
1199 | for (i = 0; i < mgr->num_cards; i++) { | 1279 | for (i = 0; i < mgr->num_cards; i++) { |
1200 | chip = mgr->chip[i]; | 1280 | chip = mgr->chip[i]; |
1201 | for (j = 0; j < chip->nb_streams_play; j++) | 1281 | for (j = 0; j < chip->nb_streams_play; j++) |
1202 | pcxhr_update_timer_pos(mgr, &chip->playback_stream[j], | 1282 | pcxhr_update_timer_pos(mgr, |
1203 | dsp_time_diff); | 1283 | &chip->playback_stream[j], |
1284 | dsp_time_diff); | ||
1204 | } | 1285 | } |
1205 | } | 1286 | } |
1206 | /* other irq's handled in the tasklet */ | 1287 | /* other irq's handled in the tasklet */ |
1207 | if (reg & PCXHR_IRQ_MASK) { | 1288 | if (reg & PCXHR_IRQ_MASK) { |
1208 | 1289 | if (reg & PCXHR_IRQ_ASYNC) { | |
1209 | /* as we didn't request any notifications, some kind of xrun error | 1290 | /* as we didn't request any async notifications, |
1210 | * will probably occured | 1291 | * some kind of xrun error will probably occured |
1211 | */ | 1292 | */ |
1212 | /* better resynchronize all streams next interrupt : */ | 1293 | /* better resynchronize all streams next interrupt : */ |
1213 | mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID; | 1294 | mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID; |
1214 | 1295 | } | |
1215 | mgr->src_it_dsp = reg; | 1296 | mgr->src_it_dsp = reg; |
1216 | tasklet_hi_schedule(&mgr->msg_taskq); | 1297 | tasklet_hi_schedule(&mgr->msg_taskq); |
1217 | } | 1298 | } |
diff --git a/sound/pci/pcxhr/pcxhr_core.h b/sound/pci/pcxhr/pcxhr_core.h index d9a4ab609875..bbbd66d13a64 100644 --- a/sound/pci/pcxhr/pcxhr_core.h +++ b/sound/pci/pcxhr/pcxhr_core.h | |||
@@ -65,7 +65,7 @@ enum { | |||
65 | CMD_RESYNC_AUDIO_INPUTS, /* cmd_len = 1 stat_len = 0 */ | 65 | CMD_RESYNC_AUDIO_INPUTS, /* cmd_len = 1 stat_len = 0 */ |
66 | CMD_GET_DSP_RESOURCES, /* cmd_len = 1 stat_len = 4 */ | 66 | CMD_GET_DSP_RESOURCES, /* cmd_len = 1 stat_len = 4 */ |
67 | CMD_SET_TIMER_INTERRUPT, /* cmd_len = 1 stat_len = 0 */ | 67 | CMD_SET_TIMER_INTERRUPT, /* cmd_len = 1 stat_len = 0 */ |
68 | CMD_RES_PIPE, /* cmd_len = 2 stat_len = 0 */ | 68 | CMD_RES_PIPE, /* cmd_len >=2 stat_len = 0 */ |
69 | CMD_FREE_PIPE, /* cmd_len = 1 stat_len = 0 */ | 69 | CMD_FREE_PIPE, /* cmd_len = 1 stat_len = 0 */ |
70 | CMD_CONF_PIPE, /* cmd_len = 2 stat_len = 0 */ | 70 | CMD_CONF_PIPE, /* cmd_len = 2 stat_len = 0 */ |
71 | CMD_STOP_PIPE, /* cmd_len = 1 stat_len = 0 */ | 71 | CMD_STOP_PIPE, /* cmd_len = 1 stat_len = 0 */ |
@@ -96,6 +96,8 @@ void pcxhr_init_rmh(struct pcxhr_rmh *rmh, int cmd); | |||
96 | void pcxhr_set_pipe_cmd_params(struct pcxhr_rmh* rmh, int capture, unsigned int param1, | 96 | void pcxhr_set_pipe_cmd_params(struct pcxhr_rmh* rmh, int capture, unsigned int param1, |
97 | unsigned int param2, unsigned int param3); | 97 | unsigned int param2, unsigned int param3); |
98 | 98 | ||
99 | #define DSP_EXT_CMD_SET(x) (x->dsp_version > 0x012800) | ||
100 | |||
99 | /* | 101 | /* |
100 | send the rmh | 102 | send the rmh |
101 | */ | 103 | */ |
@@ -110,6 +112,7 @@ int pcxhr_send_msg(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh); | |||
110 | #define IO_NUM_REG_STATUS 5 | 112 | #define IO_NUM_REG_STATUS 5 |
111 | #define IO_NUM_REG_CUER 10 | 113 | #define IO_NUM_REG_CUER 10 |
112 | #define IO_NUM_UER_CHIP_REG 11 | 114 | #define IO_NUM_UER_CHIP_REG 11 |
115 | #define IO_NUM_REG_CONFIG_SRC 12 | ||
113 | #define IO_NUM_REG_OUT_ANA_LEVEL 20 | 116 | #define IO_NUM_REG_OUT_ANA_LEVEL 20 |
114 | #define IO_NUM_REG_IN_ANA_LEVEL 21 | 117 | #define IO_NUM_REG_IN_ANA_LEVEL 21 |
115 | 118 | ||