diff options
-rw-r--r-- | arch/powerpc/platforms/cell/axon_msi.c | 4 | ||||
-rw-r--r-- | arch/powerpc/sysdev/mpic.c | 4 | ||||
-rw-r--r-- | drivers/net/ibm_emac/ibm_emac_mal.h | 4 | ||||
-rw-r--r-- | drivers/net/ibm_newemac/mal.h | 4 | ||||
-rw-r--r-- | include/asm-powerpc/dcr-mmio.h | 4 | ||||
-rw-r--r-- | include/asm-powerpc/dcr-native.h | 4 |
6 files changed, 12 insertions, 12 deletions
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c index 1245b2f517bb..aca15007a01c 100644 --- a/arch/powerpc/platforms/cell/axon_msi.c +++ b/arch/powerpc/platforms/cell/axon_msi.c | |||
@@ -77,12 +77,12 @@ static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val) | |||
77 | { | 77 | { |
78 | pr_debug("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n); | 78 | pr_debug("axon_msi: dcr_write(0x%x, 0x%x)\n", val, dcr_n); |
79 | 79 | ||
80 | dcr_write(msic->dcr_host, msic->dcr_host.base + dcr_n, val); | 80 | dcr_write(msic->dcr_host, dcr_n, val); |
81 | } | 81 | } |
82 | 82 | ||
83 | static u32 msic_dcr_read(struct axon_msic *msic, unsigned int dcr_n) | 83 | static u32 msic_dcr_read(struct axon_msic *msic, unsigned int dcr_n) |
84 | { | 84 | { |
85 | return dcr_read(msic->dcr_host, msic->dcr_host.base + dcr_n); | 85 | return dcr_read(msic->dcr_host, dcr_n); |
86 | } | 86 | } |
87 | 87 | ||
88 | static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) | 88 | static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc) |
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 893e65439e85..e47938899a92 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c | |||
@@ -156,7 +156,7 @@ static inline u32 _mpic_read(enum mpic_reg_type type, | |||
156 | switch(type) { | 156 | switch(type) { |
157 | #ifdef CONFIG_PPC_DCR | 157 | #ifdef CONFIG_PPC_DCR |
158 | case mpic_access_dcr: | 158 | case mpic_access_dcr: |
159 | return dcr_read(rb->dhost, rb->dhost.base + reg); | 159 | return dcr_read(rb->dhost, reg); |
160 | #endif | 160 | #endif |
161 | case mpic_access_mmio_be: | 161 | case mpic_access_mmio_be: |
162 | return in_be32(rb->base + (reg >> 2)); | 162 | return in_be32(rb->base + (reg >> 2)); |
@@ -173,7 +173,7 @@ static inline void _mpic_write(enum mpic_reg_type type, | |||
173 | switch(type) { | 173 | switch(type) { |
174 | #ifdef CONFIG_PPC_DCR | 174 | #ifdef CONFIG_PPC_DCR |
175 | case mpic_access_dcr: | 175 | case mpic_access_dcr: |
176 | return dcr_write(rb->dhost, rb->dhost.base + reg, value); | 176 | return dcr_write(rb->dhost, reg, value); |
177 | #endif | 177 | #endif |
178 | case mpic_access_mmio_be: | 178 | case mpic_access_mmio_be: |
179 | return out_be32(rb->base + (reg >> 2), value); | 179 | return out_be32(rb->base + (reg >> 2), value); |
diff --git a/drivers/net/ibm_emac/ibm_emac_mal.h b/drivers/net/ibm_emac/ibm_emac_mal.h index aa76d3f0dfce..b8adbe6d4b01 100644 --- a/drivers/net/ibm_emac/ibm_emac_mal.h +++ b/drivers/net/ibm_emac/ibm_emac_mal.h | |||
@@ -208,12 +208,12 @@ struct ibm_ocp_mal { | |||
208 | 208 | ||
209 | static inline u32 get_mal_dcrn(struct ibm_ocp_mal *mal, int reg) | 209 | static inline u32 get_mal_dcrn(struct ibm_ocp_mal *mal, int reg) |
210 | { | 210 | { |
211 | return dcr_read(mal->dcrhost, mal->dcrhost.base + reg); | 211 | return dcr_read(mal->dcrhost, reg); |
212 | } | 212 | } |
213 | 213 | ||
214 | static inline void set_mal_dcrn(struct ibm_ocp_mal *mal, int reg, u32 val) | 214 | static inline void set_mal_dcrn(struct ibm_ocp_mal *mal, int reg, u32 val) |
215 | { | 215 | { |
216 | dcr_write(mal->dcrhost, mal->dcrhost.base + reg, val); | 216 | dcr_write(mal->dcrhost, reg, val); |
217 | } | 217 | } |
218 | 218 | ||
219 | /* Register MAL devices */ | 219 | /* Register MAL devices */ |
diff --git a/drivers/net/ibm_newemac/mal.h b/drivers/net/ibm_newemac/mal.h index 6daa98e5992e..784edb8ea822 100644 --- a/drivers/net/ibm_newemac/mal.h +++ b/drivers/net/ibm_newemac/mal.h | |||
@@ -212,12 +212,12 @@ struct mal_instance { | |||
212 | 212 | ||
213 | static inline u32 get_mal_dcrn(struct mal_instance *mal, int reg) | 213 | static inline u32 get_mal_dcrn(struct mal_instance *mal, int reg) |
214 | { | 214 | { |
215 | return dcr_read(mal->dcr_host, mal->dcr_host.base + reg); | 215 | return dcr_read(mal->dcr_host, reg); |
216 | } | 216 | } |
217 | 217 | ||
218 | static inline void set_mal_dcrn(struct mal_instance *mal, int reg, u32 val) | 218 | static inline void set_mal_dcrn(struct mal_instance *mal, int reg, u32 val) |
219 | { | 219 | { |
220 | dcr_write(mal->dcr_host, mal->dcr_host.base + reg, val); | 220 | dcr_write(mal->dcr_host, reg, val); |
221 | } | 221 | } |
222 | 222 | ||
223 | /* Register MAL devices */ | 223 | /* Register MAL devices */ |
diff --git a/include/asm-powerpc/dcr-mmio.h b/include/asm-powerpc/dcr-mmio.h index 6b82c3ba495a..a7d9eaf22702 100644 --- a/include/asm-powerpc/dcr-mmio.h +++ b/include/asm-powerpc/dcr-mmio.h | |||
@@ -37,12 +37,12 @@ extern void dcr_unmap(dcr_host_t host, unsigned int dcr_n, unsigned int dcr_c); | |||
37 | 37 | ||
38 | static inline u32 dcr_read(dcr_host_t host, unsigned int dcr_n) | 38 | static inline u32 dcr_read(dcr_host_t host, unsigned int dcr_n) |
39 | { | 39 | { |
40 | return in_be32(host.token + dcr_n * host.stride); | 40 | return in_be32(host.token + ((host.base + dcr_n) * host.stride)); |
41 | } | 41 | } |
42 | 42 | ||
43 | static inline void dcr_write(dcr_host_t host, unsigned int dcr_n, u32 value) | 43 | static inline void dcr_write(dcr_host_t host, unsigned int dcr_n, u32 value) |
44 | { | 44 | { |
45 | out_be32(host.token + dcr_n * host.stride, value); | 45 | out_be32(host.token + ((host.base + dcr_n) * host.stride), value); |
46 | } | 46 | } |
47 | 47 | ||
48 | extern u64 of_translate_dcr_address(struct device_node *dev, | 48 | extern u64 of_translate_dcr_address(struct device_node *dev, |
diff --git a/include/asm-powerpc/dcr-native.h b/include/asm-powerpc/dcr-native.h index f41058c0f6cb..3bc780f6513a 100644 --- a/include/asm-powerpc/dcr-native.h +++ b/include/asm-powerpc/dcr-native.h | |||
@@ -30,8 +30,8 @@ typedef struct { | |||
30 | 30 | ||
31 | #define dcr_map(dev, dcr_n, dcr_c) ((dcr_host_t){ .base = (dcr_n) }) | 31 | #define dcr_map(dev, dcr_n, dcr_c) ((dcr_host_t){ .base = (dcr_n) }) |
32 | #define dcr_unmap(host, dcr_n, dcr_c) do {} while (0) | 32 | #define dcr_unmap(host, dcr_n, dcr_c) do {} while (0) |
33 | #define dcr_read(host, dcr_n) mfdcr(dcr_n) | 33 | #define dcr_read(host, dcr_n) mfdcr(dcr_n + host.base) |
34 | #define dcr_write(host, dcr_n, value) mtdcr(dcr_n, value) | 34 | #define dcr_write(host, dcr_n, value) mtdcr(dcr_n + host.base, value) |
35 | 35 | ||
36 | /* Device Control Registers */ | 36 | /* Device Control Registers */ |
37 | void __mtdcr(int reg, unsigned int val); | 37 | void __mtdcr(int reg, unsigned int val); |