aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/m68k/include/asm/checksum.h173
-rw-r--r--arch/m68k/include/asm/checksum_mm.h148
-rw-r--r--arch/m68k/include/asm/checksum_no.h132
-rw-r--r--arch/m68k/include/asm/dma.h492
-rw-r--r--arch/m68k/include/asm/dma_mm.h16
-rw-r--r--arch/m68k/include/asm/dma_no.h494
-rw-r--r--arch/m68k/include/asm/elia.h41
-rw-r--r--arch/m68k/include/asm/gpio.h238
-rw-r--r--arch/m68k/include/asm/hardirq_no.h10
-rw-r--r--arch/m68k/include/asm/io_no.h2
-rw-r--r--arch/m68k/include/asm/irq.h135
-rw-r--r--arch/m68k/include/asm/irq_mm.h126
-rw-r--r--arch/m68k/include/asm/irq_no.h26
-rw-r--r--arch/m68k/include/asm/m5206sim.h33
-rw-r--r--arch/m68k/include/asm/m520xsim.h77
-rw-r--r--arch/m68k/include/asm/m523xsim.h77
-rw-r--r--arch/m68k/include/asm/m5249sim.h54
-rw-r--r--arch/m68k/include/asm/m5272sim.h62
-rw-r--r--arch/m68k/include/asm/m527xsim.h169
-rw-r--r--arch/m68k/include/asm/m528xsim.h151
-rw-r--r--arch/m68k/include/asm/m5307sim.h32
-rw-r--r--arch/m68k/include/asm/m532xsim.h198
-rw-r--r--arch/m68k/include/asm/m5407sim.h28
-rw-r--r--arch/m68k/include/asm/mcfgpio.h40
-rw-r--r--arch/m68k/include/asm/mcfintc.h89
-rw-r--r--arch/m68k/include/asm/mcfne.h83
-rw-r--r--arch/m68k/include/asm/mcfsim.h95
-rw-r--r--arch/m68k/include/asm/mcfsmc.h6
-rw-r--r--arch/m68k/include/asm/nettel.h4
-rw-r--r--arch/m68k/include/asm/page_no.h4
-rw-r--r--arch/m68k/include/asm/pinmux.h30
-rw-r--r--arch/m68k/include/asm/processor.h171
-rw-r--r--arch/m68k/include/asm/processor_mm.h130
-rw-r--r--arch/m68k/include/asm/processor_no.h143
-rw-r--r--arch/m68k/include/asm/timex.h17
-rw-r--r--arch/m68knommu/Kconfig6
-rw-r--r--arch/m68knommu/kernel/irq.c26
-rw-r--r--arch/m68knommu/kernel/time.c2
-rw-r--r--arch/m68knommu/lib/checksum.c11
-rw-r--r--arch/m68knommu/platform/5206/Makefile2
-rw-r--r--arch/m68knommu/platform/5206/config.c56
-rw-r--r--arch/m68knommu/platform/5206/gpio.c49
-rw-r--r--arch/m68knommu/platform/5206e/Makefile2
-rw-r--r--arch/m68knommu/platform/5206e/config.c58
-rw-r--r--arch/m68knommu/platform/5206e/gpio.c49
-rw-r--r--arch/m68knommu/platform/520x/Makefile2
-rw-r--r--arch/m68knommu/platform/520x/config.c30
-rw-r--r--arch/m68knommu/platform/520x/gpio.c211
-rw-r--r--arch/m68knommu/platform/523x/Makefile2
-rw-r--r--arch/m68knommu/platform/523x/config.c66
-rw-r--r--arch/m68knommu/platform/523x/gpio.c283
-rw-r--r--arch/m68knommu/platform/5249/Makefile2
-rw-r--r--arch/m68knommu/platform/5249/config.c49
-rw-r--r--arch/m68knommu/platform/5249/gpio.c65
-rw-r--r--arch/m68knommu/platform/5249/intc2.c59
-rw-r--r--arch/m68knommu/platform/5272/Makefile2
-rw-r--r--arch/m68knommu/platform/5272/config.c78
-rw-r--r--arch/m68knommu/platform/5272/gpio.c81
-rw-r--r--arch/m68knommu/platform/5272/intc.c138
-rw-r--r--arch/m68knommu/platform/527x/Makefile2
-rw-r--r--arch/m68knommu/platform/527x/config.c49
-rw-r--r--arch/m68knommu/platform/527x/gpio.c607
-rw-r--r--arch/m68knommu/platform/528x/Makefile2
-rw-r--r--arch/m68knommu/platform/528x/config.c51
-rw-r--r--arch/m68knommu/platform/528x/gpio.c438
-rw-r--r--arch/m68knommu/platform/5307/Makefile2
-rw-r--r--arch/m68knommu/platform/5307/config.c65
-rw-r--r--arch/m68knommu/platform/5307/gpio.c49
-rw-r--r--arch/m68knommu/platform/532x/Makefile2
-rw-r--r--arch/m68knommu/platform/532x/config.c53
-rw-r--r--arch/m68knommu/platform/532x/gpio.c337
-rw-r--r--arch/m68knommu/platform/5407/Makefile2
-rw-r--r--arch/m68knommu/platform/5407/config.c68
-rw-r--r--arch/m68knommu/platform/5407/gpio.c49
-rw-r--r--arch/m68knommu/platform/68328/ints.c72
-rw-r--r--arch/m68knommu/platform/68360/ints.c44
-rw-r--r--arch/m68knommu/platform/coldfire/Makefile21
-rw-r--r--arch/m68knommu/platform/coldfire/gpio.c127
-rw-r--r--arch/m68knommu/platform/coldfire/intc-2.c93
-rw-r--r--arch/m68knommu/platform/coldfire/intc-simr.c78
-rw-r--r--arch/m68knommu/platform/coldfire/intc.c153
-rw-r--r--arch/m68knommu/platform/coldfire/pinmux.c28
-rw-r--r--arch/m68knommu/platform/coldfire/pit.c8
-rw-r--r--arch/m68knommu/platform/coldfire/timers.c18
-rw-r--r--arch/m68knommu/platform/coldfire/vectors.c20
-rw-r--r--drivers/net/fec.c18
86 files changed, 5202 insertions, 2309 deletions
diff --git a/arch/m68k/include/asm/checksum.h b/arch/m68k/include/asm/checksum.h
index 1cf544767453..ec514485c8b6 100644
--- a/arch/m68k/include/asm/checksum.h
+++ b/arch/m68k/include/asm/checksum.h
@@ -1,5 +1,170 @@
1#ifdef __uClinux__ 1#ifndef _M68K_CHECKSUM_H
2#include "checksum_no.h" 2#define _M68K_CHECKSUM_H
3
4#include <linux/in6.h>
5
6/*
7 * computes the checksum of a memory block at buff, length len,
8 * and adds in "sum" (32-bit)
9 *
10 * returns a 32-bit number suitable for feeding into itself
11 * or csum_tcpudp_magic
12 *
13 * this function must be called with even lengths, except
14 * for the last fragment, which may be odd
15 *
16 * it's best to have buff aligned on a 32-bit boundary
17 */
18__wsum csum_partial(const void *buff, int len, __wsum sum);
19
20/*
21 * the same as csum_partial, but copies from src while it
22 * checksums
23 *
24 * here even more important to align src and dst on a 32-bit (or even
25 * better 64-bit) boundary
26 */
27
28extern __wsum csum_partial_copy_from_user(const void __user *src,
29 void *dst,
30 int len, __wsum sum,
31 int *csum_err);
32
33extern __wsum csum_partial_copy_nocheck(const void *src,
34 void *dst, int len,
35 __wsum sum);
36
37
38#ifdef CONFIG_COLDFIRE
39
40/*
41 * The ColdFire cores don't support all the 68k instructions used
42 * in the optimized checksum code below. So it reverts back to using
43 * more standard C coded checksums. The fast checksum code is
44 * significantly larger than the optimized version, so it is not
45 * inlined here.
46 */
47__sum16 ip_fast_csum(const void *iph, unsigned int ihl);
48
49static inline __sum16 csum_fold(__wsum sum)
50{
51 unsigned int tmp = (__force u32)sum;
52
53 tmp = (tmp & 0xffff) + (tmp >> 16);
54 tmp = (tmp & 0xffff) + (tmp >> 16);
55
56 return (__force __sum16)~tmp;
57}
58
3#else 59#else
4#include "checksum_mm.h" 60
5#endif 61/*
62 * This is a version of ip_fast_csum() optimized for IP headers,
63 * which always checksum on 4 octet boundaries.
64 */
65static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
66{
67 unsigned int sum = 0;
68 unsigned long tmp;
69
70 __asm__ ("subqw #1,%2\n"
71 "1:\t"
72 "movel %1@+,%3\n\t"
73 "addxl %3,%0\n\t"
74 "dbra %2,1b\n\t"
75 "movel %0,%3\n\t"
76 "swap %3\n\t"
77 "addxw %3,%0\n\t"
78 "clrw %3\n\t"
79 "addxw %3,%0\n\t"
80 : "=d" (sum), "=&a" (iph), "=&d" (ihl), "=&d" (tmp)
81 : "0" (sum), "1" (iph), "2" (ihl)
82 : "memory");
83 return (__force __sum16)~sum;
84}
85
86static inline __sum16 csum_fold(__wsum sum)
87{
88 unsigned int tmp = (__force u32)sum;
89
90 __asm__("swap %1\n\t"
91 "addw %1, %0\n\t"
92 "clrw %1\n\t"
93 "addxw %1, %0"
94 : "=&d" (sum), "=&d" (tmp)
95 : "0" (sum), "1" (tmp));
96
97 return (__force __sum16)~sum;
98}
99
100#endif /* CONFIG_COLDFIRE */
101
102static inline __wsum
103csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
104 unsigned short proto, __wsum sum)
105{
106 __asm__ ("addl %2,%0\n\t"
107 "addxl %3,%0\n\t"
108 "addxl %4,%0\n\t"
109 "clrl %1\n\t"
110 "addxl %1,%0"
111 : "=&d" (sum), "=d" (saddr)
112 : "g" (daddr), "1" (saddr), "d" (len + proto),
113 "0" (sum));
114 return sum;
115}
116
117
118/*
119 * computes the checksum of the TCP/UDP pseudo-header
120 * returns a 16-bit checksum, already complemented
121 */
122static inline __sum16
123csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
124 unsigned short proto, __wsum sum)
125{
126 return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
127}
128
129/*
130 * this routine is used for miscellaneous IP-like checksums, mainly
131 * in icmp.c
132 */
133
134static inline __sum16 ip_compute_csum(const void *buff, int len)
135{
136 return csum_fold (csum_partial(buff, len, 0));
137}
138
139#define _HAVE_ARCH_IPV6_CSUM
140static __inline__ __sum16
141csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr,
142 __u32 len, unsigned short proto, __wsum sum)
143{
144 register unsigned long tmp;
145 __asm__("addl %2@,%0\n\t"
146 "movel %2@(4),%1\n\t"
147 "addxl %1,%0\n\t"
148 "movel %2@(8),%1\n\t"
149 "addxl %1,%0\n\t"
150 "movel %2@(12),%1\n\t"
151 "addxl %1,%0\n\t"
152 "movel %3@,%1\n\t"
153 "addxl %1,%0\n\t"
154 "movel %3@(4),%1\n\t"
155 "addxl %1,%0\n\t"
156 "movel %3@(8),%1\n\t"
157 "addxl %1,%0\n\t"
158 "movel %3@(12),%1\n\t"
159 "addxl %1,%0\n\t"
160 "addxl %4,%0\n\t"
161 "clrl %1\n\t"
162 "addxl %1,%0"
163 : "=&d" (sum), "=&d" (tmp)
164 : "a" (saddr), "a" (daddr), "d" (len + proto),
165 "0" (sum));
166
167 return csum_fold(sum);
168}
169
170#endif /* _M68K_CHECKSUM_H */
diff --git a/arch/m68k/include/asm/checksum_mm.h b/arch/m68k/include/asm/checksum_mm.h
deleted file mode 100644
index 494f9aec37ea..000000000000
--- a/arch/m68k/include/asm/checksum_mm.h
+++ /dev/null
@@ -1,148 +0,0 @@
1#ifndef _M68K_CHECKSUM_H
2#define _M68K_CHECKSUM_H
3
4#include <linux/in6.h>
5
6/*
7 * computes the checksum of a memory block at buff, length len,
8 * and adds in "sum" (32-bit)
9 *
10 * returns a 32-bit number suitable for feeding into itself
11 * or csum_tcpudp_magic
12 *
13 * this function must be called with even lengths, except
14 * for the last fragment, which may be odd
15 *
16 * it's best to have buff aligned on a 32-bit boundary
17 */
18__wsum csum_partial(const void *buff, int len, __wsum sum);
19
20/*
21 * the same as csum_partial, but copies from src while it
22 * checksums
23 *
24 * here even more important to align src and dst on a 32-bit (or even
25 * better 64-bit) boundary
26 */
27
28extern __wsum csum_partial_copy_from_user(const void __user *src,
29 void *dst,
30 int len, __wsum sum,
31 int *csum_err);
32
33extern __wsum csum_partial_copy_nocheck(const void *src,
34 void *dst, int len,
35 __wsum sum);
36
37/*
38 * This is a version of ip_compute_csum() optimized for IP headers,
39 * which always checksum on 4 octet boundaries.
40 *
41 */
42static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
43{
44 unsigned int sum = 0;
45 unsigned long tmp;
46
47 __asm__ ("subqw #1,%2\n"
48 "1:\t"
49 "movel %1@+,%3\n\t"
50 "addxl %3,%0\n\t"
51 "dbra %2,1b\n\t"
52 "movel %0,%3\n\t"
53 "swap %3\n\t"
54 "addxw %3,%0\n\t"
55 "clrw %3\n\t"
56 "addxw %3,%0\n\t"
57 : "=d" (sum), "=&a" (iph), "=&d" (ihl), "=&d" (tmp)
58 : "0" (sum), "1" (iph), "2" (ihl)
59 : "memory");
60 return (__force __sum16)~sum;
61}
62
63/*
64 * Fold a partial checksum
65 */
66
67static inline __sum16 csum_fold(__wsum sum)
68{
69 unsigned int tmp = (__force u32)sum;
70 __asm__("swap %1\n\t"
71 "addw %1, %0\n\t"
72 "clrw %1\n\t"
73 "addxw %1, %0"
74 : "=&d" (sum), "=&d" (tmp)
75 : "0" (sum), "1" (tmp));
76 return (__force __sum16)~sum;
77}
78
79
80static inline __wsum
81csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
82 unsigned short proto, __wsum sum)
83{
84 __asm__ ("addl %2,%0\n\t"
85 "addxl %3,%0\n\t"
86 "addxl %4,%0\n\t"
87 "clrl %1\n\t"
88 "addxl %1,%0"
89 : "=&d" (sum), "=d" (saddr)
90 : "g" (daddr), "1" (saddr), "d" (len + proto),
91 "0" (sum));
92 return sum;
93}
94
95
96/*
97 * computes the checksum of the TCP/UDP pseudo-header
98 * returns a 16-bit checksum, already complemented
99 */
100static inline __sum16
101csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
102 unsigned short proto, __wsum sum)
103{
104 return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
105}
106
107/*
108 * this routine is used for miscellaneous IP-like checksums, mainly
109 * in icmp.c
110 */
111
112static inline __sum16 ip_compute_csum(const void *buff, int len)
113{
114 return csum_fold (csum_partial(buff, len, 0));
115}
116
117#define _HAVE_ARCH_IPV6_CSUM
118static __inline__ __sum16
119csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr,
120 __u32 len, unsigned short proto, __wsum sum)
121{
122 register unsigned long tmp;
123 __asm__("addl %2@,%0\n\t"
124 "movel %2@(4),%1\n\t"
125 "addxl %1,%0\n\t"
126 "movel %2@(8),%1\n\t"
127 "addxl %1,%0\n\t"
128 "movel %2@(12),%1\n\t"
129 "addxl %1,%0\n\t"
130 "movel %3@,%1\n\t"
131 "addxl %1,%0\n\t"
132 "movel %3@(4),%1\n\t"
133 "addxl %1,%0\n\t"
134 "movel %3@(8),%1\n\t"
135 "addxl %1,%0\n\t"
136 "movel %3@(12),%1\n\t"
137 "addxl %1,%0\n\t"
138 "addxl %4,%0\n\t"
139 "clrl %1\n\t"
140 "addxl %1,%0"
141 : "=&d" (sum), "=&d" (tmp)
142 : "a" (saddr), "a" (daddr), "d" (len + proto),
143 "0" (sum));
144
145 return csum_fold(sum);
146}
147
148#endif /* _M68K_CHECKSUM_H */
diff --git a/arch/m68k/include/asm/checksum_no.h b/arch/m68k/include/asm/checksum_no.h
deleted file mode 100644
index 81883482ffb1..000000000000
--- a/arch/m68k/include/asm/checksum_no.h
+++ /dev/null
@@ -1,132 +0,0 @@
1#ifndef _M68K_CHECKSUM_H
2#define _M68K_CHECKSUM_H
3
4#include <linux/in6.h>
5
6/*
7 * computes the checksum of a memory block at buff, length len,
8 * and adds in "sum" (32-bit)
9 *
10 * returns a 32-bit number suitable for feeding into itself
11 * or csum_tcpudp_magic
12 *
13 * this function must be called with even lengths, except
14 * for the last fragment, which may be odd
15 *
16 * it's best to have buff aligned on a 32-bit boundary
17 */
18__wsum csum_partial(const void *buff, int len, __wsum sum);
19
20/*
21 * the same as csum_partial, but copies from src while it
22 * checksums
23 *
24 * here even more important to align src and dst on a 32-bit (or even
25 * better 64-bit) boundary
26 */
27
28__wsum csum_partial_copy_nocheck(const void *src, void *dst,
29 int len, __wsum sum);
30
31
32/*
33 * the same as csum_partial_copy, but copies from user space.
34 *
35 * here even more important to align src and dst on a 32-bit (or even
36 * better 64-bit) boundary
37 */
38
39extern __wsum csum_partial_copy_from_user(const void __user *src,
40 void *dst, int len, __wsum sum, int *csum_err);
41
42__sum16 ip_fast_csum(const void *iph, unsigned int ihl);
43
44/*
45 * Fold a partial checksum
46 */
47
48static inline __sum16 csum_fold(__wsum sum)
49{
50 unsigned int tmp = (__force u32)sum;
51#ifdef CONFIG_COLDFIRE
52 tmp = (tmp & 0xffff) + (tmp >> 16);
53 tmp = (tmp & 0xffff) + (tmp >> 16);
54 return (__force __sum16)~tmp;
55#else
56 __asm__("swap %1\n\t"
57 "addw %1, %0\n\t"
58 "clrw %1\n\t"
59 "addxw %1, %0"
60 : "=&d" (sum), "=&d" (tmp)
61 : "0" (sum), "1" (sum));
62 return (__force __sum16)~sum;
63#endif
64}
65
66
67/*
68 * computes the checksum of the TCP/UDP pseudo-header
69 * returns a 16-bit checksum, already complemented
70 */
71
72static inline __wsum
73csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
74 unsigned short proto, __wsum sum)
75{
76 __asm__ ("addl %1,%0\n\t"
77 "addxl %4,%0\n\t"
78 "addxl %5,%0\n\t"
79 "clrl %1\n\t"
80 "addxl %1,%0"
81 : "=&d" (sum), "=&d" (saddr)
82 : "0" (daddr), "1" (saddr), "d" (len + proto),
83 "d"(sum));
84 return sum;
85}
86
87static inline __sum16
88csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
89 unsigned short proto, __wsum sum)
90{
91 return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
92}
93
94/*
95 * this routine is used for miscellaneous IP-like checksums, mainly
96 * in icmp.c
97 */
98
99extern __sum16 ip_compute_csum(const void *buff, int len);
100
101#define _HAVE_ARCH_IPV6_CSUM
102static __inline__ __sum16
103csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr,
104 __u32 len, unsigned short proto, __wsum sum)
105{
106 register unsigned long tmp;
107 __asm__("addl %2@,%0\n\t"
108 "movel %2@(4),%1\n\t"
109 "addxl %1,%0\n\t"
110 "movel %2@(8),%1\n\t"
111 "addxl %1,%0\n\t"
112 "movel %2@(12),%1\n\t"
113 "addxl %1,%0\n\t"
114 "movel %3@,%1\n\t"
115 "addxl %1,%0\n\t"
116 "movel %3@(4),%1\n\t"
117 "addxl %1,%0\n\t"
118 "movel %3@(8),%1\n\t"
119 "addxl %1,%0\n\t"
120 "movel %3@(12),%1\n\t"
121 "addxl %1,%0\n\t"
122 "addxl %4,%0\n\t"
123 "clrl %1\n\t"
124 "addxl %1,%0"
125 : "=&d" (sum), "=&d" (tmp)
126 : "a" (saddr), "a" (daddr), "d" (len + proto),
127 "0" (sum));
128
129 return csum_fold(sum);
130}
131
132#endif /* _M68K_CHECKSUM_H */
diff --git a/arch/m68k/include/asm/dma.h b/arch/m68k/include/asm/dma.h
index b82e660cf1c2..6fbdfe895104 100644
--- a/arch/m68k/include/asm/dma.h
+++ b/arch/m68k/include/asm/dma.h
@@ -1,5 +1,491 @@
1#ifdef __uClinux__ 1#ifndef _M68K_DMA_H
2#include "dma_no.h" 2#define _M68K_DMA_H 1
3
4#ifdef CONFIG_COLDFIRE
5/*
6 * ColdFire DMA Model:
7 * ColdFire DMA supports two forms of DMA: Single and Dual address. Single
8 * address mode emits a source address, and expects that the device will either
9 * pick up the data (DMA READ) or source data (DMA WRITE). This implies that
10 * the device will place data on the correct byte(s) of the data bus, as the
11 * memory transactions are always 32 bits. This implies that only 32 bit
12 * devices will find single mode transfers useful. Dual address DMA mode
13 * performs two cycles: source read and destination write. ColdFire will
14 * align the data so that the device will always get the correct bytes, thus
15 * is useful for 8 and 16 bit devices. This is the mode that is supported
16 * below.
17 *
18 * AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000
19 * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
20 *
21 * AUG/25/2000 : addad support for 8, 16 and 32-bit Single-Address-Mode (K)2000
22 * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
23 *
24 * APR/18/2002 : added proper support for MCF5272 DMA controller.
25 * Arthur Shipkowski (art@videon-central.com)
26 */
27
28#include <asm/coldfire.h>
29#include <asm/mcfsim.h>
30#include <asm/mcfdma.h>
31
32/*
33 * Set number of channels of DMA on ColdFire for different implementations.
34 */
35#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
36 defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
37#define MAX_M68K_DMA_CHANNELS 4
38#elif defined(CONFIG_M5272)
39#define MAX_M68K_DMA_CHANNELS 1
40#elif defined(CONFIG_M532x)
41#define MAX_M68K_DMA_CHANNELS 0
3#else 42#else
4#include "dma_mm.h" 43#define MAX_M68K_DMA_CHANNELS 2
5#endif 44#endif
45
46extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS];
47extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
48
49#if !defined(CONFIG_M5272)
50#define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */
51#define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */
52#define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */
53#define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */
54
55/* I/O to memory, 8 bits, mode */
56#define DMA_MODE_READ 0
57/* memory to I/O, 8 bits, mode */
58#define DMA_MODE_WRITE 1
59/* I/O to memory, 16 bits, mode */
60#define DMA_MODE_READ_WORD 2
61/* memory to I/O, 16 bits, mode */
62#define DMA_MODE_WRITE_WORD 3
63/* I/O to memory, 32 bits, mode */
64#define DMA_MODE_READ_LONG 4
65/* memory to I/O, 32 bits, mode */
66#define DMA_MODE_WRITE_LONG 5
67/* I/O to memory, 8 bits, single-address-mode */
68#define DMA_MODE_READ_SINGLE 8
69/* memory to I/O, 8 bits, single-address-mode */
70#define DMA_MODE_WRITE_SINGLE 9
71/* I/O to memory, 16 bits, single-address-mode */
72#define DMA_MODE_READ_WORD_SINGLE 10
73/* memory to I/O, 16 bits, single-address-mode */
74#define DMA_MODE_WRITE_WORD_SINGLE 11
75/* I/O to memory, 32 bits, single-address-mode */
76#define DMA_MODE_READ_LONG_SINGLE 12
77/* memory to I/O, 32 bits, single-address-mode */
78#define DMA_MODE_WRITE_LONG_SINGLE 13
79
80#else /* CONFIG_M5272 is defined */
81
82/* Source static-address mode */
83#define DMA_MODE_SRC_SA_BIT 0x01
84/* Two bits to select between all four modes */
85#define DMA_MODE_SSIZE_MASK 0x06
86/* Offset to shift bits in */
87#define DMA_MODE_SSIZE_OFF 0x01
88/* Destination static-address mode */
89#define DMA_MODE_DES_SA_BIT 0x10
90/* Two bits to select between all four modes */
91#define DMA_MODE_DSIZE_MASK 0x60
92/* Offset to shift bits in */
93#define DMA_MODE_DSIZE_OFF 0x05
94/* Size modifiers */
95#define DMA_MODE_SIZE_LONG 0x00
96#define DMA_MODE_SIZE_BYTE 0x01
97#define DMA_MODE_SIZE_WORD 0x02
98#define DMA_MODE_SIZE_LINE 0x03
99
100/*
101 * Aliases to help speed quick ports; these may be suboptimal, however. They
102 * do not include the SINGLE mode modifiers since the MCF5272 does not have a
103 * mode where the device is in control of its addressing.
104 */
105
106/* I/O to memory, 8 bits, mode */
107#define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
108/* memory to I/O, 8 bits, mode */
109#define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
110/* I/O to memory, 16 bits, mode */
111#define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
112/* memory to I/O, 16 bits, mode */
113#define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
114/* I/O to memory, 32 bits, mode */
115#define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
116/* memory to I/O, 32 bits, mode */
117#define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
118
119#endif /* !defined(CONFIG_M5272) */
120
121#if !defined(CONFIG_M5272)
122/* enable/disable a specific DMA channel */
123static __inline__ void enable_dma(unsigned int dmanr)
124{
125 volatile unsigned short *dmawp;
126
127#ifdef DMA_DEBUG
128 printk("enable_dma(dmanr=%d)\n", dmanr);
129#endif
130
131 dmawp = (unsigned short *) dma_base_addr[dmanr];
132 dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT;
133}
134
135static __inline__ void disable_dma(unsigned int dmanr)
136{
137 volatile unsigned short *dmawp;
138 volatile unsigned char *dmapb;
139
140#ifdef DMA_DEBUG
141 printk("disable_dma(dmanr=%d)\n", dmanr);
142#endif
143
144 dmawp = (unsigned short *) dma_base_addr[dmanr];
145 dmapb = (unsigned char *) dma_base_addr[dmanr];
146
147 /* Turn off external requests, and stop any DMA in progress */
148 dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT;
149 dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE;
150}
151
152/*
153 * Clear the 'DMA Pointer Flip Flop'.
154 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
155 * Use this once to initialize the FF to a known state.
156 * After that, keep track of it. :-)
157 * --- In order to do that, the DMA routines below should ---
158 * --- only be used while interrupts are disabled! ---
159 *
160 * This is a NOP for ColdFire. Provide a stub for compatibility.
161 */
162static __inline__ void clear_dma_ff(unsigned int dmanr)
163{
164}
165
166/* set mode (above) for a specific DMA channel */
167static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
168{
169
170 volatile unsigned char *dmabp;
171 volatile unsigned short *dmawp;
172
173#ifdef DMA_DEBUG
174 printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
175#endif
176
177 dmabp = (unsigned char *) dma_base_addr[dmanr];
178 dmawp = (unsigned short *) dma_base_addr[dmanr];
179
180 /* Clear config errors */
181 dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE;
182
183 /* Set command register */
184 dmawp[MCFDMA_DCR] =
185 MCFDMA_DCR_INT | /* Enable completion irq */
186 MCFDMA_DCR_CS | /* Force one xfer per request */
187 MCFDMA_DCR_AA | /* Enable auto alignment */
188 /* single-address-mode */
189 ((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) |
190 /* sets s_rw (-> r/w) high if Memory to I/0 */
191 ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) |
192 /* Memory to I/O or I/O to Memory */
193 ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) |
194 /* 32 bit, 16 bit or 8 bit transfers */
195 ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD :
196 ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG :
197 MCFDMA_DCR_SSIZE_BYTE)) |
198 ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_DSIZE_WORD :
199 ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_DSIZE_LONG :
200 MCFDMA_DCR_DSIZE_BYTE));
201
202#ifdef DEBUG_DMA
203 printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__, __LINE__,
204 dmanr, (int) &dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR],
205 (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR]);
206#endif
207}
208
209/* Set transfer address for specific DMA channel */
210static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
211{
212 volatile unsigned short *dmawp;
213 volatile unsigned int *dmalp;
214
215#ifdef DMA_DEBUG
216 printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
217#endif
218
219 dmawp = (unsigned short *) dma_base_addr[dmanr];
220 dmalp = (unsigned int *) dma_base_addr[dmanr];
221
222 /* Determine which address registers are used for memory/device accesses */
223 if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) {
224 /* Source incrementing, must be memory */
225 dmalp[MCFDMA_SAR] = a;
226 /* Set dest address, must be device */
227 dmalp[MCFDMA_DAR] = dma_device_address[dmanr];
228 } else {
229 /* Destination incrementing, must be memory */
230 dmalp[MCFDMA_DAR] = a;
231 /* Set source address, must be device */
232 dmalp[MCFDMA_SAR] = dma_device_address[dmanr];
233 }
234
235#ifdef DEBUG_DMA
236 printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
237 __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR],
238 (int) &dmalp[MCFDMA_SAR], dmalp[MCFDMA_SAR],
239 (int) &dmalp[MCFDMA_DAR], dmalp[MCFDMA_DAR]);
240#endif
241}
242
243/*
244 * Specific for Coldfire - sets device address.
245 * Should be called after the mode set call, and before set DMA address.
246 */
247static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
248{
249#ifdef DMA_DEBUG
250 printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
251#endif
252
253 dma_device_address[dmanr] = a;
254}
255
256/*
257 * NOTE 2: "count" represents _bytes_.
258 */
259static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
260{
261 volatile unsigned short *dmawp;
262
263#ifdef DMA_DEBUG
264 printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
265#endif
266
267 dmawp = (unsigned short *) dma_base_addr[dmanr];
268 dmawp[MCFDMA_BCR] = (unsigned short)count;
269}
270
271/*
272 * Get DMA residue count. After a DMA transfer, this
273 * should return zero. Reading this while a DMA transfer is
274 * still in progress will return unpredictable results.
275 * Otherwise, it returns the number of _bytes_ left to transfer.
276 */
277static __inline__ int get_dma_residue(unsigned int dmanr)
278{
279 volatile unsigned short *dmawp;
280 unsigned short count;
281
282#ifdef DMA_DEBUG
283 printk("get_dma_residue(dmanr=%d)\n", dmanr);
284#endif
285
286 dmawp = (unsigned short *) dma_base_addr[dmanr];
287 count = dmawp[MCFDMA_BCR];
288 return((int) count);
289}
290#else /* CONFIG_M5272 is defined */
291
292/*
293 * The MCF5272 DMA controller is very different than the controller defined above
294 * in terms of register mapping. For instance, with the exception of the 16-bit
295 * interrupt register (IRQ#85, for reference), all of the registers are 32-bit.
296 *
297 * The big difference, however, is the lack of device-requested DMA. All modes
298 * are dual address transfer, and there is no 'device' setup or direction bit.
299 * You can DMA between a device and memory, between memory and memory, or even between
300 * two devices directly, with any combination of incrementing and non-incrementing
301 * addresses you choose. This puts a crimp in distinguishing between the 'device
302 * address' set up by set_dma_device_addr.
303 *
304 * Therefore, there are two options. One is to use set_dma_addr and set_dma_device_addr,
305 * which will act exactly as above in -- it will look to see if the source is set to
306 * autoincrement, and if so it will make the source use the set_dma_addr value and the
307 * destination the set_dma_device_addr value. Otherwise the source will be set to the
308 * set_dma_device_addr value and the destination will get the set_dma_addr value.
309 *
310 * The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions
311 * and make it explicit. Depending on what you're doing, one of these two should work
312 * for you, but don't mix them in the same transfer setup.
313 */
314
315/* enable/disable a specific DMA channel */
316static __inline__ void enable_dma(unsigned int dmanr)
317{
318 volatile unsigned int *dmalp;
319
320#ifdef DMA_DEBUG
321 printk("enable_dma(dmanr=%d)\n", dmanr);
322#endif
323
324 dmalp = (unsigned int *) dma_base_addr[dmanr];
325 dmalp[MCFDMA_DMR] |= MCFDMA_DMR_EN;
326}
327
328static __inline__ void disable_dma(unsigned int dmanr)
329{
330 volatile unsigned int *dmalp;
331
332#ifdef DMA_DEBUG
333 printk("disable_dma(dmanr=%d)\n", dmanr);
334#endif
335
336 dmalp = (unsigned int *) dma_base_addr[dmanr];
337
338 /* Turn off external requests, and stop any DMA in progress */
339 dmalp[MCFDMA_DMR] &= ~MCFDMA_DMR_EN;
340 dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
341}
342
343/*
344 * Clear the 'DMA Pointer Flip Flop'.
345 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
346 * Use this once to initialize the FF to a known state.
347 * After that, keep track of it. :-)
348 * --- In order to do that, the DMA routines below should ---
349 * --- only be used while interrupts are disabled! ---
350 *
351 * This is a NOP for ColdFire. Provide a stub for compatibility.
352 */
353static __inline__ void clear_dma_ff(unsigned int dmanr)
354{
355}
356
357/* set mode (above) for a specific DMA channel */
358static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
359{
360
361 volatile unsigned int *dmalp;
362 volatile unsigned short *dmawp;
363
364#ifdef DMA_DEBUG
365 printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
366#endif
367 dmalp = (unsigned int *) dma_base_addr[dmanr];
368 dmawp = (unsigned short *) dma_base_addr[dmanr];
369
370 /* Clear config errors */
371 dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
372
373 /* Set command register */
374 dmalp[MCFDMA_DMR] =
375 MCFDMA_DMR_RQM_DUAL | /* Mandatory Request Mode setting */
376 MCFDMA_DMR_DSTT_SD | /* Set up addressing types; set to supervisor-data. */
377 MCFDMA_DMR_SRCT_SD | /* Set up addressing types; set to supervisor-data. */
378 /* source static-address-mode */
379 ((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) |
380 /* dest static-address-mode */
381 ((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) |
382 /* burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272 */
383 (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) |
384 (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF);
385
386 dmawp[MCFDMA_DIR] |= MCFDMA_DIR_ASCEN; /* Enable completion interrupts */
387
388#ifdef DEBUG_DMA
389 printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__, __LINE__,
390 dmanr, (int) &dmalp[MCFDMA_DMR], dmabp[MCFDMA_DMR],
391 (int) &dmawp[MCFDMA_DIR], dmawp[MCFDMA_DIR]);
392#endif
393}
394
395/* Set transfer address for specific DMA channel */
396static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
397{
398 volatile unsigned int *dmalp;
399
400#ifdef DMA_DEBUG
401 printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
402#endif
403
404 dmalp = (unsigned int *) dma_base_addr[dmanr];
405
406 /* Determine which address registers are used for memory/device accesses */
407 if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) {
408 /* Source incrementing, must be memory */
409 dmalp[MCFDMA_DSAR] = a;
410 /* Set dest address, must be device */
411 dmalp[MCFDMA_DDAR] = dma_device_address[dmanr];
412 } else {
413 /* Destination incrementing, must be memory */
414 dmalp[MCFDMA_DDAR] = a;
415 /* Set source address, must be device */
416 dmalp[MCFDMA_DSAR] = dma_device_address[dmanr];
417 }
418
419#ifdef DEBUG_DMA
420 printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
421 __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DMR], dmawp[MCFDMA_DMR],
422 (int) &dmalp[MCFDMA_DSAR], dmalp[MCFDMA_DSAR],
423 (int) &dmalp[MCFDMA_DDAR], dmalp[MCFDMA_DDAR]);
424#endif
425}
426
427/*
428 * Specific for Coldfire - sets device address.
429 * Should be called after the mode set call, and before set DMA address.
430 */
431static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
432{
433#ifdef DMA_DEBUG
434 printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
435#endif
436
437 dma_device_address[dmanr] = a;
438}
439
440/*
441 * NOTE 2: "count" represents _bytes_.
442 *
443 * NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value.
444 */
445static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
446{
447 volatile unsigned int *dmalp;
448
449#ifdef DMA_DEBUG
450 printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
451#endif
452
453 dmalp = (unsigned int *) dma_base_addr[dmanr];
454 dmalp[MCFDMA_DBCR] = count;
455}
456
457/*
458 * Get DMA residue count. After a DMA transfer, this
459 * should return zero. Reading this while a DMA transfer is
460 * still in progress will return unpredictable results.
461 * Otherwise, it returns the number of _bytes_ left to transfer.
462 */
463static __inline__ int get_dma_residue(unsigned int dmanr)
464{
465 volatile unsigned int *dmalp;
466 unsigned int count;
467
468#ifdef DMA_DEBUG
469 printk("get_dma_residue(dmanr=%d)\n", dmanr);
470#endif
471
472 dmalp = (unsigned int *) dma_base_addr[dmanr];
473 count = dmalp[MCFDMA_DBCR];
474 return(count);
475}
476
477#endif /* !defined(CONFIG_M5272) */
478#endif /* CONFIG_COLDFIRE */
479
480/* it's useless on the m68k, but unfortunately needed by the new
481 bootmem allocator (but this should do it for this) */
482#define MAX_DMA_ADDRESS PAGE_OFFSET
483
484#define MAX_DMA_CHANNELS 8
485
486extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
487extern void free_dma(unsigned int dmanr); /* release it again */
488
489#define isa_dma_bridge_buggy (0)
490
491#endif /* _M68K_DMA_H */
diff --git a/arch/m68k/include/asm/dma_mm.h b/arch/m68k/include/asm/dma_mm.h
deleted file mode 100644
index 4240fbc946f8..000000000000
--- a/arch/m68k/include/asm/dma_mm.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef _M68K_DMA_H
2#define _M68K_DMA_H 1
3
4
5/* it's useless on the m68k, but unfortunately needed by the new
6 bootmem allocator (but this should do it for this) */
7#define MAX_DMA_ADDRESS PAGE_OFFSET
8
9#define MAX_DMA_CHANNELS 8
10
11extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
12extern void free_dma(unsigned int dmanr); /* release it again */
13
14#define isa_dma_bridge_buggy (0)
15
16#endif /* _M68K_DMA_H */
diff --git a/arch/m68k/include/asm/dma_no.h b/arch/m68k/include/asm/dma_no.h
deleted file mode 100644
index 939a02056217..000000000000
--- a/arch/m68k/include/asm/dma_no.h
+++ /dev/null
@@ -1,494 +0,0 @@
1#ifndef _M68K_DMA_H
2#define _M68K_DMA_H 1
3
4//#define DMA_DEBUG 1
5
6
7#ifdef CONFIG_COLDFIRE
8/*
9 * ColdFire DMA Model:
10 * ColdFire DMA supports two forms of DMA: Single and Dual address. Single
11 * address mode emits a source address, and expects that the device will either
12 * pick up the data (DMA READ) or source data (DMA WRITE). This implies that
13 * the device will place data on the correct byte(s) of the data bus, as the
14 * memory transactions are always 32 bits. This implies that only 32 bit
15 * devices will find single mode transfers useful. Dual address DMA mode
16 * performs two cycles: source read and destination write. ColdFire will
17 * align the data so that the device will always get the correct bytes, thus
18 * is useful for 8 and 16 bit devices. This is the mode that is supported
19 * below.
20 *
21 * AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000
22 * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
23 *
24 * AUG/25/2000 : addad support for 8, 16 and 32-bit Single-Address-Mode (K)2000
25 * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de)
26 *
27 * APR/18/2002 : added proper support for MCF5272 DMA controller.
28 * Arthur Shipkowski (art@videon-central.com)
29 */
30
31#include <asm/coldfire.h>
32#include <asm/mcfsim.h>
33#include <asm/mcfdma.h>
34
35/*
36 * Set number of channels of DMA on ColdFire for different implementations.
37 */
38#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \
39 defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x)
40#define MAX_M68K_DMA_CHANNELS 4
41#elif defined(CONFIG_M5272)
42#define MAX_M68K_DMA_CHANNELS 1
43#elif defined(CONFIG_M532x)
44#define MAX_M68K_DMA_CHANNELS 0
45#else
46#define MAX_M68K_DMA_CHANNELS 2
47#endif
48
49extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS];
50extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
51
52#if !defined(CONFIG_M5272)
53#define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */
54#define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */
55#define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */
56#define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */
57
58/* I/O to memory, 8 bits, mode */
59#define DMA_MODE_READ 0
60/* memory to I/O, 8 bits, mode */
61#define DMA_MODE_WRITE 1
62/* I/O to memory, 16 bits, mode */
63#define DMA_MODE_READ_WORD 2
64/* memory to I/O, 16 bits, mode */
65#define DMA_MODE_WRITE_WORD 3
66/* I/O to memory, 32 bits, mode */
67#define DMA_MODE_READ_LONG 4
68/* memory to I/O, 32 bits, mode */
69#define DMA_MODE_WRITE_LONG 5
70/* I/O to memory, 8 bits, single-address-mode */
71#define DMA_MODE_READ_SINGLE 8
72/* memory to I/O, 8 bits, single-address-mode */
73#define DMA_MODE_WRITE_SINGLE 9
74/* I/O to memory, 16 bits, single-address-mode */
75#define DMA_MODE_READ_WORD_SINGLE 10
76/* memory to I/O, 16 bits, single-address-mode */
77#define DMA_MODE_WRITE_WORD_SINGLE 11
78/* I/O to memory, 32 bits, single-address-mode */
79#define DMA_MODE_READ_LONG_SINGLE 12
80/* memory to I/O, 32 bits, single-address-mode */
81#define DMA_MODE_WRITE_LONG_SINGLE 13
82
83#else /* CONFIG_M5272 is defined */
84
85/* Source static-address mode */
86#define DMA_MODE_SRC_SA_BIT 0x01
87/* Two bits to select between all four modes */
88#define DMA_MODE_SSIZE_MASK 0x06
89/* Offset to shift bits in */
90#define DMA_MODE_SSIZE_OFF 0x01
91/* Destination static-address mode */
92#define DMA_MODE_DES_SA_BIT 0x10
93/* Two bits to select between all four modes */
94#define DMA_MODE_DSIZE_MASK 0x60
95/* Offset to shift bits in */
96#define DMA_MODE_DSIZE_OFF 0x05
97/* Size modifiers */
98#define DMA_MODE_SIZE_LONG 0x00
99#define DMA_MODE_SIZE_BYTE 0x01
100#define DMA_MODE_SIZE_WORD 0x02
101#define DMA_MODE_SIZE_LINE 0x03
102
103/*
104 * Aliases to help speed quick ports; these may be suboptimal, however. They
105 * do not include the SINGLE mode modifiers since the MCF5272 does not have a
106 * mode where the device is in control of its addressing.
107 */
108
109/* I/O to memory, 8 bits, mode */
110#define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
111/* memory to I/O, 8 bits, mode */
112#define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
113/* I/O to memory, 16 bits, mode */
114#define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
115/* memory to I/O, 16 bits, mode */
116#define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
117/* I/O to memory, 32 bits, mode */
118#define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT)
119/* memory to I/O, 32 bits, mode */
120#define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT)
121
122#endif /* !defined(CONFIG_M5272) */
123
124#if !defined(CONFIG_M5272)
125/* enable/disable a specific DMA channel */
126static __inline__ void enable_dma(unsigned int dmanr)
127{
128 volatile unsigned short *dmawp;
129
130#ifdef DMA_DEBUG
131 printk("enable_dma(dmanr=%d)\n", dmanr);
132#endif
133
134 dmawp = (unsigned short *) dma_base_addr[dmanr];
135 dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT;
136}
137
138static __inline__ void disable_dma(unsigned int dmanr)
139{
140 volatile unsigned short *dmawp;
141 volatile unsigned char *dmapb;
142
143#ifdef DMA_DEBUG
144 printk("disable_dma(dmanr=%d)\n", dmanr);
145#endif
146
147 dmawp = (unsigned short *) dma_base_addr[dmanr];
148 dmapb = (unsigned char *) dma_base_addr[dmanr];
149
150 /* Turn off external requests, and stop any DMA in progress */
151 dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT;
152 dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE;
153}
154
155/*
156 * Clear the 'DMA Pointer Flip Flop'.
157 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
158 * Use this once to initialize the FF to a known state.
159 * After that, keep track of it. :-)
160 * --- In order to do that, the DMA routines below should ---
161 * --- only be used while interrupts are disabled! ---
162 *
163 * This is a NOP for ColdFire. Provide a stub for compatibility.
164 */
165static __inline__ void clear_dma_ff(unsigned int dmanr)
166{
167}
168
169/* set mode (above) for a specific DMA channel */
170static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
171{
172
173 volatile unsigned char *dmabp;
174 volatile unsigned short *dmawp;
175
176#ifdef DMA_DEBUG
177 printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
178#endif
179
180 dmabp = (unsigned char *) dma_base_addr[dmanr];
181 dmawp = (unsigned short *) dma_base_addr[dmanr];
182
183 // Clear config errors
184 dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE;
185
186 // Set command register
187 dmawp[MCFDMA_DCR] =
188 MCFDMA_DCR_INT | // Enable completion irq
189 MCFDMA_DCR_CS | // Force one xfer per request
190 MCFDMA_DCR_AA | // Enable auto alignment
191 // single-address-mode
192 ((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) |
193 // sets s_rw (-> r/w) high if Memory to I/0
194 ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) |
195 // Memory to I/O or I/O to Memory
196 ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) |
197 // 32 bit, 16 bit or 8 bit transfers
198 ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD :
199 ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG :
200 MCFDMA_DCR_SSIZE_BYTE)) |
201 ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_DSIZE_WORD :
202 ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_DSIZE_LONG :
203 MCFDMA_DCR_DSIZE_BYTE));
204
205#ifdef DEBUG_DMA
206 printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__, __LINE__,
207 dmanr, (int) &dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR],
208 (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR]);
209#endif
210}
211
212/* Set transfer address for specific DMA channel */
213static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
214{
215 volatile unsigned short *dmawp;
216 volatile unsigned int *dmalp;
217
218#ifdef DMA_DEBUG
219 printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
220#endif
221
222 dmawp = (unsigned short *) dma_base_addr[dmanr];
223 dmalp = (unsigned int *) dma_base_addr[dmanr];
224
225 // Determine which address registers are used for memory/device accesses
226 if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) {
227 // Source incrementing, must be memory
228 dmalp[MCFDMA_SAR] = a;
229 // Set dest address, must be device
230 dmalp[MCFDMA_DAR] = dma_device_address[dmanr];
231 } else {
232 // Destination incrementing, must be memory
233 dmalp[MCFDMA_DAR] = a;
234 // Set source address, must be device
235 dmalp[MCFDMA_SAR] = dma_device_address[dmanr];
236 }
237
238#ifdef DEBUG_DMA
239 printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
240 __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR],
241 (int) &dmalp[MCFDMA_SAR], dmalp[MCFDMA_SAR],
242 (int) &dmalp[MCFDMA_DAR], dmalp[MCFDMA_DAR]);
243#endif
244}
245
246/*
247 * Specific for Coldfire - sets device address.
248 * Should be called after the mode set call, and before set DMA address.
249 */
250static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
251{
252#ifdef DMA_DEBUG
253 printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
254#endif
255
256 dma_device_address[dmanr] = a;
257}
258
259/*
260 * NOTE 2: "count" represents _bytes_.
261 */
262static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
263{
264 volatile unsigned short *dmawp;
265
266#ifdef DMA_DEBUG
267 printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
268#endif
269
270 dmawp = (unsigned short *) dma_base_addr[dmanr];
271 dmawp[MCFDMA_BCR] = (unsigned short)count;
272}
273
274/*
275 * Get DMA residue count. After a DMA transfer, this
276 * should return zero. Reading this while a DMA transfer is
277 * still in progress will return unpredictable results.
278 * Otherwise, it returns the number of _bytes_ left to transfer.
279 */
280static __inline__ int get_dma_residue(unsigned int dmanr)
281{
282 volatile unsigned short *dmawp;
283 unsigned short count;
284
285#ifdef DMA_DEBUG
286 printk("get_dma_residue(dmanr=%d)\n", dmanr);
287#endif
288
289 dmawp = (unsigned short *) dma_base_addr[dmanr];
290 count = dmawp[MCFDMA_BCR];
291 return((int) count);
292}
293#else /* CONFIG_M5272 is defined */
294
295/*
296 * The MCF5272 DMA controller is very different than the controller defined above
297 * in terms of register mapping. For instance, with the exception of the 16-bit
298 * interrupt register (IRQ#85, for reference), all of the registers are 32-bit.
299 *
300 * The big difference, however, is the lack of device-requested DMA. All modes
301 * are dual address transfer, and there is no 'device' setup or direction bit.
302 * You can DMA between a device and memory, between memory and memory, or even between
303 * two devices directly, with any combination of incrementing and non-incrementing
304 * addresses you choose. This puts a crimp in distinguishing between the 'device
305 * address' set up by set_dma_device_addr.
306 *
307 * Therefore, there are two options. One is to use set_dma_addr and set_dma_device_addr,
308 * which will act exactly as above in -- it will look to see if the source is set to
309 * autoincrement, and if so it will make the source use the set_dma_addr value and the
310 * destination the set_dma_device_addr value. Otherwise the source will be set to the
311 * set_dma_device_addr value and the destination will get the set_dma_addr value.
312 *
313 * The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions
314 * and make it explicit. Depending on what you're doing, one of these two should work
315 * for you, but don't mix them in the same transfer setup.
316 */
317
318/* enable/disable a specific DMA channel */
319static __inline__ void enable_dma(unsigned int dmanr)
320{
321 volatile unsigned int *dmalp;
322
323#ifdef DMA_DEBUG
324 printk("enable_dma(dmanr=%d)\n", dmanr);
325#endif
326
327 dmalp = (unsigned int *) dma_base_addr[dmanr];
328 dmalp[MCFDMA_DMR] |= MCFDMA_DMR_EN;
329}
330
331static __inline__ void disable_dma(unsigned int dmanr)
332{
333 volatile unsigned int *dmalp;
334
335#ifdef DMA_DEBUG
336 printk("disable_dma(dmanr=%d)\n", dmanr);
337#endif
338
339 dmalp = (unsigned int *) dma_base_addr[dmanr];
340
341 /* Turn off external requests, and stop any DMA in progress */
342 dmalp[MCFDMA_DMR] &= ~MCFDMA_DMR_EN;
343 dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
344}
345
346/*
347 * Clear the 'DMA Pointer Flip Flop'.
348 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
349 * Use this once to initialize the FF to a known state.
350 * After that, keep track of it. :-)
351 * --- In order to do that, the DMA routines below should ---
352 * --- only be used while interrupts are disabled! ---
353 *
354 * This is a NOP for ColdFire. Provide a stub for compatibility.
355 */
356static __inline__ void clear_dma_ff(unsigned int dmanr)
357{
358}
359
360/* set mode (above) for a specific DMA channel */
361static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
362{
363
364 volatile unsigned int *dmalp;
365 volatile unsigned short *dmawp;
366
367#ifdef DMA_DEBUG
368 printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode);
369#endif
370 dmalp = (unsigned int *) dma_base_addr[dmanr];
371 dmawp = (unsigned short *) dma_base_addr[dmanr];
372
373 // Clear config errors
374 dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET;
375
376 // Set command register
377 dmalp[MCFDMA_DMR] =
378 MCFDMA_DMR_RQM_DUAL | // Mandatory Request Mode setting
379 MCFDMA_DMR_DSTT_SD | // Set up addressing types; set to supervisor-data.
380 MCFDMA_DMR_SRCT_SD | // Set up addressing types; set to supervisor-data.
381 // source static-address-mode
382 ((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) |
383 // dest static-address-mode
384 ((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) |
385 // burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272
386 (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) |
387 (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF);
388
389 dmawp[MCFDMA_DIR] |= MCFDMA_DIR_ASCEN; /* Enable completion interrupts */
390
391#ifdef DEBUG_DMA
392 printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__, __LINE__,
393 dmanr, (int) &dmalp[MCFDMA_DMR], dmabp[MCFDMA_DMR],
394 (int) &dmawp[MCFDMA_DIR], dmawp[MCFDMA_DIR]);
395#endif
396}
397
398/* Set transfer address for specific DMA channel */
399static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
400{
401 volatile unsigned int *dmalp;
402
403#ifdef DMA_DEBUG
404 printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a);
405#endif
406
407 dmalp = (unsigned int *) dma_base_addr[dmanr];
408
409 // Determine which address registers are used for memory/device accesses
410 if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) {
411 // Source incrementing, must be memory
412 dmalp[MCFDMA_DSAR] = a;
413 // Set dest address, must be device
414 dmalp[MCFDMA_DDAR] = dma_device_address[dmanr];
415 } else {
416 // Destination incrementing, must be memory
417 dmalp[MCFDMA_DDAR] = a;
418 // Set source address, must be device
419 dmalp[MCFDMA_DSAR] = dma_device_address[dmanr];
420 }
421
422#ifdef DEBUG_DMA
423 printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n",
424 __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DMR], dmawp[MCFDMA_DMR],
425 (int) &dmalp[MCFDMA_DSAR], dmalp[MCFDMA_DSAR],
426 (int) &dmalp[MCFDMA_DDAR], dmalp[MCFDMA_DDAR]);
427#endif
428}
429
430/*
431 * Specific for Coldfire - sets device address.
432 * Should be called after the mode set call, and before set DMA address.
433 */
434static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a)
435{
436#ifdef DMA_DEBUG
437 printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a);
438#endif
439
440 dma_device_address[dmanr] = a;
441}
442
443/*
444 * NOTE 2: "count" represents _bytes_.
445 *
446 * NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value.
447 */
448static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
449{
450 volatile unsigned int *dmalp;
451
452#ifdef DMA_DEBUG
453 printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count);
454#endif
455
456 dmalp = (unsigned int *) dma_base_addr[dmanr];
457 dmalp[MCFDMA_DBCR] = count;
458}
459
460/*
461 * Get DMA residue count. After a DMA transfer, this
462 * should return zero. Reading this while a DMA transfer is
463 * still in progress will return unpredictable results.
464 * Otherwise, it returns the number of _bytes_ left to transfer.
465 */
466static __inline__ int get_dma_residue(unsigned int dmanr)
467{
468 volatile unsigned int *dmalp;
469 unsigned int count;
470
471#ifdef DMA_DEBUG
472 printk("get_dma_residue(dmanr=%d)\n", dmanr);
473#endif
474
475 dmalp = (unsigned int *) dma_base_addr[dmanr];
476 count = dmalp[MCFDMA_DBCR];
477 return(count);
478}
479
480#endif /* !defined(CONFIG_M5272) */
481#endif /* CONFIG_COLDFIRE */
482
483#define MAX_DMA_CHANNELS 8
484
485/* Don't define MAX_DMA_ADDRESS; it's useless on the m68k/coldfire and any
486 occurrence should be flagged as an error. */
487/* under 2.4 it is actually needed by the new bootmem allocator */
488#define MAX_DMA_ADDRESS PAGE_OFFSET
489
490/* These are in kernel/dma.c: */
491extern int request_dma(unsigned int dmanr, const char *device_id); /* reserve a DMA channel */
492extern void free_dma(unsigned int dmanr); /* release it again */
493
494#endif /* _M68K_DMA_H */
diff --git a/arch/m68k/include/asm/elia.h b/arch/m68k/include/asm/elia.h
deleted file mode 100644
index e037d4e2de33..000000000000
--- a/arch/m68k/include/asm/elia.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/****************************************************************************/
2
3/*
4 * elia.h -- Lineo (formerly Moreton Bay) eLIA platform support.
5 *
6 * (C) Copyright 1999-2000, Moreton Bay (www.moreton.com.au)
7 * (C) Copyright 1999-2000, Lineo (www.lineo.com)
8 */
9
10/****************************************************************************/
11#ifndef elia_h
12#define elia_h
13/****************************************************************************/
14
15#include <asm/coldfire.h>
16
17#ifdef CONFIG_eLIA
18
19/*
20 * The serial port DTR and DCD lines are also on the Parallel I/O
21 * as well, so define those too.
22 */
23
24#define eLIA_DCD1 0x0001
25#define eLIA_DCD0 0x0002
26#define eLIA_DTR1 0x0004
27#define eLIA_DTR0 0x0008
28
29#define eLIA_PCIRESET 0x0020
30
31/*
32 * Kernel macros to set and unset the LEDs.
33 */
34#ifndef __ASSEMBLY__
35extern unsigned short ppdata;
36#endif /* __ASSEMBLY__ */
37
38#endif /* CONFIG_eLIA */
39
40/****************************************************************************/
41#endif /* elia_h */
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
new file mode 100644
index 000000000000..283214dc65a7
--- /dev/null
+++ b/arch/m68k/include/asm/gpio.h
@@ -0,0 +1,238 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#ifndef coldfire_gpio_h
17#define coldfire_gpio_h
18
19#include <linux/io.h>
20#include <asm-generic/gpio.h>
21#include <asm/coldfire.h>
22#include <asm/mcfsim.h>
23
24/*
25 * The Freescale Coldfire family is quite varied in how they implement GPIO.
26 * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
27 * only one port, others have multiple ports; some have a single data latch
28 * for both input and output, others have a separate pin data register to read
29 * input; some require a read-modify-write access to change an output, others
30 * have set and clear registers for some of the outputs; Some have all the
31 * GPIOs in a single control area, others have some GPIOs implemented in
32 * different modules.
33 *
34 * This implementation attempts accomodate the differences while presenting
35 * a generic interface that will optimize to as few instructions as possible.
36 */
37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
38 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
39 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
40
41/* These parts have GPIO organized by 8 bit ports */
42
43#define MCFGPIO_PORTTYPE u8
44#define MCFGPIO_PORTSIZE 8
45#define mcfgpio_read(port) __raw_readb(port)
46#define mcfgpio_write(data, port) __raw_writeb(data, port)
47
48#elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
49
50/* These parts have GPIO organized by 16 bit ports */
51
52#define MCFGPIO_PORTTYPE u16
53#define MCFGPIO_PORTSIZE 16
54#define mcfgpio_read(port) __raw_readw(port)
55#define mcfgpio_write(data, port) __raw_writew(data, port)
56
57#elif defined(CONFIG_M5249)
58
59/* These parts have GPIO organized by 32 bit ports */
60
61#define MCFGPIO_PORTTYPE u32
62#define MCFGPIO_PORTSIZE 32
63#define mcfgpio_read(port) __raw_readl(port)
64#define mcfgpio_write(data, port) __raw_writel(data, port)
65
66#endif
67
68#define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
69#define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
70
71#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
72 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
73/*
74 * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
75 * read-modify-write to change an output and a GPIO module which has separate
76 * set/clr registers to directly change outputs with a single write access.
77 */
78#if defined(CONFIG_M528x)
79/*
80 * The 528x also has GPIOs in other modules (GPT, QADC) which use
81 * read-modify-write as well as those controlled by the EPORT and GPIO modules.
82 */
83#define MCFGPIO_SCR_START 40
84#else
85#define MCFGPIO_SCR_START 8
86#endif
87
88#define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
89 mcfgpio_port(gpio - MCFGPIO_SCR_START))
90
91#define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
92 mcfgpio_port(gpio - MCFGPIO_SCR_START))
93#else
94
95#define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
96/* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
97#define MCFGPIO_SETR_PORT(gpio) 0
98#define MCFGPIO_CLRR_PORT(gpio) 0
99
100#endif
101/*
102 * Coldfire specific helper functions
103 */
104
105/* return the port pin data register for a gpio */
106static inline u32 __mcf_gpio_ppdr(unsigned gpio)
107{
108#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
109 defined(CONFIG_M5307) || defined(CONFIG_M5407)
110 return MCFSIM_PADAT;
111#elif defined(CONFIG_M5272)
112 if (gpio < 16)
113 return MCFSIM_PADAT;
114 else if (gpio < 32)
115 return MCFSIM_PBDAT;
116 else
117 return MCFSIM_PCDAT;
118#elif defined(CONFIG_M5249)
119 if (gpio < 32)
120 return MCFSIM2_GPIOREAD;
121 else
122 return MCFSIM2_GPIO1READ;
123#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
124 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
125 if (gpio < 8)
126 return MCFEPORT_EPPDR;
127#if defined(CONFIG_M528x)
128 else if (gpio < 16)
129 return MCFGPTA_GPTPORT;
130 else if (gpio < 24)
131 return MCFGPTB_GPTPORT;
132 else if (gpio < 32)
133 return MCFQADC_PORTQA;
134 else if (gpio < 40)
135 return MCFQADC_PORTQB;
136#endif
137 else
138 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
139#endif
140}
141
142/* return the port output data register for a gpio */
143static inline u32 __mcf_gpio_podr(unsigned gpio)
144{
145#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
146 defined(CONFIG_M5307) || defined(CONFIG_M5407)
147 return MCFSIM_PADAT;
148#elif defined(CONFIG_M5272)
149 if (gpio < 16)
150 return MCFSIM_PADAT;
151 else if (gpio < 32)
152 return MCFSIM_PBDAT;
153 else
154 return MCFSIM_PCDAT;
155#elif defined(CONFIG_M5249)
156 if (gpio < 32)
157 return MCFSIM2_GPIOWRITE;
158 else
159 return MCFSIM2_GPIO1WRITE;
160#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
161 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x)
162 if (gpio < 8)
163 return MCFEPORT_EPDR;
164#if defined(CONFIG_M528x)
165 else if (gpio < 16)
166 return MCFGPTA_GPTPORT;
167 else if (gpio < 24)
168 return MCFGPTB_GPTPORT;
169 else if (gpio < 32)
170 return MCFQADC_PORTQA;
171 else if (gpio < 40)
172 return MCFQADC_PORTQB;
173#endif
174 else
175 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
176#endif
177}
178
179/*
180 * The Generic GPIO functions
181 *
182 * If the gpio is a compile time constant and is one of the Coldfire gpios,
183 * use the inline version, otherwise dispatch thru gpiolib.
184 */
185
186static inline int gpio_get_value(unsigned gpio)
187{
188 if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX)
189 return mcfgpio_read(__mcf_gpio_ppdr(gpio)) & mcfgpio_bit(gpio);
190 else
191 return __gpio_get_value(gpio);
192}
193
194static inline void gpio_set_value(unsigned gpio, int value)
195{
196 if (__builtin_constant_p(gpio) && gpio < MCFGPIO_PIN_MAX) {
197 if (gpio < MCFGPIO_SCR_START) {
198 unsigned long flags;
199 MCFGPIO_PORTTYPE data;
200
201 local_irq_save(flags);
202 data = mcfgpio_read(__mcf_gpio_podr(gpio));
203 if (value)
204 data |= mcfgpio_bit(gpio);
205 else
206 data &= ~mcfgpio_bit(gpio);
207 mcfgpio_write(data, __mcf_gpio_podr(gpio));
208 local_irq_restore(flags);
209 } else {
210 if (value)
211 mcfgpio_write(mcfgpio_bit(gpio),
212 MCFGPIO_SETR_PORT(gpio));
213 else
214 mcfgpio_write(~mcfgpio_bit(gpio),
215 MCFGPIO_CLRR_PORT(gpio));
216 }
217 } else
218 __gpio_set_value(gpio, value);
219}
220
221static inline int gpio_to_irq(unsigned gpio)
222{
223 return (gpio < MCFGPIO_IRQ_MAX) ? gpio + MCFGPIO_IRQ_VECBASE : -EINVAL;
224}
225
226static inline int irq_to_gpio(unsigned irq)
227{
228 return (irq >= MCFGPIO_IRQ_VECBASE &&
229 irq < (MCFGPIO_IRQ_VECBASE + MCFGPIO_IRQ_MAX)) ?
230 irq - MCFGPIO_IRQ_VECBASE : -ENXIO;
231}
232
233static inline int gpio_cansleep(unsigned gpio)
234{
235 return gpio < MCFGPIO_PIN_MAX ? 0 : __gpio_cansleep(gpio);
236}
237
238#endif
diff --git a/arch/m68k/include/asm/hardirq_no.h b/arch/m68k/include/asm/hardirq_no.h
index bfad28149a49..b44b14be87d9 100644
--- a/arch/m68k/include/asm/hardirq_no.h
+++ b/arch/m68k/include/asm/hardirq_no.h
@@ -1,16 +1,8 @@
1#ifndef __M68K_HARDIRQ_H 1#ifndef __M68K_HARDIRQ_H
2#define __M68K_HARDIRQ_H 2#define __M68K_HARDIRQ_H
3 3
4#include <linux/cache.h>
5#include <linux/threads.h>
6#include <asm/irq.h> 4#include <asm/irq.h>
7 5
8typedef struct {
9 unsigned int __softirq_pending;
10} ____cacheline_aligned irq_cpustat_t;
11
12#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
13
14#define HARDIRQ_BITS 8 6#define HARDIRQ_BITS 8
15 7
16/* 8/*
@@ -22,6 +14,6 @@ typedef struct {
22# error HARDIRQ_BITS is too low! 14# error HARDIRQ_BITS is too low!
23#endif 15#endif
24 16
25void ack_bad_irq(unsigned int irq); 17#include <asm-generic/hardirq.h>
26 18
27#endif /* __M68K_HARDIRQ_H */ 19#endif /* __M68K_HARDIRQ_H */
diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h
index 6adef1ee2082..7f57436ec18f 100644
--- a/arch/m68k/include/asm/io_no.h
+++ b/arch/m68k/include/asm/io_no.h
@@ -134,7 +134,7 @@ static inline void io_insl(unsigned int addr, void *buf, int len)
134#define insw(a,b,l) io_insw(a,b,l) 134#define insw(a,b,l) io_insw(a,b,l)
135#define insl(a,b,l) io_insl(a,b,l) 135#define insl(a,b,l) io_insl(a,b,l)
136 136
137#define IO_SPACE_LIMIT 0xffff 137#define IO_SPACE_LIMIT 0xffffffff
138 138
139 139
140/* Values for nocacheflag and cmode */ 140/* Values for nocacheflag and cmode */
diff --git a/arch/m68k/include/asm/irq.h b/arch/m68k/include/asm/irq.h
index d031416595b2..907eff1edd2f 100644
--- a/arch/m68k/include/asm/irq.h
+++ b/arch/m68k/include/asm/irq.h
@@ -1,5 +1,134 @@
1#ifdef __uClinux__ 1#ifndef _M68K_IRQ_H_
2#include "irq_no.h" 2#define _M68K_IRQ_H_
3
4/*
5 * This should be the same as the max(NUM_X_SOURCES) for all the
6 * different m68k hosts compiled into the kernel.
7 * Currently the Atari has 72 and the Amiga 24, but if both are
8 * supported in the kernel it is better to make room for 72.
9 */
10#if defined(CONFIG_COLDFIRE)
11#define NR_IRQS 256
12#elif defined(CONFIG_VME) || defined(CONFIG_SUN3) || defined(CONFIG_SUN3X)
13#define NR_IRQS 200
14#elif defined(CONFIG_ATARI) || defined(CONFIG_MAC)
15#define NR_IRQS 72
16#elif defined(CONFIG_Q40)
17#define NR_IRQS 43
18#elif defined(CONFIG_AMIGA) || !defined(CONFIG_MMU)
19#define NR_IRQS 32
20#elif defined(CONFIG_APOLLO)
21#define NR_IRQS 24
22#elif defined(CONFIG_HP300)
23#define NR_IRQS 8
3#else 24#else
4#include "irq_mm.h" 25#define NR_IRQS 0
5#endif 26#endif
27
28#ifdef CONFIG_MMU
29
30#include <linux/linkage.h>
31#include <linux/hardirq.h>
32#include <linux/irqreturn.h>
33#include <linux/spinlock_types.h>
34
35/*
36 * The hardirq mask has to be large enough to have
37 * space for potentially all IRQ sources in the system
38 * nesting on a single CPU:
39 */
40#if (1 << HARDIRQ_BITS) < NR_IRQS
41# error HARDIRQ_BITS is too low!
42#endif
43
44/*
45 * Interrupt source definitions
46 * General interrupt sources are the level 1-7.
47 * Adding an interrupt service routine for one of these sources
48 * results in the addition of that routine to a chain of routines.
49 * Each one is called in succession. Each individual interrupt
50 * service routine should determine if the device associated with
51 * that routine requires service.
52 */
53
54#define IRQ_SPURIOUS 0
55
56#define IRQ_AUTO_1 1 /* level 1 interrupt */
57#define IRQ_AUTO_2 2 /* level 2 interrupt */
58#define IRQ_AUTO_3 3 /* level 3 interrupt */
59#define IRQ_AUTO_4 4 /* level 4 interrupt */
60#define IRQ_AUTO_5 5 /* level 5 interrupt */
61#define IRQ_AUTO_6 6 /* level 6 interrupt */
62#define IRQ_AUTO_7 7 /* level 7 interrupt (non-maskable) */
63
64#define IRQ_USER 8
65
66extern unsigned int irq_canonicalize(unsigned int irq);
67
68struct pt_regs;
69
70/*
71 * various flags for request_irq() - the Amiga now uses the standard
72 * mechanism like all other architectures - IRQF_DISABLED and
73 * IRQF_SHARED are your friends.
74 */
75#ifndef MACH_AMIGA_ONLY
76#define IRQ_FLG_LOCK (0x0001) /* handler is not replaceable */
77#define IRQ_FLG_REPLACE (0x0002) /* replace existing handler */
78#define IRQ_FLG_FAST (0x0004)
79#define IRQ_FLG_SLOW (0x0008)
80#define IRQ_FLG_STD (0x8000) /* internally used */
81#endif
82
83/*
84 * This structure is used to chain together the ISRs for a particular
85 * interrupt source (if it supports chaining).
86 */
87typedef struct irq_node {
88 irqreturn_t (*handler)(int, void *);
89 void *dev_id;
90 struct irq_node *next;
91 unsigned long flags;
92 const char *devname;
93} irq_node_t;
94
95/*
96 * This structure has only 4 elements for speed reasons
97 */
98struct irq_handler {
99 int (*handler)(int, void *);
100 unsigned long flags;
101 void *dev_id;
102 const char *devname;
103};
104
105struct irq_controller {
106 const char *name;
107 spinlock_t lock;
108 int (*startup)(unsigned int irq);
109 void (*shutdown)(unsigned int irq);
110 void (*enable)(unsigned int irq);
111 void (*disable)(unsigned int irq);
112};
113
114extern int m68k_irq_startup(unsigned int);
115extern void m68k_irq_shutdown(unsigned int);
116
117/*
118 * This function returns a new irq_node_t
119 */
120extern irq_node_t *new_irq_node(void);
121
122extern void m68k_setup_auto_interrupt(void (*handler)(unsigned int, struct pt_regs *));
123extern void m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt,
124 void (*handler)(unsigned int, struct pt_regs *));
125extern void m68k_setup_irq_controller(struct irq_controller *, unsigned int, unsigned int);
126
127asmlinkage void m68k_handle_int(unsigned int);
128asmlinkage void __m68k_handle_int(unsigned int, struct pt_regs *);
129
130#else
131#define irq_canonicalize(irq) (irq)
132#endif /* CONFIG_MMU */
133
134#endif /* _M68K_IRQ_H_ */
diff --git a/arch/m68k/include/asm/irq_mm.h b/arch/m68k/include/asm/irq_mm.h
deleted file mode 100644
index 0cab42cad79e..000000000000
--- a/arch/m68k/include/asm/irq_mm.h
+++ /dev/null
@@ -1,126 +0,0 @@
1#ifndef _M68K_IRQ_H_
2#define _M68K_IRQ_H_
3
4#include <linux/linkage.h>
5#include <linux/hardirq.h>
6#include <linux/irqreturn.h>
7#include <linux/spinlock_types.h>
8
9/*
10 * This should be the same as the max(NUM_X_SOURCES) for all the
11 * different m68k hosts compiled into the kernel.
12 * Currently the Atari has 72 and the Amiga 24, but if both are
13 * supported in the kernel it is better to make room for 72.
14 */
15#if defined(CONFIG_VME) || defined(CONFIG_SUN3) || defined(CONFIG_SUN3X)
16#define NR_IRQS 200
17#elif defined(CONFIG_ATARI) || defined(CONFIG_MAC)
18#define NR_IRQS 72
19#elif defined(CONFIG_Q40)
20#define NR_IRQS 43
21#elif defined(CONFIG_AMIGA)
22#define NR_IRQS 32
23#elif defined(CONFIG_APOLLO)
24#define NR_IRQS 24
25#elif defined(CONFIG_HP300)
26#define NR_IRQS 8
27#else
28#define NR_IRQS 0
29#endif
30
31/*
32 * The hardirq mask has to be large enough to have
33 * space for potentially all IRQ sources in the system
34 * nesting on a single CPU:
35 */
36#if (1 << HARDIRQ_BITS) < NR_IRQS
37# error HARDIRQ_BITS is too low!
38#endif
39
40/*
41 * Interrupt source definitions
42 * General interrupt sources are the level 1-7.
43 * Adding an interrupt service routine for one of these sources
44 * results in the addition of that routine to a chain of routines.
45 * Each one is called in succession. Each individual interrupt
46 * service routine should determine if the device associated with
47 * that routine requires service.
48 */
49
50#define IRQ_SPURIOUS 0
51
52#define IRQ_AUTO_1 1 /* level 1 interrupt */
53#define IRQ_AUTO_2 2 /* level 2 interrupt */
54#define IRQ_AUTO_3 3 /* level 3 interrupt */
55#define IRQ_AUTO_4 4 /* level 4 interrupt */
56#define IRQ_AUTO_5 5 /* level 5 interrupt */
57#define IRQ_AUTO_6 6 /* level 6 interrupt */
58#define IRQ_AUTO_7 7 /* level 7 interrupt (non-maskable) */
59
60#define IRQ_USER 8
61
62extern unsigned int irq_canonicalize(unsigned int irq);
63
64struct pt_regs;
65
66/*
67 * various flags for request_irq() - the Amiga now uses the standard
68 * mechanism like all other architectures - IRQF_DISABLED and
69 * IRQF_SHARED are your friends.
70 */
71#ifndef MACH_AMIGA_ONLY
72#define IRQ_FLG_LOCK (0x0001) /* handler is not replaceable */
73#define IRQ_FLG_REPLACE (0x0002) /* replace existing handler */
74#define IRQ_FLG_FAST (0x0004)
75#define IRQ_FLG_SLOW (0x0008)
76#define IRQ_FLG_STD (0x8000) /* internally used */
77#endif
78
79/*
80 * This structure is used to chain together the ISRs for a particular
81 * interrupt source (if it supports chaining).
82 */
83typedef struct irq_node {
84 irqreturn_t (*handler)(int, void *);
85 void *dev_id;
86 struct irq_node *next;
87 unsigned long flags;
88 const char *devname;
89} irq_node_t;
90
91/*
92 * This structure has only 4 elements for speed reasons
93 */
94struct irq_handler {
95 int (*handler)(int, void *);
96 unsigned long flags;
97 void *dev_id;
98 const char *devname;
99};
100
101struct irq_controller {
102 const char *name;
103 spinlock_t lock;
104 int (*startup)(unsigned int irq);
105 void (*shutdown)(unsigned int irq);
106 void (*enable)(unsigned int irq);
107 void (*disable)(unsigned int irq);
108};
109
110extern int m68k_irq_startup(unsigned int);
111extern void m68k_irq_shutdown(unsigned int);
112
113/*
114 * This function returns a new irq_node_t
115 */
116extern irq_node_t *new_irq_node(void);
117
118extern void m68k_setup_auto_interrupt(void (*handler)(unsigned int, struct pt_regs *));
119extern void m68k_setup_user_interrupt(unsigned int vec, unsigned int cnt,
120 void (*handler)(unsigned int, struct pt_regs *));
121extern void m68k_setup_irq_controller(struct irq_controller *, unsigned int, unsigned int);
122
123asmlinkage void m68k_handle_int(unsigned int);
124asmlinkage void __m68k_handle_int(unsigned int, struct pt_regs *);
125
126#endif /* _M68K_IRQ_H_ */
diff --git a/arch/m68k/include/asm/irq_no.h b/arch/m68k/include/asm/irq_no.h
deleted file mode 100644
index 9373c31ac87d..000000000000
--- a/arch/m68k/include/asm/irq_no.h
+++ /dev/null
@@ -1,26 +0,0 @@
1#ifndef _M68KNOMMU_IRQ_H_
2#define _M68KNOMMU_IRQ_H_
3
4#ifdef CONFIG_COLDFIRE
5/*
6 * On the ColdFire we keep track of all vectors. That way drivers
7 * can register whatever vector number they wish, and we can deal
8 * with it.
9 */
10#define SYS_IRQS 256
11#define NR_IRQS SYS_IRQS
12
13#else
14
15/*
16 * # of m68k interrupts
17 */
18#define SYS_IRQS 8
19#define NR_IRQS (24 + SYS_IRQS)
20
21#endif /* CONFIG_COLDFIRE */
22
23
24#define irq_canonicalize(irq) (irq)
25
26#endif /* _M68KNOMMU_IRQ_H_ */
diff --git a/arch/m68k/include/asm/m5206sim.h b/arch/m68k/include/asm/m5206sim.h
index 7e3594dea88b..9c384e294af9 100644
--- a/arch/m68k/include/asm/m5206sim.h
+++ b/arch/m68k/include/asm/m5206sim.h
@@ -85,8 +85,21 @@
85#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */ 85#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */
86#endif 86#endif
87 87
88#define MCFSIM_PADDR 0x1c5 /* Parallel Direction (r/w) */ 88#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
89#define MCFSIM_PADAT 0x1c9 /* Parallel Port Value (r/w) */ 89#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
90
91/*
92 * Define system peripheral IRQ usage.
93 */
94#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
95#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
96
97/*
98 * Generic GPIO
99 */
100#define MCFGPIO_PIN_MAX 8
101#define MCFGPIO_IRQ_VECBASE -1
102#define MCFGPIO_IRQ_MAX -1
90 103
91/* 104/*
92 * Some symbol defines for the Parallel Port Pin Assignment Register 105 * Some symbol defines for the Parallel Port Pin Assignment Register
@@ -111,21 +124,5 @@
111#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */ 124#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
112#endif 125#endif
113 126
114#if defined(CONFIG_M5206e)
115#define MCFSIM_IMR_MASKALL 0xfffe /* All SIM intr sources */
116#endif
117
118/*
119 * Macro to get and set IMR register. It is 16 bits on the 5206.
120 */
121#define mcf_getimr() \
122 *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR))
123
124#define mcf_setimr(imr) \
125 *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR)) = (imr)
126
127#define mcf_getipr() \
128 *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IPR))
129
130/****************************************************************************/ 127/****************************************************************************/
131#endif /* m5206sim_h */ 128#endif /* m5206sim_h */
diff --git a/arch/m68k/include/asm/m520xsim.h b/arch/m68k/include/asm/m520xsim.h
index 83bbcfd6e8f2..ed2b69b96805 100644
--- a/arch/m68k/include/asm/m520xsim.h
+++ b/arch/m68k/include/asm/m520xsim.h
@@ -11,9 +11,8 @@
11#define m520xsim_h 11#define m520xsim_h
12/****************************************************************************/ 12/****************************************************************************/
13 13
14
15/* 14/*
16 * Define the 5282 SIM register set addresses. 15 * Define the 520x SIM register set addresses.
17 */ 16 */
18#define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */ 17#define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */
19#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ 18#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
@@ -22,8 +21,22 @@
22#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ 21#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
23#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ 22#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
24#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ 23#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
24#define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */
25#define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */
25#define MCFINTC_ICR0 0x40 /* Base ICR register */ 26#define MCFINTC_ICR0 0x40 /* Base ICR register */
26 27
28/*
29 * The common interrupt controller code just wants to know the absolute
30 * address to the SIMR and CIMR registers (not offsets into IPSBAR).
31 * The 520x family only has a single INTC unit.
32 */
33#define MCFINTC0_SIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_SIMR)
34#define MCFINTC0_CIMR (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_CIMR)
35#define MCFINTC0_ICR0 (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0)
36#define MCFINTC1_SIMR (0)
37#define MCFINTC1_CIMR (0)
38#define MCFINTC1_ICR0 (0)
39
27#define MCFINT_VECBASE 64 40#define MCFINT_VECBASE 64
28#define MCFINT_UART0 26 /* Interrupt number for UART0 */ 41#define MCFINT_UART0 26 /* Interrupt number for UART0 */
29#define MCFINT_UART1 27 /* Interrupt number for UART1 */ 42#define MCFINT_UART1 27 /* Interrupt number for UART1 */
@@ -41,6 +54,62 @@
41#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ 54#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */
42#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ 55#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */
43 56
57#define MCFEPORT_EPDDR 0xFC088002
58#define MCFEPORT_EPDR 0xFC088004
59#define MCFEPORT_EPPDR 0xFC088005
60
61#define MCFGPIO_PODR_BUSCTL 0xFC0A4000
62#define MCFGPIO_PODR_BE 0xFC0A4001
63#define MCFGPIO_PODR_CS 0xFC0A4002
64#define MCFGPIO_PODR_FECI2C 0xFC0A4003
65#define MCFGPIO_PODR_QSPI 0xFC0A4004
66#define MCFGPIO_PODR_TIMER 0xFC0A4005
67#define MCFGPIO_PODR_UART 0xFC0A4006
68#define MCFGPIO_PODR_FECH 0xFC0A4007
69#define MCFGPIO_PODR_FECL 0xFC0A4008
70
71#define MCFGPIO_PDDR_BUSCTL 0xFC0A400C
72#define MCFGPIO_PDDR_BE 0xFC0A400D
73#define MCFGPIO_PDDR_CS 0xFC0A400E
74#define MCFGPIO_PDDR_FECI2C 0xFC0A400F
75#define MCFGPIO_PDDR_QSPI 0xFC0A4010
76#define MCFGPIO_PDDR_TIMER 0xFC0A4011
77#define MCFGPIO_PDDR_UART 0xFC0A4012
78#define MCFGPIO_PDDR_FECH 0xFC0A4013
79#define MCFGPIO_PDDR_FECL 0xFC0A4014
80
81#define MCFGPIO_PPDSDR_BUSCTL 0xFC0A401A
82#define MCFGPIO_PPDSDR_BE 0xFC0A401B
83#define MCFGPIO_PPDSDR_CS 0xFC0A401C
84#define MCFGPIO_PPDSDR_FECI2C 0xFC0A401D
85#define MCFGPIO_PPDSDR_QSPI 0xFC0A401E
86#define MCFGPIO_PPDSDR_TIMER 0xFC0A401F
87#define MCFGPIO_PPDSDR_UART 0xFC0A4021
88#define MCFGPIO_PPDSDR_FECH 0xFC0A4021
89#define MCFGPIO_PPDSDR_FECL 0xFC0A4022
90
91#define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024
92#define MCFGPIO_PCLRR_BE 0xFC0A4025
93#define MCFGPIO_PCLRR_CS 0xFC0A4026
94#define MCFGPIO_PCLRR_FECI2C 0xFC0A4027
95#define MCFGPIO_PCLRR_QSPI 0xFC0A4028
96#define MCFGPIO_PCLRR_TIMER 0xFC0A4029
97#define MCFGPIO_PCLRR_UART 0xFC0A402A
98#define MCFGPIO_PCLRR_FECH 0xFC0A402B
99#define MCFGPIO_PCLRR_FECL 0xFC0A402C
100/*
101 * Generic GPIO support
102 */
103#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
104#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
105#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
106#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
107#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
108
109#define MCFGPIO_PIN_MAX 80
110#define MCFGPIO_IRQ_MAX 8
111#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
112/****************************************************************************/
44 113
45#define MCF_GPIO_PAR_UART (0xA4036) 114#define MCF_GPIO_PAR_UART (0xA4036)
46#define MCF_GPIO_PAR_FECI2C (0xA4033) 115#define MCF_GPIO_PAR_FECI2C (0xA4033)
@@ -55,10 +124,6 @@
55#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) 124#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
56#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) 125#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
57 126
58#define ICR_INTRCONF 0x05
59#define MCFPIT_IMR MCFINTC_IMRL
60#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1)
61
62/* 127/*
63 * Reset Controll Unit. 128 * Reset Controll Unit.
64 */ 129 */
diff --git a/arch/m68k/include/asm/m523xsim.h b/arch/m68k/include/asm/m523xsim.h
index 55183b5df1b8..a34894cf8e6f 100644
--- a/arch/m68k/include/asm/m523xsim.h
+++ b/arch/m68k/include/asm/m523xsim.h
@@ -50,5 +50,82 @@
50#define MCF_RCR_SWRESET 0x80 /* Software reset bit */ 50#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
51#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */ 51#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
52 52
53#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
54#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
55#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
56#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003)
57#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004)
58#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005)
59#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006)
60#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007)
61#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008)
62#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009)
63#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A)
64#define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B)
65#define MCFGPIO_PODR_ETPU (MCF_IPSBAR + 0x10000C)
66
67#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010)
68#define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011)
69#define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012)
70#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013)
71#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014)
72#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015)
73#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016)
74#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017)
75#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018)
76#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019)
77#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A)
78#define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B)
79#define MCFGPIO_PDDR_ETPU (MCF_IPSBAR + 0x10001C)
80
81#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020)
82#define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021)
83#define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022)
84#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023)
85#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024)
86#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025)
87#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026)
88#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027)
89#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028)
90#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029)
91#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A)
92#define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B)
93#define MCFGPIO_PPDSDR_ETPU (MCF_IPSBAR + 0x10002C)
94
95#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030)
96#define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031)
97#define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032)
98#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033)
99#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034)
100#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035)
101#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036)
102#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037)
103#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038)
104#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039)
105#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A)
106#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
107#define MCFGPIO_PCLRR_ETPU (MCF_IPSBAR + 0x10003C)
108
109/*
110 * EPort
111 */
112
113#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
114#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
115#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
116
117/*
118 * Generic GPIO support
119 */
120#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
121#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
122#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
123#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
124#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
125
126#define MCFGPIO_PIN_MAX 107
127#define MCFGPIO_IRQ_MAX 8
128#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
129
53/****************************************************************************/ 130/****************************************************************************/
54#endif /* m523xsim_h */ 131#endif /* m523xsim_h */
diff --git a/arch/m68k/include/asm/m5249sim.h b/arch/m68k/include/asm/m5249sim.h
index 366eb8602d2f..14bce877ed88 100644
--- a/arch/m68k/include/asm/m5249sim.h
+++ b/arch/m68k/include/asm/m5249sim.h
@@ -71,16 +71,22 @@
71#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 71#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
72 72
73/* 73/*
74 * Define system peripheral IRQ usage.
75 */
76#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
77#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
78
79/*
74 * General purpose IO registers (in MBAR2). 80 * General purpose IO registers (in MBAR2).
75 */ 81 */
76#define MCFSIM2_GPIOREAD 0x0 /* GPIO read values */ 82#define MCFSIM2_GPIOREAD (MCF_MBAR2 + 0x000) /* GPIO read values */
77#define MCFSIM2_GPIOWRITE 0x4 /* GPIO write values */ 83#define MCFSIM2_GPIOWRITE (MCF_MBAR2 + 0x004) /* GPIO write values */
78#define MCFSIM2_GPIOENABLE 0x8 /* GPIO enabled */ 84#define MCFSIM2_GPIOENABLE (MCF_MBAR2 + 0x008) /* GPIO enabled */
79#define MCFSIM2_GPIOFUNC 0xc /* GPIO function */ 85#define MCFSIM2_GPIOFUNC (MCF_MBAR2 + 0x00C) /* GPIO function */
80#define MCFSIM2_GPIO1READ 0xb0 /* GPIO1 read values */ 86#define MCFSIM2_GPIO1READ (MCF_MBAR2 + 0x0B0) /* GPIO1 read values */
81#define MCFSIM2_GPIO1WRITE 0xb4 /* GPIO1 write values */ 87#define MCFSIM2_GPIO1WRITE (MCF_MBAR2 + 0x0B4) /* GPIO1 write values */
82#define MCFSIM2_GPIO1ENABLE 0xb8 /* GPIO1 enabled */ 88#define MCFSIM2_GPIO1ENABLE (MCF_MBAR2 + 0x0B8) /* GPIO1 enabled */
83#define MCFSIM2_GPIO1FUNC 0xbc /* GPIO1 function */ 89#define MCFSIM2_GPIO1FUNC (MCF_MBAR2 + 0x0BC) /* GPIO1 function */
84 90
85#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */ 91#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */
86#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */ 92#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */
@@ -100,20 +106,28 @@
100#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */ 106#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */
101#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */ 107#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */
102 108
103
104/* 109/*
105 * Macro to set IMR register. It is 32 bits on the 5249. 110 * Define the base interrupt for the second interrupt controller.
111 * We set it to 128, out of the way of the base interrupts, and plenty
112 * of room for its 64 interrupts.
106 */ 113 */
107#define MCFSIM_IMR_MASKALL 0x7fffe /* All SIM intr sources */ 114#define MCFINTC2_VECBASE 128
108 115
109#define mcf_getimr() \ 116#define MCFINTC2_GPIOIRQ0 (MCFINTC2_VECBASE + 32)
110 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) 117#define MCFINTC2_GPIOIRQ1 (MCFINTC2_VECBASE + 33)
118#define MCFINTC2_GPIOIRQ2 (MCFINTC2_VECBASE + 34)
119#define MCFINTC2_GPIOIRQ3 (MCFINTC2_VECBASE + 35)
120#define MCFINTC2_GPIOIRQ4 (MCFINTC2_VECBASE + 36)
121#define MCFINTC2_GPIOIRQ5 (MCFINTC2_VECBASE + 37)
122#define MCFINTC2_GPIOIRQ6 (MCFINTC2_VECBASE + 38)
123#define MCFINTC2_GPIOIRQ7 (MCFINTC2_VECBASE + 39)
111 124
112#define mcf_setimr(imr) \ 125/*
113 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); 126 * Generic GPIO support
114 127 */
115#define mcf_getipr() \ 128#define MCFGPIO_PIN_MAX 64
116 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) 129#define MCFGPIO_IRQ_MAX -1
130#define MCFGPIO_IRQ_VECBASE -1
117 131
118/****************************************************************************/ 132/****************************************************************************/
119 133
@@ -137,9 +151,9 @@
137 subql #1,%a1 /* get MBAR2 address in a1 */ 151 subql #1,%a1 /* get MBAR2 address in a1 */
138 152
139 /* 153 /*
140 * Move secondary interrupts to base at 128. 154 * Move secondary interrupts to their base (128).
141 */ 155 */
142 moveb #0x80,%d0 156 moveb #MCFINTC2_VECBASE,%d0
143 moveb %d0,0x16b(%a1) /* interrupt base register */ 157 moveb %d0,0x16b(%a1) /* interrupt base register */
144 158
145 /* 159 /*
diff --git a/arch/m68k/include/asm/m5272sim.h b/arch/m68k/include/asm/m5272sim.h
index 6217edc21139..df3332c2317d 100644
--- a/arch/m68k/include/asm/m5272sim.h
+++ b/arch/m68k/include/asm/m5272sim.h
@@ -12,7 +12,6 @@
12#define m5272sim_h 12#define m5272sim_h
13/****************************************************************************/ 13/****************************************************************************/
14 14
15
16/* 15/*
17 * Define the 5272 SIM register set addresses. 16 * Define the 5272 SIM register set addresses.
18 */ 17 */
@@ -63,16 +62,59 @@
63#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ 62#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */
64#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ 63#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */
65 64
66#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */ 65#define MCFSIM_PACNT (MCF_MBAR + 0x80) /* Port A Control (r/w) */
67#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */ 66#define MCFSIM_PADDR (MCF_MBAR + 0x84) /* Port A Direction (r/w) */
68#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */ 67#define MCFSIM_PADAT (MCF_MBAR + 0x86) /* Port A Data (r/w) */
69#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */ 68#define MCFSIM_PBCNT (MCF_MBAR + 0x88) /* Port B Control (r/w) */
70#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */ 69#define MCFSIM_PBDDR (MCF_MBAR + 0x8c) /* Port B Direction (r/w) */
71#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */ 70#define MCFSIM_PBDAT (MCF_MBAR + 0x8e) /* Port B Data (r/w) */
72#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */ 71#define MCFSIM_PCDDR (MCF_MBAR + 0x94) /* Port C Direction (r/w) */
73#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */ 72#define MCFSIM_PCDAT (MCF_MBAR + 0x96) /* Port C Data (r/w) */
74#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */ 73#define MCFSIM_PDCNT (MCF_MBAR + 0x98) /* Port D Control (r/w) */
74
75/*
76 * Define system peripheral IRQ usage.
77 */
78#define MCFINT_VECBASE 64 /* Base of interrupts */
79#define MCF_IRQ_SPURIOUS 64 /* User Spurious */
80#define MCF_IRQ_EINT1 65 /* External Interrupt 1 */
81#define MCF_IRQ_EINT2 66 /* External Interrupt 2 */
82#define MCF_IRQ_EINT3 67 /* External Interrupt 3 */
83#define MCF_IRQ_EINT4 68 /* External Interrupt 4 */
84#define MCF_IRQ_TIMER1 69 /* Timer 1 */
85#define MCF_IRQ_TIMER2 70 /* Timer 2 */
86#define MCF_IRQ_TIMER3 71 /* Timer 3 */
87#define MCF_IRQ_TIMER4 72 /* Timer 4 */
88#define MCF_IRQ_UART1 73 /* UART 1 */
89#define MCF_IRQ_UART2 74 /* UART 2 */
90#define MCF_IRQ_PLIP 75 /* PLIC 2Khz Periodic */
91#define MCF_IRQ_PLIA 76 /* PLIC Asynchronous */
92#define MCF_IRQ_USB0 77 /* USB Endpoint 0 */
93#define MCF_IRQ_USB1 78 /* USB Endpoint 1 */
94#define MCF_IRQ_USB2 79 /* USB Endpoint 2 */
95#define MCF_IRQ_USB3 80 /* USB Endpoint 3 */
96#define MCF_IRQ_USB4 81 /* USB Endpoint 4 */
97#define MCF_IRQ_USB5 82 /* USB Endpoint 5 */
98#define MCF_IRQ_USB6 83 /* USB Endpoint 6 */
99#define MCF_IRQ_USB7 84 /* USB Endpoint 7 */
100#define MCF_IRQ_DMA 85 /* DMA Controller */
101#define MCF_IRQ_ERX 86 /* Ethernet Receiver */
102#define MCF_IRQ_ETX 87 /* Ethernet Transmitter */
103#define MCF_IRQ_ENTC 88 /* Ethernet Non-Time Critical */
104#define MCF_IRQ_QSPI 89 /* Queued Serial Interface */
105#define MCF_IRQ_EINT5 90 /* External Interrupt 5 */
106#define MCF_IRQ_EINT6 91 /* External Interrupt 6 */
107#define MCF_IRQ_SWTO 92 /* Software Watchdog */
108#define MCFINT_VECMAX 95 /* Maxmum interrupt */
75 109
110#define MCF_IRQ_TIMER MCF_IRQ_TIMER1
111#define MCF_IRQ_PROFILER MCF_IRQ_TIMER2
76 112
113/*
114 * Generic GPIO support
115 */
116#define MCFGPIO_PIN_MAX 48
117#define MCFGPIO_IRQ_MAX -1
118#define MCFGPIO_IRQ_VECBASE -1
77/****************************************************************************/ 119/****************************************************************************/
78#endif /* m5272sim_h */ 120#endif /* m5272sim_h */
diff --git a/arch/m68k/include/asm/m527xsim.h b/arch/m68k/include/asm/m527xsim.h
index 95f4f8ee8f7c..453356d72d80 100644
--- a/arch/m68k/include/asm/m527xsim.h
+++ b/arch/m68k/include/asm/m527xsim.h
@@ -54,6 +54,175 @@
54#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ 54#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */
55#endif 55#endif
56 56
57
58#ifdef CONFIG_M5271
59#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100000)
60#define MCFGPIO_PODR_DATAH (MCF_IPSBAR + 0x100001)
61#define MCFGPIO_PODR_DATAL (MCF_IPSBAR + 0x100002)
62#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100003)
63#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100004)
64#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100005)
65#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x100006)
66#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x100007)
67#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100008)
68#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100009)
69#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000A)
70#define MCFGPIO_PODR_TIMER (MCF_IPSBAR + 0x10000B)
71
72#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100010)
73#define MCFGPIO_PDDR_DATAH (MCF_IPSBAR + 0x100011)
74#define MCFGPIO_PDDR_DATAL (MCF_IPSBAR + 0x100012)
75#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100013)
76#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100014)
77#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100015)
78#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x100016)
79#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100017)
80#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100018)
81#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x100019)
82#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x10001A)
83#define MCFGPIO_PDDR_TIMER (MCF_IPSBAR + 0x10001B)
84
85#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x100020)
86#define MCFGPIO_PPDSDR_DATAH (MCF_IPSBAR + 0x100021)
87#define MCFGPIO_PPDSDR_DATAL (MCF_IPSBAR + 0x100022)
88#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x100023)
89#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x100024)
90#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100025)
91#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100026)
92#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100027)
93#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100028)
94#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100029)
95#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x10002A)
96#define MCFGPIO_PPDSDR_TIMER (MCF_IPSBAR + 0x10002B)
97
98#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100030)
99#define MCFGPIO_PCLRR_DATAH (MCF_IPSBAR + 0x100031)
100#define MCFGPIO_PCLRR_DATAL (MCF_IPSBAR + 0x100032)
101#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100033)
102#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100034)
103#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x100035)
104#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100036)
105#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100037)
106#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x100038)
107#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100039)
108#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x10003A)
109#define MCFGPIO_PCLRR_TIMER (MCF_IPSBAR + 0x10003B)
110
111/*
112 * Generic GPIO support
113 */
114#define MCFGPIO_PODR MCFGPIO_PODR_ADDR
115#define MCFGPIO_PDDR MCFGPIO_PDDR_ADDR
116#define MCFGPIO_PPDR MCFGPIO_PPDSDR_ADDR
117#define MCFGPIO_SETR MCFGPIO_PPDSDR_ADDR
118#define MCFGPIO_CLRR MCFGPIO_PCLRR_ADDR
119
120#define MCFGPIO_PIN_MAX 100
121#define MCFGPIO_IRQ_MAX 8
122#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
123#endif
124
125#ifdef CONFIG_M5275
126#define MCFGPIO_PODR_BUSCTL (MCF_IPSBAR + 0x100004)
127#define MCFGPIO_PODR_ADDR (MCF_IPSBAR + 0x100005)
128#define MCFGPIO_PODR_CS (MCF_IPSBAR + 0x100008)
129#define MCFGPIO_PODR_FEC0H (MCF_IPSBAR + 0x10000A)
130#define MCFGPIO_PODR_FEC0L (MCF_IPSBAR + 0x10000B)
131#define MCFGPIO_PODR_FECI2C (MCF_IPSBAR + 0x10000C)
132#define MCFGPIO_PODR_QSPI (MCF_IPSBAR + 0x10000D)
133#define MCFGPIO_PODR_SDRAM (MCF_IPSBAR + 0x10000E)
134#define MCFGPIO_PODR_TIMERH (MCF_IPSBAR + 0x10000F)
135#define MCFGPIO_PODR_TIMERL (MCF_IPSBAR + 0x100010)
136#define MCFGPIO_PODR_UARTL (MCF_IPSBAR + 0x100011)
137#define MCFGPIO_PODR_FEC1H (MCF_IPSBAR + 0x100012)
138#define MCFGPIO_PODR_FEC1L (MCF_IPSBAR + 0x100013)
139#define MCFGPIO_PODR_BS (MCF_IPSBAR + 0x100014)
140#define MCFGPIO_PODR_IRQ (MCF_IPSBAR + 0x100015)
141#define MCFGPIO_PODR_USBH (MCF_IPSBAR + 0x100016)
142#define MCFGPIO_PODR_USBL (MCF_IPSBAR + 0x100017)
143#define MCFGPIO_PODR_UARTH (MCF_IPSBAR + 0x100018)
144
145#define MCFGPIO_PDDR_BUSCTL (MCF_IPSBAR + 0x100020)
146#define MCFGPIO_PDDR_ADDR (MCF_IPSBAR + 0x100021)
147#define MCFGPIO_PDDR_CS (MCF_IPSBAR + 0x100024)
148#define MCFGPIO_PDDR_FEC0H (MCF_IPSBAR + 0x100026)
149#define MCFGPIO_PDDR_FEC0L (MCF_IPSBAR + 0x100027)
150#define MCFGPIO_PDDR_FECI2C (MCF_IPSBAR + 0x100028)
151#define MCFGPIO_PDDR_QSPI (MCF_IPSBAR + 0x100029)
152#define MCFGPIO_PDDR_SDRAM (MCF_IPSBAR + 0x10002A)
153#define MCFGPIO_PDDR_TIMERH (MCF_IPSBAR + 0x10002B)
154#define MCFGPIO_PDDR_TIMERL (MCF_IPSBAR + 0x10002C)
155#define MCFGPIO_PDDR_UARTL (MCF_IPSBAR + 0x10002D)
156#define MCFGPIO_PDDR_FEC1H (MCF_IPSBAR + 0x10002E)
157#define MCFGPIO_PDDR_FEC1L (MCF_IPSBAR + 0x10002F)
158#define MCFGPIO_PDDR_BS (MCF_IPSBAR + 0x100030)
159#define MCFGPIO_PDDR_IRQ (MCF_IPSBAR + 0x100031)
160#define MCFGPIO_PDDR_USBH (MCF_IPSBAR + 0x100032)
161#define MCFGPIO_PDDR_USBL (MCF_IPSBAR + 0x100033)
162#define MCFGPIO_PDDR_UARTH (MCF_IPSBAR + 0x100034)
163
164#define MCFGPIO_PPDSDR_BUSCTL (MCF_IPSBAR + 0x10003C)
165#define MCFGPIO_PPDSDR_ADDR (MCF_IPSBAR + 0x10003D)
166#define MCFGPIO_PPDSDR_CS (MCF_IPSBAR + 0x100040)
167#define MCFGPIO_PPDSDR_FEC0H (MCF_IPSBAR + 0x100042)
168#define MCFGPIO_PPDSDR_FEC0L (MCF_IPSBAR + 0x100043)
169#define MCFGPIO_PPDSDR_FECI2C (MCF_IPSBAR + 0x100044)
170#define MCFGPIO_PPDSDR_QSPI (MCF_IPSBAR + 0x100045)
171#define MCFGPIO_PPDSDR_SDRAM (MCF_IPSBAR + 0x100046)
172#define MCFGPIO_PPDSDR_TIMERH (MCF_IPSBAR + 0x100047)
173#define MCFGPIO_PPDSDR_TIMERL (MCF_IPSBAR + 0x100048)
174#define MCFGPIO_PPDSDR_UARTL (MCF_IPSBAR + 0x100049)
175#define MCFGPIO_PPDSDR_FEC1H (MCF_IPSBAR + 0x10004A)
176#define MCFGPIO_PPDSDR_FEC1L (MCF_IPSBAR + 0x10004B)
177#define MCFGPIO_PPDSDR_BS (MCF_IPSBAR + 0x10004C)
178#define MCFGPIO_PPDSDR_IRQ (MCF_IPSBAR + 0x10004D)
179#define MCFGPIO_PPDSDR_USBH (MCF_IPSBAR + 0x10004E)
180#define MCFGPIO_PPDSDR_USBL (MCF_IPSBAR + 0x10004F)
181#define MCFGPIO_PPDSDR_UARTH (MCF_IPSBAR + 0x100050)
182
183#define MCFGPIO_PCLRR_BUSCTL (MCF_IPSBAR + 0x100058)
184#define MCFGPIO_PCLRR_ADDR (MCF_IPSBAR + 0x100059)
185#define MCFGPIO_PCLRR_CS (MCF_IPSBAR + 0x10005C)
186#define MCFGPIO_PCLRR_FEC0H (MCF_IPSBAR + 0x10005E)
187#define MCFGPIO_PCLRR_FEC0L (MCF_IPSBAR + 0x10005F)
188#define MCFGPIO_PCLRR_FECI2C (MCF_IPSBAR + 0x100060)
189#define MCFGPIO_PCLRR_QSPI (MCF_IPSBAR + 0x100061)
190#define MCFGPIO_PCLRR_SDRAM (MCF_IPSBAR + 0x100062)
191#define MCFGPIO_PCLRR_TIMERH (MCF_IPSBAR + 0x100063)
192#define MCFGPIO_PCLRR_TIMERL (MCF_IPSBAR + 0x100064)
193#define MCFGPIO_PCLRR_UARTL (MCF_IPSBAR + 0x100065)
194#define MCFGPIO_PCLRR_FEC1H (MCF_IPSBAR + 0x100066)
195#define MCFGPIO_PCLRR_FEC1L (MCF_IPSBAR + 0x100067)
196#define MCFGPIO_PCLRR_BS (MCF_IPSBAR + 0x100068)
197#define MCFGPIO_PCLRR_IRQ (MCF_IPSBAR + 0x100069)
198#define MCFGPIO_PCLRR_USBH (MCF_IPSBAR + 0x10006A)
199#define MCFGPIO_PCLRR_USBL (MCF_IPSBAR + 0x10006B)
200#define MCFGPIO_PCLRR_UARTH (MCF_IPSBAR + 0x10006C)
201
202
203/*
204 * Generic GPIO support
205 */
206#define MCFGPIO_PODR MCFGPIO_PODR_BUSCTL
207#define MCFGPIO_PDDR MCFGPIO_PDDR_BUSCTL
208#define MCFGPIO_PPDR MCFGPIO_PPDSDR_BUSCTL
209#define MCFGPIO_SETR MCFGPIO_PPDSDR_BUSCTL
210#define MCFGPIO_CLRR MCFGPIO_PCLRR_BUSCTL
211
212#define MCFGPIO_PIN_MAX 148
213#define MCFGPIO_IRQ_MAX 8
214#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
215#endif
216
217/*
218 * EPort
219 */
220
221#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x130002)
222#define MCFEPORT_EPDR (MCF_IPSBAR + 0x130004)
223#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x130005)
224
225
57/* 226/*
58 * GPIO pins setups to enable the UARTs. 227 * GPIO pins setups to enable the UARTs.
59 */ 228 */
diff --git a/arch/m68k/include/asm/m528xsim.h b/arch/m68k/include/asm/m528xsim.h
index d79c49f8134a..e2ad1f42b657 100644
--- a/arch/m68k/include/asm/m528xsim.h
+++ b/arch/m68k/include/asm/m528xsim.h
@@ -41,6 +41,157 @@
41#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ 41#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */
42 42
43/* 43/*
44 * GPIO registers
45 */
46#define MCFGPIO_PORTA (MCF_IPSBAR + 0x00100000)
47#define MCFGPIO_PORTB (MCF_IPSBAR + 0x00100001)
48#define MCFGPIO_PORTC (MCF_IPSBAR + 0x00100002)
49#define MCFGPIO_PORTD (MCF_IPSBAR + 0x00100003)
50#define MCFGPIO_PORTE (MCF_IPSBAR + 0x00100004)
51#define MCFGPIO_PORTF (MCF_IPSBAR + 0x00100005)
52#define MCFGPIO_PORTG (MCF_IPSBAR + 0x00100006)
53#define MCFGPIO_PORTH (MCF_IPSBAR + 0x00100007)
54#define MCFGPIO_PORTJ (MCF_IPSBAR + 0x00100008)
55#define MCFGPIO_PORTDD (MCF_IPSBAR + 0x00100009)
56#define MCFGPIO_PORTEH (MCF_IPSBAR + 0x0010000A)
57#define MCFGPIO_PORTEL (MCF_IPSBAR + 0x0010000B)
58#define MCFGPIO_PORTAS (MCF_IPSBAR + 0x0010000C)
59#define MCFGPIO_PORTQS (MCF_IPSBAR + 0x0010000D)
60#define MCFGPIO_PORTSD (MCF_IPSBAR + 0x0010000E)
61#define MCFGPIO_PORTTC (MCF_IPSBAR + 0x0010000F)
62#define MCFGPIO_PORTTD (MCF_IPSBAR + 0x00100010)
63#define MCFGPIO_PORTUA (MCF_IPSBAR + 0x00100011)
64
65#define MCFGPIO_DDRA (MCF_IPSBAR + 0x00100014)
66#define MCFGPIO_DDRB (MCF_IPSBAR + 0x00100015)
67#define MCFGPIO_DDRC (MCF_IPSBAR + 0x00100016)
68#define MCFGPIO_DDRD (MCF_IPSBAR + 0x00100017)
69#define MCFGPIO_DDRE (MCF_IPSBAR + 0x00100018)
70#define MCFGPIO_DDRF (MCF_IPSBAR + 0x00100019)
71#define MCFGPIO_DDRG (MCF_IPSBAR + 0x0010001A)
72#define MCFGPIO_DDRH (MCF_IPSBAR + 0x0010001B)
73#define MCFGPIO_DDRJ (MCF_IPSBAR + 0x0010001C)
74#define MCFGPIO_DDRDD (MCF_IPSBAR + 0x0010001D)
75#define MCFGPIO_DDREH (MCF_IPSBAR + 0x0010001E)
76#define MCFGPIO_DDREL (MCF_IPSBAR + 0x0010001F)
77#define MCFGPIO_DDRAS (MCF_IPSBAR + 0x00100020)
78#define MCFGPIO_DDRQS (MCF_IPSBAR + 0x00100021)
79#define MCFGPIO_DDRSD (MCF_IPSBAR + 0x00100022)
80#define MCFGPIO_DDRTC (MCF_IPSBAR + 0x00100023)
81#define MCFGPIO_DDRTD (MCF_IPSBAR + 0x00100024)
82#define MCFGPIO_DDRUA (MCF_IPSBAR + 0x00100025)
83
84#define MCFGPIO_PORTAP (MCF_IPSBAR + 0x00100028)
85#define MCFGPIO_PORTBP (MCF_IPSBAR + 0x00100029)
86#define MCFGPIO_PORTCP (MCF_IPSBAR + 0x0010002A)
87#define MCFGPIO_PORTDP (MCF_IPSBAR + 0x0010002B)
88#define MCFGPIO_PORTEP (MCF_IPSBAR + 0x0010002C)
89#define MCFGPIO_PORTFP (MCF_IPSBAR + 0x0010002D)
90#define MCFGPIO_PORTGP (MCF_IPSBAR + 0x0010002E)
91#define MCFGPIO_PORTHP (MCF_IPSBAR + 0x0010002F)
92#define MCFGPIO_PORTJP (MCF_IPSBAR + 0x00100030)
93#define MCFGPIO_PORTDDP (MCF_IPSBAR + 0x00100031)
94#define MCFGPIO_PORTEHP (MCF_IPSBAR + 0x00100032)
95#define MCFGPIO_PORTELP (MCF_IPSBAR + 0x00100033)
96#define MCFGPIO_PORTASP (MCF_IPSBAR + 0x00100034)
97#define MCFGPIO_PORTQSP (MCF_IPSBAR + 0x00100035)
98#define MCFGPIO_PORTSDP (MCF_IPSBAR + 0x00100036)
99#define MCFGPIO_PORTTCP (MCF_IPSBAR + 0x00100037)
100#define MCFGPIO_PORTTDP (MCF_IPSBAR + 0x00100038)
101#define MCFGPIO_PORTUAP (MCF_IPSBAR + 0x00100039)
102
103#define MCFGPIO_SETA (MCF_IPSBAR + 0x00100028)
104#define MCFGPIO_SETB (MCF_IPSBAR + 0x00100029)
105#define MCFGPIO_SETC (MCF_IPSBAR + 0x0010002A)
106#define MCFGPIO_SETD (MCF_IPSBAR + 0x0010002B)
107#define MCFGPIO_SETE (MCF_IPSBAR + 0x0010002C)
108#define MCFGPIO_SETF (MCF_IPSBAR + 0x0010002D)
109#define MCFGPIO_SETG (MCF_IPSBAR + 0x0010002E)
110#define MCFGPIO_SETH (MCF_IPSBAR + 0x0010002F)
111#define MCFGPIO_SETJ (MCF_IPSBAR + 0x00100030)
112#define MCFGPIO_SETDD (MCF_IPSBAR + 0x00100031)
113#define MCFGPIO_SETEH (MCF_IPSBAR + 0x00100032)
114#define MCFGPIO_SETEL (MCF_IPSBAR + 0x00100033)
115#define MCFGPIO_SETAS (MCF_IPSBAR + 0x00100034)
116#define MCFGPIO_SETQS (MCF_IPSBAR + 0x00100035)
117#define MCFGPIO_SETSD (MCF_IPSBAR + 0x00100036)
118#define MCFGPIO_SETTC (MCF_IPSBAR + 0x00100037)
119#define MCFGPIO_SETTD (MCF_IPSBAR + 0x00100038)
120#define MCFGPIO_SETUA (MCF_IPSBAR + 0x00100039)
121
122#define MCFGPIO_CLRA (MCF_IPSBAR + 0x0010003C)
123#define MCFGPIO_CLRB (MCF_IPSBAR + 0x0010003D)
124#define MCFGPIO_CLRC (MCF_IPSBAR + 0x0010003E)
125#define MCFGPIO_CLRD (MCF_IPSBAR + 0x0010003F)
126#define MCFGPIO_CLRE (MCF_IPSBAR + 0x00100040)
127#define MCFGPIO_CLRF (MCF_IPSBAR + 0x00100041)
128#define MCFGPIO_CLRG (MCF_IPSBAR + 0x00100042)
129#define MCFGPIO_CLRH (MCF_IPSBAR + 0x00100043)
130#define MCFGPIO_CLRJ (MCF_IPSBAR + 0x00100044)
131#define MCFGPIO_CLRDD (MCF_IPSBAR + 0x00100045)
132#define MCFGPIO_CLREH (MCF_IPSBAR + 0x00100046)
133#define MCFGPIO_CLREL (MCF_IPSBAR + 0x00100047)
134#define MCFGPIO_CLRAS (MCF_IPSBAR + 0x00100048)
135#define MCFGPIO_CLRQS (MCF_IPSBAR + 0x00100049)
136#define MCFGPIO_CLRSD (MCF_IPSBAR + 0x0010004A)
137#define MCFGPIO_CLRTC (MCF_IPSBAR + 0x0010004B)
138#define MCFGPIO_CLRTD (MCF_IPSBAR + 0x0010004C)
139#define MCFGPIO_CLRUA (MCF_IPSBAR + 0x0010004D)
140
141#define MCFGPIO_PBCDPAR (MCF_IPSBAR + 0x00100050)
142#define MCFGPIO_PFPAR (MCF_IPSBAR + 0x00100051)
143#define MCFGPIO_PEPAR (MCF_IPSBAR + 0x00100052)
144#define MCFGPIO_PJPAR (MCF_IPSBAR + 0x00100054)
145#define MCFGPIO_PSDPAR (MCF_IPSBAR + 0x00100055)
146#define MCFGPIO_PASPAR (MCF_IPSBAR + 0x00100056)
147#define MCFGPIO_PEHLPAR (MCF_IPSBAR + 0x00100058)
148#define MCFGPIO_PQSPAR (MCF_IPSBAR + 0x00100059)
149#define MCFGPIO_PTCPAR (MCF_IPSBAR + 0x0010005A)
150#define MCFGPIO_PTDPAR (MCF_IPSBAR + 0x0010005B)
151#define MCFGPIO_PUAPAR (MCF_IPSBAR + 0x0010005C)
152
153/*
154 * Edge Port registers
155 */
156#define MCFEPORT_EPPAR (MCF_IPSBAR + 0x00130000)
157#define MCFEPORT_EPDDR (MCF_IPSBAR + 0x00130002)
158#define MCFEPORT_EPIER (MCF_IPSBAR + 0x00130003)
159#define MCFEPORT_EPDR (MCF_IPSBAR + 0x00130004)
160#define MCFEPORT_EPPDR (MCF_IPSBAR + 0x00130005)
161#define MCFEPORT_EPFR (MCF_IPSBAR + 0x00130006)
162
163/*
164 * Queued ADC registers
165 */
166#define MCFQADC_PORTQA (MCF_IPSBAR + 0x00190006)
167#define MCFQADC_PORTQB (MCF_IPSBAR + 0x00190007)
168#define MCFQADC_DDRQA (MCF_IPSBAR + 0x00190008)
169#define MCFQADC_DDRQB (MCF_IPSBAR + 0x00190009)
170
171/*
172 * General Purpose Timers registers
173 */
174#define MCFGPTA_GPTPORT (MCF_IPSBAR + 0x001A001D)
175#define MCFGPTA_GPTDDR (MCF_IPSBAR + 0x001A001E)
176#define MCFGPTB_GPTPORT (MCF_IPSBAR + 0x001B001D)
177#define MCFGPTB_GPTDDR (MCF_IPSBAR + 0x001B001E)
178/*
179 *
180 * definitions for generic gpio support
181 *
182 */
183#define MCFGPIO_PODR MCFGPIO_PORTA /* port output data */
184#define MCFGPIO_PDDR MCFGPIO_DDRA /* port data direction */
185#define MCFGPIO_PPDR MCFGPIO_PORTAP /* port pin data */
186#define MCFGPIO_SETR MCFGPIO_SETA /* set output */
187#define MCFGPIO_CLRR MCFGPIO_CLRA /* clr output */
188
189#define MCFGPIO_IRQ_MAX 8
190#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
191#define MCFGPIO_PIN_MAX 180
192
193
194/*
44 * Derek Cheung - 6 Feb 2005 195 * Derek Cheung - 6 Feb 2005
45 * add I2C and QSPI register definition using Freescale's MCF5282 196 * add I2C and QSPI register definition using Freescale's MCF5282
46 */ 197 */
diff --git a/arch/m68k/include/asm/m5307sim.h b/arch/m68k/include/asm/m5307sim.h
index 5886728409c0..c6830e5b54ce 100644
--- a/arch/m68k/include/asm/m5307sim.h
+++ b/arch/m68k/include/asm/m5307sim.h
@@ -90,8 +90,15 @@
90#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ 90#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
91#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ 91#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
92 92
93#define MCFSIM_PADDR 0x244 /* Parallel Direction (r/w) */ 93#define MCFSIM_PADDR (MCF_MBAR + 0x244)
94#define MCFSIM_PADAT 0x248 /* Parallel Data (r/w) */ 94#define MCFSIM_PADAT (MCF_MBAR + 0x248)
95
96/*
97 * Generic GPIO support
98 */
99#define MCFGPIO_PIN_MAX 16
100#define MCFGPIO_IRQ_MAX -1
101#define MCFGPIO_IRQ_VECBASE -1
95 102
96 103
97/* Definition offset address for CS2-7 -- old mask 5307 */ 104/* Definition offset address for CS2-7 -- old mask 5307 */
@@ -117,22 +124,6 @@
117#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ 124#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
118#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 125#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
119 126
120#if defined(CONFIG_M5307)
121#define MCFSIM_IMR_MASKALL 0x3fffe /* All SIM intr sources */
122#endif
123
124/*
125 * Macro to set IMR register. It is 32 bits on the 5307.
126 */
127#define mcf_getimr() \
128 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
129
130#define mcf_setimr(imr) \
131 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
132
133#define mcf_getipr() \
134 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
135
136 127
137/* 128/*
138 * Some symbol defines for the Parallel Port Pin Assignment Register 129 * Some symbol defines for the Parallel Port Pin Assignment Register
@@ -149,6 +140,11 @@
149#define IRQ3_LEVEL6 0x40 140#define IRQ3_LEVEL6 0x40
150#define IRQ1_LEVEL2 0x20 141#define IRQ1_LEVEL2 0x20
151 142
143/*
144 * Define system peripheral IRQ usage.
145 */
146#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
147#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
152 148
153/* 149/*
154 * Define the Cache register flags. 150 * Define the Cache register flags.
diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index eb7fd4448947..36bf15aec9ae 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -56,47 +56,21 @@
56#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 56#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
57 57
58 58
59#define MCFSIM_IMR_MASKALL 0xFFFFFFFF /* All SIM intr sources */ 59#define MCFINTC0_SIMR 0xFC04801C
60 60#define MCFINTC0_CIMR 0xFC04801D
61#define MCFSIM_IMR_SIMR0 0xFC04801C 61#define MCFINTC0_ICR0 0xFC048040
62#define MCFSIM_IMR_SIMR1 0xFC04C01C 62#define MCFINTC1_SIMR 0xFC04C01C
63#define MCFSIM_IMR_CIMR0 0xFC04801D 63#define MCFINTC1_CIMR 0xFC04C01D
64#define MCFSIM_IMR_CIMR1 0xFC04C01D 64#define MCFINTC1_ICR0 0xFC04C040
65 65
66#define MCFSIM_ICR_TIMER1 (0xFC048040+32) 66#define MCFSIM_ICR_TIMER1 (0xFC048040+32)
67#define MCFSIM_ICR_TIMER2 (0xFC048040+33) 67#define MCFSIM_ICR_TIMER2 (0xFC048040+33)
68 68
69
70/* 69/*
71 * Macro to set IMR register. It is 32 bits on the 5307. 70 * Define system peripheral IRQ usage.
72 */ 71 */
73#define mcf_getimr() \ 72#define MCF_IRQ_TIMER (64 + 32) /* Timer0 */
74 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) 73#define MCF_IRQ_PROFILER (64 + 33) /* Timer1 */
75
76#define mcf_setimr(imr) \
77 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
78
79#define mcf_getipr() \
80 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
81
82#define mcf_getiprl() \
83 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRL))
84
85#define mcf_getiprh() \
86 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRH))
87
88
89#define mcf_enable_irq0(irq) \
90 *((volatile unsigned char*) (MCFSIM_IMR_CIMR0)) = (irq);
91
92#define mcf_enable_irq1(irq) \
93 *((volatile unsigned char*) (MCFSIM_IMR_CIMR1)) = (irq);
94
95#define mcf_disable_irq0(irq) \
96 *((volatile unsigned char*) (MCFSIM_IMR_SIMR0)) = (irq);
97
98#define mcf_disable_irq1(irq) \
99 *((volatile unsigned char*) (MCFSIM_IMR_SIMR1)) = (irq);
100 74
101/* 75/*
102 * Define the Cache register flags. 76 * Define the Cache register flags.
@@ -422,70 +396,70 @@
422 *********************************************************************/ 396 *********************************************************************/
423 397
424/* Register read/write macros */ 398/* Register read/write macros */
425#define MCF_GPIO_PODR_FECH MCF_REG08(0xFC0A4000) 399#define MCFGPIO_PODR_FECH (0xFC0A4000)
426#define MCF_GPIO_PODR_FECL MCF_REG08(0xFC0A4001) 400#define MCFGPIO_PODR_FECL (0xFC0A4001)
427#define MCF_GPIO_PODR_SSI MCF_REG08(0xFC0A4002) 401#define MCFGPIO_PODR_SSI (0xFC0A4002)
428#define MCF_GPIO_PODR_BUSCTL MCF_REG08(0xFC0A4003) 402#define MCFGPIO_PODR_BUSCTL (0xFC0A4003)
429#define MCF_GPIO_PODR_BE MCF_REG08(0xFC0A4004) 403#define MCFGPIO_PODR_BE (0xFC0A4004)
430#define MCF_GPIO_PODR_CS MCF_REG08(0xFC0A4005) 404#define MCFGPIO_PODR_CS (0xFC0A4005)
431#define MCF_GPIO_PODR_PWM MCF_REG08(0xFC0A4006) 405#define MCFGPIO_PODR_PWM (0xFC0A4006)
432#define MCF_GPIO_PODR_FECI2C MCF_REG08(0xFC0A4007) 406#define MCFGPIO_PODR_FECI2C (0xFC0A4007)
433#define MCF_GPIO_PODR_UART MCF_REG08(0xFC0A4009) 407#define MCFGPIO_PODR_UART (0xFC0A4009)
434#define MCF_GPIO_PODR_QSPI MCF_REG08(0xFC0A400A) 408#define MCFGPIO_PODR_QSPI (0xFC0A400A)
435#define MCF_GPIO_PODR_TIMER MCF_REG08(0xFC0A400B) 409#define MCFGPIO_PODR_TIMER (0xFC0A400B)
436#define MCF_GPIO_PODR_LCDDATAH MCF_REG08(0xFC0A400D) 410#define MCFGPIO_PODR_LCDDATAH (0xFC0A400D)
437#define MCF_GPIO_PODR_LCDDATAM MCF_REG08(0xFC0A400E) 411#define MCFGPIO_PODR_LCDDATAM (0xFC0A400E)
438#define MCF_GPIO_PODR_LCDDATAL MCF_REG08(0xFC0A400F) 412#define MCFGPIO_PODR_LCDDATAL (0xFC0A400F)
439#define MCF_GPIO_PODR_LCDCTLH MCF_REG08(0xFC0A4010) 413#define MCFGPIO_PODR_LCDCTLH (0xFC0A4010)
440#define MCF_GPIO_PODR_LCDCTLL MCF_REG08(0xFC0A4011) 414#define MCFGPIO_PODR_LCDCTLL (0xFC0A4011)
441#define MCF_GPIO_PDDR_FECH MCF_REG08(0xFC0A4014) 415#define MCFGPIO_PDDR_FECH (0xFC0A4014)
442#define MCF_GPIO_PDDR_FECL MCF_REG08(0xFC0A4015) 416#define MCFGPIO_PDDR_FECL (0xFC0A4015)
443#define MCF_GPIO_PDDR_SSI MCF_REG08(0xFC0A4016) 417#define MCFGPIO_PDDR_SSI (0xFC0A4016)
444#define MCF_GPIO_PDDR_BUSCTL MCF_REG08(0xFC0A4017) 418#define MCFGPIO_PDDR_BUSCTL (0xFC0A4017)
445#define MCF_GPIO_PDDR_BE MCF_REG08(0xFC0A4018) 419#define MCFGPIO_PDDR_BE (0xFC0A4018)
446#define MCF_GPIO_PDDR_CS MCF_REG08(0xFC0A4019) 420#define MCFGPIO_PDDR_CS (0xFC0A4019)
447#define MCF_GPIO_PDDR_PWM MCF_REG08(0xFC0A401A) 421#define MCFGPIO_PDDR_PWM (0xFC0A401A)
448#define MCF_GPIO_PDDR_FECI2C MCF_REG08(0xFC0A401B) 422#define MCFGPIO_PDDR_FECI2C (0xFC0A401B)
449#define MCF_GPIO_PDDR_UART MCF_REG08(0xFC0A401C) 423#define MCFGPIO_PDDR_UART (0xFC0A401C)
450#define MCF_GPIO_PDDR_QSPI MCF_REG08(0xFC0A401E) 424#define MCFGPIO_PDDR_QSPI (0xFC0A401E)
451#define MCF_GPIO_PDDR_TIMER MCF_REG08(0xFC0A401F) 425#define MCFGPIO_PDDR_TIMER (0xFC0A401F)
452#define MCF_GPIO_PDDR_LCDDATAH MCF_REG08(0xFC0A4021) 426#define MCFGPIO_PDDR_LCDDATAH (0xFC0A4021)
453#define MCF_GPIO_PDDR_LCDDATAM MCF_REG08(0xFC0A4022) 427#define MCFGPIO_PDDR_LCDDATAM (0xFC0A4022)
454#define MCF_GPIO_PDDR_LCDDATAL MCF_REG08(0xFC0A4023) 428#define MCFGPIO_PDDR_LCDDATAL (0xFC0A4023)
455#define MCF_GPIO_PDDR_LCDCTLH MCF_REG08(0xFC0A4024) 429#define MCFGPIO_PDDR_LCDCTLH (0xFC0A4024)
456#define MCF_GPIO_PDDR_LCDCTLL MCF_REG08(0xFC0A4025) 430#define MCFGPIO_PDDR_LCDCTLL (0xFC0A4025)
457#define MCF_GPIO_PPDSDR_FECH MCF_REG08(0xFC0A4028) 431#define MCFGPIO_PPDSDR_FECH (0xFC0A4028)
458#define MCF_GPIO_PPDSDR_FECL MCF_REG08(0xFC0A4029) 432#define MCFGPIO_PPDSDR_FECL (0xFC0A4029)
459#define MCF_GPIO_PPDSDR_SSI MCF_REG08(0xFC0A402A) 433#define MCFGPIO_PPDSDR_SSI (0xFC0A402A)
460#define MCF_GPIO_PPDSDR_BUSCTL MCF_REG08(0xFC0A402B) 434#define MCFGPIO_PPDSDR_BUSCTL (0xFC0A402B)
461#define MCF_GPIO_PPDSDR_BE MCF_REG08(0xFC0A402C) 435#define MCFGPIO_PPDSDR_BE (0xFC0A402C)
462#define MCF_GPIO_PPDSDR_CS MCF_REG08(0xFC0A402D) 436#define MCFGPIO_PPDSDR_CS (0xFC0A402D)
463#define MCF_GPIO_PPDSDR_PWM MCF_REG08(0xFC0A402E) 437#define MCFGPIO_PPDSDR_PWM (0xFC0A402E)
464#define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0xFC0A402F) 438#define MCFGPIO_PPDSDR_FECI2C (0xFC0A402F)
465#define MCF_GPIO_PPDSDR_UART MCF_REG08(0xFC0A4031) 439#define MCFGPIO_PPDSDR_UART (0xFC0A4031)
466#define MCF_GPIO_PPDSDR_QSPI MCF_REG08(0xFC0A4032) 440#define MCFGPIO_PPDSDR_QSPI (0xFC0A4032)
467#define MCF_GPIO_PPDSDR_TIMER MCF_REG08(0xFC0A4033) 441#define MCFGPIO_PPDSDR_TIMER (0xFC0A4033)
468#define MCF_GPIO_PPDSDR_LCDDATAH MCF_REG08(0xFC0A4035) 442#define MCFGPIO_PPDSDR_LCDDATAH (0xFC0A4035)
469#define MCF_GPIO_PPDSDR_LCDDATAM MCF_REG08(0xFC0A4036) 443#define MCFGPIO_PPDSDR_LCDDATAM (0xFC0A4036)
470#define MCF_GPIO_PPDSDR_LCDDATAL MCF_REG08(0xFC0A4037) 444#define MCFGPIO_PPDSDR_LCDDATAL (0xFC0A4037)
471#define MCF_GPIO_PPDSDR_LCDCTLH MCF_REG08(0xFC0A4038) 445#define MCFGPIO_PPDSDR_LCDCTLH (0xFC0A4038)
472#define MCF_GPIO_PPDSDR_LCDCTLL MCF_REG08(0xFC0A4039) 446#define MCFGPIO_PPDSDR_LCDCTLL (0xFC0A4039)
473#define MCF_GPIO_PCLRR_FECH MCF_REG08(0xFC0A403C) 447#define MCFGPIO_PCLRR_FECH (0xFC0A403C)
474#define MCF_GPIO_PCLRR_FECL MCF_REG08(0xFC0A403D) 448#define MCFGPIO_PCLRR_FECL (0xFC0A403D)
475#define MCF_GPIO_PCLRR_SSI MCF_REG08(0xFC0A403E) 449#define MCFGPIO_PCLRR_SSI (0xFC0A403E)
476#define MCF_GPIO_PCLRR_BUSCTL MCF_REG08(0xFC0A403F) 450#define MCFGPIO_PCLRR_BUSCTL (0xFC0A403F)
477#define MCF_GPIO_PCLRR_BE MCF_REG08(0xFC0A4040) 451#define MCFGPIO_PCLRR_BE (0xFC0A4040)
478#define MCF_GPIO_PCLRR_CS MCF_REG08(0xFC0A4041) 452#define MCFGPIO_PCLRR_CS (0xFC0A4041)
479#define MCF_GPIO_PCLRR_PWM MCF_REG08(0xFC0A4042) 453#define MCFGPIO_PCLRR_PWM (0xFC0A4042)
480#define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0xFC0A4043) 454#define MCFGPIO_PCLRR_FECI2C (0xFC0A4043)
481#define MCF_GPIO_PCLRR_UART MCF_REG08(0xFC0A4045) 455#define MCFGPIO_PCLRR_UART (0xFC0A4045)
482#define MCF_GPIO_PCLRR_QSPI MCF_REG08(0xFC0A4046) 456#define MCFGPIO_PCLRR_QSPI (0xFC0A4046)
483#define MCF_GPIO_PCLRR_TIMER MCF_REG08(0xFC0A4047) 457#define MCFGPIO_PCLRR_TIMER (0xFC0A4047)
484#define MCF_GPIO_PCLRR_LCDDATAH MCF_REG08(0xFC0A4049) 458#define MCFGPIO_PCLRR_LCDDATAH (0xFC0A4049)
485#define MCF_GPIO_PCLRR_LCDDATAM MCF_REG08(0xFC0A404A) 459#define MCFGPIO_PCLRR_LCDDATAM (0xFC0A404A)
486#define MCF_GPIO_PCLRR_LCDDATAL MCF_REG08(0xFC0A404B) 460#define MCFGPIO_PCLRR_LCDDATAL (0xFC0A404B)
487#define MCF_GPIO_PCLRR_LCDCTLH MCF_REG08(0xFC0A404C) 461#define MCFGPIO_PCLRR_LCDCTLH (0xFC0A404C)
488#define MCF_GPIO_PCLRR_LCDCTLL MCF_REG08(0xFC0A404D) 462#define MCFGPIO_PCLRR_LCDCTLL (0xFC0A404D)
489#define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4050) 463#define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4050)
490#define MCF_GPIO_PAR_PWM MCF_REG08(0xFC0A4051) 464#define MCF_GPIO_PAR_PWM MCF_REG08(0xFC0A4051)
491#define MCF_GPIO_PAR_BUSCTL MCF_REG08(0xFC0A4052) 465#define MCF_GPIO_PAR_BUSCTL MCF_REG08(0xFC0A4052)
@@ -1187,6 +1161,20 @@
1187/* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */ 1161/* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */
1188#define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0) 1162#define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0)
1189 1163
1164/*
1165 * Generic GPIO support
1166 */
1167#define MCFGPIO_PODR MCFGPIO_PODR_FECH
1168#define MCFGPIO_PDDR MCFGPIO_PDDR_FECH
1169#define MCFGPIO_PPDR MCFGPIO_PPDSDR_FECH
1170#define MCFGPIO_SETR MCFGPIO_PPDSDR_FECH
1171#define MCFGPIO_CLRR MCFGPIO_PCLRR_FECH
1172
1173#define MCFGPIO_PIN_MAX 136
1174#define MCFGPIO_IRQ_MAX 8
1175#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
1176
1177
1190/********************************************************************* 1178/*********************************************************************
1191 * 1179 *
1192 * Interrupt Controller (INTC) 1180 * Interrupt Controller (INTC)
@@ -2154,12 +2142,12 @@
2154 *********************************************************************/ 2142 *********************************************************************/
2155 2143
2156/* Register read/write macros */ 2144/* Register read/write macros */
2157#define MCF_EPORT_EPPAR MCF_REG16(0xFC094000) 2145#define MCFEPORT_EPPAR (0xFC094000)
2158#define MCF_EPORT_EPDDR MCF_REG08(0xFC094002) 2146#define MCFEPORT_EPDDR (0xFC094002)
2159#define MCF_EPORT_EPIER MCF_REG08(0xFC094003) 2147#define MCFEPORT_EPIER (0xFC094003)
2160#define MCF_EPORT_EPDR MCF_REG08(0xFC094004) 2148#define MCFEPORT_EPDR (0xFC094004)
2161#define MCF_EPORT_EPPDR MCF_REG08(0xFC094005) 2149#define MCFEPORT_EPPDR (0xFC094005)
2162#define MCF_EPORT_EPFR MCF_REG08(0xFC094006) 2150#define MCFEPORT_EPFR (0xFC094006)
2163 2151
2164/* Bit definitions and macros for MCF_EPORT_EPPAR */ 2152/* Bit definitions and macros for MCF_EPORT_EPPAR */
2165#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) 2153#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
diff --git a/arch/m68k/include/asm/m5407sim.h b/arch/m68k/include/asm/m5407sim.h
index cc22c4a53005..c399abbf953c 100644
--- a/arch/m68k/include/asm/m5407sim.h
+++ b/arch/m68k/include/asm/m5407sim.h
@@ -73,9 +73,15 @@
73#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ 73#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
74#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ 74#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
75 75
76#define MCFSIM_PADDR 0x244 /* Parallel Direction (r/w) */ 76#define MCFSIM_PADDR (MCF_MBAR + 0x244)
77#define MCFSIM_PADAT 0x248 /* Parallel Data (r/w) */ 77#define MCFSIM_PADAT (MCF_MBAR + 0x248)
78 78
79/*
80 * Generic GPIO support
81 */
82#define MCFGPIO_PIN_MAX 16
83#define MCFGPIO_IRQ_MAX -1
84#define MCFGPIO_IRQ_VECBASE -1
79 85
80/* 86/*
81 * Some symbol defines for the above... 87 * Some symbol defines for the above...
@@ -91,19 +97,6 @@
91#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ 97#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
92 98
93/* 99/*
94 * Macro to set IMR register. It is 32 bits on the 5407.
95 */
96#define mcf_getimr() \
97 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
98
99#define mcf_setimr(imr) \
100 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
101
102#define mcf_getipr() \
103 *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR))
104
105
106/*
107 * Some symbol defines for the Parallel Port Pin Assignment Register 100 * Some symbol defines for the Parallel Port Pin Assignment Register
108 */ 101 */
109#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */ 102#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */
@@ -118,6 +111,11 @@
118#define IRQ3_LEVEL6 0x40 111#define IRQ3_LEVEL6 0x40
119#define IRQ1_LEVEL2 0x20 112#define IRQ1_LEVEL2 0x20
120 113
114/*
115 * Define system peripheral IRQ usage.
116 */
117#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
118#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
121 119
122/* 120/*
123 * Define the Cache register flags. 121 * Define the Cache register flags.
diff --git a/arch/m68k/include/asm/mcfgpio.h b/arch/m68k/include/asm/mcfgpio.h
new file mode 100644
index 000000000000..ee5e4ccce89e
--- /dev/null
+++ b/arch/m68k/include/asm/mcfgpio.h
@@ -0,0 +1,40 @@
1/*
2 * Coldfire generic GPIO support.
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef mcfgpio_h
17#define mcfgpio_h
18
19#include <linux/io.h>
20#include <asm-generic/gpio.h>
21
22struct mcf_gpio_chip {
23 struct gpio_chip gpio_chip;
24 void __iomem *pddr;
25 void __iomem *podr;
26 void __iomem *ppdr;
27 void __iomem *setr;
28 void __iomem *clrr;
29 const u8 *gpio_to_pinmux;
30};
31
32int mcf_gpio_direction_input(struct gpio_chip *, unsigned);
33int mcf_gpio_get_value(struct gpio_chip *, unsigned);
34int mcf_gpio_direction_output(struct gpio_chip *, unsigned, int);
35void mcf_gpio_set_value(struct gpio_chip *, unsigned, int);
36void mcf_gpio_set_value_fast(struct gpio_chip *, unsigned, int);
37int mcf_gpio_request(struct gpio_chip *, unsigned);
38void mcf_gpio_free(struct gpio_chip *, unsigned);
39
40#endif
diff --git a/arch/m68k/include/asm/mcfintc.h b/arch/m68k/include/asm/mcfintc.h
new file mode 100644
index 000000000000..4183320a3813
--- /dev/null
+++ b/arch/m68k/include/asm/mcfintc.h
@@ -0,0 +1,89 @@
1/****************************************************************************/
2
3/*
4 * mcfintc.h -- support definitions for the simple ColdFire
5 * Interrupt Controller
6 *
7 * (C) Copyright 2009, Greg Ungerer <gerg@uclinux.org>
8 */
9
10/****************************************************************************/
11#ifndef mcfintc_h
12#define mcfintc_h
13/****************************************************************************/
14
15/*
16 * Most of the older ColdFire parts use the same simple interrupt
17 * controller. This is currently used on the 5206, 5206e, 5249, 5307
18 * and 5407 parts.
19 *
20 * The builtin peripherals are masked through dedicated bits in the
21 * Interrupt Mask register (IMR) - and this is not indexed (or in any way
22 * related to) the actual interrupt number they use. So knowing the IRQ
23 * number doesn't explicitly map to a certain internal device for
24 * interrupt control purposes.
25 */
26
27/*
28 * Bit definitions for the ICR family of registers.
29 */
30#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
31#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
32#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
33#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
34#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
35#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
36#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
37#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
38#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
39
40#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
41#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
42#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
43#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
44
45/*
46 * IMR bit position definitions. Not all ColdFire parts with this interrupt
47 * controller actually support all of these interrupt sources. But the bit
48 * numbers are the same in all cores.
49 */
50#define MCFINTC_EINT1 1 /* External int #1 */
51#define MCFINTC_EINT2 2 /* External int #2 */
52#define MCFINTC_EINT3 3 /* External int #3 */
53#define MCFINTC_EINT4 4 /* External int #4 */
54#define MCFINTC_EINT5 5 /* External int #5 */
55#define MCFINTC_EINT6 6 /* External int #6 */
56#define MCFINTC_EINT7 7 /* External int #7 */
57#define MCFINTC_SWT 8 /* Software Watchdog */
58#define MCFINTC_TIMER1 9
59#define MCFINTC_TIMER2 10
60#define MCFINTC_I2C 11 /* I2C / MBUS */
61#define MCFINTC_UART0 12
62#define MCFINTC_UART1 13
63#define MCFINTC_DMA0 14
64#define MCFINTC_DMA1 15
65#define MCFINTC_DMA2 16
66#define MCFINTC_DMA3 17
67#define MCFINTC_QSPI 18
68
69#ifndef __ASSEMBLER__
70
71/*
72 * There is no one-is-one correspondance between the interrupt number (irq)
73 * and the bit fields on the mask register. So we create a per-cpu type
74 * mapping of irq to mask bit. The CPU platform code needs to register
75 * its supported irq's at init time, using this function.
76 */
77extern unsigned char mcf_irq2imr[];
78static inline void mcf_mapirq2imr(int irq, int imr)
79{
80 mcf_irq2imr[irq] = imr;
81}
82
83void mcf_autovector(int irq);
84void mcf_setimr(int index);
85void mcf_clrimr(int index);
86#endif
87
88/****************************************************************************/
89#endif /* mcfintc_h */
diff --git a/arch/m68k/include/asm/mcfne.h b/arch/m68k/include/asm/mcfne.h
index 431f63aadd0e..bf638be0958c 100644
--- a/arch/m68k/include/asm/mcfne.h
+++ b/arch/m68k/include/asm/mcfne.h
@@ -239,87 +239,4 @@ void ne2000_outsw(unsigned int addr, const void *vbuf, unsigned long len)
239#endif /* NE2000_OFFOFFSET */ 239#endif /* NE2000_OFFOFFSET */
240 240
241/****************************************************************************/ 241/****************************************************************************/
242
243#ifdef COLDFIRE_NE2000_FUNCS
244
245/*
246 * Lastly the interrupt set up code...
247 * Minor differences between the different board types.
248 */
249
250#if defined(CONFIG_ARN5206)
251void ne2000_irqsetup(int irq)
252{
253 volatile unsigned char *icrp;
254
255 icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_ICR4);
256 *icrp = MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI2;
257 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT4);
258}
259#endif
260
261#if defined(CONFIG_M5206eC3)
262void ne2000_irqsetup(int irq)
263{
264 volatile unsigned char *icrp;
265
266 icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_ICR4);
267 *icrp = MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI2 | MCFSIM_ICR_AUTOVEC;
268 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT4);
269}
270#endif
271
272#if defined(CONFIG_M5206e) && defined(CONFIG_NETtel)
273void ne2000_irqsetup(int irq)
274{
275 mcf_autovector(irq);
276}
277#endif
278
279#if defined(CONFIG_M5272) && defined(CONFIG_NETtel)
280void ne2000_irqsetup(int irq)
281{
282 volatile unsigned long *icrp;
283 volatile unsigned long *pitr;
284
285 /* The NE2000 device uses external IRQ3 */
286 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
287 *icrp = (*icrp & 0x77077777) | 0x00d00000;
288
289 pitr = (volatile unsigned long *) (MCF_MBAR + MCFSIM_PITR);
290 *pitr = *pitr | 0x20000000;
291}
292
293void ne2000_irqack(int irq)
294{
295 volatile unsigned long *icrp;
296
297 /* The NE2000 device uses external IRQ3 */
298 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
299 *icrp = (*icrp & 0x77777777) | 0x00800000;
300}
301#endif
302
303#if defined(CONFIG_M5307) || defined(CONFIG_M5407)
304#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3)
305
306void ne2000_irqsetup(int irq)
307{
308 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT3);
309 mcf_autovector(irq);
310}
311
312#else
313
314void ne2000_irqsetup(int irq)
315{
316 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT3);
317}
318
319#endif /* ! CONFIG_NETtel || CONFIG_SECUREEDGEMP3 */
320#endif /* CONFIG_M5307 || CONFIG_M5407 */
321
322#endif /* COLDFIRE_NE2000_FUNCS */
323
324/****************************************************************************/
325#endif /* mcfne_h */ 242#endif /* mcfne_h */
diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h
index da3f2ceff3a4..9c70a67bf85f 100644
--- a/arch/m68k/include/asm/mcfsim.h
+++ b/arch/m68k/include/asm/mcfsim.h
@@ -4,7 +4,7 @@
4 * mcfsim.h -- ColdFire System Integration Module support. 4 * mcfsim.h -- ColdFire System Integration Module support.
5 * 5 *
6 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com) 6 * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com) 7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
8 */ 8 */
9 9
10/****************************************************************************/ 10/****************************************************************************/
@@ -12,19 +12,21 @@
12#define mcfsim_h 12#define mcfsim_h
13/****************************************************************************/ 13/****************************************************************************/
14 14
15
16/* 15/*
17 * Include 5204, 5206/e, 5235, 5249, 5270/5271, 5272, 5280/5282, 16 * Include the appropriate ColdFire CPU specific System Integration Module
18 * 5307 or 5407 specific addresses. 17 * (SIM) definitions.
19 */ 18 */
20#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) 19#if defined(CONFIG_M5206) || defined(CONFIG_M5206e)
21#include <asm/m5206sim.h> 20#include <asm/m5206sim.h>
21#include <asm/mcfintc.h>
22#elif defined(CONFIG_M520x) 22#elif defined(CONFIG_M520x)
23#include <asm/m520xsim.h> 23#include <asm/m520xsim.h>
24#elif defined(CONFIG_M523x) 24#elif defined(CONFIG_M523x)
25#include <asm/m523xsim.h> 25#include <asm/m523xsim.h>
26#include <asm/mcfintc.h>
26#elif defined(CONFIG_M5249) 27#elif defined(CONFIG_M5249)
27#include <asm/m5249sim.h> 28#include <asm/m5249sim.h>
29#include <asm/mcfintc.h>
28#elif defined(CONFIG_M527x) 30#elif defined(CONFIG_M527x)
29#include <asm/m527xsim.h> 31#include <asm/m527xsim.h>
30#elif defined(CONFIG_M5272) 32#elif defined(CONFIG_M5272)
@@ -33,94 +35,13 @@
33#include <asm/m528xsim.h> 35#include <asm/m528xsim.h>
34#elif defined(CONFIG_M5307) 36#elif defined(CONFIG_M5307)
35#include <asm/m5307sim.h> 37#include <asm/m5307sim.h>
38#include <asm/mcfintc.h>
36#elif defined(CONFIG_M532x) 39#elif defined(CONFIG_M532x)
37#include <asm/m532xsim.h> 40#include <asm/m532xsim.h>
38#elif defined(CONFIG_M5407) 41#elif defined(CONFIG_M5407)
39#include <asm/m5407sim.h> 42#include <asm/m5407sim.h>
43#include <asm/mcfintc.h>
40#endif 44#endif
41 45
42
43/*
44 * Define the base address of the SIM within the MBAR address space.
45 */
46#define MCFSIM_BASE 0x0 /* Base address of SIM */
47
48
49/*
50 * Bit definitions for the ICR family of registers.
51 */
52#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
53#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
54#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
55#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
56#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
57#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
58#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
59#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
60#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
61
62#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
63#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
64#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
65#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
66
67/*
68 * Bit definitions for the Interrupt Mask register (IMR).
69 */
70#define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */
71#define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */
72#define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */
73#define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */
74#define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */
75#define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */
76#define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */
77
78#define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */
79#define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */
80#define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */
81#define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */
82#define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */
83#define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */
84
85#if defined(CONFIG_M5206e)
86#define MCFSIM_IMR_DMA1 0x4000 /* DMA 1 intr */
87#define MCFSIM_IMR_DMA2 0x8000 /* DMA 2 intr */
88#elif defined(CONFIG_M5249) || defined(CONFIG_M5307)
89#define MCFSIM_IMR_DMA0 0x4000 /* DMA 0 intr */
90#define MCFSIM_IMR_DMA1 0x8000 /* DMA 1 intr */
91#define MCFSIM_IMR_DMA2 0x10000 /* DMA 2 intr */
92#define MCFSIM_IMR_DMA3 0x20000 /* DMA 3 intr */
93#endif
94
95/*
96 * Mask for all of the SIM devices. Some parts have more or less
97 * SIM devices. This is a catchall for the sandard set.
98 */
99#ifndef MCFSIM_IMR_MASKALL
100#define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */
101#endif
102
103
104/*
105 * PIT interrupt settings, if not found in mXXXXsim.h file.
106 */
107#ifndef ICR_INTRCONF
108#define ICR_INTRCONF 0x2b /* PIT1 level 5, priority 3 */
109#endif
110#ifndef MCFPIT_IMR
111#define MCFPIT_IMR MCFINTC_IMRH
112#endif
113#ifndef MCFPIT_IMR_IBIT
114#define MCFPIT_IMR_IBIT (1 << (MCFINT_PIT1 - 32))
115#endif
116
117
118#ifndef __ASSEMBLY__
119/*
120 * Definition for the interrupt auto-vectoring support.
121 */
122extern void mcf_autovector(unsigned int vec);
123#endif /* __ASSEMBLY__ */
124
125/****************************************************************************/ 46/****************************************************************************/
126#endif /* mcfsim_h */ 47#endif /* mcfsim_h */
diff --git a/arch/m68k/include/asm/mcfsmc.h b/arch/m68k/include/asm/mcfsmc.h
index 2d7a4dbd9683..527bea5d6788 100644
--- a/arch/m68k/include/asm/mcfsmc.h
+++ b/arch/m68k/include/asm/mcfsmc.h
@@ -167,15 +167,15 @@ void smc_remap(unsigned int ioaddr)
167 static int once = 0; 167 static int once = 0;
168 extern unsigned short ppdata; 168 extern unsigned short ppdata;
169 if (once++ == 0) { 169 if (once++ == 0) {
170 *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADDR)) = 0x00ec; 170 *((volatile unsigned short *)MCFSIM_PADDR) = 0x00ec;
171 ppdata |= 0x0080; 171 ppdata |= 0x0080;
172 *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADAT)) = ppdata; 172 *((volatile unsigned short *)MCFSIM_PADAT) = ppdata;
173 outw(0x0001, ioaddr + BANK_SELECT); 173 outw(0x0001, ioaddr + BANK_SELECT);
174 outw(0x0001, ioaddr + BANK_SELECT); 174 outw(0x0001, ioaddr + BANK_SELECT);
175 outw(0x0067, ioaddr + BASE); 175 outw(0x0067, ioaddr + BASE);
176 176
177 ppdata &= ~0x0080; 177 ppdata &= ~0x0080;
178 *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADAT)) = ppdata; 178 *((volatile unsigned short *)MCFSIM_PADAT) = ppdata;
179 } 179 }
180 180
181 *((volatile unsigned short *)(MCF_MBAR+MCFSIM_CSCR3)) = 0x1180; 181 *((volatile unsigned short *)(MCF_MBAR+MCFSIM_CSCR3)) = 0x1180;
diff --git a/arch/m68k/include/asm/nettel.h b/arch/m68k/include/asm/nettel.h
index 0299f6a2deeb..4dec2d9fb994 100644
--- a/arch/m68k/include/asm/nettel.h
+++ b/arch/m68k/include/asm/nettel.h
@@ -48,14 +48,14 @@ extern volatile unsigned short ppdata;
48static __inline__ unsigned int mcf_getppdata(void) 48static __inline__ unsigned int mcf_getppdata(void)
49{ 49{
50 volatile unsigned short *pp; 50 volatile unsigned short *pp;
51 pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PADAT); 51 pp = (volatile unsigned short *) MCFSIM_PADAT;
52 return((unsigned int) *pp); 52 return((unsigned int) *pp);
53} 53}
54 54
55static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) 55static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits)
56{ 56{
57 volatile unsigned short *pp; 57 volatile unsigned short *pp;
58 pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PADAT); 58 pp = (volatile unsigned short *) MCFSIM_PADAT;
59 ppdata = (ppdata & ~mask) | bits; 59 ppdata = (ppdata & ~mask) | bits;
60 *pp = ppdata; 60 *pp = ppdata;
61} 61}
diff --git a/arch/m68k/include/asm/page_no.h b/arch/m68k/include/asm/page_no.h
index 9aa3f90f4855..1f31b060cc8d 100644
--- a/arch/m68k/include/asm/page_no.h
+++ b/arch/m68k/include/asm/page_no.h
@@ -1,10 +1,12 @@
1#ifndef _M68KNOMMU_PAGE_H 1#ifndef _M68KNOMMU_PAGE_H
2#define _M68KNOMMU_PAGE_H 2#define _M68KNOMMU_PAGE_H
3 3
4#include <linux/const.h>
5
4/* PAGE_SHIFT determines the page size */ 6/* PAGE_SHIFT determines the page size */
5 7
6#define PAGE_SHIFT (12) 8#define PAGE_SHIFT (12)
7#define PAGE_SIZE (1UL << PAGE_SHIFT) 9#define PAGE_SIZE (_AC(1,UL) << PAGE_SHIFT)
8#define PAGE_MASK (~(PAGE_SIZE-1)) 10#define PAGE_MASK (~(PAGE_SIZE-1))
9 11
10#include <asm/setup.h> 12#include <asm/setup.h>
diff --git a/arch/m68k/include/asm/pinmux.h b/arch/m68k/include/asm/pinmux.h
new file mode 100644
index 000000000000..119ee686dbd1
--- /dev/null
+++ b/arch/m68k/include/asm/pinmux.h
@@ -0,0 +1,30 @@
1/*
2 * Coldfire generic GPIO pinmux support.
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef pinmux_h
17#define pinmux_h
18
19#define MCFPINMUX_NONE -1
20
21extern int mcf_pinmux_request(unsigned, unsigned);
22extern void mcf_pinmux_release(unsigned, unsigned);
23
24static inline int mcf_pinmux_is_valid(unsigned pinmux)
25{
26 return pinmux != MCFPINMUX_NONE;
27}
28
29#endif
30
diff --git a/arch/m68k/include/asm/processor.h b/arch/m68k/include/asm/processor.h
index fc3f2c22f2b8..74fd674b15ad 100644
--- a/arch/m68k/include/asm/processor.h
+++ b/arch/m68k/include/asm/processor.h
@@ -1,5 +1,170 @@
1#ifdef __uClinux__ 1/*
2#include "processor_no.h" 2 * include/asm-m68k/processor.h
3 *
4 * Copyright (C) 1995 Hamish Macdonald
5 */
6
7#ifndef __ASM_M68K_PROCESSOR_H
8#define __ASM_M68K_PROCESSOR_H
9
10/*
11 * Default implementation of macro that returns current
12 * instruction pointer ("program counter").
13 */
14#define current_text_addr() ({ __label__ _l; _l: &&_l;})
15
16#include <linux/thread_info.h>
17#include <asm/segment.h>
18#include <asm/fpu.h>
19#include <asm/ptrace.h>
20
21static inline unsigned long rdusp(void)
22{
23#ifdef CONFIG_COLDFIRE
24 extern unsigned int sw_usp;
25 return sw_usp;
3#else 26#else
4#include "processor_mm.h" 27 unsigned long usp;
28 __asm__ __volatile__("move %/usp,%0" : "=a" (usp));
29 return usp;
30#endif
31}
32
33static inline void wrusp(unsigned long usp)
34{
35#ifdef CONFIG_COLDFIRE
36 extern unsigned int sw_usp;
37 sw_usp = usp;
38#else
39 __asm__ __volatile__("move %0,%/usp" : : "a" (usp));
40#endif
41}
42
43/*
44 * User space process size: 3.75GB. This is hardcoded into a few places,
45 * so don't change it unless you know what you are doing.
46 */
47#ifndef CONFIG_SUN3
48#define TASK_SIZE (0xF0000000UL)
49#else
50#define TASK_SIZE (0x0E000000UL)
51#endif
52
53#ifdef __KERNEL__
54#define STACK_TOP TASK_SIZE
55#define STACK_TOP_MAX STACK_TOP
56#endif
57
58/* This decides where the kernel will search for a free chunk of vm
59 * space during mmap's.
60 */
61#ifdef CONFIG_MMU
62#ifndef CONFIG_SUN3
63#define TASK_UNMAPPED_BASE 0xC0000000UL
64#else
65#define TASK_UNMAPPED_BASE 0x0A000000UL
66#endif
67#define TASK_UNMAPPED_ALIGN(addr, off) PAGE_ALIGN(addr)
68#else
69#define TASK_UNMAPPED_BASE 0
70#endif
71
72struct thread_struct {
73 unsigned long ksp; /* kernel stack pointer */
74 unsigned long usp; /* user stack pointer */
75 unsigned short sr; /* saved status register */
76 unsigned short fs; /* saved fs (sfc, dfc) */
77 unsigned long crp[2]; /* cpu root pointer */
78 unsigned long esp0; /* points to SR of stack frame */
79 unsigned long faddr; /* info about last fault */
80 int signo, code;
81 unsigned long fp[8*3];
82 unsigned long fpcntl[3]; /* fp control regs */
83 unsigned char fpstate[FPSTATESIZE]; /* floating point state */
84 struct thread_info info;
85};
86
87#define INIT_THREAD { \
88 .ksp = sizeof(init_stack) + (unsigned long) init_stack, \
89 .sr = PS_S, \
90 .fs = __KERNEL_DS, \
91 .info = INIT_THREAD_INFO(init_task), \
92}
93
94#ifdef CONFIG_MMU
95/*
96 * Do necessary setup to start up a newly executed thread.
97 */
98static inline void start_thread(struct pt_regs * regs, unsigned long pc,
99 unsigned long usp)
100{
101 /* reads from user space */
102 set_fs(USER_DS);
103
104 regs->pc = pc;
105 regs->sr &= ~0x2000;
106 wrusp(usp);
107}
108
109#else
110
111/*
112 * Coldfire stacks need to be re-aligned on trap exit, conventional
113 * 68k can handle this case cleanly.
114 */
115#ifdef CONFIG_COLDFIRE
116#define reformat(_regs) do { (_regs)->format = 0x4; } while(0)
117#else
118#define reformat(_regs) do { } while (0)
119#endif
120
121#define start_thread(_regs, _pc, _usp) \
122do { \
123 set_fs(USER_DS); /* reads from user space */ \
124 (_regs)->pc = (_pc); \
125 ((struct switch_stack *)(_regs))[-1].a6 = 0; \
126 reformat(_regs); \
127 if (current->mm) \
128 (_regs)->d5 = current->mm->start_data; \
129 (_regs)->sr &= ~0x2000; \
130 wrusp(_usp); \
131} while(0)
132
133#endif
134
135/* Forward declaration, a strange C thing */
136struct task_struct;
137
138/* Free all resources held by a thread. */
139static inline void release_thread(struct task_struct *dead_task)
140{
141}
142
143/* Prepare to copy thread state - unlazy all lazy status */
144#define prepare_to_copy(tsk) do { } while (0)
145
146extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
147
148/*
149 * Free current thread data structures etc..
150 */
151static inline void exit_thread(void)
152{
153}
154
155extern unsigned long thread_saved_pc(struct task_struct *tsk);
156
157unsigned long get_wchan(struct task_struct *p);
158
159#define KSTK_EIP(tsk) \
160 ({ \
161 unsigned long eip = 0; \
162 if ((tsk)->thread.esp0 > PAGE_SIZE && \
163 (virt_addr_valid((tsk)->thread.esp0))) \
164 eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
165 eip; })
166#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp)
167
168#define cpu_relax() barrier()
169
5#endif 170#endif
diff --git a/arch/m68k/include/asm/processor_mm.h b/arch/m68k/include/asm/processor_mm.h
deleted file mode 100644
index 1f61ef53f0e0..000000000000
--- a/arch/m68k/include/asm/processor_mm.h
+++ /dev/null
@@ -1,130 +0,0 @@
1/*
2 * include/asm-m68k/processor.h
3 *
4 * Copyright (C) 1995 Hamish Macdonald
5 */
6
7#ifndef __ASM_M68K_PROCESSOR_H
8#define __ASM_M68K_PROCESSOR_H
9
10/*
11 * Default implementation of macro that returns current
12 * instruction pointer ("program counter").
13 */
14#define current_text_addr() ({ __label__ _l; _l: &&_l;})
15
16#include <linux/thread_info.h>
17#include <asm/segment.h>
18#include <asm/fpu.h>
19#include <asm/ptrace.h>
20
21static inline unsigned long rdusp(void)
22{
23 unsigned long usp;
24
25 __asm__ __volatile__("move %/usp,%0" : "=a" (usp));
26 return usp;
27}
28
29static inline void wrusp(unsigned long usp)
30{
31 __asm__ __volatile__("move %0,%/usp" : : "a" (usp));
32}
33
34/*
35 * User space process size: 3.75GB. This is hardcoded into a few places,
36 * so don't change it unless you know what you are doing.
37 */
38#ifndef CONFIG_SUN3
39#define TASK_SIZE (0xF0000000UL)
40#else
41#define TASK_SIZE (0x0E000000UL)
42#endif
43
44#ifdef __KERNEL__
45#define STACK_TOP TASK_SIZE
46#define STACK_TOP_MAX STACK_TOP
47#endif
48
49/* This decides where the kernel will search for a free chunk of vm
50 * space during mmap's.
51 */
52#ifndef CONFIG_SUN3
53#define TASK_UNMAPPED_BASE 0xC0000000UL
54#else
55#define TASK_UNMAPPED_BASE 0x0A000000UL
56#endif
57#define TASK_UNMAPPED_ALIGN(addr, off) PAGE_ALIGN(addr)
58
59struct thread_struct {
60 unsigned long ksp; /* kernel stack pointer */
61 unsigned long usp; /* user stack pointer */
62 unsigned short sr; /* saved status register */
63 unsigned short fs; /* saved fs (sfc, dfc) */
64 unsigned long crp[2]; /* cpu root pointer */
65 unsigned long esp0; /* points to SR of stack frame */
66 unsigned long faddr; /* info about last fault */
67 int signo, code;
68 unsigned long fp[8*3];
69 unsigned long fpcntl[3]; /* fp control regs */
70 unsigned char fpstate[FPSTATESIZE]; /* floating point state */
71 struct thread_info info;
72};
73
74#define INIT_THREAD { \
75 .ksp = sizeof(init_stack) + (unsigned long) init_stack, \
76 .sr = PS_S, \
77 .fs = __KERNEL_DS, \
78 .info = INIT_THREAD_INFO(init_task), \
79}
80
81/*
82 * Do necessary setup to start up a newly executed thread.
83 */
84static inline void start_thread(struct pt_regs * regs, unsigned long pc,
85 unsigned long usp)
86{
87 /* reads from user space */
88 set_fs(USER_DS);
89
90 regs->pc = pc;
91 regs->sr &= ~0x2000;
92 wrusp(usp);
93}
94
95/* Forward declaration, a strange C thing */
96struct task_struct;
97
98/* Free all resources held by a thread. */
99static inline void release_thread(struct task_struct *dead_task)
100{
101}
102
103/* Prepare to copy thread state - unlazy all lazy status */
104#define prepare_to_copy(tsk) do { } while (0)
105
106extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
107
108/*
109 * Free current thread data structures etc..
110 */
111static inline void exit_thread(void)
112{
113}
114
115extern unsigned long thread_saved_pc(struct task_struct *tsk);
116
117unsigned long get_wchan(struct task_struct *p);
118
119#define KSTK_EIP(tsk) \
120 ({ \
121 unsigned long eip = 0; \
122 if ((tsk)->thread.esp0 > PAGE_SIZE && \
123 (virt_addr_valid((tsk)->thread.esp0))) \
124 eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
125 eip; })
126#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp)
127
128#define cpu_relax() barrier()
129
130#endif
diff --git a/arch/m68k/include/asm/processor_no.h b/arch/m68k/include/asm/processor_no.h
deleted file mode 100644
index 7a1e0ba35f5a..000000000000
--- a/arch/m68k/include/asm/processor_no.h
+++ /dev/null
@@ -1,143 +0,0 @@
1/*
2 * include/asm-m68knommu/processor.h
3 *
4 * Copyright (C) 1995 Hamish Macdonald
5 */
6
7#ifndef __ASM_M68K_PROCESSOR_H
8#define __ASM_M68K_PROCESSOR_H
9
10/*
11 * Default implementation of macro that returns current
12 * instruction pointer ("program counter").
13 */
14#define current_text_addr() ({ __label__ _l; _l: &&_l;})
15
16#include <linux/compiler.h>
17#include <linux/threads.h>
18#include <asm/types.h>
19#include <asm/segment.h>
20#include <asm/fpu.h>
21#include <asm/ptrace.h>
22#include <asm/current.h>
23
24static inline unsigned long rdusp(void)
25{
26#ifdef CONFIG_COLDFIRE
27 extern unsigned int sw_usp;
28 return(sw_usp);
29#else
30 unsigned long usp;
31 __asm__ __volatile__("move %/usp,%0" : "=a" (usp));
32 return usp;
33#endif
34}
35
36static inline void wrusp(unsigned long usp)
37{
38#ifdef CONFIG_COLDFIRE
39 extern unsigned int sw_usp;
40 sw_usp = usp;
41#else
42 __asm__ __volatile__("move %0,%/usp" : : "a" (usp));
43#endif
44}
45
46/*
47 * User space process size: 3.75GB. This is hardcoded into a few places,
48 * so don't change it unless you know what you are doing.
49 */
50#define TASK_SIZE (0xF0000000UL)
51
52/*
53 * This decides where the kernel will search for a free chunk of vm
54 * space during mmap's. We won't be using it
55 */
56#define TASK_UNMAPPED_BASE 0
57
58/*
59 * if you change this structure, you must change the code and offsets
60 * in m68k/machasm.S
61 */
62
63struct thread_struct {
64 unsigned long ksp; /* kernel stack pointer */
65 unsigned long usp; /* user stack pointer */
66 unsigned short sr; /* saved status register */
67 unsigned short fs; /* saved fs (sfc, dfc) */
68 unsigned long crp[2]; /* cpu root pointer */
69 unsigned long esp0; /* points to SR of stack frame */
70 unsigned long fp[8*3];
71 unsigned long fpcntl[3]; /* fp control regs */
72 unsigned char fpstate[FPSTATESIZE]; /* floating point state */
73};
74
75#define INIT_THREAD { \
76 .ksp = sizeof(init_stack) + (unsigned long) init_stack, \
77 .sr = PS_S, \
78 .fs = __KERNEL_DS, \
79}
80
81/*
82 * Coldfire stacks need to be re-aligned on trap exit, conventional
83 * 68k can handle this case cleanly.
84 */
85#if defined(CONFIG_COLDFIRE)
86#define reformat(_regs) do { (_regs)->format = 0x4; } while(0)
87#else
88#define reformat(_regs) do { } while (0)
89#endif
90
91/*
92 * Do necessary setup to start up a newly executed thread.
93 *
94 * pass the data segment into user programs if it exists,
95 * it can't hurt anything as far as I can tell
96 */
97#define start_thread(_regs, _pc, _usp) \
98do { \
99 set_fs(USER_DS); /* reads from user space */ \
100 (_regs)->pc = (_pc); \
101 ((struct switch_stack *)(_regs))[-1].a6 = 0; \
102 reformat(_regs); \
103 if (current->mm) \
104 (_regs)->d5 = current->mm->start_data; \
105 (_regs)->sr &= ~0x2000; \
106 wrusp(_usp); \
107} while(0)
108
109/* Forward declaration, a strange C thing */
110struct task_struct;
111
112/* Free all resources held by a thread. */
113static inline void release_thread(struct task_struct *dead_task)
114{
115}
116
117/* Prepare to copy thread state - unlazy all lazy status */
118#define prepare_to_copy(tsk) do { } while (0)
119
120extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
121
122/*
123 * Free current thread data structures etc..
124 */
125static inline void exit_thread(void)
126{
127}
128
129unsigned long thread_saved_pc(struct task_struct *tsk);
130unsigned long get_wchan(struct task_struct *p);
131
132#define KSTK_EIP(tsk) \
133 ({ \
134 unsigned long eip = 0; \
135 if ((tsk)->thread.esp0 > PAGE_SIZE && \
136 (virt_addr_valid((tsk)->thread.esp0))) \
137 eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
138 eip; })
139#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp)
140
141#define cpu_relax() barrier()
142
143#endif
diff --git a/arch/m68k/include/asm/timex.h b/arch/m68k/include/asm/timex.h
index b87f2f278f67..6759dad954f6 100644
--- a/arch/m68k/include/asm/timex.h
+++ b/arch/m68k/include/asm/timex.h
@@ -3,10 +3,23 @@
3 * 3 *
4 * m68k architecture timex specifications 4 * m68k architecture timex specifications
5 */ 5 */
6#ifndef _ASMm68k_TIMEX_H 6#ifndef _ASMm68K_TIMEX_H
7#define _ASMm68k_TIMEX_H 7#define _ASMm68K_TIMEX_H
8 8
9#ifdef CONFIG_COLDFIRE
10/*
11 * CLOCK_TICK_RATE should give the underlying frequency of the tick timer
12 * to make ntp work best. For Coldfires, that's the main clock.
13 */
14#include <asm/coldfire.h>
15#define CLOCK_TICK_RATE MCF_CLK
16#else
17/*
18 * This default CLOCK_TICK_RATE is probably wrong for many 68k boards
19 * Users of those boards will need to check and modify accordingly
20 */
9#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */ 21#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */
22#endif
10 23
11typedef unsigned long cycles_t; 24typedef unsigned long cycles_t;
12 25
diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig
index 534376299a99..e2201b90aa22 100644
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -47,6 +47,10 @@ config GENERIC_FIND_NEXT_BIT
47 bool 47 bool
48 default y 48 default y
49 49
50config GENERIC_GPIO
51 bool
52 default n
53
50config GENERIC_HWEIGHT 54config GENERIC_HWEIGHT
51 bool 55 bool
52 default y 56 default y
@@ -182,6 +186,8 @@ config M527x
182config COLDFIRE 186config COLDFIRE
183 bool 187 bool
184 depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407) 188 depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407)
189 select GENERIC_GPIO
190 select ARCH_REQUIRE_GPIOLIB
185 default y 191 default y
186 192
187config CLOCK_SET 193config CLOCK_SET
diff --git a/arch/m68knommu/kernel/irq.c b/arch/m68knommu/kernel/irq.c
index 56e0f4c55a67..c9cac36d4422 100644
--- a/arch/m68knommu/kernel/irq.c
+++ b/arch/m68knommu/kernel/irq.c
@@ -29,32 +29,6 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
29 set_irq_regs(oldregs); 29 set_irq_regs(oldregs);
30} 30}
31 31
32void ack_bad_irq(unsigned int irq)
33{
34 printk(KERN_ERR "IRQ: unexpected irq=%d\n", irq);
35}
36
37static struct irq_chip m_irq_chip = {
38 .name = "M68K-INTC",
39 .enable = enable_vector,
40 .disable = disable_vector,
41 .ack = ack_vector,
42};
43
44void __init init_IRQ(void)
45{
46 int irq;
47
48 init_vectors();
49
50 for (irq = 0; (irq < NR_IRQS); irq++) {
51 irq_desc[irq].status = IRQ_DISABLED;
52 irq_desc[irq].action = NULL;
53 irq_desc[irq].depth = 1;
54 irq_desc[irq].chip = &m_irq_chip;
55 }
56}
57
58int show_interrupts(struct seq_file *p, void *v) 32int show_interrupts(struct seq_file *p, void *v)
59{ 33{
60 struct irqaction *ap; 34 struct irqaction *ap;
diff --git a/arch/m68knommu/kernel/time.c b/arch/m68knommu/kernel/time.c
index d182b2f72211..c2aa717de08a 100644
--- a/arch/m68knommu/kernel/time.c
+++ b/arch/m68knommu/kernel/time.c
@@ -69,7 +69,7 @@ static unsigned long read_rtc_mmss(void)
69 if ((year += 1900) < 1970) 69 if ((year += 1900) < 1970)
70 year += 100; 70 year += 100;
71 71
72 return mktime(year, mon, day, hour, min, sec);; 72 return mktime(year, mon, day, hour, min, sec);
73} 73}
74 74
75unsigned long read_persistent_clock(void) 75unsigned long read_persistent_clock(void)
diff --git a/arch/m68knommu/lib/checksum.c b/arch/m68knommu/lib/checksum.c
index 269d83bfbbe1..eccf25d3d73e 100644
--- a/arch/m68knommu/lib/checksum.c
+++ b/arch/m68knommu/lib/checksum.c
@@ -92,6 +92,7 @@ out:
92 return result; 92 return result;
93} 93}
94 94
95#ifdef CONFIG_COLDFIRE
95/* 96/*
96 * This is a version of ip_compute_csum() optimized for IP headers, 97 * This is a version of ip_compute_csum() optimized for IP headers,
97 * which always checksum on 4 octet boundaries. 98 * which always checksum on 4 octet boundaries.
@@ -100,6 +101,7 @@ __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
100{ 101{
101 return (__force __sum16)~do_csum(iph,ihl*4); 102 return (__force __sum16)~do_csum(iph,ihl*4);
102} 103}
104#endif
103 105
104/* 106/*
105 * computes the checksum of a memory block at buff, length len, 107 * computes the checksum of a memory block at buff, length len,
@@ -127,15 +129,6 @@ __wsum csum_partial(const void *buff, int len, __wsum sum)
127EXPORT_SYMBOL(csum_partial); 129EXPORT_SYMBOL(csum_partial);
128 130
129/* 131/*
130 * this routine is used for miscellaneous IP-like checksums, mainly
131 * in icmp.c
132 */
133__sum16 ip_compute_csum(const void *buff, int len)
134{
135 return (__force __sum16)~do_csum(buff,len);
136}
137
138/*
139 * copy from fs while checksumming, otherwise like csum_partial 132 * copy from fs while checksumming, otherwise like csum_partial
140 */ 133 */
141 134
diff --git a/arch/m68knommu/platform/5206/Makefile b/arch/m68knommu/platform/5206/Makefile
index a439d9ab3f27..113c33390064 100644
--- a/arch/m68knommu/platform/5206/Makefile
+++ b/arch/m68knommu/platform/5206/Makefile
@@ -14,5 +14,5 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o
18 18
diff --git a/arch/m68knommu/platform/5206/config.c b/arch/m68knommu/platform/5206/config.c
index f6f79874e9af..9c335465e66d 100644
--- a/arch/m68knommu/platform/5206/config.c
+++ b/arch/m68knommu/platform/5206/config.c
@@ -49,11 +49,11 @@ static void __init m5206_uart_init_line(int line, int irq)
49 if (line == 0) { 49 if (line == 0) {
50 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 50 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
51 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR); 51 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
52 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); 52 mcf_mapirq2imr(irq, MCFINTC_UART0);
53 } else if (line == 1) { 53 } else if (line == 1) {
54 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 54 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
55 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR); 55 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
56 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); 56 mcf_mapirq2imr(irq, MCFINTC_UART1);
57 } 57 }
58} 58}
59 59
@@ -68,38 +68,19 @@ static void __init m5206_uarts_init(void)
68 68
69/***************************************************************************/ 69/***************************************************************************/
70 70
71void mcf_autovector(unsigned int vec) 71static void __init m5206_timers_init(void)
72{ 72{
73 volatile unsigned char *mbar; 73 /* Timer1 is always used as system timer */
74 unsigned char icr; 74 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
75 75 MCF_MBAR + MCFSIM_TIMER1ICR);
76 if ((vec >= 25) && (vec <= 31)) { 76 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
77 vec -= 25; 77
78 mbar = (volatile unsigned char *) MCF_MBAR; 78#ifdef CONFIG_HIGHPROFILE
79 icr = MCFSIM_ICR_AUTOVEC | (vec << 3); 79 /* Timer2 is to be used as a high speed profile timer */
80 *(mbar + MCFSIM_ICR1 + vec) = icr; 80 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
81 vec = 0x1 << (vec + 1); 81 MCF_MBAR + MCFSIM_TIMER2ICR);
82 mcf_setimr(mcf_getimr() & ~vec); 82 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
83 } 83#endif
84}
85
86/***************************************************************************/
87
88void mcf_settimericr(unsigned int timer, unsigned int level)
89{
90 volatile unsigned char *icrp;
91 unsigned int icr, imr;
92
93 if (timer <= 2) {
94 switch (timer) {
95 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
96 default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
97 }
98
99 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
100 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
101 mcf_setimr(mcf_getimr() & ~imr);
102 }
103} 84}
104 85
105/***************************************************************************/ 86/***************************************************************************/
@@ -117,15 +98,20 @@ void m5206_cpu_reset(void)
117 98
118void __init config_BSP(char *commandp, int size) 99void __init config_BSP(char *commandp, int size)
119{ 100{
120 mcf_setimr(MCFSIM_IMR_MASKALL);
121 mach_reset = m5206_cpu_reset; 101 mach_reset = m5206_cpu_reset;
102 m5206_timers_init();
103 m5206_uarts_init();
104
105 /* Only support the external interrupts on their primary level */
106 mcf_mapirq2imr(25, MCFINTC_EINT1);
107 mcf_mapirq2imr(28, MCFINTC_EINT4);
108 mcf_mapirq2imr(31, MCFINTC_EINT7);
122} 109}
123 110
124/***************************************************************************/ 111/***************************************************************************/
125 112
126static int __init init_BSP(void) 113static int __init init_BSP(void)
127{ 114{
128 m5206_uarts_init();
129 platform_add_devices(m5206_devices, ARRAY_SIZE(m5206_devices)); 115 platform_add_devices(m5206_devices, ARRAY_SIZE(m5206_devices));
130 return 0; 116 return 0;
131} 117}
diff --git a/arch/m68knommu/platform/5206/gpio.c b/arch/m68knommu/platform/5206/gpio.c
new file mode 100644
index 000000000000..60f779ce1651
--- /dev/null
+++ b/arch/m68knommu/platform/5206/gpio.c
@@ -0,0 +1,49 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PP",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = MCFSIM_PADDR,
36 .podr = MCFSIM_PADAT,
37 .ppdr = MCFSIM_PADAT,
38 },
39};
40
41static int __init mcf_gpio_init(void)
42{
43 unsigned i = 0;
44 while (i < ARRAY_SIZE(mcf_gpio_chips))
45 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
46 return 0;
47}
48
49core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/5206e/Makefile b/arch/m68knommu/platform/5206e/Makefile
index a439d9ab3f27..113c33390064 100644
--- a/arch/m68knommu/platform/5206e/Makefile
+++ b/arch/m68knommu/platform/5206e/Makefile
@@ -14,5 +14,5 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o
18 18
diff --git a/arch/m68knommu/platform/5206e/config.c b/arch/m68knommu/platform/5206e/config.c
index 65887799db81..0f41ba82a3b5 100644
--- a/arch/m68knommu/platform/5206e/config.c
+++ b/arch/m68knommu/platform/5206e/config.c
@@ -15,6 +15,7 @@
15#include <asm/machdep.h> 15#include <asm/machdep.h>
16#include <asm/coldfire.h> 16#include <asm/coldfire.h>
17#include <asm/mcfsim.h> 17#include <asm/mcfsim.h>
18#include <asm/mcfuart.h>
18#include <asm/mcfdma.h> 19#include <asm/mcfdma.h>
19#include <asm/mcfuart.h> 20#include <asm/mcfuart.h>
20 21
@@ -49,11 +50,11 @@ static void __init m5206e_uart_init_line(int line, int irq)
49 if (line == 0) { 50 if (line == 0) {
50 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 51 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
51 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR); 52 writeb(irq, MCFUART_BASE1 + MCFUART_UIVR);
52 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); 53 mcf_mapirq2imr(irq, MCFINTC_UART0);
53 } else if (line == 1) { 54 } else if (line == 1) {
54 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 55 writel(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
55 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR); 56 writeb(irq, MCFUART_BASE2 + MCFUART_UIVR);
56 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); 57 mcf_mapirq2imr(irq, MCFINTC_UART1);
57 } 58 }
58} 59}
59 60
@@ -68,38 +69,19 @@ static void __init m5206e_uarts_init(void)
68 69
69/***************************************************************************/ 70/***************************************************************************/
70 71
71void mcf_autovector(unsigned int vec) 72static void __init m5206e_timers_init(void)
72{
73 volatile unsigned char *mbar;
74 unsigned char icr;
75
76 if ((vec >= 25) && (vec <= 31)) {
77 vec -= 25;
78 mbar = (volatile unsigned char *) MCF_MBAR;
79 icr = MCFSIM_ICR_AUTOVEC | (vec << 3);
80 *(mbar + MCFSIM_ICR1 + vec) = icr;
81 vec = 0x1 << (vec + 1);
82 mcf_setimr(mcf_getimr() & ~vec);
83 }
84}
85
86/***************************************************************************/
87
88void mcf_settimericr(unsigned int timer, unsigned int level)
89{ 73{
90 volatile unsigned char *icrp; 74 /* Timer1 is always used as system timer */
91 unsigned int icr, imr; 75 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
92 76 MCF_MBAR + MCFSIM_TIMER1ICR);
93 if (timer <= 2) { 77 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
94 switch (timer) { 78
95 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break; 79#ifdef CONFIG_HIGHPROFILE
96 default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break; 80 /* Timer2 is to be used as a high speed profile timer */
97 } 81 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
98 82 MCF_MBAR + MCFSIM_TIMER2ICR);
99 icrp = (volatile unsigned char *) (MCF_MBAR + icr); 83 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
100 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3; 84#endif
101 mcf_setimr(mcf_getimr() & ~imr);
102 }
103} 85}
104 86
105/***************************************************************************/ 87/***************************************************************************/
@@ -117,8 +99,6 @@ void m5206e_cpu_reset(void)
117 99
118void __init config_BSP(char *commandp, int size) 100void __init config_BSP(char *commandp, int size)
119{ 101{
120 mcf_setimr(MCFSIM_IMR_MASKALL);
121
122#if defined(CONFIG_NETtel) 102#if defined(CONFIG_NETtel)
123 /* Copy command line from FLASH to local buffer... */ 103 /* Copy command line from FLASH to local buffer... */
124 memcpy(commandp, (char *) 0xf0004000, size); 104 memcpy(commandp, (char *) 0xf0004000, size);
@@ -126,13 +106,19 @@ void __init config_BSP(char *commandp, int size)
126#endif /* CONFIG_NETtel */ 106#endif /* CONFIG_NETtel */
127 107
128 mach_reset = m5206e_cpu_reset; 108 mach_reset = m5206e_cpu_reset;
109 m5206e_timers_init();
110 m5206e_uarts_init();
111
112 /* Only support the external interrupts on their primary level */
113 mcf_mapirq2imr(25, MCFINTC_EINT1);
114 mcf_mapirq2imr(28, MCFINTC_EINT4);
115 mcf_mapirq2imr(31, MCFINTC_EINT7);
129} 116}
130 117
131/***************************************************************************/ 118/***************************************************************************/
132 119
133static int __init init_BSP(void) 120static int __init init_BSP(void)
134{ 121{
135 m5206e_uarts_init();
136 platform_add_devices(m5206e_devices, ARRAY_SIZE(m5206e_devices)); 122 platform_add_devices(m5206e_devices, ARRAY_SIZE(m5206e_devices));
137 return 0; 123 return 0;
138} 124}
diff --git a/arch/m68knommu/platform/5206e/gpio.c b/arch/m68knommu/platform/5206e/gpio.c
new file mode 100644
index 000000000000..60f779ce1651
--- /dev/null
+++ b/arch/m68knommu/platform/5206e/gpio.c
@@ -0,0 +1,49 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PP",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = MCFSIM_PADDR,
36 .podr = MCFSIM_PADAT,
37 .ppdr = MCFSIM_PADAT,
38 },
39};
40
41static int __init mcf_gpio_init(void)
42{
43 unsigned i = 0;
44 while (i < ARRAY_SIZE(mcf_gpio_chips))
45 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
46 return 0;
47}
48
49core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/520x/Makefile b/arch/m68knommu/platform/520x/Makefile
index a50e76acc8fd..435ab3483dc1 100644
--- a/arch/m68knommu/platform/520x/Makefile
+++ b/arch/m68knommu/platform/520x/Makefile
@@ -14,4 +14,4 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o
diff --git a/arch/m68knommu/platform/520x/config.c b/arch/m68knommu/platform/520x/config.c
index 1c43a8aec69b..92614de42cd3 100644
--- a/arch/m68knommu/platform/520x/config.c
+++ b/arch/m68knommu/platform/520x/config.c
@@ -81,20 +81,11 @@ static struct platform_device *m520x_devices[] __initdata = {
81 81
82/***************************************************************************/ 82/***************************************************************************/
83 83
84#define INTC0 (MCF_MBAR + MCFICM_INTC0)
85
86static void __init m520x_uart_init_line(int line, int irq) 84static void __init m520x_uart_init_line(int line, int irq)
87{ 85{
88 u32 imr;
89 u16 par; 86 u16 par;
90 u8 par2; 87 u8 par2;
91 88
92 writeb(0x03, INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + line);
93
94 imr = readl(INTC0 + MCFINTC_IMRL);
95 imr &= ~((1 << (irq - MCFINT_VECBASE)) | 1);
96 writel(imr, INTC0 + MCFINTC_IMRL);
97
98 switch (line) { 89 switch (line) {
99 case 0: 90 case 0:
100 par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART); 91 par = readw(MCF_IPSBAR + MCF_GPIO_PAR_UART);
@@ -131,18 +122,8 @@ static void __init m520x_uarts_init(void)
131 122
132static void __init m520x_fec_init(void) 123static void __init m520x_fec_init(void)
133{ 124{
134 u32 imr;
135 u8 v; 125 u8 v;
136 126
137 /* Unmask FEC interrupts at ColdFire interrupt controller */
138 writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 36);
139 writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 40);
140 writeb(0x4, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 42);
141
142 imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
143 imr &= ~0x0001FFF0;
144 writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
145
146 /* Set multi-function pins to ethernet mode */ 127 /* Set multi-function pins to ethernet mode */
147 v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FEC); 128 v = readb(MCF_IPSBAR + MCF_GPIO_PAR_FEC);
148 writeb(v | 0xf0, MCF_IPSBAR + MCF_GPIO_PAR_FEC); 129 writeb(v | 0xf0, MCF_IPSBAR + MCF_GPIO_PAR_FEC);
@@ -153,17 +134,6 @@ static void __init m520x_fec_init(void)
153 134
154/***************************************************************************/ 135/***************************************************************************/
155 136
156/*
157 * Program the vector to be an auto-vectored.
158 */
159
160void mcf_autovector(unsigned int vec)
161{
162 /* Everything is auto-vectored on the 520x devices */
163}
164
165/***************************************************************************/
166
167static void m520x_cpu_reset(void) 137static void m520x_cpu_reset(void)
168{ 138{
169 local_irq_disable(); 139 local_irq_disable();
diff --git a/arch/m68knommu/platform/520x/gpio.c b/arch/m68knommu/platform/520x/gpio.c
new file mode 100644
index 000000000000..15b5bb62a698
--- /dev/null
+++ b/arch/m68knommu/platform/520x/gpio.c
@@ -0,0 +1,211 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PIRQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = MCFEPORT_EPDDR,
36 .podr = MCFEPORT_EPDR,
37 .ppdr = MCFEPORT_EPPDR,
38 },
39 {
40 .gpio_chip = {
41 .label = "BUSCTL",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value_fast,
48 .base = 8,
49 .ngpio = 4,
50 },
51 .pddr = MCFGPIO_PDDR_BUSCTL,
52 .podr = MCFGPIO_PODR_BUSCTL,
53 .ppdr = MCFGPIO_PPDSDR_BUSCTL,
54 .setr = MCFGPIO_PPDSDR_BUSCTL,
55 .clrr = MCFGPIO_PCLRR_BUSCTL,
56 },
57 {
58 .gpio_chip = {
59 .label = "BE",
60 .request = mcf_gpio_request,
61 .free = mcf_gpio_free,
62 .direction_input = mcf_gpio_direction_input,
63 .direction_output = mcf_gpio_direction_output,
64 .get = mcf_gpio_get_value,
65 .set = mcf_gpio_set_value_fast,
66 .base = 16,
67 .ngpio = 4,
68 },
69 .pddr = MCFGPIO_PDDR_BE,
70 .podr = MCFGPIO_PODR_BE,
71 .ppdr = MCFGPIO_PPDSDR_BE,
72 .setr = MCFGPIO_PPDSDR_BE,
73 .clrr = MCFGPIO_PCLRR_BE,
74 },
75 {
76 .gpio_chip = {
77 .label = "CS",
78 .request = mcf_gpio_request,
79 .free = mcf_gpio_free,
80 .direction_input = mcf_gpio_direction_input,
81 .direction_output = mcf_gpio_direction_output,
82 .get = mcf_gpio_get_value,
83 .set = mcf_gpio_set_value_fast,
84 .base = 25,
85 .ngpio = 3,
86 },
87 .pddr = MCFGPIO_PDDR_CS,
88 .podr = MCFGPIO_PODR_CS,
89 .ppdr = MCFGPIO_PPDSDR_CS,
90 .setr = MCFGPIO_PPDSDR_CS,
91 .clrr = MCFGPIO_PCLRR_CS,
92 },
93 {
94 .gpio_chip = {
95 .label = "FECI2C",
96 .request = mcf_gpio_request,
97 .free = mcf_gpio_free,
98 .direction_input = mcf_gpio_direction_input,
99 .direction_output = mcf_gpio_direction_output,
100 .get = mcf_gpio_get_value,
101 .set = mcf_gpio_set_value_fast,
102 .base = 32,
103 .ngpio = 4,
104 },
105 .pddr = MCFGPIO_PDDR_FECI2C,
106 .podr = MCFGPIO_PODR_FECI2C,
107 .ppdr = MCFGPIO_PPDSDR_FECI2C,
108 .setr = MCFGPIO_PPDSDR_FECI2C,
109 .clrr = MCFGPIO_PCLRR_FECI2C,
110 },
111 {
112 .gpio_chip = {
113 .label = "QSPI",
114 .request = mcf_gpio_request,
115 .free = mcf_gpio_free,
116 .direction_input = mcf_gpio_direction_input,
117 .direction_output = mcf_gpio_direction_output,
118 .get = mcf_gpio_get_value,
119 .set = mcf_gpio_set_value_fast,
120 .base = 40,
121 .ngpio = 4,
122 },
123 .pddr = MCFGPIO_PDDR_QSPI,
124 .podr = MCFGPIO_PODR_QSPI,
125 .ppdr = MCFGPIO_PPDSDR_QSPI,
126 .setr = MCFGPIO_PPDSDR_QSPI,
127 .clrr = MCFGPIO_PCLRR_QSPI,
128 },
129 {
130 .gpio_chip = {
131 .label = "TIMER",
132 .request = mcf_gpio_request,
133 .free = mcf_gpio_free,
134 .direction_input = mcf_gpio_direction_input,
135 .direction_output = mcf_gpio_direction_output,
136 .get = mcf_gpio_get_value,
137 .set = mcf_gpio_set_value_fast,
138 .base = 48,
139 .ngpio = 4,
140 },
141 .pddr = MCFGPIO_PDDR_TIMER,
142 .podr = MCFGPIO_PODR_TIMER,
143 .ppdr = MCFGPIO_PPDSDR_TIMER,
144 .setr = MCFGPIO_PPDSDR_TIMER,
145 .clrr = MCFGPIO_PCLRR_TIMER,
146 },
147 {
148 .gpio_chip = {
149 .label = "UART",
150 .request = mcf_gpio_request,
151 .free = mcf_gpio_free,
152 .direction_input = mcf_gpio_direction_input,
153 .direction_output = mcf_gpio_direction_output,
154 .get = mcf_gpio_get_value,
155 .set = mcf_gpio_set_value_fast,
156 .base = 56,
157 .ngpio = 8,
158 },
159 .pddr = MCFGPIO_PDDR_UART,
160 .podr = MCFGPIO_PODR_UART,
161 .ppdr = MCFGPIO_PPDSDR_UART,
162 .setr = MCFGPIO_PPDSDR_UART,
163 .clrr = MCFGPIO_PCLRR_UART,
164 },
165 {
166 .gpio_chip = {
167 .label = "FECH",
168 .request = mcf_gpio_request,
169 .free = mcf_gpio_free,
170 .direction_input = mcf_gpio_direction_input,
171 .direction_output = mcf_gpio_direction_output,
172 .get = mcf_gpio_get_value,
173 .set = mcf_gpio_set_value_fast,
174 .base = 64,
175 .ngpio = 8,
176 },
177 .pddr = MCFGPIO_PDDR_FECH,
178 .podr = MCFGPIO_PODR_FECH,
179 .ppdr = MCFGPIO_PPDSDR_FECH,
180 .setr = MCFGPIO_PPDSDR_FECH,
181 .clrr = MCFGPIO_PCLRR_FECH,
182 },
183 {
184 .gpio_chip = {
185 .label = "FECL",
186 .request = mcf_gpio_request,
187 .free = mcf_gpio_free,
188 .direction_input = mcf_gpio_direction_input,
189 .direction_output = mcf_gpio_direction_output,
190 .get = mcf_gpio_get_value,
191 .set = mcf_gpio_set_value_fast,
192 .base = 72,
193 .ngpio = 8,
194 },
195 .pddr = MCFGPIO_PDDR_FECL,
196 .podr = MCFGPIO_PODR_FECL,
197 .ppdr = MCFGPIO_PPDSDR_FECL,
198 .setr = MCFGPIO_PPDSDR_FECL,
199 .clrr = MCFGPIO_PCLRR_FECL,
200 },
201};
202
203static int __init mcf_gpio_init(void)
204{
205 unsigned i = 0;
206 while (i < ARRAY_SIZE(mcf_gpio_chips))
207 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
208 return 0;
209}
210
211core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/523x/Makefile b/arch/m68knommu/platform/523x/Makefile
index 5694d593f029..b8f9b45440c2 100644
--- a/arch/m68knommu/platform/523x/Makefile
+++ b/arch/m68knommu/platform/523x/Makefile
@@ -14,4 +14,4 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o
diff --git a/arch/m68knommu/platform/523x/config.c b/arch/m68knommu/platform/523x/config.c
index 961fefebca14..6ba84f2aa397 100644
--- a/arch/m68knommu/platform/523x/config.c
+++ b/arch/m68knommu/platform/523x/config.c
@@ -82,66 +82,20 @@ static struct platform_device *m523x_devices[] __initdata = {
82 82
83/***************************************************************************/ 83/***************************************************************************/
84 84
85#define INTC0 (MCF_MBAR + MCFICM_INTC0)
86
87static void __init m523x_uart_init_line(int line, int irq)
88{
89 u32 imr;
90
91 if ((line < 0) || (line > 2))
92 return;
93
94 writeb(0x30+line, (INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + line));
95
96 imr = readl(INTC0 + MCFINTC_IMRL);
97 imr &= ~((1 << (irq - MCFINT_VECBASE)) | 1);
98 writel(imr, INTC0 + MCFINTC_IMRL);
99}
100
101static void __init m523x_uarts_init(void)
102{
103 const int nrlines = ARRAY_SIZE(m523x_uart_platform);
104 int line;
105
106 for (line = 0; (line < nrlines); line++)
107 m523x_uart_init_line(line, m523x_uart_platform[line].irq);
108}
109
110/***************************************************************************/
111
112static void __init m523x_fec_init(void) 85static void __init m523x_fec_init(void)
113{ 86{
114 u32 imr; 87 u16 par;
115 88 u8 v;
116 /* Unmask FEC interrupts at ColdFire interrupt controller */ 89
117 writeb(0x28, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 23); 90 /* Set multi-function pins to ethernet use */
118 writeb(0x27, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 27); 91 par = readw(MCF_IPSBAR + 0x100082);
119 writeb(0x26, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 29); 92 writew(par | 0xf00, MCF_IPSBAR + 0x100082);
120 93 v = readb(MCF_IPSBAR + 0x100078);
121 imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH); 94 writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
122 imr &= ~0xf;
123 writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
124 imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
125 imr &= ~0xff800001;
126 writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
127}
128
129/***************************************************************************/
130
131void mcf_disableall(void)
132{
133 *((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH)) = 0xffffffff;
134 *((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL)) = 0xffffffff;
135} 95}
136 96
137/***************************************************************************/ 97/***************************************************************************/
138 98
139void mcf_autovector(unsigned int vec)
140{
141 /* Everything is auto-vectored on the 523x */
142}
143/***************************************************************************/
144
145static void m523x_cpu_reset(void) 99static void m523x_cpu_reset(void)
146{ 100{
147 local_irq_disable(); 101 local_irq_disable();
@@ -152,16 +106,14 @@ static void m523x_cpu_reset(void)
152 106
153void __init config_BSP(char *commandp, int size) 107void __init config_BSP(char *commandp, int size)
154{ 108{
155 mcf_disableall();
156 mach_reset = m523x_cpu_reset; 109 mach_reset = m523x_cpu_reset;
157 m523x_uarts_init();
158 m523x_fec_init();
159} 110}
160 111
161/***************************************************************************/ 112/***************************************************************************/
162 113
163static int __init init_BSP(void) 114static int __init init_BSP(void)
164{ 115{
116 m523x_fec_init();
165 platform_add_devices(m523x_devices, ARRAY_SIZE(m523x_devices)); 117 platform_add_devices(m523x_devices, ARRAY_SIZE(m523x_devices));
166 return 0; 118 return 0;
167} 119}
diff --git a/arch/m68knommu/platform/523x/gpio.c b/arch/m68knommu/platform/523x/gpio.c
new file mode 100644
index 000000000000..f02840d54d3c
--- /dev/null
+++ b/arch/m68knommu/platform/523x/gpio.c
@@ -0,0 +1,283 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PIRQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = MCFEPORT_EPDDR,
36 .podr = MCFEPORT_EPDR,
37 .ppdr = MCFEPORT_EPPDR,
38 },
39 {
40 .gpio_chip = {
41 .label = "ADDR",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value_fast,
48 .base = 13,
49 .ngpio = 3,
50 },
51 .pddr = MCFGPIO_PDDR_ADDR,
52 .podr = MCFGPIO_PODR_ADDR,
53 .ppdr = MCFGPIO_PPDSDR_ADDR,
54 .setr = MCFGPIO_PPDSDR_ADDR,
55 .clrr = MCFGPIO_PCLRR_ADDR,
56 },
57 {
58 .gpio_chip = {
59 .label = "DATAH",
60 .request = mcf_gpio_request,
61 .free = mcf_gpio_free,
62 .direction_input = mcf_gpio_direction_input,
63 .direction_output = mcf_gpio_direction_output,
64 .get = mcf_gpio_get_value,
65 .set = mcf_gpio_set_value_fast,
66 .base = 16,
67 .ngpio = 8,
68 },
69 .pddr = MCFGPIO_PDDR_DATAH,
70 .podr = MCFGPIO_PODR_DATAH,
71 .ppdr = MCFGPIO_PPDSDR_DATAH,
72 .setr = MCFGPIO_PPDSDR_DATAH,
73 .clrr = MCFGPIO_PCLRR_DATAH,
74 },
75 {
76 .gpio_chip = {
77 .label = "DATAL",
78 .request = mcf_gpio_request,
79 .free = mcf_gpio_free,
80 .direction_input = mcf_gpio_direction_input,
81 .direction_output = mcf_gpio_direction_output,
82 .get = mcf_gpio_get_value,
83 .set = mcf_gpio_set_value_fast,
84 .base = 24,
85 .ngpio = 8,
86 },
87 .pddr = MCFGPIO_PDDR_DATAL,
88 .podr = MCFGPIO_PODR_DATAL,
89 .ppdr = MCFGPIO_PPDSDR_DATAL,
90 .setr = MCFGPIO_PPDSDR_DATAL,
91 .clrr = MCFGPIO_PCLRR_DATAL,
92 },
93 {
94 .gpio_chip = {
95 .label = "BUSCTL",
96 .request = mcf_gpio_request,
97 .free = mcf_gpio_free,
98 .direction_input = mcf_gpio_direction_input,
99 .direction_output = mcf_gpio_direction_output,
100 .get = mcf_gpio_get_value,
101 .set = mcf_gpio_set_value_fast,
102 .base = 32,
103 .ngpio = 8,
104 },
105 .pddr = MCFGPIO_PDDR_BUSCTL,
106 .podr = MCFGPIO_PODR_BUSCTL,
107 .ppdr = MCFGPIO_PPDSDR_BUSCTL,
108 .setr = MCFGPIO_PPDSDR_BUSCTL,
109 .clrr = MCFGPIO_PCLRR_BUSCTL,
110 },
111 {
112 .gpio_chip = {
113 .label = "BS",
114 .request = mcf_gpio_request,
115 .free = mcf_gpio_free,
116 .direction_input = mcf_gpio_direction_input,
117 .direction_output = mcf_gpio_direction_output,
118 .get = mcf_gpio_get_value,
119 .set = mcf_gpio_set_value_fast,
120 .base = 40,
121 .ngpio = 4,
122 },
123 .pddr = MCFGPIO_PDDR_BS,
124 .podr = MCFGPIO_PODR_BS,
125 .ppdr = MCFGPIO_PPDSDR_BS,
126 .setr = MCFGPIO_PPDSDR_BS,
127 .clrr = MCFGPIO_PCLRR_BS,
128 },
129 {
130 .gpio_chip = {
131 .label = "CS",
132 .request = mcf_gpio_request,
133 .free = mcf_gpio_free,
134 .direction_input = mcf_gpio_direction_input,
135 .direction_output = mcf_gpio_direction_output,
136 .get = mcf_gpio_get_value,
137 .set = mcf_gpio_set_value_fast,
138 .base = 49,
139 .ngpio = 7,
140 },
141 .pddr = MCFGPIO_PDDR_CS,
142 .podr = MCFGPIO_PODR_CS,
143 .ppdr = MCFGPIO_PPDSDR_CS,
144 .setr = MCFGPIO_PPDSDR_CS,
145 .clrr = MCFGPIO_PCLRR_CS,
146 },
147 {
148 .gpio_chip = {
149 .label = "SDRAM",
150 .request = mcf_gpio_request,
151 .free = mcf_gpio_free,
152 .direction_input = mcf_gpio_direction_input,
153 .direction_output = mcf_gpio_direction_output,
154 .get = mcf_gpio_get_value,
155 .set = mcf_gpio_set_value_fast,
156 .base = 56,
157 .ngpio = 6,
158 },
159 .pddr = MCFGPIO_PDDR_SDRAM,
160 .podr = MCFGPIO_PODR_SDRAM,
161 .ppdr = MCFGPIO_PPDSDR_SDRAM,
162 .setr = MCFGPIO_PPDSDR_SDRAM,
163 .clrr = MCFGPIO_PCLRR_SDRAM,
164 },
165 {
166 .gpio_chip = {
167 .label = "FECI2C",
168 .request = mcf_gpio_request,
169 .free = mcf_gpio_free,
170 .direction_input = mcf_gpio_direction_input,
171 .direction_output = mcf_gpio_direction_output,
172 .get = mcf_gpio_get_value,
173 .set = mcf_gpio_set_value_fast,
174 .base = 64,
175 .ngpio = 4,
176 },
177 .pddr = MCFGPIO_PDDR_FECI2C,
178 .podr = MCFGPIO_PODR_FECI2C,
179 .ppdr = MCFGPIO_PPDSDR_FECI2C,
180 .setr = MCFGPIO_PPDSDR_FECI2C,
181 .clrr = MCFGPIO_PCLRR_FECI2C,
182 },
183 {
184 .gpio_chip = {
185 .label = "UARTH",
186 .request = mcf_gpio_request,
187 .free = mcf_gpio_free,
188 .direction_input = mcf_gpio_direction_input,
189 .direction_output = mcf_gpio_direction_output,
190 .get = mcf_gpio_get_value,
191 .set = mcf_gpio_set_value_fast,
192 .base = 72,
193 .ngpio = 2,
194 },
195 .pddr = MCFGPIO_PDDR_UARTH,
196 .podr = MCFGPIO_PODR_UARTH,
197 .ppdr = MCFGPIO_PPDSDR_UARTH,
198 .setr = MCFGPIO_PPDSDR_UARTH,
199 .clrr = MCFGPIO_PCLRR_UARTH,
200 },
201 {
202 .gpio_chip = {
203 .label = "UARTL",
204 .request = mcf_gpio_request,
205 .free = mcf_gpio_free,
206 .direction_input = mcf_gpio_direction_input,
207 .direction_output = mcf_gpio_direction_output,
208 .get = mcf_gpio_get_value,
209 .set = mcf_gpio_set_value_fast,
210 .base = 80,
211 .ngpio = 8,
212 },
213 .pddr = MCFGPIO_PDDR_UARTL,
214 .podr = MCFGPIO_PODR_UARTL,
215 .ppdr = MCFGPIO_PPDSDR_UARTL,
216 .setr = MCFGPIO_PPDSDR_UARTL,
217 .clrr = MCFGPIO_PCLRR_UARTL,
218 },
219 {
220 .gpio_chip = {
221 .label = "QSPI",
222 .request = mcf_gpio_request,
223 .free = mcf_gpio_free,
224 .direction_input = mcf_gpio_direction_input,
225 .direction_output = mcf_gpio_direction_output,
226 .get = mcf_gpio_get_value,
227 .set = mcf_gpio_set_value_fast,
228 .base = 88,
229 .ngpio = 5,
230 },
231 .pddr = MCFGPIO_PDDR_QSPI,
232 .podr = MCFGPIO_PODR_QSPI,
233 .ppdr = MCFGPIO_PPDSDR_QSPI,
234 .setr = MCFGPIO_PPDSDR_QSPI,
235 .clrr = MCFGPIO_PCLRR_QSPI,
236 },
237 {
238 .gpio_chip = {
239 .label = "TIMER",
240 .request = mcf_gpio_request,
241 .free = mcf_gpio_free,
242 .direction_input = mcf_gpio_direction_input,
243 .direction_output = mcf_gpio_direction_output,
244 .get = mcf_gpio_get_value,
245 .set = mcf_gpio_set_value_fast,
246 .base = 96,
247 .ngpio = 4,
248 },
249 .pddr = MCFGPIO_PDDR_TIMER,
250 .podr = MCFGPIO_PODR_TIMER,
251 .ppdr = MCFGPIO_PPDSDR_TIMER,
252 .setr = MCFGPIO_PPDSDR_TIMER,
253 .clrr = MCFGPIO_PCLRR_TIMER,
254 },
255 {
256 .gpio_chip = {
257 .label = "ETPU",
258 .request = mcf_gpio_request,
259 .free = mcf_gpio_free,
260 .direction_input = mcf_gpio_direction_input,
261 .direction_output = mcf_gpio_direction_output,
262 .get = mcf_gpio_get_value,
263 .set = mcf_gpio_set_value_fast,
264 .base = 104,
265 .ngpio = 3,
266 },
267 .pddr = MCFGPIO_PDDR_ETPU,
268 .podr = MCFGPIO_PODR_ETPU,
269 .ppdr = MCFGPIO_PPDSDR_ETPU,
270 .setr = MCFGPIO_PPDSDR_ETPU,
271 .clrr = MCFGPIO_PCLRR_ETPU,
272 },
273};
274
275static int __init mcf_gpio_init(void)
276{
277 unsigned i = 0;
278 while (i < ARRAY_SIZE(mcf_gpio_chips))
279 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
280 return 0;
281}
282
283core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/5249/Makefile b/arch/m68knommu/platform/5249/Makefile
index a439d9ab3f27..f56225d1582f 100644
--- a/arch/m68knommu/platform/5249/Makefile
+++ b/arch/m68knommu/platform/5249/Makefile
@@ -14,5 +14,5 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o intc2.o
18 18
diff --git a/arch/m68knommu/platform/5249/config.c b/arch/m68knommu/platform/5249/config.c
index 93d998825925..646f5ba462fc 100644
--- a/arch/m68knommu/platform/5249/config.c
+++ b/arch/m68knommu/platform/5249/config.c
@@ -48,11 +48,11 @@ static void __init m5249_uart_init_line(int line, int irq)
48 if (line == 0) { 48 if (line == 0) {
49 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 49 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
50 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR); 50 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
51 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); 51 mcf_mapirq2imr(irq, MCFINTC_UART0);
52 } else if (line == 1) { 52 } else if (line == 1) {
53 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 53 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
54 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); 54 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
55 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); 55 mcf_mapirq2imr(irq, MCFINTC_UART1);
56 } 56 }
57} 57}
58 58
@@ -65,38 +65,21 @@ static void __init m5249_uarts_init(void)
65 m5249_uart_init_line(line, m5249_uart_platform[line].irq); 65 m5249_uart_init_line(line, m5249_uart_platform[line].irq);
66} 66}
67 67
68
69/***************************************************************************/ 68/***************************************************************************/
70 69
71void mcf_autovector(unsigned int vec) 70static void __init m5249_timers_init(void)
72{ 71{
73 volatile unsigned char *mbar; 72 /* Timer1 is always used as system timer */
74 73 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
75 if ((vec >= 25) && (vec <= 31)) { 74 MCF_MBAR + MCFSIM_TIMER1ICR);
76 mbar = (volatile unsigned char *) MCF_MBAR; 75 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
77 vec = 0x1 << (vec - 24); 76
78 *(mbar + MCFSIM_AVR) |= vec; 77#ifdef CONFIG_HIGHPROFILE
79 mcf_setimr(mcf_getimr() & ~vec); 78 /* Timer2 is to be used as a high speed profile timer */
80 } 79 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
81} 80 MCF_MBAR + MCFSIM_TIMER2ICR);
82 81 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
83/***************************************************************************/ 82#endif
84
85void mcf_settimericr(unsigned int timer, unsigned int level)
86{
87 volatile unsigned char *icrp;
88 unsigned int icr, imr;
89
90 if (timer <= 2) {
91 switch (timer) {
92 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break;
93 default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break;
94 }
95
96 icrp = (volatile unsigned char *) (MCF_MBAR + icr);
97 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3;
98 mcf_setimr(mcf_getimr() & ~imr);
99 }
100} 83}
101 84
102/***************************************************************************/ 85/***************************************************************************/
@@ -114,15 +97,15 @@ void m5249_cpu_reset(void)
114 97
115void __init config_BSP(char *commandp, int size) 98void __init config_BSP(char *commandp, int size)
116{ 99{
117 mcf_setimr(MCFSIM_IMR_MASKALL);
118 mach_reset = m5249_cpu_reset; 100 mach_reset = m5249_cpu_reset;
101 m5249_timers_init();
102 m5249_uarts_init();
119} 103}
120 104
121/***************************************************************************/ 105/***************************************************************************/
122 106
123static int __init init_BSP(void) 107static int __init init_BSP(void)
124{ 108{
125 m5249_uarts_init();
126 platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices)); 109 platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
127 return 0; 110 return 0;
128} 111}
diff --git a/arch/m68knommu/platform/5249/gpio.c b/arch/m68knommu/platform/5249/gpio.c
new file mode 100644
index 000000000000..c611eab8b3b6
--- /dev/null
+++ b/arch/m68knommu/platform/5249/gpio.c
@@ -0,0 +1,65 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "GPIO0",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 32,
34 },
35 .pddr = MCFSIM2_GPIOENABLE,
36 .podr = MCFSIM2_GPIOWRITE,
37 .ppdr = MCFSIM2_GPIOREAD,
38 },
39 {
40 .gpio_chip = {
41 .label = "GPIO1",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value,
48 .base = 32,
49 .ngpio = 32,
50 },
51 .pddr = MCFSIM2_GPIO1ENABLE,
52 .podr = MCFSIM2_GPIO1WRITE,
53 .ppdr = MCFSIM2_GPIO1READ,
54 },
55};
56
57static int __init mcf_gpio_init(void)
58{
59 unsigned i = 0;
60 while (i < ARRAY_SIZE(mcf_gpio_chips))
61 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
62 return 0;
63}
64
65core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/5249/intc2.c b/arch/m68knommu/platform/5249/intc2.c
new file mode 100644
index 000000000000..d09d9da04537
--- /dev/null
+++ b/arch/m68knommu/platform/5249/intc2.c
@@ -0,0 +1,59 @@
1/*
2 * intc2.c -- support for the 2nd INTC controller of the 5249
3 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19
20static void intc2_irq_gpio_mask(unsigned int irq)
21{
22 u32 imr;
23 imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
24 imr &= ~(0x1 << (irq - MCFINTC2_GPIOIRQ0));
25 writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
26}
27
28static void intc2_irq_gpio_unmask(unsigned int irq)
29{
30 u32 imr;
31 imr = readl(MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
32 imr |= (0x1 << (irq - MCFINTC2_GPIOIRQ0));
33 writel(imr, MCF_MBAR2 + MCFSIM2_GPIOINTENABLE);
34}
35
36static void intc2_irq_gpio_ack(unsigned int irq)
37{
38 writel(0x1 << (irq - MCFINTC2_GPIOIRQ0), MCF_MBAR2 + MCFSIM2_GPIOINTCLEAR);
39}
40
41static struct irq_chip intc2_irq_gpio_chip = {
42 .name = "CF-INTC2",
43 .mask = intc2_irq_gpio_mask,
44 .unmask = intc2_irq_gpio_unmask,
45 .ack = intc2_irq_gpio_ack,
46};
47
48static int __init mcf_intc2_init(void)
49{
50 int irq;
51
52 /* GPIO interrupt sources */
53 for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++)
54 irq_desc[irq].chip = &intc2_irq_gpio_chip;
55
56 return 0;
57}
58
59arch_initcall(mcf_intc2_init);
diff --git a/arch/m68knommu/platform/5272/Makefile b/arch/m68knommu/platform/5272/Makefile
index 26135d92b34d..93673ef8e2c1 100644
--- a/arch/m68knommu/platform/5272/Makefile
+++ b/arch/m68knommu/platform/5272/Makefile
@@ -14,5 +14,5 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o intc.o
18 18
diff --git a/arch/m68knommu/platform/5272/config.c b/arch/m68knommu/platform/5272/config.c
index 5f95fcde05fd..59278c0887d0 100644
--- a/arch/m68knommu/platform/5272/config.c
+++ b/arch/m68knommu/platform/5272/config.c
@@ -20,12 +20,6 @@
20 20
21/***************************************************************************/ 21/***************************************************************************/
22 22
23extern unsigned int mcf_timervector;
24extern unsigned int mcf_profilevector;
25extern unsigned int mcf_timerlevel;
26
27/***************************************************************************/
28
29/* 23/*
30 * Some platforms need software versions of the GPIO data registers. 24 * Some platforms need software versions of the GPIO data registers.
31 */ 25 */
@@ -37,11 +31,11 @@ unsigned char ledbank = 0xff;
37static struct mcf_platform_uart m5272_uart_platform[] = { 31static struct mcf_platform_uart m5272_uart_platform[] = {
38 { 32 {
39 .mapbase = MCF_MBAR + MCFUART_BASE1, 33 .mapbase = MCF_MBAR + MCFUART_BASE1,
40 .irq = 73, 34 .irq = MCF_IRQ_UART1,
41 }, 35 },
42 { 36 {
43 .mapbase = MCF_MBAR + MCFUART_BASE2, 37 .mapbase = MCF_MBAR + MCFUART_BASE2,
44 .irq = 74, 38 .irq = MCF_IRQ_UART2,
45 }, 39 },
46 { }, 40 { },
47}; 41};
@@ -59,18 +53,18 @@ static struct resource m5272_fec_resources[] = {
59 .flags = IORESOURCE_MEM, 53 .flags = IORESOURCE_MEM,
60 }, 54 },
61 { 55 {
62 .start = 86, 56 .start = MCF_IRQ_ERX,
63 .end = 86, 57 .end = MCF_IRQ_ERX,
64 .flags = IORESOURCE_IRQ, 58 .flags = IORESOURCE_IRQ,
65 }, 59 },
66 { 60 {
67 .start = 87, 61 .start = MCF_IRQ_ETX,
68 .end = 87, 62 .end = MCF_IRQ_ETX,
69 .flags = IORESOURCE_IRQ, 63 .flags = IORESOURCE_IRQ,
70 }, 64 },
71 { 65 {
72 .start = 88, 66 .start = MCF_IRQ_ENTC,
73 .end = 88, 67 .end = MCF_IRQ_ENTC,
74 .flags = IORESOURCE_IRQ, 68 .flags = IORESOURCE_IRQ,
75 }, 69 },
76}; 70};
@@ -94,9 +88,6 @@ static void __init m5272_uart_init_line(int line, int irq)
94 u32 v; 88 u32 v;
95 89
96 if ((line >= 0) && (line < 2)) { 90 if ((line >= 0) && (line < 2)) {
97 v = (line) ? 0x0e000000 : 0xe0000000;
98 writel(v, MCF_MBAR + MCFSIM_ICR2);
99
100 /* Enable the output lines for the serial ports */ 91 /* Enable the output lines for the serial ports */
101 v = readl(MCF_MBAR + MCFSIM_PBCNT); 92 v = readl(MCF_MBAR + MCFSIM_PBCNT);
102 v = (v & ~0x000000ff) | 0x00000055; 93 v = (v & ~0x000000ff) | 0x00000055;
@@ -119,54 +110,6 @@ static void __init m5272_uarts_init(void)
119 110
120/***************************************************************************/ 111/***************************************************************************/
121 112
122static void __init m5272_fec_init(void)
123{
124 u32 imr;
125
126 /* Unmask FEC interrupts at ColdFire interrupt controller */
127 imr = readl(MCF_MBAR + MCFSIM_ICR3);
128 imr = (imr & ~0x00000fff) | 0x00000ddd;
129 writel(imr, MCF_MBAR + MCFSIM_ICR3);
130
131 imr = readl(MCF_MBAR + MCFSIM_ICR1);
132 imr = (imr & ~0x0f000000) | 0x0d000000;
133 writel(imr, MCF_MBAR + MCFSIM_ICR1);
134}
135
136/***************************************************************************/
137
138void mcf_disableall(void)
139{
140 volatile unsigned long *icrp;
141
142 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
143 icrp[0] = 0x88888888;
144 icrp[1] = 0x88888888;
145 icrp[2] = 0x88888888;
146 icrp[3] = 0x88888888;
147}
148
149/***************************************************************************/
150
151void mcf_autovector(unsigned int vec)
152{
153 /* Everything is auto-vectored on the 5272 */
154}
155
156/***************************************************************************/
157
158void mcf_settimericr(int timer, int level)
159{
160 volatile unsigned long *icrp;
161
162 if ((timer >= 1 ) && (timer <= 4)) {
163 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
164 *icrp = (0x8 | level) << ((4 - timer) * 4);
165 }
166}
167
168/***************************************************************************/
169
170static void m5272_cpu_reset(void) 113static void m5272_cpu_reset(void)
171{ 114{
172 local_irq_disable(); 115 local_irq_disable();
@@ -190,8 +133,6 @@ void __init config_BSP(char *commandp, int size)
190 *pivrp = 0x40; 133 *pivrp = 0x40;
191#endif 134#endif
192 135
193 mcf_disableall();
194
195#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES) 136#if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
196 /* Copy command line from FLASH to local buffer... */ 137 /* Copy command line from FLASH to local buffer... */
197 memcpy(commandp, (char *) 0xf0004000, size); 138 memcpy(commandp, (char *) 0xf0004000, size);
@@ -202,8 +143,6 @@ void __init config_BSP(char *commandp, int size)
202 commandp[size-1] = 0; 143 commandp[size-1] = 0;
203#endif 144#endif
204 145
205 mcf_timervector = 69;
206 mcf_profilevector = 70;
207 mach_reset = m5272_cpu_reset; 146 mach_reset = m5272_cpu_reset;
208} 147}
209 148
@@ -212,7 +151,6 @@ void __init config_BSP(char *commandp, int size)
212static int __init init_BSP(void) 151static int __init init_BSP(void)
213{ 152{
214 m5272_uarts_init(); 153 m5272_uarts_init();
215 m5272_fec_init();
216 platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices)); 154 platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices));
217 return 0; 155 return 0;
218} 156}
diff --git a/arch/m68knommu/platform/5272/gpio.c b/arch/m68knommu/platform/5272/gpio.c
new file mode 100644
index 000000000000..459db89a89cc
--- /dev/null
+++ b/arch/m68knommu/platform/5272/gpio.c
@@ -0,0 +1,81 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PA",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 16,
34 },
35 .pddr = MCFSIM_PADDR,
36 .podr = MCFSIM_PADAT,
37 .ppdr = MCFSIM_PADAT,
38 },
39 {
40 .gpio_chip = {
41 .label = "PB",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value,
48 .base = 16,
49 .ngpio = 16,
50 },
51 .pddr = MCFSIM_PBDDR,
52 .podr = MCFSIM_PBDAT,
53 .ppdr = MCFSIM_PBDAT,
54 },
55 {
56 .gpio_chip = {
57 .label = "PC",
58 .request = mcf_gpio_request,
59 .free = mcf_gpio_free,
60 .direction_input = mcf_gpio_direction_input,
61 .direction_output = mcf_gpio_direction_output,
62 .get = mcf_gpio_get_value,
63 .set = mcf_gpio_set_value,
64 .base = 32,
65 .ngpio = 16,
66 },
67 .pddr = MCFSIM_PCDDR,
68 .podr = MCFSIM_PCDAT,
69 .ppdr = MCFSIM_PCDAT,
70 },
71};
72
73static int __init mcf_gpio_init(void)
74{
75 unsigned i = 0;
76 while (i < ARRAY_SIZE(mcf_gpio_chips))
77 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
78 return 0;
79}
80
81core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/5272/intc.c b/arch/m68knommu/platform/5272/intc.c
new file mode 100644
index 000000000000..7081e0a9720e
--- /dev/null
+++ b/arch/m68knommu/platform/5272/intc.c
@@ -0,0 +1,138 @@
1/*
2 * intc.c -- interrupt controller or ColdFire 5272 SoC
3 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/traps.h>
20
21/*
22 * The 5272 ColdFire interrupt controller is nothing like any other
23 * ColdFire interrupt controller - it truly is completely different.
24 * Given its age it is unlikely to be used on any other ColdFire CPU.
25 */
26
27/*
28 * The masking and priproty setting of interrupts on the 5272 is done
29 * via a set of 4 "Interrupt Controller Registers" (ICR). There is a
30 * loose mapping of vector number to register and internal bits, but
31 * a table is the easiest and quickest way to map them.
32 */
33struct irqmap {
34 unsigned char icr;
35 unsigned char index;
36 unsigned char ack;
37};
38
39static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
40 /*MCF_IRQ_SPURIOUS*/ { .icr = 0, .index = 0, .ack = 0, },
41 /*MCF_IRQ_EINT1*/ { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, },
42 /*MCF_IRQ_EINT2*/ { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, },
43 /*MCF_IRQ_EINT3*/ { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, },
44 /*MCF_IRQ_EINT4*/ { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, },
45 /*MCF_IRQ_TIMER1*/ { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, },
46 /*MCF_IRQ_TIMER2*/ { .icr = MCFSIM_ICR1, .index = 8, .ack = 0, },
47 /*MCF_IRQ_TIMER3*/ { .icr = MCFSIM_ICR1, .index = 4, .ack = 0, },
48 /*MCF_IRQ_TIMER4*/ { .icr = MCFSIM_ICR1, .index = 0, .ack = 0, },
49 /*MCF_IRQ_UART1*/ { .icr = MCFSIM_ICR2, .index = 28, .ack = 0, },
50 /*MCF_IRQ_UART2*/ { .icr = MCFSIM_ICR2, .index = 24, .ack = 0, },
51 /*MCF_IRQ_PLIP*/ { .icr = MCFSIM_ICR2, .index = 20, .ack = 0, },
52 /*MCF_IRQ_PLIA*/ { .icr = MCFSIM_ICR2, .index = 16, .ack = 0, },
53 /*MCF_IRQ_USB0*/ { .icr = MCFSIM_ICR2, .index = 12, .ack = 0, },
54 /*MCF_IRQ_USB1*/ { .icr = MCFSIM_ICR2, .index = 8, .ack = 0, },
55 /*MCF_IRQ_USB2*/ { .icr = MCFSIM_ICR2, .index = 4, .ack = 0, },
56 /*MCF_IRQ_USB3*/ { .icr = MCFSIM_ICR2, .index = 0, .ack = 0, },
57 /*MCF_IRQ_USB4*/ { .icr = MCFSIM_ICR3, .index = 28, .ack = 0, },
58 /*MCF_IRQ_USB5*/ { .icr = MCFSIM_ICR3, .index = 24, .ack = 0, },
59 /*MCF_IRQ_USB6*/ { .icr = MCFSIM_ICR3, .index = 20, .ack = 0, },
60 /*MCF_IRQ_USB7*/ { .icr = MCFSIM_ICR3, .index = 16, .ack = 0, },
61 /*MCF_IRQ_DMA*/ { .icr = MCFSIM_ICR3, .index = 12, .ack = 0, },
62 /*MCF_IRQ_ERX*/ { .icr = MCFSIM_ICR3, .index = 8, .ack = 0, },
63 /*MCF_IRQ_ETX*/ { .icr = MCFSIM_ICR3, .index = 4, .ack = 0, },
64 /*MCF_IRQ_ENTC*/ { .icr = MCFSIM_ICR3, .index = 0, .ack = 0, },
65 /*MCF_IRQ_QSPI*/ { .icr = MCFSIM_ICR4, .index = 28, .ack = 0, },
66 /*MCF_IRQ_EINT5*/ { .icr = MCFSIM_ICR4, .index = 24, .ack = 1, },
67 /*MCF_IRQ_EINT6*/ { .icr = MCFSIM_ICR4, .index = 20, .ack = 1, },
68 /*MCF_IRQ_SWTO*/ { .icr = MCFSIM_ICR4, .index = 16, .ack = 0, },
69};
70
71static void intc_irq_mask(unsigned int irq)
72{
73 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
74 u32 v;
75 irq -= MCFINT_VECBASE;
76 v = 0x8 << intc_irqmap[irq].index;
77 writel(v, MCF_MBAR + intc_irqmap[irq].icr);
78 }
79}
80
81static void intc_irq_unmask(unsigned int irq)
82{
83 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
84 u32 v;
85 irq -= MCFINT_VECBASE;
86 v = 0xd << intc_irqmap[irq].index;
87 writel(v, MCF_MBAR + intc_irqmap[irq].icr);
88 }
89}
90
91static void intc_irq_ack(unsigned int irq)
92{
93 /* Only external interrupts are acked */
94 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
95 irq -= MCFINT_VECBASE;
96 if (intc_irqmap[irq].ack) {
97 u32 v;
98 v = 0xd << intc_irqmap[irq].index;
99 writel(v, MCF_MBAR + intc_irqmap[irq].icr);
100 }
101 }
102}
103
104static int intc_irq_set_type(unsigned int irq, unsigned int type)
105{
106 /* We can set the edge type here for external interrupts */
107 return 0;
108}
109
110static struct irq_chip intc_irq_chip = {
111 .name = "CF-INTC",
112 .mask = intc_irq_mask,
113 .unmask = intc_irq_unmask,
114 .ack = intc_irq_ack,
115 .set_type = intc_irq_set_type,
116};
117
118void __init init_IRQ(void)
119{
120 int irq;
121
122 init_vectors();
123
124 /* Mask all interrupt sources */
125 writel(0x88888888, MCF_MBAR + MCFSIM_ICR1);
126 writel(0x88888888, MCF_MBAR + MCFSIM_ICR2);
127 writel(0x88888888, MCF_MBAR + MCFSIM_ICR3);
128 writel(0x88888888, MCF_MBAR + MCFSIM_ICR4);
129
130 for (irq = 0; (irq < NR_IRQS); irq++) {
131 irq_desc[irq].status = IRQ_DISABLED;
132 irq_desc[irq].action = NULL;
133 irq_desc[irq].depth = 1;
134 irq_desc[irq].chip = &intc_irq_chip;
135 intc_irq_set_type(irq, 0);
136 }
137}
138
diff --git a/arch/m68knommu/platform/527x/Makefile b/arch/m68knommu/platform/527x/Makefile
index 26135d92b34d..3d90e6d92459 100644
--- a/arch/m68knommu/platform/527x/Makefile
+++ b/arch/m68knommu/platform/527x/Makefile
@@ -14,5 +14,5 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o
18 18
diff --git a/arch/m68knommu/platform/527x/config.c b/arch/m68knommu/platform/527x/config.c
index f746439cfd3e..fa51be172830 100644
--- a/arch/m68knommu/platform/527x/config.c
+++ b/arch/m68knommu/platform/527x/config.c
@@ -116,23 +116,13 @@ static struct platform_device *m527x_devices[] __initdata = {
116 116
117/***************************************************************************/ 117/***************************************************************************/
118 118
119#define INTC0 (MCF_MBAR + MCFICM_INTC0)
120
121static void __init m527x_uart_init_line(int line, int irq) 119static void __init m527x_uart_init_line(int line, int irq)
122{ 120{
123 u16 sepmask; 121 u16 sepmask;
124 u32 imr;
125 122
126 if ((line < 0) || (line > 2)) 123 if ((line < 0) || (line > 2))
127 return; 124 return;
128 125
129 /* level 6, line based priority */
130 writeb(0x30+line, INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + line);
131
132 imr = readl(INTC0 + MCFINTC_IMRL);
133 imr &= ~((1 << (irq - MCFINT_VECBASE)) | 1);
134 writel(imr, INTC0 + MCFINTC_IMRL);
135
136 /* 126 /*
137 * External Pin Mask Setting & Enable External Pin for Interface 127 * External Pin Mask Setting & Enable External Pin for Interface
138 */ 128 */
@@ -157,32 +147,11 @@ static void __init m527x_uarts_init(void)
157 147
158/***************************************************************************/ 148/***************************************************************************/
159 149
160static void __init m527x_fec_irq_init(int nr)
161{
162 unsigned long base;
163 u32 imr;
164
165 base = MCF_IPSBAR + (nr ? MCFICM_INTC1 : MCFICM_INTC0);
166
167 writeb(0x28, base + MCFINTC_ICR0 + 23);
168 writeb(0x27, base + MCFINTC_ICR0 + 27);
169 writeb(0x26, base + MCFINTC_ICR0 + 29);
170
171 imr = readl(base + MCFINTC_IMRH);
172 imr &= ~0xf;
173 writel(imr, base + MCFINTC_IMRH);
174 imr = readl(base + MCFINTC_IMRL);
175 imr &= ~0xff800001;
176 writel(imr, base + MCFINTC_IMRL);
177}
178
179static void __init m527x_fec_init(void) 150static void __init m527x_fec_init(void)
180{ 151{
181 u16 par; 152 u16 par;
182 u8 v; 153 u8 v;
183 154
184 m527x_fec_irq_init(0);
185
186 /* Set multi-function pins to ethernet mode for fec0 */ 155 /* Set multi-function pins to ethernet mode for fec0 */
187#if defined(CONFIG_M5271) 156#if defined(CONFIG_M5271)
188 v = readb(MCF_IPSBAR + 0x100047); 157 v = readb(MCF_IPSBAR + 0x100047);
@@ -195,8 +164,6 @@ static void __init m527x_fec_init(void)
195#endif 164#endif
196 165
197#ifdef CONFIG_FEC2 166#ifdef CONFIG_FEC2
198 m527x_fec_irq_init(1);
199
200 /* Set multi-function pins to ethernet mode for fec1 */ 167 /* Set multi-function pins to ethernet mode for fec1 */
201 par = readw(MCF_IPSBAR + 0x100082); 168 par = readw(MCF_IPSBAR + 0x100082);
202 writew(par | 0xa0, MCF_IPSBAR + 0x100082); 169 writew(par | 0xa0, MCF_IPSBAR + 0x100082);
@@ -207,21 +174,6 @@ static void __init m527x_fec_init(void)
207 174
208/***************************************************************************/ 175/***************************************************************************/
209 176
210void mcf_disableall(void)
211{
212 *((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH)) = 0xffffffff;
213 *((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL)) = 0xffffffff;
214}
215
216/***************************************************************************/
217
218void mcf_autovector(unsigned int vec)
219{
220 /* Everything is auto-vectored on the 5272 */
221}
222
223/***************************************************************************/
224
225static void m527x_cpu_reset(void) 177static void m527x_cpu_reset(void)
226{ 178{
227 local_irq_disable(); 179 local_irq_disable();
@@ -232,7 +184,6 @@ static void m527x_cpu_reset(void)
232 184
233void __init config_BSP(char *commandp, int size) 185void __init config_BSP(char *commandp, int size)
234{ 186{
235 mcf_disableall();
236 mach_reset = m527x_cpu_reset; 187 mach_reset = m527x_cpu_reset;
237 m527x_uarts_init(); 188 m527x_uarts_init();
238 m527x_fec_init(); 189 m527x_fec_init();
diff --git a/arch/m68knommu/platform/527x/gpio.c b/arch/m68knommu/platform/527x/gpio.c
new file mode 100644
index 000000000000..1028142851ac
--- /dev/null
+++ b/arch/m68knommu/platform/527x/gpio.c
@@ -0,0 +1,607 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24#if defined(CONFIG_M5271)
25 {
26 .gpio_chip = {
27 .label = "PIRQ",
28 .request = mcf_gpio_request,
29 .free = mcf_gpio_free,
30 .direction_input = mcf_gpio_direction_input,
31 .direction_output = mcf_gpio_direction_output,
32 .get = mcf_gpio_get_value,
33 .set = mcf_gpio_set_value,
34 .ngpio = 8,
35 },
36 .pddr = MCFEPORT_EPDDR,
37 .podr = MCFEPORT_EPDR,
38 .ppdr = MCFEPORT_EPPDR,
39 },
40 {
41 .gpio_chip = {
42 .label = "ADDR",
43 .request = mcf_gpio_request,
44 .free = mcf_gpio_free,
45 .direction_input = mcf_gpio_direction_input,
46 .direction_output = mcf_gpio_direction_output,
47 .get = mcf_gpio_get_value,
48 .set = mcf_gpio_set_value_fast,
49 .base = 13,
50 .ngpio = 3,
51 },
52 .pddr = MCFGPIO_PDDR_ADDR,
53 .podr = MCFGPIO_PODR_ADDR,
54 .ppdr = MCFGPIO_PPDSDR_ADDR,
55 .setr = MCFGPIO_PPDSDR_ADDR,
56 .clrr = MCFGPIO_PCLRR_ADDR,
57 },
58 {
59 .gpio_chip = {
60 .label = "DATAH",
61 .request = mcf_gpio_request,
62 .free = mcf_gpio_free,
63 .direction_input = mcf_gpio_direction_input,
64 .direction_output = mcf_gpio_direction_output,
65 .get = mcf_gpio_get_value,
66 .set = mcf_gpio_set_value_fast,
67 .base = 16,
68 .ngpio = 8,
69 },
70 .pddr = MCFGPIO_PDDR_DATAH,
71 .podr = MCFGPIO_PODR_DATAH,
72 .ppdr = MCFGPIO_PPDSDR_DATAH,
73 .setr = MCFGPIO_PPDSDR_DATAH,
74 .clrr = MCFGPIO_PCLRR_DATAH,
75 },
76 {
77 .gpio_chip = {
78 .label = "DATAL",
79 .request = mcf_gpio_request,
80 .free = mcf_gpio_free,
81 .direction_input = mcf_gpio_direction_input,
82 .direction_output = mcf_gpio_direction_output,
83 .get = mcf_gpio_get_value,
84 .set = mcf_gpio_set_value_fast,
85 .base = 24,
86 .ngpio = 8,
87 },
88 .pddr = MCFGPIO_PDDR_DATAL,
89 .podr = MCFGPIO_PODR_DATAL,
90 .ppdr = MCFGPIO_PPDSDR_DATAL,
91 .setr = MCFGPIO_PPDSDR_DATAL,
92 .clrr = MCFGPIO_PCLRR_DATAL,
93 },
94 {
95 .gpio_chip = {
96 .label = "BUSCTL",
97 .request = mcf_gpio_request,
98 .free = mcf_gpio_free,
99 .direction_input = mcf_gpio_direction_input,
100 .direction_output = mcf_gpio_direction_output,
101 .get = mcf_gpio_get_value,
102 .set = mcf_gpio_set_value_fast,
103 .base = 32,
104 .ngpio = 8,
105 },
106 .pddr = MCFGPIO_PDDR_BUSCTL,
107 .podr = MCFGPIO_PODR_BUSCTL,
108 .ppdr = MCFGPIO_PPDSDR_BUSCTL,
109 .setr = MCFGPIO_PPDSDR_BUSCTL,
110 .clrr = MCFGPIO_PCLRR_BUSCTL,
111 },
112 {
113 .gpio_chip = {
114 .label = "BS",
115 .request = mcf_gpio_request,
116 .free = mcf_gpio_free,
117 .direction_input = mcf_gpio_direction_input,
118 .direction_output = mcf_gpio_direction_output,
119 .get = mcf_gpio_get_value,
120 .set = mcf_gpio_set_value_fast,
121 .base = 40,
122 .ngpio = 4,
123 },
124 .pddr = MCFGPIO_PDDR_BS,
125 .podr = MCFGPIO_PODR_BS,
126 .ppdr = MCFGPIO_PPDSDR_BS,
127 .setr = MCFGPIO_PPDSDR_BS,
128 .clrr = MCFGPIO_PCLRR_BS,
129 },
130 {
131 .gpio_chip = {
132 .label = "CS",
133 .request = mcf_gpio_request,
134 .free = mcf_gpio_free,
135 .direction_input = mcf_gpio_direction_input,
136 .direction_output = mcf_gpio_direction_output,
137 .get = mcf_gpio_get_value,
138 .set = mcf_gpio_set_value_fast,
139 .base = 49,
140 .ngpio = 7,
141 },
142 .pddr = MCFGPIO_PDDR_CS,
143 .podr = MCFGPIO_PODR_CS,
144 .ppdr = MCFGPIO_PPDSDR_CS,
145 .setr = MCFGPIO_PPDSDR_CS,
146 .clrr = MCFGPIO_PCLRR_CS,
147 },
148 {
149 .gpio_chip = {
150 .label = "SDRAM",
151 .request = mcf_gpio_request,
152 .free = mcf_gpio_free,
153 .direction_input = mcf_gpio_direction_input,
154 .direction_output = mcf_gpio_direction_output,
155 .get = mcf_gpio_get_value,
156 .set = mcf_gpio_set_value_fast,
157 .base = 56,
158 .ngpio = 6,
159 },
160 .pddr = MCFGPIO_PDDR_SDRAM,
161 .podr = MCFGPIO_PODR_SDRAM,
162 .ppdr = MCFGPIO_PPDSDR_SDRAM,
163 .setr = MCFGPIO_PPDSDR_SDRAM,
164 .clrr = MCFGPIO_PCLRR_SDRAM,
165 },
166 {
167 .gpio_chip = {
168 .label = "FECI2C",
169 .request = mcf_gpio_request,
170 .free = mcf_gpio_free,
171 .direction_input = mcf_gpio_direction_input,
172 .direction_output = mcf_gpio_direction_output,
173 .get = mcf_gpio_get_value,
174 .set = mcf_gpio_set_value_fast,
175 .base = 64,
176 .ngpio = 4,
177 },
178 .pddr = MCFGPIO_PDDR_FECI2C,
179 .podr = MCFGPIO_PODR_FECI2C,
180 .ppdr = MCFGPIO_PPDSDR_FECI2C,
181 .setr = MCFGPIO_PPDSDR_FECI2C,
182 .clrr = MCFGPIO_PCLRR_FECI2C,
183 },
184 {
185 .gpio_chip = {
186 .label = "UARTH",
187 .request = mcf_gpio_request,
188 .free = mcf_gpio_free,
189 .direction_input = mcf_gpio_direction_input,
190 .direction_output = mcf_gpio_direction_output,
191 .get = mcf_gpio_get_value,
192 .set = mcf_gpio_set_value_fast,
193 .base = 72,
194 .ngpio = 2,
195 },
196 .pddr = MCFGPIO_PDDR_UARTH,
197 .podr = MCFGPIO_PODR_UARTH,
198 .ppdr = MCFGPIO_PPDSDR_UARTH,
199 .setr = MCFGPIO_PPDSDR_UARTH,
200 .clrr = MCFGPIO_PCLRR_UARTH,
201 },
202 {
203 .gpio_chip = {
204 .label = "UARTL",
205 .request = mcf_gpio_request,
206 .free = mcf_gpio_free,
207 .direction_input = mcf_gpio_direction_input,
208 .direction_output = mcf_gpio_direction_output,
209 .get = mcf_gpio_get_value,
210 .set = mcf_gpio_set_value_fast,
211 .base = 80,
212 .ngpio = 8,
213 },
214 .pddr = MCFGPIO_PDDR_UARTL,
215 .podr = MCFGPIO_PODR_UARTL,
216 .ppdr = MCFGPIO_PPDSDR_UARTL,
217 .setr = MCFGPIO_PPDSDR_UARTL,
218 .clrr = MCFGPIO_PCLRR_UARTL,
219 },
220 {
221 .gpio_chip = {
222 .label = "QSPI",
223 .request = mcf_gpio_request,
224 .free = mcf_gpio_free,
225 .direction_input = mcf_gpio_direction_input,
226 .direction_output = mcf_gpio_direction_output,
227 .get = mcf_gpio_get_value,
228 .set = mcf_gpio_set_value_fast,
229 .base = 88,
230 .ngpio = 5,
231 },
232 .pddr = MCFGPIO_PDDR_QSPI,
233 .podr = MCFGPIO_PODR_QSPI,
234 .ppdr = MCFGPIO_PPDSDR_QSPI,
235 .setr = MCFGPIO_PPDSDR_QSPI,
236 .clrr = MCFGPIO_PCLRR_QSPI,
237 },
238 {
239 .gpio_chip = {
240 .label = "TIMER",
241 .request = mcf_gpio_request,
242 .free = mcf_gpio_free,
243 .direction_input = mcf_gpio_direction_input,
244 .direction_output = mcf_gpio_direction_output,
245 .get = mcf_gpio_get_value,
246 .set = mcf_gpio_set_value_fast,
247 .base = 96,
248 .ngpio = 8,
249 },
250 .pddr = MCFGPIO_PDDR_TIMER,
251 .podr = MCFGPIO_PODR_TIMER,
252 .ppdr = MCFGPIO_PPDSDR_TIMER,
253 .setr = MCFGPIO_PPDSDR_TIMER,
254 .clrr = MCFGPIO_PCLRR_TIMER,
255 },
256#elif defined(CONFIG_M5275)
257 {
258 .gpio_chip = {
259 .label = "PIRQ",
260 .request = mcf_gpio_request,
261 .free = mcf_gpio_free,
262 .direction_input = mcf_gpio_direction_input,
263 .direction_output = mcf_gpio_direction_output,
264 .get = mcf_gpio_get_value,
265 .set = mcf_gpio_set_value,
266 .ngpio = 8,
267 },
268 .pddr = MCFEPORT_EPDDR,
269 .podr = MCFEPORT_EPDR,
270 .ppdr = MCFEPORT_EPPDR,
271 },
272 {
273 .gpio_chip = {
274 .label = "BUSCTL",
275 .request = mcf_gpio_request,
276 .free = mcf_gpio_free,
277 .direction_input = mcf_gpio_direction_input,
278 .direction_output = mcf_gpio_direction_output,
279 .get = mcf_gpio_get_value,
280 .set = mcf_gpio_set_value_fast,
281 .base = 8,
282 .ngpio = 8,
283 },
284 .pddr = MCFGPIO_PDDR_BUSCTL,
285 .podr = MCFGPIO_PODR_BUSCTL,
286 .ppdr = MCFGPIO_PPDSDR_BUSCTL,
287 .setr = MCFGPIO_PPDSDR_BUSCTL,
288 .clrr = MCFGPIO_PCLRR_BUSCTL,
289 },
290 {
291 .gpio_chip = {
292 .label = "ADDR",
293 .request = mcf_gpio_request,
294 .free = mcf_gpio_free,
295 .direction_input = mcf_gpio_direction_input,
296 .direction_output = mcf_gpio_direction_output,
297 .get = mcf_gpio_get_value,
298 .set = mcf_gpio_set_value_fast,
299 .base = 21,
300 .ngpio = 3,
301 },
302 .pddr = MCFGPIO_PDDR_ADDR,
303 .podr = MCFGPIO_PODR_ADDR,
304 .ppdr = MCFGPIO_PPDSDR_ADDR,
305 .setr = MCFGPIO_PPDSDR_ADDR,
306 .clrr = MCFGPIO_PCLRR_ADDR,
307 },
308 {
309 .gpio_chip = {
310 .label = "CS",
311 .request = mcf_gpio_request,
312 .free = mcf_gpio_free,
313 .direction_input = mcf_gpio_direction_input,
314 .direction_output = mcf_gpio_direction_output,
315 .get = mcf_gpio_get_value,
316 .set = mcf_gpio_set_value_fast,
317 .base = 25,
318 .ngpio = 7,
319 },
320 .pddr = MCFGPIO_PDDR_CS,
321 .podr = MCFGPIO_PODR_CS,
322 .ppdr = MCFGPIO_PPDSDR_CS,
323 .setr = MCFGPIO_PPDSDR_CS,
324 .clrr = MCFGPIO_PCLRR_CS,
325 },
326 {
327 .gpio_chip = {
328 .label = "FEC0H",
329 .request = mcf_gpio_request,
330 .free = mcf_gpio_free,
331 .direction_input = mcf_gpio_direction_input,
332 .direction_output = mcf_gpio_direction_output,
333 .get = mcf_gpio_get_value,
334 .set = mcf_gpio_set_value_fast,
335 .base = 32,
336 .ngpio = 8,
337 },
338 .pddr = MCFGPIO_PDDR_FEC0H,
339 .podr = MCFGPIO_PODR_FEC0H,
340 .ppdr = MCFGPIO_PPDSDR_FEC0H,
341 .setr = MCFGPIO_PPDSDR_FEC0H,
342 .clrr = MCFGPIO_PCLRR_FEC0H,
343 },
344 {
345 .gpio_chip = {
346 .label = "FEC0L",
347 .request = mcf_gpio_request,
348 .free = mcf_gpio_free,
349 .direction_input = mcf_gpio_direction_input,
350 .direction_output = mcf_gpio_direction_output,
351 .get = mcf_gpio_get_value,
352 .set = mcf_gpio_set_value_fast,
353 .base = 40,
354 .ngpio = 8,
355 },
356 .pddr = MCFGPIO_PDDR_FEC0L,
357 .podr = MCFGPIO_PODR_FEC0L,
358 .ppdr = MCFGPIO_PPDSDR_FEC0L,
359 .setr = MCFGPIO_PPDSDR_FEC0L,
360 .clrr = MCFGPIO_PCLRR_FEC0L,
361 },
362 {
363 .gpio_chip = {
364 .label = "FECI2C",
365 .request = mcf_gpio_request,
366 .free = mcf_gpio_free,
367 .direction_input = mcf_gpio_direction_input,
368 .direction_output = mcf_gpio_direction_output,
369 .get = mcf_gpio_get_value,
370 .set = mcf_gpio_set_value_fast,
371 .base = 48,
372 .ngpio = 6,
373 },
374 .pddr = MCFGPIO_PDDR_FECI2C,
375 .podr = MCFGPIO_PODR_FECI2C,
376 .ppdr = MCFGPIO_PPDSDR_FECI2C,
377 .setr = MCFGPIO_PPDSDR_FECI2C,
378 .clrr = MCFGPIO_PCLRR_FECI2C,
379 },
380 {
381 .gpio_chip = {
382 .label = "QSPI",
383 .request = mcf_gpio_request,
384 .free = mcf_gpio_free,
385 .direction_input = mcf_gpio_direction_input,
386 .direction_output = mcf_gpio_direction_output,
387 .get = mcf_gpio_get_value,
388 .set = mcf_gpio_set_value_fast,
389 .base = 56,
390 .ngpio = 7,
391 },
392 .pddr = MCFGPIO_PDDR_QSPI,
393 .podr = MCFGPIO_PODR_QSPI,
394 .ppdr = MCFGPIO_PPDSDR_QSPI,
395 .setr = MCFGPIO_PPDSDR_QSPI,
396 .clrr = MCFGPIO_PCLRR_QSPI,
397 },
398 {
399 .gpio_chip = {
400 .label = "SDRAM",
401 .request = mcf_gpio_request,
402 .free = mcf_gpio_free,
403 .direction_input = mcf_gpio_direction_input,
404 .direction_output = mcf_gpio_direction_output,
405 .get = mcf_gpio_get_value,
406 .set = mcf_gpio_set_value_fast,
407 .base = 64,
408 .ngpio = 8,
409 },
410 .pddr = MCFGPIO_PDDR_SDRAM,
411 .podr = MCFGPIO_PODR_SDRAM,
412 .ppdr = MCFGPIO_PPDSDR_SDRAM,
413 .setr = MCFGPIO_PPDSDR_SDRAM,
414 .clrr = MCFGPIO_PCLRR_SDRAM,
415 },
416 {
417 .gpio_chip = {
418 .label = "TIMERH",
419 .request = mcf_gpio_request,
420 .free = mcf_gpio_free,
421 .direction_input = mcf_gpio_direction_input,
422 .direction_output = mcf_gpio_direction_output,
423 .get = mcf_gpio_get_value,
424 .set = mcf_gpio_set_value_fast,
425 .base = 72,
426 .ngpio = 4,
427 },
428 .pddr = MCFGPIO_PDDR_TIMERH,
429 .podr = MCFGPIO_PODR_TIMERH,
430 .ppdr = MCFGPIO_PPDSDR_TIMERH,
431 .setr = MCFGPIO_PPDSDR_TIMERH,
432 .clrr = MCFGPIO_PCLRR_TIMERH,
433 },
434 {
435 .gpio_chip = {
436 .label = "TIMERL",
437 .request = mcf_gpio_request,
438 .free = mcf_gpio_free,
439 .direction_input = mcf_gpio_direction_input,
440 .direction_output = mcf_gpio_direction_output,
441 .get = mcf_gpio_get_value,
442 .set = mcf_gpio_set_value_fast,
443 .base = 80,
444 .ngpio = 4,
445 },
446 .pddr = MCFGPIO_PDDR_TIMERL,
447 .podr = MCFGPIO_PODR_TIMERL,
448 .ppdr = MCFGPIO_PPDSDR_TIMERL,
449 .setr = MCFGPIO_PPDSDR_TIMERL,
450 .clrr = MCFGPIO_PCLRR_TIMERL,
451 },
452 {
453 .gpio_chip = {
454 .label = "UARTL",
455 .request = mcf_gpio_request,
456 .free = mcf_gpio_free,
457 .direction_input = mcf_gpio_direction_input,
458 .direction_output = mcf_gpio_direction_output,
459 .get = mcf_gpio_get_value,
460 .set = mcf_gpio_set_value_fast,
461 .base = 88,
462 .ngpio = 8,
463 },
464 .pddr = MCFGPIO_PDDR_UARTL,
465 .podr = MCFGPIO_PODR_UARTL,
466 .ppdr = MCFGPIO_PPDSDR_UARTL,
467 .setr = MCFGPIO_PPDSDR_UARTL,
468 .clrr = MCFGPIO_PCLRR_UARTL,
469 },
470 {
471 .gpio_chip = {
472 .label = "FEC1H",
473 .request = mcf_gpio_request,
474 .free = mcf_gpio_free,
475 .direction_input = mcf_gpio_direction_input,
476 .direction_output = mcf_gpio_direction_output,
477 .get = mcf_gpio_get_value,
478 .set = mcf_gpio_set_value_fast,
479 .base = 96,
480 .ngpio = 8,
481 },
482 .pddr = MCFGPIO_PDDR_FEC1H,
483 .podr = MCFGPIO_PODR_FEC1H,
484 .ppdr = MCFGPIO_PPDSDR_FEC1H,
485 .setr = MCFGPIO_PPDSDR_FEC1H,
486 .clrr = MCFGPIO_PCLRR_FEC1H,
487 },
488 {
489 .gpio_chip = {
490 .label = "FEC1L",
491 .request = mcf_gpio_request,
492 .free = mcf_gpio_free,
493 .direction_input = mcf_gpio_direction_input,
494 .direction_output = mcf_gpio_direction_output,
495 .get = mcf_gpio_get_value,
496 .set = mcf_gpio_set_value_fast,
497 .base = 104,
498 .ngpio = 8,
499 },
500 .pddr = MCFGPIO_PDDR_FEC1L,
501 .podr = MCFGPIO_PODR_FEC1L,
502 .ppdr = MCFGPIO_PPDSDR_FEC1L,
503 .setr = MCFGPIO_PPDSDR_FEC1L,
504 .clrr = MCFGPIO_PCLRR_FEC1L,
505 },
506 {
507 .gpio_chip = {
508 .label = "BS",
509 .request = mcf_gpio_request,
510 .free = mcf_gpio_free,
511 .direction_input = mcf_gpio_direction_input,
512 .direction_output = mcf_gpio_direction_output,
513 .get = mcf_gpio_get_value,
514 .set = mcf_gpio_set_value_fast,
515 .base = 114,
516 .ngpio = 2,
517 },
518 .pddr = MCFGPIO_PDDR_BS,
519 .podr = MCFGPIO_PODR_BS,
520 .ppdr = MCFGPIO_PPDSDR_BS,
521 .setr = MCFGPIO_PPDSDR_BS,
522 .clrr = MCFGPIO_PCLRR_BS,
523 },
524 {
525 .gpio_chip = {
526 .label = "IRQ",
527 .request = mcf_gpio_request,
528 .free = mcf_gpio_free,
529 .direction_input = mcf_gpio_direction_input,
530 .direction_output = mcf_gpio_direction_output,
531 .get = mcf_gpio_get_value,
532 .set = mcf_gpio_set_value_fast,
533 .base = 121,
534 .ngpio = 7,
535 },
536 .pddr = MCFGPIO_PDDR_IRQ,
537 .podr = MCFGPIO_PODR_IRQ,
538 .ppdr = MCFGPIO_PPDSDR_IRQ,
539 .setr = MCFGPIO_PPDSDR_IRQ,
540 .clrr = MCFGPIO_PCLRR_IRQ,
541 },
542 {
543 .gpio_chip = {
544 .label = "USBH",
545 .request = mcf_gpio_request,
546 .free = mcf_gpio_free,
547 .direction_input = mcf_gpio_direction_input,
548 .direction_output = mcf_gpio_direction_output,
549 .get = mcf_gpio_get_value,
550 .set = mcf_gpio_set_value_fast,
551 .base = 128,
552 .ngpio = 1,
553 },
554 .pddr = MCFGPIO_PDDR_USBH,
555 .podr = MCFGPIO_PODR_USBH,
556 .ppdr = MCFGPIO_PPDSDR_USBH,
557 .setr = MCFGPIO_PPDSDR_USBH,
558 .clrr = MCFGPIO_PCLRR_USBH,
559 },
560 {
561 .gpio_chip = {
562 .label = "USBL",
563 .request = mcf_gpio_request,
564 .free = mcf_gpio_free,
565 .direction_input = mcf_gpio_direction_input,
566 .direction_output = mcf_gpio_direction_output,
567 .get = mcf_gpio_get_value,
568 .set = mcf_gpio_set_value_fast,
569 .base = 136,
570 .ngpio = 8,
571 },
572 .pddr = MCFGPIO_PDDR_USBL,
573 .podr = MCFGPIO_PODR_USBL,
574 .ppdr = MCFGPIO_PPDSDR_USBL,
575 .setr = MCFGPIO_PPDSDR_USBL,
576 .clrr = MCFGPIO_PCLRR_USBL,
577 },
578 {
579 .gpio_chip = {
580 .label = "UARTH",
581 .request = mcf_gpio_request,
582 .free = mcf_gpio_free,
583 .direction_input = mcf_gpio_direction_input,
584 .direction_output = mcf_gpio_direction_output,
585 .get = mcf_gpio_get_value,
586 .set = mcf_gpio_set_value_fast,
587 .base = 144,
588 .ngpio = 4,
589 },
590 .pddr = MCFGPIO_PDDR_UARTH,
591 .podr = MCFGPIO_PODR_UARTH,
592 .ppdr = MCFGPIO_PPDSDR_UARTH,
593 .setr = MCFGPIO_PPDSDR_UARTH,
594 .clrr = MCFGPIO_PCLRR_UARTH,
595 },
596#endif
597};
598
599static int __init mcf_gpio_init(void)
600{
601 unsigned i = 0;
602 while (i < ARRAY_SIZE(mcf_gpio_chips))
603 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
604 return 0;
605}
606
607core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/528x/Makefile b/arch/m68knommu/platform/528x/Makefile
index 26135d92b34d..3d90e6d92459 100644
--- a/arch/m68knommu/platform/528x/Makefile
+++ b/arch/m68knommu/platform/528x/Makefile
@@ -14,5 +14,5 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o
18 18
diff --git a/arch/m68knommu/platform/528x/config.c b/arch/m68knommu/platform/528x/config.c
index a1d1a61c4fe6..6e608d1836f1 100644
--- a/arch/m68knommu/platform/528x/config.c
+++ b/arch/m68knommu/platform/528x/config.c
@@ -3,8 +3,8 @@
3/* 3/*
4 * linux/arch/m68knommu/platform/528x/config.c 4 * linux/arch/m68knommu/platform/528x/config.c
5 * 5 *
6 * Sub-architcture dependant initialization code for the Motorola 6 * Sub-architcture dependant initialization code for the Freescale
7 * 5280 and 5282 CPUs. 7 * 5280, 5281 and 5282 CPUs.
8 * 8 *
9 * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com) 9 * Copyright (C) 1999-2003, Greg Ungerer (gerg@snapgear.com)
10 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com) 10 * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
@@ -15,20 +15,13 @@
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/param.h> 16#include <linux/param.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/platform_device.h> 18#include <linux/platform_device.h>
20#include <linux/spi/spi.h>
21#include <linux/spi/flash.h>
22#include <linux/io.h> 19#include <linux/io.h>
23#include <asm/machdep.h> 20#include <asm/machdep.h>
24#include <asm/coldfire.h> 21#include <asm/coldfire.h>
25#include <asm/mcfsim.h> 22#include <asm/mcfsim.h>
26#include <asm/mcfuart.h> 23#include <asm/mcfuart.h>
27 24
28#ifdef CONFIG_MTD_PARTITIONS
29#include <linux/mtd/partitions.h>
30#endif
31
32/***************************************************************************/ 25/***************************************************************************/
33 26
34static struct mcf_platform_uart m528x_uart_platform[] = { 27static struct mcf_platform_uart m528x_uart_platform[] = {
@@ -91,23 +84,13 @@ static struct platform_device *m528x_devices[] __initdata = {
91 84
92/***************************************************************************/ 85/***************************************************************************/
93 86
94#define INTC0 (MCF_MBAR + MCFICM_INTC0)
95
96static void __init m528x_uart_init_line(int line, int irq) 87static void __init m528x_uart_init_line(int line, int irq)
97{ 88{
98 u8 port; 89 u8 port;
99 u32 imr;
100 90
101 if ((line < 0) || (line > 2)) 91 if ((line < 0) || (line > 2))
102 return; 92 return;
103 93
104 /* level 6, line based priority */
105 writeb(0x30+line, INTC0 + MCFINTC_ICR0 + MCFINT_UART0 + line);
106
107 imr = readl(INTC0 + MCFINTC_IMRL);
108 imr &= ~((1 << (irq - MCFINT_VECBASE)) | 1);
109 writel(imr, INTC0 + MCFINTC_IMRL);
110
111 /* make sure PUAPAR is set for UART0 and UART1 */ 94 /* make sure PUAPAR is set for UART0 and UART1 */
112 if (line < 2) { 95 if (line < 2) {
113 port = readb(MCF_MBAR + MCF5282_GPIO_PUAPAR); 96 port = readb(MCF_MBAR + MCF5282_GPIO_PUAPAR);
@@ -129,21 +112,8 @@ static void __init m528x_uarts_init(void)
129 112
130static void __init m528x_fec_init(void) 113static void __init m528x_fec_init(void)
131{ 114{
132 u32 imr;
133 u16 v16; 115 u16 v16;
134 116
135 /* Unmask FEC interrupts at ColdFire interrupt controller */
136 writeb(0x28, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 23);
137 writeb(0x27, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 27);
138 writeb(0x26, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_ICR0 + 29);
139
140 imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
141 imr &= ~0xf;
142 writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH);
143 imr = readl(MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
144 imr &= ~0xff800001;
145 writel(imr, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
146
147 /* Set multi-function pins to ethernet mode for fec0 */ 117 /* Set multi-function pins to ethernet mode for fec0 */
148 v16 = readw(MCF_IPSBAR + 0x100056); 118 v16 = readw(MCF_IPSBAR + 0x100056);
149 writew(v16 | 0xf00, MCF_IPSBAR + 0x100056); 119 writew(v16 | 0xf00, MCF_IPSBAR + 0x100056);
@@ -152,21 +122,6 @@ static void __init m528x_fec_init(void)
152 122
153/***************************************************************************/ 123/***************************************************************************/
154 124
155void mcf_disableall(void)
156{
157 *((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRH)) = 0xffffffff;
158 *((volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL)) = 0xffffffff;
159}
160
161/***************************************************************************/
162
163void mcf_autovector(unsigned int vec)
164{
165 /* Everything is auto-vectored on the 5272 */
166}
167
168/***************************************************************************/
169
170static void m528x_cpu_reset(void) 125static void m528x_cpu_reset(void)
171{ 126{
172 local_irq_disable(); 127 local_irq_disable();
@@ -204,8 +159,6 @@ void wildfiremod_halt(void)
204 159
205void __init config_BSP(char *commandp, int size) 160void __init config_BSP(char *commandp, int size)
206{ 161{
207 mcf_disableall();
208
209#ifdef CONFIG_WILDFIRE 162#ifdef CONFIG_WILDFIRE
210 mach_halt = wildfire_halt; 163 mach_halt = wildfire_halt;
211#endif 164#endif
diff --git a/arch/m68knommu/platform/528x/gpio.c b/arch/m68knommu/platform/528x/gpio.c
new file mode 100644
index 000000000000..ec593950696a
--- /dev/null
+++ b/arch/m68knommu/platform/528x/gpio.c
@@ -0,0 +1,438 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "NQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .base = 1,
34 .ngpio = 8,
35 },
36 .pddr = MCFEPORT_EPDDR,
37 .podr = MCFEPORT_EPDR,
38 .ppdr = MCFEPORT_EPPDR,
39 },
40 {
41 .gpio_chip = {
42 .label = "TA",
43 .request = mcf_gpio_request,
44 .free = mcf_gpio_free,
45 .direction_input = mcf_gpio_direction_input,
46 .direction_output = mcf_gpio_direction_output,
47 .get = mcf_gpio_get_value,
48 .set = mcf_gpio_set_value_fast,
49 .base = 8,
50 .ngpio = 4,
51 },
52 .pddr = MCFGPTA_GPTDDR,
53 .podr = MCFGPTA_GPTPORT,
54 .ppdr = MCFGPTB_GPTPORT,
55 },
56 {
57 .gpio_chip = {
58 .label = "TB",
59 .request = mcf_gpio_request,
60 .free = mcf_gpio_free,
61 .direction_input = mcf_gpio_direction_input,
62 .direction_output = mcf_gpio_direction_output,
63 .get = mcf_gpio_get_value,
64 .set = mcf_gpio_set_value_fast,
65 .base = 16,
66 .ngpio = 4,
67 },
68 .pddr = MCFGPTB_GPTDDR,
69 .podr = MCFGPTB_GPTPORT,
70 .ppdr = MCFGPTB_GPTPORT,
71 },
72 {
73 .gpio_chip = {
74 .label = "QA",
75 .request = mcf_gpio_request,
76 .free = mcf_gpio_free,
77 .direction_input = mcf_gpio_direction_input,
78 .direction_output = mcf_gpio_direction_output,
79 .get = mcf_gpio_get_value,
80 .set = mcf_gpio_set_value_fast,
81 .base = 24,
82 .ngpio = 4,
83 },
84 .pddr = MCFQADC_DDRQA,
85 .podr = MCFQADC_PORTQA,
86 .ppdr = MCFQADC_PORTQA,
87 },
88 {
89 .gpio_chip = {
90 .label = "QB",
91 .request = mcf_gpio_request,
92 .free = mcf_gpio_free,
93 .direction_input = mcf_gpio_direction_input,
94 .direction_output = mcf_gpio_direction_output,
95 .get = mcf_gpio_get_value,
96 .set = mcf_gpio_set_value_fast,
97 .base = 32,
98 .ngpio = 4,
99 },
100 .pddr = MCFQADC_DDRQB,
101 .podr = MCFQADC_PORTQB,
102 .ppdr = MCFQADC_PORTQB,
103 },
104 {
105 .gpio_chip = {
106 .label = "A",
107 .request = mcf_gpio_request,
108 .free = mcf_gpio_free,
109 .direction_input = mcf_gpio_direction_input,
110 .direction_output = mcf_gpio_direction_output,
111 .get = mcf_gpio_get_value,
112 .set = mcf_gpio_set_value_fast,
113 .base = 40,
114 .ngpio = 8,
115 },
116 .pddr = MCFGPIO_DDRA,
117 .podr = MCFGPIO_PORTA,
118 .ppdr = MCFGPIO_PORTAP,
119 .setr = MCFGPIO_SETA,
120 .clrr = MCFGPIO_CLRA,
121 },
122 {
123 .gpio_chip = {
124 .label = "B",
125 .request = mcf_gpio_request,
126 .free = mcf_gpio_free,
127 .direction_input = mcf_gpio_direction_input,
128 .direction_output = mcf_gpio_direction_output,
129 .get = mcf_gpio_get_value,
130 .set = mcf_gpio_set_value_fast,
131 .base = 48,
132 .ngpio = 8,
133 },
134 .pddr = MCFGPIO_DDRB,
135 .podr = MCFGPIO_PORTB,
136 .ppdr = MCFGPIO_PORTBP,
137 .setr = MCFGPIO_SETB,
138 .clrr = MCFGPIO_CLRB,
139 },
140 {
141 .gpio_chip = {
142 .label = "C",
143 .request = mcf_gpio_request,
144 .free = mcf_gpio_free,
145 .direction_input = mcf_gpio_direction_input,
146 .direction_output = mcf_gpio_direction_output,
147 .get = mcf_gpio_get_value,
148 .set = mcf_gpio_set_value_fast,
149 .base = 56,
150 .ngpio = 8,
151 },
152 .pddr = MCFGPIO_DDRC,
153 .podr = MCFGPIO_PORTC,
154 .ppdr = MCFGPIO_PORTCP,
155 .setr = MCFGPIO_SETC,
156 .clrr = MCFGPIO_CLRC,
157 },
158 {
159 .gpio_chip = {
160 .label = "D",
161 .request = mcf_gpio_request,
162 .free = mcf_gpio_free,
163 .direction_input = mcf_gpio_direction_input,
164 .direction_output = mcf_gpio_direction_output,
165 .get = mcf_gpio_get_value,
166 .set = mcf_gpio_set_value_fast,
167 .base = 64,
168 .ngpio = 8,
169 },
170 .pddr = MCFGPIO_DDRD,
171 .podr = MCFGPIO_PORTD,
172 .ppdr = MCFGPIO_PORTDP,
173 .setr = MCFGPIO_SETD,
174 .clrr = MCFGPIO_CLRD,
175 },
176 {
177 .gpio_chip = {
178 .label = "E",
179 .request = mcf_gpio_request,
180 .free = mcf_gpio_free,
181 .direction_input = mcf_gpio_direction_input,
182 .direction_output = mcf_gpio_direction_output,
183 .get = mcf_gpio_get_value,
184 .set = mcf_gpio_set_value_fast,
185 .base = 72,
186 .ngpio = 8,
187 },
188 .pddr = MCFGPIO_DDRE,
189 .podr = MCFGPIO_PORTE,
190 .ppdr = MCFGPIO_PORTEP,
191 .setr = MCFGPIO_SETE,
192 .clrr = MCFGPIO_CLRE,
193 },
194 {
195 .gpio_chip = {
196 .label = "F",
197 .request = mcf_gpio_request,
198 .free = mcf_gpio_free,
199 .direction_input = mcf_gpio_direction_input,
200 .direction_output = mcf_gpio_direction_output,
201 .get = mcf_gpio_get_value,
202 .set = mcf_gpio_set_value_fast,
203 .base = 80,
204 .ngpio = 8,
205 },
206 .pddr = MCFGPIO_DDRF,
207 .podr = MCFGPIO_PORTF,
208 .ppdr = MCFGPIO_PORTFP,
209 .setr = MCFGPIO_SETF,
210 .clrr = MCFGPIO_CLRF,
211 },
212 {
213 .gpio_chip = {
214 .label = "G",
215 .request = mcf_gpio_request,
216 .free = mcf_gpio_free,
217 .direction_input = mcf_gpio_direction_input,
218 .direction_output = mcf_gpio_direction_output,
219 .get = mcf_gpio_get_value,
220 .set = mcf_gpio_set_value_fast,
221 .base = 88,
222 .ngpio = 8,
223 },
224 .pddr = MCFGPIO_DDRG,
225 .podr = MCFGPIO_PORTG,
226 .ppdr = MCFGPIO_PORTGP,
227 .setr = MCFGPIO_SETG,
228 .clrr = MCFGPIO_CLRG,
229 },
230 {
231 .gpio_chip = {
232 .label = "H",
233 .request = mcf_gpio_request,
234 .free = mcf_gpio_free,
235 .direction_input = mcf_gpio_direction_input,
236 .direction_output = mcf_gpio_direction_output,
237 .get = mcf_gpio_get_value,
238 .set = mcf_gpio_set_value_fast,
239 .base = 96,
240 .ngpio = 8,
241 },
242 .pddr = MCFGPIO_DDRH,
243 .podr = MCFGPIO_PORTH,
244 .ppdr = MCFGPIO_PORTHP,
245 .setr = MCFGPIO_SETH,
246 .clrr = MCFGPIO_CLRH,
247 },
248 {
249 .gpio_chip = {
250 .label = "J",
251 .request = mcf_gpio_request,
252 .free = mcf_gpio_free,
253 .direction_input = mcf_gpio_direction_input,
254 .direction_output = mcf_gpio_direction_output,
255 .get = mcf_gpio_get_value,
256 .set = mcf_gpio_set_value_fast,
257 .base = 104,
258 .ngpio = 8,
259 },
260 .pddr = MCFGPIO_DDRJ,
261 .podr = MCFGPIO_PORTJ,
262 .ppdr = MCFGPIO_PORTJP,
263 .setr = MCFGPIO_SETJ,
264 .clrr = MCFGPIO_CLRJ,
265 },
266 {
267 .gpio_chip = {
268 .label = "DD",
269 .request = mcf_gpio_request,
270 .free = mcf_gpio_free,
271 .direction_input = mcf_gpio_direction_input,
272 .direction_output = mcf_gpio_direction_output,
273 .get = mcf_gpio_get_value,
274 .set = mcf_gpio_set_value_fast,
275 .base = 112,
276 .ngpio = 8,
277 },
278 .pddr = MCFGPIO_DDRDD,
279 .podr = MCFGPIO_PORTDD,
280 .ppdr = MCFGPIO_PORTDDP,
281 .setr = MCFGPIO_SETDD,
282 .clrr = MCFGPIO_CLRDD,
283 },
284 {
285 .gpio_chip = {
286 .label = "EH",
287 .request = mcf_gpio_request,
288 .free = mcf_gpio_free,
289 .direction_input = mcf_gpio_direction_input,
290 .direction_output = mcf_gpio_direction_output,
291 .get = mcf_gpio_get_value,
292 .set = mcf_gpio_set_value_fast,
293 .base = 120,
294 .ngpio = 8,
295 },
296 .pddr = MCFGPIO_DDREH,
297 .podr = MCFGPIO_PORTEH,
298 .ppdr = MCFGPIO_PORTEHP,
299 .setr = MCFGPIO_SETEH,
300 .clrr = MCFGPIO_CLREH,
301 },
302 {
303 .gpio_chip = {
304 .label = "EL",
305 .request = mcf_gpio_request,
306 .free = mcf_gpio_free,
307 .direction_input = mcf_gpio_direction_input,
308 .direction_output = mcf_gpio_direction_output,
309 .get = mcf_gpio_get_value,
310 .set = mcf_gpio_set_value_fast,
311 .base = 128,
312 .ngpio = 8,
313 },
314 .pddr = MCFGPIO_DDREL,
315 .podr = MCFGPIO_PORTEL,
316 .ppdr = MCFGPIO_PORTELP,
317 .setr = MCFGPIO_SETEL,
318 .clrr = MCFGPIO_CLREL,
319 },
320 {
321 .gpio_chip = {
322 .label = "AS",
323 .request = mcf_gpio_request,
324 .free = mcf_gpio_free,
325 .direction_input = mcf_gpio_direction_input,
326 .direction_output = mcf_gpio_direction_output,
327 .get = mcf_gpio_get_value,
328 .set = mcf_gpio_set_value_fast,
329 .base = 136,
330 .ngpio = 6,
331 },
332 .pddr = MCFGPIO_DDRAS,
333 .podr = MCFGPIO_PORTAS,
334 .ppdr = MCFGPIO_PORTASP,
335 .setr = MCFGPIO_SETAS,
336 .clrr = MCFGPIO_CLRAS,
337 },
338 {
339 .gpio_chip = {
340 .label = "QS",
341 .request = mcf_gpio_request,
342 .free = mcf_gpio_free,
343 .direction_input = mcf_gpio_direction_input,
344 .direction_output = mcf_gpio_direction_output,
345 .get = mcf_gpio_get_value,
346 .set = mcf_gpio_set_value_fast,
347 .base = 144,
348 .ngpio = 7,
349 },
350 .pddr = MCFGPIO_DDRQS,
351 .podr = MCFGPIO_PORTQS,
352 .ppdr = MCFGPIO_PORTQSP,
353 .setr = MCFGPIO_SETQS,
354 .clrr = MCFGPIO_CLRQS,
355 },
356 {
357 .gpio_chip = {
358 .label = "SD",
359 .request = mcf_gpio_request,
360 .free = mcf_gpio_free,
361 .direction_input = mcf_gpio_direction_input,
362 .direction_output = mcf_gpio_direction_output,
363 .get = mcf_gpio_get_value,
364 .set = mcf_gpio_set_value_fast,
365 .base = 152,
366 .ngpio = 6,
367 },
368 .pddr = MCFGPIO_DDRSD,
369 .podr = MCFGPIO_PORTSD,
370 .ppdr = MCFGPIO_PORTSDP,
371 .setr = MCFGPIO_SETSD,
372 .clrr = MCFGPIO_CLRSD,
373 },
374 {
375 .gpio_chip = {
376 .label = "TC",
377 .request = mcf_gpio_request,
378 .free = mcf_gpio_free,
379 .direction_input = mcf_gpio_direction_input,
380 .direction_output = mcf_gpio_direction_output,
381 .get = mcf_gpio_get_value,
382 .set = mcf_gpio_set_value_fast,
383 .base = 160,
384 .ngpio = 4,
385 },
386 .pddr = MCFGPIO_DDRTC,
387 .podr = MCFGPIO_PORTTC,
388 .ppdr = MCFGPIO_PORTTCP,
389 .setr = MCFGPIO_SETTC,
390 .clrr = MCFGPIO_CLRTC,
391 },
392 {
393 .gpio_chip = {
394 .label = "TD",
395 .request = mcf_gpio_request,
396 .free = mcf_gpio_free,
397 .direction_input = mcf_gpio_direction_input,
398 .direction_output = mcf_gpio_direction_output,
399 .get = mcf_gpio_get_value,
400 .set = mcf_gpio_set_value_fast,
401 .base = 168,
402 .ngpio = 4,
403 },
404 .pddr = MCFGPIO_DDRTD,
405 .podr = MCFGPIO_PORTTD,
406 .ppdr = MCFGPIO_PORTTDP,
407 .setr = MCFGPIO_SETTD,
408 .clrr = MCFGPIO_CLRTD,
409 },
410 {
411 .gpio_chip = {
412 .label = "UA",
413 .request = mcf_gpio_request,
414 .free = mcf_gpio_free,
415 .direction_input = mcf_gpio_direction_input,
416 .direction_output = mcf_gpio_direction_output,
417 .get = mcf_gpio_get_value,
418 .set = mcf_gpio_set_value_fast,
419 .base = 176,
420 .ngpio = 4,
421 },
422 .pddr = MCFGPIO_DDRUA,
423 .podr = MCFGPIO_PORTUA,
424 .ppdr = MCFGPIO_PORTUAP,
425 .setr = MCFGPIO_SETUA,
426 .clrr = MCFGPIO_CLRUA,
427 },
428};
429
430static int __init mcf_gpio_init(void)
431{
432 unsigned i = 0;
433 while (i < ARRAY_SIZE(mcf_gpio_chips))
434 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
435 return 0;
436}
437
438core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/5307/Makefile b/arch/m68knommu/platform/5307/Makefile
index cfd586860fd8..667db6598451 100644
--- a/arch/m68knommu/platform/5307/Makefile
+++ b/arch/m68knommu/platform/5307/Makefile
@@ -14,5 +14,5 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y += config.o 17obj-y += config.o gpio.o
18 18
diff --git a/arch/m68knommu/platform/5307/config.c b/arch/m68knommu/platform/5307/config.c
index 39da9e9ff674..00900ac06a9c 100644
--- a/arch/m68knommu/platform/5307/config.c
+++ b/arch/m68knommu/platform/5307/config.c
@@ -21,12 +21,6 @@
21 21
22/***************************************************************************/ 22/***************************************************************************/
23 23
24extern unsigned int mcf_timervector;
25extern unsigned int mcf_profilevector;
26extern unsigned int mcf_timerlevel;
27
28/***************************************************************************/
29
30/* 24/*
31 * Some platforms need software versions of the GPIO data registers. 25 * Some platforms need software versions of the GPIO data registers.
32 */ 26 */
@@ -64,11 +58,11 @@ static void __init m5307_uart_init_line(int line, int irq)
64 if (line == 0) { 58 if (line == 0) {
65 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 59 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
66 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR); 60 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
67 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); 61 mcf_mapirq2imr(irq, MCFINTC_UART0);
68 } else if (line == 1) { 62 } else if (line == 1) {
69 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 63 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
70 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); 64 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
71 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); 65 mcf_mapirq2imr(irq, MCFINTC_UART1);
72 } 66 }
73} 67}
74 68
@@ -83,35 +77,19 @@ static void __init m5307_uarts_init(void)
83 77
84/***************************************************************************/ 78/***************************************************************************/
85 79
86void mcf_autovector(unsigned int vec) 80static void __init m5307_timers_init(void)
87{
88 volatile unsigned char *mbar;
89
90 if ((vec >= 25) && (vec <= 31)) {
91 mbar = (volatile unsigned char *) MCF_MBAR;
92 vec = 0x1 << (vec - 24);
93 *(mbar + MCFSIM_AVR) |= vec;
94 mcf_setimr(mcf_getimr() & ~vec);
95 }
96}
97
98/***************************************************************************/
99
100void mcf_settimericr(unsigned int timer, unsigned int level)
101{ 81{
102 volatile unsigned char *icrp; 82 /* Timer1 is always used as system timer */
103 unsigned int icr, imr; 83 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
104 84 MCF_MBAR + MCFSIM_TIMER1ICR);
105 if (timer <= 2) { 85 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
106 switch (timer) { 86
107 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break; 87#ifdef CONFIG_HIGHPROFILE
108 default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break; 88 /* Timer2 is to be used as a high speed profile timer */
109 } 89 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
110 90 MCF_MBAR + MCFSIM_TIMER2ICR);
111 icrp = (volatile unsigned char *) (MCF_MBAR + icr); 91 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
112 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3; 92#endif
113 mcf_setimr(mcf_getimr() & ~imr);
114 }
115} 93}
116 94
117/***************************************************************************/ 95/***************************************************************************/
@@ -129,20 +107,22 @@ void m5307_cpu_reset(void)
129 107
130void __init config_BSP(char *commandp, int size) 108void __init config_BSP(char *commandp, int size)
131{ 109{
132 mcf_setimr(MCFSIM_IMR_MASKALL);
133
134#if defined(CONFIG_NETtel) || \ 110#if defined(CONFIG_NETtel) || \
135 defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA) 111 defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA)
136 /* Copy command line from FLASH to local buffer... */ 112 /* Copy command line from FLASH to local buffer... */
137 memcpy(commandp, (char *) 0xf0004000, size); 113 memcpy(commandp, (char *) 0xf0004000, size);
138 commandp[size-1] = 0; 114 commandp[size-1] = 0;
139 /* Different timer setup - to prevent device clash */
140 mcf_timervector = 30;
141 mcf_profilevector = 31;
142 mcf_timerlevel = 6;
143#endif 115#endif
144 116
145 mach_reset = m5307_cpu_reset; 117 mach_reset = m5307_cpu_reset;
118 m5307_timers_init();
119 m5307_uarts_init();
120
121 /* Only support the external interrupts on their primary level */
122 mcf_mapirq2imr(25, MCFINTC_EINT1);
123 mcf_mapirq2imr(27, MCFINTC_EINT3);
124 mcf_mapirq2imr(29, MCFINTC_EINT5);
125 mcf_mapirq2imr(31, MCFINTC_EINT7);
146 126
147#ifdef CONFIG_BDM_DISABLE 127#ifdef CONFIG_BDM_DISABLE
148 /* 128 /*
@@ -158,7 +138,6 @@ void __init config_BSP(char *commandp, int size)
158 138
159static int __init init_BSP(void) 139static int __init init_BSP(void)
160{ 140{
161 m5307_uarts_init();
162 platform_add_devices(m5307_devices, ARRAY_SIZE(m5307_devices)); 141 platform_add_devices(m5307_devices, ARRAY_SIZE(m5307_devices));
163 return 0; 142 return 0;
164} 143}
diff --git a/arch/m68knommu/platform/5307/gpio.c b/arch/m68knommu/platform/5307/gpio.c
new file mode 100644
index 000000000000..8da5880e4066
--- /dev/null
+++ b/arch/m68knommu/platform/5307/gpio.c
@@ -0,0 +1,49 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PP",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 16,
34 },
35 .pddr = MCFSIM_PADDR,
36 .podr = MCFSIM_PADAT,
37 .ppdr = MCFSIM_PADAT,
38 },
39};
40
41static int __init mcf_gpio_init(void)
42{
43 unsigned i = 0;
44 while (i < ARRAY_SIZE(mcf_gpio_chips))
45 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
46 return 0;
47}
48
49core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/532x/Makefile b/arch/m68knommu/platform/532x/Makefile
index e431912f5628..4cc23245bcd1 100644
--- a/arch/m68knommu/platform/532x/Makefile
+++ b/arch/m68knommu/platform/532x/Makefile
@@ -15,4 +15,4 @@
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17#obj-y := config.o usb-mcf532x.o spi-mcf532x.o 17#obj-y := config.o usb-mcf532x.o spi-mcf532x.o
18obj-y := config.o 18obj-y := config.o gpio.o
diff --git a/arch/m68knommu/platform/532x/config.c b/arch/m68knommu/platform/532x/config.c
index cdb761971f7a..d632948e64e5 100644
--- a/arch/m68knommu/platform/532x/config.c
+++ b/arch/m68knommu/platform/532x/config.c
@@ -20,7 +20,6 @@
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/param.h> 21#include <linux/param.h>
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/io.h> 23#include <linux/io.h>
25#include <asm/machdep.h> 24#include <asm/machdep.h>
26#include <asm/coldfire.h> 25#include <asm/coldfire.h>
@@ -31,12 +30,6 @@
31 30
32/***************************************************************************/ 31/***************************************************************************/
33 32
34extern unsigned int mcf_timervector;
35extern unsigned int mcf_profilevector;
36extern unsigned int mcf_timerlevel;
37
38/***************************************************************************/
39
40static struct mcf_platform_uart m532x_uart_platform[] = { 33static struct mcf_platform_uart m532x_uart_platform[] = {
41 { 34 {
42 .mapbase = MCFUART_BASE1, 35 .mapbase = MCFUART_BASE1,
@@ -88,6 +81,7 @@ static struct platform_device m532x_fec = {
88 .num_resources = ARRAY_SIZE(m532x_fec_resources), 81 .num_resources = ARRAY_SIZE(m532x_fec_resources),
89 .resource = m532x_fec_resources, 82 .resource = m532x_fec_resources,
90}; 83};
84
91static struct platform_device *m532x_devices[] __initdata = { 85static struct platform_device *m532x_devices[] __initdata = {
92 &m532x_uart, 86 &m532x_uart,
93 &m532x_fec, 87 &m532x_fec,
@@ -98,18 +92,11 @@ static struct platform_device *m532x_devices[] __initdata = {
98static void __init m532x_uart_init_line(int line, int irq) 92static void __init m532x_uart_init_line(int line, int irq)
99{ 93{
100 if (line == 0) { 94 if (line == 0) {
101 MCF_INTC0_ICR26 = 0x3;
102 MCF_INTC0_CIMR = 26;
103 /* GPIO initialization */ 95 /* GPIO initialization */
104 MCF_GPIO_PAR_UART |= 0x000F; 96 MCF_GPIO_PAR_UART |= 0x000F;
105 } else if (line == 1) { 97 } else if (line == 1) {
106 MCF_INTC0_ICR27 = 0x3;
107 MCF_INTC0_CIMR = 27;
108 /* GPIO initialization */ 98 /* GPIO initialization */
109 MCF_GPIO_PAR_UART |= 0x0FF0; 99 MCF_GPIO_PAR_UART |= 0x0FF0;
110 } else if (line == 2) {
111 MCF_INTC0_ICR28 = 0x3;
112 MCF_INTC0_CIMR = 28;
113 } 100 }
114} 101}
115 102
@@ -125,14 +112,6 @@ static void __init m532x_uarts_init(void)
125 112
126static void __init m532x_fec_init(void) 113static void __init m532x_fec_init(void)
127{ 114{
128 /* Unmask FEC interrupts at ColdFire interrupt controller */
129 MCF_INTC0_ICR36 = 0x2;
130 MCF_INTC0_ICR40 = 0x2;
131 MCF_INTC0_ICR42 = 0x2;
132
133 MCF_INTC0_IMRH &= ~(MCF_INTC_IMRH_INT_MASK36 |
134 MCF_INTC_IMRH_INT_MASK40 | MCF_INTC_IMRH_INT_MASK42);
135
136 /* Set multi-function pins to ethernet mode for fec0 */ 115 /* Set multi-function pins to ethernet mode for fec0 */
137 MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC | 116 MCF_GPIO_PAR_FECI2C |= (MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
138 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO); 117 MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO);
@@ -142,26 +121,6 @@ static void __init m532x_fec_init(void)
142 121
143/***************************************************************************/ 122/***************************************************************************/
144 123
145void mcf_settimericr(unsigned int timer, unsigned int level)
146{
147 volatile unsigned char *icrp;
148 unsigned int icr;
149 unsigned char irq;
150
151 if (timer <= 2) {
152 switch (timer) {
153 case 2: irq = 33; icr = MCFSIM_ICR_TIMER2; break;
154 default: irq = 32; icr = MCFSIM_ICR_TIMER1; break;
155 }
156
157 icrp = (volatile unsigned char *) (icr);
158 *icrp = level;
159 mcf_enable_irq0(irq);
160 }
161}
162
163/***************************************************************************/
164
165static void m532x_cpu_reset(void) 124static void m532x_cpu_reset(void)
166{ 125{
167 local_irq_disable(); 126 local_irq_disable();
@@ -172,8 +131,6 @@ static void m532x_cpu_reset(void)
172 131
173void __init config_BSP(char *commandp, int size) 132void __init config_BSP(char *commandp, int size)
174{ 133{
175 mcf_setimr(MCFSIM_IMR_MASKALL);
176
177#if !defined(CONFIG_BOOTPARAM) 134#if !defined(CONFIG_BOOTPARAM)
178 /* Copy command line from FLASH to local buffer... */ 135 /* Copy command line from FLASH to local buffer... */
179 memcpy(commandp, (char *) 0x4000, 4); 136 memcpy(commandp, (char *) 0x4000, 4);
@@ -185,10 +142,6 @@ void __init config_BSP(char *commandp, int size)
185 } 142 }
186#endif 143#endif
187 144
188 mcf_timervector = 64+32;
189 mcf_profilevector = 64+33;
190 mach_reset = m532x_cpu_reset;
191
192#ifdef CONFIG_BDM_DISABLE 145#ifdef CONFIG_BDM_DISABLE
193 /* 146 /*
194 * Disable the BDM clocking. This also turns off most of the rest of 147 * Disable the BDM clocking. This also turns off most of the rest of
@@ -438,8 +391,8 @@ void gpio_init(void)
438 /* Initialize TIN3 as a GPIO output to enable the write 391 /* Initialize TIN3 as a GPIO output to enable the write
439 half of the latch */ 392 half of the latch */
440 MCF_GPIO_PAR_TIMER = 0x00; 393 MCF_GPIO_PAR_TIMER = 0x00;
441 MCF_GPIO_PDDR_TIMER = 0x08; 394 __raw_writeb(0x08, MCFGPIO_PDDR_TIMER);
442 MCF_GPIO_PCLRR_TIMER = 0x0; 395 __raw_writeb(0x00, MCFGPIO_PCLRR_TIMER);
443 396
444} 397}
445 398
diff --git a/arch/m68knommu/platform/532x/gpio.c b/arch/m68knommu/platform/532x/gpio.c
new file mode 100644
index 000000000000..184b77382c3d
--- /dev/null
+++ b/arch/m68knommu/platform/532x/gpio.c
@@ -0,0 +1,337 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PIRQ",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 8,
34 },
35 .pddr = MCFEPORT_EPDDR,
36 .podr = MCFEPORT_EPDR,
37 .ppdr = MCFEPORT_EPPDR,
38 },
39 {
40 .gpio_chip = {
41 .label = "FECH",
42 .request = mcf_gpio_request,
43 .free = mcf_gpio_free,
44 .direction_input = mcf_gpio_direction_input,
45 .direction_output = mcf_gpio_direction_output,
46 .get = mcf_gpio_get_value,
47 .set = mcf_gpio_set_value_fast,
48 .base = 8,
49 .ngpio = 8,
50 },
51 .pddr = MCFGPIO_PDDR_FECH,
52 .podr = MCFGPIO_PODR_FECH,
53 .ppdr = MCFGPIO_PPDSDR_FECH,
54 .setr = MCFGPIO_PPDSDR_FECH,
55 .clrr = MCFGPIO_PCLRR_FECH,
56 },
57 {
58 .gpio_chip = {
59 .label = "FECL",
60 .request = mcf_gpio_request,
61 .free = mcf_gpio_free,
62 .direction_input = mcf_gpio_direction_input,
63 .direction_output = mcf_gpio_direction_output,
64 .get = mcf_gpio_get_value,
65 .set = mcf_gpio_set_value_fast,
66 .base = 16,
67 .ngpio = 8,
68 },
69 .pddr = MCFGPIO_PDDR_FECL,
70 .podr = MCFGPIO_PODR_FECL,
71 .ppdr = MCFGPIO_PPDSDR_FECL,
72 .setr = MCFGPIO_PPDSDR_FECL,
73 .clrr = MCFGPIO_PCLRR_FECL,
74 },
75 {
76 .gpio_chip = {
77 .label = "SSI",
78 .request = mcf_gpio_request,
79 .free = mcf_gpio_free,
80 .direction_input = mcf_gpio_direction_input,
81 .direction_output = mcf_gpio_direction_output,
82 .get = mcf_gpio_get_value,
83 .set = mcf_gpio_set_value_fast,
84 .base = 24,
85 .ngpio = 5,
86 },
87 .pddr = MCFGPIO_PDDR_SSI,
88 .podr = MCFGPIO_PODR_SSI,
89 .ppdr = MCFGPIO_PPDSDR_SSI,
90 .setr = MCFGPIO_PPDSDR_SSI,
91 .clrr = MCFGPIO_PCLRR_SSI,
92 },
93 {
94 .gpio_chip = {
95 .label = "BUSCTL",
96 .request = mcf_gpio_request,
97 .free = mcf_gpio_free,
98 .direction_input = mcf_gpio_direction_input,
99 .direction_output = mcf_gpio_direction_output,
100 .get = mcf_gpio_get_value,
101 .set = mcf_gpio_set_value_fast,
102 .base = 32,
103 .ngpio = 4,
104 },
105 .pddr = MCFGPIO_PDDR_BUSCTL,
106 .podr = MCFGPIO_PODR_BUSCTL,
107 .ppdr = MCFGPIO_PPDSDR_BUSCTL,
108 .setr = MCFGPIO_PPDSDR_BUSCTL,
109 .clrr = MCFGPIO_PCLRR_BUSCTL,
110 },
111 {
112 .gpio_chip = {
113 .label = "BE",
114 .request = mcf_gpio_request,
115 .free = mcf_gpio_free,
116 .direction_input = mcf_gpio_direction_input,
117 .direction_output = mcf_gpio_direction_output,
118 .get = mcf_gpio_get_value,
119 .set = mcf_gpio_set_value_fast,
120 .base = 40,
121 .ngpio = 4,
122 },
123 .pddr = MCFGPIO_PDDR_BE,
124 .podr = MCFGPIO_PODR_BE,
125 .ppdr = MCFGPIO_PPDSDR_BE,
126 .setr = MCFGPIO_PPDSDR_BE,
127 .clrr = MCFGPIO_PCLRR_BE,
128 },
129 {
130 .gpio_chip = {
131 .label = "CS",
132 .request = mcf_gpio_request,
133 .free = mcf_gpio_free,
134 .direction_input = mcf_gpio_direction_input,
135 .direction_output = mcf_gpio_direction_output,
136 .get = mcf_gpio_get_value,
137 .set = mcf_gpio_set_value_fast,
138 .base = 49,
139 .ngpio = 5,
140 },
141 .pddr = MCFGPIO_PDDR_CS,
142 .podr = MCFGPIO_PODR_CS,
143 .ppdr = MCFGPIO_PPDSDR_CS,
144 .setr = MCFGPIO_PPDSDR_CS,
145 .clrr = MCFGPIO_PCLRR_CS,
146 },
147 {
148 .gpio_chip = {
149 .label = "PWM",
150 .request = mcf_gpio_request,
151 .free = mcf_gpio_free,
152 .direction_input = mcf_gpio_direction_input,
153 .direction_output = mcf_gpio_direction_output,
154 .get = mcf_gpio_get_value,
155 .set = mcf_gpio_set_value_fast,
156 .base = 58,
157 .ngpio = 4,
158 },
159 .pddr = MCFGPIO_PDDR_PWM,
160 .podr = MCFGPIO_PODR_PWM,
161 .ppdr = MCFGPIO_PPDSDR_PWM,
162 .setr = MCFGPIO_PPDSDR_PWM,
163 .clrr = MCFGPIO_PCLRR_PWM,
164 },
165 {
166 .gpio_chip = {
167 .label = "FECI2C",
168 .request = mcf_gpio_request,
169 .free = mcf_gpio_free,
170 .direction_input = mcf_gpio_direction_input,
171 .direction_output = mcf_gpio_direction_output,
172 .get = mcf_gpio_get_value,
173 .set = mcf_gpio_set_value_fast,
174 .base = 64,
175 .ngpio = 4,
176 },
177 .pddr = MCFGPIO_PDDR_FECI2C,
178 .podr = MCFGPIO_PODR_FECI2C,
179 .ppdr = MCFGPIO_PPDSDR_FECI2C,
180 .setr = MCFGPIO_PPDSDR_FECI2C,
181 .clrr = MCFGPIO_PCLRR_FECI2C,
182 },
183 {
184 .gpio_chip = {
185 .label = "UART",
186 .request = mcf_gpio_request,
187 .free = mcf_gpio_free,
188 .direction_input = mcf_gpio_direction_input,
189 .direction_output = mcf_gpio_direction_output,
190 .get = mcf_gpio_get_value,
191 .set = mcf_gpio_set_value_fast,
192 .base = 72,
193 .ngpio = 8,
194 },
195 .pddr = MCFGPIO_PDDR_UART,
196 .podr = MCFGPIO_PODR_UART,
197 .ppdr = MCFGPIO_PPDSDR_UART,
198 .setr = MCFGPIO_PPDSDR_UART,
199 .clrr = MCFGPIO_PCLRR_UART,
200 },
201 {
202 .gpio_chip = {
203 .label = "QSPI",
204 .request = mcf_gpio_request,
205 .free = mcf_gpio_free,
206 .direction_input = mcf_gpio_direction_input,
207 .direction_output = mcf_gpio_direction_output,
208 .get = mcf_gpio_get_value,
209 .set = mcf_gpio_set_value_fast,
210 .base = 80,
211 .ngpio = 6,
212 },
213 .pddr = MCFGPIO_PDDR_QSPI,
214 .podr = MCFGPIO_PODR_QSPI,
215 .ppdr = MCFGPIO_PPDSDR_QSPI,
216 .setr = MCFGPIO_PPDSDR_QSPI,
217 .clrr = MCFGPIO_PCLRR_QSPI,
218 },
219 {
220 .gpio_chip = {
221 .label = "TIMER",
222 .request = mcf_gpio_request,
223 .free = mcf_gpio_free,
224 .direction_input = mcf_gpio_direction_input,
225 .direction_output = mcf_gpio_direction_output,
226 .get = mcf_gpio_get_value,
227 .set = mcf_gpio_set_value_fast,
228 .base = 88,
229 .ngpio = 4,
230 },
231 .pddr = MCFGPIO_PDDR_TIMER,
232 .podr = MCFGPIO_PODR_TIMER,
233 .ppdr = MCFGPIO_PPDSDR_TIMER,
234 .setr = MCFGPIO_PPDSDR_TIMER,
235 .clrr = MCFGPIO_PCLRR_TIMER,
236 },
237 {
238 .gpio_chip = {
239 .label = "LCDDATAH",
240 .request = mcf_gpio_request,
241 .free = mcf_gpio_free,
242 .direction_input = mcf_gpio_direction_input,
243 .direction_output = mcf_gpio_direction_output,
244 .get = mcf_gpio_get_value,
245 .set = mcf_gpio_set_value_fast,
246 .base = 96,
247 .ngpio = 2,
248 },
249 .pddr = MCFGPIO_PDDR_LCDDATAH,
250 .podr = MCFGPIO_PODR_LCDDATAH,
251 .ppdr = MCFGPIO_PPDSDR_LCDDATAH,
252 .setr = MCFGPIO_PPDSDR_LCDDATAH,
253 .clrr = MCFGPIO_PCLRR_LCDDATAH,
254 },
255 {
256 .gpio_chip = {
257 .label = "LCDDATAM",
258 .request = mcf_gpio_request,
259 .free = mcf_gpio_free,
260 .direction_input = mcf_gpio_direction_input,
261 .direction_output = mcf_gpio_direction_output,
262 .get = mcf_gpio_get_value,
263 .set = mcf_gpio_set_value_fast,
264 .base = 104,
265 .ngpio = 8,
266 },
267 .pddr = MCFGPIO_PDDR_LCDDATAM,
268 .podr = MCFGPIO_PODR_LCDDATAM,
269 .ppdr = MCFGPIO_PPDSDR_LCDDATAM,
270 .setr = MCFGPIO_PPDSDR_LCDDATAM,
271 .clrr = MCFGPIO_PCLRR_LCDDATAM,
272 },
273 {
274 .gpio_chip = {
275 .label = "LCDDATAL",
276 .request = mcf_gpio_request,
277 .free = mcf_gpio_free,
278 .direction_input = mcf_gpio_direction_input,
279 .direction_output = mcf_gpio_direction_output,
280 .get = mcf_gpio_get_value,
281 .set = mcf_gpio_set_value_fast,
282 .base = 112,
283 .ngpio = 8,
284 },
285 .pddr = MCFGPIO_PDDR_LCDDATAL,
286 .podr = MCFGPIO_PODR_LCDDATAL,
287 .ppdr = MCFGPIO_PPDSDR_LCDDATAL,
288 .setr = MCFGPIO_PPDSDR_LCDDATAL,
289 .clrr = MCFGPIO_PCLRR_LCDDATAL,
290 },
291 {
292 .gpio_chip = {
293 .label = "LCDCTLH",
294 .request = mcf_gpio_request,
295 .free = mcf_gpio_free,
296 .direction_input = mcf_gpio_direction_input,
297 .direction_output = mcf_gpio_direction_output,
298 .get = mcf_gpio_get_value,
299 .set = mcf_gpio_set_value_fast,
300 .base = 120,
301 .ngpio = 1,
302 },
303 .pddr = MCFGPIO_PDDR_LCDCTLH,
304 .podr = MCFGPIO_PODR_LCDCTLH,
305 .ppdr = MCFGPIO_PPDSDR_LCDCTLH,
306 .setr = MCFGPIO_PPDSDR_LCDCTLH,
307 .clrr = MCFGPIO_PCLRR_LCDCTLH,
308 },
309 {
310 .gpio_chip = {
311 .label = "LCDCTLL",
312 .request = mcf_gpio_request,
313 .free = mcf_gpio_free,
314 .direction_input = mcf_gpio_direction_input,
315 .direction_output = mcf_gpio_direction_output,
316 .get = mcf_gpio_get_value,
317 .set = mcf_gpio_set_value_fast,
318 .base = 128,
319 .ngpio = 8,
320 },
321 .pddr = MCFGPIO_PDDR_LCDCTLL,
322 .podr = MCFGPIO_PODR_LCDCTLL,
323 .ppdr = MCFGPIO_PPDSDR_LCDCTLL,
324 .setr = MCFGPIO_PPDSDR_LCDCTLL,
325 .clrr = MCFGPIO_PCLRR_LCDCTLL,
326 },
327};
328
329static int __init mcf_gpio_init(void)
330{
331 unsigned i = 0;
332 while (i < ARRAY_SIZE(mcf_gpio_chips))
333 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
334 return 0;
335}
336
337core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/5407/Makefile b/arch/m68knommu/platform/5407/Makefile
index e6035e7a2d3f..dee62c5dbaa6 100644
--- a/arch/m68knommu/platform/5407/Makefile
+++ b/arch/m68knommu/platform/5407/Makefile
@@ -14,5 +14,5 @@
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-y := config.o 17obj-y := config.o gpio.o
18 18
diff --git a/arch/m68knommu/platform/5407/config.c b/arch/m68knommu/platform/5407/config.c
index b41d942bf8d0..70ea789a400c 100644
--- a/arch/m68knommu/platform/5407/config.c
+++ b/arch/m68knommu/platform/5407/config.c
@@ -20,12 +20,6 @@
20 20
21/***************************************************************************/ 21/***************************************************************************/
22 22
23extern unsigned int mcf_timervector;
24extern unsigned int mcf_profilevector;
25extern unsigned int mcf_timerlevel;
26
27/***************************************************************************/
28
29static struct mcf_platform_uart m5407_uart_platform[] = { 23static struct mcf_platform_uart m5407_uart_platform[] = {
30 { 24 {
31 .mapbase = MCF_MBAR + MCFUART_BASE1, 25 .mapbase = MCF_MBAR + MCFUART_BASE1,
@@ -55,11 +49,11 @@ static void __init m5407_uart_init_line(int line, int irq)
55 if (line == 0) { 49 if (line == 0) {
56 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR); 50 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCF_MBAR + MCFSIM_UART1ICR);
57 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR); 51 writeb(irq, MCF_MBAR + MCFUART_BASE1 + MCFUART_UIVR);
58 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART1); 52 mcf_mapirq2imr(irq, MCFINTC_UART0);
59 } else if (line == 1) { 53 } else if (line == 1) {
60 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR); 54 writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCF_MBAR + MCFSIM_UART2ICR);
61 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR); 55 writeb(irq, MCF_MBAR + MCFUART_BASE2 + MCFUART_UIVR);
62 mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_UART2); 56 mcf_mapirq2imr(irq, MCFINTC_UART1);
63 } 57 }
64} 58}
65 59
@@ -74,35 +68,19 @@ static void __init m5407_uarts_init(void)
74 68
75/***************************************************************************/ 69/***************************************************************************/
76 70
77void mcf_autovector(unsigned int vec) 71static void __init m5407_timers_init(void)
78{
79 volatile unsigned char *mbar;
80
81 if ((vec >= 25) && (vec <= 31)) {
82 mbar = (volatile unsigned char *) MCF_MBAR;
83 vec = 0x1 << (vec - 24);
84 *(mbar + MCFSIM_AVR) |= vec;
85 mcf_setimr(mcf_getimr() & ~vec);
86 }
87}
88
89/***************************************************************************/
90
91void mcf_settimericr(unsigned int timer, unsigned int level)
92{ 72{
93 volatile unsigned char *icrp; 73 /* Timer1 is always used as system timer */
94 unsigned int icr, imr; 74 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
95 75 MCF_MBAR + MCFSIM_TIMER1ICR);
96 if (timer <= 2) { 76 mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
97 switch (timer) { 77
98 case 2: icr = MCFSIM_TIMER2ICR; imr = MCFSIM_IMR_TIMER2; break; 78#ifdef CONFIG_HIGHPROFILE
99 default: icr = MCFSIM_TIMER1ICR; imr = MCFSIM_IMR_TIMER1; break; 79 /* Timer2 is to be used as a high speed profile timer */
100 } 80 writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
101 81 MCF_MBAR + MCFSIM_TIMER2ICR);
102 icrp = (volatile unsigned char *) (MCF_MBAR + icr); 82 mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
103 *icrp = MCFSIM_ICR_AUTOVEC | (level << 2) | MCFSIM_ICR_PRI3; 83#endif
104 mcf_setimr(mcf_getimr() & ~imr);
105 }
106} 84}
107 85
108/***************************************************************************/ 86/***************************************************************************/
@@ -120,23 +98,21 @@ void m5407_cpu_reset(void)
120 98
121void __init config_BSP(char *commandp, int size) 99void __init config_BSP(char *commandp, int size)
122{ 100{
123 mcf_setimr(MCFSIM_IMR_MASKALL);
124
125#if defined(CONFIG_CLEOPATRA)
126 /* Different timer setup - to prevent device clash */
127 mcf_timervector = 30;
128 mcf_profilevector = 31;
129 mcf_timerlevel = 6;
130#endif
131
132 mach_reset = m5407_cpu_reset; 101 mach_reset = m5407_cpu_reset;
102 m5407_timers_init();
103 m5407_uarts_init();
104
105 /* Only support the external interrupts on their primary level */
106 mcf_mapirq2imr(25, MCFINTC_EINT1);
107 mcf_mapirq2imr(27, MCFINTC_EINT3);
108 mcf_mapirq2imr(29, MCFINTC_EINT5);
109 mcf_mapirq2imr(31, MCFINTC_EINT7);
133} 110}
134 111
135/***************************************************************************/ 112/***************************************************************************/
136 113
137static int __init init_BSP(void) 114static int __init init_BSP(void)
138{ 115{
139 m5407_uarts_init();
140 platform_add_devices(m5407_devices, ARRAY_SIZE(m5407_devices)); 116 platform_add_devices(m5407_devices, ARRAY_SIZE(m5407_devices));
141 return 0; 117 return 0;
142} 118}
diff --git a/arch/m68knommu/platform/5407/gpio.c b/arch/m68knommu/platform/5407/gpio.c
new file mode 100644
index 000000000000..8da5880e4066
--- /dev/null
+++ b/arch/m68knommu/platform/5407/gpio.c
@@ -0,0 +1,49 @@
1/*
2 * Coldfire generic GPIO support
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14*/
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18
19#include <asm/coldfire.h>
20#include <asm/mcfsim.h>
21#include <asm/mcfgpio.h>
22
23static struct mcf_gpio_chip mcf_gpio_chips[] = {
24 {
25 .gpio_chip = {
26 .label = "PP",
27 .request = mcf_gpio_request,
28 .free = mcf_gpio_free,
29 .direction_input = mcf_gpio_direction_input,
30 .direction_output = mcf_gpio_direction_output,
31 .get = mcf_gpio_get_value,
32 .set = mcf_gpio_set_value,
33 .ngpio = 16,
34 },
35 .pddr = MCFSIM_PADDR,
36 .podr = MCFSIM_PADAT,
37 .ppdr = MCFSIM_PADAT,
38 },
39};
40
41static int __init mcf_gpio_init(void)
42{
43 unsigned i = 0;
44 while (i < ARRAY_SIZE(mcf_gpio_chips))
45 (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]);
46 return 0;
47}
48
49core_initcall(mcf_gpio_init);
diff --git a/arch/m68knommu/platform/68328/ints.c b/arch/m68knommu/platform/68328/ints.c
index 72e56d554f4f..b91ee85d4b5d 100644
--- a/arch/m68knommu/platform/68328/ints.c
+++ b/arch/m68knommu/platform/68328/ints.c
@@ -73,34 +73,6 @@ extern e_vector *_ramvec;
73/* The number of spurious interrupts */ 73/* The number of spurious interrupts */
74volatile unsigned int num_spurious; 74volatile unsigned int num_spurious;
75 75
76/*
77 * This function should be called during kernel startup to initialize
78 * the machine vector table.
79 */
80void __init init_vectors(void)
81{
82 int i;
83
84 /* set up the vectors */
85 for (i = 72; i < 256; ++i)
86 _ramvec[i] = (e_vector) bad_interrupt;
87
88 _ramvec[32] = system_call;
89
90 _ramvec[65] = (e_vector) inthandler1;
91 _ramvec[66] = (e_vector) inthandler2;
92 _ramvec[67] = (e_vector) inthandler3;
93 _ramvec[68] = (e_vector) inthandler4;
94 _ramvec[69] = (e_vector) inthandler5;
95 _ramvec[70] = (e_vector) inthandler6;
96 _ramvec[71] = (e_vector) inthandler7;
97
98 IVR = 0x40; /* Set DragonBall IVR (interrupt base) to 64 */
99
100 /* turn off all interrupts */
101 IMR = ~0;
102}
103
104/* The 68k family did not have a good way to determine the source 76/* The 68k family did not have a good way to determine the source
105 * of interrupts until later in the family. The EC000 core does 77 * of interrupts until later in the family. The EC000 core does
106 * not provide the vector number on the stack, we vector everything 78 * not provide the vector number on the stack, we vector everything
@@ -163,18 +135,54 @@ void process_int(int vec, struct pt_regs *fp)
163 } 135 }
164} 136}
165 137
166void enable_vector(unsigned int irq) 138static void intc_irq_unmask(unsigned int irq)
167{ 139{
168 IMR &= ~(1<<irq); 140 IMR &= ~(1<<irq);
169} 141}
170 142
171void disable_vector(unsigned int irq) 143static void intc_irq_mask(unsigned int irq)
172{ 144{
173 IMR |= (1<<irq); 145 IMR |= (1<<irq);
174} 146}
175 147
176void ack_vector(unsigned int irq) 148static struct irq_chip intc_irq_chip = {
149 .name = "M68K-INTC",
150 .mask = intc_irq_mask,
151 .unmask = intc_irq_unmask,
152};
153
154/*
155 * This function should be called during kernel startup to initialize
156 * the machine vector table.
157 */
158void __init init_IRQ(void)
177{ 159{
178 /* Nothing needed */ 160 int i;
161
162 /* set up the vectors */
163 for (i = 72; i < 256; ++i)
164 _ramvec[i] = (e_vector) bad_interrupt;
165
166 _ramvec[32] = system_call;
167
168 _ramvec[65] = (e_vector) inthandler1;
169 _ramvec[66] = (e_vector) inthandler2;
170 _ramvec[67] = (e_vector) inthandler3;
171 _ramvec[68] = (e_vector) inthandler4;
172 _ramvec[69] = (e_vector) inthandler5;
173 _ramvec[70] = (e_vector) inthandler6;
174 _ramvec[71] = (e_vector) inthandler7;
175
176 IVR = 0x40; /* Set DragonBall IVR (interrupt base) to 64 */
177
178 /* turn off all interrupts */
179 IMR = ~0;
180
181 for (i = 0; (i < NR_IRQS); i++) {
182 irq_desc[i].status = IRQ_DISABLED;
183 irq_desc[i].action = NULL;
184 irq_desc[i].depth = 1;
185 irq_desc[i].chip = &intc_irq_chip;
186 }
179} 187}
180 188
diff --git a/arch/m68knommu/platform/68360/ints.c b/arch/m68knommu/platform/68360/ints.c
index c36781157e09..1143f77caca4 100644
--- a/arch/m68knommu/platform/68360/ints.c
+++ b/arch/m68knommu/platform/68360/ints.c
@@ -37,11 +37,33 @@ extern void *_ramvec[];
37/* The number of spurious interrupts */ 37/* The number of spurious interrupts */
38volatile unsigned int num_spurious; 38volatile unsigned int num_spurious;
39 39
40static void intc_irq_unmask(unsigned int irq)
41{
42 pquicc->intr_cimr |= (1 << irq);
43}
44
45static void intc_irq_mask(unsigned int irq)
46{
47 pquicc->intr_cimr &= ~(1 << irq);
48}
49
50static void intc_irq_ack(unsigned int irq)
51{
52 pquicc->intr_cisr = (1 << irq);
53}
54
55static struct irq_chip intc_irq_chip = {
56 .name = "M68K-INTC",
57 .mask = intc_irq_mask,
58 .unmask = intc_irq_unmask,
59 .ack = intc_irq_ack,
60};
61
40/* 62/*
41 * This function should be called during kernel startup to initialize 63 * This function should be called during kernel startup to initialize
42 * the vector table. 64 * the vector table.
43 */ 65 */
44void init_vectors(void) 66void init_IRQ(void)
45{ 67{
46 int i; 68 int i;
47 int vba = (CPM_VECTOR_BASE<<4); 69 int vba = (CPM_VECTOR_BASE<<4);
@@ -109,20 +131,12 @@ void init_vectors(void)
109 131
110 /* turn off all CPM interrupts */ 132 /* turn off all CPM interrupts */
111 pquicc->intr_cimr = 0x00000000; 133 pquicc->intr_cimr = 0x00000000;
112}
113
114void enable_vector(unsigned int irq)
115{
116 pquicc->intr_cimr |= (1 << irq);
117}
118 134
119void disable_vector(unsigned int irq) 135 for (i = 0; (i < NR_IRQS); i++) {
120{ 136 irq_desc[i].status = IRQ_DISABLED;
121 pquicc->intr_cimr &= ~(1 << irq); 137 irq_desc[i].action = NULL;
122} 138 irq_desc[i].depth = 1;
123 139 irq_desc[i].chip = &intc_irq_chip;
124void ack_vector(unsigned int irq) 140 }
125{
126 pquicc->intr_cisr = (1 << irq);
127} 141}
128 142
diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile
index 1bcb9372353f..f72a0e5d9996 100644
--- a/arch/m68knommu/platform/coldfire/Makefile
+++ b/arch/m68knommu/platform/coldfire/Makefile
@@ -15,16 +15,17 @@
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16 16
17obj-$(CONFIG_COLDFIRE) += clk.o dma.o entry.o vectors.o 17obj-$(CONFIG_COLDFIRE) += clk.o dma.o entry.o vectors.o
18obj-$(CONFIG_M5206) += timers.o 18obj-$(CONFIG_M5206) += timers.o intc.o
19obj-$(CONFIG_M5206e) += timers.o 19obj-$(CONFIG_M5206e) += timers.o intc.o
20obj-$(CONFIG_M520x) += pit.o 20obj-$(CONFIG_M520x) += pit.o intc-simr.o
21obj-$(CONFIG_M523x) += pit.o dma_timer.o 21obj-$(CONFIG_M523x) += pit.o dma_timer.o intc-2.o
22obj-$(CONFIG_M5249) += timers.o 22obj-$(CONFIG_M5249) += timers.o intc.o
23obj-$(CONFIG_M527x) += pit.o 23obj-$(CONFIG_M527x) += pit.o intc-2.o
24obj-$(CONFIG_M5272) += timers.o 24obj-$(CONFIG_M5272) += timers.o
25obj-$(CONFIG_M528x) += pit.o 25obj-$(CONFIG_M528x) += pit.o intc-2.o
26obj-$(CONFIG_M5307) += timers.o 26obj-$(CONFIG_M5307) += timers.o intc.o
27obj-$(CONFIG_M532x) += timers.o 27obj-$(CONFIG_M532x) += timers.o intc-simr.o
28obj-$(CONFIG_M5407) += timers.o 28obj-$(CONFIG_M5407) += timers.o intc.o
29 29
30obj-y += pinmux.o gpio.o
30extra-y := head.o 31extra-y := head.o
diff --git a/arch/m68knommu/platform/coldfire/gpio.c b/arch/m68knommu/platform/coldfire/gpio.c
new file mode 100644
index 000000000000..ff0045793450
--- /dev/null
+++ b/arch/m68knommu/platform/coldfire/gpio.c
@@ -0,0 +1,127 @@
1/*
2 * Coldfire generic GPIO support.
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/sysdev.h>
19
20#include <asm/gpio.h>
21#include <asm/pinmux.h>
22#include <asm/mcfgpio.h>
23
24#define MCF_CHIP(chip) container_of(chip, struct mcf_gpio_chip, gpio_chip)
25
26int mcf_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
27{
28 unsigned long flags;
29 MCFGPIO_PORTTYPE dir;
30 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
31
32 local_irq_save(flags);
33 dir = mcfgpio_read(mcf_chip->pddr);
34 dir &= ~mcfgpio_bit(chip->base + offset);
35 mcfgpio_write(dir, mcf_chip->pddr);
36 local_irq_restore(flags);
37
38 return 0;
39}
40
41int mcf_gpio_get_value(struct gpio_chip *chip, unsigned offset)
42{
43 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
44
45 return mcfgpio_read(mcf_chip->ppdr) & mcfgpio_bit(chip->base + offset);
46}
47
48int mcf_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
49 int value)
50{
51 unsigned long flags;
52 MCFGPIO_PORTTYPE data;
53 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
54
55 local_irq_save(flags);
56 /* write the value to the output latch */
57 data = mcfgpio_read(mcf_chip->podr);
58 if (value)
59 data |= mcfgpio_bit(chip->base + offset);
60 else
61 data &= ~mcfgpio_bit(chip->base + offset);
62 mcfgpio_write(data, mcf_chip->podr);
63
64 /* now set the direction to output */
65 data = mcfgpio_read(mcf_chip->pddr);
66 data |= mcfgpio_bit(chip->base + offset);
67 mcfgpio_write(data, mcf_chip->pddr);
68 local_irq_restore(flags);
69
70 return 0;
71}
72
73void mcf_gpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
74{
75 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
76
77 unsigned long flags;
78 MCFGPIO_PORTTYPE data;
79
80 local_irq_save(flags);
81 data = mcfgpio_read(mcf_chip->podr);
82 if (value)
83 data |= mcfgpio_bit(chip->base + offset);
84 else
85 data &= ~mcfgpio_bit(chip->base + offset);
86 mcfgpio_write(data, mcf_chip->podr);
87 local_irq_restore(flags);
88}
89
90void mcf_gpio_set_value_fast(struct gpio_chip *chip, unsigned offset, int value)
91{
92 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
93
94 if (value)
95 mcfgpio_write(mcfgpio_bit(chip->base + offset), mcf_chip->setr);
96 else
97 mcfgpio_write(~mcfgpio_bit(chip->base + offset), mcf_chip->clrr);
98}
99
100int mcf_gpio_request(struct gpio_chip *chip, unsigned offset)
101{
102 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
103
104 return mcf_chip->gpio_to_pinmux ?
105 mcf_pinmux_request(mcf_chip->gpio_to_pinmux[offset], 0) : 0;
106}
107
108void mcf_gpio_free(struct gpio_chip *chip, unsigned offset)
109{
110 struct mcf_gpio_chip *mcf_chip = MCF_CHIP(chip);
111
112 mcf_gpio_direction_input(chip, offset);
113
114 if (mcf_chip->gpio_to_pinmux)
115 mcf_pinmux_release(mcf_chip->gpio_to_pinmux[offset], 0);
116}
117
118struct sysdev_class mcf_gpio_sysclass = {
119 .name = "gpio",
120};
121
122static int __init mcf_gpio_sysinit(void)
123{
124 return sysdev_class_register(&mcf_gpio_sysclass);
125}
126
127core_initcall(mcf_gpio_sysinit);
diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c
new file mode 100644
index 000000000000..5598c8b8661f
--- /dev/null
+++ b/arch/m68knommu/platform/coldfire/intc-2.c
@@ -0,0 +1,93 @@
1/*
2 * intc-1.c
3 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/traps.h>
20
21/*
22 * Each vector needs a unique priority and level asscoiated with it.
23 * We don't really care so much what they are, we don't rely on the
24 * tranditional priority interrupt scheme of the m68k/ColdFire.
25 */
26static u8 intc_intpri = 0x36;
27
28static void intc_irq_mask(unsigned int irq)
29{
30 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) {
31 unsigned long imraddr;
32 u32 val, imrbit;
33
34 irq -= MCFINT_VECBASE;
35 imraddr = MCF_IPSBAR;
36 imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
37 imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
38 imrbit = 0x1 << (irq & 0x1f);
39
40 val = __raw_readl(imraddr);
41 __raw_writel(val | imrbit, imraddr);
42 }
43}
44
45static void intc_irq_unmask(unsigned int irq)
46{
47 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) {
48 unsigned long intaddr, imraddr, icraddr;
49 u32 val, imrbit;
50
51 irq -= MCFINT_VECBASE;
52 intaddr = MCF_IPSBAR;
53 intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
54 imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
55 icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
56 imrbit = 0x1 << (irq & 0x1f);
57
58 /* Don't set the "maskall" bit! */
59 if ((irq & 0x20) == 0)
60 imrbit |= 0x1;
61
62 if (__raw_readb(icraddr) == 0)
63 __raw_writeb(intc_intpri--, icraddr);
64
65 val = __raw_readl(imraddr);
66 __raw_writel(val & ~imrbit, imraddr);
67 }
68}
69
70static struct irq_chip intc_irq_chip = {
71 .name = "CF-INTC",
72 .mask = intc_irq_mask,
73 .unmask = intc_irq_unmask,
74};
75
76void __init init_IRQ(void)
77{
78 int irq;
79
80 init_vectors();
81
82 /* Mask all interrupt sources */
83 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
84 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL);
85
86 for (irq = 0; (irq < NR_IRQS); irq++) {
87 irq_desc[irq].status = IRQ_DISABLED;
88 irq_desc[irq].action = NULL;
89 irq_desc[irq].depth = 1;
90 irq_desc[irq].chip = &intc_irq_chip;
91 }
92}
93
diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c
new file mode 100644
index 000000000000..1b01e79c2f63
--- /dev/null
+++ b/arch/m68knommu/platform/coldfire/intc-simr.c
@@ -0,0 +1,78 @@
1/*
2 * intc-simr.c
3 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <asm/coldfire.h>
18#include <asm/mcfsim.h>
19#include <asm/traps.h>
20
21static void intc_irq_mask(unsigned int irq)
22{
23 if (irq >= MCFINT_VECBASE) {
24 if (irq < MCFINT_VECBASE + 64)
25 __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_SIMR);
26 else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_SIMR)
27 __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_SIMR);
28 }
29}
30
31static void intc_irq_unmask(unsigned int irq)
32{
33 if (irq >= MCFINT_VECBASE) {
34 if (irq < MCFINT_VECBASE + 64)
35 __raw_writeb(irq - MCFINT_VECBASE, MCFINTC0_CIMR);
36 else if ((irq < MCFINT_VECBASE + 128) && MCFINTC1_CIMR)
37 __raw_writeb(irq - MCFINT_VECBASE - 64, MCFINTC1_CIMR);
38 }
39}
40
41static int intc_irq_set_type(unsigned int irq, unsigned int type)
42{
43 if (irq >= MCFINT_VECBASE) {
44 if (irq < MCFINT_VECBASE + 64)
45 __raw_writeb(5, MCFINTC0_ICR0 + irq - MCFINT_VECBASE);
46 else if ((irq < MCFINT_VECBASE) && MCFINTC1_ICR0)
47 __raw_writeb(5, MCFINTC1_ICR0 + irq - MCFINT_VECBASE - 64);
48 }
49 return 0;
50}
51
52static struct irq_chip intc_irq_chip = {
53 .name = "CF-INTC",
54 .mask = intc_irq_mask,
55 .unmask = intc_irq_unmask,
56 .set_type = intc_irq_set_type,
57};
58
59void __init init_IRQ(void)
60{
61 int irq;
62
63 init_vectors();
64
65 /* Mask all interrupt sources */
66 __raw_writeb(0xff, MCFINTC0_SIMR);
67 if (MCFINTC1_SIMR)
68 __raw_writeb(0xff, MCFINTC1_SIMR);
69
70 for (irq = 0; (irq < NR_IRQS); irq++) {
71 irq_desc[irq].status = IRQ_DISABLED;
72 irq_desc[irq].action = NULL;
73 irq_desc[irq].depth = 1;
74 irq_desc[irq].chip = &intc_irq_chip;
75 intc_irq_set_type(irq, 0);
76 }
77}
78
diff --git a/arch/m68knommu/platform/coldfire/intc.c b/arch/m68knommu/platform/coldfire/intc.c
new file mode 100644
index 000000000000..a4560c86db71
--- /dev/null
+++ b/arch/m68knommu/platform/coldfire/intc.c
@@ -0,0 +1,153 @@
1/*
2 * intc.c -- support for the old ColdFire interrupt controller
3 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/io.h>
17#include <asm/traps.h>
18#include <asm/coldfire.h>
19#include <asm/mcfsim.h>
20
21/*
22 * The mapping of irq number to a mask register bit is not one-to-one.
23 * The irq numbers are either based on "level" of interrupt or fixed
24 * for an autovector-able interrupt. So we keep a local data structure
25 * that maps from irq to mask register. Not all interrupts will have
26 * an IMR bit.
27 */
28unsigned char mcf_irq2imr[NR_IRQS];
29
30/*
31 * Define the miniumun and maximum external interrupt numbers.
32 * This is also used as the "level" interrupt numbers.
33 */
34#define EIRQ1 25
35#define EIRQ7 31
36
37/*
38 * In the early version 2 core ColdFire parts the IMR register was 16 bits
39 * in size. Version 3 (and later version 2) core parts have a 32 bit
40 * sized IMR register. Provide some size independant methods to access the
41 * IMR register.
42 */
43#ifdef MCFSIM_IMR_IS_16BITS
44
45void mcf_setimr(int index)
46{
47 u16 imr;
48 imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
49 __raw_writew(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
50}
51
52void mcf_clrimr(int index)
53{
54 u16 imr;
55 imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
56 __raw_writew(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
57}
58
59void mcf_maskimr(unsigned int mask)
60{
61 u16 imr;
62 imr = __raw_readw(MCF_MBAR + MCFSIM_IMR);
63 imr |= mask;
64 __raw_writew(imr, MCF_MBAR + MCFSIM_IMR);
65}
66
67#else
68
69void mcf_setimr(int index)
70{
71 u32 imr;
72 imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
73 __raw_writel(imr | (0x1 << index), MCF_MBAR + MCFSIM_IMR);
74}
75
76void mcf_clrimr(int index)
77{
78 u32 imr;
79 imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
80 __raw_writel(imr & ~(0x1 << index), MCF_MBAR + MCFSIM_IMR);
81}
82
83void mcf_maskimr(unsigned int mask)
84{
85 u32 imr;
86 imr = __raw_readl(MCF_MBAR + MCFSIM_IMR);
87 imr |= mask;
88 __raw_writel(imr, MCF_MBAR + MCFSIM_IMR);
89}
90
91#endif
92
93/*
94 * Interrupts can be "vectored" on the ColdFire cores that support this old
95 * interrupt controller. That is, the device raising the interrupt can also
96 * supply the vector number to interrupt through. The AVR register of the
97 * interrupt controller enables or disables this for each external interrupt,
98 * so provide generic support for this. Setting this up is out-of-band for
99 * the interrupt system API's, and needs to be done by the driver that
100 * supports this device. Very few devices actually use this.
101 */
102void mcf_autovector(int irq)
103{
104#ifdef MCFSIM_AVR
105 if ((irq >= EIRQ1) && (irq <= EIRQ7)) {
106 u8 avec;
107 avec = __raw_readb(MCF_MBAR + MCFSIM_AVR);
108 avec |= (0x1 << (irq - EIRQ1 + 1));
109 __raw_writeb(avec, MCF_MBAR + MCFSIM_AVR);
110 }
111#endif
112}
113
114static void intc_irq_mask(unsigned int irq)
115{
116 if (mcf_irq2imr[irq])
117 mcf_setimr(mcf_irq2imr[irq]);
118}
119
120static void intc_irq_unmask(unsigned int irq)
121{
122 if (mcf_irq2imr[irq])
123 mcf_clrimr(mcf_irq2imr[irq]);
124}
125
126static int intc_irq_set_type(unsigned int irq, unsigned int type)
127{
128 return 0;
129}
130
131static struct irq_chip intc_irq_chip = {
132 .name = "CF-INTC",
133 .mask = intc_irq_mask,
134 .unmask = intc_irq_unmask,
135 .set_type = intc_irq_set_type,
136};
137
138void __init init_IRQ(void)
139{
140 int irq;
141
142 init_vectors();
143 mcf_maskimr(0xffffffff);
144
145 for (irq = 0; (irq < NR_IRQS); irq++) {
146 irq_desc[irq].status = IRQ_DISABLED;
147 irq_desc[irq].action = NULL;
148 irq_desc[irq].depth = 1;
149 irq_desc[irq].chip = &intc_irq_chip;
150 intc_irq_set_type(irq, 0);
151 }
152}
153
diff --git a/arch/m68knommu/platform/coldfire/pinmux.c b/arch/m68knommu/platform/coldfire/pinmux.c
new file mode 100644
index 000000000000..8c62b825939f
--- /dev/null
+++ b/arch/m68knommu/platform/coldfire/pinmux.c
@@ -0,0 +1,28 @@
1/*
2 * Coldfire generic GPIO pinmux support.
3 *
4 * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/kernel.h>
18
19#include <asm/pinmux.h>
20
21int mcf_pinmux_request(unsigned pinmux, unsigned func)
22{
23 return 0;
24}
25
26void mcf_pinmux_release(unsigned pinmux, unsigned func)
27{
28}
diff --git a/arch/m68knommu/platform/coldfire/pit.c b/arch/m68knommu/platform/coldfire/pit.c
index 61b96211f8ff..d8720ee34510 100644
--- a/arch/m68knommu/platform/coldfire/pit.c
+++ b/arch/m68knommu/platform/coldfire/pit.c
@@ -32,7 +32,6 @@
32 */ 32 */
33#define FREQ ((MCF_CLK / 2) / 64) 33#define FREQ ((MCF_CLK / 2) / 64)
34#define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a)) 34#define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a))
35#define INTC0 (MCF_IPSBAR + MCFICM_INTC0)
36#define PIT_CYCLES_PER_JIFFY (FREQ / HZ) 35#define PIT_CYCLES_PER_JIFFY (FREQ / HZ)
37 36
38static u32 pit_cnt; 37static u32 pit_cnt;
@@ -154,8 +153,6 @@ static struct clocksource pit_clk = {
154 153
155void hw_timer_init(void) 154void hw_timer_init(void)
156{ 155{
157 u32 imr;
158
159 cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id()); 156 cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id());
160 cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32); 157 cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32);
161 cf_pit_clockevent.max_delta_ns = 158 cf_pit_clockevent.max_delta_ns =
@@ -166,11 +163,6 @@ void hw_timer_init(void)
166 163
167 setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq); 164 setup_irq(MCFINT_VECBASE + MCFINT_PIT1, &pit_irq);
168 165
169 __raw_writeb(ICR_INTRCONF, INTC0 + MCFINTC_ICR0 + MCFINT_PIT1);
170 imr = __raw_readl(INTC0 + MCFPIT_IMR);
171 imr &= ~MCFPIT_IMR_IBIT;
172 __raw_writel(imr, INTC0 + MCFPIT_IMR);
173
174 pit_clk.mult = clocksource_hz2mult(FREQ, pit_clk.shift); 166 pit_clk.mult = clocksource_hz2mult(FREQ, pit_clk.shift);
175 clocksource_register(&pit_clk); 167 clocksource_register(&pit_clk);
176} 168}
diff --git a/arch/m68knommu/platform/coldfire/timers.c b/arch/m68knommu/platform/coldfire/timers.c
index 1ba8a3731653..2304d736c701 100644
--- a/arch/m68knommu/platform/coldfire/timers.c
+++ b/arch/m68knommu/platform/coldfire/timers.c
@@ -31,19 +31,9 @@
31#define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a)) 31#define TA(a) (MCF_MBAR + MCFTIMER_BASE1 + (a))
32 32
33/* 33/*
34 * Default the timer and vector to use for ColdFire. Some ColdFire
35 * CPU's and some boards may want different. Their sub-architecture
36 * startup code (in config.c) can change these if they want.
37 */
38unsigned int mcf_timervector = 29;
39unsigned int mcf_profilevector = 31;
40unsigned int mcf_timerlevel = 5;
41
42/*
43 * These provide the underlying interrupt vector support. 34 * These provide the underlying interrupt vector support.
44 * Unfortunately it is a little different on each ColdFire. 35 * Unfortunately it is a little different on each ColdFire.
45 */ 36 */
46extern void mcf_settimericr(int timer, int level);
47void coldfire_profile_init(void); 37void coldfire_profile_init(void);
48 38
49#if defined(CONFIG_M532x) 39#if defined(CONFIG_M532x)
@@ -107,8 +97,6 @@ static struct clocksource mcftmr_clk = {
107 97
108void hw_timer_init(void) 98void hw_timer_init(void)
109{ 99{
110 setup_irq(mcf_timervector, &mcftmr_timer_irq);
111
112 __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR)); 100 __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
113 mcftmr_cycles_per_jiffy = FREQ / HZ; 101 mcftmr_cycles_per_jiffy = FREQ / HZ;
114 /* 102 /*
@@ -124,7 +112,7 @@ void hw_timer_init(void)
124 mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift); 112 mcftmr_clk.mult = clocksource_hz2mult(FREQ, mcftmr_clk.shift);
125 clocksource_register(&mcftmr_clk); 113 clocksource_register(&mcftmr_clk);
126 114
127 mcf_settimericr(1, mcf_timerlevel); 115 setup_irq(MCF_IRQ_TIMER, &mcftmr_timer_irq);
128 116
129#ifdef CONFIG_HIGHPROFILE 117#ifdef CONFIG_HIGHPROFILE
130 coldfire_profile_init(); 118 coldfire_profile_init();
@@ -171,8 +159,6 @@ void coldfire_profile_init(void)
171 printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n", 159 printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n",
172 PROFILEHZ); 160 PROFILEHZ);
173 161
174 setup_irq(mcf_profilevector, &coldfire_profile_irq);
175
176 /* Set up TIMER 2 as high speed profile clock */ 162 /* Set up TIMER 2 as high speed profile clock */
177 __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR)); 163 __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
178 164
@@ -180,7 +166,7 @@ void coldfire_profile_init(void)
180 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 | 166 __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
181 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR)); 167 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR));
182 168
183 mcf_settimericr(2, 7); 169 setup_irq(MCF_IRQ_PROFILER, &coldfire_profile_irq);
184} 170}
185 171
186/***************************************************************************/ 172/***************************************************************************/
diff --git a/arch/m68knommu/platform/coldfire/vectors.c b/arch/m68knommu/platform/coldfire/vectors.c
index bdca0297fa9a..a21d3f870b7a 100644
--- a/arch/m68knommu/platform/coldfire/vectors.c
+++ b/arch/m68knommu/platform/coldfire/vectors.c
@@ -1,7 +1,7 @@
1/***************************************************************************/ 1/***************************************************************************/
2 2
3/* 3/*
4 * linux/arch/m68knommu/platform/5307/vectors.c 4 * linux/arch/m68knommu/platform/coldfire/vectors.c
5 * 5 *
6 * Copyright (C) 1999-2007, Greg Ungerer <gerg@snapgear.com> 6 * Copyright (C) 1999-2007, Greg Ungerer <gerg@snapgear.com>
7 */ 7 */
@@ -15,7 +15,6 @@
15#include <asm/machdep.h> 15#include <asm/machdep.h>
16#include <asm/coldfire.h> 16#include <asm/coldfire.h>
17#include <asm/mcfsim.h> 17#include <asm/mcfsim.h>
18#include <asm/mcfdma.h>
19#include <asm/mcfwdebug.h> 18#include <asm/mcfwdebug.h>
20 19
21/***************************************************************************/ 20/***************************************************************************/
@@ -79,20 +78,3 @@ void __init init_vectors(void)
79} 78}
80 79
81/***************************************************************************/ 80/***************************************************************************/
82
83void enable_vector(unsigned int irq)
84{
85 /* Currently no action on ColdFire */
86}
87
88void disable_vector(unsigned int irq)
89{
90 /* Currently no action on ColdFire */
91}
92
93void ack_vector(unsigned int irq)
94{
95 /* Currently no action on ColdFire */
96}
97
98/***************************************************************************/
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index b47201874d84..29234380e6c6 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -1154,19 +1154,9 @@ static void __inline__ fec_request_mii_intr(struct net_device *dev)
1154 printk("FEC: Could not allocate fec(MII) IRQ(66)!\n"); 1154 printk("FEC: Could not allocate fec(MII) IRQ(66)!\n");
1155} 1155}
1156 1156
1157static void __inline__ fec_disable_phy_intr(void) 1157static void __inline__ fec_disable_phy_intr(struct net_device *dev)
1158{ 1158{
1159 volatile unsigned long *icrp; 1159 free_irq(66, dev);
1160 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1161 *icrp = 0x08000000;
1162}
1163
1164static void __inline__ fec_phy_ack_intr(void)
1165{
1166 volatile unsigned long *icrp;
1167 /* Acknowledge the interrupt */
1168 icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1);
1169 *icrp = 0x0d000000;
1170} 1160}
1171#endif 1161#endif
1172 1162
@@ -1398,7 +1388,7 @@ mii_discover_phy(uint mii_reg, struct net_device *dev)
1398 writel(0, fep->hwp + FEC_MII_SPEED); 1388 writel(0, fep->hwp + FEC_MII_SPEED);
1399 fep->phy_speed = 0; 1389 fep->phy_speed = 0;
1400#ifdef HAVE_mii_link_interrupt 1390#ifdef HAVE_mii_link_interrupt
1401 fec_disable_phy_intr(); 1391 fec_disable_phy_intr(dev);
1402#endif 1392#endif
1403 } 1393 }
1404} 1394}
@@ -1411,8 +1401,6 @@ mii_link_interrupt(int irq, void * dev_id)
1411 struct net_device *dev = dev_id; 1401 struct net_device *dev = dev_id;
1412 struct fec_enet_private *fep = netdev_priv(dev); 1402 struct fec_enet_private *fep = netdev_priv(dev);
1413 1403
1414 fec_phy_ack_intr();
1415
1416 mii_do_cmd(dev, fep->phy->ack_int); 1404 mii_do_cmd(dev, fep->phy->ack_int);
1417 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */ 1405 mii_do_cmd(dev, phy_cmd_relink); /* restart and display status */
1418 1406
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 03:38:47 -0500