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-rw-r--r--drivers/serial/Kconfig10
-rw-r--r--drivers/serial/Makefile1
-rw-r--r--drivers/serial/msm_serial.c767
-rw-r--r--drivers/serial/msm_serial.h117
-rw-r--r--include/linux/serial_core.h3
5 files changed, 898 insertions, 0 deletions
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 1132c5cae7ab..037c1e0b7c4c 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -1320,6 +1320,16 @@ config SERIAL_SGI_IOC3
1320 If you have an SGI Altix with an IOC3 serial card, 1320 If you have an SGI Altix with an IOC3 serial card,
1321 say Y or M. Otherwise, say N. 1321 say Y or M. Otherwise, say N.
1322 1322
1323config SERIAL_MSM
1324 bool "MSM on-chip serial port support"
1325 depends on ARM && ARCH_MSM
1326 select SERIAL_CORE
1327
1328config SERIAL_MSM_CONSOLE
1329 bool "MSM serial console support"
1330 depends on SERIAL_MSM=y
1331 select SERIAL_CORE_CONSOLE
1332
1323config SERIAL_NETX 1333config SERIAL_NETX
1324 tristate "NetX serial port support" 1334 tristate "NetX serial port support"
1325 depends on ARM && ARCH_NETX 1335 depends on ARM && ARCH_NETX
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 45a8658f54d5..d5a29981c6c4 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -71,6 +71,7 @@ obj-$(CONFIG_SERIAL_SGI_IOC4) += ioc4_serial.o
71obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o 71obj-$(CONFIG_SERIAL_SGI_IOC3) += ioc3_serial.o
72obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o 72obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o
73obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o 73obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o
74obj-$(CONFIG_SERIAL_MSM) += msm_serial.o
74obj-$(CONFIG_SERIAL_NETX) += netx-serial.o 75obj-$(CONFIG_SERIAL_NETX) += netx-serial.o
75obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o 76obj-$(CONFIG_SERIAL_OF_PLATFORM) += of_serial.o
76obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o 77obj-$(CONFIG_SERIAL_OF_PLATFORM_NWPSERIAL) += nwpserial.o
diff --git a/drivers/serial/msm_serial.c b/drivers/serial/msm_serial.c
new file mode 100644
index 000000000000..1a7c856f76f8
--- /dev/null
+++ b/drivers/serial/msm_serial.c
@@ -0,0 +1,767 @@
1/*
2 * drivers/serial/msm_serial.c - driver for msm7k serial device and console
3 *
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18# define SUPPORT_SYSRQ
19#endif
20
21#include <linux/hrtimer.h>
22#include <linux/module.h>
23#include <linux/io.h>
24#include <linux/ioport.h>
25#include <linux/irq.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/tty.h>
29#include <linux/tty_flip.h>
30#include <linux/serial_core.h>
31#include <linux/serial.h>
32#include <linux/clk.h>
33#include <linux/platform_device.h>
34
35#include "msm_serial.h"
36
37struct msm_port {
38 struct uart_port uart;
39 char name[16];
40 struct clk *clk;
41 unsigned int imr;
42};
43
44#define UART_TO_MSM(uart_port) ((struct msm_port *) uart_port)
45
46static inline void msm_write(struct uart_port *port, unsigned int val,
47 unsigned int off)
48{
49 __raw_writel(val, port->membase + off);
50}
51
52static inline unsigned int msm_read(struct uart_port *port, unsigned int off)
53{
54 return __raw_readl(port->membase + off);
55}
56
57static void msm_stop_tx(struct uart_port *port)
58{
59 struct msm_port *msm_port = UART_TO_MSM(port);
60
61 msm_port->imr &= ~UART_IMR_TXLEV;
62 msm_write(port, msm_port->imr, UART_IMR);
63}
64
65static void msm_start_tx(struct uart_port *port)
66{
67 struct msm_port *msm_port = UART_TO_MSM(port);
68
69 msm_port->imr |= UART_IMR_TXLEV;
70 msm_write(port, msm_port->imr, UART_IMR);
71}
72
73static void msm_stop_rx(struct uart_port *port)
74{
75 struct msm_port *msm_port = UART_TO_MSM(port);
76
77 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
78 msm_write(port, msm_port->imr, UART_IMR);
79}
80
81static void msm_enable_ms(struct uart_port *port)
82{
83 struct msm_port *msm_port = UART_TO_MSM(port);
84
85 msm_port->imr |= UART_IMR_DELTA_CTS;
86 msm_write(port, msm_port->imr, UART_IMR);
87}
88
89static void handle_rx(struct uart_port *port)
90{
91 struct tty_struct *tty = port->info->port.tty;
92 unsigned int sr;
93
94 /*
95 * Handle overrun. My understanding of the hardware is that overrun
96 * is not tied to the RX buffer, so we handle the case out of band.
97 */
98 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
99 port->icount.overrun++;
100 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
101 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
102 }
103
104 /* and now the main RX loop */
105 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
106 unsigned int c;
107 char flag = TTY_NORMAL;
108
109 c = msm_read(port, UART_RF);
110
111 if (sr & UART_SR_RX_BREAK) {
112 port->icount.brk++;
113 if (uart_handle_break(port))
114 continue;
115 } else if (sr & UART_SR_PAR_FRAME_ERR) {
116 port->icount.frame++;
117 } else {
118 port->icount.rx++;
119 }
120
121 /* Mask conditions we're ignorning. */
122 sr &= port->read_status_mask;
123
124 if (sr & UART_SR_RX_BREAK) {
125 flag = TTY_BREAK;
126 } else if (sr & UART_SR_PAR_FRAME_ERR) {
127 flag = TTY_FRAME;
128 }
129
130 if (!uart_handle_sysrq_char(port, c))
131 tty_insert_flip_char(tty, c, flag);
132 }
133
134 tty_flip_buffer_push(tty);
135}
136
137static void handle_tx(struct uart_port *port)
138{
139 struct circ_buf *xmit = &port->info->xmit;
140 struct msm_port *msm_port = UART_TO_MSM(port);
141 int sent_tx;
142
143 if (port->x_char) {
144 msm_write(port, port->x_char, UART_TF);
145 port->icount.tx++;
146 port->x_char = 0;
147 }
148
149 while (msm_read(port, UART_SR) & UART_SR_TX_READY) {
150 if (uart_circ_empty(xmit)) {
151 /* disable tx interrupts */
152 msm_port->imr &= ~UART_IMR_TXLEV;
153 msm_write(port, msm_port->imr, UART_IMR);
154 break;
155 }
156
157 msm_write(port, xmit->buf[xmit->tail], UART_TF);
158
159 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
160 port->icount.tx++;
161 sent_tx = 1;
162 }
163
164 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
165 uart_write_wakeup(port);
166}
167
168static void handle_delta_cts(struct uart_port *port)
169{
170 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
171 port->icount.cts++;
172 wake_up_interruptible(&port->info->delta_msr_wait);
173}
174
175static irqreturn_t msm_irq(int irq, void *dev_id)
176{
177 struct uart_port *port = dev_id;
178 struct msm_port *msm_port = UART_TO_MSM(port);
179 unsigned int misr;
180
181 spin_lock(&port->lock);
182 misr = msm_read(port, UART_MISR);
183 msm_write(port, 0, UART_IMR); /* disable interrupt */
184
185 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE))
186 handle_rx(port);
187 if (misr & UART_IMR_TXLEV)
188 handle_tx(port);
189 if (misr & UART_IMR_DELTA_CTS)
190 handle_delta_cts(port);
191
192 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
193 spin_unlock(&port->lock);
194
195 return IRQ_HANDLED;
196}
197
198static unsigned int msm_tx_empty(struct uart_port *port)
199{
200 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
201}
202
203static unsigned int msm_get_mctrl(struct uart_port *port)
204{
205 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
206}
207
208static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
209{
210 unsigned int mr;
211
212 mr = msm_read(port, UART_MR1);
213
214 if (!(mctrl & TIOCM_RTS)) {
215 mr &= ~UART_MR1_RX_RDY_CTL;
216 msm_write(port, mr, UART_MR1);
217 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
218 } else {
219 mr |= UART_MR1_RX_RDY_CTL;
220 msm_write(port, mr, UART_MR1);
221 }
222}
223
224static void msm_break_ctl(struct uart_port *port, int break_ctl)
225{
226 if (break_ctl)
227 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
228 else
229 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
230}
231
232static void msm_set_baud_rate(struct uart_port *port, unsigned int baud)
233{
234 unsigned int baud_code, rxstale, watermark;
235
236 switch (baud) {
237 case 300:
238 baud_code = UART_CSR_300;
239 rxstale = 1;
240 break;
241 case 600:
242 baud_code = UART_CSR_600;
243 rxstale = 1;
244 break;
245 case 1200:
246 baud_code = UART_CSR_1200;
247 rxstale = 1;
248 break;
249 case 2400:
250 baud_code = UART_CSR_2400;
251 rxstale = 1;
252 break;
253 case 4800:
254 baud_code = UART_CSR_4800;
255 rxstale = 1;
256 break;
257 case 9600:
258 baud_code = UART_CSR_9600;
259 rxstale = 2;
260 break;
261 case 14400:
262 baud_code = UART_CSR_14400;
263 rxstale = 3;
264 break;
265 case 19200:
266 baud_code = UART_CSR_19200;
267 rxstale = 4;
268 break;
269 case 28800:
270 baud_code = UART_CSR_28800;
271 rxstale = 6;
272 break;
273 case 38400:
274 baud_code = UART_CSR_38400;
275 rxstale = 8;
276 break;
277 case 57600:
278 baud_code = UART_CSR_57600;
279 rxstale = 16;
280 break;
281 case 115200:
282 default:
283 baud_code = UART_CSR_115200;
284 rxstale = 31;
285 break;
286 }
287
288 msm_write(port, baud_code, UART_CSR);
289
290 /* RX stale watermark */
291 watermark = UART_IPR_STALE_LSB & rxstale;
292 watermark |= UART_IPR_RXSTALE_LAST;
293 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
294 msm_write(port, watermark, UART_IPR);
295
296 /* set RX watermark */
297 watermark = (port->fifosize * 3) / 4;
298 msm_write(port, watermark, UART_RFWR);
299
300 /* set TX watermark */
301 msm_write(port, 10, UART_TFWR);
302}
303
304static void msm_reset(struct uart_port *port)
305{
306 /* reset everything */
307 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
308 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
309 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
310 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
311 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
312 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
313}
314
315static void msm_init_clock(struct uart_port *port)
316{
317 struct msm_port *msm_port = UART_TO_MSM(port);
318
319 clk_enable(msm_port->clk);
320
321 msm_write(port, 0xC0, UART_MREG);
322 msm_write(port, 0xB2, UART_NREG);
323 msm_write(port, 0x7D, UART_DREG);
324 msm_write(port, 0x1C, UART_MNDREG);
325}
326
327static int msm_startup(struct uart_port *port)
328{
329 struct msm_port *msm_port = UART_TO_MSM(port);
330 unsigned int data, rfr_level;
331 int ret;
332
333 snprintf(msm_port->name, sizeof(msm_port->name),
334 "msm_serial%d", port->line);
335
336 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
337 msm_port->name, port);
338 if (unlikely(ret))
339 return ret;
340
341 msm_init_clock(port);
342
343 if (likely(port->fifosize > 12))
344 rfr_level = port->fifosize - 12;
345 else
346 rfr_level = port->fifosize;
347
348 /* set automatic RFR level */
349 data = msm_read(port, UART_MR1);
350 data &= ~UART_MR1_AUTO_RFR_LEVEL1;
351 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
352 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
353 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
354 msm_write(port, data, UART_MR1);
355
356 /* make sure that RXSTALE count is non-zero */
357 data = msm_read(port, UART_IPR);
358 if (unlikely(!data)) {
359 data |= UART_IPR_RXSTALE_LAST;
360 data |= UART_IPR_STALE_LSB;
361 msm_write(port, data, UART_IPR);
362 }
363
364 msm_reset(port);
365
366 msm_write(port, 0x05, UART_CR); /* enable TX & RX */
367
368 /* turn on RX and CTS interrupts */
369 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
370 UART_IMR_CURRENT_CTS;
371 msm_write(port, msm_port->imr, UART_IMR);
372
373 return 0;
374}
375
376static void msm_shutdown(struct uart_port *port)
377{
378 struct msm_port *msm_port = UART_TO_MSM(port);
379
380 msm_port->imr = 0;
381 msm_write(port, 0, UART_IMR); /* disable interrupts */
382
383 clk_disable(msm_port->clk);
384
385 free_irq(port->irq, port);
386}
387
388static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
389 struct ktermios *old)
390{
391 unsigned long flags;
392 unsigned int baud, mr;
393
394 spin_lock_irqsave(&port->lock, flags);
395
396 /* calculate and set baud rate */
397 baud = uart_get_baud_rate(port, termios, old, 300, 115200);
398 msm_set_baud_rate(port, baud);
399
400 /* calculate parity */
401 mr = msm_read(port, UART_MR2);
402 mr &= ~UART_MR2_PARITY_MODE;
403 if (termios->c_cflag & PARENB) {
404 if (termios->c_cflag & PARODD)
405 mr |= UART_MR2_PARITY_MODE_ODD;
406 else if (termios->c_cflag & CMSPAR)
407 mr |= UART_MR2_PARITY_MODE_SPACE;
408 else
409 mr |= UART_MR2_PARITY_MODE_EVEN;
410 }
411
412 /* calculate bits per char */
413 mr &= ~UART_MR2_BITS_PER_CHAR;
414 switch (termios->c_cflag & CSIZE) {
415 case CS5:
416 mr |= UART_MR2_BITS_PER_CHAR_5;
417 break;
418 case CS6:
419 mr |= UART_MR2_BITS_PER_CHAR_6;
420 break;
421 case CS7:
422 mr |= UART_MR2_BITS_PER_CHAR_7;
423 break;
424 case CS8:
425 default:
426 mr |= UART_MR2_BITS_PER_CHAR_8;
427 break;
428 }
429
430 /* calculate stop bits */
431 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
432 if (termios->c_cflag & CSTOPB)
433 mr |= UART_MR2_STOP_BIT_LEN_TWO;
434 else
435 mr |= UART_MR2_STOP_BIT_LEN_ONE;
436
437 /* set parity, bits per char, and stop bit */
438 msm_write(port, mr, UART_MR2);
439
440 /* calculate and set hardware flow control */
441 mr = msm_read(port, UART_MR1);
442 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
443 if (termios->c_cflag & CRTSCTS) {
444 mr |= UART_MR1_CTS_CTL;
445 mr |= UART_MR1_RX_RDY_CTL;
446 }
447 msm_write(port, mr, UART_MR1);
448
449 /* Configure status bits to ignore based on termio flags. */
450 port->read_status_mask = 0;
451 if (termios->c_iflag & INPCK)
452 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
453 if (termios->c_iflag & (BRKINT | PARMRK))
454 port->read_status_mask |= UART_SR_RX_BREAK;
455
456 uart_update_timeout(port, termios->c_cflag, baud);
457
458 spin_unlock_irqrestore(&port->lock, flags);
459}
460
461static const char *msm_type(struct uart_port *port)
462{
463 return "MSM";
464}
465
466static void msm_release_port(struct uart_port *port)
467{
468 struct platform_device *pdev = to_platform_device(port->dev);
469 struct resource *resource;
470 resource_size_t size;
471
472 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
473 if (unlikely(!resource))
474 return;
475 size = resource->end - resource->start + 1;
476
477 release_mem_region(port->mapbase, size);
478 iounmap(port->membase);
479 port->membase = NULL;
480}
481
482static int msm_request_port(struct uart_port *port)
483{
484 struct platform_device *pdev = to_platform_device(port->dev);
485 struct resource *resource;
486 resource_size_t size;
487
488 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
489 if (unlikely(!resource))
490 return -ENXIO;
491 size = resource->end - resource->start + 1;
492
493 if (unlikely(!request_mem_region(port->mapbase, size, "msm_serial")))
494 return -EBUSY;
495
496 port->membase = ioremap(port->mapbase, size);
497 if (!port->membase) {
498 release_mem_region(port->mapbase, size);
499 return -EBUSY;
500 }
501
502 return 0;
503}
504
505static void msm_config_port(struct uart_port *port, int flags)
506{
507 if (flags & UART_CONFIG_TYPE) {
508 port->type = PORT_MSM;
509 msm_request_port(port);
510 }
511}
512
513static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
514{
515 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
516 return -EINVAL;
517 if (unlikely(port->irq != ser->irq))
518 return -EINVAL;
519 return 0;
520}
521
522static void msm_power(struct uart_port *port, unsigned int state,
523 unsigned int oldstate)
524{
525 struct msm_port *msm_port = UART_TO_MSM(port);
526
527 switch (state) {
528 case 0:
529 clk_enable(msm_port->clk);
530 break;
531 case 3:
532 clk_disable(msm_port->clk);
533 break;
534 default:
535 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
536 }
537}
538
539static struct uart_ops msm_uart_pops = {
540 .tx_empty = msm_tx_empty,
541 .set_mctrl = msm_set_mctrl,
542 .get_mctrl = msm_get_mctrl,
543 .stop_tx = msm_stop_tx,
544 .start_tx = msm_start_tx,
545 .stop_rx = msm_stop_rx,
546 .enable_ms = msm_enable_ms,
547 .break_ctl = msm_break_ctl,
548 .startup = msm_startup,
549 .shutdown = msm_shutdown,
550 .set_termios = msm_set_termios,
551 .type = msm_type,
552 .release_port = msm_release_port,
553 .request_port = msm_request_port,
554 .config_port = msm_config_port,
555 .verify_port = msm_verify_port,
556 .pm = msm_power,
557};
558
559static struct msm_port msm_uart_ports[] = {
560 {
561 .uart = {
562 .iotype = UPIO_MEM,
563 .ops = &msm_uart_pops,
564 .flags = UPF_BOOT_AUTOCONF,
565 .fifosize = 512,
566 .line = 0,
567 },
568 },
569 {
570 .uart = {
571 .iotype = UPIO_MEM,
572 .ops = &msm_uart_pops,
573 .flags = UPF_BOOT_AUTOCONF,
574 .fifosize = 512,
575 .line = 1,
576 },
577 },
578 {
579 .uart = {
580 .iotype = UPIO_MEM,
581 .ops = &msm_uart_pops,
582 .flags = UPF_BOOT_AUTOCONF,
583 .fifosize = 64,
584 .line = 2,
585 },
586 },
587};
588
589#define UART_NR ARRAY_SIZE(msm_uart_ports)
590
591static inline struct uart_port *get_port_from_line(unsigned int line)
592{
593 return &msm_uart_ports[line].uart;
594}
595
596#ifdef CONFIG_SERIAL_MSM_CONSOLE
597
598static void msm_console_putchar(struct uart_port *port, int c)
599{
600 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
601 ;
602 msm_write(port, c, UART_TF);
603}
604
605static void msm_console_write(struct console *co, const char *s,
606 unsigned int count)
607{
608 struct uart_port *port;
609 struct msm_port *msm_port;
610
611 BUG_ON(co->index < 0 || co->index >= UART_NR);
612
613 port = get_port_from_line(co->index);
614 msm_port = UART_TO_MSM(port);
615
616 spin_lock(&port->lock);
617 uart_console_write(port, s, count, msm_console_putchar);
618 spin_unlock(&port->lock);
619}
620
621static int __init msm_console_setup(struct console *co, char *options)
622{
623 struct uart_port *port;
624 int baud, flow, bits, parity;
625
626 if (unlikely(co->index >= UART_NR || co->index < 0))
627 return -ENXIO;
628
629 port = get_port_from_line(co->index);
630
631 if (unlikely(!port->membase))
632 return -ENXIO;
633
634 port->cons = co;
635
636 msm_init_clock(port);
637
638 if (options)
639 uart_parse_options(options, &baud, &parity, &bits, &flow);
640
641 bits = 8;
642 parity = 'n';
643 flow = 'n';
644 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
645 UART_MR2); /* 8N1 */
646
647 if (baud < 300 || baud > 115200)
648 baud = 115200;
649 msm_set_baud_rate(port, baud);
650
651 msm_reset(port);
652
653 printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
654
655 return uart_set_options(port, co, baud, parity, bits, flow);
656}
657
658static struct uart_driver msm_uart_driver;
659
660static struct console msm_console = {
661 .name = "ttyMSM",
662 .write = msm_console_write,
663 .device = uart_console_device,
664 .setup = msm_console_setup,
665 .flags = CON_PRINTBUFFER,
666 .index = -1,
667 .data = &msm_uart_driver,
668};
669
670#define MSM_CONSOLE (&msm_console)
671
672#else
673#define MSM_CONSOLE NULL
674#endif
675
676static struct uart_driver msm_uart_driver = {
677 .owner = THIS_MODULE,
678 .driver_name = "msm_serial",
679 .dev_name = "ttyMSM",
680 .nr = UART_NR,
681 .cons = MSM_CONSOLE,
682};
683
684static int __init msm_serial_probe(struct platform_device *pdev)
685{
686 struct msm_port *msm_port;
687 struct resource *resource;
688 struct uart_port *port;
689
690 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
691 return -ENXIO;
692
693 printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id);
694
695 port = get_port_from_line(pdev->id);
696 port->dev = &pdev->dev;
697 msm_port = UART_TO_MSM(port);
698
699 msm_port->clk = clk_get(&pdev->dev, "uart_clk");
700 if (unlikely(IS_ERR(msm_port->clk)))
701 return PTR_ERR(msm_port->clk);
702 port->uartclk = clk_get_rate(msm_port->clk);
703
704 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
705 if (unlikely(!resource))
706 return -ENXIO;
707 port->mapbase = resource->start;
708
709 port->irq = platform_get_irq(pdev, 0);
710 if (unlikely(port->irq < 0))
711 return -ENXIO;
712
713 platform_set_drvdata(pdev, port);
714
715 return uart_add_one_port(&msm_uart_driver, port);
716}
717
718static int __devexit msm_serial_remove(struct platform_device *pdev)
719{
720 struct msm_port *msm_port = platform_get_drvdata(pdev);
721
722 clk_put(msm_port->clk);
723
724 return 0;
725}
726
727static struct platform_driver msm_platform_driver = {
728 .probe = msm_serial_probe,
729 .remove = msm_serial_remove,
730 .driver = {
731 .name = "msm_serial",
732 .owner = THIS_MODULE,
733 },
734};
735
736static int __init msm_serial_init(void)
737{
738 int ret;
739
740 ret = uart_register_driver(&msm_uart_driver);
741 if (unlikely(ret))
742 return ret;
743
744 ret = platform_driver_probe(&msm_platform_driver, msm_serial_probe);
745 if (unlikely(ret))
746 uart_unregister_driver(&msm_uart_driver);
747
748 printk(KERN_INFO "msm_serial: driver initialized\n");
749
750 return ret;
751}
752
753static void __exit msm_serial_exit(void)
754{
755#ifdef CONFIG_SERIAL_MSM_CONSOLE
756 unregister_console(&msm_console);
757#endif
758 platform_driver_unregister(&msm_platform_driver);
759 uart_unregister_driver(&msm_uart_driver);
760}
761
762module_init(msm_serial_init);
763module_exit(msm_serial_exit);
764
765MODULE_AUTHOR("Robert Love <rlove@google.com>");
766MODULE_DESCRIPTION("Driver for msm7x serial device");
767MODULE_LICENSE("GPL");
diff --git a/drivers/serial/msm_serial.h b/drivers/serial/msm_serial.h
new file mode 100644
index 000000000000..689f1fa0e84e
--- /dev/null
+++ b/drivers/serial/msm_serial.h
@@ -0,0 +1,117 @@
1/*
2 * drivers/serial/msm_serial.h
3 *
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __DRIVERS_SERIAL_MSM_SERIAL_H
18#define __DRIVERS_SERIAL_MSM_SERIAL_H
19
20#define UART_MR1 0x0000
21
22#define UART_MR1_AUTO_RFR_LEVEL0 0x3F
23#define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00
24#define UART_MR1_RX_RDY_CTL (1 << 7)
25#define UART_MR1_CTS_CTL (1 << 6)
26
27#define UART_MR2 0x0004
28#define UART_MR2_ERROR_MODE (1 << 6)
29#define UART_MR2_BITS_PER_CHAR 0x30
30#define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4)
31#define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4)
32#define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4)
33#define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4)
34#define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2)
35#define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2)
36#define UART_MR2_PARITY_MODE_NONE 0x0
37#define UART_MR2_PARITY_MODE_ODD 0x1
38#define UART_MR2_PARITY_MODE_EVEN 0x2
39#define UART_MR2_PARITY_MODE_SPACE 0x3
40#define UART_MR2_PARITY_MODE 0x3
41
42#define UART_CSR 0x0008
43#define UART_CSR_115200 0xFF
44#define UART_CSR_57600 0xEE
45#define UART_CSR_38400 0xDD
46#define UART_CSR_28800 0xCC
47#define UART_CSR_19200 0xBB
48#define UART_CSR_14400 0xAA
49#define UART_CSR_9600 0x99
50#define UART_CSR_4800 0x77
51#define UART_CSR_2400 0x55
52#define UART_CSR_1200 0x44
53#define UART_CSR_600 0x33
54#define UART_CSR_300 0x22
55
56#define UART_TF 0x000C
57
58#define UART_CR 0x0010
59#define UART_CR_CMD_NULL (0 << 4)
60#define UART_CR_CMD_RESET_RX (1 << 4)
61#define UART_CR_CMD_RESET_TX (2 << 4)
62#define UART_CR_CMD_RESET_ERR (3 << 4)
63#define UART_CR_CMD_RESET_BREAK_INT (4 << 4)
64#define UART_CR_CMD_START_BREAK (5 << 4)
65#define UART_CR_CMD_STOP_BREAK (6 << 4)
66#define UART_CR_CMD_RESET_CTS (7 << 4)
67#define UART_CR_CMD_PACKET_MODE (9 << 4)
68#define UART_CR_CMD_MODE_RESET (12 << 4)
69#define UART_CR_CMD_SET_RFR (13 << 4)
70#define UART_CR_CMD_RESET_RFR (14 << 4)
71#define UART_CR_TX_DISABLE (1 << 3)
72#define UART_CR_TX_ENABLE (1 << 3)
73#define UART_CR_RX_DISABLE (1 << 3)
74#define UART_CR_RX_ENABLE (1 << 3)
75
76#define UART_IMR 0x0014
77#define UART_IMR_TXLEV (1 << 0)
78#define UART_IMR_RXSTALE (1 << 3)
79#define UART_IMR_RXLEV (1 << 4)
80#define UART_IMR_DELTA_CTS (1 << 5)
81#define UART_IMR_CURRENT_CTS (1 << 6)
82
83#define UART_IPR_RXSTALE_LAST 0x20
84#define UART_IPR_STALE_LSB 0x1F
85#define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80
86
87#define UART_IPR 0x0018
88#define UART_TFWR 0x001C
89#define UART_RFWR 0x0020
90#define UART_HCR 0x0024
91
92#define UART_MREG 0x0028
93#define UART_NREG 0x002C
94#define UART_DREG 0x0030
95#define UART_MNDREG 0x0034
96#define UART_IRDA 0x0038
97#define UART_MISR_MODE 0x0040
98#define UART_MISR_RESET 0x0044
99#define UART_MISR_EXPORT 0x0048
100#define UART_MISR_VAL 0x004C
101#define UART_TEST_CTRL 0x0050
102
103#define UART_SR 0x0008
104#define UART_SR_HUNT_CHAR (1 << 7)
105#define UART_SR_RX_BREAK (1 << 6)
106#define UART_SR_PAR_FRAME_ERR (1 << 5)
107#define UART_SR_OVERRUN (1 << 4)
108#define UART_SR_TX_EMPTY (1 << 3)
109#define UART_SR_TX_READY (1 << 2)
110#define UART_SR_RX_FULL (1 << 1)
111#define UART_SR_RX_READY (1 << 0)
112
113#define UART_RF 0x000C
114#define UART_MISR 0x0010
115#define UART_ISR 0x0014
116
117#endif /* __DRIVERS_SERIAL_MSM_SERIAL_H */
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 6fd80c4243f1..23d2fb051f97 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -171,6 +171,9 @@
171/* Timberdale UART */ 171/* Timberdale UART */
172#define PORT_TIMBUART 87 172#define PORT_TIMBUART 87
173 173
174/* Qualcomm MSM SoCs */
175#define PORT_MSM 88
176
174#ifdef __KERNEL__ 177#ifdef __KERNEL__
175 178
176#include <linux/compiler.h> 179#include <linux/compiler.h>
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 18:51:19 -0500