diff options
-rw-r--r-- | drivers/net/bnx2x_init.h | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h index 04f93bff2ef4..dcaecc53bdb1 100644 --- a/drivers/net/bnx2x_init.h +++ b/drivers/net/bnx2x_init.h | |||
@@ -1,6 +1,6 @@ | |||
1 | /* bnx2x_init.h: Broadcom Everest network driver. | 1 | /* bnx2x_init.h: Broadcom Everest network driver. |
2 | * | 2 | * |
3 | * Copyright (c) 2007 Broadcom Corporation | 3 | * Copyright (c) 2007-2008 Broadcom Corporation |
4 | * | 4 | * |
5 | * This program is free software; you can redistribute it and/or modify | 5 | * This program is free software; you can redistribute it and/or modify |
6 | * it under the terms of the GNU General Public License as published by | 6 | * it under the terms of the GNU General Public License as published by |
@@ -409,7 +409,7 @@ static void bnx2x_init_pxp(struct bnx2x *bp) | |||
409 | 409 | ||
410 | pci_read_config_word(bp->pdev, | 410 | pci_read_config_word(bp->pdev, |
411 | bp->pcie_cap + PCI_EXP_DEVCTL, (u16 *)&val); | 411 | bp->pcie_cap + PCI_EXP_DEVCTL, (u16 *)&val); |
412 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", val); | 412 | DP(NETIF_MSG_HW, "read 0x%x from devctl\n", (u16)val); |
413 | w_order = ((val & PCI_EXP_DEVCTL_PAYLOAD) >> 5); | 413 | w_order = ((val & PCI_EXP_DEVCTL_PAYLOAD) >> 5); |
414 | r_order = ((val & PCI_EXP_DEVCTL_READRQ) >> 12); | 414 | r_order = ((val & PCI_EXP_DEVCTL_READRQ) >> 12); |
415 | 415 | ||
@@ -472,10 +472,14 @@ static void bnx2x_init_pxp(struct bnx2x *bp) | |||
472 | REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val); | 472 | REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val); |
473 | 473 | ||
474 | REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order); | 474 | REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order); |
475 | REG_WR(bp, PXP2_REG_RQ_WR_MBS0 + 8, w_order); | 475 | REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order); |
476 | REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order); | 476 | REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order); |
477 | REG_WR(bp, PXP2_REG_RQ_RD_MBS0 + 8, r_order); | 477 | REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order); |
478 | 478 | ||
479 | if (r_order == MAX_RD_ORD) | ||
480 | REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00); | ||
481 | |||
482 | REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); | ||
479 | REG_WR(bp, PXP2_REG_WR_DMAE_TH, (128 << w_order)/16); | 483 | REG_WR(bp, PXP2_REG_WR_DMAE_TH, (128 << w_order)/16); |
480 | } | 484 | } |
481 | 485 | ||