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-rw-r--r--drivers/video/aty/radeon_accel.c8
-rw-r--r--include/video/radeon.h4
2 files changed, 12 insertions, 0 deletions
diff --git a/drivers/video/aty/radeon_accel.c b/drivers/video/aty/radeon_accel.c
index 4d13f68436e6..aa95f8350242 100644
--- a/drivers/video/aty/radeon_accel.c
+++ b/drivers/video/aty/radeon_accel.c
@@ -55,6 +55,10 @@ static void radeonfb_prim_fillrect(struct radeonfb_info *rinfo,
55 OUTREG(DP_WRITE_MSK, 0xffffffff); 55 OUTREG(DP_WRITE_MSK, 0xffffffff);
56 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM)); 56 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
57 57
58 radeon_fifo_wait(2);
59 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
60 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
61
58 radeon_fifo_wait(2); 62 radeon_fifo_wait(2);
59 OUTREG(DST_Y_X, (region->dy << 16) | region->dx); 63 OUTREG(DST_Y_X, (region->dy << 16) | region->dx);
60 OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height); 64 OUTREG(DST_WIDTH_HEIGHT, (region->width << 16) | region->height);
@@ -116,6 +120,10 @@ static void radeonfb_prim_copyarea(struct radeonfb_info *rinfo,
116 OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0) 120 OUTREG(DP_CNTL, (xdir>=0 ? DST_X_LEFT_TO_RIGHT : 0)
117 | (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0)); 121 | (ydir>=0 ? DST_Y_TOP_TO_BOTTOM : 0));
118 122
123 radeon_fifo_wait(2);
124 OUTREG(DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL);
125 OUTREG(WAIT_UNTIL, (WAIT_2D_IDLECLEAN | WAIT_DMA_GUI_IDLE));
126
119 radeon_fifo_wait(3); 127 radeon_fifo_wait(3);
120 OUTREG(SRC_Y_X, (sy << 16) | sx); 128 OUTREG(SRC_Y_X, (sy << 16) | sx);
121 OUTREG(DST_Y_X, (dy << 16) | dx); 129 OUTREG(DST_Y_X, (dy << 16) | dx);
diff --git a/include/video/radeon.h b/include/video/radeon.h
index 95a1f2038b1d..099ffa5e5bee 100644
--- a/include/video/radeon.h
+++ b/include/video/radeon.h
@@ -742,6 +742,10 @@
742#define SOFT_RESET_RB (1 << 6) 742#define SOFT_RESET_RB (1 << 6)
743#define SOFT_RESET_HDP (1 << 7) 743#define SOFT_RESET_HDP (1 << 7)
744 744
745/* WAIT_UNTIL bit constants */
746#define WAIT_DMA_GUI_IDLE (1 << 9)
747#define WAIT_2D_IDLECLEAN (1 << 16)
748
745/* SURFACE_CNTL bit consants */ 749/* SURFACE_CNTL bit consants */
746#define SURF_TRANSLATION_DIS (1 << 8) 750#define SURF_TRANSLATION_DIS (1 << 8)
747#define NONSURF_AP0_SWP_16BPP (1 << 20) 751#define NONSURF_AP0_SWP_16BPP (1 << 20)