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-rw-r--r--arch/arm/mach-omap1/devices.c2
-rw-r--r--arch/arm/mach-omap2/Makefile5
-rw-r--r--arch/arm/mach-omap2/clock.h1
-rw-r--r--arch/arm/mach-omap2/devices.c225
-rw-r--r--arch/arm/mach-omap2/gpmc.c81
-rw-r--r--arch/arm/mach-omap2/id.c39
-rw-r--r--arch/arm/mach-omap2/io.c19
-rw-r--r--arch/arm/mach-omap2/irq.c77
-rw-r--r--arch/arm/mach-omap2/memory.h7
-rw-r--r--arch/arm/mach-omap2/mux.c202
-rw-r--r--arch/arm/mach-omap2/serial.c100
-rw-r--r--arch/arm/mach-omap2/sleep24xx.S (renamed from arch/arm/mach-omap2/sleep.S)32
-rw-r--r--arch/arm/plat-omap/common.c4
-rw-r--r--arch/arm/plat-omap/devices.c11
-rw-r--r--arch/arm/plat-omap/include/mach/board-2430sdp.h6
-rw-r--r--arch/arm/plat-omap/include/mach/board-apollon.h6
-rw-r--r--arch/arm/plat-omap/include/mach/board-h4.h5
-rw-r--r--arch/arm/plat-omap/include/mach/board.h2
-rw-r--r--arch/arm/plat-omap/include/mach/common.h3
-rw-r--r--arch/arm/plat-omap/include/mach/control.h17
-rw-r--r--arch/arm/plat-omap/include/mach/cpu.h5
-rw-r--r--arch/arm/plat-omap/include/mach/gpio.h2
-rw-r--r--arch/arm/plat-omap/include/mach/gpmc.h8
-rw-r--r--arch/arm/plat-omap/include/mach/hardware.h2
-rw-r--r--arch/arm/plat-omap/include/mach/irqs.h6
-rw-r--r--arch/arm/plat-omap/include/mach/mux.h156
-rw-r--r--arch/arm/plat-omap/include/mach/omap1510.h2
-rw-r--r--arch/arm/plat-omap/include/mach/omap16xx.h7
-rw-r--r--arch/arm/plat-omap/include/mach/omap24xx.h1
-rw-r--r--arch/arm/plat-omap/include/mach/omapfb.h3
-rw-r--r--arch/arm/plat-omap/include/mach/pm.h3
-rw-r--r--arch/arm/plat-omap/include/mach/sdrc.h2
-rw-r--r--arch/arm/plat-omap/include/mach/serial.h6
33 files changed, 798 insertions, 249 deletions
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index ab708d4c597e..79cfe0147d93 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -101,7 +101,7 @@ static inline void omap_init_mbox(void) { }
101 101
102#if defined(CONFIG_OMAP_STI) 102#if defined(CONFIG_OMAP_STI)
103 103
104#define OMAP1_STI_BASE IO_ADDRESS(0xfffea000) 104#define OMAP1_STI_BASE 0xfffea000
105#define OMAP1_STI_CHANNEL_BASE (OMAP1_STI_BASE + 0x400) 105#define OMAP1_STI_CHANNEL_BASE (OMAP1_STI_BASE + 0x400)
106 106
107static struct resource sti_resources[] = { 107static struct resource sti_resources[] = {
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index e7cf1b4357ce..800639e7c6a4 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -14,7 +14,10 @@ obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
14obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o 14obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
15 15
16# Power Management 16# Power Management
17obj-$(CONFIG_PM) += pm.o sleep.o 17ifeq ($(CONFIG_PM),y)
18obj-y += pm.o
19obj-$(CONFIG_ARCH_OMAP24XX) += sleep24xx.o
20endif
18 21
19# Clock framework 22# Clock framework
20obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o 23obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index ea55f286f47d..1fb330e0847d 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -21,6 +21,7 @@
21/* The maximum error between a target DPLL rate and the rounded rate in Hz */ 21/* The maximum error between a target DPLL rate and the rounded rate in Hz */
22#define DEFAULT_DPLL_RATE_TOLERANCE 50000 22#define DEFAULT_DPLL_RATE_TOLERANCE 50000
23 23
24int omap2_clk_init(void);
24int omap2_clk_enable(struct clk *clk); 25int omap2_clk_enable(struct clk *clk);
25void omap2_clk_disable(struct clk *clk); 26void omap2_clk_disable(struct clk *clk);
26long omap2_clk_round_rate(struct clk *clk, unsigned long rate); 27long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 7a7f02559075..7cca33e23fd1 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -23,50 +23,7 @@
23#include <mach/board.h> 23#include <mach/board.h>
24#include <mach/mux.h> 24#include <mach/mux.h>
25#include <mach/gpio.h> 25#include <mach/gpio.h>
26 26#include <mach/eac.h>
27#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
28
29#define OMAP2_I2C_BASE2 0x48072000
30#define OMAP2_I2C_INT2 57
31
32static struct resource i2c_resources2[] = {
33 {
34 .start = OMAP2_I2C_BASE2,
35 .end = OMAP2_I2C_BASE2 + 0x3f,
36 .flags = IORESOURCE_MEM,
37 },
38 {
39 .start = OMAP2_I2C_INT2,
40 .flags = IORESOURCE_IRQ,
41 },
42};
43
44static struct platform_device omap_i2c_device2 = {
45 .name = "i2c_omap",
46 .id = 2,
47 .num_resources = ARRAY_SIZE(i2c_resources2),
48 .resource = i2c_resources2,
49};
50
51/* See also arch/arm/plat-omap/devices.c for first I2C on 24xx */
52static void omap_init_i2c(void)
53{
54 /* REVISIT: Second I2C not in use on H4? */
55 if (machine_is_omap_h4())
56 return;
57
58 if (!cpu_is_omap2430()) {
59 omap_cfg_reg(J15_24XX_I2C2_SCL);
60 omap_cfg_reg(H19_24XX_I2C2_SDA);
61 }
62 (void) platform_device_register(&omap_i2c_device2);
63}
64
65#else
66
67static void omap_init_i2c(void) {}
68
69#endif
70 27
71#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) 28#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
72#define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE) 29#define OMAP2_MBOX_BASE IO_ADDRESS(OMAP24XX_MAILBOX_BASE)
@@ -104,7 +61,9 @@ static inline void omap_init_mbox(void) { }
104 61
105#if defined(CONFIG_OMAP_STI) 62#if defined(CONFIG_OMAP_STI)
106 63
107#define OMAP2_STI_BASE IO_ADDRESS(0x48068000) 64#if defined(CONFIG_ARCH_OMAP2)
65
66#define OMAP2_STI_BASE 0x48068000
108#define OMAP2_STI_CHANNEL_BASE 0x54000000 67#define OMAP2_STI_CHANNEL_BASE 0x54000000
109#define OMAP2_STI_IRQ 4 68#define OMAP2_STI_IRQ 4
110 69
@@ -124,6 +83,25 @@ static struct resource sti_resources[] = {
124 .flags = IORESOURCE_IRQ, 83 .flags = IORESOURCE_IRQ,
125 } 84 }
126}; 85};
86#elif defined(CONFIG_ARCH_OMAP3)
87
88#define OMAP3_SDTI_BASE 0x54500000
89#define OMAP3_SDTI_CHANNEL_BASE 0x54600000
90
91static struct resource sti_resources[] = {
92 {
93 .start = OMAP3_SDTI_BASE,
94 .end = OMAP3_SDTI_BASE + 0xFFF,
95 .flags = IORESOURCE_MEM,
96 },
97 {
98 .start = OMAP3_SDTI_CHANNEL_BASE,
99 .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
100 .flags = IORESOURCE_MEM,
101 }
102};
103
104#endif
127 105
128static struct platform_device sti_device = { 106static struct platform_device sti_device = {
129 .name = "sti", 107 .name = "sti",
@@ -140,12 +118,14 @@ static inline void omap_init_sti(void)
140static inline void omap_init_sti(void) {} 118static inline void omap_init_sti(void) {}
141#endif 119#endif
142 120
143#if defined(CONFIG_SPI_OMAP24XX) 121#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
144 122
145#include <mach/mcspi.h> 123#include <mach/mcspi.h>
146 124
147#define OMAP2_MCSPI1_BASE 0x48098000 125#define OMAP2_MCSPI1_BASE 0x48098000
148#define OMAP2_MCSPI2_BASE 0x4809a000 126#define OMAP2_MCSPI2_BASE 0x4809a000
127#define OMAP2_MCSPI3_BASE 0x480b8000
128#define OMAP2_MCSPI4_BASE 0x480ba000
149 129
150static struct omap2_mcspi_platform_config omap2_mcspi1_config = { 130static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
151 .num_cs = 4, 131 .num_cs = 4,
@@ -159,7 +139,7 @@ static struct resource omap2_mcspi1_resources[] = {
159 }, 139 },
160}; 140};
161 141
162struct platform_device omap2_mcspi1 = { 142static struct platform_device omap2_mcspi1 = {
163 .name = "omap2_mcspi", 143 .name = "omap2_mcspi",
164 .id = 1, 144 .id = 1,
165 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources), 145 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
@@ -181,7 +161,7 @@ static struct resource omap2_mcspi2_resources[] = {
181 }, 161 },
182}; 162};
183 163
184struct platform_device omap2_mcspi2 = { 164static struct platform_device omap2_mcspi2 = {
185 .name = "omap2_mcspi", 165 .name = "omap2_mcspi",
186 .id = 2, 166 .id = 2,
187 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources), 167 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
@@ -191,16 +171,162 @@ struct platform_device omap2_mcspi2 = {
191 }, 171 },
192}; 172};
193 173
174#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
175static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
176 .num_cs = 2,
177};
178
179static struct resource omap2_mcspi3_resources[] = {
180 {
181 .start = OMAP2_MCSPI3_BASE,
182 .end = OMAP2_MCSPI3_BASE + 0xff,
183 .flags = IORESOURCE_MEM,
184 },
185};
186
187static struct platform_device omap2_mcspi3 = {
188 .name = "omap2_mcspi",
189 .id = 3,
190 .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
191 .resource = omap2_mcspi3_resources,
192 .dev = {
193 .platform_data = &omap2_mcspi3_config,
194 },
195};
196#endif
197
198#ifdef CONFIG_ARCH_OMAP3
199static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
200 .num_cs = 1,
201};
202
203static struct resource omap2_mcspi4_resources[] = {
204 {
205 .start = OMAP2_MCSPI4_BASE,
206 .end = OMAP2_MCSPI4_BASE + 0xff,
207 .flags = IORESOURCE_MEM,
208 },
209};
210
211static struct platform_device omap2_mcspi4 = {
212 .name = "omap2_mcspi",
213 .id = 4,
214 .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
215 .resource = omap2_mcspi4_resources,
216 .dev = {
217 .platform_data = &omap2_mcspi4_config,
218 },
219};
220#endif
221
194static void omap_init_mcspi(void) 222static void omap_init_mcspi(void)
195{ 223{
196 platform_device_register(&omap2_mcspi1); 224 platform_device_register(&omap2_mcspi1);
197 platform_device_register(&omap2_mcspi2); 225 platform_device_register(&omap2_mcspi2);
226#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
227 platform_device_register(&omap2_mcspi3);
228#endif
229#ifdef CONFIG_ARCH_OMAP3
230 platform_device_register(&omap2_mcspi4);
231#endif
198} 232}
199 233
200#else 234#else
201static inline void omap_init_mcspi(void) {} 235static inline void omap_init_mcspi(void) {}
202#endif 236#endif
203 237
238#ifdef CONFIG_SND_OMAP24XX_EAC
239
240#define OMAP2_EAC_BASE 0x48090000
241
242static struct resource omap2_eac_resources[] = {
243 {
244 .start = OMAP2_EAC_BASE,
245 .end = OMAP2_EAC_BASE + 0x109,
246 .flags = IORESOURCE_MEM,
247 },
248};
249
250static struct platform_device omap2_eac_device = {
251 .name = "omap24xx-eac",
252 .id = -1,
253 .num_resources = ARRAY_SIZE(omap2_eac_resources),
254 .resource = omap2_eac_resources,
255 .dev = {
256 .platform_data = NULL,
257 },
258};
259
260void omap_init_eac(struct eac_platform_data *pdata)
261{
262 omap2_eac_device.dev.platform_data = pdata;
263 platform_device_register(&omap2_eac_device);
264}
265
266#else
267void omap_init_eac(struct eac_platform_data *pdata) {}
268#endif
269
270#ifdef CONFIG_OMAP_SHA1_MD5
271static struct resource sha1_md5_resources[] = {
272 {
273 .start = OMAP24XX_SEC_SHA1MD5_BASE,
274 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
275 .flags = IORESOURCE_MEM,
276 },
277 {
278 .start = INT_24XX_SHA1MD5,
279 .flags = IORESOURCE_IRQ,
280 }
281};
282
283static struct platform_device sha1_md5_device = {
284 .name = "OMAP SHA1/MD5",
285 .id = -1,
286 .num_resources = ARRAY_SIZE(sha1_md5_resources),
287 .resource = sha1_md5_resources,
288};
289
290static void omap_init_sha1_md5(void)
291{
292 platform_device_register(&sha1_md5_device);
293}
294#else
295static inline void omap_init_sha1_md5(void) { }
296#endif
297
298#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
299#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
300#define OMAP_HDQ_BASE 0x480B2000
301#endif
302static struct resource omap_hdq_resources[] = {
303 {
304 .start = OMAP_HDQ_BASE,
305 .end = OMAP_HDQ_BASE + 0x1C,
306 .flags = IORESOURCE_MEM,
307 },
308 {
309 .start = INT_24XX_HDQ_IRQ,
310 .flags = IORESOURCE_IRQ,
311 },
312};
313static struct platform_device omap_hdq_dev = {
314 .name = "omap_hdq",
315 .id = 0,
316 .dev = {
317 .platform_data = NULL,
318 },
319 .num_resources = ARRAY_SIZE(omap_hdq_resources),
320 .resource = omap_hdq_resources,
321};
322static inline void omap_hdq_init(void)
323{
324 (void) platform_device_register(&omap_hdq_dev);
325}
326#else
327static inline void omap_hdq_init(void) {}
328#endif
329
204/*-------------------------------------------------------------------------*/ 330/*-------------------------------------------------------------------------*/
205 331
206static int __init omap2_init_devices(void) 332static int __init omap2_init_devices(void)
@@ -208,10 +334,11 @@ static int __init omap2_init_devices(void)
208 /* please keep these calls, and their implementations above, 334 /* please keep these calls, and their implementations above,
209 * in alphabetical order so they're easier to sort through. 335 * in alphabetical order so they're easier to sort through.
210 */ 336 */
211 omap_init_i2c();
212 omap_init_mbox(); 337 omap_init_mbox();
213 omap_init_mcspi(); 338 omap_init_mcspi();
339 omap_hdq_init();
214 omap_init_sti(); 340 omap_init_sti();
341 omap_init_sha1_md5();
215 342
216 return 0; 343 return 0;
217} 344}
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 9b4e58ee2ca2..149bfba43cfe 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -9,27 +9,23 @@
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12#undef DEBUG
13
12#include <linux/kernel.h> 14#include <linux/kernel.h>
13#include <linux/init.h> 15#include <linux/init.h>
14#include <linux/err.h> 16#include <linux/err.h>
15#include <linux/clk.h> 17#include <linux/clk.h>
16#include <linux/ioport.h> 18#include <linux/ioport.h>
17#include <linux/spinlock.h> 19#include <linux/spinlock.h>
20#include <linux/module.h>
18 21
19#include <asm/io.h> 22#include <asm/io.h>
20#include <asm/mach-types.h> 23#include <asm/mach-types.h>
21#include <mach/gpmc.h> 24#include <mach/gpmc.h>
22 25
23#undef DEBUG 26#include <mach/sdrc.h>
24
25#ifdef CONFIG_ARCH_OMAP2420
26#define GPMC_BASE 0x6800a000
27#endif
28
29#ifdef CONFIG_ARCH_OMAP2430
30#define GPMC_BASE 0x6E000000
31#endif
32 27
28/* GPMC register offsets */
33#define GPMC_REVISION 0x00 29#define GPMC_REVISION 0x00
34#define GPMC_SYSCONFIG 0x10 30#define GPMC_SYSCONFIG 0x10
35#define GPMC_SYSSTATUS 0x14 31#define GPMC_SYSSTATUS 0x14
@@ -51,7 +47,6 @@
51#define GPMC_CS0 0x60 47#define GPMC_CS0 0x60
52#define GPMC_CS_SIZE 0x30 48#define GPMC_CS_SIZE 0x30
53 49
54#define GPMC_CS_NUM 8
55#define GPMC_MEM_START 0x00000000 50#define GPMC_MEM_START 0x00000000
56#define GPMC_MEM_END 0x3FFFFFFF 51#define GPMC_MEM_END 0x3FFFFFFF
57#define BOOT_ROM_SPACE 0x100000 /* 1MB */ 52#define BOOT_ROM_SPACE 0x100000 /* 1MB */
@@ -64,10 +59,9 @@ static struct resource gpmc_cs_mem[GPMC_CS_NUM];
64static DEFINE_SPINLOCK(gpmc_mem_lock); 59static DEFINE_SPINLOCK(gpmc_mem_lock);
65static unsigned gpmc_cs_map; 60static unsigned gpmc_cs_map;
66 61
67static void __iomem *gpmc_base = IO_ADDRESS(GPMC_BASE); 62static void __iomem *gpmc_base;
68static void __iomem *gpmc_cs_base = IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
69 63
70static struct clk *gpmc_fck; 64static struct clk *gpmc_l3_clk;
71 65
72static void gpmc_write_reg(int idx, u32 val) 66static void gpmc_write_reg(int idx, u32 val)
73{ 67{
@@ -83,19 +77,32 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
83{ 77{
84 void __iomem *reg_addr; 78 void __iomem *reg_addr;
85 79
86 reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx; 80 reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
87 __raw_writel(val, reg_addr); 81 __raw_writel(val, reg_addr);
88} 82}
89 83
90u32 gpmc_cs_read_reg(int cs, int idx) 84u32 gpmc_cs_read_reg(int cs, int idx)
91{ 85{
92 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx); 86 void __iomem *reg_addr;
87
88 reg_addr = gpmc_base + GPMC_CS0 + (cs * GPMC_CS_SIZE) + idx;
89 return __raw_readl(reg_addr);
93} 90}
94 91
92/* TODO: Add support for gpmc_fck to clock framework and use it */
95unsigned long gpmc_get_fclk_period(void) 93unsigned long gpmc_get_fclk_period(void)
96{ 94{
97 /* In picoseconds */ 95 unsigned long rate = clk_get_rate(gpmc_l3_clk);
98 return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000); 96
97 if (rate == 0) {
98 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
99 return 0;
100 }
101
102 rate /= 1000;
103 rate = 1000000000 / rate; /* In picoseconds */
104
105 return rate;
99} 106}
100 107
101unsigned int gpmc_ns_to_ticks(unsigned int time_ns) 108unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
@@ -108,6 +115,11 @@ unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
108 return (time_ns * 1000 + tick_ps - 1) / tick_ps; 115 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
109} 116}
110 117
118unsigned int gpmc_ticks_to_ns(unsigned int ticks)
119{
120 return ticks * gpmc_get_fclk_period() / 1000;
121}
122
111unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns) 123unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
112{ 124{
113 unsigned long ticks = gpmc_ns_to_ticks(time_ns); 125 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
@@ -348,6 +360,7 @@ out:
348 spin_unlock(&gpmc_mem_lock); 360 spin_unlock(&gpmc_mem_lock);
349 return r; 361 return r;
350} 362}
363EXPORT_SYMBOL(gpmc_cs_request);
351 364
352void gpmc_cs_free(int cs) 365void gpmc_cs_free(int cs)
353{ 366{
@@ -363,8 +376,9 @@ void gpmc_cs_free(int cs)
363 gpmc_cs_set_reserved(cs, 0); 376 gpmc_cs_set_reserved(cs, 0);
364 spin_unlock(&gpmc_mem_lock); 377 spin_unlock(&gpmc_mem_lock);
365} 378}
379EXPORT_SYMBOL(gpmc_cs_free);
366 380
367void __init gpmc_mem_init(void) 381static void __init gpmc_mem_init(void)
368{ 382{
369 int cs; 383 int cs;
370 unsigned long boot_rom_space = 0; 384 unsigned long boot_rom_space = 0;
@@ -394,12 +408,33 @@ void __init gpmc_mem_init(void)
394void __init gpmc_init(void) 408void __init gpmc_init(void)
395{ 409{
396 u32 l; 410 u32 l;
411 char *ck;
412
413 if (cpu_is_omap24xx()) {
414 ck = "core_l3_ck";
415 if (cpu_is_omap2420())
416 l = OMAP2420_GPMC_BASE;
417 else
418 l = OMAP34XX_GPMC_BASE;
419 } else if (cpu_is_omap34xx()) {
420 ck = "gpmc_fck";
421 l = OMAP34XX_GPMC_BASE;
422 }
397 423
398 gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ 424 gpmc_l3_clk = clk_get(NULL, ck);
399 if (IS_ERR(gpmc_fck)) 425 if (IS_ERR(gpmc_l3_clk)) {
400 WARN_ON(1); 426 printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
401 else 427 return -ENODEV;
402 clk_enable(gpmc_fck); 428 }
429
430 gpmc_base = ioremap(l, SZ_4K);
431 if (!gpmc_base) {
432 clk_put(gpmc_l3_clk);
433 printk(KERN_ERR "Could not get GPMC register memory\n");
434 return -ENOMEM;
435 }
436
437 BUG_ON(IS_ERR(gpmc_l3_clk));
403 438
404 l = gpmc_read_reg(GPMC_REVISION); 439 l = gpmc_read_reg(GPMC_REVISION);
405 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); 440 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index e53ebe7d58be..0670c8db010a 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -17,24 +17,15 @@
17 17
18#include <asm/io.h> 18#include <asm/io.h>
19 19
20#include <mach/common.h>
20#include <mach/control.h> 21#include <mach/control.h>
21#include <mach/cpu.h> 22#include <mach/cpu.h>
22 23
23#if defined(CONFIG_ARCH_OMAP2420) 24static u32 class;
24#define TAP_BASE IO_ADDRESS(0x48014000) 25static void __iomem *tap_base;
25#elif defined(CONFIG_ARCH_OMAP2430) 26static u16 tap_prod_id;
26#define TAP_BASE IO_ADDRESS(0x4900A000)
27#elif defined(CONFIG_ARCH_OMAP34XX)
28#define TAP_BASE IO_ADDRESS(0x4830A000)
29#endif
30 27
31#define OMAP_TAP_IDCODE 0x0204 28#define OMAP_TAP_IDCODE 0x0204
32#if defined(CONFIG_ARCH_OMAP34XX)
33#define OMAP_TAP_PROD_ID 0x0210
34#else
35#define OMAP_TAP_PROD_ID 0x0208
36#endif
37
38#define OMAP_TAP_DIE_ID_0 0x0218 29#define OMAP_TAP_DIE_ID_0 0x0218
39#define OMAP_TAP_DIE_ID_1 0x021C 30#define OMAP_TAP_DIE_ID_1 0x021C
40#define OMAP_TAP_DIE_ID_2 0x0220 31#define OMAP_TAP_DIE_ID_2 0x0220
@@ -93,18 +84,24 @@ static u32 __init read_tap_reg(int reg)
93 * it means its Cortex r0p0 which is 3430 ES1 84 * it means its Cortex r0p0 which is 3430 ES1
94 */ 85 */
95 if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) { 86 if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
87
88 if (reg == tap_prod_id) {
89 regval = 0x000F00F0;
90 goto out;
91 }
92
96 switch (reg) { 93 switch (reg) {
97 case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break; 94 case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break;
98 /* Making DevType as 0xF in ES1 to differ from ES2 */ 95 /* Making DevType as 0xF in ES1 to differ from ES2 */
99 case OMAP_TAP_PROD_ID : regval = 0x000F00F0; break;
100 case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break; 96 case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
101 case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break; 97 case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
102 case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break; 98 case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
103 case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break; 99 case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
104 } 100 }
105 } else 101 } else
106 regval = __raw_readl(TAP_BASE + reg); 102 regval = __raw_readl(tap_base + reg);
107 103
104out:
108 return regval; 105 return regval;
109 106
110} 107}
@@ -203,7 +200,7 @@ void __init omap2_check_revision(void)
203 u8 rev; 200 u8 rev;
204 201
205 idcode = read_tap_reg(OMAP_TAP_IDCODE); 202 idcode = read_tap_reg(OMAP_TAP_IDCODE);
206 prod_id = read_tap_reg(OMAP_TAP_PROD_ID); 203 prod_id = read_tap_reg(tap_prod_id);
207 hawkeye = (idcode >> 12) & 0xffff; 204 hawkeye = (idcode >> 12) & 0xffff;
208 rev = (idcode >> 28) & 0x0f; 205 rev = (idcode >> 28) & 0x0f;
209 dev_type = (prod_id >> 16) & 0x0f; 206 dev_type = (prod_id >> 16) & 0x0f;
@@ -268,3 +265,13 @@ void __init omap2_check_revision(void)
268 265
269} 266}
270 267
268void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
269{
270 class = omap2_globals->class;
271 tap_base = omap2_globals->tap;
272
273 if (class == 0x3430)
274 tap_prod_id = 0x0210;
275 else
276 tap_prod_id = 0x0208;
277}
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 371e5409fef0..03c6ab1a3b1f 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -4,8 +4,11 @@
4 * OMAP2 I/O mapping code 4 * OMAP2 I/O mapping code
5 * 5 *
6 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2005 Nokia Corporation
7 * Author: Juha Yrjölä <juha.yrjola@nokia.com> 7 * Copyright (C) 2007 Texas Instruments
8 * Updated map desc to add 2430 support : <x0khasim@ti.com> 8 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
9 * 12 *
10 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as 14 * it under the terms of the GNU General Public License version 2 as
@@ -23,6 +26,11 @@
23 26
24#include <mach/mux.h> 27#include <mach/mux.h>
25#include <mach/omapfb.h> 28#include <mach/omapfb.h>
29#include <mach/sram.h>
30
31#include "memory.h"
32
33#include "clock.h"
26 34
27#include <mach/powerdomain.h> 35#include <mach/powerdomain.h>
28 36
@@ -31,13 +39,6 @@
31#include <mach/clockdomain.h> 39#include <mach/clockdomain.h>
32#include "clockdomains.h" 40#include "clockdomains.h"
33 41
34extern void omap_sram_init(void);
35extern int omap2_clk_init(void);
36extern void omap2_check_revision(void);
37extern void omap2_init_memory(void);
38extern void gpmc_init(void);
39extern void omapfb_reserve_sdram(void);
40
41/* 42/*
42 * The machine specific code may provide the extra mapping besides the 43 * The machine specific code may provide the extra mapping besides the
43 * default mapping provided here. 44 * default mapping provided here.
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 742bd0070e63..c39e26dc5ee3 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -13,17 +13,23 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/interrupt.h> 15#include <linux/interrupt.h>
16#include <linux/io.h>
16#include <mach/hardware.h> 17#include <mach/hardware.h>
17#include <asm/mach/irq.h> 18#include <asm/mach/irq.h>
18#include <asm/irq.h>
19#include <asm/io.h>
20 19
21#define INTC_REVISION 0x0000 20
22#define INTC_SYSCONFIG 0x0010 21/* selected INTC register offsets */
23#define INTC_SYSSTATUS 0x0014 22
24#define INTC_CONTROL 0x0048 23#define INTC_REVISION 0x0000
25#define INTC_MIR_CLEAR0 0x0088 24#define INTC_SYSCONFIG 0x0010
26#define INTC_MIR_SET0 0x008c 25#define INTC_SYSSTATUS 0x0014
26#define INTC_CONTROL 0x0048
27#define INTC_MIR_CLEAR0 0x0088
28#define INTC_MIR_SET0 0x008c
29#define INTC_PENDING_IRQ0 0x0098
30
31/* Number of IRQ state bits in each MIR register */
32#define IRQ_BITS_PER_REG 32
27 33
28/* 34/*
29 * OMAP2 has a number of different interrupt controllers, each interrupt 35 * OMAP2 has a number of different interrupt controllers, each interrupt
@@ -37,43 +43,45 @@ static struct omap_irq_bank {
37} __attribute__ ((aligned(4))) irq_banks[] = { 43} __attribute__ ((aligned(4))) irq_banks[] = {
38 { 44 {
39 /* MPU INTC */ 45 /* MPU INTC */
40 .base_reg = IO_ADDRESS(OMAP24XX_IC_BASE), 46 .base_reg = 0,
41 .nr_irqs = 96, 47 .nr_irqs = 96,
42 }, { 48 },
43 /* XXX: DSP INTC */
44 }
45}; 49};
46 50
51/* INTC bank register get/set */
52
53static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
54{
55 __raw_writel(val, bank->base_reg + reg);
56}
57
58static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
59{
60 return __raw_readl(bank->base_reg + reg);
61}
62
47/* XXX: FIQ and additional INTC support (only MPU at the moment) */ 63/* XXX: FIQ and additional INTC support (only MPU at the moment) */
48static void omap_ack_irq(unsigned int irq) 64static void omap_ack_irq(unsigned int irq)
49{ 65{
50 __raw_writel(0x1, irq_banks[0].base_reg + INTC_CONTROL); 66 intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
51} 67}
52 68
53static void omap_mask_irq(unsigned int irq) 69static void omap_mask_irq(unsigned int irq)
54{ 70{
55 int offset = (irq >> 5) << 5; 71 int offset = irq & (~(IRQ_BITS_PER_REG - 1));
56 72
57 if (irq >= 64) { 73 irq &= (IRQ_BITS_PER_REG - 1);
58 irq %= 64;
59 } else if (irq >= 32) {
60 irq %= 32;
61 }
62 74
63 __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_SET0 + offset); 75 intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
64} 76}
65 77
66static void omap_unmask_irq(unsigned int irq) 78static void omap_unmask_irq(unsigned int irq)
67{ 79{
68 int offset = (irq >> 5) << 5; 80 int offset = irq & (~(IRQ_BITS_PER_REG - 1));
69 81
70 if (irq >= 64) { 82 irq &= (IRQ_BITS_PER_REG - 1);
71 irq %= 64;
72 } else if (irq >= 32) {
73 irq %= 32;
74 }
75 83
76 __raw_writel(1 << irq, irq_banks[0].base_reg + INTC_MIR_CLEAR0 + offset); 84 intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
77} 85}
78 86
79static void omap_mask_ack_irq(unsigned int irq) 87static void omap_mask_ack_irq(unsigned int irq)
@@ -93,20 +101,20 @@ static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
93{ 101{
94 unsigned long tmp; 102 unsigned long tmp;
95 103
96 tmp = __raw_readl(bank->base_reg + INTC_REVISION) & 0xff; 104 tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
97 printk(KERN_INFO "IRQ: Found an INTC at 0x%p " 105 printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
98 "(revision %ld.%ld) with %d interrupts\n", 106 "(revision %ld.%ld) with %d interrupts\n",
99 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs); 107 bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
100 108
101 tmp = __raw_readl(bank->base_reg + INTC_SYSCONFIG); 109 tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
102 tmp |= 1 << 1; /* soft reset */ 110 tmp |= 1 << 1; /* soft reset */
103 __raw_writel(tmp, bank->base_reg + INTC_SYSCONFIG); 111 intc_bank_write_reg(tmp, bank, INTC_SYSCONFIG);
104 112
105 while (!(__raw_readl(bank->base_reg + INTC_SYSSTATUS) & 0x1)) 113 while (!(intc_bank_read_reg(bank, INTC_SYSSTATUS) & 0x1))
106 /* Wait for reset to complete */; 114 /* Wait for reset to complete */;
107 115
108 /* Enable autoidle */ 116 /* Enable autoidle */
109 __raw_writel(1 << 0, bank->base_reg + INTC_SYSCONFIG); 117 intc_bank_write_reg(1 << 0, bank, INTC_SYSCONFIG);
110} 118}
111 119
112void __init omap_init_irq(void) 120void __init omap_init_irq(void)
@@ -118,9 +126,8 @@ void __init omap_init_irq(void)
118 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { 126 for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
119 struct omap_irq_bank *bank = irq_banks + i; 127 struct omap_irq_bank *bank = irq_banks + i;
120 128
121 /* XXX */ 129 if (cpu_is_omap24xx())
122 if (!bank->base_reg) 130 bank->base_reg = OMAP2_IO_ADDRESS(OMAP24XX_IC_BASE);
123 continue;
124 131
125 omap_irq_bank_init_one(bank); 132 omap_irq_bank_init_one(bank);
126 133
diff --git a/arch/arm/mach-omap2/memory.h b/arch/arm/mach-omap2/memory.h
index 9a280b50a893..bb3db80a7c46 100644
--- a/arch/arm/mach-omap2/memory.h
+++ b/arch/arm/mach-omap2/memory.h
@@ -14,6 +14,9 @@
14 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
15 */ 15 */
16 16
17#ifndef ARCH_ARM_MACH_OMAP2_MEMORY_H
18#define ARCH_ARM_MACH_OMAP2_MEMORY_H
19
17/* Memory timings */ 20/* Memory timings */
18#define M_DDR 1 21#define M_DDR 1
19#define M_LOCK_CTRL (1 << 2) 22#define M_LOCK_CTRL (1 << 2)
@@ -34,3 +37,7 @@ extern u32 omap2_memory_get_fast_dll_ctrl(void);
34extern u32 omap2_memory_get_type(void); 37extern u32 omap2_memory_get_type(void);
35u32 omap2_dll_force_needed(void); 38u32 omap2_dll_force_needed(void);
36u32 omap2_reprogram_sdrc(u32 level, u32 force); 39u32 omap2_reprogram_sdrc(u32 level, u32 force);
40void __init omap2_init_memory(void);
41void __init gpmc_init(void);
42
43#endif
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 443d07fef7f3..6188e2f97854 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/mux.c 2 * linux/arch/arm/mach-omap2/mux.c
3 * 3 *
4 * OMAP2 pin multiplexing configurations 4 * OMAP2 and OMAP3 pin multiplexing configurations
5 * 5 *
6 * Copyright (C) 2004 - 2008 Texas Instruments Inc. 6 * Copyright (C) 2004 - 2008 Texas Instruments Inc.
7 * Copyright (C) 2003 - 2008 Nokia Corporation 7 * Copyright (C) 2003 - 2008 Nokia Corporation
@@ -219,16 +219,179 @@ MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF", 0x0131, 0, 0, 0, 1)
219#define OMAP24XX_PINS_SZ 0 219#define OMAP24XX_PINS_SZ 0
220#endif /* CONFIG_ARCH_OMAP24XX */ 220#endif /* CONFIG_ARCH_OMAP24XX */
221 221
222#define OMAP24XX_PULL_ENA (1 << 3) 222#ifdef CONFIG_ARCH_OMAP34XX
223#define OMAP24XX_PULL_UP (1 << 4) 223static struct pin_config __initdata_or_module omap34xx_pins[] = {
224/*
225 * Name, reg-offset,
226 * mux-mode | [active-mode | off-mode]
227 */
228
229/* 34xx I2C */
230MUX_CFG_34XX("K21_34XX_I2C1_SCL", 0x1ba,
231 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
232MUX_CFG_34XX("J21_34XX_I2C1_SDA", 0x1bc,
233 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
234MUX_CFG_34XX("AF15_34XX_I2C2_SCL", 0x1be,
235 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
236MUX_CFG_34XX("AE15_34XX_I2C2_SDA", 0x1c0,
237 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
238MUX_CFG_34XX("AF14_34XX_I2C3_SCL", 0x1c2,
239 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
240MUX_CFG_34XX("AG14_34XX_I2C3_SDA", 0x1c4,
241 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
242MUX_CFG_34XX("AD26_34XX_I2C4_SCL", 0xa00,
243 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
244MUX_CFG_34XX("AE26_34XX_I2C4_SDA", 0xa02,
245 OMAP34XX_MUX_MODE0 | OMAP34XX_PIN_INPUT_PULLUP)
246
247/* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
248MUX_CFG_34XX("Y8_3430_USB1HS_PHY_CLK", 0x5da,
249 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
250MUX_CFG_34XX("Y9_3430_USB1HS_PHY_STP", 0x5d8,
251 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
252MUX_CFG_34XX("AA14_3430_USB1HS_PHY_DIR", 0x5ec,
253 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
254MUX_CFG_34XX("AA11_3430_USB1HS_PHY_NXT", 0x5ee,
255 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
256MUX_CFG_34XX("W13_3430_USB1HS_PHY_D0", 0x5dc,
257 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
258MUX_CFG_34XX("W12_3430_USB1HS_PHY_D1", 0x5de,
259 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
260MUX_CFG_34XX("W11_3430_USB1HS_PHY_D2", 0x5e0,
261 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
262MUX_CFG_34XX("Y11_3430_USB1HS_PHY_D3", 0x5ea,
263 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
264MUX_CFG_34XX("W9_3430_USB1HS_PHY_D4", 0x5e4,
265 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
266MUX_CFG_34XX("Y12_3430_USB1HS_PHY_D5", 0x5e6,
267 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
268MUX_CFG_34XX("W8_3430_USB1HS_PHY_D6", 0x5e8,
269 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
270MUX_CFG_34XX("Y13_3430_USB1HS_PHY_D7", 0x5e2,
271 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
272
273/* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
274MUX_CFG_34XX("AA8_3430_USB2HS_PHY_CLK", 0x5f0,
275 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
276MUX_CFG_34XX("AA10_3430_USB2HS_PHY_STP", 0x5f2,
277 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_OUTPUT)
278MUX_CFG_34XX("AA9_3430_USB2HS_PHY_DIR", 0x5f4,
279 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
280MUX_CFG_34XX("AB11_3430_USB2HS_PHY_NXT", 0x5f6,
281 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
282MUX_CFG_34XX("AB10_3430_USB2HS_PHY_D0", 0x5f8,
283 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
284MUX_CFG_34XX("AB9_3430_USB2HS_PHY_D1", 0x5fa,
285 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
286MUX_CFG_34XX("W3_3430_USB2HS_PHY_D2", 0x1d4,
287 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
288MUX_CFG_34XX("T4_3430_USB2HS_PHY_D3", 0x1de,
289 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
290MUX_CFG_34XX("T3_3430_USB2HS_PHY_D4", 0x1d8,
291 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
292MUX_CFG_34XX("R3_3430_USB2HS_PHY_D5", 0x1da,
293 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
294MUX_CFG_34XX("R4_3430_USB2HS_PHY_D6", 0x1dc,
295 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
296MUX_CFG_34XX("T2_3430_USB2HS_PHY_D7", 0x1d6,
297 OMAP34XX_MUX_MODE3 | OMAP34XX_PIN_INPUT_PULLDOWN)
298
299/* TLL - HSUSB: 12-pin TLL Port 1*/
300MUX_CFG_34XX("Y8_3430_USB1HS_TLL_CLK", 0x5da,
301 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
302MUX_CFG_34XX("Y9_3430_USB1HS_TLL_STP", 0x5d8,
303 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
304MUX_CFG_34XX("AA14_3430_USB1HS_TLL_DIR", 0x5ec,
305 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
306MUX_CFG_34XX("AA11_3430_USB1HS_TLL_NXT", 0x5ee,
307 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
308MUX_CFG_34XX("W13_3430_USB1HS_TLL_D0", 0x5dc,
309 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
310MUX_CFG_34XX("W12_3430_USB1HS_TLL_D1", 0x5de,
311 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
312MUX_CFG_34XX("W11_3430_USB1HS_TLL_D2", 0x5e0,
313 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
314MUX_CFG_34XX("Y11_3430_USB1HS_TLL_D3", 0x5ea,
315 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
316MUX_CFG_34XX("W9_3430_USB1HS_TLL_D4", 0x5e4,
317 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
318MUX_CFG_34XX("Y12_3430_USB1HS_TLL_D5", 0x5e6,
319 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
320MUX_CFG_34XX("W8_3430_USB1HS_TLL_D6", 0x5e8,
321 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
322MUX_CFG_34XX("Y13_3430_USB1HS_TLL_D7", 0x5e2,
323 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
324
325/* TLL - HSUSB: 12-pin TLL Port 2*/
326MUX_CFG_34XX("AA8_3430_USB2HS_TLL_CLK", 0x5f0,
327 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
328MUX_CFG_34XX("AA10_3430_USB2HS_TLL_STP", 0x5f2,
329 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
330MUX_CFG_34XX("AA9_3430_USB2HS_TLL_DIR", 0x5f4,
331 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
332MUX_CFG_34XX("AB11_3430_USB2HS_TLL_NXT", 0x5f6,
333 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_OUTPUT)
334MUX_CFG_34XX("AB10_3430_USB2HS_TLL_D0", 0x5f8,
335 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
336MUX_CFG_34XX("AB9_3430_USB2HS_TLL_D1", 0x5fa,
337 OMAP34XX_MUX_MODE6 | OMAP34XX_PIN_INPUT_PULLDOWN)
338MUX_CFG_34XX("W3_3430_USB2HS_TLL_D2", 0x1d4,
339 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
340MUX_CFG_34XX("T4_3430_USB2HS_TLL_D3", 0x1de,
341 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
342MUX_CFG_34XX("T3_3430_USB2HS_TLL_D4", 0x1d8,
343 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
344MUX_CFG_34XX("R3_3430_USB2HS_TLL_D5", 0x1da,
345 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
346MUX_CFG_34XX("R4_3430_USB2HS_TLL_D6", 0x1dc,
347 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
348MUX_CFG_34XX("T2_3430_USB2HS_TLL_D7", 0x1d6,
349 OMAP34XX_MUX_MODE2 | OMAP34XX_PIN_INPUT_PULLDOWN)
350
351/* TLL - HSUSB: 12-pin TLL Port 3*/
352MUX_CFG_34XX("AA6_3430_USB3HS_TLL_CLK", 0x180,
353 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
354MUX_CFG_34XX("AB3_3430_USB3HS_TLL_STP", 0x166,
355 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
356MUX_CFG_34XX("AA3_3430_USB3HS_TLL_DIR", 0x168,
357 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
358MUX_CFG_34XX("Y3_3430_USB3HS_TLL_NXT", 0x16a,
359 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_OUTPUT)
360MUX_CFG_34XX("AA5_3430_USB3HS_TLL_D0", 0x186,
361 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
362MUX_CFG_34XX("Y4_3430_USB3HS_TLL_D1", 0x184,
363 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
364MUX_CFG_34XX("Y5_3430_USB3HS_TLL_D2", 0x188,
365 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
366MUX_CFG_34XX("W5_3430_USB3HS_TLL_D3", 0x18a,
367 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
368MUX_CFG_34XX("AB12_3430_USB3HS_TLL_D4", 0x16c,
369 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
370MUX_CFG_34XX("AB13_3430_USB3HS_TLL_D5", 0x16e,
371 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
372MUX_CFG_34XX("AA13_3430_USB3HS_TLL_D6", 0x170,
373 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
374MUX_CFG_34XX("AA12_3430_USB3HS_TLL_D7", 0x172,
375 OMAP34XX_MUX_MODE5 | OMAP34XX_PIN_INPUT_PULLDOWN)
376};
377
378#define OMAP34XX_PINS_SZ ARRAY_SIZE(omap34xx_pins)
379
380#else
381#define omap34xx_pins NULL
382#define OMAP34XX_PINS_SZ 0
383#endif /* CONFIG_ARCH_OMAP34XX */
224 384
225#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS) 385#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
226void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg) 386static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
227{ 387{
228 u16 orig; 388 u16 orig;
229 u8 warn = 0, debug = 0; 389 u8 warn = 0, debug = 0;
230 390
231 orig = omap_ctrl_readb(cfg->mux_reg); 391 if (cpu_is_omap24xx())
392 orig = omap_ctrl_readb(cfg->mux_reg);
393 else
394 orig = omap_ctrl_readw(cfg->mux_reg);
232 395
233#ifdef CONFIG_OMAP_MUX_DEBUG 396#ifdef CONFIG_OMAP_MUX_DEBUG
234 debug = cfg->debug; 397 debug = cfg->debug;
@@ -254,9 +417,9 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
254 spin_lock_irqsave(&mux_spin_lock, flags); 417 spin_lock_irqsave(&mux_spin_lock, flags);
255 reg |= cfg->mask & 0x7; 418 reg |= cfg->mask & 0x7;
256 if (cfg->pull_val) 419 if (cfg->pull_val)
257 reg |= OMAP24XX_PULL_ENA; 420 reg |= OMAP2_PULL_ENA;
258 if (cfg->pu_pd_val) 421 if (cfg->pu_pd_val)
259 reg |= OMAP24XX_PULL_UP; 422 reg |= OMAP2_PULL_UP;
260 omap2_cfg_debug(cfg, reg); 423 omap2_cfg_debug(cfg, reg);
261 omap_ctrl_writeb(reg, cfg->mux_reg); 424 omap_ctrl_writeb(reg, cfg->mux_reg);
262 spin_unlock_irqrestore(&mux_spin_lock, flags); 425 spin_unlock_irqrestore(&mux_spin_lock, flags);
@@ -264,7 +427,26 @@ int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
264 return 0; 427 return 0;
265} 428}
266#else 429#else
267#define omap24xx_cfg_reg 0 430#define omap24xx_cfg_reg NULL
431#endif
432
433#ifdef CONFIG_ARCH_OMAP34XX
434static int __init_or_module omap34xx_cfg_reg(const struct pin_config *cfg)
435{
436 static DEFINE_SPINLOCK(mux_spin_lock);
437 unsigned long flags;
438 u16 reg = 0;
439
440 spin_lock_irqsave(&mux_spin_lock, flags);
441 reg |= cfg->mux_val;
442 omap2_cfg_debug(cfg, reg);
443 omap_ctrl_writew(reg, cfg->mux_reg);
444 spin_unlock_irqrestore(&mux_spin_lock, flags);
445
446 return 0;
447}
448#else
449#define omap34xx_cfg_reg NULL
268#endif 450#endif
269 451
270int __init omap2_mux_init(void) 452int __init omap2_mux_init(void)
@@ -273,6 +455,10 @@ int __init omap2_mux_init(void)
273 arch_mux_cfg.pins = omap24xx_pins; 455 arch_mux_cfg.pins = omap24xx_pins;
274 arch_mux_cfg.size = OMAP24XX_PINS_SZ; 456 arch_mux_cfg.size = OMAP24XX_PINS_SZ;
275 arch_mux_cfg.cfg_reg = omap24xx_cfg_reg; 457 arch_mux_cfg.cfg_reg = omap24xx_cfg_reg;
458 } else if (cpu_is_omap34xx()) {
459 arch_mux_cfg.pins = omap34xx_pins;
460 arch_mux_cfg.size = OMAP34XX_PINS_SZ;
461 arch_mux_cfg.cfg_reg = omap34xx_cfg_reg;
276 } 462 }
277 463
278 return omap_mux_register(&arch_mux_cfg); 464 return omap_mux_register(&arch_mux_cfg);
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 69651cf08305..78ab2be70241 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -3,7 +3,7 @@
3 * 3 *
4 * OMAP2 serial support. 4 * OMAP2 serial support.
5 * 5 *
6 * Copyright (C) 2005 Nokia Corporation 6 * Copyright (C) 2005-2008 Nokia Corporation
7 * Author: Paul Mundt <paul.mundt@nokia.com> 7 * Author: Paul Mundt <paul.mundt@nokia.com>
8 * 8 *
9 * Based off of arch/arm/mach-omap/omap1/serial.c 9 * Based off of arch/arm/mach-omap/omap1/serial.c
@@ -23,12 +23,8 @@
23#include <mach/common.h> 23#include <mach/common.h>
24#include <mach/board.h> 24#include <mach/board.h>
25 25
26static struct clk * uart1_ick = NULL; 26static struct clk *uart_ick[OMAP_MAX_NR_PORTS];
27static struct clk * uart1_fck = NULL; 27static struct clk *uart_fck[OMAP_MAX_NR_PORTS];
28static struct clk * uart2_ick = NULL;
29static struct clk * uart2_fck = NULL;
30static struct clk * uart3_ick = NULL;
31static struct clk * uart3_fck = NULL;
32 28
33static struct plat_serial8250_port serial_platform_data[] = { 29static struct plat_serial8250_port serial_platform_data[] = {
34 { 30 {
@@ -38,7 +34,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
38 .flags = UPF_BOOT_AUTOCONF, 34 .flags = UPF_BOOT_AUTOCONF,
39 .iotype = UPIO_MEM, 35 .iotype = UPIO_MEM,
40 .regshift = 2, 36 .regshift = 2,
41 .uartclk = OMAP16XX_BASE_BAUD * 16, 37 .uartclk = OMAP24XX_BASE_BAUD * 16,
42 }, { 38 }, {
43 .membase = IO_ADDRESS(OMAP_UART2_BASE), 39 .membase = IO_ADDRESS(OMAP_UART2_BASE),
44 .mapbase = OMAP_UART2_BASE, 40 .mapbase = OMAP_UART2_BASE,
@@ -46,7 +42,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
46 .flags = UPF_BOOT_AUTOCONF, 42 .flags = UPF_BOOT_AUTOCONF,
47 .iotype = UPIO_MEM, 43 .iotype = UPIO_MEM,
48 .regshift = 2, 44 .regshift = 2,
49 .uartclk = OMAP16XX_BASE_BAUD * 16, 45 .uartclk = OMAP24XX_BASE_BAUD * 16,
50 }, { 46 }, {
51 .membase = IO_ADDRESS(OMAP_UART3_BASE), 47 .membase = IO_ADDRESS(OMAP_UART3_BASE),
52 .mapbase = OMAP_UART3_BASE, 48 .mapbase = OMAP_UART3_BASE,
@@ -54,7 +50,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
54 .flags = UPF_BOOT_AUTOCONF, 50 .flags = UPF_BOOT_AUTOCONF,
55 .iotype = UPIO_MEM, 51 .iotype = UPIO_MEM,
56 .regshift = 2, 52 .regshift = 2,
57 .uartclk = OMAP16XX_BASE_BAUD * 16, 53 .uartclk = OMAP24XX_BASE_BAUD * 16,
58 }, { 54 }, {
59 .flags = 0 55 .flags = 0
60 } 56 }
@@ -87,10 +83,27 @@ static inline void __init omap_serial_reset(struct plat_serial8250_port *p)
87 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0)); 83 serial_write_reg(p, UART_OMAP_SYSC, (0x02 << 3) | (1 << 2) | (1 << 0));
88} 84}
89 85
90void __init omap_serial_init() 86void omap_serial_enable_clocks(int enable)
87{
88 int i;
89 for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
90 if (uart_ick[i] && uart_fck[i]) {
91 if (enable) {
92 clk_enable(uart_ick[i]);
93 clk_enable(uart_fck[i]);
94 } else {
95 clk_disable(uart_ick[i]);
96 clk_disable(uart_fck[i]);
97 }
98 }
99 }
100}
101
102void __init omap_serial_init(void)
91{ 103{
92 int i; 104 int i;
93 const struct omap_uart_config *info; 105 const struct omap_uart_config *info;
106 char name[16];
94 107
95 /* 108 /*
96 * Make sure the serial ports are muxed on at this point. 109 * Make sure the serial ports are muxed on at this point.
@@ -98,8 +111,7 @@ void __init omap_serial_init()
98 * if not needed. 111 * if not needed.
99 */ 112 */
100 113
101 info = omap_get_config(OMAP_TAG_UART, 114 info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
102 struct omap_uart_config);
103 115
104 if (info == NULL) 116 if (info == NULL)
105 return; 117 return;
@@ -113,53 +125,21 @@ void __init omap_serial_init()
113 continue; 125 continue;
114 } 126 }
115 127
116 switch (i) { 128 sprintf(name, "uart%d_ick", i+1);
117 case 0: 129 uart_ick[i] = clk_get(NULL, name);
118 uart1_ick = clk_get(NULL, "uart1_ick"); 130 if (IS_ERR(uart_ick[i])) {
119 if (IS_ERR(uart1_ick)) 131 printk(KERN_ERR "Could not get uart%d_ick\n", i+1);
120 printk("Could not get uart1_ick\n"); 132 uart_ick[i] = NULL;
121 else { 133 } else
122 clk_enable(uart1_ick); 134 clk_enable(uart_ick[i]);
123 } 135
124 136 sprintf(name, "uart%d_fck", i+1);
125 uart1_fck = clk_get(NULL, "uart1_fck"); 137 uart_fck[i] = clk_get(NULL, name);
126 if (IS_ERR(uart1_fck)) 138 if (IS_ERR(uart_fck[i])) {
127 printk("Could not get uart1_fck\n"); 139 printk(KERN_ERR "Could not get uart%d_fck\n", i+1);
128 else { 140 uart_fck[i] = NULL;
129 clk_enable(uart1_fck); 141 } else
130 } 142 clk_enable(uart_fck[i]);
131 break;
132 case 1:
133 uart2_ick = clk_get(NULL, "uart2_ick");
134 if (IS_ERR(uart2_ick))
135 printk("Could not get uart2_ick\n");
136 else {
137 clk_enable(uart2_ick);
138 }
139
140 uart2_fck = clk_get(NULL, "uart2_fck");
141 if (IS_ERR(uart2_fck))
142 printk("Could not get uart2_fck\n");
143 else {
144 clk_enable(uart2_fck);
145 }
146 break;
147 case 2:
148 uart3_ick = clk_get(NULL, "uart3_ick");
149 if (IS_ERR(uart3_ick))
150 printk("Could not get uart3_ick\n");
151 else {
152 clk_enable(uart3_ick);
153 }
154
155 uart3_fck = clk_get(NULL, "uart3_fck");
156 if (IS_ERR(uart3_fck))
157 printk("Could not get uart3_fck\n");
158 else {
159 clk_enable(uart3_fck);
160 }
161 break;
162 }
163 143
164 omap_serial_reset(p); 144 omap_serial_reset(p);
165 } 145 }
diff --git a/arch/arm/mach-omap2/sleep.S b/arch/arm/mach-omap2/sleep24xx.S
index 87a706fd5f82..43336b93b21c 100644
--- a/arch/arm/mach-omap2/sleep.S
+++ b/arch/arm/mach-omap2/sleep24xx.S
@@ -5,6 +5,10 @@
5 * Texas Instruments, <www.ti.com> 5 * Texas Instruments, <www.ti.com>
6 * Richard Woodruff <r-woodruff2@ti.com> 6 * Richard Woodruff <r-woodruff2@ti.com>
7 * 7 *
8 * (C) Copyright 2006 Nokia Corporation
9 * Fixed idle loop sleep
10 * Igor Stoppa <igor.stoppa@nokia.com>
11 *
8 * This program is free software; you can redistribute it and/or 12 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 13 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 14 * published by the Free Software Foundation; either version 2 of
@@ -26,6 +30,8 @@
26#include <mach/io.h> 30#include <mach/io.h>
27#include <mach/pm.h> 31#include <mach/pm.h>
28 32
33#include <mach/omap24xx.h>
34
29#include "sdrc.h" 35#include "sdrc.h"
30 36
31/* First address of reserved address space? apparently valid for OMAP2 & 3 */ 37/* First address of reserved address space? apparently valid for OMAP2 & 3 */
@@ -52,15 +58,14 @@ ENTRY(omap24xx_idle_loop_suspend_sz)
52 .word . - omap24xx_idle_loop_suspend 58 .word . - omap24xx_idle_loop_suspend
53 59
54/* 60/*
55 * omap242x_cpu_suspend() - Forces OMAP into deep sleep state by completing 61 * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
56 * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore 62 * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
57 * SDRC. 63 * SDRC.
58 * 64 *
59 * Input: 65 * Input:
60 * R0 : DLL ctrl value pre-Sleep 66 * R0 : DLL ctrl value pre-Sleep
61 * R1 : Processor+Revision 67 * R1 : SDRC_DLLA_CTRL
62 * 2420: 0x21 = 242xES1, 0x26 = 242xES2.2 68 * R2 : SDRC_POWER
63 * 2430: 0x31 = 2430ES1, 0x32 = 2430ES2
64 * 69 *
65 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on 70 * The if the DPLL is going to AutoIdle. It seems like the DPLL may be back on
66 * when we get called, but the DLL probably isn't. We will wait a bit more in 71 * when we get called, but the DLL probably isn't. We will wait a bit more in
@@ -80,15 +85,14 @@ ENTRY(omap24xx_idle_loop_suspend_sz)
80 */ 85 */
81ENTRY(omap24xx_cpu_suspend) 86ENTRY(omap24xx_cpu_suspend)
82 stmfd sp!, {r0 - r12, lr} @ save registers on stack 87 stmfd sp!, {r0 - r12, lr} @ save registers on stack
83 mov r3, #0x0 @ clear for mrc call 88 mov r3, #0x0 @ clear for mcr call
84 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished 89 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
85 nop 90 nop
86 nop 91 nop
87 ldr r3, A_SDRC_POWER @ addr of sdrc power 92 ldr r4, [r2] @ read SDRC_POWER
88 ldr r4, [r3] @ value of sdrc power
89 orr r4, r4, #0x40 @ enable self refresh on idle req 93 orr r4, r4, #0x40 @ enable self refresh on idle req
90 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock) 94 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
91 str r4, [r3] @ make it so 95 str r4, [r2] @ make it so
92 mov r2, #0 96 mov r2, #0
93 nop 97 nop
94 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt 98 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
@@ -97,14 +101,13 @@ loop:
97 subs r5, r5, #0x1 @ awake, wait just a bit 101 subs r5, r5, #0x1 @ awake, wait just a bit
98 bne loop 102 bne loop
99 103
100 /* The DPLL has on before we take the DDR out of self refresh */ 104 /* The DPLL has to be on before we take the DDR out of self refresh */
101 bic r4, r4, #0x40 @ now clear self refresh bit. 105 bic r4, r4, #0x40 @ now clear self refresh bit.
102 str r4, [r3] @ put vlaue back. 106 str r4, [r2] @ write to SDRC_POWER
103 ldr r4, A_SDRC0 @ make a clock happen 107 ldr r4, A_SDRC0 @ make a clock happen
104 ldr r4, [r4] 108 ldr r4, [r4] @ read A_SDRC0
105 nop @ start auto refresh only after clk ok 109 nop @ start auto refresh only after clk ok
106 movs r0, r0 @ see if DDR or SDR 110 movs r0, r0 @ see if DDR or SDR
107 ldrne r1, A_SDRC_DLLA_CTRL_S @ get addr of DLL ctrl
108 strne r0, [r1] @ rewrite DLLA to force DLL reload 111 strne r0, [r1] @ rewrite DLLA to force DLL reload
109 addne r1, r1, #0x8 @ move to DLLB 112 addne r1, r1, #0x8 @ move to DLLB
110 strne r0, [r1] @ rewrite DLLB to force DLL reload 113 strne r0, [r1] @ rewrite DLLB to force DLL reload
@@ -116,13 +119,8 @@ loop2:
116 /* resume*/ 119 /* resume*/
117 ldmfd sp!, {r0 - r12, pc} @ restore regs and return 120 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
118 121
119A_SDRC_POWER:
120 .word OMAP242X_SDRC_REGADDR(SDRC_POWER)
121A_SDRC0: 122A_SDRC0:
122 .word A_SDRC0_V 123 .word A_SDRC0_V
123A_SDRC_DLLA_CTRL_S:
124 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
125 124
126ENTRY(omap24xx_cpu_suspend_sz) 125ENTRY(omap24xx_cpu_suspend_sz)
127 .word . - omap24xx_cpu_suspend 126 .word . - omap24xx_cpu_suspend
128
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index 20e8db5fe32a..e3143fe9cb29 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -248,6 +248,7 @@ static struct omap_globals *omap2_globals;
248 248
249static void __init __omap2_set_globals(void) 249static void __init __omap2_set_globals(void)
250{ 250{
251 omap2_set_globals_tap(omap2_globals);
251 omap2_set_globals_memory(omap2_globals); 252 omap2_set_globals_memory(omap2_globals);
252 omap2_set_globals_control(omap2_globals); 253 omap2_set_globals_control(omap2_globals);
253 omap2_set_globals_prcm(omap2_globals); 254 omap2_set_globals_prcm(omap2_globals);
@@ -258,6 +259,7 @@ static void __init __omap2_set_globals(void)
258#if defined(CONFIG_ARCH_OMAP2420) 259#if defined(CONFIG_ARCH_OMAP2420)
259 260
260static struct omap_globals omap242x_globals = { 261static struct omap_globals omap242x_globals = {
262 .class = OMAP242X_CLASS,
261 .tap = OMAP2_IO_ADDRESS(0x48014000), 263 .tap = OMAP2_IO_ADDRESS(0x48014000),
262 .sdrc = OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE), 264 .sdrc = OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
263 .sms = OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE), 265 .sms = OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
@@ -276,6 +278,7 @@ void __init omap2_set_globals_242x(void)
276#if defined(CONFIG_ARCH_OMAP2430) 278#if defined(CONFIG_ARCH_OMAP2430)
277 279
278static struct omap_globals omap243x_globals = { 280static struct omap_globals omap243x_globals = {
281 .class = OMAP243X_CLASS,
279 .tap = OMAP2_IO_ADDRESS(0x4900a000), 282 .tap = OMAP2_IO_ADDRESS(0x4900a000),
280 .sdrc = OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE), 283 .sdrc = OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
281 .sms = OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE), 284 .sms = OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
@@ -294,6 +297,7 @@ void __init omap2_set_globals_243x(void)
294#if defined(CONFIG_ARCH_OMAP3430) 297#if defined(CONFIG_ARCH_OMAP3430)
295 298
296static struct omap_globals omap343x_globals = { 299static struct omap_globals omap343x_globals = {
300 .class = OMAP343X_CLASS,
297 .tap = OMAP2_IO_ADDRESS(0x4830A000), 301 .tap = OMAP2_IO_ADDRESS(0x4830A000),
298 .sdrc = OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE), 302 .sdrc = OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
299 .sms = OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE), 303 .sms = OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 187e3d8bfdfe..1c1d831a0c09 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -20,16 +20,16 @@
20#include <asm/mach/map.h> 20#include <asm/mach/map.h>
21 21
22#include <mach/tc.h> 22#include <mach/tc.h>
23#include <mach/control.h>
23#include <mach/board.h> 24#include <mach/board.h>
24#include <mach/mux.h> 25#include <mach/mux.h>
25#include <mach/gpio.h> 26#include <mach/gpio.h>
26#include <mach/menelaus.h> 27#include <mach/menelaus.h>
27#include <mach/mcbsp.h> 28#include <mach/mcbsp.h>
29#include <mach/dsp_common.h>
28 30
29#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) 31#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
30 32
31#include "../plat-omap/dsp/dsp_common.h"
32
33static struct dsp_platform_data dsp_pdata = { 33static struct dsp_platform_data dsp_pdata = {
34 .kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list), 34 .kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list),
35}; 35};
@@ -75,7 +75,7 @@ int dsp_kfunc_device_register(struct dsp_kfunc_device *kdev)
75{ 75{
76 static DEFINE_MUTEX(dsp_pdata_lock); 76 static DEFINE_MUTEX(dsp_pdata_lock);
77 77
78 mutex_init(&kdev->lock); 78 spin_lock_init(&kdev->lock);
79 79
80 mutex_lock(&dsp_pdata_lock); 80 mutex_lock(&dsp_pdata_lock);
81 list_add_tail(&kdev->entry, &dsp_pdata.kdev_list); 81 list_add_tail(&kdev->entry, &dsp_pdata.kdev_list);
@@ -479,10 +479,6 @@ static inline void omap_init_rng(void) {}
479 */ 479 */
480static int __init omap_init_devices(void) 480static int __init omap_init_devices(void)
481{ 481{
482/*
483 * Need to enable relevant once for 2430 SDP
484 */
485#ifndef CONFIG_MACH_OMAP_2430SDP
486 /* please keep these calls, and their implementations above, 482 /* please keep these calls, and their implementations above,
487 * in alphabetical order so they're easier to sort through. 483 * in alphabetical order so they're easier to sort through.
488 */ 484 */
@@ -492,7 +488,6 @@ static int __init omap_init_devices(void)
492 omap_init_uwire(); 488 omap_init_uwire();
493 omap_init_wdt(); 489 omap_init_wdt();
494 omap_init_rng(); 490 omap_init_rng();
495#endif
496 return 0; 491 return 0;
497} 492}
498arch_initcall(omap_init_devices); 493arch_initcall(omap_init_devices);
diff --git a/arch/arm/plat-omap/include/mach/board-2430sdp.h b/arch/arm/plat-omap/include/mach/board-2430sdp.h
index cf1dc0223949..10d449ea7ed0 100644
--- a/arch/arm/plat-omap/include/mach/board-2430sdp.h
+++ b/arch/arm/plat-omap/include/mach/board-2430sdp.h
@@ -30,10 +30,12 @@
30#define __ASM_ARCH_OMAP_2430SDP_H 30#define __ASM_ARCH_OMAP_2430SDP_H
31 31
32/* Placeholder for 2430SDP specific defines */ 32/* Placeholder for 2430SDP specific defines */
33#define OMAP24XX_ETHR_START 0x08000300 33#define OMAP24XX_ETHR_START 0x08000300
34#define OMAP24XX_ETHR_GPIO_IRQ 149 34#define OMAP24XX_ETHR_GPIO_IRQ 149
35#define SDP2430_CS0_BASE 0x04000000 35#define SDP2430_CS0_BASE 0x04000000
36 36
37#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ 37/* Function prototypes */
38extern void sdp2430_flash_init(void);
39extern void sdp2430_usb_init(void);
38 40
39#endif /* __ASM_ARCH_OMAP_2430SDP_H */ 41#endif /* __ASM_ARCH_OMAP_2430SDP_H */
diff --git a/arch/arm/plat-omap/include/mach/board-apollon.h b/arch/arm/plat-omap/include/mach/board-apollon.h
index d6f2a8e963d5..731c858cf3fe 100644
--- a/arch/arm/plat-omap/include/mach/board-apollon.h
+++ b/arch/arm/plat-omap/include/mach/board-apollon.h
@@ -31,6 +31,12 @@
31 31
32extern void apollon_mmc_init(void); 32extern void apollon_mmc_init(void);
33 33
34static inline int apollon_plus(void)
35{
36 /* The apollon plus has IDCODE revision 5 */
37 return system_rev & 0xc0;
38}
39
34/* Placeholder for APOLLON specific defines */ 40/* Placeholder for APOLLON specific defines */
35#define APOLLON_ETHR_GPIO_IRQ 74 41#define APOLLON_ETHR_GPIO_IRQ 74
36 42
diff --git a/arch/arm/plat-omap/include/mach/board-h4.h b/arch/arm/plat-omap/include/mach/board-h4.h
index 1470cd3e519b..7c3fa0f0a65e 100644
--- a/arch/arm/plat-omap/include/mach/board-h4.h
+++ b/arch/arm/plat-omap/include/mach/board-h4.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/plat-omap/include/mach/board-h4.h 2 * arch/arm/plat-omap/include/mach/board-h4.h
3 * 3 *
4 * Hardware definitions for TI OMAP1610 H4 board. 4 * Hardware definitions for TI OMAP2420 H4 board.
5 * 5 *
6 * Initial creation by Dirk Behme <dirk.behme@de.bosch.com> 6 * Initial creation by Dirk Behme <dirk.behme@de.bosch.com>
7 * 7 *
@@ -29,6 +29,9 @@
29#ifndef __ASM_ARCH_OMAP_H4_H 29#ifndef __ASM_ARCH_OMAP_H4_H
30#define __ASM_ARCH_OMAP_H4_H 30#define __ASM_ARCH_OMAP_H4_H
31 31
32/* MMC Prototypes */
33extern void h4_mmc_init(void);
34
32/* Placeholder for H4 specific defines */ 35/* Placeholder for H4 specific defines */
33#define OMAP24XX_ETHR_GPIO_IRQ 92 36#define OMAP24XX_ETHR_GPIO_IRQ 92
34#endif /* __ASM_ARCH_OMAP_H4_H */ 37#endif /* __ASM_ARCH_OMAP_H4_H */
diff --git a/arch/arm/plat-omap/include/mach/board.h b/arch/arm/plat-omap/include/mach/board.h
index 54445642f35d..c23c12ccb353 100644
--- a/arch/arm/plat-omap/include/mach/board.h
+++ b/arch/arm/plat-omap/include/mach/board.h
@@ -45,6 +45,8 @@ struct omap_mmc_conf {
45 unsigned cover:1; 45 unsigned cover:1;
46 /* 4 wire signaling is optional, and is only used for SD/SDIO */ 46 /* 4 wire signaling is optional, and is only used for SD/SDIO */
47 unsigned wire4:1; 47 unsigned wire4:1;
48 /* use the internal clock */
49 unsigned internal_clock:1;
48 s16 power_pin; 50 s16 power_pin;
49 s16 switch_pin; 51 s16 switch_pin;
50 s16 wp_pin; 52 s16 wp_pin;
diff --git a/arch/arm/plat-omap/include/mach/common.h b/arch/arm/plat-omap/include/mach/common.h
index 06093112b665..ef70e2b0f054 100644
--- a/arch/arm/plat-omap/include/mach/common.h
+++ b/arch/arm/plat-omap/include/mach/common.h
@@ -34,6 +34,7 @@ struct sys_timer;
34extern void omap_map_common_io(void); 34extern void omap_map_common_io(void);
35extern struct sys_timer omap_timer; 35extern struct sys_timer omap_timer;
36extern void omap_serial_init(void); 36extern void omap_serial_init(void);
37extern void omap_serial_enable_clocks(int enable);
37#ifdef CONFIG_I2C_OMAP 38#ifdef CONFIG_I2C_OMAP
38extern int omap_register_i2c_bus(int bus_id, u32 clkrate, 39extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
39 struct i2c_board_info const *info, 40 struct i2c_board_info const *info,
@@ -49,6 +50,7 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
49 50
50/* IO bases for various OMAP processors */ 51/* IO bases for various OMAP processors */
51struct omap_globals { 52struct omap_globals {
53 u32 class; /* OMAP class to detect */
52 void __iomem *tap; /* Control module ID code */ 54 void __iomem *tap; /* Control module ID code */
53 void __iomem *sdrc; /* SDRAM Controller */ 55 void __iomem *sdrc; /* SDRAM Controller */
54 void __iomem *sms; /* SDRAM Memory Scheduler */ 56 void __iomem *sms; /* SDRAM Memory Scheduler */
@@ -62,6 +64,7 @@ void omap2_set_globals_243x(void);
62void omap2_set_globals_343x(void); 64void omap2_set_globals_343x(void);
63 65
64/* These get called from omap2_set_globals_xxxx(), do not call these */ 66/* These get called from omap2_set_globals_xxxx(), do not call these */
67void omap2_set_globals_tap(struct omap_globals *);
65void omap2_set_globals_memory(struct omap_globals *); 68void omap2_set_globals_memory(struct omap_globals *);
66void omap2_set_globals_control(struct omap_globals *); 69void omap2_set_globals_control(struct omap_globals *);
67void omap2_set_globals_prcm(struct omap_globals *); 70void omap2_set_globals_prcm(struct omap_globals *);
diff --git a/arch/arm/plat-omap/include/mach/control.h b/arch/arm/plat-omap/include/mach/control.h
index ee378d254cbd..dc9886760577 100644
--- a/arch/arm/plat-omap/include/mach/control.h
+++ b/arch/arm/plat-omap/include/mach/control.h
@@ -1,13 +1,10 @@
1#ifndef __ASM_ARCH_CONTROL_H
2#define __ASM_ARCH_CONTROL_H
3
4/* 1/*
5 * arch/arm/plat-omap/include/mach/control.h 2 * arch/arm/plat-omap/include/mach/control.h
6 * 3 *
7 * OMAP2/3 System Control Module definitions 4 * OMAP2/3 System Control Module definitions
8 * 5 *
9 * Copyright (C) 2007 Texas Instruments, Inc. 6 * Copyright (C) 2007-2008 Texas Instruments, Inc.
10 * Copyright (C) 2007 Nokia Corporation 7 * Copyright (C) 2007-2008 Nokia Corporation
11 * 8 *
12 * Written by Paul Walmsley 9 * Written by Paul Walmsley
13 * 10 *
@@ -16,14 +13,23 @@
16 * the Free Software Foundation. 13 * the Free Software Foundation.
17 */ 14 */
18 15
16#ifndef __ASM_ARCH_CONTROL_H
17#define __ASM_ARCH_CONTROL_H
18
19#include <mach/io.h> 19#include <mach/io.h>
20 20
21#ifndef __ASSEMBLY__
21#define OMAP242X_CTRL_REGADDR(reg) \ 22#define OMAP242X_CTRL_REGADDR(reg) \
22 IO_ADDRESS(OMAP242X_CTRL_BASE + (reg)) 23 IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
23#define OMAP243X_CTRL_REGADDR(reg) \ 24#define OMAP243X_CTRL_REGADDR(reg) \
24 IO_ADDRESS(OMAP243X_CTRL_BASE + (reg)) 25 IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
25#define OMAP343X_CTRL_REGADDR(reg) \ 26#define OMAP343X_CTRL_REGADDR(reg) \
26 IO_ADDRESS(OMAP343X_CTRL_BASE + (reg)) 27 IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
28#else
29#define OMAP242X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
30#define OMAP243X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
31#define OMAP343X_CTRL_REGADDR(reg) IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
32#endif /* __ASSEMBLY__ */
27 33
28/* 34/*
29 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for 35 * As elsewhere, the "OMAP2_" prefix indicates that the macro is valid for
@@ -134,6 +140,7 @@
134#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc) 140#define OMAP343X_CONTROL_TEST_KEY_13 (OMAP2_CONTROL_GENERAL + 0x00fc)
135#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190) 141#define OMAP343X_CONTROL_IVA2_BOOTADDR (OMAP2_CONTROL_GENERAL + 0x0190)
136#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194) 142#define OMAP343X_CONTROL_IVA2_BOOTMOD (OMAP2_CONTROL_GENERAL + 0x0194)
143#define OMAP343X_CONTROL_TEMP_SENSOR (OMAP2_CONTROL_GENERAL + 0x02b4)
137 144
138/* 145/*
139 * REVISIT: This list of registers is not comprehensive - there are more 146 * REVISIT: This list of registers is not comprehensive - there are more
diff --git a/arch/arm/plat-omap/include/mach/cpu.h b/arch/arm/plat-omap/include/mach/cpu.h
index 05aee0eda34f..e0464187209d 100644
--- a/arch/arm/plat-omap/include/mach/cpu.h
+++ b/arch/arm/plat-omap/include/mach/cpu.h
@@ -346,9 +346,14 @@ IS_OMAP_TYPE(3430, 0x3430)
346 get_sil_revision(system_rev) 346 get_sil_revision(system_rev)
347 347
348/* Various silicon macros defined here */ 348/* Various silicon macros defined here */
349#define OMAP242X_CLASS 0x24200000
349#define OMAP2420_REV_ES1_0 0x24200000 350#define OMAP2420_REV_ES1_0 0x24200000
350#define OMAP2420_REV_ES2_0 0x24201000 351#define OMAP2420_REV_ES2_0 0x24201000
352
353#define OMAP243X_CLASS 0x24300000
351#define OMAP2430_REV_ES1_0 0x24300000 354#define OMAP2430_REV_ES1_0 0x24300000
355
356#define OMAP343X_CLASS 0x34300000
352#define OMAP3430_REV_ES1_0 0x34300000 357#define OMAP3430_REV_ES1_0 0x34300000
353#define OMAP3430_REV_ES2_0 0x34301000 358#define OMAP3430_REV_ES2_0 0x34301000
354#define OMAP3430_REV_ES2_1 0x34302000 359#define OMAP3430_REV_ES2_1 0x34302000
diff --git a/arch/arm/plat-omap/include/mach/gpio.h b/arch/arm/plat-omap/include/mach/gpio.h
index 4cb818da672c..5bb7460cabc4 100644
--- a/arch/arm/plat-omap/include/mach/gpio.h
+++ b/arch/arm/plat-omap/include/mach/gpio.h
@@ -76,6 +76,8 @@ extern void omap_free_gpio(int gpio);
76extern void omap_set_gpio_direction(int gpio, int is_input); 76extern void omap_set_gpio_direction(int gpio, int is_input);
77extern void omap_set_gpio_dataout(int gpio, int enable); 77extern void omap_set_gpio_dataout(int gpio, int enable);
78extern int omap_get_gpio_datain(int gpio); 78extern int omap_get_gpio_datain(int gpio);
79extern void omap2_gpio_prepare_for_retention(void);
80extern void omap2_gpio_resume_after_retention(void);
79extern void omap_set_gpio_debounce(int gpio, int enable); 81extern void omap_set_gpio_debounce(int gpio, int enable);
80extern void omap_set_gpio_debounce_time(int gpio, int enable); 82extern void omap_set_gpio_debounce_time(int gpio, int enable);
81 83
diff --git a/arch/arm/plat-omap/include/mach/gpmc.h b/arch/arm/plat-omap/include/mach/gpmc.h
index 6a8e07ffc2d0..3c7b425c585e 100644
--- a/arch/arm/plat-omap/include/mach/gpmc.h
+++ b/arch/arm/plat-omap/include/mach/gpmc.h
@@ -11,6 +11,9 @@
11#ifndef __OMAP2_GPMC_H 11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H 12#define __OMAP2_GPMC_H
13 13
14/* Maximum Number of Chip Selects */
15#define GPMC_CS_NUM 8
16
14#define GPMC_CS_CONFIG1 0x00 17#define GPMC_CS_CONFIG1 0x00
15#define GPMC_CS_CONFIG2 0x04 18#define GPMC_CS_CONFIG2 0x04
16#define GPMC_CS_CONFIG3 0x08 19#define GPMC_CS_CONFIG3 0x08
@@ -22,6 +25,9 @@
22#define GPMC_CS_NAND_ADDRESS 0x20 25#define GPMC_CS_NAND_ADDRESS 0x20
23#define GPMC_CS_NAND_DATA 0x24 26#define GPMC_CS_NAND_DATA 0x24
24 27
28#define GPMC_CONFIG 0x50
29#define GPMC_STATUS 0x54
30
25#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) 31#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
26#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) 32#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
27#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) 33#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
@@ -81,6 +87,7 @@ struct gpmc_timings {
81}; 87};
82 88
83extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); 89extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns);
90extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
84extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); 91extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns);
85extern unsigned long gpmc_get_fclk_period(void); 92extern unsigned long gpmc_get_fclk_period(void);
86 93
@@ -92,5 +99,6 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
92extern void gpmc_cs_free(int cs); 99extern void gpmc_cs_free(int cs);
93extern int gpmc_cs_set_reserved(int cs, int reserved); 100extern int gpmc_cs_set_reserved(int cs, int reserved);
94extern int gpmc_cs_reserved(int cs); 101extern int gpmc_cs_reserved(int cs);
102extern void gpmc_init(void);
95 103
96#endif 104#endif
diff --git a/arch/arm/plat-omap/include/mach/hardware.h b/arch/arm/plat-omap/include/mach/hardware.h
index abb01e471c4c..29c849f5f18e 100644
--- a/arch/arm/plat-omap/include/mach/hardware.h
+++ b/arch/arm/plat-omap/include/mach/hardware.h
@@ -282,8 +282,8 @@
282 282
283#include "omap730.h" 283#include "omap730.h"
284#include "omap1510.h" 284#include "omap1510.h"
285#include "omap24xx.h"
286#include "omap16xx.h" 285#include "omap16xx.h"
286#include "omap24xx.h"
287#include "omap34xx.h" 287#include "omap34xx.h"
288 288
289#ifndef __ASSEMBLER__ 289#ifndef __ASSEMBLER__
diff --git a/arch/arm/plat-omap/include/mach/irqs.h b/arch/arm/plat-omap/include/mach/irqs.h
index 17248bbf3f27..e9fd63055cb2 100644
--- a/arch/arm/plat-omap/include/mach/irqs.h
+++ b/arch/arm/plat-omap/include/mach/irqs.h
@@ -125,6 +125,7 @@
125#define INT_UART2 (15 + IH2_BASE) 125#define INT_UART2 (15 + IH2_BASE)
126#define INT_BT_MCSI1TX (16 + IH2_BASE) 126#define INT_BT_MCSI1TX (16 + IH2_BASE)
127#define INT_BT_MCSI1RX (17 + IH2_BASE) 127#define INT_BT_MCSI1RX (17 + IH2_BASE)
128#define INT_SOSSI_MATCH (19 + IH2_BASE)
128#define INT_USB_W2FC (20 + IH2_BASE) 129#define INT_USB_W2FC (20 + IH2_BASE)
129#define INT_1WIRE (21 + IH2_BASE) 130#define INT_1WIRE (21 + IH2_BASE)
130#define INT_OS_TIMER (22 + IH2_BASE) 131#define INT_OS_TIMER (22 + IH2_BASE)
@@ -176,6 +177,7 @@
176#define INT_1610_DMA_CH14 (61 + IH2_BASE) 177#define INT_1610_DMA_CH14 (61 + IH2_BASE)
177#define INT_1610_DMA_CH15 (62 + IH2_BASE) 178#define INT_1610_DMA_CH15 (62 + IH2_BASE)
178#define INT_1610_NAND (63 + IH2_BASE) 179#define INT_1610_NAND (63 + IH2_BASE)
180#define INT_1610_SHA1MD5 (91 + IH2_BASE)
179 181
180/* 182/*
181 * OMAP-730 specific IRQ numbers for interrupt handler 2 183 * OMAP-730 specific IRQ numbers for interrupt handler 2
@@ -263,12 +265,16 @@
263#define INT_24XX_GPTIMER10 46 265#define INT_24XX_GPTIMER10 46
264#define INT_24XX_GPTIMER11 47 266#define INT_24XX_GPTIMER11 47
265#define INT_24XX_GPTIMER12 48 267#define INT_24XX_GPTIMER12 48
268#define INT_24XX_SHA1MD5 51
266#define INT_24XX_I2C1_IRQ 56 269#define INT_24XX_I2C1_IRQ 56
267#define INT_24XX_I2C2_IRQ 57 270#define INT_24XX_I2C2_IRQ 57
271#define INT_24XX_HDQ_IRQ 58
268#define INT_24XX_MCBSP1_IRQ_TX 59 272#define INT_24XX_MCBSP1_IRQ_TX 59
269#define INT_24XX_MCBSP1_IRQ_RX 60 273#define INT_24XX_MCBSP1_IRQ_RX 60
270#define INT_24XX_MCBSP2_IRQ_TX 62 274#define INT_24XX_MCBSP2_IRQ_TX 62
271#define INT_24XX_MCBSP2_IRQ_RX 63 275#define INT_24XX_MCBSP2_IRQ_RX 63
276#define INT_24XX_SPI1_IRQ 65
277#define INT_24XX_SPI2_IRQ 66
272#define INT_24XX_UART1_IRQ 72 278#define INT_24XX_UART1_IRQ 72
273#define INT_24XX_UART2_IRQ 73 279#define INT_24XX_UART2_IRQ 73
274#define INT_24XX_UART3_IRQ 74 280#define INT_24XX_UART3_IRQ 74
diff --git a/arch/arm/plat-omap/include/mach/mux.h b/arch/arm/plat-omap/include/mach/mux.h
index 614b2c1327c7..5670d563f378 100644
--- a/arch/arm/plat-omap/include/mach/mux.h
+++ b/arch/arm/plat-omap/include/mach/mux.h
@@ -125,20 +125,64 @@
125 .pu_pd_val = pull_mode, \ 125 .pu_pd_val = pull_mode, \
126}, 126},
127 127
128 128/* 24xx/34xx mux bit defines */
129#define PULL_DISABLED 0 129#define OMAP2_PULL_ENA (1 << 3)
130#define PULL_ENABLED 1 130#define OMAP2_PULL_UP (1 << 4)
131 131#define OMAP2_ALTELECTRICALSEL (1 << 5)
132#define PULL_DOWN 0 132
133#define PULL_UP 1 133/* 34xx specific mux bit defines */
134#define OMAP3_INPUT_EN (1 << 8)
135#define OMAP3_OFF_EN (1 << 9)
136#define OMAP3_OFFOUT_EN (1 << 10)
137#define OMAP3_OFFOUT_VAL (1 << 11)
138#define OMAP3_OFF_PULL_EN (1 << 12)
139#define OMAP3_OFF_PULL_UP (1 << 13)
140#define OMAP3_WAKEUP_EN (1 << 14)
141
142/* 34xx mux mode options for each pin. See TRM for options */
143#define OMAP34XX_MUX_MODE0 0
144#define OMAP34XX_MUX_MODE1 1
145#define OMAP34XX_MUX_MODE2 2
146#define OMAP34XX_MUX_MODE3 3
147#define OMAP34XX_MUX_MODE4 4
148#define OMAP34XX_MUX_MODE5 5
149#define OMAP34XX_MUX_MODE6 6
150#define OMAP34XX_MUX_MODE7 7
151
152/* 34xx active pin states */
153#define OMAP34XX_PIN_OUTPUT 0
154#define OMAP34XX_PIN_INPUT OMAP3_INPUT_EN
155#define OMAP34XX_PIN_INPUT_PULLUP (OMAP2_PULL_ENA | OMAP3_INPUT_EN \
156 | OMAP2_PULL_UP)
157#define OMAP34XX_PIN_INPUT_PULLDOWN (OMAP2_PULL_ENA | OMAP3_INPUT_EN)
158
159/* 34xx off mode states */
160#define OMAP34XX_PIN_OFF_NONE 0
161#define OMAP34XX_PIN_OFF_OUTPUT_HIGH (OMAP3_OFF_EN | OMAP3_OFFOUT_EN \
162 | OMAP3_OFFOUT_VAL)
163#define OMAP34XX_PIN_OFF_OUTPUT_LOW (OMAP3_OFF_EN | OMAP3_OFFOUT_EN)
164#define OMAP34XX_PIN_OFF_INPUT_PULLUP (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN \
165 | OMAP3_OFF_PULL_UP)
166#define OMAP34XX_PIN_OFF_INPUT_PULLDOWN (OMAP3_OFF_EN | OMAP3_OFF_PULL_EN)
167#define OMAP34XX_PIN_OFF_WAKEUPENABLE OMAP3_WAKEUP_EN
168
169#define MUX_CFG_34XX(desc, reg_offset, mux_value) { \
170 .name = desc, \
171 .debug = 0, \
172 .mux_reg = reg_offset, \
173 .mux_val = mux_value \
174},
134 175
135struct pin_config { 176struct pin_config {
136 char *name; 177 char *name;
137 unsigned char busy; 178 const unsigned int mux_reg;
138 unsigned char debug; 179 unsigned char debug;
139 180
140 const char *mux_reg_name; 181#if defined(CONFIG_ARCH_OMAP34XX)
141 const unsigned int mux_reg; 182 u16 mux_val; /* Wake-up, off mode, pull, mux mode */
183#endif
184
185#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
142 const unsigned char mask_offset; 186 const unsigned char mask_offset;
143 const unsigned char mask; 187 const unsigned char mask;
144 188
@@ -150,6 +194,12 @@ struct pin_config {
150 const char *pu_pd_name; 194 const char *pu_pd_name;
151 const unsigned int pu_pd_reg; 195 const unsigned int pu_pd_reg;
152 const unsigned char pu_pd_val; 196 const unsigned char pu_pd_val;
197#endif
198
199#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
200 const char *mux_reg_name;
201#endif
202
153}; 203};
154 204
155enum omap730_index { 205enum omap730_index {
@@ -593,6 +643,90 @@ enum omap24xx_index {
593 643
594}; 644};
595 645
646enum omap34xx_index {
647 /* 34xx I2C */
648 K21_34XX_I2C1_SCL,
649 J21_34XX_I2C1_SDA,
650 AF15_34XX_I2C2_SCL,
651 AE15_34XX_I2C2_SDA,
652 AF14_34XX_I2C3_SCL,
653 AG14_34XX_I2C3_SDA,
654 AD26_34XX_I2C4_SCL,
655 AE26_34XX_I2C4_SDA,
656
657 /* PHY - HSUSB: 12-pin ULPI PHY: Port 1*/
658 Y8_3430_USB1HS_PHY_CLK,
659 Y9_3430_USB1HS_PHY_STP,
660 AA14_3430_USB1HS_PHY_DIR,
661 AA11_3430_USB1HS_PHY_NXT,
662 W13_3430_USB1HS_PHY_DATA0,
663 W12_3430_USB1HS_PHY_DATA1,
664 W11_3430_USB1HS_PHY_DATA2,
665 Y11_3430_USB1HS_PHY_DATA3,
666 W9_3430_USB1HS_PHY_DATA4,
667 Y12_3430_USB1HS_PHY_DATA5,
668 W8_3430_USB1HS_PHY_DATA6,
669 Y13_3430_USB1HS_PHY_DATA7,
670
671 /* PHY - HSUSB: 12-pin ULPI PHY: Port 2*/
672 AA8_3430_USB2HS_PHY_CLK,
673 AA10_3430_USB2HS_PHY_STP,
674 AA9_3430_USB2HS_PHY_DIR,
675 AB11_3430_USB2HS_PHY_NXT,
676 AB10_3430_USB2HS_PHY_DATA0,
677 AB9_3430_USB2HS_PHY_DATA1,
678 W3_3430_USB2HS_PHY_DATA2,
679 T4_3430_USB2HS_PHY_DATA3,
680 T3_3430_USB2HS_PHY_DATA4,
681 R3_3430_USB2HS_PHY_DATA5,
682 R4_3430_USB2HS_PHY_DATA6,
683 T2_3430_USB2HS_PHY_DATA7,
684
685
686 /* TLL - HSUSB: 12-pin TLL Port 1*/
687 Y8_3430_USB1HS_TLL_CLK,
688 Y9_3430_USB1HS_TLL_STP,
689 AA14_3430_USB1HS_TLL_DIR,
690 AA11_3430_USB1HS_TLL_NXT,
691 W13_3430_USB1HS_TLL_DATA0,
692 W12_3430_USB1HS_TLL_DATA1,
693 W11_3430_USB1HS_TLL_DATA2,
694 Y11_3430_USB1HS_TLL_DATA3,
695 W9_3430_USB1HS_TLL_DATA4,
696 Y12_3430_USB1HS_TLL_DATA5,
697 W8_3430_USB1HS_TLL_DATA6,
698 Y13_3430_USB1HS_TLL_DATA7,
699
700 /* TLL - HSUSB: 12-pin TLL Port 2*/
701 AA8_3430_USB2HS_TLL_CLK,
702 AA10_3430_USB2HS_TLL_STP,
703 AA9_3430_USB2HS_TLL_DIR,
704 AB11_3430_USB2HS_TLL_NXT,
705 AB10_3430_USB2HS_TLL_DATA0,
706 AB9_3430_USB2HS_TLL_DATA1,
707 W3_3430_USB2HS_TLL_DATA2,
708 T4_3430_USB2HS_TLL_DATA3,
709 T3_3430_USB2HS_TLL_DATA4,
710 R3_3430_USB2HS_TLL_DATA5,
711 R4_3430_USB2HS_TLL_DATA6,
712 T2_3430_USB2HS_TLL_DATA7,
713
714 /* TLL - HSUSB: 12-pin TLL Port 3*/
715 AA6_3430_USB3HS_TLL_CLK,
716 AB3_3430_USB3HS_TLL_STP,
717 AA3_3430_USB3HS_TLL_DIR,
718 Y3_3430_USB3HS_TLL_NXT,
719 AA5_3430_USB3HS_TLL_DATA0,
720 Y4_3430_USB3HS_TLL_DATA1,
721 Y5_3430_USB3HS_TLL_DATA2,
722 W5_3430_USB3HS_TLL_DATA3,
723 AB12_3430_USB3HS_TLL_DATA4,
724 AB13_3430_USB3HS_TLL_DATA5,
725 AA13_3430_USB3HS_TLL_DATA6,
726 AA12_3430_USB3HS_TLL_DATA7
727
728};
729
596struct omap_mux_cfg { 730struct omap_mux_cfg {
597 struct pin_config *pins; 731 struct pin_config *pins;
598 unsigned long size; 732 unsigned long size;
diff --git a/arch/arm/plat-omap/include/mach/omap1510.h b/arch/arm/plat-omap/include/mach/omap1510.h
index 505a38af8b22..d24004668138 100644
--- a/arch/arm/plat-omap/include/mach/omap1510.h
+++ b/arch/arm/plat-omap/include/mach/omap1510.h
@@ -44,5 +44,7 @@
44#define OMAP1510_DSPREG_SIZE SZ_128K 44#define OMAP1510_DSPREG_SIZE SZ_128K
45#define OMAP1510_DSPREG_START 0xE1000000 45#define OMAP1510_DSPREG_START 0xE1000000
46 46
47#define OMAP1510_DSP_MMU_BASE (0xfffed200)
48
47#endif /* __ASM_ARCH_OMAP15XX_H */ 49#endif /* __ASM_ARCH_OMAP15XX_H */
48 50
diff --git a/arch/arm/plat-omap/include/mach/omap16xx.h b/arch/arm/plat-omap/include/mach/omap16xx.h
index c6c93afb2788..0e69b504c25f 100644
--- a/arch/arm/plat-omap/include/mach/omap16xx.h
+++ b/arch/arm/plat-omap/include/mach/omap16xx.h
@@ -44,6 +44,11 @@
44#define OMAP16XX_DSPREG_SIZE SZ_128K 44#define OMAP16XX_DSPREG_SIZE SZ_128K
45#define OMAP16XX_DSPREG_START 0xE1000000 45#define OMAP16XX_DSPREG_START 0xE1000000
46 46
47#define OMAP16XX_SEC_BASE 0xFFFE4000
48#define OMAP16XX_SEC_DES (OMAP16XX_SEC_BASE + 0x0000)
49#define OMAP16XX_SEC_SHA1MD5 (OMAP16XX_SEC_BASE + 0x0800)
50#define OMAP16XX_SEC_RNG (OMAP16XX_SEC_BASE + 0x1000)
51
47/* 52/*
48 * --------------------------------------------------------------------------- 53 * ---------------------------------------------------------------------------
49 * Interrupts 54 * Interrupts
@@ -190,7 +195,7 @@
190#define WSPR_DISABLE_0 (0x0000aaaa) 195#define WSPR_DISABLE_0 (0x0000aaaa)
191#define WSPR_DISABLE_1 (0x00005555) 196#define WSPR_DISABLE_1 (0x00005555)
192 197
193/* Mailbox */ 198#define OMAP16XX_DSP_MMU_BASE (0xfffed200)
194#define OMAP16XX_MAILBOX_BASE (0xfffcf000) 199#define OMAP16XX_MAILBOX_BASE (0xfffcf000)
195 200
196#endif /* __ASM_ARCH_OMAP16XX_H */ 201#endif /* __ASM_ARCH_OMAP16XX_H */
diff --git a/arch/arm/plat-omap/include/mach/omap24xx.h b/arch/arm/plat-omap/include/mach/omap24xx.h
index bb8319d66e9f..556f0eb4d55c 100644
--- a/arch/arm/plat-omap/include/mach/omap24xx.h
+++ b/arch/arm/plat-omap/include/mach/omap24xx.h
@@ -48,6 +48,7 @@
48#define OMAP2420_PRM_BASE OMAP2420_CM_BASE 48#define OMAP2420_PRM_BASE OMAP2420_CM_BASE
49#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000) 49#define OMAP2420_SDRC_BASE (L3_24XX_BASE + 0x9000)
50#define OMAP2420_SMS_BASE 0x68008000 50#define OMAP2420_SMS_BASE 0x68008000
51#define OMAP2420_GPMC_BASE 0x6800a000
51 52
52#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000) 53#define OMAP2430_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000)
53#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000) 54#define OMAP2430_PRCM_BASE (L4_WK_243X_BASE + 0x6000)
diff --git a/arch/arm/plat-omap/include/mach/omapfb.h b/arch/arm/plat-omap/include/mach/omapfb.h
index cae037d13079..ec67fb428607 100644
--- a/arch/arm/plat-omap/include/mach/omapfb.h
+++ b/arch/arm/plat-omap/include/mach/omapfb.h
@@ -62,6 +62,7 @@
62#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000 62#define OMAPFB_CAPS_WINDOW_PIXEL_DOUBLE 0x00010000
63#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000 63#define OMAPFB_CAPS_WINDOW_SCALE 0x00020000
64#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000 64#define OMAPFB_CAPS_WINDOW_OVERLAY 0x00040000
65#define OMAPFB_CAPS_WINDOW_ROTATE 0x00080000
65#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000 66#define OMAPFB_CAPS_SET_BACKLIGHT 0x01000000
66 67
67/* Values from DSP must map to lower 16-bits */ 68/* Values from DSP must map to lower 16-bits */
@@ -305,6 +306,7 @@ struct lcd_ctrl {
305 int screen_width, 306 int screen_width,
306 int pos_x, int pos_y, int width, 307 int pos_x, int pos_y, int width,
307 int height, int color_mode); 308 int height, int color_mode);
309 int (*set_rotate) (int angle);
308 int (*setup_mem) (int plane, size_t size, 310 int (*setup_mem) (int plane, size_t size,
309 int mem_type, unsigned long *paddr); 311 int mem_type, unsigned long *paddr);
310 int (*mmap) (struct fb_info *info, 312 int (*mmap) (struct fb_info *info,
@@ -374,6 +376,7 @@ extern struct lcd_ctrl omap1_lcd_ctrl;
374extern struct lcd_ctrl omap2_disp_ctrl; 376extern struct lcd_ctrl omap2_disp_ctrl;
375#endif 377#endif
376 378
379extern void omapfb_reserve_sdram(void);
377extern void omapfb_register_panel(struct lcd_panel *panel); 380extern void omapfb_register_panel(struct lcd_panel *panel);
378extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval); 381extern void omapfb_write_first_pixel(struct omapfb_device *fbdev, u16 pixval);
379extern void omapfb_notify_clients(struct omapfb_device *fbdev, 382extern void omapfb_notify_clients(struct omapfb_device *fbdev,
diff --git a/arch/arm/plat-omap/include/mach/pm.h b/arch/arm/plat-omap/include/mach/pm.h
index 6063e9681de2..768eb6e7abcf 100644
--- a/arch/arm/plat-omap/include/mach/pm.h
+++ b/arch/arm/plat-omap/include/mach/pm.h
@@ -135,7 +135,8 @@ extern void omap_pm_suspend(void);
135extern void omap730_cpu_suspend(unsigned short, unsigned short); 135extern void omap730_cpu_suspend(unsigned short, unsigned short);
136extern void omap1510_cpu_suspend(unsigned short, unsigned short); 136extern void omap1510_cpu_suspend(unsigned short, unsigned short);
137extern void omap1610_cpu_suspend(unsigned short, unsigned short); 137extern void omap1610_cpu_suspend(unsigned short, unsigned short);
138extern void omap24xx_cpu_suspend(u32 dll_ctrl, u32 cpu_revision); 138extern void omap24xx_cpu_suspend(u32 dll_ctrl, void __iomem *sdrc_dlla_ctrl,
139 void __iomem *sdrc_power);
139extern void omap730_idle_loop_suspend(void); 140extern void omap730_idle_loop_suspend(void);
140extern void omap1510_idle_loop_suspend(void); 141extern void omap1510_idle_loop_suspend(void);
141extern void omap1610_idle_loop_suspend(void); 142extern void omap1610_idle_loop_suspend(void);
diff --git a/arch/arm/plat-omap/include/mach/sdrc.h b/arch/arm/plat-omap/include/mach/sdrc.h
index d908eb527c8d..25ee3819faad 100644
--- a/arch/arm/plat-omap/include/mach/sdrc.h
+++ b/arch/arm/plat-omap/include/mach/sdrc.h
@@ -25,6 +25,8 @@
25#define SDRC_DLLB_STATUS 0x06C 25#define SDRC_DLLB_STATUS 0x06C
26#define SDRC_POWER 0x070 26#define SDRC_POWER 0x070
27#define SDRC_MR_0 0x084 27#define SDRC_MR_0 0x084
28#define SDRC_ACTIM_CTRL_A 0x09c
29#define SDRC_ACTIM_CTRL_B 0x0a0
28#define SDRC_RFR_CTRL_0 0x0a4 30#define SDRC_RFR_CTRL_0 0x0a4
29 31
30/* 32/*
diff --git a/arch/arm/plat-omap/include/mach/serial.h b/arch/arm/plat-omap/include/mach/serial.h
index 515b89bee966..8a676a04be48 100644
--- a/arch/arm/plat-omap/include/mach/serial.h
+++ b/arch/arm/plat-omap/include/mach/serial.h
@@ -20,11 +20,17 @@
20#define OMAP_UART1_BASE 0x4806a000 20#define OMAP_UART1_BASE 0x4806a000
21#define OMAP_UART2_BASE 0x4806c000 21#define OMAP_UART2_BASE 0x4806c000
22#define OMAP_UART3_BASE 0x4806e000 22#define OMAP_UART3_BASE 0x4806e000
23#elif defined(CONFIG_ARCH_OMAP3)
24/* OMAP3 serial ports */
25#define OMAP_UART1_BASE 0x4806a000
26#define OMAP_UART2_BASE 0x4806c000
27#define OMAP_UART3_BASE 0x49020000
23#endif 28#endif
24 29
25#define OMAP_MAX_NR_PORTS 3 30#define OMAP_MAX_NR_PORTS 3
26#define OMAP1510_BASE_BAUD (12000000/16) 31#define OMAP1510_BASE_BAUD (12000000/16)
27#define OMAP16XX_BASE_BAUD (48000000/16) 32#define OMAP16XX_BASE_BAUD (48000000/16)
33#define OMAP24XX_BASE_BAUD (48000000/16)
28 34
29#define is_omap_port(pt) ({int __ret = 0; \ 35#define is_omap_port(pt) ({int __ret = 0; \
30 if ((pt)->port.mapbase == OMAP_UART1_BASE || \ 36 if ((pt)->port.mapbase == OMAP_UART1_BASE || \
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 07:36:46 -0500