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-rw-r--r--drivers/gpu/drm/nouveau/nv40_graph.c20
1 files changed, 12 insertions, 8 deletions
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index d3e0a2a6acf8..7e8547cb5833 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -252,8 +252,9 @@ nv40_grctx_init(struct drm_device *dev)
252 memcpy(pgraph->ctxprog, fw->data, fw->size); 252 memcpy(pgraph->ctxprog, fw->data, fw->size);
253 253
254 cp = pgraph->ctxprog; 254 cp = pgraph->ctxprog;
255 if (cp->signature != 0x5043564e || cp->version != 0 || 255 if (le32_to_cpu(cp->signature) != 0x5043564e ||
256 cp->length != ((fw->size - 7) / 4)) { 256 cp->version != 0 ||
257 le16_to_cpu(cp->length) != ((fw->size - 7) / 4)) {
257 NV_ERROR(dev, "ctxprog invalid\n"); 258 NV_ERROR(dev, "ctxprog invalid\n");
258 release_firmware(fw); 259 release_firmware(fw);
259 nv40_grctx_fini(dev); 260 nv40_grctx_fini(dev);
@@ -281,8 +282,9 @@ nv40_grctx_init(struct drm_device *dev)
281 memcpy(pgraph->ctxvals, fw->data, fw->size); 282 memcpy(pgraph->ctxvals, fw->data, fw->size);
282 283
283 cv = (void *)pgraph->ctxvals; 284 cv = (void *)pgraph->ctxvals;
284 if (cv->signature != 0x5643564e || cv->version != 0 || 285 if (le32_to_cpu(cv->signature) != 0x5643564e ||
285 cv->length != ((fw->size - 9) / 8)) { 286 cv->version != 0 ||
287 le32_to_cpu(cv->length) != ((fw->size - 9) / 8)) {
286 NV_ERROR(dev, "ctxvals invalid\n"); 288 NV_ERROR(dev, "ctxvals invalid\n");
287 release_firmware(fw); 289 release_firmware(fw);
288 nv40_grctx_fini(dev); 290 nv40_grctx_fini(dev);
@@ -294,8 +296,9 @@ nv40_grctx_init(struct drm_device *dev)
294 cp = pgraph->ctxprog; 296 cp = pgraph->ctxprog;
295 297
296 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0); 298 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
297 for (i = 0; i < cp->length; i++) 299 for (i = 0; i < le16_to_cpu(cp->length); i++)
298 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp->data[i]); 300 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA,
301 le32_to_cpu(cp->data[i]));
299 302
300 pgraph->accel_blocked = false; 303 pgraph->accel_blocked = false;
301 return 0; 304 return 0;
@@ -329,8 +332,9 @@ nv40_grctx_vals_load(struct drm_device *dev, struct nouveau_gpuobj *ctx)
329 if (!cv) 332 if (!cv)
330 return; 333 return;
331 334
332 for (i = 0; i < cv->length; i++) 335 for (i = 0; i < le32_to_cpu(cv->length); i++)
333 nv_wo32(dev, ctx, cv->data[i].offset, cv->data[i].value); 336 nv_wo32(dev, ctx, le32_to_cpu(cv->data[i].offset),
337 le32_to_cpu(cv->data[i].value));
334} 338}
335 339
336/* 340/*