diff options
-rw-r--r-- | drivers/media/dvb/frontends/stv090x.c | 24 | ||||
-rw-r--r-- | drivers/media/dvb/frontends/stv090x_reg.h | 69 |
2 files changed, 64 insertions, 29 deletions
diff --git a/drivers/media/dvb/frontends/stv090x.c b/drivers/media/dvb/frontends/stv090x.c index e80d163c767f..b450bf12db44 100644 --- a/drivers/media/dvb/frontends/stv090x.c +++ b/drivers/media/dvb/frontends/stv090x.c | |||
@@ -176,8 +176,10 @@ static const struct stv090x_tab stv090x_rf_tab[] = { | |||
176 | static struct stv090x_reg stv0900_initval[] = { | 176 | static struct stv090x_reg stv0900_initval[] = { |
177 | 177 | ||
178 | { STV090x_OUTCFG, 0x00 }, | 178 | { STV090x_OUTCFG, 0x00 }, |
179 | { STV090x_MODECFG, 0xff }, | ||
179 | { STV090x_AGCRF1CFG, 0x11 }, | 180 | { STV090x_AGCRF1CFG, 0x11 }, |
180 | { STV090x_AGCRF2CFG, 0x13 }, | 181 | { STV090x_AGCRF2CFG, 0x13 }, |
182 | { STV090x_TSGENERAL1X, 0x14 }, | ||
181 | { STV090x_TSTTNR2, 0x21 }, | 183 | { STV090x_TSTTNR2, 0x21 }, |
182 | { STV090x_TSTTNR4, 0x21 }, | 184 | { STV090x_TSTTNR4, 0x21 }, |
183 | { STV090x_P2_DISTXCTL, 0x22 }, | 185 | { STV090x_P2_DISTXCTL, 0x22 }, |
@@ -203,8 +205,10 @@ static struct stv090x_reg stv0900_initval[] = { | |||
203 | { STV090x_P2_ERRCTRL2, 0xc1 }, | 205 | { STV090x_P2_ERRCTRL2, 0xc1 }, |
204 | { STV090x_P2_CFRICFG, 0xf8 }, | 206 | { STV090x_P2_CFRICFG, 0xf8 }, |
205 | { STV090x_P2_NOSCFG, 0x1c }, | 207 | { STV090x_P2_NOSCFG, 0x1c }, |
208 | { STV090x_P2_DMDTOM, 0x20 }, | ||
206 | { STV090x_P2_CORRELMANT, 0x70 }, | 209 | { STV090x_P2_CORRELMANT, 0x70 }, |
207 | { STV090x_P2_CORRELABS, 0x88 }, | 210 | { STV090x_P2_CORRELABS, 0x88 }, |
211 | { STV090x_P2_AGC2O, 0x5b }, | ||
208 | { STV090x_P2_AGC2REF, 0x38 }, | 212 | { STV090x_P2_AGC2REF, 0x38 }, |
209 | { STV090x_P2_CARCFG, 0xe4 }, | 213 | { STV090x_P2_CARCFG, 0xe4 }, |
210 | { STV090x_P2_ACLC, 0x1A }, | 214 | { STV090x_P2_ACLC, 0x1A }, |
@@ -246,6 +250,7 @@ static struct stv090x_reg stv0900_initval[] = { | |||
246 | { STV090x_P1_DMDCFGMD, 0xf9 }, | 250 | { STV090x_P1_DMDCFGMD, 0xf9 }, |
247 | { STV090x_P1_DEMOD, 0x08 }, | 251 | { STV090x_P1_DEMOD, 0x08 }, |
248 | { STV090x_P1_DMDCFG3, 0xc4 }, | 252 | { STV090x_P1_DMDCFG3, 0xc4 }, |
253 | { STV090x_P1_DMDTOM, 0x20 }, | ||
249 | { STV090x_P1_CARFREQ, 0xed }, | 254 | { STV090x_P1_CARFREQ, 0xed }, |
250 | { STV090x_P1_LDT, 0xd0 }, | 255 | { STV090x_P1_LDT, 0xd0 }, |
251 | { STV090x_P1_LDT2, 0xb8 }, | 256 | { STV090x_P1_LDT2, 0xb8 }, |
@@ -265,6 +270,7 @@ static struct stv090x_reg stv0900_initval[] = { | |||
265 | { STV090x_P1_NOSCFG, 0x1c }, | 270 | { STV090x_P1_NOSCFG, 0x1c }, |
266 | { STV090x_P1_CORRELMANT, 0x70 }, | 271 | { STV090x_P1_CORRELMANT, 0x70 }, |
267 | { STV090x_P1_CORRELABS, 0x88 }, | 272 | { STV090x_P1_CORRELABS, 0x88 }, |
273 | { STV090x_P1_AGC2O, 0x5b }, | ||
268 | { STV090x_P1_AGC2REF, 0x38 }, | 274 | { STV090x_P1_AGC2REF, 0x38 }, |
269 | { STV090x_P1_CARCFG, 0xe4 }, | 275 | { STV090x_P1_CARCFG, 0xe4 }, |
270 | { STV090x_P1_ACLC, 0x1A }, | 276 | { STV090x_P1_ACLC, 0x1A }, |
@@ -326,6 +332,7 @@ static struct stv090x_reg stv0900_initval[] = { | |||
326 | { STV090x_GAINLLR_NF15, 0x1A }, | 332 | { STV090x_GAINLLR_NF15, 0x1A }, |
327 | { STV090x_GAINLLR_NF16, 0x1F }, | 333 | { STV090x_GAINLLR_NF16, 0x1F }, |
328 | { STV090x_GAINLLR_NF17, 0x21 }, | 334 | { STV090x_GAINLLR_NF17, 0x21 }, |
335 | { STV090x_RCCFGH, 0x20 }, | ||
329 | { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */ | 336 | { STV090x_P1_FECM, 0x01 }, /* disable DSS modes */ |
330 | { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */ | 337 | { STV090x_P2_FECM, 0x01 }, /* disable DSS modes */ |
331 | { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */ | 338 | { STV090x_P1_PRVIT, 0x2F }, /* disable PR 6/7 */ |
@@ -364,12 +371,14 @@ static struct stv090x_reg stv0903_initval[] = { | |||
364 | { STV090x_P1_ERRCTRL2, 0xc1 }, | 371 | { STV090x_P1_ERRCTRL2, 0xc1 }, |
365 | { STV090x_P1_CFRICFG, 0xf8 }, | 372 | { STV090x_P1_CFRICFG, 0xf8 }, |
366 | { STV090x_P1_NOSCFG, 0x1c }, | 373 | { STV090x_P1_NOSCFG, 0x1c }, |
374 | { STV090x_P1_DMDTOM, 0x20 }, | ||
367 | { STV090x_P1_CORRELMANT, 0x70 }, | 375 | { STV090x_P1_CORRELMANT, 0x70 }, |
368 | { STV090x_P1_CORRELABS, 0x88 }, | 376 | { STV090x_P1_CORRELABS, 0x88 }, |
369 | { STV090x_P1_AGC2REF, 0x38 } , | 377 | { STV090x_P1_AGC2O, 0x5b }, |
378 | { STV090x_P1_AGC2REF, 0x38 }, | ||
370 | { STV090x_P1_CARCFG, 0xe4 }, | 379 | { STV090x_P1_CARCFG, 0xe4 }, |
371 | { STV090x_P1_ACLC, 0x1A }, | 380 | { STV090x_P1_ACLC, 0x1A }, |
372 | { STV090x_P1_BCLC, 0x09 } , | 381 | { STV090x_P1_BCLC, 0x09 }, |
373 | { STV090x_P1_CARHDR, 0x08 }, | 382 | { STV090x_P1_CARHDR, 0x08 }, |
374 | { STV090x_P1_KREFTMG, 0xc1 }, | 383 | { STV090x_P1_KREFTMG, 0xc1 }, |
375 | { STV090x_P1_SFRSTEP, 0x58 }, | 384 | { STV090x_P1_SFRSTEP, 0x58 }, |
@@ -427,6 +436,7 @@ static struct stv090x_reg stv0903_initval[] = { | |||
427 | { STV090x_GAINLLR_NF15, 0x1A }, | 436 | { STV090x_GAINLLR_NF15, 0x1A }, |
428 | { STV090x_GAINLLR_NF16, 0x1F }, | 437 | { STV090x_GAINLLR_NF16, 0x1F }, |
429 | { STV090x_GAINLLR_NF17, 0x21 }, | 438 | { STV090x_GAINLLR_NF17, 0x21 }, |
439 | { STV090x_RCCFGH, 0x20 }, | ||
430 | { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */ | 440 | { STV090x_P1_FECM, 0x01 }, /*disable the DSS mode */ |
431 | { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/ | 441 | { STV090x_P1_PRVIT, 0x2f } /*disable puncture rate 6/7*/ |
432 | }; | 442 | }; |
@@ -434,6 +444,7 @@ static struct stv090x_reg stv0903_initval[] = { | |||
434 | static struct stv090x_reg stv0900_cut20_val[] = { | 444 | static struct stv090x_reg stv0900_cut20_val[] = { |
435 | 445 | ||
436 | { STV090x_P2_DMDCFG3, 0xe8 }, | 446 | { STV090x_P2_DMDCFG3, 0xe8 }, |
447 | { STV090x_P2_DMDCFG4, 0x10 }, | ||
437 | { STV090x_P2_CARFREQ, 0x38 }, | 448 | { STV090x_P2_CARFREQ, 0x38 }, |
438 | { STV090x_P2_CARHDR, 0x20 }, | 449 | { STV090x_P2_CARHDR, 0x20 }, |
439 | { STV090x_P2_KREFTMG, 0x5a }, | 450 | { STV090x_P2_KREFTMG, 0x5a }, |
@@ -442,6 +453,7 @@ static struct stv090x_reg stv0900_cut20_val[] = { | |||
442 | { STV090x_P2_SMAPCOEF5, 0x04 }, | 453 | { STV090x_P2_SMAPCOEF5, 0x04 }, |
443 | { STV090x_P2_NOSCFG, 0x0c }, | 454 | { STV090x_P2_NOSCFG, 0x0c }, |
444 | { STV090x_P1_DMDCFG3, 0xe8 }, | 455 | { STV090x_P1_DMDCFG3, 0xe8 }, |
456 | { STV090x_P1_DMDCFG4, 0x10 }, | ||
445 | { STV090x_P1_CARFREQ, 0x38 }, | 457 | { STV090x_P1_CARFREQ, 0x38 }, |
446 | { STV090x_P1_CARHDR, 0x20 }, | 458 | { STV090x_P1_CARHDR, 0x20 }, |
447 | { STV090x_P1_KREFTMG, 0x5a }, | 459 | { STV090x_P1_KREFTMG, 0x5a }, |
@@ -467,6 +479,7 @@ static struct stv090x_reg stv0900_cut20_val[] = { | |||
467 | 479 | ||
468 | static struct stv090x_reg stv0903_cut20_val[] = { | 480 | static struct stv090x_reg stv0903_cut20_val[] = { |
469 | { STV090x_P1_DMDCFG3, 0xe8 }, | 481 | { STV090x_P1_DMDCFG3, 0xe8 }, |
482 | { STV090x_P1_DMDCFG4, 0x10 }, | ||
470 | { STV090x_P1_CARFREQ, 0x38 }, | 483 | { STV090x_P1_CARFREQ, 0x38 }, |
471 | { STV090x_P1_CARHDR, 0x20 }, | 484 | { STV090x_P1_CARHDR, 0x20 }, |
472 | { STV090x_P1_KREFTMG, 0x5a }, | 485 | { STV090x_P1_KREFTMG, 0x5a }, |
@@ -640,11 +653,9 @@ static int stv090x_write_reg(struct stv090x_state *state, unsigned int reg, u8 d | |||
640 | static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) | 653 | static int stv090x_i2c_gate_ctrl(struct dvb_frontend *fe, int enable) |
641 | { | 654 | { |
642 | struct stv090x_state *state = fe->demodulator_priv; | 655 | struct stv090x_state *state = fe->demodulator_priv; |
643 | const struct stv090x_config *config = state->config; | ||
644 | u32 reg; | 656 | u32 reg; |
645 | 657 | ||
646 | reg = STV090x_READ_DEMOD(state, I2CRPT); | 658 | reg = STV090x_READ_DEMOD(state, I2CRPT); |
647 | // STV090x_SETFIELD_Px(reg, ENARPT_LEVEL_FIELD, config->repeater_level); | ||
648 | if (enable) { | 659 | if (enable) { |
649 | dprintk(FE_DEBUG, 1, "Enable Gate"); | 660 | dprintk(FE_DEBUG, 1, "Enable Gate"); |
650 | STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1); | 661 | STV090x_SETFIELD_Px(reg, I2CT_ON_FIELD, 1); |
@@ -3605,10 +3616,12 @@ static int stv090x_set_tspath(struct stv090x_state *state) | |||
3605 | case STV090x_TSMODE_SERIAL_PUNCTURED: | 3616 | case STV090x_TSMODE_SERIAL_PUNCTURED: |
3606 | case STV090x_TSMODE_SERIAL_CONTINUOUS: | 3617 | case STV090x_TSMODE_SERIAL_CONTINUOUS: |
3607 | default: | 3618 | default: |
3619 | stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x10); | ||
3608 | break; | 3620 | break; |
3609 | 3621 | ||
3610 | case STV090x_TSMODE_PARALLEL_PUNCTURED: | 3622 | case STV090x_TSMODE_PARALLEL_PUNCTURED: |
3611 | case STV090x_TSMODE_DVBCI: | 3623 | case STV090x_TSMODE_DVBCI: |
3624 | stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x16); | ||
3612 | reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); | 3625 | reg = stv090x_read_reg(state, STV090x_P1_TSCFGM); |
3613 | STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); | 3626 | STV090x_SETFIELD_Px(reg, TSFIFO_MANSPEED_FIELD, 3); |
3614 | if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) | 3627 | if (stv090x_write_reg(state, STV090x_P1_TSCFGM, reg) < 0) |
@@ -3632,10 +3645,12 @@ static int stv090x_set_tspath(struct stv090x_state *state) | |||
3632 | case STV090x_TSMODE_SERIAL_PUNCTURED: | 3645 | case STV090x_TSMODE_SERIAL_PUNCTURED: |
3633 | case STV090x_TSMODE_SERIAL_CONTINUOUS: | 3646 | case STV090x_TSMODE_SERIAL_CONTINUOUS: |
3634 | default: | 3647 | default: |
3648 | stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x14); | ||
3635 | break; | 3649 | break; |
3636 | 3650 | ||
3637 | case STV090x_TSMODE_PARALLEL_PUNCTURED: | 3651 | case STV090x_TSMODE_PARALLEL_PUNCTURED: |
3638 | case STV090x_TSMODE_DVBCI: | 3652 | case STV090x_TSMODE_DVBCI: |
3653 | stv090x_write_reg(state, STV090x_TSGENERAL1X, 0x12); | ||
3639 | break; | 3654 | break; |
3640 | } | 3655 | } |
3641 | break; | 3656 | break; |
@@ -3893,6 +3908,7 @@ struct dvb_frontend *stv090x_attach(const struct stv090x_config *config, | |||
3893 | state->i2c = i2c; | 3908 | state->i2c = i2c; |
3894 | state->frontend.ops = stv090x_ops; | 3909 | state->frontend.ops = stv090x_ops; |
3895 | state->frontend.demodulator_priv = state; | 3910 | state->frontend.demodulator_priv = state; |
3911 | state->demod = demod; | ||
3896 | state->demod_mode = config->demod_mode; /* Single or Dual mode */ | 3912 | state->demod_mode = config->demod_mode; /* Single or Dual mode */ |
3897 | state->device = config->device; | 3913 | state->device = config->device; |
3898 | state->rolloff = 35; /* default */ | 3914 | state->rolloff = 35; /* default */ |
diff --git a/drivers/media/dvb/frontends/stv090x_reg.h b/drivers/media/dvb/frontends/stv090x_reg.h index b59eca9539cd..0dff56d4e94b 100644 --- a/drivers/media/dvb/frontends/stv090x_reg.h +++ b/drivers/media/dvb/frontends/stv090x_reg.h | |||
@@ -48,6 +48,8 @@ | |||
48 | #define STV090x_OFFST_OUTPARRS3_HZ_FIELD 3 | 48 | #define STV090x_OFFST_OUTPARRS3_HZ_FIELD 3 |
49 | #define STV090x_WIDTH_OUTPARRS3_HZ_FIELD 1 | 49 | #define STV090x_WIDTH_OUTPARRS3_HZ_FIELD 1 |
50 | 50 | ||
51 | #define STV090x_MODECFG 0xf11d | ||
52 | |||
51 | #define STV090x_IRQSTATUS3 0xf120 | 53 | #define STV090x_IRQSTATUS3 0xf120 |
52 | #define STV090x_OFFST_SPLL_LOCK_FIELD 5 | 54 | #define STV090x_OFFST_SPLL_LOCK_FIELD 5 |
53 | #define STV090x_WIDTH_SPLL_LOCK_FIELD 1 | 55 | #define STV090x_WIDTH_SPLL_LOCK_FIELD 1 |
@@ -312,9 +314,9 @@ | |||
312 | #define STV090x_OFFST_ERRORx_XOR_FIELD 0 | 314 | #define STV090x_OFFST_ERRORx_XOR_FIELD 0 |
313 | #define STV090x_WIDTH_ERRORx_XOR_FIELD 1 | 315 | #define STV090x_WIDTH_ERRORx_XOR_FIELD 1 |
314 | 316 | ||
315 | #define STV090x_DPNxCFG(__x) (0xf15c + (__x - 1) * 0x5) | 317 | #define STV090x_DPNxCFG(__x) (0xf15c + (__x - 1) * 0x5) |
316 | #define STV090x_DPN1CFG STV090x_DPNxCFG(1) | 318 | #define STV090x_DPN1CFG STV090x_DPNxCFG(1) |
317 | #define STV090x_DPN2CFG STV090x_DPNxCFG(2) | 319 | #define STV090x_DPN2CFG STV090x_DPNxCFG(2) |
318 | #define STV090x_DPN3CFG STV090x_DPNxCFG(3) | 320 | #define STV090x_DPN3CFG STV090x_DPNxCFG(3) |
319 | #define STV090x_OFFST_DPNx_OPD_FIELD 7 | 321 | #define STV090x_OFFST_DPNx_OPD_FIELD 7 |
320 | #define STV090x_WIDTH_DPNx_OPD_FIELD 1 | 322 | #define STV090x_WIDTH_DPNx_OPD_FIELD 1 |
@@ -571,8 +573,8 @@ | |||
571 | #define STV090x_WIDTH_FSKR_CARLOSS_THRESH_FIELD 8 | 573 | #define STV090x_WIDTH_FSKR_CARLOSS_THRESH_FIELD 8 |
572 | 574 | ||
573 | #define STV090x_Px_DISTXCTL(__x) (0xF1A0 - (__x - 1) * 0x10) | 575 | #define STV090x_Px_DISTXCTL(__x) (0xF1A0 - (__x - 1) * 0x10) |
574 | #define STV090x_P1_DISTXCTL (1) | 576 | #define STV090x_P1_DISTXCTL STV090x_Px_DISTXCTL(1) |
575 | #define STV090x_P2_DISTXCTL (2) | 577 | #define STV090x_P2_DISTXCTL STV090x_Px_DISTXCTL(2) |
576 | #define STV090x_OFFST_Px_TIM_OFF_FIELD 7 | 578 | #define STV090x_OFFST_Px_TIM_OFF_FIELD 7 |
577 | #define STV090x_WIDTH_Px_TIM_OFF_FIELD 1 | 579 | #define STV090x_WIDTH_Px_TIM_OFF_FIELD 1 |
578 | #define STV090x_OFFST_Px_DISEQC_RESET_FIELD 6 | 580 | #define STV090x_OFFST_Px_DISEQC_RESET_FIELD 6 |
@@ -585,8 +587,8 @@ | |||
585 | #define STV090x_WIDTH_Px_DISTX_MODE_FIELD 3 | 587 | #define STV090x_WIDTH_Px_DISTX_MODE_FIELD 3 |
586 | 588 | ||
587 | #define STV090x_Px_DISRXCTL(__x) (0xf1a1 - (__x - 1) * 0x10) | 589 | #define STV090x_Px_DISRXCTL(__x) (0xf1a1 - (__x - 1) * 0x10) |
588 | #define STV090x_P1_DISRXCTL (1) | 590 | #define STV090x_P1_DISRXCTL STV090x_Px_DISRXCTL(1) |
589 | #define STV090x_P2_DISRXCTL (2) | 591 | #define STV090x_P2_DISRXCTL STV090x_Px_DISRXCTL(2) |
590 | #define STV090x_OFFST_Px_RECEIVER_ON_FIELD 7 | 592 | #define STV090x_OFFST_Px_RECEIVER_ON_FIELD 7 |
591 | #define STV090x_WIDTH_Px_RECEIVER_ON_FIELD 1 | 593 | #define STV090x_WIDTH_Px_RECEIVER_ON_FIELD 1 |
592 | #define STV090x_OFFST_Px_IGNO_SHORT22K_FIELD 6 | 594 | #define STV090x_OFFST_Px_IGNO_SHORT22K_FIELD 6 |
@@ -603,8 +605,8 @@ | |||
603 | #define STV090x_WIDTH_Px_IRQ_4NBYTES_FIELD 1 | 605 | #define STV090x_WIDTH_Px_IRQ_4NBYTES_FIELD 1 |
604 | 606 | ||
605 | #define STV090x_Px_DISRX_ST0(__x) (0xf1a4 - (__x - 1) * 0x10) | 607 | #define STV090x_Px_DISRX_ST0(__x) (0xf1a4 - (__x - 1) * 0x10) |
606 | #define STV090x_P1_DISRX_ST0 (1) | 608 | #define STV090x_P1_DISRX_ST0 STV090x_Px_DISRX_ST0(1) |
607 | #define STV090x_P2_DISRX_ST0 (2) | 609 | #define STV090x_P2_DISRX_ST0 STV090x_Px_DISRX_ST0(2) |
608 | #define STV090x_OFFST_Px_RX_END_FIELD 7 | 610 | #define STV090x_OFFST_Px_RX_END_FIELD 7 |
609 | #define STV090x_WIDTH_Px_RX_END_FIELD 1 | 611 | #define STV090x_WIDTH_Px_RX_END_FIELD 1 |
610 | #define STV090x_OFFST_Px_RX_ACTIVE_FIELD 6 | 612 | #define STV090x_OFFST_Px_RX_ACTIVE_FIELD 6 |
@@ -621,8 +623,8 @@ | |||
621 | #define STV090x_WIDTH_Px_ABORT_DISRX_FIELD 1 | 623 | #define STV090x_WIDTH_Px_ABORT_DISRX_FIELD 1 |
622 | 624 | ||
623 | #define STV090x_Px_DISRX_ST1(__x) (0xf1a5 - (__x - 1) * 0x10) | 625 | #define STV090x_Px_DISRX_ST1(__x) (0xf1a5 - (__x - 1) * 0x10) |
624 | #define STV090x_P1_DISRX_ST1 (1) | 626 | #define STV090x_P1_DISRX_ST1 STV090x_Px_DISRX_ST1(1) |
625 | #define STV090x_P2_DISRX_ST1 (2) | 627 | #define STV090x_P2_DISRX_ST1 STV090x_Px_DISRX_ST1(2) |
626 | #define STV090x_OFFST_Px_RX_FAIL_FIELD 7 | 628 | #define STV090x_OFFST_Px_RX_FAIL_FIELD 7 |
627 | #define STV090x_WIDTH_Px_RX_FAIL_FIELD 1 | 629 | #define STV090x_WIDTH_Px_RX_FAIL_FIELD 1 |
628 | #define STV090x_OFFST_Px_FIFO_PARITYFAIL_FIELD 6 | 630 | #define STV090x_OFFST_Px_FIFO_PARITYFAIL_FIELD 6 |
@@ -635,20 +637,20 @@ | |||
635 | #define STV090x_WIDTH_Px_FIFO_BYTENBR_FIELD 4 | 637 | #define STV090x_WIDTH_Px_FIFO_BYTENBR_FIELD 4 |
636 | 638 | ||
637 | #define STV090x_Px_DISRXDATA(__x) (0xf1a6 - (__x - 1) * 0x10) | 639 | #define STV090x_Px_DISRXDATA(__x) (0xf1a6 - (__x - 1) * 0x10) |
638 | #define STV090x_P1_DISRXDATA (1) | 640 | #define STV090x_P1_DISRXDATA STV090x_Px_DISRXDATA(1) |
639 | #define STV090x_P2_DISRXDATA (2) | 641 | #define STV090x_P2_DISRXDATA STV090x_Px_DISRXDATA(2) |
640 | #define STV090x_OFFST_Px_DISRX_DATA_FIELD 0 | 642 | #define STV090x_OFFST_Px_DISRX_DATA_FIELD 0 |
641 | #define STV090x_WIDTH_Px_DISRX_DATA_FIELD 8 | 643 | #define STV090x_WIDTH_Px_DISRX_DATA_FIELD 8 |
642 | 644 | ||
643 | #define STV090x_Px_DISTXDATA(__x) (0xf1a7 - (__x - 1) * 0x10) | 645 | #define STV090x_Px_DISTXDATA(__x) (0xf1a7 - (__x - 1) * 0x10) |
644 | #define STV090x_P1_DISTXDATA (1) | 646 | #define STV090x_P1_DISTXDATA STV090x_Px_DISTXDATA(1) |
645 | #define STV090x_P2_DISTXDATA (2) | 647 | #define STV090x_P2_DISTXDATA STV090x_Px_DISTXDATA(2) |
646 | #define STV090x_OFFST_Px_DISEQC_FIFO_FIELD 0 | 648 | #define STV090x_OFFST_Px_DISEQC_FIFO_FIELD 0 |
647 | #define STV090x_WIDTH_Px_DISEQC_FIFO_FIELD 8 | 649 | #define STV090x_WIDTH_Px_DISEQC_FIFO_FIELD 8 |
648 | 650 | ||
649 | #define STV090x_Px_DISTXSTATUS(__x) (0xf1a8 - (__x - 1) * 0x10) | 651 | #define STV090x_Px_DISTXSTATUS(__x) (0xf1a8 - (__x - 1) * 0x10) |
650 | #define STV090x_P1_DISTXSTATUS (1) | 652 | #define STV090x_P1_DISTXSTATUS STV090x_Px_DISTXSTATUS(1) |
651 | #define STV090x_P2_DISTXSTATUS (2) | 653 | #define STV090x_P2_DISTXSTATUS STV090x_Px_DISTXSTATUS(2) |
652 | #define STV090x_OFFST_Px_TX_FAIL_FIELD 7 | 654 | #define STV090x_OFFST_Px_TX_FAIL_FIELD 7 |
653 | #define STV090x_WIDTH_Px_TX_FAIL_FIELD 1 | 655 | #define STV090x_WIDTH_Px_TX_FAIL_FIELD 1 |
654 | #define STV090x_OFFST_Px_FIFO_FULL_FIELD 6 | 656 | #define STV090x_OFFST_Px_FIFO_FULL_FIELD 6 |
@@ -661,26 +663,26 @@ | |||
661 | #define STV090x_WIDTH_Px_TXFIFO_BYTES_FIELD 4 | 663 | #define STV090x_WIDTH_Px_TXFIFO_BYTES_FIELD 4 |
662 | 664 | ||
663 | #define STV090x_Px_F22TX(__x) (0xf1a9 - (__x - 1) * 0x10) | 665 | #define STV090x_Px_F22TX(__x) (0xf1a9 - (__x - 1) * 0x10) |
664 | #define STV090x_P1_F22TX (1) | 666 | #define STV090x_P1_F22TX STV090x_Px_F22TX(1) |
665 | #define STV090x_P2_F22TX (2) | 667 | #define STV090x_P2_F22TX STV090x_Px_F22TX(2) |
666 | #define STV090x_OFFST_Px_F22_REG_FIELD 0 | 668 | #define STV090x_OFFST_Px_F22_REG_FIELD 0 |
667 | #define STV090x_WIDTH_Px_F22_REG_FIELD 8 | 669 | #define STV090x_WIDTH_Px_F22_REG_FIELD 8 |
668 | 670 | ||
669 | #define STV090x_Px_F22RX(__x) (0xf1aa - (__x - 1) * 0x10) | 671 | #define STV090x_Px_F22RX(__x) (0xf1aa - (__x - 1) * 0x10) |
670 | #define STV090x_P1_F22RX (1) | 672 | #define STV090x_P1_F22RX STV090x_Px_F22RX(1) |
671 | #define STV090x_P2_F22RX (2) | 673 | #define STV090x_P2_F22RX STV090x_Px_F22RX(2) |
672 | #define STV090x_OFFST_Px_F22RX_REG_FIELD 0 | 674 | #define STV090x_OFFST_Px_F22RX_REG_FIELD 0 |
673 | #define STV090x_WIDTH_Px_F22RX_REG_FIELD 8 | 675 | #define STV090x_WIDTH_Px_F22RX_REG_FIELD 8 |
674 | 676 | ||
675 | #define STV090x_Px_ACRPRESC(__x) (0xf1ac - (__x - 1) * 0x10) | 677 | #define STV090x_Px_ACRPRESC(__x) (0xf1ac - (__x - 1) * 0x10) |
676 | #define STV090x_P1_ACRPRESC (1) | 678 | #define STV090x_P1_ACRPRESC STV090x_Px_ACRPRESC(1) |
677 | #define STV090x_P2_ACRPRESC (2) | 679 | #define STV090x_P2_ACRPRESC STV090x_Px_ACRPRESC(2) |
678 | #define STV090x_OFFST_Px_ACR_PRESC_FIELD 0 | 680 | #define STV090x_OFFST_Px_ACR_PRESC_FIELD 0 |
679 | #define STV090x_WIDTH_Px_ACR_PRESC_FIELD 3 | 681 | #define STV090x_WIDTH_Px_ACR_PRESC_FIELD 3 |
680 | 682 | ||
681 | #define STV090x_Px_ACRDIV(__x) (0xf1ad - (__x - 1) * 0x10) | 683 | #define STV090x_Px_ACRDIV(__x) (0xf1ad - (__x - 1) * 0x10) |
682 | #define STV090x_P1_ACRDIV (1) | 684 | #define STV090x_P1_ACRDIV STV090x_Px_ACRDIV(1) |
683 | #define STV090x_P2_ACRDIV (2) | 685 | #define STV090x_P2_ACRDIV STV090x_Px_ACRDIV(2) |
684 | #define STV090x_OFFST_Px_ACR_DIV_FIELD 0 | 686 | #define STV090x_OFFST_Px_ACR_DIV_FIELD 0 |
685 | #define STV090x_WIDTH_Px_ACR_DIV_FIELD 8 | 687 | #define STV090x_WIDTH_Px_ACR_DIV_FIELD 8 |
686 | 688 | ||
@@ -892,6 +894,10 @@ | |||
892 | #define STV090x_OFFST_Px_NOSTOP_FIFOFULL_FIELD 3 | 894 | #define STV090x_OFFST_Px_NOSTOP_FIFOFULL_FIELD 3 |
893 | #define STV090x_WIDTH_Px_NOSTOP_FIFOFULL_FIELD 1 | 895 | #define STV090x_WIDTH_Px_NOSTOP_FIFOFULL_FIELD 1 |
894 | 896 | ||
897 | #define STV090x_Px_DMDCFG4(__x) (0xf41f - (__x - 1) * 0x200) | ||
898 | #define STV090x_P1_DMDCFG4 STV090x_Px_DMDCFG4(1) | ||
899 | #define STV090x_P2_DMDCFG4 STV090x_Px_DMDCFG4(2) | ||
900 | |||
895 | #define STV090x_Px_CORRELMANT(__x) (0xF420 - (__x - 1) * 0x200) | 901 | #define STV090x_Px_CORRELMANT(__x) (0xF420 - (__x - 1) * 0x200) |
896 | #define STV090x_P1_CORRELMANT STV090x_Px_CORRELMANT(1) | 902 | #define STV090x_P1_CORRELMANT STV090x_Px_CORRELMANT(1) |
897 | #define STV090x_P2_CORRELMANT STV090x_Px_CORRELMANT(2) | 903 | #define STV090x_P2_CORRELMANT STV090x_Px_CORRELMANT(2) |
@@ -922,6 +928,14 @@ | |||
922 | #define STV090x_OFFST_Px_PLH_TYPE_FIELD 0 | 928 | #define STV090x_OFFST_Px_PLH_TYPE_FIELD 0 |
923 | #define STV090x_WIDTH_Px_PLH_TYPE_FIELD 2 | 929 | #define STV090x_WIDTH_Px_PLH_TYPE_FIELD 2 |
924 | 930 | ||
931 | #define STV090x_Px_AGCK32(__x) (0xf42b - (__x - 1) * 0x200) | ||
932 | #define STV090x_P1_AGCK32 STV090x_Px_AGCK32(1) | ||
933 | #define STV090x_P2_AGCK32 STV090x_Px_AGCK32(2) | ||
934 | |||
935 | #define STV090x_Px_AGC2O(__x) (0xF42C - (__x - 1) * 0x200) | ||
936 | #define STV090x_P1_AGC2O STV090x_Px_AGC2O(1) | ||
937 | #define STV090x_P2_AGC2O STV090x_Px_AGC2O(2) | ||
938 | |||
925 | #define STV090x_Px_AGC2REF(__x) (0xF42D - (__x - 1) * 0x200) | 939 | #define STV090x_Px_AGC2REF(__x) (0xF42D - (__x - 1) * 0x200) |
926 | #define STV090x_P1_AGC2REF STV090x_Px_AGC2REF(1) | 940 | #define STV090x_P1_AGC2REF STV090x_Px_AGC2REF(1) |
927 | #define STV090x_P2_AGC2REF STV090x_Px_AGC2REF(2) | 941 | #define STV090x_P2_AGC2REF STV090x_Px_AGC2REF(2) |
@@ -1640,7 +1654,7 @@ | |||
1640 | #define STV090x_OFFST_Px_SMAPCOEF_8P_LLR23_FIELD 0 | 1654 | #define STV090x_OFFST_Px_SMAPCOEF_8P_LLR23_FIELD 0 |
1641 | #define STV090x_WIDTH_Px_SMAPCOEF_8P_LLR23_FIELD 7 | 1655 | #define STV090x_WIDTH_Px_SMAPCOEF_8P_LLR23_FIELD 7 |
1642 | 1656 | ||
1643 | #define STV090x_Px_DMDPLHSTAT(__x) (0xF520 - (__x - 1) * 0x200) | 1657 | #define STV090x_Px_DMDPLHSTAT(__x) (0xF520 - (__x - 1) * 0x200) |
1644 | #define STV090x_P1_DMDPLHSTAT STV090x_Px_DMDPLHSTAT(1) | 1658 | #define STV090x_P1_DMDPLHSTAT STV090x_Px_DMDPLHSTAT(1) |
1645 | #define STV090x_P2_DMDPLHSTAT STV090x_Px_DMDPLHSTAT(2) | 1659 | #define STV090x_P2_DMDPLHSTAT STV090x_Px_DMDPLHSTAT(2) |
1646 | #define STV090x_OFFST_Px_PLH_STATISTIC_FIELD 0 | 1660 | #define STV090x_OFFST_Px_PLH_STATISTIC_FIELD 0 |
@@ -2281,12 +2295,17 @@ | |||
2281 | #define STV090x_OFFST_Px_FSPYBER_CTIME_FIELD 0 | 2295 | #define STV090x_OFFST_Px_FSPYBER_CTIME_FIELD 0 |
2282 | #define STV090x_WIDTH_Px_FSPYBER_CTIME_FIELD 3 | 2296 | #define STV090x_WIDTH_Px_FSPYBER_CTIME_FIELD 3 |
2283 | 2297 | ||
2298 | #define STV090x_RCCFGH 0xf600 | ||
2299 | |||
2284 | #define STV090x_TSGENERAL 0xF630 | 2300 | #define STV090x_TSGENERAL 0xF630 |
2285 | #define STV090x_OFFST_Px_MUXSTREAM_OUT_FIELD 3 | 2301 | #define STV090x_OFFST_Px_MUXSTREAM_OUT_FIELD 3 |
2286 | #define STV090x_WIDTH_Px_MUXSTREAM_OUT_FIELD 1 | 2302 | #define STV090x_WIDTH_Px_MUXSTREAM_OUT_FIELD 1 |
2287 | #define STV090x_OFFST_Px_TSFIFO_PERMPARAL_FIELD 1 | 2303 | #define STV090x_OFFST_Px_TSFIFO_PERMPARAL_FIELD 1 |
2288 | #define STV090x_WIDTH_Px_TSFIFO_PERMPARAL_FIELD 2 | 2304 | #define STV090x_WIDTH_Px_TSFIFO_PERMPARAL_FIELD 2 |
2289 | 2305 | ||
2306 | #define STV090x_TSGENERAL1X 0xf670 | ||
2307 | #define STV090x_CFGEXT 0xfa80 | ||
2308 | |||
2290 | #define STV090x_TSTRES0 0xFF11 | 2309 | #define STV090x_TSTRES0 0xFF11 |
2291 | #define STV090x_OFFST_FRESFEC_FIELD 7 | 2310 | #define STV090x_OFFST_FRESFEC_FIELD 7 |
2292 | #define STV090x_WIDTH_FRESFEC_FIELD 1 | 2311 | #define STV090x_WIDTH_FRESFEC_FIELD 1 |