diff options
-rw-r--r-- | arch/arm/mach-omap1/Makefile | 3 | ||||
-rw-r--r-- | arch/arm/mach-omap1/clock.c | 488 | ||||
-rw-r--r-- | arch/arm/mach-omap1/clock.h | 667 | ||||
-rw-r--r-- | arch/arm/mach-omap1/clock_data.c | 843 | ||||
-rw-r--r-- | arch/arm/mach-omap1/io.c | 3 | ||||
-rw-r--r-- | arch/arm/mach-omap1/opp.h | 28 | ||||
-rw-r--r-- | arch/arm/mach-omap1/opp_data.c | 59 | ||||
-rw-r--r-- | arch/arm/plat-omap/include/plat/clkdev_omap.h | 18 |
8 files changed, 1096 insertions, 1013 deletions
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 87e539aa8ad9..ceced8ffe850 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile | |||
@@ -3,7 +3,8 @@ | |||
3 | # | 3 | # |
4 | 4 | ||
5 | # Common support | 5 | # Common support |
6 | obj-y := io.o id.o sram.o clock.o irq.o mux.o serial.o devices.o | 6 | obj-y := io.o id.o sram.o irq.o mux.o serial.o devices.o |
7 | obj-y += clock.o clock_data.o opp_data.o | ||
7 | 8 | ||
8 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o | 9 | obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o |
9 | 10 | ||
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c index 26a887ccda7b..2ba9ab953731 100644 --- a/arch/arm/mach-omap1/clock.c +++ b/arch/arm/mach-omap1/clock.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/mach-omap1/clock.c | 2 | * linux/arch/arm/mach-omap1/clock.c |
3 | * | 3 | * |
4 | * Copyright (C) 2004 - 2005 Nokia corporation | 4 | * Copyright (C) 2004 - 2005, 2009 Nokia corporation |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
6 | * | 6 | * |
7 | * Modified to use omap shared clock framework by | 7 | * Modified to use omap shared clock framework by |
@@ -26,12 +26,17 @@ | |||
26 | #include <plat/usb.h> | 26 | #include <plat/usb.h> |
27 | #include <plat/clock.h> | 27 | #include <plat/clock.h> |
28 | #include <plat/sram.h> | 28 | #include <plat/sram.h> |
29 | 29 | #include <plat/clkdev_omap.h> | |
30 | static const struct clkops clkops_generic; | ||
31 | static const struct clkops clkops_uart; | ||
32 | static const struct clkops clkops_dspck; | ||
33 | 30 | ||
34 | #include "clock.h" | 31 | #include "clock.h" |
32 | #include "opp.h" | ||
33 | |||
34 | __u32 arm_idlect1_mask; | ||
35 | struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; | ||
36 | |||
37 | /*------------------------------------------------------------------------- | ||
38 | * Omap1 specific clock functions | ||
39 | *-------------------------------------------------------------------------*/ | ||
35 | 40 | ||
36 | static int clk_omap1_dummy_enable(struct clk *clk) | 41 | static int clk_omap1_dummy_enable(struct clk *clk) |
37 | { | 42 | { |
@@ -42,134 +47,24 @@ static void clk_omap1_dummy_disable(struct clk *clk) | |||
42 | { | 47 | { |
43 | } | 48 | } |
44 | 49 | ||
45 | static const struct clkops clkops_dummy = { | 50 | const struct clkops clkops_dummy = { |
46 | .enable = clk_omap1_dummy_enable, | 51 | .enable = clk_omap1_dummy_enable, |
47 | .disable = clk_omap1_dummy_disable, | 52 | .disable = clk_omap1_dummy_disable, |
48 | }; | ||
49 | |||
50 | static struct clk dummy_ck = { | ||
51 | .name = "dummy", | ||
52 | .ops = &clkops_dummy, | ||
53 | .flags = RATE_FIXED, | ||
54 | }; | ||
55 | |||
56 | struct omap_clk { | ||
57 | u32 cpu; | ||
58 | struct clk_lookup lk; | ||
59 | }; | 53 | }; |
60 | 54 | ||
61 | #define CLK(dev, con, ck, cp) \ | 55 | /* XXX can be replaced with a fixed_divisor_recalc */ |
62 | { \ | 56 | unsigned long omap1_watchdog_recalc(struct clk *clk) |
63 | .cpu = cp, \ | ||
64 | .lk = { \ | ||
65 | .dev_id = dev, \ | ||
66 | .con_id = con, \ | ||
67 | .clk = ck, \ | ||
68 | }, \ | ||
69 | } | ||
70 | |||
71 | #define CK_310 (1 << 0) | ||
72 | #define CK_7XX (1 << 1) | ||
73 | #define CK_1510 (1 << 2) | ||
74 | #define CK_16XX (1 << 3) | ||
75 | |||
76 | static struct omap_clk omap_clks[] = { | ||
77 | /* non-ULPD clocks */ | ||
78 | CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
79 | CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310), | ||
80 | /* CK_GEN1 clocks */ | ||
81 | CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), | ||
82 | CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), | ||
83 | CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), | ||
84 | CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
85 | CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), | ||
86 | CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
87 | CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
88 | CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
89 | CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), | ||
90 | CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), | ||
91 | CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), | ||
92 | CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), | ||
93 | /* CK_GEN2 clocks */ | ||
94 | CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), | ||
95 | CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), | ||
96 | CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), | ||
97 | CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
98 | CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), | ||
99 | /* CK_GEN3 clocks */ | ||
100 | CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
101 | CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), | ||
102 | CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX), | ||
103 | CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), | ||
104 | CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), | ||
105 | CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), | ||
106 | CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), | ||
107 | CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
108 | CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), | ||
109 | CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), | ||
110 | CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), | ||
111 | CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX), | ||
112 | CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), | ||
113 | /* ULPD clocks */ | ||
114 | CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), | ||
115 | CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), | ||
116 | CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), | ||
117 | CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), | ||
118 | CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), | ||
119 | CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), | ||
120 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), | ||
121 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), | ||
122 | CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), | ||
123 | CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX), | ||
124 | CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), | ||
125 | CLK(NULL, "mclk", &mclk_16xx, CK_16XX), | ||
126 | CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), | ||
127 | CLK(NULL, "bclk", &bclk_16xx, CK_16XX), | ||
128 | CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), | ||
129 | CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX), | ||
130 | CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
131 | CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), | ||
132 | CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), | ||
133 | /* Virtual clocks */ | ||
134 | CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), | ||
135 | CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310), | ||
136 | CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX), | ||
137 | CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310), | ||
138 | CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
139 | CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), | ||
140 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), | ||
141 | CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), | ||
142 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), | ||
143 | CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), | ||
144 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), | ||
145 | CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
146 | CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
147 | CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
148 | }; | ||
149 | |||
150 | static int omap1_clk_enable_generic(struct clk * clk); | ||
151 | static int omap1_clk_enable(struct clk *clk); | ||
152 | static void omap1_clk_disable_generic(struct clk * clk); | ||
153 | static void omap1_clk_disable(struct clk *clk); | ||
154 | |||
155 | __u32 arm_idlect1_mask; | ||
156 | |||
157 | /*------------------------------------------------------------------------- | ||
158 | * Omap1 specific clock functions | ||
159 | *-------------------------------------------------------------------------*/ | ||
160 | |||
161 | static unsigned long omap1_watchdog_recalc(struct clk *clk) | ||
162 | { | 57 | { |
163 | return clk->parent->rate / 14; | 58 | return clk->parent->rate / 14; |
164 | } | 59 | } |
165 | 60 | ||
166 | static unsigned long omap1_uart_recalc(struct clk *clk) | 61 | unsigned long omap1_uart_recalc(struct clk *clk) |
167 | { | 62 | { |
168 | unsigned int val = __raw_readl(clk->enable_reg); | 63 | unsigned int val = __raw_readl(clk->enable_reg); |
169 | return val & clk->enable_bit ? 48000000 : 12000000; | 64 | return val & clk->enable_bit ? 48000000 : 12000000; |
170 | } | 65 | } |
171 | 66 | ||
172 | static unsigned long omap1_sossi_recalc(struct clk *clk) | 67 | unsigned long omap1_sossi_recalc(struct clk *clk) |
173 | { | 68 | { |
174 | u32 div = omap_readl(MOD_CONF_CTRL_1); | 69 | u32 div = omap_readl(MOD_CONF_CTRL_1); |
175 | 70 | ||
@@ -179,64 +74,6 @@ static unsigned long omap1_sossi_recalc(struct clk *clk) | |||
179 | return clk->parent->rate / div; | 74 | return clk->parent->rate / div; |
180 | } | 75 | } |
181 | 76 | ||
182 | static int omap1_clk_enable_dsp_domain(struct clk *clk) | ||
183 | { | ||
184 | int retval; | ||
185 | |||
186 | retval = omap1_clk_enable(&api_ck.clk); | ||
187 | if (!retval) { | ||
188 | retval = omap1_clk_enable_generic(clk); | ||
189 | omap1_clk_disable(&api_ck.clk); | ||
190 | } | ||
191 | |||
192 | return retval; | ||
193 | } | ||
194 | |||
195 | static void omap1_clk_disable_dsp_domain(struct clk *clk) | ||
196 | { | ||
197 | if (omap1_clk_enable(&api_ck.clk) == 0) { | ||
198 | omap1_clk_disable_generic(clk); | ||
199 | omap1_clk_disable(&api_ck.clk); | ||
200 | } | ||
201 | } | ||
202 | |||
203 | static const struct clkops clkops_dspck = { | ||
204 | .enable = &omap1_clk_enable_dsp_domain, | ||
205 | .disable = &omap1_clk_disable_dsp_domain, | ||
206 | }; | ||
207 | |||
208 | static int omap1_clk_enable_uart_functional(struct clk *clk) | ||
209 | { | ||
210 | int ret; | ||
211 | struct uart_clk *uclk; | ||
212 | |||
213 | ret = omap1_clk_enable_generic(clk); | ||
214 | if (ret == 0) { | ||
215 | /* Set smart idle acknowledgement mode */ | ||
216 | uclk = (struct uart_clk *)clk; | ||
217 | omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8, | ||
218 | uclk->sysc_addr); | ||
219 | } | ||
220 | |||
221 | return ret; | ||
222 | } | ||
223 | |||
224 | static void omap1_clk_disable_uart_functional(struct clk *clk) | ||
225 | { | ||
226 | struct uart_clk *uclk; | ||
227 | |||
228 | /* Set force idle acknowledgement mode */ | ||
229 | uclk = (struct uart_clk *)clk; | ||
230 | omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr); | ||
231 | |||
232 | omap1_clk_disable_generic(clk); | ||
233 | } | ||
234 | |||
235 | static const struct clkops clkops_uart = { | ||
236 | .enable = &omap1_clk_enable_uart_functional, | ||
237 | .disable = &omap1_clk_disable_uart_functional, | ||
238 | }; | ||
239 | |||
240 | static void omap1_clk_allow_idle(struct clk *clk) | 77 | static void omap1_clk_allow_idle(struct clk *clk) |
241 | { | 78 | { |
242 | struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; | 79 | struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; |
@@ -344,7 +181,7 @@ static int calc_dsor_exp(struct clk *clk, unsigned long rate) | |||
344 | return dsor_exp; | 181 | return dsor_exp; |
345 | } | 182 | } |
346 | 183 | ||
347 | static unsigned long omap1_ckctl_recalc(struct clk *clk) | 184 | unsigned long omap1_ckctl_recalc(struct clk *clk) |
348 | { | 185 | { |
349 | /* Calculate divisor encoded as 2-bit exponent */ | 186 | /* Calculate divisor encoded as 2-bit exponent */ |
350 | int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); | 187 | int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); |
@@ -352,7 +189,7 @@ static unsigned long omap1_ckctl_recalc(struct clk *clk) | |||
352 | return clk->parent->rate / dsor; | 189 | return clk->parent->rate / dsor; |
353 | } | 190 | } |
354 | 191 | ||
355 | static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) | 192 | unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) |
356 | { | 193 | { |
357 | int dsor; | 194 | int dsor; |
358 | 195 | ||
@@ -363,25 +200,29 @@ static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) | |||
363 | * Note that DSP_CKCTL virt addr = phys addr, so | 200 | * Note that DSP_CKCTL virt addr = phys addr, so |
364 | * we must use __raw_readw() instead of omap_readw(). | 201 | * we must use __raw_readw() instead of omap_readw(). |
365 | */ | 202 | */ |
366 | omap1_clk_enable(&api_ck.clk); | 203 | omap1_clk_enable(api_ck_p); |
367 | dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); | 204 | dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); |
368 | omap1_clk_disable(&api_ck.clk); | 205 | omap1_clk_disable(api_ck_p); |
369 | 206 | ||
370 | return clk->parent->rate / dsor; | 207 | return clk->parent->rate / dsor; |
371 | } | 208 | } |
372 | 209 | ||
373 | /* MPU virtual clock functions */ | 210 | /* MPU virtual clock functions */ |
374 | static int omap1_select_table_rate(struct clk * clk, unsigned long rate) | 211 | int omap1_select_table_rate(struct clk *clk, unsigned long rate) |
375 | { | 212 | { |
376 | /* Find the highest supported frequency <= rate and switch to it */ | 213 | /* Find the highest supported frequency <= rate and switch to it */ |
377 | struct mpu_rate * ptr; | 214 | struct mpu_rate * ptr; |
215 | unsigned long dpll1_rate, ref_rate; | ||
216 | |||
217 | dpll1_rate = clk_get_rate(ck_dpll1_p); | ||
218 | ref_rate = clk_get_rate(ck_ref_p); | ||
378 | 219 | ||
379 | for (ptr = rate_table; ptr->rate; ptr++) { | 220 | for (ptr = omap1_rate_table; ptr->rate; ptr++) { |
380 | if (ptr->xtal != ck_ref.rate) | 221 | if (ptr->xtal != ref_rate) |
381 | continue; | 222 | continue; |
382 | 223 | ||
383 | /* DPLL1 cannot be reprogrammed without risking system crash */ | 224 | /* DPLL1 cannot be reprogrammed without risking system crash */ |
384 | if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate) | 225 | if (likely(dpll1_rate != 0) && ptr->pll_rate != dpll1_rate) |
385 | continue; | 226 | continue; |
386 | 227 | ||
387 | /* Can check only after xtal frequency check */ | 228 | /* Can check only after xtal frequency check */ |
@@ -402,11 +243,13 @@ static int omap1_select_table_rate(struct clk * clk, unsigned long rate) | |||
402 | else | 243 | else |
403 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); | 244 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); |
404 | 245 | ||
405 | ck_dpll1.rate = ptr->pll_rate; | 246 | /* XXX Do we need to recalculate the tree below DPLL1 at this point? */ |
247 | ck_dpll1_p->rate = ptr->pll_rate; | ||
248 | |||
406 | return 0; | 249 | return 0; |
407 | } | 250 | } |
408 | 251 | ||
409 | static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) | 252 | int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) |
410 | { | 253 | { |
411 | int dsor_exp; | 254 | int dsor_exp; |
412 | u16 regval; | 255 | u16 regval; |
@@ -426,7 +269,7 @@ static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) | |||
426 | return 0; | 269 | return 0; |
427 | } | 270 | } |
428 | 271 | ||
429 | static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) | 272 | long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) |
430 | { | 273 | { |
431 | int dsor_exp = calc_dsor_exp(clk, rate); | 274 | int dsor_exp = calc_dsor_exp(clk, rate); |
432 | if (dsor_exp < 0) | 275 | if (dsor_exp < 0) |
@@ -436,7 +279,7 @@ static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) | |||
436 | return clk->parent->rate / (1 << dsor_exp); | 279 | return clk->parent->rate / (1 << dsor_exp); |
437 | } | 280 | } |
438 | 281 | ||
439 | static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) | 282 | int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) |
440 | { | 283 | { |
441 | int dsor_exp; | 284 | int dsor_exp; |
442 | u16 regval; | 285 | u16 regval; |
@@ -456,16 +299,19 @@ static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) | |||
456 | return 0; | 299 | return 0; |
457 | } | 300 | } |
458 | 301 | ||
459 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate) | 302 | long omap1_round_to_table_rate(struct clk *clk, unsigned long rate) |
460 | { | 303 | { |
461 | /* Find the highest supported frequency <= rate */ | 304 | /* Find the highest supported frequency <= rate */ |
462 | struct mpu_rate * ptr; | 305 | struct mpu_rate * ptr; |
463 | long highest_rate; | 306 | long highest_rate; |
307 | unsigned long ref_rate; | ||
308 | |||
309 | ref_rate = clk_get_rate(ck_ref_p); | ||
464 | 310 | ||
465 | highest_rate = -EINVAL; | 311 | highest_rate = -EINVAL; |
466 | 312 | ||
467 | for (ptr = rate_table; ptr->rate; ptr++) { | 313 | for (ptr = omap1_rate_table; ptr->rate; ptr++) { |
468 | if (ptr->xtal != ck_ref.rate) | 314 | if (ptr->xtal != ref_rate) |
469 | continue; | 315 | continue; |
470 | 316 | ||
471 | highest_rate = ptr->rate; | 317 | highest_rate = ptr->rate; |
@@ -500,8 +346,8 @@ static unsigned calc_ext_dsor(unsigned long rate) | |||
500 | return dsor; | 346 | return dsor; |
501 | } | 347 | } |
502 | 348 | ||
503 | /* Only needed on 1510 */ | 349 | /* XXX Only needed on 1510 */ |
504 | static int omap1_set_uart_rate(struct clk * clk, unsigned long rate) | 350 | int omap1_set_uart_rate(struct clk *clk, unsigned long rate) |
505 | { | 351 | { |
506 | unsigned int val; | 352 | unsigned int val; |
507 | 353 | ||
@@ -519,7 +365,7 @@ static int omap1_set_uart_rate(struct clk * clk, unsigned long rate) | |||
519 | } | 365 | } |
520 | 366 | ||
521 | /* External clock (MCLK & BCLK) functions */ | 367 | /* External clock (MCLK & BCLK) functions */ |
522 | static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) | 368 | int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate) |
523 | { | 369 | { |
524 | unsigned dsor; | 370 | unsigned dsor; |
525 | __u16 ratio_bits; | 371 | __u16 ratio_bits; |
@@ -537,7 +383,7 @@ static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) | |||
537 | return 0; | 383 | return 0; |
538 | } | 384 | } |
539 | 385 | ||
540 | static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) | 386 | int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) |
541 | { | 387 | { |
542 | u32 l; | 388 | u32 l; |
543 | int div; | 389 | int div; |
@@ -560,12 +406,12 @@ static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) | |||
560 | return 0; | 406 | return 0; |
561 | } | 407 | } |
562 | 408 | ||
563 | static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate) | 409 | long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate) |
564 | { | 410 | { |
565 | return 96000000 / calc_ext_dsor(rate); | 411 | return 96000000 / calc_ext_dsor(rate); |
566 | } | 412 | } |
567 | 413 | ||
568 | static void omap1_init_ext_clk(struct clk * clk) | 414 | void omap1_init_ext_clk(struct clk *clk) |
569 | { | 415 | { |
570 | unsigned dsor; | 416 | unsigned dsor; |
571 | __u16 ratio_bits; | 417 | __u16 ratio_bits; |
@@ -583,7 +429,7 @@ static void omap1_init_ext_clk(struct clk * clk) | |||
583 | clk-> rate = 96000000 / dsor; | 429 | clk-> rate = 96000000 / dsor; |
584 | } | 430 | } |
585 | 431 | ||
586 | static int omap1_clk_enable(struct clk *clk) | 432 | int omap1_clk_enable(struct clk *clk) |
587 | { | 433 | { |
588 | int ret = 0; | 434 | int ret = 0; |
589 | 435 | ||
@@ -611,7 +457,7 @@ err: | |||
611 | return ret; | 457 | return ret; |
612 | } | 458 | } |
613 | 459 | ||
614 | static void omap1_clk_disable(struct clk *clk) | 460 | void omap1_clk_disable(struct clk *clk) |
615 | { | 461 | { |
616 | if (clk->usecount > 0 && !(--clk->usecount)) { | 462 | if (clk->usecount > 0 && !(--clk->usecount)) { |
617 | clk->ops->disable(clk); | 463 | clk->ops->disable(clk); |
@@ -666,12 +512,70 @@ static void omap1_clk_disable_generic(struct clk *clk) | |||
666 | } | 512 | } |
667 | } | 513 | } |
668 | 514 | ||
669 | static const struct clkops clkops_generic = { | 515 | const struct clkops clkops_generic = { |
670 | .enable = &omap1_clk_enable_generic, | 516 | .enable = omap1_clk_enable_generic, |
671 | .disable = &omap1_clk_disable_generic, | 517 | .disable = omap1_clk_disable_generic, |
518 | }; | ||
519 | |||
520 | static int omap1_clk_enable_dsp_domain(struct clk *clk) | ||
521 | { | ||
522 | int retval; | ||
523 | |||
524 | retval = omap1_clk_enable(api_ck_p); | ||
525 | if (!retval) { | ||
526 | retval = omap1_clk_enable_generic(clk); | ||
527 | omap1_clk_disable(api_ck_p); | ||
528 | } | ||
529 | |||
530 | return retval; | ||
531 | } | ||
532 | |||
533 | static void omap1_clk_disable_dsp_domain(struct clk *clk) | ||
534 | { | ||
535 | if (omap1_clk_enable(api_ck_p) == 0) { | ||
536 | omap1_clk_disable_generic(clk); | ||
537 | omap1_clk_disable(api_ck_p); | ||
538 | } | ||
539 | } | ||
540 | |||
541 | const struct clkops clkops_dspck = { | ||
542 | .enable = omap1_clk_enable_dsp_domain, | ||
543 | .disable = omap1_clk_disable_dsp_domain, | ||
672 | }; | 544 | }; |
673 | 545 | ||
674 | static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) | 546 | static int omap1_clk_enable_uart_functional(struct clk *clk) |
547 | { | ||
548 | int ret; | ||
549 | struct uart_clk *uclk; | ||
550 | |||
551 | ret = omap1_clk_enable_generic(clk); | ||
552 | if (ret == 0) { | ||
553 | /* Set smart idle acknowledgement mode */ | ||
554 | uclk = (struct uart_clk *)clk; | ||
555 | omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8, | ||
556 | uclk->sysc_addr); | ||
557 | } | ||
558 | |||
559 | return ret; | ||
560 | } | ||
561 | |||
562 | static void omap1_clk_disable_uart_functional(struct clk *clk) | ||
563 | { | ||
564 | struct uart_clk *uclk; | ||
565 | |||
566 | /* Set force idle acknowledgement mode */ | ||
567 | uclk = (struct uart_clk *)clk; | ||
568 | omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr); | ||
569 | |||
570 | omap1_clk_disable_generic(clk); | ||
571 | } | ||
572 | |||
573 | const struct clkops clkops_uart = { | ||
574 | .enable = omap1_clk_enable_uart_functional, | ||
575 | .disable = omap1_clk_disable_uart_functional, | ||
576 | }; | ||
577 | |||
578 | long omap1_clk_round_rate(struct clk *clk, unsigned long rate) | ||
675 | { | 579 | { |
676 | if (clk->flags & RATE_FIXED) | 580 | if (clk->flags & RATE_FIXED) |
677 | return clk->rate; | 581 | return clk->rate; |
@@ -682,7 +586,7 @@ static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) | |||
682 | return clk->rate; | 586 | return clk->rate; |
683 | } | 587 | } |
684 | 588 | ||
685 | static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) | 589 | int omap1_clk_set_rate(struct clk *clk, unsigned long rate) |
686 | { | 590 | { |
687 | int ret = -EINVAL; | 591 | int ret = -EINVAL; |
688 | 592 | ||
@@ -697,7 +601,7 @@ static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) | |||
697 | 601 | ||
698 | #ifdef CONFIG_OMAP_RESET_CLOCKS | 602 | #ifdef CONFIG_OMAP_RESET_CLOCKS |
699 | 603 | ||
700 | static void __init omap1_clk_disable_unused(struct clk *clk) | 604 | void __init omap1_clk_disable_unused(struct clk *clk) |
701 | { | 605 | { |
702 | __u32 regval32; | 606 | __u32 regval32; |
703 | 607 | ||
@@ -723,168 +627,4 @@ static void __init omap1_clk_disable_unused(struct clk *clk) | |||
723 | printk(" done\n"); | 627 | printk(" done\n"); |
724 | } | 628 | } |
725 | 629 | ||
726 | #else | ||
727 | #define omap1_clk_disable_unused NULL | ||
728 | #endif | 630 | #endif |
729 | |||
730 | static struct clk_functions omap1_clk_functions = { | ||
731 | .clk_enable = omap1_clk_enable, | ||
732 | .clk_disable = omap1_clk_disable, | ||
733 | .clk_round_rate = omap1_clk_round_rate, | ||
734 | .clk_set_rate = omap1_clk_set_rate, | ||
735 | .clk_disable_unused = omap1_clk_disable_unused, | ||
736 | }; | ||
737 | |||
738 | int __init omap1_clk_init(void) | ||
739 | { | ||
740 | struct omap_clk *c; | ||
741 | const struct omap_clock_config *info; | ||
742 | int crystal_type = 0; /* Default 12 MHz */ | ||
743 | u32 reg, cpu_mask; | ||
744 | |||
745 | #ifdef CONFIG_DEBUG_LL | ||
746 | /* Resets some clocks that may be left on from bootloader, | ||
747 | * but leaves serial clocks on. | ||
748 | */ | ||
749 | omap_writel(0x3 << 29, MOD_CONF_CTRL_0); | ||
750 | #endif | ||
751 | |||
752 | /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ | ||
753 | reg = omap_readw(SOFT_REQ_REG) & (1 << 4); | ||
754 | omap_writew(reg, SOFT_REQ_REG); | ||
755 | if (!cpu_is_omap15xx()) | ||
756 | omap_writew(0, SOFT_REQ_REG2); | ||
757 | |||
758 | clk_init(&omap1_clk_functions); | ||
759 | |||
760 | /* By default all idlect1 clocks are allowed to idle */ | ||
761 | arm_idlect1_mask = ~0; | ||
762 | |||
763 | for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) | ||
764 | clk_preinit(c->lk.clk); | ||
765 | |||
766 | cpu_mask = 0; | ||
767 | if (cpu_is_omap16xx()) | ||
768 | cpu_mask |= CK_16XX; | ||
769 | if (cpu_is_omap1510()) | ||
770 | cpu_mask |= CK_1510; | ||
771 | if (cpu_is_omap7xx()) | ||
772 | cpu_mask |= CK_7XX; | ||
773 | if (cpu_is_omap310()) | ||
774 | cpu_mask |= CK_310; | ||
775 | |||
776 | for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) | ||
777 | if (c->cpu & cpu_mask) { | ||
778 | clkdev_add(&c->lk); | ||
779 | clk_register(c->lk.clk); | ||
780 | } | ||
781 | |||
782 | info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); | ||
783 | if (info != NULL) { | ||
784 | if (!cpu_is_omap15xx()) | ||
785 | crystal_type = info->system_clock_type; | ||
786 | } | ||
787 | |||
788 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | ||
789 | ck_ref.rate = 13000000; | ||
790 | #elif defined(CONFIG_ARCH_OMAP16XX) | ||
791 | if (crystal_type == 2) | ||
792 | ck_ref.rate = 19200000; | ||
793 | #endif | ||
794 | |||
795 | printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", | ||
796 | omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), | ||
797 | omap_readw(ARM_CKCTL)); | ||
798 | |||
799 | /* We want to be in syncronous scalable mode */ | ||
800 | omap_writew(0x1000, ARM_SYSST); | ||
801 | |||
802 | #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER | ||
803 | /* Use values set by bootloader. Determine PLL rate and recalculate | ||
804 | * dependent clocks as if kernel had changed PLL or divisors. | ||
805 | */ | ||
806 | { | ||
807 | unsigned pll_ctl_val = omap_readw(DPLL_CTL); | ||
808 | |||
809 | ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ | ||
810 | if (pll_ctl_val & 0x10) { | ||
811 | /* PLL enabled, apply multiplier and divisor */ | ||
812 | if (pll_ctl_val & 0xf80) | ||
813 | ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; | ||
814 | ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; | ||
815 | } else { | ||
816 | /* PLL disabled, apply bypass divisor */ | ||
817 | switch (pll_ctl_val & 0xc) { | ||
818 | case 0: | ||
819 | break; | ||
820 | case 0x4: | ||
821 | ck_dpll1.rate /= 2; | ||
822 | break; | ||
823 | default: | ||
824 | ck_dpll1.rate /= 4; | ||
825 | break; | ||
826 | } | ||
827 | } | ||
828 | } | ||
829 | #else | ||
830 | /* Find the highest supported frequency and enable it */ | ||
831 | if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { | ||
832 | printk(KERN_ERR "System frequencies not set. Check your config.\n"); | ||
833 | /* Guess sane values (60MHz) */ | ||
834 | omap_writew(0x2290, DPLL_CTL); | ||
835 | omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); | ||
836 | ck_dpll1.rate = 60000000; | ||
837 | } | ||
838 | #endif | ||
839 | propagate_rate(&ck_dpll1); | ||
840 | /* Cache rates for clocks connected to ck_ref (not dpll1) */ | ||
841 | propagate_rate(&ck_ref); | ||
842 | printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " | ||
843 | "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", | ||
844 | ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, | ||
845 | ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, | ||
846 | arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); | ||
847 | |||
848 | #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) | ||
849 | /* Select slicer output as OMAP input clock */ | ||
850 | omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL); | ||
851 | #endif | ||
852 | |||
853 | /* Amstrad Delta wants BCLK high when inactive */ | ||
854 | if (machine_is_ams_delta()) | ||
855 | omap_writel(omap_readl(ULPD_CLOCK_CTRL) | | ||
856 | (1 << SDW_MCLK_INV_BIT), | ||
857 | ULPD_CLOCK_CTRL); | ||
858 | |||
859 | /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ | ||
860 | /* (on 730, bit 13 must not be cleared) */ | ||
861 | if (cpu_is_omap7xx()) | ||
862 | omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); | ||
863 | else | ||
864 | omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); | ||
865 | |||
866 | /* Put DSP/MPUI into reset until needed */ | ||
867 | omap_writew(0, ARM_RSTCT1); | ||
868 | omap_writew(1, ARM_RSTCT2); | ||
869 | omap_writew(0x400, ARM_IDLECT1); | ||
870 | |||
871 | /* | ||
872 | * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) | ||
873 | * of the ARM_IDLECT2 register must be set to zero. The power-on | ||
874 | * default value of this bit is one. | ||
875 | */ | ||
876 | omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ | ||
877 | |||
878 | /* | ||
879 | * Only enable those clocks we will need, let the drivers | ||
880 | * enable other clocks as necessary | ||
881 | */ | ||
882 | clk_enable(&armper_ck.clk); | ||
883 | clk_enable(&armxor_ck.clk); | ||
884 | clk_enable(&armtim_ck.clk); /* This should be done by timer code */ | ||
885 | |||
886 | if (cpu_is_omap15xx()) | ||
887 | clk_enable(&arm_gpio_ck); | ||
888 | |||
889 | return 0; | ||
890 | } | ||
diff --git a/arch/arm/mach-omap1/clock.h b/arch/arm/mach-omap1/clock.h index 70195cad7610..a4190afb8614 100644 --- a/arch/arm/mach-omap1/clock.h +++ b/arch/arm/mach-omap1/clock.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/mach-omap1/clock.h | 2 | * linux/arch/arm/mach-omap1/clock.h |
3 | * | 3 | * |
4 | * Copyright (C) 2004 - 2005 Nokia corporation | 4 | * Copyright (C) 2004 - 2005, 2009 Nokia corporation |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | 5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> |
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | 6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc |
7 | * | 7 | * |
@@ -13,30 +13,36 @@ | |||
13 | #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H | 13 | #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H |
14 | #define __ARCH_ARM_MACH_OMAP1_CLOCK_H | 14 | #define __ARCH_ARM_MACH_OMAP1_CLOCK_H |
15 | 15 | ||
16 | static unsigned long omap1_ckctl_recalc(struct clk *clk); | 16 | #include <linux/clk.h> |
17 | static unsigned long omap1_watchdog_recalc(struct clk *clk); | 17 | |
18 | static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); | 18 | #include <plat/clock.h> |
19 | static unsigned long omap1_sossi_recalc(struct clk *clk); | 19 | |
20 | static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); | 20 | extern int __init omap1_clk_init(void); |
21 | static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); | 21 | extern int omap1_clk_enable(struct clk *clk); |
22 | static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); | 22 | extern void omap1_clk_disable(struct clk *clk); |
23 | static unsigned long omap1_uart_recalc(struct clk *clk); | 23 | extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate); |
24 | static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); | 24 | extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate); |
25 | static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); | 25 | extern unsigned long omap1_ckctl_recalc(struct clk *clk); |
26 | static void omap1_init_ext_clk(struct clk * clk); | 26 | extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); |
27 | static int omap1_select_table_rate(struct clk * clk, unsigned long rate); | 27 | extern unsigned long omap1_sossi_recalc(struct clk *clk); |
28 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); | 28 | extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); |
29 | 29 | extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate); | |
30 | static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); | 30 | extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate); |
31 | static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); | 31 | extern unsigned long omap1_uart_recalc(struct clk *clk); |
32 | 32 | extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate); | |
33 | struct mpu_rate { | 33 | extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate); |
34 | unsigned long rate; | 34 | extern void omap1_init_ext_clk(struct clk *clk); |
35 | unsigned long xtal; | 35 | extern int omap1_select_table_rate(struct clk *clk, unsigned long rate); |
36 | unsigned long pll_rate; | 36 | extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate); |
37 | __u16 ckctl_val; | 37 | extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); |
38 | __u16 dpllctl_val; | 38 | extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); |
39 | }; | 39 | extern unsigned long omap1_watchdog_recalc(struct clk *clk); |
40 | |||
41 | #ifdef CONFIG_OMAP_RESET_CLOCKS | ||
42 | extern void __init omap1_clk_disable_unused(struct clk *clk); | ||
43 | #else | ||
44 | #define omap1_clk_disable_unused NULL | ||
45 | #endif | ||
40 | 46 | ||
41 | struct uart_clk { | 47 | struct uart_clk { |
42 | struct clk clk; | 48 | struct clk clk; |
@@ -96,611 +102,12 @@ struct arm_idlect1_clk { | |||
96 | #define SOFT_REQ_REG 0xfffe0834 | 102 | #define SOFT_REQ_REG 0xfffe0834 |
97 | #define SOFT_REQ_REG2 0xfffe0880 | 103 | #define SOFT_REQ_REG2 0xfffe0880 |
98 | 104 | ||
99 | /*------------------------------------------------------------------------- | 105 | extern __u32 arm_idlect1_mask; |
100 | * Omap1 MPU rate table | 106 | extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; |
101 | *-------------------------------------------------------------------------*/ | ||
102 | static struct mpu_rate rate_table[] = { | ||
103 | /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL | ||
104 | * NOTE: Comment order here is different from bits in CKCTL value: | ||
105 | * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv | ||
106 | */ | ||
107 | #if defined(CONFIG_OMAP_ARM_216MHZ) | ||
108 | { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ | ||
109 | #endif | ||
110 | #if defined(CONFIG_OMAP_ARM_195MHZ) | ||
111 | { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ | ||
112 | #endif | ||
113 | #if defined(CONFIG_OMAP_ARM_192MHZ) | ||
114 | { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ | ||
115 | { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ | ||
116 | { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ | ||
117 | { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ | ||
118 | { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ | ||
119 | #endif | ||
120 | #if defined(CONFIG_OMAP_ARM_182MHZ) | ||
121 | { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ | ||
122 | #endif | ||
123 | #if defined(CONFIG_OMAP_ARM_168MHZ) | ||
124 | { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ | ||
125 | #endif | ||
126 | #if defined(CONFIG_OMAP_ARM_150MHZ) | ||
127 | { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ | ||
128 | #endif | ||
129 | #if defined(CONFIG_OMAP_ARM_120MHZ) | ||
130 | { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ | ||
131 | #endif | ||
132 | #if defined(CONFIG_OMAP_ARM_96MHZ) | ||
133 | { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ | ||
134 | #endif | ||
135 | #if defined(CONFIG_OMAP_ARM_60MHZ) | ||
136 | { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ | ||
137 | #endif | ||
138 | #if defined(CONFIG_OMAP_ARM_30MHZ) | ||
139 | { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ | ||
140 | #endif | ||
141 | { 0, 0, 0, 0, 0 }, | ||
142 | }; | ||
143 | |||
144 | /*------------------------------------------------------------------------- | ||
145 | * Omap1 clocks | ||
146 | *-------------------------------------------------------------------------*/ | ||
147 | 107 | ||
148 | static struct clk ck_ref = { | 108 | extern const struct clkops clkops_dspck; |
149 | .name = "ck_ref", | 109 | extern const struct clkops clkops_dummy; |
150 | .ops = &clkops_null, | 110 | extern const struct clkops clkops_uart; |
151 | .rate = 12000000, | 111 | extern const struct clkops clkops_generic; |
152 | }; | ||
153 | |||
154 | static struct clk ck_dpll1 = { | ||
155 | .name = "ck_dpll1", | ||
156 | .ops = &clkops_null, | ||
157 | .parent = &ck_ref, | ||
158 | }; | ||
159 | |||
160 | /* | ||
161 | * FIXME: This clock seems to be necessary but no-one has asked for its | ||
162 | * activation. [ FIX: SoSSI, SSR ] | ||
163 | */ | ||
164 | static struct arm_idlect1_clk ck_dpll1out = { | ||
165 | .clk = { | ||
166 | .name = "ck_dpll1out", | ||
167 | .ops = &clkops_generic, | ||
168 | .parent = &ck_dpll1, | ||
169 | .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT | | ||
170 | ENABLE_ON_INIT, | ||
171 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
172 | .enable_bit = EN_CKOUT_ARM, | ||
173 | .recalc = &followparent_recalc, | ||
174 | }, | ||
175 | .idlect_shift = 12, | ||
176 | }; | ||
177 | |||
178 | static struct clk sossi_ck = { | ||
179 | .name = "ck_sossi", | ||
180 | .ops = &clkops_generic, | ||
181 | .parent = &ck_dpll1out.clk, | ||
182 | .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, | ||
183 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), | ||
184 | .enable_bit = 16, | ||
185 | .recalc = &omap1_sossi_recalc, | ||
186 | .set_rate = &omap1_set_sossi_rate, | ||
187 | }; | ||
188 | |||
189 | static struct clk arm_ck = { | ||
190 | .name = "arm_ck", | ||
191 | .ops = &clkops_null, | ||
192 | .parent = &ck_dpll1, | ||
193 | .rate_offset = CKCTL_ARMDIV_OFFSET, | ||
194 | .recalc = &omap1_ckctl_recalc, | ||
195 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
196 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
197 | }; | ||
198 | |||
199 | static struct arm_idlect1_clk armper_ck = { | ||
200 | .clk = { | ||
201 | .name = "armper_ck", | ||
202 | .ops = &clkops_generic, | ||
203 | .parent = &ck_dpll1, | ||
204 | .flags = CLOCK_IDLE_CONTROL, | ||
205 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
206 | .enable_bit = EN_PERCK, | ||
207 | .rate_offset = CKCTL_PERDIV_OFFSET, | ||
208 | .recalc = &omap1_ckctl_recalc, | ||
209 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
210 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
211 | }, | ||
212 | .idlect_shift = 2, | ||
213 | }; | ||
214 | |||
215 | /* | ||
216 | * FIXME: This clock seems to be necessary but no-one has asked for its | ||
217 | * activation. [ GPIO code for 1510 ] | ||
218 | */ | ||
219 | static struct clk arm_gpio_ck = { | ||
220 | .name = "arm_gpio_ck", | ||
221 | .ops = &clkops_generic, | ||
222 | .parent = &ck_dpll1, | ||
223 | .flags = ENABLE_ON_INIT, | ||
224 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
225 | .enable_bit = EN_GPIOCK, | ||
226 | .recalc = &followparent_recalc, | ||
227 | }; | ||
228 | |||
229 | static struct arm_idlect1_clk armxor_ck = { | ||
230 | .clk = { | ||
231 | .name = "armxor_ck", | ||
232 | .ops = &clkops_generic, | ||
233 | .parent = &ck_ref, | ||
234 | .flags = CLOCK_IDLE_CONTROL, | ||
235 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
236 | .enable_bit = EN_XORPCK, | ||
237 | .recalc = &followparent_recalc, | ||
238 | }, | ||
239 | .idlect_shift = 1, | ||
240 | }; | ||
241 | |||
242 | static struct arm_idlect1_clk armtim_ck = { | ||
243 | .clk = { | ||
244 | .name = "armtim_ck", | ||
245 | .ops = &clkops_generic, | ||
246 | .parent = &ck_ref, | ||
247 | .flags = CLOCK_IDLE_CONTROL, | ||
248 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
249 | .enable_bit = EN_TIMCK, | ||
250 | .recalc = &followparent_recalc, | ||
251 | }, | ||
252 | .idlect_shift = 9, | ||
253 | }; | ||
254 | |||
255 | static struct arm_idlect1_clk armwdt_ck = { | ||
256 | .clk = { | ||
257 | .name = "armwdt_ck", | ||
258 | .ops = &clkops_generic, | ||
259 | .parent = &ck_ref, | ||
260 | .flags = CLOCK_IDLE_CONTROL, | ||
261 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
262 | .enable_bit = EN_WDTCK, | ||
263 | .recalc = &omap1_watchdog_recalc, | ||
264 | }, | ||
265 | .idlect_shift = 0, | ||
266 | }; | ||
267 | |||
268 | static struct clk arminth_ck16xx = { | ||
269 | .name = "arminth_ck", | ||
270 | .ops = &clkops_null, | ||
271 | .parent = &arm_ck, | ||
272 | .recalc = &followparent_recalc, | ||
273 | /* Note: On 16xx the frequency can be divided by 2 by programming | ||
274 | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 | ||
275 | * | ||
276 | * 1510 version is in TC clocks. | ||
277 | */ | ||
278 | }; | ||
279 | |||
280 | static struct clk dsp_ck = { | ||
281 | .name = "dsp_ck", | ||
282 | .ops = &clkops_generic, | ||
283 | .parent = &ck_dpll1, | ||
284 | .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), | ||
285 | .enable_bit = EN_DSPCK, | ||
286 | .rate_offset = CKCTL_DSPDIV_OFFSET, | ||
287 | .recalc = &omap1_ckctl_recalc, | ||
288 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
289 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
290 | }; | ||
291 | |||
292 | static struct clk dspmmu_ck = { | ||
293 | .name = "dspmmu_ck", | ||
294 | .ops = &clkops_null, | ||
295 | .parent = &ck_dpll1, | ||
296 | .rate_offset = CKCTL_DSPMMUDIV_OFFSET, | ||
297 | .recalc = &omap1_ckctl_recalc, | ||
298 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
299 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
300 | }; | ||
301 | |||
302 | static struct clk dspper_ck = { | ||
303 | .name = "dspper_ck", | ||
304 | .ops = &clkops_dspck, | ||
305 | .parent = &ck_dpll1, | ||
306 | .enable_reg = DSP_IDLECT2, | ||
307 | .enable_bit = EN_PERCK, | ||
308 | .rate_offset = CKCTL_PERDIV_OFFSET, | ||
309 | .recalc = &omap1_ckctl_recalc_dsp_domain, | ||
310 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
311 | .set_rate = &omap1_clk_set_rate_dsp_domain, | ||
312 | }; | ||
313 | |||
314 | static struct clk dspxor_ck = { | ||
315 | .name = "dspxor_ck", | ||
316 | .ops = &clkops_dspck, | ||
317 | .parent = &ck_ref, | ||
318 | .enable_reg = DSP_IDLECT2, | ||
319 | .enable_bit = EN_XORPCK, | ||
320 | .recalc = &followparent_recalc, | ||
321 | }; | ||
322 | |||
323 | static struct clk dsptim_ck = { | ||
324 | .name = "dsptim_ck", | ||
325 | .ops = &clkops_dspck, | ||
326 | .parent = &ck_ref, | ||
327 | .enable_reg = DSP_IDLECT2, | ||
328 | .enable_bit = EN_DSPTIMCK, | ||
329 | .recalc = &followparent_recalc, | ||
330 | }; | ||
331 | |||
332 | /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ | ||
333 | static struct arm_idlect1_clk tc_ck = { | ||
334 | .clk = { | ||
335 | .name = "tc_ck", | ||
336 | .ops = &clkops_null, | ||
337 | .parent = &ck_dpll1, | ||
338 | .flags = CLOCK_IDLE_CONTROL, | ||
339 | .rate_offset = CKCTL_TCDIV_OFFSET, | ||
340 | .recalc = &omap1_ckctl_recalc, | ||
341 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
342 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
343 | }, | ||
344 | .idlect_shift = 6, | ||
345 | }; | ||
346 | |||
347 | static struct clk arminth_ck1510 = { | ||
348 | .name = "arminth_ck", | ||
349 | .ops = &clkops_null, | ||
350 | .parent = &tc_ck.clk, | ||
351 | .recalc = &followparent_recalc, | ||
352 | /* Note: On 1510 the frequency follows TC_CK | ||
353 | * | ||
354 | * 16xx version is in MPU clocks. | ||
355 | */ | ||
356 | }; | ||
357 | |||
358 | static struct clk tipb_ck = { | ||
359 | /* No-idle controlled by "tc_ck" */ | ||
360 | .name = "tipb_ck", | ||
361 | .ops = &clkops_null, | ||
362 | .parent = &tc_ck.clk, | ||
363 | .recalc = &followparent_recalc, | ||
364 | }; | ||
365 | |||
366 | static struct clk l3_ocpi_ck = { | ||
367 | /* No-idle controlled by "tc_ck" */ | ||
368 | .name = "l3_ocpi_ck", | ||
369 | .ops = &clkops_generic, | ||
370 | .parent = &tc_ck.clk, | ||
371 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | ||
372 | .enable_bit = EN_OCPI_CK, | ||
373 | .recalc = &followparent_recalc, | ||
374 | }; | ||
375 | |||
376 | static struct clk tc1_ck = { | ||
377 | .name = "tc1_ck", | ||
378 | .ops = &clkops_generic, | ||
379 | .parent = &tc_ck.clk, | ||
380 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | ||
381 | .enable_bit = EN_TC1_CK, | ||
382 | .recalc = &followparent_recalc, | ||
383 | }; | ||
384 | |||
385 | /* | ||
386 | * FIXME: This clock seems to be necessary but no-one has asked for its | ||
387 | * activation. [ pm.c (SRAM), CCP, Camera ] | ||
388 | */ | ||
389 | static struct clk tc2_ck = { | ||
390 | .name = "tc2_ck", | ||
391 | .ops = &clkops_generic, | ||
392 | .parent = &tc_ck.clk, | ||
393 | .flags = ENABLE_ON_INIT, | ||
394 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | ||
395 | .enable_bit = EN_TC2_CK, | ||
396 | .recalc = &followparent_recalc, | ||
397 | }; | ||
398 | |||
399 | static struct clk dma_ck = { | ||
400 | /* No-idle controlled by "tc_ck" */ | ||
401 | .name = "dma_ck", | ||
402 | .ops = &clkops_null, | ||
403 | .parent = &tc_ck.clk, | ||
404 | .recalc = &followparent_recalc, | ||
405 | }; | ||
406 | |||
407 | static struct clk dma_lcdfree_ck = { | ||
408 | .name = "dma_lcdfree_ck", | ||
409 | .ops = &clkops_null, | ||
410 | .parent = &tc_ck.clk, | ||
411 | .recalc = &followparent_recalc, | ||
412 | }; | ||
413 | |||
414 | static struct arm_idlect1_clk api_ck = { | ||
415 | .clk = { | ||
416 | .name = "api_ck", | ||
417 | .ops = &clkops_generic, | ||
418 | .parent = &tc_ck.clk, | ||
419 | .flags = CLOCK_IDLE_CONTROL, | ||
420 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
421 | .enable_bit = EN_APICK, | ||
422 | .recalc = &followparent_recalc, | ||
423 | }, | ||
424 | .idlect_shift = 8, | ||
425 | }; | ||
426 | |||
427 | static struct arm_idlect1_clk lb_ck = { | ||
428 | .clk = { | ||
429 | .name = "lb_ck", | ||
430 | .ops = &clkops_generic, | ||
431 | .parent = &tc_ck.clk, | ||
432 | .flags = CLOCK_IDLE_CONTROL, | ||
433 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
434 | .enable_bit = EN_LBCK, | ||
435 | .recalc = &followparent_recalc, | ||
436 | }, | ||
437 | .idlect_shift = 4, | ||
438 | }; | ||
439 | |||
440 | static struct clk rhea1_ck = { | ||
441 | .name = "rhea1_ck", | ||
442 | .ops = &clkops_null, | ||
443 | .parent = &tc_ck.clk, | ||
444 | .recalc = &followparent_recalc, | ||
445 | }; | ||
446 | |||
447 | static struct clk rhea2_ck = { | ||
448 | .name = "rhea2_ck", | ||
449 | .ops = &clkops_null, | ||
450 | .parent = &tc_ck.clk, | ||
451 | .recalc = &followparent_recalc, | ||
452 | }; | ||
453 | |||
454 | static struct clk lcd_ck_16xx = { | ||
455 | .name = "lcd_ck", | ||
456 | .ops = &clkops_generic, | ||
457 | .parent = &ck_dpll1, | ||
458 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
459 | .enable_bit = EN_LCDCK, | ||
460 | .rate_offset = CKCTL_LCDDIV_OFFSET, | ||
461 | .recalc = &omap1_ckctl_recalc, | ||
462 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
463 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
464 | }; | ||
465 | |||
466 | static struct arm_idlect1_clk lcd_ck_1510 = { | ||
467 | .clk = { | ||
468 | .name = "lcd_ck", | ||
469 | .ops = &clkops_generic, | ||
470 | .parent = &ck_dpll1, | ||
471 | .flags = CLOCK_IDLE_CONTROL, | ||
472 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
473 | .enable_bit = EN_LCDCK, | ||
474 | .rate_offset = CKCTL_LCDDIV_OFFSET, | ||
475 | .recalc = &omap1_ckctl_recalc, | ||
476 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
477 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
478 | }, | ||
479 | .idlect_shift = 3, | ||
480 | }; | ||
481 | |||
482 | static struct clk uart1_1510 = { | ||
483 | .name = "uart1_ck", | ||
484 | .ops = &clkops_null, | ||
485 | /* Direct from ULPD, no real parent */ | ||
486 | .parent = &armper_ck.clk, | ||
487 | .rate = 12000000, | ||
488 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
489 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
490 | .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ | ||
491 | .set_rate = &omap1_set_uart_rate, | ||
492 | .recalc = &omap1_uart_recalc, | ||
493 | }; | ||
494 | |||
495 | static struct uart_clk uart1_16xx = { | ||
496 | .clk = { | ||
497 | .name = "uart1_ck", | ||
498 | .ops = &clkops_uart, | ||
499 | /* Direct from ULPD, no real parent */ | ||
500 | .parent = &armper_ck.clk, | ||
501 | .rate = 48000000, | ||
502 | .flags = RATE_FIXED | ENABLE_REG_32BIT | | ||
503 | CLOCK_NO_IDLE_PARENT, | ||
504 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
505 | .enable_bit = 29, | ||
506 | }, | ||
507 | .sysc_addr = 0xfffb0054, | ||
508 | }; | ||
509 | |||
510 | static struct clk uart2_ck = { | ||
511 | .name = "uart2_ck", | ||
512 | .ops = &clkops_null, | ||
513 | /* Direct from ULPD, no real parent */ | ||
514 | .parent = &armper_ck.clk, | ||
515 | .rate = 12000000, | ||
516 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
517 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
518 | .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ | ||
519 | .set_rate = &omap1_set_uart_rate, | ||
520 | .recalc = &omap1_uart_recalc, | ||
521 | }; | ||
522 | |||
523 | static struct clk uart3_1510 = { | ||
524 | .name = "uart3_ck", | ||
525 | .ops = &clkops_null, | ||
526 | /* Direct from ULPD, no real parent */ | ||
527 | .parent = &armper_ck.clk, | ||
528 | .rate = 12000000, | ||
529 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
530 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
531 | .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ | ||
532 | .set_rate = &omap1_set_uart_rate, | ||
533 | .recalc = &omap1_uart_recalc, | ||
534 | }; | ||
535 | |||
536 | static struct uart_clk uart3_16xx = { | ||
537 | .clk = { | ||
538 | .name = "uart3_ck", | ||
539 | .ops = &clkops_uart, | ||
540 | /* Direct from ULPD, no real parent */ | ||
541 | .parent = &armper_ck.clk, | ||
542 | .rate = 48000000, | ||
543 | .flags = RATE_FIXED | ENABLE_REG_32BIT | | ||
544 | CLOCK_NO_IDLE_PARENT, | ||
545 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
546 | .enable_bit = 31, | ||
547 | }, | ||
548 | .sysc_addr = 0xfffb9854, | ||
549 | }; | ||
550 | |||
551 | static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ | ||
552 | .name = "usb_clko", | ||
553 | .ops = &clkops_generic, | ||
554 | /* Direct from ULPD, no parent */ | ||
555 | .rate = 6000000, | ||
556 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | ||
557 | .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), | ||
558 | .enable_bit = USB_MCLK_EN_BIT, | ||
559 | }; | ||
560 | |||
561 | static struct clk usb_hhc_ck1510 = { | ||
562 | .name = "usb_hhc_ck", | ||
563 | .ops = &clkops_generic, | ||
564 | /* Direct from ULPD, no parent */ | ||
565 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ | ||
566 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | ||
567 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
568 | .enable_bit = USB_HOST_HHC_UHOST_EN, | ||
569 | }; | ||
570 | |||
571 | static struct clk usb_hhc_ck16xx = { | ||
572 | .name = "usb_hhc_ck", | ||
573 | .ops = &clkops_generic, | ||
574 | /* Direct from ULPD, no parent */ | ||
575 | .rate = 48000000, | ||
576 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ | ||
577 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | ||
578 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ | ||
579 | .enable_bit = 8 /* UHOST_EN */, | ||
580 | }; | ||
581 | |||
582 | static struct clk usb_dc_ck = { | ||
583 | .name = "usb_dc_ck", | ||
584 | .ops = &clkops_generic, | ||
585 | /* Direct from ULPD, no parent */ | ||
586 | .rate = 48000000, | ||
587 | .flags = RATE_FIXED, | ||
588 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
589 | .enable_bit = 4, | ||
590 | }; | ||
591 | |||
592 | static struct clk usb_dc_ck7xx = { | ||
593 | .name = "usb_dc_ck", | ||
594 | .ops = &clkops_generic, | ||
595 | /* Direct from ULPD, no parent */ | ||
596 | .rate = 48000000, | ||
597 | .flags = RATE_FIXED, | ||
598 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
599 | .enable_bit = 8, | ||
600 | }; | ||
601 | |||
602 | static struct clk mclk_1510 = { | ||
603 | .name = "mclk", | ||
604 | .ops = &clkops_generic, | ||
605 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | ||
606 | .rate = 12000000, | ||
607 | .flags = RATE_FIXED, | ||
608 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
609 | .enable_bit = 6, | ||
610 | }; | ||
611 | |||
612 | static struct clk mclk_16xx = { | ||
613 | .name = "mclk", | ||
614 | .ops = &clkops_generic, | ||
615 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | ||
616 | .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), | ||
617 | .enable_bit = COM_ULPD_PLL_CLK_REQ, | ||
618 | .set_rate = &omap1_set_ext_clk_rate, | ||
619 | .round_rate = &omap1_round_ext_clk_rate, | ||
620 | .init = &omap1_init_ext_clk, | ||
621 | }; | ||
622 | |||
623 | static struct clk bclk_1510 = { | ||
624 | .name = "bclk", | ||
625 | .ops = &clkops_generic, | ||
626 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | ||
627 | .rate = 12000000, | ||
628 | .flags = RATE_FIXED, | ||
629 | }; | ||
630 | |||
631 | static struct clk bclk_16xx = { | ||
632 | .name = "bclk", | ||
633 | .ops = &clkops_generic, | ||
634 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | ||
635 | .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), | ||
636 | .enable_bit = SWD_ULPD_PLL_CLK_REQ, | ||
637 | .set_rate = &omap1_set_ext_clk_rate, | ||
638 | .round_rate = &omap1_round_ext_clk_rate, | ||
639 | .init = &omap1_init_ext_clk, | ||
640 | }; | ||
641 | |||
642 | static struct clk mmc1_ck = { | ||
643 | .name = "mmc_ck", | ||
644 | .ops = &clkops_generic, | ||
645 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | ||
646 | .parent = &armper_ck.clk, | ||
647 | .rate = 48000000, | ||
648 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
649 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
650 | .enable_bit = 23, | ||
651 | }; | ||
652 | |||
653 | static struct clk mmc2_ck = { | ||
654 | .name = "mmc_ck", | ||
655 | .id = 1, | ||
656 | .ops = &clkops_generic, | ||
657 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | ||
658 | .parent = &armper_ck.clk, | ||
659 | .rate = 48000000, | ||
660 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
661 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
662 | .enable_bit = 20, | ||
663 | }; | ||
664 | |||
665 | static struct clk mmc3_ck = { | ||
666 | .name = "mmc_ck", | ||
667 | .id = 2, | ||
668 | .ops = &clkops_generic, | ||
669 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | ||
670 | .parent = &armper_ck.clk, | ||
671 | .rate = 48000000, | ||
672 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
673 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
674 | .enable_bit = 12, | ||
675 | }; | ||
676 | |||
677 | static struct clk virtual_ck_mpu = { | ||
678 | .name = "mpu", | ||
679 | .ops = &clkops_null, | ||
680 | .parent = &arm_ck, /* Is smarter alias for */ | ||
681 | .recalc = &followparent_recalc, | ||
682 | .set_rate = &omap1_select_table_rate, | ||
683 | .round_rate = &omap1_round_to_table_rate, | ||
684 | }; | ||
685 | |||
686 | /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK | ||
687 | remains active during MPU idle whenever this is enabled */ | ||
688 | static struct clk i2c_fck = { | ||
689 | .name = "i2c_fck", | ||
690 | .id = 1, | ||
691 | .ops = &clkops_null, | ||
692 | .flags = CLOCK_NO_IDLE_PARENT, | ||
693 | .parent = &armxor_ck.clk, | ||
694 | .recalc = &followparent_recalc, | ||
695 | }; | ||
696 | |||
697 | static struct clk i2c_ick = { | ||
698 | .name = "i2c_ick", | ||
699 | .id = 1, | ||
700 | .ops = &clkops_null, | ||
701 | .flags = CLOCK_NO_IDLE_PARENT, | ||
702 | .parent = &armper_ck.clk, | ||
703 | .recalc = &followparent_recalc, | ||
704 | }; | ||
705 | 112 | ||
706 | #endif | 113 | #endif |
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c new file mode 100644 index 000000000000..cf5f017b392c --- /dev/null +++ b/arch/arm/mach-omap1/clock_data.c | |||
@@ -0,0 +1,843 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-omap1/clock_data.c | ||
3 | * | ||
4 | * Copyright (C) 2004 - 2005, 2009 Nokia corporation | ||
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | ||
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/clk.h> | ||
15 | #include <linux/io.h> | ||
16 | |||
17 | #include <asm/mach-types.h> /* for machine_is_* */ | ||
18 | |||
19 | #include <plat/clock.h> | ||
20 | #include <plat/cpu.h> | ||
21 | #include <plat/clkdev_omap.h> | ||
22 | #include <plat/usb.h> /* for OTG_BASE */ | ||
23 | |||
24 | #include "clock.h" | ||
25 | |||
26 | /*------------------------------------------------------------------------ | ||
27 | * Omap1 clocks | ||
28 | *-------------------------------------------------------------------------*/ | ||
29 | |||
30 | /* XXX is this necessary? */ | ||
31 | static struct clk dummy_ck = { | ||
32 | .name = "dummy", | ||
33 | .ops = &clkops_dummy, | ||
34 | .flags = RATE_FIXED, | ||
35 | }; | ||
36 | |||
37 | static struct clk ck_ref = { | ||
38 | .name = "ck_ref", | ||
39 | .ops = &clkops_null, | ||
40 | .rate = 12000000, | ||
41 | }; | ||
42 | |||
43 | static struct clk ck_dpll1 = { | ||
44 | .name = "ck_dpll1", | ||
45 | .ops = &clkops_null, | ||
46 | .parent = &ck_ref, | ||
47 | }; | ||
48 | |||
49 | /* | ||
50 | * FIXME: This clock seems to be necessary but no-one has asked for its | ||
51 | * activation. [ FIX: SoSSI, SSR ] | ||
52 | */ | ||
53 | static struct arm_idlect1_clk ck_dpll1out = { | ||
54 | .clk = { | ||
55 | .name = "ck_dpll1out", | ||
56 | .ops = &clkops_generic, | ||
57 | .parent = &ck_dpll1, | ||
58 | .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT | | ||
59 | ENABLE_ON_INIT, | ||
60 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
61 | .enable_bit = EN_CKOUT_ARM, | ||
62 | .recalc = &followparent_recalc, | ||
63 | }, | ||
64 | .idlect_shift = 12, | ||
65 | }; | ||
66 | |||
67 | static struct clk sossi_ck = { | ||
68 | .name = "ck_sossi", | ||
69 | .ops = &clkops_generic, | ||
70 | .parent = &ck_dpll1out.clk, | ||
71 | .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, | ||
72 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), | ||
73 | .enable_bit = 16, | ||
74 | .recalc = &omap1_sossi_recalc, | ||
75 | .set_rate = &omap1_set_sossi_rate, | ||
76 | }; | ||
77 | |||
78 | static struct clk arm_ck = { | ||
79 | .name = "arm_ck", | ||
80 | .ops = &clkops_null, | ||
81 | .parent = &ck_dpll1, | ||
82 | .rate_offset = CKCTL_ARMDIV_OFFSET, | ||
83 | .recalc = &omap1_ckctl_recalc, | ||
84 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
85 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
86 | }; | ||
87 | |||
88 | static struct arm_idlect1_clk armper_ck = { | ||
89 | .clk = { | ||
90 | .name = "armper_ck", | ||
91 | .ops = &clkops_generic, | ||
92 | .parent = &ck_dpll1, | ||
93 | .flags = CLOCK_IDLE_CONTROL, | ||
94 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
95 | .enable_bit = EN_PERCK, | ||
96 | .rate_offset = CKCTL_PERDIV_OFFSET, | ||
97 | .recalc = &omap1_ckctl_recalc, | ||
98 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
99 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
100 | }, | ||
101 | .idlect_shift = 2, | ||
102 | }; | ||
103 | |||
104 | /* | ||
105 | * FIXME: This clock seems to be necessary but no-one has asked for its | ||
106 | * activation. [ GPIO code for 1510 ] | ||
107 | */ | ||
108 | static struct clk arm_gpio_ck = { | ||
109 | .name = "arm_gpio_ck", | ||
110 | .ops = &clkops_generic, | ||
111 | .parent = &ck_dpll1, | ||
112 | .flags = ENABLE_ON_INIT, | ||
113 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
114 | .enable_bit = EN_GPIOCK, | ||
115 | .recalc = &followparent_recalc, | ||
116 | }; | ||
117 | |||
118 | static struct arm_idlect1_clk armxor_ck = { | ||
119 | .clk = { | ||
120 | .name = "armxor_ck", | ||
121 | .ops = &clkops_generic, | ||
122 | .parent = &ck_ref, | ||
123 | .flags = CLOCK_IDLE_CONTROL, | ||
124 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
125 | .enable_bit = EN_XORPCK, | ||
126 | .recalc = &followparent_recalc, | ||
127 | }, | ||
128 | .idlect_shift = 1, | ||
129 | }; | ||
130 | |||
131 | static struct arm_idlect1_clk armtim_ck = { | ||
132 | .clk = { | ||
133 | .name = "armtim_ck", | ||
134 | .ops = &clkops_generic, | ||
135 | .parent = &ck_ref, | ||
136 | .flags = CLOCK_IDLE_CONTROL, | ||
137 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
138 | .enable_bit = EN_TIMCK, | ||
139 | .recalc = &followparent_recalc, | ||
140 | }, | ||
141 | .idlect_shift = 9, | ||
142 | }; | ||
143 | |||
144 | static struct arm_idlect1_clk armwdt_ck = { | ||
145 | .clk = { | ||
146 | .name = "armwdt_ck", | ||
147 | .ops = &clkops_generic, | ||
148 | .parent = &ck_ref, | ||
149 | .flags = CLOCK_IDLE_CONTROL, | ||
150 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
151 | .enable_bit = EN_WDTCK, | ||
152 | .recalc = &omap1_watchdog_recalc, | ||
153 | }, | ||
154 | .idlect_shift = 0, | ||
155 | }; | ||
156 | |||
157 | static struct clk arminth_ck16xx = { | ||
158 | .name = "arminth_ck", | ||
159 | .ops = &clkops_null, | ||
160 | .parent = &arm_ck, | ||
161 | .recalc = &followparent_recalc, | ||
162 | /* Note: On 16xx the frequency can be divided by 2 by programming | ||
163 | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 | ||
164 | * | ||
165 | * 1510 version is in TC clocks. | ||
166 | */ | ||
167 | }; | ||
168 | |||
169 | static struct clk dsp_ck = { | ||
170 | .name = "dsp_ck", | ||
171 | .ops = &clkops_generic, | ||
172 | .parent = &ck_dpll1, | ||
173 | .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), | ||
174 | .enable_bit = EN_DSPCK, | ||
175 | .rate_offset = CKCTL_DSPDIV_OFFSET, | ||
176 | .recalc = &omap1_ckctl_recalc, | ||
177 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
178 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
179 | }; | ||
180 | |||
181 | static struct clk dspmmu_ck = { | ||
182 | .name = "dspmmu_ck", | ||
183 | .ops = &clkops_null, | ||
184 | .parent = &ck_dpll1, | ||
185 | .rate_offset = CKCTL_DSPMMUDIV_OFFSET, | ||
186 | .recalc = &omap1_ckctl_recalc, | ||
187 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
188 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
189 | }; | ||
190 | |||
191 | static struct clk dspper_ck = { | ||
192 | .name = "dspper_ck", | ||
193 | .ops = &clkops_dspck, | ||
194 | .parent = &ck_dpll1, | ||
195 | .enable_reg = DSP_IDLECT2, | ||
196 | .enable_bit = EN_PERCK, | ||
197 | .rate_offset = CKCTL_PERDIV_OFFSET, | ||
198 | .recalc = &omap1_ckctl_recalc_dsp_domain, | ||
199 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
200 | .set_rate = &omap1_clk_set_rate_dsp_domain, | ||
201 | }; | ||
202 | |||
203 | static struct clk dspxor_ck = { | ||
204 | .name = "dspxor_ck", | ||
205 | .ops = &clkops_dspck, | ||
206 | .parent = &ck_ref, | ||
207 | .enable_reg = DSP_IDLECT2, | ||
208 | .enable_bit = EN_XORPCK, | ||
209 | .recalc = &followparent_recalc, | ||
210 | }; | ||
211 | |||
212 | static struct clk dsptim_ck = { | ||
213 | .name = "dsptim_ck", | ||
214 | .ops = &clkops_dspck, | ||
215 | .parent = &ck_ref, | ||
216 | .enable_reg = DSP_IDLECT2, | ||
217 | .enable_bit = EN_DSPTIMCK, | ||
218 | .recalc = &followparent_recalc, | ||
219 | }; | ||
220 | |||
221 | /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ | ||
222 | static struct arm_idlect1_clk tc_ck = { | ||
223 | .clk = { | ||
224 | .name = "tc_ck", | ||
225 | .ops = &clkops_null, | ||
226 | .parent = &ck_dpll1, | ||
227 | .flags = CLOCK_IDLE_CONTROL, | ||
228 | .rate_offset = CKCTL_TCDIV_OFFSET, | ||
229 | .recalc = &omap1_ckctl_recalc, | ||
230 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
231 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
232 | }, | ||
233 | .idlect_shift = 6, | ||
234 | }; | ||
235 | |||
236 | static struct clk arminth_ck1510 = { | ||
237 | .name = "arminth_ck", | ||
238 | .ops = &clkops_null, | ||
239 | .parent = &tc_ck.clk, | ||
240 | .recalc = &followparent_recalc, | ||
241 | /* Note: On 1510 the frequency follows TC_CK | ||
242 | * | ||
243 | * 16xx version is in MPU clocks. | ||
244 | */ | ||
245 | }; | ||
246 | |||
247 | static struct clk tipb_ck = { | ||
248 | /* No-idle controlled by "tc_ck" */ | ||
249 | .name = "tipb_ck", | ||
250 | .ops = &clkops_null, | ||
251 | .parent = &tc_ck.clk, | ||
252 | .recalc = &followparent_recalc, | ||
253 | }; | ||
254 | |||
255 | static struct clk l3_ocpi_ck = { | ||
256 | /* No-idle controlled by "tc_ck" */ | ||
257 | .name = "l3_ocpi_ck", | ||
258 | .ops = &clkops_generic, | ||
259 | .parent = &tc_ck.clk, | ||
260 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | ||
261 | .enable_bit = EN_OCPI_CK, | ||
262 | .recalc = &followparent_recalc, | ||
263 | }; | ||
264 | |||
265 | static struct clk tc1_ck = { | ||
266 | .name = "tc1_ck", | ||
267 | .ops = &clkops_generic, | ||
268 | .parent = &tc_ck.clk, | ||
269 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | ||
270 | .enable_bit = EN_TC1_CK, | ||
271 | .recalc = &followparent_recalc, | ||
272 | }; | ||
273 | |||
274 | /* | ||
275 | * FIXME: This clock seems to be necessary but no-one has asked for its | ||
276 | * activation. [ pm.c (SRAM), CCP, Camera ] | ||
277 | */ | ||
278 | static struct clk tc2_ck = { | ||
279 | .name = "tc2_ck", | ||
280 | .ops = &clkops_generic, | ||
281 | .parent = &tc_ck.clk, | ||
282 | .flags = ENABLE_ON_INIT, | ||
283 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), | ||
284 | .enable_bit = EN_TC2_CK, | ||
285 | .recalc = &followparent_recalc, | ||
286 | }; | ||
287 | |||
288 | static struct clk dma_ck = { | ||
289 | /* No-idle controlled by "tc_ck" */ | ||
290 | .name = "dma_ck", | ||
291 | .ops = &clkops_null, | ||
292 | .parent = &tc_ck.clk, | ||
293 | .recalc = &followparent_recalc, | ||
294 | }; | ||
295 | |||
296 | static struct clk dma_lcdfree_ck = { | ||
297 | .name = "dma_lcdfree_ck", | ||
298 | .ops = &clkops_null, | ||
299 | .parent = &tc_ck.clk, | ||
300 | .recalc = &followparent_recalc, | ||
301 | }; | ||
302 | |||
303 | static struct arm_idlect1_clk api_ck = { | ||
304 | .clk = { | ||
305 | .name = "api_ck", | ||
306 | .ops = &clkops_generic, | ||
307 | .parent = &tc_ck.clk, | ||
308 | .flags = CLOCK_IDLE_CONTROL, | ||
309 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
310 | .enable_bit = EN_APICK, | ||
311 | .recalc = &followparent_recalc, | ||
312 | }, | ||
313 | .idlect_shift = 8, | ||
314 | }; | ||
315 | |||
316 | static struct arm_idlect1_clk lb_ck = { | ||
317 | .clk = { | ||
318 | .name = "lb_ck", | ||
319 | .ops = &clkops_generic, | ||
320 | .parent = &tc_ck.clk, | ||
321 | .flags = CLOCK_IDLE_CONTROL, | ||
322 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
323 | .enable_bit = EN_LBCK, | ||
324 | .recalc = &followparent_recalc, | ||
325 | }, | ||
326 | .idlect_shift = 4, | ||
327 | }; | ||
328 | |||
329 | static struct clk rhea1_ck = { | ||
330 | .name = "rhea1_ck", | ||
331 | .ops = &clkops_null, | ||
332 | .parent = &tc_ck.clk, | ||
333 | .recalc = &followparent_recalc, | ||
334 | }; | ||
335 | |||
336 | static struct clk rhea2_ck = { | ||
337 | .name = "rhea2_ck", | ||
338 | .ops = &clkops_null, | ||
339 | .parent = &tc_ck.clk, | ||
340 | .recalc = &followparent_recalc, | ||
341 | }; | ||
342 | |||
343 | static struct clk lcd_ck_16xx = { | ||
344 | .name = "lcd_ck", | ||
345 | .ops = &clkops_generic, | ||
346 | .parent = &ck_dpll1, | ||
347 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
348 | .enable_bit = EN_LCDCK, | ||
349 | .rate_offset = CKCTL_LCDDIV_OFFSET, | ||
350 | .recalc = &omap1_ckctl_recalc, | ||
351 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
352 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
353 | }; | ||
354 | |||
355 | static struct arm_idlect1_clk lcd_ck_1510 = { | ||
356 | .clk = { | ||
357 | .name = "lcd_ck", | ||
358 | .ops = &clkops_generic, | ||
359 | .parent = &ck_dpll1, | ||
360 | .flags = CLOCK_IDLE_CONTROL, | ||
361 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), | ||
362 | .enable_bit = EN_LCDCK, | ||
363 | .rate_offset = CKCTL_LCDDIV_OFFSET, | ||
364 | .recalc = &omap1_ckctl_recalc, | ||
365 | .round_rate = omap1_clk_round_rate_ckctl_arm, | ||
366 | .set_rate = omap1_clk_set_rate_ckctl_arm, | ||
367 | }, | ||
368 | .idlect_shift = 3, | ||
369 | }; | ||
370 | |||
371 | static struct clk uart1_1510 = { | ||
372 | .name = "uart1_ck", | ||
373 | .ops = &clkops_null, | ||
374 | /* Direct from ULPD, no real parent */ | ||
375 | .parent = &armper_ck.clk, | ||
376 | .rate = 12000000, | ||
377 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
378 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
379 | .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ | ||
380 | .set_rate = &omap1_set_uart_rate, | ||
381 | .recalc = &omap1_uart_recalc, | ||
382 | }; | ||
383 | |||
384 | static struct uart_clk uart1_16xx = { | ||
385 | .clk = { | ||
386 | .name = "uart1_ck", | ||
387 | .ops = &clkops_uart, | ||
388 | /* Direct from ULPD, no real parent */ | ||
389 | .parent = &armper_ck.clk, | ||
390 | .rate = 48000000, | ||
391 | .flags = RATE_FIXED | ENABLE_REG_32BIT | | ||
392 | CLOCK_NO_IDLE_PARENT, | ||
393 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
394 | .enable_bit = 29, | ||
395 | }, | ||
396 | .sysc_addr = 0xfffb0054, | ||
397 | }; | ||
398 | |||
399 | static struct clk uart2_ck = { | ||
400 | .name = "uart2_ck", | ||
401 | .ops = &clkops_null, | ||
402 | /* Direct from ULPD, no real parent */ | ||
403 | .parent = &armper_ck.clk, | ||
404 | .rate = 12000000, | ||
405 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
406 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
407 | .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ | ||
408 | .set_rate = &omap1_set_uart_rate, | ||
409 | .recalc = &omap1_uart_recalc, | ||
410 | }; | ||
411 | |||
412 | static struct clk uart3_1510 = { | ||
413 | .name = "uart3_ck", | ||
414 | .ops = &clkops_null, | ||
415 | /* Direct from ULPD, no real parent */ | ||
416 | .parent = &armper_ck.clk, | ||
417 | .rate = 12000000, | ||
418 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
419 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
420 | .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ | ||
421 | .set_rate = &omap1_set_uart_rate, | ||
422 | .recalc = &omap1_uart_recalc, | ||
423 | }; | ||
424 | |||
425 | static struct uart_clk uart3_16xx = { | ||
426 | .clk = { | ||
427 | .name = "uart3_ck", | ||
428 | .ops = &clkops_uart, | ||
429 | /* Direct from ULPD, no real parent */ | ||
430 | .parent = &armper_ck.clk, | ||
431 | .rate = 48000000, | ||
432 | .flags = RATE_FIXED | ENABLE_REG_32BIT | | ||
433 | CLOCK_NO_IDLE_PARENT, | ||
434 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
435 | .enable_bit = 31, | ||
436 | }, | ||
437 | .sysc_addr = 0xfffb9854, | ||
438 | }; | ||
439 | |||
440 | static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ | ||
441 | .name = "usb_clko", | ||
442 | .ops = &clkops_generic, | ||
443 | /* Direct from ULPD, no parent */ | ||
444 | .rate = 6000000, | ||
445 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | ||
446 | .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), | ||
447 | .enable_bit = USB_MCLK_EN_BIT, | ||
448 | }; | ||
449 | |||
450 | static struct clk usb_hhc_ck1510 = { | ||
451 | .name = "usb_hhc_ck", | ||
452 | .ops = &clkops_generic, | ||
453 | /* Direct from ULPD, no parent */ | ||
454 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ | ||
455 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | ||
456 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
457 | .enable_bit = USB_HOST_HHC_UHOST_EN, | ||
458 | }; | ||
459 | |||
460 | static struct clk usb_hhc_ck16xx = { | ||
461 | .name = "usb_hhc_ck", | ||
462 | .ops = &clkops_generic, | ||
463 | /* Direct from ULPD, no parent */ | ||
464 | .rate = 48000000, | ||
465 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ | ||
466 | .flags = RATE_FIXED | ENABLE_REG_32BIT, | ||
467 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ | ||
468 | .enable_bit = 8 /* UHOST_EN */, | ||
469 | }; | ||
470 | |||
471 | static struct clk usb_dc_ck = { | ||
472 | .name = "usb_dc_ck", | ||
473 | .ops = &clkops_generic, | ||
474 | /* Direct from ULPD, no parent */ | ||
475 | .rate = 48000000, | ||
476 | .flags = RATE_FIXED, | ||
477 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
478 | .enable_bit = 4, | ||
479 | }; | ||
480 | |||
481 | static struct clk usb_dc_ck7xx = { | ||
482 | .name = "usb_dc_ck", | ||
483 | .ops = &clkops_generic, | ||
484 | /* Direct from ULPD, no parent */ | ||
485 | .rate = 48000000, | ||
486 | .flags = RATE_FIXED, | ||
487 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
488 | .enable_bit = 8, | ||
489 | }; | ||
490 | |||
491 | static struct clk mclk_1510 = { | ||
492 | .name = "mclk", | ||
493 | .ops = &clkops_generic, | ||
494 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | ||
495 | .rate = 12000000, | ||
496 | .flags = RATE_FIXED, | ||
497 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
498 | .enable_bit = 6, | ||
499 | }; | ||
500 | |||
501 | static struct clk mclk_16xx = { | ||
502 | .name = "mclk", | ||
503 | .ops = &clkops_generic, | ||
504 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | ||
505 | .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), | ||
506 | .enable_bit = COM_ULPD_PLL_CLK_REQ, | ||
507 | .set_rate = &omap1_set_ext_clk_rate, | ||
508 | .round_rate = &omap1_round_ext_clk_rate, | ||
509 | .init = &omap1_init_ext_clk, | ||
510 | }; | ||
511 | |||
512 | static struct clk bclk_1510 = { | ||
513 | .name = "bclk", | ||
514 | .ops = &clkops_generic, | ||
515 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | ||
516 | .rate = 12000000, | ||
517 | .flags = RATE_FIXED, | ||
518 | }; | ||
519 | |||
520 | static struct clk bclk_16xx = { | ||
521 | .name = "bclk", | ||
522 | .ops = &clkops_generic, | ||
523 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ | ||
524 | .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), | ||
525 | .enable_bit = SWD_ULPD_PLL_CLK_REQ, | ||
526 | .set_rate = &omap1_set_ext_clk_rate, | ||
527 | .round_rate = &omap1_round_ext_clk_rate, | ||
528 | .init = &omap1_init_ext_clk, | ||
529 | }; | ||
530 | |||
531 | static struct clk mmc1_ck = { | ||
532 | .name = "mmc_ck", | ||
533 | .ops = &clkops_generic, | ||
534 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | ||
535 | .parent = &armper_ck.clk, | ||
536 | .rate = 48000000, | ||
537 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
538 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
539 | .enable_bit = 23, | ||
540 | }; | ||
541 | |||
542 | static struct clk mmc2_ck = { | ||
543 | .name = "mmc_ck", | ||
544 | .id = 1, | ||
545 | .ops = &clkops_generic, | ||
546 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | ||
547 | .parent = &armper_ck.clk, | ||
548 | .rate = 48000000, | ||
549 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
550 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), | ||
551 | .enable_bit = 20, | ||
552 | }; | ||
553 | |||
554 | static struct clk mmc3_ck = { | ||
555 | .name = "mmc_ck", | ||
556 | .id = 2, | ||
557 | .ops = &clkops_generic, | ||
558 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ | ||
559 | .parent = &armper_ck.clk, | ||
560 | .rate = 48000000, | ||
561 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, | ||
562 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), | ||
563 | .enable_bit = 12, | ||
564 | }; | ||
565 | |||
566 | static struct clk virtual_ck_mpu = { | ||
567 | .name = "mpu", | ||
568 | .ops = &clkops_null, | ||
569 | .parent = &arm_ck, /* Is smarter alias for */ | ||
570 | .recalc = &followparent_recalc, | ||
571 | .set_rate = &omap1_select_table_rate, | ||
572 | .round_rate = &omap1_round_to_table_rate, | ||
573 | }; | ||
574 | |||
575 | /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK | ||
576 | remains active during MPU idle whenever this is enabled */ | ||
577 | static struct clk i2c_fck = { | ||
578 | .name = "i2c_fck", | ||
579 | .id = 1, | ||
580 | .ops = &clkops_null, | ||
581 | .flags = CLOCK_NO_IDLE_PARENT, | ||
582 | .parent = &armxor_ck.clk, | ||
583 | .recalc = &followparent_recalc, | ||
584 | }; | ||
585 | |||
586 | static struct clk i2c_ick = { | ||
587 | .name = "i2c_ick", | ||
588 | .id = 1, | ||
589 | .ops = &clkops_null, | ||
590 | .flags = CLOCK_NO_IDLE_PARENT, | ||
591 | .parent = &armper_ck.clk, | ||
592 | .recalc = &followparent_recalc, | ||
593 | }; | ||
594 | |||
595 | /* | ||
596 | * clkdev integration | ||
597 | */ | ||
598 | |||
599 | static struct omap_clk omap_clks[] = { | ||
600 | /* non-ULPD clocks */ | ||
601 | CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
602 | CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310), | ||
603 | /* CK_GEN1 clocks */ | ||
604 | CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX), | ||
605 | CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX), | ||
606 | CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310), | ||
607 | CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
608 | CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310), | ||
609 | CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
610 | CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
611 | CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
612 | CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX), | ||
613 | CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310), | ||
614 | CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310), | ||
615 | CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX), | ||
616 | /* CK_GEN2 clocks */ | ||
617 | CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310), | ||
618 | CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310), | ||
619 | CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310), | ||
620 | CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
621 | CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310), | ||
622 | /* CK_GEN3 clocks */ | ||
623 | CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
624 | CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310), | ||
625 | CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX), | ||
626 | CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX), | ||
627 | CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX), | ||
628 | CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310), | ||
629 | CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX), | ||
630 | CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
631 | CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310), | ||
632 | CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX), | ||
633 | CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX), | ||
634 | CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX), | ||
635 | CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310), | ||
636 | /* ULPD clocks */ | ||
637 | CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310), | ||
638 | CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX), | ||
639 | CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310), | ||
640 | CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310), | ||
641 | CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX), | ||
642 | CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310), | ||
643 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310), | ||
644 | CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX), | ||
645 | CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX), | ||
646 | CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX), | ||
647 | CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310), | ||
648 | CLK(NULL, "mclk", &mclk_16xx, CK_16XX), | ||
649 | CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310), | ||
650 | CLK(NULL, "bclk", &bclk_16xx, CK_16XX), | ||
651 | CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310), | ||
652 | CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX), | ||
653 | CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX), | ||
654 | CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX), | ||
655 | CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX), | ||
656 | /* Virtual clocks */ | ||
657 | CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310), | ||
658 | CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310), | ||
659 | CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX), | ||
660 | CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310), | ||
661 | CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
662 | CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX), | ||
663 | CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310), | ||
664 | CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX), | ||
665 | CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310), | ||
666 | CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX), | ||
667 | CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310), | ||
668 | CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
669 | CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310), | ||
670 | CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310), | ||
671 | }; | ||
672 | |||
673 | /* | ||
674 | * init | ||
675 | */ | ||
676 | |||
677 | static struct clk_functions omap1_clk_functions __initdata = { | ||
678 | .clk_enable = omap1_clk_enable, | ||
679 | .clk_disable = omap1_clk_disable, | ||
680 | .clk_round_rate = omap1_clk_round_rate, | ||
681 | .clk_set_rate = omap1_clk_set_rate, | ||
682 | .clk_disable_unused = omap1_clk_disable_unused, | ||
683 | }; | ||
684 | |||
685 | int __init omap1_clk_init(void) | ||
686 | { | ||
687 | struct omap_clk *c; | ||
688 | const struct omap_clock_config *info; | ||
689 | int crystal_type = 0; /* Default 12 MHz */ | ||
690 | u32 reg, cpu_mask; | ||
691 | |||
692 | #ifdef CONFIG_DEBUG_LL | ||
693 | /* | ||
694 | * Resets some clocks that may be left on from bootloader, | ||
695 | * but leaves serial clocks on. | ||
696 | */ | ||
697 | omap_writel(0x3 << 29, MOD_CONF_CTRL_0); | ||
698 | #endif | ||
699 | |||
700 | /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ | ||
701 | reg = omap_readw(SOFT_REQ_REG) & (1 << 4); | ||
702 | omap_writew(reg, SOFT_REQ_REG); | ||
703 | if (!cpu_is_omap15xx()) | ||
704 | omap_writew(0, SOFT_REQ_REG2); | ||
705 | |||
706 | clk_init(&omap1_clk_functions); | ||
707 | |||
708 | /* By default all idlect1 clocks are allowed to idle */ | ||
709 | arm_idlect1_mask = ~0; | ||
710 | |||
711 | for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) | ||
712 | clk_preinit(c->lk.clk); | ||
713 | |||
714 | cpu_mask = 0; | ||
715 | if (cpu_is_omap16xx()) | ||
716 | cpu_mask |= CK_16XX; | ||
717 | if (cpu_is_omap1510()) | ||
718 | cpu_mask |= CK_1510; | ||
719 | if (cpu_is_omap7xx()) | ||
720 | cpu_mask |= CK_7XX; | ||
721 | if (cpu_is_omap310()) | ||
722 | cpu_mask |= CK_310; | ||
723 | |||
724 | for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) | ||
725 | if (c->cpu & cpu_mask) { | ||
726 | clkdev_add(&c->lk); | ||
727 | clk_register(c->lk.clk); | ||
728 | } | ||
729 | |||
730 | /* Pointers to these clocks are needed by code in clock.c */ | ||
731 | api_ck_p = clk_get(NULL, "api_ck"); | ||
732 | ck_dpll1_p = clk_get(NULL, "ck_dpll1"); | ||
733 | ck_ref_p = clk_get(NULL, "ck_ref"); | ||
734 | |||
735 | info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); | ||
736 | if (info != NULL) { | ||
737 | if (!cpu_is_omap15xx()) | ||
738 | crystal_type = info->system_clock_type; | ||
739 | } | ||
740 | |||
741 | #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) | ||
742 | ck_ref.rate = 13000000; | ||
743 | #elif defined(CONFIG_ARCH_OMAP16XX) | ||
744 | if (crystal_type == 2) | ||
745 | ck_ref.rate = 19200000; | ||
746 | #endif | ||
747 | |||
748 | pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: " | ||
749 | "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), | ||
750 | omap_readw(ARM_CKCTL)); | ||
751 | |||
752 | /* We want to be in syncronous scalable mode */ | ||
753 | omap_writew(0x1000, ARM_SYSST); | ||
754 | |||
755 | #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER | ||
756 | /* Use values set by bootloader. Determine PLL rate and recalculate | ||
757 | * dependent clocks as if kernel had changed PLL or divisors. | ||
758 | */ | ||
759 | { | ||
760 | unsigned pll_ctl_val = omap_readw(DPLL_CTL); | ||
761 | |||
762 | ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ | ||
763 | if (pll_ctl_val & 0x10) { | ||
764 | /* PLL enabled, apply multiplier and divisor */ | ||
765 | if (pll_ctl_val & 0xf80) | ||
766 | ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; | ||
767 | ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; | ||
768 | } else { | ||
769 | /* PLL disabled, apply bypass divisor */ | ||
770 | switch (pll_ctl_val & 0xc) { | ||
771 | case 0: | ||
772 | break; | ||
773 | case 0x4: | ||
774 | ck_dpll1.rate /= 2; | ||
775 | break; | ||
776 | default: | ||
777 | ck_dpll1.rate /= 4; | ||
778 | break; | ||
779 | } | ||
780 | } | ||
781 | } | ||
782 | #else | ||
783 | /* Find the highest supported frequency and enable it */ | ||
784 | if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { | ||
785 | printk(KERN_ERR "System frequencies not set. Check your config.\n"); | ||
786 | /* Guess sane values (60MHz) */ | ||
787 | omap_writew(0x2290, DPLL_CTL); | ||
788 | omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL); | ||
789 | ck_dpll1.rate = 60000000; | ||
790 | } | ||
791 | #endif | ||
792 | propagate_rate(&ck_dpll1); | ||
793 | /* Cache rates for clocks connected to ck_ref (not dpll1) */ | ||
794 | propagate_rate(&ck_ref); | ||
795 | printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " | ||
796 | "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", | ||
797 | ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, | ||
798 | ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, | ||
799 | arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); | ||
800 | |||
801 | #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) | ||
802 | /* Select slicer output as OMAP input clock */ | ||
803 | omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL); | ||
804 | #endif | ||
805 | |||
806 | /* Amstrad Delta wants BCLK high when inactive */ | ||
807 | if (machine_is_ams_delta()) | ||
808 | omap_writel(omap_readl(ULPD_CLOCK_CTRL) | | ||
809 | (1 << SDW_MCLK_INV_BIT), | ||
810 | ULPD_CLOCK_CTRL); | ||
811 | |||
812 | /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ | ||
813 | /* (on 730, bit 13 must not be cleared) */ | ||
814 | if (cpu_is_omap7xx()) | ||
815 | omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); | ||
816 | else | ||
817 | omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); | ||
818 | |||
819 | /* Put DSP/MPUI into reset until needed */ | ||
820 | omap_writew(0, ARM_RSTCT1); | ||
821 | omap_writew(1, ARM_RSTCT2); | ||
822 | omap_writew(0x400, ARM_IDLECT1); | ||
823 | |||
824 | /* | ||
825 | * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) | ||
826 | * of the ARM_IDLECT2 register must be set to zero. The power-on | ||
827 | * default value of this bit is one. | ||
828 | */ | ||
829 | omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ | ||
830 | |||
831 | /* | ||
832 | * Only enable those clocks we will need, let the drivers | ||
833 | * enable other clocks as necessary | ||
834 | */ | ||
835 | clk_enable(&armper_ck.clk); | ||
836 | clk_enable(&armxor_ck.clk); | ||
837 | clk_enable(&armtim_ck.clk); /* This should be done by timer code */ | ||
838 | |||
839 | if (cpu_is_omap15xx()) | ||
840 | clk_enable(&arm_gpio_ck); | ||
841 | |||
842 | return 0; | ||
843 | } | ||
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c index 2a6d68aa3489..d9b8d82530ae 100644 --- a/arch/arm/mach-omap1/io.c +++ b/arch/arm/mach-omap1/io.c | |||
@@ -18,7 +18,8 @@ | |||
18 | #include <plat/mux.h> | 18 | #include <plat/mux.h> |
19 | #include <plat/tc.h> | 19 | #include <plat/tc.h> |
20 | 20 | ||
21 | extern int omap1_clk_init(void); | 21 | #include "clock.h" |
22 | |||
22 | extern void omap_check_revision(void); | 23 | extern void omap_check_revision(void); |
23 | extern void omap_sram_init(void); | 24 | extern void omap_sram_init(void); |
24 | extern void omapfb_reserve_sdram(void); | 25 | extern void omapfb_reserve_sdram(void); |
diff --git a/arch/arm/mach-omap1/opp.h b/arch/arm/mach-omap1/opp.h new file mode 100644 index 000000000000..07074d79adce --- /dev/null +++ b/arch/arm/mach-omap1/opp.h | |||
@@ -0,0 +1,28 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-omap1/opp.h | ||
3 | * | ||
4 | * Copyright (C) 2004 - 2005 Nokia corporation | ||
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | ||
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ARCH_ARM_MACH_OMAP1_OPP_H | ||
14 | #define __ARCH_ARM_MACH_OMAP1_OPP_H | ||
15 | |||
16 | #include <linux/types.h> | ||
17 | |||
18 | struct mpu_rate { | ||
19 | unsigned long rate; | ||
20 | unsigned long xtal; | ||
21 | unsigned long pll_rate; | ||
22 | __u16 ckctl_val; | ||
23 | __u16 dpllctl_val; | ||
24 | }; | ||
25 | |||
26 | extern struct mpu_rate omap1_rate_table[]; | ||
27 | |||
28 | #endif | ||
diff --git a/arch/arm/mach-omap1/opp_data.c b/arch/arm/mach-omap1/opp_data.c new file mode 100644 index 000000000000..75a546514994 --- /dev/null +++ b/arch/arm/mach-omap1/opp_data.c | |||
@@ -0,0 +1,59 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-omap1/opp_data.c | ||
3 | * | ||
4 | * Copyright (C) 2004 - 2005 Nokia corporation | ||
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | ||
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include "opp.h" | ||
14 | |||
15 | /*------------------------------------------------------------------------- | ||
16 | * Omap1 MPU rate table | ||
17 | *-------------------------------------------------------------------------*/ | ||
18 | struct mpu_rate omap1_rate_table[] = { | ||
19 | /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL | ||
20 | * NOTE: Comment order here is different from bits in CKCTL value: | ||
21 | * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv | ||
22 | */ | ||
23 | #if defined(CONFIG_OMAP_ARM_216MHZ) | ||
24 | { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ | ||
25 | #endif | ||
26 | #if defined(CONFIG_OMAP_ARM_195MHZ) | ||
27 | { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ | ||
28 | #endif | ||
29 | #if defined(CONFIG_OMAP_ARM_192MHZ) | ||
30 | { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ | ||
31 | { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ | ||
32 | { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ | ||
33 | { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ | ||
34 | { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ | ||
35 | #endif | ||
36 | #if defined(CONFIG_OMAP_ARM_182MHZ) | ||
37 | { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ | ||
38 | #endif | ||
39 | #if defined(CONFIG_OMAP_ARM_168MHZ) | ||
40 | { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ | ||
41 | #endif | ||
42 | #if defined(CONFIG_OMAP_ARM_150MHZ) | ||
43 | { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ | ||
44 | #endif | ||
45 | #if defined(CONFIG_OMAP_ARM_120MHZ) | ||
46 | { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ | ||
47 | #endif | ||
48 | #if defined(CONFIG_OMAP_ARM_96MHZ) | ||
49 | { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ | ||
50 | #endif | ||
51 | #if defined(CONFIG_OMAP_ARM_60MHZ) | ||
52 | { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ | ||
53 | #endif | ||
54 | #if defined(CONFIG_OMAP_ARM_30MHZ) | ||
55 | { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ | ||
56 | #endif | ||
57 | { 0, 0, 0, 0, 0 }, | ||
58 | }; | ||
59 | |||
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h index 97b8c126e5a1..96e5d385ac7d 100644 --- a/arch/arm/plat-omap/include/plat/clkdev_omap.h +++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h | |||
@@ -11,8 +11,8 @@ | |||
11 | #include <asm/clkdev.h> | 11 | #include <asm/clkdev.h> |
12 | 12 | ||
13 | struct omap_clk { | 13 | struct omap_clk { |
14 | u32 cpu; | 14 | u16 cpu; |
15 | struct clk_lookup lk; | 15 | struct clk_lookup lk; |
16 | }; | 16 | }; |
17 | 17 | ||
18 | #define CLK(dev, con, ck, cp) \ | 18 | #define CLK(dev, con, ck, cp) \ |
@@ -26,11 +26,15 @@ struct omap_clk { | |||
26 | } | 26 | } |
27 | 27 | ||
28 | 28 | ||
29 | #define CK_243X (1 << 0) | 29 | #define CK_310 (1 << 0) |
30 | #define CK_242X (1 << 1) | 30 | #define CK_7XX (1 << 1) |
31 | #define CK_343X (1 << 2) | 31 | #define CK_1510 (1 << 2) |
32 | #define CK_3430ES1 (1 << 3) | 32 | #define CK_16XX (1 << 3) |
33 | #define CK_3430ES2 (1 << 4) | 33 | #define CK_243X (1 << 4) |
34 | #define CK_242X (1 << 5) | ||
35 | #define CK_343X (1 << 6) | ||
36 | #define CK_3430ES1 (1 << 7) | ||
37 | #define CK_3430ES2 (1 << 8) | ||
34 | 38 | ||
35 | 39 | ||
36 | #endif | 40 | #endif |