2 files changed, 22 insertions, 0 deletions

diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 9c30938aad52..f7458396cd7c 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -298,6 +298,12 @@ InstructionTLBMiss:
         stw     r10, 0(r0)
         stw     r11, 4(r0)
         mfspr   r10, SPRN_SRR0  /* Get effective address of fault */
+#ifdef CONFIG_8xx_CPU15
+        addi    r11, r10, 0x1000
+        tlbie   r11
+        addi    r11, r10, -0x1000
+        tlbie   r11
+#endif
         DO_8xx_CPU6(0x3780, r3)
         mtspr   SPRN_MD_EPN, r10        /* Have to use MD_EPN for walk, MI_EPN can't */
         mfspr   r10, SPRN_M_TWB /* Get level 1 table entry address */
diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig
index 8ecd01ad0de8..322b155f24ec 100644
--- a/arch/powerpc/platforms/8xx/Kconfig
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -100,6 +100,22 @@ config 8xx_CPU6
 
           If in doubt, say N here.
 
+config 8xx_CPU15
+        bool "CPU15 Silicon Errata"
+        default y
+        help
+          This enables a workaround for erratum CPU15 on MPC8xx chips.
+          This bug can cause incorrect code execution under certain
+          circumstances.  This workaround adds some overhead (a TLB miss
+          every time execution crosses a page boundary), and you may wish
+          to disable it if you have worked around the bug in the compiler
+          (by not placing conditional branches or branches to LR or CTR
+          in the last word of a page, with a target of the last cache
+          line in the next page), or if you have used some other
+          workaround.
+
+          If in doubt, say Y here.
+
 choice
         prompt "Microcode patch selection"
         default NO_UCODE_PATCH