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-rw-r--r--arch/arm/mach-lh7a40x/common.h1
-rw-r--r--arch/arm/mach-lh7a40x/lcd-panel.h346
-rw-r--r--include/asm-arm/arch-lh7a40x/clocks.h20
-rw-r--r--include/asm-arm/arch-lh7a40x/constants.h8
-rw-r--r--include/asm-arm/arch-lh7a40x/dma.h79
-rw-r--r--include/asm-arm/arch-lh7a40x/hardware.h4
-rw-r--r--include/asm-arm/arch-lh7a40x/irqs.h7
-rw-r--r--include/asm-arm/arch-lh7a40x/registers.h64
-rw-r--r--include/asm-arm/arch-lh7a40x/ssp.h71
-rw-r--r--include/asm-arm/arch-lh7a40x/uncompress.h2
10 files changed, 581 insertions, 21 deletions
diff --git a/arch/arm/mach-lh7a40x/common.h b/arch/arm/mach-lh7a40x/common.h
index ea8de7e3ab1b..18e8bb4eb202 100644
--- a/arch/arm/mach-lh7a40x/common.h
+++ b/arch/arm/mach-lh7a40x/common.h
@@ -12,6 +12,7 @@ extern struct sys_timer lh7a40x_timer;
12 12
13extern void lh7a400_init_irq (void); 13extern void lh7a400_init_irq (void);
14extern void lh7a404_init_irq (void); 14extern void lh7a404_init_irq (void);
15extern void lh7a40x_clcd_init (void);
15extern void lh7a40x_init_board_irq (void); 16extern void lh7a40x_init_board_irq (void);
16 17
17#define IRQ_DISPATCH(irq) desc_handle_irq((irq),(irq_desc + irq), regs) 18#define IRQ_DISPATCH(irq) desc_handle_irq((irq),(irq_desc + irq), regs)
diff --git a/arch/arm/mach-lh7a40x/lcd-panel.h b/arch/arm/mach-lh7a40x/lcd-panel.h
new file mode 100644
index 000000000000..4fb2efc4950f
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/lcd-panel.h
@@ -0,0 +1,346 @@
1/* lcd-panel.h
2 $Id$
3
4 written by Marc Singer
5 18 Jul 2005
6
7 Copyright (C) 2005 Marc Singer
8
9 -----------
10 DESCRIPTION
11 -----------
12
13 Only one panel may be defined at a time.
14
15 The pixel clock is calculated to be no greater than the target.
16
17 Each timing value is accompanied by a specification comment.
18
19 UNITS/MIN/TYP/MAX
20
21 Most of the units will be in clocks.
22
23 USE_RGB555
24
25 Define this macro to configure the AMBA LCD controller to use an
26 RGB555 encoding for the pels instead of the normal RGB565.
27
28 LPD9520, LPD79524, LPD7A400, LPD7A404-10, LPD7A404-11
29
30 These boards are best approximated by 555 for all panels. Some
31 can use an extra low-order bit of blue in bit 16 of the color
32 value, but we don't have a way to communicate this non-linear
33 mapping to the kernel.
34
35*/
36
37#if !defined (__LCD_PANEL_H__)
38# define __LCD_PANEL_H__
39
40#if defined (MACH_LPD79520)\
41 || defined (MACH_LPD79524)\
42 || defined (MACH_LPD7A400)\
43 || defined (MACH_LPD7A404)
44# define USE_RGB555
45#endif
46
47struct clcd_panel_extra {
48 unsigned int hrmode;
49 unsigned int clsen;
50 unsigned int spsen;
51 unsigned int pcdel;
52 unsigned int revdel;
53 unsigned int lpdel;
54 unsigned int spldel;
55 unsigned int pc2del;
56};
57
58#define NS_TO_CLOCK(ns,c) ((((ns)*((c)/1000) + (1000000 - 1))/1000000))
59#define CLOCK_TO_DIV(e,c) (((c) + (e) - 1)/(e))
60
61#if defined CONFIG_FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT
62
63 /* Logic Product Development LCD 3.5" QVGA HRTFT -10 */
64 /* Sharp PN LQ035Q7DB02 w/HRTFT controller chip */
65
66#define PIX_CLOCK_TARGET (6800000)
67#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
68#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
69
70static struct clcd_panel lcd_panel = {
71 .mode = {
72 .name = "3.5in QVGA (LQ035Q7DB02)",
73 .xres = 240,
74 .yres = 320,
75 .pixclock = PIX_CLOCK,
76 .left_margin = 16,
77 .right_margin = 21,
78 .upper_margin = 8, // line/8/8/8
79 .lower_margin = 5,
80 .hsync_len = 61,
81 .vsync_len = NS_TO_CLOCK (60, PIX_CLOCK),
82 .vmode = FB_VMODE_NONINTERLACED,
83 },
84 .width = -1,
85 .height = -1,
86 .tim2 = TIM2_IPC | (PIX_CLOCK_DIVIDER - 2),
87 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
88 .bpp = 16,
89};
90
91#define HAS_LCD_PANEL_EXTRA
92
93static struct clcd_panel_extra lcd_panel_extra = {
94 .hrmode = 1,
95 .clsen = 1,
96 .spsen = 1,
97 .pcdel = 8,
98 .revdel = 7,
99 .lpdel = 13,
100 .spldel = 77,
101 .pc2del = 208,
102};
103
104#endif
105
106#if defined CONFIG_FB_ARMCLCD_SHARP_LQ057Q3DC02
107
108 /* Logic Product Development LCD 5.7" QVGA -10 */
109 /* Sharp PN LQ057Q3DC02 */
110 /* QVGA mode, V/Q=LOW */
111
112/* From Sharp on 2006.1.3. I believe some of the values are incorrect
113 * based on the datasheet.
114
115 Timing0 TIMING1 TIMING2 CONTROL
116 0x140A0C4C 0x080504EF 0x013F380D 0x00000829
117 HBP= 20 VBP= 8 BCD= 0
118 HFP= 10 VFP= 5 CPL=319
119 HSW= 12 VSW= 1 IOE= 0
120 PPL= 19 LPP=239 IPC= 1
121 IHS= 1
122 IVS= 1
123 ACB= 0
124 CSEL= 0
125 PCD= 13
126
127 */
128
129/* The full horozontal cycle (Th) is clock/360/400/450. */
130/* The full vertical cycle (Tv) is line/251/262/280. */
131
132#define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */
133#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
134#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
135
136static struct clcd_panel lcd_panel = {
137 .mode = {
138 .name = "5.7in QVGA (LQ057Q3DC02)",
139 .xres = 320,
140 .yres = 240,
141 .pixclock = PIX_CLOCK,
142 .left_margin = 11,
143 .right_margin = 400-11-320-2,
144 .upper_margin = 7, // line/7/7/7
145 .lower_margin = 262-7-240-2,
146 .hsync_len = 2, // clk/2/96/200
147 .vsync_len = 2, // line/2/-/34
148 .vmode = FB_VMODE_NONINTERLACED,
149 },
150 .width = -1,
151 .height = -1,
152 .tim2 = TIM2_IHS | TIM2_IVS
153 | (PIX_CLOCK_DIVIDER - 2),
154 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
155 .bpp = 16,
156};
157
158#endif
159
160#if defined CONFIG_FB_ARMCLCD_SHARP_LQ64D343
161
162 /* Logic Product Development LCD 6.4" VGA -10 */
163 /* Sharp PN LQ64D343 */
164
165/* The full horozontal cycle (Th) is clock/750/800/900. */
166/* The full vertical cycle (Tv) is line/515/525/560. */
167
168#define PIX_CLOCK_TARGET (28330000)
169#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
170#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
171
172static struct clcd_panel lcd_panel = {
173 .mode = {
174 .name = "6.4in QVGA (LQ64D343)",
175 .xres = 640,
176 .yres = 480,
177 .pixclock = PIX_CLOCK,
178 .left_margin = 32,
179 .right_margin = 800-32-640-96,
180 .upper_margin = 32, // line/34/34/34
181 .lower_margin = 540-32-480-2,
182 .hsync_len = 96, // clk/2/96/200
183 .vsync_len = 2, // line/2/-/34
184 .vmode = FB_VMODE_NONINTERLACED,
185 },
186 .width = -1,
187 .height = -1,
188 .tim2 = TIM2_IHS | TIM2_IVS
189 | (PIX_CLOCK_DIVIDER - 2),
190 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
191 .bpp = 16,
192};
193
194#endif
195
196#if defined CONFIG_FB_ARMCLCD_SHARP_LQ10D368
197
198 /* Logic Product Development LCD 10.4" VGA -10 */
199 /* Sharp PN LQ10D368 */
200
201#define PIX_CLOCK_TARGET (28330000)
202#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
203#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
204
205static struct clcd_panel lcd_panel = {
206 .mode = {
207 .name = "10.4in VGA (LQ10D368)",
208 .xres = 640,
209 .yres = 480,
210 .pixclock = PIX_CLOCK,
211 .left_margin = 21,
212 .right_margin = 15,
213 .upper_margin = 34,
214 .lower_margin = 5,
215 .hsync_len = 96,
216 .vsync_len = 16,
217 .vmode = FB_VMODE_NONINTERLACED,
218 },
219 .width = -1,
220 .height = -1,
221 .tim2 = TIM2_IHS | TIM2_IVS
222 | (PIX_CLOCK_DIVIDER - 2),
223 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
224 .bpp = 16,
225};
226
227#endif
228
229#if defined CONFIG_FB_ARMCLCD_SHARP_LQ121S1DG41
230
231 /* Logic Product Development LCD 12.1" SVGA -10 */
232 /* Sharp PN LQ121S1DG41, was LQ121S1DG31 */
233
234/* Note that with a 99993900 Hz HCLK, it is not possible to hit the
235 * target clock frequency range of 35MHz to 42MHz. */
236
237/* If the target pixel clock is substantially lower than the panel
238 * spec, this is done to prevent the LCD display from glitching when
239 * the CPU is under load. A pixel clock higher than 25MHz
240 * (empirically determined) will compete with the CPU for bus cycles
241 * for the Ethernet chip. However, even a pixel clock of 10MHz
242 * competes with Compact Flash interface during some operations
243 * (fdisk, e2fsck). And, at that speed the display may have a visible
244 * flicker. */
245
246/* The full horozontal cycle (Th) is clock/832/1056/1395. */
247
248#define PIX_CLOCK_TARGET (20000000)
249#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
250#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
251
252static struct clcd_panel lcd_panel = {
253 .mode = {
254 .name = "12.1in SVGA (LQ121S1DG41)",
255 .xres = 800,
256 .yres = 600,
257 .pixclock = PIX_CLOCK,
258 .left_margin = 89, // ns/5/-/(1/PIX_CLOCK)-10
259 .right_margin = 1056-800-89-128,
260 .upper_margin = 23, // line/23/23/23
261 .lower_margin = 44,
262 .hsync_len = 128, // clk/2/128/200
263 .vsync_len = 4, // line/2/4/6
264 .vmode = FB_VMODE_NONINTERLACED,
265 },
266 .width = -1,
267 .height = -1,
268 .tim2 = TIM2_IHS | TIM2_IVS
269 | (PIX_CLOCK_DIVIDER - 2),
270 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
271 .bpp = 16,
272};
273
274#endif
275
276#if defined CONFIG_FB_ARMCLCD_HITACHI
277
278 /* Hitachi*/
279 /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */
280
281#define PIX_CLOCK_TARGET (49000000)
282#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
283#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
284
285static struct clcd_panel lcd_panel = {
286 .mode = {
287 .name = "Hitachi 800x480",
288 .xres = 800,
289 .yres = 480,
290 .pixclock = PIX_CLOCK,
291 .left_margin = 88,
292 .right_margin = 40,
293 .upper_margin = 32,
294 .lower_margin = 11,
295 .hsync_len = 128,
296 .vsync_len = 2,
297 .vmode = FB_VMODE_NONINTERLACED,
298 },
299 .width = -1,
300 .height = -1,
301 .tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS
302 | (PIX_CLOCK_DIVIDER - 2),
303 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
304 .bpp = 16,
305};
306
307#endif
308
309
310#if defined CONFIG_FB_ARMCLCD_AUO_A070VW01_WIDE
311
312 /* AU Optotronics A070VW01 7.0 Wide Screen color Display*/
313 /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */
314
315#define PIX_CLOCK_TARGET (10000000)
316#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
317#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
318
319static struct clcd_panel lcd_panel = {
320 .mode = {
321 .name = "7.0in Wide (A070VW01)",
322 .xres = 480,
323 .yres = 234,
324 .pixclock = PIX_CLOCK,
325 .left_margin = 30,
326 .right_margin = 25,
327 .upper_margin = 14,
328 .lower_margin = 12,
329 .hsync_len = 100,
330 .vsync_len = 1,
331 .vmode = FB_VMODE_NONINTERLACED,
332 },
333 .width = -1,
334 .height = -1,
335 .tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS
336 | (PIX_CLOCK_DIVIDER - 2),
337 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
338 .bpp = 16,
339};
340
341#endif
342
343#undef NS_TO_CLOCK
344#undef CLOCK_TO_DIV
345
346#endif /* __LCD_PANEL_H__ */
diff --git a/include/asm-arm/arch-lh7a40x/clocks.h b/include/asm-arm/arch-lh7a40x/clocks.h
new file mode 100644
index 000000000000..bee02fd8dab1
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/clocks.h
@@ -0,0 +1,20 @@
1/* include/asm-arm/arch-lh7a40x/clocks.h
2 *
3 * Copyright (C) 2004 Marc Singer
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <linux/config.h>
12
13#ifndef __ASM_ARCH_CLOCKS_H
14#define __ASM_ARCH_CLOCKS_H
15
16unsigned int fclkfreq_get (void);
17unsigned int hclkfreq_get (void);
18unsigned int pclkfreq_get (void);
19
20#endif /* _ASM_ARCH_CLOCKS_H */
diff --git a/include/asm-arm/arch-lh7a40x/constants.h b/include/asm-arm/arch-lh7a40x/constants.h
index 52c1cb9c39c6..2929e891ee03 100644
--- a/include/asm-arm/arch-lh7a40x/constants.h
+++ b/include/asm-arm/arch-lh7a40x/constants.h
@@ -29,8 +29,7 @@
29 29
30#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) 30#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
31 31
32# define IOBARRIER_PHYS 0xc0000000 /* Start of SDRAM */ 32# define IOBARRIER_PHYS 0x10000000 /* Second bank, fastest timing */
33/*# define IOBARRIER_PHYS 0x00000000 */ /* Start of flash */
34# define IOBARRIER_VIRT 0xf0000000 33# define IOBARRIER_VIRT 0xf0000000
35# define IOBARRIER_SIZE PAGE_SIZE 34# define IOBARRIER_SIZE PAGE_SIZE
36 35
@@ -53,6 +52,9 @@
53# define CPLD08_PHYS CPLDX_PHYS (0x08) 52# define CPLD08_PHYS CPLDX_PHYS (0x08)
54# define CPLD08_VIRT CPLDX_VIRT (0x08) 53# define CPLD08_VIRT CPLDX_VIRT (0x08)
55# define CPLD08_SIZE PAGE_SIZE 54# define CPLD08_SIZE PAGE_SIZE
55# define CPLD0A_PHYS CPLDX_PHYS (0x0a)
56# define CPLD0A_VIRT CPLDX_VIRT (0x0a)
57# define CPLD0A_SIZE PAGE_SIZE
56# define CPLD0C_PHYS CPLDX_PHYS (0x0c) 58# define CPLD0C_PHYS CPLDX_PHYS (0x0c)
57# define CPLD0C_VIRT CPLDX_VIRT (0x0c) 59# define CPLD0C_VIRT CPLDX_VIRT (0x0c)
58# define CPLD0C_SIZE PAGE_SIZE 60# define CPLD0C_SIZE PAGE_SIZE
@@ -84,5 +86,7 @@
84#define XTAL_IN 14745600 /* 14.7456 MHz crystal */ 86#define XTAL_IN 14745600 /* 14.7456 MHz crystal */
85#define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */ 87#define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */
86#define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */ 88#define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */
89#define HCLK (99993600)
90//#define HCLK (119808000)
87 91
88#endif /* __ASM_ARCH_CONSTANTS_H */ 92#endif /* __ASM_ARCH_CONSTANTS_H */
diff --git a/include/asm-arm/arch-lh7a40x/dma.h b/include/asm-arm/arch-lh7a40x/dma.h
index 15492e3253f6..a8cbd14bbf9d 100644
--- a/include/asm-arm/arch-lh7a40x/dma.h
+++ b/include/asm-arm/arch-lh7a40x/dma.h
@@ -1,9 +1,86 @@
1/* include/asm-arm/arch-lh7a40x/dma.h 1/* include/asm-arm/arch-lh7a40x/dma.h
2 * 2 *
3 * Copyright (C) 2003 Coastal Environmental Systems 3 * Copyright (C) 2005 Marc Singer
4 * 4 *
5 * This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation. 7 * version 2 as published by the Free Software Foundation.
8 * 8 *
9 */ 9 */
10
11typedef enum {
12 DMA_M2M0 = 0,
13 DMA_M2M1 = 1,
14 DMA_M2P0 = 2, /* Tx */
15 DMA_M2P1 = 3, /* Rx */
16 DMA_M2P2 = 4, /* Tx */
17 DMA_M2P3 = 5, /* Rx */
18 DMA_M2P4 = 6, /* Tx - AC97 */
19 DMA_M2P5 = 7, /* Rx - AC97 */
20 DMA_M2P6 = 8, /* Tx */
21 DMA_M2P7 = 9, /* Rx */
22} dma_device_t;
23
24#define DMA_LENGTH_MAX ((64*1024) - 4) /* bytes */
25
26#define DMAC_GCA __REG(DMAC_PHYS + 0x2b80)
27#define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0)
28
29#define DMAC_GIR_MMI1 (1<<11)
30#define DMAC_GIR_MMI0 (1<<10)
31#define DMAC_GIR_MPI8 (1<<9)
32#define DMAC_GIR_MPI9 (1<<8)
33#define DMAC_GIR_MPI6 (1<<7)
34#define DMAC_GIR_MPI7 (1<<6)
35#define DMAC_GIR_MPI4 (1<<5)
36#define DMAC_GIR_MPI5 (1<<4)
37#define DMAC_GIR_MPI2 (1<<3)
38#define DMAC_GIR_MPI3 (1<<2)
39#define DMAC_GIR_MPI0 (1<<1)
40#define DMAC_GIR_MPI1 (1<<0)
41
42#define DMAC_M2P0 0x0000
43#define DMAC_M2P1 0x0040
44#define DMAC_M2P2 0x0080
45#define DMAC_M2P3 0x00c0
46#define DMAC_M2P4 0x0240
47#define DMAC_M2P5 0x0200
48#define DMAC_M2P6 0x02c0
49#define DMAC_M2P7 0x0280
50#define DMAC_M2P8 0x0340
51#define DMAC_M2P9 0x0300
52#define DMAC_M2M0 0x0100
53#define DMAC_M2M1 0x0140
54
55#define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00)
56#define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04)
57#define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08)
58#define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c)
59#define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14)
60#define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20)
61#define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24)
62#define DMAC_P_CURRENT0(c) __REG(DMAC_PHYS + (c) + 0x28)
63#define DMAC_P_MAXCNT1(c) __REG(DMAC_PHYS + (c) + 0x30)
64#define DMAC_P_BASE1(c) __REG(DMAC_PHYS + (c) + 0x34)
65#define DMAC_P_CURRENT1(c) __REG(DMAC_PHYS + (c) + 0x38)
66
67#define DMAC_PCONTROL_ENABLE (1<<4)
68
69#define DMAC_PORT_USB 0
70#define DMAC_PORT_SDMMC 1
71#define DMAC_PORT_AC97_1 2
72#define DMAC_PORT_AC97_2 3
73#define DMAC_PORT_AC97_3 4
74#define DMAC_PORT_UART1 6
75#define DMAC_PORT_UART2 7
76#define DMAC_PORT_UART3 8
77
78#define DMAC_PSTATUS_CURRSTATE_SHIFT 4
79#define DMAC_PSTATUS_CURRSTATE_MASK 0x3
80
81#define DMAC_PSTATUS_NEXTBUF (1<<6)
82#define DMAC_PSTATUS_STALLRINT (1<<0)
83
84#define DMAC_INT_CHE (1<<3)
85#define DMAC_INT_NFB (1<<1)
86#define DMAC_INT_STALL (1<<0)
diff --git a/include/asm-arm/arch-lh7a40x/hardware.h b/include/asm-arm/arch-lh7a40x/hardware.h
index aeb07c162e25..e9ff74fd7939 100644
--- a/include/asm-arm/arch-lh7a40x/hardware.h
+++ b/include/asm-arm/arch-lh7a40x/hardware.h
@@ -13,6 +13,8 @@
13#ifndef __ASM_ARCH_HARDWARE_H 13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H 14#define __ASM_ARCH_HARDWARE_H
15 15
16#include <asm/sizes.h> /* Added for the sake of amba-clcd driver */
17
16#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff)) 18#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff))
17#define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff)) 19#define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff))
18 20
@@ -53,6 +55,8 @@ typedef struct { volatile u8 offset[4096]; } __regbase8;
53 55
54#endif 56#endif
55 57
58#define MASK_AND_SET(v,m,s) (v) = ((v)&~(m))|(s)
59
56#include "registers.h" 60#include "registers.h"
57 61
58#endif /* _ASM_ARCH_HARDWARE_H */ 62#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-lh7a40x/irqs.h b/include/asm-arm/arch-lh7a40x/irqs.h
index f91f3e59f3ab..7e8a217200e9 100644
--- a/include/asm-arm/arch-lh7a40x/irqs.h
+++ b/include/asm-arm/arch-lh7a40x/irqs.h
@@ -154,9 +154,10 @@
154#if !defined (IRQ_GPIO0INTR) 154#if !defined (IRQ_GPIO0INTR)
155# define IRQ_GPIO0INTR IRQ_GPIO0FIQ 155# define IRQ_GPIO0INTR IRQ_GPIO0FIQ
156#endif 156#endif
157#define IRQ_TICK IRQ_TINTR 157#define IRQ_TICK IRQ_TINTR
158#define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */ 158#define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */
159#define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */ 159#define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */
160#define IRQ_USB IRQ_USBINTR /* USB device */
160 161
161#ifdef CONFIG_MACH_KEV7A400 162#ifdef CONFIG_MACH_KEV7A400
162# define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */ 163# define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */
@@ -191,6 +192,10 @@
191# define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */ 192# define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */
192#endif 193#endif
193 194
195#if defined (CONFIG_MACH_LPD7A400)
196# define IRQ_TOUCH IRQ_LPD7A400_TS
197#endif
198
194#define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD) 199#define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD)
195 200
196#endif 201#endif
diff --git a/include/asm-arm/arch-lh7a40x/registers.h b/include/asm-arm/arch-lh7a40x/registers.h
index 2edb22e35450..544307bb87a2 100644
--- a/include/asm-arm/arch-lh7a40x/registers.h
+++ b/include/asm-arm/arch-lh7a40x/registers.h
@@ -18,7 +18,7 @@
18 18
19 /* Physical register base addresses */ 19 /* Physical register base addresses */
20 20
21#define AC97_PHYS (0x80000000) /* AC97 Controller */ 21#define AC97C_PHYS (0x80000000) /* AC97 Controller */
22#define MMC_PHYS (0x80000100) /* Multimedia Card Controller */ 22#define MMC_PHYS (0x80000100) /* Multimedia Card Controller */
23#define USB_PHYS (0x80000200) /* USB Client */ 23#define USB_PHYS (0x80000200) /* USB Client */
24#define SCI_PHYS (0x80000300) /* Secure Card Interface */ 24#define SCI_PHYS (0x80000300) /* Secure Card Interface */
@@ -35,6 +35,8 @@
35#define RTC_PHYS (0x80000d00) /* Real-time Clock */ 35#define RTC_PHYS (0x80000d00) /* Real-time Clock */
36#define GPIO_PHYS (0x80000e00) /* General Purpose IO */ 36#define GPIO_PHYS (0x80000e00) /* General Purpose IO */
37#define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */ 37#define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */
38#define HRTFTC_PHYS (0x80001000) /* High-res TFT Controller (LH7A400) */
39#define ALI_PHYS (0x80001000) /* Advanced LCD Interface (LH7A404) */
38#define WDT_PHYS (0x80001400) /* Watchdog Timer */ 40#define WDT_PHYS (0x80001400) /* Watchdog Timer */
39#define SMC_PHYS (0x80002000) /* Static Memory Controller */ 41#define SMC_PHYS (0x80002000) /* Static Memory Controller */
40#define SDRC_PHYS (0x80002400) /* SDRAM Controller */ 42#define SDRC_PHYS (0x80002400) /* SDRAM Controller */
@@ -43,6 +45,7 @@
43 45
44 /* Physical registers of the LH7A404 */ 46 /* Physical registers of the LH7A404 */
45 47
48#define ADC_PHYS (0x80001300) /* A/D & Touchscreen Controller */
46#define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */ 49#define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */
47#define USBH_PHYS (0x80009000) /* USB OHCI host controller */ 50#define USBH_PHYS (0x80009000) /* USB OHCI host controller */
48#define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */ 51#define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */
@@ -53,10 +56,32 @@
53 56
54 /* Clock/State Controller register */ 57 /* Clock/State Controller register */
55 58
59#define CSC_PWRSR __REG(CSC_PHYS + 0x00) /* Reset register & ID */
56#define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */ 60#define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */
61#define CSC_CLKSET __REG(CSC_PHYS + 0x20) /* Clock speed control */
62#define CSC_USBDRESET __REG(CSC_PHYS + 0x4c) /* USB Device resets */
57 63
58#define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */ 64#define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */
59 65#define CSC_PWRCNT_DMAC_M2M1_EN (1<<27)
66#define CSC_PWRCNT_DMAC_M2M0_EN (1<<26)
67#define CSC_PWRCNT_DMAC_M2P8_EN (1<<25)
68#define CSC_PWRCNT_DMAC_M2P9_EN (1<<24)
69#define CSC_PWRCNT_DMAC_M2P6_EN (1<<23)
70#define CSC_PWRCNT_DMAC_M2P7_EN (1<<22)
71#define CSC_PWRCNT_DMAC_M2P4_EN (1<<21)
72#define CSC_PWRCNT_DMAC_M2P5_EN (1<<20)
73#define CSC_PWRCNT_DMAC_M2P2_EN (1<<19)
74#define CSC_PWRCNT_DMAC_M2P3_EN (1<<18)
75#define CSC_PWRCNT_DMAC_M2P0_EN (1<<17)
76#define CSC_PWRCNT_DMAC_M2P1_EN (1<<16)
77
78#define CSC_PWRSR_CHIPMAN_SHIFT (24)
79#define CSC_PWRSR_CHIPMAN_MASK (0xff)
80#define CSC_PWRSR_CHIPID_SHIFT (16)
81#define CSC_PWRSR_CHIPID_MASK (0xff)
82
83#define CSC_USBDRESET_APBRESETREG (1<<1)
84#define CSC_USBDRESET_IORESETREG (1<<0)
60 85
61 /* Interrupt Controller registers */ 86 /* Interrupt Controller registers */
62 87
@@ -109,6 +134,13 @@
109#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */ 134#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
110#define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */ 135#define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
111#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */ 136#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
137#define GPIO_PINMUX __REG(GPIO_PHYS + 0x2c)
138#define GPIO_PADD __REG(GPIO_PHYS + 0x10)
139#define GPIO_PAD __REG(GPIO_PHYS + 0x00)
140#define GPIO_PCD __REG(GPIO_PHYS + 0x08)
141#define GPIO_PCDD __REG(GPIO_PHYS + 0x18)
142#define GPIO_PEDD __REG(GPIO_PHYS + 0x24)
143#define GPIO_PED __REG(GPIO_PHYS + 0x20)
112 144
113 145
114 /* Static Memory Controller registers */ 146 /* Static Memory Controller registers */
@@ -138,20 +170,21 @@
138#endif 170#endif
139 171
140#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) 172#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
141# define CPLD_CONTROL __REG8(CPLD02_PHYS)
142# define CPLD_SPI_DATA __REG8(CPLD06_PHYS)
143# define CPLD_SPI_CONTROL __REG8(CPLD08_PHYS)
144# define CPLD_SPI_EEPROM __REG8(CPLD0A_PHYS)
145# define CPLD_INTERRUPTS __REG8(CPLD0C_PHYS) /* IRQ mask/status */
146# define CPLD_BOOT_MODE __REG8(CPLD0E_PHYS)
147# define CPLD_FLASH __REG8(CPLD10_PHYS)
148# define CPLD_POWER_MGMT __REG8(CPLD12_PHYS)
149# define CPLD_REVISION __REG8(CPLD14_PHYS)
150# define CPLD_GPIO_EXT __REG8(CPLD16_PHYS)
151# define CPLD_GPIO_DATA __REG8(CPLD18_PHYS)
152# define CPLD_GPIO_DIR __REG8(CPLD1A_PHYS)
153#endif
154 173
174# define CPLD_CONTROL __REG16(CPLD02_PHYS)
175# define CPLD_SPI_DATA __REG16(CPLD06_PHYS)
176# define CPLD_SPI_CONTROL __REG16(CPLD08_PHYS)
177# define CPLD_SPI_EEPROM __REG16(CPLD0A_PHYS)
178# define CPLD_INTERRUPTS __REG16(CPLD0C_PHYS) /* IRQ mask/status */
179# define CPLD_BOOT_MODE __REG16(CPLD0E_PHYS)
180# define CPLD_FLASH __REG16(CPLD10_PHYS)
181# define CPLD_POWER_MGMT __REG16(CPLD12_PHYS)
182# define CPLD_REVISION __REG16(CPLD14_PHYS)
183# define CPLD_GPIO_EXT __REG16(CPLD16_PHYS)
184# define CPLD_GPIO_DATA __REG16(CPLD18_PHYS)
185# define CPLD_GPIO_DIR __REG16(CPLD1A_PHYS)
186
187#endif
155 188
156 /* Timer registers */ 189 /* Timer registers */
157 190
@@ -190,4 +223,3 @@
190 223
191 224
192#endif /* _ASM_ARCH_REGISTERS_H */ 225#endif /* _ASM_ARCH_REGISTERS_H */
193
diff --git a/include/asm-arm/arch-lh7a40x/ssp.h b/include/asm-arm/arch-lh7a40x/ssp.h
new file mode 100644
index 000000000000..132b1c4d5ce6
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/ssp.h
@@ -0,0 +1,71 @@
1/* ssp.h
2 $Id$
3
4 written by Marc Singer
5 6 Dec 2004
6
7 Copyright (C) 2004 Marc Singer
8
9 -----------
10 DESCRIPTION
11 -----------
12
13 This SSP header is available throughout the kernel, for this
14 machine/architecture, because drivers that use it may be dispersed.
15
16 This file was cloned from the 7952x implementation. It would be
17 better to share them, but we're taking an easier approach for the
18 time being.
19
20*/
21
22#if !defined (__SSP_H__)
23# define __SSP_H__
24
25/* ----- Includes */
26
27/* ----- Types */
28
29struct ssp_driver {
30 int (*init) (void);
31 void (*exit) (void);
32 void (*acquire) (void);
33 void (*release) (void);
34 int (*configure) (int device, int mode, int speed,
35 int frame_size_write, int frame_size_read);
36 void (*chip_select) (int enable);
37 void (*set_callbacks) (void* handle,
38 irqreturn_t (*callback_tx)(void*),
39 irqreturn_t (*callback_rx)(void*));
40 void (*enable) (void);
41 void (*disable) (void);
42// int (*save_state) (void*);
43// void (*restore_state) (void*);
44 int (*read) (void);
45 int (*write) (u16 data);
46 int (*write_read) (u16 data);
47 void (*flush) (void);
48 void (*write_async) (void* pv, size_t cb);
49 size_t (*write_pos) (void);
50};
51
52 /* These modes are only available on the LH79524 */
53#define SSP_MODE_SPI (1)
54#define SSP_MODE_SSI (2)
55#define SSP_MODE_MICROWIRE (3)
56#define SSP_MODE_I2S (4)
57
58 /* CPLD SPI devices */
59#define DEVICE_EEPROM 0 /* Configuration eeprom */
60#define DEVICE_MAC 1 /* MAC eeprom (LPD79524) */
61#define DEVICE_CODEC 2 /* Audio codec */
62#define DEVICE_TOUCH 3 /* Touch screen (LPD79520) */
63
64/* ----- Globals */
65
66/* ----- Prototypes */
67
68//extern struct ssp_driver lh79520_i2s_driver;
69extern struct ssp_driver lh7a400_cpld_ssp_driver;
70
71#endif /* __SSP_H__ */
diff --git a/include/asm-arm/arch-lh7a40x/uncompress.h b/include/asm-arm/arch-lh7a40x/uncompress.h
index f8053346f608..3d1ce0426a33 100644
--- a/include/asm-arm/arch-lh7a40x/uncompress.h
+++ b/include/asm-arm/arch-lh7a40x/uncompress.h
@@ -16,7 +16,7 @@
16#ifndef UART_R_STATUS 16#ifndef UART_R_STATUS
17# define UART_R_STATUS (0x10) 17# define UART_R_STATUS (0x10)
18#endif 18#endif
19#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */ 19#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */
20 20
21 /* Access UART with physical addresses before MMU is setup */ 21 /* Access UART with physical addresses before MMU is setup */
22#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS)) 22#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS))
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 19:26:55 -0500