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-rw-r--r--arch/x86/kernel/cpu/perfctr-watchdog.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index 93fecd4b03de..54cdbf1a40f1 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -34,7 +34,7 @@ struct wd_ops {
34 u64 checkbit; 34 u64 checkbit;
35}; 35};
36 36
37static struct wd_ops *wd_ops; 37static const struct wd_ops *wd_ops;
38 38
39/* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's 39/* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
40 * offset from MSR_P4_BSU_ESCR0. It will be the max for all platforms (for now) 40 * offset from MSR_P4_BSU_ESCR0. It will be the max for all platforms (for now)
@@ -317,7 +317,7 @@ static void single_msr_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
317 write_watchdog_counter(wd->perfctr_msr, NULL, nmi_hz); 317 write_watchdog_counter(wd->perfctr_msr, NULL, nmi_hz);
318} 318}
319 319
320static struct wd_ops k7_wd_ops = { 320static const struct wd_ops k7_wd_ops = {
321 .reserve = single_msr_reserve, 321 .reserve = single_msr_reserve,
322 .unreserve = single_msr_unreserve, 322 .unreserve = single_msr_unreserve,
323 .setup = setup_k7_watchdog, 323 .setup = setup_k7_watchdog,
@@ -380,7 +380,7 @@ static void p6_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
380 write_watchdog_counter32(wd->perfctr_msr, NULL,nmi_hz); 380 write_watchdog_counter32(wd->perfctr_msr, NULL,nmi_hz);
381} 381}
382 382
383static struct wd_ops p6_wd_ops = { 383static const struct wd_ops p6_wd_ops = {
384 .reserve = single_msr_reserve, 384 .reserve = single_msr_reserve,
385 .unreserve = single_msr_unreserve, 385 .unreserve = single_msr_unreserve,
386 .setup = setup_p6_watchdog, 386 .setup = setup_p6_watchdog,
@@ -532,7 +532,7 @@ static void p4_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
532 write_watchdog_counter(wd->perfctr_msr, NULL, nmi_hz); 532 write_watchdog_counter(wd->perfctr_msr, NULL, nmi_hz);
533} 533}
534 534
535static struct wd_ops p4_wd_ops = { 535static const struct wd_ops p4_wd_ops = {
536 .reserve = p4_reserve, 536 .reserve = p4_reserve,
537 .unreserve = p4_unreserve, 537 .unreserve = p4_unreserve,
538 .setup = setup_p4_watchdog, 538 .setup = setup_p4_watchdog,
@@ -550,6 +550,8 @@ static struct wd_ops p4_wd_ops = {
550#define ARCH_PERFMON_NMI_EVENT_SEL ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL 550#define ARCH_PERFMON_NMI_EVENT_SEL ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
551#define ARCH_PERFMON_NMI_EVENT_UMASK ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK 551#define ARCH_PERFMON_NMI_EVENT_UMASK ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
552 552
553static struct wd_ops intel_arch_wd_ops;
554
553static int setup_intel_arch_watchdog(unsigned nmi_hz) 555static int setup_intel_arch_watchdog(unsigned nmi_hz)
554{ 556{
555 unsigned int ebx; 557 unsigned int ebx;
@@ -591,11 +593,11 @@ static int setup_intel_arch_watchdog(unsigned nmi_hz)
591 wd->perfctr_msr = perfctr_msr; 593 wd->perfctr_msr = perfctr_msr;
592 wd->evntsel_msr = evntsel_msr; 594 wd->evntsel_msr = evntsel_msr;
593 wd->cccr_msr = 0; //unused 595 wd->cccr_msr = 0; //unused
594 wd_ops->checkbit = 1ULL << (eax.split.bit_width - 1); 596 intel_arch_wd_ops.checkbit = 1ULL << (eax.split.bit_width - 1);
595 return 1; 597 return 1;
596} 598}
597 599
598static struct wd_ops intel_arch_wd_ops = { 600static struct wd_ops intel_arch_wd_ops __read_mostly = {
599 .reserve = single_msr_reserve, 601 .reserve = single_msr_reserve,
600 .unreserve = single_msr_unreserve, 602 .unreserve = single_msr_unreserve,
601 .setup = setup_intel_arch_watchdog, 603 .setup = setup_intel_arch_watchdog,