7 files changed, 68 insertions, 7 deletions

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 06448a9656dc..3e004161ebd5 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -199,7 +199,14 @@ static inline void check_wait(void)
                 if ((c->processor_id & 0xff) <= 0x64)
                         break;
 
-                cpu_wait = r4k_wait;
+                /*
+                 * Another rev is incremeting c0_count at a reduced clock
+                 * rate while in WAIT mode.  So we basically have the choice
+                 * between using the cp0 timer as clocksource or avoiding
+                 * the WAIT instruction.  Until more details are known,
+                 * disable the use of WAIT for 20Kc entirely.
+                   cpu_wait = r4k_wait;
+                 */
                 break;
         case CPU_RM9000:
                 if ((c->processor_id & 0x00ff) >= 0x40)
diff --git a/arch/mips/kernel/rtlx.c b/arch/mips/kernel/rtlx.c
index aab89e97abb5..1ba00c15505b 100644
--- a/arch/mips/kernel/rtlx.c
+++ b/arch/mips/kernel/rtlx.c
@@ -56,8 +56,6 @@ static struct chan_waitqueues {
         struct mutex mutex;
 } channel_wqs[RTLX_CHANNELS];
 
-static struct irqaction irq;
-static int irq_num;
 static struct vpe_notifications notify;
 static int sp_stopping = 0;
 
@@ -111,7 +109,7 @@ static void __used dump_rtlx(void)
 static int rtlx_init(struct rtlx_info *rtlxi)
 {
         if (rtlxi->id != RTLX_ID) {
-                printk(KERN_ERR "no valid RTLX id at 0x%p 0x%x\n", rtlxi, rtlxi->id);
+                printk(KERN_ERR "no valid RTLX id at 0x%p 0x%lx\n", rtlxi, rtlxi->id);
                 return -ENOEXEC;
         }
 
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index 53d7a977193c..118be24224f2 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -375,7 +375,7 @@ EXPORT(sysn32_call_table)
         PTR     sys_mkdirat
         PTR     sys_mknodat
         PTR     sys_fchownat
-        PTR     sys_futimesat                   /* 6255 */
+        PTR     compat_sys_futimesat            /* 6255 */
         PTR     sys_newfstatat
         PTR     sys_unlinkat
         PTR     sys_renameat
diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c
index d48d1d5bea0a..9a5596bf8571 100644
--- a/arch/mips/kernel/time.c
+++ b/arch/mips/kernel/time.c
@@ -16,6 +16,7 @@
 #include <linux/init.h>
 #include <linux/sched.h>
 #include <linux/param.h>
+#include <linux/profile.h>
 #include <linux/time.h>
 #include <linux/timex.h>
 #include <linux/smp.h>
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 97aeb8c4e601..b73f21823c5e 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -256,7 +256,7 @@ asmlinkage void plat_irq_dispatch(void)
 
         if (irq == MIPSCPU_INT_I8259A)
                 malta_hw0_irqdispatch();
-        else if (irq > 0)
+        else if (irq >= 0)
                 do_IRQ(MIPS_CPU_IRQ_BASE + irq);
         else
                 spurious_interrupt();
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 9cb39644b6f1..6c425b052442 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -58,6 +58,21 @@ static __init int __maybe_unused r10000_llsc_war(void)
 }
 
 /*
+ * Found by experiment: At least some revisions of the 4kc throw under
+ * some circumstances a machine check exception, triggered by invalid
+ * values in the index register.  Delaying the tlbp instruction until
+ * after the next branch,  plus adding an additional nop in front of
+ * tlbwi/tlbwr avoids the invalid index register values. Nobody knows
+ * why; it's not an issue caused by the core RTL.
+ *
+ */
+static __init int __attribute__((unused)) m4kc_tlbp_war(void)
+{
+        return (current_cpu_data.processor_id & 0xffff00) ==
+               (PRID_COMP_MIPS | PRID_IMP_4KC);
+}
+
+/*
  * A little micro-assembler, intended for TLB refill handler
  * synthesizing. It is intentionally kept simple, does only support
  * a subset of instructions, and does not try to hide pipeline effects
@@ -894,6 +909,8 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
         case CPU_20KC:
         case CPU_25KF:
         case CPU_LOONGSON2:
+                if (m4kc_tlbp_war())
+                        i_nop(p);
                 tlbw(p);
                 break;
 
@@ -1705,7 +1722,8 @@ build_r4000_tlbchange_handler_head(u32 **p, struct label **l,
         l_smp_pgtable_change(l, *p);
 # endif
         iPTE_LW(p, l, pte, ptr); /* get even pte */
-        build_tlb_probe_entry(p);
+        if (!m4kc_tlbp_war())
+                build_tlb_probe_entry(p);
 }
 
 static void __init
@@ -1747,6 +1765,8 @@ static void __init build_r4000_tlb_load_handler(void)
 
         build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
         build_pte_present(&p, &l, &r, K0, K1, label_nopage_tlbl);
+        if (m4kc_tlbp_war())
+                build_tlb_probe_entry(&p);
         build_make_valid(&p, &r, K0, K1);
         build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
 
@@ -1781,6 +1801,8 @@ static void __init build_r4000_tlb_store_handler(void)
 
         build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
         build_pte_writable(&p, &l, &r, K0, K1, label_nopage_tlbs);
+        if (m4kc_tlbp_war())
+                build_tlb_probe_entry(&p);
         build_make_write(&p, &r, K0, K1);
         build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
 
@@ -1815,6 +1837,8 @@ static void __init build_r4000_tlb_modify_handler(void)
 
         build_r4000_tlbchange_handler_head(&p, &l, &r, K0, K1);
         build_pte_modifiable(&p, &l, &r, K0, K1, label_nopage_tlbm);
+        if (m4kc_tlbp_war())
+                build_tlb_probe_entry(&p);
         /* Present and writable bits set, set accessed and dirty bits. */
         build_make_write(&p, &r, K0, K1);
         build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1);
diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h
index 2b928577be5d..a77128362a7d 100644
--- a/include/asm-mips/mach-generic/ide.h
+++ b/include/asm-mips/mach-generic/ide.h
@@ -29,6 +29,35 @@
 
 #define IDE_ARCH_OBSOLETE_DEFAULTS
 
+static __inline__ int ide_probe_legacy(void)
+{
+#ifdef CONFIG_PCI
+        struct pci_dev *dev;
+        /*
+         * This can be called on the ide_setup() path, super-early in
+         * boot.  But the down_read() will enable local interrupts,
+         * which can cause some machines to crash.  So here we detect
+         * and flag that situation and bail out early.
+         */
+        if (no_pci_devices())
+                return 0;
+        dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL);
+        if (dev)
+                goto found;
+        dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
+        if (dev)
+                goto found;
+        return 0;
+found:
+        pci_dev_put(dev);
+        return 1;
+#elif defined(CONFIG_EISA) || defined(CONFIG_ISA)
+        return 1;
+#else
+        return 0;
+#endif
+}
+
 static __inline__ int ide_default_irq(unsigned long base)
 {
         switch (base) {
@@ -45,6 +74,8 @@ static __inline__ int ide_default_irq(unsigned long base)
 
 static __inline__ unsigned long ide_default_io_base(int index)
 {
+        if (!ide_probe_legacy())
+                return 0;
         /*
          *      If PCI is present then it is not safe to poke around
          *      the other legacy IDE ports. Only 0x1f0 and 0x170 are