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-rw-r--r--arch/sh/drivers/dma/Kconfig8
-rw-r--r--arch/sh/drivers/dma/dma-sh.c172
-rw-r--r--arch/sh/drivers/dma/dma-sh.h75
-rw-r--r--arch/sh/include/asm/dma-sh.h117
-rw-r--r--arch/sh/include/asm/dma.h4
-rw-r--r--arch/sh/include/cpu-sh3/cpu/dma.h17
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-sh4a.h94
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma-sh7780.h39
-rw-r--r--arch/sh/include/cpu-sh4/cpu/dma.h30
9 files changed, 352 insertions, 204 deletions
diff --git a/arch/sh/drivers/dma/Kconfig b/arch/sh/drivers/dma/Kconfig
index 01936368b8b0..57d95fce0464 100644
--- a/arch/sh/drivers/dma/Kconfig
+++ b/arch/sh/drivers/dma/Kconfig
@@ -12,10 +12,10 @@ config SH_DMA
12config NR_ONCHIP_DMA_CHANNELS 12config NR_ONCHIP_DMA_CHANNELS
13 int 13 int
14 depends on SH_DMA 14 depends on SH_DMA
15 default "6" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721 15 default "4" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7750S
16 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R 16 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || CPU_SUBTYPE_SH7760
17 default "12" if CPU_SUBTYPE_SH7780 17 default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
18 default "4" 18 default "6"
19 help 19 help
20 This allows you to specify the number of channels that the on-chip 20 This allows you to specify the number of channels that the on-chip
21 DMAC supports. This will be 4 for SH7750/SH7751 and 8 for the 21 DMAC supports. This will be 4 for SH7750/SH7751 and 8 for the
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c
index 50887a592dd0..ab7b18dcbaba 100644
--- a/arch/sh/drivers/dma/dma-sh.c
+++ b/arch/sh/drivers/dma/dma-sh.c
@@ -17,28 +17,23 @@
17#include <mach-dreamcast/mach/dma.h> 17#include <mach-dreamcast/mach/dma.h>
18#include <asm/dma.h> 18#include <asm/dma.h>
19#include <asm/io.h> 19#include <asm/io.h>
20#include "dma-sh.h" 20#include <asm/dma-sh.h>
21 21
22static int dmte_irq_map[] = { 22#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
23 DMTE0_IRQ, 23 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
24 DMTE1_IRQ, 24 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
25 DMTE2_IRQ, 25 defined(CONFIG_CPU_SUBTYPE_SH7785)
26 DMTE3_IRQ, 26#define DMAC_IRQ_MULTI 1
27#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
28 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
29 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
30 defined(CONFIG_CPU_SUBTYPE_SH7760) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7780)
33 DMTE4_IRQ,
34 DMTE5_IRQ,
35#endif 27#endif
36#if defined(CONFIG_CPU_SUBTYPE_SH7751R) || \ 28
37 defined(CONFIG_CPU_SUBTYPE_SH7760) || \ 29#if defined(DMAE1_IRQ)
38 defined(CONFIG_CPU_SUBTYPE_SH7780) 30#define NR_DMAE 2
39 DMTE6_IRQ, 31#else
40 DMTE7_IRQ, 32#define NR_DMAE 1
41#endif 33#endif
34
35static const char *dmae_name[] = {
36 "DMAC Address Error0", "DMAC Address Error1"
42}; 37};
43 38
44static inline unsigned int get_dmte_irq(unsigned int chan) 39static inline unsigned int get_dmte_irq(unsigned int chan)
@@ -46,7 +41,14 @@ static inline unsigned int get_dmte_irq(unsigned int chan)
46 unsigned int irq = 0; 41 unsigned int irq = 0;
47 if (chan < ARRAY_SIZE(dmte_irq_map)) 42 if (chan < ARRAY_SIZE(dmte_irq_map))
48 irq = dmte_irq_map[chan]; 43 irq = dmte_irq_map[chan];
44
45#if defined(DMAC_IRQ_MULTI)
46 if (irq > DMTE6_IRQ)
47 return DMTE6_IRQ;
48 return DMTE0_IRQ;
49#else
49 return irq; 50 return irq;
51#endif
50} 52}
51 53
52/* 54/*
@@ -59,7 +61,7 @@ static inline unsigned int get_dmte_irq(unsigned int chan)
59 */ 61 */
60static inline unsigned int calc_xmit_shift(struct dma_channel *chan) 62static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
61{ 63{
62 u32 chcr = ctrl_inl(CHCR[chan->chan]); 64 u32 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
63 65
64 return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT]; 66 return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
65} 67}
@@ -75,13 +77,13 @@ static irqreturn_t dma_tei(int irq, void *dev_id)
75 struct dma_channel *chan = dev_id; 77 struct dma_channel *chan = dev_id;
76 u32 chcr; 78 u32 chcr;
77 79
78 chcr = ctrl_inl(CHCR[chan->chan]); 80 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
79 81
80 if (!(chcr & CHCR_TE)) 82 if (!(chcr & CHCR_TE))
81 return IRQ_NONE; 83 return IRQ_NONE;
82 84
83 chcr &= ~(CHCR_IE | CHCR_DE); 85 chcr &= ~(CHCR_IE | CHCR_DE);
84 ctrl_outl(chcr, CHCR[chan->chan]); 86 ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
85 87
86 wake_up(&chan->wait_queue); 88 wake_up(&chan->wait_queue);
87 89
@@ -94,7 +96,12 @@ static int sh_dmac_request_dma(struct dma_channel *chan)
94 return 0; 96 return 0;
95 97
96 return request_irq(get_dmte_irq(chan->chan), dma_tei, 98 return request_irq(get_dmte_irq(chan->chan), dma_tei,
97 IRQF_DISABLED, chan->dev_id, chan); 99#if defined(DMAC_IRQ_MULTI)
100 IRQF_SHARED,
101#else
102 IRQF_DISABLED,
103#endif
104 chan->dev_id, chan);
98} 105}
99 106
100static void sh_dmac_free_dma(struct dma_channel *chan) 107static void sh_dmac_free_dma(struct dma_channel *chan)
@@ -115,7 +122,7 @@ sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
115 chan->flags &= ~DMA_TEI_CAPABLE; 122 chan->flags &= ~DMA_TEI_CAPABLE;
116 } 123 }
117 124
118 ctrl_outl(chcr, CHCR[chan->chan]); 125 ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
119 126
120 chan->flags |= DMA_CONFIGURED; 127 chan->flags |= DMA_CONFIGURED;
121 return 0; 128 return 0;
@@ -126,13 +133,13 @@ static void sh_dmac_enable_dma(struct dma_channel *chan)
126 int irq; 133 int irq;
127 u32 chcr; 134 u32 chcr;
128 135
129 chcr = ctrl_inl(CHCR[chan->chan]); 136 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
130 chcr |= CHCR_DE; 137 chcr |= CHCR_DE;
131 138
132 if (chan->flags & DMA_TEI_CAPABLE) 139 if (chan->flags & DMA_TEI_CAPABLE)
133 chcr |= CHCR_IE; 140 chcr |= CHCR_IE;
134 141
135 ctrl_outl(chcr, CHCR[chan->chan]); 142 ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
136 143
137 if (chan->flags & DMA_TEI_CAPABLE) { 144 if (chan->flags & DMA_TEI_CAPABLE) {
138 irq = get_dmte_irq(chan->chan); 145 irq = get_dmte_irq(chan->chan);
@@ -150,9 +157,9 @@ static void sh_dmac_disable_dma(struct dma_channel *chan)
150 disable_irq(irq); 157 disable_irq(irq);
151 } 158 }
152 159
153 chcr = ctrl_inl(CHCR[chan->chan]); 160 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR);
154 chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE); 161 chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
155 ctrl_outl(chcr, CHCR[chan->chan]); 162 ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR));
156} 163}
157 164
158static int sh_dmac_xfer_dma(struct dma_channel *chan) 165static int sh_dmac_xfer_dma(struct dma_channel *chan)
@@ -183,12 +190,13 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
183 */ 190 */
184 if (chan->sar || (mach_is_dreamcast() && 191 if (chan->sar || (mach_is_dreamcast() &&
185 chan->chan == PVR2_CASCADE_CHAN)) 192 chan->chan == PVR2_CASCADE_CHAN))
186 ctrl_outl(chan->sar, SAR[chan->chan]); 193 ctrl_outl(chan->sar, (dma_base_addr[chan->chan]+SAR));
187 if (chan->dar || (mach_is_dreamcast() && 194 if (chan->dar || (mach_is_dreamcast() &&
188 chan->chan == PVR2_CASCADE_CHAN)) 195 chan->chan == PVR2_CASCADE_CHAN))
189 ctrl_outl(chan->dar, DAR[chan->chan]); 196 ctrl_outl(chan->dar, (dma_base_addr[chan->chan] + DAR));
190 197
191 ctrl_outl(chan->count >> calc_xmit_shift(chan), DMATCR[chan->chan]); 198 ctrl_outl(chan->count >> calc_xmit_shift(chan),
199 (dma_base_addr[chan->chan] + TCR));
192 200
193 sh_dmac_enable_dma(chan); 201 sh_dmac_enable_dma(chan);
194 202
@@ -197,36 +205,26 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
197 205
198static int sh_dmac_get_dma_residue(struct dma_channel *chan) 206static int sh_dmac_get_dma_residue(struct dma_channel *chan)
199{ 207{
200 if (!(ctrl_inl(CHCR[chan->chan]) & CHCR_DE)) 208 if (!(ctrl_inl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE))
201 return 0; 209 return 0;
202 210
203 return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan); 211 return ctrl_inl(dma_base_addr[chan->chan] + TCR)
212 << calc_xmit_shift(chan);
204} 213}
205 214
206#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 215static inline int dmaor_reset(int no)
207 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
208 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
209 defined(CONFIG_CPU_SUBTYPE_SH7709)
210#define dmaor_read_reg() ctrl_inw(DMAOR)
211#define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
212#else
213#define dmaor_read_reg() ctrl_inl(DMAOR)
214#define dmaor_write_reg(data) ctrl_outl(data, DMAOR)
215#endif
216
217static inline int dmaor_reset(void)
218{ 216{
219 unsigned long dmaor = dmaor_read_reg(); 217 unsigned long dmaor = dmaor_read_reg(no);
220 218
221 /* Try to clear the error flags first, incase they are set */ 219 /* Try to clear the error flags first, incase they are set */
222 dmaor &= ~(DMAOR_NMIF | DMAOR_AE); 220 dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
223 dmaor_write_reg(dmaor); 221 dmaor_write_reg(no, dmaor);
224 222
225 dmaor |= DMAOR_INIT; 223 dmaor |= DMAOR_INIT;
226 dmaor_write_reg(dmaor); 224 dmaor_write_reg(no, dmaor);
227 225
228 /* See if we got an error again */ 226 /* See if we got an error again */
229 if ((dmaor_read_reg() & (DMAOR_AE | DMAOR_NMIF))) { 227 if ((dmaor_read_reg(no) & (DMAOR_AE | DMAOR_NMIF))) {
230 printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n"); 228 printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
231 return -EINVAL; 229 return -EINVAL;
232 } 230 }
@@ -237,10 +235,33 @@ static inline int dmaor_reset(void)
237#if defined(CONFIG_CPU_SH4) 235#if defined(CONFIG_CPU_SH4)
238static irqreturn_t dma_err(int irq, void *dummy) 236static irqreturn_t dma_err(int irq, void *dummy)
239{ 237{
240 dmaor_reset(); 238#if defined(DMAC_IRQ_MULTI)
239 int cnt = 0;
240 switch (irq) {
241#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
242 case DMTE6_IRQ:
243 cnt++;
244#endif
245 case DMTE0_IRQ:
246 if (dmaor_read_reg(cnt) & (DMAOR_NMIF | DMAOR_AE)) {
247 disable_irq(irq);
248 /* DMA multi and error IRQ */
249 return IRQ_HANDLED;
250 }
251 default:
252 return IRQ_NONE;
253 }
254#else
255 dmaor_reset(0);
256#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
257 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
258 defined(CONFIG_CPU_SUBTYPE_SH7785)
259 dmaor_reset(1);
260#endif
241 disable_irq(irq); 261 disable_irq(irq);
242 262
243 return IRQ_HANDLED; 263 return IRQ_HANDLED;
264#endif
244} 265}
245#endif 266#endif
246 267
@@ -259,24 +280,57 @@ static struct dma_info sh_dmac_info = {
259 .flags = DMAC_CHANNELS_TEI_CAPABLE, 280 .flags = DMAC_CHANNELS_TEI_CAPABLE,
260}; 281};
261 282
283static unsigned int get_dma_error_irq(int n)
284{
285#if defined(DMAC_IRQ_MULTI)
286 return (n == 0) ? get_dmte_irq(0) : get_dmte_irq(6);
287#else
288 return (n == 0) ? DMAE0_IRQ :
289#if defined(DMAE1_IRQ)
290 DMAE1_IRQ;
291#else
292 -1;
293#endif
294#endif
295}
296
262static int __init sh_dmac_init(void) 297static int __init sh_dmac_init(void)
263{ 298{
264 struct dma_info *info = &sh_dmac_info; 299 struct dma_info *info = &sh_dmac_info;
265 int i; 300 int i;
266 301
267#ifdef CONFIG_CPU_SH4 302#ifdef CONFIG_CPU_SH4
268 i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0); 303 int n;
269 if (unlikely(i < 0)) 304
270 return i; 305 for (n = 0; n < NR_DMAE; n++) {
306 i = request_irq(get_dma_error_irq(n), dma_err,
307#if defined(DMAC_IRQ_MULTI)
308 IRQF_SHARED,
309#else
310 IRQF_DISABLED,
271#endif 311#endif
312 dmae_name[n], (void *)dmae_name[n]);
313 if (unlikely(i < 0)) {
314 printk(KERN_ERR "%s request_irq fail\n", dmae_name[n]);
315 return i;
316 }
317 }
318#endif /* CONFIG_CPU_SH4 */
272 319
273 /* 320 /*
274 * Initialize DMAOR, and clean up any error flags that may have 321 * Initialize DMAOR, and clean up any error flags that may have
275 * been set. 322 * been set.
276 */ 323 */
277 i = dmaor_reset(); 324 i = dmaor_reset(0);
325 if (unlikely(i != 0))
326 return i;
327#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
328 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
329 defined(CONFIG_CPU_SUBTYPE_SH7785)
330 i = dmaor_reset(1);
278 if (unlikely(i != 0)) 331 if (unlikely(i != 0))
279 return i; 332 return i;
333#endif
280 334
281 return register_dmac(info); 335 return register_dmac(info);
282} 336}
@@ -284,8 +338,12 @@ static int __init sh_dmac_init(void)
284static void __exit sh_dmac_exit(void) 338static void __exit sh_dmac_exit(void)
285{ 339{
286#ifdef CONFIG_CPU_SH4 340#ifdef CONFIG_CPU_SH4
287 free_irq(DMAE_IRQ, 0); 341 int n;
288#endif 342
343 for (n = 0; n < NR_DMAE; n++) {
344 free_irq(get_dma_error_irq(n), (void *)dmae_name[n]);
345 }
346#endif /* CONFIG_CPU_SH4 */
289 unregister_dmac(&sh_dmac_info); 347 unregister_dmac(&sh_dmac_info);
290} 348}
291 349
diff --git a/arch/sh/drivers/dma/dma-sh.h b/arch/sh/drivers/dma/dma-sh.h
deleted file mode 100644
index 05fecd5428e4..000000000000
--- a/arch/sh/drivers/dma/dma-sh.h
+++ /dev/null
@@ -1,75 +0,0 @@
1/*
2 * arch/sh/drivers/dma/dma-sh.h
3 *
4 * Copyright (C) 2000 Takashi YOSHII
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __DMA_SH_H
12#define __DMA_SH_H
13
14#include <cpu/dma.h>
15
16/* Definitions for the SuperH DMAC */
17#define REQ_L 0x00000000
18#define REQ_E 0x00080000
19#define RACK_H 0x00000000
20#define RACK_L 0x00040000
21#define ACK_R 0x00000000
22#define ACK_W 0x00020000
23#define ACK_H 0x00000000
24#define ACK_L 0x00010000
25#define DM_INC 0x00004000
26#define DM_DEC 0x00008000
27#define SM_INC 0x00001000
28#define SM_DEC 0x00002000
29#define RS_IN 0x00000200
30#define RS_OUT 0x00000300
31#define TS_BLK 0x00000040
32#define TM_BUR 0x00000020
33#define CHCR_DE 0x00000001
34#define CHCR_TE 0x00000002
35#define CHCR_IE 0x00000004
36
37/* DMAOR definitions */
38#define DMAOR_AE 0x00000004
39#define DMAOR_NMIF 0x00000002
40#define DMAOR_DME 0x00000001
41
42/*
43 * Define the default configuration for dual address memory-memory transfer.
44 * The 0x400 value represents auto-request, external->external.
45 */
46#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32)
47
48#define MAX_DMAC_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
49
50/*
51 * Subtypes that have fewer channels than this simply need to change
52 * CONFIG_NR_ONCHIP_DMA_CHANNELS. Likewise, subtypes with a larger number
53 * of channels should expand on this.
54 *
55 * For most subtypes we can easily figure these values out with some
56 * basic calculation, unfortunately on other subtypes these are more
57 * scattered, so we just leave it unrolled for simplicity.
58 */
59#define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \
60 SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30, \
61 SH_DMAC_BASE + 0x50, SH_DMAC_BASE + 0x60})
62#define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \
63 SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34, \
64 SH_DMAC_BASE + 0x54, SH_DMAC_BASE + 0x64})
65#define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \
66 SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38, \
67 SH_DMAC_BASE + 0x58, SH_DMAC_BASE + 0x68})
68#define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \
69 SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c, \
70 SH_DMAC_BASE + 0x5c, SH_DMAC_BASE + 0x6c})
71
72#define DMAOR (SH_DMAC_BASE + 0x40)
73
74#endif /* __DMA_SH_H */
75
diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h
new file mode 100644
index 000000000000..e873ecaa5065
--- /dev/null
+++ b/arch/sh/include/asm/dma-sh.h
@@ -0,0 +1,117 @@
1/*
2 * arch/sh/include/asm/dma-sh.h
3 *
4 * Copyright (C) 2000 Takashi YOSHII
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __DMA_SH_H
12#define __DMA_SH_H
13
14#include <cpu/dma.h>
15
16/* DMAOR contorl: The DMAOR access size is different by CPU.*/
17#if defined(CONFIG_CPU_SUBTYPE_SH7723) || \
18 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
19 defined(CONFIG_CPU_SUBTYPE_SH7785)
20#define dmaor_read_reg(n) \
21 (n ? ctrl_inw(SH_DMAC_BASE1 + DMAOR) \
22 : ctrl_inw(SH_DMAC_BASE0 + DMAOR))
23#define dmaor_write_reg(n, data) \
24 (n ? ctrl_outw(data, SH_DMAC_BASE1 + DMAOR) \
25 : ctrl_outw(data, SH_DMAC_BASE0 + DMAOR))
26#else /* Other CPU */
27#define dmaor_read_reg(n) ctrl_inw(SH_DMAC_BASE0 + DMAOR)
28#define dmaor_write_reg(n, data) ctrl_outw(data, SH_DMAC_BASE0 + DMAOR)
29#endif
30
31static int dmte_irq_map[] __maybe_unused = {
32#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 4)
33 DMTE0_IRQ,
34 DMTE0_IRQ + 1,
35 DMTE0_IRQ + 2,
36 DMTE0_IRQ + 3,
37#endif
38#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 6)
39 DMTE4_IRQ,
40 DMTE4_IRQ + 1,
41#endif
42#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 8)
43 DMTE6_IRQ,
44 DMTE6_IRQ + 1,
45#endif
46#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 12)
47 DMTE8_IRQ,
48 DMTE9_IRQ,
49 DMTE10_IRQ,
50 DMTE11_IRQ,
51#endif
52};
53
54/* Definitions for the SuperH DMAC */
55#define REQ_L 0x00000000
56#define REQ_E 0x00080000
57#define RACK_H 0x00000000
58#define RACK_L 0x00040000
59#define ACK_R 0x00000000
60#define ACK_W 0x00020000
61#define ACK_H 0x00000000
62#define ACK_L 0x00010000
63#define DM_INC 0x00004000
64#define DM_DEC 0x00008000
65#define SM_INC 0x00001000
66#define SM_DEC 0x00002000
67#define RS_IN 0x00000200
68#define RS_OUT 0x00000300
69#define TS_BLK 0x00000040
70#define TM_BUR 0x00000020
71#define CHCR_DE 0x00000001
72#define CHCR_TE 0x00000002
73#define CHCR_IE 0x00000004
74
75/* DMAOR definitions */
76#define DMAOR_AE 0x00000004
77#define DMAOR_NMIF 0x00000002
78#define DMAOR_DME 0x00000001
79
80/*
81 * Define the default configuration for dual address memory-memory transfer.
82 * The 0x400 value represents auto-request, external->external.
83 */
84#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32)
85
86/* DMA base address */
87static u32 dma_base_addr[] __maybe_unused = {
88#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 4)
89 SH_DMAC_BASE0 + 0x00, /* channel 0 */
90 SH_DMAC_BASE0 + 0x10,
91 SH_DMAC_BASE0 + 0x20,
92 SH_DMAC_BASE0 + 0x30,
93#endif
94#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 6)
95 SH_DMAC_BASE0 + 0x50,
96 SH_DMAC_BASE0 + 0x60,
97#endif
98#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 8)
99 SH_DMAC_BASE1 + 0x00,
100 SH_DMAC_BASE1 + 0x10,
101#endif
102#if (CONFIG_NR_ONCHIP_DMA_CHANNELS >= 12)
103 SH_DMAC_BASE1 + 0x20,
104 SH_DMAC_BASE1 + 0x30,
105 SH_DMAC_BASE1 + 0x50,
106 SH_DMAC_BASE1 + 0x60, /* channel 11 */
107#endif
108};
109
110/* DMA register */
111#define SAR 0x00
112#define DAR 0x04
113#define TCR 0x08
114#define CHCR 0x0C
115#define DMAOR 0x40
116
117#endif /* __DMA_SH_H */
diff --git a/arch/sh/include/asm/dma.h b/arch/sh/include/asm/dma.h
index beca7128e2ab..6bd178473878 100644
--- a/arch/sh/include/asm/dma.h
+++ b/arch/sh/include/asm/dma.h
@@ -25,9 +25,9 @@
25#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000) 25#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
26 26
27#ifdef CONFIG_NR_DMA_CHANNELS 27#ifdef CONFIG_NR_DMA_CHANNELS
28# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS) 28# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
29#else 29#else
30# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS) 30# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
31#endif 31#endif
32 32
33/* 33/*
diff --git a/arch/sh/include/cpu-sh3/cpu/dma.h b/arch/sh/include/cpu-sh3/cpu/dma.h
index 6813c3220a1d..0ea15f3f2363 100644
--- a/arch/sh/include/cpu-sh3/cpu/dma.h
+++ b/arch/sh/include/cpu-sh3/cpu/dma.h
@@ -1,22 +1,17 @@
1#ifndef __ASM_CPU_SH3_DMA_H 1#ifndef __ASM_CPU_SH3_DMA_H
2#define __ASM_CPU_SH3_DMA_H 2#define __ASM_CPU_SH3_DMA_H
3 3
4
5#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 4#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7721) 5 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
7#define SH_DMAC_BASE 0xa4010020 6 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
8#else 7 defined(CONFIG_CPU_SUBTYPE_SH7712)
9#define SH_DMAC_BASE 0xa4000020 8#define SH_DMAC_BASE0 0xa4010020
9#else /* SH7705/06/07/09 */
10#define SH_DMAC_BASE0 0xa4000020
10#endif 11#endif
11 12
12#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
13#define DMTE0_IRQ 48 13#define DMTE0_IRQ 48
14#define DMTE1_IRQ 49
15#define DMTE2_IRQ 50
16#define DMTE3_IRQ 51
17#define DMTE4_IRQ 76 14#define DMTE4_IRQ 76
18#define DMTE5_IRQ 77
19#endif
20 15
21/* Definitions for the SuperH DMAC */ 16/* Definitions for the SuperH DMAC */
22#define TM_BURST 0x00000020 17#define TM_BURST 0x00000020
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
new file mode 100644
index 000000000000..0ed5178fed69
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/dma-sh4a.h
@@ -0,0 +1,94 @@
1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
2#define __ASM_SH_CPU_SH4_DMA_SH7780_H
3
4#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
5 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7730)
7#define DMTE0_IRQ 48
8#define DMTE4_IRQ 76
9#define DMAE0_IRQ 78 /* DMA Error IRQ*/
10#define SH_DMAC_BASE0 0xFE008020
11#define SH_DMARS_BASE 0xFE009000
12#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7764)
14#define DMTE0_IRQ 34
15#define DMTE4_IRQ 44
16#define DMAE0_IRQ 38
17#define SH_DMAC_BASE0 0xFF608020
18#define SH_DMARS_BASE 0xFF609000
19#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
20#define DMTE0_IRQ 48 /* DMAC0A*/
21#define DMTE4_IRQ 40 /* DMAC0B */
22#define DMTE6_IRQ 42
23#define DMTE8_IRQ 76 /* DMAC1A */
24#define DMTE9_IRQ 77
25#define DMTE10_IRQ 72 /* DMAC1B */
26#define DMTE11_IRQ 73
27#define DMAE0_IRQ 78 /* DMA Error IRQ*/
28#define DMAE1_IRQ 74 /* DMA Error IRQ*/
29#define SH_DMAC_BASE0 0xFE008020
30#define SH_DMAC_BASE1 0xFDC08020
31#define SH_DMARS_BASE 0xFDC09000
32#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
33#define DMTE0_IRQ 34
34#define DMTE4_IRQ 44
35#define DMTE6_IRQ 46
36#define DMTE8_IRQ 92
37#define DMTE9_IRQ 93
38#define DMTE10_IRQ 94
39#define DMTE11_IRQ 95
40#define DMAE0_IRQ 38 /* DMA Error IRQ */
41#define SH_DMAC_BASE0 0xFC808020
42#define SH_DMAC_BASE1 0xFC818020
43#define SH_DMARS_BASE 0xFC809000
44#else /* SH7785 */
45#define DMTE0_IRQ 33
46#define DMTE4_IRQ 37
47#define DMTE6_IRQ 52
48#define DMTE8_IRQ 54
49#define DMTE9_IRQ 55
50#define DMTE10_IRQ 56
51#define DMTE11_IRQ 57
52#define DMAE0_IRQ 39 /* DMA Error IRQ0 */
53#define DMAE1_IRQ 58 /* DMA Error IRQ1 */
54#define SH_DMAC_BASE0 0xFC808020
55#define SH_DMAC_BASE1 0xFCC08020
56#define SH_DMARS_BASE 0xFC809000
57#endif
58
59#define REQ_HE 0x000000C0
60#define REQ_H 0x00000080
61#define REQ_LE 0x00000040
62#define TM_BURST 0x0000020
63#define TS_8 0x00000000
64#define TS_16 0x00000008
65#define TS_32 0x00000010
66#define TS_16BLK 0x00000018
67#define TS_32BLK 0x00100000
68
69/*
70 * The SuperH DMAC supports a number of transmit sizes, we list them here,
71 * with their respective values as they appear in the CHCR registers.
72 *
73 * Defaults to a 64-bit transfer size.
74 */
75enum {
76 XMIT_SZ_8BIT,
77 XMIT_SZ_16BIT,
78 XMIT_SZ_32BIT,
79 XMIT_SZ_128BIT,
80 XMIT_SZ_256BIT,
81};
82
83/*
84 * The DMA count is defined as the number of bytes to transfer.
85 */
86static unsigned int ts_shift[] __maybe_unused = {
87 [XMIT_SZ_8BIT] = 0,
88 [XMIT_SZ_16BIT] = 1,
89 [XMIT_SZ_32BIT] = 2,
90 [XMIT_SZ_128BIT] = 4,
91 [XMIT_SZ_256BIT] = 5,
92};
93
94#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h b/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h
deleted file mode 100644
index 71b426a6e482..000000000000
--- a/arch/sh/include/cpu-sh4/cpu/dma-sh7780.h
+++ /dev/null
@@ -1,39 +0,0 @@
1#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
2#define __ASM_SH_CPU_SH4_DMA_SH7780_H
3
4#define REQ_HE 0x000000C0
5#define REQ_H 0x00000080
6#define REQ_LE 0x00000040
7#define TM_BURST 0x0000020
8#define TS_8 0x00000000
9#define TS_16 0x00000008
10#define TS_32 0x00000010
11#define TS_16BLK 0x00000018
12#define TS_32BLK 0x00100000
13
14/*
15 * The SuperH DMAC supports a number of transmit sizes, we list them here,
16 * with their respective values as they appear in the CHCR registers.
17 *
18 * Defaults to a 64-bit transfer size.
19 */
20enum {
21 XMIT_SZ_8BIT,
22 XMIT_SZ_16BIT,
23 XMIT_SZ_32BIT,
24 XMIT_SZ_128BIT,
25 XMIT_SZ_256BIT,
26};
27
28/*
29 * The DMA count is defined as the number of bytes to transfer.
30 */
31static unsigned int ts_shift[] __maybe_unused = {
32 [XMIT_SZ_8BIT] = 0,
33 [XMIT_SZ_16BIT] = 1,
34 [XMIT_SZ_32BIT] = 2,
35 [XMIT_SZ_128BIT] = 4,
36 [XMIT_SZ_256BIT] = 5,
37};
38
39#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/arch/sh/include/cpu-sh4/cpu/dma.h b/arch/sh/include/cpu-sh4/cpu/dma.h
index 235b7cd1fc9a..bcb30246e85c 100644
--- a/arch/sh/include/cpu-sh4/cpu/dma.h
+++ b/arch/sh/include/cpu-sh4/cpu/dma.h
@@ -1,31 +1,29 @@
1#ifndef __ASM_CPU_SH4_DMA_H 1#ifndef __ASM_CPU_SH4_DMA_H
2#define __ASM_CPU_SH4_DMA_H 2#define __ASM_CPU_SH4_DMA_H
3 3
4#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
5
6/* SH7751/7760/7780 DMA IRQ sources */ 4/* SH7751/7760/7780 DMA IRQ sources */
7#define DMTE0_IRQ 34
8#define DMTE1_IRQ 35
9#define DMTE2_IRQ 36
10#define DMTE3_IRQ 37
11#define DMTE4_IRQ 44
12#define DMTE5_IRQ 45
13#define DMTE6_IRQ 46
14#define DMTE7_IRQ 47
15#define DMAE_IRQ 38
16 5
17#ifdef CONFIG_CPU_SH4A 6#ifdef CONFIG_CPU_SH4A
18#define SH_DMAC_BASE 0xfc808020
19 7
8#define DMAOR_INIT (DMAOR_DME)
20#define CHCR_TS_MASK 0x18 9#define CHCR_TS_MASK 0x18
21#define CHCR_TS_SHIFT 3 10#define CHCR_TS_SHIFT 3
22 11
23#include <cpu/dma-sh7780.h> 12#include <cpu/dma-sh4a.h>
24#else 13#else /* CONFIG_CPU_SH4A */
25#define SH_DMAC_BASE 0xffa00000 14/*
15 * SH7750/SH7751/SH7760
16 */
17#define DMTE0_IRQ 34
18#define DMTE4_IRQ 44
19#define DMTE6_IRQ 46
20#define DMAE0_IRQ 38
26 21
22#define DMAOR_INIT (0x8000|DMAOR_DME)
23#define SH_DMAC_BASE0 0xffa00000
24#define SH_DMAC_BASE1 0xffa00070
27/* Definitions for the SuperH DMAC */ 25/* Definitions for the SuperH DMAC */
28#define TM_BURST 0x0000080 26#define TM_BURST 0x00000080
29#define TS_8 0x00000010 27#define TS_8 0x00000010
30#define TS_16 0x00000020 28#define TS_16 0x00000020
31#define TS_32 0x00000030 29#define TS_32 0x00000030
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-12 13:23:00 -0500