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-rw-r--r--arch/sh/mm/cache-sh4.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index 6c36c2fb8199..226b190c5b9c 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -70,6 +70,20 @@ static void __init emit_cache_params(void)
70 boot_cpu_data.dcache.alias_mask, 70 boot_cpu_data.dcache.alias_mask,
71 boot_cpu_data.dcache.n_aliases); 71 boot_cpu_data.dcache.n_aliases);
72 72
73 /*
74 * Emit Secondary Cache parameters if the CPU has a probed L2.
75 */
76 if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
77 printk("S-cache : n_ways=%d n_sets=%d way_incr=%d\n",
78 boot_cpu_data.scache.ways,
79 boot_cpu_data.scache.sets,
80 boot_cpu_data.scache.way_incr);
81 printk("S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
82 boot_cpu_data.scache.entry_mask,
83 boot_cpu_data.scache.alias_mask,
84 boot_cpu_data.scache.n_aliases);
85 }
86
73 if (!__flush_dcache_segment_fn) 87 if (!__flush_dcache_segment_fn)
74 panic("unknown number of cache ways\n"); 88 panic("unknown number of cache ways\n");
75} 89}
@@ -81,6 +95,7 @@ void __init p3_cache_init(void)
81{ 95{
82 compute_alias(&boot_cpu_data.icache); 96 compute_alias(&boot_cpu_data.icache);
83 compute_alias(&boot_cpu_data.dcache); 97 compute_alias(&boot_cpu_data.dcache);
98 compute_alias(&boot_cpu_data.scache);
84 99
85 switch (boot_cpu_data.dcache.ways) { 100 switch (boot_cpu_data.dcache.ways) {
86 case 1: 101 case 1: