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-rw-r--r--sound/soc/s3c24xx/s3c24xx-i2s.c439
-rw-r--r--sound/soc/s3c24xx/s3c24xx-i2s.h35
2 files changed, 474 insertions, 0 deletions
diff --git a/sound/soc/s3c24xx/s3c24xx-i2s.c b/sound/soc/s3c24xx/s3c24xx-i2s.c
new file mode 100644
index 000000000000..df655a5db536
--- /dev/null
+++ b/sound/soc/s3c24xx/s3c24xx-i2s.c
@@ -0,0 +1,439 @@
1/*
2 * s3c24xx-i2s.c -- ALSA Soc Audio Layer
3 *
4 * (c) 2006 Wolfson Microelectronics PLC.
5 * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
6 *
7 * (c) 2004-2005 Simtec Electronics
8 * http://armlinux.simtec.co.uk/
9 * Ben Dooks <ben@simtec.co.uk>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 *
17 * Revision history
18 * 11th Dec 2006 Merged with Simtec driver
19 * 10th Nov 2006 Initial version.
20 */
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/device.h>
25#include <linux/delay.h>
26#include <linux/clk.h>
27#include <sound/driver.h>
28#include <sound/core.h>
29#include <sound/pcm.h>
30#include <sound/pcm_params.h>
31#include <sound/initval.h>
32#include <sound/soc.h>
33
34#include <asm/hardware.h>
35#include <asm/io.h>
36#include <asm/arch/regs-iis.h>
37#include <asm/arch/regs-gpio.h>
38#include <asm/arch/regs-clock.h>
39#include <asm/arch/audio.h>
40#include <asm/dma.h>
41#include <asm/arch/dma.h>
42
43#include "s3c24xx-pcm.h"
44#include "s3c24xx-i2s.h"
45
46#define S3C24XX_I2S_DEBUG 0
47#if S3C24XX_I2S_DEBUG
48#define DBG(x...) printk(KERN_DEBUG x)
49#else
50#define DBG(x...)
51#endif
52
53static struct s3c2410_dma_client s3c24xx_dma_client_out = {
54 .name = "I2S PCM Stereo out"
55};
56
57static struct s3c2410_dma_client s3c24xx_dma_client_in = {
58 .name = "I2S PCM Stereo in"
59};
60
61static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_out = {
62 .client = &s3c24xx_dma_client_out,
63 .channel = DMACH_I2S_OUT,
64 .dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO
65};
66
67static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_in = {
68 .client = &s3c24xx_dma_client_in,
69 .channel = DMACH_I2S_IN,
70 .dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO
71};
72
73struct s3c24xx_i2s_info {
74 void __iomem *regs;
75 struct clk *iis_clk;
76};
77static struct s3c24xx_i2s_info s3c24xx_i2s;
78
79static void s3c24xx_snd_txctrl(int on)
80{
81 u32 iisfcon;
82 u32 iiscon;
83 u32 iismod;
84
85 DBG("Entered %s\n", __FUNCTION__);
86
87 iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
88 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
89 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
90
91 DBG("r: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
92
93 if (on) {
94 iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
95 iiscon |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
96 iiscon &= ~S3C2410_IISCON_TXIDLE;
97 iismod |= S3C2410_IISMOD_TXMODE;
98
99 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
100 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
101 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
102 } else {
103 /* note, we have to disable the FIFOs otherwise bad things
104 * seem to happen when the DMA stops. According to the
105 * Samsung supplied kernel, this should allow the DMA
106 * engine and FIFOs to reset. If this isn't allowed, the
107 * DMA engine will simply freeze randomly.
108 */
109
110 iisfcon &= ~S3C2410_IISFCON_TXENABLE;
111 iisfcon &= ~S3C2410_IISFCON_TXDMA;
112 iiscon |= S3C2410_IISCON_TXIDLE;
113 iiscon &= ~S3C2410_IISCON_TXDMAEN;
114 iismod &= ~S3C2410_IISMOD_TXMODE;
115
116 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
117 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
118 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
119 }
120
121 DBG("w: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
122}
123
124static void s3c24xx_snd_rxctrl(int on)
125{
126 u32 iisfcon;
127 u32 iiscon;
128 u32 iismod;
129
130 DBG("Entered %s\n", __FUNCTION__);
131
132 iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
133 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
134 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
135
136 DBG("r: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
137
138 if (on) {
139 iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
140 iiscon |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
141 iiscon &= ~S3C2410_IISCON_RXIDLE;
142 iismod |= S3C2410_IISMOD_RXMODE;
143
144 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
145 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
146 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
147 } else {
148 /* note, we have to disable the FIFOs otherwise bad things
149 * seem to happen when the DMA stops. According to the
150 * Samsung supplied kernel, this should allow the DMA
151 * engine and FIFOs to reset. If this isn't allowed, the
152 * DMA engine will simply freeze randomly.
153 */
154
155 iisfcon &= ~S3C2410_IISFCON_RXENABLE;
156 iisfcon &= ~S3C2410_IISFCON_RXDMA;
157 iiscon |= S3C2410_IISCON_RXIDLE;
158 iiscon &= ~S3C2410_IISCON_RXDMAEN;
159 iismod &= ~S3C2410_IISMOD_RXMODE;
160
161 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
162 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
163 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
164 }
165
166 DBG("w: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
167}
168
169/*
170 * Wait for the LR signal to allow synchronisation to the L/R clock
171 * from the codec. May only be needed for slave mode.
172 */
173static int s3c24xx_snd_lrsync(void)
174{
175 u32 iiscon;
176 unsigned long timeout = jiffies + msecs_to_jiffies(5);
177
178 DBG("Entered %s\n", __FUNCTION__);
179
180 while (1) {
181 iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
182 if (iiscon & S3C2410_IISCON_LRINDEX)
183 break;
184
185 if (timeout < jiffies)
186 return -ETIMEDOUT;
187 }
188
189 return 0;
190}
191
192/*
193 * Check whether CPU is the master or slave
194 */
195static inline int s3c24xx_snd_is_clkmaster(void)
196{
197 DBG("Entered %s\n", __FUNCTION__);
198
199 return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
200}
201
202/*
203 * Set S3C24xx I2S DAI format
204 */
205static int s3c24xx_i2s_set_fmt(struct snd_soc_cpu_dai *cpu_dai,
206 unsigned int fmt)
207{
208 u32 iismod;
209
210 DBG("Entered %s\n", __FUNCTION__);
211
212 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
213 DBG("hw_params r: IISMOD: %lx \n", iismod);
214
215 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
216 case SND_SOC_DAIFMT_CBM_CFM:
217 iismod |= S3C2410_IISMOD_SLAVE;
218 break;
219 case SND_SOC_DAIFMT_CBS_CFS:
220 break;
221 default:
222 return -EINVAL;
223 }
224
225 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
226 case SND_SOC_DAIFMT_LEFT_J:
227 iismod |= S3C2410_IISMOD_MSB;
228 break;
229 case SND_SOC_DAIFMT_I2S:
230 break;
231 default:
232 return -EINVAL;
233 }
234
235 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
236 DBG("hw_params w: IISMOD: %lx \n", iismod);
237 return 0;
238}
239
240static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
241 struct snd_pcm_hw_params *params)
242{
243 struct snd_soc_pcm_runtime *rtd = substream->private_data;
244 u32 iismod;
245
246 DBG("Entered %s\n", __FUNCTION__);
247
248 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
249 rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out;
250 else
251 rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in;
252
253 /* Working copies of register */
254 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
255 DBG("hw_params r: IISMOD: %lx\n", iismod);
256
257 switch (params_format(params)) {
258 case SNDRV_PCM_FORMAT_S8:
259 break;
260 case SNDRV_PCM_FORMAT_S16_LE:
261 iismod |= S3C2410_IISMOD_16BIT;
262 break;
263 }
264
265 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
266 DBG("hw_params w: IISMOD: %lx\n", iismod);
267 return 0;
268}
269
270static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
271{
272 int ret = 0;
273
274 DBG("Entered %s\n", __FUNCTION__);
275
276 switch (cmd) {
277 case SNDRV_PCM_TRIGGER_START:
278 case SNDRV_PCM_TRIGGER_RESUME:
279 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
280 if (!s3c24xx_snd_is_clkmaster()) {
281 ret = s3c24xx_snd_lrsync();
282 if (ret)
283 goto exit_err;
284 }
285
286 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
287 s3c24xx_snd_rxctrl(1);
288 else
289 s3c24xx_snd_txctrl(1);
290 break;
291 case SNDRV_PCM_TRIGGER_STOP:
292 case SNDRV_PCM_TRIGGER_SUSPEND:
293 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
294 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
295 s3c24xx_snd_rxctrl(0);
296 else
297 s3c24xx_snd_txctrl(0);
298 break;
299 default:
300 ret = -EINVAL;
301 break;
302 }
303
304exit_err:
305 return ret;
306}
307
308/*
309 * Set S3C24xx Clock source
310 */
311static int s3c24xx_i2s_set_sysclk(struct snd_soc_cpu_dai *cpu_dai,
312 int clk_id, unsigned int freq, int dir)
313{
314 u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
315
316 DBG("Entered %s\n", __FUNCTION__);
317
318 iismod &= ~S3C2440_IISMOD_MPLL;
319
320 switch (clk_id) {
321 case S3C24XX_CLKSRC_PCLK:
322 break;
323 case S3C24XX_CLKSRC_MPLL:
324 iismod |= S3C2440_IISMOD_MPLL;
325 break;
326 default:
327 return -EINVAL;
328 }
329
330 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
331 return 0;
332}
333
334/*
335 * Set S3C24xx Clock dividers
336 */
337static int s3c24xx_i2s_set_clkdiv(struct snd_soc_cpu_dai *cpu_dai,
338 int div_id, int div)
339{
340 u32 reg;
341
342 DBG("Entered %s\n", __FUNCTION__);
343
344 switch (div_id) {
345 case S3C24XX_DIV_MCLK:
346 reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
347 writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
348 break;
349 case S3C24XX_DIV_BCLK:
350 reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
351 writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
352 break;
353 case S3C24XX_DIV_PRESCALER:
354 writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
355 reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
356 writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
357 break;
358 default:
359 return -EINVAL;
360 }
361
362 return 0;
363}
364
365/*
366 * To avoid duplicating clock code, allow machine driver to
367 * get the clockrate from here.
368 */
369u32 s3c24xx_i2s_get_clockrate(void)
370{
371 return clk_get_rate(s3c24xx_i2s.iis_clk);
372}
373EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
374
375static int s3c24xx_i2s_probe(struct platform_device *pdev)
376{
377 DBG("Entered %s\n", __FUNCTION__);
378
379 s3c24xx_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
380 if (s3c24xx_i2s.regs == NULL)
381 return -ENXIO;
382
383 s3c24xx_i2s.iis_clk=clk_get(&pdev->dev, "iis");
384 if (s3c24xx_i2s.iis_clk == NULL) {
385 DBG("failed to get iis_clock\n");
386 return -ENODEV;
387 }
388 clk_enable(s3c24xx_i2s.iis_clk);
389
390 /* Configure the I2S pins in correct mode */
391 s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
392 s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
393 s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
394 s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
395 s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
396
397 writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
398
399 s3c24xx_snd_txctrl(0);
400 s3c24xx_snd_rxctrl(0);
401
402 return 0;
403}
404
405#define S3C24XX_I2S_RATES \
406 (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
407 SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
408 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
409
410struct snd_soc_cpu_dai s3c24xx_i2s_dai = {
411 .name = "s3c24xx-i2s",
412 .id = 0,
413 .type = SND_SOC_DAI_I2S,
414 .probe = s3c24xx_i2s_probe,
415 .playback = {
416 .channels_min = 2,
417 .channels_max = 2,
418 .rates = S3C24XX_I2S_RATES,
419 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
420 .capture = {
421 .channels_min = 2,
422 .channels_max = 2,
423 .rates = S3C24XX_I2S_RATES,
424 .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
425 .ops = {
426 .trigger = s3c24xx_i2s_trigger,
427 .hw_params = s3c24xx_i2s_hw_params,},
428 .dai_ops = {
429 .set_fmt = s3c24xx_i2s_set_fmt,
430 .set_clkdiv = s3c24xx_i2s_set_clkdiv,
431 .set_sysclk = s3c24xx_i2s_set_sysclk,
432 },
433};
434EXPORT_SYMBOL_GPL(s3c24xx_i2s_dai);
435
436/* Module information */
437MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
438MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
439MODULE_LICENSE("GPL");
diff --git a/sound/soc/s3c24xx/s3c24xx-i2s.h b/sound/soc/s3c24xx/s3c24xx-i2s.h
new file mode 100644
index 000000000000..f9ca04edacb7
--- /dev/null
+++ b/sound/soc/s3c24xx/s3c24xx-i2s.h
@@ -0,0 +1,35 @@
1/*
2 * s3c24xx-i2s.c -- ALSA Soc Audio Layer
3 *
4 * Copyright 2005 Wolfson Microelectronics PLC.
5 * Author: Graeme Gregory
6 * graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * Revision history
14 * 10th Nov 2006 Initial version.
15 */
16
17#ifndef S3C24XXI2S_H_
18#define S3C24XXI2S_H_
19
20/* clock sources */
21#define S3C24XX_CLKSRC_PCLK 0
22#define S3C24XX_CLKSRC_MPLL 1
23
24/* Clock dividers */
25#define S3C24XX_DIV_MCLK 0
26#define S3C24XX_DIV_BCLK 1
27#define S3C24XX_DIV_PRESCALER 2
28
29/* prescaler */
30#define S3C24XX_PRESCALE(a,b) \
31 (((a - 1) << S3C2410_IISPSR_INTSHIFT) | ((b - 1) << S3C2410_IISPSR_EXTSHFIT))
32
33u32 s3c24xx_i2s_get_clockrate(void);
34
35#endif /*S3C24XXI2S_H_*/
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-02 14:11:09 -0500