4 files changed, 11 insertions, 2 deletions

diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index 0ec134034899..148a3547c9aa 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -408,6 +408,12 @@ END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
         std     r7,SLBSHADOW_STACKVSID(r9)  /* Save VSID */
         std     r0,SLBSHADOW_STACKESID(r9)  /* Save ESID */
 
+        /* No need to check for CPU_FTR_NO_SLBIE_B here, since when
+         * we have 1TB segments, the only CPUs known to have the errata
+         * only support less than 1TB of system memory and we'll never
+         * actually hit this code path.
+         */
+
         slbie   r6
         slbie   r6              /* Workaround POWER5 < DD2.1 issue */
         slbmte  r7,r0
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 09da90b53850..c78dc912411f 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -212,6 +212,7 @@ static int __init htab_dt_scan_seg_sizes(unsigned long node,
                         return 1;
                 }
         }
+        cur_cpu_spec->cpu_features &= ~CPU_FTR_NO_SLBIE_B;
         return 0;
 }
 
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index 6c164cec9d2c..bbd2c512ee05 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -157,7 +157,8 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
         unsigned long stack = KSTK_ESP(tsk);
         unsigned long unmapped_base;
 
-        if (offset <= SLB_CACHE_ENTRIES) {
+        if (!cpu_has_feature(CPU_FTR_NO_SLBIE_B) &&
+            offset <= SLB_CACHE_ENTRIES) {
                 int i;
                 asm volatile("isync" : : : "memory");
                 for (i = 0; i < offset; i++) {
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index ae093ef68363..9d74338e3dec 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -165,6 +165,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0001000000000000)
 #define CPU_FTR_DSCR                    LONG_ASM_CONST(0x0002000000000000)
 #define CPU_FTR_1T_SEGMENT              LONG_ASM_CONST(0x0004000000000000)
+#define CPU_FTR_NO_SLBIE_B              LONG_ASM_CONST(0x0008000000000000)
 
 #ifndef __ASSEMBLY__
 
@@ -367,7 +368,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
-            CPU_FTR_PURR | CPU_FTR_REAL_LE)
+            CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
 #define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)