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-rw-r--r--drivers/infiniband/hw/mlx4/cq.c16
-rw-r--r--drivers/infiniband/hw/mlx4/main.c2
-rw-r--r--drivers/infiniband/hw/mlx4/qp.c3
-rw-r--r--drivers/net/mlx4/fw.c4
-rw-r--r--include/linux/mlx4/cq.h14
-rw-r--r--include/linux/mlx4/qp.h10
6 files changed, 43 insertions, 6 deletions
diff --git a/drivers/infiniband/hw/mlx4/cq.c b/drivers/infiniband/hw/mlx4/cq.c
index 7360bbafbe84..d2e32b03e2f7 100644
--- a/drivers/infiniband/hw/mlx4/cq.c
+++ b/drivers/infiniband/hw/mlx4/cq.c
@@ -297,6 +297,20 @@ static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
297 wc->vendor_err = cqe->vendor_err_syndrome; 297 wc->vendor_err = cqe->vendor_err_syndrome;
298} 298}
299 299
300static int mlx4_ib_ipoib_csum_ok(__be32 status, __be16 checksum)
301{
302 return ((status & cpu_to_be32(MLX4_CQE_IPOIB_STATUS_IPV4 |
303 MLX4_CQE_IPOIB_STATUS_IPV4F |
304 MLX4_CQE_IPOIB_STATUS_IPV4OPT |
305 MLX4_CQE_IPOIB_STATUS_IPV6 |
306 MLX4_CQE_IPOIB_STATUS_IPOK)) ==
307 cpu_to_be32(MLX4_CQE_IPOIB_STATUS_IPV4 |
308 MLX4_CQE_IPOIB_STATUS_IPOK)) &&
309 (status & cpu_to_be32(MLX4_CQE_IPOIB_STATUS_UDP |
310 MLX4_CQE_IPOIB_STATUS_TCP)) &&
311 checksum == cpu_to_be16(0xffff);
312}
313
300static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq, 314static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
301 struct mlx4_ib_qp **cur_qp, 315 struct mlx4_ib_qp **cur_qp,
302 struct ib_wc *wc) 316 struct ib_wc *wc)
@@ -434,6 +448,8 @@ static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
434 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f; 448 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
435 wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0; 449 wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
436 wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f; 450 wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
451 wc->csum_ok = mlx4_ib_ipoib_csum_ok(cqe->ipoib_status,
452 cqe->checksum);
437 } 453 }
438 454
439 return 0; 455 return 0;
diff --git a/drivers/infiniband/hw/mlx4/main.c b/drivers/infiniband/hw/mlx4/main.c
index d5512011999c..6ea4746c2e9b 100644
--- a/drivers/infiniband/hw/mlx4/main.c
+++ b/drivers/infiniband/hw/mlx4/main.c
@@ -99,6 +99,8 @@ static int mlx4_ib_query_device(struct ib_device *ibdev,
99 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 99 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
100 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT) 100 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
101 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE; 101 props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
102 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
103 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
102 104
103 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) & 105 props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
104 0xffffff; 106 0xffffff;
diff --git a/drivers/infiniband/hw/mlx4/qp.c b/drivers/infiniband/hw/mlx4/qp.c
index ac965ab28845..31b2b5b230bd 100644
--- a/drivers/infiniband/hw/mlx4/qp.c
+++ b/drivers/infiniband/hw/mlx4/qp.c
@@ -1436,6 +1436,9 @@ int mlx4_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1436 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) | 1436 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
1437 (wr->send_flags & IB_SEND_SOLICITED ? 1437 (wr->send_flags & IB_SEND_SOLICITED ?
1438 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) | 1438 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
1439 ((wr->send_flags & IB_SEND_IP_CSUM) ?
1440 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
1441 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
1439 qp->sq_signal_bits; 1442 qp->sq_signal_bits;
1440 1443
1441 if (wr->opcode == IB_WR_SEND_WITH_IMM || 1444 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
diff --git a/drivers/net/mlx4/fw.c b/drivers/net/mlx4/fw.c
index 61dc4951d6b0..f494c3e8bce3 100644
--- a/drivers/net/mlx4/fw.c
+++ b/drivers/net/mlx4/fw.c
@@ -696,6 +696,10 @@ int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
696 /* Check port for UD address vector: */ 696 /* Check port for UD address vector: */
697 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); 697 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
698 698
699 /* Enable IPoIB checksumming if we can: */
700 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
701 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
702
699 /* QPC/EEC/CQC/EQC/RDMARC attributes */ 703 /* QPC/EEC/CQC/EQC/RDMARC attributes */
700 704
701 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); 705 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
diff --git a/include/linux/mlx4/cq.h b/include/linux/mlx4/cq.h
index 0181e0a57cbf..1243ebace561 100644
--- a/include/linux/mlx4/cq.h
+++ b/include/linux/mlx4/cq.h
@@ -45,11 +45,11 @@ struct mlx4_cqe {
45 u8 sl; 45 u8 sl;
46 u8 reserved1; 46 u8 reserved1;
47 __be16 rlid; 47 __be16 rlid;
48 u32 reserved2; 48 __be32 ipoib_status;
49 __be32 byte_cnt; 49 __be32 byte_cnt;
50 __be16 wqe_index; 50 __be16 wqe_index;
51 __be16 checksum; 51 __be16 checksum;
52 u8 reserved3[3]; 52 u8 reserved2[3];
53 u8 owner_sr_opcode; 53 u8 owner_sr_opcode;
54}; 54};
55 55
@@ -85,6 +85,16 @@ enum {
85 MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22, 85 MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22,
86}; 86};
87 87
88enum {
89 MLX4_CQE_IPOIB_STATUS_IPV4 = 1 << 22,
90 MLX4_CQE_IPOIB_STATUS_IPV4F = 1 << 23,
91 MLX4_CQE_IPOIB_STATUS_IPV6 = 1 << 24,
92 MLX4_CQE_IPOIB_STATUS_IPV4OPT = 1 << 25,
93 MLX4_CQE_IPOIB_STATUS_TCP = 1 << 26,
94 MLX4_CQE_IPOIB_STATUS_UDP = 1 << 27,
95 MLX4_CQE_IPOIB_STATUS_IPOK = 1 << 28,
96};
97
88static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd, 98static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,
89 void __iomem *uar_page, 99 void __iomem *uar_page,
90 spinlock_t *doorbell_lock) 100 spinlock_t *doorbell_lock)
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h
index 09a2230923f2..31f9eb3ccbb3 100644
--- a/include/linux/mlx4/qp.h
+++ b/include/linux/mlx4/qp.h
@@ -158,10 +158,12 @@ struct mlx4_qp_context {
158#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232) 158#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
159 159
160enum { 160enum {
161 MLX4_WQE_CTRL_NEC = 1 << 29, 161 MLX4_WQE_CTRL_NEC = 1 << 29,
162 MLX4_WQE_CTRL_FENCE = 1 << 6, 162 MLX4_WQE_CTRL_FENCE = 1 << 6,
163 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2, 163 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
164 MLX4_WQE_CTRL_SOLICITED = 1 << 1, 164 MLX4_WQE_CTRL_SOLICITED = 1 << 1,
165 MLX4_WQE_CTRL_IP_CSUM = 1 << 4,
166 MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5,
165}; 167};
166 168
167struct mlx4_wqe_ctrl_seg { 169struct mlx4_wqe_ctrl_seg {