diff options
-rw-r--r-- | include/asm-ppc/pgtable.h | 52 |
1 files changed, 49 insertions, 3 deletions
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index 4d4b20c9de78..c41c7958ea1f 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h | |||
@@ -202,18 +202,64 @@ extern unsigned long ioremap_bot, ioremap_base; | |||
202 | * | 202 | * |
203 | * Note that these bits preclude future use of a page size | 203 | * Note that these bits preclude future use of a page size |
204 | * less than 4KB. | 204 | * less than 4KB. |
205 | * | ||
206 | * | ||
207 | * PPC 440 core has following TLB attribute fields; | ||
208 | * | ||
209 | * TLB1: | ||
210 | * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 | ||
211 | * RPN................................. - - - - - - ERPN....... | ||
212 | * | ||
213 | * TLB2: | ||
214 | * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 | ||
215 | * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR | ||
216 | * | ||
217 | * There are some constrains and options, to decide mapping software bits | ||
218 | * into TLB entry. | ||
219 | * | ||
220 | * - PRESENT *must* be in the bottom three bits because swap cache | ||
221 | * entries use the top 29 bits for TLB2. | ||
222 | * | ||
223 | * - FILE *must* be in the bottom three bits because swap cache | ||
224 | * entries use the top 29 bits for TLB2. | ||
225 | * | ||
226 | * - CACHE COHERENT bit (M) has no effect on PPC440 core, because it | ||
227 | * doesn't support SMP. So we can use this as software bit, like | ||
228 | * DIRTY. | ||
229 | * | ||
230 | * PPC Book-E Linux implementation uses PPC HW PTE bit field definition, | ||
231 | * even it doesn't have HW PTE. 0-11th LSB of PTE stand for memory | ||
232 | * protection-related function. (See PTE structure in include/asm-ppc/mmu.h) | ||
233 | * Definition of _PAGE_XXX in "include/asm-ppc/pagetable.h" stands for | ||
234 | * above bits. Note that those bits values are CPU dependent, not | ||
235 | * architecture. | ||
236 | * | ||
237 | * Kernel PTE entry holds arch-dependent swp_entry structure under certain | ||
238 | * situation. In other words, in such situation, some portion of PTE bits | ||
239 | * are used as swp_entry. In PPC implementation, 3-24th LSB are shared with | ||
240 | * swp_entry, however 0-2nd three LSB still hold protection values. | ||
241 | * That means three protection bits are reserved for both PTE and SWAP | ||
242 | * entry at the most three LSBs. | ||
243 | * | ||
244 | * There are three protection bits available for SWAP entry; | ||
245 | * _PAGE_PRESENT | ||
246 | * _PAGE_FILE | ||
247 | * _PAGE_HASHPTE (if HW has) | ||
248 | * | ||
249 | * So those three bits have to be inside of 0-2nd LSB of PTE. | ||
250 | * | ||
205 | */ | 251 | */ |
252 | |||
206 | #define _PAGE_PRESENT 0x00000001 /* S: PTE valid */ | 253 | #define _PAGE_PRESENT 0x00000001 /* S: PTE valid */ |
207 | #define _PAGE_RW 0x00000002 /* S: Write permission */ | 254 | #define _PAGE_RW 0x00000002 /* S: Write permission */ |
208 | #define _PAGE_DIRTY 0x00000004 /* S: Page dirty */ | 255 | #define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */ |
209 | #define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */ | 256 | #define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */ |
210 | #define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */ | 257 | #define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */ |
211 | #define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */ | 258 | #define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */ |
212 | #define _PAGE_USER 0x00000040 /* S: User page */ | 259 | #define _PAGE_USER 0x00000040 /* S: User page */ |
213 | #define _PAGE_ENDIAN 0x00000080 /* H: E bit */ | 260 | #define _PAGE_ENDIAN 0x00000080 /* H: E bit */ |
214 | #define _PAGE_GUARDED 0x00000100 /* H: G bit */ | 261 | #define _PAGE_GUARDED 0x00000100 /* H: G bit */ |
215 | #define _PAGE_COHERENT 0x00000200 /* H: M bit */ | 262 | #define _PAGE_DIRTY 0x00000200 /* S: Page dirty */ |
216 | #define _PAGE_FILE 0x00000400 /* S: nonlinear file mapping */ | ||
217 | #define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ | 263 | #define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ |
218 | #define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ | 264 | #define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ |
219 | 265 | ||