6 files changed, 19 insertions, 1 deletions

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 17184921b71d..bef3e2dc7c52 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -433,6 +433,15 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                              MIPS_CPU_LLSC;
                 c->tlbsize = 64;
                 break;
+        case PRID_IMP_R14000:
+                c->cputype = CPU_R14000;
+                c->isa_level = MIPS_CPU_ISA_IV;
+                c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
+                             MIPS_CPU_FPU | MIPS_CPU_32FPR |
+                             MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
+                             MIPS_CPU_LLSC;
+                c->tlbsize = 64;
+                break;
         }
 }
 
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 197952c44467..9def554f335b 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -42,6 +42,7 @@ static const char *cpu_name[] = {
         [CPU_R8000]     = "R8000",
         [CPU_R10000]    = "R10000",
         [CPU_R12000]    = "R12000",
+        [CPU_R14000]    = "R14000",
         [CPU_R4300]     = "R4300",
         [CPU_R4650]     = "R4650",
         [CPU_R4700]     = "R4700",
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 570bc4e30fd5..6b3541769602 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -335,6 +335,7 @@ static inline void local_r4k___flush_cache_all(void * args)
         case CPU_R4400MC:
         case CPU_R10000:
         case CPU_R12000:
+        case CPU_R14000:
                 r4k_blast_scache();
         }
 }
@@ -833,6 +834,7 @@ static void __init probe_pcache(void)
 
         case CPU_R10000:
         case CPU_R12000:
+        case CPU_R14000:
                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
                 c->icache.linesz = 64;
                 c->icache.ways = 2;
@@ -986,6 +988,7 @@ static void __init probe_pcache(void)
                 c->dcache.flags |= MIPS_CACHE_PINDEX;
         case CPU_R10000:
         case CPU_R12000:
+        case CPU_R14000:
         case CPU_SB1:
                 break;
         case CPU_24K:
@@ -1113,6 +1116,7 @@ static void __init setup_scache(void)
 
         case CPU_R10000:
         case CPU_R12000:
+        case CPU_R14000:
                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
                 c->scache.linesz = 64 << ((config >> 13) & 1);
                 c->scache.ways = 2;
diff --git a/arch/mips/mm/pg-r4k.c b/arch/mips/mm/pg-r4k.c
index e4390dc3eb48..b7c749232ffe 100644
--- a/arch/mips/mm/pg-r4k.c
+++ b/arch/mips/mm/pg-r4k.c
@@ -357,6 +357,7 @@ void __init build_clear_page(void)
 
                 case CPU_R10000:
                 case CPU_R12000:
+                case CPU_R14000:
                         pref_src_mode = Pref_LoadStreamed;
                         pref_dst_mode = Pref_StoreStreamed;
                         break;
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 4ff07e2efcb3..54507be2ab5b 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -875,6 +875,7 @@ static __init void build_tlb_write_entry(u32 **p, struct label **l,
 
         case CPU_R10000:
         case CPU_R12000:
+        case CPU_R14000:
         case CPU_4KC:
         case CPU_SB1:
         case CPU_SB1A:
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index 0117138149bc..dff2a0a52f8f 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -51,6 +51,7 @@
 #define PRID_IMP_R4300          0x0b00
 #define PRID_IMP_VR41XX         0x0c00
 #define PRID_IMP_R12000         0x0e00
+#define PRID_IMP_R14000         0x0f00
 #define PRID_IMP_R8000          0x1000
 #define PRID_IMP_PR4450         0x1200
 #define PRID_IMP_R4600          0x2000
@@ -198,7 +199,8 @@
 #define CPU_PR4450              61
 #define CPU_SB1A                62
 #define CPU_74K                 63
-#define CPU_LAST                63
+#define CPU_R14000              64
+#define CPU_LAST                64
 
 /*
  * ISA Level encodings