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-rw-r--r--drivers/net/ixgbe/ixgbe.h5
-rw-r--r--drivers/net/ixgbe/ixgbe_82598.c160
-rw-r--r--drivers/net/ixgbe/ixgbe_main.c94
-rw-r--r--drivers/net/ixgbe/ixgbe_phy.c258
-rw-r--r--drivers/net/ixgbe/ixgbe_phy.h18
-rw-r--r--drivers/net/ixgbe/ixgbe_type.h22
6 files changed, 550 insertions, 7 deletions
diff --git a/drivers/net/ixgbe/ixgbe.h b/drivers/net/ixgbe/ixgbe.h
index 796f189f3879..9509aee2d361 100644
--- a/drivers/net/ixgbe/ixgbe.h
+++ b/drivers/net/ixgbe/ixgbe.h
@@ -311,12 +311,15 @@ struct ixgbe_adapter {
311 unsigned long link_check_timeout; 311 unsigned long link_check_timeout;
312 312
313 struct work_struct watchdog_task; 313 struct work_struct watchdog_task;
314 struct work_struct sfp_task;
315 struct timer_list sfp_timer;
314}; 316};
315 317
316enum ixbge_state_t { 318enum ixbge_state_t {
317 __IXGBE_TESTING, 319 __IXGBE_TESTING,
318 __IXGBE_RESETTING, 320 __IXGBE_RESETTING,
319 __IXGBE_DOWN 321 __IXGBE_DOWN,
322 __IXGBE_SFP_MODULE_NOT_FOUND
320}; 323};
321 324
322enum ixgbe_boards { 325enum ixgbe_boards {
diff --git a/drivers/net/ixgbe/ixgbe_82598.c b/drivers/net/ixgbe/ixgbe_82598.c
index c2cdb042c481..7e09dab0c29f 100644
--- a/drivers/net/ixgbe/ixgbe_82598.c
+++ b/drivers/net/ixgbe/ixgbe_82598.c
@@ -46,6 +46,8 @@ static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed, 46 ixgbe_link_speed speed,
47 bool autoneg, 47 bool autoneg,
48 bool autoneg_wait_to_complete); 48 bool autoneg_wait_to_complete);
49static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
50 u8 *eeprom_data);
49 51
50/** 52/**
51 */ 53 */
@@ -53,6 +55,8 @@ static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
53{ 55{
54 struct ixgbe_mac_info *mac = &hw->mac; 56 struct ixgbe_mac_info *mac = &hw->mac;
55 struct ixgbe_phy_info *phy = &hw->phy; 57 struct ixgbe_phy_info *phy = &hw->phy;
58 s32 ret_val = 0;
59 u16 list_offset, data_offset;
56 60
57 /* Call PHY identify routine to get the phy type */ 61 /* Call PHY identify routine to get the phy type */
58 ixgbe_identify_phy_generic(hw); 62 ixgbe_identify_phy_generic(hw);
@@ -64,6 +68,27 @@ static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
64 phy->ops.get_firmware_version = 68 phy->ops.get_firmware_version =
65 &ixgbe_get_phy_firmware_version_tnx; 69 &ixgbe_get_phy_firmware_version_tnx;
66 break; 70 break;
71 case ixgbe_phy_nl:
72 phy->ops.reset = &ixgbe_reset_phy_nl;
73
74 /* Call SFP+ identify routine to get the SFP+ module type */
75 ret_val = phy->ops.identify_sfp(hw);
76 if (ret_val != 0)
77 goto out;
78 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
79 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
80 goto out;
81 }
82
83 /* Check to see if SFP+ module is supported */
84 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
85 &list_offset,
86 &data_offset);
87 if (ret_val != 0) {
88 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
89 goto out;
90 }
91 break;
67 default: 92 default:
68 break; 93 break;
69 } 94 }
@@ -82,7 +107,8 @@ static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
82 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES; 107 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
83 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES; 108 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
84 109
85 return 0; 110out:
111 return ret_val;
86} 112}
87 113
88/** 114/**
@@ -191,7 +217,10 @@ static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
191 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 217 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
192 case IXGBE_DEV_ID_82598EB_CX4: 218 case IXGBE_DEV_ID_82598EB_CX4:
193 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 219 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
220 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
221 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
194 case IXGBE_DEV_ID_82598EB_XF_LR: 222 case IXGBE_DEV_ID_82598EB_XF_LR:
223 case IXGBE_DEV_ID_82598EB_SFP_LOM:
195 media_type = ixgbe_media_type_fiber; 224 media_type = ixgbe_media_type_fiber;
196 break; 225 break;
197 case IXGBE_DEV_ID_82598AT: 226 case IXGBE_DEV_ID_82598AT:
@@ -399,6 +428,46 @@ static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
399{ 428{
400 u32 links_reg; 429 u32 links_reg;
401 u32 i; 430 u32 i;
431 u16 link_reg, adapt_comp_reg;
432
433 /*
434 * SERDES PHY requires us to read link status from register 0xC79F.
435 * Bit 0 set indicates link is up/ready; clear indicates link down.
436 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
437 * clear indicates active; set indicates inactive.
438 */
439 if (hw->phy.type == ixgbe_phy_nl) {
440 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
441 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
442 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
443 &adapt_comp_reg);
444 if (link_up_wait_to_complete) {
445 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
446 if ((link_reg & 1) &&
447 ((adapt_comp_reg & 1) == 0)) {
448 *link_up = true;
449 break;
450 } else {
451 *link_up = false;
452 }
453 msleep(100);
454 hw->phy.ops.read_reg(hw, 0xC79F,
455 IXGBE_TWINAX_DEV,
456 &link_reg);
457 hw->phy.ops.read_reg(hw, 0xC00C,
458 IXGBE_TWINAX_DEV,
459 &adapt_comp_reg);
460 }
461 } else {
462 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
463 *link_up = true;
464 else
465 *link_up = false;
466 }
467
468 if (*link_up == false)
469 goto out;
470 }
402 471
403 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 472 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
404 if (link_up_wait_to_complete) { 473 if (link_up_wait_to_complete) {
@@ -424,6 +493,7 @@ static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
424 else 493 else
425 *speed = IXGBE_LINK_SPEED_1GB_FULL; 494 *speed = IXGBE_LINK_SPEED_1GB_FULL;
426 495
496out:
427 return 0; 497 return 0;
428} 498}
429 499
@@ -859,6 +929,69 @@ s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
859} 929}
860 930
861/** 931/**
932 * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
933 * over I2C interface through an intermediate phy.
934 * @hw: pointer to hardware structure
935 * @byte_offset: EEPROM byte offset to read
936 * @eeprom_data: value read
937 *
938 * Performs byte read operation to SFP module's EEPROM over I2C interface.
939 **/
940s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
941 u8 *eeprom_data)
942{
943 s32 status = 0;
944 u16 sfp_addr = 0;
945 u16 sfp_data = 0;
946 u16 sfp_stat = 0;
947 u32 i;
948
949 if (hw->phy.type == ixgbe_phy_nl) {
950 /*
951 * phy SDA/SCL registers are at addresses 0xC30A to
952 * 0xC30D. These registers are used to talk to the SFP+
953 * module's EEPROM through the SDA/SCL (I2C) interface.
954 */
955 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
956 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
957 hw->phy.ops.write_reg(hw,
958 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
959 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
960 sfp_addr);
961
962 /* Poll status */
963 for (i = 0; i < 100; i++) {
964 hw->phy.ops.read_reg(hw,
965 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
966 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
967 &sfp_stat);
968 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
969 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
970 break;
971 msleep(10);
972 }
973
974 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
975 hw_dbg(hw, "EEPROM read did not pass.\n");
976 status = IXGBE_ERR_SFP_NOT_PRESENT;
977 goto out;
978 }
979
980 /* Read data */
981 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
982 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
983
984 *eeprom_data = (u8)(sfp_data >> 8);
985 } else {
986 status = IXGBE_ERR_PHY;
987 goto out;
988 }
989
990out:
991 return status;
992}
993
994/**
862 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type 995 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
863 * @hw: pointer to hardware structure 996 * @hw: pointer to hardware structure
864 * 997 *
@@ -873,8 +1006,12 @@ s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
873 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 1006 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
874 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1007 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
875 break; 1008 break;
1009 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1010 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1011 break;
876 case IXGBE_DEV_ID_82598AF_DUAL_PORT: 1012 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
877 case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 1013 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1014 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
878 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1015 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
879 break; 1016 break;
880 case IXGBE_DEV_ID_82598EB_XF_LR: 1017 case IXGBE_DEV_ID_82598EB_XF_LR:
@@ -884,6 +1021,24 @@ s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
884 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T | 1021 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
885 IXGBE_PHYSICAL_LAYER_1000BASE_T); 1022 IXGBE_PHYSICAL_LAYER_1000BASE_T);
886 break; 1023 break;
1024 case IXGBE_DEV_ID_82598EB_SFP_LOM:
1025 hw->phy.ops.identify_sfp(hw);
1026
1027 switch (hw->phy.sfp_type) {
1028 case ixgbe_sfp_type_da_cu:
1029 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1030 break;
1031 case ixgbe_sfp_type_sr:
1032 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1033 break;
1034 case ixgbe_sfp_type_lr:
1035 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1036 break;
1037 default:
1038 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1039 break;
1040 }
1041 break;
887 1042
888 default: 1043 default:
889 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1044 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
@@ -935,12 +1090,13 @@ static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
935 1090
936static struct ixgbe_phy_operations phy_ops_82598 = { 1091static struct ixgbe_phy_operations phy_ops_82598 = {
937 .identify = &ixgbe_identify_phy_generic, 1092 .identify = &ixgbe_identify_phy_generic,
938 /* .identify_sfp = &ixgbe_identify_sfp_module_generic, */ 1093 .identify_sfp = &ixgbe_identify_sfp_module_generic,
939 .reset = &ixgbe_reset_phy_generic, 1094 .reset = &ixgbe_reset_phy_generic,
940 .read_reg = &ixgbe_read_phy_reg_generic, 1095 .read_reg = &ixgbe_read_phy_reg_generic,
941 .write_reg = &ixgbe_write_phy_reg_generic, 1096 .write_reg = &ixgbe_write_phy_reg_generic,
942 .setup_link = &ixgbe_setup_phy_link_generic, 1097 .setup_link = &ixgbe_setup_phy_link_generic,
943 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, 1098 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1099 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
944}; 1100};
945 1101
946struct ixgbe_info ixgbe_82598_info = { 1102struct ixgbe_info ixgbe_82598_info = {
diff --git a/drivers/net/ixgbe/ixgbe_main.c b/drivers/net/ixgbe/ixgbe_main.c
index 91dde9cdab66..6620397a1fb4 100644
--- a/drivers/net/ixgbe/ixgbe_main.c
+++ b/drivers/net/ixgbe/ixgbe_main.c
@@ -74,8 +74,14 @@ static struct pci_device_id ixgbe_pci_tbl[] = {
74 board_82598 }, 74 board_82598 },
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), 75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
76 board_82598 }, 76 board_82598 },
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
78 board_82598 },
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
80 board_82598 },
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), 81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
78 board_82598 }, 82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
84 board_82598 },
79 85
80 /* required last entry */ 86 /* required last entry */
81 {0, } 87 {0, }
@@ -2680,6 +2686,57 @@ err_alloc_queues:
2680} 2686}
2681 2687
2682/** 2688/**
2689 * ixgbe_sfp_timer - worker thread to find a missing module
2690 * @data: pointer to our adapter struct
2691 **/
2692static void ixgbe_sfp_timer(unsigned long data)
2693{
2694 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
2695
2696 /* Do the sfp_timer outside of interrupt context due to the
2697 * delays that sfp+ detection requires
2698 */
2699 schedule_work(&adapter->sfp_task);
2700}
2701
2702/**
2703 * ixgbe_sfp_task - worker thread to find a missing module
2704 * @work: pointer to work_struct containing our data
2705 **/
2706static void ixgbe_sfp_task(struct work_struct *work)
2707{
2708 struct ixgbe_adapter *adapter = container_of(work,
2709 struct ixgbe_adapter,
2710 sfp_task);
2711 struct ixgbe_hw *hw = &adapter->hw;
2712
2713 if ((hw->phy.type == ixgbe_phy_nl) &&
2714 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
2715 s32 ret = hw->phy.ops.identify_sfp(hw);
2716 if (ret)
2717 goto reschedule;
2718 ret = hw->phy.ops.reset(hw);
2719 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2720 DPRINTK(PROBE, ERR, "failed to initialize because an "
2721 "unsupported SFP+ module type was detected.\n"
2722 "Reload the driver after installing a "
2723 "supported module.\n");
2724 unregister_netdev(adapter->netdev);
2725 } else {
2726 DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
2727 hw->phy.sfp_type);
2728 }
2729 /* don't need this routine any more */
2730 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
2731 }
2732 return;
2733reschedule:
2734 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
2735 mod_timer(&adapter->sfp_timer,
2736 round_jiffies(jiffies + (2 * HZ)));
2737}
2738
2739/**
2683 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) 2740 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2684 * @adapter: board private structure to initialize 2741 * @adapter: board private structure to initialize
2685 * 2742 *
@@ -4006,11 +4063,31 @@ static int __devinit ixgbe_probe(struct pci_dev *pdev,
4006 4063
4007 /* PHY */ 4064 /* PHY */
4008 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); 4065 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
4009 /* phy->sfp_type = ixgbe_sfp_type_unknown; */ 4066 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
4067
4068 /* set up this timer and work struct before calling get_invariants
4069 * which might start the timer
4070 */
4071 init_timer(&adapter->sfp_timer);
4072 adapter->sfp_timer.function = &ixgbe_sfp_timer;
4073 adapter->sfp_timer.data = (unsigned long) adapter;
4074
4075 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
4010 4076
4011 err = ii->get_invariants(hw); 4077 err = ii->get_invariants(hw);
4012 if (err) 4078 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
4079 /* start a kernel thread to watch for a module to arrive */
4080 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4081 mod_timer(&adapter->sfp_timer,
4082 round_jiffies(jiffies + (2 * HZ)));
4083 err = 0;
4084 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4085 DPRINTK(PROBE, ERR, "failed to load because an "
4086 "unsupported SFP+ module type was detected.\n");
4013 goto err_hw_init; 4087 goto err_hw_init;
4088 } else if (err) {
4089 goto err_hw_init;
4090 }
4014 4091
4015 /* setup the private structure */ 4092 /* setup the private structure */
4016 err = ixgbe_sw_init(adapter); 4093 err = ixgbe_sw_init(adapter);
@@ -4144,6 +4221,9 @@ err_hw_init:
4144err_sw_init: 4221err_sw_init:
4145 ixgbe_reset_interrupt_capability(adapter); 4222 ixgbe_reset_interrupt_capability(adapter);
4146err_eeprom: 4223err_eeprom:
4224 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4225 del_timer_sync(&adapter->sfp_timer);
4226 cancel_work_sync(&adapter->sfp_task);
4147 iounmap(hw->hw_addr); 4227 iounmap(hw->hw_addr);
4148err_ioremap: 4228err_ioremap:
4149 free_netdev(netdev); 4229 free_netdev(netdev);
@@ -4170,8 +4250,15 @@ static void __devexit ixgbe_remove(struct pci_dev *pdev)
4170 struct ixgbe_adapter *adapter = netdev_priv(netdev); 4250 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4171 4251
4172 set_bit(__IXGBE_DOWN, &adapter->state); 4252 set_bit(__IXGBE_DOWN, &adapter->state);
4253 /* clear the module not found bit to make sure the worker won't
4254 * reschedule
4255 */
4256 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4173 del_timer_sync(&adapter->watchdog_timer); 4257 del_timer_sync(&adapter->watchdog_timer);
4174 4258
4259 del_timer_sync(&adapter->sfp_timer);
4260 cancel_work_sync(&adapter->watchdog_task);
4261 cancel_work_sync(&adapter->sfp_task);
4175 flush_scheduled_work(); 4262 flush_scheduled_work();
4176 4263
4177#ifdef CONFIG_IXGBE_DCA 4264#ifdef CONFIG_IXGBE_DCA
@@ -4182,7 +4269,8 @@ static void __devexit ixgbe_remove(struct pci_dev *pdev)
4182 } 4269 }
4183 4270
4184#endif 4271#endif
4185 unregister_netdev(netdev); 4272 if (netdev->reg_state == NETREG_REGISTERED)
4273 unregister_netdev(netdev);
4186 4274
4187 ixgbe_reset_interrupt_capability(adapter); 4275 ixgbe_reset_interrupt_capability(adapter);
4188 4276
diff --git a/drivers/net/ixgbe/ixgbe_phy.c b/drivers/net/ixgbe/ixgbe_phy.c
index 981e6d849592..5a8669aedf64 100644
--- a/drivers/net/ixgbe/ixgbe_phy.c
+++ b/drivers/net/ixgbe/ixgbe_phy.c
@@ -127,6 +127,9 @@ static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
127 case QT2022_PHY_ID: 127 case QT2022_PHY_ID:
128 phy_type = ixgbe_phy_qt; 128 phy_type = ixgbe_phy_qt;
129 break; 129 break;
130 case ATH_PHY_ID:
131 phy_type = ixgbe_phy_nl;
132 break;
130 default: 133 default:
131 phy_type = ixgbe_phy_unknown; 134 phy_type = ixgbe_phy_unknown;
132 break; 135 break;
@@ -430,6 +433,261 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
430} 433}
431 434
432/** 435/**
436 * ixgbe_reset_phy_nl - Performs a PHY reset
437 * @hw: pointer to hardware structure
438 **/
439s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
440{
441 u16 phy_offset, control, eword, edata, block_crc;
442 bool end_data = false;
443 u16 list_offset, data_offset;
444 u16 phy_data = 0;
445 s32 ret_val = 0;
446 u32 i;
447
448 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
449 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
450
451 /* reset the PHY and poll for completion */
452 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
453 IXGBE_MDIO_PHY_XS_DEV_TYPE,
454 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
455
456 for (i = 0; i < 100; i++) {
457 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
458 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
459 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
460 break;
461 msleep(10);
462 }
463
464 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
465 hw_dbg(hw, "PHY reset did not complete.\n");
466 ret_val = IXGBE_ERR_PHY;
467 goto out;
468 }
469
470 /* Get init offsets */
471 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
472 &data_offset);
473 if (ret_val != 0)
474 goto out;
475
476 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
477 data_offset++;
478 while (!end_data) {
479 /*
480 * Read control word from PHY init contents offset
481 */
482 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
483 control = (eword & IXGBE_CONTROL_MASK_NL) >>
484 IXGBE_CONTROL_SHIFT_NL;
485 edata = eword & IXGBE_DATA_MASK_NL;
486 switch (control) {
487 case IXGBE_DELAY_NL:
488 data_offset++;
489 hw_dbg(hw, "DELAY: %d MS\n", edata);
490 msleep(edata);
491 break;
492 case IXGBE_DATA_NL:
493 hw_dbg(hw, "DATA: \n");
494 data_offset++;
495 hw->eeprom.ops.read(hw, data_offset++,
496 &phy_offset);
497 for (i = 0; i < edata; i++) {
498 hw->eeprom.ops.read(hw, data_offset, &eword);
499 hw->phy.ops.write_reg(hw, phy_offset,
500 IXGBE_TWINAX_DEV, eword);
501 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
502 phy_offset);
503 data_offset++;
504 phy_offset++;
505 }
506 break;
507 case IXGBE_CONTROL_NL:
508 data_offset++;
509 hw_dbg(hw, "CONTROL: \n");
510 if (edata == IXGBE_CONTROL_EOL_NL) {
511 hw_dbg(hw, "EOL\n");
512 end_data = true;
513 } else if (edata == IXGBE_CONTROL_SOL_NL) {
514 hw_dbg(hw, "SOL\n");
515 } else {
516 hw_dbg(hw, "Bad control value\n");
517 ret_val = IXGBE_ERR_PHY;
518 goto out;
519 }
520 break;
521 default:
522 hw_dbg(hw, "Bad control type\n");
523 ret_val = IXGBE_ERR_PHY;
524 goto out;
525 }
526 }
527
528out:
529 return ret_val;
530}
531
532/**
533 * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns
534 * the PHY type.
535 * @hw: pointer to hardware structure
536 *
537 * Searches for and indentifies the SFP module. Assings appropriate PHY type.
538 **/
539s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
540{
541 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
542 u32 vendor_oui = 0;
543 u8 identifier = 0;
544 u8 comp_codes_1g = 0;
545 u8 comp_codes_10g = 0;
546 u8 oui_bytes[4] = {0, 0, 0, 0};
547 u8 transmission_media = 0;
548
549 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
550 &identifier);
551
552 if (status == IXGBE_ERR_SFP_NOT_PRESENT) {
553 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
554 goto out;
555 }
556
557 if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
558 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
559 &comp_codes_1g);
560 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
561 &comp_codes_10g);
562 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_TRANSMISSION_MEDIA,
563 &transmission_media);
564
565 /* ID Module
566 * =========
567 * 0 SFP_DA_CU
568 * 1 SFP_SR
569 * 2 SFP_LR
570 */
571 if (transmission_media & IXGBE_SFF_TWIN_AX_CAPABLE)
572 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
573 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
574 hw->phy.sfp_type = ixgbe_sfp_type_sr;
575 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
576 hw->phy.sfp_type = ixgbe_sfp_type_lr;
577 else
578 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
579
580 /* Determine PHY vendor */
581 if (hw->phy.type == ixgbe_phy_unknown) {
582 hw->phy.id = identifier;
583 hw->phy.ops.read_i2c_eeprom(hw,
584 IXGBE_SFF_VENDOR_OUI_BYTE0,
585 &oui_bytes[0]);
586 hw->phy.ops.read_i2c_eeprom(hw,
587 IXGBE_SFF_VENDOR_OUI_BYTE1,
588 &oui_bytes[1]);
589 hw->phy.ops.read_i2c_eeprom(hw,
590 IXGBE_SFF_VENDOR_OUI_BYTE2,
591 &oui_bytes[2]);
592
593 vendor_oui =
594 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
595 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
596 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
597
598 switch (vendor_oui) {
599 case IXGBE_SFF_VENDOR_OUI_TYCO:
600 if (transmission_media &
601 IXGBE_SFF_TWIN_AX_CAPABLE)
602 hw->phy.type = ixgbe_phy_tw_tyco;
603 break;
604 case IXGBE_SFF_VENDOR_OUI_FTL:
605 hw->phy.type = ixgbe_phy_sfp_ftl;
606 break;
607 case IXGBE_SFF_VENDOR_OUI_AVAGO:
608 hw->phy.type = ixgbe_phy_sfp_avago;
609 break;
610 default:
611 if (transmission_media &
612 IXGBE_SFF_TWIN_AX_CAPABLE)
613 hw->phy.type = ixgbe_phy_tw_unknown;
614 else
615 hw->phy.type = ixgbe_phy_sfp_unknown;
616 break;
617 }
618 }
619 status = 0;
620 }
621
622out:
623 return status;
624}
625
626/**
627 * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see
628 * if it supports a given SFP+ module type, if so it returns the offsets to the
629 * phy init sequence block.
630 * @hw: pointer to hardware structure
631 * @list_offset: offset to the SFP ID list
632 * @data_offset: offset to the SFP data block
633 **/
634s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
635 u16 *list_offset,
636 u16 *data_offset)
637{
638 u16 sfp_id;
639
640 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
641 return IXGBE_ERR_SFP_NOT_SUPPORTED;
642
643 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
644 return IXGBE_ERR_SFP_NOT_PRESENT;
645
646 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
647 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
648 return IXGBE_ERR_SFP_NOT_SUPPORTED;
649
650 /* Read offset to PHY init contents */
651 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
652
653 if ((!*list_offset) || (*list_offset == 0xFFFF))
654 return IXGBE_ERR_PHY;
655
656 /* Shift offset to first ID word */
657 (*list_offset)++;
658
659 /*
660 * Find the matching SFP ID in the EEPROM
661 * and program the init sequence
662 */
663 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
664
665 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
666 if (sfp_id == hw->phy.sfp_type) {
667 (*list_offset)++;
668 hw->eeprom.ops.read(hw, *list_offset, data_offset);
669 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
670 hw_dbg(hw, "SFP+ module not supported\n");
671 return IXGBE_ERR_SFP_NOT_SUPPORTED;
672 } else {
673 break;
674 }
675 } else {
676 (*list_offset) += 2;
677 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
678 return IXGBE_ERR_PHY;
679 }
680 }
681
682 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
683 hw_dbg(hw, "No matching SFP+ module found\n");
684 return IXGBE_ERR_SFP_NOT_SUPPORTED;
685 }
686
687 return 0;
688}
689
690/**
433 * ixgbe_check_phy_link_tnx - Determine link and speed status 691 * ixgbe_check_phy_link_tnx - Determine link and speed status
434 * @hw: pointer to hardware structure 692 * @hw: pointer to hardware structure
435 * 693 *
diff --git a/drivers/net/ixgbe/ixgbe_phy.h b/drivers/net/ixgbe/ixgbe_phy.h
index 5cc063d02770..43a97bc420f5 100644
--- a/drivers/net/ixgbe/ixgbe_phy.h
+++ b/drivers/net/ixgbe/ixgbe_phy.h
@@ -63,6 +63,18 @@
63#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500 63#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
64#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00 64#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
65 65
66/* I2C SDA and SCL timing parameters for standard mode */
67#define IXGBE_I2C_T_HD_STA 4
68#define IXGBE_I2C_T_LOW 5
69#define IXGBE_I2C_T_HIGH 4
70#define IXGBE_I2C_T_SU_STA 5
71#define IXGBE_I2C_T_HD_DATA 5
72#define IXGBE_I2C_T_SU_DATA 1
73#define IXGBE_I2C_T_RISE 1
74#define IXGBE_I2C_T_FALL 1
75#define IXGBE_I2C_T_SU_STO 4
76#define IXGBE_I2C_T_BUF 5
77
66 78
67s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw); 79s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
68s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw); 80s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
@@ -84,4 +96,10 @@ s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
84s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 96s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
85 u16 *firmware_version); 97 u16 *firmware_version);
86 98
99s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
100s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
101s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
102 u16 *list_offset,
103 u16 *data_offset);
104
87#endif /* _IXGBE_PHY_H_ */ 105#endif /* _IXGBE_PHY_H_ */
diff --git a/drivers/net/ixgbe/ixgbe_type.h b/drivers/net/ixgbe/ixgbe_type.h
index 51df39dae816..83a11ff9ffd1 100644
--- a/drivers/net/ixgbe/ixgbe_type.h
+++ b/drivers/net/ixgbe/ixgbe_type.h
@@ -36,9 +36,12 @@
36/* Device IDs */ 36/* Device IDs */
37#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 37#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
38#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 38#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
39#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
39#define IXGBE_DEV_ID_82598AT 0x10C8 40#define IXGBE_DEV_ID_82598AT 0x10C8
40#define IXGBE_DEV_ID_82598EB_CX4 0x10DD 41#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
41#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC 42#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
43#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
44#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
42#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 45#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
43 46
44/* General Registers */ 47/* General Registers */
@@ -453,6 +456,7 @@
453#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4 456#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
454#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 457#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
455#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ 458#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
459#define IXGBE_TWINAX_DEV 1
456 460
457#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ 461#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
458 462
@@ -488,14 +492,27 @@
488#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 492#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
489#define IXGBE_MAX_PHY_ADDR 32 493#define IXGBE_MAX_PHY_ADDR 32
490 494
491/* PHY IDs*/ 495/* PHY IDs */
492#define TN1010_PHY_ID 0x00A19410 496#define TN1010_PHY_ID 0x00A19410
493#define TNX_FW_REV 0xB 497#define TNX_FW_REV 0xB
494#define QT2022_PHY_ID 0x0043A400 498#define QT2022_PHY_ID 0x0043A400
499#define ATH_PHY_ID 0x03429050
495 500
496/* PHY Types */ 501/* PHY Types */
497#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0 502#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
498 503
504/* Special PHY Init Routine */
505#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
506#define IXGBE_PHY_INIT_END_NL 0xFFFF
507#define IXGBE_CONTROL_MASK_NL 0xF000
508#define IXGBE_DATA_MASK_NL 0x0FFF
509#define IXGBE_CONTROL_SHIFT_NL 12
510#define IXGBE_DELAY_NL 0
511#define IXGBE_DATA_NL 1
512#define IXGBE_CONTROL_NL 0x000F
513#define IXGBE_CONTROL_EOL_NL 0x0FFF
514#define IXGBE_CONTROL_SOL_NL 0x0000
515
499/* General purpose Interrupt Enable */ 516/* General purpose Interrupt Enable */
500#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ 517#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
501#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */ 518#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
@@ -1208,6 +1225,7 @@ enum ixgbe_phy_type {
1208 ixgbe_phy_tn, 1225 ixgbe_phy_tn,
1209 ixgbe_phy_qt, 1226 ixgbe_phy_qt,
1210 ixgbe_phy_xaui, 1227 ixgbe_phy_xaui,
1228 ixgbe_phy_nl,
1211 ixgbe_phy_tw_tyco, 1229 ixgbe_phy_tw_tyco,
1212 ixgbe_phy_tw_unknown, 1230 ixgbe_phy_tw_unknown,
1213 ixgbe_phy_sfp_avago, 1231 ixgbe_phy_sfp_avago,
@@ -1229,6 +1247,7 @@ enum ixgbe_sfp_type {
1229 ixgbe_sfp_type_da_cu = 0, 1247 ixgbe_sfp_type_da_cu = 0,
1230 ixgbe_sfp_type_sr = 1, 1248 ixgbe_sfp_type_sr = 1,
1231 ixgbe_sfp_type_lr = 2, 1249 ixgbe_sfp_type_lr = 2,
1250 ixgbe_sfp_type_not_present = 0xFFFE,
1232 ixgbe_sfp_type_unknown = 0xFFFF 1251 ixgbe_sfp_type_unknown = 0xFFFF
1233}; 1252};
1234 1253
@@ -1492,6 +1511,7 @@ struct ixgbe_info {
1492#define IXGBE_ERR_PHY_ADDR_INVALID -17 1511#define IXGBE_ERR_PHY_ADDR_INVALID -17
1493#define IXGBE_ERR_I2C -18 1512#define IXGBE_ERR_I2C -18
1494#define IXGBE_ERR_SFP_NOT_SUPPORTED -19 1513#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
1514#define IXGBE_ERR_SFP_NOT_PRESENT -20
1495#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF 1515#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
1496 1516
1497#endif /* _IXGBE_TYPE_H_ */ 1517#endif /* _IXGBE_TYPE_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 19:20:24 -0500