diff options
-rw-r--r-- | arch/sh/kernel/cpu/sh3/setup-sh770x.c | 68 |
1 files changed, 21 insertions, 47 deletions
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c index 93c55e2ed952..a74f960b5e79 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c | |||
@@ -2,6 +2,7 @@ | |||
2 | * SH3 Setup code for SH7706, SH7707, SH7708, SH7709 | 2 | * SH3 Setup code for SH7706, SH7707, SH7708, SH7709 |
3 | * | 3 | * |
4 | * Copyright (C) 2007 Magnus Damm | 4 | * Copyright (C) 2007 Magnus Damm |
5 | * Copyright (C) 2009 Paul Mundt | ||
5 | * | 6 | * |
6 | * Based on setup-sh7709.c | 7 | * Based on setup-sh7709.c |
7 | * | 8 | * |
@@ -24,46 +25,37 @@ enum { | |||
24 | /* interrupt sources */ | 25 | /* interrupt sources */ |
25 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, | 26 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, |
26 | PINT07, PINT815, | 27 | PINT07, PINT815, |
27 | DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3, | 28 | DMAC, SCIF0, SCIF2, SCI, ADC_ADI, |
28 | SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, | ||
29 | SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, | ||
30 | SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI, | ||
31 | ADC_ADI, | ||
32 | LCDC, PCC0, PCC1, | 29 | LCDC, PCC0, PCC1, |
33 | TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, | 30 | TMU0, TMU1, TMU2, |
34 | RTC_ATI, RTC_PRI, RTC_CUI, | 31 | RTC, WDT, REF, |
35 | WDT, | ||
36 | REF_RCMI, REF_ROVI, | ||
37 | |||
38 | /* interrupt groups */ | ||
39 | RTC, REF, TMU2, DMAC, SCI, SCIF2, SCIF0, | ||
40 | }; | 32 | }; |
41 | 33 | ||
42 | static struct intc_vect vectors[] __initdata = { | 34 | static struct intc_vect vectors[] __initdata = { |
43 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), | 35 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
44 | INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), | 36 | INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), |
45 | INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), | 37 | INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), |
46 | INTC_VECT(RTC_CUI, 0x4c0), | 38 | INTC_VECT(RTC, 0x4c0), |
47 | INTC_VECT(SCI_ERI, 0x4e0), INTC_VECT(SCI_RXI, 0x500), | 39 | INTC_VECT(SCI, 0x4e0), INTC_VECT(SCI, 0x500), |
48 | INTC_VECT(SCI_TXI, 0x520), INTC_VECT(SCI_TEI, 0x540), | 40 | INTC_VECT(SCI, 0x520), INTC_VECT(SCI, 0x540), |
49 | INTC_VECT(WDT, 0x560), | 41 | INTC_VECT(WDT, 0x560), |
50 | INTC_VECT(REF_RCMI, 0x580), | 42 | INTC_VECT(REF, 0x580), |
51 | INTC_VECT(REF_ROVI, 0x5a0), | 43 | INTC_VECT(REF, 0x5a0), |
52 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ | 44 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
53 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | 45 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
54 | defined(CONFIG_CPU_SUBTYPE_SH7709) | 46 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
55 | /* IRQ0->5 are handled in setup-sh3.c */ | 47 | /* IRQ0->5 are handled in setup-sh3.c */ |
56 | INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), | 48 | INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820), |
57 | INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), | 49 | INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860), |
58 | INTC_VECT(ADC_ADI, 0x980), | 50 | INTC_VECT(ADC_ADI, 0x980), |
59 | INTC_VECT(SCIF2_ERI, 0x900), INTC_VECT(SCIF2_RXI, 0x920), | 51 | INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920), |
60 | INTC_VECT(SCIF2_BRI, 0x940), INTC_VECT(SCIF2_TXI, 0x960), | 52 | INTC_VECT(SCIF2, 0x940), INTC_VECT(SCIF2, 0x960), |
61 | #endif | 53 | #endif |
62 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | 54 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
63 | defined(CONFIG_CPU_SUBTYPE_SH7709) | 55 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
64 | INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), | 56 | INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), |
65 | INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0), | 57 | INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0), |
66 | INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0), | 58 | INTC_VECT(SCIF0, 0x8c0), INTC_VECT(SCIF0, 0x8e0), |
67 | #endif | 59 | #endif |
68 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) | 60 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) |
69 | INTC_VECT(LCDC, 0x9a0), | 61 | INTC_VECT(LCDC, 0x9a0), |
@@ -71,16 +63,6 @@ static struct intc_vect vectors[] __initdata = { | |||
71 | #endif | 63 | #endif |
72 | }; | 64 | }; |
73 | 65 | ||
74 | static struct intc_group groups[] __initdata = { | ||
75 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), | ||
76 | INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), | ||
77 | INTC_GROUP(REF, REF_RCMI, REF_ROVI), | ||
78 | INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3), | ||
79 | INTC_GROUP(SCI, SCI_ERI, SCI_RXI, SCI_TXI, SCI_TEI), | ||
80 | INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), | ||
81 | INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI), | ||
82 | }; | ||
83 | |||
84 | static struct intc_prio_reg prio_registers[] __initdata = { | 66 | static struct intc_prio_reg prio_registers[] __initdata = { |
85 | { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, | 67 | { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, |
86 | { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } }, | 68 | { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } }, |
@@ -101,7 +83,7 @@ static struct intc_prio_reg prio_registers[] __initdata = { | |||
101 | #endif | 83 | #endif |
102 | }; | 84 | }; |
103 | 85 | ||
104 | static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, groups, | 86 | static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, NULL, |
105 | NULL, prio_registers, NULL); | 87 | NULL, prio_registers, NULL); |
106 | 88 | ||
107 | static struct resource rtc_resources[] = { | 89 | static struct resource rtc_resources[] = { |
@@ -111,14 +93,6 @@ static struct resource rtc_resources[] = { | |||
111 | .flags = IORESOURCE_IO, | 93 | .flags = IORESOURCE_IO, |
112 | }, | 94 | }, |
113 | [1] = { | 95 | [1] = { |
114 | .start = 21, | ||
115 | .flags = IORESOURCE_IRQ, | ||
116 | }, | ||
117 | [2] = { | ||
118 | .start = 22, | ||
119 | .flags = IORESOURCE_IRQ, | ||
120 | }, | ||
121 | [3] = { | ||
122 | .start = 20, | 96 | .start = 20, |
123 | .flags = IORESOURCE_IRQ, | 97 | .flags = IORESOURCE_IRQ, |
124 | }, | 98 | }, |
@@ -136,7 +110,7 @@ static struct plat_sci_port sci_platform_data[] = { | |||
136 | .mapbase = 0xfffffe80, | 110 | .mapbase = 0xfffffe80, |
137 | .flags = UPF_BOOT_AUTOCONF, | 111 | .flags = UPF_BOOT_AUTOCONF, |
138 | .type = PORT_SCI, | 112 | .type = PORT_SCI, |
139 | .irqs = { 23, 24, 25, 0 }, | 113 | .irqs = { 23, 23, 23, 0 }, |
140 | }, | 114 | }, |
141 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ | 115 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
142 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | 116 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
@@ -145,7 +119,7 @@ static struct plat_sci_port sci_platform_data[] = { | |||
145 | .mapbase = 0xa4000150, | 119 | .mapbase = 0xa4000150, |
146 | .flags = UPF_BOOT_AUTOCONF, | 120 | .flags = UPF_BOOT_AUTOCONF, |
147 | .type = PORT_SCIF, | 121 | .type = PORT_SCIF, |
148 | .irqs = { 56, 57, 59, 58 }, | 122 | .irqs = { 56, 56, 56, 56 }, |
149 | }, | 123 | }, |
150 | #endif | 124 | #endif |
151 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | 125 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
@@ -154,7 +128,7 @@ static struct plat_sci_port sci_platform_data[] = { | |||
154 | .mapbase = 0xa4000140, | 128 | .mapbase = 0xa4000140, |
155 | .flags = UPF_BOOT_AUTOCONF, | 129 | .flags = UPF_BOOT_AUTOCONF, |
156 | .type = PORT_IRDA, | 130 | .type = PORT_IRDA, |
157 | .irqs = { 52, 53, 55, 54 }, | 131 | .irqs = { 52, 52, 52, 52 }, |
158 | }, | 132 | }, |
159 | #endif | 133 | #endif |
160 | { | 134 | { |