aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/sparc64/kernel/entry.S309
1 files changed, 173 insertions, 136 deletions
diff --git a/arch/sparc64/kernel/entry.S b/arch/sparc64/kernel/entry.S
index cecdc0a7521f..3e0badb820c5 100644
--- a/arch/sparc64/kernel/entry.S
+++ b/arch/sparc64/kernel/entry.S
@@ -927,139 +927,6 @@ __spitfire_insn_access_exception:
927 ba,pt %xcc, rtrap 927 ba,pt %xcc, rtrap
928 clr %l6 928 clr %l6
929 929
930 /* Capture I/D/E-cache state into per-cpu error scoreboard.
931 *
932 * %g1: (TL>=0) ? 1 : 0
933 * %g2: scratch
934 * %g3: scratch
935 * %g4: AFSR
936 * %g5: AFAR
937 * %g6: current thread ptr
938 * %g7: scratch
939 */
940#define CHEETAH_LOG_ERROR \
941 /* Put "TL1" software bit into AFSR. */ \
942 and %g1, 0x1, %g1; \
943 sllx %g1, 63, %g2; \
944 or %g4, %g2, %g4; \
945 /* Get log entry pointer for this cpu at this trap level. */ \
946 BRANCH_IF_JALAPENO(g2,g3,50f) \
947 ldxa [%g0] ASI_SAFARI_CONFIG, %g2; \
948 srlx %g2, 17, %g2; \
949 ba,pt %xcc, 60f; \
950 and %g2, 0x3ff, %g2; \
95150: ldxa [%g0] ASI_JBUS_CONFIG, %g2; \
952 srlx %g2, 17, %g2; \
953 and %g2, 0x1f, %g2; \
95460: sllx %g2, 9, %g2; \
955 sethi %hi(cheetah_error_log), %g3; \
956 ldx [%g3 + %lo(cheetah_error_log)], %g3; \
957 brz,pn %g3, 80f; \
958 nop; \
959 add %g3, %g2, %g3; \
960 sllx %g1, 8, %g1; \
961 add %g3, %g1, %g1; \
962 /* %g1 holds pointer to the top of the logging scoreboard */ \
963 ldx [%g1 + 0x0], %g7; \
964 cmp %g7, -1; \
965 bne,pn %xcc, 80f; \
966 nop; \
967 stx %g4, [%g1 + 0x0]; \
968 stx %g5, [%g1 + 0x8]; \
969 add %g1, 0x10, %g1; \
970 /* %g1 now points to D-cache logging area */ \
971 set 0x3ff8, %g2; /* DC_addr mask */ \
972 and %g5, %g2, %g2; /* DC_addr bits of AFAR */ \
973 srlx %g5, 12, %g3; \
974 or %g3, 1, %g3; /* PHYS tag + valid */ \
97510: ldxa [%g2] ASI_DCACHE_TAG, %g7; \
976 cmp %g3, %g7; /* TAG match? */ \
977 bne,pt %xcc, 13f; \
978 nop; \
979 /* Yep, what we want, capture state. */ \
980 stx %g2, [%g1 + 0x20]; \
981 stx %g7, [%g1 + 0x28]; \
982 /* A membar Sync is required before and after utag access. */ \
983 membar #Sync; \
984 ldxa [%g2] ASI_DCACHE_UTAG, %g7; \
985 membar #Sync; \
986 stx %g7, [%g1 + 0x30]; \
987 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7; \
988 stx %g7, [%g1 + 0x38]; \
989 clr %g3; \
99012: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7; \
991 stx %g7, [%g1]; \
992 add %g3, (1 << 5), %g3; \
993 cmp %g3, (4 << 5); \
994 bl,pt %xcc, 12b; \
995 add %g1, 0x8, %g1; \
996 ba,pt %xcc, 20f; \
997 add %g1, 0x20, %g1; \
99813: sethi %hi(1 << 14), %g7; \
999 add %g2, %g7, %g2; \
1000 srlx %g2, 14, %g7; \
1001 cmp %g7, 4; \
1002 bl,pt %xcc, 10b; \
1003 nop; \
1004 add %g1, 0x40, %g1; \
100520: /* %g1 now points to I-cache logging area */ \
1006 set 0x1fe0, %g2; /* IC_addr mask */ \
1007 and %g5, %g2, %g2; /* IC_addr bits of AFAR */ \
1008 sllx %g2, 1, %g2; /* IC_addr[13:6]==VA[12:5] */ \
1009 srlx %g5, (13 - 8), %g3; /* Make PTAG */ \
1010 andn %g3, 0xff, %g3; /* Mask off undefined bits */ \
101121: ldxa [%g2] ASI_IC_TAG, %g7; \
1012 andn %g7, 0xff, %g7; \
1013 cmp %g3, %g7; \
1014 bne,pt %xcc, 23f; \
1015 nop; \
1016 /* Yep, what we want, capture state. */ \
1017 stx %g2, [%g1 + 0x40]; \
1018 stx %g7, [%g1 + 0x48]; \
1019 add %g2, (1 << 3), %g2; \
1020 ldxa [%g2] ASI_IC_TAG, %g7; \
1021 add %g2, (1 << 3), %g2; \
1022 stx %g7, [%g1 + 0x50]; \
1023 ldxa [%g2] ASI_IC_TAG, %g7; \
1024 add %g2, (1 << 3), %g2; \
1025 stx %g7, [%g1 + 0x60]; \
1026 ldxa [%g2] ASI_IC_TAG, %g7; \
1027 stx %g7, [%g1 + 0x68]; \
1028 sub %g2, (3 << 3), %g2; \
1029 ldxa [%g2] ASI_IC_STAG, %g7; \
1030 stx %g7, [%g1 + 0x58]; \
1031 clr %g3; \
1032 srlx %g2, 2, %g2; \
103322: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7; \
1034 stx %g7, [%g1]; \
1035 add %g3, (1 << 3), %g3; \
1036 cmp %g3, (8 << 3); \
1037 bl,pt %xcc, 22b; \
1038 add %g1, 0x8, %g1; \
1039 ba,pt %xcc, 30f; \
1040 add %g1, 0x30, %g1; \
104123: sethi %hi(1 << 14), %g7; \
1042 add %g2, %g7, %g2; \
1043 srlx %g2, 14, %g7; \
1044 cmp %g7, 4; \
1045 bl,pt %xcc, 21b; \
1046 nop; \
1047 add %g1, 0x70, %g1; \
104830: /* %g1 now points to E-cache logging area */ \
1049 andn %g5, (32 - 1), %g2; /* E-cache subblock */ \
1050 stx %g2, [%g1 + 0x20]; \
1051 ldxa [%g2] ASI_EC_TAG_DATA, %g7; \
1052 stx %g7, [%g1 + 0x28]; \
1053 ldxa [%g2] ASI_EC_R, %g0; \
1054 clr %g3; \
105531: ldxa [%g3] ASI_EC_DATA, %g7; \
1056 stx %g7, [%g1 + %g3]; \
1057 add %g3, 0x8, %g3; \
1058 cmp %g3, 0x20; \
1059 bl,pt %xcc, 31b; \
1060 nop; \
106180: /* DONE */
1062
1063 /* These get patched into the trap table at boot time 930 /* These get patched into the trap table at boot time
1064 * once we know we have a cheetah processor. 931 * once we know we have a cheetah processor.
1065 */ 932 */
@@ -1296,6 +1163,170 @@ dcpe_icpe_tl1_common:
1296 membar #Sync 1163 membar #Sync
1297 retry 1164 retry
1298 1165
1166 /* Capture I/D/E-cache state into per-cpu error scoreboard.
1167 *
1168 * %g1: (TL>=0) ? 1 : 0
1169 * %g2: scratch
1170 * %g3: scratch
1171 * %g4: AFSR
1172 * %g5: AFAR
1173 * %g6: current thread ptr
1174 * %g7: scratch
1175 */
1176__cheetah_log_error:
1177 /* Put "TL1" software bit into AFSR. */
1178 and %g1, 0x1, %g1
1179 sllx %g1, 63, %g2
1180 or %g4, %g2, %g4
1181
1182 /* Get log entry pointer for this cpu at this trap level. */
1183 BRANCH_IF_JALAPENO(g2,g3,50f)
1184 ldxa [%g0] ASI_SAFARI_CONFIG, %g2
1185 srlx %g2, 17, %g2
1186 ba,pt %xcc, 60f
1187 and %g2, 0x3ff, %g2
1188
118950: ldxa [%g0] ASI_JBUS_CONFIG, %g2
1190 srlx %g2, 17, %g2
1191 and %g2, 0x1f, %g2
1192
119360: sllx %g2, 9, %g2
1194 sethi %hi(cheetah_error_log), %g3
1195 ldx [%g3 + %lo(cheetah_error_log)], %g3
1196 brz,pn %g3, 80f
1197 nop
1198
1199 add %g3, %g2, %g3
1200 sllx %g1, 8, %g1
1201 add %g3, %g1, %g1
1202
1203 /* %g1 holds pointer to the top of the logging scoreboard */
1204 ldx [%g1 + 0x0], %g7
1205 cmp %g7, -1
1206 bne,pn %xcc, 80f
1207 nop
1208
1209 stx %g4, [%g1 + 0x0]
1210 stx %g5, [%g1 + 0x8]
1211 add %g1, 0x10, %g1
1212
1213 /* %g1 now points to D-cache logging area */
1214 set 0x3ff8, %g2 /* DC_addr mask */
1215 and %g5, %g2, %g2 /* DC_addr bits of AFAR */
1216 srlx %g5, 12, %g3
1217 or %g3, 1, %g3 /* PHYS tag + valid */
1218
121910: ldxa [%g2] ASI_DCACHE_TAG, %g7
1220 cmp %g3, %g7 /* TAG match? */
1221 bne,pt %xcc, 13f
1222 nop
1223
1224 /* Yep, what we want, capture state. */
1225 stx %g2, [%g1 + 0x20]
1226 stx %g7, [%g1 + 0x28]
1227
1228 /* A membar Sync is required before and after utag access. */
1229 membar #Sync
1230 ldxa [%g2] ASI_DCACHE_UTAG, %g7
1231 membar #Sync
1232 stx %g7, [%g1 + 0x30]
1233 ldxa [%g2] ASI_DCACHE_SNOOP_TAG, %g7
1234 stx %g7, [%g1 + 0x38]
1235 clr %g3
1236
123712: ldxa [%g2 + %g3] ASI_DCACHE_DATA, %g7
1238 stx %g7, [%g1]
1239 add %g3, (1 << 5), %g3
1240 cmp %g3, (4 << 5)
1241 bl,pt %xcc, 12b
1242 add %g1, 0x8, %g1
1243
1244 ba,pt %xcc, 20f
1245 add %g1, 0x20, %g1
1246
124713: sethi %hi(1 << 14), %g7
1248 add %g2, %g7, %g2
1249 srlx %g2, 14, %g7
1250 cmp %g7, 4
1251 bl,pt %xcc, 10b
1252 nop
1253
1254 add %g1, 0x40, %g1
1255
1256 /* %g1 now points to I-cache logging area */
125720: set 0x1fe0, %g2 /* IC_addr mask */
1258 and %g5, %g2, %g2 /* IC_addr bits of AFAR */
1259 sllx %g2, 1, %g2 /* IC_addr[13:6]==VA[12:5] */
1260 srlx %g5, (13 - 8), %g3 /* Make PTAG */
1261 andn %g3, 0xff, %g3 /* Mask off undefined bits */
1262
126321: ldxa [%g2] ASI_IC_TAG, %g7
1264 andn %g7, 0xff, %g7
1265 cmp %g3, %g7
1266 bne,pt %xcc, 23f
1267 nop
1268
1269 /* Yep, what we want, capture state. */
1270 stx %g2, [%g1 + 0x40]
1271 stx %g7, [%g1 + 0x48]
1272 add %g2, (1 << 3), %g2
1273 ldxa [%g2] ASI_IC_TAG, %g7
1274 add %g2, (1 << 3), %g2
1275 stx %g7, [%g1 + 0x50]
1276 ldxa [%g2] ASI_IC_TAG, %g7
1277 add %g2, (1 << 3), %g2
1278 stx %g7, [%g1 + 0x60]
1279 ldxa [%g2] ASI_IC_TAG, %g7
1280 stx %g7, [%g1 + 0x68]
1281 sub %g2, (3 << 3), %g2
1282 ldxa [%g2] ASI_IC_STAG, %g7
1283 stx %g7, [%g1 + 0x58]
1284 clr %g3
1285 srlx %g2, 2, %g2
1286
128722: ldxa [%g2 + %g3] ASI_IC_INSTR, %g7
1288 stx %g7, [%g1]
1289 add %g3, (1 << 3), %g3
1290 cmp %g3, (8 << 3)
1291 bl,pt %xcc, 22b
1292 add %g1, 0x8, %g1
1293
1294 ba,pt %xcc, 30f
1295 add %g1, 0x30, %g1
1296
129723: sethi %hi(1 << 14), %g7
1298 add %g2, %g7, %g2
1299 srlx %g2, 14, %g7
1300 cmp %g7, 4
1301 bl,pt %xcc, 21b
1302 nop
1303
1304 add %g1, 0x70, %g1
1305
1306 /* %g1 now points to E-cache logging area */
130730: andn %g5, (32 - 1), %g2
1308 stx %g2, [%g1 + 0x20]
1309 ldxa [%g2] ASI_EC_TAG_DATA, %g7
1310 stx %g7, [%g1 + 0x28]
1311 ldxa [%g2] ASI_EC_R, %g0
1312 clr %g3
1313
131431: ldxa [%g3] ASI_EC_DATA, %g7
1315 stx %g7, [%g1 + %g3]
1316 add %g3, 0x8, %g3
1317 cmp %g3, 0x20
1318
1319 bl,pt %xcc, 31b
1320 nop
132180:
1322 rdpr %tt, %g2
1323 cmp %g2, 0x70
1324 be c_fast_ecc
1325 cmp %g2, 0x63
1326 be c_cee
1327 nop
1328 ba,pt %xcc, c_deferred
1329
1299 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc 1330 /* Cheetah FECC trap handling, we get here from tl{0,1}_fecc
1300 * in the trap table. That code has done a memory barrier 1331 * in the trap table. That code has done a memory barrier
1301 * and has disabled both the I-cache and D-cache in the DCU 1332 * and has disabled both the I-cache and D-cache in the DCU
@@ -1321,8 +1352,10 @@ cheetah_fast_ecc:
1321 stxa %g4, [%g0] ASI_AFSR 1352 stxa %g4, [%g0] ASI_AFSR
1322 membar #Sync 1353 membar #Sync
1323 1354
1324 CHEETAH_LOG_ERROR 1355 ba,pt %xcc, __cheetah_log_error
1356 nop
1325 1357
1358c_fast_ecc:
1326 rdpr %pil, %g2 1359 rdpr %pil, %g2
1327 wrpr %g0, 15, %pil 1360 wrpr %g0, 15, %pil
1328 ba,pt %xcc, etrap_irq 1361 ba,pt %xcc, etrap_irq
@@ -1347,8 +1380,10 @@ cheetah_cee:
1347 stxa %g4, [%g0] ASI_AFSR 1380 stxa %g4, [%g0] ASI_AFSR
1348 membar #Sync 1381 membar #Sync
1349 1382
1350 CHEETAH_LOG_ERROR 1383 ba,pt %xcc, __cheetah_log_error
1384 nop
1351 1385
1386c_cee:
1352 rdpr %pil, %g2 1387 rdpr %pil, %g2
1353 wrpr %g0, 15, %pil 1388 wrpr %g0, 15, %pil
1354 ba,pt %xcc, etrap_irq 1389 ba,pt %xcc, etrap_irq
@@ -1373,8 +1408,10 @@ cheetah_deferred_trap:
1373 stxa %g4, [%g0] ASI_AFSR 1408 stxa %g4, [%g0] ASI_AFSR
1374 membar #Sync 1409 membar #Sync
1375 1410
1376 CHEETAH_LOG_ERROR 1411 ba,pt %xcc, __cheetah_log_error
1412 nop
1377 1413
1414c_deferred:
1378 rdpr %pil, %g2 1415 rdpr %pil, %g2
1379 wrpr %g0, 15, %pil 1416 wrpr %g0, 15, %pil
1380 ba,pt %xcc, etrap_irq 1417 ba,pt %xcc, etrap_irq
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 09:52:35 -0500