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-rw-r--r--arch/powerpc/kernel/paca.c33
-rw-r--r--arch/powerpc/platforms/iseries/lpardata.c72
-rw-r--r--arch/powerpc/xmon/xmon.c11
-rw-r--r--include/asm-powerpc/iseries/it_lp_reg_save.h85
-rw-r--r--include/asm-powerpc/paca.h12
5 files changed, 73 insertions, 140 deletions
diff --git a/arch/powerpc/kernel/paca.c b/arch/powerpc/kernel/paca.c
index 55f1a25085cd..867b22d17385 100644
--- a/arch/powerpc/kernel/paca.c
+++ b/arch/powerpc/kernel/paca.c
@@ -15,7 +15,6 @@
15#include <asm/ptrace.h> 15#include <asm/ptrace.h>
16#include <asm/page.h> 16#include <asm/page.h>
17#include <asm/lppaca.h> 17#include <asm/lppaca.h>
18#include <asm/iseries/it_lp_reg_save.h>
19#include <asm/paca.h> 18#include <asm/paca.h>
20#include <asm/mmu.h> 19#include <asm/mmu.h>
21 20
@@ -25,13 +24,13 @@
25extern unsigned long __toc_start; 24extern unsigned long __toc_start;
26 25
27/* 26/*
28 * iSeries structure which the hypervisor knows about - this structure 27 * The structure which the hypervisor knows about - this structure
29 * should not cross a page boundary. The vpa_init/register_vpa call 28 * should not cross a page boundary. The vpa_init/register_vpa call
30 * is now known to fail if the lppaca structure crosses a page 29 * is now known to fail if the lppaca structure crosses a page
31 * boundary. The lppaca is also used on POWER5 pSeries boxes. The 30 * boundary. The lppaca is also used on legacy iSeries and POWER5
32 * lppaca is 640 bytes long, and cannot readily change since the 31 * pSeries boxes. The lppaca is 640 bytes long, and cannot readily
33 * hypervisor knows its layout, so a 1kB alignment will suffice to 32 * change since the hypervisor knows its layout, so a 1kB alignment
34 * ensure that it doesn't cross a page boundary. 33 * will suffice to ensure that it doesn't cross a page boundary.
35 */ 34 */
36struct lppaca lppaca[] = { 35struct lppaca lppaca[] = {
37 [0 ... (NR_CPUS-1)] = { 36 [0 ... (NR_CPUS-1)] = {
@@ -66,32 +65,16 @@ struct slb_shadow slb_shadow[] __cacheline_aligned = {
66 * processors. The processor VPD array needs one entry per physical 65 * processors. The processor VPD array needs one entry per physical
67 * processor (not thread). 66 * processor (not thread).
68 */ 67 */
69#define PACA_INIT_COMMON(number) \ 68#define PACA_INIT(number) \
69{ \
70 .lppaca_ptr = &lppaca[number], \ 70 .lppaca_ptr = &lppaca[number], \
71 .lock_token = 0x8000, \ 71 .lock_token = 0x8000, \
72 .paca_index = (number), /* Paca Index */ \ 72 .paca_index = (number), /* Paca Index */ \
73 .kernel_toc = (unsigned long)(&__toc_start) + 0x8000UL, \ 73 .kernel_toc = (unsigned long)(&__toc_start) + 0x8000UL, \
74 .hw_cpu_id = 0xffff, \ 74 .hw_cpu_id = 0xffff, \
75 .slb_shadow_ptr = &slb_shadow[number], 75 .slb_shadow_ptr = &slb_shadow[number], \
76
77#ifdef CONFIG_PPC_ISERIES
78#define PACA_INIT_ISERIES(number) \
79 .reg_save_ptr = &iseries_reg_save[number],
80
81#define PACA_INIT(number) \
82{ \
83 PACA_INIT_COMMON(number) \
84 PACA_INIT_ISERIES(number) \
85} 76}
86 77
87#else
88#define PACA_INIT(number) \
89{ \
90 PACA_INIT_COMMON(number) \
91}
92
93#endif
94
95struct paca_struct paca[] = { 78struct paca_struct paca[] = {
96 PACA_INIT(0), 79 PACA_INIT(0),
97#if NR_CPUS > 1 80#if NR_CPUS > 1
diff --git a/arch/powerpc/platforms/iseries/lpardata.c b/arch/powerpc/platforms/iseries/lpardata.c
index dc8470850a81..2331d97e49f3 100644
--- a/arch/powerpc/platforms/iseries/lpardata.c
+++ b/arch/powerpc/platforms/iseries/lpardata.c
@@ -14,7 +14,6 @@
14#include <asm/ptrace.h> 14#include <asm/ptrace.h>
15#include <asm/abs_addr.h> 15#include <asm/abs_addr.h>
16#include <asm/lppaca.h> 16#include <asm/lppaca.h>
17#include <asm/iseries/it_lp_reg_save.h>
18#include <asm/paca.h> 17#include <asm/paca.h>
19#include <asm/iseries/lpar_map.h> 18#include <asm/iseries/lpar_map.h>
20#include <asm/iseries/it_lp_queue.h> 19#include <asm/iseries/it_lp_queue.h>
@@ -62,6 +61,63 @@ struct naca_struct naca = {
62 .xRamDiskSize = 0, 61 .xRamDiskSize = 0,
63}; 62};
64 63
64struct ItLpRegSave {
65 u32 xDesc; // Eye catcher "LpRS" ebcdic 000-003
66 u16 xSize; // Size of this class 004-005
67 u8 xInUse; // Area is live 006-007
68 u8 xRsvd1[9]; // Reserved 007-00F
69
70 u8 xFixedRegSave[352]; // Fixed Register Save Area 010-16F
71 u32 xCTRL; // Control Register 170-173
72 u32 xDEC; // Decrementer 174-177
73 u32 xFPSCR; // FP Status and Control Reg 178-17B
74 u32 xPVR; // Processor Version Number 17C-17F
75
76 u64 xMMCR0; // Monitor Mode Control Reg 0 180-187
77 u32 xPMC1; // Perf Monitor Counter 1 188-18B
78 u32 xPMC2; // Perf Monitor Counter 2 18C-18F
79 u32 xPMC3; // Perf Monitor Counter 3 190-193
80 u32 xPMC4; // Perf Monitor Counter 4 194-197
81 u32 xPIR; // Processor ID Reg 198-19B
82
83 u32 xMMCR1; // Monitor Mode Control Reg 1 19C-19F
84 u32 xMMCRA; // Monitor Mode Control Reg A 1A0-1A3
85 u32 xPMC5; // Perf Monitor Counter 5 1A4-1A7
86 u32 xPMC6; // Perf Monitor Counter 6 1A8-1AB
87 u32 xPMC7; // Perf Monitor Counter 7 1AC-1AF
88 u32 xPMC8; // Perf Monitor Counter 8 1B0-1B3
89 u32 xTSC; // Thread Switch Control 1B4-1B7
90 u32 xTST; // Thread Switch Timeout 1B8-1BB
91 u32 xRsvd; // Reserved 1BC-1BF
92
93 u64 xACCR; // Address Compare Control Reg 1C0-1C7
94 u64 xIMR; // Instruction Match Register 1C8-1CF
95 u64 xSDR1; // Storage Description Reg 1 1D0-1D7
96 u64 xSPRG0; // Special Purpose Reg General0 1D8-1DF
97 u64 xSPRG1; // Special Purpose Reg General1 1E0-1E7
98 u64 xSPRG2; // Special Purpose Reg General2 1E8-1EF
99 u64 xSPRG3; // Special Purpose Reg General3 1F0-1F7
100 u64 xTB; // Time Base Register 1F8-1FF
101
102 u64 xFPR[32]; // Floating Point Registers 200-2FF
103
104 u64 xMSR; // Machine State Register 300-307
105 u64 xNIA; // Next Instruction Address 308-30F
106
107 u64 xDABR; // Data Address Breakpoint Reg 310-317
108 u64 xIABR; // Inst Address Breakpoint Reg 318-31F
109
110 u64 xHID0; // HW Implementation Dependent0 320-327
111
112 u64 xHID4; // HW Implementation Dependent4 328-32F
113 u64 xSCOMd; // SCON Data Reg (SPRG4) 330-337
114 u64 xSCOMc; // SCON Command Reg (SPRG5) 338-33F
115 u64 xSDAR; // Sample Data Address Register 340-347
116 u64 xSIAR; // Sample Inst Address Register 348-34F
117
118 u8 xRsvd3[176]; // Reserved 350-3FF
119};
120
65extern void system_reset_iSeries(void); 121extern void system_reset_iSeries(void);
66extern void machine_check_iSeries(void); 122extern void machine_check_iSeries(void);
67extern void data_access_iSeries(void); 123extern void data_access_iSeries(void);
@@ -160,6 +216,13 @@ struct SpCommArea xSpCommArea = {
160 .xFormat = 1, 216 .xFormat = 1,
161}; 217};
162 218
219static struct ItLpRegSave iseries_reg_save[] = {
220 [0 ... (NR_CPUS-1)] = {
221 .xDesc = 0xd397d9e2, /* "LpRS" */
222 .xSize = sizeof(struct ItLpRegSave),
223 },
224};
225
163#define ALPACA_INIT(number) \ 226#define ALPACA_INIT(number) \
164{ \ 227{ \
165 .lppaca_ptr = &lppaca[number], \ 228 .lppaca_ptr = &lppaca[number], \
@@ -254,10 +317,3 @@ struct ItVpdAreas itVpdAreas = {
254 0,0 317 0,0
255 } 318 }
256}; 319};
257
258struct ItLpRegSave iseries_reg_save[] = {
259 [0 ... (NR_CPUS-1)] = {
260 .xDesc = 0xd397d9e2, /* "LpRS" */
261 .xSize = sizeof(struct ItLpRegSave),
262 },
263};
diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
index a34172ddc468..00fd7647f807 100644
--- a/arch/powerpc/xmon/xmon.c
+++ b/arch/powerpc/xmon/xmon.c
@@ -45,7 +45,6 @@
45#ifdef CONFIG_PPC64 45#ifdef CONFIG_PPC64
46#include <asm/hvcall.h> 46#include <asm/hvcall.h>
47#include <asm/paca.h> 47#include <asm/paca.h>
48#include <asm/iseries/it_lp_reg_save.h>
49#endif 48#endif
50 49
51#include "nonstdio.h" 50#include "nonstdio.h"
@@ -1598,7 +1597,6 @@ void super_regs(void)
1598 if (firmware_has_feature(FW_FEATURE_ISERIES)) { 1597 if (firmware_has_feature(FW_FEATURE_ISERIES)) {
1599 struct paca_struct *ptrPaca; 1598 struct paca_struct *ptrPaca;
1600 struct lppaca *ptrLpPaca; 1599 struct lppaca *ptrLpPaca;
1601 struct ItLpRegSave *ptrLpRegSave;
1602 1600
1603 /* Dump out relevant Paca data areas. */ 1601 /* Dump out relevant Paca data areas. */
1604 printf("Paca: \n"); 1602 printf("Paca: \n");
@@ -1611,15 +1609,6 @@ void super_regs(void)
1611 printf(" Saved Gpr3=%.16lx Saved Gpr4=%.16lx \n", 1609 printf(" Saved Gpr3=%.16lx Saved Gpr4=%.16lx \n",
1612 ptrLpPaca->saved_gpr3, ptrLpPaca->saved_gpr4); 1610 ptrLpPaca->saved_gpr3, ptrLpPaca->saved_gpr4);
1613 printf(" Saved Gpr5=%.16lx \n", ptrLpPaca->saved_gpr5); 1611 printf(" Saved Gpr5=%.16lx \n", ptrLpPaca->saved_gpr5);
1614
1615 printf(" Local Processor Register Save Area (LpRegSave): \n");
1616 ptrLpRegSave = ptrPaca->reg_save_ptr;
1617 printf(" Saved Sprg0=%.16lx Saved Sprg1=%.16lx \n",
1618 ptrLpRegSave->xSPRG0, ptrLpRegSave->xSPRG0);
1619 printf(" Saved Sprg2=%.16lx Saved Sprg3=%.16lx \n",
1620 ptrLpRegSave->xSPRG2, ptrLpRegSave->xSPRG3);
1621 printf(" Saved Msr =%.16lx Saved Nia =%.16lx \n",
1622 ptrLpRegSave->xMSR, ptrLpRegSave->xNIA);
1623 } 1612 }
1624#endif 1613#endif
1625 1614
diff --git a/include/asm-powerpc/iseries/it_lp_reg_save.h b/include/asm-powerpc/iseries/it_lp_reg_save.h
deleted file mode 100644
index 5403b756f654..000000000000
--- a/include/asm-powerpc/iseries/it_lp_reg_save.h
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18#ifndef _ASM_POWERPC_ISERIES_IT_LP_REG_SAVE_H
19#define _ASM_POWERPC_ISERIES_IT_LP_REG_SAVE_H
20
21/*
22 * This control block contains the data that is shared between PLIC
23 * and the OS
24 */
25
26struct ItLpRegSave {
27 u32 xDesc; // Eye catcher "LpRS" ebcdic 000-003
28 u16 xSize; // Size of this class 004-005
29 u8 xInUse; // Area is live 006-007
30 u8 xRsvd1[9]; // Reserved 007-00F
31
32 u8 xFixedRegSave[352]; // Fixed Register Save Area 010-16F
33 u32 xCTRL; // Control Register 170-173
34 u32 xDEC; // Decrementer 174-177
35 u32 xFPSCR; // FP Status and Control Reg 178-17B
36 u32 xPVR; // Processor Version Number 17C-17F
37
38 u64 xMMCR0; // Monitor Mode Control Reg 0 180-187
39 u32 xPMC1; // Perf Monitor Counter 1 188-18B
40 u32 xPMC2; // Perf Monitor Counter 2 18C-18F
41 u32 xPMC3; // Perf Monitor Counter 3 190-193
42 u32 xPMC4; // Perf Monitor Counter 4 194-197
43 u32 xPIR; // Processor ID Reg 198-19B
44
45 u32 xMMCR1; // Monitor Mode Control Reg 1 19C-19F
46 u32 xMMCRA; // Monitor Mode Control Reg A 1A0-1A3
47 u32 xPMC5; // Perf Monitor Counter 5 1A4-1A7
48 u32 xPMC6; // Perf Monitor Counter 6 1A8-1AB
49 u32 xPMC7; // Perf Monitor Counter 7 1AC-1AF
50 u32 xPMC8; // Perf Monitor Counter 8 1B0-1B3
51 u32 xTSC; // Thread Switch Control 1B4-1B7
52 u32 xTST; // Thread Switch Timeout 1B8-1BB
53 u32 xRsvd; // Reserved 1BC-1BF
54
55 u64 xACCR; // Address Compare Control Reg 1C0-1C7
56 u64 xIMR; // Instruction Match Register 1C8-1CF
57 u64 xSDR1; // Storage Description Reg 1 1D0-1D7
58 u64 xSPRG0; // Special Purpose Reg General0 1D8-1DF
59 u64 xSPRG1; // Special Purpose Reg General1 1E0-1E7
60 u64 xSPRG2; // Special Purpose Reg General2 1E8-1EF
61 u64 xSPRG3; // Special Purpose Reg General3 1F0-1F7
62 u64 xTB; // Time Base Register 1F8-1FF
63
64 u64 xFPR[32]; // Floating Point Registers 200-2FF
65
66 u64 xMSR; // Machine State Register 300-307
67 u64 xNIA; // Next Instruction Address 308-30F
68
69 u64 xDABR; // Data Address Breakpoint Reg 310-317
70 u64 xIABR; // Inst Address Breakpoint Reg 318-31F
71
72 u64 xHID0; // HW Implementation Dependent0 320-327
73
74 u64 xHID4; // HW Implementation Dependent4 328-32F
75 u64 xSCOMd; // SCON Data Reg (SPRG4) 330-337
76 u64 xSCOMc; // SCON Command Reg (SPRG5) 338-33F
77 u64 xSDAR; // Sample Data Address Register 340-347
78 u64 xSIAR; // Sample Inst Address Register 348-34F
79
80 u8 xRsvd3[176]; // Reserved 350-3FF
81};
82
83extern struct ItLpRegSave iseries_reg_save[];
84
85#endif /* _ASM_POWERPC_ISERIES_IT_LP_REG_SAVE_H */
diff --git a/include/asm-powerpc/paca.h b/include/asm-powerpc/paca.h
index 748b35ab37b5..eb61b9c1edfd 100644
--- a/include/asm-powerpc/paca.h
+++ b/include/asm-powerpc/paca.h
@@ -42,10 +42,7 @@ struct task_struct;
42 * Defines the layout of the paca. 42 * Defines the layout of the paca.
43 * 43 *
44 * This structure is not directly accessed by firmware or the service 44 * This structure is not directly accessed by firmware or the service
45 * processor except for the first two pointers that point to the 45 * processor.
46 * lppaca area and the ItLpRegSave area for this CPU. The lppaca
47 * object is currently contained within the PACA but it doesn't need
48 * to be.
49 */ 46 */
50struct paca_struct { 47struct paca_struct {
51 /* 48 /*
@@ -55,14 +52,7 @@ struct paca_struct {
55 * avoid cacheline bouncing. 52 * avoid cacheline bouncing.
56 */ 53 */
57 54
58 /*
59 * MAGIC: These first two pointers can't be moved - they're
60 * accessed by the firmware
61 */
62 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */ 55 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
63#ifdef CONFIG_PPC_ISERIES
64 void *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
65#endif /* CONFIG_PPC_ISERIES */
66 56
67 /* 57 /*
68 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c 58 * MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 07:31:23 -0500