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-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c73
1 files changed, 52 insertions, 21 deletions
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 0b71c896bbd1..1be2567a7486 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -89,32 +89,63 @@
89 89
90/* macros to modify the physical addresses for io space */ 90/* macros to modify the physical addresses for io space */
91 91
92#define PA_CS2(item) ((item) + S3C2410_CS2) 92#define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
93#define PA_CS3(item) ((item) + S3C2410_CS3) 93#define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
94#define PA_CS4(item) ((item) + S3C2410_CS4) 94#define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
95#define PA_CS5(item) ((item) + S3C2410_CS5) 95#define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
96 96
97static struct map_desc bast_iodesc[] __initdata = { 97static struct map_desc bast_iodesc[] __initdata = {
98 /* ISA IO areas */ 98 /* ISA IO areas */
99 99 {
100 { (u32)S3C24XX_VA_ISA_BYTE, PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, 100 .virtual = (u32)S3C24XX_VA_ISA_BYTE,
101 { (u32)S3C24XX_VA_ISA_WORD, PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, 101 .pfn = PA_CS2(BAST_PA_ISAIO),
102 102 .length = SZ_16M,
103 /* we could possibly compress the next set down into a set of smaller tables 103 .type = MT_DEVICE,
104 * pagetables, but that would mean using an L2 section, and it still means 104 }, {
105 * we cannot actually feed the same register to an LDR due to 16K spacing 105 .virtual = (u32)S3C24XX_VA_ISA_WORD,
106 */ 106 .pfn = PA_CS3(BAST_PA_ISAIO),
107 107 .length = SZ_16M,
108 .type = MT_DEVICE,
109 },
108 /* bast CPLD control registers, and external interrupt controls */ 110 /* bast CPLD control registers, and external interrupt controls */
109 { (u32)BAST_VA_CTRL1, BAST_PA_CTRL1, SZ_1M, MT_DEVICE }, 111 {
110 { (u32)BAST_VA_CTRL2, BAST_PA_CTRL2, SZ_1M, MT_DEVICE }, 112 .virtual = (u32)BAST_VA_CTRL1,
111 { (u32)BAST_VA_CTRL3, BAST_PA_CTRL3, SZ_1M, MT_DEVICE }, 113 .pfn = __phys_to_pfn(BAST_PA_CTRL1),
112 { (u32)BAST_VA_CTRL4, BAST_PA_CTRL4, SZ_1M, MT_DEVICE }, 114 .length = SZ_1M,
113 115 .type = MT_DEVICE,
116 }, {
117 .virtual = (u32)BAST_VA_CTRL2,
118 .pfn = __phys_to_pfn(BAST_PA_CTRL2),
119 .length = SZ_1M,
120 .type = MT_DEVICE,
121 }, {
122 .virtual = (u32)BAST_VA_CTRL3,
123 .pfn = __phys_to_pfn(BAST_PA_CTRL3),
124 .length = SZ_1M,
125 .type = MT_DEVICE,
126 }, {
127 .virtual = (u32)BAST_VA_CTRL4,
128 .pfn = __phys_to_pfn(BAST_PA_CTRL4),
129 .length = SZ_1M,
130 .type = MT_DEVICE,
131 },
114 /* PC104 IRQ mux */ 132 /* PC104 IRQ mux */
115 { (u32)BAST_VA_PC104_IRQREQ, BAST_PA_PC104_IRQREQ, SZ_1M, MT_DEVICE }, 133 {
116 { (u32)BAST_VA_PC104_IRQRAW, BAST_PA_PC104_IRQRAW, SZ_1M, MT_DEVICE }, 134 .virtual = (u32)BAST_VA_PC104_IRQREQ,
117 { (u32)BAST_VA_PC104_IRQMASK, BAST_PA_PC104_IRQMASK, SZ_1M, MT_DEVICE }, 135 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
136 .length = SZ_1M,
137 .type = MT_DEVICE,
138 }, {
139 .virtual = (u32)BAST_VA_PC104_IRQRAW,
140 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
141 .length = SZ_1M,
142 .type = MT_DEVICE,
143 }, {
144 .virtual = (u32)BAST_VA_PC104_IRQMASK,
145 .pfn = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
146 .length = SZ_1M,
147 .type = MT_DEVICE,
148 },
118 149
119 /* peripheral space... one for each of fast/slow/byte/16bit */ 150 /* peripheral space... one for each of fast/slow/byte/16bit */
120 /* note, ide is only decoded in word space, even though some registers 151 /* note, ide is only decoded in word space, even though some registers