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-rw-r--r--arch/sparc/kernel/process.c2
-rw-r--r--arch/sparc64/kernel/process.c2
-rw-r--r--include/asm-sparc/system.h2
-rw-r--r--include/asm-sparc64/system.h2
4 files changed, 4 insertions, 4 deletions
diff --git a/arch/sparc/kernel/process.c b/arch/sparc/kernel/process.c
index 0bd69d0b5cd7..70c0dd22491d 100644
--- a/arch/sparc/kernel/process.c
+++ b/arch/sparc/kernel/process.c
@@ -139,8 +139,6 @@ void cpu_idle(void)
139 139
140#endif 140#endif
141 141
142extern char reboot_command [];
143
144/* XXX cli/sti -> local_irq_xxx here, check this works once SMP is fixed. */ 142/* XXX cli/sti -> local_irq_xxx here, check this works once SMP is fixed. */
145void machine_halt(void) 143void machine_halt(void)
146{ 144{
diff --git a/arch/sparc64/kernel/process.c b/arch/sparc64/kernel/process.c
index 2aafce7dfc0e..e116e38b160e 100644
--- a/arch/sparc64/kernel/process.c
+++ b/arch/sparc64/kernel/process.c
@@ -114,8 +114,6 @@ void cpu_idle(void)
114 } 114 }
115} 115}
116 116
117extern char reboot_command [];
118
119void machine_halt(void) 117void machine_halt(void)
120{ 118{
121 sstate_halt(); 119 sstate_halt();
diff --git a/include/asm-sparc/system.h b/include/asm-sparc/system.h
index 45e47c159a6e..4e08210cd4c2 100644
--- a/include/asm-sparc/system.h
+++ b/include/asm-sparc/system.h
@@ -44,6 +44,8 @@ extern enum sparc_cpu sparc_cpu_model;
44 44
45#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */ 45#define SUN4M_NCPUS 4 /* Architectural limit of sun4m. */
46 46
47extern char reboot_command[];
48
47extern struct thread_info *current_set[NR_CPUS]; 49extern struct thread_info *current_set[NR_CPUS];
48 50
49extern unsigned long empty_bad_page; 51extern unsigned long empty_bad_page;
diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h
index ed91a5d8d4f0..53eae091a171 100644
--- a/include/asm-sparc64/system.h
+++ b/include/asm-sparc64/system.h
@@ -30,6 +30,8 @@ enum sparc_cpu {
30#define ARCH_SUN4C_SUN4 0 30#define ARCH_SUN4C_SUN4 0
31#define ARCH_SUN4 0 31#define ARCH_SUN4 0
32 32
33extern char reboot_command[];
34
33/* These are here in an effort to more fully work around Spitfire Errata 35/* These are here in an effort to more fully work around Spitfire Errata
34 * #51. Essentially, if a memory barrier occurs soon after a mispredicted 36 * #51. Essentially, if a memory barrier occurs soon after a mispredicted
35 * branch, the chip can stop executing instructions until a trap occurs. 37 * branch, the chip can stop executing instructions until a trap occurs.