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-rw-r--r--drivers/video/matrox/g450_pll.c23
-rw-r--r--drivers/video/matrox/matroxfb_DAC1064.h15
-rw-r--r--drivers/video/matrox/matroxfb_base.h1
-rw-r--r--drivers/video/matrox/matroxfb_misc.c1
4 files changed, 30 insertions, 10 deletions
diff --git a/drivers/video/matrox/g450_pll.c b/drivers/video/matrox/g450_pll.c
index 7c76e079ca7d..d42346e7fdda 100644
--- a/drivers/video/matrox/g450_pll.c
+++ b/drivers/video/matrox/g450_pll.c
@@ -331,16 +331,19 @@ static int __g450_setclk(WPMINFO unsigned int fout, unsigned int pll,
331 tmp |= M1064_XPIXCLKCTRL_PLL_UP; 331 tmp |= M1064_XPIXCLKCTRL_PLL_UP;
332 } 332 }
333 matroxfb_DAC_out(PMINFO M1064_XPIXCLKCTRL, tmp); 333 matroxfb_DAC_out(PMINFO M1064_XPIXCLKCTRL, tmp);
334#ifdef __powerpc__ 334 /* DVI PLL preferred for frequencies up to
335 /* This is necessary to avoid jitter on PowerPC 335 panel link max, standard PLL otherwise */
336 * (OpenFirmware) systems, but apparently 336 if (fout >= MINFO->max_pixel_clock_panellink)
337 * introduces jitter, at least on a x86-64 337 tmp = 0;
338 * using DVI. 338 else tmp =
339 * A simple workaround is disable for non-PPC. 339 M1064_XDVICLKCTRL_DVIDATAPATHSEL |
340 */ 340 M1064_XDVICLKCTRL_C1DVICLKSEL |
341 matroxfb_DAC_out(PMINFO M1064_XDVICLKCTRL, 0); 341 M1064_XDVICLKCTRL_C1DVICLKEN |
342#endif /* __powerpc__ */ 342 M1064_XDVICLKCTRL_DVILOOPCTL |
343 matroxfb_DAC_out(PMINFO M1064_XPWRCTRL, xpwrctrl); 343 M1064_XDVICLKCTRL_P1LOOPBWDTCTL;
344 matroxfb_DAC_out(PMINFO M1064_XDVICLKCTRL,tmp);
345 matroxfb_DAC_out(PMINFO M1064_XPWRCTRL,
346 xpwrctrl);
344 347
345 matroxfb_DAC_unlock_irqrestore(flags); 348 matroxfb_DAC_unlock_irqrestore(flags);
346 } 349 }
diff --git a/drivers/video/matrox/matroxfb_DAC1064.h b/drivers/video/matrox/matroxfb_DAC1064.h
index df39c3193735..7a98ce8043d7 100644
--- a/drivers/video/matrox/matroxfb_DAC1064.h
+++ b/drivers/video/matrox/matroxfb_DAC1064.h
@@ -33,6 +33,21 @@ void DAC1064_global_restore(WPMINFO2);
33#define M1064_XCURCTRL_3COLOR 0x01 /* transparent, 0, 1, 2 */ 33#define M1064_XCURCTRL_3COLOR 0x01 /* transparent, 0, 1, 2 */
34#define M1064_XCURCTRL_XGA 0x02 /* 0, 1, transparent, complement */ 34#define M1064_XCURCTRL_XGA 0x02 /* 0, 1, transparent, complement */
35#define M1064_XCURCTRL_XWIN 0x03 /* transparent, transparent, 0, 1 */ 35#define M1064_XCURCTRL_XWIN 0x03 /* transparent, transparent, 0, 1 */
36 /* drive DVI by standard(0)/DVI(1) PLL */
37 /* if set(1), C?DVICLKEN and C?DVICLKSEL must be set(1) */
38#define M1064_XDVICLKCTRL_DVIDATAPATHSEL 0x01
39 /* drive CRTC1 by standard(0)/DVI(1) PLL */
40#define M1064_XDVICLKCTRL_C1DVICLKSEL 0x02
41 /* drive CRTC2 by standard(0)/DVI(1) PLL */
42#define M1064_XDVICLKCTRL_C2DVICLKSEL 0x04
43 /* pixel clock allowed to(0)/blocked from(1) driving CRTC1 */
44#define M1064_XDVICLKCTRL_C1DVICLKEN 0x08
45 /* DVI PLL loop filter bandwidth selection bits */
46#define M1064_XDVICLKCTRL_DVILOOPCTL 0x30
47 /* CRTC2 pixel clock allowed to(0)/blocked from(1) driving CRTC2 */
48#define M1064_XDVICLKCTRL_C2DVICLKEN 0x40
49 /* P1PLL loop filter bandwith selection */
50#define M1064_XDVICLKCTRL_P1LOOPBWDTCTL 0x80
36#define M1064_XCURCOL0RED 0x08 51#define M1064_XCURCOL0RED 0x08
37#define M1064_XCURCOL0GREEN 0x09 52#define M1064_XCURCOL0GREEN 0x09
38#define M1064_XCURCOL0BLUE 0x0A 53#define M1064_XCURCOL0BLUE 0x0A
diff --git a/drivers/video/matrox/matroxfb_base.h b/drivers/video/matrox/matroxfb_base.h
index d59577c8de86..f3107ad7e545 100644
--- a/drivers/video/matrox/matroxfb_base.h
+++ b/drivers/video/matrox/matroxfb_base.h
@@ -424,6 +424,7 @@ struct matrox_fb_info {
424 } mmio; 424 } mmio;
425 425
426 unsigned int max_pixel_clock; 426 unsigned int max_pixel_clock;
427 unsigned int max_pixel_clock_panellink;
427 428
428 struct matrox_switch* hw_switch; 429 struct matrox_switch* hw_switch;
429 430
diff --git a/drivers/video/matrox/matroxfb_misc.c b/drivers/video/matrox/matroxfb_misc.c
index 5948e54b9ef9..ab7fb50bc1de 100644
--- a/drivers/video/matrox/matroxfb_misc.c
+++ b/drivers/video/matrox/matroxfb_misc.c
@@ -658,6 +658,7 @@ static int parse_pins5(WPMINFO const struct matrox_bios* bd) {
658 MINFO->values.reg.mctlwtst_core = (MINFO->values.reg.mctlwtst & ~7) | 658 MINFO->values.reg.mctlwtst_core = (MINFO->values.reg.mctlwtst & ~7) |
659 wtst_xlat[MINFO->values.reg.mctlwtst & 7]; 659 wtst_xlat[MINFO->values.reg.mctlwtst & 7];
660 } 660 }
661 MINFO->max_pixel_clock_panellink = bd->pins[47] * 4000;
661 return 0; 662 return 0;
662} 663}
663 664