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-rw-r--r--arch/arm/mach-iop32x/irq.c6
-rw-r--r--arch/arm/mach-iop33x/irq.c10
-rw-r--r--include/asm-arm/arch-iop32x/entry-macro.S1
-rw-r--r--include/asm-arm/arch-iop32x/irqs.h68
-rw-r--r--include/asm-arm/arch-iop33x/entry-macro.S1
-rw-r--r--include/asm-arm/arch-iop33x/irqs.h110
6 files changed, 76 insertions, 120 deletions
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index cdd6943ce768..ff049e02f5f7 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -43,7 +43,7 @@ static void
43iop321_irq_mask (unsigned int irq) 43iop321_irq_mask (unsigned int irq)
44{ 44{
45 45
46 iop321_mask &= ~(1 << (irq - IOP321_IRQ_OFS)); 46 iop321_mask &= ~(1 << irq);
47 47
48 intctl_write(iop321_mask); 48 intctl_write(iop321_mask);
49} 49}
@@ -51,7 +51,7 @@ iop321_irq_mask (unsigned int irq)
51static void 51static void
52iop321_irq_unmask (unsigned int irq) 52iop321_irq_unmask (unsigned int irq)
53{ 53{
54 iop321_mask |= (1 << (irq - IOP321_IRQ_OFS)); 54 iop321_mask |= (1 << irq);
55 55
56 intctl_write(iop321_mask); 56 intctl_write(iop321_mask);
57} 57}
@@ -73,7 +73,7 @@ void __init iop321_init_irq(void)
73 machine_is_iq31244()) // all interrupts are inputs to chip 73 machine_is_iq31244()) // all interrupts are inputs to chip
74 *IOP3XX_PCIIRSR = 0x0f; 74 *IOP3XX_PCIIRSR = 0x0f;
75 75
76 for(i = IOP321_IRQ_OFS; i < NR_IRQS; i++) 76 for(i = 0; i < NR_IRQS; i++)
77 { 77 {
78 set_irq_chip(i, &ext_chip); 78 set_irq_chip(i, &ext_chip);
79 set_irq_handler(i, do_level_IRQ); 79 set_irq_handler(i, do_level_IRQ);
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index d667439c8573..675ed3989973 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -60,28 +60,28 @@ static inline void intstr_write1(u32 val)
60static void 60static void
61iop331_irq_mask1 (unsigned int irq) 61iop331_irq_mask1 (unsigned int irq)
62{ 62{
63 iop331_mask0 &= ~(1 << (irq - IOP331_IRQ_OFS)); 63 iop331_mask0 &= ~(1 << irq);
64 intctl_write0(iop331_mask0); 64 intctl_write0(iop331_mask0);
65} 65}
66 66
67static void 67static void
68iop331_irq_mask2 (unsigned int irq) 68iop331_irq_mask2 (unsigned int irq)
69{ 69{
70 iop331_mask1 &= ~(1 << (irq - IOP331_IRQ_OFS - 32)); 70 iop331_mask1 &= ~(1 << (irq - 32));
71 intctl_write1(iop331_mask1); 71 intctl_write1(iop331_mask1);
72} 72}
73 73
74static void 74static void
75iop331_irq_unmask1(unsigned int irq) 75iop331_irq_unmask1(unsigned int irq)
76{ 76{
77 iop331_mask0 |= (1 << (irq - IOP331_IRQ_OFS)); 77 iop331_mask0 |= (1 << irq);
78 intctl_write0(iop331_mask0); 78 intctl_write0(iop331_mask0);
79} 79}
80 80
81static void 81static void
82iop331_irq_unmask2(unsigned int irq) 82iop331_irq_unmask2(unsigned int irq)
83{ 83{
84 iop331_mask1 |= (1 << (irq - IOP331_IRQ_OFS - 32)); 84 iop331_mask1 |= (1 << (irq - 32));
85 intctl_write1(iop331_mask1); 85 intctl_write1(iop331_mask1);
86} 86}
87 87
@@ -110,7 +110,7 @@ void __init iop331_init_irq(void)
110 if(machine_is_iq80331()) // all interrupts are inputs to chip 110 if(machine_is_iq80331()) // all interrupts are inputs to chip
111 *IOP3XX_PCIIRSR = 0x0f; 111 *IOP3XX_PCIIRSR = 0x0f;
112 112
113 for(i = IOP331_IRQ_OFS; i < NR_IRQS; i++) 113 for(i = 0; i < NR_IRQS; i++)
114 { 114 {
115 set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2); 115 set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2);
116 set_irq_handler(i, do_level_IRQ); 116 set_irq_handler(i, do_level_IRQ);
diff --git a/include/asm-arm/arch-iop32x/entry-macro.S b/include/asm-arm/arch-iop32x/entry-macro.S
index 00038c17317a..c5ec1e23cbea 100644
--- a/include/asm-arm/arch-iop32x/entry-macro.S
+++ b/include/asm-arm/arch-iop32x/entry-macro.S
@@ -24,6 +24,5 @@
24 clz \irqnr, \irqstat 24 clz \irqnr, \irqstat
25 mov \base, #31 25 mov \base, #31
26 subs \irqnr,\base,\irqnr 26 subs \irqnr,\base,\irqnr
27 add \irqnr,\irqnr,#IRQ_IOP321_DMA0_EOT
281001: 271001:
29 .endm 28 .endm
diff --git a/include/asm-arm/arch-iop32x/irqs.h b/include/asm-arm/arch-iop32x/irqs.h
index 4b0c82711f96..9fefcf3372b1 100644
--- a/include/asm-arm/arch-iop32x/irqs.h
+++ b/include/asm-arm/arch-iop32x/irqs.h
@@ -15,46 +15,36 @@
15/* 15/*
16 * IOP80321 chipset interrupts 16 * IOP80321 chipset interrupts
17 */ 17 */
18#define IOP321_IRQ_OFS 0 18#define IRQ_IOP321_DMA0_EOT 0
19#define IOP321_IRQ(x) (IOP321_IRQ_OFS + (x)) 19#define IRQ_IOP321_DMA0_EOC 1
20#define IRQ_IOP321_DMA1_EOT 2
21#define IRQ_IOP321_DMA1_EOC 3
22#define IRQ_IOP321_AA_EOT 6
23#define IRQ_IOP321_AA_EOC 7
24#define IRQ_IOP321_CORE_PMON 8
25#define IRQ_IOP321_TIMER0 9
26#define IRQ_IOP321_TIMER1 10
27#define IRQ_IOP321_I2C_0 11
28#define IRQ_IOP321_I2C_1 12
29#define IRQ_IOP321_MESSAGING 13
30#define IRQ_IOP321_ATU_BIST 14
31#define IRQ_IOP321_PERFMON 15
32#define IRQ_IOP321_CORE_PMU 16
33#define IRQ_IOP321_BIU_ERR 17
34#define IRQ_IOP321_ATU_ERR 18
35#define IRQ_IOP321_MCU_ERR 19
36#define IRQ_IOP321_DMA0_ERR 20
37#define IRQ_IOP321_DMA1_ERR 21
38#define IRQ_IOP321_AA_ERR 23
39#define IRQ_IOP321_MSG_ERR 24
40#define IRQ_IOP321_SSP 25
41#define IRQ_IOP321_XINT0 27
42#define IRQ_IOP321_XINT1 28
43#define IRQ_IOP321_XINT2 29
44#define IRQ_IOP321_XINT3 30
45#define IRQ_IOP321_HPI 31
20 46
21/* 47#define NR_IRQS 32
22 * On IRQ or FIQ register
23 */
24#define IRQ_IOP321_DMA0_EOT IOP321_IRQ(0)
25#define IRQ_IOP321_DMA0_EOC IOP321_IRQ(1)
26#define IRQ_IOP321_DMA1_EOT IOP321_IRQ(2)
27#define IRQ_IOP321_DMA1_EOC IOP321_IRQ(3)
28#define IRQ_IOP321_RSVD_4 IOP321_IRQ(4)
29#define IRQ_IOP321_RSVD_5 IOP321_IRQ(5)
30#define IRQ_IOP321_AA_EOT IOP321_IRQ(6)
31#define IRQ_IOP321_AA_EOC IOP321_IRQ(7)
32#define IRQ_IOP321_CORE_PMON IOP321_IRQ(8)
33#define IRQ_IOP321_TIMER0 IOP321_IRQ(9)
34#define IRQ_IOP321_TIMER1 IOP321_IRQ(10)
35#define IRQ_IOP321_I2C_0 IOP321_IRQ(11)
36#define IRQ_IOP321_I2C_1 IOP321_IRQ(12)
37#define IRQ_IOP321_MESSAGING IOP321_IRQ(13)
38#define IRQ_IOP321_ATU_BIST IOP321_IRQ(14)
39#define IRQ_IOP321_PERFMON IOP321_IRQ(15)
40#define IRQ_IOP321_CORE_PMU IOP321_IRQ(16)
41#define IRQ_IOP321_BIU_ERR IOP321_IRQ(17)
42#define IRQ_IOP321_ATU_ERR IOP321_IRQ(18)
43#define IRQ_IOP321_MCU_ERR IOP321_IRQ(19)
44#define IRQ_IOP321_DMA0_ERR IOP321_IRQ(20)
45#define IRQ_IOP321_DMA1_ERR IOP321_IRQ(21)
46#define IRQ_IOP321_RSVD_22 IOP321_IRQ(22)
47#define IRQ_IOP321_AA_ERR IOP321_IRQ(23)
48#define IRQ_IOP321_MSG_ERR IOP321_IRQ(24)
49#define IRQ_IOP321_SSP IOP321_IRQ(25)
50#define IRQ_IOP321_RSVD_26 IOP321_IRQ(26)
51#define IRQ_IOP321_XINT0 IOP321_IRQ(27)
52#define IRQ_IOP321_XINT1 IOP321_IRQ(28)
53#define IRQ_IOP321_XINT2 IOP321_IRQ(29)
54#define IRQ_IOP321_XINT3 IOP321_IRQ(30)
55#define IRQ_IOP321_HPI IOP321_IRQ(31)
56
57#define NR_IRQS (IOP321_IRQ(31) + 1)
58 48
59 49
60/* 50/*
diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S
index 57f6ea0069e4..425aa7aafa0e 100644
--- a/include/asm-arm/arch-iop33x/entry-macro.S
+++ b/include/asm-arm/arch-iop33x/entry-macro.S
@@ -30,6 +30,5 @@
30 b 1001f 30 b 1001f
311002: clz \irqnr, \irqstat 311002: clz \irqnr, \irqstat
32 rsbs \irqnr,\irqnr,#31 @ recommend by RMK 32 rsbs \irqnr,\irqnr,#31 @ recommend by RMK
33 add \irqnr,\irqnr,#IRQ_IOP331_DMA0_EOT
341001: 331001:
35 .endm 34 .endm
diff --git a/include/asm-arm/arch-iop33x/irqs.h b/include/asm-arm/arch-iop33x/irqs.h
index 45856a12815a..2e3ade3b5ff9 100644
--- a/include/asm-arm/arch-iop33x/irqs.h
+++ b/include/asm-arm/arch-iop33x/irqs.h
@@ -15,78 +15,46 @@
15/* 15/*
16 * IOP80331 chipset interrupts 16 * IOP80331 chipset interrupts
17 */ 17 */
18#define IOP331_IRQ_OFS 0 18#define IRQ_IOP331_DMA0_EOT 0
19#define IOP331_IRQ(x) (IOP331_IRQ_OFS + (x)) 19#define IRQ_IOP331_DMA0_EOC 1
20#define IRQ_IOP331_DMA1_EOT 2
21#define IRQ_IOP331_DMA1_EOC 3
22#define IRQ_IOP331_AA_EOT 6
23#define IRQ_IOP331_AA_EOC 7
24#define IRQ_IOP331_TIMER0 8
25#define IRQ_IOP331_TIMER1 9
26#define IRQ_IOP331_I2C_0 10
27#define IRQ_IOP331_I2C_1 11
28#define IRQ_IOP331_MSG 12
29#define IRQ_IOP331_MSGIBQ 13
30#define IRQ_IOP331_ATU_BIST 14
31#define IRQ_IOP331_PERFMON 15
32#define IRQ_IOP331_CORE_PMU 16
33#define IRQ_IOP331_XINT0 24
34#define IRQ_IOP331_XINT1 25
35#define IRQ_IOP331_XINT2 26
36#define IRQ_IOP331_XINT3 27
37#define IRQ_IOP331_XINT8 32
38#define IRQ_IOP331_XINT9 33
39#define IRQ_IOP331_XINT10 34
40#define IRQ_IOP331_XINT11 35
41#define IRQ_IOP331_XINT12 36
42#define IRQ_IOP331_XINT13 37
43#define IRQ_IOP331_XINT14 38
44#define IRQ_IOP331_XINT15 39
45#define IRQ_IOP331_UART0 51
46#define IRQ_IOP331_UART1 52
47#define IRQ_IOP331_PBIE 53
48#define IRQ_IOP331_ATU_CRW 54
49#define IRQ_IOP331_ATU_ERR 55
50#define IRQ_IOP331_MCU_ERR 56
51#define IRQ_IOP331_DMA0_ERR 57
52#define IRQ_IOP331_DMA1_ERR 58
53#define IRQ_IOP331_AA_ERR 60
54#define IRQ_IOP331_MSG_ERR 62
55#define IRQ_IOP331_HPI 63
20 56
21/* 57#define NR_IRQS 64
22 * On IRQ or FIQ register
23 */
24#define IRQ_IOP331_DMA0_EOT IOP331_IRQ(0)
25#define IRQ_IOP331_DMA0_EOC IOP331_IRQ(1)
26#define IRQ_IOP331_DMA1_EOT IOP331_IRQ(2)
27#define IRQ_IOP331_DMA1_EOC IOP331_IRQ(3)
28#define IRQ_IOP331_RSVD_4 IOP331_IRQ(4)
29#define IRQ_IOP331_RSVD_5 IOP331_IRQ(5)
30#define IRQ_IOP331_AA_EOT IOP331_IRQ(6)
31#define IRQ_IOP331_AA_EOC IOP331_IRQ(7)
32#define IRQ_IOP331_TIMER0 IOP331_IRQ(8)
33#define IRQ_IOP331_TIMER1 IOP331_IRQ(9)
34#define IRQ_IOP331_I2C_0 IOP331_IRQ(10)
35#define IRQ_IOP331_I2C_1 IOP331_IRQ(11)
36#define IRQ_IOP331_MSG IOP331_IRQ(12)
37#define IRQ_IOP331_MSGIBQ IOP331_IRQ(13)
38#define IRQ_IOP331_ATU_BIST IOP331_IRQ(14)
39#define IRQ_IOP331_PERFMON IOP331_IRQ(15)
40#define IRQ_IOP331_CORE_PMU IOP331_IRQ(16)
41#define IRQ_IOP331_RSVD_17 IOP331_IRQ(17)
42#define IRQ_IOP331_RSVD_18 IOP331_IRQ(18)
43#define IRQ_IOP331_RSVD_19 IOP331_IRQ(19)
44#define IRQ_IOP331_RSVD_20 IOP331_IRQ(20)
45#define IRQ_IOP331_RSVD_21 IOP331_IRQ(21)
46#define IRQ_IOP331_RSVD_22 IOP331_IRQ(22)
47#define IRQ_IOP331_RSVD_23 IOP331_IRQ(23)
48#define IRQ_IOP331_XINT0 IOP331_IRQ(24)
49#define IRQ_IOP331_XINT1 IOP331_IRQ(25)
50#define IRQ_IOP331_XINT2 IOP331_IRQ(26)
51#define IRQ_IOP331_XINT3 IOP331_IRQ(27)
52#define IRQ_IOP331_RSVD_28 IOP331_IRQ(28)
53#define IRQ_IOP331_RSVD_29 IOP331_IRQ(29)
54#define IRQ_IOP331_RSVD_30 IOP331_IRQ(30)
55#define IRQ_IOP331_RSVD_31 IOP331_IRQ(31)
56#define IRQ_IOP331_XINT8 IOP331_IRQ(32) // 0
57#define IRQ_IOP331_XINT9 IOP331_IRQ(33) // 1
58#define IRQ_IOP331_XINT10 IOP331_IRQ(34) // 2
59#define IRQ_IOP331_XINT11 IOP331_IRQ(35) // 3
60#define IRQ_IOP331_XINT12 IOP331_IRQ(36) // 4
61#define IRQ_IOP331_XINT13 IOP331_IRQ(37) // 5
62#define IRQ_IOP331_XINT14 IOP331_IRQ(38) // 6
63#define IRQ_IOP331_XINT15 IOP331_IRQ(39) // 7
64#define IRQ_IOP331_RSVD_40 IOP331_IRQ(40) // 8
65#define IRQ_IOP331_RSVD_41 IOP331_IRQ(41) // 9
66#define IRQ_IOP331_RSVD_42 IOP331_IRQ(42) // 10
67#define IRQ_IOP331_RSVD_43 IOP331_IRQ(43) // 11
68#define IRQ_IOP331_RSVD_44 IOP331_IRQ(44) // 12
69#define IRQ_IOP331_RSVD_45 IOP331_IRQ(45) // 13
70#define IRQ_IOP331_RSVD_46 IOP331_IRQ(46) // 14
71#define IRQ_IOP331_RSVD_47 IOP331_IRQ(47) // 15
72#define IRQ_IOP331_RSVD_48 IOP331_IRQ(48) // 16
73#define IRQ_IOP331_RSVD_49 IOP331_IRQ(49) // 17
74#define IRQ_IOP331_RSVD_50 IOP331_IRQ(50) // 18
75#define IRQ_IOP331_UART0 IOP331_IRQ(51) // 19
76#define IRQ_IOP331_UART1 IOP331_IRQ(52) // 20
77#define IRQ_IOP331_PBIE IOP331_IRQ(53) // 21
78#define IRQ_IOP331_ATU_CRW IOP331_IRQ(54) // 22
79#define IRQ_IOP331_ATU_ERR IOP331_IRQ(55) // 23
80#define IRQ_IOP331_MCU_ERR IOP331_IRQ(56) // 24
81#define IRQ_IOP331_DMA0_ERR IOP331_IRQ(57) // 25
82#define IRQ_IOP331_DMA1_ERR IOP331_IRQ(58) // 26
83#define IRQ_IOP331_RSVD_59 IOP331_IRQ(59) // 27
84#define IRQ_IOP331_AA_ERR IOP331_IRQ(60) // 28
85#define IRQ_IOP331_RSVD_61 IOP331_IRQ(61) // 29
86#define IRQ_IOP331_MSG_ERR IOP331_IRQ(62) // 30
87#define IRQ_IOP331_HPI IOP331_IRQ(63) // 31
88
89#define NR_IRQS (IOP331_IRQ(63) + 1)
90 58
91 59
92/* 60/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 14:12:25 -0500