diff options
-rw-r--r-- | drivers/char/drm/i915_dma.c | 4 | ||||
-rw-r--r-- | drivers/char/drm/i915_drm.h | 13 | ||||
-rw-r--r-- | drivers/char/drm/i915_drv.h | 6 | ||||
-rw-r--r-- | drivers/char/drm/i915_irq.c | 69 | ||||
-rw-r--r-- | drivers/char/drm/radeon_cp.c | 6 | ||||
-rw-r--r-- | drivers/char/drm/radeon_drm.h | 7 | ||||
-rw-r--r-- | drivers/char/drm/radeon_drv.h | 10 | ||||
-rw-r--r-- | drivers/char/drm/radeon_state.c | 39 |
8 files changed, 142 insertions, 12 deletions
diff --git a/drivers/char/drm/i915_dma.c b/drivers/char/drm/i915_dma.c index 9f4b8ce4c05e..a94233bdbc0e 100644 --- a/drivers/char/drm/i915_dma.c +++ b/drivers/char/drm/i915_dma.c | |||
@@ -758,7 +758,9 @@ drm_ioctl_desc_t i915_ioctls[] = { | |||
758 | [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH}, | 758 | [DRM_IOCTL_NR(DRM_I915_FREE)] = {i915_mem_free, DRM_AUTH}, |
759 | [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, | 759 | [DRM_IOCTL_NR(DRM_I915_INIT_HEAP)] = {i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY}, |
760 | [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH}, | 760 | [DRM_IOCTL_NR(DRM_I915_CMDBUFFER)] = {i915_cmdbuffer, DRM_AUTH}, |
761 | [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY } | 761 | [DRM_IOCTL_NR(DRM_I915_DESTROY_HEAP)] = { i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY }, |
762 | [DRM_IOCTL_NR(DRM_I915_SET_VBLANK_PIPE)] = { i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY }, | ||
763 | [DRM_IOCTL_NR(DRM_I915_GET_VBLANK_PIPE)] = { i915_vblank_pipe_get, DRM_AUTH }, | ||
762 | }; | 764 | }; |
763 | 765 | ||
764 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); | 766 | int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); |
diff --git a/drivers/char/drm/i915_drm.h b/drivers/char/drm/i915_drm.h index 4cb3da578330..5aa3e0e3bb45 100644 --- a/drivers/char/drm/i915_drm.h +++ b/drivers/char/drm/i915_drm.h | |||
@@ -124,6 +124,8 @@ typedef struct _drm_i915_sarea { | |||
124 | #define DRM_I915_INIT_HEAP 0x0a | 124 | #define DRM_I915_INIT_HEAP 0x0a |
125 | #define DRM_I915_CMDBUFFER 0x0b | 125 | #define DRM_I915_CMDBUFFER 0x0b |
126 | #define DRM_I915_DESTROY_HEAP 0x0c | 126 | #define DRM_I915_DESTROY_HEAP 0x0c |
127 | #define DRM_I915_SET_VBLANK_PIPE 0x0d | ||
128 | #define DRM_I915_GET_VBLANK_PIPE 0x0e | ||
127 | 129 | ||
128 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) | 130 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) |
129 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) | 131 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) |
@@ -138,6 +140,8 @@ typedef struct _drm_i915_sarea { | |||
138 | #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) | 140 | #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) |
139 | #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) | 141 | #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) |
140 | #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) | 142 | #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) |
143 | #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) | ||
144 | #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) | ||
141 | 145 | ||
142 | /* Allow drivers to submit batchbuffers directly to hardware, relying | 146 | /* Allow drivers to submit batchbuffers directly to hardware, relying |
143 | * on the security mechanisms provided by hardware. | 147 | * on the security mechanisms provided by hardware. |
@@ -224,4 +228,13 @@ typedef struct drm_i915_mem_destroy_heap { | |||
224 | int region; | 228 | int region; |
225 | } drm_i915_mem_destroy_heap_t; | 229 | } drm_i915_mem_destroy_heap_t; |
226 | 230 | ||
231 | /* Allow X server to configure which pipes to monitor for vblank signals | ||
232 | */ | ||
233 | #define DRM_I915_VBLANK_PIPE_A 1 | ||
234 | #define DRM_I915_VBLANK_PIPE_B 2 | ||
235 | |||
236 | typedef struct drm_i915_vblank_pipe { | ||
237 | int pipe; | ||
238 | } drm_i915_vblank_pipe_t; | ||
239 | |||
227 | #endif /* _I915_DRM_H_ */ | 240 | #endif /* _I915_DRM_H_ */ |
diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h index 7a65666899e4..2d565031c002 100644 --- a/drivers/char/drm/i915_drv.h +++ b/drivers/char/drm/i915_drv.h | |||
@@ -45,9 +45,10 @@ | |||
45 | * 1.2: Add Power Management | 45 | * 1.2: Add Power Management |
46 | * 1.3: Add vblank support | 46 | * 1.3: Add vblank support |
47 | * 1.4: Fix cmdbuffer path, add heap destroy | 47 | * 1.4: Fix cmdbuffer path, add heap destroy |
48 | * 1.5: Add vblank pipe configuration | ||
48 | */ | 49 | */ |
49 | #define DRIVER_MAJOR 1 | 50 | #define DRIVER_MAJOR 1 |
50 | #define DRIVER_MINOR 4 | 51 | #define DRIVER_MINOR 5 |
51 | #define DRIVER_PATCHLEVEL 0 | 52 | #define DRIVER_PATCHLEVEL 0 |
52 | 53 | ||
53 | typedef struct _drm_i915_ring_buffer { | 54 | typedef struct _drm_i915_ring_buffer { |
@@ -96,6 +97,7 @@ typedef struct drm_i915_private { | |||
96 | int allow_batchbuffer; | 97 | int allow_batchbuffer; |
97 | struct mem_block *agp_heap; | 98 | struct mem_block *agp_heap; |
98 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; | 99 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
100 | int vblank_pipe; | ||
99 | } drm_i915_private_t; | 101 | } drm_i915_private_t; |
100 | 102 | ||
101 | extern drm_ioctl_desc_t i915_ioctls[]; | 103 | extern drm_ioctl_desc_t i915_ioctls[]; |
@@ -119,6 +121,8 @@ extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); | |||
119 | extern void i915_driver_irq_preinstall(drm_device_t * dev); | 121 | extern void i915_driver_irq_preinstall(drm_device_t * dev); |
120 | extern void i915_driver_irq_postinstall(drm_device_t * dev); | 122 | extern void i915_driver_irq_postinstall(drm_device_t * dev); |
121 | extern void i915_driver_irq_uninstall(drm_device_t * dev); | 123 | extern void i915_driver_irq_uninstall(drm_device_t * dev); |
124 | extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS); | ||
125 | extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS); | ||
122 | 126 | ||
123 | /* i915_mem.c */ | 127 | /* i915_mem.c */ |
124 | extern int i915_mem_alloc(DRM_IOCTL_ARGS); | 128 | extern int i915_mem_alloc(DRM_IOCTL_ARGS); |
diff --git a/drivers/char/drm/i915_irq.c b/drivers/char/drm/i915_irq.c index a752afd86ab8..cd96cfa430db 100644 --- a/drivers/char/drm/i915_irq.c +++ b/drivers/char/drm/i915_irq.c | |||
@@ -44,7 +44,8 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) | |||
44 | u16 temp; | 44 | u16 temp; |
45 | 45 | ||
46 | temp = I915_READ16(I915REG_INT_IDENTITY_R); | 46 | temp = I915_READ16(I915REG_INT_IDENTITY_R); |
47 | temp &= (USER_INT_FLAG | VSYNC_PIPEA_FLAG); | 47 | |
48 | temp &= (USER_INT_FLAG | VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG); | ||
48 | 49 | ||
49 | DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp); | 50 | DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp); |
50 | 51 | ||
@@ -58,7 +59,7 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) | |||
58 | if (temp & USER_INT_FLAG) | 59 | if (temp & USER_INT_FLAG) |
59 | DRM_WAKEUP(&dev_priv->irq_queue); | 60 | DRM_WAKEUP(&dev_priv->irq_queue); |
60 | 61 | ||
61 | if (temp & VSYNC_PIPEA_FLAG) { | 62 | if (temp & (VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG)) { |
62 | atomic_inc(&dev->vbl_received); | 63 | atomic_inc(&dev->vbl_received); |
63 | DRM_WAKEUP(&dev->vbl_queue); | 64 | DRM_WAKEUP(&dev->vbl_queue); |
64 | drm_vbl_send_signals(dev); | 65 | drm_vbl_send_signals(dev); |
@@ -182,6 +183,68 @@ int i915_irq_wait(DRM_IOCTL_ARGS) | |||
182 | return i915_wait_irq(dev, irqwait.irq_seq); | 183 | return i915_wait_irq(dev, irqwait.irq_seq); |
183 | } | 184 | } |
184 | 185 | ||
186 | static int i915_enable_interrupt (drm_device_t *dev) | ||
187 | { | ||
188 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | ||
189 | u16 flag; | ||
190 | |||
191 | flag = 0; | ||
192 | if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A) | ||
193 | flag |= VSYNC_PIPEA_FLAG; | ||
194 | if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B) | ||
195 | flag |= VSYNC_PIPEB_FLAG; | ||
196 | if (dev_priv->vblank_pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) { | ||
197 | DRM_ERROR("%s called with invalid pipe 0x%x\n", | ||
198 | __FUNCTION__, dev_priv->vblank_pipe); | ||
199 | return DRM_ERR(EINVAL); | ||
200 | } | ||
201 | I915_WRITE16(I915REG_INT_ENABLE_R, USER_INT_FLAG | flag); | ||
202 | return 0; | ||
203 | } | ||
204 | |||
205 | /* Set the vblank monitor pipe | ||
206 | */ | ||
207 | int i915_vblank_pipe_set(DRM_IOCTL_ARGS) | ||
208 | { | ||
209 | DRM_DEVICE; | ||
210 | drm_i915_private_t *dev_priv = dev->dev_private; | ||
211 | drm_i915_vblank_pipe_t pipe; | ||
212 | |||
213 | if (!dev_priv) { | ||
214 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); | ||
215 | return DRM_ERR(EINVAL); | ||
216 | } | ||
217 | |||
218 | DRM_COPY_FROM_USER_IOCTL(pipe, (drm_i915_vblank_pipe_t __user *) data, | ||
219 | sizeof(pipe)); | ||
220 | |||
221 | dev_priv->vblank_pipe = pipe.pipe; | ||
222 | return i915_enable_interrupt (dev); | ||
223 | } | ||
224 | |||
225 | int i915_vblank_pipe_get(DRM_IOCTL_ARGS) | ||
226 | { | ||
227 | DRM_DEVICE; | ||
228 | drm_i915_private_t *dev_priv = dev->dev_private; | ||
229 | drm_i915_vblank_pipe_t pipe; | ||
230 | u16 flag; | ||
231 | |||
232 | if (!dev_priv) { | ||
233 | DRM_ERROR("%s called with no initialization\n", __FUNCTION__); | ||
234 | return DRM_ERR(EINVAL); | ||
235 | } | ||
236 | |||
237 | flag = I915_READ(I915REG_INT_ENABLE_R); | ||
238 | pipe.pipe = 0; | ||
239 | if (flag & VSYNC_PIPEA_FLAG) | ||
240 | pipe.pipe |= DRM_I915_VBLANK_PIPE_A; | ||
241 | if (flag & VSYNC_PIPEB_FLAG) | ||
242 | pipe.pipe |= DRM_I915_VBLANK_PIPE_B; | ||
243 | DRM_COPY_TO_USER_IOCTL((drm_i915_vblank_pipe_t __user *) data, pipe, | ||
244 | sizeof(pipe)); | ||
245 | return 0; | ||
246 | } | ||
247 | |||
185 | /* drm_dma.h hooks | 248 | /* drm_dma.h hooks |
186 | */ | 249 | */ |
187 | void i915_driver_irq_preinstall(drm_device_t * dev) | 250 | void i915_driver_irq_preinstall(drm_device_t * dev) |
@@ -197,7 +260,7 @@ void i915_driver_irq_postinstall(drm_device_t * dev) | |||
197 | { | 260 | { |
198 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | 261 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
199 | 262 | ||
200 | I915_WRITE16(I915REG_INT_ENABLE_R, USER_INT_FLAG | VSYNC_PIPEA_FLAG); | 263 | i915_enable_interrupt(dev); |
201 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); | 264 | DRM_INIT_WAITQUEUE(&dev_priv->irq_queue); |
202 | } | 265 | } |
203 | 266 | ||
diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c index 7f949c9c9691..5ad43ba7b5aa 100644 --- a/drivers/char/drm/radeon_cp.c +++ b/drivers/char/drm/radeon_cp.c | |||
@@ -39,7 +39,7 @@ | |||
39 | static int radeon_do_cleanup_cp(drm_device_t * dev); | 39 | static int radeon_do_cleanup_cp(drm_device_t * dev); |
40 | 40 | ||
41 | /* CP microcode (from ATI) */ | 41 | /* CP microcode (from ATI) */ |
42 | static u32 R200_cp_microcode[][2] = { | 42 | static const u32 R200_cp_microcode[][2] = { |
43 | {0x21007000, 0000000000}, | 43 | {0x21007000, 0000000000}, |
44 | {0x20007000, 0000000000}, | 44 | {0x20007000, 0000000000}, |
45 | {0x000000ab, 0x00000004}, | 45 | {0x000000ab, 0x00000004}, |
@@ -298,7 +298,7 @@ static u32 R200_cp_microcode[][2] = { | |||
298 | {0000000000, 0000000000}, | 298 | {0000000000, 0000000000}, |
299 | }; | 299 | }; |
300 | 300 | ||
301 | static u32 radeon_cp_microcode[][2] = { | 301 | static const u32 radeon_cp_microcode[][2] = { |
302 | {0x21007000, 0000000000}, | 302 | {0x21007000, 0000000000}, |
303 | {0x20007000, 0000000000}, | 303 | {0x20007000, 0000000000}, |
304 | {0x000000b4, 0x00000004}, | 304 | {0x000000b4, 0x00000004}, |
@@ -557,7 +557,7 @@ static u32 radeon_cp_microcode[][2] = { | |||
557 | {0000000000, 0000000000}, | 557 | {0000000000, 0000000000}, |
558 | }; | 558 | }; |
559 | 559 | ||
560 | static u32 R300_cp_microcode[][2] = { | 560 | static const u32 R300_cp_microcode[][2] = { |
561 | {0x4200e000, 0000000000}, | 561 | {0x4200e000, 0000000000}, |
562 | {0x4000e000, 0000000000}, | 562 | {0x4000e000, 0000000000}, |
563 | {0x000000af, 0x00000008}, | 563 | {0x000000af, 0x00000008}, |
diff --git a/drivers/char/drm/radeon_drm.h b/drivers/char/drm/radeon_drm.h index c8e279e89c2e..8d6350dd5360 100644 --- a/drivers/char/drm/radeon_drm.h +++ b/drivers/char/drm/radeon_drm.h | |||
@@ -161,7 +161,8 @@ | |||
161 | #define R200_EMIT_PP_TXCTLALL_3 91 | 161 | #define R200_EMIT_PP_TXCTLALL_3 91 |
162 | #define R200_EMIT_PP_TXCTLALL_4 92 | 162 | #define R200_EMIT_PP_TXCTLALL_4 92 |
163 | #define R200_EMIT_PP_TXCTLALL_5 93 | 163 | #define R200_EMIT_PP_TXCTLALL_5 93 |
164 | #define RADEON_MAX_STATE_PACKETS 94 | 164 | #define R200_EMIT_VAP_PVS_CNTL 94 |
165 | #define RADEON_MAX_STATE_PACKETS 95 | ||
165 | 166 | ||
166 | /* Commands understood by cmd_buffer ioctl. More can be added but | 167 | /* Commands understood by cmd_buffer ioctl. More can be added but |
167 | * obviously these can't be removed or changed: | 168 | * obviously these can't be removed or changed: |
@@ -176,6 +177,7 @@ | |||
176 | #define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: | 177 | #define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note: |
177 | * doesn't make the cpu wait, just | 178 | * doesn't make the cpu wait, just |
178 | * the graphics hardware */ | 179 | * the graphics hardware */ |
180 | #define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */ | ||
179 | 181 | ||
180 | typedef union { | 182 | typedef union { |
181 | int i; | 183 | int i; |
@@ -192,6 +194,9 @@ typedef union { | |||
192 | unsigned char cmd_type, offset, stride, count; | 194 | unsigned char cmd_type, offset, stride, count; |
193 | } vectors; | 195 | } vectors; |
194 | struct { | 196 | struct { |
197 | unsigned char cmd_type, addr_lo, addr_hi, count; | ||
198 | } veclinear; | ||
199 | struct { | ||
195 | unsigned char cmd_type, buf_idx, pad0, pad1; | 200 | unsigned char cmd_type, buf_idx, pad0, pad1; |
196 | } dma; | 201 | } dma; |
197 | struct { | 202 | struct { |
diff --git a/drivers/char/drm/radeon_drv.h b/drivers/char/drm/radeon_drv.h index 78345cee8f8e..e5a256f5429c 100644 --- a/drivers/char/drm/radeon_drv.h +++ b/drivers/char/drm/radeon_drv.h | |||
@@ -38,7 +38,7 @@ | |||
38 | 38 | ||
39 | #define DRIVER_NAME "radeon" | 39 | #define DRIVER_NAME "radeon" |
40 | #define DRIVER_DESC "ATI Radeon" | 40 | #define DRIVER_DESC "ATI Radeon" |
41 | #define DRIVER_DATE "20060225" | 41 | #define DRIVER_DATE "20060524" |
42 | 42 | ||
43 | /* Interface history: | 43 | /* Interface history: |
44 | * | 44 | * |
@@ -93,9 +93,11 @@ | |||
93 | * 1.22- Add support for texture cache flushes (R300_TX_CNTL) | 93 | * 1.22- Add support for texture cache flushes (R300_TX_CNTL) |
94 | * 1.23- Add new radeon memory map work from benh | 94 | * 1.23- Add new radeon memory map work from benh |
95 | * 1.24- Add general-purpose packet for manipulating scratch registers (r300) | 95 | * 1.24- Add general-purpose packet for manipulating scratch registers (r300) |
96 | * 1.25- Add support for r200 vertex programs (R200_EMIT_VAP_PVS_CNTL, | ||
97 | * new packet type) | ||
96 | */ | 98 | */ |
97 | #define DRIVER_MAJOR 1 | 99 | #define DRIVER_MAJOR 1 |
98 | #define DRIVER_MINOR 24 | 100 | #define DRIVER_MINOR 25 |
99 | #define DRIVER_PATCHLEVEL 0 | 101 | #define DRIVER_PATCHLEVEL 0 |
100 | 102 | ||
101 | /* | 103 | /* |
@@ -884,6 +886,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp, | |||
884 | #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 | 886 | #define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e00 |
885 | #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 | 887 | #define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e14 |
886 | 888 | ||
889 | #define RADEON_SE_TCL_STATE_FLUSH 0x2284 | ||
890 | |||
887 | #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 | 891 | #define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 |
888 | #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 | 892 | #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 |
889 | #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 | 893 | #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 |
@@ -905,6 +909,8 @@ extern int r300_do_cp_cmdbuf(drm_device_t * dev, DRMFILE filp, | |||
905 | #define R200_PP_AFS_0 0x2f80 | 909 | #define R200_PP_AFS_0 0x2f80 |
906 | #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ | 910 | #define R200_PP_AFS_1 0x2f00 /* same as txcblend_0 */ |
907 | 911 | ||
912 | #define R200_VAP_PVS_CNTL_1 0x22D0 | ||
913 | |||
908 | /* Constants */ | 914 | /* Constants */ |
909 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ | 915 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
910 | 916 | ||
diff --git a/drivers/char/drm/radeon_state.c b/drivers/char/drm/radeon_state.c index c5b8f774a599..5bb2234a9094 100644 --- a/drivers/char/drm/radeon_state.c +++ b/drivers/char/drm/radeon_state.c | |||
@@ -249,6 +249,7 @@ static __inline__ int radeon_check_and_fixup_packets(drm_radeon_private_t * | |||
249 | case R200_EMIT_PP_TXCTLALL_3: | 249 | case R200_EMIT_PP_TXCTLALL_3: |
250 | case R200_EMIT_PP_TXCTLALL_4: | 250 | case R200_EMIT_PP_TXCTLALL_4: |
251 | case R200_EMIT_PP_TXCTLALL_5: | 251 | case R200_EMIT_PP_TXCTLALL_5: |
252 | case R200_EMIT_VAP_PVS_CNTL: | ||
252 | /* These packets don't contain memory offsets */ | 253 | /* These packets don't contain memory offsets */ |
253 | break; | 254 | break; |
254 | 255 | ||
@@ -626,6 +627,7 @@ static struct { | |||
626 | {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, | 627 | {R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"}, |
627 | {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, | 628 | {R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"}, |
628 | {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, | 629 | {R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"}, |
630 | {R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"}, | ||
629 | }; | 631 | }; |
630 | 632 | ||
631 | /* ================================================================ | 633 | /* ================================================================ |
@@ -2595,7 +2597,8 @@ static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv, | |||
2595 | int stride = header.vectors.stride; | 2597 | int stride = header.vectors.stride; |
2596 | RING_LOCALS; | 2598 | RING_LOCALS; |
2597 | 2599 | ||
2598 | BEGIN_RING(3 + sz); | 2600 | BEGIN_RING(5 + sz); |
2601 | OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0); | ||
2599 | OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); | 2602 | OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); |
2600 | OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); | 2603 | OUT_RING(start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); |
2601 | OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); | 2604 | OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); |
@@ -2607,6 +2610,32 @@ static __inline__ int radeon_emit_vectors(drm_radeon_private_t *dev_priv, | |||
2607 | return 0; | 2610 | return 0; |
2608 | } | 2611 | } |
2609 | 2612 | ||
2613 | static __inline__ int radeon_emit_veclinear(drm_radeon_private_t *dev_priv, | ||
2614 | drm_radeon_cmd_header_t header, | ||
2615 | drm_radeon_kcmd_buffer_t *cmdbuf) | ||
2616 | { | ||
2617 | int sz = header.veclinear.count * 4; | ||
2618 | int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8); | ||
2619 | RING_LOCALS; | ||
2620 | |||
2621 | if (!sz) | ||
2622 | return 0; | ||
2623 | if (sz * 4 > cmdbuf->bufsz) | ||
2624 | return DRM_ERR(EINVAL); | ||
2625 | |||
2626 | BEGIN_RING(5 + sz); | ||
2627 | OUT_RING_REG(RADEON_SE_TCL_STATE_FLUSH, 0); | ||
2628 | OUT_RING(CP_PACKET0(RADEON_SE_TCL_VECTOR_INDX_REG, 0)); | ||
2629 | OUT_RING(start | (1 << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT)); | ||
2630 | OUT_RING(CP_PACKET0_TABLE(RADEON_SE_TCL_VECTOR_DATA_REG, (sz - 1))); | ||
2631 | OUT_RING_TABLE(cmdbuf->buf, sz); | ||
2632 | ADVANCE_RING(); | ||
2633 | |||
2634 | cmdbuf->buf += sz * sizeof(int); | ||
2635 | cmdbuf->bufsz -= sz * sizeof(int); | ||
2636 | return 0; | ||
2637 | } | ||
2638 | |||
2610 | static int radeon_emit_packet3(drm_device_t * dev, | 2639 | static int radeon_emit_packet3(drm_device_t * dev, |
2611 | drm_file_t * filp_priv, | 2640 | drm_file_t * filp_priv, |
2612 | drm_radeon_kcmd_buffer_t *cmdbuf) | 2641 | drm_radeon_kcmd_buffer_t *cmdbuf) |
@@ -2865,6 +2894,14 @@ static int radeon_cp_cmdbuf(DRM_IOCTL_ARGS) | |||
2865 | goto err; | 2894 | goto err; |
2866 | } | 2895 | } |
2867 | break; | 2896 | break; |
2897 | case RADEON_CMD_VECLINEAR: | ||
2898 | DRM_DEBUG("RADEON_CMD_VECLINEAR\n"); | ||
2899 | if (radeon_emit_veclinear(dev_priv, header, &cmdbuf)) { | ||
2900 | DRM_ERROR("radeon_emit_veclinear failed\n"); | ||
2901 | goto err; | ||
2902 | } | ||
2903 | break; | ||
2904 | |||
2868 | default: | 2905 | default: |
2869 | DRM_ERROR("bad cmd_type %d at %p\n", | 2906 | DRM_ERROR("bad cmd_type %d at %p\n", |
2870 | header.header.cmd_type, | 2907 | header.header.cmd_type, |