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-rw-r--r--drivers/net/tg3.c10
-rw-r--r--drivers/net/tg3.h3
2 files changed, 13 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index a4d0d61d6af0..a94631af21cd 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -5353,6 +5353,11 @@ static int tg3_reset_hw(struct tg3 *tp)
5353 5353
5354 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 | 5354 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5355 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2; 5355 GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
5356
5357 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5358 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5359 GRC_LCLCTRL_GPIO_OUTPUT3;
5360
5356 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; 5361 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5357 5362
5358 /* GPIO1 must be driven high for eeprom write protect */ 5363 /* GPIO1 must be driven high for eeprom write protect */
@@ -8077,6 +8082,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
8077 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) 8082 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
8078 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | 8083 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
8079 GRC_LCLCTRL_GPIO_OUTPUT1); 8084 GRC_LCLCTRL_GPIO_OUTPUT1);
8085 /* Unused GPIO3 must be driven as output on 5752 because there
8086 * are no pull-up resistors on unused GPIO pins.
8087 */
8088 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8089 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
8080 8090
8081 /* Force the chip into D0. */ 8091 /* Force the chip into D0. */
8082 err = tg3_set_power_state(tp, 0); 8092 err = tg3_set_power_state(tp, 0);
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 3f7cd6fb8891..548f469e9500 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1311,6 +1311,9 @@
1311#define GRC_LCLCTRL_CLEARINT 0x00000002 1311#define GRC_LCLCTRL_CLEARINT 0x00000002
1312#define GRC_LCLCTRL_SETINT 0x00000004 1312#define GRC_LCLCTRL_SETINT 0x00000004
1313#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008 1313#define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1314#define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
1315#define GRC_LCLCTRL_GPIO_OE3 0x00000040
1316#define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
1314#define GRC_LCLCTRL_GPIO_INPUT0 0x00000100 1317#define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1315#define GRC_LCLCTRL_GPIO_INPUT1 0x00000200 1318#define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1316#define GRC_LCLCTRL_GPIO_INPUT2 0x00000400 1319#define GRC_LCLCTRL_GPIO_INPUT2 0x00000400