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-rw-r--r--drivers/mtd/nand/denali.c300
1 files changed, 192 insertions, 108 deletions
diff --git a/drivers/mtd/nand/denali.c b/drivers/mtd/nand/denali.c
index 55a7a3940113..3ce11cc69721 100644
--- a/drivers/mtd/nand/denali.c
+++ b/drivers/mtd/nand/denali.c
@@ -36,8 +36,8 @@ MODULE_LICENSE("GPL");
36 36
37static int onfi_timing_mode = NAND_DEFAULT_TIMINGS; 37static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
38module_param(onfi_timing_mode, int, S_IRUGO); 38module_param(onfi_timing_mode, int, S_IRUGO);
39MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting. -1 indicates" 39MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting."
40 " use default timings"); 40 " -1 indicates use default timings");
41 41
42#define DENALI_NAND_NAME "denali-nand" 42#define DENALI_NAND_NAME "denali-nand"
43 43
@@ -123,8 +123,10 @@ static int nand_debug_level = 0;
123 123
124/* forward declarations */ 124/* forward declarations */
125static void clear_interrupts(struct denali_nand_info *denali); 125static void clear_interrupts(struct denali_nand_info *denali);
126static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask); 126static uint32_t wait_for_irq(struct denali_nand_info *denali,
127static void denali_irq_enable(struct denali_nand_info *denali, uint32_t int_mask); 127 uint32_t irq_mask);
128static void denali_irq_enable(struct denali_nand_info *denali,
129 uint32_t int_mask);
128static uint32_t read_interrupt_status(struct denali_nand_info *denali); 130static uint32_t read_interrupt_status(struct denali_nand_info *denali);
129 131
130#define DEBUG_DENALI 0 132#define DEBUG_DENALI 0
@@ -138,16 +140,19 @@ static void denali_write32(uint32_t value, void *addr)
138 iowrite32(value, addr); 140 iowrite32(value, addr);
139 141
140#if DEBUG_DENALI 142#if DEBUG_DENALI
141 printk(KERN_INFO "wrote: 0x%x -> 0x%x\n", value, (uint32_t)((uint32_t)addr & 0x1fff)); 143 printk(KERN_INFO "wrote: 0x%x -> 0x%x\n", value,
144 (uint32_t)((uint32_t)addr & 0x1fff));
142#endif 145#endif
143} 146}
144 147
145/* Certain operations for the denali NAND controller use an indexed mode to read/write 148/* Certain operations for the denali NAND controller use
146 data. The operation is performed by writing the address value of the command to 149 * an indexed mode to read/write data. The operation is
147 the device memory followed by the data. This function abstracts this common 150 * performed by writing the address value of the command
148 operation. 151 * to the device memory followed by the data. This function
152 * abstracts this common operation.
149*/ 153*/
150static void index_addr(struct denali_nand_info *denali, uint32_t address, uint32_t data) 154static void index_addr(struct denali_nand_info *denali,
155 uint32_t address, uint32_t data)
151{ 156{
152 denali_write32(address, denali->flash_mem); 157 denali_write32(address, denali->flash_mem);
153 denali_write32(data, denali->flash_mem + 0x10); 158 denali_write32(data, denali->flash_mem + 0x10);
@@ -191,7 +196,8 @@ static void read_status(struct denali_nand_info *denali)
191 write_byte_to_buf(denali, ioread32(denali->flash_mem + 0x10)); 196 write_byte_to_buf(denali, ioread32(denali->flash_mem + 0x10));
192 197
193#if DEBUG_DENALI 198#if DEBUG_DENALI
194 printk(KERN_INFO "device reporting status value of 0x%2x\n", denali->buf.buf[0]); 199 printk(KERN_INFO "device reporting status value of 0x%2x\n",
200 denali->buf.buf[0]);
195#endif 201#endif
196} 202}
197 203
@@ -227,8 +233,10 @@ static uint16_t NAND_Flash_Reset(struct denali_nand_info *denali)
227 denali->flash_reg + intr_status_addresses[i]); 233 denali->flash_reg + intr_status_addresses[i]);
228 234
229 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) { 235 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) {
230 denali_write32(device_reset_banks[i], denali->flash_reg + DEVICE_RESET); 236 denali_write32(device_reset_banks[i],
231 while (!(ioread32(denali->flash_reg + intr_status_addresses[i]) & 237 denali->flash_reg + DEVICE_RESET);
238 while (!(ioread32(denali->flash_reg +
239 intr_status_addresses[i]) &
232 (reset_complete[i] | operation_timeout[i]))) 240 (reset_complete[i] | operation_timeout[i])))
233 ; 241 ;
234 if (ioread32(denali->flash_reg + intr_status_addresses[i]) & 242 if (ioread32(denali->flash_reg + intr_status_addresses[i]) &
@@ -244,11 +252,12 @@ static uint16_t NAND_Flash_Reset(struct denali_nand_info *denali)
244 return PASS; 252 return PASS;
245} 253}
246 254
247/* this routine calculates the ONFI timing values for a given mode and programs 255/* this routine calculates the ONFI timing values for a given mode and
248 * the clocking register accordingly. The mode is determined by the get_onfi_nand_para 256 * programs the clocking register accordingly. The mode is determined by
249 routine. 257 * the get_onfi_nand_para routine.
250 */ 258 */
251static void NAND_ONFi_Timing_Mode(struct denali_nand_info *denali, uint16_t mode) 259static void NAND_ONFi_Timing_Mode(struct denali_nand_info *denali,
260 uint16_t mode)
252{ 261{
253 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16}; 262 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
254 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10}; 263 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
@@ -354,10 +363,11 @@ static void set_ecc_config(struct denali_nand_info *denali)
354 denali_write32(8, denali->flash_reg + ECC_CORRECTION); 363 denali_write32(8, denali->flash_reg + ECC_CORRECTION);
355#endif 364#endif
356 365
357 if ((ioread32(denali->flash_reg + ECC_CORRECTION) & ECC_CORRECTION__VALUE) 366 if ((ioread32(denali->flash_reg + ECC_CORRECTION) &
358 == 1) { 367 ECC_CORRECTION__VALUE) == 1) {
359 denali->dev_info.wECCBytesPerSector = 4; 368 denali->dev_info.wECCBytesPerSector = 4;
360 denali->dev_info.wECCBytesPerSector *= denali->dev_info.wDevicesConnected; 369 denali->dev_info.wECCBytesPerSector *=
370 denali->dev_info.wDevicesConnected;
361 denali->dev_info.wNumPageSpareFlag = 371 denali->dev_info.wNumPageSpareFlag =
362 denali->dev_info.wPageSpareSize - 372 denali->dev_info.wPageSpareSize -
363 denali->dev_info.wPageDataSize / 373 denali->dev_info.wPageDataSize /
@@ -373,8 +383,10 @@ static void set_ecc_config(struct denali_nand_info *denali)
373 else 383 else
374 denali->dev_info.wECCBytesPerSector += 1; 384 denali->dev_info.wECCBytesPerSector += 1;
375 385
376 denali->dev_info.wECCBytesPerSector *= denali->dev_info.wDevicesConnected; 386 denali->dev_info.wECCBytesPerSector *=
377 denali->dev_info.wNumPageSpareFlag = denali->dev_info.wPageSpareSize - 387 denali->dev_info.wDevicesConnected;
388 denali->dev_info.wNumPageSpareFlag =
389 denali->dev_info.wPageSpareSize -
378 denali->dev_info.wPageDataSize / 390 denali->dev_info.wPageDataSize /
379 (ECC_SECTOR_SIZE * denali->dev_info.wDevicesConnected) * 391 (ECC_SECTOR_SIZE * denali->dev_info.wDevicesConnected) *
380 denali->dev_info.wECCBytesPerSector 392 denali->dev_info.wECCBytesPerSector
@@ -392,13 +404,15 @@ static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
392 denali_write32(DEVICE_RESET__BANK0, denali->flash_reg + DEVICE_RESET); 404 denali_write32(DEVICE_RESET__BANK0, denali->flash_reg + DEVICE_RESET);
393 405
394 while (!((ioread32(denali->flash_reg + INTR_STATUS0) & 406 while (!((ioread32(denali->flash_reg + INTR_STATUS0) &
395 INTR_STATUS0__RST_COMP) | 407 INTR_STATUS0__RST_COMP) |
396 (ioread32(denali->flash_reg + INTR_STATUS0) & 408 (ioread32(denali->flash_reg + INTR_STATUS0) &
397 INTR_STATUS0__TIME_OUT))) 409 INTR_STATUS0__TIME_OUT)))
398 ; 410 ;
399 411
400 if (ioread32(denali->flash_reg + INTR_STATUS0) & INTR_STATUS0__RST_COMP) { 412 if (ioread32(denali->flash_reg + INTR_STATUS0) &
401 denali_write32(DEVICE_RESET__BANK1, denali->flash_reg + DEVICE_RESET); 413 INTR_STATUS0__RST_COMP) {
414 denali_write32(DEVICE_RESET__BANK1,
415 denali->flash_reg + DEVICE_RESET);
402 while (!((ioread32(denali->flash_reg + INTR_STATUS1) & 416 while (!((ioread32(denali->flash_reg + INTR_STATUS1) &
403 INTR_STATUS1__RST_COMP) | 417 INTR_STATUS1__RST_COMP) |
404 (ioread32(denali->flash_reg + INTR_STATUS1) & 418 (ioread32(denali->flash_reg + INTR_STATUS1) &
@@ -419,10 +433,12 @@ static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
419 INTR_STATUS2__RST_COMP) { 433 INTR_STATUS2__RST_COMP) {
420 denali_write32(DEVICE_RESET__BANK3, 434 denali_write32(DEVICE_RESET__BANK3,
421 denali->flash_reg + DEVICE_RESET); 435 denali->flash_reg + DEVICE_RESET);
422 while (!((ioread32(denali->flash_reg + INTR_STATUS3) & 436 while (!((ioread32(denali->flash_reg +
423 INTR_STATUS3__RST_COMP) | 437 INTR_STATUS3) &
424 (ioread32(denali->flash_reg + INTR_STATUS3) & 438 INTR_STATUS3__RST_COMP) |
425 INTR_STATUS3__TIME_OUT))) 439 (ioread32(denali->flash_reg +
440 INTR_STATUS3) &
441 INTR_STATUS3__TIME_OUT)))
426 ; 442 ;
427 } else { 443 } else {
428 printk(KERN_ERR "Getting a time out for bank 2!\n"); 444 printk(KERN_ERR "Getting a time out for bank 2!\n");
@@ -432,10 +448,14 @@ static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
432 } 448 }
433 } 449 }
434 450
435 denali_write32(INTR_STATUS0__TIME_OUT, denali->flash_reg + INTR_STATUS0); 451 denali_write32(INTR_STATUS0__TIME_OUT,
436 denali_write32(INTR_STATUS1__TIME_OUT, denali->flash_reg + INTR_STATUS1); 452 denali->flash_reg + INTR_STATUS0);
437 denali_write32(INTR_STATUS2__TIME_OUT, denali->flash_reg + INTR_STATUS2); 453 denali_write32(INTR_STATUS1__TIME_OUT,
438 denali_write32(INTR_STATUS3__TIME_OUT, denali->flash_reg + INTR_STATUS3); 454 denali->flash_reg + INTR_STATUS1);
455 denali_write32(INTR_STATUS2__TIME_OUT,
456 denali->flash_reg + INTR_STATUS2);
457 denali_write32(INTR_STATUS3__TIME_OUT,
458 denali->flash_reg + INTR_STATUS3);
439 459
440 denali->dev_info.wONFIDevFeatures = 460 denali->dev_info.wONFIDevFeatures =
441 ioread32(denali->flash_reg + ONFI_DEVICE_FEATURES); 461 ioread32(denali->flash_reg + ONFI_DEVICE_FEATURES);
@@ -448,8 +468,10 @@ static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
448 468
449 n_of_luns = ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & 469 n_of_luns = ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
450 ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS; 470 ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS;
451 blks_lun_l = ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L); 471 blks_lun_l = ioread32(denali->flash_reg +
452 blks_lun_h = ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U); 472 ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L);
473 blks_lun_h = ioread32(denali->flash_reg +
474 ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U);
453 475
454 blockperlun = (blks_lun_h << 16) | blks_lun_l; 476 blockperlun = (blks_lun_h << 16) | blks_lun_l;
455 477
@@ -460,7 +482,8 @@ static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
460 return FAIL; 482 return FAIL;
461 483
462 for (i = 5; i > 0; i--) { 484 for (i = 5; i > 0; i--) {
463 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) & (0x01 << i)) 485 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
486 (0x01 << i))
464 break; 487 break;
465 } 488 }
466 489
@@ -495,7 +518,8 @@ static void get_samsung_nand_para(struct denali_nand_info *denali)
495 index_addr(denali, (uint32_t)(MODE_11 | 0), 0x90); 518 index_addr(denali, (uint32_t)(MODE_11 | 0), 0x90);
496 index_addr(denali, (uint32_t)(MODE_11 | 1), 0); 519 index_addr(denali, (uint32_t)(MODE_11 | 1), 0);
497 for (i = 0; i < 5; i++) 520 for (i = 0; i < 5; i++)
498 index_addr_read_data(denali, (uint32_t)(MODE_11 | 2), &id_bytes[i]); 521 index_addr_read_data(denali, (uint32_t)(MODE_11 | 2),
522 &id_bytes[i]);
499 523
500 nand_dbg_print(NAND_DBG_DEBUG, 524 nand_dbg_print(NAND_DBG_DEBUG,
501 "ID bytes: 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", 525 "ID bytes: 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
@@ -515,7 +539,8 @@ static void get_samsung_nand_para(struct denali_nand_info *denali)
515 539
516 no_of_planes = 1 << ((id_bytes[4] & 0x0c) >> 2); 540 no_of_planes = 1 << ((id_bytes[4] & 0x0c) >> 2);
517 plane_size = (uint64_t)64 << ((id_bytes[4] & 0x70) >> 4); 541 plane_size = (uint64_t)64 << ((id_bytes[4] & 0x70) >> 4);
518 blk_size = 64 << ((ioread32(denali->flash_reg + DEVICE_PARAM_1) & 0x30) >> 4); 542 blk_size = 64 << ((ioread32(denali->flash_reg + DEVICE_PARAM_1) &
543 0x30) >> 4);
519 capacity = (uint64_t)128 * plane_size * no_of_planes; 544 capacity = (uint64_t)128 * plane_size * no_of_planes;
520 545
521 do_div(capacity, blk_size); 546 do_div(capacity, blk_size);
@@ -534,7 +559,8 @@ static void get_toshiba_nand_para(struct denali_nand_info *denali)
534 denali_write32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); 559 denali_write32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
535 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) * 560 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
536 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE); 561 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
537 denali_write32(tmp, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); 562 denali_write32(tmp,
563 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
538#if SUPPORT_15BITECC 564#if SUPPORT_15BITECC
539 denali_write32(15, denali->flash_reg + ECC_CORRECTION); 565 denali_write32(15, denali->flash_reg + ECC_CORRECTION);
540#elif SUPPORT_8BITECC 566#elif SUPPORT_8BITECC
@@ -573,10 +599,14 @@ static void get_hynix_nand_para(struct denali_nand_info *denali)
573 denali_write32(128, denali->flash_reg + PAGES_PER_BLOCK); 599 denali_write32(128, denali->flash_reg + PAGES_PER_BLOCK);
574 denali_write32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE); 600 denali_write32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
575 denali_write32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE); 601 denali_write32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
576 main_size = 4096 * ioread32(denali->flash_reg + DEVICES_CONNECTED); 602 main_size = 4096 *
577 spare_size = 224 * ioread32(denali->flash_reg + DEVICES_CONNECTED); 603 ioread32(denali->flash_reg + DEVICES_CONNECTED);
578 denali_write32(main_size, denali->flash_reg + LOGICAL_PAGE_DATA_SIZE); 604 spare_size = 224 *
579 denali_write32(spare_size, denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); 605 ioread32(denali->flash_reg + DEVICES_CONNECTED);
606 denali_write32(main_size,
607 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
608 denali_write32(spare_size,
609 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
580 denali_write32(0, denali->flash_reg + DEVICE_WIDTH); 610 denali_write32(0, denali->flash_reg + DEVICE_WIDTH);
581#if SUPPORT_15BITECC 611#if SUPPORT_15BITECC
582 denali_write32(15, denali->flash_reg + ECC_CORRECTION); 612 denali_write32(15, denali->flash_reg + ECC_CORRECTION);
@@ -619,7 +649,8 @@ static void find_valid_banks(struct denali_nand_info *denali)
619 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) { 649 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) {
620 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90); 650 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90);
621 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0); 651 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0);
622 index_addr_read_data(denali, (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]); 652 index_addr_read_data(denali,
653 (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]);
623 654
624 nand_dbg_print(NAND_DBG_DEBUG, 655 nand_dbg_print(NAND_DBG_DEBUG,
625 "Return 1st ID for bank[%d]: %x\n", i, id[i]); 656 "Return 1st ID for bank[%d]: %x\n", i, id[i]);
@@ -671,7 +702,8 @@ static void detect_partition_feature(struct denali_nand_info *denali)
671 (ioread32(denali->flash_reg + MAX_BLK_ADDR_1) & 702 (ioread32(denali->flash_reg + MAX_BLK_ADDR_1) &
672 MAX_BLK_ADDR_1__VALUE); 703 MAX_BLK_ADDR_1__VALUE);
673 704
674 denali->dev_info.wTotalBlocks *= denali->total_used_banks; 705 denali->dev_info.wTotalBlocks *=
706 denali->total_used_banks;
675 707
676 if (denali->dev_info.wSpectraEndBlock >= 708 if (denali->dev_info.wSpectraEndBlock >=
677 denali->dev_info.wTotalBlocks) { 709 denali->dev_info.wTotalBlocks) {
@@ -683,8 +715,10 @@ static void detect_partition_feature(struct denali_nand_info *denali)
683 denali->dev_info.wSpectraEndBlock - 715 denali->dev_info.wSpectraEndBlock -
684 denali->dev_info.wSpectraStartBlock + 1; 716 denali->dev_info.wSpectraStartBlock + 1;
685 } else { 717 } else {
686 denali->dev_info.wTotalBlocks *= denali->total_used_banks; 718 denali->dev_info.wTotalBlocks *=
687 denali->dev_info.wSpectraStartBlock = SPECTRA_START_BLOCK; 719 denali->total_used_banks;
720 denali->dev_info.wSpectraStartBlock =
721 SPECTRA_START_BLOCK;
688 denali->dev_info.wSpectraEndBlock = 722 denali->dev_info.wSpectraEndBlock =
689 denali->dev_info.wTotalBlocks - 1; 723 denali->dev_info.wTotalBlocks - 1;
690 denali->dev_info.wDataBlockNum = 724 denali->dev_info.wDataBlockNum =
@@ -694,7 +728,8 @@ static void detect_partition_feature(struct denali_nand_info *denali)
694 } else { 728 } else {
695 denali->dev_info.wTotalBlocks *= denali->total_used_banks; 729 denali->dev_info.wTotalBlocks *= denali->total_used_banks;
696 denali->dev_info.wSpectraStartBlock = SPECTRA_START_BLOCK; 730 denali->dev_info.wSpectraStartBlock = SPECTRA_START_BLOCK;
697 denali->dev_info.wSpectraEndBlock = denali->dev_info.wTotalBlocks - 1; 731 denali->dev_info.wSpectraEndBlock =
732 denali->dev_info.wTotalBlocks - 1;
698 denali->dev_info.wDataBlockNum = 733 denali->dev_info.wDataBlockNum =
699 denali->dev_info.wSpectraEndBlock - 734 denali->dev_info.wSpectraEndBlock -
700 denali->dev_info.wSpectraStartBlock + 1; 735 denali->dev_info.wSpectraStartBlock + 1;
@@ -776,13 +811,19 @@ static uint16_t NAND_Read_Device_ID(struct denali_nand_info *denali)
776 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n", 811 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
777 __FILE__, __LINE__, __func__); 812 __FILE__, __LINE__, __func__);
778 813
779 denali->dev_info.wDeviceMaker = ioread32(denali->flash_reg + MANUFACTURER_ID); 814 denali->dev_info.wDeviceMaker =
780 denali->dev_info.wDeviceID = ioread32(denali->flash_reg + DEVICE_ID); 815 ioread32(denali->flash_reg + MANUFACTURER_ID);
781 denali->dev_info.bDeviceParam0 = ioread32(denali->flash_reg + DEVICE_PARAM_0); 816 denali->dev_info.wDeviceID =
782 denali->dev_info.bDeviceParam1 = ioread32(denali->flash_reg + DEVICE_PARAM_1); 817 ioread32(denali->flash_reg + DEVICE_ID);
783 denali->dev_info.bDeviceParam2 = ioread32(denali->flash_reg + DEVICE_PARAM_2); 818 denali->dev_info.bDeviceParam0 =
819 ioread32(denali->flash_reg + DEVICE_PARAM_0);
820 denali->dev_info.bDeviceParam1 =
821 ioread32(denali->flash_reg + DEVICE_PARAM_1);
822 denali->dev_info.bDeviceParam2 =
823 ioread32(denali->flash_reg + DEVICE_PARAM_2);
784 824
785 denali->dev_info.MLCDevice = ioread32(denali->flash_reg + DEVICE_PARAM_0) & 0x0c; 825 denali->dev_info.MLCDevice =
826 ioread32(denali->flash_reg + DEVICE_PARAM_0) & 0x0c;
786 827
787 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) & 828 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
788 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */ 829 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
@@ -831,7 +872,8 @@ static uint16_t NAND_Read_Device_ID(struct denali_nand_info *denali)
831 denali->dev_info.wPageSpareSize = 872 denali->dev_info.wPageSpareSize =
832 ioread32(denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE); 873 ioread32(denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
833 874
834 denali->dev_info.wPagesPerBlock = ioread32(denali->flash_reg + PAGES_PER_BLOCK); 875 denali->dev_info.wPagesPerBlock =
876 ioread32(denali->flash_reg + PAGES_PER_BLOCK);
835 877
836 denali->dev_info.wPageSize = 878 denali->dev_info.wPageSize =
837 denali->dev_info.wPageDataSize + denali->dev_info.wPageSpareSize; 879 denali->dev_info.wPageDataSize + denali->dev_info.wPageSpareSize;
@@ -840,11 +882,13 @@ static uint16_t NAND_Read_Device_ID(struct denali_nand_info *denali)
840 denali->dev_info.wBlockDataSize = 882 denali->dev_info.wBlockDataSize =
841 denali->dev_info.wPagesPerBlock * denali->dev_info.wPageDataSize; 883 denali->dev_info.wPagesPerBlock * denali->dev_info.wPageDataSize;
842 884
843 denali->dev_info.wDeviceWidth = ioread32(denali->flash_reg + DEVICE_WIDTH); 885 denali->dev_info.wDeviceWidth =
886 ioread32(denali->flash_reg + DEVICE_WIDTH);
844 denali->dev_info.wDeviceType = 887 denali->dev_info.wDeviceType =
845 ((ioread32(denali->flash_reg + DEVICE_WIDTH) > 0) ? 16 : 8); 888 ((ioread32(denali->flash_reg + DEVICE_WIDTH) > 0) ? 16 : 8);
846 889
847 denali->dev_info.wDevicesConnected = ioread32(denali->flash_reg + DEVICES_CONNECTED); 890 denali->dev_info.wDevicesConnected =
891 ioread32(denali->flash_reg + DEVICES_CONNECTED);
848 892
849 denali->dev_info.wSpareSkipBytes = 893 denali->dev_info.wSpareSkipBytes =
850 ioread32(denali->flash_reg + SPARE_AREA_SKIP_BYTES) * 894 ioread32(denali->flash_reg + SPARE_AREA_SKIP_BYTES) *
@@ -933,7 +977,8 @@ static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
933 free_irq(irqnum, denali); 977 free_irq(irqnum, denali);
934} 978}
935 979
936static void denali_irq_enable(struct denali_nand_info *denali, uint32_t int_mask) 980static void denali_irq_enable(struct denali_nand_info *denali,
981 uint32_t int_mask)
937{ 982{
938 denali_write32(int_mask, denali->flash_reg + INTR_EN0); 983 denali_write32(int_mask, denali->flash_reg + INTR_EN0);
939 denali_write32(int_mask, denali->flash_reg + INTR_EN1); 984 denali_write32(int_mask, denali->flash_reg + INTR_EN1);
@@ -950,7 +995,8 @@ static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
950} 995}
951 996
952/* Interrupts are cleared by writing a 1 to the appropriate status bit */ 997/* Interrupts are cleared by writing a 1 to the appropriate status bit */
953static inline void clear_interrupt(struct denali_nand_info *denali, uint32_t irq_mask) 998static inline void clear_interrupt(struct denali_nand_info *denali,
999 uint32_t irq_mask)
954{ 1000{
955 uint32_t intr_status_reg = 0; 1001 uint32_t intr_status_reg = 0;
956 1002
@@ -1013,9 +1059,11 @@ static irqreturn_t denali_isr(int irq, void *dev_id)
1013 if (is_flash_bank_valid(denali->flash_bank)) { 1059 if (is_flash_bank_valid(denali->flash_bank)) {
1014 /* check to see if controller generated 1060 /* check to see if controller generated
1015 * the interrupt, since this is a shared interrupt */ 1061 * the interrupt, since this is a shared interrupt */
1016 if ((irq_status = denali_irq_detected(denali)) != 0) { 1062 irq_status = denali_irq_detected(denali);
1063 if (irq_status != 0) {
1017#if DEBUG_DENALI 1064#if DEBUG_DENALI
1018 denali->irq_debug_array[denali->idx++] = 0x10000000 | irq_status; 1065 denali->irq_debug_array[denali->idx++] =
1066 0x10000000 | irq_status;
1019 denali->idx %= 32; 1067 denali->idx %= 32;
1020 1068
1021 printk(KERN_INFO "IRQ status = 0x%04x\n", irq_status); 1069 printk(KERN_INFO "IRQ status = 0x%04x\n", irq_status);
@@ -1048,12 +1096,14 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
1048#if DEBUG_DENALI 1096#if DEBUG_DENALI
1049 printk(KERN_INFO "waiting for 0x%x\n", irq_mask); 1097 printk(KERN_INFO "waiting for 0x%x\n", irq_mask);
1050#endif 1098#endif
1051 comp_res = wait_for_completion_timeout(&denali->complete, timeout); 1099 comp_res =
1100 wait_for_completion_timeout(&denali->complete, timeout);
1052 spin_lock_irq(&denali->irq_lock); 1101 spin_lock_irq(&denali->irq_lock);
1053 intr_status = denali->irq_status; 1102 intr_status = denali->irq_status;
1054 1103
1055#if DEBUG_DENALI 1104#if DEBUG_DENALI
1056 denali->irq_debug_array[denali->idx++] = 0x20000000 | (irq_mask << 16) | intr_status; 1105 denali->irq_debug_array[denali->idx++] =
1106 0x20000000 | (irq_mask << 16) | intr_status;
1057 denali->idx %= 32; 1107 denali->idx %= 32;
1058#endif 1108#endif
1059 1109
@@ -1061,7 +1111,9 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
1061 denali->irq_status &= ~irq_mask; 1111 denali->irq_status &= ~irq_mask;
1062 spin_unlock_irq(&denali->irq_lock); 1112 spin_unlock_irq(&denali->irq_lock);
1063#if DEBUG_DENALI 1113#if DEBUG_DENALI
1064 if (retry) printk(KERN_INFO "status on retry = 0x%x\n", intr_status); 1114 if (retry)
1115 printk(KERN_INFO "status on retry = 0x%x\n",
1116 intr_status);
1065#endif 1117#endif
1066 /* our interrupt was detected */ 1118 /* our interrupt was detected */
1067 break; 1119 break;
@@ -1071,8 +1123,10 @@ static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
1071 spin_unlock_irq(&denali->irq_lock); 1123 spin_unlock_irq(&denali->irq_lock);
1072#if DEBUG_DENALI 1124#if DEBUG_DENALI
1073 print_irq_log(denali); 1125 print_irq_log(denali);
1074 printk(KERN_INFO "received irq nobody cared: irq_status = 0x%x," 1126 printk(KERN_INFO "received irq nobody cared:"
1075 " irq_mask = 0x%x, timeout = %ld\n", intr_status, irq_mask, comp_res); 1127 " irq_status = 0x%x, irq_mask = 0x%x,"
1128 " timeout = %ld\n", intr_status,
1129 irq_mask, comp_res);
1076#endif 1130#endif
1077 retry = true; 1131 retry = true;
1078 } 1132 }
@@ -1101,15 +1155,18 @@ static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
1101 1155
1102 /* Enable spare area/ECC per user's request. */ 1156 /* Enable spare area/ECC per user's request. */
1103 denali_write32(ecc_en_flag, denali->flash_reg + ECC_ENABLE); 1157 denali_write32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
1104 denali_write32(transfer_spare_flag, denali->flash_reg + TRANSFER_SPARE_REG); 1158 denali_write32(transfer_spare_flag,
1159 denali->flash_reg + TRANSFER_SPARE_REG);
1105} 1160}
1106 1161
1107/* sends a pipeline command operation to the controller. See the Denali NAND 1162/* sends a pipeline command operation to the controller. See the Denali NAND
1108 controller's user guide for more information (section 4.2.3.6). 1163 controller's user guide for more information (section 4.2.3.6).
1109 */ 1164 */
1110static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en, 1165static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
1111 bool transfer_spare, int access_type, 1166 bool ecc_en,
1112 int op) 1167 bool transfer_spare,
1168 int access_type,
1169 int op)
1113{ 1170{
1114 int status = PASS; 1171 int status = PASS;
1115 uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0, 1172 uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0,
@@ -1123,7 +1180,9 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en
1123 1180
1124#if DEBUG_DENALI 1181#if DEBUG_DENALI
1125 spin_lock_irq(&denali->irq_lock); 1182 spin_lock_irq(&denali->irq_lock);
1126 denali->irq_debug_array[denali->idx++] = 0x40000000 | ioread32(denali->flash_reg + ECC_ENABLE) | (access_type << 4); 1183 denali->irq_debug_array[denali->idx++] =
1184 0x40000000 | ioread32(denali->flash_reg + ECC_ENABLE) |
1185 (access_type << 4);
1127 denali->idx %= 32; 1186 denali->idx %= 32;
1128 spin_unlock_irq(&denali->irq_lock); 1187 spin_unlock_irq(&denali->irq_lock);
1129#endif 1188#endif
@@ -1157,16 +1216,19 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en
1157 cmd = MODE_01 | addr; 1216 cmd = MODE_01 | addr;
1158 denali_write32(cmd, denali->flash_mem); 1217 denali_write32(cmd, denali->flash_mem);
1159 } else { 1218 } else {
1160 index_addr(denali, (uint32_t)cmd, 0x2000 | op | page_count); 1219 index_addr(denali, (uint32_t)cmd,
1220 0x2000 | op | page_count);
1161 1221
1162 /* wait for command to be accepted 1222 /* wait for command to be accepted
1163 * can always use status0 bit as the mask is identical for each 1223 * can always use status0 bit as the
1224 * mask is identical for each
1164 * bank. */ 1225 * bank. */
1165 irq_status = wait_for_irq(denali, irq_mask); 1226 irq_status = wait_for_irq(denali, irq_mask);
1166 1227
1167 if (irq_status == 0) { 1228 if (irq_status == 0) {
1168 printk(KERN_ERR "cmd, page, addr on timeout " 1229 printk(KERN_ERR "cmd, page, addr on timeout "
1169 "(0x%x, 0x%x, 0x%x)\n", cmd, denali->page, addr); 1230 "(0x%x, 0x%x, 0x%x)\n", cmd,
1231 denali->page, addr);
1170 status = FAIL; 1232 status = FAIL;
1171 } else { 1233 } else {
1172 cmd = MODE_01 | addr; 1234 cmd = MODE_01 | addr;
@@ -1178,8 +1240,9 @@ static int denali_send_pipeline_cmd(struct denali_nand_info *denali, bool ecc_en
1178} 1240}
1179 1241
1180/* helper function that simply writes a buffer to the flash */ 1242/* helper function that simply writes a buffer to the flash */
1181static int write_data_to_flash_mem(struct denali_nand_info *denali, const uint8_t *buf, 1243static int write_data_to_flash_mem(struct denali_nand_info *denali,
1182 int len) 1244 const uint8_t *buf,
1245 int len)
1183{ 1246{
1184 uint32_t i = 0, *buf32; 1247 uint32_t i = 0, *buf32;
1185 1248
@@ -1195,8 +1258,9 @@ static int write_data_to_flash_mem(struct denali_nand_info *denali, const uint8_
1195} 1258}
1196 1259
1197/* helper function that simply reads a buffer from the flash */ 1260/* helper function that simply reads a buffer from the flash */
1198static int read_data_from_flash_mem(struct denali_nand_info *denali, uint8_t *buf, 1261static int read_data_from_flash_mem(struct denali_nand_info *denali,
1199 int len) 1262 uint8_t *buf,
1263 int len)
1200{ 1264{
1201 uint32_t i = 0, *buf32; 1265 uint32_t i = 0, *buf32;
1202 1266
@@ -1234,7 +1298,8 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1234 1298
1235#if DEBUG_DENALI 1299#if DEBUG_DENALI
1236 spin_lock_irq(&denali->irq_lock); 1300 spin_lock_irq(&denali->irq_lock);
1237 denali->irq_debug_array[denali->idx++] = 0x80000000 | mtd->oobsize; 1301 denali->irq_debug_array[denali->idx++] =
1302 0x80000000 | mtd->oobsize;
1238 denali->idx %= 32; 1303 denali->idx %= 32;
1239 spin_unlock_irq(&denali->irq_lock); 1304 spin_unlock_irq(&denali->irq_lock);
1240#endif 1305#endif
@@ -1258,7 +1323,8 @@ static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1258static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page) 1323static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1259{ 1324{
1260 struct denali_nand_info *denali = mtd_to_denali(mtd); 1325 struct denali_nand_info *denali = mtd_to_denali(mtd);
1261 uint32_t irq_mask = INTR_STATUS0__LOAD_COMP, irq_status = 0, addr = 0x0, cmd = 0x0; 1326 uint32_t irq_mask = INTR_STATUS0__LOAD_COMP,
1327 irq_status = 0, addr = 0x0, cmd = 0x0;
1262 1328
1263 denali->page = page; 1329 denali->page = page;
1264 1330
@@ -1275,7 +1341,8 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1275 irq_status = wait_for_irq(denali, irq_mask); 1341 irq_status = wait_for_irq(denali, irq_mask);
1276 1342
1277 if (irq_status == 0) 1343 if (irq_status == 0)
1278 printk(KERN_ERR "page on OOB timeout %d\n", denali->page); 1344 printk(KERN_ERR "page on OOB timeout %d\n",
1345 denali->page);
1279 1346
1280 /* We set the device back to MAIN_ACCESS here as I observed 1347 /* We set the device back to MAIN_ACCESS here as I observed
1281 * instability with the controller if you do a block erase 1348 * instability with the controller if you do a block erase
@@ -1289,7 +1356,8 @@ static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1289 1356
1290#if DEBUG_DENALI 1357#if DEBUG_DENALI
1291 spin_lock_irq(&denali->irq_lock); 1358 spin_lock_irq(&denali->irq_lock);
1292 denali->irq_debug_array[denali->idx++] = 0x60000000 | mtd->oobsize; 1359 denali->irq_debug_array[denali->idx++] =
1360 0x60000000 | mtd->oobsize;
1293 denali->idx %= 32; 1361 denali->idx %= 32;
1294 spin_unlock_irq(&denali->irq_lock); 1362 spin_unlock_irq(&denali->irq_lock);
1295#endif 1363#endif
@@ -1358,15 +1426,17 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
1358 } 1426 }
1359 } else { 1427 } else {
1360 /* if the error is not correctable, need to 1428 /* if the error is not correctable, need to
1361 * look at the page to see if it is an erased page. 1429 * look at the page to see if it is an erased
1362 * if so, then it's not a real ECC error */ 1430 * page. if so, then it's not a real ECC error
1431 * */
1363 check_erased_page = true; 1432 check_erased_page = true;
1364 } 1433 }
1365 1434
1366#if DEBUG_DENALI 1435#if DEBUG_DENALI
1367 printk(KERN_INFO "Detected ECC error in page %d: err_addr = 0x%08x," 1436 printk(KERN_INFO "Detected ECC error in page %d:"
1368 " info to fix is 0x%08x\n", denali->page, err_address, 1437 " err_addr = 0x%08x, info to fix is"
1369 err_correction_info); 1438 " 0x%08x\n", denali->page, err_address,
1439 err_correction_info);
1370#endif 1440#endif
1371 } while (!ECC_LAST_ERR(err_correction_info)); 1441 } while (!ECC_LAST_ERR(err_correction_info));
1372 } 1442 }
@@ -1451,10 +1521,11 @@ static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1451 irq_status = wait_for_irq(denali, irq_mask); 1521 irq_status = wait_for_irq(denali, irq_mask);
1452 1522
1453 if (irq_status == 0) { 1523 if (irq_status == 0) {
1454 printk(KERN_ERR "timeout on write_page (type = %d)\n", raw_xfer); 1524 printk(KERN_ERR "timeout on write_page"
1525 " (type = %d)\n", raw_xfer);
1455 denali->status = 1526 denali->status =
1456 (irq_status & INTR_STATUS0__PROGRAM_FAIL) ? NAND_STATUS_FAIL : 1527 (irq_status & INTR_STATUS0__PROGRAM_FAIL) ?
1457 PASS; 1528 NAND_STATUS_FAIL : PASS;
1458 } 1529 }
1459 1530
1460 denali_enable_dma(denali, false); 1531 denali_enable_dma(denali, false);
@@ -1637,8 +1708,8 @@ static void denali_erase(struct mtd_info *mtd, int page)
1637 irq_status = wait_for_irq(denali, INTR_STATUS0__ERASE_COMP | 1708 irq_status = wait_for_irq(denali, INTR_STATUS0__ERASE_COMP |
1638 INTR_STATUS0__ERASE_FAIL); 1709 INTR_STATUS0__ERASE_FAIL);
1639 1710
1640 denali->status = (irq_status & INTR_STATUS0__ERASE_FAIL) ? NAND_STATUS_FAIL : 1711 denali->status = (irq_status & INTR_STATUS0__ERASE_FAIL) ?
1641 PASS; 1712 NAND_STATUS_FAIL : PASS;
1642} 1713}
1643 1714
1644static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col, 1715static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
@@ -1661,11 +1732,16 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1661 /* write manufacturer information into nand 1732 /* write manufacturer information into nand
1662 buffer for NAND subsystem to fetch. 1733 buffer for NAND subsystem to fetch.
1663 */ 1734 */
1664 write_byte_to_buf(denali, denali->dev_info.wDeviceMaker); 1735 write_byte_to_buf(denali,
1665 write_byte_to_buf(denali, denali->dev_info.wDeviceID); 1736 denali->dev_info.wDeviceMaker);
1666 write_byte_to_buf(denali, denali->dev_info.bDeviceParam0); 1737 write_byte_to_buf(denali,
1667 write_byte_to_buf(denali, denali->dev_info.bDeviceParam1); 1738 denali->dev_info.wDeviceID);
1668 write_byte_to_buf(denali, denali->dev_info.bDeviceParam2); 1739 write_byte_to_buf(denali,
1740 denali->dev_info.bDeviceParam0);
1741 write_byte_to_buf(denali,
1742 denali->dev_info.bDeviceParam1);
1743 write_byte_to_buf(denali,
1744 denali->dev_info.bDeviceParam2);
1669 } else { 1745 } else {
1670 int i; 1746 int i;
1671 for (i = 0; i < 5; i++) 1747 for (i = 0; i < 5; i++)
@@ -1683,7 +1759,8 @@ static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1683 /* TODO: Read OOB data */ 1759 /* TODO: Read OOB data */
1684 break; 1760 break;
1685 default: 1761 default:
1686 printk(KERN_ERR ": unsupported command received 0x%x\n", cmd); 1762 printk(KERN_ERR ": unsupported command"
1763 " received 0x%x\n", cmd);
1687 break; 1764 break;
1688 } 1765 }
1689} 1766}
@@ -1718,7 +1795,8 @@ static void denali_hw_init(struct denali_nand_info *denali)
1718 denali_irq_init(denali); 1795 denali_irq_init(denali);
1719 NAND_Flash_Reset(denali); 1796 NAND_Flash_Reset(denali);
1720 denali_write32(0x0F, denali->flash_reg + RB_PIN_ENABLED); 1797 denali_write32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1721 denali_write32(CHIP_EN_DONT_CARE__FLAG, denali->flash_reg + CHIP_ENABLE_DONT_CARE); 1798 denali_write32(CHIP_EN_DONT_CARE__FLAG,
1799 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
1722 1800
1723 denali_write32(0x0, denali->flash_reg + SPARE_AREA_SKIP_BYTES); 1801 denali_write32(0x0, denali->flash_reg + SPARE_AREA_SKIP_BYTES);
1724 denali_write32(0xffff, denali->flash_reg + SPARE_AREA_MARKER); 1802 denali_write32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
@@ -1824,8 +1902,8 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1824 * ONFI timing mode 1 and below. 1902 * ONFI timing mode 1 and below.
1825 */ 1903 */
1826 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) { 1904 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
1827 printk(KERN_ERR "Intel CE4100 only supports ONFI timing mode 1 " 1905 printk(KERN_ERR "Intel CE4100 only supports"
1828 "or below\n"); 1906 " ONFI timing mode 1 or below\n");
1829 ret = -EINVAL; 1907 ret = -EINVAL;
1830 goto failed_enable; 1908 goto failed_enable;
1831 } 1909 }
@@ -1844,7 +1922,9 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1844 mem_base = csr_base + csr_len; 1922 mem_base = csr_base + csr_len;
1845 mem_len = csr_len; 1923 mem_len = csr_len;
1846 nand_dbg_print(NAND_DBG_WARN, 1924 nand_dbg_print(NAND_DBG_WARN,
1847 "Spectra: No second BAR for PCI device; assuming %08Lx\n", 1925 "Spectra: No second"
1926 " BAR for PCI device;"
1927 " assuming %08Lx\n",
1848 (uint64_t)csr_base); 1928 (uint64_t)csr_base);
1849 } 1929 }
1850 } 1930 }
@@ -1856,8 +1936,10 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1856 printk(KERN_ERR "Spectra: no usable DMA configuration\n"); 1936 printk(KERN_ERR "Spectra: no usable DMA configuration\n");
1857 goto failed_enable; 1937 goto failed_enable;
1858 } 1938 }
1859 denali->buf.dma_buf = pci_map_single(dev, denali->buf.buf, DENALI_BUF_SIZE, 1939 denali->buf.dma_buf =
1860 PCI_DMA_BIDIRECTIONAL); 1940 pci_map_single(dev, denali->buf.buf,
1941 DENALI_BUF_SIZE,
1942 PCI_DMA_BIDIRECTIONAL);
1861 1943
1862 if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) { 1944 if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) {
1863 printk(KERN_ERR "Spectra: failed to map DMA buffer\n"); 1945 printk(KERN_ERR "Spectra: failed to map DMA buffer\n");
@@ -1997,7 +2079,8 @@ static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1997 2079
1998 ret = add_mtd_device(&denali->mtd); 2080 ret = add_mtd_device(&denali->mtd);
1999 if (ret) { 2081 if (ret) {
2000 printk(KERN_ERR "Spectra: Failed to register MTD device: %d\n", ret); 2082 printk(KERN_ERR "Spectra: Failed to register"
2083 " MTD device: %d\n", ret);
2001 goto failed_nand; 2084 goto failed_nand;
2002 } 2085 }
2003 return 0; 2086 return 0;
@@ -2051,7 +2134,8 @@ static struct pci_driver denali_pci_driver = {
2051 2134
2052static int __devinit denali_init(void) 2135static int __devinit denali_init(void)
2053{ 2136{
2054 printk(KERN_INFO "Spectra MTD driver built on %s @ %s\n", __DATE__, __TIME__); 2137 printk(KERN_INFO "Spectra MTD driver built on %s @ %s\n",
2138 __DATE__, __TIME__);
2055 return pci_register_driver(&denali_pci_driver); 2139 return pci_register_driver(&denali_pci_driver);
2056} 2140}
2057 2141
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 04:02:51 -0500