diff options
-rw-r--r-- | arch/sh/boards/renesas/rts7751r2d/irq.c | 10 | ||||
-rw-r--r-- | arch/sh/cchips/voyagergx/irq.c | 4 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh3/setup-sh7705.c | 10 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh3/setup-sh770x.c | 10 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh3/setup-sh7710.c | 10 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4/setup-sh7750.c | 26 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4/setup-sh7760.c | 12 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7722.c | 12 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7780.c | 24 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-sh7785.c | 21 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/setup-shx3.c | 16 | ||||
-rw-r--r-- | include/asm-sh/hw_irq.h | 6 |
12 files changed, 79 insertions, 82 deletions
diff --git a/arch/sh/boards/renesas/rts7751r2d/irq.c b/arch/sh/boards/renesas/rts7751r2d/irq.c index 878852158b45..12aae0ce1d11 100644 --- a/arch/sh/boards/renesas/rts7751r2d/irq.c +++ b/arch/sh/boards/renesas/rts7751r2d/irq.c | |||
@@ -71,9 +71,8 @@ static unsigned char irl2irq_r2d_1[R2D_NR_IRL] __initdata = { | |||
71 | IRQ_TP, | 71 | IRQ_TP, |
72 | }; | 72 | }; |
73 | 73 | ||
74 | static __initdata DECLARE_INTC_DESC(intc_desc_r2d_1, "r2d-1", | 74 | static DECLARE_INTC_DESC(intc_desc_r2d_1, "r2d-1", vectors_r2d_1, |
75 | vectors_r2d_1, NULL, NULL, | 75 | NULL, NULL, mask_registers_r2d_1, NULL, NULL); |
76 | mask_registers_r2d_1, NULL, NULL); | ||
77 | 76 | ||
78 | #endif /* CONFIG_RTS7751R2D_1 */ | 77 | #endif /* CONFIG_RTS7751R2D_1 */ |
79 | 78 | ||
@@ -110,9 +109,8 @@ static unsigned char irl2irq_r2d_plus[R2D_NR_IRL] __initdata = { | |||
110 | IRQ_TP, | 109 | IRQ_TP, |
111 | }; | 110 | }; |
112 | 111 | ||
113 | static __initdata DECLARE_INTC_DESC(intc_desc_r2d_plus, "r2d-plus", | 112 | static DECLARE_INTC_DESC(intc_desc_r2d_plus, "r2d-plus", vectors_r2d_plus, |
114 | vectors_r2d_plus, NULL, NULL, | 113 | NULL, NULL, mask_registers_r2d_plus, NULL, NULL); |
115 | mask_registers_r2d_plus, NULL, NULL); | ||
116 | 114 | ||
117 | #endif /* CONFIG_RTS7751R2D_PLUS */ | 115 | #endif /* CONFIG_RTS7751R2D_PLUS */ |
118 | 116 | ||
diff --git a/arch/sh/cchips/voyagergx/irq.c b/arch/sh/cchips/voyagergx/irq.c index 2d3620cc92be..ade303876841 100644 --- a/arch/sh/cchips/voyagergx/irq.c +++ b/arch/sh/cchips/voyagergx/irq.c | |||
@@ -33,7 +33,7 @@ enum { | |||
33 | UH, TWOD, ZD, PV, CI, | 33 | UH, TWOD, ZD, PV, CI, |
34 | }; | 34 | }; |
35 | 35 | ||
36 | static struct intc_vect vectors[] = { | 36 | static struct intc_vect vectors[] __initdata = { |
37 | INTC_IRQ(UP, IRQ_SM501_UP), INTC_IRQ(G54, IRQ_SM501_G54), | 37 | INTC_IRQ(UP, IRQ_SM501_UP), INTC_IRQ(G54, IRQ_SM501_G54), |
38 | INTC_IRQ(G53, IRQ_SM501_G53), INTC_IRQ(G52, IRQ_SM501_G52), | 38 | INTC_IRQ(G53, IRQ_SM501_G53), INTC_IRQ(G52, IRQ_SM501_G52), |
39 | INTC_IRQ(G51, IRQ_SM501_G51), INTC_IRQ(G50, IRQ_SM501_G50), | 39 | INTC_IRQ(G51, IRQ_SM501_G51), INTC_IRQ(G50, IRQ_SM501_G50), |
@@ -49,7 +49,7 @@ static struct intc_vect vectors[] = { | |||
49 | INTC_IRQ(PV, IRQ_SM501_PV), INTC_IRQ(CI, IRQ_SM501_CI), | 49 | INTC_IRQ(PV, IRQ_SM501_PV), INTC_IRQ(CI, IRQ_SM501_CI), |
50 | }; | 50 | }; |
51 | 51 | ||
52 | static struct intc_mask_reg mask_registers[] = { | 52 | static struct intc_mask_reg mask_registers[] __initdata = { |
53 | { VOYAGER_INT_MASK, 0, 32, /* "Interrupt Mask", MMIO_base + 0x30 */ | 53 | { VOYAGER_INT_MASK, 0, 32, /* "Interrupt Mask", MMIO_base + 0x30 */ |
54 | { UP, G54, G53, G52, G51, G50, G49, G48, | 54 | { UP, G54, G53, G52, G51, G50, G49, G48, |
55 | I2C, PW, 0, DMA, PCI, I2S, AC, US, | 55 | I2C, PW, 0, DMA, PCI, I2S, AC, US, |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c index a1b342e170c6..f6c65f2659e9 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c | |||
@@ -36,7 +36,7 @@ enum { | |||
36 | RTC, TMU2, DMAC, USB, SCIF2, SCIF0, | 36 | RTC, TMU2, DMAC, USB, SCIF2, SCIF0, |
37 | }; | 37 | }; |
38 | 38 | ||
39 | static struct intc_vect vectors[] = { | 39 | static struct intc_vect vectors[] __initdata = { |
40 | INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), | 40 | INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), |
41 | INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), | 41 | INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720), |
42 | INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), | 42 | INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), |
@@ -57,7 +57,7 @@ static struct intc_vect vectors[] = { | |||
57 | INTC_VECT(REF_RCMI, 0x580), | 57 | INTC_VECT(REF_RCMI, 0x580), |
58 | }; | 58 | }; |
59 | 59 | ||
60 | static struct intc_group groups[] = { | 60 | static struct intc_group groups[] __initdata = { |
61 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), | 61 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), |
62 | INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), | 62 | INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), |
63 | INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3), | 63 | INTC_GROUP(DMAC, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3), |
@@ -66,13 +66,13 @@ static struct intc_group groups[] = { | |||
66 | INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI), | 66 | INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI), |
67 | }; | 67 | }; |
68 | 68 | ||
69 | static struct intc_prio priorities[] = { | 69 | static struct intc_prio priorities[] __initdata = { |
70 | INTC_PRIO(DMAC, 7), | 70 | INTC_PRIO(DMAC, 7), |
71 | INTC_PRIO(SCIF2, 3), | 71 | INTC_PRIO(SCIF2, 3), |
72 | INTC_PRIO(SCIF0, 3), | 72 | INTC_PRIO(SCIF0, 3), |
73 | }; | 73 | }; |
74 | 74 | ||
75 | static struct intc_prio_reg prio_registers[] = { | 75 | static struct intc_prio_reg prio_registers[] __initdata = { |
76 | { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, | 76 | { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, |
77 | { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } }, | 77 | { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, 0, 0 } }, |
78 | { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, | 78 | { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, |
@@ -87,7 +87,7 @@ static struct intc_prio_reg prio_registers[] = { | |||
87 | static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, groups, | 87 | static DECLARE_INTC_DESC(intc_desc, "sh7705", vectors, groups, |
88 | priorities, NULL, prio_registers, NULL); | 88 | priorities, NULL, prio_registers, NULL); |
89 | 89 | ||
90 | static struct intc_vect vectors_irq[] = { | 90 | static struct intc_vect vectors_irq[] __initdata = { |
91 | INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), | 91 | INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), |
92 | INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), | 92 | INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), |
93 | }; | 93 | }; |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c index 2980c44ffb2f..60b04b1f9453 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c | |||
@@ -39,7 +39,7 @@ enum { | |||
39 | RTC, REF, TMU2, DMAC, SCI, SCIF2, SCIF0, | 39 | RTC, REF, TMU2, DMAC, SCI, SCIF2, SCIF0, |
40 | }; | 40 | }; |
41 | 41 | ||
42 | static struct intc_vect vectors[] = { | 42 | static struct intc_vect vectors[] __initdata = { |
43 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), | 43 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
44 | INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), | 44 | INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), |
45 | INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), | 45 | INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), |
@@ -71,7 +71,7 @@ static struct intc_vect vectors[] = { | |||
71 | #endif | 71 | #endif |
72 | }; | 72 | }; |
73 | 73 | ||
74 | static struct intc_group groups[] = { | 74 | static struct intc_group groups[] __initdata = { |
75 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), | 75 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), |
76 | INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), | 76 | INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), |
77 | INTC_GROUP(REF, REF_RCMI, REF_ROVI), | 77 | INTC_GROUP(REF, REF_RCMI, REF_ROVI), |
@@ -81,14 +81,14 @@ static struct intc_group groups[] = { | |||
81 | INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI), | 81 | INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI), |
82 | }; | 82 | }; |
83 | 83 | ||
84 | static struct intc_prio priorities[] = { | 84 | static struct intc_prio priorities[] __initdata = { |
85 | INTC_PRIO(DMAC, 7), | 85 | INTC_PRIO(DMAC, 7), |
86 | INTC_PRIO(SCI, 3), | 86 | INTC_PRIO(SCI, 3), |
87 | INTC_PRIO(SCIF2, 3), | 87 | INTC_PRIO(SCIF2, 3), |
88 | INTC_PRIO(SCIF0, 3), | 88 | INTC_PRIO(SCIF0, 3), |
89 | }; | 89 | }; |
90 | 90 | ||
91 | static struct intc_prio_reg prio_registers[] = { | 91 | static struct intc_prio_reg prio_registers[] __initdata = { |
92 | { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, | 92 | { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, |
93 | { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } }, | 93 | { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, SCI, 0 } }, |
94 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ | 94 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
@@ -114,7 +114,7 @@ static DECLARE_INTC_DESC(intc_desc, "sh770x", vectors, groups, | |||
114 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ | 114 | #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \ |
115 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ | 115 | defined(CONFIG_CPU_SUBTYPE_SH7707) || \ |
116 | defined(CONFIG_CPU_SUBTYPE_SH7709) | 116 | defined(CONFIG_CPU_SUBTYPE_SH7709) |
117 | static struct intc_vect vectors_irq[] = { | 117 | static struct intc_vect vectors_irq[] __initdata = { |
118 | INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), | 118 | INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), |
119 | INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), | 119 | INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), |
120 | }; | 120 | }; |
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7710.c b/arch/sh/kernel/cpu/sh3/setup-sh7710.c index 5aa77710e42b..84e5629fa841 100644 --- a/arch/sh/kernel/cpu/sh3/setup-sh7710.c +++ b/arch/sh/kernel/cpu/sh3/setup-sh7710.c | |||
@@ -37,7 +37,7 @@ enum { | |||
37 | RTC, DMAC1, SCIF0, SCIF1, DMAC2, SIOF0, SIOF1, | 37 | RTC, DMAC1, SCIF0, SCIF1, DMAC2, SIOF0, SIOF1, |
38 | }; | 38 | }; |
39 | 39 | ||
40 | static struct intc_vect vectors[] = { | 40 | static struct intc_vect vectors[] __initdata = { |
41 | INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), | 41 | INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), |
42 | INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), | 42 | INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820), |
43 | INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), | 43 | INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860), |
@@ -63,7 +63,7 @@ static struct intc_vect vectors[] = { | |||
63 | INTC_VECT(REF, 0x580), | 63 | INTC_VECT(REF, 0x580), |
64 | }; | 64 | }; |
65 | 65 | ||
66 | static struct intc_group groups[] = { | 66 | static struct intc_group groups[] __initdata = { |
67 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), | 67 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), |
68 | INTC_GROUP(DMAC1, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3), | 68 | INTC_GROUP(DMAC1, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3), |
69 | INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), | 69 | INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), |
@@ -73,7 +73,7 @@ static struct intc_group groups[] = { | |||
73 | INTC_GROUP(SIOF1, SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI), | 73 | INTC_GROUP(SIOF1, SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI), |
74 | }; | 74 | }; |
75 | 75 | ||
76 | static struct intc_prio priorities[] = { | 76 | static struct intc_prio priorities[] __initdata = { |
77 | INTC_PRIO(DMAC1, 7), | 77 | INTC_PRIO(DMAC1, 7), |
78 | INTC_PRIO(DMAC2, 7), | 78 | INTC_PRIO(DMAC2, 7), |
79 | INTC_PRIO(SCIF0, 3), | 79 | INTC_PRIO(SCIF0, 3), |
@@ -85,7 +85,7 @@ static struct intc_prio priorities[] = { | |||
85 | INTC_PRIO(EDMAC2, 5), | 85 | INTC_PRIO(EDMAC2, 5), |
86 | }; | 86 | }; |
87 | 87 | ||
88 | static struct intc_prio_reg prio_registers[] = { | 88 | static struct intc_prio_reg prio_registers[] __initdata = { |
89 | { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, | 89 | { 0xfffffee2, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, |
90 | { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, | 90 | { 0xfffffee4, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, |
91 | { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, | 91 | { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } }, |
@@ -103,7 +103,7 @@ static struct intc_prio_reg prio_registers[] = { | |||
103 | static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups, | 103 | static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups, |
104 | priorities, NULL, prio_registers, NULL); | 104 | priorities, NULL, prio_registers, NULL); |
105 | 105 | ||
106 | static struct intc_vect vectors_irq[] = { | 106 | static struct intc_vect vectors_irq[] __initdata = { |
107 | INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), | 107 | INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), |
108 | INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), | 108 | INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), |
109 | }; | 109 | }; |
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c index 062c3c1b2431..523f68a9ce0e 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c | |||
@@ -104,7 +104,7 @@ enum { | |||
104 | DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, | 104 | DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, |
105 | }; | 105 | }; |
106 | 106 | ||
107 | static struct intc_vect vectors[] = { | 107 | static struct intc_vect vectors[] __initdata = { |
108 | INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), | 108 | INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), |
109 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), | 109 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
110 | INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), | 110 | INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), |
@@ -118,7 +118,7 @@ static struct intc_vect vectors[] = { | |||
118 | INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), | 118 | INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), |
119 | }; | 119 | }; |
120 | 120 | ||
121 | static struct intc_group groups[] = { | 121 | static struct intc_group groups[] __initdata = { |
122 | INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), | 122 | INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), |
123 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), | 123 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), |
124 | INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), | 124 | INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), |
@@ -126,13 +126,13 @@ static struct intc_group groups[] = { | |||
126 | INTC_GROUP(REF, REF_RCMI, REF_ROVI), | 126 | INTC_GROUP(REF, REF_RCMI, REF_ROVI), |
127 | }; | 127 | }; |
128 | 128 | ||
129 | static struct intc_prio priorities[] = { | 129 | static struct intc_prio priorities[] __initdata = { |
130 | INTC_PRIO(SCIF, 3), | 130 | INTC_PRIO(SCIF, 3), |
131 | INTC_PRIO(SCI1, 3), | 131 | INTC_PRIO(SCI1, 3), |
132 | INTC_PRIO(DMAC, 7), | 132 | INTC_PRIO(DMAC, 7), |
133 | }; | 133 | }; |
134 | 134 | ||
135 | static struct intc_prio_reg prio_registers[] = { | 135 | static struct intc_prio_reg prio_registers[] __initdata = { |
136 | { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, | 136 | { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, |
137 | { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, | 137 | { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, |
138 | { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, | 138 | { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, |
@@ -150,13 +150,13 @@ static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups, | |||
150 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ | 150 | defined(CONFIG_CPU_SUBTYPE_SH7750S) || \ |
151 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | 151 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ |
152 | defined(CONFIG_CPU_SUBTYPE_SH7091) | 152 | defined(CONFIG_CPU_SUBTYPE_SH7091) |
153 | static struct intc_vect vectors_dma4[] = { | 153 | static struct intc_vect vectors_dma4[] __initdata = { |
154 | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), | 154 | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), |
155 | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), | 155 | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), |
156 | INTC_VECT(DMAC_DMAE, 0x6c0), | 156 | INTC_VECT(DMAC_DMAE, 0x6c0), |
157 | }; | 157 | }; |
158 | 158 | ||
159 | static struct intc_group groups_dma4[] = { | 159 | static struct intc_group groups_dma4[] __initdata = { |
160 | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, | 160 | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, |
161 | DMAC_DMTE3, DMAC_DMAE), | 161 | DMAC_DMTE3, DMAC_DMAE), |
162 | }; | 162 | }; |
@@ -168,7 +168,7 @@ static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4", | |||
168 | 168 | ||
169 | /* SH7750R and SH7751R both have 8-channel DMA controllers */ | 169 | /* SH7750R and SH7751R both have 8-channel DMA controllers */ |
170 | #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R) | 170 | #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R) |
171 | static struct intc_vect vectors_dma8[] = { | 171 | static struct intc_vect vectors_dma8[] __initdata = { |
172 | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), | 172 | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), |
173 | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), | 173 | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), |
174 | INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), | 174 | INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), |
@@ -176,7 +176,7 @@ static struct intc_vect vectors_dma8[] = { | |||
176 | INTC_VECT(DMAC_DMAE, 0x6c0), | 176 | INTC_VECT(DMAC_DMAE, 0x6c0), |
177 | }; | 177 | }; |
178 | 178 | ||
179 | static struct intc_group groups_dma8[] = { | 179 | static struct intc_group groups_dma8[] __initdata = { |
180 | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, | 180 | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, |
181 | DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, | 181 | DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, |
182 | DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), | 182 | DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), |
@@ -191,11 +191,11 @@ static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8", | |||
191 | #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ | 191 | #if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \ |
192 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ | 192 | defined(CONFIG_CPU_SUBTYPE_SH7751) || \ |
193 | defined(CONFIG_CPU_SUBTYPE_SH7751R) | 193 | defined(CONFIG_CPU_SUBTYPE_SH7751R) |
194 | static struct intc_vect vectors_tmu34[] = { | 194 | static struct intc_vect vectors_tmu34[] __initdata = { |
195 | INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), | 195 | INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), |
196 | }; | 196 | }; |
197 | 197 | ||
198 | static struct intc_mask_reg mask_registers[] = { | 198 | static struct intc_mask_reg mask_registers[] __initdata = { |
199 | { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ | 199 | { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ |
200 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 200 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
201 | 0, 0, 0, 0, 0, 0, TMU4, TMU3, | 201 | 0, 0, 0, 0, 0, 0, TMU4, TMU3, |
@@ -210,7 +210,7 @@ static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34", | |||
210 | #endif | 210 | #endif |
211 | 211 | ||
212 | /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ | 212 | /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ |
213 | static struct intc_vect vectors_irlm[] = { | 213 | static struct intc_vect vectors_irlm[] __initdata = { |
214 | INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), | 214 | INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), |
215 | INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), | 215 | INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), |
216 | }; | 216 | }; |
@@ -220,14 +220,14 @@ static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL, | |||
220 | 220 | ||
221 | /* SH7751 and SH7751R both have PCI */ | 221 | /* SH7751 and SH7751R both have PCI */ |
222 | #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R) | 222 | #if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R) |
223 | static struct intc_vect vectors_pci[] = { | 223 | static struct intc_vect vectors_pci[] __initdata = { |
224 | INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), | 224 | INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), |
225 | INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), | 225 | INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), |
226 | INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), | 226 | INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), |
227 | INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), | 227 | INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), |
228 | }; | 228 | }; |
229 | 229 | ||
230 | static struct intc_group groups_pci[] = { | 230 | static struct intc_group groups_pci[] __initdata = { |
231 | INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, | 231 | INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, |
232 | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), | 232 | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), |
233 | }; | 233 | }; |
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c index 6b4e48cbe7ff..7a898cb1d940 100644 --- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c +++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c | |||
@@ -43,7 +43,7 @@ enum { | |||
43 | DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF, | 43 | DMAC, DMABRG, SCIF0, SCIF1, SCIF2, SIM, MMCIF, TMU2, REF, |
44 | }; | 44 | }; |
45 | 45 | ||
46 | static struct intc_vect vectors[] = { | 46 | static struct intc_vect vectors[] __initdata = { |
47 | INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), | 47 | INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), |
48 | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), | 48 | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), |
49 | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), | 49 | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), |
@@ -78,7 +78,7 @@ static struct intc_vect vectors[] = { | |||
78 | INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), | 78 | INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), |
79 | }; | 79 | }; |
80 | 80 | ||
81 | static struct intc_group groups[] = { | 81 | static struct intc_group groups[] __initdata = { |
82 | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, | 82 | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, |
83 | DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, | 83 | DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, |
84 | DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), | 84 | DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), |
@@ -92,7 +92,7 @@ static struct intc_group groups[] = { | |||
92 | INTC_GROUP(REF, REF_RCMI, REF_ROVI), | 92 | INTC_GROUP(REF, REF_RCMI, REF_ROVI), |
93 | }; | 93 | }; |
94 | 94 | ||
95 | static struct intc_prio priorities[] = { | 95 | static struct intc_prio priorities[] __initdata = { |
96 | INTC_PRIO(SCIF0, 3), | 96 | INTC_PRIO(SCIF0, 3), |
97 | INTC_PRIO(SCIF1, 3), | 97 | INTC_PRIO(SCIF1, 3), |
98 | INTC_PRIO(SCIF2, 3), | 98 | INTC_PRIO(SCIF2, 3), |
@@ -101,7 +101,7 @@ static struct intc_prio priorities[] = { | |||
101 | INTC_PRIO(DMABRG, 13), | 101 | INTC_PRIO(DMABRG, 13), |
102 | }; | 102 | }; |
103 | 103 | ||
104 | static struct intc_mask_reg mask_registers[] = { | 104 | static struct intc_mask_reg mask_registers[] __initdata = { |
105 | { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ | 105 | { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ |
106 | { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21, | 106 | { IRQ4, IRQ5, IRQ6, IRQ7, 0, 0, HCAN20, HCAN21, |
107 | SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC, | 107 | SSI0, SSI1, HAC0, HAC1, I2C0, I2C1, USB, LCDC, |
@@ -117,7 +117,7 @@ static struct intc_mask_reg mask_registers[] = { | |||
117 | 0, MFI, 0, 0, 0, 0, ADC, CMT, } }, | 117 | 0, MFI, 0, 0, 0, 0, ADC, CMT, } }, |
118 | }; | 118 | }; |
119 | 119 | ||
120 | static struct intc_prio_reg prio_registers[] = { | 120 | static struct intc_prio_reg prio_registers[] __initdata = { |
121 | { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, | 121 | { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } }, |
122 | { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, | 122 | { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } }, |
123 | { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } }, | 123 | { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, 0, HUDI } }, |
@@ -134,7 +134,7 @@ static struct intc_prio_reg prio_registers[] = { | |||
134 | static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups, | 134 | static DECLARE_INTC_DESC(intc_desc, "sh7760", vectors, groups, |
135 | priorities, mask_registers, prio_registers, NULL); | 135 | priorities, mask_registers, prio_registers, NULL); |
136 | 136 | ||
137 | static struct intc_vect vectors_irq[] = { | 137 | static struct intc_vect vectors_irq[] __initdata = { |
138 | INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), | 138 | INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), |
139 | INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), | 139 | INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), |
140 | }; | 140 | }; |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c index ae63635cf1ef..55f66104431d 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c | |||
@@ -84,7 +84,7 @@ enum { | |||
84 | SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, | 84 | SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI, |
85 | }; | 85 | }; |
86 | 86 | ||
87 | static struct intc_vect vectors[] = { | 87 | static struct intc_vect vectors[] __initdata = { |
88 | INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), | 88 | INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620), |
89 | INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), | 89 | INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660), |
90 | INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), | 90 | INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0), |
@@ -117,7 +117,7 @@ static struct intc_vect vectors[] = { | |||
117 | INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), | 117 | INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580), |
118 | }; | 118 | }; |
119 | 119 | ||
120 | static struct intc_group groups[] = { | 120 | static struct intc_group groups[] __initdata = { |
121 | INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), | 121 | INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI), |
122 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), | 122 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), |
123 | INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), | 123 | INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3), |
@@ -130,7 +130,7 @@ static struct intc_group groups[] = { | |||
130 | INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), | 130 | INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3), |
131 | }; | 131 | }; |
132 | 132 | ||
133 | static struct intc_prio priorities[] = { | 133 | static struct intc_prio priorities[] __initdata = { |
134 | INTC_PRIO(SCIF0, 3), | 134 | INTC_PRIO(SCIF0, 3), |
135 | INTC_PRIO(SCIF1, 3), | 135 | INTC_PRIO(SCIF1, 3), |
136 | INTC_PRIO(SCIF2, 3), | 136 | INTC_PRIO(SCIF2, 3), |
@@ -138,7 +138,7 @@ static struct intc_prio priorities[] = { | |||
138 | INTC_PRIO(TMU1, 2), | 138 | INTC_PRIO(TMU1, 2), |
139 | }; | 139 | }; |
140 | 140 | ||
141 | static struct intc_mask_reg mask_registers[] = { | 141 | static struct intc_mask_reg mask_registers[] __initdata = { |
142 | { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ | 142 | { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */ |
143 | { } }, | 143 | { } }, |
144 | { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ | 144 | { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */ |
@@ -168,7 +168,7 @@ static struct intc_mask_reg mask_registers[] = { | |||
168 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | 168 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
169 | }; | 169 | }; |
170 | 170 | ||
171 | static struct intc_prio_reg prio_registers[] = { | 171 | static struct intc_prio_reg prio_registers[] __initdata = { |
172 | { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } }, | 172 | { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } }, |
173 | { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, | 173 | { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } }, |
174 | { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, | 174 | { 0xa4080008, 0, 16, 4, /* IPRC */ { } }, |
@@ -185,7 +185,7 @@ static struct intc_prio_reg prio_registers[] = { | |||
185 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | 185 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
186 | }; | 186 | }; |
187 | 187 | ||
188 | static struct intc_sense_reg sense_registers[] = { | 188 | static struct intc_sense_reg sense_registers[] __initdata = { |
189 | { 0xa414001c, 16, 2, /* ICR1 */ | 189 | { 0xa414001c, 16, 2, /* ICR1 */ |
190 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | 190 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
191 | }; | 191 | }; |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c index c9965c0dde6d..d84c4575fc0a 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c | |||
@@ -114,7 +114,7 @@ enum { | |||
114 | PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO, | 114 | PCIC5, SCIF1, MMCIF, TMU345, FLCTL, GPIO, |
115 | }; | 115 | }; |
116 | 116 | ||
117 | static struct intc_vect vectors[] = { | 117 | static struct intc_vect vectors[] __initdata = { |
118 | INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), | 118 | INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), |
119 | INTC_VECT(RTC_CUI, 0x4c0), | 119 | INTC_VECT(RTC_CUI, 0x4c0), |
120 | INTC_VECT(WDT, 0x560), | 120 | INTC_VECT(WDT, 0x560), |
@@ -150,7 +150,7 @@ static struct intc_vect vectors[] = { | |||
150 | INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0), | 150 | INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0), |
151 | }; | 151 | }; |
152 | 152 | ||
153 | static struct intc_group groups[] = { | 153 | static struct intc_group groups[] __initdata = { |
154 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), | 154 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), |
155 | INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), | 155 | INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), |
156 | INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, | 156 | INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, |
@@ -167,12 +167,12 @@ static struct intc_group groups[] = { | |||
167 | INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3), | 167 | INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3), |
168 | }; | 168 | }; |
169 | 169 | ||
170 | static struct intc_prio priorities[] = { | 170 | static struct intc_prio priorities[] __initdata = { |
171 | INTC_PRIO(SCIF0, 3), | 171 | INTC_PRIO(SCIF0, 3), |
172 | INTC_PRIO(SCIF1, 3), | 172 | INTC_PRIO(SCIF1, 3), |
173 | }; | 173 | }; |
174 | 174 | ||
175 | static struct intc_mask_reg mask_registers[] = { | 175 | static struct intc_mask_reg mask_registers[] __initdata = { |
176 | { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ | 176 | { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ |
177 | { 0, 0, 0, 0, 0, 0, GPIO, FLCTL, | 177 | { 0, 0, 0, 0, 0, 0, GPIO, FLCTL, |
178 | SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB, | 178 | SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB, |
@@ -180,7 +180,7 @@ static struct intc_mask_reg mask_registers[] = { | |||
180 | HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } }, | 180 | HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } }, |
181 | }; | 181 | }; |
182 | 182 | ||
183 | static struct intc_prio_reg prio_registers[] = { | 183 | static struct intc_prio_reg prio_registers[] __initdata = { |
184 | { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, | 184 | { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, |
185 | TMU2, TMU2_TICPI } }, | 185 | TMU2, TMU2_TICPI } }, |
186 | { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } }, | 186 | { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } }, |
@@ -199,24 +199,24 @@ static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups, priorities, | |||
199 | 199 | ||
200 | /* Support for external interrupt pins in IRQ mode */ | 200 | /* Support for external interrupt pins in IRQ mode */ |
201 | 201 | ||
202 | static struct intc_vect irq_vectors[] = { | 202 | static struct intc_vect irq_vectors[] __initdata = { |
203 | INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), | 203 | INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), |
204 | INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), | 204 | INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), |
205 | INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), | 205 | INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), |
206 | INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), | 206 | INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), |
207 | }; | 207 | }; |
208 | 208 | ||
209 | static struct intc_mask_reg irq_mask_registers[] = { | 209 | static struct intc_mask_reg irq_mask_registers[] __initdata = { |
210 | { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ | 210 | { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ |
211 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | 211 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
212 | }; | 212 | }; |
213 | 213 | ||
214 | static struct intc_prio_reg irq_prio_registers[] = { | 214 | static struct intc_prio_reg irq_prio_registers[] __initdata = { |
215 | { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, | 215 | { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, |
216 | IRQ4, IRQ5, IRQ6, IRQ7 } }, | 216 | IRQ4, IRQ5, IRQ6, IRQ7 } }, |
217 | }; | 217 | }; |
218 | 218 | ||
219 | static struct intc_sense_reg irq_sense_registers[] = { | 219 | static struct intc_sense_reg irq_sense_registers[] __initdata = { |
220 | { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, | 220 | { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, |
221 | IRQ4, IRQ5, IRQ6, IRQ7 } }, | 221 | IRQ4, IRQ5, IRQ6, IRQ7 } }, |
222 | }; | 222 | }; |
@@ -227,7 +227,7 @@ static DECLARE_INTC_DESC(intc_irq_desc, "sh7780-irq", irq_vectors, | |||
227 | 227 | ||
228 | /* External interrupt pins in IRL mode */ | 228 | /* External interrupt pins in IRL mode */ |
229 | 229 | ||
230 | static struct intc_vect irl_vectors[] = { | 230 | static struct intc_vect irl_vectors[] __initdata = { |
231 | INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), | 231 | INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), |
232 | INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), | 232 | INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), |
233 | INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), | 233 | INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), |
@@ -238,7 +238,7 @@ static struct intc_vect irl_vectors[] = { | |||
238 | INTC_VECT(IRL_HHHL, 0x3c0), | 238 | INTC_VECT(IRL_HHHL, 0x3c0), |
239 | }; | 239 | }; |
240 | 240 | ||
241 | static struct intc_mask_reg irl3210_mask_registers[] = { | 241 | static struct intc_mask_reg irl3210_mask_registers[] __initdata = { |
242 | { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */ | 242 | { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */ |
243 | { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, | 243 | { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, |
244 | IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, | 244 | IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, |
@@ -246,7 +246,7 @@ static struct intc_mask_reg irl3210_mask_registers[] = { | |||
246 | IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, | 246 | IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, |
247 | }; | 247 | }; |
248 | 248 | ||
249 | static struct intc_mask_reg irl7654_mask_registers[] = { | 249 | static struct intc_mask_reg irl7654_mask_registers[] __initdata = { |
250 | { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */ | 250 | { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */ |
251 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 251 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
252 | IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, | 252 | IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c index a33d6a54c03d..a595203f74c6 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c | |||
@@ -117,7 +117,7 @@ enum { | |||
117 | PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO | 117 | PCIC5, MMCIF, GDTA, TMU345, FLCTL, GPIO |
118 | }; | 118 | }; |
119 | 119 | ||
120 | static struct intc_vect vectors[] = { | 120 | static struct intc_vect vectors[] __initdata = { |
121 | INTC_VECT(WDT, 0x560), | 121 | INTC_VECT(WDT, 0x560), |
122 | INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), | 122 | INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0), |
123 | INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), | 123 | INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0), |
@@ -158,7 +158,7 @@ static struct intc_vect vectors[] = { | |||
158 | INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0), | 158 | INTC_VECT(GPIOI2, 0xfc0), INTC_VECT(GPIOI3, 0xfe0), |
159 | }; | 159 | }; |
160 | 160 | ||
161 | static struct intc_group groups[] = { | 161 | static struct intc_group groups[] __initdata = { |
162 | INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), | 162 | INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), |
163 | INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, | 163 | INTC_GROUP(DMAC0, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, |
164 | DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE), | 164 | DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE), |
@@ -175,7 +175,7 @@ static struct intc_group groups[] = { | |||
175 | INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3), | 175 | INTC_GROUP(GPIO, GPIOI0, GPIOI1, GPIOI2, GPIOI3), |
176 | }; | 176 | }; |
177 | 177 | ||
178 | static struct intc_prio priorities[] = { | 178 | static struct intc_prio priorities[] __initdata = { |
179 | INTC_PRIO(SCIF0, 3), | 179 | INTC_PRIO(SCIF0, 3), |
180 | INTC_PRIO(SCIF1, 3), | 180 | INTC_PRIO(SCIF1, 3), |
181 | INTC_PRIO(SCIF2, 3), | 181 | INTC_PRIO(SCIF2, 3), |
@@ -184,7 +184,7 @@ static struct intc_prio priorities[] = { | |||
184 | INTC_PRIO(SCIF5, 3), | 184 | INTC_PRIO(SCIF5, 3), |
185 | }; | 185 | }; |
186 | 186 | ||
187 | static struct intc_mask_reg mask_registers[] = { | 187 | static struct intc_mask_reg mask_registers[] __initdata = { |
188 | { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ | 188 | { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ |
189 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | 189 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, |
190 | 190 | ||
@@ -205,7 +205,7 @@ static struct intc_mask_reg mask_registers[] = { | |||
205 | SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } }, | 205 | SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } }, |
206 | }; | 206 | }; |
207 | 207 | ||
208 | static struct intc_prio_reg prio_registers[] = { | 208 | static struct intc_prio_reg prio_registers[] __initdata = { |
209 | { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, | 209 | { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, |
210 | IRQ4, IRQ5, IRQ6, IRQ7 } }, | 210 | IRQ4, IRQ5, IRQ6, IRQ7 } }, |
211 | { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, | 211 | { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, |
@@ -227,20 +227,19 @@ static struct intc_prio_reg prio_registers[] = { | |||
227 | static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups, priorities, | 227 | static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups, priorities, |
228 | mask_registers, prio_registers, NULL); | 228 | mask_registers, prio_registers, NULL); |
229 | 229 | ||
230 | |||
231 | /* Support for external interrupt pins in IRQ mode */ | 230 | /* Support for external interrupt pins in IRQ mode */ |
232 | 231 | ||
233 | static struct intc_vect vectors_irq0123[] = { | 232 | static struct intc_vect vectors_irq0123[] __initdata = { |
234 | INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), | 233 | INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), |
235 | INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), | 234 | INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), |
236 | }; | 235 | }; |
237 | 236 | ||
238 | static struct intc_vect vectors_irq4567[] = { | 237 | static struct intc_vect vectors_irq4567[] __initdata = { |
239 | INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), | 238 | INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), |
240 | INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), | 239 | INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), |
241 | }; | 240 | }; |
242 | 241 | ||
243 | static struct intc_sense_reg sense_registers[] = { | 242 | static struct intc_sense_reg sense_registers[] __initdata = { |
244 | { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, | 243 | { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, |
245 | IRQ4, IRQ5, IRQ6, IRQ7 } }, | 244 | IRQ4, IRQ5, IRQ6, IRQ7 } }, |
246 | }; | 245 | }; |
@@ -255,7 +254,7 @@ static DECLARE_INTC_DESC(intc_desc_irq4567, "sh7785-irq4567", vectors_irq4567, | |||
255 | 254 | ||
256 | /* External interrupt pins in IRL mode */ | 255 | /* External interrupt pins in IRL mode */ |
257 | 256 | ||
258 | static struct intc_vect vectors_irl0123[] = { | 257 | static struct intc_vect vectors_irl0123[] __initdata = { |
259 | INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220), | 258 | INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220), |
260 | INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260), | 259 | INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260), |
261 | INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0), | 260 | INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0), |
@@ -266,7 +265,7 @@ static struct intc_vect vectors_irl0123[] = { | |||
266 | INTC_VECT(IRL0_HHHL, 0x3c0), | 265 | INTC_VECT(IRL0_HHHL, 0x3c0), |
267 | }; | 266 | }; |
268 | 267 | ||
269 | static struct intc_vect vectors_irl4567[] = { | 268 | static struct intc_vect vectors_irl4567[] __initdata = { |
270 | INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20), | 269 | INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20), |
271 | INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60), | 270 | INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60), |
272 | INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0), | 271 | INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0), |
diff --git a/arch/sh/kernel/cpu/sh4a/setup-shx3.c b/arch/sh/kernel/cpu/sh4a/setup-shx3.c index 3c8a2edff2c9..4cfd532086fa 100644 --- a/arch/sh/kernel/cpu/sh4a/setup-shx3.c +++ b/arch/sh/kernel/cpu/sh4a/setup-shx3.c | |||
@@ -97,7 +97,7 @@ enum { | |||
97 | DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3, | 97 | DMAC0, DMAC1, DTU0, DTU1, DTU2, DTU3, |
98 | }; | 98 | }; |
99 | 99 | ||
100 | static struct intc_vect vectors[] = { | 100 | static struct intc_vect vectors[] __initdata = { |
101 | INTC_VECT(HUDII, 0x3e0), | 101 | INTC_VECT(HUDII, 0x3e0), |
102 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), | 102 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), |
103 | INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460), | 103 | INTC_VECT(TMU2, 0x440), INTC_VECT(TMU3, 0x460), |
@@ -145,7 +145,7 @@ static struct intc_vect vectors[] = { | |||
145 | INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0), | 145 | INTC_VECT(INTICI6, 0xfc0), INTC_VECT(INTICI7, 0xfe0), |
146 | }; | 146 | }; |
147 | 147 | ||
148 | static struct intc_group groups[] = { | 148 | static struct intc_group groups[] __initdata = { |
149 | INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, | 149 | INTC_GROUP(IRL, IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, |
150 | IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, | 150 | IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, |
151 | IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, | 151 | IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, |
@@ -165,14 +165,14 @@ static struct intc_group groups[] = { | |||
165 | INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS), | 165 | INTC_GROUP(DTU3, DTU3_TEND, DTU3_AE, DTU3_TMISS), |
166 | }; | 166 | }; |
167 | 167 | ||
168 | static struct intc_prio priorities[] = { | 168 | static struct intc_prio priorities[] __initdata = { |
169 | INTC_PRIO(SCIF0, 3), | 169 | INTC_PRIO(SCIF0, 3), |
170 | INTC_PRIO(SCIF1, 3), | 170 | INTC_PRIO(SCIF1, 3), |
171 | INTC_PRIO(SCIF2, 3), | 171 | INTC_PRIO(SCIF2, 3), |
172 | INTC_PRIO(SCIF3, 3), | 172 | INTC_PRIO(SCIF3, 3), |
173 | }; | 173 | }; |
174 | 174 | ||
175 | static struct intc_mask_reg mask_registers[] = { | 175 | static struct intc_mask_reg mask_registers[] __initdata = { |
176 | { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */ | 176 | { 0xfe410030, 0xfe410050, 32, /* CnINTMSK0 / CnINTMSKCLR0 */ |
177 | { IRQ0, IRQ1, IRQ2, IRQ3 } }, | 177 | { IRQ0, IRQ1, IRQ2, IRQ3 } }, |
178 | { 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */ | 178 | { 0xfe410040, 0xfe410060, 32, /* CnINTMSK1 / CnINTMSKCLR1 */ |
@@ -197,7 +197,7 @@ static struct intc_mask_reg mask_registers[] = { | |||
197 | SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } }, | 197 | SCIF0_TXI, SCIF0_BRI, SCIF0_RXI, SCIF0_ERI } }, |
198 | }; | 198 | }; |
199 | 199 | ||
200 | static struct intc_prio_reg prio_registers[] = { | 200 | static struct intc_prio_reg prio_registers[] __initdata = { |
201 | { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, | 201 | { 0xfe410010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, |
202 | 202 | ||
203 | { 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4, | 203 | { 0xfe410800, 0, 32, 4, /* INT2PRI0 */ { 0, HUDII, TMU5, TMU4, |
@@ -222,12 +222,12 @@ static DECLARE_INTC_DESC(intc_desc, "shx3", vectors, groups, priorities, | |||
222 | mask_registers, prio_registers, NULL); | 222 | mask_registers, prio_registers, NULL); |
223 | 223 | ||
224 | /* Support for external interrupt pins in IRQ mode */ | 224 | /* Support for external interrupt pins in IRQ mode */ |
225 | static struct intc_vect vectors_irq[] = { | 225 | static struct intc_vect vectors_irq[] __initdata = { |
226 | INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), | 226 | INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), |
227 | INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), | 227 | INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), |
228 | }; | 228 | }; |
229 | 229 | ||
230 | static struct intc_sense_reg sense_registers[] = { | 230 | static struct intc_sense_reg sense_registers[] __initdata = { |
231 | { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, | 231 | { 0xfe41001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3 } }, |
232 | }; | 232 | }; |
233 | 233 | ||
@@ -236,7 +236,7 @@ static DECLARE_INTC_DESC(intc_desc_irq, "shx3-irq", vectors_irq, groups, | |||
236 | sense_registers); | 236 | sense_registers); |
237 | 237 | ||
238 | /* External interrupt pins in IRL mode */ | 238 | /* External interrupt pins in IRL mode */ |
239 | static struct intc_vect vectors_irl[] = { | 239 | static struct intc_vect vectors_irl[] __initdata = { |
240 | INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), | 240 | INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), |
241 | INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), | 241 | INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), |
242 | INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), | 242 | INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), |
diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h index 0e6a60304974..0c016e949931 100644 --- a/include/asm-sh/hw_irq.h +++ b/include/asm-sh/hw_irq.h | |||
@@ -42,10 +42,10 @@ struct intc_prio { | |||
42 | 42 | ||
43 | struct intc_group { | 43 | struct intc_group { |
44 | intc_enum enum_id; | 44 | intc_enum enum_id; |
45 | intc_enum *enum_ids; | 45 | intc_enum enum_ids[32]; |
46 | }; | 46 | }; |
47 | 47 | ||
48 | #define INTC_GROUP(enum_id, ids...) { enum_id, (intc_enum []) { ids, 0 } } | 48 | #define INTC_GROUP(enum_id, ids...) { enum_id, { ids } } |
49 | 49 | ||
50 | struct intc_mask_reg { | 50 | struct intc_mask_reg { |
51 | unsigned long set_reg, clr_reg, reg_width; | 51 | unsigned long set_reg, clr_reg, reg_width; |
@@ -81,7 +81,7 @@ struct intc_desc { | |||
81 | #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a) | 81 | #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a) |
82 | #define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \ | 82 | #define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \ |
83 | priorities, mask_regs, prio_regs, sense_regs) \ | 83 | priorities, mask_regs, prio_regs, sense_regs) \ |
84 | struct intc_desc symbol = { \ | 84 | struct intc_desc symbol __initdata = { \ |
85 | _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \ | 85 | _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \ |
86 | _INTC_ARRAY(priorities), \ | 86 | _INTC_ARRAY(priorities), \ |
87 | _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \ | 87 | _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \ |