13 files changed, 2252 insertions, 9 deletions

diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index b16f5e31c08a..312228ed8489 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -6,6 +6,9 @@ config AINTC
 config CP_INTC
         bool
 
+config ARCH_DAVINCI_DMx
+        bool
+
 menu "TI DaVinci Implementations"
 
 comment "DaVinci Core Type"
@@ -13,14 +16,25 @@ comment "DaVinci Core Type"
 config ARCH_DAVINCI_DM644x
         bool "DaVinci 644x based system"
         select AINTC
+        select ARCH_DAVINCI_DMx
 
 config ARCH_DAVINCI_DM355
         bool "DaVinci 355 based system"
         select AINTC
+        select ARCH_DAVINCI_DMx
 
 config ARCH_DAVINCI_DM646x
         bool "DaVinci 646x based system"
         select AINTC
+        select ARCH_DAVINCI_DMx
+
+config ARCH_DAVINCI_DA830
+        bool "DA830/OMAP-L137 based system"
+        select CP_INTC
+        select ARCH_DAVINCI_DA8XX
+
+config ARCH_DAVINCI_DA8XX
+        bool
 
 config ARCH_DAVINCI_DM365
         bool "DaVinci 365 based system"
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index bea7ba65b3f4..385638c0a711 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -5,15 +5,16 @@
 
 # Common objects
 obj-y                   := time.o clock.o serial.o io.o psc.o \
-                           gpio.o devices.o dma.o usb.o common.o sram.o
+                           gpio.o dma.o usb.o common.o sram.o
 
 obj-$(CONFIG_DAVINCI_MUX)               += mux.o
 
 # Chip specific
-obj-$(CONFIG_ARCH_DAVINCI_DM644x)       += dm644x.o
-obj-$(CONFIG_ARCH_DAVINCI_DM355)        += dm355.o
-obj-$(CONFIG_ARCH_DAVINCI_DM646x)       += dm646x.o
-obj-$(CONFIG_ARCH_DAVINCI_DM365)        += dm365.o
+obj-$(CONFIG_ARCH_DAVINCI_DM644x)       += dm644x.o devices.o
+obj-$(CONFIG_ARCH_DAVINCI_DM355)        += dm355.o devices.o
+obj-$(CONFIG_ARCH_DAVINCI_DM646x)       += dm646x.o devices.o
+obj-$(CONFIG_ARCH_DAVINCI_DM365)        += dm365.o devices.o
+obj-$(CONFIG_ARCH_DAVINCI_DA830)        += da830.o devices-da8xx.o
 
 obj-$(CONFIG_AINTC)                     += irq.o
 obj-$(CONFIG_CP_INTC)                   += cp_intc.o
diff --git a/arch/arm/mach-davinci/Makefile.boot b/arch/arm/mach-davinci/Makefile.boot
index e1dd366f836b..db97ef2c6477 100644
--- a/arch/arm/mach-davinci/Makefile.boot
+++ b/arch/arm/mach-davinci/Makefile.boot
@@ -1,3 +1,13 @@
+ifeq ($(CONFIG_ARCH_DAVINCI_DA8XX),y)
+ifeq ($(CONFIG_ARCH_DAVINCI_DMx),y)
+$(error Cannot enable DaVinci and DA8XX platforms concurrently)
+else
+   zreladdr-y   := 0xc0008000
+params_phys-y   := 0xc0000100
+initrd_phys-y   := 0xc0800000
+endif
+else
    zreladdr-y   := 0x80008000
 params_phys-y   := 0x80000100
 initrd_phys-y   := 0x80800000
+endif
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
new file mode 100644
index 000000000000..ab4242869b66
--- /dev/null
+++ b/arch/arm/mach-davinci/da830.c
@@ -0,0 +1,1247 @@
+/*
+ * TI DA830/OMAP L137 chip specific setup
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2009 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/clock.h>
+#include <mach/psc.h>
+#include <mach/mux.h>
+#include <mach/irqs.h>
+#include <mach/cputype.h>
+#include <mach/common.h>
+#include <mach/time.h>
+#include <mach/da8xx.h>
+
+#include "clock.h"
+#include "mux.h"
+
+#define DA830_PSC0_BASE         0x01c10000
+#define DA830_PLL0_BASE         0x01c11000
+#define DA830_JTAG_ID_REG       0x01c14018
+#define DA830_TIMER64P0_BASE    0x01c20000
+#define DA830_TIMER64P1_BASE    0x01c21000
+#define DA830_GPIO_BASE         0x01e26000
+#define DA830_PSC1_BASE         0x01e27000
+
+/* Offsets of the 8 compare registers on the da830 */
+#define DA830_CMP12_0           0x60
+#define DA830_CMP12_1           0x64
+#define DA830_CMP12_2           0x68
+#define DA830_CMP12_3           0x6c
+#define DA830_CMP12_4           0x70
+#define DA830_CMP12_5           0x74
+#define DA830_CMP12_6           0x78
+#define DA830_CMP12_7           0x7c
+
+#define DA830_REF_FREQ          24000000
+
+static struct pll_data pll0_data = {
+        .num            = 1,
+        .phys_base      = DA830_PLL0_BASE,
+        .flags          = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
+};
+
+static struct clk ref_clk = {
+        .name           = "ref_clk",
+        .rate           = DA830_REF_FREQ,
+};
+
+static struct clk pll0_clk = {
+        .name           = "pll0",
+        .parent         = &ref_clk,
+        .pll_data       = &pll0_data,
+        .flags          = CLK_PLL,
+};
+
+static struct clk pll0_aux_clk = {
+        .name           = "pll0_aux_clk",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL | PRE_PLL,
+};
+
+static struct clk pll0_sysclk2 = {
+        .name           = "pll0_sysclk2",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV2,
+};
+
+static struct clk pll0_sysclk3 = {
+        .name           = "pll0_sysclk3",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV3,
+};
+
+static struct clk pll0_sysclk4 = {
+        .name           = "pll0_sysclk4",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV4,
+};
+
+static struct clk pll0_sysclk5 = {
+        .name           = "pll0_sysclk5",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV5,
+};
+
+static struct clk pll0_sysclk6 = {
+        .name           = "pll0_sysclk6",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV6,
+};
+
+static struct clk pll0_sysclk7 = {
+        .name           = "pll0_sysclk7",
+        .parent         = &pll0_clk,
+        .flags          = CLK_PLL,
+        .div_reg        = PLLDIV7,
+};
+
+static struct clk i2c0_clk = {
+        .name           = "i2c0",
+        .parent         = &pll0_aux_clk,
+};
+
+static struct clk timerp64_0_clk = {
+        .name           = "timer0",
+        .parent         = &pll0_aux_clk,
+};
+
+static struct clk timerp64_1_clk = {
+        .name           = "timer1",
+        .parent         = &pll0_aux_clk,
+};
+
+static struct clk arm_rom_clk = {
+        .name           = "arm_rom",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_ARM_RAM_ROM,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk scr0_ss_clk = {
+        .name           = "scr0_ss",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_SCR0_SS,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk scr1_ss_clk = {
+        .name           = "scr1_ss",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_SCR1_SS,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk scr2_ss_clk = {
+        .name           = "scr2_ss",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_SCR2_SS,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk dmax_clk = {
+        .name           = "dmax",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_DMAX,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk tpcc_clk = {
+        .name           = "tpcc",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_TPCC,
+        .flags          = ALWAYS_ENABLED | CLK_PSC,
+};
+
+static struct clk tptc0_clk = {
+        .name           = "tptc0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_TPTC0,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk tptc1_clk = {
+        .name           = "tptc1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_TPTC1,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk mmcsd_clk = {
+        .name           = "mmcsd",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_MMC_SD,
+};
+
+static struct clk uart0_clk = {
+        .name           = "uart0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_UART0,
+};
+
+static struct clk uart1_clk = {
+        .name           = "uart1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_UART1,
+        .psc_ctlr       = 1,
+};
+
+static struct clk uart2_clk = {
+        .name           = "uart2",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_UART2,
+        .psc_ctlr       = 1,
+};
+
+static struct clk spi0_clk = {
+        .name           = "spi0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC0_SPI0,
+};
+
+static struct clk spi1_clk = {
+        .name           = "spi1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_SPI1,
+        .psc_ctlr       = 1,
+};
+
+static struct clk ecap0_clk = {
+        .name           = "ecap0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_ECAP,
+        .psc_ctlr       = 1,
+};
+
+static struct clk ecap1_clk = {
+        .name           = "ecap1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_ECAP,
+        .psc_ctlr       = 1,
+};
+
+static struct clk ecap2_clk = {
+        .name           = "ecap2",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_ECAP,
+        .psc_ctlr       = 1,
+};
+
+static struct clk pwm0_clk = {
+        .name           = "pwm0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_PWM,
+        .psc_ctlr       = 1,
+};
+
+static struct clk pwm1_clk = {
+        .name           = "pwm1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_PWM,
+        .psc_ctlr       = 1,
+};
+
+static struct clk pwm2_clk = {
+        .name           = "pwm2",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_PWM,
+        .psc_ctlr       = 1,
+};
+
+static struct clk eqep0_clk = {
+        .name           = "eqep0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA830_LPSC1_EQEP,
+        .psc_ctlr       = 1,
+};
+
+static struct clk eqep1_clk = {
+        .name           = "eqep1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA830_LPSC1_EQEP,
+        .psc_ctlr       = 1,
+};
+
+static struct clk lcdc_clk = {
+        .name           = "lcdc",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_LCDC,
+        .psc_ctlr       = 1,
+};
+
+static struct clk mcasp0_clk = {
+        .name           = "mcasp0",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_McASP0,
+        .psc_ctlr       = 1,
+};
+
+static struct clk mcasp1_clk = {
+        .name           = "mcasp1",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA830_LPSC1_McASP1,
+        .psc_ctlr       = 1,
+};
+
+static struct clk mcasp2_clk = {
+        .name           = "mcasp2",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA830_LPSC1_McASP2,
+        .psc_ctlr       = 1,
+};
+
+static struct clk usb20_clk = {
+        .name           = "usb20",
+        .parent         = &pll0_sysclk2,
+        .lpsc           = DA8XX_LPSC1_USB20,
+        .psc_ctlr       = 1,
+};
+
+static struct clk aemif_clk = {
+        .name           = "aemif",
+        .parent         = &pll0_sysclk3,
+        .lpsc           = DA8XX_LPSC0_EMIF25,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk aintc_clk = {
+        .name           = "aintc",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC0_AINTC,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk secu_mgr_clk = {
+        .name           = "secu_mgr",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC0_SECU_MGR,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk emac_clk = {
+        .name           = "emac",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC1_CPGMAC,
+        .psc_ctlr       = 1,
+};
+
+static struct clk gpio_clk = {
+        .name           = "gpio",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC1_GPIO,
+        .psc_ctlr       = 1,
+};
+
+static struct clk i2c1_clk = {
+        .name           = "i2c1",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC1_I2C,
+        .psc_ctlr       = 1,
+};
+
+static struct clk usb11_clk = {
+        .name           = "usb11",
+        .parent         = &pll0_sysclk4,
+        .lpsc           = DA8XX_LPSC1_USB11,
+        .psc_ctlr       = 1,
+};
+
+static struct clk emif3_clk = {
+        .name           = "emif3",
+        .parent         = &pll0_sysclk5,
+        .lpsc           = DA8XX_LPSC1_EMIF3C,
+        .flags          = ALWAYS_ENABLED,
+        .psc_ctlr       = 1,
+};
+
+static struct clk arm_clk = {
+        .name           = "arm",
+        .parent         = &pll0_sysclk6,
+        .lpsc           = DA8XX_LPSC0_ARM,
+        .flags          = ALWAYS_ENABLED,
+};
+
+static struct clk rmii_clk = {
+        .name           = "rmii",
+        .parent         = &pll0_sysclk7,
+};
+
+static struct davinci_clk da830_clks[] = {
+        CLK(NULL,               "ref",          &ref_clk),
+        CLK(NULL,               "pll0",         &pll0_clk),
+        CLK(NULL,               "pll0_aux",     &pll0_aux_clk),
+        CLK(NULL,               "pll0_sysclk2", &pll0_sysclk2),
+        CLK(NULL,               "pll0_sysclk3", &pll0_sysclk3),
+        CLK(NULL,               "pll0_sysclk4", &pll0_sysclk4),
+        CLK(NULL,               "pll0_sysclk5", &pll0_sysclk5),
+        CLK(NULL,               "pll0_sysclk6", &pll0_sysclk6),
+        CLK(NULL,               "pll0_sysclk7", &pll0_sysclk7),
+        CLK("i2c_davinci.1",    NULL,           &i2c0_clk),
+        CLK(NULL,               "timer0",       &timerp64_0_clk),
+        CLK("watchdog",         NULL,           &timerp64_1_clk),
+        CLK(NULL,               "arm_rom",      &arm_rom_clk),
+        CLK(NULL,               "scr0_ss",      &scr0_ss_clk),
+        CLK(NULL,               "scr1_ss",      &scr1_ss_clk),
+        CLK(NULL,               "scr2_ss",      &scr2_ss_clk),
+        CLK(NULL,               "dmax",         &dmax_clk),
+        CLK(NULL,               "tpcc",         &tpcc_clk),
+        CLK(NULL,               "tptc0",        &tptc0_clk),
+        CLK(NULL,               "tptc1",        &tptc1_clk),
+        CLK("davinci_mmc.0",    NULL,           &mmcsd_clk),
+        CLK(NULL,               "uart0",        &uart0_clk),
+        CLK(NULL,               "uart1",        &uart1_clk),
+        CLK(NULL,               "uart2",        &uart2_clk),
+        CLK("dm_spi.0",         NULL,           &spi0_clk),
+        CLK("dm_spi.1",         NULL,           &spi1_clk),
+        CLK(NULL,               "ecap0",        &ecap0_clk),
+        CLK(NULL,               "ecap1",        &ecap1_clk),
+        CLK(NULL,               "ecap2",        &ecap2_clk),
+        CLK(NULL,               "pwm0",         &pwm0_clk),
+        CLK(NULL,               "pwm1",         &pwm1_clk),
+        CLK(NULL,               "pwm2",         &pwm2_clk),
+        CLK("eqep.0",           NULL,           &eqep0_clk),
+        CLK("eqep.1",           NULL,           &eqep1_clk),
+        CLK("da830_lcdc",       NULL,           &lcdc_clk),
+        CLK("soc-audio.0",      NULL,           &mcasp0_clk),
+        CLK("soc-audio.1",      NULL,           &mcasp1_clk),
+        CLK("soc-audio.2",      NULL,           &mcasp2_clk),
+        CLK("musb_hdrc",        NULL,           &usb20_clk),
+        CLK(NULL,               "aemif",        &aemif_clk),
+        CLK(NULL,               "aintc",        &aintc_clk),
+        CLK(NULL,               "secu_mgr",     &secu_mgr_clk),
+        CLK("davinci_emac.1",   NULL,           &emac_clk),
+        CLK(NULL,               "gpio",         &gpio_clk),
+        CLK("i2c_davinci.2",    NULL,           &i2c1_clk),
+        CLK(NULL,               "usb11",        &usb11_clk),
+        CLK(NULL,               "emif3",        &emif3_clk),
+        CLK(NULL,               "arm",          &arm_clk),
+        CLK(NULL,               "rmii",         &rmii_clk),
+        CLK(NULL,               NULL,           NULL),
+};
+
+#define PINMUX0                 0x00
+#define PINMUX1                 0x04
+#define PINMUX2                 0x08
+#define PINMUX3                 0x0c
+#define PINMUX4                 0x10
+#define PINMUX5                 0x14
+#define PINMUX6                 0x18
+#define PINMUX7                 0x1c
+#define PINMUX8                 0x20
+#define PINMUX9                 0x24
+#define PINMUX10                0x28
+#define PINMUX11                0x2c
+#define PINMUX12                0x30
+#define PINMUX13                0x34
+#define PINMUX14                0x38
+#define PINMUX15                0x3c
+#define PINMUX16                0x40
+#define PINMUX17                0x44
+#define PINMUX18                0x48
+#define PINMUX19                0x4c
+
+/*
+ * Device specific mux setup
+ *
+ *           soc      description       mux    mode    mode   mux       dbg
+ *                                      reg   offset   mask   mode
+ */
+static const struct mux_config da830_pins[] = {
+#ifdef CONFIG_DAVINCI_MUX
+        MUX_CFG(DA830, GPIO7_14,        0,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, RTCK,            0,      0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_15,        0,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMU_0,           0,      4,      0xf,    8,      false)
+        MUX_CFG(DA830, EMB_SDCKE,       0,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_CLK_GLUE,    0,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_CLK,         0,      12,     0xf,    2,      false)
+        MUX_CFG(DA830, NEMB_CS_0,       0,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMB_CAS,        0,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMB_RAS,        0,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMB_WE,         0,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_BA_1,        1,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_BA_0,        1,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_0,         1,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_1,         1,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_2,         1,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_3,         1,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_4,         1,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_5,         1,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, GPIO7_0,         1,      0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_1,         1,      4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_2,         1,      8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_3,         1,      12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_4,         1,      16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_5,         1,      20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_6,         1,      24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_7,         1,      28,     0xf,    8,      false)
+        MUX_CFG(DA830, EMB_A_6,         2,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_7,         2,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_8,         2,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_9,         2,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_10,        2,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_11,        2,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_A_12,        2,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_31,        2,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, GPIO7_8,         2,      0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_9,         2,      4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_10,        2,      8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_11,        2,      12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_12,        2,      16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO7_13,        2,      20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_13,        2,      24,     0xf,    8,      false)
+        MUX_CFG(DA830, EMB_D_30,        3,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_29,        3,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_28,        3,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_27,        3,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_26,        3,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_25,        3,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_24,        3,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_23,        3,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_22,        4,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_21,        4,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_20,        4,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_19,        4,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_18,        4,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_17,        4,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_16,        4,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMB_WE_DQM_3,   4,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMB_WE_DQM_2,   5,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_0,         5,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_1,         5,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_2,         5,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_3,         5,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_4,         5,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_5,         5,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_6,         5,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, GPIO6_0,         5,      4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_1,         5,      8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_2,         5,      12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_3,         5,      16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_4,         5,      20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_5,         5,      24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_6,         5,      28,     0xf,    8,      false)
+        MUX_CFG(DA830, EMB_D_7,         6,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_8,         6,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_9,         6,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_10,        6,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_11,        6,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_12,        6,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_13,        6,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMB_D_14,        6,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, GPIO6_7,         6,      0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_8,         6,      4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_9,         6,      8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_10,        6,      12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_11,        6,      16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_12,        6,      20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_13,        6,      24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO6_14,        6,      28,     0xf,    8,      false)
+        MUX_CFG(DA830, EMB_D_15,        7,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, NEMB_WE_DQM_1,   7,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, NEMB_WE_DQM_0,   7,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, SPI0_SOMI_0,     7,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, SPI0_SIMO_0,     7,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, SPI0_CLK,        7,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, NSPI0_ENA,       7,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, NSPI0_SCS_0,     7,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, EQEP0I,          7,      12,     0xf,    2,      false)
+        MUX_CFG(DA830, EQEP0S,          7,      16,     0xf,    2,      false)
+        MUX_CFG(DA830, EQEP1I,          7,      20,     0xf,    2,      false)
+        MUX_CFG(DA830, NUART0_CTS,      7,      24,     0xf,    2,      false)
+        MUX_CFG(DA830, NUART0_RTS,      7,      28,     0xf,    2,      false)
+        MUX_CFG(DA830, EQEP0A,          7,      24,     0xf,    4,      false)
+        MUX_CFG(DA830, EQEP0B,          7,      28,     0xf,    4,      false)
+        MUX_CFG(DA830, GPIO6_15,        7,      0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_14,        7,      4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_15,        7,      8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_0,         7,      12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_1,         7,      16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_2,         7,      20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_3,         7,      24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_4,         7,      28,     0xf,    8,      false)
+        MUX_CFG(DA830, SPI1_SOMI_0,     8,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, SPI1_SIMO_0,     8,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, SPI1_CLK,        8,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, UART0_RXD,       8,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, UART0_TXD,       8,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_10,         8,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_11,         8,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, NSPI1_ENA,       8,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, I2C1_SCL,        8,      0,      0xf,    2,      false)
+        MUX_CFG(DA830, I2C1_SDA,        8,      4,      0xf,    2,      false)
+        MUX_CFG(DA830, EQEP1S,          8,      8,      0xf,    2,      false)
+        MUX_CFG(DA830, I2C0_SDA,        8,      12,     0xf,    2,      false)
+        MUX_CFG(DA830, I2C0_SCL,        8,      16,     0xf,    2,      false)
+        MUX_CFG(DA830, UART2_RXD,       8,      28,     0xf,    2,      false)
+        MUX_CFG(DA830, TM64P0_IN12,     8,      12,     0xf,    4,      false)
+        MUX_CFG(DA830, TM64P0_OUT12,    8,      16,     0xf,    4,      false)
+        MUX_CFG(DA830, GPIO5_5,         8,      0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_6,         8,      4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_7,         8,      8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_8,         8,      12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_9,         8,      16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_10,        8,      20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_11,        8,      24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO5_12,        8,      28,     0xf,    8,      false)
+        MUX_CFG(DA830, NSPI1_SCS_0,     9,      0,      0xf,    1,      false)
+        MUX_CFG(DA830, USB0_DRVVBUS,    9,      4,      0xf,    1,      false)
+        MUX_CFG(DA830, AHCLKX0,         9,      8,      0xf,    1,      false)
+        MUX_CFG(DA830, ACLKX0,          9,      12,     0xf,    1,      false)
+        MUX_CFG(DA830, AFSX0,           9,      16,     0xf,    1,      false)
+        MUX_CFG(DA830, AHCLKR0,         9,      20,     0xf,    1,      false)
+        MUX_CFG(DA830, ACLKR0,          9,      24,     0xf,    1,      false)
+        MUX_CFG(DA830, AFSR0,           9,      28,     0xf,    1,      false)
+        MUX_CFG(DA830, UART2_TXD,       9,      0,      0xf,    2,      false)
+        MUX_CFG(DA830, AHCLKX2,         9,      8,      0xf,    2,      false)
+        MUX_CFG(DA830, ECAP0_APWM0,     9,      12,     0xf,    2,      false)
+        MUX_CFG(DA830, RMII_MHZ_50_CLK, 9,      20,     0xf,    2,      false)
+        MUX_CFG(DA830, ECAP1_APWM1,     9,      24,     0xf,    2,      false)
+        MUX_CFG(DA830, USB_REFCLKIN,    9,      8,      0xf,    4,      false)
+        MUX_CFG(DA830, GPIO5_13,        9,      0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_15,        9,      4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_11,        9,      8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_12,        9,      12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_13,        9,      16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_14,        9,      20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_15,        9,      24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_12,        9,      28,     0xf,    8,      false)
+        MUX_CFG(DA830, AMUTE0,          10,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_0,          10,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_1,          10,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_2,          10,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_3,          10,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_4,          10,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_5,          10,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_6,          10,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, RMII_TXD_0,      10,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, RMII_TXD_1,      10,     8,      0xf,    2,      false)
+        MUX_CFG(DA830, RMII_TXEN,       10,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, RMII_CRS_DV,     10,     16,     0xf,    2,      false)
+        MUX_CFG(DA830, RMII_RXD_0,      10,     20,     0xf,    2,      false)
+        MUX_CFG(DA830, RMII_RXD_1,      10,     24,     0xf,    2,      false)
+        MUX_CFG(DA830, RMII_RXER,       10,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, AFSR2,           10,     4,      0xf,    4,      false)
+        MUX_CFG(DA830, ACLKX2,          10,     8,      0xf,    4,      false)
+        MUX_CFG(DA830, AXR2_3,          10,     12,     0xf,    4,      false)
+        MUX_CFG(DA830, AXR2_2,          10,     16,     0xf,    4,      false)
+        MUX_CFG(DA830, AXR2_1,          10,     20,     0xf,    4,      false)
+        MUX_CFG(DA830, AFSX2,           10,     24,     0xf,    4,      false)
+        MUX_CFG(DA830, ACLKR2,          10,     28,     0xf,    4,      false)
+        MUX_CFG(DA830, NRESETOUT,       10,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_0,         10,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_1,         10,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_2,         10,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_3,         10,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_4,         10,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_5,         10,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_6,         10,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, AXR0_7,          11,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_8,          11,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, UART1_RXD,       11,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, UART1_TXD,       11,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR0_11,         11,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, AHCLKX1,         11,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, ACLKX1,          11,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, AFSX1,           11,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, MDIO_CLK,        11,     0,      0xf,    2,      false)
+        MUX_CFG(DA830, MDIO_D,          11,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, AXR0_9,          11,     8,      0xf,    2,      false)
+        MUX_CFG(DA830, AXR0_10,         11,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, EPWM0B,          11,     20,     0xf,    2,      false)
+        MUX_CFG(DA830, EPWM0A,          11,     24,     0xf,    2,      false)
+        MUX_CFG(DA830, EPWMSYNCI,       11,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, AXR2_0,          11,     16,     0xf,    4,      false)
+        MUX_CFG(DA830, EPWMSYNC0,       11,     28,     0xf,    4,      false)
+        MUX_CFG(DA830, GPIO3_7,         11,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_8,         11,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_9,         11,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_10,        11,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_11,        11,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_14,        11,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO3_15,        11,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_10,        11,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, AHCLKR1,         12,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, ACLKR1,          12,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, AFSR1,           12,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, AMUTE1,          12,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_0,          12,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_1,          12,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_2,          12,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_3,          12,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, ECAP2_APWM2,     12,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, EHRPWMGLUETZ,    12,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, EQEP1A,          12,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, GPIO4_11,        12,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_12,        12,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_13,        12,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_14,        12,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_0,         12,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_1,         12,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_2,         12,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_3,         12,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, AXR1_4,          13,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_5,          13,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_6,          13,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_7,          13,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_8,          13,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, AXR1_9,          13,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_0,         13,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_1,         13,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, EQEP1B,          13,     0,      0xf,    2,      false)
+        MUX_CFG(DA830, EPWM2B,          13,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, EPWM2A,          13,     8,      0xf,    2,      false)
+        MUX_CFG(DA830, EPWM1B,          13,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, EPWM1A,          13,     16,     0xf,    2,      false)
+        MUX_CFG(DA830, MMCSD_DAT_0,     13,     24,     0xf,    2,      false)
+        MUX_CFG(DA830, MMCSD_DAT_1,     13,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_0,       13,     24,     0xf,    4,      false)
+        MUX_CFG(DA830, UHPI_HD_1,       13,     28,     0xf,    4,      false)
+        MUX_CFG(DA830, GPIO4_4,         13,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_5,         13,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_6,         13,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_7,         13,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_8,         13,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO4_9,         13,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_0,         13,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_1,         13,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, EMA_D_2,         14,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_3,         14,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_4,         14,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_5,         14,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_6,         14,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_7,         14,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_8,         14,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_9,         14,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, MMCSD_DAT_2,     14,     0,      0xf,    2,      false)
+        MUX_CFG(DA830, MMCSD_DAT_3,     14,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, MMCSD_DAT_4,     14,     8,      0xf,    2,      false)
+        MUX_CFG(DA830, MMCSD_DAT_5,     14,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, MMCSD_DAT_6,     14,     16,     0xf,    2,      false)
+        MUX_CFG(DA830, MMCSD_DAT_7,     14,     20,     0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_8,       14,     24,     0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_9,       14,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_2,       14,     0,      0xf,    4,      false)
+        MUX_CFG(DA830, UHPI_HD_3,       14,     4,      0xf,    4,      false)
+        MUX_CFG(DA830, UHPI_HD_4,       14,     8,      0xf,    4,      false)
+        MUX_CFG(DA830, UHPI_HD_5,       14,     12,     0xf,    4,      false)
+        MUX_CFG(DA830, UHPI_HD_6,       14,     16,     0xf,    4,      false)
+        MUX_CFG(DA830, UHPI_HD_7,       14,     20,     0xf,    4,      false)
+        MUX_CFG(DA830, LCD_D_8,         14,     24,     0xf,    4,      false)
+        MUX_CFG(DA830, LCD_D_9,         14,     28,     0xf,    4,      false)
+        MUX_CFG(DA830, GPIO0_2,         14,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_3,         14,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_4,         14,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_5,         14,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_6,         14,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_7,         14,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_8,         14,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_9,         14,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, EMA_D_10,        15,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_11,        15,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_12,        15,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_13,        15,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_14,        15,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_D_15,        15,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_0,         15,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_1,         15,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, UHPI_HD_10,      15,     0,      0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_11,      15,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_12,      15,     8,      0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_13,      15,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_14,      15,     16,     0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HD_15,      15,     20,     0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_7,         15,     24,     0xf,    2,      false)
+        MUX_CFG(DA830, MMCSD_CLK,       15,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_10,        15,     0,      0xf,    4,      false)
+        MUX_CFG(DA830, LCD_D_11,        15,     4,      0xf,    4,      false)
+        MUX_CFG(DA830, LCD_D_12,        15,     8,      0xf,    4,      false)
+        MUX_CFG(DA830, LCD_D_13,        15,     12,     0xf,    4,      false)
+        MUX_CFG(DA830, LCD_D_14,        15,     16,     0xf,    4,      false)
+        MUX_CFG(DA830, LCD_D_15,        15,     20,     0xf,    4,      false)
+        MUX_CFG(DA830, UHPI_HCNTL0,     15,     28,     0xf,    4,      false)
+        MUX_CFG(DA830, GPIO0_10,        15,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_11,        15,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_12,        15,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_13,        15,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_14,        15,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO0_15,        15,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_0,         15,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_1,         15,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, EMA_A_2,         16,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_3,         16,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_4,         16,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_5,         16,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_6,         16,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_7,         16,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_8,         16,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_9,         16,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, MMCSD_CMD,       16,     0,      0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_6,         16,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_3,         16,     8,      0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_2,         16,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_1,         16,     16,     0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_0,         16,     20,     0xf,    2,      false)
+        MUX_CFG(DA830, LCD_PCLK,        16,     24,     0xf,    2,      false)
+        MUX_CFG(DA830, LCD_HSYNC,       16,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HCNTL1,     16,     0,      0xf,    4,      false)
+        MUX_CFG(DA830, GPIO1_2,         16,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_3,         16,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_4,         16,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_5,         16,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_6,         16,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_7,         16,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_8,         16,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_9,         16,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, EMA_A_10,        17,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_11,        17,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_A_12,        17,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, EMA_BA_1,        17,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_BA_0,        17,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_CLK,         17,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, EMA_SDCKE,       17,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_CAS,        17,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, LCD_VSYNC,       17,     0,      0xf,    2,      false)
+        MUX_CFG(DA830, NLCD_AC_ENB_CS,  17,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, LCD_MCLK,        17,     8,      0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_5,         17,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, LCD_D_4,         17,     16,     0xf,    2,      false)
+        MUX_CFG(DA830, OBSCLK,          17,     20,     0xf,    2,      false)
+        MUX_CFG(DA830, NEMA_CS_4,       17,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HHWIL,      17,     12,     0xf,    4,      false)
+        MUX_CFG(DA830, AHCLKR2,         17,     20,     0xf,    4,      false)
+        MUX_CFG(DA830, GPIO1_10,        17,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_11,        17,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_12,        17,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_13,        17,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_14,        17,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO1_15,        17,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_0,         17,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_1,         17,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, NEMA_RAS,        18,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_WE,         18,     4,      0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_CS_0,       18,     8,      0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_CS_2,       18,     12,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_CS_3,       18,     16,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_OE,         18,     20,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_WE_DQM_1,   18,     24,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_WE_DQM_0,   18,     28,     0xf,    1,      false)
+        MUX_CFG(DA830, NEMA_CS_5,       18,     0,      0xf,    2,      false)
+        MUX_CFG(DA830, UHPI_HRNW,       18,     4,      0xf,    2,      false)
+        MUX_CFG(DA830, NUHPI_HAS,       18,     8,      0xf,    2,      false)
+        MUX_CFG(DA830, NUHPI_HCS,       18,     12,     0xf,    2,      false)
+        MUX_CFG(DA830, NUHPI_HDS1,      18,     20,     0xf,    2,      false)
+        MUX_CFG(DA830, NUHPI_HDS2,      18,     24,     0xf,    2,      false)
+        MUX_CFG(DA830, NUHPI_HINT,      18,     28,     0xf,    2,      false)
+        MUX_CFG(DA830, AXR0_12,         18,     4,      0xf,    4,      false)
+        MUX_CFG(DA830, AMUTE2,          18,     16,     0xf,    4,      false)
+        MUX_CFG(DA830, AXR0_13,         18,     20,     0xf,    4,      false)
+        MUX_CFG(DA830, AXR0_14,         18,     24,     0xf,    4,      false)
+        MUX_CFG(DA830, AXR0_15,         18,     28,     0xf,    4,      false)
+        MUX_CFG(DA830, GPIO2_2,         18,     0,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_3,         18,     4,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_4,         18,     8,      0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_5,         18,     12,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_6,         18,     16,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_7,         18,     20,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_8,         18,     24,     0xf,    8,      false)
+        MUX_CFG(DA830, GPIO2_9,         18,     28,     0xf,    8,      false)
+        MUX_CFG(DA830, EMA_WAIT_0,      19,     0,      0xf,    1,      false)
+        MUX_CFG(DA830, NUHPI_HRDY,      19,     0,      0xf,    2,      false)
+        MUX_CFG(DA830, GPIO2_10,        19,     0,      0xf,    8,      false)
+#endif
+};
+
+const short da830_emif25_pins[] __initdata = {
+        DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3,
+        DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7,
+        DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11,
+        DA830_EMA_D_12, DA830_EMA_D_13, DA830_EMA_D_14, DA830_EMA_D_15,
+        DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3,
+        DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7,
+        DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11,
+        DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_EMA_CLK,
+        DA830_EMA_SDCKE, DA830_NEMA_CS_4, DA830_NEMA_CS_5, DA830_NEMA_WE,
+        DA830_NEMA_CS_0, DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE,
+        DA830_NEMA_WE_DQM_1, DA830_NEMA_WE_DQM_0, DA830_EMA_WAIT_0,
+        -1
+};
+
+const short da830_spi0_pins[] __initdata = {
+        DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA,
+        DA830_NSPI0_SCS_0,
+        -1
+};
+
+const short da830_spi1_pins[] __initdata = {
+        DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA,
+        DA830_NSPI1_SCS_0,
+        -1
+};
+
+const short da830_mmc_sd_pins[] __initdata = {
+        DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2,
+        DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5,
+        DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK,
+        DA830_MMCSD_CMD,
+        -1
+};
+
+const short da830_uart0_pins[] __initdata = {
+        DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD,
+        -1
+};
+
+const short da830_uart1_pins[] __initdata = {
+        DA830_UART1_RXD, DA830_UART1_TXD,
+        -1
+};
+
+const short da830_uart2_pins[] __initdata = {
+        DA830_UART2_RXD, DA830_UART2_TXD,
+        -1
+};
+
+const short da830_usb20_pins[] __initdata = {
+        DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN,
+        -1
+};
+
+const short da830_usb11_pins[] __initdata = {
+        DA830_USB_REFCLKIN,
+        -1
+};
+
+const short da830_uhpi_pins[] __initdata = {
+        DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3,
+        DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7,
+        DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11,
+        DA830_UHPI_HD_12, DA830_UHPI_HD_13, DA830_UHPI_HD_14, DA830_UHPI_HD_15,
+        DA830_UHPI_HCNTL0, DA830_UHPI_HCNTL1, DA830_UHPI_HHWIL, DA830_UHPI_HRNW,
+        DA830_NUHPI_HAS, DA830_NUHPI_HCS, DA830_NUHPI_HDS1, DA830_NUHPI_HDS2,
+        DA830_NUHPI_HINT, DA830_NUHPI_HRDY,
+        -1
+};
+
+const short da830_cpgmac_pins[] __initdata = {
+        DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV,
+        DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK,
+        DA830_MDIO_D,
+        -1
+};
+
+const short da830_emif3c_pins[] __initdata = {
+        DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0,
+        DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1,
+        DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2,
+        DA830_EMB_A_3, DA830_EMB_A_4, DA830_EMB_A_5, DA830_EMB_A_6,
+        DA830_EMB_A_7, DA830_EMB_A_8, DA830_EMB_A_9, DA830_EMB_A_10,
+        DA830_EMB_A_11, DA830_EMB_A_12, DA830_NEMB_WE_DQM_3,
+        DA830_NEMB_WE_DQM_2, DA830_EMB_D_0, DA830_EMB_D_1, DA830_EMB_D_2,
+        DA830_EMB_D_3, DA830_EMB_D_4, DA830_EMB_D_5, DA830_EMB_D_6,
+        DA830_EMB_D_7, DA830_EMB_D_8, DA830_EMB_D_9, DA830_EMB_D_10,
+        DA830_EMB_D_11, DA830_EMB_D_12, DA830_EMB_D_13, DA830_EMB_D_14,
+        DA830_EMB_D_15, DA830_EMB_D_16, DA830_EMB_D_17, DA830_EMB_D_18,
+        DA830_EMB_D_19, DA830_EMB_D_20, DA830_EMB_D_21, DA830_EMB_D_22,
+        DA830_EMB_D_23, DA830_EMB_D_24, DA830_EMB_D_25, DA830_EMB_D_26,
+        DA830_EMB_D_27, DA830_EMB_D_28, DA830_EMB_D_29, DA830_EMB_D_30,
+        DA830_EMB_D_31, DA830_NEMB_WE_DQM_1, DA830_NEMB_WE_DQM_0,
+        -1
+};
+
+const short da830_mcasp0_pins[] __initdata = {
+        DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0,
+        DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0,
+        DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3,
+        DA830_AXR0_4, DA830_AXR0_5, DA830_AXR0_6, DA830_AXR0_7,
+        DA830_AXR0_8, DA830_AXR0_9, DA830_AXR0_10, DA830_AXR0_11,
+        DA830_AXR0_12, DA830_AXR0_13, DA830_AXR0_14, DA830_AXR0_15,
+        -1
+};
+
+const short da830_mcasp1_pins[] __initdata = {
+        DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1,
+        DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1,
+        DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3,
+        DA830_AXR1_4, DA830_AXR1_5, DA830_AXR1_6, DA830_AXR1_7,
+        DA830_AXR1_8, DA830_AXR1_9, DA830_AXR1_10, DA830_AXR1_11,
+        -1
+};
+
+const short da830_mcasp2_pins[] __initdata = {
+        DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2,
+        DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2,
+        DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3,
+        -1
+};
+
+const short da830_i2c0_pins[] __initdata = {
+        DA830_I2C0_SDA, DA830_I2C0_SCL,
+        -1
+};
+
+const short da830_i2c1_pins[] __initdata = {
+        DA830_I2C1_SCL, DA830_I2C1_SDA,
+        -1
+};
+
+const short da830_lcdcntl_pins[] __initdata = {
+        DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3,
+        DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7,
+        DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11,
+        DA830_LCD_D_12, DA830_LCD_D_13, DA830_LCD_D_14, DA830_LCD_D_15,
+        DA830_LCD_PCLK, DA830_LCD_HSYNC, DA830_LCD_VSYNC, DA830_NLCD_AC_ENB_CS,
+        DA830_LCD_MCLK,
+        -1
+};
+
+const short da830_pwm_pins[] __initdata = {
+        DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A,
+        DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ,
+        DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A,
+        -1
+};
+
+const short da830_ecap0_pins[] __initdata = {
+        DA830_ECAP0_APWM0,
+        -1
+};
+
+const short da830_ecap1_pins[] __initdata = {
+        DA830_ECAP1_APWM1,
+        -1
+};
+
+const short da830_ecap2_pins[] __initdata = {
+        DA830_ECAP2_APWM2,
+        -1
+};
+
+const short da830_eqep0_pins[] __initdata = {
+        DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B,
+        -1
+};
+
+const short da830_eqep1_pins[] __initdata = {
+        DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B,
+        -1
+};
+
+int da830_pinmux_setup(const short pins[])
+{
+        int i, error = -EINVAL;
+
+        if (pins)
+                for (i = 0; pins[i] >= 0; i++) {
+                        error = davinci_cfg_reg(pins[i]);
+                        if (error)
+                                break;
+                }
+
+        return error;
+}
+
+/* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
+static u8 da830_default_priorities[DA830_N_CP_INTC_IRQ] = {
+        [IRQ_DA8XX_COMMTX]              = 7,
+        [IRQ_DA8XX_COMMRX]              = 7,
+        [IRQ_DA8XX_NINT]                = 7,
+        [IRQ_DA8XX_EVTOUT0]             = 7,
+        [IRQ_DA8XX_EVTOUT1]             = 7,
+        [IRQ_DA8XX_EVTOUT2]             = 7,
+        [IRQ_DA8XX_EVTOUT3]             = 7,
+        [IRQ_DA8XX_EVTOUT4]             = 7,
+        [IRQ_DA8XX_EVTOUT5]             = 7,
+        [IRQ_DA8XX_EVTOUT6]             = 7,
+        [IRQ_DA8XX_EVTOUT6]             = 7,
+        [IRQ_DA8XX_EVTOUT7]             = 7,
+        [IRQ_DA8XX_CCINT0]              = 7,
+        [IRQ_DA8XX_CCERRINT]            = 7,
+        [IRQ_DA8XX_TCERRINT0]           = 7,
+        [IRQ_DA8XX_AEMIFINT]            = 7,
+        [IRQ_DA8XX_I2CINT0]             = 7,
+        [IRQ_DA8XX_MMCSDINT0]           = 7,
+        [IRQ_DA8XX_MMCSDINT1]           = 7,
+        [IRQ_DA8XX_ALLINT0]             = 7,
+        [IRQ_DA8XX_RTC]                 = 7,
+        [IRQ_DA8XX_SPINT0]              = 7,
+        [IRQ_DA8XX_TINT12_0]            = 7,
+        [IRQ_DA8XX_TINT34_0]            = 7,
+        [IRQ_DA8XX_TINT12_1]            = 7,
+        [IRQ_DA8XX_TINT34_1]            = 7,
+        [IRQ_DA8XX_UARTINT0]            = 7,
+        [IRQ_DA8XX_KEYMGRINT]           = 7,
+        [IRQ_DA8XX_SECINT]              = 7,
+        [IRQ_DA8XX_SECKEYERR]           = 7,
+        [IRQ_DA830_MPUERR]              = 7,
+        [IRQ_DA830_IOPUERR]             = 7,
+        [IRQ_DA830_BOOTCFGERR]          = 7,
+        [IRQ_DA8XX_CHIPINT0]            = 7,
+        [IRQ_DA8XX_CHIPINT1]            = 7,
+        [IRQ_DA8XX_CHIPINT2]            = 7,
+        [IRQ_DA8XX_CHIPINT3]            = 7,
+        [IRQ_DA8XX_TCERRINT1]           = 7,
+        [IRQ_DA8XX_C0_RX_THRESH_PULSE]  = 7,
+        [IRQ_DA8XX_C0_RX_PULSE]         = 7,
+        [IRQ_DA8XX_C0_TX_PULSE]         = 7,
+        [IRQ_DA8XX_C0_MISC_PULSE]       = 7,
+        [IRQ_DA8XX_C1_RX_THRESH_PULSE]  = 7,
+        [IRQ_DA8XX_C1_RX_PULSE]         = 7,
+        [IRQ_DA8XX_C1_TX_PULSE]         = 7,
+        [IRQ_DA8XX_C1_MISC_PULSE]       = 7,
+        [IRQ_DA8XX_MEMERR]              = 7,
+        [IRQ_DA8XX_GPIO0]               = 7,
+        [IRQ_DA8XX_GPIO1]               = 7,
+        [IRQ_DA8XX_GPIO2]               = 7,
+        [IRQ_DA8XX_GPIO3]               = 7,
+        [IRQ_DA8XX_GPIO4]               = 7,
+        [IRQ_DA8XX_GPIO5]               = 7,
+        [IRQ_DA8XX_GPIO6]               = 7,
+        [IRQ_DA8XX_GPIO7]               = 7,
+        [IRQ_DA8XX_GPIO8]               = 7,
+        [IRQ_DA8XX_I2CINT1]             = 7,
+        [IRQ_DA8XX_LCDINT]              = 7,
+        [IRQ_DA8XX_UARTINT1]            = 7,
+        [IRQ_DA8XX_MCASPINT]            = 7,
+        [IRQ_DA8XX_ALLINT1]             = 7,
+        [IRQ_DA8XX_SPINT1]              = 7,
+        [IRQ_DA8XX_UHPI_INT1]           = 7,
+        [IRQ_DA8XX_USB_INT]             = 7,
+        [IRQ_DA8XX_IRQN]                = 7,
+        [IRQ_DA8XX_RWAKEUP]             = 7,
+        [IRQ_DA8XX_UARTINT2]            = 7,
+        [IRQ_DA8XX_DFTSSINT]            = 7,
+        [IRQ_DA8XX_EHRPWM0]             = 7,
+        [IRQ_DA8XX_EHRPWM0TZ]           = 7,
+        [IRQ_DA8XX_EHRPWM1]             = 7,
+        [IRQ_DA8XX_EHRPWM1TZ]           = 7,
+        [IRQ_DA830_EHRPWM2]             = 7,
+        [IRQ_DA830_EHRPWM2TZ]           = 7,
+        [IRQ_DA8XX_ECAP0]               = 7,
+        [IRQ_DA8XX_ECAP1]               = 7,
+        [IRQ_DA8XX_ECAP2]               = 7,
+        [IRQ_DA830_EQEP0]               = 7,
+        [IRQ_DA830_EQEP1]               = 7,
+        [IRQ_DA830_T12CMPINT0_0]        = 7,
+        [IRQ_DA830_T12CMPINT1_0]        = 7,
+        [IRQ_DA830_T12CMPINT2_0]        = 7,
+        [IRQ_DA830_T12CMPINT3_0]        = 7,
+        [IRQ_DA830_T12CMPINT4_0]        = 7,
+        [IRQ_DA830_T12CMPINT5_0]        = 7,
+        [IRQ_DA830_T12CMPINT6_0]        = 7,
+        [IRQ_DA830_T12CMPINT7_0]        = 7,
+        [IRQ_DA830_T12CMPINT0_1]        = 7,
+        [IRQ_DA830_T12CMPINT1_1]        = 7,
+        [IRQ_DA830_T12CMPINT2_1]        = 7,
+        [IRQ_DA830_T12CMPINT3_1]        = 7,
+        [IRQ_DA830_T12CMPINT4_1]        = 7,
+        [IRQ_DA830_T12CMPINT5_1]        = 7,
+        [IRQ_DA830_T12CMPINT6_1]        = 7,
+        [IRQ_DA830_T12CMPINT7_1]        = 7,
+        [IRQ_DA8XX_ARMCLKSTOPREQ]       = 7,
+};
+
+static struct map_desc da830_io_desc[] = {
+        {
+                .virtual        = IO_VIRT,
+                .pfn            = __phys_to_pfn(IO_PHYS),
+                .length         = IO_SIZE,
+                .type           = MT_DEVICE
+        },
+        {
+                .virtual        = DA8XX_CP_INTC_VIRT,
+                .pfn            = __phys_to_pfn(DA8XX_CP_INTC_BASE),
+                .length         = DA8XX_CP_INTC_SIZE,
+                .type           = MT_DEVICE
+        },
+};
+
+static void __iomem *da830_psc_bases[] = {
+        IO_ADDRESS(DA830_PSC0_BASE),
+        IO_ADDRESS(DA830_PSC1_BASE),
+};
+
+/* Contents of JTAG ID register used to identify exact cpu type */
+static struct davinci_id da830_ids[] = {
+        {
+                .variant        = 0x0,
+                .part_no        = 0xb7df,
+                .manufacturer   = 0x017,        /* 0x02f >> 1 */
+                .cpu_id         = DAVINCI_CPU_ID_DA830,
+                .name           = "da830/omap l137",
+        },
+};
+
+static struct davinci_timer_instance da830_timer_instance[2] = {
+        {
+                .base           = IO_ADDRESS(DA830_TIMER64P0_BASE),
+                .bottom_irq     = IRQ_DA8XX_TINT12_0,
+                .top_irq        = IRQ_DA8XX_TINT34_0,
+                .cmp_off        = DA830_CMP12_0,
+                .cmp_irq        = IRQ_DA830_T12CMPINT0_0,
+        },
+        {
+                .base           = IO_ADDRESS(DA830_TIMER64P1_BASE),
+                .bottom_irq     = IRQ_DA8XX_TINT12_1,
+                .top_irq        = IRQ_DA8XX_TINT34_1,
+                .cmp_off        = DA830_CMP12_0,
+                .cmp_irq        = IRQ_DA830_T12CMPINT0_1,
+        },
+};
+
+/*
+ * T0_BOT: Timer 0, bottom              : Used for clock_event & clocksource
+ * T0_TOP: Timer 0, top                 : Used by DSP
+ * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
+ */
+static struct davinci_timer_info da830_timer_info = {
+        .timers         = da830_timer_instance,
+        .clockevent_id  = T0_BOT,
+        .clocksource_id = T0_BOT,
+};
+
+static struct davinci_soc_info davinci_soc_info_da830 = {
+        .io_desc                = da830_io_desc,
+        .io_desc_num            = ARRAY_SIZE(da830_io_desc),
+        .jtag_id_base           = IO_ADDRESS(DA830_JTAG_ID_REG),
+        .ids                    = da830_ids,
+        .ids_num                = ARRAY_SIZE(da830_ids),
+        .cpu_clks               = da830_clks,
+        .psc_bases              = da830_psc_bases,
+        .psc_bases_num          = ARRAY_SIZE(da830_psc_bases),
+        .pinmux_base            = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120),
+        .pinmux_pins            = da830_pins,
+        .pinmux_pins_num        = ARRAY_SIZE(da830_pins),
+        .intc_base              = (void __iomem *)DA8XX_CP_INTC_VIRT,
+        .intc_type              = DAVINCI_INTC_TYPE_CP_INTC,
+        .intc_irq_prios         = da830_default_priorities,
+        .intc_irq_num           = DA830_N_CP_INTC_IRQ,
+        .timer_info             = &da830_timer_info,
+        .gpio_base              = IO_ADDRESS(DA830_GPIO_BASE),
+        .gpio_num               = 128,
+        .gpio_irq               = IRQ_DA8XX_GPIO0,
+        .serial_dev             = &da8xx_serial_device,
+        .emac_pdata             = &da8xx_emac_pdata,
+};
+
+void __init da830_init(void)
+{
+        davinci_common_init(&davinci_soc_info_da830);
+}
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
new file mode 100644
index 000000000000..c367055ae9b9
--- /dev/null
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -0,0 +1,287 @@
+/*
+ * DA8XX/OMAP L1XX platform device data
+ *
+ * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
+ * Derived from code that was:
+ *      Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/serial_8250.h>
+
+#include <mach/cputype.h>
+#include <mach/common.h>
+#include <mach/time.h>
+#include <mach/da8xx.h>
+
+#include "clock.h"
+
+#define DA8XX_TPCC_BASE                 0x01c00000
+#define DA8XX_TPTC0_BASE                0x01c08000
+#define DA8XX_TPTC1_BASE                0x01c08400
+#define DA8XX_WDOG_BASE                 0x01c21000 /* DA8XX_TIMER64P1_BASE */
+#define DA8XX_I2C0_BASE                 0x01c22000
+#define DA8XX_EMAC_CPPI_PORT_BASE       0x01e20000
+#define DA8XX_EMAC_CPGMACSS_BASE        0x01e22000
+#define DA8XX_EMAC_CPGMAC_BASE          0x01e23000
+#define DA8XX_EMAC_MDIO_BASE            0x01e24000
+#define DA8XX_GPIO_BASE                 0x01e26000
+#define DA8XX_I2C1_BASE                 0x01e28000
+
+#define DA8XX_EMAC_CTRL_REG_OFFSET      0x3000
+#define DA8XX_EMAC_MOD_REG_OFFSET       0x2000
+#define DA8XX_EMAC_RAM_OFFSET           0x0000
+#define DA8XX_MDIO_REG_OFFSET           0x4000
+#define DA8XX_EMAC_CTRL_RAM_SIZE        SZ_8K
+
+static struct plat_serial8250_port da8xx_serial_pdata[] = {
+        {
+                .mapbase        = DA8XX_UART0_BASE,
+                .irq            = IRQ_DA8XX_UARTINT0,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                        UPF_IOREMAP,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        },
+        {
+                .mapbase        = DA8XX_UART1_BASE,
+                .irq            = IRQ_DA8XX_UARTINT1,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                        UPF_IOREMAP,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        },
+        {
+                .mapbase        = DA8XX_UART2_BASE,
+                .irq            = IRQ_DA8XX_UARTINT2,
+                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+                                        UPF_IOREMAP,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+        },
+        {
+                .flags  = 0,
+        },
+};
+
+struct platform_device da8xx_serial_device = {
+        .name   = "serial8250",
+        .id     = PLAT8250_DEV_PLATFORM,
+        .dev    = {
+                .platform_data  = da8xx_serial_pdata,
+        },
+};
+
+static const s8 da8xx_dma_chan_no_event[] = {
+        20, 21,
+        -1
+};
+
+static const s8 da8xx_queue_tc_mapping[][2] = {
+        /* {event queue no, TC no} */
+        {0, 0},
+        {1, 1},
+        {-1, -1}
+};
+
+static const s8 da8xx_queue_priority_mapping[][2] = {
+        /* {event queue no, Priority} */
+        {0, 3},
+        {1, 7},
+        {-1, -1}
+};
+
+static struct edma_soc_info da8xx_edma_info[] = {
+        {
+                .n_channel              = 32,
+                .n_region               = 4,
+                .n_slot                 = 128,
+                .n_tc                   = 2,
+                .n_cc                   = 1,
+                .noevent                = da8xx_dma_chan_no_event,
+                .queue_tc_mapping       = da8xx_queue_tc_mapping,
+                .queue_priority_mapping = da8xx_queue_priority_mapping,
+        },
+};
+
+static struct resource da8xx_edma_resources[] = {
+        {
+                .name   = "edma_cc0",
+                .start  = DA8XX_TPCC_BASE,
+                .end    = DA8XX_TPCC_BASE + SZ_32K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc0",
+                .start  = DA8XX_TPTC0_BASE,
+                .end    = DA8XX_TPTC0_BASE + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma_tc1",
+                .start  = DA8XX_TPTC1_BASE,
+                .end    = DA8XX_TPTC1_BASE + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .name   = "edma0",
+                .start  = IRQ_DA8XX_TCERRINT0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .name   = "edma0_err",
+                .start  = IRQ_DA8XX_CCERRINT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device da8xx_edma_device = {
+        .name           = "edma",
+        .id             = -1,
+        .dev = {
+                .platform_data  = da8xx_edma_info,
+        },
+        .num_resources  = ARRAY_SIZE(da8xx_edma_resources),
+        .resource       = da8xx_edma_resources,
+};
+
+int __init da8xx_register_edma(void)
+{
+        return platform_device_register(&da8xx_edma_device);
+}
+
+static struct resource da8xx_i2c_resources0[] = {
+        {
+                .start  = DA8XX_I2C0_BASE,
+                .end    = DA8XX_I2C0_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_DA8XX_I2CINT0,
+                .end    = IRQ_DA8XX_I2CINT0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device da8xx_i2c_device0 = {
+        .name           = "i2c_davinci",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(da8xx_i2c_resources0),
+        .resource       = da8xx_i2c_resources0,
+};
+
+static struct resource da8xx_i2c_resources1[] = {
+        {
+                .start  = DA8XX_I2C1_BASE,
+                .end    = DA8XX_I2C1_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_DA8XX_I2CINT1,
+                .end    = IRQ_DA8XX_I2CINT1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device da8xx_i2c_device1 = {
+        .name           = "i2c_davinci",
+        .id             = 2,
+        .num_resources  = ARRAY_SIZE(da8xx_i2c_resources1),
+        .resource       = da8xx_i2c_resources1,
+};
+
+int __init da8xx_register_i2c(int instance,
+                struct davinci_i2c_platform_data *pdata)
+{
+        struct platform_device *pdev;
+
+        if (instance == 0)
+                pdev = &da8xx_i2c_device0;
+        else if (instance == 1)
+                pdev = &da8xx_i2c_device1;
+        else
+                return -EINVAL;
+
+        pdev->dev.platform_data = pdata;
+        return platform_device_register(pdev);
+}
+
+static struct resource da8xx_watchdog_resources[] = {
+        {
+                .start  = DA8XX_WDOG_BASE,
+                .end    = DA8XX_WDOG_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+struct platform_device davinci_wdt_device = {
+        .name           = "watchdog",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(da8xx_watchdog_resources),
+        .resource       = da8xx_watchdog_resources,
+};
+
+int __init da8xx_register_watchdog(void)
+{
+        return platform_device_register(&davinci_wdt_device);
+}
+
+static struct resource da8xx_emac_resources[] = {
+        {
+                .start  = DA8XX_EMAC_CPPI_PORT_BASE,
+                .end    = DA8XX_EMAC_CPPI_PORT_BASE + 0x5000 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        {
+                .start  = IRQ_DA8XX_C0_RX_THRESH_PULSE,
+                .end    = IRQ_DA8XX_C0_RX_THRESH_PULSE,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_C0_RX_PULSE,
+                .end    = IRQ_DA8XX_C0_RX_PULSE,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_C0_TX_PULSE,
+                .end    = IRQ_DA8XX_C0_TX_PULSE,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = IRQ_DA8XX_C0_MISC_PULSE,
+                .end    = IRQ_DA8XX_C0_MISC_PULSE,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+struct emac_platform_data da8xx_emac_pdata = {
+        .ctrl_reg_offset        = DA8XX_EMAC_CTRL_REG_OFFSET,
+        .ctrl_mod_reg_offset    = DA8XX_EMAC_MOD_REG_OFFSET,
+        .ctrl_ram_offset        = DA8XX_EMAC_RAM_OFFSET,
+        .mdio_reg_offset        = DA8XX_MDIO_REG_OFFSET,
+        .ctrl_ram_size          = DA8XX_EMAC_CTRL_RAM_SIZE,
+        .version                = EMAC_VERSION_2,
+};
+
+static struct platform_device da8xx_emac_device = {
+        .name           = "davinci_emac",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &da8xx_emac_pdata,
+        },
+        .num_resources  = ARRAY_SIZE(da8xx_emac_resources),
+        .resource       = da8xx_emac_resources,
+};
+
+int __init da8xx_register_emac(void)
+{
+        return platform_device_register(&da8xx_emac_device);
+}
diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index 56b92d49e293..fd41189e5c62 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -31,6 +31,7 @@ struct davinci_id {
 #define DAVINCI_CPU_ID_DM6467           0x64670000
 #define DAVINCI_CPU_ID_DM355            0x03550000
 #define DAVINCI_CPU_ID_DM365            0x03650000
+#define DAVINCI_CPU_ID_DA830            0x08300000
 
 #define IS_DAVINCI_CPU(type, id)                                        \
 static inline int is_davinci_ ##type(void)                              \
@@ -42,6 +43,7 @@ IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446)
 IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467)
 IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355)
 IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
+IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830)
 
 #ifdef CONFIG_ARCH_DAVINCI_DM644x
 #define cpu_is_davinci_dm644x() is_davinci_dm644x()
@@ -67,4 +69,10 @@ IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365)
 #define cpu_is_davinci_dm365() 0
 #endif
 
+#ifdef CONFIG_ARCH_DAVINCI_DA830
+#define cpu_is_davinci_da830() is_davinci_da830()
+#else
+#define cpu_is_davinci_da830() 0
+#endif
+
 #endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
new file mode 100644
index 000000000000..084db271c7c4
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -0,0 +1,69 @@
+/*
+ * Chip specific defines for DA8XX/OMAP L1XX SoC
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2007, 2009 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_DAVINCI_DA8XX_H
+#define __ASM_ARCH_DAVINCI_DA8XX_H
+
+#include <mach/serial.h>
+#include <mach/edma.h>
+#include <mach/i2c.h>
+#include <mach/emac.h>
+
+/*
+ * The cp_intc interrupt controller for the da8xx isn't in the same
+ * chunk of physical memory space as the other registers (like it is
+ * on the davincis) so it needs to be mapped separately.  It will be
+ * mapped early on when the I/O space is mapped and we'll put it just
+ * before the I/O space in the processor's virtual memory space.
+ */
+#define DA8XX_CP_INTC_BASE      0xfffee000
+#define DA8XX_CP_INTC_SIZE      SZ_8K
+#define DA8XX_CP_INTC_VIRT      (IO_VIRT - DA8XX_CP_INTC_SIZE - SZ_4K)
+
+#define DA8XX_BOOT_CFG_BASE     (IO_PHYS + 0x14000)
+
+void __init da830_init(void);
+
+int da8xx_register_edma(void);
+int da8xx_register_i2c(int instance, struct davinci_i2c_platform_data *pdata);
+int da8xx_register_watchdog(void);
+int da8xx_register_emac(void);
+
+extern struct platform_device da8xx_serial_device;
+extern struct emac_platform_data da8xx_emac_pdata;
+
+extern const short da830_emif25_pins[];
+extern const short da830_spi0_pins[];
+extern const short da830_spi1_pins[];
+extern const short da830_mmc_sd_pins[];
+extern const short da830_uart0_pins[];
+extern const short da830_uart1_pins[];
+extern const short da830_uart2_pins[];
+extern const short da830_usb20_pins[];
+extern const short da830_usb11_pins[];
+extern const short da830_uhpi_pins[];
+extern const short da830_cpgmac_pins[];
+extern const short da830_emif3c_pins[];
+extern const short da830_mcasp0_pins[];
+extern const short da830_mcasp1_pins[];
+extern const short da830_mcasp2_pins[];
+extern const short da830_i2c0_pins[];
+extern const short da830_i2c1_pins[];
+extern const short da830_lcdcntl_pins[];
+extern const short da830_pwm_pins[];
+extern const short da830_ecap0_pins[];
+extern const short da830_ecap1_pins[];
+extern const short da830_ecap2_pins[];
+extern const short da830_eqep0_pins[];
+extern const short da830_eqep1_pins[];
+
+int da830_pinmux_setup(const short pins[]);
+
+#endif /* __ASM_ARCH_DAVINCI_DA8XX_H */
diff --git a/arch/arm/mach-davinci/include/mach/edma.h b/arch/arm/mach-davinci/include/mach/edma.h
index ba2ebdd058a0..a85cbedc9b0a 100644
--- a/arch/arm/mach-davinci/include/mach/edma.h
+++ b/arch/arm/mach-davinci/include/mach/edma.h
@@ -139,6 +139,54 @@ struct edmacc_param {
 #define DAVINCI_DMA_PWM1                 53
 #define DAVINCI_DMA_PWM2                 54
 
+/* DA830 specific EDMA3 information */
+#define EDMA_DA830_NUM_DMACH            32
+#define EDMA_DA830_NUM_TCC              32
+#define EDMA_DA830_NUM_PARAMENTRY       128
+#define EDMA_DA830_NUM_EVQUE            2
+#define EDMA_DA830_NUM_TC               2
+#define EDMA_DA830_CHMAP_EXIST          0
+#define EDMA_DA830_NUM_REGIONS          4
+#define DA830_DMACH2EVENT_MAP0          0x000FC03Fu
+#define DA830_DMACH2EVENT_MAP1          0x00000000u
+#define DA830_EDMA_ARM_OWN              0x30FFCCFFu
+
+/* DA830 specific EDMA3 Events Information */
+enum DA830_edma_ch {
+        DA830_DMACH_MCASP0_RX,
+        DA830_DMACH_MCASP0_TX,
+        DA830_DMACH_MCASP1_RX,
+        DA830_DMACH_MCASP1_TX,
+        DA830_DMACH_MCASP2_RX,
+        DA830_DMACH_MCASP2_TX,
+        DA830_DMACH_GPIO_BNK0INT,
+        DA830_DMACH_GPIO_BNK1INT,
+        DA830_DMACH_UART0_RX,
+        DA830_DMACH_UART0_TX,
+        DA830_DMACH_TMR64P0_EVTOUT12,
+        DA830_DMACH_TMR64P0_EVTOUT34,
+        DA830_DMACH_UART1_RX,
+        DA830_DMACH_UART1_TX,
+        DA830_DMACH_SPI0_RX,
+        DA830_DMACH_SPI0_TX,
+        DA830_DMACH_MMCSD_RX,
+        DA830_DMACH_MMCSD_TX,
+        DA830_DMACH_SPI1_RX,
+        DA830_DMACH_SPI1_TX,
+        DA830_DMACH_DMAX_EVTOUT6,
+        DA830_DMACH_DMAX_EVTOUT7,
+        DA830_DMACH_GPIO_BNK2INT,
+        DA830_DMACH_GPIO_BNK3INT,
+        DA830_DMACH_I2C0_RX,
+        DA830_DMACH_I2C0_TX,
+        DA830_DMACH_I2C1_RX,
+        DA830_DMACH_I2C1_TX,
+        DA830_DMACH_GPIO_BNK4INT,
+        DA830_DMACH_GPIO_BNK5INT,
+        DA830_DMACH_UART2_RX,
+        DA830_DMACH_UART2_TX
+};
+
 /*ch_status paramater of callback function possible values*/
 #define DMA_COMPLETE 1
 #define DMA_CC_ERROR 2
diff --git a/arch/arm/mach-davinci/include/mach/irqs.h b/arch/arm/mach-davinci/include/mach/irqs.h
index 0d34f2fb0993..735e378d27ee 100644
--- a/arch/arm/mach-davinci/include/mach/irqs.h
+++ b/arch/arm/mach-davinci/include/mach/irqs.h
@@ -99,9 +99,6 @@
 #define IRQ_EMUINT       63
 
 #define DAVINCI_N_AINTC_IRQ     64
-#define DAVINCI_N_GPIO          104
-
-#define NR_IRQS                 (DAVINCI_N_AINTC_IRQ + DAVINCI_N_GPIO)
 
 #define ARCH_TIMER_IRQ IRQ_TINT1_TINT34
 
@@ -242,4 +239,110 @@
 #define IRQ_DM365_TCERRINT3     62
 #define IRQ_DM365_EMUINT        63
 
+/* DA8XX interrupts */
+#define IRQ_DA8XX_COMMTX                0
+#define IRQ_DA8XX_COMMRX                1
+#define IRQ_DA8XX_NINT                  2
+#define IRQ_DA8XX_EVTOUT0               3
+#define IRQ_DA8XX_EVTOUT1               4
+#define IRQ_DA8XX_EVTOUT2               5
+#define IRQ_DA8XX_EVTOUT3               6
+#define IRQ_DA8XX_EVTOUT4               7
+#define IRQ_DA8XX_EVTOUT5               8
+#define IRQ_DA8XX_EVTOUT6               9
+#define IRQ_DA8XX_EVTOUT7               10
+#define IRQ_DA8XX_CCINT0                11
+#define IRQ_DA8XX_CCERRINT              12
+#define IRQ_DA8XX_TCERRINT0             13
+#define IRQ_DA8XX_AEMIFINT              14
+#define IRQ_DA8XX_I2CINT0               15
+#define IRQ_DA8XX_MMCSDINT0             16
+#define IRQ_DA8XX_MMCSDINT1             17
+#define IRQ_DA8XX_ALLINT0               18
+#define IRQ_DA8XX_RTC                   19
+#define IRQ_DA8XX_SPINT0                20
+#define IRQ_DA8XX_TINT12_0              21
+#define IRQ_DA8XX_TINT34_0              22
+#define IRQ_DA8XX_TINT12_1              23
+#define IRQ_DA8XX_TINT34_1              24
+#define IRQ_DA8XX_UARTINT0              25
+#define IRQ_DA8XX_KEYMGRINT             26
+#define IRQ_DA8XX_SECINT                26
+#define IRQ_DA8XX_SECKEYERR             26
+#define IRQ_DA8XX_CHIPINT0              28
+#define IRQ_DA8XX_CHIPINT1              29
+#define IRQ_DA8XX_CHIPINT2              30
+#define IRQ_DA8XX_CHIPINT3              31
+#define IRQ_DA8XX_TCERRINT1             32
+#define IRQ_DA8XX_C0_RX_THRESH_PULSE    33
+#define IRQ_DA8XX_C0_RX_PULSE           34
+#define IRQ_DA8XX_C0_TX_PULSE           35
+#define IRQ_DA8XX_C0_MISC_PULSE         36
+#define IRQ_DA8XX_C1_RX_THRESH_PULSE    37
+#define IRQ_DA8XX_C1_RX_PULSE           38
+#define IRQ_DA8XX_C1_TX_PULSE           39
+#define IRQ_DA8XX_C1_MISC_PULSE         40
+#define IRQ_DA8XX_MEMERR                41
+#define IRQ_DA8XX_GPIO0                 42
+#define IRQ_DA8XX_GPIO1                 43
+#define IRQ_DA8XX_GPIO2                 44
+#define IRQ_DA8XX_GPIO3                 45
+#define IRQ_DA8XX_GPIO4                 46
+#define IRQ_DA8XX_GPIO5                 47
+#define IRQ_DA8XX_GPIO6                 48
+#define IRQ_DA8XX_GPIO7                 49
+#define IRQ_DA8XX_GPIO8                 50
+#define IRQ_DA8XX_I2CINT1               51
+#define IRQ_DA8XX_LCDINT                52
+#define IRQ_DA8XX_UARTINT1              53
+#define IRQ_DA8XX_MCASPINT              54
+#define IRQ_DA8XX_ALLINT1               55
+#define IRQ_DA8XX_SPINT1                56
+#define IRQ_DA8XX_UHPI_INT1             57
+#define IRQ_DA8XX_USB_INT               58
+#define IRQ_DA8XX_IRQN                  59
+#define IRQ_DA8XX_RWAKEUP               60
+#define IRQ_DA8XX_UARTINT2              61
+#define IRQ_DA8XX_DFTSSINT              62
+#define IRQ_DA8XX_EHRPWM0               63
+#define IRQ_DA8XX_EHRPWM0TZ             64
+#define IRQ_DA8XX_EHRPWM1               65
+#define IRQ_DA8XX_EHRPWM1TZ             66
+#define IRQ_DA8XX_ECAP0                 69
+#define IRQ_DA8XX_ECAP1                 70
+#define IRQ_DA8XX_ECAP2                 71
+#define IRQ_DA8XX_ARMCLKSTOPREQ         90
+
+/* DA830 specific interrupts */
+#define IRQ_DA830_MPUERR                27
+#define IRQ_DA830_IOPUERR               27
+#define IRQ_DA830_BOOTCFGERR            27
+#define IRQ_DA830_EHRPWM2               67
+#define IRQ_DA830_EHRPWM2TZ             68
+#define IRQ_DA830_EQEP0                 72
+#define IRQ_DA830_EQEP1                 73
+#define IRQ_DA830_T12CMPINT0_0          74
+#define IRQ_DA830_T12CMPINT1_0          75
+#define IRQ_DA830_T12CMPINT2_0          76
+#define IRQ_DA830_T12CMPINT3_0          77
+#define IRQ_DA830_T12CMPINT4_0          78
+#define IRQ_DA830_T12CMPINT5_0          79
+#define IRQ_DA830_T12CMPINT6_0          80
+#define IRQ_DA830_T12CMPINT7_0          81
+#define IRQ_DA830_T12CMPINT0_1          82
+#define IRQ_DA830_T12CMPINT1_1          83
+#define IRQ_DA830_T12CMPINT2_1          84
+#define IRQ_DA830_T12CMPINT3_1          85
+#define IRQ_DA830_T12CMPINT4_1          86
+#define IRQ_DA830_T12CMPINT5_1          87
+#define IRQ_DA830_T12CMPINT6_1          88
+#define IRQ_DA830_T12CMPINT7_1          89
+
+#define DA830_N_CP_INTC_IRQ             96
+
+/* da830 currently has the most gpio pins (128) */
+#define DAVINCI_N_GPIO                  128
+/* da830 currently has the most irqs so use DA830_N_CP_INTC_IRQ */
+#define NR_IRQS                         (DA830_N_CP_INTC_IRQ + DAVINCI_N_GPIO)
+
 #endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index c712c7cdf38f..80309aed534a 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -20,9 +20,16 @@
 /**************************************************************************
  * Definitions
  **************************************************************************/
-#define DAVINCI_DDR_BASE    0x80000000
+#define DAVINCI_DDR_BASE        0x80000000
+#define DA8XX_DDR_BASE          0xc0000000
 
+#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx)
+#error Cannot enable DaVinci and DA8XX platforms concurrently
+#elif defined(CONFIG_ARCH_DAVINCI_DA8XX)
+#define PHYS_OFFSET DA8XX_DDR_BASE
+#else
 #define PHYS_OFFSET DAVINCI_DDR_BASE
+#endif
 
 /*
  * Increase size of DMA-consistent memory region
diff --git a/arch/arm/mach-davinci/include/mach/mux.h b/arch/arm/mach-davinci/include/mach/mux.h
index 55765e1fdb78..ae4f6dd3623c 100644
--- a/arch/arm/mach-davinci/include/mach/mux.h
+++ b/arch/arm/mach-davinci/include/mach/mux.h
@@ -242,6 +242,410 @@ enum davinci_dm365_index {
         DM365_EVT26_MMC0_RX,
 };
 
+enum da830_index {
+        DA830_GPIO7_14,
+        DA830_RTCK,
+        DA830_GPIO7_15,
+        DA830_EMU_0,
+        DA830_EMB_SDCKE,
+        DA830_EMB_CLK_GLUE,
+        DA830_EMB_CLK,
+        DA830_NEMB_CS_0,
+        DA830_NEMB_CAS,
+        DA830_NEMB_RAS,
+        DA830_NEMB_WE,
+        DA830_EMB_BA_1,
+        DA830_EMB_BA_0,
+        DA830_EMB_A_0,
+        DA830_EMB_A_1,
+        DA830_EMB_A_2,
+        DA830_EMB_A_3,
+        DA830_EMB_A_4,
+        DA830_EMB_A_5,
+        DA830_GPIO7_0,
+        DA830_GPIO7_1,
+        DA830_GPIO7_2,
+        DA830_GPIO7_3,
+        DA830_GPIO7_4,
+        DA830_GPIO7_5,
+        DA830_GPIO7_6,
+        DA830_GPIO7_7,
+        DA830_EMB_A_6,
+        DA830_EMB_A_7,
+        DA830_EMB_A_8,
+        DA830_EMB_A_9,
+        DA830_EMB_A_10,
+        DA830_EMB_A_11,
+        DA830_EMB_A_12,
+        DA830_EMB_D_31,
+        DA830_GPIO7_8,
+        DA830_GPIO7_9,
+        DA830_GPIO7_10,
+        DA830_GPIO7_11,
+        DA830_GPIO7_12,
+        DA830_GPIO7_13,
+        DA830_GPIO3_13,
+        DA830_EMB_D_30,
+        DA830_EMB_D_29,
+        DA830_EMB_D_28,
+        DA830_EMB_D_27,
+        DA830_EMB_D_26,
+        DA830_EMB_D_25,
+        DA830_EMB_D_24,
+        DA830_EMB_D_23,
+        DA830_EMB_D_22,
+        DA830_EMB_D_21,
+        DA830_EMB_D_20,
+        DA830_EMB_D_19,
+        DA830_EMB_D_18,
+        DA830_EMB_D_17,
+        DA830_EMB_D_16,
+        DA830_NEMB_WE_DQM_3,
+        DA830_NEMB_WE_DQM_2,
+        DA830_EMB_D_0,
+        DA830_EMB_D_1,
+        DA830_EMB_D_2,
+        DA830_EMB_D_3,
+        DA830_EMB_D_4,
+        DA830_EMB_D_5,
+        DA830_EMB_D_6,
+        DA830_GPIO6_0,
+        DA830_GPIO6_1,
+        DA830_GPIO6_2,
+        DA830_GPIO6_3,
+        DA830_GPIO6_4,
+        DA830_GPIO6_5,
+        DA830_GPIO6_6,
+        DA830_EMB_D_7,
+        DA830_EMB_D_8,
+        DA830_EMB_D_9,
+        DA830_EMB_D_10,
+        DA830_EMB_D_11,
+        DA830_EMB_D_12,
+        DA830_EMB_D_13,
+        DA830_EMB_D_14,
+        DA830_GPIO6_7,
+        DA830_GPIO6_8,
+        DA830_GPIO6_9,
+        DA830_GPIO6_10,
+        DA830_GPIO6_11,
+        DA830_GPIO6_12,
+        DA830_GPIO6_13,
+        DA830_GPIO6_14,
+        DA830_EMB_D_15,
+        DA830_NEMB_WE_DQM_1,
+        DA830_NEMB_WE_DQM_0,
+        DA830_SPI0_SOMI_0,
+        DA830_SPI0_SIMO_0,
+        DA830_SPI0_CLK,
+        DA830_NSPI0_ENA,
+        DA830_NSPI0_SCS_0,
+        DA830_EQEP0I,
+        DA830_EQEP0S,
+        DA830_EQEP1I,
+        DA830_NUART0_CTS,
+        DA830_NUART0_RTS,
+        DA830_EQEP0A,
+        DA830_EQEP0B,
+        DA830_GPIO6_15,
+        DA830_GPIO5_14,
+        DA830_GPIO5_15,
+        DA830_GPIO5_0,
+        DA830_GPIO5_1,
+        DA830_GPIO5_2,
+        DA830_GPIO5_3,
+        DA830_GPIO5_4,
+        DA830_SPI1_SOMI_0,
+        DA830_SPI1_SIMO_0,
+        DA830_SPI1_CLK,
+        DA830_UART0_RXD,
+        DA830_UART0_TXD,
+        DA830_AXR1_10,
+        DA830_AXR1_11,
+        DA830_NSPI1_ENA,
+        DA830_I2C1_SCL,
+        DA830_I2C1_SDA,
+        DA830_EQEP1S,
+        DA830_I2C0_SDA,
+        DA830_I2C0_SCL,
+        DA830_UART2_RXD,
+        DA830_TM64P0_IN12,
+        DA830_TM64P0_OUT12,
+        DA830_GPIO5_5,
+        DA830_GPIO5_6,
+        DA830_GPIO5_7,
+        DA830_GPIO5_8,
+        DA830_GPIO5_9,
+        DA830_GPIO5_10,
+        DA830_GPIO5_11,
+        DA830_GPIO5_12,
+        DA830_NSPI1_SCS_0,
+        DA830_USB0_DRVVBUS,
+        DA830_AHCLKX0,
+        DA830_ACLKX0,
+        DA830_AFSX0,
+        DA830_AHCLKR0,
+        DA830_ACLKR0,
+        DA830_AFSR0,
+        DA830_UART2_TXD,
+        DA830_AHCLKX2,
+        DA830_ECAP0_APWM0,
+        DA830_RMII_MHZ_50_CLK,
+        DA830_ECAP1_APWM1,
+        DA830_USB_REFCLKIN,
+        DA830_GPIO5_13,
+        DA830_GPIO4_15,
+        DA830_GPIO2_11,
+        DA830_GPIO2_12,
+        DA830_GPIO2_13,
+        DA830_GPIO2_14,
+        DA830_GPIO2_15,
+        DA830_GPIO3_12,
+        DA830_AMUTE0,
+        DA830_AXR0_0,
+        DA830_AXR0_1,
+        DA830_AXR0_2,
+        DA830_AXR0_3,
+        DA830_AXR0_4,
+        DA830_AXR0_5,
+        DA830_AXR0_6,
+        DA830_RMII_TXD_0,
+        DA830_RMII_TXD_1,
+        DA830_RMII_TXEN,
+        DA830_RMII_CRS_DV,
+        DA830_RMII_RXD_0,
+        DA830_RMII_RXD_1,
+        DA830_RMII_RXER,
+        DA830_AFSR2,
+        DA830_ACLKX2,
+        DA830_AXR2_3,
+        DA830_AXR2_2,
+        DA830_AXR2_1,
+        DA830_AFSX2,
+        DA830_ACLKR2,
+        DA830_NRESETOUT,
+        DA830_GPIO3_0,
+        DA830_GPIO3_1,
+        DA830_GPIO3_2,
+        DA830_GPIO3_3,
+        DA830_GPIO3_4,
+        DA830_GPIO3_5,
+        DA830_GPIO3_6,
+        DA830_AXR0_7,
+        DA830_AXR0_8,
+        DA830_UART1_RXD,
+        DA830_UART1_TXD,
+        DA830_AXR0_11,
+        DA830_AHCLKX1,
+        DA830_ACLKX1,
+        DA830_AFSX1,
+        DA830_MDIO_CLK,
+        DA830_MDIO_D,
+        DA830_AXR0_9,
+        DA830_AXR0_10,
+        DA830_EPWM0B,
+        DA830_EPWM0A,
+        DA830_EPWMSYNCI,
+        DA830_AXR2_0,
+        DA830_EPWMSYNC0,
+        DA830_GPIO3_7,
+        DA830_GPIO3_8,
+        DA830_GPIO3_9,
+        DA830_GPIO3_10,
+        DA830_GPIO3_11,
+        DA830_GPIO3_14,
+        DA830_GPIO3_15,
+        DA830_GPIO4_10,
+        DA830_AHCLKR1,
+        DA830_ACLKR1,
+        DA830_AFSR1,
+        DA830_AMUTE1,
+        DA830_AXR1_0,
+        DA830_AXR1_1,
+        DA830_AXR1_2,
+        DA830_AXR1_3,
+        DA830_ECAP2_APWM2,
+        DA830_EHRPWMGLUETZ,
+        DA830_EQEP1A,
+        DA830_GPIO4_11,
+        DA830_GPIO4_12,
+        DA830_GPIO4_13,
+        DA830_GPIO4_14,
+        DA830_GPIO4_0,
+        DA830_GPIO4_1,
+        DA830_GPIO4_2,
+        DA830_GPIO4_3,
+        DA830_AXR1_4,
+        DA830_AXR1_5,
+        DA830_AXR1_6,
+        DA830_AXR1_7,
+        DA830_AXR1_8,
+        DA830_AXR1_9,
+        DA830_EMA_D_0,
+        DA830_EMA_D_1,
+        DA830_EQEP1B,
+        DA830_EPWM2B,
+        DA830_EPWM2A,
+        DA830_EPWM1B,
+        DA830_EPWM1A,
+        DA830_MMCSD_DAT_0,
+        DA830_MMCSD_DAT_1,
+        DA830_UHPI_HD_0,
+        DA830_UHPI_HD_1,
+        DA830_GPIO4_4,
+        DA830_GPIO4_5,
+        DA830_GPIO4_6,
+        DA830_GPIO4_7,
+        DA830_GPIO4_8,
+        DA830_GPIO4_9,
+        DA830_GPIO0_0,
+        DA830_GPIO0_1,
+        DA830_EMA_D_2,
+        DA830_EMA_D_3,
+        DA830_EMA_D_4,
+        DA830_EMA_D_5,
+        DA830_EMA_D_6,
+        DA830_EMA_D_7,
+        DA830_EMA_D_8,
+        DA830_EMA_D_9,
+        DA830_MMCSD_DAT_2,
+        DA830_MMCSD_DAT_3,
+        DA830_MMCSD_DAT_4,
+        DA830_MMCSD_DAT_5,
+        DA830_MMCSD_DAT_6,
+        DA830_MMCSD_DAT_7,
+        DA830_UHPI_HD_8,
+        DA830_UHPI_HD_9,
+        DA830_UHPI_HD_2,
+        DA830_UHPI_HD_3,
+        DA830_UHPI_HD_4,
+        DA830_UHPI_HD_5,
+        DA830_UHPI_HD_6,
+        DA830_UHPI_HD_7,
+        DA830_LCD_D_8,
+        DA830_LCD_D_9,
+        DA830_GPIO0_2,
+        DA830_GPIO0_3,
+        DA830_GPIO0_4,
+        DA830_GPIO0_5,
+        DA830_GPIO0_6,
+        DA830_GPIO0_7,
+        DA830_GPIO0_8,
+        DA830_GPIO0_9,
+        DA830_EMA_D_10,
+        DA830_EMA_D_11,
+        DA830_EMA_D_12,
+        DA830_EMA_D_13,
+        DA830_EMA_D_14,
+        DA830_EMA_D_15,
+        DA830_EMA_A_0,
+        DA830_EMA_A_1,
+        DA830_UHPI_HD_10,
+        DA830_UHPI_HD_11,
+        DA830_UHPI_HD_12,
+        DA830_UHPI_HD_13,
+        DA830_UHPI_HD_14,
+        DA830_UHPI_HD_15,
+        DA830_LCD_D_7,
+        DA830_MMCSD_CLK,
+        DA830_LCD_D_10,
+        DA830_LCD_D_11,
+        DA830_LCD_D_12,
+        DA830_LCD_D_13,
+        DA830_LCD_D_14,
+        DA830_LCD_D_15,
+        DA830_UHPI_HCNTL0,
+        DA830_GPIO0_10,
+        DA830_GPIO0_11,
+        DA830_GPIO0_12,
+        DA830_GPIO0_13,
+        DA830_GPIO0_14,
+        DA830_GPIO0_15,
+        DA830_GPIO1_0,
+        DA830_GPIO1_1,
+        DA830_EMA_A_2,
+        DA830_EMA_A_3,
+        DA830_EMA_A_4,
+        DA830_EMA_A_5,
+        DA830_EMA_A_6,
+        DA830_EMA_A_7,
+        DA830_EMA_A_8,
+        DA830_EMA_A_9,
+        DA830_MMCSD_CMD,
+        DA830_LCD_D_6,
+        DA830_LCD_D_3,
+        DA830_LCD_D_2,
+        DA830_LCD_D_1,
+        DA830_LCD_D_0,
+        DA830_LCD_PCLK,
+        DA830_LCD_HSYNC,
+        DA830_UHPI_HCNTL1,
+        DA830_GPIO1_2,
+        DA830_GPIO1_3,
+        DA830_GPIO1_4,
+        DA830_GPIO1_5,
+        DA830_GPIO1_6,
+        DA830_GPIO1_7,
+        DA830_GPIO1_8,
+        DA830_GPIO1_9,
+        DA830_EMA_A_10,
+        DA830_EMA_A_11,
+        DA830_EMA_A_12,
+        DA830_EMA_BA_1,
+        DA830_EMA_BA_0,
+        DA830_EMA_CLK,
+        DA830_EMA_SDCKE,
+        DA830_NEMA_CAS,
+        DA830_LCD_VSYNC,
+        DA830_NLCD_AC_ENB_CS,
+        DA830_LCD_MCLK,
+        DA830_LCD_D_5,
+        DA830_LCD_D_4,
+        DA830_OBSCLK,
+        DA830_NEMA_CS_4,
+        DA830_UHPI_HHWIL,
+        DA830_AHCLKR2,
+        DA830_GPIO1_10,
+        DA830_GPIO1_11,
+        DA830_GPIO1_12,
+        DA830_GPIO1_13,
+        DA830_GPIO1_14,
+        DA830_GPIO1_15,
+        DA830_GPIO2_0,
+        DA830_GPIO2_1,
+        DA830_NEMA_RAS,
+        DA830_NEMA_WE,
+        DA830_NEMA_CS_0,
+        DA830_NEMA_CS_2,
+        DA830_NEMA_CS_3,
+        DA830_NEMA_OE,
+        DA830_NEMA_WE_DQM_1,
+        DA830_NEMA_WE_DQM_0,
+        DA830_NEMA_CS_5,
+        DA830_UHPI_HRNW,
+        DA830_NUHPI_HAS,
+        DA830_NUHPI_HCS,
+        DA830_NUHPI_HDS1,
+        DA830_NUHPI_HDS2,
+        DA830_NUHPI_HINT,
+        DA830_AXR0_12,
+        DA830_AMUTE2,
+        DA830_AXR0_13,
+        DA830_AXR0_14,
+        DA830_AXR0_15,
+        DA830_GPIO2_2,
+        DA830_GPIO2_3,
+        DA830_GPIO2_4,
+        DA830_GPIO2_5,
+        DA830_GPIO2_6,
+        DA830_GPIO2_7,
+        DA830_GPIO2_8,
+        DA830_GPIO2_9,
+        DA830_EMA_WAIT_0,
+        DA830_NUHPI_HRDY,
+        DA830_GPIO2_10,
+};
+
 #ifdef CONFIG_DAVINCI_MUX
 /* setup pin muxing */
 extern int davinci_cfg_reg(unsigned long reg_cfg);
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index 2bb414b14297..6b9621d88284 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -136,6 +136,47 @@
 #define DM646X_LPSC_TIMER1         35
 #define DM646X_LPSC_ARM_INTC       45
 
+/* PSC0 defines */
+#define DA8XX_LPSC0_TPCC                0
+#define DA8XX_LPSC0_TPTC0               1
+#define DA8XX_LPSC0_TPTC1               2
+#define DA8XX_LPSC0_EMIF25              3
+#define DA8XX_LPSC0_SPI0                4
+#define DA8XX_LPSC0_MMC_SD              5
+#define DA8XX_LPSC0_AINTC               6
+#define DA8XX_LPSC0_ARM_RAM_ROM         7
+#define DA8XX_LPSC0_SECU_MGR            8
+#define DA8XX_LPSC0_UART0               9
+#define DA8XX_LPSC0_SCR0_SS             10
+#define DA8XX_LPSC0_SCR1_SS             11
+#define DA8XX_LPSC0_SCR2_SS             12
+#define DA8XX_LPSC0_DMAX                13
+#define DA8XX_LPSC0_ARM                 14
+#define DA8XX_LPSC0_GEM                 15
+
+/* PSC1 defines */
+#define DA8XX_LPSC1_USB20               1
+#define DA8XX_LPSC1_USB11               2
+#define DA8XX_LPSC1_GPIO                3
+#define DA8XX_LPSC1_UHPI                4
+#define DA8XX_LPSC1_CPGMAC              5
+#define DA8XX_LPSC1_EMIF3C              6
+#define DA8XX_LPSC1_McASP0              7
+#define DA830_LPSC1_McASP1              8
+#define DA830_LPSC1_McASP2              9
+#define DA8XX_LPSC1_SPI1                10
+#define DA8XX_LPSC1_I2C                 11
+#define DA8XX_LPSC1_UART1               12
+#define DA8XX_LPSC1_UART2               13
+#define DA8XX_LPSC1_LCDC                16
+#define DA8XX_LPSC1_PWM                 17
+#define DA8XX_LPSC1_ECAP                20
+#define DA830_LPSC1_EQEP                21
+#define DA8XX_LPSC1_SCR_P0_SS           24
+#define DA8XX_LPSC1_SCR_P1_SS           25
+#define DA8XX_LPSC1_CR_P3_SS            26
+#define DA8XX_LPSC1_L3_CBA_RAM          31
+
 extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
 extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
                 unsigned int id, char enable);
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 794fa5cf93c1..57e68e610ee9 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -18,6 +18,10 @@
 #define DAVINCI_UART1_BASE      (IO_PHYS + 0x20400)
 #define DAVINCI_UART2_BASE      (IO_PHYS + 0x20800)
 
+#define DA8XX_UART0_BASE        (IO_PHYS + 0x042000)
+#define DA8XX_UART1_BASE        (IO_PHYS + 0x10c000)
+#define DA8XX_UART2_BASE        (IO_PHYS + 0x10d000)
+
 /* DaVinci UART register offsets */
 #define UART_DAVINCI_PWREMU             0x0c
 #define UART_DM646X_SCR                 0x10