diff options
-rw-r--r-- | drivers/net/tg3.c | 20 | ||||
-rw-r--r-- | drivers/net/tg3.h | 3 |
2 files changed, 23 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index a43ef2b3a530..003ab53cf613 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -2149,6 +2149,26 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) | |||
2149 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); | 2149 | tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); |
2150 | udelay(40); | 2150 | udelay(40); |
2151 | return; | 2151 | return; |
2152 | } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { | ||
2153 | u32 phytest; | ||
2154 | if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { | ||
2155 | u32 phy; | ||
2156 | |||
2157 | tg3_writephy(tp, MII_ADVERTISE, 0); | ||
2158 | tg3_writephy(tp, MII_BMCR, | ||
2159 | BMCR_ANENABLE | BMCR_ANRESTART); | ||
2160 | |||
2161 | tg3_writephy(tp, MII_TG3_FET_TEST, | ||
2162 | phytest | MII_TG3_FET_SHADOW_EN); | ||
2163 | if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { | ||
2164 | phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; | ||
2165 | tg3_writephy(tp, | ||
2166 | MII_TG3_FET_SHDW_AUXMODE4, | ||
2167 | phy); | ||
2168 | } | ||
2169 | tg3_writephy(tp, MII_TG3_FET_TEST, phytest); | ||
2170 | } | ||
2171 | return; | ||
2152 | } else if (do_low_power) { | 2172 | } else if (do_low_power) { |
2153 | tg3_writephy(tp, MII_TG3_EXT_CTRL, | 2173 | tg3_writephy(tp, MII_TG3_EXT_CTRL, |
2154 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); | 2174 | MII_TG3_EXT_CTRL_FORCE_LED_OFF); |
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 68431da5aad3..9999345a11a4 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -2080,6 +2080,9 @@ | |||
2080 | #define MII_TG3_FET_SHDW_MISCCTRL 0x10 | 2080 | #define MII_TG3_FET_SHDW_MISCCTRL 0x10 |
2081 | #define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000 | 2081 | #define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000 |
2082 | 2082 | ||
2083 | #define MII_TG3_FET_SHDW_AUXMODE4 0x1a | ||
2084 | #define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008 | ||
2085 | |||
2083 | #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b | 2086 | #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b |
2084 | #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020 | 2087 | #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020 |
2085 | 2088 | ||