aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--arch/arm/mm/cache-v4wb.S26
-rw-r--r--arch/arm/mm/proc-sa110.S25
-rw-r--r--arch/arm/mm/proc-sa1100.S37
3 files changed, 30 insertions, 58 deletions
diff --git a/arch/arm/mm/cache-v4wb.S b/arch/arm/mm/cache-v4wb.S
index 5c4055b62d97..54e3c5bb5186 100644
--- a/arch/arm/mm/cache-v4wb.S
+++ b/arch/arm/mm/cache-v4wb.S
@@ -10,7 +10,7 @@
10#include <linux/config.h> 10#include <linux/config.h>
11#include <linux/linkage.h> 11#include <linux/linkage.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <asm/hardware.h> 13#include <asm/memory.h>
14#include <asm/page.h> 14#include <asm/page.h>
15#include "proc-macros.S" 15#include "proc-macros.S"
16 16
@@ -46,6 +46,11 @@
46 */ 46 */
47#define CACHE_DLIMIT (CACHE_DSIZE * 4) 47#define CACHE_DLIMIT (CACHE_DSIZE * 4)
48 48
49 .data
50flush_base:
51 .long FLUSH_BASE
52 .text
53
49/* 54/*
50 * flush_user_cache_all() 55 * flush_user_cache_all()
51 * 56 *
@@ -63,11 +68,21 @@ ENTRY(v4wb_flush_kern_cache_all)
63 mov ip, #0 68 mov ip, #0
64 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 69 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
65__flush_whole_cache: 70__flush_whole_cache:
66 mov r0, #FLUSH_BASE 71 ldr r3, =flush_base
67 add r1, r0, #CACHE_DSIZE 72 ldr r1, [r3, #0]
681: ldr r2, [r0], #32 73 eor r1, r1, #CACHE_DSIZE
69 cmp r0, r1 74 str r1, [r3, #0]
75 add r2, r1, #CACHE_DSIZE
761: ldr r3, [r1], #32
77 cmp r1, r2
78 blo 1b
79#ifdef FLUSH_BASE_MINICACHE
80 add r2, r2, #FLUSH_BASE_MINICACHE - FLUSH_BASE
81 sub r1, r2, #512 @ only 512 bytes
821: ldr r3, [r1], #32
83 cmp r1, r2
70 blo 1b 84 blo 1b
85#endif
71 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 86 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
72 mov pc, lr 87 mov pc, lr
73 88
@@ -82,6 +97,7 @@ __flush_whole_cache:
82 * - flags - vma_area_struct flags describing address space 97 * - flags - vma_area_struct flags describing address space
83 */ 98 */
84ENTRY(v4wb_flush_user_cache_range) 99ENTRY(v4wb_flush_user_cache_range)
100 mov ip, #0
85 sub r3, r1, r0 @ calculate total size 101 sub r3, r1, r0 @ calculate total size
86 tst r2, #VM_EXEC @ executable region? 102 tst r2, #VM_EXEC @ executable region?
87 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 103 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index c916a6cae404..a2dd5ae1077d 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -26,22 +26,7 @@
26 * the cache line size of the I and D cache 26 * the cache line size of the I and D cache
27 */ 27 */
28#define DCACHELINESIZE 32 28#define DCACHELINESIZE 32
29#define FLUSH_OFFSET 32768
30 29
31 .macro flush_110_dcache rd, ra, re
32 ldr \rd, =flush_base
33 ldr \ra, [\rd]
34 eor \ra, \ra, #FLUSH_OFFSET
35 str \ra, [\rd]
36 add \re, \ra, #16384 @ only necessary for 16k
371001: ldr \rd, [\ra], #DCACHELINESIZE
38 teq \re, \ra
39 bne 1001b
40 .endm
41
42 .data
43flush_base:
44 .long FLUSH_BASE
45 .text 30 .text
46 31
47/* 32/*
@@ -145,13 +130,11 @@ ENTRY(cpu_sa110_dcache_clean_area)
145 */ 130 */
146 .align 5 131 .align 5
147ENTRY(cpu_sa110_switch_mm) 132ENTRY(cpu_sa110_switch_mm)
148 flush_110_dcache r3, ip, r1 133 str lr, [sp, #-4]!
149 mov r1, #0 134 bl v4wb_flush_kern_cache_all @ clears IP
150 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
151 mcr p15, 0, r1, c7, c10, 4 @ drain WB
152 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 135 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
153 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 136 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
154 mov pc, lr 137 ldr pc, [sp], #4
155 138
156/* 139/*
157 * cpu_sa110_set_pte(ptep, pte) 140 * cpu_sa110_set_pte(ptep, pte)
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 41f21f2dd8ff..777ad99c1439 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -30,30 +30,6 @@
30 * the cache line size of the I and D cache 30 * the cache line size of the I and D cache
31 */ 31 */
32#define DCACHELINESIZE 32 32#define DCACHELINESIZE 32
33#define FLUSH_OFFSET 32768
34
35 .macro flush_1100_dcache rd, ra, re
36 ldr \rd, =flush_base
37 ldr \ra, [\rd]
38 eor \ra, \ra, #FLUSH_OFFSET
39 str \ra, [\rd]
40 add \re, \ra, #8192 @ only necessary for 8k
411001: ldr \rd, [\ra], #DCACHELINESIZE
42 teq \re, \ra
43 bne 1001b
44#ifdef FLUSH_BASE_MINICACHE
45 add \ra, \ra, #FLUSH_BASE_MINICACHE - FLUSH_BASE
46 add \re, \ra, #512 @ only 512 bytes
471002: ldr \rd, [\ra], #DCACHELINESIZE
48 teq \re, \ra
49 bne 1002b
50#endif
51 .endm
52
53 .data
54flush_base:
55 .long FLUSH_BASE
56 .text
57 33
58 __INIT 34 __INIT
59 35
@@ -79,9 +55,8 @@ ENTRY(cpu_sa1100_proc_fin)
79 stmfd sp!, {lr} 55 stmfd sp!, {lr}
80 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 56 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
81 msr cpsr_c, ip 57 msr cpsr_c, ip
82 flush_1100_dcache r0, r1, r2 @ clean caches 58 bl v4wb_flush_kern_cache_all
83 mov r0, #0 59 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
84 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
85 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 60 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
86 bic r0, r0, #0x1000 @ ...i............ 61 bic r0, r0, #0x1000 @ ...i............
87 bic r0, r0, #0x000e @ ............wca. 62 bic r0, r0, #0x000e @ ............wca.
@@ -167,14 +142,12 @@ ENTRY(cpu_sa1100_dcache_clean_area)
167 */ 142 */
168 .align 5 143 .align 5
169ENTRY(cpu_sa1100_switch_mm) 144ENTRY(cpu_sa1100_switch_mm)
170 flush_1100_dcache r3, ip, r1 145 str lr, [sp, #-4]!
171 mov ip, #0 146 bl v4wb_flush_kern_cache_all @ clears IP
172 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
173 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 147 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
174 mcr p15, 0, ip, c7, c10, 4 @ drain WB
175 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 148 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
176 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 149 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
177 mov pc, lr 150 ldr pc, [sp], #4
178 151
179/* 152/*
180 * cpu_sa1100_set_pte(ptep, pte) 153 * cpu_sa1100_set_pte(ptep, pte)